Add support for the i.MX28 EVK

This patch was originally put together in January 2011 by Roshni.

824 files changed, 642442 insertions, 3055 deletions

diff --git a/drivers/Makefile b/drivers/Makefile
index bc4205d2fc3c..4a9a1c55b598 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_INPUT)		+= input/
 obj-$(CONFIG_I2O)		+= message/
 obj-$(CONFIG_RTC_LIB)		+= rtc/
 obj-y				+= i2c/ media/
+obj-$(CONFIG_I2C_SLAVE) += i2c-slave/
 obj-$(CONFIG_PPS)		+= pps/
 obj-$(CONFIG_W1)		+= w1/
 obj-$(CONFIG_POWER_SUPPLY)	+= power/
@@ -90,6 +91,7 @@ obj-y				+= lguest/
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq/
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle/
 obj-y				+= idle/
+obj-$(CONFIG_ARCH_MXC)		+= mxc/
 obj-$(CONFIG_MMC)		+= mmc/
 obj-$(CONFIG_MEMSTICK)		+= memstick/
 obj-$(CONFIG_NEW_LEDS)		+= leds/
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index b17c57f85032..f484492afea4 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -55,6 +55,14 @@ config SATA_AHCI
 
 	  If unsure, say N.
 
+config SATA_AHCI_PLATFORM
+	tristate "Platform AHCI SATA support"
+	help
+	  This option enables support for Platform AHCI Serial ATA
+	  controllers.
+
+	  If unsure, say N.
+
 config SATA_SIL24
 	tristate "Silicon Image 3124/3132 SATA support"
 	depends on PCI
@@ -751,5 +759,14 @@ config PATA_BF54X
 
 	  If unsure, say N.
 
+config PATA_FSL
+       tristate "Freescale on-chip PATA support"
+       depends on (ARCH_MX5 || ARCH_MX37 || ARCH_MX35 || ARCH_MX3 || ARCH_MX27)
+       help
+         On Freescale processors, say Y here if you wish to use the on-chip
+         ATA interface.
+         If you are unsure, say N to this.
+
 endif # ATA_SFF
+
 endif # ATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 38906f9bbb4e..69bcefa0df6b 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -1,7 +1,8 @@
 
 obj-$(CONFIG_ATA)		+= libata.o
 
-obj-$(CONFIG_SATA_AHCI)		+= ahci.o
+obj-$(CONFIG_SATA_AHCI)		+= ahci.o libahci.o
+obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
 obj-$(CONFIG_SATA_SVW)		+= sata_svw.o
 obj-$(CONFIG_ATA_PIIX)		+= ata_piix.o
 obj-$(CONFIG_SATA_PROMISE)	+= sata_promise.o
@@ -75,6 +76,7 @@ obj-$(CONFIG_PATA_PLATFORM)	+= pata_platform.o
 obj-$(CONFIG_PATA_AT91)	+= pata_at91.o
 obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_ICSIDE)	+= pata_icside.o
+obj-$(CONFIG_PATA_FSL)		+= pata_fsl.o
 # Should be last but two libata driver
 obj-$(CONFIG_PATA_ACPI)		+= pata_acpi.o
 # Should be last but one libata driver
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index fe3eba5d6b3e..edc9b0ec9f39 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -45,64 +45,13 @@
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
+#include "ahci.h"
 
 #define DRV_NAME	"ahci"
 #define DRV_VERSION	"3.0"
 
-/* Enclosure Management Control */
-#define EM_CTRL_MSG_TYPE              0x000f0000
-
-/* Enclosure Management LED Message Type */
-#define EM_MSG_LED_HBA_PORT           0x0000000f
-#define EM_MSG_LED_PMP_SLOT           0x0000ff00
-#define EM_MSG_LED_VALUE              0xffff0000
-#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
-#define EM_MSG_LED_VALUE_OFF          0xfff80000
-#define EM_MSG_LED_VALUE_ON           0x00010000
-
-static int ahci_skip_host_reset;
-static int ahci_ignore_sss;
-
-module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
-MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
-
-module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
-MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
-
-static int ahci_enable_alpm(struct ata_port *ap,
-		enum link_pm policy);
-static void ahci_disable_alpm(struct ata_port *ap);
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-			      size_t size);
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-					ssize_t size);
-
 enum {
 	AHCI_PCI_BAR		= 5,
-	AHCI_MAX_PORTS		= 32,
-	AHCI_MAX_SG		= 168, /* hardware max is 64K */
-	AHCI_DMA_BOUNDARY	= 0xffffffff,
-	AHCI_MAX_CMDS		= 32,
-	AHCI_CMD_SZ		= 32,
-	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
-	AHCI_RX_FIS_SZ		= 256,
-	AHCI_CMD_TBL_CDB	= 0x40,
-	AHCI_CMD_TBL_HDR_SZ	= 0x80,
-	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
-	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
-	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
-				  AHCI_RX_FIS_SZ,
-	AHCI_IRQ_ON_SG		= (1 << 31),
-	AHCI_CMD_ATAPI		= (1 << 5),
-	AHCI_CMD_WRITE		= (1 << 6),
-	AHCI_CMD_PREFETCH	= (1 << 7),
-	AHCI_CMD_RESET		= (1 << 8),
-	AHCI_CMD_CLR_BUSY	= (1 << 10),
-
-	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
-	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
-	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
 
 	board_ahci		= 0,
 	board_ahci_vt8251	= 1,
@@ -113,280 +62,20 @@ enum {
 	board_ahci_mcp65	= 6,
 	board_ahci_nopmp	= 7,
 	board_ahci_yesncq	= 8,
-
-	/* global controller registers */
-	HOST_CAP		= 0x00, /* host capabilities */
-	HOST_CTL		= 0x04, /* global host control */
-	HOST_IRQ_STAT		= 0x08, /* interrupt status */
-	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
-	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
-	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
-	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
-
-	/* HOST_CTL bits */
-	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
-	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
-	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
-
-	/* HOST_CAP bits */
-	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
-	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
-	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
-	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
-	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
-	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
-	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
-	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
-	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
-
-	/* registers for each SATA port */
-	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
-	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
-	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
-	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
-	PORT_IRQ_STAT		= 0x10, /* interrupt status */
-	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
-	PORT_CMD		= 0x18, /* port command */
-	PORT_TFDATA		= 0x20,	/* taskfile data */
-	PORT_SIG		= 0x24,	/* device TF signature */
-	PORT_CMD_ISSUE		= 0x38, /* command issue */
-	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
-	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
-	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
-	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
-	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
-
-	/* PORT_IRQ_{STAT,MASK} bits */
-	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
-	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
-	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
-	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
-	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
-	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
-	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
-	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
-
-	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
-	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
-	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
-	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
-	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
-	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
-	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
-	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
-	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
-
-	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
-				  PORT_IRQ_IF_ERR |
-				  PORT_IRQ_CONNECT |
-				  PORT_IRQ_PHYRDY |
-				  PORT_IRQ_UNK_FIS |
-				  PORT_IRQ_BAD_PMP,
-	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
-				  PORT_IRQ_TF_ERR |
-				  PORT_IRQ_HBUS_DATA_ERR,
-	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
-				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
-				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
-
-	/* PORT_CMD bits */
-	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
-	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
-	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
-	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
-	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
-	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
-	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
-	PORT_CMD_CLO		= (1 << 3), /* Command list override */
-	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
-	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
-	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
-
-	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
-	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
-	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
-	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
-
-	/* hpriv->flags bits */
-	AHCI_HFLAG_NO_NCQ		= (1 << 0),
-	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
-	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
-	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
-	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
-	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
-	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
-	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
-	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
-	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
-	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
-	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
-							link offline */
-
-	/* ap->flags bits */
-
-	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
-					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
-					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
-					  ATA_FLAG_IPM,
-
-	ICH_MAP				= 0x90, /* ICH MAP register */
-
-	/* em constants */
-	EM_MAX_SLOTS			= 8,
-	EM_MAX_RETRY			= 5,
-
-	/* em_ctl bits */
-	EM_CTL_RST			= (1 << 9), /* Reset */
-	EM_CTL_TM			= (1 << 8), /* Transmit Message */
-	EM_CTL_ALHD			= (1 << 26), /* Activity LED */
-};
-
-struct ahci_cmd_hdr {
-	__le32			opts;
-	__le32			status;
-	__le32			tbl_addr;
-	__le32			tbl_addr_hi;
-	__le32			reserved[4];
-};
-
-struct ahci_sg {
-	__le32			addr;
-	__le32			addr_hi;
-	__le32			reserved;
-	__le32			flags_size;
+	board_ahci_nosntf	= 9,
 };
 
-struct ahci_em_priv {
-	enum sw_activity blink_policy;
-	struct timer_list timer;
-	unsigned long saved_activity;
-	unsigned long activity;
-	unsigned long led_state;
-};
-
-struct ahci_host_priv {
-	unsigned int		flags;		/* AHCI_HFLAG_* */
-	u32			cap;		/* cap to use */
-	u32			port_map;	/* port map to use */
-	u32			saved_cap;	/* saved initial cap */
-	u32			saved_port_map;	/* saved initial port_map */
-	u32 			em_loc; /* enclosure management location */
-};
-
-struct ahci_port_priv {
-	struct ata_link		*active_link;
-	struct ahci_cmd_hdr	*cmd_slot;
-	dma_addr_t		cmd_slot_dma;
-	void			*cmd_tbl;
-	dma_addr_t		cmd_tbl_dma;
-	void			*rx_fis;
-	dma_addr_t		rx_fis_dma;
-	/* for NCQ spurious interrupt analysis */
-	unsigned int		ncq_saw_d2h:1;
-	unsigned int		ncq_saw_dmas:1;
-	unsigned int		ncq_saw_sdb:1;
-	u32 			intr_mask;	/* interrupts to enable */
-	/* enclosure management info per PM slot */
-	struct ahci_em_priv	em_priv[EM_MAX_SLOTS];
-};
-
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
-static int ahci_port_start(struct ata_port *ap);
-static void ahci_port_stop(struct ata_port *ap);
-static void ahci_qc_prep(struct ata_queued_cmd *qc);
-static void ahci_freeze(struct ata_port *ap);
-static void ahci_thaw(struct ata_port *ap);
-static void ahci_pmp_attach(struct ata_port *ap);
-static void ahci_pmp_detach(struct ata_port *ap);
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline);
 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 			  unsigned long deadline);
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline);
 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline);
-static void ahci_postreset(struct ata_link *link, unsigned int *class);
-static void ahci_error_handler(struct ata_port *ap);
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
-static int ahci_port_resume(struct ata_port *ap);
-static void ahci_dev_config(struct ata_device *dev);
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-			       u32 opts);
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 static int ahci_pci_device_resume(struct pci_dev *pdev);
 #endif
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
-static ssize_t ahci_activity_store(struct ata_device *dev,
-				   enum sw_activity val);
-static void ahci_init_sw_activity(struct ata_link *link);
-
-static struct device_attribute *ahci_shost_attrs[] = {
-	&dev_attr_link_power_management_policy,
-	&dev_attr_em_message_type,
-	&dev_attr_em_message,
-	NULL
-};
-
-static struct device_attribute *ahci_sdev_attrs[] = {
-	&dev_attr_sw_activity,
-	&dev_attr_unload_heads,
-	NULL
-};
-
-static struct scsi_host_template ahci_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
-	.can_queue		= AHCI_MAX_CMDS - 1,
-	.sg_tablesize		= AHCI_MAX_SG,
-	.dma_boundary		= AHCI_DMA_BOUNDARY,
-	.shost_attrs		= ahci_shost_attrs,
-	.sdev_attrs		= ahci_sdev_attrs,
-};
-
-static struct ata_port_operations ahci_ops = {
-	.inherits		= &sata_pmp_port_ops,
-
-	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
-	.qc_prep		= ahci_qc_prep,
-	.qc_issue		= ahci_qc_issue,
-	.qc_fill_rtf		= ahci_qc_fill_rtf,
-
-	.freeze			= ahci_freeze,
-	.thaw			= ahci_thaw,
-	.softreset		= ahci_softreset,
-	.hardreset		= ahci_hardreset,
-	.postreset		= ahci_postreset,
-	.pmp_softreset		= ahci_softreset,
-	.error_handler		= ahci_error_handler,
-	.post_internal_cmd	= ahci_post_internal_cmd,
-	.dev_config		= ahci_dev_config,
-
-	.scr_read		= ahci_scr_read,
-	.scr_write		= ahci_scr_write,
-	.pmp_attach		= ahci_pmp_attach,
-	.pmp_detach		= ahci_pmp_detach,
-
-	.enable_pm		= ahci_enable_alpm,
-	.disable_pm		= ahci_disable_alpm,
-	.em_show		= ahci_led_show,
-	.em_store		= ahci_led_store,
-	.sw_activity_show	= ahci_activity_show,
-	.sw_activity_store	= ahci_activity_store,
-#ifdef CONFIG_PM
-	.port_suspend		= ahci_port_suspend,
-	.port_resume		= ahci_port_resume,
-#endif
-	.port_start		= ahci_port_start,
-	.port_stop		= ahci_port_stop,
-};
 
 static struct ata_port_operations ahci_vt8251_ops = {
 	.inherits		= &ahci_ops,
@@ -473,7 +162,7 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	/* board_ahci_yesncq */
+	[board_ahci_yesncq] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_YES_NCQ),
 		.flags		= AHCI_FLAG_COMMON,
@@ -481,6 +170,14 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
+	[board_ahci_nosntf] =
+	{
+		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -496,7 +193,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
+	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
@@ -644,12 +341,6 @@ static struct pci_driver ahci_pci_driver = {
 #endif
 };
 
-static int ahci_em_messages = 1;
-module_param(ahci_em_messages, int, 0444);
-/* add other LED protocol types when they become supported */
-MODULE_PARM_DESC(ahci_em_messages,
-	"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
-
 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 static int marvell_enable;
 #else
@@ -659,112 +350,15 @@ module_param(marvell_enable, int, 0644);
 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 
 
-static inline int ahci_nr_ports(u32 cap)
-{
-	return (cap & 0x1f) + 1;
-}
-
-static inline void __iomem *__ahci_port_base(struct ata_host *host,
-					     unsigned int port_no)
-{
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-	return mmio + 0x100 + (port_no * 0x80);
-}
-
-static inline void __iomem *ahci_port_base(struct ata_port *ap)
-{
-	return __ahci_port_base(ap->host, ap->port_no);
-}
-
-static void ahci_enable_ahci(void __iomem *mmio)
-{
-	int i;
-	u32 tmp;
-
-	/* turn on AHCI_EN */
-	tmp = readl(mmio + HOST_CTL);
-	if (tmp & HOST_AHCI_EN)
-		return;
-
-	/* Some controllers need AHCI_EN to be written multiple times.
-	 * Try a few times before giving up.
-	 */
-	for (i = 0; i < 5; i++) {
-		tmp |= HOST_AHCI_EN;
-		writel(tmp, mmio + HOST_CTL);
-		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
-		if (tmp & HOST_AHCI_EN)
-			return;
-		msleep(10);
-	}
-
-	WARN_ON(1);
-}
-
-/**
- *	ahci_save_initial_config - Save and fixup initial config values
- *	@pdev: target PCI device
- *	@hpriv: host private area to store config values
- *
- *	Some registers containing configuration info might be setup by
- *	BIOS and might be cleared on reset.  This function saves the
- *	initial values of those registers into @hpriv such that they
- *	can be restored after controller reset.
- *
- *	If inconsistent, config values are fixed up by this function.
- *
- *	LOCKING:
- *	None.
- */
-static void ahci_save_initial_config(struct pci_dev *pdev,
-				     struct ahci_host_priv *hpriv)
+static void ahci_pci_save_initial_config(struct pci_dev *pdev,
+					 struct ahci_host_priv *hpriv)
 {
-	void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-	u32 cap, port_map;
-	int i;
-	int mv;
-
-	/* make sure AHCI mode is enabled before accessing CAP */
-	ahci_enable_ahci(mmio);
+	unsigned int force_port_map = 0;
+	unsigned int mask_port_map = 0;
 
-	/* Values prefixed with saved_ are written back to host after
-	 * reset.  Values without are used for driver operation.
-	 */
-	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
-	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
-
-	/* some chips have errata preventing 64bit use */
-	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do 64bit DMA, forcing 32bit\n");
-		cap &= ~HOST_CAP_64;
-	}
-
-	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do NCQ, turning off CAP_NCQ\n");
-		cap &= ~HOST_CAP_NCQ;
-	}
-
-	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can do NCQ, turning on CAP_NCQ\n");
-		cap |= HOST_CAP_NCQ;
-	}
-
-	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "controller can't do PMP, turning off CAP_PMP\n");
-		cap &= ~HOST_CAP_PMP;
-	}
-
-	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
-	    port_map != 1) {
-		dev_printk(KERN_INFO, &pdev->dev,
-			   "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
-			   port_map, 1);
-		port_map = 1;
+	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
+		dev_info(&pdev->dev, "JMB361 has only one port\n");
+		force_port_map = 1;
 	}
 
 	/*
@@ -774,466 +368,25 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
 	 */
 	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 		if (pdev->device == 0x6121)
-			mv = 0x3;
+			mask_port_map = 0x3;
 		else
-			mv = 0xf;
-		dev_printk(KERN_ERR, &pdev->dev,
-			   "MV_AHCI HACK: port_map %x -> %x\n",
-			   port_map,
-			   port_map & mv);
-		dev_printk(KERN_ERR, &pdev->dev,
+			mask_port_map = 0xf;
+		dev_info(&pdev->dev,
 			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
-
-		port_map &= mv;
-	}
-
-	/* cross check port_map and cap.n_ports */
-	if (port_map) {
-		int map_ports = 0;
-
-		for (i = 0; i < AHCI_MAX_PORTS; i++)
-			if (port_map & (1 << i))
-				map_ports++;
-
-		/* If PI has more ports than n_ports, whine, clear
-		 * port_map and let it be generated from n_ports.
-		 */
-		if (map_ports > ahci_nr_ports(cap)) {
-			dev_printk(KERN_WARNING, &pdev->dev,
-				   "implemented port map (0x%x) contains more "
-				   "ports than nr_ports (%u), using nr_ports\n",
-				   port_map, ahci_nr_ports(cap));
-			port_map = 0;
-		}
-	}
-
-	/* fabricate port_map from cap.nr_ports */
-	if (!port_map) {
-		port_map = (1 << ahci_nr_ports(cap)) - 1;
-		dev_printk(KERN_WARNING, &pdev->dev,
-			   "forcing PORTS_IMPL to 0x%x\n", port_map);
-
-		/* write the fixed up value to the PI register */
-		hpriv->saved_port_map = port_map;
-	}
-
-	/* record values to use during operation */
-	hpriv->cap = cap;
-	hpriv->port_map = port_map;
-}
-
-/**
- *	ahci_restore_initial_config - Restore initial config
- *	@host: target ATA host
- *
- *	Restore initial config stored by ahci_save_initial_config().
- *
- *	LOCKING:
- *	None.
- */
-static void ahci_restore_initial_config(struct ata_host *host)
-{
-	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-
-	writel(hpriv->saved_cap, mmio + HOST_CAP);
-	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
-	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
-}
-
-static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
-{
-	static const int offset[] = {
-		[SCR_STATUS]		= PORT_SCR_STAT,
-		[SCR_CONTROL]		= PORT_SCR_CTL,
-		[SCR_ERROR]		= PORT_SCR_ERR,
-		[SCR_ACTIVE]		= PORT_SCR_ACT,
-		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
-	};
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-
-	if (sc_reg < ARRAY_SIZE(offset) &&
-	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
-		return offset[sc_reg];
-	return 0;
-}
-
-static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	int offset = ahci_scr_offset(link->ap, sc_reg);
-
-	if (offset) {
-		*val = readl(port_mmio + offset);
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	int offset = ahci_scr_offset(link->ap, sc_reg);
-
-	if (offset) {
-		writel(val, port_mmio + offset);
-		return 0;
-	}
-	return -EINVAL;
-}
-
-static void ahci_start_engine(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	/* start DMA */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_START;
-	writel(tmp, port_mmio + PORT_CMD);
-	readl(port_mmio + PORT_CMD); /* flush */
-}
-
-static int ahci_stop_engine(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	tmp = readl(port_mmio + PORT_CMD);
-
-	/* check if the HBA is idle */
-	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
-		return 0;
-
-	/* setting HBA to idle */
-	tmp &= ~PORT_CMD_START;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* wait for engine to stop. This could be as long as 500 msec */
-	tmp = ata_wait_register(port_mmio + PORT_CMD,
-				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
-	if (tmp & PORT_CMD_LIST_ON)
-		return -EIO;
-
-	return 0;
-}
-
-static void ahci_start_fis_rx(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 tmp;
-
-	/* set FIS registers */
-	if (hpriv->cap & HOST_CAP_64)
-		writel((pp->cmd_slot_dma >> 16) >> 16,
-		       port_mmio + PORT_LST_ADDR_HI);
-	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
-
-	if (hpriv->cap & HOST_CAP_64)
-		writel((pp->rx_fis_dma >> 16) >> 16,
-		       port_mmio + PORT_FIS_ADDR_HI);
-	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
-
-	/* enable FIS reception */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_FIS_RX;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* flush */
-	readl(port_mmio + PORT_CMD);
-}
-
-static int ahci_stop_fis_rx(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-
-	/* disable FIS reception */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp &= ~PORT_CMD_FIS_RX;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	/* wait for completion, spec says 500ms, give it 1000 */
-	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
-				PORT_CMD_FIS_ON, 10, 1000);
-	if (tmp & PORT_CMD_FIS_ON)
-		return -EBUSY;
-
-	return 0;
-}
-
-static void ahci_power_up(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-
-	/* spin up device */
-	if (hpriv->cap & HOST_CAP_SSS) {
-		cmd |= PORT_CMD_SPIN_UP;
-		writel(cmd, port_mmio + PORT_CMD);
-	}
-
-	/* wake up link */
-	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
-}
-
-static void ahci_disable_alpm(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* IPM bits should be disabled by libata-core */
-	/* get the existing command bits */
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* disable ALPM and ASP */
-	cmd &= ~PORT_CMD_ASP;
-	cmd &= ~PORT_CMD_ALPE;
-
-	/* force the interface back to active */
-	cmd |= PORT_CMD_ICC_ACTIVE;
-
-	/* write out new cmd value */
-	writel(cmd, port_mmio + PORT_CMD);
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* wait 10ms to be sure we've come out of any low power state */
-	msleep(10);
-
-	/* clear out any PhyRdy stuff from interrupt status */
-	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
-
-	/* go ahead and clean out PhyRdy Change from Serror too */
-	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-
-	/*
- 	 * Clear flag to indicate that we should ignore all PhyRdy
- 	 * state changes
- 	 */
-	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
-
-	/*
- 	 * Enable interrupts on Phy Ready.
- 	 */
-	pp->intr_mask |= PORT_IRQ_PHYRDY;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-	/*
- 	 * don't change the link pm policy - we can be called
- 	 * just to turn of link pm temporarily
- 	 */
-}
-
-static int ahci_enable_alpm(struct ata_port *ap,
-	enum link_pm policy)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd;
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 asp;
-
-	/* Make sure the host is capable of link power management */
-	if (!(hpriv->cap & HOST_CAP_ALPM))
-		return -EINVAL;
-
-	switch (policy) {
-	case MAX_PERFORMANCE:
-	case NOT_AVAILABLE:
-		/*
- 		 * if we came here with NOT_AVAILABLE,
- 		 * it just means this is the first time we
- 		 * have tried to enable - default to max performance,
- 		 * and let the user go to lower power modes on request.
- 		 */
-		ahci_disable_alpm(ap);
-		return 0;
-	case MIN_POWER:
-		/* configure HBA to enter SLUMBER */
-		asp = PORT_CMD_ASP;
-		break;
-	case MEDIUM_POWER:
-		/* configure HBA to enter PARTIAL */
-		asp = 0;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/*
- 	 * Disable interrupts on Phy Ready. This keeps us from
- 	 * getting woken up due to spurious phy ready interrupts
-	 * TBD - Hot plug should be done via polling now, is
-	 * that even supported?
- 	 */
-	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-
-	/*
- 	 * Set a flag to indicate that we should ignore all PhyRdy
- 	 * state changes since these can happen now whenever we
- 	 * change link state
- 	 */
-	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
-
-	/* get the existing command bits */
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/*
- 	 * Set ASP based on Policy
- 	 */
-	cmd |= asp;
-
-	/*
- 	 * Setting this bit will instruct the HBA to aggressively
- 	 * enter a lower power link state when it's appropriate and
- 	 * based on the value set above for ASP
- 	 */
-	cmd |= PORT_CMD_ALPE;
-
-	/* write out new cmd value */
-	writel(cmd, port_mmio + PORT_CMD);
-	cmd = readl(port_mmio + PORT_CMD);
-
-	/* IPM bits should be set by libata-core */
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static void ahci_power_down(struct ata_port *ap)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 cmd, scontrol;
-
-	if (!(hpriv->cap & HOST_CAP_SSS))
-		return;
-
-	/* put device into listen mode, first set PxSCTL.DET to 0 */
-	scontrol = readl(port_mmio + PORT_SCR_CTL);
-	scontrol &= ~0xf;
-	writel(scontrol, port_mmio + PORT_SCR_CTL);
-
-	/* then set PxCMD.SUD to 0 */
-	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
-	cmd &= ~PORT_CMD_SPIN_UP;
-	writel(cmd, port_mmio + PORT_CMD);
-}
-#endif
-
-static void ahci_start_port(struct ata_port *ap)
-{
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_link *link;
-	struct ahci_em_priv *emp;
-	ssize_t rc;
-	int i;
-
-	/* enable FIS reception */
-	ahci_start_fis_rx(ap);
-
-	/* enable DMA */
-	ahci_start_engine(ap);
-
-	/* turn on LEDs */
-	if (ap->flags & ATA_FLAG_EM) {
-		ata_for_each_link(link, ap, EDGE) {
-			emp = &pp->em_priv[link->pmp];
-
-			/* EM Transmit bit maybe busy during init */
-			for (i = 0; i < EM_MAX_RETRY; i++) {
-				rc = ahci_transmit_led_message(ap,
-							       emp->led_state,
-							       4);
-				if (rc == -EBUSY)
-					msleep(1);
-				else
-					break;
-			}
-		}
-	}
-
-	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
-		ata_for_each_link(link, ap, EDGE)
-			ahci_init_sw_activity(link);
-
-}
-
-static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
-{
-	int rc;
-
-	/* disable DMA */
-	rc = ahci_stop_engine(ap);
-	if (rc) {
-		*emsg = "failed to stop engine";
-		return rc;
-	}
-
-	/* disable FIS reception */
-	rc = ahci_stop_fis_rx(ap);
-	if (rc) {
-		*emsg = "failed stop FIS RX";
-		return rc;
 	}
 
-	return 0;
+	ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
+				 mask_port_map);
 }
 
-static int ahci_reset_controller(struct ata_host *host)
+static int ahci_pci_reset_controller(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 tmp;
 
-	/* we must be in AHCI mode, before using anything
-	 * AHCI-specific, such as HOST_RESET.
-	 */
-	ahci_enable_ahci(mmio);
-
-	/* global controller reset */
-	if (!ahci_skip_host_reset) {
-		tmp = readl(mmio + HOST_CTL);
-		if ((tmp & HOST_RESET) == 0) {
-			writel(tmp | HOST_RESET, mmio + HOST_CTL);
-			readl(mmio + HOST_CTL); /* flush */
-		}
-
-		/*
-		 * to perform host reset, OS should set HOST_RESET
-		 * and poll until this bit is read to be "0".
-		 * reset must complete within 1 second, or
-		 * the hardware should be considered fried.
-		 */
-		tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
-					HOST_RESET, 10, 1000);
-
-		if (tmp & HOST_RESET) {
-			dev_printk(KERN_ERR, host->dev,
-				   "controller reset failed (0x%x)\n", tmp);
-			return -EIO;
-		}
-
-		/* turn on AHCI mode */
-		ahci_enable_ahci(mmio);
-
-		/* Some registers might be cleared on reset.  Restore
-		 * initial values.
-		 */
-		ahci_restore_initial_config(host);
-	} else
-		dev_printk(KERN_INFO, host->dev,
-			   "skipping global host reset\n");
+	ahci_reset_controller(host);
 
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
+		struct ahci_host_priv *hpriv = host->private_data;
 		u16 tmp16;
 
 		/* configure PCS */
@@ -1247,267 +400,10 @@ static int ahci_reset_controller(struct ata_host *host)
 	return 0;
 }
 
-static void ahci_sw_activity(struct ata_link *link)
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
-		return;
-
-	emp->activity++;
-	if (!timer_pending(&emp->timer))
-		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
-}
-
-static void ahci_sw_activity_blink(unsigned long arg)
-{
-	struct ata_link *link = (struct ata_link *)arg;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-	unsigned long led_message = emp->led_state;
-	u32 activity_led_state;
-	unsigned long flags;
-
-	led_message &= EM_MSG_LED_VALUE;
-	led_message |= ap->port_no | (link->pmp << 8);
-
-	/* check to see if we've had activity.  If so,
-	 * toggle state of LED and reset timer.  If not,
-	 * turn LED to desired idle state.
-	 */
-	spin_lock_irqsave(ap->lock, flags);
-	if (emp->saved_activity != emp->activity) {
-		emp->saved_activity = emp->activity;
-		/* get the current LED state */
-		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
-
-		if (activity_led_state)
-			activity_led_state = 0;
-		else
-			activity_led_state = 1;
-
-		/* clear old state */
-		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-		/* toggle state */
-		led_message |= (activity_led_state << 16);
-		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
-	} else {
-		/* switch to idle */
-		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
-		if (emp->blink_policy == BLINK_OFF)
-			led_message |= (1 << 16);
-	}
-	spin_unlock_irqrestore(ap->lock, flags);
-	ahci_transmit_led_message(ap, led_message, 4);
-}
-
-static void ahci_init_sw_activity(struct ata_link *link)
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	/* init activity stats, setup timer */
-	emp->saved_activity = emp->activity = 0;
-	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
-
-	/* check our blink policy and set flag for link if it's enabled */
-	if (emp->blink_policy)
-		link->flags |= ATA_LFLAG_SW_ACTIVITY;
-}
-
-static int ahci_reset_em(struct ata_host *host)
-{
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 em_ctl;
-
-	em_ctl = readl(mmio + HOST_EM_CTL);
-	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
-		return -EINVAL;
-
-	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
-	return 0;
-}
-
-static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
-					ssize_t size)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-	u32 em_ctl;
-	u32 message[] = {0, 0};
-	unsigned long flags;
-	int pmp;
-	struct ahci_em_priv *emp;
-
-	/* get the slot number from the message */
-	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-	if (pmp < EM_MAX_SLOTS)
-		emp = &pp->em_priv[pmp];
-	else
-		return -EINVAL;
-
-	spin_lock_irqsave(ap->lock, flags);
-
-	/*
-	 * if we are still busy transmitting a previous message,
-	 * do not allow
-	 */
-	em_ctl = readl(mmio + HOST_EM_CTL);
-	if (em_ctl & EM_CTL_TM) {
-		spin_unlock_irqrestore(ap->lock, flags);
-		return -EBUSY;
-	}
-
-	/*
-	 * create message header - this is all zero except for
-	 * the message size, which is 4 bytes.
-	 */
-	message[0] |= (4 << 8);
-
-	/* ignore 0:4 of byte zero, fill in port info yourself */
-	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
-
-	/* write message to EM_LOC */
-	writel(message[0], mmio + hpriv->em_loc);
-	writel(message[1], mmio + hpriv->em_loc+4);
-
-	/* save off new led state for port/slot */
-	emp->led_state = state;
-
-	/*
-	 * tell hardware to transmit the message
-	 */
-	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
-
-	spin_unlock_irqrestore(ap->lock, flags);
-	return size;
-}
-
-static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
-{
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_link *link;
-	struct ahci_em_priv *emp;
-	int rc = 0;
-
-	ata_for_each_link(link, ap, EDGE) {
-		emp = &pp->em_priv[link->pmp];
-		rc += sprintf(buf, "%lx\n", emp->led_state);
-	}
-	return rc;
-}
-
-static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
-				size_t size)
-{
-	int state;
-	int pmp;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp;
-
-	state = simple_strtoul(buf, NULL, 0);
-
-	/* get the slot number from the message */
-	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
-	if (pmp < EM_MAX_SLOTS)
-		emp = &pp->em_priv[pmp];
-	else
-		return -EINVAL;
-
-	/* mask off the activity bits if we are in sw_activity
-	 * mode, user should turn off sw_activity before setting
-	 * activity led through em_message
-	 */
-	if (emp->blink_policy)
-		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
-
-	return ahci_transmit_led_message(ap, state, size);
-}
-
-static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
-{
-	struct ata_link *link = dev->link;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-	u32 port_led_state = emp->led_state;
-
-	/* save the desired Activity LED behavior */
-	if (val == OFF) {
-		/* clear LFLAG */
-		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
-
-		/* set the LED to OFF */
-		port_led_state &= EM_MSG_LED_VALUE_OFF;
-		port_led_state |= (ap->port_no | (link->pmp << 8));
-		ahci_transmit_led_message(ap, port_led_state, 4);
-	} else {
-		link->flags |= ATA_LFLAG_SW_ACTIVITY;
-		if (val == BLINK_OFF) {
-			/* set LED to ON for idle */
-			port_led_state &= EM_MSG_LED_VALUE_OFF;
-			port_led_state |= (ap->port_no | (link->pmp << 8));
-			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
-			ahci_transmit_led_message(ap, port_led_state, 4);
-		}
-	}
-	emp->blink_policy = val;
-	return 0;
-}
-
-static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
-{
-	struct ata_link *link = dev->link;
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
-
-	/* display the saved value of activity behavior for this
-	 * disk.
-	 */
-	return sprintf(buf, "%d\n", emp->blink_policy);
-}
-
-static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
-			   int port_no, void __iomem *mmio,
-			   void __iomem *port_mmio)
-{
-	const char *emsg = NULL;
-	int rc;
-	u32 tmp;
-
-	/* make sure port is not active */
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc)
-		dev_printk(KERN_WARNING, &pdev->dev,
-			   "%s (%d)\n", emsg, rc);
-
-	/* clear SError */
-	tmp = readl(port_mmio + PORT_SCR_ERR);
-	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
-	writel(tmp, port_mmio + PORT_SCR_ERR);
-
-	/* clear port IRQ */
-	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
-	if (tmp)
-		writel(tmp, port_mmio + PORT_IRQ_STAT);
-
-	writel(1 << port_no, mmio + HOST_IRQ_STAT);
-}
-
-static void ahci_init_controller(struct ata_host *host)
+static void ahci_pci_init_controller(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	int i;
 	void __iomem *port_mmio;
 	u32 tmp;
 	int mv;
@@ -1528,222 +424,7 @@ static void ahci_init_controller(struct ata_host *host)
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
 	}
 
-	for (i = 0; i < host->n_ports; i++) {
-		struct ata_port *ap = host->ports[i];
-
-		port_mmio = ahci_port_base(ap);
-		if (ata_port_is_dummy(ap))
-			continue;
-
-		ahci_port_init(pdev, ap, i, mmio, port_mmio);
-	}
-
-	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
-	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
-	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
-}
-
-static void ahci_dev_config(struct ata_device *dev)
-{
-	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
-
-	if (hpriv->flags & AHCI_HFLAG_SECT255) {
-		dev->max_sectors = 255;
-		ata_dev_printk(dev, KERN_INFO,
-			       "SB600 AHCI: limiting to 255 sectors per cmd\n");
-	}
-}
-
-static unsigned int ahci_dev_classify(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ata_taskfile tf;
-	u32 tmp;
-
-	tmp = readl(port_mmio + PORT_SIG);
-	tf.lbah		= (tmp >> 24)	& 0xff;
-	tf.lbam		= (tmp >> 16)	& 0xff;
-	tf.lbal		= (tmp >> 8)	& 0xff;
-	tf.nsect	= (tmp)		& 0xff;
-
-	return ata_dev_classify(&tf);
-}
-
-static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
-			       u32 opts)
-{
-	dma_addr_t cmd_tbl_dma;
-
-	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
-
-	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
-	pp->cmd_slot[tag].status = 0;
-	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
-	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
-}
-
-static int ahci_kick_engine(struct ata_port *ap, int force_restart)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-	u32 tmp;
-	int busy, rc;
-
-	/* do we need to kick the port? */
-	busy = status & (ATA_BUSY | ATA_DRQ);
-	if (!busy && !force_restart)
-		return 0;
-
-	/* stop engine */
-	rc = ahci_stop_engine(ap);
-	if (rc)
-		goto out_restart;
-
-	/* need to do CLO? */
-	if (!busy) {
-		rc = 0;
-		goto out_restart;
-	}
-
-	if (!(hpriv->cap & HOST_CAP_CLO)) {
-		rc = -EOPNOTSUPP;
-		goto out_restart;
-	}
-
-	/* perform CLO */
-	tmp = readl(port_mmio + PORT_CMD);
-	tmp |= PORT_CMD_CLO;
-	writel(tmp, port_mmio + PORT_CMD);
-
-	rc = 0;
-	tmp = ata_wait_register(port_mmio + PORT_CMD,
-				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
-	if (tmp & PORT_CMD_CLO)
-		rc = -EIO;
-
-	/* restart engine */
- out_restart:
-	ahci_start_engine(ap);
-	return rc;
-}
-
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
-				struct ata_taskfile *tf, int is_cmd, u16 flags,
-				unsigned long timeout_msec)
-{
-	const u32 cmd_fis_len = 5; /* five dwords */
-	struct ahci_port_priv *pp = ap->private_data;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u8 *fis = pp->cmd_tbl;
-	u32 tmp;
-
-	/* prep the command */
-	ata_tf_to_fis(tf, pmp, is_cmd, fis);
-	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
-
-	/* issue & wait */
-	writel(1, port_mmio + PORT_CMD_ISSUE);
-
-	if (timeout_msec) {
-		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
-					1, timeout_msec);
-		if (tmp & 0x1) {
-			ahci_kick_engine(ap, 1);
-			return -EBUSY;
-		}
-	} else
-		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
-
-	return 0;
-}
-
-static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
-			     int pmp, unsigned long deadline,
-			     int (*check_ready)(struct ata_link *link))
-{
-	struct ata_port *ap = link->ap;
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	const char *reason = NULL;
-	unsigned long now, msecs;
-	struct ata_taskfile tf;
-	int rc;
-
-	DPRINTK("ENTER\n");
-
-	/* prepare for SRST (AHCI-1.1 10.4.1) */
-	rc = ahci_kick_engine(ap, 1);
-	if (rc && rc != -EOPNOTSUPP)
-		ata_link_printk(link, KERN_WARNING,
-				"failed to reset engine (errno=%d)\n", rc);
-
-	ata_tf_init(link->device, &tf);
-
-	/* issue the first D2H Register FIS */
-	msecs = 0;
-	now = jiffies;
-	if (time_after(now, deadline))
-		msecs = jiffies_to_msecs(deadline - now);
-
-	tf.ctl |= ATA_SRST;
-	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
-				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
-		rc = -EIO;
-		reason = "1st FIS failed";
-		goto fail;
-	}
-
-	/* spec says at least 5us, but be generous and sleep for 1ms */
-	msleep(1);
-
-	/* issue the second D2H Register FIS */
-	tf.ctl &= ~ATA_SRST;
-	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
-
-	/* wait for link to become ready */
-	rc = ata_wait_after_reset(link, deadline, check_ready);
-	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
-		/*
-		 * Workaround for cases where link online status can't
-		 * be trusted.  Treat device readiness timeout as link
-		 * offline.
-		 */
-		ata_link_printk(link, KERN_INFO,
-				"device not ready, treating as offline\n");
-		*class = ATA_DEV_NONE;
-	} else if (rc) {
-		/* link occupied, -ENODEV too is an error */
-		reason = "device not ready";
-		goto fail;
-	} else
-		*class = ahci_dev_classify(ap);
-
-	DPRINTK("EXIT, class=%u\n", *class);
-	return 0;
-
- fail:
-	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
-	return rc;
-}
-
-static int ahci_check_ready(struct ata_link *link)
-{
-	void __iomem *port_mmio = ahci_port_base(link->ap);
-	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
-
-	return ata_check_ready(status);
-}
-
-static int ahci_softreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline)
-{
-	int pmp = sata_srst_pmp(link);
-
-	DPRINTK("ENTER\n");
-
-	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+	ahci_init_controller(host);
 }
 
 static int ahci_sb600_check_ready(struct ata_link *link)
@@ -1795,38 +476,6 @@ static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 	return rc;
 }
 
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-			  unsigned long deadline)
-{
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
-	struct ata_port *ap = link->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-	struct ata_taskfile tf;
-	bool online;
-	int rc;
-
-	DPRINTK("ENTER\n");
-
-	ahci_stop_engine(ap);
-
-	/* clear D2H reception area to properly wait for D2H FIS */
-	ata_tf_init(link->device, &tf);
-	tf.command = 0x80;
-	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
-
-	rc = sata_link_hardreset(link, timing, deadline, &online,
-				 ahci_check_ready);
-
-	ahci_start_engine(ap);
-
-	if (online)
-		*class = ahci_dev_classify(ap);
-
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-	return rc;
-}
-
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline)
 {
@@ -1890,453 +539,17 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 					  ahci_check_ready);
 		if (rc)
-			ahci_kick_engine(ap, 0);
+			ahci_kick_engine(ap);
 	}
 	return rc;
 }
 
-static void ahci_postreset(struct ata_link *link, unsigned int *class)
-{
-	struct ata_port *ap = link->ap;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 new_tmp, tmp;
-
-	ata_std_postreset(link, class);
-
-	/* Make sure port's ATAPI bit is set appropriately */
-	new_tmp = tmp = readl(port_mmio + PORT_CMD);
-	if (*class == ATA_DEV_ATAPI)
-		new_tmp |= PORT_CMD_ATAPI;
-	else
-		new_tmp &= ~PORT_CMD_ATAPI;
-	if (new_tmp != tmp) {
-		writel(new_tmp, port_mmio + PORT_CMD);
-		readl(port_mmio + PORT_CMD); /* flush */
-	}
-}
-
-static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
-{
-	struct scatterlist *sg;
-	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
-	unsigned int si;
-
-	VPRINTK("ENTER\n");
-
-	/*
-	 * Next, the S/G list.
-	 */
-	for_each_sg(qc->sg, sg, qc->n_elem, si) {
-		dma_addr_t addr = sg_dma_address(sg);
-		u32 sg_len = sg_dma_len(sg);
-
-		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
-		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
-		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
-	}
-
-	return si;
-}
-
-static void ahci_qc_prep(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-	struct ahci_port_priv *pp = ap->private_data;
-	int is_atapi = ata_is_atapi(qc->tf.protocol);
-	void *cmd_tbl;
-	u32 opts;
-	const u32 cmd_fis_len = 5; /* five dwords */
-	unsigned int n_elem;
-
-	/*
-	 * Fill in command table information.  First, the header,
-	 * a SATA Register - Host to Device command FIS.
-	 */
-	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
-
-	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
-	if (is_atapi) {
-		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
-		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
-	}
-
-	n_elem = 0;
-	if (qc->flags & ATA_QCFLAG_DMAMAP)
-		n_elem = ahci_fill_sg(qc, cmd_tbl);
-
-	/*
-	 * Fill in command slot information.
-	 */
-	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
-	if (qc->tf.flags & ATA_TFLAG_WRITE)
-		opts |= AHCI_CMD_WRITE;
-	if (is_atapi)
-		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
-
-	ahci_fill_cmd_slot(pp, qc->tag, opts);
-}
-
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
-{
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ata_eh_info *host_ehi = &ap->link.eh_info;
-	struct ata_link *link = NULL;
-	struct ata_queued_cmd *active_qc;
-	struct ata_eh_info *active_ehi;
-	u32 serror;
-
-	/* determine active link */
-	ata_for_each_link(link, ap, EDGE)
-		if (ata_link_active(link))
-			break;
-	if (!link)
-		link = &ap->link;
-
-	active_qc = ata_qc_from_tag(ap, link->active_tag);
-	active_ehi = &link->eh_info;
-
-	/* record irq stat */
-	ata_ehi_clear_desc(host_ehi);
-	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
-
-	/* AHCI needs SError cleared; otherwise, it might lock up */
-	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
-	ahci_scr_write(&ap->link, SCR_ERROR, serror);
-	host_ehi->serror |= serror;
-
-	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
-	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
-		irq_stat &= ~PORT_IRQ_IF_ERR;
-
-	if (irq_stat & PORT_IRQ_TF_ERR) {
-		/* If qc is active, charge it; otherwise, the active
-		 * link.  There's no active qc on NCQ errors.  It will
-		 * be determined by EH by reading log page 10h.
-		 */
-		if (active_qc)
-			active_qc->err_mask |= AC_ERR_DEV;
-		else
-			active_ehi->err_mask |= AC_ERR_DEV;
-
-		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
-			host_ehi->serror &= ~SERR_INTERNAL;
-	}
-
-	if (irq_stat & PORT_IRQ_UNK_FIS) {
-		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
-
-		active_ehi->err_mask |= AC_ERR_HSM;
-		active_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(active_ehi,
-				  "unknown FIS %08x %08x %08x %08x" ,
-				  unk[0], unk[1], unk[2], unk[3]);
-	}
-
-	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
-		active_ehi->err_mask |= AC_ERR_HSM;
-		active_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(active_ehi, "incorrect PMP");
-	}
-
-	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
-		host_ehi->err_mask |= AC_ERR_HOST_BUS;
-		host_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(host_ehi, "host bus error");
-	}
-
-	if (irq_stat & PORT_IRQ_IF_ERR) {
-		host_ehi->err_mask |= AC_ERR_ATA_BUS;
-		host_ehi->action |= ATA_EH_RESET;
-		ata_ehi_push_desc(host_ehi, "interface fatal error");
-	}
-
-	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
-		ata_ehi_hotplugged(host_ehi);
-		ata_ehi_push_desc(host_ehi, "%s",
-			irq_stat & PORT_IRQ_CONNECT ?
-			"connection status changed" : "PHY RDY changed");
-	}
-
-	/* okay, let's hand over to EH */
-
-	if (irq_stat & PORT_IRQ_FREEZE)
-		ata_port_freeze(ap);
-	else
-		ata_port_abort(ap);
-}
-
-static void ahci_port_intr(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ata_eh_info *ehi = &ap->link.eh_info;
-	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
-	u32 status, qc_active;
-	int rc;
-
-	status = readl(port_mmio + PORT_IRQ_STAT);
-	writel(status, port_mmio + PORT_IRQ_STAT);
-
-	/* ignore BAD_PMP while resetting */
-	if (unlikely(resetting))
-		status &= ~PORT_IRQ_BAD_PMP;
-
-	/* If we are getting PhyRdy, this is
- 	 * just a power state change, we should
- 	 * clear out this, plus the PhyRdy/Comm
- 	 * Wake bits from Serror
- 	 */
-	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
-		(status & PORT_IRQ_PHYRDY)) {
-		status &= ~PORT_IRQ_PHYRDY;
-		ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
-	}
-
-	if (unlikely(status & PORT_IRQ_ERROR)) {
-		ahci_error_intr(ap, status);
-		return;
-	}
-
-	if (status & PORT_IRQ_SDB_FIS) {
-		/* If SNotification is available, leave notification
-		 * handling to sata_async_notification().  If not,
-		 * emulate it by snooping SDB FIS RX area.
-		 *
-		 * Snooping FIS RX area is probably cheaper than
-		 * poking SNotification but some constrollers which
-		 * implement SNotification, ICH9 for example, don't
-		 * store AN SDB FIS into receive area.
-		 */
-		if (hpriv->cap & HOST_CAP_SNTF)
-			sata_async_notification(ap);
-		else {
-			/* If the 'N' bit in word 0 of the FIS is set,
-			 * we just received asynchronous notification.
-			 * Tell libata about it.
-			 */
-			const __le32 *f = pp->rx_fis + RX_FIS_SDB;
-			u32 f0 = le32_to_cpu(f[0]);
-
-			if (f0 & (1 << 15))
-				sata_async_notification(ap);
-		}
-	}
-
-	/* pp->active_link is valid iff any command is in flight */
-	if (ap->qc_active && pp->active_link->sactive)
-		qc_active = readl(port_mmio + PORT_SCR_ACT);
-	else
-		qc_active = readl(port_mmio + PORT_CMD_ISSUE);
-
-	rc = ata_qc_complete_multiple(ap, qc_active);
-
-	/* while resetting, invalid completions are expected */
-	if (unlikely(rc < 0 && !resetting)) {
-		ehi->err_mask |= AC_ERR_HSM;
-		ehi->action |= ATA_EH_RESET;
-		ata_port_freeze(ap);
-	}
-}
-
-static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
-{
-	struct ata_host *host = dev_instance;
-	struct ahci_host_priv *hpriv;
-	unsigned int i, handled = 0;
-	void __iomem *mmio;
-	u32 irq_stat, irq_masked;
-
-	VPRINTK("ENTER\n");
-
-	hpriv = host->private_data;
-	mmio = host->iomap[AHCI_PCI_BAR];
-
-	/* sigh.  0xffffffff is a valid return from h/w */
-	irq_stat = readl(mmio + HOST_IRQ_STAT);
-	if (!irq_stat)
-		return IRQ_NONE;
-
-	irq_masked = irq_stat & hpriv->port_map;
-
-	spin_lock(&host->lock);
-
-	for (i = 0; i < host->n_ports; i++) {
-		struct ata_port *ap;
-
-		if (!(irq_masked & (1 << i)))
-			continue;
-
-		ap = host->ports[i];
-		if (ap) {
-			ahci_port_intr(ap);
-			VPRINTK("port %u\n", i);
-		} else {
-			VPRINTK("port %u (no irq)\n", i);
-			if (ata_ratelimit())
-				dev_printk(KERN_WARNING, host->dev,
-					"interrupt on disabled port %u\n", i);
-		}
-
-		handled = 1;
-	}
-
-	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
-	 * it should be cleared after all the port events are cleared;
-	 * otherwise, it will raise a spurious interrupt after each
-	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
-	 * information.
-	 *
-	 * Also, use the unmasked value to clear interrupt as spurious
-	 * pending event on a dummy port might cause screaming IRQ.
-	 */
-	writel(irq_stat, mmio + HOST_IRQ_STAT);
-
-	spin_unlock(&host->lock);
-
-	VPRINTK("EXIT\n");
-
-	return IRQ_RETVAL(handled);
-}
-
-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* Keep track of the currently active link.  It will be used
-	 * in completion path to determine whether NCQ phase is in
-	 * progress.
-	 */
-	pp->active_link = qc->dev->link;
-
-	if (qc->tf.protocol == ATA_PROT_NCQ)
-		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
-	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
-
-	ahci_sw_activity(qc->dev->link);
-
-	return 0;
-}
-
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
-	struct ahci_port_priv *pp = qc->ap->private_data;
-	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
-
-	ata_tf_from_fis(d2h_fis, &qc->result_tf);
-	return true;
-}
-
-static void ahci_freeze(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-
-	/* turn IRQ off */
-	writel(0, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_thaw(struct ata_port *ap)
-{
-	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
-	void __iomem *port_mmio = ahci_port_base(ap);
-	u32 tmp;
-	struct ahci_port_priv *pp = ap->private_data;
-
-	/* clear IRQ */
-	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	writel(tmp, port_mmio + PORT_IRQ_STAT);
-	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
-
-	/* turn IRQ back on */
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_error_handler(struct ata_port *ap)
-{
-	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
-		/* restart engine */
-		ahci_stop_engine(ap);
-		ahci_start_engine(ap);
-	}
-
-	sata_pmp_error_handler(ap);
-}
-
-static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-
-	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
-		ahci_kick_engine(ap, 1);
-}
-
-static void ahci_pmp_attach(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD);
-	cmd |= PORT_CMD_PMP;
-	writel(cmd, port_mmio + PORT_CMD);
-
-	pp->intr_mask |= PORT_IRQ_BAD_PMP;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static void ahci_pmp_detach(struct ata_port *ap)
-{
-	void __iomem *port_mmio = ahci_port_base(ap);
-	struct ahci_port_priv *pp = ap->private_data;
-	u32 cmd;
-
-	cmd = readl(port_mmio + PORT_CMD);
-	cmd &= ~PORT_CMD_PMP;
-	writel(cmd, port_mmio + PORT_CMD);
-
-	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
-	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
-}
-
-static int ahci_port_resume(struct ata_port *ap)
-{
-	ahci_power_up(ap);
-	ahci_start_port(ap);
-
-	if (sata_pmp_attached(ap))
-		ahci_pmp_attach(ap);
-	else
-		ahci_pmp_detach(ap);
-
-	return 0;
-}
-
 #ifdef CONFIG_PM
-static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
-{
-	const char *emsg = NULL;
-	int rc;
-
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc == 0)
-		ahci_power_down(ap);
-	else {
-		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
-		ahci_start_port(ap);
-	}
-
-	return rc;
-}
-
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	struct ahci_host_priv *hpriv = host->private_data;
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
+	void __iomem *mmio = hpriv->mmio;
 	u32 ctl;
 
 	if (mesg.event & PM_EVENT_SUSPEND &&
@@ -2370,11 +583,11 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 		return rc;
 
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
-		rc = ahci_reset_controller(host);
+		rc = ahci_pci_reset_controller(host);
 		if (rc)
 			return rc;
 
-		ahci_init_controller(host);
+		ahci_pci_init_controller(host);
 	}
 
 	ata_host_resume(host);
@@ -2383,72 +596,6 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
 }
 #endif
 
-static int ahci_port_start(struct ata_port *ap)
-{
-	struct device *dev = ap->host->dev;
-	struct ahci_port_priv *pp;
-	void *mem;
-	dma_addr_t mem_dma;
-
-	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
-	if (!pp)
-		return -ENOMEM;
-
-	mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
-				  GFP_KERNEL);
-	if (!mem)
-		return -ENOMEM;
-	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
-
-	/*
-	 * First item in chunk of DMA memory: 32-slot command table,
-	 * 32 bytes each in size
-	 */
-	pp->cmd_slot = mem;
-	pp->cmd_slot_dma = mem_dma;
-
-	mem += AHCI_CMD_SLOT_SZ;
-	mem_dma += AHCI_CMD_SLOT_SZ;
-
-	/*
-	 * Second item: Received-FIS area
-	 */
-	pp->rx_fis = mem;
-	pp->rx_fis_dma = mem_dma;
-
-	mem += AHCI_RX_FIS_SZ;
-	mem_dma += AHCI_RX_FIS_SZ;
-
-	/*
-	 * Third item: data area for storing a single command
-	 * and its scatter-gather table
-	 */
-	pp->cmd_tbl = mem;
-	pp->cmd_tbl_dma = mem_dma;
-
-	/*
-	 * Save off initial list of interrupts to be enabled.
-	 * This could be changed later
-	 */
-	pp->intr_mask = DEF_PORT_IRQ;
-
-	ap->private_data = pp;
-
-	/* engage engines, captain */
-	return ahci_port_resume(ap);
-}
-
-static void ahci_port_stop(struct ata_port *ap)
-{
-	const char *emsg = NULL;
-	int rc;
-
-	/* de-initialize port */
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc)
-		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
-}
-
 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 {
 	int rc;
@@ -2481,30 +628,12 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 	return 0;
 }
 
-static void ahci_print_info(struct ata_host *host)
+static void ahci_pci_print_info(struct ata_host *host)
 {
-	struct ahci_host_priv *hpriv = host->private_data;
 	struct pci_dev *pdev = to_pci_dev(host->dev);
-	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
-	u32 vers, cap, impl, speed;
-	const char *speed_s;
 	u16 cc;
 	const char *scc_s;
 
-	vers = readl(mmio + HOST_VERSION);
-	cap = hpriv->cap;
-	impl = hpriv->port_map;
-
-	speed = (cap >> 20) & 0xf;
-	if (speed == 1)
-		speed_s = "1.5";
-	else if (speed == 2)
-		speed_s = "3";
-	else if (speed == 3)
-		speed_s = "6";
-	else
-		speed_s = "?";
-
 	pci_read_config_word(pdev, 0x0a, &cc);
 	if (cc == PCI_CLASS_STORAGE_IDE)
 		scc_s = "IDE";
@@ -2515,46 +644,7 @@ static void ahci_print_info(struct ata_host *host)
 	else
 		scc_s = "unknown";
 
-	dev_printk(KERN_INFO, &pdev->dev,
-		"AHCI %02x%02x.%02x%02x "
-		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
-		,
-
-		(vers >> 24) & 0xff,
-		(vers >> 16) & 0xff,
-		(vers >> 8) & 0xff,
-		vers & 0xff,
-
-		((cap >> 8) & 0x1f) + 1,
-		(cap & 0x1f) + 1,
-		speed_s,
-		impl,
-		scc_s);
-
-	dev_printk(KERN_INFO, &pdev->dev,
-		"flags: "
-		"%s%s%s%s%s%s%s"
-		"%s%s%s%s%s%s%s"
-		"%s\n"
-		,
-
-		cap & (1 << 31) ? "64bit " : "",
-		cap & (1 << 30) ? "ncq " : "",
-		cap & (1 << 29) ? "sntf " : "",
-		cap & (1 << 28) ? "ilck " : "",
-		cap & (1 << 27) ? "stag " : "",
-		cap & (1 << 26) ? "pm " : "",
-		cap & (1 << 25) ? "led " : "",
-
-		cap & (1 << 24) ? "clo " : "",
-		cap & (1 << 19) ? "nz " : "",
-		cap & (1 << 18) ? "only " : "",
-		cap & (1 << 17) ? "pmp " : "",
-		cap & (1 << 15) ? "pio " : "",
-		cap & (1 << 14) ? "slum " : "",
-		cap & (1 << 13) ? "part " : "",
-		cap & (1 << 6) ? "ems ": ""
-		);
+	ahci_print_info(host, scc_s);
 }
 
 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
@@ -2789,6 +879,55 @@ static bool ahci_broken_online(struct pci_dev *pdev)
 	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
 }
 
+#ifdef CONFIG_ATA_ACPI
+static void ahci_gtf_filter_workaround(struct ata_host *host)
+{
+	static const struct dmi_system_id sysids[] = {
+		/*
+		 * Aspire 3810T issues a bunch of SATA enable commands
+		 * via _GTF including an invalid one and one which is
+		 * rejected by the device.  Among the successful ones
+		 * is FPDMA non-zero offset enable which when enabled
+		 * only on the drive side leads to NCQ command
+		 * failures.  Filter it out.
+		 */
+		{
+			.ident = "Aspire 3810T",
+			.matches = {
+				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+				DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
+			},
+			.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
+		},
+		{ }
+	};
+	const struct dmi_system_id *dmi = dmi_first_match(sysids);
+	unsigned int filter;
+	int i;
+
+	if (!dmi)
+		return;
+
+	filter = (unsigned long)dmi->driver_data;
+	dev_printk(KERN_INFO, host->dev,
+		   "applying extra ACPI _GTF filter 0x%x for %s\n",
+		   filter, dmi->ident);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+		struct ata_link *link;
+		struct ata_device *dev;
+
+		ata_for_each_link(link, ap, EDGE)
+			ata_for_each_dev(dev, link, ALL)
+				dev->gtf_filter |= filter;
+	}
+}
+#else
+static inline void ahci_gtf_filter_workaround(struct ata_host *host)
+{}
+#endif
+
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
 	static int printed_version;
@@ -2864,33 +1003,19 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
 		pci_enable_msi(pdev);
 
+	hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
+
 	/* save initial config */
-	ahci_save_initial_config(pdev, hpriv);
+	ahci_pci_save_initial_config(pdev, hpriv);
 
 	/* prepare host */
 	if (hpriv->cap & HOST_CAP_NCQ)
-		pi.flags |= ATA_FLAG_NCQ;
+		pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
 
 	if (hpriv->cap & HOST_CAP_PMP)
 		pi.flags |= ATA_FLAG_PMP;
 
-	if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
-		u8 messages;
-		void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
-		u32 em_loc = readl(mmio + HOST_EM_LOC);
-		u32 em_ctl = readl(mmio + HOST_EM_CTL);
-
-		messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
-
-		/* we only support LED message type right now */
-		if ((messages & 0x01) && (ahci_em_messages == 1)) {
-			/* store em_loc */
-			hpriv->em_loc = ((em_loc >> 16) * 4);
-			pi.flags |= ATA_FLAG_EM;
-			if (!(em_ctl & EM_CTL_ALHD))
-				pi.flags |= ATA_FLAG_SW_ACTIVITY;
-		}
-	}
+	ahci_set_em_messages(hpriv, &pi);
 
 	if (ahci_broken_system_poweroff(pdev)) {
 		pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
@@ -2920,7 +1045,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 	if (!host)
 		return -ENOMEM;
-	host->iomap = pcim_iomap_table(pdev);
 	host->private_data = hpriv;
 
 	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
@@ -2954,17 +1078,20 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	/* apply workaround for ASUS P5W DH Deluxe mainboard */
 	ahci_p5wdh_workaround(host);
 
+	/* apply gtf filter quirk */
+	ahci_gtf_filter_workaround(host);
+
 	/* initialize adapter */
 	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
 	if (rc)
 		return rc;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 
-	ahci_init_controller(host);
-	ahci_print_info(host);
+	ahci_pci_init_controller(host);
+	ahci_pci_print_info(host);
 
 	pci_set_master(pdev);
 	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
new file mode 100644
index 000000000000..111a878d9188
--- /dev/null
+++ b/drivers/ata/ahci.h
@@ -0,0 +1,332 @@
+/*
+ *  ahci.h - Common AHCI SATA definitions and declarations
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    		    Please ALWAYS copy linux-ide@vger.kernel.org
+ *		    on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#ifndef _AHCI_H
+#define _AHCI_H
+
+#include <linux/libata.h>
+
+/* Enclosure Management Control */
+#define EM_CTRL_MSG_TYPE              0x000f0000
+
+/* Enclosure Management LED Message Type */
+#define EM_MSG_LED_HBA_PORT           0x0000000f
+#define EM_MSG_LED_PMP_SLOT           0x0000ff00
+#define EM_MSG_LED_VALUE              0xffff0000
+#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
+#define EM_MSG_LED_VALUE_OFF          0xfff80000
+#define EM_MSG_LED_VALUE_ON           0x00010000
+
+enum {
+	AHCI_MAX_PORTS		= 32,
+	AHCI_MAX_SG		= 168, /* hardware max is 64K */
+	AHCI_DMA_BOUNDARY	= 0xffffffff,
+	AHCI_MAX_CMDS		= 32,
+	AHCI_CMD_SZ		= 32,
+	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
+	AHCI_RX_FIS_SZ		= 256,
+	AHCI_CMD_TBL_CDB	= 0x40,
+	AHCI_CMD_TBL_HDR_SZ	= 0x80,
+	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
+	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
+	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
+				  AHCI_RX_FIS_SZ,
+	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
+					  AHCI_CMD_TBL_AR_SZ +
+					  (AHCI_RX_FIS_SZ * 16),
+	AHCI_IRQ_ON_SG		= (1 << 31),
+	AHCI_CMD_ATAPI		= (1 << 5),
+	AHCI_CMD_WRITE		= (1 << 6),
+	AHCI_CMD_PREFETCH	= (1 << 7),
+	AHCI_CMD_RESET		= (1 << 8),
+	AHCI_CMD_CLR_BUSY	= (1 << 10),
+
+	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
+	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
+	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
+
+	/* global controller registers */
+	HOST_CAP		= 0x00, /* host capabilities */
+	HOST_CTL		= 0x04, /* global host control */
+	HOST_IRQ_STAT		= 0x08, /* interrupt status */
+	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
+	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
+	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
+	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
+	HOST_CAP2		= 0x24, /* host capabilities, extended */
+
+	/* HOST_CTL bits */
+	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
+	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
+	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
+
+	/* HOST_CAP bits */
+	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
+	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
+	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
+	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
+	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
+	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
+	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
+	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
+	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
+	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
+	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
+	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
+	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
+	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
+	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
+	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
+	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
+
+	/* HOST_CAP2 bits */
+	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
+	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
+	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
+
+	/* registers for each SATA port */
+	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
+	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
+	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
+	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
+	PORT_IRQ_STAT		= 0x10, /* interrupt status */
+	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
+	PORT_CMD		= 0x18, /* port command */
+	PORT_TFDATA		= 0x20,	/* taskfile data */
+	PORT_SIG		= 0x24,	/* device TF signature */
+	PORT_CMD_ISSUE		= 0x38, /* command issue */
+	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
+	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
+	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
+	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
+	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
+	PORT_FBS		= 0x40, /* FIS-based Switching */
+
+	/* PORT_IRQ_{STAT,MASK} bits */
+	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
+	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
+	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
+	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
+	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
+	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
+	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
+	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
+
+	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
+	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
+	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
+	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
+	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
+	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
+	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
+	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
+	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
+
+	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
+				  PORT_IRQ_IF_ERR |
+				  PORT_IRQ_CONNECT |
+				  PORT_IRQ_PHYRDY |
+				  PORT_IRQ_UNK_FIS |
+				  PORT_IRQ_BAD_PMP,
+	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
+				  PORT_IRQ_TF_ERR |
+				  PORT_IRQ_HBUS_DATA_ERR,
+	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
+				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
+				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
+
+	/* PORT_CMD bits */
+	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
+	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
+	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
+	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
+	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
+	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
+	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
+	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
+	PORT_CMD_CLO		= (1 << 3), /* Command list override */
+	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
+	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
+	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
+
+	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
+	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
+	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
+	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
+
+	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
+	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
+	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
+	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
+	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
+	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
+	PORT_FBS_EN		= (1 << 0), /* Enable FBS */
+
+	/* hpriv->flags bits */
+	AHCI_HFLAG_NO_NCQ		= (1 << 0),
+	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
+	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
+	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
+	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
+	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
+	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
+	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
+	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
+	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
+	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
+	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
+							link offline */
+	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
+
+	/* ap->flags bits */
+
+	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
+					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
+					  ATA_FLAG_IPM,
+
+	ICH_MAP				= 0x90, /* ICH MAP register */
+
+	/* em constants */
+	EM_MAX_SLOTS			= 8,
+	EM_MAX_RETRY			= 5,
+
+	/* em_ctl bits */
+	EM_CTL_RST			= (1 << 9), /* Reset */
+	EM_CTL_TM			= (1 << 8), /* Transmit Message */
+	EM_CTL_ALHD			= (1 << 26), /* Activity LED */
+};
+
+struct ahci_cmd_hdr {
+	__le32			opts;
+	__le32			status;
+	__le32			tbl_addr;
+	__le32			tbl_addr_hi;
+	__le32			reserved[4];
+};
+
+struct ahci_sg {
+	__le32			addr;
+	__le32			addr_hi;
+	__le32			reserved;
+	__le32			flags_size;
+};
+
+struct ahci_em_priv {
+	enum sw_activity blink_policy;
+	struct timer_list timer;
+	unsigned long saved_activity;
+	unsigned long activity;
+	unsigned long led_state;
+};
+
+struct ahci_port_priv {
+	struct ata_link		*active_link;
+	struct ahci_cmd_hdr	*cmd_slot;
+	dma_addr_t		cmd_slot_dma;
+	void			*cmd_tbl;
+	dma_addr_t		cmd_tbl_dma;
+	void			*rx_fis;
+	dma_addr_t		rx_fis_dma;
+	/* for NCQ spurious interrupt analysis */
+	unsigned int		ncq_saw_d2h:1;
+	unsigned int		ncq_saw_dmas:1;
+	unsigned int		ncq_saw_sdb:1;
+	u32 			intr_mask;	/* interrupts to enable */
+	bool			fbs_supported;	/* set iff FBS is supported */
+	bool			fbs_enabled;	/* set iff FBS is enabled */
+	int			fbs_last_dev;	/* save FBS.DEV of last FIS */
+	/* enclosure management info per PM slot */
+	struct ahci_em_priv	em_priv[EM_MAX_SLOTS];
+};
+
+struct ahci_host_priv {
+	void __iomem *		mmio;		/* bus-independant mem map */
+	unsigned int		flags;		/* AHCI_HFLAG_* */
+	u32			cap;		/* cap to use */
+	u32			cap2;		/* cap2 to use */
+	u32			port_map;	/* port map to use */
+	u32			saved_cap;	/* saved initial cap */
+	u32			saved_cap2;	/* saved initial cap2 */
+	u32			saved_port_map;	/* saved initial port_map */
+	u32 			em_loc; /* enclosure management location */
+};
+
+extern int ahci_em_messages;
+extern int ahci_ignore_sss;
+
+extern struct scsi_host_template ahci_sht;
+extern struct ata_port_operations ahci_ops;
+
+void ahci_save_initial_config(struct device *dev,
+			      struct ahci_host_priv *hpriv,
+			      unsigned int force_port_map,
+			      unsigned int mask_port_map);
+void ahci_init_controller(struct ata_host *host);
+int ahci_reset_controller(struct ata_host *host);
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+		      int pmp, unsigned long deadline,
+		      int (*check_ready)(struct ata_link *link));
+
+int ahci_stop_engine(struct ata_port *ap);
+void ahci_start_engine(struct ata_port *ap);
+int ahci_check_ready(struct ata_link *link);
+int ahci_kick_engine(struct ata_port *ap);
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+			  struct ata_port_info *pi);
+int ahci_reset_em(struct ata_host *host);
+irqreturn_t ahci_interrupt(int irq, void *dev_instance);
+void ahci_print_info(struct ata_host *host, const char *scc_s);
+
+static inline void __iomem *__ahci_port_base(struct ata_host *host,
+					     unsigned int port_no)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	return mmio + 0x100 + (port_no * 0x80);
+}
+
+static inline void __iomem *ahci_port_base(struct ata_port *ap)
+{
+	return __ahci_port_base(ap->host, ap->port_no);
+}
+
+static inline int ahci_nr_ports(u32 cap)
+{
+	return (cap & 0x1f) + 1;
+}
+
+#endif /* _AHCI_H */
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
new file mode 100644
index 000000000000..42cdd7363fad
--- /dev/null
+++ b/drivers/ata/ahci_platform.c
@@ -0,0 +1,191 @@
+/*
+ * AHCI SATA platform driver
+ *
+ * Copyright 2004-2005  Red Hat, Inc.
+ *   Jeff Garzik <jgarzik@pobox.com>
+ * Copyright 2010  MontaVista Software, LLC.
+ *   Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include "ahci.h"
+
+static int __init ahci_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ahci_platform_data *pdata = dev->platform_data;
+	struct ata_port_info pi = {
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	};
+	const struct ata_port_info *ppi[] = { &pi, NULL };
+	struct ahci_host_priv *hpriv;
+	struct ata_host *host;
+	struct resource *mem;
+	int irq;
+	int n_ports;
+	int i;
+	int rc;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(dev, "no mmio space\n");
+		return -EINVAL;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq <= 0) {
+		dev_err(dev, "no irq\n");
+		return -EINVAL;
+	}
+
+	if (pdata && pdata->init) {
+		rc = pdata->init(dev);
+		if (rc)
+			return rc;
+	}
+
+	if (pdata && pdata->ata_port_info)
+		pi = *pdata->ata_port_info;
+
+	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv) {
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	hpriv->flags |= (unsigned long)pi.private_data;
+
+	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
+	if (!hpriv->mmio) {
+		dev_err(dev, "can't map %pR\n", mem);
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	ahci_save_initial_config(dev, hpriv,
+		pdata ? pdata->force_port_map : 0,
+		pdata ? pdata->mask_port_map  : 0);
+
+	/* prepare host */
+	if (hpriv->cap & HOST_CAP_NCQ)
+		pi.flags |= ATA_FLAG_NCQ;
+
+	if (hpriv->cap & HOST_CAP_PMP)
+		pi.flags |= ATA_FLAG_PMP;
+
+	ahci_set_em_messages(hpriv, &pi);
+
+	/* CAP.NP sometimes indicate the index of the last enabled
+	 * port, at other times, that of the last possible port, so
+	 * determining the maximum port number requires looking at
+	 * both CAP.NP and port_map.
+	 */
+	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+
+	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+	if (!host) {
+		rc = -ENOMEM;
+		goto err0;
+	}
+
+	host->private_data = hpriv;
+
+	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+		host->flags |= ATA_HOST_PARALLEL_SCAN;
+	else
+		printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
+
+	if (pi.flags & ATA_FLAG_EM)
+		ahci_reset_em(host);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		ata_port_desc(ap, "mmio %pR", mem);
+		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+		/* set initial link pm policy */
+		ap->pm_policy = NOT_AVAILABLE;
+
+		/* set enclosure management message type */
+		if (ap->flags & ATA_FLAG_EM)
+			ap->em_message_type = ahci_em_messages;
+
+		/* disabled/not-implemented port */
+		if (!(hpriv->port_map & (1 << i)))
+			ap->ops = &ata_dummy_port_ops;
+	}
+
+	rc = ahci_reset_controller(host);
+	if (rc)
+		goto err0;
+
+	ahci_init_controller(host);
+	ahci_print_info(host, "platform");
+
+	rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
+			       &ahci_sht);
+	if (rc)
+		goto err0;
+
+	return 0;
+err0:
+	if (pdata && pdata->exit)
+		pdata->exit(dev);
+	return rc;
+}
+
+static int __devexit ahci_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ahci_platform_data *pdata = dev->platform_data;
+	struct ata_host *host = dev_get_drvdata(dev);
+
+	ata_host_detach(host);
+
+	if (pdata && pdata->exit)
+		pdata->exit(dev);
+
+	return 0;
+}
+
+static struct platform_driver ahci_driver = {
+	.probe = ahci_probe,
+	.remove = __devexit_p(ahci_remove),
+	.driver = {
+		.name = "ahci",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init ahci_init(void)
+{
+	return platform_driver_probe(&ahci_driver, ahci_probe);
+}
+module_init(ahci_init);
+
+static void __exit ahci_exit(void)
+{
+	platform_driver_unregister(&ahci_driver);
+}
+module_exit(ahci_exit);
+
+MODULE_DESCRIPTION("AHCI SATA platform driver");
+MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ahci");
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
new file mode 100644
index 000000000000..38e1b4e9ecf4
--- /dev/null
+++ b/drivers/ata/libahci.c
@@ -0,0 +1,2091 @@
+/*
+ *  libahci.c - Common AHCI SATA low-level routines
+ *
+ *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    		    Please ALWAYS copy linux-ide@vger.kernel.org
+ *		    on emails.
+ *
+ *  Copyright 2004-2005 Red Hat, Inc.
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+#include <linux/libata.h>
+#include "ahci.h"
+
+static int ahci_skip_host_reset;
+int ahci_ignore_sss;
+EXPORT_SYMBOL_GPL(ahci_ignore_sss);
+
+module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
+MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
+
+module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
+MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
+
+static int ahci_enable_alpm(struct ata_port *ap,
+		enum link_pm policy);
+static void ahci_disable_alpm(struct ata_port *ap);
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+			      size_t size);
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+					ssize_t size);
+
+
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static int ahci_port_start(struct ata_port *ap);
+static void ahci_port_stop(struct ata_port *ap);
+static void ahci_qc_prep(struct ata_queued_cmd *qc);
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
+static void ahci_freeze(struct ata_port *ap);
+static void ahci_thaw(struct ata_port *ap);
+static void ahci_enable_fbs(struct ata_port *ap);
+static void ahci_disable_fbs(struct ata_port *ap);
+static void ahci_pmp_attach(struct ata_port *ap);
+static void ahci_pmp_detach(struct ata_port *ap);
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline);
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline);
+static void ahci_postreset(struct ata_link *link, unsigned int *class);
+static void ahci_error_handler(struct ata_port *ap);
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
+static int ahci_port_resume(struct ata_port *ap);
+static void ahci_dev_config(struct ata_device *dev);
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+			       u32 opts);
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
+#endif
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
+static ssize_t ahci_activity_store(struct ata_device *dev,
+				   enum sw_activity val);
+static void ahci_init_sw_activity(struct ata_link *link);
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+				   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_cap2(struct device *dev,
+				   struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_host_version(struct device *dev,
+				      struct device_attribute *attr, char *buf);
+static ssize_t ahci_show_port_cmd(struct device *dev,
+				  struct device_attribute *attr, char *buf);
+
+static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
+static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
+static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
+static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
+
+static struct device_attribute *ahci_shost_attrs[] = {
+	&dev_attr_link_power_management_policy,
+	&dev_attr_em_message_type,
+	&dev_attr_em_message,
+	&dev_attr_ahci_host_caps,
+	&dev_attr_ahci_host_cap2,
+	&dev_attr_ahci_host_version,
+	&dev_attr_ahci_port_cmd,
+	NULL
+};
+
+static struct device_attribute *ahci_sdev_attrs[] = {
+	&dev_attr_sw_activity,
+	&dev_attr_unload_heads,
+	NULL
+};
+
+struct scsi_host_template ahci_sht = {
+	ATA_NCQ_SHT("ahci"),
+	.can_queue		= AHCI_MAX_CMDS - 1,
+	.sg_tablesize		= AHCI_MAX_SG,
+	.dma_boundary		= AHCI_DMA_BOUNDARY,
+	.shost_attrs		= ahci_shost_attrs,
+	.sdev_attrs		= ahci_sdev_attrs,
+};
+EXPORT_SYMBOL_GPL(ahci_sht);
+
+struct ata_port_operations ahci_ops = {
+	.inherits		= &sata_pmp_port_ops,
+
+	.qc_defer		= ahci_pmp_qc_defer,
+	.qc_prep		= ahci_qc_prep,
+	.qc_issue		= ahci_qc_issue,
+	.qc_fill_rtf		= ahci_qc_fill_rtf,
+
+	.freeze			= ahci_freeze,
+	.thaw			= ahci_thaw,
+	.softreset		= ahci_softreset,
+	.hardreset		= ahci_hardreset,
+	.postreset		= ahci_postreset,
+	.pmp_softreset		= ahci_softreset,
+	.error_handler		= ahci_error_handler,
+	.post_internal_cmd	= ahci_post_internal_cmd,
+	.dev_config		= ahci_dev_config,
+
+	.scr_read		= ahci_scr_read,
+	.scr_write		= ahci_scr_write,
+	.pmp_attach		= ahci_pmp_attach,
+	.pmp_detach		= ahci_pmp_detach,
+
+	.enable_pm		= ahci_enable_alpm,
+	.disable_pm		= ahci_disable_alpm,
+	.em_show		= ahci_led_show,
+	.em_store		= ahci_led_store,
+	.sw_activity_show	= ahci_activity_show,
+	.sw_activity_store	= ahci_activity_store,
+#ifdef CONFIG_PM
+	.port_suspend		= ahci_port_suspend,
+	.port_resume		= ahci_port_resume,
+#endif
+	.port_start		= ahci_port_start,
+	.port_stop		= ahci_port_stop,
+};
+EXPORT_SYMBOL_GPL(ahci_ops);
+
+int ahci_em_messages = 1;
+EXPORT_SYMBOL_GPL(ahci_em_messages);
+module_param(ahci_em_messages, int, 0444);
+/* add other LED protocol types when they become supported */
+MODULE_PARM_DESC(ahci_em_messages,
+	"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
+
+static void ahci_enable_ahci(void __iomem *mmio)
+{
+	int i;
+	u32 tmp;
+
+	/* turn on AHCI_EN */
+	tmp = readl(mmio + HOST_CTL);
+	if (tmp & HOST_AHCI_EN)
+		return;
+
+	/* Some controllers need AHCI_EN to be written multiple times.
+	 * Try a few times before giving up.
+	 */
+	for (i = 0; i < 5; i++) {
+		tmp |= HOST_AHCI_EN;
+		writel(tmp, mmio + HOST_CTL);
+		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
+		if (tmp & HOST_AHCI_EN)
+			return;
+		msleep(10);
+	}
+
+	WARN_ON(1);
+}
+
+static ssize_t ahci_show_host_caps(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	return sprintf(buf, "%x\n", hpriv->cap);
+}
+
+static ssize_t ahci_show_host_cap2(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	return sprintf(buf, "%x\n", hpriv->cap2);
+}
+
+static ssize_t ahci_show_host_version(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
+}
+
+static ssize_t ahci_show_port_cmd(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	void __iomem *port_mmio = ahci_port_base(ap);
+
+	return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
+}
+
+/**
+ *	ahci_save_initial_config - Save and fixup initial config values
+ *	@dev: target AHCI device
+ *	@hpriv: host private area to store config values
+ *	@force_port_map: force port map to a specified value
+ *	@mask_port_map: mask out particular bits from port map
+ *
+ *	Some registers containing configuration info might be setup by
+ *	BIOS and might be cleared on reset.  This function saves the
+ *	initial values of those registers into @hpriv such that they
+ *	can be restored after controller reset.
+ *
+ *	If inconsistent, config values are fixed up by this function.
+ *
+ *	LOCKING:
+ *	None.
+ */
+void ahci_save_initial_config(struct device *dev,
+			      struct ahci_host_priv *hpriv,
+			      unsigned int force_port_map,
+			      unsigned int mask_port_map)
+{
+	void __iomem *mmio = hpriv->mmio;
+	u32 cap, cap2, vers, port_map;
+	int i;
+
+	/* make sure AHCI mode is enabled before accessing CAP */
+	ahci_enable_ahci(mmio);
+
+	/* Values prefixed with saved_ are written back to host after
+	 * reset.  Values without are used for driver operation.
+	 */
+	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
+	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
+
+	/* CAP2 register is only defined for AHCI 1.2 and later */
+	vers = readl(mmio + HOST_VERSION);
+	if ((vers >> 16) > 1 ||
+	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
+		hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
+	else
+		hpriv->saved_cap2 = cap2 = 0;
+
+	/* some chips have errata preventing 64bit use */
+	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do 64bit DMA, forcing 32bit\n");
+		cap &= ~HOST_CAP_64;
+	}
+
+	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do NCQ, turning off CAP_NCQ\n");
+		cap &= ~HOST_CAP_NCQ;
+	}
+
+	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can do NCQ, turning on CAP_NCQ\n");
+		cap |= HOST_CAP_NCQ;
+	}
+
+	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do PMP, turning off CAP_PMP\n");
+		cap &= ~HOST_CAP_PMP;
+	}
+
+	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
+		dev_printk(KERN_INFO, dev,
+			   "controller can't do SNTF, turning off CAP_SNTF\n");
+		cap &= ~HOST_CAP_SNTF;
+	}
+
+	if (force_port_map && port_map != force_port_map) {
+		dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
+			   port_map, force_port_map);
+		port_map = force_port_map;
+	}
+
+	if (mask_port_map) {
+		dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
+			   port_map,
+			   port_map & mask_port_map);
+		port_map &= mask_port_map;
+	}
+
+	/* cross check port_map and cap.n_ports */
+	if (port_map) {
+		int map_ports = 0;
+
+		for (i = 0; i < AHCI_MAX_PORTS; i++)
+			if (port_map & (1 << i))
+				map_ports++;
+
+		/* If PI has more ports than n_ports, whine, clear
+		 * port_map and let it be generated from n_ports.
+		 */
+		if (map_ports > ahci_nr_ports(cap)) {
+			dev_printk(KERN_WARNING, dev,
+				   "implemented port map (0x%x) contains more "
+				   "ports than nr_ports (%u), using nr_ports\n",
+				   port_map, ahci_nr_ports(cap));
+			port_map = 0;
+		}
+	}
+
+	/* fabricate port_map from cap.nr_ports */
+	if (!port_map) {
+		port_map = (1 << ahci_nr_ports(cap)) - 1;
+		dev_printk(KERN_WARNING, dev,
+			   "forcing PORTS_IMPL to 0x%x\n", port_map);
+
+		/* write the fixed up value to the PI register */
+		hpriv->saved_port_map = port_map;
+	}
+
+	/* record values to use during operation */
+	hpriv->cap = cap;
+	hpriv->cap2 = cap2;
+	hpriv->port_map = port_map;
+}
+EXPORT_SYMBOL_GPL(ahci_save_initial_config);
+
+/**
+ *	ahci_restore_initial_config - Restore initial config
+ *	@host: target ATA host
+ *
+ *	Restore initial config stored by ahci_save_initial_config().
+ *
+ *	LOCKING:
+ *	None.
+ */
+static void ahci_restore_initial_config(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+
+	writel(hpriv->saved_cap, mmio + HOST_CAP);
+	if (hpriv->saved_cap2)
+		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
+	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
+	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
+}
+
+static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
+{
+	static const int offset[] = {
+		[SCR_STATUS]		= PORT_SCR_STAT,
+		[SCR_CONTROL]		= PORT_SCR_CTL,
+		[SCR_ERROR]		= PORT_SCR_ERR,
+		[SCR_ACTIVE]		= PORT_SCR_ACT,
+		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
+	};
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	if (sc_reg < ARRAY_SIZE(offset) &&
+	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
+		return offset[sc_reg];
+	return 0;
+}
+
+static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	int offset = ahci_scr_offset(link->ap, sc_reg);
+
+	if (offset) {
+		*val = readl(port_mmio + offset);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	int offset = ahci_scr_offset(link->ap, sc_reg);
+
+	if (offset) {
+		writel(val, port_mmio + offset);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+void ahci_start_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/* start DMA */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_START;
+	writel(tmp, port_mmio + PORT_CMD);
+	readl(port_mmio + PORT_CMD); /* flush */
+}
+EXPORT_SYMBOL_GPL(ahci_start_engine);
+
+int ahci_stop_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	tmp = readl(port_mmio + PORT_CMD);
+
+	/* check if the HBA is idle */
+	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
+		return 0;
+
+	/* setting HBA to idle */
+	tmp &= ~PORT_CMD_START;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* wait for engine to stop. This could be as long as 500 msec */
+	tmp = ata_wait_register(port_mmio + PORT_CMD,
+				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
+	if (tmp & PORT_CMD_LIST_ON)
+		return -EIO;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_stop_engine);
+
+static void ahci_start_fis_rx(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 tmp;
+
+	/* set FIS registers */
+	if (hpriv->cap & HOST_CAP_64)
+		writel((pp->cmd_slot_dma >> 16) >> 16,
+		       port_mmio + PORT_LST_ADDR_HI);
+	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
+
+	if (hpriv->cap & HOST_CAP_64)
+		writel((pp->rx_fis_dma >> 16) >> 16,
+		       port_mmio + PORT_FIS_ADDR_HI);
+	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
+
+	/* enable FIS reception */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_FIS_RX;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* flush */
+	readl(port_mmio + PORT_CMD);
+}
+
+static int ahci_stop_fis_rx(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/* disable FIS reception */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp &= ~PORT_CMD_FIS_RX;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	/* wait for completion, spec says 500ms, give it 1000 */
+	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
+				PORT_CMD_FIS_ON, 10, 1000);
+	if (tmp & PORT_CMD_FIS_ON)
+		return -EBUSY;
+
+	return 0;
+}
+
+static void ahci_power_up(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+
+	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+
+	/* spin up device */
+	if (hpriv->cap & HOST_CAP_SSS) {
+		cmd |= PORT_CMD_SPIN_UP;
+		writel(cmd, port_mmio + PORT_CMD);
+	}
+
+	/* wake up link */
+	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
+}
+
+static void ahci_disable_alpm(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* IPM bits should be disabled by libata-core */
+	/* get the existing command bits */
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* disable ALPM and ASP */
+	cmd &= ~PORT_CMD_ASP;
+	cmd &= ~PORT_CMD_ALPE;
+
+	/* force the interface back to active */
+	cmd |= PORT_CMD_ICC_ACTIVE;
+
+	/* write out new cmd value */
+	writel(cmd, port_mmio + PORT_CMD);
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* wait 10ms to be sure we've come out of any low power state */
+	msleep(10);
+
+	/* clear out any PhyRdy stuff from interrupt status */
+	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
+
+	/* go ahead and clean out PhyRdy Change from Serror too */
+	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+
+	/*
+	 * Clear flag to indicate that we should ignore all PhyRdy
+	 * state changes
+	 */
+	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
+
+	/*
+	 * Enable interrupts on Phy Ready.
+	 */
+	pp->intr_mask |= PORT_IRQ_PHYRDY;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+	/*
+	 * don't change the link pm policy - we can be called
+	 * just to turn of link pm temporarily
+	 */
+}
+
+static int ahci_enable_alpm(struct ata_port *ap,
+	enum link_pm policy)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd;
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 asp;
+
+	/* Make sure the host is capable of link power management */
+	if (!(hpriv->cap & HOST_CAP_ALPM))
+		return -EINVAL;
+
+	switch (policy) {
+	case MAX_PERFORMANCE:
+	case NOT_AVAILABLE:
+		/*
+		 * if we came here with NOT_AVAILABLE,
+		 * it just means this is the first time we
+		 * have tried to enable - default to max performance,
+		 * and let the user go to lower power modes on request.
+		 */
+		ahci_disable_alpm(ap);
+		return 0;
+	case MIN_POWER:
+		/* configure HBA to enter SLUMBER */
+		asp = PORT_CMD_ASP;
+		break;
+	case MEDIUM_POWER:
+		/* configure HBA to enter PARTIAL */
+		asp = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * Disable interrupts on Phy Ready. This keeps us from
+	 * getting woken up due to spurious phy ready interrupts
+	 * TBD - Hot plug should be done via polling now, is
+	 * that even supported?
+	 */
+	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+
+	/*
+	 * Set a flag to indicate that we should ignore all PhyRdy
+	 * state changes since these can happen now whenever we
+	 * change link state
+	 */
+	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
+
+	/* get the existing command bits */
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/*
+	 * Set ASP based on Policy
+	 */
+	cmd |= asp;
+
+	/*
+	 * Setting this bit will instruct the HBA to aggressively
+	 * enter a lower power link state when it's appropriate and
+	 * based on the value set above for ASP
+	 */
+	cmd |= PORT_CMD_ALPE;
+
+	/* write out new cmd value */
+	writel(cmd, port_mmio + PORT_CMD);
+	cmd = readl(port_mmio + PORT_CMD);
+
+	/* IPM bits should be set by libata-core */
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static void ahci_power_down(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 cmd, scontrol;
+
+	if (!(hpriv->cap & HOST_CAP_SSS))
+		return;
+
+	/* put device into listen mode, first set PxSCTL.DET to 0 */
+	scontrol = readl(port_mmio + PORT_SCR_CTL);
+	scontrol &= ~0xf;
+	writel(scontrol, port_mmio + PORT_SCR_CTL);
+
+	/* then set PxCMD.SUD to 0 */
+	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
+	cmd &= ~PORT_CMD_SPIN_UP;
+	writel(cmd, port_mmio + PORT_CMD);
+}
+#endif
+
+static void ahci_start_port(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_link *link;
+	struct ahci_em_priv *emp;
+	ssize_t rc;
+	int i;
+
+	/* enable FIS reception */
+	ahci_start_fis_rx(ap);
+
+	/* enable DMA */
+	ahci_start_engine(ap);
+
+	/* turn on LEDs */
+	if (ap->flags & ATA_FLAG_EM) {
+		ata_for_each_link(link, ap, EDGE) {
+			emp = &pp->em_priv[link->pmp];
+
+			/* EM Transmit bit maybe busy during init */
+			for (i = 0; i < EM_MAX_RETRY; i++) {
+				rc = ahci_transmit_led_message(ap,
+							       emp->led_state,
+							       4);
+				if (rc == -EBUSY)
+					msleep(1);
+				else
+					break;
+			}
+		}
+	}
+
+	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
+		ata_for_each_link(link, ap, EDGE)
+			ahci_init_sw_activity(link);
+
+}
+
+static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
+{
+	int rc;
+
+	/* disable DMA */
+	rc = ahci_stop_engine(ap);
+	if (rc) {
+		*emsg = "failed to stop engine";
+		return rc;
+	}
+
+	/* disable FIS reception */
+	rc = ahci_stop_fis_rx(ap);
+	if (rc) {
+		*emsg = "failed stop FIS RX";
+		return rc;
+	}
+
+	return 0;
+}
+
+int ahci_reset_controller(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 tmp;
+
+	/* we must be in AHCI mode, before using anything
+	 * AHCI-specific, such as HOST_RESET.
+	 */
+	ahci_enable_ahci(mmio);
+
+	/* global controller reset */
+	if (!ahci_skip_host_reset) {
+		tmp = readl(mmio + HOST_CTL);
+		if ((tmp & HOST_RESET) == 0) {
+			writel(tmp | HOST_RESET, mmio + HOST_CTL);
+			readl(mmio + HOST_CTL); /* flush */
+		}
+
+		/*
+		 * to perform host reset, OS should set HOST_RESET
+		 * and poll until this bit is read to be "0".
+		 * reset must complete within 1 second, or
+		 * the hardware should be considered fried.
+		 */
+		tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
+					HOST_RESET, 10, 1000);
+
+		if (tmp & HOST_RESET) {
+			dev_printk(KERN_ERR, host->dev,
+				   "controller reset failed (0x%x)\n", tmp);
+			return -EIO;
+		}
+
+		/* turn on AHCI mode */
+		ahci_enable_ahci(mmio);
+
+		/* Some registers might be cleared on reset.  Restore
+		 * initial values.
+		 */
+		ahci_restore_initial_config(host);
+	} else
+		dev_printk(KERN_INFO, host->dev,
+			   "skipping global host reset\n");
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_controller);
+
+static void ahci_sw_activity(struct ata_link *link)
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
+		return;
+
+	emp->activity++;
+	if (!timer_pending(&emp->timer))
+		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
+}
+
+static void ahci_sw_activity_blink(unsigned long arg)
+{
+	struct ata_link *link = (struct ata_link *)arg;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+	unsigned long led_message = emp->led_state;
+	u32 activity_led_state;
+	unsigned long flags;
+
+	led_message &= EM_MSG_LED_VALUE;
+	led_message |= ap->port_no | (link->pmp << 8);
+
+	/* check to see if we've had activity.  If so,
+	 * toggle state of LED and reset timer.  If not,
+	 * turn LED to desired idle state.
+	 */
+	spin_lock_irqsave(ap->lock, flags);
+	if (emp->saved_activity != emp->activity) {
+		emp->saved_activity = emp->activity;
+		/* get the current LED state */
+		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
+
+		if (activity_led_state)
+			activity_led_state = 0;
+		else
+			activity_led_state = 1;
+
+		/* clear old state */
+		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+		/* toggle state */
+		led_message |= (activity_led_state << 16);
+		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
+	} else {
+		/* switch to idle */
+		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
+		if (emp->blink_policy == BLINK_OFF)
+			led_message |= (1 << 16);
+	}
+	spin_unlock_irqrestore(ap->lock, flags);
+	ahci_transmit_led_message(ap, led_message, 4);
+}
+
+static void ahci_init_sw_activity(struct ata_link *link)
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	/* init activity stats, setup timer */
+	emp->saved_activity = emp->activity = 0;
+	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
+
+	/* check our blink policy and set flag for link if it's enabled */
+	if (emp->blink_policy)
+		link->flags |= ATA_LFLAG_SW_ACTIVITY;
+}
+
+int ahci_reset_em(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_ctl;
+
+	em_ctl = readl(mmio + HOST_EM_CTL);
+	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
+		return -EINVAL;
+
+	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ahci_reset_em);
+
+static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
+					ssize_t size)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_ctl;
+	u32 message[] = {0, 0};
+	unsigned long flags;
+	int pmp;
+	struct ahci_em_priv *emp;
+
+	/* get the slot number from the message */
+	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+	if (pmp < EM_MAX_SLOTS)
+		emp = &pp->em_priv[pmp];
+	else
+		return -EINVAL;
+
+	spin_lock_irqsave(ap->lock, flags);
+
+	/*
+	 * if we are still busy transmitting a previous message,
+	 * do not allow
+	 */
+	em_ctl = readl(mmio + HOST_EM_CTL);
+	if (em_ctl & EM_CTL_TM) {
+		spin_unlock_irqrestore(ap->lock, flags);
+		return -EBUSY;
+	}
+
+	/*
+	 * create message header - this is all zero except for
+	 * the message size, which is 4 bytes.
+	 */
+	message[0] |= (4 << 8);
+
+	/* ignore 0:4 of byte zero, fill in port info yourself */
+	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
+
+	/* write message to EM_LOC */
+	writel(message[0], mmio + hpriv->em_loc);
+	writel(message[1], mmio + hpriv->em_loc+4);
+
+	/* save off new led state for port/slot */
+	emp->led_state = state;
+
+	/*
+	 * tell hardware to transmit the message
+	 */
+	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
+
+	spin_unlock_irqrestore(ap->lock, flags);
+	return size;
+}
+
+static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_link *link;
+	struct ahci_em_priv *emp;
+	int rc = 0;
+
+	ata_for_each_link(link, ap, EDGE) {
+		emp = &pp->em_priv[link->pmp];
+		rc += sprintf(buf, "%lx\n", emp->led_state);
+	}
+	return rc;
+}
+
+static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
+				size_t size)
+{
+	int state;
+	int pmp;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp;
+
+	state = simple_strtoul(buf, NULL, 0);
+
+	/* get the slot number from the message */
+	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
+	if (pmp < EM_MAX_SLOTS)
+		emp = &pp->em_priv[pmp];
+	else
+		return -EINVAL;
+
+	/* mask off the activity bits if we are in sw_activity
+	 * mode, user should turn off sw_activity before setting
+	 * activity led through em_message
+	 */
+	if (emp->blink_policy)
+		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
+
+	return ahci_transmit_led_message(ap, state, size);
+}
+
+static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
+{
+	struct ata_link *link = dev->link;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+	u32 port_led_state = emp->led_state;
+
+	/* save the desired Activity LED behavior */
+	if (val == OFF) {
+		/* clear LFLAG */
+		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
+
+		/* set the LED to OFF */
+		port_led_state &= EM_MSG_LED_VALUE_OFF;
+		port_led_state |= (ap->port_no | (link->pmp << 8));
+		ahci_transmit_led_message(ap, port_led_state, 4);
+	} else {
+		link->flags |= ATA_LFLAG_SW_ACTIVITY;
+		if (val == BLINK_OFF) {
+			/* set LED to ON for idle */
+			port_led_state &= EM_MSG_LED_VALUE_OFF;
+			port_led_state |= (ap->port_no | (link->pmp << 8));
+			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
+			ahci_transmit_led_message(ap, port_led_state, 4);
+		}
+	}
+	emp->blink_policy = val;
+	return 0;
+}
+
+static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
+{
+	struct ata_link *link = dev->link;
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
+
+	/* display the saved value of activity behavior for this
+	 * disk.
+	 */
+	return sprintf(buf, "%d\n", emp->blink_policy);
+}
+
+static void ahci_port_init(struct device *dev, struct ata_port *ap,
+			   int port_no, void __iomem *mmio,
+			   void __iomem *port_mmio)
+{
+	const char *emsg = NULL;
+	int rc;
+	u32 tmp;
+
+	/* make sure port is not active */
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc)
+		dev_warn(dev, "%s (%d)\n", emsg, rc);
+
+	/* clear SError */
+	tmp = readl(port_mmio + PORT_SCR_ERR);
+	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
+	writel(tmp, port_mmio + PORT_SCR_ERR);
+
+	/* clear port IRQ */
+	tmp = readl(port_mmio + PORT_IRQ_STAT);
+	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+	if (tmp)
+		writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+	writel(1 << port_no, mmio + HOST_IRQ_STAT);
+}
+
+void ahci_init_controller(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	int i;
+	void __iomem *port_mmio;
+	u32 tmp;
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		port_mmio = ahci_port_base(ap);
+		if (ata_port_is_dummy(ap))
+			continue;
+
+		ahci_port_init(host->dev, ap, i, mmio, port_mmio);
+	}
+
+	tmp = readl(mmio + HOST_CTL);
+	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
+	tmp = readl(mmio + HOST_CTL);
+	VPRINTK("HOST_CTL 0x%x\n", tmp);
+}
+EXPORT_SYMBOL_GPL(ahci_init_controller);
+
+static void ahci_dev_config(struct ata_device *dev)
+{
+	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
+
+	if (hpriv->flags & AHCI_HFLAG_SECT255) {
+		dev->max_sectors = 255;
+		ata_dev_printk(dev, KERN_INFO,
+			       "SB600 AHCI: limiting to 255 sectors per cmd\n");
+	}
+}
+
+static unsigned int ahci_dev_classify(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ata_taskfile tf;
+	u32 tmp;
+
+	tmp = readl(port_mmio + PORT_SIG);
+	tf.lbah		= (tmp >> 24)	& 0xff;
+	tf.lbam		= (tmp >> 16)	& 0xff;
+	tf.lbal		= (tmp >> 8)	& 0xff;
+	tf.nsect	= (tmp)		& 0xff;
+
+	return ata_dev_classify(&tf);
+}
+
+static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+			       u32 opts)
+{
+	dma_addr_t cmd_tbl_dma;
+
+	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
+
+	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
+	pp->cmd_slot[tag].status = 0;
+	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
+	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
+}
+
+int ahci_kick_engine(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+	u32 tmp;
+	int busy, rc;
+
+	/* stop engine */
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		goto out_restart;
+
+	/* need to do CLO?
+	 * always do CLO if PMP is attached (AHCI-1.3 9.2)
+	 */
+	busy = status & (ATA_BUSY | ATA_DRQ);
+	if (!busy && !sata_pmp_attached(ap)) {
+		rc = 0;
+		goto out_restart;
+	}
+
+	if (!(hpriv->cap & HOST_CAP_CLO)) {
+		rc = -EOPNOTSUPP;
+		goto out_restart;
+	}
+
+	/* perform CLO */
+	tmp = readl(port_mmio + PORT_CMD);
+	tmp |= PORT_CMD_CLO;
+	writel(tmp, port_mmio + PORT_CMD);
+
+	rc = 0;
+	tmp = ata_wait_register(port_mmio + PORT_CMD,
+				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
+	if (tmp & PORT_CMD_CLO)
+		rc = -EIO;
+
+	/* restart engine */
+ out_restart:
+	ahci_start_engine(ap);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(ahci_kick_engine);
+
+static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+				struct ata_taskfile *tf, int is_cmd, u16 flags,
+				unsigned long timeout_msec)
+{
+	const u32 cmd_fis_len = 5; /* five dwords */
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u8 *fis = pp->cmd_tbl;
+	u32 tmp;
+
+	/* prep the command */
+	ata_tf_to_fis(tf, pmp, is_cmd, fis);
+	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
+
+	/* issue & wait */
+	writel(1, port_mmio + PORT_CMD_ISSUE);
+
+	if (timeout_msec) {
+		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
+					1, timeout_msec);
+		if (tmp & 0x1) {
+			ahci_kick_engine(ap);
+			return -EBUSY;
+		}
+	} else
+		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
+
+	return 0;
+}
+
+int ahci_do_softreset(struct ata_link *link, unsigned int *class,
+		      int pmp, unsigned long deadline,
+		      int (*check_ready)(struct ata_link *link))
+{
+	struct ata_port *ap = link->ap;
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	const char *reason = NULL;
+	unsigned long now, msecs;
+	struct ata_taskfile tf;
+	int rc;
+
+	DPRINTK("ENTER\n");
+
+	/* prepare for SRST (AHCI-1.1 10.4.1) */
+	rc = ahci_kick_engine(ap);
+	if (rc && rc != -EOPNOTSUPP)
+		ata_link_printk(link, KERN_WARNING,
+				"failed to reset engine (errno=%d)\n", rc);
+
+	ata_tf_init(link->device, &tf);
+
+	/* issue the first D2H Register FIS */
+	msecs = 0;
+	now = jiffies;
+	if (time_after(now, deadline))
+		msecs = jiffies_to_msecs(deadline - now);
+
+	tf.ctl |= ATA_SRST;
+	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
+				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
+		rc = -EIO;
+		reason = "1st FIS failed";
+		goto fail;
+	}
+
+	/* spec says at least 5us, but be generous and sleep for 1ms */
+	msleep(1);
+
+	/* issue the second D2H Register FIS */
+	tf.ctl &= ~ATA_SRST;
+	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
+
+	/* wait for link to become ready */
+	rc = ata_wait_after_reset(link, deadline, check_ready);
+	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
+		/*
+		 * Workaround for cases where link online status can't
+		 * be trusted.  Treat device readiness timeout as link
+		 * offline.
+		 */
+		ata_link_printk(link, KERN_INFO,
+				"device not ready, treating as offline\n");
+		*class = ATA_DEV_NONE;
+	} else if (rc) {
+		/* link occupied, -ENODEV too is an error */
+		reason = "device not ready";
+		goto fail;
+	} else
+		*class = ahci_dev_classify(ap);
+
+	DPRINTK("EXIT, class=%u\n", *class);
+	return 0;
+
+ fail:
+	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
+	return rc;
+}
+
+int ahci_check_ready(struct ata_link *link)
+{
+	void __iomem *port_mmio = ahci_port_base(link->ap);
+	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
+
+	return ata_check_ready(status);
+}
+EXPORT_SYMBOL_GPL(ahci_check_ready);
+
+static int ahci_softreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline)
+{
+	int pmp = sata_srst_pmp(link);
+
+	DPRINTK("ENTER\n");
+
+	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+}
+EXPORT_SYMBOL_GPL(ahci_do_softreset);
+
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+			  unsigned long deadline)
+{
+	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	struct ata_port *ap = link->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+	struct ata_taskfile tf;
+	bool online;
+	int rc;
+
+	DPRINTK("ENTER\n");
+
+	ahci_stop_engine(ap);
+
+	/* clear D2H reception area to properly wait for D2H FIS */
+	ata_tf_init(link->device, &tf);
+	tf.command = 0x80;
+	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+
+	rc = sata_link_hardreset(link, timing, deadline, &online,
+				 ahci_check_ready);
+
+	ahci_start_engine(ap);
+
+	if (online)
+		*class = ahci_dev_classify(ap);
+
+	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
+	return rc;
+}
+
+static void ahci_postreset(struct ata_link *link, unsigned int *class)
+{
+	struct ata_port *ap = link->ap;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 new_tmp, tmp;
+
+	ata_std_postreset(link, class);
+
+	/* Make sure port's ATAPI bit is set appropriately */
+	new_tmp = tmp = readl(port_mmio + PORT_CMD);
+	if (*class == ATA_DEV_ATAPI)
+		new_tmp |= PORT_CMD_ATAPI;
+	else
+		new_tmp &= ~PORT_CMD_ATAPI;
+	if (new_tmp != tmp) {
+		writel(new_tmp, port_mmio + PORT_CMD);
+		readl(port_mmio + PORT_CMD); /* flush */
+	}
+}
+
+static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
+{
+	struct scatterlist *sg;
+	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
+	unsigned int si;
+
+	VPRINTK("ENTER\n");
+
+	/*
+	 * Next, the S/G list.
+	 */
+	for_each_sg(qc->sg, sg, qc->n_elem, si) {
+		dma_addr_t addr = sg_dma_address(sg);
+		u32 sg_len = sg_dma_len(sg);
+
+		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
+		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
+		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
+	}
+
+	return si;
+}
+
+static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	if (!sata_pmp_attached(ap) || pp->fbs_enabled)
+		return ata_std_qc_defer(qc);
+	else
+		return sata_pmp_qc_defer_cmd_switch(qc);
+}
+
+static void ahci_qc_prep(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ahci_port_priv *pp = ap->private_data;
+	int is_atapi = ata_is_atapi(qc->tf.protocol);
+	void *cmd_tbl;
+	u32 opts;
+	const u32 cmd_fis_len = 5; /* five dwords */
+	unsigned int n_elem;
+
+	/*
+	 * Fill in command table information.  First, the header,
+	 * a SATA Register - Host to Device command FIS.
+	 */
+	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
+
+	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
+	if (is_atapi) {
+		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
+		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
+	}
+
+	n_elem = 0;
+	if (qc->flags & ATA_QCFLAG_DMAMAP)
+		n_elem = ahci_fill_sg(qc, cmd_tbl);
+
+	/*
+	 * Fill in command slot information.
+	 */
+	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
+	if (qc->tf.flags & ATA_TFLAG_WRITE)
+		opts |= AHCI_CMD_WRITE;
+	if (is_atapi)
+		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
+
+	ahci_fill_cmd_slot(pp, qc->tag, opts);
+}
+
+static void ahci_fbs_dec_intr(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs = readl(port_mmio + PORT_FBS);
+	int retries = 3;
+
+	DPRINTK("ENTER\n");
+	BUG_ON(!pp->fbs_enabled);
+
+	/* time to wait for DEC is not specified by AHCI spec,
+	 * add a retry loop for safety.
+	 */
+	writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	while ((fbs & PORT_FBS_DEC) && retries--) {
+		udelay(1);
+		fbs = readl(port_mmio + PORT_FBS);
+	}
+
+	if (fbs & PORT_FBS_DEC)
+		dev_printk(KERN_ERR, ap->host->dev,
+			   "failed to clear device error\n");
+}
+
+static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ata_eh_info *host_ehi = &ap->link.eh_info;
+	struct ata_link *link = NULL;
+	struct ata_queued_cmd *active_qc;
+	struct ata_eh_info *active_ehi;
+	bool fbs_need_dec = false;
+	u32 serror;
+
+	/* determine active link with error */
+	if (pp->fbs_enabled) {
+		void __iomem *port_mmio = ahci_port_base(ap);
+		u32 fbs = readl(port_mmio + PORT_FBS);
+		int pmp = fbs >> PORT_FBS_DWE_OFFSET;
+
+		if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
+		    ata_link_online(&ap->pmp_link[pmp])) {
+			link = &ap->pmp_link[pmp];
+			fbs_need_dec = true;
+		}
+
+	} else
+		ata_for_each_link(link, ap, EDGE)
+			if (ata_link_active(link))
+				break;
+
+	if (!link)
+		link = &ap->link;
+
+	active_qc = ata_qc_from_tag(ap, link->active_tag);
+	active_ehi = &link->eh_info;
+
+	/* record irq stat */
+	ata_ehi_clear_desc(host_ehi);
+	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
+
+	/* AHCI needs SError cleared; otherwise, it might lock up */
+	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
+	ahci_scr_write(&ap->link, SCR_ERROR, serror);
+	host_ehi->serror |= serror;
+
+	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
+	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
+		irq_stat &= ~PORT_IRQ_IF_ERR;
+
+	if (irq_stat & PORT_IRQ_TF_ERR) {
+		/* If qc is active, charge it; otherwise, the active
+		 * link.  There's no active qc on NCQ errors.  It will
+		 * be determined by EH by reading log page 10h.
+		 */
+		if (active_qc)
+			active_qc->err_mask |= AC_ERR_DEV;
+		else
+			active_ehi->err_mask |= AC_ERR_DEV;
+
+		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
+			host_ehi->serror &= ~SERR_INTERNAL;
+	}
+
+	if (irq_stat & PORT_IRQ_UNK_FIS) {
+		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
+
+		active_ehi->err_mask |= AC_ERR_HSM;
+		active_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(active_ehi,
+				  "unknown FIS %08x %08x %08x %08x" ,
+				  unk[0], unk[1], unk[2], unk[3]);
+	}
+
+	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
+		active_ehi->err_mask |= AC_ERR_HSM;
+		active_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(active_ehi, "incorrect PMP");
+	}
+
+	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
+		host_ehi->err_mask |= AC_ERR_HOST_BUS;
+		host_ehi->action |= ATA_EH_RESET;
+		ata_ehi_push_desc(host_ehi, "host bus error");
+	}
+
+	if (irq_stat & PORT_IRQ_IF_ERR) {
+		if (fbs_need_dec)
+			active_ehi->err_mask |= AC_ERR_DEV;
+		else {
+			host_ehi->err_mask |= AC_ERR_ATA_BUS;
+			host_ehi->action |= ATA_EH_RESET;
+		}
+
+		ata_ehi_push_desc(host_ehi, "interface fatal error");
+	}
+
+	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
+		ata_ehi_hotplugged(host_ehi);
+		ata_ehi_push_desc(host_ehi, "%s",
+			irq_stat & PORT_IRQ_CONNECT ?
+			"connection status changed" : "PHY RDY changed");
+	}
+
+	/* okay, let's hand over to EH */
+
+	if (irq_stat & PORT_IRQ_FREEZE)
+		ata_port_freeze(ap);
+	else if (fbs_need_dec) {
+		ata_link_abort(link);
+		ahci_fbs_dec_intr(ap);
+	} else
+		ata_port_abort(ap);
+}
+
+static void ahci_port_intr(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ata_eh_info *ehi = &ap->link.eh_info;
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
+	u32 status, qc_active = 0;
+	int rc;
+
+	status = readl(port_mmio + PORT_IRQ_STAT);
+	writel(status, port_mmio + PORT_IRQ_STAT);
+
+	/* ignore BAD_PMP while resetting */
+	if (unlikely(resetting))
+		status &= ~PORT_IRQ_BAD_PMP;
+
+	/* If we are getting PhyRdy, this is
+	 * just a power state change, we should
+	 * clear out this, plus the PhyRdy/Comm
+	 * Wake bits from Serror
+	 */
+	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
+		(status & PORT_IRQ_PHYRDY)) {
+		status &= ~PORT_IRQ_PHYRDY;
+		ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
+	}
+
+	if (unlikely(status & PORT_IRQ_ERROR)) {
+		ahci_error_intr(ap, status);
+		return;
+	}
+
+	if (status & PORT_IRQ_SDB_FIS) {
+		/* If SNotification is available, leave notification
+		 * handling to sata_async_notification().  If not,
+		 * emulate it by snooping SDB FIS RX area.
+		 *
+		 * Snooping FIS RX area is probably cheaper than
+		 * poking SNotification but some constrollers which
+		 * implement SNotification, ICH9 for example, don't
+		 * store AN SDB FIS into receive area.
+		 */
+		if (hpriv->cap & HOST_CAP_SNTF)
+			sata_async_notification(ap);
+		else {
+			/* If the 'N' bit in word 0 of the FIS is set,
+			 * we just received asynchronous notification.
+			 * Tell libata about it.
+			 *
+			 * Lack of SNotification should not appear in
+			 * ahci 1.2, so the workaround is unnecessary
+			 * when FBS is enabled.
+			 */
+			if (pp->fbs_enabled)
+				WARN_ON_ONCE(1);
+			else {
+				const __le32 *f = pp->rx_fis + RX_FIS_SDB;
+				u32 f0 = le32_to_cpu(f[0]);
+				if (f0 & (1 << 15))
+					sata_async_notification(ap);
+			}
+		}
+	}
+
+	/* pp->active_link is not reliable once FBS is enabled, both
+	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
+	 * NCQ and non-NCQ commands may be in flight at the same time.
+	 */
+	if (pp->fbs_enabled) {
+		if (ap->qc_active) {
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
+		}
+	} else {
+		/* pp->active_link is valid iff any command is in flight */
+		if (ap->qc_active && pp->active_link->sactive)
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+		else
+			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+	}
+
+
+	rc = ata_qc_complete_multiple(ap, qc_active);
+
+	/* while resetting, invalid completions are expected */
+	if (unlikely(rc < 0 && !resetting)) {
+		ehi->err_mask |= AC_ERR_HSM;
+		ehi->action |= ATA_EH_RESET;
+		ata_port_freeze(ap);
+	}
+}
+
+irqreturn_t ahci_interrupt(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct ahci_host_priv *hpriv;
+	unsigned int i, handled = 0;
+	void __iomem *mmio;
+	u32 irq_stat, irq_masked;
+
+	VPRINTK("ENTER\n");
+
+	hpriv = host->private_data;
+	mmio = hpriv->mmio;
+
+	/* sigh.  0xffffffff is a valid return from h/w */
+	irq_stat = readl(mmio + HOST_IRQ_STAT);
+	if (!irq_stat)
+		return IRQ_NONE;
+
+	irq_masked = irq_stat & hpriv->port_map;
+
+	spin_lock(&host->lock);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap;
+
+		if (!(irq_masked & (1 << i)))
+			continue;
+
+		ap = host->ports[i];
+		if (ap) {
+			ahci_port_intr(ap);
+			VPRINTK("port %u\n", i);
+		} else {
+			VPRINTK("port %u (no irq)\n", i);
+			if (ata_ratelimit())
+				dev_printk(KERN_WARNING, host->dev,
+					"interrupt on disabled port %u\n", i);
+		}
+
+		handled = 1;
+	}
+
+	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
+	 * it should be cleared after all the port events are cleared;
+	 * otherwise, it will raise a spurious interrupt after each
+	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
+	 * information.
+	 *
+	 * Also, use the unmasked value to clear interrupt as spurious
+	 * pending event on a dummy port might cause screaming IRQ.
+	 */
+	writel(irq_stat, mmio + HOST_IRQ_STAT);
+
+	spin_unlock(&host->lock);
+
+	VPRINTK("EXIT\n");
+
+	return IRQ_RETVAL(handled);
+}
+EXPORT_SYMBOL_GPL(ahci_interrupt);
+
+static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* Keep track of the currently active link.  It will be used
+	 * in completion path to determine whether NCQ phase is in
+	 * progress.
+	 */
+	pp->active_link = qc->dev->link;
+
+	if (qc->tf.protocol == ATA_PROT_NCQ)
+		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
+
+	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
+		u32 fbs = readl(port_mmio + PORT_FBS);
+		fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
+		fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
+		writel(fbs, port_mmio + PORT_FBS);
+		pp->fbs_last_dev = qc->dev->link->pmp;
+	}
+
+	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
+
+	ahci_sw_activity(qc->dev->link);
+
+	return 0;
+}
+
+static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+{
+	struct ahci_port_priv *pp = qc->ap->private_data;
+	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+
+	if (pp->fbs_enabled)
+		d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
+
+	ata_tf_from_fis(d2h_fis, &qc->result_tf);
+	return true;
+}
+
+static void ahci_freeze(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+
+	/* turn IRQ off */
+	writel(0, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_thaw(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+	struct ahci_port_priv *pp = ap->private_data;
+
+	/* clear IRQ */
+	tmp = readl(port_mmio + PORT_IRQ_STAT);
+	writel(tmp, port_mmio + PORT_IRQ_STAT);
+	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
+
+	/* turn IRQ back on */
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_error_handler(struct ata_port *ap)
+{
+	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+		/* restart engine */
+		ahci_stop_engine(ap);
+		ahci_start_engine(ap);
+	}
+
+	sata_pmp_error_handler(ap);
+}
+
+static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+
+	/* make DMA engine forget about the failed command */
+	if (qc->flags & ATA_QCFLAG_FAILED)
+		ahci_kick_engine(ap);
+}
+
+static void ahci_enable_fbs(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs;
+	int rc;
+
+	if (!pp->fbs_supported)
+		return;
+
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN) {
+		pp->fbs_enabled = true;
+		pp->fbs_last_dev = -1; /* initialization */
+		return;
+	}
+
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		return;
+
+	writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN) {
+		dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
+		pp->fbs_enabled = true;
+		pp->fbs_last_dev = -1; /* initialization */
+	} else
+		dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
+
+	ahci_start_engine(ap);
+}
+
+static void ahci_disable_fbs(struct ata_port *ap)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 fbs;
+	int rc;
+
+	if (!pp->fbs_supported)
+		return;
+
+	fbs = readl(port_mmio + PORT_FBS);
+	if ((fbs & PORT_FBS_EN) == 0) {
+		pp->fbs_enabled = false;
+		return;
+	}
+
+	rc = ahci_stop_engine(ap);
+	if (rc)
+		return;
+
+	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
+	fbs = readl(port_mmio + PORT_FBS);
+	if (fbs & PORT_FBS_EN)
+		dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
+	else {
+		dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
+		pp->fbs_enabled = false;
+	}
+
+	ahci_start_engine(ap);
+}
+
+static void ahci_pmp_attach(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 cmd;
+
+	cmd = readl(port_mmio + PORT_CMD);
+	cmd |= PORT_CMD_PMP;
+	writel(cmd, port_mmio + PORT_CMD);
+
+	ahci_enable_fbs(ap);
+
+	pp->intr_mask |= PORT_IRQ_BAD_PMP;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static void ahci_pmp_detach(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	struct ahci_port_priv *pp = ap->private_data;
+	u32 cmd;
+
+	ahci_disable_fbs(ap);
+
+	cmd = readl(port_mmio + PORT_CMD);
+	cmd &= ~PORT_CMD_PMP;
+	writel(cmd, port_mmio + PORT_CMD);
+
+	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
+	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+}
+
+static int ahci_port_resume(struct ata_port *ap)
+{
+	ahci_power_up(ap);
+	ahci_start_port(ap);
+
+	if (sata_pmp_attached(ap))
+		ahci_pmp_attach(ap);
+	else
+		ahci_pmp_detach(ap);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
+{
+	const char *emsg = NULL;
+	int rc;
+
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc == 0)
+		ahci_power_down(ap);
+	else {
+		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
+		ahci_start_port(ap);
+	}
+
+	return rc;
+}
+#endif
+
+static int ahci_port_start(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	struct device *dev = ap->host->dev;
+	struct ahci_port_priv *pp;
+	void *mem;
+	dma_addr_t mem_dma;
+	size_t dma_sz, rx_fis_sz;
+
+	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	/* check FBS capability */
+	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
+		void __iomem *port_mmio = ahci_port_base(ap);
+		u32 cmd = readl(port_mmio + PORT_CMD);
+		if (cmd & PORT_CMD_FBSCP)
+			pp->fbs_supported = true;
+		else
+			dev_printk(KERN_WARNING, dev,
+				   "The port is not capable of FBS\n");
+	}
+
+	if (pp->fbs_supported) {
+		dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
+		rx_fis_sz = AHCI_RX_FIS_SZ * 16;
+	} else {
+		dma_sz = AHCI_PORT_PRIV_DMA_SZ;
+		rx_fis_sz = AHCI_RX_FIS_SZ;
+	}
+
+	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
+	if (!mem)
+		return -ENOMEM;
+	memset(mem, 0, dma_sz);
+
+	/*
+	 * First item in chunk of DMA memory: 32-slot command table,
+	 * 32 bytes each in size
+	 */
+	pp->cmd_slot = mem;
+	pp->cmd_slot_dma = mem_dma;
+
+	mem += AHCI_CMD_SLOT_SZ;
+	mem_dma += AHCI_CMD_SLOT_SZ;
+
+	/*
+	 * Second item: Received-FIS area
+	 */
+	pp->rx_fis = mem;
+	pp->rx_fis_dma = mem_dma;
+
+	mem += rx_fis_sz;
+	mem_dma += rx_fis_sz;
+
+	/*
+	 * Third item: data area for storing a single command
+	 * and its scatter-gather table
+	 */
+	pp->cmd_tbl = mem;
+	pp->cmd_tbl_dma = mem_dma;
+
+	/*
+	 * Save off initial list of interrupts to be enabled.
+	 * This could be changed later
+	 */
+	pp->intr_mask = DEF_PORT_IRQ;
+
+	ap->private_data = pp;
+
+	/* engage engines, captain */
+	return ahci_port_resume(ap);
+}
+
+static void ahci_port_stop(struct ata_port *ap)
+{
+	const char *emsg = NULL;
+	int rc;
+
+	/* de-initialize port */
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc)
+		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
+}
+
+void ahci_print_info(struct ata_host *host, const char *scc_s)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *mmio = hpriv->mmio;
+	u32 vers, cap, cap2, impl, speed;
+	const char *speed_s;
+
+	vers = readl(mmio + HOST_VERSION);
+	cap = hpriv->cap;
+	cap2 = hpriv->cap2;
+	impl = hpriv->port_map;
+
+	speed = (cap >> 20) & 0xf;
+	if (speed == 1)
+		speed_s = "1.5";
+	else if (speed == 2)
+		speed_s = "3";
+	else if (speed == 3)
+		speed_s = "6";
+	else
+		speed_s = "?";
+
+	dev_info(host->dev,
+		"AHCI %02x%02x.%02x%02x "
+		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
+		,
+
+		(vers >> 24) & 0xff,
+		(vers >> 16) & 0xff,
+		(vers >> 8) & 0xff,
+		vers & 0xff,
+
+		((cap >> 8) & 0x1f) + 1,
+		(cap & 0x1f) + 1,
+		speed_s,
+		impl,
+		scc_s);
+
+	dev_info(host->dev,
+		"flags: "
+		"%s%s%s%s%s%s%s"
+		"%s%s%s%s%s%s%s"
+		"%s%s%s%s%s%s\n"
+		,
+
+		cap & HOST_CAP_64 ? "64bit " : "",
+		cap & HOST_CAP_NCQ ? "ncq " : "",
+		cap & HOST_CAP_SNTF ? "sntf " : "",
+		cap & HOST_CAP_MPS ? "ilck " : "",
+		cap & HOST_CAP_SSS ? "stag " : "",
+		cap & HOST_CAP_ALPM ? "pm " : "",
+		cap & HOST_CAP_LED ? "led " : "",
+		cap & HOST_CAP_CLO ? "clo " : "",
+		cap & HOST_CAP_ONLY ? "only " : "",
+		cap & HOST_CAP_PMP ? "pmp " : "",
+		cap & HOST_CAP_FBS ? "fbs " : "",
+		cap & HOST_CAP_PIO_MULTI ? "pio " : "",
+		cap & HOST_CAP_SSC ? "slum " : "",
+		cap & HOST_CAP_PART ? "part " : "",
+		cap & HOST_CAP_CCC ? "ccc " : "",
+		cap & HOST_CAP_EMS ? "ems " : "",
+		cap & HOST_CAP_SXS ? "sxs " : "",
+		cap2 & HOST_CAP2_APST ? "apst " : "",
+		cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
+		cap2 & HOST_CAP2_BOH ? "boh " : ""
+		);
+}
+EXPORT_SYMBOL_GPL(ahci_print_info);
+
+void ahci_set_em_messages(struct ahci_host_priv *hpriv,
+			  struct ata_port_info *pi)
+{
+	u8 messages;
+	void __iomem *mmio = hpriv->mmio;
+	u32 em_loc = readl(mmio + HOST_EM_LOC);
+	u32 em_ctl = readl(mmio + HOST_EM_CTL);
+
+	if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
+		return;
+
+	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
+
+	/* we only support LED message type right now */
+	if ((messages & 0x01) && (ahci_em_messages == 1)) {
+		/* store em_loc */
+		hpriv->em_loc = ((em_loc >> 16) * 4);
+		pi->flags |= ATA_FLAG_EM;
+		if (!(em_ctl & EM_CTL_ALHD))
+			pi->flags |= ATA_FLAG_SW_ACTIVITY;
+	}
+}
+EXPORT_SYMBOL_GPL(ahci_set_em_messages);
+
+MODULE_AUTHOR("Jeff Garzik");
+MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 072ba5ea138f..98af50f16e0c 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -2299,29 +2299,49 @@ static inline u8 ata_dev_knobble(struct ata_device *dev)
 	return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
 }
 
-static void ata_dev_config_ncq(struct ata_device *dev,
+static int ata_dev_config_ncq(struct ata_device *dev,
 			       char *desc, size_t desc_sz)
 {
 	struct ata_port *ap = dev->link->ap;
 	int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
+	unsigned int err_mask;
+	char *aa_desc = "";
 
 	if (!ata_id_has_ncq(dev->id)) {
 		desc[0] = '\0';
-		return;
+		return 0;
 	}
 	if (dev->horkage & ATA_HORKAGE_NONCQ) {
 		snprintf(desc, desc_sz, "NCQ (not used)");
-		return;
+		return 0;
 	}
 	if (ap->flags & ATA_FLAG_NCQ) {
 		hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
 		dev->flags |= ATA_DFLAG_NCQ;
 	}
 
+	if (!(dev->horkage & ATA_HORKAGE_BROKEN_FPDMA_AA) &&
+		(ap->flags & ATA_FLAG_FPDMA_AA) &&
+		ata_id_has_fpdma_aa(dev->id)) {
+		err_mask = ata_dev_set_feature(dev, SETFEATURES_SATA_ENABLE,
+			SATA_FPDMA_AA);
+		if (err_mask) {
+			ata_dev_printk(dev, KERN_ERR, "failed to enable AA"
+				"(error_mask=0x%x)\n", err_mask);
+			if (err_mask != AC_ERR_DEV) {
+				dev->horkage |= ATA_HORKAGE_BROKEN_FPDMA_AA;
+				return -EIO;
+			}
+		} else
+			aa_desc = ", AA";
+	}
+
 	if (hdepth >= ddepth)
-		snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
+		snprintf(desc, desc_sz, "NCQ (depth %d)%s", ddepth, aa_desc);
 	else
-		snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
+		snprintf(desc, desc_sz, "NCQ (depth %d/%d)%s", hdepth,
+			ddepth, aa_desc);
+	return 0;
 }
 
 /**
@@ -2461,7 +2481,7 @@ int ata_dev_configure(struct ata_device *dev)
 
 		if (ata_id_has_lba(id)) {
 			const char *lba_desc;
-			char ncq_desc[20];
+			char ncq_desc[24];
 
 			lba_desc = "LBA";
 			dev->flags |= ATA_DFLAG_LBA;
@@ -2475,7 +2495,9 @@ int ata_dev_configure(struct ata_device *dev)
 			}
 
 			/* config NCQ */
-			ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+			rc = ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+			if (rc)
+				return rc;
 
 			/* print device info to dmesg */
 			if (ata_msg_drv(ap) && print_info) {
diff --git a/drivers/ata/pata_fsl.c b/drivers/ata/pata_fsl.c
new file mode 100644
index 000000000000..955095039257
--- /dev/null
+++ b/drivers/ata/pata_fsl.c
@@ -0,0 +1,1043 @@
+/*
+ * Freescale integrated PATA driver
+ */
+
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <scsi/scsi_host.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <mach/dma.h>
+
+#define DRV_NAME "pata_fsl"
+
+struct pata_fsl_priv {
+	int ultra;
+	u8 *fsl_ata_regs;
+	struct clk *clk;
+	int dma_rchan;
+	int dma_wchan;
+	int dma_done;
+	int dma_dir;
+	unsigned int adma_des_paddr;
+	unsigned int *adma_des_tp;
+};
+
+struct adma_bd {
+	unsigned char *sg_buf;
+	unsigned char *work_buf;
+	unsigned int dma_address;
+	int length;
+};
+
+struct adma_bulk {
+	struct adma_bd adma_bd_table[64];
+	struct ata_queued_cmd *qc;
+	int sg_ents;
+	int reserved[2];
+};
+
+enum {
+	/* various constants */
+	FSL_ATA_MAX_SG_LEN = ATA_DMA_BOUNDARY << 1,
+
+	/* offsets to registers */
+	FSL_ATA_TIMING_REGS = 0x00,
+	FSL_ATA_FIFO_FILL = 0x20,
+	FSL_ATA_CONTROL = 0x24,
+	FSL_ATA_INT_PEND = 0x28,
+	FSL_ATA_INT_EN = 0x2C,
+	FSL_ATA_INT_CLEAR = 0x30,
+	FSL_ATA_FIFO_ALARM = 0x34,
+	FSL_ATA_ADMA_ERROR_STATUS = 0x38,
+	FSL_ATA_SYS_DMA_BADDR = 0x3C,
+	FSL_ATA_ADMA_SYS_ADDR = 0x40,
+	FSL_ATA_BLOCK_COUNT = 0x48,
+	FSL_ATA_BURST_LENGTH = 0x4C,
+	FSL_ATA_SECTOR_SIZE = 0x50,
+	FSL_ATA_DRIVE_DATA = 0xA0,
+	FSL_ATA_DRIVE_CONTROL = 0xD8,
+
+	/* bits within FSL_ATA_CONTROL */
+	FSL_ATA_CTRL_DMA_SRST = 0x1000,
+	FSL_ATA_CTRL_DMA_64ADMA = 0x800,
+	FSL_ATA_CTRL_DMA_32ADMA = 0x400,
+	FSL_ATA_CTRL_DMA_STAT_STOP = 0x200,
+	FSL_ATA_CTRL_DMA_ENABLE = 0x100,
+	FSL_ATA_CTRL_FIFO_RST_B = 0x80,
+	FSL_ATA_CTRL_ATA_RST_B = 0x40,
+	FSL_ATA_CTRL_FIFO_TX_EN = 0x20,
+	FSL_ATA_CTRL_FIFO_RCV_EN = 0x10,
+	FSL_ATA_CTRL_DMA_PENDING = 0x08,
+	FSL_ATA_CTRL_DMA_ULTRA = 0x04,
+	FSL_ATA_CTRL_DMA_WRITE = 0x02,
+	FSL_ATA_CTRL_IORDY_EN = 0x01,
+
+	/* bits within the interrupt control registers */
+	FSL_ATA_INTR_ATA_INTRQ1 = 0x80,
+	FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40,
+	FSL_ATA_INTR_FIFO_OVERFLOW = 0x20,
+	FSL_ATA_INTR_CTRL_IDLE = 0x10,
+	FSL_ATA_INTR_ATA_INTRQ2 = 0x08,
+	FSL_ATA_INTR_DMA_ERR = 0x04,
+	FSL_ATA_INTR_DMA_TRANS_OVER = 0x02,
+
+	/* ADMA Addr Descriptor Attribute Filed */
+	FSL_ADMA_DES_ATTR_VALID = 0x01,
+	FSL_ADMA_DES_ATTR_END = 0x02,
+	FSL_ADMA_DES_ATTR_INT = 0x04,
+	FSL_ADMA_DES_ATTR_SET = 0x10,
+	FSL_ADMA_DES_ATTR_TRAN = 0x20,
+	FSL_ADMA_DES_ATTR_LINK = 0x30,
+};
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 5 PIO modes.  The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+	short t0, t1, t2_8, t2_16, t2i, t4, t9, tA;
+} pio_specs[] = {
+	[0] = {
+	.t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0, .t4 =
+		30, .t9 = 20, .tA = 50,},
+	[1] = {
+	.t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, .t4 =
+		20, .t9 = 15, .tA = 50,},
+	[2] = {
+	.t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, .t4 =
+		15, .t9 = 10, .tA = 50,},
+	[3] = {
+	.t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, .t4 =
+		10, .t9 = 10, .tA = 50,},
+	[4] = {
+	.t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, .t4 =
+		10, .t9 = 10, .tA = 50,},
+	};
+
+#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0])
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 3 MDMA modes.  The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+	short t0M, tD, tH, tJ, tKW, tM, tN, tJNH;
+} mdma_specs[] = {
+	[0] = {
+	.t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215, .tM = 50, .tN =
+		15, .tJNH = 20,},
+	[1] = {
+	.t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50, .tM = 30, .tN =
+		10, .tJNH = 15,},
+	[2] = {
+	.t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25, .tM = 25, .tN =
+		10, .tJNH = 10,},
+	};
+
+#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0])
+
+/*
+ * This structure contains the timing parameters for
+ * ATA bus timing in the 6 UDMA modes.  The timings
+ * are in nanoseconds, and are converted to clock
+ * cycles before being stored in the ATA controller
+ * timing registers.
+ */
+static struct {
+	short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max,
+	    tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS;
+} udma_specs[] = {
+	[0] = {
+	.t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70, .tDVH =
+		6, .tCVS = 70, .tCVH = 6, .tFS_min = 0, .tLI_max =
+		100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min =
+		20, .tSR = 50, .tRFS = 75, .tRP = 160, .tACK = 20, .tSS =
+		50, .tDZFS = 80,},
+	[1] = {
+	.t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48, .tDVH =
+		6, .tCVS = 48, .tCVH = 6, .tFS_min = 0, .tLI_max =
+		100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min =
+		20, .tSR = 30, .tRFS = 70, .tRP = 125, .tACK = 20, .tSS =
+		50, .tDZFS = 63,},
+	[2] = {
+	.t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34, .tDVH =
+		6, .tCVS = 34, .tCVH = 6, .tFS_min = 0, .tLI_max =
+		100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min =
+		20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS =
+		50, .tDZFS = 47,},
+	[3] = {
+	.t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20, .tDVH =
+		6, .tCVS = 20, .tCVH = 6, .tFS_min = 0, .tLI_max =
+		100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min =
+		20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS =
+		50, .tDZFS = 35,},
+	[4] = {
+	.t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7, .tDVH =
+		6, .tCVS = 7, .tCVH = 6, .tFS_min = 0, .tLI_max =
+		100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min =
+		20, .tSR = 50, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS =
+		50, .tDZFS = 25,},
+	[5] = {
+	.t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5, .tDVH =
+		6, .tCVS = 10, .tCVH = 10, .tFS_min =
+		0, .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH =
+		20, .tENV_min = 20, .tSR = 20, .tRFS =
+		50, .tRP = 85, .tACK = 20, .tSS = 50, .tDZFS = 40,},
+};
+
+#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0])
+
+struct fsl_ata_time_regs {
+	u8 time_off, time_on, time_1, time_2w;
+	u8 time_2r, time_ax, time_pio_rdx, time_4;
+	u8 time_9, time_m, time_jn, time_d;
+	u8 time_k, time_ack, time_env, time_rpx;
+	u8 time_zah, time_mlix, time_dvh, time_dzfs;
+	u8 time_dvs, time_cvh, time_ss, time_cyc;
+};
+
+static struct regulator *io_reg;
+static struct regulator *core_reg;
+static struct adma_bulk adma_info;
+
+static void
+update_timing_config(struct fsl_ata_time_regs *tp, struct ata_host *host)
+{
+	u32 *lp = (u32 *) tp;
+	struct pata_fsl_priv *priv = host->private_data;
+	u32 *ctlp = (u32 *) priv->fsl_ata_regs;
+	int i;
+
+	for (i = 0; i < 5; i++) {
+		__raw_writel(*lp, ctlp);
+		lp++;
+		ctlp++;
+	}
+}
+
+/*!
+ * Calculate values for the ATA bus timing registers and store
+ * them into the hardware.
+ *
+ * @param       xfer_mode   specifies XFER xfer_mode
+ * @param       pdev        specifies platform_device
+ *
+ * @return      EINVAL      speed out of range, or illegal mode
+ */
+static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev)
+{
+	struct ata_host *host = dev_get_drvdata(&pdev->dev);
+	struct pata_fsl_priv *priv = host->private_data;
+
+	/* get the bus clock cycle time, in ns */
+	int T = 1 * 1000 * 1000 * 1000 / clk_get_rate(priv->clk);
+	struct fsl_ata_time_regs tr = { 0 };
+
+	/*
+	 * every mode gets the same t_off and t_on
+	 */
+	tr.time_off = 3;
+	tr.time_on = 3;
+
+	if (xfer_mode >= XFER_UDMA_0) {
+		int speed = xfer_mode - XFER_UDMA_0;
+		if (speed >= NR_UDMA_SPECS)
+			return -EINVAL;
+
+		tr.time_ack = (udma_specs[speed].tACK + T) / T;
+		tr.time_env = (udma_specs[speed].tENV_min + T) / T;
+		tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2;
+		tr.time_zah = (udma_specs[speed].tZAH + T) / T;
+		tr.time_mlix = (udma_specs[speed].tMLI + T) / T;
+		tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1;
+		tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T;
+
+		tr.time_dvs = (udma_specs[speed].tDVS + T) / T;
+		tr.time_cvh = (udma_specs[speed].tCVH + T) / T;
+		tr.time_ss = (udma_specs[speed].tSS + T) / T;
+		tr.time_cyc = (udma_specs[speed].tCYC + T) / T;
+	} else if (xfer_mode >= XFER_MW_DMA_0) {
+		int speed = xfer_mode - XFER_MW_DMA_0;
+		if (speed >= NR_MDMA_SPECS)
+			return -EINVAL;
+
+		tr.time_m = (mdma_specs[speed].tM + T) / T;
+		tr.time_jn = (mdma_specs[speed].tJNH + T) / T;
+		tr.time_d = (mdma_specs[speed].tD + T) / T;
+
+		tr.time_k = (mdma_specs[speed].tKW + T) / T;
+	} else {
+		int speed = xfer_mode - XFER_PIO_0;
+		if (speed >= NR_PIO_SPECS)
+			return -EINVAL;
+
+		tr.time_1 = (pio_specs[speed].t1 + T) / T;
+		tr.time_2w = (pio_specs[speed].t2_8 + T) / T;
+
+		tr.time_2r = (pio_specs[speed].t2_8 + T) / T;
+		tr.time_ax = (pio_specs[speed].tA + T) / T + 2;
+		tr.time_pio_rdx = 1;
+		tr.time_4 = (pio_specs[speed].t4 + T) / T;
+
+		tr.time_9 = (pio_specs[speed].t9 + T) / T;
+	}
+
+	update_timing_config(&tr, host);
+
+	return 0;
+}
+
+static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev));
+}
+
+static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+	struct pata_fsl_priv *priv = ap->host->private_data;
+
+	priv->ultra = adev->dma_mode >= XFER_UDMA_0;
+
+	set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev));
+}
+
+static int pata_fsl_port_start(struct ata_port *ap)
+{
+	return 0;
+}
+
+static void pata_adma_bulk_unmap(struct ata_queued_cmd *qc)
+{
+	int i;
+	struct adma_bd *bdp = adma_info.adma_bd_table;
+	if (adma_info.qc == NULL)
+		return;
+	BUG_ON(adma_info.qc != qc);
+
+	adma_info.qc = NULL;
+
+	for (i = 0; i < adma_info.sg_ents; i++) {
+		if (bdp->work_buf != bdp->sg_buf) {
+			if (qc->dma_dir == DMA_FROM_DEVICE) {
+				memcpy(bdp->sg_buf, bdp->work_buf, bdp->length);
+				dma_cache_maint(bdp->sg_buf, bdp->length,
+						DMA_FROM_DEVICE);
+			}
+			dma_free_coherent(qc->ap->dev, bdp->length,
+					  bdp->work_buf, bdp->dma_address);
+		}
+		bdp->work_buf = bdp->sg_buf = NULL;
+		bdp++;
+	}
+}
+
+static int pata_adma_bulk_map(struct ata_queued_cmd *qc)
+{
+	unsigned int si;
+	struct scatterlist *sg;
+	struct adma_bd *bdp = adma_info.adma_bd_table;
+
+	BUG_ON(adma_info.qc);
+
+	adma_info.qc = qc;
+	adma_info.sg_ents = 0;
+
+	for_each_sg(qc->sg, sg, qc->n_elem, si) {
+		/*
+		 * The ADMA mode is used setup the ADMA descriptor table
+		 */
+		bdp->sg_buf = sg_virt(sg);
+		bdp->length = sg->length;
+		if (sg->dma_address & 0xFFF) {
+			bdp->work_buf =
+			    dma_alloc_coherent(qc->ap->dev, bdp->length,
+					       &bdp->dma_address, GFP_KERNEL);
+			if (!bdp->work_buf) {
+				printk(KERN_WARNING
+				       "can not allocate aligned buffer\n");
+				goto fail;
+			}
+			if (qc->dma_dir == DMA_TO_DEVICE)
+				memcpy(bdp->work_buf, bdp->sg_buf, bdp->length);
+		} else {
+			bdp->work_buf = bdp->sg_buf;
+			bdp->dma_address = sg->dma_address;
+		}
+
+		adma_info.sg_ents++;
+		bdp++;
+	}
+	return 0;
+      fail:
+	pata_adma_bulk_unmap(qc);
+	return -1;
+}
+
+static void dma_callback(void *arg, int error_status, unsigned int count)
+{
+	struct ata_port *ap = arg;
+	struct pata_fsl_priv *priv = ap->host->private_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+
+	priv->dma_done = 1;
+	/*
+	 * DMA is finished, so unmask INTRQ from the drive to allow the
+	 * normal ISR to fire.
+	 */
+	__raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
+}
+
+static irqreturn_t pata_fsl_adma_intr(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct pata_fsl_priv *priv = host->private_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+	unsigned int handled = 0;
+	unsigned int i;
+	unsigned long flags;
+	unsigned int pending = __raw_readl(ata_regs + FSL_ATA_INT_PEND);
+
+	if (FSL_ATA_INTR_DMA_TRANS_OVER & pending) {
+		priv->dma_done = 1;
+		__raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR);
+		handled = 1;
+	} else if (FSL_ATA_INTR_DMA_ERR & pending) {
+		printk(KERN_ERR "dma err status 0x%x ...\n",
+		       __raw_readl(ata_regs + FSL_ATA_ADMA_ERROR_STATUS));
+		__raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR);
+		handled = 1;
+		i = __raw_readl(ata_regs + FSL_ATA_CONTROL) && 0xFF;
+		i |= FSL_ATA_CTRL_DMA_SRST | FSL_ATA_CTRL_DMA_32ADMA |
+		    FSL_ATA_CTRL_DMA_ENABLE;
+		__raw_writel(i, ata_regs + FSL_ATA_CONTROL);
+	}
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap;
+
+		ap = host->ports[i];
+		if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
+			struct ata_queued_cmd *qc;
+
+			qc = ata_qc_from_tag(ap, ap->link.active_tag);
+			raw_local_irq_restore(flags);
+			pata_adma_bulk_unmap(qc);
+			raw_local_irq_save(flags);
+			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
+			    (qc->flags & ATA_QCFLAG_ACTIVE))
+				handled |= ata_sff_host_intr(ap, qc);
+		}
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	return IRQ_RETVAL(handled);
+}
+
+static int pata_fsl_check_atapi_dma(struct ata_queued_cmd *qc)
+{
+	return 1;		/* ATAPI DMA not yet supported */
+}
+
+unsigned long pata_fsl_bmdma_mode_filter(struct ata_device *adev,
+					unsigned long xfer_mask)
+{
+	/* Capability of the controller has been specified in the
+	 * platform data. Do not filter any modes, just return
+	 * the xfer_mask */
+	return xfer_mask;
+}
+
+static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc)
+{
+	int chan, i;
+	int dma_mode = 0, dma_ultra;
+	u32 ata_control;
+	struct ata_port *ap = qc->ap;
+	struct pata_fsl_priv *priv = ap->host->private_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+	struct fsl_ata_platform_data *plat = ap->dev->platform_data;
+	int err;
+	unsigned int si;
+
+	priv->dma_dir = qc->dma_dir;
+
+	/*
+	 * Configure the on-chip ATA interface hardware.
+	 */
+	dma_ultra = priv->ultra ? FSL_ATA_CTRL_DMA_ULTRA : 0;
+
+	ata_control = FSL_ATA_CTRL_FIFO_RST_B |
+	    FSL_ATA_CTRL_ATA_RST_B | FSL_ATA_CTRL_DMA_PENDING | dma_ultra;
+	if (plat->adma_flag)
+		ata_control |= FSL_ATA_CTRL_DMA_32ADMA |
+		    FSL_ATA_CTRL_DMA_ENABLE;
+
+	if (qc->dma_dir == DMA_TO_DEVICE) {
+		chan = priv->dma_wchan;
+		ata_control |= FSL_ATA_CTRL_FIFO_TX_EN | FSL_ATA_CTRL_DMA_WRITE;
+		dma_mode = MXC_DMA_MODE_WRITE;
+	} else {
+		chan = priv->dma_rchan;
+		ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN;
+		dma_mode = MXC_DMA_MODE_READ;
+	}
+
+	__raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL);
+	__raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM);
+
+	if (plat->adma_flag) {
+		i = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR;
+		__raw_writel(FSL_ATA_INTR_ATA_INTRQ2 | i,
+			     ata_regs + FSL_ATA_INT_EN);
+	} else {
+		__raw_writel(FSL_ATA_INTR_ATA_INTRQ1,
+			     ata_regs + FSL_ATA_INT_EN);
+		/*
+		 * Set up the DMA completion callback.
+		 */
+		mxc_dma_callback_set(chan, dma_callback, (void *)ap);
+	}
+
+	/*
+	 * Copy the sg list to an array.
+	 */
+	if (plat->adma_flag) {
+		struct adma_bd *bdp = adma_info.adma_bd_table;
+		pata_adma_bulk_map(qc);
+		for (i = 0; i < adma_info.sg_ents; i++) {
+			priv->adma_des_tp[i << 1] = bdp->length << 12;
+			priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_SET;
+			priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_VALID;
+			priv->adma_des_tp[(i << 1) + 1] = bdp->dma_address;
+			priv->adma_des_tp[(i << 1) + 1] |=
+			    FSL_ADMA_DES_ATTR_TRAN;
+			priv->adma_des_tp[(i << 1) + 1] |=
+			    FSL_ADMA_DES_ATTR_VALID;
+			if (adma_info.sg_ents == (i + 1))
+				priv->adma_des_tp[(i << 1) + 1] |=
+				    FSL_ADMA_DES_ATTR_END;
+			bdp++;
+		}
+		__raw_writel((qc->nbytes / qc->sect_size), ata_regs +
+			     FSL_ATA_BLOCK_COUNT);
+		__raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_BURST_LENGTH);
+		__raw_writel(priv->adma_des_paddr,
+			     ata_regs + FSL_ATA_ADMA_SYS_ADDR);
+	} else {
+		int nr_sg = 0;
+		struct scatterlist tmp[64], *tsg, *sg;
+		tsg = tmp;
+		for_each_sg(qc->sg, sg, qc->n_elem, si) {
+			memcpy(tsg, sg, sizeof(*sg));
+			tsg++;
+			nr_sg++;
+		}
+		err = mxc_dma_sg_config(chan, tmp, nr_sg, 0, dma_mode);
+		if (err)
+			printk(KERN_ERR "pata_fsl_bmdma_setup: error %d\n",
+			       err);
+	}
+}
+
+static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct pata_fsl_priv *priv = ap->host->private_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+	struct fsl_ata_platform_data *plat = ap->dev->platform_data;
+	int chan;
+	int err;
+	unsigned i;
+
+	if (1 == plat->adma_flag) {
+		i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE;
+		/* The adma mode is used, set dma_start_stop to 1 */
+		__raw_writel(i | __raw_readl(ata_regs + FSL_ATA_CONTROL) |
+			     FSL_ATA_CTRL_DMA_STAT_STOP,
+			     ata_regs + FSL_ATA_CONTROL);
+	} else {
+		/*
+		 * Start the channel.
+		 */
+		chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan :
+		    priv->dma_rchan;
+
+		err = mxc_dma_enable(chan);
+		if (err)
+			printk(KERN_ERR "%s: : error %d\n", __func__, err);
+	}
+
+	priv->dma_done = 0;
+
+	ata_sff_exec_command(ap, &qc->tf);
+}
+
+static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct pata_fsl_priv *priv = ap->host->private_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+	struct fsl_ata_platform_data *plat = ap->dev->platform_data;
+	unsigned i;
+
+	if (plat->adma_flag) {
+		/* The adma mode is used, set dma_start_stop to 0 */
+		i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE;
+		__raw_writel((i | __raw_readl(ata_regs + FSL_ATA_CONTROL)) &
+			     (~FSL_ATA_CTRL_DMA_STAT_STOP),
+			     ata_regs + FSL_ATA_CONTROL);
+	}
+
+	/* do a dummy read as in ata_bmdma_stop */
+#if 0
+	ata_sff_dma_pause(ap);
+#endif
+}
+
+static u8 pata_fsl_bmdma_status(struct ata_port *ap)
+{
+	struct pata_fsl_priv *priv = ap->host->private_data;
+
+	return priv->dma_done ? ATA_DMA_INTR : 0;
+}
+
+static void pata_fsl_dma_init(struct ata_port *ap)
+{
+	struct pata_fsl_priv *priv = ap->host->private_data;
+
+	priv->dma_rchan = -1;
+	priv->dma_wchan = -1;
+
+	priv->dma_rchan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX");
+	if (priv->dma_rchan < 0) {
+		dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n");
+		goto err_out;
+	}
+
+	priv->dma_wchan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX");
+	if (priv->dma_wchan < 0) {
+		dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n");
+		goto err_out;
+	}
+
+	dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan,
+		   priv->dma_wchan);
+	return;
+
+      err_out:
+	ap->mwdma_mask = 0;
+	ap->udma_mask = 0;
+	mxc_dma_free(priv->dma_rchan);
+	mxc_dma_free(priv->dma_wchan);
+	kfree(priv);
+}
+
+#if 0
+static u8 pata_fsl_irq_ack(struct ata_port *ap, unsigned int chk_drq)
+{
+	unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
+	u8 status;
+
+	status = ata_sff_busy_wait(ap, bits, 1000);
+	if (status & bits)
+		if (ata_msg_err(ap))
+			printk(KERN_ERR "abnormal status 0x%X\n", status);
+
+	return status;
+}
+#endif
+
+static void ata_dummy_noret(struct ata_port *ap)
+{
+	return;
+}
+
+static struct scsi_host_template pata_fsl_sht = {
+	.module = THIS_MODULE,
+	.name = DRV_NAME,
+	.ioctl = ata_scsi_ioctl,
+	.queuecommand = ata_scsi_queuecmd,
+	.can_queue = ATA_DEF_QUEUE,
+	.this_id = ATA_SHT_THIS_ID,
+	.sg_tablesize = LIBATA_MAX_PRD,
+	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
+	.emulated = ATA_SHT_EMULATED,
+	.use_clustering = ATA_SHT_USE_CLUSTERING,
+	.proc_name = DRV_NAME,
+	.dma_boundary = FSL_ATA_MAX_SG_LEN,
+	.slave_configure = ata_scsi_slave_config,
+	.slave_destroy = ata_scsi_slave_destroy,
+	.bios_param = ata_std_bios_param,
+};
+
+static struct ata_port_operations pata_fsl_port_ops = {
+	.inherits = &ata_bmdma_port_ops,
+	.set_piomode = pata_fsl_set_piomode,
+	.set_dmamode = pata_fsl_set_dmamode,
+
+	.check_atapi_dma = pata_fsl_check_atapi_dma,
+	.cable_detect = ata_cable_unknown,
+	.mode_filter = pata_fsl_bmdma_mode_filter,
+
+	.bmdma_setup = pata_fsl_bmdma_setup,
+	.bmdma_start = pata_fsl_bmdma_start,
+	.bmdma_stop = pata_fsl_bmdma_stop,
+	.bmdma_status = pata_fsl_bmdma_status,
+
+	.qc_prep = ata_noop_qc_prep,
+
+	.sff_data_xfer = ata_sff_data_xfer_noirq,
+	.sff_irq_clear = ata_dummy_noret,
+	.sff_irq_on = ata_sff_irq_on,
+
+	.port_start = pata_fsl_port_start,
+};
+
+static void fsl_setup_port(struct ata_ioports *ioaddr)
+{
+	unsigned int shift = 2;
+
+	ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift);
+	ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift);
+	ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift);
+	ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift);
+	ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift);
+	ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift);
+	ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift);
+	ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift);
+	ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift);
+	ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift);
+}
+
+/**
+ *     pata_fsl_probe          -       attach a platform interface
+ *     @pdev: platform device
+ *
+ *     Register a platform bus integrated ATA host controller
+ *
+ *     The 3 platform device resources are used as follows:
+ *
+ *             - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs
+ *             - CTL Base (IORESOURCE_MEM) unused
+ *             - IRQ      (IORESOURCE_IRQ) platform IRQ assigned to ATA
+ *
+ */
+static int __devinit pata_fsl_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct resource *io_res;
+	struct ata_host *host;
+	struct ata_port *ap;
+	struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+	    pdev->dev.platform_data;
+	struct pata_fsl_priv *priv;
+	u8 *ata_regs;
+	unsigned int int_enable;
+
+	/*
+	 * Set up resources
+	 */
+	if (unlikely(pdev->num_resources != 2)) {
+		dev_err(&pdev->dev, "invalid number of resources\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get an ata_host structure for this device
+	 */
+	host = ata_host_alloc(&pdev->dev, 1);
+	if (!host)
+		return -ENOMEM;
+	ap = host->ports[0];
+
+	/*
+	 * Allocate private data
+	 */
+	priv = kzalloc(sizeof(struct pata_fsl_priv), GFP_KERNEL);
+	if (priv == NULL) {
+		ret = -ENOMEM;
+		goto err0;
+	}
+	host->private_data = priv;
+
+	/*
+	 * Set up resources
+	 */
+	io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ata_regs =
+	    (u8 *) ioremap(io_res->start, io_res->end - io_res->start + 1);
+	priv->fsl_ata_regs = ata_regs;
+	ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA);
+	ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL);
+	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
+	ap->ops = &pata_fsl_port_ops;
+	ap->pio_mask = plat->pio_mask;	/* support pio 0~4 */
+	ap->mwdma_mask = plat->mwdma_mask;	/* support mdma 0~2 */
+	ap->udma_mask = plat->udma_mask;
+	pata_fsl_sht.sg_tablesize = plat->max_sg;
+	fsl_setup_port(&ap->ioaddr);
+
+	if (plat->adma_flag) {
+		priv->adma_des_tp =
+		    dma_alloc_coherent(&(pdev->dev),
+				       (2 * plat->max_sg) *
+				       sizeof(unsigned int),
+				       &(priv->adma_des_paddr), GFP_DMA);
+		if (priv->adma_des_tp == NULL) {
+			ret = -ENOMEM;
+			goto err1;
+		}
+	}
+	/*
+	 * Do platform-specific initialization (e.g. allocate pins,
+	 * turn on clock).  After this call it is assumed that
+	 * plat->get_clk_rate() can be called to calculate
+	 * timing.
+	 */
+	if (plat->init && plat->init(pdev)) {
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	priv->clk = clk_get(&pdev->dev, "ata_clk");
+	clk_enable(priv->clk);
+
+	/* Deassert the reset bit to enable the interface */
+	__raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL);
+
+	/* Enable Core regulator & IO Regulator */
+	if (plat->core_reg != NULL) {
+		core_reg = regulator_get(&pdev->dev, plat->core_reg);
+		if (regulator_enable(core_reg))
+			printk(KERN_INFO "enable core regulator error.\n");
+		msleep(100);
+
+	} else
+		core_reg = NULL;
+
+	if (plat->io_reg != NULL) {
+		io_reg = regulator_get(&pdev->dev, plat->io_reg);
+		if (regulator_enable(io_reg))
+			printk(KERN_INFO "enable io regulator error.\n");
+		msleep(100);
+
+	} else
+		io_reg = NULL;
+
+	/* Set initial timing and mode */
+	set_ata_bus_timing(XFER_PIO_4, pdev);
+
+	/* get DMA ready */
+	if (plat->adma_flag == 0)
+		pata_fsl_dma_init(ap);
+
+	/*
+	 * Enable the ATA INTRQ interrupt from the bus, but
+	 * only allow the CPU to see it (INTRQ2) at this point.
+	 * INTRQ1, which goes to the DMA, will be enabled later.
+	 */
+	int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR |
+	    FSL_ATA_INTR_ATA_INTRQ2;
+	if (plat->adma_flag)
+		__raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN);
+	else
+		__raw_writel(FSL_ATA_INTR_ATA_INTRQ2,
+			     ata_regs + FSL_ATA_INT_EN);
+
+	/* activate */
+	if (plat->adma_flag)
+		ret = ata_host_activate(host, platform_get_irq(pdev, 0),
+					pata_fsl_adma_intr, 0, &pata_fsl_sht);
+	else
+		ret = ata_host_activate(host, platform_get_irq(pdev, 0),
+					ata_sff_interrupt, 0, &pata_fsl_sht);
+
+	if (!ret)
+		return ret;
+
+	clk_disable(priv->clk);
+	regulator_disable(core_reg);
+	regulator_disable(io_reg);
+      err2:
+	if (plat->adma_flag && priv->adma_des_tp)
+		dma_free_coherent(&(pdev->dev),
+				  (2 * plat->max_sg +
+				   1) * sizeof(unsigned int), priv->adma_des_tp,
+				  priv->adma_des_paddr);
+      err1:
+	iounmap(ata_regs);
+	kfree(priv);
+      err0:
+	ata_host_detach(host);
+	return ret;
+
+}
+
+/**
+ *     pata_fsl_remove -       unplug a platform interface
+ *     @pdev: platform device
+ *
+ *     A platform bus ATA device has been unplugged. Perform the needed
+ *     cleanup. Also called on module unload for any active devices.
+ */
+static int __devexit pata_fsl_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct pata_fsl_priv *priv = host->private_data;
+	struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+	    pdev->dev.platform_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+
+	__raw_writel(0, ata_regs + FSL_ATA_INT_EN);	/* Disable interrupts */
+
+	ata_host_detach(host);
+
+	clk_disable(priv->clk);
+	clk_put(priv->clk);
+	priv->clk = NULL;
+
+	/* Disable Core regulator & IO Regulator */
+	if (plat->core_reg != NULL) {
+		regulator_disable(core_reg);
+		regulator_put(core_reg);
+	}
+	if (plat->io_reg != NULL) {
+		regulator_disable(io_reg);
+		regulator_put(io_reg);
+	}
+
+	if (plat->exit)
+		plat->exit();
+
+	if (plat->adma_flag && priv->adma_des_tp)
+		dma_free_coherent(&(pdev->dev),
+				  (2 * plat->max_sg) *
+				  sizeof(unsigned int), priv->adma_des_tp,
+				  priv->adma_des_paddr);
+	iounmap(ata_regs);
+
+	kfree(priv);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct ata_host *host = dev_get_drvdata(&pdev->dev);
+	struct pata_fsl_priv *priv = host->private_data;
+	struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+	    pdev->dev.platform_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+
+	ata_host_suspend(host, state);
+
+	/* Disable interrupts. */
+	__raw_writel(0, ata_regs + FSL_ATA_INT_EN);
+
+	clk_disable(priv->clk);
+
+	if (plat->exit)
+		plat->exit();
+
+	return 0;
+}
+
+static int pata_fsl_resume(struct platform_device *pdev)
+{
+	struct ata_host *host = dev_get_drvdata(&pdev->dev);
+	struct pata_fsl_priv *priv = host->private_data;
+	struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
+	    pdev->dev.platform_data;
+	u8 *ata_regs = priv->fsl_ata_regs;
+	unsigned char int_enable;
+
+	if (plat->init && plat->init(pdev))
+		return -ENODEV;
+
+	clk_enable(priv->clk);
+
+	/* Deassert the reset bit to enable the interface */
+	__raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL);
+
+	/* Set initial timing and mode */
+	set_ata_bus_timing(XFER_PIO_4, pdev);
+
+	/*
+	 * Enable hardware interrupts.
+	 */
+	int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR |
+	    FSL_ATA_INTR_ATA_INTRQ2;
+	if (1 == plat->adma_flag)
+		__raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN);
+	else
+		__raw_writel(FSL_ATA_INTR_ATA_INTRQ2,
+			     ata_regs + FSL_ATA_INT_EN);
+
+	ata_host_resume(host);
+
+	return 0;
+}
+#endif
+
+static struct platform_driver pata_fsl_driver = {
+	.probe = pata_fsl_probe,
+	.remove = __devexit_p(pata_fsl_remove),
+#ifdef CONFIG_PM
+	.suspend = pata_fsl_suspend,
+	.resume = pata_fsl_resume,
+#endif
+	.driver = {
+		   .name = DRV_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init pata_fsl_init(void)
+{
+	return platform_driver_register(&pata_fsl_driver);
+
+	return 0;
+}
+
+static void __exit pata_fsl_exit(void)
+{
+	platform_driver_unregister(&pata_fsl_driver);
+}
+
+module_init(pata_fsl_init);
+module_exit(pata_fsl_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("low-level driver for Freescale ATA");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index dc99e26f8e5b..c4647f5b6a22 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -136,7 +136,7 @@ static unsigned int ata_data_xfer_8bit(struct ata_device *dev,
  *
  */
  
-void pcmcia_8bit_drain_fifo(struct ata_queued_cmd *qc)
+static void pcmcia_8bit_drain_fifo(struct ata_queued_cmd *qc)
 {
 	int count;
 	struct ata_port *ap;
diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
index 894b2cb11ea6..40aec0fb8596 100644
--- a/drivers/bluetooth/hci_bcsp.c
+++ b/drivers/bluetooth/hci_bcsp.c
@@ -373,8 +373,9 @@ static void bcsp_pkt_cull(struct bcsp_struct *bcsp)
 
 	i = 0;
 	skb_queue_walk_safe(&bcsp->unack, skb, tmp) {
-		if (i++ >= pkts_to_be_removed)
+		if (i >= pkts_to_be_removed)
 			break;
+		i++;
 
 		__skb_unlink(skb, &bcsp->unack);
 		kfree_skb(skb);
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 6a06913b01d3..37492dcf15c7 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -431,6 +431,29 @@ config SGI_MBCS
          If you have an SGI Altix with an attached SABrick
          say Y or M here, otherwise say N.
 
+config FM_SI4702
+	tristate "SI4702 FM device driver"
+	depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS)
+	default n
+
+config MXC_IIM
+	tristate "MXC IIM device driver"
+	depends on ARCH_MXC
+	help
+	  Support for access to MXC IIM device, most people should say N here.
+
+config MXS_VIIM
+	tristate "MXS Virtual IIM device driver"
+	depends on (ARCH_STMP3XXX || ARCH_MXS || ARCH_MX5)
+	help
+	  Support for access to MXS Virtual IIM device, most people should say N here.
+
+config IMX_SIM
+	tristate "IMX SIM support"
+	depends on (ARCH_MX5 || ARCH_MX25)
+	---help---
+         Say Y to enable the SIM driver support.
+
 source "drivers/serial/Kconfig"
 
 config UNIX98_PTYS
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 66f779ad4f4c..c711f02de8f7 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -9,6 +9,11 @@ FONTMAPFILE = cp437.uni
 
 obj-y	 += mem.o random.o tty_io.o n_tty.o tty_ioctl.o tty_ldisc.o tty_buffer.o tty_port.o
 
+obj-$(CONFIG_FM_SI4702)		+= mxc_si4702.o
+obj-$(CONFIG_MXC_IIM)		+= mxc_iim.o
+obj-$(CONFIG_MXS_VIIM)		+= mxs_viim.o
+obj-$(CONFIG_IMX_SIM) 		+= imx_sim.o
+
 obj-$(CONFIG_LEGACY_PTYS)	+= pty.o
 obj-$(CONFIG_UNIX98_PTYS)	+= pty.o
 obj-y				+= misc.o
@@ -97,7 +102,6 @@ obj-$(CONFIG_NSC_GPIO)		+= nsc_gpio.o
 obj-$(CONFIG_CS5535_GPIO)	+= cs5535_gpio.o
 obj-$(CONFIG_GPIO_TB0219)	+= tb0219.o
 obj-$(CONFIG_TELCLOCK)		+= tlclk.o
-
 obj-$(CONFIG_MWAVE)		+= mwave/
 obj-$(CONFIG_AGP)		+= agp/
 obj-$(CONFIG_PCMCIA)		+= pcmcia/
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index ce66a70184f7..108a752c9132 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -60,6 +60,30 @@ config HW_RANDOM_AMD
 
 	  If unsure, say Y.
 
+config HW_RANDOM_FSL_RNGA
+	tristate "Freescale RNGA Random Number Generator"
+	depends on HW_RANDOM && ARCH_HAS_RNGA && !MXC_SECURITY_RNG
+	---help---
+	  This driver provides kernel-side support for the Random Number
+	  Generator hardware found on Freescale i.MX processors.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called fsl-rnga.
+
+	  If unsure, say Y.
+
+config HW_RANDOM_FSL_RNGC
+	tristate "Freescale RNGC Random Number Generator"
+	depends on HW_RANDOM && ARCH_HAS_RNGC && !MXC_SECURITY_RNG
+	---help---
+	  This driver provides kernel-side support for the Random Number
+	  Generator hardware found on Freescale i.MX processors.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called fsl-rngc.
+
+	  If unsure, say Y.
+
 config HW_RANDOM_GEODE
 	tristate "AMD Geode HW Random Number Generator support"
 	depends on HW_RANDOM && X86_32 && PCI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 676828ba8123..c6170069f998 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -7,6 +7,8 @@ rng-core-y := core.o
 obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
 obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
 obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
+obj-$(CONFIG_HW_RANDOM_FSL_RNGA) += fsl-rnga.o
+obj-$(CONFIG_HW_RANDOM_FSL_RNGC) += fsl-rngc.o
 obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
 obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
 n2-rng-y := n2-drv.o n2-asm.o
diff --git a/drivers/char/hw_random/fsl-rnga.c b/drivers/char/hw_random/fsl-rnga.c
new file mode 100644
index 000000000000..a5c8065604d4
--- /dev/null
+++ b/drivers/char/hw_random/fsl-rnga.c
@@ -0,0 +1,238 @@
+/*
+ * RNG driver for Freescale RNGA
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
+ * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
+ *
+ * derived from
+ *
+ * Hardware driver for the AMD 768 Random Number Generator (RNG)
+ * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
+ *
+ * derived from
+ *
+ * Hardware driver for Intel i810 Random Number Generator (RNG)
+ * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
+ * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+
+/* RNGA Registers */
+#define RNGA_CONTROL			0x00
+#define RNGA_STATUS			0x04
+#define RNGA_ENTROPY			0x08
+#define RNGA_OUTPUT_FIFO		0x0c
+#define RNGA_MODE			0x10
+#define RNGA_VERIFICATION_CONTROL	0x14
+#define RNGA_OSC_CONTROL_COUNTER	0x18
+#define RNGA_OSC1_COUNTER		0x1c
+#define RNGA_OSC2_COUNTER		0x20
+#define RNGA_OSC_COUNTER_STATUS		0x24
+
+/* RNGA Registers Range */
+#define RNG_ADDR_RANGE			0x28
+
+/* RNGA Control Register */
+#define RNGA_CONTROL_SLEEP		0x00000010
+#define RNGA_CONTROL_CLEAR_INT		0x00000008
+#define RNGA_CONTROL_MASK_INTS		0x00000004
+#define RNGA_CONTROL_HIGH_ASSURANCE	0x00000002
+#define RNGA_CONTROL_GO			0x00000001
+
+#define RNGA_STATUS_LEVEL_MASK		0x0000ff00
+
+/* RNGA Status Register */
+#define RNGA_STATUS_OSC_DEAD		0x80000000
+#define RNGA_STATUS_SLEEP		0x00000010
+#define RNGA_STATUS_ERROR_INT		0x00000008
+#define RNGA_STATUS_FIFO_UNDERFLOW	0x00000004
+#define RNGA_STATUS_LAST_READ_STATUS	0x00000002
+#define RNGA_STATUS_SECURITY_VIOLATION	0x00000001
+
+static struct platform_device *rng_dev;
+
+static int fsl_rnga_data_present(struct hwrng *rng)
+{
+	int level;
+	u32 rng_base = (u32) rng->priv;
+
+	/* how many random numbers is in FIFO? [0-16] */
+	level = ((__raw_readl(rng_base + RNGA_STATUS) &
+			RNGA_STATUS_LEVEL_MASK) >> 8);
+
+	return level > 0 ? 1 : 0;
+}
+
+static int fsl_rnga_data_read(struct hwrng *rng, u32 * data)
+{
+	int err;
+	u32 ctrl, rng_base = (u32) rng->priv;
+
+	/* retrieve a random number from FIFO */
+	*data = __raw_readl(rng_base + RNGA_OUTPUT_FIFO);
+
+	/* some error while reading this random number? */
+	err = __raw_readl(rng_base + RNGA_STATUS) & RNGA_STATUS_ERROR_INT;
+
+	/* if error: clear error interrupt, but doesn't return random number */
+	if (err) {
+		dev_dbg(&rng_dev->dev, "Error while reading random number!\n");
+		ctrl = __raw_readl(rng_base + RNGA_CONTROL);
+		__raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT,
+					rng_base + RNGA_CONTROL);
+		return 0;
+	} else
+		return 4;
+}
+
+static int fsl_rnga_init(struct hwrng *rng)
+{
+	u32 ctrl, osc, rng_base = (u32) rng->priv;
+
+	/* wake up */
+	ctrl = __raw_readl(rng_base + RNGA_CONTROL);
+	__raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, rng_base + RNGA_CONTROL);
+
+	/* verify if oscillator is working */
+	osc = __raw_readl(rng_base + RNGA_STATUS);
+	if (osc & RNGA_STATUS_OSC_DEAD) {
+		dev_err(&rng_dev->dev, "RNGA Oscillator is dead!\n");
+		return -ENODEV;
+	}
+
+	/* go running */
+	ctrl = __raw_readl(rng_base + RNGA_CONTROL);
+	__raw_writel(ctrl | RNGA_CONTROL_GO, rng_base + RNGA_CONTROL);
+
+	return 0;
+}
+
+static void fsl_rnga_cleanup(struct hwrng *rng)
+{
+	u32 ctrl, rng_base = (u32) rng->priv;
+
+	ctrl = __raw_readl(rng_base + RNGA_CONTROL);
+
+	/* stop rnga */
+	__raw_writel(ctrl & ~RNGA_CONTROL_GO, rng_base + RNGA_CONTROL);
+}
+
+static struct hwrng fsl_rnga = {
+	.name = "fsl-rnga",
+	.init = fsl_rnga_init,
+	.cleanup = fsl_rnga_cleanup,
+	.data_present = fsl_rnga_data_present,
+	.data_read = fsl_rnga_data_read
+};
+
+static int __init fsl_rnga_probe(struct platform_device *pdev)
+{
+	int err = -ENODEV;
+	struct clk *clk;
+	struct resource *res, *mem;
+	void __iomem *rng_base = NULL;
+
+	if (rng_dev)
+		return -EBUSY;
+
+	clk = clk_get(NULL, "rng_clk");
+
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "Could not get rng_clk!\n");
+		err = PTR_ERR(clk);
+		return err;
+	}
+
+	clk_enable(clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res)
+		return -ENOENT;
+
+	mem = request_mem_region(res->start, res->end - res->start, pdev->name);
+
+	if (mem == NULL)
+		return -EBUSY;
+
+	dev_set_drvdata(&pdev->dev, mem);
+	rng_base = ioremap(res->start, res->end - res->start);
+
+	fsl_rnga.priv = (unsigned long)rng_base;
+
+	err = hwrng_register(&fsl_rnga);
+	if (err) {
+		dev_err(&pdev->dev, "FSL RNGA registering failed (%d)\n", err);
+		return err;
+	}
+
+	rng_dev = pdev;
+
+	dev_info(&pdev->dev, "FSL RNGA Registered.\n");
+
+	return 0;
+}
+
+static int __exit fsl_rnga_remove(struct platform_device *pdev)
+{
+	struct resource *mem = dev_get_drvdata(&pdev->dev);
+	void __iomem *rng_base = (void __iomem *)fsl_rnga.priv;
+
+	hwrng_unregister(&fsl_rnga);
+
+	release_resource(mem);
+
+	iounmap(rng_base);
+
+	return 0;
+}
+
+static struct platform_driver fsl_rnga_driver = {
+	.driver = {
+		   .name = "fsl_rnga",
+		   .owner = THIS_MODULE,
+		   },
+	.remove = __exit_p(fsl_rnga_remove),
+};
+
+static int __init mod_init(void)
+{
+	return platform_driver_probe(&fsl_rnga_driver, fsl_rnga_probe);
+}
+
+static void __exit mod_exit(void)
+{
+	platform_driver_unregister(&fsl_rnga_driver);
+}
+
+module_init(mod_init);
+module_exit(mod_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("H/W RNGA driver for i.MX");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/hw_random/fsl-rngc.c b/drivers/char/hw_random/fsl-rngc.c
new file mode 100644
index 000000000000..9bf78e846fa0
--- /dev/null
+++ b/drivers/char/hw_random/fsl-rngc.c
@@ -0,0 +1,372 @@
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
+ * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
+ *
+ * derived from
+ *
+ * Hardware driver for the AMD 768 Random Number Generator (RNG)
+ * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
+ *
+ * derived from
+ *
+ * Hardware driver for Intel i810 Random Number Generator (RNG)
+ * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
+ * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <asm/hardware.h>
+
+#define RNGC_VERSION_MAJOR3 3
+
+#define RNGC_VERSION_ID				0x0000
+#define RNGC_COMMAND				0x0004
+#define RNGC_CONTROL				0x0008
+#define RNGC_STATUS				0x000C
+#define RNGC_ERROR				0x0010
+#define RNGC_FIFO				0x0014
+#define RNGC_VERIF_CTRL				0x0020
+#define RNGC_OSC_CTRL_COUNT			0x0028
+#define RNGC_OSC_COUNT				0x002C
+#define RNGC_OSC_COUNT_STATUS			0x0030
+
+#define RNGC_VERID_ZEROS_MASK			0x0f000000
+#define RNGC_VERID_RNG_TYPE_MASK		0xf0000000
+#define RNGC_VERID_RNG_TYPE_SHIFT		28
+#define RNGC_VERID_CHIP_VERSION_MASK		0x00ff0000
+#define RNGC_VERID_CHIP_VERSION_SHIFT		16
+#define RNGC_VERID_VERSION_MAJOR_MASK		0x0000ff00
+#define RNGC_VERID_VERSION_MAJOR_SHIFT		8
+#define RNGC_VERID_VERSION_MINOR_MASK		0x000000ff
+#define RNGC_VERID_VERSION_MINOR_SHIFT		0
+
+#define RNGC_CMD_ZEROS_MASK			0xffffff8c
+#define RNGC_CMD_SW_RST				0x00000040
+#define RNGC_CMD_CLR_ERR			0x00000020
+#define RNGC_CMD_CLR_INT			0x00000010
+#define RNGC_CMD_SEED				0x00000002
+#define RNGC_CMD_SELF_TEST			0x00000001
+
+#define RNGC_CTRL_ZEROS_MASK			0xfffffc8c
+#define RNGC_CTRL_CTL_ACC			0x00000200
+#define RNGC_CTRL_VERIF_MODE			0x00000100
+#define RNGC_CTRL_MASK_ERROR			0x00000040
+
+#define RNGC_CTRL_MASK_DONE			0x00000020
+#define RNGC_CTRL_AUTO_SEED			0x00000010
+#define RNGC_CTRL_FIFO_UFLOW_MASK		0x00000003
+#define RNGC_CTRL_FIFO_UFLOW_SHIFT		0
+
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR	0
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2	1
+#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR		2
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR		3
+
+#define RNGC_STATUS_ST_PF_MASK			0x00c00000
+#define RNGC_STATUS_ST_PF_SHIFT			22
+#define RNGC_STATUS_ST_PF_TRNG			0x00800000
+#define RNGC_STATUS_ST_PF_PRNG			0x00400000
+#define RNGC_STATUS_ERROR			0x00010000
+#define RNGC_STATUS_FIFO_SIZE_MASK		0x0000f000
+#define RNGC_STATUS_FIFO_SIZE_SHIFT		12
+#define RNGC_STATUS_FIFO_LEVEL_MASK		0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT		8
+#define RNGC_STATUS_NEXT_SEED_DONE		0x00000040
+#define RNGC_STATUS_SEED_DONE			0x00000020
+#define RNGC_STATUS_ST_DONE			0x00000010
+#define RNGC_STATUS_RESEED			0x00000008
+#define RNGC_STATUS_SLEEP			0x00000004
+#define RNGC_STATUS_BUSY			0x00000002
+#define RNGC_STATUS_SEC_STATE			0x00000001
+
+#define RNGC_ERROR_STATUS_ZEROS_MASK		0xffffffc0
+#define RNGC_ERROR_STATUS_BAD_KEY		0x00000040
+#define RNGC_ERROR_STATUS_RAND_ERR		0x00000020
+#define RNGC_ERROR_STATUS_FIFO_ERR		0x00000010
+#define RNGC_ERROR_STATUS_STAT_ERR		0x00000008
+#define RNGC_ERROR_STATUS_ST_ERR		0x00000004
+#define RNGC_ERROR_STATUS_OSC_ERR		0x00000002
+#define RNGC_ERROR_STATUS_LFSR_ERR		0x00000001
+
+#define RNG_ADDR_RANGE				0x34
+
+static DECLARE_COMPLETION(rng_self_testing);
+static DECLARE_COMPLETION(rng_seed_done);
+
+static struct platform_device *rng_dev;
+
+int irq_rng;
+
+static int fsl_rngc_data_present(struct hwrng *rng)
+{
+	int level;
+	u32 rngc_base = (u32) rng->priv;
+
+	/* how many random numbers are in FIFO? [0-16] */
+	level = (__raw_readl(rngc_base + RNGC_STATUS) &
+	    RNGC_STATUS_FIFO_LEVEL_MASK) >> RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+	return level > 0 ? 1 : 0;
+}
+
+static int fsl_rngc_data_read(struct hwrng *rng, u32 * data)
+{
+	int err;
+	u32 rngc_base = (u32) rng->priv;
+
+	/* retrieve a random number from FIFO */
+	*data = __raw_readl(rngc_base + RNGC_FIFO);
+
+	/* is there some error while reading this random number? */
+	err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR;
+
+	/* if error happened doesn't return random number */
+	return err ? 0 : 4;
+}
+
+static irqreturn_t rngc_irq(int irq, void *dev)
+{
+	int handled = 0;
+	u32 rngc_base = (u32) dev;
+
+	/* is the seed creation done? */
+	if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) {
+		complete(&rng_seed_done);
+		__raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+		       rngc_base + RNGC_COMMAND);
+		handled = 1;
+	}
+
+	/* is the self test done? */
+	if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) {
+		complete(&rng_self_testing);
+		__raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+			rngc_base + RNGC_COMMAND);
+		handled = 1;
+	}
+
+	/* is there any error? */
+	if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR) {
+		/* clear interrupt */
+		__raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+		       rngc_base + RNGC_COMMAND);
+		handled = 1;
+	}
+
+	return handled;
+}
+
+static int fsl_rngc_init(struct hwrng *rng)
+{
+	int err;
+	u32 cmd, ctrl, osc, rngc_base = (u32) rng->priv;
+
+	INIT_COMPLETION(rng_self_testing);
+	INIT_COMPLETION(rng_seed_done);
+
+	err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR;
+	if (err) {
+		/* is this a bad keys error ? */
+		if (__raw_readl(rngc_base + RNGC_ERROR) &
+		   RNGC_ERROR_STATUS_BAD_KEY) {
+			dev_err(&rng_dev->dev, "Can't start, Bad Keys.\n");
+			return -EIO;
+		}
+	}
+
+	/* mask all interrupts, will be unmasked soon */
+	ctrl = __raw_readl(rngc_base + RNGC_CONTROL);
+	__raw_writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR,
+	       rngc_base + RNGC_CONTROL);
+
+	/* verify if oscillator is working */
+	osc = __raw_readl(rngc_base + RNGC_ERROR);
+	if (osc & RNGC_ERROR_STATUS_OSC_ERR) {
+		dev_err(&rng_dev->dev, "RNGC Oscillator is dead!\n");
+		return -EIO;
+	}
+
+	err = request_irq(irq_rng, rngc_irq, 0, "fsl_rngc", (void *)rng->priv);
+	if (err) {
+		dev_err(&rng_dev->dev, "Can't get interrupt working.\n");
+		return -EIO;
+	}
+
+	/* do self test, repeat until get success */
+	do {
+		/* clear error */
+		cmd = __raw_readl(rngc_base + RNGC_COMMAND);
+		__raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND);
+
+		/* unmask all interrupt */
+		ctrl = __raw_readl(rngc_base + RNGC_CONTROL);
+		__raw_writel(ctrl & ~(RNGC_CTRL_MASK_DONE |
+			RNGC_CTRL_MASK_ERROR), rngc_base + RNGC_CONTROL);
+
+		/* run self test */
+		cmd = __raw_readl(rngc_base + RNGC_COMMAND);
+		__raw_writel(cmd | RNGC_CMD_SELF_TEST,
+			rngc_base + RNGC_COMMAND);
+
+		wait_for_completion(&rng_self_testing);
+
+	} while (__raw_readl(rngc_base + RNGC_ERROR) &
+		RNGC_ERROR_STATUS_ST_ERR);
+
+	/* clear interrupt. Is it really necessary here? */
+	__raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+		rngc_base + RNGC_COMMAND);
+
+	/* create seed, repeat while there is some statistical error */
+	do {
+		/* clear error */
+		cmd = __raw_readl(rngc_base + RNGC_COMMAND);
+		__raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND);
+
+		/* seed creation */
+		cmd = __raw_readl(rngc_base + RNGC_COMMAND);
+		__raw_writel(cmd | RNGC_CMD_SEED, rngc_base + RNGC_COMMAND);
+
+		wait_for_completion(&rng_seed_done);
+
+	} while (__raw_readl(rngc_base + RNGC_ERROR) &
+		RNGC_ERROR_STATUS_STAT_ERR);
+
+	err = __raw_readl(rngc_base + RNGC_ERROR) &
+					(RNGC_ERROR_STATUS_STAT_ERR |
+					RNGC_ERROR_STATUS_RAND_ERR |
+					RNGC_ERROR_STATUS_FIFO_ERR |
+					RNGC_ERROR_STATUS_ST_ERR |
+					RNGC_ERROR_STATUS_OSC_ERR |
+					RNGC_ERROR_STATUS_LFSR_ERR);
+
+	if (err) {
+		dev_err(&rng_dev->dev, "FSL RNGC appears inoperable.\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static struct hwrng fsl_rngc = {
+	.name = "fsl-rngc",
+	.init = fsl_rngc_init,
+	.data_present = fsl_rngc_data_present,
+	.data_read = fsl_rngc_data_read
+};
+
+static int __init fsl_rngc_probe(struct platform_device *pdev)
+{
+	int err = -ENODEV;
+	struct clk *clk;
+	struct resource *res, *mem;
+	void __iomem *rngc_base = NULL;
+
+	if (rng_dev)
+		return -EBUSY;
+
+	clk = clk_get(NULL, "rng_clk");
+
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "Can not get rng_clk\n");
+		err = PTR_ERR(clk);
+		return err;
+	}
+
+	clk_enable(clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res)
+		return -ENOENT;
+
+	mem = request_mem_region(res->start, res->end - res->start, pdev->name);
+
+	if (mem == NULL)
+		return -EBUSY;
+
+	dev_set_drvdata(&pdev->dev, mem);
+	rngc_base = ioremap(res->start, res->end - res->start);
+
+	fsl_rngc.priv = (unsigned long)rngc_base;
+
+	irq_rng = platform_get_irq(pdev, 0);
+
+	err = hwrng_register(&fsl_rngc);
+	if (err) {
+		dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", err);
+		return err;
+	}
+
+	rng_dev = pdev;
+
+	dev_info(&pdev->dev, "FSL RNGC Registered.\n");
+
+	return 0;
+}
+
+static int __exit fsl_rngc_remove(struct platform_device *pdev)
+{
+	struct resource *mem = dev_get_drvdata(&pdev->dev);
+	void __iomem *rngc_base = (void __iomem *)fsl_rngc.priv;
+
+	hwrng_unregister(&fsl_rngc);
+
+	release_resource(mem);
+
+	iounmap(rngc_base);
+
+	return 0;
+}
+
+static struct platform_driver fsl_rngc_driver = {
+	.driver = {
+		   .name = "fsl_rngc",
+		   .owner = THIS_MODULE,
+		   },
+	.remove = __exit_p(fsl_rngc_remove),
+};
+
+static int __init mod_init(void)
+{
+	return platform_driver_probe(&fsl_rngc_driver, fsl_rngc_probe);
+}
+
+static void __exit mod_exit(void)
+{
+	platform_driver_unregister(&fsl_rngc_driver);
+}
+
+module_init(mod_init);
+module_exit(mod_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/imx_sim.c b/drivers/char/imx_sim.c
new file mode 100644
index 000000000000..4d10f11e8012
--- /dev/null
+++ b/drivers/char/imx_sim.c
@@ -0,0 +1,1497 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_sim.c
+ *
+ * @brief Driver for Freescale IMX SIM interface
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+
+#include <linux/sched.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/poll.h>
+#include <linux/miscdevice.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/mxc_sim_interface.h>
+
+#include <asm/io.h>
+#include <mach/hardware.h>
+
+#define SIM_INTERNAL_CLK  0
+#define SIM_RFU          -1
+
+/* Default communication parameters: FI=372, DI=1, PI1=5V, II=50mA, WWT=10 */
+#define SIM_PARAM_DEFAULT { 0, 1, 1, 5, 1, 0, 0, 0, 10 }
+
+/* Transmit and receive buffer sizes */
+#define SIM_XMT_BUFFER_SIZE 256
+#define SIM_RCV_BUFFER_SIZE 256
+
+/* Interface character references */
+#define SIM_IFC_TXI(letter, number) (letter + number * 4)
+#define SIM_IFC_TA1   SIM_IFC_TXI(0, 0)
+#define SIM_IFC_TB1   SIM_IFC_TXI(0, 1)
+#define SIM_IFC_TC1   SIM_IFC_TXI(0, 2)
+#define SIM_IFC_TD1   SIM_IFC_TXI(0, 3)
+#define SIM_IFC_TA2   SIM_IFC_TXI(1, 0)
+#define SIM_IFC_TB2   SIM_IFC_TXI(1, 1)
+#define SIM_IFC_TC2   SIM_IFC_TXI(1, 2)
+#define SIM_IFC_TD2   SIM_IFC_TXI(1, 3)
+#define SIM_IFC_TA3   SIM_IFC_TXI(2, 0)
+#define SIM_IFC_TB3   SIM_IFC_TXI(2, 1)
+#define SIM_IFC_TC3   SIM_IFC_TXI(2, 2)
+#define SIM_IFC_TD3   SIM_IFC_TXI(2, 3)
+#define SIM_IFC_TA4   SIM_IFC_TXI(3, 0)
+#define SIM_IFC_TB4   SIM_IFC_TXI(3, 1)
+#define SIM_IFC_TC4   SIM_IFC_TXI(3, 2)
+#define SIM_IFC_TD4   SIM_IFC_TXI(3, 3)
+
+/* ATR and OPS states */
+#define SIM_STATE_REMOVED              0
+#define SIM_STATE_OPERATIONAL_IDLE     1
+#define SIM_STATE_OPERATIONAL_COMMAND  2
+#define SIM_STATE_OPERATIONAL_RESPONSE 3
+#define SIM_STATE_OPERATIONAL_STATUS1  4
+#define SIM_STATE_OPERATIONAL_STATUS2  5
+#define SIM_STATE_OPERATIONAL_PTS      6
+#define SIM_STATE_DETECTED_ATR_T0       7
+#define SIM_STATE_DETECTED_ATR_TS       8
+#define SIM_STATE_DETECTED_ATR_TXI      9
+#define SIM_STATE_DETECTED_ATR_THB      10
+#define SIM_STATE_DETECTED_ATR_TCK      11
+
+/* Definitions of the offset of the SIM hardware registers */
+#define PORT1_CNTL 	0x00	/* 00 */
+#define SETUP 		0x04	/* 04 */
+#define PORT1_DETECT 	0x08	/* 08 */
+#define PORT1_XMT_BUF 	0x0C	/* 0c */
+#define PORT1_RCV_BUF 	0x10	/* 10 */
+#define PORT0_CNTL 	0x14	/* 14 */
+#define CNTL 		0x18	/* 18 */
+#define CLK_PRESCALER 	0x1C	/* 1c */
+#define RCV_THRESHOLD 	0x20	/* 20 */
+#define ENABLE 		0x24	/* 24 */
+#define XMT_STATUS 	0x28	/* 28 */
+#define RCV_STATUS 	0x2C	/* 2c */
+#define INT_MASK 	0x30	/* 30 */
+#define PORTO_XMT_BUF 	0x34	/* 34 */
+#define PORT0_RCV_BUF 	0x38	/* 38 */
+#define PORT0_DETECT 	0x3C	/* 3c */
+#define DATA_FORMAT 	0x40	/* 40 */
+#define XMT_THRESHOLD 	0x44	/* 44 */
+#define GUARD_CNTL 	0x48	/* 48 */
+#define OD_CONFIG 	0x4C	/* 4c */
+#define RESET_CNTL 	0x50	/* 50 */
+#define CHAR_WAIT 	0x54	/* 54 */
+#define GPCNT 		0x58	/* 58 */
+#define DIVISOR 	0x5C	/* 5c */
+#define BWT 		0x60	/* 60 */
+#define BGT 		0x64	/* 64 */
+#define BWT_H 		0x68	/* 68 */
+#define XMT_FIFO_STAT 	0x6C	/* 6c */
+#define RCV_FIFO_CNT 	0x70	/* 70 */
+#define RCV_FIFO_WPTR 	0x74	/* 74 */
+#define RCV_FIFO_RPTR 	0x78	/* 78 */
+
+/* SIM port[0|1]_cntl register bits */
+#define SIM_PORT_CNTL_SFPD   (1<<7)
+#define SIM_PORT_CNTL_3VOLT  (1<<6)
+#define SIM_PORT_CNTL_SCSP   (1<<5)
+#define SIM_PORT_CNTL_SCEN   (1<<4)
+#define SIM_PORT_CNTL_SRST   (1<<3)
+#define SIM_PORT_CNTL_STEN   (1<<2)
+#define SIM_PORT_CNTL_SVEN   (1<<1)
+#define SIM_PORT_CNTL_SAPD   (1<<0)
+
+/* SIM od_config register bits */
+#define SIM_OD_CONFIG_OD_P1  (1<<1)
+#define SIM_OD_CONFIG_OD_P0  (1<<0)
+
+/* SIM enable register bits */
+#define SIM_ENABLE_XMTEN     (1<<1)
+#define SIM_ENABLE_RCVEN     (1<<0)
+
+/* SIM int_mask register bits */
+#define SIM_INT_MASK_RFEM    (1<<13)
+#define SIM_INT_MASK_BGTM    (1<<12)
+#define SIM_INT_MASK_BWTM    (1<<11)
+#define SIM_INT_MASK_RTM     (1<<10)
+#define SIM_INT_MASK_CWTM    (1<<9)
+#define SIM_INT_MASK_GPCM    (1<<8)
+#define SIM_INT_MASK_TDTFM   (1<<7)
+#define SIM_INT_MASK_TFOM    (1<<6)
+#define SIM_INT_MASK_XTM     (1<<5)
+#define SIM_INT_MASK_TFEIM   (1<<4)
+#define SIM_INT_MASK_ETCIM   (1<<3)
+#define SIM_INT_MASK_OIM     (1<<2)
+#define SIM_INT_MASK_TCIM    (1<<1)
+#define SIM_INT_MASK_RIM     (1<<0)
+
+/* SIM xmt_status register bits */
+#define SIM_XMT_STATUS_GPCNT (1<<8)
+#define SIM_XMT_STATUS_TDTF  (1<<7)
+#define SIM_XMT_STATUS_TFO   (1<<6)
+#define SIM_XMT_STATUS_TC    (1<<5)
+#define SIM_XMT_STATUS_ETC   (1<<4)
+#define SIM_XMT_STATUS_TFE   (1<<3)
+#define SIM_XMT_STATUS_XTE   (1<<0)
+
+/* SIM rcv_status register bits */
+#define SIM_RCV_STATUS_BGT   (1<<11)
+#define SIM_RCV_STATUS_BWT   (1<<10)
+#define SIM_RCV_STATUS_RTE   (1<<9)
+#define SIM_RCV_STATUS_CWT   (1<<8)
+#define SIM_RCV_STATUS_CRCOK (1<<7)
+#define SIM_RCV_STATUS_LRCOK (1<<6)
+#define SIM_RCV_STATUS_RDRF  (1<<5)
+#define SIM_RCV_STATUS_RFD   (1<<4)
+#define SIM_RCV_STATUS_RFE   (1<<1)
+#define SIM_RCV_STATUS_OEF   (1<<0)
+
+/* SIM cntl register bits */
+#define SIM_CNTL_BWTEN       (1<<15)
+#define SIM_CNTL_XMT_CRC_LRC (1<<14)
+#define SIM_CNTL_CRCEN       (1<<13)
+#define SIM_CNTL_LRCEN       (1<<12)
+#define SIM_CNTL_CWTEN       (1<<11)
+#define SIM_CNTL_SAMPLE12    (1<<4)
+#define SIM_CNTL_ONACK       (1<<3)
+#define SIM_CNTL_ANACK       (1<<2)
+#define SIM_CNTL_ICM         (1<<1)
+#define SIM_CNTL_GPCNT_CLK_SEL(x)   ((x&0x03)<<9)
+#define SIM_CNTL_GPCNT_CLK_SEL_MASK     (0x03<<9)
+#define SIM_CNTL_BAUD_SEL(x)        ((x&0x07)<<6)
+#define SIM_CNTL_BAUD_SEL_MASK          (0x07<<6)
+
+/* SIM rcv_threshold register bits */
+#define SIM_RCV_THRESHOLD_RTH(x)    ((x&0x0f)<<9)
+#define SIM_RCV_THRESHOLD_RTH_MASK      (0x0f<<9)
+#define SIM_RCV_THRESHOLD_RDT(x)   ((x&0x1ff)<<0)
+#define SIM_RCV_THRESHOLD_RDT_MASK     (0x1ff<<0)
+
+/* SIM xmt_threshold register bits */
+#define SIM_XMT_THRESHOLD_XTH(x)    ((x&0x0f)<<4)
+#define SIM_XMT_THRESHOLD_XTH_MASK      (0x0f<<4)
+#define SIM_XMT_THRESHOLD_TDT(x)    ((x&0x0f)<<0)
+#define SIM_XMT_THRESHOLD_TDT_MASK      (0x0f<<0)
+
+/* SIM guard_cntl register bits */
+#define SIM_GUARD_CNTL_RCVR11              (1<<8)
+#define SIM_GIARD_CNTL_GETU(x)           (x&0xff)
+#define SIM_GIARD_CNTL_GETU_MASK           (0xff)
+
+/* SIM port[0|]_detect register bits */
+#define SIM_PORT_DETECT_SPDS  (1<<3)
+#define SIM_PORT_DETECT_SPDP  (1<<2)
+#define SIM_PORT_DETECT_SDI   (1<<1)
+#define SIM_PORT_DETECT_SDIM  (1<<0)
+
+/* END of REGS definitions */
+
+/* ATR parser data (the parser state is stored in the main device structure) */
+typedef struct {
+	uint8_t T0;		/* ATR T0 */
+	uint8_t TS;		/* ATR TS */
+	/* ATR TA1, TB1, TC1, TD1, TB1, ... , TD4 */
+	uint8_t TXI[16];
+	uint8_t THB[15];	/* ATR historical bytes */
+	uint8_t TCK;		/* ATR checksum */
+	uint16_t ifc_valid;	/* valid interface characters */
+	uint8_t ifc_current_valid;	/* calid ifcs in the current batch */
+	uint8_t cnt;		/* number of current batch */
+	uint8_t num_hb;		/* number of historical bytes */
+} sim_atrparser_t;
+
+/* Main SIM driver structure */
+typedef struct {
+	/* card inserted = 1, ATR received = 2, card removed = 0 */
+	int present;
+	/* current ATR or OPS state */
+	int state;
+	/* current power state */
+	int power;
+	/* error code occured during transfer */
+	int errval;
+	struct clk *clk;	/* Clock id */
+	uint8_t clk_flag;
+	struct resource *res;	/* IO map memory */
+	void __iomem *ioaddr;	/* Mapped address */
+	int ipb_irq;		/* sim ipb IRQ num */
+	int dat_irq;		/* sim dat IRQ num */
+	/* parser for incoming ATR stream */
+	sim_atrparser_t atrparser;
+	/* raw ATR stream received */
+	sim_atr_t atr;
+	/* communication parameters according to ATR */
+	sim_param_t param_atr;
+	/* current communication parameters */
+	sim_param_t param;
+	/* current TPDU or PTS transfer */
+	sim_xfer_t xfer;
+	/* transfer is on the way = 1, idle = 2 */
+	int xfer_ongoing;
+	/* remaining bytes to transmit for the current transfer */
+	int xmt_remaining;
+	/* transmit position */
+	int xmt_pos;
+	/* receive position / number of bytes received */
+	int rcv_count;
+	uint8_t rcv_buffer[SIM_RCV_BUFFER_SIZE];
+	uint8_t xmt_buffer[SIM_XMT_BUFFER_SIZE];
+	/* transfer completion notifier */
+	struct completion xfer_done;
+	/* async notifier for card and ATR detection */
+	struct fasync_struct *fasync;
+	/* Platform specific data */
+	struct mxc_sim_platform_data *plat_data;
+} sim_t;
+
+static int sim_param_F[] = {
+	SIM_INTERNAL_CLK, 372, 558, 744, 1116, 1488, 1860, SIM_RFU,
+	SIM_RFU, 512, 768, 1024, 1536, 2048, SIM_RFU, SIM_RFU
+};
+
+static int sim_param_D[] = {
+	SIM_RFU, 64 * 1, 64 * 2, 64 * 4, 64 * 8, 64 * 16, SIM_RFU, SIM_RFU,
+	SIM_RFU, SIM_RFU, 64 * 1 / 2, 64 * 1 / 4, 64 * 1 / 8, 64 * 1 / 16,
+	64 * 1 / 32, 64 * 1 / 64
+};
+
+static struct miscdevice sim_dev;
+
+/* Function: sim_calc_param
+ *
+ * Description: determine register values depending on communication parameters
+ *
+ * Parameters:
+ * uint32_t fi             ATR frequency multiplier index
+ * uint32_t di             ATR frequency divider index
+ * uint32_t* ptr_divisor   location to store divisor result
+ * uint32_t* ptr_sample12  location to store sample12 result
+ *
+ * Return Values:
+ *  SIM_OK                          calculation finished without errors
+ * -SIM_E_PARAM_DIVISOR_RANGE       calculated divisor > 255
+ * -SIM_E_PARAM_FBYD_NOTDIVBY8OR12  F/D not divisable by 12 (as required)
+ * -SIM_E_PARAM_FBYD_WITHFRACTION   F/D has a remainder
+ * -SIM_E_PARAM_DI_INVALID          frequency multiplyer index not supported
+ * -SIM_E_PARAM_FI_INVALID          frequency divider index not supported
+ */
+
+static int sim_calc_param(uint32_t fi, uint32_t di, uint32_t *ptr_divisor,
+			  uint32_t *ptr_sample12)
+{
+	int32_t errval = SIM_OK;
+	int32_t f = sim_param_F[fi];
+	int32_t d = sim_param_D[di];
+	int32_t stage2_fra = (64 * f) % d;
+	int32_t stage2_div = (64 * f) / d;
+	uint32_t sample12 = 1;
+	uint32_t divisor = 31;
+
+	pr_debug("%s entering.\n", __func__);
+	if ((f > 0) || (d > 0)) {
+		if (stage2_fra == 0) {
+			if ((stage2_div % 12) == 0) {
+				sample12 = 1;
+				divisor = stage2_div / 12;
+			} else if ((stage2_div % 8) == 0) {
+				sample12 = 0;
+				divisor = stage2_div / 8;
+			} else
+				sample12 = -1;
+			if (sample12 >= 0) {
+				if (divisor < 256) {
+					pr_debug("fi=%i", fi);
+					pr_debug("di=%i", di);
+					pr_debug("f=%i", f);
+					pr_debug("d=%i/64", d);
+					pr_debug("div=%i", stage2_div);
+					pr_debug("divisor=%i", divisor);
+					pr_debug("sample12=%i\n", sample12);
+
+					*ptr_divisor = divisor;
+					*ptr_sample12 = sample12;
+					errval = SIM_OK;
+				} else
+					errval = -SIM_E_PARAM_DIVISOR_RANGE;
+			} else
+				errval = -SIM_E_PARAM_FBYD_NOTDIVBY8OR12;
+		} else
+			errval = -SIM_E_PARAM_FBYD_WITHFRACTION;
+	} else
+		errval = -SIM_E_PARAM_FI_INVALID;
+
+	return errval;
+};
+
+/* Function: sim_set_param
+ *
+ * Description: apply communication parameters (setup devisor and sample12)
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ * sim_param_t* param      pointer to communication parameters
+ *
+ * Return Values:
+ * see function sim_calc_param
+ */
+
+static int sim_set_param(sim_t *sim, sim_param_t *param)
+{
+	uint32_t divisor, sample12, reg_data;
+	int errval;
+
+	pr_debug("%s entering.\n", __func__);
+	errval = sim_calc_param(param->FI, param->DI, &divisor, &sample12);
+	if (errval == SIM_OK) {
+		__raw_writel(divisor, sim->ioaddr + DIVISOR);
+		if (sample12) {
+			reg_data = __raw_readl(sim->ioaddr + CNTL);
+			reg_data |= SIM_CNTL_SAMPLE12;
+			__raw_writel(reg_data, sim->ioaddr + CNTL);
+		} else {
+			reg_data = __raw_readl(sim->ioaddr + CNTL);
+			reg_data &= ~SIM_CNTL_SAMPLE12;
+			__raw_writel(reg_data, sim->ioaddr + CNTL);
+		}
+	}
+
+	return errval;
+};
+
+/* Function: sim_atr_received
+ *
+ * Description: this function is called whenever a valid ATR has been received.
+ * It determines the communication parameters from the ATR received and notifies
+ * the user space application with SIGIO.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_atr_received(sim_t *sim)
+{
+	sim_param_t param_default = SIM_PARAM_DEFAULT;
+	sim->param_atr = param_default;
+
+	pr_debug("%s entering.\n", __func__);
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TA1))) {
+		sim->param_atr.FI = sim->atrparser.TXI[SIM_IFC_TA1] >> 4;
+		sim->param_atr.DI = sim->atrparser.TXI[SIM_IFC_TA1] & 0x0f;
+	}
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TB1))) {
+		sim->param_atr.PI1 = (sim->atrparser.TXI[SIM_IFC_TB1] >> 4)
+		    & 0x07;
+		sim->param_atr.II = sim->atrparser.TXI[SIM_IFC_TB1] & 0x07f;
+	}
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TC1)))
+		sim->param_atr.N = sim->atrparser.TXI[SIM_IFC_TC1];
+
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TD1)))
+		sim->param_atr.T = sim->atrparser.TXI[SIM_IFC_TD1] & 0x0f;
+
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TB2)))
+		sim->param_atr.PI2 = sim->atrparser.TXI[SIM_IFC_TB2];
+
+	if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TC2)))
+		sim->param_atr.WWT = sim->atrparser.TXI[SIM_IFC_TC2];
+
+	if (sim->fasync)
+		kill_fasync(&sim->fasync, SIGIO, POLL_IN);
+
+};
+
+/* Function: sim_xmt_fill
+ *
+ * Description: fill the transmit FIFO until the FIFO is full or
+ * the end of the transmission has been reached.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_xmt_fill(sim_t *sim)
+{
+	uint32_t reg_data;
+	int bytesleft;
+
+	reg_data = __raw_readl(sim->ioaddr + XMT_FIFO_STAT);
+	bytesleft = 16 - ((reg_data >> 8) & 0x0f);
+
+	pr_debug("txfill: remaining=%i bytesleft=%i\n",
+		 sim->xmt_remaining, bytesleft);
+	if (bytesleft > sim->xmt_remaining)
+		bytesleft = sim->xmt_remaining;
+
+	sim->xmt_remaining -= bytesleft;
+	for (; bytesleft > 0; bytesleft--) {
+		__raw_writel(sim->xmt_buffer[sim->xmt_pos],
+			     sim->ioaddr + PORT1_XMT_BUF);
+		sim->xmt_pos++;
+	};
+/* FIXME: optimization - keep filling until fifo full */
+};
+
+/* Function: sim_xmt_start
+ *
+ * Description: initiate a transfer
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ * int pos                 position in the xfer transmit buffer
+ * int count               number of bytes to be transmitted
+ */
+
+static void sim_xmt_start(sim_t *sim, int pos, int count)
+{
+	uint32_t reg_data;
+
+	pr_debug("tx\n");
+	sim->xmt_remaining = count;
+	sim->xmt_pos = pos;
+	sim_xmt_fill(sim);
+
+	if (sim->xmt_remaining) {
+		reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+		reg_data &= ~SIM_INT_MASK_TDTFM;
+		__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+	} else {
+		reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+		reg_data &= ~SIM_INT_MASK_TCIM;
+		__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+		__raw_writel(SIM_XMT_STATUS_TC | SIM_XMT_STATUS_TDTF,
+			     sim->ioaddr + XMT_STATUS);
+		reg_data = __raw_readl(sim->ioaddr + ENABLE);
+		reg_data |= SIM_ENABLE_XMTEN;
+		__raw_writel(reg_data, sim->ioaddr + ENABLE);
+	}
+};
+
+/* Function: sim_atr_add
+ *
+ * Description: add a byte to the raw ATR string
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ * uint8_t data            byte to be added
+ */
+
+static void sim_atr_add(sim_t *sim, uint8_t data)
+{
+	pr_debug("%s entering.\n", __func__);
+	if (sim->atr.size < SIM_ATR_LENGTH_MAX)
+		sim->atr.t[sim->atr.size++] = data;
+	else
+		printk(KERN_ERR "sim.c: ATR received is too big!\n");
+};
+
+/* Function: sim_fsm
+ *
+ * Description: main finite state machine running in ISR context.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ * uint8_t data            byte received
+ */
+
+static void sim_fsm(sim_t *sim, uint16_t data)
+{
+	uint32_t temp, i = 0;
+	switch (sim->state) {
+
+		pr_debug("%s stat is %d \n", __func__, sim->state);
+		/* OPS FSM */
+
+	case SIM_STATE_OPERATIONAL_IDLE:
+		printk(KERN_INFO "data received unexpectidly (%04x)\n", data);
+		break;
+
+	case SIM_STATE_OPERATIONAL_COMMAND:
+		if (data == sim->xmt_buffer[1]) {
+			if (sim->xfer.rcv_length) {
+				sim->state = SIM_STATE_OPERATIONAL_RESPONSE;
+			} else {
+				sim->state = SIM_STATE_OPERATIONAL_STATUS1;
+				if (sim->xfer.xmt_length > 5)
+					sim_xmt_start(sim, 5,
+						      sim->xfer.xmt_length - 5);
+			};
+		} else if (((data & 0xf0) == 0x60) | ((data & 0xf0) == 0x90)) {
+			sim->xfer.sw1 = data;
+			sim->state = SIM_STATE_OPERATIONAL_STATUS2;
+		} else {
+			sim->errval = -SIM_E_NACK;
+			complete(&sim->xfer_done);
+		};
+		break;
+
+	case SIM_STATE_OPERATIONAL_RESPONSE:
+		sim->rcv_buffer[sim->rcv_count] = data;
+		sim->rcv_count++;
+		if (sim->rcv_count == sim->xfer.rcv_length)
+			sim->state = SIM_STATE_OPERATIONAL_STATUS1;
+		break;
+
+	case SIM_STATE_OPERATIONAL_STATUS1:
+		sim->xfer.sw1 = data;
+		sim->state = SIM_STATE_OPERATIONAL_STATUS2;
+		break;
+
+	case SIM_STATE_OPERATIONAL_STATUS2:
+		sim->xfer.sw2 = data;
+		sim->state = SIM_STATE_OPERATIONAL_IDLE;
+		complete(&sim->xfer_done);
+		break;
+
+	case SIM_STATE_OPERATIONAL_PTS:
+		sim->rcv_buffer[sim->rcv_count] = data;
+		sim->rcv_count++;
+		if (sim->rcv_count == sim->xfer.rcv_length)
+			sim->state = SIM_STATE_OPERATIONAL_IDLE;
+		break;
+
+		/* ATR FSM */
+
+	case SIM_STATE_DETECTED_ATR_T0:
+		sim_atr_add(sim, data);
+		pr_debug("T0 %02x\n", data);
+		sim->atrparser.T0 = data;
+		sim->state = SIM_STATE_DETECTED_ATR_TS;
+		break;
+
+	case SIM_STATE_DETECTED_ATR_TS:
+		sim_atr_add(sim, data);
+		pr_debug("TS %02x\n", data);
+		sim->atrparser.TS = data;
+		if (data & 0xf0) {
+			sim->atrparser.ifc_current_valid = (data >> 4) & 0x0f;
+			sim->atrparser.num_hb = data & 0x0f;
+			sim->atrparser.ifc_valid = 0;
+			sim->state = SIM_STATE_DETECTED_ATR_TXI;
+			sim->atrparser.cnt = 0;
+		} else {
+			goto sim_fsm_atr_thb;
+		};
+		break;
+
+	case SIM_STATE_DETECTED_ATR_TXI:
+		sim_atr_add(sim, data);
+		i = ffs(sim->atrparser.ifc_current_valid) - 1;
+		pr_debug("T%c%i %02x\n", 'A' + i, sim->atrparser.cnt + 1, data);
+		sim->atrparser.TXI[SIM_IFC_TXI(i, sim->atrparser.cnt)] = data;
+		sim->atrparser.ifc_valid |= 1 << SIM_IFC_TXI(i,
+							     sim->atrparser.
+							     cnt);
+		sim->atrparser.ifc_current_valid &= ~(1 << i);
+
+		if (sim->atrparser.ifc_current_valid == 0) {
+			if (i == 3) {
+				sim->atrparser.ifc_current_valid = (data >> 4)
+				    & 0x0f;
+				sim->atrparser.cnt++;
+
+				if (sim->atrparser.cnt >= 4) {
+					/* error */
+					printk(KERN_ERR "ERROR !\n");
+					break;
+				};
+
+				if (sim->atrparser.ifc_current_valid == 0)
+					goto sim_fsm_atr_thb;
+			} else {
+sim_fsm_atr_thb:
+				if (sim->atrparser.num_hb) {
+					sim->state = SIM_STATE_DETECTED_ATR_THB;
+					sim->atrparser.cnt = 0;
+				} else {
+					goto sim_fsm_atr_tck;
+				};
+			};
+		};
+		break;
+
+	case SIM_STATE_DETECTED_ATR_THB:
+		sim_atr_add(sim, data);
+		pr_debug("THB%i %02x\n", i, data);
+		sim->atrparser.THB[sim->atrparser.cnt] = data;
+		sim->atrparser.cnt++;
+
+		if (sim->atrparser.cnt == sim->atrparser.num_hb) {
+sim_fsm_atr_tck:
+			i = sim->atrparser.ifc_valid & (1 << (SIM_IFC_TD1));
+			temp = sim->atrparser.TXI[SIM_IFC_TD1] & 0x0f;
+			if ((i && temp) == SIM_PROTOCOL_T1)
+				sim->state = SIM_STATE_DETECTED_ATR_TCK;
+			else
+				goto sim_fsm_atr_received;
+		};
+		break;
+
+	case SIM_STATE_DETECTED_ATR_TCK:
+		sim_atr_add(sim, data);
+		/* checksum not required for T=0 */
+		sim->atrparser.TCK = data;
+sim_fsm_atr_received:
+		sim->state = SIM_STATE_OPERATIONAL_IDLE;
+		sim->present = SIM_PRESENT_OPERATIONAL;
+		sim_atr_received(sim);
+		break;
+	};
+};
+
+/* Function: sim_irq_handler
+ *
+ * Description: interrupt service routine.
+ *
+ * Parameters:
+ * int irq                 interrupt number
+ * void *dev_id            pointer to SIM device handler
+ *
+ * Return values:
+ * IRQ_HANDLED             OS specific
+ */
+
+static irqreturn_t sim_irq_handler(int irq, void *dev_id)
+{
+	uint32_t reg_data, reg_data0, reg_data1;
+
+	sim_t *sim = (sim_t *) dev_id;
+
+	pr_debug("%s entering\n", __func__);
+
+	reg_data0 = __raw_readl(sim->ioaddr + XMT_STATUS);
+	reg_data1 = __raw_readl(sim->ioaddr + INT_MASK);
+	if ((reg_data0 & SIM_XMT_STATUS_TC)
+	    && (!(reg_data1 & SIM_INT_MASK_TCIM))) {
+		pr_debug("TC_IRQ\n");
+		__raw_writel(SIM_XMT_STATUS_TC, sim->ioaddr + XMT_STATUS);
+		reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+		reg_data |= SIM_INT_MASK_TCIM;
+		__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+		reg_data = __raw_readl(sim->ioaddr + ENABLE);
+		reg_data &= ~SIM_ENABLE_XMTEN;
+		__raw_writel(reg_data, sim->ioaddr + ENABLE);
+	};
+
+	reg_data0 = __raw_readl(sim->ioaddr + XMT_STATUS);
+	reg_data1 = __raw_readl(sim->ioaddr + INT_MASK);
+	if ((reg_data0 & SIM_XMT_STATUS_TDTF)
+	    && (!(reg_data1 & SIM_INT_MASK_TDTFM))) {
+		pr_debug("TDTF_IRQ\n");
+		__raw_writel(SIM_XMT_STATUS_TDTF, sim->ioaddr + XMT_STATUS);
+		sim_xmt_fill(sim);
+
+		if (sim->xmt_remaining == 0) {
+			__raw_writel(SIM_XMT_STATUS_TC,
+				     sim->ioaddr + XMT_STATUS);
+			reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+			reg_data &= ~SIM_INT_MASK_TCIM;
+			reg_data |= SIM_INT_MASK_TDTFM;
+			__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+		};
+	};
+
+	reg_data0 = __raw_readl(sim->ioaddr + RCV_STATUS);
+	reg_data1 = __raw_readl(sim->ioaddr + INT_MASK);
+	if ((reg_data0 & SIM_RCV_STATUS_RDRF)
+	    && (!(reg_data1 & SIM_INT_MASK_RIM))) {
+		pr_debug("%s RDRF_IRQ\n", __func__);
+		__raw_writel(SIM_RCV_STATUS_RDRF, sim->ioaddr + RCV_STATUS);
+
+		while (__raw_readl(sim->ioaddr + RCV_FIFO_CNT)) {
+			uint32_t data;
+			data = __raw_readl(sim->ioaddr + PORT1_RCV_BUF);
+			pr_debug("RX = %02x state = %i\n", data, sim->state);
+			if (data & 0x700) {
+				if (sim->xfer_ongoing) {
+					/* error */
+					printk(KERN_ERR "ERROR !\n");
+					return IRQ_HANDLED;
+				};
+			} else
+				sim_fsm(sim, data);
+		};
+	};
+
+	reg_data0 = __raw_readl(sim->ioaddr + PORT0_DETECT);
+	if (reg_data0 & SIM_PORT_DETECT_SDI) {
+		pr_debug("%s PD_IRQ\n", __func__);
+		reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+		reg_data |= SIM_PORT_DETECT_SDI;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+
+		reg_data0 = __raw_readl(sim->ioaddr + PORT0_DETECT);
+		if (reg_data0 & SIM_PORT_DETECT_SPDP) {
+			reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+			reg_data &= ~SIM_PORT_DETECT_SPDS;
+			__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+
+			if (sim->present != SIM_PRESENT_REMOVED) {
+				pr_debug("Removed sim card\n");
+				sim->present = SIM_PRESENT_REMOVED;
+				sim->state = SIM_STATE_REMOVED;
+
+				if (sim->fasync)
+					kill_fasync(&sim->fasync,
+						    SIGIO, POLL_IN);
+			};
+		} else {
+			reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+			reg_data |= SIM_PORT_DETECT_SPDS;
+			__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+
+			if (sim->present == SIM_PRESENT_REMOVED) {
+				pr_debug("Inserted sim card\n");
+				sim->state = SIM_STATE_DETECTED_ATR_T0;
+				sim->present = SIM_PRESENT_DETECTED;
+
+				if (sim->fasync)
+					kill_fasync(&sim->fasync,
+						    SIGIO, POLL_IN);
+			};
+		};
+	};
+
+	return IRQ_HANDLED;
+};
+
+/* Function: sim_power_on
+ *
+ * Description: run the power on sequence
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_power_on(sim_t *sim)
+{
+	uint32_t reg_data;
+
+	/* power on sequence */
+	pr_debug("%s Powering on the sim port.\n", __func__);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data |= SIM_PORT_CNTL_SVEN;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	msleep(10);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data |= SIM_PORT_CNTL_SCEN;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	msleep(10);
+	reg_data = SIM_RCV_THRESHOLD_RTH(0) | SIM_RCV_THRESHOLD_RDT(1);
+	__raw_writel(reg_data, sim->ioaddr + RCV_THRESHOLD);
+	__raw_writel(SIM_RCV_STATUS_RDRF, sim->ioaddr + RCV_STATUS);
+	reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+	reg_data &= ~SIM_INT_MASK_RIM;
+	__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+	__raw_writel(31, sim->ioaddr + DIVISOR);
+	reg_data = __raw_readl(sim->ioaddr + CNTL);
+	reg_data |= SIM_CNTL_SAMPLE12;
+	__raw_writel(reg_data, sim->ioaddr + CNTL);
+	reg_data = __raw_readl(sim->ioaddr + ENABLE);
+	reg_data |= SIM_ENABLE_RCVEN;
+	__raw_writel(reg_data, sim->ioaddr + ENABLE);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data |= SIM_PORT_CNTL_SRST;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	pr_debug("%s port0_ctl is 0x%x.\n", __func__,
+		 __raw_readl(sim->ioaddr + PORT0_CNTL));
+	sim->power = SIM_POWER_ON;
+};
+
+/* Function: sim_power_off
+ *
+ * Description: run the power off sequence
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_power_off(sim_t *sim)
+{
+	uint32_t reg_data;
+
+	pr_debug("%s entering.\n", __func__);
+	/* sim_power_off sequence */
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data &= ~SIM_PORT_CNTL_SCEN;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	reg_data = __raw_readl(sim->ioaddr + ENABLE);
+	reg_data &= ~SIM_ENABLE_RCVEN;
+	__raw_writel(reg_data, sim->ioaddr + ENABLE);
+	reg_data = __raw_readl(sim->ioaddr + INT_MASK);
+	reg_data |= SIM_INT_MASK_RIM;
+	__raw_writel(reg_data, sim->ioaddr + INT_MASK);
+	__raw_writel(0, sim->ioaddr + RCV_THRESHOLD);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data &= ~SIM_PORT_CNTL_SRST;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data &= ~SIM_PORT_CNTL_SVEN;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	sim->power = SIM_POWER_OFF;
+};
+
+/* Function: sim_start
+ *
+ * Description: ramp up the SIM interface
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_start(sim_t *sim)
+{
+	uint32_t reg_data, clk_rate, clk_div = 0;
+
+	pr_debug("%s entering.\n", __func__);
+	/* Configuring SIM for Operation */
+	reg_data = SIM_XMT_THRESHOLD_XTH(0) | SIM_XMT_THRESHOLD_TDT(4);
+	__raw_writel(reg_data, sim->ioaddr + XMT_THRESHOLD);
+	__raw_writel(0, sim->ioaddr + SETUP);
+	/* ~ 4 MHz */
+	clk_rate = clk_get_rate(sim->clk);
+	clk_div = clk_rate / sim->plat_data->clk_rate;
+	if (clk_rate % sim->plat_data->clk_rate)
+		clk_div++;
+	pr_debug("%s prescaler is 0x%x.\n", __func__, clk_div);
+	__raw_writel(clk_div, sim->ioaddr + CLK_PRESCALER);
+
+	reg_data = SIM_CNTL_GPCNT_CLK_SEL(0) | SIM_CNTL_BAUD_SEL(7)
+	    | SIM_CNTL_SAMPLE12 | SIM_CNTL_ANACK | SIM_CNTL_ICM;
+	__raw_writel(reg_data, sim->ioaddr + CNTL);
+	__raw_writel(31, sim->ioaddr + DIVISOR);
+	reg_data = __raw_readl(sim->ioaddr + OD_CONFIG);
+	reg_data |= SIM_OD_CONFIG_OD_P0;
+	__raw_writel(reg_data, sim->ioaddr + OD_CONFIG);
+	reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+	reg_data |= SIM_PORT_CNTL_3VOLT | SIM_PORT_CNTL_STEN;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+
+	/* presense detect */
+	pr_debug("%s p0_det is 0x%x \n", __func__,
+		 __raw_readl(sim->ioaddr + PORT0_DETECT));
+	if (__raw_readl(sim->ioaddr + PORT0_DETECT) & SIM_PORT_DETECT_SPDP) {
+		pr_debug("%s card removed \n", __func__);
+		reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+		reg_data &= ~SIM_PORT_DETECT_SPDS;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+		sim->present = SIM_PRESENT_REMOVED;
+		sim->state = SIM_STATE_REMOVED;
+	} else {
+		pr_debug("%s card inserted \n", __func__);
+		reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+		reg_data |= SIM_PORT_DETECT_SPDS;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+		sim->present = SIM_PRESENT_DETECTED;
+		sim->state = SIM_STATE_DETECTED_ATR_T0;
+	};
+	reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+	reg_data |= SIM_PORT_DETECT_SDI;
+	reg_data &= ~SIM_PORT_DETECT_SDIM;
+	__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+
+	/*
+	 * Since there is no PD0 layout on MX51, assume
+	 * that there is a SIM card in slot defaulty.
+	 * */
+	if (0 == (sim->plat_data->detect)) {
+		reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+		reg_data |= SIM_PORT_DETECT_SPDS;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_DETECT);
+		sim->present = SIM_PRESENT_DETECTED;
+		sim->state = SIM_STATE_DETECTED_ATR_T0;
+	}
+
+	if (sim->present == SIM_PRESENT_DETECTED)
+		sim_power_on(sim);
+
+};
+
+/* Function: sim_stop
+ *
+ * Description: shut down the SIM interface
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_stop(sim_t *sim)
+{
+	pr_debug("%s entering.\n", __func__);
+	__raw_writel(0, sim->ioaddr + SETUP);
+	__raw_writel(0, sim->ioaddr + ENABLE);
+	__raw_writel(0, sim->ioaddr + PORT0_CNTL);
+	__raw_writel(0x06, sim->ioaddr + CNTL);
+	__raw_writel(0, sim->ioaddr + CLK_PRESCALER);
+	__raw_writel(0, sim->ioaddr + SETUP);
+	__raw_writel(0, sim->ioaddr + OD_CONFIG);
+	__raw_writel(0, sim->ioaddr + XMT_THRESHOLD);
+	__raw_writel(0xb8, sim->ioaddr + XMT_STATUS);
+	__raw_writel(4, sim->ioaddr + RESET_CNTL);
+	mdelay(1);
+};
+
+/* Function: sim_data_reset
+ *
+ * Description: reset a SIM structure to default values
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_data_reset(sim_t *sim)
+{
+	sim_param_t param_default = SIM_PARAM_DEFAULT;
+	sim->present = SIM_PRESENT_REMOVED;
+	sim->state = SIM_STATE_REMOVED;
+	sim->power = SIM_POWER_OFF;
+	sim->errval = SIM_OK;
+	memset(&sim->atrparser, 0, sizeof(sim->atrparser));
+	memset(&sim->atr, 0, sizeof(sim->atr));
+	sim->param_atr = param_default;
+	memset(&sim->param, 0, sizeof(sim->param));
+	memset(&sim->xfer, 0, sizeof(sim->xfer));
+	sim->xfer_ongoing = 0;
+	sim->xmt_remaining = 0;
+	sim->xmt_pos = 0;
+	sim->rcv_count = 0;
+	memset(sim->rcv_buffer, 0, SIM_RCV_BUFFER_SIZE);
+	memset(sim->xmt_buffer, 0, SIM_XMT_BUFFER_SIZE);
+};
+
+/* Function: sim_cold_reset
+ *
+ * Description: cold reset the SIM interface, including card
+ * power down and interface hardware reset.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_cold_reset(sim_t *sim)
+{
+	pr_debug("%s entering.\n", __func__);
+	if (sim->present != SIM_PRESENT_REMOVED) {
+		sim_power_off(sim);
+		sim_stop(sim);
+		sim_data_reset(sim);
+		sim->state = SIM_STATE_DETECTED_ATR_T0;
+		sim->present = SIM_PRESENT_DETECTED;
+		msleep(50);
+		sim_start(sim);
+		sim_power_on(sim);
+	};
+};
+
+/* Function: sim_warm_reset
+ *
+ * Description: warm reset the SIM interface: just invoke the
+ * reset signal and reset the SIM structure for the interface.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static void sim_warm_reset(sim_t *sim)
+{
+	uint32_t reg_data;
+
+	pr_debug("%s entering.\n", __func__);
+	if (sim->present != SIM_PRESENT_REMOVED) {
+		reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+		reg_data |= SIM_PORT_CNTL_SRST;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+		sim_data_reset(sim);
+		msleep(50);
+		reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL);
+		reg_data &= ~SIM_PORT_CNTL_SRST;
+		__raw_writel(reg_data, sim->ioaddr + PORT0_CNTL);
+	};
+};
+
+/* Function: sim_card_lock
+ *
+ * Description: physically lock the SIM card.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static int sim_card_lock(sim_t *sim)
+{
+	int errval;
+
+	pr_debug("%s entering.\n", __func__);
+	/* place holder for true physcial locking */
+	if (sim->present != SIM_PRESENT_REMOVED)
+		errval = SIM_OK;
+	else
+		errval = -SIM_E_NOCARD;
+	return errval;
+};
+
+/* Function: sim_card_eject
+ *
+ * Description: physically unlock and eject the SIM card.
+ *
+ * Parameters:
+ * sim_t* sim              pointer to SIM device handler
+ */
+
+static int sim_card_eject(sim_t *sim)
+{
+	int errval;
+
+	pr_debug("%s entering.\n", __func__);
+	/* place holder for true physcial locking */
+	if (sim->present != SIM_PRESENT_REMOVED)
+		errval = SIM_OK;
+	else
+		errval = -SIM_E_NOCARD;
+	return errval;
+};
+
+/* Function: sim_ioctl
+ *
+ * Description: handle ioctl calls
+ *
+ * Parameters: OS specific
+ */
+
+static int sim_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, unsigned long arg)
+{
+	int ret, errval = SIM_OK;
+	unsigned long timeout;
+
+	sim_t *sim = (sim_t *) file->private_data;
+
+	pr_debug("%s entering.\n", __func__);
+	switch (cmd) {
+		pr_debug("ioctl cmd %d is issued...\n", cmd);
+
+	case SIM_IOCTL_GET_ATR:
+		if (sim->present != SIM_PRESENT_OPERATIONAL) {
+			errval = -SIM_E_NOCARD;
+			break;
+		};
+		ret = copy_to_user((sim_atr_t *) arg, &sim->atr,
+				   sizeof(sim_atr_t));
+		if (ret)
+			errval = -SIM_E_ACCESS;
+		break;
+
+	case SIM_IOCTL_GET_PARAM_ATR:
+		if (sim->present != SIM_PRESENT_OPERATIONAL) {
+			errval = -SIM_E_NOCARD;
+			break;
+		};
+		ret = copy_to_user((sim_param_t *) arg, &sim->param_atr,
+				   sizeof(sim_param_t));
+		if (ret)
+			errval = -SIM_E_ACCESS;
+		break;
+
+	case SIM_IOCTL_GET_PARAM:
+		ret = copy_to_user((sim_param_t *) arg, &sim->param,
+				   sizeof(sim_param_t));
+		if (ret)
+			errval = -SIM_E_ACCESS;
+		break;
+
+	case SIM_IOCTL_SET_PARAM:
+		ret = copy_from_user(&sim->param, (sim_param_t *) arg,
+				     sizeof(sim_param_t));
+		if (ret)
+			errval = -SIM_E_ACCESS;
+		else
+			errval = sim_set_param(sim, &sim->param);
+		break;
+
+	case SIM_IOCTL_POWER_ON:
+		if (sim->power == SIM_POWER_ON) {
+			errval = -SIM_E_POWERED_ON;
+			break;
+		};
+		sim_power_on(sim);
+		break;
+
+	case SIM_IOCTL_POWER_OFF:
+		if (sim->power == SIM_POWER_OFF) {
+			errval = -SIM_E_POWERED_OFF;
+			break;
+		};
+		sim_power_off(sim);
+		break;
+
+	case SIM_IOCTL_COLD_RESET:
+		if (sim->power == SIM_POWER_OFF) {
+			errval = -SIM_E_POWERED_OFF;
+			break;
+		};
+		sim_cold_reset(sim);
+		break;
+
+	case SIM_IOCTL_WARM_RESET:
+		sim_warm_reset(sim);
+		if (sim->power == SIM_POWER_OFF) {
+			errval = -SIM_E_POWERED_OFF;
+			break;
+		};
+		break;
+
+	case SIM_IOCTL_XFER:
+		if (sim->present != SIM_PRESENT_OPERATIONAL) {
+			errval = -SIM_E_NOCARD;
+			break;
+		};
+
+		ret = copy_from_user(&sim->xfer, (sim_xfer_t *) arg,
+				     sizeof(sim_xfer_t));
+		if (ret) {
+			errval = -SIM_E_ACCESS;
+			break;
+		};
+
+		ret = copy_from_user(sim->xmt_buffer, sim->xfer.xmt_buffer,
+				     sim->xfer.xmt_length);
+		if (ret) {
+			errval = -SIM_E_ACCESS;
+			break;
+		};
+
+		sim->rcv_count = 0;
+		sim->xfer.sw1 = 0;
+		sim->xfer.sw2 = 0;
+
+		if (sim->xfer.type == SIM_XFER_TYPE_TPDU) {
+			if (sim->xfer.xmt_length < 5) {
+				errval = -SIM_E_TPDUSHORT;
+				break;
+			}
+			sim->state = SIM_STATE_OPERATIONAL_COMMAND;
+		} else if (sim->xfer.type == SIM_XFER_TYPE_PTS) {
+			if (sim->xfer.xmt_length == 0) {
+				errval = -SIM_E_PTSEMPTY;
+				break;
+			}
+			sim->state = SIM_STATE_OPERATIONAL_PTS;
+		} else {
+			errval = -SIM_E_INVALIDXFERTYPE;
+			break;
+		};
+
+		if (sim->xfer.xmt_length > SIM_XMT_BUFFER_SIZE) {
+			errval = -SIM_E_INVALIDXMTLENGTH;
+			break;
+		};
+
+		if (sim->xfer.rcv_length > SIM_XMT_BUFFER_SIZE) {
+			errval = -SIM_E_INVALIDRCVLENGTH;
+			break;
+		};
+
+		sim->errval = 0;
+		sim->xfer_ongoing = 1;
+		init_completion(&sim->xfer_done);
+		sim_xmt_start(sim, 0, 5);
+		timeout =
+		    wait_for_completion_interruptible_timeout(&sim->xfer_done,
+							      sim->xfer.
+							      timeout);
+		sim->xfer_ongoing = 0;
+
+		if (sim->errval) {
+			errval = sim->errval;
+			break;
+		};
+
+		if (timeout == 0) {
+			errval = -SIM_E_TIMEOUT;
+			break;
+		}
+
+		ret = copy_to_user(sim->xfer.rcv_buffer, sim->rcv_buffer,
+				   sim->xfer.rcv_length);
+		if (ret) {
+			errval = -SIM_E_ACCESS;
+			break;
+		};
+
+		ret = copy_to_user((sim_xfer_t *) arg, &sim->xfer,
+				   sizeof(sim_xfer_t));
+		if (ret)
+			errval = -SIM_E_ACCESS;
+		break;
+
+	case SIM_IOCTL_GET_PRESENSE:
+		if (put_user(sim->present, (int *)arg))
+			errval = -SIM_E_ACCESS;
+		break;
+
+	case SIM_IOCTL_CARD_LOCK:
+		errval = sim_card_lock(sim);
+		break;
+
+	case SIM_IOCTL_CARD_EJECT:
+		errval = sim_card_eject(sim);
+		break;
+
+	};
+
+	return errval;
+};
+
+/* Function: sim_fasync
+ *
+ * Description: async handler
+ *
+ * Parameters: OS specific
+ */
+
+static int sim_fasync(int fd, struct file *file, int mode)
+{
+	sim_t *sim = (sim_t *) file->private_data;
+	pr_debug("%s entering.\n", __func__);
+	return fasync_helper(fd, file, mode, &sim->fasync);
+}
+
+/* Function: sim_open
+ *
+ * Description: ramp up interface when being opened
+ *
+ * Parameters: OS specific
+ */
+
+static int sim_open(struct inode *inode, struct file *file)
+{
+	int errval = SIM_OK;
+
+	sim_t *sim = dev_get_drvdata(sim_dev.parent);
+	file->private_data = sim;
+
+	pr_debug("%s entering.\n", __func__);
+	if (!sim->ioaddr) {
+		errval = -ENOMEM;
+		return errval;
+	}
+
+	if (!(sim->clk_flag)) {
+		pr_debug("\n%s enable the clock\n", __func__);
+		clk_enable(sim->clk);
+		sim->clk_flag = 1;
+	}
+
+	sim_start(sim);
+
+	return errval;
+};
+
+/* Function: sim_release
+ *
+ * Description: shut down interface when being closed
+ *
+ * Parameters: OS specific
+ */
+
+static int sim_release(struct inode *inode, struct file *file)
+{
+	uint32_t reg_data;
+
+	sim_t *sim = (sim_t *) file->private_data;
+
+	pr_debug("%s entering.\n", __func__);
+	if (sim->clk_flag) {
+		pr_debug("\n%s disable the clock\n", __func__);
+		clk_disable(sim->clk);
+		sim->clk_flag = 0;
+	}
+
+	/* disable presense detection */
+	reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT);
+	__raw_writel(reg_data | SIM_PORT_DETECT_SDIM,
+		     sim->ioaddr + PORT0_DETECT);
+
+	if (sim->present != SIM_PRESENT_REMOVED) {
+		sim_power_off(sim);
+		if (sim->fasync)
+			kill_fasync(&sim->fasync, SIGIO, POLL_IN);
+	};
+
+	sim_stop(sim);
+
+	sim_fasync(-1, file, 0);
+
+	pr_debug("exit\n");
+	return 0;
+};
+
+static const struct file_operations sim_fops = {
+	.open = sim_open,
+	.ioctl = sim_ioctl,
+	.fasync = sim_fasync,
+	.release = sim_release
+};
+
+static struct miscdevice sim_dev = {
+	MISC_DYNAMIC_MINOR,
+	"mxc_sim",
+	&sim_fops
+};
+
+/*****************************************************************************\
+ *                                                                           *
+ * Driver init/exit                                                          *
+ *                                                                           *
+\*****************************************************************************/
+
+static int sim_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_sim_platform_data *sim_plat = pdev->dev.platform_data;
+
+	sim_t *sim = kzalloc(sizeof(sim_t), GFP_KERNEL);
+
+	if (sim == 0) {
+		ret = -ENOMEM;
+		printk(KERN_ERR "Can't get the MEMORY\n");
+		return ret;
+	};
+
+	BUG_ON(pdev == NULL);
+
+	sim->plat_data = sim_plat;
+	sim->clk_flag = 0;
+
+	sim->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!sim->res) {
+		ret = -ENOMEM;
+		printk(KERN_ERR "Can't get the MEMORY\n");
+		goto out;
+	}
+
+	/* request the sim clk and sim_serial_clk */
+	sim->clk = clk_get(NULL, sim->plat_data->clock_sim);
+	if (IS_ERR(sim->clk)) {
+		ret = PTR_ERR(sim->clk);
+		printk(KERN_ERR "Get CLK ERROR !\n");
+		goto out;
+	}
+	pr_debug("sim clock:%lu\n", clk_get_rate(sim->clk));
+
+	sim->ipb_irq = platform_get_irq(pdev, 0);
+	sim->dat_irq = platform_get_irq(pdev, 1);
+	if (!(sim->ipb_irq | sim->dat_irq)) {
+		ret = -ENOMEM;
+		goto out1;
+	}
+
+	if (!request_mem_region(sim->res->start,
+				sim->res->end -
+				sim->res->start + 1, pdev->name)) {
+		printk(KERN_ERR "request_mem_region failed\n");
+		ret = -ENOMEM;
+		goto out1;
+	}
+
+	sim->ioaddr = (void *)ioremap(sim->res->start, sim->res->end -
+				      sim->res->start + 1);
+	if (sim->ipb_irq)
+		ret = request_irq(sim->ipb_irq, sim_irq_handler,
+				  0, "mxc_sim_ipb", sim);
+	if (sim->dat_irq)
+		ret |= request_irq(sim->dat_irq, sim_irq_handler,
+				   0, "mxc_sim_dat", sim);
+
+	if (ret) {
+		printk(KERN_ERR "Can't get the irq\n");
+		goto out2;
+	};
+
+	platform_set_drvdata(pdev, sim);
+	sim_dev.parent = &(pdev->dev);
+
+	misc_register(&sim_dev);
+
+	return ret;
+out2:
+	if (sim->ipb_irq)
+		free_irq(sim->ipb_irq, sim);
+	if (sim->dat_irq)
+		free_irq(sim->dat_irq, sim);
+	release_mem_region(sim->res->start,
+			   sim->res->end - sim->res->start + 1);
+out1:
+	clk_put(sim->clk);
+out:
+	kfree(sim);
+	return ret;
+}
+
+static int sim_remove(struct platform_device *pdev)
+{
+	sim_t *sim = platform_get_drvdata(pdev);
+
+	clk_put(sim->clk);
+
+	if (sim->ipb_irq)
+		free_irq(sim->ipb_irq, sim);
+	if (sim->dat_irq)
+		free_irq(sim->dat_irq, sim);
+
+	iounmap(sim->ioaddr);
+
+	kfree(sim);
+	release_mem_region(sim->res->start,
+			   sim->res->end - sim->res->start + 1);
+
+	misc_deregister(&sim_dev);
+	return 0;
+}
+
+static struct platform_driver sim_driver = {
+	.driver = {
+		   .name = "mxc_sim",
+		   },
+	.probe = sim_probe,
+	.remove = sim_remove,
+	.suspend = NULL,
+	.resume = NULL,
+};
+
+static int __init sim_drv_init(void)
+{
+	return platform_driver_register(&sim_driver);
+}
+
+static void __exit sim_drv_exit(void)
+{
+	platform_driver_unregister(&sim_driver);
+}
+
+module_init(sim_drv_init);
+module_exit(sim_drv_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC SIM Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/mxc_iim.c b/drivers/char/mxc_iim.c
new file mode 100644
index 000000000000..b407d34759a9
--- /dev/null
+++ b/drivers/char/mxc_iim.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/clk.h>
+#include <linux/miscdevice.h>
+
+static unsigned long iim_reg_base, iim_reg_end, iim_reg_size;
+static struct clk *iim_clk;
+static struct device *iim_dev;
+
+/*!
+ * MXC IIM interface - memory map function
+ * This function maps 4KB IIM registers from IIM base address.
+ *
+ * @param file	     struct file *
+ * @param vma	     structure vm_area_struct *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
+	if (remap_pfn_range(vma,
+			    vma->vm_start,
+			    iim_reg_base >> PAGE_SHIFT,
+			    iim_reg_size,
+			    vma->vm_page_prot))
+		return -EAGAIN;
+
+	return 0;
+}
+
+/*!
+ * MXC IIM interface - open function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_open(struct inode *inode, struct file *filp)
+{
+	iim_clk = clk_get(NULL, "iim_clk");
+	if (IS_ERR(iim_clk)) {
+		dev_err(iim_dev, "No IIM clock defined\n");
+		return -ENODEV;
+	}
+	clk_enable(iim_clk);
+
+	return 0;
+}
+
+/*!
+ * MXC IIM interface - release function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_release(struct inode *inode, struct file *filp)
+{
+	clk_disable(iim_clk);
+	clk_put(iim_clk);
+	return 0;
+}
+
+static const struct file_operations mxc_iim_fops = {
+	.mmap = mxc_iim_mmap,
+	.open = mxc_iim_open,
+	.release = mxc_iim_release,
+};
+
+static struct miscdevice mxc_iim_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "mxc_iim",
+	.fops = &mxc_iim_fops,
+};
+
+/*!
+ * This function is called by the driver framework to get iim base/end address
+ * and register iim misc device.
+ *
+ * @param	dev	The device structure for IIM passed in by the driver
+ *			framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int mxc_iim_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	iim_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(iim_dev, "Unable to get IIM resource\n");
+		return -ENODEV;
+	}
+
+	iim_reg_base = res->start;
+	iim_reg_end = res->end;
+	iim_reg_size = iim_reg_end - iim_reg_base + 1;
+
+	ret = misc_register(&mxc_iim_miscdev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int mxc_iim_remove(struct platform_device *pdev)
+{
+	misc_deregister(&mxc_iim_miscdev);
+	return 0;
+}
+
+static struct platform_driver mxc_iim_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "mxc_iim",
+		   },
+	.probe = mxc_iim_probe,
+	.remove = mxc_iim_remove,
+};
+
+static int __init mxc_iim_dev_init(void)
+{
+	return platform_driver_register(&mxc_iim_driver);
+}
+
+static void __exit mxc_iim_dev_cleanup(void)
+{
+	platform_driver_unregister(&mxc_iim_driver);
+}
+
+module_init(mxc_iim_dev_init);
+module_exit(mxc_iim_dev_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC IIM driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR);
diff --git a/drivers/char/mxc_si4702.c b/drivers/char/mxc_si4702.c
new file mode 100644
index 000000000000..d9fcce6cb439
--- /dev/null
+++ b/drivers/char/mxc_si4702.c
@@ -0,0 +1,1221 @@
+/*
+ * linux/drivers/char/mxc_si4702.c
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/cdev.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/mxc_si4702.h>
+#include <asm/uaccess.h>
+#include <mach/hardware.h>
+
+#define SI4702_DEV_NAME		"si4702"
+#define DEV_MAJOR		0	/* this could be module param */
+#define DEV_MINOR		0
+#define DEV_BASE_MINOR		0
+#define DEV_MINOR_COUNT		256
+#define SI4702_I2C_ADDR	0x10	/* 7bits I2C address */
+#define DELAY_WAIT	0xffff	/* loop_counter max value */
+/* register define */
+#define SI4702_DEVICEID		0x00
+#define SI4702_CHIPID			0x01
+#define SI4702_POWERCFG		0x02
+#define SI4702_CHANNEL		0x03
+#define SI4702_SYSCONFIG1		0x04
+#define SI4702_SYSCONFIG2		0x05
+#define SI4702_SYSCONFIG3		0x06
+#define SI4702_TEST1			0x07
+#define SI4702_TEST2			0x08
+#define SI4702_B00TCONFIG		0x09
+#define SI4702_STATUSRSSI		0x0A
+#define SI4702_READCHAN		0x0B
+#define SI4702_REG_NUM		0x10
+#define SI4702_REG_BYTE		(SI4702_REG_NUM * 2)
+#define SI4702_DEVICE_ID		0x1242
+#define SI4702_RW_REG_NUM	(SI4702_STATUSRSSI - SI4702_POWERCFG)
+#define SI4702_RW_OFFSET	\
+	(SI4702_REG_NUM - SI4702_STATUSRSSI + SI4702_POWERCFG)
+
+#define SI4702_SPACE_MASK	0x0030
+#define SI4702_SPACE_200K	0x0
+#define SI4702_SPACE_100K	0x10
+#define SI4702_SPACE_50K	0x20
+
+#define SI4702_BAND_MASK	0x00c0
+#define SI4702_BAND_LSB		6
+
+#define SI4702_SEEKTH_MASK	0xff00
+#define SI4702_SEEKTH_LSB	8
+
+#define SI4702_SNR_MASK		0x00f0
+#define SI4702_SNR_LSB		4
+
+#define SI4702_CNT_MASK		0x000f
+#define SI4702_CNT_LSB		0
+
+#define SI4702_VOL_MASK		0x000f
+#define SI4702_VOL_LSB		0
+
+#define SI4702_CHAN_MASK	0x03ff
+#define SI4702_TUNE_BIT		0x8000
+#define SI4702_STC_BIT		0x4000
+#define SI4702_DMUTE_BIT	0x4000
+#define SI4702_SEEKUP_BIT	0x0200
+#define SI4702_SEEK_BIT		0x0100
+#define SI4702_SF_BIT		0x2000
+#define SI4702_ENABLE_BIT	0x0001
+#define SI4702_DISABLE_BIT	0x0040
+
+enum {
+	BAND_USA = 0,
+	BAND_JAP_W,
+	BAND_JAP
+};
+
+struct si4702_info {
+	int min_band;
+	int max_band;
+	int space;
+	int volume;
+	int channel;
+	int mute;
+};
+
+struct si4702_drvdata {
+	struct regulator *vio;
+	struct regulator *vdd;
+	struct class *radio_class;
+	struct si4702_info info;
+	/*by default, dev major is zero, and it's alloc dynamicaly. */
+	int major;
+	int minor;
+	struct cdev *cdev;
+	int count;		/* open count */
+	struct i2c_client *client;
+	unsigned char reg_rw_buf[SI4702_REG_BYTE];
+	struct mxc_fm_platform_data *plat_data;
+};
+
+static struct si4702_drvdata *si4702_drvdata;
+
+DEFINE_SPINLOCK(count_lock);
+
+#ifdef DEBUG
+static void si4702_dump_reg(void)
+{
+	int i, j;
+	unsigned char *reg_rw_buf;
+
+	if (NULL == si4702_drvdata)
+		return;
+
+	reg_rw_buf = si4702_drvdata->reg_rw_buf;
+
+	for (i = 0; i < 10; i++) {
+		j = i * 2 + 12;
+		pr_debug("reg[%02d] = %04x\n", i,
+			 ((reg_rw_buf[j] << 8) & 0xFF00) +
+			 (reg_rw_buf[j + 1] & 0x00FF));
+	}
+	for (; i < 16; i++) {
+		j = (i - 10) * 2;
+		pr_debug("reg[%02d] = %04x\n", i,
+			 ((reg_rw_buf[j] << 8) & 0xFF00) +
+			 (reg_rw_buf[j + 1] & 0x00FF));
+	}
+}
+#else
+static void si4702_dump_reg(void)
+{
+}
+#endif				/* DEBUG */
+
+/*
+ *check the si4702 spec for the read/write concequence.
+ *
+ *0 2       A    F0         A    F
+ *-------------------------------
+ *      buf:0 2      A     F
+ */
+#define REG_to_BUF(reg) (((reg >= 0) && (reg < SI4702_STATUSRSSI))?\
+		(reg - SI4702_STATUSRSSI + SI4702_REG_NUM):\
+		((reg >= SI4702_STATUSRSSI) && (reg < SI4702_REG_NUM))?\
+		(reg - SI4702_STATUSRSSI) : -1)
+
+static int si4702_read_reg(const int reg, u16 *value)
+{
+	int ret, index;
+	unsigned char *reg_rw_buf;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	reg_rw_buf = si4702_drvdata->reg_rw_buf;
+
+	index = REG_to_BUF(reg);
+
+	if (-1 == index)
+		return -1;
+
+	ret =
+	    i2c_master_recv(si4702_drvdata->client, reg_rw_buf,
+			    SI4702_REG_BYTE);
+
+	*value = (reg_rw_buf[index * 2] << 8) & 0xFF00;
+	*value |= reg_rw_buf[index * 2 + 1] & 0x00FF;
+
+	return ret < 0 ? ret : 0;
+}
+
+static int si4702_write_reg(const int reg, const u16 value)
+{
+	int index, ret;
+	unsigned char *reg_rw_buf;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	reg_rw_buf = si4702_drvdata->reg_rw_buf;
+
+	index = REG_to_BUF(reg);
+
+	if (-1 == index)
+		return -1;
+
+	reg_rw_buf[index * 2] = (value & 0xFF00) >> 8;
+	reg_rw_buf[index * 2 + 1] = value & 0x00FF;
+
+	ret = i2c_master_send(si4702_drvdata->client,
+			      &reg_rw_buf[SI4702_RW_OFFSET * 2],
+			      (SI4702_STATUSRSSI - SI4702_POWERCFG) * 2);
+	return ret < 0 ? ret : 0;
+}
+
+static void si4702_gpio_get(void)
+{
+	if (NULL == si4702_drvdata)
+		return;
+
+	si4702_drvdata->plat_data->gpio_get();
+}
+
+static void si4702_gpio_put(void)
+{
+	if (NULL == si4702_drvdata)
+		return;
+
+	si4702_drvdata->plat_data->gpio_put();
+}
+
+static void si4702_reset(void)
+{
+	if (NULL == si4702_drvdata)
+		return;
+
+	si4702_drvdata->plat_data->reset();
+}
+
+static void si4702_clock_en(int flag)
+{
+	if (NULL == si4702_drvdata)
+		return;
+
+	si4702_drvdata->plat_data->clock_ctl(flag);
+}
+
+static int si4702_id_detect(struct i2c_client *client)
+{
+	int ret, index;
+	unsigned int ID = 0;
+	unsigned char reg_rw_buf[SI4702_REG_BYTE];
+
+	si4702_gpio_get();
+	si4702_reset();
+	si4702_clock_en(1);
+
+	ret = i2c_master_recv(client, (char *)reg_rw_buf, SI4702_REG_BYTE);
+
+	si4702_gpio_put();
+
+	if (ret < 0)
+		return ret;
+
+	index = REG_to_BUF(SI4702_DEVICEID);
+	if (index < 0)
+		return index;
+
+	ID = (reg_rw_buf[index * 2] << 8) & 0xFF00;
+	ID |= reg_rw_buf[index * 2 + 1] & 0x00FF;
+
+	return ID;
+}
+
+/* valid args 50/100/200 */
+static int si4702_set_space(int space)
+{
+	u16 reg;
+	int ret;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG2, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg &= ~SI4702_SPACE_MASK;
+	switch (space) {
+	case 50:
+		reg |= SI4702_SPACE_50K;
+		break;
+	case 100:
+		reg |= SI4702_SPACE_100K;
+		break;
+	case 200:
+		ret |= SI4702_SPACE_200K;
+		break;
+	default:
+		return -1;
+	}
+
+	ret = si4702_write_reg(SI4702_SYSCONFIG2, reg);
+	if (ret == -1)
+		return ret;
+
+	info = &si4702_drvdata->info;
+	info->space = space;
+	return 0;
+}
+
+static int si4702_set_band_range(int band)
+{
+	u16 reg;
+	int ret, band_min, band_max;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	switch (band) {
+	case BAND_USA:
+		band_min = 87500;
+		band_max = 108000;
+		break;
+	case BAND_JAP_W:
+		band_min = 76000;
+		band_max = 108000;
+		break;
+	case BAND_JAP:
+		band_min = 76000;
+		band_max = 90000;
+		break;
+	default:
+		return -1;
+	}
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG2, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg = (reg & ~SI4702_BAND_MASK)
+	    | ((band << SI4702_BAND_LSB) & SI4702_BAND_MASK);
+	ret = si4702_write_reg(SI4702_SYSCONFIG2, reg);
+	if (ret == -1)
+		return ret;
+
+	info = &si4702_drvdata->info;
+	info->min_band = band_min;
+	info->max_band = band_max;
+	return 0;
+}
+
+static int si4702_set_seekth(u8 seekth)
+{
+	u16 reg;
+	int ret;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG2, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg =
+	    (reg & ~SI4702_SEEKTH_MASK) | ((seekth << SI4702_SEEKTH_LSB) &
+					   SI4702_SEEKTH_MASK);
+	ret = si4702_write_reg(SI4702_SYSCONFIG2, reg);
+	if (ret == -1)
+		return ret;
+
+	return 0;
+}
+
+static int si4702_set_sksnr(u8 sksnr)
+{
+	u16 reg;
+	int ret;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG3, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg =
+	    (reg & ~SI4702_SNR_MASK) | ((sksnr << SI4702_SNR_LSB) &
+					SI4702_SNR_MASK);
+	ret = si4702_write_reg(SI4702_SYSCONFIG3, reg);
+	if (ret == -1)
+		return ret;
+
+	return 0;
+}
+
+static int si4702_set_skcnt(u8 skcnt)
+{
+	u16 reg;
+	int ret;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG3, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg = (reg & ~SI4702_CNT_MASK) | (skcnt & SI4702_CNT_MASK);
+	ret = si4702_write_reg(SI4702_SYSCONFIG3, reg);
+	if (ret == -1)
+		return ret;
+
+	return 0;
+}
+
+static int si4702_set_vol(int vol)
+{
+	u16 reg;
+	int ret;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	ret = si4702_read_reg(SI4702_SYSCONFIG2, &reg);
+	if (ret == -1)
+		return ret;
+
+	reg = (reg & ~SI4702_VOL_MASK) | (vol & SI4702_VOL_MASK);
+	ret = si4702_write_reg(SI4702_SYSCONFIG2, reg);
+	if (ret == -1)
+		return ret;
+
+	info = &si4702_drvdata->info;
+	info->volume = vol;
+
+	return 0;
+}
+
+static u8 si4702_channel_select(u32 freq)
+{
+	u16 loop_counter = 0;
+	s16 channel;
+	u16 si4702_reg_data;
+	u8 error_ind = 0;
+	struct i2c_client *client;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	info = &si4702_drvdata->info;
+	client = si4702_drvdata->client;
+
+	dev_info(&client->dev, "Input frequnce is %d\n", freq);
+	if (freq < 76000 || freq > 108000) {
+		dev_err(&client->dev, "Input frequnce is invalid\n");
+		return -1;
+	}
+	/* convert freq to channel */
+	channel = (freq - info->min_band) / info->space;
+
+	si4702_reg_data = SI4702_TUNE_BIT | (channel & SI4702_CHAN_MASK);
+	/* set channel */
+	error_ind = si4702_write_reg(SI4702_CHANNEL, si4702_reg_data);
+	if (error_ind) {
+		dev_err(&client->dev, "Failed to set channel\n");
+		return -1;
+	}
+	dev_info(&client->dev, "Set channel to %d\n", channel);
+
+	/* wait for STC == 1 */
+	do {
+		error_ind =
+		    si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data);
+
+		if (error_ind) {
+			dev_err(&client->dev, "Failed to read setted STC\n");
+			return -1;
+		}
+		if ((si4702_reg_data & SI4702_STC_BIT) != 0)
+			break;
+	} while (++loop_counter < DELAY_WAIT);
+
+	/* check loop_counter */
+	if (loop_counter >= DELAY_WAIT) {
+		dev_err(&client->dev, "Can't wait for STC bit set");
+		return -1;
+	}
+	dev_info(&client->dev, "loop counter %d\n", loop_counter);
+
+	loop_counter = 0;
+	/* clear tune bit */
+	error_ind = si4702_write_reg(SI4702_CHANNEL, 0);
+
+	if (error_ind) {
+		dev_err(&client->dev, "Failed to set stop tune\n");
+		return -1;
+	}
+
+	/* wait for STC == 0 */
+	do {
+		error_ind =
+		    si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data);
+
+		if (error_ind) {
+			dev_err(&client->dev, "Failed to set read STC\n");
+			return -1;
+		}
+		if ((si4702_reg_data & SI4702_STC_BIT) == 0)
+			break;
+	} while (++loop_counter < DELAY_WAIT);
+
+	/* check loop_counter */
+	if (loop_counter >= DELAY_WAIT) {
+		dev_err(&client->dev, "Can't wait for STC bit clean");
+		return -1;
+	}
+	dev_info(&client->dev, "loop counter %d\n", loop_counter);
+
+	/* read RSSI */
+	error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data);
+
+	if (error_ind) {
+		dev_err(&client->dev, "Failed to read RSSI\n");
+		return -1;
+	}
+
+	channel = si4702_reg_data & SI4702_CHAN_MASK;
+	dev_info(&client->dev, "seek finish: channel(%d)\n", channel);
+
+	return 0;
+}
+
+static s32 si4702_channel_seek(s16 dir)
+{
+	u16 loop_counter = 0;
+	u16 si4702_reg_data, reg_power_cfg;
+	u8 error_ind = 0;
+	u32 channel, freq;
+	struct i2c_client *client;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	info = &si4702_drvdata->info;
+	client = si4702_drvdata->client;
+
+	error_ind = si4702_read_reg(SI4702_POWERCFG, &reg_power_cfg);
+
+	if (info->mute) {
+		/* check disable mute */
+		reg_power_cfg &= ~SI4702_DMUTE_BIT;
+	} else {
+		reg_power_cfg |= SI4702_DMUTE_BIT;
+	}
+
+	if (dir) {
+		reg_power_cfg |= SI4702_SEEKUP_BIT;
+	} else {
+		reg_power_cfg &= ~SI4702_SEEKUP_BIT;
+	}
+	/* start seek */
+	reg_power_cfg |= SI4702_SEEK_BIT;
+	error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg);
+
+	if (error_ind) {
+		dev_err(&client->dev, "Failed to set seek start bit\n");
+		return -1;
+	}
+
+	/* wait STC == 1 */
+	do {
+		error_ind =
+		    si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data);
+		if (error_ind) {
+			dev_err(&client->dev, "Failed to read STC bit\n");
+			return -1;
+		}
+
+		if ((si4702_reg_data & SI4702_STC_BIT) != 0)
+			break;
+	} while (++loop_counter < DELAY_WAIT);
+
+	/* clear seek bit */
+	reg_power_cfg &= ~SI4702_SEEK_BIT;
+	error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg);
+	if (error_ind) {
+		dev_err(&client->dev, "Failed to stop seek\n");
+		return -1;
+	}
+
+	if (loop_counter >= DELAY_WAIT) {
+		dev_err(&client->dev, "Can't wait for STC bit set\n");
+		return -1;
+	}
+
+	/* check whether SF==1 (seek failed bit) */
+	if ((si4702_reg_data & SI4702_SF_BIT) != 0) {
+		dev_err(&client->dev, "Failed to seek any channel\n");
+		return -1;
+	}
+
+	loop_counter = 0;
+	/* wait STC == 0 */
+	do {
+		error_ind =
+		    si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data);
+
+		if (error_ind) {
+			dev_err(&client->dev,
+				"Failed to wait STC bit to clear\n");
+			return -1;
+		}
+		if ((si4702_reg_data & SI4702_STC_BIT) == 0)
+			break;
+	} while (++loop_counter < DELAY_WAIT);
+
+	/* check loop_counter */
+	if (loop_counter >= DELAY_WAIT) {
+		dev_err(&client->dev, "Can't wait for STC bit clean");
+		return -1;
+	}
+
+	error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data);
+
+	if (error_ind) {
+		dev_err(&client->dev, "I2C simulate failed\n");
+		return -1;
+	}
+
+	channel = si4702_reg_data & SI4702_CHAN_MASK;
+	freq = channel * info->space + info->min_band;
+	dev_err(&client->dev,
+		"seek finish: channel(%d), freq(%dKHz)\n", channel, freq);
+
+	return 0;
+}
+
+static int si4702_startup(void)
+{
+	u16 magic = 0, id;
+	struct i2c_client *client;
+	struct mxc_fm_platform_data *data;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	if (si4702_drvdata->vio)
+		regulator_enable(si4702_drvdata->vio);
+	if (si4702_drvdata->vdd)
+		regulator_enable(si4702_drvdata->vdd);
+	data = si4702_drvdata->plat_data;
+	client = si4702_drvdata->client;
+
+	/* read prior to write, otherwise write op will fail */
+	si4702_read_reg(SI4702_DEVICEID, &id);
+	dev_err(&client->dev, "si4702: DEVICEID: 0x%x\n", id);
+
+	si4702_clock_en(1);
+	msleep(100);
+
+	/* disable mute, stereo, seek down, powerup */
+	si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT | SI4702_ENABLE_BIT);
+	msleep(500);
+	si4702_read_reg(SI4702_TEST1, &magic);
+	if (magic != 0x3C04)
+		dev_err(&client->dev, "magic number 0x%x.\n", magic);
+	/* close tune, set channel to 0 */
+	si4702_write_reg(SI4702_CHANNEL, 0);
+	/* disable interrupt, disable GPIO */
+	si4702_write_reg(SI4702_SYSCONFIG1, 0);
+	/* set volume to middle level */
+	si4702_set_vol(0xf);
+
+	si4702_set_space(data->space);
+	si4702_set_band_range(data->band);
+	si4702_set_seekth(data->seekth);
+	si4702_set_skcnt(data->skcnt);
+	si4702_set_sksnr(data->sksnr);
+
+	return 0;
+}
+
+static void si4702_shutdown(void)
+{
+	if (NULL == si4702_drvdata)
+		return;
+
+	si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT |
+			 SI4702_ENABLE_BIT | SI4702_DISABLE_BIT);
+	msleep(100);
+	si4702_clock_en(0);
+
+	if (si4702_drvdata->vdd)
+		regulator_disable(si4702_drvdata->vdd);
+	if (si4702_drvdata->vio)
+		regulator_disable(si4702_drvdata->vio);
+}
+
+enum {
+	FM_STARTUP = 0,
+	FM_SHUTDOWN,
+	FM_RESET,
+	FM_VOLUP,
+	FM_VOLDOWN,
+	FM_SEEK_UP,
+	FM_SEEK_DOWN,
+	FM_MUTEON,
+	FM_MUTEDIS,
+	FM_SEL,
+	FM_SEEKTH,
+	FM_DL,
+	FM_CTL_MAX
+};
+
+static const char *const fm_control[FM_CTL_MAX] = {
+	[FM_STARTUP] = "start",
+	[FM_SHUTDOWN] = "halt",
+	[FM_RESET] = "reset",
+	[FM_VOLUP] = "volup",
+	[FM_VOLDOWN] = "voldown",
+	[FM_SEEK_UP] = "seeku",
+	[FM_SEEK_DOWN] = "seekd",
+	[FM_MUTEON] = "mute",
+	[FM_MUTEDIS] = "muted",
+	[FM_SEL] = "select",
+	[FM_SEEKTH] = "seekth",
+	[FM_DL] = "delay"
+};
+
+static int cmd(unsigned int index, int arg)
+{
+	struct i2c_client *client;
+	struct mxc_fm_platform_data *plat_data;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	client = si4702_drvdata->client;
+	plat_data = si4702_drvdata->plat_data;
+
+	switch (index) {
+	case FM_SHUTDOWN:
+		dev_err(&client->dev, "FM_SHUTDOWN\n");
+		si4702_shutdown();
+		break;
+	case FM_STARTUP:
+		dev_err(&client->dev, "FM_STARTUP\n");
+		si4702_reset();
+		si4702_startup();
+		break;
+	case FM_RESET:
+		dev_err(&client->dev, "FM_RESET\n");
+		si4702_reset();
+		break;
+	case FM_SEEK_DOWN:
+		dev_err(&client->dev, "SEEK DOWN\n");
+		si4702_channel_seek(0);
+		break;
+	case FM_SEEK_UP:
+		dev_err(&client->dev, "SEEK UP\n");
+		si4702_channel_seek(1);
+		break;
+	case FM_SEL:
+		dev_err(&client->dev, "select %d\n", arg * 100);
+		si4702_channel_select(arg * 100);
+		break;
+	case FM_SEEKTH:
+		dev_err(&client->dev, "seekth = %d\n", arg);
+		si4702_set_seekth(arg);
+		break;
+	case FM_DL:
+		dev_err(&client->dev, "delay = %d\n", arg);
+		break;
+	default:
+		dev_err(&client->dev, "error command\n");
+		break;
+	}
+	return 0;
+}
+
+static ssize_t si4702_show(struct device *dev,
+			   struct device_attribute *attr, char *buf)
+{
+	struct si4702_drvdata *drv_data = dev_get_drvdata(dev);
+	u16 device_id;
+
+	dev_err(&(drv_data->client->dev), "si4702 show\n");
+	si4702_read_reg(SI4702_DEVICEID, &device_id);
+	pr_info("device id %x\n", device_id);
+	si4702_dump_reg();
+	return 0;
+}
+
+static ssize_t si4702_store(struct device *dev,
+			    struct device_attribute *attr, const char *buf,
+			    size_t count)
+{
+	int state = 0;
+	const char *const *s;
+	char *p = NULL;
+	int error;
+	int len, arg = 0;
+	struct si4702_drvdata *drv_data = dev_get_drvdata(dev);
+	struct i2c_client *client = drv_data->client;
+
+	dev_err(&client->dev, "si4702 store %d\n", count);
+
+	p = memchr(buf, ' ', count);
+	if (p) {
+		len = p - buf;
+		*p = '\0';
+	} else
+		len = count;
+
+	len -= 1;
+	dev_err(&client->dev, "cmd %s\n", buf);
+
+	for (s = &fm_control[state]; state < FM_CTL_MAX; s++, state++) {
+		if (*s && !strncmp(buf, *s, len)) {
+			break;
+		}
+	}
+	if (state < FM_CTL_MAX && *s) {
+		if (p)
+			arg = simple_strtoul(p + 1, NULL, 0);
+		dev_err(&client->dev, "arg = %d\n", arg);
+		error = cmd(state, arg);
+	} else {
+		dev_err(&client->dev, "error cmd\n");
+		error = -EINVAL;
+	}
+
+	return error ? error : count;
+}
+
+static int ioctl_si4702(struct inode *inode, struct file *file,
+			unsigned int cmd, unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	int mute = 0;
+	u16 data;
+	int error;
+	u8 volume;
+	unsigned int freq;
+	int dir;
+	struct i2c_client *client;
+	struct si4702_info *info;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	info = &si4702_drvdata->info;
+	client = si4702_drvdata->client;
+
+	dev_err(&client->dev, "ioctl, cmd: 0x%x, arg: 0x%lx\n", cmd, arg);
+
+	switch (cmd) {
+	case SI4702_SETVOLUME:
+		/* get volume from user */
+		if (copy_from_user(&volume, argp, sizeof(u8))) {
+
+			dev_err(&client->dev,
+				"ioctl, copy volume value from user failed\n");
+			return -EFAULT;
+		}
+		dev_err(&client->dev, "volume %d\n", volume);
+		/* refill the register value */
+		volume &= 0x0f;
+		if (info->mute)
+			error = si4702_write_reg(SI4702_POWERCFG, 0x0001);
+		else
+			error = si4702_write_reg(SI4702_POWERCFG, 0x4001);
+
+		error = si4702_write_reg(SI4702_CHANNEL, 0);
+		error = si4702_write_reg(SI4702_SYSCONFIG1, 0);
+		error = si4702_write_reg(SI4702_SYSCONFIG2, 0x0f10 | volume);
+		if (error) {
+			dev_err(&client->dev, "ioctl, set volume failed\n");
+			return -EFAULT;
+		}
+		/* renew the device info */
+		info->volume = volume;
+
+		break;
+	case SI4702_GETVOLUME:
+		/* just copy volume value to user */
+		if (copy_to_user(argp, &(info->volume), sizeof(unsigned int))) {
+			dev_err(&client->dev, "ioctl, copy to user failed\n");
+			return -EFAULT;
+		}
+		break;
+	case SI4702_MUTEON:
+		mute = 1;
+	case SI4702_MUTEOFF:
+		if (mute) {
+			/* enable mute */
+			si4702_read_reg(SI4702_POWERCFG, &data);
+			data &= 0x00FF;
+			error = si4702_write_reg(SI4702_POWERCFG, data);
+		} else {
+			si4702_read_reg(SI4702_POWERCFG, &data);
+			data &= 0x00FF;
+			data |= 0x4000;
+			error = si4702_write_reg(SI4702_POWERCFG, data);
+		}
+		if (error) {
+			dev_err(&client->dev, "ioctl, set mute failed\n");
+			return -EFAULT;
+		}
+		break;
+	case SI4702_SELECT:
+		if (copy_from_user(&freq, argp, sizeof(unsigned int))) {
+
+			dev_err(&client->dev,
+				"ioctl, copy frequence from user failed\n");
+			return -EFAULT;
+		}
+		/* check frequence */
+		if (freq > info->max_band || freq < info->min_band) {
+			dev_err(&client->dev,
+				"the frequence select is out of band\n");
+			return -EINVAL;
+		}
+		if (si4702_channel_select(freq)) {
+			dev_err(&client->dev,
+				"ioctl, failed to select channel\n");
+			return -EFAULT;
+		}
+		break;
+	case SI4702_SEEK:
+		if (copy_from_user(&dir, argp, sizeof(int))) {
+
+			dev_err(&client->dev, "ioctl, copy from user failed\n");
+			return -EFAULT;
+		}
+		/* get seeked channel */
+		dir = si4702_channel_seek(dir);
+		if (dir == -1) {
+			return -EAGAIN;
+		} else if (dir == -2) {
+			return -EFAULT;
+		}
+		if (copy_to_user(argp, &dir, sizeof(int))) {
+
+			dev_err(&client->dev,
+				"ioctl, copy seek frequnce to user failed\n");
+			return -EFAULT;
+		}
+		break;
+	default:
+		dev_err(&client->dev, "SI4702: Invalid ioctl command\n");
+		return -EINVAL;
+
+	}
+	return 0;
+}
+
+static int open_si4702(struct inode *inode, struct file *file)
+{
+	struct i2c_client *client;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	client = si4702_drvdata->client;
+
+	spin_lock(&count_lock);
+	if (si4702_drvdata->count != 0) {
+		dev_err(&client->dev, "device has been open already\n");
+		spin_unlock(&count_lock);
+		return -EBUSY;
+	}
+	si4702_drvdata->count++;
+	spin_unlock(&count_lock);
+
+	/* request and active GPIO */
+	si4702_gpio_get();
+	/* reset the si4702 from it's reset pin */
+	si4702_reset();
+
+	/* startup si4702 */
+	if (si4702_startup()) {
+		spin_lock(&count_lock);
+		si4702_drvdata->count--;
+		spin_unlock(&count_lock);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int release_si4702(struct inode *inode, struct file *file)
+{
+	struct i2c_client *client;
+
+	if (NULL == si4702_drvdata)
+		return -1;
+
+	client = si4702_drvdata->client;
+
+	dev_err(&client->dev, "release\n");
+	/* software shutdown */
+	si4702_shutdown();
+	/* inactive, free GPIO, cut power */
+	si4702_gpio_put();
+
+	spin_lock(&count_lock);
+	si4702_drvdata->count--;
+	spin_unlock(&count_lock);
+
+	return 0;
+}
+
+static int si4702_suspend(struct i2c_client *client, pm_message_t state)
+{
+	return 0;
+}
+
+static int si4702_resume(struct i2c_client *client)
+{
+	return 0;
+}
+
+static struct device_attribute si4702_dev_attr = {
+	.attr = {
+		 .name = "si4702_ctl",
+		 .mode = S_IRUSR | S_IWUSR,
+		 },
+	.show = si4702_show,
+	.store = si4702_store,
+};
+
+static struct file_operations si4702_fops = {
+	.owner = THIS_MODULE,
+	.open = open_si4702,
+	.release = release_si4702,
+	.ioctl = ioctl_si4702,
+};
+
+static int __devinit si4702_probe(struct i2c_client *client,
+				  const struct i2c_device_id *id)
+{
+	int ret = 0;
+	struct mxc_fm_platform_data *plat_data;
+	struct si4702_drvdata *drv_data;
+	struct device *dev;
+
+	dev_info(&client->dev, "si4702 device probe process start.\n");
+
+	plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data;
+	if (plat_data == NULL) {
+		dev_err(&client->dev, "lack of platform data!\n");
+		return -ENODEV;
+	}
+
+	drv_data = kmalloc(sizeof(struct si4702_drvdata), GFP_KERNEL);
+	if (drv_data == NULL) {
+		dev_err(&client->dev, "lack of kernel memory!\n");
+		return -ENOMEM;
+	}
+	memset(drv_data, 0, sizeof(struct si4702_drvdata));
+	drv_data->plat_data = plat_data;
+	drv_data->major = DEV_MAJOR;
+	drv_data->minor = DEV_MINOR;
+	drv_data->count = 0;
+
+	/*enable power supply */
+	if (plat_data->reg_vio != NULL) {
+		drv_data->vio = regulator_get(&client->dev, plat_data->reg_vio);
+		if (drv_data->vio == ERR_PTR(-ENOENT))
+			goto free_drv_data;
+		regulator_enable(drv_data->vio);
+	}
+
+	/* here, we assume that vio and vdd are not the same */
+	if (plat_data->reg_vdd != NULL) {
+		drv_data->vdd = regulator_get(&client->dev, plat_data->reg_vdd);
+		if (drv_data->vdd == ERR_PTR(-ENOENT))
+			goto disable_vio;
+		regulator_enable(drv_data->vdd);
+	}
+
+	/*attach client and check device id */
+	if (SI4702_DEVICE_ID != si4702_id_detect(client)) {
+		dev_err(&client->dev, "id wrong.\n");
+		goto disable_vdd;
+	}
+	dev_info(&client->dev, "chip id %x detect.\n", SI4702_DEVICE_ID);
+	drv_data->client = client;
+
+	/*user interface begain */
+	/*create device file in sysfs as a user interface,
+	 * also for debug support */
+	ret = device_create_file(&client->dev, &si4702_dev_attr);
+	if (ret) {
+		dev_err(&client->dev, "create device file failed!\n");
+		goto gpio_put;	/* shall i use some meanful error code? */
+	}
+
+	/*create a char dev for application code access */
+	if (drv_data->major) {
+		ret = register_chrdev(drv_data->major, "si4702", &si4702_fops);;
+	} else {
+		ret = register_chrdev(0, "si4702", &si4702_fops);
+	}
+
+	if (drv_data->major == 0)
+		drv_data->major = ret;
+
+	/* create class and device for udev information */
+	drv_data->radio_class = class_create(THIS_MODULE, "radio");
+	if (IS_ERR(drv_data->radio_class)) {
+		dev_err(&client->dev, "SI4702: failed to create radio class\n");
+		goto char_dev_remove;
+	}
+
+	dev = device_create(drv_data->radio_class, NULL,
+		    MKDEV(drv_data->major, drv_data->minor), NULL, "si4702");
+	if (IS_ERR(dev)) {
+		dev_err(&client->dev,
+			"SI4702: failed to create radio class device\n");
+		goto class_remove;
+	}
+	/*User interface end */
+	dev_set_drvdata(&client->dev, drv_data);
+	si4702_drvdata = drv_data;
+
+	si4702_gpio_get();
+	dev_info(&client->dev, "si4702 device probe successfully.\n");
+	si4702_shutdown();
+
+	return 0;
+
+class_remove:
+	class_destroy(drv_data->radio_class);
+char_dev_remove:
+	unregister_chrdev(drv_data->major, "si4702");
+	device_remove_file(&client->dev, &si4702_dev_attr);
+gpio_put:
+	si4702_gpio_put();
+disable_vdd:
+	if (plat_data->reg_vdd) {
+		regulator_disable(drv_data->vdd);
+		regulator_put(drv_data->vdd);
+	}
+disable_vio:
+	if (plat_data->reg_vio) {
+		regulator_disable(drv_data->vio);
+		regulator_put(drv_data->vio);
+	}
+
+free_drv_data:
+	kfree(drv_data);
+
+	return -ENODEV;
+}
+
+static int __devexit si4702_remove(struct i2c_client *client)
+{
+	struct mxc_fm_platform_data *plat_data;
+	struct si4702_drvdata *drv_data = dev_get_drvdata(&client->dev);
+
+	plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data;
+
+	device_destroy(drv_data->radio_class,
+		       MKDEV(drv_data->major, drv_data->minor));
+	class_destroy(drv_data->radio_class);
+
+	unregister_chrdev(drv_data->major, "si4702");
+	device_remove_file(&client->dev, &si4702_dev_attr);
+	si4702_gpio_put();
+
+	if (plat_data->reg_vdd)
+		regulator_put(drv_data->vdd);
+
+	if (plat_data->reg_vio)
+		regulator_put(drv_data->vio);
+
+	kfree(si4702_drvdata);
+	si4702_drvdata = NULL;
+
+	return 0;
+}
+
+static const struct i2c_device_id si4702_id[] = {
+	{"si4702", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, si4702_id);
+
+static struct i2c_driver i2c_si4702_driver = {
+	.driver = {
+		   .name = "si4702",
+		   },
+	.probe = si4702_probe,
+	.remove = si4702_remove,
+	.suspend = si4702_suspend,
+	.resume = si4702_resume,
+	.id_table = si4702_id,
+};
+
+static int __init init_si4702(void)
+{
+	/*add to i2c driver */
+	pr_info("add si4702 i2c driver\n");
+	return i2c_add_driver(&i2c_si4702_driver);
+}
+
+static void __exit exit_si4702(void)
+{
+	i2c_del_driver(&i2c_si4702_driver);
+}
+
+module_init(init_si4702);
+module_exit(exit_si4702);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("SI4702 FM driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/mxs_viim.c b/drivers/char/mxs_viim.c
new file mode 100644
index 000000000000..2510afa6c13e
--- /dev/null
+++ b/drivers/char/mxs_viim.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/miscdevice.h>
+
+static unsigned long iim_reg_base0, iim_reg_end0, iim_reg_size0;
+static unsigned long iim_reg_base1, iim_reg_end1, iim_reg_size1;
+static struct device *iim_dev;
+
+/*!
+ * MXS Virtual IIM interface - memory map function
+ * This function maps one page size VIIM registers from VIIM base address0
+ * if the size of the required virtual memory space is less than or equal to
+ * one page size, otherwise this function will also map one page size VIIM
+ * registers from VIIM base address1.
+ *
+ * @param file	     struct file *
+ * @param vma	     structure vm_area_struct *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxs_viim_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	size_t size = vma->vm_end - vma->vm_start;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
+	if (remap_pfn_range(vma,
+			    vma->vm_start,
+			    iim_reg_base0 >> PAGE_SHIFT,
+			    iim_reg_size0,
+			    vma->vm_page_prot))
+		return -EAGAIN;
+
+	if (size > iim_reg_size0) {
+		if (remap_pfn_range(vma,
+				    vma->vm_start + iim_reg_size0,
+				    iim_reg_base1 >> PAGE_SHIFT,
+				    iim_reg_size1,
+				    vma->vm_page_prot))
+			return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*!
+ * MXS Virtual IIM interface - open function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxs_viim_open(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+/*!
+ * MXS Virtual IIM interface - release function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxs_viim_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static const struct file_operations mxs_viim_fops = {
+	.mmap = mxs_viim_mmap,
+	.open = mxs_viim_open,
+	.release = mxs_viim_release,
+};
+
+static struct miscdevice mxs_viim_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "mxs_viim",
+	.fops = &mxs_viim_fops,
+};
+
+/*!
+ * This function is called by the driver framework to get virtual iim base/end
+ * address and register iim misc device.
+ *
+ * @param	dev	The device structure for Virtual IIM passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int mxs_viim_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	iim_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(iim_dev, "Unable to get Virtual IIM resource 0\n");
+		return -ENODEV;
+	}
+
+	iim_reg_base0 = res->start;
+	iim_reg_end0 = res->end;
+	iim_reg_size0 = iim_reg_end0 - iim_reg_base0 + 1;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (IS_ERR(res)) {
+		dev_err(iim_dev, "Unable to get Virtual IIM resource 1\n");
+		return -ENODEV;
+	}
+
+	iim_reg_base1 = res->start;
+	iim_reg_end1 = res->end;
+	iim_reg_size1 = iim_reg_end1 - iim_reg_base1 + 1;
+
+	ret = misc_register(&mxs_viim_miscdev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int mxs_viim_remove(struct platform_device *pdev)
+{
+	misc_deregister(&mxs_viim_miscdev);
+	return 0;
+}
+
+static struct platform_driver mxs_viim_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "mxs_viim",
+		   },
+	.probe = mxs_viim_probe,
+	.remove = mxs_viim_remove,
+};
+
+static int __init mxs_viim_dev_init(void)
+{
+	return platform_driver_register(&mxs_viim_driver);
+}
+
+static void __exit mxs_viim_dev_cleanup(void)
+{
+	platform_driver_unregister(&mxs_viim_driver);
+}
+
+module_init(mxs_viim_dev_init);
+module_exit(mxs_viim_dev_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXS Virtual IIM driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR);
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b27692372bf..9c2919a431a8 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -209,4 +209,16 @@ config CRYPTO_DEV_PPC4XX
 	help
 	  This option allows you to have support for AMCC crypto acceleration.
 
+config CRYPTO_DEV_DCP
+	tristate "Support for the DCP engine"
+	depends on ARCH_MX28 || ARCH_MX23
+	select CRYPTO_ALGAPI
+	select CRYPTO_BLKCIPHER
+	help
+	  Say 'Y' here to use the DCP AES and SHA
+	  engine for the CryptoAPI algorithms.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called geode-aes.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 9bf4a2bc8846..161dd2d7433e 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
 obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
+obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o
diff --git a/drivers/crypto/dcp.c b/drivers/crypto/dcp.c
new file mode 100644
index 000000000000..8b54b127d6d0
--- /dev/null
+++ b/drivers/crypto/dcp.c
@@ -0,0 +1,1696 @@
+/*
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Based on geode-aes.c
+ * Copyright (C) 2004-2006, Advanced Micro Devices, Inc.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysdev.h>
+#include <linux/bitops.h>
+#include <linux/crypto.h>
+#include <linux/spinlock.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/sysfs.h>
+#include <linux/fs.h>
+#include <crypto/algapi.h>
+#include <crypto/aes.h>
+#include <crypto/sha.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include "dcp.h"
+#include "dcp_bootstream_ioctl.h"
+
+/* Following data only used by DCP bootstream interface */
+struct dcpboot_dma_area {
+	struct dcp_hw_packet hw_packet;
+	uint16_t block[16];
+};
+
+struct dcp {
+	struct device *dev;
+	spinlock_t lock;
+	struct mutex op_mutex[DCP_NUM_CHANNELS];
+	struct completion op_wait[DCP_NUM_CHANNELS];
+	int wait[DCP_NUM_CHANNELS];
+	int dcp_vmi_irq;
+	int dcp_irq;
+	u32 dcp_regs_base;
+
+	/* Following buffers used in hashing to meet 64-byte len alignment */
+	char *buf1;
+	char *buf2;
+	dma_addr_t buf1_phys;
+	dma_addr_t buf2_phys;
+	struct dcp_hash_coherent_block *buf1_desc;
+	struct dcp_hash_coherent_block *buf2_desc;
+	struct dcp_hash_coherent_block *user_buf_desc;
+
+	/* Following data only used by DCP bootstream interface */
+	struct dcpboot_dma_area *dcpboot_dma_area;
+	dma_addr_t dcpboot_dma_area_phys;
+};
+
+/* cipher flags */
+#define DCP_ENC	0x0001
+#define DCP_DEC	0x0002
+#define DCP_ECB	0x0004
+#define DCP_CBC	0x0008
+#define DCP_CBC_INIT	0x0010
+#define DCP_OTPKEY	0x0020
+
+/* hash flags */
+#define DCP_INIT	0x0001
+#define DCP_UPDATE	0x0002
+#define DCP_FINAL	0x0004
+
+#define DCP_AES	0x1000
+#define DCP_SHA1	0x2000
+#define DCP_CRC32	0x3000
+#define DCP_COPY	0x4000
+#define DCP_FILL	0x5000
+#define DCP_MODE_MASK	0xf000
+
+struct dcp_op {
+
+	unsigned int flags;
+
+	void *src;
+	dma_addr_t src_phys;
+
+	void *dst;
+	dma_addr_t dst_phys;
+
+	int len;
+
+	/* the key contains the IV for block modes */
+	union {
+		struct {
+			u8 key[2 * AES_KEYSIZE_128]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t key_phys;
+			int keylen;
+		} cipher;
+		struct {
+			u8 digest[SHA256_DIGEST_SIZE]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t digest_phys;
+			int digestlen;
+			int init;
+		} hash;
+	};
+
+	union {
+		struct crypto_blkcipher *blk;
+		struct crypto_cipher *cip;
+		struct crypto_hash *hash;
+	} fallback;
+
+	struct dcp_hw_packet pkt
+		__attribute__ ((__aligned__(32)));
+};
+
+struct dcp_hash_coherent_block {
+	struct dcp_hw_packet pkt[1]
+		__attribute__ ((__aligned__(32)));
+	u8 digest[SHA256_DIGEST_SIZE]
+		__attribute__ ((__aligned__(32)));
+	unsigned int len;
+	dma_addr_t src_phys;
+	void *src;
+	void *dst;
+	dma_addr_t my_phys;
+	u32 hash_sel;
+	struct dcp_hash_coherent_block *next;
+};
+
+struct dcp_hash_op {
+
+	unsigned int flags;
+
+	/* the key contains the IV for block modes */
+	union {
+		struct {
+			u8 key[2 * AES_KEYSIZE_128]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t key_phys;
+			int keylen;
+		} cipher;
+		struct {
+			u8 digest[SHA256_DIGEST_SIZE]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t digest_phys;
+			int digestlen;
+			int init;
+		} hash;
+	};
+
+	u32 length;
+	struct dcp_hash_coherent_block *head_desc;
+	struct dcp_hash_coherent_block *tail_desc;
+};
+
+/* only one */
+static struct dcp *global_sdcp;
+
+static void dcp_perform_op(struct dcp_op *op)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct mutex *mutex;
+	struct dcp_hw_packet *pkt;
+	int chan;
+	u32 pkt1, pkt2;
+	unsigned long timeout;
+	dma_addr_t pkt_phys;
+	u32 stat;
+
+	pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE | BM_DCP_PACKET1_INTERRUPT;
+
+	switch (op->flags & DCP_MODE_MASK) {
+
+	case DCP_AES:
+
+		chan = CIPHER_CHAN;
+
+		/* key is at the payload */
+		pkt1 |= BM_DCP_PACKET1_ENABLE_CIPHER;
+		if ((op->flags & DCP_OTPKEY) == 0)
+			pkt1 |= BM_DCP_PACKET1_PAYLOAD_KEY;
+		if (op->flags & DCP_ENC)
+			pkt1 |= BM_DCP_PACKET1_CIPHER_ENCRYPT;
+		if (op->flags & DCP_CBC_INIT)
+			pkt1 |= BM_DCP_PACKET1_CIPHER_INIT;
+
+		pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) |
+		       BF(0, DCP_PACKET2_KEY_SELECT) |
+		       BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128,
+		       DCP_PACKET2_CIPHER_SELECT);
+
+		if (op->flags & DCP_ECB)
+			pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__ECB,
+				DCP_PACKET2_CIPHER_MODE);
+		else if (op->flags & DCP_CBC)
+			pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__CBC,
+				DCP_PACKET2_CIPHER_MODE);
+
+		break;
+
+	case DCP_SHA1:
+
+		chan = HASH_CHAN;
+
+		pkt1 |= BM_DCP_PACKET1_ENABLE_HASH;
+		if (op->flags & DCP_INIT)
+			pkt1 |= BM_DCP_PACKET1_HASH_INIT;
+		if (op->flags & DCP_FINAL) {
+			pkt1 |= BM_DCP_PACKET1_HASH_TERM;
+			BUG_ON(op->hash.digest == NULL);
+		}
+
+		pkt2 = BF(BV_DCP_PACKET2_HASH_SELECT__SHA1,
+			DCP_PACKET2_HASH_SELECT);
+		break;
+
+	default:
+		dev_err(sdcp->dev, "Unsupported mode\n");
+		return;
+	}
+
+	mutex = &sdcp->op_mutex[chan];
+	pkt = &op->pkt;
+
+	pkt->pNext = 0;
+	pkt->pkt1 = pkt1;
+	pkt->pkt2 = pkt2;
+	pkt->pSrc = (u32)op->src_phys;
+	pkt->pDst = (u32)op->dst_phys;
+	pkt->size = op->len;
+	pkt->pPayload = chan == CIPHER_CHAN ?
+		(u32)op->cipher.key_phys : (u32)op->hash.digest_phys;
+	pkt->stat = 0;
+
+	pkt_phys = dma_map_single(sdcp->dev, pkt, sizeof(*pkt),
+			DMA_BIDIRECTIONAL);
+	if (dma_mapping_error(sdcp->dev, pkt_phys)) {
+		dev_err(sdcp->dev, "Unable to map packet descriptor\n");
+		return;
+	}
+
+	/* submit the work */
+	mutex_lock(mutex);
+
+	__raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(chan));
+
+	/* Load the work packet pointer and bump the channel semaphore */
+	__raw_writel((u32)pkt_phys, sdcp->dcp_regs_base +
+		HW_DCP_CHnCMDPTR(chan));
+
+	/* XXX wake from interrupt instead of looping */
+	timeout = jiffies + msecs_to_jiffies(1000);
+
+	sdcp->wait[chan] = 0;
+	__raw_writel(BF(1, DCP_CHnSEMA_INCREMENT), sdcp->dcp_regs_base
+		+ HW_DCP_CHnSEMA(chan));
+	while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0)
+		cpu_relax();
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev, "Timeout while waiting STAT 0x%08x\n",
+				__raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT));
+		goto out;
+	}
+
+	stat = __raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(chan));
+	if ((stat & 0xff) != 0)
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+				__raw_readl(sdcp->dcp_regs_base +
+				HW_DCP_CHnSTAT(chan)) & 0xff);
+out:
+	mutex_unlock(mutex);
+
+	dma_unmap_single(sdcp->dev, pkt_phys, sizeof(*pkt), DMA_TO_DEVICE);
+}
+
+static int dcp_aes_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
+		unsigned int len)
+{
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+	unsigned int ret;
+
+	op->cipher.keylen = len;
+
+	if (len == AES_KEYSIZE_128) {
+		memcpy(op->cipher.key, key, len);
+		return 0;
+	}
+
+	if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
+		/* not supported at all */
+		tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+		return -EINVAL;
+	}
+
+	/*
+	 * The requested key size is not supported by HW, do a fallback
+	 */
+	op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+	op->fallback.blk->base.crt_flags |= (tfm->crt_flags &
+						CRYPTO_TFM_REQ_MASK);
+
+	ret = crypto_cipher_setkey(op->fallback.cip, key, len);
+	if (ret) {
+		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+		tfm->crt_flags |= (op->fallback.blk->base.crt_flags &
+					CRYPTO_TFM_RES_MASK);
+	}
+	return ret;
+}
+
+static void dcp_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) {
+		crypto_cipher_encrypt_one(op->fallback.cip, out, in);
+		return;
+	}
+
+	op->src = (void *) in;
+	op->dst = (void *) out;
+	op->flags = DCP_AES | DCP_ENC | DCP_ECB;
+	op->len = AES_KEYSIZE_128;
+
+	/* map the data */
+	op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128,
+					DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+		dev_err(sdcp->dev, "Unable to map source\n");
+		return;
+	}
+
+	op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128,
+					DMA_FROM_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+		dev_err(sdcp->dev, "Unable to map dest\n");
+		goto err_unmap_src;
+	}
+
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		goto err_unmap_dst;
+	}
+
+	/* perform the operation */
+	dcp_perform_op(op);
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+err_unmap_dst:
+	dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE);
+err_unmap_src:
+	dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE);
+}
+
+static void dcp_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) {
+		crypto_cipher_decrypt_one(op->fallback.cip, out, in);
+		return;
+	}
+
+	op->src = (void *) in;
+	op->dst = (void *) out;
+	op->flags = DCP_AES | DCP_DEC | DCP_ECB;
+	op->len = AES_KEYSIZE_128;
+
+	/* map the data */
+	op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128,
+					DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+		dev_err(sdcp->dev, "Unable to map source\n");
+		return;
+	}
+
+	op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128,
+					DMA_FROM_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+		dev_err(sdcp->dev, "Unable to map dest\n");
+		goto err_unmap_src;
+	}
+
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		goto err_unmap_dst;
+	}
+
+	/* perform the operation */
+	dcp_perform_op(op);
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+err_unmap_dst:
+	dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE);
+err_unmap_src:
+	dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE);
+}
+
+static int fallback_init_cip(struct crypto_tfm *tfm)
+{
+	const char *name = tfm->__crt_alg->cra_name;
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	op->fallback.cip = crypto_alloc_cipher(name, 0,
+				CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
+
+	if (IS_ERR(op->fallback.cip)) {
+		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+		return PTR_ERR(op->fallback.cip);
+	}
+
+	return 0;
+}
+
+static void fallback_exit_cip(struct crypto_tfm *tfm)
+{
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	crypto_free_cipher(op->fallback.cip);
+	op->fallback.cip = NULL;
+}
+
+static struct crypto_alg dcp_aes_alg = {
+	.cra_name		= "aes",
+	.cra_driver_name	= "dcp-aes",
+	.cra_priority		= 300,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_CIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_cip,
+	.cra_exit		= fallback_exit_cip,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct dcp_op),
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_alg.cra_list),
+	.cra_u			= {
+		.cipher	= {
+			.cia_min_keysize	= AES_MIN_KEY_SIZE,
+			.cia_max_keysize	= AES_MAX_KEY_SIZE,
+			.cia_setkey		= dcp_aes_setkey_cip,
+			.cia_encrypt		= dcp_aes_encrypt,
+			.cia_decrypt		= dcp_aes_decrypt
+		}
+	}
+};
+
+static int dcp_aes_setkey_blk(struct crypto_tfm *tfm, const u8 *key,
+		unsigned int len)
+{
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+	unsigned int ret;
+
+	op->cipher.keylen = len;
+
+	if (len == AES_KEYSIZE_128) {
+		memcpy(op->cipher.key, key, len);
+		return 0;
+	}
+
+	if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
+		/* not supported at all */
+		tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+		return -EINVAL;
+	}
+
+	/*
+	 * The requested key size is not supported by HW, do a fallback
+	 */
+	op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+	op->fallback.blk->base.crt_flags |= (tfm->crt_flags &
+						CRYPTO_TFM_REQ_MASK);
+
+	ret = crypto_blkcipher_setkey(op->fallback.blk, key, len);
+	if (ret) {
+		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+		tfm->crt_flags |= (op->fallback.blk->base.crt_flags &
+					CRYPTO_TFM_RES_MASK);
+	}
+	return ret;
+}
+
+static int fallback_blk_dec(struct blkcipher_desc *desc,
+		struct scatterlist *dst, struct scatterlist *src,
+		unsigned int nbytes)
+{
+	unsigned int ret;
+	struct crypto_blkcipher *tfm;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+
+	tfm = desc->tfm;
+	desc->tfm = op->fallback.blk;
+
+	ret = crypto_blkcipher_decrypt_iv(desc, dst, src, nbytes);
+
+	desc->tfm = tfm;
+	return ret;
+}
+
+static int fallback_blk_enc(struct blkcipher_desc *desc,
+		struct scatterlist *dst, struct scatterlist *src,
+		unsigned int nbytes)
+{
+	unsigned int ret;
+	struct crypto_blkcipher *tfm;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+
+	tfm = desc->tfm;
+	desc->tfm = op->fallback.blk;
+
+	ret = crypto_blkcipher_encrypt_iv(desc, dst, src, nbytes);
+
+	desc->tfm = tfm;
+	return ret;
+}
+
+static int fallback_init_blk(struct crypto_tfm *tfm)
+{
+	const char *name = tfm->__crt_alg->cra_name;
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	op->fallback.blk = crypto_alloc_blkcipher(name, 0,
+			CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
+
+	if (IS_ERR(op->fallback.blk)) {
+		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+		return PTR_ERR(op->fallback.blk);
+	}
+
+	return 0;
+}
+
+static void fallback_exit_blk(struct crypto_tfm *tfm)
+{
+	struct dcp_op *op = crypto_tfm_ctx(tfm);
+
+	crypto_free_blkcipher(op->fallback.blk);
+	op->fallback.blk = NULL;
+}
+
+static int
+dcp_aes_ecb_decrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_dec(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	/* key needs to be mapped only once */
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+				AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		return -ENOMEM;
+	}
+
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = DCP_AES | DCP_DEC |
+				DCP_ECB;
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+						DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+						DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+						DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+					DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		err = blkcipher_walk_done(desc, &walk, nbytes);
+	}
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+				DMA_TO_DEVICE);
+
+	return err;
+}
+
+static int
+dcp_aes_ecb_encrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, ret;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_enc(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	/* key needs to be mapped only once */
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+				AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		return -ENOMEM;
+	}
+
+	err = blkcipher_walk_virt(desc, &walk);
+
+	err = 0;
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = DCP_AES | DCP_ENC |
+			    DCP_ECB;
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+				DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+				DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+				DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+				DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		ret =  blkcipher_walk_done(desc, &walk, nbytes);
+	}
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+
+	return err;
+}
+
+
+static struct crypto_alg dcp_aes_ecb_alg = {
+	.cra_name		= "ecb(aes)",
+	.cra_driver_name	= "dcp-ecb-aes",
+	.cra_priority		= 400,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_BLKCIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_blk,
+	.cra_exit		= fallback_exit_blk,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct dcp_op),
+	.cra_type		= &crypto_blkcipher_type,
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_ecb_alg.cra_list),
+	.cra_u			= {
+		.blkcipher 	= {
+			.min_keysize	= AES_MIN_KEY_SIZE,
+			.max_keysize	= AES_MAX_KEY_SIZE,
+			.setkey		= dcp_aes_setkey_blk,
+			.encrypt	= dcp_aes_ecb_encrypt,
+			.decrypt	= dcp_aes_ecb_decrypt
+		}
+	}
+};
+
+static int
+dcp_aes_cbc_decrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, blockno;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_dec(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	blockno = 0;
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = DCP_AES | DCP_DEC |
+			    DCP_CBC;
+		if (blockno == 0) {
+			op->flags |= DCP_CBC_INIT;
+			memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv,
+				AES_KEYSIZE_128);
+		}
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* key (+iv) needs to be mapped only once */
+		op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+			dev_err(sdcp->dev, "Unable to map key\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+					DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+						DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+					DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		err = blkcipher_walk_done(desc, &walk, nbytes);
+
+		blockno++;
+	}
+
+	return err;
+}
+
+static int
+dcp_aes_cbc_encrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, ret, blockno;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_enc(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	blockno = 0;
+
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = DCP_AES | DCP_ENC |
+			    DCP_CBC;
+		if (blockno == 0) {
+			op->flags |= DCP_CBC_INIT;
+			memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv,
+				AES_KEYSIZE_128);
+		}
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* key needs to be mapped only once */
+		op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+			dev_err(sdcp->dev, "Unable to map key\n");
+			return -ENOMEM;
+		}
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+				DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+				AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+				DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+				AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+				DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+				DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		ret =  blkcipher_walk_done(desc, &walk, nbytes);
+
+		blockno++;
+	}
+
+	return err;
+}
+
+static struct crypto_alg dcp_aes_cbc_alg = {
+	.cra_name		= "cbc(aes)",
+	.cra_driver_name	= "dcp-cbc-aes",
+	.cra_priority		= 400,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_BLKCIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_blk,
+	.cra_exit		= fallback_exit_blk,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct dcp_op),
+	.cra_type		= &crypto_blkcipher_type,
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_cbc_alg.cra_list),
+	.cra_u			= {
+		.blkcipher 	= {
+			.min_keysize	= AES_MIN_KEY_SIZE,
+			.max_keysize	= AES_MAX_KEY_SIZE,
+			.setkey		= dcp_aes_setkey_blk,
+			.encrypt	= dcp_aes_cbc_encrypt,
+			.decrypt	= dcp_aes_cbc_decrypt,
+			.ivsize		= AES_KEYSIZE_128,
+		}
+	}
+};
+
+static int dcp_perform_hash_op(
+	struct dcp_hash_coherent_block *input,
+	u32 num_desc, bool init, bool terminate)
+{
+	struct dcp *sdcp = global_sdcp;
+	int chan;
+	struct dcp_hw_packet *pkt;
+	struct dcp_hash_coherent_block *hw;
+	unsigned long timeout;
+	u32 stat;
+	int descno, mapped;
+
+	chan = HASH_CHAN;
+
+	hw = input;
+	pkt = hw->pkt;
+
+	for (descno = 0; descno < num_desc; descno++) {
+
+		if (descno != 0) {
+
+			/* set next ptr and CHAIN bit in last packet */
+			pkt->pNext = hw->next->my_phys + offsetof(
+				struct dcp_hash_coherent_block,
+				pkt[0]);
+			pkt->pkt1 |= BM_DCP_PACKET1_CHAIN;
+
+			/* iterate to next descriptor */
+			hw = hw->next;
+			pkt = hw->pkt;
+		}
+
+		pkt->pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE |
+					BM_DCP_PACKET1_ENABLE_HASH;
+
+		if (init && descno == 0)
+			pkt->pkt1 |= BM_DCP_PACKET1_HASH_INIT;
+
+		pkt->pkt2 = BF(hw->hash_sel,
+				DCP_PACKET2_HASH_SELECT);
+
+		/* no need to flush buf1 or buf2, which are uncached */
+		if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2) {
+
+			/* we have to flush the cache for the buffer */
+			hw->src_phys = dma_map_single(sdcp->dev,
+				hw->src, hw->len, DMA_TO_DEVICE);
+
+			if (dma_mapping_error(sdcp->dev, hw->src_phys)) {
+				dev_err(sdcp->dev, "Unable to map source\n");
+
+				/* unmap any previous mapped buffers */
+				for (mapped = 0, hw = input; mapped < descno;
+					mapped++) {
+
+					if (mapped != 0)
+						hw = hw->next;
+					if (hw->src != sdcp->buf1 &&
+						hw->src != sdcp->buf2)
+						dma_unmap_single(sdcp->dev,
+							hw->src_phys, hw->len,
+							DMA_TO_DEVICE);
+				}
+
+				return -EFAULT;
+			}
+		}
+
+		pkt->pSrc = (u32)hw->src_phys;
+		pkt->pDst = 0;
+		pkt->size = hw->len;
+		pkt->pPayload = 0;
+		pkt->stat = 0;
+
+		/* set HASH_TERM bit on last buf if terminate was set */
+		if (terminate && (descno == (num_desc - 1))) {
+			pkt->pkt1 |= BM_DCP_PACKET1_HASH_TERM;
+
+			memset(input->digest, 0, sizeof(input->digest));
+
+			/* set payload ptr to the 1st buffer's digest */
+			pkt->pPayload = (u32)input->my_phys +
+				offsetof(
+				struct dcp_hash_coherent_block,
+				digest);
+		}
+	}
+
+	/* submit the work */
+
+	__raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(chan));
+
+	mb();
+	/* Load the 1st descriptor's physical address */
+	__raw_writel((u32)input->my_phys +
+		offsetof(struct dcp_hash_coherent_block,
+		pkt[0]), sdcp->dcp_regs_base + HW_DCP_CHnCMDPTR(chan));
+
+	/* XXX wake from interrupt instead of looping */
+	timeout = jiffies + msecs_to_jiffies(1000);
+
+	/* write num_desc into sema register */
+	__raw_writel(BF(num_desc, DCP_CHnSEMA_INCREMENT),
+		sdcp->dcp_regs_base + HW_DCP_CHnSEMA(chan));
+
+	while (time_before(jiffies, timeout) &&
+		((__raw_readl(sdcp->dcp_regs_base +
+		HW_DCP_CHnSEMA(chan)) >> 16) & 0xff) != 0) {
+
+		cpu_relax();
+	}
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev,
+			"Timeout while waiting STAT 0x%08x\n",
+			__raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT));
+	}
+
+	stat = __raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(chan));
+	if ((stat & 0xff) != 0)
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+				__raw_readl(sdcp->dcp_regs_base +
+				HW_DCP_CHnSTAT(chan)) & 0xff);
+
+	/* unmap all src buffers */
+	for (descno = 0, hw = input; descno < num_desc; descno++) {
+		if (descno != 0)
+			hw = hw->next;
+		if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2)
+			dma_unmap_single(sdcp->dev, hw->src_phys, hw->len,
+				DMA_TO_DEVICE);
+	}
+
+	return 0;
+
+}
+
+static int dcp_sha_init(struct shash_desc *desc)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_hash_op *op = shash_desc_ctx(desc);
+	struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN];
+
+	mutex_lock(mutex);
+
+	op->length = 0;
+
+	/* reset the lengths and the pointers of buffer descriptors */
+	sdcp->buf1_desc->len = 0;
+	sdcp->buf1_desc->src = sdcp->buf1;
+	sdcp->buf2_desc->len = 0;
+	sdcp->buf2_desc->src = sdcp->buf2;
+	op->head_desc = sdcp->buf1_desc;
+	op->tail_desc = sdcp->buf2_desc;
+
+	return 0;
+}
+
+static int dcp_sha_update(struct shash_desc *desc, const u8 *data,
+		      unsigned int length)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcp_hash_op *op = shash_desc_ctx(desc);
+	struct dcp_hash_coherent_block *temp;
+	u32 rem_bytes, bytes_borrowed, hash_sel;
+	int ret = 0;
+
+	if (strcmp(desc->tfm->base.__crt_alg->cra_name, "sha1") == 0)
+		hash_sel = BV_DCP_PACKET2_HASH_SELECT__SHA1;
+	else
+		hash_sel = BV_DCP_PACKET2_HASH_SELECT__SHA256;
+
+	sdcp->user_buf_desc->src = (void *)data;
+	sdcp->user_buf_desc->len = length;
+
+	op->tail_desc->len = 0;
+
+	/* check if any pending data from previous updates */
+	if (op->head_desc->len) {
+
+			/* borrow from this buffer to make it 64 bytes */
+			bytes_borrowed = min(64 - op->head_desc->len,
+					sdcp->user_buf_desc->len);
+
+			/* copy n bytes to head */
+			memcpy(op->head_desc->src + op->head_desc->len,
+				sdcp->user_buf_desc->src, bytes_borrowed);
+			op->head_desc->len += bytes_borrowed;
+
+			/* update current buffer's src and len */
+			sdcp->user_buf_desc->src += bytes_borrowed;
+			sdcp->user_buf_desc->len -= bytes_borrowed;
+	}
+
+	/* Is current buffer unaligned to 64 byte length?
+	  * Each buffer's length must be a multiple of 64 bytes for DCP
+	  */
+	rem_bytes = sdcp->user_buf_desc->len % 64;
+
+	/* if length is unaligned, copy remainder to tail */
+	if (rem_bytes) {
+
+		memcpy(op->tail_desc->src, (sdcp->user_buf_desc->src +
+			sdcp->user_buf_desc->len - rem_bytes),
+			rem_bytes);
+
+		/* update length of current buffer */
+		sdcp->user_buf_desc->len -= rem_bytes;
+
+		op->tail_desc->len = rem_bytes;
+	}
+
+	/* do not send to DCP if length is < 64 */
+	if ((op->head_desc->len + sdcp->user_buf_desc->len) >= 64) {
+
+		/* set hash alg to be used (SHA1 or SHA256) */
+		op->head_desc->hash_sel = hash_sel;
+		sdcp->user_buf_desc->hash_sel = hash_sel;
+
+		if (op->head_desc->len) {
+			op->head_desc->next = sdcp->user_buf_desc;
+
+			ret = dcp_perform_hash_op(op->head_desc,
+				sdcp->user_buf_desc->len ? 2 : 1,
+				op->length == 0, false);
+		} else {
+			ret = dcp_perform_hash_op(sdcp->user_buf_desc, 1,
+				op->length == 0, false);
+		}
+
+		op->length += op->head_desc->len + sdcp->user_buf_desc->len;
+		op->head_desc->len = 0;
+	}
+
+	/* if tail has bytes, make it the head for next time */
+	if (op->tail_desc->len) {
+		temp = op->head_desc;
+		op->head_desc = op->tail_desc;
+		op->tail_desc = temp;
+	}
+
+	/* hash_sel to be used by final function */
+	op->head_desc->hash_sel = hash_sel;
+
+	return ret;
+}
+
+static int dcp_sha_final(struct shash_desc *desc, u8 *out)
+{
+	struct dcp_hash_op *op = shash_desc_ctx(desc);
+	const uint8_t *digest;
+	struct dcp *sdcp = global_sdcp;
+	u32 i, digest_len;
+	struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN];
+	int ret = 0;
+
+	/* Send the leftover bytes in head, which can be length 0,
+	  * but DCP still produces hash result in payload ptr.
+	  * Last data bytes need not be 64-byte multiple.
+	  */
+	ret = dcp_perform_hash_op(op->head_desc, 1, op->length == 0, true);
+
+	op->length += op->head_desc->len;
+
+	digest_len = (op->head_desc->hash_sel ==
+		BV_DCP_PACKET2_HASH_SELECT__SHA1) ? SHA1_DIGEST_SIZE :
+		SHA256_DIGEST_SIZE;
+
+	/* hardware reverses the digest (for some unexplicable reason) */
+	digest = op->head_desc->digest + digest_len;
+	for (i = 0; i < digest_len; i++)
+		*out++ = *--digest;
+
+	mutex_unlock(mutex);
+
+	return ret;
+}
+
+static struct shash_alg dcp_sha1_alg = {
+	.init			=	dcp_sha_init,
+	.update			=	dcp_sha_update,
+	.final			=	dcp_sha_final,
+	.descsize		=	sizeof(struct dcp_hash_op),
+	.digestsize		=	SHA1_DIGEST_SIZE,
+	.base			=	{
+		.cra_name		=	"sha1",
+		.cra_driver_name	=	"sha1-dcp",
+		.cra_priority		=	300,
+		.cra_blocksize		=	SHA1_BLOCK_SIZE,
+		.cra_ctxsize		=
+			sizeof(struct dcp_hash_op),
+		.cra_module		=	THIS_MODULE,
+	}
+};
+
+static struct shash_alg dcp_sha256_alg = {
+	.init			=	dcp_sha_init,
+	.update			=	dcp_sha_update,
+	.final			=	dcp_sha_final,
+	.descsize		=	sizeof(struct dcp_hash_op),
+	.digestsize		=	SHA256_DIGEST_SIZE,
+	.base			=	{
+		.cra_name		=	"sha256",
+		.cra_driver_name	=	"sha256-dcp",
+		.cra_priority		=	300,
+		.cra_blocksize		=	SHA256_BLOCK_SIZE,
+		.cra_ctxsize		=
+			sizeof(struct dcp_hash_op),
+		.cra_module		=	THIS_MODULE,
+	}
+};
+
+static irqreturn_t dcp_common_irq(int irq, void *context)
+{
+	struct dcp *sdcp = context;
+	u32 msk;
+
+	/* check */
+	msk = __raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT) &
+		BF(0x0f, DCP_STAT_IRQ);
+	if (msk == 0)
+		return IRQ_NONE;
+
+	/* clear this channel */
+	__raw_writel(msk, sdcp->dcp_regs_base + HW_DCP_STAT_CLR);
+	if (msk & BF(0x01, DCP_STAT_IRQ))
+		sdcp->wait[0]++;
+	if (msk & BF(0x02, DCP_STAT_IRQ))
+		sdcp->wait[1]++;
+	if (msk & BF(0x04, DCP_STAT_IRQ))
+		sdcp->wait[2]++;
+	if (msk & BF(0x08, DCP_STAT_IRQ))
+		sdcp->wait[3]++;
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t dcp_vmi_irq(int irq, void *context)
+{
+	return dcp_common_irq(irq, context);
+}
+
+static irqreturn_t dcp_irq(int irq, void *context)
+{
+	return dcp_common_irq(irq, context);
+}
+
+/* DCP bootstream verification interface: uses OTP key for crypto */
+static int dcp_bootstream_ioctl(struct inode *inode, struct file *file,
+					 unsigned int cmd, unsigned long arg)
+{
+	struct dcp *sdcp = global_sdcp;
+	struct dcpboot_dma_area *da = sdcp->dcpboot_dma_area;
+	void __user *argp = (void __user *)arg;
+	int chan = ROM_DCP_CHAN;
+	unsigned long timeout;
+	struct mutex *mutex;
+	int retVal;
+
+	/* be paranoid */
+	if (sdcp == NULL)
+		return -EBADF;
+
+	if (cmd != DBS_ENC && cmd != DBS_DEC)
+		return -EINVAL;
+
+	/* copy to (aligned) block */
+	if (copy_from_user(da->block, argp, 16))
+		return -EFAULT;
+
+	mutex = &sdcp->op_mutex[chan];
+	mutex_lock(mutex);
+
+	__raw_writel(-1, sdcp->dcp_regs_base +
+		HW_DCP_CHnSTAT_CLR(ROM_DCP_CHAN));
+	__raw_writel(BF(ROM_DCP_CHAN_MASK, DCP_STAT_IRQ),
+		sdcp->dcp_regs_base + HW_DCP_STAT_CLR);
+
+	da->hw_packet.pNext = 0;
+	da->hw_packet.pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE |
+	    BM_DCP_PACKET1_ENABLE_CIPHER | BM_DCP_PACKET1_OTP_KEY |
+	    BM_DCP_PACKET1_INTERRUPT |
+	    (cmd == DBS_ENC ? BM_DCP_PACKET1_CIPHER_ENCRYPT : 0);
+	da->hw_packet.pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) |
+	    BF(0, DCP_PACKET2_KEY_SELECT) |
+	    BF(BV_DCP_PACKET2_CIPHER_MODE__ECB, DCP_PACKET2_CIPHER_MODE) |
+	    BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128, DCP_PACKET2_CIPHER_SELECT);
+	da->hw_packet.pSrc = sdcp->dcpboot_dma_area_phys +
+	    offsetof(struct dcpboot_dma_area, block);
+	da->hw_packet.pDst = da->hw_packet.pSrc;	/* in-place */
+	da->hw_packet.size = 16;
+	da->hw_packet.pPayload = 0;
+	da->hw_packet.stat = 0;
+
+	/* Load the work packet pointer and bump the channel semaphore */
+	__raw_writel(sdcp->dcpboot_dma_area_phys +
+		     offsetof(struct dcpboot_dma_area, hw_packet),
+		     sdcp->dcp_regs_base + HW_DCP_CHnCMDPTR(ROM_DCP_CHAN));
+
+	sdcp->wait[chan] = 0;
+	__raw_writel(BF(1, DCP_CHnSEMA_INCREMENT),
+		     sdcp->dcp_regs_base + HW_DCP_CHnSEMA(ROM_DCP_CHAN));
+
+	timeout = jiffies + msecs_to_jiffies(100);
+
+	while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0)
+		cpu_relax();
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev,
+			"Timeout while waiting for operation to complete\n");
+		retVal = -ETIMEDOUT;
+		goto exit;
+	}
+
+	if ((__raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(ROM_DCP_CHAN))
+			& 0xff) != 0) {
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+			__raw_readl(sdcp->dcp_regs_base +
+				    HW_DCP_CHnSTAT(ROM_DCP_CHAN)) & 0xff);
+		retVal = -EFAULT;
+		goto exit;
+	}
+
+	if (copy_to_user(argp, da->block, 16)) {
+		retVal =  -EFAULT;
+		goto exit;
+	}
+
+	retVal = 0;
+
+exit:
+	mutex_unlock(mutex);
+	return retVal;
+}
+
+static const struct file_operations dcp_bootstream_fops = {
+	.owner =	THIS_MODULE,
+	.ioctl =	dcp_bootstream_ioctl,
+};
+
+static struct miscdevice dcp_bootstream_misc = {
+	.minor	= MISC_DYNAMIC_MINOR,
+	.name	= "dcpboot",
+	.fops = &dcp_bootstream_fops,
+};
+
+static int dcp_probe(struct platform_device *pdev)
+{
+	struct dcp *sdcp = NULL;
+	struct resource *r;
+	int i, ret;
+	dma_addr_t hw_phys;
+
+	if (global_sdcp != NULL) {
+		dev_err(&pdev->dev, "Only one instance allowed\n");
+		ret = -ENODEV;
+		goto err;
+	}
+
+	/* allocate memory */
+	sdcp = kzalloc(sizeof(*sdcp), GFP_KERNEL);
+	if (sdcp == NULL) {
+		dev_err(&pdev->dev, "Failed to allocate structure\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	sdcp->dev = &pdev->dev;
+	spin_lock_init(&sdcp->lock);
+
+	for (i = 0; i < DCP_NUM_CHANNELS; i++) {
+		mutex_init(&sdcp->op_mutex[i]);
+		init_completion(&sdcp->op_wait[i]);
+	}
+
+	platform_set_drvdata(pdev, sdcp);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n");
+		ret = -ENXIO;
+		goto err_kfree;
+	}
+	sdcp->dcp_regs_base = (u32) IO_ADDRESS(r->start);
+
+	/* Soft reset and remove the clock gate */
+	__raw_writel(BM_DCP_CTRL_SFTRST, sdcp->dcp_regs_base + HW_DCP_CTRL_SET);
+
+	/* At 24Mhz, it takes no more than 4 clocks (160 ns) Maximum for
+	 * the part to reset, reading the register twice should
+	 * be sufficient to get 4 clks delay.
+	 */
+	__raw_readl(sdcp->dcp_regs_base + HW_DCP_CTRL);
+	__raw_readl(sdcp->dcp_regs_base + HW_DCP_CTRL);
+
+	__raw_writel(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE,
+		sdcp->dcp_regs_base + HW_DCP_CTRL_CLR);
+
+	/* Initialize control registers */
+	__raw_writel(DCP_CTRL_INIT, sdcp->dcp_regs_base + HW_DCP_CTRL);
+	__raw_writel(DCP_CHANNELCTRL_INIT, sdcp->dcp_regs_base +
+		HW_DCP_CHANNELCTRL);
+
+	/* We do not enable context switching. Give the context
+	 * buffer pointer an illegal address so if context switching is
+	 * inadvertantly enabled, the dcp will return an error instead of
+	 * trashing good memory. The dcp dma cannot access rom, so any rom
+	 * address will do.
+	 */
+	__raw_writel(0xFFFF0000, sdcp->dcp_regs_base + HW_DCP_CONTEXT);
+
+	for (i = 0; i < DCP_NUM_CHANNELS; i++)
+		__raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(i));
+	__raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_STAT_CLR);
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IRQ resource (0)\n");
+		ret = -EIO;
+		goto err_kfree;
+	}
+	sdcp->dcp_vmi_irq = r->start;
+	ret = request_irq(sdcp->dcp_vmi_irq, dcp_vmi_irq, 0, "dcp",
+				sdcp);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "can't request_irq (0)\n");
+		goto err_kfree;
+	}
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IRQ resource (1)\n");
+		ret = -EIO;
+		goto err_free_irq0;
+	}
+	sdcp->dcp_irq = r->start;
+	ret = request_irq(sdcp->dcp_irq, dcp_irq, 0, "dcp", sdcp);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "can't request_irq (1)\n");
+		goto err_free_irq0;
+	}
+
+	global_sdcp = sdcp;
+
+	ret = crypto_register_alg(&dcp_aes_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes crypto\n");
+		goto err_kfree;
+	}
+
+	ret = crypto_register_alg(&dcp_aes_ecb_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes ecb crypto\n");
+		goto err_unregister_aes;
+	}
+
+	ret = crypto_register_alg(&dcp_aes_cbc_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes cbc crypto\n");
+		goto err_unregister_aes_ecb;
+	}
+
+	/* Allocate the descriptor to be used for user buffer
+	  * passed in by the "update" function from Crypto API
+	  */
+	sdcp->user_buf_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct dcp_hash_coherent_block),  &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->user_buf_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->user_buf_desc->my_phys = hw_phys;
+
+	/* Allocate 2 buffers (head & tail) & its descriptors to deal with
+	  * buffer lengths that are not 64 byte aligned, except for the
+	  * last one.
+	  */
+	sdcp->buf1 = dma_alloc_coherent(sdcp->dev,
+		64, &sdcp->buf1_phys, GFP_KERNEL);
+	if (sdcp->buf1 == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf2 = dma_alloc_coherent(sdcp->dev,
+		64,  &sdcp->buf2_phys, GFP_KERNEL);
+	if (sdcp->buf2 == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf1_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct dcp_hash_coherent_block), &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->buf1_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf1_desc->my_phys = hw_phys;
+	sdcp->buf1_desc->src = (void *)sdcp->buf1;
+	sdcp->buf1_desc->src_phys = sdcp->buf1_phys;
+
+	sdcp->buf2_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct dcp_hash_coherent_block), &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->buf2_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf2_desc->my_phys = hw_phys;
+	sdcp->buf2_desc->src = (void *)sdcp->buf2;
+	sdcp->buf2_desc->src_phys = sdcp->buf2_phys;
+
+
+	ret = crypto_register_shash(&dcp_sha1_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register sha1 hash\n");
+		goto err_unregister_aes_cbc;
+	}
+
+	if (__raw_readl(sdcp->dcp_regs_base + HW_DCP_CAPABILITY1) &
+		BF_DCP_CAPABILITY1_HASH_ALGORITHMS(
+		BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256)) {
+
+		ret = crypto_register_shash(&dcp_sha256_alg);
+		if (ret != 0)  {
+			dev_err(&pdev->dev, "Failed to register sha256 hash\n");
+			goto err_unregister_sha1;
+		}
+	}
+
+	/* register dcpboot interface to allow apps (such as kobs-ng) to
+	 * verify files (such as the bootstream) using the OTP key for crypto */
+	ret = misc_register(&dcp_bootstream_misc);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "Unable to register misc device\n");
+		goto err_unregister_sha1;
+	}
+
+	sdcp->dcpboot_dma_area = dma_alloc_coherent(&pdev->dev,
+		sizeof(*sdcp->dcpboot_dma_area), &sdcp->dcpboot_dma_area_phys,
+		GFP_KERNEL);
+	if (sdcp->dcpboot_dma_area == NULL) {
+		dev_err(&pdev->dev,
+			"Unable to allocate DMAable memory \
+			 for dcpboot interface\n");
+		goto err_dereg;
+	}
+
+	dev_notice(&pdev->dev, "DCP crypto enabled.!\n");
+	return 0;
+
+err_dereg:
+	misc_deregister(&dcp_bootstream_misc);
+err_unregister_sha1:
+	crypto_unregister_shash(&dcp_sha1_alg);
+err_unregister_aes_cbc:
+	crypto_unregister_alg(&dcp_aes_cbc_alg);
+err_unregister_aes_ecb:
+	crypto_unregister_alg(&dcp_aes_ecb_alg);
+err_unregister_aes:
+	crypto_unregister_alg(&dcp_aes_alg);
+err_free_irq0:
+	free_irq(sdcp->dcp_vmi_irq, sdcp);
+err_kfree:
+	kfree(sdcp);
+err:
+
+	return ret;
+}
+
+static int dcp_remove(struct platform_device *pdev)
+{
+	struct dcp *sdcp;
+
+	sdcp = platform_get_drvdata(pdev);
+	platform_set_drvdata(pdev, NULL);
+
+	free_irq(sdcp->dcp_irq, sdcp);
+	free_irq(sdcp->dcp_vmi_irq, sdcp);
+
+	/* if head and tail buffers were allocated, free them */
+	if (sdcp->buf1) {
+		dma_free_coherent(sdcp->dev, 64, sdcp->buf1, sdcp->buf1_phys);
+		dma_free_coherent(sdcp->dev, 64, sdcp->buf2, sdcp->buf2_phys);
+
+		dma_free_coherent(sdcp->dev,
+				sizeof(struct dcp_hash_coherent_block),
+				sdcp->buf1_desc, sdcp->buf1_desc->my_phys);
+
+		dma_free_coherent(sdcp->dev,
+				sizeof(struct dcp_hash_coherent_block),
+				sdcp->buf2_desc, sdcp->buf2_desc->my_phys);
+
+		dma_free_coherent(sdcp->dev,
+			sizeof(struct dcp_hash_coherent_block),
+			sdcp->user_buf_desc, sdcp->user_buf_desc->my_phys);
+	}
+
+	if (sdcp->dcpboot_dma_area) {
+		dma_free_coherent(&pdev->dev, sizeof(*sdcp->dcpboot_dma_area),
+			  sdcp->dcpboot_dma_area, sdcp->dcpboot_dma_area_phys);
+		misc_deregister(&dcp_bootstream_misc);
+	}
+
+
+	crypto_unregister_shash(&dcp_sha1_alg);
+
+	if (__raw_readl(sdcp->dcp_regs_base + HW_DCP_CAPABILITY1) &
+		BF_DCP_CAPABILITY1_HASH_ALGORITHMS(
+		BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256))
+		crypto_unregister_shash(&dcp_sha256_alg);
+
+	crypto_unregister_alg(&dcp_aes_cbc_alg);
+	crypto_unregister_alg(&dcp_aes_ecb_alg);
+	crypto_unregister_alg(&dcp_aes_alg);
+	kfree(sdcp);
+	global_sdcp = NULL;
+
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int dcp_suspend(struct platform_device *pdev,
+		pm_message_t state)
+{
+	return 0;
+}
+
+static int dcp_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define dcp_suspend	NULL
+#define	dcp_resume	NULL
+#endif
+
+static struct platform_driver dcp_driver = {
+	.probe		= dcp_probe,
+	.remove		= dcp_remove,
+	.suspend	= dcp_suspend,
+	.resume		= dcp_resume,
+	.driver		= {
+		.name   = "dcp",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init
+dcp_init(void)
+{
+	return platform_driver_register(&dcp_driver);
+}
+
+static void __exit
+dcp_exit(void)
+{
+	platform_driver_unregister(&dcp_driver);
+}
+
+MODULE_AUTHOR("Pantelis Antoniou <pantelis@embeddedalley.com>");
+MODULE_DESCRIPTION("DCP Crypto Driver");
+MODULE_LICENSE("GPL");
+
+module_init(dcp_init);
+module_exit(dcp_exit);
diff --git a/drivers/crypto/dcp.h b/drivers/crypto/dcp.h
new file mode 100644
index 000000000000..a4db91334d06
--- /dev/null
+++ b/drivers/crypto/dcp.h
@@ -0,0 +1,717 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef DCP_H_
+#define DCP_H_
+
+#define CIPHER_CHAN	1
+#define CIPHER_MASK	(1 << CIPHER_CHAN)
+
+#define HASH_CHAN	0
+#define HASH_MASK	(1 << HASH_CHAN)
+
+/* DCP boostream interface uses this channel (same as the ROM) */
+#define ROM_DCP_CHAN 3
+#define ROM_DCP_CHAN_MASK (1 << ROM_DCP_CHAN)
+
+
+#define ALL_MASK	(CIPHER_MASK | HASH_MASK | ROM_DCP_CHAN_MASK)
+
+/* Defines the initialization value for the dcp control register */
+#define DCP_CTRL_INIT \
+   (BM_DCP_CTRL_GATHER_RESIDUAL_WRITES | \
+    BM_DCP_CTRL_ENABLE_CONTEXT_CACHING | \
+    BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 | \
+    BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 | \
+    BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 | \
+    BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3)
+
+/* Defines the initialization value for the dcp channel control register */
+#define DCP_CHANNELCTRL_INIT \
+    BF(ALL_MASK, DCP_CHANNELCTRL_ENABLE_CHANNEL)
+
+/* DCP work packet 1 value for encryption */
+#define DCP_PKT1_ENCRYPT \
+   (BM_DCP_PACKET1_DECR_SEMAPHORE | \
+    BM_DCP_PACKET1_ENABLE_CIPHER | \
+    BM_DCP_PACKET1_CIPHER_ENCRYPT | \
+    BM_DCP_PACKET1_CIPHER_INIT)
+
+/* DCP work packet 1 value for decryption */
+#define DCP_PKT1_DECRYPT \
+   (BM_DCP_PACKET1_DECR_SEMAPHORE | \
+    BM_DCP_PACKET1_ENABLE_CIPHER | \
+    BM_DCP_PACKET1_CIPHER_INIT)
+
+/* DCP (decryption) work packet definition */
+struct dcp_hw_packet {
+	uint32_t pNext;     /* next dcp work packet address */
+	uint32_t pkt1;      /* dcp work packet 1 (control 0) */
+	uint32_t pkt2;      /* dcp work packet 2 (control 1) */
+	uint32_t pSrc;      /* source buffer address */
+	uint32_t pDst;      /* destination buffer address */
+	uint32_t size;      /* buffer size in bytes */
+	uint32_t pPayload;  /* payload buffer address */
+	uint32_t stat;      /* dcp status (written by dcp) */
+};
+
+#define DCP_NUM_CHANNELS 4
+
+/* DCP Register definitions */
+
+#ifndef BF
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+#endif
+
+#define REGS_DCP_SIZE 0x00002000
+
+#define HW_DCP_CTRL	(0x00000000)
+#define HW_DCP_CTRL_SET	(0x00000004)
+#define HW_DCP_CTRL_CLR	(0x00000008)
+#define HW_DCP_CTRL_TOG	(0x0000000c)
+
+#define BM_DCP_CTRL_SFTRST	0x80000000
+#define BM_DCP_CTRL_CLKGATE	0x40000000
+#define BM_DCP_CTRL_PRESENT_CRYPTO	0x20000000
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent  0x0
+#define BM_DCP_CTRL_PRESENT_CSC	0x10000000
+#define BV_DCP_CTRL_PRESENT_CSC__Present 0x1
+#define BV_DCP_CTRL_PRESENT_CSC__Absent  0x0
+#define BP_DCP_CTRL_RSVD1	24
+#define BM_DCP_CTRL_RSVD1	0x0F000000
+#define BF_DCP_CTRL_RSVD1(v)  \
+		(((v) << 24) & BM_DCP_CTRL_RSVD1)
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES	0x00800000
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING	0x00400000
+#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING	0x00200000
+#define BP_DCP_CTRL_RSVD0	9
+#define BM_DCP_CTRL_RSVD0	0x001FFE00
+#define BF_DCP_CTRL_RSVD0(v)  \
+		(((v) << 9) & BM_DCP_CTRL_RSVD0)
+#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE	0x00000100
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE	0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE	0x000000FF
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)  \
+		(((v) << 0) & BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE)
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x01
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x02
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x04
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x08
+
+#define HW_DCP_STAT	(0x00000010)
+#define HW_DCP_STAT_SET	(0x00000014)
+#define HW_DCP_STAT_CLR	(0x00000018)
+#define HW_DCP_STAT_TOG	(0x0000001c)
+
+#define BP_DCP_STAT_RSVD2	29
+#define BM_DCP_STAT_RSVD2	0xE0000000
+#define BF_DCP_STAT_RSVD2(v) \
+		(((v) << 29) & BM_DCP_STAT_RSVD2)
+#define BM_DCP_STAT_OTP_KEY_READY	0x10000000
+#define BP_DCP_STAT_CUR_CHANNEL	24
+#define BM_DCP_STAT_CUR_CHANNEL	0x0F000000
+#define BF_DCP_STAT_CUR_CHANNEL(v)  \
+		(((v) << 24) & BM_DCP_STAT_CUR_CHANNEL)
+#define BV_DCP_STAT_CUR_CHANNEL__None 0x0
+#define BV_DCP_STAT_CUR_CHANNEL__CH0  0x1
+#define BV_DCP_STAT_CUR_CHANNEL__CH1  0x2
+#define BV_DCP_STAT_CUR_CHANNEL__CH2  0x3
+#define BV_DCP_STAT_CUR_CHANNEL__CH3  0x4
+#define BV_DCP_STAT_CUR_CHANNEL__CSC  0x8
+#define BP_DCP_STAT_READY_CHANNELS	16
+#define BM_DCP_STAT_READY_CHANNELS	0x00FF0000
+#define BF_DCP_STAT_READY_CHANNELS(v)  \
+		(((v) << 16) & BM_DCP_STAT_READY_CHANNELS)
+#define BV_DCP_STAT_READY_CHANNELS__CH0 0x01
+#define BV_DCP_STAT_READY_CHANNELS__CH1 0x02
+#define BV_DCP_STAT_READY_CHANNELS__CH2 0x04
+#define BV_DCP_STAT_READY_CHANNELS__CH3 0x08
+#define BP_DCP_STAT_RSVD1	9
+#define BM_DCP_STAT_RSVD1	0x0000FE00
+#define BF_DCP_STAT_RSVD1(v)  \
+		(((v) << 9) & BM_DCP_STAT_RSVD1)
+#define BM_DCP_STAT_CSCIRQ	0x00000100
+#define BP_DCP_STAT_RSVD0	4
+#define BM_DCP_STAT_RSVD0	0x000000F0
+#define BF_DCP_STAT_RSVD0(v)  \
+		(((v) << 4) & BM_DCP_STAT_RSVD0)
+#define BP_DCP_STAT_IRQ	0
+#define BM_DCP_STAT_IRQ	0x0000000F
+#define BF_DCP_STAT_IRQ(v)  \
+		(((v) << 0) & BM_DCP_STAT_IRQ)
+
+#define HW_DCP_CHANNELCTRL	(0x00000020)
+#define HW_DCP_CHANNELCTRL_SET	(0x00000024)
+#define HW_DCP_CHANNELCTRL_CLR	(0x00000028)
+#define HW_DCP_CHANNELCTRL_TOG	(0x0000002c)
+
+#define BP_DCP_CHANNELCTRL_RSVD	19
+#define BM_DCP_CHANNELCTRL_RSVD	0xFFF80000
+#define BF_DCP_CHANNELCTRL_RSVD(v) \
+		(((v) << 19) & BM_DCP_CHANNELCTRL_RSVD)
+#define BP_DCP_CHANNELCTRL_CSC_PRIORITY	17
+#define BM_DCP_CHANNELCTRL_CSC_PRIORITY	0x00060000
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)  \
+		(((v) << 17) & BM_DCP_CHANNELCTRL_CSC_PRIORITY)
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH       0x3
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED        0x2
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW        0x1
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0
+#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED	0x00010000
+#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL	8
+#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL	0x0000FF00
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)  \
+		(((v) << 8) & BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL)
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x01
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x02
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x04
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x08
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL	0
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL	0x000000FF
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)  \
+		(((v) << 0) & BM_DCP_CHANNELCTRL_ENABLE_CHANNEL)
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x01
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x02
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x04
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x08
+
+#define HW_DCP_CAPABILITY0	(0x00000030)
+
+#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT	0x80000000
+#define BM_DCP_CAPABILITY0_ENABLE_TZONE	0x40000000
+#define BP_DCP_CAPABILITY0_RSVD	12
+#define BM_DCP_CAPABILITY0_RSVD	0x3FFFF000
+#define BF_DCP_CAPABILITY0_RSVD(v)  \
+		(((v) << 12) & BM_DCP_CAPABILITY0_RSVD)
+#define BP_DCP_CAPABILITY0_NUM_CHANNELS	8
+#define BM_DCP_CAPABILITY0_NUM_CHANNELS	0x00000F00
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)  \
+		(((v) << 8) & BM_DCP_CAPABILITY0_NUM_CHANNELS)
+#define BP_DCP_CAPABILITY0_NUM_KEYS	0
+#define BM_DCP_CAPABILITY0_NUM_KEYS	0x000000FF
+#define BF_DCP_CAPABILITY0_NUM_KEYS(v)  \
+		(((v) << 0) & BM_DCP_CAPABILITY0_NUM_KEYS)
+
+#define HW_DCP_CAPABILITY1	(0x00000040)
+
+#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS	16
+#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS	0xFFFF0000
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) \
+		(((v) << 16) & BM_DCP_CAPABILITY1_HASH_ALGORITHMS)
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1  0x0001
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x0002
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256  0x0004
+#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS	0
+#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS	0x0000FFFF
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)  \
+		(((v) << 0) & BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS)
+#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x0001
+
+#define HW_DCP_CONTEXT	(0x00000050)
+
+#define BP_DCP_CONTEXT_ADDR	0
+#define BM_DCP_CONTEXT_ADDR	0xFFFFFFFF
+#define BF_DCP_CONTEXT_ADDR(v)	(v)
+
+#define HW_DCP_KEY	(0x00000060)
+
+#define BP_DCP_KEY_RSVD	8
+#define BM_DCP_KEY_RSVD	0xFFFFFF00
+#define BF_DCP_KEY_RSVD(v) \
+		(((v) << 8) & BM_DCP_KEY_RSVD)
+#define BP_DCP_KEY_RSVD_INDEX	6
+#define BM_DCP_KEY_RSVD_INDEX	0x000000C0
+#define BF_DCP_KEY_RSVD_INDEX(v)  \
+		(((v) << 6) & BM_DCP_KEY_RSVD_INDEX)
+#define BP_DCP_KEY_INDEX	4
+#define BM_DCP_KEY_INDEX	0x00000030
+#define BF_DCP_KEY_INDEX(v)  \
+		(((v) << 4) & BM_DCP_KEY_INDEX)
+#define BP_DCP_KEY_RSVD_SUBWORD	2
+#define BM_DCP_KEY_RSVD_SUBWORD	0x0000000C
+#define BF_DCP_KEY_RSVD_SUBWORD(v)  \
+		(((v) << 2) & BM_DCP_KEY_RSVD_SUBWORD)
+#define BP_DCP_KEY_SUBWORD	0
+#define BM_DCP_KEY_SUBWORD	0x00000003
+#define BF_DCP_KEY_SUBWORD(v)  \
+		(((v) << 0) & BM_DCP_KEY_SUBWORD)
+
+#define HW_DCP_KEYDATA	(0x00000070)
+
+#define BP_DCP_KEYDATA_DATA	0
+#define BM_DCP_KEYDATA_DATA	0xFFFFFFFF
+#define BF_DCP_KEYDATA_DATA(v)	(v)
+
+#define HW_DCP_PACKET0	(0x00000080)
+
+#define BP_DCP_PACKET0_ADDR	0
+#define BM_DCP_PACKET0_ADDR	0xFFFFFFFF
+#define BF_DCP_PACKET0_ADDR(v)	(v)
+
+#define HW_DCP_PACKET1	(0x00000090)
+
+#define BP_DCP_PACKET1_TAG	24
+#define BM_DCP_PACKET1_TAG	0xFF000000
+#define BF_DCP_PACKET1_TAG(v) \
+		(((v) << 24) & BM_DCP_PACKET1_TAG)
+#define BM_DCP_PACKET1_OUTPUT_WORDSWAP	0x00800000
+#define BM_DCP_PACKET1_OUTPUT_BYTESWAP	0x00400000
+#define BM_DCP_PACKET1_INPUT_WORDSWAP	0x00200000
+#define BM_DCP_PACKET1_INPUT_BYTESWAP	0x00100000
+#define BM_DCP_PACKET1_KEY_WORDSWAP	0x00080000
+#define BM_DCP_PACKET1_KEY_BYTESWAP	0x00040000
+#define BM_DCP_PACKET1_TEST_SEMA_IRQ	0x00020000
+#define BM_DCP_PACKET1_CONSTANT_FILL	0x00010000
+#define BM_DCP_PACKET1_HASH_OUTPUT	0x00008000
+#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT  0x00
+#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x01
+#define BM_DCP_PACKET1_CHECK_HASH	0x00004000
+#define BM_DCP_PACKET1_HASH_TERM	0x00002000
+#define BM_DCP_PACKET1_HASH_INIT	0x00001000
+#define BM_DCP_PACKET1_PAYLOAD_KEY	0x00000800
+#define BM_DCP_PACKET1_OTP_KEY	0x00000400
+#define BM_DCP_PACKET1_CIPHER_INIT	0x00000200
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT	0x00000100
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x01
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x00
+#define BM_DCP_PACKET1_ENABLE_BLIT	0x00000080
+#define BM_DCP_PACKET1_ENABLE_HASH	0x00000040
+#define BM_DCP_PACKET1_ENABLE_CIPHER	0x00000020
+#define BM_DCP_PACKET1_ENABLE_MEMCOPY	0x00000010
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS	0x00000008
+#define BM_DCP_PACKET1_CHAIN	0x00000004
+#define BM_DCP_PACKET1_DECR_SEMAPHORE	0x00000002
+#define BM_DCP_PACKET1_INTERRUPT	0x00000001
+
+#define HW_DCP_PACKET2	(0x000000a0)
+
+#define BP_DCP_PACKET2_CIPHER_CFG	24
+#define BM_DCP_PACKET2_CIPHER_CFG	0xFF000000
+#define BF_DCP_PACKET2_CIPHER_CFG(v) \
+		(((v) << 24) & BM_DCP_PACKET2_CIPHER_CFG)
+#define BP_DCP_PACKET2_RSVD	20
+#define BM_DCP_PACKET2_RSVD	0x00F00000
+#define BF_DCP_PACKET2_RSVD(v)  \
+		(((v) << 20) & BM_DCP_PACKET2_RSVD)
+#define BP_DCP_PACKET2_HASH_SELECT	16
+#define BM_DCP_PACKET2_HASH_SELECT	0x000F0000
+#define BF_DCP_PACKET2_HASH_SELECT(v)  \
+		(((v) << 16) & BM_DCP_PACKET2_HASH_SELECT)
+#define BV_DCP_PACKET2_HASH_SELECT__SHA1  0x00
+#define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x01
+#define BV_DCP_PACKET2_HASH_SELECT__SHA256  0x02
+#define BP_DCP_PACKET2_KEY_SELECT	8
+#define BM_DCP_PACKET2_KEY_SELECT	0x0000FF00
+#define BF_DCP_PACKET2_KEY_SELECT(v)  \
+		(((v) << 8) & BM_DCP_PACKET2_KEY_SELECT)
+#define BP_DCP_PACKET2_CIPHER_MODE	4
+#define BM_DCP_PACKET2_CIPHER_MODE	0x000000F0
+#define BF_DCP_PACKET2_CIPHER_MODE(v)  \
+		(((v) << 4) & BM_DCP_PACKET2_CIPHER_MODE)
+#define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x00
+#define BV_DCP_PACKET2_CIPHER_MODE__CBC 0x01
+#define BP_DCP_PACKET2_CIPHER_SELECT	0
+#define BM_DCP_PACKET2_CIPHER_SELECT	0x0000000F
+#define BF_DCP_PACKET2_CIPHER_SELECT(v)  \
+		(((v) << 0) & BM_DCP_PACKET2_CIPHER_SELECT)
+#define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x00
+
+#define HW_DCP_PACKET3	(0x000000b0)
+
+#define BP_DCP_PACKET3_ADDR	0
+#define BM_DCP_PACKET3_ADDR	0xFFFFFFFF
+#define BF_DCP_PACKET3_ADDR(v)	(v)
+
+#define HW_DCP_PACKET4	(0x000000c0)
+
+#define BP_DCP_PACKET4_ADDR	0
+#define BM_DCP_PACKET4_ADDR	0xFFFFFFFF
+#define BF_DCP_PACKET4_ADDR(v)	(v)
+
+#define HW_DCP_PACKET5	(0x000000d0)
+
+#define BP_DCP_PACKET5_COUNT	0
+#define BM_DCP_PACKET5_COUNT	0xFFFFFFFF
+#define BF_DCP_PACKET5_COUNT(v)	(v)
+
+#define HW_DCP_PACKET6	(0x000000e0)
+
+#define BP_DCP_PACKET6_ADDR	0
+#define BM_DCP_PACKET6_ADDR	0xFFFFFFFF
+#define BF_DCP_PACKET6_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_DCP_CHnCMDPTR
+ *              base 0x00000100
+ *              count 4
+ *              offset 0x40
+ */
+#define HW_DCP_CHnCMDPTR(n)	(0x00000100 + (n) * 0x40)
+
+#define BP_DCP_CHnCMDPTR_ADDR	0
+#define BM_DCP_CHnCMDPTR_ADDR	0xFFFFFFFF
+#define BF_DCP_CHnCMDPTR_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_DCP_CHnSEMA
+ *              base 0x00000110
+ *              count 4
+ *              offset 0x40
+ */
+#define HW_DCP_CHnSEMA(n)	(0x00000110 + (n) * 0x40)
+
+#define BP_DCP_CHnSEMA_RSVD2	24
+#define BM_DCP_CHnSEMA_RSVD2	0xFF000000
+#define BF_DCP_CHnSEMA_RSVD2(v) \
+		(((v) << 24) & BM_DCP_CHnSEMA_RSVD2)
+#define BP_DCP_CHnSEMA_VALUE	16
+#define BM_DCP_CHnSEMA_VALUE	0x00FF0000
+#define BF_DCP_CHnSEMA_VALUE(v)  \
+		(((v) << 16) & BM_DCP_CHnSEMA_VALUE)
+#define BP_DCP_CHnSEMA_RSVD1	8
+#define BM_DCP_CHnSEMA_RSVD1	0x0000FF00
+#define BF_DCP_CHnSEMA_RSVD1(v)  \
+		(((v) << 8) & BM_DCP_CHnSEMA_RSVD1)
+#define BP_DCP_CHnSEMA_INCREMENT	0
+#define BM_DCP_CHnSEMA_INCREMENT	0x000000FF
+#define BF_DCP_CHnSEMA_INCREMENT(v)  \
+		(((v) << 0) & BM_DCP_CHnSEMA_INCREMENT)
+
+/*
+ *  multi-register-define name HW_DCP_CHnSTAT
+ *              base 0x00000120
+ *              count 4
+ *              offset 0x40
+ */
+#define HW_DCP_CHnSTAT(n)	(0x00000120 + (n) * 0x40)
+#define HW_DCP_CHnSTAT_SET(n)	(0x00000124 + (n) * 0x40)
+#define HW_DCP_CHnSTAT_CLR(n)	(0x00000128 + (n) * 0x40)
+#define HW_DCP_CHnSTAT_TOG(n)	(0x0000012c + (n) * 0x40)
+
+#define BP_DCP_CHnSTAT_TAG	24
+#define BM_DCP_CHnSTAT_TAG	0xFF000000
+#define BF_DCP_CHnSTAT_TAG(v) \
+		(((v) << 24) & BM_DCP_CHnSTAT_TAG)
+#define BP_DCP_CHnSTAT_ERROR_CODE	16
+#define BM_DCP_CHnSTAT_ERROR_CODE	0x00FF0000
+#define BF_DCP_CHnSTAT_ERROR_CODE(v)  \
+		(((v) << 16) & BM_DCP_CHnSTAT_ERROR_CODE)
+#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x01
+#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN        0x02
+#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR   0x03
+#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR   0x04
+#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE    0x05
+#define BP_DCP_CHnSTAT_RSVD0	7
+#define BM_DCP_CHnSTAT_RSVD0	0x0000FF80
+#define BF_DCP_CHnSTAT_RSVD0(v)  \
+		(((v) << 7) & BM_DCP_CHnSTAT_RSVD0)
+#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT	0x00000040
+#define BM_DCP_CHnSTAT_ERROR_DST	0x00000020
+#define BM_DCP_CHnSTAT_ERROR_SRC	0x00000010
+#define BM_DCP_CHnSTAT_ERROR_PACKET	0x00000008
+#define BM_DCP_CHnSTAT_ERROR_SETUP	0x00000004
+#define BM_DCP_CHnSTAT_HASH_MISMATCH	0x00000002
+#define BM_DCP_CHnSTAT_RSVD_COMPLETE	0x00000001
+
+/*
+ *  multi-register-define name HW_DCP_CHnOPTS
+ *              base 0x00000130
+ *              count 4
+ *              offset 0x40
+ */
+#define HW_DCP_CHnOPTS(n)	(0x00000130 + (n) * 0x40)
+#define HW_DCP_CHnOPTS_SET(n)	(0x00000134 + (n) * 0x40)
+#define HW_DCP_CHnOPTS_CLR(n)	(0x00000138 + (n) * 0x40)
+#define HW_DCP_CHnOPTS_TOG(n)	(0x0000013c + (n) * 0x40)
+
+#define BP_DCP_CHnOPTS_RSVD	16
+#define BM_DCP_CHnOPTS_RSVD	0xFFFF0000
+#define BF_DCP_CHnOPTS_RSVD(v) \
+		(((v) << 16) & BM_DCP_CHnOPTS_RSVD)
+#define BP_DCP_CHnOPTS_RECOVERY_TIMER	0
+#define BM_DCP_CHnOPTS_RECOVERY_TIMER	0x0000FFFF
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)  \
+		(((v) << 0) & BM_DCP_CHnOPTS_RECOVERY_TIMER)
+
+#define HW_DCP_CSCCTRL0	(0x00000300)
+#define HW_DCP_CSCCTRL0_SET	(0x00000304)
+#define HW_DCP_CSCCTRL0_CLR	(0x00000308)
+#define HW_DCP_CSCCTRL0_TOG	(0x0000030c)
+
+#define BP_DCP_CSCCTRL0_RSVD1	16
+#define BM_DCP_CSCCTRL0_RSVD1	0xFFFF0000
+#define BF_DCP_CSCCTRL0_RSVD1(v) \
+		(((v) << 16) & BM_DCP_CSCCTRL0_RSVD1)
+#define BM_DCP_CSCCTRL0_CLIP	0x00008000
+#define BM_DCP_CSCCTRL0_UPSAMPLE	0x00004000
+#define BM_DCP_CSCCTRL0_SCALE	0x00002000
+#define BM_DCP_CSCCTRL0_ROTATE	0x00001000
+#define BM_DCP_CSCCTRL0_SUBSAMPLE	0x00000800
+#define BM_DCP_CSCCTRL0_DELTA	0x00000400
+#define BP_DCP_CSCCTRL0_RGB_FORMAT	8
+#define BM_DCP_CSCCTRL0_RGB_FORMAT	0x00000300
+#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)  \
+		(((v) << 8) & BM_DCP_CSCCTRL0_RGB_FORMAT)
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI    0x1
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24     0x2
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I   0x3
+#define BP_DCP_CSCCTRL0_YUV_FORMAT	4
+#define BM_DCP_CSCCTRL0_YUV_FORMAT	0x000000F0
+#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)  \
+		(((v) << 4) & BM_DCP_CSCCTRL0_YUV_FORMAT)
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2
+#define BP_DCP_CSCCTRL0_RSVD0	1
+#define BM_DCP_CSCCTRL0_RSVD0	0x0000000E
+#define BF_DCP_CSCCTRL0_RSVD0(v)  \
+		(((v) << 1) & BM_DCP_CSCCTRL0_RSVD0)
+#define BM_DCP_CSCCTRL0_ENABLE	0x00000001
+
+#define HW_DCP_CSCSTAT	(0x00000310)
+#define HW_DCP_CSCSTAT_SET	(0x00000314)
+#define HW_DCP_CSCSTAT_CLR	(0x00000318)
+#define HW_DCP_CSCSTAT_TOG	(0x0000031c)
+
+#define BP_DCP_CSCSTAT_RSVD3	24
+#define BM_DCP_CSCSTAT_RSVD3	0xFF000000
+#define BF_DCP_CSCSTAT_RSVD3(v) \
+		(((v) << 24) & BM_DCP_CSCSTAT_RSVD3)
+#define BP_DCP_CSCSTAT_ERROR_CODE	16
+#define BM_DCP_CSCSTAT_ERROR_CODE	0x00FF0000
+#define BF_DCP_CSCSTAT_ERROR_CODE(v)  \
+		(((v) << 16) & BM_DCP_CSCSTAT_ERROR_CODE)
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x01
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x02
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x03
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x04
+#define BP_DCP_CSCSTAT_RSVD2	7
+#define BM_DCP_CSCSTAT_RSVD2	0x0000FF80
+#define BF_DCP_CSCSTAT_RSVD2(v)  \
+		(((v) << 7) & BM_DCP_CSCSTAT_RSVD2)
+#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT	0x00000040
+#define BM_DCP_CSCSTAT_ERROR_DST	0x00000020
+#define BM_DCP_CSCSTAT_ERROR_SRC	0x00000010
+#define BM_DCP_CSCSTAT_RSVD1	0x00000008
+#define BM_DCP_CSCSTAT_ERROR_SETUP	0x00000004
+#define BM_DCP_CSCSTAT_RSVD0	0x00000002
+#define BM_DCP_CSCSTAT_COMPLETE	0x00000001
+
+#define HW_DCP_CSCOUTBUFPARAM	(0x00000320)
+
+#define BP_DCP_CSCOUTBUFPARAM_RSVD1	24
+#define BM_DCP_CSCOUTBUFPARAM_RSVD1	0xFF000000
+#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v) \
+		(((v) << 24) & BM_DCP_CSCOUTBUFPARAM_RSVD1)
+#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE	12
+#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE	0x00FFF000
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v)  \
+		(((v) << 12) & BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE)
+#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE	0
+#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE	0x00000FFF
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  \
+		(((v) << 0) & BM_DCP_CSCOUTBUFPARAM_LINE_SIZE)
+
+#define HW_DCP_CSCINBUFPARAM	(0x00000330)
+
+#define BP_DCP_CSCINBUFPARAM_RSVD1	12
+#define BM_DCP_CSCINBUFPARAM_RSVD1	0xFFFFF000
+#define BF_DCP_CSCINBUFPARAM_RSVD1(v) \
+		(((v) << 12) & BM_DCP_CSCINBUFPARAM_RSVD1)
+#define BP_DCP_CSCINBUFPARAM_LINE_SIZE	0
+#define BM_DCP_CSCINBUFPARAM_LINE_SIZE	0x00000FFF
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)  \
+		(((v) << 0) & BM_DCP_CSCINBUFPARAM_LINE_SIZE)
+
+#define HW_DCP_CSCRGB	(0x00000340)
+
+#define BP_DCP_CSCRGB_ADDR	0
+#define BM_DCP_CSCRGB_ADDR	0xFFFFFFFF
+#define BF_DCP_CSCRGB_ADDR(v)	(v)
+
+#define HW_DCP_CSCLUMA	(0x00000350)
+
+#define BP_DCP_CSCLUMA_ADDR	0
+#define BM_DCP_CSCLUMA_ADDR	0xFFFFFFFF
+#define BF_DCP_CSCLUMA_ADDR(v)	(v)
+
+#define HW_DCP_CSCCHROMAU	(0x00000360)
+
+#define BP_DCP_CSCCHROMAU_ADDR	0
+#define BM_DCP_CSCCHROMAU_ADDR	0xFFFFFFFF
+#define BF_DCP_CSCCHROMAU_ADDR(v)	(v)
+
+#define HW_DCP_CSCCHROMAV	(0x00000370)
+
+#define BP_DCP_CSCCHROMAV_ADDR	0
+#define BM_DCP_CSCCHROMAV_ADDR	0xFFFFFFFF
+#define BF_DCP_CSCCHROMAV_ADDR(v)	(v)
+
+#define HW_DCP_CSCCOEFF0	(0x00000380)
+
+#define BP_DCP_CSCCOEFF0_RSVD1	26
+#define BM_DCP_CSCCOEFF0_RSVD1	0xFC000000
+#define BF_DCP_CSCCOEFF0_RSVD1(v) \
+		(((v) << 26) & BM_DCP_CSCCOEFF0_RSVD1)
+#define BP_DCP_CSCCOEFF0_C0	16
+#define BM_DCP_CSCCOEFF0_C0	0x03FF0000
+#define BF_DCP_CSCCOEFF0_C0(v)  \
+		(((v) << 16) & BM_DCP_CSCCOEFF0_C0)
+#define BP_DCP_CSCCOEFF0_UV_OFFSET	8
+#define BM_DCP_CSCCOEFF0_UV_OFFSET	0x0000FF00
+#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)  \
+		(((v) << 8) & BM_DCP_CSCCOEFF0_UV_OFFSET)
+#define BP_DCP_CSCCOEFF0_Y_OFFSET	0
+#define BM_DCP_CSCCOEFF0_Y_OFFSET	0x000000FF
+#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)  \
+		(((v) << 0) & BM_DCP_CSCCOEFF0_Y_OFFSET)
+
+#define HW_DCP_CSCCOEFF1	(0x00000390)
+
+#define BP_DCP_CSCCOEFF1_RSVD1	26
+#define BM_DCP_CSCCOEFF1_RSVD1	0xFC000000
+#define BF_DCP_CSCCOEFF1_RSVD1(v) \
+		(((v) << 26) & BM_DCP_CSCCOEFF1_RSVD1)
+#define BP_DCP_CSCCOEFF1_C1	16
+#define BM_DCP_CSCCOEFF1_C1	0x03FF0000
+#define BF_DCP_CSCCOEFF1_C1(v)  \
+		(((v) << 16) & BM_DCP_CSCCOEFF1_C1)
+#define BP_DCP_CSCCOEFF1_RSVD0	10
+#define BM_DCP_CSCCOEFF1_RSVD0	0x0000FC00
+#define BF_DCP_CSCCOEFF1_RSVD0(v)  \
+		(((v) << 10) & BM_DCP_CSCCOEFF1_RSVD0)
+#define BP_DCP_CSCCOEFF1_C4	0
+#define BM_DCP_CSCCOEFF1_C4	0x000003FF
+#define BF_DCP_CSCCOEFF1_C4(v)  \
+		(((v) << 0) & BM_DCP_CSCCOEFF1_C4)
+
+#define HW_DCP_CSCCOEFF2	(0x000003a0)
+
+#define BP_DCP_CSCCOEFF2_RSVD1	26
+#define BM_DCP_CSCCOEFF2_RSVD1	0xFC000000
+#define BF_DCP_CSCCOEFF2_RSVD1(v) \
+		(((v) << 26) & BM_DCP_CSCCOEFF2_RSVD1)
+#define BP_DCP_CSCCOEFF2_C2	16
+#define BM_DCP_CSCCOEFF2_C2	0x03FF0000
+#define BF_DCP_CSCCOEFF2_C2(v)  \
+		(((v) << 16) & BM_DCP_CSCCOEFF2_C2)
+#define BP_DCP_CSCCOEFF2_RSVD0	10
+#define BM_DCP_CSCCOEFF2_RSVD0	0x0000FC00
+#define BF_DCP_CSCCOEFF2_RSVD0(v)  \
+		(((v) << 10) & BM_DCP_CSCCOEFF2_RSVD0)
+#define BP_DCP_CSCCOEFF2_C3	0
+#define BM_DCP_CSCCOEFF2_C3	0x000003FF
+#define BF_DCP_CSCCOEFF2_C3(v)  \
+		(((v) << 0) & BM_DCP_CSCCOEFF2_C3)
+
+#define HW_DCP_CSCCLIP	(0x000003d0)
+
+#define BP_DCP_CSCCLIP_RSVD1	24
+#define BM_DCP_CSCCLIP_RSVD1	0xFF000000
+#define BF_DCP_CSCCLIP_RSVD1(v) \
+		(((v) << 24) & BM_DCP_CSCCLIP_RSVD1)
+#define BP_DCP_CSCCLIP_HEIGHT	12
+#define BM_DCP_CSCCLIP_HEIGHT	0x00FFF000
+#define BF_DCP_CSCCLIP_HEIGHT(v)  \
+		(((v) << 12) & BM_DCP_CSCCLIP_HEIGHT)
+#define BP_DCP_CSCCLIP_WIDTH	0
+#define BM_DCP_CSCCLIP_WIDTH	0x00000FFF
+#define BF_DCP_CSCCLIP_WIDTH(v)  \
+		(((v) << 0) & BM_DCP_CSCCLIP_WIDTH)
+
+#define HW_DCP_CSCXSCALE	(0x000003e0)
+
+#define BP_DCP_CSCXSCALE_RSVD1	26
+#define BM_DCP_CSCXSCALE_RSVD1	0xFC000000
+#define BF_DCP_CSCXSCALE_RSVD1(v) \
+		(((v) << 26) & BM_DCP_CSCXSCALE_RSVD1)
+#define BP_DCP_CSCXSCALE_INT	24
+#define BM_DCP_CSCXSCALE_INT	0x03000000
+#define BF_DCP_CSCXSCALE_INT(v)  \
+		(((v) << 24) & BM_DCP_CSCXSCALE_INT)
+#define BP_DCP_CSCXSCALE_FRAC	12
+#define BM_DCP_CSCXSCALE_FRAC	0x00FFF000
+#define BF_DCP_CSCXSCALE_FRAC(v)  \
+		(((v) << 12) & BM_DCP_CSCXSCALE_FRAC)
+#define BP_DCP_CSCXSCALE_WIDTH	0
+#define BM_DCP_CSCXSCALE_WIDTH	0x00000FFF
+#define BF_DCP_CSCXSCALE_WIDTH(v)  \
+		(((v) << 0) & BM_DCP_CSCXSCALE_WIDTH)
+
+#define HW_DCP_CSCYSCALE	(0x000003f0)
+
+#define BP_DCP_CSCYSCALE_RSVD1	26
+#define BM_DCP_CSCYSCALE_RSVD1	0xFC000000
+#define BF_DCP_CSCYSCALE_RSVD1(v) \
+		(((v) << 26) & BM_DCP_CSCYSCALE_RSVD1)
+#define BP_DCP_CSCYSCALE_INT	24
+#define BM_DCP_CSCYSCALE_INT	0x03000000
+#define BF_DCP_CSCYSCALE_INT(v)  \
+		(((v) << 24) & BM_DCP_CSCYSCALE_INT)
+#define BP_DCP_CSCYSCALE_FRAC	12
+#define BM_DCP_CSCYSCALE_FRAC	0x00FFF000
+#define BF_DCP_CSCYSCALE_FRAC(v)  \
+		(((v) << 12) & BM_DCP_CSCYSCALE_FRAC)
+#define BP_DCP_CSCYSCALE_HEIGHT	0
+#define BM_DCP_CSCYSCALE_HEIGHT	0x00000FFF
+#define BF_DCP_CSCYSCALE_HEIGHT(v)  \
+		(((v) << 0) & BM_DCP_CSCYSCALE_HEIGHT)
+
+#define HW_DCP_DBGSELECT	(0x00000400)
+
+#define BP_DCP_DBGSELECT_RSVD	8
+#define BM_DCP_DBGSELECT_RSVD	0xFFFFFF00
+#define BF_DCP_DBGSELECT_RSVD(v) \
+		(((v) << 8) & BM_DCP_DBGSELECT_RSVD)
+#define BP_DCP_DBGSELECT_INDEX	0
+#define BM_DCP_DBGSELECT_INDEX	0x000000FF
+#define BF_DCP_DBGSELECT_INDEX(v)  \
+		(((v) << 0) & BM_DCP_DBGSELECT_INDEX)
+#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x01
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
+
+#define HW_DCP_DBGDATA	(0x00000410)
+
+#define BP_DCP_DBGDATA_DATA	0
+#define BM_DCP_DBGDATA_DATA	0xFFFFFFFF
+#define BF_DCP_DBGDATA_DATA(v)	(v)
+
+#define HW_DCP_PAGETABLE	(0x00000420)
+
+#define BP_DCP_PAGETABLE_BASE	2
+#define BM_DCP_PAGETABLE_BASE	0xFFFFFFFC
+#define BF_DCP_PAGETABLE_BASE(v) \
+		(((v) << 2) & BM_DCP_PAGETABLE_BASE)
+#define BM_DCP_PAGETABLE_FLUSH	0x00000002
+#define BM_DCP_PAGETABLE_ENABLE	0x00000001
+
+#define HW_DCP_VERSION	(0x00000430)
+
+#define BP_DCP_VERSION_MAJOR	24
+#define BM_DCP_VERSION_MAJOR	0xFF000000
+#define BF_DCP_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_DCP_VERSION_MAJOR)
+#define BP_DCP_VERSION_MINOR	16
+#define BM_DCP_VERSION_MINOR	0x00FF0000
+#define BF_DCP_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_DCP_VERSION_MINOR)
+#define BP_DCP_VERSION_STEP	0
+#define BM_DCP_VERSION_STEP	0x0000FFFF
+#define BF_DCP_VERSION_STEP(v)  \
+		(((v) << 0) & BM_DCP_VERSION_STEP)
+
+
+#endif
diff --git a/drivers/crypto/dcp_bootstream_ioctl.h b/drivers/crypto/dcp_bootstream_ioctl.h
new file mode 100644
index 000000000000..7c0c07d5a72d
--- /dev/null
+++ b/drivers/crypto/dcp_bootstream_ioctl.h
@@ -0,0 +1,32 @@
+/*
+ * Freescale DCP driver for bootstream update. Only handles the OTP KEY
+ * case and can only encrypt/decrypt.
+ *
+ * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
+ *
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef DCP_BOOTSTREAM_IOCTL_H
+#define DCP_BOOTSTREAM_IOCTL_H
+
+/* remember to have included the proper _IO definition
+ * file before hand.
+ * For user space it's <sys/ioctl.h>
+ */
+
+#define DBS_IOCTL_BASE   'd'
+
+#define DBS_ENC	_IOW(DBS_IOCTL_BASE, 0x00, uint8_t[16])
+#define DBS_DEC _IOW(DBS_IOCTL_BASE, 0x01, uint8_t[16])
+
+#endif
diff --git a/drivers/crypto/stmp3xxx_dcp.c b/drivers/crypto/stmp3xxx_dcp.c
new file mode 100644
index 000000000000..2fe02c71d308
--- /dev/null
+++ b/drivers/crypto/stmp3xxx_dcp.c
@@ -0,0 +1,1485 @@
+/*
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Based on geode-aes.c
+ * Copyright (C) 2004-2006, Advanced Micro Devices, Inc.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/crypto.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/aes.h>
+#include <crypto/sha.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <asm/cacheflush.h>
+
+#include "stmp3xxx_dcp.h"
+
+struct stmp3xxx_dcp {
+	struct device *dev;
+	spinlock_t lock;
+	struct mutex op_mutex[STMP3XXX_DCP_NUM_CHANNELS];
+	struct completion op_wait[STMP3XXX_DCP_NUM_CHANNELS];
+	int wait[STMP3XXX_DCP_NUM_CHANNELS];
+	int dcp_vmi_irq;
+	int dcp_irq;
+
+	/* Following buffers used in hashing to meet 64-byte len alignment */
+	char *buf1;
+	char *buf2;
+	dma_addr_t buf1_phys;
+	dma_addr_t buf2_phys;
+	struct stmp3xxx_dcp_hash_coherent_block *buf1_desc;
+	struct stmp3xxx_dcp_hash_coherent_block *buf2_desc;
+	struct stmp3xxx_dcp_hash_coherent_block *user_buf_desc;
+};
+
+/* cipher flags */
+#define STMP3XXX_DCP_ENC	0x0001
+#define STMP3XXX_DCP_DEC	0x0002
+#define STMP3XXX_DCP_ECB	0x0004
+#define STMP3XXX_DCP_CBC	0x0008
+#define STMP3XXX_DCP_CBC_INIT	0x0010
+#define STMP3XXX_DCP_OTPKEY	0x0020
+
+/* hash flags */
+#define STMP3XXX_DCP_INIT	0x0001
+#define STMP3XXX_DCP_UPDATE	0x0002
+#define STMP3XXX_DCP_FINAL	0x0004
+
+#define STMP3XXX_DCP_AES	0x1000
+#define STMP3XXX_DCP_SHA1	0x2000
+#define STMP3XXX_DCP_CRC32	0x3000
+#define STMP3XXX_DCP_COPY	0x4000
+#define STMP3XXX_DCP_FILL	0x5000
+#define STMP3XXX_DCP_MODE_MASK	0xf000
+
+struct stmp3xxx_dcp_op {
+
+	unsigned int flags;
+
+	void *src;
+	dma_addr_t src_phys;
+
+	void *dst;
+	dma_addr_t dst_phys;
+
+	int len;
+
+	/* the key contains the IV for block modes */
+	union {
+		struct {
+			u8 key[2 * AES_KEYSIZE_128]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t key_phys;
+			int keylen;
+		} cipher;
+		struct {
+			u8 digest[SHA1_DIGEST_SIZE]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t digest_phys;
+			int digestlen;
+			int init;
+		} hash;
+	};
+
+	union {
+		struct crypto_blkcipher *blk;
+		struct crypto_cipher *cip;
+		struct crypto_hash *hash;
+	} fallback;
+
+	struct stmp3xxx_dcp_hw_packet pkt
+		__attribute__ ((__aligned__(32)));
+};
+
+struct stmp3xxx_dcp_hash_coherent_block {
+	struct stmp3xxx_dcp_hw_packet pkt[1]
+		__attribute__ ((__aligned__(32)));
+	u8 digest[SHA1_DIGEST_SIZE]
+		__attribute__ ((__aligned__(32)));
+	unsigned int len;
+	dma_addr_t src_phys;
+	void *src;
+	void *dst;
+	dma_addr_t my_phys;
+	struct stmp3xxx_dcp_hash_coherent_block *next;
+};
+
+struct stmp3xxx_dcp_hash_op {
+
+	unsigned int flags;
+
+	/* the key contains the IV for block modes */
+	union {
+		struct {
+			u8 key[2 * AES_KEYSIZE_128]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t key_phys;
+			int keylen;
+		} cipher;
+		struct {
+			u8 digest[SHA1_DIGEST_SIZE]
+				__attribute__ ((__aligned__(32)));
+			dma_addr_t digest_phys;
+			int digestlen;
+			int init;
+		} hash;
+	};
+
+	u32 length;
+	struct stmp3xxx_dcp_hash_coherent_block *head_desc;
+	struct stmp3xxx_dcp_hash_coherent_block *tail_desc;
+};
+
+/* only one */
+static struct stmp3xxx_dcp *global_sdcp;
+
+static void dcp_perform_op(struct stmp3xxx_dcp_op *op)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct mutex *mutex;
+	struct stmp3xxx_dcp_hw_packet *pkt;
+	int chan;
+	u32 pkt1, pkt2;
+	unsigned long timeout;
+	dma_addr_t pkt_phys;
+	u32 stat;
+
+	pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE | BM_DCP_PACKET1_INTERRUPT;
+
+	switch (op->flags & STMP3XXX_DCP_MODE_MASK) {
+
+	case STMP3XXX_DCP_AES:
+
+		chan = CIPHER_CHAN;
+
+		/* key is at the payload */
+		pkt1 |= BM_DCP_PACKET1_ENABLE_CIPHER;
+		if ((op->flags & STMP3XXX_DCP_OTPKEY) == 0)
+			pkt1 |= BM_DCP_PACKET1_PAYLOAD_KEY;
+		if (op->flags & STMP3XXX_DCP_ENC)
+			pkt1 |= BM_DCP_PACKET1_CIPHER_ENCRYPT;
+		if (op->flags & STMP3XXX_DCP_CBC_INIT)
+			pkt1 |= BM_DCP_PACKET1_CIPHER_INIT;
+
+		pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) |
+		       BF(0, DCP_PACKET2_KEY_SELECT) |
+		       BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128,
+		       DCP_PACKET2_CIPHER_SELECT);
+
+		if (op->flags & STMP3XXX_DCP_ECB)
+			pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__ECB,
+				DCP_PACKET2_CIPHER_MODE);
+		else if (op->flags & STMP3XXX_DCP_CBC)
+			pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__CBC,
+				DCP_PACKET2_CIPHER_MODE);
+
+		break;
+
+	case STMP3XXX_DCP_SHA1:
+
+		chan = HASH_CHAN;
+
+		pkt1 |= BM_DCP_PACKET1_ENABLE_HASH;
+		if (op->flags & STMP3XXX_DCP_INIT)
+			pkt1 |= BM_DCP_PACKET1_HASH_INIT;
+		if (op->flags & STMP3XXX_DCP_FINAL) {
+			pkt1 |= BM_DCP_PACKET1_HASH_TERM;
+			BUG_ON(op->hash.digest == NULL);
+		}
+
+		pkt2 = BF(BV_DCP_PACKET2_HASH_SELECT__SHA1,
+			DCP_PACKET2_HASH_SELECT);
+		break;
+
+	default:
+		dev_err(sdcp->dev, "Unsupported mode\n");
+		return;
+	}
+
+	mutex = &sdcp->op_mutex[chan];
+	pkt = &op->pkt;
+
+	pkt->pNext = 0;
+	pkt->pkt1 = pkt1;
+	pkt->pkt2 = pkt2;
+	pkt->pSrc = (u32)op->src_phys;
+	pkt->pDst = (u32)op->dst_phys;
+	pkt->size = op->len;
+	pkt->pPayload = chan == CIPHER_CHAN ?
+		(u32)op->cipher.key_phys : (u32)op->hash.digest_phys;
+	pkt->stat = 0;
+
+	pkt_phys = dma_map_single(sdcp->dev, pkt, sizeof(*pkt),
+			DMA_BIDIRECTIONAL);
+	if (dma_mapping_error(sdcp->dev, pkt_phys)) {
+		dev_err(sdcp->dev, "Unable to map packet descriptor\n");
+		return;
+	}
+
+	/* submit the work */
+	mutex_lock(mutex);
+
+	__raw_writel(-1, REGS_DCP_BASE + HW_DCP_CHnSTAT_CLR(chan));
+
+	/* Load the work packet pointer and bump the channel semaphore */
+	__raw_writel((u32)pkt_phys, REGS_DCP_BASE + HW_DCP_CHnCMDPTR(chan));
+
+	/* XXX wake from interrupt instead of looping */
+	timeout = jiffies + msecs_to_jiffies(1000);
+
+	sdcp->wait[chan] = 0;
+	__raw_writel(BF(1, DCP_CHnSEMA_INCREMENT), REGS_DCP_BASE + HW_DCP_CHnSEMA(chan));
+	while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0)
+		cpu_relax();
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev, "Timeout while waiting STAT 0x%08x\n",
+				__raw_readl(REGS_DCP_BASE + HW_DCP_STAT));
+		goto out;
+	}
+
+	stat = __raw_readl(REGS_DCP_BASE + HW_DCP_CHnSTAT(chan));
+	if ((stat & 0xff) != 0)
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+				__raw_readl(REGS_DCP_BASE + HW_DCP_CHnSTAT(chan)) & 0xff);
+out:
+	mutex_unlock(mutex);
+
+	dma_unmap_single(sdcp->dev, pkt_phys, sizeof(*pkt), DMA_TO_DEVICE);
+}
+
+static int dcp_aes_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
+		unsigned int len)
+{
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+	unsigned int ret;
+
+	op->cipher.keylen = len;
+
+	if (len == AES_KEYSIZE_128) {
+		memcpy(op->cipher.key, key, len);
+		return 0;
+	}
+
+	if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
+		/* not supported at all */
+		tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+		return -EINVAL;
+	}
+
+	/*
+	 * The requested key size is not supported by HW, do a fallback
+	 */
+	op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+	op->fallback.blk->base.crt_flags |= (tfm->crt_flags &
+						CRYPTO_TFM_REQ_MASK);
+
+	ret = crypto_cipher_setkey(op->fallback.cip, key, len);
+	if (ret) {
+		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+		tfm->crt_flags |= (op->fallback.blk->base.crt_flags &
+					CRYPTO_TFM_RES_MASK);
+	}
+	return ret;
+}
+
+static void dcp_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) {
+		crypto_cipher_encrypt_one(op->fallback.cip, out, in);
+		return;
+	}
+
+	op->src = (void *) in;
+	op->dst = (void *) out;
+	op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_ENC | STMP3XXX_DCP_ECB;
+	op->len = AES_KEYSIZE_128;
+
+	/* map the data */
+	op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128,
+					DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+		dev_err(sdcp->dev, "Unable to map source\n");
+		return;
+	}
+
+	op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128,
+					DMA_FROM_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+		dev_err(sdcp->dev, "Unable to map dest\n");
+		goto err_unmap_src;
+	}
+
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		goto err_unmap_dst;
+	}
+
+	/* perform the operation */
+	dcp_perform_op(op);
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+err_unmap_dst:
+	dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE);
+err_unmap_src:
+	dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE);
+}
+
+static void dcp_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) {
+		crypto_cipher_decrypt_one(op->fallback.cip, out, in);
+		return;
+	}
+
+	op->src = (void *) in;
+	op->dst = (void *) out;
+	op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_DEC | STMP3XXX_DCP_ECB;
+	op->len = AES_KEYSIZE_128;
+
+	/* map the data */
+	op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128,
+					DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+		dev_err(sdcp->dev, "Unable to map source\n");
+		return;
+	}
+
+	op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128,
+					DMA_FROM_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+		dev_err(sdcp->dev, "Unable to map dest\n");
+		goto err_unmap_src;
+	}
+
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		goto err_unmap_dst;
+	}
+
+	/* perform the operation */
+	dcp_perform_op(op);
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+err_unmap_dst:
+	dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE);
+err_unmap_src:
+	dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE);
+}
+
+static int fallback_init_cip(struct crypto_tfm *tfm)
+{
+	const char *name = tfm->__crt_alg->cra_name;
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	op->fallback.cip = crypto_alloc_cipher(name, 0,
+				CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
+
+	if (IS_ERR(op->fallback.cip)) {
+		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+		return PTR_ERR(op->fallback.cip);
+	}
+
+	return 0;
+}
+
+static void fallback_exit_cip(struct crypto_tfm *tfm)
+{
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	crypto_free_cipher(op->fallback.cip);
+	op->fallback.cip = NULL;
+}
+
+static struct crypto_alg dcp_aes_alg = {
+	.cra_name		= "aes",
+	.cra_driver_name	= "dcp-aes",
+	.cra_priority		= 300,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_CIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_cip,
+	.cra_exit		= fallback_exit_cip,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct stmp3xxx_dcp_op),
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_alg.cra_list),
+	.cra_u			= {
+		.cipher	= {
+			.cia_min_keysize	= AES_MIN_KEY_SIZE,
+			.cia_max_keysize	= AES_MAX_KEY_SIZE,
+			.cia_setkey		= dcp_aes_setkey_cip,
+			.cia_encrypt		= dcp_aes_encrypt,
+			.cia_decrypt		= dcp_aes_decrypt
+		}
+	}
+};
+
+static int dcp_aes_setkey_blk(struct crypto_tfm *tfm, const u8 *key,
+		unsigned int len)
+{
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+	unsigned int ret;
+
+	op->cipher.keylen = len;
+
+	if (len == AES_KEYSIZE_128) {
+		memcpy(op->cipher.key, key, len);
+		return 0;
+	}
+
+	if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
+		/* not supported at all */
+		tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+		return -EINVAL;
+	}
+
+	/*
+	 * The requested key size is not supported by HW, do a fallback
+	 */
+	op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+	op->fallback.blk->base.crt_flags |= (tfm->crt_flags &
+						CRYPTO_TFM_REQ_MASK);
+
+	ret = crypto_blkcipher_setkey(op->fallback.blk, key, len);
+	if (ret) {
+		tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
+		tfm->crt_flags |= (op->fallback.blk->base.crt_flags &
+					CRYPTO_TFM_RES_MASK);
+	}
+	return ret;
+}
+
+static int fallback_blk_dec(struct blkcipher_desc *desc,
+		struct scatterlist *dst, struct scatterlist *src,
+		unsigned int nbytes)
+{
+	unsigned int ret;
+	struct crypto_blkcipher *tfm;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+
+	tfm = desc->tfm;
+	desc->tfm = op->fallback.blk;
+
+	ret = crypto_blkcipher_decrypt_iv(desc, dst, src, nbytes);
+
+	desc->tfm = tfm;
+	return ret;
+}
+
+static int fallback_blk_enc(struct blkcipher_desc *desc,
+		struct scatterlist *dst, struct scatterlist *src,
+		unsigned int nbytes)
+{
+	unsigned int ret;
+	struct crypto_blkcipher *tfm;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+
+	tfm = desc->tfm;
+	desc->tfm = op->fallback.blk;
+
+	ret = crypto_blkcipher_encrypt_iv(desc, dst, src, nbytes);
+
+	desc->tfm = tfm;
+	return ret;
+}
+
+static int fallback_init_blk(struct crypto_tfm *tfm)
+{
+	const char *name = tfm->__crt_alg->cra_name;
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	op->fallback.blk = crypto_alloc_blkcipher(name, 0,
+			CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
+
+	if (IS_ERR(op->fallback.blk)) {
+		printk(KERN_ERR "Error allocating fallback algo %s\n", name);
+		return PTR_ERR(op->fallback.blk);
+	}
+
+	return 0;
+}
+
+static void fallback_exit_blk(struct crypto_tfm *tfm)
+{
+	struct stmp3xxx_dcp_op *op = crypto_tfm_ctx(tfm);
+
+	crypto_free_blkcipher(op->fallback.blk);
+	op->fallback.blk = NULL;
+}
+
+static int
+dcp_aes_ecb_decrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_dec(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	/* key needs to be mapped only once */
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+				AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		return -ENOMEM;
+	}
+
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_DEC |
+				STMP3XXX_DCP_ECB;
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+						DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+						DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+						DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+					DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		err = blkcipher_walk_done(desc, &walk, nbytes);
+	}
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+				DMA_TO_DEVICE);
+
+	return err;
+}
+
+static int
+dcp_aes_ecb_encrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, ret;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_enc(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	/* key needs to be mapped only once */
+	op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+				AES_KEYSIZE_128, DMA_TO_DEVICE);
+	if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+		dev_err(sdcp->dev, "Unable to map key\n");
+		return -ENOMEM;
+	}
+
+	err = blkcipher_walk_virt(desc, &walk);
+
+	err = 0;
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_ENC |
+			    STMP3XXX_DCP_ECB;
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+				DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+				DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+				DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+				DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		ret =  blkcipher_walk_done(desc, &walk, nbytes);
+	}
+
+	dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128,
+			DMA_TO_DEVICE);
+
+	return err;
+}
+
+
+static struct crypto_alg dcp_aes_ecb_alg = {
+	.cra_name		= "ecb(aes)",
+	.cra_driver_name	= "dcp-ecb-aes",
+	.cra_priority		= 400,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_BLKCIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_blk,
+	.cra_exit		= fallback_exit_blk,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct stmp3xxx_dcp_op),
+	.cra_type		= &crypto_blkcipher_type,
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_ecb_alg.cra_list),
+	.cra_u			= {
+		.blkcipher 	= {
+			.min_keysize	= AES_MIN_KEY_SIZE,
+			.max_keysize	= AES_MAX_KEY_SIZE,
+			.setkey		= dcp_aes_setkey_blk,
+			.encrypt	= dcp_aes_ecb_encrypt,
+			.decrypt	= dcp_aes_ecb_decrypt
+		}
+	}
+};
+
+static int
+dcp_aes_cbc_decrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, blockno;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_dec(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	blockno = 0;
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_DEC |
+			    STMP3XXX_DCP_CBC;
+		if (blockno == 0) {
+			op->flags |= STMP3XXX_DCP_CBC_INIT;
+			memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv,
+				AES_KEYSIZE_128);
+		}
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* key (+iv) needs to be mapped only once */
+		op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+			dev_err(sdcp->dev, "Unable to map key\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+					DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+						DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+					DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		err = blkcipher_walk_done(desc, &walk, nbytes);
+
+		blockno++;
+	}
+
+	return err;
+}
+
+static int
+dcp_aes_cbc_encrypt(struct blkcipher_desc *desc,
+		  struct scatterlist *dst, struct scatterlist *src,
+		  unsigned int nbytes)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_op *op = crypto_blkcipher_ctx(desc->tfm);
+	struct blkcipher_walk walk;
+	int err, ret, blockno;
+
+	if (unlikely(op->cipher.keylen != AES_KEYSIZE_128))
+		return fallback_blk_enc(desc, dst, src, nbytes);
+
+	blkcipher_walk_init(&walk, dst, src, nbytes);
+
+	blockno = 0;
+
+	err = blkcipher_walk_virt(desc, &walk);
+	while (err == 0 && (nbytes = walk.nbytes) > 0) {
+		op->src = walk.src.virt.addr,
+		op->dst = walk.dst.virt.addr;
+		op->flags = STMP3XXX_DCP_AES | STMP3XXX_DCP_ENC |
+			    STMP3XXX_DCP_CBC;
+		if (blockno == 0) {
+			op->flags |= STMP3XXX_DCP_CBC_INIT;
+			memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv,
+				AES_KEYSIZE_128);
+		}
+		op->len = nbytes - (nbytes % AES_KEYSIZE_128);
+
+		/* key needs to be mapped only once */
+		op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) {
+			dev_err(sdcp->dev, "Unable to map key\n");
+			return -ENOMEM;
+		}
+
+		/* map the data */
+		op->src_phys = dma_map_single(sdcp->dev, op->src, op->len,
+				DMA_TO_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->src_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+				AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dev_err(sdcp->dev, "Unable to map source\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len,
+				DMA_FROM_DEVICE);
+		if (dma_mapping_error(sdcp->dev, op->dst_phys)) {
+			dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+					AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+			dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+					DMA_TO_DEVICE);
+			dev_err(sdcp->dev, "Unable to map dest\n");
+			err = -ENOMEM;
+			break;
+		}
+
+		/* perform! */
+		dcp_perform_op(op);
+
+		dma_unmap_single(sdcp->dev, op->cipher.key_phys,
+				AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL);
+		dma_unmap_single(sdcp->dev, op->dst_phys, op->len,
+				DMA_FROM_DEVICE);
+		dma_unmap_single(sdcp->dev, op->src_phys, op->len,
+				DMA_TO_DEVICE);
+
+		nbytes -= op->len;
+		ret =  blkcipher_walk_done(desc, &walk, nbytes);
+
+		blockno++;
+	}
+
+	return err;
+}
+
+static struct crypto_alg dcp_aes_cbc_alg = {
+	.cra_name		= "cbc(aes)",
+	.cra_driver_name	= "dcp-cbc-aes",
+	.cra_priority		= 400,
+	.cra_alignmask		= 15,
+	.cra_flags		= CRYPTO_ALG_TYPE_BLKCIPHER |
+				  CRYPTO_ALG_NEED_FALLBACK,
+	.cra_init		= fallback_init_blk,
+	.cra_exit		= fallback_exit_blk,
+	.cra_blocksize		= AES_KEYSIZE_128,
+	.cra_ctxsize		= sizeof(struct stmp3xxx_dcp_op),
+	.cra_type		= &crypto_blkcipher_type,
+	.cra_module		= THIS_MODULE,
+	.cra_list		= LIST_HEAD_INIT(dcp_aes_cbc_alg.cra_list),
+	.cra_u			= {
+		.blkcipher 	= {
+			.min_keysize	= AES_MIN_KEY_SIZE,
+			.max_keysize	= AES_MAX_KEY_SIZE,
+			.setkey		= dcp_aes_setkey_blk,
+			.encrypt	= dcp_aes_cbc_encrypt,
+			.decrypt	= dcp_aes_cbc_decrypt,
+			.ivsize		= AES_KEYSIZE_128,
+		}
+	}
+};
+
+static int dcp_perform_hash_op(
+	struct stmp3xxx_dcp_hash_coherent_block *input,
+	u32 num_desc, bool init, bool terminate)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	int chan;
+	struct stmp3xxx_dcp_hw_packet *pkt;
+	struct stmp3xxx_dcp_hash_coherent_block *hw;
+	unsigned long timeout;
+	u32 stat;
+	int descno, mapped;
+
+	chan = HASH_CHAN;
+
+	hw = input;
+	pkt = hw->pkt;
+
+	for (descno = 0; descno < num_desc; descno++) {
+
+		if (descno != 0) {
+
+			/* set next ptr and CHAIN bit in last packet */
+			pkt->pNext = hw->next->my_phys + offsetof(
+				struct stmp3xxx_dcp_hash_coherent_block,
+				pkt[0]);
+			pkt->pkt1 |= BM_DCP_PACKET1_CHAIN;
+
+			/* iterate to next descriptor */
+			hw = hw->next;
+			pkt = hw->pkt;
+		}
+
+		pkt->pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE |
+					BM_DCP_PACKET1_ENABLE_HASH;
+
+		if (init && descno == 0)
+			pkt->pkt1 |= BM_DCP_PACKET1_HASH_INIT;
+
+		pkt->pkt2 = BF(BV_DCP_PACKET2_HASH_SELECT__SHA1,
+				DCP_PACKET2_HASH_SELECT);
+
+		/* no need to flush buf1 or buf2, which are uncached */
+		if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2) {
+
+			/* we have to flush the cache for the buffer */
+			hw->src_phys = dma_map_single(sdcp->dev,
+				hw->src, hw->len, DMA_TO_DEVICE);
+
+			if (dma_mapping_error(sdcp->dev, hw->src_phys)) {
+				dev_err(sdcp->dev, "Unable to map source\n");
+
+				/* unmap any previous mapped buffers */
+				for (mapped = 0, hw = input; mapped < descno;
+					mapped++) {
+
+					if (mapped != 0)
+						hw = hw->next;
+					if (hw->src != sdcp->buf1 &&
+						hw->src != sdcp->buf2)
+						dma_unmap_single(sdcp->dev,
+							hw->src_phys, hw->len,
+							DMA_TO_DEVICE);
+				}
+
+				return -EFAULT;
+			}
+		}
+
+		pkt->pSrc = (u32)hw->src_phys;
+		pkt->pDst = 0;
+		pkt->size = hw->len;
+		pkt->pPayload = 0;
+		pkt->stat = 0;
+
+		/* set HASH_TERM bit on last buf if terminate was set */
+		if (terminate && (descno == (num_desc - 1))) {
+			pkt->pkt1 |= BM_DCP_PACKET1_HASH_TERM;
+
+			memset(input->digest, 0, sizeof(input->digest));
+
+			/* set payload ptr to the 1st buffer's digest */
+			pkt->pPayload = (u32)input->my_phys +
+				offsetof(
+				struct stmp3xxx_dcp_hash_coherent_block,
+				digest);
+		}
+	}
+
+	/* submit the work */
+
+	__raw_writel(-1, REGS_DCP_BASE + HW_DCP_CHnSTAT_CLR(chan));
+
+	mb();
+	/* Load the 1st descriptor's physical address */
+	__raw_writel((u32)input->my_phys +
+		offsetof(struct stmp3xxx_dcp_hash_coherent_block,
+		pkt[0]), REGS_DCP_BASE + HW_DCP_CHnCMDPTR(chan));
+
+	/* XXX wake from interrupt instead of looping */
+	timeout = jiffies + msecs_to_jiffies(1000);
+
+	/* write num_desc into sema register */
+	__raw_writel(BF(num_desc, DCP_CHnSEMA_INCREMENT),
+		REGS_DCP_BASE + HW_DCP_CHnSEMA(chan));
+
+	while (time_before(jiffies, timeout) &&
+		((__raw_readl(REGS_DCP_BASE +
+		HW_DCP_CHnSEMA(chan)) >> 16) & 0xff) != 0) {
+
+		cpu_relax();
+	}
+
+	if (!time_before(jiffies, timeout)) {
+		dev_err(sdcp->dev,
+			"Timeout while waiting STAT 0x%08x\n",
+			__raw_readl(REGS_DCP_BASE + HW_DCP_STAT));
+	}
+
+	stat = __raw_readl(REGS_DCP_BASE + HW_DCP_CHnSTAT(chan));
+	if ((stat & 0xff) != 0)
+		dev_err(sdcp->dev, "Channel stat error 0x%02x\n",
+				__raw_readl(REGS_DCP_BASE +
+				HW_DCP_CHnSTAT(chan)) & 0xff);
+
+	/* unmap all src buffers */
+	for (descno = 0, hw = input; descno < num_desc; descno++) {
+		if (descno != 0)
+			hw = hw->next;
+		if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2)
+			dma_unmap_single(sdcp->dev, hw->src_phys, hw->len,
+				DMA_TO_DEVICE);
+	}
+
+	return 0;
+
+}
+
+static int dcp_sha1_init(struct shash_desc *desc)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_hash_op *op = shash_desc_ctx(desc);
+	struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN];
+
+	mutex_lock(mutex);
+
+	op->length = 0;
+
+	/* reset the lengths and the pointers of buffer descriptors */
+	sdcp->buf1_desc->len = 0;
+	sdcp->buf1_desc->src = sdcp->buf1;
+	sdcp->buf2_desc->len = 0;
+	sdcp->buf2_desc->src = sdcp->buf2;
+	op->head_desc = sdcp->buf1_desc;
+	op->tail_desc = sdcp->buf2_desc;
+
+	return 0;
+}
+
+static int dcp_sha1_update(struct shash_desc *desc, const u8 *data,
+		      unsigned int length)
+{
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	struct stmp3xxx_dcp_hash_op *op = shash_desc_ctx(desc);
+	struct stmp3xxx_dcp_hash_coherent_block *temp;
+	u32 rem_bytes, bytes_borrowed;
+	int ret = 0;
+
+	sdcp->user_buf_desc->src = (void *)data;
+	sdcp->user_buf_desc->len = length;
+
+	op->tail_desc->len = 0;
+
+	/* check if any pending data from previous updates */
+	if (op->head_desc->len) {
+
+			/* borrow from this buffer to make it 64 bytes */
+			bytes_borrowed = min(64 - op->head_desc->len,
+					sdcp->user_buf_desc->len);
+
+			/* copy n bytes to head */
+			memcpy(op->head_desc->src + op->head_desc->len,
+				sdcp->user_buf_desc->src, bytes_borrowed);
+			op->head_desc->len += bytes_borrowed;
+
+			/* update current buffer's src and len */
+			sdcp->user_buf_desc->src += bytes_borrowed;
+			sdcp->user_buf_desc->len -= bytes_borrowed;
+	}
+
+	/* Is current buffer unaligned to 64 byte length?
+	  * Each buffer's length must be a multiple of 64 bytes for DCP
+	  */
+	rem_bytes = sdcp->user_buf_desc->len % 64;
+
+	/* if length is unaligned, copy remainder to tail */
+	if (rem_bytes) {
+
+		memcpy(op->tail_desc->src, (sdcp->user_buf_desc->src +
+			sdcp->user_buf_desc->len - rem_bytes),
+			rem_bytes);
+
+		/* update length of current buffer */
+		sdcp->user_buf_desc->len -= rem_bytes;
+
+		op->tail_desc->len = rem_bytes;
+	}
+
+	/* do not send to DCP if length is < 64 */
+	if ((op->head_desc->len + sdcp->user_buf_desc->len) >= 64) {
+		if (op->head_desc->len) {
+			op->head_desc->next = sdcp->user_buf_desc;
+
+			ret = dcp_perform_hash_op(op->head_desc,
+				sdcp->user_buf_desc->len ? 2 : 1,
+				op->length == 0, false);
+		} else {
+			ret = dcp_perform_hash_op(sdcp->user_buf_desc, 1,
+				op->length == 0, false);
+		}
+
+		op->length += op->head_desc->len + sdcp->user_buf_desc->len;
+		op->head_desc->len = 0;
+	}
+
+	/* if tail has bytes, make it the head for next time */
+	if (op->tail_desc->len) {
+		temp = op->head_desc;
+		op->head_desc = op->tail_desc;
+		op->tail_desc = temp;
+	}
+
+	return ret;
+}
+
+static int dcp_sha1_final(struct shash_desc *desc, u8 *out)
+{
+	struct stmp3xxx_dcp_hash_op *op = shash_desc_ctx(desc);
+	const uint8_t *digest;
+	struct stmp3xxx_dcp *sdcp = global_sdcp;
+	u32 i;
+	struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN];
+	int ret = 0;
+
+	/* Send the leftover bytes in head, which can be length 0,
+	  * but DCP still produces hash result in payload ptr.
+	  * Last data bytes need not be 64-byte multiple.
+	  */
+	ret = dcp_perform_hash_op(op->head_desc, 1, op->length == 0, true);
+
+	op->length += op->head_desc->len;
+
+	/* hardware reverses the digest (for some unexplicable reason) */
+	digest = op->head_desc->digest + SHA1_DIGEST_SIZE;
+	for (i = 0; i < SHA1_DIGEST_SIZE; i++)
+		*out++ = *--digest;
+
+	mutex_unlock(mutex);
+
+	return ret;
+}
+
+static struct shash_alg dcp_sha1_alg = {
+	.init			=	dcp_sha1_init,
+	.update			=	dcp_sha1_update,
+	.final			=	dcp_sha1_final,
+	.descsize		=	sizeof(struct stmp3xxx_dcp_hash_op),
+	.digestsize		=	SHA1_DIGEST_SIZE,
+	.base			=	{
+		.cra_name		=	"sha1",
+		.cra_driver_name	=	"sha1-dcp",
+		.cra_priority		=	300,
+		.cra_blocksize		=	SHA1_BLOCK_SIZE,
+		.cra_ctxsize		=
+			sizeof(struct stmp3xxx_dcp_hash_op),
+		.cra_module		=	THIS_MODULE,
+	}
+};
+
+static irqreturn_t dcp_common_irq(int irq, void *context)
+{
+	struct stmp3xxx_dcp *sdcp = context;
+	u32 msk;
+
+	/* check */
+	msk = __raw_readl(REGS_DCP_BASE + HW_DCP_STAT) & BF(0x0f, DCP_STAT_IRQ);
+	if (msk == 0)
+		return IRQ_NONE;
+
+	/* clear this channel */
+	__raw_writel(msk, REGS_DCP_BASE + HW_DCP_STAT_CLR);
+	if (msk & BF(0x01, DCP_STAT_IRQ))
+		sdcp->wait[0]++;
+	if (msk & BF(0x02, DCP_STAT_IRQ))
+		sdcp->wait[1]++;
+	if (msk & BF(0x04, DCP_STAT_IRQ))
+		sdcp->wait[2]++;
+	if (msk & BF(0x08, DCP_STAT_IRQ))
+		sdcp->wait[3]++;
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t dcp_vmi_irq(int irq, void *context)
+{
+	return dcp_common_irq(irq, context);
+}
+
+static irqreturn_t dcp_irq(int irq, void *context)
+{
+	return dcp_common_irq(irq, context);
+}
+
+static int stmp3xxx_dcp_probe(struct platform_device *pdev)
+{
+	struct stmp3xxx_dcp *sdcp = NULL;
+	struct resource *r;
+	int i, ret;
+	dma_addr_t hw_phys;
+
+	if (global_sdcp != NULL) {
+		dev_err(&pdev->dev, "Only one instance allowed\n");
+		ret = -ENODEV;
+		goto err;
+	}
+
+	/* allocate memory */
+	sdcp = kzalloc(sizeof(*sdcp), GFP_KERNEL);
+	if (sdcp == NULL) {
+		dev_err(&pdev->dev, "Failed to allocate structure\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	sdcp->dev = &pdev->dev;
+	spin_lock_init(&sdcp->lock);
+
+	for (i = 0; i < STMP3XXX_DCP_NUM_CHANNELS; i++) {
+		mutex_init(&sdcp->op_mutex[i]);
+		init_completion(&sdcp->op_wait[i]);
+	}
+
+	platform_set_drvdata(pdev, sdcp);
+
+	/* Soft reset and remove the clock gate */
+	__raw_writel(BM_DCP_CTRL_SFTRST, REGS_DCP_BASE + HW_DCP_CTRL_SET);
+
+	/* At 24Mhz, it takes no more than 4 clocks (160 ns) Maximum for
+	 * the part to reset, reading the register twice should
+	 * be sufficient to get 4 clks delay.
+	 */
+	__raw_readl(REGS_DCP_BASE + HW_DCP_CTRL);
+	__raw_readl(REGS_DCP_BASE + HW_DCP_CTRL);
+
+	__raw_writel(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE,
+		REGS_DCP_BASE + HW_DCP_CTRL_CLR);
+
+	/* Initialize control registers */
+	__raw_writel(STMP3XXX_DCP_CTRL_INIT, REGS_DCP_BASE + HW_DCP_CTRL);
+	__raw_writel(STMP3XXX_DCP_CHANNELCTRL_INIT, REGS_DCP_BASE + HW_DCP_CHANNELCTRL);
+
+	/* We do not enable context switching. Give the context
+	 * buffer pointer an illegal address so if context switching is
+	 * inadvertantly enabled, the dcp will return an error instead of
+	 * trashing good memory. The dcp dma cannot access rom, so any rom
+	 * address will do.
+	 */
+	__raw_writel(0xFFFF0000, REGS_DCP_BASE + HW_DCP_CONTEXT);
+
+	for (i = 0; i < STMP3XXX_DCP_NUM_CHANNELS; i++)
+		__raw_writel(-1, REGS_DCP_BASE + HW_DCP_CHnSTAT_CLR(i));
+	__raw_writel(-1, REGS_DCP_BASE + HW_DCP_STAT_CLR);
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IRQ resource (0)\n");
+		ret = -EIO;
+		goto err_kfree;
+	}
+	sdcp->dcp_vmi_irq = r->start;
+	ret = request_irq(sdcp->dcp_vmi_irq, dcp_vmi_irq, 0, "stmp3xxx-dcp",
+				sdcp);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "can't request_irq (0)\n");
+		goto err_kfree;
+	}
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IRQ resource (1)\n");
+		ret = -EIO;
+		goto err_free_irq0;
+	}
+	sdcp->dcp_irq = r->start;
+	ret = request_irq(sdcp->dcp_irq, dcp_irq, 0, "stmp3xxx-dcp", sdcp);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "can't request_irq (1)\n");
+		goto err_free_irq0;
+	}
+
+	global_sdcp = sdcp;
+
+	ret = crypto_register_alg(&dcp_aes_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes crypto\n");
+		goto err_kfree;
+	}
+
+	ret = crypto_register_alg(&dcp_aes_ecb_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes ecb crypto\n");
+		goto err_unregister_aes;
+	}
+
+	ret = crypto_register_alg(&dcp_aes_cbc_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register aes cbc crypto\n");
+		goto err_unregister_aes_ecb;
+	}
+
+	/* Allocate the descriptor to be used for user buffer
+	  * passed in by the "update" function from Crypto API
+	  */
+	sdcp->user_buf_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct stmp3xxx_dcp_hash_coherent_block),  &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->user_buf_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->user_buf_desc->my_phys = hw_phys;
+
+	/* Allocate 2 buffers (head & tail) & its descriptors to deal with
+	  * buffer lengths that are not 64 byte aligned, except for the
+	  * last one.
+	  */
+	sdcp->buf1 = dma_alloc_coherent(sdcp->dev,
+		64, &sdcp->buf1_phys, GFP_KERNEL);
+	if (sdcp->buf1 == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf2 = dma_alloc_coherent(sdcp->dev,
+		64,  &sdcp->buf2_phys, GFP_KERNEL);
+	if (sdcp->buf2 == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf1_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct stmp3xxx_dcp_hash_coherent_block), &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->buf1_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf1_desc->my_phys = hw_phys;
+	sdcp->buf1_desc->src = (void *)sdcp->buf1;
+	sdcp->buf1_desc->src_phys = sdcp->buf1_phys;
+
+	sdcp->buf2_desc = dma_alloc_coherent(sdcp->dev,
+		sizeof(struct stmp3xxx_dcp_hash_coherent_block), &hw_phys,
+		GFP_KERNEL);
+	if (sdcp->buf2_desc == NULL) {
+		printk(KERN_ERR "Error allocating coherent block\n");
+		ret = -ENOMEM;
+		goto err_unregister_aes_cbc;
+	}
+
+	sdcp->buf2_desc->my_phys = hw_phys;
+	sdcp->buf2_desc->src = (void *)sdcp->buf2;
+	sdcp->buf2_desc->src_phys = sdcp->buf2_phys;
+
+
+	ret = crypto_register_shash(&dcp_sha1_alg);
+	if (ret != 0)  {
+		dev_err(&pdev->dev, "Failed to register sha1 hash\n");
+		goto err_unregister_aes_cbc;
+	}
+
+	dev_notice(&pdev->dev, "DCP crypto enabled.!\n");
+	return 0;
+
+	crypto_unregister_shash(&dcp_sha1_alg);
+err_unregister_aes_cbc:
+	crypto_unregister_alg(&dcp_aes_cbc_alg);
+err_unregister_aes_ecb:
+	crypto_unregister_alg(&dcp_aes_ecb_alg);
+err_unregister_aes:
+	crypto_unregister_alg(&dcp_aes_alg);
+err_free_irq0:
+	free_irq(sdcp->dcp_vmi_irq, sdcp);
+err_kfree:
+	kfree(sdcp);
+err:
+
+	return ret;
+}
+
+static int stmp3xxx_dcp_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_dcp *sdcp;
+
+	sdcp = platform_get_drvdata(pdev);
+	platform_set_drvdata(pdev, NULL);
+
+	free_irq(sdcp->dcp_irq, sdcp);
+	free_irq(sdcp->dcp_vmi_irq, sdcp);
+
+	/* if head and tail buffers were allocated, free them */
+	if (sdcp->buf1) {
+		dma_free_coherent(sdcp->dev, 64, sdcp->buf1, sdcp->buf1_phys);
+		dma_free_coherent(sdcp->dev, 64, sdcp->buf2, sdcp->buf2_phys);
+
+		dma_free_coherent(sdcp->dev,
+				sizeof(struct stmp3xxx_dcp_hash_coherent_block),
+				sdcp->buf1_desc, sdcp->buf1_desc->my_phys);
+
+		dma_free_coherent(sdcp->dev,
+				sizeof(struct stmp3xxx_dcp_hash_coherent_block),
+				sdcp->buf2_desc, sdcp->buf2_desc->my_phys);
+
+		dma_free_coherent(sdcp->dev,
+			sizeof(struct stmp3xxx_dcp_hash_coherent_block),
+			sdcp->user_buf_desc, sdcp->user_buf_desc->my_phys);
+	}
+
+	crypto_unregister_shash(&dcp_sha1_alg);
+
+	crypto_unregister_alg(&dcp_aes_cbc_alg);
+	crypto_unregister_alg(&dcp_aes_ecb_alg);
+	crypto_unregister_alg(&dcp_aes_alg);
+	kfree(sdcp);
+	global_sdcp = NULL;
+
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int stmp3xxx_dcp_suspend(struct platform_device *pdev,
+		pm_message_t state)
+{
+	return 0;
+}
+
+static int stmp3xxx_dcp_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define stmp3xxx_dcp_suspend	NULL
+#define	stmp3xxx_dcp_resume	NULL
+#endif
+
+static struct platform_driver stmp3xxx_dcp_driver = {
+	.probe		= stmp3xxx_dcp_probe,
+	.remove		= stmp3xxx_dcp_remove,
+	.suspend	= stmp3xxx_dcp_suspend,
+	.resume		= stmp3xxx_dcp_resume,
+	.driver		= {
+		.name   = "stmp3xxx-dcp",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init
+stmp3xxx_dcp_init(void)
+{
+	return platform_driver_register(&stmp3xxx_dcp_driver);
+}
+
+static void __exit
+stmp3xxx_dcp_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_dcp_driver);
+}
+
+MODULE_AUTHOR("Pantelis Antoniou <pantelis@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP3XXX DCP Crypto Driver");
+MODULE_LICENSE("GPL");
+
+module_init(stmp3xxx_dcp_init);
+module_exit(stmp3xxx_dcp_exit);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 81e1020fb514..27e06ebc2a59 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -89,6 +89,15 @@ config MX3_IPU_IRQS
 	  To avoid bloating the irq_desc[] array we allocate a sufficient
 	  number of IRQ slots and map them dynamically to specific sources.
 
+config MXC_PXP
+    bool "MXC PxP support"
+    select DMA_ENGINE
+
+config MXC_PXP_CLIENT_DEVICE
+    bool "MXC PxP Client Device"
+    default y
+    depends on MXC_PXP
+
 config TXX9_DMAC
 	tristate "Toshiba TXx9 SoC DMA support"
 	depends on MACH_TX49XX || MACH_TX39XX
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 40e1e0083571..72c212ac6b79 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
+obj-$(CONFIG_MXC_PXP) += pxp/
 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile
new file mode 100644
index 000000000000..88e51a7fb1e2
--- /dev/null
+++ b/drivers/dma/pxp/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MXC_PXP) += pxp_dma.o
+obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o
diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c
new file mode 100644
index 000000000000..74176d3da9d3
--- /dev/null
+++ b/drivers/dma/pxp/pxp_device.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#include <linux/interrupt.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+
+#include <asm/atomic.h>
+
+static atomic_t open_count = ATOMIC_INIT(0);
+
+static DEFINE_SPINLOCK(pxp_mem_lock);
+static DEFINE_SPINLOCK(pxp_chan_lock);
+static LIST_HEAD(head);
+static LIST_HEAD(list);
+static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL];
+
+struct pxp_chan_handle {
+	int chan_id;
+	int hist_status;
+};
+
+/* To track the allocated memory buffer */
+struct memalloc_record {
+	struct list_head list;
+	struct pxp_mem_desc mem;
+};
+
+struct pxp_chan_info {
+	int chan_id;
+	struct dma_chan *dma_chan;
+	struct list_head list;
+};
+
+static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem)
+{
+	mem->cpu_addr = (unsigned long)
+	    dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
+			       (dma_addr_t *) (&mem->phys_addr),
+			       GFP_DMA | GFP_KERNEL);
+	pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr);
+	if ((void *)(mem->cpu_addr) == NULL) {
+		printk(KERN_ERR "Physical memory allocation error!\n");
+		return -1;
+	}
+	return 0;
+}
+
+static void pxp_free_dma_buffer(struct pxp_mem_desc *mem)
+{
+	if (mem->cpu_addr != 0) {
+		dma_free_coherent(0, PAGE_ALIGN(mem->size),
+				  (void *)mem->cpu_addr, mem->phys_addr);
+	}
+}
+
+static int pxp_free_buffers(void)
+{
+	struct memalloc_record *rec, *n;
+	struct pxp_mem_desc mem;
+
+	list_for_each_entry_safe(rec, n, &head, list) {
+		mem = rec->mem;
+		if (mem.cpu_addr != 0) {
+			pxp_free_dma_buffer(&mem);
+			pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr);
+			/* delete from list */
+			list_del(&rec->list);
+			kfree(rec);
+		}
+	}
+
+	return 0;
+}
+
+/* Callback function triggered after PxP receives an EOF interrupt */
+static void pxp_dma_done(void *arg)
+{
+	struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
+	struct dma_chan *chan = tx_desc->txd.chan;
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	int chan_id = pxp_chan->dma_chan.chan_id;
+
+	pr_debug("DMA Done ISR, chan_id %d\n", chan_id);
+
+	irq_info[chan_id].irq_pending++;
+	irq_info[chan_id].hist_status = tx_desc->hist_status;
+
+	wake_up_interruptible(&(irq_info[chan_id].waitq));
+}
+
+static int pxp_ioc_config_chan(unsigned long arg)
+{
+	struct scatterlist sg[3];
+	struct pxp_tx_desc *desc;
+	struct dma_async_tx_descriptor *txd;
+	struct pxp_chan_info *info;
+	struct pxp_config_data pxp_conf;
+	dma_cookie_t cookie;
+	int chan_id;
+	int i, length, ret;
+
+	ret = copy_from_user(&pxp_conf,
+			     (struct pxp_config_data *)arg,
+			     sizeof(struct pxp_config_data));
+	if (ret)
+		return -EFAULT;
+
+	chan_id = pxp_conf.chan_id;
+	if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+		return -ENODEV;
+
+	init_waitqueue_head(&(irq_info[chan_id].waitq));
+
+	/* find the channel */
+	spin_lock(&pxp_chan_lock);
+	list_for_each_entry(info, &list, list) {
+		if (info->dma_chan->chan_id == chan_id)
+			break;
+	}
+	spin_unlock(&pxp_chan_lock);
+
+	sg_init_table(sg, 3);
+
+	txd =
+	    info->dma_chan->device->device_prep_slave_sg(info->dma_chan,
+							 sg, 3,
+							 DMA_TO_DEVICE,
+							 DMA_PREP_INTERRUPT);
+	if (!txd) {
+		pr_err("Error preparing a DMA transaction descriptor.\n");
+		return -EIO;
+	}
+
+	txd->callback_param = txd;
+	txd->callback = pxp_dma_done;
+
+	desc = to_tx_desc(txd);
+
+	length = desc->len;
+	for (i = 0; i < length; i++) {
+		if (i == 0) {	/* S0 */
+			memcpy(&desc->proc_data,
+			       &pxp_conf.proc_data,
+			       sizeof(struct pxp_proc_data));
+			memcpy(&desc->layer_param.s0_param,
+			       &pxp_conf.s0_param,
+			       sizeof(struct pxp_layer_param));
+		} else if (i == 1) {	/* Output */
+			memcpy(&desc->layer_param.out_param,
+			       &pxp_conf.out_param,
+			       sizeof(struct pxp_layer_param));
+		} else {
+			/* OverLay */
+			memcpy(&desc->layer_param.ol_param,
+			       &pxp_conf.ol_param,
+			       sizeof(struct pxp_layer_param));
+		}
+
+		desc = desc->next;
+	}
+
+	cookie = txd->tx_submit(txd);
+	if (cookie < 0) {
+		pr_err("Error tx_submit\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int pxp_device_open(struct inode *inode, struct file *filp)
+{
+	atomic_inc(&open_count);
+
+	return 0;
+}
+
+static int pxp_device_release(struct inode *inode, struct file *filp)
+{
+	if (atomic_dec_and_test(&open_count))
+		pxp_free_buffers();
+
+	return 0;
+}
+
+static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct memalloc_record *rec, *n;
+	int request_size, found;
+
+	request_size = vma->vm_end - vma->vm_start;
+	found = 0;
+
+	pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n",
+		 (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff),
+		 request_size);
+
+	spin_lock(&pxp_mem_lock);
+	list_for_each_entry_safe(rec, n, &head, list) {
+		if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) &&
+			(rec->mem.size <= request_size)) {
+			found = 1;
+			break;
+		}
+	}
+	spin_unlock(&pxp_mem_lock);
+
+	if (found == 0)
+		return -ENOMEM;
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			       request_size, vma->vm_page_prot) ? -EAGAIN : 0;
+}
+
+static int pxp_device_ioctl(struct inode *inode, struct file *filp,
+			    unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case PXP_IOC_GET_CHAN:
+		{
+			struct pxp_chan_info *info;
+			dma_cap_mask_t mask;
+
+			pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__);
+			info = kzalloc(sizeof(*info), GFP_KERNEL);
+			if (!info) {
+				pr_err("%d: alloc err\n", __LINE__);
+				return -ENOMEM;
+			}
+
+			dma_cap_zero(mask);
+			dma_cap_set(DMA_SLAVE, mask);
+			dma_cap_set(DMA_PRIVATE, mask);
+			info->dma_chan = dma_request_channel(mask, NULL, NULL);
+			if (!info->dma_chan) {
+				pr_err("Unsccessfully received channel!\n");
+				kfree(info);
+				return -EBUSY;
+			}
+			pr_debug("Successfully received channel."
+				 "chan_id %d\n", info->dma_chan->chan_id);
+
+			spin_lock(&pxp_chan_lock);
+			list_add_tail(&info->list, &list);
+			spin_unlock(&pxp_chan_lock);
+
+			if (put_user
+			    (info->dma_chan->chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			break;
+		}
+	case PXP_IOC_PUT_CHAN:
+		{
+			int chan_id;
+			struct pxp_chan_info *info;
+
+			if (get_user(chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+				return -ENODEV;
+
+			spin_lock(&pxp_chan_lock);
+			list_for_each_entry(info, &list, list) {
+				if (info->dma_chan->chan_id == chan_id)
+					break;
+			}
+			spin_unlock(&pxp_chan_lock);
+
+			pr_debug("%d release chan_id %d\n", __LINE__,
+				 info->dma_chan->chan_id);
+			/* REVISIT */
+			dma_release_channel(info->dma_chan);
+			spin_lock(&pxp_chan_lock);
+			list_del_init(&info->list);
+			spin_unlock(&pxp_chan_lock);
+			kfree(info);
+
+			break;
+		}
+	case PXP_IOC_CONFIG_CHAN:
+		{
+
+			int ret;
+
+			ret = pxp_ioc_config_chan(arg);
+			if (ret)
+				return ret;
+
+			break;
+		}
+	case PXP_IOC_START_CHAN:
+		{
+			struct pxp_chan_info *info;
+			int chan_id;
+
+			if (get_user(chan_id, (u32 __user *) arg))
+				return -EFAULT;
+
+			/* find the channel */
+			spin_lock(&pxp_chan_lock);
+			list_for_each_entry(info, &list, list) {
+				if (info->dma_chan->chan_id == chan_id)
+					break;
+			}
+			spin_unlock(&pxp_chan_lock);
+
+			dma_async_issue_pending(info->dma_chan);
+
+			break;
+		}
+	case PXP_IOC_GET_PHYMEM:
+		{
+			struct memalloc_record *rec;
+
+			rec = kzalloc(sizeof(*rec), GFP_KERNEL);
+			if (!rec)
+				return -ENOMEM;
+
+			ret = copy_from_user(&(rec->mem),
+					     (struct pxp_mem_desc *)arg,
+					     sizeof(struct pxp_mem_desc));
+			if (ret) {
+				kfree(rec);
+				return -EFAULT;
+			}
+
+			pr_debug("[ALLOC] mem alloc size = 0x%x\n",
+				 rec->mem.size);
+
+			ret = pxp_alloc_dma_buffer(&(rec->mem));
+			if (ret == -1) {
+				kfree(rec);
+				printk(KERN_ERR
+				       "Physical memory allocation error!\n");
+				break;
+			}
+			ret = copy_to_user((void __user *)arg, &(rec->mem),
+					   sizeof(struct pxp_mem_desc));
+			if (ret) {
+				kfree(rec);
+				ret = -EFAULT;
+				break;
+			}
+
+			spin_lock(&pxp_mem_lock);
+			list_add(&rec->list, &head);
+			spin_unlock(&pxp_mem_lock);
+
+			break;
+		}
+	case PXP_IOC_PUT_PHYMEM:
+		{
+			struct memalloc_record *rec, *n;
+			struct pxp_mem_desc pxp_mem;
+
+			ret = copy_from_user(&pxp_mem,
+					     (struct pxp_mem_desc *)arg,
+					     sizeof(struct pxp_mem_desc));
+			if (ret)
+				return -EACCES;
+
+			pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
+				 pxp_mem.cpu_addr);
+			if ((void *)pxp_mem.cpu_addr != NULL)
+				pxp_free_dma_buffer(&pxp_mem);
+
+			spin_lock(&pxp_mem_lock);
+			list_for_each_entry_safe(rec, n, &head, list) {
+				if (rec->mem.cpu_addr == pxp_mem.cpu_addr) {
+					/* delete from list */
+					list_del(&rec->list);
+					kfree(rec);
+					break;
+				}
+			}
+			spin_unlock(&pxp_mem_lock);
+
+			break;
+		}
+	case PXP_IOC_WAIT4CMPLT:
+		{
+			struct pxp_chan_handle chan_handle;
+			int ret, chan_id;
+
+			ret = copy_from_user(&chan_handle,
+					     (struct pxp_chan_handle *)arg,
+					     sizeof(struct pxp_chan_handle));
+			if (ret)
+				return -EFAULT;
+
+			chan_id = chan_handle.chan_id;
+			if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
+				return -ENODEV;
+
+			if (!wait_event_interruptible_timeout
+			    (irq_info[chan_id].waitq,
+			     (irq_info[chan_id].irq_pending != 0), 2 * HZ)) {
+				pr_warning("pxp blocking: timeout.\n");
+				return -ETIME;
+			} else if (signal_pending(current)) {
+				printk(KERN_WARNING
+				       "pxp interrupt received.\n");
+				return -ERESTARTSYS;
+			} else
+				irq_info[chan_id].irq_pending--;
+
+			chan_handle.hist_status = irq_info[chan_id].hist_status;
+			ret = copy_to_user((struct pxp_chan_handle *)arg,
+					   &chan_handle,
+					   sizeof(struct pxp_chan_handle));
+			if (ret)
+				return -EFAULT;
+			break;
+		}
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static const struct file_operations pxp_device_fops = {
+	.open = pxp_device_open,
+	.release = pxp_device_release,
+	.ioctl = pxp_device_ioctl,
+	.mmap = pxp_device_mmap,
+};
+
+static struct miscdevice pxp_device_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "pxp_device",
+	.fops = &pxp_device_fops,
+};
+
+static int __devinit pxp_device_probe(struct platform_device *pdev)
+{
+	int ret;
+
+	/* PxP DMA interface */
+	dmaengine_get();
+
+	ret = misc_register(&pxp_device_miscdev);
+	if (ret)
+		return ret;
+
+	pr_debug("PxP_Device Probe Successfully\n");
+	return 0;
+}
+
+static int __devexit pxp_device_remove(struct platform_device *pdev)
+{
+	misc_deregister(&pxp_device_miscdev);
+
+	dmaengine_put();
+
+	return 0;
+}
+
+static struct platform_driver pxp_client_driver = {
+	.probe = pxp_device_probe,
+	.remove = __exit_p(pxp_device_remove),
+	.driver = {
+		   .name = "pxp-device",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init pxp_device_init(void)
+{
+	return platform_driver_register(&pxp_client_driver);
+}
+
+static void __exit pxp_device_exit(void)
+{
+	platform_driver_unregister(&pxp_client_driver);
+}
+
+module_init(pxp_device_init);
+module_exit(pxp_device_exit);
+
+MODULE_DESCRIPTION("i.MX PxP client driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pxp/pxp_dma.c b/drivers/dma/pxp/pxp_dma.c
new file mode 100644
index 000000000000..10e7bab8feb6
--- /dev/null
+++ b/drivers/dma/pxp/pxp_dma.c
@@ -0,0 +1,1377 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X PxP driver
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+#include <linux/clk.h>
+
+#include "regs-pxp.h"
+
+#define	PXP_DOWNSCALE_THRESHOLD		0x4000
+
+static LIST_HEAD(head);
+
+struct pxp_dma {
+	struct dma_device dma;
+};
+
+struct pxps {
+	struct platform_device *pdev;
+	struct clk *clk;
+	void __iomem *base;
+	int irq;		/* PXP IRQ to the CPU */
+
+	spinlock_t lock;
+	struct mutex mutex;
+
+	struct device *dev;
+	struct pxp_dma pxp_dma;
+	struct pxp_channel channel[NR_PXP_VIRT_CHANNEL];
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	wait_queue_head_t done;
+
+	/* describes most recent processing configuration */
+	struct pxp_config_data pxp_conf_state;
+};
+
+#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma)
+#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
+#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
+#define to_pxp(id) container_of(id, struct pxps, pxp_dma)
+
+#define PXP_DEF_BUFS	2
+#define PXP_MIN_PIX	8
+
+#define PXP_WAITCON	((__raw_readl(pxp->base + HW_PXP_STAT) & \
+				BM_PXP_STAT_IRQ) != BM_PXP_STAT_IRQ)
+
+static uint32_t pxp_s0_formats[] = {
+	PXP_PIX_FMT_RGB24,
+	PXP_PIX_FMT_RGB565,
+	PXP_PIX_FMT_RGB555,
+	PXP_PIX_FMT_YUV420P,
+	PXP_PIX_FMT_YUV422P,
+};
+
+/*
+ * PXP common functions
+ */
+static void dump_pxp_reg(struct pxps *pxp)
+{
+	dev_err(pxp->dev, "PXP_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CTRL));
+	dev_err(pxp->dev, "PXP_STAT 0x%x",
+		__raw_readl(pxp->base + HW_PXP_STAT));
+	dev_err(pxp->dev, "PXP_OUTBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTBUF));
+	dev_err(pxp->dev, "PXP_OUTBUF2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTBUF2));
+	dev_err(pxp->dev, "PXP_OUTSIZE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OUTSIZE));
+	dev_err(pxp->dev, "PXP_S0BUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0BUF));
+	dev_err(pxp->dev, "PXP_S0UBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0UBUF));
+	dev_err(pxp->dev, "PXP_S0VBUF 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0VBUF));
+	dev_err(pxp->dev, "PXP_S0PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0PARAM));
+	dev_err(pxp->dev, "PXP_S0BACKGROUND 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0BACKGROUND));
+	dev_err(pxp->dev, "PXP_S0CROP 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0CROP));
+	dev_err(pxp->dev, "PXP_S0SCALE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_S0SCALE));
+	dev_err(pxp->dev, "PXP_OLn 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLn(0)));
+	dev_err(pxp->dev, "PXP_OLnSIZE 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLnSIZE(0)));
+	dev_err(pxp->dev, "PXP_OLnPARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_OLnPARAM(0)));
+	dev_err(pxp->dev, "PXP_CSCCOEF0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSCCOEF0));
+	dev_err(pxp->dev, "PXP_CSC2CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2CTRL));
+	dev_err(pxp->dev, "PXP_CSC2COEF0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF0));
+	dev_err(pxp->dev, "PXP_CSC2COEF1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF1));
+	dev_err(pxp->dev, "PXP_CSC2COEF2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF2));
+	dev_err(pxp->dev, "PXP_CSC2COEF3 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF3));
+	dev_err(pxp->dev, "PXP_CSC2COEF4 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF4));
+	dev_err(pxp->dev, "PXP_CSC2COEF5 0x%x",
+		__raw_readl(pxp->base + HW_PXP_CSC2COEF5));
+	dev_err(pxp->dev, "PXP_LUT_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_LUT_CTRL));
+	dev_err(pxp->dev, "PXP_LUT 0x%x", __raw_readl(pxp->base + HW_PXP_LUT));
+	dev_err(pxp->dev, "PXP_HIST_CTRL 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST_CTRL));
+	dev_err(pxp->dev, "PXP_HIST2_PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST2_PARAM));
+	dev_err(pxp->dev, "PXP_HIST4_PARAM 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST4_PARAM));
+	dev_err(pxp->dev, "PXP_HIST8_PARAM0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST8_PARAM0));
+	dev_err(pxp->dev, "PXP_HIST8_PARAM1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST8_PARAM1));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM0 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM0));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM1 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM1));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM2 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM2));
+	dev_err(pxp->dev, "PXP_HIST16_PARAM3 0x%x",
+		__raw_readl(pxp->base + HW_PXP_HIST16_PARAM3));
+}
+
+static bool is_yuv(pix_fmt)
+{
+	if ((pix_fmt == PXP_PIX_FMT_YUYV) |
+	    (pix_fmt == PXP_PIX_FMT_UYVY) |
+	    (pix_fmt == PXP_PIX_FMT_Y41P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV444) |
+	    (pix_fmt == PXP_PIX_FMT_NV12) |
+	    (pix_fmt == PXP_PIX_FMT_GREY) |
+	    (pix_fmt == PXP_PIX_FMT_YVU410P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV410P) |
+	    (pix_fmt == PXP_PIX_FMT_YVU420P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV420P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV420P2) |
+	    (pix_fmt == PXP_PIX_FMT_YVU422P) |
+	    (pix_fmt == PXP_PIX_FMT_YUV422P)) {
+		return true;
+	} else {
+		return false;
+	}
+}
+
+static void pxp_set_ctrl(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 ctrl;
+	u32 fmt_ctrl;
+
+	/* Configure S0 input format */
+	switch (pxp_conf->s0_param.pixel_fmt) {
+	case PXP_PIX_FMT_RGB24:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB888;
+		break;
+	case PXP_PIX_FMT_RGB565:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB565;
+		break;
+	case PXP_PIX_FMT_RGB555:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB555;
+		break;
+	case PXP_PIX_FMT_YUV420P:
+	case PXP_PIX_FMT_GREY:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420;
+		break;
+	case PXP_PIX_FMT_YUV422P:
+		fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV422;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+	ctrl = BF_PXP_CTRL_S0_FORMAT(fmt_ctrl);
+
+	/* Configure output format based on out_channel format */
+	switch (pxp_conf->out_param.pixel_fmt) {
+	case PXP_PIX_FMT_RGB24:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB888;
+		break;
+	case PXP_PIX_FMT_RGB565:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB565;
+		break;
+	case PXP_PIX_FMT_RGB555:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB555;
+		break;
+	case PXP_PIX_FMT_YUV420P:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420;
+		break;
+	case PXP_PIX_FMT_YUV422P:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422;
+		break;
+	case PXP_PIX_FMT_GREY:
+		fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+	ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(fmt_ctrl);
+
+	ctrl |= BM_PXP_CTRL_CROP;
+
+	if (proc_data->scaling)
+		ctrl |= BM_PXP_CTRL_SCALE;
+	if (proc_data->vflip)
+		ctrl |= BM_PXP_CTRL_VFLIP;
+	if (proc_data->hflip)
+		ctrl |= BM_PXP_CTRL_HFLIP;
+	if (proc_data->rotate)
+		ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90);
+
+	__raw_writel(ctrl, pxp->base + HW_PXP_CTRL);
+}
+
+static int pxp_start(struct pxps *pxp)
+{
+	__raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET);
+	__raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET);
+
+	return 0;
+}
+
+static void pxp_set_outbuf(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *out_params = &pxp_conf->out_param;
+
+	__raw_writel(out_params->paddr, pxp->base + HW_PXP_OUTBUF);
+
+	__raw_writel(BF_PXP_OUTSIZE_WIDTH(out_params->width) |
+		     BF_PXP_OUTSIZE_HEIGHT(out_params->height),
+		     pxp->base + HW_PXP_OUTSIZE);
+}
+
+static void pxp_set_s0colorkey(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (s0_params->color_key == -1) {
+		/* disable color key */
+		__raw_writel(0xFFFFFF, pxp->base + HW_PXP_S0COLORKEYLOW);
+		__raw_writel(0, pxp->base + HW_PXP_S0COLORKEYHIGH);
+	} else {
+		__raw_writel(s0_params->color_key,
+			     pxp->base + HW_PXP_S0COLORKEYLOW);
+		__raw_writel(s0_params->color_key,
+			     pxp->base + HW_PXP_S0COLORKEYHIGH);
+	}
+}
+
+static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no];
+
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) {
+		__raw_writel(ol_params->color_key,
+			     pxp->base + HW_PXP_OLCOLORKEYLOW);
+		__raw_writel(ol_params->color_key,
+			     pxp->base + HW_PXP_OLCOLORKEYHIGH);
+	} else {
+		/* disable color key */
+		__raw_writel(0xFFFFFF, pxp->base + HW_PXP_OLCOLORKEYLOW);
+		__raw_writel(0, pxp->base + HW_PXP_OLCOLORKEYHIGH);
+	}
+}
+
+static void pxp_set_oln(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
+	dma_addr_t phys_addr = olparams_data->paddr;
+	__raw_writel(phys_addr, pxp->base + HW_PXP_OLn(layer_no));
+
+	/* Fixme */
+	__raw_writel(BF_PXP_OLnSIZE_WIDTH(olparams_data->width >> 3) |
+		     BF_PXP_OLnSIZE_HEIGHT(olparams_data->height >> 3),
+		     pxp->base + HW_PXP_OLnSIZE(layer_no));
+}
+
+static void pxp_set_olparam(int layer_no, struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
+	u32 olparam;
+
+	olparam = BF_PXP_OLnPARAM_ALPHA(olparams_data->global_alpha);
+	if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24)
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888);
+	else
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565);
+	if (olparams_data->global_alpha)
+		olparam |=
+		    BF_PXP_OLnPARAM_ALPHA_CNTL
+		    (BV_PXP_OLnPARAM_ALPHA_CNTL__Override);
+	if (olparams_data->color_key_enable)
+		olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY;
+	if (olparams_data->combine_enable)
+		olparam |= BM_PXP_OLnPARAM_ENABLE;
+	__raw_writel(olparam, pxp->base + HW_PXP_OLnPARAM(layer_no));
+}
+
+static void pxp_set_s0param(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0params_data = &pxp_conf->s0_param;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 s0param;
+
+	s0param = BF_PXP_S0PARAM_XBASE(proc_data->drect.left >> 3);
+	s0param |= BF_PXP_S0PARAM_YBASE(proc_data->drect.top >> 3);
+	s0param |= BF_PXP_S0PARAM_WIDTH(s0params_data->width >> 3);
+	s0param |= BF_PXP_S0PARAM_HEIGHT(s0params_data->height >> 3);
+	__raw_writel(s0param, pxp->base + HW_PXP_S0PARAM);
+}
+
+static void pxp_set_s0crop(struct pxps *pxp)
+{
+	u32 s0crop;
+	struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
+
+	s0crop = BF_PXP_S0CROP_XBASE(proc_data->srect.left >> 3);
+	s0crop |= BF_PXP_S0CROP_YBASE(proc_data->srect.top >> 3);
+	s0crop |= BF_PXP_S0CROP_WIDTH(proc_data->drect.width >> 3);
+	s0crop |= BF_PXP_S0CROP_HEIGHT(proc_data->drect.height >> 3);
+	__raw_writel(s0crop, pxp->base + HW_PXP_S0CROP);
+}
+
+static int pxp_set_scaling(struct pxps *pxp)
+{
+	int ret = 0;
+	u32 xscale, yscale, s0scale;
+	struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
+	struct pxp_layer_param *s0params_data = &pxp->pxp_conf_state.s0_param;
+
+	if ((s0params_data->pixel_fmt != PXP_PIX_FMT_YUV420P) &&
+	    (s0params_data->pixel_fmt != PXP_PIX_FMT_YUV422P)) {
+		proc_data->scaling = 0;
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if ((proc_data->srect.width == proc_data->drect.width) &&
+	    (proc_data->srect.height == proc_data->drect.height)) {
+		proc_data->scaling = 0;
+		__raw_writel(0x10001000, pxp->base + HW_PXP_S0SCALE);
+		goto out;
+	}
+
+	proc_data->scaling = 1;
+	xscale = proc_data->srect.width * 0x1000 / proc_data->drect.width;
+	yscale = proc_data->srect.height * 0x1000 / proc_data->drect.height;
+	if (xscale > PXP_DOWNSCALE_THRESHOLD)
+		xscale = PXP_DOWNSCALE_THRESHOLD;
+	if (yscale > PXP_DOWNSCALE_THRESHOLD)
+		yscale = PXP_DOWNSCALE_THRESHOLD;
+	s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale);
+	__raw_writel(s0scale, pxp->base + HW_PXP_S0SCALE);
+
+out:
+	pxp_set_ctrl(pxp);
+
+	return ret;
+}
+
+static void pxp_set_bg(struct pxps *pxp)
+{
+	__raw_writel(pxp->pxp_conf_state.proc_data.bgcolor,
+		     pxp->base + HW_PXP_S0BACKGROUND);
+}
+
+static void pxp_set_lut(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	u32 reg_val;
+	int i;
+
+	if (pxp_conf->proc_data.lut_transform == PXP_LUT_NONE) {
+		__raw_writel(BM_PXP_LUT_CTRL_BYPASS,
+			     pxp->base + HW_PXP_LUT_CTRL);
+	} else if (pxp_conf->proc_data.lut_transform == PXP_LUT_INVERT) {
+		/* Fill out LUT table with 8-bit inverted values */
+
+		/* Initialize LUT address to 0 and clear bypass bit */
+		__raw_writel(0, pxp->base + HW_PXP_LUT_CTRL);
+
+		/* LUT address pointer auto-increments after each data write */
+		for (i = 0; i < 256; i++) {
+			reg_val =
+			    __raw_readl(pxp->base +
+					HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR;
+			reg_val = ~reg_val & BM_PXP_LUT_DATA;
+			__raw_writel(reg_val, pxp->base + HW_PXP_LUT);
+		}
+	}
+}
+
+static void pxp_set_csc(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+	struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0];
+	struct pxp_layer_param *out_params = &pxp_conf->out_param;
+
+	bool input_is_YUV = is_yuv(s0_params->pixel_fmt);
+	bool output_is_YUV = is_yuv(out_params->pixel_fmt);
+
+	if (input_is_YUV && output_is_YUV) {
+		/*
+		 * Input = YUV, Output = YUV
+		 * No CSC unless we need to do combining
+		 */
+		if (ol_params->combine_enable) {
+			/* Must convert to RGB for combining with RGB overlay */
+
+			/* CSC1 - YUV->RGB */
+			__raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0);
+			__raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1);
+			__raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2);
+
+			/* CSC2 - RGB->YUV */
+			__raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL);
+			__raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0);
+			__raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1);
+			__raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2);
+			__raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3);
+			__raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4);
+			__raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5);
+		} else {
+			/* Input & Output both YUV, so bypass both CSCs */
+
+			/* CSC1 - Bypass */
+			__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+			/* CSC2 - Bypass */
+			__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+		}
+	} else if (input_is_YUV && !output_is_YUV) {
+		/*
+		 * Input = YUV, Output = RGB
+		 * Use CSC1 to convert to RGB
+		 */
+
+		/* CSC1 - YUV->RGB */
+		__raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0);
+		__raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1);
+		__raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2);
+
+		/* CSC2 - Bypass */
+		__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+	} else if (!input_is_YUV && output_is_YUV) {
+		/*
+		 * Input = RGB, Output = YUV
+		 * Use CSC2 to convert to YUV
+		 */
+
+		/* CSC1 - Bypass */
+		__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+		/* CSC2 - RGB->YUV */
+		__raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL);
+		__raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0);
+		__raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1);
+		__raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2);
+		__raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3);
+		__raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4);
+		__raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5);
+	} else {
+		/*
+		 * Input = RGB, Output = RGB
+		 * Input & Output both RGB, so bypass both CSCs
+		 */
+
+		/* CSC1 - Bypass */
+		__raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0);
+
+		/* CSC2 - Bypass */
+		__raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL);
+	}
+
+	/* YCrCb colorspace */
+	/* Not sure when we use this...no YCrCb formats are defined for PxP */
+	/*
+	   __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
+	   __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
+	   __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
+	 */
+
+}
+
+static void pxp_set_s0buf(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+	dma_addr_t Y, U, V;
+
+	Y = s0_params->paddr;
+	__raw_writel(Y, pxp->base + HW_PXP_S0BUF);
+	if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) ||
+	    (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) ||
+	    (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)) {
+		/* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */
+		int s = 2;
+		U = Y + (s0_params->width * s0_params->height);
+		V = U + ((s0_params->width * s0_params->height) >> s);
+		__raw_writel(U, pxp->base + HW_PXP_S0UBUF);
+		__raw_writel(V, pxp->base + HW_PXP_S0VBUF);
+	}
+}
+
+/**
+ * pxp_config() - configure PxP for a processing task
+ * @pxps:	PXP context.
+ * @pxp_chan:	PXP channel.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan)
+{
+	struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state;
+	int ol_nr;
+	int i;
+
+	/* Configure PxP regs */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+	ol_nr = pxp_conf_data->layer_nr - 2;
+	while (ol_nr > 0) {
+		i = pxp_conf_data->layer_nr - 2 - ol_nr;
+		pxp_set_oln(i, pxp);
+		pxp_set_olparam(i, pxp);
+		/* only the color key in higher overlay will take effect. */
+		pxp_set_olcolorkey(i, pxp);
+		ol_nr--;
+	}
+	pxp_set_s0colorkey(pxp);
+	pxp_set_csc(pxp);
+	pxp_set_bg(pxp);
+	pxp_set_lut(pxp);
+
+	pxp_set_s0buf(pxp);
+	pxp_set_outbuf(pxp);
+
+	return 0;
+}
+
+static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan)
+{
+	return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list);
+}
+
+static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan)
+{
+	return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list);
+}
+
+/* called with pxp_chan->lock held */
+static void __pxpdma_dostart(struct pxp_channel *pxp_chan)
+{
+	struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	struct pxp_tx_desc *desc;
+	struct pxp_tx_desc *child;
+	int i = 0;
+
+	/* so far we presume only one transaction on active_list */
+	/* S0 */
+	desc = pxpdma_first_active(pxp_chan);
+	memcpy(&pxp->pxp_conf_state.s0_param,
+	       &desc->layer_param.s0_param, sizeof(struct pxp_layer_param));
+	memcpy(&pxp->pxp_conf_state.proc_data,
+	       &desc->proc_data, sizeof(struct pxp_proc_data));
+
+	/* Save PxP configuration */
+	list_for_each_entry(child, &desc->txd.tx_list, list) {
+		if (i == 0) {	/* Output */
+			memcpy(&pxp->pxp_conf_state.out_param,
+			       &child->layer_param.out_param,
+			       sizeof(struct pxp_layer_param));
+		} else {	/* Overlay */
+			memcpy(&pxp->pxp_conf_state.ol_param[i - 1],
+			       &child->layer_param.ol_param,
+			       sizeof(struct pxp_layer_param));
+		}
+
+		i++;
+	}
+	pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__,
+		 pxp->pxp_conf_state.s0_param.width,
+		 pxp->pxp_conf_state.s0_param.height,
+		 pxp->pxp_conf_state.s0_param.paddr);
+	pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__,
+		 pxp->pxp_conf_state.out_param.width,
+		 pxp->pxp_conf_state.out_param.height,
+		 pxp->pxp_conf_state.out_param.paddr);
+}
+
+static void pxpdma_dostart_work(struct work_struct *w)
+{
+	struct pxps *pxp = container_of(w, struct pxps, work);
+	struct pxp_channel *pxp_chan = NULL;
+	unsigned long flags, flags1;
+
+	while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
+		;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+	if (list_empty(&head)) {
+		spin_unlock_irqrestore(&pxp->lock, flags);
+		return;
+	}
+
+	pxp_chan = list_entry(head.next, struct pxp_channel, list);
+
+	spin_lock_irqsave(&pxp_chan->lock, flags1);
+	if (!list_empty(&pxp_chan->active_list)) {
+		struct pxp_tx_desc *desc;
+		/* REVISIT */
+		desc = pxpdma_first_active(pxp_chan);
+		__pxpdma_dostart(pxp_chan);
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags1);
+
+	/* Configure PxP */
+	pxp_config(pxp, pxp_chan);
+
+	pxp_start(pxp);
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list)
+{
+	struct pxp_tx_desc *desc = NULL;
+	do {
+		desc = pxpdma_first_queued(pxp_chan);
+		list_move_tail(&desc->list, list);
+	} while (!list_empty(&pxp_chan->queue));
+}
+
+static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct pxp_tx_desc *desc = to_tx_desc(tx);
+	struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan);
+	dma_cookie_t cookie;
+	unsigned long flags;
+
+	dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n");
+
+	mutex_lock(&pxp_chan->chan_mutex);
+
+	cookie = pxp_chan->dma_chan.cookie;
+
+	if (++cookie < 0)
+		cookie = 1;
+
+	/* from dmaengine.h: "last cookie value returned to client" */
+	pxp_chan->dma_chan.cookie = cookie;
+	tx->cookie = cookie;
+
+	/* pxp_chan->lock can be taken under ichan->lock, but not v.v. */
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+
+	/* Here we add the tx descriptor to our PxP task queue. */
+	list_add_tail(&desc->list, &pxp_chan->queue);
+
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n");
+
+	mutex_unlock(&pxp_chan->chan_mutex);
+	return cookie;
+}
+
+/* Called with pxp_chan->chan_mutex held */
+static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n)
+{
+	struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc));
+
+	if (!desc)
+		return -ENOMEM;
+
+	pxp_chan->n_tx_desc = n;
+	pxp_chan->desc = desc;
+	INIT_LIST_HEAD(&pxp_chan->active_list);
+	INIT_LIST_HEAD(&pxp_chan->queue);
+	INIT_LIST_HEAD(&pxp_chan->free_list);
+
+	while (n--) {
+		struct dma_async_tx_descriptor *txd = &desc->txd;
+
+		memset(txd, 0, sizeof(*txd));
+		dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan);
+		txd->tx_submit = pxp_tx_submit;
+
+		list_add(&desc->list, &pxp_chan->free_list);
+
+		desc++;
+	}
+
+	return 0;
+}
+
+/**
+ * pxp_init_channel() - initialize a PXP channel.
+ * @pxp_dma:   PXP DMA context.
+ * @pchan:  pointer to the channel object.
+ * @return      0 on success or negative error code on failure.
+ */
+static int pxp_init_channel(struct pxp_dma *pxp_dma,
+			    struct pxp_channel *pxp_chan)
+{
+	unsigned long flags;
+	struct pxps *pxp = to_pxp(pxp_dma);
+	int ret = 0, n_desc = 0;
+
+	/*
+	 * We are using _virtual_ channel here.
+	 * Each channel contains all parameters of corresponding layers
+	 * for one transaction; each layer is represented as one descriptor
+	 * (i.e., pxp_tx_desc) here.
+	 */
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	/* max desc nr: S0+OL+OUT = 1+8+1 */
+	n_desc = 10;
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	if (n_desc && !pxp_chan->desc)
+		ret = pxp_desc_alloc(pxp_chan, n_desc);
+
+	return ret;
+}
+
+/**
+ * pxp_uninit_channel() - uninitialize a PXP channel.
+ * @pxp_dma:   PXP DMA context.
+ * @pchan:  pointer to the channel object.
+ * @return      0 on success or negative error code on failure.
+ */
+static int pxp_uninit_channel(struct pxp_dma *pxp_dma,
+			      struct pxp_channel *pxp_chan)
+{
+	int ret = 0;
+
+	if (pxp_chan->desc)
+		vfree(pxp_chan->desc);
+
+	pxp_chan->desc = NULL;
+
+	return ret;
+}
+
+static irqreturn_t pxp_irq(int irq, void *dev_id)
+{
+	struct pxps *pxp = dev_id;
+	struct pxp_channel *pxp_chan;
+	struct pxp_tx_desc *desc;
+	dma_async_tx_callback callback;
+	void *callback_param;
+	unsigned long flags, flags1;
+	u32 hist_status;
+
+	hist_status =
+	    __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS;
+
+	__raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR);
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	if (list_empty(&head)) {
+		spin_unlock_irqrestore(&pxp->lock, flags);
+		return IRQ_NONE;
+	}
+
+	spin_lock_irqsave(&pxp_chan->lock, flags1);
+	pxp_chan = list_entry(head.next, struct pxp_channel, list);
+	list_del_init(&pxp_chan->list);
+
+	if (list_empty(&pxp_chan->active_list)) {
+		pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n",
+			 pxp_chan->dma_chan.chan_id);
+		spin_unlock_irqrestore(&pxp_chan->lock, flags1);
+		spin_unlock_irqrestore(&pxp->lock, flags);
+		return IRQ_NONE;
+	}
+
+	/* Get descriptor and call callback */
+	desc = pxpdma_first_active(pxp_chan);
+
+	pxp_chan->completed = desc->txd.cookie;
+
+	callback = desc->txd.callback;
+	callback_param = desc->txd.callback_param;
+
+	/* Send histogram status back to caller */
+	desc->hist_status = hist_status;
+
+	if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
+		callback(callback_param);
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+
+	list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list);
+	list_move(&desc->list, &pxp_chan->free_list);
+
+	list_del(&pxp_chan->list);
+
+	wake_up(&pxp->done);
+
+	spin_unlock_irqrestore(&pxp_chan->lock, flags1);
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static struct pxp_tx_desc *pxp_desc_get(struct pxp_channel *pxp_chan)
+{
+	struct pxp_tx_desc *desc, *_desc;
+	struct pxp_tx_desc *ret = NULL;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) {
+		list_del_init(&desc->list);
+		ret = desc;
+		break;
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	return ret;
+}
+
+static void pxpdma_desc_put(struct pxp_channel *pxp_chan,
+			    struct pxp_tx_desc *desc)
+{
+	if (desc) {
+		struct device *dev = &pxp_chan->dma_chan.dev->device;
+		struct pxp_tx_desc *child;
+		unsigned long flags;
+
+		spin_lock_irqsave(&pxp_chan->lock, flags);
+		list_for_each_entry(child, &desc->txd.tx_list, list)
+		    dev_info(dev, "moving child desc %p to freelist\n", child);
+		list_splice_init(&desc->txd.tx_list, &pxp_chan->free_list);
+		dev_info(dev, "moving desc %p to freelist\n", desc);
+		list_add(&desc->list, &pxp_chan->free_list);
+		spin_unlock_irqrestore(&pxp_chan->lock, flags);
+	}
+}
+
+/* Allocate and initialise a transfer descriptor. */
+static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan,
+							 struct scatterlist
+							 *sgl,
+							 unsigned int sg_len,
+							 enum dma_data_direction
+							 direction,
+							 unsigned long tx_flags)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	struct pxp_tx_desc *desc = NULL;
+	struct pxp_tx_desc *first = NULL, *prev = NULL;
+	struct scatterlist *sg;
+	unsigned long flags;
+	dma_addr_t phys_addr;
+	int i;
+
+	if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
+		dev_err(chan->device->dev, "Invalid DMA direction %d!\n",
+			direction);
+		return NULL;
+	}
+
+	if (unlikely(sg_len < 2))
+		return NULL;
+
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	for_each_sg(sgl, sg, sg_len, i) {
+		desc = pxp_desc_get(pxp_chan);
+		if (!desc) {
+			pxpdma_desc_put(pxp_chan, first);
+			dev_err(chan->device->dev, "Can't get DMA desc.\n");
+			spin_unlock_irqrestore(&pxp_chan->lock, flags);
+			return NULL;
+		}
+
+		phys_addr = sg_dma_address(sg);
+
+		if (!first) {
+			first = desc;
+
+			desc->layer_param.s0_param.paddr = phys_addr;
+		} else {
+			list_add_tail(&desc->list, &first->txd.tx_list);
+			prev->next = desc;
+			desc->next = NULL;
+
+			if (i == 1)
+				desc->layer_param.out_param.paddr = phys_addr;
+			else
+				desc->layer_param.ol_param.paddr = phys_addr;
+		}
+
+		prev = desc;
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	pxp->pxp_conf_state.layer_nr = sg_len;
+	first->txd.flags = tx_flags;
+	first->len = sg_len;
+	pr_debug("%s:%d first %p, first->len %d, flags %08x\n",
+		 __func__, __LINE__, first, first->len, first->txd.flags);
+
+	return &first->txd;
+}
+
+static void pxp_issue_pending(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	struct pxps *pxp = to_pxp(pxp_dma);
+	unsigned long flags0, flags;
+
+	spin_lock_irqsave(&pxp->lock, flags0);
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+
+	if (!list_empty(&pxp_chan->queue)) {
+		pxpdma_dequeue(pxp_chan, &pxp_chan->active_list);
+		pxp_chan->status = PXP_CHANNEL_READY;
+		list_add_tail(&pxp_chan->list, &head);
+	} else {
+		spin_unlock_irqrestore(&pxp_chan->lock, flags);
+		spin_unlock_irqrestore(&pxp->lock, flags0);
+		return;
+	}
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+	spin_unlock_irqrestore(&pxp->lock, flags0);
+
+	if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, 2 * HZ) ||
+		signal_pending(current))
+		return;
+
+	queue_work(pxp->workqueue, &pxp->work);
+}
+
+static void __pxp_terminate_all(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	unsigned long flags;
+
+	cancel_work_sync(&to_pxp(pxp_dma)->work);
+
+	/* pchan->queue is modified in ISR, have to spinlock */
+	spin_lock_irqsave(&pxp_chan->lock, flags);
+	list_splice_init(&pxp_chan->queue, &pxp_chan->free_list);
+	list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list);
+
+	spin_unlock_irqrestore(&pxp_chan->lock, flags);
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+}
+
+static void pxp_terminate_all(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+
+	mutex_lock(&pxp_chan->chan_mutex);
+	__pxp_terminate_all(chan);
+	mutex_unlock(&pxp_chan->chan_mutex);
+}
+
+static int pxp_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+	int ret;
+
+	/* dmaengine.c now guarantees to only offer free channels */
+	BUG_ON(chan->client_count > 1);
+	WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE);
+
+	chan->cookie = 1;
+	pxp_chan->completed = -ENXIO;
+
+	pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id);
+	ret = pxp_init_channel(pxp_dma, pxp_chan);
+	if (ret < 0)
+		goto err_chan;
+
+	pxp_chan->status = PXP_CHANNEL_INITIALIZED;
+
+	dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
+		chan->chan_id, pxp_chan->eof_irq);
+
+	return ret;
+
+err_chan:
+	return ret;
+}
+
+static void pxp_free_chan_resources(struct dma_chan *chan)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
+
+	mutex_lock(&pxp_chan->chan_mutex);
+
+	__pxp_terminate_all(chan);
+
+	pxp_chan->status = PXP_CHANNEL_FREE;
+
+	pxp_uninit_channel(pxp_dma, pxp_chan);
+
+	mutex_unlock(&pxp_chan->chan_mutex);
+}
+
+static enum dma_status pxp_is_tx_complete(struct dma_chan *chan,
+					  dma_cookie_t cookie,
+					  dma_cookie_t *done,
+					  dma_cookie_t *used)
+{
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+
+	if (done)
+		*done = pxp_chan->completed;
+	if (used)
+		*used = chan->cookie;
+	if (cookie != chan->cookie)
+		return DMA_ERROR;
+	return DMA_SUCCESS;
+}
+
+static int pxp_hw_init(struct pxps *pxp)
+{
+	struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	u32 reg_val;
+	int i;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, pxp->base + HW_PXP_CTRL);
+
+	/* Config defaults */
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = 0;
+	proc_data->drect.height = proc_data->srect.height = 0;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = 0;
+	proc_data->bgcolor = 0;
+
+	/* Initialize S0 channel parameters */
+	pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0];
+	pxp_conf->s0_param.width = 0;
+	pxp_conf->s0_param.height = 0;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/* Initialize OL channel parameters */
+	for (i = 0; i < 8; i++) {
+		pxp_conf->ol_param[i].combine_enable = false;
+		pxp_conf->ol_param[i].width = 0;
+		pxp_conf->ol_param[i].height = 0;
+		pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
+		pxp_conf->ol_param[i].color_key_enable = false;
+		pxp_conf->ol_param[i].color_key = -1;
+		pxp_conf->ol_param[i].global_alpha_enable = false;
+		pxp_conf->ol_param[i].global_alpha = 0;
+		pxp_conf->ol_param[i].local_alpha_enable = false;
+	}
+
+	/* Initialize Output channel parameters */
+	pxp_conf->out_param.width = 0;
+	pxp_conf->out_param.height = 0;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+
+	proc_data->overlay_state = 0;
+
+	/* Write default h/w config */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	for (i = 0; i < 8; i++) {
+		pxp_set_oln(i, pxp);
+		pxp_set_olparam(i, pxp);
+		pxp_set_olcolorkey(i, pxp);
+	}
+	pxp_set_s0colorkey(pxp);
+	pxp_set_csc(pxp);
+	pxp_set_bg(pxp);
+	pxp_set_lut(pxp);
+
+	/* One-time histogram configuration */
+	reg_val =
+	    BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL);
+
+	reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) |
+	    BF_PXP_HIST2_PARAM_VALUE1(0x00F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM);
+
+	reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) |
+	    BF_PXP_HIST4_PARAM_VALUE1(0x05) |
+	    BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM);
+
+	reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) |
+	    BF_PXP_HIST8_PARAM0_VALUE1(0x02) |
+	    BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0);
+	reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) |
+	    BF_PXP_HIST8_PARAM1_VALUE5(0x0B) |
+	    BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1);
+
+	reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) |
+	    BF_PXP_HIST16_PARAM0_VALUE1(0x01) |
+	    BF_PXP_HIST16_PARAM0_VALUE2(0x02) |
+	    BF_PXP_HIST16_PARAM0_VALUE3(0x03);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0);
+	reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) |
+	    BF_PXP_HIST16_PARAM1_VALUE5(0x05) |
+	    BF_PXP_HIST16_PARAM1_VALUE6(0x06) |
+	    BF_PXP_HIST16_PARAM1_VALUE7(0x07);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1);
+	reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) |
+	    BF_PXP_HIST16_PARAM2_VALUE9(0x09) |
+	    BF_PXP_HIST16_PARAM2_VALUE10(0x0A) |
+	    BF_PXP_HIST16_PARAM2_VALUE11(0x0B);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2);
+	reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) |
+	    BF_PXP_HIST16_PARAM3_VALUE13(0x0D) |
+	    BF_PXP_HIST16_PARAM3_VALUE14(0x0E) |
+	    BF_PXP_HIST16_PARAM3_VALUE15(0x0F);
+	__raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3);
+
+	return 0;
+}
+
+static int pxp_dma_init(struct pxps *pxp)
+{
+	struct pxp_dma *pxp_dma = &pxp->pxp_dma;
+	struct dma_device *dma = &pxp_dma->dma;
+	int i;
+
+	dma_cap_set(DMA_SLAVE, dma->cap_mask);
+	dma_cap_set(DMA_PRIVATE, dma->cap_mask);
+
+	/* Compulsory common fields */
+	dma->dev = pxp->dev;
+	dma->device_alloc_chan_resources = pxp_alloc_chan_resources;
+	dma->device_free_chan_resources = pxp_free_chan_resources;
+	dma->device_is_tx_complete = pxp_is_tx_complete;
+	dma->device_issue_pending = pxp_issue_pending;
+
+	/* Compulsory for DMA_SLAVE fields */
+	dma->device_prep_slave_sg = pxp_prep_slave_sg;
+	dma->device_terminate_all = pxp_terminate_all;
+
+	/* Initialize PxP Channels */
+	INIT_LIST_HEAD(&dma->channels);
+	for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) {
+		struct pxp_channel *pxp_chan = pxp->channel + i;
+		struct dma_chan *dma_chan = &pxp_chan->dma_chan;
+
+		spin_lock_init(&pxp_chan->lock);
+		mutex_init(&pxp_chan->chan_mutex);
+
+		/* Only one EOF IRQ for PxP, shared by all channels */
+		pxp_chan->eof_irq = pxp->irq;
+		pxp_chan->status = PXP_CHANNEL_FREE;
+		pxp_chan->completed = -ENXIO;
+		snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name),
+			 "PXP EOF %d", i);
+
+		dma_chan->device = &pxp_dma->dma;
+		dma_chan->cookie = 1;
+		dma_chan->chan_id = i;
+		list_add_tail(&dma_chan->device_node, &dma->channels);
+	}
+
+	return dma_async_device_register(&pxp_dma->dma);
+}
+
+static int pxp_probe(struct platform_device *pdev)
+{
+	struct pxps *pxp;
+	struct resource *res;
+	int irq;
+	int err = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!res || irq < 0) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
+	if (!pxp) {
+		dev_err(&pdev->dev, "failed to allocate control object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	pxp->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pxp);
+	pxp->irq = irq;
+
+	spin_lock_init(&pxp->lock);
+	mutex_init(&pxp->mutex);
+
+	if (!request_mem_region(res->start, resource_size(res), "pxp-mem")) {
+		err = -EBUSY;
+		goto freepxp;
+	}
+
+	pxp->base = ioremap(res->start, SZ_4K);
+	pxp->pdev = pdev;
+
+	pxp->clk = clk_get(NULL, "pxp_axi");
+	clk_enable(pxp->clk);
+
+	err = pxp_hw_init(pxp);
+	if (err) {
+		dev_err(&pdev->dev, "failed to initialize hardware\n");
+		goto release;
+	}
+
+	err = request_irq(pxp->irq, pxp_irq, 0, "pxp-irq", pxp);
+	if (err)
+		goto release;
+	/* Initialize DMA engine */
+	err = pxp_dma_init(pxp);
+	if (err < 0)
+		goto err_dma_init;
+
+	init_waitqueue_head(&pxp->done);
+	INIT_WORK(&pxp->work, pxpdma_dostart_work);
+	pxp->workqueue = create_singlethread_workqueue("pxp_dma");
+exit:
+	return err;
+err_dma_init:
+	free_irq(pxp->irq, pxp);
+	clk_disable(pxp->clk);
+release:
+	release_mem_region(res->start, resource_size(res));
+freepxp:
+	kfree(pxp);
+	dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe function\n");
+	return err;
+}
+
+static int __devexit pxp_remove(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	cancel_work_sync(&pxp->work);
+	kfree(pxp);
+
+	free_irq(pxp->irq, pxp);
+	clk_disable(pxp->clk);
+	clk_put(pxp->clk);
+	iounmap(pxp->base);
+
+	kfree(pxp);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pxp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
+		;
+
+	__raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL);
+	clk_disable(pxp->clk);
+
+	return 0;
+}
+
+static int pxp_resume(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	clk_enable(pxp->clk);
+	/* Pull PxP out of reset */
+	__raw_writel(0, pxp->base + HW_PXP_CTRL);
+
+	return 0;
+}
+#else
+#define	pxp_suspend	NULL
+#define	pxp_resume	NULL
+#endif
+
+static struct platform_driver pxp_driver = {
+	.driver = {
+		   .name = "mxc-pxp",
+		   },
+	.probe = pxp_probe,
+	.remove = __exit_p(pxp_remove),
+	.suspend = pxp_suspend,
+	.resume = pxp_resume,
+};
+
+static int __init pxp_init(void)
+{
+	return platform_driver_register(&pxp_driver);
+}
+
+subsys_initcall(pxp_init);
+
+static void __exit pxp_exit(void)
+{
+	platform_driver_unregister(&pxp_driver);
+}
+
+module_exit(pxp_exit);
+
+MODULE_DESCRIPTION("i.MX PxP driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pxp/regs-pxp.h b/drivers/dma/pxp/regs-pxp.h
new file mode 100644
index 000000000000..b0c1b00fdfa0
--- /dev/null
+++ b/drivers/dma/pxp/regs-pxp.h
@@ -0,0 +1,949 @@
+/*
+ * Freescale PXP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.6
+ * Template revision: 1.3
+ */
+
+#ifndef __ARCH_ARM___PXP_H
+#define __ARCH_ARM___PXP_H
+
+
+#define HW_PXP_CTRL	(0x00000000)
+#define HW_PXP_CTRL_SET	(0x00000004)
+#define HW_PXP_CTRL_CLR	(0x00000008)
+#define HW_PXP_CTRL_TOG	(0x0000000c)
+
+#define BM_PXP_CTRL_SFTRST 0x80000000
+#define BM_PXP_CTRL_CLKGATE 0x40000000
+#define BM_PXP_CTRL_RSVD 0x20000000
+#define BM_PXP_CTRL_EN_REPEAT 0x10000000
+#define BP_PXP_CTRL_INTERLACED_OUTPUT      26
+#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000
+#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)  \
+	(((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT)
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0      0x1
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1      0x2
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED  0x3
+#define BP_PXP_CTRL_INTERLACED_INPUT      24
+#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
+#define BF_PXP_CTRL_INTERLACED_INPUT(v)  \
+	(((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0      0x2
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1      0x3
+#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
+#define BV_PXP_CTRL_BLOCK_SIZE__8X8   0x0
+#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
+#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000
+#define BM_PXP_CTRL_IN_PLACE 0x00200000
+#define BM_PXP_CTRL_DELTA 0x00100000
+#define BM_PXP_CTRL_CROP 0x00080000
+#define BM_PXP_CTRL_SCALE 0x00040000
+#define BM_PXP_CTRL_UPSAMPLE 0x00020000
+#define BM_PXP_CTRL_SUBSAMPLE 0x00010000
+#define BP_PXP_CTRL_S0_FORMAT      12
+#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
+#define BF_PXP_CTRL_S0_FORMAT(v)  \
+	(((v) << 12) & BM_PXP_CTRL_S0_FORMAT)
+#define BV_PXP_CTRL_S0_FORMAT__RGB888    0x1
+#define BV_PXP_CTRL_S0_FORMAT__RGB565    0x4
+#define BV_PXP_CTRL_S0_FORMAT__RGB555    0x5
+#define BV_PXP_CTRL_S0_FORMAT__YUV422    0x8
+#define BV_PXP_CTRL_S0_FORMAT__YUV420    0x9
+#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA
+#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB
+#define BV_PXP_CTRL_S0_FORMAT__YUV2P422  0xC
+#define BV_PXP_CTRL_S0_FORMAT__YUV2P420  0xD
+#define BV_PXP_CTRL_S0_FORMAT__YVU2P422  0xE
+#define BV_PXP_CTRL_S0_FORMAT__YVU2P420  0xF
+#define BM_PXP_CTRL_VFLIP 0x00000800
+#define BM_PXP_CTRL_HFLIP 0x00000400
+#define BP_PXP_CTRL_ROTATE      8
+#define BM_PXP_CTRL_ROTATE 0x00000300
+#define BF_PXP_CTRL_ROTATE(v)  \
+	(((v) << 8) & BM_PXP_CTRL_ROTATE)
+#define BV_PXP_CTRL_ROTATE__ROT_0   0x0
+#define BV_PXP_CTRL_ROTATE__ROT_90  0x1
+#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
+#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
+#define BP_PXP_CTRL_OUTBUF_FORMAT      4
+#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0
+#define BF_PXP_CTRL_OUTBUF_FORMAT(v)  \
+	(((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT)
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888  0x0
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888    0x1
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P   0x2
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555  0x3
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565    0x4
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555    0x5
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444    0x7
+#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8    0x8
+#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC4    0x9
+#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA
+#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422  0xC
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420  0xD
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422  0xE
+#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420  0xF
+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008
+#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
+#define BM_PXP_CTRL_ENABLE 0x00000001
+
+#define HW_PXP_STAT	(0x00000010)
+#define HW_PXP_STAT_SET	(0x00000014)
+#define HW_PXP_STAT_CLR	(0x00000018)
+#define HW_PXP_STAT_TOG	(0x0000001c)
+
+#define BP_PXP_STAT_BLOCKX      24
+#define BM_PXP_STAT_BLOCKX 0xFF000000
+#define BF_PXP_STAT_BLOCKX(v) \
+	(((v) << 24) & BM_PXP_STAT_BLOCKX)
+#define BP_PXP_STAT_BLOCKY      16
+#define BM_PXP_STAT_BLOCKY 0x00FF0000
+#define BF_PXP_STAT_BLOCKY(v)  \
+	(((v) << 16) & BM_PXP_STAT_BLOCKY)
+#define BP_PXP_STAT_RSVD2      8
+#define BM_PXP_STAT_RSVD2 0x0000FF00
+#define BF_PXP_STAT_RSVD2(v)  \
+	(((v) << 8) & BM_PXP_STAT_RSVD2)
+#define BP_PXP_STAT_AXI_ERROR_ID      4
+#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
+#define BF_PXP_STAT_AXI_ERROR_ID(v)  \
+	(((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
+#define BM_PXP_STAT_NEXT_IRQ 0x00000008
+#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
+#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
+#define BM_PXP_STAT_IRQ 0x00000001
+
+#define HW_PXP_OUTBUF	(0x00000020)
+
+#define BP_PXP_OUTBUF_ADDR      0
+#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_OUTBUF_ADDR(v)   (v)
+
+#define HW_PXP_OUTBUF2	(0x00000030)
+
+#define BP_PXP_OUTBUF2_ADDR      0
+#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF
+#define BF_PXP_OUTBUF2_ADDR(v)   (v)
+
+#define HW_PXP_OUTSIZE	(0x00000040)
+
+#define BP_PXP_OUTSIZE_ALPHA      24
+#define BM_PXP_OUTSIZE_ALPHA 0xFF000000
+#define BF_PXP_OUTSIZE_ALPHA(v) \
+	(((v) << 24) & BM_PXP_OUTSIZE_ALPHA)
+#define BP_PXP_OUTSIZE_WIDTH      12
+#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000
+#define BF_PXP_OUTSIZE_WIDTH(v)  \
+	(((v) << 12) & BM_PXP_OUTSIZE_WIDTH)
+#define BP_PXP_OUTSIZE_HEIGHT      0
+#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF
+#define BF_PXP_OUTSIZE_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_OUTSIZE_HEIGHT)
+
+#define HW_PXP_S0BUF	(0x00000050)
+
+#define BP_PXP_S0BUF_ADDR      0
+#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0BUF_ADDR(v)   (v)
+
+#define HW_PXP_S0UBUF	(0x00000060)
+
+#define BP_PXP_S0UBUF_ADDR      0
+#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0UBUF_ADDR(v)   (v)
+
+#define HW_PXP_S0VBUF	(0x00000070)
+
+#define BP_PXP_S0VBUF_ADDR      0
+#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0VBUF_ADDR(v)   (v)
+
+#define HW_PXP_S0PARAM	(0x00000080)
+
+#define BP_PXP_S0PARAM_XBASE      24
+#define BM_PXP_S0PARAM_XBASE 0xFF000000
+#define BF_PXP_S0PARAM_XBASE(v) \
+	(((v) << 24) & BM_PXP_S0PARAM_XBASE)
+#define BP_PXP_S0PARAM_YBASE      16
+#define BM_PXP_S0PARAM_YBASE 0x00FF0000
+#define BF_PXP_S0PARAM_YBASE(v)  \
+	(((v) << 16) & BM_PXP_S0PARAM_YBASE)
+#define BP_PXP_S0PARAM_WIDTH      8
+#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
+#define BF_PXP_S0PARAM_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_S0PARAM_WIDTH)
+#define BP_PXP_S0PARAM_HEIGHT      0
+#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
+#define BF_PXP_S0PARAM_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_S0PARAM_HEIGHT)
+
+#define HW_PXP_S0BACKGROUND	(0x00000090)
+
+#define BP_PXP_S0BACKGROUND_COLOR      0
+#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF
+#define BF_PXP_S0BACKGROUND_COLOR(v)   (v)
+
+#define HW_PXP_S0CROP	(0x000000a0)
+
+#define BP_PXP_S0CROP_XBASE      24
+#define BM_PXP_S0CROP_XBASE 0xFF000000
+#define BF_PXP_S0CROP_XBASE(v) \
+	(((v) << 24) & BM_PXP_S0CROP_XBASE)
+#define BP_PXP_S0CROP_YBASE      16
+#define BM_PXP_S0CROP_YBASE 0x00FF0000
+#define BF_PXP_S0CROP_YBASE(v)  \
+	(((v) << 16) & BM_PXP_S0CROP_YBASE)
+#define BP_PXP_S0CROP_WIDTH      8
+#define BM_PXP_S0CROP_WIDTH 0x0000FF00
+#define BF_PXP_S0CROP_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_S0CROP_WIDTH)
+#define BP_PXP_S0CROP_HEIGHT      0
+#define BM_PXP_S0CROP_HEIGHT 0x000000FF
+#define BF_PXP_S0CROP_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_S0CROP_HEIGHT)
+
+#define HW_PXP_S0SCALE	(0x000000b0)
+
+#define BM_PXP_S0SCALE_RSVD2 0x80000000
+#define BP_PXP_S0SCALE_YSCALE      16
+#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000
+#define BF_PXP_S0SCALE_YSCALE(v)  \
+	(((v) << 16) & BM_PXP_S0SCALE_YSCALE)
+#define BM_PXP_S0SCALE_RSVD1 0x00008000
+#define BP_PXP_S0SCALE_XSCALE      0
+#define BM_PXP_S0SCALE_XSCALE 0x00007FFF
+#define BF_PXP_S0SCALE_XSCALE(v)  \
+	(((v) << 0) & BM_PXP_S0SCALE_XSCALE)
+
+#define HW_PXP_S0OFFSET	(0x000000c0)
+
+#define BP_PXP_S0OFFSET_RSVD2      28
+#define BM_PXP_S0OFFSET_RSVD2 0xF0000000
+#define BF_PXP_S0OFFSET_RSVD2(v) \
+	(((v) << 28) & BM_PXP_S0OFFSET_RSVD2)
+#define BP_PXP_S0OFFSET_YOFFSET      16
+#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000
+#define BF_PXP_S0OFFSET_YOFFSET(v)  \
+	(((v) << 16) & BM_PXP_S0OFFSET_YOFFSET)
+#define BP_PXP_S0OFFSET_RSVD1      12
+#define BM_PXP_S0OFFSET_RSVD1 0x0000F000
+#define BF_PXP_S0OFFSET_RSVD1(v)  \
+	(((v) << 12) & BM_PXP_S0OFFSET_RSVD1)
+#define BP_PXP_S0OFFSET_XOFFSET      0
+#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF
+#define BF_PXP_S0OFFSET_XOFFSET(v)  \
+	(((v) << 0) & BM_PXP_S0OFFSET_XOFFSET)
+
+#define HW_PXP_CSCCOEF0	(0x000000d0)
+
+#define BM_PXP_CSCCOEF0_YCBCR_MODE 0x80000000
+#define BM_PXP_CSCCOEF0_BYPASS 0x40000000
+#define BM_PXP_CSCCOEF0_RSVD1 0x20000000
+#define BP_PXP_CSCCOEF0_C0      18
+#define BM_PXP_CSCCOEF0_C0 0x1FFC0000
+#define BF_PXP_CSCCOEF0_C0(v)  \
+	(((v) << 18) & BM_PXP_CSCCOEF0_C0)
+#define BP_PXP_CSCCOEF0_UV_OFFSET      9
+#define BM_PXP_CSCCOEF0_UV_OFFSET 0x0003FE00
+#define BF_PXP_CSCCOEF0_UV_OFFSET(v)  \
+	(((v) << 9) & BM_PXP_CSCCOEF0_UV_OFFSET)
+#define BP_PXP_CSCCOEF0_Y_OFFSET      0
+#define BM_PXP_CSCCOEF0_Y_OFFSET 0x000001FF
+#define BF_PXP_CSCCOEF0_Y_OFFSET(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF0_Y_OFFSET)
+
+#define HW_PXP_CSCCOEF1	(0x000000e0)
+
+#define BP_PXP_CSCCOEF1_RSVD1      27
+#define BM_PXP_CSCCOEF1_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEF1_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSCCOEF1_RSVD1)
+#define BP_PXP_CSCCOEF1_C1      16
+#define BM_PXP_CSCCOEF1_C1 0x07FF0000
+#define BF_PXP_CSCCOEF1_C1(v)  \
+	(((v) << 16) & BM_PXP_CSCCOEF1_C1)
+#define BP_PXP_CSCCOEF1_RSVD0      11
+#define BM_PXP_CSCCOEF1_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEF1_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSCCOEF1_RSVD0)
+#define BP_PXP_CSCCOEF1_C4      0
+#define BM_PXP_CSCCOEF1_C4 0x000007FF
+#define BF_PXP_CSCCOEF1_C4(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF1_C4)
+
+#define HW_PXP_CSCCOEF2	(0x000000f0)
+
+#define BP_PXP_CSCCOEF2_RSVD1      27
+#define BM_PXP_CSCCOEF2_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEF2_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSCCOEF2_RSVD1)
+#define BP_PXP_CSCCOEF2_C2      16
+#define BM_PXP_CSCCOEF2_C2 0x07FF0000
+#define BF_PXP_CSCCOEF2_C2(v)  \
+	(((v) << 16) & BM_PXP_CSCCOEF2_C2)
+#define BP_PXP_CSCCOEF2_RSVD0      11
+#define BM_PXP_CSCCOEF2_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEF2_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSCCOEF2_RSVD0)
+#define BP_PXP_CSCCOEF2_C3      0
+#define BM_PXP_CSCCOEF2_C3 0x000007FF
+#define BF_PXP_CSCCOEF2_C3(v)  \
+	(((v) << 0) & BM_PXP_CSCCOEF2_C3)
+
+#define HW_PXP_NEXT	(0x00000100)
+#define HW_PXP_NEXT_SET	(0x00000104)
+#define HW_PXP_NEXT_CLR	(0x00000108)
+#define HW_PXP_NEXT_TOG	(0x0000010c)
+
+#define BP_PXP_NEXT_POINTER      2
+#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
+#define BF_PXP_NEXT_POINTER(v) \
+	(((v) << 2) & BM_PXP_NEXT_POINTER)
+#define BM_PXP_NEXT_RSVD 0x00000002
+#define BM_PXP_NEXT_ENABLED 0x00000001
+
+#define HW_PXP_S0COLORKEYLOW	(0x00000180)
+
+#define BP_PXP_S0COLORKEYLOW_RSVD1      24
+#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \
+	(((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1)
+#define BP_PXP_S0COLORKEYLOW_PIXEL      0
+#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYLOW_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL)
+
+#define HW_PXP_S0COLORKEYHIGH	(0x00000190)
+
+#define BP_PXP_S0COLORKEYHIGH_RSVD1      24
+#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \
+	(((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1)
+#define BP_PXP_S0COLORKEYHIGH_PIXEL      0
+#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL)
+
+#define HW_PXP_OLCOLORKEYLOW	(0x000001a0)
+
+#define BP_PXP_OLCOLORKEYLOW_RSVD1      24
+#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \
+	(((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1)
+#define BP_PXP_OLCOLORKEYLOW_PIXEL      0
+#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL)
+
+#define HW_PXP_OLCOLORKEYHIGH	(0x000001b0)
+
+#define BP_PXP_OLCOLORKEYHIGH_RSVD1      24
+#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \
+	(((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1)
+#define BP_PXP_OLCOLORKEYHIGH_PIXEL      0
+#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)  \
+	(((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL)
+
+#define HW_PXP_DEBUGCTRL	(0x000001d0)
+
+#define BP_PXP_DEBUGCTRL_RSVD      8
+#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFF00
+#define BF_PXP_DEBUGCTRL_RSVD(v) \
+	(((v) << 8) & BM_PXP_DEBUGCTRL_RSVD)
+#define BP_PXP_DEBUGCTRL_SELECT      0
+#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
+#define BF_PXP_DEBUGCTRL_SELECT(v)  \
+	(((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
+#define BV_PXP_DEBUGCTRL_SELECT__NONE     0x0
+#define BV_PXP_DEBUGCTRL_SELECT__CTRL     0x1
+#define BV_PXP_DEBUGCTRL_SELECT__S0REGS   0x2
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAX    0x3
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAY    0x4
+#define BV_PXP_DEBUGCTRL_SELECT__PXBUF    0x5
+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0  0x7
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1  0x8
+
+#define HW_PXP_DEBUG	(0x000001e0)
+
+#define BP_PXP_DEBUG_DATA      0
+#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
+#define BF_PXP_DEBUG_DATA(v)   (v)
+
+#define HW_PXP_VERSION	(0x000001f0)
+
+#define BP_PXP_VERSION_MAJOR      24
+#define BM_PXP_VERSION_MAJOR 0xFF000000
+#define BF_PXP_VERSION_MAJOR(v) \
+	(((v) << 24) & BM_PXP_VERSION_MAJOR)
+#define BP_PXP_VERSION_MINOR      16
+#define BM_PXP_VERSION_MINOR 0x00FF0000
+#define BF_PXP_VERSION_MINOR(v)  \
+	(((v) << 16) & BM_PXP_VERSION_MINOR)
+#define BP_PXP_VERSION_STEP      0
+#define BM_PXP_VERSION_STEP 0x0000FFFF
+#define BF_PXP_VERSION_STEP(v)  \
+	(((v) << 0) & BM_PXP_VERSION_STEP)
+
+/*
+ *  multi-register-define name HW_PXP_OLn
+ *              base 0x00000200
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLn(n)	(0x00000200 + (n) * 0x40)
+#define BP_PXP_OLn_ADDR      0
+#define BM_PXP_OLn_ADDR 0xFFFFFFFF
+#define BF_PXP_OLn_ADDR(v)   (v)
+
+/*
+ *  multi-register-define name HW_PXP_OLnSIZE
+ *              base 0x00000210
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnSIZE(n)	(0x00000210 + (n) * 0x40)
+#define BP_PXP_OLnSIZE_XBASE      24
+#define BM_PXP_OLnSIZE_XBASE 0xFF000000
+#define BF_PXP_OLnSIZE_XBASE(v) \
+	(((v) << 24) & BM_PXP_OLnSIZE_XBASE)
+#define BP_PXP_OLnSIZE_YBASE      16
+#define BM_PXP_OLnSIZE_YBASE 0x00FF0000
+#define BF_PXP_OLnSIZE_YBASE(v)  \
+	(((v) << 16) & BM_PXP_OLnSIZE_YBASE)
+#define BP_PXP_OLnSIZE_WIDTH      8
+#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
+#define BF_PXP_OLnSIZE_WIDTH(v)  \
+	(((v) << 8) & BM_PXP_OLnSIZE_WIDTH)
+#define BP_PXP_OLnSIZE_HEIGHT      0
+#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
+#define BF_PXP_OLnSIZE_HEIGHT(v)  \
+	(((v) << 0) & BM_PXP_OLnSIZE_HEIGHT)
+
+/*
+ *  multi-register-define name HW_PXP_OLnPARAM
+ *              base 0x00000220
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnPARAM(n)	(0x00000220 + (n) * 0x40)
+#define BP_PXP_OLnPARAM_RSVD1      20
+#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000
+#define BF_PXP_OLnPARAM_RSVD1(v) \
+	(((v) << 20) & BM_PXP_OLnPARAM_RSVD1)
+#define BP_PXP_OLnPARAM_ROP      16
+#define BM_PXP_OLnPARAM_ROP 0x000F0000
+#define BF_PXP_OLnPARAM_ROP(v)  \
+	(((v) << 16) & BM_PXP_OLnPARAM_ROP)
+#define BV_PXP_OLnPARAM_ROP__MASKOL     0x0
+#define BV_PXP_OLnPARAM_ROP__MASKNOTOL  0x1
+#define BV_PXP_OLnPARAM_ROP__MASKOLNOT  0x2
+#define BV_PXP_OLnPARAM_ROP__MERGEOL    0x3
+#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4
+#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5
+#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL  0x6
+#define BV_PXP_OLnPARAM_ROP__NOT        0x7
+#define BV_PXP_OLnPARAM_ROP__NOTMASKOL  0x8
+#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9
+#define BV_PXP_OLnPARAM_ROP__XOROL      0xA
+#define BV_PXP_OLnPARAM_ROP__NOTXOROL   0xB
+#define BP_PXP_OLnPARAM_ALPHA      8
+#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
+#define BF_PXP_OLnPARAM_ALPHA(v)  \
+	(((v) << 8) & BM_PXP_OLnPARAM_ALPHA)
+#define BP_PXP_OLnPARAM_FORMAT      4
+#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
+#define BF_PXP_OLnPARAM_FORMAT(v)  \
+	(((v) << 4) & BM_PXP_OLnPARAM_FORMAT)
+#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0
+#define BV_PXP_OLnPARAM_FORMAT__RGB888   0x1
+#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3
+#define BV_PXP_OLnPARAM_FORMAT__RGB565   0x4
+#define BV_PXP_OLnPARAM_FORMAT__RGB555   0x5
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
+#define BP_PXP_OLnPARAM_ALPHA_CNTL      1
+#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
+#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)  \
+	(((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL)
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs     0x3
+#define BM_PXP_OLnPARAM_ENABLE 0x00000001
+
+/*
+ *  multi-register-define name HW_PXP_OLnPARAM2
+ *              base 0x00000230
+ *              count 8
+ *              offset 0x40
+ */
+#define HW_PXP_OLnPARAM2(n)	(0x00000230 + (n) * 0x40)
+#define BP_PXP_OLnPARAM2_RSVD      0
+#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF
+#define BF_PXP_OLnPARAM2_RSVD(v)   (v)
+
+#define HW_PXP_CSC2CTRL	(0x00000400)
+
+#define BP_PXP_CSC2CTRL_RSVD      3
+#define BM_PXP_CSC2CTRL_RSVD 0xFFFFFFF8
+#define BF_PXP_CSC2CTRL_RSVD(v) \
+	(((v) << 3) & BM_PXP_CSC2CTRL_RSVD)
+#define BP_PXP_CSC2CTRL_CSC_MODE      1
+#define BM_PXP_CSC2CTRL_CSC_MODE 0x00000006
+#define BF_PXP_CSC2CTRL_CSC_MODE(v)  \
+	(((v) << 1) & BM_PXP_CSC2CTRL_CSC_MODE)
+#define BV_PXP_CSC2CTRL_CSC_MODE__YUV2RGB   0x0
+#define BV_PXP_CSC2CTRL_CSC_MODE__YCbCr2RGB 0x1
+#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YUV   0x2
+#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YCbCr 0x3
+#define BM_PXP_CSC2CTRL_BYPASS 0x00000001
+
+#define HW_PXP_CSC2COEF0	(0x00000410)
+
+#define BP_PXP_CSC2COEF0_RSVD1      27
+#define BM_PXP_CSC2COEF0_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF0_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF0_RSVD1)
+#define BP_PXP_CSC2COEF0_A2      16
+#define BM_PXP_CSC2COEF0_A2 0x07FF0000
+#define BF_PXP_CSC2COEF0_A2(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF0_A2)
+#define BP_PXP_CSC2COEF0_RSVD0      11
+#define BM_PXP_CSC2COEF0_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF0_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF0_RSVD0)
+#define BP_PXP_CSC2COEF0_A1      0
+#define BM_PXP_CSC2COEF0_A1 0x000007FF
+#define BF_PXP_CSC2COEF0_A1(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF0_A1)
+
+#define HW_PXP_CSC2COEF1	(0x00000420)
+
+#define BP_PXP_CSC2COEF1_RSVD1      27
+#define BM_PXP_CSC2COEF1_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF1_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF1_RSVD1)
+#define BP_PXP_CSC2COEF1_B1      16
+#define BM_PXP_CSC2COEF1_B1 0x07FF0000
+#define BF_PXP_CSC2COEF1_B1(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF1_B1)
+#define BP_PXP_CSC2COEF1_RSVD0      11
+#define BM_PXP_CSC2COEF1_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF1_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF1_RSVD0)
+#define BP_PXP_CSC2COEF1_A3      0
+#define BM_PXP_CSC2COEF1_A3 0x000007FF
+#define BF_PXP_CSC2COEF1_A3(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF1_A3)
+
+#define HW_PXP_CSC2COEF2	(0x00000430)
+
+#define BP_PXP_CSC2COEF2_RSVD1      27
+#define BM_PXP_CSC2COEF2_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF2_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF2_RSVD1)
+#define BP_PXP_CSC2COEF2_B3      16
+#define BM_PXP_CSC2COEF2_B3 0x07FF0000
+#define BF_PXP_CSC2COEF2_B3(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF2_B3)
+#define BP_PXP_CSC2COEF2_RSVD0      11
+#define BM_PXP_CSC2COEF2_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF2_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF2_RSVD0)
+#define BP_PXP_CSC2COEF2_B2      0
+#define BM_PXP_CSC2COEF2_B2 0x000007FF
+#define BF_PXP_CSC2COEF2_B2(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF2_B2)
+
+#define HW_PXP_CSC2COEF3	(0x00000440)
+
+#define BP_PXP_CSC2COEF3_RSVD1      27
+#define BM_PXP_CSC2COEF3_RSVD1 0xF8000000
+#define BF_PXP_CSC2COEF3_RSVD1(v) \
+	(((v) << 27) & BM_PXP_CSC2COEF3_RSVD1)
+#define BP_PXP_CSC2COEF3_C2      16
+#define BM_PXP_CSC2COEF3_C2 0x07FF0000
+#define BF_PXP_CSC2COEF3_C2(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF3_C2)
+#define BP_PXP_CSC2COEF3_RSVD0      11
+#define BM_PXP_CSC2COEF3_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF3_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF3_RSVD0)
+#define BP_PXP_CSC2COEF3_C1      0
+#define BM_PXP_CSC2COEF3_C1 0x000007FF
+#define BF_PXP_CSC2COEF3_C1(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF3_C1)
+
+#define HW_PXP_CSC2COEF4	(0x00000450)
+
+#define BP_PXP_CSC2COEF4_RSVD1      25
+#define BM_PXP_CSC2COEF4_RSVD1 0xFE000000
+#define BF_PXP_CSC2COEF4_RSVD1(v) \
+	(((v) << 25) & BM_PXP_CSC2COEF4_RSVD1)
+#define BP_PXP_CSC2COEF4_D1      16
+#define BM_PXP_CSC2COEF4_D1 0x01FF0000
+#define BF_PXP_CSC2COEF4_D1(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF4_D1)
+#define BP_PXP_CSC2COEF4_RSVD0      11
+#define BM_PXP_CSC2COEF4_RSVD0 0x0000F800
+#define BF_PXP_CSC2COEF4_RSVD0(v)  \
+	(((v) << 11) & BM_PXP_CSC2COEF4_RSVD0)
+#define BP_PXP_CSC2COEF4_C3      0
+#define BM_PXP_CSC2COEF4_C3 0x000007FF
+#define BF_PXP_CSC2COEF4_C3(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF4_C3)
+
+#define HW_PXP_CSC2COEF5	(0x00000460)
+
+#define BP_PXP_CSC2COEF5_RSVD1      25
+#define BM_PXP_CSC2COEF5_RSVD1 0xFE000000
+#define BF_PXP_CSC2COEF5_RSVD1(v) \
+	(((v) << 25) & BM_PXP_CSC2COEF5_RSVD1)
+#define BP_PXP_CSC2COEF5_D3      16
+#define BM_PXP_CSC2COEF5_D3 0x01FF0000
+#define BF_PXP_CSC2COEF5_D3(v)  \
+	(((v) << 16) & BM_PXP_CSC2COEF5_D3)
+#define BP_PXP_CSC2COEF5_RSVD0      9
+#define BM_PXP_CSC2COEF5_RSVD0 0x0000FE00
+#define BF_PXP_CSC2COEF5_RSVD0(v)  \
+	(((v) << 9) & BM_PXP_CSC2COEF5_RSVD0)
+#define BP_PXP_CSC2COEF5_D2      0
+#define BM_PXP_CSC2COEF5_D2 0x000001FF
+#define BF_PXP_CSC2COEF5_D2(v)  \
+	(((v) << 0) & BM_PXP_CSC2COEF5_D2)
+
+#define HW_PXP_LUT_CTRL	(0x00000470)
+
+#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
+#define BP_PXP_LUT_CTRL_RSVD      8
+#define BM_PXP_LUT_CTRL_RSVD 0x7FFFFF00
+#define BF_PXP_LUT_CTRL_RSVD(v)  \
+	(((v) << 8) & BM_PXP_LUT_CTRL_RSVD)
+#define BP_PXP_LUT_CTRL_ADDR      0
+#define BM_PXP_LUT_CTRL_ADDR 0x000000FF
+#define BF_PXP_LUT_CTRL_ADDR(v)  \
+	(((v) << 0) & BM_PXP_LUT_CTRL_ADDR)
+
+#define HW_PXP_LUT	(0x00000480)
+
+#define BP_PXP_LUT_RSVD      8
+#define BM_PXP_LUT_RSVD 0xFFFFFF00
+#define BF_PXP_LUT_RSVD(v) \
+	(((v) << 8) & BM_PXP_LUT_RSVD)
+#define BP_PXP_LUT_DATA      0
+#define BM_PXP_LUT_DATA 0x000000FF
+#define BF_PXP_LUT_DATA(v)  \
+	(((v) << 0) & BM_PXP_LUT_DATA)
+
+#define HW_PXP_HIST_CTRL	(0x00000490)
+
+#define BP_PXP_HIST_CTRL_RSVD      6
+#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0
+#define BF_PXP_HIST_CTRL_RSVD(v) \
+	(((v) << 6) & BM_PXP_HIST_CTRL_RSVD)
+#define BP_PXP_HIST_CTRL_PANEL_MODE      4
+#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030
+#define BF_PXP_HIST_CTRL_PANEL_MODE(v)  \
+	(((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE)
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4  0x0
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8  0x1
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2
+#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3
+#define BP_PXP_HIST_CTRL_STATUS      0
+#define BM_PXP_HIST_CTRL_STATUS 0x0000000F
+#define BF_PXP_HIST_CTRL_STATUS(v)  \
+	(((v) << 0) & BM_PXP_HIST_CTRL_STATUS)
+
+#define HW_PXP_HIST2_PARAM	(0x000004a0)
+
+#define BP_PXP_HIST2_PARAM_RSVD      16
+#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000
+#define BF_PXP_HIST2_PARAM_RSVD(v) \
+	(((v) << 16) & BM_PXP_HIST2_PARAM_RSVD)
+#define BP_PXP_HIST2_PARAM_RSVD1      13
+#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000
+#define BF_PXP_HIST2_PARAM_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1)
+#define BP_PXP_HIST2_PARAM_VALUE1      8
+#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00
+#define BF_PXP_HIST2_PARAM_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1)
+#define BP_PXP_HIST2_PARAM_RSVD0      5
+#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0
+#define BF_PXP_HIST2_PARAM_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0)
+#define BP_PXP_HIST2_PARAM_VALUE0      0
+#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F
+#define BF_PXP_HIST2_PARAM_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0)
+
+#define HW_PXP_HIST4_PARAM	(0x000004b0)
+
+#define BP_PXP_HIST4_PARAM_RSVD3      29
+#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000
+#define BF_PXP_HIST4_PARAM_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3)
+#define BP_PXP_HIST4_PARAM_VALUE3      24
+#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000
+#define BF_PXP_HIST4_PARAM_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3)
+#define BP_PXP_HIST4_PARAM_RSVD2      21
+#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000
+#define BF_PXP_HIST4_PARAM_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2)
+#define BP_PXP_HIST4_PARAM_VALUE2      16
+#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000
+#define BF_PXP_HIST4_PARAM_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2)
+#define BP_PXP_HIST4_PARAM_RSVD1      13
+#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000
+#define BF_PXP_HIST4_PARAM_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1)
+#define BP_PXP_HIST4_PARAM_VALUE1      8
+#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00
+#define BF_PXP_HIST4_PARAM_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1)
+#define BP_PXP_HIST4_PARAM_RSVD0      5
+#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0
+#define BF_PXP_HIST4_PARAM_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0)
+#define BP_PXP_HIST4_PARAM_VALUE0      0
+#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F
+#define BF_PXP_HIST4_PARAM_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0)
+
+#define HW_PXP_HIST8_PARAM0	(0x000004c0)
+
+#define BP_PXP_HIST8_PARAM0_RSVD3      29
+#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000
+#define BF_PXP_HIST8_PARAM0_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3)
+#define BP_PXP_HIST8_PARAM0_VALUE3      24
+#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000
+#define BF_PXP_HIST8_PARAM0_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3)
+#define BP_PXP_HIST8_PARAM0_RSVD2      21
+#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000
+#define BF_PXP_HIST8_PARAM0_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2)
+#define BP_PXP_HIST8_PARAM0_VALUE2      16
+#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000
+#define BF_PXP_HIST8_PARAM0_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2)
+#define BP_PXP_HIST8_PARAM0_RSVD1      13
+#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000
+#define BF_PXP_HIST8_PARAM0_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1)
+#define BP_PXP_HIST8_PARAM0_VALUE1      8
+#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00
+#define BF_PXP_HIST8_PARAM0_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1)
+#define BP_PXP_HIST8_PARAM0_RSVD0      5
+#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0
+#define BF_PXP_HIST8_PARAM0_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0)
+#define BP_PXP_HIST8_PARAM0_VALUE0      0
+#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F
+#define BF_PXP_HIST8_PARAM0_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0)
+
+#define HW_PXP_HIST8_PARAM1	(0x000004d0)
+
+#define BP_PXP_HIST8_PARAM1_RSVD7      29
+#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000
+#define BF_PXP_HIST8_PARAM1_RSVD7(v) \
+	(((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7)
+#define BP_PXP_HIST8_PARAM1_VALUE7      24
+#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000
+#define BF_PXP_HIST8_PARAM1_VALUE7(v)  \
+	(((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7)
+#define BP_PXP_HIST8_PARAM1_RSVD6      21
+#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000
+#define BF_PXP_HIST8_PARAM1_RSVD6(v)  \
+	(((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6)
+#define BP_PXP_HIST8_PARAM1_VALUE6      16
+#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000
+#define BF_PXP_HIST8_PARAM1_VALUE6(v)  \
+	(((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6)
+#define BP_PXP_HIST8_PARAM1_RSVD5      13
+#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000
+#define BF_PXP_HIST8_PARAM1_RSVD5(v)  \
+	(((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5)
+#define BP_PXP_HIST8_PARAM1_VALUE5      8
+#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00
+#define BF_PXP_HIST8_PARAM1_VALUE5(v)  \
+	(((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5)
+#define BP_PXP_HIST8_PARAM1_RSVD4      5
+#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0
+#define BF_PXP_HIST8_PARAM1_RSVD4(v)  \
+	(((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4)
+#define BP_PXP_HIST8_PARAM1_VALUE4      0
+#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F
+#define BF_PXP_HIST8_PARAM1_VALUE4(v)  \
+	(((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4)
+
+#define HW_PXP_HIST16_PARAM0	(0x000004e0)
+
+#define BP_PXP_HIST16_PARAM0_RSVD3      29
+#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000
+#define BF_PXP_HIST16_PARAM0_RSVD3(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3)
+#define BP_PXP_HIST16_PARAM0_VALUE3      24
+#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000
+#define BF_PXP_HIST16_PARAM0_VALUE3(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3)
+#define BP_PXP_HIST16_PARAM0_RSVD2      21
+#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000
+#define BF_PXP_HIST16_PARAM0_RSVD2(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2)
+#define BP_PXP_HIST16_PARAM0_VALUE2      16
+#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000
+#define BF_PXP_HIST16_PARAM0_VALUE2(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2)
+#define BP_PXP_HIST16_PARAM0_RSVD1      13
+#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000
+#define BF_PXP_HIST16_PARAM0_RSVD1(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1)
+#define BP_PXP_HIST16_PARAM0_VALUE1      8
+#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00
+#define BF_PXP_HIST16_PARAM0_VALUE1(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1)
+#define BP_PXP_HIST16_PARAM0_RSVD0      5
+#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0
+#define BF_PXP_HIST16_PARAM0_RSVD0(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0)
+#define BP_PXP_HIST16_PARAM0_VALUE0      0
+#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F
+#define BF_PXP_HIST16_PARAM0_VALUE0(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0)
+
+#define HW_PXP_HIST16_PARAM1	(0x000004f0)
+
+#define BP_PXP_HIST16_PARAM1_RSVD7      29
+#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000
+#define BF_PXP_HIST16_PARAM1_RSVD7(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7)
+#define BP_PXP_HIST16_PARAM1_VALUE7      24
+#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000
+#define BF_PXP_HIST16_PARAM1_VALUE7(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7)
+#define BP_PXP_HIST16_PARAM1_RSVD6      21
+#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000
+#define BF_PXP_HIST16_PARAM1_RSVD6(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6)
+#define BP_PXP_HIST16_PARAM1_VALUE6      16
+#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000
+#define BF_PXP_HIST16_PARAM1_VALUE6(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6)
+#define BP_PXP_HIST16_PARAM1_RSVD5      13
+#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000
+#define BF_PXP_HIST16_PARAM1_RSVD5(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5)
+#define BP_PXP_HIST16_PARAM1_VALUE5      8
+#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00
+#define BF_PXP_HIST16_PARAM1_VALUE5(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5)
+#define BP_PXP_HIST16_PARAM1_RSVD4      5
+#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0
+#define BF_PXP_HIST16_PARAM1_RSVD4(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4)
+#define BP_PXP_HIST16_PARAM1_VALUE4      0
+#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F
+#define BF_PXP_HIST16_PARAM1_VALUE4(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4)
+
+#define HW_PXP_HIST16_PARAM2	(0x00000500)
+
+#define BP_PXP_HIST16_PARAM2_RSVD11      29
+#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000
+#define BF_PXP_HIST16_PARAM2_RSVD11(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11)
+#define BP_PXP_HIST16_PARAM2_VALUE11      24
+#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000
+#define BF_PXP_HIST16_PARAM2_VALUE11(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11)
+#define BP_PXP_HIST16_PARAM2_RSVD10      21
+#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000
+#define BF_PXP_HIST16_PARAM2_RSVD10(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10)
+#define BP_PXP_HIST16_PARAM2_VALUE10      16
+#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000
+#define BF_PXP_HIST16_PARAM2_VALUE10(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10)
+#define BP_PXP_HIST16_PARAM2_RSVD9      13
+#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000
+#define BF_PXP_HIST16_PARAM2_RSVD9(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9)
+#define BP_PXP_HIST16_PARAM2_VALUE9      8
+#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00
+#define BF_PXP_HIST16_PARAM2_VALUE9(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9)
+#define BP_PXP_HIST16_PARAM2_RSVD8      5
+#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0
+#define BF_PXP_HIST16_PARAM2_RSVD8(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8)
+#define BP_PXP_HIST16_PARAM2_VALUE8      0
+#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F
+#define BF_PXP_HIST16_PARAM2_VALUE8(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8)
+
+#define HW_PXP_HIST16_PARAM3	(0x00000510)
+
+#define BP_PXP_HIST16_PARAM3_RSVD15      29
+#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000
+#define BF_PXP_HIST16_PARAM3_RSVD15(v) \
+	(((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15)
+#define BP_PXP_HIST16_PARAM3_VALUE15      24
+#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000
+#define BF_PXP_HIST16_PARAM3_VALUE15(v)  \
+	(((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15)
+#define BP_PXP_HIST16_PARAM3_RSVD14      21
+#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000
+#define BF_PXP_HIST16_PARAM3_RSVD14(v)  \
+	(((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14)
+#define BP_PXP_HIST16_PARAM3_VALUE14      16
+#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000
+#define BF_PXP_HIST16_PARAM3_VALUE14(v)  \
+	(((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14)
+#define BP_PXP_HIST16_PARAM3_RSVD13      13
+#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000
+#define BF_PXP_HIST16_PARAM3_RSVD13(v)  \
+	(((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13)
+#define BP_PXP_HIST16_PARAM3_VALUE13      8
+#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00
+#define BF_PXP_HIST16_PARAM3_VALUE13(v)  \
+	(((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13)
+#define BP_PXP_HIST16_PARAM3_RSVD12      5
+#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0
+#define BF_PXP_HIST16_PARAM3_RSVD12(v)  \
+	(((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12)
+#define BP_PXP_HIST16_PARAM3_VALUE12      0
+#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F
+#define BF_PXP_HIST16_PARAM3_VALUE12(v)  \
+	(((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12)
+#endif /* __ARCH_ARM___PXP_H */
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 2d5016691d40..3477e689b7e8 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1026,4 +1026,14 @@ config HWMON_DEBUG_CHIP
 	  a problem with I2C support and want to see more of what is going
 	  on.
 
+config MXC_MMA7450
+	tristate "MMA7450 device driver"
+	depends on MACH_MX31_3DS || MACH_MX23EVK
+	default n
+
+config SENSORS_ISL29003
+	tristate "ISL29003 Light Sensor"
+	depends on MACH_MX37_3DS || MACH_MX51_3DS
+	default y
+
 endif # HWMON
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index b793dce6bed5..24368b04323b 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -88,7 +88,9 @@ obj-$(CONFIG_SENSORS_VT1211)	+= vt1211.o
 obj-$(CONFIG_SENSORS_VT8231)	+= vt8231.o
 obj-$(CONFIG_SENSORS_W83627EHF)	+= w83627ehf.o
 obj-$(CONFIG_SENSORS_W83L785TS)	+= w83l785ts.o
+obj-$(CONFIG_MXC_MMA7450)	+= mxc_mma7450.o
 obj-$(CONFIG_SENSORS_W83L786NG)	+= w83l786ng.o
+obj-$(CONFIG_SENSORS_ISL29003)	+= isl29003.o
 
 ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/hwmon/isl29003.c b/drivers/hwmon/isl29003.c
new file mode 100644
index 000000000000..9f1afe6faadb
--- /dev/null
+++ b/drivers/hwmon/isl29003.c
@@ -0,0 +1,438 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/hwmon/isl29003.c
+ *
+ * @brief ISL29003 light sensor Driver
+ *
+ * @ingroup
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+
+enum isl29003_width {
+	ISL29003_WIDTH_16 = 0,
+	ISL29003_WIDTH_12,
+	ISL29003_WIDTH_8,
+	ISL29003_WIDTH_4,
+};
+
+enum isl29003_gain {
+	ISL29003_GAIN_1000 = 0,
+	ISL29003_GAIN_4000,
+	ISL29003_GAIN_16000,
+	ISL29003_GAIN_64000,
+};
+
+enum isl29003_mode {
+	ISL29003_MODE_DIODE1 = 0,
+	ISL29003_MODE_DIODE2,
+	ISL29003_MODE_DIODE1_2,
+};
+
+struct isl29003_param {
+	enum isl29003_width width;
+	enum isl29003_gain gain;
+	enum isl29003_mode mode;
+};
+
+/* bit definition for ISL29003_CMD reg */
+#define ENABLE 7
+#define ADCPD 6
+#define TIMEING_MODE 5
+#define MODE 2
+#define WIDTH 0
+
+/* bit definition for ISL29003_CTRL reg */
+#define INT_FLAG 5
+#define GAIN 2
+#define INT_PERSIST 0
+
+enum isl29003_reg {
+	ISL29003_CMD = 0,
+	ISL29003_CTRL,
+	ISL29003_THRS_HI,
+	ISL29003_THRS_LO,
+	ISL29003_LSB_S,
+	ISL29003_MSB_S,
+	ISL29003_LSB_T,
+	ISL29003_MSB_T,
+	ISL29003_SYNC_IIC = 0x80,
+	ISL29003_CLAR_INT = 0x40
+};
+
+/* default configure for ISL29003 */
+#define ISL29003_WIDTH_DEFAULT ISL29003_WIDTH_16
+#define ISL29003_GAIN_DEFAULT ISL29003_GAIN_16000
+#define ISL29003_MODE_DEFAULT ISL29003_MODE_DIODE1
+
+/* range table for different GAIN settings */
+int range[4] = { 973, 3892, 15568, 62272 };
+
+/* width table for different WIDTH settings */
+int width[4] = { 16, 1, 256, 16 };
+
+struct isl29003_data {
+	struct i2c_client *client;
+	struct device *hwmon_dev;
+	struct regulator *vdd_reg;
+	struct isl29003_param param;
+	int lux_coeff;
+	unsigned char enable;
+};
+
+static struct i2c_client *isl29003_client;
+
+/*!
+ * This function do the isl29003 register read.
+ */
+int isl29003_read(struct i2c_client *client, u8 reg)
+{
+	return i2c_smbus_read_byte_data(client, reg);
+}
+
+/*!
+ * This function do the isl29003 register write.
+ */
+int isl29003_write(struct i2c_client *client, u8 reg, char value)
+{
+	return i2c_smbus_write_byte_data(client, reg, value);
+}
+
+/*!
+ * This function do the isl29003 config and enable.
+ */
+static int isl29003_on(void)
+{
+	unsigned char cmd;
+	int err = 0;
+	struct mxc_lightsensor_platform_data *ls_data;
+	struct isl29003_data *data = i2c_get_clientdata(isl29003_client);
+
+	if (data->enable)
+		goto exit;
+
+	ls_data = (struct mxc_lightsensor_platform_data *)
+	    (isl29003_client->dev).platform_data;
+
+	/* coeff=range*100k/rext/2^n */
+	data->lux_coeff = range[data->param.gain] * 100 /
+	    ls_data->rext / width[data->param.width];
+
+	if (data->vdd_reg)
+		regulator_enable(data->vdd_reg);
+	msleep(100);
+
+	cmd = data->param.gain << GAIN;
+	if (isl29003_write(isl29003_client, ISL29003_CTRL, cmd)) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	cmd = (data->param.width << WIDTH) | (data->param.mode << MODE) |
+	    (1 << ENABLE);
+	if (isl29003_write(isl29003_client, ISL29003_CMD, cmd)) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	data->enable = 1;
+
+	pr_info("isl29003 on\n");
+	return 0;
+exit:
+	return err;
+}
+
+/*!
+ * This function shut down the isl29003.
+ */
+static int isl29003_off(void)
+{
+	struct isl29003_data *data = i2c_get_clientdata(isl29003_client);
+	int cmd;
+
+	if (!data->enable)
+		return 0;
+
+	cmd = isl29003_read(isl29003_client, ISL29003_CMD);
+	if (cmd < 0)
+		return -ENODEV;
+
+	cmd = ((cmd | (1 << ADCPD)) & (~(1 << ENABLE)));
+	if (isl29003_write(isl29003_client, ISL29003_CMD, (char)cmd))
+		return -ENODEV;
+
+	if (data->vdd_reg)
+		regulator_disable(data->vdd_reg);
+
+	data->enable = 0;
+
+	pr_info("isl29003 off\n");
+	return 0;
+}
+
+/*!
+ * This function read the isl29003 lux registers and convert them to the lux
+ * value.
+ *
+ * @output buffer	this param holds the lux value, when =-1, read fail
+ *
+ * @return 0
+ */
+static int isl29003_read_lux(void)
+{
+	int d;
+	int lux;
+	struct isl29003_data *data = i2c_get_clientdata(isl29003_client);
+
+	d = isl29003_read(isl29003_client, ISL29003_MSB_S);
+	if (d < 0)
+		goto err;
+
+	lux = d;
+	d = isl29003_read(isl29003_client, ISL29003_LSB_S);
+	if (d < 0)
+		goto err;
+
+	lux = (lux << 8) + d;
+
+	if (data->param.width < ISL29003_WIDTH_8)
+		lux = (data->lux_coeff * lux) >> 12;
+	else
+		lux = data->lux_coeff * lux;
+
+	return lux;
+err:
+	return -1;
+}
+
+static ssize_t ls_enable(struct device *dev, struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+	char *endp;
+	int enable = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	if (enable == 1) {
+		if (isl29003_on())
+			pr_info("device open fail\n");
+	}
+	if (enable == 0) {
+		if (isl29003_off())
+			pr_info("device powerdown fail\n");
+	}
+
+	return count;
+}
+
+static SENSOR_DEVICE_ATTR(enable, S_IWUGO, NULL, ls_enable, 0);
+
+static ssize_t show_lux(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%u\n", isl29003_read_lux());
+}
+
+static SENSOR_DEVICE_ATTR(lux, S_IRUGO, show_lux, NULL, 0);
+
+static int isl29003_i2c_probe(struct i2c_client *client,
+			      const struct i2c_device_id *did)
+{
+	int err = 0;
+	struct isl29003_data *data;
+	struct regulator *vdd_reg;
+	struct mxc_lightsensor_platform_data *ls_data;
+
+	ls_data = (struct mxc_lightsensor_platform_data *)
+	    (client->dev).platform_data;
+
+	if (ls_data && ls_data->vdd_reg)
+		vdd_reg = regulator_get(&client->dev, ls_data->vdd_reg);
+	else
+		vdd_reg = NULL;
+
+	/* check the existence of the device */
+	if (vdd_reg)
+		regulator_enable(vdd_reg);
+	msleep(100);
+
+	if (isl29003_write(client, ISL29003_CMD, 0))
+		err = -ENODEV;
+
+	if (!err)
+		if (isl29003_read(client, ISL29003_CMD))
+			err = -ENODEV;
+
+	if (vdd_reg)
+		regulator_disable(vdd_reg);
+	if (err < 0)
+		goto exit1;
+
+	isl29003_client = client;
+	data = kzalloc(sizeof(struct isl29003_data), GFP_KERNEL);
+	if (data == NULL) {
+		err = -ENOMEM;
+		goto exit1;
+	}
+
+	i2c_set_clientdata(client, data);
+	data->client = client;
+
+	data->param.width = ISL29003_WIDTH_DEFAULT;
+	data->param.gain = ISL29003_GAIN_DEFAULT;
+	data->param.mode = ISL29003_MODE_DEFAULT;
+
+	data->enable = 0;
+
+	err = device_create_file(&client->dev,
+				 &sensor_dev_attr_enable.dev_attr);
+	if (err)
+		goto exit2;
+
+	err = device_create_file(&client->dev, &sensor_dev_attr_lux.dev_attr);
+	if (err)
+		goto exit_remove1;
+
+	/* Register sysfs hooks */
+	data->hwmon_dev = hwmon_device_register(&client->dev);
+	if (IS_ERR(data->hwmon_dev)) {
+		err = PTR_ERR(data->hwmon_dev);
+		goto exit_remove2;
+	}
+
+	data->vdd_reg = vdd_reg;
+	return 0;
+
+exit_remove2:
+	device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr);
+exit_remove1:
+	device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr);
+exit2:
+	kfree(data);
+exit1:
+	if (vdd_reg) {
+		regulator_put(vdd_reg);
+		vdd_reg = NULL;
+	}
+	isl29003_client = NULL;
+	return err;
+}
+
+static int isl29003_i2c_remove(struct i2c_client *client)
+{
+	struct isl29003_data *data = i2c_get_clientdata(client);
+
+	if (data->vdd_reg) {
+		regulator_put(data->vdd_reg);
+		data->vdd_reg = NULL;
+	}
+	hwmon_device_unregister(data->hwmon_dev);
+	device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr);
+	device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr);
+	kfree(data);
+	return 0;
+}
+
+static int isl29003_suspend(struct i2c_client *client, pm_message_t message)
+{
+	int cmd;
+
+	struct isl29003_data *data = i2c_get_clientdata(client);
+
+	if (!data->enable)
+		goto exit;
+
+	cmd = isl29003_read(client, ISL29003_CMD);
+	if (cmd < 0)
+		goto err;
+
+	cmd = (cmd | (1 << ADCPD));
+	if (isl29003_write(client, ISL29003_CMD, (char)cmd))
+		goto err;
+exit:
+	return 0;
+err:
+	return -ENODEV;
+}
+
+static int isl29003_resume(struct i2c_client *client)
+{
+	int cmd;
+
+	struct isl29003_data *data = i2c_get_clientdata(client);
+
+	if (!data->enable)
+		goto exit;
+
+	cmd = isl29003_read(client, ISL29003_CMD);
+	if (cmd < 0)
+		goto err;
+
+	cmd = (cmd & (~(1 << ADCPD)));
+	if (isl29003_write(client, ISL29003_CMD, (char)cmd))
+		goto err;
+exit:
+	return 0;
+err:
+	return -ENODEV;
+}
+
+static const struct i2c_device_id isl29003_id[] = {
+	{"isl29003", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(i2c, isl29003_id);
+
+static struct i2c_driver isl29003_driver = {
+	.driver = {
+		   .name = "isl29003",
+		   },
+	.probe = isl29003_i2c_probe,
+	.remove = isl29003_i2c_remove,
+	.suspend = isl29003_suspend,
+	.resume = isl29003_resume,
+	.id_table = isl29003_id,
+};
+
+static int __init isl29003_init(void)
+{
+	return i2c_add_driver(&isl29003_driver);;
+}
+
+static void __exit isl29003_cleanup(void)
+{
+	i2c_del_driver(&isl29003_driver);
+}
+
+module_init(isl29003_init);
+module_exit(isl29003_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("ISL29003 light sensor driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/mxc_mma7450.c b/drivers/hwmon/mxc_mma7450.c
new file mode 100644
index 000000000000..2ee23200a909
--- /dev/null
+++ b/drivers/hwmon/mxc_mma7450.c
@@ -0,0 +1,788 @@
+/*
+ * linux/drivers/hwmon/mma7450.c
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*include file*/
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/input-polldev.h>
+#include <linux/hwmon.h>
+#include <linux/regulator/consumer.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <mach/hardware.h>
+
+/*macro define*/
+#define MMA7450_I2C_ADDR	0x1D
+#define DEVICE_NAME		"mma7450"
+#define POLL_INTERVAL		100
+#define DEBUG
+
+#define INPUT_FUZZ	4
+#define INPUT_FLAT	4
+
+enum {
+	REG_XOUTL = 0x00,
+	REG_XOUTH,
+	REG_YOUTL,
+	REG_YOUTH,
+	REG_ZOUTL,
+	REG_ZOUTH,
+	REG_XOUT8,
+	REG_YOUT8,
+	REG_ZOUT8,
+	REG_STATUS,
+	REG_DETSRC,
+	REG_TOUT,
+	REG_RESERVED_0,
+	REG_I2CAD,
+	REG_USRINF,
+	REG_WHOAMI,
+	REG_XOFFL,
+	REG_XOFFH,
+	REG_YOFFL,
+	REG_YOFFH,
+	REG_ZOFFL,
+	REG_ZOFFH,
+	REG_MCTL,
+	REG_INTRST,
+	REG_CTL1,
+	REG_CTL2,
+	REG_LDTH,
+	REG_PDTH,
+	REG_PD,
+	REG_LT,
+	REG_TW,
+	REG_REVERVED_1,
+};
+
+enum {
+	MOD_STANDBY = 0,
+	MOD_MEASURE,
+	MOD_LEVEL_D,
+	MOD_PULSE_D,
+};
+
+enum {
+	INT_1L_2P = 0,
+	INT_1P_2L,
+	INT_1SP_2P,
+};
+
+struct mma7450_status {
+	u8 mod;
+	u8 ctl1;
+	u8 ctl2;
+};
+
+/*forward declear*/
+static ssize_t mma7450_show(struct device *dev,
+			    struct device_attribute *attr, char *buf);
+static ssize_t mma7450_store(struct device *dev,
+			     struct device_attribute *attr, const char *buf,
+			     size_t count);
+static int mma7450_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id);
+static int mma7450_remove(struct i2c_client *client);
+static int mma7450_suspend(struct i2c_client *client, pm_message_t state);
+static int mma7450_resume(struct i2c_client *client);
+static void mma_bh_handler(struct work_struct *work);
+
+/*definition*/
+static struct regulator *reg_dvdd_io;
+static struct regulator *reg_avdd;
+static struct i2c_client *mma7450_client;
+static struct device *hwmon_dev;
+static struct input_polled_dev *mma7450_idev;
+static struct mxc_mma7450_platform_data *plat_data;
+static u8 mma7450_mode;
+static struct device_attribute mma7450_dev_attr = {
+	.attr = {
+		 .name = "mma7450_ctl",
+		 .mode = S_IRUSR | S_IWUSR,
+		 },
+	.show = mma7450_show,
+	.store = mma7450_store,
+};
+
+static const struct i2c_device_id mma7450_id[] = {
+	{"mma7450", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, mma7450_id);
+
+static struct i2c_driver i2c_mma7450_driver = {
+	.driver = {
+		   .name = "mma7450",
+		   },
+	.probe = mma7450_probe,
+	.remove = mma7450_remove,
+	.suspend = mma7450_suspend,
+	.resume = mma7450_resume,
+	.id_table = mma7450_id,
+};
+
+static struct mma7450_status mma_status = {
+	.mod = 0,
+	.ctl1 = 0,
+	.ctl2 = 0,
+};
+
+DECLARE_WORK(mma_work, mma_bh_handler);
+
+#ifdef DEBUG
+enum {
+	MMA_REG_R = 0,
+	MMA_REG_W,
+	MMA_SET_MOD,
+	MMA_SET_L_THR,
+	MMA_SET_P_THR,
+	MMA_SET_INTP,
+	MMA_SET_INTB,
+	MMA_SET_G,
+	MMA_I2C_EABLE,
+	MMA_OFF_X,
+	MMA_OFF_Y,
+	MMA_OFF_Z,
+	MMA_SELF_TEST,
+	MMA_SET_LDPL,
+	MMA_SET_PDPL,
+	MMA_SET_PDV,
+	MMA_SET_LTV,
+	MMA_SET_TW,
+	MMA_CMD_MAX
+};
+
+static char *command[MMA_CMD_MAX] = {
+	[MMA_REG_R] = "readreg",
+	[MMA_REG_W] = "writereg",
+	[MMA_SET_MOD] = "setmod",
+	[MMA_SET_L_THR] = "setlt",
+	[MMA_SET_P_THR] = "setpt",
+	[MMA_SET_INTP] = "setintp",
+	[MMA_SET_INTB] = "setintb",
+	[MMA_SET_G] = "setg",
+	[MMA_I2C_EABLE] = "setie",
+	[MMA_OFF_X] = "setxo",
+	[MMA_OFF_Y] = "setyo",
+	[MMA_OFF_Z] = "setzo",
+	[MMA_SELF_TEST] = "selft",
+	[MMA_SET_LDPL] = "setldp",
+	[MMA_SET_PDPL] = "setpdp",
+	[MMA_SET_PDV] = "setpdv",
+	[MMA_SET_LTV] = "setltv",
+	[MMA_SET_TW] = "settw",
+};
+
+static void set_mod(u8 mode)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL);
+	/* shall I test the ret value? */
+	ret = (ret & ~0x3) | (mode & 0x3);
+	mma_status.mod = ret;
+	i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret);
+}
+
+static void set_level_thr(u8 lth)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_LDTH, lth);
+}
+
+static void set_pulse_thr(u8 pth)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_PDTH, pth);
+}
+
+static void set_int_pin(u8 pin)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1);
+	ret = (ret & ~0x1) | (pin & 0x1);
+	mma_status.ctl1 = ret;
+	i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret);
+}
+
+static void set_int_bit(u8 bit)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1);
+	ret = (ret & ~0x6) | ((bit << 1) & 0x6);
+	mma_status.ctl1 = ret;
+	i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret);
+}
+
+static void set_g_level(u8 gl)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL);
+	ret = (ret & ~0xC) | ((gl << 2) & 0xC);
+	i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret);
+}
+
+static void set_i2c_enable(u8 i2c_e)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_I2CAD);
+	ret = (ret & ~0x80) | ((i2c_e << 7) & 0x80);
+	i2c_smbus_write_byte_data(mma7450_client, REG_I2CAD, ret);
+}
+
+static void set_x_offset(u16 xo)
+{
+	u8 data;
+
+	data = (xo & 0xFF);
+	i2c_smbus_write_byte_data(mma7450_client, REG_XOFFL, data);
+	data = (xo & 0xFF00) >> 8;
+	i2c_smbus_write_byte_data(mma7450_client, REG_XOFFH, data);
+}
+
+static void set_y_offset(u16 yo)
+{
+	u8 data;
+
+	data = (yo & 0xFF);
+	i2c_smbus_write_byte_data(mma7450_client, REG_YOFFL, data);
+	data = (yo & 0xFF00) >> 8;
+	i2c_smbus_write_byte_data(mma7450_client, REG_YOFFH, data);
+}
+
+static void set_z_offset(u16 zo)
+{
+	u8 data;
+
+	data = (zo & 0xFF);
+	i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFL, data);
+	data = (zo & 0xFF00) >> 8;
+	i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFH, data);
+}
+
+static void selftest(u8 st)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL);
+	ret = (ret & ~0x10) | ((st << 4) & 0x10);
+	i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret);
+}
+
+static void set_level_det_p(u8 ldp)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2);
+	ret = (ret & ~0x1) | ((ldp << 0) & 0x1);
+	mma_status.ctl2 = ret;
+	i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret);
+}
+
+static void set_pulse_det_p(u8 pdp)
+{
+	int ret;
+
+	ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2);
+	ret = (ret & ~0x2) | ((pdp << 1) & 0x2);
+	mma_status.ctl2 = ret;
+	i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret);
+}
+
+static void set_pulse_duration(u8 pd)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_PD, pd);
+}
+
+static void set_latency_time(u8 lt)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_LT, lt);
+}
+
+static void set_time_window(u8 tw)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_TW, tw);
+}
+
+static void parse_arg(const char *arg, int *reg, int *value)
+{
+	const char *p;
+
+	for (p = arg;; p++) {
+		if (*p == ' ' || *p == '\0')
+			break;
+	}
+
+	p++;
+
+	*reg = simple_strtoul(arg, NULL, 16);
+	*value = simple_strtoul(p, NULL, 16);
+}
+
+static void cmd_read_reg(const char *arg)
+{
+	int reg, value, ret;
+
+	parse_arg(arg, &reg, &value);
+	ret = i2c_smbus_read_byte_data(mma7450_client, reg);
+	dev_info(&mma7450_client->dev, "read reg0x%x = %x\n", reg, ret);
+}
+
+static void cmd_write_reg(const char *arg)
+{
+	int reg, value, ret;
+
+	parse_arg(arg, &reg, &value);
+	ret = i2c_smbus_write_byte_data(mma7450_client, reg, value);
+	dev_info(&mma7450_client->dev, "write reg result %s\n",
+		 ret ? "failed" : "success");
+}
+
+static int exec_command(const char *buf, size_t count)
+{
+	const char *p, *s;
+	const char *arg;
+	int i, value = 0;
+
+	for (p = buf;; p++) {
+		if (*p == ' ' || *p == '\0' || p - buf >= count)
+			break;
+	}
+	arg = p + 1;
+
+	for (i = MMA_REG_R; i < MMA_CMD_MAX; i++) {
+		s = command[i];
+		if (s && !strncmp(buf, s, p - buf)) {
+			dev_info(&mma7450_client->dev, "command %s\n", s);
+			goto mma_exec_command;
+		}
+	}
+
+	dev_err(&mma7450_client->dev, "command is not found\n");
+	return -1;
+
+      mma_exec_command:
+	if (i != MMA_REG_R && i != MMA_REG_W)
+		value = simple_strtoul(arg, NULL, 16);
+
+	switch (i) {
+	case MMA_REG_R:
+		cmd_read_reg(arg);
+		break;
+	case MMA_REG_W:
+		cmd_write_reg(arg);
+		break;
+	case MMA_SET_MOD:
+		set_mod(value);
+		break;
+	case MMA_SET_L_THR:
+		set_level_thr(value);
+		break;
+	case MMA_SET_P_THR:
+		set_pulse_thr(value);
+		break;
+	case MMA_SET_INTP:
+		set_int_pin(value);
+		break;
+	case MMA_SET_INTB:
+		set_int_bit(value);
+		break;
+	case MMA_SET_G:
+		set_g_level(value);
+		break;
+	case MMA_I2C_EABLE:
+		set_i2c_enable(value);
+		break;
+	case MMA_OFF_X:
+		set_x_offset(value);
+		break;
+	case MMA_OFF_Y:
+		set_y_offset(value);
+		break;
+	case MMA_OFF_Z:
+		set_z_offset(value);
+		break;
+	case MMA_SELF_TEST:
+		selftest(value);
+		break;
+	case MMA_SET_LDPL:
+		set_level_det_p(value);
+		break;
+	case MMA_SET_PDPL:
+		set_pulse_det_p(value);
+		break;
+	case MMA_SET_PDV:
+		set_pulse_duration(value);
+		break;
+	case MMA_SET_LTV:
+		set_latency_time(value);
+		break;
+	case MMA_SET_TW:
+		set_time_window(value);
+		break;
+	default:
+		dev_err(&mma7450_client->dev, "command is not found\n");
+		break;
+	}
+
+	return 0;
+}
+
+static ssize_t mma7450_show(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	int ret, reg;
+
+	for (reg = REG_XOUTL; reg < REG_REVERVED_1; reg++) {
+		ret = i2c_smbus_read_byte_data(mma7450_client, reg);
+		dev_info(&mma7450_client->dev, "reg0x%02x:\t%03d\t0x%02x\n",
+			 reg, (s8) ret, ret);
+	}
+
+	return 0;
+}
+
+static ssize_t mma7450_store(struct device *dev,
+			     struct device_attribute *attr, const char *buf,
+			     size_t count)
+{
+	exec_command(buf, count);
+
+	return count;
+}
+
+#else
+
+static ssize_t mma7450_show(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	return 0;
+}
+
+static ssize_t mma7450_store(struct device *dev,
+			     struct device_attribute *attr, const char *buf,
+			     size_t count)
+{
+	return count;
+}
+
+#endif
+
+static void report_abs(void)
+{
+	u8 status, mod = mma_status.mod;
+	s16 x, y, z;
+
+	status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS);
+	if (!(status & 0x01)) {	/* data ready in measurement mode? */
+		return;
+	}
+	if ((mod & 0x0c) == 0) {	/* 8g range */
+		x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUTL);
+		x |= 0xFF00 &
+		    (i2c_smbus_read_byte_data(mma7450_client, REG_XOUTH) << 8);
+		y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUTL);
+		y |= 0xFF00 &
+		    (i2c_smbus_read_byte_data(mma7450_client, REG_YOUTH) << 8);
+		z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTL);
+		z |= 0xFF00 &
+		    (i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTH) << 8);
+	} else {		/* 2g/4g range */
+		x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUT8);
+		y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUT8);
+		z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUT8);
+	}
+
+	status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS);
+	if (status & 0x02) {	/* data is overwrite */
+		return;
+	}
+
+	/* convert signed 10bits to signed 16bits */
+	x = (short)(x << 6) >> 6;
+	y = (short)(y << 6) >> 6;
+	z = (short)(z << 6) >> 6;
+
+	input_report_abs(mma7450_idev->input, ABS_X, x);
+	input_report_abs(mma7450_idev->input, ABS_Y, y);
+	input_report_abs(mma7450_idev->input, ABS_Z, z);
+	input_sync(mma7450_idev->input);
+}
+
+static void mma_bh_handler(struct work_struct *work)
+{
+}
+
+static void mma7450_dev_poll(struct input_polled_dev *dev)
+{
+	report_abs();
+}
+
+static irqreturn_t mma7450_interrupt(int irq, void *dev_id)
+{
+	struct input_dev *input_dev = dev_id;
+	u8 int_bit, int_pin;
+
+	int_bit = mma_status.ctl1 & 0x6;
+	int_pin = mma_status.ctl1 & 0x1;
+
+	switch (mma_status.mod & 0x03) {
+	case 1:
+		/*only int1 report data ready int */
+		if (plat_data->int1 != irq)
+			goto error_bad_int;
+		schedule_work(&mma_work);
+		break;
+	case 2:
+		/* for level and pulse detection mode,
+		 * choice tasklet to handle interrupt quickly.
+		 * Currently, leave it doing nothing*/
+		if (plat_data->int1 == irq) {
+			if ((int_bit == 0) && (int_pin != 0))
+				goto error_bad_int;
+			if ((int_bit == 0x2) && (int_pin != 0x1))
+				goto error_bad_int;
+			if (int_bit == 0x4)
+				goto error_bad_int;
+		}
+		if (plat_data->int2 == irq) {
+			if ((int_bit == 0) && (int_pin != 0x1))
+				goto error_bad_int;
+			if ((int_bit == 0x2) && (int_pin != 0))
+				goto error_bad_int;
+			if (int_bit == 0x4)
+				goto error_bad_int;
+		}
+
+		dev_info(&input_dev->dev, "motion detected in level mod\n");
+
+		break;
+	case 3:
+		if (plat_data->int1 == irq) {
+			if ((int_bit == 0) && (int_pin != 0x1))
+				goto error_bad_int;
+			if ((int_bit == 0x2) && (int_pin != 0))
+				goto error_bad_int;
+			if ((int_bit == 0x4) && (int_pin != 0x1))
+				goto error_bad_int;
+		}
+		if (plat_data->int2 == irq) {
+			if ((int_bit == 0) && (int_pin != 0))
+				goto error_bad_int;
+			if ((int_bit == 0x2) && (int_pin != 0x1))
+				goto error_bad_int;
+			if ((int_bit == 0x4) && (int_pin != 0))
+				goto error_bad_int;
+		}
+
+		if (mma_status.ctl2 & 0x02)
+			dev_info(&input_dev->dev,
+				 "freefall detected in pulse mod\n");
+		else
+			dev_info(&input_dev->dev,
+				 "motion detected in pulse mod\n");
+
+		break;
+	case 0:
+	default:
+		break;
+	}
+      error_bad_int:
+	return IRQ_RETVAL(1);
+}
+
+static int mma7450_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	int ret;
+	struct input_dev *idev;
+
+	plat_data =
+	    (struct mxc_mma7450_platform_data *)client->dev.platform_data;
+	if (plat_data == NULL) {
+		dev_err(&client->dev, "lack of platform data!\n");
+		return -ENODEV;
+	}
+
+	/*enable power supply */
+	/*when to power on/off the power is to be considered later */
+	/*shall I check the return value */
+	reg_dvdd_io = regulator_get(&client->dev, plat_data->reg_dvdd_io);
+	if (reg_dvdd_io != ERR_PTR(-ENOENT))
+		regulator_enable(reg_dvdd_io);
+	else
+		return -EINVAL;
+
+	reg_avdd = regulator_get(&client->dev, plat_data->reg_avdd);
+	if (reg_avdd != ERR_PTR(-ENOENT))
+		regulator_enable(reg_avdd);
+	else {
+		regulator_put(reg_dvdd_io);
+		return -EINVAL;
+	}
+
+	/*bind the right device to the driver */
+	ret = i2c_smbus_read_byte_data(client, REG_I2CAD);
+	if (MMA7450_I2C_ADDR != (0x7F & ret)) {	/*compare the address value */
+		dev_err(&client->dev,
+			"read chip ID 0x%x is not equal to 0x%x!\n", ret,
+			MMA7450_I2C_ADDR);
+		goto error_disable_power;
+	}
+	mma7450_client = client;
+
+	/*interrupt register */
+	/*when to register interrupt is to be considered later */
+
+	/*create device file in sysfs as user interface */
+	ret = device_create_file(&client->dev, &mma7450_dev_attr);
+	if (ret) {
+		dev_err(&client->dev, "create device file failed!\n");
+		goto error_disable_power;
+	}
+
+	/*register to hwmon device */
+	hwmon_dev = hwmon_device_register(&client->dev);
+	if (IS_ERR(hwmon_dev)) {
+		dev_err(&client->dev, "hwmon register failed!\n");
+		ret = PTR_ERR(hwmon_dev);
+		goto error_rm_dev_file;
+	}
+
+	/*input poll device register */
+	mma7450_idev = input_allocate_polled_device();
+	if (!mma7450_idev) {
+		dev_err(&client->dev, "alloc poll device failed!\n");
+		ret = -ENOMEM;
+		goto error_rm_hwmon_dev;
+	}
+	mma7450_idev->poll = mma7450_dev_poll;
+	mma7450_idev->poll_interval = POLL_INTERVAL;
+	idev = mma7450_idev->input;
+	idev->name = DEVICE_NAME;
+	idev->id.bustype = BUS_I2C;
+	idev->dev.parent = &client->dev;
+	idev->evbit[0] = BIT_MASK(EV_ABS);
+
+	input_set_abs_params(idev, ABS_X, -512, 512, INPUT_FUZZ, INPUT_FLAT);
+	input_set_abs_params(idev, ABS_Y, -512, 512, INPUT_FUZZ, INPUT_FLAT);
+	input_set_abs_params(idev, ABS_Z, -512, 512, INPUT_FUZZ, INPUT_FLAT);
+	ret = input_register_polled_device(mma7450_idev);
+	if (ret) {
+		dev_err(&client->dev, "register poll device failed!\n");
+		goto error_free_poll_dev;
+	}
+
+	/* configure gpio as input for interrupt monitor */
+	plat_data->gpio_pin_get();
+
+	set_irq_type(plat_data->int1, IRQF_TRIGGER_RISING);
+	/* register interrupt handle */
+	ret = request_irq(plat_data->int1, mma7450_interrupt,
+			  IRQF_TRIGGER_RISING, DEVICE_NAME, idev);
+
+	if (ret) {
+		dev_err(&client->dev, "request_irq(%d) returned error %d\n",
+			plat_data->int1, ret);
+		goto error_rm_poll_dev;
+	}
+
+	set_irq_type(plat_data->int2, IRQF_TRIGGER_RISING);
+	ret = request_irq(plat_data->int2, mma7450_interrupt,
+			  IRQF_TRIGGER_RISING, DEVICE_NAME, idev);
+	if (ret) {
+		dev_err(&client->dev, "request_irq(%d) returned error %d\n",
+			plat_data->int2, ret);
+		goto error_free_irq1;
+	}
+
+	dev_info(&client->dev, "mma7450 device is probed successfully.\n");
+
+	set_mod(1);
+	return 0;		/*what value shall be return */
+
+	/*error handle */
+      error_free_irq1:
+	free_irq(plat_data->int1, 0);
+      error_rm_poll_dev:
+	input_unregister_polled_device(mma7450_idev);
+      error_free_poll_dev:
+	input_free_polled_device(mma7450_idev);
+      error_rm_hwmon_dev:
+	hwmon_device_unregister(hwmon_dev);
+      error_rm_dev_file:
+	device_remove_file(&client->dev, &mma7450_dev_attr);
+      error_disable_power:
+	regulator_disable(reg_dvdd_io);	/*shall I check the return value */
+	regulator_disable(reg_avdd);
+	regulator_put(reg_dvdd_io);
+	regulator_put(reg_avdd);
+
+	return ret;
+}
+
+static int mma7450_remove(struct i2c_client *client)
+{
+	free_irq(plat_data->int2, mma7450_idev->input);
+	free_irq(plat_data->int1, mma7450_idev->input);
+	plat_data->gpio_pin_put();
+	input_unregister_polled_device(mma7450_idev);
+	input_free_polled_device(mma7450_idev);
+	hwmon_device_unregister(hwmon_dev);
+	device_remove_file(&client->dev, &mma7450_dev_attr);
+	regulator_disable(reg_dvdd_io);	/*shall I check the return value */
+	regulator_disable(reg_avdd);
+	regulator_put(reg_dvdd_io);
+	regulator_put(reg_avdd);
+	return 0;
+}
+
+static int mma7450_suspend(struct i2c_client *client, pm_message_t state)
+{
+	mma7450_mode = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL);
+	i2c_smbus_write_byte_data(mma7450_client, REG_MCTL,
+				  mma7450_mode & ~0x3);
+	return 0;
+}
+
+static int mma7450_resume(struct i2c_client *client)
+{
+	i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, mma7450_mode);
+	return 0;
+}
+
+static int __init init_mma7450(void)
+{
+	/*register driver */
+	printk(KERN_INFO "add mma i2c driver\n");
+	return i2c_add_driver(&i2c_mma7450_driver);
+}
+
+static void __exit exit_mma7450(void)
+{
+	printk(KERN_INFO "del mma i2c driver.\n");
+	return i2c_del_driver(&i2c_mma7450_driver);
+}
+
+module_init(init_mma7450);
+module_exit(exit_mma7450);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MMA7450 sensor driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c-slave/Kconfig b/drivers/i2c-slave/Kconfig
new file mode 100644
index 000000000000..89717e15e784
--- /dev/null
+++ b/drivers/i2c-slave/Kconfig
@@ -0,0 +1,39 @@
+#
+# I2C slave subsystem configuration
+#
+
+menuconfig I2C_SLAVE
+	bool "I2C Slave support"
+	depends on HAS_IOMEM
+	---help---
+	  I2C (pronounce: I-square-C) is a slow serial bus protocol used in
+	  many micro controller applications and developed by Philips.
+
+	  If you want I2C Slave support, you should say Y here.
+
+	  This I2C Slave support can also be built as a module.  If so, the module
+	  will be called i2c-slave.
+
+if I2C_SLAVE
+
+config I2C_SLAVE_CORE
+	tristate "I2C SLAVE CORE"
+	default y
+	---help---
+		i2c slave core.
+
+config MXC_I2C_SLAVE
+	tristate "MXC I2C SLAVE"
+	depends on I2C_SLAVE_CORE
+	default y
+	---help---
+		mxc i2c slave support.
+
+config I2C_SLAVE_CLIENT
+	tristate "I2C SLAVE CLIENT"
+	default y
+	---help---
+		i2c slave client that used when the master is on the same board.
+		this is for i2c master which is on the same board with the slave.
+
+endif # I2C_SLAVE
diff --git a/drivers/i2c-slave/Makefile b/drivers/i2c-slave/Makefile
new file mode 100644
index 000000000000..a7b08c919af9
--- /dev/null
+++ b/drivers/i2c-slave/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the i2c slave.
+#
+
+i2c_slave-objs := i2c_slave_ring_buffer.o i2c_slave_device.o i2c_slave_core.o
+obj-$(CONFIG_I2C_SLAVE_CORE)	+= i2c_slave.o
+obj-$(CONFIG_MXC_I2C_SLAVE)		+= mxc_i2c_slave.o
+obj-$(CONFIG_I2C_SLAVE_CLIENT)		+= i2c_slave_client.o
diff --git a/drivers/i2c-slave/i2c_slave_client.c b/drivers/i2c-slave/i2c_slave_client.c
new file mode 100644
index 000000000000..4068fe172b83
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_client.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+
+struct i2c_client *i2c_slave_client;
+static int i2c_slave_client_probe(struct i2c_client *adapter);
+static int i2c_slave_client_remove(struct i2c_client *client);
+static struct i2c_driver i2c_slave_client_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "i2c-slave-client",
+		   },
+	.probe = i2c_slave_client_probe,
+	.remove = i2c_slave_client_remove,
+};
+
+/*!
+ * ov2640 I2C attach function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  Error code indicating success or failure
+ */
+static int i2c_slave_client_probe(struct i2c_client *client)
+{
+	i2c_slave_client = client;
+	return 0;
+}
+
+/*!
+ * ov2640 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int i2c_slave_client_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+/*!
+ * ov2640 init function
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int i2c_slave_client_init(void)
+{
+	return i2c_add_driver(&i2c_slave_client_driver);
+}
+
+/*!
+ * OV2640 cleanup function
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit i2c_slave_client_clean(void)
+{
+	i2c_del_driver(&i2c_slave_client_driver);
+}
+
+module_init(i2c_slave_client_init);
+module_exit(i2c_slave_client_clean);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("I2c Slave Client Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c-slave/i2c_slave_core.c b/drivers/i2c-slave/i2c_slave_core.c
new file mode 100644
index 000000000000..0592d53a6fad
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_core.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/fs.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <asm/uaccess.h>
+#include "i2c_slave_device.h"
+
+int i2c_slave_major;
+
+static ssize_t i2c_slave_read(struct file *fd, char __user *buf, size_t len,
+			      loff_t *ptr)
+{
+	i2c_slave_device_t *dev;
+	void *kbuf;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	kbuf = kmalloc(len, GFP_KERNEL);
+	if (!kbuf) {
+		ret = -ENOMEM;
+		goto error0;
+	}
+
+	dev = (i2c_slave_device_t *) fd->private_data;
+	if (!dev) {
+		ret = -ENODEV;
+		goto error1;
+	}
+
+	ret = i2c_slave_device_read(dev, len, kbuf);
+	if (ret <= 0 || copy_to_user(buf, kbuf, len)) {
+		ret = -EFAULT;
+	}
+
+      error1:
+	kfree(kbuf);
+      error0:
+	return ret;
+}
+
+static ssize_t i2c_slave_write(struct file *fd, const char __user *buf,
+			       size_t len, loff_t *ptr)
+{
+	i2c_slave_device_t *dev;
+	void *kbuf;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	kbuf = kmalloc(len, GFP_KERNEL);
+	if (!kbuf) {
+		ret = -ENOMEM;
+		goto error0;
+	}
+	if (copy_from_user(kbuf, buf, len)) {
+		ret = -EFAULT;
+		goto error1;
+	}
+
+	dev = (i2c_slave_device_t *) fd->private_data;
+	if (!dev) {
+		ret = -ENODEV;
+		goto error1;
+	}
+
+	ret = i2c_slave_device_write(dev, len, (u8 *) kbuf);
+
+      error1:
+	kfree(kbuf);
+      error0:
+	return ret;
+}
+
+static int i2c_slave_ioctl(struct inode *inode, struct file *fd,
+			   unsigned code, unsigned long value)
+{
+	/*todo */
+	return 0;
+}
+
+static int i2c_slave_open(struct inode *inode, struct file *fd)
+{
+	int ret;
+	unsigned int id;
+	i2c_slave_device_t *dev;
+	id = iminor(inode);
+
+	if (id >= I2C_SLAVE_DEVICE_MAX) {
+		ret = -ENODEV;
+		goto error;
+	}
+
+	dev = i2c_slave_device_find(id);
+	if (!dev) {
+		ret = -ENODEV;
+		goto error;
+	}
+
+	i2c_slave_rb_clear(dev->receive_buffer);
+	i2c_slave_rb_clear(dev->send_buffer);
+
+	if (i2c_slave_device_start(dev)) {
+		ret = -EBUSY;
+		goto error;
+	}
+
+	fd->private_data = (void *)dev;
+	ret = 0;
+
+      error:
+	return ret;
+}
+
+static int i2c_slave_release(struct inode *inode, struct file *fd)
+{
+	int ret;
+	unsigned int id;
+	i2c_slave_device_t *dev;
+	id = iminor(inode);
+
+	if (id >= I2C_SLAVE_DEVICE_MAX) {
+		ret = -ENODEV;
+		goto error;
+	}
+
+	dev = i2c_slave_device_find(id);
+	if (!dev) {
+		ret = -ENODEV;
+		goto error;
+	}
+
+	if (i2c_slave_device_stop(dev)) {
+		ret = -EBUSY;
+		goto error;
+	}
+
+	ret = 0;
+
+      error:
+	return ret;
+}
+
+static const struct file_operations i2c_slave_fops = {
+	.owner = THIS_MODULE,
+	.llseek = no_llseek,
+	.read = i2c_slave_read,
+	.write = i2c_slave_write,
+	.ioctl = i2c_slave_ioctl,
+	.open = i2c_slave_open,
+	.release = i2c_slave_release,
+};
+
+static int i2c_slave_bus_match(struct device *dev, struct device_driver *drv)
+{
+	return 0;
+}
+
+/*
+static int i2c_slave_bus_probe(struct device *dev)
+{
+	struct device_driver *driver = dev->driver;
+
+	if (driver) {
+		return driver->probe(dev);
+	} else {
+		dev_err(dev, "%s: no driver\n", __func__);
+		return -ENODEV;
+	}
+}
+*/
+
+static int i2c_slave_bus_remove(struct device *dev)
+{
+	struct device_driver *driver = dev->driver;
+
+	if (driver) {
+		if (!driver->remove) {
+			return 0;
+		} else {
+			return driver->remove(dev);
+		}
+	} else {
+
+		dev_err(dev, "%s: no driver\n", __func__);
+		return -ENODEV;
+	}
+}
+
+static void i2c_slave_bus_shutdown(struct device *dev)
+{
+	struct device_driver *driver = dev->driver;
+
+	if (driver) {
+
+		driver->shutdown(dev);
+	} else {
+
+		dev_err(dev, "%s: no driver\n", __func__);
+		return;
+	}
+}
+static int i2c_slave_bus_suspend(struct device *dev, pm_message_t state)
+{
+	struct device_driver *driver = dev->driver;
+
+	if (driver) {
+
+		if (!driver->suspend) {
+			return 0;
+		} else {
+			return driver->suspend(dev, state);
+		}
+	} else {
+
+		dev_err(dev, "%s: no driver\n", __func__);
+		return -ENODEV;
+	}
+}
+
+static int i2c_slave_bus_resume(struct device *dev)
+{
+	struct device_driver *driver = dev->driver;
+
+	if (driver) {
+
+		if (!driver->resume) {
+			return 0;
+		} else {
+			return driver->resume(dev);
+		}
+	} else {
+
+		dev_err(dev, "%s: no driver\n", __func__);
+		return -ENODEV;
+	}
+}
+
+struct bus_type i2c_slave_bus_type = {
+	.name = "i2c-slave",
+	.match = i2c_slave_bus_match,
+	.remove = i2c_slave_bus_remove,
+	.shutdown = i2c_slave_bus_shutdown,
+	.suspend = i2c_slave_bus_suspend,
+	.resume = i2c_slave_bus_resume,
+};
+
+EXPORT_SYMBOL_GPL(i2c_slave_bus_type);
+
+static int i2c_slave_driver_probe(struct device *dev)
+{
+	return 0;
+}
+
+static int i2c_slave_driver_remove(struct device *dev)
+{
+	return 0;
+}
+
+static int i2c_slave_driver_shutdown(struct device *dev)
+{
+	return 0;
+}
+
+static int i2c_slave_driver_suspend(struct device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int i2c_slave_driver_resume(struct device *dev)
+{
+	return 0;
+}
+
+extern struct class *i2c_slave_class;
+
+static struct device_driver i2c_slave_driver = {
+	.name = "i2c-slave",
+	.owner = THIS_MODULE,
+	.bus = &i2c_slave_bus_type,
+	.probe = i2c_slave_driver_probe,
+	.remove = i2c_slave_driver_remove,
+	.shutdown = i2c_slave_driver_shutdown,
+	.suspend = i2c_slave_driver_suspend,
+	.resume = i2c_slave_driver_resume,
+};
+
+static int __init i2c_slave_dev_init(void)
+{
+	int ret;
+
+	printk(KERN_INFO "i2c slave /dev entries driver\n");
+
+	ret = bus_register(&i2c_slave_bus_type);
+	if (ret) {
+		printk(KERN_ERR "%s: bus_register error\n", __func__);
+		goto out;
+	}
+
+	i2c_slave_class = class_create(THIS_MODULE, "i2c-slave");
+	if (IS_ERR(i2c_slave_class)) {
+		pr_err("%s: class_create error\n", __func__);
+		goto out_unreg_bus;
+	}
+
+	i2c_slave_major = register_chrdev(0, "i2c-slave", &i2c_slave_fops);
+	if (i2c_slave_major <= 0) {
+		pr_err("%s: register_chrdev error\n", __func__);
+		goto out_unreg_class;
+	}
+
+	ret = driver_register(&i2c_slave_driver);
+	if (ret) {
+		pr_err("%s: driver_register error\n", __func__);
+		goto out_unreg_chrdev;
+	}
+
+	return 0;
+
+      out_unreg_chrdev:
+	unregister_chrdev(i2c_slave_major, "i2c-slave");
+      out_unreg_class:
+	class_destroy(i2c_slave_class);
+      out_unreg_bus:
+	bus_unregister(&i2c_slave_bus_type);
+      out:
+	pr_err("%s: init error\n", __func__);
+	return ret;
+}
+
+static void __exit i2c_dev_exit(void)
+{
+	driver_unregister(&i2c_slave_driver);
+	class_destroy(i2c_slave_class);
+	unregister_chrdev(i2c_slave_major, "i2c-slave");
+	bus_unregister(&i2c_slave_bus_type);
+}
+
+module_init(i2c_slave_dev_init);
+module_exit(i2c_dev_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("I2C Slave Driver Core");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c-slave/i2c_slave_device.c b/drivers/i2c-slave/i2c_slave_device.c
new file mode 100644
index 000000000000..bfe39809928e
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_device.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/major.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/kdev_t.h>
+#include "i2c_slave_device.h"
+static i2c_slave_device_t *i2c_slave_devices[I2C_SLAVE_DEVICE_MAX];
+struct class *i2c_slave_class;
+static int i2c_slave_device_get_id(void)
+{
+	int i;
+	for (i = 0; i < I2C_SLAVE_DEVICE_MAX; i++) {
+		if (!i2c_slave_devices[i])
+			return i;
+	}
+	return -1;
+}
+
+i2c_slave_device_t *i2c_slave_device_find(int id)
+{
+	if (id >= 0 && id < I2C_SLAVE_DEVICE_MAX)
+		return i2c_slave_devices[id];
+
+	else
+		return NULL;
+}
+void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name)
+{
+	device->name = name;
+}
+
+void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address)
+{
+	device->address = address;
+}
+
+u8 i2c_slave_device_get_addr(i2c_slave_device_t *device)
+{
+	return device->address;
+}
+
+int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq)
+{
+	/*TODO: freq check */
+	device->scl_freq = freq;
+	return 0;
+}
+
+u32 i2c_slave_device_get_freq(i2c_slave_device_t *device)
+{
+	return device->scl_freq;
+}
+
+/*used by the specific i2c device to register itself to the core.*/
+i2c_slave_device_t *i2c_slave_device_alloc(void)
+{
+	int id;
+	i2c_slave_device_t *device;
+	id = i2c_slave_device_get_id();
+	if (id < 0) {
+		goto error;
+	}
+	device =
+	    (i2c_slave_device_t *) kzalloc(sizeof(i2c_slave_device_t),
+					   GFP_KERNEL);
+	if (!device) {
+		printk(KERN_ERR "%s: alloc device error\n", __func__);
+		goto error_device;
+	}
+	device->receive_buffer = i2c_slave_rb_alloc(PAGE_SIZE);
+	if (!device->receive_buffer) {
+		printk(KERN_ERR "%s: alloc receive buffer error\n", __func__);
+		goto error_receive_buffer;
+	}
+	device->send_buffer = i2c_slave_rb_alloc(PAGE_SIZE);
+	if (!device->send_buffer) {
+		printk(KERN_ERR "%s: alloc send buffer error\n", __func__);
+		goto error_send_buffer;
+	}
+	device->id = id;
+	return device;
+
+      error_send_buffer:
+	kfree(device->receive_buffer);
+      error_receive_buffer:
+	kfree((void *)device);
+      error_device:
+	pr_debug(KERN_ERR "%s: no memory\n", __func__);
+      error:
+	return 0;
+}
+
+void i2c_slave_device_free(i2c_slave_device_t *dev)
+{
+	i2c_slave_rb_release(dev->receive_buffer);
+	i2c_slave_rb_release(dev->send_buffer);
+	kfree(dev);
+}
+
+int i2c_slave_device_register(i2c_slave_device_t *device)
+{
+	device->dev = device_create(i2c_slave_class, NULL,
+				    MKDEV(i2c_slave_major, device->id),
+				    NULL, "slave-i2c-%d", device->id);
+	if (!device->dev) {
+		return -1;
+	}
+	i2c_slave_devices[device->id] = device;
+	return 0;
+}
+
+void i2c_slave_device_unregister(i2c_slave_device_t *device)
+{
+	device_destroy(i2c_slave_class, MKDEV(i2c_slave_major, device->id));
+	i2c_slave_devices[device->id] = 0;
+	i2c_slave_device_free(device);
+}
+
+/*
+	this two functions are used by i2c slave core to start or stop the specific i2c device.
+*/
+int i2c_slave_device_start(i2c_slave_device_t *device)
+{
+	return device->start(device);
+}
+
+int i2c_slave_device_stop(i2c_slave_device_t *device)
+{
+	return device->stop(device);
+}
+
+/*
+	this two functions are used by i2c slave core to get data by the specific i2c slave device
+	or send data to it to feed i2c master's need.
+
+	@mod: async(1) or sync(0) mode.
+*/
+int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data)
+{
+	int read_num, read_total = 0;
+	int step = 1000;
+	u8 *read_buf = data;
+	printk(KERN_INFO "%s: device id=%d, num=%d\n", __func__, device->id,
+	       num);
+	read_num = i2c_slave_rb_consume(device->receive_buffer, num, read_buf);
+	read_total += read_num;
+	read_buf += read_num;
+	step--;
+	while ((read_total < num) && step) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(HZ / 10);
+		if (!signal_pending(current)) {
+		} else {
+			 /*TODO*/ break;
+		}
+		read_num =
+		    i2c_slave_rb_consume(device->receive_buffer,
+					 num - read_total, read_buf);
+		num -= read_num;
+		read_buf += read_num;
+		step--;
+	}
+	return read_total;
+}
+int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data)
+{
+	int write_num, write_total = 0;
+	int step = 1000;
+	u8 *buf_index = data;
+	write_num = i2c_slave_rb_produce(device->send_buffer, num, buf_index);
+	write_total += write_num;
+	buf_index += write_num;
+	step--;
+	while (write_total < num && step) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(HZ / 10);
+		if (!signal_pending(current)) {
+		} else {
+			 /*TODO*/ step = 0;
+			break;
+		}
+		write_num =
+		    i2c_slave_rb_produce(device->send_buffer, num - write_total,
+					 buf_index);
+		write_total += write_num;
+		buf_index += write_num;
+		step--;
+	}
+	while (step && i2c_slave_rb_num(device->send_buffer)) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(HZ / 10);
+		if (!signal_pending(current)) {
+			step--;
+		} else {
+			 /*TODO*/ step = 0;
+			break;
+		}
+	}
+	if (!step) {
+		write_total -= i2c_slave_rb_num(device->send_buffer);
+		i2c_slave_rb_clear(device->send_buffer);
+	}
+	return write_total;
+}
+
+/*
+ * this 2 functions used by the specific i2c slave device when they got data from master(produce),
+ * or is request by master(consume).
+ */
+int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data)
+{
+	int ret;
+	ret = i2c_slave_rb_produce(device->receive_buffer, num, data);
+	return ret;
+}
+int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data)
+{
+	return i2c_slave_rb_consume(device->send_buffer, num, data);
+}
+
+EXPORT_SYMBOL(i2c_slave_device_set_name);
+EXPORT_SYMBOL(i2c_slave_device_set_address);
+EXPORT_SYMBOL(i2c_slave_device_get_addr);
+EXPORT_SYMBOL(i2c_slave_device_find);
+EXPORT_SYMBOL(i2c_slave_device_set_freq);
+EXPORT_SYMBOL(i2c_slave_device_get_freq);
+
+/*
+* used by the specific i2c device to register itself to the core.
+*/
+EXPORT_SYMBOL(i2c_slave_device_alloc);
+EXPORT_SYMBOL(i2c_slave_device_free);
+EXPORT_SYMBOL(i2c_slave_device_register);
+EXPORT_SYMBOL(i2c_slave_device_unregister);
+
+/*
+	this two functions are used by i2c slave core to start or stop the specific i2c device.
+*/
+EXPORT_SYMBOL(i2c_slave_device_start);
+EXPORT_SYMBOL(i2c_slave_device_stop);
+
+/*
+	this two functions are used by i2c slave core to get data by the specific i2c slave device
+	or send data to it for it to feed i2c master's need.
+
+	@mod: async(1) or sync(0) mode.
+*/
+EXPORT_SYMBOL(i2c_slave_device_read);
+EXPORT_SYMBOL(i2c_slave_device_write);
+
+/*
+* this 2 functions used by the specific i2c slave device when they got data from master,
+* or is request by master.
+*/
+EXPORT_SYMBOL(i2c_slave_device_produce);
+EXPORT_SYMBOL(i2c_slave_device_consume);
diff --git a/drivers/i2c-slave/i2c_slave_device.h b/drivers/i2c-slave/i2c_slave_device.h
new file mode 100644
index 000000000000..e08ea569e030
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_device.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __I2C_SLAVE_H__
+#define __I2C_SLAVE_H__
+
+#include <linux/list.h>
+#include "i2c_slave_ring_buffer.h"
+
+#define I2C_SLAVE_DEVICE_MAX 256
+extern int i2c_slave_major;
+
+typedef struct i2c_slave_device {
+	struct list_head list;
+	u8 address;
+	u32 scl_freq;
+	char *name;
+	i2c_slave_ring_buffer_t *receive_buffer;
+	i2c_slave_ring_buffer_t *send_buffer;
+	int (*start) (struct i2c_slave_device *);
+	int (*stop) (struct i2c_slave_device *);
+	/*int (*set_freq)(struct i2c_slave_device*);
+	int (*set_addr)(struct i2c_slave_device*);*/
+	void *private_data;
+	struct device *dev;
+	int id;
+} i2c_slave_device_t;
+
+/*
+	used by the specific device to set some infomations.
+*/
+void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name);
+void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address);
+i2c_slave_device_t *i2c_slave_device_find(int id);
+u8 i2c_slave_device_get_addr(i2c_slave_device_t *device);
+int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq);
+u32 i2c_slave_device_get_freq(i2c_slave_device_t *device);
+
+/*
+**used by the specific i2c device to register itself to the core.
+*/
+i2c_slave_device_t *i2c_slave_device_alloc(void);
+void i2c_slave_device_free(i2c_slave_device_t *);
+int i2c_slave_device_register(i2c_slave_device_t *device);
+void i2c_slave_device_unregister(i2c_slave_device_t *device);
+
+/*
+	this two functions are used by i2c slave core to start or stop the specific i2c device.
+*/
+int i2c_slave_device_start(i2c_slave_device_t *device);
+int i2c_slave_device_stop(i2c_slave_device_t *device);
+
+/*
+	this two functions are used by i2c slave core to get data by the specific i2c slave device
+	or send data to it for it to feed i2c master's need.
+
+	@mod: async(1) or sync(0) mode.
+*/
+int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data);
+int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data);
+
+/*
+*this 2 functions used by the specific i2c slave device when they got data from master,
+*or is requested by master.
+*/
+int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data);
+int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data);
+
+#endif
diff --git a/drivers/i2c-slave/i2c_slave_ring_buffer.c b/drivers/i2c-slave/i2c_slave_ring_buffer.c
new file mode 100644
index 000000000000..4a55e099235f
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_ring_buffer.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/slab.h>
+#include <linux/hardirq.h>
+#include "i2c_slave_ring_buffer.h"
+
+i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size)
+{
+	i2c_slave_ring_buffer_t *ring_buf;
+
+	ring_buf =
+	    (i2c_slave_ring_buffer_t *) kzalloc(sizeof(i2c_slave_ring_buffer_t),
+						GFP_KERNEL);
+	if (!ring_buf) {
+		pr_debug("%s: alloc ring_buf error\n", __func__);
+		goto error;
+	}
+
+	ring_buf->buffer = kmalloc(size, GFP_KERNEL);
+	if (!ring_buf->buffer) {
+		pr_debug("%s: alloc buffer error\n", __func__);
+		goto error1;
+	}
+
+	ring_buf->total = size;
+
+	ring_buf->lock = __SPIN_LOCK_UNLOCKED(ring_buf->lock);
+	return ring_buf;
+
+      error1:
+	kfree(ring_buf);
+      error:
+	return NULL;
+}
+
+void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(ring->lock, flags);
+	kfree(ring->buffer);
+	spin_unlock_irqrestore(ring->lock, flags);
+	kfree(ring);
+}
+
+int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(ring->lock, flags);
+
+	if (ring->start < ring->end) {
+		if ((ring->start + num) < ring->end) {	/*have enough space */
+			memcpy(&ring->buffer[ring->start], data, num);
+			ring->start += num;
+			ret = num;
+		} else {	/*space not enough, just copy part of it. */
+			ret = ring->end - ring->start;
+			memcpy(&ring->buffer[ring->start], data, ret);
+			ring->start += ret;
+			ring->full = 1;
+		}
+	} else if (ring->start >= ring->end && !ring->full) {
+		if (ring->start + num <= ring->total) {	/*space enough */
+			ret = num;
+			memcpy(&ring->buffer[ring->start], data, ret);
+			ring->start += ret;
+		} else {	/*turn ring->start around */
+			ret = ring->total - ring->start;
+			memcpy(&ring->buffer[ring->start], data, ret);
+			ring->start = 0;
+			num -= ret;
+			data += ret;
+			if (num < ring->end) {	/*space enough */
+				ret += num;
+				memcpy(&ring->buffer[ring->start], data, num);
+			} else {	/*space not enough, just copy part of it. */
+				ret += ring->end;
+				memcpy(&ring->buffer[ring->start], data,
+				       ring->end);
+				ring->start = ring->end;
+				ring->full = 1;
+			}
+		}
+	} else {		/*(ring->data == ring->end) && ring->full ) : full */
+		ret = 0;
+	}
+
+	spin_unlock_irqrestore(ring->lock, flags);
+	return ret;
+}
+
+int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(ring->lock, flags);
+	if (num <= 0) {
+		ret = 0;
+		goto out;
+	}
+
+	if (ring->start > ring->end) {
+		if (num <= ring->start - ring->end) {	/*enough */
+			ret = num;
+			memcpy(data, &ring->buffer[ring->end], ret);
+			ring->end += ret;
+		} else {	/*not enough */
+			ret = ring->start - ring->end;
+			memcpy(data, &ring->buffer[ring->end], ret);
+			ring->end += ret;
+		}
+	} else if (ring->start < ring->end || ring->full) {
+		if (num <= ring->total - ring->end) {
+			ret = ring->total - ring->end;
+			memcpy(data, &ring->buffer[ring->end], ret);
+			ring->end += ret;
+		} else if (num <= ring->total - ring->end + ring->start) {
+			ret = ring->total - ring->end;
+			memcpy(data, &ring->buffer[ring->end], ret);
+			ring->end = 0;
+			data += ret;
+			num -= ret;
+			memcpy(data, &ring->buffer[ring->end], num);
+			ring->end = num;
+			ret += num;
+		} else {
+			ret = ring->total - ring->end;
+			memcpy(data, &ring->buffer[ring->end], ret);
+			ring->end = 0;
+			data += ret;
+			num -= ret;
+			memcpy(data, &ring->buffer[ring->end], ring->start);
+			ring->end = ring->start;
+			ret += ring->start;
+		}
+		ring->full = 0;
+	} else {		/*empty */
+		ret = 0;
+	}
+
+      out:
+	spin_unlock_irqrestore(ring->lock, flags);
+
+	return ret;
+}
+
+int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(ring->lock, flags);
+	if (ring->start > ring->end) {
+		ret = ring->start - ring->end;
+	} else if (ring->start < ring->end) {
+		ret = ring->total - ring->end + ring->start;
+	} else if (ring->full) {
+		ret = ring->total;
+	} else {
+		ret = 0;
+	}
+	spin_unlock_irqrestore(ring->lock, flags);
+	return ret;
+}
+
+void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring)
+{
+	unsigned long flags;
+	spin_lock_irqsave(ring->lock, flags);
+
+	ring->start = ring->end = 0;
+	ring->full = 0;
+	spin_unlock_irqrestore(ring->lock, flags);
+}
diff --git a/drivers/i2c-slave/i2c_slave_ring_buffer.h b/drivers/i2c-slave/i2c_slave_ring_buffer.h
new file mode 100644
index 000000000000..1068e5f1b527
--- /dev/null
+++ b/drivers/i2c-slave/i2c_slave_ring_buffer.h
@@ -0,0 +1,39 @@
+#ifndef __BUFFER_MANAGER_H__
+#define __BUFFER_MANAGER_H__
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+typedef struct i2c_slave_ring_buffer {
+	int start;
+	int end;
+	int total;
+	bool full;
+	char *buffer;
+	spinlock_t lock;
+} i2c_slave_ring_buffer_t;
+
+i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size);
+
+void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring);
+
+int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data);
+
+int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data);
+
+int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring);
+
+void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring);
+
+#endif
diff --git a/drivers/i2c-slave/mxc_i2c_slave.c b/drivers/i2c-slave/mxc_i2c_slave.c
new file mode 100644
index 000000000000..af8756722ea1
--- /dev/null
+++ b/drivers/i2c-slave/mxc_i2c_slave.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/io.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include "i2c_slave_device.h"
+#include "mxc_i2c_slave.h"
+#include "mxc_i2c_slave_reg.h"
+
+struct mxc_i2c_slave_clk {
+	int reg_value;
+	int div;
+};
+
+static const struct mxc_i2c_slave_clk i2c_clk_table[] = {
+	{0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28},
+	{0, 30}, {1, 32}, {0x24, 32}, {2, 36},
+	{0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44},
+	{4, 48}, {0x28, 48}, {5, 52}, {0x29, 56},
+	{6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72},
+	{8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96},
+	{0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128},
+	{0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192},
+	{0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256},
+	{0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384},
+	{0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512},
+	{0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768},
+	{0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024},
+	{0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536},
+	{0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048},
+	{0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840},
+	{0, 0}
+};
+
+extern void gpio_i2c_active(int i2c_num);
+extern void gpio_i2c_inactive(int i2c_num);
+
+static irqreturn_t interrupt_handler(int irq, void *dev_id)
+{
+	u16 status, ctl;
+	int num;
+	u16 data;
+	struct mxc_i2c_slave_device *mxc_i2c =
+	    (struct mxc_i2c_slave_device *)dev_id;
+
+	status = readw(mxc_i2c->reg_base + MXC_I2SR);
+	ctl = readw(mxc_i2c->reg_base + MXC_I2CR);
+
+	dev_dbg(mxc_i2c->dev->dev, "status=%x, ctl=%x\n", status, ctl);
+
+	if (status & MXC_I2SR_IAAS) {
+		if (status & MXC_I2SR_SRW) {
+			/*slave send */
+			num =
+			    i2c_slave_device_consume(mxc_i2c->dev, 1,
+						     (u8 *) &data);
+			if (num < 1) {
+				/*FIXME:not ready to send data */
+				printk(KERN_ERR
+				       " i2c-slave:%s:data not ready\n",
+				       __func__);
+			} else {
+				ctl |= MXC_I2CR_MTX;
+				writew(ctl, mxc_i2c->reg_base + MXC_I2CR);
+				/*send data */
+				writew(data, mxc_i2c->reg_base + MXC_I2DR);
+			}
+
+		} else {
+			/*slave receive */
+			ctl &= ~MXC_I2CR_MTX;
+			writew(ctl, mxc_i2c->reg_base + MXC_I2CR);
+
+			/*dummy read */
+			data = readw(mxc_i2c->reg_base + MXC_I2DR);
+		}
+	} else {
+		/*slave send */
+		if (ctl & MXC_I2CR_MTX) {
+			if (!(status & MXC_I2SR_RXAK)) {	/*ACK received */
+				num =
+				    i2c_slave_device_consume(mxc_i2c->dev, 1,
+							     (u8 *) &data);
+				if (num < 1) {
+					/*FIXME:not ready to send data */
+					printk(KERN_ERR
+					       " i2c-slave:%s:data not ready\n",
+					       __func__);
+				} else {
+					ctl |= MXC_I2CR_MTX;
+					writew(ctl,
+					       mxc_i2c->reg_base + MXC_I2CR);
+					writew(data,
+					       mxc_i2c->reg_base + MXC_I2DR);
+				}
+			} else {
+				/*no ACK. */
+				/*dummy read */
+				ctl &= ~MXC_I2CR_MTX;
+				writew(ctl, mxc_i2c->reg_base + MXC_I2CR);
+				data = readw(mxc_i2c->reg_base + MXC_I2DR);
+			}
+		} else {	/*read */
+			ctl &= ~MXC_I2CR_MTX;
+			writew(ctl, mxc_i2c->reg_base + MXC_I2CR);
+
+			/*read */
+			data = readw(mxc_i2c->reg_base + MXC_I2DR);
+			i2c_slave_device_produce(mxc_i2c->dev, 1,
+						 (u8 *) &data);
+		}
+
+	}
+
+	writew(0x0, mxc_i2c->reg_base + MXC_I2SR);
+
+	return IRQ_HANDLED;
+}
+
+static int start(i2c_slave_device_t *device)
+{
+	volatile unsigned int cr;
+	unsigned int addr;
+	struct mxc_i2c_slave_device *mxc_dev;
+
+	mxc_dev = (struct mxc_i2c_slave_device *)device->private_data;
+	if (!mxc_dev) {
+		dev_err(device->dev, "%s: get mxc_dev error\n", __func__);
+		return -ENODEV;
+	}
+
+	clk_enable(mxc_dev->clk);
+	/* Set the frequency divider */
+	writew(mxc_dev->clkdiv, mxc_dev->reg_base + MXC_IFDR);
+
+	/* Set the Slave bit */
+	cr = readw(mxc_dev->reg_base + MXC_I2CR);
+	cr &= (!MXC_I2CR_MSTA);
+	writew(cr, mxc_dev->reg_base + MXC_I2CR);
+
+	/*Set Slave Address */
+	addr = mxc_dev->dev->address << 1;
+	writew(addr, mxc_dev->reg_base + MXC_IADR);
+
+	/* Clear the status register */
+	writew(0x0, mxc_dev->reg_base + MXC_I2SR);
+
+	/* Enable I2C and its interrupts */
+	writew(MXC_I2CR_IEN, mxc_dev->reg_base + MXC_I2CR);
+	writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, mxc_dev->reg_base + MXC_I2CR);
+
+	return 0;
+
+}
+
+static int stop(i2c_slave_device_t *device)
+{
+	struct mxc_i2c_slave_device *mxc_dev;
+
+	mxc_dev = (struct mxc_i2c_slave_device *)device->private_data;
+
+	writew(0x0, mxc_dev->reg_base + MXC_I2CR);
+	clk_disable(mxc_dev->clk);
+
+	return 0;
+}
+
+static int mxc_i2c_slave_probe(struct platform_device *pdev)
+{
+	int i;
+	u32 clk_freq;
+	struct resource *res;
+	struct mxc_i2c_slave_device *mxc_dev;
+
+	mxc_dev = kzalloc(sizeof(struct mxc_i2c_slave_device), GFP_KERNEL);
+	if (!mxc_dev) {
+		goto error0;
+	}
+	mxc_dev->dev = i2c_slave_device_alloc();
+	if (mxc_dev->dev == 0) {
+		dev_err(&pdev->dev, "%s: i2c_slave_device_alloc error\n",
+			__func__);
+		goto error1;
+	}
+
+	i2c_slave_device_set_address(mxc_dev->dev, MXC_I2C_SLAVE_ADDRESS);
+	i2c_slave_device_set_freq(mxc_dev->dev, MXC_I2C_SLAVE_FREQ);
+	i2c_slave_device_set_name(mxc_dev->dev, MXC_I2C_SLAVE_NAME);
+	mxc_dev->dev->start = start;
+	mxc_dev->dev->stop = stop;
+
+	mxc_dev->dev->private_data = mxc_dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "%s: get resource error\n", __func__);
+		goto error2;
+	}
+	mxc_dev->reg_base = ioremap(res->start, res->end - res->start + 1);
+
+	mxc_dev->irq = platform_get_irq(pdev, 0);
+	if (mxc_dev->irq < 0) {
+		dev_err(&pdev->dev, "%s: get irq error\n", __func__);
+		goto error3;
+	}
+	if (request_irq(mxc_dev->irq, interrupt_handler,
+			0, mxc_dev->dev->name, mxc_dev) < 0) {
+		dev_err(&pdev->dev, "%s: request_irq error\n", __func__);
+		goto error3;
+	}
+
+	/*i2c id on soc */
+	mxc_dev->id = pdev->id;
+
+	gpio_i2c_active(mxc_dev->id);
+
+	/*clock */
+	mxc_dev->clk = clk_get(&pdev->dev, "i2c_clk");
+	clk_freq = clk_get_rate(mxc_dev->clk);
+	mxc_dev->clkdiv = -1;
+	if (mxc_dev->dev->scl_freq) {
+		/* Calculate divider and round up any fractional part */
+		int div = (clk_freq + mxc_dev->dev->scl_freq - 1) /
+		    mxc_dev->dev->scl_freq;
+		for (i = 0; i2c_clk_table[i].div != 0; i++) {
+			if (i2c_clk_table[i].div >= div) {
+				mxc_dev->clkdiv = i2c_clk_table[i].reg_value;
+				break;
+			}
+		}
+	}
+	if (mxc_dev->clkdiv == -1) {
+		i--;
+		mxc_dev->clkdiv = 0x1F;	/* Use max divider */
+	}
+	dev_dbg(&pdev->dev,
+		"i2c slave speed is %d/%d = %d bps, reg val = 0x%02X\n",
+		clk_freq, i2c_clk_table[i].div, clk_freq / i2c_clk_table[i].div,
+		mxc_dev->clkdiv);
+
+	if (i2c_slave_device_register(mxc_dev->dev) < 0) {
+		dev_err(&pdev->dev, "%s: i2c_slave_device_register error\n",
+			__func__);
+		goto error4;
+	}
+
+	platform_set_drvdata(pdev, (void *)mxc_dev);
+
+	/*start(mxc_dev->dev); */
+	return 0;
+
+      error4:
+	free_irq(mxc_dev->irq, mxc_dev);
+      error3:
+	iounmap(mxc_dev->reg_base);
+      error2:
+	i2c_slave_device_free(mxc_dev->dev);
+      error1:
+	kfree(mxc_dev);
+      error0:
+	return -ENODEV;
+}
+
+static int mxc_i2c_slave_remove(struct platform_device *pdev)
+{
+	struct mxc_i2c_slave_device *mxc_dev;
+	mxc_dev = (struct mxc_i2c_slave_device *)platform_get_drvdata(pdev);
+
+	i2c_slave_device_unregister(mxc_dev->dev);
+	free_irq(mxc_dev->irq, mxc_dev);
+	iounmap(mxc_dev->reg_base);
+	kfree((void *)mxc_dev);
+
+	return 0;
+}
+
+static int mxc_i2c_slave_suspend(struct platform_device *pdev,
+				 pm_message_t state)
+{
+	return 0;
+}
+
+static int mxc_i2c_slave_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver mxci2c_slave_driver = {
+	.driver = {
+		   .name = "mxc_i2c_slave",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxc_i2c_slave_probe,
+	.remove = mxc_i2c_slave_remove,
+	.suspend = mxc_i2c_slave_suspend,
+	.resume = mxc_i2c_slave_resume,
+};
+
+static int __init mxc_i2c_slave_init(void)
+{
+	/* Register the device driver structure. */
+	return platform_driver_register(&mxci2c_slave_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxc_i2c_slave_exit(void)
+{
+	platform_driver_unregister(&mxci2c_slave_driver);
+}
+
+module_init(mxc_i2c_slave_init);
+module_exit(mxc_i2c_slave_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC I2C Slave Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c-slave/mxc_i2c_slave.h b/drivers/i2c-slave/mxc_i2c_slave.h
new file mode 100644
index 000000000000..7b8d5143588e
--- /dev/null
+++ b/drivers/i2c-slave/mxc_i2c_slave.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXC_I2C_SLAVE_H__
+#define __MXC_I2C_SLAVE_H__
+
+#include <linux/clk.h>
+#include "i2c_slave_device.h"
+
+#define MXC_I2C_SLAVE_NAME "MXC_I2C_SLAVE"
+#define MXC_I2C_SLAVE_ADDRESS 0x55
+#define MXC_I2C_SLAVE_FREQ 1000*100
+
+struct mxc_i2c_slave_device {
+	/*!
+	 * The default clock divider value to be used.
+	 */
+	unsigned int clkdiv;
+
+	/*!
+	 * The clock source for the device.
+	 */
+	struct clk *clk;
+
+	/*i2c id on soc */
+	int id;
+
+	int irq;
+	unsigned long reg_base;
+	bool state;		/*0:stop, 1:start */
+	i2c_slave_device_t *dev;
+};
+
+#endif
diff --git a/drivers/i2c-slave/mxc_i2c_slave_reg.h b/drivers/i2c-slave/mxc_i2c_slave_reg.h
new file mode 100644
index 000000000000..6450ad6e3db9
--- /dev/null
+++ b/drivers/i2c-slave/mxc_i2c_slave_reg.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXC_I2C_SLAVE_REG_H__
+#define __MXC_I2C_SLAVE_REG_H__
+
+/* Address offsets of the I2C registers */
+#define MXC_IADR                0x00	/* Address Register */
+#define MXC_IFDR                0x04	/* Freq div register */
+#define MXC_I2CR                0x08	/* Control regsiter */
+#define MXC_I2SR                0x0C	/* Status register */
+#define MXC_I2DR                0x10	/* Data I/O register */
+
+/* Bit definitions of I2CR */
+#define MXC_I2CR_IEN            0x0080
+#define MXC_I2CR_IIEN           0x0040
+#define MXC_I2CR_MSTA           0x0020
+#define MXC_I2CR_MTX            0x0010
+#define MXC_I2CR_TXAK           0x0008
+#define MXC_I2CR_RSTA           0x0004
+
+/* Bit definitions of I2SR */
+#define MXC_I2SR_ICF            0x0080
+#define MXC_I2SR_IAAS           0x0040
+#define MXC_I2SR_IBB            0x0020
+#define MXC_I2SR_IAL            0x0010
+#define MXC_I2SR_SRW            0x0004
+#define MXC_I2SR_IIF            0x0002
+#define MXC_I2SR_RXAK           0x0001
+
+#endif /* __MXC_I2C_REG_H__ */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 8206442fbabd..c2244379aeec 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -339,6 +339,10 @@ config I2C_DESIGNWARE
 config I2C_GPIO
 	tristate "GPIO-based bitbanging I2C"
 	depends on GENERIC_GPIO
+
+config I2C_PARPORT
+	tristate "Parallel port adapter"
+	depends on PARPORT
 	select I2C_ALGOBIT
 	help
 	  This is a very simple bitbanging I2C driver utilizing the
@@ -412,9 +416,68 @@ config I2C_MPC
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mpc.
 
+config I2C_MXC
+	tristate "MXC I2C support"
+	depends on I2C && ARCH_MXC
+	help
+	  If you say yes to this option, support will be included for Freescale
+	  MXC I2C modules.
+
+	  This driver can also be built as a module.
+
+config I2C_MXC_HS
+	tristate "MXC HIGH SPEED I2C support"
+	depends on I2C && ARCH_MXC
+	help
+	  If you say yes to this option, support will be included for Freescale
+	  MXC HIGH SPEED I2C modules.
+
+	  This driver can also be built as a module.
+
+config I2C_MXS
+	tristate "MXS I2C Support"
+	depends on I2C && ARCH_MXS
+	help
+	  If you say yes to this option, support will be included for Freescale
+	  MXS I2C modules.
+
+config I2C_MXS_SELECT0
+	bool "Enable I2C0 module"
+	default y
+	depends on I2C_MXS
+	help
+	  Enable MXS I2C0 Module
+
+config I2C_MXS_SELECT0_PIOQUEUE_MODE
+	tristate "MXS I2C0 PIOQUEUE MODE Support"
+	depends on (I2C_MXS_SELECT0 && !ARCH_MX23)
+	help
+	  say yes if you are sure transfer length is eqaul to or less than 24 bytes.
+	  Otherwise say no to use DMA mode by default.
+
+config I2C_MXS_SELECT1
+	bool "Enable I2C1 module"
+	depends on (I2C_MXS && !ARCH_MX23)
+	help
+	  Enable MXS I2C1 Module
+
+config I2C_MXS_SELECT1_PIOQUEUE_MODE
+	tristate "MXS I2C1 PIOQUEUE MODE Support"
+	depends on I2C_MXS_SELECT1
+	help
+	  say yes if you are sure transfer length is eqaul to or less than 24 bytes.
+	  Otherwise say no to use DMA mode by default.
+
+config I2C_STMP378X
+	tristate "STMP378x I2C adapter"
+	depends on MACH_STMP378X
+	help
+	  TBD
+
 config I2C_MV64XXX
 	tristate "Marvell mv64xxx I2C Controller"
 	depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL
+
 	help
 	  If you say yes to this option, support will be included for the
 	  built-in I2C interface on the Marvell 64xxx line of host bridges.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index e654263bfc01..e0029e362588 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -71,6 +71,10 @@ obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
 obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_MXC)		+= mxc_i2c.o
+obj-$(CONFIG_I2C_MXC_HS)	+= mxc_i2c_hs.o
+obj-$(CONFIG_I2C_STMP378X)	+= i2c-stmp378x.o
+obj-$(CONFIG_I2C_MXS)		+= i2c-mxs.o
 
 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
new file mode 100644
index 000000000000..e3235ff8e551
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -0,0 +1,597 @@
+/*
+ * Freescale MX28 I2C bus driver
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/dmaengine.h>
+#include <mach/device.h>
+#include <mach/regs-i2c.h>
+#include <mach/system.h>
+#include <mach/hardware.h>
+
+#include "i2c-mxs.h"
+
+/* 2 for read, 1 for write */
+#define	NR_DESC		3
+static struct mxs_dma_desc *desc[NR_DESC];
+static dma_addr_t i2c_buf_phys;
+static u8 *i2c_buf_virt;
+
+#define	CMD_I2C_SELECT	(BM_I2C_CTRL0_RETAIN_CLOCK |	\
+			BM_I2C_CTRL0_PRE_SEND_START |	\
+			BM_I2C_CTRL0_MASTER_MODE |	\
+			BM_I2C_CTRL0_DIRECTION |	\
+			BF_I2C_CTRL0_XFER_COUNT(1))
+#define	CMD_I2C_WRITE	(BM_I2C_CTRL0_PRE_SEND_START |	\
+			BM_I2C_CTRL0_MASTER_MODE |	\
+			BM_I2C_CTRL0_DIRECTION)
+#define	CMD_I2C_READ	(BM_I2C_CTRL0_SEND_NAK_ON_LAST |	\
+			BM_I2C_CTRL0_MASTER_MODE)
+
+/* Hack for platform which does not support PioQueue Mode */
+#if !defined(HW_I2C_QUEUECMD) || 	\
+    !defined(HW_I2C_QUEUEDATA) ||	\
+    !defined(HW_I2C_QUEUECTRL_CLR) ||	\
+    !defined(HW_I2C_QUEUECTRL_SET)
+#warning "Pio Queue Mode *NOT* Support!"
+#define HW_I2C_QUEUECMD		HW_I2C_VERSION
+#define HW_I2C_QUEUEDATA	HW_I2C_VERSION
+#define HW_I2C_QUEUECTRL_SET	HW_I2C_VERSION
+#define HW_I2C_QUEUECTRL_CLR	HW_I2C_VERSION
+#endif
+
+static void hw_i2c_dmachan_reset(struct mxs_i2c_dev *dev)
+{
+	mxs_dma_reset(dev->dma_chan);
+	mxs_dma_ack_irq(dev->dma_chan);
+}
+
+static int hw_i2c_dma_init(struct platform_device *pdev)
+{
+	struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev);
+	int i, ret;
+
+	ret = mxs_dma_request(mxs_i2c->dma_chan, &pdev->dev, "i2c");
+	if (ret)
+		return ret;
+
+	for (i = 0; i < NR_DESC; i++) {
+		desc[i] = mxs_dma_alloc_desc();
+		if (desc[i] == NULL)
+			goto err;
+	}
+
+	i2c_buf_virt = dma_alloc_coherent(&pdev->dev,
+					  PAGE_SIZE, &i2c_buf_phys, GFP_KERNEL);
+	if (i2c_buf_virt == NULL)
+		goto err;
+
+	hw_i2c_dmachan_reset(mxs_i2c);
+	mxs_dma_enable_irq(mxs_i2c->dma_chan, 1);
+
+	return 0;
+
+err:
+	while (--i >= 0)
+		mxs_dma_free_desc(desc[i]);
+
+	return -ENOMEM;
+}
+
+static void hw_i2c_dma_uninit(struct platform_device *pdev)
+{
+	struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev);
+	int i;
+	LIST_HEAD(list);
+
+	mxs_dma_enable_irq(mxs_i2c->dma_chan, 0);
+	mxs_dma_get_cooked(mxs_i2c->dma_chan, &list);
+	mxs_dma_disable(mxs_i2c->dma_chan);
+
+	for (i = 0; i < NR_DESC; i++)
+		mxs_dma_free_desc(desc[i]);
+
+	hw_i2c_dmachan_reset(mxs_i2c);
+
+	dma_free_coherent(&pdev->dev, PAGE_SIZE, i2c_buf_virt, i2c_buf_phys);
+
+	mxs_dma_release(mxs_i2c->dma_chan, &pdev->dev);
+}
+
+static void hw_i2c_pioq_setup_read(struct mxs_i2c_dev *dev,
+				   u8 addr, void *buff, int len, int flags)
+{
+	u32 queuecmd;
+	u32 queuedata;
+
+	WARN_ONCE(len > 24, "choose DMA mode if xfer len > 24 bytes\n");
+
+	/* fill queue cmd */
+	queuecmd = CMD_I2C_SELECT;
+	__raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD);
+
+	/* fill data (slave addr) */
+	queuedata = addr | I2C_READ;
+	__raw_writel(queuedata, dev->regbase + HW_I2C_DATA);
+
+	/* fill queue cmd */
+	queuecmd = CMD_I2C_READ | flags;
+	queuecmd |= BF_I2C_CTRL0_XFER_COUNT(len) | flags;
+	__raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD);
+
+}
+
+static void hw_i2c_dma_setup_read(u8 addr, void *buff, int len, int flags)
+{
+	if (len > (PAGE_SIZE - 4))
+		BUG();
+
+	memset(&desc[0]->cmd, 0, sizeof(desc[0]->cmd));
+	memset(&desc[1]->cmd, 0, sizeof(desc[1]->cmd));
+
+	desc[0]->cmd.cmd.bits.bytes = 1;
+	desc[0]->cmd.cmd.bits.pio_words = 1;
+	desc[0]->cmd.cmd.bits.wait4end = 1;
+	desc[0]->cmd.cmd.bits.dec_sem = 1;
+	desc[0]->cmd.cmd.bits.irq = 1;
+	desc[0]->cmd.cmd.bits.chain = 1;
+	desc[0]->cmd.cmd.bits.command = DMA_READ;
+	desc[0]->cmd.address = i2c_buf_phys;
+	desc[0]->cmd.pio_words[0] = CMD_I2C_SELECT;
+	i2c_buf_virt[0] = addr | I2C_READ;
+
+	desc[1]->cmd.cmd.bits.bytes = len;
+	desc[1]->cmd.cmd.bits.pio_words = 1;
+	desc[1]->cmd.cmd.bits.wait4end = 1;
+	desc[1]->cmd.cmd.bits.dec_sem = 1;
+	desc[1]->cmd.cmd.bits.irq = 1;
+	desc[1]->cmd.cmd.bits.command = DMA_WRITE;
+	desc[1]->cmd.address = (u32) i2c_buf_phys + 1;
+	desc[1]->cmd.pio_words[0] = CMD_I2C_READ;
+	desc[1]->cmd.pio_words[0] |= BF_I2C_CTRL0_XFER_COUNT(len) | flags;
+}
+
+static void hw_i2c_pioq_setup_write(struct mxs_i2c_dev *dev,
+				    u8 addr, void *buff, int len, int flags)
+{
+	int align_len, i;
+	u8 slaveaddr;
+	u32 queuecmd;
+	u8 *buf1;
+	u32 *buf2;
+
+	WARN_ONCE(len > 24, "choose DMA mode if xfer len > 24 bytes\n");
+
+	align_len = (len + 1 + 3) & ~3;
+
+	buf1 = (u8 *) dev->buf;
+	buf2 = (u32 *) dev->buf;
+
+	/* fill queue cmd */
+	queuecmd = CMD_I2C_WRITE;
+	queuecmd |= BF_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
+	__raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD);
+
+	/* fill data (slave addr) */
+	slaveaddr = addr | I2C_WRITE;
+	memcpy(buf1, &slaveaddr, 1);
+
+	memcpy(&buf1[1], buff, len);
+
+	/* fill data */
+	for (i = 0; i < align_len / 4; i++)
+		__raw_writel(*buf2++, dev->regbase + HW_I2C_DATA);
+}
+
+static void hw_i2c_dma_setup_write(u8 addr, void *buff, int len, int flags)
+{
+	memset(&desc[2]->cmd, 0, sizeof(desc[2]->cmd));
+
+	desc[2]->cmd.cmd.bits.bytes = len + 1;
+	desc[2]->cmd.cmd.bits.pio_words = 1;
+	desc[2]->cmd.cmd.bits.wait4end = 1;
+	desc[2]->cmd.cmd.bits.dec_sem = 1;
+	desc[2]->cmd.cmd.bits.irq = 1;
+	desc[2]->cmd.cmd.bits.command = DMA_READ;
+	desc[2]->cmd.address = i2c_buf_phys;
+	desc[2]->cmd.pio_words[0] = CMD_I2C_WRITE;
+	desc[2]->cmd.pio_words[0] |= BM_I2C_CTRL0_POST_SEND_STOP;
+	desc[2]->cmd.pio_words[0] |= BF_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
+
+	i2c_buf_virt[0] = addr | I2C_WRITE;
+	memcpy(&i2c_buf_virt[1], buff, len);
+}
+
+static void hw_i2c_pioq_run(struct mxs_i2c_dev *dev)
+{
+	__raw_writel(0x20, dev->regbase + HW_I2C_QUEUECTRL_SET);
+}
+
+static void hw_i2c_dma_run(struct mxs_i2c_dev *dev, int dir)
+{
+	if (dir == I2C_READ) {
+		mxs_dma_desc_append(dev->dma_chan, desc[0]);
+		mxs_dma_desc_append(dev->dma_chan, desc[1]);
+	} else
+		mxs_dma_desc_append(dev->dma_chan, desc[2]);
+
+	mxs_dma_enable(dev->dma_chan);
+}
+
+static void hw_i2c_pioq_stop(struct mxs_i2c_dev *dev)
+{
+	__raw_writel(0x20, dev->regbase + HW_I2C_QUEUECTRL_CLR);
+}
+
+static void hw_i2c_finish_read(struct mxs_i2c_dev *dev, void *buff, int len)
+{
+	int i, align_len;
+	u8 *buf1;
+	u32 *buf2;
+
+	if (dev->flags & MXS_I2C_PIOQUEUE_MODE) {
+		align_len = (len + 3) & ~3;
+
+		buf1 = (u8 *) dev->buf;
+		buf2 = (u32 *) dev->buf;
+
+		for (i = 0; i < align_len / 4; i++)
+			*buf2++ = __raw_readl(dev->regbase + HW_I2C_QUEUEDATA);
+
+		memcpy(buff, buf1, len);
+	} else
+		memcpy(buff, &i2c_buf_virt[1], len);
+}
+
+/*
+ * Low level master read/write transaction.
+ */
+static int mxs_i2c_xfer_msg(struct i2c_adapter *adap,
+			    struct i2c_msg *msg, int stop)
+{
+	struct mxs_i2c_dev *dev = i2c_get_adapdata(adap);
+	int err;
+	int flags;
+
+	init_completion(&dev->cmd_complete);
+	dev->cmd_err = 0;
+
+	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
+		msg->addr, msg->len, msg->flags, stop);
+
+	if ((msg->len == 0) || (msg->len > (PAGE_SIZE - 1)))
+		return -EINVAL;
+
+	flags = stop ? BM_I2C_CTRL0_POST_SEND_STOP : 0;
+
+	if (msg->flags & I2C_M_RD) {
+		if (dev->flags & MXS_I2C_PIOQUEUE_MODE) {
+			hw_i2c_pioq_setup_read(dev,
+					       msg->addr,
+					       msg->buf, msg->len, flags);
+			hw_i2c_pioq_run(dev);
+		} else {
+			hw_i2c_dma_setup_read(msg->addr,
+					      msg->buf, msg->len, flags);
+
+			hw_i2c_dma_run(dev, I2C_READ);
+		}
+	} else {
+		if (dev->flags & MXS_I2C_PIOQUEUE_MODE) {
+			hw_i2c_pioq_setup_write(dev,
+						msg->addr,
+						msg->buf, msg->len, flags);
+			hw_i2c_pioq_run(dev);
+		} else {
+			hw_i2c_dma_setup_write(msg->addr,
+					       msg->buf, msg->len, flags);
+			hw_i2c_dma_run(dev, I2C_WRITE);
+		}
+	}
+
+	err = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
+							msecs_to_jiffies(1000)
+	    );
+	if (err <= 0) {
+		dev_dbg(dev->dev, "controller is timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	if ((!dev->cmd_err) && (msg->flags & I2C_M_RD))
+		hw_i2c_finish_read(dev, msg->buf, msg->len);
+
+	dev_dbg(dev->dev, "Done with err=%d\n", dev->cmd_err);
+
+	return dev->cmd_err;
+}
+
+static int
+mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+	int i;
+	int err;
+
+	if (!msgs->len)
+		return -EINVAL;
+
+	for (i = 0; i < num; i++) {
+		err = mxs_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
+		if (err)
+			break;
+	}
+
+	if (err == 0)
+		err = num;
+
+	return err;
+}
+
+static u32 mxs_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+static irqreturn_t mxs_i2c_dma_isr(int this_irq, void *dev_id)
+{
+	struct mxs_i2c_dev *mxs_i2c = dev_id;
+
+	LIST_HEAD(list);
+	mxs_dma_ack_irq(mxs_i2c->dma_chan);
+	mxs_dma_cooked(mxs_i2c->dma_chan, &list);
+
+	return IRQ_HANDLED;
+}
+
+#define I2C_IRQ_MASK 0x000000FF
+static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
+{
+	struct mxs_i2c_dev *mxs_i2c = dev_id;
+	u32 stat;
+	u32 done_mask =
+	    BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | BM_I2C_CTRL1_BUS_FREE_IRQ;
+
+	stat = __raw_readl(mxs_i2c->regbase + HW_I2C_CTRL1) & I2C_IRQ_MASK;
+	if (!stat)
+		return IRQ_NONE;
+
+	if (stat & BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
+		mxs_i2c->cmd_err = -EREMOTEIO;
+
+		/*
+		 * Stop DMA
+		 * Clear NAK
+		 */
+		__raw_writel(BM_I2C_CTRL1_CLR_GOT_A_NAK,
+			     mxs_i2c->regbase + HW_I2C_CTRL1_SET);
+		hw_i2c_dmachan_reset(mxs_i2c);
+		mxs_reset_block((void __iomem *)mxs_i2c->regbase, 1);
+		/* Will catch all error (IRQ mask) */
+		__raw_writel(0x0000FF00, mxs_i2c->regbase + HW_I2C_CTRL1_SET);
+
+		complete(&mxs_i2c->cmd_complete);
+
+		goto done;
+	}
+
+	/* Don't care about BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ */
+	if (stat & (BM_I2C_CTRL1_EARLY_TERM_IRQ |
+		    BM_I2C_CTRL1_MASTER_LOSS_IRQ |
+		    BM_I2C_CTRL1_SLAVE_STOP_IRQ | BM_I2C_CTRL1_SLAVE_IRQ)) {
+		mxs_i2c->cmd_err = -EIO;
+		complete(&mxs_i2c->cmd_complete);
+		goto done;
+	}
+	if ((stat & done_mask) == done_mask)
+		complete(&mxs_i2c->cmd_complete);
+
+done:
+	__raw_writel(stat, mxs_i2c->regbase + HW_I2C_CTRL1_CLR);
+	return IRQ_HANDLED;
+}
+
+static const struct i2c_algorithm mxs_i2c_algo = {
+	.master_xfer = mxs_i2c_xfer,
+	.functionality = mxs_i2c_func,
+};
+
+static int mxs_i2c_probe(struct platform_device *pdev)
+{
+	struct mxs_i2c_dev *mxs_i2c;
+	struct mxs_i2c_plat_data *pdata;
+	struct i2c_adapter *adap;
+	struct resource *res;
+	int err = 0;
+
+	mxs_i2c = kzalloc(sizeof(struct mxs_i2c_dev), GFP_KERNEL);
+	if (!mxs_i2c) {
+		dev_err(&pdev->dev, "no mem \n");
+		return -ENOMEM;
+	}
+
+	pdata = pdev->dev.platform_data;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no register base resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+	mxs_i2c->regbase = (unsigned long)IO_ADDRESS(res->start);
+
+	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no dma channel resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+	mxs_i2c->dma_chan = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no err_irq resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+	mxs_i2c->irq_err = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!res) {
+		dev_err(&pdev->dev, "no dma_irq resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+	mxs_i2c->irq_dma = res->start;
+
+	mxs_i2c->dev = &pdev->dev;
+	mxs_i2c->flags = pdata->pioqueue_mode ?
+	    MXS_I2C_PIOQUEUE_MODE : MXS_I2C_DMA_MODE;
+
+	err =
+	    request_irq(mxs_i2c->irq_err, mxs_i2c_isr, 0, pdev->name, mxs_i2c);
+	if (err) {
+		dev_err(&pdev->dev, "Can't get IRQ\n");
+		goto no_err_irq;
+	}
+
+	err =
+	    request_irq(mxs_i2c->irq_dma, mxs_i2c_dma_isr, 0, pdev->name,
+			mxs_i2c);
+	if (err) {
+		dev_err(&pdev->dev, "Can't get IRQ\n");
+		goto no_dma_irq;
+	}
+
+	/* reset I2C module */
+	mxs_reset_block((void __iomem *)mxs_i2c->regbase, 1);
+	platform_set_drvdata(pdev, mxs_i2c);
+
+	if (mxs_i2c->flags & MXS_I2C_PIOQUEUE_MODE)
+		__raw_writel(0x04, mxs_i2c->regbase + HW_I2C_QUEUECTRL_SET);
+
+	mxs_i2c->buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+	if (mxs_i2c->buf == NULL) {
+		dev_err(&pdev->dev, "HW Init failed\n");
+		goto init_failed;
+	} else {
+		err = hw_i2c_dma_init(pdev);
+		if (err) {
+			dev_err(&pdev->dev, "HW Init failed\n");
+			goto init_failed;
+		}
+	}
+
+	/* Will catch all error (IRQ mask) */
+	__raw_writel(0x0000FF00, mxs_i2c->regbase + HW_I2C_CTRL1_SET);
+
+	adap = &mxs_i2c->adapter;
+	strncpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
+	adap->owner = THIS_MODULE;
+	adap->class = I2C_CLASS_HWMON;
+	adap->algo = &mxs_i2c_algo;
+	adap->dev.parent = &pdev->dev;
+	adap->nr = pdev->id;
+	i2c_set_adapdata(adap, mxs_i2c);
+	err = i2c_add_numbered_adapter(adap);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to add adapter\n");
+		goto no_i2c_adapter;
+
+	}
+
+	return 0;
+
+no_i2c_adapter:
+	__raw_writel(BM_I2C_CTRL0_SFTRST, mxs_i2c->regbase + HW_I2C_CTRL0_SET);
+
+	if (mxs_i2c->flags & MXS_I2C_DMA_MODE)
+		hw_i2c_dma_uninit(pdev);
+	else
+		kfree(mxs_i2c->buf);
+init_failed:
+	free_irq(mxs_i2c->irq_dma, mxs_i2c);
+no_dma_irq:
+	free_irq(mxs_i2c->irq_err, mxs_i2c);
+no_err_irq:
+nores:
+	kfree(mxs_i2c);
+	return err;
+}
+
+static int mxs_i2c_remove(struct platform_device *pdev)
+{
+	struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev);
+	int res;
+
+	res = i2c_del_adapter(&mxs_i2c->adapter);
+	if (res)
+		return -EBUSY;
+
+	__raw_writel(BM_I2C_CTRL0_SFTRST, mxs_i2c->regbase + HW_I2C_CTRL0_SET);
+
+	if (mxs_i2c->flags & MXS_I2C_DMA_MODE)
+		hw_i2c_dma_uninit(pdev);
+	if (mxs_i2c->flags & MXS_I2C_PIOQUEUE_MODE)
+		hw_i2c_pioq_stop(mxs_i2c);
+
+	platform_set_drvdata(pdev, NULL);
+
+	free_irq(mxs_i2c->irq_err, mxs_i2c);
+	free_irq(mxs_i2c->irq_dma, mxs_i2c);
+
+	kfree(mxs_i2c->buf);
+	kfree(mxs_i2c);
+	return 0;
+}
+
+static struct platform_driver mxs_i2c_driver = {
+	.driver = {
+		   .name = "mxs-i2c",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxs_i2c_probe,
+	.remove = __devexit_p(mxs_i2c_remove),
+};
+
+static int __init mxs_i2c_init(void)
+{
+	return platform_driver_register(&mxs_i2c_driver);
+}
+
+subsys_initcall(mxs_i2c_init);
+
+static void __exit mxs_i2c_exit(void)
+{
+	platform_driver_unregister(&mxs_i2c_driver);
+}
+
+module_exit(mxs_i2c_exit);
+
+MODULE_AUTHOR("Embedded Alley Solutions, Inc/Freescale Inc");
+MODULE_DESCRIPTION("MXS I2C Bus Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-mxs.h b/drivers/i2c/busses/i2c-mxs.h
new file mode 100644
index 000000000000..4ddca007624a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mxs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _I2C_H
+#define _I2C_H
+
+#define I2C_READ   1
+#define I2C_WRITE  0
+
+struct mxs_i2c_dev {
+	struct device		*dev;
+	void			*buf;
+	unsigned long		regbase;
+	u32			flags;
+#define	MXS_I2C_DMA_MODE	0x1
+#define	MXS_I2C_PIOQUEUE_MODE	0x2
+	int			dma_chan;
+	int			irq_dma;
+	int			irq_err;
+	struct completion	cmd_complete;
+	u32			cmd_err;
+	struct i2c_adapter	adapter;
+	spinlock_t		lock;
+	wait_queue_head_t	queue;
+};
+#endif
diff --git a/drivers/i2c/busses/i2c-s6000.c b/drivers/i2c/busses/i2c-s6000.c
index c91359f4965c..a19af5101d1b 100644
--- a/drivers/i2c/busses/i2c-s6000.c
+++ b/drivers/i2c/busses/i2c-s6000.c
@@ -276,7 +276,7 @@ static int __devinit s6i2c_probe(struct platform_device *dev)
 	}
 	iface->res = request_mem_region(iface->res->start,
 					resource_size(iface->res),
-					dev->dev.bus_id);
+					dev_name(&dev->dev));
 	if (!iface->res) {
 		rc = -EBUSY;
 		goto err_out;
diff --git a/drivers/i2c/busses/i2c-stmp378x.c b/drivers/i2c/busses/i2c-stmp378x.c
new file mode 100644
index 000000000000..08c20f80f897
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stmp378x.c
@@ -0,0 +1,345 @@
+/*
+ * Freescale STMP378X I2C bus driver
+ *
+ * Author: Dmitrij Frasenyak <sed@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/platform.h>
+#include <mach/regs-i2c.h>
+#include <mach/regs-apbx.h>
+#include <mach/i2c.h>
+#include <mach/platform.h>
+
+static void reset_i2c_module(void)
+{
+	u32 ctrl;
+	int count;
+	count = 1000;
+	__raw_writel(BM_I2C_CTRL0_SFTRST, REGS_I2C_BASE + HW_I2C_CTRL0_SET);
+	udelay(10); /* Reseting the module can take multiple clocks.*/
+	while (--count && (!(__raw_readl(REGS_I2C_BASE + HW_I2C_CTRL0) & BM_I2C_CTRL0_CLKGATE)))
+		udelay(1);
+
+	if (!count) {
+		printk(KERN_ERR "timeout reseting the module\n");
+		BUG();
+	}
+
+	/* take controller out of reset */
+	__raw_writel(BM_I2C_CTRL0_SFTRST | BM_I2C_CTRL0_CLKGATE,
+		REGS_I2C_BASE + HW_I2C_CTRL0_CLR);
+	udelay(10);
+	/* Wil catch all error (IRQ mask) */
+	__raw_writel(0x0000FF00, REGS_I2C_BASE + HW_I2C_CTRL1_SET);
+}
+
+/*
+ * Low level master read/write transaction.
+ */
+static int stmp378x_i2c_xfer_msg(struct i2c_adapter *adap,
+				 struct i2c_msg *msg, int stop)
+{
+	struct stmp378x_i2c_dev *dev = i2c_get_adapdata(adap);
+	int err;
+
+	init_completion(&dev->cmd_complete);
+	dev->cmd_err = 0;
+
+	dev_dbg(dev->dev, " Start XFER ===>\n");
+	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
+		msg->addr, msg->len, msg->flags, stop);
+
+	if ((msg->len == 0) || (msg->len > (PAGE_SIZE - 1)))
+		return -EINVAL;
+
+	if (msg->flags & I2C_M_RD) {
+		hw_i2c_setup_read(msg->addr ,
+				  msg->buf ,
+				  msg->len,
+				  stop ? BM_I2C_CTRL0_POST_SEND_STOP : 0);
+
+		hw_i2c_run(1); /* read */
+	} else {
+		hw_i2c_setup_write(msg->addr ,
+				   msg->buf ,
+				   msg->len,
+				   stop ? BM_I2C_CTRL0_POST_SEND_STOP : 0);
+
+		hw_i2c_run(0); /* write */
+	}
+
+	err = wait_for_completion_interruptible_timeout(
+		&dev->cmd_complete,
+		msecs_to_jiffies(1000)
+		);
+
+	if (err < 0) {
+		dev_dbg(dev->dev, "controler is timed out\n");
+		return -ETIMEDOUT;
+	}
+	if ((!dev->cmd_err) && (msg->flags & I2C_M_RD))
+		hw_i2c_finish_read(msg->buf, msg->len);
+
+	dev_dbg(dev->dev, "<============= Done with err=%d\n", dev->cmd_err);
+
+
+	return dev->cmd_err;
+}
+
+
+static int
+stmp378x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+	int i;
+	int err;
+
+	if (!msgs->len)
+		return -EINVAL;
+
+	for (i = 0; i < num; i++) {
+		err = stmp378x_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
+		if (err)
+			break;
+	}
+
+	if (err == 0)
+		err = num;
+
+	return err;
+}
+
+static u32
+stmp378x_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+/*
+ * Debug. Don't need dma_irq for the final version
+ */
+
+static irqreturn_t
+stmp378x_i2c_dma_isr(int this_irq, void *dev_id)
+{
+	hw_i2c_clear_dma_interrupt();
+	return IRQ_HANDLED;
+
+}
+
+#define I2C_IRQ_MASK 0x000000FF
+
+static irqreturn_t
+stmp378x_i2c_isr(int this_irq, void *dev_id)
+{
+	struct stmp378x_i2c_dev *dev = dev_id;
+	u32 stat, ctrl;
+	u32 done_mask =
+		BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ |
+		BM_I2C_CTRL1_BUS_FREE_IRQ ;
+
+	stat = __raw_readl(REGS_I2C_BASE + HW_I2C_CTRL1) & I2C_IRQ_MASK;
+	if (!stat)
+		return IRQ_NONE;
+
+	if (stat & BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
+		dev->cmd_err = -EREMOTEIO;
+
+		/*
+		 * Stop DMA
+		 * Clear NAK
+		 */
+		__raw_writel(BM_I2C_CTRL1_CLR_GOT_A_NAK,
+			REGS_I2C_BASE + HW_I2C_CTRL1_SET);
+		hw_i2c_reset_dma();
+		reset_i2c_module();
+
+		complete(&dev->cmd_complete);
+
+		goto done;
+	}
+
+/* Don't care about  BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ */
+	if (stat & (
+		    BM_I2C_CTRL1_EARLY_TERM_IRQ |
+		    BM_I2C_CTRL1_MASTER_LOSS_IRQ |
+		    BM_I2C_CTRL1_SLAVE_STOP_IRQ |
+		    BM_I2C_CTRL1_SLAVE_IRQ
+		    )) {
+		dev->cmd_err = -EIO;
+		complete(&dev->cmd_complete);
+		goto done;
+	}
+	if ((stat & done_mask)  == done_mask)
+		complete(&dev->cmd_complete);
+
+
+done:
+	__raw_writel(stat, REGS_I2C_BASE + HW_I2C_CTRL1_CLR);
+	return IRQ_HANDLED;
+}
+
+static const struct i2c_algorithm stmp378x_i2c_algo = {
+	.master_xfer	= stmp378x_i2c_xfer,
+	.functionality	= stmp378x_i2c_func,
+};
+
+
+static int
+stmp378x_i2c_probe(struct platform_device *pdev)
+{
+	struct stmp378x_i2c_dev	*dev;
+	struct i2c_adapter	*adap;
+	struct resource		*irq;
+	u32 ctrl;
+	int err = 0;
+
+	/* NOTE: driver uses the static register mapping */
+	dev = kzalloc(sizeof(struct stmp378x_i2c_dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "no mem \n");
+		return -ENOMEM;
+	}
+
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); /* Error */
+	if (!irq) {
+		dev_err(&pdev->dev, "no err_irq resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+	dev->irq_err = irq->start;
+
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); /* DMA */
+	if (!irq) {
+		dev_err(&pdev->dev, "no dma_irq resource\n");
+		err = -ENODEV;
+		goto nores;
+	}
+
+	dev->irq_dma = irq->start;
+	dev->dev = &pdev->dev;
+
+	err = request_irq(dev->irq_err, stmp378x_i2c_isr, 0, pdev->name, dev);
+	if (err) {
+		dev_err(&pdev->dev, "Can't get IRQ\n");
+		goto no_err_irq;
+	}
+
+	err = request_irq(dev->irq_dma,
+			  stmp378x_i2c_dma_isr,
+			  0, pdev->name, dev);
+	if (err) {
+		dev_err(&pdev->dev, "Can't get IRQ\n");
+		goto no_dma_irq;
+	}
+
+	err = hw_i2c_init(&pdev->dev);
+	if (err) {
+		dev_err(&pdev->dev, "HW Init failed\n");
+		goto init_failed;
+	}
+
+	/* Will catch all error (IRQ mask) */
+	__raw_writel(0x0000FF00,
+		REGS_I2C_BASE + HW_I2C_CTRL1_SET);
+
+	adap = &dev->adapter;
+	i2c_set_adapdata(adap, dev);
+	adap->owner = THIS_MODULE;
+	adap->class = I2C_CLASS_HWMON;
+	strncpy(adap->name, "378x I2C adapter", sizeof(adap->name));
+	adap->algo = &stmp378x_i2c_algo;
+	adap->dev.parent = &pdev->dev;
+
+	adap->nr = pdev->id;
+	err = i2c_add_numbered_adapter(adap);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to add adapter\n");
+		goto no_i2c_adapter;
+
+	}
+
+	return 0;
+
+no_i2c_adapter:
+	hw_i2c_stop(dev->dev);
+init_failed:
+	free_irq(dev->irq_dma, dev);
+no_dma_irq:
+	free_irq(dev->irq_err, dev);
+no_err_irq:
+nores:
+	kfree(dev);
+	return err;
+}
+
+static int
+stmp378x_i2c_remove(struct platform_device *pdev)
+{
+	struct stmp378x_i2c_dev	*dev = platform_get_drvdata(pdev);
+	int res;
+
+	res = i2c_del_adapter(&dev->adapter);
+	if (res)
+		return -EBUSY;
+
+	hw_i2c_stop(dev->dev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	free_irq(dev->irq_err, dev);
+	free_irq(dev->irq_dma, dev);
+
+	kfree(dev);
+	return 0;
+}
+
+static struct platform_driver stmp378x_i2c_driver = {
+	.probe		= stmp378x_i2c_probe,
+	.remove		= __devexit_p(stmp378x_i2c_remove),
+	.driver		= {
+		.name	= "i2c_stmp",
+		.owner	= THIS_MODULE,
+	},
+};
+
+/* I2C may be needed to bring up other drivers */
+
+static int __init stmp378x_i2c_init_driver(void)
+{
+	return platform_driver_register(&stmp378x_i2c_driver);
+}
+subsys_initcall(stmp378x_i2c_init_driver);
+
+static void __exit stmp378x_i2c_exit_driver(void)
+{
+	platform_driver_unregister(&stmp378x_i2c_driver);
+}
+module_exit(stmp378x_i2c_exit_driver);
+
+MODULE_AUTHOR("old_chap@embeddedalley.com");
+MODULE_DESCRIPTION("IIC for Freescale STMP378x");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/mxc_i2c.c b/drivers/i2c/busses/mxc_i2c.c
new file mode 100644
index 000000000000..2ecec62aeabe
--- /dev/null
+++ b/drivers/i2c/busses/mxc_i2c.c
@@ -0,0 +1,805 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_i2c.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC I2C buses.
+ *
+ * Based on i2c driver algorithm for PCF8584 adapters
+ *
+ * @ingroup MXCI2C
+ */
+
+/*
+ * Include Files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include "mxc_i2c_reg.h"
+
+/*!
+ * In case the MXC device has multiple I2C modules, this structure is used to
+ * store information specific to each I2C module.
+ */
+typedef struct {
+	/*!
+	 * This structure is used to identify the physical i2c bus along with
+	 * the access algorithms necessary to access it.
+	 */
+	struct i2c_adapter adap;
+
+	/*!
+	 * This waitqueue is used to wait for the data transfer to complete.
+	 */
+	wait_queue_head_t wq;
+
+	/*!
+	 * The base address of the I2C device.
+	 */
+	void __iomem *membase;
+
+	/*!
+	 * The interrupt number used by the I2C device.
+	 */
+	int irq;
+
+	/*!
+	 * The default clock divider value to be used.
+	 */
+	unsigned int clkdiv;
+
+	/*!
+	 * The clock source for the device.
+	 */
+	struct clk *clk;
+
+	/*!
+	 * The current power state of the device
+	 */
+	bool low_power;
+
+	/*!
+	 * Boolean to indicate if data was transferred
+	 */
+	bool transfer_done;
+
+	/*!
+	 * Boolean to indicate if we received an ACK for the data transmitted
+	 */
+	bool tx_success;
+} mxc_i2c_device;
+
+struct clk_div_table {
+	int reg_value;
+	int div;
+};
+
+static const struct clk_div_table i2c_clk_table[] = {
+	{0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28},
+	{0, 30}, {1, 32}, {0x24, 32}, {2, 36},
+	{0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44},
+	{4, 48}, {0x28, 48}, {5, 52}, {0x29, 56},
+	{6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72},
+	{8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96},
+	{0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128},
+	{0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192},
+	{0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256},
+	{0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384},
+	{0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512},
+	{0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768},
+	{0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024},
+	{0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536},
+	{0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048},
+	{0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840},
+	{0, 0}
+};
+
+extern void gpio_i2c_active(int i2c_num);
+extern void gpio_i2c_inactive(int i2c_num);
+
+/*!
+ * Transmit a \b STOP signal to the slave device.
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ */
+static void mxc_i2c_stop(mxc_i2c_device * dev)
+{
+	unsigned int cr, sr;
+	int retry = 16;
+
+	cr = readw(dev->membase + MXC_I2CR);
+	cr &= ~(MXC_I2CR_MSTA | MXC_I2CR_MTX);
+	writew(cr, dev->membase + MXC_I2CR);
+
+	/* Wait till the Bus Busy bit is reset */
+	sr = readw(dev->membase + MXC_I2SR);
+	while (retry-- && ((sr & MXC_I2SR_IBB))) {
+		udelay(3);
+		sr = readw(dev->membase + MXC_I2SR);
+	}
+	if (retry <= 0)
+		dev_err(&dev->adap.dev, "Could not set I2C Bus Busy bit"
+			" to zero.\n");
+}
+
+/*!
+ * Wait for the transmission of the data byte to complete. This function waits
+ * till we get a signal from the interrupt service routine indicating completion
+ * of the address cycle or we time out.
+ *
+ * @param   dev         the mxc i2c structure used to get to the right i2c device
+ * @param   trans_flag  transfer flag
+ *
+ *
+ * @return  The function returns 0 on success or -1 if an ack was not received
+ */
+
+static int mxc_i2c_wait_for_tc(mxc_i2c_device * dev, int trans_flag)
+{
+	int retry = 16;
+
+	while (retry-- && !dev->transfer_done) {
+		wait_event_interruptible_timeout(dev->wq,
+						 dev->transfer_done,
+						 dev->adap.timeout);
+	}
+	dev->transfer_done = false;
+
+	if (retry <= 0) {
+		/* Unable to send data */
+		dev_err(&dev->adap.dev, "Data not transmitted\n");
+		return -1;
+	}
+
+	if (!dev->tx_success) {
+		/* An ACK was not received for transmitted byte */
+		dev_err(&dev->adap.dev, "ACK not received \n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*!
+ * Transmit a \b START signal to the slave device.
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ * @param   *msg  pointer to a message structure that contains the slave
+ *                address
+ *
+ * @return  The function returns EBUSY on failure, 0 on success.
+ */
+static int mxc_i2c_start(mxc_i2c_device *dev, struct i2c_msg *msg)
+{
+	volatile unsigned int cr, sr;
+	unsigned int addr_trans;
+	int retry = 16;
+
+	/*
+	 * Set the slave address and the requested transfer mode
+	 * in the data register
+	 */
+	addr_trans = msg->addr << 1;
+	if (msg->flags & I2C_M_RD) {
+		addr_trans |= 0x01;
+	}
+
+	/* Set the Master bit */
+	cr = readw(dev->membase + MXC_I2CR);
+	cr |= MXC_I2CR_MSTA;
+	writew(cr, dev->membase + MXC_I2CR);
+
+	/* Wait till the Bus Busy bit is set */
+	sr = readw(dev->membase + MXC_I2SR);
+	while (retry-- && (!(sr & MXC_I2SR_IBB))) {
+		udelay(3);
+		sr = readw(dev->membase + MXC_I2SR);
+	}
+	if (retry <= 0) {
+		dev_err(&dev->adap.dev, "Could not grab Bus ownership\n");
+		return -EBUSY;
+	}
+
+	/* Set the Transmit bit */
+	cr = readw(dev->membase + MXC_I2CR);
+	cr |= MXC_I2CR_MTX;
+	writew(cr, dev->membase + MXC_I2CR);
+
+	writew(addr_trans, dev->membase + MXC_I2DR);
+	return 0;
+}
+
+/*!
+ * Transmit a \b REPEAT START to the slave device
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ * @param   *msg  pointer to a message structure that contains the slave
+ *                address
+ */
+static int mxc_i2c_repstart(mxc_i2c_device *dev, struct i2c_msg *msg)
+{
+	volatile unsigned int cr, sr;
+	unsigned int addr_trans;
+	int retry = 16;
+
+	/*
+	 * Set the slave address and the requested transfer mode
+	 * in the data register
+	 */
+	addr_trans = msg->addr << 1;
+	if (msg->flags & I2C_M_RD) {
+		addr_trans |= 0x01;
+	}
+	cr = readw(dev->membase + MXC_I2CR);
+	cr |= MXC_I2CR_RSTA;
+	writew(cr, dev->membase + MXC_I2CR);
+	/* Wait till the Bus Busy bit is set */
+	sr = readw(dev->membase + MXC_I2SR);
+	while (retry-- && (!(sr & MXC_I2SR_IBB))) {
+		udelay(3);
+		sr = readw(dev->membase + MXC_I2SR);
+	}
+	if (retry <= 0) {
+		dev_err(&dev->adap.dev, "Could not grab Bus ownership\n");
+		return -EBUSY;
+	}
+	writew(addr_trans, dev->membase + MXC_I2DR);
+	return 0;
+}
+
+/*!
+ * Read the received data. The function waits till data is available or times
+ * out. Generates a stop signal if this is the last message to be received.
+ * Sends an ack for all the bytes received except the last byte.
+ *
+ * @param  dev       the mxc i2c structure used to get to the right i2c device
+ * @param  *msg      pointer to a message structure that contains the slave
+ *                   address and a pointer to the receive buffer
+ * @param  last      indicates that this is the last message to be received
+ * @param  addr_comp flag indicates that we just finished the address cycle
+ *
+ * @return  The function returns the number of bytes read or -1 on time out.
+ */
+static int mxc_i2c_readbytes(mxc_i2c_device * dev, struct i2c_msg *msg,
+			     int last, int addr_comp)
+{
+	int i;
+	char *buf = msg->buf;
+	int len = msg->len;
+	volatile unsigned int cr;
+
+	cr = readw(dev->membase + MXC_I2CR);
+	/*
+	 * Clear MTX to switch to receive mode.
+	 */
+	cr &= ~MXC_I2CR_MTX;
+	/*
+	 * Clear the TXAK bit to gen an ack when receiving only one byte.
+	 */
+	if (len == 1) {
+		cr |= MXC_I2CR_TXAK;
+	} else {
+		cr &= ~MXC_I2CR_TXAK;
+	}
+	writew(cr, dev->membase + MXC_I2CR);
+	/*
+	 * Dummy read only at the end of an address cycle
+	 */
+	if (addr_comp > 0) {
+		readw(dev->membase + MXC_I2DR);
+	}
+
+	for (i = 0; i < len; i++) {
+		/*
+		 * Wait for data transmission to complete
+		 */
+		if (mxc_i2c_wait_for_tc(dev, msg->flags)) {
+			mxc_i2c_stop(dev);
+			return -1;
+		}
+		/*
+		 * Do not generate an ACK for the last byte
+		 */
+		if (i == (len - 2)) {
+			cr = readw(dev->membase + MXC_I2CR);
+			cr |= MXC_I2CR_TXAK;
+			writew(cr, dev->membase + MXC_I2CR);
+		} else if (i == (len - 1)) {
+			if (last) {
+				mxc_i2c_stop(dev);
+			}
+		}
+		/* Read the data */
+		*buf++ = readw(dev->membase + MXC_I2DR);
+	}
+
+	return i;
+}
+
+/*!
+ * Write the data to the data register. Generates a stop signal if this is
+ * the last message to be sent or if no ack was received for the data sent.
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ * @param   *msg  pointer to a message structure that contains the slave
+ *                address and data to be sent
+ * @param   last  indicates that this is the last message to be received
+ *
+ * @return  The function returns the number of bytes written or -1 on time out
+ *          or if no ack was received for the data that was sent.
+ */
+static int mxc_i2c_writebytes(mxc_i2c_device * dev, struct i2c_msg *msg,
+			      int last)
+{
+	int i;
+	char *buf = msg->buf;
+	int len = msg->len;
+	volatile unsigned int cr;
+
+	cr = readw(dev->membase + MXC_I2CR);
+	/* Set MTX to switch to transmit mode */
+	cr |= MXC_I2CR_MTX;
+	writew(cr, dev->membase + MXC_I2CR);
+
+	for (i = 0; i < len; i++) {
+		/*
+		 * Write the data
+		 */
+		writew(*buf++, dev->membase + MXC_I2DR);
+		if (mxc_i2c_wait_for_tc(dev, msg->flags)) {
+			mxc_i2c_stop(dev);
+			return -1;
+		}
+	}
+	if (last > 0) {
+		mxc_i2c_stop(dev);
+	}
+
+	return i;
+}
+
+/*!
+ * Function enables the I2C module and initializes the registers.
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ * @param   trans_flag  transfer flag
+ */
+static void mxc_i2c_module_en(mxc_i2c_device * dev, int trans_flag)
+{
+	clk_enable(dev->clk);
+	/* Set the frequency divider */
+	writew(dev->clkdiv, dev->membase + MXC_IFDR);
+	/* Clear the status register */
+	writew(0x0, dev->membase + MXC_I2SR);
+	/* Enable I2C and its interrupts */
+	writew(MXC_I2CR_IEN, dev->membase + MXC_I2CR);
+	writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, dev->membase + MXC_I2CR);
+}
+
+/*!
+ * Disables the I2C module.
+ *
+ * @param   dev   the mxc i2c structure used to get to the right i2c device
+ */
+static void mxc_i2c_module_dis(mxc_i2c_device * dev)
+{
+	writew(0x0, dev->membase + MXC_I2CR);
+	clk_disable(dev->clk);
+}
+
+/*!
+ * The function is registered in the adapter structure. It is called when an MXC
+ * driver wishes to transfer data to a device connected to the I2C device.
+ *
+ * @param   adap   adapter structure for the MXC i2c device
+ * @param   msgs[] array of messages to be transferred to the device
+ * @param   num    number of messages to be transferred to the device
+ *
+ * @return  The function returns the number of messages transferred,
+ *          \b -EREMOTEIO on I2C failure and a 0 if the num argument is
+ *          less than 0.
+ */
+static int mxc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
+			int num)
+{
+	mxc_i2c_device *dev = (mxc_i2c_device *) (i2c_get_adapdata(adap));
+	int i, ret = 0, addr_comp = 0;
+	volatile unsigned int sr;
+	int retry = 5;
+
+	if (dev->low_power) {
+		dev_err(&dev->adap.dev, "I2C Device in low power mode\n");
+		return -EREMOTEIO;
+	}
+
+	if (num < 1) {
+		return 0;
+	}
+
+	mxc_i2c_module_en(dev, msgs[0].flags);
+	sr = readw(dev->membase + MXC_I2SR);
+	/*
+	 * Check bus state
+	 */
+
+	while ((sr & MXC_I2SR_IBB) && retry--) {
+		udelay(5);
+		sr = readw(dev->membase + MXC_I2SR);
+	}
+
+	if ((sr & MXC_I2SR_IBB) && retry < 0) {
+		mxc_i2c_module_dis(dev);
+		dev_err(&dev->adap.dev, "Bus busy\n");
+		return -EREMOTEIO;
+	}
+
+	//gpio_i2c_active(dev->adap.id);
+	dev->transfer_done = false;
+	dev->tx_success = false;
+	for (i = 0; i < num && ret >= 0; i++) {
+		addr_comp = 0;
+		/*
+		 * Send the slave address and transfer direction in the
+		 * address cycle
+		 */
+		if (i == 0) {
+			/*
+			 * Send a start or repeat start signal
+			 */
+			if (mxc_i2c_start(dev, &msgs[0]))
+				return -EREMOTEIO;
+			/* Wait for the address cycle to complete */
+			if (mxc_i2c_wait_for_tc(dev, msgs[0].flags)) {
+				mxc_i2c_stop(dev);
+				//gpio_i2c_inactive(dev->adap.id);
+				mxc_i2c_module_dis(dev);
+				return -EREMOTEIO;
+			}
+			addr_comp = 1;
+		} else {
+			/*
+			 * Generate repeat start only if required i.e the address
+			 * changed or the transfer direction changed
+			 */
+			if ((msgs[i].addr != msgs[i - 1].addr) ||
+			    ((msgs[i].flags & I2C_M_RD) !=
+			     (msgs[i - 1].flags & I2C_M_RD))) {
+				mxc_i2c_repstart(dev, &msgs[i]);
+				/* Wait for the address cycle to complete */
+				if (mxc_i2c_wait_for_tc(dev, msgs[i].flags)) {
+					mxc_i2c_stop(dev);
+					//gpio_i2c_inactive(dev->adap.id);
+					mxc_i2c_module_dis(dev);
+					return -EREMOTEIO;
+				}
+				addr_comp = 1;
+			}
+		}
+
+		/* Transfer the data */
+		if (msgs[i].flags & I2C_M_RD) {
+			/* Read the data */
+			ret = mxc_i2c_readbytes(dev, &msgs[i], (i + 1 == num),
+						addr_comp);
+			if (ret < 0) {
+				dev_err(&dev->adap.dev, "mxc_i2c_readbytes:"
+					" fail.\n");
+				break;
+			}
+		} else {
+			/* Write the data */
+			ret = mxc_i2c_writebytes(dev, &msgs[i], (i + 1 == num));
+			if (ret < 0) {
+				dev_err(&dev->adap.dev, "mxc_i2c_writebytes:"
+					" fail.\n");
+				break;
+			}
+		}
+	}
+
+	//gpio_i2c_inactive(dev->adap.id);
+	mxc_i2c_module_dis(dev);
+	/*
+	 * Decrease by 1 as we do not want Start message to be included in
+	 * the count
+	 */
+	return (i < 0 ? ret : i);
+}
+
+/*!
+ * Returns the i2c functionality supported by this driver.
+ *
+ * @param   adap adapter structure for this i2c device
+ *
+ * @return Returns the functionality that is supported.
+ */
+static u32 mxc_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+/*!
+ * Stores the pointers for the i2c algorithm functions. The algorithm functions
+ * is used by the i2c bus driver to talk to the i2c bus
+ */
+static struct i2c_algorithm mxc_i2c_algorithm = {
+	.master_xfer = mxc_i2c_xfer,
+	.functionality = mxc_i2c_func
+};
+
+/*!
+ * Interrupt Service Routine. It signals to the process about the data transfer
+ * completion. Also sets a flag if bus arbitration is lost.
+ * @param   irq    the interrupt number
+ * @param   dev_id driver private data
+ *
+ * @return  The function returns \b IRQ_HANDLED.
+ */
+static irqreturn_t mxc_i2c_handler(int irq, void *dev_id)
+{
+	mxc_i2c_device *dev = dev_id;
+	volatile unsigned int sr, cr;
+
+	sr = readw(dev->membase + MXC_I2SR);
+	cr = readw(dev->membase + MXC_I2CR);
+
+	/*
+	 * Clear the interrupt bit
+	 */
+	writew(0x0, dev->membase + MXC_I2SR);
+
+	if (sr & MXC_I2SR_IAL) {
+		dev_err(&dev->adap.dev, "Bus Arbitration lost\n");
+	} else {
+		/* Interrupt due byte transfer completion */
+		dev->tx_success = true;
+		/* Check if RXAK is received in Transmit mode */
+		if ((cr & MXC_I2CR_MTX) && (sr & MXC_I2SR_RXAK)) {
+			dev->tx_success = false;
+		}
+		dev->transfer_done = true;
+		wake_up_interruptible(&dev->wq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is called to put the I2C adapter in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which I2C
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int mxci2c_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	mxc_i2c_device *mxcdev = platform_get_drvdata(pdev);
+	volatile unsigned int sr = 0;
+
+	if (mxcdev == NULL) {
+		return -1;
+	}
+
+	/* Prevent further calls to be processed */
+	mxcdev->low_power = true;
+	/* Wait till we finish the current transfer */
+	sr = readw(mxcdev->membase + MXC_I2SR);
+	while (sr & MXC_I2SR_IBB) {
+		msleep(10);
+		sr = readw(mxcdev->membase + MXC_I2SR);
+	}
+	gpio_i2c_inactive(mxcdev->adap.id);
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the I2C adapter back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which I2C
+ *                to resume
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxci2c_resume(struct platform_device *pdev)
+{
+	mxc_i2c_device *mxcdev = platform_get_drvdata(pdev);
+
+	if (mxcdev == NULL)
+		return -1;
+
+	mxcdev->low_power = false;
+	gpio_i2c_active(mxcdev->adap.id);
+
+	return 0;
+}
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions
+ *
+ * @return  The function always returns 0.
+ */
+static int mxci2c_probe(struct platform_device *pdev)
+{
+	mxc_i2c_device *mxc_i2c;
+	struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data;
+	struct resource *res;
+	int id = pdev->id;
+	u32 clk_freq;
+	int ret = 0;
+	int i;
+
+	mxc_i2c = kzalloc(sizeof(mxc_i2c_device), GFP_KERNEL);
+	if (!mxc_i2c) {
+		return -ENOMEM;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto err1;
+	}
+	mxc_i2c->membase = ioremap(res->start, res->end - res->start + 1);
+
+	/*
+	 * Request the I2C interrupt
+	 */
+	mxc_i2c->irq = platform_get_irq(pdev, 0);
+	if (mxc_i2c->irq < 0) {
+		ret = mxc_i2c->irq;
+		goto err2;
+	}
+
+	ret = request_irq(mxc_i2c->irq, mxc_i2c_handler,
+			  0, pdev->name, mxc_i2c);
+	if (ret < 0) {
+		goto err2;
+	}
+
+	init_waitqueue_head(&mxc_i2c->wq);
+
+	mxc_i2c->low_power = false;
+
+	gpio_i2c_active(id);
+
+	mxc_i2c->clk = clk_get(&pdev->dev, "i2c_clk");
+	clk_freq = clk_get_rate(mxc_i2c->clk);
+	mxc_i2c->clkdiv = -1;
+	if (i2c_plat_data->i2c_clk) {
+		/* Calculate divider and round up any fractional part */
+		int div = (clk_freq + i2c_plat_data->i2c_clk - 1) /
+		    i2c_plat_data->i2c_clk;
+		for (i = 0; i2c_clk_table[i].div != 0; i++) {
+			if (i2c_clk_table[i].div >= div) {
+				mxc_i2c->clkdiv = i2c_clk_table[i].reg_value;
+				break;
+			}
+		}
+	}
+	if (mxc_i2c->clkdiv == -1) {
+		i--;
+		mxc_i2c->clkdiv = 0x1F;	/* Use max divider */
+	}
+	dev_dbg(&pdev->dev, "i2c speed is %d/%d = %d bps, reg val = 0x%02X\n",
+		clk_freq, i2c_clk_table[i].div,
+		clk_freq / i2c_clk_table[i].div, mxc_i2c->clkdiv);
+
+	/*
+	 * Set the adapter information
+	 */
+	strlcpy(mxc_i2c->adap.name, pdev->name, 48);
+	mxc_i2c->adap.id = mxc_i2c->adap.nr = id;
+	mxc_i2c->adap.algo = &mxc_i2c_algorithm;
+	mxc_i2c->adap.timeout = 1;
+	platform_set_drvdata(pdev, mxc_i2c);
+	i2c_set_adapdata(&mxc_i2c->adap, mxc_i2c);
+	if ((ret = i2c_add_numbered_adapter(&mxc_i2c->adap)) < 0) {
+		goto err3;
+	}
+
+	printk(KERN_INFO "MXC I2C driver\n");
+	return 0;
+
+      err3:
+	free_irq(mxc_i2c->irq, mxc_i2c);
+	gpio_i2c_inactive(id);
+      err2:
+	iounmap(mxc_i2c->membase);
+      err1:
+	dev_err(&pdev->dev, "failed to probe i2c adapter\n");
+	kfree(mxc_i2c);
+	return ret;
+}
+
+/*!
+ * Dissociates the driver from the I2C device.
+ *
+ * @param   pdev   the device structure used to give information on which I2C
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxci2c_remove(struct platform_device *pdev)
+{
+	mxc_i2c_device *mxc_i2c = platform_get_drvdata(pdev);
+	int id = pdev->id;
+
+	free_irq(mxc_i2c->irq, mxc_i2c);
+	i2c_del_adapter(&mxc_i2c->adap);
+	gpio_i2c_inactive(id);
+	clk_put(mxc_i2c->clk);
+	platform_set_drvdata(pdev, NULL);
+	iounmap(mxc_i2c->membase);
+	kfree(mxc_i2c);
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxci2c_driver = {
+	.driver = {
+		   .name = "mxc_i2c",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxci2c_probe,
+	.remove = mxci2c_remove,
+	.suspend_late = mxci2c_suspend,
+	.resume_early = mxci2c_resume,
+};
+
+/*!
+ * Function requests the interrupts and registers the i2c adapter structures.
+ *
+ * @return The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxc_i2c_init(void)
+{
+	/* Register the device driver structure. */
+	return platform_driver_register(&mxci2c_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxc_i2c_exit(void)
+{
+	platform_driver_unregister(&mxci2c_driver);
+}
+
+subsys_initcall(mxc_i2c_init);
+module_exit(mxc_i2c_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC I2C driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/mxc_i2c_hs.c b/drivers/i2c/busses/mxc_i2c_hs.c
new file mode 100644
index 000000000000..16cf8a8d66e2
--- /dev/null
+++ b/drivers/i2c/busses/mxc_i2c_hs.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include "mxc_i2c_hs_reg.h"
+
+typedef struct {
+	struct device *dev;
+
+	void __iomem *reg_base_virt;
+	unsigned long reg_base_phy;
+	int irq;
+	unsigned int speed;
+	struct clk *ipg_clk;
+	struct clk *serial_clk;
+	bool low_power;
+
+	struct i2c_msg *msg;
+	int index;
+} mxc_i2c_hs;
+
+struct clk_div_table {
+	int reg_value;
+	int div;
+};
+
+static const struct clk_div_table i2c_clk_table[] = {
+	{0x0, 16}, {0x1, 18}, {0x2, 20}, {0x3, 22},
+	{0x20, 24}, {0x21, 26}, {0x22, 28}, {0x23, 30},
+	{0x4, 32}, {0x5, 36}, {0x6, 40}, {0x7, 44},
+	{0x24, 48}, {0x25, 52}, {0x26, 56}, {0x27, 60},
+	{0x8, 64}, {0x9, 72}, {0xa, 80}, {0xb, 88},
+	{0x28, 96}, {0x29, 104}, {0x2a, 112}, {0x2b, 120},
+	{0xc, 128}, {0xd, 144}, {0xe, 160}, {0xf, 176},
+	{0x2c, 192}, {0x2d, 208}, {0x2e, 224}, {0x2f, 240},
+	{0x10, 256}, {0x11, 288}, {0x12, 320}, {0x13, 352},
+	{0x30, 384}, {0x31, 416}, {0x32, 448}, {0x33, 480},
+	{0x14, 512}, {0x15, 576}, {0x16, 640}, {0x17, 704},
+	{0x34, 768}, {0x35, 832}, {0x36, 896}, {0x37, 960},
+	{0x18, 1024}, {0x19, 1152}, {0x1a, 1280}, {0x1b, 1408},
+	{0x38, 1536}, {0x39, 1664}, {0x3a, 1792}, {0x3b, 1920},
+	{0x1c, 2048}, {0x1d, 2304}, {0x1e, 2560}, {0x1f, 2816},
+	{0x3c, 3072}, {0x3d, 3328}, {0x3E, 3584}, {0x3F, 3840},
+	{-1, -1}
+};
+
+static struct i2c_adapter *adap;
+
+extern void gpio_i2c_hs_inactive(void);
+extern void gpio_i2c_hs_active(void);
+
+static u16 reg_read(mxc_i2c_hs *i2c_hs, u32 reg_offset)
+{
+	return __raw_readw(i2c_hs->reg_base_virt + reg_offset);
+}
+
+static void reg_write(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 data)
+{
+	__raw_writew(data, i2c_hs->reg_base_virt + reg_offset);
+}
+
+static void reg_set_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask)
+{
+	u16 value;
+
+	value = reg_read(i2c_hs, reg_offset);
+	value |= mask;
+	reg_write(i2c_hs, reg_offset, value);
+}
+static void reg_clear_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask)
+{
+	u16 value;
+
+	value = reg_read(i2c_hs, reg_offset);
+	value &= ~mask;
+	reg_write(i2c_hs, reg_offset, value);
+}
+
+static void mxci2c_hs_set_div(mxc_i2c_hs *i2c_hs)
+{
+	unsigned long clk_freq;
+	int i;
+	int div = -1;;
+
+	clk_freq = clk_get_rate(i2c_hs->serial_clk);
+	if (i2c_hs->speed) {
+		div = (clk_freq + i2c_hs->speed - 1) / i2c_hs->speed;
+		for (i = 0; i2c_clk_table[i].div >= 0; i++) {
+			if (i2c_clk_table[i].div >= div) {
+				div = i2c_clk_table[i].reg_value;
+				reg_write(i2c_hs, HIFSFDR, div);
+				break;
+			}
+		}
+	}
+}
+
+static int mxci2c_hs_enable(mxc_i2c_hs *i2c_hs)
+{
+	gpio_i2c_hs_active();
+	clk_enable(i2c_hs->ipg_clk);
+	clk_enable(i2c_hs->serial_clk);
+	mxci2c_hs_set_div(i2c_hs);
+	reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) | HICR_HIEN);
+
+	return 0;
+}
+
+static int mxci2c_hs_disable(mxc_i2c_hs *i2c_hs)
+{
+	reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) & (~HICR_HIEN));
+	clk_disable(i2c_hs->ipg_clk);
+	clk_disable(i2c_hs->serial_clk);
+
+	return 0;
+}
+
+static int mxci2c_hs_bus_busy(mxc_i2c_hs *i2c_hs)
+{
+	u16 value;
+	int retry = 1000;
+
+	while (retry--) {
+		value = reg_read(i2c_hs, HISR);
+		if (value & HISR_HIBB) {
+			udelay(1);
+		} else {
+			break;
+		}
+	}
+
+	if (retry <= 0) {
+		dev_dbg(NULL, "%s: Bus Busy!\n", __func__);
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static int mxci2c_hs_start(mxc_i2c_hs *i2c_hs, int repeat_start, u16 address)
+{
+	u16 mask;
+	int ret = 0;
+
+	mxci2c_hs_bus_busy(i2c_hs);
+
+	/*7 bit address */
+	reg_clear_mask(i2c_hs, HICR, HICR_ADDR_MODE);
+
+	/*send start */
+	if (repeat_start)
+		mask = HICR_RSTA;
+	else
+		mask = HICR_MSTA;
+	reg_set_mask(i2c_hs, HICR, mask);
+
+	return ret;
+}
+
+static int mxci2c_hs_stop(mxc_i2c_hs *i2c_hs)
+{
+	reg_clear_mask(i2c_hs, HICR, HICR_MSTA);
+	reg_clear_mask(i2c_hs, HICR, HICR_HIIEN);
+
+	return 0;
+}
+
+static int mxci2c_wait_writefifo(mxc_i2c_hs *i2c_hs)
+{
+	int i, num, left;
+	int retry, ret = 0;
+
+	retry = 10000;
+	while (retry--) {
+		udelay(10);
+		if (reg_read(i2c_hs, HISR) & (HISR_TDE | HISR_TDC_ZERO)) {
+			if (i2c_hs->index < i2c_hs->msg->len) {
+				left = i2c_hs->msg->len - i2c_hs->index;
+				num =
+				    (left >
+				     HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left;
+				for (i = 0; i < num; i++) {
+					reg_write(i2c_hs, HITDR,
+						  i2c_hs->msg->buf[i2c_hs->
+								   index + i]);
+				}
+				i2c_hs->index += num;
+			} else {
+				if (reg_read(i2c_hs, HISR) & HISR_TDC_ZERO) {
+					msleep(1);
+					break;
+				}
+			}
+		}
+	}
+
+	if (retry <= 0) {
+		printk(KERN_ERR "%s:wait error\n", __func__);
+		ret = -1;
+	}
+
+	return ret;
+}
+
+static int mxci2c_wait_readfifo(mxc_i2c_hs *i2c_hs)
+{
+	int i, num, left;
+	int retry, ret = 0;
+	u16 value;
+
+	retry = 10000;
+	while (retry--) {
+		udelay(10);
+		value = reg_read(i2c_hs, HISR);
+		if (value & (HISR_RDF | HISR_RDC_ZERO)) {
+			if (i2c_hs->index < i2c_hs->msg->len) {
+				left = i2c_hs->msg->len - i2c_hs->index;
+				num =
+				    (left >
+				     HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left;
+				for (i = 0; i < num; i++) {
+					i2c_hs->msg->buf[i2c_hs->index + i] =
+					    reg_read(i2c_hs, HIRDR);
+				}
+				i2c_hs->index += num;
+			} else {
+				if (value & HISR_RDC_ZERO) {
+					break;
+				}
+			}
+		}
+	}
+
+	if (retry <= 0) {
+		printk(KERN_ERR "%s:wait error\n", __func__);
+		ret = -1;
+	}
+
+	return ret;
+}
+
+static int mxci2c_hs_read(mxc_i2c_hs *i2c_hs, int repeat_start,
+			  struct i2c_msg *msg)
+{
+	int ret;
+
+	if (msg->len > HIRDCR_MAX_COUNT) {
+		printk(KERN_ERR "%s: error: msg too long, max longth 256\n",
+		       __func__);
+		return -1;
+	}
+
+	ret = 0;
+	i2c_hs->msg = msg;
+	i2c_hs->index = 0;
+
+	/*set address */
+	reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr));
+
+	/*receive mode */
+	reg_clear_mask(i2c_hs, HICR, HICR_MTX);
+
+	reg_clear_mask(i2c_hs, HICR, HICR_HIIEN);
+
+	 /*FIFO*/ reg_set_mask(i2c_hs, HIRFR, HIRFR_RFEN | HIRFR_RFWM(7));
+	reg_set_mask(i2c_hs, HIRFR, HIRFR_RFLSH);
+
+	 /*TDCR*/
+	    reg_write(i2c_hs, HIRDCR, HIRDCR_RDC_EN | HIRDCR_RDC(msg->len));
+
+	mxci2c_hs_start(i2c_hs, repeat_start, msg->addr);
+
+	ret = mxci2c_wait_readfifo(i2c_hs);
+
+	if (ret < 0)
+		return ret;
+	else
+		return msg->len;
+}
+
+static int mxci2c_hs_write(mxc_i2c_hs *i2c_hs, int repeat_start,
+			   struct i2c_msg *msg)
+{
+	int ret, i;
+
+	if (msg->len > HITDCR_MAX_COUNT) {
+		printk(KERN_ERR "%s: error: msg too long, max longth 256\n",
+		       __func__);
+		return -1;
+	}
+
+	ret = 0;
+	i2c_hs->msg = msg;
+	i2c_hs->index = 0;
+
+	/*set address */
+	reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr));
+
+	/*transmit mode */
+	reg_set_mask(i2c_hs, HICR, HICR_MTX);
+
+	reg_clear_mask(i2c_hs, HICR, HICR_HIIEN);
+
+	/* TDCR */
+	reg_write(i2c_hs, HITDCR, HITDCR_TDC_EN | HITDCR_TDC(msg->len));
+
+	/* FIFO */
+	reg_set_mask(i2c_hs, HITFR, HITFR_TFEN);
+	reg_set_mask(i2c_hs, HITFR, HITFR_TFLSH);
+
+	if (msg->len > HITFR_MAX_COUNT)
+		i2c_hs->index = HITFR_MAX_COUNT;
+	else {
+		i2c_hs->index = msg->len;
+	}
+
+	for (i = 0; i < i2c_hs->index; i++) {
+		reg_write(i2c_hs, HITDR, msg->buf[i]);
+	}
+
+	mxci2c_hs_start(i2c_hs, repeat_start, msg->addr);
+
+	ret = mxci2c_wait_writefifo(i2c_hs);
+
+	if (ret < 0)
+		return ret;
+	else
+		return msg->len;
+}
+
+static int mxci2c_hs_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
+			  int num)
+{
+	int i;
+	int ret = -EIO;
+
+	mxc_i2c_hs *i2c_hs = (mxc_i2c_hs *) (i2c_get_adapdata(adap));
+
+	if (i2c_hs->low_power) {
+		dev_err(&adap->dev, "I2C Device in low power mode\n");
+		return -EREMOTEIO;
+	}
+
+	if (num < 1) {
+		return 0;
+	}
+
+	mxci2c_hs_enable(i2c_hs);
+
+	for (i = 0; i < num; i++) {
+		if (msgs[i].flags & I2C_M_RD) {
+			ret = mxci2c_hs_read(i2c_hs, 0, &msgs[i]);
+			if (ret < 0)
+				break;
+		} else {
+			ret = mxci2c_hs_write(i2c_hs, 0, &msgs[i]);
+			if (ret < 0)
+				break;
+		}
+		mxci2c_hs_stop(i2c_hs);
+	}
+	mxci2c_hs_stop(i2c_hs);
+
+	mxci2c_hs_disable(i2c_hs);
+
+	if (ret < 0)
+		return ret;
+
+	return i;
+}
+
+static u32 mxci2c_hs_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+/*!
+ * Stores the pointers for the i2c algorithm functions. The algorithm functions
+ * is used by the i2c bus driver to talk to the i2c bus
+ */
+static struct i2c_algorithm mxci2c_hs_algorithm = {
+	.master_xfer = mxci2c_hs_xfer,
+	.functionality = mxci2c_hs_func
+};
+
+static int mxci2c_hs_probe(struct platform_device *pdev)
+{
+	mxc_i2c_hs *i2c_hs;
+	struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data;
+	struct resource *res;
+	int id = pdev->id;
+	int ret = 0;
+
+	i2c_hs = kzalloc(sizeof(mxc_i2c_hs), GFP_KERNEL);
+	if (!i2c_hs) {
+		return -ENOMEM;
+	}
+
+	i2c_hs->dev = &pdev->dev;
+
+	i2c_hs->speed = i2c_plat_data->i2c_clk;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto err1;
+	}
+	i2c_hs->reg_base_virt = ioremap(res->start, res->end - res->start + 1);
+	i2c_hs->reg_base_phy = res->start;
+
+	i2c_hs->ipg_clk = clk_get(&pdev->dev, "hsi2c_clk");
+	i2c_hs->serial_clk = clk_get(&pdev->dev, "hsi2c_serial_clk");
+
+	/*
+	 * Request the I2C interrupt
+	 */
+	i2c_hs->irq = platform_get_irq(pdev, 0);
+	if (i2c_hs->irq < 0) {
+		ret = i2c_hs->irq;
+		goto err1;
+	}
+
+	i2c_hs->low_power = false;
+
+	/*
+	 * Set the adapter information
+	 */
+	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
+	if (!adap) {
+		ret = -ENODEV;
+		goto err1;
+	}
+	strlcpy(adap->name, pdev->name, 48);
+	adap->id = adap->nr = id;
+	adap->algo = &mxci2c_hs_algorithm;
+	adap->timeout = 1;
+	platform_set_drvdata(pdev, i2c_hs);
+	i2c_set_adapdata(adap, i2c_hs);
+	ret = i2c_add_numbered_adapter(adap);
+	if (ret < 0) {
+		goto err2;
+	}
+
+	printk(KERN_INFO "MXC HS I2C driver\n");
+	return 0;
+
+      err2:
+	kfree(adap);
+      err1:
+	dev_err(&pdev->dev, "failed to probe high speed i2c adapter\n");
+	iounmap(i2c_hs->reg_base_virt);
+	kfree(i2c_hs);
+	return ret;
+}
+
+static int mxci2c_hs_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev);
+
+	if (i2c_hs == NULL) {
+		return -1;
+	}
+
+	/* Prevent further calls to be processed */
+	i2c_hs->low_power = true;
+
+	gpio_i2c_hs_inactive();
+
+	return 0;
+}
+
+static int mxci2c_hs_resume(struct platform_device *pdev)
+{
+	mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev);
+
+	if (i2c_hs == NULL)
+		return -1;
+
+	i2c_hs->low_power = false;
+	gpio_i2c_hs_active();
+
+	return 0;
+}
+
+static int mxci2c_hs_remove(struct platform_device *pdev)
+{
+	mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(adap);
+	gpio_i2c_hs_inactive();
+	platform_set_drvdata(pdev, NULL);
+	iounmap(i2c_hs->reg_base_virt);
+	kfree(i2c_hs);
+	return 0;
+}
+
+static struct platform_driver mxci2c_hs_driver = {
+	.driver = {
+		   .name = "mxc_i2c_hs",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxci2c_hs_probe,
+	.remove = mxci2c_hs_remove,
+	.suspend = mxci2c_hs_suspend,
+	.resume = mxci2c_hs_resume,
+};
+
+/*!
+ * Function requests the interrupts and registers the i2c adapter structures.
+ *
+ * @return The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxci2c_hs_init(void)
+{
+	/* Register the device driver structure. */
+	return platform_driver_register(&mxci2c_hs_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxci2c_hs_exit(void)
+{
+	platform_driver_unregister(&mxci2c_hs_driver);
+}
+
+subsys_initcall(mxci2c_hs_init);
+module_exit(mxci2c_hs_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC HIGH SPEED I2C driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/mxc_i2c_hs_reg.h b/drivers/i2c/busses/mxc_i2c_hs_reg.h
new file mode 100644
index 000000000000..fe6bb9a8f1ff
--- /dev/null
+++ b/drivers/i2c/busses/mxc_i2c_hs_reg.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MXC_I2C_HS_REG_H__
+#define __MXC_I2C_HS_REG_H__
+
+#define	HISADR        0x00
+
+#define	HIMADR        0x04
+#define	HIMADR_LSB_ADR(x) ((x) << 1)
+#define	HIMADR_MSB_ADR(x) (((x) & 0x7) << 8)
+
+#define	HICR          0x08
+#define	HICR_HIEN	0x1
+#define	HICR_DMA_EN_RX 0x2
+#define	HICR_DMA_EN_TR 0x4
+#define	HICR_RSTA 0x8
+#define	HICR_TXAK 0x10
+#define	HICR_MTX 0x20
+#define	HICR_MSTA 0x40
+#define	HICR_HIIEN 0x80
+#define	HICR_ADDR_MODE 0x100
+#define	HICR_MST_CODE(x) (((x)&0x7) << 9)
+#define	HICR_HSM_EN 0x1000
+#define	HICR_SAMC(x) (((x)&0x3) << 13)
+#define 	SAMC_7_10 	0
+#define	SMAC_7		1
+#define	SMAC_10		2
+
+#define  HISR          0x0c
+#define 	HISR_RDF		0x1
+#define 	HISR_TDE		0x2
+#define 	HISR_HIAAS	0x4
+#define 	HISR_HIAL	0x8
+#define 	HISR_BTD		0x10
+#define 	HISR_RDC_ZERO	0x20
+#define 	HISR_TDC_ZERO	0x40
+#define 	HISR_RXAK		0x80
+#define 	HISR_HIBB		0x100
+#define 	HISR_SRW		0x200
+#define 	HISR_SADDR_MODE	0x400
+#define 	HISR_SHS_MODE	0x800
+
+#define  HIIMR         0x10
+#define  	HIIMR_RDF	0x1
+#define  	HIIMR_TDE	0x2
+#define  	HIIMR_AAS	0x4
+#define  	HIIMR_AL	0x8
+#define  	HIIMR_BTD	0x10
+#define  	HIIMR_RDC	0x20
+#define  	HIIMR_TDC	0x40
+#define  	HIIMR_RXAK	0x80
+
+#define  HITDR         0x14
+
+#define  HIRDR         0x18
+
+#define  HIFSFDR       0x1c
+
+#define  HIHSFDR       0x20
+
+#define  HITFR         0x24
+#define	HITFR_TFEN		0x1
+#define	HITFR_TFLSH	0x2
+#define	HITFR_TFWM(x) (((x) & 0x7) << 2)
+#define	HITFR_TFC(x)	(((x) >> 8) & 0xF)
+#define	HITFR_MAX_COUNT 8
+
+#define  HIRFR         0x28
+#define  	HIRFR_RFEN			0x1
+#define  	HIRFR_RFLSH		0x2
+#define  	HIRFR_RFWM(x)	 	(((x) & 0x7) << 2)
+#define  	HIRFR_RFC(x) 		(((x) >> 8) & 0xF)
+#define	HIRFR_MAX_COUNT 8
+
+#define  HITDCR        0x2c
+#define	HITDCR_TDC(x)		((x) & 0xFF)
+#define	HITDCR_TDC_EN	0x100
+#define	HITDCR_TDC_RSTA	0x200
+#define	HITDCR_MAX_COUNT 0xFF
+
+#define  HIRDCR        0x30
+#define	HIRDCR_RDC(x)		((x) & 0xFF)
+#define	HIRDCR_RDC_EN	0x100
+#define	HIRDCR_RDC_RSTA	0x200
+#define	HIRDCR_MAX_COUNT 0xFF
+
+#endif
diff --git a/drivers/i2c/busses/mxc_i2c_reg.h b/drivers/i2c/busses/mxc_i2c_reg.h
new file mode 100644
index 000000000000..4fc76c8aa811
--- /dev/null
+++ b/drivers/i2c/busses/mxc_i2c_reg.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MXC_I2C_REG_H__
+#define __MXC_I2C_REG_H__
+
+/* Address offsets of the I2C registers */
+#define MXC_IADR                0x00	/* Address Register */
+#define MXC_IFDR                0x04	/* Freq div register */
+#define MXC_I2CR                0x08	/* Control regsiter */
+#define MXC_I2SR                0x0C	/* Status register */
+#define MXC_I2DR                0x10	/* Data I/O register */
+
+/* Bit definitions of I2CR */
+#define MXC_I2CR_IEN            0x0080
+#define MXC_I2CR_IIEN           0x0040
+#define MXC_I2CR_MSTA           0x0020
+#define MXC_I2CR_MTX            0x0010
+#define MXC_I2CR_TXAK           0x0008
+#define MXC_I2CR_RSTA           0x0004
+
+/* Bit definitions of I2SR */
+#define MXC_I2SR_ICF            0x0080
+#define MXC_I2SR_IAAS           0x0040
+#define MXC_I2SR_IBB            0x0020
+#define MXC_I2SR_IAL            0x0010
+#define MXC_I2SR_SRW            0x0004
+#define MXC_I2SR_IIF            0x0002
+#define MXC_I2SR_RXAK           0x0001
+
+#endif				/* __MXC_I2C_REG_H__ */
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a6b989a9dc07..89803885cadf 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -310,6 +310,13 @@ config KEYBOARD_SUNKBD
 	  To compile this driver as a module, choose M here: the
 	  module will be called sunkbd.
 
+config KEYBOARD_MPR084
+	tristate "Freescale MPR084 Touch Keypad Driver"
+	depends on ARCH_MX37
+	help
+	  This is the Keypad driver for the Freescale Proximity Capacitive
+	  Touch Sensor controller chip.
+
 config KEYBOARD_SH_KEYSC
 	tristate "SuperH KEYSC keypad support"
 	depends on SUPERH
@@ -317,6 +324,7 @@ config KEYBOARD_SH_KEYSC
 	  Say Y here if you want to use a keypad attached to the KEYSC block
 	  on SuperH processors such as sh7722 and sh7343.
 
+
 	  To compile this driver as a module, choose M here: the
 	  module will be called sh_keysc.
 
@@ -361,4 +369,30 @@ config KEYBOARD_XTKBD
 	  To compile this driver as a module, choose M here: the
 	  module will be called xtkbd.
 
+config KEYBOARD_MXC
+	tristate "MXC Keypad Driver"
+	depends on ARCH_MXC
+	help
+	  This is the Keypad driver for the Freescale MXC application
+	  processors.
+
+config KEYBOARD_STMP3XXX
+	tristate "STMP3xxx keyboard"
+	depends on ARCH_STMP3XXX
+	help
+	 -to be written-
+
+config KEYBOARD_MXS
+	tristate "MXS keyboard"
+	depends on ARCH_MXS
+	help
+	  This is the Keypad driver for the Freescale mxs soc
+
+
+config KEYBOARD_MC9S08DZ60
+	tristate "mc9s08dz60 keyboard"
+	depends on MXC_PMIC_MC9S08DZ60
+	help
+	 -to be written-
+
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index b5b5eae9724f..fea01a591076 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -31,3 +31,8 @@ obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
 obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
 obj-$(CONFIG_KEYBOARD_TOSA)		+= tosakbd.o
 obj-$(CONFIG_KEYBOARD_XTKBD)		+= xtkbd.o
+obj-$(CONFIG_KEYBOARD_MXC)		+= mxc_keyb.o
+obj-$(CONFIG_KEYBOARD_MPR084)		+= mpr084.o
+obj-$(CONFIG_KEYBOARD_STMP3XXX)		+= stmp3xxx-kbd.o
+obj-$(CONFIG_KEYBOARD_MXS)		+= mxs-kbd.o
+obj-$(CONFIG_KEYBOARD_MC9S08DZ60)	+= mc9s08dz60_keyb.o
diff --git a/drivers/input/keyboard/mc9s08dz60_keyb.c b/drivers/input/keyboard/mc9s08dz60_keyb.c
new file mode 100644
index 000000000000..8ec9f646c7c7
--- /dev/null
+++ b/drivers/input/keyboard/mc9s08dz60_keyb.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc9s08dz60keyb.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC keypad port.
+ *
+ * The keypad driver is designed as a standard Input driver which interacts
+ * with low level keypad port hardware. Upon opening, the Keypad driver
+ * initializes the keypad port. When the keypad interrupt happens the driver
+ * calles keypad polling timer and scans the keypad matrix for key
+ * press/release. If all key press/release happened it comes out of timer and
+ * waits for key press interrupt. The scancode for key press and release events
+ * are passed to Input subsytem.
+ *
+ * @ingroup keypad
+ */
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <linux/kd.h>
+#include <linux/fs.h>
+#include <linux/kbd_kern.h>
+#include <linux/ioctl.h>
+#include <linux/poll.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/input.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/mfd/mc9s08dz60/pmic.h>
+#include <asm/mach/keypad.h>
+
+#define MOD_NAME "mc9s08dz60-keyb"
+/*
+ * Module header file
+ */
+
+/*! Input device structure. */
+static struct input_dev *mc9s08dz60kbd_dev;
+static unsigned int key_status;
+static int keypad_irq;
+static unsigned int key_code_map[8] = {
+	KEY_LEFT,
+	KEY_DOWN,
+	0,
+	0,
+	KEY_UP,
+	KEY_RIGHT,
+	0,
+	0,
+};
+static unsigned int keycodes_size = 8;
+
+static void read_key_handler(struct work_struct *work);
+static DECLARE_WORK(key_pad_event, read_key_handler);
+
+
+static void read_key_handler(struct work_struct *work)
+{
+	unsigned int val1, val2;
+	int pre_val, curr_val, i;
+	val1 = val2 = 0xff;
+	mcu_pmic_read_reg(REG_MCU_KPD_1, &val1, 0xff);
+	mcu_pmic_read_reg(REG_MCU_KPD_2, &val2, 0xff);
+	pr_debug("key pressed, 0x%02x%02x\n", val2, val1);
+	for (i = 0; i < 8; i++) {
+		curr_val = (val1 >> i) & 0x1;
+		if (curr_val > 0)
+			input_event(mc9s08dz60kbd_dev, EV_KEY,
+			key_code_map[i], 1);
+		else {
+			pre_val = (key_status >> i) & 0x1;
+			if (pre_val > 0)
+				input_event(mc9s08dz60kbd_dev, EV_KEY,
+				key_code_map[i], 0);
+		}
+	}
+	key_status = val1;
+
+}
+
+static irqreturn_t mc9s08dz60kpp_interrupt(int irq, void *dev_id)
+{
+	schedule_work(&key_pad_event);
+	return IRQ_RETVAL(1);
+}
+
+/*!
+ * This function is called when the keypad driver is opened.
+ * Since keypad initialization is done in __init, nothing is done in open.
+ *
+ * @param    dev    Pointer to device inode
+ *
+ * @result    The function always return 0
+ */
+static int mc9s08dz60kpp_open(struct input_dev *dev)
+{
+	return 0;
+}
+
+/*!
+ * This function is called close the keypad device.
+ * Nothing is done in this function, since every thing is taken care in
+ * __exit function.
+ *
+ * @param    dev    Pointer to device inode
+ *
+ */
+static void mc9s08dz60kpp_close(struct input_dev *dev)
+{
+}
+
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions.
+ *
+ * @return  The function returns 0 on successful registration. Otherwise returns
+ *          specific error code.
+ */
+static int mc9s08dz60kpp_probe(struct platform_device *pdev)
+{
+	int i, irq;
+	int retval;
+
+	retval = mcu_pmic_write_reg(REG_MCU_KPD_CONTROL, 0x1, 0x1);
+	if (retval != 0) {
+		pr_info("mc9s08dz60 keypad: mcu not detected!\n");
+		return retval;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	retval = request_irq(irq, mc9s08dz60kpp_interrupt,
+			0, MOD_NAME, MOD_NAME);
+	if (retval) {
+		pr_debug("KPP: request_irq(%d) returned error %d\n",
+			 irq, retval);
+		return retval;
+	}
+	keypad_irq = irq;
+
+	mc9s08dz60kbd_dev = input_allocate_device();
+	if (!mc9s08dz60kbd_dev) {
+		pr_info(KERN_ERR "mc9s08dz60kbd_dev: \
+		not enough memory for input device\n");
+		retval = -ENOMEM;
+		goto err1;
+	}
+
+	mc9s08dz60kbd_dev->name = "mc9s08dz60kpd";
+	mc9s08dz60kbd_dev->id.bustype = BUS_HOST;
+	mc9s08dz60kbd_dev->open = mc9s08dz60kpp_open;
+	mc9s08dz60kbd_dev->close = mc9s08dz60kpp_close;
+
+	retval = input_register_device(mc9s08dz60kbd_dev);
+	if (retval < 0) {
+		pr_info(KERN_ERR
+		       "mc9s08dz60kbd_dev: failed to register input device\n");
+		goto err2;
+	}
+
+	__set_bit(EV_KEY, mc9s08dz60kbd_dev->evbit);
+
+	for (i = 0; i < keycodes_size; i++)
+		__set_bit(key_code_map[i], mc9s08dz60kbd_dev->keybit);
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	pr_info("mc9s08dz60 keypad probed\n");
+
+	return 0;
+
+err2:
+	input_free_device(mc9s08dz60kbd_dev);
+err1:
+	free_irq(irq, MOD_NAME);
+	return retval;
+}
+
+/*!
+ * Dissociates the driver from the kpp device.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mc9s08dz60kpp_remove(struct platform_device *pdev)
+{
+	free_irq(keypad_irq, MOD_NAME);
+	input_unregister_device(mc9s08dz60kbd_dev);
+
+	if (mc9s08dz60kbd_dev)
+		input_free_device(mc9s08dz60kbd_dev);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mc9s08dz60kpd_driver = {
+	.driver = {
+		   .name = "mc9s08dz60keypad",
+		   .bus = &platform_bus_type,
+		   },
+	.probe = mc9s08dz60kpp_probe,
+	.remove = mc9s08dz60kpp_remove
+};
+
+static int __init mc9s08dz60kpp_init(void)
+{
+	pr_info(KERN_INFO "mc9s08dz60 keypad loaded\n");
+	platform_driver_register(&mc9s08dz60kpd_driver);
+	return 0;
+}
+
+static void __exit mc9s08dz60kpp_cleanup(void)
+{
+	platform_driver_unregister(&mc9s08dz60kpd_driver);
+}
+
+module_init(mc9s08dz60kpp_init);
+module_exit(mc9s08dz60kpp_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC Keypad Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/keyboard/mpr084.c b/drivers/input/keyboard/mpr084.c
new file mode 100644
index 000000000000..4b0c4883751e
--- /dev/null
+++ b/drivers/input/keyboard/mpr084.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file  linux/drivers/input/keyboard/mpr084.c
+ *
+ * @brief Driver for the Freescale MPR084 I2C Touch Sensor KeyPad module.
+ *
+ *
+ *
+ * @ingroup Keypad
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/string.h>
+#include <linux/bcd.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/kthread.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/mach/irq.h>
+#include <mach/gpio.h>
+
+/*
+ * Definitions
+ */
+#define DEBUG 0
+
+#define KEY_COUNT         8
+
+/*
+  *Registers in MPR084
+  */
+#define MPR084_FIFO_ADDR                        0x00
+#define MPR084_FAULT_ADDR                       0x01
+#define MPR084_TPS_ADDR                         0x02
+#define MPR084_TPC_ADDR                         0x03
+#define MPR084_STR1_ADDR                        0x04
+#define MPR084_STR2_ADDR                        0x05
+#define MPR084_STR3_ADDR                        0x06
+#define MPR084_STR4_ADDR                        0x07
+#define MPR084_STR5_ADDR                        0x08
+#define MPR084_STR6_ADDR                        0x09
+#define MPR084_STR7_ADDR                        0x0A
+#define MPR084_STR8_ADDR                        0x0B
+#define MPR084_ECEM_ADDR                        0x0C
+#define MPR084_MNTP_ADDR                        0x0D
+#define MPR084_MTC_ADDR                         0x0E
+#define MPR084_TASP_ADDR                        0x0F
+#define MPR084_SC_ADDR                          0x10
+#define MPR084_LPC_ADDR                         0x11
+#define MPR084_SKT_ADDR                         0x12
+#define MPR084_CONFIG_ADDR                      0x13
+#define MPR084_SI_ADDR                          0x14
+#define MPR084_ADDR_MINI                        MPR084_FIFO_ADDR
+#define MPR084_ADDR_MAX                         MPR084_SI_ADDR
+
+/* FIFO registers */
+#define MPR084_FIFO_MORE_DATA_FLAG              0x80
+#define MPR084_FIFO_NO_DATA_FLAG                0x40
+#define MPR084_FIFO_OVERFLOW_FLAG               0x20
+#define MPR084_FIFO_PAD_IS_TOUCHED              0x10
+#define MPR084_FIFO_POSITION_MASK               0x0F
+
+#define DRIVER_NAME "mpr084"
+
+struct mpr084_data {
+	struct i2c_client *client;
+	struct device_driver driver;
+	struct input_dev *idev;
+	struct task_struct *tstask;
+	struct completion kpirq_completion;
+	int kpirq;
+	int kp_thread_cnt;
+	int opened;
+};
+
+static int kpstatus[KEY_COUNT];
+static struct mxc_keyp_platform_data *keypad;
+static const unsigned short *mxckpd_keycodes;
+static struct regulator *vdd_reg;
+
+static int mpr084_read_register(struct mpr084_data *data,
+				unsigned char regaddr, int *value)
+{
+	int ret = 0;
+	unsigned char regvalue;
+
+	ret = i2c_master_send(data->client, &regaddr, 1);
+	if (ret < 0)
+		goto err;
+	udelay(20);
+	ret = i2c_master_recv(data->client, &regvalue, 1);
+	if (ret < 0)
+		goto err;
+	*value = regvalue;
+
+	return ret;
+err:
+	return -ENODEV;
+}
+
+static int mpr084_write_register(struct mpr084_data *data,
+				 u8 regaddr, u8 regvalue)
+{
+	int ret = 0;
+	unsigned char msgbuf[2];
+
+	msgbuf[0] = regaddr;
+	msgbuf[1] = regvalue;
+	ret = i2c_master_send(data->client, msgbuf, 2);
+	if (ret < 0) {
+		printk(KERN_ERR "%s - Error in writing to I2C Register %d \n",
+		       __func__, regaddr);
+		return ret;
+	}
+
+	return ret;
+}
+
+
+static irqreturn_t mpr084_keypadirq(int irq, void *v)
+{
+	struct mpr084_data *d = v;
+
+	disable_irq(d->kpirq);
+	complete(&d->kpirq_completion);
+	return IRQ_HANDLED;
+}
+
+static int mpr084ts_thread(void *v)
+{
+	struct mpr084_data *d = v;
+	int ret = 0, fifo = 0;
+	int index = 0, currentstatus = 0;
+
+	if (d->kp_thread_cnt)
+		return -EINVAL;
+	d->kp_thread_cnt = 1;
+	while (1) {
+
+		if (kthread_should_stop())
+			break;
+		/* Wait for keypad interrupt */
+		if (wait_for_completion_interruptible_timeout
+		    (&d->kpirq_completion, HZ) <= 0)
+			continue;
+
+		ret = mpr084_read_register(d, MPR084_FIFO_ADDR, &fifo);
+		if (ret < 0) {
+			printk(KERN_ERR
+			       "%s: Err in reading keypad FIFO register \n\n",
+			       __func__);
+		} else {
+			if (fifo & MPR084_FIFO_OVERFLOW_FLAG)
+				printk(KERN_ERR
+				       "%s: FIFO overflow \n\n", __func__);
+			while (!(fifo & MPR084_FIFO_NO_DATA_FLAG)) {
+				index = fifo & MPR084_FIFO_POSITION_MASK;
+				currentstatus =
+				    fifo & MPR084_FIFO_PAD_IS_TOUCHED;
+				/*Scan key map for changes */
+				if ((currentstatus) ^ (kpstatus[index])) {
+					if (!(currentstatus)) {
+						/*Key released. */
+						input_event(d->idev, EV_KEY,
+							    mxckpd_keycodes
+							    [index], 0);
+					} else {
+						/* Key pressed. */
+						input_event(d->idev, EV_KEY,
+							    mxckpd_keycodes
+							    [index], 1);
+					}
+					/*Store current keypad status */
+					kpstatus[index] = currentstatus;
+				}
+				mpr084_read_register(d, MPR084_FIFO_ADDR,
+						     &fifo);
+				if (fifo & MPR084_FIFO_OVERFLOW_FLAG)
+					printk(KERN_ERR
+					       "%s: FIFO overflow \n\n",
+					       __func__);
+			}
+		}
+		/* Re-enable interrupts */
+		enable_irq(d->kpirq);
+	}
+
+	d->kp_thread_cnt = 0;
+	return 0;
+}
+
+/*!
+ * This function puts the Keypad controller in low-power mode/state.
+ *
+ * @param   pdev  the device structure used to give information on Keypad
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mpr084_suspend(struct i2c_client *client, pm_message_t state)
+{
+	struct mpr084_data *d = i2c_get_clientdata(client);
+
+	if (!IS_ERR(d->tstask) && d->opened)
+		kthread_stop(d->tstask);
+
+	return 0;
+}
+
+/*!
+ * This function brings the Keypad controller back from low-power state.
+ *
+ * @param   pdev  the device structure used to give information on Keypad
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mpr084_resume(struct i2c_client *client)
+{
+	struct mpr084_data *d = i2c_get_clientdata(client);
+
+	if (d->opened)
+		d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd");
+
+	return 0;
+}
+
+static int mpr084_idev_open(struct input_dev *idev)
+{
+	struct mpr084_data *d = input_get_drvdata(idev);
+	int ret = 0;
+
+	d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd");
+	if (IS_ERR(d->tstask))
+		ret = PTR_ERR(d->tstask);
+	else
+		d->opened++;
+	return ret;
+}
+
+static void mpr084_idev_close(struct input_dev *idev)
+{
+	struct mpr084_data *d = input_get_drvdata(idev);
+
+	if (!IS_ERR(d->tstask))
+		kthread_stop(d->tstask);
+	if (d->opened > 0)
+		d->opened--;
+}
+
+static int mpr084_driver_register(struct mpr084_data *data)
+{
+	struct input_dev *idev;
+	int ret = 0;
+
+	if (data->kpirq) {
+		ret =
+		    request_irq(data->kpirq, mpr084_keypadirq,
+				IRQF_TRIGGER_FALLING, DRIVER_NAME, data);
+		if (!ret) {
+			init_completion(&data->kpirq_completion);
+			set_irq_wake(data->kpirq, 1);
+		} else {
+			printk(KERN_ERR "%s: cannot grab irq %d\n",
+			       __func__, data->kpirq);
+		}
+
+	}
+	idev = input_allocate_device();
+	data->idev = idev;
+	input_set_drvdata(idev, data);
+	idev->name = DRIVER_NAME;
+	idev->open = mpr084_idev_open;
+	idev->close = mpr084_idev_close;
+	if (!ret)
+		ret = input_register_device(idev);
+
+	return ret;
+}
+
+static int mpr084_i2c_remove(struct i2c_client *client)
+{
+	struct mpr084_data *d = i2c_get_clientdata(client);
+
+	free_irq(d->kpirq, d);
+	input_unregister_device(d->idev);
+	if (keypad->inactive)
+		keypad->inactive();
+
+	/*Disable the Regulator*/
+	if (keypad->vdd_reg) {
+		regulator_disable(vdd_reg);
+		regulator_put(vdd_reg);
+	}
+
+	return 0;
+}
+
+static int mpr084_configure(struct mpr084_data *data)
+{
+	int ret = 0, regValue = 0;
+
+	ret = mpr084_write_register(data, MPR084_TPC_ADDR, 0x1d);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR1_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR2_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR3_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR4_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR5_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR6_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR7_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	ret = mpr084_write_register(data, MPR084_STR8_ADDR, 0x10);
+	if (ret < 0)
+		goto err;
+	/* channel enable mask: enable all */
+	ret = mpr084_write_register(data, MPR084_ECEM_ADDR, 0xff);
+	if (ret < 0)
+		goto err;
+	/*two conccurrent touch position allowed */
+	ret = mpr084_write_register(data, MPR084_MNTP_ADDR, 0x02);
+	if (ret < 0)
+		goto err;
+
+	/* master tick period*/
+	ret = mpr084_write_register(data, MPR084_MTC_ADDR, 0x05);
+	if (ret < 0)
+		goto err;
+
+
+	/*Sample period */
+	ret = mpr084_write_register(data, MPR084_TASP_ADDR, 0x02);
+	if (ret < 0)
+		goto err;
+
+
+	/* disable sournder*/
+	ret = mpr084_write_register(data, MPR084_SC_ADDR, 0x00);
+	if (ret < 0)
+		goto err;
+
+	/* stuck key timeout */
+	ret = mpr084_write_register(data, MPR084_SKT_ADDR, 0x01);
+	if (ret < 0)
+		goto err;
+
+	/*enabled IRQEN, RUNE, IRQR */
+	ret = mpr084_read_register(data, MPR084_CONFIG_ADDR, &regValue);
+	if (ret < 0) {
+		printk(KERN_ERR
+		  "%s: Err in reading keypad CONFIGADDR register \n\n",
+		   __func__);
+		goto err;
+	}
+	regValue |= 0x03;
+	ret = mpr084_write_register(data, MPR084_CONFIG_ADDR, regValue);
+	if (ret < 0)
+		goto err;
+	return ret;
+err:
+	return -ENODEV;
+}
+
+static int mpr084_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct mpr084_data *data;
+	int err = 0, i = 0;
+#if DEBUG
+	int regValue = 0;
+#endif
+	data = kzalloc(sizeof(struct mpr084_data), GFP_KERNEL);
+	if (data == NULL)
+		return -ENOMEM;
+	i2c_set_clientdata(client, data);
+	data->client = client;
+	data->kpirq = client->irq;
+	err = mpr084_driver_register(data);
+	if (err < 0)
+		goto exit_free;
+	keypad = (struct mxc_keyp_platform_data *)(client->dev).platform_data;
+	if (keypad->active)
+		keypad->active();
+
+	/*Enable the Regulator*/
+	if (keypad && keypad->vdd_reg) {
+		vdd_reg = regulator_get(&client->dev, keypad->vdd_reg);
+		if (!IS_ERR(vdd_reg))
+			regulator_enable(vdd_reg);
+		else
+			vdd_reg = NULL;
+	} else
+		vdd_reg = NULL;
+
+	mxckpd_keycodes = keypad->matrix;
+	data->idev->keycode = &mxckpd_keycodes;
+	data->idev->keycodesize = sizeof(unsigned char);
+	data->idev->keycodemax = KEY_COUNT;
+	data->idev->id.bustype = BUS_I2C;
+	__set_bit(EV_KEY, data->idev->evbit);
+	for (i = 0; i < 8; i++)
+		__set_bit(mxckpd_keycodes[i], data->idev->keybit);
+	err = mpr084_configure(data);
+	if (err == -ENODEV) {
+		free_irq(data->kpirq, data);
+		input_unregister_device(data->idev);
+		goto exit_free;
+	}
+
+#if DEBUG
+	for (i = MPR084_ADDR_MINI; i <= MPR084_ADDR_MAX; i++) {
+		err = mpr084_read_register(data, i, &regValue);
+		if (err < 0) {
+		   printk(KERN_ERR
+		  "%s: Err in reading keypad CONFIGADDR register \n\n",
+		   __func__);
+		   goto exit_free;
+	    }
+	    printk("MPR084 Register id: %d, Value:%d \n", i, regValue);
+
+	}
+#endif
+	memset(kpstatus, 0, sizeof(kpstatus));
+	printk(KERN_INFO "%s: Device Attached\n", __func__);
+	return 0;
+exit_free:
+	/*disable the Regulator*/
+	if (vdd_reg) {
+		regulator_disable(vdd_reg);
+		regulator_put(vdd_reg);
+		vdd_reg = NULL;
+	}
+	kfree(data);
+	return err;
+}
+
+static const struct i2c_device_id mpr084_id[] = {
+	{ "mpr084", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, mpr084_id);
+
+static struct i2c_driver mpr084_driver = {
+	.driver = {
+		   .name = DRIVER_NAME,
+		   },
+	.probe = mpr084_i2c_probe,
+	.remove = mpr084_i2c_remove,
+	.suspend = mpr084_suspend,
+	.resume = mpr084_resume,
+	.command = NULL,
+	.id_table = mpr084_id,
+};
+static int __init mpr084_init(void)
+{
+	return i2c_add_driver(&mpr084_driver);
+}
+
+static void __exit mpr084_exit(void)
+{
+	i2c_del_driver(&mpr084_driver);
+}
+
+MODULE_AUTHOR("Freescale Semiconductor Inc");
+MODULE_DESCRIPTION("MPR084 Touch KeyPad Controller driver");
+MODULE_LICENSE("GPL");
+module_init(mpr084_init);
+module_exit(mpr084_exit);
diff --git a/drivers/input/keyboard/mxc_keyb.c b/drivers/input/keyboard/mxc_keyb.c
new file mode 100644
index 000000000000..033713cbdfdf
--- /dev/null
+++ b/drivers/input/keyboard/mxc_keyb.c
@@ -0,0 +1,1202 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_keyb.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC keypad port.
+ *
+ * The keypad driver is designed as a standard Input driver which interacts
+ * with low level keypad port hardware. Upon opening, the Keypad driver
+ * initializes the keypad port. When the keypad interrupt happens the driver
+ * calles keypad polling timer and scans the keypad matrix for key
+ * press/release. If all key press/release happened it comes out of timer and
+ * waits for key press interrupt. The scancode for key press and release events
+ * are passed to Input subsytem.
+ *
+ * @ingroup keypad
+ */
+
+/*!
+ * Comment KPP_DEBUG to disable debug messages
+ */
+#define KPP_DEBUG        0
+
+#if KPP_DEBUG
+#define	DEBUG
+#include <linux/kernel.h>
+#endif
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <mach/hardware.h>
+#include <linux/kd.h>
+#include <linux/fs.h>
+#include <linux/kbd_kern.h>
+#include <linux/ioctl.h>
+#include <linux/poll.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/input.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <asm/mach/keypad.h>
+
+/*!
+ * Keypad Module Name
+ */
+#define MOD_NAME  "mxckpd"
+
+/*!
+ * XLATE mode selection
+ */
+#define KEYPAD_XLATE        0
+
+/*!
+ * RAW mode selection
+ */
+#define KEYPAD_RAW          1
+
+/*!
+ * Maximum number of keys.
+ */
+#define MAXROW			8
+#define MAXCOL			8
+#define MXC_MAXKEY		(MAXROW * MAXCOL)
+
+/*!
+ * This define indicates break scancode for every key release. A constant
+ * of 128 is added to the key press scancode.
+ */
+#define  MXC_KEYRELEASE   128
+
+/*
+ * _reg_KPP_KPCR   _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR
+ *  The offset of Keypad Control Register Address
+ */
+#define KPCR    0x00
+
+/*
+ * The offset of Keypad Status Register Address
+ */
+#define KPSR    0x02
+
+/*
+ * The offset of Keypad Data Direction Address
+ */
+#define KDDR   0x04
+
+/*
+ * The offset of Keypad Data Register
+ */
+#define KPDR    0x06
+
+/*
+ * Key Press Interrupt Status bit
+ */
+#define KBD_STAT_KPKD        0x01
+
+/*
+ * Key Release Interrupt Status bit
+ */
+#define KBD_STAT_KPKR        0x02
+
+/*
+ * Key Depress Synchronizer Chain Status bit
+ */
+#define KBD_STAT_KDSC        0x04
+
+/*
+ * Key Release Synchronizer Status bit
+ */
+#define KBD_STAT_KRSS        0x08
+
+/*
+ * Key Depress Interrupt Enable Status bit
+ */
+#define KBD_STAT_KDIE        0x100
+
+/*
+ * Key Release Interrupt Enable
+ */
+#define KBD_STAT_KRIE        0x200
+
+/*
+ * Keypad Clock Enable
+ */
+#define KBD_STAT_KPPEN       0x400
+
+/*!
+ * Buffer size of keypad queue. Should be a power of 2.
+ */
+#define KPP_BUF_SIZE    128
+
+/*!
+ * Test whether bit is set for integer c
+ */
+#define TEST_BIT(c, n) ((c) & (0x1 << (n)))
+
+/*!
+ * Set nth bit in the integer c
+ */
+#define BITSET(c, n)   ((c) | (1 << (n)))
+
+/*!
+ * Reset nth bit in the integer c
+ */
+#define BITRESET(c, n) ((c) & ~(1 << (n)))
+
+/*!
+ * This enum represents the keypad state machine to maintain debounce logic
+ * for key press/release.
+ */
+enum KeyState {
+
+	/*!
+	 * Key press state.
+	 */
+	KStateUp,
+
+	/*!
+	 * Key press debounce state.
+	 */
+	KStateFirstDown,
+
+	/*!
+	 * Key release state.
+	 */
+	KStateDown,
+
+	/*!
+	 * Key release debounce state.
+	 */
+	KStateFirstUp
+};
+
+/*!
+ * Keypad Private Data Structure
+ */
+struct keypad_priv {
+
+	/*!
+	 * Keypad state machine.
+	 */
+	enum KeyState iKeyState;
+
+	/*!
+	 * Number of rows configured in the keypad matrix
+	 */
+	unsigned long kpp_rows;
+
+	/*!
+	 * Number of Columns configured in the keypad matrix
+	 */
+	unsigned long kpp_cols;
+
+	/*!
+	 * Timer used for Keypad polling.
+	 */
+	struct timer_list poll_timer;
+
+	/*!
+	 * The base address
+	 */
+	void __iomem *base;
+};
+/*!
+ * This structure holds the keypad private data structure.
+ */
+static struct keypad_priv kpp_dev;
+
+/*! Indicates if the key pad device is enabled. */
+static unsigned int key_pad_enabled;
+
+/*! Input device structure. */
+static struct input_dev *mxckbd_dev = NULL;
+
+/*! KPP clock handle. */
+static struct clk *kpp_clk;
+
+/*! This static variable indicates whether a key event is pressed/released. */
+static unsigned short KPress;
+
+/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */
+static unsigned short *cur_rcmap;	/* max 64 bits (8x8 matrix) */
+static unsigned short *prev_rcmap;
+
+/*!
+ * Debounce polling period(10ms) in system ticks.
+ */
+static unsigned short KScanRate = (10 * HZ) / 1000;
+
+static struct keypad_data *keypad;
+
+static int has_leaning_key;
+/*!
+ * These arrays are used to store press and release scancodes.
+ */
+static short **press_scancode;
+static short **release_scancode;
+
+static const unsigned short *mxckpd_keycodes;
+static unsigned short mxckpd_keycodes_size;
+
+#define press_left_code     30
+#define press_right_code    29
+#define press_up_code       28
+#define press_down_code     27
+
+#define rel_left_code       158
+#define rel_right_code      157
+#define rel_up_code         156
+#define rel_down_code       155
+/*!
+ * These functions are used to configure and the GPIO pins for keypad to
+ * activate and deactivate it.
+ */
+extern void gpio_keypad_active(void);
+extern void gpio_keypad_inactive(void);
+
+/*!
+ * This function is called for generating scancodes for key press and
+ * release on keypad for the board.
+ *
+ *  @param   row        Keypad row pressed on the keypad matrix.
+ *  @param   col        Keypad col pressed on the keypad matrix.
+ *  @param   press      Indicated key press/release.
+ *
+ *  @return     Key press/release Scancode.
+ */
+static signed short mxc_scan_matrix_leaning_key(int row, int col, int press)
+{
+	static unsigned first_row;
+	static unsigned first_set = 0, flag = 0;
+	signed short scancode = -1;
+
+	if (press) {
+		if ((3 == col) && ((3 == row) ||
+				   (4 == row) || (5 == row) || (6 == row))) {
+			if (first_set == 0) {
+				first_set = 1;
+				first_row = row;
+			} else {
+				first_set = 0;
+				if (((first_row == 6) || (first_row == 3))
+				    && ((row == 6) || (row == 3)))
+					scancode = press_down_code;
+				else if (((first_row == 3) || (first_row == 5))
+					 && ((row == 3) || (row == 5)))
+					scancode = press_left_code;
+				else if (((first_row == 6) || (first_row == 4))
+					 && ((row == 6) || (row == 4)))
+					scancode = press_right_code;
+				else if (((first_row == 4) || (first_row == 5))
+					 && ((row == 4) || (row == 5)))
+					scancode = press_up_code;
+				KPress = 1;
+				kpp_dev.iKeyState = KStateUp;
+				pr_debug("Press (%d, %d) scan=%d Kpress=%d\n",
+					 row, col, scancode, KPress);
+			}
+		} else {
+			/*
+			 * check for other keys only
+			 * if the cursor key presses
+			 * are not detected may be
+			 * this needs better logic
+			 */
+			if ((0 == (cur_rcmap[3] & BITSET(0, 3))) &&
+			    (0 == (cur_rcmap[4] & BITSET(0, 3))) &&
+			    (0 == (cur_rcmap[5] & BITSET(0, 3))) &&
+			    (0 == (cur_rcmap[6] & BITSET(0, 3)))) {
+				scancode = ((col * kpp_dev.kpp_rows) + row);
+				KPress = 1;
+				kpp_dev.iKeyState = KStateUp;
+				flag = 1;
+				pr_debug("Press (%d, %d) scan=%d Kpress=%d\n",
+					 row, col, scancode, KPress);
+			}
+		}
+	} else {
+		if ((flag == 0) && (3 == col)
+		    && ((3 == row) || (4 == row) || (5 == row)
+			|| (6 == row))) {
+			if (first_set == 0) {
+				first_set = 1;
+				first_row = row;
+			} else {
+				first_set = 0;
+				if (((first_row == 6) || (first_row == 3))
+				    && ((row == 6) || (row == 3)))
+					scancode = rel_down_code;
+				else if (((first_row == 3) || (first_row == 5))
+					 && ((row == 3) || (row == 5)))
+					scancode = rel_left_code;
+				else if (((first_row == 6) || (first_row == 4))
+					 && ((row == 6) || (row == 4)))
+					scancode = rel_right_code;
+				else if (((first_row == 4) || (first_row == 5))
+					 && ((row == 4) || (row == 5)))
+					scancode = rel_up_code;
+				KPress = 0;
+				kpp_dev.iKeyState = KStateDown;
+				pr_debug("Release (%d, %d) scan=%d Kpress=%d\n",
+					 row, col, scancode, KPress);
+			}
+		} else {
+			/*
+			 * check for other keys only
+			 * if the cursor key presses
+			 * are not detected may be
+			 * this needs better logic
+			 */
+			if ((0 == (prev_rcmap[3] & BITSET(0, 3))) &&
+			    (0 == (prev_rcmap[4] & BITSET(0, 3))) &&
+			    (0 == (cur_rcmap[5] & BITSET(0, 3))) &&
+			    (0 == (cur_rcmap[6] & BITSET(0, 3)))) {
+				scancode = ((col * kpp_dev.kpp_rows) + row) +
+				    MXC_KEYRELEASE;
+				KPress = 0;
+				flag = 0;
+				kpp_dev.iKeyState = KStateDown;
+				pr_debug("Release (%d, %d) scan=%d Kpress=%d\n",
+					 row, col, scancode, KPress);
+			}
+		}
+	}
+	return scancode;
+}
+
+/*!
+ * This function is called to scan the keypad matrix to find out the key press
+ * and key release events. Make scancode and break scancode are generated for
+ * key press and key release events.
+ *
+ * The following scanning sequence are done for
+ * keypad row and column scanning,
+ * -# Write 1's to KPDR[15:8], setting column data to 1's
+ * -# Configure columns as totem pole outputs(for quick discharging of keypad
+ * capacitance)
+ * -# Configure columns as open-drain
+ * -# Write a single column to 0, others to 1.
+ * -# Sample row inputs and save data. Multiple key presses can be detected on
+ * a single column.
+ * -# Repeat steps the above steps for remaining columns.
+ * -# Return all columns to 0 in preparation for standby mode.
+ * -# Clear KPKD and KPKR status bit(s) by writing to a 1,
+ *    Set the KPKR synchronizer chain by writing "1" to KRSS register,
+ *    Clear the KPKD synchronizer chain by writing "1" to KDSC register
+ *
+ * @result    Number of key pressed/released.
+ */
+static int mxc_kpp_scan_matrix(void)
+{
+	unsigned short reg_val;
+	int col, row;
+	short scancode = 0;
+	int keycnt = 0;		/* How many keys are still pressed */
+
+	/*
+	 * wmb() linux kernel function which guarantees orderings in write
+	 * operations
+	 */
+	wmb();
+
+	/* save cur keypad matrix to prev */
+
+	memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+	memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+
+	for (col = 0; col < kpp_dev.kpp_cols; col++) {	/* Col */
+		/* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
+		reg_val |= 0xff00;
+		__raw_writew(reg_val, kpp_dev.base + KPDR);
+
+		/*
+		 * 3. Configure columns as totem pole outputs(for quick
+		 * discharging of keypad capacitance)
+		 */
+		reg_val = __raw_readw(kpp_dev.base + KPCR);
+		reg_val &= 0x00ff;
+		__raw_writew(reg_val, kpp_dev.base + KPCR);
+
+		udelay(2);
+
+		/*
+		 * 4. Configure columns as open-drain
+		 */
+		reg_val = __raw_readw(kpp_dev.base + KPCR);
+		reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8;
+		__raw_writew(reg_val, kpp_dev.base + KPCR);
+
+		/*
+		 * 5. Write a single column to 0, others to 1.
+		 * 6. Sample row inputs and save data. Multiple key presses
+		 * can be detected on a single column.
+		 * 7. Repeat steps 2 - 6 for remaining columns.
+		 */
+
+		/* Col bit starts at 8th bit in KPDR */
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
+		reg_val &= ~(1 << (8 + col));
+		__raw_writew(reg_val, kpp_dev.base + KPDR);
+
+		/* Delay added to avoid propagating the 0 from column to row
+		 * when scanning. */
+
+		udelay(5);
+
+		/* Read row input */
+		reg_val = __raw_readw(kpp_dev.base + KPDR);
+		for (row = 0; row < kpp_dev.kpp_rows; row++) {	/* sample row */
+			if (TEST_BIT(reg_val, row) == 0) {
+				cur_rcmap[row] = BITSET(cur_rcmap[row], col);
+				keycnt++;
+			}
+		}
+	}
+
+	/*
+	 * 8. Return all columns to 0 in preparation for standby mode.
+	 * 9. Clear KPKD and KPKR status bit(s) by writing to a .1.,
+	 * set the KPKR synchronizer chain by writing "1" to KRSS register,
+	 * clear the KPKD synchronizer chain by writing "1" to KDSC register
+	 */
+	reg_val = 0x00;
+	__raw_writew(reg_val, kpp_dev.base + KPDR);
+	reg_val = __raw_readw(kpp_dev.base + KPDR);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
+	reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS |
+	    KBD_STAT_KDSC;
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
+
+	/* Check key press status change */
+
+	/*
+	 * prev_rcmap array will contain the previous status of the keypad
+	 * matrix.  cur_rcmap array will contains the present status of the
+	 * keypad matrix. If a bit is set in the array, that (row, col) bit is
+	 * pressed, else it is not pressed.
+	 *
+	 * XORing these two variables will give us the change in bit for
+	 * particular row and column.  If a bit is set in XOR output, then that
+	 * (row, col) has a change of status from the previous state.  From
+	 * the diff variable the key press and key release of row and column
+	 * are found out.
+	 *
+	 * If the key press is determined then scancode for key pressed
+	 * can be generated using the following statement:
+	 *    scancode = ((row * 8) + col);
+	 *
+	 * If the key release is determined then scancode for key release
+	 * can be generated using the following statement:
+	 *    scancode = ((row * 8) + col) + MXC_KEYRELEASE;
+	 */
+	for (row = 0; row < kpp_dev.kpp_rows; row++) {
+		unsigned char diff;
+
+		/*
+		 * Calculate the change in the keypad row status
+		 */
+		diff = prev_rcmap[row] ^ cur_rcmap[row];
+
+		for (col = 0; col < kpp_dev.kpp_cols; col++) {
+			if ((diff >> col) & 0x1) {
+				/* There is a status change on col */
+				if ((prev_rcmap[row] & BITSET(0, col)) == 0) {
+					/*
+					 * Previous state is 0, so now
+					 * a key is pressed
+					 */
+					if (has_leaning_key) {
+						scancode =
+						    mxc_scan_matrix_leaning_key
+						    (row, col, 1);
+					} else {
+						scancode =
+						    ((row * kpp_dev.kpp_cols) +
+						     col);
+						KPress = 1;
+						kpp_dev.iKeyState = KStateUp;
+					}
+					pr_debug("Press   (%d, %d) scan=%d "
+						 "Kpress=%d\n",
+						 row, col, scancode, KPress);
+					press_scancode[row][col] =
+					    (short)scancode;
+				} else {
+					/*
+					 * Previous state is not 0, so
+					 * now a key is released
+					 */
+					if (has_leaning_key) {
+						scancode =
+						    mxc_scan_matrix_leaning_key
+						    (row, col, 0);
+					} else {
+						scancode =
+						    (row * kpp_dev.kpp_cols) +
+						    col + MXC_KEYRELEASE;
+						KPress = 0;
+						kpp_dev.iKeyState = KStateDown;
+					}
+
+					pr_debug
+					    ("Release (%d, %d) scan=%d Kpress=%d\n",
+					     row, col, scancode, KPress);
+					release_scancode[row][col] =
+					    (short)scancode;
+					keycnt++;
+				}
+			}
+		}
+	}
+
+	/*
+	 * This switch case statement is the
+	 * implementation of state machine of debounce
+	 * logic for key press/release.
+	 * The explaination of state machine is as
+	 * follows:
+	 *
+	 * KStateUp State:
+	 * This is in intial state of the state machine
+	 * this state it checks for any key presses.
+	 * The key press can be checked using the
+	 * variable KPress. If KPress is set, then key
+	 * press is identified and switches the to
+	 * KStateFirstDown state for key press to
+	 * debounce.
+	 *
+	 * KStateFirstDown:
+	 * After debounce delay(10ms), if the KPress is
+	 * still set then pass scancode generated to
+	 * input device and change the state to
+	 * KStateDown, else key press debounce is not
+	 * satisfied so change the state to KStateUp.
+	 *
+	 * KStateDown:
+	 * In this state it checks for any key release.
+	 * If KPress variable is cleared, then key
+	 * release is indicated and so, switch the
+	 * state to KStateFirstUp else to state
+	 * KStateDown.
+	 *
+	 * KStateFirstUp:
+	 * After debounce delay(10ms), if the KPress is
+	 * still reset then pass the key release
+	 * scancode to input device and change
+	 * the state to KStateUp else key release is
+	 * not satisfied so change the state to
+	 * KStateDown.
+	 */
+	switch (kpp_dev.iKeyState) {
+	case KStateUp:
+		if (KPress) {
+			/* First Down (must debounce). */
+			kpp_dev.iKeyState = KStateFirstDown;
+		} else {
+			/* Still UP.(NO Changes) */
+			kpp_dev.iKeyState = KStateUp;
+		}
+		break;
+
+	case KStateFirstDown:
+		if (KPress) {
+			for (row = 0; row < kpp_dev.kpp_rows; row++) {
+				for (col = 0; col < kpp_dev.kpp_cols; col++) {
+					if ((press_scancode[row][col] != -1)) {
+						/* Still Down, so add scancode */
+						scancode =
+						    press_scancode[row][col];
+						input_event(mxckbd_dev, EV_KEY,
+							    mxckpd_keycodes
+							    [scancode], 1);
+						if (mxckpd_keycodes[scancode] ==
+						    KEY_LEFTSHIFT) {
+							input_event(mxckbd_dev,
+								    EV_KEY,
+								    KEY_3, 1);
+						}
+						kpp_dev.iKeyState = KStateDown;
+						press_scancode[row][col] = -1;
+					}
+				}
+			}
+		} else {
+			/* Just a bounce */
+			kpp_dev.iKeyState = KStateUp;
+		}
+		break;
+
+	case KStateDown:
+		if (KPress) {
+			/* Still down (no change) */
+			kpp_dev.iKeyState = KStateDown;
+		} else {
+			/* First Up. Must debounce */
+			kpp_dev.iKeyState = KStateFirstUp;
+		}
+		break;
+
+	case KStateFirstUp:
+		if (KPress) {
+			/* Just a bounce */
+			kpp_dev.iKeyState = KStateDown;
+		} else {
+			for (row = 0; row < kpp_dev.kpp_rows; row++) {
+				for (col = 0; col < kpp_dev.kpp_cols; col++) {
+					if ((release_scancode[row][col] != -1)) {
+						scancode =
+						    release_scancode[row][col];
+						scancode =
+						    scancode - MXC_KEYRELEASE;
+						input_event(mxckbd_dev, EV_KEY,
+							    mxckpd_keycodes
+							    [scancode], 0);
+						if (mxckpd_keycodes[scancode] ==
+						    KEY_LEFTSHIFT) {
+							input_event(mxckbd_dev,
+								    EV_KEY,
+								    KEY_3, 0);
+						}
+						kpp_dev.iKeyState = KStateUp;
+						release_scancode[row][col] = -1;
+					}
+				}
+			}
+		}
+		break;
+
+	default:
+		return -EBADRQC;
+		break;
+	}
+
+	return keycnt;
+}
+
+/*!
+ * This function is called to start the timer for scanning the keypad if there
+ * is any key press. Currently this interval is  set to 10 ms. When there are
+ * no keys pressed on the keypad we return back, waiting for a keypad key
+ * press interrupt.
+ *
+ * @param data  Opaque data passed back by kernel. Not used.
+ */
+static void mxc_kpp_handle_timer(unsigned long data)
+{
+	unsigned short reg_val;
+	int i;
+
+	if (key_pad_enabled == 0) {
+		return;
+	}
+	if (mxc_kpp_scan_matrix() == 0) {
+		/*
+		 * Stop scanning and wait for interrupt.
+		 * Enable press interrupt and disable release interrupt.
+		 */
+		__raw_writew(0x00FF, kpp_dev.base + KPDR);
+		reg_val = __raw_readw(kpp_dev.base + KPSR);
+		reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD);
+		reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
+		reg_val |= KBD_STAT_KDIE;
+		reg_val &= ~KBD_STAT_KRIE;
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
+
+		/*
+		 * No more keys pressed... make sure unwanted key codes are
+		 * not given upstairs
+		 */
+		for (i = 0; i < kpp_dev.kpp_rows; i++) {
+			memset(press_scancode[i], -1,
+			       sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+			memset(release_scancode[i], -1,
+			       sizeof(release_scancode[0][0]) *
+			       kpp_dev.kpp_cols);
+		}
+		return;
+	}
+
+	/*
+	 * There are still some keys pressed, continue to scan.
+	 * We shall scan again in 10 ms. This has to be tuned according
+	 * to the requirement.
+	 */
+	kpp_dev.poll_timer.expires = jiffies + KScanRate;
+	kpp_dev.poll_timer.function = mxc_kpp_handle_timer;
+	add_timer(&kpp_dev.poll_timer);
+}
+
+/*!
+ * This function is the keypad Interrupt handler.
+ * This function checks for keypad status register (KPSR) for key press
+ * and interrupt. If key press interrupt has occurred, then the key
+ * press interrupt in the KPSR are disabled.
+ * It then calls mxc_kpp_scan_matrix to check for any key pressed/released.
+ * If any key is found to be pressed, then a timer is set to call
+ * mxc_kpp_scan_matrix function for every 10 ms.
+ *
+ * @param   irq      The Interrupt number
+ * @param   dev_id   Driver private data
+ *
+ * @result    The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *            returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ *            \b IRQ_RETVAL is defined in include/linux/interrupt.h.
+ */
+static irqreturn_t mxc_kpp_interrupt(int irq, void *dev_id)
+{
+	unsigned short reg_val;
+
+	/* Delete the polling timer */
+	del_timer(&kpp_dev.poll_timer);
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
+
+	/* Check if it is key press interrupt */
+	if (reg_val & KBD_STAT_KPKD) {
+		/*
+		 * Disable key press(KDIE status bit) interrupt
+		 */
+		reg_val &= ~KBD_STAT_KDIE;
+		__raw_writew(reg_val, kpp_dev.base + KPSR);
+	} else {
+		/* spurious interrupt */
+		return IRQ_RETVAL(0);
+	}
+	/*
+	 * Check if any keys are pressed, if so start polling.
+	 */
+	mxc_kpp_handle_timer(0);
+
+	return IRQ_RETVAL(1);
+}
+
+/*!
+ * This function is called when the keypad driver is opened.
+ * Since keypad initialization is done in __init, nothing is done in open.
+ *
+ * @param    dev    Pointer to device inode
+ *
+ * @result    The function always return 0
+ */
+static int mxc_kpp_open(struct input_dev *dev)
+{
+	return 0;
+}
+
+/*!
+ * This function is called close the keypad device.
+ * Nothing is done in this function, since every thing is taken care in
+ * __exit function.
+ *
+ * @param    dev    Pointer to device inode
+ *
+ */
+static void mxc_kpp_close(struct input_dev *dev)
+{
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This function puts the Keypad controller in low-power mode/state.
+ * If Keypad is enabled as a wake source(i.e. it can resume the system
+ * from suspend mode), the Keypad controller doesn't enter low-power state.
+ *
+ * @param   pdev  the device structure used to give information on Keypad
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  return -1 when the keypad is pressed. Otherwise, return 0
+ */
+static int mxc_kpp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	/* When the keypad is still pressed, clean up registers and timers */
+	if (timer_pending(&kpp_dev.poll_timer))
+		return -1;
+
+	if (device_may_wakeup(&pdev->dev)) {
+		enable_irq_wake(keypad->irq);
+	} else {
+		disable_irq(keypad->irq);
+		key_pad_enabled = 0;
+		clk_disable(kpp_clk);
+		gpio_keypad_inactive();
+	}
+
+	return 0;
+}
+
+/*!
+ * This function brings the Keypad controller back from low-power state.
+ * If Keypad is enabled as a wake source(i.e. it can resume the system
+ * from suspend mode), the Keypad controller doesn't enter low-power state.
+ *
+ * @param   pdev  the device structure used to give information on Keypad
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_kpp_resume(struct platform_device *pdev)
+{
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(keypad->irq);
+	} else {
+		gpio_keypad_active();
+		clk_enable(kpp_clk);
+		key_pad_enabled = 1;
+		enable_irq(keypad->irq);
+	}
+
+	return 0;
+}
+
+#else
+#define mxc_kpp_suspend  NULL
+#define mxc_kpp_resume   NULL
+#endif				/* CONFIG_PM */
+
+/*!
+ * This function is called to free the allocated memory for local arrays
+ */
+static void mxc_kpp_free_allocated(void)
+{
+
+	int i;
+
+	if (press_scancode) {
+		for (i = 0; i < kpp_dev.kpp_rows; i++) {
+			if (press_scancode[i])
+				kfree(press_scancode[i]);
+		}
+		kfree(press_scancode);
+	}
+
+	if (release_scancode) {
+		for (i = 0; i < kpp_dev.kpp_rows; i++) {
+			if (release_scancode[i])
+				kfree(release_scancode[i]);
+		}
+		kfree(release_scancode);
+	}
+
+	if (cur_rcmap)
+		kfree(cur_rcmap);
+
+	if (prev_rcmap)
+		kfree(prev_rcmap);
+
+	if (mxckbd_dev)
+		input_free_device(mxckbd_dev);
+}
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions.
+ *
+ * @return  The function returns 0 on successful registration. Otherwise returns
+ *          specific error code.
+ */
+static int mxc_kpp_probe(struct platform_device *pdev)
+{
+	int i, irq;
+	int retval;
+	unsigned int reg_val;
+	struct resource *res;
+
+	keypad = (struct keypad_data *)pdev->dev.platform_data;
+
+	kpp_dev.kpp_cols = keypad->colmax;
+	kpp_dev.kpp_rows = keypad->rowmax;
+	key_pad_enabled = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	kpp_dev.base = ioremap(res->start, res->end - res->start + 1);
+	if (!kpp_dev.base)
+		return -ENOMEM;
+
+	irq = platform_get_irq(pdev, 0);
+	keypad->irq = irq;
+
+	/* Enable keypad clock */
+	kpp_clk = clk_get(&pdev->dev, "kpp_clk");
+	clk_enable(kpp_clk);
+
+	/* IOMUX configuration for keypad */
+	gpio_keypad_active();
+
+	/* Configure keypad */
+
+	/* Enable number of rows in keypad (KPCR[7:0])
+	 * Configure keypad columns as open-drain (KPCR[15:8])
+	 *
+	 * Configure the rows/cols in KPP
+	 * LSB nibble in KPP is for 8 rows
+	 * MSB nibble in KPP is for 8 cols
+	 */
+	reg_val = __raw_readw(kpp_dev.base + KPCR);
+	reg_val |= (1 << keypad->rowmax) - 1;	/* LSB */
+	reg_val |= ((1 << keypad->colmax) - 1) << 8;	/* MSB */
+	__raw_writew(reg_val, kpp_dev.base + KPCR);
+
+	/* Write 0's to KPDR[15:8] */
+	reg_val = __raw_readw(kpp_dev.base + KPDR);
+	reg_val &= 0x00ff;
+	__raw_writew(reg_val, kpp_dev.base + KPDR);
+
+	/* Configure columns as output, rows as input (KDDR[15:0]) */
+	reg_val = __raw_readw(kpp_dev.base + KDDR);
+	reg_val |= 0xff00;
+	reg_val &= 0xff00;
+	__raw_writew(reg_val, kpp_dev.base + KDDR);
+
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
+	reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD);
+	reg_val |= KBD_STAT_KPKD;
+	reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
+	reg_val |= KBD_STAT_KDIE;
+	reg_val &= ~KBD_STAT_KRIE;
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
+
+	has_leaning_key = keypad->learning;
+	mxckpd_keycodes = keypad->matrix;
+	mxckpd_keycodes_size = keypad->rowmax * keypad->colmax;
+
+	if ((keypad->matrix == (void *)0)
+	    || (mxckpd_keycodes_size == 0)) {
+		retval = -ENODEV;
+		goto err1;
+	}
+
+	mxckbd_dev = input_allocate_device();
+	if (!mxckbd_dev) {
+		printk(KERN_ERR
+		       "mxckbd_dev: not enough memory for input device\n");
+		retval = -ENOMEM;
+		goto err1;
+	}
+
+	mxckbd_dev->keycode = (void *)mxckpd_keycodes;
+	mxckbd_dev->keycodesize = sizeof(mxckpd_keycodes[0]);
+	mxckbd_dev->keycodemax = mxckpd_keycodes_size;
+	mxckbd_dev->name = "mxckpd";
+	mxckbd_dev->id.bustype = BUS_HOST;
+	mxckbd_dev->open = mxc_kpp_open;
+	mxckbd_dev->close = mxc_kpp_close;
+
+	retval = input_register_device(mxckbd_dev);
+	if (retval < 0) {
+		printk(KERN_ERR
+		       "mxckbd_dev: failed to register input device\n");
+		goto err2;
+	}
+
+	/* allocate required memory */
+	press_scancode = kmalloc(kpp_dev.kpp_rows * sizeof(press_scancode[0]),
+				 GFP_KERNEL);
+	release_scancode =
+	    kmalloc(kpp_dev.kpp_rows * sizeof(release_scancode[0]), GFP_KERNEL);
+
+	if (!press_scancode || !release_scancode) {
+		retval = -ENOMEM;
+		goto err3;
+	}
+
+	for (i = 0; i < kpp_dev.kpp_rows; i++) {
+		press_scancode[i] = kmalloc(kpp_dev.kpp_cols
+					    * sizeof(press_scancode[0][0]),
+					    GFP_KERNEL);
+		release_scancode[i] =
+		    kmalloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0]),
+			    GFP_KERNEL);
+
+		if (!press_scancode[i] || !release_scancode[i]) {
+			retval = -ENOMEM;
+			goto err3;
+		}
+	}
+
+	cur_rcmap =
+	    kmalloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0]), GFP_KERNEL);
+	prev_rcmap =
+	    kmalloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0]), GFP_KERNEL);
+
+	if (!cur_rcmap || !prev_rcmap) {
+		retval = -ENOMEM;
+		goto err3;
+	}
+
+	__set_bit(EV_KEY, mxckbd_dev->evbit);
+
+	for (i = 0; i < mxckpd_keycodes_size; i++)
+		__set_bit(mxckpd_keycodes[i], mxckbd_dev->keybit);
+
+	for (i = 0; i < kpp_dev.kpp_rows; i++) {
+		memset(press_scancode[i], -1,
+		       sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+		memset(release_scancode[i], -1,
+		       sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols);
+	}
+	memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+	memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+
+	key_pad_enabled = 1;
+	/* Initialize the polling timer */
+	init_timer(&kpp_dev.poll_timer);
+
+	/*
+	 * Request for IRQ number for keypad port. The Interrupt handler
+	 * function (mxc_kpp_interrupt) is called when ever interrupt occurs on
+	 * keypad port.
+	 */
+	retval = request_irq(irq, mxc_kpp_interrupt, 0, MOD_NAME, MOD_NAME);
+	if (retval) {
+		pr_debug("KPP: request_irq(%d) returned error %d\n",
+			 MXC_INT_KPP, retval);
+		goto err3;
+	}
+
+	/* By default, devices should wakeup if they can */
+	/* So keypad is set as "should wakeup" as it can */
+	device_init_wakeup(&pdev->dev, 1);
+
+	return 0;
+
+      err3:
+	mxc_kpp_free_allocated();
+      err2:
+	input_free_device(mxckbd_dev);
+      err1:
+	free_irq(irq, MOD_NAME);
+	clk_disable(kpp_clk);
+	clk_put(kpp_clk);
+	return retval;
+}
+
+/*!
+ * Dissociates the driver from the kpp device.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_kpp_remove(struct platform_device *pdev)
+{
+	unsigned short reg_val;
+
+	/*
+	 * Clear the KPKD status flag (write 1 to it) and synchronizer chain.
+	 * Set KDIE control bit, clear KRIE control bit (avoid false release
+	 * events. Disable the keypad GPIO pins.
+	 */
+	__raw_writew(0x00, kpp_dev.base + KPCR);
+	__raw_writew(0x00, kpp_dev.base + KPDR);
+	__raw_writew(0x00, kpp_dev.base + KDDR);
+
+	reg_val = __raw_readw(kpp_dev.base + KPSR);
+	reg_val |= KBD_STAT_KPKD;
+	reg_val &= ~KBD_STAT_KRSS;
+	reg_val |= KBD_STAT_KDIE;
+	reg_val &= ~KBD_STAT_KRIE;
+	__raw_writew(reg_val, kpp_dev.base + KPSR);
+
+	gpio_keypad_inactive();
+	clk_disable(kpp_clk);
+	clk_put(kpp_clk);
+
+	KPress = 0;
+
+	del_timer(&kpp_dev.poll_timer);
+
+	free_irq(keypad->irq, MOD_NAME);
+	input_unregister_device(mxckbd_dev);
+
+	mxc_kpp_free_allocated();
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_kpd_driver = {
+	.driver = {
+		   .name = "mxc_keypad",
+		   .bus = &platform_bus_type,
+		   },
+	.suspend = mxc_kpp_suspend,
+	.resume = mxc_kpp_resume,
+	.probe = mxc_kpp_probe,
+	.remove = mxc_kpp_remove
+};
+
+/*!
+ * This function is called for module initialization.
+ * It registers keypad char driver and requests for KPP irq number. This
+ * function does the initialization of the keypad device.
+ *
+ * The following steps are used for keypad configuration,\n
+ * -# Enable number of rows in the keypad control register (KPCR[7:0}).\n
+ * -# Write 0's to KPDR[15:8]\n
+ * -# Configure keypad columns as open-drain (KPCR[15:8])\n
+ * -# Configure columns as output, rows as input (KDDR[15:0])\n
+ * -# Clear the KPKD status flag (write 1 to it) and synchronizer chain\n
+ * -# Set KDIE control bit, clear KRIE control bit\n
+ * In this function the keypad queue initialization is done.
+ * The keypad IOMUX configuration are done here.*
+
+ *
+ * @return      0 on success and a non-zero value on failure.
+ */
+static int __init mxc_kpp_init(void)
+{
+	printk(KERN_INFO "MXC keypad loaded\n");
+	platform_driver_register(&mxc_kpd_driver);
+	return 0;
+}
+
+/*!
+ * This function is called whenever the module is removed from the kernel. It
+ * unregisters the keypad driver from kernel and frees the irq number.
+ * This function puts the keypad to standby mode. The keypad interrupts are
+ * disabled. It calls gpio_keypad_inactive function to switch gpio
+ * configuration into default state.
+ *
+ */
+static void __exit mxc_kpp_cleanup(void)
+{
+	platform_driver_unregister(&mxc_kpd_driver);
+}
+
+module_init(mxc_kpp_init);
+module_exit(mxc_kpp_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC Keypad Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/keyboard/mxs-kbd.c b/drivers/input/keyboard/mxs-kbd.c
new file mode 100644
index 000000000000..ed04a7eff19a
--- /dev/null
+++ b/drivers/input/keyboard/mxs-kbd.c
@@ -0,0 +1,364 @@
+/*
+ * Keypad ladder driver for Freescale MXS boards
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <mach/device.h>
+#include <mach/hardware.h>
+#include <mach/regs-lradc.h>
+#include <mach/lradc.h>
+
+#define BUTTON_PRESS_THRESHOLD  3300
+#define LRADC_NOISE_MARGIN      100
+
+/* this value represents the the lradc value at 3.3V ( 3.3V / 0.000879 V/b ) */
+#define TARGET_VDDIO_LRADC_VALUE 3754
+
+struct mxskbd_data {
+	struct input_dev *input;
+	int last_button;
+	int irq;
+	int btn_irq;
+	struct mxskbd_keypair *keycodes;
+	unsigned int base;
+	int chan;
+	unsigned int btn_enable; /* detect enable bits */
+	unsigned int btn_irq_stat; /* detect irq status bits */
+	unsigned int btn_irq_ctrl; /* detect irq enable bits */
+};
+
+static int delay1 = 500;
+static int delay2 = 200;
+
+static int mxskbd_open(struct input_dev *dev);
+static void mxskbd_close(struct input_dev *dev);
+
+static struct mxskbd_data *mxskbd_data_alloc(struct platform_device *pdev,
+		struct mxskbd_keypair *keys)
+{
+	struct mxskbd_data *d = kzalloc(sizeof(*d), GFP_KERNEL);
+
+	if (!d)
+		return NULL;
+
+	if (!keys) {
+		dev_err(&pdev->dev,
+			"No keycodes in platform_data, bailing out.\n");
+		kfree(d);
+		return NULL;
+	}
+	d->keycodes = keys;
+
+	d->input = input_allocate_device();
+	if (!d->input) {
+		kfree(d);
+		return NULL;
+	}
+
+	d->input->phys = "onboard";
+	d->input->uniq = "0000'0000";
+	d->input->name = pdev->name;
+	d->input->id.bustype = BUS_HOST;
+	d->input->open = mxskbd_open;
+	d->input->close = mxskbd_close;
+	d->input->dev.parent = &pdev->dev;
+
+	set_bit(EV_KEY, d->input->evbit);
+	set_bit(EV_REL, d->input->evbit);
+	set_bit(EV_REP, d->input->evbit);
+
+
+	d->last_button = -1;
+
+	while (keys->raw >= 0) {
+		set_bit(keys->kcode, d->input->keybit);
+		keys++;
+	}
+
+	return d;
+}
+
+static inline struct input_dev *GET_INPUT_DEV(struct mxskbd_data *d)
+{
+	BUG_ON(!d);
+	return d->input;
+}
+
+static void mxskbd_data_free(struct mxskbd_data *d)
+{
+	if (!d)
+		return;
+	if (d->input)
+		input_free_device(d->input);
+	kfree(d);
+}
+
+static unsigned mxskbd_decode_button(struct mxskbd_keypair *codes,
+			int raw_button)
+
+{
+	pr_debug("Decoding %d\n", raw_button);
+	while (codes->raw != -1) {
+		if ((raw_button >= (codes->raw - LRADC_NOISE_MARGIN)) &&
+		    (raw_button < (codes->raw + LRADC_NOISE_MARGIN))) {
+			pr_debug("matches code 0x%x = %d\n",
+				codes->kcode, codes->kcode);
+			return codes->kcode;
+		}
+		codes++;
+	}
+	return (unsigned)-1; /* invalid key */
+}
+
+
+static irqreturn_t mxskbd_irq_handler(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct mxskbd_data *devdata = platform_get_drvdata(pdev);
+	u16 raw_button, normalized_button, vddio;
+	unsigned btn;
+
+	if (devdata->btn_irq == irq) {
+		__raw_writel(devdata->btn_irq_stat,
+			     devdata->base + HW_LRADC_CTRL1_CLR);
+		__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << devdata->chan,
+			     devdata->base + HW_LRADC_CTRL1_CLR);
+		__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << devdata->chan,
+			     devdata->base + HW_LRADC_CTRL1_SET);
+		return IRQ_HANDLED;
+	}
+
+	raw_button = __raw_readl(devdata->base + HW_LRADC_CHn(devdata->chan)) &
+				 BM_LRADC_CHn_VALUE;
+	vddio = hw_lradc_vddio();
+	BUG_ON(vddio == 0);
+
+	normalized_button = (raw_button * TARGET_VDDIO_LRADC_VALUE) /
+		vddio;
+
+	if (normalized_button < BUTTON_PRESS_THRESHOLD &&
+	    devdata->last_button < 0) {
+		btn = mxskbd_decode_button(devdata->keycodes,
+					   normalized_button);
+		if (btn < KEY_MAX) {
+			devdata->last_button = btn;
+			input_report_key(GET_INPUT_DEV(devdata),
+					 devdata->last_button, !0);
+		} else
+			dev_err(&pdev->dev, "Invalid button: raw = %d, "
+				"normalized = %d, vddio = %d\n",
+				raw_button, normalized_button, vddio);
+	} else if (devdata->last_button > 0 &&
+		   normalized_button >= BUTTON_PRESS_THRESHOLD) {
+		input_report_key(GET_INPUT_DEV(devdata),
+				 devdata->last_button, 0);
+		devdata->last_button = -1;
+		if (devdata->btn_irq > 0)
+			__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN <<
+					devdata->chan,
+				     devdata->base + HW_LRADC_CTRL1_CLR);
+	}
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << devdata->chan,
+		     devdata->base + HW_LRADC_CTRL1_CLR);
+	return IRQ_HANDLED;
+}
+
+static int mxskbd_open(struct input_dev *dev)
+{
+	/* enable clock */
+	return 0;
+}
+
+static void mxskbd_close(struct input_dev *dev)
+{
+	/* disable clock */
+}
+
+static void mxskbd_hwinit(struct platform_device *pdev)
+{
+	struct mxskbd_data *d = platform_get_drvdata(pdev);
+
+	hw_lradc_init_ladder(d->chan, LRADC_DELAY_TRIGGER_BUTTON, 200);
+	if (d->btn_irq > 0) {
+		__raw_writel(d->btn_enable, d->base + HW_LRADC_CTRL0_SET);
+		__raw_writel(d->btn_irq_ctrl, d->base + HW_LRADC_CTRL1_SET);
+	} else {
+		__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << d->chan,
+			     d->base + HW_LRADC_CTRL1_CLR);
+		__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan,
+			     d->base + HW_LRADC_CTRL1_SET);
+	}
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, !0);
+}
+
+#ifdef CONFIG_PM
+static int mxskbd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxskbd_data *d = platform_get_drvdata(pdev);
+
+	hw_lradc_stop_ladder(d->chan, LRADC_DELAY_TRIGGER_BUTTON);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, 0);
+	hw_lradc_unuse_channel(d->chan);
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan,
+		     d->base + HW_LRADC_CTRL1_CLR);
+	mxskbd_close(d->input);
+	return 0;
+}
+
+static int mxskbd_resume(struct platform_device *pdev)
+{
+	struct mxskbd_data *d = platform_get_drvdata(pdev);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan,
+		     d->base + HW_LRADC_CTRL1_SET);
+	mxskbd_open(d->input);
+	hw_lradc_use_channel(d->chan);
+	mxskbd_hwinit(pdev);
+	return 0;
+}
+#endif
+
+static int __devinit mxskbd_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct resource *res;
+	struct mxskbd_data *d;
+	struct mxs_kbd_plat_data *plat_data;
+
+	plat_data = (struct mxs_kbd_plat_data *)pdev->dev.platform_data;
+	if (plat_data == NULL)
+		return -ENODEV;
+
+	/* Create and register the input driver. */
+	d = mxskbd_data_alloc(pdev, plat_data->keypair);
+	if (!d) {
+		dev_err(&pdev->dev, "Cannot allocate driver structures\n");
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		err = -ENODEV;
+		goto err_out;
+	}
+	d->base = (unsigned int)IO_ADDRESS(res->start);
+	d->chan = plat_data->channel;
+	d->irq = platform_get_irq(pdev, 0);
+	d->btn_irq = platform_get_irq(pdev, 1);
+	d->btn_enable = plat_data->btn_enable;
+	d->btn_irq_stat = plat_data->btn_irq_stat;
+	d->btn_irq_ctrl = plat_data->btn_irq_ctrl;
+
+	platform_set_drvdata(pdev, d);
+
+	err = request_irq(d->irq, mxskbd_irq_handler,
+			  IRQF_DISABLED, pdev->name, pdev);
+	if (err) {
+		dev_err(&pdev->dev, "Cannot request keypad IRQ\n");
+		goto err_free_dev;
+	}
+
+	if (d->btn_irq > 0) {
+		err = request_irq(d->btn_irq, mxskbd_irq_handler,
+			  IRQF_DISABLED, pdev->name, pdev);
+		if (err) {
+			dev_err(&pdev->dev,
+				"Cannot request keybad detect IRQ\n");
+			goto err_free_irq;
+		}
+	}
+
+	/* Register the input device */
+	err = input_register_device(GET_INPUT_DEV(d));
+	if (err)
+		goto err_free_irq2;
+
+	/* these two have to be set after registering the input device */
+	d->input->rep[REP_DELAY] = delay1;
+	d->input->rep[REP_PERIOD] = delay2;
+
+	hw_lradc_use_channel(d->chan);
+	mxskbd_hwinit(pdev);
+
+	return 0;
+
+err_free_irq2:
+	platform_set_drvdata(pdev, NULL);
+	if (d->btn_irq > 0)
+		free_irq(d->btn_irq, pdev);
+err_free_irq:
+	free_irq(d->irq, pdev);
+err_free_dev:
+	mxskbd_data_free(d);
+err_out:
+	return err;
+}
+
+static int __devexit mxskbd_remove(struct platform_device *pdev)
+{
+	struct mxskbd_data *d = platform_get_drvdata(pdev);
+
+	hw_lradc_unuse_channel(d->chan);
+	input_unregister_device(GET_INPUT_DEV(d));
+	free_irq(d->irq, pdev);
+	if (d->btn_irq > 0)
+		free_irq(d->btn_irq, pdev);
+	mxskbd_data_free(d);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver mxskbd_driver = {
+	.probe		= mxskbd_probe,
+	.remove		= __devexit_p(mxskbd_remove),
+#ifdef CONFIG_PM
+	.suspend	= mxskbd_suspend,
+	.resume		= mxskbd_resume,
+#endif
+	.driver		= {
+		.name	= "mxs-kbd",
+	},
+};
+
+static int __init mxskbd_init(void)
+{
+	return platform_driver_register(&mxskbd_driver);
+}
+
+static void __exit mxskbd_exit(void)
+{
+	platform_driver_unregister(&mxskbd_driver);
+}
+
+module_init(mxskbd_init);
+module_exit(mxskbd_exit);
+MODULE_DESCRIPTION("Freescale keyboard driver for mxs family");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>")
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/keyboard/stmp3xxx-kbd.c b/drivers/input/keyboard/stmp3xxx-kbd.c
new file mode 100644
index 000000000000..a230aa92710c
--- /dev/null
+++ b/drivers/input/keyboard/stmp3xxx-kbd.c
@@ -0,0 +1,307 @@
+/*
+ * Keypad ladder driver for Freescale STMP37XX/STMP378X boards
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <mach/regs-lradc.h>
+#include <mach/lradc.h>
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+
+#define BUTTON_PRESS_THRESHOLD  3300
+#define LRADC_NOISE_MARGIN      100
+
+/* this value represents the the lradc value at 3.3V ( 3.3V / 0.000879 V/b ) */
+#define TARGET_VDDIO_LRADC_VALUE 3754
+
+struct stmpkbd_data {
+	struct input_dev *input;
+	int last_button;
+	int irq;
+	struct stmpkbd_keypair *keycodes;
+};
+
+static int delay1 = 500;
+static int delay2 = 200;
+
+static int stmpkbd_open(struct input_dev *dev);
+static void stmpkbd_close(struct input_dev *dev);
+
+static struct stmpkbd_data *stmpkbd_data_alloc(struct platform_device *pdev,
+		struct stmpkbd_keypair *keys)
+{
+	struct stmpkbd_data *d = kzalloc(sizeof(*d), GFP_KERNEL);
+
+	if (!d)
+		return NULL;
+
+	if (!keys) {
+		dev_err(&pdev->dev,
+			"No keycodes in platform_data, bailing out.\n");
+		kfree(d);
+		return NULL;
+	}
+	d->keycodes = keys;
+
+	d->input = input_allocate_device();
+	if (!d->input) {
+		kfree(d);
+		return NULL;
+	}
+
+	d->input->phys = "onboard";
+	d->input->uniq = "0000'0000";
+	d->input->name = pdev->name;
+	d->input->id.bustype = BUS_HOST;
+	d->input->open = stmpkbd_open;
+	d->input->close = stmpkbd_close;
+	d->input->dev.parent = &pdev->dev;
+
+	set_bit(EV_KEY, d->input->evbit);
+	set_bit(EV_REL, d->input->evbit);
+	set_bit(EV_REP, d->input->evbit);
+
+
+	d->last_button = -1;
+
+	while (keys->raw >= 0) {
+		set_bit(keys->kcode, d->input->keybit);
+		keys++;
+	}
+
+	return d;
+}
+
+static inline struct input_dev *GET_INPUT_DEV(struct stmpkbd_data *d)
+{
+	BUG_ON(!d);
+	return d->input;
+}
+
+static void stmpkbd_data_free(struct stmpkbd_data *d)
+{
+	if (!d)
+		return;
+	if (d->input)
+		input_free_device(d->input);
+	kfree(d);
+}
+
+static unsigned stmpkbd_decode_button(struct stmpkbd_keypair *codes,
+			int raw_button)
+
+{
+	pr_debug("Decoding %d\n", raw_button);
+	while (codes->raw != -1) {
+		if ((raw_button > (codes->raw - LRADC_NOISE_MARGIN)) &&
+		    (raw_button < (codes->raw + LRADC_NOISE_MARGIN))) {
+			pr_debug("matches code 0x%x = %d\n",
+				codes->kcode, codes->kcode);
+			return codes->kcode;
+		}
+		codes++;
+	}
+	return (unsigned)-1; /* invalid key */
+}
+
+
+static irqreturn_t stmpkbd_irq_handler(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct stmpkbd_data *devdata = platform_get_drvdata(pdev);
+	u16 raw_button, normalized_button, vddio;
+	unsigned btn;
+
+	raw_button = __raw_readl(REGS_LRADC_BASE +
+			HW_LRADC_CHn(LRADC_CH0)) & BM_LRADC_CHn_VALUE;
+	vddio = hw_lradc_vddio();
+	BUG_ON(vddio == 0);
+
+	normalized_button = (raw_button * TARGET_VDDIO_LRADC_VALUE) /
+		vddio;
+
+	if (normalized_button < BUTTON_PRESS_THRESHOLD &&
+	    devdata->last_button < 0) {
+
+		btn = stmpkbd_decode_button(devdata->keycodes,
+				normalized_button);
+
+		if (btn < KEY_MAX) {
+			devdata->last_button = btn;
+			input_report_key(GET_INPUT_DEV(devdata),
+				devdata->last_button, !0);
+		} else
+			dev_err(&pdev->dev, "Invalid button: raw = %d, "
+				"normalized = %d, vddio = %d\n",
+				raw_button, normalized_button, vddio);
+	} else if (devdata->last_button > 0 &&
+		normalized_button >= BUTTON_PRESS_THRESHOLD) {
+
+		input_report_key(GET_INPUT_DEV(devdata),
+				devdata->last_button, 0);
+		devdata->last_button = -1;
+
+	}
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	return IRQ_HANDLED;
+}
+
+static int stmpkbd_open(struct input_dev *dev)
+{
+	/* enable clock */
+	return 0;
+}
+
+static void stmpkbd_close(struct input_dev *dev)
+{
+	/* disable clock */
+}
+
+static void stmpkbd_hwinit(struct platform_device *pdev)
+{
+	hw_lradc_init_ladder(LRADC_CH0, LRADC_DELAY_TRIGGER_BUTTON, 200);
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_SET);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, !0);
+}
+
+static int stmpkbd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+#ifdef CONFIG_PM
+	struct input_dev *idev = platform_get_drvdata(pdev);
+
+	hw_lradc_stop_ladder(LRADC_CH0, LRADC_DELAY_TRIGGER_BUTTON);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, 0);
+	hw_lradc_unuse_channel(LRADC_CH0);
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	stmpkbd_close(idev);
+#endif
+	return 0;
+}
+
+static int stmpkbd_resume(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM
+	struct input_dev *idev = platform_get_drvdata(pdev);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_SET);
+	stmpkbd_open(idev);
+	hw_lradc_use_channel(LRADC_CH0);
+	stmpkbd_hwinit(pdev);
+#endif
+	return 0;
+}
+
+static int __devinit stmpkbd_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	int irq = platform_get_irq(pdev, 0);
+	struct stmpkbd_data *d;
+
+	/* Create and register the input driver. */
+	d = stmpkbd_data_alloc(pdev,
+		(struct stmpkbd_keypair *)pdev->dev.platform_data);
+	if (!d) {
+		dev_err(&pdev->dev, "Cannot allocate driver structures\n");
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	d->irq = irq;
+	err = request_irq(irq, stmpkbd_irq_handler,
+		IRQF_DISABLED, pdev->name, pdev);
+	if (err) {
+		dev_err(&pdev->dev, "Cannot request keypad IRQ\n");
+		goto err_free_dev;
+	}
+
+	platform_set_drvdata(pdev, d);
+
+	/* Register the input device */
+	err = input_register_device(GET_INPUT_DEV(d));
+	if (err)
+		goto err_free_irq;
+
+	/* these two have to be set after registering the input device */
+	d->input->rep[REP_DELAY] = delay1;
+	d->input->rep[REP_PERIOD] = delay2;
+
+	hw_lradc_use_channel(LRADC_CH0);
+	stmpkbd_hwinit(pdev);
+
+	return 0;
+
+err_free_irq:
+	platform_set_drvdata(pdev, NULL);
+	free_irq(irq, pdev);
+err_free_dev:
+	stmpkbd_data_free(d);
+err_out:
+	return err;
+}
+
+static int __devexit stmpkbd_remove(struct platform_device *pdev)
+{
+	struct stmpkbd_data *d = platform_get_drvdata(pdev);
+
+	hw_lradc_unuse_channel(LRADC_CH0);
+	input_unregister_device(GET_INPUT_DEV(d));
+	free_irq(d->irq, pdev);
+	stmpkbd_data_free(d);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver stmpkbd_driver = {
+	.probe		= stmpkbd_probe,
+	.remove		= __devexit_p(stmpkbd_remove),
+	.suspend	= stmpkbd_suspend,
+	.resume		= stmpkbd_resume,
+	.driver		= {
+		.name	= "stmp3xxx-keyboard",
+	},
+};
+
+static int __init stmpkbd_init(void)
+{
+	return platform_driver_register(&stmpkbd_driver);
+}
+
+static void __exit stmpkbd_exit(void)
+{
+	platform_driver_unregister(&stmpkbd_driver);
+}
+
+module_init(stmpkbd_init);
+module_exit(stmpkbd_exit);
+MODULE_DESCRIPTION("Freescale STMP3xxxx keyboard driver");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 1acfa3a05aad..afee839ba338 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -40,6 +40,15 @@ config INPUT_M68K_BEEP
 	tristate "M68k Beeper support"
 	depends on M68K
 
+config INPUT_STMP3XXX_ROTDEC
+	tristate "STMP3xxx Rotary Decoder support"
+	depends on MACH_STMP378X
+	select INPUT_POLLDEV
+	help
+	  Say Y here for support for the rotary decoder on STMP3xxx
+
+	  If compiled as a module, it will be called stmp3xxx_rotdec
+
 config INPUT_APANEL
 	tristate "Fujitsu Lifebook Application Panel buttons"
 	depends on X86 && I2C && LEDS_CLASS
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 0d979fd4cd57..0cb5e795cfb4 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON)	+= twl4030-pwrbutton.o
 obj-$(CONFIG_INPUT_UINPUT)		+= uinput.o
 obj-$(CONFIG_INPUT_WISTRON_BTNS)	+= wistron_btns.o
 obj-$(CONFIG_INPUT_YEALINK)		+= yealink.o
+obj-$(CONFIG_INPUT_STMP3XXX_ROTDEC)	+= stmp3xxx_rotdec.o
diff --git a/drivers/input/misc/stmp3xxx_rotdec.c b/drivers/input/misc/stmp3xxx_rotdec.c
new file mode 100644
index 000000000000..621db95dba8c
--- /dev/null
+++ b/drivers/input/misc/stmp3xxx_rotdec.c
@@ -0,0 +1,174 @@
+/*
+ * Freescale STMP3XXX Rotary Encoder Driver
+ *
+ * Author: Drew Benedetti <drewb@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/input-polldev.h>
+#include <mach/regs-timrot.h>
+#include <mach/rotdec.h>
+#include <mach/platform.h>
+
+static int relative;
+static unsigned int poll_interval = 500;
+
+void stmp3xxx_rotdec_flush(struct input_polled_dev *dev)
+{
+	/* in relative mode, reading the counter resets it */
+	if (relative)
+		__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_ROTCOUNT);
+}
+
+void stmp3xxx_rotdec_poll(struct input_polled_dev *dev)
+{
+	s16 cnt = __raw_readl(REGS_TIMROT_BASE + HW_TIMROT_ROTCOUNT) & BM_TIMROT_ROTCOUNT_UPDOWN;
+	if (relative)
+		input_report_rel(dev->input, REL_WHEEL, cnt);
+	else
+		input_report_abs(dev->input, ABS_WHEEL, cnt);
+}
+
+struct input_polled_dev *rotdec;
+static u32 rotctrl;
+
+static int stmp3xxx_rotdec_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+
+	/* save original state of HW_TIMROT_ROTCTRL */
+	rotctrl = __raw_readl(REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+
+	if (!(rotctrl & BM_TIMROT_ROTCTRL_ROTARY_PRESENT)) {
+		dev_info(&pdev->dev, "No rotary decoder present\n");
+		rc = -ENODEV;
+		goto err_rotdec_present;
+	} else {
+		/* I had to add some extra line breaks in here
+		 * to avoid lines >80 chars wide
+		 */
+		__raw_writel(
+		 BF(0x0, TIMROT_ROTCTRL_DIVIDER) | /* 32kHz divider - 1 */
+		 BF(BV_TIMROT_ROTCTRL_OVERSAMPLE__2X,
+			TIMROT_ROTCTRL_OVERSAMPLE) |
+		 BF(BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB,
+			TIMROT_ROTCTRL_SELECT_B) |
+		 BF(BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA,
+			TIMROT_ROTCTRL_SELECT_A)
+		, REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+		__raw_writel(
+		 BM_TIMROT_ROTCTRL_POLARITY_B |
+		 BM_TIMROT_ROTCTRL_POLARITY_A
+		, REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_CLR);
+
+		if (relative)
+			__raw_writel(BM_TIMROT_ROTCTRL_RELATIVE,
+				REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_SET);
+		else
+			__raw_writel(BM_TIMROT_ROTCTRL_RELATIVE,
+				REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_CLR);
+
+		rc = rotdec_pinmux_request();
+		if (rc) {
+			dev_err(&pdev->dev,
+				"Pin request failed (err=%d)\n", rc);
+			goto err_pinmux;
+		}
+
+		/* set up input_polled_dev */
+		rotdec = input_allocate_polled_device();
+		if (!rotdec) {
+			dev_err(&pdev->dev,
+				"Unable to allocate polled device\n");
+			rc = -ENOMEM;
+			goto err_alloc_polldev;
+		}
+		rotdec->flush = stmp3xxx_rotdec_flush;
+		rotdec->poll = stmp3xxx_rotdec_poll;
+		rotdec->poll_interval = poll_interval; /* msec */
+
+		rotdec->input->name = "stmp3xxx-rotdec";
+		if (relative)
+			input_set_capability(rotdec->input, EV_REL, REL_WHEEL);
+		else {
+			input_set_capability(rotdec->input, EV_ABS, ABS_WHEEL);
+			input_set_abs_params(rotdec->input, ABS_WHEEL,
+					-32768, 32767, 0, 0);
+		}
+
+		rc = input_register_polled_device(rotdec);
+		if (rc) {
+			dev_err(&pdev->dev,
+				"Unable to register rotary decoder (err=%d)\n",
+				rc);
+			goto err_reg_polldev;
+		}
+	}
+
+	return 0;
+
+err_reg_polldev:
+	input_free_polled_device(rotdec);
+err_alloc_polldev:
+	rotdec_pinmux_free();
+err_pinmux:
+	/* restore original register state */
+	__raw_writel(rotctrl, REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+
+err_rotdec_present:
+	return rc;
+}
+
+static int stmp3xxx_rotdec_remove(struct platform_device *pdev)
+{
+	input_unregister_polled_device(rotdec);
+	input_free_polled_device(rotdec);
+
+	rotdec_pinmux_free();
+
+	/* restore original register state */
+	__raw_writel(rotctrl, REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+
+	return 0;
+}
+
+static struct platform_driver stmp3xxx_rotdec_driver = {
+	.probe	= stmp3xxx_rotdec_probe,
+	.remove	= stmp3xxx_rotdec_remove,
+	.driver	= {
+		.name	= "stmp3xxx-rotdec",
+	},
+};
+
+static int __init stmp3xxx_rotdec_init(void)
+{
+	return platform_driver_register(&stmp3xxx_rotdec_driver);
+}
+
+static void __exit stmp3xxx_rotdec_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_rotdec_driver);
+}
+
+module_init(stmp3xxx_rotdec_init);
+module_exit(stmp3xxx_rotdec_exit);
+
+module_param(relative, bool, 0600);
+module_param(poll_interval, uint, 0600);
+
+MODULE_AUTHOR("Drew Benedetti <drewb@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP3xxx rotary decoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 72e2712c7e2a..cd489febde11 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -225,6 +225,46 @@ config TOUCHSCREEN_HP7XX
 	  To compile this driver as a module, choose M here: the
 	  module will be called jornada720_ts.
 
+config TOUCHSCREEN_MXC
+	tristate "MXC touchscreen input driver"
+	depends on MXC_MC13783_ADC || MXC_MC13892_ADC
+	help
+	  Say Y here if you have an MXC based board with touchscreen
+	  attached to it.
+
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called mxc_ts.
+
+config TOUCHSCREEN_IMX_ADC
+	tristate "Freescale i.MX ADC touchscreen input driver"
+	depends on IMX_ADC
+	help
+	  Say Y here if you have a Freescale i.MX based board with a
+	  touchscreen interfaced to the processor's integrated ADC.
+
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called imx_adc_ts.
+
+config TOUCHSCREEN_STMP3XXX
+	tristate "STMP3XXX LRADC-based touchscreen"
+	depends on ARCH_STMP3XXX
+	select SERIO
+	help
+	  Say Y here if you want to enable TMP3XXX LRADC-based touchscreen.
+	  module will be called stmp3xxx_ts.
+
+config TOUCHSCREEN_MXS
+	tristate "MXS LRADC-based touchscreen"
+	depends on ARCH_MXS
+	select SERIO
+	help
+	  Say Y here if you want to enable MXS LRADC-based touchscreen.
+	  module will be called mxs-ts.
+
 config TOUCHSCREEN_HTCPEN
 	tristate "HTC Shift X9500 touchscreen"
 	depends on ISA
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 3e1c5e0b952f..05589702fdaa 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -23,6 +23,10 @@ obj-$(CONFIG_TOUCHSCREEN_MK712)		+= mk712.o
 obj-$(CONFIG_TOUCHSCREEN_HP600)		+= hp680_ts_input.o
 obj-$(CONFIG_TOUCHSCREEN_HP7XX)		+= jornada720_ts.o
 obj-$(CONFIG_TOUCHSCREEN_HTCPEN)	+= htcpen.o
+obj-$(CONFIG_TOUCHSCREEN_MXC)		+= mxc_ts.o
+obj-$(CONFIG_TOUCHSCREEN_IMX_ADC)	+= imx_adc_ts.o
+obj-$(CONFIG_TOUCHSCREEN_STMP3XXX)	+= stmp3xxx_ts.o
+obj-$(CONFIG_TOUCHSCREEN_MXS)		+= mxs-ts.o
 obj-$(CONFIG_TOUCHSCREEN_USB_COMPOSITE)	+= usbtouchscreen.o
 obj-$(CONFIG_TOUCHSCREEN_PENMOUNT)	+= penmount.o
 obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213)	+= touchit213.o
diff --git a/drivers/input/touchscreen/imx_adc_ts.c b/drivers/input/touchscreen/imx_adc_ts.c
new file mode 100644
index 000000000000..ec43a16213ae
--- /dev/null
+++ b/drivers/input/touchscreen/imx_adc_ts.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file imx_adc_ts.c
+ *
+ * @brief Driver for the Freescale Semiconductor i.MX ADC touchscreen.
+ *
+ * This touchscreen driver is designed as a standard input driver.  It is a
+ * wrapper around the low level ADC driver. Much of the hardware configuration
+ * and touchscreen functionality is implemented in the low level ADC driver.
+ * During initialization, this driver creates a kernel thread.  This thread
+ * then calls the ADC driver to obtain touchscreen values continously. These
+ * values are then passed to the input susbsystem.
+ *
+ * @ingroup touchscreen
+ */
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/freezer.h>
+#include <linux/imx_adc.h>
+
+#define IMX_ADC_TS_NAME	"imx_adc_ts"
+
+static struct input_dev *imx_inputdev;
+static u32 input_ts_installed;
+
+static int ts_thread(void *arg)
+{
+	struct t_touch_screen ts_sample;
+	int wait = 0;
+	daemonize("imx_adc_ts");
+	while (input_ts_installed) {
+		try_to_freeze();
+
+		memset(&ts_sample, 0, sizeof(ts_sample));
+		if (0 != imx_adc_get_touch_sample(&ts_sample, !wait))
+			continue;
+
+		input_report_abs(imx_inputdev, ABS_X, ts_sample.x_position);
+		input_report_abs(imx_inputdev, ABS_Y, ts_sample.y_position);
+		input_report_abs(imx_inputdev, ABS_PRESSURE,
+				 ts_sample.contact_resistance);
+		input_sync(imx_inputdev);
+		wait = ts_sample.contact_resistance;
+		msleep(10);
+	}
+
+	return 0;
+}
+
+static int __init imx_adc_ts_init(void)
+{
+	int retval;
+
+	if (!is_imx_adc_ready())
+		return -ENODEV;
+
+	imx_inputdev = input_allocate_device();
+	if (!imx_inputdev) {
+		pr_err("imx_ts_init: not enough memory for input device\n");
+		return -ENOMEM;
+	}
+
+	imx_inputdev->name = IMX_ADC_TS_NAME;
+	imx_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	imx_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH);
+	imx_inputdev->absbit[0] =
+	    BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE);
+	retval = input_register_device(imx_inputdev);
+	if (retval < 0) {
+		input_free_device(imx_inputdev);
+		return retval;
+	}
+
+	input_ts_installed = 1;
+	kthread_run(ts_thread, NULL, "ts_thread");
+	pr_info("i.MX ADC input touchscreen loaded.\n");
+	return 0;
+}
+
+static void __exit imx_adc_ts_exit(void)
+{
+	input_ts_installed = 0;
+	input_unregister_device(imx_inputdev);
+
+	if (imx_inputdev) {
+		input_free_device(imx_inputdev);
+		imx_inputdev = NULL;
+	}
+}
+
+late_initcall(imx_adc_ts_init);
+module_exit(imx_adc_ts_exit);
+
+MODULE_DESCRIPTION("i.MX ADC input touchscreen driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/mxc_ts.c b/drivers/input/touchscreen/mxc_ts.c
new file mode 100644
index 000000000000..0783188e8376
--- /dev/null
+++ b/drivers/input/touchscreen/mxc_ts.c
@@ -0,0 +1,189 @@
+/*
+ * Freescale touchscreen driver
+ *
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+/*!
+ * @file mxc_ts.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC touchscreen with calibration support.
+ *
+ * The touchscreen driver is designed as a standard input driver which is a
+ * wrapper over low level PMIC driver. Most of the hardware configuration and
+ * touchscreen functionality is implemented in the low level PMIC driver. During
+ * initialization, this driver creates a kernel thread. This thread then calls
+ * PMIC driver to obtain touchscreen values continously. These values are then
+ * passed to the input susbsystem.
+ *
+ * @ingroup touchscreen
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/freezer.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_adc.h>
+#include <linux/kthread.h>
+
+#define MXC_TS_NAME	"mxc_ts"
+
+static struct input_dev *mxc_inputdev;
+static struct task_struct *tstask;
+/**
+ * calibration array refers to
+ * (delta_x[0], delta_x[1], delta_x[2], delta_y[0], delta_y[1], delta_y[2], delta).
+ * Which generated by calibration service.
+ * In this driver when we got touch pointer (x', y') from PMIC ADC,
+ * we calculate the display pointer (x,y) by:
+ * x = (delta_x[0] * x' + delta_x[1] * y' + delta_x[2]) / delta;
+ * y = (delta_y[0] * x' + delta_y[1] * y' + delta_y[2]) / delta;
+ */
+static int calibration[7];
+module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR);
+
+static int ts_thread(void *arg)
+{
+	t_touch_screen ts_sample;
+	s32 wait = 0;
+
+	do {
+		int x, y;
+		static int last_x = -1, last_y = -1, last_press = -1;
+
+		memset(&ts_sample, 0, sizeof(t_touch_screen));
+		if (0 != pmic_adc_get_touch_sample(&ts_sample, !wait))
+			continue;
+		if (!(ts_sample.contact_resistance || wait))
+			continue;
+
+		if (ts_sample.x_position == 0 && ts_sample.y_position == 0 &&
+			ts_sample.contact_resistance == 0) {
+			x = last_x;
+			y = last_y;
+		} else if (calibration[6] == 0) {
+			x = ts_sample.x_position;
+			y = ts_sample.y_position;
+		} else {
+			x = calibration[0] * (int)ts_sample.x_position +
+				calibration[1] * (int)ts_sample.y_position +
+				calibration[2];
+			x /= calibration[6];
+			if (x < 0)
+				x = 0;
+			y = calibration[3] * (int)ts_sample.x_position +
+				calibration[4] * (int)ts_sample.y_position +
+				calibration[5];
+			y /= calibration[6];
+			if (y < 0)
+				y = 0;
+		}
+
+		if (x != last_x) {
+			input_report_abs(mxc_inputdev, ABS_X, x);
+			last_x = x;
+		}
+		if (y != last_y) {
+			input_report_abs(mxc_inputdev, ABS_Y, y);
+			last_y = y;
+		}
+
+		/* report pressure */
+		input_report_abs(mxc_inputdev, ABS_PRESSURE,
+				 ts_sample.contact_resistance);
+#ifdef CONFIG_MXC_PMIC_MC13892
+		/* workaround for aplite ADC resistance large range value */
+		if (ts_sample.contact_resistance > 22)
+			ts_sample.contact_resistance = 1;
+		else
+			ts_sample.contact_resistance = 0;
+#endif
+		/* report the BTN_TOUCH */
+		if (ts_sample.contact_resistance != last_press)
+			input_event(mxc_inputdev, EV_KEY,
+					BTN_TOUCH, ts_sample.contact_resistance);
+
+		input_sync(mxc_inputdev);
+		last_press = ts_sample.contact_resistance;
+
+		wait = ts_sample.contact_resistance;
+		msleep(20);
+
+	} while (!kthread_should_stop());
+
+	return 0;
+}
+
+static int __init mxc_ts_init(void)
+{
+	int retval;
+
+	if (!is_pmic_adc_ready())
+		return -ENODEV;
+
+	mxc_inputdev = input_allocate_device();
+	if (!mxc_inputdev) {
+		printk(KERN_ERR
+		       "mxc_ts_init: not enough memory\n");
+		return -ENOMEM;
+	}
+
+	mxc_inputdev->name = MXC_TS_NAME;
+	mxc_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	mxc_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH);
+	mxc_inputdev->absbit[0] =
+	    BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE);
+	retval = input_register_device(mxc_inputdev);
+	if (retval < 0) {
+		input_free_device(mxc_inputdev);
+		return retval;
+	}
+
+	tstask = kthread_run(ts_thread, NULL, "mxc_ts");
+	if (IS_ERR(tstask)) {
+		printk(KERN_ERR
+			"mxc_ts_init: failed to create kthread");
+		tstask = NULL;
+		return -1;
+	}
+	printk("mxc input touchscreen loaded\n");
+	return 0;
+}
+
+static void __exit mxc_ts_exit(void)
+{
+	if (tstask)
+		kthread_stop(tstask);
+
+	input_unregister_device(mxc_inputdev);
+
+	if (mxc_inputdev) {
+		input_free_device(mxc_inputdev);
+		mxc_inputdev = NULL;
+	}
+}
+
+late_initcall(mxc_ts_init);
+module_exit(mxc_ts_exit);
+
+MODULE_DESCRIPTION("MXC touchscreen driver with calibration");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/mxs-ts.c b/drivers/input/touchscreen/mxs-ts.c
new file mode 100644
index 000000000000..a2ea102290a8
--- /dev/null
+++ b/drivers/input/touchscreen/mxs-ts.c
@@ -0,0 +1,462 @@
+/*
+ * Freesclae MXS Touchscreen driver
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+
+#include <mach/lradc.h>
+#include <mach/hardware.h>
+#include <mach/device.h>
+#include <mach/regs-lradc.h>
+
+#define TOUCH_DEBOUNCE_TOLERANCE	100
+
+struct mxs_ts_info {
+	int touch_irq;
+	int device_irq;
+	unsigned int base;
+	u8 x_plus_chan;
+	u8 x_minus_chan;
+	u8 y_plus_chan;
+	u8 y_minus_chan;
+
+	unsigned int x_plus_val;
+	unsigned int x_minus_val;
+	unsigned int y_plus_val;
+	unsigned int y_minus_val;
+	unsigned int x_plus_mask;
+	unsigned int x_minus_mask;
+	unsigned int y_plus_mask;
+	unsigned int y_minus_mask;
+
+	struct input_dev *idev;
+	enum {
+		TS_STATE_DISABLED,
+		TS_STATE_TOUCH_DETECT,
+		TS_STATE_TOUCH_VERIFY,
+		TS_STATE_X_PLANE,
+		TS_STATE_Y_PLANE,
+	} state;
+	u16 x;
+	u16 y;
+	int sample_count;
+};
+
+static inline void enter_state_touch_detect(struct mxs_ts_info *info)
+{
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->x_plus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->y_plus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->x_minus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->y_minus_chan));
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan,
+		     info->base + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+		     info->base + HW_LRADC_CTRL1_CLR);
+	/*
+	 * turn off the yplus and yminus pullup and pulldown, and turn off touch
+	 * detect (enables yminus, and xplus through a resistor.On a press,
+	 * xplus is pulled down)
+	 */
+	__raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		     info->base + HW_LRADC_CTRL0_SET);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0);
+	info->state = TS_STATE_TOUCH_DETECT;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_disabled(struct mxs_ts_info *info)
+{
+	__raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		     info->base + HW_LRADC_CTRL0_CLR);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0);
+	info->state = TS_STATE_DISABLED;
+	info->sample_count = 0;
+}
+
+
+static inline void enter_state_x_plane(struct mxs_ts_info *info)
+{
+	__raw_writel(info->y_plus_val, info->base + HW_LRADC_CTRL0_SET);
+	__raw_writel(info->y_minus_val, info->base + HW_LRADC_CTRL0_SET);
+	__raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		     info->base + HW_LRADC_CTRL0_CLR);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+
+	info->state = TS_STATE_X_PLANE;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_y_plane(struct mxs_ts_info *info)
+{
+	__raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_plus_val, info->base + HW_LRADC_CTRL0_SET);
+	__raw_writel(info->x_minus_val, info->base + HW_LRADC_CTRL0_SET);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		     info->base + HW_LRADC_CTRL0_CLR);
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+	info->state = TS_STATE_Y_PLANE;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_touch_verify(struct mxs_ts_info *info)
+{
+	__raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		     info->base + HW_LRADC_CTRL0_SET);
+	info->state = TS_STATE_TOUCH_VERIFY;
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+	info->sample_count = 0;
+}
+
+static void process_lradc(struct mxs_ts_info *info, u16 x, u16 y,
+			int pressure)
+{
+	switch (info->state) {
+	case TS_STATE_X_PLANE:
+		pr_debug("%s: x plane state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (info->sample_count < 2) {
+			info->x = x;
+			info->sample_count++;
+		} else {
+			if (abs(info->x - x) > TOUCH_DEBOUNCE_TOLERANCE)
+				info->sample_count = 1;
+			else {
+				u16 x_c = info->x * (info->sample_count - 1);
+				info->x = (x_c + x) / info->sample_count;
+				info->sample_count++;
+			}
+		}
+		if (info->sample_count > 4)
+			enter_state_y_plane(info);
+		else
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		break;
+
+	case TS_STATE_Y_PLANE:
+		pr_debug("%s: y plane state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (info->sample_count < 2) {
+			info->y = y;
+			info->sample_count++;
+		} else {
+			if (abs(info->y - y) > TOUCH_DEBOUNCE_TOLERANCE)
+				info->sample_count = 1;
+			else {
+				u16 y_c = info->y * (info->sample_count - 1);
+				info->y = (y_c + y) / info->sample_count;
+				info->sample_count++;
+			}
+		}
+		if (info->sample_count > 4)
+			enter_state_touch_verify(info);
+		else
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		break;
+
+	case TS_STATE_TOUCH_VERIFY:
+		pr_debug("%s: touch verify state, sample_count %d\n", __func__,
+				info->sample_count);
+		pr_debug("%s: x %d, y %d\n", __func__, info->x, info->y);
+		input_report_abs(info->idev, ABS_X, info->x);
+		input_report_abs(info->idev, ABS_Y, info->y);
+		input_report_abs(info->idev, ABS_PRESSURE, pressure);
+		input_sync(info->idev);
+		/* fall through */
+	case TS_STATE_TOUCH_DETECT:
+		pr_debug("%s: touch detect state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (pressure) {
+			input_report_abs(info->idev, ABS_PRESSURE, pressure);
+			enter_state_x_plane(info);
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		} else
+			enter_state_touch_detect(info);
+		break;
+
+	default:
+		printk(KERN_ERR "%s: unknown touchscreen state %d\n", __func__,
+				info->state);
+	}
+}
+
+static irqreturn_t ts_handler(int irq, void *dev_id)
+{
+	struct mxs_ts_info *info = dev_id;
+	u16 x_plus, y_plus;
+	int pressure = 0;
+
+	if (irq == info->touch_irq)
+		__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+			     info->base + HW_LRADC_CTRL1_CLR);
+	else if (irq == info->device_irq)
+		__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan,
+			     info->base + HW_LRADC_CTRL1_CLR);
+
+	/* get x, y values */
+	x_plus = __raw_readl(info->base + HW_LRADC_CHn(info->x_plus_chan)) &
+		BM_LRADC_CHn_VALUE;
+	y_plus = __raw_readl(info->base + HW_LRADC_CHn(info->y_plus_chan)) &
+		BM_LRADC_CHn_VALUE;
+
+	/* pressed? */
+	if (__raw_readl(info->base + HW_LRADC_STATUS) &
+	    BM_LRADC_STATUS_TOUCH_DETECT_RAW)
+		pressure = 1;
+
+	pr_debug("%s: irq %d, x_plus %d, y_plus %d, pressure %d\n",
+			__func__, irq, x_plus, y_plus, pressure);
+
+	process_lradc(info, x_plus, y_plus, pressure);
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit mxs_ts_probe(struct platform_device *pdev)
+{
+	struct input_dev *idev;
+	struct mxs_ts_info *info;
+	int ret = 0;
+	struct resource *res;
+	struct mxs_touchscreen_plat_data *plat_data;
+
+	plat_data = (struct mxs_touchscreen_plat_data *)pdev->dev.platform_data;
+	if (plat_data == NULL)
+		return -ENODEV;
+
+	idev = input_allocate_device();
+	if (idev == NULL)
+		return -ENOMEM;
+
+	info = kzalloc(sizeof(struct mxs_ts_info), GFP_KERNEL);
+	if (info == NULL) {
+		ret = -ENOMEM;
+		goto out_nomem_info;
+	}
+
+	idev->name = "MXS touchscreen";
+	idev->evbit[0] = BIT(EV_ABS);
+	input_set_abs_params(idev, ABS_X, 0, 0xFFF, 0, 0);
+	input_set_abs_params(idev, ABS_Y, 0, 0xFFF, 0, 0);
+	input_set_abs_params(idev, ABS_PRESSURE, 0, 1, 0, 0);
+
+	ret = input_register_device(idev);
+	if (ret)
+		goto out_nomem;
+
+	info->idev = idev;
+	info->x_plus_chan = plat_data->x_plus_chan;
+	info->x_minus_chan = plat_data->x_minus_chan;
+	info->y_plus_chan = plat_data->y_plus_chan;
+	info->y_minus_chan = plat_data->y_minus_chan;
+	info->x_plus_val = plat_data->x_plus_val;
+	info->x_minus_val = plat_data->x_minus_val;
+	info->y_plus_val = plat_data->y_plus_val;
+	info->y_minus_val = plat_data->y_minus_val;
+	info->x_plus_mask = plat_data->x_plus_mask;
+	info->x_minus_mask = plat_data->x_minus_mask;
+	info->y_plus_mask = plat_data->y_plus_mask;
+	info->y_minus_mask = plat_data->y_minus_mask;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "%s: couldn't get MEM resource\n", __func__);
+		ret = -ENODEV;
+		goto out_nodev;
+	}
+	info->base = (unsigned int)IO_ADDRESS(res->start);
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__);
+		ret = -ENODEV;
+		goto out_nodev;
+	}
+	info->touch_irq = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!res) {
+		printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__);
+		ret = -ENODEV;
+		goto out_nodev;
+	}
+	info->device_irq = res->start;
+
+	ret = request_irq(info->touch_irq, ts_handler, IRQF_DISABLED,
+				"mxs_ts_touch", info);
+	if (ret)
+		goto out_nodev;
+
+	ret = request_irq(info->device_irq, ts_handler, IRQF_DISABLED,
+				"mxs_ts_dev", info);
+	if (ret) {
+		free_irq(info->touch_irq, info);
+		goto out_nodev;
+	}
+	enter_state_touch_detect(info);
+
+	hw_lradc_use_channel(info->x_plus_chan);
+	hw_lradc_use_channel(info->x_minus_chan);
+	hw_lradc_use_channel(info->y_plus_chan);
+	hw_lradc_use_channel(info->y_minus_chan);
+	hw_lradc_configure_channel(info->x_plus_chan, 0, 0, 0);
+	hw_lradc_configure_channel(info->x_minus_chan, 0, 0, 0);
+	hw_lradc_configure_channel(info->y_plus_chan, 0, 0, 0);
+	hw_lradc_configure_channel(info->y_minus_chan, 0, 0, 0);
+
+	/* Clear the accumulator & NUM_SAMPLES for the channels */
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->x_plus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->x_minus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->y_plus_chan));
+	__raw_writel(0xFFFFFFFF,
+		     info->base + HW_LRADC_CHn_CLR(info->y_minus_chan));
+
+	hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_TOUCHSCREEN,
+			0x3c, 0, 0, 8);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan,
+		     info->base + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+		     info->base + HW_LRADC_CTRL1_CLR);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << info->y_minus_chan,
+		     info->base + HW_LRADC_CTRL1_SET);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
+		     info->base + HW_LRADC_CTRL1_SET);
+
+	platform_set_drvdata(pdev, info);
+	device_init_wakeup(&pdev->dev, 1);
+	goto out;
+
+out_nodev:
+	input_free_device(idev);
+out_nomem:
+	kfree(info);
+out_nomem_info:
+	kfree(idev);
+out:
+	return ret;
+}
+
+static int __devexit mxs_ts_remove(struct platform_device *pdev)
+{
+	struct mxs_ts_info *info = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	hw_lradc_unuse_channel(info->x_plus_chan);
+	hw_lradc_unuse_channel(info->x_minus_chan);
+	hw_lradc_unuse_channel(info->y_plus_chan);
+	hw_lradc_unuse_channel(info->y_minus_chan);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << info->y_minus_chan,
+		     info->base + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
+		     info->base + HW_LRADC_CTRL1_CLR);
+
+	free_irq(info->device_irq, info);
+	free_irq(info->touch_irq, info);
+	input_free_device(info->idev);
+
+	enter_state_disabled(info);
+	kfree(info->idev);
+	kfree(info);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_ts_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+	struct mxs_ts_info *info = platform_get_drvdata(pdev);
+
+	if (!device_may_wakeup(&pdev->dev)) {
+		hw_lradc_unuse_channel(info->x_plus_chan);
+		hw_lradc_unuse_channel(info->x_minus_chan);
+		hw_lradc_unuse_channel(info->y_plus_chan);
+		hw_lradc_unuse_channel(info->y_minus_chan);
+	}
+	return 0;
+}
+
+static int mxs_ts_resume(struct platform_device *pdev)
+{
+	struct mxs_ts_info *info = platform_get_drvdata(pdev);
+
+	if (!device_may_wakeup(&pdev->dev)) {
+		hw_lradc_use_channel(info->x_plus_chan);
+		hw_lradc_use_channel(info->x_minus_chan);
+		hw_lradc_use_channel(info->y_plus_chan);
+		hw_lradc_use_channel(info->y_minus_chan);
+	}
+	return 0;
+}
+#endif
+
+static struct platform_driver mxs_ts_driver = {
+	.probe		= mxs_ts_probe,
+	.remove		= __devexit_p(mxs_ts_remove),
+#ifdef CONFIG_PM
+	.suspend	= mxs_ts_suspend,
+	.resume		= mxs_ts_resume,
+#endif
+	.driver		= {
+		.name	= "mxs-ts",
+	},
+};
+
+static int __init mxs_ts_init(void)
+{
+	return platform_driver_register(&mxs_ts_driver);
+}
+
+static void __exit mxs_ts_exit(void)
+{
+	platform_driver_unregister(&mxs_ts_driver);
+}
+
+module_init(mxs_ts_init);
+module_exit(mxs_ts_exit);
diff --git a/drivers/input/touchscreen/stmp3xxx_ts.c b/drivers/input/touchscreen/stmp3xxx_ts.c
new file mode 100644
index 000000000000..4e6ab20ea780
--- /dev/null
+++ b/drivers/input/touchscreen/stmp3xxx_ts.c
@@ -0,0 +1,422 @@
+/*
+ * Freesclae STMP37XX/STMP378X Touchscreen driver
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG*/
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+
+#include <mach/lradc.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <mach/regs-lradc.h>
+
+#define TOUCH_DEBOUNCE_TOLERANCE	100
+
+struct stmp3xxx_ts_info {
+	int touch_irq;
+	int device_irq;
+	struct input_dev *idev;
+	enum {
+		TS_STATE_DISABLED,
+		TS_STATE_TOUCH_DETECT,
+		TS_STATE_TOUCH_VERIFY,
+		TS_STATE_X_PLANE,
+		TS_STATE_Y_PLANE,
+	} state;
+	u16 x;
+	u16 y;
+	int sample_count;
+};
+
+static inline void enter_state_touch_detect(struct stmp3xxx_ts_info *info)
+{
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(2));
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(3));
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(4));
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(5));
+	__raw_writel(BM_LRADC_CTRL1_LRADC5_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	/*
+	 * turn off the yplus and yminus pullup and pulldown, and turn off touch
+	 * detect (enables yminus, and xplus through a resistor.On a press,
+	 * xplus is pulled down)
+	 */
+	__raw_writel(BM_LRADC_CTRL0_YMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_YPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0);
+	info->state = TS_STATE_TOUCH_DETECT;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_disabled(struct stmp3xxx_ts_info *info)
+{
+	__raw_writel(BM_LRADC_CTRL0_YMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_YPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0);
+	info->state = TS_STATE_DISABLED;
+	info->sample_count = 0;
+}
+
+
+static inline void enter_state_x_plane(struct stmp3xxx_ts_info *info)
+{
+	__raw_writel(BM_LRADC_CTRL0_YMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	__raw_writel(BM_LRADC_CTRL0_YPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	__raw_writel(BM_LRADC_CTRL0_XMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+
+	info->state = TS_STATE_X_PLANE;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_y_plane(struct stmp3xxx_ts_info *info)
+{
+	__raw_writel(BM_LRADC_CTRL0_YMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_YPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	__raw_writel(BM_LRADC_CTRL0_XPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+	info->state = TS_STATE_Y_PLANE;
+	info->sample_count = 0;
+}
+
+static inline void enter_state_touch_verify(struct stmp3xxx_ts_info *info)
+{
+	__raw_writel(BM_LRADC_CTRL0_YMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_YPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XMINUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_XPLUS_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR);
+	__raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE,
+		REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+
+	info->state = TS_STATE_TOUCH_VERIFY;
+	hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+	info->sample_count = 0;
+}
+
+static void process_lradc(struct stmp3xxx_ts_info *info, u16 x, u16 y,
+			int pressure)
+{
+	switch (info->state) {
+	case TS_STATE_X_PLANE:
+		pr_debug("%s: x plane state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (info->sample_count < 2) {
+			info->x = x;
+			info->sample_count++;
+		} else {
+			if (abs(info->x - x) > TOUCH_DEBOUNCE_TOLERANCE)
+				info->sample_count = 1;
+			else {
+				u16 x_c = info->x * (info->sample_count - 1);
+				info->x = (x_c + x) / info->sample_count;
+				info->sample_count++;
+			}
+		}
+		if (info->sample_count > 4)
+			enter_state_y_plane(info);
+		else
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		break;
+
+	case TS_STATE_Y_PLANE:
+		pr_debug("%s: y plane state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (info->sample_count < 2) {
+			info->y = y;
+			info->sample_count++;
+		} else {
+			if (abs(info->y - y) > TOUCH_DEBOUNCE_TOLERANCE)
+				info->sample_count = 1;
+			else {
+				u16 y_c = info->y * (info->sample_count - 1);
+				info->y = (y_c + y) / info->sample_count;
+				info->sample_count++;
+			}
+		}
+		if (info->sample_count > 4)
+			enter_state_touch_verify(info);
+		else
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		break;
+
+	case TS_STATE_TOUCH_VERIFY:
+		pr_debug("%s: touch verify state, sample_count %d\n", __func__,
+				info->sample_count);
+		pr_debug("%s: x %d, y %d\n", __func__, info->x, info->y);
+		input_report_abs(info->idev, ABS_X, info->x);
+		input_report_abs(info->idev, ABS_Y, info->y);
+		input_report_abs(info->idev, ABS_PRESSURE, pressure);
+		input_sync(info->idev);
+		/* fall through */
+	case TS_STATE_TOUCH_DETECT:
+		pr_debug("%s: touch detect state, sample_count %d\n", __func__,
+				info->sample_count);
+		if (pressure) {
+			input_report_abs(info->idev, ABS_PRESSURE, pressure);
+			enter_state_x_plane(info);
+			hw_lradc_set_delay_trigger_kick(
+					LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1);
+		} else
+			enter_state_touch_detect(info);
+		break;
+
+	default:
+		printk(KERN_ERR "%s: unknown touchscreen state %d\n", __func__,
+				info->state);
+	}
+}
+
+static irqreturn_t ts_handler(int irq, void *dev_id)
+{
+	struct stmp3xxx_ts_info *info = dev_id;
+	u16 x_plus, y_plus;
+	int pressure = 0;
+
+	if (irq == info->touch_irq)
+		__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	else if (irq == info->device_irq)
+		__raw_writel(BM_LRADC_CTRL1_LRADC5_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+	/* get x, y values */
+	x_plus = __raw_readl(REGS_LRADC_BASE + HW_LRADC_CHn(LRADC_TOUCH_X_PLUS)) & BM_LRADC_CHn_VALUE;
+	y_plus = __raw_readl(REGS_LRADC_BASE + HW_LRADC_CHn(LRADC_TOUCH_Y_PLUS)) & BM_LRADC_CHn_VALUE;
+
+	/* pressed? */
+	if (__raw_readl(REGS_LRADC_BASE + HW_LRADC_STATUS) & BM_LRADC_STATUS_TOUCH_DETECT_RAW)
+		pressure = 1;
+
+	pr_debug("%s: irq %d, x_plus %d, y_plus %d, pressure %d\n",
+			__func__, irq, x_plus, y_plus, pressure);
+
+	process_lradc(info, x_plus, y_plus, pressure);
+
+	return IRQ_HANDLED;
+}
+
+static int stmp3xxx_ts_probe(struct platform_device *pdev)
+{
+	struct input_dev *idev;
+	struct stmp3xxx_ts_info *info;
+	int ret = 0;
+	struct resource *res;
+
+	idev = input_allocate_device();
+	info = kzalloc(sizeof(struct stmp3xxx_ts_info), GFP_KERNEL);
+	if (idev == NULL || info == NULL) {
+		ret = -ENOMEM;
+		goto out_nomem;
+	}
+
+	idev->name = "STMP3XXX touchscreen";
+	idev->evbit[0] = BIT(EV_ABS);
+	input_set_abs_params(idev, ABS_X, 0, 0xFFF, 0, 0);
+	input_set_abs_params(idev, ABS_Y, 0, 0xFFF, 0, 0);
+	input_set_abs_params(idev, ABS_PRESSURE, 0, 1, 0, 0);
+
+	ret = input_register_device(idev);
+	if (ret)
+		goto out_nomem;
+
+	info->idev = idev;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__);
+		ret = -ENODEV;
+		goto out_nodev;
+	}
+	info->touch_irq = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!res) {
+		printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__);
+		ret = -ENODEV;
+		goto out_nodev;
+	}
+	info->device_irq = res->start;
+
+	ret = request_irq(info->touch_irq, ts_handler, IRQF_DISABLED,
+				"stmp3xxx_ts_touch", info);
+	if (ret)
+		goto out_nodev;
+
+	ret = request_irq(info->device_irq, ts_handler, IRQF_DISABLED,
+				"stmp3xxx_ts_dev", info);
+	if (ret) {
+		free_irq(info->touch_irq, info);
+		goto out_nodev;
+	}
+	enter_state_touch_detect(info);
+
+	hw_lradc_use_channel(LRADC_CH2);
+	hw_lradc_use_channel(LRADC_CH3);
+	hw_lradc_use_channel(LRADC_CH5);
+	hw_lradc_configure_channel(LRADC_CH2, 0, 0, 0);
+	hw_lradc_configure_channel(LRADC_CH3, 0, 0, 0);
+	hw_lradc_configure_channel(LRADC_CH5, 0, 0, 0);
+
+	/* Clear the accumulator & NUM_SAMPLES for the channels */
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(LRADC_CH2));
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(LRADC_CH3));
+	__raw_writel(0xFFFFFFFF, REGS_LRADC_BASE + HW_LRADC_CHn_CLR(LRADC_CH5));
+
+	hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_TOUCHSCREEN,
+			0x3c, 0, 0, 8);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC5_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+	__raw_writel(BM_LRADC_CTRL1_LRADC5_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_SET);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_SET);
+
+	platform_set_drvdata(pdev, info);
+	device_init_wakeup(&pdev->dev, 1);
+	goto out;
+
+out_nodev:
+	input_free_device(idev);
+out_nomem:
+	kfree(idev);
+	kfree(info);
+out:
+	return ret;
+}
+
+static int stmp3xxx_ts_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_ts_info *info = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	hw_lradc_unuse_channel(LRADC_CH2);
+	hw_lradc_unuse_channel(LRADC_CH3);
+	hw_lradc_unuse_channel(LRADC_CH5);
+	__raw_writel(BM_LRADC_CTRL1_LRADC5_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
+		REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+	free_irq(info->device_irq, info);
+	free_irq(info->touch_irq, info);
+	input_free_device(info->idev);
+
+	enter_state_disabled(info);
+	kfree(info->idev);
+	kfree(info);
+	return 0;
+}
+
+static int stmp3xxx_ts_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+#ifdef CONFIG_PM
+	if (!device_may_wakeup(&pdev->dev)) {
+		hw_lradc_unuse_channel(LRADC_CH2);
+		hw_lradc_unuse_channel(LRADC_CH3);
+		hw_lradc_unuse_channel(LRADC_CH5);
+	}
+#endif
+	return 0;
+}
+
+static int stmp3xxx_ts_resume(struct platform_device *pdev)
+{
+#ifdef CONFIG_PM
+	if (!device_may_wakeup(&pdev->dev)) {
+		hw_lradc_use_channel(LRADC_CH2);
+		hw_lradc_use_channel(LRADC_CH3);
+		hw_lradc_use_channel(LRADC_CH5);
+	}
+#endif
+	return 0;
+}
+
+static struct platform_driver stmp3xxx_ts_driver = {
+	.probe		= stmp3xxx_ts_probe,
+	.remove		= stmp3xxx_ts_remove,
+	.suspend	= stmp3xxx_ts_suspend,
+	.resume		= stmp3xxx_ts_resume,
+	.driver		= {
+		.name		= "stmp3xxx_ts",
+	},
+};
+
+static int __init stmp3xxx_ts_init(void)
+{
+	return platform_driver_register(&stmp3xxx_ts_driver);
+}
+
+static void __exit stmp3xxx_ts_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_ts_driver);
+}
+
+module_init(stmp3xxx_ts_init);
+module_exit(stmp3xxx_ts_exit);
diff --git a/drivers/input/touchscreen/tsc2007.c b/drivers/input/touchscreen/tsc2007.c
index 880f58c6a7c4..fd5a503ffb93 100644
--- a/drivers/input/touchscreen/tsc2007.c
+++ b/drivers/input/touchscreen/tsc2007.c
@@ -21,15 +21,13 @@
  */
 
 #include <linux/module.h>
-#include <linux/hrtimer.h>
 #include <linux/slab.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
 
-#define TS_POLL_DELAY	(10 * 1000)	/* ns delay before the first sample */
-#define TS_POLL_PERIOD	(5 * 1000)	/* ns delay between samples */
+#define TS_POLL_PERIOD	msecs_to_jiffies(1) /* ms delay between samples */
 
 #define TSC2007_MEASURE_TEMP0		(0x0 << 4)
 #define TSC2007_MEASURE_AUX		(0x2 << 4)
@@ -70,13 +68,11 @@ struct ts_event {
 struct tsc2007 {
 	struct input_dev	*input;
 	char			phys[32];
-	struct hrtimer		timer;
+	struct delayed_work	work;
 	struct ts_event		tc;
 
 	struct i2c_client	*client;
 
-	spinlock_t		lock;
-
 	u16			model;
 	u16			x_plate_ohms;
 
@@ -142,8 +138,7 @@ static void tsc2007_send_event(void *tsc)
 	if (rt > MAX_12BIT) {
 		dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
 
-		hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_PERIOD),
-			      HRTIMER_MODE_REL);
+		schedule_delayed_work(&ts->work, TS_POLL_PERIOD);
 		return;
 	}
 
@@ -153,7 +148,7 @@ static void tsc2007_send_event(void *tsc)
 	 * in some cases may not even settle at the expected value.
 	 *
 	 * The only safe way to check for the pen up condition is in the
-	 * timer by reading the pen signal state (it's a GPIO _and_ IRQ).
+	 * work function by reading the pen signal state (it's a GPIO and IRQ).
 	 */
 	if (rt) {
 		struct input_dev *input = ts->input;
@@ -175,8 +170,7 @@ static void tsc2007_send_event(void *tsc)
 			x, y, rt);
 	}
 
-	hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_PERIOD),
-			HRTIMER_MODE_REL);
+	schedule_delayed_work(&ts->work, TS_POLL_PERIOD);
 }
 
 static int tsc2007_read_values(struct tsc2007 *tsc)
@@ -197,13 +191,10 @@ static int tsc2007_read_values(struct tsc2007 *tsc)
 	return 0;
 }
 
-static enum hrtimer_restart tsc2007_timer(struct hrtimer *handle)
+static void tsc2007_work(struct work_struct *work)
 {
-	struct tsc2007 *ts = container_of(handle, struct tsc2007, timer);
-	unsigned long flags;
-
-	spin_lock_irqsave(&ts->lock, flags);
-
+	struct tsc2007 *ts =
+		container_of(to_delayed_work(work), struct tsc2007, work);
 	if (unlikely(!ts->get_pendown_state() && ts->pendown)) {
 		struct input_dev *input = ts->input;
 
@@ -222,30 +213,20 @@ static enum hrtimer_restart tsc2007_timer(struct hrtimer *handle)
 		tsc2007_read_values(ts);
 		tsc2007_send_event(ts);
 	}
-
-	spin_unlock_irqrestore(&ts->lock, flags);
-
-	return HRTIMER_NORESTART;
 }
 
 static irqreturn_t tsc2007_irq(int irq, void *handle)
 {
 	struct tsc2007 *ts = handle;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ts->lock, flags);
 
 	if (likely(ts->get_pendown_state())) {
 		disable_irq_nosync(ts->irq);
-		hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_DELAY),
-					HRTIMER_MODE_REL);
+		schedule_delayed_work(&ts->work, 0);
 	}
 
 	if (ts->clear_penirq)
 		ts->clear_penirq();
 
-	spin_unlock_irqrestore(&ts->lock, flags);
-
 	return IRQ_HANDLED;
 }
 
@@ -278,11 +259,6 @@ static int tsc2007_probe(struct i2c_client *client,
 
 	ts->input = input_dev;
 
-	hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
-	ts->timer.function = tsc2007_timer;
-
-	spin_lock_init(&ts->lock);
-
 	ts->model             = pdata->model;
 	ts->x_plate_ohms      = pdata->x_plate_ohms;
 	ts->get_pendown_state = pdata->get_pendown_state;
@@ -290,6 +266,11 @@ static int tsc2007_probe(struct i2c_client *client,
 
 	pdata->init_platform_hw();
 
+	if (tsc2007_xfer(ts, PWRDOWN) < 0) {
+		err = -ENODEV;
+		goto err_no_dev;
+	}
+
 	snprintf(ts->phys, sizeof(ts->phys),
 		 "%s/input0", dev_name(&client->dev));
 
@@ -308,6 +289,8 @@ static int tsc2007_probe(struct i2c_client *client,
 
 	ts->irq = client->irq;
 
+	INIT_DELAYED_WORK(&ts->work, tsc2007_work);
+
 	err = request_irq(ts->irq, tsc2007_irq, 0,
 			client->dev.driver->name, ts);
 	if (err < 0) {
@@ -325,9 +308,10 @@ static int tsc2007_probe(struct i2c_client *client,
 
  err_free_irq:
 	free_irq(ts->irq, ts);
-	hrtimer_cancel(&ts->timer);
  err_free_mem:
 	input_free_device(input_dev);
+ err_no_dev:
+	pdata->exit_platform_hw();
 	kfree(ts);
 	return err;
 }
@@ -337,11 +321,12 @@ static int tsc2007_remove(struct i2c_client *client)
 	struct tsc2007	*ts = i2c_get_clientdata(client);
 	struct tsc2007_platform_data *pdata;
 
+	cancel_delayed_work_sync(&ts->work);
+
 	pdata = client->dev.platform_data;
 	pdata->exit_platform_hw();
 
 	free_irq(ts->irq, ts);
-	hrtimer_cancel(&ts->timer);
 	input_unregister_device(ts->input);
 	kfree(ts);
 
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 7c8e7122aaa9..9b9f50882377 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -17,6 +17,20 @@ config LEDS_CLASS
 
 comment "LED drivers"
 
+config LEDS_STMP378X
+	tristate "Support for PWM LEDs on STMP378X"
+	depends on LEDS_CLASS && MACH_STMP378X
+	help
+	  This option enables support for the LEDs connected to PWM
+	  outputs on the Freescale STMP378X.
+
+config LEDS_MXS
+	tristate "Support for PWM LEDs on MXS"
+	depends on LEDS_CLASS && ARCH_MXS
+	help
+	  This option enables support for the LEDs connected to PWM
+	  outputs on the Freescale MXS SOC.
+
 config LEDS_ATMEL_PWM
 	tristate "LED Support using Atmel PWM outputs"
 	depends on LEDS_CLASS && ATMEL_PWM
@@ -24,6 +38,10 @@ config LEDS_ATMEL_PWM
 	  This option enables support for LEDs driven using outputs
 	  of the dedicated PWM controller found on newer Atmel SOCs.
 
+config LEDS_MC13892
+	tristate "LED Support for mc13892 pmic"
+	depends on LEDS_CLASS && MXC_MC13892_LIGHT
+
 config LEDS_LOCOMO
 	tristate "LED Support for Locomo device"
 	depends on LEDS_CLASS && SHARP_LOCOMO
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index e8cdcf77a4c3..46a0f9a90f50 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_LEDS_TRIGGERS)		+= led-triggers.o
 # LED Platform Drivers
 obj-$(CONFIG_LEDS_ATMEL_PWM)		+= leds-atmel-pwm.o
 obj-$(CONFIG_LEDS_BD2802)		+= leds-bd2802.o
+obj-$(CONFIG_LEDS_MC13892)		+= leds-mc13892.o
+obj-$(CONFIG_LEDS_STMP378X)		+= leds-stmp378x-pwm.o
 obj-$(CONFIG_LEDS_LOCOMO)		+= leds-locomo.o
 obj-$(CONFIG_LEDS_MIKROTIK_RB532)	+= leds-rb532.o
 obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
@@ -28,6 +30,7 @@ obj-$(CONFIG_LEDS_PCA955X)		+= leds-pca955x.o
 obj-$(CONFIG_LEDS_DA903X)		+= leds-da903x.o
 obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
 obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
+obj-$(CONFIG_LEDS_MXS)			+= leds-mxs-pwm.o
 
 # LED SPI Drivers
 obj-$(CONFIG_LEDS_DAC124S085)		+= leds-dac124s085.o
diff --git a/drivers/leds/leds-mc13892.c b/drivers/leds/leds-mc13892.c
new file mode 100644
index 000000000000..9edd20446235
--- /dev/null
+++ b/drivers/leds/leds-mc13892.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/pmic_light.h>
+
+static void mc13892_led_set(struct led_classdev *led_cdev,
+			    enum led_brightness value)
+{
+	struct platform_device *dev = to_platform_device(led_cdev->dev->parent);
+	int led_ch;
+
+	switch (dev->id) {
+	case 'r':
+		led_ch = LIT_RED;
+		break;
+	case 'g':
+		led_ch = LIT_GREEN;
+		break;
+	case 'b':
+		led_ch = LIT_BLUE;
+		break;
+	default:
+		return;
+	}
+
+	/* set current with medium value, in case current is too large */
+	mc13892_bklit_set_current(led_ch, LIT_CURR_12);
+	/* max duty cycle is 63, brightness needs to be divided by 4 */
+	mc13892_bklit_set_dutycycle(led_ch, value / 4);
+
+}
+
+static int mc13892_led_remove(struct platform_device *dev)
+{
+	struct led_classdev *led_cdev = platform_get_drvdata(dev);
+
+	led_classdev_unregister(led_cdev);
+	kfree(led_cdev->name);
+	kfree(led_cdev);
+
+	return 0;
+}
+
+#define LED_NAME_LEN	16
+
+static int mc13892_led_probe(struct platform_device *dev)
+{
+	int ret;
+	struct led_classdev *led_cdev;
+	char *name;
+
+	led_cdev = kzalloc(sizeof(struct led_classdev), GFP_KERNEL);
+	if (led_cdev == NULL) {
+		dev_err(&dev->dev, "No memory for device\n");
+		return -ENOMEM;
+	}
+	name = kzalloc(LED_NAME_LEN, GFP_KERNEL);
+	if (name == NULL) {
+		dev_err(&dev->dev, "No memory for device\n");
+		ret = -ENOMEM;
+		goto exit_err;
+	}
+
+	strcpy(name, dev->name);
+	ret = strlen(dev->name);
+	if (ret > LED_NAME_LEN - 2) {
+		dev_err(&dev->dev, "led name is too long\n");
+		goto exit_err1;
+	}
+	name[ret] = dev->id;
+	name[ret + 1] = '\0';
+	led_cdev->name = name;
+	led_cdev->brightness_set = mc13892_led_set;
+
+	ret = led_classdev_register(&dev->dev, led_cdev);
+	if (ret < 0) {
+		dev_err(&dev->dev, "led_classdev_register failed\n");
+		goto exit_err1;
+	}
+
+	platform_set_drvdata(dev, led_cdev);
+
+	return 0;
+      exit_err1:
+	kfree(led_cdev->name);
+      exit_err:
+	kfree(led_cdev);
+	return ret;
+}
+
+#ifdef CONFIG_PM
+static int mc13892_led_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct led_classdev *led_cdev = platform_get_drvdata(dev);
+
+	led_classdev_suspend(led_cdev);
+	return 0;
+}
+
+static int mc13892_led_resume(struct platform_device *dev)
+{
+	struct led_classdev *led_cdev = platform_get_drvdata(dev);
+
+	led_classdev_resume(led_cdev);
+	return 0;
+}
+#else
+#define mc13892_led_suspend NULL
+#define mc13892_led_resume NULL
+#endif
+
+static struct platform_driver mc13892_led_driver = {
+	.probe = mc13892_led_probe,
+	.remove = mc13892_led_remove,
+	.suspend = mc13892_led_suspend,
+	.resume = mc13892_led_resume,
+	.driver = {
+		   .name = "pmic_leds",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init mc13892_led_init(void)
+{
+	return platform_driver_register(&mc13892_led_driver);
+}
+
+static void __exit mc13892_led_exit(void)
+{
+	platform_driver_unregister(&mc13892_led_driver);
+}
+
+module_init(mc13892_led_init);
+module_exit(mc13892_led_exit);
+
+MODULE_DESCRIPTION("Led driver for PMIC mc13892");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/leds/leds-mxs-pwm.c b/drivers/leds/leds-mxs-pwm.c
new file mode 100644
index 000000000000..a546900a44d0
--- /dev/null
+++ b/drivers/leds/leds-mxs-pwm.c
@@ -0,0 +1,217 @@
+/*
+ * Freescale MXS PWM LED driver
+ *
+ * Author: Drew Benedetti <drewb@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/hardware.h>
+#include <mach/system.h>
+#include <mach/device.h>
+#include <mach/regs-pwm.h>
+
+
+/*
+ * PWM enables are the lowest bits of HW_PWM_CTRL register
+ */
+#define BM_PWM_CTRL_PWM_ENABLE	((1<<(CONFIG_MXS_PWM_CHANNELS)) - 1)
+#define BF_PWM_CTRL_PWM_ENABLE(n) ((1<<(n)) & BM_PWM_CTRL_PWM_ENABLE)
+
+#define BF_PWM_PERIODn_SETTINGS					\
+		(BF_PWM_PERIODn_CDIV(5) | /* divide by 64 */ 	\
+		BF_PWM_PERIODn_INACTIVE_STATE(3) | /* low */ 	\
+		BF_PWM_PERIODn_ACTIVE_STATE(2) | /* high */ 	\
+		BF_PWM_PERIODn_PERIOD(LED_FULL)) /* 255 cycles */
+
+struct mxs_pwm_leds {
+	struct clk *pwm_clk;
+	unsigned int base;
+	unsigned int led_num;
+	struct mxs_pwm_led *leds;
+};
+
+static struct mxs_pwm_leds leds;
+
+static void mxs_pwm_led_brightness_set(struct led_classdev *pled,
+					    enum led_brightness value)
+{
+	struct mxs_pwm_led *pwm_led;
+
+	pwm_led = container_of(pled, struct mxs_pwm_led, dev);
+
+	if (pwm_led->pwm < CONFIG_MXS_PWM_CHANNELS) {
+		__raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm_led->pwm),
+			     leds.base + HW_PWM_CTRL_CLR);
+		__raw_writel(BF_PWM_ACTIVEn_INACTIVE(LED_FULL) |
+				BF_PWM_ACTIVEn_ACTIVE(value),
+			     leds.base + HW_PWM_ACTIVEn(pwm_led->pwm));
+		__raw_writel(BF_PWM_PERIODn_SETTINGS,
+			     leds.base + HW_PWM_PERIODn(pwm_led->pwm));
+		__raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm_led->pwm),
+			     leds.base + HW_PWM_CTRL_SET);
+	}
+}
+
+static int __devinit mxs_pwm_led_probe(struct platform_device *pdev)
+{
+	struct mxs_pwm_leds_plat_data *plat_data;
+	struct resource *res;
+	struct led_classdev *led;
+	unsigned int pwmn;
+	int leds_in_use = 0, rc = 0;
+	int i;
+
+	plat_data = (struct mxs_pwm_leds_plat_data *)pdev->dev.platform_data;
+	if (plat_data == NULL)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL)
+		return -ENODEV;
+	leds.base = (unsigned int)IO_ADDRESS(res->start);
+
+	mxs_reset_block((void __iomem *)leds.base, 1);
+
+	leds.led_num = plat_data->num;
+	if (leds.led_num <= 0 || leds.led_num > CONFIG_MXS_PWM_CHANNELS)
+		return -EFAULT;
+	leds.leds = plat_data->leds;
+	if (leds.leds == NULL)
+		return -EFAULT;
+
+	leds.pwm_clk = clk_get(&pdev->dev, "pwm");
+	if (IS_ERR(leds.pwm_clk)) {
+		rc = PTR_ERR(leds.pwm_clk);
+		return rc;
+	}
+
+	clk_enable(leds.pwm_clk);
+
+	for (i = 0; i < leds.led_num; i++) {
+		pwmn = leds.leds[i].pwm;
+		if (pwmn >= CONFIG_MXS_PWM_CHANNELS) {
+			dev_err(&pdev->dev,
+				"[led-pwm%d]:PWM %d doesn't exist\n",
+				i, pwmn);
+			continue;
+		}
+		led = &(leds.leds[i].dev);
+		led->name = leds.leds[i].name;
+		led->brightness = LED_HALF;
+		led->flags = 0;
+		led->brightness_set = mxs_pwm_led_brightness_set;
+		led->default_trigger = 0;
+
+		rc = led_classdev_register(&pdev->dev, led);
+		if (rc < 0) {
+			dev_err(&pdev->dev,
+				"Unable to register LED device %d (err=%d)\n",
+				i, rc);
+			continue;
+		}
+
+		leds_in_use++;
+
+		/* Set default brightness */
+		mxs_pwm_led_brightness_set(led, LED_HALF);
+	}
+
+	if (leds_in_use == 0) {
+		dev_info(&pdev->dev, "No PWM LEDs available\n");
+		clk_disable(leds.pwm_clk);
+		clk_put(leds.pwm_clk);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int __devexit mxs_pwm_led_remove(struct platform_device *pdev)
+{
+	int i;
+	unsigned int pwm;
+	for (i = 0; i < leds.led_num; i++) {
+		pwm = leds.leds[i].pwm;
+		__raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm),
+			     leds.base + HW_PWM_CTRL_CLR);
+		__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
+				BF_PWM_ACTIVEn_ACTIVE(0),
+			     leds.base + HW_PWM_ACTIVEn(pwm));
+		__raw_writel(BF_PWM_PERIODn_SETTINGS,
+			     leds.base + HW_PWM_PERIODn(pwm));
+		led_classdev_unregister(&leds.leds[i].dev);
+	}
+
+	clk_disable(leds.pwm_clk);
+	clk_put(leds.pwm_clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_led_suspend(struct platform_device *dev, pm_message_t state)
+{
+	int i;
+
+	for (i = 0; i < leds.led_num; i++)
+		led_classdev_suspend(&leds.leds[i].dev);
+	return 0;
+}
+
+static int mxs_led_resume(struct platform_device *dev)
+{
+	int i;
+
+	for (i = 0; i < leds.led_num; i++)
+		led_classdev_resume(&leds.leds[i].dev);
+	return 0;
+}
+#else
+#define mxs_led_suspend NULL
+#define mxs_led_resume NULL
+#endif
+
+
+static struct platform_driver mxs_pwm_led_driver = {
+	.probe   = mxs_pwm_led_probe,
+	.remove  = __devexit_p(mxs_pwm_led_remove),
+	.suspend = mxs_led_suspend,
+	.resume = mxs_led_resume,
+	.driver  = {
+		.name = "mxs-leds",
+	},
+};
+
+static int __init mxs_pwm_led_init(void)
+{
+	return platform_driver_register(&mxs_pwm_led_driver);
+}
+
+static void __exit mxs_pwm_led_exit(void)
+{
+	platform_driver_unregister(&mxs_pwm_led_driver);
+}
+
+module_init(mxs_pwm_led_init);
+module_exit(mxs_pwm_led_exit);
+
+MODULE_AUTHOR("Drew Benedetti <drewb@embeddedalley.com>");
+MODULE_DESCRIPTION("mxs PWM LED driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/leds/leds-stmp378x-pwm.c b/drivers/leds/leds-stmp378x-pwm.c
new file mode 100644
index 000000000000..f0865db4eb90
--- /dev/null
+++ b/drivers/leds/leds-stmp378x-pwm.c
@@ -0,0 +1,190 @@
+/*
+ * Freescale STMP378X PWM LED driver
+ *
+ * Author: Drew Benedetti <drewb@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <mach/hardware.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-clkctrl.h>
+#include <mach/pwm-led.h>
+#include <mach/stmp3xxx.h>
+
+/* Up to 5 PWM lines are available. */
+#define PWM_MAX 5
+
+/* PWM enables are the lowest PWM_MAX bits of HW_PWM_CTRL register */
+#define BM_PWM_CTRL_PWM_ENABLE(n)	((1<<(n)) & ((1<<(PWM_MAX))-1))
+#define BF_PWM_PERIODn_SETTINGS					\
+		(BF_PWM_PERIODn_CDIV(5) | /* divide by 64 */ 	\
+		BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ 	\
+		BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ 	\
+		BF_PWM_PERIODn_PERIOD(LED_FULL)) /* 255 cycles */
+
+struct stmp378x_led {
+	struct led_classdev led_dev;
+	int in_use;
+};
+
+static struct stmp378x_led leds[PWM_MAX];
+
+static struct clk *pwm_clk;
+
+static void stmp378x_pwm_led_brightness_set(struct led_classdev *pled,
+					    enum led_brightness value)
+{
+	unsigned int pwmn;
+
+	pwmn = container_of(pled, struct stmp378x_led, led_dev) - leds;
+
+	if (pwmn < PWM_MAX && leds[pwmn].in_use) {
+		HW_PWM_CTRL_CLR(BM_PWM_CTRL_PWM_ENABLE(pwmn));
+		HW_PWM_ACTIVEn_WR(pwmn, BF_PWM_ACTIVEn_INACTIVE(value) |
+				BF_PWM_ACTIVEn_ACTIVE(0));
+		HW_PWM_PERIODn_WR(pwmn, BF_PWM_PERIODn_SETTINGS);
+		HW_PWM_CTRL_SET(BM_PWM_CTRL_PWM_ENABLE(pwmn));
+	}
+}
+
+static int stmp378x_pwm_led_probe(struct platform_device *pdev)
+{
+	struct led_classdev *led;
+	unsigned int pwmn;
+	int leds_in_use = 0, rc = 0;
+	int i;
+
+	stmp3xxx_reset_block(REGS_PWM_BASE, 1);
+
+	pwm_clk = clk_get(&pdev->dev, "pwm");
+	if (IS_ERR(pwm_clk)) {
+		rc = PTR_ERR(pwm_clk);
+		return rc;
+	}
+
+	clk_enable(pwm_clk);
+
+	for (i = 0; i < pdev->num_resources; i++) {
+
+		if (pdev->resource[i].flags & IORESOURCE_DISABLED)
+			continue;
+
+		pwmn = pdev->resource[i].start;
+		if (pwmn >= PWM_MAX) {
+			dev_err(&pdev->dev, "PWM %d doesn't exist\n", pwmn);
+			continue;
+		}
+
+		rc = pwm_led_pinmux_request(pwmn, "stmp378x_pwm_led");
+		if (rc) {
+			dev_err(&pdev->dev,
+				"PWM %d is not available (err=%d)\n",
+				pwmn, rc);
+			continue;
+		}
+
+		led = &leds[pwmn].led_dev;
+
+		led->flags = pdev->resource[i].flags;
+		led->name = pdev->resource[i].name;
+		led->brightness = LED_HALF;
+		led->flags = 0;
+		led->brightness_set = stmp378x_pwm_led_brightness_set;
+		led->default_trigger = 0;
+
+		rc = led_classdev_register(&pdev->dev, led);
+		if (rc < 0) {
+			dev_err(&pdev->dev,
+				"Unable to register LED device %d (err=%d)\n",
+				pwmn, rc);
+			pwm_led_pinmux_free(pwmn, "stmp378x_pwm_led");
+			continue;
+		}
+
+		/* PWM LED is available now */
+		leds[pwmn].in_use = !0;
+		leds_in_use++;
+
+		/* Set default brightness */
+		stmp378x_pwm_led_brightness_set(led, LED_HALF);
+	}
+
+	if (leds_in_use == 0) {
+		dev_info(&pdev->dev, "No PWM LEDs available\n");
+		clk_disable(pwm_clk);
+		clk_put(pwm_clk);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int stmp378x_pwm_led_remove(struct platform_device *pdev)
+{
+	unsigned int pwmn;
+
+	for (pwmn = 0; pwmn < PWM_MAX; pwmn++) {
+
+		if (!leds[pwmn].in_use)
+			continue;
+
+		/* Disable LED */
+		HW_PWM_CTRL_CLR(BM_PWM_CTRL_PWM_ENABLE(pwmn));
+		HW_PWM_ACTIVEn_WR(pwmn, BF_PWM_ACTIVEn_INACTIVE(0) |
+				BF_PWM_ACTIVEn_ACTIVE(0));
+		HW_PWM_PERIODn_WR(pwmn, BF_PWM_PERIODn_SETTINGS);
+
+		led_classdev_unregister(&leds[pwmn].led_dev);
+		pwm_led_pinmux_free(pwmn, "stmp378x_pwm_led");
+
+		leds[pwmn].led_dev.name = 0;
+		leds[pwmn].in_use = 0;
+	}
+
+	clk_disable(pwm_clk);
+	clk_put(pwm_clk);
+
+	return 0;
+}
+
+
+static struct platform_driver stmp378x_pwm_led_driver = {
+	.probe   = stmp378x_pwm_led_probe,
+	.remove  = stmp378x_pwm_led_remove,
+	.driver  = {
+		.name = "stmp378x-pwm-led",
+	},
+};
+
+static int __init stmp378x_pwm_led_init(void)
+{
+	return platform_driver_register(&stmp378x_pwm_led_driver);
+}
+
+static void __exit stmp378x_pwm_led_exit(void)
+{
+	platform_driver_unregister(&stmp378x_pwm_led_driver);
+}
+
+module_init(stmp378x_pwm_led_init);
+module_exit(stmp378x_pwm_led_exit);
+
+MODULE_AUTHOR("Drew Benedetti <drewb@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP378X PWM LED driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig
index 3315cac875e5..14b1af783e1a 100644
--- a/drivers/media/radio/Kconfig
+++ b/drivers/media/radio/Kconfig
@@ -406,4 +406,6 @@ config RADIO_TEA5764_XTAL
 	  Say Y here if TEA5764 have a 32768 Hz crystal in circuit, say N
 	  here if TEA5764 reference frequency is connected in FREQIN.
 
+source "drivers/media/radio/stfm1000/Kconfig"
+
 endif # RADIO_ADAPTERS
diff --git a/drivers/media/radio/Makefile b/drivers/media/radio/Makefile
index 0f2b35b3e560..d8f720f16782 100644
--- a/drivers/media/radio/Makefile
+++ b/drivers/media/radio/Makefile
@@ -21,4 +21,6 @@ obj-$(CONFIG_USB_SI470X) += radio-si470x.o
 obj-$(CONFIG_USB_MR800) += radio-mr800.o
 obj-$(CONFIG_RADIO_TEA5764) += radio-tea5764.o
 
+obj-$(CONFIG_RADIO_STFM1000) += stfm1000/
+
 EXTRA_CFLAGS += -Isound
diff --git a/drivers/media/radio/stfm1000/Kconfig b/drivers/media/radio/stfm1000/Kconfig
new file mode 100644
index 000000000000..ef30bf87de0b
--- /dev/null
+++ b/drivers/media/radio/stfm1000/Kconfig
@@ -0,0 +1,26 @@
+config RADIO_STFM1000
+	tristate "STFM1000 support"
+	depends on I2C && VIDEO_V4L2 && ARCH_STMP3XXX
+	select I2C_ALGOBIT
+	---help---
+	  Choose Y here if you have this FM radio card, and then fill in the
+	  port address below.
+
+	  In order to control your radio card, you will need to use programs
+	  that are compatible with the Video For Linux API.  Information on
+	  this API and pointers to "v4l" programs may be found at
+	  <file:Documentation/video4linux/API.html>.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called stfm1000.
+
+config RADIO_STFM1000_ALSA
+	tristate "STFM1000 audio support"
+	depends on RADIO_STFM1000 && SND
+	select SND_PCM
+	---help---
+	  This is a video4linux driver for direct (DMA) audio in
+	  STFM1000 using ALSA
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called stfm1000-alsa.
diff --git a/drivers/media/radio/stfm1000/Makefile b/drivers/media/radio/stfm1000/Makefile
new file mode 100644
index 000000000000..01f354001a64
--- /dev/null
+++ b/drivers/media/radio/stfm1000/Makefile
@@ -0,0 +1,14 @@
+stfm1000-objs	:= stfm1000-core.o stfm1000-i2c.o stfm1000-precalc.o stfm1000-filter.o stfm1000-rds.o
+
+clean-files += stfm1000-precalc.o
+
+obj-$(CONFIG_RADIO_STFM1000) += stfm1000.o
+obj-$(CONFIG_RADIO_STFM1000_ALSA) += stfm1000-alsa.o
+
+stfm1000-core.o: $(obj)/stfm1000-precalc.h
+
+hostprogs-$(CONFIG_RADIO_STFM1000) := gen-precalc
+$(obj)/stfm1000-precalc.c: $(obj)/gen-precalc $(src)/stfm1000-regs.h
+	$(obj)/gen-precalc >$@
+
+EXTRA_CFLAGS += -Idrivers/media/radio
diff --git a/drivers/media/radio/stfm1000/gen-precalc.c b/drivers/media/radio/stfm1000/gen-precalc.c
new file mode 100644
index 000000000000..d3797dbef815
--- /dev/null
+++ b/drivers/media/radio/stfm1000/gen-precalc.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* generate precalculated tables */
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "stfm1000-regs.h"
+
+static void generate_tune1(void)
+{
+	int start, end;
+	int ndiv;           // N Divider in PLL
+	int incr;           // Increment in PLL
+	int cicosr;         // CIC oversampling ratio
+	int sdnominal;      // value to serve pilot/interpolator loop in SD
+	int i, temp;        // used in tuning table construction
+
+	start = STFM1000_FREQUENCY_100KHZ_MIN;
+	end = start + STFM1000_FREQUENCY_100KHZ_RANGE;
+
+	printf("const struct stfm1000_tune1\n"
+		"stfm1000_tune1_table[STFM1000_FREQUENCY_100KHZ_RANGE] = {\n");
+
+	for (i = start; i < end; i++) {
+
+		ndiv = (int)((i+14)/15) - 48;
+		incr = i - (int)(i/15)*15;
+		cicosr = (int)(i*2/3.0/16.0 + 0.5);
+		sdnominal = (int)(i*100.0e3/1.5/(double)cicosr/2.0/2.0*2.0*8.0*256.0/228.0e3*65536);
+
+		temp = 0x00000000;                                    // clear
+		temp = temp | ((cicosr<<9) & STFM1000_TUNE1_CICOSR);  // bits[14:9] 0x00007E00
+		temp = temp | ((ndiv<<4)   & STFM1000_TUNE1_PLL_DIV); // bits[8:4]  0x000001F0
+		temp = temp | ((incr)      & STFM1000_TUNE1_PLL_DIV); // bits[3:0]  0x0000000F
+
+		printf("\t[%d - STFM1000_FREQUENCY_100KHZ_MIN] = "
+			"{ .tune1 = 0x%08x, .sdnom = 0x%08x },\n",
+			i, temp, sdnominal);
+	}
+	printf("};\n");
+
+}
+
+int main(int argc, char *argv[])
+{
+	printf("#include \"stfm1000-regs.h\"\n\n");
+
+	generate_tune1();
+
+	return 0;
+}
diff --git a/drivers/media/radio/stfm1000/stfm1000-alsa.c b/drivers/media/radio/stfm1000/stfm1000-alsa.c
new file mode 100644
index 000000000000..d1da4475bc07
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-alsa.c
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/math64.h>
+
+#include <sound/control.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <linux/version.h>      /* for KERNEL_VERSION MACRO     */
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <mach/regs-dri.h>
+#include <mach/regs-apbx.h>
+#include <mach/regs-clkctrl.h>
+
+#include "stfm1000.h"
+
+#define STFM1000_PERIODS	16
+
+static int stfm1000_snd_volume_info(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 2;			/* two channels */
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 20;
+	return 0;
+}
+
+static int stfm1000_snd_volume_get(struct snd_kcontrol *kcontrol,
+				  struct snd_ctl_elem_value *ucontrol)
+{
+	struct stfm1000 *stfm1000 = snd_kcontrol_chip(kcontrol);
+
+	(void)stfm1000;
+	ucontrol->value.integer.value[0] = 0;	/* left */
+	ucontrol->value.integer.value[1] = 0;	/* right */
+	return 0;
+}
+
+static int stfm1000_snd_volume_put(struct snd_kcontrol *kcontrol,
+				  struct snd_ctl_elem_value *ucontrol)
+{
+	struct stfm1000 *stfm1000 = snd_kcontrol_chip(kcontrol);
+	int change;
+	int left, right;
+
+	(void)stfm1000;
+
+	left = ucontrol->value.integer.value[0];
+	if (left < 0)
+		left = 0;
+	if (left > 20)
+		left = 20;
+	right = ucontrol->value.integer.value[1];
+	if (right < 0)
+		right = 0;
+	if (right > 20)
+		right = 20;
+
+	change = 1;
+	return change;
+}
+
+static struct snd_kcontrol_new stfm1000_snd_controls[] = {
+	{
+		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+		.name = "Radio Volume",
+		.index = 0,
+		.info = stfm1000_snd_volume_info,
+		.get = stfm1000_snd_volume_get,
+		.put = stfm1000_snd_volume_put,
+		.private_value = 0,
+	},
+};
+
+static struct snd_pcm_hardware stfm1000_snd_capture = {
+
+	.info =                 SNDRV_PCM_INFO_MMAP |
+				SNDRV_PCM_INFO_MMAP_VALID |
+				SNDRV_PCM_INFO_INTERLEAVED |
+				SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
+	.rates =		SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+	.rate_min =		44100,
+	.rate_max =		48000,
+	.channels_min =		2,
+	.channels_max =		2,
+	.buffer_bytes_max =	SZ_256K,
+	.period_bytes_min =	SZ_4K,
+	.period_bytes_max =	SZ_4K,
+	.periods_min =		STFM1000_PERIODS,
+	.periods_max =		STFM1000_PERIODS,
+};
+
+static int stfm1000_snd_capture_open(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct stfm1000 *stfm1000 = snd_pcm_substream_chip(substream);
+	int err;
+
+	/* should never happen, just a sanity check */
+	BUG_ON(stfm1000 == NULL);
+
+	mutex_lock(&stfm1000->deffered_work_lock);
+	stfm1000->read_count  = 0;
+	stfm1000->read_offset = 0;
+
+	stfm1000->substream = substream;
+	runtime->private_data = stfm1000;
+	runtime->hw = stfm1000_snd_capture;
+
+	mutex_unlock(&stfm1000->deffered_work_lock);
+
+	err = snd_pcm_hw_constraint_integer(runtime,
+		SNDRV_PCM_HW_PARAM_PERIODS);
+	if (err < 0) {
+		printk(KERN_ERR "%s: snd_pcm_hw_constraint_integer "
+			"SNDRV_PCM_HW_PARAM_PERIODS failed\n", __func__);
+		return err;
+	}
+
+	err = snd_pcm_hw_constraint_step(runtime, 0,
+		SNDRV_PCM_HW_PARAM_PERIODS, 2);
+	if (err < 0) {
+		printk(KERN_ERR "%s: snd_pcm_hw_constraint_integer "
+			"SNDRV_PCM_HW_PARAM_PERIODS failed\n", __func__);
+		return err;
+	}
+
+	return 0;
+}
+
+static int stfm1000_snd_capture_close(struct snd_pcm_substream *substream)
+{
+	struct stfm1000 *stfm1000 = snd_pcm_substream_chip(substream);
+
+	(void)stfm1000;	/* nothing */
+	return 0;
+}
+
+static int stfm1000_snd_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *hw_params)
+{
+	struct stfm1000 *stfm1000 = snd_pcm_substream_chip(substream);
+	unsigned int period_size, periods;
+	int ret;
+
+	periods = params_periods(hw_params);
+	period_size = params_period_bytes(hw_params);
+
+	if (period_size < 0x100 || period_size > 0x10000)
+		return -EINVAL;
+	if (periods < STFM1000_PERIODS)
+		return -EINVAL;
+	if (period_size * periods > 1024 * 1024)
+		return -EINVAL;
+
+	stfm1000->blocks  = periods;
+	stfm1000->blksize = period_size;
+	stfm1000->bufsize = params_buffer_bytes(hw_params);
+
+	ret = snd_pcm_lib_malloc_pages(substream, stfm1000->bufsize);
+	if (ret < 0) {	/* 0 & 1 are valid returns */
+		printk(KERN_ERR "%s: snd_pcm_lib_malloc_pages() failed\n",
+			__func__);
+		return ret;
+	}
+
+	/* the dri buffer is twice as large as the audio buffer */
+	stfm1000->dri_bufsz = (stfm1000->bufsize / 4) *
+		sizeof(struct stfm1000_dri_sample);
+	stfm1000->dri_buf = dma_alloc_coherent(&stfm1000->radio.dev,
+			stfm1000->dri_bufsz, &stfm1000->dri_phys, GFP_KERNEL);
+	if (stfm1000->dri_buf == NULL) {
+		printk(KERN_ERR "%s: dma_alloc_coherent() failed\n", __func__);
+		snd_pcm_lib_free_pages(substream);
+		return -ENOMEM;
+	}
+
+	return ret;
+}
+
+static int stfm1000_snd_hw_free(struct snd_pcm_substream *substream)
+{
+	struct stfm1000 *stfm1000 = snd_pcm_substream_chip(substream);
+
+	if (stfm1000->dri_buf) {
+		dma_free_coherent(&stfm1000->radio.dev,
+			(stfm1000->bufsize / 4) *
+			sizeof(struct stfm1000_dri_sample),
+			stfm1000->dri_buf, stfm1000->dri_phys);
+		stfm1000->dri_buf = NULL;
+		stfm1000->dri_phys = 0;
+	}
+	snd_pcm_lib_free_pages(substream);
+	return 0;
+}
+
+
+static int stfm1000_snd_capture_prepare(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct stfm1000 *stfm1000 = snd_pcm_substream_chip(substream);
+
+	stfm1000->substream = substream;
+
+	if (snd_pcm_format_width(runtime->format) != 16 ||
+		!snd_pcm_format_signed(runtime->format) ||
+			snd_pcm_format_big_endian(runtime->format)) {
+		printk(KERN_INFO "STFM1000: ALSA capture_prepare illegal format\n");
+		return -EINVAL;
+	}
+
+	/* really shouldn't happen */
+	BUG_ON(stfm1000->blocks > stfm1000->desc_num);
+
+	mutex_lock(&stfm1000->deffered_work_lock);
+
+	if (stfm1000->now_recording != 0) {
+		printk(KERN_INFO "STFM1000: ALSA capture_prepare still running\n");
+		mutex_unlock(&stfm1000->deffered_work_lock);
+		return -EBUSY;
+	}
+	stfm1000->now_recording = 1;
+
+	mutex_unlock(&stfm1000->deffered_work_lock);
+
+	return 0;
+
+}
+
+static void stfm1000_snd_capture_trigger_start(struct work_struct *work)
+{
+	struct stfm1000 *stfm1000;
+
+	stfm1000 = container_of(work, struct stfm1000,
+		snd_capture_start_work.work);
+
+	mutex_lock(&stfm1000->deffered_work_lock);
+
+	BUG_ON(stfm1000->now_recording != 1);
+
+	stfm1000_bring_up(stfm1000);
+
+	mutex_unlock(&stfm1000->deffered_work_lock);
+}
+
+static void stfm1000_snd_capture_trigger_stop(struct work_struct *work)
+{
+	struct stfm1000 *stfm1000;
+
+	stfm1000 = container_of(work, struct stfm1000,
+		snd_capture_stop_work.work);
+
+	mutex_lock(&stfm1000->deffered_work_lock);
+
+	stfm1000->stopping_recording = 1;
+
+	stfm1000_take_down(stfm1000);
+
+	BUG_ON(stfm1000->now_recording != 1);
+	stfm1000->now_recording = 0;
+
+	stfm1000->stopping_recording = 0;
+
+	mutex_unlock(&stfm1000->deffered_work_lock);
+}
+
+static int execute_non_atomic(work_func_t fn, struct execute_work *ew)
+{
+	if (!in_atomic() && !in_interrupt()) {
+		fn(&ew->work);
+		return 0;
+	}
+
+	INIT_WORK(&ew->work, fn);
+	schedule_work(&ew->work);
+
+	return 1;
+}
+
+static int stfm1000_snd_capture_trigger(struct snd_pcm_substream *substream,
+	int cmd)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct stfm1000 *stfm1000 = runtime->private_data;
+	int err = 0;
+
+	(void)stfm1000;
+
+	switch (cmd) {
+
+	case SNDRV_PCM_TRIGGER_START:
+		execute_non_atomic(stfm1000_snd_capture_trigger_start,
+			&stfm1000->snd_capture_start_work);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+		execute_non_atomic(stfm1000_snd_capture_trigger_stop,
+			&stfm1000->snd_capture_stop_work);
+		break;
+
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		stmp3xxx_dma_unfreeze(stfm1000->dma_ch);
+		break;
+
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		stmp3xxx_dma_freeze(stfm1000->dma_ch);
+		break;
+
+	default:
+		err = -EINVAL;
+		break;
+	}
+
+	return err;
+}
+
+static snd_pcm_uframes_t
+stfm1000_snd_capture_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct stfm1000 *stfm1000 = runtime->private_data;
+
+	if (stfm1000->read_count) {
+		stfm1000->read_count  -= snd_pcm_lib_period_bytes(substream);
+		stfm1000->read_offset += snd_pcm_lib_period_bytes(substream);
+		if (stfm1000->read_offset == substream->runtime->dma_bytes)
+			stfm1000->read_offset = 0;
+	}
+
+	return bytes_to_frames(runtime, stfm1000->read_offset);
+}
+
+static struct snd_pcm_ops stfm1000_snd_capture_ops = {
+	.open = stfm1000_snd_capture_open,
+	.close = stfm1000_snd_capture_close,
+	.ioctl = snd_pcm_lib_ioctl,
+	.hw_params = stfm1000_snd_hw_params,
+	.hw_free = stfm1000_snd_hw_free,
+	.prepare = stfm1000_snd_capture_prepare,
+	.trigger = stfm1000_snd_capture_trigger,
+	.pointer = stfm1000_snd_capture_pointer,
+};
+
+static void stfm1000_snd_free(struct snd_card *card)
+{
+	struct stfm1000 *stfm1000 = card->private_data;
+
+	free_irq(IRQ_DRI_ATTENTION, stfm1000);
+	free_irq(IRQ_DRI_DMA, stfm1000);
+}
+
+static int stfm1000_alsa_instance_init(struct stfm1000 *stfm1000)
+{
+	int ret, i;
+	struct snd_card *card;
+	struct snd_pcm *pcm;
+	struct snd_kcontrol *ctl;
+
+	mutex_init(&stfm1000->deffered_work_lock);
+
+	/* request dma channel */
+	stfm1000->desc_num = STFM1000_PERIODS;
+	stfm1000->dma_ch = STMP3xxx_DMA(5, STMP3XXX_BUS_APBX);
+	ret = stmp3xxx_dma_request(stfm1000->dma_ch, &stfm1000->radio.dev,
+			"stmp3xxx dri");
+	if (ret != 0) {
+		printk(KERN_ERR "%s: stmp3xxx_dma_request failed\n", __func__);
+		goto err;
+	}
+
+	stfm1000->dma = kzalloc(sizeof(*stfm1000->dma) * stfm1000->desc_num,
+			GFP_KERNEL);
+	if (stfm1000->dma == NULL) {
+		printk(KERN_ERR "%s: stmp3xxx_dma_request failed\n", __func__);
+		ret = -ENOMEM;
+		goto err_rel_dma;
+	}
+
+	for (i = 0; i < stfm1000->desc_num; i++) {
+		ret = stmp3xxx_dma_allocate_command(stfm1000->dma_ch,
+				&stfm1000->dma[i]);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: stmp3xxx_dma_allocate_command "
+				"failed\n", __func__);
+			goto err_free_dma;
+		}
+	}
+
+	/* allocate ALSA card structure (we only need an extra pointer
+	 * back to stfm1000) */
+	card = snd_card_new(-1, NULL, THIS_MODULE, 0);
+	if (card == NULL) {
+		ret = -ENOMEM;
+		printk(KERN_ERR "%s: snd_card_new failed\n", __func__);
+		goto err_free_dma;
+	}
+	stfm1000->card = card;
+	card->private_data = stfm1000;	/* point back */
+
+	/* mixer controls */
+	strcpy(card->driver, "stfm1000");
+	card->private_free = stfm1000_snd_free;
+
+	strcpy(card->mixername, "stfm1000 mixer");
+	for (i = 0; i < ARRAY_SIZE(stfm1000_snd_controls); i++) {
+		ctl = snd_ctl_new1(&stfm1000_snd_controls[i], stfm1000);
+		if (ctl == NULL) {
+			printk(KERN_ERR "%s: snd_ctl_new1 failed\n", __func__);
+			goto err_free_controls;
+		}
+		ret = snd_ctl_add(card, ctl);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: snd_ctl_add failed\n", __func__);
+			goto err_free_controls;
+		}
+	}
+
+	/* PCM */
+	ret = snd_pcm_new(card, "STFM1000 PCM", 0, 0, 1, &pcm);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: snd_ctl_add failed\n", __func__);
+		goto err_free_controls;
+	}
+	stfm1000->pcm = pcm;
+	pcm->private_data = stfm1000;	/* point back */
+
+	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
+		&stfm1000_snd_capture_ops);
+	pcm->info_flags = 0;
+	strcpy(pcm->name, "STFM1000 PCM");
+
+	snd_card_set_dev(card, &stfm1000->radio.dev);
+	strcpy(card->shortname, "STFM1000");
+
+	ret = snd_pcm_lib_preallocate_pages_for_all(stfm1000->pcm,
+		SNDRV_DMA_TYPE_CONTINUOUS, card->dev, SZ_256K, SZ_256K);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: snd_pcm_lib_preallocate_pages_for_all "
+			"failed\n", __func__);
+		goto err_free_pcm;
+	}
+
+	ret = request_irq(IRQ_DRI_DMA, stfm1000_dri_dma_irq, 0, "stfm1000",
+		stfm1000);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: request_irq failed\n", __func__);
+		goto err_free_prealloc;
+	}
+
+	ret = request_irq(IRQ_DRI_ATTENTION, stfm1000_dri_attn_irq, 0,
+		"stfm1000", stfm1000);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: request_irq failed\n", __func__);
+		goto err_rel_irq;
+	}
+
+	ret = snd_card_register(stfm1000->card);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: snd_card_register failed\n", __func__);
+		goto err_rel_irq2;
+	}
+
+	/* Enable completion interrupt */
+	stmp3xxx_dma_clear_interrupt(stfm1000->dma_ch);
+	stmp3xxx_dma_enable_interrupt(stfm1000->dma_ch);
+
+	printk(KERN_INFO "%s/alsa: %s registered\n", "STFM1000",
+		card->longname);
+
+	return 0;
+
+err_rel_irq2:
+	free_irq(IRQ_DRI_ATTENTION, stfm1000);
+
+err_rel_irq:
+	free_irq(IRQ_DRI_DMA, stfm1000);
+
+err_free_prealloc:
+	snd_pcm_lib_preallocate_free_for_all(stfm1000->pcm);
+
+err_free_pcm:
+	/* XXX TODO */
+
+err_free_controls:
+	/* XXX TODO */
+
+/* err_free_card: */
+	snd_card_free(stfm1000->card);
+
+err_free_dma:
+	for (i = stfm1000->desc_num - 1; i >= 0; i--) {
+		if (stfm1000->dma[i].command != NULL)
+			stmp3xxx_dma_free_command(stfm1000->dma_ch,
+				&stfm1000->dma[i]);
+	}
+
+err_rel_dma:
+	stmp3xxx_dma_release(stfm1000->dma_ch);
+err:
+	return ret;
+}
+
+static void stfm1000_alsa_instance_release(struct stfm1000 *stfm1000)
+{
+	int i;
+
+	stmp3xxx_dma_clear_interrupt(stfm1000->dma_ch);
+	stmp3xxx_arch_dma_reset_channel(stfm1000->dma_ch);
+
+	snd_card_free(stfm1000->card);
+
+	for (i = stfm1000->desc_num - 1; i >= 0; i--)
+		stmp3xxx_dma_free_command(stfm1000->dma_ch, &stfm1000->dma[i]);
+
+	kfree(stfm1000->dma);
+
+	stmp3xxx_dma_release(stfm1000->dma_ch);
+}
+
+static void stfm1000_alsa_dma_irq(struct stfm1000 *stfm1000)
+{
+	struct snd_pcm_runtime *runtime;
+	int desc;
+	s16 *src, *dst;
+
+	if (stfm1000->stopping_recording)
+		return;
+
+	if (stfm1000->read_count >= stfm1000->blksize *
+			(stfm1000->blocks - 2)) {
+		printk(KERN_ERR "irq: overrun %d - Blocks in %d\n",
+			stfm1000->read_count, stfm1000->blocks);
+		return;
+	}
+
+	/* someone has brutally killed user-space */
+	if (stfm1000->substream == NULL ||
+			stfm1000->substream->runtime == NULL)
+		return;
+
+	BUG_ON(stfm1000->substream == NULL);
+	BUG_ON(stfm1000->substream->runtime == NULL);
+
+	desc = stfm1000->read_offset / stfm1000->blksize;
+	runtime = stfm1000->substream->runtime;
+
+	if (runtime->dma_area == NULL)
+		printk(KERN_INFO "runtime->dma_area = NULL\n");
+	BUG_ON(runtime->dma_area == NULL);
+	if (stfm1000->dri_buf == NULL)
+		printk(KERN_INFO "stfm1000->dri_buf = NULL\n");
+	BUG_ON(stfm1000->dri_buf == NULL);
+
+	if (desc >= stfm1000->blocks) {
+		printk(KERN_INFO "desc=%d ->blocks=%d\n",
+				desc, stfm1000->blocks);
+		printk(KERN_INFO "->read_offset=%x ->blksize=%x\n",
+				stfm1000->read_offset, stfm1000->blksize);
+	}
+	BUG_ON(desc >= stfm1000->blocks);
+
+	src = stfm1000->dri_buf + desc * (stfm1000->blksize * 2);
+	dst = (void *)runtime->dma_area + desc * stfm1000->blksize;
+
+	/* perform filtering */
+	stfm1000_decode_block(stfm1000, src, dst, stfm1000->blksize / 4);
+
+	stfm1000->read_count += stfm1000->blksize;
+
+	if (stfm1000->read_count >=
+		snd_pcm_lib_period_bytes(stfm1000->substream))
+		snd_pcm_period_elapsed(stfm1000->substream);
+}
+
+static void stfm1000_alsa_attn_irq(struct stfm1000 *stfm1000)
+{
+	/* nothing */
+}
+
+struct stfm1000_alsa_ops stfm1000_default_alsa_ops = {
+	.init = stfm1000_alsa_instance_init,
+	.release = stfm1000_alsa_instance_release,
+	.dma_irq = stfm1000_alsa_dma_irq,
+	.attn_irq = stfm1000_alsa_attn_irq,
+};
+
+static int stfm1000_alsa_init(void)
+{
+	struct stfm1000 *stfm1000 = NULL;
+	struct list_head *list;
+	int ret;
+
+	stfm1000_alsa_ops = &stfm1000_default_alsa_ops;
+
+	list_for_each(list, &stfm1000_devlist) {
+		stfm1000 = list_entry(list, struct stfm1000, devlist);
+		ret = (*stfm1000_alsa_ops->init)(stfm1000);
+		if (ret != 0) {
+			printk(KERN_ERR "stfm1000 ALSA driver for DMA sound "
+				"failed init.\n");
+			return ret;
+		}
+		stfm1000->alsa_initialized = 1;
+	}
+
+	printk(KERN_INFO "stfm1000 ALSA driver for DMA sound loaded\n");
+
+	return 0;
+}
+
+static void stfm1000_alsa_exit(void)
+{
+	struct stfm1000 *stfm1000 = NULL;
+	struct list_head *list;
+
+	list_for_each(list, &stfm1000_devlist) {
+		stfm1000 = list_entry(list, struct stfm1000, devlist);
+
+		if (!stfm1000->alsa_initialized)
+			continue;
+
+		stfm1000_take_down(stfm1000);
+		(*stfm1000_alsa_ops->release)(stfm1000);
+		stfm1000->alsa_initialized = 0;
+	}
+
+	printk(KERN_INFO "stfm1000 ALSA driver for DMA sound unloaded\n");
+}
+
+/* We initialize this late, to make sure the sound system is up and running */
+late_initcall(stfm1000_alsa_init);
+module_exit(stfm1000_alsa_exit);
+
+MODULE_AUTHOR("Pantelis Antoniou");
+MODULE_DESCRIPTION("An ALSA PCM driver for the STFM1000 chip.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/radio/stfm1000/stfm1000-core.c b/drivers/media/radio/stfm1000/stfm1000-core.c
new file mode 100644
index 000000000000..5086100bb480
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-core.c
@@ -0,0 +1,2459 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/math64.h>
+
+#include <sound/control.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <linux/version.h>	/* for KERNEL_VERSION MACRO */
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/freezer.h>
+#include <linux/kthread.h>
+#include <mach/regs-dri.h>
+#include <mach/regs-apbx.h>
+#include <mach/regs-clkctrl.h>
+
+#include "stfm1000.h"
+
+static DEFINE_MUTEX(devlist_lock);
+static unsigned int stfm1000_devcount;
+
+LIST_HEAD(stfm1000_devlist);
+EXPORT_SYMBOL(stfm1000_devlist);
+
+/* alsa interface */
+struct stfm1000_alsa_ops *stfm1000_alsa_ops;
+EXPORT_SYMBOL(stfm1000_alsa_ops);
+
+/* region, 0=US, 1=europe */
+static int georegion = 1;	/* default is europe */
+static int rds_enable = 1;	/* default is enabled */
+
+static int sw_tune(struct stfm1000 *stfm1000, u32 freq);
+
+static const const char *stfm1000_get_rev_txt(u32 id)
+{
+	switch (id) {
+	case 0x01: return "TA1";
+	case 0x02: return "TA2";
+	case 0x11: return "TB1";
+	case 0x12: return "TB2";
+	}
+	return NULL;
+}
+
+static const struct stfm1000_reg stfm1000_tb2_powerup[] = {
+	STFM1000_REG(REF, 0x00200000),
+	STFM1000_DELAY(20),
+	STFM1000_REG(DATAPATH, 0x00010210),
+	STFM1000_REG(TUNE1, 0x0004CF01),
+	STFM1000_REG(SDNOMINAL, 0x1C5EBCF0),
+	STFM1000_REG(PILOTTRACKING, 0x000001B6),
+	STFM1000_REG(INITIALIZATION1, 0x9fb80008),
+	STFM1000_REG(INITIALIZATION2, 0x8516e444 | STFM1000_DEEMPH_50_75B),
+	STFM1000_REG(INITIALIZATION3, 0x1402190b),
+	STFM1000_REG(INITIALIZATION4, 0x525bf052),
+	STFM1000_REG(INITIALIZATION5, 0x1000d106),
+	STFM1000_REG(INITIALIZATION6, 0x000062cb),
+	STFM1000_REG(AGC_CONTROL1, 0x1BCB2202),
+	STFM1000_REG(AGC_CONTROL2, 0x000020F0),
+	STFM1000_REG(CLK1, 0x10000000),
+	STFM1000_REG(CLK1, 0x20000000),
+	STFM1000_REG(CLK1, 0x00000000),
+	STFM1000_REG(CLK2, 0x7f000000),
+	STFM1000_REG(REF, 0x00B8222D),
+	STFM1000_REG(CLK1, 0x30000000),
+	STFM1000_REG(CLK1, 0x30002000),
+	STFM1000_REG(CLK1, 0x10002000),
+	STFM1000_REG(LNA, 0x0D080009),
+	STFM1000_DELAY(10),
+	STFM1000_REG(MIXFILT, 0x00008000),
+	STFM1000_REG(MIXFILT, 0x00000000),
+	STFM1000_REG(MIXFILT, 0x00007205),
+	STFM1000_REG(ADC, 0x001B3282),
+	STFM1000_REG(ATTENTION, 0x0000003F),
+	STFM1000_END,
+};
+
+static const struct stfm1000_reg stfm1000_ta2_powerup[] = {
+	STFM1000_REG(REF, 0x00200000),
+	STFM1000_DELAY(20),
+	STFM1000_REG(DATAPATH, 0x00010210),
+	STFM1000_REG(TUNE1, 0x00044F01),
+	STFM1000_REG(SDNOMINAL, 0x1C5EBCF0),
+	STFM1000_REG(PILOTTRACKING, 0x000001B6),
+	STFM1000_REG(INITIALIZATION1, 0x9fb80008),
+	STFM1000_REG(INITIALIZATION2, 0x8506e444),
+	STFM1000_REG(INITIALIZATION3, 0x1402190b),
+	STFM1000_REG(INITIALIZATION4, 0x525bf052),
+	STFM1000_REG(INITIALIZATION5, 0x7000d106),
+	STFM1000_REG(INITIALIZATION6, 0x0000c2cb),
+	STFM1000_REG(AGC_CONTROL1, 0x002c8402),
+	STFM1000_REG(AGC_CONTROL2, 0x00140050),
+	STFM1000_REG(CLK1, 0x10000000),
+	STFM1000_REG(CLK1, 0x20000000),
+	STFM1000_REG(CLK1, 0x00000000),
+	STFM1000_REG(CLK2, 0x7f000000),
+	STFM1000_REG(REF, 0x0030222D),
+	STFM1000_REG(CLK1, 0x30000000),
+	STFM1000_REG(CLK1, 0x30002000),
+	STFM1000_REG(CLK1, 0x10002000),
+	STFM1000_REG(LNA, 0x05080009),
+	STFM1000_REG(MIXFILT, 0x00008000),
+	STFM1000_REG(MIXFILT, 0x00000000),
+	STFM1000_REG(MIXFILT, 0x00007200),
+	STFM1000_REG(ADC, 0x00033000),
+	STFM1000_REG(ATTENTION, 0x0000003F),
+	STFM1000_END,
+};
+
+static const struct stfm1000_reg stfm1000_powerdown[] = {
+	STFM1000_REG(DATAPATH, 0x00010210),
+	STFM1000_REG(REF, 0),
+	STFM1000_REG(LNA, 0),
+	STFM1000_REG(MIXFILT, 0),
+	STFM1000_REG(CLK1, 0x20000000),
+	STFM1000_REG(CLK1, 0),
+	STFM1000_REG(CLK2, 0),
+	STFM1000_REG(ADC, 0),
+	STFM1000_REG(TUNE1, 0),
+	STFM1000_REG(SDNOMINAL, 0),
+	STFM1000_REG(PILOTTRACKING, 0),
+	STFM1000_REG(INITIALIZATION1, 0),
+	STFM1000_REG(INITIALIZATION2, 0),
+	STFM1000_REG(INITIALIZATION3, 0),
+	STFM1000_REG(INITIALIZATION4, 0),
+	STFM1000_REG(INITIALIZATION5, 0),
+	STFM1000_REG(INITIALIZATION6, 0x00007E00),
+	STFM1000_REG(AGC_CONTROL1, 0),
+	STFM1000_REG(AGC_CONTROL2, 0),
+	STFM1000_REG(DATAPATH, 0x00000200),
+};
+
+struct stfm1000_tuner_pmi {
+	u32 min;
+	u32 max;
+	u32 freq;
+	u32 pll_xtal;	/* 1 = pll, 0 = xtal */
+};
+
+#define PLL 1
+#define XTAL 0
+
+static const struct stfm1000_tuner_pmi stfm1000_pmi_lookup[] = {
+	{ .min =  76100, .max =  76500, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  79700, .max =  79900, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  80800, .max =  81200, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  82100, .max =  82600, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  86800, .max =  87200, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  88100, .max =  88600, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  89800, .max =  90500, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  91400, .max =  91900, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  92800, .max =  93300, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  97400, .max =  97900, .freq = 19200, .pll_xtal = PLL },
+	{ .min =  98800, .max =  99200, .freq = 19200, .pll_xtal = PLL },
+	{ .min = 100200, .max = 100400, .freq = 19200, .pll_xtal = PLL },
+	{ .min = 103500, .max = 103900, .freq = 19200, .pll_xtal = PLL },
+	{ .min = 104800, .max = 105200, .freq = 19200, .pll_xtal = PLL },
+	{ .min = 106100, .max = 106500, .freq = 19200, .pll_xtal = PLL },
+
+	{ .min =  76600, .max =  77000, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  77800, .max =  78300, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  79200, .max =  79600, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  80600, .max =  80700, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  83900, .max =  84400, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  85300, .max =  85800, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  94200, .max =  94700, .freq = 20000, .pll_xtal = PLL },
+	{ .min =  95600, .max =  96100, .freq = 20000, .pll_xtal = PLL },
+	{ .min = 100500, .max = 100800, .freq = 20000, .pll_xtal = PLL },
+	{ .min = 101800, .max = 102200, .freq = 20000, .pll_xtal = PLL },
+	{ .min = 103100, .max = 103400, .freq = 20000, .pll_xtal = PLL },
+	{ .min = 106600, .max = 106900, .freq = 20000, .pll_xtal = PLL },
+	{ .min = 107800, .max = 108000, .freq = 20000, .pll_xtal = PLL },
+
+	{ .min =      0, .max =      0, .freq = 24000, .pll_xtal = XTAL }
+};
+
+int stfm1000_power_up(struct stfm1000 *stfm1000)
+{
+	struct stfm1000_reg *reg, *pwrup_reg;
+	const struct stfm1000_reg *orig_reg, *treg;
+	int ret, size;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	/* Enable DRI clock for 24Mhz. */
+	HW_CLKCTRL_XTAL_CLR(BM_CLKCTRL_XTAL_DRI_CLK24M_GATE);
+
+	orig_reg = stfm1000->revid == STFM1000_CHIP_REV_TA2 ?
+			stfm1000_ta2_powerup : stfm1000_tb2_powerup;
+
+	/* find size of the set */
+	for (treg = orig_reg; treg->regno != STFM1000_REG_END; treg++)
+		;
+	size = (treg + 1 - orig_reg) * sizeof(*treg);
+
+	/* allocate copy */
+	pwrup_reg = kmalloc(size, GFP_KERNEL);
+	if (pwrup_reg == NULL) {
+		printk(KERN_ERR "%s: out of memory\n", __func__);
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	/* copy it */
+	memcpy(pwrup_reg, orig_reg, size);
+
+	/* fixup region of INITILIZATION2 */
+	for (reg = pwrup_reg; reg->regno != STFM1000_REG_END; reg++) {
+
+		/* we only care for INITIALIZATION2 register */
+		if (reg->regno != STFM1000_INITIALIZATION2)
+			continue;
+
+		/* geographic region select */
+		if (stfm1000->georegion == 0)	/* USA */
+			reg->value &= ~STFM1000_DEEMPH_50_75B;
+		else			/* Europe */
+			reg->value |=  STFM1000_DEEMPH_50_75B;
+
+		/* RDS enabled */
+		if (stfm1000->revid == STFM1000_CHIP_REV_TB2) {
+			if (stfm1000->rds_enable)
+				reg->value |=  STFM1000_RDS_ENABLE;
+			else
+				reg->value &= ~STFM1000_RDS_ENABLE;
+		}
+	}
+
+	ret = stfm1000_write_regs(stfm1000, pwrup_reg);
+
+	kfree(pwrup_reg);
+out:
+	mutex_unlock(&stfm1000->state_lock);
+
+	return ret;
+}
+
+int stfm1000_power_down(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	/* Disable DRI clock for 24Mhz. */
+	HW_CLKCTRL_XTAL_CLR(BM_CLKCTRL_XTAL_DRI_CLK24M_GATE);
+
+	ret = stfm1000_write_regs(stfm1000, stfm1000_powerdown);
+
+	/* Disable DRI clock for 24Mhz. */
+	/* XXX bug warning, disabling the DRI clock is bad news */
+	/* doing so causes noise to be received from the DRI */
+	/* interface. Leave it on for now */
+	/* HW_CLKCTRL_XTAL_CLR(BM_CLKCTRL_XTAL_DRI_CLK24M_GATE); */
+
+	mutex_unlock(&stfm1000->state_lock);
+
+	return ret;
+}
+
+int stfm1000_dcdc_update(struct stfm1000 *stfm1000, u32 freq)
+{
+	const struct stfm1000_tuner_pmi *pmi;
+	int i;
+
+	/* search for DCDC frequency */
+	pmi = stfm1000_pmi_lookup;
+	for (i = 0;  i < ARRAY_SIZE(stfm1000_pmi_lookup); i++, pmi++) {
+		if (freq >= pmi->min && freq <= pmi->max)
+			break;
+	}
+	if (i >= ARRAY_SIZE(stfm1000_pmi_lookup))
+		return -1;
+
+	/* adjust DCDC frequency so that it is out of Tuner PLL range */
+	/* XXX there is no adjustment API (os_pmi_SetDcdcFreq)*/
+	return 0;
+}
+
+static void Mute_Audio(struct stfm1000 *stfm1000)
+{
+	stfm1000->mute = 1;
+}
+
+static void Unmute_Audio(struct stfm1000 *stfm1000)
+{
+	stfm1000->mute = 0;
+}
+
+static const struct stfm1000_reg sd_dp_on_regs[] = {
+	STFM1000_REG_SETBITS(DATAPATH, STFM1000_DP_EN),
+	STFM1000_DELAY(3),
+	STFM1000_REG_SETBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_REG_CLRBITS(AGC_CONTROL1, STFM1000_B2_BYPASS_AGC_CTL),
+	STFM1000_REG_CLRBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_END,
+};
+
+static int SD_DP_On(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	ret = stfm1000_write_regs(stfm1000, sd_dp_on_regs);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static const struct stfm1000_reg sd_dp_off_regs[] = {
+	STFM1000_REG_SETBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_REG_CLRBITS(DATAPATH, STFM1000_DP_EN),
+	STFM1000_REG_SETBITS(AGC_CONTROL1, STFM1000_B2_BYPASS_AGC_CTL),
+	STFM1000_REG_CLRBITS(PILOTTRACKING, STFM1000_B2_PILOTTRACKING_EN),
+	STFM1000_REG_CLRBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_END,
+};
+
+static int SD_DP_Off(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	ret = stfm1000_write_regs(stfm1000, sd_dp_off_regs);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static int DRI_Start_Stream(struct stfm1000 *stfm1000)
+{
+	dma_addr_t dma_buffer_phys;
+	int i, next;
+	u32 cmd;
+
+	/* we must not be gated */
+	BUG_ON(HW_CLKCTRL_XTAL_RD() & BM_CLKCTRL_XTAL_DRI_CLK24M_GATE);
+
+	/* hw_dri_SetReset */
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_SFTRST | BM_DRI_CTRL_CLKGATE);
+	HW_DRI_CTRL_SET(BM_DRI_CTRL_SFTRST);
+	while ((HW_DRI_CTRL_RD() & BM_DRI_CTRL_CLKGATE) == 0)
+		cpu_relax();
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_SFTRST | BM_DRI_CTRL_CLKGATE);
+
+	/* DRI enable/config */
+	HW_DRI_TIMING_WR(BF_DRI_TIMING_GAP_DETECTION_INTERVAL(0x10) |
+			 BF_DRI_TIMING_PILOT_REP_RATE(0x08));
+
+	/* XXX SDK bug */
+	/* While the SDK enables the gate here, everytime the stream */
+	/* is started, doing so, causes the DRI to input audio noise */
+	/* at any subsequent starts */
+	/* Enable DRI clock for 24Mhz. */
+	/* HW_CLKCTRL_XTAL_CLR(BM_CLKCTRL_XTAL_DRI_CLK24M_GATE); */
+
+	stmp3xxx_arch_dma_reset_channel(stfm1000->dma_ch);
+
+	dma_buffer_phys = stfm1000->dri_phys;
+
+	for (i = 0; i < stfm1000->blocks; i++) {
+		next = (i + 1) % stfm1000->blocks;
+
+		/* link */
+		stfm1000->dma[i].command->next = stfm1000->dma[next].handle;
+		stfm1000->dma[i].next_descr = &stfm1000->dma[next];
+
+		/* receive DRI is 8 bytes per 4 samples */
+		cmd = BF_APBX_CHn_CMD_XFER_COUNT(stfm1000->blksize * 2) |
+		      BM_APBX_CHn_CMD_IRQONCMPLT |
+		      BM_APBX_CHn_CMD_CHAIN |
+		      BF_APBX_CHn_CMD_COMMAND(
+			BV_APBX_CHn_CMD_COMMAND__DMA_WRITE);
+
+		stfm1000->dma[i].command->cmd = cmd;
+		stfm1000->dma[i].command->buf_ptr = dma_buffer_phys;
+		stfm1000->dma[i].command->pio_words[0] =
+			BM_DRI_CTRL_OVERFLOW_IRQ_EN |
+			BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN |
+			BM_DRI_CTRL_ATTENTION_IRQ_EN |
+			/* BM_DRI_CTRL_STOP_ON_OFLOW_ERROR | */
+			/* BM_DRI_CTRL_STOP_ON_PILOT_ERROR | */
+			BM_DRI_CTRL_ENABLE_INPUTS;
+
+		dma_buffer_phys += stfm1000->blksize * 2;
+
+	}
+
+	/* Enable completion interrupt */
+	stmp3xxx_dma_clear_interrupt(stfm1000->dma_ch);
+	stmp3xxx_dma_enable_interrupt(stfm1000->dma_ch);
+
+	/* clear DRI interrupts pending */
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_OVERFLOW_IRQ |
+			BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ |
+			BM_DRI_CTRL_ATTENTION_IRQ);
+
+	/* Stop DRI on error */
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_STOP_ON_OFLOW_ERROR |
+			BM_DRI_CTRL_STOP_ON_PILOT_ERROR);
+
+	/* Reacquire data stream */
+	HW_DRI_CTRL_SET(BM_DRI_CTRL_REACQUIRE_PHASE |
+		BM_DRI_CTRL_OVERFLOW_IRQ_EN |
+		BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN |
+		BM_DRI_CTRL_ATTENTION_IRQ_EN |
+		BM_DRI_CTRL_ENABLE_INPUTS);
+
+	stmp3xxx_dma_go(stfm1000->dma_ch, stfm1000->dma, 1);
+
+	/* Turn on DRI hardware (don't forget to leave RUN bit ON) */
+	HW_DRI_CTRL_SET(BM_DRI_CTRL_RUN);
+
+	return 0;
+}
+
+static int DRI_Stop_Stream(struct stfm1000 *stfm1000)
+{
+	int desc;
+
+	/* disable interrupts */
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_OVERFLOW_IRQ_EN |
+			BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN |
+			BM_DRI_CTRL_ATTENTION_IRQ_EN);
+
+	/* Freeze DMA channel for a moment */
+	stmp3xxx_dma_freeze(stfm1000->dma_ch);
+
+	/* all descriptors, set sema bit */
+	for (desc = 0; desc < stfm1000->blocks; desc++)
+		stfm1000->dma[desc].command->cmd |= BM_APBX_CHn_CMD_SEMAPHORE;
+
+	/* Let the current DMA transaction finish */
+	stmp3xxx_dma_unfreeze(stfm1000->dma_ch);
+	msleep(5);
+
+	/* dma shutdown */
+	stmp3xxx_arch_dma_reset_channel(stfm1000->dma_ch);
+
+	/* Turn OFF data lines and stop controller */
+	HW_DRI_CTRL_CLR(BM_DRI_CTRL_ENABLE_INPUTS | BM_DRI_CTRL_RUN);
+
+	/* hw_dri_SetReset */
+	HW_DRI_CTRL_SET(BM_DRI_CTRL_SFTRST | BM_DRI_CTRL_CLKGATE);
+
+	/* XXX SDK bug */
+	/* While the SDK enables the gate here, everytime the stream */
+	/* is started, doing so, causes the DRI to input audio noise */
+	/* at any subsequent starts */
+	/* Enable DRI clock for 24Mhz. */
+	/* Disable DRI clock for 24Mhz. */
+	/* HW_CLKCTRL_XTAL_SET(BM_CLKCTRL_XTAL_DRI_CLK24M_GATE); */
+
+	return 0;
+}
+
+static int DRI_On(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	if (stfm1000->active)
+		DRI_Start_Stream(stfm1000);
+
+	ret = stfm1000_set_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_SAI_EN);
+	return ret;
+}
+
+static int DRI_Off(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	if (stfm1000->active)
+		DRI_Stop_Stream(stfm1000);
+
+	ret = stfm1000_clear_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_SAI_EN);
+
+	return 0;
+}
+
+static int SD_Set_Channel_Filter(struct stfm1000 *stfm1000)
+{
+	int bypass_setting;
+	int sig_qual;
+	u32 tmp;
+	int ret;
+
+	/*
+	 * set channel filter
+	 *
+	 * B2_NEAR_CHAN_MIX_REG_MASK values from T-Spec
+	 * 000 : 0 kHz mix.
+	 * 001 : +100 kHz mix.
+	 * 010 : +200 kHz mix.
+	 * 011 : +300 kHz mix.
+	 * 100 : -400 kHz mix.
+	 * 101 : -300 kHz mix.
+	 * 110 : -200 kHz mix.
+	 * 111 : -100 kHz mix.
+	 */
+
+	/* get near channel amplitude */
+	ret = stfm1000_write_masked(stfm1000, STFM1000_INITIALIZATION3,
+		STFM1000_B2_NEAR_CHAN_MIX(0x01),
+		STFM1000_B2_NEAR_CHAN_MIX_MASK);
+	if (ret != 0)
+		return ret;
+
+	msleep(10);	/* wait for the signal quality to settle */
+
+	ret = stfm1000_read(stfm1000, STFM1000_SIGNALQUALITY, &tmp);
+	if (ret != 0)
+		return ret;
+
+	sig_qual = (tmp & STFM1000_NEAR_CHAN_AMPLITUDE_MASK) >>
+		STFM1000_NEAR_CHAN_AMPLITUDE_SHIFT;
+
+	bypass_setting = 0;
+
+	/* check near channel amplitude vs threshold */
+	if (sig_qual < stfm1000->adj_chan_th) {
+		/* get near channel amplitude again */
+		ret = stfm1000_write_masked(stfm1000, STFM1000_INITIALIZATION3,
+			STFM1000_B2_NEAR_CHAN_MIX(0x05),
+			STFM1000_B2_NEAR_CHAN_MIX_MASK);
+		if (ret != 0)
+			return ret;
+
+		msleep(10);	/* wait for the signal quality to settle */
+
+		ret = stfm1000_read(stfm1000, STFM1000_SIGNALQUALITY, &tmp);
+		if (ret != 0)
+			return ret;
+
+		sig_qual = (tmp & STFM1000_NEAR_CHAN_AMPLITUDE_MASK) >>
+			STFM1000_NEAR_CHAN_AMPLITUDE_SHIFT;
+
+		if (sig_qual < stfm1000->adj_chan_th)
+			bypass_setting = 2;
+	}
+
+	/* set filter settings */
+	ret = stfm1000_write_masked(stfm1000, STFM1000_INITIALIZATION1,
+		STFM1000_B2_BYPASS_FILT(bypass_setting),
+		STFM1000_B2_BYPASS_FILT_MASK);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static int SD_Look_For_Pilot_TA2(struct stfm1000 *stfm1000)
+{
+	int i;
+	u32 pilot;
+	int ret;
+
+	/* assume pilot */
+	stfm1000->pilot_present = 1;
+
+	for (i = 0; i < 3; i++) {
+
+		ret = stfm1000_read(stfm1000, STFM1000_PILOTCORRECTION,
+			&pilot);
+		if (ret != 0)
+			return ret;
+
+		pilot &= STFM1000_PILOTEST_TA2_MASK;
+		pilot >>= STFM1000_PILOTEST_TA2_SHIFT;
+
+		/* out of range? */
+		if (pilot < 0xe2 || pilot >= 0xb5) {
+			stfm1000->pilot_present = 0;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+
+static int SD_Look_For_Pilot_TB2(struct stfm1000 *stfm1000)
+{
+	int i;
+	u32 pilot;
+	int ret;
+
+	/* assume pilot */
+	stfm1000->pilot_present = 1;
+
+	for (i = 0; i < 3; i++) {
+
+		ret = stfm1000_read(stfm1000, STFM1000_PILOTCORRECTION,
+			&pilot);
+		if (ret != 0)
+			return ret;
+
+		pilot &= STFM1000_PILOTEST_TB2_MASK;
+		pilot >>= STFM1000_PILOTEST_TB2_SHIFT;
+
+		/* out of range? */
+		if (pilot < 0x1e || pilot >= 0x7f) {
+			stfm1000->pilot_present = 0;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int SD_Look_For_Pilot(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	if (stfm1000->revid == STFM1000_CHIP_REV_TA2)
+		ret = SD_Look_For_Pilot_TA2(stfm1000);
+	else
+		ret = SD_Look_For_Pilot_TB2(stfm1000);
+
+	if (ret != 0)
+		return ret;
+
+	if (!stfm1000->pilot_present) {
+		ret = stfm1000_clear_bits(stfm1000, STFM1000_PILOTTRACKING,
+			STFM1000_B2_PILOTTRACKING_EN);
+		if (ret != 0)
+			return ret;
+
+		/* set force mono parameters for the filter */
+		stfm1000->filter_parms.pCoefForcedMono = 1;
+
+		/* yeah, I know, it's stupid */
+		stfm1000->rds_state.demod.pCoefForcedMono =
+			stfm1000->filter_parms.pCoefForcedMono;
+	}
+
+	return 0;
+}
+
+static int SD_Gear_Shift_Pilot_Tracking(struct stfm1000 *stfm1000)
+{
+	static const struct {
+		int delay;
+		u32 value;
+	} track_table[] = {
+		{ .delay = 10, .value = 0x81b6 },
+		{ .delay =  6, .value = 0x82a5 },
+		{ .delay =  6, .value = 0x8395 },
+		{ .delay =  8, .value = 0x8474 },
+		{ .delay = 20, .value = 0x8535 },
+		{ .delay = 50, .value = 0x8632 },
+		{ .delay =  0, .value = 0x8810 },
+	};
+	int i;
+	int ret;
+
+	for (i = 0; i < ARRAY_SIZE(track_table); i++) {
+		ret = stfm1000_write(stfm1000, STFM1000_PILOTTRACKING,
+			track_table[i].value);
+		if (ret != 0)
+			return ret;
+
+		if (i < ARRAY_SIZE(track_table) - 1)	/* last one no delay */
+			msleep(track_table[i].delay);
+	}
+
+	return 0;
+}
+
+static int SD_Optimize_Channel(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	ret = stfm1000_set_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		return ret;
+
+	ret = stfm1000_write(stfm1000, STFM1000_PILOTTRACKING,
+		STFM1000_B2_PILOTTRACKING_EN |
+		STFM1000_B2_PILOTLPF_TIMECONSTANT(0x01) |
+		STFM1000_B2_PFDSCALE(0x0B) |
+		STFM1000_B2_PFDFILTER_SPEEDUP(0x06));	/* 0x000081B6 */
+	if (ret != 0)
+		return ret;
+
+	ret = SD_Set_Channel_Filter(stfm1000);
+	if (ret != 0)
+		return ret;
+
+	ret = SD_Look_For_Pilot(stfm1000);
+	if (ret != 0)
+		return ret;
+
+	if (stfm1000->pilot_present) {
+		ret = SD_Gear_Shift_Pilot_Tracking(stfm1000);
+		if (ret != 0)
+			return ret;
+	}
+
+	ret = stfm1000_clear_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static int Monitor_STFM_Quality(struct stfm1000 *stfm1000)
+{
+	u32 tmp, rssi_dc_est, tone_data;
+	u32 lna_rms, bias, agc_out, lna_th, lna, ref;
+	u16 rssi_mantissa, rssi_exponent, rssi_decoded;
+	u16 prssi;
+	s16 mpx_dc;
+	int rssi_log;
+	int bypass_filter;
+	int ret;
+
+	ret = stfm1000_set_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		return ret;
+
+	/* Get Rssi register readings from STFM1000 */
+	stfm1000_read(stfm1000, STFM1000_RSSI_TONE, &tmp);
+	rssi_dc_est = tmp & 0xffff;
+	tone_data = (tmp >> 16) & 0x0fff;
+
+	rssi_mantissa = (rssi_dc_est & 0xffe0) >> 5;	/* 11Msb */
+	rssi_exponent = rssi_dc_est & 0x001f;	/* 5 lsb */
+	rssi_decoded = (u32)rssi_mantissa << rssi_exponent;
+
+	/* Convert Rsst to 10log(Rssi) */
+	for (prssi = 20; prssi > 0; prssi--)
+		if (rssi_decoded >= (1 << prssi))
+			break;
+
+	rssi_log = (3 * rssi_decoded >> prssi) + (3 * prssi - 3);
+	/* clamp to positive */
+	if (rssi_log < 0)
+		rssi_log = 0;
+	/* Compensate for errors in truncation/approximation by adding 1 */
+	rssi_log++;
+
+	stfm1000->rssi_dc_est_log = rssi_log;
+	stfm1000->signal_strength = stfm1000->rssi_dc_est_log;
+
+	/* determine absolute value */
+	if (tmp & 0x0800)
+		mpx_dc = ((tmp >> 16) & 0x0fff) | 0xf000;
+	else
+		mpx_dc = (tmp >> 16) & 0x0fff;
+	stfm1000->mpx_dc = mpx_dc;
+	mpx_dc = mpx_dc < 0 ? -mpx_dc : mpx_dc;
+
+	if (stfm1000->tuning_grid_50KHz)
+		stfm1000->is_station = rssi_log > stfm1000->tune_rssi_th;
+	else
+		stfm1000->is_station = rssi_log > stfm1000->tune_rssi_th &&
+			mpx_dc > stfm1000->tune_mpx_dc_th;
+
+	/* weak signal? */
+	if (stfm1000->rssi_dc_est_log <
+		(stfm1000->filter_parms.pCoefLmrGaTh - 20)) {
+
+		if (stfm1000->pilot_present)
+			bypass_filter = 1;	/* Filter settings #2 */
+		else
+			bypass_filter = 0;
+
+		/* configure filter for narrow band */
+		ret = stfm1000_write_masked(stfm1000, STFM1000_AGC_CONTROL1,
+				STFM1000_B2_BYPASS_FILT(bypass_filter),
+				STFM1000_B2_BYPASS_FILT_MASK);
+		if (ret != 0)
+			return ret;
+
+		/* Turn off pilot tracking */
+		ret = stfm1000_clear_bits(stfm1000, STFM1000_PILOTTRACKING,
+				STFM1000_B2_PILOTTRACKING_EN);
+		if (ret != 0)
+			return ret;
+
+		/* enable "forced mono" in black box */
+		stfm1000->filter_parms.pCoefForcedMono = 1;
+
+		/* yeah, I know, it's stupid */
+		stfm1000->rds_state.demod.pCoefForcedMono =
+			stfm1000->filter_parms.pCoefForcedMono;
+
+		/* Set weak signal flag */
+		stfm1000->weak_signal = 1;
+
+		if (stfm1000->revid == STFM1000_CHIP_REV_TA2) {
+
+			/* read AGC_STAT register */
+			ret = stfm1000_read(stfm1000, STFM1000_AGC_STAT, &tmp);
+			if (ret != 0)
+				return ret;
+
+			lna_rms = (tmp & STFM1000_LNA_RMS_MASK) >>
+				STFM1000_LNA_RMS_SHIFT;
+
+			/* Check  the energy level from LNA Power Meter A/D */
+			if (lna_rms == 0)
+				bias = STFM1000_IBIAS2_DN | STFM1000_IBIAS1_UP;
+			else
+				bias = STFM1000_IBIAS2_UP | STFM1000_IBIAS1_DN;
+
+			if (lna_rms == 0 || lna_rms > 2) {
+				ret = stfm1000_write_masked(stfm1000,
+					STFM1000_LNA, bias,
+					STFM1000_IBIAS2_UP |
+					STFM1000_IBIAS2_DN |
+					STFM1000_IBIAS1_UP |
+					STFM1000_IBIAS1_DN);
+				if (ret != 0)
+					return ret;
+			}
+
+		} else {
+
+			/* Set LNA bias */
+
+			/* read AGC_STAT register */
+			ret = stfm1000_read(stfm1000, STFM1000_AGC_STAT, &tmp);
+			if (ret != 0)
+				return ret;
+
+			agc_out = (tmp & STFM1000_AGCOUT_STAT_MASK) >>
+					STFM1000_AGCOUT_STAT_SHIFT;
+
+			/* read LNA register (this is a cached register) */
+			ret = stfm1000_read(stfm1000, STFM1000_LNA, &lna);
+			if (ret != 0)
+				return ret;
+
+			/* read REF register (this is a cached register) */
+			ret = stfm1000_read(stfm1000, STFM1000_REF, &ref);
+			if (ret != 0)
+				return ret;
+
+/* work around the 80 line width problem */
+#undef LNADEF
+#define LNADEF STFM1000_LNA_AMP1_IMPROVE_DISTORTION
+			if (agc_out == 31) {
+				if (rssi_log <= 16) {
+					if (lna & STFM1000_IBIAS1_DN)
+						lna &= ~STFM1000_IBIAS1_DN;
+					else {
+						lna |=  STFM1000_IBIAS1_UP;
+						ref &= ~LNADEF;
+					}
+				}
+				if (rssi_log >= 26) {
+					if (lna & STFM1000_IBIAS1_UP) {
+						lna &= ~STFM1000_IBIAS1_UP;
+						ref |=  LNADEF;
+					} else
+						lna |=  STFM1000_IBIAS1_DN;
+				}
+			} else {
+				lna &= ~STFM1000_IBIAS1_UP;
+				lna |=  STFM1000_IBIAS1_DN;
+				ref |=  LNADEF;
+			}
+#undef LNADEF
+
+			ret = stfm1000_write_masked(stfm1000, STFM1000_LNA,
+				lna, STFM1000_IBIAS1_UP | STFM1000_IBIAS1_DN);
+			if (ret != 0)
+				return ret;
+
+			ret = stfm1000_write_masked(stfm1000, STFM1000_REF,
+				ref, STFM1000_LNA_AMP1_IMPROVE_DISTORTION);
+			if (ret != 0)
+				return ret;
+		}
+
+	} else if (stfm1000->rssi_dc_est_log >
+		(stfm1000->filter_parms.pCoefLmrGaTh - 17)) {
+
+			bias = STFM1000_IBIAS2_UP | STFM1000_IBIAS1_DN;
+
+			ret = stfm1000_write_masked(stfm1000, STFM1000_LNA,
+				bias, STFM1000_IBIAS2_UP | STFM1000_IBIAS2_DN |
+				STFM1000_IBIAS1_UP | STFM1000_IBIAS1_DN);
+			if (ret != 0)
+				return ret;
+
+			ret = SD_Set_Channel_Filter(stfm1000);
+			if (ret != 0)
+				return ret;
+
+			ret = SD_Look_For_Pilot(stfm1000);
+			if (ret != 0)
+				return ret;
+
+			if (stfm1000->pilot_present) {
+				if (stfm1000->prev_pilot_present ||
+					stfm1000->weak_signal) {
+
+					/* gear shift pilot tracking */
+					ret = SD_Gear_Shift_Pilot_Tracking(
+						stfm1000);
+					if (ret != 0)
+						return ret;
+
+					/* set force mono parameters for the
+					 * filter */
+					stfm1000->filter_parms.
+						pCoefForcedMono = stfm1000->
+							force_mono;
+
+					/* yeah, I know, it's stupid */
+					stfm1000->rds_state.demod.
+						pCoefForcedMono = stfm1000->
+							filter_parms.
+							pCoefForcedMono;
+				}
+			} else {
+				ret = stfm1000_clear_bits(stfm1000,
+					STFM1000_PILOTTRACKING,
+					STFM1000_B2_PILOTTRACKING_EN);
+				if (ret != 0)
+					return ret;
+
+				/* set force mono parameters for the filter */
+				stfm1000->filter_parms.pCoefForcedMono = 1;
+
+				/* yeah, I know, it's stupid */
+				stfm1000->rds_state.demod.pCoefForcedMono =
+					stfm1000->filter_parms.pCoefForcedMono;
+			}
+
+			/* Reset weak signal flag */
+			stfm1000->weak_signal = 0;
+			stfm1000->prev_pilot_present = stfm1000->pilot_present;
+
+	} else {
+
+		ret = SD_Look_For_Pilot(stfm1000);
+		if (ret != 0)
+			return ret;
+
+		if (!stfm1000->pilot_present) {
+			ret = stfm1000_clear_bits(stfm1000,
+				STFM1000_PILOTTRACKING,
+				STFM1000_B2_PILOTTRACKING_EN);
+			if (ret != 0)
+				return ret;
+
+			/* set force mono parameters for the filter */
+			stfm1000->filter_parms.pCoefForcedMono = 1;
+
+			/* yeah, I know, it's stupid */
+			stfm1000->rds_state.demod.pCoefForcedMono =
+				stfm1000->filter_parms.pCoefForcedMono;
+
+			/* Reset weak signal flag */
+			stfm1000->weak_signal = 0;
+			stfm1000->prev_pilot_present = stfm1000->pilot_present;
+		}
+
+	}
+
+	if (stfm1000->revid == STFM1000_CHIP_REV_TA2) {
+
+		/* read AGC_STAT register */
+		ret = stfm1000_read(stfm1000, STFM1000_AGC_STAT, &tmp);
+		if (ret != 0)
+			return ret;
+
+		agc_out = (tmp & STFM1000_AGCOUT_STAT_MASK) >>
+			STFM1000_AGCOUT_STAT_SHIFT;
+		lna_rms = (tmp & STFM1000_LNA_RMS_MASK) >>
+			STFM1000_LNA_RMS_SHIFT;
+
+		ret = stfm1000_read(stfm1000, STFM1000_AGC_CONTROL1, &tmp);
+		if (ret != 0)
+			return ret;
+
+		/* extract LNATH */
+		lna_th = (tmp & STFM1000_B2_LNATH_MASK) >>
+			STFM1000_B2_LNATH_SHIFT;
+
+		if (lna_rms > lna_th && agc_out <= 1) {
+
+			ret = stfm1000_write_masked(stfm1000, STFM1000_LNA,
+				STFM1000_USEATTEN(1), STFM1000_USEATTEN_MASK);
+			if (ret != 0)
+				return ret;
+
+		} else if (agc_out > 15) {
+
+			ret = stfm1000_write_masked(stfm1000, STFM1000_LNA,
+				STFM1000_USEATTEN(0), STFM1000_USEATTEN_MASK);
+			if (ret != 0)
+				return ret;
+		}
+	}
+
+	/* disable buffered writes */
+	ret = stfm1000_clear_bits(stfm1000, STFM1000_DATAPATH,
+		STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		return ret;
+
+	return ret;
+}
+
+static int Is_Station(struct stfm1000 *stfm1000)
+{
+	u32 tmp, rssi_dc_est, tone_data;
+	u16 rssi_mantissa, rssi_exponent, rssi_decoded;
+	u16 prssi;
+	s16 mpx_dc;
+	int rssi_log;
+
+	/* Get Rssi register readings from STFM1000 */
+	stfm1000_read(stfm1000, STFM1000_RSSI_TONE, &tmp);
+	rssi_dc_est = tmp & 0xffff;
+	tone_data = (tmp >> 16) & 0x0fff;
+
+	rssi_mantissa = (rssi_dc_est & 0xffe0) >> 5;	/* 11Msb */
+	rssi_exponent = rssi_dc_est & 0x001f;	/* 5 lsb */
+	rssi_decoded = (u32)rssi_mantissa << rssi_exponent;
+
+	/* Convert Rsst to 10log(Rssi) */
+	for (prssi = 20; prssi > 0; prssi--)
+		if (rssi_decoded >= (1 << prssi))
+			break;
+
+	rssi_log = (3 * rssi_decoded >> prssi) + (3 * prssi - 3);
+	/* clamp to positive */
+	if (rssi_log < 0)
+		rssi_log = 0;
+	/* Compensate for errors in truncation/approximation by adding 1 */
+	rssi_log++;
+
+	stfm1000->rssi_dc_est_log = rssi_log;
+	stfm1000->signal_strength = stfm1000->rssi_dc_est_log;
+
+	/* determine absolute value */
+	if (tmp & 0x0800)
+		mpx_dc = ((tmp >> 16) & 0x0fff) | 0xf000;
+	else
+		mpx_dc = (tmp >> 16) & 0x0fff;
+	stfm1000->mpx_dc = mpx_dc;
+	mpx_dc = mpx_dc < 0 ? -mpx_dc : mpx_dc;
+
+	if (stfm1000->tuning_grid_50KHz)
+		stfm1000->is_station = rssi_log > stfm1000->tune_rssi_th;
+	else
+		stfm1000->is_station = rssi_log > stfm1000->tune_rssi_th &&
+			mpx_dc > stfm1000->tune_mpx_dc_th;
+
+	return 0;
+}
+
+int Monitor_STFM_AGC(struct stfm1000 *stfm1000)
+{
+	/* we don't do any AGC for now */
+	return 0;
+}
+
+static int Take_Down(struct stfm1000 *stfm1000)
+{
+	Mute_Audio(stfm1000);
+
+	DRI_Off(stfm1000);
+
+	SD_DP_Off(stfm1000);
+
+	return 0;
+}
+
+static int Bring_Up(struct stfm1000 *stfm1000)
+{
+	SD_DP_On(stfm1000);
+
+	SD_Optimize_Channel(stfm1000);
+
+	DRI_On(stfm1000);
+
+	Unmute_Audio(stfm1000);
+
+	if (stfm1000->rds_enable)
+		stfm1000_rds_reset(&stfm1000->rds_state);
+
+	stfm1000->rds_sync = stfm1000->rds_enable; /* force sync (if RDS) */
+	stfm1000->rds_demod_running = 0;
+	stfm1000->rssi_dc_est_log = 0;
+	stfm1000->signal_strength = 0;
+
+	stfm1000->next_quality_monitor = jiffies + msecs_to_jiffies(
+		stfm1000->quality_monitor_period);
+	stfm1000->next_agc_monitor = jiffies + msecs_to_jiffies(
+		stfm1000->agc_monitor_period);
+	stfm1000->rds_pkt_bad = 0;
+	stfm1000->rds_pkt_good = 0;
+	stfm1000->rds_pkt_recovered = 0;
+	stfm1000->rds_pkt_lost_sync = 0;
+	stfm1000->rds_bit_overruns = 0;
+
+	return 0;
+}
+
+/* These are not used yet */
+
+static int Lock_Station(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	ret = SD_Optimize_Channel(stfm1000);
+	if (ret != 0)
+		return ret;
+
+	/* AGC monitor start? */
+
+	return ret;
+}
+
+static const struct stfm1000_reg sd_unlock_regs[] = {
+	STFM1000_REG_SETBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_REG_CLRBITS(PILOTTRACKING, STFM1000_B2_PILOTTRACKING_EN),
+	STFM1000_REG_CLRBITS(DATAPATH, STFM1000_DB_ACCEPT),
+	STFM1000_END,
+};
+
+static int Unlock_Station(struct stfm1000 *stfm1000)
+{
+	int ret;
+
+	ret = stfm1000_write_regs(stfm1000, sd_unlock_regs);
+	return ret;
+}
+
+irqreturn_t stfm1000_dri_dma_irq(int irq, void *dev_id)
+{
+	struct stfm1000 *stfm1000 = dev_id;
+	u32 err_mask, irq_mask;
+	u32 ctrl;
+	int handled = 0;
+
+#ifdef CONFIG_ARCH_STMP37XX
+	err_mask = 1 << (16 + stfm1000->dma_ch);
+#endif
+#ifdef CONFIG_ARCH_STMP378X
+	err_mask = 1 << stfm1000->dma_ch;
+#endif
+	irq_mask = 1 << stfm1000->dma_ch;
+
+#ifdef CONFIG_ARCH_STMP37XX
+	ctrl = HW_APBX_CTRL1_RD();
+#endif
+#ifdef CONFIG_ARCH_STMP378X
+	ctrl = HW_APBX_CTRL2_RD();
+#endif
+
+	if (ctrl & err_mask) {
+		handled = 1;
+		printk(KERN_WARNING "%s: DMA audio channel %d error\n",
+			__func__, stfm1000->dma_ch);
+#ifdef CONFIG_ARCH_STMP37XX
+		HW_APBX_CTRL1_CLR(err_mask);
+#endif
+#ifdef CONFIG_ARCH_STMP378X
+		HW_APBX_CTRL2_CLR(err_mask);
+#endif
+	}
+
+	if (HW_APBX_CTRL1_RD() & irq_mask) {
+		handled = 1;
+		stmp3xxx_dma_clear_interrupt(stfm1000->dma_ch);
+
+		if (stfm1000->alsa_initialized) {
+			BUG_ON(stfm1000_alsa_ops->dma_irq == NULL);
+			(*stfm1000_alsa_ops->dma_irq)(stfm1000);
+		}
+	}
+
+	return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+EXPORT_SYMBOL(stfm1000_dri_dma_irq);
+
+irqreturn_t stfm1000_dri_attn_irq(int irq, void *dev_id)
+{
+	struct stfm1000 *stfm1000 = dev_id;
+	int handled = 1;
+	u32 mask;
+
+	(void)stfm1000;
+	mask = HW_DRI_CTRL_RD();
+	mask &= BM_DRI_CTRL_OVERFLOW_IRQ | BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ |
+		BM_DRI_CTRL_ATTENTION_IRQ;
+
+	HW_DRI_CTRL_CLR(mask);
+
+	printk(KERN_INFO "DRI_ATTN:%s%s%s\n",
+			(mask & BM_DRI_CTRL_OVERFLOW_IRQ) ? " OV" : "",
+			(mask & BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ) ? " SL" : "",
+			(mask & BM_DRI_CTRL_ATTENTION_IRQ) ? " AT" : "");
+
+	if (stfm1000->alsa_initialized) {
+		BUG_ON(stfm1000_alsa_ops->attn_irq == NULL);
+		(*stfm1000_alsa_ops->attn_irq)(stfm1000);
+	}
+
+	return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+EXPORT_SYMBOL(stfm1000_dri_attn_irq);
+
+void stfm1000_decode_block(struct stfm1000 *stfm1000, const s16 *src, s16 *dst,
+	int count)
+{
+	int i;
+
+	if (stfm1000->mute) {
+		memset(dst, 0, count * sizeof(s16) * 2);
+		return;
+
+	}
+
+	for (i = 0; i < count; i++, dst += 2, src += 4) {
+
+		stfm1000_filter_decode(&stfm1000->filter_parms,
+			src[0],	src[1], src[2]);
+
+		dst[0] = stfm1000_filter_value_left(&stfm1000->filter_parms);
+		dst[1] = stfm1000_filter_value_right(&stfm1000->filter_parms);
+	}
+
+	stfm1000->rssi = stfm1000->filter_parms.RssiDecoded;
+	stfm1000->stereo = stfm1000->pilot_present &&
+		!stfm1000->filter_parms.pCoefForcedMono;
+
+	/* RDS processing */
+	if (stfm1000->rds_demod_running) {
+		/* rewind */
+		src -= count * 4;
+		stfm1000_rds_demod(&stfm1000->rds_state, src, count);
+	}
+
+}
+EXPORT_SYMBOL(stfm1000_decode_block);
+
+void stfm1000_take_down(struct stfm1000 *stfm1000)
+{
+	mutex_lock(&stfm1000->state_lock);
+	stfm1000->active = 0;
+	Take_Down(stfm1000);
+	mutex_unlock(&stfm1000->state_lock);
+}
+EXPORT_SYMBOL(stfm1000_take_down);
+
+void stfm1000_bring_up(struct stfm1000 *stfm1000)
+{
+	mutex_lock(&stfm1000->state_lock);
+
+	stfm1000->active = 1;
+
+	stfm1000_filter_reset(&stfm1000->filter_parms);
+
+	Bring_Up(stfm1000);
+
+	mutex_unlock(&stfm1000->state_lock);
+}
+EXPORT_SYMBOL(stfm1000_bring_up);
+
+void stfm1000_tune_current(struct stfm1000 *stfm1000)
+{
+	mutex_lock(&stfm1000->state_lock);
+	sw_tune(stfm1000, stfm1000->freq);
+	mutex_unlock(&stfm1000->state_lock);
+}
+EXPORT_SYMBOL(stfm1000_tune_current);
+
+/* Alternate ZIF Tunings to avoid EMI */
+const struct stfm1000_tune1
+stfm1000_board_emi_tuneups[STFM1000_FREQUENCY_100KHZ_RANGE] = {
+#undef TUNE_ENTRY
+#define TUNE_ENTRY(f, t1, sd) \
+	[(f) - STFM1000_FREQUENCY_100KHZ_MIN] = \
+		{ .tune1 = (t1), .sdnom = (sd) }
+	TUNE_ENTRY(765, 0x84030, 0x1BF5E50D),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(780, 0x84240, 0x1BA5162F),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(795, 0x84250, 0x1C2D2F39),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(810, 0x84460, 0x1BDD207E),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(825, 0x84470, 0x1C6138CD),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(839, 0xC4680, 0x1C11F704),	/* 061215 Jon, IF +100kHz */
+	TUNE_ENTRY(840, 0x84680, 0x1c11f704),
+	TUNE_ENTRY(855, 0x84890, 0x1BC71C71),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(870, 0x848A0, 0x1C43DE10),	/* 061215 Jon, IF +0kHz */
+	TUNE_ENTRY(885, 0x84AB0, 0x1BF9B021),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(899, 0xC4CC0, 0x1BB369A9),	/* 061025 Arthur, IF +100kHz */
+	TUNE_ENTRY(900, 0x84CC0, 0x1BB369A9),	/* 061025 Arthur, IF 0kHz */
+	TUNE_ENTRY(915, 0x84CD0, 0x1C299A5B),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(930, 0x84ee0, 0x1be3e6aa),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(945, 0x84ef0, 0x1c570f8b),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(959, 0xC5100, 0x1c11f704),
+	TUNE_ENTRY(960, 0x85100, 0x1c11f704),
+	TUNE_ENTRY(975, 0x85310, 0x1bd03d57),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(990, 0x85320, 0x1c3dc822),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(1005, 0x85530, 0x1bfc93ff),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(1019, 0xC5740, 0x1BBE683C),	/* 061025 Arthur, IF +100kHz */
+	TUNE_ENTRY(1020, 0x85740, 0x1bbe683c),	/* 061025 Arthur, IF +0kHz */
+	TUNE_ENTRY(1035, 0x85750, 0x1c26dab6),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(1050, 0x85960, 0x1be922b4),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(1065, 0x85970, 0x1c4f357c),	/* 061101 Arthur, IF +0kHz */
+	TUNE_ENTRY(1079, 0xC5B80, 0x1c11f704),
+	TUNE_ENTRY(1080, 0x85B80, 0x1c11f704),
+#undef TUNE_ENTRY
+};
+
+static const struct stfm1000_tune1 *stfm1000_board_emi_tune(int freq100)
+{
+	const struct stfm1000_tune1 *tune1;
+
+	if ((unsigned int)(freq100 - STFM1000_FREQUENCY_100KHZ_MIN) >=
+			STFM1000_FREQUENCY_100KHZ_RANGE)
+		return NULL;
+
+	tune1 = &stfm1000_board_emi_tuneups[freq100 -
+		STFM1000_FREQUENCY_100KHZ_MIN];
+	if (tune1->tune1 == 0 && tune1->sdnom == 0)
+		return NULL;
+	return tune1;
+}
+
+/* freq in kHz */
+static int sw_tune(struct stfm1000 *stfm1000, u32 freq)
+{
+	u32 freq100 = freq / 100;
+	int tune_cap;
+	int i2s_clock;
+	int mix_reg;
+	int if_freq, fe_freq;
+	u32 tune1, sdnom, agc1;
+	const struct stfm1000_tune1 *tp;
+	int ret;
+
+	if_freq = 0;
+	mix_reg = 1;
+	switch (mix_reg) {
+	case 0: if_freq = -2; break;
+	case 1: if_freq = -1; break;
+	case 2: if_freq =  0; break;
+	case 3: if_freq =  1; break;
+	case 4: if_freq =  2; break;
+	}
+
+	/* handle board specific EMI tuning */
+	tp = stfm1000_board_emi_tune(freq100);
+	if (tp != NULL) {
+		tune1 = tp->tune1;
+		sdnom = tp->sdnom;
+	} else {
+		fe_freq = freq100 + if_freq;
+
+		/* clamp into range */
+		if (fe_freq < STFM1000_FREQUENCY_100KHZ_MIN)
+			fe_freq = STFM1000_FREQUENCY_100KHZ_MIN;
+		else if (fe_freq > STFM1000_FREQUENCY_100KHZ_MAX)
+			fe_freq = STFM1000_FREQUENCY_100KHZ_MAX;
+
+		tp = &stfm1000_tune1_table[fe_freq -
+			STFM1000_FREQUENCY_100KHZ_MIN];
+
+		/* bits [14:0], [20:18] */
+		tune1 = (tp->tune1 & 0x7fff) | (mix_reg << 18);
+		sdnom = tp->sdnom;
+	}
+
+	agc1 = stfm1000->revid == STFM1000_CHIP_REV_TA2 ? 0x0400 : 0x2200;
+
+	ret = stfm1000_write_masked(stfm1000, STFM1000_AGC_CONTROL1,
+			agc1, 0x3f00);
+	if (ret != 0)
+		goto err;
+
+	ret = stfm1000_write_masked(stfm1000, STFM1000_TUNE1, tune1,
+		0xFFFF7FFF);	/* do not set bit-15 */
+	if (ret != 0)
+		goto err;
+
+	/* keep this around */
+	stfm1000->sdnominal_pivot = sdnom;
+
+	ret = stfm1000_write(stfm1000, STFM1000_SDNOMINAL, sdnom);
+	if (ret != 0)
+		goto err;
+
+	/* fix for seek-not-stopping on alternate tunings */
+	ret = stfm1000_set_bits(stfm1000, STFM1000_DATAPATH,
+			STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		goto err;
+
+	ret = stfm1000_clear_bits(stfm1000, STFM1000_DATAPATH,
+			STFM1000_DB_ACCEPT);
+	if (ret != 0)
+		goto err;
+
+	ret = stfm1000_set_bits(stfm1000, STFM1000_INITIALIZATION2,
+			STFM1000_DRI_CLK_EN);
+	if (ret != 0)
+		goto err;
+
+	/* 6MHz spur fix */
+	if ((freq100 >=  778 && freq100 <=  782) ||
+	    (freq100 >=  838 && freq100 <=  842) ||
+	    (freq100 >=  898 && freq100 <=  902) ||
+	    (freq100 >=  958 && freq100 <=  962) ||
+	    (freq100 >= 1018 && freq100 <= 1022) ||
+	    (freq100 >= 1078 && freq100 <= 1080))
+		i2s_clock = 5;  /* 4.8MHz */
+	else
+		i2s_clock = 4;
+
+	ret = stfm1000_write_masked(stfm1000, STFM1000_DATAPATH,
+		STFM1000_SAI_CLK_DIV(i2s_clock), STFM1000_SAI_CLK_DIV_MASK);
+	if (ret != 0)
+		goto err;
+
+	ret = stfm1000_set_bits(stfm1000, STFM1000_INITIALIZATION2,
+		STFM1000_DRI_CLK_EN);
+	if (ret != 0)
+		goto err;
+
+	if (tune1 & 0xf)
+		ret = stfm1000_set_bits(stfm1000, STFM1000_CLK1,
+			STFM1000_ENABLE_TAPDELAYFIX);
+	else
+		ret = stfm1000_clear_bits(stfm1000, STFM1000_CLK1,
+			STFM1000_ENABLE_TAPDELAYFIX);
+
+	if (ret != 0)
+		goto err;
+
+	tune_cap = (int)(stfm1000->tune_cap_a_f -
+		stfm1000->tune_cap_b_f * freq100);
+	if (tune_cap < 4)
+		tune_cap = 4;
+	ret = stfm1000_write_masked(stfm1000, STFM1000_LNA,
+		STFM1000_ANTENNA_TUNECAP(tune_cap),
+		STFM1000_ANTENNA_TUNECAP_MASK);
+	if (ret != 0)
+		goto err;
+
+	/* set signal strenth to 0 */
+	/* stfm1000_dcdc_update(); */
+
+	/* cmp_rds_setRdsStatus(0) */
+	/* cmp_rds_ResetGroupCallbacks(); */
+	stfm1000->freq = freq;
+
+	return 0;
+err:
+	return -1;
+}
+
+static const struct v4l2_queryctrl radio_qctrl[] = {
+	{
+		.id		= V4L2_CID_AUDIO_MUTE,
+		.name		= "Mute",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 1,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+	},
+};
+
+static int vidioc_querycap(struct file *file, void *priv,
+				struct v4l2_capability *v)
+{
+	strlcpy(v->driver, "radio-stfm1000", sizeof(v->driver));
+	strlcpy(v->card, "STFM1000 Radio", sizeof(v->card));
+	sprintf(v->bus_info, "i2c");
+	v->version = KERNEL_VERSION(0, 0, 1);
+	v->capabilities = V4L2_CAP_TUNER;
+	return 0;
+}
+
+static int vidioc_g_tuner(struct file *file, void *priv,
+				struct v4l2_tuner *v)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+	u32 tmp, rssi_dc_est, tone_data;
+	u16 rssi_mantissa, rssi_exponent, rssi_decoded;
+	u16 prssi;
+	s16 mpx_dc;
+	int rssi_log;
+	int ret;
+
+	if (v->index > 0)
+		return -EINVAL;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	strcpy(v->name, "FM");
+	v->type = V4L2_TUNER_RADIO;
+	v->rangelow = (u32)(87.5 * 16000);
+	v->rangehigh = (u32)(108 * 16000);
+	v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
+	v->capability = V4L2_TUNER_CAP_LOW;
+	v->audmode = V4L2_TUNER_MODE_STEREO;
+	v->signal = 0; /* tr_getsigstr(); */
+
+	msleep(50);
+
+	ret = stfm1000_read(stfm1000, STFM1000_RSSI_TONE, &tmp);
+	if (ret != 0)
+		goto out;
+
+	rssi_dc_est = tmp & 0xffff;
+	tone_data = (tmp >> 16) & 0x0fff;
+
+	rssi_mantissa = (rssi_dc_est & 0xffe0) >> 5;	/* 11Msb */
+	rssi_exponent = rssi_dc_est & 0x001f;	/* 5 lsb */
+	rssi_decoded = (u32)rssi_mantissa << rssi_exponent;
+
+	/* Convert Rsst to 10log(Rssi) */
+	for (prssi = 20; prssi > 0; prssi--)
+		if (rssi_decoded >= (1 << prssi))
+			break;
+
+	rssi_log = (3 * rssi_decoded >> prssi) + (3 * prssi - 3);
+	/* clamp to positive */
+	if (rssi_log < 0)
+		rssi_log = 0;
+	/* Compensate for errors in truncation/approximation by adding 1 */
+	rssi_log++;
+
+	stfm1000->rssi_dc_est_log = rssi_log;
+	stfm1000->signal_strength = stfm1000->rssi_dc_est_log;
+
+	/* determine absolute value */
+	if (tmp & 0x0800)
+		mpx_dc = ((tmp >> 16) & 0x0fff) | 0xf000;
+	else
+		mpx_dc = (tmp >> 16) & 0x0fff;
+	stfm1000->mpx_dc = mpx_dc;
+	mpx_dc = mpx_dc < 0 ? -mpx_dc : mpx_dc;
+
+	v->signal = rssi_decoded & 0xffff;
+
+out:
+	mutex_unlock(&stfm1000->state_lock);
+
+	return ret;
+}
+
+static int vidioc_s_tuner(struct file *file, void *priv,
+				struct v4l2_tuner *v)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	(void)stfm1000;
+
+	if (v->index > 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int vidioc_s_frequency(struct file *file, void *priv,
+				struct v4l2_frequency *f)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	mutex_lock(&stfm1000->state_lock);
+
+	/* convert from the crazy linux value to our decimal based values */
+	stfm1000->freq = (u32)div_u64((u64)(125 * (u64)f->frequency), 2000);
+
+	if (stfm1000->active)
+		Take_Down(stfm1000);
+
+	sw_tune(stfm1000, stfm1000->freq);
+
+	if (stfm1000->active)
+		Bring_Up(stfm1000);
+
+	mutex_unlock(&stfm1000->state_lock);
+
+	return 0;
+}
+
+static int vidioc_g_frequency(struct file *file, void *priv,
+				struct v4l2_frequency *f)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	f->type = V4L2_TUNER_RADIO;
+	f->frequency = stfm1000->freq * 16;
+
+	return 0;
+}
+
+static int vidioc_queryctrl(struct file *file, void *priv,
+				struct v4l2_queryctrl *qc)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+	int i;
+
+	(void)stfm1000;
+
+	for (i = 0; i < ARRAY_SIZE(radio_qctrl); i++) {
+		if (qc->id && qc->id == radio_qctrl[i].id) {
+			memcpy(qc, &radio_qctrl[i], sizeof(*qc));
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static int vidioc_g_ctrl(struct file *file, void *priv,
+				struct v4l2_control *ctrl)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	switch (ctrl->id) {
+
+	case V4L2_CID_AUDIO_MUTE:
+		ctrl->value = stfm1000->mute;
+		return 0;
+
+	}
+	return -EINVAL;
+}
+
+static int vidioc_s_ctrl(struct file *file, void *priv,
+				struct v4l2_control *ctrl)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+	int ret;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	ret = -EINVAL;
+
+	switch (ctrl->id) {
+
+	case V4L2_CID_AUDIO_MUTE:
+		stfm1000->mute = ctrl->value;
+		ret = 0;
+		break;
+	}
+
+	mutex_unlock(&stfm1000->state_lock);
+
+	return ret;
+}
+
+static int vidioc_g_audio(struct file *file, void *priv,
+				struct v4l2_audio *a)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	(void)stfm1000;
+
+	if (a->index > 1)
+		return -EINVAL;
+
+	strcpy(a->name, "Radio");
+	a->capability = V4L2_AUDCAP_STEREO;
+	return 0;
+}
+
+static int vidioc_s_audio(struct file *file, void *priv,
+					struct v4l2_audio *a)
+{
+	if (a->index > 1)
+		return -EINVAL;
+	return 0;
+}
+
+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	(void)stfm1000;
+
+	*i = 0;
+
+	return 0;
+}
+
+static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	(void)stfm1000;
+
+	if (i != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+const struct v4l2_ioctl_ops stfm_ioctl_ops = {
+	.vidioc_querycap	= vidioc_querycap,
+	.vidioc_g_tuner		= vidioc_g_tuner,
+	.vidioc_s_tuner		= vidioc_s_tuner,
+	.vidioc_g_frequency	= vidioc_g_frequency,
+	.vidioc_s_frequency	= vidioc_s_frequency,
+	.vidioc_queryctrl	= vidioc_queryctrl,
+	.vidioc_g_ctrl		= vidioc_g_ctrl,
+	.vidioc_s_ctrl		= vidioc_s_ctrl,
+	.vidioc_g_audio		= vidioc_g_audio,
+	.vidioc_s_audio		= vidioc_s_audio,
+	.vidioc_g_input		= vidioc_g_input,
+	.vidioc_s_input		= vidioc_s_input,
+};
+
+static int stfm1000_open(struct inode *inode, struct file *file)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	mutex_lock(&stfm1000->state_lock);
+	stfm1000->users = 1;
+	mutex_unlock(&stfm1000->state_lock);
+
+	return 0;
+}
+static int stfm1000_close(struct inode *inode, struct file *file)
+{
+	struct stfm1000 *stfm1000 = stfm1000_from_file(file);
+
+	if (!stfm1000)
+		return -ENODEV;
+
+	stfm1000->users = 0;
+	if (stfm1000->removed)
+		kfree(stfm1000);
+	return 0;
+}
+
+static const struct file_operations stfm1000_fops = {
+	.owner		= THIS_MODULE,
+	.open		= stfm1000_open,
+	.release	= stfm1000_close,
+	.ioctl		= video_ioctl2,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl	= v4l_compat_ioctl32,
+#endif
+	.llseek		= no_llseek,
+};
+
+/* sysfs */
+
+#define STFM1000_RO_ATTR(var) \
+static ssize_t stfm1000_show_ ## var(struct device *d, \
+	struct device_attribute *attr, char *buf) \
+{ \
+	struct i2c_client *client = to_i2c_client(d); \
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client); \
+	return sprintf(buf, "%d\n", stfm1000->var); \
+} \
+static DEVICE_ATTR(var, 0444, stfm1000_show_ ##var, NULL)
+
+#define STFM1000_RW_ATTR(var) \
+static ssize_t stfm1000_show_ ## var(struct device *d, \
+	struct device_attribute *attr, char *buf) \
+{ \
+	struct i2c_client *client = to_i2c_client(d); \
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client); \
+	return sprintf(buf, "%u\n", stfm1000->var); \
+} \
+static ssize_t stfm1000_store_ ## var(struct device *d, \
+	struct device_attribute *attr, const char *buf, size_t size) \
+{ \
+	struct i2c_client *client = to_i2c_client(d); \
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client); \
+	unsigned long v; \
+	\
+	strict_strtoul(buf, 0, &v); \
+	stfm1000_commit_ ## var(stfm1000, v); \
+	return size; \
+} \
+static DEVICE_ATTR(var, 0644, stfm1000_show_ ##var, stfm1000_store_ ##var)
+
+#define STFM1000_RW_ATTR_SIMPLE(var) \
+static void stfm1000_commit_ ## var(struct stfm1000 *stfm1000, \
+	unsigned long value) \
+{ \
+	stfm1000->var = value; \
+} \
+STFM1000_RW_ATTR(var)
+
+STFM1000_RO_ATTR(weak_signal);
+STFM1000_RO_ATTR(pilot_present);
+STFM1000_RO_ATTR(stereo);
+STFM1000_RO_ATTR(rssi);
+STFM1000_RO_ATTR(mpx_dc);
+STFM1000_RO_ATTR(signal_strength);
+STFM1000_RW_ATTR_SIMPLE(rds_signal_th);
+STFM1000_RO_ATTR(rds_present);
+STFM1000_RO_ATTR(is_station);
+
+static void stfm1000_commit_georegion(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	/* don't do anything for illegal region */
+	if (value != 0 && value != 1)
+		return;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	stfm1000->georegion = value;
+	if (stfm1000->georegion == 0)
+		stfm1000_clear_bits(stfm1000, STFM1000_INITIALIZATION2,
+			STFM1000_DEEMPH_50_75B);
+	else
+		stfm1000_set_bits(stfm1000, STFM1000_INITIALIZATION2,
+			STFM1000_DEEMPH_50_75B);
+
+	mutex_unlock(&stfm1000->state_lock);
+}
+STFM1000_RW_ATTR(georegion);
+
+static void stfm1000_commit_freq(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	mutex_lock(&stfm1000->state_lock);
+
+	/* clamp */
+	if (value < STFM1000_FREQUENCY_100KHZ_MIN * 100)
+		value = STFM1000_FREQUENCY_100KHZ_MIN * 100;
+	else if (value > STFM1000_FREQUENCY_100KHZ_MAX * 100)
+		value = STFM1000_FREQUENCY_100KHZ_MAX * 100;
+
+	stfm1000->freq = value;
+
+	if (stfm1000->active)
+		Take_Down(stfm1000);
+
+	sw_tune(stfm1000, stfm1000->freq);
+
+	if (stfm1000->active)
+		Bring_Up(stfm1000);
+
+	mutex_unlock(&stfm1000->state_lock);
+}
+STFM1000_RW_ATTR(freq);
+
+static void stfm1000_commit_mute(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	stfm1000->mute = !!value;
+}
+STFM1000_RW_ATTR(mute);
+
+static void stfm1000_commit_force_mono(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	stfm1000->force_mono = !!value;
+	/* set force mono parameters for the filter */
+	stfm1000->filter_parms.pCoefForcedMono = stfm1000->force_mono;
+
+	/* yeah, I know, it's stupid */
+	stfm1000->rds_state.demod.pCoefForcedMono =
+		stfm1000->filter_parms.pCoefForcedMono;
+}
+STFM1000_RW_ATTR(force_mono);
+
+STFM1000_RW_ATTR_SIMPLE(monitor_period);
+STFM1000_RW_ATTR_SIMPLE(quality_monitor);
+STFM1000_RW_ATTR_SIMPLE(quality_monitor_period);
+STFM1000_RW_ATTR_SIMPLE(agc_monitor_period);
+STFM1000_RW_ATTR_SIMPLE(tune_rssi_th);
+STFM1000_RW_ATTR_SIMPLE(tune_mpx_dc_th);
+
+static void stfm1000_commit_rds_enable(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	/* don't do anything for illegal values (or for not TB2) */
+	if ((value != 0 && value != 1) ||
+		stfm1000->revid == STFM1000_CHIP_REV_TA2)
+		return;
+
+	mutex_lock(&stfm1000->state_lock);
+
+	stfm1000->rds_enable = value;
+	if (stfm1000->rds_enable == 0)
+		stfm1000_clear_bits(stfm1000, STFM1000_INITIALIZATION2,
+			STFM1000_RDS_ENABLE);
+	else
+		stfm1000_set_bits(stfm1000, STFM1000_INITIALIZATION2,
+			STFM1000_RDS_ENABLE);
+
+	mutex_unlock(&stfm1000->state_lock);
+}
+STFM1000_RW_ATTR(rds_enable);
+
+static void stfm1000_commit_rds_sync(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	stfm1000->rds_sync = stfm1000->rds_enable && !!value;
+}
+STFM1000_RW_ATTR(rds_sync);
+
+STFM1000_RW_ATTR_SIMPLE(rds_pkt_good);
+STFM1000_RW_ATTR_SIMPLE(rds_pkt_bad);
+STFM1000_RW_ATTR_SIMPLE(rds_pkt_recovered);
+STFM1000_RW_ATTR_SIMPLE(rds_pkt_lost_sync);
+STFM1000_RW_ATTR_SIMPLE(rds_bit_overruns);
+STFM1000_RW_ATTR_SIMPLE(rds_info);
+
+static void stfm1000_commit_rds_sdnominal_adapt(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	stfm1000->rds_sdnominal_adapt = !!value;
+	stfm1000->rds_state.demod.sdnom_adapt = stfm1000->rds_sdnominal_adapt;
+}
+STFM1000_RW_ATTR(rds_sdnominal_adapt);
+
+static void stfm1000_commit_rds_phase_pop(struct stfm1000 *stfm1000,
+	unsigned long value)
+{
+	stfm1000->rds_phase_pop = !!value;
+	stfm1000->rds_state.demod.PhasePoppingEnabled =
+		stfm1000->rds_phase_pop;
+}
+STFM1000_RW_ATTR(rds_phase_pop);
+
+STFM1000_RW_ATTR_SIMPLE(tuning_grid_50KHz);
+
+static ssize_t stfm1000_show_rds_ps(struct device *d,
+	struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(d);
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client);
+	char ps[9];
+
+	if (stfm1000_rds_get_ps(&stfm1000->rds_state, ps, sizeof(ps)) <= 0)
+		ps[0] = '\0';
+
+	return sprintf(buf, "%s\n", ps);
+}
+static DEVICE_ATTR(rds_ps, 0444, stfm1000_show_rds_ps, NULL);
+
+static ssize_t stfm1000_show_rds_text(struct device *d,
+	struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(d);
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client);
+	char text[65];
+
+	if (stfm1000_rds_get_text(&stfm1000->rds_state, text,
+		sizeof(text)) <= 0)
+		text[0] = '\0';
+
+	return sprintf(buf, "%s\n", text);
+}
+static DEVICE_ATTR(rds_text, 0444, stfm1000_show_rds_text, NULL);
+
+static struct device_attribute *stfm1000_attrs[] = {
+	&dev_attr_agc_monitor_period,
+	&dev_attr_force_mono,
+	&dev_attr_freq,
+	&dev_attr_georegion,
+	&dev_attr_is_station,
+	&dev_attr_monitor_period,
+	&dev_attr_mpx_dc,
+	&dev_attr_mute,
+	&dev_attr_pilot_present,
+	&dev_attr_quality_monitor,
+	&dev_attr_quality_monitor_period,
+	&dev_attr_rds_bit_overruns,
+	&dev_attr_rds_enable,
+	&dev_attr_rds_info,
+	&dev_attr_rds_phase_pop,
+	&dev_attr_rds_pkt_bad,
+	&dev_attr_rds_pkt_good,
+	&dev_attr_rds_pkt_lost_sync,
+	&dev_attr_rds_pkt_recovered,
+	&dev_attr_rds_present,
+	&dev_attr_rds_ps,
+	&dev_attr_rds_sdnominal_adapt,
+	&dev_attr_rds_signal_th,
+	&dev_attr_rds_sync,
+	&dev_attr_rds_text,
+	&dev_attr_rssi,
+	&dev_attr_signal_strength,
+	&dev_attr_stereo,
+	&dev_attr_tune_mpx_dc_th,
+	&dev_attr_tune_rssi_th,
+	&dev_attr_tuning_grid_50KHz,
+	&dev_attr_weak_signal,
+	NULL,
+};
+
+/* monitor thread */
+
+static void rds_process(struct stfm1000 *stfm1000)
+{
+	int count, bit;
+	int mix_reg, sdnominal_reg;
+	u32 sdnom, sdnom_new, limit;
+	u8 buf[8];
+
+	if (!stfm1000->rds_enable)
+		return;
+
+	if (stfm1000->rds_sync &&
+		stfm1000->rssi_dc_est_log > stfm1000->rds_signal_th) {
+		if (stfm1000->rds_info)
+			printk(KERN_INFO "RDS: sync\n");
+		stfm1000_rds_reset(&stfm1000->rds_state);
+		stfm1000->rds_demod_running = 1;
+		stfm1000->rds_sync = 0;
+	}
+
+	if (!stfm1000->rds_demod_running)
+		return;
+
+	/* process mix reg requests */
+	spin_lock_irq(&stfm1000->rds_lock);
+	mix_reg = stfm1000_rds_mix_msg_get(&stfm1000->rds_state);
+	spin_unlock_irq(&stfm1000->rds_lock);
+
+	if (mix_reg != -1) {
+
+		if (stfm1000->rds_info)
+			printk(KERN_INFO "RDS: new RDS_MIXOFFSET %d\n",
+				mix_reg & 1);
+
+		/* update register */
+		if (mix_reg & 1)
+			stfm1000_set_bits(stfm1000, STFM1000_INITIALIZATION2,
+				STFM1000_RDS_MIXOFFSET);
+		else
+			stfm1000_clear_bits(stfm1000, STFM1000_INITIALIZATION2,
+				STFM1000_RDS_MIXOFFSET);
+
+		/* signal it's processed */
+		spin_lock_irq(&stfm1000->rds_lock);
+		stfm1000_rds_mix_msg_processed(&stfm1000->rds_state, mix_reg);
+		spin_unlock_irq(&stfm1000->rds_lock);
+	}
+
+	/* process sdnominal reg requests */
+	spin_lock_irq(&stfm1000->rds_lock);
+	sdnominal_reg = stfm1000_rds_sdnominal_msg_get(&stfm1000->rds_state);
+	spin_unlock_irq(&stfm1000->rds_lock);
+
+	/* any change? */
+	if (sdnominal_reg != 0) {
+
+		stfm1000_read(stfm1000, STFM1000_SDNOMINAL, &sdnom);
+
+		sdnom_new = sdnom + sdnominal_reg;
+
+		/* Limit SDNOMINAL to within 244 ppm of its ideal value */
+		limit = stfm1000->sdnominal_pivot +
+			(stfm1000->sdnominal_pivot >> 12);
+		if (sdnom_new > limit)
+			sdnom_new = limit;
+
+		limit = stfm1000->sdnominal_pivot -
+			(stfm1000->sdnominal_pivot >> 12);
+		if (sdnom_new < limit)
+			sdnom_new = limit;
+
+		/* write the register */
+		stfm1000_write(stfm1000, STFM1000_SDNOMINAL, sdnom_new);
+
+		/* signal it's processed */
+		spin_lock_irq(&stfm1000->rds_lock);
+		stfm1000_rds_sdnominal_msg_processed(&stfm1000->rds_state,
+			sdnominal_reg);
+		spin_unlock_irq(&stfm1000->rds_lock);
+	}
+
+	/* pump bits out & pass them to the process function */
+	spin_lock_irq(&stfm1000->rds_lock);
+	while (stfm1000_rds_bits_available(&stfm1000->rds_state) > 128) {
+		count = 0;
+		while (count++ < 128 &&
+			(bit = stmf1000_rds_get_bit(
+				&stfm1000->rds_state)) >= 0) {
+			spin_unlock_irq(&stfm1000->rds_lock);
+
+			/* push bit for packet processing */
+			stfm1000_rds_packet_bit(&stfm1000->rds_state, bit);
+
+			spin_lock_irq(&stfm1000->rds_lock);
+		}
+	}
+	spin_unlock_irq(&stfm1000->rds_lock);
+
+	/* now we're free to process non-interrupt related work */
+	while (stfm1000_rds_packet_dequeue(&stfm1000->rds_state, buf) == 0) {
+
+		if (stfm1000->rds_info)
+			printk(KERN_INFO "RDS-PKT: %02x %02x %02x %02x "
+					"%02x %02x %02x %02x\n",
+				buf[0], buf[1], buf[2], buf[3],
+				buf[4], buf[5], buf[6], buf[7]);
+
+		stfm1000_rds_process_packet(&stfm1000->rds_state, buf);
+	}
+
+	/* update our own counters */
+	stfm1000->rds_pkt_good += stfm1000->rds_state.pkt.good_packets;
+	stfm1000->rds_pkt_bad += stfm1000->rds_state.pkt.bad_packets;
+	stfm1000->rds_pkt_recovered +=
+		stfm1000->rds_state.pkt.recovered_packets;
+	stfm1000->rds_pkt_lost_sync +=
+		stfm1000->rds_state.pkt.sync_lost_packets;
+	stfm1000->rds_bit_overruns +=
+		stfm1000->rds_state.demod.RdsDemodSkippedBitCnt;
+
+	/* zero them now */
+	stfm1000->rds_state.pkt.good_packets = 0;
+	stfm1000->rds_state.pkt.bad_packets = 0;
+	stfm1000->rds_state.pkt.recovered_packets = 0;
+	stfm1000->rds_state.pkt.sync_lost_packets = 0;
+	stfm1000->rds_state.demod.RdsDemodSkippedBitCnt = 0;
+
+	/* reset requested from RDS handler? */
+	if (stfm1000_rds_get_reset_req(&stfm1000->rds_state)) {
+		if (stfm1000->rds_info)
+			printk(KERN_INFO "RDS: reset requested\n");
+		stfm1000_rds_reset(&stfm1000->rds_state);
+
+		stfm1000->rds_sync = stfm1000->rds_enable; /* force sync (if RDS) */
+		stfm1000->rds_demod_running = 0;
+		stfm1000->rssi_dc_est_log = 0;
+		stfm1000->signal_strength = 0;
+	}
+}
+
+void stfm1000_monitor_signal(struct stfm1000 *stfm1000, int bit)
+{
+	set_bit(bit, &stfm1000->thread_events);
+	return wake_up_interruptible(&stfm1000->thread_wait);
+}
+
+static int stfm1000_monitor_thread(void *data)
+{
+	struct stfm1000 *stfm1000 = data;
+	int ret;
+
+	printk(KERN_INFO "stfm1000: monitor thread started\n");
+
+	set_freezable();
+
+	/* Hmm, linux becomes *very* unhappy without this ... */
+	while (!kthread_should_stop()) {
+
+		ret = wait_event_interruptible_timeout(stfm1000->thread_wait,
+				stfm1000->thread_events == 0,
+				msecs_to_jiffies(stfm1000->monitor_period));
+
+		stfm1000->thread_events = 0;
+
+		if (kthread_should_stop())
+			break;
+
+		try_to_freeze();
+
+		mutex_lock(&stfm1000->state_lock);
+
+		/* we must be active */
+		if (!stfm1000->active)
+			goto next;
+
+		if (stfm1000->rds_enable)
+			rds_process(stfm1000);
+
+		/* perform quality monitor */
+		if (time_after_eq(jiffies, stfm1000->next_quality_monitor)) {
+
+			/* full quality monitor? */
+			if (stfm1000->quality_monitor)
+				Monitor_STFM_Quality(stfm1000);
+			else	/* simple */
+				Is_Station(stfm1000);
+
+			while (time_after_eq(jiffies,
+					stfm1000->next_quality_monitor))
+				stfm1000->next_quality_monitor +=
+					msecs_to_jiffies(
+					stfm1000->quality_monitor_period);
+		}
+
+		/* perform AGC monitor (if enabled) */
+		if (stfm1000->agc_monitor && time_after_eq(jiffies,
+				stfm1000->next_agc_monitor)) {
+			Monitor_STFM_AGC(stfm1000);
+			while (time_after_eq(jiffies,
+					stfm1000->next_agc_monitor))
+				stfm1000->next_agc_monitor +=
+					msecs_to_jiffies(
+						stfm1000->agc_monitor_period);
+		}
+next:
+		mutex_unlock(&stfm1000->state_lock);
+	}
+
+	printk(KERN_INFO "stfm1000: monitor thread stopped\n");
+
+	return 0;
+}
+
+static u64 stfm1000_dma_mask = DMA_32BIT_MASK;
+
+static int stfm1000_probe(struct i2c_client *client,
+			 const struct i2c_device_id *did)
+{
+	struct device *dev;
+	struct stfm1000 *stfm1000;
+	struct video_device *vd;
+	struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+	int ret;
+	u32 id;
+	const char *idtxt;
+	int i;
+
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+		dev_warn(&adapter->dev,
+			"I2C doesn't support I2C_FUNC_SMBUS_BYTE_DATA\n");
+		return -EIO;
+	}
+
+	/* make sure the dma masks are set correctly */
+	dev = &client->dev;
+	if (!dev->dma_mask)
+		dev->dma_mask = &stfm1000_dma_mask;
+	if (!dev->coherent_dma_mask)
+		dev->coherent_dma_mask = DMA_32BIT_MASK;
+
+	stfm1000 = kzalloc(sizeof(*stfm1000), GFP_KERNEL);
+	if (!stfm1000)
+		return -ENOMEM;
+
+	stfm1000->client = client;
+	i2c_set_clientdata(client, stfm1000);
+
+	mutex_init(&stfm1000->xfer_lock);
+	mutex_init(&stfm1000->state_lock);
+
+	vd = &stfm1000->radio;
+
+	strcpy(vd->name, "stfm1000");
+	vd->vfl_type		= VID_TYPE_TUNER;
+	vd->fops		= &stfm1000_fops;
+	vd->ioctl_ops		= &stfm_ioctl_ops;
+
+	/* vd->debug = V4L2_DEBUG_IOCTL | V4L2_DEBUG_IOCTL_ARG; */
+
+	vd->parent = &client->dev;
+
+	ret = video_register_device(vd, VFL_TYPE_RADIO, -1);
+	if (ret != 0) {
+		dev_warn(&adapter->dev,
+			 "Cannot register radio device\n");
+		goto out;
+	}
+
+	spin_lock_init(&stfm1000->rds_lock);
+
+	stfm1000_setup_reg_set(stfm1000);
+
+	/* stfm1000->dbgflg |= STFM1000_DBGFLG_I2C; */
+
+	ret = stfm1000_read(stfm1000, STFM1000_CHIPID, &id);
+	if (ret < 0) {
+		dev_warn(&adapter->dev,
+			 "Cannot read ID register\n");
+		goto out;
+	}
+	stfm1000->revid = id & 0xff;
+
+	/* NOTE: the tables are precalculated */
+	stfm1000->tune_rssi_th = 28;
+	stfm1000->tune_mpx_dc_th = 300;
+	stfm1000->adj_chan_th = 100;
+	stfm1000->pilot_est_th = 25;
+	stfm1000->agc_monitor = 0;	/* AGC monitor disabled */
+	stfm1000->quality_monitor = 1;
+	stfm1000->weak_signal = 0;
+	stfm1000->prev_pilot_present = 0;
+	stfm1000->tune_cap_a_f = (u32)(72.4 * 65536);
+	stfm1000->tune_cap_b_f = (u32)(0.07 * 65536);
+
+	/* only TB2 supports RDS */
+	stfm1000->rds_enable = stfm1000->revid == STFM1000_CHIP_REV_TB2 &&
+		rds_enable;
+	stfm1000->rds_present = 0;
+	stfm1000->rds_signal_th = 33;
+
+	stfm1000->freq = 92600;
+
+	stfm1000->georegion = georegion;
+	stfm1000->rssi = 0;
+	stfm1000->stereo = 0;
+	stfm1000->force_mono = 0;
+	stfm1000->monitor_period = 100;
+	stfm1000->quality_monitor_period = 1000;
+	stfm1000->agc_monitor_period = 200;
+
+	stfm1000->rds_sdnominal_adapt = 0;
+	stfm1000->rds_phase_pop = 1;
+
+	/* enable info about RDS */
+	stfm1000->rds_info = 0;
+
+	ret = stfm1000_power_up(stfm1000);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: stfm1000_power_up failed\n",
+				__func__);
+		goto out;
+	}
+
+	if (stfm1000_alsa_ops && stfm1000_alsa_ops->init) {
+		ret = (*stfm1000_alsa_ops->init)(stfm1000);
+		if (ret != 0)
+			goto out;
+		stfm1000->alsa_initialized = 1;
+	}
+
+	ret = 0;
+	for (i = 0; stfm1000_attrs[i]; i++) {
+		ret = device_create_file(dev, stfm1000_attrs[i]);
+		if (ret)
+			break;
+	}
+	if (ret) {
+		while (--i >= 0)
+			device_remove_file(dev, stfm1000_attrs[i]);
+		goto out;
+	}
+
+	/* add it to the list */
+	mutex_lock(&devlist_lock);
+	stfm1000->idx = stfm1000_devcount++;
+	list_add_tail(&stfm1000->devlist, &stfm1000_devlist);
+	mutex_unlock(&devlist_lock);
+
+	init_waitqueue_head(&stfm1000->thread_wait);
+	stfm1000->thread = kthread_run(stfm1000_monitor_thread, stfm1000,
+			"stfm1000-%d", stfm1000->idx);
+	if (stfm1000->thread == NULL) {
+		printk(KERN_ERR "stfm1000: kthread_run failed\n");
+		goto out;
+	}
+
+	idtxt = stfm1000_get_rev_txt(stfm1000->revid);
+	if (idtxt == NULL)
+		printk(KERN_INFO "STFM1000: Loaded for unknown revision id "
+			"0x%02x\n", stfm1000->revid);
+	else
+		printk(KERN_INFO "STFM1000: Loaded for revision %s\n", idtxt);
+
+	return 0;
+
+out:
+	kfree(stfm1000);
+	return ret;
+}
+
+static int stfm1000_remove(struct i2c_client *client)
+{
+	struct stfm1000 *stfm1000 = i2c_get_clientdata(client);
+	struct device *dev = &client->dev;
+	int i;
+
+	kthread_stop(stfm1000->thread);
+
+	for (i = 0; stfm1000_attrs[i]; i++)
+		device_remove_file(dev, stfm1000_attrs[i]);
+
+	if (stfm1000->alsa_initialized) {
+		BUG_ON(stfm1000_alsa_ops->release == NULL);
+		(*stfm1000_alsa_ops->release)(stfm1000);
+		stfm1000->alsa_initialized = 0;
+	}
+
+	stfm1000_power_down(stfm1000);
+
+	video_unregister_device(&stfm1000->radio);
+
+	mutex_lock(&devlist_lock);
+	list_del(&stfm1000->devlist);
+	mutex_unlock(&devlist_lock);
+
+	kfree(stfm1000);
+	return 0;
+}
+
+static const struct i2c_device_id stfm1000_id[] = {
+	{ "stfm1000", 0xC0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, stfm1000_id);
+
+static struct i2c_driver stfm1000_i2c_driver = {
+	.driver = {
+		.name = "stfm1000",
+	},
+	.probe		= stfm1000_probe,
+	.remove		= stfm1000_remove,
+	.id_table	= stfm1000_id,
+};
+
+static int __init
+stfm1000_init(void)
+{
+	/* pull those in */
+	(void)Lock_Station;
+	(void)Unlock_Station;
+	return i2c_add_driver(&stfm1000_i2c_driver);
+}
+
+static void __exit
+stfm1000_exit(void)
+{
+	i2c_del_driver(&stfm1000_i2c_driver);
+
+	stfm1000_alsa_ops = NULL;
+}
+
+module_init(stfm1000_init);
+module_exit(stfm1000_exit);
+
+MODULE_AUTHOR("Pantelis Antoniou");
+MODULE_DESCRIPTION("A driver for the STFM1000 chip.");
+MODULE_LICENSE("GPL");
+
+module_param(georegion, int, 0400);
+module_param(rds_enable, int, 0400);
diff --git a/drivers/media/radio/stfm1000/stfm1000-filter.c b/drivers/media/radio/stfm1000/stfm1000-filter.c
new file mode 100644
index 000000000000..df42524a5da7
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-filter.c
@@ -0,0 +1,860 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+
+#include "stfm1000.h"
+
+void stfm1000_filter_reset(struct stfm1000_filter_parms *sdf)
+{
+	sdf->Left = 0;
+	sdf->Right = 0;
+	sdf->RssiDecoded = 0;
+	sdf->RssiMant = 0;
+	sdf->RssiExp = 0;
+	sdf->RssiLb = 0;
+	sdf->TrueRssi = 0;
+	sdf->Prssi = 0;
+	sdf->RssiLog = 0;
+	sdf->ScaledTrueRssi = 0;
+	sdf->FilteredRssi = 0;
+	sdf->PrevFilteredRssi = 0;
+	sdf->DecRssi = 0;
+	sdf->ScaledRssiDecoded = 0;
+	sdf->ScaledRssiDecodedZ = 0;
+	sdf->ScaledRssiDecodedZz = 0;
+	sdf->Echo = 0;
+	sdf->EchoLb = 0;
+	sdf->TrueEcho = 0;
+	sdf->FilteredEchoLpr = 0;
+	sdf->PrevFilteredEchoLpr = 0;
+	sdf->FilteredEchoLmr = 0;
+	sdf->PrevFilteredEchoLmr = 0;
+	sdf->GatedEcho = 0;
+	sdf->ControlLpr = 0;
+	sdf->ControlLmr = 0;
+	sdf->LprBw = 0;
+	sdf->LmrBw = 0;
+
+	sdf->LprXz = 0;
+	sdf->LprXzz = 0;
+	sdf->LprYz = 0;
+	sdf->LprYzz = 0;
+	sdf->LmrXz = 0;
+	sdf->LmrXzz = 0;
+	sdf->LmrYz = 0;
+	sdf->LmrYzz = 0;
+	sdf->FilteredLpr = 0;
+	sdf->FilteredLmr = 0;
+
+	sdf->B0B = 0;
+	sdf->B0S = 0;
+	sdf->B0M = 0;
+	sdf->B1over2B = 0;
+	sdf->B1over2S = 0;
+	sdf->B1over2M = 0;
+	sdf->A1over2B = 0;
+	sdf->A1over2S = 0;
+	sdf->A1over2M = 0;
+	sdf->A2B = 0;
+	sdf->A2S = 0;
+	sdf->A2M = 0;
+
+	sdf->AdjBw = 0;
+
+	sdf->pCoefLprBwThLo = 20 << 8;
+	sdf->pCoefLprBwThHi = 30 << 8;
+	sdf->pCoefLmrBwThLo = 40 << 8;
+	sdf->pCoefLmrBwThHi = 50 << 8;
+	sdf->pCoefLprBwSlSc = 4800;	/* SDK-2287 */
+	sdf->pCoefLprBwSlSh = 10;	/* SDK-2287 */
+	sdf->pCoefLmrBwSlSc = 4800;	/* SDK-2287 */
+	sdf->pCoefLmrBwSlSh = 10;	/* SDK-2287 */
+	sdf->pCoefLprGaSlSc = 0;
+	sdf->pCoefLprGaSlSh = 0;
+
+	sdf->ScaledControlLmr = 0;
+
+	sdf->LprGa = 32767;
+	sdf->LmrGa = 32767;
+
+	sdf->pCoefLprGaTh = 20;		/* 25 */
+	sdf->pCoefLmrGaTh = 55;		/* 60 50 */
+
+	sdf->MuteAudio = 0;
+	sdf->PrevMuteAudio = 0;
+	sdf->MuteActionFlag = 0;
+	sdf->ScaleAudio = 0;
+
+	/* *** Programmable initial setup for stereo path filters */
+	sdf->LprB0 = 18806;		/* -3dB cutoff = 17 kHz */
+	sdf->LprB1over2 = 18812;	/* -3dB cutoff = 17 kHz */
+	sdf->LprA1over2 = -16079;	/* -3dB cutoff = 17 kHz */
+	sdf->LprA2 = -11125;		/* -3dB cutoff = 17 kHz */
+	sdf->LmrB0 = 18806;		/* -3dB cutoff = 17 kHz */
+	sdf->LmrB1over2 = 18812;	/* -3dB cutoff = 17 kHz */
+	sdf->LmrA1over2 = -16079;	/* -3dB cutoff = 17 kHz */
+	sdf->LmrA2 = -11125;		/* -3dB cutoff = 17 kHz */
+
+	sdf->pCoefForceLockLmrBw = 0;	/* Force Lock LMR BW = LPR BW
+					 * XXX BUG WARNING -
+					 * This control doesn't work! */
+
+	sdf->pCoefForcedMono = 0;	/* Do not set this =
+					 * Quality Monitor will overwrite it */
+	sdf->pCoefBypassBlend = 0;	/* BUG WARNING -
+					 * This control doesn't work! */
+	sdf->pCoefBypassSoftmute = 0;	/* BUG WARNING -
+					 * This control doesn't work! */
+	sdf->pCoefBypassBwCtl = 0;	/* BUG WARNING -
+					 * This control doesn't work! */
+
+	/* There's a bug or something in the attack/decay section b/c
+	 * setting these coef's to anything */
+	/* higher than 100ms or so causes the RSSI to be artificially low -
+	 * Needs investigation! 15DEC06 */
+	sdf->pCoefRssiAttack = 65386;		/* changed to 100ms to avoid
+						 * stereo crackling
+						 * 60764 corresponds to 3 */
+	sdf->pCoefRssiDecay = 65386;		/* changed to 100ms to avoid
+						 * stereo crackling
+						 * 65530 corresponds to 10 */
+	sdf->pCoefEchoLprAttack = 52239;	/* corresponds to 1 */
+	sdf->pCoefEchoLprDecay = 64796;		/* corresponds to 20 */
+	sdf->pCoefEchoLmrAttack = 52239;	/* corresponds to 1 */
+	sdf->pCoefEchoLmrDecay = 65520;		/* corresponds to 20 */
+	sdf->pCoefEchoTh = 100;
+	sdf->pCoefEchoScLpr = (u16) (0.9999 * 32767.0);
+	sdf->pCoefEchoScLmr = (u16) (0.9999 * 32767.0);
+}
+
+void stfm1000_filter_decode(struct stfm1000_filter_parms *sdf, s16 Lpr,
+	s16 Lmr, u16 Rssi)
+{
+	s16 temp1_reg;		/* mimics 16 bit register */
+	s16 temp2_reg;		/* mimics 16 bit register */
+	s16 temp3_reg;		/* mimics 16 bit register */
+	s16 temp4_reg;		/* mimics 16 bit register */
+#ifndef _TUNER_STFM_MUTE
+	s16 temp5_reg;		/* mimics 16 bit register */
+#endif
+	s32 temp2_reg_32;	/*eI 108 27th Feb 06 temp variables. */
+
+	/* **************************************************************** */
+	/* *** Stereo Processing ****************************************** */
+	/* **************************************************************** */
+	/* *** This block operates at Fs = 44.1kHz */
+	/* ******** */
+	/* *** LPR path filter (2nd order IIR) */
+
+	sdf->Acc_signed = sdf->LprB0 * Lpr + 2 * (sdf->LprB1over2 * sdf->LprXz)
+	    + sdf->LprB0 * sdf->LprXzz + 2 * (sdf->LprA1over2 * sdf->LprYz)
+	    + sdf->LprA2 * sdf->LprYzz;
+
+	sdf->FilteredLpr = sdf->Acc_signed >> 15;
+
+	sdf->LprXzz = sdf->LprXz;	/* update taps */
+	sdf->LprXz = Lpr;
+	sdf->LprYzz = sdf->LprYz;
+	sdf->LprYz = sdf->FilteredLpr;
+
+	/* *** LMR path filter (2nd order IIR) */
+	sdf->Acc_signed = sdf->LmrB0 * Lmr + 2 * (sdf->LmrB1over2 * sdf->LmrXz)
+	    + sdf->LmrB0 * sdf->LmrXzz + 2 * (sdf->LmrA1over2 * sdf->LmrYz)
+	    + sdf->LmrA2 * sdf->LmrYzz;
+
+	sdf->FilteredLmr = sdf->Acc_signed >> 15;
+
+	sdf->LmrXzz = sdf->LmrXz;	/* update taps */
+	sdf->LmrXz = Lmr;
+	sdf->LmrYzz = sdf->LmrYz;
+	sdf->LmrYz = sdf->FilteredLmr;
+
+	/* *** Stereo Matrix */
+	if (0 == sdf->pCoefBypassBlend)
+		temp1_reg = sdf->LmrGa * sdf->FilteredLmr >> 15; /* Blend */
+	else
+		temp1_reg = sdf->FilteredLmr;
+
+	if (sdf->pCoefForcedMono)	/* Forced Mono */
+		temp1_reg = 0;
+
+	if (0 == sdf->pCoefBypassSoftmute) {
+		temp2_reg = sdf->LprGa * sdf->FilteredLpr >> 15; /* LPR */
+		temp3_reg = sdf->LprGa * temp1_reg >> 15;	 /* LMR */
+	} else {
+		temp2_reg = sdf->FilteredLpr;
+		temp3_reg = temp1_reg;
+	}
+
+	temp4_reg = (temp2_reg + temp3_reg) / 2;	/* Matrix */
+
+#ifndef _TUNER_STFM_MUTE
+	temp5_reg = (temp2_reg - temp3_reg) / 2;
+#endif
+
+#if 0
+	/* *** DC Cut Filter (leaky bucket estimate) */
+	if (0 == sdf->pCoefBypassDcCut) {
+		sdf->LeftLb_i32 =
+		    sdf->LeftLb_i32 + temp4_reg - (sdf->LeftLb_i32 >> 8);
+		temp2_reg = temp4_reg - (sdf->LeftLb_i32 >> 8);	/* signal -
+								dc_estimate */
+
+		sdf->RightLb_i32 =
+		    sdf->RightLb_i32 + temp5_reg - (sdf->RightLb_i32 >> 8);
+		temp3_reg = temp5_reg - (sdf->RightLb_i32 >> 8); /* signal -
+								dc_estimate */
+	} else {
+		temp2_reg = temp4_reg;
+		temp3_reg = temp5_reg;
+	}
+#endif
+#ifdef _TUNER_STFM_MUTE
+	/* *** Mute Audio */
+	if (sdf->MuteAudio != sdf->PrevMuteAudio)	/* Mute transition */
+		sdf->MuteActionFlag = 1;	/* set flag */
+	sdf->PrevMuteAudio = sdf->MuteAudio;	/* update history */
+
+	if (sdf->MuteActionFlag) {
+		if (0 == sdf->MuteAudio) {	/* Mute to zero */
+			/* gradual mute down */
+			sdf->ScaleAudio = sdf->ScaleAudio - sdf->pCoefMuteStep;
+
+			/* eI-117:Oct28:as per C++ code */
+			/* if (0 < sdf->ScaleAudio) */
+			if (0 > sdf->ScaleAudio) {
+				sdf->ScaleAudio = 0;	 /* Minimum scale
+							  * factor */
+				sdf->MuteActionFlag = 0; /* End Mute Action */
+			}
+		} else {	/* Un-Mute to one */
+				/* gradual mute up */
+			sdf->ScaleAudio = sdf->ScaleAudio + sdf->pCoefMuteStep;
+			if (0 > sdf->ScaleAudio) {	/* look for rollover
+							 * beyong 32767 */
+				sdf->ScaleAudio = 32767; /* Maximum scale
+							  * factor */
+				sdf->MuteActionFlag = 0; /* End Mute Action */
+			}
+		}		/* end else */
+	}			/* end if (sdf->MuteActionFlag) */
+
+/*! Output Processed Sample */
+
+	sdf->Left = (temp2_reg * sdf->ScaleAudio) >> 15;	/* Scale */
+	sdf->Right = (temp3_reg * sdf->ScaleAudio) >> 15;	/* Scale */
+
+#else /* !_TUNER_STFM_MUTE */
+
+	sdf->Left = temp4_reg;
+	sdf->Right = temp5_reg;
+
+#endif /* !_TUNER_STFM_MUTE */
+
+	/* *** End Stereo Processing ************************************** */
+	/* **************************************************************** */
+
+	/* **************************************************************** */
+	/* *** Signal Quality Indicators ********************************** */
+	/* **************************************************************** */
+	/* *** This block operates at Fs = 44.1kHz */
+	/* ******** */
+	/* *** RSSI */
+	/* ******** */
+	/* Decode Floating Point RSSI data */
+	/*! Input RSSI sample */
+	sdf->RssiMant = (Rssi & 0xFFE0) >> 5;	/* 11 msb's */
+	sdf->RssiExp = Rssi & 0x001F;	/* 5 lsb's */
+	sdf->RssiDecoded = sdf->RssiMant << sdf->RssiExp;
+
+	/* *** Convert RSSI to 10*Log10(RSSI) */
+	/* This is easily accomplished in DSP code using the CLZ instruction */
+	/* rather than using all these comparisons. */
+	/* The basic idea is this: */
+	/* if x >= 2^P */
+	/*   f(x) = 3*x>>P + (3*P-3) */
+	/* Approx. is valid over the range of sdf->RssiDecoded in [0, 2^21] */
+	/* *** */
+	if (sdf->RssiDecoded >= 1048576)
+		sdf->Prssi = 20;
+	else if (sdf->RssiDecoded >= 524288)
+		sdf->Prssi = 19;
+	else if (sdf->RssiDecoded >= 262144)
+		sdf->Prssi = 18;
+	else if (sdf->RssiDecoded >= 131072)
+		sdf->Prssi = 17;
+	else if (sdf->RssiDecoded >= 65536)
+		sdf->Prssi = 16;
+	else if (sdf->RssiDecoded >= 32768)
+		sdf->Prssi = 15;
+	else if (sdf->RssiDecoded >= 16384)
+		sdf->Prssi = 14;
+	else if (sdf->RssiDecoded >= 8192)
+		sdf->Prssi = 13;
+	else if (sdf->RssiDecoded >= 4096)
+		sdf->Prssi = 12;
+	else if (sdf->RssiDecoded >= 2048)
+		sdf->Prssi = 11;
+	else if (sdf->RssiDecoded >= 1024)
+		sdf->Prssi = 10;
+	else if (sdf->RssiDecoded >= 512)
+		sdf->Prssi = 9;
+	else if (sdf->RssiDecoded >= 256)
+		sdf->Prssi = 8;
+	else if (sdf->RssiDecoded >= 128)
+		sdf->Prssi = 7;
+	else if (sdf->RssiDecoded >= 64)
+		sdf->Prssi = 6;
+	else if (sdf->RssiDecoded >= 32)
+		sdf->Prssi = 5;
+	else if (sdf->RssiDecoded >= 16)
+		sdf->Prssi = 4;
+	else if (sdf->RssiDecoded >= 8)
+		sdf->Prssi = 3;
+	else if (sdf->RssiDecoded >= 4)
+		sdf->Prssi = 2;
+	else if (sdf->RssiDecoded >= 2)
+		sdf->Prssi = 1;
+	else
+		sdf->Prssi = 0;
+	sdf->RssiLog =
+	    (3 * sdf->RssiDecoded >> sdf->Prssi) + (3 * sdf->Prssi - 3);
+
+	if (0 > sdf->RssiLog)	/* Clamp to positive */
+		sdf->RssiLog = 0;
+
+	/* Compensate for errors in truncation/approximation by adding 1 */
+	sdf->RssiLog = sdf->RssiLog + 1;
+
+	/* Leaky Bucket Filter DC estimate of RSSI */
+	sdf->RssiLb = sdf->RssiLb + sdf->RssiLog - (sdf->RssiLb >> 3);
+	sdf->TrueRssi = sdf->RssiLb >> 3;
+
+	/* Scale up so we have some room for precision */
+	sdf->ScaledTrueRssi = sdf->TrueRssi << 8;
+	/* ************ */
+	/* *** end RSSI */
+	/* ************ */
+
+	/* ******** */
+	/* *** Echo */
+	/* ******** */
+	/* *** Isolate Echo information as higher frequency info */
+	/* using [1 -2 1] highpass FIR */
+	sdf->ScaledRssiDecoded = sdf->RssiDecoded >> 4;
+	sdf->Echo =
+	    (s16) ((sdf->ScaledRssiDecoded -
+		    2 * sdf->ScaledRssiDecodedZ + sdf->ScaledRssiDecodedZz));
+	sdf->ScaledRssiDecodedZz = sdf->ScaledRssiDecodedZ;
+	sdf->ScaledRssiDecodedZ = sdf->ScaledRssiDecoded;
+	/* ************ */
+	/* *** end Echo */
+	/* ************ */
+	/* *** End Signal Quality Indicators ******************************* */
+	/* ***************************************************************** */
+
+	/* ***************************************************************** */
+	/* *** Weak Signal Processing ************************************** */
+	/* ***************************************************************** */
+	/* *** This block operates at Fs = 44.1/16 = 2.75 Khz
+	 * *eI 108 28th Feb 06 WSP and SM executes at 2.75Khz */
+	/* decimate by 16                   STFM_FILTER_BLOCK_MULTIPLE is 16 */
+	if (0 == sdf->DecRssi) {
+		/* *** Filter RSSI via attack/decay structure */
+		if (sdf->ScaledTrueRssi > sdf->PrevFilteredRssi)
+			sdf->Acc =
+			    sdf->pCoefRssiAttack *
+			    sdf->PrevFilteredRssi + (65535 -
+						     sdf->pCoefRssiAttack)
+			    * sdf->ScaledTrueRssi;
+		else
+			sdf->Acc =
+			    sdf->pCoefRssiDecay *
+			    sdf->PrevFilteredRssi + (65535 -
+						     sdf->pCoefRssiDecay)
+			    * sdf->ScaledTrueRssi;
+
+		sdf->FilteredRssi = sdf->Acc >> 16;
+		sdf->PrevFilteredRssi = sdf->FilteredRssi;
+
+		/* *** Form Echo "energy" representation */
+		if (0 > sdf->Echo)
+			sdf->Echo = -sdf->Echo;	/* ABS() */
+
+		/* Threshold compare */
+		sdf->GatedEcho = (s16) (sdf->Echo - sdf->pCoefEchoTh);
+		if (0 > sdf->GatedEcho)	/* Clamp to (+)ve */
+			sdf->GatedEcho = 0;
+
+		/* *** Leaky bucket DC estimate of Echo energy */
+		sdf->EchoLb = sdf->EchoLb + sdf->GatedEcho -
+				(sdf->EchoLb >> 3);
+		sdf->TrueEcho = sdf->EchoLb >> 3;
+
+		/* *** Filter Echo via attack/decay structure for LPR */
+		if (sdf->TrueEcho > sdf->PrevFilteredEchoLpr)
+			sdf->Acc =
+			    sdf->pCoefEchoLprAttack *
+			    sdf->PrevFilteredEchoLpr +
+				(65535 - sdf->pCoefEchoLprAttack) *
+					sdf->TrueEcho;
+		else
+			sdf->Acc =
+			    sdf->pCoefEchoLprDecay *
+			    sdf->PrevFilteredEchoLpr +
+				(65535 - sdf->pCoefEchoLprDecay) *
+					sdf->TrueEcho;
+
+		sdf->FilteredEchoLpr = sdf->Acc >> 16;
+		sdf->PrevFilteredEchoLpr = sdf->FilteredEchoLpr;
+
+		/* *** Filter Echo via attack/decay structure for LMR */
+		if (sdf->TrueEcho > sdf->PrevFilteredEchoLmr)
+			sdf->Acc = sdf->pCoefEchoLmrAttack *
+				sdf->PrevFilteredEchoLmr +
+					(65535 - sdf->pCoefEchoLmrAttack)
+						* sdf->TrueEcho;
+		else
+			sdf->Acc =
+			    sdf->pCoefEchoLmrDecay *
+			    sdf->PrevFilteredEchoLmr + (65535 -
+							sdf->pCoefEchoLmrDecay)
+			    * sdf->TrueEcho;
+
+		sdf->FilteredEchoLmr = sdf->Acc >> 16;
+		sdf->PrevFilteredEchoLmr = sdf->FilteredEchoLmr;
+
+		/* *** Form control variables */
+		/* Generically speaking, ctl = f(RSSI, Echo) =
+		 * RSSI - (a*Echo)<<b, where a,b are programmable */
+		sdf->ControlLpr = sdf->FilteredRssi -
+		    ((sdf->pCoefEchoScLpr *
+		      sdf->FilteredEchoLpr << sdf->pCoefEchoShLpr) >> 15);
+		if (0 > sdf->ControlLpr)
+			sdf->ControlLpr = 0;	/* Clamp to positive */
+
+		sdf->ControlLmr = sdf->FilteredRssi -
+		    ((sdf->pCoefEchoScLmr *
+		      sdf->FilteredEchoLmr << sdf->pCoefEchoShLmr) >> 15);
+		if (0 > sdf->ControlLmr)
+			sdf->ControlLmr = 0;	/* Clamp to positive */
+
+		/* *** Define LPR_BW = f(control LPR) */
+		/* Assume that 5 kHz and 17 kHz are limits of LPR_BW control */
+		if (sdf->ControlLpr <= sdf->pCoefLprBwThLo)
+			sdf->LprBw = 5000;	/* lower limit is 5 kHz */
+		else if (sdf->ControlLpr >= sdf->pCoefLprBwThHi)
+			sdf->LprBw = 17000;	/* upper limit is 17 kHz */
+		else
+			sdf->LprBw = 17000 -
+			    ((sdf->pCoefLprBwSlSc *
+			      (sdf->pCoefLprBwThHi -
+			       sdf->ControlLpr)) >> sdf->pCoefLprBwSlSh);
+
+		/* *** Define LMR_BW = f(control LMR) */
+		/* Assume that 5 kHz and 17 kHz are limits of LPR_BW control */
+		if (0 == sdf->pCoefForceLockLmrBw) {	/* only do these calc's
+							 * if LMR BW not
+							 * ForceLocked */
+			if (sdf->ControlLmr <= sdf->pCoefLmrBwThLo)
+				sdf->LmrBw = 5000;	/* lower limit is
+							 * 5 kHz */
+			else if (sdf->ControlLmr >= sdf->pCoefLmrBwThHi)
+				sdf->LmrBw = 17000;	/* upper limit is
+							 * 17 kHz */
+			else
+				sdf->LmrBw = 17000 -
+				    ((sdf->pCoefLmrBwSlSc *
+				      (sdf->pCoefLmrBwThHi -
+				       sdf->ControlLmr)) >>
+				     sdf->pCoefLmrBwSlSh);
+		}
+		/* *** Define LMR_Gain = f(control LMR)
+		 * Assume that Blending occurs across 20 dB range of
+		 * control LMR. For sake of listenability, approximate
+		 * antilog blending curve
+		 * To simplify antilog approx, scale control LMR back into
+		 * "RSSI in dB range" [0,60] */
+		sdf->ScaledControlLmr = sdf->ControlLmr >> 8;
+
+		/* how far below blend threshold are we? */
+		temp1_reg = sdf->pCoefLmrGaTh - sdf->ScaledControlLmr;
+		if (0 > temp1_reg)	/* We're not below threshold,
+					 * so no blending needed */
+			temp1_reg = 0;
+		temp2_reg = 20 - temp1_reg;	/* Blend range = 20 dB */
+		if (0 > temp2_reg)
+			temp2_reg = 0;	/* if beyond that range,
+					 * then clamp to 0 */
+
+		/* We want stereo separation (n dB) to rolloff linearly over
+		 * the 20 dB wide blend region.
+		 * this necessitates a particular rolloff for the blend
+		 * parameter, which is not obvious.
+		 * See sw_audio/log_approx.m for calculation of this rolloff,
+		 * implemented below...
+		 * Note that stereo_separation (in dB) = 20*log10((1+a)/(1-a)),
+		 * where a = blend scaler
+		 * appropriately scaled for 2^15.  This relationship sits at
+		 * the heart of why this curve is needed. */
+		if (15 <= temp2_reg)
+			temp3_reg = 264 * temp2_reg + 27487;
+		else if (10 <= temp2_reg)
+			temp3_reg = 650 * temp2_reg + 21692;
+		else if (5 <= temp2_reg)
+			temp3_reg = 1903 * temp2_reg + 9166;
+		else
+			temp3_reg = 3736 * temp2_reg;
+
+		sdf->LmrGa = temp3_reg;
+
+		if (32767 < sdf->LmrGa)
+			sdf->LmrGa = 32767;	/* Clamp to '1' */
+
+		/* *** Define LPR_Gain = f(control LPR)
+		 * Assume that SoftMuting occurs across 20 dB range of
+		 * control LPR
+		 * For sake of listenability, approximate antilog softmute
+		 * curve To simplify antilog approx, scale control LPR back
+		 * into "RSSI in dB range" [0,60] */
+		sdf->ScaledControlLpr = sdf->ControlLpr >> 8;
+		/* how far below softmute threshold are we? */
+		temp1_reg = sdf->pCoefLprGaTh - sdf->ScaledControlLpr;
+		if (0 > temp1_reg)	/* We're not below threshold,
+					 * so no softmute needed */
+			temp1_reg = 0;
+		temp2_reg = 20 - temp1_reg;	/* SoftmMute range = 20 dB */
+		if (0 > temp2_reg)
+			temp2_reg = 0;	/* if beyond that range,
+					 * then clamp to 0 */
+		/* Form 100*10^((temp2_reg-20)/20) approximation (antilog)
+		 * over range [0,20] dB
+		 * approximation in range [0,100], but we only want to
+		 * softmute down to -20 dB, no further */
+		if (16 < temp2_reg)
+			temp3_reg = 9 * temp2_reg - 80;
+		else if (12 < temp2_reg)
+			temp3_reg = 6 * temp2_reg - 33;
+		else if (8 < temp2_reg)
+			temp3_reg = 4 * temp2_reg - 8;
+		else
+			temp3_reg = 2 * temp2_reg + 9;
+
+		sdf->LprGa = 328 * temp3_reg;	/* close to 32767*(1/100) */
+
+		if (32767 < sdf->LprGa)
+			sdf->LprGa = 32767;	/* Clamp to '1' */
+
+		if (3277 > sdf->LprGa)
+			sdf->LprGa = 3277;	/* Clamp to 0.1*32767 =
+						 * -20 dB min gain */
+
+		/* *************** Bandwidth Sweep Algorithm ************ */
+		/* *** Calculate 2nd order filter coefficients as function
+		 * of desired BW. We do this by constructing piece-wise
+		 * linear filter coef's as f(BW), which is why we break the
+		 * calc's into different BW regions below.
+		 * coef(BW) = S*(M*BW + B)
+		 * For more info, see sw_audio/ws_filter.m checked into CVS */
+		if (0 == sdf->pCoefBypassBwCtl)	{ /* if ==1, then we just go
+						   * with default coef set */
+			/* determine if we run thru loop once or twice... */
+			if (1 == sdf->pCoefForceLockLmrBw)
+				temp4_reg = 1;	/* run thru once only to calc.
+						 * LPR coef's */
+			else
+				temp4_reg = 2;	/* run thru twice to calc.
+						 * LPR and LMR coef's */
+
+			/* Here's the big coef. calc. loop */
+			for (temp1_reg = 0; temp1_reg < temp4_reg;
+				temp1_reg++) {
+
+				if (0 == temp1_reg)
+					temp2_reg = (s16) sdf->LprBw;
+				else
+					temp2_reg = (s16) sdf->LmrBw;
+
+
+				if (6000 > temp2_reg) {
+					/* interval = [4.4kHz, 6.0kHz) */
+					sdf->B0M = 22102;
+					sdf->B0B = -2209;
+					sdf->B0S = 1;
+
+					sdf->B1over2M = 22089;
+					sdf->B1over2B = -2205;
+					sdf->B1over2S = 1;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = -24664;
+					sdf->A2B = 11698;
+					sdf->A2S = 2;
+				} else if (8000 > temp2_reg) {
+					/* interval = [6.0kHz, 8.0kHz) */
+					sdf->B0M = 22102;
+					sdf->B0B = -2209;
+					sdf->B0S = 1;
+
+					sdf->B1over2M = 22089;
+					sdf->B1over2B = -2205;
+					sdf->B1over2S = 1;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = -31231;
+					sdf->A2B = 18468;
+					sdf->A2S = 1;
+				} else if (10000 > temp2_reg) {
+					/* interval = [8.0kHz, 10.0kHz) */
+					sdf->B0M = 28433;
+					sdf->B0B = -4506;
+					sdf->B0S = 1;
+
+					sdf->B1over2M = 28462;
+					sdf->B1over2B = -4584;
+					sdf->B1over2S = 1;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = -14811;
+					sdf->A2B = 12511;
+					sdf->A2S = 1;
+				} else if (12000 > temp2_reg) {
+					/* interval = [10.0kHz, 12.0kHz) */
+					sdf->B0M = 28433;
+					sdf->B0B = -4506;
+					sdf->B0S = 1;
+
+					sdf->B1over2M = 28462;
+					sdf->B1over2B = -4584;
+					sdf->B1over2S = 1;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = -181;
+					sdf->A2B = 5875;
+					sdf->A2S = 1;
+				} else if (14000 > temp2_reg) {
+					/* interval = [12.0kHz, 14.0kHz) */
+					sdf->B0M = 18291;
+					sdf->B0B = -4470;
+					sdf->B0S = 2;
+
+					sdf->B1over2M = 18461;
+					sdf->B1over2B = -4597;
+					sdf->B1over2S = 2;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = 14379;
+					sdf->A2B = -2068;
+					sdf->A2S = 1;
+				} else if (16000 > temp2_reg) {
+					/* interval = [14.0kHz, 16.0kHz) */
+					sdf->B0M = 18291;
+					sdf->B0B = -4470;
+					sdf->B0S = 2;
+
+					sdf->B1over2M = 18461;
+					sdf->B1over2B = -4597;
+					sdf->B1over2S = 2;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = 30815;
+					sdf->A2B = -12481;
+					sdf->A2S = 1;
+				} else if (18000 > temp2_reg) {
+					/* interval = [16.0kHz, 18.0kHz) */
+					sdf->B0M = 24740;
+					sdf->B0B = -9152;
+					sdf->B0S = 2;
+
+					sdf->B1over2M = 24730;
+					sdf->B1over2B = -9142;
+					sdf->B1over2S = 2;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = 25631;
+					sdf->A2B = -13661;
+					sdf->A2S = 2;
+				} else {
+					/* interval = [18.0kHz, 19.845kHz) */
+					sdf->B0M = 24740;
+					sdf->B0B = -9152;
+					sdf->B0S = 2;
+
+					sdf->B1over2M = 24730;
+					sdf->B1over2B = -9142;
+					sdf->B1over2S = 2;
+
+					sdf->A1over2M = 31646;
+					sdf->A1over2B = -15695;
+					sdf->A1over2S = 2;
+
+					sdf->A2M = 19382;
+					sdf->A2B = -12183;
+					sdf->A2S = 4;
+				}
+
+				if (0 == temp1_reg) {
+					/* The piece-wise linear eq's are
+					 * based on a scaled version
+					 * (32768/22050) of BW */
+
+					/* Note 32768/22050 <-> 2*(16384/22050)
+					 * <-> 2*((16384/22050)*32768)>>15 */
+					sdf->AdjBw = ((temp2_reg << 1) *
+						24348) >> 15;
+
+					/* temp = mx */
+					temp3_reg = (sdf->B0M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LprB0 = sdf->B0S *
+						(temp3_reg + sdf->B0B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->B1over2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LprB1over2 = sdf->B1over2S *
+						(temp3_reg + sdf->B1over2B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->A1over2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LprA1over2 = -sdf->A1over2S *
+						(temp3_reg + sdf->A1over2B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->A2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LprA2 = -sdf->A2S *
+						(temp3_reg + sdf->A2B);
+					/* *** end LPR channel --
+					 * LPR coefficients now ready for
+					 * Stereo Path next time */
+				} else {
+					/* The piece-wise linear eq's are
+					 * based on a scaled version
+					 * (32768/22050) of BW */
+
+					/* Note 32768/22050 <-> 2*(16384/22050)
+					 * <-> 2*((16384/22050)*32768)>>15 */
+					sdf->AdjBw = ((temp2_reg << 1) *
+						24348) >> 15;
+
+					/* temp = mx */
+					temp3_reg = (sdf->B0M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LmrB0 = sdf->B0S *
+						(temp3_reg + sdf->B0B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->B1over2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LmrB1over2 = sdf->B1over2S *
+						(temp3_reg + sdf->B1over2B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->A1over2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LmrA1over2 = -sdf->A1over2S *
+						(temp3_reg + sdf->A1over2B);
+
+					/* temp = mx */
+					temp3_reg = (sdf->A2M *
+						sdf->AdjBw) >> 15;
+
+					/* y = S*(mx + b) */
+					sdf->LmrA2 = -sdf->A2S *
+						(temp3_reg + sdf->A2B);
+					/* *** end LMR channel -- LMR
+					 * coefficients now ready for Stereo
+					 * Path next time */
+				}
+			}	/* end for (temp1_reg=0... */
+			if (1 == sdf->pCoefForceLockLmrBw) {
+				/* if Force Lock LMR BW = LPR BW */
+				/* then set LMR coef's = LPR coef's */
+				sdf->LmrB0 = sdf->LprB0;
+				sdf->LmrB1over2 = sdf->LprB1over2;
+				sdf->LmrA1over2 = sdf->LprA1over2;
+				sdf->LmrA2 = sdf->LprA2;
+			}
+
+		}		/* end if (0 == sdf->pCoef_BypassBwCtl) */
+		/* eI 108 24th Feb 06 Streo Matrix part moved after
+		 * weak signal processing. */
+		if (0 == sdf->pCoefBypassBlend)
+			temp1_reg = sdf->LmrGa;	/* Blend */
+		else
+			temp1_reg = 1;
+
+		if (sdf->pCoefForcedMono)	/* Forced Mono */
+			temp1_reg = 0;
+
+		if (0 == sdf->pCoefBypassSoftmute) {
+
+			/* SoftMute applied to LPR */
+			sdf->temp2_reg_sm = sdf->LprGa;
+
+			temp2_reg_32 = sdf->LprGa * temp1_reg;
+
+			/* SoftMute applied to LMR */
+			sdf->temp3_reg_sm = (temp2_reg_32) >> 15;
+		} else {
+			sdf->temp2_reg_sm = 1;	/* eI 108 24th Feb 06 update
+						 * global variable for IIR
+						 * filter. */
+			sdf->temp3_reg_sm = temp1_reg;
+		}
+
+	}			/* end if (0 == sdf->DecRssi) */
+
+	sdf->DecRssi = ((sdf->DecRssi + 1) % 16);	/* end decimation
+							 * by 16 */
+
+	/* *** End Weak Signal Processing ********************************** */
+	/* ***************************************************************** */
+}
diff --git a/drivers/media/radio/stfm1000/stfm1000-filter.h b/drivers/media/radio/stfm1000/stfm1000-filter.h
new file mode 100644
index 000000000000..d24e3e9244b8
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-filter.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef STFM1000_FILTER_H
+#define STFM1000_FILTER_H
+
+/* STFM1000 Black Box Filter parameters */
+struct stfm1000_filter_parms {
+	s16 LprXzz;		/* LPR x(n-2) stereo filter */
+	s16 LmrXzz;		/* LMR x(n-2) stereo filter */
+	s16 LprYzz;		/* LPR y(n-2) stereo filter */
+	s16 LmrYzz;		/* LMR y(n-2) stereo filter */
+
+	s16 LprXz;		/* LPR x(n-1) stereo filter */
+	s16 LmrXz;		/* LMR x(n-1) stereo filter */
+	s16 FilteredLpr;	/* LPR filter output */
+	s16 FilteredLmr;	/* LMR filter output */
+
+	s16 LprB0;		/* LPR stereo filter coef */
+	s16 LprB1over2;		/* LPR stereo filter coef */
+	s16 LprA1over2;		/* LPR stereo filter coef */
+	s16 LprA2;		/* LPR stereo filter coef */
+
+	s16 LmrB0;		/* LMR stereo filter coef */
+	s16 LmrB1over2;		/* LMR stereo filter coef */
+	s16 LmrA1over2;		/* LMR stereo filter coef */
+	s16 LmrA2;		/* LMR stereo filter coef */
+
+	s16 LprYz;		/* LPR y(n-1) stereo filter */
+	s16 LmrYz;		/* LMR y(n-1) stereo filter */
+
+	s16 Left;		/* left channel audio out */
+	s16 Right;		/* right channel audio out */
+	s32 LeftLb;		/* left channel dc estimate */
+	s32 RightLb;		/* right channel dc estimate */
+
+	u32 RssiDecoded;	/* integer decoded RSSI */
+
+	u16 RssiMant;		/* mantissa of float-coded RSSI */
+	s16 RssiLog;		/* 10log10(decoded RSSI) */
+
+	u16 RssiExp;		/* exponent of float-coded RSSI */
+	u16 RssiLb;		/* leaky bucket dc of rssi */
+
+	u16 Prssi;		/* power of 2 for RSSI */
+	u16 TrueRssi;		/* DC estimate of log RSSI */
+
+	u16 ScaledRssiDecoded;	/* scaled log RSSI */
+	s16 Echo;		/* Echo info from HiPass(RSSI) */
+	u16 ScaledRssiDecodedZ;	/* history buffer for above */
+	u16 ScaledRssiDecodedZz;/* ditto */
+
+	u16 ScaledTrueRssi;	/* scaled version for precision */
+	u16 FilteredRssi;	/* Attack/Decay filtered RSSI */
+	u16 PrevFilteredRssi;	/* previous version of above */
+
+	u16 EchoLb;		/* DC estimate of Echo energy */
+	u16 TrueEcho;		/* scaled version of above */
+	u16 FilteredEchoLpr;	/* Attack/Decay filt. Echo */
+	u16 PrevFilteredEchoLpr;/* previous version of above */
+	u16 FilteredEchoLmr;	/* Attack/Decay filt. Echo */
+	u16 PrevFilteredEchoLmr;/* previous version of above */
+	s16 GatedEcho;		/* Echo gated by threshold */
+
+	s16 ControlLpr;		/* master control for LPR */
+	s16 ControlLmr;		/* master control for LMR */
+	u16 LprBw;		/* LPR Bandwidth desired */
+	u16 LmrBw;		/* LMR Bandwidth desired */
+	u16 LprGa;		/* LPR Gain (SoftMute) desired */
+	u16 LmrGa;		/* LMR Gain (Blend) desired */
+	u16 ScaledControlLmr;	/* Scaled down version Ctl LMR */
+	u16 ScaledControlLpr;	/* Scaled down version Ctl LPR */
+
+	s16 B0M;		/* BW ctl B0 coef slope */
+	s16 B0B;		/* BW ctl B0 coef y-intercept */
+
+	u16 B0S;		/* BW ctl B0 coef scale */
+	s16 B1over2M;		/* BW ctl B1/2 coef slope */
+
+	s16 B1over2B;		/* BW ctl B1/2 coef y-intercept */
+	s16 A1over2B;		/* BW ctl A1/2 coef y-intercept */
+
+	u16 B1over2S;		/* BW ctl B1/2 coef scale */
+	u16 A1over2S;		/* BW ctl A1/2 coef scale */
+
+	s16 A1over2M;		/* BW ctl A1/2 coef slope */
+	u16 A2S;		/* BW ctl A2 coef scale */
+
+	s16 A2M;		/* BW ctl A2 coef slope */
+	s16 A2B;		/* BW ctl A2 coef y-intercept */
+
+	u16 AdjBw;		/* Desired Filter BW scaled into range */
+
+	u16 DecRssi;		/*! Decimation modulo counter */
+
+	s16 ScaleAudio;		/*! Scale factor for Audio Mute */
+	u8 MuteAudio;		/*! Control for muting audio */
+	u8 PrevMuteAudio;	/*! History of control for muting audio */
+	u8 MuteActionFlag;	/*! Indicator of when mute ramping occurs */
+
+	u32 Acc;		/* mimics H/W accumulator */
+	s32 Acc_signed;
+	s16 temp1_reg;		/* mimics 16 bit register */
+	s16 temp2_reg;		/* mimics 16 bit register */
+	s16 temp3_reg;		/* mimics 16 bit register */
+	s16 temp4_reg;		/* mimics 16 bit register */
+	s16 temp5_reg;		/* mimics 16 bit register */
+
+	/* *** Programmable Coefficients */
+	u16 pCoefRssiAttack;	/* prog coef RSSI attack */
+	u16 pCoefRssiDecay;	/* prog coef RSSI decay */
+	u16 pCoefEchoLprAttack;	/* prog coef Echo LPR attack */
+	u16 pCoefEchoLprDecay;	/* prog coef Echo LPR decay */
+	u16 pCoefEchoLmrAttack;	/* prog coef Echo LMR attack */
+	u16 pCoefEchoLmrDecay;	/* prog coef Echo LMR decay */
+
+	u16 pCoefEchoTh;	/* prog coef Echo threshold */
+
+	u16 pCoefEchoScLpr;	/* prog coef scale Echo LPR infl. */
+	u16 pCoefEchoScLmr;	/* prog coef scale Echo LMR infl. */
+	u16 pCoefEchoShLpr;	/* prog coef shift Echo LPR infl. */
+	u16 pCoefEchoShLmr;	/* prog coef shift Echo LMR infl. */
+
+	u16 pCoefLprBwThLo;	/* prog coef Low Th LPR BW */
+	u16 pCoefLprBwThHi;	/* prog coef High Th LPR BW */
+	u16 pCoefLmrBwThLo;	/* prog coef Low Th LMR BW */
+	u16 pCoefLmrBwThHi;	/* prog coef High Th LMR BW */
+
+	u16 pCoefLprGaTh;	/* prog coef Th LPR Gain (SoftMute) */
+	u16 pCoefLmrGaTh;	/* prog coef Th LMR Gain (Blend) */
+
+	u16 pCoefLprBwSlSc;	/* prog coef Slope scale LPR BW */
+	u16 pCoefLprBwSlSh;	/* prog coef Slope shift LPR BW */
+	u16 pCoefLmrBwSlSc;	/* prog coef Slope scale LMR BW */
+	u16 pCoefLmrBwSlSh;	/* prog coef Slope shift LMR BW */
+	u16 pCoefLprGaSlSc;	/* prog coef Slope scale LPR Gain */
+	u16 pCoefLprGaSlSh;	/* prog coef Slope shift LPR Gain */
+
+	u8 pCoefForcedMono;	/* Forced Mono control bit */
+	u8 pCoefBypassBlend;	/* Forced bypass of stereo blend */
+	u8 pCoefBypassSoftmute;	/* Forced bypass of softmute */
+	u8 pCoefBypassDcCut;	/* Forced bypass of audio DC Cut filter */
+
+	u8 pCoefBypassBwCtl;	/* Forced bypass of bandwidth control */
+	u8 pCoefForceLockLmrBw;	/* prog flag to force LMR BW=LPR BW */
+
+	/* XXX added here, they were global */
+	s16 temp2_reg_sm;
+	s16 temp3_reg_sm;
+
+};
+
+/* STFM1000 Black Box Filter Function prototypes */
+void stfm1000_filter_reset(struct stfm1000_filter_parms *sdf);
+void stfm1000_filter_decode(struct stfm1000_filter_parms *sdf, s16 Lpr,
+	s16 Lmr, u16 Rssi);
+
+static inline s16
+stfm1000_filter_value_left(struct stfm1000_filter_parms *sdf)
+{
+	return sdf->Left;
+}
+
+static inline s16
+stfm1000_filter_value_right(struct stfm1000_filter_parms *sdf)
+{
+	return sdf->Right;
+}
+
+static inline u32
+stfm1000_filter_value_rssi(struct stfm1000_filter_parms *sdf)
+{
+	return sdf->RssiDecoded;
+}
+
+#endif
diff --git a/drivers/media/radio/stfm1000/stfm1000-i2c.c b/drivers/media/radio/stfm1000/stfm1000-i2c.c
new file mode 100644
index 000000000000..5ddeb3a5fd3a
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-i2c.c
@@ -0,0 +1,452 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+
+#include <linux/version.h>      /* for KERNEL_VERSION MACRO     */
+
+#include "stfm1000.h"
+
+#define stfm1000_i2c_debug(p, fmt, arg...) \
+	do { \
+		if ((p)->dbgflg & STFM1000_DBGFLG_I2C) \
+			printk(KERN_INFO "stfm1000: " fmt, ##arg); \
+	} while (0)
+
+static const char *reg_names[STFM1000_NUM_REGS] = {
+#undef REGNAME
+#define REGNAME(x) \
+	[STFM1000_ ## x / 4] = #x ""
+
+	REGNAME(TUNE1),
+	REGNAME(SDNOMINAL),
+	REGNAME(PILOTTRACKING),
+	REGNAME(INITIALIZATION1),
+	REGNAME(INITIALIZATION2),
+	REGNAME(INITIALIZATION3),
+	REGNAME(INITIALIZATION4),
+	REGNAME(INITIALIZATION5),
+	REGNAME(INITIALIZATION6),
+	REGNAME(REF),
+	REGNAME(LNA),
+	REGNAME(MIXFILT),
+	REGNAME(CLK1),
+	REGNAME(CLK2),
+	REGNAME(ADC),
+	REGNAME(AGC_CONTROL1),
+	REGNAME(AGC_CONTROL2),
+	REGNAME(DATAPATH),
+	REGNAME(RMS),
+	REGNAME(AGC_STAT),
+	REGNAME(SIGNALQUALITY),
+	REGNAME(DCEST),
+	REGNAME(RSSI_TONE),
+	REGNAME(PILOTCORRECTION),
+	REGNAME(ATTENTION),
+	REGNAME(CLK3),
+	REGNAME(CHIPID),
+#undef REGNAME
+};
+
+static const int stfm1000_rw_regs[] = {
+	STFM1000_TUNE1,
+	STFM1000_SDNOMINAL,
+	STFM1000_PILOTTRACKING,
+	STFM1000_INITIALIZATION1,
+	STFM1000_INITIALIZATION2,
+	STFM1000_INITIALIZATION3,
+	STFM1000_INITIALIZATION4,
+	STFM1000_INITIALIZATION5,
+	STFM1000_INITIALIZATION6,
+	STFM1000_REF,
+	STFM1000_LNA,
+	STFM1000_MIXFILT,
+	STFM1000_CLK1,
+	STFM1000_CLK2,
+	STFM1000_ADC,
+	STFM1000_AGC_CONTROL1,
+	STFM1000_AGC_CONTROL2,
+	STFM1000_DATAPATH,
+	STFM1000_ATTENTION,	/* it's both WR/RD */
+};
+
+static const int stfm1000_ra_regs[] = {
+	STFM1000_RMS,
+	STFM1000_AGC_STAT,
+	STFM1000_SIGNALQUALITY,
+	STFM1000_DCEST,
+	STFM1000_RSSI_TONE,
+	STFM1000_PILOTCORRECTION,
+	STFM1000_ATTENTION,	/* it's both WR/RD - always read */
+	STFM1000_CLK3,
+	STFM1000_CHIPID
+};
+
+static int verify_writes;
+
+void stfm1000_setup_reg_set(struct stfm1000 *stfm1000)
+{
+	int i, reg;
+
+	/* set up register sets (read/write) */
+	for (i = 0; i < ARRAY_SIZE(stfm1000_rw_regs); i++) {
+		reg = stfm1000_rw_regs[i] / 4;
+		stfm1000->reg_rw_set[reg / 32] |= 1U << (reg & 31);
+		/* printk(KERN_INFO "STFM1000: rw <= %d\n", reg); */
+	}
+
+	/* for (i = 0; i < ARRAY_SIZE(stfm1000->reg_rw_set); i++)
+		printk("RW[%d] = 0x%08x\n", i, stfm1000->reg_rw_set[i]); */
+
+	/* set up register sets (read only) */
+	for (i = 0; i < ARRAY_SIZE(stfm1000_ra_regs); i++) {
+		reg = stfm1000_ra_regs[i] / 4;
+		stfm1000->reg_ra_set[reg / 32] |= 1U << (reg & 31);
+		/* printk(KERN_INFO "STFM1000: rw <= %d\n", reg); */
+	}
+	/* for (i = 0; i < ARRAY_SIZE(stfm1000->reg_ra_set); i++)
+		printk("RO[%d] = 0x%08x\n", i, stfm1000->reg_ra_set[i]); */
+
+	/* clear dirty */
+	memset(stfm1000->reg_dirty_set, 0, sizeof(stfm1000->reg_dirty_set));
+}
+
+static int stfm1000_reg_is_rw(struct stfm1000 *stfm1000, int reg)
+{
+	reg >>= 2;
+	return !!(stfm1000->reg_rw_set[reg / 32] & (1 << (reg & 31)));
+}
+
+static int stfm1000_reg_is_ra(struct stfm1000 *stfm1000, int reg)
+{
+	reg >>= 2;
+	return !!(stfm1000->reg_ra_set[reg / 32] & (1 << (reg & 31)));
+}
+
+static int stfm1000_reg_is_dirty(struct stfm1000 *stfm1000, int reg)
+{
+	reg >>= 2;
+	return !!(stfm1000->reg_dirty_set[reg / 32] & (1 << (reg & 31)));
+}
+
+static void stfm1000_reg_set_dirty(struct stfm1000 *stfm1000, int reg)
+{
+	reg >>= 2;
+	stfm1000->reg_dirty_set[reg / 32] |= 1 << (reg & 31);
+}
+
+static inline int stfm1000_reg_is_writeable(struct stfm1000 *stfm1000, int reg)
+{
+	return stfm1000_reg_is_rw(stfm1000, reg);
+}
+
+static inline int stfm1000_reg_is_readable(struct stfm1000 *stfm1000, int reg)
+{
+	return stfm1000_reg_is_rw(stfm1000, reg) ||
+	       stfm1000_reg_is_ra(stfm1000, reg);
+}
+
+/********************************************************/
+
+static int write_reg_internal(struct stfm1000 *stfm1000, int reg, u32 value)
+{
+	u8 values[5];
+	int ret;
+
+	stfm1000_i2c_debug(stfm1000, "%s(%s - 0x%02x, 0x%08x)\n", __func__,
+		reg_names[reg / 4], reg, value);
+
+	values[0] = (u8)reg;
+	values[1] = (u8)value;
+	values[2] = (u8)(value >> 8);
+	values[3] = (u8)(value >> 16);
+	values[4] = (u8)(value >> 24);
+	ret = i2c_master_send(stfm1000->client, values, 5);
+	if (ret < 0)
+		return ret;
+	return 0;
+}
+
+static int read_reg_internal(struct stfm1000 *stfm1000, int reg, u32 *value)
+{
+	u8 regb = reg;
+	u8 values[4];
+	int ret;
+
+	ret = i2c_master_send(stfm1000->client, &regb, 1);
+	if (ret < 0)
+		goto out;
+	ret = i2c_master_recv(stfm1000->client, values, 4);
+	if (ret < 0)
+		goto out;
+	*value = (u32)values[0] | ((u32)values[1] << 8) |
+		 ((u32)values[2] << 16) | ((u32)values[3] << 24);
+	ret = 0;
+
+	stfm1000_i2c_debug(stfm1000, "%s(%s - 0x%02x, 0x%08x)\n", __func__,
+		reg_names[reg / 4], reg, *value);
+out:
+	return ret;
+}
+
+int stfm1000_raw_write(struct stfm1000 *stfm1000, int reg, u32 value)
+{
+	int ret;
+
+	mutex_lock(&stfm1000->xfer_lock);
+	ret = write_reg_internal(stfm1000, reg, value);
+	mutex_unlock(&stfm1000->xfer_lock);
+
+	if (ret < 0)
+		dev_err(&stfm1000->client->dev, "%s: failed", __func__);
+
+	return ret;
+}
+
+int stfm1000_raw_read(struct stfm1000 *stfm1000, int reg, u32 *value)
+{
+	int ret;
+
+	mutex_lock(&stfm1000->xfer_lock);
+	ret = read_reg_internal(stfm1000, reg, value);
+	mutex_unlock(&stfm1000->xfer_lock);
+
+	if (ret < 0)
+		dev_err(&stfm1000->client->dev, "%s: failed", __func__);
+
+	return ret;
+}
+
+static inline void stfm1000_set_shadow_reg(struct stfm1000 *stfm1000,
+	int reg, u32 val)
+{
+	stfm1000->shadow_regs[reg / 4] = val;
+}
+
+static inline u32 stfm1000_get_shadow_reg(struct stfm1000 *stfm1000, int reg)
+{
+	return stfm1000->shadow_regs[reg / 4];
+}
+
+int stfm1000_write(struct stfm1000 *stfm1000, int reg, u32 value)
+{
+	int ret;
+
+	if (!stfm1000_reg_is_writeable(stfm1000, reg)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	mutex_lock(&stfm1000->xfer_lock);
+
+	/* same value as last one written? */
+	if (stfm1000_reg_is_dirty(stfm1000, reg) &&
+		stfm1000_get_shadow_reg(stfm1000, reg) == value) {
+		ret = 0;
+
+		stfm1000_i2c_debug(stfm1000, "%s - HIT "
+			"(%s - 0x%02x, 0x%08x)\n", __func__,
+			reg_names[reg / 4], reg, value);
+
+		goto out_unlock;
+	}
+
+	/* actually write the register */
+	ret = write_reg_internal(stfm1000, reg, value);
+	if (ret < 0)
+		goto out_unlock;
+
+	/* update shadow register & mark it as dirty */
+	/* only if register is not read always */
+	if (!stfm1000_reg_is_ra(stfm1000, reg)) {
+		stfm1000_set_shadow_reg(stfm1000, reg, value);
+		stfm1000_reg_set_dirty(stfm1000, reg);
+	}
+
+out_unlock:
+	mutex_unlock(&stfm1000->xfer_lock);
+
+out:
+	if (ret < 0)
+		dev_err(&stfm1000->client->dev, "%s: failed", __func__);
+
+	if (verify_writes) {
+		u32 value2 = ~0;
+
+		stfm1000_raw_read(stfm1000, reg, &value2);
+
+		stfm1000_i2c_debug(stfm1000, "%s - VER "
+			"(%s - 0x%02x, W=0x%08x V=0x%08x) %s\n", __func__,
+			reg_names[reg / 4], reg, value, value2,
+			value == value2 ? "OK" : "** differs **");
+	}
+
+	return ret;
+}
+
+int stfm1000_read(struct stfm1000 *stfm1000, int reg, u32 *value)
+{
+	int ret = 0;
+
+	if (!stfm1000_reg_is_readable(stfm1000, reg)) {
+		ret = -EINVAL;
+		printk(KERN_INFO "%s: !readable(%d)\n", __func__, reg);
+		goto out;
+	}
+
+	mutex_lock(&stfm1000->xfer_lock);
+
+	/* if the register can be written & is dirty, use the shadow */
+	if (stfm1000_reg_is_writeable(stfm1000, reg) &&
+		stfm1000_reg_is_dirty(stfm1000, reg)) {
+
+		*value = stfm1000_get_shadow_reg(stfm1000, reg);
+		ret = 0;
+
+		stfm1000_i2c_debug(stfm1000, "%s - HIT "
+			"(%s - 0x%02x, 0x%08x)\n", __func__,
+			reg_names[reg / 4], reg, *value);
+
+		goto out_unlock;
+	}
+
+	/* register must be read */
+	ret = read_reg_internal(stfm1000, reg, value);
+	if (ret < 0)
+		goto out;
+
+	/* if the register is writeable, update shadow */
+	if (stfm1000_reg_is_writeable(stfm1000, reg)) {
+		stfm1000_set_shadow_reg(stfm1000, reg, *value);
+		stfm1000_reg_set_dirty(stfm1000, reg);
+	}
+
+out_unlock:
+	mutex_unlock(&stfm1000->xfer_lock);
+
+out:
+	if (ret < 0)
+		dev_err(&stfm1000->client->dev, "%s: failed", __func__);
+
+	return ret;
+}
+
+int stfm1000_write_masked(struct stfm1000 *stfm1000, int reg, u32 value,
+	u32 mask)
+{
+	int ret = 0;
+	u32 old_value;
+
+	if (!stfm1000_reg_is_writeable(stfm1000, reg)) {
+		ret = -EINVAL;
+		printk(KERN_ERR "%s: !writeable(%d)\n", __func__, reg);
+		goto out;
+	}
+
+	mutex_lock(&stfm1000->xfer_lock);
+
+	/* if the register wasn't written before, read it */
+	if (!stfm1000_reg_is_dirty(stfm1000, reg)) {
+		ret = read_reg_internal(stfm1000, reg, &old_value);
+		if (ret != 0)
+			goto out_unlock;
+	} else	/* register was written, use the last value */
+		old_value = stfm1000_get_shadow_reg(stfm1000, reg);
+
+	/* perform masking */
+	value = (old_value & ~mask) | (value & mask);
+
+	/* if we write the same value, don't bother */
+	if (stfm1000_reg_is_dirty(stfm1000, reg) && value == old_value) {
+		ret = 0;
+
+		stfm1000_i2c_debug(stfm1000, "%s - HIT "
+			"(%s - 0x%02x, 0x%08x)\n", __func__,
+			reg_names[reg / 4], reg, value);
+
+		goto out_unlock;
+	}
+
+	/* actually write the register to the chip */
+	ret = write_reg_internal(stfm1000, reg, value);
+	if (ret < 0)
+		goto out_unlock;
+
+	/* if no error, update the shadow register and mark it as dirty */
+	stfm1000_set_shadow_reg(stfm1000, reg, value);
+	stfm1000_reg_set_dirty(stfm1000, reg);
+
+out_unlock:
+	mutex_unlock(&stfm1000->xfer_lock);
+
+out:
+	if (ret < 0)
+		dev_err(&stfm1000->client->dev, "%s: failed", __func__);
+
+	if (verify_writes) {
+		u32 value2 = ~0;
+
+		stfm1000_raw_read(stfm1000, reg, &value2);
+
+		stfm1000_i2c_debug(stfm1000, "%s - VER "
+			"(%s - 0x%02x, W=0x%08x V=0x%08x) %s\n", __func__,
+			reg_names[reg / 4], reg, value, value2,
+			value == value2 ? "OK" : "** differs **");
+	}
+
+	return ret;
+}
+
+int stfm1000_set_bits(struct stfm1000 *stfm1000, int reg, u32 value)
+{
+	return stfm1000_write_masked(stfm1000, reg, value, value);
+}
+
+int stfm1000_clear_bits(struct stfm1000 *stfm1000, int reg, u32 value)
+{
+	return stfm1000_write_masked(stfm1000, reg, ~value, value);
+}
+
+int stfm1000_write_regs(struct stfm1000 *stfm1000,
+	const struct stfm1000_reg *reg)
+{
+	int ret;
+
+	for (; reg && reg->regno != STFM1000_REG_END; reg++) {
+
+		if (reg->regno == STFM1000_REG_DELAY) {
+			msleep(reg->value);
+			continue;
+		}
+
+		if (reg->regno & STFM1000_REG_SET_BITS_MASK)
+			ret = stfm1000_set_bits(stfm1000, reg->regno & 0xff,
+				reg->value);
+		else if (reg->regno & STFM1000_REG_CLEAR_BITS_MASK)
+			ret = stfm1000_clear_bits(stfm1000, reg->regno & 0xff,
+				reg->value);
+		else
+			ret = stfm1000_write(stfm1000, reg->regno, reg->value);
+
+		if (ret != 0) {
+			printk(KERN_ERR "%s: failed to write reg 0x%x "
+				"with 0x%08x\n",
+				__func__, reg->regno, reg->value);
+			return ret;
+		}
+	}
+	return 0;
+}
diff --git a/drivers/media/radio/stfm1000/stfm1000-rds.c b/drivers/media/radio/stfm1000/stfm1000-rds.c
new file mode 100644
index 000000000000..5f63052d00c2
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-rds.c
@@ -0,0 +1,1529 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+
+#include "stfm1000.h"
+
+#include "stfm1000-rds.h"
+
+#define bitstream_to_rds_state(b)	\
+	container_of(b, struct stfm1000_rds_state, bitstream)
+#define demod_to_rds_state(d)		\
+	container_of(d, struct stfm1000_rds_state, demod)
+#define pkt_to_rds_state(p)		\
+	container_of(p, struct stfm1000_rds_state, pkt)
+#define text_to_rds_state(t)		\
+	container_of(t, struct stfm1000_rds_state, text)
+#define rds_state_to_stfm1000(r)	\
+	container_of(r, struct stfm1000, rds_state)
+
+#define TADJSH 8 /*Shifts used in bitslice loop filter */
+
+/* Reverse of Matlab's Fquant (see MatchedFilterDecomposition.m), so that */
+/* mixandsum code is easy;   Used by rds_bitstream_stfmdemod.arm */
+const s16 u16_rds_basis[2*RDS_BASISLENGTH+8] = {
+	14, 24, 34, 43, 50, 56, 60, 62, 62,
+	60, 55, 49, 41, 32, 22, 11, 14, 24,
+	34, 43, 50, 56, 60, 62, 62, 60, 55,
+	49, 41, 32, 22, 11, 14, 24, 34, 43,
+	50, 56, 60, 62
+};
+
+static int bits_free(struct stfm1000_rds_bitstream *rdsb)
+{
+	/* Do not show the last one word free. */
+	int FreeSpace = rdsb->TailBitCount - rdsb->HeadBitCount - 32;
+
+	if (FreeSpace < 0)
+		FreeSpace = (RDS_BITBUFSIZE * 32) + FreeSpace;
+	return FreeSpace;
+}
+
+static void put1bit(struct stfm1000_rds_bitstream *rdsb, int bit)
+{
+	int index = (rdsb->HeadBitCount >> 5);
+	u32 CurBit = (rdsb->HeadBitCount & 0x1f);
+	u32 CurWord = rdsb->buf[index];
+
+	if (CurBit == 0)
+		CurWord = 0;
+
+	CurWord = CurWord | (((u32)bit & 1) << CurBit);
+	rdsb->buf[index] = CurWord;
+	rdsb->HeadBitCount++;
+	if (rdsb->HeadBitCount >= RDS_BITBUFSIZE * 32)
+		rdsb->HeadBitCount = 0;
+}
+
+static int get1bit(struct stfm1000_rds_bitstream *rdsb)
+{
+	int Bit = 0;
+	int index = (rdsb->TailBitCount >> 5);
+	int CurBit = (rdsb->TailBitCount & 0x1f);
+	u32 CurWord = rdsb->buf[index];
+
+	Bit = (CurWord >> CurBit) & 1;
+	rdsb->TailBitCount++;
+	if (rdsb->TailBitCount == RDS_BITBUFSIZE*32)
+		rdsb->TailBitCount = 0;
+
+	return Bit;
+}
+
+static int bits_filled(struct stfm1000_rds_bitstream *rdsb)
+{
+	int FilledSpace = rdsb->HeadBitCount - rdsb->TailBitCount;
+
+	if (FilledSpace < 0)
+		FilledSpace = (RDS_BITBUFSIZE * 32) + FilledSpace;
+	return FilledSpace;
+}
+
+static void rds_mix_msg(struct stfm1000_rds_demod *rdsd, u8 MixSetting)
+{
+	if (rdsd->mix_msg_pending)
+		rdsd->mix_msg_overrun++;
+	rdsd->mix_msg = MixSetting;
+	rdsd->mix_msg_pending = 1;
+
+	/* signal monitor thread */
+	stfm1000_monitor_signal(
+		rds_state_to_stfm1000(demod_to_rds_state(rdsd)),
+		EVENT_RDS_MIXFILT);
+}
+
+/* call with interrupts disabled please */
+int stfm1000_rds_mix_msg_get(struct stfm1000_rds_state *rds)
+{
+	struct stfm1000_rds_demod *rdsd = &rds->demod;
+
+	if (!rdsd->mix_msg_pending)
+		return -1;
+
+	return rdsd->mix_msg;
+}
+
+/* call with interrupts disabled please */
+int stfm1000_rds_mix_msg_processed(struct stfm1000_rds_state *rds, int mix_msg)
+{
+	struct stfm1000_rds_demod *rdsd = &rds->demod;
+
+	if (!rdsd->mix_msg_pending)
+		return -1;
+
+	rdsd->mix_msg_pending = 0;
+
+	/* update the completion indication bit */
+	if ((mix_msg & 0x8) == 0)
+		rdsd->MixPopDone = 1;
+
+	/* this is reflected off the hardware register */
+	rdsd->rds_mix_offset = mix_msg & 1;
+
+	if (rdsd->mix_msg != mix_msg) {
+		rdsd->mix_msg_processed_changed++;
+		return -1;
+	}
+	return 0;
+}
+
+static void rds_sdnominal_msg(struct stfm1000_rds_demod *rdsd, int sdnominal)
+{
+	if (rdsd->sdnominal_msg_pending)
+		rdsd->sdnominal_msg_overrun++;
+	rdsd->sdnominal_msg = sdnominal;
+	rdsd->sdnominal_msg_pending = 1;
+
+	/* signal monitor thread */
+	stfm1000_monitor_signal(
+		rds_state_to_stfm1000(demod_to_rds_state(rdsd)),
+		EVENT_RDS_SDNOMINAL);
+}
+
+/* call with interrupts disabled please */
+int stfm1000_rds_sdnominal_msg_get(struct stfm1000_rds_state *rds)
+{
+	struct stfm1000_rds_demod *rdsd = &rds->demod;
+
+	if (!rdsd->sdnominal_msg_pending)
+		return 0;
+
+	return rdsd->sdnominal_msg;
+}
+
+/* call with interrupts disabled please */
+int stfm1000_rds_sdnominal_msg_processed(struct stfm1000_rds_state *rds,
+	int sdnominal_msg)
+{
+	struct stfm1000_rds_demod *rdsd = &rds->demod;
+
+	if (!rdsd->sdnominal_msg_pending)
+		return -1;
+
+	rdsd->sdnominal_msg_pending = 0;
+	return 0;
+}
+
+void demod_loop(struct stfm1000_rds_bitstream *rdsb,
+	struct stfm1000_rds_demod *rdsd)
+{
+	s32 filter_out;
+	u32 freeSpace;
+	s32 decomp_hist_pp;
+	u8 phase;
+
+	/* Check if we're at a half-basis point */
+	if ((rdsd->i & (RDS_BASISLENGTH/2 - 1)) != 0)
+		return;	/* Nope, return */
+
+	/* Yes, time to do our work */
+	/* Rotate the length 3 history buffer */
+	decomp_hist_pp = rdsd->decomp_hist_p;
+	rdsd->decomp_hist_p = rdsd->decomp_hist;
+	if ((rdsd->i & (RDS_BASISLENGTH-1)) == 0) {
+		rdsd->decomp_hist = rdsd->mixandsum1>>9; /* Grab output of
+							  * mixandsum1/512 */
+		rdsd->mixandsum1 = 0;	 /* Reset mixandsum #1 */
+	} else {
+		rdsd->decomp_hist = rdsd->mixandsum2>>9; /*Grab output of
+							  * mixandsum2/512 */
+		rdsd->mixandsum2 = 0;	/* Reset mixandsum #2 */
+	}
+
+	/* Form correlator/decimator output by convolving with the
+	 * decomposition coefficients, DecompQuant from Matlab work. */
+	filter_out = (-58*rdsd->decomp_hist + 59*decomp_hist_pp)>>7;
+
+	/*Figure out which half-basis we are in (out of a bit-length cycle) */
+	phase = rdsd->i*2/RDS_BASISLENGTH;
+	/*Now what we do depends on the phase variable */
+	/*Phase 0:      Bitslice and do timing alignment */
+	/*others (1-3): Keep value for timing alignment */
+
+	if (phase == 0) {   /*Main processing (bitslice) */
+		u32 Ph;
+		u8 OldBit = rdsd->sliced_data;	/* Save the previous value */
+
+		rdsd->return_num = 1;
+		if (filter_out >= 0) { /*This bit is "1" */
+			/*return value is XOR of previous bit (still in
+			 * sliced_data) w/ this */
+			/*  bit (1), which equals (NOT of the previous bit) */
+			rdsd->return_rdsdemod = !OldBit;
+			rdsd->sliced_data = 1;	/*Newest bit value is 1 */
+		} else { /*This bit is "0" */
+			/*return value is XOR of previous bit (still in
+			 * sliced_data) w/ this */
+			/*  bit (0), which equals the previous bit */
+			rdsd->return_rdsdemod = OldBit;
+			rdsd->sliced_data = 0;	/*Newest bit value is 0 */
+		}
+
+		freeSpace = bits_free(rdsb);
+
+		if (freeSpace > 0)
+			put1bit(rdsb, rdsd->return_rdsdemod);
+		else
+			rdsd->RdsDemodSkippedBitCnt++;
+
+		/*Increment bits received counter */
+		rdsd->BitAlignmentCounter++;
+		/*If mixer phase determination hasn't been done, start it */
+		if ((rdsd->MixPhaseState == 0) && (!rdsd->MixPhaseDetInProg)) {
+			rdsd->MixPhaseDetInProg = 1;
+			/*Go to first mixer setting (0) */
+			rds_mix_msg(rdsd, 0);
+		}
+
+		/* Do bit-slicing time adaption after the mixer phase
+		 * determination */
+		if (!(rdsd->MixPhaseDetInProg) && !(rdsd->Synchronous)) {
+
+			/* Bitslice Timing Adjust Code (runs after
+			 * MixPhaseDetInProg and if RDS is not synchronous to
+			 * the FM pilot. */
+
+			u8 BigPh2;	/* Expecting a large value in
+					 * PhaseValue[2] */
+			u32 MaxRMS = 0;	/*Largest phase RMS */
+			s8 MaxPh = 0;	/*Index of largest phase RMS */
+			s32 zerocross;
+
+			/* Locate the largest phase RMS
+			 * (should be at phase zero) */
+			for (Ph = 0; Ph < 4; Ph++)
+				if (rdsd->Ph_RMS[Ph] > MaxRMS) {
+					MaxRMS = rdsd->Ph_RMS[Ph];
+					MaxPh = Ph;
+				}
+
+			/* During each bit time we expect the four phases to
+			 * take one of the following patterns, where 1
+			 * corresponds to maximum modulation:
+			 *   1,    0,  -1,    0			Case I
+			 *  -1,    0,   1,    0			Case II
+			 *   1,  1/2,   0, -1/2			Case III
+			 *  -1, -1/2,   0,  1/2			Case IV
+			 * We need to distinguish between cases in order to do
+			 * the timing adjustment. Below we compare the
+			 * correlation of the samples with Case I and Case III
+			 * to see which has a bigger abs(correlation).  Thus
+			 * BigPh2, if set, means that we decided on Case I or
+			 * Case II; if BigPh2 clear, we decided Case III or IV.
+			 */
+			BigPh2 = abs(rdsd->PhaseValue[0]-rdsd->PhaseValue[2]) >
+				 abs(rdsd->PhaseValue[0] +
+				 ((rdsd->PhaseValue[1]-
+					rdsd->PhaseValue[3])>>1));
+			/* If BigPh2, use the difference between phase 1 value
+			 * (downgoing for Case I, upgoing for Case II) and
+			 * phase 3 value (upgoing for Case I, downgoing for
+			 * Case II, thus the subtraction) to indicate timing
+			 * error.  If not BigPh2, use the sum of the phase 1
+			 * value (downgoing for Case III, upgoing for Case IV)
+			 * and phase 3 value (downgoing for Case III, upgoing
+			 * for Case IV, thus the addition) to indicate timing
+			 * error.  If BigPh2, the slopes at phase 1 & phase 3
+			 * are approximately double that if not BigPh2.
+			 * Since we are trying to measure timing, scale
+			 * by 1/2 in the BigPh2 case. */
+			if (BigPh2)
+				zerocross = (rdsd->PhaseValue[1]-
+					rdsd->PhaseValue[3])>>1;
+			else
+				zerocross = rdsd->PhaseValue[1]+
+					rdsd->PhaseValue[3];
+			/* Now if the prev bit was a "1", then the first zero
+			 * crossing (phase 1 if BigPh2, phase 2 if !BigPh2)
+			 * was a falling one, and if we were late then
+			 * zerocross should be negative. If the prev bit was a
+			 * "0", then the first zero crossing was a rising one,
+			 * and if we were late then zerocross would be
+			 * positive. If we are "late" it means that we need to
+			 * do a shorter cycle of, say, 15 samples instead of
+			 * 16, to "catch up" so that in the future we will be
+			 * sampling earlier.  We shorten the cycle by adding
+			 * to i, so "late" is going to mean "increment i".
+			 * Therefore "late" should be positive, which is done
+			 * here by inverting zerocross if the previous bit was
+			 * 1.  You could say that this step reflects cases I
+			 * and III into II and IV, respectively. */
+			if (OldBit)
+				zerocross = -zerocross;
+			if (!rdsd->DisablePushing) {
+				/*The algorithm so far has a stable operating
+				 * point 17 phases away from the correct one.
+				 * The following code is experimental and may
+				 * be deleterious in low SNR conditions, but is
+				 * an attempt to move off of the incorrect
+				 * operating point. */
+
+				if (MaxPh != 0) {
+					/* If it isn't the same MaxPh as the
+					 * last non-zero one, clear the counter
+					 */
+					if (MaxPh != rdsd->PushLastMaxPh) {
+						/*Reset the counter */
+						rdsd->PushCounter = 0;
+						/*Record which phase we're now
+						 * counting */
+						rdsd->PushLastMaxPh = MaxPh;
+					}
+					/* If the Max RMS is on the same
+					 * non-zero phase, count up */
+					rdsd->PushCounter++;
+				}
+				/* Once every 128 bits, check and then reset
+				 * PushCounter */
+				if (!(rdsd->BitAlignmentCounter & 0x0FF)) {
+					/*If 90% of the time the max phase has
+					 * been from the same non-zero phase,
+					 * decide that we are latched onto a 0
+					 * lock point. Do a large push of the
+					 * timing. */
+					if (rdsd->PushCounter > 230) {
+						s32 pshiph;
+						/*Convert from phase number to
+						 * the number of filter
+						 *  output samples that we need
+						 *  to shift */
+						if (rdsd->PushLastMaxPh >= 2)
+							pshiph =
+								4 - (s8)rdsd->
+								PushLastMaxPh;
+						else
+							pshiph =
+								-(s8)rdsd->
+								PushLastMaxPh;
+						/* Scale by the number of i-
+						 * phases per output sample */
+						pshiph <<=
+							RDS_BASISSHIFTS-1;
+						/* Perform big pop to get near
+						 * correct timing */
+						rdsd->i += (RDS_BASISLENGTH<<1)
+							+ pshiph;
+						/* Set status indicating big
+						 * pop was needed.  Reset all
+						 * leaky-bucket and summation
+						 * variables because the big
+						 * timing shift has invalidated
+						 * them. Ph_RMS values don't
+						 * need to be reset because
+						 * they will shift over to
+						 * reasonable values again
+						 * before their erroneous
+						 * values could have effect. */
+						rdsd->rds_big_timeshift = 1;
+						/*rdsd->Ph_RMS[0] = 0; */
+						/*rdsd->Ph_RMS[1] = 0; */
+						/*rdsd->Ph_RMS[2] = 0; */
+						/*rdsd->Ph_RMS[3] = 0; */
+						rdsd->mixandsum1 = 0;
+						rdsd->mixandsum2 = 0;
+						rdsd->SkipsAccum +=
+							pshiph;
+
+						/* Make adjustments in other
+						 * values because of the push
+						 * (they wouldn't otherwise be
+						 * able to use the information
+						 * that a push was needed in
+						 * their future control
+						 * decisions). */
+						if (rdsd->PushLastMaxPh != 2) {
+							/* If we weren't
+							 * pushing from phase
+							 * two, accumulate (for
+							 * use in adapting
+							 * SDNOMINAL) the
+							 * phases moved by
+							 * pushing. Phase two
+							 * pushes are not used;
+							 * the push direction
+							 * is arbitrary since
+							 * Phase 2 is 180
+							 * degrees out.  Also,
+							 * phase 2 pushes don't
+							 * result from
+							 * reasonable slippage.
+							 * */
+
+							if (rdsd->sdnom_adapt)
+								rdsd->SdnomSk
+								+= pshiph;
+
+							/* Modify timing_adj to
+							 * account for half of
+							 * the DC response that
+							 * would have occurred
+							 * in timing_adj if
+							 * that control loop
+							 * had seen the push
+							 * happen. (Why half?
+							 * Because the loop has
+							 * already seen a
+							 * history of zerocross
+							 * values that heads it
+							 * in the same
+							 * direction as this
+							 * adjustment, but may
+							 * have seen as few as
+							 * half of what it
+							 * should have.) */
+							rdsd->timing_adj +=
+								pshiph <<
+								(TADJSH+1);
+						}
+						/*Set countdown timer that will
+						 * prevent any mixer popping
+						 * until the Ph_RMS variables
+						 * have had enough time to
+						 * stabilize */
+
+						/* 2.5 time constants */
+						rdsd->PushSafetyZone = 5;
+					}
+					/*Reset the push counter */
+					rdsd->PushCounter = 0;
+				}  /*end once every 128 bits */
+			}  /*end if !DisablePushing */
+
+			/* Further possible additions:
+			 *
+			 * 1. Pushes modify timing_adj to decrease convergence
+			 *    time.
+			 * 2. Separate timing_adj into pilottracking and non-pt
+			 *    cases (avoids convergence time after stereo/mono
+			 *    transitions)
+			 *
+			 * Old loop filter was a leaky bucket integrator, and
+			 * it always lagged behind if the FM station had RDS
+			 * asynchronous to the pilot, because the control loop
+			 * needs another integrator to converge on a frequency
+			 * error.
+			 * New loop filter = 1/(1-1/z) * (a-1/z) * k,
+			 * where a = 1+1/256 and k = 1/1024.
+			 * You can narrow the loop bandwidth by making "a"
+			 * twice as close to 1 and halving k, e.g. a = 1+1/512
+			 * and k = 1/2048.
+			 * (The way implemented, that narrowing loop BW by
+			 * a factor of 2 can be done by incrementing TADJSH.)
+			 *
+			 * TGR 8/31/2007 */
+
+			/*Integrator, 1/(1-1/z) */
+			rdsd->timing_adj += zerocross;
+			/*Limit to 1 phase every 8 samples */
+			if (rdsd->SkipSafetyZone) {
+				rdsd->SkipSafetyZone--;
+				rdsd->sampskip = 0;
+			} else {
+				/*sampskip of non-zero is allowed,
+				 * calculate what it really is */
+
+				/*Saturate timing_adj to 2's comp
+				 * (2*TADJSH+4)-bit range. */
+				if (rdsd->timing_adj > (1<<(2*TADJSH+3))-1)
+					rdsd->timing_adj = (1<<(2*TADJSH+3))-1;
+				if (rdsd->timing_adj < -(1<<(2*TADJSH+3)))
+					rdsd->timing_adj = -(1<<(2*TADJSH+3));
+
+				/* Zero, implemented after the integrator
+				 * output.
+				 * (a-1/z) = (1+1/256) - 1/z = (1-1/z) + 1/256.
+				 * But (1 - 1/z) is timing_adj-
+				 * prev_timing_adj = zerocross. */
+				rdsd->sampskip = zerocross	/* 1 - 1/z */
+					/* 1/256 (with rounding) */
+					+ ((rdsd->timing_adj
+						+ (1<<(TADJSH-1)))>>TADJSH);
+				/*Round and apply k */
+				rdsd->sampskip += (1<<(TADJSH+1));
+				rdsd->sampskip >>= (TADJSH+2);
+				/*Limit to [-1,+1] inclusive */
+				if (rdsd->sampskip > 1)
+					rdsd->sampskip = 1;
+				if (rdsd->sampskip < -1)
+					rdsd->sampskip = -1;
+				/* If non-zero, start the skip safety zone,
+				 * which excludes more sample skipping for a
+				 * while.  Note that the safety zone only
+				 * applies to the skips -- pushes can still
+				 * happen inside a SkipSafetyZone. */
+				if (rdsd->sampskip)
+					rdsd->SkipSafetyZone = 8-1;
+			}
+			/**********************************************
+			* End Timing Adjust Code
+			**********************************************/
+
+			/**********************************************
+			* Begin Phase Popper Code
+			**********************************************/
+			/* If Phase Popping is enabled and 1/2 of a
+			 * time constant has gone by... */
+			if (rdsd->PhasePoppingEnabled &&
+				!(rdsd->BitAlignmentCounter &
+					((1<<(RMSALPHASHIFTS-1))-1))) {
+
+				u8 ForcePop = 0; /* Used to force a pop */
+
+				/*Record the maximum of the envelope */
+				if (MaxRMS > rdsd->PhasePopMaxRMS)
+					rdsd->PhasePopMaxRMS = MaxRMS;
+				/* Also track MaxRMS into MixPhase0/1Mag, so
+				 * that we can see what the largest RMS on each
+				 * of those phases is.  On synchronous stations
+				 * (meaning the RDS carrier and bit rate are
+				 * synchronized with the pilot), the right mix
+				 * phase will always be big and the wrong phase
+				 * small. On asynchronous stations (and
+				 * stations without RDS), both phases will at
+				 * some time or other have about the
+				 * same amplitude on each of the phases. */
+				if (rdsd->rds_mix_offset) {
+					if (MaxRMS > rdsd->MixPhase1Mag)
+						rdsd->MixPhase1Mag = MaxRMS;
+				} else {
+					if (MaxRMS > rdsd->MixPhase0Mag)
+						rdsd->MixPhase0Mag = MaxRMS;
+				}
+				/* Update PopSafetyZone and PushSafetyZone
+				 * counters.  With RMSALPHASHIFTS = 5, each
+				 * tick is 16/1187.5 =~ 13.5 ms. */
+				if (rdsd->PopSafetyZone) {
+					rdsd->PopSafetyZone--;
+					/* If safety zone just ended and this
+					 * mix phase is giving smaller RMS than
+					 * before the pop, then the pop was a
+					 * mistake.  Go back to previous mixer
+					 * phase */
+					if (!(rdsd->PopSafetyZone)
+						&& (rdsd->PhasePopMaxRMS <
+							rdsd->PrePopRMS))
+						ForcePop = 1;
+				}
+				/* If there is no recent push, and Phase 0 has
+				 * the maximum RMS, and at least 1/7th of a
+				 * second has passed since the last phase pop,
+				 * and ((the RMS is less than 1/2 of
+				 * PhasePopMaxRMS) or (the RMS is less than
+				 * 100)), then try a phase pop. */
+				if (/* (rdsd->Ph_RMS[0] == MaxRMS) &&
+						* Phase 0 has maximum RMS  */
+					!(rdsd->PopSafetyZone))	{
+					 /* and Long enough since last
+					  * phase pop */
+
+					/* Eligible for a pop, see if one of
+					 * the pop conditions is met */
+					if ((MaxRMS<<1) <
+							rdsd->PhasePopMaxRMS) {
+						/*RMS decline from its peak */
+						ForcePop = 1;
+					} else if ((MaxRMS>>RMSALPHASHIFTS)
+						< 50) {
+						/*RMS too small to receive,
+						 * either there's no RDS or
+						 * this is the wrong phase */
+						ForcePop = 1;
+					}
+				}
+				if (ForcePop) {
+
+					/*Pop to opposite setting */
+					rds_mix_msg(rdsd, 0x8 |
+						!rdsd->rds_mix_offset);
+
+					/*Save the pre-pop RMS so that later we
+					 * can see if the pop was actually
+					 * effective */
+					rdsd->PrePopRMS = MaxRMS;
+					/*Reset the PhasePopMaxRMS.  We rely on
+					 * the PopSafetyZone to give time to
+					 * get a new valid max RMS before we're
+					 * eligible for the next phase pop.  If
+					 * there were no reset we'd be forever
+					 * incrementing PhasePopMaxRMS due
+					 * to just happenstance large-noise
+					 * samples and it might eventually get
+					 * some freakish large value causing
+					 * frequent erroneous pops. */
+					rdsd->PhasePopMaxRMS = 0;
+					/* Pop Safety zone length is decided by
+					 * how much of an asynchronous
+					 * frequency can be supported. Allowing
+					* 50 ppm of transmitter error (error
+					* between their own pilot, that we
+					* should be locked to, and their RDS
+					* carrier (which by RDS spec should be
+					* locked to their pilot, but we've
+					* recently found frequently isn't).
+					* 50ppm * 57kHz = 2.85Hz.
+					* (2.85 cycles/sec)(4 pops/cycle)
+					* = 11.4 pops/second.
+					* Safety zone = (1/11.4) seconds =~ 104
+					* bits, round down to 96 bits which
+					* yields 6 ticks if RMSALPHASHIFTS = 5.
+					* */
+					rdsd->PopSafetyZone = 96>>
+						(RMSALPHASHIFTS-1);
+				}
+			}
+			/******************************************************
+			* End Phase Popper Code
+			******************************************************/
+
+			/* SDNOMINAL adaption */
+			if (rdsd->sdnom_adapt) {
+				rdsd->SdnomSk += rdsd->sampskip;
+				if (rdsd->pCoefForcedMono &&
+					(rdsd->BitAlignmentCounter & 0xFFF) ==
+						0x800) {
+
+					rds_sdnominal_msg(rdsd,
+						-(rdsd->SdnomSk<<9));
+
+					/*Reset skips counter */
+					rdsd->SdnomSk = 0;
+				}
+			}
+
+			rdsd->SkipsAccum += rdsd->sampskip;
+			/* Once per 3.45 seconds, print out signal strength,
+			 * skips and pops. Then reset the variables totalling
+			 * those occurrences */
+			if (!(rdsd->BitAlignmentCounter & 0xFFF)) {
+				/* During very noisy input (or if no RDS, or no
+				 * station present), timing_adj can go crazy,
+				 * since it is the integral of noise.  Although
+				 * it is a saturated value (earlier, in the
+				 * timing adjust code), the level at which we
+				 * can saturate still leaves room for
+				 * timing_adj to get too big.  A large value of
+				 * timing_adj is a persistent pathology because
+				 * the phase is shifting so quickly that the
+				 * push detector (which relies on stable
+				 * phase-RMS values) never triggers, thus there
+				 * is no implemented rescue besides this
+				 * clearing that restores proper function. */
+				if (abs(rdsd->SkipsAccum) > 300)
+					rdsd->timing_adj = 0;
+				/*Reset the accumulations. */
+				rdsd->SkipsAccum = 0;
+			}
+		} /*End of bit timing adaption */
+
+		/* If mixer phase determination in progress,
+		 * perform actions at certain times */
+		if (rdsd->MixPhaseDetInProg) {
+			/*~10ms settling time after mixer phase change */
+			#define MIXPHASE_STARTMEAS 12
+			/*~20ms measurement window */
+			#define MIXPHASE_ENDMEAS (MIXPHASE_STARTMEAS+24)
+			if (rdsd->BitAlignmentCounter == MIXPHASE_STARTMEAS) {
+				/*Reset the RMS variables */
+				rdsd->Ph_RMS[0] = 0;
+				rdsd->Ph_RMS[1] = 0;
+				rdsd->Ph_RMS[2] = 0;
+				rdsd->Ph_RMS[3] = 0;
+				/* Don't reset mixandsum values because at
+				 * least they have filtered continuously.  All
+				 * we really need for the mixer phase decision
+				 * is a constant measurement window. */
+			} else if (rdsd->BitAlignmentCounter ==
+					MIXPHASE_ENDMEAS) {
+				/*Measurement = mean of RMS values */
+				u32 Ndx, MeasVal = 0;
+				for (Ndx = 0; Ndx < 4;
+					MeasVal += rdsd->Ph_RMS[Ndx++]>>2);
+				/*Store measurement in correct place */
+				if (rdsd->MixPhaseState == 1) {
+					rdsd->MixPhase0Mag = MeasVal;
+					/*Go to next mixer setting */
+					rds_mix_msg(rdsd, 1);
+				} else if (rdsd->MixPhaseState == 2) {
+					u8 NextMixSetting;
+					rdsd->MixPhase1Mag = MeasVal;
+					/* Both measurements done now, see what
+					 * mixer setting we need to use.
+					 * 0 if MixPhase0Mag > MixPhase1Mag,
+					 * 1 otherwise. */
+					NextMixSetting = (rdsd->MixPhase0Mag
+						<= rdsd->MixPhase1Mag);
+					/* If the mixer setting needed is 1,
+					 * that is already the current setting.
+					 * Terminate mixer phase determination.
+					 * Otherwise send message to switch the
+					 * mixer phase setting. */
+					if (NextMixSetting) {
+						rdsd->MixPhaseState = 3;
+						rdsd->MixPhaseDetInProg = 0;
+					} else
+						rds_mix_msg(rdsd, 0);
+				}
+			}
+			/* Reset BitAlignmentCounter if the Mixer just popped
+			 * Change state, if required.  States are:
+			 * 0: Initial state, send msg causing RDS_MIXOFFSET=>0
+			 * 1: Measure with RDS_MIXOFFSET = 0.
+			 * 	Lasts just over 30 ms.
+			 * 2: Measure with RDS_MIXOFFSET = 1.
+			 * 	Lasts just over 30 ms.
+			 * 3: At final RDS_MIXOFFSET value.
+			 * 	Lasts as long as RDS continues. */
+			if (rdsd->MixPopDone) {
+				rdsd->MixPopDone = 0;
+				rdsd->BitAlignmentCounter = 0;
+				rdsd->MixPhaseState++;	/*Go to next state */
+				/* If we got to state 3, turn off mixer phase
+				 * determination code */
+				if (rdsd->MixPhaseState == 3)
+					rdsd->MixPhaseDetInProg = 0;
+			}
+		}
+
+		/* Update status variables */
+		rdsd->RDS_BIT_AMP_STAT_REG9 = rdsd->Ph_RMS[0]>>RMSALPHASHIFTS;
+		/*Saturate */
+		if (rdsd->RDS_BIT_AMP_STAT_REG9 > 511)
+			rdsd->RDS_BIT_AMP_STAT_REG9 = 511;
+	}  /*End phase 0 code */
+
+	/***************************************************
+	* Actions common to all phases
+	***************************************************/
+
+	/* Save the output of each phase for possible
+	 * calculations during phase 0 */
+	rdsd->PhaseValue[phase] = filter_out;
+
+	/*So that we can measure signal amplitude and/or determine what (if */
+	/*  any) big jump is needed, maintain the RMS of each phase.  Phase */
+	/*  0 RMS is already in Ph_RMS[0] (see bitslicing code, earlier). */
+	rdsd->Ph_RMS[phase] += abs(filter_out) -
+		(rdsd->Ph_RMS[phase]>>RMSALPHASHIFTS);
+}
+
+#if defined(CONFIG_ARM)
+
+/* assembly version for ARM */
+#define RDS_MAC(_acc, _x, _y) \
+	__asm__ __volatile__ (			 \
+	"smlabb	%0, %1, %2, %0\n"		 \
+	: "=&r" (_acc)				 \
+	: "r" (_x), "r" (_y)			 \
+	: "cc")
+
+#else
+
+/* all others, use standard C */
+#define RDS_MAC(_acc, _x, _y) 			 \
+	do {					 \
+		(_acc) += (s16)(_x) * (s16)(_y); \
+	} while (0)
+
+#endif
+
+static void rds_demod(const u16 *data, struct stfm1000_rds_demod *rdsd,
+	struct stfm1000_rds_bitstream *rbit, int total)
+{
+	register const s16 *basis0;
+	register const s16 *basis1;
+	register s16 val;
+	register int i;
+	register int sampskip;
+	register s32 acc1;
+	register s32 acc2;
+
+	/* point to the table */
+	basis0 = u16_rds_basis;
+	basis1 = basis0 + 8;
+
+	rdsd->return_num = 0;
+
+	/* restore state */
+	i = rdsd->i;
+	acc1 = rdsd->mixandsum1;
+	acc2 = rdsd->mixandsum2;	/* 64 bit */
+	sampskip = rdsd->sampskip;
+
+	while (total-- > 0) {
+
+		val = data[3];	/* load RDS data */
+		data += 4;
+		if (val == 0x7fff)	/* illegal RDS sample */
+			continue;
+
+		RDS_MAC(acc1, val, basis0[i]);
+		RDS_MAC(acc2, val, basis1[i]);
+
+		if (i == 4) {
+			i += sampskip;
+			sampskip = 0;
+		}
+
+		if ((i & (RDS_BASISLENGTH / 2 - 1)) == 0) {
+
+			/* save state */
+			rdsd->mixandsum1 = acc1;
+			rdsd->mixandsum2 = acc2;
+			rdsd->i = i;
+			rdsd->sampskip = sampskip;
+
+			demod_loop(rbit, rdsd);
+
+			/* restore state */
+			acc1 = rdsd->mixandsum1;
+			acc2 = rdsd->mixandsum2;
+			i = rdsd->i;
+			sampskip = rdsd->sampskip;
+		}
+		i = (i + 1) & 31;
+	}
+
+	/* save state */
+	rdsd->mixandsum1 = acc1;
+	rdsd->mixandsum2 = acc2;
+	rdsd->i = i;
+	rdsd->sampskip = sampskip;
+}
+
+void stfm1000_rds_demod(struct stfm1000_rds_state *rds, const u16 *dri_data,
+	int total)
+{
+	rds_demod(dri_data, &rds->demod, &rds->bitstream, total);
+
+	/* signal only when we have enough */
+	if (bits_filled(&rds->bitstream) > 128)
+		stfm1000_monitor_signal(rds_state_to_stfm1000(rds),
+				EVENT_RDS_BITS);
+}
+
+static void bitstream_reset(struct stfm1000_rds_bitstream *rdsb)
+{
+	memset(rdsb, 0, sizeof(*rdsb));
+}
+
+static void demod_reset(struct stfm1000_rds_demod *rdsd)
+{
+	memset(rdsd, 0, sizeof(*rdsd));
+	rdsd->sdnom_adapt = 0;	/* XXX this doesn't really work right */
+					/* it causes underruns at ALSA */
+	rdsd->PhasePoppingEnabled = 1;	/* does this? */
+}
+
+static void packet_reset(struct stfm1000_rds_pkt *rdsp)
+{
+	memset(rdsp, 0, sizeof(*rdsp));
+	rdsp->state = SYNC_OFFSET_A;
+}
+
+static void text_reset(struct stfm1000_rds_text *rdst)
+{
+	memset(rdst, 0, sizeof(*rdst));
+}
+
+void stfm1000_rds_reset(struct stfm1000_rds_state *rds)
+{
+	bitstream_reset(&rds->bitstream);
+	demod_reset(&rds->demod);
+	packet_reset(&rds->pkt);
+	text_reset(&rds->text);
+	rds->reset_req = 0;
+}
+
+int stfm1000_rds_bits_available(struct stfm1000_rds_state *rds)
+{
+	return bits_filled(&rds->bitstream);
+}
+
+int stmf1000_rds_get_bit(struct stfm1000_rds_state *rds)
+{
+	if (bits_filled(&rds->bitstream) == 0)
+		return -1;
+	return get1bit(&rds->bitstream);
+}
+
+int stmf1000_rds_avail_bits(struct stfm1000_rds_state *rds)
+{
+	return bits_filled(&rds->bitstream);
+}
+
+static const u32 rds_ParityCheck[] = {
+	0x31B, 0x38F, 0x2A7, 0x0F7, 0x1EE,
+	0x3DC, 0x201, 0x1BB, 0x376, 0x355,
+	0x313, 0x39F, 0x287, 0x0B7, 0x16E,
+	0x2DC, 0x001, 0x002, 0x004, 0x008,
+	0x010, 0x020, 0x040, 0x080, 0x100,
+	0x200
+};
+
+static int calc_syndrome(u32 rdscrc)
+{
+	int i;
+	u32 syndrome = 0;
+	int word = 0x1;
+
+	for (i = 0; i < 26; i++) {
+		if (rdscrc & word)
+			syndrome ^= rds_ParityCheck[i];
+		word <<= 1;
+	}
+	return syndrome;
+}
+
+static u32 ecc_table[1024];
+static int ecc_table_generated;
+
+static void generate_ecc_table(void)
+{
+	int i, j, size;
+	u32 syndrome, word;
+
+	for (i = 0; i < ECC_TBL_SIZE; i++)
+		ecc_table[i] = 0xFFFFFFFF;
+	ecc_table[0] = 0x0;
+
+	for (j = 0; j < 5; j++) {
+		word = (1 << (j + 1)) - 1;	/* 0x01 0x03 0x07 0x0f 0x1f */
+		size = 26 - j; 			/* 26, 25, 24, 23, 22 */
+		syndrome = 0;
+		for (i = 0; i < size; i++) {
+			syndrome = calc_syndrome(word);
+			ecc_table[syndrome] = word;
+			word <<= 1;
+		}
+	}
+}
+
+static u32 ecc_correct(u32 rdsBits, int *recovered)
+{
+	u32 syndrome;
+	u32 errorBits;
+
+	if (recovered)
+		*recovered = 0;
+
+	/* Calculate Syndrome on Received Packet */
+	syndrome = calc_syndrome(rdsBits);
+
+	if (syndrome == 0)
+		return rdsBits; /* block is clean */
+
+	/* generate table first time we get here */
+	if (!ecc_table_generated) {
+		generate_ecc_table();
+		ecc_table_generated = 1;
+	}
+
+	/* Attempt to recover block */
+	errorBits = ecc_table[syndrome];
+	if (errorBits == UNRECOVERABLE_RDS_BLOCK)
+		return UNRECOVERABLE_RDS_BLOCK;	/* Block can not be recovered.
+						 * it is bad packet */
+
+	rdsBits = rdsBits ^ errorBits;
+	if (recovered)
+		(*recovered)++;
+	return rdsBits;                 /* ECC correct */
+}
+
+/* The following table lists the RDS and RBDS Program Type codes
+ * and their meanings:
+ * PTY code RDS Program type RBDS Program type */
+static const struct stfm1000_rds_pty stc_tss_pty_tab[] = {
+	{  0, "No program type",    "No program type"},
+	{  1, "News",               "News"},
+	{  2, "Current affairs",    "Information"},
+	{  3, "Information",        "Sports"},
+	{  4, "Sports",             "Talk"},
+	{  5, "Education",          "Rock"},
+	{  6, "Drama",              "Classic Rock"},
+	{  7, "Culture",            "Adult Hits"},
+	{  8, "Science",            "Soft Rock"},
+	{  9, "Varied",             "Top 40"},
+	{ 10, "Pop",                "Music Country"},
+	{ 11, "Rock",               "Music Oldies"},
+	{ 12, "M.O.R.",             "Music Soft"},
+	{ 13, "Light classical",    "Nostalgia"},
+	{ 14, "Serious",            "Classical Jazz"},
+	{ 15, "Other Music",        "Classical"},
+	{ 16, "Weather",            "Rhythm and Blues"},
+	{ 17, "Finance",            "Soft Rhythm and Blues"},
+	{ 18, "Children's programs", "Language"},
+	{ 19, "Social Affairs",     "Religious Music"},
+	{ 20, "Religion",           "Religious Talk"},
+	{ 21, "Phone In",           "Personality"},
+	{ 22, "Travel",             "Public"},
+	{ 23, "Leisure",            "College"},
+	{ 24, "Jazz Music",         "Unassigned"},
+	{ 25, "Country Music",      "Unassigned"},
+	{ 26, "National Music",     "Unassigned"},
+	{ 27, "Oldies Music",       "Unassigned"},
+	{ 28, "Folk Music",         "Unassigned"},
+	{ 29, "Documentary",        "Weather"},
+	{ 30, "Alarm Test",         "Emergency Test"},
+	{ 31, "Alarm",              "Emergency"},
+};
+
+#if 0
+static const char *rds_group_txt[] = {
+	[RDS_GROUP_TYPE_0A] = "Basic tuning and switching information (0A)",
+	[RDS_GROUP_TYPE_0B] = "Basic tuning and switching information (0B)",
+	[RDS_GROUP_TYPE_1A] = "Program item number and slow labeling codes",
+	[RDS_GROUP_TYPE_1B] = "Program item number",
+	[RDS_GROUP_TYPE_2A] = "Radio Text (2A)",
+	[RDS_GROUP_TYPE_2B] = "Radio Text (2B)",
+	[RDS_GROUP_TYPE_3A] = "Application identification for ODA only",
+	[RDS_GROUP_TYPE_3B] = "Open data applications",
+	[RDS_GROUP_TYPE_4A] = "Clock-time and date",
+	[RDS_GROUP_TYPE_4B] = "Open data applications",
+	[RDS_GROUP_TYPE_5A] = "Transparent Data Channels (32 ch.) or ODA (5A)",
+	[RDS_GROUP_TYPE_5B] = "Transparent Data Channels (32 ch.) or ODA (5B)",
+	[RDS_GROUP_TYPE_6A] = "In House Applications or ODA (6A)",
+	[RDS_GROUP_TYPE_6B] = "In House Applications or ODA (6B)",
+	[RDS_GROUP_TYPE_7A] = "Radio Paging or ODA",
+	[RDS_GROUP_TYPE_7B] = "Open Data Applications",
+	[RDS_GROUP_TYPE_8A] = "Traffic Message Channel or ODA",
+	[RDS_GROUP_TYPE_8B] = "Open Data Applications",
+	[RDS_GROUP_TYPE_9A] = "Emergency warning system or ODA",
+	[RDS_GROUP_TYPE_9B] = "Open Data Applications",
+	[RDS_GROUP_TYPE_10A] = "Program Type Name",
+	[RDS_GROUP_TYPE_10B] = "Open Data Applications (10B)",
+	[RDS_GROUP_TYPE_11A] = "Open Data Applications (11A)",
+	[RDS_GROUP_TYPE_11B] = "Open Data Applications (11B)",
+	[RDS_GROUP_TYPE_12A] = "Open Data Applications (12A)",
+	[RDS_GROUP_TYPE_12B] = "Open Data Applications (12B)",
+	[RDS_GROUP_TYPE_13A] = "Enhanced Radio Paging or ODA",
+	[RDS_GROUP_TYPE_13B] = "Open Data Applications",
+	[RDS_GROUP_TYPE_14A] = "Enhanced Other Networks information (14A)",
+	[RDS_GROUP_TYPE_14B] = "Enhanced Other Networks information (14B)",
+	[RDS_GROUP_TYPE_15A] = "Defined in RBDS",
+	[RDS_GROUP_TYPE_15B] = "Fast switching information",
+};
+#endif
+
+static void dump_rds_packet(u8 *buf)
+{
+	u16 pi, offb;
+
+	pi   = (u16)(buf[0] << 8) | buf[1];
+	offb = (u16)(buf[1] << 8) | buf[2];
+
+	printk(KERN_INFO "GRP: "
+		"PI=0x%04x "
+		"GT=%2d VER=%d TP=%d PTY=%2d "
+		"PS_SEG=%2d RT_AB=%2d RT_SEG=%2d\n", pi,
+		RDS_GROUP_TYPE(offb), RDS_VERSION(offb), RDS_TP(offb),
+		RDS_PTY(offb),
+		RDS_PS_SEG(offb), RDS_RT_AB(offb), RDS_RT_SEG(offb));
+}
+
+void stfm1000_rds_process_packet(struct stfm1000_rds_state *rds, u8 *buffer)
+{
+	struct stfm1000_rds_text *rdst = &rds->text;
+	/* char tempCallLetters[5] = {0}; */
+	struct rds_group_data grp;
+	int grpno;
+	u32 offset;
+	char tps[9];
+	int i, seg, idx;
+
+	grp.piCode  = ((u16)buffer[0] << 8) | buffer[1];
+	grp.offsetB = ((u16)buffer[2] << 8) | buffer[3];
+	grp.offsetC = ((u16)buffer[4] << 8) | buffer[5];
+	grp.offsetD = ((u16)buffer[6] << 8) | buffer[7];
+
+	grpno = (grp.offsetB >> (8 + 3)) & 0x1f;
+
+	if (rds_state_to_stfm1000(rds)->rds_info)
+		dump_rds_packet(buffer);
+
+	/* Is this the first time through? */
+	if (!rdst->bRds_detected) {
+		rdst->pi            = grp.piCode;
+		rdst->tp            = RDS_TP(grp.offsetB);
+		rdst->version       = RDS_VERSION(grp.offsetB);
+		rdst->pty.id        = RDS_PTY(grp.offsetB);
+		rdst->pty.pRds      = stc_tss_pty_tab[rdst->pty.id].pRds;
+		rdst->pty.pRdbs     = stc_tss_pty_tab[rdst->pty.id].pRdbs;
+		rdst->bRds_detected = 1;
+	}
+
+	/* Have we process too many PI errors? */
+	if (grp.piCode != rdst->pi) {
+		if (rdst->mismatch++ > 10) {
+
+			/* requested reset of RDS */
+			rds->reset_req = 1;
+
+			/* signal monitor thread */
+			stfm1000_monitor_signal(rds_state_to_stfm1000(rds),
+				EVENT_RDS_RESET);
+
+			if (rds_state_to_stfm1000(rds)->rds_info)
+				printk(KERN_INFO "RDS: RESET!!!\n");
+
+			text_reset(rdst);
+		}
+		rdst->consecutiveGood = 0;
+		return;
+	}
+
+	if (rdst->consecutiveGood++ > 10)
+		rdst->mismatch = 0;            /* reset bad count */
+
+	if (rdst->consecutiveGood > rdst->consecutiveGoodMax)
+		rdst->consecutiveGoodMax = rdst->consecutiveGood;
+
+	switch (grpno) {
+	case RDS_GROUP_TYPE_0A:
+	case RDS_GROUP_TYPE_0B:
+		/* Extract Service Name information */
+		offset = RDS_PS_SEG(grp.offsetB) * 2;
+		rdst->wk_ps[offset]     = buffer[6];	/* better */
+		rdst->wk_ps[offset + 1] = buffer[7];
+		rdst->wk_ps_mask |= 1 << RDS_PS_SEG(grp.offsetB);
+
+		if (rds_state_to_stfm1000(rds)->rds_info) {
+			for (i = 0; i < 8; i++) {
+				if (rdst->wk_ps_mask & (1 << i)) {
+					tps[i * 2] =
+						rdst->wk_ps[i * 2];
+					tps[i * 2 + 1] =
+						rdst->wk_ps[i * 2 + 1];
+				} else {
+					tps[i * 2] = '_';
+					tps[i * 2 + 1] = '_';
+				}
+			}
+			tps[ARRAY_SIZE(tps) - 1] = '\0';
+			if (rds_state_to_stfm1000(rds)->rds_info)
+				printk(KERN_INFO "RDS-PS (curr): %s\n", tps);
+		}
+
+		if (rdst->wk_ps_mask != ALL_SEGMENT_BITS)
+			break;
+
+		if (rdst->ps_valid) {
+			if (memcmp(rdst->ps, rdst->wk_ps, 8) != 0) {
+				memset(rdst->cp_ps, 0, 8);
+				memset(rdst->wk_ps, 0, 8);
+				rdst->wk_ps_mask = 0;
+			}
+
+			memset(rdst->ps, 0, 8);
+			rdst->ps_valid = 0;
+			break;
+		}
+
+		/* does working buffer == compare buffer */
+		if (memcmp(rdst->cp_ps, rdst->wk_ps, 8) != 0) {
+			/* just copy from working to compare buffer */
+			memcpy(rdst->cp_ps, rdst->wk_ps, 8);
+			rdst->wk_ps_mask = 0;
+			break;
+		}
+
+		/* working buffer matches compare buffer, send to UI */
+		memcpy(rdst->ps, rdst->cp_ps, 8);
+		rdst->ps_valid = 1;
+
+		if (rds_state_to_stfm1000(rds)->rds_info)
+			printk(KERN_INFO "RDS: PS '%s'\n", rdst->ps);
+
+		/* clear working mask-only */
+		rdst->wk_ps_mask = 0;
+		break;
+
+	case RDS_GROUP_TYPE_2A:
+
+		/* Clear buffer */
+		if (rdst->textAB_flag != RDS_RT_AB(grp.offsetB)) {
+			memset(rdst->wk_text, 0, 64);
+			rdst->wk_text_mask = 0;
+			rdst->textAB_flag  = RDS_RT_AB(grp.offsetB);
+		}
+
+		/* Extract Text */
+		seg = RDS_RT_SEG(grp.offsetB);
+		idx = seg * 4;
+
+		#define CNVT_EOT(x) ((x) != RDS_EOT ? (x) : 0)
+		rdst->wk_text[idx++] = CNVT_EOT(buffer[4]);
+		rdst->wk_text[idx++] = CNVT_EOT(buffer[5]);
+		rdst->wk_text[idx++] = CNVT_EOT(buffer[6]);
+		rdst->wk_text[idx++] = CNVT_EOT(buffer[7]);
+
+		rdst->wk_text_mask |= 1 << seg;
+		/* scan msg data for EOT.  If found set all higher
+		 * mask bits */
+		for (idx = 0; idx < 4; idx++) {
+			if (rdst->text[idx] == RDS_EOT)
+				break;
+		}
+		if (idx < 4) {
+			/* set current and all higher bits  */
+			for (idx = RDS_RT_SEG(grp.offsetB); idx < 16;
+				idx++)
+				rdst->wk_text_mask |= 1 << idx;
+		}
+
+		/* Process buffer when filled */
+		if (rdst->wk_text_mask != ALL_TEXT_BITS)
+			break;
+
+		if (!rdst->text_valid)
+			rdst->text_valid = 1;
+		else if (memcmp(rdst->text, rdst->wk_text, 64) == 0)
+			break;
+
+		memcpy(rdst->text, rdst->wk_text, 64);
+
+		if (rds_state_to_stfm1000(rds)->rds_info)
+			printk(KERN_INFO "RDS: TEXT '%s'\n", rdst->text);
+
+		memset(rdst->wk_text, 0, 64);
+		rdst->wk_text_mask = 0;
+		break;
+
+	default:
+		break;
+	}
+}
+
+int stfm1000_rds_packet_dequeue(struct stfm1000_rds_state *rds, u8 *buf)
+{
+	struct stfm1000_rds_pkt *pkt = &rds->pkt;
+
+	if (pkt->buf_cnt == 0)
+		return -1;
+
+	memcpy(buf, &pkt->buf_queue[pkt->buf_tail][0], 8);
+	if (++pkt->buf_tail >= RDS_PKT_QUEUE)
+		pkt->buf_tail = 0;
+	pkt->buf_cnt--;
+
+	return 0;
+}
+
+void stfm1000_rds_packet_bit(struct stfm1000_rds_state *rds, int bit)
+{
+	struct stfm1000_rds_pkt *pkt = &rds->pkt;
+	u32 rdsdata, rdscrc, rdscrc_c, rdscrc_cp;
+	int correct, correct2, recovered, recovered2;
+	int RetVal;
+
+	/* Stick into shift register */
+	pkt->rdsstream = ((pkt->rdsstream << 1) | bit) & 0x03ffffff;
+	pkt->bitsinfifo++;
+	pkt->bitcount++;
+
+	/* wait for 26 bits of block */
+	if (pkt->bitsinfifo < 26)
+		return;
+
+	rdsdata = pkt->rdsstream & 0x03fffc00;	/* 16 bits of Info. word */
+	rdscrc = pkt->rdsstream & 0x3ff;	/* 10 bits of Checkword */
+
+	switch (pkt->state) {
+	case SYNC_OFFSET_A:
+
+		RetVal = calc_syndrome(pkt->rdsstream);
+
+		switch (RetVal) {
+		case RDS_SYNDROME_OFFSETA:
+			pkt->state = OFFSET_B;
+			break;
+		case RDS_SYNDROME_OFFSETB:
+			pkt->state = OFFSET_C_CP;
+			break;
+		case RDS_SYNDROME_OFFSETC:
+			pkt->state = OFFSET_D;
+			break;
+		case RDS_SYNDROME_OFFSETCP:
+			pkt->state = OFFSET_D;
+			break;
+		case RDS_SYNDROME_OFFSETD:
+			pkt->state = OFFSET_A;
+			break;
+		default:
+			pkt->state = SYNC_OFFSET_A;
+			break;
+		}
+		if (pkt->state == SYNC_OFFSET_A) {
+			pkt->sync_lost_packets++;
+			/* XXX send info? */
+			break;
+		}
+
+		pkt->good_packets++;
+
+		rdsdata = pkt->rdsstream & 0x03fffc00;
+
+		/* Save type A packet in buffer */
+		rdsdata >>= 10;
+		pkt->buffer[0] = (rdsdata >> 8);
+		pkt->buffer[1] = (rdsdata & 0xff);
+		pkt->bitsinfifo = 0;
+
+		/* We found a block with zero errors, but it is not at the
+		 * start of the group. */
+		if (pkt->state == OFFSET_B)
+			pkt->discardpacket = 0;
+		else
+			pkt->discardpacket = 1;
+		break;
+
+	case OFFSET_A:		/* Type A: we are in sync now */
+		rdscrc ^= RDS_OFFSETA;
+		correct = ecc_correct(rdsdata | rdscrc, &recovered);
+		if (correct == UNRECOVERABLE_RDS_BLOCK) {
+			pkt->bad_packets++;
+			pkt->discardpacket++;
+			pkt->state++;
+			pkt->bitsinfifo = 0;
+			break;
+		}
+
+		if (recovered)
+			pkt->recovered_packets++;
+		pkt->good_packets++;
+
+		/* Attempt to see, if we can get the entire group.
+		 * Don't discard. */
+		pkt->discardpacket = 0;
+		rdsdata = correct & 0x03fffc00;
+
+		/* Save type A packet in buffer */
+		rdsdata >>= 10;
+		pkt->buffer[0] = (rdsdata >> 8);
+		pkt->buffer[1] = (rdsdata & 0xff);
+		pkt->bitsinfifo = 0;
+		pkt->state++;
+		break;
+
+	case OFFSET_B:		/* Waiting for type B */
+		rdscrc ^= RDS_OFFSETB;
+		correct = ecc_correct(rdsdata | rdscrc, &recovered);
+		if (correct == UNRECOVERABLE_RDS_BLOCK) {
+			pkt->bad_packets++;
+			pkt->discardpacket++;
+			pkt->state++;
+			pkt->bitsinfifo = 0;
+			break;
+		}
+		if (recovered)
+			pkt->recovered_packets++;
+		pkt->good_packets++;
+
+		rdsdata = correct & 0x03fffc00;
+
+		/* Save type B packet in buffer */
+		rdsdata >>= 10;
+		pkt->buffer[2] = (rdsdata >> 8);
+		pkt->buffer[3] = (rdsdata & 0xff);
+		pkt->bitsinfifo = 0;
+		pkt->state++;
+		break;
+
+	case OFFSET_C_CP:	/* Waiting for type C or C' */
+		rdscrc_c = rdscrc ^ RDS_OFFSETC;
+		rdscrc_cp = rdscrc ^ RDS_OFFSETCP;
+		correct = ecc_correct(rdsdata | rdscrc_c, &recovered);
+		correct2 = ecc_correct(rdsdata | rdscrc_cp, &recovered2);
+		if (correct == UNRECOVERABLE_RDS_BLOCK
+		    && correct2 == UNRECOVERABLE_RDS_BLOCK) {
+			pkt->bad_packets++;
+			pkt->discardpacket++;
+			pkt->state++;
+			pkt->bitsinfifo = 0;
+			break;
+		}
+
+		if (recovered || recovered2)
+			pkt->recovered_packets++;
+		pkt->good_packets++;
+
+		if (correct == UNRECOVERABLE_RDS_BLOCK)
+			correct = correct2;
+
+		rdsdata = correct & 0x03fffc00;
+
+		/* Save type C packet in buffer */
+		rdsdata >>= 10;
+		pkt->buffer[4] = (rdsdata >> 8);
+		pkt->buffer[5] = (rdsdata & 0xff);
+		pkt->bitsinfifo = 0;
+		pkt->state++;
+		break;
+
+	case OFFSET_D:		/* Waiting for type D */
+		rdscrc ^= RDS_OFFSETD;
+		correct = ecc_correct(rdsdata | rdscrc, &recovered);
+		if (correct == UNRECOVERABLE_RDS_BLOCK) {
+			pkt->bad_packets++;
+			pkt->discardpacket++;
+			pkt->state = OFFSET_A;
+			pkt->bitsinfifo = 0;
+			break;
+		}
+
+		if (recovered)
+			pkt->recovered_packets++;
+		pkt->good_packets++;
+
+		rdsdata = correct & 0x03fffc00;
+
+		/* Save type D packet in buffer */
+		rdsdata >>= 10;
+		pkt->buffer[6] = (rdsdata >> 8);
+		pkt->buffer[7] = (rdsdata & 0xff);
+
+		/* buffer it if all segments were ok */
+		if (pkt->discardpacket) {
+			/* We're still in sync, so back to state 1 */
+			pkt->state = OFFSET_A;
+			pkt->bitsinfifo = 0;
+			pkt->discardpacket = 0;
+			break;
+		}
+
+		pkt->state++;
+		/* fall-through */
+
+	case PACKET_OUT:
+		pkt->GroupDropOnce = 1;
+
+		/* queue packet */
+		if (pkt->buf_cnt < RDS_PKT_QUEUE) {
+			memcpy(&pkt->buf_queue[pkt->buf_head][0],
+				pkt->buffer, 8);
+			if (++pkt->buf_head >= RDS_PKT_QUEUE)
+				pkt->buf_head = 0;
+			pkt->buf_cnt++;
+		} else
+			pkt->buf_overruns++;
+
+		/* We're still in sync, so back to state 1 */
+		pkt->state = OFFSET_A;
+		pkt->bitsinfifo = 0;
+		pkt->discardpacket = 0;
+		break;
+
+	}
+
+	/* Lots of errors? If so, go back to resync mode */
+	if (pkt->discardpacket >= 10) {
+		pkt->state = SYNC_OFFSET_A;	/* reset sync state */
+		pkt->bitsinfifo = 26;	/* resync a bit faster */
+	}
+}
+
+/* GROUP_TYPE 0A-0B (buffer must have enough space for 9 bytes) */
+int stfm1000_rds_get_ps(struct stfm1000_rds_state *rds, u8 *buffer,
+	int bufsize)
+{
+	struct stfm1000_rds_text *rdst = &rds->text;
+
+	if (bufsize < 9)
+		return -1;
+
+	if (!rdst->ps_valid)
+		return -1;
+
+	memcpy(buffer, rdst->ps, 8);
+	buffer[8] = '\0';
+
+	return 8;
+}
+
+/* GROUP_TYPE 2A (buffer must have enough space for 65 bytes) */
+int stfm1000_rds_get_text(struct stfm1000_rds_state *rds, u8 *buffer,
+	int bufsize)
+{
+	struct stfm1000_rds_text *rdst = &rds->text;
+
+	if (bufsize < 9)
+		return -1;
+
+	if (!rdst->text_valid)
+		return -1;
+
+	memcpy(buffer, rdst->text, 64);
+	buffer[64] = '\0';
+
+	return 64;
+}
diff --git a/drivers/media/radio/stfm1000/stfm1000-rds.h b/drivers/media/radio/stfm1000/stfm1000-rds.h
new file mode 100644
index 000000000000..44b9a610f86e
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-rds.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef STFM1000_RDS_H
+#define STFM1000_RDS_H
+
+#include <linux/types.h>
+
+/* log2(number of samples in a filter basis) */
+#define RDS_BASISSHIFTS		4
+
+/* number of samples in a filter basis */
+#define RDS_BASISLENGTH		(1 << RDS_BASISSHIFTS)
+
+#define TIME_ADAPT_OVER		100
+
+/* 2^(-this) is the RMS leaky bucket time constant */
+#define RMSALPHASHIFTS		5
+
+#define PROCESS_RDS_BITS	128
+
+#define RDS_BITBUFSIZE		1024	/* was 128 */
+struct stfm1000_rds_bitstream {
+	u32 buf[RDS_BITBUFSIZE];	/* bit buffer */
+	int HeadBitCount;		/* bit buffer head counter */
+	int TailBitCount;		/* bit buffer tail counter */
+};
+
+struct stfm1000_rds_demod {
+	u32 mixandsum1;			/* Accumulator for first
+					 * basis filter */
+	u32 mixandsum2;			/* Accumulator for 2nd
+					 * basis filter */
+	u32 i;				/* Phase Index, 32 phases per
+					 * RDS bit */
+	u32 return_num;			/* Set if there is a new RDS bit */
+	u32 BitAlignmentCounter;	/* Counts bits for timing purposes */
+	int sampskip;			/* Requested timing shift (on i) */
+
+	int DisablePushing;		/* Disables phase push algorithm
+					 * (phase push happens when Ph_RMS[x],
+					 * x != 0, is consistently the maximum
+					 * Ph_RMS) */
+	int MixPopDone;			/* Last mixer phase set request is
+					 * done */
+	u8 rds_big_timeshift;		/* If set, indicates a push or large
+					 * timing shift occurred */
+	int return_rdsdemod;		/* Output, (most recent bit) XOR
+					 * (prev bit) */
+	u32 RDS_BIT_AMP_STAT_REG9;	/* Size of bit (RMS of RDS signal at
+					 * bitslicing instant, typically 220
+					 * to 270) */
+	s32 decomp_hist;		/* Most recent basis filter output */
+	s32 decomp_hist_p;		/* Previous basis filter output */
+	s32 PhaseValue[4];		/* Half-basis phase samples over the
+					 * most recent bit */
+	u32 Ph_RMS[4];			/* RMS of the four half-basis phases */
+	s32 timing_adj;			/* Timing loop leaky-bucket
+					 * accumulator */
+	u32 MixPhase0Mag;		/* Magnitude of RDS signal with RDS
+					 * mixer phase 0 (from mixer phase
+					 * determination) */
+	u32 MixPhase1Mag;		/* Magnitude of RDS signal with RDS
+					 * mixer phase 1 (from mixer phase
+					 * determination) */
+	u32 PhasePopMaxRMS;		/* Maximum RMS observed since last
+					 * phase pop */
+	u32 PrePopRMS;			/* Max of Ph_RMS array right before the
+					 * most recent phase pop */
+	u8 MixPhaseState;		/* State of RDS mixer phase
+					 * determination state machine */
+	int MixPhaseDetInProg;		/* Set if RDS mix phase determination
+					 * is in progress */
+	int sliced_data;		/* The most recent bit decision */
+	u8 PopSafetyZone;		/* Countdown timer, holds off next
+					 * phase pop after a recent one */
+	u8 PushSafetyZone;		/* Countdown timer, holds off next
+					 * phase pop after a timing push (b/c
+					 * timing push resets Ph_RMS vars) */
+	u8 SkipSafetyZone;		/* Countdown timer, holds off next
+					 * phase skip (small timing adj) */
+	int Synchronous;		/* RDS has been determined to be
+					 * synchronous to pilot */
+	u8 PushLastMaxPh;		/* The index at which Ph_RMS is
+					 * maximum ("x" in the above two
+					 * comments) */
+	s32 PushCounter;		/* Counts instances of Ph_RMS[x], x!=0,
+					 * being the maximum Ph_RMS */
+	s32 SkipsAccum;			/* Accumulation of all timing skips
+					 * since RDS demod started */
+	s32 SdnomSk;			/* Skips counter used for SDNOMINAL
+					 * adaption */
+
+	/* update this everytime it's changed & put it here */
+	unsigned int rds_mix_offset : 1;
+
+	unsigned int sdnom_adapt : 1;
+	unsigned int pCoefForcedMono : 1;	/* copy of filter parameter */
+	unsigned int PhasePoppingEnabled : 1;
+
+	unsigned int mix_msg_pending : 1;
+	u8 mix_msg;
+	unsigned int mix_msg_overrun;
+	unsigned int mix_msg_processed_changed;
+
+	unsigned int sdnominal_msg_pending : 1;
+	int sdnominal_msg;
+	unsigned int sdnominal_msg_overrun;
+
+	u32 RdsDemodSkippedBitCnt;	/* bit skipped by RDS demodulator due
+					 * to unavailable space in buf[]
+					 * (bit buffer) */
+};
+
+#define RDS_OFFSETA	0x0fc
+#define RDS_OFFSETB	0x198
+#define RDS_OFFSETC	0x168
+#define RDS_OFFSETCP	0x350
+#define RDS_OFFSETD	0x1b4
+
+#define RDS_SYNDROME_OFFSETA    0x3d8
+#define RDS_SYNDROME_OFFSETB    0x3d4
+#define RDS_SYNDROME_OFFSETC    0x25c
+#define RDS_SYNDROME_OFFSETCP   0x3cc
+#define RDS_SYNDROME_OFFSETD    0x258
+
+#define SYNC_OFFSET_A 0 /* default state */
+#define OFFSET_A      1
+#define OFFSET_B      2
+#define OFFSET_C_CP   3
+#define OFFSET_D      4
+#define PACKET_OUT    5
+
+#define ECC_TBL_SIZE   		    1024
+#define UNRECOVERABLE_RDS_BLOCK 0xffffffff
+
+#define RDS_PKT_QUEUE	16
+
+struct stfm1000_rds_pkt {
+	int state;		/* Current state */
+	u32 rdsstream;		/* Current RDS data */
+	u8 buffer[8];		/* temporary storage of RDS data */
+	int discardpacket;	/* discard packet count */
+	int sync_lost_packets;	/* sync lost */
+	int good_packets;	/* good packet */
+	int bad_packets;	/* bad packet */
+	int recovered_packets;	/* recovered packet */
+	int bitsinfifo;		/* bits count */
+	int GroupDropOnce;	/* Send Group Drop Message once */
+	int bitcount;		/* Counter for Number of Bits read */
+
+	/* queue the packets here */
+	int buf_overruns;
+	int buf_head;
+	int buf_tail;
+	int buf_cnt;
+	int buf_queue[RDS_PKT_QUEUE][8];
+};
+
+#define AUDIT            0
+#define ALL_SEGMENT_BITS 0xF
+#define ALL_TEXT_BITS    0xFFFF
+
+struct stfm1000_rds_pty {
+	u8  id;         /* Program Type ID */
+	u8 *pRds;       /* RDS description */
+	u8 *pRdbs;      /* RDBS description */
+};
+
+struct stfm1000_rds_text {
+	u8 bRds_detected;		/* Has the first packet come in yet? */
+	u16 pi;				/* Program Identification Code (PI) */
+	struct stfm1000_rds_pty pty;	/* Program Type (PTY)) */
+	u8 tp;				/* Traffic Program (TP) identification
+					 * code */
+	u8 ps[9];			/* Program Service Name Sent to UI */
+	u8 altFreq[2];			/* Alternate frequency (AF) */
+	u8 callLetters[5];		/* For US, stations call letters */
+
+	u8 text[65];			/* Radio Text A */
+
+	unsigned int version : 1;	/* Is station broadcasting version
+					 * A or B (B0) */
+	unsigned int ps_valid : 1;	/* station name is valid */
+	unsigned int text_valid : 1;	/* Text is valid */
+	unsigned int textAB_flag : 1;	/* Current flag setting, reset if flag
+					 * changes */
+
+	/*------------------Working area--------------------------- */
+	u8 cp_ps[8];			/* Compare buffer for PS */
+	u8 wk_ps[8];			/* Program Service buffer */
+	u8 wk_ps_mask;			/* lower 4 bits must be set
+					 * before copy */
+	u8 wk_text[64];			/* Radio Text buffer */
+	u16 wk_text_mask;		/* all bits must be set before copy */
+
+	/*-------------------Counters------------------------------ */
+	u32 messages;			/* total number of messages recieved */
+	u32 unsupported;		/* call to unsupported group type */
+	u32 mismatch;			/* Mismatched values */
+	u32 consecutiveGood;		/* Consecutive good will clear bad  */
+	u32 consecutiveGoodMax;		/* Max counter for paramaters */
+};
+
+/* Maximum number of RDS groups described in the U.S. RBDS Standard. */
+#define MAX_RDS_GROUPS_SUPPORTED 32
+
+/* Common Constants */
+#define RDS_LINE_FEED   0xA
+#define RDS_EOT         0xD
+
+/* Offsets into OFFSETB  */
+#define RDS_GROUP_TYPE(x)         (((x) >> 12) & 0xF)
+#define RDS_VERSION(x)            (((x) >> 11) & 0x1)
+#define RDS_TP(x)                 (((x) >> 10) & 0x1)
+#define RDS_PTY(x)                (((x) >>  5) & 0x1F)
+#define RDS_PS_SEG(x)              ((x) & 0x3)
+#define RDS_RT_AB(x)              (((x) >>  4) & 0x1)
+#define RDS_RT_SEG(x)              ((x) & 0xF)
+
+/* This values corresond to the Group Types defined */
+/* In the U.S. RBDS standard. */
+#define RDS_GROUP_TYPE_0A	 0 /* Basic tuning and switching information */
+#define RDS_GROUP_TYPE_0B	 1 /* Basic tuning and switching information */
+#define RDS_GROUP_TYPE_1A	 2 /* Program item number and slow labeling
+				    * codes */
+#define RDS_GROUP_TYPE_1B	 3 /* Program item number */
+#define RDS_GROUP_TYPE_2A	 4 /* Radio Text */
+#define RDS_GROUP_TYPE_2B	 5 /* Radio Text */
+#define RDS_GROUP_TYPE_3A	 6 /* Application identification for ODA
+				    * only */
+#define RDS_GROUP_TYPE_3B	 7 /* Open data applications */
+#define RDS_GROUP_TYPE_4A	 8 /* Clock-time and date */
+#define RDS_GROUP_TYPE_4B	 9 /* Open data applications */
+#define RDS_GROUP_TYPE_5A	10 /* Transparent Data Channels (32 channels)
+				    * or ODA */
+#define RDS_GROUP_TYPE_5B	11 /* Transparent Data Channels (32 channels)
+				    * or ODA */
+#define RDS_GROUP_TYPE_6A	12 /* In House Applications or ODA */
+#define RDS_GROUP_TYPE_6B	13 /* In House Applications or ODA */
+#define RDS_GROUP_TYPE_7A	14 /* Radio Paging or ODA */
+#define RDS_GROUP_TYPE_7B	15 /* Open Data Applications */
+#define RDS_GROUP_TYPE_8A	16 /* Traffic Message Channel or ODA */
+#define RDS_GROUP_TYPE_8B	17 /* Open Data Applications */
+#define RDS_GROUP_TYPE_9A	18 /* Emergency warning system or ODA */
+#define RDS_GROUP_TYPE_9B	19 /* Open Data Applications */
+#define RDS_GROUP_TYPE_10A	20 /* Program Type Name */
+#define RDS_GROUP_TYPE_10B	21 /* Open Data Applications */
+#define RDS_GROUP_TYPE_11A	22 /* Open Data Applications */
+#define RDS_GROUP_TYPE_11B	23 /* Open Data Applications */
+#define RDS_GROUP_TYPE_12A	24 /* Open Data Applications */
+#define RDS_GROUP_TYPE_12B	25 /* Open Data Applications */
+#define RDS_GROUP_TYPE_13A	26 /* Enhanced Radio Paging or ODA */
+#define RDS_GROUP_TYPE_13B	27 /* Open Data Applications */
+#define RDS_GROUP_TYPE_14A	28 /* Enhanced Other Networks information */
+#define RDS_GROUP_TYPE_14B	29 /* Enhanced Other Networks information */
+#define RDS_GROUP_TYPE_15A	30 /* Defined in RBDS */
+#define RDS_GROUP_TYPE_15B	31 /* Fast switching information */
+#define NUM_DEFINED_RDS_GROUPS	32 /* Number of groups defined in RBDS
+				    * standard */
+
+/* Structure representing Generic packet of 64 bits. */
+struct rds_group_data {
+	u16 piCode;	/* * Program ID */
+	u16 offsetB;	/* subject to group type */
+	u16 offsetC;	/* subject to group type */
+	u16 offsetD;	/* subject to group type */
+};
+
+/* Structure representing Group 0A (Service Name) */
+struct rds_group0A {
+	u16 piCode;	/* * Program ID */
+	u16 offsetB;	/* subject to group type */
+	u8 freq[2];	/* alt frequency 0=1 */
+	u8 text[2];	/* Name segment */
+};
+
+/* Structure representing Group 0B (Service Name) */
+struct rds_group0B {
+	u16 piCode;	/* * Program ID */
+	u16 offsetB;	/* subject to group type */
+	u16 piCode_dup;	/* Duplicate PI Code */
+	u8 text[2];	/* station text */
+};
+
+/* Structure representing Group 2A (Radio Text) (64 char) */
+struct rds_group2A {
+	u16 piCode;	/* * Program ID */
+	u16 offsetB;	/* subject to group type */
+	u8 text[4];
+};
+
+/* Structure representing Group 2B (Radio Text) (32 char) */
+struct rds_group2B {
+	u16 piCode;	/* * Program ID */
+	u16 offsetB;	/* subject to group type */
+	u16 piCode_dup;	/* Duplicate PI Code */
+	u8 text[2];
+};
+
+/* Structure representing all groups */
+union rds_msg {
+	struct rds_group2B gt2B;
+	struct rds_group2A gt2A;
+	struct rds_group0B gt0B;
+	struct rds_group0A gt0A;
+	struct rds_group_data gt00;
+};
+
+struct stfm1000_rds_state {
+	struct stfm1000_rds_bitstream bitstream;
+	struct stfm1000_rds_demod demod;
+	struct stfm1000_rds_pkt pkt;
+	struct stfm1000_rds_text text;
+	unsigned int reset_req : 1;
+};
+
+/* callback from rds etc. */
+void stfm1000_rds_reset(struct stfm1000_rds_state *rds);
+void stfm1000_rds_start(struct stfm1000_rds_state *rds);
+void stfm1000_rds_stop(struct stfm1000_rds_state *rds);
+
+/* call these from the monitor thread, but with interrupts disabled */
+int stfm1000_rds_mix_msg_get(struct stfm1000_rds_state *rds);
+int stfm1000_rds_mix_msg_processed(struct stfm1000_rds_state *rds,
+	int mix_msg);
+int stfm1000_rds_sdnominal_msg_get(struct stfm1000_rds_state *rds);
+int stfm1000_rds_sdnominal_msg_processed(struct stfm1000_rds_state *rds,
+	int sdnominal_msg);
+int stfm1000_rds_bits_available(struct stfm1000_rds_state *rds);
+int stmf1000_rds_get_bit(struct stfm1000_rds_state *rds);
+
+/* called from audio handler (interrupt) */
+void stfm1000_rds_demod(struct stfm1000_rds_state *rds, const u16 *dri_data,
+	int total);
+
+/* call these from monitor thread, interrupts enabled */
+void stfm1000_rds_packet_bit(struct stfm1000_rds_state *rds, int bit);
+int stfm1000_rds_packet_dequeue(struct stfm1000_rds_state *rds, u8 *buf);
+void stfm1000_rds_process_packet(struct stfm1000_rds_state *rds, u8 *buffer);
+
+static inline int stfm1000_rds_get_reset_req(struct stfm1000_rds_state *rds)
+{
+	return rds->reset_req;
+}
+
+/* GROUP_TYPE 0A-0B */
+int stfm1000_rds_get_ps(struct stfm1000_rds_state *rds, u8 *buffer,
+	int bufsize);
+
+/* GROUP_TYPE 2A */
+int stfm1000_rds_get_text(struct stfm1000_rds_state *rds, u8 *buffer,
+	int bufsize);
+
+#endif
diff --git a/drivers/media/radio/stfm1000/stfm1000-regs.h b/drivers/media/radio/stfm1000/stfm1000-regs.h
new file mode 100644
index 000000000000..c9476b7d67e1
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000-regs.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef STFM1000_REGS_H
+#define STFM1000_REGS_H
+
+/* registers */
+#define STFM1000_TUNE1			0x00
+#define STFM1000_SDNOMINAL		0x04
+#define STFM1000_PILOTTRACKING		0x08
+#define STFM1000_INITIALIZATION1	0x10
+#define STFM1000_INITIALIZATION2	0x14
+#define STFM1000_INITIALIZATION3	0x18
+#define STFM1000_INITIALIZATION4	0x1C
+#define STFM1000_INITIALIZATION5	0x20
+#define STFM1000_INITIALIZATION6	0x24
+#define STFM1000_REF			0x28
+#define STFM1000_LNA			0x2C
+#define STFM1000_MIXFILT		0x30
+#define STFM1000_CLK1			0x34
+#define STFM1000_CLK2			0x38
+#define STFM1000_ADC			0x3C
+#define STFM1000_AGC_CONTROL1		0x44
+#define STFM1000_AGC_CONTROL2		0x48
+#define STFM1000_DATAPATH		0x5C
+#define STFM1000_RMS			0x60
+#define STFM1000_AGC_STAT		0x64
+#define STFM1000_SIGNALQUALITY		0x68
+#define STFM1000_DCEST			0x6C
+#define STFM1000_RSSI_TONE		0x70
+#define STFM1000_PILOTCORRECTION	0x74
+#define STFM1000_ATTENTION		0x78
+#define STFM1000_CLK3			0x7C
+#define STFM1000_CHIPID			0x80
+
+/* number of registers */
+#define STFM1000_NUM_REGS		((0x80 + 4) / 4)
+
+#define STFM1000_FREQUENCY_100KHZ_MIN	758
+#define STFM1000_FREQUENCY_100KHZ_RANGE	325
+#define STFM1000_FREQUENCY_100KHZ_MAX	(STFM1000_FREQUENCY_100KHZ_MIN + \
+					STFM1000_FREQUENCY_100KHZ_RANGE)
+
+#define STFM1000_TUNE1_B2_MIX		0x001C0000
+#define STFM1000_TUNE1_CICOSR		0x00007E00
+#define STFM1000_TUNE1_PLL_DIV		0x000001FF
+
+#define STFM1000_CHIP_REV_TA1		0x00000001
+#define STFM1000_CHIP_REV_TA2		0x00000002
+#define STFM1000_CHIP_REV_TB1		0x00000011
+#define STFM1000_CHIP_REV_TB2		0x00000012
+
+/* DATAPATH bits we use */
+#define STFM1000_DP_EN			0x01000000
+#define STFM1000_DB_ACCEPT		0x00010000
+#define STFM1000_SAI_CLK_DIV_MASK	0x7c
+#define STFM1000_SAI_CLK_DIV_SHIFT	2
+#define STFM1000_SAI_CLK_DIV(x) \
+	(((x) << STFM1000_SAI_CLK_DIV_SHIFT) & STFM1000_SAI_CLK_DIV_MASK)
+#define STFM1000_SAI_EN			0x00000001
+
+/* AGC_CONTROL1 bits we use */
+#define STFM1000_B2_BYPASS_AGC_CTL	0x00004000
+#define STFM1000_B2_BYPASS_FILT_MASK	0x0000000C
+#define STFM1000_B2_BYPASS_FILT_SHIFT	2
+#define STFM1000_B2_BYPASS_FILT(x) \
+	(((x) << STFM1000_B2_BYPASS_FILT_SHIFT) & STFM1000_B2_BYPASS_FILT_MASK)
+#define STFM1000_B2_LNATH_MASK		0x001F0000
+#define STFM1000_B2_LNATH_SHIFT		16
+#define STFM1000_B2_LNATH(x) \
+	(((x) << STFM1000_B2_LNATH_SHIFT) & STFM1000_B2_LNATH_MASK)
+
+/* AGC_STAT bits we use */
+#define STFM1000_AGCOUT_STAT_MASK	0x1F000000
+#define STFM1000_AGCOUT_STAT_SHIFT	24
+#define STFM1000_LNA_RMS_MASK		0x00001F00
+#define STFM1000_LNA_RMS_SHIFT		8
+
+/* PILOTTRACKING bits we use */
+#define STFM1000_B2_PILOTTRACKING_EN		0x00008000
+#define STFM1000_B2_PILOTLPF_TIMECONSTANT_MASK	0x00000f00
+#define STFM1000_B2_PILOTLPF_TIMECONSTANT_SHIFT	8
+#define STFM1000_B2_PILOTLPF_TIMECONSTANT(x)	\
+	(((x) << STFM1000_B2_PILOTLPF_TIMECONSTANT_SHIFT) & \
+		STFM1000_B2_PILOTLPF_TIMECONSTANT_MASK)
+#define STFM1000_B2_PFDSCALE_MASK		0x000000f0
+#define STFM1000_B2_PFDSCALE_SHIFT		4
+#define STFM1000_B2_PFDSCALE(x)	\
+	(((x) << STFM1000_B2_PFDSCALE_SHIFT) & STFM1000_B2_PFDSCALE_MASK)
+#define STFM1000_B2_PFDFILTER_SPEEDUP_MASK	0x0000000f
+#define STFM1000_B2_PFDFILTER_SPEEDUP_SHIFT	0
+#define STFM1000_B2_PFDFILTER_SPEEDUP(x)	\
+	(((x) << STFM1000_B2_PFDFILTER_SPEEDUP_SHIFT) & \
+		STFM1000_B2_PFDFILTER_SPEEDUP_MASK)
+
+/* PILOTCORRECTION bits we use */
+#define STFM1000_PILOTEST_TA2_MASK	0xff000000
+#define STFM1000_PILOTEST_TA2_SHIFT	24
+#define STFM1000_PILOTEST_TB2_MASK	0xfe000000
+#define STFM1000_PILOTEST_TB2_SHIFT	25
+
+/* INITIALIZATION1 bits we use */
+#define STFM1000_B2_BYPASS_FILT_MASK	0x0000000C
+#define STFM1000_B2_BYPASS_FILT_SHIFT	2
+#define STFM1000_B2_BYPASS_FILT(x)	\
+	(((x) << STFM1000_B2_BYPASS_FILT_SHIFT) & STFM1000_B2_BYPASS_FILT_MASK)
+
+/* INITIALIZATION2 bits we use */
+#define STFM1000_DRI_CLK_EN		0x80000000
+#define STFM1000_DEEMPH_50_75B		0x00000100
+#define STFM1000_RDS_ENABLE		0x00100000
+#define STFM1000_RDS_MIXOFFSET		0x00200000
+
+/* INITIALIZATION3 bits we use */
+#define STFM1000_B2_NEAR_CHAN_MIX_MASK	0x1c000000
+#define STFM1000_B2_NEAR_CHAN_MIX_SHIFT	26
+#define STFM1000_B2_NEAR_CHAN_MIX(x)	\
+	(((x) << STFM1000_B2_NEAR_CHAN_MIX_SHIFT) & \
+		STFM1000_B2_NEAR_CHAN_MIX_MASK)
+
+/* CLK1 bits we use */
+#define STFM1000_ENABLE_TAPDELAYFIX	0x00000020
+
+/* REF bits we use */
+#define STFM1000_LNA_AMP1_IMPROVE_DISTORTION 0x08000000
+
+/* LNA bits we use */
+#define STFM1000_AMP2_IMPROVE_DISTORTION 0x08000000
+#define STFM1000_ANTENNA_TUNECAP_MASK	0x001F0000
+#define STFM1000_ANTENNA_TUNECAP_SHIFT	16
+#define STFM1000_ANTENNA_TUNECAP(x)	\
+	(((x) << STFM1000_ANTENNA_TUNECAP_SHIFT) & \
+		STFM1000_ANTENNA_TUNECAP_MASK)
+#define STFM1000_IBIAS2_UP		0x00000008
+#define STFM1000_IBIAS2_DN		0x00000004
+#define STFM1000_IBIAS1_UP		0x00000002
+#define STFM1000_IBIAS1_DN		0x00000001
+#define STFM1000_USEATTEN_MASK		0x00600000
+#define STFM1000_USEATTEN_SHIFT		21
+#define STFM1000_USEATTEN(x)	\
+	(((x) << STFM1000_USEATTEN_SHIFT) & STFM1000_USEATTEN_MASK)
+
+/* SIGNALQUALITY bits we use */
+#define STFM1000_NEAR_CHAN_AMPLITUDE_MASK	0x0000007F
+#define STFM1000_NEAR_CHAN_AMPLITUDE_SHIFT	0
+#define STFM1000_NEAR_CHAN_AMPLITUDE(x)	\
+	(((x) << STFM1000_NEAR_CHAN_AMPLITUDE_SHIFT) & \
+		STFM1000_NEAR_CHAN_AMPLITUDE_MASK)
+
+/* precalc tables elements */
+struct stfm1000_tune1 {
+	unsigned int tune1;	/* at least 32 bit */
+	unsigned int sdnom;
+};
+
+#endif
diff --git a/drivers/media/radio/stfm1000/stfm1000.h b/drivers/media/radio/stfm1000/stfm1000.h
new file mode 100644
index 000000000000..5ae6f38db3b0
--- /dev/null
+++ b/drivers/media/radio/stfm1000/stfm1000.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef STFM1000_H
+#define STFM1000_H
+
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <linux/i2c.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/irq.h>
+#include <media/videobuf-dma-sg.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <mach/dma.h>
+
+#include "stfm1000-regs.h"
+
+#include "stfm1000-filter.h"
+#include "stfm1000-rds.h"
+
+struct stfm1000 {
+	struct list_head devlist;
+	int idx;
+
+	struct i2c_client *client;
+	struct video_device radio;
+
+	/* alsa */
+	struct snd_card *card;
+	struct snd_pcm *pcm;
+	struct snd_pcm_substream *substream;
+	struct stmp3xxx_dma_descriptor *dma;
+	int desc_num;
+	int dma_ch;
+	int dma_irq;
+	int attn_irq;
+
+	struct mutex state_lock;
+	int read_count;
+	int read_offset;
+	int blocks;
+	int blksize;
+	int bufsize;
+
+	struct mutex deffered_work_lock;
+	struct execute_work snd_capture_start_work;
+	struct execute_work snd_capture_stop_work;
+
+	int now_recording;
+	int alsa_initialized;
+	int stopping_recording;
+
+	/* actual DRI buffer */
+	dma_addr_t dri_phys;
+	void *dri_buf;
+	int dri_bufsz;
+
+	/* various */
+	u16 curvol;
+	int users;
+	int removed;
+	struct mutex xfer_lock;
+	u8 revid;
+
+	unsigned int dbgflg;
+
+	/* shadow registers */
+	u32 shadow_regs[STFM1000_NUM_REGS];
+	u32 reg_rw_set[(STFM1000_NUM_REGS + 31) / 32];
+	u32 reg_ra_set[(STFM1000_NUM_REGS + 31) / 32];
+	u32 reg_dirty_set[(STFM1000_NUM_REGS + 31) / 32];
+
+	/* tuning parameters (not everything is used for now) */
+	u16 tune_rssi_th;		/* sd_ctl_TuneRssiTh_u16 */
+	u16 tune_mpx_dc_th;		/* sd_ctl_TuneMpxDcTh_u16 */
+	u16 adj_chan_th;		/* sd_ctl_AdjChanTh_u16 */
+	u16 pilot_est_th;		/* sd_ctl_PilotEstTh_u16 */
+	u16 coef_lna_turn_off_th;	/* sd_ctl_pCoefLnaTurnOffTh_u16 */
+	u16 coef_lna_turn_on_th;	/* sd_ctl_pCoefLnaTurnOnTh_u16 */
+	u16 reg_agc_ref_lna_off;	/* sd_ctl_pRegAgcRefLnaOff_u16 */
+	u16 reg_agc_ref_lna_on;		/* sd_ctl_pRegAgcRefLnaOn_u16 */
+
+	u32 sdnominal_pivot;		/* sd_ctl_SdnominalData_u32 */
+
+	/* jiffies of the next monitor cycle */
+	unsigned long next_quality_monitor;
+	unsigned long next_agc_monitor;
+
+	unsigned int mute : 1;			/* XXX */
+	unsigned int lna_driving : 1;		/* sd_ctl_LnaDriving_u1 */
+	unsigned int weak_signal : 1;		/* sd_ctl_WeakSignal_u1 */
+	unsigned int is_station : 1;		/* XXX */
+	unsigned int force_mono : 1;		/* XXX */
+	unsigned int signal_indicator : 1;	/* XXX */
+	unsigned int stereo_indicator : 1;	/* XXX */
+	unsigned int agc_monitor : 1;		/* XXX */
+	unsigned int quality_monitor : 1;	/* XXX */
+	unsigned int pilot_present : 1;		/* sd_ctl_PilotPresent_u1 */
+	unsigned int prev_pilot_present : 1;	/* XXX */
+	unsigned int stereo : 1;
+	unsigned int active : 1;		/* set when audio enabled */
+	unsigned int rds_enable : 1;		/* set when rds is enabled */
+	unsigned int rds_present : 1;		/* RDS info present */
+	unsigned int rds_sync : 1;		/* RDS force sync */
+	unsigned int rds_demod_running : 1;	/* RDS demod is running ATM */
+	unsigned int rds_sdnominal_adapt : 1;	/* adapt for better recept. */
+	unsigned int rds_phase_pop : 1;		/* enable phase pop */
+	unsigned int rds_info : 1;		/* print debugging info RDS */
+	unsigned int tuning_grid_50KHz : 1;	/* tuning grid of 50Khz */
+	u32 rssi;				/* rssi last decoded frame */
+	u16 rssi_dc_est_log;
+	u16 signal_strength;			/* is rssi_dc_est_log */
+	u16 rds_signal_th;			/* RDS threshold */
+	s16 mpx_dc;				/* sd_ctl_ShadowToneData_i16 */
+
+	u32 tune_cap_a_f;			/* float! sd_ctl_TuneCapA_f */
+	u32 tune_cap_b_f;			/* float! sd_ctl_TuneCapB_f */
+
+	int monitor_period;			/* period of the monitor */
+	int quality_monitor_period;		/* update period in ms */
+	int agc_monitor_period;			/* update period in ms */
+
+	int georegion;				/* current graphical region */
+
+	/* last tuned frequency */
+	int freq;				/* 88.0 = 8800 */
+
+	/* weak signal processing filter state */
+	struct stfm1000_filter_parms filter_parms;
+
+	/* state of rds */
+	spinlock_t rds_lock;
+	struct stfm1000_rds_state rds_state;
+	unsigned int rds_pkt_bad;
+	unsigned int rds_pkt_good;
+	unsigned int rds_pkt_recovered;
+	unsigned int rds_pkt_lost_sync;
+	unsigned int rds_bit_overruns;
+
+	/* monitor thread */
+	wait_queue_head_t thread_wait;
+	unsigned long thread_events;
+	struct task_struct *thread;
+};
+
+#define EVENT_RDS_BITS		0
+#define EVENT_RDS_MIXFILT	1
+#define EVENT_RDS_SDNOMINAL	2
+#define EVENT_RDS_RESET		3
+
+#define STFM1000_DBGFLG_I2C	(1 << 0)
+
+static inline struct stfm1000 *stfm1000_from_file(struct file *file)
+{
+	return container_of(video_devdata(file), struct stfm1000, radio);
+}
+
+/* in stfm1000-i2c.c */
+
+/* setup reg set */
+void stfm1000_setup_reg_set(struct stfm1000 *stfm1000);
+
+/* direct access to registers bypassing the shadow register set */
+int stfm1000_raw_read(struct stfm1000 *stfm1000, int reg, u32 *value);
+int stfm1000_raw_write(struct stfm1000 *stfm1000, int reg, u32 value);
+
+/* access using the shadow register set */
+int stfm1000_write(struct stfm1000 *stfm1000, int reg, u32 value);
+int stfm1000_read(struct stfm1000 *stfm1000, int reg, u32 *value);
+int stfm1000_write_masked(struct stfm1000 *stfm1000, int reg, u32 value,
+		u32 mask);
+int stfm1000_set_bits(struct stfm1000 *stfm1000, int reg, u32 value);
+int stfm1000_clear_bits(struct stfm1000 *stfm1000, int reg, u32 value);
+
+struct stfm1000_reg {
+	unsigned int regno;
+	u32 value;
+};
+
+#define STFM1000_REG_END	-1
+#define STFM1000_REG_DELAY	-2
+
+#define STFM1000_REG_SET_BITS_MASK	0x1000
+#define STFM1000_REG_CLEAR_BITS_MASK	0x2000
+
+#define STFM1000_REG(r, v) \
+	{ .regno = STFM1000_ ## r , .value = (v) }
+
+#define STFM1000_END \
+	{ .regno = STFM1000_REG_END }
+
+#define STFM1000_DELAY(x) \
+	{ .regno = STFM1000_REG_DELAY, .value = (x) }
+
+#define STFM1000_REG_SETBITS(r, v) \
+	{ .regno = STFM1000_ ## r | STFM1000_REG_SET_BITS_MASK, \
+		.value = (v) }
+
+#define STFM1000_REG_CLRBITS(r, v) \
+	{ .regno = STFM1000_ ## r | STFM1000_REG_CLEAR_BITS_MASK, \
+		.value = (v) }
+
+int stfm1000_write_regs(struct stfm1000 *stfm1000,
+		const struct stfm1000_reg *reg);
+
+/* in stfm1000-precalc.c */
+extern const struct stfm1000_tune1
+stfm1000_tune1_table[STFM1000_FREQUENCY_100KHZ_RANGE];
+
+/* exported for use by alsa driver */
+
+struct stfm1000_dri_sample {
+	/* L+R */
+	u16 l_plus_r;
+	/* L-R */
+	u16 l_minus_r;
+	/* Rx signal strength channel */
+	u16 rssi;
+	/* Radio data service channel */
+	u16 rds;
+};
+
+struct stfm1000_alsa_ops {
+	int  (*init)(struct stfm1000 *stfm1000);
+	void  (*release)(struct stfm1000 *stfm1000);
+	void (*dma_irq)(struct stfm1000 *stfm1000);
+	void (*attn_irq)(struct stfm1000 *stfm1000);
+};
+
+extern struct list_head stfm1000_devlist;
+extern struct stfm1000_alsa_ops *stfm1000_alsa_ops;
+
+/* needed for setting the interrupt handlers from alsa */
+irqreturn_t stfm1000_dri_attn_irq(int irq, void *dev_id);
+irqreturn_t stfm1000_dri_dma_irq(int irq, void *dev_id);
+void stfm1000_decode_block(struct stfm1000 *stfm1000, const s16 *src, s16 *dst, int count);
+void stfm1000_take_down(struct stfm1000 *stfm1000);
+void stfm1000_bring_up(struct stfm1000 *stfm1000);
+void stfm1000_tune_current(struct stfm1000 *stfm1000);
+
+void stfm1000_monitor_signal(struct stfm1000 *stfm1000, int bit);
+
+#endif
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index dcf9fa9264bb..c64c8d201262 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -550,6 +550,57 @@ config VIDEO_W9966
 	  Check out <file:Documentation/video4linux/w9966.txt> for more
 	  information.
 
+config VIDEO_MXC_CAMERA
+	tristate "MXC Video For Linux Camera"
+	depends on VIDEO_DEV && ARCH_MXC
+	default y
+	---help---
+	  This is the video4linux2 capture driver based on MXC IPU/eMMA module.
+
+source "drivers/media/video/mxc/capture/Kconfig"
+
+config VIDEO_MXC_OUTPUT
+	tristate "MXC Video For Linux Video Output"
+	depends on VIDEO_DEV && ARCH_MXC
+	default y
+	---help---
+	  This is the video4linux2 output driver based on MXC IPU/eMMA module.
+
+source "drivers/media/video/mxc/output/Kconfig"
+
+config VIDEO_PXP
+	tristate "STMP3XXX PxP"
+	depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_STMP3XXX
+	select VIDEOBUF_DMA_CONTIG
+	---help---
+	  This is a video4linux driver for the Freescale PxP
+	  (Pixel Pipeline). This module supports output overlay of
+	  the STMP3xxx framebuffer on a video stream.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called pxp.
+
+config VIDEO_MXS_PXP
+	tristate "MXS PxP"
+	depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXS
+	select VIDEOBUF_DMA_CONTIG
+	---help---
+	  This is a video4linux driver for the Freescale PxP
+	  (Pixel Pipeline). This module supports output overlay of
+	  the MXS framebuffer on a video stream.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called pxp.
+
+config VIDEO_MXC_OPL
+	tristate
+	depends on VIDEO_DEV && ARCH_MXC
+	default n
+	---help---
+	  This is the ARM9-optimized OPL (Open Primitives Library) software
+	  rotation/mirroring implementation. It may be used by eMMA video
+	  capture or output device.
+
 config VIDEO_CPIA
 	tristate "CPiA Video For Linux"
 	depends on VIDEO_V4L1
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 9f2e3214a482..49cb18802024 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -88,6 +88,15 @@ obj-$(CONFIG_VIDEO_W9966) += w9966.o
 obj-$(CONFIG_VIDEO_PMS) += pms.o
 obj-$(CONFIG_VIDEO_VINO) += vino.o
 obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
+obj-$(CONFIG_VIDEO_MXC_IPU_CAMERA) += mxc/capture/
+obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mxc/capture/
+obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += mxc/capture/
+obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc/output/
+obj-$(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT) += mxc/output/
+obj-$(CONFIG_VIDEO_MXC_EMMA_OUTPUT) += mxc/output/
+obj-$(CONFIG_VIDEO_MXC_OPL) += mxc/opl/
+obj-$(CONFIG_VIDEO_PXP)	+= pxp.o
+obj-$(CONFIG_VIDEO_MXS_PXP)	+= mxs_pxp.o
 obj-$(CONFIG_VIDEO_CPIA) += cpia.o
 obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o
 obj-$(CONFIG_VIDEO_CPIA_USB) += cpia_usb.o
diff --git a/drivers/media/video/mxc/capture/Kconfig b/drivers/media/video/mxc/capture/Kconfig
new file mode 100644
index 000000000000..1b352afebd87
--- /dev/null
+++ b/drivers/media/video/mxc/capture/Kconfig
@@ -0,0 +1,123 @@
+if VIDEO_MXC_CAMERA
+
+menu "MXC Camera/V4L2 PRP Features support"
+config VIDEO_MXC_IPU_CAMERA
+	bool
+	depends on VIDEO_MXC_CAMERA && MXC_IPU
+	default y
+
+config VIDEO_MXC_EMMA_CAMERA
+	tristate "MX27 eMMA support"
+	depends on VIDEO_MXC_CAMERA && MXC_EMMA && FB_MXC_SYNC_PANEL
+	select VIDEO_MXC_OPL
+	default y
+
+config VIDEO_MXC_CSI_CAMERA
+	tristate "MX25 CSI camera support"
+	depends on !VIDEO_MXC_EMMA_CAMERA
+
+config VIDEO_MXC_CSI_DMA
+	bool "CSI-DMA Still Image Capture support"
+	depends on VIDEO_MXC_EMMA_CAMERA
+	default n
+	---help---
+	  Use CSI-DMA method instead of CSI-PrP link to capture still image. This allows
+	  to use less physical contiguous memory to capture big resolution still image. But
+	  with this method the CSC (Color Space Conversion) and resize are not supported.
+	  If unsure, say N.
+
+choice
+	prompt "Select Camera/TV Decoder"
+	default MXC_CAMERA_OV3640
+	depends on VIDEO_MXC_CAMERA
+
+config MXC_CAMERA_MC521DA
+	tristate "Magnachip mc521da camera support"
+	select I2C_MXC
+	depends on VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the mc521da Camera with your MXC system, say Y here.
+
+config MXC_EMMA_CAMERA_MICRON111
+	tristate "Micron mt9v111 camera support with eMMA"
+	select I2C_MXC
+	depends on VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the mt9v111 Camera with your MXC system, say Y here.
+
+config MXC_CAMERA_OV2640_EMMA
+	tristate "OmniVision ov2640 camera support with eMMA"
+	depends on VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the ov2640 Camera with your MXC system, say Y here.
+
+config MXC_CAMERA_MICRON111
+	tristate "Micron mt9v111 camera support"
+	select I2C_MXC
+	depends on ! VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the mt9v111 Camera with your MXC system, say Y here.
+
+config MXC_CAMERA_OV2640
+	tristate "OmniVision ov2640 camera support"
+	depends on !VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the ov2640 Camera with your MXC system, say Y here.
+
+config MXC_CAMERA_OV3640
+	tristate "OmniVision ov3640 camera support"
+	depends on !VIDEO_MXC_EMMA_CAMERA
+	---help---
+	  If you plan to use the ov3640 Camera with your MXC system, say Y here.
+
+config MXC_TVIN_ADV7180
+	tristate "Analog Device adv7180 TV Decoder Input support"
+	depends on (MACH_MX35_3DS || MACH_MX51_3DS)
+	---help---
+	  If you plan to use the adv7180 video decoder with your MXC system, say Y here.
+
+endchoice
+
+config MXC_IPU_PRP_VF_SDC
+	tristate "Pre-Processor VF SDC library"
+	depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL
+	default y
+	---help---
+	  Use case PRP_VF_SDC:
+		Preprocessing image from smart sensor for viewfinder and
+		displaying it on synchronous display with SDC use case.
+		If SDC BG is selected, Rotation will not be supported.
+		CSI -> IC (PRP VF) -> MEM
+		MEM -> IC (ROT) -> MEM
+		MEM -> SDC (FG/BG)
+
+config MXC_IPU_PRP_VF_ADC
+	tristate "Pre-Processor VF ADC library"
+	depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_ASYNC_PANEL
+	default y
+	---help---
+	  Use case PRP_VF_ADC:
+		Preprocessing image from smart sensor for viewfinder and
+		displaying it on asynchronous display.
+		CSI -> IC (PRP VF) -> ADC2
+
+config MXC_IPU_PRP_ENC
+	tristate "Pre-processor Encoder library"
+	depends on VIDEO_MXC_IPU_CAMERA
+	default y
+	---help---
+	  Use case PRP_ENC:
+		Preprocessing image from smart sensor for encoder.
+		CSI -> IC (PRP ENC) -> MEM
+
+config MXC_IPU_CSI_ENC
+	tristate "IPU CSI Encoder library"
+	depends on VIDEO_MXC_IPU_CAMERA
+	default y
+	---help---
+	  Use case IPU_CSI_ENC:
+		Get raw image with CSI from smart sensor for encoder.
+		CSI -> MEM
+endmenu
+
+endif
diff --git a/drivers/media/video/mxc/capture/Makefile b/drivers/media/video/mxc/capture/Makefile
new file mode 100644
index 000000000000..03ff094171bf
--- /dev/null
+++ b/drivers/media/video/mxc/capture/Makefile
@@ -0,0 +1,39 @@
+ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y)
+	obj-$(CONFIG_VIDEO_MXC_CAMERA) += mxc_v4l2_capture.o
+	obj-$(CONFIG_MXC_IPU_PRP_VF_ADC) += ipu_prp_vf_adc.o
+	obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o
+	obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o
+	obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o
+endif
+
+obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += fsl_csi.o csi_v4l2_capture.o
+
+mx27_capture-objs := mx27_prphw.o mx27_prpsw.o emma_v4l2_capture.o
+obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mx27_csi.o mx27_capture.o
+
+mc521da_camera-objs := mc521da.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_MC521DA) += mc521da_camera.o
+
+emma_mt9v111_camera-objs := emma_mt9v111.o sensor_clock.o
+obj-$(CONFIG_MXC_EMMA_CAMERA_MICRON111) += emma_mt9v111_camera.o
+
+mt9v111_camera-objs := mt9v111.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_MICRON111) += mt9v111_camera.o
+
+hv7161_camera-objs := hv7161.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_HV7161) += hv7161_camera.o
+
+s5k3aaex_camera-objs := s5k3aaex.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_S5K3AAEX) += s5k3aaex_camera.o
+
+emma_ov2640_camera-objs := emma_ov2640.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_OV2640_EMMA) += emma_ov2640_camera.o
+
+ov2640_camera-objs := ov2640.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_OV2640) += ov2640_camera.o
+
+ov3640_camera-objs := ov3640.o sensor_clock.o
+obj-$(CONFIG_MXC_CAMERA_OV3640) += ov3640_camera.o
+
+adv7180_tvin-objs := adv7180.o
+obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
diff --git a/drivers/media/video/mxc/capture/adv7180.c b/drivers/media/video/mxc/capture/adv7180.c
new file mode 100644
index 000000000000..527a0d1ad9fa
--- /dev/null
+++ b/drivers/media/video/mxc/capture/adv7180.c
@@ -0,0 +1,1001 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file adv7180.c
+ *
+ * @brief Analog Device ADV7180 video decoder functions
+ *
+ * @ingroup Camera
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/wait.h>
+#include <linux/videodev2.h>
+#include <linux/workqueue.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-int-device.h>
+#include <mach/hardware.h>
+#include "mxc_v4l2_capture.h"
+
+static struct regulator *dvddio_regulator;
+static struct regulator *dvdd_regulator;
+static struct regulator *avdd_regulator;
+static struct regulator *pvdd_regulator;
+static struct mxc_tvin_platform_data *tvin_plat;
+
+extern void gpio_sensor_active(void);
+extern void gpio_sensor_inactive(void);
+
+static int adv7180_probe(struct i2c_client *adapter,
+			 const struct i2c_device_id *id);
+static int adv7180_detach(struct i2c_client *client);
+
+static const struct i2c_device_id adv7180_id[] = {
+	{"adv7180", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, adv7180_id);
+
+static struct i2c_driver adv7180_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "adv7180",
+		   },
+	.probe = adv7180_probe,
+	.remove = adv7180_detach,
+	.id_table = adv7180_id,
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+struct sensor {
+	struct v4l2_int_device *v4l2_int_device;
+	struct i2c_client *i2c_client;
+	struct v4l2_pix_format pix;
+	struct v4l2_captureparm streamcap;
+	bool on;
+
+	/* control settings */
+	int brightness;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+	v4l2_std_id std_id;
+} adv7180_data;
+
+/*! List of input video formats supported. The video formats is corresponding
+ * with v4l2 id in video_fmt_t
+ */
+typedef enum {
+	ADV7180_NTSC = 0,	/*!< Locked on (M) NTSC video signal. */
+	ADV7180_PAL,		/*!< (B, G, H, I, N)PAL video signal. */
+	ADV7180_NOT_LOCKED,	/*!< Not locked on a signal. */
+} video_fmt_idx;
+
+/*! Number of video standards supported (including 'not locked' signal). */
+#define ADV7180_STD_MAX		(ADV7180_PAL + 1)
+
+/*! Video format structure. */
+typedef struct {
+	int v4l2_id;		/*!< Video for linux ID. */
+	char name[16];		/*!< Name (e.g., "NTSC", "PAL", etc.) */
+	u16 raw_width;		/*!< Raw width. */
+	u16 raw_height;		/*!< Raw height. */
+	u16 active_width;	/*!< Active width. */
+	u16 active_height;	/*!< Active height. */
+} video_fmt_t;
+
+/*! Description of video formats supported.
+ *
+ *  PAL: raw=720x625, active=720x576.
+ *  NTSC: raw=720x525, active=720x480.
+ */
+static video_fmt_t video_fmts[] = {
+	{			/*! NTSC */
+	 .v4l2_id = V4L2_STD_NTSC,
+	 .name = "NTSC",
+	 .raw_width = 720,	/* SENS_FRM_WIDTH */
+	 .raw_height = 525,	/* SENS_FRM_HEIGHT */
+	 .active_width = 720,	/* ACT_FRM_WIDTH plus 1 */
+	 .active_height = 480,	/* ACT_FRM_WIDTH plus 1 */
+	 },
+	{			/*! (B, G, H, I, N) PAL */
+	 .v4l2_id = V4L2_STD_PAL,
+	 .name = "PAL",
+	 .raw_width = 720,
+	 .raw_height = 625,
+	 .active_width = 720,
+	 .active_height = 576,
+	 },
+	{			/*! Unlocked standard */
+	 .v4l2_id = V4L2_STD_ALL,
+	 .name = "Autodetect",
+	 .raw_width = 720,
+	 .raw_height = 625,
+	 .active_width = 720,
+	 .active_height = 576,
+	 },
+};
+
+/*!* Standard index of ADV7180. */
+static video_fmt_idx video_idx = ADV7180_PAL;
+
+/*! @brief This mutex is used to provide mutual exclusion.
+ *
+ *  Create a mutex that can be used to provide mutually exclusive
+ *  read/write access to the globally accessible data structures
+ *  and variables that were defined above.
+ */
+static DECLARE_MUTEX(mutex);
+
+#define IF_NAME                    "adv7180"
+#define ADV7180_INPUT_CTL              0x00	/* Input Control */
+#define ADV7180_STATUS_1               0x10	/* Status #1 */
+#define ADV7180_BRIGHTNESS             0x0a	/* Brightness */
+#define ADV7180_IDENT                  0x11	/* IDENT */
+#define ADV7180_VSYNC_FIELD_CTL_1      0x31	/* VSYNC Field Control #1 */
+#define ADV7180_MANUAL_WIN_CTL         0x3d	/* Manual Window Control */
+#define ADV7180_SD_SATURATION_CB       0xe3	/* SD Saturation Cb */
+#define ADV7180_SD_SATURATION_CR       0xe4	/* SD Saturation Cr */
+#define ADV7180_PWR_MNG                0x0f     /* Power Management */
+
+/* supported controls */
+/* This hasn't been fully implemented yet.
+ * This is how it should work, though. */
+static struct v4l2_queryctrl adv7180_qctrl[] = {
+	{
+	.id = V4L2_CID_BRIGHTNESS,
+	.type = V4L2_CTRL_TYPE_INTEGER,
+	.name = "Brightness",
+	.minimum = 0,		/* check this value */
+	.maximum = 255,		/* check this value */
+	.step = 1,		/* check this value */
+	.default_value = 127,	/* check this value */
+	.flags = 0,
+	}, {
+	.id = V4L2_CID_SATURATION,
+	.type = V4L2_CTRL_TYPE_INTEGER,
+	.name = "Saturation",
+	.minimum = 0,		/* check this value */
+	.maximum = 255,		/* check this value */
+	.step = 0x1,		/* check this value */
+	.default_value = 127,	/* check this value */
+	.flags = 0,
+	}
+};
+
+/***********************************************************************
+ * I2C transfert.
+ ***********************************************************************/
+
+/*! Read one register from a ADV7180 i2c slave device.
+ *
+ *  @param *reg		register in the device we wish to access.
+ *
+ *  @return		       0 if success, an error code otherwise.
+ */
+static inline int adv7180_read(u8 reg)
+{
+	int val;
+	val = i2c_smbus_read_byte_data(adv7180_data.i2c_client, reg);
+	if (val < 0) {
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"%s:read reg error: reg=%2x \n", __func__, reg);
+		return -1;
+	}
+	return val;
+}
+
+/*! Write one register of a ADV7180 i2c slave device.
+ *
+ *  @param *reg		register in the device we wish to access.
+ *
+ *  @return		       0 if success, an error code otherwise.
+ */
+static int adv7180_write_reg(u8 reg, u8 val)
+{
+	if (i2c_smbus_write_byte_data(adv7180_data.i2c_client, reg, val) < 0) {
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"%s:write reg error:reg=%2x,val=%2x\n", __func__,
+			reg, val);
+		return -1;
+	}
+	return 0;
+}
+
+/***********************************************************************
+ * mxc_v4l2_capture interface.
+ ***********************************************************************/
+
+/*!
+ * Return attributes of current video standard.
+ * Since this device autodetects the current standard, this function also
+ * sets the values that need to be changed if the standard changes.
+ * There is no set std equivalent function.
+ *
+ *  @return		None.
+ */
+static void adv7180_get_std(v4l2_std_id *std)
+{
+	int tmp;
+	int idx;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_get_std\n");
+
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
+	/* Read the AD_RESULT to get the detect output video standard */
+	tmp = adv7180_read(ADV7180_STATUS_1) & 0x70;
+
+	down(&mutex);
+	if (tmp == 0x40) {
+		/* PAL */
+		*std = V4L2_STD_PAL;
+		idx = ADV7180_PAL;
+	} else if (tmp == 0) {
+		/*NTSC*/
+		*std = V4L2_STD_NTSC;
+		idx = ADV7180_NTSC;
+	} else {
+		*std = V4L2_STD_ALL;
+		idx = ADV7180_NOT_LOCKED;
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"Got invalid video standard! \n");
+	}
+	up(&mutex);
+
+	/* This assumes autodetect which this device uses. */
+	if (*std != adv7180_data.std_id) {
+		video_idx = idx;
+		adv7180_data.std_id = *std;
+		adv7180_data.pix.width = video_fmts[video_idx].raw_width;
+		adv7180_data.pix.height = video_fmts[video_idx].raw_height;
+	}
+}
+
+/***********************************************************************
+ * IOCTL Functions from v4l2_int_ioctl_desc.
+ ***********************************************************************/
+
+/*!
+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
+ * s: pointer to standard V4L2 device structure
+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
+ *
+ * Gets slave interface parameters.
+ * Calculates the required xclk value to support the requested
+ * clock parameters in p.  This value is returned in the p
+ * parameter.
+ *
+ * vidioc_int_g_ifparm returns platform-specific information about the
+ * interface settings used by the sensor.
+ *
+ * Called on open.
+ */
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ifparm\n");
+
+	if (s == NULL) {
+		pr_err("   ERROR!! no slave device set!\n");
+		return -1;
+	}
+
+	/* Initialize structure to 0s then set any non-0 values. */
+	memset(p, 0, sizeof(*p));
+	p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+	p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+	p->u.bt656.nobt_hs_inv = 1;
+
+	/* ADV7180 has a dedicated clock so no clock settings needed. */
+
+	return 0;
+}
+
+/*!
+ * Sets the camera power.
+ *
+ * s  pointer to the camera device
+ * on if 1, power is to be turned on.  0 means power is to be turned off
+ *
+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
+ * @s: pointer to standard V4L2 device structure
+ * @on: power state to which device is to be set
+ *
+ * Sets devices power state to requrested state, if possible.
+ * This is called on open, close, suspend and resume.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+	struct sensor *sensor = s->priv;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_power\n");
+
+	if (on && !sensor->on) {
+		gpio_sensor_active();
+
+		/* Make sure pwoer on */
+		if (tvin_plat->pwdn)
+			tvin_plat->pwdn(0);
+
+		if (adv7180_write_reg(ADV7180_PWR_MNG, 0) != 0)
+			return -EIO;
+	} else if (!on && sensor->on) {
+		if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0)
+			return -EIO;
+		gpio_sensor_inactive();
+	}
+
+	sensor->on = on;
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	struct sensor *sensor = s->priv;
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_parm\n");
+
+	switch (a->type) {
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		memset(a, 0, sizeof(*a));
+		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cparm->capability = sensor->streamcap.capability;
+		cparm->timeperframe = sensor->streamcap.timeperframe;
+		cparm->capturemode = sensor->streamcap.capturemode;
+		break;
+
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		break;
+
+	default:
+		pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible.  If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ *
+ * This driver cannot change these settings.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_parm\n");
+
+	switch (a->type) {
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		break;
+
+	default:
+		pr_debug("   type is unknown - %d\n", a->type);
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	struct sensor *sensor = s->priv;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_fmt_cap\n");
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   Returning size of %dx%d\n",
+			 sensor->pix.width, sensor->pix.height);
+		f->fmt.pix = sensor->pix;
+		break;
+
+	case V4L2_BUF_TYPE_PRIVATE: {
+		v4l2_std_id std;
+		adv7180_get_std(&std);
+		f->fmt.pix.pixelformat = (u32)std;
+		}
+		break;
+
+	default:
+		f->fmt.pix = sensor->pix;
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control information
+ * from the video_control[] array.  Otherwise, returns -EINVAL if the
+ * control is not supported.
+ */
+static int ioctl_queryctrl(struct v4l2_int_device *s,
+			   struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_queryctrl\n");
+
+	for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++)
+		if (qc->id && qc->id == adv7180_qctrl[i].id) {
+			memcpy(qc, &(adv7180_qctrl[i]),
+				sizeof(*qc));
+			return (0);
+		}
+
+	return -EINVAL;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array.  Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int ret = 0;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n");
+
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_BRIGHTNESS\n");
+		adv7180_data.brightness = adv7180_read(ADV7180_BRIGHTNESS);
+		vc->value = adv7180_data.brightness;
+		break;
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_CONTRAST\n");
+		vc->value = adv7180_data.contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_SATURATION\n");
+		adv7180_data.saturation = adv7180_read(ADV7180_SD_SATURATION_CB);
+		vc->value = adv7180_data.saturation;
+		break;
+	case V4L2_CID_HUE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_HUE\n");
+		vc->value = adv7180_data.hue;
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_DO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_RED_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_RED_BALANCE\n");
+		vc->value = adv7180_data.red;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_BLUE_BALANCE\n");
+		vc->value = adv7180_data.blue;
+		break;
+	case V4L2_CID_GAMMA:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_GAMMA\n");
+		break;
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_EXPOSURE\n");
+		vc->value = adv7180_data.ae_mode;
+		break;
+	case V4L2_CID_AUTOGAIN:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_AUTOGAIN\n");
+		break;
+	case V4L2_CID_GAIN:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_GAIN\n");
+		break;
+	case V4L2_CID_HFLIP:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_HFLIP\n");
+		break;
+	case V4L2_CID_VFLIP:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_VFLIP\n");
+		break;
+	default:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   Default case\n");
+		vc->value = 0;
+		ret = -EPERM;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array).  Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int retval = 0;
+	u8 tmp;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n");
+
+	/* Make sure power on */
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_BRIGHTNESS\n");
+		tmp = vc->value;
+		adv7180_write_reg(ADV7180_BRIGHTNESS, tmp);
+		adv7180_data.brightness = vc->value;
+		break;
+	case V4L2_CID_CONTRAST:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_CONTRAST\n");
+		break;
+	case V4L2_CID_SATURATION:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_SATURATION\n");
+		tmp = vc->value;
+		adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp);
+		adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp);
+		adv7180_data.saturation = vc->value;
+		break;
+	case V4L2_CID_HUE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_HUE\n");
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_DO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_RED_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_RED_BALANCE\n");
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_BLUE_BALANCE\n");
+		break;
+	case V4L2_CID_GAMMA:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_GAMMA\n");
+		break;
+	case V4L2_CID_EXPOSURE:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_EXPOSURE\n");
+		break;
+	case V4L2_CID_AUTOGAIN:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_AUTOGAIN\n");
+		break;
+	case V4L2_CID_GAIN:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_GAIN\n");
+		break;
+	case V4L2_CID_HFLIP:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_HFLIP\n");
+		break;
+	case V4L2_CID_VFLIP:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   V4L2_CID_VFLIP\n");
+		break;
+	default:
+		dev_dbg(&adv7180_data.i2c_client->dev,
+			"   Default case\n");
+		retval = -EPERM;
+		break;
+	}
+
+	return retval;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_init\n");
+	return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_dev_init\n");
+	return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module.
+ */
+static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = {
+
+	{vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init},
+
+	/*!
+	 * Delinitialise the dev. at slave detach.
+	 * The complement of ioctl_dev_init.
+	 */
+/*	{vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */
+
+	{vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power},
+	{vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm},
+/*	{vidioc_int_g_needs_reset_num,
+				(v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
+/*	{vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
+	{vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init},
+
+	/*!
+	 * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
+	 */
+/*	{vidioc_int_enum_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
+
+	/*!
+	 * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
+	 * This ioctl is used to negotiate the image capture size and
+	 * pixel format without actually making it take effect.
+	 */
+/*	{vidioc_int_try_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
+
+	{vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap},
+
+	/*!
+	 * If the requested format is supported, configures the HW to use that
+	 * format, returns error code if format not supported or HW can't be
+	 * correctly configured.
+	 */
+/*	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+
+	{vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm},
+	{vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm},
+	{vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl},
+	{vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl},
+	{vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl},
+};
+
+static struct v4l2_int_slave adv7180_slave = {
+	.ioctls = adv7180_ioctl_desc,
+	.num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc),
+};
+
+static struct v4l2_int_device adv7180_int_device = {
+	.module = THIS_MODULE,
+	.name = "adv7180",
+	.type = v4l2_int_type_slave,
+	.u = {
+		.slave = &adv7180_slave,
+	},
+};
+
+
+/***********************************************************************
+ * I2C client and driver.
+ ***********************************************************************/
+
+/*! ADV7180 Reset function.
+ *
+ *  @return		None.
+ */
+static void adv7180_hard_reset(void)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev,
+		"In adv7180:adv7180_hard_reset\n");
+
+	/*! Driver works fine without explicit register
+	 * initialization. Furthermore, initializations takes about 2 seconds
+	 * at startup...
+	 */
+
+	/*! Set YPbPr input on AIN1,4,5 and normal
+	 * operations(autodection of all stds).
+	 */
+	adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
+
+	/*! Datasheet recommends: */
+	adv7180_write_reg(ADV7180_VSYNC_FIELD_CTL_1, 0x02);
+	adv7180_write_reg(ADV7180_MANUAL_WIN_CTL, 0xa2);
+}
+
+/*! ADV7180 I2C attach function.
+ *
+ *  @param *adapter	struct i2c_adapter *.
+ *
+ *  @return		Error code indicating success or failure.
+ */
+
+/*!
+ * ADV7180 I2C probe function.
+ * Function set in i2c_driver struct.
+ * Called by insmod.
+ *
+ *  @param *adapter	I2C adapter descriptor.
+ *
+ *  @return		Error code indicating success or failure.
+ */
+static int adv7180_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	int rev_id;
+	int ret = 0;
+	tvin_plat = client->dev.platform_data;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_probe\n");
+
+	if (tvin_plat->dvddio_reg) {
+		dvddio_regulator =
+		    regulator_get(&client->dev, tvin_plat->dvddio_reg);
+		if (!IS_ERR_VALUE((unsigned long)dvddio_regulator)) {
+			regulator_set_voltage(dvddio_regulator, 3300000, 3300000);
+			if (regulator_enable(dvddio_regulator) != 0)
+				return -ENODEV;
+		}
+	}
+
+	if (tvin_plat->dvdd_reg) {
+		dvdd_regulator =
+		    regulator_get(&client->dev, tvin_plat->dvdd_reg);
+		if (!IS_ERR_VALUE((unsigned long)dvdd_regulator)) {
+			regulator_set_voltage(dvdd_regulator, 1800000, 1800000);
+			if (regulator_enable(dvdd_regulator) != 0)
+				return -ENODEV;
+		}
+	}
+
+	if (tvin_plat->avdd_reg) {
+		avdd_regulator =
+		    regulator_get(&client->dev, tvin_plat->avdd_reg);
+		if (!IS_ERR_VALUE((unsigned long)avdd_regulator)) {
+			regulator_set_voltage(avdd_regulator, 1800000, 1800000);
+			if (regulator_enable(avdd_regulator) != 0)
+				return -ENODEV;
+		}
+	}
+
+	if (tvin_plat->pvdd_reg) {
+		pvdd_regulator =
+		    regulator_get(&client->dev, tvin_plat->pvdd_reg);
+		if (!IS_ERR_VALUE((unsigned long)pvdd_regulator)) {
+			regulator_set_voltage(pvdd_regulator, 1800000, 1800000);
+			if (regulator_enable(pvdd_regulator) != 0)
+				return -ENODEV;
+		}
+	}
+
+
+	if (tvin_plat->reset)
+		tvin_plat->reset();
+
+	if (tvin_plat->pwdn)
+		tvin_plat->pwdn(0);
+
+	msleep(1);
+
+	/* Set initial values for the sensor struct. */
+	memset(&adv7180_data, 0, sizeof(adv7180_data));
+	adv7180_data.i2c_client = client;
+	adv7180_data.streamcap.timeperframe.denominator = 30;
+	adv7180_data.streamcap.timeperframe.numerator = 1;
+	adv7180_data.std_id = V4L2_STD_ALL;
+	video_idx = ADV7180_NOT_LOCKED;
+	adv7180_data.pix.width = video_fmts[video_idx].raw_width;
+	adv7180_data.pix.height = video_fmts[video_idx].raw_height;
+	adv7180_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;  /* YUV422 */
+	adv7180_data.pix.priv = 1;  /* 1 is used to indicate TV in */
+	adv7180_data.on = true;
+
+	gpio_sensor_active();
+
+	dev_dbg(&adv7180_data.i2c_client->dev,
+		"%s:adv7180 probe i2c address is 0x%02X \n",
+		__func__, adv7180_data.i2c_client->addr);
+
+	/*! Read the revision ID of the tvin chip */
+	rev_id = adv7180_read(ADV7180_IDENT);
+	dev_dbg(&adv7180_data.i2c_client->dev,
+		"%s:Analog Device adv7%2X0 detected! \n", __func__,
+		rev_id);
+
+	/*! ADV7180 initialization. */
+	adv7180_hard_reset();
+
+	pr_debug("   type is %d (expect %d)\n",
+		 adv7180_int_device.type, v4l2_int_type_slave);
+	pr_debug("   num ioctls is %d\n",
+		 adv7180_int_device.u.slave->num_ioctls);
+
+	/* This function attaches this structure to the /dev/video0 device.
+	 * The pointer in priv points to the mt9v111_data structure here.*/
+	adv7180_int_device.priv = &adv7180_data;
+	ret = v4l2_int_device_register(&adv7180_int_device);
+
+	return ret;
+}
+
+/*!
+ * ADV7180 I2C detach function.
+ * Called on rmmod.
+ *
+ *  @param *client	struct i2c_client*.
+ *
+ *  @return		Error code indicating success or failure.
+ */
+static int adv7180_detach(struct i2c_client *client)
+{
+	struct mxc_tvin_platform_data *plat_data = client->dev.platform_data;
+
+	dev_dbg(&adv7180_data.i2c_client->dev,
+		"%s:Removing %s video decoder @ 0x%02X from adapter %s \n",
+		__func__, IF_NAME, client->addr << 1, client->adapter->name);
+
+	if (plat_data->pwdn)
+		plat_data->pwdn(1);
+
+	if (dvddio_regulator) {
+		regulator_disable(dvddio_regulator);
+		regulator_put(dvddio_regulator);
+	}
+
+	if (dvdd_regulator) {
+		regulator_disable(dvdd_regulator);
+		regulator_put(dvdd_regulator);
+	}
+
+	if (avdd_regulator) {
+		regulator_disable(avdd_regulator);
+		regulator_put(avdd_regulator);
+	}
+
+	if (pvdd_regulator) {
+		regulator_disable(pvdd_regulator);
+		regulator_put(pvdd_regulator);
+	}
+
+	v4l2_int_device_unregister(&adv7180_int_device);
+
+	return 0;
+}
+
+/*!
+ * ADV7180 init function.
+ * Called on insmod.
+ *
+ * @return    Error code indicating success or failure.
+ */
+static __init int adv7180_init(void)
+{
+	u8 err = 0;
+
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_init\n");
+
+	/* Tells the i2c driver what functions to call for this driver. */
+	err = i2c_add_driver(&adv7180_i2c_driver);
+	if (err != 0)
+		pr_err("%s:driver registration failed, error=%d \n",
+			__func__, err);
+
+	return err;
+}
+
+/*!
+ * ADV7180 cleanup function.
+ * Called on rmmod.
+ *
+ * @return   Error code indicating success or failure.
+ */
+static void __exit adv7180_clean(void)
+{
+	dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_clean\n");
+	i2c_del_driver(&adv7180_i2c_driver);
+	gpio_sensor_inactive();
+}
+
+module_init(adv7180_init);
+module_exit(adv7180_clean);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/csi_v4l2_capture.c b/drivers/media/video/mxc/capture/csi_v4l2_capture.c
new file mode 100644
index 000000000000..cf224e0673f0
--- /dev/null
+++ b/drivers/media/video/mxc/capture/csi_v4l2_capture.c
@@ -0,0 +1,1466 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/media/video/mxc/capture/csi_v4l2_capture.c
+ * This file is derived from mxc_v4l2_capture.c
+ *
+ * @brief MX25 Video For Linux 2 driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <linux/semaphore.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-int-device.h>
+#include <linux/mxcfb.h>
+#include "mxc_v4l2_capture.h"
+#include "fsl_csi.h"
+
+static int video_nr = -1;
+static cam_data *g_cam;
+
+static int csi_v4l2_master_attach(struct v4l2_int_device *slave);
+static void csi_v4l2_master_detach(struct v4l2_int_device *slave);
+static u8 camera_power(cam_data *cam, bool cameraOn);
+
+/*! Information about this driver. */
+static struct v4l2_int_master csi_v4l2_master = {
+	.attach = csi_v4l2_master_attach,
+	.detach = csi_v4l2_master_detach,
+};
+
+static struct v4l2_int_device csi_v4l2_int_device = {
+	.module = THIS_MODULE,
+	.name = "csi_v4l2_cap",
+	.type = v4l2_int_type_master,
+	.u = {
+	      .master = &csi_v4l2_master,
+	      },
+};
+
+/*!
+ * Camera V4l2 callback function.
+ *
+ * @param mask 	   u32
+ * @param dev      void device structure
+ *
+ * @return none
+ */
+static void camera_callback(u32 mask, void *dev)
+{
+	struct mxc_v4l_frame *done_frame;
+	struct mxc_v4l_frame *ready_frame;
+	cam_data *cam;
+
+	cam = (cam_data *) dev;
+	if (cam == NULL)
+		return;
+
+	if (list_empty(&cam->working_q)) {
+		pr_err("ERROR: v4l2 capture: %s: "
+				"working queue empty\n", __func__);
+		return;
+	}
+
+	done_frame =
+		list_entry(cam->working_q.next, struct mxc_v4l_frame, queue);
+	if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+		done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
+		done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+		if (list_empty(&cam->ready_q)) {
+			cam->skip_frame++;
+		} else {
+			ready_frame = list_entry(cam->ready_q.next,
+						 struct mxc_v4l_frame, queue);
+			list_del(cam->ready_q.next);
+			list_add_tail(&ready_frame->queue, &cam->working_q);
+
+			if (cam->ping_pong_csi == 1) {
+				__raw_writel(cam->frame[ready_frame->index].
+					     paddress, CSI_CSIDMASA_FB1);
+			} else {
+				__raw_writel(cam->frame[ready_frame->index].
+					     paddress, CSI_CSIDMASA_FB2);
+			}
+		}
+
+		/* Added to the done queue */
+		list_del(cam->working_q.next);
+		list_add_tail(&done_frame->queue, &cam->done_q);
+		cam->enc_counter++;
+		wake_up_interruptible(&cam->enc_queue);
+	} else {
+		pr_err("ERROR: v4l2 capture: %s: "
+				"buffer not queued\n", __func__);
+	}
+
+	return;
+}
+
+/*!
+ * Make csi ready for capture image.
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status 0 success
+ */
+static int csi_cap_image(cam_data *cam)
+{
+	unsigned int value;
+
+	value = __raw_readl(CSI_CSICR3);
+	__raw_writel(value | BIT_DMA_REFLASH_RFF | BIT_FRMCNT_RST, CSI_CSICR3);
+	value = __raw_readl(CSI_CSISR);
+	__raw_writel(value, CSI_CSISR);
+
+	return 0;
+}
+
+/***************************************************************************
+ * Functions for handling Frame buffers.
+ **************************************************************************/
+
+/*!
+ * Free frame buffers
+ *
+ * @param cam      Structure cam_data *
+ *
+ * @return status  0 success.
+ */
+static int csi_free_frame_buf(cam_data *cam)
+{
+	int i;
+
+	pr_debug("MVC: In %s\n", __func__);
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		if (cam->frame[i].vaddress != 0) {
+			dma_free_coherent(0, cam->frame[i].buffer.length,
+					     cam->frame[i].vaddress,
+					     cam->frame[i].paddress);
+			cam->frame[i].vaddress = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * Allocate frame buffers
+ *
+ * @param cam      Structure cam_data *
+ * @param count    int number of buffer need to allocated
+ *
+ * @return status  -0 Successfully allocated a buffer, -ENOBUFS	failed.
+ */
+static int csi_allocate_frame_buf(cam_data *cam, int count)
+{
+	int i;
+
+	pr_debug("In MVC:%s- size=%d\n",
+		 __func__, cam->v2f.fmt.pix.sizeimage);
+	for (i = 0; i < count; i++) {
+		cam->frame[i].vaddress = dma_alloc_coherent(0, PAGE_ALIGN
+							       (cam->v2f.fmt.
+							       pix.sizeimage),
+							       &cam->frame[i].
+							       paddress,
+							       GFP_DMA |
+							       GFP_KERNEL);
+		if (cam->frame[i].vaddress == 0) {
+			pr_err("ERROR: v4l2 capture: "
+			       "%s failed.\n", __func__);
+			csi_free_frame_buf(cam);
+			return -ENOBUFS;
+		}
+		cam->frame[i].buffer.index = i;
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+		cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cam->frame[i].buffer.length = PAGE_ALIGN(cam->v2f.fmt.
+							 pix.sizeimage);
+		cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
+		cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
+		cam->frame[i].index = i;
+	}
+
+	return 0;
+}
+
+/*!
+ * Free frame buffers status
+ *
+ * @param cam    Structure cam_data *
+ *
+ * @return none
+ */
+static void csi_free_frames(cam_data *cam)
+{
+	int i;
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	for (i = 0; i < FRAME_NUM; i++)
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+
+	cam->skip_frame = 0;
+	INIT_LIST_HEAD(&cam->ready_q);
+	INIT_LIST_HEAD(&cam->working_q);
+	INIT_LIST_HEAD(&cam->done_q);
+
+	return;
+}
+
+/*!
+ * Return the buffer status
+ *
+ * @param cam 	   Structure cam_data *
+ * @param buf      Structure v4l2_buffer *
+ *
+ * @return status  0 success, EINVAL failed.
+ */
+static int csi_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
+{
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (buf->index < 0 || buf->index >= FRAME_NUM) {
+		pr_err("ERROR: v4l2 capture: %s buffers "
+				"not allocated\n", __func__);
+		return -EINVAL;
+	}
+
+	memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
+
+	return 0;
+}
+
+/*!
+ * Indicates whether the palette is supported.
+ *
+ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_UYVY or V4L2_PIX_FMT_YUV420
+ *
+ * @return 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	return (palette == V4L2_PIX_FMT_RGB565) ||
+	    (palette == V4L2_PIX_FMT_UYVY) || (palette == V4L2_PIX_FMT_YUV420);
+}
+
+/*!
+ * Start stream I/O
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int csi_streamon(cam_data *cam)
+{
+	struct mxc_v4l_frame *frame;
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (NULL == cam) {
+		pr_err("ERROR: v4l2 capture: %s cam parameter is NULL\n",
+				__func__);
+		return -1;
+	}
+
+	/* move the frame from readyq to workingq */
+	if (list_empty(&cam->ready_q)) {
+		pr_err("ERROR: v4l2 capture: %s: "
+				"ready_q queue empty\n", __func__);
+		return -1;
+	}
+	frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+	list_del(cam->ready_q.next);
+	list_add_tail(&frame->queue, &cam->working_q);
+	__raw_writel(cam->frame[frame->index].paddress, CSI_CSIDMASA_FB1);
+
+	if (list_empty(&cam->ready_q)) {
+		pr_err("ERROR: v4l2 capture: %s: "
+				"ready_q queue empty\n", __func__);
+		return -1;
+	}
+	frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+	list_del(cam->ready_q.next);
+	list_add_tail(&frame->queue, &cam->working_q);
+	__raw_writel(cam->frame[frame->index].paddress, CSI_CSIDMASA_FB2);
+
+	cam->capture_pid = current->pid;
+	cam->capture_on = true;
+	csi_cap_image(cam);
+	csi_enable_int(1);
+
+	return 0;
+}
+
+/*!
+ * Stop stream I/O
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int csi_streamoff(cam_data *cam)
+{
+	unsigned int cr3;
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (cam->capture_on == false)
+		return 0;
+
+	csi_disable_int();
+	cam->capture_on = false;
+
+	/* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
+	__raw_writel(0, CSI_CSIDMASA_FB1);
+	__raw_writel(0, CSI_CSIDMASA_FB2);
+	cr3 = __raw_readl(CSI_CSICR3);
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+
+	csi_free_frames(cam);
+	csi_free_frame_buf(cam);
+
+	return 0;
+}
+
+/*!
+ * start the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int start_preview(cam_data *cam)
+{
+	unsigned long fb_addr = (unsigned long)cam->v4l2_fb.base;
+
+	__raw_writel(fb_addr, CSI_CSIDMASA_FB1);
+	__raw_writel(fb_addr, CSI_CSIDMASA_FB2);
+	__raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+
+	csi_enable_int(0);
+
+	return 0;
+}
+
+/*!
+ * shut down the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int stop_preview(cam_data *cam)
+{
+	csi_disable_int();
+
+	/* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
+	__raw_writel(0, CSI_CSIDMASA_FB1);
+	__raw_writel(0, CSI_CSIDMASA_FB2);
+	__raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+
+	return 0;
+}
+
+/***************************************************************************
+ * VIDIOC Functions.
+ **************************************************************************/
+
+/*!
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int csi_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		f->fmt.pix = cam->v2f.fmt.pix;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
+		f->fmt.win = cam->win;
+		break;
+	default:
+		pr_debug("   type is invalid\n");
+		retval = -EINVAL;
+	}
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+
+	return retval;
+}
+
+/*!
+ * V4L2 - csi_v4l2_s_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int csi_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+	int size = 0;
+	int bytesperline = 0;
+	int *width, *height;
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		if (!valid_mode(f->fmt.pix.pixelformat)) {
+			pr_err("ERROR: v4l2 capture: %s: format "
+			       "not supported\n", __func__);
+			return -EINVAL;
+		}
+
+		/* Handle case where size requested is larger than cuurent
+		 * camera setting. */
+		if ((f->fmt.pix.width > cam->crop_bounds.width)
+		    || (f->fmt.pix.height > cam->crop_bounds.height)) {
+			/* Need the logic here, calling vidioc_s_param if
+			 * camera can change. */
+			pr_debug("csi_v4l2_s_fmt size changed\n");
+		}
+		if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+			height = &f->fmt.pix.width;
+			width = &f->fmt.pix.height;
+		} else {
+			width = &f->fmt.pix.width;
+			height = &f->fmt.pix.height;
+		}
+
+		if ((cam->crop_bounds.width / *width > 8) ||
+		    ((cam->crop_bounds.width / *width == 8) &&
+		     (cam->crop_bounds.width % *width))) {
+			*width = cam->crop_bounds.width / 8;
+			if (*width % 8)
+				*width += 8 - *width % 8;
+			pr_err("ERROR: v4l2 capture: width exceeds limit "
+			       "resize to %d.\n", *width);
+		}
+
+		if ((cam->crop_bounds.height / *height > 8) ||
+		    ((cam->crop_bounds.height / *height == 8) &&
+		     (cam->crop_bounds.height % *height))) {
+			*height = cam->crop_bounds.height / 8;
+			if (*height % 8)
+				*height += 8 - *height % 8;
+			pr_err("ERROR: v4l2 capture: height exceeds limit "
+			       "resize to %d.\n", *height);
+		}
+
+		switch (f->fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_RGB565:
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			csi_set_16bit_imagpara(f->fmt.pix.width,
+					       f->fmt.pix.height);
+			bytesperline = f->fmt.pix.width * 2;
+			break;
+		case V4L2_PIX_FMT_UYVY:
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			csi_set_16bit_imagpara(f->fmt.pix.width,
+					       f->fmt.pix.height);
+			bytesperline = f->fmt.pix.width * 2;
+			break;
+		case V4L2_PIX_FMT_YUV420:
+			size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
+			csi_set_12bit_imagpara(f->fmt.pix.width,
+					       f->fmt.pix.height);
+			bytesperline = f->fmt.pix.width;
+			break;
+		case V4L2_PIX_FMT_YUV422P:
+		case V4L2_PIX_FMT_RGB24:
+		case V4L2_PIX_FMT_BGR24:
+		case V4L2_PIX_FMT_BGR32:
+		case V4L2_PIX_FMT_RGB32:
+		case V4L2_PIX_FMT_NV12:
+		default:
+			pr_debug("   case not supported\n");
+			break;
+		}
+
+		if (f->fmt.pix.bytesperline < bytesperline)
+			f->fmt.pix.bytesperline = bytesperline;
+		else
+			bytesperline = f->fmt.pix.bytesperline;
+
+		if (f->fmt.pix.sizeimage < size)
+			f->fmt.pix.sizeimage = size;
+		else
+			size = f->fmt.pix.sizeimage;
+
+		cam->v2f.fmt.pix = f->fmt.pix;
+
+		if (cam->v2f.fmt.pix.priv != 0) {
+			if (copy_from_user(&cam->offset,
+					   (void *)cam->v2f.fmt.pix.priv,
+					   sizeof(cam->offset))) {
+				retval = -EFAULT;
+				break;
+			}
+		}
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		pr_debug("   type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
+		cam->win = f->fmt.win;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+
+	return retval;
+}
+
+/*!
+ * V4L2 - csi_v4l2_s_param function
+ * Allows setting of capturemode and frame rate.
+ *
+ * @param cam         structure cam_data *
+ * @param parm        structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int csi_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
+{
+	struct v4l2_ifparm ifparm;
+	struct v4l2_format cam_fmt;
+	struct v4l2_streamparm currentparm;
+	int err = 0;
+
+	pr_debug("In %s\n", __func__);
+
+	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		pr_err(KERN_ERR "%s invalid type\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Stop the viewfinder */
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+
+	currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	/* First check that this device can support the changes requested. */
+	err = vidioc_int_g_parm(cam->sensor, &currentparm);
+	if (err) {
+		pr_err("%s: vidioc_int_g_parm returned an error %d\n",
+		       __func__, err);
+		goto exit;
+	}
+
+	pr_debug("   Current capabilities are %x\n",
+		 currentparm.parm.capture.capability);
+	pr_debug("   Current capturemode is %d  change to %d\n",
+		 currentparm.parm.capture.capturemode,
+		 parm->parm.capture.capturemode);
+	pr_debug("   Current framerate is %d  change to %d\n",
+		 currentparm.parm.capture.timeperframe.denominator,
+		 parm->parm.capture.timeperframe.denominator);
+
+	err = vidioc_int_s_parm(cam->sensor, parm);
+	if (err) {
+		pr_err("%s: vidioc_int_s_parm returned an error %d\n",
+		       __func__, err);
+		goto exit;
+	}
+
+	vidioc_int_g_ifparm(cam->sensor, &ifparm);
+	cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	pr_debug("   g_fmt_cap returns widthxheight of input as %d x %d\n",
+		 cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
+
+exit:
+	return err;
+}
+
+/*!
+ * Dequeue one V4L capture buffer
+ *
+ * @param cam         structure cam_data *
+ * @param buf         structure v4l2_buffer *
+ *
+ * @return  status    0 success, EINVAL invalid frame number
+ *                    ETIME timeout, ERESTARTSYS interrupted by user
+ */
+static int csi_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
+{
+	int retval = 0;
+	struct mxc_v4l_frame *frame;
+	unsigned long lock_flags;
+
+	if (!wait_event_interruptible_timeout(cam->enc_queue,
+				cam->enc_counter != 0, 10 * HZ)) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout "
+			"enc_counter %x\n", cam->enc_counter);
+		return -ETIME;
+	} else if (signal_pending(current)) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() "
+				"interrupt received\n");
+		return -ERESTARTSYS;
+	}
+
+	spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
+
+	cam->enc_counter--;
+
+	frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
+	list_del(cam->done_q.next);
+
+	if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
+	} else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+		pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
+			"Buffer not filled.\n");
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+		retval = -EINVAL;
+	} else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
+		pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
+			"Buffer not queued.\n");
+		retval = -EINVAL;
+	}
+
+	spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
+
+	buf->bytesused = cam->v2f.fmt.pix.sizeimage;
+	buf->index = frame->index;
+	buf->flags = frame->buffer.flags;
+	buf->m = cam->frame[frame->index].buffer.m;
+
+	return retval;
+}
+
+/*!
+ * V4L interface - open function
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int csi_v4l_open(struct file *file)
+{
+	struct v4l2_ifparm ifparm;
+	struct v4l2_format cam_fmt;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int err = 0;
+
+	pr_debug("   device name is %s\n", dev->name);
+
+	if (!cam) {
+		pr_err("ERROR: v4l2 capture: Internal error, "
+		       "cam_data not found!\n");
+		return -EBADF;
+	}
+
+	down(&cam->busy_lock);
+	err = 0;
+	if (signal_pending(current))
+		goto oops;
+
+	if (cam->open_count++ == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+
+		cam->enc_counter = 0;
+		cam->skip_frame = 0;
+		INIT_LIST_HEAD(&cam->ready_q);
+		INIT_LIST_HEAD(&cam->working_q);
+		INIT_LIST_HEAD(&cam->done_q);
+
+		vidioc_int_g_ifparm(cam->sensor, &ifparm);
+
+		cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		csi_enable_mclk(CSI_MCLK_I2C, true, true);
+		vidioc_int_init(cam->sensor);
+	}
+
+	file->private_data = dev;
+
+oops:
+	up(&cam->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L interface - close function
+ *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int csi_v4l_close(struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	int err = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	pr_debug("In MVC:%s\n", __func__);
+
+	if (!cam) {
+		pr_err("ERROR: v4l2 capture: Internal error, "
+		       "cam_data not found!\n");
+		return -EBADF;
+	}
+
+	/* for the case somebody hit the ctrl C */
+	if (cam->overlay_pid == current->pid) {
+		err = stop_preview(cam);
+		cam->overlay_on = false;
+	}
+
+	if (--cam->open_count == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+		file->private_data = NULL;
+		csi_enable_mclk(CSI_MCLK_I2C, false, false);
+	}
+
+	return err;
+}
+
+/*
+ * V4L interface - read function
+ *
+ * @param file       struct file *
+ * @param read buf   char *
+ * @param count      size_t
+ * @param ppos       structure loff_t *
+ *
+ * @return           bytes read
+ */
+static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count,
+			    loff_t *ppos)
+{
+	int err = 0;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	/* Stop the viewfinder */
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+
+	if (cam->still_buf_vaddr == NULL) {
+		cam->still_buf_vaddr = dma_alloc_coherent(0,
+							  PAGE_ALIGN
+							  (cam->v2f.fmt.
+							   pix.sizeimage),
+							  &cam->
+							  still_buf[0],
+							  GFP_DMA | GFP_KERNEL);
+		if (cam->still_buf_vaddr == NULL) {
+			pr_err("alloc dma memory failed\n");
+			return -ENOMEM;
+		}
+		cam->still_counter = 0;
+		__raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB2);
+		__raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB1);
+		__raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF,
+			     CSI_CSICR3);
+		__raw_writel(__raw_readl(CSI_CSISR), CSI_CSISR);
+		__raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST,
+			     CSI_CSICR3);
+		csi_enable_int(1);
+	}
+
+	wait_event_interruptible(cam->still_queue, cam->still_counter);
+	csi_disable_int();
+	err = copy_to_user(buf, cam->still_buf_vaddr,
+			   cam->v2f.fmt.pix.sizeimage);
+
+	if (cam->still_buf_vaddr != NULL) {
+		dma_free_coherent(0, PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				  cam->still_buf_vaddr, cam->still_buf[0]);
+		cam->still_buf[0] = 0;
+		cam->still_buf_vaddr = NULL;
+	}
+
+	if (cam->overlay_on == true)
+		start_preview(cam);
+
+	up(&cam->busy_lock);
+	if (err < 0)
+		return err;
+
+	return cam->v2f.fmt.pix.sizeimage - err;
+}
+
+/*!
+ * V4L interface - ioctl function
+ *
+ * @param file       struct file*
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void*
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static long csi_v4l_do_ioctl(struct file *file,
+			    unsigned int ioctlnr, void *arg)
+{
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int retval = 0;
+	unsigned long lock_flags;
+
+	pr_debug("In MVC: %s, %x\n", __func__, ioctlnr);
+	wait_event_interruptible(cam->power_queue, cam->low_power == false);
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+		/*!
+		 * V4l2 VIDIOC_G_FMT ioctl
+		 */
+	case VIDIOC_G_FMT:{
+			struct v4l2_format *gf = arg;
+			pr_debug("   case VIDIOC_G_FMT\n");
+			retval = csi_v4l2_g_fmt(cam, gf);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_FMT ioctl
+		 */
+	case VIDIOC_S_FMT:{
+			struct v4l2_format *sf = arg;
+			pr_debug("   case VIDIOC_S_FMT\n");
+			retval = csi_v4l2_s_fmt(cam, sf);
+			vidioc_int_s_fmt_cap(cam->sensor, sf);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_OVERLAY ioctl
+		 */
+	case VIDIOC_OVERLAY:{
+			int *on = arg;
+			pr_debug("   case VIDIOC_OVERLAY\n");
+			if (*on) {
+				cam->overlay_on = true;
+				cam->overlay_pid = current->pid;
+				start_preview(cam);
+			}
+			if (!*on) {
+				stop_preview(cam);
+				cam->overlay_on = false;
+			}
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_G_FBUF ioctl
+		 */
+	case VIDIOC_G_FBUF:{
+			struct v4l2_framebuffer *fb = arg;
+			*fb = cam->v4l2_fb;
+			fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_FBUF ioctl
+		 */
+	case VIDIOC_S_FBUF:{
+			struct v4l2_framebuffer *fb = arg;
+			cam->v4l2_fb = *fb;
+			break;
+		}
+
+	case VIDIOC_G_PARM:{
+			struct v4l2_streamparm *parm = arg;
+			pr_debug("   case VIDIOC_G_PARM\n");
+			vidioc_int_g_parm(cam->sensor, parm);
+			break;
+		}
+
+	case VIDIOC_S_PARM:{
+			struct v4l2_streamparm *parm = arg;
+			pr_debug("   case VIDIOC_S_PARM\n");
+			retval = csi_v4l2_s_param(cam, parm);
+			break;
+		}
+
+	case VIDIOC_QUERYCAP:{
+			struct v4l2_capability *cap = arg;
+			pr_debug("   case VIDIOC_QUERYCAP\n");
+			strcpy(cap->driver, "csi_v4l2");
+			cap->version = KERNEL_VERSION(0, 1, 11);
+			cap->capabilities = V4L2_CAP_VIDEO_OVERLAY |
+			    V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_READWRITE;
+			cap->card[0] = '\0';
+			cap->bus_info[0] = '\0';
+			break;
+		}
+
+	case VIDIOC_S_CROP:
+		pr_debug("   case not supported\n");
+		break;
+
+	case VIDIOC_REQBUFS: {
+		struct v4l2_requestbuffers *req = arg;
+		pr_debug("   case VIDIOC_REQBUFS\n");
+
+		if (req->count > FRAME_NUM) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
+					"not enough buffers\n");
+			req->count = FRAME_NUM;
+		}
+
+		if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
+				(req->memory != V4L2_MEMORY_MMAP)) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
+					"wrong buffer type\n");
+			retval = -EINVAL;
+			break;
+		}
+
+		csi_streamoff(cam);
+		csi_free_frame_buf(cam);
+		cam->skip_frame = 0;
+		INIT_LIST_HEAD(&cam->ready_q);
+		INIT_LIST_HEAD(&cam->working_q);
+		INIT_LIST_HEAD(&cam->done_q);
+		retval = csi_allocate_frame_buf(cam, req->count);
+		break;
+	}
+
+	case VIDIOC_QUERYBUF: {
+		struct v4l2_buffer *buf = arg;
+		int index = buf->index;
+		pr_debug("   case VIDIOC_QUERYBUF\n");
+
+		if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+			retval = -EINVAL;
+			break;
+		}
+
+		memset(buf, 0, sizeof(buf));
+		buf->index = index;
+		retval = csi_v4l2_buffer_status(cam, buf);
+		break;
+	}
+
+	case VIDIOC_QBUF: {
+		struct v4l2_buffer *buf = arg;
+		int index = buf->index;
+		pr_debug("   case VIDIOC_QBUF\n");
+
+		spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
+		cam->frame[index].buffer.m.offset = buf->m.offset;
+		if ((cam->frame[index].buffer.flags & 0x7) ==
+				V4L2_BUF_FLAG_MAPPED) {
+			cam->frame[index].buffer.flags |= V4L2_BUF_FLAG_QUEUED;
+			if (cam->skip_frame > 0) {
+				list_add_tail(&cam->frame[index].queue,
+					      &cam->working_q);
+				cam->skip_frame = 0;
+
+				if (cam->ping_pong_csi == 1) {
+					__raw_writel(cam->frame[index].paddress,
+						     CSI_CSIDMASA_FB1);
+				} else {
+					__raw_writel(cam->frame[index].paddress,
+						     CSI_CSIDMASA_FB2);
+				}
+			} else {
+				list_add_tail(&cam->frame[index].queue,
+					      &cam->ready_q);
+			}
+		} else if (cam->frame[index].buffer.flags &
+				V4L2_BUF_FLAG_QUEUED) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
+					"buffer already queued\n");
+			retval = -EINVAL;
+		} else if (cam->frame[index].buffer.
+			   flags & V4L2_BUF_FLAG_DONE) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
+			       "overwrite done buffer.\n");
+			cam->frame[index].buffer.flags &=
+			    ~V4L2_BUF_FLAG_DONE;
+			cam->frame[index].buffer.flags |=
+			    V4L2_BUF_FLAG_QUEUED;
+			retval = -EINVAL;
+		}
+		buf->flags = cam->frame[index].buffer.flags;
+		spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
+
+		break;
+	}
+
+	case VIDIOC_DQBUF: {
+		struct v4l2_buffer *buf = arg;
+		pr_debug("   case VIDIOC_DQBUF\n");
+
+		retval = csi_v4l_dqueue(cam, buf);
+
+		break;
+	}
+
+	case VIDIOC_STREAMON: {
+		pr_debug("   case VIDIOC_STREAMON\n");
+		retval = csi_streamon(cam);
+		break;
+	}
+
+	case VIDIOC_STREAMOFF: {
+		pr_debug("   case VIDIOC_STREAMOFF\n");
+		retval = csi_streamoff(cam);
+		break;
+	}
+
+	case VIDIOC_S_CTRL:
+	case VIDIOC_G_STD:
+	case VIDIOC_G_OUTPUT:
+	case VIDIOC_S_OUTPUT:
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_CROP:
+	case VIDIOC_CROPCAP:
+	case VIDIOC_S_STD:
+	case VIDIOC_G_CTRL:
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_ENUMINPUT:
+	case VIDIOC_G_INPUT:
+	case VIDIOC_S_INPUT:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	case VIDIOC_ENUMOUTPUT:
+	default:
+		pr_debug("   case not supported\n");
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&cam->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L interface - ioctl function
+ *
+ * @return  None
+ */
+static long csi_v4l_ioctl(struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	return video_usercopy(file, cmd, arg, csi_v4l_do_ioctl);
+}
+
+/*!
+ * V4L interface - mmap function
+ *
+ * @param file        structure file *
+ *
+ * @param vma         structure vm_area_struct *
+ *
+ * @return status     0 Success, EINTR busy lock error, ENOBUFS remap_page error
+ */
+static int csi_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *dev = video_devdata(file);
+	unsigned long size;
+	int res = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	pr_debug("%s\n", __func__);
+	pr_debug("\npgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		 vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	size = vma->vm_end - vma->vm_start;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		pr_err("ERROR: v4l2 capture: %s : "
+		       "remap_pfn_range failed\n", __func__);
+		res = -ENOBUFS;
+		goto csi_mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+csi_mmap_exit:
+	up(&cam->busy_lock);
+	return res;
+}
+
+/*!
+ * This structure defines the functions to be called in this driver.
+ */
+static struct v4l2_file_operations csi_v4l_fops = {
+	.owner = THIS_MODULE,
+	.open = csi_v4l_open,
+	.release = csi_v4l_close,
+	.read = csi_v4l_read,
+	.ioctl = csi_v4l_ioctl,
+	.mmap = csi_mmap,
+};
+
+static struct video_device csi_v4l_template = {
+	.name = "Mx25 Camera",
+	.fops = &csi_v4l_fops,
+	.release = video_device_release,
+};
+
+/*!
+ * This function can be used to release any platform data on closing.
+ */
+static void camera_platform_release(struct device *device)
+{
+}
+
+/*! Device Definition for csi v4l2 device */
+static struct platform_device csi_v4l2_devices = {
+	.name = "csi_v4l2",
+	.dev = {
+		.release = camera_platform_release,
+		},
+	.id = 0,
+};
+
+/*!
+ * initialize cam_data structure
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static void init_camera_struct(cam_data *cam)
+{
+	pr_debug("In MVC: %s\n", __func__);
+
+	/* Default everything to 0 */
+	memset(cam, 0, sizeof(cam_data));
+
+	init_MUTEX(&cam->param_lock);
+	init_MUTEX(&cam->busy_lock);
+
+	cam->video_dev = video_device_alloc();
+	if (cam->video_dev == NULL)
+		return;
+
+	*(cam->video_dev) = csi_v4l_template;
+
+	video_set_drvdata(cam->video_dev, cam);
+	dev_set_drvdata(&csi_v4l2_devices.dev, (void *)cam);
+	cam->video_dev->minor = -1;
+
+	init_waitqueue_head(&cam->enc_queue);
+	init_waitqueue_head(&cam->still_queue);
+
+	cam->streamparm.parm.capture.capturemode = 0;
+
+	cam->standard.index = 0;
+	cam->standard.id = V4L2_STD_UNKNOWN;
+	cam->standard.frameperiod.denominator = 30;
+	cam->standard.frameperiod.numerator = 1;
+	cam->standard.framelines = 480;
+	cam->standard_autodetect = true;
+	cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
+	cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+	cam->overlay_on = false;
+	cam->capture_on = false;
+	cam->skip_frame = 0;
+	cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
+
+	cam->v2f.fmt.pix.sizeimage = 480 * 640 * 2;
+	cam->v2f.fmt.pix.bytesperline = 640 * 2;
+	cam->v2f.fmt.pix.width = 640;
+	cam->v2f.fmt.pix.height = 480;
+	cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY;
+	cam->win.w.width = 160;
+	cam->win.w.height = 160;
+	cam->win.w.left = 0;
+	cam->win.w.top = 0;
+	cam->still_counter = 0;
+
+	cam->enc_callback = camera_callback;
+	csi_start_callback(cam);
+	init_waitqueue_head(&cam->power_queue);
+	spin_lock_init(&cam->queue_int_lock);
+	spin_lock_init(&cam->dqueue_int_lock);
+}
+
+/*!
+ * camera_power function
+ *    Turns Sensor power On/Off
+ *
+ * @param       cam           cam data struct
+ * @param       cameraOn      true to turn camera on, false to turn off power.
+ *
+ * @return status
+ */
+static u8 camera_power(cam_data *cam, bool cameraOn)
+{
+	pr_debug("In MVC: %s on=%d\n", __func__, cameraOn);
+
+	if (cameraOn == true) {
+		csi_enable_mclk(CSI_MCLK_I2C, true, true);
+		vidioc_int_s_power(cam->sensor, 1);
+	} else {
+		csi_enable_mclk(CSI_MCLK_I2C, false, false);
+		vidioc_int_s_power(cam->sensor, 0);
+	}
+	return 0;
+}
+
+/*!
+ * This function is called to put the sensor in a low power state.
+ * Refer to the document driver-model/driver.txt in the kernel source tree
+ * for more information.
+ *
+ * @param   pdev  the device structure used to give information on which I2C
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int csi_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (cam == NULL)
+		return -1;
+
+	cam->low_power = true;
+
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+
+	camera_power(cam, false);
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the sensor back from a low power state.
+ * Refer to the document driver-model/driver.txt in the kernel source tree
+ * for more information.
+ *
+ * @param   pdev   the device structure
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int csi_v4l2_resume(struct platform_device *pdev)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (cam == NULL)
+		return -1;
+
+	cam->low_power = false;
+	wake_up_interruptible(&cam->power_queue);
+	camera_power(cam, true);
+
+	if (cam->overlay_on == true)
+		start_preview(cam);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver csi_v4l2_driver = {
+	.driver = {
+		   .name = "csi_v4l2",
+		   },
+	.probe = NULL,
+	.remove = NULL,
+#ifdef CONFIG_PM
+	.suspend = csi_v4l2_suspend,
+	.resume = csi_v4l2_resume,
+#endif
+	.shutdown = NULL,
+};
+
+/*!
+ * Initializes the camera driver.
+ */
+static int csi_v4l2_master_attach(struct v4l2_int_device *slave)
+{
+	cam_data *cam = slave->u.slave->master->priv;
+	struct v4l2_format cam_fmt;
+
+	pr_debug("In MVC: %s\n", __func__);
+	pr_debug("   slave.name = %s\n", slave->name);
+	pr_debug("   master.name = %s\n", slave->u.slave->master->name);
+
+	cam->sensor = slave;
+	if (slave == NULL) {
+		pr_err("ERROR: v4l2 capture: slave parameter not valid.\n");
+		return -1;
+	}
+
+	csi_enable_mclk(CSI_MCLK_I2C, true, true);
+	vidioc_int_dev_init(slave);
+	csi_enable_mclk(CSI_MCLK_I2C, false, false);
+	cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	/* Used to detect TV in (type 1) vs. camera (type 0) */
+	cam->device_type = cam_fmt.fmt.pix.priv;
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+
+	return 0;
+}
+
+/*!
+ * Disconnects the camera driver.
+ */
+static void csi_v4l2_master_detach(struct v4l2_int_device *slave)
+{
+	pr_debug("In MVC: %s\n", __func__);
+
+	vidioc_int_dev_exit(slave);
+}
+
+/*!
+ * Entry point for the V4L2
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int camera_init(void)
+{
+	u8 err = 0;
+
+	/* Register the device driver structure. */
+	err = platform_driver_register(&csi_v4l2_driver);
+	if (err != 0) {
+		pr_err("ERROR: v4l2 capture:camera_init: "
+		       "platform_driver_register failed.\n");
+		return err;
+	}
+
+	/* Create g_cam and initialize it. */
+	g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
+	if (g_cam == NULL) {
+		pr_err("ERROR: v4l2 capture: failed to register camera\n");
+		platform_driver_unregister(&csi_v4l2_driver);
+		return -1;
+	}
+	init_camera_struct(g_cam);
+
+	/* Set up the v4l2 device and register it */
+	csi_v4l2_int_device.priv = g_cam;
+	/* This function contains a bug that won't let this be rmmod'd. */
+	v4l2_int_device_register(&csi_v4l2_int_device);
+
+	/* Register the platform device */
+	err = platform_device_register(&csi_v4l2_devices);
+	if (err != 0) {
+		pr_err("ERROR: v4l2 capture: camera_init: "
+		       "platform_device_register failed.\n");
+		platform_driver_unregister(&csi_v4l2_driver);
+		kfree(g_cam);
+		g_cam = NULL;
+		return err;
+	}
+
+	/* register v4l video device */
+	if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr)
+	    == -1) {
+		platform_device_unregister(&csi_v4l2_devices);
+		platform_driver_unregister(&csi_v4l2_driver);
+		kfree(g_cam);
+		g_cam = NULL;
+		pr_err("ERROR: v4l2 capture: video_register_device failed\n");
+		return -1;
+	}
+	pr_debug("   Video device registered: %s #%d\n",
+		 g_cam->video_dev->name, g_cam->video_dev->minor);
+
+	return err;
+}
+
+/*!
+ * Exit and cleanup for the V4L2
+ */
+static void __exit camera_exit(void)
+{
+	pr_debug("In MVC: %s\n", __func__);
+
+	if (g_cam->open_count) {
+		pr_err("ERROR: v4l2 capture:camera open "
+		       "-- setting ops to NULL\n");
+	} else {
+		pr_info("V4L2 freeing image input device\n");
+		v4l2_int_device_unregister(&csi_v4l2_int_device);
+		csi_stop_callback(g_cam);
+		video_unregister_device(g_cam->video_dev);
+		platform_driver_unregister(&csi_v4l2_driver);
+		platform_device_unregister(&csi_v4l2_devices);
+
+		kfree(g_cam);
+		g_cam = NULL;
+	}
+}
+
+module_init(camera_init);
+module_exit(camera_exit);
+
+module_param(video_nr, int, 0444);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2 capture driver for Mx25 based cameras");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/capture/emma_mt9v111.c b/drivers/media/video/mxc/capture/emma_mt9v111.c
new file mode 100644
index 000000000000..73e9bba36d1e
--- /dev/null
+++ b/drivers/media/video/mxc/capture/emma_mt9v111.c
@@ -0,0 +1,679 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mt9v111.c
+ *
+ * @brief mt9v111 camera driver functions
+ *
+ * @ingroup Camera
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include "mxc_v4l2_capture.h"
+#include "mt9v111.h"
+
+#ifdef MT9V111_DEBUG
+static u16 testpattern;
+#endif
+
+static sensor_interface *interface_param;
+static mt9v111_conf mt9v111_device;
+static int reset_frame_rate = 30;
+
+#define MT9V111_FRAME_RATE_NUM    20
+
+static mt9v111_image_format format[2] = {
+	{
+	 .index = 0,
+	 .width = 640,
+	 .height = 480,
+	 },
+	{
+	 .index = 1,
+	 .width = 352,
+	 .height = 288,
+	 },
+};
+
+static int mt9v111_attach(struct i2c_adapter *adapter);
+static int mt9v111_detach(struct i2c_client *client);
+
+static struct i2c_driver mt9v111_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "MT9V111 Client",
+		   },
+	.attach_adapter = mt9v111_attach,
+	.detach_client = mt9v111_detach,
+};
+
+static struct i2c_client mt9v111_i2c_client = {
+	.name = "mt9v111 I2C dev",
+	.addr = MT9V111_I2C_ADDRESS,
+	.driver = &mt9v111_i2c_driver,
+};
+
+/*
+ * Function definitions
+ */
+
+#ifdef MT9V111_DEBUG
+static inline int mt9v111_read_reg(u8 reg)
+{
+	int val = i2c_smbus_read_word_data(&mt9v111_i2c_client, reg);
+	if (val != -1)
+		val = cpu_to_be16(val);
+	return val;
+}
+#endif
+
+static inline int mt9v111_write_reg(u8 reg, u16 val)
+{
+	pr_debug("write reg %x val %x.\n", reg, val);
+	return i2c_smbus_write_word_data(&mt9v111_i2c_client, reg,
+					 cpu_to_be16(val));
+}
+
+/*!
+ * Initialize mt9v111_sensor_lib
+ * Libarary for Sensor configuration through I2C
+ *
+ * @param       coreReg       Core Registers
+ * @param       ifpReg        IFP Register
+ *
+ * @return status
+ */
+static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg)
+{
+	u8 reg;
+	u16 data;
+	u8 error = 0;
+
+	/*
+	 * setup to IFP registers
+	 */
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111I_MODE_CONTROL;
+	data = ifpReg->modeControl;
+	mt9v111_write_reg(reg, data);
+
+	/* Output format */
+	reg = MT9V111I_FORMAT_CONTROL;
+	data = ifpReg->formatControl;	/* Set bit 12 */
+	mt9v111_write_reg(reg, data);
+
+	/* AE limit 4 */
+	reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE;
+	data = ifpReg->gainLimitAE;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_OUTPUT_FORMAT_CTRL2;
+	data = ifpReg->outputFormatCtrl2;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_AE_SPEED;
+	data = ifpReg->AESpeed;
+	mt9v111_write_reg(reg, data);
+
+	/* output image size */
+	reg = MT9V111i_H_PAN;
+	data = 0x8000 | ifpReg->HPan;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_ZOOM;
+	data = 0x8000 | ifpReg->HZoom;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_SIZE;
+	data = 0x8000 | ifpReg->HSize;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_PAN;
+	data = 0x8000 | ifpReg->VPan;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_ZOOM;
+	data = 0x8000 | ifpReg->VZoom;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_SIZE;
+	data = 0x8000 | ifpReg->VSize;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_PAN;
+	data = ~0x8000 & ifpReg->HPan;
+	mt9v111_write_reg(reg, data);
+#if 0
+	reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM;
+	data = ifpReg->upperShutterDelayLi;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_SHUTTER_60;
+	data = ifpReg->shutter_width_60;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_SEARCH_FLICK_60;
+	data = ifpReg->search_flicker_60;
+	mt9v111_write_reg(reg, data);
+#endif
+
+	/*
+	 * setup to sensor core registers
+	 */
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = coreReg->addressSelect;
+	mt9v111_write_reg(reg, data);
+
+	/* enable changes and put the Sync bit on */
+	reg = MT9V111S_OUTPUT_CTRL;
+	data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
+	mt9v111_write_reg(reg, data);
+
+	/* min PIXCLK - Default */
+	reg = MT9V111S_PIXEL_CLOCK_SPEED;
+	data = coreReg->pixelClockSpeed;
+	mt9v111_write_reg(reg, data);
+
+	/* Setup image flipping / Dark rows / row/column skip */
+	reg = MT9V111S_READ_MODE;
+	data = coreReg->readMode;
+	mt9v111_write_reg(reg, data);
+
+	/*zoom 0 */
+	reg = MT9V111S_DIGITAL_ZOOM;
+	data = coreReg->digitalZoom;
+	mt9v111_write_reg(reg, data);
+
+	/* min H-blank */
+	reg = MT9V111S_HOR_BLANKING;
+	data = coreReg->horizontalBlanking;
+	mt9v111_write_reg(reg, data);
+
+	/* min V-blank */
+	reg = MT9V111S_VER_BLANKING;
+	data = coreReg->verticalBlanking;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111S_SHUTTER_WIDTH;
+	data = coreReg->shutterWidth;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111S_SHUTTER_DELAY;
+	data = ifpReg->upperShutterDelayLi;
+	mt9v111_write_reg(reg, data);
+
+	/* changes become effective */
+	reg = MT9V111S_OUTPUT_CTRL;
+	data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
+	mt9v111_write_reg(reg, data);
+
+	return error;
+}
+
+/*!
+ * mt9v111 sensor interface Initialization
+ * @param param            sensor_interface *
+ * @param width            u32
+ * @param height           u32
+ * @return  None
+ */
+static void mt9v111_interface(sensor_interface *param, u32 width, u32 height)
+{
+	param->Vsync_pol = 0x0;
+	param->clk_mode = 0x0;	/*gated */
+	param->pixclk_pol = 0x0;
+	param->data_width = 0x1;
+	param->data_pol = 0x0;
+	param->ext_vsync = 0x0;
+	param->Vsync_pol = 0x0;
+	param->Hsync_pol = 0x0;
+	param->width = width - 1;
+	param->height = height - 1;
+	param->active_width = width;
+	param->active_height = height;
+	param->pixel_fmt = IPU_PIX_FMT_UYVY;
+	param->mclk = 27000000;
+}
+
+/*!
+ * MT9V111 frame rate calculate
+ *
+ * @param frame_rate       int *
+ * @param mclk             int
+ * @return  None
+ */
+static void mt9v111_rate_cal(int *frame_rate, int mclk)
+{
+	int num_clock_per_row;
+	int max_rate = 0;
+
+	mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN;
+
+	num_clock_per_row = (format[0].width + 114 + MT9V111_HORZBLANK_MIN) * 2;
+	max_rate = mclk / (num_clock_per_row *
+			   (format[0].height + MT9V111_VERTBLANK_DEFAULT));
+
+	if ((*frame_rate > max_rate) || (*frame_rate == 0)) {
+		*frame_rate = max_rate;
+	}
+
+	mt9v111_device.coreReg->verticalBlanking
+	    = mclk / (*frame_rate * num_clock_per_row) - format[0].height;
+
+	reset_frame_rate = *frame_rate;
+}
+
+/*!
+ * MT9V111 sensor configuration
+ *
+ * @param frame_rate       int *
+ * @param high_quality     int
+ * @return  sensor_interface *
+ */
+sensor_interface *mt9v111_config(int *frame_rate, int high_quality)
+{
+	u32 out_width, out_height;
+
+	if (interface_param == NULL)
+		return NULL;
+
+	mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA;
+	mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP;
+
+	mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT;
+	mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH;
+	mt9v111_device.coreReg->zoomColStart = 0;
+	mt9v111_device.coreReg->zomRowStart = 0;
+	mt9v111_device.coreReg->digitalZoom = 0x0;
+
+	mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT;
+	mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN;
+	mt9v111_device.coreReg->pixelClockSpeed = 0;
+	mt9v111_device.coreReg->readMode = 0xd0a1;
+
+	mt9v111_device.ifpReg->outputFormatCtrl2 = 0;
+	mt9v111_device.ifpReg->gainLimitAE = 0x300;
+	mt9v111_device.ifpReg->AESpeed = 0x80;
+
+	/* here is the default value */
+	mt9v111_device.ifpReg->formatControl = 0xc800;
+	mt9v111_device.ifpReg->modeControl = 0x708e;
+	mt9v111_device.ifpReg->awbSpeed = 0x4514;
+	mt9v111_device.coreReg->shutterWidth = 0xf8;
+
+	out_width = 640;
+	out_height = 480;
+
+	/*output size */
+	mt9v111_device.ifpReg->HPan = 0;
+	mt9v111_device.ifpReg->HZoom = 640;
+	mt9v111_device.ifpReg->HSize = out_width;
+	mt9v111_device.ifpReg->VPan = 0;
+	mt9v111_device.ifpReg->VZoom = 480;
+	mt9v111_device.ifpReg->VSize = out_height;
+
+	mt9v111_interface(interface_param, out_width, out_height);
+	set_mclk_rate(&interface_param->mclk);
+	mt9v111_rate_cal(frame_rate, interface_param->mclk);
+	mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg);
+
+	return interface_param;
+}
+
+/*!
+ * mt9v111 sensor set color configuration
+ *
+ * @param bright       int
+ * @param saturation   int
+ * @param red          int
+ * @param green        int
+ * @param blue         int
+ * @return  None
+ */
+static void
+mt9v111_set_color(int bright, int saturation, int red, int green, int blue)
+{
+	u8 reg;
+	u16 data;
+
+	switch (saturation) {
+	case 100:
+		mt9v111_device.ifpReg->awbSpeed = 0x4514;
+		break;
+	case 150:
+		mt9v111_device.ifpReg->awbSpeed = 0x6D14;
+		break;
+	case 75:
+		mt9v111_device.ifpReg->awbSpeed = 0x4D14;
+		break;
+	case 50:
+		mt9v111_device.ifpReg->awbSpeed = 0x5514;
+		break;
+	case 37:
+		mt9v111_device.ifpReg->awbSpeed = 0x5D14;
+		break;
+	case 25:
+		mt9v111_device.ifpReg->awbSpeed = 0x6514;
+		break;
+	default:
+		mt9v111_device.ifpReg->awbSpeed = 0x4514;
+		break;
+	}
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111I_AWB_SPEED;
+	data = mt9v111_device.ifpReg->awbSpeed;
+	mt9v111_write_reg(reg, data);
+}
+
+/*!
+ * mt9v111 sensor get color configuration
+ *
+ * @param bright       int *
+ * @param saturation   int *
+ * @param red          int *
+ * @param green        int *
+ * @param blue         int *
+ * @return  None
+ */
+static void
+mt9v111_get_color(int *bright, int *saturation, int *red, int *green, int *blue)
+{
+	*saturation = (mt9v111_device.ifpReg->awbSpeed & 0x3800) >> 11;
+	switch (*saturation) {
+	case 0:
+		*saturation = 100;
+		break;
+	case 1:
+		*saturation = 75;
+		break;
+	case 2:
+		*saturation = 50;
+		break;
+	case 3:
+		*saturation = 37;
+		break;
+	case 4:
+		*saturation = 25;
+		break;
+	case 5:
+		*saturation = 150;
+		break;
+	case 6:
+		*saturation = 0;
+		break;
+	default:
+		*saturation = 0;
+		break;
+	}
+}
+
+/*!
+ * mt9v111 sensor set AE measurement window mode configuration
+ *
+ * @param ae_mode      int
+ * @return  None
+ */
+static void mt9v111_set_ae_mode(int ae_mode)
+{
+	u8 reg;
+	u16 data;
+
+	mt9v111_device.ifpReg->modeControl &= 0xfff3;
+	mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 2;
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_MODE_CONTROL;
+	data = mt9v111_device.ifpReg->modeControl;
+	mt9v111_write_reg(reg, data);
+}
+
+/*!
+ * mt9v111 sensor get AE measurement window mode configuration
+ *
+ * @param ae_mode      int *
+ * @return  None
+ */
+static void mt9v111_get_ae_mode(int *ae_mode)
+{
+	if (ae_mode != NULL) {
+		*ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2;
+	}
+}
+
+/*!
+ * mt9v111 Reset function
+ *
+ * @return  None
+ */
+static sensor_interface *mt9v111_reset(void)
+{
+	return mt9v111_config(&reset_frame_rate, 0);
+}
+
+struct camera_sensor camera_sensor_if = {
+	.set_color = mt9v111_set_color,
+	.get_color = mt9v111_get_color,
+	.set_ae_mode = mt9v111_set_ae_mode,
+	.get_ae_mode = mt9v111_get_ae_mode,
+	.config = mt9v111_config,
+	.reset = mt9v111_reset,
+};
+
+#ifdef MT9V111_DEBUG
+/*!
+ * Set sensor to test mode, which will generate test pattern.
+ *
+ * @return none
+ */
+static void mt9v111_test_pattern(bool flag)
+{
+	u16 data;
+
+	/* switch to sensor registers */
+	mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA);
+
+	if (flag == true) {
+		testpattern = MT9V111S_OUTCTRL_TEST_MODE;
+
+		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF;
+		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
+
+		mt9v111_write_reg(MT9V111S_TEST_DATA, 0);
+
+		/* changes take effect */
+		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
+		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+	} else {
+		testpattern = 0;
+
+		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40;
+		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
+
+		/* changes take effect */
+		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
+		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+	}
+}
+#endif
+
+/*!
+ * mt9v111 I2C detect_client function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @param address            int
+ * @param kind               int
+ *
+ * @return  Error code indicating success or failure
+ */
+static int mt9v111_detect_client(struct i2c_adapter *adapter, int address,
+				 int kind)
+{
+	mt9v111_i2c_client.adapter = adapter;
+	if (i2c_attach_client(&mt9v111_i2c_client)) {
+		mt9v111_i2c_client.adapter = NULL;
+		printk(KERN_ERR "mt9v111_attach: i2c_attach_client failed\n");
+		return -1;
+	}
+
+	interface_param = (sensor_interface *)
+	    kmalloc(sizeof(sensor_interface), GFP_KERNEL);
+	if (!interface_param) {
+		printk(KERN_ERR "mt9v111_attach: kmalloc failed \n");
+		return -1;
+	}
+
+	printk(KERN_INFO "MT9V111 Detected\n");
+
+	return 0;
+}
+
+static unsigned short normal_i2c[] = { MT9V111_I2C_ADDRESS, I2C_CLIENT_END };
+
+/* Magic definition of all other variables and things */
+I2C_CLIENT_INSMOD;
+
+/*!
+ * mt9v111 I2C attach function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  Error code indicating success or failure
+ */
+static int mt9v111_attach(struct i2c_adapter *adap)
+{
+	uint32_t mclk = 27000000;
+	struct clk *clk;
+	int err;
+
+	clk = clk_get(NULL, "csi_clk");
+	clk_enable(clk);
+	set_mclk_rate(&mclk);
+
+	err = i2c_probe(adap, &addr_data, &mt9v111_detect_client);
+
+	clk_disable(clk);
+	clk_put(clk);
+
+	return err;
+}
+
+/*!
+ * mt9v111 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int mt9v111_detach(struct i2c_client *client)
+{
+	int err;
+
+	if (!mt9v111_i2c_client.adapter)
+		return -1;
+
+	err = i2c_detach_client(&mt9v111_i2c_client);
+	mt9v111_i2c_client.adapter = NULL;
+
+	if (interface_param)
+		kfree(interface_param);
+	interface_param = NULL;
+
+	return err;
+}
+
+extern void gpio_sensor_active(void);
+
+/*!
+ * MT9V111 init function
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int mt9v111_init(void)
+{
+	u8 err;
+
+	gpio_sensor_active();
+
+	mt9v111_device.coreReg = (mt9v111_coreReg *)
+	    kmalloc(sizeof(mt9v111_coreReg), GFP_KERNEL);
+	if (!mt9v111_device.coreReg)
+		return -1;
+
+	memset(mt9v111_device.coreReg, 0, sizeof(mt9v111_coreReg));
+
+	mt9v111_device.ifpReg = (mt9v111_IFPReg *)
+	    kmalloc(sizeof(mt9v111_IFPReg), GFP_KERNEL);
+	if (!mt9v111_device.ifpReg) {
+		kfree(mt9v111_device.coreReg);
+		mt9v111_device.coreReg = NULL;
+		return -1;
+	}
+
+	memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg));
+
+	err = i2c_add_driver(&mt9v111_i2c_driver);
+
+	return err;
+}
+
+extern void gpio_sensor_inactive(void);
+/*!
+ * MT9V111 cleanup function
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit mt9v111_clean(void)
+{
+	if (mt9v111_device.coreReg) {
+		kfree(mt9v111_device.coreReg);
+		mt9v111_device.coreReg = NULL;
+	}
+
+	if (mt9v111_device.ifpReg) {
+		kfree(mt9v111_device.ifpReg);
+		mt9v111_device.ifpReg = NULL;
+	}
+
+	i2c_del_driver(&mt9v111_i2c_driver);
+
+	gpio_sensor_inactive();
+}
+
+module_init(mt9v111_init);
+module_exit(mt9v111_clean);
+
+/* Exported symbols for modules. */
+EXPORT_SYMBOL(camera_sensor_if);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Mt9v111 Camera Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/emma_ov2640.c b/drivers/media/video/mxc/capture/emma_ov2640.c
new file mode 100644
index 000000000000..ceffea4d52a9
--- /dev/null
+++ b/drivers/media/video/mxc/capture/emma_ov2640.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/regulator/consumer.h>
+
+#include "mxc_v4l2_capture.h"
+
+enum ov2640_mode {
+	ov2640_mode_1600_1120,
+	ov2640_mode_800_600
+};
+
+struct reg_value {
+	u8 reg;
+	u8 value;
+	int delay_ms;
+};
+
+static struct reg_value ov2640_setting_1600_1120[] = {
+	{0xff, 0x1, 0}, {0x12, 0x80, 1}, {0xff, 0, 0}, {0x2c, 0xff, 0},
+	{0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, {0x11, 0x01, 0},
+	{0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0},
+	{0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0},
+	{0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x82, 0},
+	{0x35, 0x88, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0},
+	{0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0},
+	{0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0},
+	{0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0},
+	{0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x0c, 0x3c, 0},
+	{0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, {0x60, 0x55, 0},
+	{0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0},
+	{0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 00, 0},
+	{0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0},
+	{0x5a, 0x57, 0}, {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0},
+	{0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0},
+	{0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0},
+	{0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0xd7, 0x03, 0},
+	{0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0},
+	{0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0},
+	{0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0},
+	{0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0},
+	{0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0},
+	{0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0},
+	{0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0},
+	{0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0},
+	{0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, {0x93, 0x00, 0},
+	{0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0},
+	{0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0},
+	{0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0},
+	{0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0},
+	{0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0},
+	{0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0},
+	{0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0},
+	{0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xa6, 0x00, 0},
+	{0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, {0xa7, 0x31, 0},
+	{0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0},
+	{0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0},
+	{0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0},
+	{0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0},
+	{0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x18, 0},
+	{0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0},
+	{0x5a, 0x90, 0}, {0x5b, 0x18, 0}, {0x5c, 0x05, 0}, {0xc3, 0xef, 0},
+	{0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0},
+	{0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0}
+};
+
+static struct reg_value ov2640_setting_800_600[] = {
+	{0xff, 0, 0}, {0xff, 1, 0}, {0x12, 0x80, 1}, {0xff, 00, 0},
+	{0x2c, 0xff, 0}, {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0},
+	{0x11, 0x01, 0}, {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0},
+	{0x14, 0x48, 0}, {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0},
+	{0x3b, 0xfb, 0}, {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0},
+	{0x39, 0x92, 0}, {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0},
+	{0x23, 0x00, 0}, {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0},
+	{0x07, 0xc0, 0}, {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0},
+	{0x4a, 0x81, 0}, {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0},
+	{0x26, 0x82, 0}, {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0},
+	{0x0c, 0x3c, 0}, {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0},
+	{0x60, 0x55, 0}, {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0},
+	{0x20, 0x80, 0}, {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0},
+	{0x6e, 00, 0}, {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0},
+	{0x12, 0x40, 0}, {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0},
+	{0x1a, 0x4b, 0}, {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0},
+	{0x50, 0xa8, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0},
+	{0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0},
+	{0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0},
+	{0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0x88, 0x3f, 0},
+	{0xd7, 0x03, 0}, {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0},
+	{0xc9, 0x80, 0}, {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0},
+	{0x7d, 0x48, 0}, {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0},
+	{0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0},
+	{0x91, 0x1a, 0}, {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0},
+	{0x91, 0x75, 0}, {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0},
+	{0x91, 0x96, 0}, {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0},
+	{0x91, 0xd7, 0}, {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0},
+	{0x93, 0x06, 0}, {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0},
+	{0x93, 0x00, 0}, {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0},
+	{0x97, 0x02, 0}, {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0},
+	{0x97, 0x28, 0}, {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0},
+	{0x97, 0x80, 0}, {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0},
+	{0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0},
+	{0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0},
+	{0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0},
+	{0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0},
+	{0xa6, 0x00, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0},
+	{0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0},
+	{0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0},
+	{0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0},
+	{0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0x64, 0},
+	{0xc1, 0x4b, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0xc8, 0},
+	{0x52, 0x96, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x00, 0},
+	{0x57, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, {0x5c, 0x00, 0},
+	{0xc3, 0xef, 0}, {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0},
+	{0xe1, 0x67, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0}
+};
+
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+static struct regulator *gpo_regulator;
+u32 mclk = 24000000;
+
+struct i2c_client *ov2640_i2c_client;
+
+static sensor_interface *interface_param;
+static int reset_frame_rate = 30;
+static int ov2640_probe(struct i2c_client *adapter,
+			const struct i2c_device_id *id);
+static int ov2640_remove(struct i2c_client *client);
+
+static const struct i2c_device_id ov2640_id[] = {
+	{"ov2640", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, ov2640_id);
+
+static struct i2c_driver ov2640_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "ov2640",
+		   },
+	.probe = ov2640_probe,
+	.remove = ov2640_remove,
+	.id_table = ov2640_id,
+};
+
+/*!
+ * ov2640 I2C attach function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  Error code indicating success or failure
+ */
+static int ov2640_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct mxc_camera_platform_data *plat_data = client->dev.platform_data;
+
+	ov2640_i2c_client = client;
+	mclk = plat_data->mclk;
+
+	io_regulator = regulator_get(&client->dev, plat_data->io_regulator);
+	core_regulator = regulator_get(&client->dev, plat_data->core_regulator);
+	analog_regulator =
+	    regulator_get(&client->dev, plat_data->analog_regulator);
+	gpo_regulator = regulator_get(&client->dev, plat_data->gpo_regulator);
+
+	interface_param = (sensor_interface *)
+	    kmalloc(sizeof(sensor_interface), GFP_KERNEL);
+	if (!interface_param) {
+		dev_dbg(&ov2640_i2c_client->dev,
+			"ov2640_probe: kmalloc failed \n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*!
+ * ov2640 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int ov2640_remove(struct i2c_client *client)
+{
+	kfree(interface_param);
+	interface_param = NULL;
+
+	if (!IS_ERR_VALUE((unsigned long)io_regulator)) {
+		regulator_disable(io_regulator);
+		regulator_put(io_regulator);
+	}
+
+	if (!IS_ERR_VALUE((unsigned long)core_regulator)) {
+		regulator_disable(core_regulator);
+		regulator_put(core_regulator);
+	}
+
+	if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) {
+		regulator_disable(gpo_regulator);
+		regulator_put(gpo_regulator);
+	}
+
+	if (!IS_ERR_VALUE((unsigned long)analog_regulator)) {
+		regulator_disable(analog_regulator);
+		regulator_put(analog_regulator);
+	}
+
+	return 0;
+}
+
+static int ov2640_write_reg(u8 reg, u8 val)
+{
+	if (i2c_smbus_write_byte_data(ov2640_i2c_client, reg, val) < 0) {
+		dev_dbg(&ov2640_i2c_client->dev,
+			"%s:write reg errorr:reg=%x,val=%x\n", __func__, reg,
+			val);
+		return -1;
+	}
+	return 0;
+}
+
+static int ov2640_init_mode(enum ov2640_mode mode)
+{
+	struct reg_value *setting;
+	int i, num;
+
+	switch (mode) {
+	case ov2640_mode_1600_1120:
+		setting = ov2640_setting_1600_1120;
+		num = ARRAY_SIZE(ov2640_setting_1600_1120);
+		break;
+	case ov2640_mode_800_600:
+		setting = ov2640_setting_800_600;
+		num = ARRAY_SIZE(ov2640_setting_800_600);
+		break;
+	default:
+		return 0;
+	}
+
+	for (i = 0; i < num; i++) {
+		ov2640_write_reg(setting[i].reg, setting[i].value);
+		if (setting[i].delay_ms > 0)
+			msleep(setting[i].delay_ms);
+	}
+
+	return 0;
+}
+
+/*!
+ * ov2640 sensor interface Initialization
+ * @param param            sensor_interface *
+ * @param width            u32
+ * @param height           u32
+ * @return  None
+ */
+static void ov2640_interface(sensor_interface *param, u32 width, u32 height)
+{
+	param->Vsync_pol = 0x0;
+	param->clk_mode = 0x0;	/*gated */
+	param->pixclk_pol = 0x0;
+	param->data_width = 0x1;
+	param->data_pol = 0x0;
+	param->ext_vsync = 0x0;
+	param->Vsync_pol = 0x0;
+	param->Hsync_pol = 0x0;
+	param->width = width - 1;
+	param->height = height - 1;
+	param->active_width = width;
+	param->active_height = height;
+	param->pixel_fmt = IPU_PIX_FMT_UYVY;
+	param->mclk = mclk;
+}
+
+static void ov2640_set_color(int bright, int saturation, int red, int green,
+			     int blue)
+{
+
+}
+
+static void ov2640_get_color(int *bright, int *saturation, int *red, int *green,
+			     int *blue)
+{
+
+}
+static void ov2640_set_ae_mode(int ae_mode)
+{
+
+}
+static void ov2640_get_ae_mode(int *ae_mode)
+{
+
+}
+
+extern void gpio_sensor_active(void);
+
+static sensor_interface *ov2640_config(int *frame_rate, int high_quality)
+{
+
+	u32 out_width, out_height;
+
+	/*set io votage */
+	if (!IS_ERR_VALUE((unsigned long)io_regulator)) {
+		regulator_set_voltage(io_regulator, 2800000, 2800000);
+		if (regulator_enable(io_regulator) != 0) {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:io set voltage error\n", __func__);
+			return NULL;
+		} else {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:io set voltage ok\n", __func__);
+		}
+	}
+
+	/*core votage */
+	if (!IS_ERR_VALUE((unsigned long)core_regulator)) {
+		regulator_set_voltage(core_regulator, 1300000, 1300000);
+		if (regulator_enable(core_regulator) != 0) {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:core set voltage error\n", __func__);
+			return NULL;
+		} else {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:core set voltage ok\n", __func__);
+		}
+	}
+
+	/*GPO 3 */
+	if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) {
+		if (regulator_enable(gpo_regulator) != 0) {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:gpo3 enable error\n", __func__);
+			return NULL;
+		} else {
+			dev_dbg(&ov2640_i2c_client->dev, "%s:gpo3 enable ok\n",
+				__func__);
+		}
+	}
+
+	if (!IS_ERR_VALUE((unsigned long)analog_regulator)) {
+		regulator_set_voltage(analog_regulator, 2000000, 2000000);
+		if (regulator_enable(analog_regulator) != 0) {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:analog set voltage error\n", __func__);
+			return NULL;
+		} else {
+			dev_dbg(&ov2640_i2c_client->dev,
+				"%s:analog set voltage ok\n", __func__);
+		}
+	}
+
+	gpio_sensor_active();
+
+	if (high_quality) {
+		out_width = 1600;
+		out_height = 1120;
+	} else {
+		out_width = 800;
+		out_height = 600;
+	}
+	ov2640_interface(interface_param, out_width, out_height);
+	set_mclk_rate(&interface_param->mclk);
+
+	if (high_quality)
+		ov2640_init_mode(ov2640_mode_1600_1120);
+	else
+		ov2640_init_mode(ov2640_mode_800_600);
+
+	msleep(300);
+
+	return interface_param;
+}
+
+static sensor_interface *ov2640_reset(void)
+{
+	return ov2640_config(&reset_frame_rate, 0);
+}
+
+struct camera_sensor camera_sensor_if = {
+	.set_color = ov2640_set_color,
+	.get_color = ov2640_get_color,
+	.set_ae_mode = ov2640_set_ae_mode,
+	.get_ae_mode = ov2640_get_ae_mode,
+	.config = ov2640_config,
+	.reset = ov2640_reset,
+};
+
+EXPORT_SYMBOL(camera_sensor_if);
+
+/*!
+ * ov2640 init function
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int ov2640_init(void)
+{
+	u8 err;
+
+	err = i2c_add_driver(&ov2640_i2c_driver);
+
+	return err;
+}
+
+extern void gpio_sensor_inactive(void);
+/*!
+ * OV2640 cleanup function
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit ov2640_clean(void)
+{
+	i2c_del_driver(&ov2640_i2c_driver);
+
+	gpio_sensor_inactive();
+}
+
+module_init(ov2640_init);
+module_exit(ov2640_clean);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("OV2640 Camera Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/emma_v4l2_capture.c b/drivers/media/video/mxc/capture/emma_v4l2_capture.c
new file mode 100644
index 000000000000..170807716ec6
--- /dev/null
+++ b/drivers/media/video/mxc/capture/emma_v4l2_capture.c
@@ -0,0 +1,2075 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_v4l2_capture.c
+ *
+ * @brief MX27 Video For Linux 2 driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/semaphore.h>
+#include <linux/version.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+
+#include "mxc_v4l2_capture.h"
+#include "mx27_prp.h"
+#include "mx27_csi.h"
+
+static int csi_mclk_flag_backup;
+static int video_nr = -1;
+static cam_data *g_cam;
+
+/*!
+ * Free frame buffers
+ *
+ * @param cam      Structure cam_data *
+ *
+ * @return status  0 success.
+ */
+static int mxc_free_frame_buf(cam_data *cam)
+{
+	int i;
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		if (cam->frame[i].vaddress != 0) {
+			dma_free_coherent(0,
+					  cam->frame[i].buffer.length,
+					  cam->frame[i].vaddress,
+					  cam->frame[i].paddress);
+			cam->frame[i].vaddress = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * Allocate frame buffers
+ *
+ * @param cam      Structure cam_data *
+ *
+ * @param count    int number of buffer need to allocated
+ *
+ * @return status  -0 Successfully allocated a buffer, -ENOBUFS	failed.
+ */
+static int mxc_allocate_frame_buf(cam_data *cam, int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		cam->frame[i].vaddress =
+			dma_alloc_coherent(0,
+					PAGE_ALIGN(cam->v2f. fmt.pix.sizeimage),
+					   &cam->frame[i].paddress,
+					   GFP_DMA | GFP_KERNEL);
+		if (cam->frame[i].vaddress == 0) {
+			pr_debug("mxc_allocate_frame_buf failed.\n");
+			mxc_free_frame_buf(cam);
+			return -ENOBUFS;
+		}
+		cam->frame[i].buffer.index = i;
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+		cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cam->frame[i].buffer.length =
+		    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
+		cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
+		cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
+		cam->frame[i].index = i;
+	}
+
+	return 0;
+}
+
+/*!
+ * Free frame buffers status
+ *
+ * @param cam    Structure cam_data *
+ *
+ * @return none
+ */
+static void mxc_free_frames(cam_data *cam)
+{
+	int i;
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+	}
+
+	cam->enc_counter = 0;
+	cam->skip_frame = 0;
+	INIT_LIST_HEAD(&cam->ready_q);
+	INIT_LIST_HEAD(&cam->working_q);
+	INIT_LIST_HEAD(&cam->done_q);
+}
+
+/*!
+ * Return the buffer status
+ *
+ * @param cam 	   Structure cam_data *
+ * @param buf      Structure v4l2_buffer *
+ *
+ * @return status  0 success, EINVAL failed.
+ */
+static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
+{
+	/* check range */
+	if (buf->index < 0 || buf->index >= FRAME_NUM) {
+		pr_debug("mxc_v4l2_buffer_status buffers not allocated\n");
+		return -EINVAL;
+	}
+
+	memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
+	return 0;
+}
+
+/*!
+ * start the encoder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_streamon(cam_data *cam)
+{
+	struct mxc_v4l_frame *frame;
+	int err = 0;
+
+	if (!cam)
+		return -EIO;
+
+	if (list_empty(&cam->ready_q)) {
+		printk(KERN_ERR "mxc_streamon buffer not been queued yet\n");
+		return -EINVAL;
+	}
+
+	cam->capture_pid = current->pid;
+
+	if (cam->enc_enable) {
+		err = cam->enc_enable(cam);
+		if (err != 0) {
+			return err;
+		}
+	}
+
+	cam->ping_pong_csi = 0;
+	if (cam->enc_update_eba) {
+		frame =
+		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+		list_del(cam->ready_q.next);
+		list_add_tail(&frame->queue, &cam->working_q);
+		err = cam->enc_update_eba(frame->paddress, &cam->ping_pong_csi);
+
+		frame =
+		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+		list_del(cam->ready_q.next);
+		list_add_tail(&frame->queue, &cam->working_q);
+		err |=
+		    cam->enc_update_eba(frame->paddress, &cam->ping_pong_csi);
+	} else {
+		return -EINVAL;
+	}
+
+	return err;
+}
+
+/*!
+ * Shut down the encoder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_streamoff(cam_data *cam)
+{
+	int err = 0;
+
+	if (!cam)
+		return -EIO;
+
+	if (cam->enc_disable) {
+		err = cam->enc_disable(cam);
+	}
+	mxc_free_frames(cam);
+	return err;
+}
+
+/*!
+ * Valid whether the palette is supported
+ *
+ * @param palette pixel format
+ *
+ * @return 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	/*
+	 * MX27 PrP channel 2 supports YUV444, but YUV444 is not
+	 * defined by V4L2 :(
+	 */
+	return ((palette == V4L2_PIX_FMT_YUYV) ||
+		(palette == V4L2_PIX_FMT_YUV420));
+}
+
+/*!
+ * Valid and adjust the overlay window size, position
+ *
+ * @param cam      structure cam_data *
+ * @param win      struct v4l2_window  *
+ *
+ * @return 0
+ */
+static int verify_preview(cam_data *cam, struct v4l2_window *win)
+{
+	if (cam->output >= num_registered_fb) {
+		pr_debug("verify_preview No matched.\n");
+		return -1;
+	}
+	cam->overlay_fb = (struct fb_info *)registered_fb[cam->output];
+
+	/* TODO: suppose 16bpp, 4 bytes alignment */
+	win->w.left &= ~0x1;
+
+	if (win->w.width + win->w.left > cam->overlay_fb->var.xres)
+		win->w.width = cam->overlay_fb->var.xres - win->w.left;
+	if (win->w.height + win->w.top > cam->overlay_fb->var.yres)
+		win->w.height = cam->overlay_fb->var.yres - win->w.top;
+
+	/*
+	 * TODO: suppose 16bpp. Rounded down to a multiple of 2 pixels for
+	 * width according to PrP limitations.
+	 */
+	if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT))
+		win->w.height &= ~0x1;
+	else
+		win->w.width &= ~0x1;
+
+	return 0;
+}
+
+/*!
+ * start the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int start_preview(cam_data *cam)
+{
+	int err = 0;
+
+	err = prp_vf_select(cam);
+	if (err != 0)
+		return err;
+
+	cam->overlay_pid = current->pid;
+	err = cam->vf_start_sdc(cam);
+
+	return err;
+}
+
+/*!
+ * shut down the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int stop_preview(cam_data *cam)
+{
+	int err = 0;
+
+	err = prp_vf_deselect(cam);
+	return err;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_g_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		f->fmt.pix.width = cam->v2f.fmt.pix.width;
+		f->fmt.pix.height = cam->v2f.fmt.pix.height;
+		f->fmt.pix.sizeimage = cam->v2f.fmt.pix.sizeimage;
+		f->fmt.pix.pixelformat = cam->v2f.fmt.pix.pixelformat;
+		f->fmt.pix.bytesperline = cam->v2f.fmt.pix.bytesperline;
+		f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
+		retval = 0;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		f->fmt.win = cam->win;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_s_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+	int size = 0;
+	int bytesperline = 0;
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		if (!valid_mode(f->fmt.pix.pixelformat)) {
+			pr_debug("mxc_v4l2_s_fmt: format not supported\n");
+			retval = -EINVAL;
+		}
+
+		if (cam->rotation != V4L2_MXC_ROTATE_NONE)
+			pr_debug("mxc_v4l2_s_fmt: capture rotation ignored\n");
+
+		switch (f->fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_YUYV:
+			f->fmt.pix.width &= ~0x1;	/* Multiple of 2 */
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			bytesperline = f->fmt.pix.width * 2;
+			break;
+		case V4L2_PIX_FMT_YUV420:
+			f->fmt.pix.width &= ~0x7;	/* Multiple of 8 */
+			f->fmt.pix.height &= ~0x1;	/* Multiple of 2 */
+			size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
+			bytesperline = f->fmt.pix.width * 3 / 2;
+			break;
+		default:
+			/* Suppose it's YUV444 or 32bpp */
+			size = f->fmt.pix.width * f->fmt.pix.height * 4;
+			bytesperline = f->fmt.pix.width * 4;
+			pr_info("mxc_v4l2_s_fmt: default assume"
+				" to be YUV444 interleaved.\n");
+			break;
+		}
+
+		if (f->fmt.pix.bytesperline < bytesperline) {
+			f->fmt.pix.bytesperline = bytesperline;
+		} else {
+			bytesperline = f->fmt.pix.bytesperline;
+		}
+
+		if (f->fmt.pix.sizeimage > size) {
+			pr_debug("mxc_v4l2_s_fmt: sizeimage bigger than"
+				 " needed.\n");
+			size = f->fmt.pix.sizeimage;
+		}
+		f->fmt.pix.sizeimage = size;
+
+		cam->v2f.fmt.pix.sizeimage = size;
+		cam->v2f.fmt.pix.bytesperline = bytesperline;
+		cam->v2f.fmt.pix.width = f->fmt.pix.width;
+		cam->v2f.fmt.pix.height = f->fmt.pix.height;
+		cam->v2f.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
+		retval = 0;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		retval = verify_preview(cam, &f->fmt.win);
+		cam->win = f->fmt.win;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*!
+ * get control param
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_get_v42l_control(cam_data *cam, struct v4l2_control *c)
+{
+	int status = 0;
+
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		c->value = cam->rotation;
+		break;
+	case V4L2_CID_VFLIP:
+		c->value = cam->rotation;
+		break;
+	case V4L2_CID_MXC_ROT:
+		c->value = cam->rotation;
+		break;
+	case V4L2_CID_BRIGHTNESS:
+		c->value = cam->bright;
+		break;
+	case V4L2_CID_HUE:
+		c->value = cam->hue;
+		break;
+	case V4L2_CID_CONTRAST:
+		c->value = cam->contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		c->value = cam->saturation;
+		break;
+	case V4L2_CID_RED_BALANCE:
+		c->value = cam->red;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		c->value = cam->blue;
+		break;
+	case V4L2_CID_BLACK_LEVEL:
+		c->value = cam->ae_mode;
+		break;
+	default:
+		status = -EINVAL;
+	}
+	return status;
+}
+
+/*!
+ * V4L2 - set_control function
+ * V4L2_CID_MXC_ROT is the extention for rotation/mirroring.
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_set_v42l_control(cam_data *cam, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		if (c->value == 1) {
+			if ((cam->rotation != V4L2_MXC_ROTATE_VERT_FLIP) &&
+			    (cam->rotation != V4L2_MXC_ROTATE_180))
+				cam->rotation = V4L2_MXC_ROTATE_HORIZ_FLIP;
+			else
+				cam->rotation = V4L2_MXC_ROTATE_180;
+		} else {
+			if (cam->rotation == V4L2_MXC_ROTATE_HORIZ_FLIP)
+				cam->rotation = V4L2_MXC_ROTATE_NONE;
+			else if (cam->rotation == V4L2_MXC_ROTATE_180)
+				cam->rotation = V4L2_MXC_ROTATE_VERT_FLIP;
+		}
+		break;
+	case V4L2_CID_VFLIP:
+		if (c->value == 1) {
+			if ((cam->rotation != V4L2_MXC_ROTATE_HORIZ_FLIP) &&
+			    (cam->rotation != V4L2_MXC_ROTATE_180))
+				cam->rotation = V4L2_MXC_ROTATE_VERT_FLIP;
+			else
+				cam->rotation = V4L2_MXC_ROTATE_180;
+		} else {
+			if (cam->rotation == V4L2_MXC_ROTATE_VERT_FLIP)
+				cam->rotation = V4L2_MXC_ROTATE_NONE;
+			if (cam->rotation == V4L2_MXC_ROTATE_180)
+				cam->rotation = V4L2_MXC_ROTATE_HORIZ_FLIP;
+		}
+		break;
+	case V4L2_CID_MXC_ROT:
+		switch (c->value) {
+		case V4L2_MXC_ROTATE_NONE:
+		case V4L2_MXC_ROTATE_VERT_FLIP:
+		case V4L2_MXC_ROTATE_HORIZ_FLIP:
+		case V4L2_MXC_ROTATE_180:
+		case V4L2_MXC_ROTATE_90_RIGHT:
+		case V4L2_MXC_ROTATE_90_RIGHT_VFLIP:
+		case V4L2_MXC_ROTATE_90_RIGHT_HFLIP:
+		case V4L2_MXC_ROTATE_90_LEFT:
+			cam->rotation = c->value;
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	case V4L2_CID_HUE:
+		cam->hue = c->value;
+		break;
+	case V4L2_CID_CONTRAST:
+		cam->contrast = c->value;
+		break;
+	case V4L2_CID_BRIGHTNESS:
+		cam->bright = c->value;
+	case V4L2_CID_SATURATION:
+		cam->saturation = c->value;
+	case V4L2_CID_RED_BALANCE:
+		cam->red = c->value;
+	case V4L2_CID_BLUE_BALANCE:
+		cam->blue = c->value;
+		csi_enable_mclk(CSI_MCLK_I2C, true, true);
+		cam->cam_sensor->set_color(cam->bright, cam->saturation,
+					   cam->red, cam->green, cam->blue);
+		csi_enable_mclk(CSI_MCLK_I2C, false, false);
+		break;
+	case V4L2_CID_BLACK_LEVEL:
+		cam->ae_mode = c->value & 0x03;
+		csi_enable_mclk(CSI_MCLK_I2C, true, true);
+		if (cam->cam_sensor->set_ae_mode)
+			cam->cam_sensor->set_ae_mode(cam->ae_mode);
+		csi_enable_mclk(CSI_MCLK_I2C, false, false);
+		break;
+	case V4L2_CID_MXC_FLASH:
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_s_param function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param parm        structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
+{
+	sensor_interface *param;
+	csi_signal_cfg_t csi_param;
+
+	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		pr_debug("mxc_v4l2_s_param invalid type\n");
+		return -EINVAL;
+	}
+
+	if (parm->parm.capture.timeperframe.denominator >
+	    cam->standard.frameperiod.denominator) {
+		pr_debug("mxc_v4l2_s_param frame rate %d larger "
+			 "than standard supported %d\n",
+			 parm->parm.capture.timeperframe.denominator,
+			 cam->standard.frameperiod.denominator);
+		return -EINVAL;
+	}
+
+	cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+
+	csi_enable_mclk(CSI_MCLK_I2C, true, true);
+	param = cam->cam_sensor->config
+	    (&parm->parm.capture.timeperframe.denominator,
+	     parm->parm.capture.capturemode);
+	csi_enable_mclk(CSI_MCLK_I2C, false, false);
+
+	cam->streamparm.parm.capture.timeperframe =
+	    parm->parm.capture.timeperframe;
+
+	if ((parm->parm.capture.capturemode != 0) &&
+	    (parm->parm.capture.capturemode != V4L2_MODE_HIGHQUALITY)) {
+		pr_debug("mxc_v4l2_s_param frame un-supported capture mode\n");
+		return -EINVAL;
+	}
+
+	if (parm->parm.capture.capturemode ==
+	    cam->streamparm.parm.capture.capturemode) {
+		return 0;
+	}
+
+	/* resolution changed, so need to re-program the CSI */
+	csi_param.sens_clksrc = 0;
+	csi_param.clk_mode = param->clk_mode;
+	csi_param.pixclk_pol = param->pixclk_pol;
+	csi_param.data_width = param->data_width;
+	csi_param.data_pol = param->data_pol;
+	csi_param.ext_vsync = param->ext_vsync;
+	csi_param.Vsync_pol = param->Vsync_pol;
+	csi_param.Hsync_pol = param->Hsync_pol;
+	csi_init_interface(param->width, param->height, param->pixel_fmt,
+			   csi_param);
+
+	if (parm->parm.capture.capturemode != V4L2_MODE_HIGHQUALITY) {
+		cam->streamparm.parm.capture.capturemode = 0;
+	} else {
+		cam->streamparm.parm.capture.capturemode =
+		    V4L2_MODE_HIGHQUALITY;
+		cam->streamparm.parm.capture.extendedmode =
+		    parm->parm.capture.extendedmode;
+		cam->streamparm.parm.capture.readbuffers = 1;
+	}
+	return 0;
+}
+
+/*!
+ * Dequeue one V4L capture buffer
+ *
+ * @param cam         structure cam_data *
+ * @param buf         structure v4l2_buffer *
+ *
+ * @return  status    0 success, EINVAL invalid frame number,
+ *                    ETIME timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
+{
+	int retval = 0;
+	struct mxc_v4l_frame *frame;
+
+	if (!wait_event_interruptible_timeout(cam->enc_queue,
+					      cam->enc_counter != 0, 10 * HZ)) {
+		printk(KERN_ERR "mxc_v4l_dqueue timeout enc_counter %x\n",
+		       cam->enc_counter);
+		return -ETIME;
+	} else if (signal_pending(current)) {
+		printk(KERN_ERR "mxc_v4l_dqueue() interrupt received\n");
+		return -ERESTARTSYS;
+	}
+
+	cam->enc_counter--;
+
+	frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
+	list_del(cam->done_q.next);
+	if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
+	} else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+		printk(KERN_ERR "VIDIOC_DQBUF: Buffer not filled.\n");
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+		retval = -EINVAL;
+	} else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
+		printk(KERN_ERR "VIDIOC_DQBUF: Buffer not queued.\n");
+		retval = -EINVAL;
+	}
+
+	buf->bytesused = cam->v2f.fmt.pix.sizeimage;
+	buf->index = frame->index;
+	buf->flags = frame->buffer.flags;
+
+	return retval;
+}
+
+/*!
+ * V4L interface - open function
+ *
+ * @param inode        structure inode *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l_open(struct inode *inode, struct file *file)
+{
+	sensor_interface *param;
+	csi_signal_cfg_t csi_param;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int err = 0;
+
+	if (!cam) {
+		pr_info("Internal error, cam_data not found!\n");
+		return -ENODEV;
+	}
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	if (signal_pending(current))
+		goto oops;
+
+	if (cam->open_count++ == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+
+		err = prp_enc_select(cam);
+
+		cam->enc_counter = 0;
+		cam->skip_frame = 0;
+		INIT_LIST_HEAD(&cam->ready_q);
+		INIT_LIST_HEAD(&cam->working_q);
+		INIT_LIST_HEAD(&cam->done_q);
+
+		csi_enable_mclk(CSI_MCLK_I2C, true, true);
+		param = cam->cam_sensor->reset();
+		if (param == NULL) {
+			cam->open_count--;
+			csi_enable_mclk(CSI_MCLK_I2C, false, false);
+			err = -ENODEV;
+			goto oops;
+		}
+		csi_param.sens_clksrc = 0;
+		csi_param.clk_mode = param->clk_mode;
+		csi_param.pixclk_pol = param->pixclk_pol;
+		csi_param.data_width = param->data_width;
+		csi_param.data_pol = param->data_pol;
+		csi_param.ext_vsync = param->ext_vsync;
+		csi_param.Vsync_pol = param->Vsync_pol;
+		csi_param.Hsync_pol = param->Hsync_pol;
+		csi_init_interface(param->width, param->height,
+				   param->pixel_fmt, csi_param);
+		cam->cam_sensor->get_color(&cam->bright, &cam->saturation,
+					   &cam->red, &cam->green, &cam->blue);
+		if (cam->cam_sensor->get_ae_mode)
+			cam->cam_sensor->get_ae_mode(&cam->ae_mode);
+		csi_enable_mclk(CSI_MCLK_I2C, false, false);
+		prp_init(cam);
+
+	}
+
+	file->private_data = dev;
+      oops:
+	up(&cam->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L interface - close function
+ *
+ * @param inode    struct inode *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int mxc_v4l_close(struct inode *inode, struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	int err = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	/* for the case somebody hit the ctrl C */
+	if (cam->overlay_pid == current->pid) {
+		err = stop_preview(cam);
+		cam->overlay_on = false;
+	}
+	if (cam->capture_pid == current->pid) {
+		err |= mxc_streamoff(cam);
+		cam->capture_on = false;
+		wake_up_interruptible(&cam->enc_queue);
+	}
+
+	if (--cam->open_count == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+		pr_debug("mxc_v4l_close: release resource\n");
+
+		err |= prp_enc_deselect(cam);
+
+		mxc_free_frame_buf(cam);
+		file->private_data = NULL;
+
+		/* capture off */
+		wake_up_interruptible(&cam->enc_queue);
+		mxc_free_frames(cam);
+		cam->enc_counter++;
+		prp_exit(cam);
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_VIDEO_MXC_CSI_DMA
+#include <mach/dma.h>
+
+#define CSI_DMA_STATUS_IDLE	0	/* DMA is not started */
+#define CSI_DMA_STATUS_WORKING	1	/* DMA is transfering the data */
+#define CSI_DMA_STATUS_DONE	2	/* One frame completes successfully */
+#define CSI_DMA_STATUS_ERROR	3	/* Error occurs during the DMA */
+
+/*
+ * Sometimes the start of the DMA is not synchronized with the CSI
+ * SOF (Start of Frame) interrupt which will lead to incorrect
+ * captured image. In this case the driver will re-try capturing
+ * another frame. The following macro defines the maximum re-try
+ * times.
+ */
+#define CSI_DMA_RETRY		8
+
+/*
+ * Size of the physical contiguous memory area used to hold image data
+ * transfered by DMA. It can be less than the size of the image data.
+ */
+#define CSI_MEM_SIZE		(1024 * 600)
+
+/* Number of bytes for one DMA transfer */
+#define CSI_DMA_LENGTH		(1024 * 200)
+
+static int g_dma_channel;
+static int g_dma_status = CSI_DMA_STATUS_DONE;
+static volatile int g_dma_completed;	/* number of completed DMA transfers */
+static volatile int g_dma_copied;	/* number of copied DMA transfers */
+static struct tasklet_struct g_dma_tasklet;
+static char *g_user_buf;	/* represents the buf passed by read() */
+static int g_user_count;	/* represents the count passed by read() */
+
+/*!
+ * @brief setup the DMA to transfer data
+ *	  There may be more than one DMA to transfer the whole image. Those
+ *	  DMAs work like chain. This function is used to setup the DMA in
+ *	  case there is enough space to hold the data.
+ * @param	data	pointer to the cam structure
+ */
+static void mxc_csi_dma_chaining(void *data)
+{
+	cam_data *cam = (cam_data *) data;
+	int count, chained = 0;
+	int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH;
+	mxc_dma_requestbuf_t dma_request;
+
+	while (chained * CSI_DMA_LENGTH < g_user_count) {
+		/*
+		 * Calculate how many bytes the DMA should transfer. It may
+		 * be less than CSI_DMA_LENGTH if the DMA is the last one.
+		 */
+		if ((chained + 1) * CSI_DMA_LENGTH > g_user_count)
+			count = g_user_count - chained * CSI_DMA_LENGTH;
+		else
+			count = CSI_DMA_LENGTH;
+		pr_debug("%s() DMA chained count = %d\n", __FUNCTION__, count);
+
+		/* Config DMA */
+		memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t));
+		dma_request.dst_addr = cam->still_buf[0]
+		    + (chained % max_dma) * CSI_DMA_LENGTH;
+		dma_request.src_addr = (dma_addr_t) CSI_CSIRXFIFO_PHYADDR;
+		dma_request.num_of_bytes = count;
+		mxc_dma_config(g_dma_channel, &dma_request, 1,
+			       MXC_DMA_MODE_READ);
+
+		chained++;
+	}
+}
+
+/*!
+ * @brief Copy image data from physical contiguous memory to user space buffer
+ *	  Once the data are copied, there will be more spare space in the
+ *	  physical contiguous memory to receive data from DMA.
+ * @param	data	pointer to the cam structure
+ */
+static void mxc_csi_dma_task(unsigned long data)
+{
+	cam_data *cam = (cam_data *) data;
+	int count;
+	int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH;
+
+	while (g_dma_copied < g_dma_completed) {
+		/*
+		 * Calculate how many bytes the DMA has transfered. It may
+		 * be less than CSI_DMA_LENGTH if the DMA is the last one.
+		 */
+		if ((g_dma_copied + 1) * CSI_DMA_LENGTH > g_user_count)
+			count = g_user_count - g_dma_copied * CSI_DMA_LENGTH;
+		else
+			count = CSI_DMA_LENGTH;
+		if (copy_to_user(g_user_buf + g_dma_copied * CSI_DMA_LENGTH,
+				 cam->still_buf_vaddr + (g_dma_copied % max_dma)
+				 * CSI_DMA_LENGTH, count))
+			pr_debug("Warning: some bytes not copied\n");
+
+		g_dma_copied++;
+	}
+
+	/* If the whole image has been captured */
+	if (g_dma_copied * CSI_DMA_LENGTH >= g_user_count) {
+		cam->still_counter++;
+		wake_up_interruptible(&cam->still_queue);
+	}
+
+	pr_debug("%s() DMA completed = %d copied = %d\n",
+		 __FUNCTION__, g_dma_completed, g_dma_copied);
+}
+
+/*!
+ * @brief DMA interrupt callback function
+ * @param	data	pointer to the cam structure
+ * @param	error	DMA error flag
+ * @param	count	number of bytes transfered by the DMA
+ */
+static void mxc_csi_dma_callback(void *data, int error, unsigned int count)
+{
+	cam_data *cam = (cam_data *) data;
+	int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&cam->int_lock, lock_flags);
+
+	g_dma_completed++;
+
+	if (error != MXC_DMA_DONE) {
+		g_dma_status = CSI_DMA_STATUS_ERROR;
+		pr_debug("%s() DMA error\n", __FUNCTION__);
+	}
+
+	/* If the whole image has been captured */
+	if ((g_dma_status != CSI_DMA_STATUS_ERROR)
+	    && (g_dma_completed * CSI_DMA_LENGTH >= g_user_count))
+		g_dma_status = CSI_DMA_STATUS_DONE;
+
+	if ((g_dma_status == CSI_DMA_STATUS_WORKING) &&
+	    (g_dma_completed >= g_dma_copied + max_dma)) {
+		g_dma_status = CSI_DMA_STATUS_ERROR;
+		pr_debug("%s() Previous buffer over written\n", __FUNCTION__);
+	}
+
+	/* Schedule the tasklet */
+	tasklet_schedule(&g_dma_tasklet);
+
+	spin_unlock_irqrestore(&cam->int_lock, lock_flags);
+
+	pr_debug("%s() count = %d bytes\n", __FUNCTION__, count);
+}
+
+/*!
+ * @brief CSI interrupt callback function
+ * @param	data	pointer to the cam structure
+ * @param	status	CSI interrupt status
+ */
+static void mxc_csi_irq_callback(void *data, unsigned long status)
+{
+	cam_data *cam = (cam_data *) data;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&cam->int_lock, lock_flags);
+
+	/* Wait for SOF (Start of Frame) interrupt to sync the image */
+	if (status & BIT_SOF_INT) {
+		if (g_dma_status == CSI_DMA_STATUS_IDLE) {
+			/* Start DMA transfer to capture image */
+			mxc_dma_enable(g_dma_channel);
+			g_dma_status = CSI_DMA_STATUS_WORKING;
+			pr_debug("%s() DMA started.\n", __FUNCTION__);
+		} else if (g_dma_status == CSI_DMA_STATUS_WORKING) {
+			/*
+			 * Another SOF occurs during DMA transfer. In this
+			 * case the image is not synchronized so need to
+			 * report error and probably try again.
+			 */
+			g_dma_status = CSI_DMA_STATUS_ERROR;
+			pr_debug("%s() Image is not synchronized with DMA - "
+				 "SOF before DMA completes\n", __FUNCTION__);
+		}
+	}
+
+	spin_unlock_irqrestore(&cam->int_lock, lock_flags);
+
+	pr_debug("%s() g_dma_status = %d\n", __FUNCTION__, g_dma_status);
+}
+
+/*!
+ * V4L interface - read function
+ *
+ * @param file       struct file *
+ * @param read buf   char *
+ * @param count      size_t
+ * @param ppos       structure loff_t *
+ *
+ * @return           bytes read
+ */
+static ssize_t
+mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
+{
+	int err = 0;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int retry = CSI_DMA_RETRY;
+
+	g_user_buf = buf;
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	/* Video capture and still image capture are exclusive */
+	if (cam->capture_on == true) {
+		err = -EBUSY;
+		goto exit0;
+	}
+
+	/* The CSI-DMA can not do CSC */
+	if (cam->v2f.fmt.pix.pixelformat != V4L2_PIX_FMT_YUYV) {
+		pr_info("mxc_v4l_read support YUYV pixel format only\n");
+		err = -EINVAL;
+		goto exit0;
+	}
+
+	/* The CSI-DMA can not do resize or crop */
+	if ((cam->v2f.fmt.pix.width != cam->crop_bounds.width)
+	    || (cam->v2f.fmt.pix.height != cam->crop_bounds.height)) {
+		pr_info("mxc_v4l_read resize is not supported\n");
+		pr_info("supported image size width = %d height = %d\n",
+			cam->crop_bounds.width, cam->crop_bounds.height);
+		err = -EINVAL;
+		goto exit0;
+	}
+	if ((cam->crop_current.left != cam->crop_bounds.left)
+	    || (cam->crop_current.width != cam->crop_bounds.width)
+	    || (cam->crop_current.top != cam->crop_bounds.top)
+	    || (cam->crop_current.height != cam->crop_bounds.height)) {
+		pr_info("mxc_v4l_read cropping is not supported\n");
+		err = -EINVAL;
+		goto exit0;
+	}
+
+	cam->still_buf_vaddr = dma_alloc_coherent(0,
+						  PAGE_ALIGN(CSI_MEM_SIZE),
+						  &cam->still_buf[0],
+						  GFP_DMA | GFP_KERNEL);
+
+	if (!cam->still_buf_vaddr) {
+		pr_info("mxc_v4l_read failed at allocate still_buf\n");
+		err = -ENOBUFS;
+		goto exit0;
+	}
+
+	/* Initialize DMA */
+	g_dma_channel = mxc_dma_request(MXC_DMA_CSI_RX, "CSI RX DMA");
+	if (g_dma_channel < 0) {
+		pr_debug("mxc_v4l_read failed to request DMA channel\n");
+		err = -EIO;
+		goto exit1;
+	}
+
+	err = mxc_dma_callback_set(g_dma_channel,
+				   (mxc_dma_callback_t) mxc_csi_dma_callback,
+				   (void *)cam);
+	if (err != 0) {
+		pr_debug("mxc_v4l_read failed to set DMA callback\n");
+		err = -EIO;
+		goto exit2;
+	}
+
+	g_user_buf = buf;
+	if (cam->v2f.fmt.pix.sizeimage < count)
+		g_user_count = cam->v2f.fmt.pix.sizeimage;
+	else
+		g_user_count = count & ~0x3;
+
+	tasklet_init(&g_dma_tasklet, mxc_csi_dma_task, (unsigned long)cam);
+	g_dma_status = CSI_DMA_STATUS_DONE;
+	csi_set_callback(mxc_csi_irq_callback, cam);
+	csi_enable_prpif(0);
+
+	/* clear current SOF first */
+	csi_clear_status(BIT_SOF_INT);
+	csi_enable_mclk(CSI_MCLK_RAW, true, true);
+
+	do {
+		g_dma_completed = g_dma_copied = 0;
+		mxc_csi_dma_chaining(cam);
+		cam->still_counter = 0;
+		g_dma_status = CSI_DMA_STATUS_IDLE;
+
+		if (!wait_event_interruptible_timeout(cam->still_queue,
+						      cam->still_counter != 0,
+						      10 * HZ)) {
+			pr_info("mxc_v4l_read timeout counter %x\n",
+				cam->still_counter);
+			err = -ETIME;
+			goto exit3;
+		}
+
+		if (g_dma_status == CSI_DMA_STATUS_DONE)
+			break;
+
+		if (retry-- == 0)
+			break;
+
+		pr_debug("Now retry image capture\n");
+	} while (1);
+
+	if (g_dma_status != CSI_DMA_STATUS_DONE)
+		err = -EIO;
+
+      exit3:
+	csi_enable_prpif(1);
+	g_dma_status = CSI_DMA_STATUS_DONE;
+	csi_set_callback(0, 0);
+	csi_enable_mclk(CSI_MCLK_RAW, false, false);
+	tasklet_kill(&g_dma_tasklet);
+
+      exit2:
+	mxc_dma_free(g_dma_channel);
+
+      exit1:
+	dma_free_coherent(0, PAGE_ALIGN(CSI_MEM_SIZE),
+			  cam->still_buf_vaddr, cam->still_buf[0]);
+	cam->still_buf[0] = 0;
+
+      exit0:
+	up(&cam->busy_lock);
+	if (err < 0)
+		return err;
+	else
+		return g_user_count;
+}
+#else
+/*!
+ * V4L interface - read function
+ *
+ * @param file       struct file *
+ * @param read buf   char *
+ * @param count      size_t
+ * @param ppos       structure loff_t *
+ *
+ * @return           bytes read
+ */
+static ssize_t
+mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos)
+{
+	int err = 0;
+	u8 *v_address;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	/* Video capture and still image capture are exclusive */
+	if (cam->capture_on == true) {
+		err = -EBUSY;
+		goto exit0;
+	}
+
+	v_address = dma_alloc_coherent(0,
+				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				       &cam->still_buf[0],
+				       GFP_DMA | GFP_KERNEL);
+
+	if (!v_address) {
+		pr_info("mxc_v4l_read failed at allocate still_buf\n");
+		err = -ENOBUFS;
+		goto exit0;
+	}
+
+	if (prp_still_select(cam)) {
+		err = -EIO;
+		goto exit1;
+	}
+
+	cam->still_counter = 0;
+	if (cam->csi_start(cam)) {
+		err = -EIO;
+		goto exit2;
+	}
+
+	if (!wait_event_interruptible_timeout(cam->still_queue,
+					      cam->still_counter != 0,
+					      10 * HZ)) {
+		pr_info("mxc_v4l_read timeout counter %x\n",
+			cam->still_counter);
+		err = -ETIME;
+		goto exit2;
+	}
+	err = copy_to_user(buf, v_address, cam->v2f.fmt.pix.sizeimage);
+
+      exit2:
+	prp_still_deselect(cam);
+
+      exit1:
+	dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address,
+			  cam->still_buf[0]);
+	cam->still_buf[0] = 0;
+
+      exit0:
+	up(&cam->busy_lock);
+	if (err < 0)
+		return err;
+	else
+		return (cam->v2f.fmt.pix.sizeimage - err);
+}
+#endif				/* CONFIG_VIDEO_MXC_CSI_DMA */
+
+/*!
+ * V4L interface - ioctl function
+ *
+ * @param inode      struct inode *
+ *
+ * @param file       struct file *
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void *
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static int
+mxc_v4l_do_ioctl(struct inode *inode, struct file *file,
+		 unsigned int ioctlnr, void *arg)
+{
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int retval = 0;
+	unsigned long lock_flags;
+
+	if (!cam)
+		return -EBADF;
+
+	wait_event_interruptible(cam->power_queue, cam->low_power == false);
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+		/*!
+		 * V4l2 VIDIOC_QUERYCAP ioctl
+		 */
+	case VIDIOC_QUERYCAP:{
+			struct v4l2_capability *cap = arg;
+			strcpy(cap->driver, "mxc_v4l2");
+			cap->version = KERNEL_VERSION(0, 1, 11);
+			cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
+			    V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_STREAMING
+			    | V4L2_CAP_READWRITE;
+			cap->card[0] = '\0';
+			cap->bus_info[0] = '\0';
+			retval = 0;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_G_FMT ioctl
+		 */
+	case VIDIOC_G_FMT:{
+			struct v4l2_format *gf = arg;
+			retval = mxc_v4l2_g_fmt(cam, gf);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_FMT ioctl
+		 */
+	case VIDIOC_S_FMT:{
+			struct v4l2_format *sf = arg;
+			retval = mxc_v4l2_s_fmt(cam, sf);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_REQBUFS ioctl
+		 */
+	case VIDIOC_REQBUFS:{
+			struct v4l2_requestbuffers *req = arg;
+			if (req->count > FRAME_NUM) {
+				pr_info("VIDIOC_REQBUFS: not enough buffer\n");
+				req->count = FRAME_NUM;
+			}
+
+			if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
+			    (req->memory != V4L2_MEMORY_MMAP)) {
+				pr_debug("VIDIOC_REQBUFS: wrong buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			mxc_streamoff(cam);
+			mxc_free_frame_buf(cam);
+
+			retval = mxc_allocate_frame_buf(cam, req->count);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_QUERYBUF ioctl
+		 */
+	case VIDIOC_QUERYBUF:{
+			struct v4l2_buffer *buf = arg;
+			int index = buf->index;
+
+			if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+				pr_debug
+				    ("VIDIOC_QUERYBUFS: wrong buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			memset(buf, 0, sizeof(buf));
+			buf->index = index;
+
+			down(&cam->param_lock);
+			retval = mxc_v4l2_buffer_status(cam, buf);
+			up(&cam->param_lock);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_QBUF ioctl
+		 */
+	case VIDIOC_QBUF:{
+			struct v4l2_buffer *buf = arg;
+			int index = buf->index;
+
+			pr_debug("VIDIOC_QBUF: %d\n", buf->index);
+
+			spin_lock_irqsave(&cam->int_lock, lock_flags);
+			if ((cam->frame[index].buffer.flags & 0x7) ==
+			    V4L2_BUF_FLAG_MAPPED) {
+				cam->frame[index].buffer.flags |=
+				    V4L2_BUF_FLAG_QUEUED;
+				if (cam->skip_frame > 0) {
+					list_add_tail(&cam->frame[index].queue,
+						      &cam->working_q);
+					retval =
+					    cam->enc_update_eba(cam->
+								frame[index].
+								paddress,
+								&cam->
+								ping_pong_csi);
+					cam->skip_frame = 0;
+				} else {
+					list_add_tail(&cam->frame[index].queue,
+						      &cam->ready_q);
+				}
+			} else if (cam->frame[index].buffer.flags &
+				   V4L2_BUF_FLAG_QUEUED) {
+				pr_debug
+				    ("VIDIOC_QBUF: buffer already queued\n");
+			} else if (cam->frame[index].buffer.
+				   flags & V4L2_BUF_FLAG_DONE) {
+				pr_debug
+				    ("VIDIOC_QBUF: overwrite done buffer.\n");
+				cam->frame[index].buffer.flags &=
+				    ~V4L2_BUF_FLAG_DONE;
+				cam->frame[index].buffer.flags |=
+				    V4L2_BUF_FLAG_QUEUED;
+			}
+			buf->flags = cam->frame[index].buffer.flags;
+			spin_unlock_irqrestore(&cam->int_lock, lock_flags);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_DQBUF ioctl
+		 */
+	case VIDIOC_DQBUF:{
+			struct v4l2_buffer *buf = arg;
+
+			retval = mxc_v4l_dqueue(cam, buf);
+
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_STREAMON ioctl
+		 */
+	case VIDIOC_STREAMON:{
+			cam->capture_on = true;
+			retval = mxc_streamon(cam);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_STREAMOFF ioctl
+		 */
+	case VIDIOC_STREAMOFF:{
+			retval = mxc_streamoff(cam);
+			cam->capture_on = false;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_G_CTRL ioctl
+		 */
+	case VIDIOC_G_CTRL:{
+			retval = mxc_get_v42l_control(cam, arg);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_CTRL ioctl
+		 */
+	case VIDIOC_S_CTRL:{
+			retval = mxc_set_v42l_control(cam, arg);
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_CROPCAP ioctl
+		 */
+	case VIDIOC_CROPCAP:{
+			struct v4l2_cropcap *cap = arg;
+
+			if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+			    cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+				retval = -EINVAL;
+				break;
+			}
+			cap->bounds = cam->crop_bounds;
+			cap->defrect = cam->crop_defrect;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_G_CROP ioctl
+		 */
+	case VIDIOC_G_CROP:{
+			struct v4l2_crop *crop = arg;
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+			    crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+				retval = -EINVAL;
+				break;
+			}
+			crop->c = cam->crop_current;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_CROP ioctl
+		 */
+	case VIDIOC_S_CROP:{
+			struct v4l2_crop *crop = arg;
+			struct v4l2_rect *b = &cam->crop_bounds;
+			int i;
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+			    crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+				retval = -EINVAL;
+				break;
+			}
+
+			crop->c.top = (crop->c.top < b->top) ? b->top
+			    : crop->c.top;
+			if (crop->c.top > b->top + b->height)
+				crop->c.top = b->top + b->height - 1;
+			if (crop->c.height > b->top + b->height - crop->c.top)
+				crop->c.height =
+				    b->top + b->height - crop->c.top;
+
+			crop->c.left = (crop->c.left < b->left) ? b->left
+			    : crop->c.left;
+			if (crop->c.left > b->left + b->width)
+				crop->c.left = b->left + b->width - 1;
+			if (crop->c.width > b->left - crop->c.left + b->width)
+				crop->c.width =
+				    b->left - crop->c.left + b->width;
+
+			crop->c.width &= ~0x1;
+
+			/*
+			 * MX27 PrP limitation:
+			 * The right spare space (CSI_FRAME_X_SIZE
+			 *  - SOURCE_LINE_STRIDE - PICTURE_X_SIZE)) must be
+			 * multiple of 32.
+			 * So we tune the crop->c.left value to the closest
+			 * desired cropping value and meet the PrP requirement.
+			 */
+			i = ((b->left + b->width)
+			     - (crop->c.left + crop->c.width)) % 32;
+			if (i <= 16) {
+				if (crop->c.left + crop->c.width + i
+				    <= b->left + b->width)
+					crop->c.left += i;
+				else if (crop->c.left - (32 - i) >= b->left)
+					crop->c.left -= 32 - i;
+				else {
+					retval = -EINVAL;
+					break;
+				}
+			} else {
+				if (crop->c.left - (32 - i) >= b->left)
+					crop->c.left -= 32 - i;
+				else if (crop->c.left + crop->c.width + i
+					 <= b->left + b->width)
+					crop->c.left += i;
+				else {
+					retval = -EINVAL;
+					break;
+				}
+			}
+
+			cam->crop_current = crop->c;
+
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_OVERLAY ioctl
+		 */
+	case VIDIOC_OVERLAY:{
+			int *on = arg;
+			if (*on) {
+				cam->overlay_on = true;
+				retval = start_preview(cam);
+			}
+			if (!*on) {
+				retval = stop_preview(cam);
+				cam->overlay_on = false;
+			}
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_G_FBUF ioctl
+		 */
+	case VIDIOC_G_FBUF:{
+			struct v4l2_framebuffer *fb = arg;
+			struct fb_var_screeninfo *var;
+
+			if (cam->output >= num_registered_fb) {
+				retval = -EINVAL;
+				break;
+			}
+
+			var = &registered_fb[cam->output]->var;
+			cam->v4l2_fb.fmt.width = var->xres;
+			cam->v4l2_fb.fmt.height = var->yres;
+			cam->v4l2_fb.fmt.bytesperline =
+			    var->xres_virtual * var->bits_per_pixel;
+			cam->v4l2_fb.fmt.colorspace = V4L2_COLORSPACE_SRGB;
+			*fb = cam->v4l2_fb;
+			break;
+		}
+
+		/*!
+		 * V4l2 VIDIOC_S_FBUF ioctl
+		 */
+	case VIDIOC_S_FBUF:{
+			struct v4l2_framebuffer *fb = arg;
+			cam->v4l2_fb.flags = fb->flags;
+			cam->v4l2_fb.fmt.pixelformat = fb->fmt.pixelformat;
+			break;
+		}
+
+	case VIDIOC_G_PARM:{
+			struct v4l2_streamparm *parm = arg;
+			if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+				pr_debug("VIDIOC_G_PARM invalid type\n");
+				retval = -EINVAL;
+				break;
+			}
+			parm->parm.capture = cam->streamparm.parm.capture;
+			break;
+		}
+	case VIDIOC_S_PARM:{
+			struct v4l2_streamparm *parm = arg;
+			retval = mxc_v4l2_s_param(cam, parm);
+			break;
+		}
+
+		/* linux v4l2 bug, kernel c0485619 user c0405619 */
+	case VIDIOC_ENUMSTD:{
+			struct v4l2_standard *e = arg;
+			*e = cam->standard;
+			pr_debug("VIDIOC_ENUMSTD call\n");
+			retval = 0;
+			break;
+		}
+
+	case VIDIOC_G_STD:{
+			v4l2_std_id *e = arg;
+			*e = cam->standard.id;
+			break;
+		}
+
+	case VIDIOC_S_STD:{
+			break;
+		}
+
+	case VIDIOC_ENUMOUTPUT:
+		{
+			struct v4l2_output *output = arg;
+
+			if (output->index >= num_registered_fb) {
+				retval = -EINVAL;
+				break;
+			}
+
+			strncpy(output->name,
+				registered_fb[output->index]->fix.id, 31);
+			output->type = V4L2_OUTPUT_TYPE_ANALOG;
+			output->audioset = 0;
+			output->modulator = 0;
+			output->std = V4L2_STD_UNKNOWN;
+
+			break;
+		}
+	case VIDIOC_G_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			*p_output_num = cam->output;
+			break;
+		}
+	case VIDIOC_S_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			if (*p_output_num >= num_registered_fb) {
+				retval = -EINVAL;
+				break;
+			}
+
+			cam->output = *p_output_num;
+			break;
+		}
+
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_ENUMINPUT:
+	case VIDIOC_G_INPUT:
+	case VIDIOC_S_INPUT:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&cam->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L interface - ioctl function
+ *
+ * @return  None
+ */
+static int
+mxc_v4l_ioctl(struct inode *inode, struct file *file,
+	      unsigned int cmd, unsigned long arg)
+{
+	return video_usercopy(inode, file, cmd, arg, mxc_v4l_do_ioctl);
+}
+
+/*!
+ * V4L interface - mmap function
+ *
+ * @param file        structure file *
+ *
+ * @param vma         structure vm_area_struct *
+ *
+ * @return status     0 Success, EINTR busy lock error, ENOBUFS remap_page error
+ */
+static int mxc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *dev = video_devdata(file);
+	unsigned long size;
+	int res = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	pr_debug("pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		 vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	size = vma->vm_end - vma->vm_start;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		pr_debug("mxc_mmap: remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+      mxc_mmap_exit:
+	up(&cam->busy_lock);
+	return res;
+}
+
+/*!
+ * V4L interface - poll function
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_poll(struct file *file, poll_table * wait)
+{
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	queue = &cam->enc_queue;
+	poll_wait(file, queue, wait);
+
+	up(&cam->busy_lock);
+	return res;
+}
+
+static struct
+file_operations mxc_v4l_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_v4l_open,
+	.release = mxc_v4l_close,
+	.read = mxc_v4l_read,
+	.ioctl = mxc_v4l_ioctl,
+	.mmap = mxc_mmap,
+	.poll = mxc_poll,
+};
+
+static struct video_device mxc_v4l_template = {
+	.name = "Mxc Camera",
+	.vfl_type = VID_TYPE_CAPTURE,
+	.fops = &mxc_v4l_fops,
+	.release = video_device_release,
+};
+
+static void camera_platform_release(struct device *device)
+{
+}
+
+/*! Device Definition for Mt9v111 devices */
+static struct platform_device mxc_v4l2_devices = {
+	.name = "mxc_v4l2",
+	.dev = {
+		.release = camera_platform_release,
+		},
+	.id = 0,
+};
+
+extern struct camera_sensor camera_sensor_if;
+
+/*!
+* Camera V4l2 callback function.
+*
+* @return status
+*/
+static void camera_callback(u32 mask, void *dev)
+{
+	struct mxc_v4l_frame *done_frame;
+	struct mxc_v4l_frame *ready_frame;
+
+	cam_data *cam = (cam_data *) dev;
+	if (cam == NULL)
+		return;
+
+	if (list_empty(&cam->working_q)) {
+		printk(KERN_ERR "camera_callback: working queue empty\n");
+		return;
+	}
+
+	done_frame =
+	    list_entry(cam->working_q.next, struct mxc_v4l_frame, queue);
+	if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+		done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
+		done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+
+		if (list_empty(&cam->ready_q)) {
+			cam->skip_frame++;
+		} else {
+			ready_frame =
+			    list_entry(cam->ready_q.next, struct mxc_v4l_frame,
+				       queue);
+			list_del(cam->ready_q.next);
+			list_add_tail(&ready_frame->queue, &cam->working_q);
+			cam->enc_update_eba(ready_frame->paddress,
+					    &cam->ping_pong_csi);
+		}
+
+		/* Added to the done queue */
+		list_del(cam->working_q.next);
+		list_add_tail(&done_frame->queue, &cam->done_q);
+
+		/* Wake up the queue */
+		cam->enc_counter++;
+		wake_up_interruptible(&cam->enc_queue);
+	} else {
+		printk(KERN_ERR "camera_callback :buffer not queued\n");
+	}
+}
+
+/*!
+ * initialize cam_data structure
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static void init_camera_struct(cam_data *cam)
+{
+	int i;
+
+	/* Default everything to 0 */
+	memset(cam, 0, sizeof(cam_data));
+
+	init_MUTEX(&cam->param_lock);
+	init_MUTEX(&cam->busy_lock);
+
+	cam->video_dev = video_device_alloc();
+	if (cam->video_dev == NULL)
+		return;
+
+	*(cam->video_dev) = mxc_v4l_template;
+
+	video_set_drvdata(cam->video_dev, cam);
+	dev_set_drvdata(&mxc_v4l2_devices.dev, (void *)cam);
+	cam->video_dev->minor = -1;
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		cam->frame[i].width = 0;
+		cam->frame[i].height = 0;
+		cam->frame[i].paddress = 0;
+	}
+
+	init_waitqueue_head(&cam->enc_queue);
+	init_waitqueue_head(&cam->still_queue);
+
+	/* setup cropping */
+	cam->crop_bounds.left = 0;
+	cam->crop_bounds.width = 640;
+	cam->crop_bounds.top = 0;
+	cam->crop_bounds.height = 480;
+	cam->crop_current = cam->crop_defrect = cam->crop_bounds;
+	cam->streamparm.parm.capture.capturemode = 0;
+
+	cam->standard.index = 0;
+	cam->standard.id = V4L2_STD_UNKNOWN;
+	cam->standard.frameperiod.denominator = 30;
+	cam->standard.frameperiod.numerator = 1;
+	cam->standard.framelines = 480;
+	cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
+	cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+	cam->overlay_on = false;
+	cam->capture_on = false;
+	cam->skip_frame = 0;
+	cam->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+	cam->v4l2_fb.flags = V4L2_FBUF_FLAG_PRIMARY;
+
+	cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2;
+	cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2;
+	cam->v2f.fmt.pix.width = 288;
+	cam->v2f.fmt.pix.height = 352;
+	cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
+	cam->win.w.width = 160;
+	cam->win.w.height = 160;
+	cam->win.w.left = 0;
+	cam->win.w.top = 0;
+
+	cam->cam_sensor = &camera_sensor_if;
+	cam->enc_callback = camera_callback;
+
+	init_waitqueue_head(&cam->power_queue);
+	cam->int_lock = __SPIN_LOCK_UNLOCKED(cam->int_lock);
+	spin_lock_init(&cam->int_lock);
+}
+
+extern void gpio_sensor_active(void);
+extern void gpio_sensor_inactive(void);
+
+/*!
+ * camera_power function
+ *    Turn Sensor power On/Off
+ *
+ * @param       cameraOn      true to turn camera on, otherwise shut down
+ *
+ * @return status
+ */
+static u8 camera_power(bool cameraOn)
+{
+	if (cameraOn == true) {
+		gpio_sensor_active();
+		csi_enable_mclk(csi_mclk_flag_backup, true, true);
+	} else {
+		csi_mclk_flag_backup = csi_read_mclk_flag();
+		csi_enable_mclk(csi_mclk_flag_backup, false, false);
+		gpio_sensor_inactive();
+	}
+	return 0;
+}
+
+/*!
+ * This function is called to put the sensor in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which I2C
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	if (cam == NULL) {
+		return -1;
+	}
+
+	cam->low_power = true;
+
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+	if ((cam->capture_on == true) && cam->enc_disable) {
+		cam->enc_disable(cam);
+	}
+	camera_power(false);
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the sensor back from a low power state.Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxc_v4l2_resume(struct platform_device *pdev)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	if (cam == NULL) {
+		return -1;
+	}
+
+	cam->low_power = false;
+	wake_up_interruptible(&cam->power_queue);
+
+	if (cam->overlay_on == true)
+		start_preview(cam);
+	if (cam->capture_on == true)
+		mxc_streamon(cam);
+	camera_power(true);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_v4l2_driver = {
+	.driver = {
+		   .name = "mxc_v4l2",
+		   .owner = THIS_MODULE,
+		   .bus = &platform_bus_type,
+		   },
+	.probe = NULL,
+	.remove = NULL,
+	.suspend = mxc_v4l2_suspend,
+	.resume = mxc_v4l2_resume,
+	.shutdown = NULL,
+};
+
+/*!
+ * Entry point for the V4L2
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int camera_init(void)
+{
+	u8 err = 0;
+	cam_data *cam;
+
+	g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
+	if (g_cam == NULL) {
+		pr_debug("failed to mxc_v4l_register_camera\n");
+		return -1;
+	}
+
+	cam = g_cam;
+	init_camera_struct(cam);
+
+	/* Register the I2C device */
+	err = platform_device_register(&mxc_v4l2_devices);
+	if (err != 0) {
+		pr_debug("camera_init: platform_device_register failed.\n");
+		video_device_release(cam->video_dev);
+		kfree(cam);
+		g_cam = NULL;
+	}
+
+	/* Register the device driver structure. */
+	err = platform_driver_register(&mxc_v4l2_driver);
+	if (err != 0) {
+		platform_device_unregister(&mxc_v4l2_devices);
+		pr_debug("camera_init: driver_register failed.\n");
+		video_device_release(cam->video_dev);
+		kfree(cam);
+		g_cam = NULL;
+		return err;
+	}
+
+	/* register v4l device */
+	if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr)
+	    == -1) {
+		platform_driver_unregister(&mxc_v4l2_driver);
+		platform_device_unregister(&mxc_v4l2_devices);
+		video_device_release(cam->video_dev);
+		kfree(cam);
+		g_cam = NULL;
+		pr_debug("video_register_device failed\n");
+		return -1;
+	}
+
+	return err;
+}
+
+/*!
+ * Exit and cleanup for the V4L2
+ *
+ */
+static void __exit camera_exit(void)
+{
+	pr_debug("unregistering video\n");
+
+	video_unregister_device(g_cam->video_dev);
+
+	platform_driver_unregister(&mxc_v4l2_driver);
+	platform_device_unregister(&mxc_v4l2_devices);
+
+	if (g_cam->open_count) {
+		pr_debug("camera open -- setting ops to NULL\n");
+	} else {
+		pr_debug("freeing camera\n");
+		mxc_free_frame_buf(g_cam);
+		kfree(g_cam);
+		g_cam = NULL;
+	}
+}
+
+module_init(camera_init);
+module_exit(camera_exit);
+
+module_param(video_nr, int, 0444);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/capture/fsl_csi.c b/drivers/media/video/mxc/capture/fsl_csi.c
new file mode 100644
index 000000000000..6dd0cc5a59d8
--- /dev/null
+++ b/drivers/media/video/mxc/capture/fsl_csi.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_csi.c, this file is derived from mx27_csi.c
+ *
+ * @brief mx25 CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+#include "mxc_v4l2_capture.h"
+#include "fsl_csi.h"
+
+static bool g_csi_mclk_on;
+static csi_irq_callback_t g_callback;
+static void *g_callback_data;
+static struct clk csi_mclk;
+
+static irqreturn_t csi_irq_handler(int irq, void *data)
+{
+	cam_data *cam = (cam_data *) data;
+	unsigned long status = __raw_readl(CSI_CSISR);
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+	unsigned int frame_count = (cr3 >> 16) & 0xFFFF;
+
+	__raw_writel(status, CSI_CSISR);
+
+	if (status & BIT_SOF_INT) {
+		/* reflash the embeded DMA controller */
+		if (frame_count % 2 == 1)
+			__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+	}
+
+	if (status & BIT_DMA_TSF_DONE_FB1) {
+		if (cam->capture_on) {
+			cam->ping_pong_csi = 1;
+			cam->enc_callback(0, cam);
+		} else {
+			cam->still_counter++;
+			wake_up_interruptible(&cam->still_queue);
+		}
+	}
+
+	if (status & BIT_DMA_TSF_DONE_FB2) {
+		if (cam->capture_on) {
+			cam->ping_pong_csi = 2;
+			cam->enc_callback(0, cam);
+		} else {
+			cam->still_counter++;
+			wake_up_interruptible(&cam->still_queue);
+		}
+	}
+
+	if (g_callback)
+		g_callback(g_callback_data, status);
+
+	pr_debug("CSI status = 0x%08lX\n", status);
+
+	return IRQ_HANDLED;
+}
+
+static void csihw_reset_frame_count(void)
+{
+	__raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3);
+}
+
+static void csihw_reset(void)
+{
+	csihw_reset_frame_count();
+	__raw_writel(CSICR1_RESET_VAL, CSI_CSICR1);
+	__raw_writel(CSICR2_RESET_VAL, CSI_CSICR2);
+	__raw_writel(CSICR3_RESET_VAL, CSI_CSICR3);
+}
+
+/*!
+ * csi_init_interface
+ *    Init csi interface
+ */
+void csi_init_interface(void)
+{
+	unsigned int val = 0;
+	unsigned int imag_para;
+
+	val |= BIT_SOF_POL;
+	val |= BIT_REDGE;
+	val |= BIT_GCLK_MODE;
+	val |= BIT_HSYNC_POL;
+	val |= BIT_PACK_DIR;
+	val |= BIT_FCC;
+	val |= BIT_SWAP16_EN;
+	val |= 1 << SHIFT_MCLKDIV;
+	__raw_writel(val, CSI_CSICR1);
+
+	imag_para = (640 << 16) | 960;
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	val = 0x1010;
+	val |= BIT_DMA_REFLASH_RFF;
+	__raw_writel(val, CSI_CSICR3);
+}
+EXPORT_SYMBOL(csi_init_interface);
+
+/*!
+ * csi_enable_mclk
+ *
+ * @param       src         enum define which source to control the clk
+ *                          CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C
+ * @param       flag        true to enable mclk, false to disable mclk
+ * @param       wait        true to wait 100ms make clock stable, false not wait
+ *
+ * @return      0 for success
+ */
+int32_t csi_enable_mclk(int src, bool flag, bool wait)
+{
+	if (flag == true) {
+		csi_mclk_enable();
+		if (wait == true)
+			msleep(10);
+		pr_debug("Enable csi clock from source %d\n", src);
+		g_csi_mclk_on = true;
+	} else {
+		csi_mclk_disable();
+		pr_debug("Disable csi clock from source %d\n", src);
+		g_csi_mclk_on = false;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(csi_enable_mclk);
+
+/*!
+ * csi_read_mclk_flag
+ *
+ * @return  gcsi_mclk_source
+ */
+int csi_read_mclk_flag(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL(csi_read_mclk_flag);
+
+void csi_start_callback(void *data)
+{
+	cam_data *cam = (cam_data *) data;
+
+	if (request_irq(MXC_INT_CSI, csi_irq_handler, 0, "csi", cam) < 0)
+		pr_debug("CSI error: irq request fail\n");
+
+}
+EXPORT_SYMBOL(csi_start_callback);
+
+void csi_stop_callback(void *data)
+{
+	cam_data *cam = (cam_data *) data;
+
+	free_irq(MXC_INT_CSI, cam);
+}
+EXPORT_SYMBOL(csi_stop_callback);
+
+void csi_enable_int(int arg)
+{
+	unsigned long cr1 = __raw_readl(CSI_CSICR1);
+
+	cr1 |= BIT_SOF_INTEN;
+	if (arg == 1) {
+		/* still capture needs DMA intterrupt */
+		cr1 |= BIT_FB1_DMA_DONE_INTEN;
+		cr1 |= BIT_FB2_DMA_DONE_INTEN;
+	}
+	__raw_writel(cr1, CSI_CSICR1);
+}
+EXPORT_SYMBOL(csi_enable_int);
+
+void csi_disable_int(void)
+{
+	unsigned long cr1 = __raw_readl(CSI_CSICR1);
+
+	cr1 &= ~BIT_SOF_INTEN;
+	cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
+	cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
+	__raw_writel(cr1, CSI_CSICR1);
+}
+EXPORT_SYMBOL(csi_disable_int);
+
+void csi_set_16bit_imagpara(int width, int height)
+{
+	int imag_para = 0;
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	imag_para = (width << 16) | (height * 2);
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	/* reflash the embeded DMA controller */
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+}
+EXPORT_SYMBOL(csi_set_16bit_imagpara);
+
+void csi_set_12bit_imagpara(int width, int height)
+{
+	int imag_para = 0;
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	imag_para = (width << 16) | (height * 3 / 2);
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	/* reflash the embeded DMA controller */
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+}
+EXPORT_SYMBOL(csi_set_12bit_imagpara);
+
+static void csi_mclk_recalc(struct clk *clk)
+{
+	u32 div;
+
+	div = (__raw_readl(CSI_CSICR1) & BIT_MCLKDIV) >> SHIFT_MCLKDIV;
+	if (div == 0)
+		div = 1;
+	else
+		div = div * 2;
+
+	clk->rate = clk->parent->rate / div;
+}
+
+void csi_mclk_enable(void)
+{
+	__raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1);
+}
+
+void csi_mclk_disable(void)
+{
+	__raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1);
+}
+
+int32_t __init csi_init_module(void)
+{
+	int ret = 0;
+	struct clk *per_clk;
+
+	csihw_reset();
+	csi_init_interface();
+
+	per_clk = clk_get(NULL, "csi_clk");
+	if (IS_ERR(per_clk))
+		return PTR_ERR(per_clk);
+
+	clk_put(per_clk);
+	csi_mclk.name = "csi_mclk";
+	csi_mclk.parent = per_clk;
+	clk_register(&csi_mclk);
+	clk_enable(per_clk);
+	csi_mclk_recalc(&csi_mclk);
+
+	return ret;
+}
+
+void __exit csi_cleanup_module(void)
+{
+	clk_disable(&csi_mclk);
+	clk_unregister(&csi_mclk);
+}
+
+module_init(csi_init_module);
+module_exit(csi_cleanup_module);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("fsl CSI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/fsl_csi.h b/drivers/media/video/mxc/capture/fsl_csi.h
new file mode 100644
index 000000000000..ee57597407f3
--- /dev/null
+++ b/drivers/media/video/mxc/capture/fsl_csi.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_csi.h
+ *
+ * @brief mx25 CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+
+#ifndef MX25_CSI_H
+#define MX25_CSI_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+/* reset values */
+#define CSICR1_RESET_VAL	0x40000800
+#define CSICR2_RESET_VAL	0x0
+#define CSICR3_RESET_VAL	0x0
+
+/* csi control reg 1 */
+#define BIT_SWAP16_EN		(0x1 << 31)
+#define BIT_EXT_VSYNC		(0x1 << 30)
+#define BIT_EOF_INT_EN		(0x1 << 29)
+#define BIT_PRP_IF_EN		(0x1 << 28)
+#define BIT_CCIR_MODE		(0x1 << 27)
+#define BIT_COF_INT_EN		(0x1 << 26)
+#define BIT_SF_OR_INTEN		(0x1 << 25)
+#define BIT_RF_OR_INTEN		(0x1 << 24)
+#define BIT_SFF_DMA_DONE_INTEN  (0x1 << 22)
+#define BIT_STATFF_INTEN	(0x1 << 21)
+#define BIT_FB2_DMA_DONE_INTEN  (0x1 << 20)
+#define BIT_FB1_DMA_DONE_INTEN  (0x1 << 19)
+#define BIT_RXFF_INTEN		(0x1 << 18)
+#define BIT_SOF_POL		(0x1 << 17)
+#define BIT_SOF_INTEN		(0x1 << 16)
+#define BIT_MCLKDIV		(0xF << 12)
+#define BIT_HSYNC_POL		(0x1 << 11)
+#define BIT_CCIR_EN		(0x1 << 10)
+#define BIT_MCLKEN		(0x1 << 9)
+#define BIT_FCC			(0x1 << 8)
+#define BIT_PACK_DIR		(0x1 << 7)
+#define BIT_CLR_STATFIFO	(0x1 << 6)
+#define BIT_CLR_RXFIFO		(0x1 << 5)
+#define BIT_GCLK_MODE		(0x1 << 4)
+#define BIT_INV_DATA		(0x1 << 3)
+#define BIT_INV_PCLK		(0x1 << 2)
+#define BIT_REDGE		(0x1 << 1)
+#define BIT_PIXEL_BIT		(0x1 << 0)
+
+#define SHIFT_MCLKDIV		12
+
+/* control reg 3 */
+#define BIT_FRMCNT		(0xFFFF << 16)
+#define BIT_FRMCNT_RST		(0x1 << 15)
+#define BIT_DMA_REFLASH_RFF	(0x1 << 14)
+#define BIT_DMA_REFLASH_SFF	(0x1 << 13)
+#define BIT_DMA_REQ_EN_RFF	(0x1 << 12)
+#define BIT_DMA_REQ_EN_SFF	(0x1 << 11)
+#define BIT_STATFF_LEVEL	(0x7 << 8)
+#define BIT_HRESP_ERR_EN	(0x1 << 7)
+#define BIT_RXFF_LEVEL		(0x7 << 4)
+#define BIT_TWO_8BIT_SENSOR	(0x1 << 3)
+#define BIT_ZERO_PACK_EN	(0x1 << 2)
+#define BIT_ECC_INT_EN		(0x1 << 1)
+#define BIT_ECC_AUTO_EN		(0x1 << 0)
+
+#define SHIFT_FRMCNT		16
+
+/* csi status reg */
+#define BIT_SFF_OR_INT		(0x1 << 25)
+#define BIT_RFF_OR_INT		(0x1 << 24)
+#define BIT_DMA_TSF_DONE_SFF	(0x1 << 22)
+#define BIT_STATFF_INT		(0x1 << 21)
+#define BIT_DMA_TSF_DONE_FB2	(0x1 << 20)
+#define BIT_DMA_TSF_DONE_FB1	(0x1 << 19)
+#define BIT_RXFF_INT		(0x1 << 18)
+#define BIT_EOF_INT		(0x1 << 17)
+#define BIT_SOF_INT		(0x1 << 16)
+#define BIT_F2_INT		(0x1 << 15)
+#define BIT_F1_INT		(0x1 << 14)
+#define BIT_COF_INT		(0x1 << 13)
+#define BIT_HRESP_ERR_INT	(0x1 << 7)
+#define BIT_ECC_INT		(0x1 << 1)
+#define BIT_DRDY		(0x1 << 0)
+
+#define CSI_MCLK_VF		1
+#define CSI_MCLK_ENC		2
+#define CSI_MCLK_RAW		4
+#define CSI_MCLK_I2C		8
+#endif
+
+#define CSI_CSICR1		(IO_ADDRESS(CSI_BASE_ADDR))
+#define CSI_CSICR2		(IO_ADDRESS(CSI_BASE_ADDR + 0x4))
+#define CSI_CSICR3		(IO_ADDRESS(CSI_BASE_ADDR + 0x8))
+#define CSI_STATFIFO		(IO_ADDRESS(CSI_BASE_ADDR + 0xC))
+#define CSI_CSIRXFIFO		(IO_ADDRESS(CSI_BASE_ADDR + 0x10))
+#define CSI_CSIRXCNT		(IO_ADDRESS(CSI_BASE_ADDR + 0x14))
+#define CSI_CSISR		(IO_ADDRESS(CSI_BASE_ADDR + 0x18))
+
+#define CSI_CSIDBG		(IO_ADDRESS(CSI_BASE_ADDR + 0x1C))
+#define CSI_CSIDMASA_STATFIFO	(IO_ADDRESS(CSI_BASE_ADDR + 0x20))
+#define CSI_CSIDMATS_STATFIFO	(IO_ADDRESS(CSI_BASE_ADDR + 0x24))
+#define CSI_CSIDMASA_FB1	(IO_ADDRESS(CSI_BASE_ADDR + 0x28))
+#define CSI_CSIDMASA_FB2	(IO_ADDRESS(CSI_BASE_ADDR + 0x2C))
+#define CSI_CSIFBUF_PARA	(IO_ADDRESS(CSI_BASE_ADDR + 0x30))
+#define CSI_CSIIMAG_PARA	(IO_ADDRESS(CSI_BASE_ADDR + 0x34))
+
+#define CSI_CSIRXFIFO_PHYADDR	(CSI_BASE_ADDR + 0x10)
+
+static inline void csi_clear_status(unsigned long status)
+{
+	__raw_writel(status, CSI_CSISR);
+}
+
+struct csi_signal_cfg_t {
+	unsigned data_width:3;
+	unsigned clk_mode:2;
+	unsigned ext_vsync:1;
+	unsigned Vsync_pol:1;
+	unsigned Hsync_pol:1;
+	unsigned pixclk_pol:1;
+	unsigned data_pol:1;
+	unsigned sens_clksrc:1;
+};
+
+struct csi_config_t {
+	/* control reg 1 */
+	unsigned int swap16_en:1;
+	unsigned int ext_vsync:1;
+	unsigned int eof_int_en:1;
+	unsigned int prp_if_en:1;
+	unsigned int ccir_mode:1;
+	unsigned int cof_int_en:1;
+	unsigned int sf_or_inten:1;
+	unsigned int rf_or_inten:1;
+	unsigned int sff_dma_done_inten:1;
+	unsigned int statff_inten:1;
+	unsigned int fb2_dma_done_inten:1;
+	unsigned int fb1_dma_done_inten:1;
+	unsigned int rxff_inten:1;
+	unsigned int sof_pol:1;
+	unsigned int sof_inten:1;
+	unsigned int mclkdiv:4;
+	unsigned int hsync_pol:1;
+	unsigned int ccir_en:1;
+	unsigned int mclken:1;
+	unsigned int fcc:1;
+	unsigned int pack_dir:1;
+	unsigned int gclk_mode:1;
+	unsigned int inv_data:1;
+	unsigned int inv_pclk:1;
+	unsigned int redge:1;
+	unsigned int pixel_bit:1;
+
+	/* control reg 3 */
+	unsigned int frmcnt:16;
+	unsigned int frame_reset:1;
+	unsigned int dma_reflash_rff:1;
+	unsigned int dma_reflash_sff:1;
+	unsigned int dma_req_en_rff:1;
+	unsigned int dma_req_en_sff:1;
+	unsigned int statff_level:3;
+	unsigned int hresp_err_en:1;
+	unsigned int rxff_level:3;
+	unsigned int two_8bit_sensor:1;
+	unsigned int zero_pack_en:1;
+	unsigned int ecc_int_en:1;
+	unsigned int ecc_auto_en:1;
+	/* fifo counter */
+	unsigned int rxcnt;
+};
+
+typedef void (*csi_irq_callback_t) (void *data, unsigned long status);
+
+int32_t csi_enable_mclk(int src, bool flag, bool wait);
+void csi_init_interface(void);
+void csi_set_16bit_imagpara(int width, int height);
+void csi_set_12bit_imagpara(int width, int height);
+int csi_read_mclk_flag(void);
+void csi_start_callback(void *data);
+void csi_stop_callback(void *data);
+void csi_enable_int(int arg);
+void csi_disable_int(void);
+void csi_mclk_enable(void);
+void csi_mclk_disable(void);
diff --git a/drivers/media/video/mxc/capture/ipu_csi_enc.c b/drivers/media/video/mxc/capture/ipu_csi_enc.c
new file mode 100644
index 000000000000..c0842f81ee27
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_csi_enc.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_csi_enc.c
+ *
+ * @brief CSI Use case for video capture
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/ipu.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+#ifdef CAMERA_DBG
+	#define CAMERA_TRACE(x) (printk)x
+#else
+	#define CAMERA_TRACE(x)
+#endif
+
+/*
+ * Function definitions
+ */
+
+/*!
+ * csi ENC callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t csi_enc_callback(int irq, void *dev_id)
+{
+	cam_data *cam = (cam_data *) dev_id;
+
+	if (cam->enc_callback == NULL)
+		return IRQ_HANDLED;
+
+	cam->enc_callback(irq, dev_id);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * CSI ENC enable channel setup function
+ *
+ * @param cam       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int csi_enc_setup(cam_data *cam)
+{
+	ipu_channel_params_t params;
+	u32 pixel_fmt;
+	int err = 0;
+	dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
+
+	CAMERA_TRACE("In csi_enc_setup\n");
+	if (!cam) {
+		printk(KERN_ERR "cam private is NULL\n");
+		return -ENXIO;
+	}
+
+	memset(&params, 0, sizeof(ipu_channel_params_t));
+	params.csi_mem.csi = cam->csi;
+
+	if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
+		pixel_fmt = IPU_PIX_FMT_YUV420P;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
+		pixel_fmt = IPU_PIX_FMT_YUV422P;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
+		pixel_fmt = IPU_PIX_FMT_UYVY;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
+		pixel_fmt = IPU_PIX_FMT_YUYV;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
+		pixel_fmt = IPU_PIX_FMT_NV12;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
+		pixel_fmt = IPU_PIX_FMT_BGR24;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
+		pixel_fmt = IPU_PIX_FMT_RGB24;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
+		pixel_fmt = IPU_PIX_FMT_RGB565;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
+		pixel_fmt = IPU_PIX_FMT_BGR32;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
+		pixel_fmt = IPU_PIX_FMT_RGB32;
+	else {
+		printk(KERN_ERR "format not supported\n");
+		return -EINVAL;
+	}
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true);
+
+	err = ipu_init_channel(CSI_MEM, &params);
+	if (err != 0) {
+		printk(KERN_ERR "ipu_init_channel %d\n", err);
+		return err;
+	}
+
+	err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+				      pixel_fmt, cam->v2f.fmt.pix.width,
+				      cam->v2f.fmt.pix.height,
+				      cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
+				      dummy, dummy,
+				      cam->offset.u_offset,
+				      cam->offset.v_offset);
+	if (err != 0) {
+		printk(KERN_ERR "CSI_MEM output buffer\n");
+		return err;
+	}
+	err = ipu_enable_channel(CSI_MEM);
+	if (err < 0) {
+		printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
+		return err;
+	}
+
+	return err;
+}
+
+/*!
+ * function to update physical buffer address for encorder IDMA channel
+ *
+ * @param eba         physical buffer address for encorder IDMA channel
+ * @param buffer_num  int buffer 0 or buffer 1
+ *
+ * @return  status
+ */
+static int csi_enc_eba_update(dma_addr_t eba, int *buffer_num)
+{
+	int err = 0;
+
+	pr_debug("eba %x\n", eba);
+	err = ipu_update_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+					*buffer_num, eba);
+	if (err != 0) {
+		ipu_clear_buffer_ready(CSI_MEM, IPU_OUTPUT_BUFFER,
+				       *buffer_num);
+		printk(KERN_ERR "err %d buffer_num %d\n", err, *buffer_num);
+		return err;
+	}
+
+	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num);
+
+	*buffer_num = (*buffer_num == 0) ? 1 : 0;
+
+	return 0;
+}
+
+/*!
+ * Enable encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int csi_enc_enabling_tasks(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+	CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
+
+	cam->dummy_frame.vaddress = dma_alloc_coherent(0,
+			       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+			       &cam->dummy_frame.paddress,
+			       GFP_DMA | GFP_KERNEL);
+	if (cam->dummy_frame.vaddress == 0) {
+		pr_err("ERROR: v4l2 capture: Allocate dummy frame "
+		       "failed.\n");
+		return -ENOBUFS;
+	}
+	cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
+	cam->dummy_frame.buffer.length =
+	    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
+	cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
+
+	ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF);
+	err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF,
+			      csi_enc_callback, 0, "Mxc Camera", cam);
+	if (err != 0) {
+		printk(KERN_ERR "Error registering rot irq\n");
+		return err;
+	}
+
+	err = csi_enc_setup(cam);
+	if (err != 0) {
+		printk(KERN_ERR "csi_enc_setup %d\n", err);
+		return err;
+	}
+
+	return err;
+}
+
+/*!
+ * Disable encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+static int csi_enc_disabling_tasks(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam);
+
+	err = ipu_disable_channel(CSI_MEM, true);
+
+	ipu_uninit_channel(CSI_MEM);
+
+	if (cam->dummy_frame.vaddress != 0) {
+		dma_free_coherent(0, cam->dummy_frame.buffer.length,
+				  cam->dummy_frame.vaddress,
+				  cam->dummy_frame.paddress);
+		cam->dummy_frame.vaddress = 0;
+	}
+	ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, false, false);
+
+	return err;
+}
+
+/*!
+ * Enable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int csi_enc_enable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_enable_csi(cam->csi);
+}
+
+/*!
+ * Disable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int csi_enc_disable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_disable_csi(cam->csi);
+}
+
+/*!
+ * function to select CSI ENC as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+int csi_enc_select(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (cam) {
+		cam->enc_update_eba = csi_enc_eba_update;
+		cam->enc_enable = csi_enc_enabling_tasks;
+		cam->enc_disable = csi_enc_disabling_tasks;
+		cam->enc_enable_csi = csi_enc_enable_csi;
+		cam->enc_disable_csi = csi_enc_disable_csi;
+	} else {
+		err = -EIO;
+	}
+
+	return err;
+}
+
+/*!
+ * function to de-select CSI ENC as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+int csi_enc_deselect(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (cam) {
+		cam->enc_update_eba = NULL;
+		cam->enc_enable = NULL;
+		cam->enc_disable = NULL;
+		cam->enc_enable_csi = NULL;
+		cam->enc_disable_csi = NULL;
+	}
+
+	return err;
+}
+
+/*!
+ * Init the Encorder channels
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int csi_enc_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit the Encorder channels
+ *
+ */
+void __exit csi_enc_exit(void)
+{
+}
+
+module_init(csi_enc_init);
+module_exit(csi_enc_exit);
+
+EXPORT_SYMBOL(csi_enc_select);
+EXPORT_SYMBOL(csi_enc_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("CSI ENC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_prp_enc.c b/drivers/media/video/mxc/capture/ipu_prp_enc.c
new file mode 100644
index 000000000000..3a07bbfdcbaa
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_prp_enc.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_prp_enc.c
+ *
+ * @brief IPU Use case for PRP-ENC
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/ipu.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+#ifdef CAMERA_DBG
+	#define CAMERA_TRACE(x) (printk)x
+#else
+	#define CAMERA_TRACE(x)
+#endif
+
+static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE;
+
+/*
+ * Function definitions
+ */
+
+/*!
+ * IPU ENC callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t prp_enc_callback(int irq, void *dev_id)
+{
+	cam_data *cam = (cam_data *) dev_id;
+
+	if (cam->enc_callback == NULL)
+		return IRQ_HANDLED;
+
+	cam->enc_callback(irq, dev_id);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * PrpENC enable channel setup function
+ *
+ * @param cam       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_enc_setup(cam_data * cam)
+{
+	ipu_channel_params_t enc;
+	int err = 0;
+	dma_addr_t dummy = 0xdeadbeaf;
+
+	CAMERA_TRACE("In prp_enc_setup\n");
+	if (!cam) {
+		printk(KERN_ERR "cam private is NULL\n");
+		return -ENXIO;
+	}
+	memset(&enc, 0, sizeof(ipu_channel_params_t));
+
+	ipu_csi_get_window_size(&enc.csi_prp_enc_mem.in_width,
+				&enc.csi_prp_enc_mem.in_height, cam->csi);
+
+	enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
+	enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width;
+	enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height;
+	enc.csi_prp_enc_mem.csi = cam->csi;
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height;
+		enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width;
+	}
+
+	if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P;
+		pr_info("YUV420\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P;
+		pr_info("YUV422P\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUYV;
+		pr_info("YUYV\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_UYVY;
+		pr_info("UYVY\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12;
+		pr_info("NV12\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24;
+		pr_info("BGR24\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24;
+		pr_info("RGB24\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565;
+		pr_info("RGB565\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32;
+		pr_info("BGR32\n");
+	} else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) {
+		enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32;
+		pr_info("RGB32\n");
+	} else {
+		printk(KERN_ERR "format not supported\n");
+		return -EINVAL;
+	}
+
+	err = ipu_init_channel(CSI_PRP_ENC_MEM, &enc);
+	if (err != 0) {
+		printk(KERN_ERR "ipu_init_channel %d\n", err);
+		return err;
+	}
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true);
+
+	grotation = cam->rotation;
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		if (cam->rot_enc_bufs_vaddr[0]) {
+			dma_free_coherent(0, cam->rot_enc_buf_size[0],
+					  cam->rot_enc_bufs_vaddr[0],
+					  cam->rot_enc_bufs[0]);
+		}
+		if (cam->rot_enc_bufs_vaddr[1]) {
+			dma_free_coherent(0, cam->rot_enc_buf_size[1],
+					  cam->rot_enc_bufs_vaddr[1],
+					  cam->rot_enc_bufs[1]);
+		}
+		cam->rot_enc_buf_size[0] =
+		    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
+		cam->rot_enc_bufs_vaddr[0] =
+		    (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0],
+					       &cam->rot_enc_bufs[0],
+					       GFP_DMA | GFP_KERNEL);
+		if (!cam->rot_enc_bufs_vaddr[0]) {
+			printk(KERN_ERR "alloc enc_bufs0\n");
+			return -ENOMEM;
+		}
+		cam->rot_enc_buf_size[1] =
+		    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
+		cam->rot_enc_bufs_vaddr[1] =
+		    (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1],
+					       &cam->rot_enc_bufs[1],
+					       GFP_DMA | GFP_KERNEL);
+		if (!cam->rot_enc_bufs_vaddr[1]) {
+			dma_free_coherent(0, cam->rot_enc_buf_size[0],
+					  cam->rot_enc_bufs_vaddr[0],
+					  cam->rot_enc_bufs[0]);
+			cam->rot_enc_bufs_vaddr[0] = NULL;
+			cam->rot_enc_bufs[0] = 0;
+			printk(KERN_ERR "alloc enc_bufs1\n");
+			return -ENOMEM;
+		}
+
+		err = ipu_init_channel_buffer(CSI_PRP_ENC_MEM,
+					      IPU_OUTPUT_BUFFER,
+					      enc.csi_prp_enc_mem.out_pixel_fmt,
+					      enc.csi_prp_enc_mem.out_width,
+					      enc.csi_prp_enc_mem.out_height,
+					      enc.csi_prp_enc_mem.out_width,
+					      IPU_ROTATE_NONE,
+					      cam->rot_enc_bufs[0],
+					      cam->rot_enc_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "CSI_PRP_ENC_MEM err\n");
+			return err;
+		}
+
+		err = ipu_init_channel(MEM_ROT_ENC_MEM, NULL);
+		if (err != 0) {
+			printk(KERN_ERR "MEM_ROT_ENC_MEM channel err\n");
+			return err;
+		}
+
+		err = ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_INPUT_BUFFER,
+					      enc.csi_prp_enc_mem.out_pixel_fmt,
+					      enc.csi_prp_enc_mem.out_width,
+					      enc.csi_prp_enc_mem.out_height,
+					      enc.csi_prp_enc_mem.out_width,
+					      cam->rotation,
+					      cam->rot_enc_bufs[0],
+					      cam->rot_enc_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n");
+			return err;
+		}
+
+		err =
+		    ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER,
+					    enc.csi_prp_enc_mem.out_pixel_fmt,
+					    enc.csi_prp_enc_mem.out_height,
+					    enc.csi_prp_enc_mem.out_width,
+					    cam->v2f.fmt.pix.bytesperline /
+					    bytes_per_pixel(enc.csi_prp_enc_mem.
+							    out_pixel_fmt),
+					    IPU_ROTATE_NONE, dummy, dummy,
+					    cam->offset.u_offset,
+					    cam->offset.v_offset);
+		if (err != 0) {
+			printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n");
+			return err;
+		}
+
+		err = ipu_link_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n");
+			return err;
+		}
+
+		err = ipu_enable_channel(CSI_PRP_ENC_MEM);
+		if (err < 0) {
+			printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
+			return err;
+		}
+		err = ipu_enable_channel(MEM_ROT_ENC_MEM);
+		if (err < 0) {
+			printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n");
+			return err;
+		}
+
+		ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 1);
+	} else {
+		err =
+		    ipu_init_channel_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER,
+					    enc.csi_prp_enc_mem.out_pixel_fmt,
+					    enc.csi_prp_enc_mem.out_width,
+					    enc.csi_prp_enc_mem.out_height,
+					    cam->v2f.fmt.pix.bytesperline /
+					    bytes_per_pixel(enc.csi_prp_enc_mem.
+							    out_pixel_fmt),
+					    cam->rotation, dummy, dummy,
+					    cam->offset.u_offset,
+					    cam->offset.v_offset);
+		if (err != 0) {
+			printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n");
+			return err;
+		}
+		err = ipu_enable_channel(CSI_PRP_ENC_MEM);
+		if (err < 0) {
+			printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
+			return err;
+		}
+	}
+
+	return err;
+}
+
+/*!
+ * function to update physical buffer address for encorder IDMA channel
+ *
+ * @param eba         physical buffer address for encorder IDMA channel
+ * @param buffer_num  int buffer 0 or buffer 1
+ *
+ * @return  status
+ */
+static int prp_enc_eba_update(dma_addr_t eba, int *buffer_num)
+{
+	int err = 0;
+
+	pr_debug("eba %x\n", eba);
+	if (grotation >= IPU_ROTATE_90_RIGHT) {
+		err = ipu_update_channel_buffer(MEM_ROT_ENC_MEM,
+						IPU_OUTPUT_BUFFER, *buffer_num,
+						eba);
+	} else {
+		err = ipu_update_channel_buffer(CSI_PRP_ENC_MEM,
+						IPU_OUTPUT_BUFFER, *buffer_num,
+						eba);
+	}
+	if (err != 0) {
+		printk(KERN_ERR "err %d buffer_num %d\n", err, *buffer_num);
+		return err;
+	}
+
+	if (grotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_select_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER,
+				  *buffer_num);
+	} else {
+		ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER,
+				  *buffer_num);
+	}
+
+	*buffer_num = (*buffer_num == 0) ? 1 : 0;
+	return 0;
+}
+
+/*!
+ * Enable encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_enc_enabling_tasks(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+	CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n");
+
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		err = ipu_request_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF,
+				      prp_enc_callback, 0, "Mxc Camera", cam);
+	} else {
+		err = ipu_request_irq(IPU_IRQ_PRP_ENC_OUT_EOF,
+				      prp_enc_callback, 0, "Mxc Camera", cam);
+	}
+	if (err != 0) {
+		printk(KERN_ERR "Error registering rot irq\n");
+		return err;
+	}
+
+	err = prp_enc_setup(cam);
+	if (err != 0) {
+		printk(KERN_ERR "prp_enc_setup %d\n", err);
+		return err;
+	}
+
+	return err;
+}
+
+/*!
+ * Disable encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+static int prp_enc_disabling_tasks(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_free_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam);
+	} else {
+		ipu_free_irq(IPU_IRQ_PRP_ENC_OUT_EOF, cam);
+	}
+
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_unlink_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
+	}
+
+	err = ipu_disable_channel(CSI_PRP_ENC_MEM, true);
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		err |= ipu_disable_channel(MEM_ROT_ENC_MEM, true);
+	}
+
+	ipu_uninit_channel(CSI_PRP_ENC_MEM);
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_uninit_channel(MEM_ROT_ENC_MEM);
+	}
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, false, false);
+
+	return err;
+}
+
+/*!
+ * Enable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_enc_enable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_enable_csi(cam->csi);
+}
+
+/*!
+ * Disable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_enc_disable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_disable_csi(cam->csi);
+}
+
+/*!
+ * function to select PRP-ENC as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+int prp_enc_select(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (cam) {
+		cam->enc_update_eba = prp_enc_eba_update;
+		cam->enc_enable = prp_enc_enabling_tasks;
+		cam->enc_disable = prp_enc_disabling_tasks;
+		cam->enc_enable_csi = prp_enc_enable_csi;
+		cam->enc_disable_csi = prp_enc_disable_csi;
+	} else {
+		err = -EIO;
+	}
+
+	return err;
+}
+
+/*!
+ * function to de-select PRP-ENC as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  int
+ */
+int prp_enc_deselect(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	//err = prp_enc_disabling_tasks(cam);
+
+	if (cam) {
+		cam->enc_update_eba = NULL;
+		cam->enc_enable = NULL;
+		cam->enc_disable = NULL;
+		cam->enc_enable_csi = NULL;
+		cam->enc_disable_csi = NULL;
+		if (cam->rot_enc_bufs_vaddr[0]) {
+			dma_free_coherent(0, cam->rot_enc_buf_size[0],
+					  cam->rot_enc_bufs_vaddr[0],
+					  cam->rot_enc_bufs[0]);
+			cam->rot_enc_bufs_vaddr[0] = NULL;
+			cam->rot_enc_bufs[0] = 0;
+		}
+		if (cam->rot_enc_bufs_vaddr[1]) {
+			dma_free_coherent(0, cam->rot_enc_buf_size[1],
+					  cam->rot_enc_bufs_vaddr[1],
+					  cam->rot_enc_bufs[1]);
+			cam->rot_enc_bufs_vaddr[1] = NULL;
+			cam->rot_enc_bufs[1] = 0;
+		}
+	}
+
+	return err;
+}
+
+/*!
+ * Init the Encorder channels
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int prp_enc_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit the Encorder channels
+ *
+ */
+void __exit prp_enc_exit(void)
+{
+}
+
+module_init(prp_enc_init);
+module_exit(prp_enc_exit);
+
+EXPORT_SYMBOL(prp_enc_select);
+EXPORT_SYMBOL(prp_enc_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP ENC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_prp_sw.h b/drivers/media/video/mxc/capture/ipu_prp_sw.h
new file mode 100644
index 000000000000..0d51e2ae8670
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_prp_sw.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_prp_sw.h
+ *
+ * @brief This file contains the IPU PRP use case driver header.
+ *
+ * @ingroup IPU
+ */
+
+#ifndef _INCLUDE_IPU__PRP_SW_H_
+#define _INCLUDE_IPU__PRP_SW_H_
+
+int csi_enc_select(void *private);
+int csi_enc_deselect(void *private);
+int prp_enc_select(void *private);
+int prp_enc_deselect(void *private);
+int prp_vf_adc_select(void *private);
+int prp_vf_sdc_select(void *private);
+int prp_vf_sdc_select_bg(void *private);
+int prp_vf_adc_deselect(void *private);
+int prp_vf_sdc_deselect(void *private);
+int prp_vf_sdc_deselect_bg(void *private);
+int prp_still_select(void *private);
+int prp_still_deselect(void *private);
+
+#endif
diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c b/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c
new file mode 100644
index 000000000000..a7ac09ae87d4
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_prp_vf_adc.c
+ *
+ * @brief IPU Use case for PRP-VF
+ *
+ * @ingroup IPU
+ */
+
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+#include <mach/mxcfb.h>
+#include <mach/ipu.h>
+#include <linux/dma-mapping.h>
+
+/*
+ * Function definitions
+ */
+
+/*!
+ * prpvf_start - start the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	ipu_channel_params_t vf;
+	ipu_channel_params_t params;
+	u32 format = IPU_PIX_FMT_RGB565;
+	u32 size = 2;
+	int err = 0;
+
+	if (!cam) {
+		printk(KERN_ERR "prpvf_start private is NULL\n");
+		return -ENXIO;
+	}
+
+	if (cam->overlay_active == true) {
+		printk(KERN_ERR "prpvf_start already start.\n");
+		return 0;
+	}
+
+	mxcfb_set_refresh_mode(cam->overlay_fb, MXCFB_REFRESH_OFF, 0);
+
+	memset(&vf, 0, sizeof(ipu_channel_params_t));
+	ipu_csi_get_window_size(&vf.csi_prp_vf_adc.in_width,
+				&vf.csi_prp_vf_adc.in_height);
+	vf.csi_prp_vf_adc.in_pixel_fmt = IPU_PIX_FMT_UYVY;
+	vf.csi_prp_vf_adc.out_width = cam->win.w.width;
+	vf.csi_prp_vf_adc.out_height = cam->win.w.height;
+	vf.csi_prp_vf_adc.graphics_combine_en = 0;
+	vf.csi_prp_vf_adc.out_left = cam->win.w.left;
+
+	/* hope to be removed when those offset taken cared by adc driver. */
+#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL
+	vf.csi_prp_vf_adc.out_left += 12;
+#endif
+#ifdef CONFIG_FB_MXC_EPSON_PANEL
+	vf.csi_prp_vf_adc.out_left += 2;
+#endif
+
+	vf.csi_prp_vf_adc.out_top = cam->win.w.top;
+
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		vf.csi_prp_vf_adc.out_width = cam->win.w.height;
+		vf.csi_prp_vf_adc.out_height = cam->win.w.width;
+
+		size = cam->win.w.width * cam->win.w.height * size;
+		vf.csi_prp_vf_adc.out_pixel_fmt = format;
+		err = ipu_init_channel(CSI_PRP_VF_MEM, &vf);
+		if (err != 0)
+			return err;
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true);
+
+		if (cam->vf_bufs_vaddr[0]) {
+			dma_free_coherent(0, cam->vf_bufs_size[0],
+					  cam->vf_bufs_vaddr[0],
+					  cam->vf_bufs[0]);
+		}
+		if (cam->vf_bufs_vaddr[1]) {
+			dma_free_coherent(0, cam->vf_bufs_size[1],
+					  cam->vf_bufs_vaddr[1],
+					  cam->vf_bufs[1]);
+		}
+		cam->vf_bufs_size[0] = size;
+		cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+								   cam->
+								   vf_bufs_size
+								   [0],
+								   &cam->
+								   vf_bufs[0],
+								   GFP_DMA |
+								   GFP_KERNEL);
+		if (cam->vf_bufs_vaddr[0] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate vf buffer\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+		cam->vf_bufs_size[1] = size;
+		cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+								   cam->
+								   vf_bufs_size
+								   [1],
+								   &cam->
+								   vf_bufs[1],
+								   GFP_DMA |
+								   GFP_KERNEL);
+		if (cam->vf_bufs_vaddr[1] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate vf buffer\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+
+		err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      IPU_ROTATE_NONE,
+					      cam->vf_bufs[0], cam->vf_bufs[1],
+					      0, 0);
+		if (err != 0)
+			goto out_3;
+
+		if (cam->rot_vf_bufs[0]) {
+			dma_free_coherent(0, cam->rot_vf_buf_size[0],
+					  cam->rot_vf_bufs_vaddr[0],
+					  cam->rot_vf_bufs[0]);
+		}
+		if (cam->rot_vf_bufs[1]) {
+			dma_free_coherent(0, cam->rot_vf_buf_size[1],
+					  cam->rot_vf_bufs_vaddr[1],
+					  cam->rot_vf_bufs[1]);
+		}
+		cam->rot_vf_buf_size[0] = PAGE_ALIGN(size);
+		cam->rot_vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+								       cam->
+								       rot_vf_buf_size
+								       [0],
+								       &cam->
+								       rot_vf_bufs
+								       [0],
+								       GFP_DMA |
+								       GFP_KERNEL);
+		if (cam->rot_vf_bufs_vaddr[0] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate rot_vf_bufs\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+		cam->rot_vf_buf_size[1] = PAGE_ALIGN(size);
+		cam->rot_vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+								       cam->
+								       rot_vf_buf_size
+								       [1],
+								       &cam->
+								       rot_vf_bufs
+								       [1],
+								       GFP_DMA |
+								       GFP_KERNEL);
+		if (cam->rot_vf_bufs_vaddr[1] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate rot_vf_bufs\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+		err = ipu_init_channel(MEM_ROT_VF_MEM, NULL);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start :Error "
+			       "MEM_ROT_VF_MEM channel\n");
+			goto out_3;
+		}
+
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      cam->vf_rotation, cam->vf_bufs[0],
+					      cam->vf_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "MEM_ROT_VF_MEM input buffer\n");
+			goto out_2;
+		}
+
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      IPU_ROTATE_NONE,
+					      cam->rot_vf_bufs[0],
+					      cam->rot_vf_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "MEM_ROT_VF_MEM output buffer\n");
+			goto out_2;
+		}
+
+		err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
+		if (err < 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "linking CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n");
+			goto out_2;
+		}
+
+		ipu_disable_channel(ADC_SYS2, false);
+		ipu_uninit_channel(ADC_SYS2);
+
+		params.adc_sys2.disp = DISP0;
+		params.adc_sys2.ch_mode = WriteTemplateNonSeq;
+		params.adc_sys2.out_left = cam->win.w.left;
+		/* going to be removed when those offset taken cared by adc driver. */
+#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL
+		params.adc_sys2.out_left += 12;
+#endif
+#ifdef CONFIG_FB_MXC_EPSON_PANEL
+		params.adc_sys2.out_left += 2;
+#endif
+		params.adc_sys2.out_top = cam->win.w.top;
+		err = ipu_init_channel(ADC_SYS2, &params);
+		if (err != 0) {
+			printk(KERN_ERR
+			       "prpvf_start: Error initializing ADC SYS1\n");
+			goto out_2;
+		}
+
+		err = ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      IPU_ROTATE_NONE,
+					      cam->rot_vf_bufs[0],
+					      cam->rot_vf_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "Error initializing ADC SYS1 buffer\n");
+			goto out_1;
+		}
+
+		err = ipu_link_channels(MEM_ROT_VF_MEM, ADC_SYS2);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "Error linking MEM_ROT_VF_MEM-ADC_SYS2\n");
+			goto out_1;
+		}
+
+		ipu_enable_channel(CSI_PRP_VF_MEM);
+		ipu_enable_channel(MEM_ROT_VF_MEM);
+		ipu_enable_channel(ADC_SYS2);
+
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+	}
+#ifndef CONFIG_MXC_IPU_PRP_VF_SDC
+	else if (cam->vf_rotation == IPU_ROTATE_NONE) {
+		vf.csi_prp_vf_adc.out_pixel_fmt = IPU_PIX_FMT_BGR32;
+		err = ipu_init_channel(CSI_PRP_VF_ADC, &vf);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing CSI_PRP_VF_ADC\n");
+			return err;
+		}
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true);
+		err = ipu_init_channel_buffer(CSI_PRP_VF_ADC, IPU_OUTPUT_BUFFER,
+					      format, cam->win.w.width,
+					      cam->win.w.height,
+					      cam->win.w.width, IPU_ROTATE_NONE,
+					      0, 0, 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing CSI_PRP_VF_MEM\n");
+			return err;
+		}
+		ipu_enable_channel(CSI_PRP_VF_ADC);
+	}
+#endif
+	else {
+		size = cam->win.w.width * cam->win.w.height * size;
+		vf.csi_prp_vf_adc.out_pixel_fmt = format;
+		err = ipu_init_channel(CSI_PRP_VF_MEM, &vf);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing CSI_PRP_VF_MEM\n");
+			return err;
+		}
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true);
+
+		if (cam->vf_bufs[0]) {
+			dma_free_coherent(0, cam->vf_bufs_size[0],
+					  cam->vf_bufs_vaddr[0],
+					  cam->vf_bufs[0]);
+		}
+		if (cam->vf_bufs[1]) {
+			dma_free_coherent(0, cam->vf_bufs_size[1],
+					  cam->vf_bufs_vaddr[1],
+					  cam->vf_bufs[1]);
+		}
+		cam->vf_bufs_size[0] = PAGE_ALIGN(size);
+		cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+								   cam->
+								   vf_bufs_size
+								   [0],
+								   &cam->
+								   vf_bufs[0],
+								   GFP_DMA |
+								   GFP_KERNEL);
+		if (cam->vf_bufs_vaddr[0] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate vf_bufs\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+		cam->vf_bufs_size[1] = PAGE_ALIGN(size);
+		cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+								   cam->
+								   vf_bufs_size
+								   [1],
+								   &cam->
+								   vf_bufs[1],
+								   GFP_DMA |
+								   GFP_KERNEL);
+		if (cam->vf_bufs_vaddr[1] == NULL) {
+			printk(KERN_ERR
+			       "prpvf_start: Error to allocate vf_bufs\n");
+			err = -ENOMEM;
+			goto out_3;
+		}
+		err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      cam->vf_rotation,
+					      cam->vf_bufs[0], cam->vf_bufs[1],
+					      0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing CSI_PRP_VF_MEM\n");
+			goto out_3;
+		}
+
+		ipu_disable_channel(ADC_SYS2, false);
+		ipu_uninit_channel(ADC_SYS2);
+
+		params.adc_sys2.disp = DISP0;
+		params.adc_sys2.ch_mode = WriteTemplateNonSeq;
+		params.adc_sys2.out_left = cam->win.w.left;
+		// going to be removed when those offset taken cared by adc driver.
+#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL
+		params.adc_sys2.out_left += 12;
+#endif
+#ifdef CONFIG_FB_MXC_EPSON_PANEL
+		params.adc_sys2.out_left += 2;
+#endif
+		params.adc_sys2.out_top = cam->win.w.top;
+		err = ipu_init_channel(ADC_SYS2, &params);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing ADC_SYS2\n");
+			goto out_3;
+		}
+
+		err = ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      IPU_ROTATE_NONE, cam->vf_bufs[0],
+					      cam->vf_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "initializing ADC SYS1 buffer\n");
+			goto out_1;
+		}
+
+		err = ipu_link_channels(CSI_PRP_VF_MEM, ADC_SYS2);
+		if (err < 0) {
+			printk(KERN_ERR "prpvf_start: Error "
+			       "linking MEM_ROT_VF_MEM-ADC_SYS2\n");
+			goto out_1;
+		}
+
+		ipu_enable_channel(CSI_PRP_VF_MEM);
+		ipu_enable_channel(ADC_SYS2);
+
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+	}
+
+	cam->overlay_active = true;
+	return err;
+
+      out_1:
+	ipu_uninit_channel(ADC_SYS2);
+      out_2:
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_uninit_channel(MEM_ROT_VF_MEM);
+	}
+      out_3:
+	ipu_uninit_channel(CSI_PRP_VF_MEM);
+	if (cam->rot_vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[0],
+				  cam->rot_vf_bufs_vaddr[0],
+				  cam->rot_vf_bufs[0]);
+		cam->rot_vf_bufs_vaddr[0] = NULL;
+		cam->rot_vf_bufs[0] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[1],
+				  cam->rot_vf_bufs_vaddr[1],
+				  cam->rot_vf_bufs[1]);
+		cam->rot_vf_bufs_vaddr[1] = NULL;
+		cam->rot_vf_bufs[1] = 0;
+	}
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+	return err;
+}
+
+/*!
+ * prpvf_stop - stop the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_stop(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (cam->overlay_active == false)
+		return 0;
+
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
+		ipu_unlink_channels(MEM_ROT_VF_MEM, ADC_SYS2);
+
+		ipu_disable_channel(CSI_PRP_VF_MEM, true);
+		ipu_disable_channel(MEM_ROT_VF_MEM, true);
+		ipu_disable_channel(ADC_SYS2, true);
+
+		ipu_uninit_channel(CSI_PRP_VF_MEM);
+		ipu_uninit_channel(MEM_ROT_VF_MEM);
+		ipu_uninit_channel(ADC_SYS2);
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false);
+	}
+#ifndef CONFIG_MXC_IPU_PRP_VF_SDC
+	else if (cam->vf_rotation == IPU_ROTATE_NONE) {
+		ipu_disable_channel(CSI_PRP_VF_ADC, false);
+		ipu_uninit_channel(CSI_PRP_VF_ADC);
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false);
+	}
+#endif
+	else {
+		ipu_unlink_channels(CSI_PRP_VF_MEM, ADC_SYS2);
+
+		ipu_disable_channel(CSI_PRP_VF_MEM, true);
+		ipu_disable_channel(ADC_SYS2, true);
+
+		ipu_uninit_channel(CSI_PRP_VF_MEM);
+		ipu_uninit_channel(ADC_SYS2);
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false);
+	}
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[0],
+				  cam->rot_vf_bufs_vaddr[0],
+				  cam->rot_vf_bufs[0]);
+		cam->rot_vf_bufs_vaddr[0] = NULL;
+		cam->rot_vf_bufs[0] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[1],
+				  cam->rot_vf_bufs_vaddr[1],
+				  cam->rot_vf_bufs[1]);
+		cam->rot_vf_bufs_vaddr[1] = NULL;
+		cam->rot_vf_bufs[1] = 0;
+	}
+
+	cam->overlay_active = false;
+
+	mxcfb_set_refresh_mode(cam->overlay_fb, MXCFB_REFRESH_PARTIAL, 0);
+	return err;
+}
+
+/*!
+ * function to select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int prp_vf_adc_select(void *private)
+{
+	cam_data *cam;
+	if (private) {
+		cam = (cam_data *) private;
+		cam->vf_start_adc = prpvf_start;
+		cam->vf_stop_adc = prpvf_stop;
+		cam->overlay_active = false;
+	} else {
+		return -EIO;
+	}
+	return 0;
+}
+
+/*!
+ * function to de-select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int prp_vf_adc_deselect(void *private)
+{
+	cam_data *cam;
+	int err = 0;
+	err = prpvf_stop(private);
+
+	if (private) {
+		cam = (cam_data *) private;
+		cam->vf_start_adc = NULL;
+		cam->vf_stop_adc = NULL;
+	}
+	return err;
+}
+
+/*!
+ * Init viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int prp_vf_adc_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+void __exit prp_vf_adc_exit(void)
+{
+}
+
+module_init(prp_vf_adc_init);
+module_exit(prp_vf_adc_exit);
+
+EXPORT_SYMBOL(prp_vf_adc_select);
+EXPORT_SYMBOL(prp_vf_adc_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP VF ADC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c
new file mode 100644
index 000000000000..882bacf923b1
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_prp_vf_sdc.c
+ *
+ * @brief IPU Use case for PRP-VF
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/console.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <mach/hardware.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+#define OVERLAY_FB_SUPPORT_NONSTD	(cpu_is_mx51_rev(CHIP_REV_2_0) >= 1)
+
+/*
+ * Function definitions
+ */
+
+/*!
+ * prpvf_start - start the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_start(void *private)
+{
+	struct fb_var_screeninfo fbvar;
+	struct fb_info *fbi = NULL;
+	cam_data *cam = (cam_data *) private;
+	ipu_channel_params_t vf;
+	u32 vf_out_format = 0;
+	u32 size = 2, temp = 0;
+	int err = 0, i = 0;
+
+	if (!cam) {
+		printk(KERN_ERR "private is NULL\n");
+		return -EIO;
+	}
+
+	if (cam->overlay_active == true) {
+		pr_debug("already started.\n");
+		return 0;
+	}
+
+	for (i = 0; i < num_registered_fb; i++) {
+		char *idstr = registered_fb[i]->fix.id;
+		if (strcmp(idstr, "DISP3 FG") == 0) {
+			fbi = registered_fb[i];
+			break;
+		}
+	}
+
+	if (fbi == NULL) {
+		printk(KERN_ERR "DISP3 FG fb not found\n");
+		return -EPERM;
+	}
+
+	fbvar = fbi->var;
+
+	/* Store the overlay frame buffer's original std */
+	cam->fb_origin_std = fbvar.nonstd;
+
+	if (OVERLAY_FB_SUPPORT_NONSTD) {
+		/* Use DP to do CSC so that we can get better performance */
+		vf_out_format = IPU_PIX_FMT_UYVY;
+		fbvar.nonstd = vf_out_format;
+	} else {
+		vf_out_format = IPU_PIX_FMT_RGB565;
+		fbvar.nonstd = 0;
+	}
+
+	fbvar.bits_per_pixel = 16;
+	fbvar.xres = fbvar.xres_virtual = cam->win.w.width;
+	fbvar.yres = cam->win.w.height;
+	fbvar.yres_virtual = cam->win.w.height * 2;
+	fbvar.activate |= FB_ACTIVATE_FORCE;
+	fb_set_var(fbi, &fbvar);
+
+	ipu_disp_set_window_pos(MEM_FG_SYNC, cam->win.w.left,
+			cam->win.w.top);
+
+	acquire_console_sem();
+	fb_blank(fbi, FB_BLANK_UNBLANK);
+	release_console_sem();
+
+	memset(&vf, 0, sizeof(ipu_channel_params_t));
+	ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width,
+				&vf.csi_prp_vf_mem.in_height, cam->csi);
+	vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
+	vf.csi_prp_vf_mem.out_width = cam->win.w.width;
+	vf.csi_prp_vf_mem.out_height = cam->win.w.height;
+	vf.csi_prp_vf_mem.csi = cam->csi;
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		vf.csi_prp_vf_mem.out_width = cam->win.w.height;
+		vf.csi_prp_vf_mem.out_height = cam->win.w.width;
+	}
+	vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format;
+	size = cam->win.w.width * cam->win.w.height * size;
+
+	err = ipu_init_channel(CSI_PRP_VF_MEM, &vf);
+	if (err != 0)
+		goto out_5;
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true);
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0],
+				  (dma_addr_t) cam->vf_bufs[0]);
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1],
+				  (dma_addr_t) cam->vf_bufs[1]);
+	}
+	cam->vf_bufs_size[0] = PAGE_ALIGN(size);
+	cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[0],
+							   (dma_addr_t *) &
+							   cam->vf_bufs[0],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[0] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_4;
+	}
+	cam->vf_bufs_size[1] = PAGE_ALIGN(size);
+	cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[1],
+							   (dma_addr_t *) &
+							   cam->vf_bufs[1],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[1] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_3;
+	}
+	pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
+
+	if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
+		err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER,
+					      vf_out_format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      IPU_ROTATE_NONE, cam->vf_bufs[0],
+					      cam->vf_bufs[1], 0, 0);
+		if (err != 0) {
+			goto out_3;
+		}
+
+		err = ipu_init_channel(MEM_ROT_VF_MEM, NULL);
+		if (err != 0) {
+			printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n");
+			goto out_3;
+		}
+
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER,
+					      vf_out_format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      cam->vf_rotation, cam->vf_bufs[0],
+					      cam->vf_bufs[1], 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
+			goto out_2;
+		}
+
+		if (cam->vf_rotation < IPU_ROTATE_90_RIGHT) {
+			temp = vf.csi_prp_vf_mem.out_width;
+			vf.csi_prp_vf_mem.out_width =
+						vf.csi_prp_vf_mem.out_height;
+			vf.csi_prp_vf_mem.out_height = temp;
+		}
+
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER,
+					      vf_out_format,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      IPU_ROTATE_NONE,
+					      fbi->fix.smem_start +
+					      (fbi->fix.line_length *
+					       fbi->var.yres),
+					      fbi->fix.smem_start, 0, 0);
+
+		if (err != 0) {
+			printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
+			goto out_2;
+		}
+
+		err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n");
+			goto out_2;
+		}
+
+		err = ipu_link_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "Error link MEM_ROT_VF_MEM-MEM_FG_SYNC\n");
+			goto out_1;
+		}
+
+		ipu_enable_channel(CSI_PRP_VF_MEM);
+		ipu_enable_channel(MEM_ROT_VF_MEM);
+
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+	} else {
+		err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER,
+					      vf_out_format, cam->win.w.width,
+					      cam->win.w.height,
+					      cam->win.w.width,
+					      cam->vf_rotation,
+					      fbi->fix.smem_start +
+					      (fbi->fix.line_length *
+					       fbi->var.yres),
+					      fbi->fix.smem_start, 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
+			goto out_4;
+		}
+
+		err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC);
+		if (err < 0) {
+			printk(KERN_ERR "Error linking ipu channels\n");
+			goto out_4;
+		}
+
+		ipu_enable_channel(CSI_PRP_VF_MEM);
+
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+	}
+
+	cam->overlay_active = true;
+	return err;
+
+out_1:
+	ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
+out_2:
+	if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
+		ipu_uninit_channel(MEM_ROT_VF_MEM);
+	}
+out_3:
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0],
+				  (dma_addr_t) cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1],
+				  (dma_addr_t) cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+out_4:
+	ipu_uninit_channel(CSI_PRP_VF_MEM);
+out_5:
+	return err;
+}
+
+/*!
+ * prpvf_stop - stop the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_stop(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0, i = 0;
+	struct fb_info *fbi = NULL;
+	struct fb_var_screeninfo fbvar;
+
+	if (cam->overlay_active == false)
+		return 0;
+
+	for (i = 0; i < num_registered_fb; i++) {
+		char *idstr = registered_fb[i]->fix.id;
+		if (strcmp(idstr, "DISP3 FG") == 0) {
+			fbi = registered_fb[i];
+			break;
+		}
+	}
+
+	if (fbi == NULL) {
+		printk(KERN_ERR "DISP3 FG fb not found\n");
+		return -EPERM;
+	}
+
+	ipu_disp_set_window_pos(MEM_FG_SYNC, 0, 0);
+
+	if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
+		ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
+		ipu_unlink_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC);
+	} else {
+		ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC);
+	}
+
+	ipu_disable_channel(CSI_PRP_VF_MEM, true);
+
+	if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
+		ipu_disable_channel(MEM_ROT_VF_MEM, true);
+		ipu_uninit_channel(MEM_ROT_VF_MEM);
+	}
+	ipu_uninit_channel(CSI_PRP_VF_MEM);
+
+	acquire_console_sem();
+	fb_blank(fbi, FB_BLANK_POWERDOWN);
+	release_console_sem();
+
+	/* Set the overlay frame buffer std to what it is used to be */
+	fbvar = fbi->var;
+	fbvar.nonstd = cam->fb_origin_std;
+	fbvar.activate |= FB_ACTIVATE_FORCE;
+	fb_set_var(fbi, &fbvar);
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false);
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0],
+				  (dma_addr_t) cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1],
+				  (dma_addr_t) cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+
+	cam->overlay_active = false;
+	return err;
+}
+
+/*!
+ * Enable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_vf_enable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_enable_csi(cam->csi);
+}
+
+/*!
+ * Disable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_vf_disable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_disable_csi(cam->csi);
+}
+
+/*!
+ * function to select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int prp_vf_sdc_select(void *private)
+{
+	cam_data *cam;
+	int err = 0;
+	if (private) {
+		cam = (cam_data *) private;
+		cam->vf_start_sdc = prpvf_start;
+		cam->vf_stop_sdc = prpvf_stop;
+		cam->vf_enable_csi = prp_vf_enable_csi;
+		cam->vf_disable_csi = prp_vf_disable_csi;
+		cam->overlay_active = false;
+	} else
+		err = -EIO;
+
+	return err;
+}
+
+/*!
+ * function to de-select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  int
+ */
+int prp_vf_sdc_deselect(void *private)
+{
+	cam_data *cam;
+	int err = 0;
+	err = prpvf_stop(private);
+
+	if (private) {
+		cam = (cam_data *) private;
+		cam->vf_start_sdc = NULL;
+		cam->vf_stop_sdc = NULL;
+		cam->vf_enable_csi = NULL;
+		cam->vf_disable_csi = NULL;
+	}
+	return err;
+}
+
+/*!
+ * Init viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int prp_vf_sdc_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+void __exit prp_vf_sdc_exit(void)
+{
+}
+
+module_init(prp_vf_sdc_init);
+module_exit(prp_vf_sdc_exit);
+
+EXPORT_SYMBOL(prp_vf_sdc_select);
+EXPORT_SYMBOL(prp_vf_sdc_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP VF SDC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
new file mode 100644
index 000000000000..7f0984c42950
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_prp_vf_sdc_bg.c
+ *
+ * @brief IPU Use case for PRP-VF back-ground
+ *
+ * @ingroup IPU
+ */
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <linux/ipu.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+static int buffer_num = 0;
+static int buffer_ready = 0;
+
+/*
+ * Function definitions
+ */
+
+/*!
+ * SDC V-Sync callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id)
+{
+	pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num);
+	if (buffer_ready > 0) {
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		buffer_ready--;
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * VF EOF callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id)
+{
+	pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num);
+
+	ipu_select_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, buffer_num);
+
+	buffer_num = (buffer_num == 0) ? 1 : 0;
+
+	ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, buffer_num);
+	buffer_ready++;
+	return IRQ_HANDLED;
+}
+
+/*!
+ * prpvf_start - start the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	ipu_channel_params_t vf;
+	u32 format;
+	u32 offset;
+	u32 bpp, size = 3;
+	int err = 0;
+
+	if (!cam) {
+		printk(KERN_ERR "private is NULL\n");
+		return -EIO;
+	}
+
+	if (cam->overlay_active == true) {
+		pr_debug("already start.\n");
+		return 0;
+	}
+
+	format = cam->v4l2_fb.fmt.pixelformat;
+	if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
+		bpp = 3, size = 3;
+		pr_info("BGR24\n");
+	} else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
+		bpp = 2, size = 2;
+		pr_info("RGB565\n");
+	} else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
+		bpp = 4, size = 4;
+		pr_info("BGR32\n");
+	} else {
+		printk(KERN_ERR
+		       "unsupported fix format from the framebuffer.\n");
+		return -EINVAL;
+	}
+
+	offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
+	    size * cam->win.w.left;
+
+	if (cam->v4l2_fb.base == 0) {
+		printk(KERN_ERR "invalid frame buffer address.\n");
+	} else {
+		offset += (u32) cam->v4l2_fb.base;
+	}
+
+	memset(&vf, 0, sizeof(ipu_channel_params_t));
+	ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width,
+				&vf.csi_prp_vf_mem.in_height, cam->csi);
+	vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
+	vf.csi_prp_vf_mem.out_width = cam->win.w.width;
+	vf.csi_prp_vf_mem.out_height = cam->win.w.height;
+	vf.csi_prp_vf_mem.csi = cam->csi;
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		vf.csi_prp_vf_mem.out_width = cam->win.w.height;
+		vf.csi_prp_vf_mem.out_height = cam->win.w.width;
+	}
+	vf.csi_prp_vf_mem.out_pixel_fmt = format;
+	size = cam->win.w.width * cam->win.w.height * size;
+
+	err = ipu_init_channel(CSI_PRP_VF_MEM, &vf);
+	if (err != 0)
+		goto out_4;
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true);
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+	}
+	cam->vf_bufs_size[0] = PAGE_ALIGN(size);
+	cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[0],
+							   &cam->vf_bufs[0],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[0] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_3;
+	}
+	cam->vf_bufs_size[1] = PAGE_ALIGN(size);
+	cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[1],
+							   &cam->vf_bufs[1],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[1] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_3;
+	}
+
+	err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER,
+				      format, vf.csi_prp_vf_mem.out_width,
+				      vf.csi_prp_vf_mem.out_height,
+				      vf.csi_prp_vf_mem.out_width,
+				      IPU_ROTATE_NONE, cam->vf_bufs[0],
+				      cam->vf_bufs[1], 0, 0);
+	if (err != 0) {
+		printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
+		goto out_3;
+	}
+	err = ipu_init_channel(MEM_ROT_VF_MEM, NULL);
+	if (err != 0) {
+		printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n");
+		goto out_3;
+	}
+
+	err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER,
+				      format, vf.csi_prp_vf_mem.out_width,
+				      vf.csi_prp_vf_mem.out_height,
+				      vf.csi_prp_vf_mem.out_width,
+				      cam->vf_rotation, cam->vf_bufs[0],
+				      cam->vf_bufs[1], 0, 0);
+	if (err != 0) {
+		printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
+		goto out_2;
+	}
+
+	if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_height,
+					      vf.csi_prp_vf_mem.out_width,
+					      cam->overlay_fb->var.xres * bpp,
+					      IPU_ROTATE_NONE, offset, 0, 0, 0);
+
+		if (err != 0) {
+			printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
+			goto out_2;
+		}
+	} else {
+		err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER,
+					      format,
+					      vf.csi_prp_vf_mem.out_width,
+					      vf.csi_prp_vf_mem.out_height,
+					      cam->overlay_fb->var.xres * bpp,
+					      IPU_ROTATE_NONE, offset, 0, 0, 0);
+		if (err != 0) {
+			printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
+			goto out_2;
+		}
+	}
+
+	ipu_clear_irq(IPU_IRQ_PRP_VF_OUT_EOF);
+	err = ipu_request_irq(IPU_IRQ_PRP_VF_OUT_EOF, prpvf_vf_eof_callback,
+			      0, "Mxc Camera", cam);
+	if (err != 0) {
+		printk(KERN_ERR
+		       "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n");
+		goto out_2;
+	}
+
+	ipu_clear_irq(IPU_IRQ_BG_SF_END);
+	err = ipu_request_irq(IPU_IRQ_BG_SF_END, prpvf_sdc_vsync_callback,
+			      0, "Mxc Camera", NULL);
+	if (err != 0) {
+		printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n");
+		goto out_1;
+	}
+
+	ipu_enable_channel(CSI_PRP_VF_MEM);
+	ipu_enable_channel(MEM_ROT_VF_MEM);
+
+	buffer_num = 0;
+	buffer_ready = 0;
+	ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+
+	cam->overlay_active = true;
+	return err;
+
+      out_1:
+	ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, NULL);
+      out_2:
+	ipu_uninit_channel(MEM_ROT_VF_MEM);
+      out_3:
+	ipu_uninit_channel(CSI_PRP_VF_MEM);
+      out_4:
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[0],
+				  cam->rot_vf_bufs_vaddr[0],
+				  cam->rot_vf_bufs[0]);
+		cam->rot_vf_bufs_vaddr[0] = NULL;
+		cam->rot_vf_bufs[0] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[1],
+				  cam->rot_vf_bufs_vaddr[1],
+				  cam->rot_vf_bufs[1]);
+		cam->rot_vf_bufs_vaddr[1] = NULL;
+		cam->rot_vf_bufs[1] = 0;
+	}
+	return err;
+}
+
+/*!
+ * prpvf_stop - stop the vf task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int prpvf_stop(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam->overlay_active == false)
+		return 0;
+
+	ipu_free_irq(IPU_IRQ_BG_SF_END, NULL);
+
+	ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, cam);
+
+	ipu_disable_channel(CSI_PRP_VF_MEM, true);
+	ipu_disable_channel(MEM_ROT_VF_MEM, true);
+	ipu_uninit_channel(CSI_PRP_VF_MEM);
+	ipu_uninit_channel(MEM_ROT_VF_MEM);
+	ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false);
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[0],
+				  cam->rot_vf_bufs_vaddr[0],
+				  cam->rot_vf_bufs[0]);
+		cam->rot_vf_bufs_vaddr[0] = NULL;
+		cam->rot_vf_bufs[0] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[1],
+				  cam->rot_vf_bufs_vaddr[1],
+				  cam->rot_vf_bufs[1]);
+		cam->rot_vf_bufs_vaddr[1] = NULL;
+		cam->rot_vf_bufs[1] = 0;
+	}
+
+	buffer_num = 0;
+	buffer_ready = 0;
+	cam->overlay_active = false;
+	return 0;
+}
+
+/*!
+ * Enable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_vf_enable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_enable_csi(cam->csi);
+}
+
+/*!
+ * Disable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_vf_disable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_disable_csi(cam->csi);
+}
+
+/*!
+ * function to select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int prp_vf_sdc_select_bg(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->vf_start_sdc = prpvf_start;
+		cam->vf_stop_sdc = prpvf_stop;
+		cam->vf_enable_csi = prp_vf_enable_csi;
+		cam->vf_disable_csi = prp_vf_disable_csi;
+		cam->overlay_active = false;
+	}
+
+	return 0;
+}
+
+/*!
+ * function to de-select PRP-VF as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int prp_vf_sdc_deselect_bg(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+	err = prpvf_stop(private);
+
+	if (cam) {
+		cam->vf_start_sdc = NULL;
+		cam->vf_stop_sdc = NULL;
+		cam->vf_enable_csi = NULL;
+		cam->vf_disable_csi = NULL;
+	}
+	return err;
+}
+
+/*!
+ * Init viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int prp_vf_sdc_init_bg(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit viewfinder task.
+ *
+ * @return  Error code indicating success or failure
+ */
+void __exit prp_vf_sdc_exit_bg(void)
+{
+}
+
+module_init(prp_vf_sdc_init_bg);
+module_exit(prp_vf_sdc_exit_bg);
+
+EXPORT_SYMBOL(prp_vf_sdc_select_bg);
+EXPORT_SYMBOL(prp_vf_sdc_deselect_bg);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_still.c b/drivers/media/video/mxc/capture/ipu_still.c
new file mode 100644
index 000000000000..ded24623ce2a
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_still.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_still.c
+ *
+ * @brief IPU Use case for still image capture
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/ipu.h>
+#include <linux/semaphore.h>
+#include <linux/ipu.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+static int callback_eof_flag;
+#ifndef CONFIG_MXC_IPU_V1
+static int buffer_num;
+#endif
+
+#ifdef CONFIG_MXC_IPU_V1
+static int callback_flag;
+/*
+ * Function definitions
+ */
+/*!
+ * CSI EOF callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id)
+{
+	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+			  callback_flag%2 ? 1 : 0);
+	if (callback_flag == 0)
+		ipu_enable_channel(CSI_MEM);
+
+	callback_flag++;
+	return IRQ_HANDLED;
+}
+#endif
+
+/*!
+ * CSI callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t prp_still_callback(int irq, void *dev_id)
+{
+	cam_data *cam = (cam_data *) dev_id;
+
+	callback_eof_flag++;
+	if (callback_eof_flag < 5) {
+#ifndef CONFIG_MXC_IPU_V1
+		buffer_num = (buffer_num == 0) ? 1 : 0;
+		ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, buffer_num);
+#endif
+	} else {
+		cam->still_counter++;
+		wake_up_interruptible(&cam->still_queue);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * start csi->mem task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_still_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	u32 pixel_fmt;
+	int err;
+	ipu_channel_params_t params;
+
+	if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
+		pixel_fmt = IPU_PIX_FMT_YUV420P;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
+		pixel_fmt = IPU_PIX_FMT_NV12;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
+		pixel_fmt = IPU_PIX_FMT_YUV422P;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
+		pixel_fmt = IPU_PIX_FMT_UYVY;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
+		pixel_fmt = IPU_PIX_FMT_YUYV;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
+		pixel_fmt = IPU_PIX_FMT_BGR24;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
+		pixel_fmt = IPU_PIX_FMT_RGB24;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
+		pixel_fmt = IPU_PIX_FMT_RGB565;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
+		pixel_fmt = IPU_PIX_FMT_BGR32;
+	else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
+		pixel_fmt = IPU_PIX_FMT_RGB32;
+	else {
+		printk(KERN_ERR "format not supported\n");
+		return -EINVAL;
+	}
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, true, true);
+
+	memset(&params, 0, sizeof(params));
+	err = ipu_init_channel(CSI_MEM, &params);
+	if (err != 0)
+		return err;
+
+	err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER,
+				      pixel_fmt, cam->v2f.fmt.pix.width,
+				      cam->v2f.fmt.pix.height,
+				      cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
+				      cam->still_buf[0], cam->still_buf[1],
+				      0, 0);
+	if (err != 0)
+		return err;
+
+#ifdef CONFIG_MXC_IPU_V1
+	ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF);
+	err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback,
+			      0, "Mxc Camera", cam);
+	if (err != 0) {
+		printk(KERN_ERR "Error registering irq.\n");
+		return err;
+	}
+	callback_flag = 0;
+	callback_eof_flag = 0;
+	ipu_clear_irq(IPU_IRQ_SENSOR_EOF);
+	err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback,
+			      0, "Mxc Camera", NULL);
+	if (err != 0) {
+		printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF \n");
+		return err;
+	}
+#else
+	callback_eof_flag = 0;
+	buffer_num = 0;
+
+	ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF);
+	err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF, prp_still_callback,
+			      0, "Mxc Camera", cam);
+	if (err != 0) {
+		printk(KERN_ERR "Error registering irq.\n");
+		return err;
+	}
+
+	ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0);
+	ipu_enable_channel(CSI_MEM);
+	ipu_enable_csi(cam->csi);
+#endif
+
+	return err;
+}
+
+/*!
+ * stop csi->mem encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int prp_still_stop(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+#ifdef CONFIG_MXC_IPU_V1
+	ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL);
+	ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam);
+#else
+	ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam);
+#endif
+
+	ipu_disable_csi(cam->csi);
+	ipu_disable_channel(CSI_MEM, true);
+	ipu_uninit_channel(CSI_MEM);
+	ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, false, false);
+
+	return err;
+}
+
+/*!
+ * function to select CSI_MEM as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+int prp_still_select(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->csi_start = prp_still_start;
+		cam->csi_stop = prp_still_stop;
+	}
+
+	return 0;
+}
+
+/*!
+ * function to de-select CSI_MEM as the working path
+ *
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+int prp_still_deselect(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	err = prp_still_stop(cam);
+
+	if (cam) {
+		cam->csi_start = NULL;
+		cam->csi_stop = NULL;
+	}
+
+	return err;
+}
+
+/*!
+ * Init the Encorder channels
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int prp_still_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit the Encorder channels
+ *
+ */
+void __exit prp_still_exit(void)
+{
+}
+
+module_init(prp_still_init);
+module_exit(prp_still_exit);
+
+EXPORT_SYMBOL(prp_still_select);
+EXPORT_SYMBOL(prp_still_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/mc521da.c b/drivers/media/video/mxc/capture/mc521da.c
new file mode 100644
index 000000000000..a8ff84fb4c84
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mc521da.c
@@ -0,0 +1,648 @@
+/*
+ * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc521da.c
+ *
+ * @brief MC521DA camera driver functions
+ *
+ * @ingroup Camera
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include "mxc_v4l2_capture.h"
+
+#define MC521DA_I2C_ADDRESS	0x22
+#define MC521DA_TERM		0xFF
+
+typedef struct {
+	u16 width;
+	u16 height;
+} mc521da_image_format;
+
+struct mc521da_reg {
+	u8 reg;
+	u8 val;
+};
+
+static sensor_interface *interface_param = NULL;
+
+static mc521da_image_format format[2] = {
+	{
+	 .width = 1600,
+	 .height = 1200,
+	 },
+	{
+	 .width = 640,
+	 .height = 480,
+	 },
+};
+
+const static struct mc521da_reg mc521da_initial[] = {
+	/*----------------------------------------------------------
+	 * Sensor Setting Start
+	 *----------------------------------------------------------
+	 */
+	{0xff, 0x01},		/* Sensor setting start */
+	{0x01, 0x10},		/* Wavetable script, generated by waveman */
+	{0x10, 0x64},
+	{0x03, 0x00}, {0x04, 0x06}, {0x05, 0x30}, {0x06, 0x02}, {0x08, 0x00},
+	{0x03, 0x01}, {0x04, 0x41}, {0x05, 0x70}, {0x06, 0x03}, {0x08, 0x00},
+	{0x03, 0x02}, {0x04, 0x55}, {0x05, 0x30}, {0x06, 0x03}, {0x08, 0x00},
+	{0x03, 0x03}, {0x04, 0x5A}, {0x05, 0x30}, {0x06, 0x02}, {0x08, 0x00},
+	{0x03, 0x04}, {0x04, 0x7A}, {0x05, 0x30}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x05}, {0x04, 0x9C}, {0x05, 0x30}, {0x06, 0x0F}, {0x08, 0x00},
+	{0x03, 0x06}, {0x04, 0x73}, {0x05, 0x31}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x07}, {0x04, 0x2D}, {0x05, 0x3B}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x08}, {0x04, 0x32}, {0x05, 0x33}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x09}, {0x04, 0x67}, {0x05, 0x63}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x0a}, {0x04, 0x6C}, {0x05, 0x23}, {0x06, 0x0E}, {0x08, 0x00},
+	{0x03, 0x0b}, {0x04, 0x71}, {0x05, 0x23}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x0c}, {0x04, 0x30}, {0x05, 0x2F}, {0x06, 0x06}, {0x08, 0x00},
+	{0x03, 0x0d}, {0x04, 0x00}, {0x05, 0x00}, {0x06, 0x06}, {0x08, 0x00},
+	{0x07, 0x0e},
+
+	/* Start Address */
+	{0x10, 0x64}, {0x14, 0x10}, {0x15, 0x00},
+
+	/* SYNC */
+	{0x18, 0x40}, {0x19, 0x00}, {0x1A, 0x03}, {0x1B, 0x00},
+
+	/* X-Y Mirror */
+	{0x11, 0x00}, {0xda, 0x00},	/* X mirror OFF, Y Mirror OFF */
+
+	/* Frame height */
+	{0x1c, 0x13}, {0x1d, 0x04}, {0x0e, 0x4b}, {0x0f, 0x05},
+	{0x9e, 0x04}, {0x9d, 0xc6}, {0xcc, 0x14}, {0xcd, 0x05},
+
+	/* Frame width */
+	{0x0c, 0x35}, {0x0d, 0x07}, {0x9b, 0x10}, {0x9c, 0x07},
+	{0x93, 0x21},
+
+	{0x01, 0x01}, {0x40, 0x00}, {0x41, 0x00}, {0x42, 0xf0},
+	{0x43, 0x03}, {0x44, 0x0a}, {0x45, 0x00}, {0x3b, 0x40},
+	{0x38, 0x18}, {0x3c, 0x00}, {0x20, 0x00}, {0x21, 0x01},
+	{0x22, 0x00}, {0x23, 0x01}, {0x24, 0x00}, {0x25, 0x01},
+	{0x26, 0x00}, {0x27, 0x01}, {0xb9, 0x04}, {0xb8, 0xc3},
+	{0xbb, 0x04}, {0xba, 0xc3}, {0xbf, 0x04}, {0xbe, 0xc3},
+
+	/* Ramp */
+	{0x57, 0x07}, {0x56, 0xd6}, {0x55, 0x03}, {0x54, 0x74},
+	{0x9f, 0x99}, {0x94, 0x80}, {0x91, 0x78}, {0x92, 0x8b},
+
+	/* Output Mode */
+	{0x52, 0x10}, {0x51, 0x00},
+
+	/* Analog Gain and Output driver */
+	{0x28, 0x00}, {0xdd, 0x82}, {0xdb, 0x00}, {0xdc, 0x00},
+
+	/* Update */
+	{0x00, 0x84},
+
+	/* PLL  ADC clock = 75 MHz */
+	{0xb5, 0x60}, {0xb4, 0x02}, {0xb5, 0x20},
+
+	/*----------------------------------------------*/
+	/*      ISP Setting Start                       */
+	/*----------------------------------------------*/
+	{0xff, 0x02},
+	{0x01, 0xbd}, {0x02, 0xf8}, {0x03, 0x3a}, {0x04, 0x00}, {0x0e, 0x00},
+
+	/* Output mode */
+	{0x88, 0x00}, {0x87, 0x11},
+
+	/* Threshold */
+	{0xb6, 0x1b}, {0x0d, 0xc0}, {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00},
+
+	/* Image Effect */
+	{0x3f, 0x80}, {0x40, 0x00}, {0x41, 0x00}, {0x42, 0x80}, {0x43, 0x00},
+	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x56, 0x80}, {0x57, 0x20},
+	{0x58, 0x20}, {0x59, 0x02}, {0x5a, 0x00}, {0x5b, 0x78}, {0x5c, 0x7c},
+	{0x5d, 0x84}, {0x5e, 0x85}, {0x5f, 0x78}, {0x60, 0x7e}, {0x61, 0x82},
+	{0x62, 0x85}, {0x63, 0x00}, {0x64, 0x80}, {0x65, 0x00}, {0x66, 0x80},
+	{0x67, 0x80}, {0x68, 0x80},
+
+	/* Auto Focus */
+	{0x6e, 0x02}, {0x6f, 0xe5}, {0x70, 0x08}, {0x71, 0x01}, {0x72, 0x00},
+
+	/* Decimator */
+	{0x78, 0xff}, {0x79, 0xff}, {0x7a, 0x70}, {0x7b, 0x00}, {0x7c, 0x00},
+	{0x7d, 0x00}, {0x7e, 0xc8}, {0x7f, 0xc8}, {0x80, 0x96}, {0x81, 0x96},
+	{0x82, 0x00}, {0x83, 0x00}, {0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00},
+
+	/* Luminance Info */
+	{0xf9, 0x20}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08},
+	{0xf9, 0xa0}, {0xb7, 0x10}, {0xb9, 0x00},
+	{0xf9, 0x40}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08},
+	{0xf9, 0xc0}, {0xb7, 0x08}, {0xb9, 0x00},
+	{0xf9, 0x60}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08},
+	{0xf9, 0xe0}, {0xb7, 0x05}, {0xb9, 0x00},
+	{0xf9, 0x00}, {0xb7, 0x03}, {0xb8, 0x2d}, {0xb9, 0xcd},
+	{0xf9, 0x80}, {0xb7, 0x02}, {0xb9, 0x00},
+
+	/* AE */
+	{0x8a, 0x00}, {0x89, 0xc0}, {0x8c, 0x32}, {0x8d, 0x96}, {0x8e, 0x25},
+	{0x8f, 0x70}, {0x90, 0x12}, {0x91, 0x41}, {0x9e, 0x2e}, {0x9f, 0x2e},
+	{0xa0, 0x0b}, {0xa1, 0x71}, {0xa2, 0xb0}, {0xa3, 0x09}, {0xa4, 0x89},
+	{0xa5, 0x68}, {0xa6, 0x1a}, {0xa7, 0xb3}, {0xa8, 0xf0}, {0xa9, 0x19},
+	{0xaa, 0x6a}, {0xab, 0x6b}, {0xac, 0x01}, {0xad, 0xe8}, {0xae, 0x48},
+	{0xaf, 0x01}, {0xb0, 0x96}, {0xb1, 0xe6}, {0xb2, 0x03}, {0xb3, 0x00},
+	{0xb4, 0x10}, {0xb5, 0x00}, {0xb6, 0x04}, {0xba, 0x44}, {0xbb, 0x3a},
+	{0xbc, 0x01}, {0xbd, 0x08}, {0xbe, 0xa0}, {0xbf, 0x01}, {0xc0, 0x82},
+	{0x8a, 0xe1}, {0x8b, 0x8c},
+
+	/* AWB */
+	{0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x40}, {0xcb, 0xB0}, {0xcc, 0x40},
+	{0xcd, 0xff}, {0xce, 0x19}, {0xcf, 0x40}, {0xd0, 0x01}, {0xd1, 0x43},
+	{0xd2, 0x80}, {0xd3, 0x80}, {0xd4, 0xf1}, {0xdf, 0x00}, {0xe0, 0x8f},
+	{0xe1, 0x8f}, {0xe2, 0x53}, {0xe3, 0x97}, {0xe4, 0x1f}, {0xe5, 0x3b},
+	{0xe6, 0x9c}, {0xe7, 0x2e}, {0xe8, 0x03}, {0xe9, 0x02},
+
+	/* Neutral CCM */
+	{0xfa, 0x00}, {0xd5, 0x3f}, {0xd6, 0x8c}, {0xd7, 0x43}, {0xd8, 0x08},
+	{0xd9, 0x27}, {0xda, 0x7e}, {0xdb, 0x17}, {0xdc, 0x1a}, {0xdd, 0x47},
+	{0xde, 0xa1},
+
+	/* Blue CCM */
+	{0xfa, 0x01}, {0xd5, 0x3f}, {0xd6, 0x77}, {0xd7, 0x34}, {0xd8, 0x03},
+	{0xd9, 0x18}, {0xda, 0x6e}, {0xdb, 0x16}, {0xdc, 0x0f}, {0xdd, 0x29},
+	{0xde, 0x77},
+
+	/* Red CCM */
+	{0xfa, 0x02}, {0xd5, 0x3f}, {0xd6, 0x7d}, {0xd7, 0x2f}, {0xd8, 0x0e},
+	{0xd9, 0x1e}, {0xda, 0x76}, {0xdb, 0x18}, {0xdc, 0x29}, {0xdd, 0x51},
+	{0xde, 0xba},
+
+	/* AWB */
+	{0xea, 0x00}, {0xeb, 0x1a}, {0xc8, 0x33}, {0xc9, 0xc2},
+
+	{0xed, 0x02}, {0xee, 0x02},
+
+	/* AFD */
+	{0xf0, 0x11}, {0xf1, 0x03}, {0xf2, 0x05}, {0xf5, 0x05}, {0xf6, 0x32},
+	{0xf7, 0x32},
+
+	/* Lens Shading */
+	{0xf9, 0x00}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0xf2}, {0x08, 0x00},
+	{0x09, 0x00}, {0x0a, 0xf2}, {0x0b, 0xff}, {0x0c, 0xff},
+	{0xf9, 0x01}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x8b}, {0x08, 0x16},
+	{0x09, 0x16}, {0x0a, 0x8b}, {0x0b, 0xff}, {0x0c, 0xe0},
+	{0xf9, 0x02}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x8b}, {0x08, 0x16},
+	{0x09, 0x16}, {0x0a, 0x8b}, {0x0b, 0xff}, {0x0c, 0xe0},
+	{0xf9, 0x03}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x7c}, {0x08, 0x26},
+	{0x09, 0x26}, {0x0a, 0x7c}, {0x0b, 0xd0}, {0x0c, 0xe0},
+	{0xf9, 0x04}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00},
+	{0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xe0},
+	{0xf9, 0x05}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00},
+	{0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0},
+	{0xf9, 0x06}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00},
+	{0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0},
+	{0xf9, 0x07}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00},
+	{0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0},
+
+	/* Edge setting */
+	{0x73, 0x68}, {0x74, 0x40}, {0x75, 0x00}, {0x76, 0xff}, {0x77, 0x80},
+	{0x4f, 0x80}, {0x50, 0x82}, {0x51, 0x82}, {0x52, 0x08},
+
+	/* Interpolation Setting */
+	{0x23, 0x7f}, {0x22, 0x08}, {0x18, 0xff}, {0x19, 0x00},
+	{0x40, 0x00}, {0x53, 0xff}, {0x54, 0x0a}, {0x55, 0xc2},
+	{0x1b, 0x18},
+
+	{0xfa, 0x00}, {0x15, 0x0c}, {0x22, 0x00}, {0x0e, 0xef}, {0x1f, 0x1d},
+	{0x20, 0x2d}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03}, {0x0e, 0xee},
+	{0x12, 0x10}, {0x16, 0x10}, {0x17, 0x02}, {0x1a, 0x01},
+	{0xfa, 0x04}, {0x0e, 0xef}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03},
+	{0x1f, 0x11}, {0x20, 0x11}, {0x0e, 0xee}, {0x12, 0x03}, {0x16, 0x10},
+	{0x17, 0x02}, {0x1a, 0xee},
+	{0xfa, 0x08}, {0x0e, 0xef}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03},
+	{0x1f, 0x00}, {0x20, 0x00}, {0x0e, 0xee}, {0x12, 0x03}, {0x16, 0x10},
+	{0x17, 0x02}, {0x1a, 0x22},
+
+	/* Gamma Correction */
+	{0x27, 0x62}, {0x28, 0x00}, {0x27, 0x62}, {0x28, 0x00}, {0x29, 0x00},
+	{0x2a, 0x00}, {0x2f, 0x03}, {0x30, 0x10}, {0x31, 0x2b}, {0x32, 0x50},
+	{0x33, 0x70}, {0x34, 0x90}, {0x35, 0xB0}, {0x36, 0xD0}, {0x37, 0x00},
+	{0x38, 0x18}, {0x39, 0x57}, {0x3a, 0x89}, {0x3b, 0xac}, {0x3c, 0xc9},
+	{0x3d, 0xde}, {0x3e, 0xef}, {0x2b, 0x00}, {0x2c, 0x00}, {0x2d, 0x40},
+	{0x2e, 0xab},
+
+	/* Contrast */
+	{0x47, 0x10}, {0x48, 0x1f}, {0x49, 0xe3}, {0x4a, 0xf0}, {0x4b, 0x08},
+	{0x4c, 0x14}, {0x4d, 0xe9}, {0x4e, 0xf5}, {0x98, 0x8a},
+
+	{0xfa, 0x00},
+	{MC521DA_TERM, MC521DA_TERM}
+};
+
+static int mc521da_attach(struct i2c_adapter *adapter);
+static int mc521da_detach(struct i2c_client *client);
+
+static struct i2c_driver mc521da_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "MC521DA Client",
+		   },
+	.attach_adapter = mc521da_attach,
+	.detach_client = mc521da_detach,
+};
+
+static struct i2c_client mc521da_i2c_client = {
+	.name = "MC521DA I2C dev",
+	.addr = MC521DA_I2C_ADDRESS,
+	.driver = &mc521da_i2c_driver,
+};
+
+static inline int mc521da_read_reg(u8 reg)
+{
+	return i2c_smbus_read_byte_data(&mc521da_i2c_client, reg);
+}
+
+static inline int mc521da_write_reg(u8 reg, u8 val)
+{
+	return i2c_smbus_write_byte_data(&mc521da_i2c_client, reg, val);
+}
+
+static int mc521da_write_regs(const struct mc521da_reg reglist[])
+{
+	int err;
+	const struct mc521da_reg *next = reglist;
+
+	while (!((next->reg == MC521DA_TERM) && (next->val == MC521DA_TERM))) {
+		err = mc521da_write_reg(next->reg, next->val);
+		if (err) {
+			return err;
+		}
+		next++;
+	}
+	return 0;
+}
+
+/*!
+ * mc521da sensor downscale function
+ * @param downscale            bool
+ * @return  Error code indicating success or failure
+ */
+static u8 mc521da_sensor_downscale(bool downscale)
+{
+	u8 data;
+	u32 i = 0;
+
+	if (downscale == true) {
+		// VGA
+		mc521da_write_reg(0xff, 0x01);
+
+		mc521da_write_reg(0x52, 0x30);
+		mc521da_write_reg(0x51, 0x00);
+
+		mc521da_write_reg(0xda, 0x01);
+		mc521da_write_reg(0x00, 0x8C);
+
+		/* Wait for changes to take effect */
+		while (i < 256) {
+			i++;
+			data = mc521da_read_reg(0x00);
+			if ((data & 0x80) == 0)
+				break;
+			msleep(5);
+		}
+
+		/* ISP */
+		mc521da_write_reg(0xff, 0x02);
+
+		mc521da_write_reg(0x03, 0x3b);	/* Enable Decimator */
+
+		mc521da_write_reg(0x7a, 0x74);
+		mc521da_write_reg(0x7b, 0x01);
+		mc521da_write_reg(0x7e, 0x50);
+		mc521da_write_reg(0x7f, 0x50);
+		mc521da_write_reg(0x80, 0x3c);
+		mc521da_write_reg(0x81, 0x3c);
+	} else {
+		//UXGA
+		mc521da_write_reg(0xff, 0x01);
+		mc521da_write_reg(0x52, 0x10);
+		mc521da_write_reg(0x51, 0x00);
+		mc521da_write_reg(0xda, 0x00);
+
+		/* update */
+		mc521da_write_reg(0x00, 0x84);
+
+		/* Wait for changes to take effect */
+		while (i < 256) {
+			i++;
+			data = mc521da_read_reg(0x00);
+			if ((data & 0x80) == 0)
+				break;
+			msleep(5);
+		}
+
+		/* ISP */
+		mc521da_write_reg(0xff, 0x02);
+
+		mc521da_write_reg(0x03, 0x3a);
+
+		mc521da_write_reg(0x7a, 0x70);
+		mc521da_write_reg(0x7b, 0x00);
+		mc521da_write_reg(0x7e, 0xc8);
+		mc521da_write_reg(0x7f, 0xc8);
+		mc521da_write_reg(0x80, 0x96);
+		mc521da_write_reg(0x81, 0x96);
+	}
+
+	return 0;
+}
+
+/*!
+ * mc521da sensor interface Initialization
+ * @param param            sensor_interface *
+ * @param width            u32
+ * @param height           u32
+ * @return  None
+ */
+static void mc521da_interface(sensor_interface * param, u32 width, u32 height)
+{
+	param->clk_mode = 0x0;	//gated
+	param->pixclk_pol = 0x0;
+	param->data_width = 0x1;
+	param->data_pol = 0x0;
+	param->ext_vsync = 0x0;
+	param->Vsync_pol = 0x0;
+	param->Hsync_pol = 0x0;
+	param->width = width - 1;
+	param->height = height - 1;
+	param->active_width = width;
+	param->active_height = height;
+	param->pixel_fmt = IPU_PIX_FMT_UYVY;
+}
+
+extern void gpio_sensor_reset(bool flag);
+
+/*!
+ * mc521da Reset function
+ *
+ * @return  None
+ */
+static sensor_interface *mc521da_reset(void)
+{
+	if (interface_param == NULL)
+		return NULL;
+
+	mc521da_interface(interface_param, format[1].width, format[1].height);
+	set_mclk_rate(&interface_param->mclk);
+
+	gpio_sensor_reset(true);
+	msleep(10);
+	gpio_sensor_reset(false);
+	msleep(50);
+
+	return interface_param;
+}
+
+/*!
+ * mc521da sensor configuration
+ *
+ * @param frame_rate       int 	*
+ * @param high_quality     int
+ * @return  sensor_interface *
+ */
+static sensor_interface *mc521da_config(int *frame_rate, int high_quality)
+{
+	int num_clock_per_row, err;
+	int max_rate = 0;
+	int index = 1;
+	u16 frame_height;
+
+	if (high_quality == 1)
+		index = 0;
+
+	err = mc521da_write_regs(mc521da_initial);
+	if (err) {
+		/* Reduce the MCLK */
+		interface_param->mclk = 20000000;
+		mc521da_reset();
+
+		printk(KERN_INFO "mc521da: mclk reduced\n");
+		mc521da_write_regs(mc521da_initial);
+	}
+
+	mc521da_interface(interface_param, format[index].width,
+			  format[index].height);
+
+	if (index == 0) {
+		mc521da_sensor_downscale(false);
+	} else {
+		mc521da_sensor_downscale(true);
+	}
+
+	num_clock_per_row = 1845;
+	max_rate = interface_param->mclk * 3 * (index + 1)
+	    / (2 * num_clock_per_row * 1300);
+
+	if ((*frame_rate > max_rate) || (*frame_rate == 0)) {
+		*frame_rate = max_rate;
+	}
+
+	frame_height = 1300 * max_rate / (*frame_rate);
+
+	*frame_rate = interface_param->mclk * 3 * (index + 1)
+	    / (2 * num_clock_per_row * frame_height);
+
+	mc521da_write_reg(0xff, 0x01);
+	mc521da_write_reg(0xE, frame_height & 0xFF);
+	mc521da_write_reg(0xF, (frame_height & 0xFF00) >> 8);
+	mc521da_write_reg(0xCC, frame_height & 0xFF);
+	mc521da_write_reg(0xCD, (frame_height & 0xFF00) >> 8);
+
+	return interface_param;
+}
+
+/*!
+ * mc521da sensor set color configuration
+ *
+ * @param bright       int
+ * @param saturation   int
+ * @param red          int
+ * @param green        int
+ * @param blue         int
+ * @return  None
+ */
+static void
+mc521da_set_color(int bright, int saturation, int red, int green, int blue)
+{
+	/* Select ISP */
+	mc521da_write_reg(0xff, 0x02);
+
+	mc521da_write_reg(0x41, bright);
+	mc521da_write_reg(0xca, red);
+	mc521da_write_reg(0xcb, green);
+	mc521da_write_reg(0xcc, blue);
+}
+
+/*!
+ * mc521da sensor get color configuration
+ *
+ * @param bright       int *
+ * @param saturation   int *
+ * @param red          int *
+ * @param green        int *
+ * @param blue         int *
+ * @return  None
+ */
+static void
+mc521da_get_color(int *bright, int *saturation, int *red, int *green, int *blue)
+{
+	*saturation = 0;
+
+	/* Select ISP */
+	mc521da_write_reg(0xff, 0x02);
+
+	*bright = mc521da_read_reg(0x41);
+	*red = mc521da_read_reg(0xCA);
+	*green = mc521da_read_reg(0xCB);
+	*blue = mc521da_read_reg(0xCC);
+}
+
+struct camera_sensor camera_sensor_if = {
+      set_color:mc521da_set_color,
+      get_color:mc521da_get_color,
+      config:mc521da_config,
+      reset:mc521da_reset,
+};
+
+/*!
+ * mc521da I2C detect_client function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @param address            int
+ * @param kind               int
+ *
+ * @return  Error code indicating success or failure
+ */
+static int mc521da_detect_client(struct i2c_adapter *adapter, int address,
+				 int kind)
+{
+	mc521da_i2c_client.adapter = adapter;
+	if (i2c_attach_client(&mc521da_i2c_client)) {
+		mc521da_i2c_client.adapter = NULL;
+		printk(KERN_ERR "mc521da_attach: i2c_attach_client failed\n");
+		return -1;
+	}
+
+	interface_param = (sensor_interface *)
+	    kmalloc(sizeof(sensor_interface), GFP_KERNEL);
+	if (!interface_param) {
+		printk(KERN_ERR "mc521da_attach: kmalloc failed \n");
+		return -1;
+	}
+
+	interface_param->mclk = 25000000;
+
+	printk(KERN_INFO "mc521da Detected\n");
+
+	return 0;
+}
+
+static unsigned short normal_i2c[] = { MC521DA_I2C_ADDRESS, I2C_CLIENT_END };
+
+/* Magic definition of all other variables and things */
+I2C_CLIENT_INSMOD;
+
+static int mc521da_attach(struct i2c_adapter *adap)
+{
+	uint32_t mclk = 25000000;
+	struct clk *clk;
+	int err;
+
+	clk = clk_get(NULL, "csi_clk");
+	clk_enable(clk);
+	set_mclk_rate(&mclk);
+
+	gpio_sensor_reset(true);
+	msleep(10);
+	gpio_sensor_reset(false);
+	msleep(100);
+
+	err = i2c_probe(adap, &addr_data, &mc521da_detect_client);
+
+	clk_disable(clk);
+	clk_put(clk);
+
+	return err;
+}
+
+/*!
+ * mc521da I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int mc521da_detach(struct i2c_client *client)
+{
+	int err;
+
+	if (!mc521da_i2c_client.adapter)
+		return -1;
+
+	err = i2c_detach_client(&mc521da_i2c_client);
+	mc521da_i2c_client.adapter = NULL;
+
+	if (interface_param)
+		kfree(interface_param);
+	interface_param = NULL;
+
+	return err;
+}
+
+extern void gpio_sensor_active(void);
+extern void gpio_sensor_inactive(void);
+
+/*!
+ * mc521da init function
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int mc521da_init(void)
+{
+	gpio_sensor_active();
+	return i2c_add_driver(&mc521da_i2c_driver);
+}
+
+/*!
+ * mc521da cleanup function
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit mc521da_clean(void)
+{
+	i2c_del_driver(&mc521da_i2c_driver);
+	gpio_sensor_inactive();
+}
+
+module_init(mc521da_init);
+module_exit(mc521da_clean);
+
+/* Exported symbols for modules. */
+EXPORT_SYMBOL(camera_sensor_if);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC521DA Camera Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/mt9v111.c b/drivers/media/video/mxc/capture/mt9v111.c
new file mode 100644
index 000000000000..c95a20683924
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mt9v111.c
@@ -0,0 +1,1076 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mt9v111.c
+ *
+ * @brief mt9v111 camera driver functions
+ *
+ * @ingroup Camera
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <media/v4l2-int-device.h>
+#include "mxc_v4l2_capture.h"
+#include "mt9v111.h"
+
+#ifdef MT9V111_DEBUG
+static u16 testpattern = 0;
+#endif
+
+static mt9v111_conf mt9v111_device;
+
+/*!
+ * Holds the current frame rate.
+ */
+static int reset_frame_rate = MT9V111_FRAME_RATE;
+
+struct sensor {
+	const struct mt9v111_platform_data *platform_data;
+	struct v4l2_int_device *v4l2_int_device;
+	struct i2c_client *i2c_client;
+	struct v4l2_pix_format pix;
+	struct v4l2_captureparm streamcap;
+	bool on;
+
+	/* control settings */
+	int brightness;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+} mt9v111_data;
+
+extern void gpio_sensor_active(void);
+extern void gpio_sensor_inactive(void);
+
+static int mt9v111_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id);
+static int mt9v111_remove(struct i2c_client *client);
+
+static const struct i2c_device_id mt9v111_id[] = {
+	{"mt9v111", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, mt9v111_id);
+
+static struct i2c_driver mt9v111_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "mt9v111",
+		   },
+	.probe = mt9v111_probe,
+	.remove = mt9v111_remove,
+	.id_table = mt9v111_id,
+/* To add power management add .suspend and .resume functions */
+};
+
+/*
+ * Function definitions
+ */
+
+#ifdef MT9V111_DEBUG
+static inline int mt9v111_read_reg(u8 reg)
+{
+	int val = i2c_smbus_read_word_data(mt9v111_data.i2c_client, reg);
+	if (val != -1)
+		val = cpu_to_be16(val);
+	return val;
+}
+#endif
+
+/*!
+ * Writes to the register via I2C.
+ */
+static inline int mt9v111_write_reg(u8 reg, u16 val)
+{
+	pr_debug("In mt9v111_write_reg (0x%x, 0x%x)\n", reg, val);
+	pr_debug("   write reg %x val %x.\n", reg, val);
+
+	return i2c_smbus_write_word_data(mt9v111_data.i2c_client,
+					 reg, cpu_to_be16(val));
+}
+
+/*!
+ * Initialize mt9v111_sensor_lib
+ * Libarary for Sensor configuration through I2C
+ *
+ * @param       coreReg       Core Registers
+ * @param       ifpReg        IFP Register
+ *
+ * @return status
+ */
+static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg)
+{
+	u8 reg;
+	u16 data;
+	u8 error = 0;
+
+	pr_debug("In mt9v111_sensor_lib\n");
+
+	/*
+	 * setup to IFP registers
+	 */
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111I_MODE_CONTROL;
+	data = ifpReg->modeControl;
+	mt9v111_write_reg(reg, data);
+
+	/* Output format */
+	reg = MT9V111I_FORMAT_CONTROL;
+	data = ifpReg->formatControl;	/* Set bit 12 */
+	mt9v111_write_reg(reg, data);
+
+	/* AE limit 4 */
+	reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE;
+	data = ifpReg->gainLimitAE;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_OUTPUT_FORMAT_CTRL2;
+	data = ifpReg->outputFormatCtrl2;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_AE_SPEED;
+	data = ifpReg->AESpeed;
+	mt9v111_write_reg(reg, data);
+
+	/* output image size */
+	reg = MT9V111i_H_PAN;
+	data = 0x8000 | ifpReg->HPan;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_ZOOM;
+	data = 0x8000 | ifpReg->HZoom;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_SIZE;
+	data = 0x8000 | ifpReg->HSize;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_PAN;
+	data = 0x8000 | ifpReg->VPan;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_ZOOM;
+	data = 0x8000 | ifpReg->VZoom;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_V_SIZE;
+	data = 0x8000 | ifpReg->VSize;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111i_H_PAN;
+	data = ~0x8000 & ifpReg->HPan;
+	mt9v111_write_reg(reg, data);
+#if 0
+	reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM;
+	data = ifpReg->upperShutterDelayLi;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_SHUTTER_60;
+	data = ifpReg->shutter_width_60;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_SEARCH_FLICK_60;
+	data = ifpReg->search_flicker_60;
+	mt9v111_write_reg(reg, data);
+#endif
+
+	/*
+	 * setup to sensor core registers
+	 */
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = coreReg->addressSelect;
+	mt9v111_write_reg(reg, data);
+
+	/* enable changes and put the Sync bit on */
+	reg = MT9V111S_OUTPUT_CTRL;
+	data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
+	mt9v111_write_reg(reg, data);
+
+	/* min PIXCLK - Default */
+	reg = MT9V111S_PIXEL_CLOCK_SPEED;
+	data = coreReg->pixelClockSpeed;
+	mt9v111_write_reg(reg, data);
+
+	/* Setup image flipping / Dark rows / row/column skip */
+	reg = MT9V111S_READ_MODE;
+	data = coreReg->readMode;
+	mt9v111_write_reg(reg, data);
+
+	/* zoom 0 */
+	reg = MT9V111S_DIGITAL_ZOOM;
+	data = coreReg->digitalZoom;
+	mt9v111_write_reg(reg, data);
+
+	/* min H-blank */
+	reg = MT9V111S_HOR_BLANKING;
+	data = coreReg->horizontalBlanking;
+	mt9v111_write_reg(reg, data);
+
+	/* min V-blank */
+	reg = MT9V111S_VER_BLANKING;
+	data = coreReg->verticalBlanking;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111S_SHUTTER_WIDTH;
+	data = coreReg->shutterWidth;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111S_SHUTTER_DELAY;
+	data = ifpReg->upperShutterDelayLi;
+	mt9v111_write_reg(reg, data);
+
+	/* changes become effective */
+	reg = MT9V111S_OUTPUT_CTRL;
+	data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000;
+	mt9v111_write_reg(reg, data);
+
+	return error;
+}
+
+/*!
+ * MT9V111 frame rate calculate
+ *
+ * @param frame_rate       int *
+ * @param mclk             int
+ * @return  None
+ */
+static void mt9v111_rate_cal(int *frame_rate, int mclk)
+{
+	int num_clock_per_row;
+	int max_rate = 0;
+
+	pr_debug("In mt9v111_rate_cal\n");
+
+	num_clock_per_row = (MT9V111_MAX_WIDTH + 114 + MT9V111_HORZBLANK_MIN)
+			* 2;
+	max_rate = mclk / (num_clock_per_row *
+			   (MT9V111_MAX_HEIGHT + MT9V111_VERTBLANK_DEFAULT));
+
+	if ((*frame_rate > max_rate) || (*frame_rate == 0)) {
+		*frame_rate = max_rate;
+	}
+
+	mt9v111_device.coreReg->verticalBlanking
+	    = mclk / (*frame_rate * num_clock_per_row) - MT9V111_MAX_HEIGHT;
+
+	reset_frame_rate = *frame_rate;
+}
+
+/*!
+ * MT9V111 sensor configuration
+ */
+void mt9v111_config(void)
+{
+	pr_debug("In mt9v111_config\n");
+
+	mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA;
+	mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP;
+
+	mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT;
+	mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH;
+	mt9v111_device.coreReg->zoomColStart = 0;
+	mt9v111_device.coreReg->zomRowStart = 0;
+	mt9v111_device.coreReg->digitalZoom = 0x0;
+
+	mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT;
+	mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN;
+	mt9v111_device.coreReg->pixelClockSpeed = 0;
+	mt9v111_device.coreReg->readMode = 0xd0a1;
+
+	mt9v111_device.ifpReg->outputFormatCtrl2 = 0;
+	mt9v111_device.ifpReg->gainLimitAE = 0x300;
+	mt9v111_device.ifpReg->AESpeed = 0x80;
+
+	/* here is the default value */
+	mt9v111_device.ifpReg->formatControl = 0xc800;
+	mt9v111_device.ifpReg->modeControl = 0x708e;
+	mt9v111_device.ifpReg->awbSpeed = 0x4514;
+	mt9v111_device.coreReg->shutterWidth = 0xf8;
+
+	/* output size */
+	mt9v111_device.ifpReg->HPan = 0;
+	mt9v111_device.ifpReg->HZoom = MT9V111_MAX_WIDTH;
+	mt9v111_device.ifpReg->HSize = MT9V111_MAX_WIDTH;
+	mt9v111_device.ifpReg->VPan = 0;
+	mt9v111_device.ifpReg->VZoom = MT9V111_MAX_HEIGHT;
+	mt9v111_device.ifpReg->VSize = MT9V111_MAX_HEIGHT;
+}
+
+/*!
+ * mt9v111 sensor set saturtionn
+ *
+ * @param saturation   int
+
+ * @return  Error code of 0.
+ */
+static int mt9v111_set_saturation(int saturation)
+{
+	u8 reg;
+	u16 data;
+	pr_debug("In mt9v111_set_saturation(%d)\n",
+		saturation);
+
+	switch (saturation) {
+	case 150:
+		mt9v111_device.ifpReg->awbSpeed = 0x6D14;
+		break;
+	case 100:
+		mt9v111_device.ifpReg->awbSpeed = 0x4514;
+		break;
+	case 75:
+		mt9v111_device.ifpReg->awbSpeed = 0x4D14;
+		break;
+	case 50:
+		mt9v111_device.ifpReg->awbSpeed = 0x5514;
+		break;
+	case 37:
+		mt9v111_device.ifpReg->awbSpeed = 0x5D14;
+		break;
+	case 25:
+		mt9v111_device.ifpReg->awbSpeed = 0x6514;
+		break;
+	default:
+		mt9v111_device.ifpReg->awbSpeed = 0x4514;
+		break;
+	}
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	/* Operation Mode Control */
+	reg = MT9V111I_AWB_SPEED;
+	data = mt9v111_device.ifpReg->awbSpeed;
+	mt9v111_write_reg(reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor set Auto Exposure measurement window mode configuration
+ *
+ * @param ae_mode      int
+ * @return  Error code of 0 (no Error)
+ */
+static int mt9v111_set_ae_mode(int ae_mode)
+{
+	u8 reg;
+	u16 data;
+
+	pr_debug("In mt9v111_set_ae_mode(%d)\n",
+		ae_mode);
+
+	/* Currently this driver only supports auto and manual exposure
+	 * modes. */
+	if ((ae_mode > 1) || (ae_mode << 0))
+		return -EPERM;
+
+	/*
+	 * The auto exposure is set in bit 14.
+	 * Other values are set for:
+	 *  -on the fly defect correction is on (bit 13).
+	 *  -aperature correction knee enabled (bit 12).
+	 *  -ITU_R BT656 synchronization codes are embedded in the image (bit 7)
+	 *  -AE measurement window is weighted sum of large and center windows
+	 *     (bits 2-3).
+	 *  -auto white balance is on (bit 1).
+	 *  -normal color processing (bit 4 = 0).
+	 */
+	/* V4L2_EXPOSURE_AUTO = 0; needs register setting of 0x708E */
+	/* V4L2_EXPOSURE_MANUAL = 1 needs register setting of 0x308E */
+	mt9v111_device.ifpReg->modeControl &= 0x3fff;
+	mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 14;
+	mt9v111_data.ae_mode = ae_mode;
+
+	reg = MT9V111I_ADDR_SPACE_SEL;
+	data = mt9v111_device.ifpReg->addrSpaceSel;
+	mt9v111_write_reg(reg, data);
+
+	reg = MT9V111I_MODE_CONTROL;
+	data = mt9v111_device.ifpReg->modeControl;
+	mt9v111_write_reg(reg, data);
+
+	return 0;
+}
+
+/*!
+ * mt9v111 sensor get AE measurement window mode configuration
+ *
+ * @param ae_mode      int *
+ * @return  None
+ */
+static void mt9v111_get_ae_mode(int *ae_mode)
+{
+	pr_debug("In mt9v111_get_ae_mode(%d)\n", *ae_mode);
+
+	if (ae_mode != NULL) {
+		*ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2;
+	}
+}
+
+#ifdef MT9V111_DEBUG
+/*!
+ * Set sensor to test mode, which will generate test pattern.
+ *
+ * @return none
+ */
+static void mt9v111_test_pattern(bool flag)
+{
+	u16 data;
+
+	/* switch to sensor registers */
+	mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA);
+
+	if (flag == true) {
+		testpattern = MT9V111S_OUTCTRL_TEST_MODE;
+
+		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF;
+		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
+
+		mt9v111_write_reg(MT9V111S_TEST_DATA, 0);
+
+		/* changes take effect */
+		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
+		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+	} else {
+		testpattern = 0;
+
+		data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40;
+		mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data);
+
+		/* changes take effect */
+		data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000;
+		mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data);
+	}
+}
+#endif
+
+
+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
+
+/*!
+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
+ * s: pointer to standard V4L2 device structure
+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
+ *
+ * Gets slave interface parameters.
+ * Calculates the required xclk value to support the requested
+ * clock parameters in p.  This value is returned in the p
+ * parameter.
+ *
+ * vidioc_int_g_ifparm returns platform-specific information about the
+ * interface settings used by the sensor.
+ *
+ * Given the image capture format in pix, the nominal frame period in
+ * timeperframe, calculate the required xclk frequency.
+ *
+ * Called on open.
+ */
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+	pr_debug("In mt9v111:ioctl_g_ifparm\n");
+
+	if (s == NULL) {
+		pr_err("   ERROR!! no slave device set!\n");
+		return -1;
+	}
+
+	memset(p, 0, sizeof(*p));
+	p->u.bt656.clock_curr = MT9V111_MCLK;
+	p->if_type = V4L2_IF_TYPE_BT656;
+	p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+	p->u.bt656.clock_min = MT9V111_CLK_MIN;
+	p->u.bt656.clock_max = MT9V111_CLK_MAX;
+
+	return 0;
+}
+
+/*!
+ * Sets the camera power.
+ *
+ * s  pointer to the camera device
+ * on if 1, power is to be turned on.  0 means power is to be turned off
+ *
+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
+ * @s: pointer to standard V4L2 device structure
+ * @on: power state to which device is to be set
+ *
+ * Sets devices power state to requrested state, if possible.
+ * This is called on suspend and resume.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+	struct sensor *sensor = s->priv;
+
+	pr_debug("In mt9v111:ioctl_s_power\n");
+
+	sensor->on = on;
+
+	if (on)
+		gpio_sensor_active();
+	else
+		gpio_sensor_inactive();
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	int ret = 0;
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+	/* s->priv points to mt9v111_data */
+
+	pr_debug("In mt9v111:ioctl_g_parm\n");
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		memset(a, 0, sizeof(*a));
+		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cparm->capability = mt9v111_data.streamcap.capability;
+		cparm->timeperframe =
+				mt9v111_data.streamcap.timeperframe;
+		cparm->capturemode = mt9v111_data.streamcap.capturemode;
+		ret = 0;
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_err("   type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \
+			"but %d\n", a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_err("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible.  If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	int ret = 0;
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+	/* s->priv points to mt9v111_data */
+
+	pr_debug("In mt9v111:ioctl_s_parm\n");
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+
+		/* Check that the new frame rate is allowed.
+		 * Changing the frame rate is not allowed on this
+		 *camera. */
+		if (cparm->timeperframe.denominator !=
+		    mt9v111_data.streamcap.timeperframe.denominator) {
+			pr_err("ERROR: mt9v111: ioctl_s_parm: " \
+			       "This camera does not allow frame rate "
+			       "changes.\n");
+			ret = -EINVAL;
+		} else {
+			mt9v111_data.streamcap.timeperframe =
+						cparm->timeperframe;
+		      /* Call any camera functions to match settings. */
+		}
+
+		/* Check that new capture mode is supported. */
+		if ((cparm->capturemode != 0) &&
+		    !(cparm->capturemode & V4L2_MODE_HIGHQUALITY)) {
+			pr_err("ERROR: mt9v111: ioctl_s_parm: " \
+				"unsupported capture mode\n");
+			ret  = -EINVAL;
+		} else {
+			mt9v111_data.streamcap.capturemode =
+						cparm->capturemode;
+		      /* Call any camera functions to match settings. */
+		      /* Right now this camera only supports 1 mode. */
+		}
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_err("   type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \
+			"but %d\n", a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_err("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	struct sensor *sensor = s->priv;
+	/* s->priv points to mt9v111_data */
+
+	pr_debug("In mt9v111:ioctl_g_fmt_cap.\n");
+	pr_debug("   Returning size of %dx%d\n",
+		sensor->pix.width, sensor->pix.height);
+
+	f->fmt.pix = sensor->pix;
+
+	return 0;
+}
+
+/*!
+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control information
+ * from the video_control[] array.  Otherwise, returns -EINVAL if the
+ * control is not supported.
+ */
+static int ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc)
+{
+	pr_debug("In mt9v111:ioctl_queryctrl\n");
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array.  Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	pr_debug("In mt9v111:ioctl_g_ctrl\n");
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		pr_debug("   V4L2_CID_BRIGHTNESS\n");
+		vc->value = mt9v111_data.brightness;
+		break;
+	case V4L2_CID_CONTRAST:
+		pr_debug("   V4L2_CID_CONTRAST\n");
+		vc->value = mt9v111_data.contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		pr_debug("   V4L2_CID_SATURATION\n");
+		vc->value = mt9v111_data.saturation;
+		break;
+	case V4L2_CID_HUE:
+		pr_debug("   V4L2_CID_HUE\n");
+		vc->value = mt9v111_data.hue;
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_DO_WHITE_BALANCE\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_RED_BALANCE:
+		pr_debug("   V4L2_CID_RED_BALANCE\n");
+		vc->value = mt9v111_data.red;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		pr_debug("   V4L2_CID_BLUE_BALANCE\n");
+		vc->value = mt9v111_data.blue;
+		break;
+	case V4L2_CID_GAMMA:
+		pr_debug("   V4L2_CID_GAMMA\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_EXPOSURE:
+		pr_debug("   V4L2_CID_EXPOSURE\n");
+		vc->value = mt9v111_data.ae_mode;
+		break;
+	case V4L2_CID_AUTOGAIN:
+		pr_debug("   V4L2_CID_AUTOGAIN\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_GAIN:
+		pr_debug("   V4L2_CID_GAIN\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_HFLIP:
+		pr_debug("   V4L2_CID_HFLIP\n");
+		vc->value = 0;
+		break;
+	case V4L2_CID_VFLIP:
+		pr_debug("   V4L2_CID_VFLIP\n");
+		vc->value = 0;
+		break;
+	default:
+		pr_debug("   Default case\n");
+		return -EPERM;
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array).  Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int retval = 0;
+
+	pr_debug("In mt9v111:ioctl_s_ctrl %d\n",
+		vc->id);
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		pr_debug("   V4L2_CID_BRIGHTNESS\n");
+		break;
+	case V4L2_CID_CONTRAST:
+		pr_debug("   V4L2_CID_CONTRAST\n");
+		break;
+	case V4L2_CID_SATURATION:
+		pr_debug("   V4L2_CID_SATURATION\n");
+		retval = mt9v111_set_saturation(vc->value);
+		break;
+	case V4L2_CID_HUE:
+		pr_debug("   V4L2_CID_HUE\n");
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_DO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_RED_BALANCE:
+		pr_debug("   V4L2_CID_RED_BALANCE\n");
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		pr_debug("   V4L2_CID_BLUE_BALANCE\n");
+		break;
+	case V4L2_CID_GAMMA:
+		pr_debug("   V4L2_CID_GAMMA\n");
+		break;
+	case V4L2_CID_EXPOSURE:
+		pr_debug("   V4L2_CID_EXPOSURE\n");
+		retval = mt9v111_set_ae_mode(vc->value);
+		break;
+	case V4L2_CID_AUTOGAIN:
+		pr_debug("   V4L2_CID_AUTOGAIN\n");
+		break;
+	case V4L2_CID_GAIN:
+		pr_debug("   V4L2_CID_GAIN\n");
+		break;
+	case V4L2_CID_HFLIP:
+		pr_debug("   V4L2_CID_HFLIP\n");
+		break;
+	case V4L2_CID_VFLIP:
+		pr_debug("   V4L2_CID_VFLIP\n");
+		break;
+	default:
+		pr_debug("   Default case\n");
+		retval = -EPERM;
+		break;
+	}
+
+	return retval;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+	pr_debug("In mt9v111:ioctl_init\n");
+
+	return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+	uint32_t clock_rate = MT9V111_MCLK;
+
+	pr_debug("In mt9v111:ioctl_dev_init\n");
+
+	gpio_sensor_active();
+
+	set_mclk_rate(&clock_rate);
+	mt9v111_rate_cal(&reset_frame_rate, clock_rate);
+	mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg);
+
+	return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module and links them to the
+ * enumeration.
+ */
+static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = {
+
+	{vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init},
+
+	/*!
+	 * Delinitialise the dev. at slave detach.
+	 * The complement of ioctl_dev_init.
+	 */
+/*	{vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *) ioctl_dev_exit}, */
+
+	{vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power},
+	{vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm},
+/*	{vidioc_int_g_needs_reset_num,
+				(v4l2_int_ioctl_func *) ioctl_g_needs_reset}, */
+/*	{vidioc_int_reset_num, (v4l2_int_ioctl_func *) ioctl_reset}, */
+	{vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init},
+
+	/*!
+	 * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
+	 */
+/*	{vidioc_int_enum_fmt_cap_num,
+				(v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, */
+
+	/*!
+	 * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
+	 * This ioctl is used to negotiate the image capture size and
+	 * pixel format without actually making it take effect.
+	 */
+/*	{vidioc_int_try_fmt_cap_num,
+				(v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, */
+
+	{vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
+
+	/*!
+	 * If the requested format is supported, configures the HW to use that
+	 * format, returns error code if format not supported or HW can't be
+	 * correctly configured.
+	 */
+/*	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+
+	{vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
+	{vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
+/*	{vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *) ioctl_queryctrl}, */
+	{vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
+	{vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
+};
+
+static struct v4l2_int_slave mt9v111_slave = {
+	.ioctls = mt9v111_ioctl_desc,
+	.num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc),
+};
+
+static struct v4l2_int_device mt9v111_int_device = {
+	.module = THIS_MODULE,
+	.name = "mt9v111",
+	.type = v4l2_int_type_slave,
+	.u = {
+		.slave = &mt9v111_slave,
+		},
+};
+
+/*!
+ * mt9v111 I2C probe function
+ * Function set in i2c_driver struct.
+ * Called by insmod mt9v111_camera.ko.
+ *
+ * @return  Error code indicating success or failure
+ */
+static int mt9v111_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	int retval;
+
+	pr_debug("In mt9v111_probe  device id is %s\n", id->name);
+
+	/* Set initial values for the sensor struct. */
+	memset(&mt9v111_data, 0, sizeof(mt9v111_data));
+	mt9v111_data.i2c_client = client;
+	pr_debug("   client name is %s\n", client->name);
+	mt9v111_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
+	mt9v111_data.pix.width = MT9V111_MAX_WIDTH;
+	mt9v111_data.pix.height = MT9V111_MAX_HEIGHT;
+	mt9v111_data.streamcap.capability = 0; /* No higher resolution or frame
+						* frame rate changes supported.
+						*/
+	mt9v111_data.streamcap.timeperframe.denominator = MT9V111_FRAME_RATE;
+	mt9v111_data.streamcap.timeperframe.numerator = 1;
+
+	mt9v111_int_device.priv = &mt9v111_data;
+
+	pr_debug("   type is %d (expect %d)\n",
+		mt9v111_int_device.type, v4l2_int_type_slave);
+	pr_debug("   num ioctls is %d\n",
+		mt9v111_int_device.u.slave->num_ioctls);
+
+	/* This function attaches this structure to the /dev/video0 device.
+	 * The pointer in priv points to the mt9v111_data structure here.*/
+	retval = v4l2_int_device_register(&mt9v111_int_device);
+
+	return retval;
+}
+
+/*!
+ * Function set in i2c_driver struct.
+ * Called on rmmod mt9v111_camera.ko
+ */
+static int mt9v111_remove(struct i2c_client *client)
+{
+	pr_debug("In mt9v111_remove\n");
+
+	v4l2_int_device_unregister(&mt9v111_int_device);
+	return 0;
+}
+
+/*!
+ * MT9V111 init function.
+ * Called by insmod mt9v111_camera.ko.
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int mt9v111_init(void)
+{
+	u8 err;
+
+	pr_debug("In mt9v111_init\n");
+
+	/* Allocate memory for state structures. */
+	mt9v111_device.coreReg = (mt9v111_coreReg *)
+				kmalloc(sizeof(mt9v111_coreReg), GFP_KERNEL);
+	if (!mt9v111_device.coreReg)
+		return -1;
+	memset(mt9v111_device.coreReg, 0, sizeof(mt9v111_coreReg));
+
+	mt9v111_device.ifpReg = (mt9v111_IFPReg *)
+				kmalloc(sizeof(mt9v111_IFPReg), GFP_KERNEL);
+	if (!mt9v111_device.ifpReg) {
+		kfree(mt9v111_device.coreReg);
+		mt9v111_device.coreReg = NULL;
+		return -1;
+	}
+	memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg));
+
+	/* Set contents of the just created structures. */
+	mt9v111_config();
+
+	/* Tells the i2c driver what functions to call for this driver. */
+	err = i2c_add_driver(&mt9v111_i2c_driver);
+	if (err != 0)
+		pr_err("%s:driver registration failed, error=%d \n",
+		       __func__, err);
+
+	return err;
+}
+
+/*!
+ * MT9V111 cleanup function.
+ * Called on rmmod mt9v111_camera.ko
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit mt9v111_clean(void)
+{
+	pr_debug("In mt9v111_clean()\n");
+
+	i2c_del_driver(&mt9v111_i2c_driver);
+	gpio_sensor_inactive();
+
+	if (mt9v111_device.coreReg) {
+		kfree(mt9v111_device.coreReg);
+		mt9v111_device.coreReg = NULL;
+	}
+
+	if (mt9v111_device.ifpReg) {
+		kfree(mt9v111_device.ifpReg);
+		mt9v111_device.ifpReg = NULL;
+	}
+}
+
+module_init(mt9v111_init);
+module_exit(mt9v111_clean);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Mt9v111 Camera Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/mt9v111.h b/drivers/media/video/mxc/capture/mt9v111.h
new file mode 100644
index 000000000000..cf38cec4757c
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mt9v111.h
@@ -0,0 +1,431 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Camera Sensor Drivers
+ */
+
+/*!
+ * @file mt9v111.h
+ *
+ * @brief MT9V111 Camera Header file
+ *
+ * This header file contains defines and structures for the iMagic mi8012
+ * aka the Micron mt9v111 camera.
+ *
+ * @ingroup Camera
+ */
+
+#ifndef MT9V111_H_
+#define MT9V111_H_
+
+/*!
+ * Basic camera values
+ */
+#define MT9V111_FRAME_RATE        30
+#define MT9V111_MCLK              27000000 /* Desired clock rate */
+#define MT9V111_CLK_MIN           12000000 /* This clock rate yields 15 fps */
+#define MT9V111_CLK_MAX           27000000
+#define MT9V111_MAX_WIDTH         640      /* Max width for this camera */
+#define MT9V111_MAX_HEIGHT        480      /* Max height for this camera */
+
+/*!
+ * mt9v111 IFP REGISTER BANK MAP
+ */
+#define MT9V111I_ADDR_SPACE_SEL           0x1
+#define MT9V111I_BASE_MAXTRIX_SIGN        0x2
+#define MT9V111I_BASE_MAXTRIX_SCALE15     0x3
+#define MT9V111I_BASE_MAXTRIX_SCALE69     0x4
+#define MT9V111I_APERTURE_GAIN            0x5
+#define MT9V111I_MODE_CONTROL             0x6
+#define MT9V111I_SOFT_RESET               0x7
+#define MT9V111I_FORMAT_CONTROL           0x8
+#define MT9V111I_BASE_MATRIX_CFK1         0x9
+#define MT9V111I_BASE_MATRIX_CFK2         0xa
+#define MT9V111I_BASE_MATRIX_CFK3         0xb
+#define MT9V111I_BASE_MATRIX_CFK4         0xc
+#define MT9V111I_BASE_MATRIX_CFK5         0xd
+#define MT9V111I_BASE_MATRIX_CFK6         0xe
+#define MT9V111I_BASE_MATRIX_CFK7         0xf
+#define MT9V111I_BASE_MATRIX_CFK8         0x10
+#define MT9V111I_BASE_MATRIX_CFK9         0x11
+#define MT9V111I_AWB_POSITION             0x12
+#define MT9V111I_AWB_RED_GAIN             0x13
+#define MT9V111I_AWB_BLUE_GAIN            0x14
+#define MT9V111I_DELTA_MATRIX_CF_SIGN     0x15
+#define MT9V111I_DELTA_MATRIX_CF_D1       0x16
+#define MT9V111I_DELTA_MATRIX_CF_D2       0x17
+#define MT9V111I_DELTA_MATRIX_CF_D3       0x18
+#define MT9V111I_DELTA_MATRIX_CF_D4       0x19
+#define MT9V111I_DELTA_MATRIX_CF_D5       0x1a
+#define MT9V111I_DELTA_MATRIX_CF_D6       0x1b
+#define MT9V111I_DELTA_MATRIX_CF_D7       0x1c
+#define MT9V111I_DELTA_MATRIX_CF_D8       0x1d
+#define MT9V111I_DELTA_MATRIX_CF_D9       0x1e
+#define MT9V111I_LUMINANCE_LIMIT_WB       0x20
+#define MT9V111I_RBG_MANUUAL_WB           0x21
+#define MT9V111I_AWB_RED_LIMIT            0x22
+#define MT9V111I_AWB_BLUE_LIMIT           0x23
+#define MT9V111I_MATRIX_ADJUST_LIMIT      0x24
+#define MT9V111I_AWB_SPEED                0x25
+#define MT9V111I_H_BOUND_AE               0x26
+#define MT9V111I_V_BOUND_AE               0x27
+#define MT9V111I_H_BOUND_AE_CEN_WIN       0x2b
+#define MT9V111I_V_BOUND_AE_CEN_WIN       0x2c
+#define MT9V111I_BOUND_AWB_WIN            0x2d
+#define MT9V111I_AE_PRECISION_TARGET      0x2e
+#define MT9V111I_AE_SPEED                 0x2f
+#define MT9V111I_RED_AWB_MEASURE          0x30
+#define MT9V111I_LUMA_AWB_MEASURE         0x31
+#define MT9V111I_BLUE_AWB_MEASURE         0x32
+#define MT9V111I_LIMIT_SHARP_SATU_CTRL    0x33
+#define MT9V111I_LUMA_OFFSET              0x34
+#define MT9V111I_CLIP_LIMIT_OUTPUT_LUMI   0x35
+#define MT9V111I_GAIN_LIMIT_AE            0x36
+#define MT9V111I_SHUTTER_WIDTH_LIMIT_AE   0x37
+#define MT9V111I_UPPER_SHUTTER_DELAY_LIM  0x39
+#define MT9V111I_OUTPUT_FORMAT_CTRL2      0x3a
+#define MT9V111I_IPF_BLACK_LEVEL_SUB      0x3b
+#define MT9V111I_IPF_BLACK_LEVEL_ADD      0x3c
+#define MT9V111I_ADC_LIMIT_AE_ADJ         0x3d
+#define MT9V111I_GAIN_THRE_CCAM_ADJ       0x3e
+#define MT9V111I_LINEAR_AE                0x3f
+#define MT9V111I_THRESHOLD_EDGE_DEFECT    0x47
+#define MT9V111I_LUMA_SUM_MEASURE         0x4c
+#define MT9V111I_TIME_ADV_SUM_LUMA        0x4d
+#define MT9V111I_MOTION                   0x52
+#define MT9V111I_GAMMA_KNEE_Y12           0x53
+#define MT9V111I_GAMMA_KNEE_Y34           0x54
+#define MT9V111I_GAMMA_KNEE_Y56           0x55
+#define MT9V111I_GAMMA_KNEE_Y78           0x56
+#define MT9V111I_GAMMA_KNEE_Y90           0x57
+#define MT9V111I_GAMMA_VALUE_Y0           0x58
+#define MT9V111I_SHUTTER_60               0x59
+#define MT9V111I_SEARCH_FLICK_60          0x5c
+#define MT9V111I_RATIO_IMAGE_GAIN_BASE    0x5e
+#define MT9V111I_RATIO_IMAGE_GAIN_DELTA   0x5f
+#define MT9V111I_SIGN_VALUE_REG5F         0x60
+#define MT9V111I_AE_GAIN                  0x62
+#define MT9V111I_MAX_GAIN_AE              0x67
+#define MT9V111I_LENS_CORRECT_CTRL        0x80
+#define MT9V111I_SHADING_PARAMETER1       0x81
+#define MT9V111I_SHADING_PARAMETER2       0x82
+#define MT9V111I_SHADING_PARAMETER3       0x83
+#define MT9V111I_SHADING_PARAMETER4       0x84
+#define MT9V111I_SHADING_PARAMETER5       0x85
+#define MT9V111I_SHADING_PARAMETER6       0x86
+#define MT9V111I_SHADING_PARAMETER7       0x87
+#define MT9V111I_SHADING_PARAMETER8       0x88
+#define MT9V111I_SHADING_PARAMETER9       0x89
+#define MT9V111I_SHADING_PARAMETER10      0x8A
+#define MT9V111I_SHADING_PARAMETER11      0x8B
+#define MT9V111I_SHADING_PARAMETER12      0x8C
+#define MT9V111I_SHADING_PARAMETER13      0x8D
+#define MT9V111I_SHADING_PARAMETER14      0x8E
+#define MT9V111I_SHADING_PARAMETER15      0x8F
+#define MT9V111I_SHADING_PARAMETER16      0x90
+#define MT9V111I_SHADING_PARAMETER17      0x91
+#define MT9V111I_SHADING_PARAMETER18      0x92
+#define MT9V111I_SHADING_PARAMETER19      0x93
+#define MT9V111I_SHADING_PARAMETER20      0x94
+#define MT9V111I_SHADING_PARAMETER21      0x95
+#define MT9V111i_FLASH_CTRL               0x98
+#define MT9V111i_LINE_COUNTER             0x99
+#define MT9V111i_FRAME_COUNTER            0x9A
+#define MT9V111i_H_PAN                    0xA5
+#define MT9V111i_H_ZOOM                   0xA6
+#define MT9V111i_H_SIZE                   0xA7
+#define MT9V111i_V_PAN                    0xA8
+#define MT9V111i_V_ZOOM                   0xA9
+#define MT9V111i_V_SIZE                   0xAA
+
+#define MT9V111I_SEL_IFP                  0x1
+#define MT9V111I_SEL_SCA                  0x4
+#define MT9V111I_FC_RGB_OR_YUV            0x1000
+
+/*!
+ * Mt9v111 SENSOR CORE REGISTER BANK MAP
+ */
+#define MT9V111S_ADDR_SPACE_SEL           0x1
+#define MT9V111S_COLUMN_START             0x2
+#define MT9V111S_WIN_HEIGHT               0x3
+#define MT9V111S_WIN_WIDTH                0x4
+#define MT9V111S_HOR_BLANKING             0x5
+#define MT9V111S_VER_BLANKING             0x6
+#define MT9V111S_OUTPUT_CTRL              0x7
+#define MT9V111S_ROW_START                0x8
+#define MT9V111S_SHUTTER_WIDTH            0x9
+#define MT9V111S_PIXEL_CLOCK_SPEED        0xa
+#define MT9V111S_RESTART                  0xb
+#define MT9V111S_SHUTTER_DELAY            0xc
+#define MT9V111S_RESET                    0xd
+#define MT9V111S_COLUMN_START_IN_ZOOM     0x12
+#define MT9V111S_ROW_START_IN_ZOOM        0x13
+#define MT9V111S_DIGITAL_ZOOM             0x1e
+#define MT9V111S_READ_MODE                0x20
+#define MT9V111S_DAC_CTRL                 0x27
+#define MT9V111S_GREEN1_GAIN              0x2b
+#define MT9V111S_BLUE_GAIN                0x2c
+#define MT9V111S_READ_GAIN                0x2d
+#define MT9V111S_GREEN2_GAIN              0x2e
+#define MT9V111S_ROW_NOISE_CTRL           0x30
+#define MT9V111S_DARK_TARGET_W            0x31
+#define MT9V111S_TEST_DATA                0x32
+#define MT9V111S_GLOBAL_GAIN              0x35
+#define MT9V111S_SENSOR_CORE_VERSION      0x36
+#define MT9V111S_DARK_TARGET_WO           0x37
+#define MT9V111S_VERF_DAC                 0x41
+#define MT9V111S_VCM_VCL                  0x42
+#define MT9V111S_DISABLE_BYPASS           0x58
+#define MT9V111S_CALIB_MEAN_TEST          0x59
+#define MT9V111S_DARK_G1_AVE              0x5B
+#define MT9V111S_DARK_G2_AVE              0x5C
+#define MT9V111S_DARK_R_AVE               0x5D
+#define MT9V111S_DARK_B_AVE               0x5E
+#define MT9V111S_CAL_THRESHOLD            0x5f
+#define MT9V111S_CAL_G1                   0x60
+#define MT9V111S_CAL_G2                   0x61
+#define MT9V111S_CAL_CTRL                 0x62
+#define MT9V111S_CAL_R                    0x63
+#define MT9V111S_CAL_B                    0x64
+#define MT9V111S_CHIP_ENABLE              0xF1
+#define MT9V111S_CHIP_VERSION             0xFF
+
+/* OUTPUT_CTRL */
+#define MT9V111S_OUTCTRL_SYNC             0x1
+#define MT9V111S_OUTCTRL_CHIP_ENABLE      0x2
+#define MT9V111S_OUTCTRL_TEST_MODE        0x40
+
+/* READ_MODE */
+#define MT9V111S_RM_NOBADFRAME            0x1
+#define MT9V111S_RM_NODESTRUCT            0x2
+#define MT9V111S_RM_COLUMNSKIP            0x4
+#define MT9V111S_RM_ROWSKIP               0x8
+#define MT9V111S_RM_BOOSTEDRESET          0x1000
+#define MT9V111S_RM_COLUMN_LATE           0x10
+#define MT9V111S_RM_ROW_LATE              0x80
+#define MT9V111S_RM_RIGTH_TO_LEFT         0x4000
+#define MT9V111S_RM_BOTTOM_TO_TOP         0x8000
+
+/*! I2C Slave Address */
+#define MT9V111_I2C_ADDRESS	0x48
+
+/*!
+ * The image resolution enum for the mt9v111 sensor
+ */
+typedef enum {
+	MT9V111_OutputResolution_VGA = 0,	/*!< VGA size */
+	MT9V111_OutputResolution_QVGA,	/*!< QVGA size */
+	MT9V111_OutputResolution_CIF,	/*!< CIF size */
+	MT9V111_OutputResolution_QCIF,	/*!< QCIF size */
+	MT9V111_OutputResolution_QQVGA,	/*!< QQVGA size */
+	MT9V111_OutputResolution_SXGA	/*!< SXGA size */
+} MT9V111_OutputResolution;
+
+enum {
+	MT9V111_WINWIDTH = 0x287,
+	MT9V111_WINWIDTH_DEFAULT = 0x287,
+	MT9V111_WINWIDTH_MIN = 0x9,
+
+	MT9V111_WINHEIGHT = 0x1E7,
+	MT9V111_WINHEIGHT_DEFAULT = 0x1E7,
+
+	MT9V111_HORZBLANK_DEFAULT = 0x26,
+	MT9V111_HORZBLANK_MIN = 0x9,
+	MT9V111_HORZBLANK_MAX = 0x3FF,
+
+	MT9V111_VERTBLANK_DEFAULT = 0x4,
+	MT9V111_VERTBLANK_MIN = 0x3,
+	MT9V111_VERTBLANK_MAX = 0xFFF,
+};
+
+/*!
+ * Mt9v111 Core Register structure.
+ */
+typedef struct {
+	u32 addressSelect;	/*!< select address bank for Core Register 0x4 */
+	u32 columnStart;	/*!< Starting Column */
+	u32 windowHeight;	/*!< Window Height */
+	u32 windowWidth;	/*!< Window Width */
+	u32 horizontalBlanking;	/*!< Horizontal Blank time, in pixels */
+	u32 verticalBlanking;	/*!< Vertical Blank time, in pixels */
+	u32 outputControl;	/*!< Register to control sensor output */
+	u32 rowStart;		/*!< Starting Row */
+	u32 shutterWidth;
+	u32 pixelClockSpeed;	/*!< pixel date rate */
+	u32 restart;		/*!< Abandon the readout of current frame */
+	u32 shutterDelay;
+	u32 reset;		/*!< reset the sensor to the default mode */
+	u32 zoomColStart;	/*!< Column start in the Zoom mode */
+	u32 zomRowStart;	/*!< Row start in the Zoom mode */
+	u32 digitalZoom;	/*!< 1 means zoom by 2 */
+	u32 readMode;		/*!< Readmode: aspects of the readout of the sensor */
+	u32 dACStandbyControl;
+	u32 green1Gain;		/*!< Gain Settings */
+	u32 blueGain;
+	u32 redGain;
+	u32 green2Gain;
+	u32 rowNoiseControl;
+	u32 darkTargetwNC;
+	u32 testData;		/*!< test mode */
+	u32 globalGain;
+	u32 chipVersion;
+	u32 darkTargetwoNC;
+	u32 vREFDACs;
+	u32 vCMandVCL;
+	u32 disableBypass;
+	u32 calibMeanTest;
+	u32 darkG1average;
+	u32 darkG2average;
+	u32 darkRaverage;
+	u32 darkBaverage;
+	u32 calibThreshold;
+	u32 calibGreen1;
+	u32 calibGreen2;
+	u32 calibControl;
+	u32 calibRed;
+	u32 calibBlue;
+	u32 chipEnable;		/*!< Image core Registers written by image flow processor */
+} mt9v111_coreReg;
+
+/*!
+ * Mt9v111 IFP Register structure.
+ */
+typedef struct {
+	u32 addrSpaceSel;	/*!< select address bank for Core Register 0x1 */
+	u32 baseMaxtrixSign;	/*!< sign of coefficient for base color correction matrix */
+	u32 baseMaxtrixScale15;	/*!< scaling of color correction coefficient K1-5 */
+	u32 baseMaxtrixScale69;	/*!< scaling of color correction coefficient K6-9 */
+	u32 apertureGain;	/*!< sharpening */
+	u32 modeControl;	/*!< bit 7 CCIR656 sync codes are embedded in the image */
+	u32 softReset;		/*!< Image processing mode: 1 reset mode, 0 operational mode */
+	u32 formatControl;	/*!< bit12 1 for RGB565, 0 for YcrCb */
+	u32 baseMatrixCfk1;	/*!< K1 Color correction coefficient */
+	u32 baseMatrixCfk2;	/*!< K2 Color correction coefficient */
+	u32 baseMatrixCfk3;	/*!< K3 Color correction coefficient */
+	u32 baseMatrixCfk4;	/*!< K4 Color correction coefficient */
+	u32 baseMatrixCfk5;	/*!< K5 Color correction coefficient */
+	u32 baseMatrixCfk6;	/*!< K6 Color correction coefficient */
+	u32 baseMatrixCfk7;	/*!< K7 Color correction coefficient */
+	u32 baseMatrixCfk8;	/*!< K8 Color correction coefficient */
+	u32 baseMatrixCfk9;	/*!< K9 Color correction coefficient */
+	u32 awbPosition;	/*!< Current position of AWB color correction matrix */
+	u32 awbRedGain;		/*!< Current value of AWB red channel gain */
+	u32 awbBlueGain;	/*!< Current value of AWB blue channel gain */
+	u32 deltaMatrixCFSign;	/*!< Sign of coefficients of delta color correction matrix register */
+	u32 deltaMatrixCFD1;	/*!< D1 Delta coefficient */
+	u32 deltaMatrixCFD2;	/*!< D2 Delta coefficient */
+	u32 deltaMatrixCFD3;	/*!< D3 Delta coefficient */
+	u32 deltaMatrixCFD4;	/*!< D4 Delta coefficient */
+	u32 deltaMatrixCFD5;	/*!< D5 Delta coefficient */
+	u32 deltaMatrixCFD6;	/*!< D6 Delta coefficient */
+	u32 deltaMatrixCFD7;	/*!< D7 Delta coefficient */
+	u32 deltaMatrixCFD8;	/*!< D8 Delta coefficient */
+	u32 deltaMatrixCFD9;	/*!< D9 Delta coefficient */
+	u32 lumLimitWB;		/*!< Luminance range of pixels considered in WB statistics */
+	u32 RBGManualWB;	/*!< Red and Blue color channel gains for manual white balance */
+	u32 awbRedLimit;	/*!< Limits on Red channel gain adjustment through AWB */
+	u32 awbBlueLimit;	/*!< Limits on Blue channel gain adjustment through AWB */
+	u32 matrixAdjLimit;	/*!< Limits on color correction matrix adjustment through AWB */
+	u32 awbSpeed;		/*!< AWB speed and color saturation control */
+	u32 HBoundAE;		/*!< Horizontal boundaries of AWB measurement window */
+	u32 VBoundAE;		/*!< Vertical boundaries of AWB measurement window */
+	u32 HBoundAECenWin;	/*!< Horizontal boundaries of AE measurement window for backlight compensation */
+	u32 VBoundAECenWin;	/*!< Vertical boundaries of AE measurement window for backlight compensation */
+	u32 boundAwbWin;	/*!< Boundaries of AWB measurement window */
+	u32 AEPrecisionTarget;	/*!< Auto exposure target and precision control */
+	u32 AESpeed;		/*!< AE speed and sensitivity control register */
+	u32 redAWBMeasure;	/*!< Measure of the red channel value used by AWB */
+	u32 lumaAWBMeasure;	/*!< Measure of the luminance channel value used by AWB */
+	u32 blueAWBMeasure;	/*!< Measure of the blue channel value used by AWB */
+	u32 limitSharpSatuCtrl;	/*!< Automatic control of sharpness and color saturation */
+	u32 lumaOffset;		/*!< Luminance offset control (brightness control) */
+	u32 clipLimitOutputLumi;	/*!< Clipping limits for output luminance */
+	u32 gainLimitAE;	/*!< Imager gain limits for AE adjustment */
+	u32 shutterWidthLimitAE;	/*!< Shutter width (exposure time) limits for AE adjustment */
+	u32 upperShutterDelayLi;	/*!< Upper Shutter Delay Limit */
+	u32 outputFormatCtrl2;	/*!< Output Format Control 2
+				   00 = 16-bit RGB565.
+				   01 = 15-bit RGB555.
+				   10 = 12-bit RGB444x.
+				   11 = 12-bit RGBx444.       */
+	u32 ipfBlackLevelSub;	/*!< IFP black level subtraction */
+	u32 ipfBlackLevelAdd;	/*!< IFP black level addition */
+	u32 adcLimitAEAdj;	/*!< ADC limits for AE adjustment */
+	u32 agimnThreCamAdj;	/*!< Gain threshold for CCM adjustment */
+	u32 linearAE;
+	u32 thresholdEdgeDefect;	/*!< Edge threshold for interpolation and defect correction */
+	u32 lumaSumMeasure;	/*!< Luma measured by AE engine */
+	u32 timeAdvSumLuma;	/*!< Time-averaged luminance value tracked by auto exposure */
+	u32 motion;		/*!< 1 when motion is detected */
+	u32 gammaKneeY12;	/*!< Gamma knee points Y1 and Y2 */
+	u32 gammaKneeY34;	/*!< Gamma knee points Y3 and Y4 */
+	u32 gammaKneeY56;	/*!< Gamma knee points Y5 and Y6 */
+	u32 gammaKneeY78;	/*!< Gamma knee points Y7 and Y8 */
+	u32 gammaKneeY90;	/*!< Gamma knee points Y9 and Y10 */
+	u32 gammaKneeY0;	/*!< Gamma knee point Y0 */
+	u32 shutter_width_60;
+	u32 search_flicker_60;
+	u32 ratioImageGainBase;
+	u32 ratioImageGainDelta;
+	u32 signValueReg5F;
+	u32 aeGain;
+	u32 maxGainAE;
+	u32 lensCorrectCtrl;
+	u32 shadingParameter1;	/*!< Shade Parameters */
+	u32 shadingParameter2;
+	u32 shadingParameter3;
+	u32 shadingParameter4;
+	u32 shadingParameter5;
+	u32 shadingParameter6;
+	u32 shadingParameter7;
+	u32 shadingParameter8;
+	u32 shadingParameter9;
+	u32 shadingParameter10;
+	u32 shadingParameter11;
+	u32 shadingParameter12;
+	u32 shadingParameter13;
+	u32 shadingParameter14;
+	u32 shadingParameter15;
+	u32 shadingParameter16;
+	u32 shadingParameter17;
+	u32 shadingParameter18;
+	u32 shadingParameter19;
+	u32 shadingParameter20;
+	u32 shadingParameter21;
+	u32 flashCtrl;		/*!< Flash control */
+	u32 lineCounter;	/*!< Line counter */
+	u32 frameCounter;	/*!< Frame counter */
+	u32 HPan;		/*!< Horizontal pan in decimation */
+	u32 HZoom;		/*!< Horizontal zoom in decimation */
+	u32 HSize;		/*!< Horizontal output size iIn decimation */
+	u32 VPan;		/*!< Vertical pan in decimation */
+	u32 VZoom;		/*!< Vertical zoom in decimation */
+	u32 VSize;		/*!< Vertical output size in decimation */
+} mt9v111_IFPReg;
+
+/*!
+ * mt9v111 Config structure
+ */
+typedef struct {
+	mt9v111_coreReg *coreReg;	/*!< Sensor Core Register Bank */
+	mt9v111_IFPReg *ifpReg;	/*!< IFP Register Bank */
+} mt9v111_conf;
+
+typedef struct {
+	u8 index;
+	u16 width;
+	u16 height;
+} mt9v111_image_format;
+
+#endif				/* MT9V111_H_  */
diff --git a/drivers/media/video/mxc/capture/mx27_csi.c b/drivers/media/video/mxc/capture/mx27_csi.c
new file mode 100644
index 000000000000..24fce05be110
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mx27_csi.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_csi.c
+ *
+ * @brief CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+#include "mx27_csi.h"
+
+static csi_config_t g_csi_cfg;	/* csi hardware configuration */
+static bool gcsi_mclk_on = false;
+static csi_irq_callback_t g_callback = 0;
+static void *g_callback_data = 0;
+static struct clk csi_mclk;
+
+static irqreturn_t csi_irq_handler(int irq, void *data)
+{
+	unsigned long status = __raw_readl(CSI_CSISR);
+
+	__raw_writel(status, CSI_CSISR);
+	if (g_callback)
+		g_callback(g_callback_data, status);
+
+	pr_debug("CSI status = 0x%08lX\n", status);
+
+	return IRQ_HANDLED;
+}
+
+static void csihw_set_config(csi_config_t * cfg)
+{
+	unsigned val = 0;
+
+	/* control reg 1 */
+	val |= cfg->swap16_en ? BIT_SWAP16_EN : 0;
+	val |= cfg->ext_vsync ? BIT_EXT_VSYNC : 0;
+	val |= cfg->eof_int_en ? BIT_EOF_INT_EN : 0;
+	val |= cfg->prp_if_en ? BIT_PRP_IF_EN : 0;
+	val |= cfg->ccir_mode ? BIT_CCIR_MODE : 0;
+	val |= cfg->cof_int_en ? BIT_COF_INT_EN : 0;
+	val |= cfg->sf_or_inten ? BIT_SF_OR_INTEN : 0;
+	val |= cfg->rf_or_inten ? BIT_RF_OR_INTEN : 0;
+	val |= cfg->statff_level << SHIFT_STATFF_LEVEL;
+	val |= cfg->staff_inten ? BIT_STATFF_INTEN : 0;
+	val |= cfg->rxff_level << SHIFT_RXFF_LEVEL;
+	val |= cfg->rxff_inten ? BIT_RXFF_INTEN : 0;
+	val |= cfg->sof_pol ? BIT_SOF_POL : 0;
+	val |= cfg->sof_inten ? BIT_SOF_INTEN : 0;
+	val |= cfg->mclkdiv << SHIFT_MCLKDIV;
+	val |= cfg->hsync_pol ? BIT_HSYNC_POL : 0;
+	val |= cfg->ccir_en ? BIT_CCIR_EN : 0;
+	val |= cfg->mclken ? BIT_MCLKEN : 0;
+	val |= cfg->fcc ? BIT_FCC : 0;
+	val |= cfg->pack_dir ? BIT_PACK_DIR : 0;
+	val |= cfg->gclk_mode ? BIT_GCLK_MODE : 0;
+	val |= cfg->inv_data ? BIT_INV_DATA : 0;
+	val |= cfg->inv_pclk ? BIT_INV_PCLK : 0;
+	val |= cfg->redge ? BIT_REDGE : 0;
+
+	__raw_writel(val, CSI_CSICR1);
+
+	/* control reg 3 */
+	val = 0x0;
+	val |= cfg->csi_sup ? BIT_CSI_SUP : 0;
+	val |= cfg->zero_pack_en ? BIT_ZERO_PACK_EN : 0;
+	val |= cfg->ecc_int_en ? BIT_ECC_INT_EN : 0;
+	val |= cfg->ecc_auto_en ? BIT_ECC_AUTO_EN : 0;
+
+	__raw_writel(val, CSI_CSICR3);
+
+	/* rxfifo counter */
+	__raw_writel(cfg->rxcnt, CSI_CSIRXCNT);
+
+	/* update global config */
+	memcpy(&g_csi_cfg, cfg, sizeof(csi_config_t));
+}
+
+static void csihw_reset_frame_count(void)
+{
+	__raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3);
+}
+
+static void csihw_reset(void)
+{
+	csihw_reset_frame_count();
+	__raw_writel(CSICR1_RESET_VAL, CSI_CSICR1);
+	__raw_writel(CSICR2_RESET_VAL, CSI_CSICR2);
+	__raw_writel(CSICR3_RESET_VAL, CSI_CSICR3);
+}
+
+/*!
+ * csi_init_interface
+ *    Sets initial values for the CSI registers.
+ *    The width and height of the sensor and the actual frame size will be
+ *    set to the same values.
+ * @param       width        Sensor width
+ * @param       height       Sensor height
+ * @param       pixel_fmt    pixel format
+ * @param       sig          csi_signal_cfg_t
+ *
+ * @return      0 for success, -EINVAL for error
+ */
+int32_t csi_init_interface(uint16_t width, uint16_t height,
+			   uint32_t pixel_fmt, csi_signal_cfg_t sig)
+{
+	csi_config_t cfg;
+
+	/* Set the CSI_SENS_CONF register remaining fields */
+	cfg.swap16_en = 1;
+	cfg.ext_vsync = sig.ext_vsync;
+	cfg.eof_int_en = 0;
+	cfg.prp_if_en = 1;
+	cfg.ccir_mode = 0;
+	cfg.cof_int_en = 0;
+	cfg.sf_or_inten = 0;
+	cfg.rf_or_inten = 0;
+	cfg.statff_level = 0;
+	cfg.staff_inten = 0;
+	cfg.rxff_level = 2;
+	cfg.rxff_inten = 0;
+	cfg.sof_pol = 1;
+	cfg.sof_inten = 0;
+	cfg.mclkdiv = 0;
+	cfg.hsync_pol = 1;
+	cfg.ccir_en = 0;
+	cfg.mclken = gcsi_mclk_on ? 1 : 0;
+	cfg.fcc = 1;
+	cfg.pack_dir = 0;
+	cfg.gclk_mode = 1;
+	cfg.inv_data = sig.data_pol;
+	cfg.inv_pclk = sig.pixclk_pol;
+	cfg.redge = 1;
+	cfg.csicnt1_rsv = 0;
+
+	/* control reg 3 */
+	cfg.frmcnt = 0;
+	cfg.frame_reset = 0;
+	cfg.csi_sup = 0;
+	cfg.zero_pack_en = 0;
+	cfg.ecc_int_en = 0;
+	cfg.ecc_auto_en = 0;
+
+	csihw_set_config(&cfg);
+
+	return 0;
+}
+
+/*!
+ * csi_enable_prpif
+ *    Enable or disable CSI-PrP interface
+ * @param       enable        Non-zero to enable, zero to disable
+ */
+void csi_enable_prpif(uint32_t enable)
+{
+	if (enable) {
+		g_csi_cfg.prp_if_en = 1;
+		g_csi_cfg.sof_inten = 0;
+		g_csi_cfg.pack_dir = 0;
+	} else {
+		g_csi_cfg.prp_if_en = 0;
+		g_csi_cfg.sof_inten = 1;
+		g_csi_cfg.pack_dir = 1;
+	}
+
+	csihw_set_config(&g_csi_cfg);
+}
+
+/*!
+ * csi_enable_mclk
+ *
+ * @param       src         enum define which source to control the clk
+ *                          CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C
+ * @param       flag        true to enable mclk, false to disable mclk
+ * @param       wait        true to wait 100ms make clock stable, false not wait
+ *
+ * @return      0 for success
+ */
+int32_t csi_enable_mclk(int src, bool flag, bool wait)
+{
+	if (flag == true) {
+		clk_enable(&csi_mclk);
+		if (wait == true)
+			msleep(10);
+		pr_debug("Enable csi clock from source %d\n", src);
+		gcsi_mclk_on = true;
+	} else {
+		clk_disable(&csi_mclk);
+		pr_debug("Disable csi clock from source %d\n", src);
+		gcsi_mclk_on = false;
+	}
+
+	return 0;
+}
+
+/*!
+ * csi_read_mclk_flag
+ *
+ * @return  gcsi_mclk_source
+ */
+int csi_read_mclk_flag(void)
+{
+	return 0;
+}
+
+void csi_set_callback(csi_irq_callback_t callback, void *data)
+{
+	g_callback = callback;
+	g_callback_data = data;
+}
+
+static void _mclk_recalc(struct clk *clk)
+{
+	u32 div;
+
+	div = (__raw_readl(CSI_CSICR1) & BIT_MCLKDIV) >> SHIFT_MCLKDIV;
+	div = (div + 1) * 2;
+
+	clk->rate = clk->parent->rate / div;
+}
+
+static unsigned long _mclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	/* Keep CSI divider and change parent clock */
+	if (clk->parent->round_rate) {
+		return clk->parent->round_rate(clk->parent, rate * 2);
+	}
+	return 0;
+}
+
+static int _mclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = -EINVAL;
+
+	/* Keep CSI divider and change parent clock */
+	if (clk->parent->set_rate) {
+		ret = clk->parent->set_rate(clk->parent, rate * 2);
+		if (ret == 0) {
+			clk->rate = clk->parent->rate / 2;
+		}
+	}
+
+	return ret;
+}
+
+static int _mclk_enable(struct clk *clk)
+{
+	__raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1);
+	return 0;
+}
+
+static void _mclk_disable(struct clk *clk)
+{
+	__raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1);
+}
+
+static struct clk csi_mclk = {
+	.name = "csi_clk",
+	.recalc = _mclk_recalc,
+	.round_rate = _mclk_round_rate,
+	.set_rate = _mclk_set_rate,
+	.enable = _mclk_enable,
+	.disable = _mclk_disable,
+};
+
+int32_t __init csi_init_module(void)
+{
+	int ret = 0;
+	struct clk *per_clk;
+
+	per_clk = clk_get(NULL, "csi_perclk");
+	if (IS_ERR(per_clk))
+		return PTR_ERR(per_clk);
+	clk_put(per_clk);
+	csi_mclk.parent = per_clk;
+	clk_register(&csi_mclk);
+	clk_enable(per_clk);
+	csi_mclk.recalc(&csi_mclk);
+
+	csihw_reset();
+
+	/* interrupt enable */
+	ret = request_irq(MXC_INT_CSI, csi_irq_handler, 0, "csi", 0);
+	if (ret)
+		pr_debug("CSI error: irq request fail\n");
+
+	return ret;
+}
+
+void __exit csi_cleanup_module(void)
+{
+	/* free irq */
+	free_irq(MXC_INT_CSI, 0);
+
+	clk_disable(&csi_mclk);
+}
+
+module_init(csi_init_module);
+module_exit(csi_cleanup_module);
+
+EXPORT_SYMBOL(csi_init_interface);
+EXPORT_SYMBOL(csi_enable_mclk);
+EXPORT_SYMBOL(csi_read_mclk_flag);
+EXPORT_SYMBOL(csi_set_callback);
+EXPORT_SYMBOL(csi_enable_prpif);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MX27 CSI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/mx27_csi.h b/drivers/media/video/mxc/capture/mx27_csi.h
new file mode 100644
index 000000000000..9bd99781e626
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mx27_csi.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_csi.h
+ *
+ * @brief CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+
+#ifndef MX27_CSI_H
+#define MX27_CSI_H
+
+#include <linux/io.h>
+
+/* reset values */
+#define CSICR1_RESET_VAL	0x40000800
+#define CSICR2_RESET_VAL	0x0
+#define CSICR3_RESET_VAL	0x0
+
+/* csi control reg 1 */
+#define BIT_SWAP16_EN		(0x1 << 31)
+#define BIT_EXT_VSYNC		(0x1 << 30)
+#define BIT_EOF_INT_EN		(0x1 << 29)
+#define BIT_PRP_IF_EN		(0x1 << 28)
+#define BIT_CCIR_MODE		(0x1 << 27)
+#define BIT_COF_INT_EN		(0x1 << 26)
+#define BIT_SF_OR_INTEN		(0x1 << 25)
+#define BIT_RF_OR_INTEN		(0x1 << 24)
+#define BIT_STATFF_LEVEL	(0x3 << 22)
+#define BIT_STATFF_INTEN	(0x1 << 21)
+#define BIT_RXFF_LEVEL		(0x3 << 19)
+#define BIT_RXFF_INTEN		(0x1 << 18)
+#define BIT_SOF_POL		(0x1 << 17)
+#define BIT_SOF_INTEN		(0x1 << 16)
+#define BIT_MCLKDIV		(0xF << 12)
+#define BIT_HSYNC_POL		(0x1 << 11)
+#define BIT_CCIR_EN		(0x1 << 10)
+#define BIT_MCLKEN		(0x1 << 9)
+#define BIT_FCC			(0x1 << 8)
+#define BIT_PACK_DIR		(0x1 << 7)
+#define BIT_CLR_STATFIFO	(0x1 << 6)
+#define BIT_CLR_RXFIFO		(0x1 << 5)
+#define BIT_GCLK_MODE		(0x1 << 4)
+#define BIT_INV_DATA		(0x1 << 3)
+#define BIT_INV_PCLK		(0x1 << 2)
+#define BIT_REDGE		(0x1 << 1)
+
+#define SHIFT_STATFF_LEVEL	22
+#define SHIFT_RXFF_LEVEL	19
+#define SHIFT_MCLKDIV		12
+
+/* control reg 3 */
+#define BIT_FRMCNT		(0xFFFF << 16)
+#define BIT_FRMCNT_RST		(0x1 << 15)
+#define BIT_CSI_SUP		(0x1 << 3)
+#define BIT_ZERO_PACK_EN	(0x1 << 2)
+#define BIT_ECC_INT_EN		(0x1 << 1)
+#define BIT_ECC_AUTO_EN		(0x1)
+
+#define SHIFT_FRMCNT		16
+
+/* csi status reg */
+#define BIT_SFF_OR_INT		(0x1 << 25)
+#define BIT_RFF_OR_INT		(0x1 << 24)
+#define BIT_STATFF_INT		(0x1 << 21)
+#define BIT_RXFF_INT		(0x1 << 18)
+#define BIT_EOF_INT		(0x1 << 17)
+#define BIT_SOF_INT		(0x1 << 16)
+#define BIT_F2_INT		(0x1 << 15)
+#define BIT_F1_INT		(0x1 << 14)
+#define BIT_COF_INT		(0x1 << 13)
+#define BIT_ECC_INT		(0x1 << 1)
+#define BIT_DRDY		(0x1 << 0)
+
+#define CSI_MCLK_VF		1
+#define CSI_MCLK_ENC		2
+#define CSI_MCLK_RAW		4
+#define CSI_MCLK_I2C		8
+
+#define CSI_CSICR1		(IO_ADDRESS(CSI_BASE_ADDR))
+#define CSI_CSICR2		(IO_ADDRESS(CSI_BASE_ADDR + 0x4))
+#define CSI_CSISR		(IO_ADDRESS(CSI_BASE_ADDR + 0x8))
+#define CSI_STATFIFO		(IO_ADDRESS(CSI_BASE_ADDR + 0xC))
+#define CSI_CSIRXFIFO		(IO_ADDRESS(CSI_BASE_ADDR + 0x10))
+#define CSI_CSIRXCNT		(IO_ADDRESS(CSI_BASE_ADDR + 0x14))
+#define CSI_CSICR3		(IO_ADDRESS(CSI_BASE_ADDR + 0x1C))
+
+#define CSI_CSIRXFIFO_PHYADDR	(CSI_BASE_ADDR + 0x10)
+
+static __inline void csi_clear_status(unsigned long status)
+{
+	__raw_writel(status, CSI_CSISR);
+}
+
+typedef struct {
+	unsigned data_width:3;
+	unsigned clk_mode:2;
+	unsigned ext_vsync:1;
+	unsigned Vsync_pol:1;
+	unsigned Hsync_pol:1;
+	unsigned pixclk_pol:1;
+	unsigned data_pol:1;
+	unsigned sens_clksrc:1;
+} csi_signal_cfg_t;
+
+typedef struct {
+	/* control reg 1 */
+	unsigned int swap16_en:1;
+	unsigned int ext_vsync:1;
+	unsigned int eof_int_en:1;
+	unsigned int prp_if_en:1;
+	unsigned int ccir_mode:1;
+	unsigned int cof_int_en:1;
+	unsigned int sf_or_inten:1;
+	unsigned int rf_or_inten:1;
+	unsigned int statff_level:2;
+	unsigned int staff_inten:1;
+	unsigned int rxff_level:2;
+	unsigned int rxff_inten:1;
+	unsigned int sof_pol:1;
+	unsigned int sof_inten:1;
+	unsigned int mclkdiv:4;
+	unsigned int hsync_pol:1;
+	unsigned int ccir_en:1;
+	unsigned int mclken:1;
+	unsigned int fcc:1;
+	unsigned int pack_dir:1;
+	unsigned int gclk_mode:1;
+	unsigned int inv_data:1;
+	unsigned int inv_pclk:1;
+	unsigned int redge:1;
+	unsigned int csicnt1_rsv:1;
+
+	/* control reg 3 */
+	unsigned int frmcnt:16;
+	unsigned int frame_reset:1;
+	unsigned int csi_sup:1;
+	unsigned int zero_pack_en:1;
+	unsigned int ecc_int_en:1;
+	unsigned int ecc_auto_en:1;
+
+	/* fifo counter */
+	unsigned int rxcnt;
+} csi_config_t;
+
+typedef void (*csi_irq_callback_t) (void *data, unsigned long status);
+
+int32_t csi_enable_mclk(int src, bool flag, bool wait);
+int32_t csi_init_interface(uint16_t width, uint16_t height,
+			   uint32_t pixel_fmt, csi_signal_cfg_t sig);
+int csi_read_mclk_flag(void);
+void csi_set_callback(csi_irq_callback_t callback, void *data);
+void csi_enable_prpif(uint32_t enable);
+
+#endif
diff --git a/drivers/media/video/mxc/capture/mx27_prp.h b/drivers/media/video/mxc/capture/mx27_prp.h
new file mode 100644
index 000000000000..e32e9029daff
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mx27_prp.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_prp.h
+ *
+ * @brief Header file for MX27 V4L2 capture driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#ifndef __MX27_PRP_H__
+#define __MX27_PRP_H__
+
+#define PRP_REG(ofs)	(IO_ADDRESS(EMMA_BASE_ADDR) + ofs)
+
+/* Register definitions of PrP */
+#define PRP_CNTL			PRP_REG(0x00)
+#define PRP_INTRCNTL	 		PRP_REG(0x04)
+#define PRP_INTRSTATUS			PRP_REG(0x08)
+#define PRP_SOURCE_Y_PTR		PRP_REG(0x0C)
+#define PRP_SOURCE_CB_PTR		PRP_REG(0x10)
+#define PRP_SOURCE_CR_PTR		PRP_REG(0x14)
+#define PRP_DEST_RGB1_PTR		PRP_REG(0x18)
+#define PRP_DEST_RGB2_PTR		PRP_REG(0x1C)
+#define PRP_DEST_Y_PTR			PRP_REG(0x20)
+#define PRP_DEST_CB_PTR			PRP_REG(0x24)
+#define PRP_DEST_CR_PTR			PRP_REG(0x28)
+#define PRP_SOURCE_FRAME_SIZE  		PRP_REG(0x2C)
+#define PRP_CH1_LINE_STRIDE		PRP_REG(0x30)
+#define PRP_SRC_PIXEL_FORMAT_CNTL	PRP_REG(0x34)
+#define PRP_CH1_PIXEL_FORMAT_CNTL	PRP_REG(0x38)
+#define PRP_CH1_OUT_IMAGE_SIZE		PRP_REG(0x3C)
+#define PRP_CH2_OUT_IMAGE_SIZE		PRP_REG(0x40)
+#define PRP_SOURCE_LINE_STRIDE		PRP_REG(0x44)
+#define PRP_CSC_COEF_012		PRP_REG(0x48)
+#define PRP_CSC_COEF_345		PRP_REG(0x4C)
+#define PRP_CSC_COEF_678		PRP_REG(0x50)
+#define PRP_CH1_RZ_HORI_COEF1		PRP_REG(0x54)
+#define PRP_CH1_RZ_HORI_COEF2		PRP_REG(0x58)
+#define PRP_CH1_RZ_HORI_VALID		PRP_REG(0x5C)
+#define PRP_CH1_RZ_VERT_COEF1		PRP_REG(0x60)
+#define PRP_CH1_RZ_VERT_COEF2		PRP_REG(0x64)
+#define PRP_CH1_RZ_VERT_VALID		PRP_REG(0x68)
+#define PRP_CH2_RZ_HORI_COEF1		PRP_REG(0x6C)
+#define PRP_CH2_RZ_HORI_COEF2		PRP_REG(0x70)
+#define PRP_CH2_RZ_HORI_VALID		PRP_REG(0x74)
+#define PRP_CH2_RZ_VERT_COEF1		PRP_REG(0x78)
+#define PRP_CH2_RZ_VERT_COEF2		PRP_REG(0x7C)
+#define PRP_CH2_RZ_VERT_VALID		PRP_REG(0x80)
+
+#define B_SET(b)			(1 << (b))
+
+/* Bit definitions for PrP control register */
+#define PRP_CNTL_RSTVAL			0x28
+#define PRP_CNTL_CH1EN			B_SET(0)
+#define PRP_CNTL_CH2EN			B_SET(1)
+#define PRP_CNTL_CSI			B_SET(2)
+#define PRP_CNTL_IN_32			B_SET(3)
+#define PRP_CNTL_IN_RGB			B_SET(4)
+#define PRP_CNTL_IN_YUV420		0
+#define PRP_CNTL_IN_YUV422		PRP_CNTL_IN_32
+#define PRP_CNTL_IN_RGB16		PRP_CNTL_IN_RGB
+#define PRP_CNTL_IN_RGB32		(PRP_CNTL_IN_RGB | PRP_CNTL_IN_32)
+#define PRP_CNTL_CH1_RGB8		0
+#define PRP_CNTL_CH1_RGB16		B_SET(5)
+#define PRP_CNTL_CH1_RGB32		B_SET(6)
+#define PRP_CNTL_CH1_YUV422		(B_SET(5) | B_SET(6))
+#define PRP_CNTL_CH2_YUV420		0
+#define PRP_CNTL_CH2_YUV422		B_SET(7)
+#define PRP_CNTL_CH2_YUV444		B_SET(8)
+#define PRP_CNTL_CH1_LOOP		B_SET(9)
+#define PRP_CNTL_CH2_LOOP		B_SET(10)
+#define PRP_CNTL_AUTODROP		B_SET(11)
+#define PRP_CNTL_RST			B_SET(12)
+#define PRP_CNTL_CNTREN			B_SET(13)
+#define PRP_CNTL_WINEN			B_SET(14)
+#define PRP_CNTL_UNCHAIN		B_SET(15)
+#define PRP_CNTL_IN_SKIP_NONE		0
+#define PRP_CNTL_IN_SKIP_1_2		B_SET(16)
+#define PRP_CNTL_IN_SKIP_1_3		B_SET(17)
+#define PRP_CNTL_IN_SKIP_2_3		(B_SET(16) | B_SET(17))
+#define PRP_CNTL_IN_SKIP_1_4		B_SET(18)
+#define PRP_CNTL_IN_SKIP_3_4		(B_SET(16) | B_SET(18))
+#define PRP_CNTL_IN_SKIP_2_5		(B_SET(17) | B_SET(18))
+#define PRP_CNTL_IN_SKIP_3_5		(B_SET(16) | B_SET(17) | B_SET(18))
+#define PRP_CNTL_CH1_SKIP_NONE		0
+#define PRP_CNTL_CH1_SKIP_1_2		B_SET(19)
+#define PRP_CNTL_CH1_SKIP_1_3		B_SET(20)
+#define PRP_CNTL_CH1_SKIP_2_3		(B_SET(19) | B_SET(20))
+#define PRP_CNTL_CH1_SKIP_1_4		B_SET(21)
+#define PRP_CNTL_CH1_SKIP_3_4		(B_SET(19) | B_SET(21))
+#define PRP_CNTL_CH1_SKIP_2_5		(B_SET(20) | B_SET(21))
+#define PRP_CNTL_CH1_SKIP_3_5		(B_SET(19) | B_SET(20) | B_SET(21))
+#define PRP_CNTL_CH2_SKIP_NONE		0
+#define PRP_CNTL_CH2_SKIP_1_2		B_SET(22)
+#define PRP_CNTL_CH2_SKIP_1_3		B_SET(23)
+#define PRP_CNTL_CH2_SKIP_2_3		(B_SET(22) | B_SET(23))
+#define PRP_CNTL_CH2_SKIP_1_4		B_SET(24)
+#define PRP_CNTL_CH2_SKIP_3_4		(B_SET(22) | B_SET(24))
+#define PRP_CNTL_CH2_SKIP_2_5		(B_SET(23) | B_SET(24))
+#define PRP_CNTL_CH2_SKIP_3_5		(B_SET(22) | B_SET(23) | B_SET(24))
+#define PRP_CNTL_FIFO_I128		0
+#define PRP_CNTL_FIFO_I96		B_SET(25)
+#define PRP_CNTL_FIFO_I64		B_SET(26)
+#define PRP_CNTL_FIFO_I32		(B_SET(25) | B_SET(26))
+#define PRP_CNTL_FIFO_O64		0
+#define PRP_CNTL_FIFO_O48		B_SET(27)
+#define PRP_CNTL_FIFO_O32		B_SET(28)
+#define PRP_CNTL_FIFO_O16		(B_SET(27) | B_SET(28))
+#define PRP_CNTL_CH2B1			B_SET(29)
+#define PRP_CNTL_CH2B2			B_SET(30)
+#define PRP_CNTL_CH2_FLOWEN		B_SET(31)
+
+/* Bit definitions for PrP interrupt control register */
+#define PRP_INTRCNTL_RDERR		B_SET(0)
+#define PRP_INTRCNTL_CH1WERR		B_SET(1)
+#define PRP_INTRCNTL_CH2WERR		B_SET(2)
+#define PRP_INTRCNTL_CH1FC		B_SET(3)
+#define PRP_INTRCNTL_CH2FC		B_SET(5)
+#define PRP_INTRCNTL_LBOVF		B_SET(7)
+#define PRP_INTRCNTL_CH2OVF		B_SET(8)
+
+/* Bit definitions for PrP interrupt status register */
+#define PRP_INTRSTAT_RDERR		B_SET(0)
+#define PRP_INTRSTAT_CH1WERR		B_SET(1)
+#define PRP_INTRSTAT_CH2WERR		B_SET(2)
+#define PRP_INTRSTAT_CH2BUF2		B_SET(3)
+#define PRP_INTRSTAT_CH2BUF1		B_SET(4)
+#define PRP_INTRSTAT_CH1BUF2		B_SET(5)
+#define PRP_INTRSTAT_CH1BUF1		B_SET(6)
+#define PRP_INTRSTAT_LBOVF		B_SET(7)
+#define PRP_INTRSTAT_CH2OVF		B_SET(8)
+
+#define PRP_CHANNEL_1		0x1
+#define PRP_CHANNEL_2		0x2
+
+/* PRP-CSI config */
+#define PRP_CSI_EN		0x80
+#define PRP_CSI_LOOP		(0x40 | PRP_CSI_EN)
+#define PRP_CSI_IRQ_FRM		(0x08 | PRP_CSI_LOOP)
+#define PRP_CSI_IRQ_CH1ERR	(0x10 | PRP_CSI_LOOP)
+#define PRP_CSI_IRQ_CH2ERR	(0x20 | PRP_CSI_LOOP)
+#define PRP_CSI_IRQ_ALL		(0x38 | PRP_CSI_LOOP)
+#define PRP_CSI_SKIP_NONE	0
+#define PRP_CSI_SKIP_1OF2	1
+#define PRP_CSI_SKIP_1OF3	2
+#define PRP_CSI_SKIP_2OF3	3
+#define PRP_CSI_SKIP_1OF4	4
+#define PRP_CSI_SKIP_3OF4	5
+#define PRP_CSI_SKIP_2OF5	6
+#define PRP_CSI_SKIP_4OF5	7
+
+#define PRP_PIXIN_RGB565	0x2CA00565
+#define PRP_PIXIN_RGB888	0x41000888
+#define PRP_PIXIN_YUV420	0
+#define PRP_PIXIN_YUYV		0x22000888
+#define PRP_PIXIN_YVYU		0x20100888
+#define PRP_PIXIN_UYVY		0x03080888
+#define PRP_PIXIN_VYUY		0x01180888
+#define PRP_PIXIN_YUV422	0x62080888
+
+#define PRP_PIX1_RGB332		0x14400322
+#define PRP_PIX1_RGB565		0x2CA00565
+#define PRP_PIX1_RGB888		0x41000888
+#define PRP_PIX1_YUYV		0x62000888
+#define PRP_PIX1_YVYU		0x60100888
+#define PRP_PIX1_UYVY		0x43080888
+#define PRP_PIX1_VYUY		0x41180888
+#define PRP_PIX1_UNUSED		0
+
+#define PRP_PIX2_YUV420		0
+#define PRP_PIX2_YUV422		1
+#define PRP_PIX2_YUV444		4
+#define PRP_PIX2_UNUSED		8
+
+#define PRP_ALGO_WIDTH_ANY	0
+#define PRP_ALGO_HEIGHT_ANY	0
+#define PRP_ALGO_WIDTH_BIL	1
+#define PRP_ALGO_WIDTH_AVG	2
+#define PRP_ALGO_HEIGHT_BIL	4
+#define PRP_ALGO_HEIGHT_AVG	8
+#define PRP_ALGO_BYPASS		0x10
+
+typedef struct _emma_prp_ratio {
+	unsigned short num;
+	unsigned short den;
+} emma_prp_ratio;
+
+/*
+ * The following definitions are for resizing. Definition values must not
+ * be changed otherwise decision logic will be wrong.
+ */
+#define SCALE_RETRY	16	/* retry times if ratio is not supported */
+
+#define BC_COEF		3
+#define MAX_TBL		20
+#define SZ_COEF		(1 << BC_COEF)
+
+#define ALGO_AUTO	0
+#define ALGO_BIL	1
+#define ALGO_AVG	2
+
+typedef struct {
+	char tbl[20];		/* table entries */
+	char len;		/* table length used */
+	char algo;		/* ALGO_xxx */
+	char ratio[20];		/* ratios used */
+} scale_t;
+
+/*
+ * structure for prp scaling.
+ * algorithm - bilinear or averaging for each axis
+ * PRP_ALGO_WIDTH_x | PRP_ALGO_HEIGHT_x | PRP_ALGO_BYPASS
+ * PRP_ALGO_BYPASS - Ch1 will not use Ch2 scaling with this flag
+ */
+typedef struct _emma_prp_scale {
+	unsigned char algo;
+	emma_prp_ratio width;
+	emma_prp_ratio height;
+} emma_prp_scale;
+
+typedef struct emma_prp_cfg {
+	unsigned int in_pix;	/* PRP_PIXIN_xxx */
+	unsigned short in_width;	/* image width, 32 - 2044 */
+	unsigned short in_height;	/* image height, 32 - 2044 */
+	unsigned char in_csi;	/* PRP_CSI_SKIP_x | PRP_CSI_LOOP */
+	unsigned short in_line_stride;	/* in_line_stride and in_line_skip */
+	unsigned short in_line_skip;	/* allow cropping from CSI */
+	unsigned int in_ptr;	/* bus address */
+	/*
+	 * in_csc[9] = 1 -> Y-16
+	 * if in_csc[1..9] == 0
+	 *      in_csc[0] represents YUV range 0-3 = A0,A1,B0,B1;
+	 * else
+	 *      in_csc[0..9] represents either format
+	 */
+	unsigned short in_csc[10];
+
+	unsigned char ch2_pix;	/* PRP_PIX2_xxx */
+	emma_prp_scale ch2_scale;	/* resizing paramters */
+	unsigned short ch2_width;	/* 4-2044, 0 = scaled */
+	unsigned short ch2_height;	/* 4-2044, 0 = scaled */
+	unsigned int ch2_ptr;	/* bus addr */
+	unsigned int ch2_ptr2;	/* bus addr for 2nd buf (loop mode) */
+	unsigned char ch2_csi;	/* PRP_CSI_SKIP_x | PRP_CSI_LOOP */
+
+	unsigned int ch1_pix;	/* PRP_PIX1_xxx */
+	emma_prp_scale ch1_scale;	/* resizing parameters */
+	unsigned short ch1_width;	/* 4-2044, 0 = scaled */
+	unsigned short ch1_height;	/* 4-2044, 0 = scaled */
+	unsigned short ch1_stride;	/* 4-4088, 0 = ch1_width */
+	unsigned int ch1_ptr;	/* bus addr */
+	unsigned int ch1_ptr2;	/* bus addr for 2nd buf (loop mode) */
+	unsigned char ch1_csi;	/* PRP_CSI_SKIP_x | PRP_CSI_LOOP */
+
+	/*
+	 * channel resizing coefficients
+	 * scale[0] for channel 1 width
+	 * scale[1] for channel 1 height
+	 * scale[2] for channel 2 width
+	 * scale[3] for channel 2 height
+	 */
+	scale_t scale[4];
+} emma_prp_cfg;
+
+int prphw_reset(void);
+int prphw_enable(int channel);
+int prphw_disable(int channel);
+int prphw_inptr(emma_prp_cfg *);
+int prphw_ch1ptr(emma_prp_cfg *);
+int prphw_ch1ptr2(emma_prp_cfg *);
+int prphw_ch2ptr(emma_prp_cfg *);
+int prphw_ch2ptr2(emma_prp_cfg *);
+int prphw_cfg(emma_prp_cfg *);
+int prphw_isr(void);
+void prphw_init(void);
+void prphw_exit(void);
+
+/*
+ * scale	out	coefficient table
+ * din		in	scale numerator
+ * dout		in	scale denominator
+ * inv		in	pre-scale dimension
+ * vout		in/out	post-scale output dimension
+ * pout		out	post-scale internal dimension [opt]
+ * retry	in	retry times (round the output length) when need
+ */
+int prp_scale(scale_t * pscale, int din, int dout, int inv,
+	      unsigned short *vout, unsigned short *pout, int retry);
+
+int prp_init(void *dev_id);
+void prp_exit(void *dev_id);
+int prp_enc_select(void *data);
+int prp_enc_deselect(void *data);
+int prp_vf_select(void *data);
+int prp_vf_deselect(void *data);
+int prp_still_select(void *data);
+int prp_still_deselect(void *data);
+
+#endif				/* __MX27_PRP_H__ */
diff --git a/drivers/media/video/mxc/capture/mx27_prphw.c b/drivers/media/video/mxc/capture/mx27_prphw.c
new file mode 100644
index 000000000000..c56a6df1716e
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mx27_prphw.c
@@ -0,0 +1,1099 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_prphw.c
+ *
+ * @brief MX27 Video For Linux 2 capture driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#include "mx27_prp.h"
+
+#define PRP_MIN_IN_WIDTH	32
+#define PRP_MAX_IN_WIDTH	2044
+#define PRP_MIN_IN_HEIGHT	32
+#define PRP_MAX_IN_HEIGHT	2044
+
+typedef struct _coeff_t {
+	unsigned long coeff[2];
+	unsigned long cntl;
+} coeff_t[2][2];
+
+static coeff_t *PRP_RSZ_COEFF = (coeff_t *) PRP_CH1_RZ_HORI_COEF1;
+
+static unsigned char scale_get(scale_t * t,
+			       unsigned char *i, unsigned char *out);
+static int gcd(int x, int y);
+static int ratio(int x, int y, int *den);
+static int prp_scale_bilinear(scale_t * t, int coeff, int base, int nxt);
+static int prp_scale_ave(scale_t * t, unsigned char base);
+static int ave_scale(scale_t * t, int inv, int outv);
+static int scale(scale_t * t, int inv, int outv);
+
+/*!
+ * @param t	table
+ * @param i	table index
+ * @param out	bilinear	# input pixels to advance
+ *		average		whether result is ready for output
+ * @return	coefficient
+*/
+static unsigned char scale_get(scale_t * t, unsigned char *i,
+			       unsigned char *out)
+{
+	unsigned char c;
+
+	c = t->tbl[*i];
+	(*i)++;
+	*i %= t->len;
+
+	if (out) {
+		if (t->algo == ALGO_BIL) {
+			for ((*out) = 1;
+			     (*i) && ((*i) < t->len) && !t->tbl[(*i)]; (*i)++) {
+				(*out)++;
+			}
+			if ((*i) == t->len)
+				(*i) = 0;
+		} else
+			*out = c >> BC_COEF;
+	}
+
+	c &= SZ_COEF - 1;
+
+	if (c == SZ_COEF - 1)
+		c = SZ_COEF;
+
+	return c;
+}
+
+/*!
+ * @brief Get maximum common divisor.
+ * @param x	First input value
+ * @param y	Second input value
+ * @return	Maximum common divisor of x and y
+ */
+static int gcd(int x, int y)
+{
+	int k;
+
+	if (x < y) {
+		k = x;
+		x = y;
+		y = k;
+	}
+
+	while ((k = x % y)) {
+		x = y;
+		y = k;
+	}
+
+	return y;
+}
+
+/*!
+ * @brief Get ratio.
+ * @param x	First input value
+ * @param y	Second input value
+ * @param den	Denominator of the ratio (corresponding to y)
+ * @return	Numerator of the ratio (corresponding to x)
+ */
+static int ratio(int x, int y, int *den)
+{
+	int g;
+
+	if (!x || !y)
+		return 0;
+
+	g = gcd(x, y);
+	*den = y / g;
+
+	return x / g;
+}
+
+/*!
+ * @brief Build PrP coefficient entry based on bilinear algorithm
+ *
+ * @param t	The pointer to scale_t structure
+ * @param coeff	The weighting coefficient
+ * @param base	The base of the coefficient
+ * @param nxt	Number of pixels to be read
+ *
+ * @return	The length of current coefficient table on success
+ *		-1 on failure
+ */
+static int prp_scale_bilinear(scale_t * t, int coeff, int base, int nxt)
+{
+	int i;
+
+	if (t->len >= sizeof(t->tbl))
+		return -1;
+
+	coeff = ((coeff << BC_COEF) + (base >> 1)) / base;
+	if (coeff >= SZ_COEF - 1)
+		coeff--;
+
+	coeff |= SZ_COEF;
+	t->tbl[(int)t->len++] = (unsigned char)coeff;
+
+	for (i = 1; i < nxt; i++) {
+		if (t->len >= MAX_TBL)
+			return -1;
+
+		t->tbl[(int)t->len++] = 0;
+	}
+
+	return t->len;
+}
+
+#define _bary(name)	static const unsigned char name[]
+
+_bary(c1) = {
+7};
+
+_bary(c2) = {
+4, 4};
+
+_bary(c3) = {
+2, 4, 2};
+
+_bary(c4) = {
+2, 2, 2, 2};
+
+_bary(c5) = {
+1, 2, 2, 2, 1};
+
+_bary(c6) = {
+1, 1, 2, 2, 1, 1};
+
+_bary(c7) = {
+1, 1, 1, 2, 1, 1, 1};
+
+_bary(c8) = {
+1, 1, 1, 1, 1, 1, 1, 1};
+
+_bary(c9) = {
+1, 1, 1, 1, 1, 1, 1, 1, 0};
+
+_bary(c10) = {
+0, 1, 1, 1, 1, 1, 1, 1, 1, 0};
+
+_bary(c11) = {
+0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0};
+
+_bary(c12) = {
+0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0};
+
+_bary(c13) = {
+0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0};
+
+_bary(c14) = {
+0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0};
+
+_bary(c15) = {
+0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0};
+
+_bary(c16) = {
+1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+
+_bary(c17) = {
+0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+
+_bary(c18) = {
+0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+
+_bary(c19) = {
+0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0};
+
+_bary(c20) = {
+0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0};
+
+static const unsigned char *ave_coeff[] = {
+	c1, c2, c3, c4, c5, c6, c7, c8, c9, c10,
+	c11, c12, c13, c14, c15, c16, c17, c18, c19, c20
+};
+
+/*!
+ * @brief Build PrP coefficient table based on average algorithm
+ *
+ * @param t	The pointer to scale_t structure
+ * @param base	The base of the coefficient
+ *
+ * @return	The length of current coefficient table on success
+ *		-1 on failure
+ */
+static int prp_scale_ave(scale_t * t, unsigned char base)
+{
+	if (t->len + base > sizeof(t->tbl))
+		return -1;
+
+	memcpy(&t->tbl[(int)t->len], ave_coeff[(int)base - 1], base);
+	t->len = (unsigned char)(t->len + base);
+	t->tbl[t->len - 1] |= SZ_COEF;
+
+	return t->len;
+}
+
+/*!
+ * @brief Build PrP coefficient table based on average algorithm
+ *
+ * @param t	The pointer to scale_t structure
+ * @param inv	Input resolution
+ * @param outv	Output resolution
+ *
+ * @return	The length of current coefficient table on success
+ *		-1 on failure
+ */
+static int ave_scale(scale_t * t, int inv, int outv)
+{
+	int ratio_count;
+
+	ratio_count = 0;
+	if (outv != 1) {
+		unsigned char a[20];
+		int v;
+
+		/* split n:m into multiple n[i]:1 */
+		for (v = 0; v < outv; v++)
+			a[v] = (unsigned char)(inv / outv);
+
+		inv %= outv;
+		if (inv) {
+			/* find start of next layer */
+			v = (outv - inv) >> 1;
+			inv += v;
+			for (; v < inv; v++)
+				a[v]++;
+		}
+
+		for (v = 0; v < outv; v++) {
+			if (prp_scale_ave(t, a[v]) < 0)
+				return -1;
+
+			t->ratio[ratio_count] = a[v];
+			ratio_count++;
+		}
+	} else if (prp_scale_ave(t, inv) < 0) {
+		return -1;
+	} else {
+		t->ratio[ratio_count++] = (char)inv;
+		ratio_count++;
+	}
+
+	return t->len;
+}
+
+/*!
+ * @brief Build PrP coefficient table
+ *
+ * @param t	The pointer to scale_t structure
+ * @param inv	input resolution reduced ratio
+ * @param outv	output resolution reduced ratio
+ *
+ * @return	The length of current coefficient table on success
+ *		-1 on failure
+ */
+static int scale(scale_t * t, int inv, int outv)
+{
+	int v;			/* overflow counter */
+	int coeff, nxt;		/* table output */
+
+	t->len = 0;
+	if (t->algo == ALGO_AUTO) {
+		/* automatic choice - bilinear for shrinking less than 2:1 */
+		t->algo = ((outv != inv) && ((2 * outv) > inv)) ?
+		    ALGO_BIL : ALGO_AVG;
+	}
+
+	/* 1:1 resize must use averaging, bilinear will hang */
+	if ((inv == outv) && (t->algo == ALGO_BIL)) {
+		pr_debug("Warning: 1:1 resize must use averaging algo\n");
+		t->algo = ALGO_AVG;
+	}
+
+	memset(t->tbl, 0, sizeof(t->tbl));
+	if (t->algo == ALGO_BIL) {
+		t->ratio[0] = (char)inv;
+		t->ratio[1] = (char)outv;
+	} else
+		memset(t->ratio, 0, sizeof(t->ratio));
+
+	if (inv == outv) {
+		/* force scaling */
+		t->ratio[0] = 1;
+		if (t->algo == ALGO_BIL)
+			t->ratio[1] = 1;
+
+		return prp_scale_ave(t, 1);
+	}
+
+	if (inv < outv) {
+		pr_debug("Upscaling not supported %d:%d\n", inv, outv);
+		return -1;
+	}
+
+	if (t->algo != ALGO_BIL)
+		return ave_scale(t, inv, outv);
+
+	v = 0;
+	if (inv >= 2 * outv) {
+		/* downscale: >=2:1 bilinear approximation */
+		coeff = inv - 2 * outv;
+		v = 0;
+		nxt = 0;
+		do {
+			v += coeff;
+			nxt = 2;
+			while (v >= outv) {
+				v -= outv;
+				nxt++;
+			}
+
+			if (prp_scale_bilinear(t, 1, 2, nxt) < 0)
+				return -1;
+		} while (v);
+	} else {
+		/* downscale: bilinear */
+		int in_pos_inc = 2 * outv;
+		int out_pos = inv;
+		int out_pos_inc = 2 * inv;
+		int init_carry = inv - outv;
+		int carry = init_carry;
+
+		v = outv + in_pos_inc;
+		do {
+			coeff = v - out_pos;
+			out_pos += out_pos_inc;
+			carry += out_pos_inc;
+			for (nxt = 0; v < out_pos; nxt++) {
+				v += in_pos_inc;
+				carry -= in_pos_inc;
+			}
+			if (prp_scale_bilinear(t, coeff, in_pos_inc, nxt) < 0)
+				return -1;
+		} while (carry != init_carry);
+	}
+	return t->len;
+}
+
+/*!
+ * @brief Build PrP coefficient table
+ *
+ * @param pscale	The pointer to scale_t structure which holdes
+ * 			coefficient tables
+ * @param din		Scale ratio numerator
+ * @param dout		Scale ratio denominator
+ * @param inv		Input resolution
+ * @param vout		Output resolution
+ * @param pout		Internal output resolution
+ * @param retry		Retry times (round the output length) when need
+ *
+ * @return		Zero on success, others on failure
+ */
+int prp_scale(scale_t * pscale, int din, int dout, int inv,
+	      unsigned short *vout, unsigned short *pout, int retry)
+{
+	int num;
+	int den;
+	unsigned short outv;
+
+	/* auto-generation of values */
+	if (!(dout && din)) {
+		if (!*vout)
+			dout = din = 1;
+		else {
+			din = inv;
+			dout = *vout;
+		}
+	}
+
+	if (din < dout) {
+		pr_debug("Scale err, unsupported ratio %d : %d\n", din, dout);
+		return -1;
+	}
+
+      lp_retry:
+	num = ratio(din, dout, &den);
+	if (!num) {
+		pr_debug("Scale err, unsupported ratio %d : %d\n", din, dout);
+		return -1;
+	}
+
+	if (num > MAX_TBL || scale(pscale, num, den) < 0) {
+		dout++;
+		if (retry--)
+			goto lp_retry;
+
+		pr_debug("Scale err, unsupported ratio %d : %d\n", num, den);
+		return -1;
+	}
+
+	if (pscale->algo == ALGO_BIL) {
+		unsigned char i, j, k;
+
+		outv =
+		    (unsigned short)(inv / pscale->ratio[0] * pscale->ratio[1]);
+		inv %= pscale->ratio[0];
+		for (i = j = 0; inv > 0; j++) {
+			unsigned char nxt;
+
+			k = scale_get(pscale, &i, &nxt);
+			if (inv == 1 && k < SZ_COEF) {
+				/* needs 2 pixels for this output */
+				break;
+			}
+			inv -= nxt;
+		}
+		outv = outv + j;
+	} else {
+		unsigned char i, tot;
+
+		for (tot = i = 0; pscale->ratio[i]; i++)
+			tot = tot + pscale->ratio[i];
+
+		outv = (unsigned short)(inv / tot) * i;
+		inv %= tot;
+		for (i = 0; inv > 0; i++, outv++)
+			inv -= pscale->ratio[i];
+	}
+
+	if (!(*vout) || ((*vout) > outv))
+		*vout = outv;
+
+	if (pout)
+		*pout = outv;
+
+	return 0;
+}
+
+/*!
+ * @brief Reset PrP block
+ */
+int prphw_reset(void)
+{
+	unsigned long val;
+	unsigned long flag;
+	int i;
+
+	flag = PRP_CNTL_RST;
+	val = PRP_CNTL_RSTVAL;
+
+	__raw_writel(flag, PRP_CNTL);
+
+	/* timeout */
+	for (i = 0; i < 1000; i++) {
+		if (!(__raw_readl(PRP_CNTL) & flag)) {
+			pr_debug("PrP reset over\n");
+			break;
+		}
+		msleep(1);
+	}
+
+	/* verify reset value */
+	if (__raw_readl(PRP_CNTL) != val) {
+		pr_info("PrP reset err, val = 0x%08X\n", __raw_readl(PRP_CNTL));
+		return -1;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Enable PrP channel.
+ * @param channel	Channel number to be enabled
+ * @return		Zero on success, others on failure
+ */
+int prphw_enable(int channel)
+{
+	unsigned long val;
+
+	val = __raw_readl(PRP_CNTL);
+	if (channel & PRP_CHANNEL_1)
+		val |= PRP_CNTL_CH1EN;
+	if (channel & PRP_CHANNEL_2)
+		val |= (PRP_CNTL_CH2EN | PRP_CNTL_CH2_FLOWEN);
+
+	__raw_writel(val, PRP_CNTL);
+
+	return 0;
+}
+
+/*!
+ * @brief Disable PrP channel.
+ * @param channel	Channel number to be disable
+ * @return		Zero on success, others on failure
+ */
+int prphw_disable(int channel)
+{
+	unsigned long val;
+
+	val = __raw_readl(PRP_CNTL);
+	if (channel & PRP_CHANNEL_1)
+		val &= ~PRP_CNTL_CH1EN;
+	if (channel & PRP_CHANNEL_2)
+		val &= ~(PRP_CNTL_CH2EN | PRP_CNTL_CH2_FLOWEN);
+
+	__raw_writel(val, PRP_CNTL);
+
+	return 0;
+}
+
+/*!
+ * @brief Set PrP input buffer address.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_inptr(emma_prp_cfg * cfg)
+{
+	if (cfg->in_csi & PRP_CSI_EN)
+		return -1;
+
+	__raw_writel(cfg->in_ptr, PRP_SOURCE_Y_PTR);
+	if (cfg->in_pix == PRP_PIXIN_YUV420) {
+		u32 size;
+
+		size = cfg->in_line_stride * cfg->in_height;
+		__raw_writel(cfg->in_ptr + size, PRP_SOURCE_CB_PTR);
+		__raw_writel(cfg->in_ptr + size + (size >> 2),
+			     PRP_SOURCE_CR_PTR);
+	}
+	return 0;
+}
+
+/*!
+ * @brief Set PrP channel 1 output buffer 1 address.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_ch1ptr(emma_prp_cfg * cfg)
+{
+	if (cfg->ch1_pix == PRP_PIX1_UNUSED)
+		return -1;
+
+	__raw_writel(cfg->ch1_ptr, PRP_DEST_RGB1_PTR);
+
+	/* support double buffer in loop mode only */
+	if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) {
+		if (cfg->ch1_ptr2)
+			__raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR);
+		else
+			__raw_writel(cfg->ch1_ptr, PRP_DEST_RGB2_PTR);
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Set PrP channel 1 output buffer 2 address.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_ch1ptr2(emma_prp_cfg * cfg)
+{
+	if (cfg->ch1_pix == PRP_PIX1_UNUSED ||
+	    (cfg->in_csi & PRP_CSI_LOOP) != PRP_CSI_LOOP)
+		return -1;
+
+	if (cfg->ch1_ptr2)
+		__raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR);
+	else
+		return -1;
+
+	return 0;
+}
+
+/*!
+ * @brief Set PrP channel 2 output buffer 1 address.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_ch2ptr(emma_prp_cfg * cfg)
+{
+	u32 size;
+
+	if (cfg->ch2_pix == PRP_PIX2_UNUSED)
+		return -1;
+
+	__raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR);
+
+	if (cfg->ch2_pix == PRP_PIX2_YUV420) {
+		size = cfg->ch2_width * cfg->ch2_height;
+		__raw_writel(cfg->ch2_ptr + size, PRP_DEST_CB_PTR);
+		__raw_writel(cfg->ch2_ptr + size + (size >> 2),
+			     PRP_DEST_CR_PTR);
+	}
+
+	__raw_writel(__raw_readl(PRP_CNTL) | PRP_CNTL_CH2B1, PRP_CNTL);
+	return 0;
+}
+
+/*!
+ * @brief Set PrP channel 2 output buffer 2 address.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_ch2ptr2(emma_prp_cfg * cfg)
+{
+	u32 size;
+
+	if (cfg->ch2_pix == PRP_PIX2_UNUSED ||
+	    (cfg->in_csi & PRP_CSI_LOOP) != PRP_CSI_LOOP)
+		return -1;
+
+	__raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR);
+	if (cfg->ch2_pix == PRP_PIX2_YUV420) {
+		size = cfg->ch2_width * cfg->ch2_height;
+		__raw_writel(cfg->ch2_ptr2 + size, PRP_SOURCE_CB_PTR);
+		__raw_writel(cfg->ch2_ptr2 + size + (size >> 2),
+			     PRP_SOURCE_CR_PTR);
+	}
+
+	__raw_writel(__raw_readl(PRP_CNTL) | PRP_CNTL_CH2B2, PRP_CNTL);
+	return 0;
+}
+
+/*!
+ * @brief Build CSC table
+ * @param csc	CSC table
+ *		in	csc[0]=index		0..3 : A.1 A.0 B.1 B.0
+ *			csc[1]=direction	0 : YUV2RGB  1 : RGB2YUV
+ *		out	csc[0..4] are coefficients c[9] is offset
+ *			csc[0..8] are coefficients c[9] is offset
+ */
+void csc_tbl(short csc[10])
+{
+	static const unsigned short _r2y[][9] = {
+		{0x4D, 0x4B, 0x3A, 0x57, 0x55, 0x40, 0x40, 0x6B, 0x29},
+		{0x42, 0x41, 0x32, 0x4C, 0x4A, 0x38, 0x38, 0x5E, 0x24},
+		{0x36, 0x5C, 0x25, 0x3B, 0x63, 0x40, 0x40, 0x74, 0x18},
+		{0x2F, 0x4F, 0x20, 0x34, 0x57, 0x38, 0x38, 0x66, 0x15},
+	};
+	static const unsigned short _y2r[][5] = {
+		{0x80, 0xb4, 0x2c, 0x5b, 0x0e4},
+		{0x95, 0xcc, 0x32, 0x68, 0x104},
+		{0x80, 0xca, 0x18, 0x3c, 0x0ec},
+		{0x95, 0xe5, 0x1b, 0x44, 0x1e0},
+	};
+	unsigned short *_csc;
+	int _csclen;
+
+	csc[9] = csc[0] & 1;
+	_csclen = csc[0] & 3;
+
+	if (csc[1]) {
+		_csc = (unsigned short *)_r2y[_csclen];
+		_csclen = sizeof(_r2y[0]);
+	} else {
+		_csc = (unsigned short *)_y2r[_csclen];
+		_csclen = sizeof(_y2r[0]);
+		memset(csc + 5, 0, sizeof(short) * 4);
+	}
+	memcpy(csc, _csc, _csclen);
+}
+
+/*!
+ * @brief Setup PrP resize coefficient registers
+ *
+ * @param ch	PrP channel number
+ * @param dir	Direction, 0 - horizontal, 1 - vertical
+ * @param scale	The pointer to scale_t structure
+ */
+static void prp_set_scaler(int ch, int dir, scale_t * scale)
+{
+	int i;
+	unsigned int coeff[2];
+	unsigned int valid;
+
+	for (coeff[0] = coeff[1] = valid = 0, i = 19; i >= 0; i--) {
+		int j;
+
+		j = i > 9 ? 1 : 0;
+		coeff[j] = (coeff[j] << BC_COEF) |
+		    (scale->tbl[i] & (SZ_COEF - 1));
+
+		if (i == 5 || i == 15)
+			coeff[j] <<= 1;
+
+		valid = (valid << 1) | (scale->tbl[i] >> BC_COEF);
+	}
+
+	valid |= (scale->len << 24) | ((2 - scale->algo) << 31);
+
+	for (i = 0; i < 2; i++)
+		(*PRP_RSZ_COEFF)[1 - ch][dir].coeff[i] = coeff[i];
+
+	(*PRP_RSZ_COEFF)[1 - ch][dir].cntl = valid;
+}
+
+/*!
+ * @brief Setup PrP registers relevant to input.
+ * @param cfg		Pointer to PrP configuration parameter
+ * @param prp_cntl	Holds the value for PrP control register
+ * @return		Zero on success, others on failure
+ */
+static int prphw_input_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl)
+{
+	unsigned long mask;
+
+	switch (cfg->in_pix) {
+	case PRP_PIXIN_YUV420:
+		*prp_cntl |= PRP_CNTL_IN_YUV420;
+		mask = 0x7;
+		break;
+	case PRP_PIXIN_YUYV:
+	case PRP_PIXIN_YVYU:
+	case PRP_PIXIN_UYVY:
+	case PRP_PIXIN_VYUY:
+		*prp_cntl |= PRP_CNTL_IN_YUV422;
+		mask = 0x1;
+		break;
+	case PRP_PIXIN_RGB565:
+		*prp_cntl |= PRP_CNTL_IN_RGB16;
+		mask = 0x1;
+		break;
+	case PRP_PIXIN_RGB888:
+		*prp_cntl |= PRP_CNTL_IN_RGB32;
+		mask = 0;
+		break;
+	default:
+		pr_debug("Unsupported input pix format 0x%08X\n", cfg->in_pix);
+		return -1;
+	}
+
+	/* align the input image width */
+	if (cfg->in_width & mask) {
+		pr_debug("in_width misaligned. in_width=%d\n", cfg->in_width);
+		return -1;
+	}
+
+	if ((cfg->in_width < PRP_MIN_IN_WIDTH)
+	    || (cfg->in_width > PRP_MAX_IN_WIDTH)) {
+		pr_debug("Unsupported input width %d\n", cfg->in_width);
+		return -1;
+	}
+
+	cfg->in_height &= ~1;	/* truncate to make even */
+
+	if ((cfg->in_height < PRP_MIN_IN_HEIGHT)
+	    || (cfg->in_height > PRP_MAX_IN_HEIGHT)) {
+		pr_debug("Unsupported input height %d\n", cfg->in_height);
+		return -1;
+	}
+
+	if (!(cfg->in_csi & PRP_CSI_EN))
+		if (!cfg->in_line_stride)
+			cfg->in_line_stride = cfg->in_width;
+
+	__raw_writel(cfg->in_pix, PRP_SRC_PIXEL_FORMAT_CNTL);
+	__raw_writel((cfg->in_width << 16) | cfg->in_height,
+		     PRP_SOURCE_FRAME_SIZE);
+	__raw_writel((cfg->in_line_skip << 16) | cfg->in_line_stride,
+		     PRP_SOURCE_LINE_STRIDE);
+
+	if (!(cfg->in_csi & PRP_CSI_EN)) {
+		__raw_writel(cfg->in_ptr, PRP_SOURCE_Y_PTR);
+		if (cfg->in_pix == PRP_PIXIN_YUV420) {
+			unsigned int size;
+
+			size = cfg->in_line_stride * cfg->in_height;
+			__raw_writel(cfg->in_ptr + size, PRP_SOURCE_CB_PTR);
+			__raw_writel(cfg->in_ptr + size + (size >> 2),
+				     PRP_SOURCE_CR_PTR);
+		}
+	}
+
+	/* always cropping */
+	*prp_cntl |= PRP_CNTL_WINEN;
+
+	/* color space conversion */
+	if (!cfg->in_csc[1]) {
+		if (cfg->in_csc[0] > 3) {
+			pr_debug("in_csc invalid 0x%X\n", cfg->in_csc[0]);
+			return -1;
+		}
+		if ((cfg->in_pix == PRP_PIXIN_RGB565)
+		    || (cfg->in_pix == PRP_PIXIN_RGB888))
+			cfg->in_csc[1] = 1;
+		else
+			cfg->in_csc[0] = 0;
+		csc_tbl(cfg->in_csc);
+	}
+
+	__raw_writel((cfg->in_csc[0] << 21) | (cfg->in_csc[1] << 11)
+		     | cfg->in_csc[2], PRP_CSC_COEF_012);
+	__raw_writel((cfg->in_csc[3] << 21) | (cfg->in_csc[4] << 11)
+		     | cfg->in_csc[5], PRP_CSC_COEF_345);
+	__raw_writel((cfg->in_csc[6] << 21) | (cfg->in_csc[7] << 11)
+		     | cfg->in_csc[8] | (cfg->in_csc[9] << 31),
+		     PRP_CSC_COEF_678);
+
+	if (cfg->in_csi & PRP_CSI_EN) {
+		*prp_cntl |= PRP_CNTL_CSI;
+
+		/* loop mode enable, ch1 ch2 together */
+		if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP)
+			*prp_cntl |= (PRP_CNTL_CH1_LOOP | PRP_CNTL_CH2_LOOP);
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Setup PrP registers relevant to channel 2.
+ * @param cfg		Pointer to PrP configuration parameter
+ * @param prp_cntl	Holds the value for PrP control register
+ * @return		Zero on success, others on failure
+ */
+static int prphw_ch2_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl)
+{
+	switch (cfg->ch2_pix) {
+	case PRP_PIX2_YUV420:
+		*prp_cntl |= PRP_CNTL_CH2_YUV420;
+		break;
+	case PRP_PIX2_YUV422:
+		*prp_cntl |= PRP_CNTL_CH2_YUV422;
+		break;
+	case PRP_PIX2_YUV444:
+		*prp_cntl |= PRP_CNTL_CH2_YUV444;
+		break;
+	case PRP_PIX2_UNUSED:
+		return 0;
+	default:
+		pr_debug("Unsupported channel 2 pix format 0x%08X\n",
+			 cfg->ch2_pix);
+		return -1;
+	}
+
+	if (cfg->ch2_pix == PRP_PIX2_YUV420) {
+		cfg->ch2_height &= ~1;	/* ensure U/V presence */
+		cfg->ch2_width &= ~7;	/* ensure U/V word aligned */
+	} else if (cfg->ch2_pix == PRP_PIX2_YUV422) {
+		cfg->ch2_width &= ~1;	/* word aligned */
+	}
+
+	__raw_writel((cfg->ch2_width << 16) | cfg->ch2_height,
+		     PRP_CH2_OUT_IMAGE_SIZE);
+
+	if (cfg->ch2_pix == PRP_PIX2_YUV420) {
+		u32 size;
+
+		/* Luminanance band start address */
+		__raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR);
+
+		if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) {
+			if (!cfg->ch2_ptr2)
+				__raw_writel(cfg->ch2_ptr, PRP_SOURCE_Y_PTR);
+			else
+				__raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR);
+		}
+
+		/* Cb and Cr band start address */
+		size = cfg->ch2_width * cfg->ch2_height;
+		__raw_writel(cfg->ch2_ptr + size, PRP_DEST_CB_PTR);
+		__raw_writel(cfg->ch2_ptr + size + (size >> 2),
+			     PRP_DEST_CR_PTR);
+
+		if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) {
+			if (!cfg->ch2_ptr2) {
+				__raw_writel(cfg->ch2_ptr + size,
+					     PRP_SOURCE_CB_PTR);
+				__raw_writel(cfg->ch2_ptr + size + (size >> 2),
+					     PRP_SOURCE_CR_PTR);
+			} else {
+				__raw_writel(cfg->ch2_ptr2 + size,
+					     PRP_SOURCE_CB_PTR);
+				__raw_writel(cfg->ch2_ptr2 + size + (size >> 2),
+					     PRP_SOURCE_CR_PTR);
+			}
+		}
+	} else {		/* Pixel interleaved YUV422 or YUV444 */
+		__raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR);
+
+		if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) {
+			if (!cfg->ch2_ptr2)
+				__raw_writel(cfg->ch2_ptr, PRP_SOURCE_Y_PTR);
+			else
+				__raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR);
+		}
+	}
+	*prp_cntl |= PRP_CNTL_CH2B1 | PRP_CNTL_CH2B2;
+
+	return 0;
+}
+
+/*!
+ * @brief Setup PrP registers relevant to channel 1.
+ * @param cfg		Pointer to PrP configuration parameter
+ * @param prp_cntl	Holds the value for PrP control register
+ * @return		Zero on success, others on failure
+ */
+static int prphw_ch1_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl)
+{
+	int ch1_bpp = 0;
+
+	switch (cfg->ch1_pix) {
+	case PRP_PIX1_RGB332:
+		*prp_cntl |= PRP_CNTL_CH1_RGB8;
+		ch1_bpp = 1;
+		break;
+	case PRP_PIX1_RGB565:
+		*prp_cntl |= PRP_CNTL_CH1_RGB16;
+		ch1_bpp = 2;
+		break;
+	case PRP_PIX1_RGB888:
+		*prp_cntl |= PRP_CNTL_CH1_RGB32;
+		ch1_bpp = 4;
+		break;
+	case PRP_PIX1_YUYV:
+	case PRP_PIX1_YVYU:
+	case PRP_PIX1_UYVY:
+	case PRP_PIX1_VYUY:
+		*prp_cntl |= PRP_CNTL_CH1_YUV422;
+		ch1_bpp = 2;
+		break;
+	case PRP_PIX1_UNUSED:
+		return 0;
+	default:
+		pr_debug("Unsupported channel 1 pix format 0x%08X\n",
+			 cfg->ch1_pix);
+		return -1;
+	}
+
+	/* parallel or cascade resize */
+	if (cfg->ch1_scale.algo & PRP_ALGO_BYPASS)
+		*prp_cntl |= PRP_CNTL_UNCHAIN;
+
+	/* word align */
+	if (ch1_bpp == 2)
+		cfg->ch1_width &= ~1;
+	else if (ch1_bpp == 1)
+		cfg->ch1_width &= ~3;
+
+	if (!cfg->ch1_stride)
+		cfg->ch1_stride = cfg->ch1_width;
+
+	__raw_writel(cfg->ch1_pix, PRP_CH1_PIXEL_FORMAT_CNTL);
+	__raw_writel((cfg->ch1_width << 16) | cfg->ch1_height,
+		     PRP_CH1_OUT_IMAGE_SIZE);
+	__raw_writel(cfg->ch1_stride * ch1_bpp, PRP_CH1_LINE_STRIDE);
+	__raw_writel(cfg->ch1_ptr, PRP_DEST_RGB1_PTR);
+
+	/* double buffer for loop mode */
+	if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) {
+		if (cfg->ch1_ptr2)
+			__raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR);
+		else
+			__raw_writel(cfg->ch1_ptr, PRP_DEST_RGB2_PTR);
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Setup PrP registers.
+ * @param cfg	Pointer to PrP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+int prphw_cfg(emma_prp_cfg * cfg)
+{
+	unsigned long prp_cntl = 0;
+	unsigned long val;
+
+	/* input pixel format checking */
+	if (prphw_input_cfg(cfg, &prp_cntl))
+		return -1;
+
+	if (prphw_ch2_cfg(cfg, &prp_cntl))
+		return -1;
+
+	if (prphw_ch1_cfg(cfg, &prp_cntl))
+		return -1;
+
+	/* register setting */
+	__raw_writel(prp_cntl, PRP_CNTL);
+
+	/* interrupt configuration */
+	val = PRP_INTRCNTL_RDERR | PRP_INTRCNTL_LBOVF;
+	if (cfg->ch1_pix != PRP_PIX1_UNUSED)
+		val |= PRP_INTRCNTL_CH1FC | PRP_INTRCNTL_CH1WERR;
+	if (cfg->ch2_pix != PRP_PIX2_UNUSED)
+		val |=
+		    PRP_INTRCNTL_CH2FC | PRP_INTRCNTL_CH2WERR |
+		    PRP_INTRCNTL_CH2OVF;
+	__raw_writel(val, PRP_INTRCNTL);
+
+	prp_set_scaler(1, 0, &cfg->scale[0]);	/* Channel 1 width */
+	prp_set_scaler(1, 1, &cfg->scale[1]);	/* Channel 1 height */
+	prp_set_scaler(0, 0, &cfg->scale[2]);	/* Channel 2 width */
+	prp_set_scaler(0, 1, &cfg->scale[3]);	/* Channel 2 height */
+
+	return 0;
+}
+
+/*!
+ * @brief Check PrP interrupt status.
+ * @return	PrP interrupt status
+ */
+int prphw_isr(void)
+{
+	int status;
+
+	status = __raw_readl(PRP_INTRSTATUS) & 0x1FF;
+
+	if (status & (PRP_INTRSTAT_RDERR | PRP_INTRSTAT_CH1WERR |
+		      PRP_INTRSTAT_CH2WERR))
+		pr_debug("isr bus error. status= 0x%08X\n", status);
+	else if (status & PRP_INTRSTAT_CH2OVF)
+		pr_debug("isr ch 2 buffer overflow. status= 0x%08X\n", status);
+	else if (status & PRP_INTRSTAT_LBOVF)
+		pr_debug("isr line buffer overflow. status= 0x%08X\n", status);
+
+	/* silicon bug?? enable bit does not self clear? */
+	if (!(__raw_readl(PRP_CNTL) & PRP_CNTL_CH1_LOOP))
+		__raw_writel(__raw_readl(PRP_CNTL) & (~PRP_CNTL_CH1EN),
+			     PRP_CNTL);
+	if (!(__raw_readl(PRP_CNTL) & PRP_CNTL_CH2_LOOP))
+		__raw_writel(__raw_readl(PRP_CNTL) & (~PRP_CNTL_CH2EN),
+			     PRP_CNTL);
+
+	__raw_writel(status, PRP_INTRSTATUS);	/* clr irq */
+
+	return status;
+}
+
+static struct clk *emma_clk;
+
+/*!
+ * @brief  PrP module clock enable
+ */
+void prphw_init(void)
+{
+	emma_clk = clk_get(NULL, "emma_clk");
+	clk_enable(emma_clk);
+}
+
+/*!
+ * @brief PrP module clock disable
+ */
+void prphw_exit(void)
+{
+	clk_disable(emma_clk);
+	clk_put(emma_clk);
+}
diff --git a/drivers/media/video/mxc/capture/mx27_prpsw.c b/drivers/media/video/mxc/capture/mx27_prpsw.c
new file mode 100644
index 000000000000..eca200a580f2
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mx27_prpsw.c
@@ -0,0 +1,1042 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_prpsw.c
+ *
+ * @brief MX27 Video For Linux 2 capture driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/fb.h>
+#include <linux/pci.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "mxc_v4l2_capture.h"
+#include "mx27_prp.h"
+#include "mx27_csi.h"
+#include "../drivers/video/mxc/mx2fb.h"
+#include "../opl/opl.h"
+
+#define MEAN_COEF	(SZ_COEF >> 1)
+
+static char prp_dev[] = "emma_prp";
+static int g_still_on = 0;
+static emma_prp_cfg g_prp_cfg;
+static int g_vfbuf, g_rotbuf;
+static struct tasklet_struct prp_vf_tasklet;
+
+/*
+ * The following variables represents the virtual address for the cacheable
+ * buffers accessed by SW rotation/mirroring. The rotation/mirroring in
+ * cacheable buffers has significant performance improvement than it in
+ * non-cacheable buffers.
+ */
+static char *g_vaddr_vfbuf[2] = { 0, 0 };
+static char *g_vaddr_rotbuf[2] = { 0, 0 };
+static char *g_vaddr_fb = 0;
+
+static int set_ch1_addr(emma_prp_cfg * cfg, cam_data * cam);
+static int prp_v4l2_cfg(emma_prp_cfg * cfg, cam_data * cam);
+static int prp_vf_mem_alloc(cam_data * cam);
+static void prp_vf_mem_free(cam_data * cam);
+static int prp_rot_mem_alloc(cam_data * cam);
+static void prp_rot_mem_free(cam_data * cam);
+static int prp_enc_update_eba(u32 eba, int *buffer_num);
+static int prp_enc_enable(void *private);
+static int prp_enc_disable(void *private);
+static int prp_vf_start(void *private);
+static int prp_vf_stop(void *private);
+static int prp_still_start(void *private);
+static int prp_still_stop(void *private);
+static irqreturn_t prp_isr(int irq, void *dev_id);
+static void rotation(unsigned long private);
+static int prp_resize_check_ch1(emma_prp_cfg * cfg);
+static int prp_resize_check_ch2(emma_prp_cfg * cfg);
+
+#define PRP_DUMP(val)	pr_debug("%s\t = 0x%08X\t%d\n", #val, val, val)
+
+/*!
+ * @brief Dump PrP configuration parameters.
+ * @param cfg	The pointer to PrP configuration parameter
+ */
+static void prp_cfg_dump(emma_prp_cfg * cfg)
+{
+	PRP_DUMP(cfg->in_pix);
+	PRP_DUMP(cfg->in_width);
+	PRP_DUMP(cfg->in_height);
+	PRP_DUMP(cfg->in_csi);
+	PRP_DUMP(cfg->in_line_stride);
+	PRP_DUMP(cfg->in_line_skip);
+	PRP_DUMP(cfg->in_ptr);
+
+	PRP_DUMP(cfg->ch1_pix);
+	PRP_DUMP(cfg->ch1_width);
+	PRP_DUMP(cfg->ch1_height);
+	PRP_DUMP(cfg->ch1_scale.algo);
+	PRP_DUMP(cfg->ch1_scale.width.num);
+	PRP_DUMP(cfg->ch1_scale.width.den);
+	PRP_DUMP(cfg->ch1_scale.height.num);
+	PRP_DUMP(cfg->ch1_scale.height.den);
+	PRP_DUMP(cfg->ch1_stride);
+	PRP_DUMP(cfg->ch1_ptr);
+	PRP_DUMP(cfg->ch1_ptr2);
+	PRP_DUMP(cfg->ch1_csi);
+
+	PRP_DUMP(cfg->ch2_pix);
+	PRP_DUMP(cfg->ch2_width);
+	PRP_DUMP(cfg->ch2_height);
+	PRP_DUMP(cfg->ch2_scale.algo);
+	PRP_DUMP(cfg->ch2_scale.width.num);
+	PRP_DUMP(cfg->ch2_scale.width.den);
+	PRP_DUMP(cfg->ch2_scale.height.num);
+	PRP_DUMP(cfg->ch2_scale.height.den);
+	PRP_DUMP(cfg->ch2_ptr);
+	PRP_DUMP(cfg->ch2_ptr2);
+	PRP_DUMP(cfg->ch2_csi);
+}
+
+/*!
+ * @brief Set PrP channel 1 output address.
+ * @param cfg	Pointer to emma_prp_cfg structure
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static int set_ch1_addr(emma_prp_cfg * cfg, cam_data * cam)
+{
+	if (cam->rotation != V4L2_MXC_ROTATE_NONE) {
+		cfg->ch1_ptr = (unsigned int)cam->rot_vf_bufs[0];
+		cfg->ch1_ptr2 = (unsigned int)cam->rot_vf_bufs[1];
+		if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT))
+			cfg->ch1_stride = cam->win.w.height;
+		else
+			cfg->ch1_stride = cam->win.w.width;
+
+		if (cam->v4l2_fb.flags != V4L2_FBUF_FLAG_OVERLAY) {
+			struct fb_info *fb = cam->overlay_fb;
+			if (!fb)
+				return -1;
+			if (g_vaddr_fb)
+				iounmap(g_vaddr_fb);
+			g_vaddr_fb = ioremap_cached(fb->fix.smem_start,
+						    fb->fix.smem_len);
+			if (!g_vaddr_fb)
+				return -1;
+		}
+	} else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		cfg->ch1_ptr = (unsigned int)cam->vf_bufs[0];
+		cfg->ch1_ptr2 = (unsigned int)cam->vf_bufs[1];
+		cfg->ch1_stride = cam->win.w.width;
+	} else {
+		struct fb_info *fb = cam->overlay_fb;
+
+		if (!fb)
+			return -1;
+
+		cfg->ch1_ptr = fb->fix.smem_start;
+		cfg->ch1_ptr += cam->win.w.top * fb->var.xres_virtual
+		    * (fb->var.bits_per_pixel >> 3)
+		    + cam->win.w.left * (fb->var.bits_per_pixel >> 3);
+		cfg->ch1_ptr2 = cfg->ch1_ptr;
+		cfg->ch1_stride = fb->var.xres_virtual;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Setup PrP configuration parameters.
+ * @param cfg	Pointer to emma_prp_cfg structure
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static int prp_v4l2_cfg(emma_prp_cfg * cfg, cam_data * cam)
+{
+	cfg->in_pix = PRP_PIXIN_YUYV;
+	cfg->in_width = cam->crop_current.width;
+	cfg->in_height = cam->crop_current.height;
+	cfg->in_line_stride = cam->crop_current.left;
+	cfg->in_line_skip = cam->crop_current.top;
+	cfg->in_ptr = 0;
+	cfg->in_csi = PRP_CSI_LOOP;
+	memset(cfg->in_csc, 0, sizeof(cfg->in_csc));
+
+	if (cam->overlay_on) {
+		/* Convert V4L2 pixel format to PrP pixel format */
+		switch (cam->v4l2_fb.fmt.pixelformat) {
+		case V4L2_PIX_FMT_RGB332:
+			cfg->ch1_pix = PRP_PIX1_RGB332;
+			break;
+		case V4L2_PIX_FMT_RGB32:
+		case V4L2_PIX_FMT_BGR32:
+			cfg->ch1_pix = PRP_PIX1_RGB888;
+			break;
+		case V4L2_PIX_FMT_YUYV:
+			cfg->ch1_pix = PRP_PIX1_YUYV;
+			break;
+		case V4L2_PIX_FMT_UYVY:
+			cfg->ch1_pix = PRP_PIX1_UYVY;
+			break;
+		case V4L2_PIX_FMT_RGB565:
+		default:
+			cfg->ch1_pix = PRP_PIX1_RGB565;
+			break;
+		}
+		if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP)
+		    || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) {
+			cfg->ch1_width = cam->win.w.height;
+			cfg->ch1_height = cam->win.w.width;
+		} else {
+			cfg->ch1_width = cam->win.w.width;
+			cfg->ch1_height = cam->win.w.height;
+		}
+
+		if (set_ch1_addr(cfg, cam))
+			return -1;
+	} else {
+		cfg->ch1_pix = PRP_PIX1_UNUSED;
+		cfg->ch1_width = cfg->in_width;
+		cfg->ch1_height = cfg->in_height;
+	}
+	cfg->ch1_scale.algo = 0;
+	cfg->ch1_scale.width.num = cfg->in_width;
+	cfg->ch1_scale.width.den = cfg->ch1_width;
+	cfg->ch1_scale.height.num = cfg->in_height;
+	cfg->ch1_scale.height.den = cfg->ch1_height;
+	cfg->ch1_csi = PRP_CSI_EN;
+
+	if (cam->capture_on || g_still_on) {
+		switch (cam->v2f.fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_YUYV:
+			cfg->ch2_pix = PRP_PIX2_YUV422;
+			break;
+		case V4L2_PIX_FMT_YUV420:
+			cfg->ch2_pix = PRP_PIX2_YUV420;
+			break;
+			/*
+			 * YUV444 is not defined by V4L2.
+			 * We support it in default case.
+			 */
+		default:
+			cfg->ch2_pix = PRP_PIX2_YUV444;
+			break;
+		}
+		cfg->ch2_width = cam->v2f.fmt.pix.width;
+		cfg->ch2_height = cam->v2f.fmt.pix.height;
+	} else {
+		cfg->ch2_pix = PRP_PIX2_UNUSED;
+		cfg->ch2_width = cfg->in_width;
+		cfg->ch2_height = cfg->in_height;
+	}
+	cfg->ch2_scale.algo = 0;
+	cfg->ch2_scale.width.num = cfg->in_width;
+	cfg->ch2_scale.width.den = cfg->ch2_width;
+	cfg->ch2_scale.height.num = cfg->in_height;
+	cfg->ch2_scale.height.den = cfg->ch2_height;
+	cfg->ch2_csi = PRP_CSI_EN;
+
+	memset(cfg->scale, 0, sizeof(cfg->scale));
+	cfg->scale[0].algo = cfg->ch1_scale.algo & 3;
+	cfg->scale[1].algo = (cfg->ch1_scale.algo >> 2) & 3;
+	cfg->scale[2].algo = cfg->ch2_scale.algo & 3;
+	cfg->scale[3].algo = (cfg->ch2_scale.algo >> 2) & 3;
+
+	prp_cfg_dump(cfg);
+
+	if (prp_resize_check_ch2(cfg))
+		return -1;
+
+	if (prp_resize_check_ch1(cfg))
+		return -1;
+
+	return 0;
+}
+
+/*!
+ * @brief PrP interrupt handler
+ */
+static irqreturn_t prp_isr(int irq, void *dev_id)
+{
+	int status;
+	cam_data *cam = (cam_data *) dev_id;
+
+	status = prphw_isr();
+
+	if (g_still_on && (status & PRP_INTRSTAT_CH2BUF1)) {
+		prp_still_stop(cam);
+		cam->still_counter++;
+		wake_up_interruptible(&cam->still_queue);
+		/*
+		 * Still & video capture use the same PrP channel 2.
+		 * They are execlusive.
+		 */
+	} else if (cam->capture_on) {
+		if (status & (PRP_INTRSTAT_CH2BUF1 | PRP_INTRSTAT_CH2BUF2)) {
+			cam->enc_callback(0, cam);
+		}
+	}
+	if (cam->overlay_on
+	    && (status & (PRP_INTRSTAT_CH1BUF1 | PRP_INTRSTAT_CH1BUF2))) {
+		if (cam->rotation != V4L2_MXC_ROTATE_NONE) {
+			g_rotbuf = (status & PRP_INTRSTAT_CH1BUF1) ? 0 : 1;
+			tasklet_schedule(&prp_vf_tasklet);
+		} else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+			struct fb_gwinfo gwinfo;
+
+			gwinfo.enabled = 1;
+			gwinfo.alpha_value = 255;
+			gwinfo.ck_enabled = 0;
+			gwinfo.xpos = cam->win.w.left;
+			gwinfo.ypos = cam->win.w.top;
+			gwinfo.xres = cam->win.w.width;
+			gwinfo.yres = cam->win.w.height;
+			gwinfo.xres_virtual = cam->win.w.width;
+			gwinfo.vs_reversed = 0;
+			if (status & PRP_INTRSTAT_CH1BUF1)
+				gwinfo.base = (unsigned long)cam->vf_bufs[0];
+			else
+				gwinfo.base = (unsigned long)cam->vf_bufs[1];
+
+			mx2_gw_set(&gwinfo);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * @brief PrP initialization.
+ * @param dev_id	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_init(void *dev_id)
+{
+	enable_irq(MXC_INT_EMMAPRP);
+	if (request_irq(MXC_INT_EMMAPRP, prp_isr, 0, prp_dev, dev_id))
+		return -1;
+	prphw_init();
+
+	return 0;
+}
+
+/*!
+ * @brief PrP initialization.
+ * @param dev_id	Pointer to cam_data structure
+ */
+void prp_exit(void *dev_id)
+{
+	prphw_exit();
+	disable_irq(MXC_INT_EMMAPRP);
+	free_irq(MXC_INT_EMMAPRP, dev_id);
+}
+
+/*!
+ * @brief Update PrP channel 2 output buffer address.
+ * @param eba		Physical address for PrP output buffer
+ * @param buffer_num	The PrP channel 2 buffer number to be updated
+ * @return		Zero on success, others on failure
+ */
+static int prp_enc_update_eba(u32 eba, int *buffer_num)
+{
+	if (*buffer_num) {
+		g_prp_cfg.ch2_ptr2 = eba;
+		prphw_ch2ptr2(&g_prp_cfg);
+		*buffer_num = 0;
+	} else {
+		g_prp_cfg.ch2_ptr = eba;
+		prphw_ch2ptr(&g_prp_cfg);
+		*buffer_num = 1;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Enable PrP for encoding.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_enc_enable(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (prp_v4l2_cfg(&g_prp_cfg, cam))
+		return -1;
+
+	csi_enable_mclk(CSI_MCLK_ENC, true, true);
+	prphw_reset();
+
+	if (prphw_cfg(&g_prp_cfg))
+		return -1;
+
+	prphw_enable(cam->overlay_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2)
+		     : PRP_CHANNEL_2);
+
+	return 0;
+}
+
+/*!
+ * @brief Disable PrP for encoding.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_enc_disable(void *private)
+{
+	prphw_disable(PRP_CHANNEL_2);
+	csi_enable_mclk(CSI_MCLK_ENC, false, false);
+
+	return 0;
+}
+
+/*!
+ * @brief Setup encoding functions.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_enc_select(void *private)
+{
+	int ret = 0;
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->enc_update_eba = prp_enc_update_eba;
+		cam->enc_enable = prp_enc_enable;
+		cam->enc_disable = prp_enc_disable;
+	} else
+		ret = -EIO;
+
+	return ret;
+}
+
+/*!
+ * @brief Uninstall encoding functions.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_enc_deselect(void *private)
+{
+	int ret = 0;
+	cam_data *cam = (cam_data *) private;
+
+	ret = prp_enc_disable(private);
+
+	if (cam) {
+		cam->enc_update_eba = NULL;
+		cam->enc_enable = NULL;
+		cam->enc_disable = NULL;
+	}
+
+	return ret;
+}
+
+/*!
+ * @brief Allocate memory for overlay.
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static int prp_vf_mem_alloc(cam_data * cam)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		cam->vf_bufs_size[i] = cam->win.w.width * cam->win.w.height * 2;
+		cam->vf_bufs_vaddr[i] = dma_alloc_coherent(0,
+							   cam->vf_bufs_size[i],
+							   &cam->vf_bufs[i],
+							   GFP_DMA |
+							   GFP_KERNEL);
+		if (!cam->vf_bufs_vaddr[i]) {
+			pr_debug("Failed to alloc memory for vf.\n");
+			prp_vf_mem_free(cam);
+			return -1;
+		}
+
+		g_vaddr_vfbuf[i] =
+		    ioremap_cached(cam->vf_bufs[i], cam->vf_bufs_size[i]);
+		if (!g_vaddr_vfbuf[i]) {
+			pr_debug("Failed to ioremap_cached() for vf.\n");
+			prp_vf_mem_free(cam);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Free memory for overlay.
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static void prp_vf_mem_free(cam_data * cam)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		if (cam->vf_bufs_vaddr[i]) {
+			dma_free_coherent(0,
+					  cam->vf_bufs_size[i],
+					  cam->vf_bufs_vaddr[i],
+					  cam->vf_bufs[i]);
+		}
+		cam->vf_bufs[i] = 0;
+		cam->vf_bufs_vaddr[i] = 0;
+		cam->vf_bufs_size[i] = 0;
+		if (g_vaddr_vfbuf[i]) {
+			iounmap(g_vaddr_vfbuf[i]);
+			g_vaddr_vfbuf[i] = 0;
+		}
+	}
+}
+
+/*!
+ * @brief Allocate intermediate memory for overlay rotation/mirroring.
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static int prp_rot_mem_alloc(cam_data * cam)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		cam->rot_vf_buf_size[i] =
+		    cam->win.w.width * cam->win.w.height * 2;
+		cam->rot_vf_bufs_vaddr[i] =
+		    dma_alloc_coherent(0, cam->rot_vf_buf_size[i],
+				       &cam->rot_vf_bufs[i],
+				       GFP_DMA | GFP_KERNEL);
+		if (!cam->rot_vf_bufs_vaddr[i]) {
+			pr_debug("Failed to alloc memory for vf rotation.\n");
+			prp_rot_mem_free(cam);
+			return -1;
+		}
+
+		g_vaddr_rotbuf[i] =
+		    ioremap_cached(cam->rot_vf_bufs[i],
+				   cam->rot_vf_buf_size[i]);
+		if (!g_vaddr_rotbuf[i]) {
+			pr_debug
+			    ("Failed to ioremap_cached() for rotation buffer.\n");
+			prp_rot_mem_free(cam);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Free intermedaite memory for overlay rotation/mirroring.
+ * @param cam	Pointer to cam_data structure
+ * @return	Zero on success, others on failure
+ */
+static void prp_rot_mem_free(cam_data * cam)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		if (cam->rot_vf_bufs_vaddr[i]) {
+			dma_free_coherent(0,
+					  cam->rot_vf_buf_size[i],
+					  cam->rot_vf_bufs_vaddr[i],
+					  cam->rot_vf_bufs[i]);
+		}
+		cam->rot_vf_bufs[i] = 0;
+		cam->rot_vf_bufs_vaddr[i] = 0;
+		cam->rot_vf_buf_size[i] = 0;
+		if (g_vaddr_rotbuf[i]) {
+			iounmap(g_vaddr_rotbuf[i]);
+			g_vaddr_rotbuf[i] = 0;
+		}
+	}
+}
+
+/*!
+ * @brief Start overlay (view finder).
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_vf_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		prp_vf_mem_free(cam);
+		if (prp_vf_mem_alloc(cam)) {
+			pr_info("Error to allocate vf buffer\n");
+			return -ENOMEM;
+		}
+	}
+
+	if (cam->rotation != V4L2_MXC_ROTATE_NONE) {
+		prp_rot_mem_free(cam);
+		if (prp_rot_mem_alloc(cam)) {
+			pr_info("Error to allocate rotation buffer\n");
+			prp_vf_mem_free(cam);
+			return -ENOMEM;
+		}
+	}
+
+	if (prp_v4l2_cfg(&g_prp_cfg, cam)) {
+		prp_vf_mem_free(cam);
+		prp_rot_mem_free(cam);
+		return -1;
+	}
+
+	csi_enable_mclk(CSI_MCLK_VF, true, true);
+	prphw_reset();
+
+	if (prphw_cfg(&g_prp_cfg)) {
+		prp_vf_mem_free(cam);
+		prp_rot_mem_free(cam);
+		return -1;
+	}
+	g_vfbuf = g_rotbuf = 0;
+	tasklet_init(&prp_vf_tasklet, rotation, (unsigned long)private);
+
+	prphw_enable(cam->capture_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2)
+		     : PRP_CHANNEL_1);
+
+	return 0;
+}
+
+/*!
+ * @brief Stop overlay (view finder).
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_vf_stop(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	prphw_disable(PRP_CHANNEL_1);
+
+	csi_enable_mclk(CSI_MCLK_VF, false, false);
+	tasklet_kill(&prp_vf_tasklet);
+
+	if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		struct fb_gwinfo gwinfo;
+
+		/* Disable graphic window */
+		gwinfo.enabled = 0;
+		mx2_gw_set(&gwinfo);
+
+		prp_vf_mem_free(cam);
+	}
+	prp_rot_mem_free(cam);
+	if (g_vaddr_fb) {
+		iounmap(g_vaddr_fb);
+		g_vaddr_fb = 0;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Setup overlay functions.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_vf_select(void *private)
+{
+	int ret = 0;
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->vf_start_sdc = prp_vf_start;
+		cam->vf_stop_sdc = prp_vf_stop;
+		cam->overlay_active = false;
+	} else
+		ret = -EIO;
+
+	return ret;
+}
+
+/*!
+ * @brief Uninstall overlay functions.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_vf_deselect(void *private)
+{
+	int ret = 0;
+	cam_data *cam = (cam_data *) private;
+
+	ret = prp_vf_stop(private);
+
+	if (cam) {
+		cam->vf_start_sdc = NULL;
+		cam->vf_stop_sdc = NULL;
+	}
+
+	return ret;
+}
+
+/*!
+ * @brief Start still picture capture.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_still_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	g_still_on = 1;
+	g_prp_cfg.ch2_ptr = (unsigned int)cam->still_buf[0];
+	g_prp_cfg.ch2_ptr2 = 0;
+
+	if (prp_v4l2_cfg(&g_prp_cfg, cam))
+		return -1;
+
+	csi_enable_mclk(CSI_MCLK_RAW, true, true);
+	prphw_reset();
+
+	if (prphw_cfg(&g_prp_cfg)) {
+		g_still_on = 0;
+		return -1;
+	}
+
+	prphw_enable(cam->overlay_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2)
+		     : PRP_CHANNEL_2);
+
+	return 0;
+}
+
+/*!
+ * @brief Stop still picture capture.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+static int prp_still_stop(void *private)
+{
+	prphw_disable(PRP_CHANNEL_2);
+
+	csi_enable_mclk(CSI_MCLK_RAW, false, false);
+
+	g_still_on = 0;
+
+	return 0;
+}
+
+/*!
+ * @brief Setup functions for still picture capture.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_still_select(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->csi_start = prp_still_start;
+		cam->csi_stop = prp_still_stop;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Uninstall functions for still picture capture.
+ * @param private	Pointer to cam_data structure
+ * @return		Zero on success, others on failure
+ */
+int prp_still_deselect(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	err = prp_still_stop(cam);
+
+	if (cam) {
+		cam->csi_start = NULL;
+		cam->csi_stop = NULL;
+	}
+
+	return err;
+}
+
+/*!
+ * @brief Perform software rotation or mirroring
+ * @param private	Argument passed to the tasklet
+ */
+static void rotation(unsigned long private)
+{
+	char *src, *dst;
+	int width, height, s_stride, d_stride;
+	int size;
+	cam_data *cam = (cam_data *) private;
+
+	src = g_vaddr_rotbuf[g_rotbuf];
+	size = cam->rot_vf_buf_size[g_rotbuf];
+
+	if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP)
+	    || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) {
+		width = cam->win.w.height;
+		height = cam->win.w.width;
+		s_stride = cam->win.w.height << 1;
+	} else {
+		width = cam->win.w.width;
+		height = cam->win.w.height;
+		s_stride = cam->win.w.width << 1;
+	}
+
+	if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		dst = g_vaddr_vfbuf[g_vfbuf];
+		d_stride = cam->win.w.width << 1;
+	} else {		/* The destination is the framebuffer */
+		struct fb_info *fb = cam->overlay_fb;
+		if (!fb)
+			return;
+		dst = g_vaddr_fb;
+		dst += cam->win.w.top * fb->var.xres_virtual
+		    * (fb->var.bits_per_pixel >> 3)
+		    + cam->win.w.left * (fb->var.bits_per_pixel >> 3);
+		d_stride = fb->var.xres_virtual << 1;
+	}
+
+	/*
+	 * Invalidate the data in cache before performing the SW rotaion
+	 * or mirroring in case the image size is less than QVGA. For image
+	 * larger than QVGA it is not invalidated becase the invalidation
+	 * will consume much time while we don't see any artifacts on the
+	 * output if we don't perform invalidation for them.
+	 * Similarly we don't flush the data after SW rotation/mirroring.
+	 */
+	if (size < 320 * 240 * 2)
+		dmac_inv_range(src, src + size);
+	switch (cam->rotation) {
+	case V4L2_MXC_ROTATE_VERT_FLIP:
+		opl_vmirror_u16(src, s_stride, width, height, dst, d_stride);
+		break;
+	case V4L2_MXC_ROTATE_HORIZ_FLIP:
+		opl_hmirror_u16(src, s_stride, width, height, dst, d_stride);
+		break;
+	case V4L2_MXC_ROTATE_180:
+		opl_rotate180_u16(src, s_stride, width, height, dst, d_stride);
+		break;
+	case V4L2_MXC_ROTATE_90_RIGHT:
+		opl_rotate90_u16(src, s_stride, width, height, dst, d_stride);
+		break;
+	case V4L2_MXC_ROTATE_90_RIGHT_VFLIP:
+		opl_rotate90_vmirror_u16(src, s_stride, width, height, dst,
+					 d_stride);
+		break;
+	case V4L2_MXC_ROTATE_90_RIGHT_HFLIP:
+		/* ROTATE_90_RIGHT_HFLIP = ROTATE_270_RIGHT_VFLIP */
+		opl_rotate270_vmirror_u16(src, s_stride, width, height, dst,
+					  d_stride);
+		break;
+	case V4L2_MXC_ROTATE_90_LEFT:
+		opl_rotate270_u16(src, s_stride, width, height, dst, d_stride);
+		break;
+	default:
+		return;
+	}
+
+	/* Config and display the graphic window */
+	if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		struct fb_gwinfo gwinfo;
+
+		gwinfo.enabled = 1;
+		gwinfo.alpha_value = 255;
+		gwinfo.ck_enabled = 0;
+		gwinfo.xpos = cam->win.w.left;
+		gwinfo.ypos = cam->win.w.top;
+		gwinfo.xres = cam->win.w.width;
+		gwinfo.yres = cam->win.w.height;
+		gwinfo.xres_virtual = cam->win.w.width;
+		gwinfo.vs_reversed = 0;
+		gwinfo.base = (unsigned long)cam->vf_bufs[g_vfbuf];
+		mx2_gw_set(&gwinfo);
+
+		g_vfbuf = g_vfbuf ? 0 : 1;
+	}
+}
+
+/*
+ * @brief Check if the resize ratio is supported based on the input and output
+ *        dimension
+ * @param	input	input dimension
+ * @param	output	output dimension
+ * @return	output dimension (should equal the parameter *output*)
+ * 		-1 on failure
+ */
+static int check_simple(scale_t * scale, int input, int output)
+{
+	unsigned short int_out;	/* PrP internel width or height */
+	unsigned short orig_out = output;
+
+	if (prp_scale(scale, input, output, input, &orig_out, &int_out, 0))
+		return -1;	/* resize failed */
+	else
+		return int_out;
+}
+
+/*
+ * @brief Check if the resize ratio is supported based on the input and output
+ *        dimension
+ * @param	input	input dimension
+ * @param	output	output dimension
+ * @return	output dimension, may be rounded.
+ * 		-1 on failure
+ */
+static int check_simple_retry(scale_t * scale, int input, int output)
+{
+	unsigned short int_out;	/* PrP internel width or height */
+	unsigned short orig_out = output;
+
+	if (prp_scale(scale, input, output, input, &orig_out, &int_out,
+		      SCALE_RETRY))
+		return -1;	/* resize failed */
+	else
+		return int_out;
+}
+
+/*!
+ * @brief Check if the resize ratio is supported by PrP channel 1
+ * @param cfg	Pointer to emma_prp_cfg structure
+ * @return	Zero on success, others on failure
+ */
+static int prp_resize_check_ch1(emma_prp_cfg * cfg)
+{
+	int in_w, in_h, ch1_w, ch1_h, ch2_w, ch2_h, w, h;
+	scale_t *pscale = &cfg->scale[0];	/* Ch1 width resize coeff */
+
+	if (cfg->ch1_pix == PRP_PIX1_UNUSED)
+		return 0;
+
+	in_w = cfg->in_width;
+	in_h = cfg->in_height;
+	ch1_w = cfg->ch1_width;
+	ch1_h = cfg->ch1_height;
+	ch2_w = cfg->ch2_width;
+	ch2_h = cfg->ch2_height;
+
+	/*
+	 * For channel 1, try parallel resize first. If the resize
+	 * ratio is not exactly supported, try cascade resize. If it
+	 * still fails, use parallel resize but with rounded value.
+	 */
+	w = check_simple(pscale, in_w, ch1_w);
+	h = check_simple(pscale + 1, in_h, ch1_h);
+	if ((w == ch1_w) && (h == ch1_h))
+		goto exit_parallel;
+
+	if (cfg->ch2_pix != PRP_PIX2_UNUSED) {
+		/*
+		 * Channel 2 is already used. The pscale is still pointing
+		 * to ch1 resize coeff for temporary use.
+		 */
+		w = check_simple(pscale, in_w, ch2_w);
+		h = check_simple(pscale + 1, in_h, ch2_h);
+		if ((w == ch2_w) && (h == ch2_h)) {
+			/* Try cascade resize now */
+			w = check_simple(pscale, ch2_w, ch1_w);
+			h = check_simple(pscale + 1, ch2_h, ch1_h);
+			if ((w == ch1_w) && (h == ch1_h))
+				goto exit_cascade;
+		}
+	} else {
+		/*
+		 * Try cascade resize for width, width is multiple of 2.
+		 * Channel 2 is not used. So we have more values to pick
+		 * for channel 2 resize.
+		 */
+		for (w = in_w - 2; w > ch1_w; w -= 2) {
+			/* Ch2 width resize */
+			if (check_simple(pscale + 2, in_w, w) != w)
+				continue;
+			/* Ch1 width resize */
+			if (check_simple(pscale, w, ch1_w) != ch1_w)
+				continue;
+			break;
+		}
+		if ((ch2_w = w) > ch1_w) {
+			/* try cascade resize for height */
+			for (h = in_h - 1; h > ch1_h; h--) {
+				/* Ch2 height resize */
+				if (check_simple(pscale + 3, in_h, h) != h)
+					continue;
+				/* Ch1 height resize */
+				if (check_simple(pscale + 1, h, ch1_h) != ch1_h)
+					continue;
+				break;
+			}
+			if ((ch2_h = h) > ch1_h)
+				goto exit_cascade;
+		}
+	}
+
+	/* Have to try parallel resize again and round the dimensions */
+	w = check_simple_retry(pscale, in_w, ch1_w);
+	h = check_simple_retry(pscale + 1, in_h, ch1_h);
+	if ((w != -1) && (h != -1))
+		goto exit_parallel;
+
+	pr_debug("Ch1 resize error.\n");
+	return -1;
+
+      exit_parallel:
+	cfg->ch1_scale.algo |= PRP_ALGO_BYPASS;
+	pr_debug("ch1 parallel resize.\n");
+	pr_debug("original width = %d internel width = %d\n", ch1_w, w);
+	pr_debug("original height = %d internel height = %d\n", ch1_h, h);
+	return 0;
+
+      exit_cascade:
+	cfg->ch1_scale.algo &= ~PRP_ALGO_BYPASS;
+	pr_debug("ch1 cascade resize.\n");
+	pr_debug("[width] in : ch2 : ch1=%d : %d : %d\n", in_w, ch2_w, ch1_w);
+	pr_debug("[height] in : ch2 : ch1=%d : %d : %d\n", in_h, ch2_h, ch1_h);
+	return 0;
+}
+
+/*!
+ * @brief Check if the resize ratio is supported by PrP channel 2
+ * @param cfg	Pointer to emma_prp_cfg structure
+ * @return	Zero on success, others on failure
+ */
+static int prp_resize_check_ch2(emma_prp_cfg * cfg)
+{
+	int w, h;
+	scale_t *pscale = &cfg->scale[2];	/* Ch2 width resize coeff */
+
+	if (cfg->ch2_pix == PRP_PIX2_UNUSED)
+		return 0;
+
+	w = check_simple_retry(pscale, cfg->in_width, cfg->ch2_width);
+	h = check_simple_retry(pscale + 1, cfg->in_height, cfg->ch2_height);
+	if ((w != -1) && (h != -1)) {
+		pr_debug("Ch2 resize.\n");
+		pr_debug("Original width = %d internel width = %d\n",
+			 cfg->ch2_width, w);
+		pr_debug("Original height = %d internel height = %d\n",
+			 cfg->ch2_height, h);
+		return 0;
+	} else {
+		pr_debug("Ch2 resize error.\n");
+		return -1;
+	}
+}
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
new file mode 100644
index 000000000000..f08cfe8dfcc1
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
@@ -0,0 +1,2728 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c
+ *
+ * @brief Mxc Video For Linux 2 driver
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <linux/semaphore.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <linux/mxcfb.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-int-device.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+static int video_nr = -1;
+static cam_data *g_cam;
+
+/*! This data is used for the output to the display. */
+#define MXC_V4L2_CAPTURE_NUM_OUTPUTS	3
+#define MXC_V4L2_CAPTURE_NUM_INPUTS	2
+static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = {
+	{
+	 .index = 0,
+	 .name = "DISP3 BG",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN,
+	 },
+	{
+	 .index = 1,
+	 .name = "DISP0",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN,
+	 },
+	{
+	 .index = 2,
+	 .name = "DISP3 FG",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN,
+	 },
+};
+
+static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = {
+	{
+	 .index = 0,
+	 .name = "CSI IC MEM",
+	 .type = V4L2_INPUT_TYPE_CAMERA,
+	 .audioset = 0,
+	 .tuner = 0,
+	 .std = V4L2_STD_UNKNOWN,
+	 .status = 0,
+	 },
+	{
+	 .index = 1,
+	 .name = "CSI MEM",
+	 .type = V4L2_INPUT_TYPE_CAMERA,
+	 .audioset = 0,
+	 .tuner = 0,
+	 .std = V4L2_STD_UNKNOWN,
+	 .status = V4L2_IN_ST_NO_POWER,
+	 },
+};
+
+/*! List of TV input video formats supported. The video formats is corresponding
+ * to the v4l2_id in video_fmt_t.
+ * Currently, only PAL and NTSC is supported. Needs to be expanded in the
+ * future.
+ */
+typedef enum {
+	TV_NTSC = 0,		/*!< Locked on (M) NTSC video signal. */
+	TV_PAL,			/*!< (B, G, H, I, N)PAL video signal. */
+	TV_NOT_LOCKED,		/*!< Not locked on a signal. */
+} video_fmt_idx;
+
+/*! Number of video standards supported (including 'not locked' signal). */
+#define TV_STD_MAX		(TV_NOT_LOCKED + 1)
+
+/*! Video format structure. */
+typedef struct {
+	int v4l2_id;		/*!< Video for linux ID. */
+	char name[16];		/*!< Name (e.g., "NTSC", "PAL", etc.) */
+	u16 raw_width;		/*!< Raw width. */
+	u16 raw_height;		/*!< Raw height. */
+	u16 active_width;	/*!< Active width. */
+	u16 active_height;	/*!< Active height. */
+	u16 active_top;		/*!< Active top. */
+	u16 active_left;	/*!< Active left. */
+} video_fmt_t;
+
+/*!
+ * Description of video formats supported.
+ *
+ *  PAL: raw=720x625, active=720x576.
+ *  NTSC: raw=720x525, active=720x480.
+ */
+static video_fmt_t video_fmts[] = {
+	{			/*! NTSC */
+	 .v4l2_id = V4L2_STD_NTSC,
+	 .name = "NTSC",
+	 .raw_width = 720,		/* SENS_FRM_WIDTH */
+	 .raw_height = 525,		/* SENS_FRM_HEIGHT */
+	 .active_width = 720,		/* ACT_FRM_WIDTH */
+	 .active_height = 240,		/* ACT_FRM_HEIGHT */
+	 .active_top = 0,
+	 .active_left = 0,
+	 },
+	{			/*! (B, G, H, I, N) PAL */
+	 .v4l2_id = V4L2_STD_PAL,
+	 .name = "PAL",
+	 .raw_width = 720,
+	 .raw_height = 625,
+	 .active_width = 720,
+	 .active_height = 288,
+	 .active_top = 0,
+	 .active_left = 0,
+	 },
+	{			/*! Unlocked standard */
+	 .v4l2_id = V4L2_STD_ALL,
+	 .name = "Autodetect",
+	 .raw_width = 720,
+	 .raw_height = 625,
+	 .active_width = 720,
+	 .active_height = 288,
+	 .active_top = 0,
+	 .active_left = 0,
+	 },
+};
+
+/*!* Standard index of TV. */
+static video_fmt_idx video_index = TV_NOT_LOCKED;
+
+static int mxc_v4l2_master_attach(struct v4l2_int_device *slave);
+static void mxc_v4l2_master_detach(struct v4l2_int_device *slave);
+static u8 camera_power(cam_data *cam, bool cameraOn);
+static int start_preview(cam_data *cam);
+static int stop_preview(cam_data *cam);
+
+/*! Information about this driver. */
+static struct v4l2_int_master mxc_v4l2_master = {
+	.attach = mxc_v4l2_master_attach,
+	.detach = mxc_v4l2_master_detach,
+};
+
+static struct v4l2_int_device mxc_v4l2_int_device = {
+	.module = THIS_MODULE,
+	.name = "mxc_v4l2_cap",
+	.type = v4l2_int_type_master,
+	.u = {
+		.master = &mxc_v4l2_master,
+		},
+};
+
+/***************************************************************************
+ * Functions for handling Frame buffers.
+ **************************************************************************/
+
+/*!
+ * Free frame buffers
+ *
+ * @param cam      Structure cam_data *
+ *
+ * @return status  0 success.
+ */
+static int mxc_free_frame_buf(cam_data *cam)
+{
+	int i;
+
+	pr_debug("MVC: In mxc_free_frame_buf\n");
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		if (cam->frame[i].vaddress != 0) {
+			dma_free_coherent(0, cam->frame[i].buffer.length,
+					  cam->frame[i].vaddress,
+					  cam->frame[i].paddress);
+			cam->frame[i].vaddress = 0;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * Allocate frame buffers
+ *
+ * @param cam      Structure cam_data*
+ * @param count    int number of buffer need to allocated
+ *
+ * @return status  -0 Successfully allocated a buffer, -ENOBUFS	failed.
+ */
+static int mxc_allocate_frame_buf(cam_data *cam, int count)
+{
+	int i;
+
+	pr_debug("In MVC:mxc_allocate_frame_buf - size=%d\n",
+		cam->v2f.fmt.pix.sizeimage);
+
+	for (i = 0; i < count; i++) {
+		cam->frame[i].vaddress =
+		    dma_alloc_coherent(0,
+				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				       &cam->frame[i].paddress,
+				       GFP_DMA | GFP_KERNEL);
+		if (cam->frame[i].vaddress == 0) {
+			pr_err("ERROR: v4l2 capture: "
+				"mxc_allocate_frame_buf failed.\n");
+			mxc_free_frame_buf(cam);
+			return -ENOBUFS;
+		}
+		cam->frame[i].buffer.index = i;
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+		cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cam->frame[i].buffer.length =
+		    PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
+		cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
+		cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
+		cam->frame[i].index = i;
+	}
+
+	return 0;
+}
+
+/*!
+ * Free frame buffers status
+ *
+ * @param cam    Structure cam_data *
+ *
+ * @return none
+ */
+static void mxc_free_frames(cam_data *cam)
+{
+	int i;
+
+	pr_debug("In MVC:mxc_free_frames\n");
+
+	for (i = 0; i < FRAME_NUM; i++) {
+		cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
+	}
+
+	cam->enc_counter = 0;
+	cam->skip_frame = 0;
+	INIT_LIST_HEAD(&cam->ready_q);
+	INIT_LIST_HEAD(&cam->working_q);
+	INIT_LIST_HEAD(&cam->done_q);
+}
+
+/*!
+ * Return the buffer status
+ *
+ * @param cam 	   Structure cam_data *
+ * @param buf      Structure v4l2_buffer *
+ *
+ * @return status  0 success, EINVAL failed.
+ */
+static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
+{
+	pr_debug("In MVC:mxc_v4l2_buffer_status\n");
+
+	if (buf->index < 0 || buf->index >= FRAME_NUM) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers "
+		       "not allocated\n");
+		return -EINVAL;
+	}
+
+	memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
+	return 0;
+}
+
+/***************************************************************************
+ * Functions for handling the video stream.
+ **************************************************************************/
+
+/*!
+ * Indicates whether the palette is supported.
+ *
+ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	return ((palette == V4L2_PIX_FMT_RGB565) ||
+		(palette == V4L2_PIX_FMT_BGR24) ||
+		(palette == V4L2_PIX_FMT_RGB24) ||
+		(palette == V4L2_PIX_FMT_BGR32) ||
+		(palette == V4L2_PIX_FMT_RGB32) ||
+		(palette == V4L2_PIX_FMT_YUV422P) ||
+		(palette == V4L2_PIX_FMT_UYVY) ||
+		(palette == V4L2_PIX_FMT_YUYV) ||
+		(palette == V4L2_PIX_FMT_YUV420) ||
+		(palette == V4L2_PIX_FMT_NV12));
+}
+
+/*!
+ * Start the encoder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_streamon(cam_data *cam)
+{
+	struct mxc_v4l_frame *frame;
+	int err = 0;
+
+	pr_debug("In MVC:mxc_streamon\n");
+
+	if (NULL == cam) {
+		pr_err("ERROR! cam parameter is NULL\n");
+		return -1;
+	}
+
+	if (cam->capture_on) {
+		pr_err("ERROR: v4l2 capture: Capture stream has been turned "
+		       " on\n");
+		return -1;
+	}
+
+	if (list_empty(&cam->ready_q)) {
+		pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been "
+			"queued yet\n");
+		return -EINVAL;
+	}
+
+	cam->capture_pid = current->pid;
+
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+
+	if (cam->enc_enable) {
+		err = cam->enc_enable(cam);
+		if (err != 0) {
+			return err;
+		}
+	}
+
+	cam->ping_pong_csi = 0;
+	if (cam->enc_update_eba) {
+		frame =
+		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+		list_del(cam->ready_q.next);
+		list_add_tail(&frame->queue, &cam->working_q);
+		err = cam->enc_update_eba(frame->buffer.m.offset,
+					  &cam->ping_pong_csi);
+
+		frame =
+		    list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
+		list_del(cam->ready_q.next);
+		list_add_tail(&frame->queue, &cam->working_q);
+		err |= cam->enc_update_eba(frame->buffer.m.offset,
+					   &cam->ping_pong_csi);
+	} else {
+		return -EINVAL;
+	}
+
+	if (cam->overlay_on == true)
+		start_preview(cam);
+
+	if (cam->enc_enable_csi) {
+		err = cam->enc_enable_csi(cam);
+		if (err != 0)
+			return err;
+	}
+
+	cam->capture_on = true;
+
+	return err;
+}
+
+/*!
+ * Shut down the encoder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_streamoff(cam_data *cam)
+{
+	int err = 0;
+
+	pr_debug("In MVC:mxc_streamoff\n");
+
+	if (cam->capture_on == false)
+		return 0;
+
+	if (cam->enc_disable_csi) {
+		err = cam->enc_disable_csi(cam);
+		if (err != 0)
+			return err;
+	}
+	if (cam->enc_disable)
+		err = cam->enc_disable(cam);
+
+	mxc_free_frames(cam);
+	mxc_capture_inputs[cam->current_input].status |= V4L2_IN_ST_NO_POWER;
+	cam->capture_on = false;
+	return err;
+}
+
+/*!
+ * Valid and adjust the overlay window size, position
+ *
+ * @param cam      structure cam_data *
+ * @param win      struct v4l2_window  *
+ *
+ * @return 0
+ */
+static int verify_preview(cam_data *cam, struct v4l2_window *win)
+{
+	int i = 0, width_bound = 0, height_bound = 0;
+	int *width, *height;
+	struct fb_info *bg_fbi = NULL;
+	bool foregound_fb;
+
+	pr_debug("In MVC: verify_preview\n");
+
+	do {
+		cam->overlay_fb = (struct fb_info *)registered_fb[i];
+		if (cam->overlay_fb == NULL) {
+			pr_err("ERROR: verify_preview frame buffer NULL.\n");
+			return -1;
+		}
+		if (strcmp(cam->overlay_fb->fix.id, "DISP3 BG") == 0)
+			bg_fbi = cam->overlay_fb;
+		if (strcmp(cam->overlay_fb->fix.id,
+			    mxc_capture_outputs[cam->output].name) == 0) {
+			if (strcmp(cam->overlay_fb->fix.id, "DISP3 FG") == 0)
+				foregound_fb = true;
+			break;
+		}
+	} while (++i < FB_MAX);
+
+	if (foregound_fb) {
+		width_bound = bg_fbi->var.xres;
+		height_bound = bg_fbi->var.yres;
+
+		if (win->w.width + win->w.left > bg_fbi->var.xres ||
+		    win->w.height + win->w.top > bg_fbi->var.yres) {
+			pr_err("ERROR: FG window position exceeds.\n");
+			return -1;
+		}
+	} else {
+		/* 4 bytes alignment for BG */
+		width_bound = cam->overlay_fb->var.xres;
+		height_bound = cam->overlay_fb->var.yres;
+
+		if (cam->overlay_fb->var.bits_per_pixel == 24) {
+			win->w.left -= win->w.left % 4;
+		} else if (cam->overlay_fb->var.bits_per_pixel == 16) {
+			win->w.left -= win->w.left % 2;
+		}
+
+		if (win->w.width + win->w.left > cam->overlay_fb->var.xres)
+			win->w.width = cam->overlay_fb->var.xres - win->w.left;
+		if (win->w.height + win->w.top > cam->overlay_fb->var.yres)
+			win->w.height = cam->overlay_fb->var.yres - win->w.top;
+	}
+
+	/* stride line limitation */
+	win->w.height -= win->w.height % 8;
+	win->w.width -= win->w.width % 8;
+
+	if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+		height = &win->w.width;
+		width = &win->w.height;
+	} else {
+		width = &win->w.width;
+		height = &win->w.height;
+	}
+
+	if ((cam->crop_bounds.width / *width > 8) ||
+	    ((cam->crop_bounds.width / *width == 8) &&
+	     (cam->crop_bounds.width % *width))) {
+		*width = cam->crop_bounds.width / 8;
+		if (*width % 8)
+			*width += 8 - *width % 8;
+		if (*width + win->w.left > width_bound) {
+			pr_err("ERROR: v4l2 capture: width exceeds "
+				"resize limit.\n");
+			return -1;
+		}
+		pr_err("ERROR: v4l2 capture: width exceeds limit. "
+			"Resize to %d.\n",
+			*width);
+	}
+
+	if ((cam->crop_bounds.height / *height > 8) ||
+	    ((cam->crop_bounds.height / *height == 8) &&
+	     (cam->crop_bounds.height % *height))) {
+		*height = cam->crop_bounds.height / 8;
+		if (*height % 8)
+			*height += 8 - *height % 8;
+		if (*height + win->w.top > height_bound) {
+			pr_err("ERROR: v4l2 capture: height exceeds "
+				"resize limit.\n");
+			return -1;
+		}
+		pr_err("ERROR: v4l2 capture: height exceeds limit "
+			"resize to %d.\n",
+			*height);
+	}
+
+	return 0;
+}
+
+/*!
+ * start the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int start_preview(cam_data *cam)
+{
+	int err = 0;
+
+	pr_debug("MVC: start_preview\n");
+
+#if defined(CONFIG_MXC_IPU_PRP_VF_SDC) || defined(CONFIG_MXC_IPU_PRP_VF_SDC_MODULE)
+	pr_debug("   This is an SDC display\n");
+	if (cam->output == 0 || cam->output == 2) {
+		if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
+			err = prp_vf_sdc_select(cam);
+		else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
+			err = prp_vf_sdc_select_bg(cam);
+		if (err != 0)
+			return err;
+
+		err = cam->vf_start_sdc(cam);
+		if (err != 0)
+			return err;
+
+		if (cam->vf_enable_csi)
+			err = cam->vf_enable_csi(cam);
+	}
+#endif
+
+#if defined(CONFIG_MXC_IPU_PRP_VF_ADC) || defined(CONFIG_MXC_IPU_PRP_VF_ADC_MODULE)
+	pr_debug("   This is an ADC display\n");
+	if (cam->output == 1) {
+		err = prp_vf_adc_select(cam);
+		if (err != 0)
+			return err;
+
+		err = cam->vf_start_adc(cam);
+	}
+#endif
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__,
+		 cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+	pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_bounds.width, cam->crop_bounds.height);
+	pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_defrect.width, cam->crop_defrect.height);
+	pr_debug("End of %s: crop_current widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_current.width, cam->crop_current.height);
+
+	return err;
+}
+
+/*!
+ * shut down the viewfinder job
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static int stop_preview(cam_data *cam)
+{
+	int err = 0;
+
+	pr_debug("MVC: stop preview\n");
+
+#if defined(CONFIG_MXC_IPU_PRP_VF_ADC) || defined(CONFIG_MXC_IPU_PRP_VF_ADC_MODULE)
+	if (cam->output == 1) {
+		err = prp_vf_adc_deselect(cam);
+	}
+#endif
+
+#if defined(CONFIG_MXC_IPU_PRP_VF_SDC) || defined(CONFIG_MXC_IPU_PRP_VF_SDC_MODULE)
+	if (cam->vf_disable_csi) {
+		err = cam->vf_disable_csi(cam);
+		if (err != 0)
+			return err;
+	}
+
+	if (cam->output == 0 || cam->output == 2) {
+		if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
+			err = prp_vf_sdc_deselect(cam);
+		else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
+			err = prp_vf_sdc_deselect_bg(cam);
+	}
+#endif
+
+	return err;
+}
+
+/***************************************************************************
+ * VIDIOC Functions.
+ **************************************************************************/
+
+/*!
+ * V4L2 - mxc_v4l2_g_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+
+	pr_debug("In MVC: mxc_v4l2_g_fmt type=%d\n", f->type);
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		f->fmt.pix = cam->v2f.fmt.pix;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
+		f->fmt.win = cam->win;
+		break;
+	default:
+		pr_debug("   type is invalid\n");
+		retval = -EINVAL;
+	}
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__,
+		 cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+	pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_bounds.width, cam->crop_bounds.height);
+	pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_defrect.width, cam->crop_defrect.height);
+	pr_debug("End of %s: crop_current widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_current.width, cam->crop_current.height);
+
+	return retval;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_s_fmt function
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param f           structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
+{
+	int retval = 0;
+	int size = 0;
+	int bytesperline = 0;
+	int *width, *height;
+
+	pr_debug("In MVC: mxc_v4l2_s_fmt\n");
+
+	switch (f->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		if (!valid_mode(f->fmt.pix.pixelformat)) {
+			pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format "
+			       "not supported\n");
+			return -EINVAL;
+		}
+
+		/*
+		 * Force the capture window resolution to be crop bounds
+		 * for CSI MEM input mode.
+		 */
+		if (strcmp(mxc_capture_inputs[cam->current_input].name,
+			   "CSI MEM") == 0) {
+			f->fmt.pix.width = cam->crop_current.width;
+			f->fmt.pix.height = cam->crop_current.height;
+		}
+
+		if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
+			height = &f->fmt.pix.width;
+			width = &f->fmt.pix.height;
+		} else {
+			width = &f->fmt.pix.width;
+			height = &f->fmt.pix.height;
+		}
+
+		/* stride line limitation */
+		*width -= *width % 8;
+		*height -= *height % 8;
+
+		if ((cam->crop_current.width / *width > 8) ||
+		    ((cam->crop_current.width / *width == 8) &&
+		     (cam->crop_current.width % *width))) {
+			*width = cam->crop_current.width / 8;
+			if (*width % 8)
+				*width += 8 - *width % 8;
+			pr_err("ERROR: v4l2 capture: width exceeds limit "
+				"resize to %d.\n",
+			       *width);
+		}
+
+		if ((cam->crop_current.height / *height > 8) ||
+		    ((cam->crop_current.height / *height == 8) &&
+		     (cam->crop_current.height % *height))) {
+			*height = cam->crop_current.height / 8;
+			if (*height % 8)
+				*height += 8 - *height % 8;
+			pr_err("ERROR: v4l2 capture: height exceeds limit "
+			       "resize to %d.\n",
+			       *height);
+		}
+
+		switch (f->fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_RGB565:
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			bytesperline = f->fmt.pix.width * 2;
+			break;
+		case V4L2_PIX_FMT_BGR24:
+			size = f->fmt.pix.width * f->fmt.pix.height * 3;
+			bytesperline = f->fmt.pix.width * 3;
+			break;
+		case V4L2_PIX_FMT_RGB24:
+			size = f->fmt.pix.width * f->fmt.pix.height * 3;
+			bytesperline = f->fmt.pix.width * 3;
+			break;
+		case V4L2_PIX_FMT_BGR32:
+			size = f->fmt.pix.width * f->fmt.pix.height * 4;
+			bytesperline = f->fmt.pix.width * 4;
+			break;
+		case V4L2_PIX_FMT_RGB32:
+			size = f->fmt.pix.width * f->fmt.pix.height * 4;
+			bytesperline = f->fmt.pix.width * 4;
+			break;
+		case V4L2_PIX_FMT_YUV422P:
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			bytesperline = f->fmt.pix.width;
+			break;
+		case V4L2_PIX_FMT_UYVY:
+		case V4L2_PIX_FMT_YUYV:
+			size = f->fmt.pix.width * f->fmt.pix.height * 2;
+			bytesperline = f->fmt.pix.width * 2;
+			break;
+		case V4L2_PIX_FMT_YUV420:
+			size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
+			bytesperline = f->fmt.pix.width;
+			break;
+		case V4L2_PIX_FMT_NV12:
+			size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
+			bytesperline = f->fmt.pix.width;
+			break;
+		default:
+			break;
+		}
+
+		if (f->fmt.pix.bytesperline < bytesperline) {
+			f->fmt.pix.bytesperline = bytesperline;
+		} else {
+			bytesperline = f->fmt.pix.bytesperline;
+		}
+
+		if (f->fmt.pix.sizeimage < size) {
+			f->fmt.pix.sizeimage = size;
+		} else {
+			size = f->fmt.pix.sizeimage;
+		}
+
+		cam->v2f.fmt.pix = f->fmt.pix;
+
+		if (cam->v2f.fmt.pix.priv != 0) {
+			if (copy_from_user(&cam->offset,
+					   (void *)cam->v2f.fmt.pix.priv,
+					   sizeof(cam->offset))) {
+				retval = -EFAULT;
+				break;
+			}
+		}
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		pr_debug("   type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
+		retval = verify_preview(cam, &f->fmt.win);
+		cam->win = f->fmt.win;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__,
+		 cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+	pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_bounds.width, cam->crop_bounds.height);
+	pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_defrect.width, cam->crop_defrect.height);
+	pr_debug("End of %s: crop_current widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_current.width, cam->crop_current.height);
+
+	return retval;
+}
+
+/*!
+ * get control param
+ *
+ * @param cam         structure cam_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
+{
+	int status = 0;
+
+	pr_debug("In MVC:mxc_v4l2_g_ctrl\n");
+
+	/* probably don't need to store the values that can be retrieved,
+	 * locally, but they are for now. */
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		/* This is handled in the ipu. */
+		if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
+			c->value = 1;
+		break;
+	case V4L2_CID_VFLIP:
+		/* This is handled in the ipu. */
+		if (cam->rotation == IPU_ROTATE_VERT_FLIP)
+			c->value = 1;
+		break;
+	case V4L2_CID_MXC_ROT:
+		/* This is handled in the ipu. */
+		c->value = cam->rotation;
+		break;
+	case V4L2_CID_BRIGHTNESS:
+		c->value = cam->bright;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->bright = c->value;
+		break;
+	case V4L2_CID_HUE:
+		c->value = cam->hue;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->hue = c->value;
+		break;
+	case V4L2_CID_CONTRAST:
+		c->value = cam->contrast;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->contrast = c->value;
+		break;
+	case V4L2_CID_SATURATION:
+		c->value = cam->saturation;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->saturation = c->value;
+		break;
+	case V4L2_CID_RED_BALANCE:
+		c->value = cam->red;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->red = c->value;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		c->value = cam->blue;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->blue = c->value;
+		break;
+	case V4L2_CID_BLACK_LEVEL:
+		c->value = cam->ae_mode;
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+		cam->ae_mode = c->value;
+		break;
+	default:
+		status = vidioc_int_g_ctrl(cam->sensor, c);
+	}
+
+	return status;
+}
+
+/*!
+ * V4L2 - set_control function
+ *          V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing.
+ *          0 for normal operation
+ *          1 for vertical flip
+ *          2 for horizontal flip
+ *          3 for horizontal and vertical flip
+ *          4 for 90 degree rotation
+ * @param cam         structure cam_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
+{
+	int ret = 0;
+	int tmp_rotation = IPU_ROTATE_NONE;
+
+	pr_debug("In MVC:mxc_v4l2_s_ctrl\n");
+
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		/* This is done by the IPU */
+		if (c->value == 1) {
+			if ((cam->rotation != IPU_ROTATE_VERT_FLIP) &&
+			    (cam->rotation != IPU_ROTATE_180))
+				cam->rotation = IPU_ROTATE_HORIZ_FLIP;
+			else
+				cam->rotation = IPU_ROTATE_180;
+		} else {
+			if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
+				cam->rotation = IPU_ROTATE_NONE;
+			if (cam->rotation == IPU_ROTATE_180)
+				cam->rotation = IPU_ROTATE_VERT_FLIP;
+		}
+		break;
+	case V4L2_CID_VFLIP:
+		/* This is done by the IPU */
+		if (c->value == 1) {
+			if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) &&
+			    (cam->rotation != IPU_ROTATE_180))
+				cam->rotation = IPU_ROTATE_VERT_FLIP;
+			else
+				cam->rotation = IPU_ROTATE_180;
+		} else {
+			if (cam->rotation == IPU_ROTATE_VERT_FLIP)
+				cam->rotation = IPU_ROTATE_NONE;
+			if (cam->rotation == IPU_ROTATE_180)
+				cam->rotation = IPU_ROTATE_HORIZ_FLIP;
+		}
+		break;
+	case V4L2_CID_MXC_ROT:
+	case V4L2_CID_MXC_VF_ROT:
+		/* This is done by the IPU */
+		switch (c->value) {
+		case V4L2_MXC_ROTATE_NONE:
+			tmp_rotation = IPU_ROTATE_NONE;
+			break;
+		case V4L2_MXC_ROTATE_VERT_FLIP:
+			tmp_rotation = IPU_ROTATE_VERT_FLIP;
+			break;
+		case V4L2_MXC_ROTATE_HORIZ_FLIP:
+			tmp_rotation = IPU_ROTATE_HORIZ_FLIP;
+			break;
+		case V4L2_MXC_ROTATE_180:
+			tmp_rotation = IPU_ROTATE_180;
+			break;
+		case V4L2_MXC_ROTATE_90_RIGHT:
+			tmp_rotation = IPU_ROTATE_90_RIGHT;
+			break;
+		case V4L2_MXC_ROTATE_90_RIGHT_VFLIP:
+			tmp_rotation = IPU_ROTATE_90_RIGHT_VFLIP;
+			break;
+		case V4L2_MXC_ROTATE_90_RIGHT_HFLIP:
+			tmp_rotation = IPU_ROTATE_90_RIGHT_HFLIP;
+			break;
+		case V4L2_MXC_ROTATE_90_LEFT:
+			tmp_rotation = IPU_ROTATE_90_LEFT;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+
+		if (c->id == V4L2_CID_MXC_VF_ROT)
+			cam->vf_rotation = tmp_rotation;
+		else
+			cam->rotation = tmp_rotation;
+
+		break;
+	case V4L2_CID_HUE:
+		cam->hue = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_CONTRAST:
+		cam->contrast = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_BRIGHTNESS:
+		cam->bright = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_SATURATION:
+		cam->saturation = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_RED_BALANCE:
+		cam->red = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		cam->blue = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_EXPOSURE:
+		cam->ae_mode = c->value;
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		ret = vidioc_int_s_ctrl(cam->sensor, c);
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		break;
+	case V4L2_CID_MXC_FLASH:
+#ifdef CONFIG_MXC_IPU_V1
+		ipu_csi_flash_strobe(true);
+#endif
+		break;
+	default:
+		pr_debug("   default case\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_s_param function
+ * Allows setting of capturemode and frame rate.
+ *
+ * @param cam         structure cam_data *
+ * @param parm        structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
+{
+	struct v4l2_ifparm ifparm;
+	struct v4l2_format cam_fmt;
+	struct v4l2_streamparm currentparm;
+	ipu_csi_signal_cfg_t csi_param;
+	int err = 0;
+
+	pr_debug("In mxc_v4l2_s_param\n");
+
+	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n");
+		return -EINVAL;
+	}
+
+	/* Stop the viewfinder */
+	if (cam->overlay_on == true) {
+		stop_preview(cam);
+	}
+
+	currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	/* First check that this device can support the changes requested. */
+	err = vidioc_int_g_parm(cam->sensor, &currentparm);
+	if (err) {
+		pr_err("%s: vidioc_int_g_parm returned an error %d\n",
+			__func__, err);
+		goto exit;
+	}
+
+	pr_debug("   Current capabilities are %x\n",
+			currentparm.parm.capture.capability);
+	pr_debug("   Current capturemode is %d  change to %d\n",
+			currentparm.parm.capture.capturemode,
+			parm->parm.capture.capturemode);
+	pr_debug("   Current framerate is %d  change to %d\n",
+			currentparm.parm.capture.timeperframe.denominator,
+			parm->parm.capture.timeperframe.denominator);
+
+	/* This will change any camera settings needed. */
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+	err = vidioc_int_s_parm(cam->sensor, parm);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+	if (err) {
+		pr_err("%s: vidioc_int_s_parm returned an error %d\n",
+			__func__, err);
+		goto exit;
+	}
+
+	/* If resolution changed, need to re-program the CSI */
+	/* Get new values. */
+	vidioc_int_g_ifparm(cam->sensor, &ifparm);
+
+	csi_param.data_width = 0;
+	csi_param.clk_mode = 0;
+	csi_param.ext_vsync = 0;
+	csi_param.Vsync_pol = 0;
+	csi_param.Hsync_pol = 0;
+	csi_param.pixclk_pol = 0;
+	csi_param.data_pol = 0;
+	csi_param.sens_clksrc = 0;
+	csi_param.pack_tight = 0;
+	csi_param.force_eof = 0;
+	csi_param.data_en_pol = 0;
+	csi_param.data_fmt = 0;
+	csi_param.csi = 0;
+	csi_param.mclk = 0;
+
+	/* This may not work on other platforms. Check when adding a new one.*/
+	pr_debug("   clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
+	if (ifparm.u.bt656.clock_curr == 0) {
+		csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
+	} else {
+		csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
+	}
+
+	csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
+
+	if (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) {
+		csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
+	} else if (ifparm.u.bt656.mode
+				== V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) {
+		csi_param.data_width = IPU_CSI_DATA_WIDTH_10;
+	} else {
+		csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
+	}
+
+	csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv;
+	csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv;
+	csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct;
+
+	/* if the capturemode changed, the size bounds will have changed. */
+	cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
+	pr_debug("   g_fmt_cap returns widthxheight of input as %d x %d\n",
+			cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
+
+	csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat;
+
+	cam->crop_bounds.top = cam->crop_bounds.left = 0;
+	cam->crop_bounds.width = cam_fmt.fmt.pix.width;
+	cam->crop_bounds.height = cam_fmt.fmt.pix.height;
+
+	/*
+	 * Set the default current cropped resolution to be the same with
+	 * the cropping boundary(except for tvin module).
+	 */
+	if (cam->device_type != 1) {
+		cam->crop_current.width = cam->crop_bounds.width;
+		cam->crop_current.height = cam->crop_bounds.height;
+	}
+
+	/* This essentially loses the data at the left and bottom of the image
+	 * giving a digital zoom image, if crop_current is less than the full
+	 * size of the image. */
+	ipu_csi_set_window_size(cam->crop_current.width,
+				cam->crop_current.height, cam->csi);
+	ipu_csi_set_window_pos(cam->crop_current.left,
+			       cam->crop_current.top,
+			       cam->csi);
+	ipu_csi_init_interface(cam->crop_bounds.width,
+			       cam->crop_bounds.height,
+			       cam_fmt.fmt.pix.pixelformat, csi_param);
+
+
+exit:
+	if (cam->overlay_on == true)
+		start_preview(cam);
+
+	return err;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_s_std function
+ *
+ * Sets the TV standard to be used.
+ *
+ * @param cam	      structure cam_data *
+ * @param parm	      structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e)
+{
+	bool change = false;
+
+	if (e != cam->standard.id) {
+		change = true;
+	}
+
+	pr_debug("In mxc_v4l2_s_std %Lx\n", e);
+	if (e == V4L2_STD_PAL) {
+		pr_debug("   Setting standard to PAL %Lx\n", V4L2_STD_PAL);
+		cam->standard.id = V4L2_STD_PAL;
+		video_index = TV_PAL;
+		cam->crop_current.top = 0;
+	} else if (e == V4L2_STD_NTSC) {
+		pr_debug("   Setting standard to NTSC %Lx\n",
+				V4L2_STD_NTSC);
+		/* Get rid of the white dot line in NTSC signal input */
+		cam->standard.id = V4L2_STD_NTSC;
+		video_index = TV_NTSC;
+		cam->crop_current.top = 12;
+	} else {
+		cam->standard.id = V4L2_STD_ALL;
+		video_index = TV_NOT_LOCKED;
+		cam->crop_current.top = 0;
+		pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n",
+			e, V4L2_STD_PAL, V4L2_STD_NTSC);
+	}
+
+	cam->standard.index = video_index;
+	strcpy(cam->standard.name, video_fmts[video_index].name);
+	cam->crop_bounds.width = video_fmts[video_index].raw_width;
+	cam->crop_bounds.height = video_fmts[video_index].raw_height;
+	cam->crop_current.width = video_fmts[video_index].active_width;
+	cam->crop_current.height = video_fmts[video_index].active_height;
+	cam->crop_current.left = 0;
+
+	return 0;
+}
+
+/*!
+ * V4L2 - mxc_v4l2_g_std function
+ *
+ * Gets the TV standard from the TV input device.
+ *
+ * @param cam	      structure cam_data *
+ *
+ * @param e	      structure v4l2_streamparm *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e)
+{
+	struct v4l2_format tv_fmt;
+
+	pr_debug("In mxc_v4l2_g_std\n");
+
+	if (cam->device_type == 1) {
+		/* Use this function to get what the TV-In device detects the
+		 * format to be. pixelformat is used to return the std value
+		 * since the interface has no vidioc_g_std.*/
+		tv_fmt.type = V4L2_BUF_TYPE_PRIVATE;
+		vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt);
+
+		/* If the TV-in automatically detects the standard, then if it
+		 * changes, the settings need to change. */
+		if (cam->standard_autodetect) {
+			if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) {
+				pr_debug("MVC: mxc_v4l2_g_std: "
+					"Changing standard\n");
+				mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat);
+			}
+		}
+
+		*e = tv_fmt.fmt.pix.pixelformat;
+	}
+
+	return 0;
+}
+
+/*!
+ * Dequeue one V4L capture buffer
+ *
+ * @param cam         structure cam_data *
+ * @param buf         structure v4l2_buffer *
+ *
+ * @return  status    0 success, EINVAL invalid frame number,
+ *                    ETIME timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
+{
+	int retval = 0;
+	struct mxc_v4l_frame *frame;
+	unsigned long lock_flags;
+
+	pr_debug("In MVC:mxc_v4l_dqueue\n");
+
+	if (!wait_event_interruptible_timeout(cam->enc_queue,
+					      cam->enc_counter != 0, 10 * HZ)) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout "
+			"enc_counter %x\n",
+		       cam->enc_counter);
+		return -ETIME;
+	} else if (signal_pending(current)) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() "
+			"interrupt received\n");
+		return -ERESTARTSYS;
+	}
+
+	spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
+
+	cam->enc_counter--;
+
+	frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
+	list_del(cam->done_q.next);
+	if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
+	} else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+		pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
+			"Buffer not filled.\n");
+		frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+		retval = -EINVAL;
+	} else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
+		pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
+			"Buffer not queued.\n");
+		retval = -EINVAL;
+	}
+
+	buf->bytesused = cam->v2f.fmt.pix.sizeimage;
+	buf->index = frame->index;
+	buf->flags = frame->buffer.flags;
+	buf->m = cam->frame[frame->index].buffer.m;
+	buf->timestamp = cam->frame[frame->index].buffer.timestamp;
+
+	spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
+	return retval;
+}
+
+/*!
+ * V4L interface - open function
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l_open(struct file *file)
+{
+	struct v4l2_ifparm ifparm;
+	struct v4l2_format cam_fmt;
+	ipu_csi_signal_cfg_t csi_param;
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int err = 0;
+
+	pr_debug("\nIn MVC: mxc_v4l_open\n");
+	pr_debug("   device name is %s\n", dev->name);
+
+	if (!cam) {
+		pr_err("ERROR: v4l2 capture: Internal error, "
+			"cam_data not found!\n");
+		return -EBADF;
+	}
+
+	down(&cam->busy_lock);
+	err = 0;
+	if (signal_pending(current))
+		goto oops;
+
+	if (cam->open_count++ == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+
+		if (strcmp(mxc_capture_inputs[cam->current_input].name,
+			   "CSI MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+			err = csi_enc_select(cam);
+#endif
+		} else if (strcmp(mxc_capture_inputs[cam->current_input].name,
+				  "CSI IC MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
+			err = prp_enc_select(cam);
+#endif
+		}
+
+		cam->enc_counter = 0;
+		cam->skip_frame = 0;
+		INIT_LIST_HEAD(&cam->ready_q);
+		INIT_LIST_HEAD(&cam->working_q);
+		INIT_LIST_HEAD(&cam->done_q);
+
+		vidioc_int_g_ifparm(cam->sensor, &ifparm);
+
+		csi_param.sens_clksrc = 0;
+
+		csi_param.clk_mode = 0;
+		csi_param.data_pol = 0;
+		csi_param.ext_vsync = 0;
+
+		csi_param.pack_tight = 0;
+		csi_param.force_eof = 0;
+		csi_param.data_en_pol = 0;
+		csi_param.mclk = ifparm.u.bt656.clock_curr;
+
+		csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
+
+		/* Once we handle multiple inputs this will need to change. */
+		csi_param.csi = 0;
+
+		if (ifparm.u.bt656.mode
+				== V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT)
+			csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
+		else if (ifparm.u.bt656.mode
+				== V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT)
+			csi_param.data_width = IPU_CSI_DATA_WIDTH_10;
+		else
+			csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
+
+
+		csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv;
+		csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv;
+
+		csi_param.csi = cam->csi;
+
+		cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
+
+		/* Reset the sizes.  Needed to prevent carryover of last
+		 * operation.*/
+		cam->crop_bounds.top = cam->crop_bounds.left = 0;
+		cam->crop_bounds.width = cam_fmt.fmt.pix.width;
+		cam->crop_bounds.height = cam_fmt.fmt.pix.height;
+
+		/* This also is the max crop size for this device. */
+		cam->crop_defrect.top = cam->crop_defrect.left = 0;
+		cam->crop_defrect.width = cam_fmt.fmt.pix.width;
+		cam->crop_defrect.height = cam_fmt.fmt.pix.height;
+
+		/* At this point, this is also the current image size. */
+		cam->crop_current.top = cam->crop_current.left = 0;
+		cam->crop_current.width = cam_fmt.fmt.pix.width;
+		cam->crop_current.height = cam_fmt.fmt.pix.height;
+
+		pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+			__func__,
+			cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+		pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
+			__func__,
+			cam->crop_bounds.width, cam->crop_bounds.height);
+		pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
+			__func__,
+			cam->crop_defrect.width, cam->crop_defrect.height);
+		pr_debug("End of %s: crop_current widthxheight %d x %d\n",
+			__func__,
+			cam->crop_current.width, cam->crop_current.height);
+
+		csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat;
+		pr_debug("On Open: Input to ipu size is %d x %d\n",
+				cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
+		ipu_csi_set_window_size(cam->crop_current.width,
+					cam->crop_current.width,
+					cam->csi);
+		ipu_csi_set_window_pos(cam->crop_current.left,
+					cam->crop_current.top,
+					cam->csi);
+		ipu_csi_init_interface(cam->crop_bounds.width,
+					cam->crop_bounds.height,
+					cam_fmt.fmt.pix.pixelformat,
+					csi_param);
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
+				       true, true);
+		vidioc_int_init(cam->sensor);
+
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi,
+				       false, false);
+}
+
+	file->private_data = dev;
+
+      oops:
+	up(&cam->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L interface - close function
+ *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int mxc_v4l_close(struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	int err = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	pr_debug("In MVC:mxc_v4l_close\n");
+
+	if (!cam) {
+		pr_err("ERROR: v4l2 capture: Internal error, "
+			"cam_data not found!\n");
+		return -EBADF;
+	}
+
+	/* for the case somebody hit the ctrl C */
+	if (cam->overlay_pid == current->pid) {
+		err = stop_preview(cam);
+		cam->overlay_on = false;
+	}
+	if (cam->capture_pid == current->pid) {
+		err |= mxc_streamoff(cam);
+		wake_up_interruptible(&cam->enc_queue);
+	}
+
+	if (--cam->open_count == 0) {
+		wait_event_interruptible(cam->power_queue,
+					 cam->low_power == false);
+		pr_info("mxc_v4l_close: release resource\n");
+
+		if (strcmp(mxc_capture_inputs[cam->current_input].name,
+			   "CSI MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+			err |= csi_enc_deselect(cam);
+#endif
+		} else if (strcmp(mxc_capture_inputs[cam->current_input].name,
+				  "CSI IC MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
+			err |= prp_enc_deselect(cam);
+#endif
+		}
+
+		mxc_free_frame_buf(cam);
+		file->private_data = NULL;
+
+		/* capture off */
+		wake_up_interruptible(&cam->enc_queue);
+		mxc_free_frames(cam);
+		cam->enc_counter++;
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC) || \
+    defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) || \
+    defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+/*
+ * V4L interface - read function
+ *
+ * @param file       struct file *
+ * @param read buf   char *
+ * @param count      size_t
+ * @param ppos       structure loff_t *
+ *
+ * @return           bytes read
+ */
+static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
+			    loff_t *ppos)
+{
+	int err = 0;
+	u8 *v_address[2];
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	/* Stop the viewfinder */
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+
+	v_address[0] = dma_alloc_coherent(0,
+				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				       &cam->still_buf[0],
+				       GFP_DMA | GFP_KERNEL);
+
+	v_address[1] = dma_alloc_coherent(0,
+				       PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
+				       &cam->still_buf[1],
+				       GFP_DMA | GFP_KERNEL);
+
+	if (!v_address[0] || !v_address[1]) {
+		err = -ENOBUFS;
+		goto exit0;
+	}
+
+	err = prp_still_select(cam);
+	if (err != 0) {
+		err = -EIO;
+		goto exit0;
+	}
+
+	cam->still_counter = 0;
+	err = cam->csi_start(cam);
+	if (err != 0) {
+		err = -EIO;
+		goto exit1;
+	}
+
+	if (!wait_event_interruptible_timeout(cam->still_queue,
+					      cam->still_counter != 0,
+					      10 * HZ)) {
+		pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n",
+		       cam->still_counter);
+		err = -ETIME;
+		goto exit1;
+	}
+	err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage);
+
+      exit1:
+	prp_still_deselect(cam);
+
+      exit0:
+	if (v_address[0] != 0)
+		dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0],
+				  cam->still_buf[0]);
+	if (v_address[1] != 0)
+		dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1],
+				  cam->still_buf[1]);
+
+	cam->still_buf[0] = cam->still_buf[1] = 0;
+
+	if (cam->overlay_on == true) {
+		start_preview(cam);
+	}
+
+	up(&cam->busy_lock);
+	if (err < 0)
+		return err;
+
+	return (cam->v2f.fmt.pix.sizeimage - err);
+}
+#endif
+
+/*!
+ * V4L interface - ioctl function
+ *
+ * @param file       struct file*
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void*
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static long mxc_v4l_do_ioctl(struct file *file,
+			    unsigned int ioctlnr, void *arg)
+{
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	int retval = 0;
+	unsigned long lock_flags;
+
+	pr_debug("In MVC: mxc_v4l_do_ioctl %x\n", ioctlnr);
+	wait_event_interruptible(cam->power_queue, cam->low_power == false);
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+	/*!
+	 * V4l2 VIDIOC_QUERYCAP ioctl
+	 */
+	case VIDIOC_QUERYCAP: {
+		struct v4l2_capability *cap = arg;
+		pr_debug("   case VIDIOC_QUERYCAP\n");
+		strcpy(cap->driver, "mxc_v4l2");
+		cap->version = KERNEL_VERSION(0, 1, 11);
+		cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
+				    V4L2_CAP_VIDEO_OVERLAY |
+				    V4L2_CAP_STREAMING |
+				    V4L2_CAP_READWRITE;
+		cap->card[0] = '\0';
+		cap->bus_info[0] = '\0';
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_G_FMT ioctl
+	 */
+	case VIDIOC_G_FMT: {
+		struct v4l2_format *gf = arg;
+		pr_debug("   case VIDIOC_G_FMT\n");
+		retval = mxc_v4l2_g_fmt(cam, gf);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_S_FMT ioctl
+	 */
+	case VIDIOC_S_FMT: {
+		struct v4l2_format *sf = arg;
+		pr_debug("   case VIDIOC_S_FMT\n");
+		retval = mxc_v4l2_s_fmt(cam, sf);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_REQBUFS ioctl
+	 */
+	case VIDIOC_REQBUFS: {
+		struct v4l2_requestbuffers *req = arg;
+		pr_debug("   case VIDIOC_REQBUFS\n");
+
+		if (req->count > FRAME_NUM) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
+			       "not enough buffers\n");
+			req->count = FRAME_NUM;
+		}
+
+		if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
+		    (req->memory != V4L2_MEMORY_MMAP)) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
+			       "wrong buffer type\n");
+			retval = -EINVAL;
+			break;
+		}
+
+		mxc_streamoff(cam);
+		mxc_free_frame_buf(cam);
+		cam->enc_counter = 0;
+		cam->skip_frame = 0;
+		INIT_LIST_HEAD(&cam->ready_q);
+		INIT_LIST_HEAD(&cam->working_q);
+		INIT_LIST_HEAD(&cam->done_q);
+
+		retval = mxc_allocate_frame_buf(cam, req->count);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_QUERYBUF ioctl
+	 */
+	case VIDIOC_QUERYBUF: {
+		struct v4l2_buffer *buf = arg;
+		int index = buf->index;
+		pr_debug("   case VIDIOC_QUERYBUF\n");
+
+		if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+			pr_err("ERROR: v4l2 capture: "
+			       "VIDIOC_QUERYBUFS: "
+			       "wrong buffer type\n");
+			retval = -EINVAL;
+			break;
+		}
+
+		memset(buf, 0, sizeof(buf));
+		buf->index = index;
+
+		down(&cam->param_lock);
+		retval = mxc_v4l2_buffer_status(cam, buf);
+		up(&cam->param_lock);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_QBUF ioctl
+	 */
+	case VIDIOC_QBUF: {
+		struct v4l2_buffer *buf = arg;
+		int index = buf->index;
+		pr_debug("   case VIDIOC_QBUF\n");
+
+		spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
+		cam->frame[index].buffer.m.offset = buf->m.offset;
+		if ((cam->frame[index].buffer.flags & 0x7) ==
+		    V4L2_BUF_FLAG_MAPPED) {
+			cam->frame[index].buffer.flags |=
+			    V4L2_BUF_FLAG_QUEUED;
+			if (strcmp(mxc_capture_inputs[cam->current_input].name,
+				"CSI IC MEM") == 0) {
+				if (cam->skip_frame > 0) {
+					list_add_tail(&cam->frame[index].queue,
+						      &cam->working_q);
+
+					retval =
+					   cam->enc_update_eba(cam->
+							       frame[index].
+							       buffer.m.offset,
+							       &cam->
+							       ping_pong_csi);
+
+					cam->skip_frame = 0;
+				} else
+					list_add_tail(&cam->frame[index].queue,
+						      &cam->ready_q);
+			} else if (strcmp(
+					mxc_capture_inputs[cam->current_input].
+					name, "CSI MEM") == 0) {
+				list_add_tail(&cam->frame[index].queue,
+					      &cam->ready_q);
+			}
+		} else if (cam->frame[index].buffer.
+			   flags & V4L2_BUF_FLAG_QUEUED) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
+			       "buffer already queued\n");
+			retval = -EINVAL;
+		} else if (cam->frame[index].buffer.
+			   flags & V4L2_BUF_FLAG_DONE) {
+			pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
+			       "overwrite done buffer.\n");
+			cam->frame[index].buffer.flags &=
+			    ~V4L2_BUF_FLAG_DONE;
+			cam->frame[index].buffer.flags |=
+			    V4L2_BUF_FLAG_QUEUED;
+			retval = -EINVAL;
+		}
+
+		buf->flags = cam->frame[index].buffer.flags;
+		spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_DQBUF ioctl
+	 */
+	case VIDIOC_DQBUF: {
+		struct v4l2_buffer *buf = arg;
+		pr_debug("   case VIDIOC_DQBUF\n");
+
+		if ((cam->enc_counter == 0) &&
+			(file->f_flags & O_NONBLOCK)) {
+			retval = -EAGAIN;
+			break;
+		}
+
+		retval = mxc_v4l_dqueue(cam, buf);
+
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_STREAMON ioctl
+	 */
+	case VIDIOC_STREAMON: {
+		pr_debug("   case VIDIOC_STREAMON\n");
+		retval = mxc_streamon(cam);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_STREAMOFF ioctl
+	 */
+	case VIDIOC_STREAMOFF: {
+		pr_debug("   case VIDIOC_STREAMOFF\n");
+		retval = mxc_streamoff(cam);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_G_CTRL ioctl
+	 */
+	case VIDIOC_G_CTRL: {
+		pr_debug("   case VIDIOC_G_CTRL\n");
+		retval = mxc_v4l2_g_ctrl(cam, arg);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_S_CTRL ioctl
+	 */
+	case VIDIOC_S_CTRL: {
+		pr_debug("   case VIDIOC_S_CTRL\n");
+		retval = mxc_v4l2_s_ctrl(cam, arg);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_CROPCAP ioctl
+	 */
+	case VIDIOC_CROPCAP: {
+		struct v4l2_cropcap *cap = arg;
+		pr_debug("   case VIDIOC_CROPCAP\n");
+		if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+		    cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+			retval = -EINVAL;
+			break;
+		}
+		cap->bounds = cam->crop_bounds;
+		cap->defrect = cam->crop_defrect;
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_G_CROP ioctl
+	 */
+	case VIDIOC_G_CROP: {
+		struct v4l2_crop *crop = arg;
+		pr_debug("   case VIDIOC_G_CROP\n");
+
+		if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+		    crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+			retval = -EINVAL;
+			break;
+		}
+		crop->c = cam->crop_current;
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_S_CROP ioctl
+	 */
+	case VIDIOC_S_CROP: {
+		struct v4l2_crop *crop = arg;
+		struct v4l2_rect *b = &cam->crop_bounds;
+		pr_debug("   case VIDIOC_S_CROP\n");
+
+		if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+		    crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+			retval = -EINVAL;
+			break;
+		}
+
+		crop->c.top = (crop->c.top < b->top) ? b->top
+			      : crop->c.top;
+		if (crop->c.top > b->top + b->height)
+			crop->c.top = b->top + b->height - 1;
+		if (crop->c.height > b->top + b->height - crop->c.top)
+			crop->c.height =
+				b->top + b->height - crop->c.top;
+
+		crop->c.left = (crop->c.left < b->left) ? b->left
+		    : crop->c.left;
+		if (crop->c.left > b->left + b->width)
+			crop->c.left = b->left + b->width - 1;
+		if (crop->c.width > b->left - crop->c.left + b->width)
+			crop->c.width =
+				b->left - crop->c.left + b->width;
+
+		crop->c.width -= crop->c.width % 8;
+		crop->c.left -= crop->c.left % 4;
+		cam->crop_current = crop->c;
+
+		pr_debug("   Cropping Input to ipu size %d x %d\n",
+				cam->crop_current.width,
+				cam->crop_current.height);
+		ipu_csi_set_window_size(cam->crop_current.width,
+					cam->crop_current.height,
+					cam->csi);
+		ipu_csi_set_window_pos(cam->crop_current.left,
+				       cam->crop_current.top,
+				       cam->csi);
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_OVERLAY ioctl
+	 */
+	case VIDIOC_OVERLAY: {
+		int *on = arg;
+		pr_debug("   VIDIOC_OVERLAY on=%d\n", *on);
+		if (*on) {
+			cam->overlay_on = true;
+			cam->overlay_pid = current->pid;
+			retval = start_preview(cam);
+		}
+		if (!*on) {
+			retval = stop_preview(cam);
+			cam->overlay_on = false;
+		}
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_G_FBUF ioctl
+	 */
+	case VIDIOC_G_FBUF: {
+		struct v4l2_framebuffer *fb = arg;
+		pr_debug("   case VIDIOC_G_FBUF\n");
+		*fb = cam->v4l2_fb;
+		fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+		break;
+	}
+
+	/*!
+	 * V4l2 VIDIOC_S_FBUF ioctl
+	 */
+	case VIDIOC_S_FBUF: {
+		struct v4l2_framebuffer *fb = arg;
+		pr_debug("   case VIDIOC_S_FBUF\n");
+		cam->v4l2_fb = *fb;
+		break;
+	}
+
+	case VIDIOC_G_PARM: {
+		struct v4l2_streamparm *parm = arg;
+		pr_debug("   case VIDIOC_G_PARM\n");
+		vidioc_int_g_parm(cam->sensor, parm);
+		break;
+	}
+
+	case VIDIOC_S_PARM:  {
+		struct v4l2_streamparm *parm = arg;
+		pr_debug("   case VIDIOC_S_PARM\n");
+		retval = mxc_v4l2_s_param(cam, parm);
+		break;
+	}
+
+	/* linux v4l2 bug, kernel c0485619 user c0405619 */
+	case VIDIOC_ENUMSTD: {
+		struct v4l2_standard *e = arg;
+		pr_debug("   case VIDIOC_ENUMSTD\n");
+		*e = cam->standard;
+		break;
+	}
+
+	case VIDIOC_G_STD: {
+		v4l2_std_id *e = arg;
+		pr_debug("   case VIDIOC_G_STD\n");
+		retval = mxc_v4l2_g_std(cam, e);
+		break;
+	}
+
+	case VIDIOC_S_STD: {
+		v4l2_std_id *e = arg;
+		pr_debug("   case VIDIOC_S_STD\n");
+		retval = mxc_v4l2_s_std(cam, *e);
+
+		break;
+	}
+
+	case VIDIOC_ENUMOUTPUT: {
+		struct v4l2_output *output = arg;
+		pr_debug("   case VIDIOC_ENUMOUTPUT\n");
+		if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
+			retval = -EINVAL;
+			break;
+		}
+		*output = mxc_capture_outputs[output->index];
+
+		break;
+	}
+	case VIDIOC_G_OUTPUT: {
+		int *p_output_num = arg;
+		pr_debug("   case VIDIOC_G_OUTPUT\n");
+		*p_output_num = cam->output;
+		break;
+	}
+
+	case VIDIOC_S_OUTPUT: {
+		int *p_output_num = arg;
+		pr_debug("   case VIDIOC_S_OUTPUT\n");
+		if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
+			retval = -EINVAL;
+			break;
+		}
+		cam->output = *p_output_num;
+		break;
+	}
+
+	case VIDIOC_ENUMINPUT: {
+		struct v4l2_input *input = arg;
+		pr_debug("   case VIDIOC_ENUMINPUT\n");
+		if (input->index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
+			retval = -EINVAL;
+			break;
+		}
+		*input = mxc_capture_inputs[input->index];
+		break;
+	}
+
+	case VIDIOC_G_INPUT: {
+		int *index = arg;
+		pr_debug("   case VIDIOC_G_INPUT\n");
+		*index = cam->current_input;
+		break;
+	}
+
+	case VIDIOC_S_INPUT: {
+		int *index = arg;
+		pr_debug("   case VIDIOC_S_INPUT\n");
+		if (*index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
+			retval = -EINVAL;
+			break;
+		}
+
+		if (*index == cam->current_input)
+			break;
+
+		if ((mxc_capture_inputs[cam->current_input].status &
+		    V4L2_IN_ST_NO_POWER) == 0) {
+			retval = mxc_streamoff(cam);
+			if (retval)
+				break;
+			mxc_capture_inputs[cam->current_input].status |=
+							V4L2_IN_ST_NO_POWER;
+		}
+
+		if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
+			retval = csi_enc_select(cam);
+			if (retval)
+				break;
+#endif
+		} else if (strcmp(mxc_capture_inputs[*index].name,
+				  "CSI IC MEM") == 0) {
+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
+			retval = prp_enc_select(cam);
+			if (retval)
+				break;
+#endif
+		}
+
+		mxc_capture_inputs[*index].status &= ~V4L2_IN_ST_NO_POWER;
+		cam->current_input = *index;
+		break;
+	}
+
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	default:
+		pr_debug("   case default or not supported\n");
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&cam->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L interface - ioctl function
+ *
+ * @return  None
+ */
+static long mxc_v4l_ioctl(struct file *file, unsigned int cmd,
+			 unsigned long arg)
+{
+	pr_debug("In MVC:mxc_v4l_ioctl\n");
+	return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl);
+}
+
+/*!
+ * V4L interface - mmap function
+ *
+ * @param file        structure file *
+ *
+ * @param vma         structure vm_area_struct *
+ *
+ * @return status     0 Success, EINTR busy lock error, ENOBUFS remap_page error
+ */
+static int mxc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *dev = video_devdata(file);
+	unsigned long size;
+	int res = 0;
+	cam_data *cam = video_get_drvdata(dev);
+
+	pr_debug("In MVC:mxc_mmap\n");
+	pr_debug("   pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		 vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	size = vma->vm_end - vma->vm_start;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		pr_err("ERROR: v4l2 capture: mxc_mmap: "
+			"remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+      mxc_mmap_exit:
+	up(&cam->busy_lock);
+	return res;
+}
+
+/*!
+ * V4L interface - poll function
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table_struct *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait)
+{
+	struct video_device *dev = video_devdata(file);
+	cam_data *cam = video_get_drvdata(dev);
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	pr_debug("In MVC:mxc_poll\n");
+
+	if (down_interruptible(&cam->busy_lock))
+		return -EINTR;
+
+	queue = &cam->enc_queue;
+	poll_wait(file, queue, wait);
+
+	up(&cam->busy_lock);
+
+	return res;
+}
+
+/*!
+ * This structure defines the functions to be called in this driver.
+ */
+static struct v4l2_file_operations mxc_v4l_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_v4l_open,
+	.release = mxc_v4l_close,
+	.read = mxc_v4l_read,
+	.ioctl = mxc_v4l_ioctl,
+	.mmap = mxc_mmap,
+	.poll = mxc_poll,
+};
+
+static struct video_device mxc_v4l_template = {
+	.name = "Mxc Camera",
+	.fops = &mxc_v4l_fops,
+	.release = video_device_release,
+};
+
+/*!
+ * This function can be used to release any platform data on closing.
+ */
+static void camera_platform_release(struct device *device)
+{
+}
+
+/*!
+ * Camera V4l2 callback function.
+ *
+ * @param mask      u32
+ *
+ * @param dev       void device structure
+ *
+ * @return status
+ */
+static void camera_callback(u32 mask, void *dev)
+{
+	struct mxc_v4l_frame *done_frame;
+	struct mxc_v4l_frame *ready_frame;
+	struct timeval cur_time;
+
+	cam_data *cam = (cam_data *) dev;
+	if (cam == NULL)
+		return;
+
+	pr_debug("In MVC:camera_callback\n");
+
+	if (strcmp(mxc_capture_inputs[cam->current_input].name, "CSI IC MEM")
+	    == 0) {
+		if (list_empty(&cam->working_q)) {
+			pr_err("ERROR: v4l2 capture: camera_callback: "
+				"working queue empty\n");
+			return;
+		}
+		do_gettimeofday(&cur_time);
+
+		done_frame = list_entry(cam->working_q.next,
+					struct mxc_v4l_frame,
+					queue);
+
+		/*
+		 * Set the current time to done frame buffer's timestamp.
+		 * Users can use this information to judge the frame's usage.
+		 */
+		done_frame->buffer.timestamp = cur_time;
+		if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+			done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
+			done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
+
+			/* Added to the done queue */
+			list_del(cam->working_q.next);
+			list_add_tail(&done_frame->queue, &cam->done_q);
+
+			/* Wake up the queue */
+			cam->enc_counter++;
+			wake_up_interruptible(&cam->enc_queue);
+
+			if (list_empty(&cam->ready_q)) {
+				cam->skip_frame++;
+			} else {
+				ready_frame = list_entry(cam->ready_q.next,
+							 struct mxc_v4l_frame,
+							 queue);
+
+				if (cam->enc_update_eba(
+						ready_frame->buffer.m.offset,
+						&cam->ping_pong_csi) == 0) {
+					list_del(cam->ready_q.next);
+					list_add_tail(&ready_frame->queue,
+						      &cam->working_q);
+				} else
+					return;
+			}
+		} else {
+			pr_err("ERROR: v4l2 capture: camera_callback: "
+				"buffer not queued\n");
+		}
+	} else if (strcmp(mxc_capture_inputs[cam->current_input].name,
+		   "CSI MEM") == 0) {
+		if (!list_empty(&cam->working_q)) {
+			do_gettimeofday(&cur_time);
+
+			done_frame = list_entry(cam->working_q.next,
+						struct mxc_v4l_frame,
+						queue);
+
+			/*
+			 * Set the current time to done frame buffer's
+			 * timestamp. Users can use this information to judge
+			 * the frame's usage.
+			 */
+			done_frame->buffer.timestamp = cur_time;
+
+			if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
+				done_frame->buffer.flags |=
+							V4L2_BUF_FLAG_DONE;
+				done_frame->buffer.flags &=
+							~V4L2_BUF_FLAG_QUEUED;
+
+				/* Added to the done queue */
+				list_del(cam->working_q.next);
+				list_add_tail(&done_frame->queue, &cam->done_q);
+
+				/* Wake up the queue */
+				cam->enc_counter++;
+				wake_up_interruptible(&cam->enc_queue);
+			} else {
+				pr_err("ERROR: v4l2 capture: camera_callback: "
+					"buffer not queued\n");
+			}
+		}
+
+		if (!list_empty(&cam->ready_q)) {
+			ready_frame = list_entry(cam->ready_q.next,
+						 struct mxc_v4l_frame,
+						 queue);
+			if (cam->enc_update_eba(ready_frame->buffer.m.offset,
+						&cam->ping_pong_csi) == 0) {
+				list_del(cam->ready_q.next);
+				list_add_tail(&ready_frame->queue,
+					      &cam->working_q);
+			} else
+				return;
+		} else {
+			if (cam->enc_update_eba(
+				cam->dummy_frame.buffer.m.offset,
+				&cam->ping_pong_csi) == -EACCES)
+				return;
+		}
+	}
+
+	return;
+}
+
+/*!
+ * initialize cam_data structure
+ *
+ * @param cam      structure cam_data *
+ *
+ * @return status  0 Success
+ */
+static void init_camera_struct(cam_data *cam, struct platform_device *pdev)
+{
+	pr_debug("In MVC: init_camera_struct\n");
+
+	/* Default everything to 0 */
+	memset(cam, 0, sizeof(cam_data));
+
+	init_MUTEX(&cam->param_lock);
+	init_MUTEX(&cam->busy_lock);
+
+	cam->video_dev = video_device_alloc();
+	if (cam->video_dev == NULL)
+		return;
+
+	*(cam->video_dev) = mxc_v4l_template;
+
+	video_set_drvdata(cam->video_dev, cam);
+	dev_set_drvdata(&pdev->dev, (void *)cam);
+	cam->video_dev->minor = -1;
+
+	init_waitqueue_head(&cam->enc_queue);
+	init_waitqueue_head(&cam->still_queue);
+
+	/* setup cropping */
+	cam->crop_bounds.left = 0;
+	cam->crop_bounds.width = 640;
+	cam->crop_bounds.top = 0;
+	cam->crop_bounds.height = 480;
+	cam->crop_current = cam->crop_defrect = cam->crop_bounds;
+	ipu_csi_set_window_size(cam->crop_current.width,
+				cam->crop_current.height, cam->csi);
+	ipu_csi_set_window_pos(cam->crop_current.left,
+				cam->crop_current.top, cam->csi);
+	cam->streamparm.parm.capture.capturemode = 0;
+
+	cam->standard.index = 0;
+	cam->standard.id = V4L2_STD_UNKNOWN;
+	cam->standard.frameperiod.denominator = 30;
+	cam->standard.frameperiod.numerator = 1;
+	cam->standard.framelines = 480;
+	cam->standard_autodetect = true;
+	cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
+	cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+	cam->overlay_on = false;
+	cam->capture_on = false;
+	cam->skip_frame = 0;
+	cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
+
+	cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2;
+	cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2;
+	cam->v2f.fmt.pix.width = 288;
+	cam->v2f.fmt.pix.height = 352;
+	cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
+	cam->win.w.width = 160;
+	cam->win.w.height = 160;
+	cam->win.w.left = 0;
+	cam->win.w.top = 0;
+
+	cam->csi = 0;  /* Need to determine how to set this correctly with
+			* multiple video input devices. */
+
+	cam->enc_callback = camera_callback;
+	init_waitqueue_head(&cam->power_queue);
+	spin_lock_init(&cam->queue_int_lock);
+	spin_lock_init(&cam->dqueue_int_lock);
+}
+
+/*!
+ * camera_power function
+ *    Turns Sensor power On/Off
+ *
+ * @param       cam           cam data struct
+ * @param       cameraOn      true to turn camera on, false to turn off power.
+ *
+ * @return status
+ */
+static u8 camera_power(cam_data *cam, bool cameraOn)
+{
+	pr_debug("In MVC:camera_power on=%d\n", cameraOn);
+
+	if (cameraOn == true) {
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+		vidioc_int_s_power(cam->sensor, 1);
+	} else {
+		ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+		vidioc_int_s_power(cam->sensor, 0);
+	}
+	return 0;
+}
+
+/*!
+ * This function is called to probe the devices if registered.
+ *
+ * @param   pdev  the device structure used to give information on which device
+ *                to probe
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int mxc_v4l2_probe(struct platform_device *pdev)
+{
+	/* Create g_cam and initialize it. */
+	g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
+	if (g_cam == NULL) {
+		pr_err("ERROR: v4l2 capture: failed to register camera\n");
+		return -1;
+	}
+	init_camera_struct(g_cam, pdev);
+	pdev->dev.release = camera_platform_release;
+
+	/* Set up the v4l2 device and register it*/
+	mxc_v4l2_int_device.priv = g_cam;
+	/* This function contains a bug that won't let this be rmmod'd. */
+	v4l2_int_device_register(&mxc_v4l2_int_device);
+
+	/* register v4l video device */
+	if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr)
+	    == -1) {
+		kfree(g_cam);
+		g_cam = NULL;
+		pr_err("ERROR: v4l2 capture: video_register_device failed\n");
+		return -1;
+	}
+	pr_debug("   Video device registered: %s #%d\n",
+		 g_cam->video_dev->name, g_cam->video_dev->minor);
+
+	return 0;
+}
+
+/*!
+ * This function is called to remove the devices when device unregistered.
+ *
+ * @param   pdev  the device structure used to give information on which device
+ *                to remove
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int mxc_v4l2_remove(struct platform_device *pdev)
+{
+
+	if (g_cam->open_count) {
+		pr_err("ERROR: v4l2 capture:camera open "
+			"-- setting ops to NULL\n");
+		return -EBUSY;
+	} else {
+		pr_info("V4L2 freeing image input device\n");
+		v4l2_int_device_unregister(&mxc_v4l2_int_device);
+		video_unregister_device(g_cam->video_dev);
+
+		mxc_free_frame_buf(g_cam);
+		kfree(g_cam);
+		g_cam = NULL;
+	}
+
+	pr_info("V4L2 unregistering video\n");
+	return 0;
+}
+
+/*!
+ * This function is called to put the sensor in a low power state.
+ * Refer to the document driver-model/driver.txt in the kernel source tree
+ * for more information.
+ *
+ * @param   pdev  the device structure used to give information on which I2C
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure.
+ */
+static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	pr_debug("In MVC:mxc_v4l2_suspend\n");
+
+	if (cam == NULL) {
+		return -1;
+	}
+
+	cam->low_power = true;
+
+	if (cam->overlay_on == true)
+		stop_preview(cam);
+	if ((cam->capture_on == true) && cam->enc_disable) {
+		cam->enc_disable(cam);
+	}
+	camera_power(cam, false);
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the sensor back from a low power state.
+ * Refer to the document driver-model/driver.txt in the kernel source tree
+ * for more information.
+ *
+ * @param   pdev   the device structure
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxc_v4l2_resume(struct platform_device *pdev)
+{
+	cam_data *cam = platform_get_drvdata(pdev);
+
+	pr_debug("In MVC:mxc_v4l2_resume\n");
+
+	if (cam == NULL) {
+		return -1;
+	}
+
+	cam->low_power = false;
+	wake_up_interruptible(&cam->power_queue);
+	camera_power(cam, true);
+
+	if (cam->overlay_on == true)
+		start_preview(cam);
+	if (cam->capture_on == true)
+		mxc_streamon(cam);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_v4l2_driver = {
+	.driver = {
+		   .name = "mxc_v4l2_capture",
+		   },
+	.probe = mxc_v4l2_probe,
+	.remove = mxc_v4l2_remove,
+	.suspend = mxc_v4l2_suspend,
+	.resume = mxc_v4l2_resume,
+	.shutdown = NULL,
+};
+
+/*!
+ * Initializes the camera driver.
+ */
+static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
+{
+	cam_data *cam = slave->u.slave->master->priv;
+	struct v4l2_format cam_fmt;
+
+	pr_debug("In MVC: mxc_v4l2_master_attach\n");
+	pr_debug("   slave.name = %s\n", slave->name);
+	pr_debug("   master.name = %s\n", slave->u.slave->master->name);
+
+	cam->sensor = slave;
+	if (slave == NULL) {
+		pr_err("ERROR: v4l2 capture: slave parameter not valid.\n");
+		return -1;
+	}
+
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true);
+	vidioc_int_s_power(cam->sensor, 1);
+	vidioc_int_dev_init(slave);
+	ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false);
+	cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
+
+	/* Used to detect TV in (type 1) vs. camera (type 0)*/
+	cam->device_type = cam_fmt.fmt.pix.priv;
+
+	/* Set the input size to the ipu for this device */
+	cam->crop_bounds.top = cam->crop_bounds.left = 0;
+	cam->crop_bounds.width = cam_fmt.fmt.pix.width;
+	cam->crop_bounds.height = cam_fmt.fmt.pix.height;
+
+	/* This also is the max crop size for this device. */
+	cam->crop_defrect.top = cam->crop_defrect.left = 0;
+	cam->crop_defrect.width = cam_fmt.fmt.pix.width;
+	cam->crop_defrect.height = cam_fmt.fmt.pix.height;
+
+	/* At this point, this is also the current image size. */
+	cam->crop_current.top = cam->crop_current.left = 0;
+	cam->crop_current.width = cam_fmt.fmt.pix.width;
+	cam->crop_current.height = cam_fmt.fmt.pix.height;
+
+	pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
+		 __func__,
+		 cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
+	pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_bounds.width, cam->crop_bounds.height);
+	pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_defrect.width, cam->crop_defrect.height);
+	pr_debug("End of %s: crop_current widthxheight %d x %d\n",
+		 __func__,
+		 cam->crop_current.width, cam->crop_current.height);
+
+	return 0;
+}
+
+/*!
+ * Disconnects the camera driver.
+ */
+static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
+{
+	pr_debug("In MVC:mxc_v4l2_master_detach\n");
+	vidioc_int_dev_exit(slave);
+}
+
+/*!
+ * Entry point for the V4L2
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int camera_init(void)
+{
+	u8 err = 0;
+
+	pr_debug("In MVC:camera_init\n");
+
+	/* Register the device driver structure. */
+	err = platform_driver_register(&mxc_v4l2_driver);
+	if (err != 0) {
+		pr_err("ERROR: v4l2 capture:camera_init: "
+			"platform_driver_register failed.\n");
+		return err;
+	}
+
+	return err;
+}
+
+/*!
+ * Exit and cleanup for the V4L2
+ */
+static void __exit camera_exit(void)
+{
+	pr_debug("In MVC: camera_exit\n");
+
+	platform_driver_unregister(&mxc_v4l2_driver);
+}
+
+module_init(camera_init);
+module_exit(camera_exit);
+
+module_param(video_nr, int, 0444);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
new file mode 100644
index 000000000000..50f695102095
--- /dev/null
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver
+ */
+/*!
+ * @file mxc_v4l2_capture.h
+ *
+ * @brief mxc V4L2 capture device API  Header file
+ *
+ * It include all the defines for frame operations, also three structure defines
+ * use case ops structure, common v4l2 driver structure and frame structure.
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+#ifndef __MXC_V4L2_CAPTURE_H__
+#define __MXC_V4L2_CAPTURE_H__
+
+#include <asm/uaccess.h>
+#include <linux/list.h>
+#include <linux/smp_lock.h>
+#include <linux/ipu.h>
+#include <linux/mxc_v4l2.h>
+
+#include <media/v4l2-dev.h>
+
+#define FRAME_NUM 3
+
+/*!
+ * v4l2 frame structure.
+ */
+struct mxc_v4l_frame {
+	u32 paddress;
+	void *vaddress;
+	int count;
+	int width;
+	int height;
+
+	struct v4l2_buffer buffer;
+	struct list_head queue;
+	int index;
+};
+
+/* Only for old version.  Will go away soon. */
+typedef struct {
+	u8 clk_mode;
+	u8 ext_vsync;
+	u8 Vsync_pol;
+	u8 Hsync_pol;
+	u8 pixclk_pol;
+	u8 data_pol;
+	u8 data_width;
+	u8 pack_tight;
+	u8 force_eof;
+	u8 data_en_pol;
+	u16 width;
+	u16 height;
+	u32 pixel_fmt;
+	u32 mclk;
+	u16 active_width;
+	u16 active_height;
+} sensor_interface;
+
+/* Sensor control function */
+/* Only for old version.  Will go away soon. */
+struct camera_sensor {
+	void (*set_color) (int bright, int saturation, int red, int green,
+			   int blue);
+	void (*get_color) (int *bright, int *saturation, int *red, int *green,
+			   int *blue);
+	void (*set_ae_mode) (int ae_mode);
+	void (*get_ae_mode) (int *ae_mode);
+	sensor_interface *(*config) (int *frame_rate, int high_quality);
+	sensor_interface *(*reset) (void);
+	void (*get_std) (v4l2_std_id *std);
+	void (*set_std) (v4l2_std_id std);
+	unsigned int csi;
+};
+
+/*!
+ * common v4l2 driver structure.
+ */
+typedef struct _cam_data {
+	struct video_device *video_dev;
+	int device_type;
+
+	/* semaphore guard against SMP multithreading */
+	struct semaphore busy_lock;
+
+	int open_count;
+
+	/* params lock for this camera */
+	struct semaphore param_lock;
+
+	/* Encoder */
+	struct list_head ready_q;
+	struct list_head done_q;
+	struct list_head working_q;
+	int ping_pong_csi;
+	spinlock_t queue_int_lock;
+	spinlock_t dqueue_int_lock;
+	struct mxc_v4l_frame frame[FRAME_NUM];
+	struct mxc_v4l_frame dummy_frame;
+	int skip_frame;
+	wait_queue_head_t enc_queue;
+	int enc_counter;
+	dma_addr_t rot_enc_bufs[2];
+	void *rot_enc_bufs_vaddr[2];
+	int rot_enc_buf_size[2];
+	enum v4l2_buf_type type;
+
+	/* still image capture */
+	wait_queue_head_t still_queue;
+	int still_counter;
+	dma_addr_t still_buf[2];
+	void *still_buf_vaddr;
+
+	/* overlay */
+	struct v4l2_window win;
+	struct v4l2_framebuffer v4l2_fb;
+	dma_addr_t vf_bufs[2];
+	void *vf_bufs_vaddr[2];
+	int vf_bufs_size[2];
+	dma_addr_t rot_vf_bufs[2];
+	void *rot_vf_bufs_vaddr[2];
+	int rot_vf_buf_size[2];
+	bool overlay_active;
+	int output;
+	struct fb_info *overlay_fb;
+	int fb_origin_std;
+
+	/* v4l2 format */
+	struct v4l2_format v2f;
+	int rotation;	/* for IPUv1 and IPUv3, this means encoder rotation */
+	int vf_rotation; /* viewfinder rotation only for IPUv1 and IPUv3 */
+	struct v4l2_mxc_offset offset;
+
+	/* V4l2 control bit */
+	int bright;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+	/* standard */
+	struct v4l2_streamparm streamparm;
+	struct v4l2_standard standard;
+	bool standard_autodetect;
+
+	/* crop */
+	struct v4l2_rect crop_bounds;
+	struct v4l2_rect crop_defrect;
+	struct v4l2_rect crop_current;
+
+	int (*enc_update_eba) (dma_addr_t eba, int *bufferNum);
+	int (*enc_enable) (void *private);
+	int (*enc_disable) (void *private);
+	int (*enc_enable_csi) (void *private);
+	int (*enc_disable_csi) (void *private);
+	void (*enc_callback) (u32 mask, void *dev);
+	int (*vf_start_adc) (void *private);
+	int (*vf_stop_adc) (void *private);
+	int (*vf_start_sdc) (void *private);
+	int (*vf_stop_sdc) (void *private);
+	int (*vf_enable_csi) (void *private);
+	int (*vf_disable_csi) (void *private);
+	int (*csi_start) (void *private);
+	int (*csi_stop) (void *private);
+
+	/* misc status flag */
+	bool overlay_on;
+	bool capture_on;
+	int overlay_pid;
+	int capture_pid;
+	bool low_power;
+	wait_queue_head_t power_queue;
+	unsigned int csi;
+	int current_input;
+
+	/* camera sensor interface */
+	struct camera_sensor *cam_sensor; 	/* old version */
+	struct v4l2_int_device *sensor;
+} cam_data;
+
+#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) \
+			       || defined(CONFIG_VIDEO_MXC_CSI_CAMERA_MODULE) \
+			       || defined(CONFIG_VIDEO_MXC_CSI_CAMERA)
+void set_mclk_rate(uint32_t *p_mclk_freq);
+#else
+void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi);
+#endif
+#endif				/* __MXC_V4L2_CAPTURE_H__ */
diff --git a/drivers/media/video/mxc/capture/ov2640.c b/drivers/media/video/mxc/capture/ov2640.c
new file mode 100644
index 000000000000..c906925eca21
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ov2640.c
@@ -0,0 +1,1081 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ov2640.c
+ *
+ * @brief ov2640 camera driver functions
+ *
+ * @ingroup Camera
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/hardware.h>
+#include <media/v4l2-int-device.h>
+#include "mxc_v4l2_capture.h"
+
+#define MIN_FPS 5
+#define MAX_FPS 30
+#define DEFAULT_FPS 30
+
+#define OV2640_XCLK_MIN 6000000
+#define OV2640_XCLK_MAX 27000000
+
+/*
+enum ov2640_mode {
+	ov2640_mode_1600_1120,
+	ov2640_mode_800_600
+};
+*/
+
+struct reg_value {
+	u8 reg;
+	u8 value;
+	int delay_ms;
+};
+
+static struct reg_value ov2640_setting_1600_1120[] = {
+#ifdef CONFIG_MACH_MX25_3DS
+	{0xff, 0x01, 0}, {0x12, 0x80, 5}, {0xff, 0x00, 0}, {0x2c, 0xff, 0},
+	{0x2e, 0xdf, 0}, {0xff, 0x01, 0}, {0x3c, 0x32, 0}, {0x11, 0x00, 0},
+	{0x09, 0x02, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0},
+	{0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0},
+	{0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x02, 0},
+	{0x35, 0x58, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0},
+	{0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0},
+	{0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0},
+	{0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0},
+	{0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x61, 0x70, 0},
+	{0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, {0x28, 0x30, 0},
+	{0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 0x00, 0}, {0x70, 0x02, 0},
+	{0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0}, {0x5a, 0x57, 0},
+	{0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0}, {0xe5, 0x7f, 0},
+	{0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0xe0, 0x14, 0}, {0x76, 0xff, 0},
+	{0x33, 0xa0, 0}, {0x42, 0x20, 0}, {0x43, 0x18, 0}, {0x4c, 0x00, 0},
+	{0x87, 0xd0, 0}, {0x88, 0x3f, 0}, {0xd7, 0x01, 0}, {0xd9, 0x10, 0},
+	{0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, {0x7c, 0x00, 0},
+	{0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, {0x7d, 0x48, 0},
+	{0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, {0x7d, 0x0e, 0},
+	{0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, {0x91, 0x31, 0},
+	{0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, {0x91, 0x7e, 0},
+	{0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, {0x91, 0xa3, 0},
+	{0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, {0x91, 0xe8, 0},
+	{0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, {0x93, 0xe3, 0},
+	{0x93, 0x05, 0}, {0x93, 0x05, 0}, {0x93, 0x00, 0}, {0x93, 0x04, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x96, 0x00, 0},
+	{0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, {0x97, 0x0c, 0},
+	{0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, {0x97, 0x26, 0},
+	{0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, {0x97, 0x00, 0},
+	{0x97, 0x00, 0}, {0xc3, 0xed, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0},
+	{0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0},
+	{0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0},
+	{0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0},
+	{0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xc0, 0xc8, 0},
+	{0xc1, 0x96, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0},
+	{0x52, 0x2c, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0},
+	{0x57, 0x00, 0}, {0x5a, 0x90, 0}, {0x5b, 0x2c, 0}, {0x5c, 0x05, 0},
+	{0xc3, 0xed, 0}, {0x7f, 0x00, 0}, {0xda, 0x00, 0}, {0xe5, 0x1f, 0},
+	{0xe1, 0x77, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0},
+	{0xff, 0x00, 0}, {0xe0, 0x04, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0},
+	{0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x2c, 0},
+	{0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0},
+	{0x5a, 0x40, 0}, {0x5b, 0xf0, 0}, {0x5c, 0x01, 0}, {0xd3, 0x82, 0},
+	{0xe0, 0x00, 1000}
+#else
+	{0xff, 0x1, 0}, {0x12, 0x80, 1}, {0xff, 0, 0}, {0x2c, 0xff, 0},
+	{0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, {0x11, 0x01, 0},
+	{0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0},
+	{0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0},
+	{0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x82, 0},
+	{0x35, 0x88, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0},
+	{0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0},
+	{0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0},
+	{0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0},
+	{0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x0c, 0x3c, 0},
+	{0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, {0x60, 0x55, 0},
+	{0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0},
+	{0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 00, 0},
+	{0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0},
+	{0x5a, 0x57, 0}, {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0},
+	{0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0},
+	{0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0},
+	{0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0xd7, 0x03, 0},
+	{0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0},
+	{0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0},
+	{0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0},
+	{0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0},
+	{0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0},
+	{0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0},
+	{0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0},
+	{0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0},
+	{0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, {0x93, 0x00, 0},
+	{0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0},
+	{0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0},
+	{0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0},
+	{0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0},
+	{0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0},
+	{0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0},
+	{0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0},
+	{0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xa6, 0x00, 0},
+	{0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, {0xa7, 0x31, 0},
+	{0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0},
+	{0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0},
+	{0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0},
+	{0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0},
+	{0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x18, 0},
+	{0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0},
+	{0x5a, 0x90, 0}, {0x5b, 0x18, 0}, {0x5c, 0x05, 0}, {0xc3, 0xef, 0},
+	{0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0},
+	{0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0}
+#endif
+};
+
+static struct reg_value ov2640_setting_800_600[] = {
+#ifdef CONFIG_MACH_MX25_3DS
+	{0xff, 0x01, 0}, {0x12, 0x80, 5}, {0xff, 0x00, 0}, {0x2c, 0xff, 0},
+	{0x2e, 0xdf, 0}, {0xff, 0x01, 0}, {0x3c, 0x32, 0}, {0x11, 0x00, 0},
+	{0x09, 0x02, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0},
+	{0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0},
+	{0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x92, 0},
+	{0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0}, {0x23, 0x00, 0},
+	{0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0}, {0x07, 0xc0, 0},
+	{0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0},
+	{0x48, 0x00, 0}, {0x5b, 0x00, 0}, {0x42, 0x03, 0}, {0x4a, 0x81, 0},
+	{0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0},
+	{0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0}, {0x0c, 0x3c, 0},
+	{0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0},
+	{0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 0x00, 0},
+	{0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x12, 0x40, 0},
+	{0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0}, {0x1a, 0x4b, 0},
+	{0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0}, {0x50, 0xa8, 0},
+	{0x5a, 0x23, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0},
+	{0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0xe0, 0x14, 0},
+	{0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, {0x43, 0x18, 0},
+	{0x4c, 0x00, 0}, {0x87, 0xd5, 0}, {0x88, 0x3f, 0}, {0xd7, 0x01, 0},
+	{0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0},
+	{0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0},
+	{0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0},
+	{0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0},
+	{0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0},
+	{0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0},
+	{0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0},
+	{0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0},
+	{0x93, 0xe3, 0}, {0x93, 0x05, 0}, {0x93, 0x05, 0}, {0x93, 0x00, 0},
+	{0x93, 0x04, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0},
+	{0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0},
+	{0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0},
+	{0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xc3, 0xed, 0}, {0xa4, 0x00, 0},
+	{0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0},
+	{0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0},
+	{0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0},
+	{0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0},
+	{0xc0, 0x64, 0}, {0xc1, 0x4b, 0}, {0x8c, 0x00, 0}, {0x86, 0x3d, 0},
+	{0x50, 0x00, 0}, {0x51, 0xc8, 0}, {0x52, 0x96, 0}, {0x53, 0x00, 0},
+	{0x54, 0x00, 0}, {0x55, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0},
+	{0x5c, 0x00, 0}, {0xd3, 0x82, 0}, {0xc3, 0xed, 0}, {0x7f, 0x00, 0},
+	{0xda, 0x00, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0}, {0xe0, 0x00, 0},
+	{0xdd, 0x7f, 0}, {0x05, 0x00, 0}, {0xff, 0x00, 0}, {0xe0, 0x04, 0},
+	{0xc0, 0x64, 0}, {0xc1, 0x4b, 0}, {0x8c, 0x00, 0}, {0x86, 0x3d, 0},
+	{0x50, 0x00, 0}, {0x51, 0xc8, 0}, {0x52, 0x96, 0}, {0x53, 0x00, 0},
+	{0x54, 0x00, 0}, {0x55, 0x00, 0}, {0x5a, 0xa0, 0}, {0x5b, 0x78, 0},
+	{0x5c, 0x00, 0}, {0xd3, 0x82, 0}, {0xe0, 0x00, 1000}
+#else
+	{0xff, 0, 0}, {0xff, 1, 0}, {0x12, 0x80, 1}, {0xff, 00, 0},
+	{0x2c, 0xff, 0}, {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0},
+	{0x11, 0x01, 0}, {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0},
+	{0x14, 0x48, 0}, {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0},
+	{0x3b, 0xfb, 0}, {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0},
+	{0x39, 0x92, 0}, {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0},
+	{0x23, 0x00, 0}, {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0},
+	{0x07, 0xc0, 0}, {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0},
+	{0x4a, 0x81, 0}, {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0},
+	{0x26, 0x82, 0}, {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0},
+	{0x0c, 0x3c, 0}, {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0},
+	{0x60, 0x55, 0}, {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0},
+	{0x20, 0x80, 0}, {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0},
+	{0x6e, 00, 0}, {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0},
+	{0x12, 0x40, 0}, {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0},
+	{0x1a, 0x4b, 0}, {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0},
+	{0x50, 0xa8, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0},
+	{0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0},
+	{0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0},
+	{0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0x88, 0x3f, 0},
+	{0xd7, 0x03, 0}, {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0},
+	{0xc9, 0x80, 0}, {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0},
+	{0x7d, 0x48, 0}, {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0},
+	{0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0},
+	{0x91, 0x1a, 0}, {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0},
+	{0x91, 0x75, 0}, {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0},
+	{0x91, 0x96, 0}, {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0},
+	{0x91, 0xd7, 0}, {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0},
+	{0x93, 0x06, 0}, {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0},
+	{0x93, 0x00, 0}, {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0},
+	{0x93, 0x00, 0}, {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0},
+	{0x97, 0x02, 0}, {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0},
+	{0x97, 0x28, 0}, {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0},
+	{0x97, 0x80, 0}, {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0},
+	{0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0},
+	{0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0},
+	{0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0},
+	{0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0},
+	{0xa6, 0x00, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0},
+	{0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0},
+	{0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0},
+	{0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0},
+	{0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0x64, 0},
+	{0xc1, 0x4b, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0xc8, 0},
+	{0x52, 0x96, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x00, 0},
+	{0x57, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, {0x5c, 0x00, 0},
+	{0xc3, 0xef, 0}, {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0},
+	{0xe1, 0x67, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0}
+#endif
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+struct sensor {
+	const struct ov2640_platform_data *platform_data;
+	struct v4l2_int_device *v4l2_int_device;
+	struct i2c_client *i2c_client;
+	struct v4l2_pix_format pix;
+	struct v4l2_captureparm streamcap;
+	bool on;
+
+	/* control settings */
+	int brightness;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+	u32 csi;
+	u32 mclk;
+
+} ov2640_data;
+
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+static struct regulator *gpo_regulator;
+
+extern void gpio_sensor_active(void);
+extern void gpio_sensor_inactive(void);
+
+/* list of image formats supported by this sensor */
+/*
+const static struct v4l2_fmtdesc ov2640_formats[] = {
+	{
+		.description = "YUYV (YUV 4:2:2), packed",
+		.pixelformat = V4L2_PIX_FMT_UYVY,
+	},
+};
+ */
+
+static int ov2640_init_mode(struct sensor *s)
+{
+	int ret = -1;
+	struct reg_value *setting;
+	int i, num;
+
+	pr_debug("In ov2640:ov2640_init_mode capturemode is %d\n",
+		s->streamcap.capturemode);
+
+	if (s->streamcap.capturemode & V4L2_MODE_HIGHQUALITY) {
+		s->pix.width = 1600;
+		s->pix.height = 1120;
+		setting = ov2640_setting_1600_1120;
+		num = ARRAY_SIZE(ov2640_setting_1600_1120);
+	} else {
+		s->pix.width = 800;
+		s->pix.height = 600;
+		setting = ov2640_setting_800_600;
+		num = ARRAY_SIZE(ov2640_setting_800_600);
+	}
+
+	for (i = 0; i < num; i++) {
+		ret = i2c_smbus_write_byte_data(s->i2c_client,
+						setting[i].reg,
+						setting[i].value);
+		if (ret < 0) {
+			pr_err("write reg error: reg=%x, val=%x\n",
+			       setting[i].reg, setting[i].value);
+			return ret;
+		}
+		if (setting[i].delay_ms > 0)
+			msleep(setting[i].delay_ms);
+	}
+
+	return ret;
+}
+
+/* At present only support change to 15fps(only for SVGA mode) */
+static int ov2640_set_fps(struct sensor *s, int fps)
+{
+	int ret = 0;
+
+	if (i2c_smbus_write_byte_data(s->i2c_client, 0xff, 0x01) < 0) {
+		pr_err("in %s,change to sensor addr failed\n", __func__);
+		ret = -EPERM;
+	}
+
+	/* change the camera framerate to 15fps(only for SVGA mode) */
+	if (i2c_smbus_write_byte_data(s->i2c_client, 0x11, 0x01) < 0) {
+		pr_err("change camera to 15fps failed\n");
+		ret = -EPERM;
+	}
+
+	return ret;
+}
+
+static int ov2640_set_format(struct sensor *s, int format)
+{
+	int ret = 0;
+
+	if (i2c_smbus_write_byte_data(s->i2c_client, 0xff, 0x00) < 0)
+		ret = -EPERM;
+
+	if (format == V4L2_PIX_FMT_RGB565) {
+		/* set RGB565 format */
+		if (i2c_smbus_write_byte_data(s->i2c_client, 0xda, 0x08) < 0)
+			ret = -EPERM;
+
+		if (i2c_smbus_write_byte_data(s->i2c_client, 0xd7, 0x03) < 0)
+			ret = -EPERM;
+	} else if (format == V4L2_PIX_FMT_YUV420) {
+		/* set YUV420 format */
+		if (i2c_smbus_write_byte_data(s->i2c_client, 0xda, 0x00) < 0)
+			ret = -EPERM;
+
+		if (i2c_smbus_write_byte_data(s->i2c_client, 0xd7, 0x1b) < 0)
+			ret = -EPERM;
+	} else {
+		pr_debug("format not supported\n");
+	}
+
+	return ret;
+}
+
+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
+
+/*!
+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
+ * s: pointer to standard V4L2 device structure
+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
+ *
+ * Gets slave interface parameters.
+ * Calculates the required xclk value to support the requested
+ * clock parameters in p.  This value is returned in the p
+ * parameter.
+ *
+ * vidioc_int_g_ifparm returns platform-specific information about the
+ * interface settings used by the sensor.
+ *
+ * Given the image capture format in pix, the nominal frame period in
+ * timeperframe, calculate the required xclk frequency.
+ *
+ * Called on open.
+ */
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+	pr_debug("In ov2640:ioctl_g_ifparm\n");
+
+	if (s == NULL) {
+		pr_err("   ERROR!! no slave device set!\n");
+		return -1;
+	}
+
+	memset(p, 0, sizeof(*p));
+	p->u.bt656.clock_curr = ov2640_data.mclk;
+	p->if_type = V4L2_IF_TYPE_BT656;
+	p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+	p->u.bt656.clock_min = OV2640_XCLK_MIN;
+	p->u.bt656.clock_max = OV2640_XCLK_MAX;
+
+	return 0;
+}
+
+/*!
+ * Sets the camera power.
+ *
+ * s  pointer to the camera device
+ * on if 1, power is to be turned on.  0 means power is to be turned off
+ *
+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
+ * @s: pointer to standard V4L2 device structure
+ * @on: power state to which device is to be set
+ *
+ * Sets devices power state to requrested state, if possible.
+ * This is called on open, close, suspend and resume.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+	struct sensor *sensor = s->priv;
+
+	pr_debug("In ov2640:ioctl_s_power\n");
+
+	if (on && !sensor->on) {
+		gpio_sensor_active();
+		if (io_regulator)
+			if (regulator_enable(io_regulator) != 0)
+				return -EIO;
+		if (core_regulator)
+			if (regulator_enable(core_regulator) != 0)
+				return -EIO;
+		if (gpo_regulator)
+			if (regulator_enable(gpo_regulator) != 0)
+				return -EIO;
+		if (analog_regulator)
+			if (regulator_enable(analog_regulator) != 0)
+				return -EIO;
+	} else if (!on && sensor->on) {
+		if (analog_regulator)
+			regulator_disable(analog_regulator);
+		if (core_regulator)
+			regulator_disable(core_regulator);
+		if (io_regulator)
+			regulator_disable(io_regulator);
+		if (gpo_regulator)
+			regulator_disable(gpo_regulator);
+		gpio_sensor_inactive();
+	}
+
+	sensor->on = on;
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	struct sensor *sensor = s->priv;
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+	int ret = 0;
+
+	pr_debug("In ov2640:ioctl_g_parm\n");
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+		memset(a, 0, sizeof(*a));
+		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cparm->capability = sensor->streamcap.capability;
+		cparm->timeperframe = sensor->streamcap.timeperframe;
+		cparm->capturemode = sensor->streamcap.capturemode;
+		ret = 0;
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_err("   type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \
+			"but %d\n", a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_err("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible.  If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	struct sensor *sensor = s->priv;
+	struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
+	u32 tgt_fps;	/* target frames per secound */
+	int ret = 0;
+
+	pr_debug("In ov2640:ioctl_s_parm\n");
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		pr_debug("   type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+
+		/* Check that the new frame rate is allowed. */
+		if ((timeperframe->numerator == 0)
+		    || (timeperframe->denominator == 0)) {
+			timeperframe->denominator = DEFAULT_FPS;
+			timeperframe->numerator = 1;
+		}
+		tgt_fps = timeperframe->denominator
+			  / timeperframe->numerator;
+
+		if (tgt_fps > MAX_FPS) {
+			timeperframe->denominator = MAX_FPS;
+			timeperframe->numerator = 1;
+		} else if (tgt_fps < MIN_FPS) {
+			timeperframe->denominator = MIN_FPS;
+			timeperframe->numerator = 1;
+		}
+		sensor->streamcap.timeperframe = *timeperframe;
+		sensor->streamcap.capturemode =
+				(u32)a->parm.capture.capturemode;
+
+		ret = ov2640_init_mode(sensor);
+		if (tgt_fps == 15)
+			ov2640_set_fps(sensor, tgt_fps);
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_err("   type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \
+			"but %d\n", a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_err("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_fmt_cap - V4L2 sensor interface handler for ioctl_s_fmt_cap
+ * 		     set camera output format and resolution format
+ *
+ * @s: pointer to standard V4L2 device structure
+ * @arg: pointer to parameter, according this to set camera
+ *
+ * Returns 0 if set succeed, else return -1
+ */
+static int ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	struct sensor *sensor = s->priv;
+	u32 format = f->fmt.pix.pixelformat;
+	int size = 0, ret = 0;
+
+	size = f->fmt.pix.width * f->fmt.pix.height;
+	switch (format) {
+	case V4L2_PIX_FMT_RGB565:
+		if (size > 640 * 480)
+			sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY;
+		else
+			sensor->streamcap.capturemode = 0;
+		ret = ov2640_init_mode(sensor);
+
+		ret = ov2640_set_format(sensor, V4L2_PIX_FMT_RGB565);
+		break;
+	case V4L2_PIX_FMT_UYVY:
+		if (size > 640 * 480)
+			sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY;
+		else
+			sensor->streamcap.capturemode = 0;
+		ret = ov2640_init_mode(sensor);
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		if (size > 640 * 480)
+			sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY;
+		else
+			sensor->streamcap.capturemode = 0;
+		ret = ov2640_init_mode(sensor);
+
+		/* YUYV: width * 2, YY: width */
+		ret = ov2640_set_format(sensor, V4L2_PIX_FMT_YUV420);
+		break;
+	default:
+		pr_debug("case not supported\n");
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	struct sensor *sensor = s->priv;
+
+	pr_debug("In ov2640:ioctl_g_fmt_cap.\n");
+
+	f->fmt.pix = sensor->pix;
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array.  Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int ret = 0;
+
+	pr_debug("In ov2640:ioctl_g_ctrl\n");
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		vc->value = ov2640_data.brightness;
+		break;
+	case V4L2_CID_HUE:
+		vc->value = ov2640_data.hue;
+		break;
+	case V4L2_CID_CONTRAST:
+		vc->value = ov2640_data.contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		vc->value = ov2640_data.saturation;
+		break;
+	case V4L2_CID_RED_BALANCE:
+		vc->value = ov2640_data.red;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		vc->value = ov2640_data.blue;
+		break;
+	case V4L2_CID_EXPOSURE:
+		vc->value = ov2640_data.ae_mode;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array).  Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int retval = 0;
+
+	pr_debug("In ov2640:ioctl_s_ctrl %d\n", vc->id);
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		pr_debug("   V4L2_CID_BRIGHTNESS\n");
+		break;
+	case V4L2_CID_CONTRAST:
+		pr_debug("   V4L2_CID_CONTRAST\n");
+		break;
+	case V4L2_CID_SATURATION:
+		pr_debug("   V4L2_CID_SATURATION\n");
+		break;
+	case V4L2_CID_HUE:
+		pr_debug("   V4L2_CID_HUE\n");
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_AUTO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		pr_debug(
+			"   V4L2_CID_DO_WHITE_BALANCE\n");
+		break;
+	case V4L2_CID_RED_BALANCE:
+		pr_debug("   V4L2_CID_RED_BALANCE\n");
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		pr_debug("   V4L2_CID_BLUE_BALANCE\n");
+		break;
+	case V4L2_CID_GAMMA:
+		pr_debug("   V4L2_CID_GAMMA\n");
+		break;
+	case V4L2_CID_EXPOSURE:
+		pr_debug("   V4L2_CID_EXPOSURE\n");
+		break;
+	case V4L2_CID_AUTOGAIN:
+		pr_debug("   V4L2_CID_AUTOGAIN\n");
+		break;
+	case V4L2_CID_GAIN:
+		pr_debug("   V4L2_CID_GAIN\n");
+		break;
+	case V4L2_CID_HFLIP:
+		pr_debug("   V4L2_CID_HFLIP\n");
+		break;
+	case V4L2_CID_VFLIP:
+		pr_debug("   V4L2_CID_VFLIP\n");
+		break;
+	default:
+		pr_debug("   Default case\n");
+		retval = -EPERM;
+		break;
+	}
+
+	return retval;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+	pr_debug("In ov2640:ioctl_init\n");
+
+	return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+	struct sensor *sensor = s->priv;
+	u32 tgt_xclk;	/* target xclk */
+
+	pr_debug("In ov2640:ioctl_dev_init\n");
+
+	gpio_sensor_active();
+	ov2640_data.on = true;
+
+	tgt_xclk = ov2640_data.mclk;
+	tgt_xclk = min(tgt_xclk, (u32)OV2640_XCLK_MAX);
+	tgt_xclk = max(tgt_xclk, (u32)OV2640_XCLK_MIN);
+	ov2640_data.mclk = tgt_xclk;
+
+	pr_debug("   Setting mclk to %d MHz\n",
+		tgt_xclk / 1000000);
+	set_mclk_rate(&ov2640_data.mclk);
+
+	return ov2640_init_mode(sensor);
+}
+
+/*!
+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Delinitialise the device when slave detaches to the master.
+ */
+static int ioctl_dev_exit(struct v4l2_int_device *s)
+{
+	pr_debug("In ov2640:ioctl_dev_exit\n");
+
+	gpio_sensor_inactive();
+
+	return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module and links them to the
+ * enumeration.
+ */
+static struct v4l2_int_ioctl_desc ov2640_ioctl_desc[] = {
+	{vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init},
+	{vidioc_int_dev_exit_num, (v4l2_int_ioctl_func*)ioctl_dev_exit},
+	{vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power},
+	{vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm},
+/*	{vidioc_int_g_needs_reset_num,
+				(v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
+/*	{vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
+	{vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init},
+/*	{vidioc_int_enum_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
+/*	{vidioc_int_try_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
+	{vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap},
+	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_s_fmt_cap},
+	{vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm},
+	{vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm},
+/*	{vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */
+	{vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl},
+	{vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl},
+};
+
+static struct v4l2_int_slave ov2640_slave = {
+	.ioctls = ov2640_ioctl_desc,
+	.num_ioctls = ARRAY_SIZE(ov2640_ioctl_desc),
+};
+
+static struct v4l2_int_device ov2640_int_device = {
+	.module = THIS_MODULE,
+	.name = "ov2640",
+	.type = v4l2_int_type_slave,
+	.u = {
+		.slave = &ov2640_slave,
+		},
+};
+
+/*!
+ * ov2640 I2C attach function
+ * Function set in i2c_driver struct.
+ * Called by insmod ov2640_camera.ko.
+ *
+ * @param client            struct i2c_client*
+ * @return  Error code indicating success or failure
+ */
+static int ov2640_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int retval;
+	struct mxc_camera_platform_data *plat_data = client->dev.platform_data;
+
+	pr_debug("In ov2640_probe (RH_BT565)\n");
+
+	/* Set initial values for the sensor struct. */
+	memset(&ov2640_data, 0, sizeof(ov2640_data));
+	ov2640_data.i2c_client = client;
+	ov2640_data.mclk = 24000000;
+	ov2640_data.mclk = plat_data->mclk;
+	ov2640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
+	ov2640_data.pix.width = 800;
+	ov2640_data.pix.height = 600;
+	ov2640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY
+					   | V4L2_CAP_TIMEPERFRAME;
+	ov2640_data.streamcap.capturemode = 0;
+	ov2640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
+	ov2640_data.streamcap.timeperframe.numerator = 1;
+
+	if (plat_data->io_regulator) {
+		io_regulator =
+		    regulator_get(&client->dev, plat_data->io_regulator);
+		if (!IS_ERR(io_regulator)) {
+			regulator_set_voltage(io_regulator, 2800000, 2800000);
+			if (regulator_enable(io_regulator) != 0) {
+				pr_err("%s:io set voltage error\n", __func__);
+				goto err1;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:io set voltage ok\n", __func__);
+			}
+		} else
+			io_regulator = NULL;
+	}
+
+	if (plat_data->core_regulator) {
+		core_regulator =
+		    regulator_get(&client->dev, plat_data->core_regulator);
+		if (!IS_ERR(core_regulator)) {
+			regulator_set_voltage(core_regulator,
+					 1300000, 1300000);
+			if (regulator_enable(core_regulator) != 0) {
+				pr_err("%s:core set voltage error\n", __func__);
+				goto err2;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:core set voltage ok\n", __func__);
+			}
+		} else
+			core_regulator = NULL;
+	}
+
+	if (plat_data->analog_regulator) {
+		analog_regulator =
+		    regulator_get(&client->dev, plat_data->analog_regulator);
+		if (!IS_ERR(analog_regulator)) {
+			regulator_set_voltage(analog_regulator, 2000000, 2000000);
+			if (regulator_enable(analog_regulator) != 0) {
+				pr_err("%s:analog set voltage error\n",
+					 __func__);
+				goto err3;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:analog set voltage ok\n", __func__);
+			}
+		} else
+			analog_regulator = NULL;
+	}
+
+	if (plat_data->gpo_regulator) {
+		gpo_regulator =
+		    regulator_get(&client->dev, plat_data->gpo_regulator);
+		if (!IS_ERR(gpo_regulator)) {
+			if (regulator_enable(gpo_regulator) != 0) {
+				pr_err("%s:gpo3 set voltage error\n", __func__);
+				goto err4;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:gpo3 set voltage ok\n", __func__);
+			}
+		} else
+			gpo_regulator = NULL;
+	}
+
+	/* This function attaches this structure to the /dev/video0 device.
+	 * The pointer in priv points to the ov2640_data structure here.*/
+	ov2640_int_device.priv = &ov2640_data;
+	retval = v4l2_int_device_register(&ov2640_int_device);
+
+	return retval;
+
+err4:
+	if (analog_regulator) {
+		regulator_disable(analog_regulator);
+		regulator_put(analog_regulator);
+	}
+err3:
+	if (core_regulator) {
+		regulator_disable(core_regulator);
+		regulator_put(core_regulator);
+	}
+err2:
+	if (io_regulator) {
+		regulator_disable(io_regulator);
+		regulator_put(io_regulator);
+	}
+err1:
+	return -1;
+}
+
+/*!
+ * ov2640 I2C detach function
+ * Called on rmmod ov2640_camera.ko
+ *
+ * @param client            struct i2c_client*
+ * @return  Error code indicating success or failure
+ */
+static int ov2640_remove(struct i2c_client *client)
+{
+	pr_debug("In ov2640_remove\n");
+
+	v4l2_int_device_unregister(&ov2640_int_device);
+
+	if (gpo_regulator) {
+		regulator_disable(gpo_regulator);
+		regulator_put(gpo_regulator);
+	}
+
+	if (analog_regulator) {
+		regulator_disable(analog_regulator);
+		regulator_put(analog_regulator);
+	}
+
+	if (core_regulator) {
+		regulator_disable(core_regulator);
+		regulator_put(core_regulator);
+	}
+
+	if (io_regulator) {
+		regulator_disable(io_regulator);
+		regulator_put(io_regulator);
+	}
+
+	return 0;
+}
+
+static const struct i2c_device_id ov2640_id[] = {
+	{"ov2640", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, ov2640_id);
+
+static struct i2c_driver ov2640_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "ov2640",
+		  },
+	.probe = ov2640_probe,
+	.remove = ov2640_remove,
+	.id_table = ov2640_id,
+/* To add power management add .suspend and .resume functions */
+};
+
+/*!
+ * ov2640 init function
+ * Called by insmod ov2640_camera.ko.
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int ov2640_init(void)
+{
+	u8 err;
+
+	pr_debug("In ov2640_init\n");
+
+	err = i2c_add_driver(&ov2640_i2c_driver);
+	if (err != 0)
+		pr_err("%s:driver registration failed, error=%d \n",
+			__func__, err);
+
+	return err;
+}
+
+/*!
+ * OV2640 cleanup function
+ * Called on rmmod ov2640_camera.ko
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit ov2640_clean(void)
+{
+	pr_debug("In ov2640_clean\n");
+	i2c_del_driver(&ov2640_i2c_driver);
+}
+
+module_init(ov2640_init);
+module_exit(ov2640_clean);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("OV2640 Camera Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ov3640.c b/drivers/media/video/mxc/capture/ov3640.c
new file mode 100644
index 000000000000..899945b7d071
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ov3640.c
@@ -0,0 +1,1432 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <media/v4l2-int-device.h>
+#include "mxc_v4l2_capture.h"
+
+#define OV3640_VOLTAGE_ANALOG               2800000
+#define OV3640_VOLTAGE_DIGITAL_CORE         1500000
+#define OV3640_VOLTAGE_DIGITAL_IO           1800000
+#define OV3640_VOLTAGE_DIGITAL_GPO	    2800000
+
+/* Check these values! */
+#define MIN_FPS 15
+#define MAX_FPS 30
+#define DEFAULT_FPS 30
+
+#define OV3640_XCLK_MIN 6000000
+#define OV3640_XCLK_MAX 24000000
+
+enum ov3640_mode {
+	ov3640_mode_MIN = 0,
+	ov3640_mode_VGA_640_480 = 0,
+	ov3640_mode_QVGA_320_240 = 1,
+	ov3640_mode_XGA_1024_768 = 2,
+	ov3640_mode_QXGA_2048_1536 = 3,
+	ov3640_mode_NTSC_720_480 = 4,
+	ov3640_mode_PAL_720_576 = 5,
+	ov3640_mode_MAX = 5
+};
+
+enum ov3640_frame_rate {
+	ov3640_15_fps,
+	ov3640_30_fps
+};
+
+struct reg_value {
+	u16 u16RegAddr;
+	u8 u8Val;
+	u8 u8Mask;
+	u32 u32Delay_ms;
+};
+
+struct ov3640_mode_info {
+	enum ov3640_mode mode;
+	u32 width;
+	u32 height;
+	struct reg_value *init_data_ptr;
+	u32 init_data_size;
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+struct sensor {
+	const struct ov3640_platform_data *platform_data;
+	struct v4l2_int_device *v4l2_int_device;
+	struct i2c_client *i2c_client;
+	struct v4l2_pix_format pix;
+	struct v4l2_captureparm streamcap;
+	bool on;
+
+	/* control settings */
+	int brightness;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+	u32 mclk;
+	int csi;
+} ov3640_data;
+
+static struct reg_value ov3640_setting_15fps_QXGA_2048_1536[] = {
+#if 0
+	/* The true 15fps QXGA setting. */
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x41, 0, 0}, {0x3087, 0x16, 0, 0},
+	{0x30aa, 0x45, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x13, 0, 0}, {0x30d7, 0x10, 0, 0}, {0x309e, 0x00, 0, 0},
+	{0x3602, 0x26, 0, 0}, {0x3603, 0x4D, 0, 0}, {0x364c, 0x04, 0, 0},
+	{0x360c, 0x12, 0, 0}, {0x361e, 0x00, 0, 0}, {0x361f, 0x11, 0, 0},
+	{0x3633, 0x03, 0, 0}, {0x3629, 0x3c, 0, 0}, {0x300e, 0x33, 0, 0},
+	{0x300f, 0x21, 0, 0}, {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0},
+	{0x304c, 0x81, 0, 0}, {0x3029, 0x47, 0, 0}, {0x3070, 0x00, 0, 0},
+	{0x3071, 0xEC, 0, 0}, {0x301C, 0x06, 0, 0}, {0x3072, 0x00, 0, 0},
+	{0x3073, 0xC5, 0, 0}, {0x301D, 0x07, 0, 0}, {0x3018, 0x38, 0, 0},
+	{0x3019, 0x30, 0, 0}, {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0},
+	{0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x303c, 0x08, 0, 0},
+	{0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, {0x303F, 0x0c, 0, 0},
+	{0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0},
+	{0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0},
+	{0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, {0x3015, 0x12, 0, 0},
+	{0x3014, 0x04, 0, 0}, {0x3013, 0xf7, 0, 0}, {0x3104, 0x02, 0, 0},
+	{0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0},
+	{0x3308, 0xa5, 0, 0}, {0x3316, 0xff, 0, 0}, {0x3317, 0x00, 0, 0},
+	{0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x3300, 0x13, 0, 0},
+	{0x3301, 0xd6, 0, 0}, {0x3302, 0xef, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3304, 0x00, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x02, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
+	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
+	{0x3025, 0x18, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x0c, 0, 0},
+	{0x335f, 0x68, 0, 0}, {0x3360, 0x18, 0, 0}, {0x3361, 0x0c, 0, 0},
+	{0x3362, 0x68, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0},
+	{0x3403, 0x42, 0, 0}, {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0},
+	{0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3507, 0x06, 0, 0},
+	{0x350a, 0x4f, 0, 0}, {0x3600, 0xc4, 0, 0},
+#endif
+	/*
+	 * Only support 7.5fps for QXGA to workaround screen tearing issue
+	 * for 15fps when capturing still image.
+	 */
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0},
+	{0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0},
+	{0x3400, 0x00, 0, 0}, {0x3404, 0x02, 0, 0}, {0x3600, 0xc4, 0, 0},
+	{0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0},
+	{0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0},
+};
+
+static struct reg_value ov3640_setting_15fps_XGA_1024_768[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0},
+	{0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0},
+	{0x3400, 0x01, 0, 0}, {0x3404, 0x1d, 0, 0}, {0x3600, 0xc4, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
+	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
+	{0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0},
+	{0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0},
+	{0x3362, 0x34, 0, 0}, {0x3363, 0x00, 0, 0}, {0x3364, 0x00, 0, 0},
+	{0x3403, 0x00, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0},
+	{0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x307c, 0x10, 0, 0},
+	{0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0},
+	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0},
+};
+
+static struct reg_value ov3640_setting_30fps_XGA_1024_768[] = {
+	{0x0, 0x0, 0}
+};
+
+static struct reg_value ov3640_setting_15fps_VGA_640_480[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0},
+	{0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0},
+	{0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
+	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
+	{0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0},
+	{0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0},
+	{0x3362, 0x12, 0, 0}, {0x3363, 0x80, 0, 0}, {0x3364, 0xe0, 0, 0},
+	{0x3403, 0x00, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0},
+	{0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x307c, 0x10, 0, 0},
+	{0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0},
+	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x00, 0, 0},
+};
+
+static struct reg_value ov3640_setting_30fps_VGA_640_480[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0},
+	{0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0},
+	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0},
+	{0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0},
+	{0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0},
+	{0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0},
+	{0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0},
+	{0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0},
+	{0x3362, 0x12, 0, 0}, {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0},
+	{0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0},
+	{0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x3362, 0x12, 0, 0},
+	{0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0},
+	{0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0},
+	{0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0},
+	{0x3014, 0x04, 0, 0}, {0x3015, 0x02, 0, 0}, {0x302e, 0x00, 0, 0},
+	{0x302d, 0x00, 0, 0},
+};
+
+static struct reg_value ov3640_setting_15fps_QVGA_320_240[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0},
+	{0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0},
+	{0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0},
+	{0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0},
+	{0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0},
+	{0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0},
+	{0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0},
+	{0x3362, 0x01, 0, 0}, {0x3363, 0x40, 0, 0}, {0x3364, 0xf0, 0, 0},
+	{0x3403, 0x00, 0, 0}, {0x3088, 0x01, 0, 0}, {0x3089, 0x40, 0, 0},
+	{0x308a, 0x00, 0, 0}, {0x308b, 0xf0, 0, 0}, {0x307c, 0x10, 0, 0},
+	{0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0},
+	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0},
+};
+
+static struct reg_value ov3640_setting_30fps_QVGA_320_240[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0},
+	{0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0},
+	{0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0},
+	{0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0},
+	{0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0},
+	{0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0},
+	{0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0},
+	{0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0},
+	{0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0},
+	{0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0},
+	{0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0},
+	{0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0},
+	{0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0},
+	{0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0},
+	{0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0},
+	{0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0},
+	{0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0},
+	{0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0},
+	{0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0},
+	{0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0},
+	{0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0},
+	{0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0},
+	{0x3362, 0x34, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0},
+	{0x3403, 0x42, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0},
+	{0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3362, 0x12, 0, 0},
+	{0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0},
+	{0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0},
+	{0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0},
+};
+
+static struct reg_value ov3640_setting_15fps_NTSC_720_480[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0},
+	{0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0},
+	{0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0},
+	{0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0},
+	{0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0},
+	{0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0},
+	{0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0},
+	{0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0},
+	{0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0},
+	{0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0},
+	{0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0},
+	{0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0},
+	{0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0},
+	{0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0},
+	{0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0},
+	{0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0},
+	{0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0},
+	{0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0},
+	{0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0},
+	{0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0},
+	{0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0},
+	{0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0},
+	{0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0},
+	{0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0},
+	{0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0},
+	{0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0},
+	{0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0},
+	{0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0},
+	{0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0},
+	{0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0},
+	{0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0},
+	{0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0},
+	{0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0},
+	{0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0},
+	{0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0},
+	{0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0},
+	{0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0},
+	{0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0},
+	{0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0},
+	{0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0},
+	{0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0},
+	{0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0},
+	{0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0},
+	{0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0},
+	{0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0},
+	{0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0},
+	{0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0},
+	{0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0},
+	{0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0},
+	{0x3089, 0xD0, 0, 0}, {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0},
+	{0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x302e, 0x00, 0, 0},
+	{0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, {0x301C, 0x02, 0, 0},
+	{0x3404, 0x02, 0, 0},
+};
+
+static struct reg_value ov3640_setting_15fps_PAL_720_576[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0},
+	{0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0},
+	{0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0},
+	{0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0},
+	{0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0},
+	{0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0},
+	{0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0},
+	{0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0},
+	{0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0},
+	{0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0},
+	{0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0},
+	{0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0},
+	{0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0},
+	{0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0},
+	{0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0},
+	{0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0},
+	{0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0},
+	{0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0},
+	{0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0},
+	{0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0},
+	{0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0},
+	{0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0},
+	{0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0},
+	{0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0},
+	{0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0},
+	{0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0},
+	{0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0},
+	{0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0},
+	{0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0},
+	{0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0},
+	{0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0},
+	{0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0},
+	{0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0},
+	{0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0},
+	{0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0},
+	{0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0},
+	{0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0},
+	{0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0},
+	{0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0},
+	{0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0},
+	{0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0},
+	{0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0},
+	{0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0},
+	{0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0},
+	{0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0},
+	{0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0},
+	{0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0},
+	{0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0},
+	{0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0},
+	{0x3089, 0xD0, 0, 0}, {0x308a, 0x02, 0, 0}, {0x308b, 0x40, 0, 0},
+	{0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x302e, 0x00, 0, 0},
+	{0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, {0x301C, 0x02, 0, 0},
+	{0x3404, 0x02, 0, 0},
+};
+
+static struct reg_value ov3640_setting_30fps_NTSC_720_480[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0},
+	{0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0},
+	{0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0},
+	{0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0},
+	{0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0},
+	{0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0},
+	{0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0},
+	{0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0},
+	{0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0},
+	{0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0},
+	{0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0},
+	{0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0},
+	{0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0},
+	{0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0},
+	{0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0},
+	{0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0},
+	{0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0},
+	{0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0},
+	{0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0},
+	{0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0},
+	{0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0},
+	{0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0},
+	{0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0},
+	{0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0},
+	{0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0},
+	{0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0},
+	{0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0},
+	{0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0},
+	{0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0},
+	{0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0},
+	{0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0},
+	{0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0},
+	{0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0},
+	{0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0},
+	{0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0},
+	{0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0},
+	{0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0},
+	{0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0},
+	{0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0},
+	{0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0},
+	{0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0},
+	{0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0},
+	{0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0},
+	{0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0},
+	{0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0},
+	{0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0},
+	{0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0},
+	{0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0},
+	{0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0},
+	{0x3089, 0xD0, 0, 0}, {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0},
+	{0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0xA1, 0, 0},
+	{0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x3014, 0x84, 0, 0},
+	{0x302e, 0x00, 0, 0}, {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0},
+	{0x301C, 0x02, 0, 0}, {0x3404, 0x02, 0, 0},
+};
+
+static struct reg_value ov3640_setting_30fps_PAL_720_576[] = {
+	{0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0},
+	{0x3086, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0},
+	{0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0},
+	{0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0},
+	{0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0},
+	{0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0},
+	{0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0},
+	{0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0},
+	{0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0},
+	{0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0},
+	{0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0},
+	{0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0},
+	{0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0},
+	{0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0},
+	{0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0},
+	{0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0},
+	{0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0},
+	{0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0},
+	{0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0},
+	{0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0},
+	{0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0},
+	{0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0},
+	{0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0},
+	{0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0},
+	{0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0},
+	{0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0},
+	{0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0},
+	{0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0},
+	{0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0},
+	{0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0},
+	{0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0},
+	{0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0},
+	{0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0},
+	{0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0},
+	{0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0},
+	{0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0},
+	{0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0},
+	{0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0},
+	{0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0},
+	{0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0},
+	{0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0},
+	{0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0},
+	{0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0},
+	{0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0},
+	{0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0},
+	{0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0},
+	{0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0},
+	{0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0},
+	{0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0},
+	{0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0},
+	{0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0},
+	{0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0},
+	{0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0},
+	{0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0},
+	{0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0},
+	{0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0},
+	{0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0},
+	{0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0},
+	{0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0},
+	{0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0},
+	{0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0},
+	{0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0},
+	{0x3089, 0xD0, 0, 0}, {0x308a, 0x02, 0, 0}, {0x308b, 0x40, 0, 0},
+	{0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0xA1, 0, 0},
+	{0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x3014, 0x84, 0, 0},
+	{0x302e, 0x00, 0, 0}, {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0},
+	{0x301C, 0x02, 0, 0}, {0x3404, 0x02, 0, 0},
+};
+
+static struct ov3640_mode_info ov3640_mode_info_data[2][ov3640_mode_MAX + 1] = {
+	{
+		{ov3640_mode_VGA_640_480,    640,  480,
+		ov3640_setting_15fps_VGA_640_480,
+		ARRAY_SIZE(ov3640_setting_15fps_VGA_640_480)},
+		{ov3640_mode_QVGA_320_240,   320,  240,
+		ov3640_setting_15fps_QVGA_320_240,
+		ARRAY_SIZE(ov3640_setting_15fps_QVGA_320_240)},
+		{ov3640_mode_XGA_1024_768,   1024, 768,
+		ov3640_setting_15fps_XGA_1024_768,
+		ARRAY_SIZE(ov3640_setting_15fps_XGA_1024_768)},
+		{ov3640_mode_QXGA_2048_1536, 2048, 1536,
+		ov3640_setting_15fps_QXGA_2048_1536,
+		ARRAY_SIZE(ov3640_setting_15fps_QXGA_2048_1536)},
+		{ov3640_mode_NTSC_720_480,   720, 480,
+		ov3640_setting_15fps_NTSC_720_480,
+		ARRAY_SIZE(ov3640_setting_15fps_NTSC_720_480)},
+		{ov3640_mode_PAL_720_576,    720, 576,
+		ov3640_setting_15fps_PAL_720_576,
+		ARRAY_SIZE(ov3640_setting_15fps_PAL_720_576)},
+	},
+	{
+		{ov3640_mode_VGA_640_480,    640,  480,
+		ov3640_setting_30fps_VGA_640_480,
+		ARRAY_SIZE(ov3640_setting_30fps_VGA_640_480)},
+		{ov3640_mode_QVGA_320_240,   320,  240,
+		ov3640_setting_30fps_QVGA_320_240,
+		ARRAY_SIZE(ov3640_setting_30fps_QVGA_320_240)},
+		{ov3640_mode_XGA_1024_768,   1024, 768,
+		ov3640_setting_30fps_XGA_1024_768,
+		ARRAY_SIZE(ov3640_setting_30fps_XGA_1024_768)},
+		{ov3640_mode_QXGA_2048_1536, 0, 0, NULL, 0},
+		{ov3640_mode_NTSC_720_480,   720, 480,
+		ov3640_setting_30fps_NTSC_720_480,
+		ARRAY_SIZE(ov3640_setting_30fps_NTSC_720_480)},
+		{ov3640_mode_PAL_720_576,    720, 576,
+		ov3640_setting_30fps_PAL_720_576,
+		ARRAY_SIZE(ov3640_setting_30fps_PAL_720_576)},
+	},
+};
+
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+static struct regulator *gpo_regulator;
+static struct mxc_camera_platform_data *camera_plat;
+
+static int ov3640_probe(struct i2c_client *adapter,
+				const struct i2c_device_id *device_id);
+static int ov3640_remove(struct i2c_client *client);
+
+static s32 ov3640_read_reg(u16 reg, u8 *val);
+static s32 ov3640_write_reg(u16 reg, u8 val);
+
+static const struct i2c_device_id ov3640_id[] = {
+	{"ov3640", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, ov3640_id);
+
+static struct i2c_driver ov3640_i2c_driver = {
+	.driver = {
+		  .owner = THIS_MODULE,
+		  .name  = "ov3640",
+		  },
+	.probe  = ov3640_probe,
+	.remove = ov3640_remove,
+	.id_table = ov3640_id,
+};
+
+extern void gpio_sensor_active(unsigned int csi_index);
+extern void gpio_sensor_inactive(unsigned int csi);
+
+static s32 ov3640_write_reg(u16 reg, u8 val)
+{
+	u8 au8Buf[3] = {0};
+
+	au8Buf[0] = reg >> 8;
+	au8Buf[1] = reg & 0xff;
+	au8Buf[2] = val;
+
+	if (i2c_master_send(ov3640_data.i2c_client, au8Buf, 3) < 0) {
+		pr_err("%s:write reg error:reg=%x,val=%x\n",
+			__func__, reg, val);
+		return -1;
+	}
+
+	return 0;
+}
+
+static s32 ov3640_read_reg(u16 reg, u8 *val)
+{
+	u8 au8RegBuf[2] = {0};
+	u8 u8RdVal = 0;
+
+	au8RegBuf[0] = reg >> 8;
+	au8RegBuf[1] = reg & 0xff;
+
+	if (2 != i2c_master_send(ov3640_data.i2c_client, au8RegBuf, 2)) {
+		pr_err("%s:write reg error:reg=%x\n",
+				__func__, reg);
+		return -1;
+	}
+
+	if (1 != i2c_master_recv(ov3640_data.i2c_client, &u8RdVal, 1)) {
+		pr_err("%s:read reg error:reg=%x,val=%x\n",
+				__func__, reg, u8RdVal);
+		return -1;
+	}
+
+	*val = u8RdVal;
+
+	return u8RdVal;
+}
+
+static int ov3640_init_mode(enum ov3640_frame_rate frame_rate,
+			    enum ov3640_mode mode)
+{
+	struct reg_value *pModeSetting = NULL;
+	s32 i = 0;
+	s32 iModeSettingArySize = 0;
+	register u32 Delay_ms = 0;
+	register u16 RegAddr = 0;
+	register u8 Mask = 0;
+	register u8 Val = 0;
+	u8 RegVal = 0;
+	int retval = 0;
+
+	if (mode > ov3640_mode_MAX || mode < ov3640_mode_MIN) {
+		pr_err("Wrong ov3640 mode detected!\n");
+		return -1;
+	}
+
+	pModeSetting = ov3640_mode_info_data[frame_rate][mode].init_data_ptr;
+	iModeSettingArySize =
+		ov3640_mode_info_data[frame_rate][mode].init_data_size;
+
+	ov3640_data.pix.width = ov3640_mode_info_data[frame_rate][mode].width;
+	ov3640_data.pix.height = ov3640_mode_info_data[frame_rate][mode].height;
+
+	for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
+		Delay_ms = pModeSetting->u32Delay_ms;
+		RegAddr = pModeSetting->u16RegAddr;
+		Val = pModeSetting->u8Val;
+		Mask = pModeSetting->u8Mask;
+
+		if (Mask) {
+			retval = ov3640_read_reg(RegAddr, &RegVal);
+			if (retval < 0)
+				goto err;
+
+			RegVal &= ~(u8)Mask;
+			Val &= Mask;
+			Val |= RegVal;
+		}
+
+		retval = ov3640_write_reg(RegAddr, Val);
+		if (retval < 0)
+			goto err;
+
+		if (Delay_ms)
+			msleep(Delay_ms);
+	}
+err:
+	return retval;
+}
+
+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
+
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+	if (s == NULL) {
+		pr_err("   ERROR!! no slave device set!\n");
+		return -1;
+	}
+
+	memset(p, 0, sizeof(*p));
+	p->u.bt656.clock_curr = ov3640_data.mclk;
+	pr_debug("   clock_curr=mclk=%d\n", ov3640_data.mclk);
+	p->if_type = V4L2_IF_TYPE_BT656;
+	p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+	p->u.bt656.clock_min = OV3640_XCLK_MIN;
+	p->u.bt656.clock_max = OV3640_XCLK_MAX;
+	p->u.bt656.bt_sync_correct = 1;  /* Indicate external vsync */
+
+	return 0;
+}
+
+/*!
+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @on: indicates power mode (on or off)
+ *
+ * Turns the power on or off, depending on the value of on and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+	struct sensor *sensor = s->priv;
+
+	if (on && !sensor->on) {
+		gpio_sensor_active(ov3640_data.csi);
+		if (io_regulator)
+			if (regulator_enable(io_regulator) != 0)
+				return -EIO;
+		if (core_regulator)
+			if (regulator_enable(core_regulator) != 0)
+				return -EIO;
+		if (gpo_regulator)
+			if (regulator_enable(gpo_regulator) != 0)
+				return -EIO;
+		if (analog_regulator)
+			if (regulator_enable(analog_regulator) != 0)
+				return -EIO;
+		/* Make sure power on */
+		if (camera_plat->pwdn)
+			camera_plat->pwdn(0);
+
+	} else if (!on && sensor->on) {
+		if (analog_regulator)
+			regulator_disable(analog_regulator);
+		if (core_regulator)
+			regulator_disable(core_regulator);
+		if (io_regulator)
+			regulator_disable(io_regulator);
+		if (gpo_regulator)
+			regulator_disable(gpo_regulator);
+		gpio_sensor_inactive(ov3640_data.csi);
+	}
+
+	sensor->on = on;
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	struct sensor *sensor = s->priv;
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+	int ret = 0;
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		memset(a, 0, sizeof(*a));
+		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cparm->capability = sensor->streamcap.capability;
+		cparm->timeperframe = sensor->streamcap.timeperframe;
+		cparm->capturemode = sensor->streamcap.capturemode;
+		ret = 0;
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_debug("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible.  If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+	struct sensor *sensor = s->priv;
+	struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
+	u32 tgt_fps;	/* target frames per secound */
+	enum ov3640_frame_rate frame_rate;
+	int ret = 0;
+
+	/* Make sure power on */
+	if (camera_plat->pwdn)
+		camera_plat->pwdn(0);
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		/* Check that the new frame rate is allowed. */
+		if ((timeperframe->numerator == 0) ||
+		    (timeperframe->denominator == 0)) {
+			timeperframe->denominator = DEFAULT_FPS;
+			timeperframe->numerator = 1;
+		}
+
+		tgt_fps = timeperframe->denominator /
+			  timeperframe->numerator;
+
+		if (tgt_fps > MAX_FPS) {
+			timeperframe->denominator = MAX_FPS;
+			timeperframe->numerator = 1;
+		} else if (tgt_fps < MIN_FPS) {
+			timeperframe->denominator = MIN_FPS;
+			timeperframe->numerator = 1;
+		}
+
+		/* Actual frame rate we use */
+		tgt_fps = timeperframe->denominator /
+			  timeperframe->numerator;
+
+		if (tgt_fps == 15)
+			frame_rate = ov3640_15_fps;
+		else if (tgt_fps == 30)
+			frame_rate = ov3640_30_fps;
+		else {
+			pr_err(" The camera frame rate is not supported!\n");
+			return -EINVAL;
+		}
+
+		sensor->streamcap.timeperframe = *timeperframe;
+		sensor->streamcap.capturemode =
+				(u32)a->parm.capture.capturemode;
+
+		ret = ov3640_init_mode(frame_rate,
+				       sensor->streamcap.capturemode);
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_debug("   type is not " \
+			"V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
+			a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_debug("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+	struct sensor *sensor = s->priv;
+
+	f->fmt.pix = sensor->pix;
+
+	return 0;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array.  Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int ret = 0;
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		vc->value = ov3640_data.brightness;
+		break;
+	case V4L2_CID_HUE:
+		vc->value = ov3640_data.hue;
+		break;
+	case V4L2_CID_CONTRAST:
+		vc->value = ov3640_data.contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		vc->value = ov3640_data.saturation;
+		break;
+	case V4L2_CID_RED_BALANCE:
+		vc->value = ov3640_data.red;
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		vc->value = ov3640_data.blue;
+		break;
+	case V4L2_CID_EXPOSURE:
+		vc->value = ov3640_data.ae_mode;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array).  Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+	int retval = 0;
+
+	pr_debug("In ov3640:ioctl_s_ctrl %d\n",
+		 vc->id);
+
+	switch (vc->id) {
+	case V4L2_CID_BRIGHTNESS:
+		break;
+	case V4L2_CID_CONTRAST:
+		break;
+	case V4L2_CID_SATURATION:
+		break;
+	case V4L2_CID_HUE:
+		break;
+	case V4L2_CID_AUTO_WHITE_BALANCE:
+		break;
+	case V4L2_CID_DO_WHITE_BALANCE:
+		break;
+	case V4L2_CID_RED_BALANCE:
+		break;
+	case V4L2_CID_BLUE_BALANCE:
+		break;
+	case V4L2_CID_GAMMA:
+		break;
+	case V4L2_CID_EXPOSURE:
+		break;
+	case V4L2_CID_AUTOGAIN:
+		break;
+	case V4L2_CID_GAIN:
+		break;
+	case V4L2_CID_HFLIP:
+		break;
+	case V4L2_CID_VFLIP:
+		break;
+	default:
+		retval = -EPERM;
+		break;
+	}
+
+	return retval;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+
+	return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+	struct sensor *sensor = s->priv;
+	u32 tgt_xclk;	/* target xclk */
+	u32 tgt_fps;	/* target frames per secound */
+	enum ov3640_frame_rate frame_rate;
+
+	gpio_sensor_active(ov3640_data.csi);
+	ov3640_data.on = true;
+
+	/* mclk */
+	tgt_xclk = ov3640_data.mclk;
+	tgt_xclk = min(tgt_xclk, (u32)OV3640_XCLK_MAX);
+	tgt_xclk = max(tgt_xclk, (u32)OV3640_XCLK_MIN);
+	ov3640_data.mclk = tgt_xclk;
+
+	pr_debug("   Setting mclk to %d MHz\n", tgt_xclk / 1000000);
+	set_mclk_rate(&ov3640_data.mclk, ov3640_data.csi);
+
+	/* Default camera frame rate is set in probe */
+	tgt_fps = sensor->streamcap.timeperframe.denominator /
+		  sensor->streamcap.timeperframe.numerator;
+
+	if (tgt_fps == 15)
+		frame_rate = ov3640_15_fps;
+	else if (tgt_fps == 30)
+		frame_rate = ov3640_30_fps;
+	else
+		return -EINVAL; /* Only support 15fps or 30fps now. */
+
+	return ov3640_init_mode(frame_rate,
+				sensor->streamcap.capturemode);
+}
+
+/*!
+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Delinitialise the device when slave detaches to the master.
+ */
+static int ioctl_dev_exit(struct v4l2_int_device *s)
+{
+	gpio_sensor_inactive(ov3640_data.csi);
+
+	return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module and links them to the
+ * enumeration.
+ */
+static struct v4l2_int_ioctl_desc ov3640_ioctl_desc[] = {
+	{vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init},
+	{vidioc_int_dev_exit_num, ioctl_dev_exit},
+	{vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power},
+	{vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm},
+/*	{vidioc_int_g_needs_reset_num,
+				(v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
+/*	{vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
+	{vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init},
+/*	{vidioc_int_enum_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
+/*	{vidioc_int_try_fmt_cap_num,
+				(v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
+	{vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap},
+/*	{vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+	{vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm},
+	{vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm},
+/*	{vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */
+	{vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl},
+	{vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl},
+};
+
+static struct v4l2_int_slave ov3640_slave = {
+	.ioctls = ov3640_ioctl_desc,
+	.num_ioctls = ARRAY_SIZE(ov3640_ioctl_desc),
+};
+
+static struct v4l2_int_device ov3640_int_device = {
+	.module = THIS_MODULE,
+	.name = "ov3640",
+	.type = v4l2_int_type_slave,
+	.u = {
+		.slave = &ov3640_slave,
+	},
+};
+
+/*!
+ * ov3640 I2C probe function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  Error code indicating success or failure
+ */
+static int ov3640_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int retval;
+	struct mxc_camera_platform_data *plat_data = client->dev.platform_data;
+
+	/* Set initial values for the sensor struct. */
+	memset(&ov3640_data, 0, sizeof(ov3640_data));
+	ov3640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */
+	ov3640_data.mclk = plat_data->mclk;
+	ov3640_data.csi = plat_data->csi;
+
+	ov3640_data.i2c_client = client;
+	ov3640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
+	ov3640_data.pix.width = 640;
+	ov3640_data.pix.height = 480;
+	ov3640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
+					   V4L2_CAP_TIMEPERFRAME;
+	ov3640_data.streamcap.capturemode = 0;
+	ov3640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
+	ov3640_data.streamcap.timeperframe.numerator = 1;
+
+	if (plat_data->io_regulator) {
+		io_regulator = regulator_get(&client->dev,
+					     plat_data->io_regulator);
+		if (!IS_ERR(io_regulator)) {
+			regulator_set_voltage(io_regulator,
+					      OV3640_VOLTAGE_DIGITAL_IO,
+					      OV3640_VOLTAGE_DIGITAL_IO);
+			if (regulator_enable(io_regulator) != 0) {
+				pr_err("%s:io set voltage error\n", __func__);
+				goto err1;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:io set voltage ok\n", __func__);
+			}
+		} else
+			io_regulator = NULL;
+	}
+
+	if (plat_data->core_regulator) {
+		core_regulator = regulator_get(&client->dev,
+					       plat_data->core_regulator);
+		if (!IS_ERR(core_regulator)) {
+			regulator_set_voltage(core_regulator,
+					      OV3640_VOLTAGE_DIGITAL_CORE,
+					      OV3640_VOLTAGE_DIGITAL_CORE);
+			if (regulator_enable(core_regulator) != 0) {
+				pr_err("%s:core set voltage error\n", __func__);
+				goto err2;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:core set voltage ok\n", __func__);
+			}
+		} else
+			core_regulator = NULL;
+	}
+
+	if (plat_data->analog_regulator) {
+		analog_regulator = regulator_get(&client->dev,
+						 plat_data->analog_regulator);
+		if (!IS_ERR(analog_regulator)) {
+			regulator_set_voltage(analog_regulator,
+					      OV3640_VOLTAGE_ANALOG,
+					      OV3640_VOLTAGE_ANALOG);
+			if (regulator_enable(analog_regulator) != 0) {
+				pr_err("%s:analog set voltage error\n",
+					__func__);
+				goto err3;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:analog set voltage ok\n", __func__);
+			}
+		} else
+			analog_regulator = NULL;
+	}
+
+	if (plat_data->gpo_regulator) {
+		gpo_regulator = regulator_get(&client->dev,
+					      plat_data->gpo_regulator);
+		if (!IS_ERR(gpo_regulator)) {
+			regulator_set_voltage(gpo_regulator,
+					      OV3640_VOLTAGE_DIGITAL_GPO,
+					      OV3640_VOLTAGE_DIGITAL_GPO);
+			if (regulator_enable(gpo_regulator) != 0) {
+				pr_err("%s:gpo enable error\n", __func__);
+				goto err4;
+			} else {
+				dev_dbg(&client->dev,
+					"%s:gpo enable ok\n", __func__);
+			}
+		} else
+			gpo_regulator = NULL;
+	}
+
+	if (plat_data->pwdn)
+		plat_data->pwdn(0);
+
+	camera_plat = plat_data;
+
+	ov3640_int_device.priv = &ov3640_data;
+	retval = v4l2_int_device_register(&ov3640_int_device);
+
+	return retval;
+
+err4:
+	if (analog_regulator) {
+		regulator_disable(analog_regulator);
+		regulator_put(analog_regulator);
+	}
+err3:
+	if (core_regulator) {
+		regulator_disable(core_regulator);
+		regulator_put(core_regulator);
+	}
+err2:
+	if (io_regulator) {
+		regulator_disable(io_regulator);
+		regulator_put(io_regulator);
+	}
+err1:
+	return -1;
+}
+
+/*!
+ * ov3640 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int ov3640_remove(struct i2c_client *client)
+{
+	v4l2_int_device_unregister(&ov3640_int_device);
+
+	if (gpo_regulator) {
+		regulator_disable(gpo_regulator);
+		regulator_put(gpo_regulator);
+	}
+
+	if (analog_regulator) {
+		regulator_disable(analog_regulator);
+		regulator_put(analog_regulator);
+	}
+
+	if (core_regulator) {
+		regulator_disable(core_regulator);
+		regulator_put(core_regulator);
+	}
+
+	if (io_regulator) {
+		regulator_disable(io_regulator);
+		regulator_put(io_regulator);
+	}
+
+	return 0;
+}
+
+/*!
+ * ov3640 init function
+ * Called by insmod ov3640_camera.ko.
+ *
+ * @return  Error code indicating success or failure
+ */
+static __init int ov3640_init(void)
+{
+	u8 err;
+
+	err = i2c_add_driver(&ov3640_i2c_driver);
+	if (err != 0)
+		pr_err("%s:driver registration failed, error=%d \n",
+			__func__, err);
+
+	return err;
+}
+
+/*!
+ * OV3640 cleanup function
+ * Called on rmmod ov3640_camera.ko
+ *
+ * @return  Error code indicating success or failure
+ */
+static void __exit ov3640_clean(void)
+{
+	i2c_del_driver(&ov3640_i2c_driver);
+}
+
+module_init(ov3640_init);
+module_exit(ov3640_clean);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("OV3640 Camera Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("CSI");
diff --git a/drivers/media/video/mxc/capture/sensor_clock.c b/drivers/media/video/mxc/capture/sensor_clock.c
new file mode 100644
index 000000000000..3d1bf8d71019
--- /dev/null
+++ b/drivers/media/video/mxc/capture/sensor_clock.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sensor_clock.c
+ *
+ * @brief camera clock function
+ *
+ * @ingroup Camera
+ */
+#include <linux/init.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <mach/hardware.h>
+
+#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) \
+			       || defined(CONFIG_VIDEO_MXC_CSI_CAMERA_MODULE) \
+			       || defined(CONFIG_VIDEO_MXC_CSI_CAMERA)
+/*
+ * set_mclk_rate
+ *
+ * @param       p_mclk_freq  mclk frequence
+ *
+ */
+void set_mclk_rate(uint32_t * p_mclk_freq)
+{
+	struct clk *clk;
+	uint32_t freq = 0;
+
+	clk = clk_get(NULL, "csi_clk");
+
+	freq = clk_round_rate(clk, *p_mclk_freq);
+	clk_set_rate(clk, freq);
+
+	*p_mclk_freq = freq;
+
+	clk_put(clk);
+	pr_debug("mclk frequency = %d\n", *p_mclk_freq);
+}
+#else
+/*
+ * set_mclk_rate
+ *
+ * @param       p_mclk_freq  mclk frequence
+ * @param	csi         csi 0 or csi 1
+ *
+ */
+void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi)
+{
+	struct clk *clk;
+	uint32_t freq = 0;
+	char *mclk;
+
+	if (cpu_is_mx53()) {
+		if (csi == 0)
+			mclk = "ssi_ext1_clk";
+		else {
+			pr_err("invalid csi num %d\n", csi);
+			return;
+		}
+	} else {
+		if (csi == 0) {
+			mclk = "csi_mclk1";
+		} else if (csi == 1) {
+			mclk = "csi_mclk2";
+		} else {
+			pr_err("invalid csi num %d\n", csi);
+			return;
+		}
+	}
+
+	clk = clk_get(NULL, mclk);
+
+	freq = clk_round_rate(clk, *p_mclk_freq);
+	clk_set_rate(clk, freq);
+
+	*p_mclk_freq = freq;
+
+	clk_put(clk);
+	pr_debug("%s frequency = %d\n", mclk, *p_mclk_freq);
+}
+#endif
+
+/* Exported symbols for modules. */
+EXPORT_SYMBOL(set_mclk_rate);
diff --git a/drivers/media/video/mxc/opl/Makefile b/drivers/media/video/mxc/opl/Makefile
new file mode 100644
index 000000000000..092a62c5ac4a
--- /dev/null
+++ b/drivers/media/video/mxc/opl/Makefile
@@ -0,0 +1,5 @@
+opl-objs	:= opl_mod.o rotate90_u16.o rotate270_u16.o	\
+		   rotate90_u16_qcif.o rotate270_u16_qcif.o	\
+		   vmirror_u16.o hmirror_rotate180_u16.o
+
+obj-$(CONFIG_VIDEO_MXC_OPL)	+= opl.o
diff --git a/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c b/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c
new file mode 100644
index 000000000000..3119a128c1f2
--- /dev/null
+++ b/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include "opl.h"
+
+static inline u32 rot_left_u16(u16 x, unsigned int n)
+{
+	return (x << n) | (x >> (16 - n));
+}
+
+static inline u32 rot_left_u32(u32 x, unsigned int n)
+{
+	return (x << n) | (x >> (32 - n));
+}
+
+static inline u32 byte_swap_u32(u32 x)
+{
+	u32 t1, t2, t3;
+
+	t1 = x ^ ((x << 16) | x >> 16);
+	t2 = t1 & 0xff00ffff;
+	t3 = (x >> 8) | (x << 24);
+	return t3 ^ (t2 >> 8);
+}
+
+static int opl_hmirror_u16_by1(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror);
+static int opl_hmirror_u16_by2(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror);
+static int opl_hmirror_u16_by4(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror);
+static int opl_hmirror_u16_by8(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror);
+
+int opl_hmirror_u16(const u8 * src, int src_line_stride, int width, int height,
+		    u8 * dst, int dst_line_stride)
+{
+	if (!src || !dst)
+		return OPLERR_NULL_PTR;
+
+	if (width == 0 || height == 0 || src_line_stride == 0
+	    || dst_line_stride == 0)
+		return OPLERR_BAD_ARG;
+
+	if (width % 8 == 0)
+		return opl_hmirror_u16_by8(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 0);
+	else if (width % 4 == 0)
+		return opl_hmirror_u16_by4(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 0);
+	else if (width % 2 == 0)
+		return opl_hmirror_u16_by2(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 0);
+	else			/* (width % 1) */
+		return opl_hmirror_u16_by1(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 0);
+}
+
+int opl_rotate180_u16(const u8 * src, int src_line_stride, int width,
+		      int height, u8 * dst, int dst_line_stride)
+{
+	if (!src || !dst)
+		return OPLERR_NULL_PTR;
+
+	if (width == 0 || height == 0 || src_line_stride == 0
+	    || dst_line_stride == 0)
+		return OPLERR_BAD_ARG;
+
+	if (width % 8 == 0)
+		return opl_hmirror_u16_by8(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 1);
+	else if (width % 4 == 0)
+		return opl_hmirror_u16_by4(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 1);
+	else if (width % 2 == 0)
+		return opl_hmirror_u16_by2(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 1);
+	else			/* (width % 1) */
+		return opl_hmirror_u16_by1(src, src_line_stride, width, height,
+					   dst, dst_line_stride, 1);
+}
+
+static int opl_hmirror_u16_by1(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror)
+{
+	const u8 *src_row_addr;
+	const u8 *psrc;
+	u8 *dst_row_addr, *pdst;
+	int i, j;
+	u16 pixel;
+
+	src_row_addr = src;
+	if (vmirror) {
+		dst_row_addr = dst + dst_line_stride * (height - 1);
+		dst_line_stride = -dst_line_stride;
+	} else
+		dst_row_addr = dst;
+
+	/* Loop over all rows */
+	for (i = 0; i < height; i++) {
+		/* Loop over each pixel */
+		psrc = src_row_addr;
+		pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL
+		    - (BYTES_PER_PIXEL - BYTES_PER_PIXEL);
+		for (j = 0; j < width; j++) {
+			pixel = *(u16 *) psrc;
+			*(u16 *) pdst = pixel;
+			psrc += BYTES_PER_PIXEL;
+			pdst -= BYTES_PER_PIXEL;
+		}
+		src_row_addr += src_line_stride;
+		dst_row_addr += dst_line_stride;
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+static int opl_hmirror_u16_by2(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror)
+{
+	const u8 *src_row_addr;
+	const u8 *psrc;
+	u8 *dst_row_addr, *pdst;
+	int i, j;
+	u32 pixelsin, pixelsout;
+
+	src_row_addr = src;
+	if (vmirror) {
+		dst_row_addr = dst + dst_line_stride * (height - 1);
+		dst_line_stride = -dst_line_stride;
+	} else
+		dst_row_addr = dst;
+
+	/* Loop over all rows */
+	for (i = 0; i < height; i++) {
+		/* Loop over each pixel */
+		psrc = src_row_addr;
+		pdst = dst_row_addr + (width - 2) * BYTES_PER_PIXEL;
+		for (j = 0; j < (width >> 1); j++) {
+			pixelsin = *(u32 *) psrc;
+			pixelsout = rot_left_u32(pixelsin, 16);
+			*(u32 *) pdst = pixelsout;
+			psrc += BYTES_PER_2PIXEL;
+			pdst -= BYTES_PER_2PIXEL;
+		}
+		src_row_addr += src_line_stride;
+		dst_row_addr += dst_line_stride;
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+static int opl_hmirror_u16_by4(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror)
+{
+	const u8 *src_row_addr;
+	const u8 *psrc;
+	u8 *dst_row_addr, *pdst;
+	int i, j;
+
+	union doubleword {
+		u64 dw;
+		u32 w[2];
+	};
+
+	union doubleword inbuf;
+	union doubleword outbuf;
+
+	src_row_addr = src;
+	if (vmirror) {
+		dst_row_addr = dst + dst_line_stride * (height - 1);
+		dst_line_stride = -dst_line_stride;
+	} else
+		dst_row_addr = dst;
+
+	/* Loop over all rows */
+	for (i = 0; i < height; i++) {
+		/* Loop over each pixel */
+		psrc = src_row_addr;
+		pdst = dst_row_addr + (width - 4) * BYTES_PER_PIXEL;
+		for (j = 0; j < (width >> 2); j++) {
+			inbuf.dw = *(u64 *) psrc;
+			outbuf.w[0] = rot_left_u32(inbuf.w[1], 16);
+			outbuf.w[1] = rot_left_u32(inbuf.w[0], 16);
+			*(u64 *) pdst = outbuf.dw;
+			psrc += BYTES_PER_4PIXEL;
+			pdst -= BYTES_PER_4PIXEL;
+		}
+		src_row_addr += src_line_stride;
+		dst_row_addr += dst_line_stride;
+	}
+	return OPLERR_SUCCESS;
+}
+
+static int opl_hmirror_u16_by8(const u8 * src, int src_line_stride, int width,
+			       int height, u8 * dst, int dst_line_stride,
+			       int vmirror)
+{
+	const u8 *src_row_addr;
+	const u8 *psrc;
+	u8 *dst_row_addr, *pdst;
+	int i, j;
+
+	src_row_addr = src;
+	if (vmirror) {
+		dst_row_addr = dst + dst_line_stride * (height - 1);
+		dst_line_stride = -dst_line_stride;
+	} else
+		dst_row_addr = dst;
+
+	/* Loop over all rows */
+	for (i = 0; i < height; i++) {
+		/* Loop over each pixel */
+		psrc = src_row_addr;
+		pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL - 2;
+		for (j = (width >> 3); j > 0; j--) {
+			__asm__ volatile (
+				"ldmia	%0!,{r2-r5}\n\t"
+				"mov	r6, r2\n\t"
+				"mov	r7, r3\n\t"
+				"mov	r2, r5, ROR #16\n\t"
+				"mov	r3, r4, ROR #16\n\t"
+				"mov	r4, r7, ROR #16\n\t"
+				"mov	r5, r6, ROR #16\n\t"
+				"stmda	%1!,{r2-r5}\n\t"
+
+				:"+r"(psrc), "+r"(pdst)
+				:"0"(psrc), "1"(pdst)
+				:"r2", "r3", "r4", "r5", "r6", "r7",
+				"memory"
+			);
+		}
+		src_row_addr += src_line_stride;
+		dst_row_addr += dst_line_stride;
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+EXPORT_SYMBOL(opl_hmirror_u16);
+EXPORT_SYMBOL(opl_rotate180_u16);
diff --git a/drivers/media/video/mxc/opl/opl.h b/drivers/media/video/mxc/opl/opl.h
new file mode 100644
index 000000000000..24644c8e78fa
--- /dev/null
+++ b/drivers/media/video/mxc/opl/opl.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup OPLIP OPL Image Processing
+ */
+/*!
+ * @file opl.h
+ *
+ * @brief The OPL (Open Primitives Library) Image Processing library defines
+ * efficient functions for rotation and mirroring.
+ *
+ * It includes ARM9-optimized rotation and mirroring functions. It is derived
+ * from the original OPL project which is found at sourceforge.freescale.net.
+ *
+ * @ingroup OPLIP
+ */
+#ifndef __OPL_H__
+#define __OPL_H__
+
+#include <linux/types.h>
+
+#define BYTES_PER_PIXEL			2
+#define CACHE_LINE_WORDS		8
+#define BYTES_PER_WORD			4
+
+#define BYTES_PER_2PIXEL		(BYTES_PER_PIXEL * 2)
+#define BYTES_PER_4PIXEL		(BYTES_PER_PIXEL * 4)
+#define BYTES_PER_8PIXEL		(BYTES_PER_PIXEL * 8)
+
+#define QCIF_Y_WIDTH			176
+#define QCIF_Y_HEIGHT			144
+
+/*! Enumerations of opl error code */
+enum opl_error {
+	OPLERR_SUCCESS = 0,
+	OPLERR_NULL_PTR,
+	OPLERR_BAD_ARG,
+	OPLERR_DIV_BY_ZERO,
+	OPLERR_OVER_FLOW,
+	OPLERR_UNDER_FLOW,
+	OPLERR_MISALIGNED,
+};
+
+/*!
+ * @brief Rotate a 16bbp buffer 90 degrees clockwise.
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_rotate90_u16(const u8 * src, int src_line_stride, int width, int height,
+		     u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Rotate a 16bbp buffer 180 degrees clockwise.
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_rotate180_u16(const u8 * src, int src_line_stride, int width,
+		      int height, u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Rotate a 16bbp buffer 270 degrees clockwise
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_rotate270_u16(const u8 * src, int src_line_stride, int width,
+		      int height, u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Mirror a 16bpp buffer horizontally
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_hmirror_u16(const u8 * src, int src_line_stride, int width, int height,
+		    u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Mirror a 16bpp buffer vertically
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_vmirror_u16(const u8 * src, int src_line_stride, int width, int height,
+		    u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Rotate a 16bbp buffer 90 degrees clockwise and mirror vertically
+ *	  It is equivalent to rotate 270 degree and mirror horizontally
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_rotate90_vmirror_u16(const u8 * src, int src_line_stride, int width,
+			     int height, u8 * dst, int dst_line_stride);
+
+/*!
+ * @brief Rotate a 16bbp buffer 270 degrees clockwise and mirror vertically
+ *	  It is equivalent to rotate 90 degree and mirror horizontally
+ *
+ * @param src             Pointer to the input buffer
+ * @param src_line_stride Length in bytes of a raster line of the input buffer
+ * @param width           Width in pixels of the region in the input buffer
+ * @param height          Height in pixels of the region in the input buffer
+ * @param dst             Pointer to the output buffer
+ * @param dst_line_stride Length in bytes of a raster line of the output buffer
+ *
+ * @return Standard OPL error code. See enumeration for possible result codes.
+ */
+int opl_rotate270_vmirror_u16(const u8 * src, int src_line_stride, int width,
+			      int height, u8 * dst, int dst_line_stride);
+
+#endif				/* __OPL_H__ */
diff --git a/drivers/media/video/mxc/opl/opl_mod.c b/drivers/media/video/mxc/opl/opl_mod.c
new file mode 100644
index 000000000000..a581aadda252
--- /dev/null
+++ b/drivers/media/video/mxc/opl/opl_mod.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+
+static __init int opl_init(void)
+{
+	return 0;
+}
+
+static void __exit opl_exit(void)
+{
+}
+
+module_init(opl_init);
+module_exit(opl_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("OPL Software Rotation/Mirroring");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/opl/rotate270_u16.c b/drivers/media/video/mxc/opl/rotate270_u16.c
new file mode 100644
index 000000000000..add87f1a9e44
--- /dev/null
+++ b/drivers/media/video/mxc/opl/rotate270_u16.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include "opl.h"
+
+static int opl_rotate270_u16_by16(const u8 * src, int src_line_stride,
+				  int width, int height, u8 * dst,
+				  int dst_line_stride, int vmirror);
+static int opl_rotate270_u16_by4(const u8 * src, int src_line_stride, int width,
+				 int height, u8 * dst, int dst_line_stride,
+				 int vmirror);
+static int opl_rotate270_vmirror_u16_both(const u8 * src, int src_line_stride,
+					  int width, int height, u8 * dst,
+					  int dst_line_stride, int vmirror);
+int opl_rotate270_u16_qcif(const u8 * src, u8 * dst);
+
+int opl_rotate270_u16(const u8 * src, int src_line_stride, int width,
+		      int height, u8 * dst, int dst_line_stride)
+{
+	return opl_rotate270_vmirror_u16_both(src, src_line_stride, width,
+					      height, dst, dst_line_stride, 0);
+}
+
+int opl_rotate270_vmirror_u16(const u8 * src, int src_line_stride, int width,
+			      int height, u8 * dst, int dst_line_stride)
+{
+	return opl_rotate270_vmirror_u16_both(src, src_line_stride, width,
+					      height, dst, dst_line_stride, 1);
+}
+
+static int opl_rotate270_vmirror_u16_both(const u8 * src, int src_line_stride,
+					  int width, int height, u8 * dst,
+					  int dst_line_stride, int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL;
+	const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL / 4;
+
+	if (!src || !dst)
+		return OPLERR_NULL_PTR;
+
+	if (width == 0 || height == 0 || src_line_stride == 0
+	    || dst_line_stride == 0)
+		return OPLERR_BAD_ARG;
+
+	/* The QCIF algorithm doesn't support vertical mirroring */
+	if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT
+	    && src_line_stride == QCIF_Y_WIDTH * 2
+	    && src_line_stride == QCIF_Y_HEIGHT * 2)
+		return opl_rotate270_u16_qcif(src, dst);
+	else if (width % BLOCK_SIZE_PIXELS == 0
+		 && height % BLOCK_SIZE_PIXELS == 0)
+		return opl_rotate270_u16_by16(src, src_line_stride, width,
+					      height, dst, dst_line_stride,
+					      vmirror);
+	else if (width % BLOCK_SIZE_PIXELS_BY4 == 0
+		 && height % BLOCK_SIZE_PIXELS_BY4 == 0)
+		return opl_rotate270_u16_by4(src, src_line_stride, width,
+					     height, dst, dst_line_stride,
+					     vmirror);
+	else
+		return OPLERR_BAD_ARG;
+}
+
+/*
+ * Rotate Counter Clockwise, divide RGB component into 16 row strips, read
+ * non sequentially and write sequentially. This is done in 16 line strips
+ * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels
+ * are 2 bytes. The 16 reads will be cache misses, but the next 240 should
+ * be from cache. The writes to the output buffer will be sequential for 16
+ * writes.
+ *
+ * Example:
+ * Input data matrix:	    output matrix
+ *
+ * 0 | 1 | 2 | 3 | 4 |      4 | 0 | 0 | 3 |
+ * 4 | 3 | 2 | 1 | 0 |      3 | 1 | 9 | 6 |
+ * 6 | 7 | 8 | 9 | 0 |      2 | 2 | 8 | 2 |
+ * 5 | 3 | 2 | 6 | 3 |      1 | 3 | 7 | 3 |
+ * ^			    0 | 4 | 6 | 5 | < Write the input data sequentially
+ * Read first column
+ * Start at the bottom
+ * Move to next column and repeat
+ *
+ * Loop over k decreasing (blocks)
+ * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k)
+ *                * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES)
+ * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k)
+ *                * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1)
+ *                * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL
+ *
+ * Loop over i decreasing (width)
+ * Each pix:
+ * in_block_ptr += RGB_WIDTH_BYTES
+ * out_block_ptr += 4
+ *
+ * Each row of block:
+ * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2
+ * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS;
+ *
+ * It may perform vertical mirroring too depending on the vmirror flag.
+ */
+static int opl_rotate270_u16_by16(const u8 * src, int src_line_stride,
+				  int width, int height, u8 * dst,
+				  int dst_line_stride, int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL;
+	const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS
+	    - BYTES_PER_PIXEL;
+	const int OUT_INDEX = vmirror ?
+	    -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS
+	    : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS;
+	const u8 *in_block_ptr;
+	u8 *out_block_ptr;
+	int i, k;
+
+	for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) {
+		in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k)
+				      * BLOCK_SIZE_PIXELS) * src_line_stride;
+		out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k)
+				       * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL) +
+		    (width - 1) * dst_line_stride;
+
+		/*
+		* For vertical mirroring the writing starts from the
+		* first line
+		*/
+		if (vmirror)
+			out_block_ptr -= dst_line_stride * (width - 1);
+
+		for (i = width; i > 0; i--) {
+			__asm__ volatile (
+				"ldrh	r2, [%0], %4\n\t"
+				"ldrh	r3, [%0], %4\n\t"
+				"ldrh	r4, [%0], %4\n\t"
+				"ldrh	r5, [%0], %4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], %4\n\t"
+				"ldrh	r3, [%0], %4\n\t"
+				"ldrh	r4, [%0], %4\n\t"
+				"ldrh	r5, [%0], %4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], %4\n\t"
+				"ldrh	r3, [%0], %4\n\t"
+				"ldrh	r4, [%0], %4\n\t"
+				"ldrh	r5, [%0], %4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], %4\n\t"
+				"ldrh	r3, [%0], %4\n\t"
+				"ldrh	r4, [%0], %4\n\t"
+				"ldrh	r5, [%0], %4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				:"+r" (in_block_ptr), "+r"(out_block_ptr)	/* output */
+				:"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride)	/* input  */
+				:"r2", "r3", "r4", "r5", "memory"	/* modify */
+			);
+			in_block_ptr -= IN_INDEX;
+			out_block_ptr -= OUT_INDEX;
+		}
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+/*
+ * Rotate Counter Clockwise, divide RGB component into 4 row strips, read
+ * non sequentially and write sequentially. This is done in 4 line strips
+ * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels
+ * are 2 bytes. The 4 reads will be cache misses, but the next 60 should
+ * be from cache. The writes to the output buffer will be sequential for 4
+ * writes.
+ *
+ * Example:
+ * Input data matrix:	    output matrix
+ *
+ * 0 | 1 | 2 | 3 | 4 |      4 | 0 | 0 | 3 |
+ * 4 | 3 | 2 | 1 | 0 |      3 | 1 | 9 | 6 |
+ * 6 | 7 | 8 | 9 | 0 |      2 | 2 | 8 | 2 |
+ * 5 | 3 | 2 | 6 | 3 |      1 | 3 | 7 | 3 |
+ * ^			    0 | 4 | 6 | 5 | < Write the input data sequentially
+ * Read first column
+ * Start at the bottom
+ * Move to next column and repeat
+ *
+ * Loop over k decreasing (blocks)
+ * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k)
+ *                * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES)
+ * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k)
+ *                * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1)
+ *                * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL
+ *
+ * Loop over i decreasing (width)
+ * Each pix:
+ * in_block_ptr += RGB_WIDTH_BYTES
+ * out_block_ptr += 4
+ *
+ * Each row of block:
+ * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2
+ * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS;
+ *
+ * It may perform vertical mirroring too depending on the vmirror flag.
+ */
+static int opl_rotate270_u16_by4(const u8 * src, int src_line_stride, int width,
+				 int height, u8 * dst, int dst_line_stride,
+				 int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL / 4;
+	const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS
+	    - BYTES_PER_PIXEL;
+	const int OUT_INDEX = vmirror ?
+	    -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS
+	    : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS;
+	const u8 *in_block_ptr;
+	u8 *out_block_ptr;
+	int i, k;
+
+	for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) {
+		in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k)
+				      * BLOCK_SIZE_PIXELS) * src_line_stride;
+		out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k)
+				       * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL)
+		    + (width - 1) * dst_line_stride;
+
+		/*
+		* For vertical mirroring the writing starts from the
+		* first line
+		*/
+		if (vmirror)
+			out_block_ptr -= dst_line_stride * (width - 1);
+
+		for (i = width; i > 0; i--) {
+			__asm__ volatile (
+				"ldrh	r2, [%0], %4\n\t"
+				"ldrh	r3, [%0], %4\n\t"
+				"ldrh	r4, [%0], %4\n\t"
+				"ldrh	r5, [%0], %4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				:"+r" (in_block_ptr), "+r"(out_block_ptr)	/* output */
+				:"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride)	/* input  */
+				:"r2", "r3", "r4", "r5", "memory"	/* modify */
+			);
+			in_block_ptr -= IN_INDEX;
+			out_block_ptr -= OUT_INDEX;
+		}
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+EXPORT_SYMBOL(opl_rotate270_u16);
+EXPORT_SYMBOL(opl_rotate270_vmirror_u16);
diff --git a/drivers/media/video/mxc/opl/rotate270_u16_qcif.S b/drivers/media/video/mxc/opl/rotate270_u16_qcif.S
new file mode 100644
index 000000000000..4101eaac4554
--- /dev/null
+++ b/drivers/media/video/mxc/opl/rotate270_u16_qcif.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/linkage.h>
+
+	.text
+	.align	2
+ENTRY(opl_rotate270_u16_qcif)
+	STMFD    sp!,{r4-r10}
+        MOV      r12,#0x160
+        MOV      r10,#0x90
+        MOV      r3,r10,LSR #4
+.L1.16:
+        RSB      r2,r3,r10,LSR #4
+        MOV      r5,r2,LSL #5
+        MOV      r4,r12,LSR #1
+        SMULBB   r4,r5,r4
+        ADD      r2,r1,r2,LSL #5
+        ADD      r5,r2,#0xc000
+        ADD      r5,r5,#0x4e0
+        MOV      r2,r12,LSR #1
+        ADD      r4,r0,r4
+.L1.52:
+        LDRH     r6,[r4],r12
+        LDRH     r7,[r4],r12
+        LDRH     r8,[r4],r12
+        LDRH     r9,[r4],r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        SUBS     r2,r2,#1
+        LDRH     r6,[r4],r12
+        LDRH     r7,[r4],r12
+        LDRH     r8,[r4],r12
+        LDRH     r9,[r4],r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        LDRH     r6,[r4],r12
+        LDRH     r7,[r4],r12
+        LDRH     r8,[r4],r12
+        LDRH     r9,[r4],r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        LDRH     r6,[r4],r12
+        LDRH     r7,[r4],r12
+        LDRH     r8,[r4],r12
+        LDRH     r9,[r4],r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        SUB      r4,r4,#0x1500
+        STMIA    r5,{r6,r7}
+        SUB      r5,r5,#0x138
+        SUB      r4,r4,#0xfe
+        BGT      .L1.52
+        SUBS     r3,r3,#1
+        BGT      .L1.16
+        LDMFD    sp!,{r4-r10}
+        BX       lr
+	.size	opl_rotate270_u16_qcif, . - opl_rotate270_u16_qcif
diff --git a/drivers/media/video/mxc/opl/rotate90_u16.c b/drivers/media/video/mxc/opl/rotate90_u16.c
new file mode 100644
index 000000000000..dd7d445aa952
--- /dev/null
+++ b/drivers/media/video/mxc/opl/rotate90_u16.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include "opl.h"
+
+static int opl_rotate90_u16_by16(const u8 * src, int src_line_stride, int width,
+				 int height, u8 * dst, int dst_line_stride,
+				 int vmirror);
+static int opl_rotate90_u16_by4(const u8 * src, int src_line_stride, int width,
+				int height, u8 * dst, int dst_line_stride,
+				int vmirror);
+static int opl_rotate90_vmirror_u16_both(const u8 * src, int src_line_stride,
+					 int width, int height, u8 * dst,
+					 int dst_line_stride, int vmirror);
+int opl_rotate90_u16_qcif(const u8 * src, u8 * dst);
+
+int opl_rotate90_u16(const u8 * src, int src_line_stride, int width, int height,
+		     u8 * dst, int dst_line_stride)
+{
+	return opl_rotate90_vmirror_u16_both(src, src_line_stride, width,
+					    height, dst, dst_line_stride, 0);
+}
+
+int opl_rotate90_vmirror_u16(const u8 * src, int src_line_stride, int width,
+			    int height, u8 * dst, int dst_line_stride)
+{
+	return opl_rotate90_vmirror_u16_both(src, src_line_stride, width,
+					    height, dst, dst_line_stride, 1);
+}
+
+static int opl_rotate90_vmirror_u16_both(const u8 * src, int src_line_stride,
+					 int width, int height, u8 * dst,
+					 int dst_line_stride, int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL;
+	const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL / 4;
+
+	if (!src || !dst)
+		return OPLERR_NULL_PTR;
+
+	if (width == 0 || height == 0 || src_line_stride == 0
+	    || dst_line_stride == 0)
+		return OPLERR_BAD_ARG;
+
+	/* The QCIF algorithm doesn't support vertical mirroring */
+	if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT
+	    && src_line_stride == QCIF_Y_WIDTH * 2
+	    && src_line_stride == QCIF_Y_HEIGHT * 2)
+		return opl_rotate90_u16_qcif(src, dst);
+	else if (width % BLOCK_SIZE_PIXELS == 0
+		 && height % BLOCK_SIZE_PIXELS == 0)
+		return opl_rotate90_u16_by16(src, src_line_stride, width,
+					     height, dst, dst_line_stride,
+					     vmirror);
+	else if (width % BLOCK_SIZE_PIXELS_BY4 == 0
+		 && height % BLOCK_SIZE_PIXELS_BY4 == 0)
+		return opl_rotate90_u16_by4(src, src_line_stride, width, height,
+					    dst, dst_line_stride, vmirror);
+	else
+		return OPLERR_BAD_ARG;
+}
+
+/*
+ * Performs clockwise rotation (and possibly vertical mirroring depending
+ * on the vmirror flag) using block sizes of 16x16
+ * The algorithm is similar to 270 degree clockwise rotation algorithm
+ */
+static int opl_rotate90_u16_by16(const u8 * src, int src_line_stride, int width,
+				 int height, u8 * dst, int dst_line_stride,
+				 int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL;
+	const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS;
+	const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS
+	    + BYTES_PER_PIXEL;
+	const int OUT_INDEX = vmirror ?
+	    -dst_line_stride - BLOCK_SIZE_BYTES
+	    : dst_line_stride - BLOCK_SIZE_BYTES;
+	const u8 *in_block_ptr;
+	u8 *out_block_ptr;
+	int i, k;
+
+	for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) {
+		in_block_ptr = src + src_line_stride * (height - 1)
+		    - (src_line_stride * BLOCK_SIZE_PIXELS *
+		       (height / BLOCK_SIZE_PIXELS - k));
+		out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS *
+		    ((height / BLOCK_SIZE_PIXELS) - k);
+
+		/*
+		 * For vertical mirroring the writing starts from the
+		 * bottom line
+		 */
+		if (vmirror)
+			out_block_ptr += dst_line_stride * (width - 1);
+
+		for (i = width; i > 0; i--) {
+			__asm__ volatile (
+				"ldrh	r2, [%0], -%4\n\t"
+				"ldrh	r3, [%0], -%4\n\t"
+				"ldrh	r4, [%0], -%4\n\t"
+				"ldrh	r5, [%0], -%4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], -%4\n\t"
+				"ldrh	r3, [%0], -%4\n\t"
+				"ldrh	r4, [%0], -%4\n\t"
+				"ldrh	r5, [%0], -%4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], -%4\n\t"
+				"ldrh	r3, [%0], -%4\n\t"
+				"ldrh	r4, [%0], -%4\n\t"
+				"ldrh	r5, [%0], -%4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				"ldrh	r2, [%0], -%4\n\t"
+				"ldrh	r3, [%0], -%4\n\t"
+				"ldrh	r4, [%0], -%4\n\t"
+				"ldrh	r5, [%0], -%4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				:"+r" (in_block_ptr), "+r"(out_block_ptr)	/* output */
+				:"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride)	/* input  */
+				:"r2", "r3", "r4", "r5", "memory"	/* modify */
+			);
+			in_block_ptr += IN_INDEX;
+			out_block_ptr += OUT_INDEX;
+		}
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+/*
+ * Performs clockwise rotation (and possibly vertical mirroring depending
+ * on the vmirror flag) using block sizes of 4x4
+ * The algorithm is similar to 270 degree clockwise rotation algorithm
+ */
+static int opl_rotate90_u16_by4(const u8 * src, int src_line_stride, int width,
+				int height, u8 * dst, int dst_line_stride,
+				int vmirror)
+{
+	const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD
+	    / BYTES_PER_PIXEL / 4;
+	const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS;
+	const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS
+	    + BYTES_PER_PIXEL;
+	const int OUT_INDEX = vmirror ?
+	    -dst_line_stride - BLOCK_SIZE_BYTES
+	    : dst_line_stride - BLOCK_SIZE_BYTES;
+	const u8 *in_block_ptr;
+	u8 *out_block_ptr;
+	int i, k;
+
+	for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) {
+		in_block_ptr = src + src_line_stride * (height - 1)
+		    - (src_line_stride * BLOCK_SIZE_PIXELS *
+		       (height / BLOCK_SIZE_PIXELS - k));
+		out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS
+		    * ((height / BLOCK_SIZE_PIXELS) - k);
+
+		/*
+		 * For horizontal mirroring the writing starts from the
+		 * bottom line
+		 */
+		if (vmirror)
+			out_block_ptr += dst_line_stride * (width - 1);
+
+		for (i = width; i > 0; i--) {
+			__asm__ volatile (
+				"ldrh	r2, [%0], -%4\n\t"
+				"ldrh	r3, [%0], -%4\n\t"
+				"ldrh	r4, [%0], -%4\n\t"
+				"ldrh	r5, [%0], -%4\n\t"
+				"orr	r2, r2, r3, lsl #16\n\t"
+				"orr	r4, r4, r5, lsl #16\n\t"
+				"str	r2, [%1], #4\n\t"
+				"str	r4, [%1], #4\n\t"
+
+				:"+r" (in_block_ptr), "+r"(out_block_ptr)	/* output */
+				:"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride)	/* input  */
+				:"r2", "r3", "r4", "r5", "memory"	/* modify */
+			);
+			in_block_ptr += IN_INDEX;
+			out_block_ptr += OUT_INDEX;
+		}
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+EXPORT_SYMBOL(opl_rotate90_u16);
+EXPORT_SYMBOL(opl_rotate90_vmirror_u16);
diff --git a/drivers/media/video/mxc/opl/rotate90_u16_qcif.S b/drivers/media/video/mxc/opl/rotate90_u16_qcif.S
new file mode 100644
index 000000000000..8568a9e629e5
--- /dev/null
+++ b/drivers/media/video/mxc/opl/rotate90_u16_qcif.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/linkage.h>
+
+	.text
+	.align	2
+ENTRY(opl_rotate90_u16_qcif)
+        STMFD    sp!,{r4-r10}
+        MOV      r12,#0x160
+        MOV      r10,#0x90
+        MOV      r3,r10,LSR #4
+.L1.216:
+        RSB      r2,r3,r10,LSR #4
+        MOV      r4,#0x20
+        SMULBB   r5,r4,r2
+        MOV      r4,#0x1600
+        SMULBB   r2,r4,r2
+        ADD      r4,r0,#0xc000
+        ADD      r4,r4,#0x4a0
+        SUB      r4,r4,r2
+        MOV      r2,r12,LSR #1
+        ADD      r5,r1,r5
+.L1.256:
+        LDRH     r6,[r4],-r12
+        LDRH     r7,[r4],-r12
+        LDRH     r8,[r4],-r12
+        LDRH     r9,[r4],-r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        SUBS     r2,r2,#1
+        LDRH     r6,[r4],-r12
+        LDRH     r7,[r4],-r12
+        LDRH     r8,[r4],-r12
+        LDRH     r9,[r4],-r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        LDRH     r6,[r4],-r12
+        LDRH     r7,[r4],-r12
+        LDRH     r8,[r4],-r12
+        LDRH     r9,[r4],-r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        STMIA    r5!,{r6,r7}
+        LDRH     r6,[r4],-r12
+        LDRH     r7,[r4],-r12
+        LDRH     r8,[r4],-r12
+        LDRH     r9,[r4],-r12
+        ORR      r6,r6,r7,LSL #16
+        ORR      r7,r8,r9,LSL #16
+        ADD      r4,r4,#0x1600
+        STMIA    r5!,{r6,r7}
+        ADD      r5,r5,#0x100
+        ADD      r4,r4,#2
+        BGT      .L1.256
+        SUBS     r3,r3,#1
+        BGT      .L1.216
+        LDMFD    sp!,{r4-r10}
+        BX       lr
+	.size	opl_rotate90_u16_qcif, . - opl_rotate90_u16_qcif
diff --git a/drivers/media/video/mxc/opl/vmirror_u16.c b/drivers/media/video/mxc/opl/vmirror_u16.c
new file mode 100644
index 000000000000..57f805c08a81
--- /dev/null
+++ b/drivers/media/video/mxc/opl/vmirror_u16.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/string.h>
+#include "opl.h"
+
+int opl_vmirror_u16(const u8 * src, int src_line_stride, int width, int height,
+		    u8 * dst, int dst_line_stride)
+{
+	const u8 *src_row_addr;
+	u8 *dst_row_addr;
+	int i;
+
+	if (!src || !dst)
+		return OPLERR_NULL_PTR;
+
+	if (width == 0 || height == 0 || src_line_stride == 0
+	    || dst_line_stride == 0)
+		return OPLERR_BAD_ARG;
+
+	src_row_addr = src;
+	dst_row_addr = dst + (height - 1) * dst_line_stride;
+
+	/* Loop over all rows */
+	for (i = 0; i < height; i++) {
+		/* memcpy each row */
+		memcpy(dst_row_addr, src_row_addr, BYTES_PER_PIXEL * width);
+		src_row_addr += src_line_stride;
+		dst_row_addr -= dst_line_stride;
+	}
+
+	return OPLERR_SUCCESS;
+}
+
+EXPORT_SYMBOL(opl_vmirror_u16);
diff --git a/drivers/media/video/mxc/output/Kconfig b/drivers/media/video/mxc/output/Kconfig
new file mode 100644
index 000000000000..2153ad248907
--- /dev/null
+++ b/drivers/media/video/mxc/output/Kconfig
@@ -0,0 +1,28 @@
+config VIDEO_MXC_IPU_OUTPUT
+	bool "IPU v4l2 support"
+	depends on VIDEO_MXC_OUTPUT && MXC_IPU
+	default y
+	---help---
+	  This is the video4linux2 driver for IPU post processing video output.
+
+config VIDEO_MXC_IPUV1_WVGA_OUTPUT
+	bool "IPUv1 WVGA v4l2 display support"
+	depends on VIDEO_MXC_OUTPUT && MXC_IPU
+	default n
+	---help---
+	  This is the video4linux2 driver for IPUv1 WVGA post processing video output.
+
+config VIDEO_MXC_EMMA_OUTPUT
+	bool
+	depends on VIDEO_MXC_OUTPUT && MXC_EMMA && FB_MXC_SYNC_PANEL
+	default y
+	---help---
+	  This is the video4linux2 driver for EMMA post processing video output.
+
+config VIDEO_MXC_OUTPUT_FBSYNC
+	bool "Synchronize the output with LCDC refresh"
+	depends on VIDEO_MXC_EMMA_OUTPUT
+	default y
+	---help---
+	  Synchronize the post-processing with LCDC EOF (End of Frame) to
+	  prevent tearing issue. If unsure, say Y.
diff --git a/drivers/media/video/mxc/output/Makefile b/drivers/media/video/mxc/output/Makefile
new file mode 100644
index 000000000000..1713fa3bf3ab
--- /dev/null
+++ b/drivers/media/video/mxc/output/Makefile
@@ -0,0 +1,11 @@
+ifeq ($(CONFIG_VIDEO_MXC_EMMA_OUTPUT),y)
+	mx27_output-objs := mx27_v4l2_output.o mx27_pp.o
+	obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mx27_output.o
+endif
+
+ifeq ($(CONFIG_VIDEO_MXC_IPU_OUTPUT),y)
+	obj-$(CONFIG_VIDEO_MXC_OUTPUT)	+= mxc_v4l2_output.o
+endif
+ifeq ($(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT),y)
+	obj-$(CONFIG_VIDEO_MXC_OUTPUT)	+= mx31_v4l2_wvga_output.o
+endif
diff --git a/drivers/media/video/mxc/output/mx27_pp.c b/drivers/media/video/mxc/output/mx27_pp.c
new file mode 100644
index 000000000000..a82328015fe2
--- /dev/null
+++ b/drivers/media/video/mxc/output/mx27_pp.c
@@ -0,0 +1,904 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_pp.c
+ *
+ * @brief MX27 V4L2 Video Output Driver
+ *
+ * Video4Linux2 Output Device using MX27 eMMA Post-processing functionality.
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/fb.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <asm/io.h>
+
+#include "mx27_pp.h"
+#include "mxc_v4l2_output.h"
+
+#define SCALE_RETRY	32	/* to be more relax, less precise */
+#define PP_SKIP		1
+#define PP_TBL_MAX	40
+
+static unsigned short scale_tbl[PP_TBL_MAX];
+static int g_hlen, g_vlen;
+
+static emma_pp_cfg g_pp_cfg;
+static int g_disp_num = 0;
+static char pp_dev[] = "emma_pp";
+
+/*!
+ * @brief PP resizing routines
+ */
+static int gcd(int x, int y);
+static int ratio(int x, int y, int *den);
+static int scale_0d(int k, int coeff, int base, int nxt);
+static int scale_1d(int inv, int outv, int k);
+static int scale_1d_smart(int *inv, int *outv, int index);
+static int scale_2d(emma_pp_scale * sz);
+
+static irqreturn_t pp_isr(int irq, void *dev_id);
+static int set_output_addr(emma_pp_cfg * cfg, vout_data * vout);
+static int pphw_reset(void);
+static int pphw_enable(int flag);
+static int pphw_ptr(emma_pp_cfg * cfg);
+static int pphw_outptr(emma_pp_cfg * cfg);
+static int pphw_cfg(emma_pp_cfg * cfg);
+static int pphw_isr(void);
+static void pphw_init(void);
+static void pphw_exit(void);
+
+#define PP_DUMP(reg)	pr_debug("%s\t = 0x%08X\n", #reg, __raw_readl(reg))
+void pp_dump(void)
+{
+	PP_DUMP(PP_CNTL);
+	PP_DUMP(PP_INTRCNTL);
+	PP_DUMP(PP_INTRSTATUS);
+	PP_DUMP(PP_SOURCE_Y_PTR);
+	PP_DUMP(PP_SOURCE_CB_PTR);
+	PP_DUMP(PP_SOURCE_CR_PTR);
+	PP_DUMP(PP_DEST_RGB_PTR);
+	PP_DUMP(PP_QUANTIZER_PTR);
+	PP_DUMP(PP_PROCESS_FRAME_PARA);
+	PP_DUMP(PP_SOURCE_FRAME_WIDTH);
+	PP_DUMP(PP_DEST_DISPLAY_WIDTH);
+	PP_DUMP(PP_DEST_IMAGE_SIZE);
+	PP_DUMP(PP_DEST_FRAME_FMT_CNTL);
+	PP_DUMP(PP_RESIZE_INDEX);
+	PP_DUMP(PP_CSC_COEF_0123);
+	PP_DUMP(PP_CSC_COEF_4);
+}
+
+/*!
+ * @brief Set PP input address.
+ * @param ptr	The pointer to the Y value of input
+ * @return	Zero on success, others on failure
+ */
+int pp_ptr(unsigned long ptr)
+{
+	g_pp_cfg.ptr.y = ptr;
+	g_pp_cfg.ptr.u = g_pp_cfg.ptr.v = g_pp_cfg.ptr.qp = 0;
+
+	return pphw_ptr(&g_pp_cfg);
+}
+
+/*!
+ * @brief Enable or disable PP.
+ * @param flag	Zero to disable PP, others to enable PP
+ * @return	Zero on success, others on failure
+ */
+int pp_enable(int flag)
+{
+	return pphw_enable(flag);
+}
+
+/*!
+ * @brief Get the display No. of last completed PP frame.
+ * @return	The display No. of last completed PP frame.
+ */
+int pp_num_last(void)
+{
+	return (g_disp_num ? 0 : 1);
+}
+
+/*!
+ * @brief Initialize PP.
+ * @param vout	Pointer to _vout_data structure
+ * @return	Zero on success, others on failure
+ */
+int pp_init(vout_data * vout)
+{
+	pphw_init();
+	pphw_enable(0);
+	enable_irq(MXC_INT_EMMAPP);
+	return request_irq(MXC_INT_EMMAPP, pp_isr, 0, pp_dev, vout);
+}
+
+/*!
+ * @brief Deinitialize PP.
+ * @param vout	Pointer to _vout_data structure
+ */
+void pp_exit(vout_data * vout)
+{
+	disable_irq(MXC_INT_EMMAPP);
+	free_irq(MXC_INT_EMMAPP, vout);
+	pphw_enable(0);
+	pphw_exit();
+}
+
+/*!
+ * @brief Configure PP.
+ * @param vout	Pointer to _vout_data structure
+ * @return	Zero on success, others on failure
+ */
+int pp_cfg(vout_data * vout)
+{
+	if (!vout)
+		return -1;
+
+	/* PP accepts YUV420 input only */
+	if (vout->v2f.fmt.pix.pixelformat != V4L2_PIX_FMT_YUV420) {
+		pr_debug("unsupported pixel format.\n");
+		return -1;
+	}
+
+	g_pp_cfg.operation = 0;
+
+	memset(g_pp_cfg.csc_table, 0, sizeof(g_pp_cfg.csc_table));
+
+	/* Convert output pixel format to PP required format */
+	switch (vout->v4l2_fb.fmt.pixelformat) {
+	case V4L2_PIX_FMT_BGR32:
+		g_pp_cfg.red_width = 8;
+		g_pp_cfg.green_width = 8;
+		g_pp_cfg.blue_width = 8;
+		g_pp_cfg.red_offset = 8;
+		g_pp_cfg.green_offset = 16;
+		g_pp_cfg.blue_offset = 24;
+		g_pp_cfg.rgb_resolution = 32;
+		break;
+	case V4L2_PIX_FMT_RGB32:
+		g_pp_cfg.red_width = 8;
+		g_pp_cfg.green_width = 8;
+		g_pp_cfg.blue_width = 8;
+		g_pp_cfg.red_offset = 24;
+		g_pp_cfg.green_offset = 16;
+		g_pp_cfg.blue_offset = 8;
+		g_pp_cfg.rgb_resolution = 32;
+		break;
+	case V4L2_PIX_FMT_YUYV:
+		g_pp_cfg.red_width = 0;
+		g_pp_cfg.green_width = 0;
+		g_pp_cfg.blue_width = 0;
+		g_pp_cfg.red_offset = 0;
+		g_pp_cfg.green_offset = 0;
+		g_pp_cfg.blue_offset = PP_PIX_YUYV;
+		g_pp_cfg.rgb_resolution = 16;
+		break;
+	case V4L2_PIX_FMT_UYVY:
+		g_pp_cfg.red_width = 0;
+		g_pp_cfg.green_width = 0;
+		g_pp_cfg.blue_width = 0;
+		g_pp_cfg.red_offset = 0;
+		g_pp_cfg.green_offset = 0;
+		g_pp_cfg.blue_offset = PP_PIX_UYVY;
+		g_pp_cfg.rgb_resolution = 16;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+	default:
+		g_pp_cfg.red_width = 5;
+		g_pp_cfg.green_width = 6;
+		g_pp_cfg.blue_width = 5;
+		g_pp_cfg.red_offset = 11;
+		g_pp_cfg.green_offset = 5;
+		g_pp_cfg.blue_offset = 0;
+		g_pp_cfg.rgb_resolution = 16;
+		break;
+	}
+
+	if (vout->ipu_buf[0] != -1)
+		g_pp_cfg.ptr.y =
+		    (unsigned int)vout->queue_buf_paddr[vout->ipu_buf[0]];
+	else
+		g_pp_cfg.ptr.y = 0;
+
+	g_pp_cfg.ptr.u = g_pp_cfg.ptr.v = g_pp_cfg.ptr.qp = 0;
+
+	g_pp_cfg.dim.in.width = vout->v2f.fmt.pix.width;
+	g_pp_cfg.dim.in.height = vout->v2f.fmt.pix.height;
+	g_pp_cfg.dim.out.width = vout->crop_current.width;
+	g_pp_cfg.dim.out.height = vout->crop_current.height;
+	g_pp_cfg.dim.num.width = 0;
+	g_pp_cfg.dim.num.height = 0;
+	g_pp_cfg.dim.den.width = 0;
+	g_pp_cfg.dim.den.height = 0;
+
+	if (scale_2d(&g_pp_cfg.dim)) {
+		pr_debug("unsupported resize ratio.\n");
+		return -1;
+	}
+
+	g_pp_cfg.dim.out.width = vout->crop_current.width;
+	g_pp_cfg.dim.out.height = vout->crop_current.height;
+
+	g_pp_cfg.in_y_stride = 0;
+	if (set_output_addr(&g_pp_cfg, vout)) {
+		pr_debug("failed to set pp output address.\n");
+		return -1;
+	}
+
+	return pphw_cfg(&g_pp_cfg);
+}
+
+irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id);
+
+/*!
+ * @brief PP IRQ handler.
+ */
+static irqreturn_t pp_isr(int irq, void *dev_id)
+{
+	int status;
+	vout_data *vout = dev_id;
+
+	status = pphw_isr();
+	if ((status & 0x1) == 0) {	/* Not frame complete interrupt */
+		pr_debug("not pp frame complete interrupt\n");
+		return IRQ_HANDLED;
+	}
+
+	if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		g_disp_num = g_disp_num ? 0 : 1;
+		g_pp_cfg.outptr = (unsigned int)vout->display_bufs[g_disp_num];
+		pphw_outptr(&g_pp_cfg);
+	}
+
+	return mxc_v4l2out_pp_in_irq_handler(irq, dev_id);
+}
+
+/*!
+ * @brief Set PP output address.
+ * @param cfg	Pointer to emma_pp_cfg structure
+ * @param vout	Pointer to _vout_data structure
+ * @return	Zero on success, others on failure
+ */
+static int set_output_addr(emma_pp_cfg * cfg, vout_data * vout)
+{
+	if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		g_disp_num = 0;
+		cfg->outptr = (unsigned int)vout->display_bufs[g_disp_num];
+		cfg->out_stride = vout->crop_current.width;
+		return 0;
+	} else {
+		struct fb_info *fb;
+
+		fb = registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+		if (!fb)
+			return -1;
+
+		cfg->outptr = fb->fix.smem_start;
+		cfg->outptr += vout->crop_current.top * fb->var.xres_virtual
+		    * (fb->var.bits_per_pixel >> 3)
+		    + vout->crop_current.left * (fb->var.bits_per_pixel >> 3);
+		cfg->out_stride = fb->var.xres_virtual;
+
+		return 0;
+	}
+}
+
+/*!
+ * @brief Get maximum common divisor.
+ * @param x	First input value
+ * @param y	Second input value
+ * @return	Maximum common divisor of x and y
+ */
+static int gcd(int x, int y)
+{
+	int k;
+
+	if (x < y) {
+		k = x;
+		x = y;
+		y = k;
+	}
+
+	while ((k = x % y)) {
+		x = y;
+		y = k;
+	}
+
+	return y;
+}
+
+/*!
+ * @brief Get ratio.
+ * @param x	First input value
+ * @param y	Second input value
+ * @param den	Denominator of the ratio (corresponding to y)
+ * @return	Numerator of the ratio (corresponding to x)
+ */
+static int ratio(int x, int y, int *den)
+{
+	int g;
+
+	if (!x || !y)
+		return 0;
+
+	g = gcd(x, y);
+	*den = y / g;
+
+	return x / g;
+}
+
+/*!
+ * @brief Build PP coefficient entry
+ * Build one or more coefficient entries for PP coefficient table based
+ * on given coefficient.
+ *
+ * @param k	The index of the coefficient in coefficient table
+ * @param coeff	The weighting coefficient
+ * @param base	The base of the coefficient
+ * @param nxt	Number of pixels to be read
+ *
+ * @return	The index of the next coefficient entry on success
+ *		-1 on failure
+ */
+static int scale_0d(int k, int coeff, int base, int nxt)
+{
+	if (k >= PP_TBL_MAX) {
+		/* no more space in table */
+		pr_debug("no space in scale table, k = %d\n", k);
+		return -1;
+	}
+
+	coeff = ((coeff << BC_COEF) + (base >> 1)) / base;
+
+	/*
+	 * Valid values for weighting coefficient are 0, 2 to 30, and 31.
+	 * A value of 31 is treated as 32 and therefore 31 is an
+	 * invalid co-efficient.
+	 */
+	if (coeff >= SZ_COEF - 1)
+		coeff--;
+	else if (coeff == 1)
+		coeff++;
+	coeff = coeff << BC_NXT;
+
+	if (nxt < SZ_NXT) {
+		coeff |= nxt;
+		coeff <<= 1;
+		coeff |= 1;
+	} else {
+		/*
+		 * src inc field is 2 bit wide, for 4+, use special
+		 * code 0:0:1 to prevent dest inc
+		 */
+		coeff |= PP_SKIP;
+		coeff <<= 1;
+		coeff |= 1;
+		nxt -= PP_SKIP;
+		do {
+			pr_debug("tbl = %03X\n", coeff);
+			scale_tbl[k++] = coeff;
+			coeff = (nxt > PP_SKIP) ? PP_SKIP : nxt;
+			coeff <<= 1;
+		} while ((nxt -= PP_SKIP) > 0);
+	}
+	pr_debug("tbl = %03X\n", coeff);
+	scale_tbl[k++] = coeff;
+
+	return k;
+}
+
+/*
+ * @brief Build PP coefficient table
+ * Build PP coefficient table for one dimension (width or height)
+ * based on given input and output resolution
+ *
+ * @param inv	input resolution
+ * @param outv	output resolution
+ * @param k	index of free table entry
+ *
+ * @return	The index of the next free coefficient entry on success
+ *		-1 on failure
+ */
+static int scale_1d(int inv, int outv, int k)
+{
+	int v;			/* overflow counter */
+	int coeff, nxt;		/* table output */
+
+	if (inv == outv)
+		return scale_0d(k, 1, 1, 1);	/* force scaling */
+
+	if (inv * 4 < outv) {
+		pr_debug("upscale err: ratio should be in range 1:1 to 1:4\n");
+		return -1;
+	}
+
+	v = 0;
+	if (inv < outv) {
+		/* upscale: mix <= 2 input pixels per output pixel */
+		do {
+			coeff = outv - v;
+			v += inv;
+			if (v >= outv) {
+				v -= outv;
+				nxt = 1;
+			} else
+				nxt = 0;
+			pr_debug("upscale: coeff = %d/%d nxt = %d\n", coeff,
+				 outv, nxt);
+			k = scale_0d(k, coeff, outv, nxt);
+			if (k < 0)
+				return -1;
+		} while (v);
+	} else if (inv >= 2 * outv) {
+		/* PP doesn't support resize ratio > 2:1 except 4:1. */
+		if ((inv != 2 * outv) && (inv != 4 * outv))
+			return -1;
+		/* downscale: >=2:1 bilinear approximation */
+		coeff = inv - 2 * outv;
+		v = 0;
+		nxt = 0;
+		do {
+			v += coeff;
+			nxt = 2;
+			while (v >= outv) {
+				v -= outv;
+				nxt++;
+			}
+			pr_debug("downscale: coeff = 1/2 nxt = %d\n", nxt);
+			k = scale_0d(k, 1, 2, nxt);
+			if (k < 0)
+				return -1;
+		} while (v);
+	} else {
+		/* downscale: bilinear */
+		int in_pos_inc = 2 * outv;
+		int out_pos = inv;
+		int out_pos_inc = 2 * inv;
+		int init_carry = inv - outv;
+		int carry = init_carry;
+
+		v = outv + in_pos_inc;
+		do {
+			coeff = v - out_pos;
+			out_pos += out_pos_inc;
+			carry += out_pos_inc;
+			for (nxt = 0; v < out_pos; nxt++) {
+				v += in_pos_inc;
+				carry -= in_pos_inc;
+			}
+			pr_debug("downscale: coeff = %d/%d nxt = %d\n", coeff,
+				 in_pos_inc, nxt);
+			k = scale_0d(k, coeff, in_pos_inc, nxt);
+			if (k < 0)
+				return -1;
+		} while (carry != init_carry);
+	}
+	return k;
+}
+
+/*
+ * @brief Build PP coefficient table
+ * Build PP coefficient table for one dimension (width or height)
+ * based on given input and output resolution. The given input
+ * and output resolution might be not supported due to hardware
+ * limits. In this case this functin rounds the input and output
+ * to closest possible values and return them to caller.
+ *
+ * @param inv	input resolution, might be modified after the call
+ * @param outv	output resolution, might be modified after the call
+ * @param k	index of free table entry
+ *
+ * @return	The index of the next free coefficient entry on success
+ *		-1 on failure
+ */
+static int scale_1d_smart(int *inv, int *outv, int index)
+{
+	int len, num, den, retry;
+	static int num1, den1;
+
+	if (!inv || !outv)
+		return -1;
+
+	/* Both should be non-zero */
+	if (!(*inv) || !(*outv))
+		return -1;
+
+	retry = SCALE_RETRY;
+
+	do {
+		num = ratio(*inv, *outv, &den);
+		pr_debug("num = %d, den = %d\n", num, den);
+		if (!num)
+			continue;
+
+		if (index != 0) {
+			/*
+			 * We are now resizing height. Check to see if the
+			 * resize ratio for width can be reused by height
+			 */
+			if ((num == num1) && (den == den1))
+				return index;
+		}
+
+		if ((len = scale_1d(num, den, index)) < 0)
+			/* increase output dimension to try another ratio */
+			(*outv)++;
+		else {
+			if (index == 0) {
+				/*
+				 * We are now resizing width. The same resize
+				 * ratio may be reused by height, so save the
+				 * ratio.
+				 */
+				num1 = num;
+				den1 = den;
+			}
+			return len;
+		}
+	} while (retry--);
+
+	pr_debug("pp scale err\n");
+	return -1;
+}
+
+/*
+ * @brief Build PP coefficient table for both width and height
+ * Build PP coefficient table for both width and height based on
+ * given resizing ratios.
+ *
+ * @param sz	Structure contains resizing ratio informations
+ *
+ * @return	0 on success, others on failure
+ */
+static int scale_2d(emma_pp_scale * sz)
+{
+	int inv, outv;
+
+	/* horizontal resizing. parameter check - must provide in size */
+	if (!sz->in.width)
+		return -1;
+
+	/* Resizing based on num:den */
+	inv = sz->num.width;
+	outv = sz->den.width;
+
+	if ((g_hlen = scale_1d_smart(&inv, &outv, 0)) > 0) {
+		/* Resizing succeeded */
+		sz->den.width = outv;
+		sz->out.width = (sz->in.width * outv) / inv;
+	} else {
+		/* Resizing based on in:out */
+		inv = sz->in.width;
+		outv = sz->out.width;
+
+		if ((g_hlen = scale_1d_smart(&inv, &outv, 0)) > 0) {
+			/* Resizing succeeded */
+			sz->out.width = outv;
+			sz->num.width = ratio(sz->in.width, sz->out.width,
+					      &sz->den.width);
+		} else
+			return -1;
+	}
+
+	sz->out.width &= ~1;
+
+	/* vertical resizing. parameter check - must provide in size */
+	if (!sz->in.height)
+		return -1;
+
+	/* Resizing based on num:den */
+	inv = sz->num.height;
+	outv = sz->den.height;
+
+	if ((g_vlen = scale_1d_smart(&inv, &outv, g_hlen)) > 0) {
+		/* Resizing succeeded */
+		sz->den.height = outv;
+		sz->out.height = (sz->in.height * outv) / inv;
+	} else {
+		/* Resizing based on in:out */
+		inv = sz->in.height;
+		outv = sz->out.height;
+
+		if ((g_vlen = scale_1d_smart(&inv, &outv, g_hlen)) > 0) {
+			/* Resizing succeeded */
+			sz->out.height = outv;
+			sz->num.height = ratio(sz->in.height, sz->out.height,
+					       &sz->den.height);
+		} else
+			return -1;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Set PP resizing registers.
+ * @param sz	Pointer to pp scaling structure
+ * @return	Zero on success, others on failure
+ */
+static int pphw_scale(emma_pp_scale * sz)
+{
+	__raw_writel((sz->out.width << 16) | sz->out.height,
+		     PP_DEST_IMAGE_SIZE);
+	__raw_writel(((g_hlen - 1) << 16) | (g_vlen ==
+					     g_hlen ? 0 : (g_hlen << 8)) |
+		     (g_vlen - 1), PP_RESIZE_INDEX);
+	for (g_hlen = 0; g_hlen < g_vlen; g_hlen++)
+		__raw_writel(scale_tbl[g_hlen],
+			     PP_RESIZE_COEF_TBL + g_hlen * 4);
+
+	return 0;
+}
+
+/*!
+ * @brief Reset PP.
+ * @return	Zero on success, others on failure
+ */
+static int pphw_reset(void)
+{
+	int i;
+
+	__raw_writel(0x100, PP_CNTL);
+
+	/* timeout */
+	for (i = 0; i < 1000; i++) {
+		if (!(__raw_readl(PP_CNTL) & 0x100)) {
+			pr_debug("pp reset over\n");
+			break;
+		}
+	}
+
+	/* check reset value */
+	if (__raw_readl(PP_CNTL) != 0x876) {
+		pr_debug("pp reset value err = 0x%08X\n", __raw_readl(PP_CNTL));
+		return -1;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Enable or disable PP.
+ * @param flag	Zero to disable PP, others to enable PP
+ * @return	Zero on success, others on failure
+ */
+static int pphw_enable(int flag)
+{
+	int ret = 0;
+
+	if (flag)
+		__raw_writel(__raw_readl(PP_CNTL) | 1, PP_CNTL);
+	else
+		ret = pphw_reset();
+
+	return ret;
+}
+
+/*!
+ * @brief Set PP input address.
+ * @param cfg	The pointer to PP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+static int pphw_ptr(emma_pp_cfg * cfg)
+{
+	if (!cfg->ptr.u) {
+		int size;
+
+		/* yuv - packed */
+		size = PP_CALC_Y_SIZE(cfg);
+		cfg->ptr.u = cfg->ptr.y + size;
+		cfg->ptr.v = cfg->ptr.u + (size >> 2);
+
+		/* yuv packed with qp appended */
+		if (!cfg->ptr.qp)
+			cfg->ptr.qp = cfg->ptr.v + (size >> 2);
+	}
+	__raw_writel(cfg->ptr.y, PP_SOURCE_Y_PTR);
+	__raw_writel(cfg->ptr.u, PP_SOURCE_CB_PTR);
+	__raw_writel(cfg->ptr.v, PP_SOURCE_CR_PTR);
+	__raw_writel(cfg->ptr.qp, PP_QUANTIZER_PTR);
+
+	return 0;
+}
+
+/*!
+ * @brief Set PP output address.
+ * @param cfg	The pointer to PP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+static int pphw_outptr(emma_pp_cfg * cfg)
+{
+	__raw_writel(cfg->outptr, PP_DEST_RGB_PTR);
+	return 0;
+}
+
+/*!
+ * @brief Configuration PP.
+ * @param cfg	The pointer to PP configuration parameter
+ * @return	Zero on success, others on failure
+ */
+static int pphw_cfg(emma_pp_cfg * cfg)
+{
+	int rt;
+	register int r;
+
+	pphw_scale(&cfg->dim);
+
+	if (!cfg->in_y_stride)
+		cfg->in_y_stride = cfg->dim.in.width;
+
+	if (!cfg->out_stride)
+		cfg->out_stride = cfg->dim.out.width;
+
+	r = __raw_readl(PP_CNTL) & ~EN_MASK;
+
+	/* config parms */
+	r |= cfg->operation & EN_MASK;
+	if (cfg->operation & EN_MACROBLOCK) {
+		/* Macroblock Mode */
+		r |= 0x0200;
+		__raw_writel(0x06, PP_INTRCNTL);
+	} else {
+		/* Frame mode */
+		__raw_writel(0x05, PP_INTRCNTL);
+	}
+
+	if (cfg->red_width | cfg->green_width | cfg->blue_width) {
+		/* color conversion to be performed */
+		r |= EN_CSC;
+		if (!(cfg->red_offset | cfg->green_offset)) {
+			/* auto offset B:G:R LSb to Msb */
+			cfg->green_offset = cfg->blue_offset + cfg->blue_width;
+			cfg->red_offset = cfg->green_offset + cfg->green_width;
+		}
+		if (!cfg->rgb_resolution) {
+			/* derive minimum resolution required */
+			int w, w2;
+
+			w = cfg->red_offset + cfg->red_width;
+			w2 = cfg->blue_offset + cfg->blue_width;
+			if (w < w2)
+				w = w2;
+			w2 = cfg->green_offset + cfg->green_width;
+			if (w < w2)
+				w = w2;
+			if (w > 16)
+				w = 24;
+			else if (w > 8)
+				w = 16;
+			else
+				w = 8;
+			cfg->rgb_resolution = w;
+		}
+		/* 00,11 - 32 bpp, 10 - 16 bpp, 01 - 8 bpp */
+		r &= ~0xC00;
+		if (cfg->rgb_resolution < 32)
+			r |= (cfg->rgb_resolution << 7);
+		__raw_writel((cfg->red_offset << 26) |
+			     (cfg->green_offset << 21) |
+			     (cfg->blue_offset << 16) |
+			     (cfg->red_width << 8) |
+			     (cfg->green_width << 4) |
+			     cfg->blue_width, PP_DEST_FRAME_FMT_CNTL);
+	} else {
+		/* add YUV422 formatting */
+		static const unsigned int _422[] = {
+			0x62000888,
+			0x60100888,
+			0x43080888,
+			0x41180888
+		};
+
+		__raw_writel(_422[(cfg->blue_offset >> 3) & 3],
+			     PP_DEST_FRAME_FMT_CNTL);
+		cfg->rgb_resolution = 16;
+		r &= ~0xC00;
+		r |= (cfg->rgb_resolution << 7);
+	}
+
+	/* add csc formatting */
+	if (!cfg->csc_table[1]) {
+		static const unsigned short _csc[][6] = {
+			{0x80, 0xb4, 0x2c, 0x5b, 0x0e4, 0},
+			{0x95, 0xcc, 0x32, 0x68, 0x104, 1},
+			{0x80, 0xca, 0x18, 0x3c, 0x0ec, 0},
+			{0x95, 0xe5, 0x1b, 0x44, 0x10e, 1},
+		};
+		memcpy(cfg->csc_table, _csc[cfg->csc_table[0]],
+		       sizeof(_csc[0]));
+	}
+	__raw_writel((cfg->csc_table[0] << 24) |
+		     (cfg->csc_table[1] << 16) |
+		     (cfg->csc_table[2] << 8) |
+		     cfg->csc_table[3], PP_CSC_COEF_0123);
+	__raw_writel((cfg->csc_table[5] ? (1 << 9) : 0) | cfg->csc_table[4],
+		     PP_CSC_COEF_4);
+
+	__raw_writel(r, PP_CNTL);
+
+	pphw_ptr(cfg);
+	pphw_outptr(cfg);
+
+	/*
+	 * #MB in a row = input_width / 16pix
+	 * 1 byte per QP per MB
+	 * QP must be formatted to be 4-byte aligned
+	 * YUV lines are to be 4-byte aligned as well
+	 * So Y is 8 byte aligned, as U = V = Y/2 for 420
+	 * MPEG MBs are 16x16 anyway
+	 */
+	__raw_writel((cfg->dim.in.width << 16) | cfg->dim.in.height,
+		     PP_PROCESS_FRAME_PARA);
+	__raw_writel(cfg->in_y_stride | (PP_CALC_QP_WIDTH(cfg) << 16),
+		     PP_SOURCE_FRAME_WIDTH);
+
+	/* in bytes */
+	rt = cfg->rgb_resolution >> 3;
+	if (rt == 3)
+		rt = 4;
+	__raw_writel(cfg->out_stride * rt, PP_DEST_DISPLAY_WIDTH);
+
+	pp_dump();
+	return 0;
+}
+
+/*!
+ * @brief Check PP interrupt status.
+ * @return	PP interrupt status
+ */
+static int pphw_isr(void)
+{
+	unsigned long status;
+
+	pr_debug("pp: in isr.\n");
+	status = __raw_readl(PP_INTRSTATUS) & 7;
+	if (!status) {
+		pr_debug("pp: not my isr err.\n");
+		return status;
+	}
+
+	if (status & 4)
+		pr_debug("pp: isr state error.\n");
+
+	/* clear interrupt status */
+	__raw_writel(status, PP_INTRSTATUS);
+
+	return status;
+}
+
+static struct clk *emma_clk;
+
+/*!
+ * @brief PP module clock enable
+ */
+static void pphw_init(void)
+{
+	emma_clk = clk_get(NULL, "emma_clk");
+	clk_enable(emma_clk);
+}
+
+/*!
+ * @brief PP module clock disable
+ */
+static void pphw_exit(void)
+{
+	clk_disable(emma_clk);
+	clk_put(emma_clk);
+}
diff --git a/drivers/media/video/mxc/output/mx27_pp.h b/drivers/media/video/mxc/output/mx27_pp.h
new file mode 100644
index 000000000000..7bc65ddda3a1
--- /dev/null
+++ b/drivers/media/video/mxc/output/mx27_pp.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_pp.h
+ *
+ * @brief Header file for MX27 V4L2 Video Output Driver
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#ifndef __MX27_PP_H__
+#define __MX27_PP_H__
+
+#include "mxc_v4l2_output.h"
+
+/* PP register definitions */
+#define PP_REG(ofs)    (IO_ADDRESS(EMMA_BASE_ADDR) - 0x400 + ofs)
+
+/* Register offsets */
+#define PP_CNTL			PP_REG(0x00)
+#define PP_INTRCNTL	 	PP_REG(0x04)
+#define PP_INTRSTATUS		PP_REG(0x08)
+#define PP_SOURCE_Y_PTR		PP_REG(0x0C)
+#define PP_SOURCE_CB_PTR	PP_REG(0x10)
+#define PP_SOURCE_CR_PTR	PP_REG(0x14)
+#define PP_DEST_RGB_PTR 	PP_REG(0x18)
+#define PP_QUANTIZER_PTR	PP_REG(0x1C)
+#define PP_PROCESS_FRAME_PARA	PP_REG(0x20)
+#define PP_SOURCE_FRAME_WIDTH	PP_REG(0x24)
+#define PP_DEST_DISPLAY_WIDTH	PP_REG(0x28)
+#define PP_DEST_IMAGE_SIZE	PP_REG(0x2C)
+#define PP_DEST_FRAME_FMT_CNTL	PP_REG(0x30)
+#define PP_RESIZE_INDEX		PP_REG(0x34)
+#define	PP_CSC_COEF_0123	PP_REG(0x38)
+#define	PP_CSC_COEF_4		PP_REG(0x3C)
+#define PP_RESIZE_COEF_TBL	PP_REG(0x100)
+
+/* resize table dimensions
+    dest pixel index    left/32    right/32    #src pixels to read
+    0                   [BC_COEF]  [BC_COEF]   [BC_NXT]
+    :
+    pp_tbl_max-1
+*/
+#define BC_NXT		2
+#define BC_COEF		5
+#define SZ_COEF		(1 << BC_COEF)
+#define SZ_NXT		(1 << BC_NXT)
+
+/* PP operations */
+#define EN_DEBLOCK 	0x02
+#define EN_DERING	0x04
+#define EN_CSC		0x10
+#define EN_MACROBLOCK	0x20
+#define EN_DEF		0x16
+#define EN_MASK		0x36
+#define EN_BIGDATA	0x1000
+#define EN_BIGQP	0x2000
+
+/* PP CSC tables */
+#define CSC_TBL_NONE	0x80
+#define CSC_TBL_REUSE	0x81
+#define CSC_TBL_A1	0x00
+#define CSC_TBL_A0	0x20
+#define CSC_TBL_B1	0x40
+#define CSC_TBL_B0	0x60
+/* converts from 4 decimal fixed point to hw setting & vice versa */
+#define PP_CSC_FP4_2_HW(coeff)	((((coeff) << 7) + 5000) / 10000)
+#define PP_CSC_HW_2_FP4(coeff)	((((coeff) * 10000) + 64) >> 7)
+
+#define PP_PIX_YUYV	0
+#define PP_PIX_YVYU	8
+#define PP_PIX_UYVY	16
+#define PP_PIX_VYUY	24
+
+/* PP size & width calculation macros */
+#define PP_CALC_QP_WIDTH(cfg)	\
+	(!((cfg)->operation & (EN_DEBLOCK | EN_DERING)) ? 0 : \
+		(((((cfg)->dim.in.width + 15) >> 4) + 3) & ~3))
+#define PP_CALC_Y_SIZE(cfg)		\
+	((cfg)->in_y_stride * (cfg)->dim.in.height)
+#define PP_CALC_CH_SIZE(cfg)		(PP_CALC_Y_SIZE(cfg) >> 2)
+#define PP_CALC_BPP(cfg) 		\
+	((cfg)->rgb_resolution > 16 ?  4 : ((cfg)->rgb_resolution >> 3))
+#define PP_CALC_YUV_SIZE(cfg)		\
+	((PP_CALC_Y_SIZE(cfg) * 3) >> 1)
+#define PP_CALC_QP_SIZE(cfg)		\
+	(PP_CALC_QP_WIDTH(cfg) * (((cfg)->dim.in.height + 15) >> 4))
+#define PP_CALC_DEST_WIDTH(cfg)	\
+	(((cfg)->out_stride & ~1) * PP_CALC_BPP(cfg))
+#define PP_CALC_DEST_SIZE(cfg)	\
+	((cfg)->dim.out.height * PP_CALC_DEST_WIDTH(cfg))
+
+/*
+ * physical addresses for bus mastering
+ * v=0 -> yuv packed
+ * v=0 & qp=0 -> yuv packed with qp appended
+ */
+typedef struct _emma_pp_ptr {
+	unsigned int y;		/* Y data (line align8) */
+	unsigned int u;		/* U data (line align4) */
+	unsigned int v;		/* V data (line align4) */
+	unsigned int qp;	/* Quantization (line align4) */
+} emma_pp_ptr;
+
+typedef struct _emma_pp_size {
+	int width;
+	int height;
+} emma_pp_size;
+
+/*
+ * if num.width != 0
+ * 	resize ratio = num.width : den.width
+ * else
+ * 	resize ratio = in.width : out.width
+ * same for height
+ */
+typedef struct _emma_pp_scale {
+	emma_pp_size num;
+	emma_pp_size den;
+	emma_pp_size in;	/* clip */
+	emma_pp_size out;	/* 0 -> same as in */
+} emma_pp_scale;
+
+typedef struct _emma_pp_cfg {
+	unsigned char operation;	/* OR of EN_xx defines */
+
+	/*
+	 * input color coeff
+	 * fixed pt 8 bits, steps of 1/128
+	 * csc[5] is 1 or 0 to indicate Y + 16
+	 * csc[0] is matrix id 0-3 while csc[1-5]=0
+	 */
+	unsigned short csc_table[6];
+
+	/*
+	 * Output color (shade width, shade offset, pixel resolution)
+	 * Eg. 16bpp RGB565 resolution, the values could be:
+	 * red_width = 5, green_width = 6, blue_width = 6
+	 * red_offset = 11, green_offset = 5, blue_offset = 0 (defaults)
+	 * rgb_resolution = 16 (default)
+	 * For YUV422: xxx_width=0, blue_offset=PP_PIX_xxx
+	 */
+	unsigned short red_width;
+	unsigned short green_width;
+	unsigned short blue_width;
+	/* if offsets are 0, the offsets are by width LSb to MSb B:G:R */
+	unsigned short red_offset;
+	unsigned short blue_offset;
+	unsigned short green_offset;
+	/* if resolution is 0, the minimum for the sum of widths is chosen */
+	short rgb_resolution;	/* 8,16,24 bpp only */
+
+	emma_pp_ptr ptr;	/* dma buffer pointers */
+	unsigned int outptr;	/* RGB/YUV output */
+	emma_pp_scale dim;	/* in/out dimensions */
+
+	/* pixels between two adjacent input Y rows */
+	unsigned short in_y_stride;	/* 0 = in_width */
+	/* PIXELS between two adjacent output rows */
+	unsigned short out_stride;	/* 0 = out_width */
+} emma_pp_cfg;
+
+int pp_ptr(unsigned long ptr);
+int pp_enable(int flag);
+int pp_cfg(vout_data * vout);
+int pp_init(vout_data * vout);
+int pp_num_last(void);
+void pp_exit(vout_data * vout);
+
+#endif				/* __MX27_PP_H__ */
diff --git a/drivers/media/video/mxc/output/mx27_v4l2_output.c b/drivers/media/video/mxc/output/mx27_v4l2_output.c
new file mode 100644
index 000000000000..a00f92d8e979
--- /dev/null
+++ b/drivers/media/video/mxc/output/mx27_v4l2_output.c
@@ -0,0 +1,1442 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx27_v4l2_output.c
+ *
+ * @brief MX27 V4L2 Video Output Driver
+ *
+ * Video4Linux2 Output Device using MX27 eMMA Post-processing functionality.
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/semaphore.h>
+#include <linux/poll.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+
+#include "mxc_v4l2_output.h"
+#include "mx27_pp.h"
+#include "../drivers/video/mxc/mx2fb.h"
+
+#define SDC_FG_FB_FORMAT	V4L2_PIX_FMT_RGB565
+
+struct v4l2_output mxc_outputs[1] = {
+	{
+	 .index = 0,
+	 .name = "DISP0 Video Out",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,	/* not really correct,
+						   but no other choice */
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN},
+};
+
+static int video_nr = 16;
+static spinlock_t g_lock = SPIN_LOCK_UNLOCKED;
+vout_data *g_vout;
+
+/* debug counters */
+uint32_t g_irq_cnt;
+uint32_t g_buf_output_cnt;
+uint32_t g_buf_q_cnt;
+uint32_t g_buf_dq_cnt;
+
+#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC
+static uint32_t g_output_fb = -1;
+static uint32_t g_fb_enabled = 0;
+static uint32_t g_pp_ready = 0;
+
+static int fb_event_notify(struct notifier_block *self,
+			   unsigned long action, void *data)
+{
+	struct fb_event *event = data;
+	struct fb_info *info = event->info;
+	unsigned long lock_flags;
+	int blank, i;
+
+	for (i = 0; i < num_registered_fb; i++)
+		if (registered_fb[i] == info)
+			break;
+
+	/*
+	 * Check if the event is sent by the framebuffer in which
+	 * the video is displayed.
+	 */
+	if (i != g_output_fb)
+		return 0;
+
+	switch (action) {
+	case FB_EVENT_BLANK:
+		blank = *(int *)event->data;
+		spin_lock_irqsave(&g_lock, lock_flags);
+		g_fb_enabled = !blank;
+		if (blank && g_pp_ready) {
+			if (pp_enable(1))
+				pr_debug("unable to enable PP\n");
+			g_pp_ready = 0;
+		}
+		spin_unlock_irqrestore(&g_lock, lock_flags);
+		break;
+	case FB_EVENT_MXC_EOF:
+		spin_lock_irqsave(&g_lock, lock_flags);
+		g_fb_enabled = 1;
+		if (g_pp_ready) {
+			if (pp_enable(1))
+				pr_debug("unable to enable PP\n");
+			g_pp_ready = 0;
+		}
+		spin_unlock_irqrestore(&g_lock, lock_flags);
+		break;
+	}
+
+	return 0;
+}
+
+static struct notifier_block fb_event_notifier = {
+	.notifier_call = fb_event_notify,
+};
+
+static struct notifier_block mx2fb_event_notifier = {
+	.notifier_call = fb_event_notify,
+};
+#endif
+
+#define QUEUE_SIZE (MAX_FRAME_NUM + 1)
+static __inline int queue_size(v4l_queue * q)
+{
+	if (q->tail >= q->head)
+		return (q->tail - q->head);
+	else
+		return ((q->tail + QUEUE_SIZE) - q->head);
+}
+
+static __inline int queue_buf(v4l_queue * q, int idx)
+{
+	if (((q->tail + 1) % QUEUE_SIZE) == q->head)
+		return -1;	/* queue full */
+	q->list[q->tail] = idx;
+	q->tail = (q->tail + 1) % QUEUE_SIZE;
+	return 0;
+}
+
+static __inline int dequeue_buf(v4l_queue * q)
+{
+	int ret;
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	ret = q->list[q->head];
+	q->head = (q->head + 1) % QUEUE_SIZE;
+	return ret;
+}
+
+static __inline int peek_next_buf(v4l_queue * q)
+{
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	return q->list[q->head];
+}
+
+static __inline unsigned long get_jiffies(struct timeval *t)
+{
+	struct timeval cur;
+
+	if (t->tv_usec >= 1000000) {
+		t->tv_sec += t->tv_usec / 1000000;
+		t->tv_usec = t->tv_usec % 1000000;
+	}
+
+	do_gettimeofday(&cur);
+	if ((t->tv_sec < cur.tv_sec)
+	    || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
+		return jiffies;
+
+	if (t->tv_usec < cur.tv_usec) {
+		cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
+		cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
+	} else {
+		cur.tv_sec = t->tv_sec - cur.tv_sec;
+		cur.tv_usec = t->tv_usec - cur.tv_usec;
+	}
+
+	return jiffies + timeval_to_jiffies(&cur);
+}
+
+/*!
+ * Private function to free buffers
+ *
+ * @param bufs_paddr	Array of physical address of buffers to be freed
+ *
+ * @param bufs_vaddr	Array of virtual address of buffers to be freed
+ *
+ * @param num_buf	Number of buffers to be freed
+ *
+ * @param size		Size for each buffer to be free
+ *
+ * @return status  0 success.
+ */
+static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+			    int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		if (bufs_vaddr[i] != 0) {
+			dma_free_coherent(0, size, bufs_vaddr[i],
+					  bufs_paddr[i]);
+			pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]);
+			bufs_paddr[i] = 0;
+			bufs_vaddr[i] = NULL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Private function to allocate buffers
+ *
+ * @param bufs_paddr	Output array of physical address of buffers allocated
+ *
+ * @param bufs_vaddr	Output array of virtual address of buffers allocated
+ *
+ * @param num_buf	Input number of buffers to allocate
+ *
+ * @param size		Input size for each buffer to allocate
+ *
+ * @return status	-0 Successfully allocated a buffer, -ENOBUFS failed.
+ */
+static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+				int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		bufs_vaddr[i] = dma_alloc_coherent(0, size,
+						   &bufs_paddr[i],
+						   GFP_DMA | GFP_KERNEL);
+
+		if (bufs_vaddr[i] == 0) {
+			mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size);
+			pr_debug("dma_alloc_coherent failed.\n");
+			return -ENOBUFS;
+		}
+		pr_debug("allocated @ paddr=0x%08X, size=%d.\n",
+			 (u32) bufs_paddr[i], size);
+	}
+
+	return 0;
+}
+
+static void mxc_v4l2out_timer_handler(unsigned long arg)
+{
+	int index;
+	unsigned long timeout;
+	unsigned long lock_flags;
+	vout_data *vout = (vout_data *) arg;
+
+	pr_debug("timer handler: %lu\n", jiffies);
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	if ((vout->state == STATE_STREAM_OFF)
+	    || (vout->state == STATE_STREAM_STOPPING)) {
+		pr_debug("stream has stopped\n");
+		goto exit0;
+	}
+
+	/*
+	 * If timer occurs before PP h/w is ready, then set the state to
+	 * paused and the timer will be set again when next buffer is queued
+	 * or PP completes.
+	 */
+	if (vout->ipu_buf[0] != -1) {
+		pr_debug("buffer is busy\n");
+		vout->state = STATE_STREAM_PAUSED;
+		goto exit0;
+	}
+
+	/* Dequeue buffer and pass to PP */
+	index = dequeue_buf(&vout->ready_q);
+	if (index == -1) {	/* no buffers ready, should never occur */
+		pr_debug("mxc_v4l2out: timer - no queued buffers ready\n");
+		goto exit0;
+	}
+
+	g_buf_dq_cnt++;
+	vout->frame_count++;
+	vout->ipu_buf[0] = index;
+
+	if (pp_ptr((unsigned int)vout->queue_buf_paddr[index])) {
+		pr_debug("unable to update buffer\n");
+		goto exit0;
+	}
+#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC
+	if (g_fb_enabled && (vout->v4l2_fb.flags != V4L2_FBUF_FLAG_OVERLAY))
+		g_pp_ready = 1;
+	else if (pp_enable(1)) {
+		pr_debug("unable to enable PP\n");
+		goto exit0;
+	}
+#else
+	if (pp_enable(1)) {
+		pr_debug("unable to enable PP\n");
+		goto exit0;
+	}
+#endif
+	pr_debug("enabled index %d\n", index);
+
+	/* Setup timer for next buffer */
+	index = peek_next_buf(&vout->ready_q);
+	pr_debug("next index %d\n", index);
+	if (index != -1) {
+		/* if timestamp is 0, then default to 30fps */
+		if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+		    && (vout->v4l2_bufs[index].timestamp.tv_usec == 0))
+			timeout =
+			    vout->start_jiffies + vout->frame_count * HZ / 30;
+		else
+			timeout =
+			    get_jiffies(&vout->v4l2_bufs[index].timestamp);
+
+		if (jiffies >= timeout) {
+			pr_debug("warning: timer timeout already expired.\n");
+		}
+
+		if (mod_timer(&vout->output_timer, timeout))
+			pr_debug("warning: timer was already set\n");
+
+		pr_debug("timer handler next schedule: %lu\n", timeout);
+	} else {
+		vout->state = STATE_STREAM_PAUSED;
+		pr_debug("timer handler paused\n");
+	}
+
+      exit0:
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+}
+
+irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id)
+{
+	int last_buf;
+	int index;
+	unsigned long timeout;
+	unsigned long lock_flags;
+	vout_data *vout = dev_id;
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	g_irq_cnt++;
+
+	if ((vout->state == STATE_STREAM_OFF)
+	    || (vout->state == STATE_STREAM_STOPPING)) {
+		spin_unlock_irqrestore(&g_lock, lock_flags);
+		return IRQ_HANDLED;
+	}
+
+	if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		struct fb_gwinfo gwinfo;
+
+		gwinfo.enabled = 1;
+		gwinfo.alpha_value = 255;
+		gwinfo.ck_enabled = 0;
+		gwinfo.xpos = vout->crop_current.left;
+		gwinfo.ypos = vout->crop_current.top;
+		gwinfo.base = (unsigned long)vout->display_bufs[pp_num_last()];
+		gwinfo.xres = vout->crop_current.width;
+		gwinfo.yres = vout->crop_current.height;
+		gwinfo.xres_virtual = vout->crop_current.width;
+		gwinfo.vs_reversed = 0;
+
+		mx2_gw_set(&gwinfo);
+	}
+
+	/* Process previous buffer */
+	last_buf = vout->ipu_buf[0];
+	pr_debug("last_buf %d g_irq_cnt %d\n", last_buf, g_irq_cnt);
+	if (last_buf != -1) {
+		g_buf_output_cnt++;
+		vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
+		queue_buf(&vout->done_q, last_buf);
+		vout->ipu_buf[0] = -1;
+		wake_up_interruptible(&vout->v4l_bufq);
+	}
+
+	/* Setup timer for next buffer, when stream has been paused */
+	if ((vout->state == STATE_STREAM_PAUSED)
+	    && ((index = peek_next_buf(&vout->ready_q)) != -1)) {
+		pr_debug("next index %d\n", index);
+		/* if timestamp is 0, then default to 30fps */
+		if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+		    && (vout->v4l2_bufs[index].timestamp.tv_usec == 0))
+			timeout =
+			    vout->start_jiffies + vout->frame_count * HZ / 30;
+		else
+			timeout =
+			    get_jiffies(&vout->v4l2_bufs[index].timestamp);
+
+		if (jiffies >= timeout) {
+			pr_debug("warning: timer timeout already expired.\n");
+		}
+
+		vout->state = STATE_STREAM_ON;
+
+		if (mod_timer(&vout->output_timer, timeout))
+			pr_debug("warning: timer was already set\n");
+
+		pr_debug("timer handler next schedule: %lu\n", timeout);
+	}
+
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * Start the output stream
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamon(vout_data * vout)
+{
+	unsigned long timeout;
+	int index;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state != STATE_STREAM_OFF)
+		return -EBUSY;
+
+	if (queue_size(&vout->ready_q) < 1) {
+		pr_debug("no buffers queued yet!\n");
+		return -EINVAL;
+	}
+
+	vout->ipu_buf[0] = -1;
+
+	if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		/* Free previously allocated buffer */
+		mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr,
+				 2, vout->display_buf_size);
+		/* Allocate buffers for foreground */
+		if (mxc_allocate_buffers(vout->display_bufs,
+					 vout->display_bufs_vaddr, 2,
+					 vout->display_buf_size) < 0) {
+			pr_debug("unable to allocate SDC FG buffers\n");
+			return -ENOMEM;
+		}
+	}
+
+	/* Configure PP */
+	if (pp_cfg(vout)) {
+		/* Free previously allocated buffer */
+		mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr,
+				 2, vout->display_buf_size);
+		pr_debug("failed to config PP.\n");
+		return -EINVAL;
+	}
+#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC
+	g_output_fb = vout->output_fb_num[vout->cur_disp_output];
+	g_fb_enabled = 0;
+	g_pp_ready = 0;
+	fb_register_client(&fb_event_notifier);
+	mx2fb_register_client(&mx2fb_event_notifier);
+#endif
+	vout->frame_count = 0;
+	vout->state = STATE_STREAM_ON;
+	index = peek_next_buf(&vout->ready_q);
+
+	/* if timestamp is 0, then default to 30fps */
+	if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+	    && (vout->v4l2_bufs[index].timestamp.tv_usec == 0))
+		timeout = jiffies;
+	else
+		timeout = get_jiffies(&vout->v4l2_bufs[index].timestamp);
+
+	if (jiffies >= timeout) {
+		pr_debug("warning: timer timeout already expired.\n");
+	}
+
+	vout->start_jiffies = vout->output_timer.expires = timeout;
+	pr_debug("STREAMON:Add timer %d timeout @ %lu jiffies, current = %lu\n",
+		 index, timeout, jiffies);
+	add_timer(&vout->output_timer);
+
+	return 0;
+}
+
+/*!
+ * Shut down the voutera
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamoff(vout_data * vout)
+{
+	int i, retval = 0;
+	unsigned long lock_flag = 0;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state == STATE_STREAM_OFF) {
+		return 0;
+	}
+
+	spin_lock_irqsave(&g_lock, lock_flag);
+
+	del_timer(&vout->output_timer);
+	pp_enable(0);		/* Disable PP */
+
+	if (vout->state == STATE_STREAM_ON) {
+		vout->state = STATE_STREAM_STOPPING;
+	}
+
+	spin_unlock_irqrestore(&g_lock, lock_flag);
+
+	vout->ready_q.head = vout->ready_q.tail = 0;
+	vout->done_q.head = vout->done_q.tail = 0;
+	for (i = 0; i < vout->buffer_cnt; i++) {
+		vout->v4l2_bufs[i].flags = 0;
+		vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+		vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+	}
+
+	vout->state = STATE_STREAM_OFF;
+
+	if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) {
+		struct fb_gwinfo gwinfo;
+
+		/* Disable graphic window */
+		gwinfo.enabled = 0;
+		mx2_gw_set(&gwinfo);
+	}
+#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC
+	g_output_fb = -1;
+	g_fb_enabled = 0;
+	g_pp_ready = 0;
+	fb_unregister_client(&fb_event_notifier);
+	mx2fb_unregister_client(&mx2fb_event_notifier);
+#endif
+
+	mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr,
+			 2, vout->display_buf_size);
+
+	return retval;
+}
+
+/*
+ * Valid whether the palette is supported
+ *
+ * @param palette  V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return 1 if supported, 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	return (palette == V4L2_PIX_FMT_YUV420);
+}
+
+/*
+ * Returns bits per pixel for given pixel format
+ *
+ * @param pixelformat  V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return bits per pixel of pixelformat
+ */
+static u32 fmt_to_bpp(u32 pixelformat)
+{
+	u32 bpp;
+
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_RGB565:
+		bpp = 16;
+		break;
+	case V4L2_PIX_FMT_BGR24:
+	case V4L2_PIX_FMT_RGB24:
+		bpp = 24;
+		break;
+	case V4L2_PIX_FMT_BGR32:
+	case V4L2_PIX_FMT_RGB32:
+		bpp = 32;
+		break;
+	default:
+		bpp = 8;
+		break;
+	}
+	return bpp;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_g_fmt(vout_data * vout, struct v4l2_format *f)
+{
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		return -EINVAL;
+	}
+	*f = vout->v2f;
+	return 0;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_s_fmt(vout_data * vout, struct v4l2_format *f)
+{
+	int retval = 0;
+	u32 size = 0;
+	u32 bytesperline;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		retval = -EINVAL;
+		goto err0;
+	}
+	if (!valid_mode(f->fmt.pix.pixelformat)) {
+		pr_debug("pixel format not supported\n");
+		retval = -EINVAL;
+		goto err0;
+	}
+
+	bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) /
+	    8;
+	if (f->fmt.pix.bytesperline < bytesperline) {
+		f->fmt.pix.bytesperline = bytesperline;
+	} else {
+		bytesperline = f->fmt.pix.bytesperline;
+	}
+
+	switch (f->fmt.pix.pixelformat) {
+	case V4L2_PIX_FMT_YUV422P:
+		/* byteperline for YUV planar formats is for
+		   Y plane only */
+		size = bytesperline * f->fmt.pix.height * 2;
+		break;
+	case V4L2_PIX_FMT_YUV420:
+		size = (bytesperline * f->fmt.pix.height * 3) / 2;
+		break;
+	default:
+		size = bytesperline * f->fmt.pix.height;
+		break;
+	}
+
+	/* Return the actual size of the image to the app */
+	f->fmt.pix.sizeimage = size;
+
+	vout->v2f.fmt.pix.sizeimage = size;
+	vout->v2f.fmt.pix.width = f->fmt.pix.width;
+	vout->v2f.fmt.pix.height = f->fmt.pix.height;
+	vout->v2f.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
+	vout->v2f.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
+
+	retval = 0;
+      err0:
+	return retval;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_get_v42lout_control(vout_data * vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0;
+	case V4L2_CID_VFLIP:
+		return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0;
+	case (V4L2_CID_PRIVATE_BASE + 1):
+		return vout->rotate;
+	default:
+		return -EINVAL;
+	}
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_set_v42lout_control(vout_data * vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+	case V4L2_CID_VFLIP:
+	case V4L2_CID_MXC_ROT:
+		return 0;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * V4L2 interface - open function
+ *
+ * @param inode        structure inode *
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l2out_open(struct inode *inode, struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+	int err;
+
+	if (!vout) {
+		pr_info("Internal error, vout_data not found!\n");
+		return -ENODEV;
+	}
+
+	down(&vout->busy_lock);
+
+	err = -EINTR;
+	if (signal_pending(current))
+		goto oops;
+
+	if (vout->open_count++ == 0) {
+		pp_init(vout);
+
+		init_waitqueue_head(&vout->v4l_bufq);
+
+		init_timer(&vout->output_timer);
+		vout->output_timer.function = mxc_v4l2out_timer_handler;
+		vout->output_timer.data = (unsigned long)vout;
+
+		vout->state = STATE_STREAM_OFF;
+		g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0;
+
+	}
+
+	file->private_data = dev;
+	up(&vout->busy_lock);
+	return 0;
+
+      oops:
+	up(&vout->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L2 interface - close function
+ *
+ * @param inode    struct inode *
+ *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int mxc_v4l2out_close(struct inode *inode, struct file *file)
+{
+	struct video_device *dev = file->private_data;
+	vout_data *vout = video_get_drvdata(dev);
+
+	if (--vout->open_count == 0) {
+		pr_debug("release resource\n");
+
+		pp_exit(vout);
+		if (vout->state != STATE_STREAM_OFF)
+			mxc_v4l2out_streamoff(vout);
+
+		file->private_data = NULL;
+
+		mxc_free_buffers(vout->queue_buf_paddr,
+				 vout->queue_buf_vaddr,
+				 vout->buffer_cnt, vout->queue_buf_size);
+		vout->buffer_cnt = 0;
+		mxc_free_buffers(vout->display_bufs,
+				 vout->display_bufs_vaddr,
+				 2, vout->display_buf_size);
+
+		/* capture off */
+		wake_up_interruptible(&vout->v4l_bufq);
+	}
+
+	return 0;
+}
+
+/*!
+ * V4L2 interface - ioctl function
+ *
+ * @param inode      struct inode *
+ *
+ * @param file       struct file *
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void *
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static int
+mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file,
+		     unsigned int ioctlnr, void *arg)
+{
+	struct video_device *dev = file->private_data;
+	vout_data *vout = video_get_drvdata(dev);
+	int retval = 0;
+	int i = 0;
+
+	if (!vout)
+		return -EBADF;
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+	case VIDIOC_QUERYCAP:
+		{
+			struct v4l2_capability *cap = arg;
+			strcpy(cap->driver, "mxc_v4l2_output");
+			cap->version = 0;
+			cap->capabilities =
+			    V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
+			cap->card[0] = '\0';
+			cap->bus_info[0] = '\0';
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_FMT:
+		{
+			struct v4l2_format *gf = arg;
+			retval = mxc_v4l2out_g_fmt(vout, gf);
+			break;
+		}
+	case VIDIOC_S_FMT:
+		{
+			struct v4l2_format *sf = arg;
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+			retval = mxc_v4l2out_s_fmt(vout, sf);
+			break;
+		}
+	case VIDIOC_REQBUFS:
+		{
+			struct v4l2_requestbuffers *req = arg;
+			if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (req->memory != V4L2_MEMORY_MMAP)) {
+				pr_debug
+				    ("VIDIOC_REQBUFS: incorrect buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			if (req->count == 0)
+				mxc_v4l2out_streamoff(vout);
+
+			if (vout->state == STATE_STREAM_OFF) {
+				if (vout->queue_buf_paddr[0] != 0) {
+					mxc_free_buffers(vout->queue_buf_paddr,
+							 vout->queue_buf_vaddr,
+							 vout->buffer_cnt,
+							 vout->queue_buf_size);
+					pr_debug
+					    ("VIDIOC_REQBUFS: freed buffers\n");
+				}
+				vout->buffer_cnt = 0;
+			} else {
+				pr_debug("VIDIOC_REQBUFS: Buffer is in use\n");
+				retval = -EBUSY;
+				break;
+			}
+
+			if (req->count == 0)
+				break;
+
+			if (req->count < MIN_FRAME_NUM) {
+				req->count = MIN_FRAME_NUM;
+			} else if (req->count > MAX_FRAME_NUM) {
+				req->count = MAX_FRAME_NUM;
+			}
+			vout->buffer_cnt = req->count;
+			vout->queue_buf_size =
+			    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+
+			retval = mxc_allocate_buffers(vout->queue_buf_paddr,
+						      vout->queue_buf_vaddr,
+						      vout->buffer_cnt,
+						      vout->queue_buf_size);
+			if (retval < 0)
+				break;
+
+			/* Init buffer queues */
+			vout->done_q.head = 0;
+			vout->done_q.tail = 0;
+			vout->ready_q.head = 0;
+			vout->ready_q.tail = 0;
+
+			for (i = 0; i < vout->buffer_cnt; i++) {
+				memset(&(vout->v4l2_bufs[i]), 0,
+				       sizeof(vout->v4l2_bufs[i]));
+				vout->v4l2_bufs[i].flags = 0;
+				vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP;
+				vout->v4l2_bufs[i].index = i;
+				vout->v4l2_bufs[i].type =
+				    V4L2_BUF_TYPE_VIDEO_OUTPUT;
+				vout->v4l2_bufs[i].length =
+				    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+				vout->v4l2_bufs[i].m.offset =
+				    (unsigned long)vout->queue_buf_paddr[i];
+				vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+				vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+			}
+			break;
+		}
+	case VIDIOC_QUERYBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			u32 type = buf->type;
+			int index = buf->index;
+
+			if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt)) {
+				pr_debug
+				    ("VIDIOC_QUERYBUFS: incorrect buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+			down(&vout->param_lock);
+			memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf));
+			up(&vout->param_lock);
+			break;
+		}
+	case VIDIOC_QBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int index = buf->index;
+			unsigned long lock_flags;
+			unsigned long timeout;
+
+			if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt) || (buf->flags != 0)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			pr_debug("VIDIOC_QBUF: %d\n", buf->index);
+
+			spin_lock_irqsave(&g_lock, lock_flags);
+
+			memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf));
+			vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED;
+
+			g_buf_q_cnt++;
+			queue_buf(&vout->ready_q, index);
+
+			if (vout->state == STATE_STREAM_PAUSED) {
+				index = peek_next_buf(&vout->ready_q);
+
+				/* if timestamp is 0, then default to 30fps */
+				if ((vout->v4l2_bufs[index].timestamp.tv_sec ==
+				     0)
+				    && (vout->v4l2_bufs[index].timestamp.
+					tv_usec == 0))
+					timeout =
+					    vout->start_jiffies +
+					    vout->frame_count * HZ / 30;
+				else
+					timeout =
+					    get_jiffies(&vout->v4l2_bufs[index].
+							timestamp);
+
+				if (jiffies >= timeout) {
+					pr_debug
+					    ("warning: timer timeout already expired.\n");
+				}
+
+				vout->output_timer.expires = timeout;
+				pr_debug
+				    ("QBUF:Add timer %d timeout @ %lu jiffies, "
+				     "current = %lu\n", index, timeout,
+				     jiffies);
+				add_timer(&vout->output_timer);
+				vout->state = STATE_STREAM_ON;
+			}
+
+			spin_unlock_irqrestore(&g_lock, lock_flags);
+			break;
+		}
+	case VIDIOC_DQBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int idx;
+
+			pr_debug("VIDIOC_DQBUF: q size = %d\n",
+				 queue_size(&vout->done_q));
+
+			if ((queue_size(&vout->done_q) == 0) &&
+			    (file->f_flags & O_NONBLOCK)) {
+				retval = -EAGAIN;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout(vout->v4l_bufq,
+							      queue_size(&vout->
+									 done_q)
+							      != 0, 10 * HZ)) {
+				pr_debug("VIDIOC_DQBUF: timeout\n");
+				retval = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				pr_debug("VIDIOC_DQBUF: interrupt received\n");
+				retval = -ERESTARTSYS;
+				break;
+			}
+			idx = dequeue_buf(&vout->done_q);
+			if (idx == -1) {	/* No frame free */
+				pr_debug
+				    ("VIDIOC_DQBUF: no free buffers, returning\n");
+				retval = -EAGAIN;
+				break;
+			}
+			if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) ==
+			    0)
+				pr_debug
+				    ("VIDIOC_DQBUF: buffer in done q, but not "
+				     "flagged as done\n");
+
+			vout->v4l2_bufs[idx].flags = 0;
+			memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf));
+			pr_debug("VIDIOC_DQBUF: %d\n", buf->index);
+			break;
+		}
+	case VIDIOC_STREAMON:
+		{
+			retval = mxc_v4l2out_streamon(vout);
+			break;
+		}
+	case VIDIOC_STREAMOFF:
+		{
+			retval = mxc_v4l2out_streamoff(vout);
+			break;
+		}
+	case VIDIOC_G_CTRL:
+		{
+			retval = mxc_get_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_S_CTRL:
+		{
+			retval = mxc_set_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_CROPCAP:
+		{
+			struct v4l2_cropcap *cap = arg;
+
+			if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			cap->bounds = vout->crop_bounds[vout->cur_disp_output];
+			cap->defrect = vout->crop_bounds[vout->cur_disp_output];
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			crop->c = vout->crop_current;
+			break;
+		}
+	case VIDIOC_S_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+			struct v4l2_rect *b =
+			    &(vout->crop_bounds[vout->cur_disp_output]);
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.height < 0) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.width < 0) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (crop->c.top < b->top)
+				crop->c.top = b->top;
+			if (crop->c.top > b->top + b->height)
+				crop->c.top = b->top + b->height;
+			if (crop->c.height > b->top - crop->c.top + b->height)
+				crop->c.height =
+				    b->top - crop->c.top + b->height;
+
+			if (crop->c.left < b->left)
+				crop->c.top = b->left;
+			if (crop->c.left > b->left + b->width)
+				crop->c.top = b->left + b->width;
+			if (crop->c.width > b->left - crop->c.left + b->width)
+				crop->c.width =
+				    b->left - crop->c.left + b->width;
+
+			/* stride line limitation */
+			crop->c.height -= crop->c.height % 8;
+			crop->c.width -= crop->c.width % 8;
+
+			vout->crop_current = crop->c;
+
+			vout->display_buf_size = vout->crop_current.width *
+			    vout->crop_current.height;
+			vout->display_buf_size *=
+			    fmt_to_bpp(SDC_FG_FB_FORMAT) / 8;
+			break;
+		}
+	case VIDIOC_ENUMOUTPUT:
+		{
+			struct v4l2_output *output = arg;
+
+			if ((output->index >= 2) ||
+			    (vout->output_enabled[output->index] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			*output = mxc_outputs[0];
+			output->name[4] = '0' + output->index;
+			break;
+		}
+	case VIDIOC_G_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			*p_output_num = vout->cur_disp_output;
+			break;
+		}
+	case VIDIOC_S_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			if ((*p_output_num >= 2) ||
+			    (vout->output_enabled[*p_output_num] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+
+			vout->cur_disp_output = *p_output_num;
+			break;
+		}
+	case VIDIOC_G_FBUF:
+		{
+			struct v4l2_framebuffer *fb = arg;
+			*fb = vout->v4l2_fb;
+			break;
+		}
+	case VIDIOC_S_FBUF:
+		{
+			struct v4l2_framebuffer *fb = arg;
+			vout->v4l2_fb = *fb;
+			vout->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+			break;
+		}
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_G_PARM:
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_STD:
+	case VIDIOC_S_STD:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&vout->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L2 interface - ioctl function
+ *
+ * @return  None
+ */
+static int
+mxc_v4l2out_ioctl(struct inode *inode, struct file *file,
+		  unsigned int cmd, unsigned long arg)
+{
+	return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl);
+}
+
+/*!
+ * V4L2 interface - mmap function
+ *
+ * @param file          structure file *
+ *
+ * @param vma           structure vm_area_struct *
+ *
+ * @return status       0 Success, EINTR busy lock error,
+ *                      ENOBUFS remap_page error
+ */
+static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *dev = file->private_data;
+	unsigned long start = vma->vm_start;
+	unsigned long size = vma->vm_end - vma->vm_start;
+	int res = 0;
+	vout_data *vout = video_get_drvdata(dev);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	/* make buffers write-thru cacheable */
+	vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) &
+				     ~L_PTE_BUFFERABLE);
+
+	if (remap_pfn_range(vma, start, vma->vm_pgoff, size, vma->vm_page_prot)) {
+		pr_debug("mxc_mmap(V4L)i - remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+      mxc_mmap_exit:
+	up(&vout->busy_lock);
+	return res;
+}
+
+/*!
+ * V4L2 interface - poll function
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait)
+{
+	struct video_device *dev = file->private_data;
+	vout_data *vout = video_get_drvdata(dev);
+
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	queue = &vout->v4l_bufq;
+	poll_wait(file, queue, wait);
+
+	up(&vout->busy_lock);
+	return res;
+}
+
+static struct file_operations mxc_v4l2out_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_v4l2out_open,
+	.release = mxc_v4l2out_close,
+	.ioctl = mxc_v4l2out_ioctl,
+	.mmap = mxc_v4l2out_mmap,
+	.poll = mxc_v4l2out_poll,
+};
+
+static struct video_device mxc_v4l2out_template = {
+	.name = "MXC Video Output",
+	.vfl_type = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING,
+	.fops = &mxc_v4l2out_fops,
+	.release = video_device_release,
+};
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxc_v4l2out_probe(struct platform_device *pdev)
+{
+	int i;
+	vout_data *vout;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL);
+
+	if (!vout)
+		return 0;
+
+	memset(vout, 0, sizeof(vout_data));
+
+	vout->video_dev = video_device_alloc();
+	if (vout->video_dev == NULL)
+		return -1;
+	vout->video_dev->minor = -1;
+
+	*(vout->video_dev) = mxc_v4l2out_template;
+
+	/* register v4l device */
+	if (video_register_device(vout->video_dev,
+				  VFL_TYPE_GRABBER, video_nr) == -1) {
+		pr_debug("video_register_device failed\n");
+		return 0;
+	}
+	pr_debug("mxc_v4l2out: registered device video%d\n",
+		 vout->video_dev->minor & 0x1f);
+
+	video_set_drvdata(vout->video_dev, vout);
+
+	init_MUTEX(&vout->param_lock);
+	init_MUTEX(&vout->busy_lock);
+
+	/* setup outputs and cropping */
+	vout->cur_disp_output = -1;
+	for (i = 0; i < num_registered_fb; i++) {
+		char *idstr = registered_fb[i]->fix.id;
+		if (strncmp(idstr, "DISP", 4) == 0) {
+			int disp_num = i;
+			vout->crop_bounds[disp_num].left = 0;
+			vout->crop_bounds[disp_num].top = 0;
+			vout->crop_bounds[disp_num].width =
+			    registered_fb[i]->var.xres;
+			vout->crop_bounds[disp_num].height =
+			    registered_fb[i]->var.yres;
+			vout->output_enabled[disp_num] = true;
+			vout->output_fb_num[disp_num] = i;
+			if (vout->cur_disp_output == -1)
+				vout->cur_disp_output = disp_num;
+		}
+
+	}
+	vout->crop_current = vout->crop_bounds[vout->cur_disp_output];
+
+	/* Setup framebuffer parameters */
+	vout->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
+	vout->v4l2_fb.flags = V4L2_FBUF_FLAG_PRIMARY;
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_v4l2out_driver = {
+	.driver = {
+		   .name = "MXC Video Output",
+		   .owner = THIS_MODULE,
+		   .bus = &platform_bus_type,
+		   },
+	.probe = mxc_v4l2out_probe,
+	.remove = NULL,
+};
+
+static void camera_platform_release(struct device *device)
+{
+}
+
+static struct platform_device mxc_v4l2out_device = {
+	.name = "MXC Video Output",
+	.dev = {
+		.release = camera_platform_release,
+		},
+	.id = 0,
+};
+
+/*!
+ * mxc v4l2 init function
+ *
+ */
+static int mxc_v4l2out_init(void)
+{
+	u8 err = 0;
+
+	err = platform_driver_register(&mxc_v4l2out_driver);
+	if (err == 0) {
+		platform_device_register(&mxc_v4l2out_device);
+	}
+	return err;
+}
+
+/*!
+ * mxc v4l2 cleanup function
+ *
+ */
+static void mxc_v4l2out_clean(void)
+{
+	pr_debug("unregistering video\n");
+
+	video_unregister_device(g_vout->video_dev);
+
+	platform_driver_unregister(&mxc_v4l2out_driver);
+	platform_device_unregister(&mxc_v4l2out_device);
+	kfree(g_vout);
+	g_vout = NULL;
+}
+
+module_init(mxc_v4l2out_init);
+module_exit(mxc_v4l2out_clean);
+
+module_param(video_nr, int, 0444);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2-driver for MXC video output");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c b/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c
new file mode 100644
index 000000000000..4a82da2d7d00
--- /dev/null
+++ b/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c
@@ -0,0 +1,1926 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/media/video/mxc/output/mxc_v4l2_output.c
+ *
+ * @brief MXC V4L2 Video Output Driver
+ *
+ * Video4Linux2 Output Device using MXC IPU Post-processing functionality.
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/semaphore.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/mxcfb.h>
+#include <mach/ipu.h>
+
+#include "mxc_v4l2_output.h"
+
+vout_data *g_vout;
+#define SDC_FG_FB_FORMAT        IPU_PIX_FMT_RGB565
+
+struct v4l2_output mxc_outputs[2] = {
+	{
+	 .index = MXC_V4L2_OUT_2_SDC,
+	 .name = "DISP3 Video Out",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,	/* not really correct,
+						   but no other choice */
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN},
+	{
+	 .index = MXC_V4L2_OUT_2_ADC,
+	 .name = "DISPx Video Out",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,	/* not really correct,
+						   but no other choice */
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN}
+};
+
+static int video_nr = 16;
+static DEFINE_SPINLOCK(g_lock);
+static unsigned int g_pp_out_number;
+static unsigned int g_pp_in_number;
+
+/* debug counters */
+uint32_t g_irq_cnt;
+uint32_t g_buf_output_cnt;
+uint32_t g_buf_q_cnt;
+uint32_t g_buf_dq_cnt;
+
+static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+	return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) :
+		((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF)
+		 : (((uint32_t) ch >> 16) & 0xFF)));
+};
+
+static inline uint32_t DMAParamAddr(uint32_t dma_ch)
+{
+	return (0x10000 | (dma_ch << 4));
+};
+
+#define QUEUE_SIZE (MAX_FRAME_NUM + 1)
+static inline int queue_size(v4l_queue * q)
+{
+	if (q->tail >= q->head)
+		return (q->tail - q->head);
+	else
+		return ((q->tail + QUEUE_SIZE) - q->head);
+}
+
+static inline int queue_buf(v4l_queue * q, int idx)
+{
+	if (((q->tail + 1) % QUEUE_SIZE) == q->head)
+		return -1;	/* queue full */
+	q->list[q->tail] = idx;
+	q->tail = (q->tail + 1) % QUEUE_SIZE;
+	return 0;
+}
+
+static inline int dequeue_buf(v4l_queue * q)
+{
+	int ret;
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	ret = q->list[q->head];
+	q->head = (q->head + 1) % QUEUE_SIZE;
+	return ret;
+}
+
+static inline int peek_next_buf(v4l_queue * q)
+{
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	return q->list[q->head];
+}
+
+static inline unsigned long get_jiffies(struct timeval *t)
+{
+	struct timeval cur;
+
+	if (t->tv_usec >= 1000000) {
+		t->tv_sec += t->tv_usec / 1000000;
+		t->tv_usec = t->tv_usec % 1000000;
+	}
+
+	do_gettimeofday(&cur);
+	if ((t->tv_sec < cur.tv_sec)
+	    || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
+		return jiffies;
+
+	if (t->tv_usec < cur.tv_usec) {
+		cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
+		cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
+	} else {
+		cur.tv_sec = t->tv_sec - cur.tv_sec;
+		cur.tv_usec = t->tv_usec - cur.tv_usec;
+	}
+
+	return jiffies + timeval_to_jiffies(&cur);
+}
+
+/*!
+ * Private function to free buffers
+ *
+ * @param bufs_paddr	Array of physical address of buffers to be freed
+ *
+ * @param bufs_vaddr	Array of virtual address of buffers to be freed
+ *
+ * @param num_buf	Number of buffers to be freed
+ *
+ * @param size		Size for each buffer to be free
+ *
+ * @return status  0 success.
+ */
+static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+			    int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		if (bufs_vaddr[i] != 0) {
+			dma_free_coherent(0, size, bufs_vaddr[i],
+					  bufs_paddr[i]);
+			pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]);
+			bufs_paddr[i] = 0;
+			bufs_vaddr[i] = NULL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Private function to allocate buffers
+ *
+ * @param bufs_paddr	Output array of physical address of buffers allocated
+ *
+ * @param bufs_vaddr	Output array of virtual address of buffers allocated
+ *
+ * @param num_buf	Input number of buffers to allocate
+ *
+ * @param size		Input size for each buffer to allocate
+ *
+ * @return status	-0 Successfully allocated a buffer, -ENOBUFS failed.
+ */
+static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+				int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		bufs_vaddr[i] = dma_alloc_coherent(0, size,
+						   &bufs_paddr[i],
+						   GFP_DMA | GFP_KERNEL);
+
+		if (bufs_vaddr[i] == 0) {
+			mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size);
+			printk(KERN_ERR "dma_alloc_coherent failed.\n");
+			return -ENOBUFS;
+		}
+		pr_debug("allocated @ paddr=0x%08X, size=%d.\n",
+			 (u32) bufs_paddr[i], size);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns bits per pixel for given pixel format
+ *
+ * @param pixelformat  V4L2_PIX_FMT_RGB565,
+ * 		       V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return bits per pixel of pixelformat
+ */
+static u32 fmt_to_bpp(u32 pixelformat)
+{
+	u32 bpp;
+
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_RGB565:
+		bpp = 16;
+		break;
+	case V4L2_PIX_FMT_BGR24:
+	case V4L2_PIX_FMT_RGB24:
+		bpp = 24;
+		break;
+	case V4L2_PIX_FMT_BGR32:
+	case V4L2_PIX_FMT_RGB32:
+		bpp = 32;
+		break;
+	default:
+		bpp = 8;
+		break;
+	}
+	return bpp;
+}
+
+static u32 bpp_to_fmt(struct fb_info *fbi)
+{
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	if (fbi->var.bits_per_pixel == 24)
+		return V4L2_PIX_FMT_BGR24;
+	else if (fbi->var.bits_per_pixel == 32)
+		return V4L2_PIX_FMT_BGR32;
+	else if (fbi->var.bits_per_pixel == 16)
+		return V4L2_PIX_FMT_RGB565;
+
+	return 0;
+}
+
+static void mxc_v4l2out_timer_handler(unsigned long arg)
+{
+	int index;
+	unsigned long timeout;
+	unsigned long lock_flags = 0;
+	vout_data *vout = (vout_data *) arg;
+
+	dev_dbg(vout->video_dev->dev, "timer handler: %lu\n", jiffies);
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	if ((vout->state == STATE_STREAM_STOPPING)
+	    || (vout->state == STATE_STREAM_OFF))
+		goto exit0;
+	/*
+	 * If timer occurs before IPU h/w is ready, then set the state to
+	 * paused and the timer will be set again when next buffer is queued
+	 * or PP comletes
+	 */
+	if (vout->ipu_buf[0] != -1) {
+		dev_dbg(vout->video_dev->dev, "IPU buffer busy\n");
+		vout->state = STATE_STREAM_PAUSED;
+		goto exit0;
+	}
+
+	/* One frame buffer should be ready here */
+	if (vout->frame_count % 2 == 1) {
+		/* set BUF0 rdy */
+		if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0) <
+		    0)
+			pr_debug("error selecting display buf 0");
+	} else {
+		if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1) <
+		    0)
+			pr_debug("error selecting display buf 1");
+	}
+
+	/* Dequeue buffer and pass to IPU */
+	index = dequeue_buf(&vout->ready_q);
+	if (index == -1) {	/* no buffers ready, should never occur */
+		dev_err(vout->video_dev->dev,
+			"mxc_v4l2out: timer - no queued buffers ready\n");
+		goto exit0;
+	}
+
+	g_buf_dq_cnt++;
+	vout->frame_count++;
+	vout->ipu_buf[1] = vout->ipu_buf[0] = index;
+
+	if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+				      0,
+				      vout->v4l2_bufs[vout->ipu_buf[0]].m.
+				      offset) < 0)
+		goto exit0;
+
+	if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+				      1,
+				      vout->v4l2_bufs[vout->ipu_buf[0]].m.
+				      offset + vout->v2f.fmt.pix.width / 2) < 0)
+		goto exit0;
+
+	/* All buffer should now ready in IPU out, tranfer to display buf */
+	if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
+				      0,
+				      vout->
+				      display_bufs[(vout->frame_count -
+						    1) % 2]) < 0) {
+		dev_err(vout->video_dev->dev,
+			"unable to update buffer %d address\n",
+			vout->next_rdy_ipu_buf);
+		goto exit0;
+	}
+	if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
+				      1,
+				      vout->
+				      display_bufs[(vout->frame_count -
+						    1) % 2] +
+				      vout->crop_current.width / 2 *
+				      bytes_per_pixel(SDC_FG_FB_FORMAT)) < 0) {
+		dev_err(vout->video_dev->dev,
+			"unable to update buffer %d address\n",
+			vout->next_rdy_ipu_buf);
+		goto exit0;
+	}
+
+	if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0) < 0) {
+		dev_err(vout->video_dev->dev,
+			"unable to set IPU buffer ready\n");
+		goto exit0;
+	}
+
+	if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0) < 0) {
+		dev_err(vout->video_dev->dev,
+			"unable to set IPU buffer ready\n");
+		goto exit0;
+	}
+
+	/* Setup timer for next buffer */
+	index = peek_next_buf(&vout->ready_q);
+	if (index != -1) {
+		/* if timestamp is 0, then default to 30fps */
+		if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+		    && (vout->v4l2_bufs[index].timestamp.tv_usec == 0))
+			timeout =
+			    vout->start_jiffies + vout->frame_count * HZ / 30;
+		else
+			timeout =
+			    get_jiffies(&vout->v4l2_bufs[index].timestamp);
+
+		if (jiffies >= timeout) {
+			dev_dbg(vout->video_dev->dev,
+				"warning: timer timeout already expired.\n");
+		}
+		if (mod_timer(&vout->output_timer, timeout))
+			dev_dbg(vout->video_dev->dev,
+				"warning: timer was already set\n");
+
+		dev_dbg(vout->video_dev->dev,
+			"timer handler next schedule: %lu\n", timeout);
+	} else {
+		vout->state = STATE_STREAM_PAUSED;
+	}
+
+exit0:
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+}
+
+extern void _ipu_write_param_mem(uint32_t addr, uint32_t *data,
+				 uint32_t numWords);
+
+static irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id)
+{
+	unsigned long lock_flags = 0;
+	vout_data *vout = dev_id;
+	uint32_t u_offset;
+	uint32_t v_offset;
+	uint32_t local_params[4];
+	uint32_t width, height;
+	uint32_t dma_chan;
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+	g_irq_cnt++;
+
+	dma_chan = channel_2_dma(vout->post_proc_ch, IPU_INPUT_BUFFER);
+	memset(&local_params, 0, sizeof(local_params));
+
+	if (g_pp_in_number % 2 == 1) {
+		u_offset = vout->offset.u_offset - vout->v2f.fmt.pix.width / 4;
+		v_offset = vout->offset.v_offset - vout->v2f.fmt.pix.width / 4;
+		width = vout->v2f.fmt.pix.width / 2;
+		height = vout->v2f.fmt.pix.height;
+		local_params[3] =
+		    (uint32_t) ((width - 1) << 12) | ((uint32_t) (height -
+								  1) << 24);
+		local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32));
+		local_params[2] = u_offset >> (64 - 53);
+		local_params[2] |= v_offset << (79 - 64);
+		local_params[3] |= v_offset >> (96 - 79);
+		_ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4);
+
+		if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1) <
+		    0) {
+			dev_err(vout->video_dev->dev,
+				"unable to set IPU buffer ready\n");
+		}
+	} else {
+		u_offset = vout->offset.u_offset;
+		v_offset = vout->offset.v_offset;
+		width = vout->v2f.fmt.pix.width / 2;
+		height = vout->v2f.fmt.pix.height;
+		local_params[3] =
+		    (uint32_t) ((width - 1) << 12) | ((uint32_t) (height -
+								  1) << 24);
+		local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32));
+		local_params[2] = u_offset >> (64 - 53);
+		local_params[2] |= v_offset << (79 - 64);
+		local_params[3] |= v_offset >> (96 - 79);
+		_ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4);
+	}
+	g_pp_in_number++;
+
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxc_v4l2out_pp_out_irq_handler(int irq, void *dev_id)
+{
+	vout_data *vout = dev_id;
+	int index;
+	unsigned long timeout;
+	u32 lock_flags = 0;
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	if (g_pp_out_number % 2 == 1) {
+		if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1)
+		    < 0) {
+			dev_err(vout->video_dev->dev,
+				"unable to set IPU buffer ready\n");
+		}
+	} else {
+		if (vout->ipu_buf[0] != -1) {
+			vout->v4l2_bufs[vout->ipu_buf[0]].flags =
+			    V4L2_BUF_FLAG_DONE;
+			queue_buf(&vout->done_q, vout->ipu_buf[0]);
+			wake_up_interruptible(&vout->v4l_bufq);
+			vout->ipu_buf[0] = -1;
+		}
+		if (vout->state == STATE_STREAM_STOPPING) {
+			if ((vout->ipu_buf[0] == -1)
+			    && (vout->ipu_buf[1] == -1))
+				vout->state = STATE_STREAM_OFF;
+		} else if ((vout->state == STATE_STREAM_PAUSED)
+			   && ((index = peek_next_buf(&vout->ready_q)) != -1)) {
+			/*!
+			 * Setup timer for next buffer,
+			 * when stream has been paused
+			 */
+			pr_debug("next index %d\n", index);
+
+			/* if timestamp is 0, then default to 30fps */
+			if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+			    && (vout->v4l2_bufs[index].timestamp.tv_usec == 0))
+				timeout =
+				    vout->start_jiffies +
+				    vout->frame_count * HZ / 30;
+			else
+				timeout =
+				    get_jiffies(&vout->v4l2_bufs[index].
+						timestamp);
+
+			if (jiffies >= timeout) {
+				pr_debug
+				    ("warning: timer timeout"
+				     "already expired.\n");
+			}
+
+			vout->state = STATE_STREAM_ON;
+
+			if (mod_timer(&vout->output_timer, timeout))
+				pr_debug("warning: timer was already set\n");
+
+			pr_debug("timer handler next schedule: %lu\n", timeout);
+		}
+	}
+	g_pp_out_number++;
+
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * Start the output stream
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamon(vout_data *vout)
+{
+	struct device *dev = vout->video_dev->dev;
+	ipu_channel_params_t params;
+	struct mxcfb_pos fb_pos;
+	struct fb_var_screeninfo fbvar;
+	struct fb_info *fbi =
+	    registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	int pp_in_buf[2];
+	u16 out_width;
+	u16 out_height;
+	ipu_channel_t display_input_ch = MEM_PP_MEM;
+	bool use_direct_adc = false;
+	mm_segment_t old_fs;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state != STATE_STREAM_OFF)
+		return -EBUSY;
+
+	if (queue_size(&vout->ready_q) < 2) {
+		dev_err(dev, "2 buffers not been queued yet!\n");
+		return -EINVAL;
+	}
+
+	out_width = vout->crop_current.width;
+	out_height = vout->crop_current.height;
+
+	vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0;
+	vout->ipu_buf[0] = pp_in_buf[0] = dequeue_buf(&vout->ready_q);
+	vout->ipu_buf[1] = pp_in_buf[1] = vout->ipu_buf[0];
+	vout->frame_count = 1;
+	g_pp_out_number = 1;
+	g_pp_in_number = 1;
+
+	ipu_enable_irq(IPU_IRQ_PP_IN_EOF);
+	ipu_enable_irq(IPU_IRQ_PP_OUT_EOF);
+
+	/* Init Display Channel */
+#ifdef CONFIG_FB_MXC_ASYNC_PANEL
+	if (vout->cur_disp_output < DISP3) {
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, 0);
+		fbi = NULL;
+		if (ipu_can_rotate_in_place(vout->rotate)) {
+			dev_dbg(dev, "Using PP direct to ADC channel\n");
+			use_direct_adc = true;
+			vout->display_ch = MEM_PP_ADC;
+			vout->post_proc_ch = MEM_PP_ADC;
+
+			memset(&params, 0, sizeof(params));
+			params.mem_pp_adc.in_width = vout->v2f.fmt.pix.width;
+			params.mem_pp_adc.in_height = vout->v2f.fmt.pix.height;
+			params.mem_pp_adc.in_pixel_fmt =
+			    vout->v2f.fmt.pix.pixelformat;
+			params.mem_pp_adc.out_width = out_width;
+			params.mem_pp_adc.out_height = out_height;
+			params.mem_pp_adc.out_pixel_fmt = SDC_FG_FB_FORMAT;
+#ifdef CONFIG_FB_MXC_EPSON_PANEL
+			params.mem_pp_adc.out_left =
+			    2 + vout->crop_current.left;
+#else
+			params.mem_pp_adc.out_left =
+			    12 + vout->crop_current.left;
+#endif
+			params.mem_pp_adc.out_top = vout->crop_current.top;
+			if (ipu_init_channel(
+				vout->post_proc_ch, &params) != 0) {
+				dev_err(dev, "Error initializing PP chan\n");
+				return -EINVAL;
+			}
+
+			if (ipu_init_channel_buffer(vout->post_proc_ch,
+						    IPU_INPUT_BUFFER,
+						    params.mem_pp_adc.
+						    in_pixel_fmt,
+						    params.mem_pp_adc.in_width,
+						    params.mem_pp_adc.in_height,
+						    vout->v2f.fmt.pix.
+						    bytesperline /
+						    bytes_per_pixel(params.
+							mem_pp_adc.
+							in_pixel_fmt),
+						    vout->rotate,
+						    vout->
+						    v4l2_bufs[pp_in_buf[0]].m.
+						    offset,
+						    vout->
+						    v4l2_bufs[pp_in_buf[1]].m.
+						    offset,
+						    vout->offset.u_offset,
+						    vout->offset.v_offset) !=
+			    0) {
+				dev_err(dev, "Error initializing PP in buf\n");
+				return -EINVAL;
+			}
+
+			if (ipu_init_channel_buffer(vout->post_proc_ch,
+						    IPU_OUTPUT_BUFFER,
+						    params.mem_pp_adc.
+						    out_pixel_fmt, out_width,
+						    out_height, out_width,
+						    vout->rotate, 0, 0, 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing PP"
+					"output buffer\n");
+				return -EINVAL;
+			}
+
+		} else {
+			dev_dbg(dev, "Using ADC SYS2 channel\n");
+			vout->display_ch = ADC_SYS2;
+			vout->post_proc_ch = MEM_PP_MEM;
+
+			if (vout->display_bufs[0]) {
+				mxc_free_buffers(vout->display_bufs,
+						 vout->display_bufs_vaddr,
+						 2, vout->display_buf_size);
+			}
+
+			vout->display_buf_size = vout->crop_current.width *
+			    vout->crop_current.height *
+			    fmt_to_bpp(SDC_FG_FB_FORMAT) / 8;
+			mxc_allocate_buffers(vout->display_bufs,
+					     vout->display_bufs_vaddr,
+					     2, vout->display_buf_size);
+
+			memset(&params, 0, sizeof(params));
+			params.adc_sys2.disp = vout->cur_disp_output;
+			params.adc_sys2.ch_mode = WriteTemplateNonSeq;
+#ifdef CONFIG_FB_MXC_EPSON_PANEL
+			params.adc_sys2.out_left = 2 + vout->crop_current.left;
+#else
+			params.adc_sys2.out_left = 12 + vout->crop_current.left;
+#endif
+			params.adc_sys2.out_top = vout->crop_current.top;
+			if (ipu_init_channel(ADC_SYS2, &params) < 0)
+				return -EINVAL;
+
+			if (ipu_init_channel_buffer(vout->display_ch,
+						    IPU_INPUT_BUFFER,
+						    SDC_FG_FB_FORMAT,
+						    out_width, out_height,
+						    out_width, IPU_ROTATE_NONE,
+						    vout->display_bufs[0],
+						    vout->display_bufs[1], 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing SDC FG buffer\n");
+				return -EINVAL;
+			}
+		}
+	} else
+#endif
+	{			/* Use SDC */
+		dev_dbg(dev, "Using SDC channel\n");
+
+		fbvar = fbi->var;
+		if (vout->cur_disp_output == 3) {
+			vout->display_ch = MEM_FG_SYNC;
+			fbvar.bits_per_pixel = 16;
+			fbvar.nonstd = IPU_PIX_FMT_UYVY;
+
+			fbvar.xres = fbvar.xres_virtual = out_width;
+			fbvar.yres = out_height;
+			fbvar.yres_virtual = out_height * 2;
+		} else if (vout->cur_disp_output == 5) {
+			vout->display_ch = MEM_DC_SYNC;
+			fbvar.bits_per_pixel = 16;
+			fbvar.nonstd = IPU_PIX_FMT_UYVY;
+
+			fbvar.xres = fbvar.xres_virtual = out_width;
+			fbvar.yres = out_height;
+			fbvar.yres_virtual = out_height * 2;
+		} else {
+			vout->display_ch = MEM_BG_SYNC;
+		}
+
+		fbvar.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbvar);
+
+		fb_pos.x = vout->crop_current.left;
+		fb_pos.y = vout->crop_current.top;
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
+					     (unsigned long)&fb_pos);
+			set_fs(old_fs);
+		}
+
+		vout->display_bufs[1] = fbi->fix.smem_start;
+		vout->display_bufs[0] = fbi->fix.smem_start +
+		    (fbi->fix.line_length * fbi->var.yres);
+		vout->display_buf_size = vout->crop_current.width *
+		    vout->crop_current.height * fbi->var.bits_per_pixel / 8;
+
+		vout->post_proc_ch = MEM_PP_MEM;
+	}
+
+	/* Init PP */
+	if (use_direct_adc == false) {
+		if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
+			out_width = vout->crop_current.height;
+			out_height = vout->crop_current.width;
+		}
+		memset(&params, 0, sizeof(params));
+		params.mem_pp_mem.in_width = vout->v2f.fmt.pix.width / 2;
+		params.mem_pp_mem.in_height = vout->v2f.fmt.pix.height;
+		params.mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat;
+		params.mem_pp_mem.out_width = out_width / 2;
+		params.mem_pp_mem.out_height = out_height;
+		if (vout->display_ch == ADC_SYS2)
+			params.mem_pp_mem.out_pixel_fmt = SDC_FG_FB_FORMAT;
+		else
+			params.mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi);
+		if (ipu_init_channel(vout->post_proc_ch, &params) != 0) {
+			dev_err(dev, "Error initializing PP channel\n");
+			return -EINVAL;
+		}
+
+		if (ipu_init_channel_buffer(vout->post_proc_ch,
+					    IPU_INPUT_BUFFER,
+					    params.mem_pp_mem.in_pixel_fmt,
+					    params.mem_pp_mem.in_width,
+					    params.mem_pp_mem.in_height,
+					    vout->v2f.fmt.pix.bytesperline /
+					    bytes_per_pixel(params.mem_pp_mem.
+							    in_pixel_fmt),
+					    IPU_ROTATE_NONE,
+					    vout->v4l2_bufs[pp_in_buf[0]].m.
+					    offset,
+					    vout->v4l2_bufs[pp_in_buf[0]].m.
+					    offset + params.mem_pp_mem.in_width,
+					    vout->offset.u_offset,
+					    vout->offset.v_offset) != 0) {
+			dev_err(dev, "Error initializing PP input buffer\n");
+			return -EINVAL;
+		}
+
+		if (!ipu_can_rotate_in_place(vout->rotate)) {
+			if (vout->rot_pp_bufs[0]) {
+				mxc_free_buffers(vout->rot_pp_bufs,
+						 vout->rot_pp_bufs_vaddr, 2,
+						 vout->display_buf_size);
+			}
+			if (mxc_allocate_buffers
+			    (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2,
+			     vout->display_buf_size) < 0)
+				return -ENOBUFS;
+
+			if (ipu_init_channel_buffer(vout->post_proc_ch,
+						    IPU_OUTPUT_BUFFER,
+						    params.mem_pp_mem.
+						    out_pixel_fmt, out_width,
+						    out_height, out_width,
+						    IPU_ROTATE_NONE,
+						    vout->rot_pp_bufs[0],
+						    vout->rot_pp_bufs[1], 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing"
+					"PP output buffer\n");
+				return -EINVAL;
+			}
+
+			if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) {
+				dev_err(dev,
+					"Error initializing PP ROT channel\n");
+				return -EINVAL;
+			}
+
+			if (ipu_init_channel_buffer(MEM_ROT_PP_MEM,
+						    IPU_INPUT_BUFFER,
+						    params.mem_pp_mem.
+						    out_pixel_fmt, out_width,
+						    out_height, out_width,
+						    vout->rotate,
+						    vout->rot_pp_bufs[0],
+						    vout->rot_pp_bufs[1], 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing PP ROT"
+					"input buffer\n");
+				return -EINVAL;
+			}
+
+			/* swap width and height */
+			if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
+				out_width = vout->crop_current.width;
+				out_height = vout->crop_current.height;
+			}
+
+			if (ipu_init_channel_buffer(MEM_ROT_PP_MEM,
+						    IPU_OUTPUT_BUFFER,
+						    params.mem_pp_mem.
+						    out_pixel_fmt, out_width,
+						    out_height, out_width,
+						    IPU_ROTATE_NONE,
+						    vout->display_bufs[0],
+						    vout->display_bufs[1], 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing PP"
+					"output buffer\n");
+				return -EINVAL;
+			}
+
+			if (ipu_link_channels(vout->post_proc_ch,
+					      MEM_ROT_PP_MEM) < 0)
+				return -EINVAL;
+
+			ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0);
+			ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1);
+
+			ipu_enable_channel(MEM_ROT_PP_MEM);
+
+			display_input_ch = MEM_ROT_PP_MEM;
+		} else {
+			if (ipu_init_channel_buffer(vout->post_proc_ch,
+						    IPU_OUTPUT_BUFFER,
+						    params.mem_pp_mem.
+						    out_pixel_fmt,
+						    out_width / 2,
+						    out_height,
+						    out_width,
+						    vout->rotate,
+						    vout->display_bufs[0],
+						    vout->display_bufs[0]
+						    +
+						    out_width / 2 *
+						    bytes_per_pixel
+						    (SDC_FG_FB_FORMAT), 0,
+						    0) != 0) {
+				dev_err(dev,
+					"Error initializing PP"
+					"output buffer\n");
+				return -EINVAL;
+			}
+		}
+		if (ipu_unlink_channels(
+			display_input_ch, vout->display_ch) < 0) {
+			dev_err(dev, "Error linking ipu channels\n");
+			return -EINVAL;
+		}
+	}
+
+	vout->state = STATE_STREAM_PAUSED;
+
+	ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
+
+	if (use_direct_adc == false) {
+		ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0);
+		ipu_enable_channel(vout->post_proc_ch);
+
+		if (fbi) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_UNBLANK);
+			release_console_sem();
+		} else {
+			ipu_enable_channel(vout->display_ch);
+		}
+	} else {
+		ipu_enable_channel(vout->post_proc_ch);
+	}
+
+	vout->start_jiffies = jiffies;
+	dev_dbg(dev,
+		"streamon: start time = %lu jiffies\n", vout->start_jiffies);
+
+	return 0;
+}
+
+/*!
+ * Shut down the voutera
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamoff(vout_data *vout)
+{
+	struct fb_info *fbi =
+	    registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	int i, retval = 0;
+	unsigned long lockflag = 0;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state == STATE_STREAM_OFF)
+		return 0;
+
+	spin_lock_irqsave(&g_lock, lockflag);
+
+	del_timer(&vout->output_timer);
+
+	if (vout->state == STATE_STREAM_ON)
+		vout->state = STATE_STREAM_STOPPING;
+
+	ipu_disable_irq(IPU_IRQ_PP_IN_EOF);
+	ipu_disable_irq(IPU_IRQ_PP_OUT_EOF);
+
+	spin_unlock_irqrestore(&g_lock, lockflag);
+
+	if (vout->post_proc_ch == MEM_PP_MEM) {	/* SDC or ADC with Rotation */
+		if (!ipu_can_rotate_in_place(vout->rotate)) {
+			ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM);
+			ipu_unlink_channels(MEM_ROT_PP_MEM, vout->display_ch);
+			ipu_disable_channel(MEM_ROT_PP_MEM, true);
+
+			if (vout->rot_pp_bufs[0]) {
+				mxc_free_buffers(vout->rot_pp_bufs,
+						 vout->rot_pp_bufs_vaddr, 2,
+						 vout->display_buf_size);
+			}
+		} else {
+			ipu_unlink_channels(MEM_PP_MEM, vout->display_ch);
+		}
+		ipu_disable_channel(MEM_PP_MEM, true);
+
+		if (vout->display_ch == ADC_SYS2) {
+			ipu_disable_channel(vout->display_ch, true);
+			ipu_uninit_channel(vout->display_ch);
+		} else {
+			fbi->var.activate |= FB_ACTIVATE_FORCE;
+			fb_set_var(fbi, &fbi->var);
+
+			if (vout->display_ch == MEM_FG_SYNC) {
+				acquire_console_sem();
+				fb_blank(fbi, FB_BLANK_POWERDOWN);
+				release_console_sem();
+			}
+
+			vout->display_bufs[0] = 0;
+			vout->display_bufs[1] = 0;
+		}
+
+		ipu_uninit_channel(MEM_PP_MEM);
+		if (!ipu_can_rotate_in_place(vout->rotate))
+			ipu_uninit_channel(MEM_ROT_PP_MEM);
+	} else {		/* ADC Direct */
+		ipu_disable_channel(MEM_PP_ADC, true);
+		ipu_uninit_channel(MEM_PP_ADC);
+	}
+	vout->ready_q.head = vout->ready_q.tail = 0;
+	vout->done_q.head = vout->done_q.tail = 0;
+	for (i = 0; i < vout->buffer_cnt; i++) {
+		vout->v4l2_bufs[i].flags = 0;
+		vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+		vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+	}
+
+	vout->state = STATE_STREAM_OFF;
+
+#ifdef CONFIG_FB_MXC_ASYNC_PANEL
+	if (vout->cur_disp_output < DISP3) {
+		if (vout->display_bufs[0] != 0) {
+			mxc_free_buffers(vout->display_bufs,
+					 vout->display_bufs_vaddr, 2,
+					 vout->display_buf_size);
+		}
+
+		mxcfb_set_refresh_mode(registered_fb
+				       [vout->
+					output_fb_num[vout->cur_disp_output]],
+				       MXCFB_REFRESH_PARTIAL, 0);
+	}
+#endif
+
+	return retval;
+}
+
+/*
+ * Valid whether the palette is supported
+ *
+ * @param palette  V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return 1 if supported, 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	return ((palette == V4L2_PIX_FMT_RGB565) ||
+		(palette == V4L2_PIX_FMT_BGR24) ||
+		(palette == V4L2_PIX_FMT_RGB24) ||
+		(palette == V4L2_PIX_FMT_BGR32) ||
+		(palette == V4L2_PIX_FMT_RGB32) ||
+		(palette == V4L2_PIX_FMT_NV12) ||
+		(palette == V4L2_PIX_FMT_YUV422P) ||
+		(palette == V4L2_PIX_FMT_YUV420));
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_g_fmt(vout_data *vout, struct v4l2_format *f)
+{
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+	*f = vout->v2f;
+	return 0;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_s_fmt(vout_data *vout, struct v4l2_format *f)
+{
+	int retval = 0;
+	u32 size = 0;
+	u32 bytesperline;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		retval = -EINVAL;
+		goto err0;
+	}
+	if (!valid_mode(f->fmt.pix.pixelformat)) {
+		dev_err(vout->video_dev->dev, "pixel format not supported\n");
+		retval = -EINVAL;
+		goto err0;
+	}
+
+	bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) /
+	    8;
+	if (f->fmt.pix.bytesperline < bytesperline) {
+		f->fmt.pix.bytesperline = bytesperline;
+	} else {
+		bytesperline = f->fmt.pix.bytesperline;
+	}
+
+	switch (f->fmt.pix.pixelformat) {
+	case V4L2_PIX_FMT_YUV422P:
+		/* byteperline for YUV planar formats is for
+		   Y plane only */
+		size = bytesperline * f->fmt.pix.height * 2;
+		break;
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_NV12:
+		size = (bytesperline * f->fmt.pix.height * 3) / 2;
+		break;
+	default:
+		size = bytesperline * f->fmt.pix.height;
+		break;
+	}
+
+	/* Return the actual size of the image to the app */
+	if (f->fmt.pix.sizeimage < size)
+		f->fmt.pix.sizeimage = size;
+	else
+		size = f->fmt.pix.sizeimage;
+
+	vout->v2f.fmt.pix = f->fmt.pix;
+	if (vout->v2f.fmt.pix.priv != 0) {
+		if (copy_from_user(&vout->offset,
+				   (void *)vout->v2f.fmt.pix.priv,
+				   sizeof(vout->offset))) {
+			retval = -EFAULT;
+			goto err0;
+		}
+	} else {
+		vout->offset.u_offset = 0;
+		vout->offset.v_offset = 0;
+	}
+
+	retval = 0;
+err0:
+	return retval;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_get_v42lout_control(vout_data *vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0;
+	case V4L2_CID_VFLIP:
+		return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0;
+	case (V4L2_CID_PRIVATE_BASE + 1):
+		return vout->rotate;
+	default:
+		return -EINVAL;
+	}
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_set_v42lout_control(vout_data *vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP :
+		    IPU_ROTATE_NONE;
+		break;
+	case V4L2_CID_VFLIP:
+		vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP :
+		    IPU_ROTATE_NONE;
+		break;
+	case V4L2_CID_MXC_ROT:
+		vout->rotate = c->value;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * V4L2 interface - open function
+ *
+ * @param inode        structure inode *
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l2out_open(struct inode *inode, struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+	int err;
+
+	if (!vout)
+		return -ENODEV;
+
+	down(&vout->busy_lock);
+
+	err = -EINTR;
+	if (signal_pending(current))
+		goto oops;
+
+	if (vout->open_count++ == 0) {
+		ipu_request_irq(IPU_IRQ_PP_IN_EOF,
+				mxc_v4l2out_pp_in_irq_handler,
+				0, dev->name, vout);
+		ipu_request_irq(IPU_IRQ_PP_OUT_EOF,
+				mxc_v4l2out_pp_out_irq_handler,
+				0, dev->name, vout);
+
+		init_waitqueue_head(&vout->v4l_bufq);
+
+		init_timer(&vout->output_timer);
+		vout->output_timer.function = mxc_v4l2out_timer_handler;
+		vout->output_timer.data = (unsigned long)vout;
+
+		vout->state = STATE_STREAM_OFF;
+		vout->rotate = IPU_ROTATE_NONE;
+		g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0;
+
+	}
+
+	file->private_data = dev;
+
+	up(&vout->busy_lock);
+
+	return 0;
+
+oops:
+	up(&vout->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L2 interface - close function
+ *
+ * @param inode    struct inode *
+ *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int mxc_v4l2out_close(struct inode *inode, struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+
+	if (--vout->open_count == 0) {
+		if (vout->state != STATE_STREAM_OFF)
+			mxc_v4l2out_streamoff(vout);
+
+		ipu_free_irq(IPU_IRQ_PP_IN_EOF, vout);
+		ipu_free_irq(IPU_IRQ_PP_OUT_EOF, vout);
+
+		file->private_data = NULL;
+
+		mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr,
+				 vout->buffer_cnt, vout->queue_buf_size);
+		vout->buffer_cnt = 0;
+		mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2,
+				 vout->display_buf_size);
+
+		/* capture off */
+		wake_up_interruptible(&vout->v4l_bufq);
+	}
+
+	return 0;
+}
+
+/*!
+ * V4L2 interface - ioctl function
+ *
+ * @param inode      struct inode *
+ *
+ * @param file       struct file *
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void *
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static int
+mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file,
+		     unsigned int ioctlnr, void *arg)
+{
+	struct video_device *vdev = file->private_data;
+	vout_data *vout = video_get_drvdata(vdev);
+	int retval = 0;
+	int i = 0;
+
+	if (!vout)
+		return -EBADF;
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+	case VIDIOC_QUERYCAP:
+		{
+			struct v4l2_capability *cap = arg;
+			strcpy(cap->driver, "mxc_v4l2_output");
+			cap->version = 0;
+			cap->capabilities =
+			    V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
+			cap->card[0] = '\0';
+			cap->bus_info[0] = '\0';
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_FMT:
+		{
+			struct v4l2_format *gf = arg;
+			retval = mxc_v4l2out_g_fmt(vout, gf);
+			break;
+		}
+	case VIDIOC_S_FMT:
+		{
+			struct v4l2_format *sf = arg;
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+			retval = mxc_v4l2out_s_fmt(vout, sf);
+			break;
+		}
+	case VIDIOC_REQBUFS:
+		{
+			struct v4l2_requestbuffers *req = arg;
+			if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (req->memory != V4L2_MEMORY_MMAP)) {
+				dev_dbg(vdev->dev,
+					"VIDIOC_REQBUFS: incorrect"
+					"buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			if (req->count == 0)
+				mxc_v4l2out_streamoff(vout);
+
+			if (vout->state == STATE_STREAM_OFF) {
+				if (vout->queue_buf_paddr[0] != 0) {
+					mxc_free_buffers(vout->queue_buf_paddr,
+							 vout->queue_buf_vaddr,
+							 vout->buffer_cnt,
+							 vout->queue_buf_size);
+					dev_dbg(vdev->dev,
+						"VIDIOC_REQBUFS:"
+						"freed buffers\n");
+				}
+				vout->buffer_cnt = 0;
+			} else {
+				dev_dbg(vdev->dev,
+					"VIDIOC_REQBUFS: Buffer is in use\n");
+				retval = -EBUSY;
+				break;
+			}
+
+			if (req->count == 0)
+				break;
+
+			if (req->count < MIN_FRAME_NUM)
+				req->count = MIN_FRAME_NUM;
+			else if (req->count > MAX_FRAME_NUM)
+				req->count = MAX_FRAME_NUM;
+			vout->buffer_cnt = req->count;
+			vout->queue_buf_size =
+			    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+
+			retval = mxc_allocate_buffers(vout->queue_buf_paddr,
+						      vout->queue_buf_vaddr,
+						      vout->buffer_cnt,
+						      vout->queue_buf_size);
+			if (retval < 0)
+				break;
+
+			/* Init buffer queues */
+			vout->done_q.head = 0;
+			vout->done_q.tail = 0;
+			vout->ready_q.head = 0;
+			vout->ready_q.tail = 0;
+
+			for (i = 0; i < vout->buffer_cnt; i++) {
+				memset(&(vout->v4l2_bufs[i]), 0,
+				       sizeof(vout->v4l2_bufs[i]));
+				vout->v4l2_bufs[i].flags = 0;
+				vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP;
+				vout->v4l2_bufs[i].index = i;
+				vout->v4l2_bufs[i].type =
+				    V4L2_BUF_TYPE_VIDEO_OUTPUT;
+				vout->v4l2_bufs[i].length =
+				    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+				vout->v4l2_bufs[i].m.offset =
+				    (unsigned long)vout->queue_buf_paddr[i];
+				vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+				vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+			}
+			break;
+		}
+	case VIDIOC_QUERYBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			u32 type = buf->type;
+			int index = buf->index;
+
+			if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt)) {
+				dev_dbg(vdev->dev,
+					"VIDIOC_QUERYBUFS: incorrect"
+					"buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+			down(&vout->param_lock);
+			memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf));
+			up(&vout->param_lock);
+			break;
+		}
+	case VIDIOC_QBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int index = buf->index;
+			unsigned long lock_flags;
+
+			if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			dev_dbg(vdev->dev, "VIDIOC_QBUF: %d\n", buf->index);
+
+			/* mmapped buffers are L1 WB cached,
+			 * so we need to clean them */
+			if (buf->flags & V4L2_BUF_FLAG_MAPPED)
+				flush_cache_all();
+
+			spin_lock_irqsave(&g_lock, lock_flags);
+
+			memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf));
+			vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED;
+
+			g_buf_q_cnt++;
+			queue_buf(&vout->ready_q, index);
+			if (vout->state == STATE_STREAM_PAUSED) {
+				unsigned long timeout;
+
+				index = peek_next_buf(&vout->ready_q);
+
+				/* if timestamp is 0, then default to 30fps */
+				if ((vout->v4l2_bufs[index].timestamp.tv_sec ==
+				     0)
+				    && (vout->v4l2_bufs[index].timestamp.
+					tv_usec == 0))
+					timeout =
+					    vout->start_jiffies +
+					    vout->frame_count * HZ / 30;
+				else
+					timeout =
+					    get_jiffies(&vout->v4l2_bufs[index].
+							timestamp);
+
+				if (jiffies >= timeout) {
+					dev_dbg(vout->video_dev->dev,
+						"warning: timer timeout"
+						"already expired.\n");
+				}
+				vout->output_timer.expires = timeout;
+				dev_dbg(vdev->dev,
+					"QBUF: frame #%u timeout @"
+					" %lu jiffies, current = %lu\n",
+					vout->frame_count, timeout, jiffies);
+				add_timer(&vout->output_timer);
+				vout->state = STATE_STREAM_ON;
+			}
+
+			spin_unlock_irqrestore(&g_lock, lock_flags);
+			break;
+		}
+	case VIDIOC_DQBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int idx;
+
+			if ((queue_size(&vout->done_q) == 0) &&
+			    (file->f_flags & O_NONBLOCK)) {
+				retval = -EAGAIN;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout(vout->v4l_bufq,
+							      queue_size(&vout->
+									 done_q)
+							      != 0, 10 * HZ)) {
+				dev_dbg(vdev->dev, "VIDIOC_DQBUF: timeout\n");
+				retval = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				dev_dbg(vdev->dev,
+					"VIDIOC_DQBUF: interrupt received\n");
+				retval = -ERESTARTSYS;
+				break;
+			}
+			idx = dequeue_buf(&vout->done_q);
+			if (idx == -1) {	/* No frame free */
+				dev_dbg(vdev->dev,
+					"VIDIOC_DQBUF: no free buffers\n");
+				retval = -EAGAIN;
+				break;
+			}
+			if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) ==
+			    0)
+				dev_dbg(vdev->dev,
+					"VIDIOC_DQBUF: buffer in done q, "
+					"but not flagged as done\n");
+
+			vout->v4l2_bufs[idx].flags = 0;
+			memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf));
+			dev_dbg(vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index);
+			break;
+		}
+	case VIDIOC_STREAMON:
+		{
+			retval = mxc_v4l2out_streamon(vout);
+			break;
+		}
+	case VIDIOC_STREAMOFF:
+		{
+			retval = mxc_v4l2out_streamoff(vout);
+			break;
+		}
+	case VIDIOC_G_CTRL:
+		{
+			retval = mxc_get_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_S_CTRL:
+		{
+			retval = mxc_set_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_CROPCAP:
+		{
+			struct v4l2_cropcap *cap = arg;
+
+			if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+
+			cap->bounds = vout->crop_bounds[vout->cur_disp_output];
+			cap->defrect = vout->crop_bounds[vout->cur_disp_output];
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			crop->c = vout->crop_current;
+			break;
+		}
+	case VIDIOC_S_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+			struct v4l2_rect *b =
+			    &(vout->crop_bounds[vout->cur_disp_output]);
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.height < 0) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.width < 0) {
+				retval = -EINVAL;
+				break;
+			}
+
+			/* only full screen supported for SDC BG */
+			if (vout->cur_disp_output == 4) {
+				crop->c = vout->crop_current;
+				break;
+			}
+
+			if (crop->c.top < b->top)
+				crop->c.top = b->top;
+			if (crop->c.top >= b->top + b->height)
+				crop->c.top = b->top + b->height - 1;
+			if (crop->c.height > b->top - crop->c.top + b->height)
+				crop->c.height =
+				    b->top - crop->c.top + b->height;
+
+			if (crop->c.left < b->left)
+				crop->c.left = b->left;
+			if (crop->c.left >= b->left + b->width)
+				crop->c.left = b->left + b->width - 1;
+			if (crop->c.width > b->left - crop->c.left + b->width)
+				crop->c.width =
+				    b->left - crop->c.left + b->width;
+
+			/* stride line limitation */
+			crop->c.height -= crop->c.height % 8;
+			crop->c.width -= crop->c.width % 8;
+
+			vout->crop_current = crop->c;
+			break;
+		}
+	case VIDIOC_ENUMOUTPUT:
+		{
+			struct v4l2_output *output = arg;
+
+			if ((output->index >= 5) ||
+			    (vout->output_enabled[output->index] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (output->index < 3) {
+				*output = mxc_outputs[MXC_V4L2_OUT_2_ADC];
+				output->name[4] = '0' + output->index;
+			} else {
+				*output = mxc_outputs[MXC_V4L2_OUT_2_SDC];
+			}
+			break;
+		}
+	case VIDIOC_G_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			*p_output_num = vout->cur_disp_output;
+			break;
+		}
+	case VIDIOC_S_OUTPUT:
+		{
+			int *p_output_num = arg;
+			int fbnum;
+			struct v4l2_rect *b;
+
+			if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) ||
+			    (vout->output_enabled[*p_output_num] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+
+			vout->cur_disp_output = *p_output_num;
+
+			/* Update bounds in case they have changed */
+			b = &vout->crop_bounds[vout->cur_disp_output];
+
+			fbnum = vout->output_fb_num[vout->cur_disp_output];
+			if (vout->cur_disp_output == 3)
+				fbnum = vout->output_fb_num[4];
+
+			b->width = registered_fb[fbnum]->var.xres;
+			b->height = registered_fb[fbnum]->var.yres;
+
+			vout->crop_current = *b;
+			break;
+		}
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_G_PARM:
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_STD:
+	case VIDIOC_S_STD:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&vout->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L2 interface - ioctl function
+ *
+ * @return  None
+ */
+static int
+mxc_v4l2out_ioctl(struct inode *inode, struct file *file,
+		  unsigned int cmd, unsigned long arg)
+{
+	return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl);
+}
+
+/*!
+ * V4L2 interface - mmap function
+ *
+ * @param file          structure file *
+ *
+ * @param vma           structure vm_area_struct *
+ *
+ * @return status       0 Success, EINTR busy lock error,
+ *                      ENOBUFS remap_page error
+ */
+static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *vdev = video_devdata(file);
+	unsigned long size = vma->vm_end - vma->vm_start;
+	int res = 0;
+	int i;
+	vout_data *vout = video_get_drvdata(vdev);
+
+	dev_dbg(vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	for (i = 0; i < vout->buffer_cnt; i++) {
+		if ((vout->v4l2_bufs[i].m.offset ==
+		     (vma->vm_pgoff << PAGE_SHIFT)) &&
+		    (vout->v4l2_bufs[i].length >= size)) {
+			vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED;
+			break;
+		}
+	}
+	if (i == vout->buffer_cnt) {
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	/* make buffers inner write-back, outer write-thru cacheable */
+	vma->vm_page_prot = pgprot_outer_wrthru(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		dev_dbg(vdev->dev, "mmap remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+mxc_mmap_exit:
+	up(&vout->busy_lock);
+	return res;
+}
+
+/*!
+ * V4L2 interface - poll function
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	queue = &vout->v4l_bufq;
+	poll_wait(file, queue, wait);
+
+	up(&vout->busy_lock);
+	return res;
+}
+
+static struct
+file_operations mxc_v4l2out_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_v4l2out_open,
+	.release = mxc_v4l2out_close,
+	.ioctl = mxc_v4l2out_ioctl,
+	.mmap = mxc_v4l2out_mmap,
+	.poll = mxc_v4l2out_poll,
+};
+
+static struct video_device mxc_v4l2out_template = {
+	.owner = THIS_MODULE,
+	.name = "MXC Video Output",
+	.type = 0,
+	.type2 = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING,
+	.fops = &mxc_v4l2out_fops,
+	.release = video_device_release,
+};
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxc_v4l2out_probe(struct platform_device *pdev)
+{
+	int i;
+	vout_data *vout;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL);
+
+	if (!vout)
+		return 0;
+
+	memset(vout, 0, sizeof(vout_data));
+
+	vout->video_dev = video_device_alloc();
+	if (vout->video_dev == NULL)
+		return -1;
+	vout->video_dev->dev = &pdev->dev;
+	vout->video_dev->minor = -1;
+
+	*(vout->video_dev) = mxc_v4l2out_template;
+
+	/* register v4l device */
+	if (video_register_device(vout->video_dev,
+				  VFL_TYPE_GRABBER, video_nr) == -1) {
+		dev_dbg(&pdev->dev, "video_register_device failed\n");
+		return 0;
+	}
+	dev_info(&pdev->dev, "Registered device video%d\n",
+		 vout->video_dev->minor & 0x1f);
+	vout->video_dev->dev = &pdev->dev;
+
+	video_set_drvdata(vout->video_dev, vout);
+
+	init_MUTEX(&vout->param_lock);
+	init_MUTEX(&vout->busy_lock);
+
+	/* setup outputs and cropping */
+	vout->cur_disp_output = -1;
+	for (i = 0; i < num_registered_fb; i++) {
+		char *idstr = registered_fb[i]->fix.id;
+		if (strncmp(idstr, "DISP", 4) == 0) {
+			int disp_num = idstr[4] - '0';
+			if (disp_num == 3) {
+				if (strcmp(idstr, "DISP3 BG - DI1") == 0)
+					disp_num = 5;
+				else if (strncmp(idstr, "DISP3 BG", 8) == 0)
+					disp_num = 4;
+			}
+			vout->crop_bounds[disp_num].left = 0;
+			vout->crop_bounds[disp_num].top = 0;
+			vout->crop_bounds[disp_num].width =
+			    registered_fb[i]->var.xres;
+			vout->crop_bounds[disp_num].height =
+			    registered_fb[i]->var.yres;
+			vout->output_enabled[disp_num] = true;
+			vout->output_fb_num[disp_num] = i;
+			if (vout->cur_disp_output == -1)
+				vout->cur_disp_output = disp_num;
+		}
+
+	}
+	vout->crop_current = vout->crop_bounds[vout->cur_disp_output];
+
+	platform_set_drvdata(pdev, vout);
+
+	return 0;
+}
+
+static int mxc_v4l2out_remove(struct platform_device *pdev)
+{
+	vout_data *vout = platform_get_drvdata(pdev);
+
+	if (vout->video_dev) {
+		if (-1 != vout->video_dev->minor)
+			video_unregister_device(vout->video_dev);
+		else
+			video_device_release(vout->video_dev);
+		vout->video_dev = NULL;
+	}
+
+	platform_set_drvdata(pdev, NULL);
+
+	kfree(vout);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_v4l2out_driver = {
+	.driver = {
+		   .name = "MXC Video Output",
+		   },
+	.probe = mxc_v4l2out_probe,
+	.remove = mxc_v4l2out_remove,
+};
+
+static struct platform_device mxc_v4l2out_device = {
+	.name = "MXC Video Output",
+	.id = 0,
+};
+
+/*!
+ * mxc v4l2 init function
+ *
+ */
+static int mxc_v4l2out_init(void)
+{
+	u8 err = 0;
+
+	err = platform_driver_register(&mxc_v4l2out_driver);
+	if (err == 0)
+		platform_device_register(&mxc_v4l2out_device);
+	return err;
+}
+
+/*!
+ * mxc v4l2 cleanup function
+ *
+ */
+static void mxc_v4l2out_clean(void)
+{
+	video_unregister_device(g_vout->video_dev);
+
+	platform_driver_unregister(&mxc_v4l2out_driver);
+	platform_device_unregister(&mxc_v4l2out_device);
+	kfree(g_vout);
+	g_vout = NULL;
+}
+
+module_init(mxc_v4l2out_init);
+module_exit(mxc_v4l2out_clean);
+
+module_param(video_nr, int, 0444);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2-driver for MXC video output");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.c b/drivers/media/video/mxc/output/mxc_v4l2_output.c
new file mode 100644
index 000000000000..ce577c4c27d3
--- /dev/null
+++ b/drivers/media/video/mxc/output/mxc_v4l2_output.c
@@ -0,0 +1,2614 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/media/video/mxc/output/mxc_v4l2_output.c
+ *
+ * @brief MXC V4L2 Video Output Driver
+ *
+ * Video4Linux2 Output Device using MXC IPU Post-processing functionality.
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/semaphore.h>
+#include <linux/console.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mxcfb.h>
+#include <media/v4l2-ioctl.h>
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+
+#include "mxc_v4l2_output.h"
+
+#define INTERLACED_CONTENT(vout) (((cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) || \
+				   cpu_is_mx53()) &&			\
+				  (((vout)->field_fmt == V4L2_FIELD_INTERLACED_TB) || \
+				   ((vout)->field_fmt == V4L2_FIELD_INTERLACED_BT)))
+#define LOAD_3FIELDS(vout) ((INTERLACED_CONTENT(vout)) && \
+			    ((vout)->motion_sel != HIGH_MOTION))
+
+struct v4l2_output mxc_outputs[1] = {
+	{
+	 .index = MXC_V4L2_OUT_2_SDC,
+	 .name = "DISP3 Video Out",
+	 .type = V4L2_OUTPUT_TYPE_ANALOG,	/* not really correct,
+						   but no other choice */
+	 .audioset = 0,
+	 .modulator = 0,
+	 .std = V4L2_STD_UNKNOWN}
+};
+
+static int video_nr = 16;
+static spinlock_t g_lock = SPIN_LOCK_UNLOCKED;
+static int last_index_n;
+static unsigned int ipu_ic_out_max_width_size;
+static unsigned int ipu_ic_out_max_height_size;
+/* debug counters */
+uint32_t g_irq_cnt;
+uint32_t g_buf_output_cnt;
+uint32_t g_buf_q_cnt;
+uint32_t g_buf_dq_cnt;
+
+#define QUEUE_SIZE (MAX_FRAME_NUM + 1)
+static __inline int queue_size(v4l_queue * q)
+{
+	if (q->tail >= q->head)
+		return (q->tail - q->head);
+	else
+		return ((q->tail + QUEUE_SIZE) - q->head);
+}
+
+static __inline int queue_buf(v4l_queue * q, int idx)
+{
+	if (((q->tail + 1) % QUEUE_SIZE) == q->head)
+		return -1;	/* queue full */
+	q->list[q->tail] = idx;
+	q->tail = (q->tail + 1) % QUEUE_SIZE;
+	return 0;
+}
+
+static __inline int dequeue_buf(v4l_queue * q)
+{
+	int ret;
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	ret = q->list[q->head];
+	q->head = (q->head + 1) % QUEUE_SIZE;
+	return ret;
+}
+
+static __inline int peek_next_buf(v4l_queue * q)
+{
+	if (q->tail == q->head)
+		return -1;	/* queue empty */
+	return q->list[q->head];
+}
+
+static __inline unsigned long get_jiffies(struct timeval *t)
+{
+	struct timeval cur;
+
+	if (t->tv_usec >= 1000000) {
+		t->tv_sec += t->tv_usec / 1000000;
+		t->tv_usec = t->tv_usec % 1000000;
+	}
+
+	do_gettimeofday(&cur);
+	if ((t->tv_sec < cur.tv_sec)
+	    || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
+		return jiffies;
+
+	if (t->tv_usec < cur.tv_usec) {
+		cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
+		cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
+	} else {
+		cur.tv_sec = t->tv_sec - cur.tv_sec;
+		cur.tv_usec = t->tv_usec - cur.tv_usec;
+	}
+
+	return jiffies + timeval_to_jiffies(&cur);
+}
+
+/*!
+ * Private function to free buffers
+ *
+ * @param bufs_paddr	Array of physical address of buffers to be freed
+ *
+ * @param bufs_vaddr	Array of virtual address of buffers to be freed
+ *
+ * @param num_buf	Number of buffers to be freed
+ *
+ * @param size		Size for each buffer to be free
+ *
+ * @return status  0 success.
+ */
+static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+			    int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		if (bufs_vaddr[i] != 0) {
+			dma_free_coherent(0, size, bufs_vaddr[i],
+					  bufs_paddr[i]);
+			pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]);
+			bufs_paddr[i] = 0;
+			bufs_vaddr[i] = NULL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Private function to allocate buffers
+ *
+ * @param bufs_paddr	Output array of physical address of buffers allocated
+ *
+ * @param bufs_vaddr	Output array of virtual address of buffers allocated
+ *
+ * @param num_buf	Input number of buffers to allocate
+ *
+ * @param size		Input size for each buffer to allocate
+ *
+ * @return status	-0 Successfully allocated a buffer, -ENOBUFS failed.
+ */
+static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[],
+				int num_buf, int size)
+{
+	int i;
+
+	for (i = 0; i < num_buf; i++) {
+		bufs_vaddr[i] = dma_alloc_coherent(0, size,
+						   &bufs_paddr[i],
+						   GFP_DMA | GFP_KERNEL);
+
+		if (bufs_vaddr[i] == 0) {
+			mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size);
+			printk(KERN_ERR "dma_alloc_coherent failed.\n");
+			return -ENOBUFS;
+		}
+		pr_debug("allocated @ paddr=0x%08X, size=%d.\n",
+			 (u32) bufs_paddr[i], size);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns bits per pixel for given pixel format
+ *
+ * @param pixelformat  V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return bits per pixel of pixelformat
+ */
+static u32 fmt_to_bpp(u32 pixelformat)
+{
+	u32 bpp;
+
+	bpp = 8 * bytes_per_pixel(pixelformat);
+	return bpp;
+}
+
+static bool format_is_yuv(u32 pixelformat)
+{
+	switch (pixelformat) {
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_UYVY:
+	case V4L2_PIX_FMT_YUYV:
+	case V4L2_PIX_FMT_YUV422P:
+	case V4L2_PIX_FMT_YVU420:
+	case V4L2_PIX_FMT_NV12:
+		return true;
+		break;
+	}
+	return false;
+}
+
+static u32 bpp_to_fmt(struct fb_info *fbi)
+{
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	if (fbi->var.bits_per_pixel == 24)
+		return V4L2_PIX_FMT_BGR24;
+	else if (fbi->var.bits_per_pixel == 32)
+		return V4L2_PIX_FMT_BGR32;
+	else if (fbi->var.bits_per_pixel == 16)
+		return V4L2_PIX_FMT_RGB565;
+
+	return 0;
+}
+
+/*
+ * we are using double buffer for video playback, ipu need make
+ * sure current buffer should not be the same buffer of next display
+ * one.
+ */
+static int select_display_buffer(vout_data *vout, int next_buf)
+{
+	int ret = 0;
+
+	if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER)
+			!= next_buf)
+		ret = ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER,
+				next_buf);
+	else
+		dev_dbg(&vout->video_dev->dev,
+			"display buffer not ready for select\n");
+	return ret;
+}
+
+static void setup_next_buf_timer(vout_data *vout, int index)
+{
+	unsigned long timeout;
+
+	/* Setup timer for next buffer */
+	/* if timestamp is 0, then default to 30fps */
+	if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0)
+			&& (vout->v4l2_bufs[index].timestamp.tv_usec == 0)
+			&& vout->start_jiffies)
+		timeout =
+			vout->start_jiffies + vout->frame_count * HZ / 30;
+	else
+		timeout =
+			get_jiffies(&vout->v4l2_bufs[index].timestamp);
+
+	if (jiffies >= timeout) {
+		dev_dbg(&vout->video_dev->dev,
+				"warning: timer timeout already expired.\n");
+	}
+	if (mod_timer(&vout->output_timer, timeout))
+		dev_dbg(&vout->video_dev->dev,
+				"warning: timer was already set\n");
+
+	dev_dbg(&vout->video_dev->dev,
+			"timer handler next schedule: %lu\n", timeout);
+}
+
+static int finish_previous_frame(vout_data *vout)
+{
+	struct fb_info *fbi =
+		registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	mm_segment_t old_fs;
+	int ret = 0;
+
+	/* make sure buf[next_done_ipu_buf] showed */
+	while (ipu_check_buffer_busy(vout->display_ch,
+			IPU_INPUT_BUFFER, vout->next_done_ipu_buf)) {
+		/* wait for display frame finish */
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
+					(unsigned int)NULL);
+			set_fs(old_fs);
+
+			if (ret < 0) {
+				/* ic_bypass need clear display buffer ready for next update*/
+				ipu_clear_buffer_ready(vout->display_ch, IPU_INPUT_BUFFER,
+						vout->next_done_ipu_buf);
+			}
+		}
+	}
+
+	return ret;
+}
+
+static int show_current_frame(vout_data *vout)
+{
+	struct fb_info *fbi =
+		registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	mm_segment_t old_fs;
+	int ret = 0;
+
+	/* make sure buf[next_rdy_ipu_buf] begin to show */
+	if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER)
+		!= vout->next_rdy_ipu_buf) {
+		/* wait for display frame finish */
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
+					(unsigned int)NULL);
+			set_fs(old_fs);
+		}
+	}
+
+	return ret;
+}
+
+static void timer_work_func(struct work_struct *work)
+{
+	vout_data *vout =
+		container_of(work, vout_data, timer_work);
+	int index, ret;
+	int last_buf;
+	unsigned long lock_flags = 0;
+
+	finish_previous_frame(vout);
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	if (g_buf_output_cnt == 0) {
+		ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1);
+	} else {
+		index = dequeue_buf(&vout->ready_q);
+		if (index == -1) {	/* no buffers ready, should never occur */
+			dev_err(&vout->video_dev->dev,
+					"mxc_v4l2out: timer - no queued buffers ready\n");
+			goto exit;
+		}
+		g_buf_dq_cnt++;
+		vout->frame_count++;
+
+		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
+		ret = ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index].m.offset);
+		ret += select_display_buffer(vout, vout->next_rdy_ipu_buf);
+		if (ret < 0) {
+			dev_err(&vout->video_dev->dev,
+					"unable to update buffer %d address rc=%d\n",
+					vout->next_rdy_ipu_buf, ret);
+			goto exit;
+		}
+		spin_unlock_irqrestore(&g_lock, lock_flags);
+		show_current_frame(vout);
+		spin_lock_irqsave(&g_lock, lock_flags);
+		vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+	}
+
+	last_buf = vout->ipu_buf[vout->next_done_ipu_buf];
+	if (last_buf != -1) {
+		g_buf_output_cnt++;
+		vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
+		queue_buf(&vout->done_q, last_buf);
+		wake_up_interruptible(&vout->v4l_bufq);
+		vout->ipu_buf[vout->next_done_ipu_buf] = -1;
+		vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
+	}
+
+	if (g_buf_output_cnt > 0) {
+		/* Setup timer for next buffer */
+		index = peek_next_buf(&vout->ready_q);
+		if (index != -1)
+			setup_next_buf_timer(vout, index);
+		else
+			vout->state = STATE_STREAM_PAUSED;
+
+		if (vout->state == STATE_STREAM_STOPPING) {
+			if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
+				vout->state = STATE_STREAM_OFF;
+			}
+		}
+	}
+exit:
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+}
+
+static void mxc_v4l2out_timer_handler(unsigned long arg)
+{
+	int index, ret;
+	unsigned long lock_flags = 0;
+	vout_data *vout = (vout_data *) arg;
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	if ((vout->state == STATE_STREAM_STOPPING)
+	    || (vout->state == STATE_STREAM_OFF))
+		goto exit0;
+
+	/*
+	 * If timer occurs before IPU h/w is ready, then set the state to
+	 * paused and the timer will be set again when next buffer is queued
+	 * or PP comletes
+	 */
+	if (vout->ipu_buf[vout->next_rdy_ipu_buf] != -1) {
+		dev_dbg(&vout->video_dev->dev, "IPU buffer busy\n");
+		vout->state = STATE_STREAM_PAUSED;
+		goto exit0;
+	}
+
+	/* VDI need both buffer done before update buffer? */
+	if (INTERLACED_CONTENT(vout) &&
+		(vout->ipu_buf[!vout->next_rdy_ipu_buf] != -1)) {
+		dev_dbg(&vout->video_dev->dev, "IPU buffer busy\n");
+		vout->state = STATE_STREAM_PAUSED;
+		goto exit0;
+	}
+
+	/* Handle ic bypass mode in work queue */
+	if (vout->ic_bypass) {
+		if (queue_work(vout->v4l_wq, &vout->timer_work) == 0) {
+			dev_err(&vout->video_dev->dev, "work was in queue already!\n ");
+			vout->state = STATE_STREAM_PAUSED;
+		}
+		goto exit0;
+	}
+
+	/* Dequeue buffer and pass to IPU */
+	index = dequeue_buf(&vout->ready_q);
+	if (index == -1) {	/* no buffers ready, should never occur */
+		dev_err(&vout->video_dev->dev,
+			"mxc_v4l2out: timer - no queued buffers ready\n");
+		goto exit0;
+	}
+	g_buf_dq_cnt++;
+	vout->frame_count++;
+
+	/* update next buffer */
+	if (LOAD_3FIELDS(vout)) {
+		int index_n = index;
+		int index_p = last_index_n;
+		vout->ipu_buf_p[vout->next_rdy_ipu_buf] = last_index_n;
+		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
+		vout->ipu_buf_n[vout->next_rdy_ipu_buf] = index;
+		ret = ipu_update_channel_buffer(vout->post_proc_ch,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index].m.offset);
+		ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_P,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index_p].m.offset + vout->bytesperline);
+		ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_N,
+				IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf,
+				vout->v4l2_bufs[index_n].m.offset) + vout->bytesperline;
+		last_index_n = index;
+	} else {
+		vout->ipu_buf[vout->next_rdy_ipu_buf] = index;
+		if (vout->pp_split) {
+			vout->ipu_buf[!vout->next_rdy_ipu_buf] = index;
+			/* always left stripe */
+			ret = ipu_update_channel_buffer(vout->post_proc_ch,
+					IPU_INPUT_BUFFER,
+					0,/* vout->next_rdy_ipu_buf,*/
+					(vout->v4l2_bufs[index].m.offset) +
+					vout->pp_left_stripe.input_column +
+					vout->pp_up_stripe.input_column * vout->bytesperline);
+
+			/* the U/V offset has to be updated inside of IDMAC */
+			/* according to stripe offset */
+			ret += ipu_update_channel_offset(vout->post_proc_ch,
+					IPU_INPUT_BUFFER,
+					vout->v2f.fmt.pix.pixelformat,
+					vout->v2f.fmt.pix.width,
+					vout->v2f.fmt.pix.height,
+					vout->bytesperline,
+					vout->offset.u_offset,
+					vout->offset.v_offset,
+					vout->pp_up_stripe.input_column,
+					vout->pp_left_stripe.input_column);
+		} else
+			ret = ipu_update_channel_buffer(vout->post_proc_ch,
+					IPU_INPUT_BUFFER,
+					vout->next_rdy_ipu_buf,
+					vout->v4l2_bufs[index].m.offset);
+	}
+
+	if (ret < 0) {
+		dev_err(&vout->video_dev->dev,
+			"unable to update buffer %d address rc=%d\n",
+			vout->next_rdy_ipu_buf, ret);
+		goto exit0;
+	}
+
+	/* set next buffer ready */
+	if (LOAD_3FIELDS(vout))
+		ret = ipu_select_multi_vdi_buffer(vout->next_rdy_ipu_buf);
+	else
+		ret = ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+				vout->next_rdy_ipu_buf);
+	if (ret < 0) {
+		dev_err(&vout->video_dev->dev,
+				"unable to set IPU buffer ready\n");
+		goto exit0;
+	}
+
+	/* Non IC split action */
+	if (!vout->pp_split)
+		vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+
+	/* Setup timer for next buffer */
+	index = peek_next_buf(&vout->ready_q);
+	if (index != -1)
+		setup_next_buf_timer(vout, index);
+	else
+		vout->state = STATE_STREAM_PAUSED;
+
+	if (vout->state == STATE_STREAM_STOPPING) {
+		if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
+			vout->state = STATE_STREAM_OFF;
+		}
+	}
+
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+
+	return;
+
+exit0:
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+}
+
+static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id)
+{
+	int last_buf;
+	int index;
+	unsigned long lock_flags = 0;
+	vout_data *vout = dev_id;
+	int pp_out_buf_left_right = 0;
+	int disp_buf_num = 0;
+	int disp_buf_num_next = 1;
+	int local_buffer = 0;
+	int pp_out_buf_offset = 0;
+	int pp_out_buf_up_down = 0;
+	int release_buffer = 0;
+	u32 eba_offset = 0;
+	u32 vertical_offset = 0;
+	u16 x_pos;
+	u16 y_pos;
+	int ret = -1;
+
+	spin_lock_irqsave(&g_lock, lock_flags);
+
+	g_irq_cnt++;
+
+	/* Process previous buffer */
+	if (LOAD_3FIELDS(vout))
+		last_buf = vout->ipu_buf_p[vout->next_done_ipu_buf];
+	else
+		last_buf = vout->ipu_buf[vout->next_done_ipu_buf];
+
+	if (last_buf != -1) {
+		/* If IC split mode on, update output buffer number */
+		if (vout->pp_split) {
+			pp_out_buf_up_down = vout->pp_split_buf_num & 1;/* left/right stripe */
+			pp_out_buf_left_right = (vout->pp_split_buf_num >> 1) & 1; /* up/down */
+			local_buffer = (vout->pp_split == 1) ? pp_out_buf_up_down :
+					pp_out_buf_left_right;
+			disp_buf_num = vout->pp_split_buf_num >> 2;
+			disp_buf_num_next =
+					((vout->pp_split_buf_num + (vout->pp_split << 0x1)) & 7) >> 2;
+			if ((!pp_out_buf_left_right) ||
+				((!pp_out_buf_up_down) && (vout->pp_split == 1))) {
+				if (vout->pp_split == 1) {
+						eba_offset = ((pp_out_buf_left_right + pp_out_buf_up_down) & 1) ?
+									vout->pp_right_stripe.input_column :
+									vout->pp_left_stripe.input_column;
+						vertical_offset = pp_out_buf_up_down ?
+									vout->pp_up_stripe.input_column :
+									vout->pp_down_stripe.input_column;
+
+				} else {
+						eba_offset = pp_out_buf_left_right ?
+									vout->pp_left_stripe.input_column :
+									vout->pp_right_stripe.input_column;
+						vertical_offset = pp_out_buf_left_right ?
+									vout->pp_up_stripe.input_column :
+									vout->pp_down_stripe.input_column;
+				}
+
+				ret = ipu_update_channel_buffer(vout->post_proc_ch,
+						IPU_INPUT_BUFFER,
+						(1 - local_buffer),
+						(vout->v4l2_bufs[vout->ipu_buf[disp_buf_num]].m.offset)
+						+ eba_offset + vertical_offset * vout->bytesperline);
+				ret += ipu_update_channel_offset(vout->post_proc_ch,
+								IPU_INPUT_BUFFER,
+								vout->v2f.fmt.pix.pixelformat,
+								vout->v2f.fmt.pix.width,
+								vout->v2f.fmt.pix.height,
+								vout->bytesperline,
+								vout->offset.u_offset,
+								vout->offset.v_offset,
+								vertical_offset,
+								eba_offset);
+
+				/* select right stripe */
+				ret += ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+							(1 - local_buffer));
+				if (ret < 0)
+					dev_err(&vout->video_dev->dev,
+					"unable to set IPU buffer ready\n");
+					vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+
+			} else {/* last stripe is done, run display refresh */
+				select_display_buffer(vout, disp_buf_num);
+				vout->ipu_buf[vout->next_done_ipu_buf] = -1;
+				vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
+				vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf;
+			}
+
+			/* offset for next buffer's EBA */
+			eba_offset = 0;
+			if (vout->pp_split == 1) {
+				pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+								vout->pp_left_stripe.output_column :
+								vout->pp_right_stripe.output_column;
+
+				eba_offset = ((vout->pp_split_buf_num & 1) ?
+								vout->pp_down_stripe.output_column :
+								vout->pp_up_stripe.output_column);
+
+			} else {
+				pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+									vout->pp_right_stripe.output_column :
+									vout->pp_left_stripe.output_column;
+				eba_offset = ((vout->pp_split_buf_num >> 1) & 1) ?
+									vout->pp_down_stripe.output_column :
+									vout->pp_up_stripe.output_column;
+			}
+
+			if (vout->cur_disp_output == 5) {
+				x_pos = (vout->crop_current.left / 8) * 8;
+				y_pos = vout->crop_current.top;
+				eba_offset += (vout->xres * y_pos + x_pos) * vout->bpp / 8;
+			}
+
+
+			/* next buffer update */
+			eba_offset = vout->display_bufs[disp_buf_num_next] +
+						pp_out_buf_offset + eba_offset;
+
+			ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
+						local_buffer, eba_offset);
+
+			/* next buffer ready */
+			ret = ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, local_buffer);
+
+			/* next stripe_buffer index 0..7 */
+			vout->pp_split_buf_num = (vout->pp_split_buf_num + vout->pp_split) & 0x7;
+
+
+		} else {
+			/* show to display */
+			select_display_buffer(vout, vout->next_done_ipu_buf);
+			ret += ipu_select_buffer(vout->display_input_ch, IPU_OUTPUT_BUFFER,
+					vout->next_done_ipu_buf);
+		}
+
+		/* release buffer. For split mode: if second stripe is done */
+		release_buffer = vout->pp_split ? (!(vout->pp_split_buf_num & 0x3)) : 1;
+		if (release_buffer) {
+			g_buf_output_cnt++;
+			vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE;
+			queue_buf(&vout->done_q, last_buf);
+			wake_up_interruptible(&vout->v4l_bufq);
+			vout->ipu_buf[vout->next_done_ipu_buf] = -1;
+			if (LOAD_3FIELDS(vout)) {
+				vout->ipu_buf_p[vout->next_done_ipu_buf] = -1;
+				vout->ipu_buf_n[vout->next_done_ipu_buf] = -1;
+			}
+			vout->next_done_ipu_buf = !vout->next_done_ipu_buf;
+		}
+	} /* end of last_buf != -1 */
+
+	if (vout->state == STATE_STREAM_STOPPING) {
+		if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) {
+			vout->state = STATE_STREAM_OFF;
+		}
+	} else if ((vout->state == STATE_STREAM_PAUSED)
+		   && ((index = peek_next_buf(&vout->ready_q)) != -1)) {
+		/* Setup timer for next buffer, when stream has been paused */
+		pr_debug("next index %d\n", index);
+		setup_next_buf_timer(vout, index);
+		vout->state = STATE_STREAM_ON;
+	}
+
+	spin_unlock_irqrestore(&g_lock, lock_flags);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ *  Initialize VDI channels
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int init_VDI_channel(vout_data *vout, ipu_channel_params_t params)
+{
+	struct device *dev = &vout->video_dev->dev;
+
+	if (ipu_init_channel(MEM_VDI_PRP_VF_MEM, &params) != 0) {
+		dev_dbg(dev, "Error initializing VDI current channel\n");
+		return -EINVAL;
+	}
+	if (LOAD_3FIELDS(vout)) {
+		if (ipu_init_channel(MEM_VDI_PRP_VF_MEM_P, &params) != 0) {
+			dev_err(dev, "Error initializing VDI previous channel\n");
+			return -EINVAL;
+		}
+		if (ipu_init_channel(MEM_VDI_PRP_VF_MEM_N, &params) != 0) {
+			dev_err(dev, "Error initializing VDI next channel\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Initialize VDI channel buffers
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt,
+				   uint16_t in_width, uint16_t in_height,
+				   uint32_t stride,
+				   uint32_t u_offset, uint32_t v_offset)
+{
+	struct device *dev = &vout->video_dev->dev;
+
+	if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER,
+				    in_pixel_fmt, in_width, in_height, stride,
+				    IPU_ROTATE_NONE,
+				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
+				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
+				    u_offset, v_offset) != 0) {
+		dev_err(dev, "Error initializing VDI current input buffer\n");
+		return -EINVAL;
+	}
+	if (LOAD_3FIELDS(vout)) {
+		if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM_P,
+					    IPU_INPUT_BUFFER,
+					    in_pixel_fmt, in_width, in_height,
+					    stride, IPU_ROTATE_NONE,
+					    vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline,
+					    vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline,
+					    u_offset, v_offset) != 0) {
+			dev_err(dev, "Error initializing VDI previous input buffer\n");
+			return -EINVAL;
+		}
+		if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM_N,
+					    IPU_INPUT_BUFFER,
+					    in_pixel_fmt, in_width, in_height,
+					    stride, IPU_ROTATE_NONE,
+					    vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline,
+					    vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline,
+					    u_offset, v_offset) != 0) {
+			dev_err(dev, "Error initializing VDI next input buffer\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Initialize VDI path
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int init_VDI(ipu_channel_params_t params, vout_data *vout,
+			struct device *dev, struct fb_info *fbi,
+			u16 out_width, u16 out_height)
+{
+	params.mem_prp_vf_mem.in_width = vout->v2f.fmt.pix.width;
+	params.mem_prp_vf_mem.in_height = vout->v2f.fmt.pix.height;
+	params.mem_prp_vf_mem.motion_sel = vout->motion_sel;
+	params.mem_prp_vf_mem.field_fmt = vout->field_fmt;
+	params.mem_prp_vf_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat;
+	params.mem_prp_vf_mem.out_width = out_width;
+	params.mem_prp_vf_mem.out_height = out_height;
+	params.mem_prp_vf_mem.out_pixel_fmt = bpp_to_fmt(fbi);
+
+	if (init_VDI_channel(vout, params) != 0) {
+		dev_err(dev, "Error init_VDI_channel channel\n");
+		return -EINVAL;
+	}
+
+	if (init_VDI_in_channel_buffer(vout,
+				       params.mem_prp_vf_mem.in_pixel_fmt,
+				       params.mem_prp_vf_mem.in_width,
+				       params.mem_prp_vf_mem.in_height,
+				       bytes_per_pixel(params.mem_prp_vf_mem.
+						       in_pixel_fmt),
+				       vout->offset.u_offset,
+				       vout->offset.v_offset) != 0) {
+		return -EINVAL;
+	}
+
+	if (!ipu_can_rotate_in_place(vout->rotate)) {
+		if (vout->rot_pp_bufs[0]) {
+			mxc_free_buffers(vout->rot_pp_bufs,
+					 vout->rot_pp_bufs_vaddr, 2,
+					 vout->display_buf_size);
+		}
+		if (mxc_allocate_buffers
+		    (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2,
+		     vout->display_buf_size) < 0) {
+			return -ENOBUFS;
+		}
+
+		if (ipu_init_channel_buffer(vout->post_proc_ch,
+					    IPU_OUTPUT_BUFFER,
+					    params.mem_prp_vf_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_width,
+					    IPU_ROTATE_NONE,
+					    vout->rot_pp_bufs[0],
+					    vout->rot_pp_bufs[1], 0, 0) != 0) {
+			dev_err(dev, "Error initializing PRP output buffer\n");
+			return -EINVAL;
+		}
+
+		if (ipu_init_channel(MEM_ROT_VF_MEM, NULL) != 0) {
+			dev_err(dev, "Error initializing PP ROT channel\n");
+			return -EINVAL;
+		}
+		if (ipu_init_channel_buffer(MEM_ROT_VF_MEM,
+					    IPU_INPUT_BUFFER,
+					    params.mem_prp_vf_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_width,
+					    vout->rotate,
+					    vout->rot_pp_bufs[0],
+					    vout->rot_pp_bufs[1], 0, 0) != 0) {
+			dev_err(dev,
+				"Error initializing PP ROT input buffer\n");
+			return -EINVAL;
+		}
+
+		/* swap width and height */
+		if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
+			out_width = vout->crop_current.width;
+			out_height = vout->crop_current.height;
+		}
+
+		if (ipu_init_channel_buffer(MEM_ROT_VF_MEM,
+					    IPU_OUTPUT_BUFFER,
+					    params.mem_prp_vf_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_width,
+					    IPU_ROTATE_NONE,
+					    vout->display_bufs[0],
+					    vout->display_bufs[1], 0, 0) != 0) {
+			dev_err(dev,
+				"Error initializing PP-VDI output buffer\n");
+			return -EINVAL;
+		}
+
+		if (ipu_link_channels(vout->post_proc_ch, MEM_ROT_VF_MEM) < 0)
+			return -EINVAL;
+
+		vout->display_input_ch = MEM_ROT_VF_MEM;
+		ipu_enable_channel(MEM_ROT_VF_MEM);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1);
+	} else {
+		if (ipu_init_channel_buffer(vout->post_proc_ch,
+					    IPU_OUTPUT_BUFFER,
+					    params.mem_prp_vf_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_width,
+					    vout->rotate,
+					    vout->display_bufs[0],
+					    vout->display_bufs[1], 0, 0) != 0) {
+			dev_err(dev,
+				"Error initializing PP-VDI output buffer\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * Initialize PP path
+ *
+ * @param params    structure ipu_channel_params_t
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int init_PP(ipu_channel_params_t *params, vout_data *vout,
+		   struct device *dev, struct fb_info *fbi,
+		   u16 out_width, u16 out_height)
+{
+	u16 in_width, out_stride; /* stride of output channel */
+	u32 eba_offset;
+	u16 x_pos;
+	u16 y_pos;
+	eba_offset = 0;
+	x_pos = 0;
+	y_pos = 0;
+
+	params->mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi);
+
+	if (vout->cur_disp_output == 5) {
+		x_pos = (vout->crop_current.left / 8) * 8;
+		y_pos = vout->crop_current.top;
+		eba_offset = (vout->xres*y_pos + x_pos) *
+				bytes_per_pixel(params->mem_pp_mem.out_pixel_fmt);
+	}
+
+	vout->bpp = fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt);
+	out_stride = vout->xres *
+				bytes_per_pixel(params->mem_pp_mem.out_pixel_fmt);
+	in_width = params->mem_pp_mem.in_width = vout->v2f.fmt.pix.width;
+	params->mem_pp_mem.in_height = vout->v2f.fmt.pix.height;
+	params->mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat;
+	params->mem_pp_mem.out_width = out_width;
+	params->mem_pp_mem.out_height = out_height;
+	params->mem_pp_mem.outh_resize_ratio = 0; /* 0 means unused */
+	params->mem_pp_mem.outv_resize_ratio = 0; /* 0 means unused */
+	/* split IC by two stripes, the by pass is impossible*/
+	if (vout->pp_split) {
+		vout->pp_left_stripe.input_column = 0;
+		vout->pp_left_stripe.output_column = 0;
+		vout->pp_right_stripe.input_column = 0;
+		vout->pp_right_stripe.output_column = 0;
+		vout->pp_up_stripe.input_column = 0;
+		vout->pp_up_stripe.output_column = 0;
+		vout->pp_down_stripe.input_column = 0;
+		vout->pp_down_stripe.output_column = 0;
+		if (vout->pp_split != 3) {
+			ipu_calc_stripes_sizes(
+				params->mem_pp_mem.in_width, /* input frame width;>1 */
+				params->mem_pp_mem.out_width, /* output frame width; >1 */
+				ipu_ic_out_max_width_size,
+				(((unsigned long long)1) << 32), /* 32bit for fractional*/
+				1,	/* equal stripes */
+				params->mem_pp_mem.in_pixel_fmt,
+				params->mem_pp_mem.out_pixel_fmt,
+				&(vout->pp_left_stripe),
+				&(vout->pp_right_stripe));
+
+			vout->pp_left_stripe.input_column = vout->pp_left_stripe.input_column *
+								fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8;
+			vout->pp_left_stripe.output_column = vout->pp_left_stripe.output_column *
+								fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8;
+			vout->pp_right_stripe.input_column = vout->pp_right_stripe.input_column *
+								fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8;
+			vout->pp_right_stripe.output_column = vout->pp_right_stripe.output_column *
+								fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8;
+
+
+		/* updare parameters */
+		params->mem_pp_mem.in_width = vout->pp_left_stripe.input_width;
+		params->mem_pp_mem.out_width = vout->pp_left_stripe.output_width;
+		out_width = vout->pp_left_stripe.output_width;
+		/* for using in ic_init*/
+		params->mem_pp_mem.outh_resize_ratio = vout->pp_left_stripe.irr;
+		}
+		if (vout->pp_split != 2) {
+			ipu_calc_stripes_sizes(
+				params->mem_pp_mem.in_height, /* input frame width;>1 */
+				params->mem_pp_mem.out_height, /* output frame width; >1 */
+				ipu_ic_out_max_height_size,
+				(((unsigned long long)1) << 32),/* 32bit for fractional */
+				1,	/* equal stripes */
+				params->mem_pp_mem.in_pixel_fmt,
+				params->mem_pp_mem.out_pixel_fmt,
+				&(vout->pp_up_stripe),
+				&(vout->pp_down_stripe));
+			vout->pp_down_stripe.output_column = vout->pp_down_stripe.output_column * out_stride;
+			vout->pp_up_stripe.output_column = vout->pp_up_stripe.output_column * out_stride;
+			params->mem_pp_mem.outv_resize_ratio = vout->pp_up_stripe.irr;
+			params->mem_pp_mem.in_height = vout->pp_up_stripe.input_width;/*height*/
+			out_height = vout->pp_up_stripe.output_width;/*height*/
+			if (vout->pp_split == 3)
+				vout->pp_split = 2;/*2 vertical stripe as two horizontal stripes */
+		}
+		vout->pp_split_buf_num = 0;
+	}
+
+	if (ipu_init_channel(vout->post_proc_ch, params) != 0) {
+		dev_err(dev, "Error initializing PP channel\n");
+		return -EINVAL;
+	}
+
+	if (ipu_init_channel_buffer(vout->post_proc_ch,
+				    IPU_INPUT_BUFFER,
+				    params->mem_pp_mem.in_pixel_fmt,
+				    params->mem_pp_mem.in_width,
+				    params->mem_pp_mem.in_height,
+				    vout->v2f.fmt.pix.bytesperline /
+				    bytes_per_pixel(params->mem_pp_mem.
+					    in_pixel_fmt),
+				    IPU_ROTATE_NONE,
+				    vout->v4l2_bufs[vout->ipu_buf[0]].m.offset,
+				    vout->v4l2_bufs[vout->ipu_buf[1]].m.offset,
+				    vout->offset.u_offset,
+				    vout->offset.v_offset) != 0) {
+		dev_err(dev, "Error initializing PP input buffer\n");
+		return -EINVAL;
+	}
+
+	if (!ipu_can_rotate_in_place(vout->rotate)) {
+		if (vout->rot_pp_bufs[0]) {
+			mxc_free_buffers(vout->rot_pp_bufs,
+					 vout->rot_pp_bufs_vaddr, 2,
+					 vout->display_buf_size);
+		}
+		if (mxc_allocate_buffers
+		    (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2,
+		     vout->display_buf_size) < 0) {
+			return -ENOBUFS;
+		}
+
+		if (ipu_init_channel_buffer(vout->post_proc_ch,
+					    IPU_OUTPUT_BUFFER,
+					    params->mem_pp_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_stride,
+					    IPU_ROTATE_NONE,
+					    vout->rot_pp_bufs[0] + eba_offset,
+					    vout->rot_pp_bufs[1] + eba_offset, 0, 0) != 0) {
+			dev_err(dev, "Error initializing PP output buffer\n");
+			return -EINVAL;
+		}
+
+		if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) {
+			dev_err(dev, "Error initializing PP ROT channel\n");
+			return -EINVAL;
+		}
+		if (ipu_init_channel_buffer(MEM_ROT_PP_MEM,
+					    IPU_INPUT_BUFFER,
+					    params->mem_pp_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_stride,
+					    vout->rotate,
+					    vout->rot_pp_bufs[0],
+					    vout->rot_pp_bufs[1], 0, 0) != 0) {
+			dev_err(dev,
+				"Error initializing PP ROT input buffer\n");
+			return -EINVAL;
+		}
+
+		/* swap width and height */
+		if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
+			out_width = vout->crop_current.width;
+			out_height = vout->crop_current.height;
+		}
+
+		if (ipu_init_channel_buffer(MEM_ROT_PP_MEM,
+					    IPU_OUTPUT_BUFFER,
+					    params->mem_pp_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_stride,
+					    IPU_ROTATE_NONE,
+					    vout->display_bufs[0] + eba_offset,
+					    vout->display_bufs[1] + eba_offset, 0, 0) != 0) {
+			dev_err(dev, "Error initializing PP output buffer\n");
+			return -EINVAL;
+		}
+
+		if (ipu_link_channels(vout->post_proc_ch, MEM_ROT_PP_MEM) < 0)
+			return -EINVAL;
+
+		vout->display_input_ch = MEM_ROT_PP_MEM;
+		ipu_enable_channel(MEM_ROT_PP_MEM);
+		ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1);
+	} else {
+		if (ipu_init_channel_buffer(vout->post_proc_ch,
+					    IPU_OUTPUT_BUFFER,
+					    params->mem_pp_mem.
+					    out_pixel_fmt, out_width,
+					    out_height, out_stride,
+					    vout->rotate,
+					    vout->display_bufs[0] + eba_offset,
+					    vout->display_bufs[1] + eba_offset, 0, 0) != 0) {
+			dev_err(dev, "Error initializing PP output buffer\n");
+			return -EINVAL;
+		}
+	}
+
+	/* fix EBAs for IDMAC channels */
+	if (vout->pp_split) {
+		ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+									0,
+									vout->v4l2_bufs[vout->ipu_buf[0]].m.offset +
+									vout->pp_left_stripe.input_column +
+									vout->pp_up_stripe.input_column * vout->bytesperline);
+
+
+		ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER,
+									1,
+									vout->v4l2_bufs[vout->ipu_buf[0]].m.offset +
+									vout->pp_right_stripe.input_column +
+									vout->pp_up_stripe.input_column * vout->bytesperline);
+
+		ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
+									0,
+									vout->display_bufs[0] + eba_offset +
+									vout->pp_left_stripe.output_column +
+									vout->pp_up_stripe.output_column);
+
+		ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER,
+									1,
+									vout->display_bufs[0] + eba_offset +
+									vout->pp_right_stripe.output_column +
+									vout->pp_up_stripe.output_column);
+	}
+
+	return 0;
+}
+
+/*!
+ * Start the output stream
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamon(vout_data * vout)
+{
+	struct device *dev = &vout->video_dev->dev;
+	ipu_channel_params_t params;
+	struct mxcfb_pos fb_pos;
+	struct fb_var_screeninfo fbvar;
+	struct fb_info *fbi =
+	    registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	u16 out_width;
+	u16 out_height;
+	mm_segment_t old_fs;
+	unsigned int ipu_ch = CHAN_NONE;
+	int rc = 0;
+
+	dev_dbg(dev, "mxc_v4l2out_streamon: field format=%d\n",
+		vout->field_fmt);
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state != STATE_STREAM_OFF)
+		return -EBUSY;
+
+	if (queue_size(&vout->ready_q) < 2) {
+		dev_err(dev, "2 buffers not been queued yet!\n");
+		return -EINVAL;
+	}
+
+	if ((vout->field_fmt == V4L2_FIELD_BOTTOM) || (vout->field_fmt == V4L2_FIELD_TOP)) {
+		dev_err(dev, "4 queued buffers need, not supported yet!\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * params init, check whether operation exceed the IC limitation:
+	 * whether split mode used ( ipu version >= ipuv3 only)
+	 */
+	g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0;
+	out_width = vout->crop_current.width;
+	out_height = vout->crop_current.height;
+	vout->next_done_ipu_buf = 0;
+	vout->next_rdy_ipu_buf = 1;
+	vout->pp_split = 0;
+	ipu_ic_out_max_height_size = 1024;
+#ifdef CONFIG_MXC_IPU_V1
+	if (cpu_is_mx35())
+		ipu_ic_out_max_width_size = 800;
+	else
+		ipu_ic_out_max_width_size = 720;
+#else
+	ipu_ic_out_max_width_size = 1024;
+#endif
+	if ((out_width > ipu_ic_out_max_width_size) ||
+		(out_height > ipu_ic_out_max_height_size))
+		vout->pp_split = 4;
+	if (!INTERLACED_CONTENT(vout)) {
+		vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0;
+		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
+		/* split IC by two stripes, the by pass is impossible*/
+		if ((out_width != vout->v2f.fmt.pix.width ||
+			out_height != vout->v2f.fmt.pix.height) &&
+			vout->pp_split) {
+			vout->ipu_buf[1] = vout->ipu_buf[0];
+			vout->frame_count = 1;
+			if ((out_width > ipu_ic_out_max_width_size) &&
+				(out_height > ipu_ic_out_max_height_size))
+				vout->pp_split = 1; /*4 stripes*/
+			else if (!(out_height > ipu_ic_out_max_height_size))
+				vout->pp_split = 2; /*two horizontal stripes */
+			else
+				vout->pp_split = 3; /*2 vertical stripes*/
+		} else {
+			vout->ipu_buf[1] = dequeue_buf(&vout->ready_q);
+			vout->frame_count = 2;
+		}
+	} else if (!LOAD_3FIELDS(vout)) {
+		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
+		vout->ipu_buf[1] = -1;
+		vout->frame_count = 1;
+	} else {
+		vout->ipu_buf_p[0] = dequeue_buf(&vout->ready_q);
+		vout->ipu_buf[0] = dequeue_buf(&vout->ready_q);
+		vout->ipu_buf_n[0] = vout->ipu_buf[0];
+		vout->ipu_buf_p[1] = -1;
+		vout->ipu_buf[1] = -1;
+		vout->ipu_buf_n[1] = -1;
+		last_index_n = vout->ipu_buf_n[0];
+		vout->frame_count = 2;
+	}
+
+	/*
+	 * Bypass IC if resizing and rotation are not needed
+	 * Meanwhile, apply IC bypass to SDC only
+	 */
+	fbvar = fbi->var;
+	vout->xres = fbvar.xres;
+	vout->yres = fbvar.yres;
+
+	if (vout->cur_disp_output == 3 || vout->cur_disp_output == 5) {
+		fbvar.bits_per_pixel = 16;
+		if (format_is_yuv(vout->v2f.fmt.pix.pixelformat))
+			fbvar.nonstd = IPU_PIX_FMT_UYVY;
+		else
+			fbvar.nonstd = 0;
+		if (vout->cur_disp_output == 3) {
+			fbvar.xres = out_width;
+			fbvar.yres = out_height;
+			vout->xres = fbvar.xres;
+			vout->yres = fbvar.yres;
+		}
+
+		fbvar.xres_virtual = fbvar.xres;
+		fbvar.yres_virtual = fbvar.yres * 2;
+	}
+
+	if (out_width == vout->v2f.fmt.pix.width &&
+	    out_height == vout->v2f.fmt.pix.height &&
+	    vout->xres == out_width &&
+	    vout->yres == out_height &&
+	    ipu_can_rotate_in_place(vout->rotate) &&
+	    (vout->bytesperline ==
+	     bytes_per_pixel(vout->v2f.fmt.pix.pixelformat) * out_width) &&
+	    !INTERLACED_CONTENT(vout)) {
+		vout->ic_bypass = 1;
+	} else {
+		vout->ic_bypass = 0;
+	}
+
+#ifdef CONFIG_MXC_IPU_V1
+	/* IPUv1 needs IC to do CSC */
+	if (format_is_yuv(vout->v2f.fmt.pix.pixelformat) !=
+	    format_is_yuv(bpp_to_fmt(fbi)))
+		vout->ic_bypass = 0;
+#endif
+
+	if (fbi->fbops->fb_ioctl) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
+				(unsigned long)&ipu_ch);
+		set_fs(old_fs);
+	}
+
+	if (ipu_ch == CHAN_NONE) {
+		dev_err(dev, "Can not get display ipu channel\n");
+		return -EINVAL;
+	}
+
+	vout->display_ch = ipu_ch;
+
+	if (vout->ic_bypass) {
+		pr_debug("Bypassing IC\n");
+		vout->pp_split = 0;
+		switch (vout->v2f.fmt.pix.pixelformat) {
+			case V4L2_PIX_FMT_YUV420:
+			case V4L2_PIX_FMT_YVU420:
+			case V4L2_PIX_FMT_NV12:
+				fbvar.bits_per_pixel = 12;
+				break;
+			case V4L2_PIX_FMT_YUV422P:
+				fbvar.bits_per_pixel = 16;
+				break;
+			default:
+				fbvar.bits_per_pixel = 8*
+					bytes_per_pixel(vout->v2f.fmt.pix.pixelformat);
+		}
+		fbvar.nonstd = vout->v2f.fmt.pix.pixelformat;
+	}
+
+	/* Init display channel through fb API */
+	fbvar.activate |= FB_ACTIVATE_FORCE;
+	fb_set_var(fbi, &fbvar);
+
+	if (fbi->fbops->fb_ioctl && vout->display_ch == MEM_FG_SYNC) {
+		fb_pos.x = vout->crop_current.left;
+		fb_pos.y = vout->crop_current.top;
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
+				(unsigned long)&fb_pos);
+		set_fs(old_fs);
+	}
+
+	vout->display_bufs[1] = fbi->fix.smem_start;
+	vout->display_bufs[0] = fbi->fix.smem_start +
+		(fbi->fix.line_length * vout->yres);
+	vout->display_buf_size = vout->xres *
+		vout->yres * fbi->var.bits_per_pixel / 8;
+
+	/* fill black color for init fb, we assume fb has double buffer*/
+	if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) {
+		int i;
+
+		if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) ||
+			(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) ||
+			(!vout->ic_bypass)) {
+			short * tmp = (short *) fbi->screen_base;
+			short color;
+			if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
+				color = 0x8000;
+			else
+				color = 0x80;
+			for (i = 0; i < (fbi->fix.line_length * fbi->var.yres_virtual)/2;
+					i++, tmp++)
+				*tmp = color;
+		} else if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) ||
+				(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) ||
+				(vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)) {
+			char * base = (char *)fbi->screen_base;
+			int j, screen_size = fbi->var.xres * fbi->var.yres;
+
+			for (j = 0; j < 2; j++) {
+				memset(base, 0, screen_size);
+				base += screen_size;
+				for (i = 0; i < screen_size/2; i++, base++)
+					*base = 0x80;
+			}
+		} else if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
+			char * base = (char *)fbi->screen_base;
+			int j, screen_size = fbi->var.xres * fbi->var.yres;
+
+			for (j = 0; j < 2; j++) {
+				memset(base, 0, screen_size);
+				base += screen_size;
+				for (i = 0; i < screen_size; i++, base++)
+					*base = 0x80;
+			}
+		}
+	} else
+		memset(fbi->screen_base, 0x0,
+				fbi->fix.line_length * fbi->var.yres_virtual);
+
+	if (INTERLACED_CONTENT(vout))
+		vout->post_proc_ch = MEM_VDI_PRP_VF_MEM;
+	else if (!vout->ic_bypass)
+		vout->post_proc_ch = MEM_PP_MEM;
+
+	/* Init IC channel */
+	if (!vout->ic_bypass) {
+		if (vout->rotate >= IPU_ROTATE_90_RIGHT) {
+			out_width = vout->crop_current.height;
+			out_height = vout->crop_current.width;
+		}
+		vout->display_input_ch = vout->post_proc_ch;
+		memset(&params, 0, sizeof(params));
+		if (INTERLACED_CONTENT(vout)) {
+			if (vout->pp_split) {
+				dev_err(&vout->video_dev->dev, "VDI split has not supported yet.\n");
+				return -1;
+			} else
+				rc = init_VDI(params, vout, dev, fbi, out_width, out_height);
+		} else {
+			rc = init_PP(&params, vout, dev, fbi, out_width, out_height);
+		}
+		if (rc < 0)
+			return rc;
+	}
+
+	if (!vout->ic_bypass) {
+		switch (vout->display_input_ch) {
+		case MEM_PP_MEM:
+			vout->work_irq = IPU_IRQ_PP_OUT_EOF;
+			break;
+		case MEM_VDI_PRP_VF_MEM:
+			vout->work_irq = IPU_IRQ_PRP_VF_OUT_EOF;
+			break;
+		case MEM_ROT_VF_MEM:
+			vout->work_irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
+			break;
+		case MEM_ROT_PP_MEM:
+			vout->work_irq = IPU_IRQ_PP_ROT_OUT_EOF;
+			break;
+		default:
+			dev_err(&vout->video_dev->dev,
+				"not support channel, should not be here\n");
+		}
+	} else
+		vout->work_irq = -1;
+
+	if (!vout->ic_bypass && (vout->work_irq > 0)) {
+		ipu_clear_irq(vout->work_irq);
+		ipu_request_irq(vout->work_irq,
+				mxc_v4l2out_work_irq_handler,
+				0, vout->video_dev->name, vout);
+	}
+
+	vout->state = STATE_STREAM_PAUSED;
+
+	/* Enable display and IC channels */
+	if (fbi) {
+		acquire_console_sem();
+		fb_blank(fbi, FB_BLANK_UNBLANK);
+		release_console_sem();
+	} else {
+		ipu_enable_channel(vout->display_ch);
+	}
+	if (!vout->ic_bypass) {
+#ifndef CONFIG_MXC_IPU_V1
+		ipu_enable_channel(vout->post_proc_ch);
+#endif
+		if (LOAD_3FIELDS(vout)) {
+			ipu_enable_channel(MEM_VDI_PRP_VF_MEM_P);
+			ipu_enable_channel(MEM_VDI_PRP_VF_MEM_N);
+			ipu_select_multi_vdi_buffer(0);
+		} else if (INTERLACED_CONTENT(vout)) {
+			ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
+		} else {
+			ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0);
+			if (!vout->pp_split)
+				ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1);
+		}
+		ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1);
+#ifdef CONFIG_MXC_IPU_V1
+		ipu_enable_channel(vout->post_proc_ch);
+#endif
+	} else {
+		ipu_update_channel_buffer(vout->display_ch,
+				IPU_INPUT_BUFFER,
+				0, vout->v4l2_bufs[vout->ipu_buf[0]].m.offset);
+		ipu_update_channel_buffer(vout->display_ch,
+				IPU_INPUT_BUFFER,
+				1, vout->v4l2_bufs[vout->ipu_buf[1]].m.offset);
+		if (vout->offset.u_offset || vout->offset.v_offset)
+			/* only update u/v offset */
+			ipu_update_channel_offset(vout->display_ch,
+					IPU_INPUT_BUFFER,
+					vout->v2f.fmt.pix.pixelformat,
+					vout->v2f.fmt.pix.width,
+					vout->v2f.fmt.pix.height,
+					vout->bytesperline,
+					vout->offset.u_offset,
+					vout->offset.v_offset,
+					0,
+					0);
+		ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0);
+		queue_work(vout->v4l_wq, &vout->timer_work);
+	}
+
+	vout->start_jiffies = jiffies;
+
+	msleep(1);
+
+	dev_dbg(dev,
+		"streamon: start time = %lu jiffies\n", vout->start_jiffies);
+
+	return 0;
+}
+
+/*!
+ * Shut down the voutera
+ *
+ * @param vout      structure vout_data *
+ *
+ * @return status  0 Success
+ */
+static int mxc_v4l2out_streamoff(vout_data * vout)
+{
+	struct fb_info *fbi =
+	    registered_fb[vout->output_fb_num[vout->cur_disp_output]];
+	int i, retval = 0;
+	unsigned long lockflag = 0;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (vout->state == STATE_STREAM_OFF) {
+		return 0;
+	}
+
+	if (!vout->ic_bypass)
+		ipu_free_irq(vout->work_irq, vout);
+
+	if (vout->ic_bypass)
+		cancel_work_sync(&vout->timer_work);
+
+	spin_lock_irqsave(&g_lock, lockflag);
+
+	del_timer(&vout->output_timer);
+
+	if (vout->state == STATE_STREAM_ON) {
+		vout->state = STATE_STREAM_STOPPING;
+	}
+
+	spin_unlock_irqrestore(&g_lock, lockflag);
+
+	if (vout->display_ch == MEM_FG_SYNC) {
+		struct mxcfb_pos fb_pos;
+		mm_segment_t old_fs;
+
+		fb_pos.x = 0;
+		fb_pos.y = 0;
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
+					(unsigned long)&fb_pos);
+			set_fs(old_fs);
+		}
+	}
+
+	if (vout->ic_bypass) {
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
+
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
+		}
+
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+	} else if (vout->post_proc_ch == MEM_PP_MEM ||
+	    vout->post_proc_ch == MEM_PRP_VF_MEM) {
+		/* SDC with Rotation */
+		if (!ipu_can_rotate_in_place(vout->rotate)) {
+			ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM);
+			ipu_disable_channel(MEM_ROT_PP_MEM, true);
+
+			if (vout->rot_pp_bufs[0]) {
+				mxc_free_buffers(vout->rot_pp_bufs,
+						 vout->rot_pp_bufs_vaddr, 2,
+						 vout->display_buf_size);
+			}
+		}
+		ipu_disable_channel(MEM_PP_MEM, true);
+
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
+
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
+		}
+
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+
+		ipu_uninit_channel(MEM_PP_MEM);
+		if (!ipu_can_rotate_in_place(vout->rotate))
+			ipu_uninit_channel(MEM_ROT_PP_MEM);
+	} else if (INTERLACED_CONTENT(vout) &&
+		(vout->post_proc_ch == MEM_VDI_PRP_VF_MEM)) {
+		if (!ipu_can_rotate_in_place(vout->rotate)) {
+			ipu_unlink_channels(MEM_VDI_PRP_VF_MEM,
+					    MEM_ROT_VF_MEM);
+			ipu_disable_channel(MEM_ROT_VF_MEM, true);
+
+			if (vout->rot_pp_bufs[0]) {
+				mxc_free_buffers(vout->rot_pp_bufs,
+						 vout->rot_pp_bufs_vaddr, 2,
+						 vout->display_buf_size);
+			}
+		}
+
+		ipu_disable_channel(MEM_VDI_PRP_VF_MEM, true);
+		if (LOAD_3FIELDS(vout)) {
+			ipu_disable_channel(MEM_VDI_PRP_VF_MEM_P, true);
+			ipu_disable_channel(MEM_VDI_PRP_VF_MEM_N, true);
+		}
+
+		fbi->var.activate |= FB_ACTIVATE_FORCE;
+		fb_set_var(fbi, &fbi->var);
+
+		if (vout->display_ch == MEM_FG_SYNC) {
+			acquire_console_sem();
+			fb_blank(fbi, FB_BLANK_POWERDOWN);
+			release_console_sem();
+		}
+
+		vout->display_bufs[0] = 0;
+		vout->display_bufs[1] = 0;
+
+		ipu_uninit_channel(MEM_VDI_PRP_VF_MEM);
+		if (LOAD_3FIELDS(vout)) {
+			ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_P);
+			ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_N);
+		}
+		if (!ipu_can_rotate_in_place(vout->rotate))
+			ipu_uninit_channel(MEM_ROT_VF_MEM);
+	}
+
+	vout->ready_q.head = vout->ready_q.tail = 0;
+	vout->done_q.head = vout->done_q.tail = 0;
+	for (i = 0; i < vout->buffer_cnt; i++) {
+		vout->v4l2_bufs[i].flags = 0;
+		vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+		vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+	}
+
+	vout->post_proc_ch = CHAN_NONE;
+	vout->state = STATE_STREAM_OFF;
+
+	return retval;
+}
+
+/*
+ * Valid whether the palette is supported
+ *
+ * @param palette  V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
+ *
+ * @return 1 if supported, 0 if failed
+ */
+static inline int valid_mode(u32 palette)
+{
+	return ((palette == V4L2_PIX_FMT_RGB565) ||
+		(palette == V4L2_PIX_FMT_BGR24) ||
+		(palette == V4L2_PIX_FMT_RGB24) ||
+		(palette == V4L2_PIX_FMT_BGR32) ||
+		(palette == V4L2_PIX_FMT_RGB32) ||
+		(palette == V4L2_PIX_FMT_NV12) ||
+		(palette == V4L2_PIX_FMT_UYVY) ||
+		(palette == V4L2_PIX_FMT_YUYV) ||
+		(palette == V4L2_PIX_FMT_YUV422P) ||
+		(palette == V4L2_PIX_FMT_YUV420));
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_g_fmt(vout_data * vout, struct v4l2_format *f)
+{
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		return -EINVAL;
+	}
+	*f = vout->v2f;
+	return 0;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_FMT Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param v4l2_format structure v4l2_format *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_v4l2out_s_fmt(vout_data * vout, struct v4l2_format *f)
+{
+	int retval = 0;
+	u32 size = 0;
+	u32 bytesperline;
+
+	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		retval = -EINVAL;
+		goto err0;
+	}
+	if (!valid_mode(f->fmt.pix.pixelformat)) {
+		dev_err(&vout->video_dev->dev, "pixel format not supported\n");
+		retval = -EINVAL;
+		goto err0;
+	}
+
+	bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) /
+	    8;
+	if (f->fmt.pix.bytesperline < bytesperline) {
+		f->fmt.pix.bytesperline = bytesperline;
+	} else {
+		bytesperline = f->fmt.pix.bytesperline;
+	}
+	vout->bytesperline = bytesperline;
+
+	/* Based on http://v4l2spec.bytesex.org/spec/x6386.htm#V4L2-FIELD */
+	vout->field_fmt = f->fmt.pix.field;
+	switch (vout->field_fmt) {
+		/* Images are in progressive format, not interlaced */
+	case V4L2_FIELD_NONE:
+		break;
+		/* The two fields of a frame are passed in separate buffers,
+		   in temporal order, i. e. the older one first. */
+	case V4L2_FIELD_ALTERNATE:
+		dev_err(&vout->video_dev->dev,
+			"V4L2_FIELD_ALTERNATE field format not supported yet!\n");
+		break;
+	case V4L2_FIELD_INTERLACED_TB:
+		if (cpu_is_mx51() || cpu_is_mx53())
+			break;
+		dev_err(&vout->video_dev->dev,
+			"De-interlacing not supported in this device!\n");
+		vout->field_fmt = V4L2_FIELD_NONE;
+	case V4L2_FIELD_INTERLACED_BT:
+		dev_err(&vout->video_dev->dev,
+			"V4L2_FIELD_INTERLACED_BT field format not supported yet!\n");
+	default:
+		vout->field_fmt = V4L2_FIELD_NONE;
+		break;
+	}
+
+	switch (f->fmt.pix.pixelformat) {
+	case V4L2_PIX_FMT_YUV422P:
+		/* byteperline for YUV planar formats is for
+		   Y plane only */
+		size = bytesperline * f->fmt.pix.height * 2;
+		break;
+	case V4L2_PIX_FMT_YUV420:
+	case V4L2_PIX_FMT_NV12:
+		size = (bytesperline * f->fmt.pix.height * 3) / 2;
+		break;
+	default:
+		size = bytesperline * f->fmt.pix.height;
+		break;
+	}
+
+	/* Return the actual size of the image to the app */
+	if (f->fmt.pix.sizeimage < size) {
+		f->fmt.pix.sizeimage = size;
+	} else {
+		size = f->fmt.pix.sizeimage;
+	}
+
+	vout->v2f.fmt.pix = f->fmt.pix;
+	if (vout->v2f.fmt.pix.priv != 0) {
+		if (copy_from_user(&vout->offset,
+				   (void *)vout->v2f.fmt.pix.priv,
+				   sizeof(vout->offset))) {
+			retval = -EFAULT;
+			goto err0;
+		}
+	} else {
+		vout->offset.u_offset = 0;
+		vout->offset.v_offset = 0;
+	}
+
+	retval = 0;
+      err0:
+	return retval;
+}
+
+/*
+ * V4L2 - Handles VIDIOC_G_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_get_v42lout_control(vout_data * vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0;
+	case V4L2_CID_VFLIP:
+		return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0;
+	case (V4L2_CID_PRIVATE_BASE + 1):
+		return vout->rotate;
+	default:
+		return -EINVAL;
+	}
+}
+
+/*
+ * V4L2 - Handles VIDIOC_S_CTRL Ioctl
+ *
+ * @param vout         structure vout_data *
+ *
+ * @param c           structure v4l2_control *
+ *
+ * @return  status    0 success, EINVAL failed
+ */
+static int mxc_set_v42lout_control(vout_data * vout, struct v4l2_control *c)
+{
+	switch (c->id) {
+	case V4L2_CID_HFLIP:
+		vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP :
+		    IPU_ROTATE_NONE;
+		break;
+	case V4L2_CID_VFLIP:
+		vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP :
+		    IPU_ROTATE_NONE;
+		break;
+	case V4L2_CID_MXC_ROT:
+		vout->rotate = c->value;
+		break;
+	case V4L2_CID_MXC_MOTION:
+		vout->motion_sel = c->value;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * V4L2 interface - open function
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *                    ENODEV timeout, ERESTARTSYS interrupted by user
+ */
+static int mxc_v4l2out_open(struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+	int err;
+
+	if (!vout) {
+		return -ENODEV;
+	}
+
+	down(&vout->busy_lock);
+
+	err = -EINTR;
+	if (signal_pending(current))
+		goto oops;
+
+
+	if (vout->open_count++ == 0) {
+		init_waitqueue_head(&vout->v4l_bufq);
+
+		init_timer(&vout->output_timer);
+		vout->output_timer.function = mxc_v4l2out_timer_handler;
+		vout->output_timer.data = (unsigned long)vout;
+
+		vout->state = STATE_STREAM_OFF;
+		vout->rotate = IPU_ROTATE_NONE;
+
+		vout->v4l_wq = create_singlethread_workqueue("v4l2q");
+		if (!vout->v4l_wq) {
+			dev_dbg(&dev->dev,
+					"Could not create work queue\n");
+			err = -ENOMEM;
+			goto oops;
+		}
+
+		INIT_WORK(&vout->timer_work, timer_work_func);
+	}
+
+	file->private_data = dev;
+
+	up(&vout->busy_lock);
+
+	return 0;
+
+      oops:
+	up(&vout->busy_lock);
+	return err;
+}
+
+/*!
+ * V4L2 interface - close function
+ *
+ * @param file     struct file *
+ *
+ * @return         0 success
+ */
+static int mxc_v4l2out_close(struct file *file)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+
+	if (--vout->open_count == 0) {
+		if (vout->state != STATE_STREAM_OFF)
+			mxc_v4l2out_streamoff(vout);
+
+		file->private_data = NULL;
+
+		mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr,
+				 vout->buffer_cnt, vout->queue_buf_size);
+		vout->buffer_cnt = 0;
+		mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2,
+				 vout->display_buf_size);
+
+		/* capture off */
+		wake_up_interruptible(&vout->v4l_bufq);
+
+		flush_workqueue(vout->v4l_wq);
+		destroy_workqueue(vout->v4l_wq);
+	}
+
+	return 0;
+}
+
+/*!
+ * V4L2 interface - ioctl function
+ *
+ * @param file       struct file *
+ *
+ * @param ioctlnr    unsigned int
+ *
+ * @param arg        void *
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static long
+mxc_v4l2out_do_ioctl(struct file *file,
+		     unsigned int ioctlnr, void *arg)
+{
+	struct video_device *vdev = file->private_data;
+	vout_data *vout = video_get_drvdata(vdev);
+	int retval = 0;
+	int i = 0;
+
+	if (!vout)
+		return -EBADF;
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EBUSY;
+
+	switch (ioctlnr) {
+	case VIDIOC_QUERYCAP:
+		{
+			struct v4l2_capability *cap = arg;
+			strcpy(cap->driver, "mxc_v4l2_output");
+			cap->version = 0;
+			cap->capabilities =
+			    V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
+			cap->card[0] = '\0';
+			cap->bus_info[0] = '\0';
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_FMT:
+		{
+			struct v4l2_format *gf = arg;
+			retval = mxc_v4l2out_g_fmt(vout, gf);
+			break;
+		}
+	case VIDIOC_S_FMT:
+		{
+			struct v4l2_format *sf = arg;
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+			retval = mxc_v4l2out_s_fmt(vout, sf);
+			break;
+		}
+	case VIDIOC_REQBUFS:
+		{
+			struct v4l2_requestbuffers *req = arg;
+			if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (req->memory != V4L2_MEMORY_MMAP)) {
+				dev_dbg(&vdev->dev,
+					"VIDIOC_REQBUFS: incorrect buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			if (req->count == 0)
+				mxc_v4l2out_streamoff(vout);
+
+			if (vout->state == STATE_STREAM_OFF) {
+				if (vout->queue_buf_paddr[0] != 0) {
+					mxc_free_buffers(vout->queue_buf_paddr,
+							 vout->queue_buf_vaddr,
+							 vout->buffer_cnt,
+							 vout->queue_buf_size);
+					dev_dbg(&vdev->dev,
+						"VIDIOC_REQBUFS: freed buffers\n");
+				}
+				vout->buffer_cnt = 0;
+			} else {
+				dev_dbg(&vdev->dev,
+					"VIDIOC_REQBUFS: Buffer is in use\n");
+				retval = -EBUSY;
+				break;
+			}
+
+			if (req->count == 0)
+				break;
+
+			if (req->count < MIN_FRAME_NUM) {
+				req->count = MIN_FRAME_NUM;
+			} else if (req->count > MAX_FRAME_NUM) {
+				req->count = MAX_FRAME_NUM;
+			}
+			vout->buffer_cnt = req->count;
+			vout->queue_buf_size =
+			    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+
+			retval = mxc_allocate_buffers(vout->queue_buf_paddr,
+						      vout->queue_buf_vaddr,
+						      vout->buffer_cnt,
+						      vout->queue_buf_size);
+			if (retval < 0)
+				break;
+
+			/* Init buffer queues */
+			vout->done_q.head = 0;
+			vout->done_q.tail = 0;
+			vout->ready_q.head = 0;
+			vout->ready_q.tail = 0;
+
+			for (i = 0; i < vout->buffer_cnt; i++) {
+				memset(&(vout->v4l2_bufs[i]), 0,
+				       sizeof(vout->v4l2_bufs[i]));
+				vout->v4l2_bufs[i].flags = 0;
+				vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP;
+				vout->v4l2_bufs[i].index = i;
+				vout->v4l2_bufs[i].type =
+				    V4L2_BUF_TYPE_VIDEO_OUTPUT;
+				vout->v4l2_bufs[i].length =
+				    PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage);
+				vout->v4l2_bufs[i].m.offset =
+				    (unsigned long)vout->queue_buf_paddr[i];
+				vout->v4l2_bufs[i].timestamp.tv_sec = 0;
+				vout->v4l2_bufs[i].timestamp.tv_usec = 0;
+			}
+			break;
+		}
+	case VIDIOC_QUERYBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			u32 type = buf->type;
+			int index = buf->index;
+
+			if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt)) {
+				dev_dbg(&vdev->dev,
+					"VIDIOC_QUERYBUFS: incorrect buffer type\n");
+				retval = -EINVAL;
+				break;
+			}
+			down(&vout->param_lock);
+			memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf));
+			up(&vout->param_lock);
+			break;
+		}
+	case VIDIOC_QBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int index = buf->index;
+			unsigned long lock_flags;
+			int param[5][3];
+
+			if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) ||
+			    (index >= vout->buffer_cnt)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			dev_dbg(&vdev->dev, "VIDIOC_QBUF: %d field = %d\n", buf->index, buf->field);
+
+			/* mmapped buffers are L1 WB cached,
+			 * so we need to clean them */
+			if (buf->memory & V4L2_MEMORY_MMAP) {
+				flush_cache_all();
+			}
+
+			spin_lock_irqsave(&g_lock, lock_flags);
+
+			memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf));
+			vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED;
+
+			g_buf_q_cnt++;
+			if (vout->v4l2_bufs[index].reserved)
+				if (!copy_from_user(&param[0][0],
+						    (void *)vout->
+						    v4l2_bufs[index]
+						    .reserved, sizeof(param)))
+					ipu_set_csc_coefficients(vout->
+								 display_ch,
+								 param);
+			queue_buf(&vout->ready_q, index);
+			if (vout->state == STATE_STREAM_PAUSED) {
+				index = peek_next_buf(&vout->ready_q);
+				setup_next_buf_timer(vout, index);
+				vout->state = STATE_STREAM_ON;
+			}
+
+			spin_unlock_irqrestore(&g_lock, lock_flags);
+			break;
+		}
+	case VIDIOC_DQBUF:
+		{
+			struct v4l2_buffer *buf = arg;
+			int idx;
+
+			if ((queue_size(&vout->done_q) == 0) &&
+			    (file->f_flags & O_NONBLOCK)) {
+				retval = -EAGAIN;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout(vout->v4l_bufq,
+							      queue_size(&vout->
+									 done_q)
+							      != 0, 10 * HZ)) {
+				dev_dbg(&vdev->dev, "VIDIOC_DQBUF: timeout\n");
+				retval = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				dev_dbg(&vdev->dev,
+					"VIDIOC_DQBUF: interrupt received\n");
+				retval = -ERESTARTSYS;
+				break;
+			}
+			idx = dequeue_buf(&vout->done_q);
+			if (idx == -1) {	/* No frame free */
+				dev_dbg(&vdev->dev,
+					"VIDIOC_DQBUF: no free buffers, returning\n");
+				retval = -EAGAIN;
+				break;
+			}
+			if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) ==
+			    0)
+				dev_dbg(&vdev->dev,
+					"VIDIOC_DQBUF: buffer in done q, but not "
+					"flagged as done\n");
+
+			vout->v4l2_bufs[idx].flags = 0;
+			memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf));
+			dev_dbg(&vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index);
+			break;
+		}
+	case VIDIOC_STREAMON:
+		{
+			retval = mxc_v4l2out_streamon(vout);
+			break;
+		}
+	case VIDIOC_STREAMOFF:
+		{
+			retval = mxc_v4l2out_streamoff(vout);
+			break;
+		}
+	case VIDIOC_G_CTRL:
+		{
+			retval = mxc_get_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_S_CTRL:
+		{
+			retval = mxc_set_v42lout_control(vout, arg);
+			break;
+		}
+	case VIDIOC_CROPCAP:
+		{
+			struct v4l2_cropcap *cap = arg;
+
+			if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+
+			cap->bounds = vout->crop_bounds[vout->cur_disp_output];
+			cap->defrect = vout->crop_bounds[vout->cur_disp_output];
+			retval = 0;
+			break;
+		}
+	case VIDIOC_G_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			crop->c = vout->crop_current;
+			break;
+		}
+	case VIDIOC_S_CROP:
+		{
+			struct v4l2_crop *crop = arg;
+			struct v4l2_rect *b =
+			    &(vout->crop_bounds[vout->cur_disp_output]);
+
+			if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.height < 0) {
+				retval = -EINVAL;
+				break;
+			}
+			if (crop->c.width < 0) {
+				retval = -EINVAL;
+				break;
+			}
+
+			/* only full screen supported for SDC BG and SDC DC */
+			if (vout->cur_disp_output == 4) {
+				crop->c = vout->crop_current;
+				break;
+			}
+
+			if (crop->c.top < b->top)
+				crop->c.top = b->top;
+			if (crop->c.top >= b->top + b->height)
+				crop->c.top = b->top + b->height - 1;
+			if (crop->c.height > b->top - crop->c.top + b->height)
+				crop->c.height =
+				    b->top - crop->c.top + b->height;
+
+			if (crop->c.left < b->left)
+				crop->c.left = b->left;
+			if (crop->c.left >= b->left + b->width)
+				crop->c.left = b->left + b->width - 1;
+			if (crop->c.width > b->left - crop->c.left + b->width)
+				crop->c.width =
+				    b->left - crop->c.left + b->width;
+
+			/* stride line limitation */
+			crop->c.height -= crop->c.height % 8;
+			crop->c.width -= crop->c.width % 8;
+
+			vout->crop_current = crop->c;
+			break;
+		}
+	case VIDIOC_ENUMOUTPUT:
+		{
+			struct v4l2_output *output = arg;
+
+			if ((output->index >= 5) ||
+			    (vout->output_enabled[output->index] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (output->index >= 3)
+				*output = mxc_outputs[MXC_V4L2_OUT_2_SDC];
+			break;
+		}
+	case VIDIOC_G_OUTPUT:
+		{
+			int *p_output_num = arg;
+
+			*p_output_num = vout->cur_disp_output;
+			break;
+		}
+	case VIDIOC_S_OUTPUT:
+		{
+			int *p_output_num = arg;
+			int fbnum;
+			struct v4l2_rect *b;
+
+			if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) ||
+			    (vout->output_enabled[*p_output_num] == false)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (vout->state != STATE_STREAM_OFF) {
+				retval = -EBUSY;
+				break;
+			}
+
+			vout->cur_disp_output = *p_output_num;
+
+			/* Update bounds in case they have changed */
+			b = &vout->crop_bounds[vout->cur_disp_output];
+
+			fbnum = vout->output_fb_num[vout->cur_disp_output];
+
+			/*
+			 * For FG overlay, it uses BG window parameter as
+			 * limitation reference; and BG must be enabled to
+			 * support FG.
+			 */
+			if (vout->cur_disp_output == 3) {
+				unsigned int i, ipu_ch = CHAN_NONE;
+				struct fb_info *fbi;
+				mm_segment_t old_fs;
+
+				for (i = 0; i < num_registered_fb; i++) {
+					fbi = registered_fb[i];
+					if (fbi->fbops->fb_ioctl) {
+						old_fs = get_fs();
+						set_fs(KERNEL_DS);
+						fbi->fbops->fb_ioctl(fbi,
+							MXCFB_GET_FB_IPU_CHAN,
+							(unsigned long)&ipu_ch);
+						set_fs(old_fs);
+					}
+					if (ipu_ch == CHAN_NONE) {
+						dev_err(&vdev->dev,
+						"Can't get disp ipu channel\n");
+						retval = -EINVAL;
+						break;
+					}
+
+					if (ipu_ch == MEM_BG_SYNC) {
+						fbnum = i;
+						break;
+					}
+				}
+			}
+
+			b->width = registered_fb[fbnum]->var.xres;
+			b->height = registered_fb[fbnum]->var.yres;
+
+			vout->crop_current = *b;
+			break;
+		}
+	case VIDIOC_ENUM_FMT:
+	case VIDIOC_TRY_FMT:
+	case VIDIOC_QUERYCTRL:
+	case VIDIOC_G_PARM:
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_STD:
+	case VIDIOC_S_STD:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQUENCY:
+	case VIDIOC_S_FREQUENCY:
+	default:
+		retval = -EINVAL;
+		break;
+	}
+
+	up(&vout->busy_lock);
+	return retval;
+}
+
+/*
+ * V4L2 interface - ioctl function
+ *
+ * @return  None
+ */
+static long
+mxc_v4l2out_ioctl(struct file *file,
+		  unsigned int cmd, unsigned long arg)
+{
+	return video_usercopy(file, cmd, arg, mxc_v4l2out_do_ioctl);
+}
+
+/*!
+ * V4L2 interface - mmap function
+ *
+ * @param file          structure file *
+ *
+ * @param vma           structure vm_area_struct *
+ *
+ * @return status       0 Success, EINTR busy lock error,
+ *                      ENOBUFS remap_page error
+ */
+static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct video_device *vdev = video_devdata(file);
+	unsigned long size = vma->vm_end - vma->vm_start;
+	int res = 0;
+	int i;
+	vout_data *vout = video_get_drvdata(vdev);
+
+	dev_dbg(&vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	for (i = 0; i < vout->buffer_cnt; i++) {
+		if ((vout->v4l2_bufs[i].m.offset ==
+		     (vma->vm_pgoff << PAGE_SHIFT)) &&
+		    (vout->v4l2_bufs[i].length >= size)) {
+			vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED;
+			break;
+		}
+	}
+	if (i == vout->buffer_cnt) {
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	/* make buffers inner write-back, outer write-thru cacheable */
+	/* vma->vm_page_prot = pgprot_outer_wrthru(vma->vm_page_prot);*/
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		dev_dbg(&vdev->dev, "mmap remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mxc_mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+      mxc_mmap_exit:
+	up(&vout->busy_lock);
+	return res;
+}
+
+/*!
+ * V4L2 interface - poll function
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table_struct *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_v4l2out_poll(struct file *file, struct poll_table_struct * wait)
+{
+	struct video_device *dev = video_devdata(file);
+	vout_data *vout = video_get_drvdata(dev);
+
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	if (down_interruptible(&vout->busy_lock))
+		return -EINTR;
+
+	queue = &vout->v4l_bufq;
+	poll_wait(file, queue, wait);
+
+	up(&vout->busy_lock);
+	return res;
+}
+
+static struct
+v4l2_file_operations mxc_v4l2out_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_v4l2out_open,
+	.release = mxc_v4l2out_close,
+	.ioctl = mxc_v4l2out_ioctl,
+	.mmap = mxc_v4l2out_mmap,
+	.poll = mxc_v4l2out_poll,
+};
+
+static struct video_device mxc_v4l2out_template = {
+	.name = "MXC Video Output",
+	.vfl_type = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING,
+	.fops = &mxc_v4l2out_fops,
+	.release = video_device_release,
+};
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxc_v4l2out_probe(struct platform_device *pdev)
+{
+	int i;
+	vout_data *vout;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	vout = kmalloc(sizeof(vout_data), GFP_KERNEL);
+
+	if (!vout)
+		return 0;
+
+	memset(vout, 0, sizeof(vout_data));
+
+	vout->video_dev = video_device_alloc();
+	if (vout->video_dev == NULL)
+		return -1;
+	vout->video_dev->minor = -1;
+
+	*(vout->video_dev) = mxc_v4l2out_template;
+
+	/* register v4l device */
+	if (video_register_device(vout->video_dev,
+				  VFL_TYPE_GRABBER, video_nr) == -1) {
+		dev_dbg(&pdev->dev, "video_register_device failed\n");
+		return 0;
+	}
+	dev_info(&pdev->dev, "Registered device video%d\n",
+		 vout->video_dev->minor & 0x1f);
+	/*vout->video_dev->dev = &pdev->dev;*/
+
+	video_set_drvdata(vout->video_dev, vout);
+
+	init_MUTEX(&vout->param_lock);
+	init_MUTEX(&vout->busy_lock);
+
+	/* setup outputs and cropping */
+	vout->cur_disp_output = -1;
+	for (i = 0; i < num_registered_fb; i++) {
+		char *idstr = registered_fb[i]->fix.id;
+		if (strncmp(idstr, "DISP", 4) == 0) {
+			int disp_num = idstr[4] - '0';
+			if (disp_num == 3) {
+				if (strcmp(idstr, "DISP3 BG - DI1") == 0)
+					disp_num = 5;
+				else if (strncmp(idstr, "DISP3 BG", 8) == 0)
+					disp_num = 4;
+			}
+			vout->crop_bounds[disp_num].left = 0;
+			vout->crop_bounds[disp_num].top = 0;
+			vout->crop_bounds[disp_num].width =
+			    registered_fb[i]->var.xres;
+			vout->crop_bounds[disp_num].height =
+			    registered_fb[i]->var.yres;
+			vout->output_enabled[disp_num] = true;
+			vout->output_fb_num[disp_num] = i;
+			if (vout->cur_disp_output == -1) {
+				vout->cur_disp_output = disp_num;
+			}
+		}
+
+	}
+	vout->crop_current = vout->crop_bounds[vout->cur_disp_output];
+
+	platform_set_drvdata(pdev, vout);
+
+	return 0;
+}
+
+static int mxc_v4l2out_remove(struct platform_device *pdev)
+{
+	vout_data *vout = platform_get_drvdata(pdev);
+
+	if (vout->video_dev) {
+		video_unregister_device(vout->video_dev);
+		vout->video_dev = NULL;
+	}
+
+	platform_set_drvdata(pdev, NULL);
+
+	kfree(vout);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_v4l2out_driver = {
+	.driver = {
+		   .name = "mxc_v4l2_output",
+		   },
+	.probe = mxc_v4l2out_probe,
+	.remove = mxc_v4l2out_remove,
+};
+
+/*!
+ * mxc v4l2 init function
+ *
+ */
+static int mxc_v4l2out_init(void)
+{
+	return platform_driver_register(&mxc_v4l2out_driver);
+}
+
+/*!
+ * mxc v4l2 cleanup function
+ *
+ */
+static void mxc_v4l2out_clean(void)
+{
+	platform_driver_unregister(&mxc_v4l2out_driver);
+}
+
+module_init(mxc_v4l2out_init);
+module_exit(mxc_v4l2out_clean);
+
+module_param(video_nr, int, 0444);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2-driver for MXC video output");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("video");
diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.h b/drivers/media/video/mxc/output/mxc_v4l2_output.h
new file mode 100644
index 000000000000..096dc3b17a06
--- /dev/null
+++ b/drivers/media/video/mxc/output/mxc_v4l2_output.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup MXC_V4L2_OUTPUT MXC V4L2 Video Output Driver
+ */
+/*!
+ * @file mxc_v4l2_output.h
+ *
+ * @brief MXC V4L2 Video Output Driver Header file
+ *
+ * Video4Linux2 Output Device using MXC IPU Post-processing functionality.
+ *
+ * @ingroup MXC_V4L2_OUTPUT
+ */
+#ifndef __MXC_V4L2_OUTPUT_H__
+#define __MXC_V4L2_OUTPUT_H__
+
+#include <media/v4l2-dev.h>
+
+#ifdef __KERNEL__
+
+#include <linux/ipu.h>
+#include <linux/mxc_v4l2.h>
+#include <linux/videodev2.h>
+
+#define MIN_FRAME_NUM 2
+#define MAX_FRAME_NUM 30
+
+#define MXC_V4L2_OUT_NUM_OUTPUTS        6
+#define MXC_V4L2_OUT_2_SDC              0
+
+
+typedef struct {
+	int list[MAX_FRAME_NUM + 1];
+	int head;
+	int tail;
+} v4l_queue;
+
+/*!
+ * States for the video stream
+ */
+typedef enum {
+	STATE_STREAM_OFF,
+	STATE_STREAM_ON,
+	STATE_STREAM_PAUSED,
+	STATE_STREAM_STOPPING,
+} v4lout_state;
+
+/*!
+ * common v4l2 driver structure.
+ */
+typedef struct _vout_data {
+	struct video_device *video_dev;
+	/*!
+	 * semaphore guard against SMP multithreading
+	 */
+	struct semaphore busy_lock;
+
+	/*!
+	 * number of process that have device open
+	 */
+	int open_count;
+
+	/*!
+	 * params lock for this camera
+	 */
+	struct semaphore param_lock;
+
+	struct timer_list output_timer;
+	struct workqueue_struct *v4l_wq;
+	struct work_struct timer_work;
+	unsigned long start_jiffies;
+	u32 frame_count;
+
+	v4l_queue ready_q;
+	v4l_queue done_q;
+
+	s8 next_rdy_ipu_buf;
+	s8 next_done_ipu_buf;
+	s8 ipu_buf[2];
+	s8 ipu_buf_p[2];
+	s8 ipu_buf_n[2];
+	volatile v4lout_state state;
+
+	int cur_disp_output;
+	int output_fb_num[MXC_V4L2_OUT_NUM_OUTPUTS];
+	int output_enabled[MXC_V4L2_OUT_NUM_OUTPUTS];
+	struct v4l2_framebuffer v4l2_fb;
+	int ic_bypass;
+	u32 work_irq;
+	ipu_channel_t display_ch;
+	ipu_channel_t post_proc_ch;
+	ipu_channel_t display_input_ch;
+
+	/*!
+	 * FRAME_NUM-buffering, so we need a array
+	 */
+	int buffer_cnt;
+	dma_addr_t queue_buf_paddr[MAX_FRAME_NUM];
+	void *queue_buf_vaddr[MAX_FRAME_NUM];
+	u32 queue_buf_size;
+	struct v4l2_buffer v4l2_bufs[MAX_FRAME_NUM];
+	u32 display_buf_size;
+	dma_addr_t display_bufs[2];
+	void *display_bufs_vaddr[2];
+	dma_addr_t rot_pp_bufs[2];
+	void *rot_pp_bufs_vaddr[2];
+
+	/*!
+	 * Poll wait queue
+	 */
+	wait_queue_head_t v4l_bufq;
+
+	/*!
+	 * v4l2 format
+	 */
+	struct v4l2_format v2f;
+	struct v4l2_mxc_offset offset;
+	ipu_rotate_mode_t rotate;
+
+	/* crop */
+	struct v4l2_rect crop_bounds[MXC_V4L2_OUT_NUM_OUTPUTS];
+	struct v4l2_rect crop_current;
+	u32 bytesperline;
+	enum v4l2_field field_fmt;
+	ipu_motion_sel motion_sel;
+
+	/* PP split fot two stripes*/
+	int pp_split; /* 0,1 */
+	struct stripe_param pp_left_stripe;
+	struct stripe_param pp_right_stripe; /* struct for split parameters */
+	struct stripe_param pp_up_stripe;
+	struct stripe_param pp_down_stripe;
+	/* IC ouput buffer number. Counting from 0 to 7 */
+	int pp_split_buf_num; /*  0..7 */
+	u16 bpp ; /* bit per pixel */
+	u16 xres; /* width of physical frame (BGs) */
+	u16 yres; /* heigth of physical frame (BGs)*/
+
+} vout_data;
+
+#endif
+#endif				/* __MXC_V4L2_OUTPUT_H__ */
diff --git a/drivers/media/video/mxs_pxp.c b/drivers/media/video/mxs_pxp.c
new file mode 100644
index 000000000000..017d22458a22
--- /dev/null
+++ b/drivers/media/video/mxs_pxp.c
@@ -0,0 +1,1413 @@
+/*
+ * Freescale MXS PxP driver
+ *
+ * Author: Matt Porter <mporter@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+#include <linux/videodev2.h>
+#include <linux/delay.h>
+
+#include <media/videobuf-dma-contig.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-pxp.h>
+
+#include "mxs_pxp.h"
+
+#define	PXP_BASE_ADDR	IO_ADDRESS(PXP_PHYS_ADDR)
+
+#define PXP_DRIVER_NAME			"mxs-pxp"
+#define PXP_DRIVER_MAJOR		1
+#define PXP_DRIVER_MINOR		0
+
+#define PXP_DEF_BUFS			2
+#define PXP_MIN_PIX			8
+
+#define V4L2_OUTPUT_TYPE_INTERNAL	4
+
+#define PXP_WAITCON	((__raw_readl(PXP_BASE_ADDR + HW_PXP_NEXT) & \
+				BM_PXP_NEXT_ENABLED) != BM_PXP_NEXT_ENABLED)
+
+#define REG_OFFSET	0x10
+#define REGS1_NUMS	16
+#define REGS2_NUMS	5
+#define REGS3_NUMS	32
+static u32 regs1[REGS1_NUMS];
+static u32 regs2[REGS2_NUMS];
+static u32 regs3[REGS3_NUMS];
+
+static struct pxp_data_format pxp_s0_formats[] = {
+	{
+	 .name = "24-bit RGB",
+	 .bpp = 4,
+	 .fourcc = V4L2_PIX_FMT_RGB24,
+	 .colorspace = V4L2_COLORSPACE_SRGB,
+	 .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB888,
+	 },
+	{
+	 .name = "16-bit RGB 5:6:5",
+	 .bpp = 2,
+	 .fourcc = V4L2_PIX_FMT_RGB565,
+	 .colorspace = V4L2_COLORSPACE_SRGB,
+	 .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB565,
+	 },
+	{
+	 .name = "16-bit RGB 5:5:5",
+	 .bpp = 2,
+	 .fourcc = V4L2_PIX_FMT_RGB555,
+	 .colorspace = V4L2_COLORSPACE_SRGB,
+	 .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB555,
+	 },
+	{
+	 .name = "YUV 4:2:0 Planar",
+	 .bpp = 2,
+	 .fourcc = V4L2_PIX_FMT_YUV420,
+	 .colorspace = V4L2_COLORSPACE_JPEG,
+	 .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV420,
+	 },
+	{
+	 .name = "YUV 4:2:2 Planar",
+	 .bpp = 2,
+	 .fourcc = V4L2_PIX_FMT_YUV422P,
+	 .colorspace = V4L2_COLORSPACE_JPEG,
+	 .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV422,
+	 },
+};
+
+struct v4l2_queryctrl pxp_controls[] = {
+	{
+	 .id = V4L2_CID_HFLIP,
+	 .type = V4L2_CTRL_TYPE_BOOLEAN,
+	 .name = "Horizontal Flip",
+	 .minimum = 0,
+	 .maximum = 1,
+	 .step = 1,
+	 .default_value = 0,
+	 .flags = 0,
+	 },
+	{
+	 .id = V4L2_CID_VFLIP,
+	 .type = V4L2_CTRL_TYPE_BOOLEAN,
+	 .name = "Vertical Flip",
+	 .minimum = 0,
+	 .maximum = 1,
+	 .step = 1,
+	 .default_value = 0,
+	 .flags = 0,
+	 },
+	{
+	 .id = V4L2_CID_PRIVATE_BASE,
+	 .type = V4L2_CTRL_TYPE_INTEGER,
+	 .name = "Rotation",
+	 .minimum = 0,
+	 .maximum = 270,
+	 .step = 90,
+	 .default_value = 0,
+	 .flags = 0,
+	 },
+	{
+	 .id = V4L2_CID_PRIVATE_BASE + 1,
+	 .name = "Background Color",
+	 .minimum = 0,
+	 .maximum = 0xFFFFFF,
+	 .step = 1,
+	 .default_value = 0,
+	 .flags = 0,
+	 .type = V4L2_CTRL_TYPE_INTEGER,
+	 },
+	{
+	 .id = V4L2_CID_PRIVATE_BASE + 2,
+	 .name = "Set S0 Chromakey",
+	 .minimum = -1,
+	 .maximum = 0xFFFFFF,
+	 .step = 1,
+	 .default_value = -1,
+	 .flags = 0,
+	 .type = V4L2_CTRL_TYPE_INTEGER,
+	 },
+	{
+	 .id = V4L2_CID_PRIVATE_BASE + 3,
+	 .name = "YUV Colorspace",
+	 .minimum = 0,
+	 .maximum = 1,
+	 .step = 1,
+	 .default_value = 0,
+	 .flags = 0,
+	 .type = V4L2_CTRL_TYPE_BOOLEAN,
+	 },
+};
+
+static void pxp_set_ctrl(struct pxps *pxp)
+{
+	u32 ctrl;
+
+	ctrl = BF_PXP_CTRL_S0_FORMAT(pxp->s0_fmt->ctrl_s0_fmt);
+	ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(BV_PXP_CTRL_OUTBUF_FORMAT__RGB888);
+	ctrl |= BM_PXP_CTRL_CROP;
+
+	if (pxp->scaling)
+		ctrl |= BM_PXP_CTRL_SCALE;
+	if (pxp->vflip)
+		ctrl |= BM_PXP_CTRL_VFLIP;
+	if (pxp->hflip)
+		ctrl |= BM_PXP_CTRL_HFLIP;
+	if (pxp->rotate)
+		ctrl |= BF_PXP_CTRL_ROTATE(pxp->rotate / 90);
+
+	ctrl |= BM_PXP_CTRL_IRQ_ENABLE;
+	if (pxp->active)
+		ctrl |= BM_PXP_CTRL_ENABLE;
+
+	__raw_writel(ctrl, PXP_BASE_ADDR + HW_PXP_CTRL);
+	pxp->regs_virt->ctrl = ctrl;
+}
+
+static void pxp_set_outbuf(struct pxps *pxp)
+{
+	pxp->regs_virt->outbuf = pxp->outb_phys;
+	/* Always equal to the FB size */
+	if (pxp->rotate % 180)
+		pxp->regs_virt->outsize =
+		    BF_PXP_OUTSIZE_WIDTH(pxp->fb.fmt.height) |
+		    BF_PXP_OUTSIZE_HEIGHT(pxp->fb.fmt.width);
+	else
+		pxp->regs_virt->outsize =
+		    BF_PXP_OUTSIZE_WIDTH(pxp->fb.fmt.width) |
+		    BF_PXP_OUTSIZE_HEIGHT(pxp->fb.fmt.height);
+}
+
+static void pxp_set_s0colorkey(struct pxps *pxp)
+{
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (pxp->s0_chromakey == -1) {
+		/* disable color key */
+		pxp->regs_virt->s0colorkeylow = 0xFFFFFF;
+		pxp->regs_virt->s0colorkeyhigh = 0;
+	} else {
+		pxp->regs_virt->s0colorkeylow = pxp->s0_chromakey;
+		pxp->regs_virt->s0colorkeyhigh = pxp->s0_chromakey;
+	}
+}
+
+static void pxp_set_s1colorkey(struct pxps *pxp)
+{
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (pxp->s1_chromakey_state != 0 && pxp->s1_chromakey != -1) {
+		pxp->regs_virt->olcolorkeylow = pxp->s1_chromakey;
+		pxp->regs_virt->olcolorkeyhigh = pxp->s1_chromakey;
+	} else {
+		/* disable color key */
+		pxp->regs_virt->olcolorkeylow = 0xFFFFFF;
+		pxp->regs_virt->olcolorkeyhigh = 0;
+	}
+}
+
+static void pxp_set_oln(struct pxps *pxp)
+{
+	pxp->regs_virt->ol0.ol = (u32) pxp->fb.base;
+	if (pxp->rotate % 180)
+		pxp->regs_virt->ol0.olsize =
+		    BF_PXP_OLnSIZE_WIDTH(pxp->fb.fmt.height >> 3) |
+		    BF_PXP_OLnSIZE_HEIGHT(pxp->fb.fmt.width >> 3);
+	else
+		pxp->regs_virt->ol0.olsize =
+		    BF_PXP_OLnSIZE_WIDTH(pxp->fb.fmt.width >> 3) |
+		    BF_PXP_OLnSIZE_HEIGHT(pxp->fb.fmt.height >> 3);
+}
+
+static void pxp_set_olparam(struct pxps *pxp)
+{
+	u32 olparam;
+	struct v4l2_pix_format *fmt = &pxp->fb.fmt;
+
+	olparam = BF_PXP_OLnPARAM_ALPHA(pxp->global_alpha);
+	if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888);
+	else
+		olparam |=
+		    BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565);
+	if (pxp->global_alpha_state)
+		olparam |=
+		    BF_PXP_OLnPARAM_ALPHA_CNTL
+		    (BV_PXP_OLnPARAM_ALPHA_CNTL__Override);
+	if (pxp->s1_chromakey_state)
+		olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY;
+	if (pxp->overlay_state)
+		olparam |= BM_PXP_OLnPARAM_ENABLE;
+
+	pxp->regs_virt->ol0.olparam = olparam;
+}
+
+static void pxp_set_s0param(struct pxps *pxp)
+{
+	u32 s0param;
+
+	s0param = BF_PXP_S0PARAM_XBASE(pxp->drect.left >> 3);
+	s0param |= BF_PXP_S0PARAM_YBASE(pxp->drect.top >> 3);
+	s0param |= BF_PXP_S0PARAM_WIDTH(pxp->s0_width >> 3);
+	s0param |= BF_PXP_S0PARAM_HEIGHT(pxp->s0_height >> 3);
+	pxp->regs_virt->s0param = s0param;
+}
+
+static void pxp_set_s0crop(struct pxps *pxp)
+{
+	u32 s0crop;
+
+	s0crop = BF_PXP_S0CROP_XBASE(pxp->srect.left >> 3);
+	s0crop |= BF_PXP_S0CROP_YBASE(pxp->srect.top >> 3);
+	s0crop |= BF_PXP_S0CROP_WIDTH(pxp->drect.width >> 3);
+	s0crop |= BF_PXP_S0CROP_HEIGHT(pxp->drect.height >> 3);
+	pxp->regs_virt->s0crop = s0crop;
+}
+
+static int pxp_set_scaling(struct pxps *pxp)
+{
+	int ret = 0;
+	u32 xscale, yscale, s0scale;
+
+	if ((pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV420) &&
+	    (pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV422P)) {
+		pxp->scaling = 0;
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if ((pxp->srect.width == pxp->drect.width) &&
+	    (pxp->srect.height == pxp->drect.height)) {
+		pxp->regs_virt->s0scale = 0x10001000;
+		pxp->scaling = 0;
+		goto out;
+	}
+
+	pxp->scaling = 1;
+	xscale = pxp->srect.width * 0x1000 / pxp->drect.width;
+	yscale = pxp->srect.height * 0x1000 / pxp->drect.height;
+	if (xscale > PXP_DOWNSCALE_THRESHOLD)
+		xscale = PXP_DOWNSCALE_THRESHOLD;
+	if (yscale > PXP_DOWNSCALE_THRESHOLD)
+		yscale = PXP_DOWNSCALE_THRESHOLD;
+	s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale);
+	pxp->regs_virt->s0scale = s0scale;
+
+out:
+	pxp_set_ctrl(pxp);
+
+	return ret;
+}
+
+static int pxp_set_fbinfo(struct pxps *pxp)
+{
+	struct fb_var_screeninfo var;
+	struct fb_fix_screeninfo fix;
+	struct v4l2_framebuffer *fb = &pxp->fb;
+	int err;
+
+	err = mxsfb_get_info(&var, &fix);
+
+	fb->fmt.width = var.xres;
+	fb->fmt.height = var.yres;
+	if (var.bits_per_pixel == 16)
+		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565;
+	else
+		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24;
+	fb->base = (void *)fix.smem_start;
+	return err;
+}
+
+static void pxp_set_s0bg(struct pxps *pxp)
+{
+	pxp->regs_virt->s0background = pxp->s0_bgcolor;
+}
+
+static void pxp_set_csc(struct pxps *pxp)
+{
+	if (pxp->yuv) {
+		/* YUV colorspace */
+		__raw_writel(0x04030000, PXP_BASE_ADDR + HW_PXP_CSCCOEFF0);
+		__raw_writel(0x01230208, PXP_BASE_ADDR + HW_PXP_CSCCOEFF1);
+		__raw_writel(0x076b079b, PXP_BASE_ADDR + HW_PXP_CSCCOEFF2);
+	} else {
+		/* YCrCb colorspace */
+		__raw_writel(0x84ab01f0, PXP_BASE_ADDR + HW_PXP_CSCCOEFF0);
+		__raw_writel(0x01230204, PXP_BASE_ADDR + HW_PXP_CSCCOEFF1);
+		__raw_writel(0x0730079c, PXP_BASE_ADDR + HW_PXP_CSCCOEFF2);
+	}
+}
+
+static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc)
+{
+
+	if (vc->id == V4L2_CID_HFLIP)
+		pxp->hflip = vc->value;
+	else if (vc->id == V4L2_CID_VFLIP)
+		pxp->vflip = vc->value;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE) {
+		if (vc->value % 90)
+			return -ERANGE;
+		pxp->rotate = vc->value;
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) {
+		pxp->s0_bgcolor = vc->value;
+		pxp_set_s0bg(pxp);
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) {
+		pxp->s0_chromakey = vc->value;
+		pxp_set_s0colorkey(pxp);
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) {
+		pxp->yuv = vc->value;
+		pxp_set_csc(pxp);
+	}
+
+	pxp_set_ctrl(pxp);
+
+	return 0;
+}
+
+static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc)
+{
+	if (vc->id == V4L2_CID_HFLIP)
+		vc->value = pxp->hflip;
+	else if (vc->id == V4L2_CID_VFLIP)
+		vc->value = pxp->vflip;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE)
+		vc->value = pxp->rotate;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 1)
+		vc->value = pxp->s0_bgcolor;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 2)
+		vc->value = pxp->s0_chromakey;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 3)
+		vc->value = pxp->yuv;
+
+	return 0;
+}
+
+static int pxp_enumoutput(struct file *file, void *fh, struct v4l2_output *o)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if ((o->index < 0) || (o->index > 1))
+		return -EINVAL;
+
+	memset(o, 0, sizeof(struct v4l2_output));
+	if (o->index == 0) {
+		strcpy(o->name, "PxP Display Output");
+		pxp->output = 0;
+	} else {
+		strcpy(o->name, "PxP Virtual Output");
+		pxp->output = 1;
+	}
+	o->type = V4L2_OUTPUT_TYPE_INTERNAL;
+	o->std = 0;
+	o->reserved[0] = pxp->outb_phys;
+
+	return 0;
+}
+
+static int pxp_g_output(struct file *file, void *fh, unsigned int *i)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	*i = pxp->output;
+
+	return 0;
+}
+
+static int pxp_s_output(struct file *file, void *fh, unsigned int i)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_pix_format *fmt = &pxp->fb.fmt;
+	int bpp;
+
+	if ((i < 0) || (i > 1))
+		return -EINVAL;
+
+	if (pxp->outb)
+		goto out;
+
+	/* Output buffer is same format as fbdev */
+	if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
+		bpp = 4;
+	else
+		bpp = 2;
+
+	pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL);
+	pxp->outb_phys = virt_to_phys(pxp->outb);
+	dma_map_single(NULL, pxp->outb,
+		       fmt->width * fmt->height * bpp, DMA_TO_DEVICE);
+
+out:
+	pxp_set_outbuf(pxp);
+
+	return 0;
+}
+
+static int pxp_enum_fmt_video_output(struct file *file, void *fh,
+				     struct v4l2_fmtdesc *fmt)
+{
+	enum v4l2_buf_type type = fmt->type;
+	int index = fmt->index;
+
+	if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats)))
+		return -EINVAL;
+
+	memset(fmt, 0, sizeof(struct v4l2_fmtdesc));
+	fmt->index = index;
+	fmt->type = type;
+	fmt->pixelformat = pxp_s0_formats[index].fourcc;
+	strcpy(fmt->description, pxp_s0_formats[index].name);
+
+	return 0;
+}
+
+static int pxp_g_fmt_video_output(struct file *file, void *fh,
+				  struct v4l2_format *f)
+{
+	struct v4l2_pix_format *pf = &f->fmt.pix;
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct pxp_data_format *fmt = pxp->s0_fmt;
+
+	pf->width = pxp->s0_width;
+	pf->height = pxp->s0_height;
+	pf->pixelformat = fmt->fourcc;
+	pf->field = V4L2_FIELD_NONE;
+	pf->bytesperline = fmt->bpp * pf->width;
+	pf->sizeimage = pf->bytesperline * pf->height;
+	pf->colorspace = fmt->colorspace;
+	pf->priv = 0;
+
+	return 0;
+}
+
+static struct pxp_data_format *pxp_get_format(struct v4l2_format *f)
+{
+	struct pxp_data_format *fmt;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) {
+		fmt = &pxp_s0_formats[i];
+		if (fmt->fourcc == f->fmt.pix.pixelformat)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(pxp_s0_formats))
+		return NULL;
+
+	return &pxp_s0_formats[i];
+}
+
+static int pxp_try_fmt_video_output(struct file *file, void *fh,
+				    struct v4l2_format *f)
+{
+	int w = f->fmt.pix.width;
+	int h = f->fmt.pix.height;
+	struct pxp_data_format *fmt = pxp_get_format(f);
+
+	if (!fmt)
+		return -EINVAL;
+
+	w = min(w, 2040);
+	w = max(w, 8);
+	h = min(h, 2040);
+	h = max(h, 8);
+	f->fmt.pix.field = V4L2_FIELD_NONE;
+	f->fmt.pix.width = w;
+	f->fmt.pix.height = h;
+	f->fmt.pix.pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+static int pxp_s_fmt_video_output(struct file *file, void *fh,
+				  struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_pix_format *pf = &f->fmt.pix;
+	int ret = pxp_try_fmt_video_output(file, fh, f);
+
+	if (ret == 0) {
+		pxp->s0_fmt = pxp_get_format(f);
+		pxp->s0_width = pf->width;
+		pxp->s0_height = pf->height;
+		pxp_set_ctrl(pxp);
+		pxp_set_s0param(pxp);
+	}
+
+	return ret;
+}
+
+static int pxp_g_fmt_output_overlay(struct file *file, void *fh,
+				    struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+
+	memset(wf, 0, sizeof(struct v4l2_window));
+	wf->chromakey = pxp->s1_chromakey;
+	wf->global_alpha = pxp->global_alpha;
+	wf->field = V4L2_FIELD_NONE;
+	wf->clips = NULL;
+	wf->clipcount = 0;
+	wf->bitmap = NULL;
+	wf->w.left = pxp->srect.left;
+	wf->w.top = pxp->srect.top;
+	wf->w.width = pxp->srect.width;
+	wf->w.height = pxp->srect.height;
+
+	return 0;
+}
+
+static int pxp_try_fmt_output_overlay(struct file *file, void *fh,
+				      struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+	struct v4l2_rect srect;
+	u32 s1_chromakey = wf->chromakey;
+	u8 global_alpha = wf->global_alpha;
+
+	memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect));
+
+	pxp_g_fmt_output_overlay(file, fh, f);
+
+	wf->chromakey = s1_chromakey;
+	wf->global_alpha = global_alpha;
+
+	/* Constrain parameters to the input buffer */
+	wf->w.left = srect.left;
+	wf->w.top = srect.top;
+	wf->w.width = min(srect.width, ((__s32) pxp->s0_width - wf->w.left));
+	wf->w.height = min(srect.height, ((__s32) pxp->s0_height - wf->w.top));
+
+	return 0;
+}
+
+static int pxp_s_fmt_output_overlay(struct file *file, void *fh,
+				    struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+	int ret = pxp_try_fmt_output_overlay(file, fh, f);
+
+	if (ret == 0) {
+		pxp->srect.left = wf->w.left;
+		pxp->srect.top = wf->w.top;
+		pxp->srect.width = wf->w.width;
+		pxp->srect.height = wf->w.height;
+		pxp->global_alpha = wf->global_alpha;
+		pxp->s1_chromakey = wf->chromakey;
+		pxp_set_s0param(pxp);
+		pxp_set_s0crop(pxp);
+		pxp_set_scaling(pxp);
+		pxp_set_olparam(pxp);
+		pxp_set_s1colorkey(pxp);
+	}
+
+	return ret;
+}
+
+static int pxp_reqbufs(struct file *file, void *priv,
+		       struct v4l2_requestbuffers *r)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_reqbufs(&pxp->s0_vbq, r);
+}
+
+static int pxp_querybuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_querybuf(&pxp->s0_vbq, b);
+}
+
+static int pxp_qbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_qbuf(&pxp->s0_vbq, b);
+}
+
+static int pxp_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK);
+}
+
+static int pxp_streamon(struct file *file, void *priv, enum v4l2_buf_type t)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -EINVAL;
+
+	pxp_set_outbuf(pxp);
+	ret = videobuf_streamon(&pxp->s0_vbq);
+	msleep(20);
+
+	if (!ret && (pxp->output == 0))
+		mxsfb_cfg_pxp(1, pxp->outb_phys);
+
+	return ret;
+}
+
+static int pxp_streamoff(struct file *file, void *priv, enum v4l2_buf_type t)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -EINVAL;
+
+	cancel_work_sync(&pxp->work);
+	ret = videobuf_streamoff(&pxp->s0_vbq);
+	msleep(20);
+
+	if (!ret)
+		mxsfb_cfg_pxp(0, 0);
+
+	return ret;
+}
+
+static int pxp_buf_setup(struct videobuf_queue *q,
+			 unsigned int *count, unsigned *size)
+{
+	struct pxps *pxp = q->priv_data;
+
+	*size = pxp->s0_width * pxp->s0_height * pxp->s0_fmt->bpp;
+
+	if (0 == *count)
+		*count = PXP_DEF_BUFS;
+
+	return 0;
+}
+
+static void pxp_buf_free(struct videobuf_queue *q, struct videobuf_buffer *vb)
+{
+	if (in_interrupt())
+		BUG();
+
+	videobuf_dma_contig_free(q, vb);
+
+	vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int pxp_buf_prepare(struct videobuf_queue *q,
+			   struct videobuf_buffer *vb, enum v4l2_field field)
+{
+	struct pxps *pxp = q->priv_data;
+	int ret = 0;
+
+	vb->width = pxp->s0_width;
+	vb->height = pxp->s0_height;
+	vb->size = vb->width * vb->height * pxp->s0_fmt->bpp;
+	vb->field = V4L2_FIELD_NONE;
+	vb->state = VIDEOBUF_NEEDS_INIT;
+
+	ret = videobuf_iolock(q, vb, NULL);
+	if (ret)
+		goto fail;
+	vb->state = VIDEOBUF_PREPARED;
+
+	return 0;
+
+fail:
+	pxp_buf_free(q, vb);
+	return ret;
+}
+
+static void pxp_buf_next(struct pxps *pxp)
+{
+	dma_addr_t Y, U, V;
+
+	if (pxp->active) {
+		pxp->active->state = VIDEOBUF_ACTIVE;
+		Y = videobuf_to_dma_contig(pxp->active);
+		pxp->regs_virt->s0buf = Y;
+		if ((pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) ||
+		    (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV422P)) {
+			int s = 1;	/* default to YUV 4:2:2 */
+			if (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420)
+				s = 2;
+			U = Y + (pxp->s0_width * pxp->s0_height);
+			V = U + ((pxp->s0_width * pxp->s0_height) >> s);
+			pxp->regs_virt->s0ubuf = U;
+			pxp->regs_virt->s0vbuf = V;
+		}
+		pxp->regs_virt->ctrl =
+		    __raw_readl(PXP_BASE_ADDR +
+				HW_PXP_CTRL) | BM_PXP_CTRL_ENABLE;
+	}
+
+	__raw_writel(pxp->regs_phys, PXP_BASE_ADDR + HW_PXP_NEXT);
+}
+
+static void pxp_next_handle(struct work_struct *w)
+{
+	struct pxps *pxp = container_of(w, struct pxps, work);
+	struct pxp_buffer *buf, *next;
+	unsigned long flags;
+
+	if (pxp->next_queue_ended == 1)
+		return;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	while (!list_empty(&pxp->nextq)) {
+		spin_unlock_irqrestore(&pxp->lock, flags);
+
+		if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON,
+						      5 * HZ)
+		    || signal_pending(current)) {
+			spin_lock_irqsave(&pxp->lock, flags);
+			list_for_each_entry_safe(buf, next, &pxp->nextq, queue)
+			    list_del(&buf->queue);
+			spin_unlock_irqrestore(&pxp->lock, flags);
+			pxp->next_queue_ended = 1;
+			return;
+		}
+
+		spin_lock_irqsave(&pxp->lock, flags);
+		buf = list_entry(pxp->nextq.next, struct pxp_buffer, queue);
+		list_del_init(&buf->queue);
+		pxp->active = &buf->vb;
+		pxp->active->state = VIDEOBUF_QUEUED;
+		pxp_buf_next(pxp);
+	}
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxp_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
+{
+	struct pxps *pxp = q->priv_data;
+	struct pxp_buffer *buf;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	if (list_empty(&pxp->outq)) {
+		list_add_tail(&vb->queue, &pxp->outq);
+		vb->state = VIDEOBUF_QUEUED;
+
+		pxp->active = vb;
+		pxp_buf_next(pxp);
+	} else {
+		list_add_tail(&vb->queue, &pxp->outq);
+
+		buf = container_of(vb, struct pxp_buffer, vb);
+		list_add_tail(&buf->queue, &pxp->nextq);
+		queue_work(pxp->workqueue, &pxp->work);
+	}
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxp_buf_release(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb)
+{
+	pxp_buf_free(q, vb);
+}
+
+static struct videobuf_queue_ops pxp_vbq_ops = {
+	.buf_setup = pxp_buf_setup,
+	.buf_prepare = pxp_buf_prepare,
+	.buf_queue = pxp_buf_queue,
+	.buf_release = pxp_buf_release,
+};
+
+static int pxp_querycap(struct file *file, void *fh,
+			struct v4l2_capability *cap)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	memset(cap, 0, sizeof(*cap));
+	strcpy(cap->driver, "pxp");
+	strcpy(cap->card, "pxp");
+	strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev),
+		sizeof(cap->bus_info));
+
+	cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR;
+
+	cap->capabilities = V4L2_CAP_VIDEO_OUTPUT |
+	    V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_STREAMING;
+
+	return 0;
+}
+
+static int pxp_g_fbuf(struct file *file, void *priv,
+		      struct v4l2_framebuffer *fb)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	memset(fb, 0, sizeof(*fb));
+
+	fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
+	    V4L2_FBUF_CAP_CHROMAKEY |
+	    V4L2_FBUF_CAP_LOCAL_ALPHA | V4L2_FBUF_CAP_GLOBAL_ALPHA;
+
+	if (pxp->global_alpha_state)
+		fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA;
+	if (pxp->local_alpha_state)
+		fb->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
+	if (pxp->s1_chromakey_state)
+		fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
+
+	return 0;
+}
+
+static int pxp_s_fbuf(struct file *file, void *priv,
+		      struct v4l2_framebuffer *fb)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	pxp->overlay_state = (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0;
+	pxp->global_alpha_state =
+	    (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0;
+	pxp->local_alpha_state = (fb->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) != 0;
+	/* Global alpha overrides local alpha if both are requested */
+	if (pxp->global_alpha_state && pxp->local_alpha_state)
+		pxp->local_alpha_state = 0;
+	pxp->s1_chromakey_state = (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0;
+
+	pxp_set_olparam(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+
+	return 0;
+}
+
+static int pxp_g_crop(struct file *file, void *fh, struct v4l2_crop *c)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
+		return -EINVAL;
+
+	c->c.left = pxp->drect.left;
+	c->c.top = pxp->drect.top;
+	c->c.width = pxp->drect.width;
+	c->c.height = pxp->drect.height;
+
+	return 0;
+}
+
+static int pxp_s_crop(struct file *file, void *fh, struct v4l2_crop *c)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int l = c->c.left;
+	int t = c->c.top;
+	int w = c->c.width;
+	int h = c->c.height;
+	int fbw = pxp->fb.fmt.width;
+	int fbh = pxp->fb.fmt.height;
+
+	if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
+		return -EINVAL;
+
+	/* Constrain parameters to FB limits */
+	w = min(w, fbw);
+	w = max(w, PXP_MIN_PIX);
+	h = min(h, fbh);
+	h = max(h, PXP_MIN_PIX);
+	if ((l + w) > fbw)
+		l = 0;
+	if ((t + h) > fbh)
+		t = 0;
+
+	/* Round up values to PxP pixel block */
+	l = roundup(l, PXP_MIN_PIX);
+	t = roundup(t, PXP_MIN_PIX);
+	w = roundup(w, PXP_MIN_PIX);
+	h = roundup(h, PXP_MIN_PIX);
+
+	pxp->drect.left = l;
+	pxp->drect.top = t;
+	pxp->drect.width = w;
+	pxp->drect.height = h;
+
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+
+	return 0;
+}
+
+static int pxp_queryctrl(struct file *file, void *priv,
+			 struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (qc->id && qc->id == pxp_controls[i].id) {
+			memcpy(qc, &(pxp_controls[i]), sizeof(*qc));
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
+static int pxp_g_ctrl(struct file *file, void *priv, struct v4l2_control *vc)
+{
+	int i;
+
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (vc->id == pxp_controls[i].id)
+			return pxp_get_cstate(pxp, vc);
+
+	return -EINVAL;
+}
+
+static int pxp_s_ctrl(struct file *file, void *priv, struct v4l2_control *vc)
+{
+	int i;
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (vc->id == pxp_controls[i].id) {
+			if (vc->value < pxp_controls[i].minimum ||
+			    vc->value > pxp_controls[i].maximum)
+				return -ERANGE;
+			return pxp_set_cstate(pxp, vc);
+		}
+
+	return -EINVAL;
+}
+
+void pxp_release(struct video_device *vfd)
+{
+	struct pxps *pxp = video_get_drvdata(vfd);
+
+	spin_lock(&pxp->lock);
+	video_device_release(vfd);
+	spin_unlock(&pxp->lock);
+}
+
+static int pxp_hw_init(struct pxps *pxp)
+{
+	struct fb_var_screeninfo var;
+	struct fb_fix_screeninfo fix;
+	int err;
+
+	err = mxsfb_get_info(&var, &fix);
+	if (err)
+		return err;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, PXP_BASE_ADDR + HW_PXP_CTRL);
+
+	/* Config defaults */
+	pxp->active = NULL;
+
+	pxp->s0_fmt = &pxp_s0_formats[0];
+	pxp->drect.left = pxp->srect.left = 0;
+	pxp->drect.top = pxp->srect.top = 0;
+	pxp->drect.width = pxp->srect.width = pxp->s0_width = var.xres;
+	pxp->drect.height = pxp->srect.height = pxp->s0_height = var.yres;
+	pxp->s0_bgcolor = 0;
+
+	pxp->output = 0;
+	err = pxp_set_fbinfo(pxp);
+	if (err)
+		return err;
+
+	pxp->scaling = 0;
+	pxp->hflip = 0;
+	pxp->vflip = 0;
+	pxp->rotate = 0;
+	pxp->yuv = 0;
+
+	pxp->overlay_state = 0;
+	pxp->global_alpha_state = 0;
+	pxp->global_alpha = 0;
+	pxp->local_alpha_state = 0;
+	pxp->s1_chromakey_state = 0;
+	pxp->s1_chromakey = -1;
+	pxp->s0_chromakey = -1;
+
+	/* Write default h/w config */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_oln(pxp);
+	pxp_set_olparam(pxp);
+	pxp_set_s0colorkey(pxp);
+	pxp_set_s1colorkey(pxp);
+	pxp_set_csc(pxp);
+
+	return 0;
+}
+
+static int pxp_open(struct file *file)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	mutex_lock(&pxp->mutex);
+	pxp->users++;
+
+	if (pxp->users > 1) {
+		pxp->users--;
+		ret = -EBUSY;
+		goto out;
+	}
+out:
+	mutex_unlock(&pxp->mutex);
+	if (ret)
+		return ret;
+
+	pxp->next_queue_ended = 0;
+	pxp->workqueue = create_singlethread_workqueue("pxp");
+
+	videobuf_queue_dma_contig_init(&pxp->s0_vbq,
+				       &pxp_vbq_ops,
+				       &pxp->pdev->dev,
+				       &pxp->lock,
+				       V4L2_BUF_TYPE_VIDEO_OUTPUT,
+				       V4L2_FIELD_NONE,
+				       sizeof(struct pxp_buffer), pxp);
+
+	return 0;
+}
+
+static int pxp_close(struct file *file)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if (pxp->workqueue) {
+		flush_workqueue(pxp->workqueue);
+		destroy_workqueue(pxp->workqueue);
+	}
+
+	videobuf_stop(&pxp->s0_vbq);
+	videobuf_mmap_free(&pxp->s0_vbq);
+	pxp->active = NULL;
+
+	mutex_lock(&pxp->mutex);
+	pxp->users--;
+	mutex_unlock(&pxp->mutex);
+
+	return 0;
+}
+
+static int pxp_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret;
+
+	ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma);
+
+	return ret;
+}
+
+static const struct v4l2_file_operations pxp_fops = {
+	.owner = THIS_MODULE,
+	.open = pxp_open,
+	.release = pxp_close,
+	.ioctl = video_ioctl2,
+	.mmap = pxp_mmap,
+};
+
+static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
+	.vidioc_querycap = pxp_querycap,
+
+	.vidioc_reqbufs = pxp_reqbufs,
+	.vidioc_querybuf = pxp_querybuf,
+	.vidioc_qbuf = pxp_qbuf,
+	.vidioc_dqbuf = pxp_dqbuf,
+
+	.vidioc_streamon = pxp_streamon,
+	.vidioc_streamoff = pxp_streamoff,
+
+	.vidioc_enum_output = pxp_enumoutput,
+	.vidioc_g_output = pxp_g_output,
+	.vidioc_s_output = pxp_s_output,
+
+	.vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output,
+	.vidioc_try_fmt_vid_out = pxp_try_fmt_video_output,
+	.vidioc_g_fmt_vid_out = pxp_g_fmt_video_output,
+	.vidioc_s_fmt_vid_out = pxp_s_fmt_video_output,
+
+	.vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay,
+	.vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay,
+	.vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay,
+
+	.vidioc_g_fbuf = pxp_g_fbuf,
+	.vidioc_s_fbuf = pxp_s_fbuf,
+
+	.vidioc_g_crop = pxp_g_crop,
+	.vidioc_s_crop = pxp_s_crop,
+
+	.vidioc_queryctrl = pxp_queryctrl,
+	.vidioc_g_ctrl = pxp_g_ctrl,
+	.vidioc_s_ctrl = pxp_s_ctrl,
+};
+
+static const struct video_device pxp_template = {
+	.name = "PxP",
+	.vfl_type = V4L2_CAP_VIDEO_OUTPUT |
+		    V4L2_CAP_VIDEO_OVERLAY |
+		    V4L2_CAP_STREAMING,
+	.fops = &pxp_fops,
+	.release = pxp_release,
+	.minor = -1,
+	.ioctl_ops = &pxp_ioctl_ops,
+};
+
+static irqreturn_t pxp_irq(int irq, void *dev_id)
+{
+	struct pxps *pxp = (struct pxps *)dev_id;
+	struct videobuf_buffer *vb;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	__raw_writel(BM_PXP_STAT_IRQ, PXP_BASE_ADDR + HW_PXP_STAT_CLR);
+
+	if (list_empty(&pxp->outq)) {
+		pr_warning("irq: outq empty!!!\n");
+		goto out;
+	}
+
+	vb = list_entry(pxp->outq.next, struct videobuf_buffer, queue);
+	list_del_init(&vb->queue);
+
+	vb->state = VIDEOBUF_DONE;
+	do_gettimeofday(&vb->ts);
+	vb->field_count++;
+
+	wake_up(&vb->done);
+	wake_up(&pxp->done);
+out:
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int pxp_probe(struct platform_device *pdev)
+{
+	struct pxps *pxp;
+	struct resource *res;
+	int irq;
+	int err = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!res || irq < 0) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
+	if (!pxp) {
+		dev_err(&pdev->dev, "failed to allocate control object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	dev_set_drvdata(&pdev->dev, pxp);
+	pxp->res = res;
+	pxp->irq = irq;
+
+	pxp->regs_virt = dma_alloc_coherent(NULL,
+					    PAGE_ALIGN(sizeof
+						       (struct pxp_registers)),
+					    &pxp->regs_phys, GFP_KERNEL);
+	if (pxp->regs_virt == NULL) {
+		dev_err(&pdev->dev, "failed to allocate pxp_register object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	init_waitqueue_head(&pxp->done);
+
+	INIT_WORK(&pxp->work, pxp_next_handle);
+	INIT_LIST_HEAD(&pxp->outq);
+	INIT_LIST_HEAD(&pxp->nextq);
+	spin_lock_init(&pxp->lock);
+	mutex_init(&pxp->mutex);
+
+	if (!request_mem_region(res->start, res->end - res->start + 1,
+				PXP_DRIVER_NAME)) {
+		err = -EBUSY;
+		goto freepxp;
+	}
+
+	pxp->regs = (void __iomem *)res->start;	/* it is already ioremapped */
+	pxp->pdev = pdev;
+
+	err = request_irq(pxp->irq, pxp_irq, 0, PXP_DRIVER_NAME, pxp);
+
+	if (err) {
+		dev_err(&pdev->dev, "interrupt register failed\n");
+		goto release;
+	}
+
+	pxp->vdev = video_device_alloc();
+	if (!pxp->vdev) {
+		dev_err(&pdev->dev, "video_device_alloc() failed\n");
+		err = -ENOMEM;
+		goto freeirq;
+	}
+
+	memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template));
+	video_set_drvdata(pxp->vdev, pxp);
+
+	err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0);
+	if (err) {
+		dev_err(&pdev->dev, "failed to register video device\n");
+		goto freevdev;
+	}
+
+	err = pxp_hw_init(pxp);
+	if (err) {
+		dev_err(&pdev->dev, "failed to initialize hardware\n");
+		goto freevdev;
+	}
+
+	dev_info(&pdev->dev, "initialized\n");
+
+exit:
+	return err;
+
+freevdev:
+	video_device_release(pxp->vdev);
+
+freeirq:
+	free_irq(pxp->irq, pxp);
+
+release:
+	release_mem_region(res->start, res->end - res->start + 1);
+
+freepxp:
+	kfree(pxp);
+
+	return err;
+}
+
+static int __devexit pxp_remove(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	video_unregister_device(pxp->vdev);
+	video_device_release(pxp->vdev);
+
+	if (pxp->regs_virt)
+		dma_free_coherent(0, PAGE_ALIGN(sizeof(struct pxp_registers)),
+				  pxp->regs_virt, pxp->regs_phys);
+	kfree(pxp->outb);
+	kfree(pxp);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pxp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+
+	while (__raw_readl(PXP_BASE_ADDR + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
+		;
+
+	for (i = 0; i < REGS1_NUMS; i++)
+		regs1[i] =
+		    __raw_readl(PXP_BASE_ADDR + HW_PXP_CTRL + REG_OFFSET * i);
+
+	for (i = 0; i < REGS2_NUMS; i++)
+		regs2[i] =
+		    __raw_readl(PXP_BASE_ADDR + HW_PXP_S0COLORKEYLOW +
+				REG_OFFSET * i);
+
+	for (i = 0; i < REGS3_NUMS; i++)
+		regs3[i] =
+		    __raw_readl(PXP_BASE_ADDR + HW_PXP_OLn(0) + REG_OFFSET * i);
+
+	__raw_writel(BM_PXP_CTRL_SFTRST, PXP_BASE_ADDR + HW_PXP_CTRL);
+
+	return 0;
+}
+
+static int pxp_resume(struct platform_device *pdev)
+{
+	int i;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, PXP_BASE_ADDR + HW_PXP_CTRL);
+
+	for (i = 0; i < REGS1_NUMS; i++)
+		__raw_writel(regs1[i],
+			     PXP_BASE_ADDR + HW_PXP_CTRL + REG_OFFSET * i);
+
+	for (i = 0; i < REGS2_NUMS; i++)
+		__raw_writel(regs2[i],
+			     PXP_BASE_ADDR + HW_PXP_S0COLORKEYLOW +
+			     REG_OFFSET * i);
+
+	for (i = 0; i < REGS3_NUMS; i++)
+		__raw_writel(regs3[i],
+			     PXP_BASE_ADDR + HW_PXP_OLn(0) + REG_OFFSET * i);
+
+	return 0;
+}
+#else
+#define	pxp_suspend	NULL
+#define	pxp_resume	NULL
+#endif
+
+static struct platform_driver pxp_driver = {
+	.driver = {
+		   .name = PXP_DRIVER_NAME,
+		   },
+	.probe = pxp_probe,
+	.remove = __exit_p(pxp_remove),
+	.suspend = pxp_suspend,
+	.resume = pxp_resume,
+};
+
+static int __devinit pxp_init(void)
+{
+	return platform_driver_register(&pxp_driver);
+}
+
+static void __exit pxp_exit(void)
+{
+	platform_driver_unregister(&pxp_driver);
+}
+
+module_init(pxp_init);
+module_exit(pxp_exit);
+
+MODULE_DESCRIPTION("STMP37xx PxP driver");
+MODULE_AUTHOR("Matt Porter <mporter@embeddedalley.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxs_pxp.h b/drivers/media/video/mxs_pxp.h
new file mode 100644
index 000000000000..6538388fa4cd
--- /dev/null
+++ b/drivers/media/video/mxs_pxp.h
@@ -0,0 +1,158 @@
+/*
+ * Freescale MXS PxP driver
+ *
+ * Author: Matt Porter <mporter@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifdef	CONFIG_ARCH_MX23
+#define BF_PXP_CTRL_OUTBUF_FORMAT(v)	BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v)
+
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P   	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P
+#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565
+#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555	\
+	BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555
+
+#define BF_PXP_OUTSIZE_WIDTH(v)		BF_PXP_RGBSIZE_WIDTH(v)
+#define BF_PXP_OUTSIZE_HEIGHT(v)	BF_PXP_RGBSIZE_HEIGHT(v)
+
+/* The maximum down scaling factor is 1/2 */
+#define	PXP_DOWNSCALE_THRESHOLD		0x2000
+#else
+/* The maximum down scaling factor is 1/4 */
+#define	PXP_DOWNSCALE_THRESHOLD		0x4000
+#endif
+
+struct pxp_overlay_registers {
+	u32 ol;
+	u32 olsize;
+	u32 olparam;
+	u32 olparam2;
+};
+
+/* Registers feed for PXP_NEXT */
+struct pxp_registers {
+	u32 ctrl;
+	u32 outbuf;
+	u32 outbuf2;
+	u32 outsize;
+	u32 s0buf;
+	u32 s0ubuf;
+	u32 s0vbuf;
+	u32 s0param;
+	u32 s0background;
+	u32 s0crop;
+	u32 s0scale;
+	u32 s0offset;
+	u32 s0colorkeylow;
+	u32 s0colorkeyhigh;
+	u32 olcolorkeylow;
+	u32 olcolorkeyhigh;
+
+	struct pxp_overlay_registers ol0;
+	struct pxp_overlay_registers ol1;
+	struct pxp_overlay_registers ol2;
+	struct pxp_overlay_registers ol3;
+	struct pxp_overlay_registers ol4;
+	struct pxp_overlay_registers ol5;
+	struct pxp_overlay_registers ol6;
+	struct pxp_overlay_registers ol7;
+};
+
+struct pxp_buffer {
+	/* Must be first! */
+	struct videobuf_buffer vb;
+	struct list_head queue;
+};
+
+struct pxps {
+	struct platform_device *pdev;
+	struct resource *res;
+	int irq;
+	void __iomem *regs;
+
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	spinlock_t lock;
+	struct mutex mutex;
+	int users;
+
+	struct video_device *vdev;
+
+	struct videobuf_queue s0_vbq;
+	struct videobuf_buffer *active;
+	struct list_head outq;
+	struct list_head nextq;
+
+	int output;
+	u32 *outb;
+	dma_addr_t outb_phys;
+
+	/* Current S0 configuration */
+	struct pxp_data_format *s0_fmt;
+	u32 s0_width;
+	u32 s0_height;
+	u32 s0_bgcolor;
+	u32 s0_chromakey;
+
+	struct v4l2_framebuffer fb;
+	struct v4l2_rect drect;
+	struct v4l2_rect srect;
+
+	/* Transformation support */
+	int scaling;
+	int hflip;
+	int vflip;
+	int rotate;
+	int yuv;
+
+	/* Output overlay support */
+	int overlay_state;
+	int global_alpha_state;
+	u8  global_alpha;
+	int local_alpha_state;
+	int s1_chromakey_state;
+	u32 s1_chromakey;
+
+	/* PXP_NEXT */
+	u32 regs_phys;
+	struct pxp_registers *regs_virt;
+	wait_queue_head_t done;
+	int next_queue_ended;
+};
+
+struct pxp_data_format {
+	char *name;
+	unsigned int bpp;
+	u32 fourcc;
+	enum v4l2_colorspace colorspace;
+	u32 ctrl_s0_fmt;
+};
+
+extern int mxsfb_get_info(struct fb_var_screeninfo *var,
+				struct fb_fix_screeninfo *fix);
+extern void mxsfb_cfg_pxp(int enable, dma_addr_t pxp_phys);
diff --git a/drivers/media/video/pxp.c b/drivers/media/video/pxp.c
new file mode 100644
index 000000000000..0f0e89cd6806
--- /dev/null
+++ b/drivers/media/video/pxp.c
@@ -0,0 +1,1408 @@
+/*
+ * Freescale STMP378X PxP driver
+ *
+ * Author: Matt Porter <mporter@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+#include <linux/videodev2.h>
+
+#include <media/videobuf-dma-contig.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+
+#include <mach/platform.h>
+#include <mach/regs-pxp.h>
+#include <mach/lcdif.h>
+
+#include "pxp.h"
+
+#define PXP_DRIVER_NAME			"stmp3xxx-pxp"
+#define PXP_DRIVER_MAJOR		1
+#define PXP_DRIVER_MINOR		0
+
+#define PXP_DEF_BUFS			2
+#define PXP_MIN_PIX			8
+
+#define V4L2_OUTPUT_TYPE_INTERNAL	4
+
+#define PXP_WAITCON	((__raw_readl(HW_PXP_NEXT_ADDR) & BM_PXP_NEXT_ENABLED) \
+				!= BM_PXP_NEXT_ENABLED)
+
+#define REG_OFFSET	0x10
+#define REGS1_NUMS	16
+#define REGS2_NUMS	5
+#define REGS3_NUMS	32
+static u32 regs1[REGS1_NUMS];
+static u32 regs2[REGS2_NUMS];
+static u32 regs3[REGS3_NUMS];
+
+static struct pxp_data_format pxp_s0_formats[] = {
+	{
+		.name = "24-bit RGB",
+		.bpp = 4,
+		.fourcc = V4L2_PIX_FMT_RGB24,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+		.ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB888,
+	}, {
+		.name = "16-bit RGB 5:6:5",
+		.bpp = 2,
+		.fourcc = V4L2_PIX_FMT_RGB565,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+		.ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB565,
+	}, {
+		.name = "16-bit RGB 5:5:5",
+		.bpp = 2,
+		.fourcc = V4L2_PIX_FMT_RGB555,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+		.ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB555,
+	}, {
+		.name = "YUV 4:2:0 Planar",
+		.bpp = 2,
+		.fourcc = V4L2_PIX_FMT_YUV420,
+		.colorspace = V4L2_COLORSPACE_JPEG,
+		.ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV420,
+	}, {
+		.name = "YUV 4:2:2 Planar",
+		.bpp = 2,
+		.fourcc = V4L2_PIX_FMT_YUV422P,
+		.colorspace = V4L2_COLORSPACE_JPEG,
+		.ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV422,
+	},
+};
+
+struct v4l2_queryctrl pxp_controls[] = {
+	{
+		.id 		= V4L2_CID_HFLIP,
+		.type 		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name 		= "Horizontal Flip",
+		.minimum 	= 0,
+		.maximum 	= 1,
+		.step 		= 1,
+		.default_value	= 0,
+		.flags		= 0,
+	}, {
+		.id		= V4L2_CID_VFLIP,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "Vertical Flip",
+		.minimum	= 0,
+		.maximum	= 1,
+		.step		= 1,
+		.default_value	= 0,
+		.flags		= 0,
+	}, {
+		.id		= V4L2_CID_PRIVATE_BASE,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Rotation",
+		.minimum	= 0,
+		.maximum	= 270,
+		.step		= 90,
+		.default_value	= 0,
+		.flags		= 0,
+	}, {
+		.id		= V4L2_CID_PRIVATE_BASE + 1,
+		.name		= "Background Color",
+		.minimum	= 0,
+		.maximum	= 0xFFFFFF,
+		.step		= 1,
+		.default_value	= 0,
+		.flags		= 0,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+	}, {
+		.id		= V4L2_CID_PRIVATE_BASE + 2,
+		.name		= "Set S0 Chromakey",
+		.minimum	= -1,
+		.maximum	= 0xFFFFFF,
+		.step		= 1,
+		.default_value	= -1,
+		.flags		= 0,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+	}, {
+		.id		= V4L2_CID_PRIVATE_BASE + 3,
+		.name		= "YUV Colorspace",
+		.minimum	= 0,
+		.maximum	= 1,
+		.step		= 1,
+		.default_value	= 0,
+		.flags		= 0,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+	},
+};
+
+static void pxp_set_ctrl(struct pxps *pxp)
+{
+	u32 ctrl;
+
+	ctrl = BF(pxp->s0_fmt->ctrl_s0_fmt, PXP_CTRL_S0_FORMAT);
+	ctrl |=
+	BF(BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888, PXP_CTRL_OUTPUT_RGB_FORMAT);
+	ctrl |= BM_PXP_CTRL_CROP;
+
+	if (pxp->scaling)
+		ctrl |= BM_PXP_CTRL_SCALE;
+	if (pxp->vflip)
+		ctrl |= BM_PXP_CTRL_VFLIP;
+	if (pxp->hflip)
+		ctrl |= BM_PXP_CTRL_HFLIP;
+	if (pxp->rotate)
+		ctrl |= BF(pxp->rotate/90, PXP_CTRL_ROTATE);
+
+	ctrl |= BM_PXP_CTRL_IRQ_ENABLE;
+	if (pxp->active)
+		ctrl |= BM_PXP_CTRL_ENABLE;
+
+	__raw_writel(ctrl, HW_PXP_CTRL_ADDR);
+	pxp->regs_virt->ctrl = ctrl;
+}
+
+static void pxp_set_rgbbuf(struct pxps *pxp)
+{
+	pxp->regs_virt->rgbbuf = pxp->outb_phys;
+	/* Always equal to the FB size */
+	pxp->regs_virt->rgbsize = BF(pxp->fb.fmt.width, PXP_RGBSIZE_WIDTH) |
+				BF(pxp->fb.fmt.height, PXP_RGBSIZE_HEIGHT);
+}
+
+static void pxp_set_s0colorkey(struct pxps *pxp)
+{
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (pxp->s0_chromakey == -1) {
+		/* disable color key */
+		pxp->regs_virt->s0colorkeylow = 0xFFFFFF;
+		pxp->regs_virt->s0colorkeyhigh = 0;
+	} else {
+		pxp->regs_virt->s0colorkeylow = pxp->s0_chromakey;
+		pxp->regs_virt->s0colorkeyhigh = pxp->s0_chromakey;
+	}
+}
+
+static void pxp_set_s1colorkey(struct pxps *pxp)
+{
+	/* Low and high are set equal. V4L does not allow a chromakey range */
+	if (pxp->s1_chromakey_state != 0 && pxp->s1_chromakey != -1) {
+		pxp->regs_virt->olcolorkeylow = pxp->s1_chromakey;
+		pxp->regs_virt->olcolorkeyhigh = pxp->s1_chromakey;
+	} else {
+		/* disable color key */
+		pxp->regs_virt->olcolorkeylow = 0xFFFFFF;
+		pxp->regs_virt->olcolorkeyhigh = 0;
+	}
+}
+
+static void pxp_set_oln(struct pxps *pxp)
+{
+	pxp->regs_virt->ol0.ol = (u32)pxp->fb.base;
+	pxp->regs_virt->ol0.olsize =
+		BF(pxp->fb.fmt.width >> 3, PXP_OLnSIZE_WIDTH) |
+		BF(pxp->fb.fmt.height >> 3, PXP_OLnSIZE_HEIGHT);
+}
+
+static void pxp_set_olparam(struct pxps *pxp)
+{
+	u32 olparam;
+	struct v4l2_pix_format *fmt = &pxp->fb.fmt;
+
+	olparam = BF(pxp->global_alpha, PXP_OLnPARAM_ALPHA);
+	if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
+		olparam |=
+		BF(BV_PXP_OLnPARAM_FORMAT__RGB888, PXP_OLnPARAM_FORMAT);
+	else
+		olparam |=
+		BF(BV_PXP_OLnPARAM_FORMAT__RGB565, PXP_OLnPARAM_FORMAT);
+	if (pxp->global_alpha_state)
+		olparam |= BF(BV_PXP_OLnPARAM_ALPHA_CNTL__Override,
+					PXP_OLnPARAM_ALPHA_CNTL);
+	if (pxp->s1_chromakey_state)
+		olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY;
+	if (pxp->overlay_state)
+		olparam |= BM_PXP_OLnPARAM_ENABLE;
+
+	pxp->regs_virt->ol0.olparam = olparam;
+}
+
+static void pxp_set_s0param(struct pxps *pxp)
+{
+	u32 s0param;
+
+	s0param = BF(pxp->drect.left >> 3, PXP_S0PARAM_XBASE);
+	s0param |= BF(pxp->drect.top >> 3, PXP_S0PARAM_YBASE);
+	s0param |= BF(pxp->s0_width >> 3, PXP_S0PARAM_WIDTH);
+	s0param |= BF(pxp->s0_height >> 3, PXP_S0PARAM_HEIGHT);
+	pxp->regs_virt->s0param = s0param;
+}
+
+static void pxp_set_s0crop(struct pxps *pxp)
+{
+	u32 s0crop;
+
+	s0crop = BF(pxp->srect.left >> 3, PXP_S0CROP_XBASE);
+	s0crop |= BF(pxp->srect.top >> 3, PXP_S0CROP_YBASE);
+	s0crop |= BF(pxp->drect.width >> 3, PXP_S0CROP_WIDTH);
+	s0crop |= BF(pxp->drect.height >> 3, PXP_S0CROP_HEIGHT);
+	pxp->regs_virt->s0crop = s0crop;
+}
+
+static int pxp_set_scaling(struct pxps *pxp)
+{
+	int ret = 0;
+	u32 xscale, yscale, s0scale;
+
+	if ((pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV420) &&
+		(pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV422P)) {
+		pxp->scaling = 0;
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if ((pxp->srect.width == pxp->drect.width) &&
+		(pxp->srect.height == pxp->drect.height)) {
+		pxp->scaling = 0;
+		goto out;
+	}
+
+	pxp->scaling = 1;
+	xscale = pxp->srect.width * 0x1000 / pxp->drect.width;
+	yscale = pxp->srect.height * 0x1000 / pxp->drect.height;
+	s0scale = BF(yscale, PXP_S0SCALE_YSCALE) |
+		  BF(xscale, PXP_S0SCALE_XSCALE);
+	pxp->regs_virt->s0scale = s0scale;
+
+out:
+	pxp_set_ctrl(pxp);
+
+	return ret;
+}
+
+static int pxp_set_fbinfo(struct pxps *pxp)
+{
+	struct fb_var_screeninfo var;
+	struct fb_fix_screeninfo fix;
+	struct v4l2_framebuffer *fb = &pxp->fb;
+	int err;
+
+	err = stmp3xxxfb_get_info(&var, &fix);
+
+	fb->fmt.width = var.xres;
+	fb->fmt.height = var.yres;
+	if (var.bits_per_pixel == 16)
+		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565;
+	else
+		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24;
+	fb->base = (void *)fix.smem_start;
+	return err;
+}
+
+static void pxp_set_s0bg(struct pxps *pxp)
+{
+	pxp->regs_virt->s0background = pxp->s0_bgcolor;
+}
+
+static void pxp_set_csc(struct pxps *pxp)
+{
+	if (pxp->yuv) {
+		/* YUV colorspace */
+		__raw_writel(0x04030000, HW_PXP_CSCCOEFF0_ADDR);
+		__raw_writel(0x01230208, HW_PXP_CSCCOEFF1_ADDR);
+		__raw_writel(0x076b079c, HW_PXP_CSCCOEFF2_ADDR);
+	} else {
+		/* YCrCb colorspace */
+		__raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
+		__raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
+		__raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
+	}
+}
+
+static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc)
+{
+
+	if (vc->id == V4L2_CID_HFLIP)
+		pxp->hflip = vc->value;
+	else if (vc->id == V4L2_CID_VFLIP)
+		pxp->vflip = vc->value;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE) {
+		if (vc->value % 90)
+			return -ERANGE;
+		pxp->rotate = vc->value;
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) {
+		pxp->s0_bgcolor = vc->value;
+		pxp_set_s0bg(pxp);
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) {
+		pxp->s0_chromakey = vc->value;
+		pxp_set_s0colorkey(pxp);
+	} else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) {
+		pxp->yuv = vc->value;
+		pxp_set_csc(pxp);
+	}
+
+	pxp_set_ctrl(pxp);
+
+	return 0;
+}
+
+static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc)
+{
+	if (vc->id == V4L2_CID_HFLIP)
+		vc->value = pxp->hflip;
+	else if (vc->id == V4L2_CID_VFLIP)
+		vc->value = pxp->vflip;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE)
+		vc->value = pxp->rotate;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 1)
+		vc->value = pxp->s0_bgcolor;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 2)
+		vc->value = pxp->s0_chromakey;
+	else if (vc->id == V4L2_CID_PRIVATE_BASE + 3)
+		vc->value = pxp->yuv;
+
+	return 0;
+}
+
+static int pxp_enumoutput(struct file *file, void *fh,
+			struct v4l2_output *o)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if ((o->index < 0) || (o->index > 1))
+		return -EINVAL;
+
+	memset(o, 0, sizeof(struct v4l2_output));
+	if (o->index == 0) {
+		strcpy(o->name, "PxP Display Output");
+		pxp->output = 0;
+	} else {
+		strcpy(o->name, "PxP Virtual Output");
+		pxp->output = 1;
+	}
+	o->type = V4L2_OUTPUT_TYPE_INTERNAL;
+	o->std = 0;
+	o->reserved[0] = pxp->outb_phys;
+
+	return 0;
+}
+
+static int pxp_g_output(struct file *file, void *fh,
+			unsigned int *i)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	*i = pxp->output;
+
+	return 0;
+}
+
+static int pxp_s_output(struct file *file, void *fh,
+			unsigned int i)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_pix_format *fmt = &pxp->fb.fmt;
+	int bpp;
+
+	if ((i < 0) || (i > 1))
+		return -EINVAL;
+
+	if (pxp->outb)
+		goto out;
+
+	/* Output buffer is same format as fbdev */
+	if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
+		bpp = 4;
+	else
+		bpp = 2;
+
+	pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL);
+	pxp->outb_phys = virt_to_phys(pxp->outb);
+	dma_map_single(NULL, pxp->outb,
+			fmt->width * fmt->height * bpp, DMA_TO_DEVICE);
+
+out:
+	pxp_set_rgbbuf(pxp);
+
+	return 0;
+}
+
+static int pxp_enum_fmt_video_output(struct file *file, void *fh,
+				struct v4l2_fmtdesc *fmt)
+{
+	enum v4l2_buf_type type = fmt->type;
+	int index = fmt->index;
+
+	if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats)))
+		return -EINVAL;
+
+	memset(fmt, 0, sizeof(struct v4l2_fmtdesc));
+	fmt->index = index;
+	fmt->type = type;
+	fmt->pixelformat = pxp_s0_formats[index].fourcc;
+	strcpy(fmt->description, pxp_s0_formats[index].name);
+
+	return 0;
+}
+
+static int pxp_g_fmt_video_output(struct file *file, void *fh,
+				struct v4l2_format *f)
+{
+	struct v4l2_pix_format *pf = &f->fmt.pix;
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct pxp_data_format *fmt = pxp->s0_fmt;
+
+	pf->width = pxp->s0_width;
+	pf->height = pxp->s0_height;
+	pf->pixelformat = fmt->fourcc;
+	pf->field = V4L2_FIELD_NONE;
+	pf->bytesperline = fmt->bpp * pf->width;
+	pf->sizeimage = pf->bytesperline * pf->height;
+	pf->colorspace = fmt->colorspace;
+	pf->priv = 0;
+
+	return 0;
+}
+
+static struct pxp_data_format *pxp_get_format(struct v4l2_format *f)
+{
+	struct pxp_data_format *fmt;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) {
+		fmt = &pxp_s0_formats[i];
+		if (fmt->fourcc == f->fmt.pix.pixelformat)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(pxp_s0_formats))
+		return NULL;
+
+	return &pxp_s0_formats[i];
+}
+
+static int pxp_try_fmt_video_output(struct file *file, void *fh,
+				struct v4l2_format *f)
+{
+	int w = f->fmt.pix.width;
+	int h = f->fmt.pix.height;
+	struct pxp_data_format *fmt = pxp_get_format(f);
+
+	if (!fmt)
+		return -EINVAL;
+
+	w = min(w, 2040);
+	w = max(w, 8);
+	h = min(h, 2040);
+	h = max(h, 8);
+	f->fmt.pix.field = V4L2_FIELD_NONE;
+	f->fmt.pix.width = w;
+	f->fmt.pix.height = h;
+	f->fmt.pix.pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+static int pxp_s_fmt_video_output(struct file *file, void *fh,
+				struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_pix_format *pf = &f->fmt.pix;
+	int ret = pxp_try_fmt_video_output(file, fh, f);
+
+	if (ret == 0) {
+		pxp->s0_fmt = pxp_get_format(f);
+		pxp->s0_width = pf->width;
+		pxp->s0_height = pf->height;
+		pxp_set_ctrl(pxp);
+		pxp_set_s0param(pxp);
+	}
+
+	return ret;
+}
+
+static int pxp_g_fmt_output_overlay(struct file *file, void *fh,
+				struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+
+	memset(wf, 0, sizeof(struct v4l2_window));
+	wf->chromakey = pxp->s1_chromakey;
+	wf->global_alpha = pxp->global_alpha;
+	wf->field = V4L2_FIELD_NONE;
+	wf->clips = NULL;
+	wf->clipcount = 0;
+	wf->bitmap = NULL;
+	wf->w.left = pxp->srect.left;
+	wf->w.top = pxp->srect.top;
+	wf->w.width = pxp->srect.width;
+	wf->w.height = pxp->srect.height;
+
+	return 0;
+}
+
+static int pxp_try_fmt_output_overlay(struct file *file, void *fh,
+				struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+	struct v4l2_rect srect;
+	u32 s1_chromakey = wf->chromakey;
+	u8 global_alpha = wf->global_alpha;
+
+	memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect));
+
+	pxp_g_fmt_output_overlay(file, fh, f);
+
+	wf->chromakey = s1_chromakey;
+	wf->global_alpha = global_alpha;
+
+	/* Constrain parameters to the input buffer */
+	wf->w.left = srect.left;
+	wf->w.top = srect.top;
+	wf->w.width = min(srect.width, ((__s32)pxp->s0_width - wf->w.left));
+	wf->w.height = min(srect.height, ((__s32)pxp->s0_height - wf->w.top));
+
+	return 0;
+}
+
+static int pxp_s_fmt_output_overlay(struct file *file, void *fh,
+					struct v4l2_format *f)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	struct v4l2_window *wf = &f->fmt.win;
+	int ret = pxp_try_fmt_output_overlay(file, fh, f);
+
+	if (ret == 0) {
+		pxp->srect.left = wf->w.left;
+		pxp->srect.top = wf->w.top;
+		pxp->srect.width = wf->w.width;
+		pxp->srect.height = wf->w.height;
+		pxp->global_alpha = wf->global_alpha;
+		pxp->s1_chromakey = wf->chromakey;
+		pxp_set_s0param(pxp);
+		pxp_set_s0crop(pxp);
+		pxp_set_scaling(pxp);
+		pxp_set_olparam(pxp);
+		pxp_set_s1colorkey(pxp);
+	}
+
+	return ret;
+}
+
+static int pxp_reqbufs(struct file *file, void *priv,
+			struct v4l2_requestbuffers *r)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_reqbufs(&pxp->s0_vbq, r);
+}
+
+static int pxp_querybuf(struct file *file, void *priv,
+			struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_querybuf(&pxp->s0_vbq, b);
+}
+
+static int pxp_qbuf(struct file *file, void *priv,
+			struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_qbuf(&pxp->s0_vbq, b);
+}
+
+static int pxp_dqbuf(struct file *file, void *priv,
+			struct v4l2_buffer *b)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK);
+}
+
+static int pxp_streamon(struct file *file, void *priv,
+			enum v4l2_buf_type t)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -EINVAL;
+
+	ret = videobuf_streamon(&pxp->s0_vbq);
+
+	if (!ret && (pxp->output == 0))
+		stmp3xxxfb_cfg_pxp(1, pxp->outb_phys);
+
+	return ret;
+}
+
+static int pxp_streamoff(struct file *file, void *priv,
+			enum v4l2_buf_type t)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -EINVAL;
+
+	ret = videobuf_streamoff(&pxp->s0_vbq);
+
+	if (!ret)
+		stmp3xxxfb_cfg_pxp(0, 0);
+
+	return ret;
+}
+
+static int pxp_buf_setup(struct videobuf_queue *q,
+			unsigned int *count, unsigned *size)
+{
+	struct pxps *pxp = q->priv_data;
+
+	*size = pxp->s0_width * pxp->s0_height * pxp->s0_fmt->bpp;
+
+	if (0 == *count)
+		*count = PXP_DEF_BUFS;
+
+	return 0;
+}
+
+static void pxp_buf_free(struct videobuf_queue *q, struct videobuf_buffer *vb)
+{
+	if (in_interrupt())
+		BUG();
+
+	videobuf_dma_contig_free(q, vb);
+
+	vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int pxp_buf_prepare(struct videobuf_queue *q,
+			struct videobuf_buffer *vb,
+			enum v4l2_field field)
+{
+	struct pxps *pxp = q->priv_data;
+	int ret = 0;
+
+	vb->width = pxp->s0_width;
+	vb->height = pxp->s0_height;
+	vb->size = vb->width * vb->height * pxp->s0_fmt->bpp;
+	vb->field = V4L2_FIELD_NONE;
+	vb->state = VIDEOBUF_NEEDS_INIT;
+
+	ret = videobuf_iolock(q, vb, NULL);
+	if (ret)
+		goto fail;
+	vb->state = VIDEOBUF_PREPARED;
+
+	return 0;
+
+fail:
+	pxp_buf_free(q, vb);
+	return ret;
+}
+
+static void pxp_buf_next(struct pxps *pxp)
+{
+	dma_addr_t Y, U, V;
+
+	if (pxp->active) {
+		pxp->active->state = VIDEOBUF_ACTIVE;
+		Y = videobuf_to_dma_contig(pxp->active);
+		pxp->regs_virt->s0buf = Y;
+		if ((pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) ||
+		    (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV422P)) {
+			int s = 1;	/* default to YUV 4:2:2 */
+			if (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420)
+				s = 2;
+			U = Y + (pxp->s0_width * pxp->s0_height);
+			V = U + ((pxp->s0_width * pxp->s0_height) >> s);
+			pxp->regs_virt->s0ubuf = U;
+			pxp->regs_virt->s0vbuf = V;
+		}
+		pxp->regs_virt->ctrl =
+			__raw_readl(HW_PXP_CTRL_ADDR) | BM_PXP_CTRL_ENABLE;
+	}
+
+	__raw_writel(pxp->regs_phys, HW_PXP_NEXT_ADDR);
+}
+
+static void pxp_next_handle(struct work_struct *w)
+{
+	struct pxps *pxp = container_of(w, struct pxps, work);
+	struct pxp_buffer *buf, *next;
+	unsigned long flags;
+
+	if (pxp->next_queue_ended == 1)
+		return;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	while (!list_empty(&pxp->nextq)) {
+		spin_unlock_irqrestore(&pxp->lock, flags);
+
+		if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON,
+					5 * HZ) || signal_pending(current)) {
+			spin_lock_irqsave(&pxp->lock, flags);
+			list_for_each_entry_safe(buf, next, &pxp->nextq, queue)
+				list_del(&buf->queue);
+			spin_unlock_irqrestore(&pxp->lock, flags);
+			pxp->next_queue_ended = 1;
+			return;
+		}
+
+		spin_lock_irqsave(&pxp->lock, flags);
+		buf = list_entry(pxp->nextq.next,
+					struct pxp_buffer,
+					queue);
+		list_del_init(&buf->queue);
+		pxp->active = &buf->vb;
+		pxp->active->state = VIDEOBUF_QUEUED;
+		pxp_buf_next(pxp);
+	}
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxp_buf_queue(struct videobuf_queue *q,
+			struct videobuf_buffer *vb)
+{
+	struct pxps *pxp = q->priv_data;
+	struct pxp_buffer *buf;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	if (list_empty(&pxp->outq)) {
+		list_add_tail(&vb->queue, &pxp->outq);
+		vb->state = VIDEOBUF_QUEUED;
+
+		pxp->active = vb;
+		pxp_buf_next(pxp);
+	} else {
+		list_add_tail(&vb->queue, &pxp->outq);
+
+		buf = container_of(vb, struct pxp_buffer, vb);
+		list_add_tail(&buf->queue, &pxp->nextq);
+		queue_work(pxp->workqueue, &pxp->work);
+	}
+
+	spin_unlock_irqrestore(&pxp->lock, flags);
+}
+
+static void pxp_buf_release(struct videobuf_queue *q,
+			struct videobuf_buffer *vb)
+{
+	pxp_buf_free(q, vb);
+}
+
+static struct videobuf_queue_ops pxp_vbq_ops = {
+	.buf_setup	= pxp_buf_setup,
+	.buf_prepare	= pxp_buf_prepare,
+	.buf_queue	= pxp_buf_queue,
+	.buf_release	= pxp_buf_release,
+};
+
+static int pxp_querycap(struct file *file, void *fh,
+			struct v4l2_capability *cap)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	memset(cap, 0, sizeof(*cap));
+	strcpy(cap->driver, "pxp");
+	strcpy(cap->card, "pxp");
+	strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev), sizeof(cap->bus_info));
+
+	cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR;
+
+	cap->capabilities = V4L2_CAP_VIDEO_OUTPUT |
+				V4L2_CAP_VIDEO_OUTPUT_OVERLAY |
+				V4L2_CAP_STREAMING;
+
+	return 0;
+}
+
+static int pxp_g_fbuf(struct file *file, void *priv,
+			struct v4l2_framebuffer *fb)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	memset(fb, 0, sizeof(*fb));
+
+	fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
+			 V4L2_FBUF_CAP_CHROMAKEY |
+			 V4L2_FBUF_CAP_LOCAL_ALPHA |
+			 V4L2_FBUF_CAP_GLOBAL_ALPHA;
+
+	if (pxp->global_alpha_state)
+		fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA;
+	if (pxp->local_alpha_state)
+		fb->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
+	if (pxp->s1_chromakey_state)
+		fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
+
+	return 0;
+}
+
+static int pxp_s_fbuf(struct file *file, void *priv,
+			struct v4l2_framebuffer *fb)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	pxp->overlay_state =
+		(fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0;
+	pxp->global_alpha_state =
+		(fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0;
+	pxp->local_alpha_state =
+		(fb->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) != 0;
+	/* Global alpha overrides local alpha if both are requested */
+	if (pxp->global_alpha_state && pxp->local_alpha_state)
+		pxp->local_alpha_state = 0;
+	pxp->s1_chromakey_state =
+		(fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0;
+
+	pxp_set_olparam(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+
+	return 0;
+}
+
+static int pxp_g_crop(struct file *file, void *fh,
+			struct v4l2_crop *c)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
+		return -EINVAL;
+
+	c->c.left = pxp->drect.left;
+	c->c.top = pxp->drect.top;
+	c->c.width = pxp->drect.width;
+	c->c.height = pxp->drect.height;
+
+	return 0;
+}
+
+static int pxp_s_crop(struct file *file, void *fh,
+			struct v4l2_crop *c)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int l = c->c.left;
+	int t = c->c.top;
+	int w = c->c.width;
+	int h = c->c.height;
+	int fbw = pxp->fb.fmt.width;
+	int fbh = pxp->fb.fmt.height;
+
+	if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
+		return -EINVAL;
+
+	/* Constrain parameters to FB limits */
+	w = min(w, fbw);
+	w = max(w, PXP_MIN_PIX);
+	h = min(h, fbh);
+	h = max(h, PXP_MIN_PIX);
+	if ((l + w) > fbw)
+		l = 0;
+	if ((t + h) > fbh)
+		t = 0;
+
+	/* Round up values to PxP pixel block */
+	l = roundup(l, PXP_MIN_PIX);
+	t = roundup(t, PXP_MIN_PIX);
+	w = roundup(w, PXP_MIN_PIX);
+	h = roundup(h, PXP_MIN_PIX);
+
+	pxp->drect.left = l;
+	pxp->drect.top = t;
+	pxp->drect.width = w;
+	pxp->drect.height = h;
+
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_scaling(pxp);
+
+	return 0;
+}
+
+static int pxp_queryctrl(struct file *file, void *priv,
+			 struct v4l2_queryctrl *qc)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (qc->id && qc->id == pxp_controls[i].id) {
+			memcpy(qc, &(pxp_controls[i]), sizeof(*qc));
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
+static int pxp_g_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *vc)
+{
+	int i;
+
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (vc->id == pxp_controls[i].id)
+			return pxp_get_cstate(pxp, vc);
+
+	return -EINVAL;
+}
+
+static int pxp_s_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *vc)
+{
+	int i;
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
+		if (vc->id == pxp_controls[i].id) {
+			if (vc->value < pxp_controls[i].minimum ||
+			    vc->value > pxp_controls[i].maximum)
+				return -ERANGE;
+			return pxp_set_cstate(pxp, vc);
+		}
+
+	return -EINVAL;
+}
+
+void pxp_release(struct video_device *vfd)
+{
+	struct pxps *pxp = video_get_drvdata(vfd);
+
+	spin_lock(&pxp->lock);
+	video_device_release(vfd);
+	spin_unlock(&pxp->lock);
+}
+
+static int pxp_hw_init(struct pxps *pxp)
+{
+	struct fb_var_screeninfo var;
+	struct fb_fix_screeninfo fix;
+	int err;
+
+	err = stmp3xxxfb_get_info(&var, &fix);
+	if (err)
+		return err;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, HW_PXP_CTRL_ADDR);
+
+	/* Config defaults */
+	pxp->active = NULL;
+
+	pxp->s0_fmt = &pxp_s0_formats[0];
+	pxp->drect.left = pxp->srect.left = 0;
+	pxp->drect.top = pxp->srect.top = 0;
+	pxp->drect.width = pxp->srect.width = pxp->s0_width = var.xres;
+	pxp->drect.height = pxp->srect.height = pxp->s0_height = var.yres;
+	pxp->s0_bgcolor = 0;
+
+	pxp->output = 0;
+	err = pxp_set_fbinfo(pxp);
+	if (err)
+		return err;
+
+	pxp->scaling = 0;
+	pxp->hflip = 0;
+	pxp->vflip = 0;
+	pxp->rotate = 0;
+	pxp->yuv = 0;
+
+	pxp->overlay_state = 0;
+	pxp->global_alpha_state = 0;
+	pxp->global_alpha = 0;
+	pxp->local_alpha_state = 0;
+	pxp->s1_chromakey_state = 0;
+	pxp->s1_chromakey = -1;
+	pxp->s0_chromakey = -1;
+
+	/* Write default h/w config */
+	pxp_set_ctrl(pxp);
+	pxp_set_s0param(pxp);
+	pxp_set_s0crop(pxp);
+	pxp_set_oln(pxp);
+	pxp_set_olparam(pxp);
+	pxp_set_s0colorkey(pxp);
+	pxp_set_s1colorkey(pxp);
+	pxp_set_csc(pxp);
+
+	return 0;
+}
+
+static int pxp_open(struct file *file)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret = 0;
+
+	mutex_lock(&pxp->mutex);
+	pxp->users++;
+
+	if (pxp->users > 1) {
+		pxp->users--;
+		ret = -EBUSY;
+		goto out;
+	}
+out:
+	mutex_unlock(&pxp->mutex);
+	if (ret)
+		return ret;
+
+	pxp->next_queue_ended = 0;
+	pxp->workqueue = create_singlethread_workqueue("pxp");
+
+	videobuf_queue_dma_contig_init(&pxp->s0_vbq,
+				&pxp_vbq_ops,
+				&pxp->pdev->dev,
+				&pxp->lock,
+				V4L2_BUF_TYPE_VIDEO_OUTPUT,
+				V4L2_FIELD_NONE,
+				sizeof(struct pxp_buffer),
+				pxp);
+
+	return 0;
+}
+
+static int pxp_close(struct file *file)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+
+	if (pxp->workqueue)
+		destroy_workqueue(pxp->workqueue);
+
+	videobuf_stop(&pxp->s0_vbq);
+	videobuf_mmap_free(&pxp->s0_vbq);
+	pxp->active = NULL;
+
+	mutex_lock(&pxp->mutex);
+	pxp->users--;
+	mutex_unlock(&pxp->mutex);
+
+	return 0;
+}
+
+static int pxp_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct pxps *pxp = video_get_drvdata(video_devdata(file));
+	int ret;
+
+	ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma);
+
+	return ret;
+}
+
+static const struct v4l2_file_operations pxp_fops = {
+	.owner		= THIS_MODULE,
+	.open		= pxp_open,
+	.release	= pxp_close,
+	.ioctl		= video_ioctl2,
+	.mmap		= pxp_mmap,
+};
+
+static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
+	.vidioc_querycap		= pxp_querycap,
+
+	.vidioc_reqbufs			= pxp_reqbufs,
+	.vidioc_querybuf		= pxp_querybuf,
+	.vidioc_qbuf			= pxp_qbuf,
+	.vidioc_dqbuf			= pxp_dqbuf,
+
+	.vidioc_streamon		= pxp_streamon,
+	.vidioc_streamoff		= pxp_streamoff,
+
+	.vidioc_enum_output		= pxp_enumoutput,
+	.vidioc_g_output		= pxp_g_output,
+	.vidioc_s_output		= pxp_s_output,
+
+	.vidioc_enum_fmt_vid_out	= pxp_enum_fmt_video_output,
+	.vidioc_try_fmt_vid_out		= pxp_try_fmt_video_output,
+	.vidioc_g_fmt_vid_out		= pxp_g_fmt_video_output,
+	.vidioc_s_fmt_vid_out		= pxp_s_fmt_video_output,
+
+	.vidioc_try_fmt_vid_out_overlay	= pxp_try_fmt_output_overlay,
+	.vidioc_g_fmt_vid_out_overlay	= pxp_g_fmt_output_overlay,
+	.vidioc_s_fmt_vid_out_overlay	= pxp_s_fmt_output_overlay,
+
+	.vidioc_g_fbuf			= pxp_g_fbuf,
+	.vidioc_s_fbuf			= pxp_s_fbuf,
+
+	.vidioc_g_crop			= pxp_g_crop,
+	.vidioc_s_crop			= pxp_s_crop,
+
+	.vidioc_queryctrl		= pxp_queryctrl,
+	.vidioc_g_ctrl			= pxp_g_ctrl,
+	.vidioc_s_ctrl			= pxp_s_ctrl,
+};
+
+static const struct video_device pxp_template = {
+	.name				= "PxP",
+	.vfl_type 			= V4L2_CAP_VIDEO_OUTPUT |
+					  V4L2_CAP_VIDEO_OVERLAY |
+					  V4L2_CAP_STREAMING,
+	.fops				= &pxp_fops,
+	.release			= pxp_release,
+	.minor				= -1,
+	.ioctl_ops			= &pxp_ioctl_ops,
+};
+
+static irqreturn_t pxp_irq(int irq, void *dev_id)
+{
+	struct pxps *pxp = (struct pxps *)dev_id;
+	struct videobuf_buffer *vb;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pxp->lock, flags);
+
+	__raw_writel(BM_PXP_STAT_IRQ, HW_PXP_STAT_CLR_ADDR);
+
+	if (list_empty(&pxp->outq)) {
+		pr_warning("irq: outq empty!!!\n");
+		goto out;
+	}
+
+	vb = list_entry(pxp->outq.next,
+				struct videobuf_buffer,
+				queue);
+	list_del_init(&vb->queue);
+
+	vb->state = VIDEOBUF_DONE;
+	do_gettimeofday(&vb->ts);
+	vb->field_count++;
+
+	wake_up(&vb->done);
+	wake_up(&pxp->done);
+out:
+	spin_unlock_irqrestore(&pxp->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int pxp_notifier_callback(struct notifier_block *self,
+		       unsigned long event, void *data)
+{
+	struct pxps *pxp = container_of(self, struct pxps, nb);
+
+	switch (event) {
+	case STMP3XXX_LCDIF_PANEL_INIT:
+		pxp_set_fbinfo(pxp);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int pxp_probe(struct platform_device *pdev)
+{
+	struct pxps *pxp;
+	struct resource *res;
+	int irq;
+	int err = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!res || irq < 0) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
+	if (!pxp) {
+		dev_err(&pdev->dev, "failed to allocate control object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	dev_set_drvdata(&pdev->dev, pxp);
+	pxp->res = res;
+	pxp->irq = irq;
+
+	pxp->regs_virt = dma_alloc_coherent(NULL,
+				PAGE_ALIGN(sizeof(struct pxp_registers)),
+				&pxp->regs_phys, GFP_KERNEL);
+	if (pxp->regs_virt == NULL) {
+		dev_err(&pdev->dev, "failed to allocate pxp_register object\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	init_waitqueue_head(&pxp->done);
+
+	INIT_WORK(&pxp->work, pxp_next_handle);
+	INIT_LIST_HEAD(&pxp->outq);
+	INIT_LIST_HEAD(&pxp->nextq);
+	spin_lock_init(&pxp->lock);
+	mutex_init(&pxp->mutex);
+
+	if (!request_mem_region(res->start, res->end - res->start + 1,
+				PXP_DRIVER_NAME)) {
+		err = -EBUSY;
+		goto freepxp;
+	}
+
+	pxp->regs = (void __iomem *)res->start; /* it is already ioremapped */
+	pxp->pdev = pdev;
+
+	err = request_irq(pxp->irq, pxp_irq, 0, PXP_DRIVER_NAME, pxp);
+
+	if (err) {
+		dev_err(&pdev->dev, "interrupt register failed\n");
+		goto release;
+	}
+
+	pxp->vdev = video_device_alloc();
+	if (!pxp->vdev) {
+		dev_err(&pdev->dev, "video_device_alloc() failed\n");
+		err = -ENOMEM;
+		goto freeirq;
+	}
+
+	memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template));
+	video_set_drvdata(pxp->vdev, pxp);
+
+	err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0);
+	if (err) {
+		dev_err(&pdev->dev, "failed to register video device\n");
+		goto freevdev;
+	}
+
+	err = pxp_hw_init(pxp);
+	if (err) {
+		dev_err(&pdev->dev, "failed to initialize hardware\n");
+		goto freevdev;
+	}
+
+	pxp->nb.notifier_call = pxp_notifier_callback,
+	stmp3xxx_lcdif_register_client(&pxp->nb);
+	dev_info(&pdev->dev, "initialized\n");
+
+exit:
+	return err;
+
+freevdev:
+	video_device_release(pxp->vdev);
+
+freeirq:
+	free_irq(pxp->irq, pxp);
+
+release:
+	release_mem_region(res->start, res->end - res->start + 1);
+
+freepxp:
+	kfree(pxp);
+
+	return err;
+}
+
+static int __devexit pxp_remove(struct platform_device *pdev)
+{
+	struct pxps *pxp = platform_get_drvdata(pdev);
+
+	stmp3xxx_lcdif_unregister_client(&pxp->nb);
+	video_unregister_device(pxp->vdev);
+	video_device_release(pxp->vdev);
+
+	if (pxp->regs_virt)
+		dma_free_coherent(0, PAGE_ALIGN(sizeof(struct pxp_registers)),
+				pxp->regs_virt, pxp->regs_phys);
+	kfree(pxp->outb);
+	kfree(pxp);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pxp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+
+	while (__raw_readl(HW_PXP_CTRL_ADDR) & BM_PXP_CTRL_ENABLE)
+		;
+
+	for (i = 0; i < REGS1_NUMS; i++)
+		regs1[i] = __raw_readl(HW_PXP_CTRL_ADDR + REG_OFFSET * i);
+
+	for (i = 0; i < REGS2_NUMS; i++)
+		regs2[i] = __raw_readl(HW_PXP_PAGETABLE_ADDR + REG_OFFSET * i);
+
+	for (i = 0; i < REGS3_NUMS; i++)
+		regs3[i] = __raw_readl(HW_PXP_OLn_ADDR(0) + REG_OFFSET * i);
+
+	__raw_writel(BM_PXP_CTRL_SFTRST, HW_PXP_CTRL_ADDR);
+
+	return 0;
+}
+
+static int pxp_resume(struct platform_device *pdev)
+{
+	int i;
+
+	/* Pull PxP out of reset */
+	__raw_writel(0, HW_PXP_CTRL_ADDR);
+
+	for (i = 0; i < REGS1_NUMS; i++)
+		__raw_writel(regs1[i], HW_PXP_CTRL_ADDR + REG_OFFSET * i);
+
+	for (i = 0; i < REGS2_NUMS; i++)
+		__raw_writel(regs2[i], HW_PXP_PAGETABLE_ADDR + REG_OFFSET * i);
+
+	for (i = 0; i < REGS3_NUMS; i++)
+		__raw_writel(regs3[i], HW_PXP_OLn_ADDR(0) + REG_OFFSET * i);
+
+	return 0;
+}
+#else
+#define	pxp_suspend	NULL
+#define	pxp_resume	NULL
+#endif
+
+static struct platform_driver pxp_driver = {
+	.driver 	= {
+		.name	= PXP_DRIVER_NAME,
+	},
+	.probe		= pxp_probe,
+	.remove		= __exit_p(pxp_remove),
+	.suspend	= pxp_suspend,
+	.resume		= pxp_resume,
+};
+
+
+static int __devinit pxp_init(void)
+{
+	return platform_driver_register(&pxp_driver);
+}
+
+static void __exit pxp_exit(void)
+{
+	platform_driver_unregister(&pxp_driver);
+}
+
+module_init(pxp_init);
+module_exit(pxp_exit);
+
+MODULE_DESCRIPTION("STMP37xx PxP driver");
+MODULE_AUTHOR("Matt Porter <mporter@embeddedalley.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/pxp.h b/drivers/media/video/pxp.h
new file mode 100644
index 000000000000..11b41dcc6ade
--- /dev/null
+++ b/drivers/media/video/pxp.h
@@ -0,0 +1,130 @@
+/*
+ * Freescale STMP378X PxP driver
+ *
+ * Author: Matt Porter <mporter@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+struct pxp_overlay_registers {
+	u32 ol;
+	u32 olsize;
+	u32 olparam;
+	u32 olparam2;
+};
+
+/* Registers feed for PXP_NEXT */
+struct pxp_registers {
+	u32 ctrl;
+	u32 rgbbuf;
+	u32 rgbbuf2;
+	u32 rgbsize;
+	u32 s0buf;
+	u32 s0ubuf;
+	u32 s0vbuf;
+	u32 s0param;
+	u32 s0background;
+	u32 s0crop;
+	u32 s0scale;
+	u32 s0offset;
+	u32 s0colorkeylow;
+	u32 s0colorkeyhigh;
+	u32 olcolorkeylow;
+	u32 olcolorkeyhigh;
+
+	struct pxp_overlay_registers ol0;
+	struct pxp_overlay_registers ol1;
+	struct pxp_overlay_registers ol2;
+	struct pxp_overlay_registers ol3;
+	struct pxp_overlay_registers ol4;
+	struct pxp_overlay_registers ol5;
+	struct pxp_overlay_registers ol6;
+	struct pxp_overlay_registers ol7;
+};
+
+struct pxp_buffer {
+	/* Must be first! */
+	struct videobuf_buffer vb;
+	struct list_head queue;
+};
+
+struct pxps {
+	struct platform_device *pdev;
+	struct resource *res;
+	int irq;
+	void __iomem *regs;
+
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	spinlock_t lock;
+	struct mutex mutex;
+	int users;
+
+	struct video_device *vdev;
+
+	struct videobuf_queue s0_vbq;
+	struct videobuf_buffer *active;
+	struct list_head outq;
+	struct list_head nextq;
+
+	int output;
+	u32 *outb;
+	dma_addr_t outb_phys;
+
+	/* Current S0 configuration */
+	struct pxp_data_format *s0_fmt;
+	u32 s0_width;
+	u32 s0_height;
+	u32 s0_bgcolor;
+	u32 s0_chromakey;
+
+	struct v4l2_framebuffer fb;
+	struct v4l2_rect drect;
+	struct v4l2_rect srect;
+
+	/* Transformation support */
+	int scaling;
+	int hflip;
+	int vflip;
+	int rotate;
+	int yuv;
+
+	/* Output overlay support */
+	int overlay_state;
+	int global_alpha_state;
+	u8  global_alpha;
+	int local_alpha_state;
+	int s1_chromakey_state;
+	u32 s1_chromakey;
+
+	/* PXP_NEXT */
+	u32 regs_phys;
+	struct pxp_registers *regs_virt;
+	wait_queue_head_t done;
+	int next_queue_ended;
+
+	/* notifier for PXP when fb changed */
+	struct notifier_block nb;
+};
+
+struct pxp_data_format {
+	char *name;
+	unsigned int bpp;
+	u32 fourcc;
+	enum v4l2_colorspace colorspace;
+	u32 ctrl_s0_fmt;
+};
+
+extern int stmp3xxxfb_get_info(struct fb_var_screeninfo *var,
+				struct fb_fix_screeninfo *fix);
+extern void stmp3xxxfb_cfg_pxp(int enable, dma_addr_t pxp_phys);
diff --git a/drivers/media/video/videobuf-dma-contig.c b/drivers/media/video/videobuf-dma-contig.c
index d09ce83a9429..dc4f32bbd83d 100644
--- a/drivers/media/video/videobuf-dma-contig.c
+++ b/drivers/media/video/videobuf-dma-contig.c
@@ -319,7 +319,7 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
 
 	mem->size = PAGE_ALIGN(q->bufs[first]->bsize);
 	mem->vaddr = dma_alloc_coherent(q->dev, mem->size,
-					&mem->dma_handle, GFP_KERNEL);
+					&mem->dma_handle, GFP_DMA);
 	if (!mem->vaddr) {
 		dev_err(q->dev, "dma_alloc_coherent size %ld failed\n",
 			mem->size);
@@ -333,7 +333,7 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q,
 	size = vma->vm_end - vma->vm_start;
 	size = (size < mem->size) ? size : mem->size;
 
-	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot);
 	retval = remap_pfn_range(vma, vma->vm_start,
 				 mem->dma_handle >> PAGE_SHIFT,
 				 size, vma->vm_page_prot);
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index fe24079387c5..66a1280b87ec 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -1466,7 +1466,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
 		}
 	}
 
-	wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
+	/*mask gpio and rtc interrupt*/
+	wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x50);
 
 	wm8350_client_dev_register(wm8350, "wm8350-codec",
 				   &(wm8350->codec.pdev));
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 68ab39d7cb35..281b61b3b5f3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -233,6 +233,11 @@ config ISL29003
 	  This driver can also be built as a module.  If so, the module
 	  will be called isl29003.
 
+config MXS_PERSISTENT
+	tristate "MX23/MX28 persistent bit"
+	depends on ARCH_MXS
+	default y
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 36f733cd60e6..03dd5ee05ce2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,5 +20,6 @@ obj-$(CONFIG_SGI_GRU)		+= sgi-gru/
 obj-$(CONFIG_HP_ILO)		+= hpilo.o
 obj-$(CONFIG_ISL29003)		+= isl29003.o
 obj-$(CONFIG_C2PORT)		+= c2port/
+obj-$(CONFIG_MXS_PERSISTENT)	+= mxs-persistent.o
 obj-y				+= eeprom/
 obj-y				+= cb710/
diff --git a/drivers/misc/mxs-persistent.c b/drivers/misc/mxs-persistent.c
new file mode 100644
index 000000000000..415010c6b810
--- /dev/null
+++ b/drivers/misc/mxs-persistent.c
@@ -0,0 +1,270 @@
+/*
+ * Freescale STMP378X Persistent bits manipulation driver
+ *
+ * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysdev.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/sysfs.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <mach/device.h>
+
+#include <mach/regs-rtc.h>
+
+struct mxs_persistent_data {
+	struct device *dev;
+	struct mxs_platform_persistent_data *pdata;
+	int count;
+	struct attribute_group attr_group;
+	unsigned int base;
+	/* attribute ** follow */
+	/* device_attribute follow */
+};
+
+#define pd_attribute_ptr(x) \
+	((struct attribute **)((x) + 1))
+#define pd_device_attribute_ptr(x) \
+	((struct device_attribute *)(pd_attribute_ptr(x) + (x)->count + 1))
+
+static inline u32 persistent_reg_read(struct mxs_persistent_data *pdata,
+						int reg)
+{
+	u32 msk;
+
+	/* wait for stable value */
+	msk = BF_RTC_STAT_STALE_REGS((0x1 << reg));
+	while (__raw_readl(pdata->base + HW_RTC_STAT) & msk)
+		cpu_relax();
+
+	return __raw_readl(pdata->base + 0x60 + (reg * 0x10));
+}
+
+static inline void persistent_reg_wait_settle(struct mxs_persistent_data *pdata
+				, int reg)
+{
+	u32 msk;
+
+	/* wait until the change is propagated */
+	msk = BF_RTC_STAT_NEW_REGS((0x1 << reg));
+	while (__raw_readl(pdata->base + HW_RTC_STAT) & msk)
+		cpu_relax();
+}
+
+static inline void persistent_reg_write(struct mxs_persistent_data *pdata,
+				u32 val, int reg)
+{
+	__raw_writel(val, pdata->base + 0x60 + (reg * 0x10));
+	persistent_reg_wait_settle(pdata, reg);
+}
+
+static inline void persistent_reg_set(struct mxs_persistent_data *pdata,
+				u32 val, int reg)
+{
+	__raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0x4);
+	persistent_reg_wait_settle(pdata, reg);
+}
+
+static inline void persistent_reg_clr(struct mxs_persistent_data *pdata,
+				u32 val, int reg)
+{
+	__raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0x8);
+	persistent_reg_wait_settle(pdata, reg);
+}
+
+static inline void persistent_reg_tog(struct mxs_persistent_data *pdata,
+				u32 val, int reg)
+{
+	__raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0xc);
+	persistent_reg_wait_settle(pdata, reg);
+}
+
+static ssize_t
+persistent_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct mxs_persistent_data *pd = platform_get_drvdata(pdev);
+	struct device_attribute *devattr = pd_device_attribute_ptr(pd);
+	const struct mxs_persistent_bit_config *pb;
+	int idx;
+	u32 val;
+
+	idx = attr - devattr;
+	if ((unsigned int)idx >= pd->count)
+		return -EINVAL;
+
+	pb = &pd->pdata->bit_config_tab[idx];
+
+	/* read value and shift */
+	val = persistent_reg_read(pd, pb->reg);
+	val >>= pb->start;
+	val &= (1 << pb->width) - 1;
+
+	return sprintf(buf, "%u\n", val);
+}
+
+static ssize_t
+persistent_store(struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct mxs_persistent_data *pd = platform_get_drvdata(pdev);
+	struct device_attribute *devattr = pd_device_attribute_ptr(pd);
+	const struct mxs_persistent_bit_config *pb;
+	int idx, r;
+	unsigned long val, msk;
+
+	idx = attr - devattr;
+	if ((unsigned int)idx >= pd->count)
+		return -EINVAL;
+
+	pb = &pd->pdata->bit_config_tab[idx];
+
+	/* get value to write */
+	r = strict_strtoul(buf, 10, &val);
+	if (r != 0)
+		return r;
+
+	/* verify it fits */
+	if ((unsigned int)val > (1 << pb->width) - 1)
+		return -EINVAL;
+
+	/* lockless update, first clear the area */
+	msk = ((1 << pb->width) - 1) << pb->start;
+	persistent_reg_clr(pd, msk, pb->reg);
+
+	/* shift into position */
+	val <<= pb->start;
+	persistent_reg_set(pd, val, pb->reg);
+
+	return count;
+}
+
+
+static int __devinit mxs_persistent_probe(struct platform_device *pdev)
+{
+	struct mxs_persistent_data *pd;
+	struct mxs_platform_persistent_data *pdata;
+	struct resource *res;
+	const struct mxs_persistent_bit_config *pb;
+	struct attribute **attr;
+	struct device_attribute *devattr;
+	int i, cnt, size;
+	int err;
+
+	pdata = pdev->dev.platform_data;
+	if (pdata == NULL)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL)
+		return -ENODEV;
+
+	cnt = pdata->bit_config_cnt;
+	size = sizeof(*pd) +
+		 (cnt + 1) * sizeof(struct atrribute *) +
+		 cnt * sizeof(struct device_attribute);
+	pd = kzalloc(size, GFP_KERNEL);
+	if (pd == NULL)
+		return -ENOMEM;
+	pd->dev = &pdev->dev;
+	pd->pdata = pdata;
+	pd->base =  (unsigned int)IO_ADDRESS(res->start);
+
+	platform_set_drvdata(pdev, pd);
+	pd->count = cnt;
+	attr = pd_attribute_ptr(pd);
+	devattr = pd_device_attribute_ptr(pd);
+
+	/* build the attributes structures */
+	pd->attr_group.attrs = attr;
+	pb = pdata->bit_config_tab;
+	for (i = 0; i < cnt; i++) {
+		devattr[i].attr.name = pb[i].name;
+		devattr[i].attr.mode = S_IWUSR | S_IRUGO;
+		devattr[i].show = persistent_show;
+		devattr[i].store = persistent_store;
+		attr[i] = &devattr[i].attr;
+	}
+
+	err = sysfs_create_group(&pdev->dev.kobj, &pd->attr_group);
+	if (err != 0) {
+		platform_set_drvdata(pdev, NULL);
+		kfree(pd);
+		return err;
+	}
+
+	return 0;
+}
+
+static int __devexit mxs_persistent_remove(struct platform_device *pdev)
+{
+	struct mxs_persistent_data *pd;
+
+	pd = platform_get_drvdata(pdev);
+	sysfs_remove_group(&pdev->dev.kobj, &pd->attr_group);
+	platform_set_drvdata(pdev, NULL);
+	kfree(pd);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int
+mxs_persistent_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int mxs_persistent_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define mxs_persistent_suspend	NULL
+#define	mxs_persistent_resume	NULL
+#endif
+
+static struct platform_driver mxs_persistent_driver = {
+	.probe		= mxs_persistent_probe,
+	.remove		= __exit_p(mxs_persistent_remove),
+	.suspend	= mxs_persistent_suspend,
+	.resume		= mxs_persistent_resume,
+	.driver		= {
+		.name   = "mxs-persistent",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init mxs_persistent_init(void)
+{
+	return platform_driver_register(&mxs_persistent_driver);
+}
+
+static void __exit mxs_persistent_exit(void)
+{
+	platform_driver_unregister(&mxs_persistent_driver);
+}
+
+MODULE_AUTHOR("Pantelis Antoniou <pantelis@embeddedalley.com>");
+MODULE_DESCRIPTION("Persistent bits user-access driver");
+MODULE_LICENSE("GPL");
+
+module_init(mxs_persistent_init);
+module_exit(mxs_persistent_exit);
diff --git a/drivers/mmc/card/Kconfig b/drivers/mmc/card/Kconfig
index 3f2a912659af..10ba9a035a58 100644
--- a/drivers/mmc/card/Kconfig
+++ b/drivers/mmc/card/Kconfig
@@ -50,3 +50,15 @@ config MMC_TEST
 
 	  This driver is only of interest to those developing or
 	  testing a host driver. Most people should say N here.
+
+config SDIO_UNIFI_FS
+	tristate "UniFi SDIO glue for Freescale MMC/SDIO"
+	depends on (MMC_MXC || MMC_IMX_ESDHCI)
+	depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS)
+	help
+	  This provides an interface between the CSR UniFi WiFi
+	  driver and the Freescale MMC/SDIO interface.
+	  If you have a MXC platform with a UniFi WiFi chip,
+	  say M here.
+
+	  If unsure, say N.
diff --git a/drivers/mmc/card/Makefile b/drivers/mmc/card/Makefile
index 0d407514f67d..bbcf742d0ea1 100644
--- a/drivers/mmc/card/Makefile
+++ b/drivers/mmc/card/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_MMC_TEST)		+= mmc_test.o
 
 obj-$(CONFIG_SDIO_UART)		+= sdio_uart.o
 
+obj-$(CONFIG_SDIO_UNIFI_FS)	+= unifi_fs/
diff --git a/drivers/mmc/card/unifi_fs/Makefile b/drivers/mmc/card/unifi_fs/Makefile
new file mode 100644
index 000000000000..381d4a2d1fd5
--- /dev/null
+++ b/drivers/mmc/card/unifi_fs/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SDIO_UNIFI_FS) = unifi_fs.o
+unifi_fs-objs = fs_lx.o
diff --git a/drivers/mmc/card/unifi_fs/fs_lx.c b/drivers/mmc/card/unifi_fs/fs_lx.c
new file mode 100644
index 000000000000..09972e94ea27
--- /dev/null
+++ b/drivers/mmc/card/unifi_fs/fs_lx.c
@@ -0,0 +1,681 @@
+/*
+ * fs_lx.c - Freescale SDIO glue module for UniFi.
+ *
+ * Copyright (C) 2008 Cambridge Silicon Radio Ltd.
+ *
+ *  Important:
+ *      This module does not support more than one device driver instances.
+ *
+ */
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/scatterlist.h>
+
+#include <linux/mmc/core.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <mach/mmc.h>
+#include <mach/gpio.h>
+
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include "fs_sdio_api.h"
+
+struct regulator_unifi {
+	struct regulator *reg_gpo1;
+	struct regulator *reg_gpo2;
+	struct regulator *reg_1v5_ana_bb;
+	struct regulator *reg_vdd_vpa;
+	struct regulator *reg_1v5_dd;
+};
+
+static struct sdio_driver sdio_unifi_driver;
+
+static int fs_sdio_probe(struct sdio_func *func,
+			 const struct sdio_device_id *id);
+static void fs_sdio_remove(struct sdio_func *func);
+static void fs_sdio_irq(struct sdio_func *func);
+static int fs_sdio_suspend(struct device *dev, pm_message_t state);
+static int fs_sdio_resume(struct device *dev);
+
+/* Globals to store the context to this module and the device driver */
+static struct sdio_dev *available_sdio_dev;
+static struct fs_driver *available_driver;
+struct mxc_unifi_platform_data *plat_data;
+
+extern void mxc_mmc_force_detect(int id);
+
+enum sdio_cmd_direction {
+	CMD_READ,
+	CMD_WRITE,
+};
+
+static int fsl_io_rw_direct(struct mmc_card *card, int write, unsigned fn,
+	unsigned addr, u8 in, u8 *out)
+{
+	struct mmc_command cmd;
+	int err;
+
+	BUG_ON(!card);
+	BUG_ON(fn > 7);
+
+	memset(&cmd, 0, sizeof(struct mmc_command));
+
+	cmd.opcode = SD_IO_RW_DIRECT;
+	cmd.arg = write ? 0x80000000 : 0x00000000;
+	cmd.arg |= fn << 28;
+	cmd.arg |= (write && out) ? 0x08000000 : 0x00000000;
+	cmd.arg |= addr << 9;
+	cmd.arg |= in;
+	cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
+
+	err = mmc_wait_for_cmd(card->host, &cmd, 0);
+	if (err)
+		return err;
+
+	if (mmc_host_is_spi(card->host)) {
+		/* host driver already reported errors */
+	} else {
+		if (cmd.resp[0] & R5_ERROR)
+			return -EIO;
+		if (cmd.resp[0] & R5_FUNCTION_NUMBER)
+			return -EINVAL;
+		if (cmd.resp[0] & R5_OUT_OF_RANGE)
+			return -ERANGE;
+	}
+
+	if (out) {
+		if (mmc_host_is_spi(card->host))
+			*out = (cmd.resp[0] >> 8) & 0xFF;
+		else
+			*out = cmd.resp[0] & 0xFF;
+	}
+
+	return 0;
+}
+
+
+int fs_sdio_readb(struct sdio_dev *fdev, int funcnum, unsigned long addr,
+		  unsigned char *pdata)
+{
+	int err;
+	char val;
+
+	sdio_claim_host(fdev->func);
+	if (funcnum == 0)
+		val = sdio_f0_readb(fdev->func, (unsigned int)addr, &err);
+	else
+		val = sdio_readb(fdev->func, (unsigned int)addr, &err);
+	sdio_release_host(fdev->func);
+	if (!err)
+		*pdata = val;
+	else
+		printk(KERN_ERR "fs_lx: readb error,fun=%d,addr=%d,data=%d,"
+		       "err=%d\n", funcnum, (int)addr, *pdata, err);
+
+	return err;
+}
+EXPORT_SYMBOL(fs_sdio_readb);
+
+int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum, unsigned long addr,
+		   unsigned char data)
+{
+	int err;
+
+	sdio_claim_host(fdev->func);
+	if (funcnum == 0)
+		err = fsl_io_rw_direct(fdev->func->card, 1, 0, addr,
+				       data, NULL);
+	else
+		sdio_writeb(fdev->func, data, (unsigned int)addr, &err);
+	sdio_release_host(fdev->func);
+
+	if (err)
+		printk(KERN_ERR "fs_lx: writeb error,fun=%d,addr=%d,data=%d,"
+		       "err=%d\n", funcnum, (int)addr, data, err);
+	return err;
+}
+EXPORT_SYMBOL(fs_sdio_writeb);
+
+int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum, unsigned long addr,
+		     unsigned char *pdata, unsigned int count, int direction)
+{
+	int err;
+
+	sdio_claim_host(fdev->func);
+	if (direction == CMD_READ)
+		err = sdio_memcpy_fromio(fdev->func, pdata, addr, count);
+	else
+		err = sdio_memcpy_toio(fdev->func, addr, pdata, count);
+	sdio_release_host(fdev->func);
+
+	return err;
+}
+EXPORT_SYMBOL(fs_sdio_block_rw);
+
+int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable)
+{
+	struct mmc_host *host = fdev->func->card->host;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fdev->lock, flags);
+	if (enable) {
+		if (!fdev->int_enabled) {
+		fdev->int_enabled = 1;
+		host->ops->enable_sdio_irq(host, 1);
+		}
+	} else {
+		if (fdev->int_enabled) {
+		host->ops->enable_sdio_irq(host, 0);
+		fdev->int_enabled = 0;
+		}
+	}
+	spin_unlock_irqrestore(&fdev->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(fs_sdio_enable_interrupt);
+
+int fs_sdio_disable(struct sdio_dev *fdev)
+{
+	int err;
+	sdio_claim_host(fdev->func);
+	err = sdio_disable_func(fdev->func);
+	sdio_release_host(fdev->func);
+	if (err)
+		printk(KERN_ERR "fs_lx:fs_sdio_disable error,err=%d\n", err);
+	return err;
+}
+EXPORT_SYMBOL(fs_sdio_disable);
+
+int fs_sdio_enable(struct sdio_dev *fdev)
+{
+	int err = 0;
+
+	sdio_claim_host(fdev->func);
+	err = sdio_disable_func(fdev->func);
+	err = sdio_enable_func(fdev->func);
+	sdio_release_host(fdev->func);
+	if (err)
+		printk(KERN_ERR "fs_lx:fs_sdio_enable error,err=%d\n", err);
+	return err;
+}
+EXPORT_SYMBOL(fs_sdio_enable);
+
+int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz)
+{
+	struct mmc_card *card = fdev->func->card;
+
+	/* Respect the host controller's min-max. */
+	max_khz *= 1000;
+	if (max_khz < card->host->f_min)
+		max_khz = card->host->f_min;
+	if (max_khz > card->host->f_max)
+		max_khz = card->host->f_max;
+
+	card->host->ios.clock = max_khz;
+	card->host->ops->set_ios(card->host, &card->host->ios);
+
+	return max_khz / 1000;
+}
+EXPORT_SYMBOL(fs_sdio_set_max_clock_speed);
+
+int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz)
+{
+	return 0;
+}
+EXPORT_SYMBOL(fs_sdio_set_block_size);
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Turn on the power of WIFI card
+ *
+ * ---------------------------------------------------------------------------
+ */
+static void fs_unifi_power_on(void)
+{
+	struct regulator_unifi *reg_unifi;
+	unsigned int tmp;
+
+	reg_unifi = plat_data->priv;
+
+	if (reg_unifi->reg_gpo1)
+		regulator_enable(reg_unifi->reg_gpo1);
+	if (reg_unifi->reg_gpo2)
+		regulator_enable(reg_unifi->reg_gpo2);
+
+	if (plat_data->enable)
+		plat_data->enable(1);
+
+	if (reg_unifi->reg_1v5_ana_bb) {
+		regulator_set_voltage(reg_unifi->reg_1v5_ana_bb,
+					1500000, 1500000);
+		regulator_enable(reg_unifi->reg_1v5_ana_bb);
+	}
+	if (reg_unifi->reg_vdd_vpa) {
+		tmp = regulator_get_voltage(reg_unifi->reg_vdd_vpa);
+		if (tmp < 3000000 || tmp > 3600000)
+			regulator_set_voltage(reg_unifi->reg_vdd_vpa,
+					      3000000, 3000000);
+		regulator_enable(reg_unifi->reg_vdd_vpa);
+	}
+	/* WL_1V5DD should come on last, 10ms after other supplies */
+	msleep(10);
+	if (reg_unifi->reg_1v5_dd) {
+		regulator_set_voltage(reg_unifi->reg_1v5_dd,
+					1500000, 1500000);
+		regulator_enable(reg_unifi->reg_1v5_dd);
+	}
+	msleep(10);
+}
+
+/*
+ * ---------------------------------------------------------------------------
+ *
+ * Turn off the power of WIFI card
+ *
+ * ---------------------------------------------------------------------------
+ */
+static void fs_unifi_power_off(void)
+{
+	struct regulator_unifi *reg_unifi;
+
+	reg_unifi = plat_data->priv;
+	if (reg_unifi->reg_1v5_dd)
+		regulator_disable(reg_unifi->reg_1v5_dd);
+	if (reg_unifi->reg_vdd_vpa)
+		regulator_disable(reg_unifi->reg_vdd_vpa);
+
+	if (reg_unifi->reg_1v5_ana_bb)
+		regulator_disable(reg_unifi->reg_1v5_ana_bb);
+
+	if (plat_data->enable)
+		plat_data->enable(0);
+
+	if (reg_unifi->reg_gpo2)
+		regulator_disable(reg_unifi->reg_gpo2);
+
+	if (reg_unifi->reg_gpo1)
+		regulator_disable(reg_unifi->reg_gpo1);
+}
+
+/* This should be made conditional on being slot 2 too - so we can
+ * use a plug in card in slot 1
+ */
+int fs_sdio_hard_reset(struct sdio_dev *fdev)
+{
+	return 0;
+}
+EXPORT_SYMBOL(fs_sdio_hard_reset);
+
+static const struct sdio_device_id fs_sdio_ids[] = {
+	{SDIO_DEVICE(0x032a, 0x0001)},
+	{ /* end: all zeroes */	},
+};
+
+static struct sdio_driver sdio_unifi_driver = {
+	.name = "fs_unifi",
+	.probe = fs_sdio_probe,
+	.remove = fs_sdio_remove,
+	.id_table = fs_sdio_ids,
+	.drv = {
+		.suspend = fs_sdio_suspend,
+		.resume	= fs_sdio_resume,
+	}
+};
+
+int fs_sdio_register_driver(struct fs_driver *driver)
+{
+	int ret, retry;
+
+	/* Switch us on, sdio device may exist if power is on by default. */
+	plat_data->hardreset(0);
+	if (available_sdio_dev)
+		mxc_mmc_force_detect(plat_data->host_id);
+	/* Wait for card removed */
+	for (retry = 0; retry < 100; retry++) {
+		if (!available_sdio_dev)
+			break;
+		msleep(100);
+	}
+	if (retry == 100)
+		printk(KERN_ERR "fs_sdio_register_driver: sdio device exists, "
+				"timeout for card removed");
+	fs_unifi_power_on();
+	plat_data->hardreset(1);
+	msleep(500);
+	mxc_mmc_force_detect(plat_data->host_id);
+	for (retry = 0; retry < 100; retry++) {
+		if (available_sdio_dev)
+			break;
+		msleep(50);
+	}
+	if (retry == 100)
+		printk(KERN_ERR "fs_sdio_register_driver: Timeout waiting"
+				" for card added\n");
+	/* Store the context to the device driver to the global */
+	available_driver = driver;
+
+	/*
+	 * If available_sdio_dev is not NULL, probe has been called,
+	 * so pass the probe to the registered driver
+	 */
+	if (available_sdio_dev) {
+		/* Store the context to the new device driver */
+		available_sdio_dev->driver = driver;
+
+		printk(KERN_INFO "fs_sdio_register_driver: Glue exists, add "
+		       "device driver and register IRQ\n");
+		driver->probe(available_sdio_dev);
+
+		/* Register the IRQ handler to the SDIO IRQ. */
+		sdio_claim_host(available_sdio_dev->func);
+		ret = sdio_claim_irq(available_sdio_dev->func, fs_sdio_irq);
+		sdio_release_host(available_sdio_dev->func);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(fs_sdio_register_driver);
+
+void fs_sdio_unregister_driver(struct fs_driver *driver)
+{
+	/*
+	 * If available_sdio_dev is not NULL, probe has been called,
+	 * so pass the remove to the registered driver to clean up.
+	 */
+	if (available_sdio_dev) {
+		struct mmc_host *host = available_sdio_dev->func->card->host;
+
+		printk(KERN_INFO "fs_sdio_unregister_driver: Glue exists, "
+		       "unregister IRQ and remove device driver\n");
+
+		/* Unregister the IRQ handler first. */
+		sdio_claim_host(available_sdio_dev->func);
+		sdio_release_irq(available_sdio_dev->func);
+		sdio_release_host(available_sdio_dev->func);
+
+		driver->remove(available_sdio_dev);
+
+		if (!available_sdio_dev->int_enabled) {
+			available_sdio_dev->int_enabled = 1;
+			host->ops->enable_sdio_irq(host, 1);
+		}
+
+		/* Invalidate the context to the device driver */
+		available_sdio_dev->driver = NULL;
+	}
+
+	/* invalidate the context to the device driver to the global */
+	available_driver = NULL;
+	/* Power down the UniFi */
+	fs_unifi_power_off();
+
+}
+EXPORT_SYMBOL(fs_sdio_unregister_driver);
+
+static void fs_sdio_irq(struct sdio_func *func)
+{
+	struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func);
+	if (fdev->driver) {
+		if (fdev->driver->card_int_handler)
+			fdev->driver->card_int_handler(fdev);
+	}
+}
+
+#ifdef CONFIG_PM
+static int fs_sdio_suspend(struct device *dev, pm_message_t state)
+{
+	struct sdio_dev *fdev = available_sdio_dev;
+
+	/* Pass event to the registered driver. */
+	if (fdev->driver)
+		if (fdev->driver->suspend)
+			fdev->driver->suspend(fdev, state);
+
+	return 0;
+}
+
+static int fs_sdio_resume(struct device *dev)
+{
+	struct sdio_dev *fdev = available_sdio_dev;
+
+	/* Pass event to the registered driver. */
+	if (fdev->driver)
+		if (fdev->driver->resume)
+			fdev->driver->resume(fdev);
+
+	return 0;
+}
+#else
+#define fs_sdio_suspend NULL
+#define fs_sdio_resume  NULL
+#endif
+
+static int fs_sdio_probe(struct sdio_func *func,
+			 const struct sdio_device_id *id)
+{
+	struct sdio_dev *fdev;
+
+	/* Allocate our private context */
+	fdev = kmalloc(sizeof(struct sdio_dev), GFP_KERNEL);
+	if (!fdev)
+		return -ENOMEM;
+	available_sdio_dev = fdev;
+	memset(fdev, 0, sizeof(struct sdio_dev));
+	fdev->func = func;
+	fdev->vendor_id = id->vendor;
+	fdev->device_id = id->device;
+	fdev->max_blocksize = func->max_blksize;
+	fdev->int_enabled = 1;
+	spin_lock_init(&fdev->lock);
+
+	/* Store our context in the MMC driver */
+	printk(KERN_INFO "fs_sdio_probe: Add glue driver\n");
+	sdio_set_drvdata(func, fdev);
+
+	return 0;
+}
+
+static void fs_sdio_remove(struct sdio_func *func)
+{
+	struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func);
+	struct mmc_host *host = func->card->host;
+
+	/* If there is a registered device driver, pass on the remove */
+	if (fdev->driver) {
+		printk(KERN_INFO "fs_sdio_remove: Free IRQ and remove device "
+		       "driver\n");
+		/* Unregister the IRQ handler first. */
+		sdio_claim_host(fdev->func);
+		sdio_release_irq(func);
+		sdio_release_host(fdev->func);
+
+		fdev->driver->remove(fdev);
+
+		if (!fdev->int_enabled) {
+			fdev->int_enabled = 1;
+			host->ops->enable_sdio_irq(host, 1);
+		}
+	}
+
+	/* Unregister the card context from the MMC driver. */
+	sdio_set_drvdata(func, NULL);
+
+	/* Invalidate the global to our context. */
+	available_sdio_dev = NULL;
+	kfree(fdev);
+}
+
+static int fs_unifi_init(void)
+{
+	struct regulator_unifi *reg_unifi;
+	struct regulator *reg;
+	int err = 0;
+
+	plat_data = get_unifi_plat_data();
+
+	if (!plat_data)
+		return -ENOENT;
+
+	reg_unifi = kzalloc(sizeof(struct regulator_unifi), GFP_KERNEL);
+	if (!reg_unifi)
+		return -ENOMEM;
+
+	if (plat_data->reg_gpo1) {
+		reg = regulator_get(NULL, plat_data->reg_gpo1);
+		if (!IS_ERR(reg))
+			reg_unifi->reg_gpo1 = reg;
+		else {
+			err = -EINVAL;
+			goto err_reg_gpo1;
+		}
+	}
+
+	if (plat_data->reg_gpo2) {
+		reg = regulator_get(NULL, plat_data->reg_gpo2);
+		if (!IS_ERR(reg))
+			reg_unifi->reg_gpo2 = reg;
+		else {
+			err = -EINVAL;
+			goto err_reg_gpo2;
+		}
+	}
+
+	if (plat_data->reg_1v5_ana_bb) {
+		reg = regulator_get(NULL, plat_data->reg_1v5_ana_bb);
+		if (!IS_ERR(reg))
+			reg_unifi->reg_1v5_ana_bb = reg;
+		else {
+			err = -EINVAL;
+			goto err_reg_1v5_ana_bb;
+		}
+	}
+
+	if (plat_data->reg_vdd_vpa) {
+		reg = regulator_get(NULL, plat_data->reg_vdd_vpa);
+		if (!IS_ERR(reg))
+			reg_unifi->reg_vdd_vpa = reg;
+		else {
+			err = -EINVAL;
+			goto err_reg_vdd_vpa;
+		}
+	}
+
+	if (plat_data->reg_1v5_dd) {
+		reg = regulator_get(NULL, plat_data->reg_1v5_dd);
+		if (!IS_ERR(reg))
+			reg_unifi->reg_1v5_dd = reg;
+		else {
+			err = -EINVAL;
+			goto err_reg_1v5_dd;
+		}
+	}
+	plat_data->priv = reg_unifi;
+	return 0;
+
+err_reg_1v5_dd:
+	if (reg_unifi->reg_vdd_vpa)
+		regulator_put(reg_unifi->reg_vdd_vpa);
+err_reg_vdd_vpa:
+	if (reg_unifi->reg_1v5_ana_bb)
+		regulator_put(reg_unifi->reg_1v5_ana_bb);
+err_reg_1v5_ana_bb:
+	if (reg_unifi->reg_gpo2)
+		regulator_put(reg_unifi->reg_gpo2);
+err_reg_gpo2:
+	if (reg_unifi->reg_gpo1)
+		regulator_put(reg_unifi->reg_gpo1);
+err_reg_gpo1:
+	kfree(reg_unifi);
+	return err;
+}
+
+int fs_unifi_remove(void)
+{
+	struct regulator_unifi *reg_unifi;
+
+	reg_unifi = plat_data->priv;
+	plat_data->priv = NULL;
+
+	if (reg_unifi->reg_1v5_dd)
+		regulator_put(reg_unifi->reg_1v5_dd);
+	if (reg_unifi->reg_vdd_vpa)
+		regulator_put(reg_unifi->reg_vdd_vpa);
+
+	if (reg_unifi->reg_1v5_ana_bb)
+		regulator_put(reg_unifi->reg_1v5_ana_bb);
+
+	if (reg_unifi->reg_gpo2)
+		regulator_put(reg_unifi->reg_gpo2);
+
+	if (reg_unifi->reg_gpo1)
+		regulator_put(reg_unifi->reg_gpo1);
+
+	kfree(reg_unifi);
+	return 0;
+}
+
+/* Module init and exit, register and unregister to the SDIO/MMC driver */
+static int __init fs_sdio_init(void)
+{
+	int err;
+
+	printk(KERN_INFO "Freescale: Register to MMC/SDIO driver\n");
+	/* Sleep a bit - otherwise if the mmc subsystem has just started, it
+	 * will allow us to register, then immediatly remove us!
+	 */
+	msleep(10);
+	err = fs_unifi_init();
+	if (err) {
+		printk(KERN_ERR "Error: fs_unifi_init failed!\n");
+		return err;
+	}
+	err = sdio_register_driver(&sdio_unifi_driver);
+	if (err) {
+		printk(KERN_ERR "Error: register sdio_unifi_driver failed!\n");
+		fs_unifi_remove();
+	}
+	return err;
+}
+
+module_init(fs_sdio_init);
+
+static void __exit fs_sdio_exit(void)
+{
+	printk(KERN_INFO "Freescale: Unregister from MMC/SDIO driver\n");
+	sdio_unregister_driver(&sdio_unifi_driver);
+	fs_unifi_remove();
+}
+
+module_exit(fs_sdio_exit);
+
+MODULE_DESCRIPTION("Freescale SDIO glue driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/card/unifi_fs/fs_sdio_api.h b/drivers/mmc/card/unifi_fs/fs_sdio_api.h
new file mode 100644
index 000000000000..ea6ebd765e28
--- /dev/null
+++ b/drivers/mmc/card/unifi_fs/fs_sdio_api.h
@@ -0,0 +1,68 @@
+/*
+ *fs_sdio_api.h - Freescale SDIO glue module API for UniFi.
+ *
+ * Copyright (C) 2008 Cambridge Silicon Radio Ltd.
+ *
+ */
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef _FS_SDIO_API_H
+#define _FS_SDIO_API_H
+
+struct sdio_dev;
+
+struct fs_driver {
+	const char *name;
+	int (*probe)(struct sdio_dev *fdev);
+	void (*remove)(struct sdio_dev *fdev);
+	void (*card_int_handler)(struct sdio_dev *fdev);
+	void (*suspend)(struct sdio_dev *fdev, pm_message_t state);
+	void (*resume)(struct sdio_dev *fdev);
+};
+
+int fs_sdio_readb(struct sdio_dev *fdev, int funcnum,
+		  unsigned long addr, unsigned char *pdata);
+int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum,
+		   unsigned long addr, unsigned char data);
+int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum,
+		     unsigned long addr, unsigned char *pdata,
+		     unsigned int count, int direction);
+
+int fs_sdio_register_driver(struct fs_driver *driver);
+void fs_sdio_unregister_driver(struct fs_driver *driver);
+int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz);
+int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz);
+int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable);
+int fs_sdio_enable(struct sdio_dev *fdev);
+int fs_sdio_hard_reset(struct sdio_dev *fdev);
+
+struct sdio_dev {
+	/**< Device driver for this module. */
+	struct fs_driver *driver;
+
+	struct sdio_func *func;
+
+	/**< Data private to the device driver. */
+	void *drv_data;
+
+	int int_enabled;
+	spinlock_t lock;
+
+	uint16_t vendor_id;     /**< Vendor ID of the card. */
+	uint16_t device_id;     /**< Device ID of the card. */
+
+	/**< Maximum block size supported. */
+	int max_blocksize;
+};
+
+
+#endif	/* #ifndef _FS_SDIO_API_H */
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 06084dbf1277..ff6e15125fa9 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -121,7 +121,7 @@ static int mmc_decode_csd(struct mmc_card *card)
 	 * v1.2 has extra information in bits 15, 11 and 10.
 	 */
 	csd_struct = UNSTUFF_BITS(resp, 126, 2);
-	if (csd_struct != 1 && csd_struct != 2) {
+	if (csd_struct < 1 || csd_struct > 3) {
 		printk(KERN_ERR "%s: unrecognised CSD structure version %d\n",
 			mmc_hostname(card->host), csd_struct);
 		return -EINVAL;
@@ -208,7 +208,7 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 	}
 
 	ext_csd_struct = ext_csd[EXT_CSD_REV];
-	if (ext_csd_struct > 3) {
+	if (ext_csd_struct > 5) {
 		printk(KERN_ERR "%s: unrecognised EXT_CSD structure "
 			"version %d\n", mmc_hostname(card->host),
 			ext_csd_struct);
@@ -226,7 +226,16 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 			mmc_card_set_blockaddr(card);
 	}
 
+	card->ext_csd.boot_info = ext_csd[EXT_CSD_BOOT_INFO];
+	card->ext_csd.boot_size_mult = ext_csd[EXT_CSD_BOOT_SIZE_MULT];
+	card->ext_csd.boot_config = ext_csd[EXT_CSD_BOOT_CONFIG];
+	card->ext_csd.card_type = ext_csd[EXT_CSD_CARD_TYPE];
+
 	switch (ext_csd[EXT_CSD_CARD_TYPE]) {
+	case EXT_CSD_CARD_TYPE_DDR_52 | EXT_CSD_CARD_TYPE_52
+		| EXT_CSD_CARD_TYPE_26:
+		card->ext_csd.hs_max_dtr = 52000000;
+		break;
 	case EXT_CSD_CARD_TYPE_52 | EXT_CSD_CARD_TYPE_26:
 		card->ext_csd.hs_max_dtr = 52000000;
 		break;
@@ -238,6 +247,8 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 		printk(KERN_WARNING "%s: card is mmc v4 but doesn't "
 			"support any high-speed modes.\n",
 			mmc_hostname(card->host));
+		printk(KERN_WARNING "%s: card type is 0x%x\n",
+			mmc_hostname(card->host), ext_csd[EXT_CSD_CARD_TYPE]);
 		goto out;
 	}
 
@@ -247,6 +258,102 @@ out:
 	return err;
 }
 
+/* switch the partitions */
+static ssize_t
+switch_partitions(struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	int err;
+	u32 part, new_part;
+	u8 *ext_csd, boot_config;
+	struct mmc_card *card = container_of(dev, struct mmc_card, dev);
+	struct mmc_host *host = card->host;
+
+	BUG_ON(!card);
+
+	mmc_claim_host(card->host);
+	sscanf(buf, "%d\n", &part);
+
+	/* partition must be -
+	 * 0 - user area
+	 * 1 - boot partition 1
+	 * 2 - boot partition 2
+	 */
+	if (part > 2) {
+		printk(KERN_ERR "%s: wrong partition id"
+			" 0 (user area), 1 (boot1), 2 (boot2)\n",
+			mmc_hostname(card->host));
+		return -EINVAL;
+	}
+
+	if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
+		printk(KERN_ERR "%s: invalid mmc version"
+			" mmc version is below version 4!)\n",
+			mmc_hostname(card->host));
+		return -EINVAL;
+	}
+
+	/* it's a normal SD/MMC but user request to configure boot partition */
+	if (card->ext_csd.boot_size_mult <= 0) {
+		printk(KERN_ERR "%s: this is a normal SD/MMC card"
+			" but you request to access boot partition!\n",
+			mmc_hostname(card->host));
+		return -EINVAL;
+	}
+
+	ext_csd = kmalloc(512, GFP_KERNEL);
+	if (!ext_csd) {
+		printk(KERN_ERR "%s: could not allocate a buffer to "
+			"receive the ext_csd.\n", mmc_hostname(card->host));
+		return -ENOMEM;
+	}
+
+	err = mmc_send_ext_csd(card, ext_csd);
+	if (err) {
+		printk(KERN_ERR "%s: unable to read EXT_CSD.\n",
+			mmc_hostname(card->host));
+		goto err_rtn;
+	}
+
+	/* Send SWITCH command to change partition for access */
+	boot_config = (ext_csd[EXT_CSD_BOOT_CONFIG] &
+			~EXT_CSD_BOOT_PARTITION_ACCESS_MASK) | part;
+	err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+			EXT_CSD_BOOT_CONFIG, boot_config);
+	if (err) {
+		printk(KERN_ERR "%s: fail to send SWITCH command"
+				" to card to swich partition for access!\n",
+			mmc_hostname(card->host));
+		goto err_rtn;
+	}
+
+	/* Now check whether it works */
+	err = mmc_send_ext_csd(card, ext_csd);
+	if (err) {
+		printk(KERN_ERR "%s: %d unable to read EXT_CSD.\n",
+			mmc_hostname(card->host), err);
+		goto err_rtn;
+	}
+
+	new_part = ext_csd[EXT_CSD_BOOT_CONFIG] &
+		EXT_CSD_BOOT_PARTITION_ACCESS_MASK;
+	if (part != new_part) {
+		printk(KERN_ERR "%s: after SWITCH, current part id %d is not"
+				" same as requested partition %d!\n",
+			mmc_hostname(card->host), new_part, part);
+		goto err_rtn;
+	}
+	card->ext_csd.boot_config = ext_csd[EXT_CSD_BOOT_CONFIG];
+
+err_rtn:
+	mmc_release_host(card->host);
+	kfree(ext_csd);
+	if (err)
+		return err;
+	else
+		return count;
+}
+
 MMC_DEV_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1],
 	card->raw_cid[2], card->raw_cid[3]);
 MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1],
@@ -258,6 +365,10 @@ MMC_DEV_ATTR(manfid, "0x%06x\n", card->cid.manfid);
 MMC_DEV_ATTR(name, "%s\n", card->cid.prod_name);
 MMC_DEV_ATTR(oemid, "0x%04x\n", card->cid.oemid);
 MMC_DEV_ATTR(serial, "0x%08x\n", card->cid.serial);
+MMC_DEV_ATTR(boot_info, "Info:0x%02x;Size:0x%02xMB;Part:0x%02x\n",
+	card->ext_csd.boot_info, card->ext_csd.boot_size_mult / 8,
+	card->ext_csd.boot_config);
+DEVICE_ATTR(boot_config, S_IWUGO, NULL, switch_partitions);
 
 static struct attribute *mmc_std_attrs[] = {
 	&dev_attr_cid.attr,
@@ -269,6 +380,8 @@ static struct attribute *mmc_std_attrs[] = {
 	&dev_attr_name.attr,
 	&dev_attr_oemid.attr,
 	&dev_attr_serial.attr,
+	&dev_attr_boot_info.attr,
+	&dev_attr_boot_config.attr,
 	NULL,
 };
 
@@ -434,10 +547,21 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	 * Activate wide bus (if supported).
 	 */
 	if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
-	    (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) {
+		(host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
+			       | MMC_CAP_DATA_DDR))) {
 		unsigned ext_csd_bit, bus_width;
 
-		if (host->caps & MMC_CAP_8_BIT_DATA) {
+		if ((host->caps & MMC_CAP_8_BIT_DATA) &&
+				(host->caps & MMC_CAP_DATA_DDR) &&
+				(card->ext_csd.card_type & MMC_DDR_MODE_MASK)) {
+			ext_csd_bit = EXT_CSD_BUS_WIDTH_8_DDR;
+			bus_width = MMC_BUS_WIDTH_8 | MMC_BUS_WIDTH_DDR;
+		} else if ((host->caps & MMC_CAP_4_BIT_DATA) &&
+				(host->caps & MMC_CAP_DATA_DDR) &&
+				(card->ext_csd.card_type & MMC_DDR_MODE_MASK)) {
+			ext_csd_bit = EXT_CSD_BUS_WIDTH_4_DDR;
+			bus_width = MMC_BUS_WIDTH_4 | MMC_BUS_WIDTH_DDR;
+		} else if (host->caps & MMC_CAP_8_BIT_DATA) {
 			ext_csd_bit = EXT_CSD_BUS_WIDTH_8;
 			bus_width = MMC_BUS_WIDTH_8;
 		} else {
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 891ef18bd77b..8cf0287eb8d1 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -250,6 +250,59 @@ config MMC_SPI
 
 	  If unsure, or if your system has no SPI master driver, say N.
 
+config MMC_MXC
+	tristate "Freescale MXC Multimedia Card Interface support"
+	depends on ARCH_MXC && MMC
+	help
+	  This selects the Freescale MXC Multimedia card Interface.
+	  If you have a MXC platform with a Multimedia Card slot,
+	  say Y or M here.
+
+config MMC_IMX_ESDHCI
+	tristate "Freescale i.MX Secure Digital Host Controller Interface support"
+	depends on ARCH_MXC && MMC
+	help
+	  This selects the Freescale i.MX Multimedia card Interface.
+	  If you have a i.MX platform with a Multimedia Card slot,
+	  say Y or M here.
+
+	  If unsure, say N.
+
+config MMC_IMX_ESDHCI_SELECT2
+	bool "Enable second ESDHCI port"
+	depends on MMC_IMX_ESDHCI && ARCH_MX25
+	default n
+	help
+	  Enable the second ESDHC port
+
+config MMC_IMX_ESDHCI_PIO_MODE
+	bool "Freescale i.MX Secure Digital Host Controller Interface PIO mode"
+	depends on MMC_IMX_ESDHC != n
+	default n
+	help
+	  This set the Freescale i.MX Multimedia card Interface to PIO mode.
+	  If you have a i.MX platform with a Multimedia Card slot,
+	  and want test it with PIO mode.
+	  say Y here.
+
+	  If unsure, say N.
+
+config MMC_STMP3XXX
+	tristate "STMP37xx/378x MMC support"
+	depends on MMC && ARCH_STMP3XXX
+	help
+	  Select Y if you would like to access STMP37xx/378x MMC support.
+
+	  If unsure, say N.
+
+config MMC_MXS
+	tristate "MXS MMC support"
+	depends on MMC && (ARCH_MX28 || ARCH_MX23)
+	help
+	  Select Y if you would like to access MXS MMC support.
+
+	  If unsure, say N.
+
 config MMC_S3C
 	tristate "Samsung S3C SD/MMC Card Interface support"
 	depends on ARCH_S3C2410
@@ -267,6 +320,7 @@ config MMC_SDRICOH_CS
 	help
 	  Say Y here if your Notebook reports a Ricoh Bay1Controller PCMCIA
 	  card whenever you insert a MMC or SD card into the card slot.
+	  say Y or M here.
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called sdricoh_cs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cf153f628457..fbef5ea2632b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -9,13 +9,16 @@ endif
 obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
 obj-$(CONFIG_MMC_IMX)		+= imxmmc.o
-obj-$(CONFIG_MMC_MXC)		+= mxcmmc.o
+obj-$(CONFIG_MMC_MXC)		+= mxc_mmc.o
 obj-$(CONFIG_MMC_SDHCI)		+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PCI)	+= sdhci-pci.o
 obj-$(CONFIG_MMC_RICOH_MMC)	+= ricoh_mmc.o
 obj-$(CONFIG_MMC_SDHCI_OF)	+= sdhci-of.o
 obj-$(CONFIG_MMC_SDHCI_PLTFM)	+= sdhci-pltfm.o
 obj-$(CONFIG_MMC_SDHCI_S3C)	+= sdhci-s3c.o
+obj-$(CONFIG_MMC_IMX_ESDHCI)	+= mx_sdhci.o
+obj-$(CONFIG_MMC_STMP3XXX)	+= stmp3xxx_mmc.o
+obj-$(CONFIG_MMC_MXS)		+= mxs-mmc.o
 obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
 obj-$(CONFIG_MMC_AU1X)		+= au1xmmc.o
 obj-$(CONFIG_MMC_OMAP)		+= omap.o
diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c
new file mode 100644
index 000000000000..0a49b556dee9
--- /dev/null
+++ b/drivers/mmc/host/mx_sdhci.c
@@ -0,0 +1,2223 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx_sdhci.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC eSDHC modules.
+ *
+ * This driver code is based on sdhci.c, by Pierre Ossman <drzeus@drzeus.cx>");
+ * This driver supports Enhanced Secure Digital Host Controller
+ * modules eSDHC of MXC. eSDHC is also referred as enhanced MMC/SD
+ * controller.
+ *
+ * @ingroup MMC_SD
+ */
+
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+
+#include <linux/leds.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/card.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/mmc.h>
+
+#include "mx_sdhci.h"
+
+#define DRIVER_NAME "mxsdhci"
+
+#define DBG(f, x...) \
+	pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
+
+static unsigned int debug_quirks;
+static int last_op_dir;
+
+/*
+ * Different quirks to handle when the hardware deviates from a strict
+ * interpretation of the SDHCI specification.
+ */
+
+/* Controller doesn't honor resets unless we touch the clock register */
+#define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
+/* Controller has bad caps bits, but really supports DMA */
+#define SDHCI_QUIRK_FORCE_DMA				(1<<1)
+/* Controller doesn't like to be reset when there is no card inserted. */
+#define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
+/* Controller doesn't like clearing the power reg before a change */
+#define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
+/* Controller has flaky internal state so reset it on each ios change */
+#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
+/* Controller has an unusable DMA engine */
+#define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
+/* Controller can only DMA from 32-bit aligned addresses */
+#define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<6)
+/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
+#define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<7)
+/* Controller needs to be reset after each request to stay stable */
+#define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<8)
+/* Controller needs voltage and power writes to happen separately */
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<9)
+/* Controller has an off-by-one issue with timeout value */
+#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL		(1<<10)
+/* Controller only support the PIO */
+#define SDHCI_QUIRK_ONLY_PIO 				(1<<16)
+/* Controller support the External DMA */
+#define SDHCI_QUIRK_EXTERNAL_DMA_MODE			(1<<17)
+/* Controller support the Internal Simple DMA */
+#define SDHCI_QUIRK_INTERNAL_SIMPLE_DMA			(1<<18)
+/* Controller support the Internal Advanced DMA */
+#define SDHCI_QUIRK_INTERNAL_ADVANCED_DMA 		(1<<19)
+
+/*
+ * defines the mxc flags refer to the special hw pre-conditons and behavior
+ */
+static unsigned int mxc_quirks;
+#ifdef CONFIG_MMC_IMX_ESDHCI_PIO_MODE
+static unsigned int debug_quirks = SDHCI_QUIRK_ONLY_PIO;
+#else
+static unsigned int debug_quirks;
+#endif
+static unsigned int mxc_wml_value = 512;
+static unsigned int *adma_des_table;
+
+#ifndef MXC_SDHCI_NUM
+#define MXC_SDHCI_NUM	4
+#endif
+
+static struct sdhci_chip *mxc_fix_chips[MXC_SDHCI_NUM];
+
+static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
+static void sdhci_finish_data(struct sdhci_host *);
+
+static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
+static void sdhci_finish_command(struct sdhci_host *);
+
+/* Used to active the SD bus */
+extern void gpio_sdhc_active(int module);
+extern void gpio_sdhc_inactive(int module);
+static void sdhci_dma_irq(void *devid, int error, unsigned int cnt);
+
+void mxc_mmc_force_detect(int id)
+{
+	struct sdhci_host *host;
+	if ((id < 0) || (id >= MXC_SDHCI_NUM))
+		return;
+	if (!mxc_fix_chips[id])
+		return;
+	host = mxc_fix_chips[id]->hosts[0];
+	if (host->detect_irq)
+		return;
+
+	schedule_work(&host->cd_wq);
+	return;
+}
+
+EXPORT_SYMBOL(mxc_mmc_force_detect);
+
+static void sdhci_dumpregs(struct sdhci_host *host)
+{
+	printk(KERN_INFO DRIVER_NAME
+	       ": ============== REGISTER DUMP ==============\n");
+
+	printk(KERN_INFO DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
+	       readl(host->ioaddr + SDHCI_DMA_ADDRESS),
+	       readl(host->ioaddr + SDHCI_HOST_VERSION));
+	printk(KERN_INFO DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
+	       (readl(host->ioaddr + SDHCI_BLOCK_SIZE) & 0xFFFF),
+	       (readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16));
+	printk(KERN_INFO DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
+	       readl(host->ioaddr + SDHCI_ARGUMENT),
+	       readl(host->ioaddr + SDHCI_TRANSFER_MODE));
+	printk(KERN_INFO DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
+	       readl(host->ioaddr + SDHCI_PRESENT_STATE),
+	       readl(host->ioaddr + SDHCI_HOST_CONTROL));
+	printk(KERN_INFO DRIVER_NAME ": Clock:    0x%08x\n",
+	       readl(host->ioaddr + SDHCI_CLOCK_CONTROL));
+	printk(KERN_INFO DRIVER_NAME ": Int stat: 0x%08x\n",
+	       readl(host->ioaddr + SDHCI_INT_STATUS));
+	printk(KERN_INFO DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
+	       readl(host->ioaddr + SDHCI_INT_ENABLE),
+	       readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
+	printk(KERN_INFO DRIVER_NAME ": Caps:     0x%08x\n",
+	       readl(host->ioaddr + SDHCI_CAPABILITIES));
+
+	printk(KERN_INFO DRIVER_NAME
+	       ": ===========================================\n");
+}
+
+/*****************************************************************************\
+ *                                                                           *
+ * Low level functions                                                       *
+ *                                                                           *
+\*****************************************************************************/
+
+static void sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+	unsigned long tmp;
+	unsigned long mask_u32;
+	unsigned long reg_save = 0;
+
+	if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+		if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
+		      SDHCI_CARD_PRESENT))
+			return;
+	}
+
+	if (mask & SDHCI_RESET_ALL)
+		host->clock = 0;
+	else if (host->flags & SDHCI_CD_PRESENT)
+		reg_save = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+
+	tmp = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) | (mask << 24);
+	mask_u32 = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	writel(tmp, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	/* Wait max 100 ms */
+	tmp = 5000;
+
+	/* hw clears the bit when it's done */
+	while ((readl(host->ioaddr + SDHCI_CLOCK_CONTROL) >> 24) & mask) {
+		if (tmp == 0) {
+			printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
+			       mmc_hostname(host->mmc), (int)mask);
+			sdhci_dumpregs(host);
+			return;
+		}
+		tmp--;
+		udelay(20);
+	}
+	/*
+	 * The INT_EN SIG_EN regs have been modified after reset.
+	 * re-configure them ag.
+	 */
+	if (!(mask & SDHCI_RESET_ALL) && (host->flags & SDHCI_CD_PRESENT))
+		writel(reg_save, host->ioaddr + SDHCI_HOST_CONTROL);
+	if (host->flags & SDHCI_USE_DMA)
+		mask_u32 &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL);
+	if (mxc_wml_value == 512)
+		writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML);
+	else
+		writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML);
+	writel(mask_u32 | SDHCI_INT_CARD_INT, host->ioaddr + SDHCI_INT_ENABLE);
+	writel(mask_u32, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	last_op_dir = 0;
+}
+
+static void sdhci_init(struct sdhci_host *host)
+{
+	u32 intmask;
+
+	sdhci_reset(host, SDHCI_RESET_ALL);
+
+	intmask = SDHCI_INT_ADMA_ERROR | SDHCI_INT_ACMD12ERR |
+	    SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC |
+	    SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
+	    SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
+	    SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
+	    SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
+
+	if (host->flags & SDHCI_USE_DMA)
+		intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL);
+	/* Configure the WML rege */
+	if (mxc_wml_value == 512)
+		writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML);
+	else
+		writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML);
+	writel(intmask | SDHCI_INT_CARD_INT, host->ioaddr + SDHCI_INT_ENABLE);
+	writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_activate_led(struct sdhci_host *host)
+{
+	u32 ctrl;
+
+	ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+	ctrl |= SDHCI_CTRL_LED;
+	writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+}
+
+static void sdhci_deactivate_led(struct sdhci_host *host)
+{
+	u32 ctrl;
+
+	ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+	ctrl &= ~SDHCI_CTRL_LED;
+	writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+}
+
+/*****************************************************************************\
+ *                                                                           *
+ * Core functions                                                            *
+ *                                                                           *
+\*****************************************************************************/
+
+static inline char *sdhci_sg_to_buffer(struct sdhci_host *host)
+{
+	return sg_virt(host->cur_sg);
+}
+
+static inline int sdhci_next_sg(struct sdhci_host *host)
+{
+	/*
+	 * Skip to next SG entry.
+	 */
+	host->cur_sg++;
+	host->num_sg--;
+
+	/*
+	 * Any entries left?
+	 */
+	if (host->num_sg > 0) {
+		host->offset = 0;
+		host->remain = host->cur_sg->length;
+	}
+
+	return host->num_sg;
+}
+
+static void sdhci_read_block_pio(struct sdhci_host *host)
+{
+	int blksize, chunk_remain;
+	u32 data;
+	char *buffer;
+	int size;
+
+	DBG("PIO reading\n");
+
+	blksize = host->data->blksz;
+	chunk_remain = 0;
+	data = 0;
+
+	buffer = sdhci_sg_to_buffer(host) + host->offset;
+
+	while (blksize) {
+		if (chunk_remain == 0) {
+			data = readl(host->ioaddr + SDHCI_BUFFER);
+			chunk_remain = min(blksize, 4);
+		}
+
+		size = min(host->remain, chunk_remain);
+
+		chunk_remain -= size;
+		blksize -= size;
+		host->offset += size;
+		host->remain -= size;
+
+		while (size) {
+			*buffer = data & 0xFF;
+			buffer++;
+			data >>= 8;
+			size--;
+		}
+
+		if (host->remain == 0) {
+			if (sdhci_next_sg(host) == 0) {
+				BUG_ON(blksize != 0);
+				return;
+			}
+			buffer = sdhci_sg_to_buffer(host);
+		}
+	}
+}
+
+static void sdhci_write_block_pio(struct sdhci_host *host)
+{
+	int blksize, chunk_remain;
+	u32 data;
+	char *buffer;
+	int bytes, size;
+
+	DBG("PIO writing\n");
+
+	blksize = host->data->blksz;
+	chunk_remain = 4;
+	data = 0;
+
+	bytes = 0;
+	buffer = sdhci_sg_to_buffer(host) + host->offset;
+
+	while (blksize) {
+		size = min(host->remain, chunk_remain);
+
+		chunk_remain -= size;
+		blksize -= size;
+		host->offset += size;
+		host->remain -= size;
+
+		while (size) {
+			data >>= 8;
+			data |= (u32) *buffer << 24;
+			buffer++;
+			size--;
+		}
+
+		if (chunk_remain == 0) {
+			writel(data, host->ioaddr + SDHCI_BUFFER);
+			chunk_remain = min(blksize, 4);
+		}
+
+		if (host->remain == 0) {
+			if (sdhci_next_sg(host) == 0) {
+				BUG_ON(blksize != 0);
+				return;
+			}
+			buffer = sdhci_sg_to_buffer(host);
+		}
+	}
+}
+
+static void sdhci_transfer_pio(struct sdhci_host *host)
+{
+	u32 mask;
+
+	BUG_ON(!host->data);
+
+	if (host->num_sg == 0)
+		return;
+
+	if (host->data->flags & MMC_DATA_READ)
+		mask = SDHCI_DATA_AVAILABLE;
+	else
+		mask = SDHCI_SPACE_AVAILABLE;
+
+	while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
+		if (host->data->flags & MMC_DATA_READ)
+			sdhci_read_block_pio(host);
+		else
+			sdhci_write_block_pio(host);
+
+		if (host->num_sg == 0)
+			break;
+	}
+
+	DBG("PIO transfer complete.\n");
+}
+
+static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
+{
+	u32 count;
+	unsigned target_timeout, current_timeout;
+
+	WARN_ON(host->data);
+
+	if (data == NULL)
+		return;
+
+	/* Sanity checks */
+	BUG_ON(data->blksz * data->blocks > 524288);
+	BUG_ON(data->blksz > host->mmc->max_blk_size);
+	BUG_ON(data->blocks > 65535);
+
+	host->data = data;
+	host->data_early = 0;
+	if (host->data->flags & MMC_DATA_READ)
+		writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL) |
+		       SDHCI_CLOCK_HLK_EN, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	/* timeout in us */
+	target_timeout = data->timeout_ns / 1000 +
+	    data->timeout_clks / host->clock;
+
+	/*
+	 * Figure out needed cycles.
+	 * We do this in steps in order to fit inside a 32 bit int.
+	 * The first step is the minimum timeout, which will have a
+	 * minimum resolution of 6 bits:
+	 * (1) 2^13*1000 > 2^22,
+	 * (2) host->timeout_clk < 2^16
+	 *     =>
+	 *     (1) / (2) > 2^6
+	 */
+	count = 0;
+	current_timeout = (1 << 13) * 1000 / host->timeout_clk;
+	while (current_timeout < target_timeout) {
+		count++;
+		current_timeout <<= 1;
+		if (count >= 0xF)
+			break;
+	}
+
+	/*
+	 * Compensate for an off-by-one error in the CaFe hardware; otherwise,
+	 * a too-small count gives us interrupt timeouts.
+	 */
+	if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
+		count++;
+
+	if (count >= 0xF) {
+		DBG(KERN_WARNING "%s: Too large timeout requested!\n",
+		    mmc_hostname(host->mmc));
+		count = 0xE;
+	}
+
+	/* Set the max time-out value to level up the compatibility */
+	count = 0xE;
+
+	count =
+	    (count << 16) | (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) &
+			     0xFFF0FFFF);
+	writel(count, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	if (host->flags & SDHCI_USE_DMA)
+		host->flags |= SDHCI_REQ_USE_DMA;
+
+	if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
+		     (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
+		     ((data->blksz * data->blocks) & 0x3))) {
+		DBG("Reverting to PIO because of transfer size (%d)\n",
+		    data->blksz * data->blocks);
+		host->flags &= ~SDHCI_REQ_USE_DMA;
+	}
+
+	/*
+	 * The assumption here being that alignment is the same after
+	 * translation to device address space.
+	 */
+	if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
+		     (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
+		     (data->sg->offset & 0x3))) {
+		DBG("Reverting to PIO because of bad alignment\n");
+		host->flags &= ~SDHCI_REQ_USE_DMA;
+	}
+
+	if (cpu_is_mx25() && (data->blksz * data->blocks < 0x10)) {
+		host->flags &= ~SDHCI_REQ_USE_DMA;
+		DBG("Reverting to PIO in small data transfer.\n");
+		writel(readl(host->ioaddr + SDHCI_INT_ENABLE)
+				| SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL,
+				host->ioaddr + SDHCI_INT_ENABLE);
+		writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)
+				| SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL,
+				host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	} else if (cpu_is_mx25() && (host->flags & SDHCI_USE_DMA)) {
+		host->flags |= SDHCI_REQ_USE_DMA;
+		DBG("Reverting to DMA in large data transfer.\n");
+		writel(readl(host->ioaddr + SDHCI_INT_ENABLE)
+				& ~(SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL),
+				host->ioaddr + SDHCI_INT_ENABLE);
+		writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)
+				& ~(SDHCI_INT_DATA_AVAIL
+				| SDHCI_INT_SPACE_AVAIL),
+				host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	}
+
+	if (host->flags & SDHCI_REQ_USE_DMA) {
+		int i;
+		struct scatterlist *tsg;
+
+		host->dma_size = data->blocks * data->blksz;
+		count =
+		    dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+			       (data->
+				flags & MMC_DATA_READ) ? DMA_FROM_DEVICE :
+			       DMA_TO_DEVICE);
+		BUG_ON(count != data->sg_len);
+		DBG("Configure the sg DMA, %s, len is 0x%x, count is %d\n",
+		    (data->flags & MMC_DATA_READ)
+		    ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", host->dma_size,
+		    count);
+
+		/* Make sure the ADMA mode is selected. */
+		i = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+		i |= SDHCI_CTRL_ADMA;
+		writel(i, host->ioaddr + SDHCI_HOST_CONTROL);
+
+		tsg = data->sg;
+		/* ADMA mode is used, create the descriptor table */
+		for (i = 0; i < count; i++) {
+			if (tsg->dma_address & 0xFFF) {
+				DBG(KERN_ERR "ADMA addr isn't 4K aligned.\n");
+				DBG(KERN_ERR "0x%x\n", tsg->dma_address);
+				DBG(KERN_ERR "Changed to Single DMA mode.\n");
+				goto Single_DMA;
+			}
+			adma_des_table[2 * i] = tsg->length << 12;
+			adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_SET;
+			adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_VALID;
+			adma_des_table[2 * i + 1] = tsg->dma_address;
+			adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_TRAN;
+			adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_VALID;
+			if (count == (i + 1))
+				adma_des_table[2 * i + 1] |=
+				    FSL_ADMA_DES_ATTR_END;
+			tsg++;
+		}
+
+		/* Write the physical address to ADMA address reg */
+		writel(virt_to_phys(adma_des_table),
+		       host->ioaddr + SDHCI_ADMA_ADDRESS);
+	      Single_DMA:
+		/* Rollback to the Single DMA mode */
+		i = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+		i &= ~SDHCI_CTRL_ADMA;
+		writel(i, host->ioaddr + SDHCI_HOST_CONTROL);
+		/* Single DMA mode is used */
+		writel(sg_dma_address(data->sg),
+		       host->ioaddr + SDHCI_DMA_ADDRESS);
+	} else if ((host->flags & SDHCI_USE_EXTERNAL_DMA) &&
+		   (data->blocks * data->blksz >= mxc_wml_value)) {
+		host->dma_size = data->blocks * data->blksz;
+		DBG("Configure the External DMA, %s, len is 0x%x\n",
+		    (data->flags & MMC_DATA_READ)
+		    ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", host->dma_size);
+
+		if (data->blksz & 0x3) {
+			printk(KERN_ERR
+			       "mxc_mci: block size not multiple of 4 bytes\n");
+		}
+
+		if (data->flags & MMC_DATA_READ)
+			host->dma_dir = DMA_FROM_DEVICE;
+		else
+			host->dma_dir = DMA_TO_DEVICE;
+
+		host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
+					   data->sg_len, host->dma_dir);
+
+		if (data->flags & MMC_DATA_READ) {
+			mxc_dma_sg_config(host->dma, data->sg, data->sg_len,
+					  host->dma_size, MXC_DMA_MODE_READ);
+		} else {
+			mxc_dma_sg_config(host->dma, data->sg, data->sg_len,
+					  host->dma_size, MXC_DMA_MODE_WRITE);
+		}
+	} else {
+		host->cur_sg = data->sg;
+		host->num_sg = data->sg_len;
+
+		host->offset = 0;
+		host->remain = host->cur_sg->length;
+	}
+
+	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
+	writel((data->blocks << 16) | SDHCI_MAKE_BLKSZ(0, data->blksz),
+	       host->ioaddr + SDHCI_BLOCK_SIZE);
+}
+
+static void sdhci_finish_data(struct sdhci_host *host)
+{
+	struct mmc_data *data;
+	u16 blocks;
+
+	BUG_ON(!host->data);
+
+	data = host->data;
+	host->data = NULL;
+
+	if (host->flags & SDHCI_REQ_USE_DMA) {
+		dma_unmap_sg(&(host->chip->pdev)->dev, data->sg, data->sg_len,
+			     (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE :
+			     DMA_TO_DEVICE);
+	}
+	if ((host->flags & SDHCI_USE_EXTERNAL_DMA) &&
+	    (host->dma_size >= mxc_wml_value) && (data != NULL)) {
+		dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+			     host->dma_len, host->dma_dir);
+		host->dma_size = 0;
+	}
+
+	/*
+	 * Controller doesn't count down when in single block mode.
+	 */
+	if (data->blocks == 1)
+		blocks = (data->error == 0) ? 0 : 1;
+	else
+		blocks = readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16;
+	data->bytes_xfered = data->blksz * data->blocks;
+
+	tasklet_schedule(&host->finish_tasklet);
+}
+
+static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
+{
+	int flags, tmp;
+	u32 mask;
+	u32 mode = 0;
+	unsigned long timeout;
+
+	DBG("sdhci_send_command 0x%x is starting...\n", cmd->opcode);
+	WARN_ON(host->cmd);
+
+	/* Wait max 10 ms */
+	timeout = 500;
+
+	mask = SDHCI_CMD_INHIBIT;
+	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
+		mask |= SDHCI_DATA_INHIBIT;
+
+	/* We shouldn't wait for data inihibit for stop commands, even
+	   though they might use busy signaling */
+	if (host->mrq->data && (cmd == host->mrq->data->stop))
+		mask &= ~SDHCI_DATA_INHIBIT;
+
+	while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
+		if (timeout == 0) {
+			printk(KERN_ERR "%s: Controller never released "
+			       "inhibit bit(s).\n", mmc_hostname(host->mmc));
+			sdhci_dumpregs(host);
+			cmd->error = -EIO;
+			tasklet_schedule(&host->finish_tasklet);
+			return;
+		}
+		timeout--;
+		udelay(20);
+	}
+
+	mod_timer(&host->timer, jiffies + 10 * HZ);
+
+	host->cmd = cmd;
+
+	sdhci_prepare_data(host, cmd->data);
+
+	writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
+
+	/* Set up the transfer mode */
+	if (cmd->data != NULL) {
+		mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DPSEL;
+		if (cmd->data->blocks > 1) {
+			mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
+			if (cmd->opcode == 0x35) {
+				tmp = readl(host->ioaddr + SDHCI_INT_ENABLE);
+				tmp &= ~SDHCI_INT_ACMD12ERR;
+				writel(tmp, host->ioaddr + SDHCI_INT_ENABLE);
+			} else {
+				tmp = readl(host->ioaddr + SDHCI_INT_ENABLE);
+				tmp |= SDHCI_INT_ACMD12ERR;
+				writel(tmp, host->ioaddr + SDHCI_INT_ENABLE);
+			}
+		}
+		if (cmd->data->flags & MMC_DATA_READ)
+			mode |= SDHCI_TRNS_READ;
+		else
+			mode &= ~SDHCI_TRNS_READ;
+		if (host->flags & SDHCI_REQ_USE_DMA)
+			mode |= SDHCI_TRNS_DMA;
+		if (host->flags & SDHCI_USE_EXTERNAL_DMA)
+			DBG("Prepare data completely in %s transfer mode.\n",
+			    "EXTTERNAL DMA");
+	}
+
+	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
+		printk(KERN_ERR "%s: Unsupported response type!\n",
+		       mmc_hostname(host->mmc));
+		cmd->error = -EINVAL;
+		tasklet_schedule(&host->finish_tasklet);
+		return;
+	}
+
+	if (!(cmd->flags & MMC_RSP_PRESENT))
+		flags = SDHCI_CMD_RESP_NONE;
+	else if (cmd->flags & MMC_RSP_136)
+		flags = SDHCI_CMD_RESP_LONG;
+	else if (cmd->flags & MMC_RSP_BUSY)
+		flags = SDHCI_CMD_RESP_SHORT_BUSY;
+	else
+		flags = SDHCI_CMD_RESP_SHORT;
+
+	if (cmd->flags & MMC_RSP_CRC)
+		flags |= SDHCI_CMD_CRC;
+	if (cmd->flags & MMC_RSP_OPCODE)
+		flags |= SDHCI_CMD_INDEX;
+	if (cmd->data)
+		flags |= SDHCI_CMD_DATA;
+
+	mode |= SDHCI_MAKE_CMD(cmd->opcode, flags);
+	if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR) {
+		/* Eanble the DDR mode */
+		mode |= SDHCI_TRNS_DDR_EN;
+	} else
+		mode &= ~SDHCI_TRNS_DDR_EN;
+	DBG("Complete sending cmd, transfer mode would be 0x%x.\n", mode);
+	writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
+}
+
+static void sdhci_finish_command(struct sdhci_host *host)
+{
+	int i;
+
+	BUG_ON(host->cmd == NULL);
+
+	if (host->cmd->flags & MMC_RSP_PRESENT) {
+		if (host->cmd->flags & MMC_RSP_136) {
+			/* CRC is stripped so we need to do some shifting. */
+			for (i = 0; i < 4; i++) {
+				host->cmd->resp[i] = readl(host->ioaddr +
+							   SDHCI_RESPONSE + (3 -
+									     i)
+							   * 4) << 8;
+				if (i != 3)
+					host->cmd->resp[i] |=
+					    readb(host->ioaddr +
+						  SDHCI_RESPONSE + (3 - i) * 4 -
+						  1);
+			}
+		} else {
+			host->cmd->resp[0] =
+			    readl(host->ioaddr + SDHCI_RESPONSE);
+		}
+	}
+
+	host->cmd->error = 0;
+
+	if (host->data && host->data_early)
+		sdhci_finish_data(host);
+
+	if (!host->cmd->data)
+		tasklet_schedule(&host->finish_tasklet);
+
+	host->cmd = NULL;
+}
+
+static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	/*This variable holds the value of clock divider, prescaler */
+	int div = 0, prescaler = 0;
+	int clk_rate = 0;
+	u32 clk;
+	unsigned long timeout;
+	struct mmc_ios ios = host->mmc->ios;
+
+	if (clock == 0) {
+		goto out;
+	} else {
+		if (!host->plat_data->clk_flg) {
+			clk_enable(host->clk);
+			host->plat_data->clk_flg = 1;
+		}
+	}
+
+	if (clock == host->clock && !(ios.bus_width & MMC_BUS_WIDTH_DDR))
+		return;
+
+	clk_rate = clk_get_rate(host->clk);
+	clk = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & ~SDHCI_CLOCK_MASK;
+	if (cpu_is_mx53() || cpu_is_mx50())
+		writel(clk | SDHCI_CLOCK_SDCLKFS1,
+				host->ioaddr + SDHCI_CLOCK_CONTROL);
+	else
+		writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	if (clock == host->min_clk)
+		prescaler = 16;
+	else if (cpu_is_mx53() || cpu_is_mx50())
+		prescaler = 1;
+	else
+		prescaler = 0;
+	while (prescaler <= 0x80) {
+		for (div = 0; div <= 0xF; div++) {
+			int x;
+			if (prescaler != 0)
+				x = (clk_rate / (div + 1)) / (prescaler * 2);
+			else
+				x = clk_rate / (div + 1);
+
+			DBG("x=%d, clock=%d %d\n", x, clock, div);
+			if (x <= clock)
+				break;
+		}
+		if (div < 0x10)
+			break;
+		if (prescaler == 0)
+			prescaler = 1;
+		else
+			prescaler <<= 1;
+	}
+	DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div);
+	clk |= (prescaler << 8) | (div << 4);
+
+	if (host->plat_data->clk_always_on
+		| (host->mmc->card && mmc_card_sdio(host->mmc->card)))
+		clk |= SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN
+			| SDHCI_CLOCK_IPG_EN;
+	else
+		clk &= ~(SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN
+			| SDHCI_CLOCK_IPG_EN);
+
+	/* Configure the clock delay line */
+	if ((host->plat_data->vendor_ver >= ESDHC_VENDOR_V3)
+		&& host->plat_data->dll_override_en)
+		writel((host->plat_data->dll_delay_cells << 10)
+			| DLL_CTRL_SLV_OVERRIDE,
+			host->ioaddr + SDHCI_DLL_CONTROL);
+
+	/* Configure the clock control register */
+	clk |=
+	    (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_MASK));
+	if (host->plat_data->vendor_ver < ESDHC_VENDOR_V22)
+		writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
+	else
+		writel(clk | SDHCI_CLOCK_SD_EN,
+		       host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	/* Wait max 10 ms */
+	timeout = 500;
+	while (timeout > 0) {
+		timeout--;
+		udelay(20);
+	}
+
+      out:
+	if (prescaler != 0)
+		 host->clock = (clk_rate / (div + 1)) / (prescaler * 2);
+	 else
+		 host->clock = clk_rate / (div + 1);
+}
+
+static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
+{
+	int voltage = 0;
+
+	/* There is no PWR CTL REG */
+	if (host->power == power)
+		return;
+
+	if (host->regulator_mmc) {
+		if (power == (unsigned short)-1) {
+			regulator_disable(host->regulator_mmc);
+			DBG("mmc power off\n");
+		} else {
+			if (power == 7)
+				voltage = 1800000;
+			else if (power >= 8)
+				voltage = 2000000 + (power - 8) * 100000;
+			regulator_set_voltage(host->regulator_mmc,
+					      voltage, voltage);
+
+			if (regulator_enable(host->regulator_mmc) == 0) {
+				DBG("mmc power on\n");
+				msleep(1);
+			}
+		}
+	}
+
+	host->power = power;
+}
+
+/*****************************************************************************\
+ *                                                                           *
+ * MMC callbacks                                                             *
+ *                                                                           *
+\*****************************************************************************/
+
+static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+
+	host = mmc_priv(mmc);
+
+	/* Enable the clock */
+	if (!host->plat_data->clk_flg) {
+		clk_enable(host->clk);
+		host->plat_data->clk_flg = 1;
+	}
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	WARN_ON(host->mrq != NULL);
+
+	sdhci_activate_led(host);
+	if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) {
+		if (mrq->cmd && mrq->data) {
+			if (mrq->data->flags & MMC_DATA_READ)
+				last_op_dir = 1;
+			else {
+				if (last_op_dir)
+					sdhci_reset(host,
+						    SDHCI_RESET_CMD |
+						    SDHCI_RESET_DATA);
+			}
+		}
+	}
+
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA)
+		spin_unlock_irqrestore(&host->lock, flags);
+
+	host->mrq = mrq;
+	if (!(host->flags & SDHCI_CD_PRESENT)) {
+		host->mrq->cmd->error = -ENOMEDIUM;
+		tasklet_schedule(&host->finish_tasklet);
+	} else
+		sdhci_send_command(host, mrq->cmd);
+
+	if (!(host->flags & SDHCI_USE_EXTERNAL_DMA))
+		spin_unlock_irqrestore(&host->lock, flags);
+
+	mmiowb();
+}
+
+static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+	u32 tmp;
+	mxc_dma_device_t dev_id = 0;
+
+	DBG("%s: clock %u, bus %u, power %u, vdd %u\n", DRIVER_NAME,
+	    ios->clock, ios->bus_width, ios->power_mode, ios->vdd);
+
+	host = mmc_priv(mmc);
+
+	/* Configure the External DMA mode */
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA) {
+		host->dma_dir = DMA_NONE;
+		if (mmc->ios.bus_width != host->mode) {
+			mxc_dma_free(host->dma);
+			if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
+				if (host->id == 0)
+					dev_id = MXC_DMA_MMC1_WIDTH_4;
+				else
+					dev_id = MXC_DMA_MMC2_WIDTH_4;
+			} else {
+				if (host->id == 0)
+					dev_id = MXC_DMA_MMC1_WIDTH_1;
+				else
+					dev_id = MXC_DMA_MMC2_WIDTH_1;
+			}
+			host->dma = mxc_dma_request(dev_id, "MXC MMC");
+			if (host->dma < 0)
+				DBG("Cannot allocate MMC DMA channel\n");
+			mxc_dma_callback_set(host->dma, sdhci_dma_irq,
+					     (void *)host);
+			/* Configure the WML rege */
+			if (mxc_wml_value == 512)
+				writel(SDHCI_WML_128_WORDS,
+				       host->ioaddr + SDHCI_WML);
+			else
+				writel(SDHCI_WML_16_WORDS,
+				       host->ioaddr + SDHCI_WML);
+		}
+	}
+
+	host->mode = mmc->ios.bus_width;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	/*
+	 * Reset the chip on each power off.
+	 * Should clear out any weird states.
+	 */
+	if (ios->power_mode == MMC_POWER_OFF) {
+		writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+		sdhci_init(host);
+	}
+
+	sdhci_set_clock(host, ios->clock);
+
+	if (ios->power_mode == MMC_POWER_OFF)
+		sdhci_set_power(host, -1);
+	else {
+		sdhci_set_power(host, ios->vdd);
+		if (!readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)) {
+			tmp = readl(host->ioaddr + SDHCI_INT_ENABLE);
+			if (host->sdio_enable)
+				writel(tmp, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+			else
+				writel(tmp & ~SDHCI_INT_CARD_INT,
+				       host->ioaddr + SDHCI_SIGNAL_ENABLE);
+		}
+	}
+
+	tmp = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+
+	if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4) {
+		tmp &= ~SDHCI_CTRL_8BITBUS;
+		tmp |= SDHCI_CTRL_4BITBUS;
+	} else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8) {
+		tmp &= ~SDHCI_CTRL_4BITBUS;
+		tmp |= SDHCI_CTRL_8BITBUS;
+	} else if (ios->bus_width == MMC_BUS_WIDTH_1) {
+		tmp &= ~SDHCI_CTRL_4BITBUS;
+		tmp &= ~SDHCI_CTRL_8BITBUS;
+	}
+
+	if (host->flags & SDHCI_USE_DMA)
+		tmp |= SDHCI_CTRL_ADMA;
+
+	writel(tmp, host->ioaddr + SDHCI_HOST_CONTROL);
+
+	/*
+	 * Some (ENE) controllers go apeshit on some ios operation,
+	 * signalling timeout and CRC errors even on CMD0. Resetting
+	 * it on each ios seems to solve the problem.
+	 */
+	if (host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
+		sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+	mmiowb();
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+	struct sdhci_host *host;
+
+	host = mmc_priv(mmc);
+
+	if (host->plat_data->wp_status)
+		return host->plat_data->wp_status(mmc->parent);
+	else
+		return 0;
+}
+
+static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+	u32 ier, prot, present;
+
+	host = mmc_priv(mmc);
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (enable) {
+		if (host->sdio_enable++)
+			goto exit_unlock;
+	} else {
+		if (--(host->sdio_enable))
+			goto exit_unlock;
+	}
+
+	ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
+	prot = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+
+	if (enable) {
+		ier |= SDHCI_INT_CARD_INT;
+		prot |= SDHCI_CTRL_D3CD;
+		present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
+		if ((present & SDHCI_CARD_INT_MASK) != SDHCI_CARD_INT_ID)
+			writel(SDHCI_INT_CARD_INT,
+			       host->ioaddr + SDHCI_INT_STATUS);
+	} else {
+		ier &= ~SDHCI_INT_CARD_INT;
+		prot &= ~SDHCI_CTRL_D3CD;
+	}
+
+	writel(prot, host->ioaddr + SDHCI_HOST_CONTROL);
+	writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+
+	mmiowb();
+      exit_unlock:
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static const struct mmc_host_ops sdhci_ops = {
+	.request = sdhci_request,
+	.set_ios = sdhci_set_ios,
+	.get_ro = sdhci_get_ro,
+	.enable_sdio_irq = sdhci_enable_sdio_irq,
+};
+
+/*****************************************************************************\
+ *                                                                           *
+ * Tasklets                                                                  *
+ *                                                                           *
+\*****************************************************************************/
+
+static void sdhci_tasklet_card(unsigned long param)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+	unsigned int cd_status = 0;
+
+	host = (struct sdhci_host *)param;
+
+	if (host->flags & SDHCI_CD_PRESENT)
+		host->flags &= ~SDHCI_CD_PRESENT;
+	else
+		host->flags |= SDHCI_CD_PRESENT;
+	/* Detect there is a card in slot or not */
+	DBG("cd_status=%d %s\n", cd_status,
+	    (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (!(host->flags & SDHCI_CD_PRESENT)) {
+		if (host->mrq) {
+			printk(KERN_ERR "%s: Card removed during transfer!\n",
+			       mmc_hostname(host->mmc));
+			printk(KERN_ERR "%s: Resetting controller.\n",
+			       mmc_hostname(host->mmc));
+
+			sdhci_reset(host, SDHCI_RESET_CMD);
+			sdhci_reset(host, SDHCI_RESET_DATA);
+
+			host->mrq->cmd->error = -ENOMEDIUM;
+			tasklet_schedule(&host->finish_tasklet);
+		}
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+}
+
+static void sdhci_tasklet_finish(unsigned long param)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+	int req_done;
+	struct mmc_request *mrq;
+
+	host = (struct sdhci_host *)param;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	del_timer(&host->timer);
+
+	mrq = host->mrq;
+
+	/*
+	 * The controller needs a reset of internal state machines
+	 * upon error conditions.
+	 */
+	if (mrq->cmd->error ||
+	    (mrq->data && (mrq->data->error ||
+			   (mrq->data->stop && mrq->data->stop->error))) ||
+	    (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
+
+		/* Some controllers need this kick or reset won't work here */
+		if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
+			unsigned int clock;
+
+			/* This is to force an update */
+			clock = host->clock;
+			host->clock = 0;
+			sdhci_set_clock(host, clock);
+		}
+
+		/* Spec says we should do both at the same time, but Ricoh
+		   controllers do not like that. */
+		sdhci_reset(host, SDHCI_RESET_CMD);
+		sdhci_reset(host, SDHCI_RESET_DATA);
+	}
+
+	host->mrq = NULL;
+	host->cmd = NULL;
+	host->data = NULL;
+
+	sdhci_deactivate_led(host);
+
+	mmiowb();
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	/* Stop the clock when the req is done */
+	req_done = !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
+		(SDHCI_DATA_ACTIVE | SDHCI_DOING_WRITE | SDHCI_DOING_READ));
+	if (req_done && host->plat_data->clk_flg &&
+		!(host->plat_data->clk_always_on) &&
+		!(host->mmc->card && mmc_card_sdio(host->mmc->card))) {
+		clk_disable(host->clk);
+		host->plat_data->clk_flg = 0;
+	}
+
+	mmc_request_done(host->mmc, mrq);
+}
+
+static void sdhci_timeout_timer(unsigned long data)
+{
+	struct sdhci_host *host;
+	unsigned long tmp, flags;
+
+	host = (struct sdhci_host *)data;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (host->mrq) {
+		printk(KERN_ERR "%s: Timeout waiting for hardware "
+		       "interrupt.\n", mmc_hostname(host->mmc));
+		sdhci_dumpregs(host);
+
+		if (host->data) {
+			host->data->error = -ETIMEDOUT;
+			sdhci_finish_data(host);
+		} else {
+			if (host->cmd)
+				host->cmd->error = -ETIMEDOUT;
+			else
+				host->mrq->cmd->error = -ETIMEDOUT;
+
+			tasklet_schedule(&host->finish_tasklet);
+		}
+
+		if (!readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)) {
+			printk(KERN_ERR "%s, ERROR SIG_INT is 0.\n", __func__);
+			tmp = readl(host->ioaddr + SDHCI_INT_ENABLE);
+			if (host->sdio_enable)
+				writel(tmp, host->ioaddr + SDHCI_SIGNAL_ENABLE);
+			else
+				writel(tmp & ~SDHCI_INT_CARD_INT,
+				       host->ioaddr + SDHCI_SIGNAL_ENABLE);
+			if (!host->plat_data->status(host->mmc->parent))
+				schedule_work(&host->cd_wq);
+		}
+	}
+
+	mmiowb();
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void sdhci_cd_timer(unsigned long data)
+{
+	struct sdhci_host *host;
+
+	host = (struct sdhci_host *)data;
+	host->flags |= SDHCI_CD_TIMEOUT;
+	schedule_work(&host->cd_wq);
+}
+
+/*****************************************************************************\
+ *                                                                           *
+ * Interrupt handling                                                        *
+ *                                                                           *
+\*****************************************************************************/
+
+static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
+{
+	BUG_ON(intmask == 0);
+
+	if (!host->cmd) {
+		printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
+		       "though no command operation was in progress.\n",
+		       mmc_hostname(host->mmc), (unsigned)intmask);
+		sdhci_dumpregs(host);
+		return;
+	}
+
+	if (intmask & SDHCI_INT_TIMEOUT)
+		host->cmd->error = -ETIMEDOUT;
+	else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
+			    SDHCI_INT_INDEX))
+		host->cmd->error = -EILSEQ;
+
+	if (intmask & SDHCI_INT_ACMD12ERR) {
+		int tmp = 0;
+		tmp = readl(host->ioaddr + SDHCI_ACMD12_ERR);
+		if (tmp & (SDHCI_ACMD12_ERR_CE | SDHCI_ACMD12_ERR_IE |
+			   SDHCI_ACMD12_ERR_EBE))
+			host->cmd->error = -EILSEQ;
+		else if (tmp & SDHCI_ACMD12_ERR_TOE)
+			host->cmd->error = -ETIMEDOUT;
+	}
+
+	if (host->cmd->error)
+		tasklet_schedule(&host->finish_tasklet);
+	else if (intmask & SDHCI_INT_RESPONSE)
+		sdhci_finish_command(host);
+}
+
+static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
+{
+	u32 intsave = 0;
+
+	BUG_ON(intmask == 0);
+
+	if (!host->data) {
+		/*
+		 * A data end interrupt is sent together with the response
+		 * for the stop command.
+		 */
+		if (intmask & SDHCI_INT_DATA_END)
+			return;
+
+		printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
+		       "though no data operation was in progress.\n",
+		       mmc_hostname(host->mmc), (unsigned)intmask);
+		sdhci_dumpregs(host);
+		sdhci_reset(host, SDHCI_RESET_CMD);
+		sdhci_reset(host, SDHCI_RESET_DATA);
+		return;
+	}
+
+	/* Mask the INT */
+	intsave = readl(host->ioaddr + SDHCI_INT_ENABLE);
+	writel(intsave & (~(intmask & SDHCI_INT_DATA_RE_MASK)),
+	       host->ioaddr + SDHCI_INT_ENABLE);
+
+	if (intmask & SDHCI_INT_DATA_TIMEOUT)
+		host->data->error = -ETIMEDOUT;
+	else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
+		host->data->error = -EILSEQ;
+
+	if (host->data->error)
+		sdhci_finish_data(host);
+	else {
+		if ((host->flags & SDHCI_USE_EXTERNAL_DMA) &&
+		    (host->dma_size >= mxc_wml_value)) {
+			/* Use DMA if transfer size is greater than fifo size */
+			if (intmask & (SDHCI_INT_DATA_AVAIL |
+				       SDHCI_INT_SPACE_AVAIL)) {
+				intsave &= ~SDHCI_INT_DATA_RE_MASK;
+				if (mxc_dma_enable(host->dma) < 0) {
+					printk(KERN_ERR "ENABLE SDMA ERR.\n");
+					intsave |= SDHCI_INT_DATA_RE_MASK;
+				}
+			}
+		} else {
+			if (intmask & (SDHCI_INT_DATA_AVAIL |
+				       SDHCI_INT_SPACE_AVAIL))
+				sdhci_transfer_pio(host);
+		}
+
+		/*
+		 * We currently don't do anything fancy with DMA
+		 * boundaries, but as we can't disable the feature
+		 * we need to at least restart the transfer.
+		 */
+		if ((intmask & SDHCI_INT_DMA_END) &&
+		    (!(intmask & SDHCI_INT_DATA_END)))
+			writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
+			       host->ioaddr + SDHCI_DMA_ADDRESS);
+
+		if (intmask & SDHCI_INT_DATA_END) {
+			if (host->data->flags & MMC_DATA_READ)
+				writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL)
+				       & ~SDHCI_CLOCK_HLK_EN,
+				       host->ioaddr + SDHCI_CLOCK_CONTROL);
+			if (host->cmd) {
+				/*
+				 * Data managed to finish before the
+				 * command completed. Make sure we do
+				 * things in the proper order.
+				 */
+				host->data_early = 1;
+			} else {
+
+				if (host->plat_data->vendor_ver
+				    < ESDHC_VENDOR_V22) {
+					/*
+					 * There are the DATA END INT when
+					 * writing is not complete. Double
+					 * check on it. TO2 has been fixed it.
+					 */
+					intmask = readl(host->ioaddr +
+							SDHCI_PRESENT_STATE);
+					if (intmask & SDHCI_DATA_ACTIVE)
+						goto data_irq_out;
+				}
+				sdhci_finish_data(host);
+			}
+		}
+	}
+      data_irq_out:
+	/* Enable the INT */
+	writel(intsave, host->ioaddr + SDHCI_INT_ENABLE);
+}
+
+/*!
+* This function is called by DMA Interrupt Service Routine to indicate
+* requested DMA transfer is completed.
+*
+* @param   devid  pointer to device specific structure
+* @param   error any DMA error
+* @param   cnt   amount of data that was transferred
+*/
+static void sdhci_dma_irq(void *devid, int error, unsigned int cnt)
+{
+	u32 intsave = 0;
+	int ret;
+	struct sdhci_host *host = devid;
+
+	DBG("%s: error: %d Transferred bytes:%d\n", DRIVER_NAME, error, cnt);
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA) {
+		/*
+		 * Stop the DMA transfer here, the data_irq would be called
+		 * to process the others
+		 */
+		ret = mxc_dma_disable(host->dma);
+		if (ret < 0)
+			printk(KERN_ERR "Disable dma channel err %d\n", ret);
+
+		if (error) {
+			DBG("Error in DMA transfer\n");
+			return;
+		}
+		intsave = readl(host->ioaddr + SDHCI_INT_ENABLE);
+		intsave |= SDHCI_INT_DATA_RE_MASK;
+		writel(intsave, host->ioaddr + SDHCI_INT_ENABLE);
+	}
+}
+
+/* woke queue handler func */
+static void esdhc_cd_callback(struct work_struct *work)
+{
+	unsigned long flags;
+	unsigned int cd_status = 0;
+	struct sdhci_host *host = container_of(work, struct sdhci_host, cd_wq);
+
+	do {
+		if (host->detect_irq == 0)
+			break;
+		cd_status = host->plat_data->status(host->mmc->parent);
+		if (cd_status)
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING);
+		else
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING);
+	} while (cd_status != host->plat_data->status(host->mmc->parent));
+
+	cd_status = host->plat_data->status(host->mmc->parent);
+
+	DBG("cd_status=%d %s\n", cd_status, cd_status ? "removed" : "inserted");
+	/* If there is no card, call the card detection func
+	 * immediately. */
+	if (!cd_status) {
+		/* If there is a card in the slot, the timer is start
+		 * to work. Then the card detection would be carried
+		 * after the timer is timeout.
+		 * */
+		if (host->flags & SDHCI_CD_TIMEOUT)
+			host->flags &= ~SDHCI_CD_TIMEOUT;
+		else {
+			mod_timer(&host->cd_timer, jiffies + HZ / 4);
+			return;
+		}
+	}
+
+	cd_status = host->plat_data->status(host->mmc->parent);
+	if (cd_status)
+		host->flags &= ~SDHCI_CD_PRESENT;
+	else
+		host->flags |= SDHCI_CD_PRESENT;
+	/* Detect there is a card in slot or not */
+	DBG("cd_status=%d %s\n", cd_status,
+	    (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (!(host->flags & SDHCI_CD_PRESENT)) {
+		printk(KERN_INFO
+		       "%s: Card removed and resetting controller.\n",
+		       mmc_hostname(host->mmc));
+		if (host->mrq) {
+			struct mmc_data *data;
+			data = host->data;
+			host->data = NULL;
+
+			printk(KERN_ERR
+			       "%s: Card removed during transfer!\n",
+			       mmc_hostname(host->mmc));
+			printk(KERN_ERR
+			       "%s: Resetting controller.\n",
+			       mmc_hostname(host->mmc));
+
+			if ((host->flags & SDHCI_USE_EXTERNAL_DMA) &&
+			    (data != NULL)) {
+				dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+					     host->dma_len, host->dma_dir);
+				host->dma_size = 0;
+			}
+			sdhci_reset(host, SDHCI_RESET_CMD);
+			sdhci_reset(host, SDHCI_RESET_DATA);
+
+			host->mrq->cmd->error = -ENOMEDIUM;
+			tasklet_schedule(&host->finish_tasklet);
+		}
+
+		if (host->init_flag > 0)
+			/* The initialization of sdhc controller has been
+			 * done in the resume func */
+			host->init_flag--;
+		else
+			sdhci_init(host);
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (host->flags & SDHCI_CD_PRESENT) {
+		del_timer(&host->cd_timer);
+		mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+	} else
+		mmc_detect_change(host->mmc, 0);
+}
+
+/*!
+* Card detection interrupt service routine registered to handle
+* the SDHC interrupts. This interrupt routine handles card
+* insertion and card removal interrupts.
+*
+* @param   irq    the interrupt number
+* @param   devid  driver private data
+*
+* @return  The function returns \b IRQ_RETVAL(1)
+*/
+static irqreturn_t sdhci_cd_irq(int irq, void *dev_id)
+{
+	struct sdhci_host *host = dev_id;
+
+	schedule_work(&host->cd_wq);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t sdhci_irq(int irq, void *dev_id)
+{
+	irqreturn_t result;
+	struct sdhci_host *host = dev_id;
+	u32 intmask;
+	int cardint = 0;
+
+	spin_lock(&host->lock);
+
+	intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
+
+	if (!intmask || intmask == 0xffffffff) {
+		result = IRQ_NONE;
+		goto out;
+	}
+
+	DBG("*** %s got interrupt: 0x%08x\n", mmc_hostname(host->mmc), intmask);
+
+	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+		writel(intmask &
+		       (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
+		       host->ioaddr + SDHCI_INT_STATUS);
+		tasklet_schedule(&host->card_tasklet);
+	}
+
+	intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+
+	if (intmask & SDHCI_INT_CMD_MASK) {
+		writel(intmask & SDHCI_INT_CMD_MASK,
+		       host->ioaddr + SDHCI_INT_STATUS);
+		sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
+	}
+
+	if (intmask & SDHCI_INT_DATA_MASK) {
+		writel(intmask & SDHCI_INT_DATA_MASK,
+		       host->ioaddr + SDHCI_INT_STATUS);
+		if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) {
+			if (!
+			    (readl(host->ioaddr + SDHCI_TRANSFER_MODE) &
+			     SDHCI_TRNS_READ))
+				intmask &= ~SDHCI_INT_DATA_END_BIT;
+		}
+		if (intmask & SDHCI_INT_DATA_MASK)
+			sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+	}
+
+	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
+
+	intmask &= ~SDHCI_INT_ERROR;
+
+	if (intmask & SDHCI_INT_BUS_POWER) {
+		printk(KERN_ERR "%s: Card is consuming too much power!\n",
+		       mmc_hostname(host->mmc));
+		writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
+	}
+
+	intmask &= ~SDHCI_INT_BUS_POWER;
+
+	if (intmask & SDHCI_INT_CARD_INT)
+		cardint = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) &
+		    SDHCI_INT_CARD_INT;
+
+	intmask &= ~SDHCI_INT_CARD_INT;
+
+	if (intmask) {
+		printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
+		       mmc_hostname(host->mmc), intmask);
+		sdhci_dumpregs(host);
+
+		writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
+	}
+
+	result = IRQ_HANDLED;
+
+	mmiowb();
+      out:
+	spin_unlock(&host->lock);
+
+	/*
+	 * We have to delay this as it calls back into the driver.
+	 */
+	if (cardint)
+		mmc_signal_sdio_irq(host->mmc);
+
+	return result;
+}
+
+/*****************************************************************************\
+ *                                                                           *
+ * Suspend/resume                                                            *
+ *                                                                           *
+\*****************************************************************************/
+
+#ifdef CONFIG_PM
+
+static int sdhci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct sdhci_chip *chip;
+	int i, ret;
+
+	chip = dev_get_drvdata(&pdev->dev);
+	if (!chip)
+		return 0;
+
+	DBG("Suspending...\n");
+
+	for (i = 0; i < chip->num_slots; i++) {
+		if (!chip->hosts[i])
+			continue;
+		ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
+		if (ret) {
+			for (i--; i >= 0; i--)
+				mmc_resume_host(chip->hosts[i]->mmc);
+			return ret;
+		}
+	}
+
+	for (i = 0; i < chip->num_slots; i++) {
+		if (!chip->hosts[i])
+			continue;
+		free_irq(chip->hosts[i]->irq, chip->hosts[i]);
+	}
+
+	return 0;
+}
+
+static int sdhci_resume(struct platform_device *pdev)
+{
+	struct sdhci_chip *chip;
+	int i, ret;
+
+	chip = dev_get_drvdata(&pdev->dev);
+	if (!chip)
+		return 0;
+
+	DBG("Resuming...\n");
+
+	for (i = 0; i < chip->num_slots; i++) {
+		if (!chip->hosts[i])
+			continue;
+		ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
+				  IRQF_SHARED,
+				  mmc_hostname(chip->hosts[i]->mmc),
+				  chip->hosts[i]);
+		if (ret)
+			return ret;
+		sdhci_init(chip->hosts[i]);
+		chip->hosts[i]->init_flag = 2;
+		mmiowb();
+		ret = mmc_resume_host(chip->hosts[i]->mmc);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#else				/* CONFIG_PM */
+
+#define sdhci_suspend NULL
+#define sdhci_resume NULL
+
+#endif				/* CONFIG_PM */
+
+/*****************************************************************************\
+ *                                                                           *
+ * Device probing/removal                                                    *
+ *                                                                           *
+\*****************************************************************************/
+
+static int __devinit sdhci_probe_slot(struct platform_device
+				      *pdev, int slot)
+{
+	struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data;
+	int ret = 0;
+	unsigned int version, caps;
+	struct sdhci_chip *chip;
+	struct mmc_host *mmc;
+	struct sdhci_host *host;
+	mxc_dma_device_t dev_id = 0;
+
+	if (!mmc_plat)
+		return -EINVAL;
+
+	chip = dev_get_drvdata(&pdev->dev);
+	BUG_ON(!chip);
+
+	mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
+	if (!mmc)
+		return -ENOMEM;
+
+	host = mmc_priv(mmc);
+	host->mmc = mmc;
+	host->id = pdev->id;
+	host->dma = -1;
+	host->plat_data = mmc_plat;
+	if (!host->plat_data) {
+		ret = -EINVAL;
+		goto out0;
+	}
+
+	host->chip = chip;
+	chip->hosts[slot] = host;
+
+	/* Get pwr supply for eSDHC */
+	if (NULL != mmc_plat->power_mmc) {
+		host->regulator_mmc =
+		    regulator_get(&pdev->dev, mmc_plat->power_mmc);
+		if (IS_ERR(host->regulator_mmc)) {
+			ret = PTR_ERR(host->regulator_mmc);
+			goto out1;
+		}
+		if (regulator_enable(host->regulator_mmc) == 0) {
+			DBG("mmc power on\n");
+			msleep(1);
+		}
+	}
+
+	/* Active the eSDHC bus */
+	gpio_sdhc_active(pdev->id);
+
+	/* Get the SDHC clock from clock system APIs */
+	host->clk = clk_get(&pdev->dev, mmc_plat->clock_mmc);
+	if (NULL == host->clk) {
+		printk(KERN_ERR "MXC MMC can't get clock.\n");
+		goto out1;
+	} else
+		clk_enable(host->clk);
+	DBG("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk));
+
+	host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!host->res) {
+		ret = -ENOMEM;
+		goto out2;
+	}
+	host->irq = platform_get_irq(pdev, 0);
+	if (!host->irq) {
+		ret = -ENOMEM;
+		goto out2;
+	}
+	host->detect_irq = platform_get_irq(pdev, 1);
+	if (!host->detect_irq) {
+		if (mmc_plat->card_inserted_state)
+			host->flags |= SDHCI_CD_PRESENT;
+		else
+			host->flags &= ~SDHCI_CD_PRESENT;
+		if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM))
+			mxc_fix_chips[pdev->id] = chip;
+		goto no_detect_irq;
+	}
+
+	do {
+		ret = host->plat_data->status(host->mmc->parent);
+		if (ret)
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING);
+		else
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING);
+	} while (ret != host->plat_data->status(host->mmc->parent));
+
+	ret = host->plat_data->status(host->mmc->parent);
+	if (ret)
+		host->flags &= ~SDHCI_CD_PRESENT;
+	else
+		host->flags |= SDHCI_CD_PRESENT;
+
+      no_detect_irq:
+	DBG("slot %d at 0x%x, irq %d \n", slot, host->res->start, host->irq);
+	if (!request_mem_region(host->res->start,
+				host->res->end -
+				host->res->start + 1, pdev->name)) {
+		printk(KERN_ERR "request_mem_region failed\n");
+		ret = -ENOMEM;
+		goto out2;
+	}
+	host->ioaddr = (void *)ioremap(host->res->start, host->res->end -
+				       host->res->start + 1);
+	if (!host->ioaddr) {
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	sdhci_reset(host, SDHCI_RESET_ALL);
+
+	version = readl(host->ioaddr + SDHCI_HOST_VERSION);
+	host->plat_data->vendor_ver = (version & SDHCI_VENDOR_VER_MASK) >>
+	    SDHCI_VENDOR_VER_SHIFT;
+	version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
+	if (version != 1) {
+		printk(KERN_ERR "%s: Unknown controller version (%d). "
+		       "You may experience problems.\n", mmc_hostname(mmc),
+		       version);
+	}
+
+	caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+
+	if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
+		host->flags |= SDHCI_USE_DMA;
+	else if (!(caps & SDHCI_CAN_DO_DMA))
+		DBG("Controller doesn't have DMA capability\n");
+	else if (chip->
+		 quirks & (SDHCI_QUIRK_INTERNAL_ADVANCED_DMA |
+			   SDHCI_QUIRK_INTERNAL_SIMPLE_DMA))
+		host->flags |= SDHCI_USE_DMA;
+	else if (chip->quirks & (SDHCI_QUIRK_EXTERNAL_DMA_MODE))
+		host->flags |= SDHCI_USE_EXTERNAL_DMA;
+	else
+		host->flags &= ~SDHCI_USE_DMA;
+
+	/*
+	 * These definitions of eSDHC are not compatible with the SD Host
+	 * Controller Spec v2.0
+	 */
+	host->min_clk = mmc_plat->min_clk;
+	host->max_clk = mmc_plat->max_clk;
+	host->timeout_clk = 1024 * 1000;	/* Just set the value temply. */
+
+	/*
+	 * Set host parameters.
+	 */
+	mmc->ops = &sdhci_ops;
+	mmc->f_min = host->min_clk;
+	mmc->f_max = host->max_clk;
+	mmc->caps = MMC_CAP_SDIO_IRQ;
+	mmc->caps |= mmc_plat->caps;
+
+	if (caps & SDHCI_CAN_DO_HISPD)
+		mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+
+	mmc->ocr_avail = mmc_plat->ocr_mask;
+	if (caps & SDHCI_CAN_VDD_330)
+		mmc->ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
+	if (caps & SDHCI_CAN_VDD_300)
+		mmc->ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
+	if (caps & SDHCI_CAN_VDD_180)
+		mmc->ocr_avail |= MMC_VDD_165_195;
+
+	if (mmc->ocr_avail == 0) {
+		printk(KERN_ERR "%s: Hardware doesn't report any "
+		       "support voltages.\n", mmc_hostname(mmc));
+		ret = -ENODEV;
+		goto out3;
+	}
+
+	spin_lock_init(&host->lock);
+
+	/*
+	 * Maximum number of segments. Hardware cannot do scatter lists.
+	 */
+	if (host->flags & SDHCI_USE_DMA)
+		mmc->max_hw_segs = 1;
+	else
+		mmc->max_hw_segs = 16;
+	mmc->max_phys_segs = 16;
+
+	/*
+	 * Maximum number of sectors in one transfer. Limited by DMA boundary
+	 * size (512KiB).
+	 */
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA)
+		mmc->max_req_size = 32 * 1024;
+	else
+		mmc->max_req_size = 524288;
+
+	/*
+	 * Maximum segment size. Could be one segment with the maximum number
+	 * of bytes.
+	 */
+	mmc->max_seg_size = mmc->max_req_size;
+
+	/*
+	 * Maximum block size. This varies from controller to controller and
+	 * is specified in the capabilities register.
+	 */
+	mmc->max_blk_size =
+	    (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
+	if (mmc->max_blk_size > 3) {
+		printk(KERN_WARNING "%s: Invalid maximum block size, "
+		       "assuming 512 bytes\n", mmc_hostname(mmc));
+		mmc->max_blk_size = 512;
+	} else
+		mmc->max_blk_size = 512 << mmc->max_blk_size;
+
+	/*
+	 * Maximum block count.
+	 */
+	mmc->max_blk_count = 65535;
+
+	/*
+	 * Apply a continous physical memory used for storing the ADMA
+	 * descriptor table.
+	 */
+	if (host->flags & SDHCI_USE_DMA) {
+		adma_des_table = kcalloc((2 * (mmc->max_phys_segs) + 1),
+					 sizeof(unsigned int), GFP_DMA);
+		if (adma_des_table == NULL) {
+			printk(KERN_ERR "Cannot allocate ADMA memory\n");
+			ret = -ENOMEM;
+			goto out3;
+		}
+	}
+
+	/*
+	 * Init tasklets.
+	 */
+	tasklet_init(&host->card_tasklet,
+		     sdhci_tasklet_card, (unsigned long)host);
+	tasklet_init(&host->finish_tasklet,
+		     sdhci_tasklet_finish, (unsigned long)host);
+
+	/* initialize the work queue */
+	INIT_WORK(&host->cd_wq, esdhc_cd_callback);
+
+	setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
+	setup_timer(&host->cd_timer, sdhci_cd_timer, (unsigned long)host);
+
+	if (host->detect_irq) {
+		ret = request_irq(host->detect_irq, sdhci_cd_irq, 0,
+				  pdev->name, host);
+		if (ret)
+			goto out4;
+	}
+
+	ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, pdev->name, host);
+	if (ret)
+		goto out5;
+
+	sdhci_init(host);
+
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA) {
+		/* Apply the 1-bit SDMA channel. */
+		if (host->id == 0)
+			dev_id = MXC_DMA_MMC1_WIDTH_1;
+		else
+			dev_id = MXC_DMA_MMC2_WIDTH_1;
+		host->dma = mxc_dma_request(dev_id, "MXC MMC");
+		if (host->dma < 0) {
+			DBG("Cannot allocate MMC DMA channel\n");
+			goto out6;
+		}
+		mxc_dma_callback_set(host->dma, sdhci_dma_irq, (void *)host);
+	}
+#ifdef CONFIG_MMC_DEBUG
+	sdhci_dumpregs(host);
+#endif
+
+	mmiowb();
+
+	if (mmc_add_host(mmc) < 0)
+		goto out6;
+	if (host->flags & SDHCI_USE_EXTERNAL_DMA)
+		printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n",
+		       mmc_hostname(mmc), host->detect_irq, host->irq,
+		       "EXTERNAL DMA");
+	else
+		printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n",
+		       mmc_hostname(mmc), host->detect_irq, host->irq,
+		       (host->flags & SDHCI_USE_DMA) ? "INTERNAL DMA" : "PIO");
+
+	return 0;
+
+      out6:
+	free_irq(host->irq, host);
+      out5:
+	if (host->detect_irq)
+		free_irq(host->detect_irq, host);
+	else {
+		if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM))
+			mxc_fix_chips[pdev->id] = chip;
+	}
+      out4:
+	del_timer_sync(&host->timer);
+	del_timer_sync(&host->cd_timer);
+	tasklet_kill(&host->card_tasklet);
+	tasklet_kill(&host->finish_tasklet);
+      out3:
+	if (host->flags & SDHCI_USE_DMA)
+		kfree(adma_des_table);
+	release_mem_region(host->res->start,
+			   host->res->end - host->res->start + 1);
+      out2:
+	clk_disable(host->clk);
+	host->plat_data->clk_flg = 0;
+	clk_put(host->clk);
+      out1:
+	gpio_sdhc_inactive(pdev->id);
+      out0:
+	mmc_free_host(mmc);
+	return ret;
+}
+
+static void sdhci_remove_slot(struct platform_device *pdev, int slot)
+{
+	struct sdhci_chip *chip;
+	struct mmc_host *mmc;
+	struct sdhci_host *host;
+
+	chip = dev_get_drvdata(&pdev->dev);
+	host = chip->hosts[slot];
+	mmc = host->mmc;
+
+	chip->hosts[slot] = NULL;
+
+	mmc_remove_host(mmc);
+
+	sdhci_reset(host, SDHCI_RESET_ALL);
+
+	if (host->detect_irq)
+		free_irq(host->detect_irq, host);
+	else {
+		if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM))
+			mxc_fix_chips[pdev->id] = NULL;
+	}
+	free_irq(host->irq, host);
+	if (chip->quirks & SDHCI_QUIRK_EXTERNAL_DMA_MODE) {
+		host->flags &= ~SDHCI_USE_EXTERNAL_DMA;
+		mxc_dma_free(host->dma);
+	}
+
+	del_timer_sync(&host->timer);
+
+	tasklet_kill(&host->card_tasklet);
+	tasklet_kill(&host->finish_tasklet);
+
+	if (host->flags & SDHCI_USE_DMA)
+		kfree(adma_des_table);
+	release_mem_region(host->res->start,
+			   host->res->end - host->res->start + 1);
+	clk_disable(host->clk);
+	host->plat_data->clk_flg = 0;
+	clk_put(host->clk);
+	mmc_free_host(mmc);
+	gpio_sdhc_inactive(pdev->id);
+}
+
+static int sdhci_probe(struct platform_device *pdev)
+{
+	int ret = 0, i;
+	u8 slots = 1;
+	struct sdhci_chip *chip;
+
+	printk(KERN_INFO DRIVER_NAME ": MXC SDHCI Controller Driver. \n");
+	BUG_ON(pdev == NULL);
+
+	chip = kzalloc(sizeof(struct sdhci_chip) +
+		       sizeof(struct sdhci_host *) * slots, GFP_KERNEL);
+	if (!chip) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	/* Distinguish different platform */
+	if (machine_is_mx37_3ds()) {
+		mxc_quirks = SDHCI_QUIRK_EXTERNAL_DMA_MODE;
+	} else {
+		mxc_quirks = SDHCI_QUIRK_INTERNAL_ADVANCED_DMA |
+		    SDHCI_QUIRK_INTERNAL_SIMPLE_DMA;
+	}
+	chip->pdev = pdev;
+	chip->quirks = mxc_quirks;
+
+	if (debug_quirks)
+		chip->quirks = debug_quirks;
+
+	chip->num_slots = slots;
+	dev_set_drvdata(&pdev->dev, chip);
+
+	for (i = 0; i < slots; i++) {
+		ret = sdhci_probe_slot(pdev, i);
+		if (ret) {
+			for (i--; i >= 0; i--)
+				sdhci_remove_slot(pdev, i);
+			goto free;
+		}
+	}
+
+	return 0;
+
+      free:
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(chip);
+
+      err:
+	return ret;
+}
+
+static int sdhci_remove(struct platform_device *pdev)
+{
+	int i;
+	struct sdhci_chip *chip;
+
+	chip = dev_get_drvdata(&pdev->dev);
+
+	if (chip) {
+		for (i = 0; i < chip->num_slots; i++)
+			sdhci_remove_slot(pdev, i);
+
+		dev_set_drvdata(&pdev->dev, NULL);
+
+		kfree(chip);
+	}
+
+	return 0;
+}
+
+static struct platform_driver sdhci_driver = {
+	.driver = {
+		   .name = DRIVER_NAME,
+		   },
+	.probe = sdhci_probe,
+	.remove = sdhci_remove,
+	.suspend = sdhci_suspend,
+	.resume = sdhci_resume,
+};
+
+/*****************************************************************************\
+ *                                                                           *
+ * Driver init/exit                                                          *
+ *                                                                           *
+\*****************************************************************************/
+
+static int __init sdhci_drv_init(void)
+{
+	printk(KERN_INFO DRIVER_NAME
+	       ": MXC Secure Digital Host Controller Interface driver\n");
+	return platform_driver_register(&sdhci_driver);
+}
+
+static void __exit sdhci_drv_exit(void)
+{
+	DBG("Exiting\n");
+
+	platform_driver_unregister(&sdhci_driver);
+}
+
+module_init(sdhci_drv_init);
+module_exit(sdhci_drv_exit);
+
+module_param(debug_quirks, uint, 0444);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC Secure Digital Host Controller Interface driver");
+MODULE_LICENSE("GPL");
+
+MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
diff --git a/drivers/mmc/host/mx_sdhci.h b/drivers/mmc/host/mx_sdhci.h
new file mode 100644
index 000000000000..a212cb2bb03a
--- /dev/null
+++ b/drivers/mmc/host/mx_sdhci.h
@@ -0,0 +1,297 @@
+/*
+ *  linux/drivers/mmc/host/mx_sdhci.h - Secure Digital Host
+ *  Controller Interface driver
+ *
+ *  Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+/*
+ * Controller registers
+ */
+
+#define SDHCI_DMA_ADDRESS	0x00
+
+#define SDHCI_BLOCK_SIZE	0x04
+#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 13) | (blksz & 0x1FFF))
+
+#define SDHCI_BLOCK_COUNT	0x04
+
+#define SDHCI_ARGUMENT		0x08
+
+#define SDHCI_TRANSFER_MODE	0x0C
+#define  SDHCI_TRNS_DMA		0x00000001
+#define  SDHCI_TRNS_BLK_CNT_EN	0x00000002
+#define  SDHCI_TRNS_ACMD12	0x00000004
+#define  SDHCI_TRNS_DDR_EN 	0x00000008
+#define  SDHCI_TRNS_READ	0x00000010
+#define  SDHCI_TRNS_MULTI	0x00000020
+#define  SDHCI_TRNS_DPSEL	0x00200000
+#define  SDHCI_TRNS_MASK	0xFFFF0000
+
+#define SDHCI_COMMAND		0x0E
+#define  SDHCI_CMD_RESP_MASK	0x03
+#define  SDHCI_CMD_CRC		0x08
+#define  SDHCI_CMD_INDEX	0x10
+#define  SDHCI_CMD_DATA		0x20
+
+#define  SDHCI_CMD_RESP_NONE	0x00
+#define  SDHCI_CMD_RESP_LONG	0x01
+#define  SDHCI_CMD_RESP_SHORT	0x02
+#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) << 16
+
+#define SDHCI_RESPONSE		0x10
+
+#define SDHCI_BUFFER		0x20
+
+#define SDHCI_PRESENT_STATE	0x24
+#define  SDHCI_CMD_INHIBIT	0x00000001
+#define  SDHCI_DATA_INHIBIT	0x00000002
+#define  SDHCI_DATA_ACTIVE 	0x00000004
+#define  SDHCI_DOING_WRITE	0x00000100
+#define  SDHCI_DOING_READ	0x00000200
+#define  SDHCI_SPACE_AVAILABLE	0x00000400
+#define  SDHCI_DATA_AVAILABLE	0x00000800
+#define  SDHCI_CARD_PRESENT	0x00010000
+#define  SDHCI_WRITE_PROTECT	0x00080000
+#define  SDHCI_DAT0_IDLE	0x01000000
+#define  SDHCI_CARD_INT_MASK	0x0E000000
+#define  SDHCI_CARD_INT_ID	0x0C000000
+
+#define SDHCI_HOST_CONTROL 	0x28
+#define  SDHCI_CTRL_LED		0x00000001
+#define  SDHCI_CTRL_4BITBUS	0x00000002
+#define  SDHCI_CTRL_8BITBUS	0x00000004
+#define  SDHCI_CTRL_HISPD	0x00000004
+#define  SDHCI_CTRL_DMA_MASK	0x18
+#define   SDHCI_CTRL_SDMA	0x00
+#define   SDHCI_CTRL_ADMA1	0x08
+#define   SDHCI_CTRL_ADMA32	0x10
+#define   SDHCI_CTRL_ADMA64	0x18
+#define  SDHCI_CTRL_D3CD 	0x00000008
+#define  SDHCI_CTRL_ADMA 	0x00000100
+/* wake up control */
+#define  SDHCI_CTRL_WECINS 	0x04000000
+
+#define SDHCI_POWER_CONTROL	0x29
+#define  SDHCI_POWER_ON		0x01
+#define  SDHCI_POWER_180	0x0A
+#define  SDHCI_POWER_300	0x0C
+#define  SDHCI_POWER_330	0x0E
+
+#define SDHCI_BLOCK_GAP_CONTROL	0x2A
+
+#define SDHCI_WAKE_UP_CONTROL	0x2B
+
+#define SDHCI_CLOCK_CONTROL	0x2C
+#define  SDHCI_DIVIDER_SHIFT	8
+#define  SDHCI_CLOCK_SD_EN	0x00000008
+#define  SDHCI_CLOCK_PER_EN	0x00000004
+#define  SDHCI_CLOCK_HLK_EN	0x00000002
+#define  SDHCI_CLOCK_IPG_EN	0x00000001
+#define  SDHCI_CLOCK_SDCLKFS1 	0x00000100
+#define  SDHCI_CLOCK_MASK 	0x0000FFFF
+
+#define SDHCI_TIMEOUT_CONTROL	0x2E
+
+#define SDHCI_SOFTWARE_RESET	0x2F
+#define  SDHCI_RESET_ALL	0x01
+#define  SDHCI_RESET_CMD	0x02
+#define  SDHCI_RESET_DATA	0x04
+
+#define SDHCI_INT_STATUS	0x30
+#define SDHCI_INT_ENABLE	0x34
+#define SDHCI_SIGNAL_ENABLE	0x38
+#define  SDHCI_INT_RESPONSE	0x00000001
+#define  SDHCI_INT_DATA_END	0x00000002
+#define  SDHCI_INT_DMA_END	0x00000008
+#define  SDHCI_INT_SPACE_AVAIL	0x00000010
+#define  SDHCI_INT_DATA_AVAIL	0x00000020
+#define  SDHCI_INT_CARD_INSERT	0x00000040
+#define  SDHCI_INT_CARD_REMOVE	0x00000080
+#define  SDHCI_INT_CARD_INT	0x00000100
+#define  SDHCI_INT_ERROR	0x00008000
+#define  SDHCI_INT_TIMEOUT	0x00010000
+#define  SDHCI_INT_CRC		0x00020000
+#define  SDHCI_INT_END_BIT	0x00040000
+#define  SDHCI_INT_INDEX	0x00080000
+#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
+#define  SDHCI_INT_DATA_CRC	0x00200000
+#define  SDHCI_INT_DATA_END_BIT	0x00400000
+#define  SDHCI_INT_BUS_POWER	0x00800000
+#define  SDHCI_INT_ACMD12ERR	0x01000000
+#define  SDHCI_INT_ADMA_ERROR	0x10000000
+
+#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
+#define  SDHCI_INT_ERROR_MASK	0xFFFF8000
+
+#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
+		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
+		SDHCI_INT_ACMD12ERR)
+#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
+#define  SDHCI_INT_DATA_RE_MASK	(SDHCI_INT_DMA_END | \
+		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)
+
+#define SDHCI_ACMD12_ERR	0x3C
+#define SDHCI_ACMD12_ERR_NE 	0x00000001
+#define SDHCI_ACMD12_ERR_TOE 	0x00000002
+#define SDHCI_ACMD12_ERR_EBE 	0x00000004
+#define SDHCI_ACMD12_ERR_CE 	0x00000008
+#define SDHCI_ACMD12_ERR_IE 	0x00000010
+#define SDHCI_ACMD12_ERR_CNIBE 	0x00000080
+
+/* 3E-3F reserved */
+
+#define SDHCI_CAPABILITIES	0x40
+#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
+#define  SDHCI_TIMEOUT_CLK_SHIFT 0
+#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
+#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define  SDHCI_CLOCK_BASE_SHIFT	8
+#define  SDHCI_MAX_BLOCK_MASK	0x00030000
+#define  SDHCI_MAX_BLOCK_SHIFT  16
+#define  SDHCI_CAN_DO_ADMA2	0x00080000
+#define  SDHCI_CAN_DO_ADMA1	0x00100000
+#define  SDHCI_CAN_DO_HISPD	0x00200000
+#define  SDHCI_CAN_DO_DMA	0x00400000
+#define  SDHCI_CAN_VDD_330	0x01000000
+#define  SDHCI_CAN_VDD_300	0x02000000
+#define  SDHCI_CAN_VDD_180	0x04000000
+#define  SDHCI_CAN_64BIT	0x10000000
+
+/* 44-47 reserved for more caps */
+#define SDHCI_WML 		0x44
+#define  SDHCI_WML_4_WORDS 	0x00040004
+#define  SDHCI_WML_16_WORDS 	0x00100010
+#define  SDHCI_WML_64_WORDS 	0x00400040
+#define  SDHCI_WML_128_WORDS 	0x00800080
+
+#define SDHCI_MAX_CURRENT	0x48
+
+/* 4C-4F reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR	0x50
+#define SDHCI_SET_INT_ERROR	0x52
+
+#define SDHCI_ADMA_ERROR	0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS	0x58
+
+/* 60-FB reserved */
+#define SDHCI_DLL_CONTROL 	0x60
+#define DLL_CTRL_ENABLE 	0x00000001
+#define DLL_CTRL_RESET 		0x00000002
+#define DLL_CTRL_SLV_FORCE_UPD 	0x00000004
+#define DLL_CTRL_SLV_OVERRIDE	0x00000200
+#define DLL_CTRL_SLV_DLY_TAR 	0x00000000
+#define DLL_CTRL_SLV_UP_INT 	0x00200000
+#define DLL_CTRL_REF_UP_INT 	0x20000000
+
+#define SDHCI_DLL_STATUS 	0x64
+#define DLL_STS_SLV_LOCK 	0x00000001
+#define DLL_STS_REF_LOCK 	0x00000002
+
+/* ADMA Addr Descriptor Attribute Filed */
+enum {
+	FSL_ADMA_DES_ATTR_VALID = 0x01,
+	FSL_ADMA_DES_ATTR_END = 0x02,
+	FSL_ADMA_DES_ATTR_INT = 0x04,
+	FSL_ADMA_DES_ATTR_SET = 0x10,
+	FSL_ADMA_DES_ATTR_TRAN = 0x20,
+	FSL_ADMA_DES_ATTR_LINK = 0x30,
+};
+
+#define SDHCI_HOST_VERSION	0xFC
+#define  SDHCI_VENDOR_VER_MASK	0xFF00
+#define  SDHCI_VENDOR_VER_SHIFT	8
+#define  SDHCI_SPEC_VER_MASK	0x00FF
+#define  SDHCI_SPEC_VER_SHIFT	0
+#define   SDHCI_SPEC_100	0
+#define   SDHCI_SPEC_200	1
+#define   ESDHC_VENDOR_V22 	0x12
+#define   ESDHC_VENDOR_V3 	0x13
+
+struct sdhci_chip;
+
+struct sdhci_host {
+	struct sdhci_chip *chip;
+	struct mmc_host *mmc;	/* MMC structure */
+
+#ifdef CONFIG_LEDS_CLASS
+	struct led_classdev led;	/* LED control */
+#endif
+
+	spinlock_t lock;	/* Mutex */
+
+	int init_flag;		/* Host has been initialized */
+	int flags;		/* Host attributes */
+#define SDHCI_USE_DMA		(1<<0)	/* Host is DMA capable */
+#define SDHCI_REQ_USE_DMA	(1<<1)	/* Use DMA for this req. */
+#define SDHCI_USE_EXTERNAL_DMA	(1<<2)	/* Use the External DMA */
+#define SDHCI_CD_PRESENT 	(1<<8)	/* CD present */
+#define SDHCI_WP_ENABLED	(1<<9)	/* Write protect */
+#define SDHCI_CD_TIMEOUT 	(1<<10)	/* cd timer is expired */
+
+	unsigned int max_clk;	/* Max possible freq (MHz) */
+	unsigned int min_clk;	/* Min possible freq (MHz) */
+	unsigned int timeout_clk;	/* Timeout freq (KHz) */
+
+	unsigned int clock;	/* Current clock (MHz) */
+	unsigned short power;	/* Current voltage */
+	struct regulator *regulator_mmc;	/*! Regulator */
+
+	struct mmc_request *mrq;	/* Current request */
+	struct mmc_command *cmd;	/* Current command */
+	struct mmc_data *data;	/* Current data request */
+	unsigned int data_early:1;	/* Data finished before cmd */
+
+	unsigned int id;	/* Id for SD/MMC block */
+	int mode;		/* SD/MMC mode */
+	int dma;		/* DMA channel number. */
+	unsigned int dma_size;	/* Number of Bytes in DMA */
+	unsigned int dma_len;	/* Length of the s-g list */
+	unsigned int dma_dir;	/* DMA transfer direction */
+
+	struct scatterlist *cur_sg;	/* We're working on this */
+	int num_sg;		/* Entries left */
+	int offset;		/* Offset into current sg */
+	int remain;		/* Bytes left in current */
+
+	struct resource *res;	/* IO map memory */
+	int irq;		/* Device IRQ */
+	int detect_irq;		/* Card Detect IRQ number. */
+	int sdio_enable;	/* sdio interrupt enable number. */
+	struct clk *clk;	/* Clock id */
+	int bar;		/* PCI BAR index */
+	unsigned long addr;	/* Bus address */
+	void __iomem *ioaddr;	/* Mapped address */
+
+	struct tasklet_struct card_tasklet;	/* Tasklet structures */
+	struct tasklet_struct finish_tasklet;
+	struct work_struct cd_wq;	/* card detection work queue */
+	/* Platform specific data */
+	struct mxc_mmc_platform_data *plat_data;
+
+	struct timer_list timer;	/* Timer for timeouts */
+	struct timer_list cd_timer;	/* Timer for cd */
+};
+
+struct sdhci_chip {
+	struct platform_device *pdev;
+
+	unsigned long quirks;
+
+	int num_slots;		/* Slots on controller */
+	struct sdhci_host *hosts[0];	/* Pointers to hosts */
+};
diff --git a/drivers/mmc/host/mxc_mmc.c b/drivers/mmc/host/mxc_mmc.c
new file mode 100644
index 000000000000..9cb492f40145
--- /dev/null
+++ b/drivers/mmc/host/mxc_mmc.c
@@ -0,0 +1,1530 @@
+/*
+ *  linux/drivers/mmc/host/mxc_mmc.c - Freescale MXC/i.MX MMC driver
+ *
+ *  based on imxmmc.c
+ *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
+ *
+ *  derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_mmc.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC SDHC modules.
+ *
+ * This driver code is based on imxmmc.c, by Sascha Hauer,
+ * Pengutronix <sascha@saschahauer.de>. This driver supports both Secure Digital
+ * Host Controller modules (SDHC1 and SDHC2) of MXC. SDHC is also referred as
+ * MMC/SD controller. This code is not tested for SD cards.
+ *
+ * @ingroup MMC_SD
+ */
+
+/*
+ * Include Files
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sd.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+#include <asm/mach-types.h>
+#include <asm/mach/irq.h>
+#include <mach/mmc.h>
+
+#include "mxc_mmc.h"
+
+#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
+
+/*
+ * This define is used to test the driver without using DMA
+ */
+#define MXC_MMC_DMA_ENABLE
+
+/*!
+ * Maxumum length of s/g list, only length of 1 is currently supported
+ */
+#define NR_SG   1
+
+#ifdef CONFIG_MMC_DEBUG
+static void dump_cmd(struct mmc_command *cmd)
+{
+	printk(KERN_INFO "%s: CMD: opcode: %d ", DRIVER_NAME, cmd->opcode);
+	printk(KERN_INFO "arg: 0x%08x ", cmd->arg);
+	printk(KERN_INFO "flags: 0x%08x\n", cmd->flags);
+}
+
+static void dump_status(const char *func, int sts)
+{
+	unsigned int bitset;
+	printk(KERN_INFO "%s:status: ", func);
+	while (sts) {
+		/* Find the next bit set */
+		bitset = sts & ~(sts - 1);
+		switch (bitset) {
+		case STATUS_CARD_INSERTION:
+			printk(KERN_INFO "CARD_INSERTION|");
+			break;
+		case STATUS_CARD_REMOVAL:
+			printk(KERN_INFO "CARD_REMOVAL |");
+			break;
+		case STATUS_YBUF_EMPTY:
+			printk(KERN_INFO "YBUF_EMPTY |");
+			break;
+		case STATUS_XBUF_EMPTY:
+			printk(KERN_INFO "XBUF_EMPTY |");
+			break;
+		case STATUS_YBUF_FULL:
+			printk(KERN_INFO "YBUF_FULL |");
+			break;
+		case STATUS_XBUF_FULL:
+			printk(KERN_INFO "XBUF_FULL |");
+			break;
+		case STATUS_BUF_UND_RUN:
+			printk(KERN_INFO "BUF_UND_RUN |");
+			break;
+		case STATUS_BUF_OVFL:
+			printk(KERN_INFO "BUF_OVFL |");
+			break;
+		case STATUS_READ_OP_DONE:
+			printk(KERN_INFO "READ_OP_DONE |");
+			break;
+		case STATUS_WR_CRC_ERROR_CODE_MASK:
+			printk(KERN_INFO "WR_CRC_ERROR_CODE |");
+			break;
+		case STATUS_READ_CRC_ERR:
+			printk(KERN_INFO "READ_CRC_ERR |");
+			break;
+		case STATUS_WRITE_CRC_ERR:
+			printk(KERN_INFO "WRITE_CRC_ERR |");
+			break;
+		case STATUS_SDIO_INT_ACTIVE:
+			printk(KERN_INFO "SDIO_INT_ACTIVE |");
+			break;
+		case STATUS_END_CMD_RESP:
+			printk(KERN_INFO "END_CMD_RESP |");
+			break;
+		case STATUS_WRITE_OP_DONE:
+			printk(KERN_INFO "WRITE_OP_DONE |");
+			break;
+		case STATUS_CARD_BUS_CLK_RUN:
+			printk(KERN_INFO "CARD_BUS_CLK_RUN |");
+			break;
+		case STATUS_BUF_READ_RDY:
+			printk(KERN_INFO "BUF_READ_RDY |");
+			break;
+		case STATUS_BUF_WRITE_RDY:
+			printk(KERN_INFO "BUF_WRITE_RDY |");
+			break;
+		case STATUS_RESP_CRC_ERR:
+			printk(KERN_INFO "RESP_CRC_ERR |");
+			break;
+		case STATUS_TIME_OUT_RESP:
+			printk(KERN_INFO "TIME_OUT_RESP |");
+			break;
+		case STATUS_TIME_OUT_READ:
+			printk(KERN_INFO "TIME_OUT_READ |");
+			break;
+		default:
+			printk(KERN_INFO "Invalid Status Register value0x%x\n",
+			       bitset);
+			break;
+		}
+		sts &= ~bitset;
+	}
+	printk(KERN_INFO "\n");
+}
+#endif
+
+/*!
+ * This structure is a way for the low level driver to define their own
+ * \b mmc_host structure. This structure includes the core \b mmc_host
+ * structure that is provided by Linux MMC/SD Bus protocol driver as an
+ * element and has other elements that are specifically required by this
+ * low-level driver.
+ */
+struct mxcmci_host {
+	/*!
+	 * The mmc structure holds all the information about the device
+	 * structure, current SDHC io bus settings, the current OCR setting,
+	 * devices attached to this host, and so on.
+	 */
+	struct mmc_host *mmc;
+
+	/*!
+	 * This variable is used for locking the host data structure from
+	 * multiple access.
+	 */
+	spinlock_t lock;
+
+	/*!
+	 * Resource structure, which will maintain base addresses and IRQs.
+	 */
+	struct resource *res;
+
+	/*!
+	 * Base address of SDHC, used in readl and writel.
+	 */
+	void *base;
+
+	/*!
+	 * SDHC IRQ number.
+	 */
+	int irq;
+
+	/*!
+	 * Card Detect IRQ number.
+	 */
+	int detect_irq;
+
+	/*!
+	 * Clock id to hold ipg_perclk.
+	 */
+	struct clk *clk;
+	/*!
+	 * MMC mode.
+	 */
+	int mode;
+
+	/*!
+	 * DMA channel number.
+	 */
+	int dma;
+
+	/*!
+	 * Pointer to hold MMC/SD request.
+	 */
+	struct mmc_request *req;
+
+	/*!
+	 * Pointer to hold MMC/SD command.
+	 */
+	struct mmc_command *cmd;
+
+	/*!
+	 * Pointer to hold MMC/SD data.
+	 */
+	struct mmc_data *data;
+
+	/*!
+	 * Holds the number of bytes to transfer using DMA.
+	 */
+	unsigned int dma_size;
+
+	/*!
+	 * Value to store in Command and Data Control Register
+	 * - currently unused
+	 */
+	unsigned int cmdat;
+
+	/*!
+	 * Regulator
+	 */
+	struct regulator *regulator_mmc;
+
+	/*!
+	 * Current vdd settting
+	 */
+	int current_vdd;
+
+	/*!
+	 * Power mode - currently unused
+	 */
+	unsigned int power_mode;
+
+	/*!
+	 * DMA address for scatter-gather transfers
+	 */
+	dma_addr_t sg_dma;
+
+	/*!
+	 * Length of the scatter-gather list
+	 */
+	unsigned int dma_len;
+
+	/*!
+	 * Holds the direction of data transfer.
+	 */
+	unsigned int dma_dir;
+
+	/*!
+	 * Id for MMC block.
+	 */
+	unsigned int id;
+
+	/*!
+	 * Note whether this driver has been suspended.
+	 */
+	unsigned int mxc_mmc_suspend_flag;
+
+	/*!
+	 * sdio_irq enable/disable ref count
+	 */
+	int sdio_irq_cnt;
+
+	/*!
+	 * Platform specific data
+	 */
+	struct mxc_mmc_platform_data *plat_data;
+};
+
+extern void gpio_sdhc_active(int module);
+extern void gpio_sdhc_inactive(int module);
+
+#ifdef MXC_MMC_DMA_ENABLE
+static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt);
+#endif
+static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
+
+/* Wait count to start the clock */
+#define CMD_WAIT_CNT 100
+
+#define MAX_HOST 10
+static struct mmc_host *hosts[MAX_HOST];
+
+void mxc_mmc_force_detect(int id)
+{
+	if (id < MAX_HOST)
+		mmc_detect_change(hosts[id], msecs_to_jiffies(100));
+}
+
+EXPORT_SYMBOL(mxc_mmc_force_detect);
+
+/*!
+  This function sets the SDHC register to stop the clock and waits for the
+ * clock stop indication.
+ */
+static void mxcmci_stop_clock(struct mxcmci_host *host, bool wait)
+{
+	int wait_cnt = 0;
+	while (1) {
+		__raw_writel(STR_STP_CLK_STOP_CLK,
+			     host->base + MMC_STR_STP_CLK);
+
+		if (!wait)
+			break;
+
+		wait_cnt = CMD_WAIT_CNT;
+		while (wait_cnt--) {
+			if (!(__raw_readl(host->base + MMC_STATUS) &
+			      STATUS_CARD_BUS_CLK_RUN))
+				break;
+		}
+
+		if (!(__raw_readl(host->base + MMC_STATUS) &
+		      STATUS_CARD_BUS_CLK_RUN))
+			break;
+	}
+}
+
+/*!
+ * This function sets the SDHC register to start the clock and waits for the
+ * clock start indication. When the clock starts SDHC module starts processing
+ * the command in CMD Register with arguments in ARG Register.
+ *
+ * @param host Pointer to MMC/SD host structure
+ * @param wait Boolean value to indicate whether to wait for the clock to start or come out instantly
+ */
+static void mxcmci_start_clock(struct mxcmci_host *host, bool wait)
+{
+	int wait_cnt;
+
+#ifdef CONFIG_MMC_DEBUG
+	dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS));
+#endif
+
+	while (1) {
+		__raw_writel(STR_STP_CLK_START_CLK,
+			     host->base + MMC_STR_STP_CLK);
+		if (!wait)
+			break;
+
+		wait_cnt = CMD_WAIT_CNT;
+		while (wait_cnt--) {
+			if (__raw_readl(host->base + MMC_STATUS) &
+			    STATUS_CARD_BUS_CLK_RUN) {
+				break;
+			}
+		}
+
+		if (__raw_readl(host->base + MMC_STATUS) &
+		    STATUS_CARD_BUS_CLK_RUN) {
+			break;
+		}
+	}
+#ifdef CONFIG_MMC_DEBUG
+	dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS));
+#endif
+	pr_debug("%s:CLK_RATE: 0x%08x\n", DRIVER_NAME,
+		 __raw_readl(host->base + MMC_CLK_RATE));
+}
+
+/*!
+ * This function resets the SDHC host.
+ *
+ * @param host  Pointer to MMC/SD  host structure
+ */
+static void mxcmci_softreset(struct mxcmci_host *host)
+{
+	/* reset sequence */
+	__raw_writel(0x8, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x9, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x1, host->base + MMC_STR_STP_CLK);
+	__raw_writel(0x3f, host->base + MMC_CLK_RATE);
+
+	__raw_writel(0xff, host->base + MMC_RES_TO);
+	__raw_writel(512, host->base + MMC_BLK_LEN);
+	__raw_writel(1, host->base + MMC_NOB);
+}
+
+/*!
+ * This function is called to setup SDHC register for data transfer.
+ * The function allocates DMA buffers, configures the DMA channel.
+ * Start the DMA channel to transfer data. When DMA is not enabled this
+ * function set ups only Number of Block and Block Length registers.
+ *
+ * @param host  Pointer to MMC/SD host structure
+ * @param data  Pointer to MMC/SD data structure
+ */
+static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
+{
+	unsigned int nob = data->blocks;
+
+	if (data->flags & MMC_DATA_STREAM) {
+		nob = 0xffff;
+	}
+
+	host->data = data;
+
+	__raw_writel(nob, host->base + MMC_NOB);
+	__raw_writel(data->blksz, host->base + MMC_BLK_LEN);
+
+	host->dma_size = data->blocks * data->blksz;
+	pr_debug("%s:Request bytes to transfer:%d\n", DRIVER_NAME,
+		 host->dma_size);
+
+#ifdef MXC_MMC_DMA_ENABLE
+	if (host->dma_size <= (16 << host->mmc->ios.bus_width)) {
+		return;
+	}
+
+	if (data->blksz & 0x3) {
+		printk(KERN_ERR
+		       "mxc_mci: block size not multiple of 4 bytes\n");
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		host->dma_dir = DMA_FROM_DEVICE;
+	} else {
+		host->dma_dir = DMA_TO_DEVICE;
+	}
+	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+				   host->dma_dir);
+
+	if (data->flags & MMC_DATA_READ) {
+		mxc_dma_sg_config(host->dma, data->sg, data->sg_len,
+				  host->dma_size, MXC_DMA_MODE_READ);
+	} else {
+		mxc_dma_sg_config(host->dma, data->sg, data->sg_len,
+				  host->dma_size, MXC_DMA_MODE_WRITE);
+	}
+#endif
+}
+
+/*!
+ * This function is called by \b mxcmci_request() function to setup the SDHC
+ * register to issue command. This function disables the card insertion and
+ * removal detection interrupt.
+ *
+ * @param host  Pointer to MMC/SD host structure
+ * @param cmd   Pointer to MMC/SD command structure
+ * @param cmdat Value to store in Command and Data Control Register
+ */
+static void mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
+			     unsigned int cmdat)
+{
+	WARN_ON(host->cmd != NULL);
+	host->cmd = cmd;
+
+	switch (RSP_TYPE(mmc_resp_type(cmd))) {
+	case RSP_TYPE(MMC_RSP_R1):	/* r1, r1b, r6 */
+		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
+		break;
+	case RSP_TYPE(MMC_RSP_R3):
+		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
+		break;
+	case RSP_TYPE(MMC_RSP_R2):
+		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
+		break;
+	default:
+		/* No Response required */
+		break;
+	}
+
+	if (cmd->opcode == MMC_GO_IDLE_STATE) {
+		cmdat |= CMD_DAT_CONT_INIT;	/* This command needs init */
+	}
+
+	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
+		cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
+	}
+
+	__raw_writel(cmd->opcode, host->base + MMC_CMD);
+	__raw_writel(cmd->arg, host->base + MMC_ARG);
+
+	__raw_writel(cmdat, host->base + MMC_CMD_DAT_CONT);
+
+	if (!(__raw_readl(host->base + MMC_STATUS) & STATUS_CARD_BUS_CLK_RUN))
+		mxcmci_start_clock(host, true);
+}
+
+/*!
+ * This function is called to complete the command request.
+ * This function enables insertion or removal interrupt.
+ *
+ * @param host Pointer to MMC/SD host structure
+ * @param req  Pointer to MMC/SD command request structure
+ */
+static void mxcmci_finish_request(struct mxcmci_host *host,
+				  struct mmc_request *req)
+{
+
+	host->req = NULL;
+	host->cmd = NULL;
+	host->data = NULL;
+
+	mmc_request_done(host->mmc, req);
+}
+
+/*!
+ * This function is called when the requested command is completed.
+ * This function reads the response from the card and data if the command is for
+ * data transfer. This function checks for CRC error in response FIFO or
+ * data FIFO.
+ *
+ * @param host  Pointer to MMC/SD host structure
+ * @param stat  Content of SDHC Status Register
+ *
+ * @return This function returns 0 if there is no pending command, otherwise 1
+ * always.
+ */
+static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct mmc_data *data = host->data;
+	int i;
+	u32 a, b, c;
+	u32 temp_data;
+	unsigned int status;
+	unsigned long *buf;
+	u8 *buf8;
+	int no_of_bytes;
+	int no_of_words;
+
+	if (!cmd) {
+		/* There is no command for completion */
+		return 0;
+	}
+
+	/* As this function finishes the command, initialize cmd to NULL */
+	host->cmd = NULL;
+
+	/* check for Time out errors */
+	if (stat & STATUS_TIME_OUT_RESP) {
+		__raw_writel(STATUS_TIME_OUT_RESP, host->base + MMC_STATUS);
+		pr_debug("%s: CMD %d TIMEOUT\n", DRIVER_NAME, cmd->opcode);
+		cmd->error = -ETIMEDOUT;
+		/*
+		 * Reinitialized the controller to clear the unknown
+		 * error state.
+		 */
+		mxcmci_softreset(host);
+		__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+		__raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR);
+	} else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
+		__raw_writel(STATUS_RESP_CRC_ERR, host->base + MMC_STATUS);
+		printk(KERN_ERR "%s: cmd %d CRC error\n", DRIVER_NAME,
+		       cmd->opcode);
+		cmd->error = -EILSEQ;
+		/*
+		 * Reinitialized the controller to clear the unknown
+		 * error state.
+		 */
+		mxcmci_softreset(host);
+		__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+		__raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR);
+	}
+
+	/* Read response from the card */
+	switch (RSP_TYPE(mmc_resp_type(cmd))) {
+	case RSP_TYPE(MMC_RSP_R1):	/* r1, r1b, r6 */
+		a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		cmd->resp[0] = a << 24 | b << 8 | c >> 8;
+		break;
+	case RSP_TYPE(MMC_RSP_R3):	/* r3, r4 */
+		a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+		cmd->resp[0] = a << 24 | b << 8 | c >> 8;
+		break;
+	case RSP_TYPE(MMC_RSP_R2):
+		for (i = 0; i < 4; i++) {
+			a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+			b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff;
+			cmd->resp[i] = a << 16 | b;
+		}
+		break;
+	default:
+		break;
+	}
+
+	pr_debug("%s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", DRIVER_NAME,
+		 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+	if (!host->data || cmd->error) {
+		/* complete the command */
+		mxcmci_finish_request(host, host->req);
+		return 1;
+	}
+
+	/* The command has a data transfer */
+#ifdef MXC_MMC_DMA_ENABLE
+	/* Use DMA if transfer size is greater than fifo size */
+	if (host->dma_size > (16 << host->mmc->ios.bus_width)) {
+		mxc_dma_enable(host->dma);
+		return 1;
+	}
+#endif
+	/* Use PIO tranfer of data */
+	buf = (unsigned long *)sg_virt(data->sg);
+	buf8 = (u8 *) buf;
+
+	/* calculate the number of bytes requested for transfer */
+	no_of_bytes = data->blocks * data->blksz;
+	no_of_words = (no_of_bytes + 3) / 4;
+	pr_debug("no_of_words=%d\n", no_of_words);
+
+	if (data->flags & MMC_DATA_READ) {
+		for (i = 0; i < no_of_words; i++) {
+			/* wait for buffers to be ready for read */
+			while (!(__raw_readl(host->base + MMC_STATUS) &
+				 (STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE))) ;
+
+			pr_debug("status is 0x%x\n",
+				 __raw_readl(host->base + MMC_STATUS));
+			/* read 32 bit data */
+			temp_data = __raw_readl(host->base + MMC_BUFFER_ACCESS);
+			if (SD_APP_SEND_SCR == cmd->opcode) {
+				pr_debug("CMD51 read out 0x%x\n", temp_data);
+				if (temp_data == 0xFFFFFFFF)
+					temp_data = 0;
+			}
+			if (no_of_bytes >= 4) {
+				*buf++ = temp_data;
+				no_of_bytes -= 4;
+			} else {
+				do {
+					*buf8++ = temp_data;
+					temp_data = temp_data >> 8;
+				} while (--no_of_bytes);
+			}
+		}
+
+		/* wait for read operation completion bit */
+		while (!(__raw_readl(host->base + MMC_STATUS) &
+			 STATUS_READ_OP_DONE)) ;
+
+		/* check for time out and CRC errors */
+		status = __raw_readl(host->base + MMC_STATUS);
+		if (status & STATUS_TIME_OUT_READ) {
+			printk(KERN_ERR "%s: Read time out occurred\n",
+			       DRIVER_NAME);
+			data->error = -ETIMEDOUT;
+			__raw_writel(STATUS_TIME_OUT_READ,
+				     host->base + MMC_STATUS);
+			/*
+			 * Reinitialized the controller to clear the unknown
+			 * error state.
+			 */
+			mxcmci_softreset(host);
+			__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+			__raw_writel(INT_CNTR_END_CMD_RES,
+				     host->base + MMC_INT_CNTR);
+		} else if (status & STATUS_READ_CRC_ERR) {
+			printk(KERN_ERR "%s: Read CRC error occurred\n",
+			       DRIVER_NAME);
+			if (SD_APP_SEND_SCR != cmd->opcode)
+				data->error = -EILSEQ;
+			__raw_writel(STATUS_READ_CRC_ERR,
+				     host->base + MMC_STATUS);
+			/*
+			 * Reinitialized the controller to clear the unknown
+			 * error state.
+			 */
+			mxcmci_softreset(host);
+			__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+			__raw_writel(INT_CNTR_END_CMD_RES,
+				     host->base + MMC_INT_CNTR);
+		}
+		__raw_writel(STATUS_READ_OP_DONE, host->base + MMC_STATUS);
+
+		pr_debug("%s: Read %u words\n", DRIVER_NAME, i);
+	} else {
+		for (i = 0; i < no_of_words; i++) {
+
+			/* wait for buffers to be ready for write */
+			while (!(__raw_readl(host->base + MMC_STATUS) &
+				 STATUS_BUF_WRITE_RDY)) ;
+
+			/* write 32 bit data */
+			__raw_writel(*buf++, host->base + MMC_BUFFER_ACCESS);
+			if (__raw_readl(host->base + MMC_STATUS) &
+			    STATUS_WRITE_OP_DONE) {
+				break;
+			}
+		}
+
+		/* wait for write operation completion bit */
+		while (!(__raw_readl(host->base + MMC_STATUS) &
+			 STATUS_WRITE_OP_DONE)) ;
+
+		/* check for CRC errors */
+		status = __raw_readl(host->base + MMC_STATUS);
+		if (status & STATUS_WRITE_CRC_ERR) {
+			printk(KERN_ERR "%s: Write CRC error occurred\n",
+			       DRIVER_NAME);
+			data->error = -EILSEQ;
+			__raw_writel(STATUS_WRITE_CRC_ERR,
+				     host->base + MMC_STATUS);
+		}
+		__raw_writel(STATUS_WRITE_OP_DONE, host->base + MMC_STATUS);
+		pr_debug("%s: Written %u words\n", DRIVER_NAME, i);
+	}
+
+	/* complete the data transfer request */
+	mxcmci_data_done(host, status);
+
+	return 1;
+}
+
+/*!
+ * This function is called when the data transfer is completed either by DMA
+ * or by core. This function is called to clean up the DMA buffer and to send
+ * STOP transmission command for commands to transfer data. This function
+ * completes request issued by the MMC/SD core driver.
+ *
+ * @param host   pointer to MMC/SD host structure.
+ * @param stat   content of SDHC Status Register
+ *
+ * @return This function returns 0 if no data transfer otherwise return 1
+ * always.
+ */
+static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
+{
+	struct mmc_data *data = host->data;
+
+	if (!data) {
+		return 0;
+	}
+#ifdef MXC_MMC_DMA_ENABLE
+	if (host->dma_size > (16 << host->mmc->ios.bus_width)) {
+		dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
+			     host->dma_dir);
+	}
+#endif
+	if (__raw_readl(host->base + MMC_STATUS) & STATUS_ERR_MASK) {
+		printk(KERN_ERR "%s: request failed. status: 0x%08x\n",
+		       DRIVER_NAME, __raw_readl(host->base + MMC_STATUS));
+	}
+
+	host->data = NULL;
+	data->bytes_xfered = host->dma_size;
+
+	if (host->req->stop && !(data->error)) {
+		mxcmci_stop_clock(host, true);
+		mxcmci_start_cmd(host, host->req->stop, 0);
+	} else {
+		mxcmci_finish_request(host, host->req);
+	}
+
+	return 1;
+}
+
+/*!
+ * GPIO interrupt service routine registered to handle the SDHC interrupts.
+ * This interrupt routine handles card insertion and card removal interrupts.
+ *
+ * @param   irq    the interrupt number
+ * @param   devid  driver private data
+ * @param   regs   holds a snapshot of the processor's context before the
+ *                 processor entered the interrupt code
+ *
+ * @return  The function returns \b IRQ_RETVAL(1)
+ */
+static irqreturn_t mxcmci_gpio_irq(int irq, void *devid)
+{
+	struct mxcmci_host *host = devid;
+	int card_gpio_status = host->plat_data->status(host->mmc->parent);
+
+	pr_debug("%s: MMC%d status=%d %s\n", DRIVER_NAME, host->id,
+		 card_gpio_status, card_gpio_status ? "removed" : "inserted");
+
+	if (card_gpio_status == host->plat_data->card_inserted_state) {
+		/*
+		 * Reinitialized the controller to clear the unknown
+		 * error state when a card is inserted.
+		 */
+		mxcmci_softreset(host);
+		__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+		__raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR);
+
+		mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+	} else {
+		mxcmci_cmd_done(host, STATUS_TIME_OUT_RESP);
+		mmc_detect_change(host->mmc, msecs_to_jiffies(50));
+	}
+
+	do {
+		card_gpio_status = host->plat_data->status(host->mmc->parent);
+		if (card_gpio_status) {
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING);
+		} else {
+			set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING);
+		}
+	} while (card_gpio_status !=
+		 host->plat_data->status(host->mmc->parent));
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * Interrupt service routine registered to handle the SDHC interrupts.
+ * This interrupt routine handles end of command, card insertion and
+ * card removal interrupts. If the interrupt is card insertion or removal then
+ * inform the MMC/SD core driver to detect the change in physical connections.
+ * If the command is END_CMD_RESP read the Response FIFO. If DMA is not enabled
+ * and data transfer is associated with the command then read or write the data
+ * from or to the BUFFER_ACCESS FIFO.
+ *
+ * @param   irq    the interrupt number
+ * @param   devid  driver private data
+ * @param   regs   holds a snapshot of the processor's context before the
+ *                 processor entered the interrupt code
+ *
+ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ */
+static irqreturn_t mxcmci_irq(int irq, void *devid)
+{
+	struct mxcmci_host *host = devid;
+	struct mmc_data *data = host->data;
+	unsigned int status = 0;
+	u32 intctrl;
+
+	if (host->mxc_mmc_suspend_flag == 1) {
+		clk_enable(host->clk);
+	}
+
+	status = __raw_readl(host->base + MMC_STATUS);
+	pr_debug("MXC MMC IRQ status is 0x%x.\n", status);
+#ifdef CONFIG_MMC_DEBUG
+	dump_status(__FUNCTION__, status);
+#endif
+	if (status & STATUS_END_CMD_RESP) {
+		__raw_writel(STATUS_END_CMD_RESP, host->base + MMC_STATUS);
+		mxcmci_cmd_done(host, status);
+	}
+#ifdef MXC_MMC_DMA_ENABLE
+	/*
+	 * If read length < fifo length, STATUS_END_CMD_RESP and
+	 * STATUS_READ_OP_DONE may come together. In this case, it's using PIO
+	 * mode, we ignore STATUS_READ_OP_DONE.
+	 */
+	if ((status & (STATUS_WRITE_OP_DONE | STATUS_READ_OP_DONE)) &&
+	    !(status & STATUS_END_CMD_RESP)) {
+		pr_debug(KERN_INFO "MXC MMC IO OP DONE INT.\n");
+		intctrl = __raw_readl(host->base + MMC_INT_CNTR);
+		__raw_writel((~(INT_CNTR_WRITE_OP_DONE | INT_CNTR_READ_OP_DONE)
+			      & intctrl), host->base + MMC_INT_CNTR);
+
+		pr_debug("%s:READ/WRITE OPERATION DONE\n", DRIVER_NAME);
+		/* check for time out and CRC errors */
+		status = __raw_readl(host->base + MMC_STATUS);
+		if (status & STATUS_READ_OP_DONE) {
+			if (status & STATUS_TIME_OUT_READ) {
+				pr_debug("%s: Read time out occurred\n",
+					 DRIVER_NAME);
+				data->error = -ETIMEDOUT;
+				__raw_writel(STATUS_TIME_OUT_READ,
+					     host->base + MMC_STATUS);
+			} else if (status & STATUS_READ_CRC_ERR) {
+				pr_debug("%s: Read CRC error occurred\n",
+					 DRIVER_NAME);
+				data->error = -EILSEQ;
+				__raw_writel(STATUS_READ_CRC_ERR,
+					     host->base + MMC_STATUS);
+			}
+			__raw_writel(STATUS_READ_OP_DONE,
+				     host->base + MMC_STATUS);
+		}
+
+		/* check for CRC errors */
+		if (status & STATUS_WRITE_OP_DONE) {
+			if (status & STATUS_WRITE_CRC_ERR) {
+				printk(KERN_ERR
+				       "%s: Write CRC error occurred\n",
+				       DRIVER_NAME);
+				data->error = -EILSEQ;
+				__raw_writel(STATUS_WRITE_CRC_ERR,
+					     host->base + MMC_STATUS);
+			}
+			__raw_writel(STATUS_WRITE_OP_DONE,
+				     host->base + MMC_STATUS);
+		}
+
+		mxcmci_data_done(host, status);
+	}
+#endif
+	status = __raw_readl(host->base + MMC_STATUS);
+	intctrl = __raw_readl(host->base + MMC_INT_CNTR);
+	if ((status & STATUS_SDIO_INT_ACTIVE)
+	    && (intctrl & INT_CNTR_SDIO_IRQ_EN)) {
+		__raw_writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_STATUS);
+
+		/*Here we do not handle the sdio interrupt to client driver
+		   if the host is in suspend state */
+		if (host->mxc_mmc_suspend_flag == 0) {
+			mmc_signal_sdio_irq(host->mmc);
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is called by MMC/SD Bus Protocol driver to issue a MMC
+ * and SD commands to the SDHC.
+ *
+ * @param  mmc  Pointer to MMC/SD host structure
+ * @param  req  Pointer to MMC/SD command request structure
+ */
+static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+	struct mxcmci_host *host = mmc_priv(mmc);
+	/* Holds the value of Command and Data Control Register */
+	unsigned long cmdat;
+
+	WARN_ON(host->req != NULL);
+
+	host->req = req;
+#ifdef CONFIG_MMC_DEBUG
+	dump_cmd(req->cmd);
+	dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS));
+#endif
+
+	cmdat = 0;
+	if (req->data) {
+		mxcmci_setup_data(host, req->data);
+
+		cmdat |= CMD_DAT_CONT_DATA_ENABLE;
+
+		if (req->data->flags & MMC_DATA_WRITE) {
+			cmdat |= CMD_DAT_CONT_WRITE;
+		}
+		if (req->data->flags & MMC_DATA_STREAM) {
+			printk(KERN_ERR
+			       "MXC MMC does not support stream mode\n");
+		}
+	}
+	mxcmci_start_cmd(host, req->cmd, cmdat);
+}
+
+/*!
+ * This function is called by MMC/SD Bus Protocol driver to change the clock
+ * speed of MMC or SD card
+ *
+ * @param mmc Pointer to MMC/SD host structure
+ * @param ios Pointer to MMC/SD I/O type structure
+ */
+static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct mxcmci_host *host = mmc_priv(mmc);
+	/*This variable holds the value of clock prescaler */
+	int prescaler;
+	int clk_rate = clk_get_rate(host->clk);
+	int voltage = 0;
+#ifdef MXC_MMC_DMA_ENABLE
+	mxc_dma_device_t dev_id = 0;
+#endif
+
+	pr_debug("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME,
+		 ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd);
+
+	host->dma_dir = DMA_NONE;
+
+#ifdef MXC_MMC_DMA_ENABLE
+	if (mmc->ios.bus_width != host->mode) {
+		mxc_dma_free(host->dma);
+		if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
+			if (host->id == 0) {
+				dev_id = MXC_DMA_MMC1_WIDTH_4;
+			} else {
+				dev_id = MXC_DMA_MMC2_WIDTH_4;
+			}
+		} else {
+			if (host->id == 0) {
+				dev_id = MXC_DMA_MMC1_WIDTH_1;
+			} else {
+				dev_id = MXC_DMA_MMC2_WIDTH_1;
+			}
+		}
+		host->dma = mxc_dma_request(dev_id, "MXC MMC");
+		if (host->dma < 0) {
+			printk(KERN_ERR "Cannot allocate MMC DMA channel\n");
+		}
+		host->mode = mmc->ios.bus_width;
+		mxc_dma_callback_set(host->dma, mxcmci_dma_irq, (void *)host);
+	}
+#endif
+
+	if ((ios->vdd != host->current_vdd) && host->regulator_mmc) {
+		if (ios->vdd == 7)
+			voltage = 1800000;
+		else if (ios->vdd >= 8)
+			voltage = 2000000 + (ios->vdd - 8) * 100000;
+		regulator_set_voltage(host->regulator_mmc, voltage, voltage);
+	}
+	host->current_vdd = ios->vdd;
+
+	if (ios->power_mode != host->power_mode && host->regulator_mmc) {
+		if (ios->power_mode == MMC_POWER_UP) {
+			if (regulator_enable(host->regulator_mmc) == 0) {
+				pr_debug("mmc power on\n");
+				msleep(1);
+			}
+		} else if (ios->power_mode == MMC_POWER_OFF) {
+			regulator_disable(host->regulator_mmc);
+			pr_debug("mmc power off\n");
+		}
+	}
+	host->power_mode = ios->power_mode;
+
+	/*
+	 *  Vary divider first, then prescaler.
+	 **/
+	if (ios->clock) {
+		unsigned int clk_dev = 0;
+
+		/*
+		 * when prescaler = 16, CLK_20M = CLK_DIV / 2
+		 */
+		if (ios->clock == mmc->f_min)
+			prescaler = 16;
+		else
+			prescaler = 0;
+
+		/* clk_dev =1, CLK_DIV = ipg_perclk/2 */
+		while (prescaler <= 0x800) {
+			for (clk_dev = 1; clk_dev <= 0xF; clk_dev++) {
+				int x;
+				if (prescaler != 0) {
+					x = (clk_rate / (clk_dev + 1)) /
+					    (prescaler * 2);
+				} else {
+					x = clk_rate / (clk_dev + 1);
+				}
+
+				pr_debug("x=%d, clock=%d %d\n", x, ios->clock,
+					 clk_dev);
+				if (x <= ios->clock) {
+					break;
+				}
+			}
+			if (clk_dev < 0x10) {
+				break;
+			}
+			if (prescaler == 0)
+				prescaler = 1;
+			else
+				prescaler <<= 1;
+		}
+
+		pr_debug("prescaler = 0x%x, divider = 0x%x\n", prescaler,
+			 clk_dev);
+		mxcmci_stop_clock(host, true);
+		__raw_writel((prescaler << 4) | clk_dev,
+			     host->base + MMC_CLK_RATE);
+		mxcmci_start_clock(host, false);
+	} else {
+		mxcmci_stop_clock(host, true);
+	}
+}
+
+static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct mxcmci_host *host = mmc_priv(mmc);
+	u32 intctrl;
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (enable)
+		host->sdio_irq_cnt++;
+	else
+		host->sdio_irq_cnt--;
+
+	if (host->sdio_irq_cnt == 1 || host->sdio_irq_cnt == 0) {
+		intctrl = __raw_readl(host->base + MMC_INT_CNTR);
+		intctrl &= ~INT_CNTR_SDIO_IRQ_EN;
+		if (host->sdio_irq_cnt)
+			intctrl |= INT_CNTR_SDIO_IRQ_EN;
+		__raw_writel(intctrl, host->base + MMC_INT_CNTR);
+	}
+
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static int mxcmci_get_ro(struct mmc_host *mmc)
+{
+	struct mxcmci_host *host = mmc_priv(mmc);
+
+	if (host->plat_data->wp_status)
+		return host->plat_data->wp_status(mmc->parent);
+	else
+		return 0;
+}
+
+/*!
+ * MMC/SD host operations structure.
+ * These functions are registered with MMC/SD Bus protocol driver.
+ */
+static struct mmc_host_ops mxcmci_ops = {
+	.request = mxcmci_request,
+	.set_ios = mxcmci_set_ios,
+	.get_ro = mxcmci_get_ro,
+	.enable_sdio_irq = mxcmci_enable_sdio_irq,
+};
+
+#ifdef MXC_MMC_DMA_ENABLE
+/*!
+ * This function is called by DMA Interrupt Service Routine to indicate
+ * requested DMA transfer is completed.
+ *
+ * @param   devid  pointer to device specific structure
+ * @param   error any DMA error
+ * @param   cnt   amount of data that was transferred
+ */
+static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt)
+{
+	struct mxcmci_host *host = devid;
+	u32 status;
+	ulong nob, blk_size, i, blk_len;
+
+	mxc_dma_disable(host->dma);
+
+	if (error) {
+		printk(KERN_ERR "Error in DMA transfer\n");
+		status = __raw_readl(host->base + MMC_STATUS);
+#ifdef CONFIG_MMC_DEBUG
+		dump_status(__FUNCTION__, status);
+#endif
+		mxcmci_data_done(host, status);
+		return;
+	}
+	pr_debug("%s: Transfered bytes:%d\n", DRIVER_NAME, cnt);
+	nob = __raw_readl(host->base + MMC_REM_NOB);
+	blk_size = __raw_readl(host->base + MMC_REM_BLK_SIZE);
+	blk_len = __raw_readl(host->base + MMC_BLK_LEN);
+	pr_debug("%s: REM_NOB:%lu REM_BLK_SIZE:%lu\n", DRIVER_NAME, nob,
+		 blk_size);
+	i = 0;
+
+	/* Enable the WRITE OP Done INT */
+	status = __raw_readl(host->base + MMC_INT_CNTR);
+	__raw_writel((INT_CNTR_READ_OP_DONE | INT_CNTR_WRITE_OP_DONE | status),
+		     host->base + MMC_INT_CNTR);
+}
+#endif
+
+/*!
+ * This function is called during the driver binding process. Based on the SDHC
+ * module that is being probed this function adds the appropriate SDHC module
+ * structure in the core driver.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions.
+ *
+ * @return  The function returns 0 on successful registration and initialization
+ *          of SDHC module. Otherwise returns specific error code.
+ */
+static int mxcmci_probe(struct platform_device *pdev)
+{
+	struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data;
+	struct mmc_host *mmc;
+	struct mxcmci_host *host = NULL;
+	int card_gpio_status;
+	int ret = -ENODEV;
+
+	if (!mmc_plat) {
+		return -EINVAL;
+	}
+
+	mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
+	if (!mmc) {
+		return -ENOMEM;
+	}
+	host = mmc_priv(mmc);
+	platform_set_drvdata(pdev, mmc);
+
+	mmc->ops = &mxcmci_ops;
+	mmc->ocr_avail = mmc_plat->ocr_mask;
+
+	/* Hack to work with LP1070 */
+	if (mmc->ocr_avail && ~(MMC_VDD_31_32 - 1) == 0)
+		mmc->ocr_avail |= MMC_VDD_31_32;
+
+	mmc->max_phys_segs = NR_SG;
+	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+
+	mmc->f_min = mmc_plat->min_clk;
+	mmc->f_max = mmc_plat->max_clk;
+	mmc->max_req_size = 32 * 1024;
+	mmc->max_seg_size = mmc->max_req_size;
+	mmc->max_blk_count = 32;
+
+	spin_lock_init(&host->lock);
+	host->mmc = mmc;
+	host->dma = -1;
+	host->dma_dir = DMA_NONE;
+	host->id = pdev->id;
+	host->mxc_mmc_suspend_flag = 0;
+	host->mode = -1;
+	host->plat_data = mmc_plat;
+	if (!host->plat_data) {
+		ret = -EINVAL;
+		goto out0;
+	}
+
+	/* Get pwr supply for SDHC */
+	if (NULL != mmc_plat->power_mmc) {
+		host->regulator_mmc =
+		    regulator_get(&pdev->dev, mmc_plat->power_mmc);
+		if (IS_ERR(host->regulator_mmc)) {
+			ret = PTR_ERR(host->regulator_mmc);
+			goto out1;
+		}
+		if (!regulator_is_enabled(host->regulator_mmc)) {
+			if (regulator_enable(host->regulator_mmc) == 0) {
+				pr_debug("mmc power on\n");
+				msleep(1);
+			}
+		}
+	}
+
+	gpio_sdhc_active(pdev->id);
+
+	host->clk = clk_get(&pdev->dev, "sdhc_clk");
+	pr_debug("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk));
+	clk_enable(host->clk);
+
+	host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!host->res) {
+		ret = -ENOMEM;
+		goto out2;
+	}
+
+	if (!request_mem_region(host->res->start,
+				host->res->end -
+				host->res->start + 1, pdev->name)) {
+		printk(KERN_ERR "request_mem_region failed\n");
+		ret = -ENOMEM;
+		goto out2;
+	}
+	host->base = (void *)IO_ADDRESS(host->res->start);
+	if (!host->base) {
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	host->irq = platform_get_irq(pdev, 0);
+	if (!host->irq) {
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	if (!host->plat_data->card_fixed) {
+		host->detect_irq = platform_get_irq(pdev, 1);
+		if (!host->detect_irq)
+			goto out3;
+
+		do {
+			card_gpio_status =
+			    host->plat_data->status(host->mmc->parent);
+			if (card_gpio_status)
+				set_irq_type(host->detect_irq,
+					     IRQF_TRIGGER_FALLING);
+			else
+				set_irq_type(host->detect_irq,
+					     IRQF_TRIGGER_RISING);
+
+		} while (card_gpio_status !=
+			 host->plat_data->status(host->mmc->parent));
+
+		ret = request_irq(host->detect_irq, mxcmci_gpio_irq, 0,
+				  pdev->name, host);
+		if (ret)
+			goto out3;
+	}
+
+	mxcmci_softreset(host);
+
+	if (__raw_readl(host->base + MMC_REV_NO) != SDHC_REV_NO) {
+		printk(KERN_ERR "%s: wrong rev.no. 0x%08x. aborting.\n",
+		       pdev->name, MMC_REV_NO);
+		goto out3;
+	}
+	__raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO);
+
+	__raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR);
+
+	ret = request_irq(host->irq, mxcmci_irq, 0, pdev->name, host);
+	if (ret) {
+		goto out4;
+	}
+
+	if ((ret = mmc_add_host(mmc)) < 0) {
+		goto out5;
+	}
+
+	printk(KERN_INFO "%s-%d found\n", pdev->name, pdev->id);
+	if (host->id < MAX_HOST)
+		hosts[host->id] = host->mmc;
+
+	return 0;
+
+      out5:
+	free_irq(host->irq, host);
+      out4:
+	free_irq(host->detect_irq, host);
+      out3:
+	release_mem_region(pdev->resource[0].start,
+			   pdev->resource[0].end - pdev->resource[0].start + 1);
+      out2:
+	clk_disable(host->clk);
+	regulator_disable(host->regulator_mmc);
+	regulator_put(host->regulator_mmc);
+      out1:
+	gpio_sdhc_inactive(pdev->id);
+      out0:
+	mmc_free_host(mmc);
+	platform_set_drvdata(pdev, NULL);
+	return ret;
+}
+
+/*!
+ * Dissociates the driver from the SDHC device. Removes the appropriate SDHC
+ * module structure from the core driver.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxcmci_remove(struct platform_device *pdev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(pdev);
+
+	if (mmc) {
+		struct mxcmci_host *host = mmc_priv(mmc);
+
+		hosts[host->id] = NULL;
+		mmc_remove_host(mmc);
+		free_irq(host->irq, host);
+		free_irq(host->detect_irq, host);
+#ifdef MXC_MMC_DMA_ENABLE
+		mxc_dma_free(host->dma);
+#endif
+		release_mem_region(host->res->start,
+				   host->res->end - host->res->start + 1);
+		mmc_free_host(mmc);
+		if (NULL != host->regulator_mmc)
+			regulator_put(host->regulator_mmc);
+		gpio_sdhc_inactive(pdev->id);
+	}
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+/*!
+ * This function is called to put the SDHC in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mxcmci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(pdev);
+	struct mxcmci_host *host = mmc_priv(mmc);
+	int ret = 0;
+
+	if (mmc) {
+		host->mxc_mmc_suspend_flag = 1;
+		ret = mmc_suspend_host(mmc, state);
+	}
+
+	clk_disable(host->clk);
+	/*
+	 * The CD INT should be disabled in the suspend
+	 * and enabled in resumed.
+	 * Otherwise, the system would be halt when wake
+	 * up with the situation that there is a card
+	 * insertion during the system is in suspend mode.
+	 */
+	disable_irq(host->detect_irq);
+
+	gpio_sdhc_inactive(pdev->id);
+
+	if (host->regulator_mmc)
+		regulator_disable(host->regulator_mmc);
+
+	return ret;
+}
+
+/*!
+ * This function is called to bring the SDHC back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mxcmci_resume(struct platform_device *pdev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(pdev);
+	struct mxcmci_host *host = mmc_priv(mmc);
+	int ret = 0;
+
+	/*
+	 * Note that a card insertion interrupt will cause this
+	 * driver to resume automatically.  In that case we won't
+	 * actually have to do any work here.  Return success.
+	 */
+	if (!host->mxc_mmc_suspend_flag) {
+		return 0;
+	}
+
+	/* enable pwr supply for SDHC */
+	if (host->regulator_mmc && !regulator_is_enabled(host->regulator_mmc)) {
+		regulator_enable(host->regulator_mmc);
+		msleep(1);
+	}
+
+	gpio_sdhc_active(pdev->id);
+
+	clk_enable(host->clk);
+
+	if (mmc) {
+		ret = mmc_resume_host(mmc);
+		host->mxc_mmc_suspend_flag = 0;
+	}
+
+	enable_irq(host->detect_irq);
+
+	return ret;
+}
+#else
+#define mxcmci_suspend  NULL
+#define mxcmci_resume   NULL
+#endif				/* CONFIG_PM */
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcmci_driver = {
+	.driver = {
+		   .name = "mxcmci",
+		   },
+	.probe = mxcmci_probe,
+	.remove = mxcmci_remove,
+	.suspend = mxcmci_suspend,
+	.resume = mxcmci_resume,
+};
+
+/*!
+ * This function is used to initialize the MMC/SD driver module. The function
+ * registers the power management callback functions with the kernel and also
+ * registers the MMC/SD callback functions with the core MMC/SD driver.
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxcmci_init(void)
+{
+	printk(KERN_INFO "MXC MMC/SD driver\n");
+	return platform_driver_register(&mxcmci_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxcmci_exit(void)
+{
+	platform_driver_unregister(&mxcmci_driver);
+}
+
+module_init(mxcmci_init);
+module_exit(mxcmci_exit);
+
+MODULE_DESCRIPTION("MXC Multimedia Card Interface Driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/mxc_mmc.h b/drivers/mmc/host/mxc_mmc.h
new file mode 100644
index 000000000000..3ad45377dde6
--- /dev/null
+++ b/drivers/mmc/host/mxc_mmc.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXC_MMC_REG_H__
+#define __MXC_MMC_REG_H__
+
+#include <mach/hardware.h>
+
+/*!
+ * @defgroup MMC_SD MMC/SD Driver
+ */
+
+/*!
+ * @file mxc_mmc.h
+ *
+ * @brief Driver for the Freescale Semiconductor MXC SDHC modules.
+ *
+ * This file defines offsets and bits of SDHC registers. SDHC is also referred as
+ * MMC/SD controller
+ *
+ * @ingroup MMC_SD
+ */
+
+/*!
+ * Number of SDHC modules
+ */
+
+#define SDHC_MMC_WML                    16
+#define SDHC_SD_WML                     64
+#define DRIVER_NAME                     "MXCMMC"
+#define SDHC_MEM_SIZE                   16384
+#define SDHC_REV_NO                     0x400
+#define READ_TO_VALUE                   0x2db4
+
+/* Address offsets of the SDHC registers */
+#define MMC_STR_STP_CLK                 0x00	/* Clock Control Reg */
+#define MMC_STATUS                      0x04	/* Status Reg */
+#define MMC_CLK_RATE                    0x08	/* Clock Rate Reg */
+#define MMC_CMD_DAT_CONT                0x0C	/* Command and Data Control Reg */
+#define MMC_RES_TO                      0x10	/* Response Time-out Reg */
+#define MMC_READ_TO                     0x14	/* Read Time-out Reg */
+#define MMC_BLK_LEN                     0x18	/* Block Length Reg */
+#define MMC_NOB                         0x1C	/* Number of Blocks Reg */
+#define MMC_REV_NO                      0x20	/* Revision Number Reg */
+#define MMC_INT_CNTR                    0x24	/* Interrupt Control Reg */
+#define MMC_CMD                         0x28	/* Command Number Reg */
+#define MMC_ARG                         0x2C	/* Command Argument Reg */
+#define MMC_RES_FIFO                    0x34	/* Command Response Reg */
+#define MMC_BUFFER_ACCESS               0x38	/* Data Buffer Access Reg */
+#define MMC_REM_NOB                     0x40	/* Remaining NOB Reg */
+#define MMC_REM_BLK_SIZE                0x44	/* Remaining Block Size Reg */
+
+/* Bit definitions for STR_STP_CLK */
+#define STR_STP_CLK_RESET               (1<<3)
+#define STR_STP_CLK_START_CLK           (1<<1)
+#define STR_STP_CLK_STOP_CLK            (1<<0)
+
+/* Bit definitions for STATUS */
+#define STATUS_CARD_INSERTION           (1<<31)
+#define STATUS_CARD_REMOVAL             (1<<30)
+#define STATUS_YBUF_EMPTY               (1<<29)
+#define STATUS_XBUF_EMPTY               (1<<28)
+#define STATUS_YBUF_FULL                (1<<27)
+#define STATUS_XBUF_FULL                (1<<26)
+#define STATUS_BUF_UND_RUN              (1<<25)
+#define STATUS_BUF_OVFL                 (1<<24)
+#define STATUS_SDIO_INT_ACTIVE          (1<<14)
+#define STATUS_END_CMD_RESP             (1<<13)
+#define STATUS_WRITE_OP_DONE            (1<<12)
+#define STATUS_READ_OP_DONE             (1<<11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK   (3<<9)
+#define STATUS_CARD_BUS_CLK_RUN         (1<<8)
+#define STATUS_BUF_READ_RDY             (1<<7)
+#define STATUS_BUF_WRITE_RDY            (1<<6)
+#define STATUS_RESP_CRC_ERR             (1<<5)
+#define STATUS_READ_CRC_ERR             (1<<3)
+#define STATUS_WRITE_CRC_ERR            (1<<2)
+#define STATUS_TIME_OUT_RESP            (1<<1)
+#define STATUS_TIME_OUT_READ            (1<<0)
+#define STATUS_ERR_MASK                 0x3f
+
+/* Clock rate definitions */
+#define CLK_RATE_PRESCALER(x)           ((x) & 0xF)
+#define CLK_RATE_CLK_DIVIDER(x)         (((x) & 0xF) << 4)
+
+/* Bit definitions for CMD_DAT_CONT */
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF  (1<<12)
+#define CMD_DAT_CONT_STOP_READWAIT      (1<<11)
+#define CMD_DAT_CONT_START_READWAIT     (1<<10)
+#define CMD_DAT_CONT_BUS_WIDTH_1        (0<<8)
+#define CMD_DAT_CONT_BUS_WIDTH_4        (2<<8)
+#define CMD_DAT_CONT_INIT               (1<<7)
+#define CMD_DAT_CONT_WRITE              (1<<4)
+#define CMD_DAT_CONT_DATA_ENABLE        (1<<3)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6)
+
+/* Bit definitions for INT_CNTR */
+#define INT_CNTR_SDIO_INT_WKP_EN        (1<<18)
+#define INT_CNTR_CARD_INSERTION_WKP_EN  (1<<17)
+#define INT_CNTR_CARD_REMOVAL_WKP_EN    (1<<16)
+#define INT_CNTR_CARD_INSERTION_EN      (1<<15)
+#define INT_CNTR_CARD_REMOVAL_EN        (1<<14)
+#define INT_CNTR_SDIO_IRQ_EN            (1<<13)
+#define INT_CNTR_DAT0_EN                (1<<12)
+#define INT_CNTR_BUF_READ_EN            (1<<4)
+#define INT_CNTR_BUF_WRITE_EN           (1<<3)
+#define INT_CNTR_END_CMD_RES            (1<<2)
+#define INT_CNTR_WRITE_OP_DONE          (1<<1)
+#define INT_CNTR_READ_OP_DONE           (1<<0)
+
+#endif				/* __MXC_MMC_REG_H__ */
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
new file mode 100644
index 000000000000..b7210b7d7af3
--- /dev/null
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -0,0 +1,1325 @@
+/*
+ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
+ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/highmem.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/mmc/host.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/hardware.h>
+#include <mach/dmaengine.h>
+#include <mach/regs-ssp.h>
+#include <mach/device.h>
+#include <mach/system.h>
+
+#define DRIVER_NAME	"mxs-mmc"
+
+/*
+ * Card detect polling timeout
+ */
+#define MXS_MMC_DETECT_TIMEOUT		(HZ/2)
+
+/* Max value supported for XFER_COUNT */
+#define SSP_BUFFER_SIZE		(65535)
+
+#ifndef BF
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+#endif
+
+#ifndef HW_SSP_XFER_SIZE
+#define HW_SSP_XFER_SIZE	(0xFFFFFFFF)
+#endif
+#ifndef HW_SSP_BLOCK_SIZE
+#define HW_SSP_BLOCK_SIZE	(0xFFFFFFFF)
+#endif
+
+#ifndef BP_SSP_XFER_SIZE_XFER_COUNT
+#define BP_SSP_XFER_SIZE_XFER_COUNT BP_SSP_CTRL0_XFER_COUNT
+#endif
+#ifndef BM_SSP_XFER_SIZE_XFER_COUNT
+#define BM_SSP_XFER_SIZE_XFER_COUNT BM_SSP_CTRL0_XFER_COUNT
+#endif
+#ifndef BF_SSP_XFER_SIZE_XFER_COUNT
+#define BF_SSP_XFER_SIZE_XFER_COUNT(v)  \
+		(((v) << 0) & BM_SSP_CTRL0_XFER_COUNT)
+#endif
+
+#ifndef BP_SSP_BLOCK_SIZE_BLOCK_COUNT
+#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT	8
+#endif
+#ifndef BM_SSP_BLOCK_SIZE_BLOCK_COUNT
+#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT	0x0000FF00
+#endif
+#ifndef BF_SSP_BLOCK_SIZE_BLOCK_COUNT
+#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v)  \
+		(((v) << 8) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT)
+#endif
+#ifndef BP_SSP_BLOCK_SIZE_BLOCK_SIZE
+#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE	16
+#endif
+#ifndef BM_SSP_BLOCK_SIZE_BLOCK_SIZE
+#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE	0x000F0000
+#endif
+#ifndef BF_SSP_BLOCK_SIZE_BLOCK_SIZE
+#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v)  \
+		(((v) << 16) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE)
+#endif
+#ifndef BM_SSP_CMD0_DBL_DATA_RATE_EN
+#define BM_SSP_CMD0_DBL_DATA_RATE_EN	0x02000000
+#endif
+
+struct mxs_mmc_host {
+	struct device *dev;
+	struct mmc_host *mmc;
+
+	struct clk *clk;
+	unsigned int clkrt;
+
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+
+	/*  data bus width 0:1bit, 1:4bit, 2:8bit */
+	unsigned char	bus_width;
+
+	/* Whether SD card is present */
+	unsigned present:1;
+
+	/* Polling timer */
+	struct timer_list timer;
+
+	/* SSP interface which MMC/SD card slot is attached to */
+	void __iomem *ssp_base;
+
+	/* DMA channel used for this host */
+	unsigned int dmach;
+
+	/* IRQs */
+	int dmairq, errirq;
+
+	/* DMA descriptor to transfer data over SSP interface */
+	struct mxs_dma_desc *dma_desc;
+
+	/* DMA buffer */
+	dma_addr_t dma_buf_phys;
+	char *dma_buf;
+
+	struct completion dma_done;
+	/* status on last interrupt */
+	u32 status;
+	int read_uA, write_uA;
+	struct regulator *regulator;	/*! Regulator */
+
+	spinlock_t lock;
+	int sdio_irq_en;
+};
+
+/* Return read only state of card */
+static int mxs_mmc_get_ro(struct mmc_host *mmc)
+{
+	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_mmc_platform_data *mmc_data = host->dev->platform_data;
+
+	if (mmc_data && mmc_data->get_wp)
+		return mmc_data->get_wp();
+
+	return 0;
+}
+
+/* Detect if card is plugged */
+static inline int mxs_mmc_is_plugged(struct mxs_mmc_host *host)
+{
+	u32 status = __raw_readl(host->ssp_base + HW_SSP_STATUS);
+	return !(status & BM_SSP_STATUS_CARD_DETECT);
+}
+
+static void mxs_mmc_reset(struct mxs_mmc_host *host);
+/* Card detection polling function */
+static void mxs_mmc_detect_poll(unsigned long arg)
+{
+	struct mxs_mmc_host *host = (struct mxs_mmc_host *)arg;
+	int card_status;
+
+	card_status = mxs_mmc_is_plugged(host);
+	if (card_status != host->present) {
+		/* Reset MMC block */
+		mxs_mmc_reset(host);
+		host->present = card_status;
+		mmc_detect_change(host->mmc, 0);
+	}
+
+	mod_timer(&host->timer, jiffies + MXS_MMC_DETECT_TIMEOUT);
+}
+
+#define MXS_MMC_IRQ_BITS  (BM_SSP_CTRL1_SDIO_IRQ		| \
+				BM_SSP_CTRL1_RESP_ERR_IRQ	| \
+				BM_SSP_CTRL1_RESP_TIMEOUT_IRQ	| \
+				BM_SSP_CTRL1_DATA_TIMEOUT_IRQ	| \
+				BM_SSP_CTRL1_DATA_CRC_IRQ	| \
+				BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ	| \
+				BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
+
+#define MXS_MMC_ERR_BITS (BM_SSP_CTRL1_RESP_ERR_IRQ       | \
+				BM_SSP_CTRL1_RESP_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_DATA_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_DATA_CRC_IRQ       | \
+				BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)
+
+/* SSP DMA interrupt handler */
+static irqreturn_t mmc_irq_handler(int irq, void *dev_id)
+{
+	struct mxs_mmc_host *host = dev_id;
+	u32 c1;
+
+	c1 = __raw_readl(host->ssp_base + HW_SSP_CTRL1);
+	__raw_writel(c1 & MXS_MMC_IRQ_BITS,
+			host->ssp_base + HW_SSP_CTRL1_CLR);
+	if (irq == host->dmairq) {
+		dev_dbg(host->dev, "dma irq 0x%x and stop DMA.\n", irq);
+		mxs_dma_ack_irq(host->dmach);
+		/* STOP the dma transfer here. */
+		mxs_dma_cooked(host->dmach, NULL);
+	}
+
+	if ((irq == host->dmairq) || (c1 & MXS_MMC_ERR_BITS))
+		if (host->cmd) {
+			host->status =
+				__raw_readl(host->ssp_base + HW_SSP_STATUS);
+			complete(&host->dma_done);
+		}
+
+	if ((c1 & BM_SSP_CTRL1_SDIO_IRQ) && (c1 & BM_SSP_CTRL1_SDIO_IRQ_EN))
+		mmc_signal_sdio_irq(host->mmc);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Check for MMC command errors
+ * Returns error code or zerro if no errors
+ */
+static inline int mxs_mmc_cmd_error(u32 status)
+{
+	int err = 0;
+
+	if (status & BM_SSP_STATUS_TIMEOUT)
+		err = -ETIMEDOUT;
+	else if (status & BM_SSP_STATUS_RESP_TIMEOUT)
+		err = -ETIMEDOUT;
+	else if (status & BM_SSP_STATUS_RESP_CRC_ERR)
+		err = -EILSEQ;
+	else if (status & BM_SSP_STATUS_RESP_ERR)
+		err = -EIO;
+
+	return err;
+}
+
+/* Send the BC command to the device */
+static void mxs_mmc_bc(struct mxs_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct mxs_dma_desc *dma_desc = host->dma_desc;
+	unsigned long flags;
+
+	dma_desc->cmd.cmd.bits.command = NO_DMA_XFER;
+	dma_desc->cmd.cmd.bits.irq = 1;
+	dma_desc->cmd.cmd.bits.dec_sem = 1;
+	dma_desc->cmd.cmd.bits.wait4end = 1;
+	dma_desc->cmd.cmd.bits.pio_words = 3;
+	dma_desc->cmd.cmd.bits.bytes = 0;
+
+	dma_desc->cmd.pio_words[0] = BM_SSP_CTRL0_ENABLE |
+	    BM_SSP_CTRL0_IGNORE_CRC;
+	dma_desc->cmd.pio_words[1] = BF(cmd->opcode, SSP_CMD0_CMD) |
+	    BM_SSP_CMD0_APPEND_8CYC;
+	dma_desc->cmd.pio_words[2] = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	if (host->sdio_irq_en) {
+		dma_desc->cmd.pio_words[0] |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+		dma_desc->cmd.pio_words[1] |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
+	}
+
+	init_completion(&host->dma_done);
+	mxs_dma_reset(host->dmach);
+	if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0)
+		dev_err(host->dev, "mmc_dma_desc_append failed\n");
+	dev_dbg(host->dev, "%s start DMA.\n", __func__);
+	if (mxs_dma_enable(host->dmach) < 0)
+		dev_err(host->dev, "mmc_dma_enable failed\n");
+
+	wait_for_completion(&host->dma_done);
+
+	cmd->error = mxs_mmc_cmd_error(host->status);
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		mxs_dma_reset(host->dmach);
+	}
+	mxs_dma_disable(host->dmach);
+}
+
+/* Send the ac command to the device */
+static void mxs_mmc_ac(struct mxs_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct mxs_dma_desc *dma_desc = host->dma_desc;
+	u32 ignore_crc, resp, long_resp;
+	u32 ssp_ctrl0;
+	u32 ssp_cmd0;
+	u32 ssp_cmd1;
+	unsigned long flags;
+
+	ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+	    0 : BM_SSP_CTRL0_IGNORE_CRC;
+	resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+	    BM_SSP_CTRL0_GET_RESP : 0;
+	long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+	    BM_SSP_CTRL0_LONG_RESP : 0;
+
+	dma_desc->cmd.cmd.bits.command = NO_DMA_XFER;
+	dma_desc->cmd.cmd.bits.irq = 1;
+	dma_desc->cmd.cmd.bits.dec_sem = 1;
+	dma_desc->cmd.cmd.bits.wait4end = 1;
+	dma_desc->cmd.cmd.bits.pio_words = 3;
+	dma_desc->cmd.cmd.bits.bytes = 0;
+
+	ssp_ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | long_resp | resp;
+	ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD);
+	ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	if (host->sdio_irq_en) {
+		ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
+	}
+
+	dma_desc->cmd.pio_words[0] = ssp_ctrl0;
+	dma_desc->cmd.pio_words[1] = ssp_cmd0;
+	dma_desc->cmd.pio_words[2] = ssp_cmd1;
+
+	mxs_dma_reset(host->dmach);
+	init_completion(&host->dma_done);
+	if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0)
+		dev_err(host->dev, "mmc_dma_desc_append failed\n");
+	dev_dbg(host->dev, "%s start DMA.\n", __func__);
+	if (mxs_dma_enable(host->dmach) < 0)
+		dev_err(host->dev, "mmc_dma_enable failed\n");
+	wait_for_completion(&host->dma_done);
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_NONE:
+		while (__raw_readl(host->ssp_base + HW_SSP_CTRL0)
+		       & BM_SSP_CTRL0_RUN)
+			continue;
+		break;
+	case MMC_RSP_R1:
+	case MMC_RSP_R1B:
+	case MMC_RSP_R3:
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		break;
+	case MMC_RSP_R2:
+		cmd->resp[3] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		cmd->resp[2] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP1);
+		cmd->resp[1] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP2);
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP3);
+		break;
+	default:
+		dev_warn(host->dev, "Unsupported response type 0x%x\n",
+			 mmc_resp_type(cmd));
+		BUG();
+		break;
+	}
+
+	cmd->error = mxs_mmc_cmd_error(host->status);
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		mxs_dma_reset(host->dmach);
+	}
+	mxs_dma_disable(host->dmach);
+}
+
+/* Copy data between sg list and dma buffer */
+static unsigned int mxs_sg_dma_copy(struct mxs_mmc_host *host,
+					 unsigned int size, int to_dma)
+{
+	struct mmc_data *data = host->cmd->data;
+	unsigned int copy_size, bytes_copied = 0;
+	struct scatterlist *sg;
+	char *dmabuf = host->dma_buf;
+	char *sgbuf;
+	int len, i;
+
+	sg = data->sg;
+	len = data->sg_len;
+
+	/*
+	 * Just loop through all entries. Size might not
+	 * be the entire list though so make sure that
+	 * we do not transfer too much.
+	 */
+	for (i = 0; i < len; i++) {
+		sgbuf = kmap_atomic(sg_page(&sg[i]), KM_BIO_SRC_IRQ) +
+		    sg[i].offset;
+		copy_size = size < sg[i].length ? size : sg[i].length;
+		if (to_dma)
+			memcpy(dmabuf, sgbuf, copy_size);
+		else
+			memcpy(sgbuf, dmabuf, copy_size);
+		kunmap_atomic(sgbuf, KM_BIO_SRC_IRQ);
+
+		dmabuf += sg[i].length;
+
+		bytes_copied += copy_size;
+		size -= copy_size;
+
+		if (size == 0)
+			break;
+	}
+
+	return bytes_copied;
+}
+
+/* Convert ns to tick count according to the current sclk speed */
+static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
+{
+	const unsigned int ssp_timeout_mul = 4096;
+	/*
+	 * Calculate ticks in ms since ns are large numbers
+	 * and might overflow
+	 */
+	const unsigned int clock_per_ms = clock_rate / 1000;
+	const unsigned int ms = ns / 1000;
+	const unsigned int ticks = ms * clock_per_ms;
+	const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
+
+	BUG_ON(ssp_ticks == 0);
+	return ssp_ticks;
+}
+
+static void __init_reg(struct device *dev, struct regulator **pp_reg)
+{
+#if 0
+	/* Up to now, there is not pwr ctrl. Just keep it for future usage. */
+	struct regulator *reg = *pp_reg;
+
+	if (!reg) {
+		reg = regulator_get(NULL, "mmc_ssp-1");
+		if (reg && !IS_ERR(reg))
+			regulator_set_mode(reg, REGULATOR_MODE_NORMAL);
+		else
+			reg = NULL;
+		*pp_reg = reg;
+	}
+#endif
+}
+
+/* Send adtc command to the card */
+static void mxs_mmc_adtc(struct mxs_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct mxs_dma_desc *dma_desc = host->dma_desc;
+	int ignore_crc, resp, long_resp;
+	int is_reading = 0;
+	unsigned int copy_size;
+	unsigned int ssp_ver_major;
+
+	u32 ssp_ctrl0;
+	u32 ssp_cmd0;
+	u32 ssp_cmd1;
+	u32 timeout;
+	u32 val;
+
+	u32 data_size = cmd->data->blksz * cmd->data->blocks;
+	u32 log2_block_size;
+	unsigned long flags;
+
+	ignore_crc = mmc_resp_type(cmd) & MMC_RSP_CRC ? 0 : 1;
+	resp = mmc_resp_type(cmd) & MMC_RSP_PRESENT ? 1 : 0;
+	long_resp = mmc_resp_type(cmd) & MMC_RSP_136 ? 1 : 0;
+
+	dev_dbg(host->dev, "ADTC command:\n"
+		"response: %d, ignore crc: %d\n"
+		"data list: %u, blocksz: %u, blocks: %u, timeout: %uns %uclks, "
+		"flags: 0x%x\n", resp, ignore_crc, cmd->data->sg_len,
+		cmd->data->blksz, cmd->data->blocks, cmd->data->timeout_ns,
+		cmd->data->timeout_clks, cmd->data->flags);
+
+	if (cmd->data->flags & MMC_DATA_WRITE) {
+		dev_dbg(host->dev, "Data Write\n");
+		copy_size = mxs_sg_dma_copy(host, data_size, 1);
+		BUG_ON(copy_size < data_size);
+		is_reading = 0;
+		if (!host->regulator)
+			__init_reg(host->dev, &host->regulator);
+		if (host->regulator)
+			regulator_set_current_limit(host->regulator,
+						    host->write_uA,
+						    host->write_uA);
+	} else if (cmd->data->flags & MMC_DATA_READ) {
+		dev_dbg(host->dev, "Data Read\n");
+		is_reading = 1;
+		if (!host->regulator)
+			__init_reg(host->dev, &host->regulator);
+		if (host->regulator)
+			regulator_set_current_limit(host->regulator,
+						    host->read_uA,
+						    host->read_uA);
+	} else {
+		dev_warn(host->dev, "Unsuspported data mode, 0x%x\n",
+			 cmd->data->flags);
+		BUG();
+	}
+
+	BUG_ON(cmd->data->flags & MMC_DATA_STREAM);
+	/* BUG_ON((data_size % 8) > 0); */
+
+	/* when is_reading is set, DMA controller performs WRITE operation. */
+	dma_desc->cmd.cmd.bits.command = is_reading ? DMA_WRITE : DMA_READ;
+	dma_desc->cmd.cmd.bits.irq = 1;
+	dma_desc->cmd.cmd.bits.dec_sem = 1;
+	dma_desc->cmd.cmd.bits.wait4end = 1;
+	dma_desc->cmd.cmd.bits.pio_words = 3;
+	dma_desc->cmd.cmd.bits.bytes = data_size;
+
+	ssp_ver_major = __raw_readl(host->ssp_base + HW_SSP_VERSION) >> 24;
+	dev_dbg(host->dev, "ssp ver major is 0x%x\n", ssp_ver_major);
+	if (ssp_ver_major > 3) {
+		__raw_writel(data_size, host->ssp_base + HW_SSP_XFER_SIZE);
+		ssp_ctrl0 = (ignore_crc ? BM_SSP_CTRL0_IGNORE_CRC : 0) |
+			(resp ? BM_SSP_CTRL0_GET_RESP : 0) |
+			(long_resp ? BM_SSP_CTRL0_LONG_RESP : 0) |
+			(is_reading ? BM_SSP_CTRL0_READ : 0) |
+			BM_SSP_CTRL0_DATA_XFER | BM_SSP_CTRL0_WAIT_FOR_IRQ |
+			BM_SSP_CTRL0_ENABLE;
+		if (host->bus_width == 2)
+			ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT,
+					     SSP_CTRL0_BUS_WIDTH);
+		else if (host->bus_width == 1)
+			ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT,
+					     SSP_CTRL0_BUS_WIDTH);
+		else
+			ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT,
+					     SSP_CTRL0_BUS_WIDTH);
+	} else
+		ssp_ctrl0 = (ignore_crc ? BM_SSP_CTRL0_IGNORE_CRC : 0) |
+			(resp ? BM_SSP_CTRL0_GET_RESP : 0) |
+			(long_resp ? BM_SSP_CTRL0_LONG_RESP : 0) |
+			(is_reading ? BM_SSP_CTRL0_READ : 0) |
+			BM_SSP_CTRL0_DATA_XFER | BM_SSP_CTRL0_WAIT_FOR_IRQ |
+			BM_SSP_CTRL0_ENABLE |
+			BF(data_size, SSP_XFER_SIZE_XFER_COUNT) |
+			BF(host->bus_width ?
+			BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT :
+					     BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT,
+					     SSP_CTRL0_BUS_WIDTH);
+
+	/*
+	 * We need to set the hardware register to the logarithm to base 2 of
+	 * the block size.
+	 */
+	log2_block_size = ilog2(cmd->data->blksz);
+	dev_dbg(host->dev, "%s blksz is 0x%x.\n", __func__, log2_block_size);
+
+	if (ssp_ver_major > 3) {
+		/* Configure the CMD0 */
+		ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD);
+
+		/* Configure the BLOCK SIZE and BLOCK COUNT */
+		if ((1<<log2_block_size) != cmd->data->blksz) {
+			BUG_ON(cmd->data->blocks > 1);
+			__raw_writel(0, host->ssp_base + HW_SSP_BLOCK_SIZE);
+		} else{
+			val = BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) |
+			BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT);
+			__raw_writel(val, host->ssp_base + HW_SSP_BLOCK_SIZE);
+			if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR)
+				/* Enable the DDR mode */
+				ssp_cmd0 |= BM_SSP_CMD0_DBL_DATA_RATE_EN;
+			else
+				ssp_cmd0 &= ~BM_SSP_CMD0_DBL_DATA_RATE_EN;
+
+		}
+	} else {
+		if ((1<<log2_block_size) != cmd->data->blksz) {
+			BUG_ON(cmd->data->blocks > 1);
+			ssp_cmd0 =
+				BF(0, SSP_BLOCK_SIZE_BLOCK_SIZE) |
+				BF(cmd->opcode, SSP_CMD0_CMD) |
+				BF(0, SSP_BLOCK_SIZE_BLOCK_COUNT);
+		} else
+			ssp_cmd0 =
+			BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) |
+			BF(cmd->opcode, SSP_CMD0_CMD) |
+			BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT);
+	}
+	if (host->sdio_irq_en) {
+		ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+		ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \
+			| BM_SSP_CMD0_SLOW_CLKING_EN;
+	}
+	if ((cmd->opcode == 12) || (cmd->opcode == 53))
+		ssp_cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
+
+	ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	dma_desc->cmd.pio_words[0] = ssp_ctrl0;
+	dma_desc->cmd.pio_words[1] = ssp_cmd0;
+	dma_desc->cmd.pio_words[2] = ssp_cmd1;
+
+	/* Set the timeout count */
+	timeout = mxs_ns_to_ssp_ticks(host->clkrt, cmd->data->timeout_ns);
+	val = __raw_readl(host->ssp_base + HW_SSP_TIMING);
+	val &= ~(BM_SSP_TIMING_TIMEOUT);
+	val |= BF(timeout, SSP_TIMING_TIMEOUT);
+	__raw_writel(val, host->ssp_base + HW_SSP_TIMING);
+
+	init_completion(&host->dma_done);
+	mxs_dma_reset(host->dmach);
+	if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0)
+		dev_err(host->dev, "mmc_dma_desc_append failed\n");
+	dev_dbg(host->dev, "%s start DMA.\n", __func__);
+	if (mxs_dma_enable(host->dmach) < 0)
+		dev_err(host->dev, "mmc_dma_enable failed\n");
+	wait_for_completion(&host->dma_done);
+	if (host->regulator)
+		regulator_set_current_limit(host->regulator, 0, 0);
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_NONE:
+		break;
+	case MMC_RSP_R1:
+	case MMC_RSP_R3:
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		break;
+	case MMC_RSP_R2:
+		cmd->resp[3] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		cmd->resp[2] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP1);
+		cmd->resp[1] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP2);
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP3);
+		break;
+	default:
+		dev_warn(host->dev, "Unsupported response type 0x%x\n",
+			 mmc_resp_type(cmd));
+		BUG();
+		break;
+	}
+
+	cmd->error = mxs_mmc_cmd_error(host->status);
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		mxs_dma_reset(host->dmach);
+	} else {
+		if (is_reading) {
+			cmd->data->bytes_xfered =
+			    mxs_sg_dma_copy(host, data_size, 0);
+		} else
+			cmd->data->bytes_xfered = data_size;
+
+		dev_dbg(host->dev, "Transferred %u bytes\n",
+			cmd->data->bytes_xfered);
+	}
+	mxs_dma_disable(host->dmach);
+}
+
+/* Begin sedning a command to the card */
+static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
+				   struct mmc_command *cmd)
+{
+	dev_dbg(host->dev, "MMC command:\n"
+		"type: 0x%x opcode: %u, arg: %u, flags 0x%x retries: %u\n",
+		mmc_cmd_type(cmd), cmd->opcode, cmd->arg, cmd->flags,
+		cmd->retries);
+
+	host->cmd = cmd;
+
+	switch (mmc_cmd_type(cmd)) {
+	case MMC_CMD_BC:
+		mxs_mmc_bc(host);
+		break;
+	case MMC_CMD_BCR:
+		mxs_mmc_ac(host);
+		break;
+	case MMC_CMD_AC:
+		mxs_mmc_ac(host);
+		break;
+	case MMC_CMD_ADTC:
+		mxs_mmc_adtc(host);
+		break;
+	default:
+		dev_warn(host->dev, "Unknown MMC command\n");
+		BUG();
+		break;
+	}
+
+	dev_dbg(host->dev, "response: %u %u %u %u errors: %u\n",
+		cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
+		cmd->error);
+}
+
+/* Handle MMC request */
+static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct mxs_mmc_host *host = mmc_priv(mmc);
+
+	dev_dbg(host->dev, "MMC request\n");
+
+	if (!host->present) {
+		mrq->cmd->error = -ETIMEDOUT;
+		mmc_request_done(mmc, mrq);
+		return;
+	}
+
+	BUG_ON(host->mrq != NULL);
+	host->mrq = mrq;
+
+	mxs_mmc_start_cmd(host, mrq->cmd);
+
+	if (mrq->data && mrq->data->stop) {
+		dev_dbg(host->dev, "Stop opcode is %u\n",
+			mrq->data->stop->opcode);
+		mxs_mmc_start_cmd(host, mrq->data->stop);
+	}
+
+	host->mrq = NULL;
+	mmc_request_done(mmc, mrq);
+}
+
+/*
+ * Change divisors to reflect the rate of 'hz'. Note that we should not
+ * play with clock rate, because the same source is used to clock both
+ * SSP ports.
+ */
+static void
+mxs_set_sclk_speed(struct mxs_mmc_host *host, unsigned int hz)
+{
+	unsigned long ssp, bus_clk = 0;
+	u32 div1, div2;
+	u32 val;
+	struct mxs_mmc_platform_data *mmc_data = host->dev->platform_data;
+
+	if (mmc_data && mmc_data->setclock) {
+		/* using SSP1, no timeout, clock rate 1 */
+		__raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) |
+			     BF(2, SSP_TIMING_CLOCK_DIVIDE) |
+			     BF(0, SSP_TIMING_CLOCK_RATE),
+			     host->ssp_base + HW_SSP_TIMING);
+
+		/*
+		   if the SSP is buggy and platform provides callback...
+		   well, let it be.
+		 */
+		host->clkrt = mmc_data->setclock(hz);
+		dev_dbg(host->dev, "Setting clock rate to %d Hz"
+			"(requested %d)\n",
+			host->clkrt, hz);
+		dev_dbg(host->dev, "source %ldk\n",
+			clk_get_rate(host->clk));
+
+		return;
+	}
+
+	/*
+	   ...but the RightIdea(tm) is to set divisors to match
+	   the requested clock.
+	 */
+	ssp = clk_get_rate(host->clk);
+
+	for (div1 = 2; div1 < 254; div1 += 2) {
+		div2 = ssp / hz / div1;
+		if (div2 < 0x100)
+			break;
+	}
+	if (div1 >= 254) {
+		dev_err(host->dev, "Cannot set clock to %dHz\n", hz);
+		return;
+	}
+
+	if (div2 == 0)
+		bus_clk = ssp / div1;
+	else
+		bus_clk = ssp / div1 / div2;
+
+	dev_dbg(host->dev, "Setting clock rate to %ld Hz [%x+%x] "
+		"(requested %d), source %ldk\n",
+		bus_clk, div1, div2, hz, ssp);
+
+	val = __raw_readl(host->ssp_base + HW_SSP_TIMING);
+	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
+	val |= BF(div1, SSP_TIMING_CLOCK_DIVIDE) |
+		      BF(div2 - 1, SSP_TIMING_CLOCK_RATE);
+	__raw_writel(val, host->ssp_base + HW_SSP_TIMING);
+
+	host->clkrt = bus_clk;
+}
+
+/* Configure card */
+static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_mmc_platform_data *mmc_data;
+
+	dev_dbg(host->dev, "MMC set ios:\n"
+		"Clock %u, vdd %u, bus_mode %u, chip_select %u, "
+		"power mode %u, bus_width %u\n", ios->clock, ios->vdd,
+		ios->bus_mode, ios->chip_select, ios->power_mode,
+		ios->bus_width);
+
+	mmc_data = host->dev->platform_data;
+
+	if (mmc_data->cmd_pullup) {
+		if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
+			mmc_data->cmd_pullup(0);
+		else
+			mmc_data->cmd_pullup(1);
+	} else
+		dev_warn(host->dev,
+			 "Platform does not support CMD pin pullup control\n");
+
+	if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8)
+		host->bus_width = 2;
+	else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4)
+		host->bus_width = 1;
+	else
+		host->bus_width = 0;
+	dev_dbg(host->dev, "MMC bus_width %u\n", host->bus_width);
+
+	if (ios->clock > 0)
+		mxs_set_sclk_speed(host, ios->clock);
+}
+
+static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	unsigned long flags;
+	struct mxs_mmc_host *host = mmc_priv(mmc);
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	if (enable) {
+		if (host->sdio_irq_en)
+			goto exit;
+		host->sdio_irq_en = 1;
+		__raw_writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, host->ssp_base + \
+			HW_SSP_CTRL0_SET);
+		__raw_writel(BM_SSP_CTRL1_SDIO_IRQ_EN, host->ssp_base + \
+			HW_SSP_CTRL1_SET);
+
+		if (__raw_readl(host->ssp_base + \
+		HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
+			mmc_signal_sdio_irq(host->mmc);
+
+	} else {
+		if (host->sdio_irq_en == 0)
+			goto exit;
+		host->sdio_irq_en = 0;
+		__raw_writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, \
+			host->ssp_base + HW_SSP_CTRL0_CLR);
+		__raw_writel(BM_SSP_CTRL1_SDIO_IRQ_EN, \
+			host->ssp_base + HW_SSP_CTRL1_CLR);
+	}
+
+exit:
+	spin_unlock_irqrestore(&host->lock, flags);
+	return;
+}
+
+static const struct mmc_host_ops mxs_mmc_ops = {
+	.request = mxs_mmc_request,
+	.get_ro = mxs_mmc_get_ro,
+	.set_ios = mxs_mmc_set_ios,
+	.enable_sdio_irq = mxs_mmc_enable_sdio_irq,
+};
+
+/*
+ * MXS MMC/SD driver initialization
+ */
+
+/* Reset ssp peripheral to default values */
+static void mxs_mmc_reset(struct mxs_mmc_host *host)
+{
+	u32 ssp_ctrl0;
+	u32 ssp_ctrl1;
+
+	mxs_reset_block(host->ssp_base, 0);
+
+	/* Configure SSP Control Register 0 */
+	ssp_ctrl0 =
+	    BM_SSP_CTRL0_IGNORE_CRC |
+	    BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, SSP_CTRL0_BUS_WIDTH);
+
+	/* Configure SSP Control Register 1 */
+	ssp_ctrl1 =
+	    BM_SSP_CTRL1_DMA_ENABLE |
+	    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
+	    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_RESP_ERR_IRQ_EN |
+	    BF(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS, SSP_CTRL1_WORD_LENGTH) |
+	    BF(BV_SSP_CTRL1_SSP_MODE__SD_MMC, SSP_CTRL1_SSP_MODE);
+
+	__raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) |
+		     BF(2, SSP_TIMING_CLOCK_DIVIDE) |
+		     BF(0, SSP_TIMING_CLOCK_RATE),
+		     host->ssp_base + HW_SSP_TIMING);
+
+	if (host->sdio_irq_en) {
+		ssp_ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
+		ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+       }
+
+	/* Write the SSP Control Register 0 and 1 values out to the interface */
+	__raw_writel(ssp_ctrl0, host->ssp_base + HW_SSP_CTRL0);
+	__raw_writel(ssp_ctrl1, host->ssp_base + HW_SSP_CTRL1);
+}
+
+static void mxs_mmc_irq_release(struct mxs_mmc_host *host)
+{
+	free_irq(host->dmairq, host);
+	free_irq(host->errirq, host);
+}
+
+static int __init mxs_mmc_irq_init(struct mxs_mmc_host *host)
+{
+	int ret;
+
+	ret = request_irq(host->dmairq, mmc_irq_handler, 0,
+			  DRIVER_NAME " dma", host);
+	if (ret) {
+		dev_err(host->dev, "Unable to set up DMA irq handler\n");
+		goto out0;
+	}
+
+	ret = request_irq(host->errirq, mmc_irq_handler, IRQF_SHARED,
+			  DRIVER_NAME " error", host);
+	if (ret) {
+		dev_err(host->dev, "Unable to set up SSP error irq handler\n");
+		goto out1;
+	}
+	return 0;
+
+out1:
+	free_irq(host->dmairq, host);
+out0:
+	return ret;
+}
+
+/* Allocate and initialise the DMA chains */
+static int mxs_mmc_dma_init(struct mxs_mmc_host *host, int reset)
+{
+	int ret = 0;
+
+	if (!reset) {
+		/* Allocate DMA channel */
+		ret = mxs_dma_request(host->dmach,
+					   host->dev, "MXS MMC/SD");
+		if (ret) {
+			dev_err(host->dev, "Unable to request DMA channel\n");
+			return ret;
+		}
+
+		host->dma_buf = dma_alloc_coherent(host->dev, SSP_BUFFER_SIZE,
+						   &host->dma_buf_phys,
+						   GFP_DMA);
+		if (host->dma_buf == NULL) {
+			dev_err(host->dev, "Unable to allocate DMA memory\n");
+			ret = -ENOMEM;
+			goto out_mem;
+		}
+
+		host->dma_desc = mxs_dma_alloc_desc();
+		if (host->dma_desc == NULL) {
+			dev_err(host->dev,
+				"Unable to allocate DMA descriptor\n");
+			ret = -ENOMEM;
+			goto out_cmd;
+		}
+
+		host->dma_desc->cmd.next = (u32) host->dma_desc->address;
+		host->dma_desc->cmd.address = (u32) host->dma_buf_phys;
+		host->dma_desc->buffer = host->dma_buf;
+	}
+
+	/* Reset DMA channel */
+	mxs_dma_reset(host->dmach);
+
+	/* Enable DMA interrupt */
+	mxs_dma_ack_irq(host->dmach);
+	mxs_dma_enable_irq(host->dmach, 1);
+
+	return 0;
+
+out_cmd:
+	dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf,
+			  host->dma_buf_phys);
+out_mem:
+	mxs_dma_release(host->dmach, host->dev);
+
+	return ret;
+}
+
+static void mxs_mmc_dma_release(struct mxs_mmc_host *host)
+{
+	mxs_dma_reset(host->dmach);
+
+	mxs_dma_enable_irq(host->dmach, 0);
+	mxs_dma_disable(host->dmach);
+	mxs_dma_get_cooked(host->dmach, NULL);
+
+	dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf,
+			  host->dma_buf_phys);
+
+	mxs_dma_free_desc(host->dma_desc);
+	mxs_dma_release(host->dmach, host->dev);
+}
+
+/* Probe peripheral for connected cards */
+static int __init mxs_mmc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mxs_mmc_platform_data *mmc_data;
+	struct mxs_mmc_host *host;
+	struct mmc_host *mmc;
+	struct resource *r;
+	int err = 0;
+	unsigned int ssp_ver_major;
+
+	mmc_data = dev->platform_data;
+	if (mmc_data == NULL) {
+		err = -EINVAL;
+		dev_err(dev, "Missing platform data\n");
+		goto out;
+	}
+
+	/* Allocate main MMC host structure */
+	mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), dev);
+	if (!mmc) {
+		dev_err(dev, "Unable to allocate MMC host\n");
+		err = -ENOMEM;
+		goto out;
+	}
+	host = mmc_priv(mmc);
+
+	host->read_uA = mmc_data->read_uA;
+	host->write_uA = mmc_data->write_uA;
+	if (mmc_data->power_mmc != NULL)
+		host->regulator = regulator_get(NULL, mmc_data->power_mmc);
+	if (host->regulator && !IS_ERR(host->regulator))
+		regulator_set_mode(host->regulator, REGULATOR_MODE_NORMAL);
+	else
+		host->regulator = NULL;
+
+	/* get resources: */
+
+	/*
+	 *  1. io memory
+	 */
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n");
+		err = -ENXIO;
+		goto out_res;
+	}
+	host->ssp_base = IO_ADDRESS(r->start);
+
+	/*
+	 *  2. DMA channel
+	 */
+	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_DMA\n");
+		err = -ENXIO;
+		goto out_res;
+	}
+	host->dmach = r->start;
+
+	/*
+	 * 3. two IRQs
+	 */
+	host->dmairq = platform_get_irq(pdev, 0);
+	if (host->dmairq < 0) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/0\n");
+		err = host->dmairq;
+		goto out_res;
+	}
+
+	host->errirq = platform_get_irq(pdev, 1);
+	if (host->errirq < 0) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/1\n");
+		err = host->errirq;
+		goto out_res;
+	}
+
+	/* Set up MMC pins */
+	if (mmc_data->hw_init) {
+		err = mmc_data->hw_init();
+		if (err) {
+			dev_err(dev, "MMC HW configuration failed\n");
+			goto out_res;
+		}
+	}
+
+	host->mmc = mmc;
+	host->dev = dev;
+
+	host->sdio_irq_en = 0;
+
+	/* Set minimal clock rate */
+	host->clk = clk_get(dev, mmc_data->clock_mmc);
+	if (IS_ERR(host->clk)) {
+		err = PTR_ERR(host->clk);
+		dev_err(dev, "Clocks initialization failed\n");
+		goto out_clk;
+	}
+
+	clk_enable(host->clk);
+	mxs_set_sclk_speed(host, mmc_data->min_clk);
+
+	/* Reset MMC block */
+	mxs_mmc_reset(host);
+
+	/* Enable DMA */
+	err = mxs_mmc_dma_init(host, 0);
+	if (err) {
+		dev_err(dev, "DMA init failed\n");
+		goto out_dma;
+	}
+
+	/* Set up interrupt handlers */
+	err = mxs_mmc_irq_init(host);
+	if (err) {
+		dev_err(dev, "IRQ initialization failed\n");
+		goto out_irq;
+	}
+
+	/* Get current card status for further cnanges tracking */
+	host->present = mxs_mmc_is_plugged(host);
+
+	/* Add a card detection polling timer */
+	init_timer(&host->timer);
+	host->timer.function = mxs_mmc_detect_poll;
+	host->timer.data = (unsigned long)host;
+	host->timer.expires = jiffies + MXS_MMC_DETECT_TIMEOUT;
+	add_timer(&host->timer);
+
+	mmc->ops = &mxs_mmc_ops;
+	mmc->f_min = mmc_data->min_clk;
+	mmc->f_max = mmc_data->max_clk;
+	mmc->caps = mmc_data->caps;
+	mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+	mmc->caps |= MMC_CAP_SDIO_IRQ;
+
+	/* Maximum block count requests. */
+	mmc->max_blk_size = 512;
+	ssp_ver_major = __raw_readl(host->ssp_base + HW_SSP_VERSION) >> 24;
+	dev_dbg(host->dev, "ssp ver major is 0x%x\n", ssp_ver_major);
+	if (ssp_ver_major > 3) {
+		mmc->max_blk_count = SSP_BUFFER_SIZE / 512;
+		mmc->max_hw_segs = SSP_BUFFER_SIZE / 512;
+		mmc->max_phys_segs = SSP_BUFFER_SIZE / 512;
+		mmc->max_req_size = SSP_BUFFER_SIZE;
+		mmc->max_seg_size = SSP_BUFFER_SIZE;
+	} else {
+		mmc->max_blk_count = SSP_BUFFER_SIZE / 512 - 1;
+		mmc->max_hw_segs = SSP_BUFFER_SIZE / 512 - 1;
+		mmc->max_phys_segs = SSP_BUFFER_SIZE / 512 - 1;
+		mmc->max_req_size = SSP_BUFFER_SIZE - 512;
+		mmc->max_seg_size = SSP_BUFFER_SIZE - 512;
+	}
+
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	platform_set_drvdata(pdev, mmc);
+
+	spin_lock_init(&host->lock);
+
+	err = mmc_add_host(mmc);
+	if (err) {
+		dev_err(dev, "Oh God. mmc_add_host failed\n");
+		goto out_all;
+	}
+
+	dev_info(&pdev->dev, "%s: MXS SSP MMC DMAIRQ %d ERRIRQ %d \n",
+			mmc_hostname(mmc), host->dmairq, host->errirq);
+
+	return err;
+
+out_all:
+
+out_irq:
+	mxs_mmc_dma_release(host);
+out_dma:
+	clk_disable(host->clk);
+out_clk:
+	if (mmc_data->hw_release)
+		mmc_data->hw_release();
+out_res:
+	mmc_free_host(mmc);
+out:
+	return err;
+}
+
+static int __exit mxs_mmc_remove(struct platform_device *pdev)
+{
+	struct mxs_mmc_host *host;
+	struct mxs_mmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+
+	dev_info(&pdev->dev, "Removing\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	platform_set_drvdata(pdev, NULL);
+
+	host = mmc_priv(mmc);
+	mmc_remove_host(mmc);
+
+	/* Disable SSP clock */
+	clk_disable(host->clk);
+	clk_put(host->clk);
+
+	/* Release IRQs */
+	mxs_mmc_irq_release(host);
+
+	/* Delete card detection timer */
+	del_timer(&host->timer);
+
+	/* Release DMA */
+	mxs_mmc_dma_release(host);
+	if (host->regulator)
+		regulator_put(host->regulator);
+
+	mmc_free_host(mmc);
+
+	if (mmc_data->hw_release)
+		mmc_data->hw_release();
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_mmc_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+	struct mxs_mmc_host *host;
+	struct mxs_mmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+	int ret = 0;
+
+	dev_dbg(&pdev->dev, "Suspending\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	host = mmc_priv(mmc);
+
+	ret = mmc_suspend_host(mmc, state);
+	if (!ret) {
+		if (mmc_data && mmc_data->hw_release)
+			mmc_data->hw_release();
+		clk_disable(host->clk);
+	}
+	return ret;
+}
+
+static int mxs_mmc_resume(struct platform_device *pdev)
+{
+	struct mxs_mmc_host *host;
+	struct mxs_mmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+
+	dev_dbg(&pdev->dev, "Resuming\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	host = mmc_priv(mmc);
+
+	clk_enable(host->clk);
+
+	if (mmc_data->hw_init)
+		mmc_data->hw_init();
+	mxs_mmc_reset(host);
+	mxs_mmc_dma_init(host, 1);
+
+	return mmc_resume_host(mmc);
+}
+#else
+#define mxs_mmc_suspend	NULL
+#define mxs_mmc_resume	NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver mxs_mmc_driver = {
+	.probe = mxs_mmc_probe,
+	.remove = __exit_p(mxs_mmc_remove),
+	.suspend = mxs_mmc_suspend,
+	.resume = mxs_mmc_resume,
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init mxs_mmc_init(void)
+{
+	int ret = 0;
+
+	printk(KERN_INFO DRIVER_NAME
+	       ": MXS SSP Controller MMC Interface driver\n");
+	ret = platform_driver_register(&mxs_mmc_driver);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static void __exit mxs_mmc_exit(void)
+{
+	platform_driver_unregister(&mxs_mmc_driver);
+}
+
+module_init(mxs_mmc_init);
+module_exit(mxs_mmc_exit);
+
+MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/stmp3xxx_mmc.c b/drivers/mmc/host/stmp3xxx_mmc.c
new file mode 100644
index 000000000000..0caa43dfb79f
--- /dev/null
+++ b/drivers/mmc/host/stmp3xxx_mmc.c
@@ -0,0 +1,1095 @@
+/*
+ * Copyright (C) 2007 SigmaTel, Inc., Ioannis Kappas <ikappas@sigmatel.com>
+ *
+ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
+ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/highmem.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/mmc/host.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/regs-apbh.h>
+#include <mach/regs-ssp.h>
+#include <mach/regs-clkctrl.h>
+#include <mach/stmp3xxx.h>
+#include <mach/mmc.h>
+#include <mach/platform.h>
+
+#define DRIVER_NAME	"stmp3xxx-mmc"
+
+#define CLOCKRATE_MIN 400000
+#define CLOCKRATE_MAX 48000000
+
+/*
+ * Card detect polling timeout
+ */
+#define STMP37XX_MMC_DETECT_TIMEOUT		(HZ/2)
+
+/* Max value supported for XFER_COUNT */
+#define SSP_BUFFER_SIZE		(65536 - 512)
+
+struct stmp3xxx_mmc_host {
+	struct device *dev;
+	struct mmc_host *mmc;
+
+	struct clk *clk;
+	unsigned int clkrt;
+
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+
+	/* Whether the card is capable of 4-bit data */
+	int bus_width_4:1;
+
+	/* Whether SD card is present */
+	unsigned present:1;
+
+	/* Polling timer */
+	struct timer_list timer;
+
+	/* SSP interface which MMC/SD card slot is attached to */
+	void __iomem *ssp_base;
+
+	/* DMA channel used for this host */
+	unsigned int dmach;
+
+	/* IRQs */
+	int dmairq, errirq;
+
+	/* DMA descriptor to transfer data over SSP interface */
+	struct stmp3xxx_dma_descriptor dma_desc;
+
+	/* DMA buffer */
+	dma_addr_t dma_buf_phys;
+	char *dma_buf;
+
+	struct completion dma_done;
+	/* status on last interrupt */
+	u32 status;
+	int read_uA, write_uA;
+	struct regulator *regulator;
+};
+
+/* Return read only state of card */
+static int stmp3xxx_mmc_get_ro(struct mmc_host *mmc)
+{
+	struct stmp3xxx_mmc_host *host = mmc_priv(mmc);
+	struct stmp3xxxmmc_platform_data *pdata = host->dev->platform_data;
+
+	if (pdata && pdata->get_wp)
+		return pdata->get_wp();
+
+	return 0;
+}
+
+/* Detect if card is plugged */
+static inline int stmp3xxx_mmc_is_plugged(struct stmp3xxx_mmc_host *host)
+{
+	u32 status = __raw_readl(host->ssp_base + HW_SSP_STATUS);
+	return !(status & BM_SSP_STATUS_CARD_DETECT);
+}
+
+/* Card detection polling function */
+static void stmp3xxx_mmc_detect_poll(unsigned long arg)
+{
+	struct stmp3xxx_mmc_host *host = (struct stmp3xxx_mmc_host *)arg;
+	int card_status;
+
+	card_status = stmp3xxx_mmc_is_plugged(host);
+	if (card_status != host->present) {
+		host->present = card_status;
+		mmc_detect_change(host->mmc, 0);
+	}
+
+	mod_timer(&host->timer, jiffies + STMP37XX_MMC_DETECT_TIMEOUT);
+}
+
+#define STMP3XXX_MMC_IRQ_BITS  (BM_SSP_CTRL1_SDIO_IRQ		| \
+				BM_SSP_CTRL1_RESP_ERR_IRQ	| \
+				BM_SSP_CTRL1_RESP_TIMEOUT_IRQ	| \
+				BM_SSP_CTRL1_DATA_TIMEOUT_IRQ	| \
+				BM_SSP_CTRL1_DATA_CRC_IRQ	| \
+				BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ	| \
+				BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   | \
+				BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
+
+/* SSP DMA interrupt handler */
+static irqreturn_t mmc_irq_handler(int irq, void *dev_id)
+{
+	struct stmp3xxx_mmc_host *host = dev_id;
+	u32 c1;
+
+	c1 = __raw_readl(host->ssp_base + HW_SSP_CTRL1);
+	__raw_writel(c1 & STMP3XXX_MMC_IRQ_BITS,
+			host->ssp_base + HW_SSP_CTRL1_CLR);
+	if (irq == host->dmairq)
+		stmp3xxx_dma_clear_interrupt(host->dmach);
+	host->status =
+	    __raw_readl(host->ssp_base + HW_SSP_STATUS);
+
+	if (host->cmd)		/* else it is a bogus interrupt */
+		complete(&host->dma_done);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Check for MMC command errors
+ * Returns error code or zerro if no errors
+ */
+static inline int stmp3xxx_mmc_cmd_error(u32 status)
+{
+	int err = 0;
+
+	if (status & BM_SSP_STATUS_TIMEOUT)
+		err = -ETIMEDOUT;
+	else if (status & BM_SSP_STATUS_RESP_TIMEOUT)
+		err = -ETIMEDOUT;
+	else if (status & BM_SSP_STATUS_RESP_CRC_ERR)
+		err = -EILSEQ;
+	else if (status & BM_SSP_STATUS_RESP_ERR)
+		err = -EIO;
+
+	return err;
+}
+
+/* Send the BC command to the device */
+static void stmp3xxx_mmc_bc(struct stmp3xxx_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct stmp3xxx_dma_descriptor *dma_desc = &host->dma_desc;
+
+	dma_desc->command->cmd = BM_APBH_CHn_CMD_WAIT4ENDCMD | BM_APBH_CHn_CMD_SEMAPHORE | BM_APBH_CHn_CMD_IRQONCMPLT | BF(0, APBH_CHn_CMD_XFER_COUNT) | BF(3, APBH_CHn_CMD_CMDWORDS) | BF(0, APBH_CHn_CMD_COMMAND);	/* NO_DMA_XFER */
+
+	dma_desc->command->pio_words[0] = BM_SSP_CTRL0_ENABLE |
+	    BM_SSP_CTRL0_IGNORE_CRC;
+	dma_desc->command->pio_words[1] = BF(cmd->opcode, SSP_CMD0_CMD) |
+	    BM_SSP_CMD0_APPEND_8CYC;
+	dma_desc->command->pio_words[2] = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	init_completion(&host->dma_done);
+	stmp3xxx_dma_reset_channel(host->dmach);
+	stmp3xxx_dma_go(host->dmach, dma_desc, 1);
+	wait_for_completion(&host->dma_done);
+
+	cmd->error = stmp3xxx_mmc_cmd_error(host->status);
+
+	if (stmp3xxx_dma_running(host->dmach))
+		dev_dbg(host->dev, "DMA command not finished\n");
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		stmp3xxx_dma_reset_channel(host->dmach);
+	}
+}
+
+/* Send the ac command to the device */
+static void stmp3xxx_mmc_ac(struct stmp3xxx_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct stmp3xxx_dma_descriptor *dma_desc = &host->dma_desc;
+	u32 ignore_crc, resp, long_resp;
+	u32 ssp_ctrl0;
+	u32 ssp_cmd0;
+	u32 ssp_cmd1;
+
+	ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+	    0 : BM_SSP_CTRL0_IGNORE_CRC;
+	resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+	    BM_SSP_CTRL0_GET_RESP : 0;
+	long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+	    BM_SSP_CTRL0_LONG_RESP : 0;
+
+	dma_desc->command->cmd =
+	    BM_APBH_CHn_CMD_WAIT4ENDCMD |
+	    BM_APBH_CHn_CMD_SEMAPHORE |
+	    BM_APBH_CHn_CMD_IRQONCMPLT |
+	    BF(0, APBH_CHn_CMD_XFER_COUNT) |
+	    BF(3, APBH_CHn_CMD_CMDWORDS) | BF(0, APBH_CHn_CMD_COMMAND);
+
+	ssp_ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | long_resp | resp;
+	ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD);
+	ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	dma_desc->command->pio_words[0] = ssp_ctrl0;
+	dma_desc->command->pio_words[1] = ssp_cmd0;
+	dma_desc->command->pio_words[2] = ssp_cmd1;
+
+	stmp3xxx_dma_reset_channel(host->dmach);
+	init_completion(&host->dma_done);
+	stmp3xxx_dma_go(host->dmach, dma_desc, 1);
+	wait_for_completion(&host->dma_done);
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_NONE:
+		while (__raw_readl(host->ssp_base + HW_SSP_CTRL0)
+		       & BM_SSP_CTRL0_RUN)
+			continue;
+		break;
+	case MMC_RSP_R1:
+	case MMC_RSP_R1B:
+	case MMC_RSP_R3:
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		break;
+	case MMC_RSP_R2:
+		cmd->resp[3] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		cmd->resp[2] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP1);
+		cmd->resp[1] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP2);
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP3);
+		break;
+	default:
+		dev_warn(host->dev, "Unsupported response type 0x%x\n",
+			 mmc_resp_type(cmd));
+		BUG();
+		break;
+	}
+
+	cmd->error = stmp3xxx_mmc_cmd_error(host->status);
+
+	if (stmp3xxx_dma_running(host->dmach))
+		dev_dbg(host->dev, "DMA command not finished\n");
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		stmp3xxx_dma_reset_channel(host->dmach);
+	}
+}
+
+/* Copy data between sg list and dma buffer */
+static unsigned int stmp3xxx_sg_dma_copy(struct stmp3xxx_mmc_host *host,
+					 unsigned int size, int to_dma)
+{
+	struct mmc_data *data = host->cmd->data;
+	unsigned int copy_size, bytes_copied = 0;
+	struct scatterlist *sg;
+	char *dmabuf = host->dma_buf;
+	char *sgbuf;
+	int len, i;
+
+	sg = data->sg;
+	len = data->sg_len;
+
+	/*
+	 * Just loop through all entries. Size might not
+	 * be the entire list though so make sure that
+	 * we do not transfer too much.
+	 */
+	for (i = 0; i < len; i++) {
+		sgbuf = kmap_atomic(sg_page(&sg[i]), KM_BIO_SRC_IRQ) +
+		    sg[i].offset;
+		copy_size = size < sg[i].length ? size : sg[i].length;
+		if (to_dma)
+			memcpy(dmabuf, sgbuf, copy_size);
+		else
+			memcpy(sgbuf, dmabuf, copy_size);
+		kunmap_atomic(sgbuf, KM_BIO_SRC_IRQ);
+
+		dmabuf += sg[i].length;
+
+		bytes_copied += copy_size;
+		size -= copy_size;
+
+		if (size == 0)
+			break;
+	}
+
+	return bytes_copied;
+}
+
+/* Convert ns to tick count according to the current sclk speed */
+static unsigned short stmp3xxx_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
+{
+	const unsigned int ssp_timeout_mul = 4096;
+	/*
+	 * Calculate ticks in ms since ns are large numbers
+	 * and might overflow
+	 */
+	const unsigned int clock_per_ms = clock_rate / 1000;
+	const unsigned int ms = ns / 1000;
+	const unsigned int ticks = ms * clock_per_ms;
+	const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
+
+	BUG_ON(ssp_ticks == 0);
+	return ssp_ticks;
+}
+
+static void __init_reg(struct device *dev, struct regulator **pp_reg)
+{
+	struct regulator *reg = *pp_reg;
+
+	if (!reg) {
+		reg = regulator_get(NULL, "mmc_ssp-1");
+		if (reg && !IS_ERR(reg))
+			regulator_set_mode(reg, REGULATOR_MODE_NORMAL);
+		else
+			reg = NULL;
+		*pp_reg = reg;
+	}
+}
+
+/* Send adtc command to the card */
+static void stmp3xxx_mmc_adtc(struct stmp3xxx_mmc_host *host)
+{
+	struct mmc_command *cmd = host->cmd;
+	struct stmp3xxx_dma_descriptor *dma_desc = &host->dma_desc;
+	int ignore_crc, resp, long_resp;
+	int is_reading = 0;
+	unsigned int copy_size;
+
+	u32 ssp_ctrl0;
+	u32 ssp_cmd0;
+	u32 ssp_cmd1;
+	u32 timeout;
+	u32 val;
+
+	u32 data_size = cmd->data->blksz * cmd->data->blocks;
+	u32 log2_block_size;
+
+	ignore_crc = mmc_resp_type(cmd) & MMC_RSP_CRC ? 0 : 1;
+	resp = mmc_resp_type(cmd) & MMC_RSP_PRESENT ? 1 : 0;
+	long_resp = mmc_resp_type(cmd) & MMC_RSP_136 ? 1 : 0;
+
+	dev_dbg(host->dev, "ADTC command:\n"
+		"response: %d, ignore crc: %d\n"
+		"data list: %u, blocksz: %u, blocks: %u, timeout: %uns %uclks, "
+		"flags: 0x%x\n", resp, ignore_crc, cmd->data->sg_len,
+		cmd->data->blksz, cmd->data->blocks, cmd->data->timeout_ns,
+		cmd->data->timeout_clks, cmd->data->flags);
+
+	if (cmd->data->flags & MMC_DATA_WRITE) {
+		dev_dbg(host->dev, "Data Write\n");
+		copy_size = stmp3xxx_sg_dma_copy(host, data_size, 1);
+		BUG_ON(copy_size < data_size);
+		is_reading = 0;
+		if (!host->regulator)
+			__init_reg(host->dev, &host->regulator);
+		if (host->regulator)
+			regulator_set_current_limit(host->regulator,
+						    host->write_uA,
+						    host->write_uA);
+	} else if (cmd->data->flags & MMC_DATA_READ) {
+		dev_dbg(host->dev, "Data Read\n");
+		is_reading = 1;
+		if (!host->regulator)
+			__init_reg(host->dev, &host->regulator);
+		if (host->regulator)
+			regulator_set_current_limit(host->regulator,
+						    host->read_uA,
+						    host->read_uA);
+	} else {
+		dev_warn(host->dev, "Unsuspported data mode, 0x%x\n",
+			 cmd->data->flags);
+		BUG();
+	}
+
+	BUG_ON(cmd->data->flags & MMC_DATA_STREAM);
+	BUG_ON((data_size % 8) > 0);
+
+	dma_desc->command->cmd =
+	    BM_APBH_CHn_CMD_WAIT4ENDCMD |
+	    BM_APBH_CHn_CMD_SEMAPHORE |
+	    BM_APBH_CHn_CMD_IRQONCMPLT |
+	    BF(data_size, APBH_CHn_CMD_XFER_COUNT) |
+	    BF(3, APBH_CHn_CMD_CMDWORDS);
+
+	/* when is_reading is set, DMA controller performs WRITE operation. */
+	dma_desc->command->cmd |=
+	    BF(is_reading ? BV_APBH_CHn_CMD_COMMAND__DMA_WRITE :
+			     BV_APBH_CHn_CMD_COMMAND__DMA_READ,
+			     APBH_CHn_CMD_COMMAND);
+	ssp_ctrl0 =
+	    (ignore_crc ? BM_SSP_CTRL0_IGNORE_CRC : 0) | (resp ?
+							  BM_SSP_CTRL0_GET_RESP
+							  : 0) | (long_resp ?
+								  BM_SSP_CTRL0_LONG_RESP
+								  : 0) |
+	    (is_reading ? BM_SSP_CTRL0_READ : 0) | BM_SSP_CTRL0_DATA_XFER |
+	    BM_SSP_CTRL0_WAIT_FOR_IRQ | BM_SSP_CTRL0_ENABLE | BF(data_size,
+								 SSP_CTRL0_XFER_COUNT)
+	    | BF(host->bus_width_4 ? BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT :
+				     BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT,
+				     SSP_CTRL0_BUS_WIDTH);
+
+	/*
+	 * We need to set the hardware register to the logarithm to base 2 of
+	 * the block size.
+	 */
+	log2_block_size = ilog2(cmd->data->blksz);
+
+	ssp_cmd0 =
+	    BF(log2_block_size, SSP_CMD0_BLOCK_SIZE) |
+	    BF(cmd->opcode, SSP_CMD0_CMD) |
+	    BF(cmd->data->blocks - 1, SSP_CMD0_BLOCK_COUNT);
+
+	if (cmd->opcode == 12)
+		ssp_cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
+
+	ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG);
+
+	dma_desc->command->pio_words[0] = ssp_ctrl0;
+	dma_desc->command->pio_words[1] = ssp_cmd0;
+	dma_desc->command->pio_words[2] = ssp_cmd1;
+
+	/* Set the timeout count */
+	timeout = stmp3xxx_ns_to_ssp_ticks(host->clkrt, cmd->data->timeout_ns);
+	val = __raw_readl(host->ssp_base + HW_SSP_TIMING);
+	val &= ~(BM_SSP_TIMING_TIMEOUT);
+	val |= BF(timeout, SSP_TIMING_TIMEOUT);
+	__raw_writel(val, host->ssp_base + HW_SSP_TIMING);
+
+	init_completion(&host->dma_done);
+	stmp3xxx_dma_reset_channel(host->dmach);
+	stmp3xxx_dma_go(host->dmach, dma_desc, 1);
+	wait_for_completion(&host->dma_done);
+	if (host->regulator)
+		regulator_set_current_limit(host->regulator, 0, 0);
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_NONE:
+		break;
+	case MMC_RSP_R1:
+	case MMC_RSP_R3:
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		break;
+	case MMC_RSP_R2:
+		cmd->resp[3] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP0);
+		cmd->resp[2] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP1);
+		cmd->resp[1] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP2);
+		cmd->resp[0] =
+		    __raw_readl(host->ssp_base + HW_SSP_SDRESP3);
+		break;
+	default:
+		dev_warn(host->dev, "Unsupported response type 0x%x\n",
+			 mmc_resp_type(cmd));
+		BUG();
+		break;
+	}
+
+	cmd->error = stmp3xxx_mmc_cmd_error(host->status);
+
+	if (stmp3xxx_dma_running(host->dmach))
+		dev_dbg(host->dev, "DMA command not finished\n");
+
+	if (cmd->error) {
+		dev_dbg(host->dev, "Command error 0x%x\n", cmd->error);
+		stmp3xxx_dma_reset_channel(host->dmach);
+	} else {
+		if (is_reading)
+			cmd->data->bytes_xfered =
+			    stmp3xxx_sg_dma_copy(host, data_size, 0);
+		else
+			cmd->data->bytes_xfered = data_size;
+
+		dev_dbg(host->dev, "Transferred %u bytes\n",
+			cmd->data->bytes_xfered);
+	}
+}
+
+/* Begin sedning a command to the card */
+static void stmp3xxx_mmc_start_cmd(struct stmp3xxx_mmc_host *host,
+				   struct mmc_command *cmd)
+{
+	dev_dbg(host->dev, "MMC command:\n"
+		"type: 0x%x opcode: %u, arg: %u, flags 0x%x retries: %u\n",
+		mmc_cmd_type(cmd), cmd->opcode, cmd->arg, cmd->flags,
+		cmd->retries);
+
+	host->cmd = cmd;
+
+	switch (mmc_cmd_type(cmd)) {
+	case MMC_CMD_BC:
+		stmp3xxx_mmc_bc(host);
+		break;
+	case MMC_CMD_BCR:
+		stmp3xxx_mmc_ac(host);
+		break;
+	case MMC_CMD_AC:
+		stmp3xxx_mmc_ac(host);
+		break;
+	case MMC_CMD_ADTC:
+		stmp3xxx_mmc_adtc(host);
+		break;
+	default:
+		dev_warn(host->dev, "Unknown MMC command\n");
+		BUG();
+		break;
+	}
+
+	dev_dbg(host->dev, "response: %u %u %u %u errors: %u\n",
+		cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
+		cmd->error);
+}
+
+/* Handle MMC request */
+static void stmp3xxx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct stmp3xxx_mmc_host *host = mmc_priv(mmc);
+
+	dev_dbg(host->dev, "MMC request\n");
+
+	host->mrq = mrq;
+
+	stmp3xxx_mmc_start_cmd(host, mrq->cmd);
+
+	if (mrq->data && mrq->data->stop) {
+		dev_dbg(host->dev, "Stop opcode is %u\n",
+			mrq->data->stop->opcode);
+		stmp3xxx_mmc_start_cmd(host, mrq->data->stop);
+	}
+
+	host->mrq = NULL;
+	mmc_request_done(mmc, mrq);
+}
+
+/*
+ * Change divisors to reflect the rate of 'hz'. Note that we should not
+ * play with clock rate, because the same source is used to clock both
+ * SSP ports.
+ */
+static void
+stmp3xxx_set_sclk_speed(struct stmp3xxx_mmc_host *host, unsigned int hz)
+{
+	unsigned long ssp;
+	u32 div1, div2;
+	u32 val;
+	struct stmp3xxxmmc_platform_data *pdata = host->dev->platform_data;
+
+	if (get_evk_board_version() == 1) {
+		/*EVK Ver1 max clock is 12M */
+		if (hz > 12000000)
+			hz = 12000000;
+	}
+
+	if (pdata && pdata->setclock) {
+		/*
+		   if the SSP is buggy and platform provides callback...
+		   well, let it be.
+		 */
+		host->clkrt = pdata->setclock(hz);
+		return;
+	}
+
+	/*
+	   ...but the RightIdea(tm) is to set divisors to match
+	   the requested clock.
+	 */
+	hz /= 1000;
+
+	ssp = clk_get_rate(host->clk);
+
+	for (div1 = 2; div1 < 254; div1 += 2) {
+		div2 = ssp / hz / div1;
+		if (div2 < 0x100)
+			break;
+	}
+	if (div1 >= 254) {
+		dev_err(host->dev, "Cannot set clock to %dkHz\n", hz);
+		return;
+	}
+
+	dev_dbg(host->dev, "Setting clock rate to %ld kHz [%x+%x] "
+		"(requested %d), source %ldk\n",
+		ssp / div1 / div2, div1, div2, hz, ssp);
+
+	val = __raw_readl(host->ssp_base + HW_SSP_TIMING);
+	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
+	val |= BF(div1, SSP_TIMING_CLOCK_DIVIDE) |
+		      BF(div2 - 1, SSP_TIMING_CLOCK_RATE);
+	__raw_writel(val, host->ssp_base + HW_SSP_TIMING);
+
+	host->clkrt = ssp / div1 / div2 * 1000;
+}
+
+/* Configure card */
+static void stmp3xxx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct stmp3xxx_mmc_host *host = mmc_priv(mmc);
+	struct stmp3xxxmmc_platform_data *pdata;
+
+	dev_dbg(host->dev, "MMC set ios:\n"
+		"Clock %u, vdd %u, bus_mode %u, chip_select %u, "
+		"power mode %u, bus_width %u\n", ios->clock, ios->vdd,
+		ios->bus_mode, ios->chip_select, ios->power_mode,
+		ios->bus_width);
+
+	pdata = host->dev->platform_data;
+
+	if (pdata->cmd_pullup) {
+		if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
+			pdata->cmd_pullup(0);
+		else
+			pdata->cmd_pullup(1);
+	} else
+		dev_warn(host->dev,
+			 "Platform does not support CMD pin pullup control\n");
+
+	if (ios->bus_width == MMC_BUS_WIDTH_4)
+		host->bus_width_4 = 1;
+	else
+		host->bus_width_4 = 0;
+
+	if (ios->clock > 0)
+		stmp3xxx_set_sclk_speed(host, ios->clock);
+}
+
+static const struct mmc_host_ops stmp3xxx_mmc_ops = {
+	.request = stmp3xxx_mmc_request,
+	.get_ro = stmp3xxx_mmc_get_ro,
+	.set_ios = stmp3xxx_mmc_set_ios,
+};
+
+/*
+ * STMP37XX MMC/SD driver initialization
+ */
+
+/* Reset ssp peripheral to default values */
+static void stmp3xxx_mmc_reset(struct stmp3xxx_mmc_host *host)
+{
+	u32 ssp_ctrl0;
+	u32 ssp_ctrl1;
+
+	stmp3xxx_reset_block(host->ssp_base, 0);
+
+	/* Configure SSP Control Register 0 */
+	ssp_ctrl0 =
+	    BM_SSP_CTRL0_IGNORE_CRC |
+	    BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, SSP_CTRL0_BUS_WIDTH);
+
+	/* Configure SSP Control Register 1 */
+	ssp_ctrl1 =
+	    BM_SSP_CTRL1_DMA_ENABLE |
+	    BM_SSP_CTRL1_POLARITY |
+	    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
+	    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+	    BM_SSP_CTRL1_RESP_ERR_IRQ_EN |
+	    BF(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS, SSP_CTRL1_WORD_LENGTH) |
+	    BF(BV_SSP_CTRL1_SSP_MODE__SD_MMC, SSP_CTRL1_SSP_MODE);
+
+	__raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) |
+		     BF(2, SSP_TIMING_CLOCK_DIVIDE) |
+		     BF(0, SSP_TIMING_CLOCK_RATE),
+		     host->ssp_base + HW_SSP_TIMING);
+
+	/* Write the SSP Control Register 0 and 1 values out to the interface */
+	__raw_writel(ssp_ctrl0, host->ssp_base + HW_SSP_CTRL0);
+	__raw_writel(ssp_ctrl1, host->ssp_base + HW_SSP_CTRL1);
+}
+
+static void stmp3xxx_mmc_irq_release(struct stmp3xxx_mmc_host *host)
+{
+	free_irq(host->dmairq, host);
+	free_irq(host->errirq, host);
+}
+
+static int __init stmp3xxx_mmc_irq_init(struct stmp3xxx_mmc_host *host)
+{
+	int ret;
+
+	ret = request_irq(host->dmairq, mmc_irq_handler, 0,
+			  DRIVER_NAME " dma", host);
+	if (ret) {
+		dev_err(host->dev, "Unable to set up DMA irq handler\n");
+		goto out0;
+	}
+
+	ret = request_irq(host->errirq, mmc_irq_handler, IRQF_SHARED,
+			  DRIVER_NAME " error", host);
+	if (ret) {
+		dev_err(host->dev, "Unable to set up SSP error irq handler\n");
+		goto out1;
+	}
+	return 0;
+
+out1:
+	free_irq(host->dmairq, host);
+out0:
+	return ret;
+}
+
+/* Allocate and initialise the DMA chains */
+static int stmp3xxx_mmc_dma_init(struct stmp3xxx_mmc_host *host, int reset)
+{
+	int ret;
+
+	if (!reset) {
+		/* Allocate DMA channel */
+		ret = stmp3xxx_dma_request(host->dmach,
+					   host->dev, "STMP37XX MMC/SD");
+		if (ret) {
+			dev_err(host->dev, "Unable to request DMA channel\n");
+			return ret;
+		}
+
+		host->dma_buf = dma_alloc_coherent(host->dev, SSP_BUFFER_SIZE,
+						   &host->dma_buf_phys,
+						   GFP_DMA);
+		if (host->dma_buf == NULL) {
+			dev_err(host->dev, "Unable to allocate DMA memory\n");
+			ret = -ENOMEM;
+			goto out_mem;
+		}
+
+		ret = stmp3xxx_dma_allocate_command(host->dmach,
+						    &host->dma_desc);
+		if (ret) {
+			dev_err(host->dev,
+				"Unable to allocate DMA descriptor\n");
+			goto out_cmd;
+		}
+
+		host->dma_desc.command->next = (u32) host->dma_desc.handle;
+		host->dma_desc.command->buf_ptr = (u32) host->dma_buf_phys;
+		host->dma_desc.virtual_buf_ptr = host->dma_buf;
+	}
+
+	/* Reset DMA channel */
+	stmp3xxx_dma_reset_channel(host->dmach);
+
+	/* Enable DMA interrupt */
+	stmp3xxx_dma_clear_interrupt(host->dmach);
+	stmp3xxx_dma_enable_interrupt(host->dmach);
+
+	return 0;
+
+out_cmd:
+	dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf,
+			  host->dma_buf_phys);
+out_mem:
+	stmp3xxx_dma_release(host->dmach);
+
+	return ret;
+}
+
+static void stmp3xxx_mmc_dma_release(struct stmp3xxx_mmc_host *host)
+{
+	stmp3xxx_dma_reset_channel(host->dmach);
+
+	dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf,
+			  host->dma_buf_phys);
+
+	stmp3xxx_dma_free_command(host->dmach, &host->dma_desc);
+	stmp3xxx_dma_release(host->dmach);
+}
+
+/* Probe peripheral for connected cards */
+static int __init stmp3xxx_mmc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct stmp3xxxmmc_platform_data *mmc_data;
+	struct stmp3xxx_mmc_host *host;
+	struct mmc_host *mmc;
+	struct resource *r;
+	int err = 0;
+
+	mmc_data = dev->platform_data;
+	if (mmc_data == NULL) {
+		err = -EINVAL;
+		dev_err(dev, "Missing platform data\n");
+		goto out;
+	}
+
+	/* Allocate main MMC host structure */
+	mmc = mmc_alloc_host(sizeof(struct stmp3xxx_mmc_host), dev);
+	if (!mmc) {
+		dev_err(dev, "Unable to allocate MMC host\n");
+		err = -ENOMEM;
+		goto out;
+	}
+	host = mmc_priv(mmc);
+
+	host->read_uA = mmc_data->read_uA;
+	host->write_uA = mmc_data->write_uA;
+	host->regulator = regulator_get(NULL, "mmc_ssp-1");
+	if (host->regulator && !IS_ERR(host->regulator))
+		regulator_set_mode(host->regulator, REGULATOR_MODE_NORMAL);
+	else
+		host->regulator = NULL;
+
+	/* get resources: */
+
+	/*
+	 *  1. io memory
+	 */
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n");
+		err = -ENXIO;
+		goto out_res;
+	}
+	host->ssp_base =
+		r->start - STMP3XXX_REGS_PHBASE + STMP3XXX_REGS_BASE;
+
+	/*
+	 *  2. DMA channel
+	 */
+	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_DMA\n");
+		err = -ENXIO;
+		goto out_res;
+	}
+	host->dmach = r->start;
+
+	/*
+	 * 3. two IRQs
+	 */
+	host->dmairq = platform_get_irq(pdev, 0);
+	if (host->dmairq < 0) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/0\n");
+		err = host->dmairq;
+		goto out_res;
+	}
+
+	host->errirq = platform_get_irq(pdev, 1);
+	if (host->errirq < 0) {
+		dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/1\n");
+		err = host->errirq;
+		goto out_res;
+	}
+
+	/* Set up MMC pins */
+	if (mmc_data->hw_init) {
+		err = mmc_data->hw_init();
+		if (err) {
+			dev_err(dev, "MMC HW configuration failed\n");
+			goto out_res;
+		}
+	}
+
+	host->mmc = mmc;
+	host->dev = dev;
+
+	/* Set minimal clock rate */
+	host->clk = clk_get(dev, "ssp");
+	if (IS_ERR(host->clk)) {
+		err = PTR_ERR(host->clk);
+		dev_err(dev, "Clocks initialization failed\n");
+		goto out_clk;
+	}
+
+	clk_enable(host->clk);
+	stmp3xxx_set_sclk_speed(host, CLOCKRATE_MIN);
+
+	/* Reset MMC block */
+	stmp3xxx_mmc_reset(host);
+
+	/* Enable DMA */
+	err = stmp3xxx_mmc_dma_init(host, 0);
+	if (err) {
+		dev_err(dev, "DMA init failed\n");
+		goto out_dma;
+	}
+
+	/* Set up interrupt handlers */
+	err = stmp3xxx_mmc_irq_init(host);
+	if (err) {
+		dev_err(dev, "IRQ initialization failed\n");
+		goto out_irq;
+	}
+
+	/* Get current card status for further cnanges tracking */
+	host->present = stmp3xxx_mmc_is_plugged(host);
+
+	/* Add a card detection polling timer */
+	init_timer(&host->timer);
+	host->timer.function = stmp3xxx_mmc_detect_poll;
+	host->timer.data = (unsigned long)host;
+	host->timer.expires = jiffies + STMP37XX_MMC_DETECT_TIMEOUT;
+	add_timer(&host->timer);
+
+	mmc->ops = &stmp3xxx_mmc_ops;
+	mmc->f_min = CLOCKRATE_MIN;
+	mmc->f_max = CLOCKRATE_MAX;
+	mmc->caps = MMC_CAP_4_BIT_DATA;
+
+	/* Maximum block count requests. */
+	mmc->max_blk_size = 512;
+	mmc->max_blk_count = SSP_BUFFER_SIZE / 512;
+	mmc->max_hw_segs = SSP_BUFFER_SIZE / 512;
+	mmc->max_phys_segs = SSP_BUFFER_SIZE / 512;
+	mmc->max_req_size = SSP_BUFFER_SIZE;
+	mmc->max_seg_size = SSP_BUFFER_SIZE;
+
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	platform_set_drvdata(pdev, mmc);
+
+	err = mmc_add_host(mmc);
+	if (err) {
+		dev_err(dev, "Oh God. mmc_add_host failed\n");
+		goto out_all;
+	}
+
+	return err;
+
+out_all:
+
+out_irq:
+	stmp3xxx_mmc_dma_release(host);
+out_dma:
+	clk_disable(host->clk);
+out_clk:
+	if (mmc_data->hw_release)
+		mmc_data->hw_release();
+out_res:
+	mmc_free_host(mmc);
+out:
+	return err;
+}
+
+static int __exit stmp3xxx_mmc_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_mmc_host *host;
+	struct stmp3xxxmmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+
+	dev_info(&pdev->dev, "Removing\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	platform_set_drvdata(pdev, NULL);
+
+	host = mmc_priv(mmc);
+	mmc_remove_host(mmc);
+
+	/* Disable SSP clock */
+	clk_disable(host->clk);
+	clk_put(host->clk);
+
+	/* Release IRQs */
+	stmp3xxx_mmc_irq_release(host);
+
+	/* Delete card detection timer */
+	del_timer(&host->timer);
+
+	/* Release DMA */
+	stmp3xxx_mmc_dma_release(host);
+	if (host->regulator)
+		regulator_put(host->regulator);
+
+	mmc_free_host(mmc);
+
+	if (mmc_data->hw_release)
+		mmc_data->hw_release();
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stmp3xxx_mmc_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+	struct stmp3xxx_mmc_host *host;
+	struct stmp3xxxmmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+	int ret = 0;
+
+	dev_dbg(&pdev->dev, "Suspending\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	host = mmc_priv(mmc);
+
+	ret = mmc_suspend_host(mmc, state);
+	if (!ret) {
+		if (mmc_data && mmc_data->hw_release)
+			mmc_data->hw_release();
+		clk_disable(host->clk);
+	}
+	return ret;
+}
+
+static int stmp3xxx_mmc_resume(struct platform_device *pdev)
+{
+	struct stmp3xxx_mmc_host *host;
+	struct stmp3xxxmmc_platform_data *mmc_data;
+	struct mmc_host *mmc;
+
+	dev_dbg(&pdev->dev, "Resuming\n");
+
+	mmc_data = pdev->dev.platform_data;
+	mmc = platform_get_drvdata(pdev);
+	host = mmc_priv(mmc);
+
+	clk_enable(host->clk);
+
+	if (mmc_data->hw_init)
+		mmc_data->hw_init();
+	stmp3xxx_mmc_reset(host);
+	stmp3xxx_mmc_dma_init(host, 1);
+
+	return mmc_resume_host(mmc);
+}
+#else
+#define stmp3xxx_mmc_suspend	NULL
+#define stmp3xxx_mmc_resume	NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver stmp3xxx_mmc_driver = {
+	.probe = stmp3xxx_mmc_probe,
+	.remove = __exit_p(stmp3xxx_mmc_remove),
+	.suspend = stmp3xxx_mmc_suspend,
+	.resume = stmp3xxx_mmc_resume,
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init stmp3xxx_mmc_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&stmp3xxx_mmc_driver);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static void __exit stmp3xxx_mmc_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_mmc_driver);
+}
+
+module_init(stmp3xxx_mmc_init);
+module_exit(stmp3xxx_mmc_exit);
+
+MODULE_DESCRIPTION("STMP37xx/378x MMC peripheral");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index b8e35a0b4d72..7e77736b83f7 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -329,4 +329,12 @@ source "drivers/mtd/lpddr/Kconfig"
 
 source "drivers/mtd/ubi/Kconfig"
 
+config MTD_UBI_BLOCK
+	tristate "Simple mtdblock-like FTL over UBI volumes"
+	depends on MTD_UBI
+	select MTD_BLKDEVS
+	default n
+	help
+	  This enables cached block access to UBI volumes
+
 endif # MTD
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 82d1e4de475b..300a66099b8d 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,3 +32,4 @@ inftl-objs		:= inftlcore.o inftlmount.o
 obj-y		+= chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
 
 obj-$(CONFIG_MTD_UBI)		+= ubi/
+obj-$(CONFIG_MTD_UBI_BLOCK)	+= ubiblock.o
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 325fab92a62c..b81b781abc1e 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -80,6 +80,14 @@ config MTD_DATAFLASH_OTP
 	  other key product data.  The second half is programmed with a
 	  unique-to-each-chip bit pattern at the factory.
 
+config MTD_MXC_DATAFLASH
+        tristate "Support for AT DataFlash via FSL SPI interface"
+        depends on SPI_MASTER && EXPERIMENTAL
+        help
+          This enables access to AT DataFlash chips, using FSL SPI.
+          Sometimes DataFlash chips are packaged inside MMC-format
+          cards; at this writing, the MMC stack won't handle those.
+
 config MTD_M25P80
 	tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
 	depends on SPI_MASTER && EXPERIMENTAL
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index 0993d5cf3923..98a95aa875c0 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_MTD_LART)		+= lart.o
 obj-$(CONFIG_MTD_BLOCK2MTD)	+= block2mtd.o
 obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
 obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
+obj-$(CONFIG_MTD_MXC_DATAFLASH)	+= mxc_dataflash.o
diff --git a/drivers/mtd/devices/mxc_dataflash.c b/drivers/mtd/devices/mxc_dataflash.c
new file mode 100644
index 000000000000..0ed701d6778c
--- /dev/null
+++ b/drivers/mtd/devices/mxc_dataflash.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * (c) 2005 MontaVista Software, Inc.
+ *
+ * This code is based on mtd_dataflash.c by adding FSL spi access.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+
+#include <linux/spi/spi.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/flash.h>
+
+/*
+ * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS	0xE8
+#define OP_READ_PAGE		0xD2
+
+/* group B requests can run even while status reports "busy" */
+#define OP_READ_STATUS		0xD7	/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER1		0xD4	/* group B */
+#define OP_READ_BUFFER2		0xD6	/* group B */
+#define OP_WRITE_BUFFER1	0x84	/* group B */
+#define OP_WRITE_BUFFER2	0x87	/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE		0x81
+#define OP_ERASE_BLOCK		0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1	0x53
+#define OP_TRANSFER_BUF2	0x55
+#define OP_MREAD_BUFFER1	0xD4
+#define OP_MREAD_BUFFER2	0xD6
+#define OP_MWERASE_BUFFER1	0x83
+#define OP_MWERASE_BUFFER2	0x86
+#define OP_MWRITE_BUFFER1	0x88	/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2	0x89	/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF1	0x82
+#define OP_PROGRAM_VIA_BUF2	0x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF1		0x60
+#define OP_COMPARE_BUF2		0x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF1	0x58
+#define OP_REWRITE_VIA_BUF2	0x59
+
+/* newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID		0x9F
+#define OP_READ_SECURITY	0x77
+#define OP_WRITE_SECURITY_REVC	0x9A
+#define OP_WRITE_SECURITY	0x9B	/* revision D */
+
+#define	SPI_FIFOSIZE		24	/* Bust size in bytes */
+#define	CMD_SIZE		4
+#define DUMY_SIZE		4
+
+struct dataflash {
+	uint8_t command[4];
+	char name[24];
+
+	unsigned partitioned:1;
+
+	unsigned short page_offset;	/* offset in flash address */
+	unsigned int page_size;	/* of bytes per page */
+
+	struct mutex lock;
+	struct spi_device *spi;
+
+	struct mtd_info mtd;
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+#define	mtd_has_partitions()	(1)
+#else
+#define	mtd_has_partitions()	(0)
+#endif
+
+/* ......................................................................... */
+
+/*
+ * This function initializes the SPI device parameters.
+ */
+static inline int spi_nor_setup(struct spi_device *spi, u8 bst_len)
+{
+	spi->bits_per_word = bst_len << 3;
+
+	return spi_setup(spi);
+}
+
+/*
+ * This function perform spi read/write transfer.
+ */
+static int spi_read_write(struct spi_device *spi, u8 * buf, u32 len)
+{
+	struct spi_message m;
+	struct spi_transfer t;
+
+	if (len > SPI_FIFOSIZE || len <= 0)
+		return -1;
+
+	spi_nor_setup(spi, len);
+
+	spi_message_init(&m);
+	memset(&t, 0, sizeof t);
+
+	t.tx_buf = buf;
+	t.rx_buf = buf;
+	t.len = ((len - 1) >> 2) + 1;
+
+	spi_message_add_tail(&t, &m);
+
+	if (spi_sync(spi, &m) != 0 || m.status != 0) {
+		printk(KERN_ERR "%s: error\n", __func__);
+		return -1;
+	}
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: len: 0x%x success\n", __func__, len);
+
+	return 0;
+
+}
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_device *spi)
+{
+	/* NOTE:  at45db321c over 25 MHz wants to write
+	 * a dummy byte after the opcode...
+	 */
+	ssize_t retval;
+
+	u16 val = OP_READ_STATUS << 8;
+
+	retval = spi_read_write(spi, (u8 *)&val, 2);
+
+	if (retval < 0)
+		return retval;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: status: 0x%x\n", __func__, val & 0xff);
+
+	return val & 0xff;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ */
+static int dataflash_waitready(struct spi_device *spi)
+{
+	int status;
+
+	for (;;) {
+		status = dataflash_status(spi);
+		if (status < 0) {
+			DEBUG(MTD_DEBUG_LEVEL1, "%s: status %d?\n",
+			      dev_name(&spi->dev), status);
+			status = 0;
+		}
+
+		if (status & (1 << 7))	/* RDY/nBSY */
+			return status;
+
+		msleep(3);
+	}
+}
+
+/* ......................................................................... */
+
+/*
+ * Erase pages of flash.
+ */
+static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct dataflash *priv = (struct dataflash *)mtd->priv;
+	struct spi_device *spi = priv->spi;
+	unsigned blocksize = priv->page_size << 3;
+	uint8_t *command;
+	uint32_t		rem;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: erase addr=0x%llx len 0x%llx\n",
+	      dev_name(&spi->dev), (long long)instr->addr,
+	      (long long)instr->len);
+
+	/* Sanity checks */
+	if (instr->addr + instr->len > mtd->size)
+		return -EINVAL;
+	div_u64_rem(instr->len, priv->page_size, &rem);
+	if (rem)
+		return -EINVAL;
+	div_u64_rem(instr->addr, priv->page_size, &rem);
+	if (rem)
+		return -EINVAL;
+
+	command = priv->command;
+
+	mutex_lock(&priv->lock);
+	while (instr->len > 0) {
+		unsigned int pageaddr;
+		int status;
+		int do_block;
+
+		/* Calculate flash page address; use block erase (for speed) if
+		 * we're at a block boundary and need to erase the whole block.
+		 */
+		pageaddr = div_u64(instr->addr, priv->page_size);
+		do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize;
+		pageaddr = pageaddr << priv->page_offset;
+
+		command[3] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
+		command[2] = (uint8_t) (pageaddr >> 16);
+		command[1] = (uint8_t) (pageaddr >> 8);
+		command[0] = 0;
+
+		DEBUG(MTD_DEBUG_LEVEL3, "ERASE %s: (%x) %x %x %x [%i]\n",
+		      do_block ? "block" : "page",
+		      command[0], command[1], command[2], command[3], pageaddr);
+
+		status = spi_read_write(spi, command, 4);
+		(void)dataflash_waitready(spi);
+
+		if (status < 0) {
+			printk(KERN_ERR "%s: erase %x, err %d\n",
+			       dev_name(&spi->dev), pageaddr, status);
+			/* REVISIT:  can retry instr->retries times; or
+			 * giveup and instr->fail_addr = instr->addr;
+			 */
+			continue;
+		}
+
+		if (do_block) {
+			instr->addr += blocksize;
+			instr->len -= blocksize;
+		} else {
+			instr->addr += priv->page_size;
+			instr->len -= priv->page_size;
+		}
+	}
+	mutex_unlock(&priv->lock);
+
+	/* Inform MTD subsystem that erase is complete */
+	instr->state = MTD_ERASE_DONE;
+	mtd_erase_callback(instr);
+
+	return 0;
+}
+
+/*
+ * Read from the DataFlash device.
+ *   from   : Start offset in flash device
+ *   len    : Amount to read
+ *   retlen : About of data actually read
+ *   buf    : Buffer containing the data
+ */
+static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+			  size_t *retlen, u_char *buf)
+{
+	struct dataflash *priv = mtd->priv;
+	struct spi_device *spi = priv->spi;
+	u32 addr;
+	int rx_len = 0, count = 0, i = 0;
+	u_char txer[SPI_FIFOSIZE];
+	u_char *s = txer;
+	u_char *d = buf;
+	int cmd_len = CMD_SIZE + DUMY_SIZE;
+	int status = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: read 0x%x..0x%x\n",
+	      dev_name(&priv->spi->dev), (unsigned)from, (unsigned)(from + len));
+
+	*retlen = 0;
+
+	/* Sanity checks */
+	if (!len)
+		return 0;
+
+	if (from + len > mtd->size)
+		return -EINVAL;
+
+	/* Calculate flash page/byte address */
+	addr = (((unsigned)from / priv->page_size) << priv->page_offset)
+	    + ((unsigned)from % priv->page_size);
+
+	mutex_unlock(&priv->lock);
+
+	while (len > 0) {
+
+		rx_len = len > (SPI_FIFOSIZE - cmd_len) ?
+		    SPI_FIFOSIZE - cmd_len : len;
+
+		txer[3] = OP_READ_CONTINUOUS;
+		txer[2] = (addr >> 16) & 0xff;
+		txer[1] = (addr >> 8) & 0xff;
+		txer[0] = addr & 0xff;
+
+		status = spi_read_write(spi, txer,
+					roundup(rx_len, 4) + cmd_len);
+		if (status) {
+			mutex_unlock(&priv->lock);
+			return status;
+		}
+
+		s = txer + cmd_len;
+
+		for (i = rx_len; i >= 0; i -= 4, s += 4) {
+			if (i < 4) {
+				if (i == 1) {
+					*d = s[3];
+				} else if (i == 2) {
+					*d++ = s[3];
+					*d++ = s[2];
+				} else if (i == 3) {
+					*d++ = s[3];
+					*d++ = s[2];
+					*d++ = s[1];
+				}
+
+				break;
+			}
+
+			*d++ = s[3];
+			*d++ = s[2];
+			*d++ = s[1];
+			*d++ = s[0];
+		}
+
+		/* updaate */
+		len -= rx_len;
+		addr += rx_len;
+		count += rx_len;
+
+		DEBUG(MTD_DEBUG_LEVEL2,
+		      "%s: left:0x%x, from:0x%08x, to:0x%p, done: 0x%x\n",
+		      __func__, len, (u32) addr, d, count);
+	}
+
+	*retlen = count;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: %d bytes read\n", __func__, count);
+
+	mutex_unlock(&priv->lock);
+
+	return status;
+}
+
+/*
+ * Write to the DataFlash device.
+ *   to     : Start offset in flash device
+ *   len    : Amount to write
+ *   retlen : Amount of data actually written
+ *   buf    : Buffer containing the data
+ */
+static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
+			   size_t *retlen, const u_char *buf)
+{
+	struct dataflash *priv = mtd->priv;
+	struct spi_device *spi = priv->spi;
+	u32 pageaddr, addr, offset, writelen;
+	size_t remaining = len;
+	u_char *writebuf = (u_char *) buf;
+	int status = -EINVAL;
+	u_char txer[SPI_FIFOSIZE] = { 0 };
+	uint8_t *command = priv->command;
+	u_char *d = txer;
+	u_char *s = (u_char *) buf;
+	int delta = 0, l = 0, i = 0, count = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "%s: write 0x%x..0x%x\n",
+	      dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len));
+
+	*retlen = 0;
+
+	/* Sanity checks */
+	if (!len)
+		return 0;
+
+	if ((to + len) > mtd->size)
+		return -EINVAL;
+
+	pageaddr = ((unsigned)to / priv->page_size);
+	offset = ((unsigned)to % priv->page_size);
+	if (offset + len > priv->page_size)
+		writelen = priv->page_size - offset;
+	else
+		writelen = len;
+
+	mutex_lock(&priv->lock);
+
+	while (remaining > 0) {
+		DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n",
+		      pageaddr, offset, writelen);
+
+		addr = pageaddr << priv->page_offset;
+
+		/* (1) Maybe transfer partial page to Buffer1 */
+		if (writelen != priv->page_size) {
+			command[3] = OP_TRANSFER_BUF1;
+			command[2] = (addr & 0x00FF0000) >> 16;
+			command[1] = (addr & 0x0000FF00) >> 8;
+			command[0] = 0;
+
+			DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n",
+			      command[3], command[2], command[1], command[0]);
+
+			status = spi_read_write(spi, command, CMD_SIZE);
+			if (status) {
+				mutex_unlock(&priv->lock);
+				return status;
+
+			}
+
+			(void)dataflash_waitready(spi);
+		}
+
+		count = writelen;
+		while (count) {
+			d = txer;
+			l = count > (SPI_FIFOSIZE - CMD_SIZE) ?
+			    SPI_FIFOSIZE - CMD_SIZE : count;
+
+			delta = l % 4;
+			if (delta) {
+				switch (delta) {
+				case 1:
+					d[0] = OP_WRITE_BUFFER1;
+					d[6] = (offset >> 8) & 0xff;
+					d[5] = offset & 0xff;
+					d[4] = *s++;
+					break;
+				case 2:
+					d[1] = OP_WRITE_BUFFER1;
+					d[7] = (offset >> 8) & 0xff;
+					d[6] = offset & 0xff;
+					d[5] = *s++;
+					d[4] = *s++;
+					break;
+				case 3:
+					d[2] = OP_WRITE_BUFFER1;
+					d[0] = (offset >> 8) & 0xff;
+					d[7] = offset & 0xff;
+					d[6] = *s++;
+					d[5] = *s++;
+					d[4] = *s++;
+					break;
+				default:
+					break;
+				}
+
+				DEBUG(MTD_DEBUG_LEVEL3,
+				      "WRITEBUF: (%x) %x %x %x\n",
+				      txer[3], txer[2], txer[1], txer[0]);
+
+				status = spi_read_write(spi, txer,
+							delta + CMD_SIZE);
+				if (status) {
+					mutex_unlock(&priv->lock);
+					return status;
+				}
+
+				/* update */
+				count -= delta;
+				offset += delta;
+				l -= delta;
+			}
+
+			d[3] = OP_WRITE_BUFFER1;
+			d[1] = (offset >> 8) & 0xff;
+			d[0] = offset & 0xff;
+
+			for (i = 0, d += 4; i < l / 4; i++, d += 4) {
+				d[3] = *s++;
+				d[2] = *s++;
+				d[1] = *s++;
+				d[0] = *s++;
+			}
+
+			DEBUG(MTD_DEBUG_LEVEL3, "WRITEBUF: (%x) %x %x %x\n",
+			      txer[3], txer[2], txer[1], txer[0]);
+
+			status = spi_read_write(spi, txer, l + CMD_SIZE);
+			if (status) {
+				mutex_unlock(&priv->lock);
+				return status;
+			}
+
+			/* update */
+			count -= l;
+			offset += l;
+		}
+
+		/* (2) Program full page via Buffer1 */
+		command[3] = OP_MWERASE_BUFFER1;
+		command[2] = (addr >> 16) & 0xff;
+		command[1] = (addr >> 8) & 0xff;
+
+		DEBUG(MTD_DEBUG_LEVEL3, "PROGRAM: (%x) %x %x %x\n",
+		      command[3], command[2], command[1], command[0]);
+
+		status = spi_read_write(spi, command, CMD_SIZE);
+		if (status) {
+			mutex_unlock(&priv->lock);
+			return status;
+		}
+
+		(void)dataflash_waitready(spi);
+
+		remaining -= writelen;
+		pageaddr++;
+		offset = 0;
+		writebuf += writelen;
+		*retlen += writelen;
+
+		if (remaining > priv->page_size)
+			writelen = priv->page_size;
+		else
+			writelen = remaining;
+	}
+	mutex_unlock(&priv->lock);
+
+	return status;
+}
+
+/* ......................................................................... */
+
+#ifdef CONFIG_MTD_DATAFLASH_OTP
+
+static int dataflash_get_otp_info(struct mtd_info *mtd,
+				  struct otp_info *info, size_t len)
+{
+	/* Report both blocks as identical:  bytes 0..64, locked.
+	 * Unless the user block changed from all-ones, we can't
+	 * tell whether it's still writable; so we assume it isn't.
+	 */
+	info->start = 0;
+	info->length = 64;
+	info->locked = 1;
+	return sizeof(*info);
+}
+
+static ssize_t otp_read(struct spi_device *spi, unsigned base,
+			uint8_t *buf, loff_t off, size_t len)
+{
+	struct dataflash *priv = mtd->priv;
+	struct spi_device *spi = priv->spi;
+	int rx_len = 0, count = 0, i = 0;
+	u_char txer[SPI_FIFOSIZE];
+	u_char *s = txer;
+	u_char *d = NULL;
+	int cmd_len = CMD_SIZE;
+	int status;
+
+	if (off > 64)
+		return -EINVAL;
+
+	if ((off + len) > 64)
+		len = 64 - off;
+	if (len == 0)
+		return len;
+
+	/* to make simple, we read 64 out */
+	l = base + 64;
+
+	d = kzalloc(l, GFP_KERNEL);
+	if (!d)
+		return -ENOMEM;
+
+	while (l > 0) {
+
+		rx_len = l > (SPI_FIFOSIZE - cmd_len) ?
+		    SPI_FIFOSIZE - cmd_len : l;
+
+		txer[3] = OP_READ_SECURITY;
+
+		status = spi_read_write(spi, txer, rx_len + cmd_len);
+		if (status) {
+			mutex_unlock(&priv->lock);
+			return status;
+		}
+
+		s = txer + cmd_len;
+		for (i = rx_len; i >= 0; i -= 4, s += 4) {
+
+			*d++ = s[3];
+			*d++ = s[2];
+			*d++ = s[1];
+			*d++ = s[0];
+		}
+
+		/* updaate */
+		l -= rx_len;
+		addr += rx_len;
+		count += rx_len;
+
+		DEBUG(MTD_DEBUG_LEVEL2,
+		      "%s: left:0x%x, from:0x%08x, to:0x%p, done: 0x%x\n",
+		      __func__, len, (u32) addr, d, count);
+	}
+
+	d -= count;
+	memcpy(buf, d + base + off, len);
+
+	mutex_unlock(&priv->lock);
+
+	return len;
+}
+
+static int dataflash_read_fact_otp(struct mtd_info *mtd,
+				   loff_t from, size_t len, size_t *retlen,
+				   u_char *buf)
+{
+	struct dataflash *priv = (struct dataflash *)mtd->priv;
+	int status;
+
+	/* 64 bytes, from 0..63 ... start at 64 on-chip */
+	mutex_lock(&priv->lock);
+	status = otp_read(priv->spi, 64, buf, from, len);
+	mutex_unlock(&priv->lock);
+
+	if (status < 0)
+		return status;
+	*retlen = status;
+	return 0;
+}
+
+static int dataflash_read_user_otp(struct mtd_info *mtd,
+				   loff_t from, size_t len, size_t *retlen,
+				   u_char *buf)
+{
+	struct dataflash *priv = (struct dataflash *)mtd->priv;
+	int status;
+
+	/* 64 bytes, from 0..63 ... start at 0 on-chip */
+	mutex_lock(&priv->lock);
+	status = otp_read(priv->spi, 0, buf, from, len);
+	mutex_unlock(&priv->lock);
+
+	if (status < 0)
+		return status;
+	*retlen = status;
+	return 0;
+}
+
+static int dataflash_write_user_otp(struct mtd_info *mtd,
+				    loff_t from, size_t len, size_t *retlen,
+				    u_char *buf)
+{
+	printk(KERN_ERR "%s not support!!\n", __func__);
+	return 0;
+}
+
+static char *otp_setup(struct mtd_info *device, char revision)
+{
+	device->get_fact_prot_info = dataflash_get_otp_info;
+	device->read_fact_prot_reg = dataflash_read_fact_otp;
+	device->get_user_prot_info = dataflash_get_otp_info;
+	device->read_user_prot_reg = dataflash_read_user_otp;
+
+	/* rev c parts (at45db321c and at45db1281 only!) use a
+	 * different write procedure; not (yet?) implemented.
+	 */
+	if (revision > 'c')
+		device->write_user_prot_reg = dataflash_write_user_otp;
+
+	return ", OTP";
+}
+
+#else
+
+static char *otp_setup(struct mtd_info *device, char revision)
+{
+	return " (OTP)";
+}
+
+#endif
+
+/* ......................................................................... */
+
+/*
+ * Register DataFlash device with MTD subsystem.
+ */
+static int __devinit
+add_dataflash_otp(struct spi_device *spi, char *name,
+		  int nr_pages, int pagesize, int pageoffset, char revision)
+{
+	struct dataflash *priv;
+	struct mtd_info *device;
+	struct flash_platform_data *pdata = spi->dev.platform_data;
+	char *otp_tag = "";
+
+	priv = kzalloc(sizeof *priv, GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	mutex_init(&priv->lock);
+	priv->spi = spi;
+	priv->page_size = pagesize;
+	priv->page_offset = pageoffset;
+
+	/* name must be usable with cmdlinepart */
+	sprintf(priv->name, "spi%d.%d-%s",
+		spi->master->bus_num, spi->chip_select, name);
+
+	device = &priv->mtd;
+	device->name = (pdata && pdata->name) ? pdata->name : priv->name;
+	device->size = nr_pages * pagesize;
+	device->erasesize = pagesize;
+	device->writesize = pagesize;
+	device->owner = THIS_MODULE;
+	device->type = MTD_DATAFLASH;
+	device->flags = MTD_CAP_NORFLASH;
+	device->erase = dataflash_erase;
+	device->read = dataflash_read;
+	device->write = dataflash_write;
+	device->priv = priv;
+
+	if (revision >= 'c')
+		otp_tag = otp_setup(device, revision);
+
+	dev_info(&spi->dev, "%s (%llx KBytes) pagesize %d bytes%s\n",
+		 name, DIV_ROUND_UP(device->size, 1024), pagesize, otp_tag);
+	dev_set_drvdata(&spi->dev, priv);
+
+	if (mtd_has_partitions()) {
+		struct mtd_partition *parts;
+		int nr_parts = 0;
+
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+		static const char *part_probes[] = { "cmdlinepart", NULL, };
+
+		nr_parts = parse_mtd_partitions(device, part_probes, &parts, 0);
+#endif
+
+		if (nr_parts <= 0 && pdata && pdata->parts) {
+			parts = pdata->parts;
+			nr_parts = pdata->nr_parts;
+		}
+
+		if (nr_parts > 0) {
+			priv->partitioned = 1;
+			return add_mtd_partitions(device, parts, nr_parts);
+		}
+	} else if (pdata && pdata->nr_parts)
+		dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
+			 pdata->nr_parts, device->name);
+
+	return add_mtd_device(device) == 1 ? -ENODEV : 0;
+}
+
+static inline int __devinit
+add_dataflash(struct spi_device *spi, char *name,
+	      int nr_pages, int pagesize, int pageoffset)
+{
+	return add_dataflash_otp(spi, name, nr_pages, pagesize, pageoffset, 0);
+}
+
+struct flash_info {
+	char *name;
+
+	/* JEDEC id has a high byte of zero plus three data bytes:
+	 * the manufacturer id, then a two byte device id.
+	 */
+	uint32_t jedec_id;
+
+	/* The size listed here is what works with OP_ERASE_PAGE. */
+	unsigned nr_pages;
+	uint16_t pagesize;
+	uint16_t pageoffset;
+
+	uint16_t flags;
+#define SUP_POW2PS	0x0002	/* supports 2^N byte pages */
+#define IS_POW2PS	0x0001	/* uses 2^N byte pages */
+};
+
+static struct flash_info __devinitdata dataflash_data[] = {
+
+	/*
+	 * NOTE:  chips with SUP_POW2PS (rev D and up) need two entries,
+	 * one with IS_POW2PS and the other without.  The entry with the
+	 * non-2^N byte page size can't name exact chip revisions without
+	 * losing backwards compatibility for cmdlinepart.
+	 *
+	 * These newer chips also support 128-byte security registers (with
+	 * 64 bytes one-time-programmable) and software write-protection.
+	 */
+	{"AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
+	{"at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
+	{"at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
+	{"at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
+	{"at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
+	{"at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB321x", 0x1f2700, 8192, 528, 10, 0},	/* rev C */
+
+	{"AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
+	{"at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+	{"AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
+	{"at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
+};
+
+static struct flash_info *__devinit jedec_probe(struct spi_device *spi)
+{
+	int tmp;
+	u32 code = OP_READ_ID << 24;
+	u32 jedec;
+	struct flash_info *info;
+	int status;
+
+	/* JEDEC also defines an optional "extended device information"
+	 * string for after vendor-specific data, after the three bytes
+	 * we use here.  Supporting some chips might require using it.
+	 *
+	 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
+	 * That's not an error; only rev C and newer chips handle it, and
+	 * only Atmel sells these chips.
+	 */
+
+	tmp = spi_read_write(spi, (u8 *)&code, 4);
+	if (tmp < 0) {
+		DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n",
+		      dev_name(&spi->dev), tmp);
+		return NULL;
+	}
+
+	jedec = code & 0xFFFFFF;
+
+	for (tmp = 0, info = dataflash_data;
+	     tmp < ARRAY_SIZE(dataflash_data); tmp++, info++) {
+		if (info->jedec_id == jedec) {
+			DEBUG(MTD_DEBUG_LEVEL1, "%s: OTP, sector protect%s\n",
+			      dev_name(&spi->dev), (info->flags & SUP_POW2PS)
+			      ? ", binary pagesize" : "");
+			if (info->flags & SUP_POW2PS) {
+				status = dataflash_status(spi);
+				if (status < 0) {
+					DEBUG(MTD_DEBUG_LEVEL1,
+					      "%s: status error %d\n",
+					      dev_name(&spi->dev), status);
+					return ERR_PTR(status);
+				}
+				if (status & 0x1) {
+					if (info->flags & IS_POW2PS)
+						return info;
+				} else {
+					if (!(info->flags & IS_POW2PS))
+						return info;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Treat other chips as errors ... we won't know the right page
+	 * size (it might be binary) even when we can tell which density
+	 * class is involved (legacy chip id scheme).
+	 */
+	dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec);
+	return ERR_PTR(-ENODEV);
+}
+
+/*
+ * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
+ * or else the ID code embedded in the status bits:
+ *
+ *   Device      Density         ID code          #Pages PageSize  Offset
+ *   AT45DB011B  1Mbit   (128K)  xx0011xx (0x0c)    512    264      9
+ *   AT45DB021B  2Mbit   (256K)  xx0101xx (0x14)   1024    264      9
+ *   AT45DB041B  4Mbit   (512K)  xx0111xx (0x1c)   2048    264      9
+ *   AT45DB081B  8Mbit   (1M)    xx1001xx (0x24)   4096    264      9
+ *   AT45DB0161B 16Mbit  (2M)    xx1011xx (0x2c)   4096    528     10
+ *   AT45DB0321B 32Mbit  (4M)    xx1101xx (0x34)   8192    528     10
+ *   AT45DB0642  64Mbit  (8M)    xx111xxx (0x3c)   8192   1056     11
+ *   AT45DB1282  128Mbit (16M)   xx0100xx (0x10)  16384   1056     11
+ */
+static int __devinit dataflash_probe(struct spi_device *spi)
+{
+	int status;
+	struct flash_info *info;
+
+	/*
+	 * Try to detect dataflash by JEDEC ID.
+	 * If it succeeds we know we have either a C or D part.
+	 * D will support power of 2 pagesize option.
+	 * Both support the security register, though with different
+	 * write procedures.
+	 */
+	info = jedec_probe(spi);
+	if (IS_ERR(info))
+		return PTR_ERR(info);
+	if (info != NULL)
+		return add_dataflash_otp(spi, info->name, info->nr_pages,
+					 info->pagesize, info->pageoffset,
+					 (info->flags & SUP_POW2PS) ? 'd' :
+					 'c');
+
+	/*
+	 * Older chips support only legacy commands, identifing
+	 * capacity using bits in the status byte.
+	 */
+	status = dataflash_status(spi);
+	if (status <= 0 || status == 0xff) {
+		DEBUG(MTD_DEBUG_LEVEL1, "%s: status error %d\n",
+		      dev_name(&spi->dev), status);
+		if (status == 0 || status == 0xff)
+			status = -ENODEV;
+		return status;
+	}
+
+	/* if there's a device there, assume it's dataflash.
+	 * board setup should have set spi->max_speed_max to
+	 * match f(car) for continuous reads, mode 0 or 3.
+	 */
+	switch (status & 0x3c) {
+	case 0x0c:		/* 0 0 1 1 x x */
+		status = add_dataflash(spi, "AT45DB011B", 512, 264, 9);
+		break;
+	case 0x14:		/* 0 1 0 1 x x */
+		status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9);
+		break;
+	case 0x1c:		/* 0 1 1 1 x x */
+		status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9);
+		break;
+	case 0x24:		/* 1 0 0 1 x x */
+		status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9);
+		break;
+	case 0x2c:		/* 1 0 1 1 x x */
+		status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10);
+		break;
+	case 0x34:		/* 1 1 0 1 x x */
+		status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10);
+		break;
+	case 0x38:		/* 1 1 1 x x x */
+	case 0x3c:
+		status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11);
+		break;
+		/* obsolete AT45DB1282 not (yet?) supported */
+	default:
+		DEBUG(MTD_DEBUG_LEVEL1, "%s: unsupported device (%x)\n",
+		      dev_name(&spi->dev), status & 0x3c);
+		status = -ENODEV;
+	}
+
+	if (status < 0)
+		DEBUG(MTD_DEBUG_LEVEL1, "%s: add_dataflash --> %d\n",
+		      dev_name(&spi->dev), status);
+
+	return status;
+}
+
+static int __devexit dataflash_remove(struct spi_device *spi)
+{
+	struct dataflash *flash = dev_get_drvdata(&spi->dev);
+	int status;
+
+	DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", dev_name(&spi->dev));
+
+	if (mtd_has_partitions() && flash->partitioned)
+		status = del_mtd_partitions(&flash->mtd);
+	else
+		status = del_mtd_device(&flash->mtd);
+	if (status == 0)
+		kfree(flash);
+	return status;
+}
+
+static struct spi_driver dataflash_driver = {
+	.driver = {
+		   .name = "mxc_dataflash",
+		   .bus = &spi_bus_type,
+		   .owner = THIS_MODULE,
+		   },
+
+	.probe = dataflash_probe,
+	.remove = __devexit_p(dataflash_remove),
+
+	/* FIXME:  investigate suspend and resume... */
+};
+
+static int __init dataflash_init(void)
+{
+	return spi_register_driver(&dataflash_driver);
+}
+
+module_init(dataflash_init);
+
+static void __exit dataflash_exit(void)
+{
+	spi_unregister_driver(&dataflash_driver);
+}
+
+module_exit(dataflash_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MTD DataFlash driver");
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 7a58bd5522fd..c90fcb79af03 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -546,4 +546,14 @@ config MTD_VMU
 	  To build this as a module select M here, the module will be called
 	  vmu-flash.
 
+config MTD_MXC
+	bool "Map driver for Freescale MXC boards"
+	depends on MTD && ARCH_MXC
+	default y
+	select MTD_CFI
+	select MTD_PARTITIONS
+	help
+	  This enables access to the flash chips on Freescale MXC based
+	  platforms. If you have such a board, say 'Y'.
+
 endmenu
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 5beb0662d724..01bf210825c9 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_MTD_INTEL_VR_NOR)	+= intel_vr_nor.o
 obj-$(CONFIG_MTD_BFIN_ASYNC)	+= bfin-async-flash.o
 obj-$(CONFIG_MTD_RBTX4939)	+= rbtx4939-flash.o
 obj-$(CONFIG_MTD_VMU)		+= vmu-flash.o
+obj-$(CONFIG_MTD_MXC)		+= mxc_nor.o
diff --git a/drivers/mtd/maps/mxc_nor.c b/drivers/mtd/maps/mxc_nor.c
new file mode 100644
index 000000000000..69b55bcac847
--- /dev/null
+++ b/drivers/mtd/maps/mxc_nor.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * (c) 2005 MontaVista Software, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/ioport.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/clocksource.h>
+#include <asm/mach-types.h>
+#include <asm/mach/flash.h>
+
+#define DVR_VER "2.0"
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
+#endif
+
+struct clocksource *mtd_xip_clksrc;
+
+struct mxcflash_info {
+	struct mtd_partition *parts;
+	struct mtd_info *mtd;
+	struct map_info map;
+};
+
+/*!
+ * @defgroup NOR_MTD NOR Flash MTD Driver
+ */
+
+/*!
+ * @file mxc_nor.c
+ *
+ * @brief This file contains the MTD Mapping information on the MXC.
+ *
+ * @ingroup NOR_MTD
+ */
+
+static int __devinit mxcflash_probe(struct platform_device *pdev)
+{
+	int err, nr_parts = 0;
+	struct mxcflash_info *info;
+	struct flash_platform_data *flash = pdev->dev.platform_data;
+	struct resource *res = pdev->resource;
+	unsigned long size = res->end - res->start + 1;
+
+	info = kzalloc(sizeof(struct mxcflash_info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	if (!request_mem_region(res->start, size, "flash")) {
+		err = -EBUSY;
+		goto out_free_info;
+	}
+	info->map.virt = ioremap(res->start, size);
+	if (!info->map.virt) {
+		err = -ENOMEM;
+		goto out_release_mem_region;
+	}
+	info->map.name = dev_name(&pdev->dev);
+	info->map.phys = res->start;
+	info->map.size = size;
+	info->map.bankwidth = flash->width;
+
+	mtd_xip_clksrc = clocksource_get_next();
+
+	simple_map_init(&info->map);
+	info->mtd = do_map_probe(flash->map_name, &info->map);
+	if (!info->mtd) {
+		err = -EIO;
+		goto out_iounmap;
+	}
+	info->mtd->owner = THIS_MODULE;
+
+#ifdef CONFIG_MTD_PARTITIONS
+	nr_parts =
+	    parse_mtd_partitions(info->mtd, part_probes, &info->parts, 0);
+	if (nr_parts > 0) {
+		add_mtd_partitions(info->mtd, info->parts, nr_parts);
+	} else if (flash->parts) {
+		add_mtd_partitions(info->mtd, flash->parts, flash->nr_parts);
+	} else
+#endif
+	{
+		printk(KERN_NOTICE "MXC flash: no partition info "
+		       "available, registering whole flash\n");
+		add_mtd_device(info->mtd);
+	}
+
+	platform_set_drvdata(pdev, info);
+	return 0;
+
+      out_iounmap:
+	iounmap(info->map.virt);
+      out_release_mem_region:
+	release_mem_region(res->start, size);
+      out_free_info:
+	kfree(info);
+
+	return err;
+}
+
+static int __devexit mxcflash_remove(struct platform_device *pdev)
+{
+
+	struct mxcflash_info *info = platform_get_drvdata(pdev);
+	struct flash_platform_data *flash = pdev->dev.platform_data;
+
+	platform_set_drvdata(pdev, NULL);
+
+	if (info) {
+		if (info->parts) {
+			del_mtd_partitions(info->mtd);
+			kfree(info->parts);
+		} else if (flash->parts)
+			del_mtd_partitions(info->mtd);
+		else
+			del_mtd_device(info->mtd);
+
+		map_destroy(info->mtd);
+		release_mem_region(info->map.phys, info->map.size);
+		iounmap((void __iomem *)info->map.virt);
+		kfree(info);
+	}
+	return 0;
+}
+
+static struct platform_driver mxcflash_driver = {
+	.driver = {
+		   .name = "mxc_nor_flash",
+		   },
+	.probe = mxcflash_probe,
+	.remove = __devexit_p(mxcflash_remove),
+};
+
+/*!
+ * This is the module's entry function. It passes board specific
+ * config details into the MTD physmap driver which then does the
+ * real work for us. After this function runs, our job is done.
+ *
+ * @return  0 if successful; non-zero otherwise
+ */
+static int __init mxc_mtd_init(void)
+{
+	pr_info("MXC MTD nor Driver %s\n", DVR_VER);
+	if (platform_driver_register(&mxcflash_driver) != 0) {
+		printk(KERN_ERR "Driver register failed for mxcflash_driver\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+/*!
+ * This function is the module's exit function. It's empty because the
+ * MTD physmap driver is doing the real work and our job was done after
+ * mxc_mtd_init() runs.
+ */
+static void __exit mxc_mtd_exit(void)
+{
+	platform_driver_unregister(&mxcflash_driver);
+}
+
+module_init(mxc_mtd_init);
+module_exit(mxc_mtd_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MTD map and partitions for Freescale MXC boards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c
index 7baba40c1ed2..5febf394bc3e 100644
--- a/drivers/mtd/mtd_blkdevs.c
+++ b/drivers/mtd/mtd_blkdevs.c
@@ -137,6 +137,24 @@ static void mtd_blktrans_request(struct request_queue *rq)
 	wake_up_process(tr->blkcore_priv->thread);
 }
 
+static int blktrans_mtd_get(struct mtd_info *mtd)
+{
+	if (mtd) {
+		if (!get_mtd_device(mtd, mtd->index))
+			return -ENODEV;
+		mtd->usecount++;
+	}
+	return 0;
+}
+
+static int blktrans_mtd_put(struct mtd_info *mtd)
+{
+	if (mtd) {
+		mtd->usecount--;
+		put_mtd_device(mtd);
+	}
+	return 0;
+}
 
 static int blktrans_open(struct block_device *bdev, fmode_t mode)
 {
@@ -144,25 +162,25 @@ static int blktrans_open(struct block_device *bdev, fmode_t mode)
 	struct mtd_blktrans_ops *tr = dev->tr;
 	int ret = -ENODEV;
 
-	if (!get_mtd_device(NULL, dev->mtd->index))
+	if (!try_module_get(tr->owner))
 		goto out;
 
-	if (!try_module_get(tr->owner))
+	ret = blktrans_mtd_get(dev->mtd);
+	if (ret < 0)
 		goto out_tr;
 
-	/* FIXME: Locking. A hot pluggable device can go away
-	   (del_mtd_device can be called for it) without its module
-	   being unloaded. */
-	dev->mtd->usecount++;
-
 	ret = 0;
+
 	if (tr->open && (ret = tr->open(dev))) {
-		dev->mtd->usecount--;
-		put_mtd_device(dev->mtd);
-	out_tr:
-		module_put(tr->owner);
+		blktrans_mtd_put(dev->mtd);
+		goto out_tr;
 	}
- out:
+
+	return 0;
+
+out_tr:
+	module_put(tr->owner);
+out:
 	return ret;
 }
 
@@ -176,8 +194,7 @@ static int blktrans_release(struct gendisk *disk, fmode_t mode)
 		ret = tr->release(dev);
 
 	if (!ret) {
-		dev->mtd->usecount--;
-		put_mtd_device(dev->mtd);
+		blktrans_mtd_put(dev->mtd);
 		module_put(tr->owner);
 	}
 
@@ -291,7 +308,8 @@ int add_mtd_blktrans_dev(struct mtd_blktrans_dev *new)
 	gd->private_data = new;
 	new->blkcore_priv = gd;
 	gd->queue = tr->blkcore_priv->rq;
-	gd->driverfs_dev = &new->mtd->dev;
+	if (new->mtd)
+		gd->driverfs_dev = &new->mtd->dev;
 
 	if (new->readonly)
 		set_disk_ro(gd, 1);
@@ -360,13 +378,15 @@ int register_mtd_blktrans(struct mtd_blktrans_ops *tr)
 	mutex_lock(&mtd_table_mutex);
 
 	ret = register_blkdev(tr->major, tr->name);
-	if (ret) {
+	if (ret < 0) {
 		printk(KERN_WARNING "Unable to register %s block device on major %d: %d\n",
 		       tr->name, tr->major, ret);
 		kfree(tr->blkcore_priv);
 		mutex_unlock(&mtd_table_mutex);
 		return ret;
 	}
+	if (!tr->major)
+		tr->major = ret;
 	spin_lock_init(&tr->blkcore_priv->queue_lock);
 
 	tr->blkcore_priv->rq = blk_init_queue(mtd_blktrans_request, &tr->blkcore_priv->queue_lock);
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ce96c091f01b..1a85f6d5543b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -378,6 +378,68 @@ config MTD_NAND_NANDSIM
 	  The simulator may simulate various NAND flash chips for the
 	  MTD nand layer.
 
+config MTD_NAND_IMX_NFC
+	tristate "i.MX NAND Flash Controller driver"
+	depends on MTD_NAND && (ARCH_MX2 || ARCH_MX3 || ARCH_MX5)
+	help
+	  Enables the i.MX NAND Flash controller driver.
+
+config MTD_NAND_MXC
+	tristate "MXC NAND support"
+	depends on MTD_NAND && ARCH_MXC_HAS_NFC_V1
+	help
+	  This enables the driver for the NAND flash controller on the
+	  MXC processors.
+
+config MTD_NAND_MXC_V2
+	tristate "MXC NAND Version 2 support"
+	depends on MTD_NAND && ARCH_MXC_HAS_NFC_V2
+	help
+	  This enables the driver for the version 2 of NAND flash controller
+	  on the MXC processors.
+
+config MTD_NAND_MXC_V3
+	tristate "MXC NAND Version 3 support"
+	depends on MTD_NAND && ARCH_MXC_HAS_NFC_V3
+	help
+	  This enables the driver for the version 3 of NAND flash controller
+	  on the MXC processors.
+
+config MTD_NAND_MXC_SWECC
+	bool "Software ECC support "
+	depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3
+	help
+	  This enables the support for Software ECC handling. By
+	  default MXC NAND controller Hardware ECC is supported.
+
+
+config MTD_NAND_MXC_FORCE_CE
+	bool "NAND chip select operation support"
+	 depends on MTD_NAND_MXC || MTD_NAND_MXC_V2|| MTD_NAND_MXC_V3
+	help
+	  This enables the NAND chip select by using CE control line. By
+	  default CE operation is disabled.
+
+config MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+	bool "ECC correction in S/W"
+	depends on MTD_NAND_MXC
+	help
+	  This enables the Option2 NFC ECC correction in software. By
+	  default Option 1 is selected. Enable if you need option2 ECC correction.
+
+config MXC_NAND_LOW_LEVEL_ERASE
+	bool "Low level NAND erase"
+	depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3
+	help
+	  This enables the erase of whole NAND flash. By
+	  default low level erase operation is disabled.
+
+config MTD_NAND_GPMI_NFC
+        tristate "GPMI NAND Flash Controller driver"
+        depends on MTD_NAND && (ARCH_MX23 || ARCH_MX28 || ARCH_MX50)
+        help
+         Enables NAND Flash support.
+
 config MTD_NAND_PLATFORM
 	tristate "Support for generic platform NAND driver"
 	depends on MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f3a786b3cff3..2245a8df441b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,7 +37,11 @@ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_ELBC)		+= fsl_elbc_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_UPM)		+= fsl_upm.o
 obj-$(CONFIG_MTD_NAND_SH_FLCTL)		+= sh_flctl.o
+obj-$(CONFIG_MTD_NAND_IMX_NFC)		+= imx_nfc.o
 obj-$(CONFIG_MTD_NAND_MXC)		+= mxc_nand.o
+obj-$(CONFIG_MTD_NAND_MXC_V2)		+= mxc_nd2.o nand_device_info.o
+obj-$(CONFIG_MTD_NAND_MXC_V3)		+= mxc_nd2.o nand_device_info.o
+obj-$(CONFIG_MTD_NAND_GPMI_NFC)		+= gpmi-nfc/ nand_device_info.o
 obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
 
diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile
new file mode 100644
index 000000000000..9df1b6454e90
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/Makefile
@@ -0,0 +1,11 @@
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o
+gpmi-nfc-objs += gpmi-nfc-main.o
+gpmi-nfc-objs += gpmi-nfc-event-reporting.o
+gpmi-nfc-objs += gpmi-nfc-hal-common.o
+gpmi-nfc-objs += gpmi-nfc-hal-v0.o
+gpmi-nfc-objs += gpmi-nfc-hal-v1.o
+gpmi-nfc-objs += gpmi-nfc-hal-v2.o
+gpmi-nfc-objs += gpmi-nfc-rom-common.o
+gpmi-nfc-objs += gpmi-nfc-rom-v0.o
+gpmi-nfc-objs += gpmi-nfc-rom-v1.o
+gpmi-nfc-objs += gpmi-nfc-mil.o
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h
new file mode 100644
index 000000000000..9af4feb29021
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h
@@ -0,0 +1,550 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST	0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE	0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5	23
+#define BM_BCH_CTRL_RSVD5	0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
+#define BP_BCH_CTRL_RSVD4	20
+#define BM_BCH_CTRL_RSVD4	0x00300000
+#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT	18
+#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
+#define BP_BCH_CTRL_RSVD3	11
+#define BM_BCH_CTRL_RSVD3	0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
+#define BM_BCH_CTRL_RSVD2	0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
+#define BP_BCH_CTRL_RSVD1	4
+#define BM_BCH_CTRL_RSVD1	0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
+#define BM_BCH_CTRL_RSVD0	0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE	20
+#define BM_BCH_STATUS0_HANDLE	0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+		(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE	16
+#define BM_BCH_STATUS0_COMPLETED_CE	0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+		(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0	8
+#define BM_BCH_STATUS0_STATUS_BLK0	0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+		(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1	5
+#define BM_BCH_STATUS0_RSVD1	0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+		(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES	0x00000010
+#define BM_BCH_STATUS0_CORRECTED	0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE	0x00000004
+#define BP_BCH_STATUS0_RSVD0	0
+#define BM_BCH_STATUS0_RSVD0	0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+		(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD	8
+#define BM_BCH_MODE_RSVD	0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+		(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD	0
+#define BM_BCH_MODE_ERASE_THRESHOLD	0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+		(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR	0
+#define BM_BCH_ENCODEPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR	0
+#define BM_BCH_DATAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR	0
+#define BM_BCH_METAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT	30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT	0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+		(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT	28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT	0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+		(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT	26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT	0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+		(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT	24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT	0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+		(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT	22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT	0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+		(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT	20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT	0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+		(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT	18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT	0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+		(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT	16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT	0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+		(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT	14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT	0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+		(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT	12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT	0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+		(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT	10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT	0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+		(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT	8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT	0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+		(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT	6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT	0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+		(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT	4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT	0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+		(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT	2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT	0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+		(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT	0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT	0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+		(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0	12
+#define BM_BCH_FLASH0LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN	12
+#define BM_BCH_FLASH0LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0	12
+#define BM_BCH_FLASH1LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN	12
+#define BM_BCH_FLASH1LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0	12
+#define BM_BCH_FLASH2LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN	12
+#define BM_BCH_FLASH2LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0	12
+#define BM_BCH_FLASH3LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN	12
+#define BM_BCH_FLASH3LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1	27
+#define BM_BCH_DEBUG0_RSVD1	0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+		(((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE	0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE	0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+		(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND	0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG	0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K	0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK	0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE	0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP	0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL	0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS	0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0	6
+#define BM_BCH_DEBUG0_RSVD0	0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+		(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT	0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT	0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+		(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES	0
+#define BM_BCH_DBGKESREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES	0
+#define BM_BCH_DBGCSFEREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES	0
+#define BM_BCH_DBGSYNDGENREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES	0
+#define BM_BCH_DBGAHBMREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME	0
+#define BM_BCH_BLOCKNAME_NAME	0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR	24
+#define BM_BCH_VERSION_MAJOR	0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR	16
+#define BM_BCH_VERSION_MINOR	0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP	0
+#define BM_BCH_VERSION_STEP	0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h
new file mode 100644
index 000000000000..692db086de4d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h
@@ -0,0 +1,557 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.5
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST	0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE	0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5	23
+#define BM_BCH_CTRL_RSVD5	0x3F800000
+#define BF_BCH_CTRL_RSVD5(v)  \
+		(((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
+#define BP_BCH_CTRL_RSVD4	20
+#define BM_BCH_CTRL_RSVD4	0x00300000
+#define BF_BCH_CTRL_RSVD4(v)  \
+		(((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT	18
+#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)  \
+		(((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
+#define BP_BCH_CTRL_RSVD3	11
+#define BM_BCH_CTRL_RSVD3	0x0000F800
+#define BF_BCH_CTRL_RSVD3(v)  \
+		(((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
+#define BM_BCH_CTRL_RSVD2	0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
+#define BP_BCH_CTRL_RSVD1	4
+#define BM_BCH_CTRL_RSVD1	0x000000F0
+#define BF_BCH_CTRL_RSVD1(v)  \
+		(((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
+#define BM_BCH_CTRL_RSVD0	0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE	20
+#define BM_BCH_STATUS0_HANDLE	0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+		(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE	16
+#define BM_BCH_STATUS0_COMPLETED_CE	0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+		(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0	8
+#define BM_BCH_STATUS0_STATUS_BLK0	0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+		(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1	5
+#define BM_BCH_STATUS0_RSVD1	0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+		(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES	0x00000010
+#define BM_BCH_STATUS0_CORRECTED	0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE	0x00000004
+#define BP_BCH_STATUS0_RSVD0	0
+#define BM_BCH_STATUS0_RSVD0	0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+		(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD	8
+#define BM_BCH_MODE_RSVD	0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+		(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD	0
+#define BM_BCH_MODE_ERASE_THRESHOLD	0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+		(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR	0
+#define BM_BCH_ENCODEPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR	0
+#define BM_BCH_DATAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR	0
+#define BM_BCH_METAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT	30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT	0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+		(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT	28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT	0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+		(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT	26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT	0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+		(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT	24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT	0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+		(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT	22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT	0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+		(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT	20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT	0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+		(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT	18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT	0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+		(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT	16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT	0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+		(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT	14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT	0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+		(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT	12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT	0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+		(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT	10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT	0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+		(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT	8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT	0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+		(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT	6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT	0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+		(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT	4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT	0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+		(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT	2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT	0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+		(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT	0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT	0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+		(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0	12
+#define BM_BCH_FLASH0LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN	12
+#define BM_BCH_FLASH0LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0	12
+#define BM_BCH_FLASH1LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN	12
+#define BM_BCH_FLASH1LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0	12
+#define BM_BCH_FLASH2LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN	12
+#define BM_BCH_FLASH2LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0	12
+#define BM_BCH_FLASH3LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN	12
+#define BM_BCH_FLASH3LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1	27
+#define BM_BCH_DEBUG0_RSVD1	0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+		(((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE	0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE	0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+		(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND	0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG	0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K	0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK	0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE	0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP	0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL	0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS	0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0	6
+#define BM_BCH_DEBUG0_RSVD0	0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+		(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT	0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT	0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+		(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES	0
+#define BM_BCH_DBGKESREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES	0
+#define BM_BCH_DBGCSFEREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES	0
+#define BM_BCH_DBGSYNDGENREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES	0
+#define BM_BCH_DBGAHBMREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME	0
+#define BM_BCH_BLOCKNAME_NAME	0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR	24
+#define BM_BCH_VERSION_MAJOR	0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR	16
+#define BM_BCH_VERSION_MINOR	0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP	0
+#define BM_BCH_VERSION_STEP	0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h
new file mode 100644
index 000000000000..46c0ceb6ddff
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h
@@ -0,0 +1,567 @@
+/*
+ * Freescale BCH Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.3
+ * Template revision: 1.3
+ */
+
+#ifndef __ARCH_ARM___BCH_H
+#define __ARCH_ARM___BCH_H
+
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5      23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v)  \
+	(((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4      20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v)  \
+	(((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT      18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)  \
+	(((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3      11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v)  \
+	(((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1      4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v)  \
+	(((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE      20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+	(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE      16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+	(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0      8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+	(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1      5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+	(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0      0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+	(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD      8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+	(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD      0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+	(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR      0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)   (v)
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR      0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)   (v)
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR      0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)   (v)
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT      30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+	(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT      28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+	(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT      26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+	(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT      24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+	(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT      22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+	(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT      20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+	(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT      18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+	(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT      16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+	(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT      14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+	(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT      12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+	(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT      10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+	(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT      8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+	(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT      6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+	(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT      4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+	(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT      2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+	(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT      0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+	(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS      24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+	(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+	(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0      11
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F800
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+	(((v) << 11) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC22 0xB
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC24 0xC
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC26 0xD
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC28 0xE
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC30 0xF
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC32 0x10
+#define BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE      0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x000003FF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+	(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN      11
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F800
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+	(((v) << 11) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC22 0xB
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC24 0xC
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC26 0xD
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC28 0xE
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC30 0xF
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC32 0x10
+#define BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE      0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x000003FF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS      24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+	(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+	(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0      11
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F800
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+	(((v) << 11) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC22 0xB
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC24 0xC
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC26 0xD
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC28 0xE
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC30 0xF
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC32 0x10
+#define BM_BCH_FLASH1LAYOUT0_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE      0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x000003FF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+	(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN      11
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F800
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+	(((v) << 11) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC22 0xB
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC24 0xC
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC26 0xD
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC28 0xE
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC30 0xF
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC32 0x10
+#define BM_BCH_FLASH1LAYOUT1_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE      0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x000003FF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS      24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+	(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+	(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0      11
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F800
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+	(((v) << 11) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC22 0xB
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC24 0xC
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC26 0xD
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC28 0xE
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC30 0xF
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC32 0x10
+#define BM_BCH_FLASH2LAYOUT0_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE      0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x000003FF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+	(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN      11
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F800
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+	(((v) << 11) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC22 0xB
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC24 0xC
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC26 0xD
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC28 0xE
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC30 0xF
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC32 0x10
+#define BM_BCH_FLASH2LAYOUT1_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE      0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x000003FF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS      24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+	(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+	(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0      11
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F800
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+	(((v) << 11) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC22 0xB
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC24 0xC
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC26 0xD
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC28 0xE
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC30 0xF
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC32 0x10
+#define BM_BCH_FLASH3LAYOUT0_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE      0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x000003FF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+	(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN      11
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F800
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+	(((v) << 11) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC22 0xB
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC24 0xC
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC26 0xD
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC28 0xE
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC30 0xF
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC32 0x10
+#define BM_BCH_FLASH3LAYOUT1_GF13_0_GF14_1 0x00000400
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE      0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x000003FF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+	(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1      25
+#define BM_BCH_DEBUG0_RSVD1 0xFE000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+	(((v) << 25) & BM_BCH_DEBUG0_RSVD1)
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL      16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+	(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0      6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+	(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT      0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+	(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES      0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)   (v)
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES      0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)   (v)
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES      0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)   (v)
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES      0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)   (v)
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME      0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)   (v)
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR      24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+	(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR      16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+	(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP      0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+	(((v) << 0) & BM_BCH_VERSION_STEP)
+#endif /* __ARCH_ARM___BCH_H */
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c
new file mode 100644
index 000000000000..45574391b0f0
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-event-reporting.c
@@ -0,0 +1,307 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#if defined(EVENT_REPORTING)
+
+/*
+ * This variable and module parameter controls whether the driver reports event
+ * information by printing to the console.
+ */
+
+static int report_events;
+module_param(report_events, int, 0600);
+
+/**
+ * struct event - A single record in the event trace.
+ *
+ * @time:         The time at which the event occurred.
+ * @nesting:      Indicates function call nesting.
+ * @description:  A description of the event.
+ */
+
+struct event {
+	ktime_t       time;
+	unsigned int  nesting;
+	char          *description;
+};
+
+/**
+ * The event trace.
+ *
+ * @overhead:  The delay to take a time stamp and nothing else.
+ * @nesting:   The current nesting level.
+ * @overflow:  Indicates the trace overflowed.
+ * @next:      Index of the next event to write.
+ * @events:    The array of events.
+ */
+
+#define MAX_EVENT_COUNT  (200)
+
+static struct {
+	ktime_t       overhead;
+	int           nesting;
+	int           overflow;
+	unsigned int  next;
+	struct event  events[MAX_EVENT_COUNT];
+} event_trace;
+
+/**
+ * gpmi_nfc_reset_event_trace() - Resets the event trace.
+ */
+void gpmi_nfc_reset_event_trace(void)
+{
+	event_trace.nesting  = 0;
+	event_trace.overflow = false;
+	event_trace.next     = 0;
+}
+
+/**
+ * gpmi_nfc_add_event() - Adds an event to the event trace.
+ *
+ * @description:  A description of the event.
+ * @delta:        A delta to the nesting level for this event [-1, 0, 1].
+ */
+void gpmi_nfc_add_event(char *description, int delta)
+{
+	struct event  *event;
+
+	if (!report_events)
+		return;
+
+	if (event_trace.overflow)
+		return;
+
+	if (event_trace.next >= MAX_EVENT_COUNT) {
+		event_trace.overflow = true;
+		return;
+	}
+
+	event = event_trace.events + event_trace.next;
+
+	event->time = ktime_get();
+
+	event->description = description;
+
+	if (!delta)
+		event->nesting = event_trace.nesting;
+	else if (delta < 0) {
+		event->nesting = event_trace.nesting - 1;
+		event_trace.nesting -= 2;
+	} else {
+		event->nesting = event_trace.nesting + 1;
+		event_trace.nesting += 2;
+	}
+
+	if (event_trace.nesting < 0)
+		event_trace.nesting = 0;
+
+	event_trace.next++;
+
+}
+
+/**
+ * gpmi_nfc_start_event_trace() - Starts an event trace.
+ *
+ * @description:  A description of the first event.
+ */
+void gpmi_nfc_start_event_trace(char *description)
+{
+
+	ktime_t  t0;
+	ktime_t  t1;
+
+	if (!report_events)
+		return;
+
+	gpmi_nfc_reset_event_trace();
+
+	t0 = ktime_get();
+	t1 = ktime_get();
+
+	event_trace.overhead = ktime_sub(t1, t0);
+
+	gpmi_nfc_add_event(description, 1);
+
+}
+
+/**
+ * gpmi_nfc_dump_event_trace() - Dumps the event trace.
+ */
+void gpmi_nfc_dump_event_trace(void)
+{
+	unsigned int  i;
+	time_t        seconds;
+	long          nanoseconds;
+	char          line[100];
+	int           o;
+	struct event  *first_event;
+	struct event  *last_event;
+	struct event  *matching_event;
+	struct event  *event;
+	ktime_t       delta;
+
+	/* Check if event reporting is turned off. */
+
+	if (!report_events)
+		return;
+
+	/* Print important facts about this event trace. */
+
+	pr_info("\n+----------------\n");
+
+	pr_info("|  Overhead    : [%d:%d]\n", event_trace.overhead.tv.sec,
+						event_trace.overhead.tv.nsec);
+
+	if (!event_trace.next) {
+		pr_info("|  No Events\n");
+		return;
+	}
+
+	first_event = event_trace.events;
+	last_event  = event_trace.events + (event_trace.next - 1);
+
+	delta = ktime_sub(last_event->time, first_event->time);
+	pr_info("|  Elapsed Time: [%d:%d]\n", delta.tv.sec, delta.tv.nsec);
+
+	if (event_trace.overflow)
+		pr_info("|  Overflow!\n");
+
+	/* Print the events in this history. */
+
+	for (i = 0, event = event_trace.events;
+					i < event_trace.next; i++, event++) {
+
+		/* Get the delta between this event and the previous event. */
+
+		if (!i) {
+			seconds     = 0;
+			nanoseconds = 0;
+		} else {
+			delta = ktime_sub(event[0].time, event[-1].time);
+			seconds     = delta.tv.sec;
+			nanoseconds = delta.tv.nsec;
+		}
+
+		/* Print the current event. */
+
+		o = 0;
+
+		o = snprintf(line, sizeof(line) - o, "|  [%ld:% 10ld]%*s %s",
+							seconds, nanoseconds,
+							event->nesting, "",
+							event->description);
+		/* Check if this is the last event in a nested series. */
+
+		if (i && (event[0].nesting < event[-1].nesting)) {
+
+			for (matching_event = event - 1;; matching_event--) {
+
+				if (matching_event < event_trace.events) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(event->time,
+							matching_event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" <%d:%d]", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		/* Check if this is the first event in a nested series. */
+
+		if ((i < event_trace.next - 1) &&
+				(event[0].nesting < event[1].nesting)) {
+
+			for (matching_event = event + 1;; matching_event++) {
+
+				if (matching_event >=
+					(event_trace.events+event_trace.next)) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(matching_event->time,
+								event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" [%d:%d>", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		pr_info("%s\n", line);
+
+	}
+
+	pr_info("+----------------\n");
+
+}
+
+/**
+ * gpmi_nfc_stop_event_trace() - Stops an event trace.
+ *
+ * @description:  A description of the last event.
+ */
+void gpmi_nfc_stop_event_trace(char *description)
+{
+	struct event  *event;
+
+	if (!report_events)
+		return;
+
+	/*
+	 * We want the end of the trace, no matter what happens. If the trace
+	 * has already overflowed, or is about to, just jam this event into the
+	 * last spot. Otherwise, add this event like any other.
+	 */
+
+	if (event_trace.overflow || (event_trace.next >= MAX_EVENT_COUNT)) {
+		event = event_trace.events + (MAX_EVENT_COUNT - 1);
+		event->time = ktime_get();
+		event->description = description;
+		event->nesting     = 0;
+	} else {
+		gpmi_nfc_add_event(description, -1);
+	}
+
+	gpmi_nfc_dump_event_trace();
+	gpmi_nfc_reset_event_trace();
+
+}
+
+#endif /* EVENT_REPORTING */
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h
new file mode 100644
index 000000000000..2f9fce609a34
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0      (0x00000000)
+#define HW_GPMI_CTRL0_SET  (0x00000004)
+#define HW_GPMI_CTRL0_CLR  (0x00000008)
+#define HW_GPMI_CTRL0_TOG  (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST	     0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN    0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET  0x1
+#define BM_GPMI_CTRL0_CLKGATE           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS  0x1
+#define BM_GPMI_CTRL0_RUN        0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE  0x0
+#define BV_GPMI_CTRL0_RUN__BUSY  0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN     0x10000000
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000
+#define BM_GPMI_CTRL0_UDMA           0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE    24
+#define BM_GPMI_CTRL0_COMMAND_MODE    0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+	(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH	   0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT  0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT   0x1
+#define BM_GPMI_CTRL0_LOCK_CS            0x00400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED  0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED   0x1
+#define BP_GPMI_CTRL0_CS     20
+#define BM_GPMI_CTRL0_CS     0x00300000
+#define BF_GPMI_CTRL0_CS(v)  (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS	  17
+#define BM_GPMI_CTRL0_ADDRESS	  0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA  0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE   0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE   0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	  0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED  0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED   0x1
+#define BP_GPMI_CTRL0_XFER_COUNT    0
+#define BM_GPMI_CTRL0_XFER_COUNT    0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+	(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE  (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK	 16
+#define BM_GPMI_COMPARE_MASK	 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v)  (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE    0
+#define BM_GPMI_COMPARE_REFERENCE    0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+	(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL  (0x00000020)
+#define HW_GPMI_ECCCTRL_SET  (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR  (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG  (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE	   16
+#define BM_GPMI_ECCCTRL_HANDLE	   0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)  (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2  0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD  13
+#define BM_GPMI_ECCCTRL_ECC_CMD  0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+#define BM_GPMI_ECCCTRL_ENABLE_ECC           0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE   0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE  0x0
+#define BP_GPMI_ECCCTRL_RSVD1      9
+#define BM_GPMI_ECCCTRL_RSVD1      0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)   (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK	0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK	0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+		(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY   0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7     0x080
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6     0x040
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5     0x020
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4     0x010
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3     0x008
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2     0x004
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1     0x002
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0     0x001
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2     16
+#define BM_GPMI_ECCCOUNT_RSVD2     0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v)  (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT     0
+#define BM_GPMI_ECCCOUNT_COUNT     0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS	    2
+#define BM_GPMI_PAYLOAD_ADDRESS	    0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0     0
+#define BM_GPMI_PAYLOAD_RSVD0     0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS    2
+#define BM_GPMI_AUXILIARY_ADDRESS    0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+	(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0     0
+#define BM_GPMI_AUXILIARY_RSVD0     0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1  (0x00000060)
+#define HW_GPMI_CTRL1_SET  (0x00000064)
+#define HW_GPMI_CTRL1_CLR  (0x00000068)
+#define HW_GPMI_CTRL1_TOG  (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2	24
+#define BM_GPMI_CTRL1_RSVD2	0xFF000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+		(((v) << 24) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_CE3_SEL	0x00800000
+#define BM_GPMI_CTRL1_CE2_SEL	0x00400000
+#define BM_GPMI_CTRL1_CE1_SEL	0x00200000
+#define BM_GPMI_CTRL1_CE0_SEL	0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY	0x00080000
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE	0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_BCH_MODE	0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE	17
+#define BM_GPMI_CTRL1_DLL_ENABLE	0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD	16
+#define BM_GPMI_CTRL1_HALF_PERIOD	0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+		(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE	0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_BURST_EN	0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3	0x00000080
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2	0x00000040
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1	0x00000020
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0	0x00000010
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE	0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1	24
+#define BM_GPMI_TIMING0_RSVD1	0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+		(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP	16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP	0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+		(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD	8
+#define BM_GPMI_TIMING0_DATA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP	0
+#define BM_GPMI_TIMING0_DATA_SETUP	0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+		(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1	0
+#define BM_GPMI_TIMING1_RSVD1	0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+		(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP	24
+#define BM_GPMI_TIMING2_UDMA_TRP	0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+		(((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV	16
+#define BM_GPMI_TIMING2_UDMA_ENV	0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)  \
+		(((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD	8
+#define BM_GPMI_TIMING2_UDMA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP	0
+#define BM_GPMI_TIMING2_UDMA_SETUP	0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA	0
+#define BM_GPMI_DATA_DATA	0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)	(v)
+
+/*============================================================================*/
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BM_GPMI_STAT_PRESENT	0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+#define BP_GPMI_STAT_RSVD1	12
+#define BM_GPMI_STAT_RSVD1	0x7FFFF000
+#define BF_GPMI_STAT_RSVD1(v)  \
+		(((v) << 12) & BM_GPMI_STAT_RSVD1)
+#define BP_GPMI_STAT_RDY_TIMEOUT	8
+#define BM_GPMI_STAT_RDY_TIMEOUT	0x00000F00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+		(((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_ATA_IRQ	0x00000080
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK	0x00000040
+#define BM_GPMI_STAT_FIFO_EMPTY	0x00000020
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL	0x00000010
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_DEV3_ERROR	0x00000008
+#define BM_GPMI_STAT_DEV2_ERROR	0x00000004
+#define BM_GPMI_STAT_DEV1_ERROR	0x00000002
+#define BM_GPMI_STAT_DEERROR	0x00000001
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BM_GPMI_DEBUG_READY3	0x80000000
+#define BM_GPMI_DEBUG_READY2	0x40000000
+#define BM_GPMI_DEBUG_READY1	0x20000000
+#define BM_GPMI_DEBUG_READY0	0x10000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3	0x08000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2	0x04000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1	0x02000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0	0x01000000
+#define BM_GPMI_DEBUG_SENSE3	0x00800000
+#define BM_GPMI_DEBUG_SENSE2	0x00400000
+#define BM_GPMI_DEBUG_SENSE1	0x00200000
+#define BM_GPMI_DEBUG_SENSE0	0x00100000
+#define BM_GPMI_DEBUG_DMAREQ3	0x00080000
+#define BM_GPMI_DEBUG_DMAREQ2	0x00040000
+#define BM_GPMI_DEBUG_DMAREQ1	0x00020000
+#define BM_GPMI_DEBUG_DMAREQ0	0x00010000
+#define BP_GPMI_DEBUG_CMD_END	12
+#define BM_GPMI_DEBUG_CMD_END	0x0000F000
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG_CMD_END)
+#define BP_GPMI_DEBUG_UDMA_STATE	8
+#define BM_GPMI_DEBUG_UDMA_STATE	0x00000F00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)  \
+		(((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE)
+#define BM_GPMI_DEBUG_BUSY	0x00000080
+#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG_PIN_STATE	4
+#define BM_GPMI_DEBUG_PIN_STATE	0x00000070
+#define BF_GPMI_DEBUG_PIN_STATE(v)  \
+		(((v) << 4) & BM_GPMI_DEBUG_PIN_STATE)
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG_MAIN_STATE	0
+#define BM_GPMI_DEBUG_MAIN_STATE	0x0000000F
+#define BF_GPMI_DEBUG_MAIN_STATE(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE)
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE   0xA
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR     24
+#define BM_GPMI_VERSION_MAJOR     0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v)  (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR     16
+#define BM_GPMI_VERSION_MINOR     0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP      0
+#define BM_GPMI_VERSION_STEP      0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)   (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2       (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1	16
+#define BM_GPMI_DEBUG2_RSVD1	0xFFFF0000
+#define BF_GPMI_DEBUG2_RSVD1(v)	(((v) << 16) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE	12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE	0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID	0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY	0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID	0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY	0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN	0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW	0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP     0
+#define BM_GPMI_DEBUG2_RDN_TAP     0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3       (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR	16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR	0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+		(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR	0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR	0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h
new file mode 100644
index 000000000000..dcb3b7d3fc88
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h
@@ -0,0 +1,421 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.2
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0	(0x00000000)
+#define HW_GPMI_CTRL0_SET	(0x00000004)
+#define HW_GPMI_CTRL0_CLR	(0x00000008)
+#define HW_GPMI_CTRL0_TOG	(0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST	0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN   0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE	0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN     0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN	0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN	0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS	0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED  0x1
+#define BM_GPMI_CTRL0_UDMA	0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE	24
+#define BM_GPMI_CTRL0_COMMAND_MODE	0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)  \
+		(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH	0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT  0x1
+#define BP_GPMI_CTRL0_CS	20
+#define BM_GPMI_CTRL0_CS	0x00700000
+#define BF_GPMI_CTRL0_CS(v)  \
+		(((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS	17
+#define BM_GPMI_CTRL0_ADDRESS	0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  \
+		(((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE  0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE  0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED  0x1
+#define BP_GPMI_CTRL0_XFER_COUNT	0
+#define BM_GPMI_CTRL0_XFER_COUNT	0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE	(0x00000010)
+
+#define BP_GPMI_COMPARE_MASK	16
+#define BM_GPMI_COMPARE_MASK	0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+		(((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE	0
+#define BM_GPMI_COMPARE_REFERENCE	0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v)  \
+		(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL	(0x00000020)
+#define HW_GPMI_ECCCTRL_SET	(0x00000024)
+#define HW_GPMI_ECCCTRL_CLR	(0x00000028)
+#define HW_GPMI_ECCCTRL_TOG	(0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE	16
+#define BM_GPMI_ECCCTRL_HANDLE	0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+		(((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2	0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD	13
+#define BM_GPMI_ECCCTRL_ECC_CMD	0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)  \
+		(((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC	0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE  0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1	9
+#define BM_GPMI_ECCCTRL_RSVD1	0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)  \
+		(((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK	0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK	0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+		(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2	16
+#define BM_GPMI_ECCCOUNT_RSVD2	0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+		(((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT	0
+#define BM_GPMI_ECCCOUNT_COUNT	0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS	2
+#define BM_GPMI_PAYLOAD_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0	0
+#define BM_GPMI_PAYLOAD_RSVD0	0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS	2
+#define BM_GPMI_AUXILIARY_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0	0
+#define BM_GPMI_AUXILIARY_RSVD0	0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1	(0x00000060)
+#define HW_GPMI_CTRL1_SET	(0x00000064)
+#define HW_GPMI_CTRL1_CLR	(0x00000068)
+#define HW_GPMI_CTRL1_TOG	(0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2	25
+#define BM_GPMI_CTRL1_RSVD2	0xFE000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+		(((v) << 25) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_DECOUPLE_CS	0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL	22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL	0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+		(((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1	0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN	0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY	0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE	0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE	17
+#define BM_GPMI_CTRL1_DLL_ENABLE	0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD	16
+#define BM_GPMI_CTRL1_HALF_PERIOD	0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+		(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE	0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_BURST_EN	0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST	0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v)  \
+		(((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE	0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1	24
+#define BM_GPMI_TIMING0_RSVD1	0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+		(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP	16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP	0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+		(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD	8
+#define BM_GPMI_TIMING0_DATA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP	0
+#define BM_GPMI_TIMING0_DATA_SETUP	0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+		(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1	0
+#define BM_GPMI_TIMING1_RSVD1	0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+		(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP	24
+#define BM_GPMI_TIMING2_UDMA_TRP	0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+		(((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV	16
+#define BM_GPMI_TIMING2_UDMA_ENV	0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)  \
+		(((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD	8
+#define BM_GPMI_TIMING2_UDMA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP	0
+#define BM_GPMI_TIMING2_UDMA_SETUP	0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA	0
+#define BM_GPMI_DATA_DATA	0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)	(v)
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY	24
+#define BM_GPMI_STAT_READY_BUSY	0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+		(((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT	16
+#define BM_GPMI_STAT_RDY_TIMEOUT	0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+		(((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR	0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR	0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR	0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR	0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR	0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR	0x00000400
+#define BM_GPMI_STAT_DEERROR	0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR	0x00000100
+#define BP_GPMI_STAT_RSVD1	5
+#define BM_GPMI_STAT_RSVD1	0x000000E0
+#define BF_GPMI_STAT_RSVD1(v)  \
+		(((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ	0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK	0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY	0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL	0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_PRESENT	0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END	24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END	0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+		(((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE	16
+#define BM_GPMI_DEBUG_DMA_SENSE	0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ	8
+#define BM_GPMI_DEBUG_DMAREQ	0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v)  \
+		(((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END	0
+#define BM_GPMI_DEBUG_CMD_END	0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR	24
+#define BM_GPMI_VERSION_MAJOR	0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR	16
+#define BM_GPMI_VERSION_MINOR	0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP	0
+#define BM_GPMI_VERSION_STEP	0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)  \
+		(((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2	(0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1	28
+#define BM_GPMI_DEBUG2_RSVD1	0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+		(((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE	24
+#define BM_GPMI_DEBUG2_UDMA_STATE	0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v)  \
+		(((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY	0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG2_PIN_STATE	20
+#define BM_GPMI_DEBUG2_PIN_STATE	0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v)  \
+		(((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE	16
+#define BM_GPMI_DEBUG2_MAIN_STATE	0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE   0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE	12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE	0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID	0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY	0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID	0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY	0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN	0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW	0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP	0
+#define BM_GPMI_DEBUG2_RDN_TAP	0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3	(0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR	16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR	0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+		(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR	0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR	0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h
new file mode 100644
index 000000000000..3baa9012da69
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h
@@ -0,0 +1,511 @@
+/*
+ * Freescale GPMI Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.19
+ * Template revision: 1.3
+ */
+
+#ifndef __ARCH_ARM___GPMI_H
+#define __ARCH_ARM___GPMI_H
+
+
+#define HW_GPMI_CTRL0	(0x00000000)
+#define HW_GPMI_CTRL0_SET	(0x00000004)
+#define HW_GPMI_CTRL0_CLR	(0x00000008)
+#define HW_GPMI_CTRL0_TOG	(0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN   0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN     0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS 0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED  0x1
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE      24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)  \
+	(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT  0x1
+#define BP_GPMI_CTRL0_CS      20
+#define BM_GPMI_CTRL0_CS 0x00700000
+#define BF_GPMI_CTRL0_CS(v)  \
+	(((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS      17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  \
+	(((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE  0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE  0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED  0x1
+#define BP_GPMI_CTRL0_XFER_COUNT      0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v)  \
+	(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+#define HW_GPMI_COMPARE	(0x00000010)
+
+#define BP_GPMI_COMPARE_MASK      16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+	(((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE      0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v)  \
+	(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+#define HW_GPMI_ECCCTRL	(0x00000020)
+#define HW_GPMI_ECCCTRL_SET	(0x00000024)
+#define HW_GPMI_ECCCTRL_CLR	(0x00000028)
+#define HW_GPMI_ECCCTRL_TOG	(0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE      16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+	(((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD      13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)  \
+	(((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE  0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1      9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)  \
+	(((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK      0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+	(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2      16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+	(((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT      0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  \
+	(((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS      2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+	(((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0      0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  \
+	(((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS      2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+	(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0      0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  \
+	(((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+#define HW_GPMI_CTRL1	(0x00000060)
+#define HW_GPMI_CTRL1_SET	(0x00000064)
+#define HW_GPMI_CTRL1_CLR	(0x00000068)
+#define HW_GPMI_CTRL1_TOG	(0x0000006c)
+
+#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000
+#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000
+#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000
+#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000
+#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000
+#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000
+#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000
+#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0
+#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1
+#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL      22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+	(((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1 0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD       16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY      12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+	(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL      4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v)  \
+	(((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1      24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+	(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP      16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+	(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD      8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+	(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP      0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+	(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT      16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+	(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1      0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+	(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_RSVD1      27
+#define BM_GPMI_TIMING2_RSVD1 0xF8000000
+#define BF_GPMI_TIMING2_RSVD1(v) \
+	(((v) << 27) & BM_GPMI_TIMING2_RSVD1)
+#define BP_GPMI_TIMING2_READ_LATENCY      24
+#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000
+#define BF_GPMI_TIMING2_READ_LATENCY(v)  \
+	(((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY)
+#define BP_GPMI_TIMING2_RSVD0      21
+#define BM_GPMI_TIMING2_RSVD0 0x00E00000
+#define BF_GPMI_TIMING2_RSVD0(v)  \
+	(((v) << 21) & BM_GPMI_TIMING2_RSVD0)
+#define BP_GPMI_TIMING2_CE_DELAY      16
+#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000
+#define BF_GPMI_TIMING2_CE_DELAY(v)  \
+	(((v) << 16) & BM_GPMI_TIMING2_CE_DELAY)
+#define BP_GPMI_TIMING2_PREAMBLE_DELAY      12
+#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000
+#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v)  \
+	(((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY)
+#define BP_GPMI_TIMING2_POSTAMBLE_DELAY      8
+#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00
+#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v)  \
+	(((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY)
+#define BP_GPMI_TIMING2_CMDADD_PAUSE      4
+#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0
+#define BF_GPMI_TIMING2_CMDADD_PAUSE(v)  \
+	(((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE)
+#define BP_GPMI_TIMING2_DATA_PAUSE      0
+#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F
+#define BF_GPMI_TIMING2_DATA_PAUSE(v)  \
+	(((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE)
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA      0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)   (v)
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY      24
+#define BM_GPMI_STAT_READY_BUSY 0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+	(((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT      16
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+	(((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR 0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR 0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR 0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR 0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000400
+#define BM_GPMI_STAT_DEV1_ERROR 0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR 0x00000100
+#define BP_GPMI_STAT_RSVD1      5
+#define BM_GPMI_STAT_RSVD1 0x000000E0
+#define BF_GPMI_STAT_RSVD1(v)  \
+	(((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_PRESENT 0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END      24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+	(((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE      16
+#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v)  \
+	(((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ      8
+#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v)  \
+	(((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END      0
+#define BM_GPMI_DEBUG_CMD_END 0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+	(((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR      24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+	(((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR      16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  \
+	(((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP      0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)  \
+	(((v) << 0) & BM_GPMI_VERSION_STEP)
+
+#define HW_GPMI_DEBUG2	(0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1      28
+#define BM_GPMI_DEBUG2_RSVD1 0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+	(((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE      24
+#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v)  \
+	(((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY 0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG2_PIN_STATE      20
+#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v)  \
+	(((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE      16
+#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v)  \
+	(((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE   0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE      12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+	(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP      0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  \
+	(((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+#define HW_GPMI_DEBUG3	(0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR      16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+	(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR      0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+	(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+#define HW_GPMI_READ_DDR_DLL_CTRL	(0x00000100)
+
+#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT      28
+#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000
+#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) \
+	(((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT)
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT      20
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v)  \
+	(((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT)
+#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1      18
+#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000
+#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v)  \
+	(((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1)
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL      10
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v)  \
+	(((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL)
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200
+#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100
+#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET      3
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v)  \
+	(((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET)
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004
+#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002
+#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001
+
+#define HW_GPMI_WRITE_DDR_DLL_CTRL	(0x00000110)
+
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT      28
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) \
+	(((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT      20
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v)  \
+	(((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1      18
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v)  \
+	(((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL      10
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v)  \
+	(((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL)
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET      3
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v)  \
+	(((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET)
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001
+
+#define HW_GPMI_READ_DDR_DLL_STS	(0x00000120)
+
+#define BP_GPMI_READ_DDR_DLL_STS_RSVD1      25
+#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000
+#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) \
+	(((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1)
+#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL      17
+#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000
+#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v)  \
+	(((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL)
+#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000
+#define BP_GPMI_READ_DDR_DLL_STS_RSVD0      9
+#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00
+#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v)  \
+	(((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0)
+#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL      1
+#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE
+#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v)  \
+	(((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL)
+#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001
+
+#define HW_GPMI_WRITE_DDR_DLL_STS	(0x00000130)
+
+#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1      25
+#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000
+#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) \
+	(((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1)
+#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL      17
+#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000
+#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v)  \
+	(((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL)
+#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000
+#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0      9
+#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00
+#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v)  \
+	(((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0)
+#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL      1
+#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE
+#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v)  \
+	(((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL)
+#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001
+#endif /* __ARCH_ARM___GPMI_H */
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c
new file mode 100644
index 000000000000..b38d653a21fd
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c
@@ -0,0 +1,1037 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * gpmi_nfc_bch_isr - BCH interrupt service routine.
+ *
+ * @interrupt_number:  The interrupt number.
+ * @cookie:            A cookie that contains a pointer to the owning device
+ *                     data structure.
+ */
+irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie)
+{
+	struct gpmi_nfc_data  *this      = cookie;
+	struct nfc_hal        *nfc       =  this->nfc;
+
+	gpmi_nfc_add_event("> gpmi_nfc_bch_isr", 1);
+
+	/* Clear the interrupt. */
+
+	nfc->clear_bch(this);
+
+	/* Release the base level. */
+
+	complete(&(nfc->bch_done));
+
+	/* Return success. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_bch_isr", -1);
+
+	return IRQ_HANDLED;
+
+}
+
+/**
+ * gpmi_nfc_dma_isr - DMA interrupt service routine.
+ *
+ * @interrupt_number:  The interrupt number.
+ * @cookie:            A cookie that contains a pointer to the owning device
+ *                     data structure.
+ */
+irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie)
+{
+	struct gpmi_nfc_data  *this = cookie;
+	struct nfc_hal        *nfc  =  this->nfc;
+
+	gpmi_nfc_add_event("> gpmi_nfc_dma_isr", 1);
+
+	/* Acknowledge the DMA channel's interrupt. */
+
+	mxs_dma_ack_irq(nfc->isr_dma_channel);
+
+	/* Release the base level. */
+
+	complete(&(nfc->dma_done));
+
+	/* Return success. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_dma_isr", -1);
+
+	return IRQ_HANDLED;
+
+}
+
+/**
+ * gpmi_nfc_dma_init() - Initializes DMA.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_dma_init(struct gpmi_nfc_data *this)
+{
+	struct device   *dev = this->dev;
+	struct nfc_hal  *nfc = this->nfc;
+	int             i;
+	int             error;
+
+	/* Allocate the DMA descriptors. */
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) {
+		nfc->dma_descriptors[i] = mxs_dma_alloc_desc();
+		if (!nfc->dma_descriptors[i]) {
+			dev_err(dev, "Cannot allocate all DMA descriptors.\n");
+			error = -ENOMEM;
+			goto exit_descriptor_allocation;
+		}
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+	/* Control arrives here when something has gone wrong. */
+
+exit_descriptor_allocation:
+	while (--i >= 0)
+		mxs_dma_free_desc(this->nfc->dma_descriptors[i]);
+
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_dma_exit() - Shuts down DMA.
+ *
+ * @this:  Per-device data.
+ */
+void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this)
+{
+	struct nfc_hal  *nfc = this->nfc;
+	int             i;
+
+	/* Free the DMA descriptors. */
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++)
+		mxs_dma_free_desc(nfc->dma_descriptors[i]);
+
+}
+
+/**
+ * gpmi_nfc_set_geometry() - Shared NFC geometry configuration.
+ *
+ * In principle, computing the NFC geometry is version-specific. However, at
+ * this writing all, versions share the same page model, so this code can also
+ * be shared.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this)
+{
+	struct device             *dev      = this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nfc_geometry       *geometry = &this->nfc_geometry;
+	struct boot_rom_helper    *rom      =  this->rom;
+	unsigned int              metadata_size;
+	unsigned int              status_size;
+	unsigned int              chunk_data_size_in_bits;
+	unsigned int              chunk_ecc_size_in_bits;
+	unsigned int              chunk_total_size_in_bits;
+	unsigned int              block_mark_chunk_number;
+	unsigned int              block_mark_chunk_bit_offset;
+	unsigned int              block_mark_bit_offset;
+
+	/* At this writing, we support only BCH. */
+
+	geometry->ecc_algorithm = "BCH";
+
+	/*
+	 * We always choose a metadata size of 10. Don't try to make sense of
+	 * it -- this is really only for historical compatibility.
+	 */
+
+	geometry->metadata_size_in_bytes = 10;
+
+	/*
+	 * At this writing, we always use 512-byte ECC chunks. Later hardware
+	 * will be able to support larger chunks, which will cause this
+	 * decision to move into version-specific code.
+	 */
+
+	geometry->ecc_chunk_size_in_bytes = 512;
+
+	/* Compute the page size based on the physical geometry. */
+
+	geometry->page_size_in_bytes =
+			physical->page_data_size_in_bytes +
+			physical->page_oob_size_in_bytes  ;
+
+	/*
+	 * Compute the total number of ECC chunks in a page. This includes the
+	 * slightly larger chunk at the beginning of the page, which contains
+	 * both data and metadata.
+	 */
+
+	geometry->ecc_chunk_count =
+			  physical->page_data_size_in_bytes /
+			/*---------------------------------*/
+			  geometry->ecc_chunk_size_in_bytes;
+
+	/*
+	 * We use the same ECC strength for all chunks, including the first one.
+	 * At this writing, we base our ECC strength choice entirely on the
+	 * the physical page geometry. In the future, this should be changed to
+	 * pay attention to the detailed device information we gathered earlier.
+	 */
+
+	geometry->ecc_strength = 0;
+
+	switch (physical->page_data_size_in_bytes) {
+	case 2048:
+		geometry->ecc_strength = 8;
+		break;
+	case 4096:
+		switch (physical->page_oob_size_in_bytes) {
+		case 128:
+			geometry->ecc_strength = 8;
+			break;
+		case 218:
+			geometry->ecc_strength = 16;
+			break;
+		}
+		break;
+	}
+
+	/* Check if we were able to figure out the ECC strength. */
+
+	if (!geometry->ecc_strength) {
+		dev_err(dev, "Unsupported page geometry: %u:%u\n",
+			physical->page_data_size_in_bytes,
+			physical->page_oob_size_in_bytes);
+		return !0;
+	}
+
+	/*
+	 * The payload buffer contains the data area of a page. The ECC engine
+	 * only needs what's required to hold the data.
+	 */
+
+	geometry->payload_size_in_bytes = physical->page_data_size_in_bytes;
+
+	/*
+	 * In principle, computing the auxiliary buffer geometry is NFC
+	 * version-specific. However, at this writing, all versions share the
+	 * same model, so this code can also be shared.
+	 *
+	 * The auxiliary buffer contains the metadata and the ECC status. The
+	 * metadata is padded to the nearest 32-bit boundary. The ECC status
+	 * contains one byte for every ECC chunk, and is also padded to the
+	 * nearest 32-bit boundary.
+	 */
+
+	metadata_size = (geometry->metadata_size_in_bytes + 0x3) & ~0x3;
+	status_size   = (geometry->ecc_chunk_count        + 0x3) & ~0x3;
+
+	geometry->auxiliary_size_in_bytes = metadata_size + status_size;
+	geometry->auxiliary_status_offset = metadata_size;
+
+	/* Check if we're going to do block mark swapping. */
+
+	if (!rom->swap_block_mark)
+		return 0;
+
+	/*
+	 * If control arrives here, we're doing block mark swapping, so we need
+	 * to compute the byte and bit offsets of the physical block mark within
+	 * the ECC-based view of the page data. In principle, this isn't a
+	 * difficult computation -- but it's very important and it's easy to get
+	 * it wrong, so we do it carefully.
+	 *
+	 * Note that this calculation is simpler because we use the same ECC
+	 * strength for all chunks, including the zero'th one, which contains
+	 * the metadata. The calculation would be slightly more complicated
+	 * otherwise.
+	 *
+	 * We start by computing the physical bit offset of the block mark. We
+	 * then subtract the number of metadata and ECC bits appearing before
+	 * the mark to arrive at its bit offset within the data alone.
+	 */
+
+	/* Compute some important facts about chunk geometry. */
+
+	chunk_data_size_in_bits = geometry->ecc_chunk_size_in_bytes * 8;
+	chunk_ecc_size_in_bits  = geometry->ecc_strength * 13;
+
+	chunk_total_size_in_bits =
+			chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+	/* Compute the bit offset of the block mark within the physical page. */
+
+	block_mark_bit_offset = physical->page_data_size_in_bytes * 8;
+
+	/* Subtract the metadata bits. */
+
+	block_mark_bit_offset -= geometry->metadata_size_in_bytes * 8;
+
+	/*
+	 * Compute the chunk number (starting at zero) in which the block mark
+	 * appears.
+	 */
+
+	block_mark_chunk_number =
+			block_mark_bit_offset / chunk_total_size_in_bits;
+
+	/*
+	 * Compute the bit offset of the block mark within its chunk, and
+	 * validate it.
+	 */
+
+	block_mark_chunk_bit_offset =
+		block_mark_bit_offset -
+			(block_mark_chunk_number * chunk_total_size_in_bits);
+
+	if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) {
+
+		/*
+		 * If control arrives here, the block mark actually appears in
+		 * the ECC bits of this chunk. This wont' work.
+		 */
+
+		dev_err(dev, "Unsupported page geometry "
+					"(block mark in ECC): %u:%u\n",
+					physical->page_data_size_in_bytes,
+					physical->page_oob_size_in_bytes);
+		return !0;
+
+	}
+
+	/*
+	 * Now that we know the chunk number in which the block mark appears,
+	 * we can subtract all the ECC bits that appear before it.
+	 */
+
+	block_mark_bit_offset -=
+			block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+	/*
+	 * We now know the absolute bit offset of the block mark within the
+	 * ECC-based data. We can now compute the byte offset and the bit
+	 * offset within the byte.
+	 */
+
+	geometry->block_mark_byte_offset = block_mark_bit_offset / 8;
+	geometry->block_mark_bit_offset  = block_mark_bit_offset % 8;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/*
+ * This code is useful for debugging.
+ */
+
+/*#define DUMP_DMA_CONTEXT*/
+
+#if (defined DUMP_DMA_CONTEXT)
+
+int dump_dma_context_flag;
+
+void dump_dma_context(struct gpmi_nfc_data *this, char *title)
+{
+
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	void                 *q;
+	uint32_t             *p;
+	unsigned int         i;
+	unsigned int         j;
+
+	if (!dump_dma_context_flag)
+		return;
+
+	pr_info("%s\n", title);
+	pr_info("======\n");
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  Descriptors\n");
+	pr_info("  -----------\n");
+	{
+
+	for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++, d++) {
+		pr_info("    #%u\n", i);
+		pr_info("    --\n");
+		pr_info("    Physical Address: 0x%08x\n" , (*d)->address);
+		pr_info("    Next            : 0x%08lx\n", (*d)->cmd.next);
+		pr_info("    Command         : 0x%08lx\n", (*d)->cmd.cmd.data);
+		pr_info("    Buffer          : 0x%08x\n" , (*d)->cmd.address);
+		for (j = 0; j < 6; j++)
+			pr_info("    PIO[%u]          : 0x%08lx\n",
+						j, (*d)->cmd.pio_words[j]);
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  DMA\n");
+	pr_info("  ---\n");
+	{
+	void  *DMA = IO_ADDRESS(APBH_DMA_PHYS_ADDR);
+
+	p = q = DMA + 0x200;
+
+	for (i = 0; i < 7; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - DMA, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  GPMI\n");
+	pr_info("  ----\n");
+	{
+	void  *GPMI = resources->gpmi_regs;
+
+	p = q = GPMI;
+
+	for (i = 0; i < 33; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - GPMI, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+	/*--------------------------------------------------------------------*/
+
+	pr_info("  BCH\n");
+	pr_info("  ---\n");
+	{
+	void  *BCH = resources->bch_regs;
+
+	p = q = BCH;
+
+	for (i = 0; i < 22; i++) {
+		pr_info("    [0x%03x] 0x%08x\n", q - BCH, *p);
+		q += 0x10;
+		p = q;
+	}
+
+	}
+	pr_info("\n");
+
+}
+
+#endif
+
+/**
+ * gpmi_nfc_dma_go - Run a DMA channel.
+ *
+ * @this:         Per-device data structure.
+ * @dma_channel:  The DMA channel we're going to use.
+ */
+int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int  dma_channel)
+{
+	struct device     *dev       =  this->dev;
+	struct resources  *resources = &this->resources;
+	struct nfc_hal    *nfc       =  this->nfc;
+	unsigned long     timeout;
+	int               error;
+	LIST_HEAD(tmp_desc_list);
+
+	gpmi_nfc_add_event("> gpmi_nfc_dma_go", 1);
+
+	/* Get ready... */
+
+	nfc->isr_dma_channel = dma_channel;
+	init_completion(&nfc->dma_done);
+	mxs_dma_enable_irq(dma_channel, 1);
+
+	/* Go! */
+
+	#if defined(DUMP_DMA_CONTEXT)
+		dump_dma_context(this, "BEFORE");
+	#endif
+
+	mxs_dma_enable(dma_channel);
+
+	/* Wait for it to finish. */
+
+	timeout = wait_for_completion_timeout(&nfc->dma_done,
+							msecs_to_jiffies(1000));
+
+	#if defined(DUMP_DMA_CONTEXT)
+		dump_dma_context(this, "AFTER");
+	#endif
+
+	error = (!timeout) ? -ETIMEDOUT : 0;
+
+	if (error) {
+		dev_err(dev, "[%s] Chip: %u, DMA Channel: %d, Error %d\n",
+			__func__, dma_channel - resources->dma_low_channel,
+			dma_channel, error);
+		gpmi_nfc_add_event("...DMA timed out", 0);
+	} else
+		gpmi_nfc_add_event("...Finished DMA successfully", 0);
+
+	/* Clear out the descriptors we just ran. */
+
+	mxs_dma_cooked(dma_channel, &tmp_desc_list);
+
+	/* Shut the DMA channel down. */
+
+	mxs_dma_reset(dma_channel);
+	mxs_dma_enable_irq(dma_channel, 0);
+	mxs_dma_disable(dma_channel);
+
+	/* Return. */
+
+	gpmi_nfc_add_event("< gpmi_nfc_dma_go", -1);
+
+	return error;
+
+}
+
+/**
+ * ns_to_cycles - Converts time in nanoseconds to cycles.
+ *
+ * @ntime:   The time, in nanoseconds.
+ * @period:  The cycle period, in nanoseconds.
+ * @min:     The minimum allowable number of cycles.
+ */
+static unsigned int ns_to_cycles(unsigned int time,
+					unsigned int period, unsigned int min)
+{
+	unsigned int k;
+
+	/*
+	 * Compute the minimum number of cycles that entirely contain the
+	 * given time.
+	 */
+
+	k = (time + period - 1) / period;
+
+	return max(k, min);
+
+}
+
+/**
+ * gpmi_compute_hardware_timing - Apply timing to current hardware conditions.
+ *
+ * @this:             Per-device data.
+ * @hardware_timing:  A pointer to a hardware timing structure that will receive
+ *                    the results of our calculations.
+ */
+int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+					struct gpmi_nfc_hardware_timing *hw)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct nfc_hal                 *nfc      =  this->nfc;
+	struct gpmi_nfc_timing         target    = nfc->timing;
+	bool           improved_timing_is_available;
+	unsigned long  clock_frequency_in_hz;
+	unsigned int   clock_period_in_ns;
+	bool           dll_use_half_periods;
+	unsigned int   dll_delay_shift;
+	unsigned int   max_sample_delay_in_ns;
+	unsigned int   address_setup_in_cycles;
+	unsigned int   data_setup_in_ns;
+	unsigned int   data_setup_in_cycles;
+	unsigned int   data_hold_in_cycles;
+	int            ideal_sample_delay_in_ns;
+	unsigned int   sample_delay_factor;
+	int            tEYE;
+	unsigned int   min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
+	unsigned int   max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
+
+	/*
+	 * If there are multiple chips, we need to relax the timings to allow
+	 * for signal distortion due to higher capacitance.
+	 */
+
+	if (physical->chip_count > 2) {
+		target.data_setup_in_ns    += 10;
+		target.data_hold_in_ns     += 10;
+		target.address_setup_in_ns += 10;
+	} else if (physical->chip_count > 1) {
+		target.data_setup_in_ns    += 5;
+		target.data_hold_in_ns     += 5;
+		target.address_setup_in_ns += 5;
+	}
+
+	/* Check if improved timing information is available. */
+
+	improved_timing_is_available =
+		(target.tREA_in_ns  >= 0) &&
+		(target.tRLOH_in_ns >= 0) &&
+		(target.tRHOH_in_ns >= 0) ;
+
+	/* Inspect the clock. */
+
+	clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+	clock_period_in_ns    = 1000000000 / clock_frequency_in_hz;
+
+	/*
+	 * The NFC quantizes setup and hold parameters in terms of clock cycles.
+	 * Here, we quantize the setup and hold timing parameters to the
+	 * next-highest clock period to make sure we apply at least the
+	 * specified times.
+	 *
+	 * For data setup and data hold, the hardware interprets a value of zero
+	 * as the largest possible delay. This is not what's intended by a zero
+	 * in the input parameter, so we impose a minimum of one cycle.
+	 */
+
+	data_setup_in_cycles    = ns_to_cycles(target.data_setup_in_ns,
+							clock_period_in_ns, 1);
+	data_hold_in_cycles     = ns_to_cycles(target.data_hold_in_ns,
+							clock_period_in_ns, 1);
+	address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
+							clock_period_in_ns, 0);
+
+	/*
+	 * The clock's period affects the sample delay in a number of ways:
+	 *
+	 * (1) The NFC HAL tells us the maximum clock period the sample delay
+	 *     DLL can tolerate. If the clock period is greater than half that
+	 *     maximum, we must configure the DLL to be driven by half periods.
+	 *
+	 * (2) We need to convert from an ideal sample delay, in ns, to a
+	 *     "sample delay factor," which the NFC uses. This factor depends on
+	 *     whether we're driving the DLL with full or half periods.
+	 *     Paraphrasing the reference manual:
+	 *
+	 *         AD = SDF x 0.125 x RP
+	 *
+	 * where:
+	 *
+	 *     AD   is the applied delay, in ns.
+	 *     SDF  is the sample delay factor, which is dimensionless.
+	 *     RP   is the reference period, in ns, which is a full clock period
+	 *          if the DLL is being driven by full periods, or half that if
+	 *          the DLL is being driven by half periods.
+	 *
+	 * Let's re-arrange this in a way that's more useful to us:
+	 *
+	 *                        8
+	 *         SDF  =  AD x ----
+	 *                       RP
+	 *
+	 * The reference period is either the clock period or half that, so this
+	 * is:
+	 *
+	 *                        8       AD x DDF
+	 *         SDF  =  AD x -----  =  --------
+	 *                      f x P        P
+	 *
+	 * where:
+	 *
+	 *       f  is 1 or 1/2, depending on how we're driving the DLL.
+	 *       P  is the clock period.
+	 *     DDF  is the DLL Delay Factor, a dimensionless value that
+	 *          incorporates all the constants in the conversion.
+	 *
+	 * DDF will be either 8 or 16, both of which are powers of two. We can
+	 * reduce the cost of this conversion by using bit shifts instead of
+	 * multiplication or division. Thus:
+	 *
+	 *                 AD << DDS
+	 *         SDF  =  ---------
+	 *                     P
+	 *
+	 *     or
+	 *
+	 *         AD  =  (SDF >> DDS) x P
+	 *
+	 * where:
+	 *
+	 *     DDS  is the DLL Delay Shift, the logarithm to base 2 of the DDF.
+	 */
+
+	if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
+		dll_use_half_periods = true;
+		dll_delay_shift      = 3 + 1;
+	} else {
+		dll_use_half_periods = false;
+		dll_delay_shift      = 3;
+	}
+
+	/*
+	 * Compute the maximum sample delay the NFC allows, under current
+	 * conditions. If the clock is running too slowly, no sample delay is
+	 * possible.
+	 */
+
+	if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
+		max_sample_delay_in_ns = 0;
+	else {
+
+		/*
+		 * Compute the delay implied by the largest sample delay factor
+		 * the NFC allows.
+		 */
+
+		max_sample_delay_in_ns =
+			(nfc->max_sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+		/*
+		 * Check if the implied sample delay larger than the NFC
+		 * actually allows.
+		 */
+
+		if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
+			max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
+
+	}
+
+	/*
+	 * Check if improved timing information is available. If not, we have to
+	 * use a less-sophisticated algorithm.
+	 */
+
+	if (!improved_timing_is_available) {
+
+		/*
+		 * Fold the read setup time required by the NFC into the ideal
+		 * sample delay.
+		 */
+
+		ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
+						nfc->internal_data_setup_in_ns;
+
+		/*
+		 * The ideal sample delay may be greater than the maximum
+		 * allowed by the NFC. If so, we can trade off sample delay time
+		 * for more data setup time.
+		 *
+		 * In each iteration of the following loop, we add a cycle to
+		 * the data setup time and subtract a corresponding amount from
+		 * the sample delay until we've satisified the constraints or
+		 * can't do any better.
+		 */
+
+		while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+			data_setup_in_cycles++;
+			ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+			if (ideal_sample_delay_in_ns < 0)
+				ideal_sample_delay_in_ns = 0;
+
+		}
+
+		/*
+		 * Compute the sample delay factor that corresponds most closely
+		 * to the ideal sample delay. If the result is too large for the
+		 * NFC, use the maximum value.
+		 *
+		 * Notice that we use the ns_to_cycles function to compute the
+		 * sample delay factor. We do this because the form of the
+		 * computation is the same as that for calculating cycles.
+		 */
+
+		sample_delay_factor =
+			ns_to_cycles(
+				ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+		if (sample_delay_factor > nfc->max_sample_delay_factor)
+			sample_delay_factor = nfc->max_sample_delay_factor;
+
+		/* Skip to the part where we return our results. */
+
+		goto return_results;
+
+	}
+
+	/*
+	 * If control arrives here, we have more detailed timing information,
+	 * so we can use a better algorithm.
+	 */
+
+	/*
+	 * Fold the read setup time required by the NFC into the maximum
+	 * propagation delay.
+	 */
+
+	max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
+
+	/*
+	 * Earlier, we computed the number of clock cycles required to satisfy
+	 * the data setup time. Now, we need to know the actual nanoseconds.
+	 */
+
+	data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
+
+	/*
+	 * Compute tEYE, the width of the data eye when reading from the NAND
+	 * Flash. The eye width is fundamentally determined by the data setup
+	 * time, perturbed by propagation delays and some characteristics of the
+	 * NAND Flash device.
+	 *
+	 * start of the eye = max_prop_delay + tREA
+	 * end of the eye   = min_prop_delay + tRHOH + data_setup
+	 */
+
+	tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
+							(int)data_setup_in_ns;
+
+	tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
+
+	/*
+	 * The eye must be open. If it's not, we can try to open it by
+	 * increasing its main forcer, the data setup time.
+	 *
+	 * In each iteration of the following loop, we increase the data setup
+	 * time by a single clock cycle. We do this until either the eye is
+	 * open or we run into NFC limits.
+	 */
+
+	while ((tEYE <= 0) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+	}
+
+	/*
+	 * When control arrives here, the eye is open. The ideal time to sample
+	 * the data is in the center of the eye:
+	 *
+	 *     end of the eye + start of the eye
+	 *     ---------------------------------  -  data_setup
+	 *                    2
+	 *
+	 * After some algebra, this simplifies to the code immediately below.
+	 */
+
+	ideal_sample_delay_in_ns =
+		((int)max_prop_delay_in_ns +
+			(int)target.tREA_in_ns +
+				(int)min_prop_delay_in_ns +
+					(int)target.tRHOH_in_ns -
+						(int)data_setup_in_ns) >> 1;
+
+	/*
+	 * The following figure illustrates some aspects of a NAND Flash read:
+	 *
+	 *
+	 *           __                   _____________________________________
+	 * RDN         \_________________/
+	 *
+	 *                                         <---- tEYE ----->
+	 *                                        /-----------------\
+	 * Read Data ----------------------------<                   >---------
+	 *                                        \-----------------/
+	 *             ^                 ^                 ^              ^
+	 *             |                 |                 |              |
+	 *             |<--Data Setup -->|<--Delay Time -->|              |
+	 *             |                 |                 |              |
+	 *             |                 |                                |
+	 *             |                 |<--   Quantized Delay Time   -->|
+	 *             |                 |                                |
+	 *
+	 *
+	 * We have some issues we must now address:
+	 *
+	 * (1) The *ideal* sample delay time must not be negative. If it is, we
+	 *     jam it to zero.
+	 *
+	 * (2) The *ideal* sample delay time must not be greater than that
+	 *     allowed by the NFC. If it is, we can increase the data setup
+	 *     time, which will reduce the delay between the end of the data
+	 *     setup and the center of the eye. It will also make the eye
+	 *     larger, which might help with the next issue...
+	 *
+	 * (3) The *quantized* sample delay time must not fall either before the
+	 *     eye opens or after it closes (the latter is the problem
+	 *     illustrated in the above figure).
+	 */
+
+	/* Jam a negative ideal sample delay to zero. */
+
+	if (ideal_sample_delay_in_ns < 0)
+		ideal_sample_delay_in_ns = 0;
+
+	/*
+	 * Extend the data setup as needed to reduce the ideal sample delay
+	 * below the maximum permitted by the NFC.
+	 */
+
+	while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+
+		/*
+		 * Decrease the ideal sample delay by one half cycle, to keep it
+		 * in the middle of the eye.
+		 */
+		ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+		/* Jam a negative ideal sample delay to zero. */
+		if (ideal_sample_delay_in_ns < 0)
+			ideal_sample_delay_in_ns = 0;
+
+	}
+
+	/*
+	 * Compute the sample delay factor that corresponds to the ideal sample
+	 * delay. If the result is too large, then use the maximum allowed
+	 * value.
+	 *
+	 * Notice that we use the ns_to_cycles function to compute the sample
+	 * delay factor. We do this because the form of the computation is the
+	 * same as that for calculating cycles.
+	 */
+
+	sample_delay_factor =
+		ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+	if (sample_delay_factor > nfc->max_sample_delay_factor)
+		sample_delay_factor = nfc->max_sample_delay_factor;
+
+	/*
+	 * These macros conveniently encapsulate a computation we'll use to
+	 * continuously evaluate whether or not the data sample delay is inside
+	 * the eye.
+	 */
+
+	#define IDEAL_DELAY  ((int) ideal_sample_delay_in_ns)
+
+	#define QUANTIZED_DELAY  \
+		((int) ((sample_delay_factor * clock_period_in_ns) >> \
+							dll_delay_shift))
+
+	#define DELAY_ERROR  (abs(QUANTIZED_DELAY - IDEAL_DELAY))
+
+	#define SAMPLE_IS_NOT_WITHIN_THE_EYE  (DELAY_ERROR > (tEYE >> 1))
+
+	/*
+	 * While the quantized sample time falls outside the eye, reduce the
+	 * sample delay or extend the data setup to move the sampling point back
+	 * toward the eye. Do not allow the number of data setup cycles to
+	 * exceed the maximum allowed by the NFC.
+	 */
+
+	while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
+			(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+		/*
+		 * If control arrives here, the quantized sample delay falls
+		 * outside the eye. Check if it's before the eye opens, or after
+		 * the eye closes.
+		 */
+
+		if (QUANTIZED_DELAY > IDEAL_DELAY) {
+
+			/*
+			 * If control arrives here, the quantized sample delay
+			 * falls after the eye closes. Decrease the quantized
+			 * delay time and then go back to re-evaluate.
+			 */
+
+			if (sample_delay_factor != 0)
+				sample_delay_factor--;
+
+			continue;
+
+		}
+
+		/*
+		 * If control arrives here, the quantized sample delay falls
+		 * before the eye opens. Shift the sample point by increasing
+		 * data setup time. This will also make the eye larger.
+		 */
+
+		/* Give a cycle to data setup. */
+		data_setup_in_cycles++;
+		/* Synchronize the data setup time with the cycles. */
+		data_setup_in_ns += clock_period_in_ns;
+		/* Adjust tEYE accordingly. */
+		tEYE += clock_period_in_ns;
+
+		/*
+		 * Decrease the ideal sample delay by one half cycle, to keep it
+		 * in the middle of the eye.
+		 */
+		ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+		/* ...and one less period for the delay time. */
+		ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+		/* Jam a negative ideal sample delay to zero. */
+		if (ideal_sample_delay_in_ns < 0)
+			ideal_sample_delay_in_ns = 0;
+
+		/*
+		 * We have a new ideal sample delay, so re-compute the quantized
+		 * delay.
+		 */
+
+		sample_delay_factor =
+			ns_to_cycles(
+				ideal_sample_delay_in_ns << dll_delay_shift,
+							clock_period_in_ns, 0);
+
+		if (sample_delay_factor > nfc->max_sample_delay_factor)
+			sample_delay_factor = nfc->max_sample_delay_factor;
+
+	}
+
+	/* Control arrives here when we're ready to return our results. */
+
+return_results:
+
+	hw->data_setup_in_cycles    = data_setup_in_cycles;
+	hw->data_hold_in_cycles     = data_hold_in_cycles;
+	hw->address_setup_in_cycles = address_setup_in_cycles;
+	hw->use_half_periods        = dll_use_half_periods;
+	hw->sample_delay_factor     = sample_delay_factor;
+
+	/* Return success. */
+
+	return 0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c
new file mode 100644
index 000000000000..294bb9409581
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c
@@ -0,0 +1,924 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#include "gpmi-nfc-gpmi-regs-v0.h"
+#include "gpmi-nfc-bch-regs-v0.h"
+
+/**
+ * init() - Initializes the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static int init(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	int               error;
+
+	/* Initialize DMA. */
+
+	error = gpmi_nfc_dma_init(this);
+
+	if (error)
+		return error;
+
+	/* Enable the clock. It will stay on until the end of set_geometry(). */
+
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+
+	mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * set_geometry() - Configures the NFC geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+
+	if (gpmi_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work. If you try to soft reset the BCH block, it becomes
+	 * unusable until the next hard reset.
+	 */
+
+	mxs_reset_block(resources->bch_regs, true);
+
+	/* Configure layout 0. */
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * set_timing() - Configures the NFC timing.
+ *
+ * @this:    Per-device data.
+ * @timing:  The timing of interest.
+ */
+static int set_timing(struct gpmi_nfc_data *this,
+					const struct gpmi_nfc_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	/* Accept the new timing. */
+
+	nfc->timing = *timing;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * exit() - Shuts down the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static void exit(struct gpmi_nfc_data *this)
+{
+	gpmi_nfc_dma_exit(this);
+}
+
+/**
+ * begin() - Begin NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	struct gpmi_nfc_hardware_timing  hw;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	unsigned int                     clock_period_in_ns;
+	uint32_t                         register_image;
+	unsigned int                     dll_wait_time_in_us;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Get the timing information we need. */
+
+	nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+	gpmi_nfc_compute_hardware_timing(this, &hw);
+
+	/* Set up all the simple timing parameters. */
+
+	register_image =
+		BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+		BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
+		BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
+
+	__raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+	/*
+	 * HEY - PAY ATTENTION!
+	 *
+	 * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+	 */
+
+	__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Clear out the DLL control fields. */
+
+	__raw_writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
+	__raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* If no sample delay is called for, return immediately. */
+
+	if (!hw.sample_delay_factor)
+		return;
+
+	/* Configure the HALF_PERIOD flag. */
+
+	if (hw.use_half_periods)
+		__raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+						gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Set the delay factor. */
+
+	__raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+						gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Enable the DLL. */
+
+	__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/*
+	 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+	 * we can use the GPMI.
+	 *
+	 * Calculate the amount of time we need to wait, in microseconds.
+	 */
+
+	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+	if (!dll_wait_time_in_us)
+		dll_wait_time_in_us = 1;
+
+	/* Wait for the DLL to settle. */
+
+	udelay(dll_wait_time_in_us);
+
+}
+
+/**
+ * end() - End NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * clear_bch() - Clears a BCH interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
+				resources->bch_regs + HW_BCH_CTRL_CLR);
+
+}
+
+/**
+ * is_ready() - Returns the ready/busy status of the given chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip of interest.
+ */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+
+	mask = BM_GPMI_DEBUG_READY0 << chip;
+
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+
+	return !!(register_image & mask);
+
+}
+
+/**
+ * send_command() - Sends a command and associated addresses.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the command bytes.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_command(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that sends out the command. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BM_GPMI_CTRL0_ADDRESS_INCREMENT          |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_data() - Sends data to the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the data.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that writes a buffer out. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_data() - Receives data from the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that will receive the data.
+ * @length:  The number of bytes to read.
+ */
+static int read_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that reads the data. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_WRITE;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/*
+	 * A DMA descriptor that waits for the command to end and the chip to
+	 * become ready.
+	 *
+	 * I think we actually should *not* be waiting for the chip to become
+	 * ready because, after all, we don't care. I think the original code
+	 * did that and no one has re-thought it yet.
+	 */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_page() - Sends a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int send_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that does an ECC page read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	(*d)->cmd.pio_words[1] = 0;
+
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_page() - Reads a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int read_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* Wait for the chip to report ready. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Enable the BCH block and read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC 	         |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Disable the BCH block */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Deassert the NAND lock and interrupt. */
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 0;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 0;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+
+struct nfc_hal  gpmi_nfc_hal_v0 = {
+	.version                     = 0,
+	.description                 = "4-chip GPMI and BCH",
+	.max_chip_count              = 4,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.send_data                   = send_data,
+	.read_data                   = read_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c
new file mode 100644
index 000000000000..962efe686853
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c
@@ -0,0 +1,866 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#include "gpmi-nfc-gpmi-regs-v1.h"
+#include "gpmi-nfc-bch-regs-v1.h"
+
+/**
+ * init() - Initializes the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static int init(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	int               error;
+
+	/* Initialize DMA. */
+
+	error = gpmi_nfc_dma_init(this);
+
+	if (error)
+		return error;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+
+	mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * set_geometry() - Configures the NFC geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+
+	if (gpmi_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work and the version 1 BCH block is similar enough that we
+	 * suspect the same (though this has not been officially tested). If you
+	 * try to soft reset a version 0 BCH block, it becomes unusable until
+	 * the next hard reset.
+	 */
+
+	mxs_reset_block(resources->bch_regs, true);
+
+	/* Configure layout 0. */
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * set_timing() - Configures the NFC timing.
+ *
+ * @this:    Per-device data.
+ * @timing:  The timing of interest.
+ */
+static int set_timing(struct gpmi_nfc_data *this,
+					const struct gpmi_nfc_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	/* Accept the new timing. */
+
+	nfc->timing = *timing;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * exit() - Shuts down the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static void exit(struct gpmi_nfc_data *this)
+{
+	gpmi_nfc_dma_exit(this);
+}
+
+/**
+ * begin() - Begin NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	struct gpmi_nfc_hardware_timing  hw;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Get the timing information we need. */
+
+	nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+	gpmi_nfc_compute_hardware_timing(this, &hw);
+
+	/* Apply the hardware timing. */
+
+	/* Coming soon - the clock handling code isn't ready yet. */
+
+}
+
+/**
+ * end() - End NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * clear_bch() - Clears a BCH interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
+				resources->bch_regs + HW_BCH_CTRL_CLR);
+
+}
+
+/**
+ * is_ready() - Returns the ready/busy status of the given chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip of interest.
+ */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+
+	mask = BF_GPMI_STAT_READY_BUSY(1 << chip);
+
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+
+	return !!(register_image & mask);
+
+}
+
+/**
+ * send_command() - Sends a command and associated addresses.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the command bytes.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_command(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that sends out the command. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BM_GPMI_CTRL0_ADDRESS_INCREMENT          |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_data() - Sends data to the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the data.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that writes a buffer out. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_data() - Receives data from the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that will receive the data.
+ * @length:  The number of bytes to read.
+ */
+static int read_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that reads the data. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_WRITE;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/*
+	 * A DMA descriptor that waits for the command to end and the chip to
+	 * become ready.
+	 *
+	 * I think we actually should *not* be waiting for the chip to become
+	 * ready because, after all, we don't care. I think the original code
+	 * did that and no one has re-thought it yet.
+	 */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_page() - Sends a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int send_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that does an ECC page read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	(*d)->cmd.pio_words[1] = 0;
+
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_page() - Reads a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int read_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* Wait for the chip to report ready. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Enable the BCH block and read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC 	         |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Disable the BCH block */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Deassert the NAND lock and interrupt. */
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 0;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 0;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	wait_for_completion(&nfc->bch_done);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+
+struct nfc_hal  gpmi_nfc_hal_v1 = {
+	.version                     = 1,
+	.description                 = "8-chip GPMI and BCH",
+	.max_chip_count              = 8,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.send_data                   = send_data,
+	.read_data                   = read_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c
new file mode 100644
index 000000000000..eee49ae58dea
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c
@@ -0,0 +1,839 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+#include "gpmi-nfc-gpmi-regs-v2.h"
+#include "gpmi-nfc-bch-regs-v2.h"
+
+/**
+ * init() - Initializes the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static int init(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	int               error;
+
+	/* Initialize DMA. */
+
+	error = gpmi_nfc_dma_init(this);
+
+	if (error)
+		return error;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+
+	mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * set_geometry() - Configures the NFC geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+
+	if (gpmi_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes >> 2;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work and the version 1 BCH block is similar enough that we
+	 * suspect the same (though this has not been officially tested). If you
+	 * try to soft reset a version 0 BCH block, it becomes unusable until
+	 * the next hard reset.
+	 */
+
+	mxs_reset_block(resources->bch_regs, false);
+
+	/* Configure layout 0. */
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * set_timing() - Configures the NFC timing.
+ *
+ * @this:    Per-device data.
+ * @timing:  The timing of interest.
+ */
+static int set_timing(struct gpmi_nfc_data *this,
+					const struct gpmi_nfc_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	/* Accept the new timing. */
+
+	nfc->timing = *timing;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * exit() - Shuts down the NFC hardware.
+ *
+ * @this:  Per-device data.
+ */
+static void exit(struct gpmi_nfc_data *this)
+{
+	gpmi_nfc_dma_exit(this);
+}
+
+/**
+ * begin() - Begin NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	struct gpmi_nfc_hardware_timing  hw;
+
+	/* Enable the clock. */
+
+	clk_enable(resources->clock);
+
+	/* Get the timing information we need. */
+
+	nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+	gpmi_nfc_compute_hardware_timing(this, &hw);
+
+	/* Apply the hardware timing. */
+
+	/* Coming soon - the clock handling code isn't ready yet. */
+
+}
+
+/**
+ * end() - End NFC I/O.
+ *
+ * @this:  Per-device data.
+ */
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Disable the clock. */
+
+	clk_disable(resources->clock);
+
+}
+
+/**
+ * clear_bch() - Clears a BCH interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
+				resources->bch_regs + HW_BCH_CTRL_CLR);
+
+}
+
+/**
+ * is_ready() - Returns the ready/busy status of the given chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip of interest.
+ */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+
+	mask = BF_GPMI_STAT_READY_BUSY(1 << 0);
+
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+
+	return !!(register_image & mask);
+
+}
+
+/**
+ * send_command() - Sends a command and associated addresses.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the command bytes.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_command(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that sends out the command. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
+
+	/* reset the cmd bits fieled */
+	(*d)->cmd.cmd.data                   = 0;
+
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 1;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BM_GPMI_CTRL0_ADDRESS_INCREMENT          |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_data() - Sends data to the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that contains the data.
+ * @length:  The number of bytes in the buffer.
+ */
+static int send_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that writes a buffer out. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_READ;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 4;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+	(*d)->cmd.pio_words[3] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_data() - Receives data from the given chip.
+ *
+ * @this:    Per-device data.
+ * @chip:    The chip of interest.
+ * @buffer:  The physical address of a buffer that will receive the data.
+ * @length:  The number of bytes to read.
+ */
+static int read_data(struct gpmi_nfc_data *this, unsigned chip,
+					dma_addr_t buffer, unsigned int length)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that reads the data. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = DMA_WRITE;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 1;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = length;
+
+	(*d)->cmd.address = buffer;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(length)         ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * send_page() - Sends a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int send_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* A DMA descriptor that does an ECC page read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	(*d)->cmd.pio_words[1] = 0;
+
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	error = wait_for_completion_timeout(&nfc->bch_done,
+							msecs_to_jiffies(1000));
+
+	error = (!error) ? -ETIMEDOUT : 0;
+
+	if (error)
+		dev_err(dev, "[%s] bch timeout!!! \n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/**
+ * read_page() - Reads a page, using ECC.
+ *
+ * @this:       Per-device data.
+ * @chip:       The chip of interest.
+ * @payload:    The physical address of the payload buffer.
+ * @auxiliary:  The physical address of the auxiliary buffer.
+ */
+static int read_page(struct gpmi_nfc_data *this, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct device        *dev       =  this->dev;
+	struct resources     *resources = &this->resources;
+	struct nfc_hal       *nfc       =  this->nfc;
+	struct nfc_geometry  *nfc_geo   = &this->nfc_geometry;
+	struct mxs_dma_desc  **d        = nfc->dma_descriptors;
+	int                  dma_channel;
+	int                  error = 0;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	/* Compute the DMA channel. */
+
+	dma_channel = resources->dma_low_channel + chip;
+
+	/* Wait for the chip to report ready. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 0;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 1;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Enable the BCH block and read. */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 0;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 6;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC 	         |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	(*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes;
+	(*d)->cmd.pio_words[4] = payload;
+	(*d)->cmd.pio_words[5] = auxiliary;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Disable the BCH block */
+
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 1;
+	(*d)->cmd.cmd.bits.irq               = 0;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 1;
+	(*d)->cmd.cmd.bits.dec_sem           = 0;
+	(*d)->cmd.cmd.bits.wait4end          = 1;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 3;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	(*d)->cmd.pio_words[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ;
+
+	(*d)->cmd.pio_words[1] = 0;
+	(*d)->cmd.pio_words[2] = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Deassert the NAND lock and interrupt. */
+
+	(*d)->cmd.cmd.data                   = 0;
+	(*d)->cmd.cmd.bits.command           = NO_DMA_XFER;
+	(*d)->cmd.cmd.bits.chain             = 0;
+	(*d)->cmd.cmd.bits.irq               = 1;
+	(*d)->cmd.cmd.bits.nand_lock         = 0;
+	(*d)->cmd.cmd.bits.nand_wait_4_ready = 0;
+	(*d)->cmd.cmd.bits.dec_sem           = 1;
+	(*d)->cmd.cmd.bits.wait4end          = 0;
+	(*d)->cmd.cmd.bits.halt_on_terminate = 0;
+	(*d)->cmd.cmd.bits.terminate_flush   = 0;
+	(*d)->cmd.cmd.bits.pio_words         = 0;
+	(*d)->cmd.cmd.bits.bytes             = 0;
+
+	(*d)->cmd.address = 0;
+
+	mxs_dma_desc_append(dma_channel, (*d));
+	d++;
+
+	/* Prepare to receive an interrupt from the BCH block. */
+
+	init_completion(&nfc->bch_done);
+
+	/* Go! */
+
+	error = gpmi_nfc_dma_go(this, dma_channel);
+
+	if (error)
+		dev_err(dev, "[%s] DMA error\n", __func__);
+
+	/* Wait for the interrupt from the BCH block. */
+
+	error = wait_for_completion_timeout(&nfc->bch_done,
+							msecs_to_jiffies(1000));
+
+	error = (!error) ? -ETIMEDOUT : 0;
+
+	if (error)
+		dev_err(dev, "[%s] bch timeout!!! \n", __func__);
+
+	/* Return success. */
+
+	return error;
+
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+
+struct nfc_hal  gpmi_nfc_hal_v2 = {
+	.version                     = 2,
+	.description                 = "8-chip GPMI and BCH",
+	.max_chip_count              = 8,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.send_data                   = send_data,
+	.read_data                   = read_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
new file mode 100644
index 000000000000..54df1f084509
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
@@ -0,0 +1,1908 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * This structure contains the "safe" GPMI timing that should succeed with any
+ * NAND Flash device (although, with less-than-optimal performance).
+ */
+
+static struct gpmi_nfc_timing  safe_timing = {
+	.data_setup_in_ns        = 80,
+	.data_hold_in_ns         = 60,
+	.address_setup_in_ns     = 25,
+	.gpmi_sample_delay_in_ns =  6,
+	.tREA_in_ns              = -1,
+	.tRLOH_in_ns             = -1,
+	.tRHOH_in_ns             = -1,
+};
+
+/*
+ * This array has a pointer to every NFC HAL structure. The probing process will
+ * find and install the one that matches the version given by the platform.
+ */
+
+static struct nfc_hal  *(nfc_hals[]) = {
+	/* i.mx23 */
+	&gpmi_nfc_hal_v0,
+	/* i.mx28 */
+	&gpmi_nfc_hal_v1,
+	/* i.mx50 */
+	&gpmi_nfc_hal_v2,
+};
+
+/*
+ * This array has a pointer to every Boot ROM Helper structure. The probing
+ * process will find and install the one that matches the version given by the
+ * platform.
+ */
+
+static struct boot_rom_helper  *(boot_rom_helpers[]) = {
+	&gpmi_nfc_boot_rom_helper_v0,
+	&gpmi_nfc_boot_rom_helper_v1,
+};
+
+/**
+ * show_device_report() - Contains a shell script that creates a handy report.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_report(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+
+	static const char *script =
+		"GPMISysDirectory=/sys/bus/platform/devices/gpmi-nfc.0\n"
+		"\n"
+		"NodeList='\n"
+		"physical_geometry\n"
+		"nfc_info\n"
+		"nfc_geometry\n"
+		"timing\n"
+		"timing_diagram\n"
+		"rom_geometry\n"
+		"mtd_nand_info\n"
+		"mtd_info\n"
+		"'\n"
+		"\n"
+		"cd ${GPMISysDirectory}\n"
+		"\n"
+		"printf '\\n'\n"
+		"\n"
+		"for NodeName in ${NodeList}\n"
+		"do\n"
+		"\n"
+		"    printf '--------------------------------------------\\n'\n"
+		"    printf '%s\\n' ${NodeName}\n"
+		"    printf '--------------------------------------------\\n'\n"
+		"    printf '\\n'\n"
+		"\n"
+		"    cat ${NodeName}\n"
+		"\n"
+		"    printf '\\n'\n"
+		"\n"
+		"done\n"
+		;
+
+	return sprintf(buf, "%s", script);
+
+}
+
+/**
+ * show_device_numchips() - Shows the number of physical chips.
+ *
+ * This node is made obsolete by the physical_geometry node, but we keep it for
+ * backward compatibility (especially for kobs).
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_numchips(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this     = dev_get_drvdata(dev);
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	return sprintf(buf, "%d\n", physical->chip_count);
+
+}
+
+/**
+ * show_device_physical_geometry() - Shows the physical Flash device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_physical_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this     = dev_get_drvdata(dev);
+	struct nand_device_info   *info     = &this->device_info;
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	return sprintf(buf,
+		"Description            : %s\n"
+		"Chip Count             : %u\n"
+		"Chip Size in Bytes     : %llu\n"
+		"Block Size in Bytes    : %u\n"
+		"Page Data Size in Bytes: %u\n"
+		"Page OOB Size in Bytes : %u\n"
+		,
+		info->description,
+		physical->chip_count,
+		physical->chip_size_in_bytes,
+		physical->block_size_in_bytes,
+		physical->page_data_size_in_bytes,
+		physical->page_oob_size_in_bytes
+	);
+
+}
+
+/**
+ * show_device_nfc_info() - Shows the NFC-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct nfc_hal        *nfc  =  this->nfc;
+
+	return sprintf(buf,
+		"Version                   : %u\n"
+		"Description               : %s\n"
+		"Max Chip Count            : %u\n"
+		"Max Data Setup Cycles     : 0x%x\n"
+		"Internal Data Setup in ns : %u\n"
+		"Max Sample Delay Factor   : 0x%x\n"
+		"Max DLL Clock Period in ns: %u\n"
+		"Max DLL Delay in ns       : %u\n"
+		,
+		nfc->version,
+		nfc->description,
+		nfc->max_chip_count,
+		nfc->max_data_setup_cycles,
+		nfc->internal_data_setup_in_ns,
+		nfc->max_sample_delay_factor,
+		nfc->max_dll_clock_period_in_ns,
+		nfc->max_dll_delay_in_ns
+	);
+
+}
+
+/**
+ * show_device_nfc_geometry() - Shows the NFC view of the device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct nfc_geometry   *nfc  = &this->nfc_geometry;
+
+	return sprintf(buf,
+		"ECC Algorithm          : %s\n"
+		"ECC Strength           : %u\n"
+		"Page Size in Bytes     : %u\n"
+		"Metadata Size in Bytes : %u\n"
+		"ECC Chunk Size in Bytes: %u\n"
+		"ECC Chunk Count        : %u\n"
+		"Payload Size in Bytes  : %u\n"
+		"Auxiliary Size in Bytes: %u\n"
+		"Auxiliary Status Offset: %u\n"
+		"Block Mark Byte Offset : %u\n"
+		"Block Mark Bit Offset  : %u\n"
+		,
+		nfc->ecc_algorithm,
+		nfc->ecc_strength,
+		nfc->page_size_in_bytes,
+		nfc->metadata_size_in_bytes,
+		nfc->ecc_chunk_size_in_bytes,
+		nfc->ecc_chunk_count,
+		nfc->payload_size_in_bytes,
+		nfc->auxiliary_size_in_bytes,
+		nfc->auxiliary_status_offset,
+		nfc->block_mark_byte_offset,
+		nfc->block_mark_bit_offset
+	);
+
+}
+
+/**
+ * show_device_rom_geometry() - Shows the Boot ROM Helper's geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_rom_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data      *this = dev_get_drvdata(dev);
+	struct boot_rom_geometry  *rom  = &this->rom_geometry;
+
+	return sprintf(buf,
+		"Boot Area Count           : %u\n"
+		"Boot Area Size in Bytes   : %u\n"
+		"Stride Size in Pages      : %u\n"
+		"Seach Area Stride Exponent: %u\n"
+		,
+		rom->boot_area_count,
+		rom->boot_area_size_in_bytes,
+		rom->stride_size_in_pages,
+		rom->search_area_stride_exponent
+	);
+
+}
+
+/**
+ * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_nand_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct gpmi_nfc_data       *this = dev_get_drvdata(dev);
+	struct mil                 *mil  = &this->mil;
+	struct nand_chip           *nand = &mil->nand;
+
+	o += sprintf(buf + o,
+		"Options                       : 0x%08x\n"
+		"Chip Count                    : %u\n"
+		"Chip Size in Bytes            : %llu\n"
+		"Minimum Writable Size in Bytes: %u\n"
+		"Page Shift                    : %u\n"
+		"Page Mask                     : 0x%x\n"
+		"Block Shift                   : %u\n"
+		"BBT Block Shift               : %u\n"
+		"Chip Shift                    : %u\n"
+		"Block Mark Offset             : %u\n"
+		"Cached Page Number            : %d\n"
+		,
+		nand->options,
+		nand->numchips,
+		nand->chipsize,
+		nand->subpagesize,
+		nand->page_shift,
+		nand->pagemask,
+		nand->phys_erase_shift,
+		nand->bbt_erase_shift,
+		nand->chip_shift,
+		nand->badblockpos,
+		nand->pagebuf
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count       : %u\n"
+		,
+		nand->ecc.layout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= nand->ecc.layout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				nand->ecc.layout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes  : %u\n"
+		,
+		nand->ecc.layout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < nand->ecc.layout->oobavail; i++) {
+
+		j += nand->ecc.layout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			nand->ecc.layout->oobfree[i].offset,
+			nand->ecc.layout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+ * show_device_mtd_info() - Shows the device's MTD-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct gpmi_nfc_data       *this = dev_get_drvdata(dev);
+	struct mil                 *mil  = &this->mil;
+	struct mtd_info            *mtd  = &mil->mtd;
+
+	o += sprintf(buf + o,
+		"Name               : %s\n"
+		"Type               : %u\n"
+		"Flags              : 0x%08x\n"
+		"Size in Bytes      : %llu\n"
+		"Erase Region Count : %d\n"
+		"Erase Size in Bytes: %u\n"
+		"Write Size in Bytes: %u\n"
+		"OOB Size in Bytes  : %u\n"
+		"Errors Corrected   : %u\n"
+		"Failed Reads       : %u\n"
+		"Bad Block Count    : %u\n"
+		"BBT Block Count    : %u\n"
+		,
+		mtd->name,
+		mtd->type,
+		mtd->flags,
+		mtd->size,
+		mtd->numeraseregions,
+		mtd->erasesize,
+		mtd->writesize,
+		mtd->oobsize,
+		mtd->ecc_stats.corrected,
+		mtd->ecc_stats.failed,
+		mtd->ecc_stats.badblocks,
+		mtd->ecc_stats.bbtblocks
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count     : %u\n"
+		,
+		mtd->ecclayout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= mtd->ecclayout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				mtd->ecclayout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes: %u\n"
+		,
+		mtd->ecclayout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < mtd->ecclayout->oobavail; i++) {
+
+		j += mtd->ecclayout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			mtd->ecclayout->oobfree[i].offset,
+			mtd->ecclayout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+  * show_device_timing_diagram() - Shows a timing diagram.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing_diagram(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data             *this      = dev_get_drvdata(dev);
+	struct gpmi_nfc_platform_data    *pdata     =  this->pdata;
+	struct nfc_hal                   *nfc       = this->nfc;
+	struct gpmi_nfc_timing           timing     = nfc->timing;
+	struct gpmi_nfc_hardware_timing  hardware_timing;
+	unsigned long                    clock_frequency_in_hz;
+	unsigned long                    clock_period_in_ns;
+	unsigned int                     data_setup_in_ns;
+	unsigned int                     dll_delay_shift;
+	unsigned int                     sample_delay_in_ns;
+	unsigned int                     tDS_in_ns;
+	unsigned int                     tOPEN_in_ns;
+	unsigned int                     tCLOSE_in_ns;
+	unsigned int                     tEYE_in_ns;
+	unsigned int                     tDELAY_in_ns;
+	unsigned int                     tDS;
+	unsigned int                     tOPEN;
+	unsigned int                     tCLOSE;
+	unsigned int                     tEYE;
+	unsigned int                     tDELAY;
+	const unsigned int               diagram_width_in_chars = 55;
+	unsigned int                     diagram_width_in_ns;
+	int                              o = 0;
+	unsigned int                     i;
+
+	/*
+	 * If there are any timing characteristics we need, but don't know, we
+	 * pretend they're zero.
+	 */
+
+	if (timing.tREA_in_ns < 0)
+		timing.tREA_in_ns = 0;
+
+	if (timing.tRHOH_in_ns < 0)
+		timing.tRHOH_in_ns = 0;
+
+	/* Get information about the current/last I/O transaction. */
+
+	nfc->get_timing(this, &clock_frequency_in_hz, &hardware_timing);
+
+	clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+	/* Compute basic timing facts. */
+
+	data_setup_in_ns =
+		hardware_timing.data_setup_in_cycles * clock_period_in_ns;
+
+	/* Compute data sample delay facts. */
+
+	dll_delay_shift = 3;
+
+	if (hardware_timing.use_half_periods)
+		dll_delay_shift++;
+
+	sample_delay_in_ns =
+		(hardware_timing.sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+	/* Compute the basic metrics in the diagram, in nanoseconds. */
+
+	tDS_in_ns    = data_setup_in_ns;
+	tOPEN_in_ns  = pdata->max_prop_delay_in_ns + timing.tREA_in_ns;
+	tCLOSE_in_ns = pdata->min_prop_delay_in_ns + timing.tRHOH_in_ns;
+	tEYE_in_ns   = tDS_in_ns + tCLOSE_in_ns - tOPEN_in_ns;
+	tDELAY_in_ns = sample_delay_in_ns;
+
+	/*
+	 * We need to translate nanosecond timings into character widths in the
+	 * diagram. The first step is to discover how "wide" the diagram is in
+	 * nanoseconds. That depends on which happens latest: the sample point
+	 * or the close of the eye.
+	 */
+
+	if (tCLOSE_in_ns >= tDELAY_in_ns)
+		diagram_width_in_ns = tDS_in_ns + tCLOSE_in_ns;
+	else
+		diagram_width_in_ns = tDS_in_ns + tDELAY_in_ns;
+
+	/* Convert the metrics that appear in the diagram. */
+
+	tDS    = (tDS_in_ns    * diagram_width_in_chars) / diagram_width_in_ns;
+	tOPEN  = (tOPEN_in_ns  * diagram_width_in_chars) / diagram_width_in_ns;
+	tCLOSE = (tCLOSE_in_ns * diagram_width_in_chars) / diagram_width_in_ns;
+	tEYE   = (tEYE_in_ns   * diagram_width_in_chars) / diagram_width_in_ns;
+	tDELAY = (tDELAY_in_ns * diagram_width_in_chars) / diagram_width_in_ns;
+
+	/*
+	 * Show the results.
+	 *
+	 * This code is really ugly, but it draws a pretty picture :)
+	 */
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Sample ______");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, "_");
+	if (tDELAY > 0)
+		for (i = 0; i < (tDELAY - 1); i++)
+			o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "|");
+	for (i = 0; i < (diagram_width_in_chars - (tDS + tDELAY)); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Strobe       ");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tDELAY > 1) {
+		for (i = 2; i < tDELAY; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tDELAY\n");
+
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "         tDS ");
+	o += sprintf(buf + o, "|");
+	if (tDS > 1) {
+		for (i = 2; i < tDS; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "       ______");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	for (i = 0; i < (diagram_width_in_chars - tDS); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "RDN          ");
+	if (tDS > 0) {
+		if (tDS == 1)
+			o += sprintf(buf + o, "V");
+		else {
+			o += sprintf(buf + o, "\\");
+			for (i = 2; i < tDS; i++)
+				o += sprintf(buf + o, "_");
+			o += sprintf(buf + o, "/");
+		}
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "       tOPEN ");
+	o += sprintf(buf + o, "|");
+	if (tOPEN > 1) {
+		for (i = 2; i < tOPEN; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tDS; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tCLOSE > 1) {
+		for (i = 2; i < tCLOSE; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tCLOSE\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	if (tEYE > 2) {
+		o += sprintf(buf + o, " ");
+		for (i = 2; i < tEYE; i++)
+			o += sprintf(buf + o, "_");
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "Data   ______");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, "_");
+	if (tEYE > 0) {
+		if (tEYE == 1)
+			o += sprintf(buf + o, "|");
+		else {
+			o += sprintf(buf + o, "/");
+			for (i = 2; i < tEYE; i++)
+				o += sprintf(buf + o, " ");
+			o += sprintf(buf + o, "\\");
+		}
+	}
+	for (i = 0; i < (diagram_width_in_chars - (tOPEN + tEYE)); i++)
+		o += sprintf(buf + o, "_");
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	if (tEYE > 0) {
+		if (tEYE == 1)
+			o += sprintf(buf + o, "|");
+		else {
+			o += sprintf(buf + o, "\\");
+			for (i = 2; i < tEYE; i++)
+				o += sprintf(buf + o, "_");
+			o += sprintf(buf + o, "/");
+		}
+	}
+	o += sprintf(buf + o, "\n");
+
+
+	o += sprintf(buf + o, "             ");
+	for (i = 0; i < tOPEN; i++)
+		o += sprintf(buf + o, " ");
+	o += sprintf(buf + o, "|");
+	if (tEYE > 1) {
+		for (i = 2; i < tEYE; i++)
+			o += sprintf(buf + o, "-");
+		o += sprintf(buf + o, "|");
+	}
+	o += sprintf(buf + o, " tEYE\n");
+
+
+	o += sprintf(buf + o, "\n");
+	o += sprintf(buf + o, "tDS   : %u ns\n", tDS_in_ns);
+	o += sprintf(buf + o, "tOPEN : %u ns\n", tOPEN_in_ns);
+	o += sprintf(buf + o, "tCLOSE: %u ns\n", tCLOSE_in_ns);
+	o += sprintf(buf + o, "tEYE  : %u ns\n", tEYE_in_ns);
+	o += sprintf(buf + o, "tDELAY: %u ns\n", tDELAY_in_ns);
+	o += sprintf(buf + o, "\n");
+
+
+	return o;
+
+}
+
+/**
+ * store_device_invalidate_page_cache() - Invalidates the device's page cache.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_invalidate_page_cache(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+
+	/* Invalidate the page cache. */
+
+	this->mil.nand.pagebuf = -1;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * store_device_mark_block_bad() - Marks a block as bad.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_mark_block_bad(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	struct mtd_info       *mtd  = &mil->mtd;
+	struct nand_chip      *nand = &mil->nand;
+	unsigned long         block_number;
+	loff_t                byte_address;
+	int                   error;
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the block number. */
+
+	if (strict_strtoul(buf, 0, &block_number))
+		return -EINVAL;
+
+	/* Compute the byte address of this block. */
+
+	byte_address = block_number << nand->phys_erase_shift;
+
+	/* Attempt to mark the block bad. */
+
+	error = mtd->block_markbad(mtd, byte_address);
+
+	if (error)
+		return error;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * show_device_ignorebad() - Shows the value of the 'ignorebad' flag.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_ignorebad(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+
+	return sprintf(buf, "%d\n", mil->ignore_bad_block_marks);
+}
+
+/**
+ * store_device_ignorebad() - Sets the value of the 'ignorebad' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_ignorebad(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	const char            *p = buf;
+	unsigned long         v;
+
+	/* Try to make sense of what arrived from user space. */
+
+	if (strict_strtoul(p, 0, &v) < 0)
+		return size;
+
+	if (v > 0)
+		v = 1;
+
+	/* Only do something if the value is changing. */
+
+	if (v != mil->ignore_bad_block_marks) {
+
+		if (v) {
+
+			/*
+			 * If control arrives here, we want to begin ignoring
+			 * bad block marks. Reach into the NAND Flash MTD data
+			 * structures and set the in-memory BBT pointer to NULL.
+			 * This will cause the NAND Flash MTD code to believe
+			 * that it never created a BBT and force it to call our
+			 * block_bad function.
+			 *
+			 * See mil_block_bad for more details.
+			 */
+
+			mil->saved_bbt = mil->nand.bbt;
+			mil->nand.bbt  = 0;
+
+		} else {
+
+			/*
+			 * If control arrives here, we want to stop ignoring
+			 * bad block marks. Restore the NAND Flash MTD's pointer
+			 * to its in-memory BBT.
+			 */
+
+			mil->nand.bbt = mil->saved_bbt;
+
+		}
+
+		mil->ignore_bad_block_marks = v;
+
+	}
+
+	return size;
+
+}
+
+/**
+ * show_device_inject_ecc_error() - Shows the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_inject_ecc_error(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+
+	return sprintf(buf, "%d\n", mil->inject_ecc_error);
+
+}
+
+/**
+ * store_device_inject_ecc_error() - Sets the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_inject_ecc_error(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data  *this = dev_get_drvdata(dev);
+	struct mil            *mil  = &this->mil;
+	long                  new_inject_ecc_error;
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the ECC error count. */
+
+	if (strict_strtol(buf, 0, &new_inject_ecc_error))
+		return -EINVAL;
+
+	/* Store the value. */
+
+	mil->inject_ecc_error = new_inject_ecc_error;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * show_device_timing_help() - Show help for setting timing.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing_help(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+
+	static const char *help =
+		"<Data Setup>,<Data Hold>,<Address Setup>,<Sample Delay>,"
+						"<tREA>,<tRLOH>,<tRHOH>\n";
+
+	return sprintf(buf, "%s", help);
+
+}
+
+/**
+ * show_device_timing() - Shows the current timing.
+ *
+ * @d:     The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_timing(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct gpmi_nfc_data             *this      = dev_get_drvdata(dev);
+	struct gpmi_nfc_platform_data    *pdata     = this->pdata;
+	struct nfc_hal                   *nfc       = this->nfc;
+	struct gpmi_nfc_timing           *recorded  = &nfc->timing;
+	unsigned long                    clock_frequency_in_hz;
+	unsigned long                    clock_period_in_ns;
+	struct gpmi_nfc_hardware_timing  hardware;
+	unsigned int                     effective_data_setup_in_ns;
+	unsigned int                     effective_data_hold_in_ns;
+	unsigned int                     effective_address_setup_in_ns;
+	unsigned int                     dll_delay_shift;
+	unsigned int                     effective_sample_delay_in_ns;
+
+	/* Get information about the current/last I/O transaction. */
+
+	nfc->get_timing(this, &clock_frequency_in_hz, &hardware);
+
+	clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+	/* Compute basic timing facts. */
+
+	effective_data_setup_in_ns    =
+			hardware.data_setup_in_cycles    * clock_period_in_ns;
+	effective_data_hold_in_ns     =
+			hardware.data_hold_in_cycles     * clock_period_in_ns;
+	effective_address_setup_in_ns =
+			hardware.address_setup_in_cycles * clock_period_in_ns;
+
+	/* Compute data sample delay facts. */
+
+	dll_delay_shift = 3;
+
+	if (hardware.use_half_periods)
+		dll_delay_shift++;
+
+	effective_sample_delay_in_ns =
+		(hardware.sample_delay_factor * clock_period_in_ns) >>
+								dll_delay_shift;
+
+	/* Show the results. */
+
+	return sprintf(buf,
+		"Minimum Propagation Delay in ns  : %u\n"
+		"Maximum Propagation Delay in ns  : %u\n"
+		"Clock Frequency in Hz            : %lu\n"
+		"Clock Period in ns               : %lu\n"
+		"Recorded  Data Setup in ns       : %d\n"
+		"Hardware  Data Setup in cycles   : %u\n"
+		"Effective Data Setup in ns       : %u\n"
+		"Recorded  Data Hold in ns        : %d\n"
+		"Hardware  Data Hold in cycles    : %u\n"
+		"Effective Data Hold in ns        : %u\n"
+		"Recorded  Address Setup in ns    : %d\n"
+		"Hardware  Address Setup in cycles: %u\n"
+		"Effective Address Setup in ns    : %u\n"
+		"Using Half Period                : %s\n"
+		"Recorded  Sample Delay in ns     : %d\n"
+		"Hardware  Sample Delay Factor    : %u\n"
+		"Effective Sample Delay in ns     : %u\n"
+		"Recorded  tREA in ns             : %d\n"
+		"Recorded  tRLOH in ns            : %d\n"
+		"Recorded  tRHOH in ns            : %d\n"
+		,
+		pdata->min_prop_delay_in_ns,
+		pdata->max_prop_delay_in_ns,
+		clock_frequency_in_hz,
+		clock_period_in_ns,
+		recorded->data_setup_in_ns,
+		hardware .data_setup_in_cycles,
+		effective_data_setup_in_ns,
+		recorded->data_hold_in_ns,
+		hardware .data_hold_in_cycles,
+		effective_data_hold_in_ns,
+		recorded->address_setup_in_ns,
+		hardware .address_setup_in_cycles,
+		effective_address_setup_in_ns,
+		hardware .use_half_periods ? "Yes" : "No",
+		recorded->gpmi_sample_delay_in_ns,
+		hardware .sample_delay_factor,
+		effective_sample_delay_in_ns,
+		recorded->tREA_in_ns,
+		recorded->tRLOH_in_ns,
+		recorded->tRHOH_in_ns);
+
+}
+
+/**
+ * store_device_timing() - Sets the current timing.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_timing(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct gpmi_nfc_data    *this = dev_get_drvdata(dev);
+	struct nfc_hal          *nfc  = this->nfc;
+	const char              *p    = buf;
+	const char              *q;
+	char                    tmps[20];
+	long                    t;
+	struct gpmi_nfc_timing  new;
+
+	int8_t *field_pointers[] = {
+		&new.data_setup_in_ns,
+		&new.data_hold_in_ns,
+		&new.address_setup_in_ns,
+		&new.gpmi_sample_delay_in_ns,
+		&new.tREA_in_ns,
+		&new.tRLOH_in_ns,
+		&new.tRHOH_in_ns,
+		NULL,
+	};
+
+	int8_t **field_pointer = field_pointers;
+
+	/*
+	 * Loop over comma-separated timing values in the incoming buffer,
+	 * assigning them to fields in the timing structure as we go along.
+	 */
+
+	while (*field_pointer != NULL) {
+
+		/* Clear out the temporary buffer. */
+
+		memset(tmps, 0, sizeof(tmps));
+
+		/* Copy the timing value into the temporary buffer. */
+
+		q = strchr(p, ',');
+		if (q)
+			strncpy(tmps, p, min_t(int, sizeof(tmps) - 1, q - p));
+		else
+			strncpy(tmps, p, sizeof(tmps) - 1);
+
+		/* Attempt to convert the current timing value. */
+
+		if (strict_strtol(tmps, 0, &t) < 0)
+			return -EINVAL;
+
+		if ((t > 127) || (t < -128))
+			return -EINVAL;
+
+		/* Assign this value to the current field. */
+
+		**field_pointer = (int8_t) t;
+		field_pointer++;
+
+		/* Check if we ran out of input too soon. */
+
+		if (!q && *field_pointer)
+			return -EINVAL;
+
+		/* Move past the comma to the next timing value. */
+
+		p = q + 1;
+
+	}
+
+	/* Hand over the timing to the NFC. */
+
+	nfc->set_timing(this, &new);
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/* Device attributes that appear in sysfs. */
+
+static DEVICE_ATTR(report           , 0555, show_device_report           , 0);
+static DEVICE_ATTR(numchips         , 0444, show_device_numchips         , 0);
+static DEVICE_ATTR(physical_geometry, 0444, show_device_physical_geometry, 0);
+static DEVICE_ATTR(nfc_info         , 0444, show_device_nfc_info         , 0);
+static DEVICE_ATTR(nfc_geometry     , 0444, show_device_nfc_geometry     , 0);
+static DEVICE_ATTR(rom_geometry     , 0444, show_device_rom_geometry     , 0);
+static DEVICE_ATTR(mtd_nand_info    , 0444, show_device_mtd_nand_info    , 0);
+static DEVICE_ATTR(mtd_info         , 0444, show_device_mtd_info         , 0);
+static DEVICE_ATTR(timing_diagram   , 0444, show_device_timing_diagram   , 0);
+static DEVICE_ATTR(timing_help      , 0444, show_device_timing_help      , 0);
+
+static DEVICE_ATTR(invalidate_page_cache, 0644,
+	0, store_device_invalidate_page_cache);
+
+static DEVICE_ATTR(mark_block_bad, 0200,
+	0, store_device_mark_block_bad);
+
+static DEVICE_ATTR(ignorebad, 0644,
+	show_device_ignorebad, store_device_ignorebad);
+
+static DEVICE_ATTR(inject_ecc_error, 0644,
+	show_device_inject_ecc_error, store_device_inject_ecc_error);
+
+static DEVICE_ATTR(timing, 0644,
+	show_device_timing, store_device_timing);
+
+static struct device_attribute *device_attributes[] = {
+	&dev_attr_report,
+	&dev_attr_numchips,
+	&dev_attr_physical_geometry,
+	&dev_attr_nfc_info,
+	&dev_attr_nfc_geometry,
+	&dev_attr_rom_geometry,
+	&dev_attr_mtd_nand_info,
+	&dev_attr_mtd_info,
+	&dev_attr_invalidate_page_cache,
+	&dev_attr_mark_block_bad,
+	&dev_attr_ignorebad,
+	&dev_attr_inject_ecc_error,
+	&dev_attr_timing,
+	&dev_attr_timing_help,
+	&dev_attr_timing_diagram,
+};
+
+/**
+ * validate_the_platform() - Validates information about the platform.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int validate_the_platform(struct platform_device *pdev)
+{
+	struct device                  *dev   = &pdev->dev;
+	struct gpmi_nfc_platform_data  *pdata = pdev->dev.platform_data;
+
+	/* Validate the clock name. */
+
+	if (!pdata->clock_name) {
+		dev_err(dev, "No clock name\n");
+		return -ENXIO;
+	}
+
+	/* Validate the partitions. */
+
+	if ((pdata->partitions && (!pdata->partition_count)) ||
+			(!pdata->partitions && (pdata->partition_count))) {
+		dev_err(dev, "Bad partition data\n");
+		return -ENXIO;
+	}
+
+	/* Return success */
+
+	return 0;
+
+}
+
+/**
+ * acquire_register_block() - Tries to acquire and map a register block.
+ *
+ * @this:            Per-device data.
+ * @resource_name:   The name of the resource.
+ * @reg_block_base:  A pointer to a variable that will receive the address of
+ *                   the mapped register block.
+ */
+static int acquire_register_block(struct gpmi_nfc_data *this,
+			const char *resource_name, void **reg_block_base)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	void                    *p;
+	struct resource         *r;
+
+	/* Attempt to get information about the given resource. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
+
+	if (!r) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Attempt to remap the register block. */
+
+	p = ioremap(r->start, r->end - r->start + 1);
+
+	if (!p) {
+		dev_err(dev, "Can't remap %s\n", resource_name);
+		return -EIO;
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*reg_block_base = p;
+
+	return 0;
+
+}
+
+/**
+ * release_register_block() - Releases a register block.
+ *
+ * @this:            Per-device data.
+ * @reg_block_base:  A pointer to the mapped register block.
+ */
+static void release_register_block(struct gpmi_nfc_data *this,
+							void *reg_block_base)
+{
+	iounmap(reg_block_base);
+}
+
+/**
+ * acquire_interrupt() - Tries to acquire an interrupt.
+ *
+ * @this:              Per-device data.
+ * @resource_name:     The name of the resource.
+ * @interrupt_handler: A pointer to the function that will handle interrupts
+ *                     from this interrupt number.
+ * @lno:               A pointer to a variable that will receive the acquired
+ *                     interrupt number(low part).
+ * @hno:               A pointer to a variable that will receive the acquired
+ *                     interrupt number(high part).
+ */
+static int acquire_interrupt(
+			struct gpmi_nfc_data *this, const char *resource_name,
+			irq_handler_t interrupt_handler, int *lno, int *hno)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	int                     error = 0;
+	struct resource         *r;
+	int                     i;
+
+	/* Attempt to get information about the given resource. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name);
+
+	if (!r) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Attempt to own the interrupt. */
+	for (i = r->start; i <= r->end; i++) {
+		error = request_irq(i, interrupt_handler, 0,
+						resource_name, this);
+
+		if (error) {
+			dev_err(dev, "Can't own %s\n", resource_name);
+
+			/* Free all the irq's we've already acquired. */
+
+			while ((i - r->start) >= 0) {
+				free_irq(i, this);
+				i--;
+			}
+
+			return -EIO;
+		}
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*lno = r->start;
+	*hno = r->end;
+
+	return 0;
+
+}
+
+/**
+ * release_interrupt() - Releases an interrupt.
+ *
+ * @this:              Per-device data.
+ * @interrupt_number:  The interrupt number.
+ */
+static void release_interrupt(struct gpmi_nfc_data *this,
+			int low_interrupt_number, int high_interrupt_number)
+{
+	int i;
+	for (i = low_interrupt_number; i <= high_interrupt_number; i++)
+		free_irq(i, this);
+}
+
+/**
+ * acquire_dma_channels() - Tries to acquire DMA channels.
+ *
+ * @this:           Per-device data.
+ * @resource_name:  The name of the resource.
+ * @low_channel:    A pointer to a variable that will receive the acquired
+ *                  low DMA channel number.
+ * @high_channel:   A pointer to a variable that will receive the acquired
+ *                  high DMA channel number.
+ */
+static int acquire_dma_channels(
+			struct gpmi_nfc_data *this, const char *resource_name,
+			unsigned *low_channel, unsigned *high_channel)
+{
+	struct platform_device  *pdev = this->pdev;
+	struct device           *dev  = this->dev;
+	int                     error = 0;
+	struct resource         *r;
+	unsigned int            dma_channel;
+
+	/* Attempt to get information about the given resource. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name);
+
+	if (!r) {
+		dev_err(dev, "Can't get resource information for '%s'\n",
+								resource_name);
+		return -ENXIO;
+	}
+
+	/* Loop over DMA channels, attempting to own them. */
+
+	for (dma_channel = r->start; dma_channel <= r->end; dma_channel++) {
+
+		/* Attempt to own the current channel. */
+
+		error = mxs_dma_request(dma_channel, dev, resource_name);
+
+		/* Check if we successfully acquired the current channel. */
+
+		if (error) {
+
+			dev_err(dev, "Can't acquire DMA channel %u\n",
+								dma_channel);
+
+			/* Free all the channels we've already acquired. */
+
+			while (--dma_channel >= 0)
+				mxs_dma_release(dma_channel, dev);
+
+			return error;
+
+		}
+
+		/*
+		 * If control arrives here, we successfully acquired the
+		 * current channel. Continue initializing it.
+		 */
+
+		mxs_dma_reset(dma_channel);
+		mxs_dma_ack_irq(dma_channel);
+
+	}
+
+	/* If control arrives here, all went well. */
+
+	*low_channel  = r->start;
+	*high_channel = r->end;
+
+	return 0;
+
+}
+
+/**
+ * release_dma_channels() - Releases DMA channels.
+ *
+ * @this:          Per-device data.
+ * @low_channel:   The low DMA channel number.
+ * @high_channel:  The high DMA channel number.
+ */
+static void release_dma_channels(struct gpmi_nfc_data *this,
+				unsigned low_channel, unsigned high_channel)
+{
+	struct device  *dev = this->dev;
+	unsigned int   i;
+
+	for (i = low_channel; i <= high_channel; i++)
+		mxs_dma_release(i, dev);
+}
+
+/**
+ * acquire_clock() - Tries to acquire a clock.
+ *
+ * @this:           Per-device data.
+ * @resource_name:  The name of the clock.
+ * @high_channel:   A pointer to a variable that will receive the acquired
+ *                  clock address.
+ */
+static int acquire_clock(struct gpmi_nfc_data *this,
+				const char *clock_name, struct clk **clock)
+{
+	struct device  *dev  = this->dev;
+	int            error = 0;
+	struct clk     *c;
+
+	/* Try to get the clock. */
+
+	c = clk_get(dev, clock_name);
+
+	if (IS_ERR(c)) {
+		error = PTR_ERR(c);
+		dev_err(dev, "Can't own clock %s\n", clock_name);
+		return error;
+	}
+
+	/* If control arrives here, everything went fine. */
+
+	*clock = c;
+
+	return 0;
+
+}
+
+/**
+ * release_clock() - Releases a clock.
+ *
+ * @this:   Per-device data.
+ * @clock:  A pointer to the clock structure.
+ */
+static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
+{
+	clk_disable(clock);
+	clk_put(clock);
+}
+
+/**
+ * acquire_resources() - Tries to acquire resources.
+ *
+ * @this:  Per-device data.
+ */
+static int acquire_resources(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata     =  this->pdata;
+	struct resources               *resources = &this->resources;
+	int                            error      = 0;
+
+	/* Attempt to acquire the GPMI register block. */
+
+	error = acquire_register_block(this,
+		GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, &(resources->gpmi_regs));
+
+	if (error)
+		goto exit_gpmi_regs;
+
+	/* Attempt to acquire the BCH register block. */
+
+	error = acquire_register_block(this,
+		GPMI_NFC_BCH_REGS_ADDR_RES_NAME, &(resources->bch_regs));
+
+	if (error)
+		goto exit_bch_regs;
+
+	/* Attempt to acquire the BCH interrupt. */
+
+	error = acquire_interrupt(this,
+		GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+		gpmi_nfc_bch_isr,
+		&(resources->bch_low_interrupt),
+		&(resources->bch_high_interrupt));
+
+	if (error)
+		goto exit_bch_interrupt;
+
+	/* Attempt to acquire the DMA channels. */
+
+	error = acquire_dma_channels(this,
+		GPMI_NFC_DMA_CHANNELS_RES_NAME,
+		&(resources->dma_low_channel), &(resources->dma_high_channel));
+
+	if (error)
+		goto exit_dma_channels;
+
+	/* Attempt to acquire the DMA interrupt. */
+
+	error = acquire_interrupt(this,
+		GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+		gpmi_nfc_dma_isr,
+		&(resources->dma_low_interrupt),
+		&(resources->dma_high_interrupt));
+
+	if (error)
+		goto exit_dma_interrupt;
+
+	/* Attempt to acquire our clock. */
+
+	error = acquire_clock(this, pdata->clock_name, &(resources->clock));
+
+	if (error)
+		goto exit_clock;
+
+	/* If control arrives here, all went well. */
+
+	return 0;
+
+	/* Control arrives here if something went wrong. */
+
+exit_clock:
+	release_interrupt(this,
+		resources->dma_low_interrupt, resources->dma_high_interrupt);
+exit_dma_interrupt:
+	release_dma_channels(this,
+		resources->dma_low_channel, resources->dma_high_channel);
+exit_dma_channels:
+	release_interrupt(this,
+		resources->bch_low_interrupt, resources->bch_high_interrupt);
+exit_bch_interrupt:
+	release_register_block(this, resources->bch_regs);
+exit_bch_regs:
+	release_register_block(this, resources->gpmi_regs);
+exit_gpmi_regs:
+
+	return error;
+
+}
+
+/**
+ * release_resources() - Releases resources.
+ *
+ * @this:  Per-device data.
+ */
+static void release_resources(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	release_clock(this, resources->clock);
+	release_register_block(this, resources->gpmi_regs);
+	release_register_block(this, resources->bch_regs);
+	release_interrupt(this,
+		resources->bch_low_interrupt, resources->bch_low_interrupt);
+	release_dma_channels(this,
+		resources->dma_low_channel, resources->dma_high_channel);
+	release_interrupt(this,
+		resources->dma_low_interrupt, resources->dma_high_interrupt);
+}
+
+/**
+ * set_up_nfc_hal() - Sets up the NFC HAL.
+ *
+ * @this:  Per-device data.
+ */
+static int set_up_nfc_hal(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+	struct device                  *dev   = this->dev;
+	struct nfc_hal                 *nfc;
+	int                            error = 0;
+	unsigned int                   i;
+
+	/* Attempt to find an NFC HAL that matches the given version. */
+
+	for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) {
+
+		nfc = nfc_hals[i];
+
+		if (nfc->version == pdata->nfc_version) {
+			this->nfc = nfc;
+			break;
+		}
+
+	}
+
+	/* Check if we found a HAL. */
+
+	if (i >= ARRAY_SIZE(nfc_hals)) {
+		dev_err(dev, "Unkown NFC version %u\n", pdata->nfc_version);
+		return -ENXIO;
+	}
+
+	pr_info("NFC: Version %u, %s\n", nfc->version, nfc->description);
+
+	/*
+	 * Check if we can handle the number of chips called for by the platform
+	 * data.
+	 */
+
+	if (pdata->max_chip_count > nfc->max_chip_count) {
+		dev_err(dev, "Platform data calls for %u chips "
+				"but NFC supports a max of %u.\n",
+				pdata->max_chip_count, nfc->max_chip_count);
+		return -ENXIO;
+	}
+
+	/* Initialize the NFC HAL. */
+
+	error = nfc->init(this);
+
+	if (error)
+		return error;
+
+	/* Set up safe timing. */
+
+	nfc->set_timing(this, &safe_timing);
+
+	/*
+	 * If control arrives here, all is well.
+	 */
+
+	return 0;
+
+}
+
+/**
+ * set_up_boot_rom_helper() - Sets up the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+	struct device                  *dev   = this->dev;
+	unsigned int                   i;
+	struct boot_rom_helper         *rom;
+
+	/* Attempt to find a Boot ROM Helper that matches the given version. */
+
+	for (i = 0; i < ARRAY_SIZE(boot_rom_helpers); i++) {
+
+		rom = boot_rom_helpers[i];
+
+		if (rom->version == pdata->boot_rom_version) {
+			this->rom = rom;
+			break;
+		}
+
+	}
+
+	/* Check if we found a Boot ROM Helper. */
+
+	if (i >= ARRAY_SIZE(boot_rom_helpers)) {
+		dev_err(dev, "Unkown Boot ROM version %u\n",
+						pdata->boot_rom_version);
+		return -ENXIO;
+	}
+
+	pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
+
+	/*
+	 * If control arrives here, all is well.
+	 */
+
+	return 0;
+
+}
+
+/**
+ * manage_sysfs_files() - Creates/removes sysfs files for this device.
+ *
+ * @this:  Per-device data.
+ */
+static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
+{
+	struct device            *dev = this->dev;
+	int                      error;
+	unsigned int             i;
+	struct device_attribute  **attr;
+
+	for (i = 0, attr = device_attributes;
+			i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+		if (create) {
+			error = device_create_file(dev, *attr);
+			if (error) {
+				while (--attr >= device_attributes)
+					device_remove_file(dev, *attr);
+				return;
+			}
+		} else {
+			device_remove_file(dev, *attr);
+		}
+
+	}
+
+}
+
+/**
+ * gpmi_nfc_probe() - Probes for a device and, if possible, takes ownership.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int gpmi_nfc_probe(struct platform_device *pdev)
+{
+	int                            error  = 0;
+	struct device                  *dev   = &pdev->dev;
+	struct gpmi_nfc_platform_data  *pdata = pdev->dev.platform_data;
+	struct gpmi_nfc_data           *this  = 0;
+
+	/* Validate the platform device data. */
+
+	error = validate_the_platform(pdev);
+
+	if (error)
+		goto exit_validate_platform;
+
+	/* Allocate memory for the per-device data. */
+
+	this = kzalloc(sizeof(*this), GFP_KERNEL);
+
+	if (!this) {
+		dev_err(dev, "Failed to allocate per-device memory\n");
+		error = -ENOMEM;
+		goto exit_allocate_this;
+	}
+
+	/* Set up our data structures. */
+
+	platform_set_drvdata(pdev, this);
+
+	this->pdev  = pdev;
+	this->dev   = &pdev->dev;
+	this->pdata = pdata;
+
+	/* Acquire the resources we need. */
+
+	error = acquire_resources(this);
+
+	if (error)
+		goto exit_acquire_resources;
+
+	/* Set up the NFC. */
+
+	error = set_up_nfc_hal(this);
+
+	if (error)
+		goto exit_nfc_init;
+
+	/* Set up the platform. */
+
+	if (pdata->platform_init)
+		error = pdata->platform_init(pdata->max_chip_count);
+
+	if (error)
+		goto exit_platform_init;
+
+	/* Set up the Boot ROM Helper. */
+
+	error = set_up_boot_rom_helper(this);
+
+	if (error)
+		goto exit_boot_rom_helper_init;
+
+	/* Initialize the MTD Interface Layer. */
+
+	error = gpmi_nfc_mil_init(this);
+
+	if (error)
+		goto exit_mil_init;
+
+	/* Create sysfs entries for this device. */
+
+	manage_sysfs_files(this, true);
+
+	/* Return success. */
+
+	return 0;
+
+	/* Error return paths begin here. */
+
+exit_mil_init:
+exit_boot_rom_helper_init:
+	if (pdata->platform_exit)
+		pdata->platform_exit(pdata->max_chip_count);
+exit_platform_init:
+	this->nfc->exit(this);
+exit_nfc_init:
+	release_resources(this);
+exit_acquire_resources:
+	platform_set_drvdata(pdev, NULL);
+	kfree(this);
+exit_allocate_this:
+exit_validate_platform:
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_remove() - Dissociates this driver from the given device.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int __exit gpmi_nfc_remove(struct platform_device *pdev)
+{
+	struct gpmi_nfc_data           *this = platform_get_drvdata(pdev);
+	struct gpmi_nfc_platform_data  *pdata = this->pdata;
+
+	manage_sysfs_files(this, false);
+	gpmi_nfc_mil_exit(this);
+	if (pdata->platform_exit)
+		pdata->platform_exit(pdata->max_chip_count);
+	this->nfc->exit(this);
+	release_resources(this);
+	platform_set_drvdata(pdev, NULL);
+	kfree(this);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+/**
+ * gpmi_nfc_suspend() - Puts the NFC into a low power state.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ * @state: The new power state.
+ */
+static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+/**
+ * gpmi_nfc_resume() - Brings the NFC back from a low power state.
+ *
+ * @pdev:  A pointer to the platform device data structure.
+ */
+static int gpmi_nfc_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#else
+
+#define suspend  NULL
+#define resume   NULL
+
+#endif  /* CONFIG_PM */
+
+/*
+ * This structure represents this driver to the platform management system.
+ */
+static struct platform_driver gpmi_nfc_driver = {
+	.driver = {
+		.name = GPMI_NFC_DRIVER_NAME,
+	},
+	.probe   = gpmi_nfc_probe,
+	.remove  = __exit_p(gpmi_nfc_remove),
+	.suspend = gpmi_nfc_suspend,
+	.resume  = gpmi_nfc_resume,
+};
+
+/**
+ * gpmi_nfc_init() - Initializes this module.
+ */
+static int __init gpmi_nfc_init(void)
+{
+
+	pr_info("i.MX GPMI NFC\n");
+
+	/* Register this driver with the platform management system. */
+
+	if (platform_driver_register(&gpmi_nfc_driver) != 0) {
+		pr_err("i.MX GPMI NFC driver registration failed\n");
+		return -ENODEV;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * gpmi_nfc_exit() - Deactivates this module.
+ */
+static void __exit gpmi_nfc_exit(void)
+{
+	platform_driver_unregister(&gpmi_nfc_driver);
+}
+
+module_init(gpmi_nfc_init);
+module_exit(gpmi_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c
new file mode 100644
index 000000000000..50ba771853a4
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c
@@ -0,0 +1,2630 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * Indicates the driver should register the MTD that represents the entire
+ * medium, thus making it visible.
+ */
+
+static int register_main_mtd;
+module_param(register_main_mtd, int, 0400);
+
+/*
+ * Indicates the driver should attempt to perform DMA directly to/from buffers
+ * passed into this driver. This is true by default. If false, the driver will
+ * *always* copy incoming/outgoing data to/from its own DMA buffers.
+ */
+
+static int map_io_buffers = true;
+module_param(map_io_buffers, int, 0600);
+
+/**
+ * mil_outgoing_buffer_dma_begin() - Begins DMA on an outgoing buffer.
+ *
+ * @this:      Per-device data.
+ * @source:    The source buffer.
+ * @length:    The length of the data in the source buffer.
+ * @alt_virt:  The virtual address of an alternate buffer which is ready to be
+ *             used for DMA.
+ * @alt_phys:  The physical address of an alternate buffer which is ready to be
+ *             used for DMA.
+ * @alt_size:  The size of the alternate buffer.
+ * @use_virt:  A pointer to a variable that will receive the virtual address to
+ *             use.
+ * @use_phys:  A pointer to a variable that will receive the physical address to
+ *             use.
+ */
+static int mil_outgoing_buffer_dma_begin(struct gpmi_nfc_data *this,
+			const void *source, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			const void **use_virt, dma_addr_t *use_phys)
+{
+	struct device  *dev = this->dev;
+	dma_addr_t     source_phys = ~0;
+
+	/*
+	 * If we can, we want to use the caller's buffer directly for DMA. Check
+	 * if the system will let us map them.
+	 */
+
+	if (map_io_buffers && virt_addr_valid(source))
+		source_phys =
+			dma_map_single(dev,
+				(void *) source, length, DMA_TO_DEVICE);
+
+	if (dma_mapping_error(dev, source_phys)) {
+
+		/*
+		 * If control arrives here, we're not mapping the source buffer.
+		 * Make sure the alternate is large enough.
+		 */
+
+		if (alt_size < length) {
+			dev_err(dev, "Alternate buffer is too small "
+							"for outgoing I/O\n");
+			return -ENOMEM;
+		}
+
+		/*
+		 * Copy the contents of the source buffer into the alternate
+		 * buffer and set up the return values accordingly.
+		 */
+
+		memcpy(alt_virt, source, length);
+
+		*use_virt = alt_virt;
+		*use_phys = alt_phys;
+
+	} else {
+
+		/*
+		 * If control arrives here, we're mapping the source buffer. Set
+		 * up the return values accordingly.
+		 */
+
+		*use_virt = source;
+		*use_phys = source_phys;
+
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * mil_outgoing_buffer_dma_end() - Ends DMA on an outgoing buffer.
+ *
+ * @this:       Per-device data.
+ * @source:     The source buffer.
+ * @length:     The length of the data in the source buffer.
+ * @alt_virt:   The virtual address of an alternate buffer which was ready to be
+ *              used for DMA.
+ * @alt_phys:   The physical address of an alternate buffer which was ready to
+ *              be used for DMA.
+ * @alt_size:   The size of the alternate buffer.
+ * @used_virt:  The virtual address that was used.
+ * @used_phys:  The physical address that was used.
+ */
+static void mil_outgoing_buffer_dma_end(struct gpmi_nfc_data *this,
+		const void *source, unsigned length,
+		void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+		const void *used_virt, dma_addr_t used_phys)
+{
+	struct device  *dev = this->dev;
+
+	/*
+	 * Check if we used the source buffer, and it's not one of our own DMA
+	 * buffers. If so, we need to unmap it.
+	 */
+
+	if (used_virt == source)
+		dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE);
+
+}
+
+/**
+ * mil_incoming_buffer_dma_begin() - Begins DMA on an incoming buffer.
+ *
+ * @this:         Per-device data.
+ * @destination:  The destination buffer.
+ * @length:       The length of the data that will arrive.
+ * @alt_virt:     The virtual address of an alternate buffer which is ready
+ *                to be used for DMA.
+ * @alt_phys:     The physical address of an alternate buffer which is ready
+ *                to be used for DMA.
+ * @alt_size:     The size of the alternate buffer.
+ * @use_virt:     A pointer to a variable that will receive the virtual address
+ *                to use.
+ * @use_phys:     A pointer to a variable that will receive the physical address
+ *                to use.
+ */
+static int mil_incoming_buffer_dma_begin(struct gpmi_nfc_data *this,
+			void *destination, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			void **use_virt, dma_addr_t *use_phys)
+{
+	struct device  *dev = this->dev;
+	dma_addr_t     destination_phys = ~0;
+
+	/*
+	 * If we can, we want to use the caller's buffer directly for DMA. Check
+	 * if the system will let us map them.
+	 */
+	if (map_io_buffers && virt_addr_valid(destination) &&
+				!((int)destination & 0x3) && 0)
+		destination_phys =
+			dma_map_single(dev,
+				(void *) destination, length, DMA_FROM_DEVICE);
+
+	if (dma_mapping_error(dev, destination_phys)) {
+
+		/*
+		 * If control arrives here, we're not mapping the destination
+		 * buffer. Make sure the alternate is large enough.
+		 */
+
+		if (alt_size < length) {
+			dev_err(dev, "Alternate buffer is too small "
+							"for incoming I/O\n");
+			return -ENOMEM;
+		}
+
+		/* Set up the return values to use the alternate. */
+
+		*use_virt = alt_virt;
+		*use_phys = alt_phys;
+
+	} else {
+
+		/*
+		 * If control arrives here, we're mapping the destination
+		 * buffer. Set up the return values accordingly.
+		 */
+
+		*use_virt = destination;
+		*use_phys = destination_phys;
+
+	}
+
+	/* If control arrives here, all is well. */
+
+	return 0;
+
+}
+
+/**
+ * mil_incoming_buffer_dma_end() - Ends DMA on an incoming buffer.
+ *
+ * @this:         Per-device data.
+ * @destination:  The destination buffer.
+ * @length:       The length of the data that arrived.
+ * @alt_virt:     The virtual address of an alternate buffer which was ready to
+ *                be used for DMA.
+ * @alt_phys:     The physical address of an alternate buffer which was ready to
+ *                be used for DMA.
+ * @alt_size:     The size of the alternate buffer.
+ * @used_virt:    The virtual address that was used.
+ * @used_phys:    The physical address that was used.
+ */
+static void mil_incoming_buffer_dma_end(struct gpmi_nfc_data *this,
+			void *destination, unsigned length,
+			void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+			void *used_virt, dma_addr_t used_phys)
+{
+	struct device  *dev = this->dev;
+
+	/*
+	 * Check if we used the destination buffer, and it's not one of our own
+	 * DMA buffers. If so, we need to unmap it.
+	 */
+
+	if (used_virt == destination)
+		dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE);
+	else
+		memcpy(destination, alt_virt, length);
+
+}
+
+/**
+ * mil_cmd_ctrl - MTD Interface cmd_ctrl()
+ *
+ * This is the function that we install in the cmd_ctrl function pointer of the
+ * owning struct nand_chip. The only functions in the reference implementation
+ * that use these functions pointers are cmdfunc and select_chip.
+ *
+ * In this driver, we implement our own select_chip, so this function will only
+ * be called by the reference implementation's cmdfunc. For this reason, we can
+ * ignore the chip enable bit and concentrate only on sending bytes to the
+ * NAND Flash.
+ *
+ * @mtd:   The owning MTD.
+ * @data:  The value to push onto the data signals.
+ * @ctrl:  The values to push onto the control signals.
+ */
+static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+	struct nand_chip      *nand = mtd->priv;
+	struct gpmi_nfc_data  *this = nand->priv;
+	struct device         *dev  =  this->dev;
+	struct mil            *mil  = &this->mil;
+	struct nfc_hal        *nfc  =  this->nfc;
+	int                   error;
+#if defined(CONFIG_MTD_DEBUG)
+	unsigned int          i;
+	char                  display[MIL_COMMAND_BUFFER_SIZE * 5];
+#endif
+
+	/*
+	 * Every operation begins with a command byte and a series of zero or
+	 * more address bytes. These are distinguished by either the Address
+	 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+	 * asserted. When MTD is ready to execute the command, it will deassert
+	 * both latch enables.
+	 *
+	 * Rather than run a separate DMA operation for every single byte, we
+	 * queue them up and run a single DMA operation for the entire series
+	 * of command and data bytes.
+	 */
+
+	if ((ctrl & (NAND_ALE | NAND_CLE))) {
+		if (data != NAND_CMD_NONE)
+			mil->cmd_virt[mil->command_length++] = data;
+		return;
+	}
+
+	/*
+	 * If control arrives here, MTD has deasserted both the ALE and CLE,
+	 * which means it's ready to run an operation. Check if we have any
+	 * bytes to send.
+	 */
+
+	if (!mil->command_length)
+		return;
+
+	/* Hand the command over to the NFC. */
+
+	gpmi_nfc_add_event("mil_cmd_ctrl sending command...", 1);
+
+#if defined(CONFIG_MTD_DEBUG)
+	display[0] = 0;
+	for (i = 0; i < mil->command_length; i++)
+		sprintf(display + strlen(display), " 0x%02x",
+						mil->cmd_virt[i] & 0xff);
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc cmd_ctrl] command: %s\n", display);
+#endif
+
+	error = nfc->send_command(this,
+			mil->current_chip, mil->cmd_phys, mil->command_length);
+
+	if (error) {
+		dev_err(dev, "[%s] Chip: %u, Error %d\n",
+					__func__, mil->current_chip, error);
+		print_hex_dump(KERN_ERR,
+			"    Command Bytes: ", DUMP_PREFIX_NONE, 16, 1,
+					mil->cmd_virt, mil->command_length, 0);
+	}
+
+	gpmi_nfc_add_event("...Finished", -1);
+
+	/* Reset. */
+
+	mil->command_length = 0;
+
+}
+
+/**
+ * mil_dev_ready() - MTD Interface dev_ready()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ */
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip      *nand = mtd->priv;
+	struct gpmi_nfc_data  *this = nand->priv;
+	struct nfc_hal        *nfc  = this->nfc;
+	struct mil            *mil  = &this->mil;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc dev_ready]\n");
+
+	gpmi_nfc_add_event("> mil_dev_ready", 1);
+
+	if (nfc->is_ready(this, mil->current_chip)) {
+		gpmi_nfc_add_event("< mil_dev_ready - Returning ready", -1);
+		return !0;
+	} else {
+		gpmi_nfc_add_event("< mil_dev_ready - Returning busy", -1);
+		return 0;
+	}
+
+}
+
+/**
+ * mil_select_chip() - MTD Interface select_chip()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @chip:  The chip number to select, or -1 to select no chip.
+ */
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip      *nand  = mtd->priv;
+	struct gpmi_nfc_data  *this  = nand->priv;
+	struct mil            *mil   = &this->mil;
+	struct nfc_hal        *nfc   =  this->nfc;
+	struct clk            *clock =  this->resources.clock;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc select_chip] chip: %d\n", chip);
+
+	/* Figure out what kind of transition this is. */
+
+	if ((mil->current_chip < 0) && (chip >= 0)) {
+		gpmi_nfc_start_event_trace("> mil_select_chip");
+		clk_enable(clock);
+		nfc->begin(this);
+		gpmi_nfc_add_event("< mil_select_chip", -1);
+	} else if ((mil->current_chip >= 0) && (chip < 0)) {
+		gpmi_nfc_add_event("> mil_select_chip", 1);
+		gpmi_nfc_add_event("> not disable clk", 1);
+		clk_disable(clock);
+		nfc->end(this);
+		gpmi_nfc_stop_event_trace("< mil_select_chip");
+	} else {
+		gpmi_nfc_add_event("> mil_select_chip", 1);
+		gpmi_nfc_add_event("< mil_select_chip", -1);
+	}
+
+	mil->current_chip = chip;
+
+}
+
+/**
+ * mil_read_buf() - MTD Interface read_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The destination buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct nand_chip      *nand     = mtd->priv;
+	struct gpmi_nfc_data  *this     = nand->priv;
+	struct device         *dev      =  this->dev;
+	struct nfc_hal        *nfc      =  this->nfc;
+	struct nfc_geometry   *nfc_geo  = &this->nfc_geometry;
+	struct mil            *mil      = &this->mil;
+	void                  *use_virt =  0;
+	dma_addr_t            use_phys  = ~0;
+	int                   error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc readbuf] len: %d\n", len);
+
+	gpmi_nfc_add_event("> mil_read_buf", 1);
+
+	/* Set up DMA. */
+	error = mil_incoming_buffer_dma_begin(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&use_virt, &use_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		goto exit;
+	}
+
+	/* Ask the NFC. */
+
+	nfc->read_data(this, mil->current_chip, use_phys, len);
+
+	/* Finish with DMA. */
+
+	mil_incoming_buffer_dma_end(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					use_virt, use_phys);
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_read_buf", -1);
+
+}
+
+/**
+ * mil_write_buf() - MTD Interface write_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The source buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip      *nand     = mtd->priv;
+	struct gpmi_nfc_data  *this     = nand->priv;
+	struct device         *dev      =  this->dev;
+	struct nfc_hal        *nfc      =  this->nfc;
+	struct nfc_geometry   *nfc_geo  = &this->nfc_geometry;
+	struct mil            *mil      = &this->mil;
+	const void            *use_virt =  0;
+	dma_addr_t            use_phys  = ~0;
+	int                   error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc writebuf] len: %d\n", len);
+
+	gpmi_nfc_add_event("> mil_write_buf", 1);
+
+	/* Set up DMA. */
+
+	error = mil_outgoing_buffer_dma_begin(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&use_virt, &use_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		goto exit;
+	}
+
+	/* Ask the NFC. */
+
+	nfc->send_data(this, mil->current_chip, use_phys, len);
+
+	/* Finish with DMA. */
+
+	mil_outgoing_buffer_dma_end(this, buf, len,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					use_virt, use_phys);
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_write_buf", -1);
+
+}
+
+/**
+ * mil_read_byte() - MTD Interface read_byte().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+	uint8_t  byte;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]\n");
+
+	gpmi_nfc_add_event("> mil_read_byte", 1);
+
+	mil_read_buf(mtd, (uint8_t *) &byte, 1);
+
+	gpmi_nfc_add_event("< mil_read_byte", -1);
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc read_byte]: 0x%02x\n", byte);
+
+	return byte;
+
+}
+
+/**
+ * mil_handle_block_mark_swapping() - Handles block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ *
+ * @this:       Per-device data.
+ * @payload:    A pointer to the payload buffer.
+ * @auxiliary:  A pointer to the auxiliary buffer.
+ */
+static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
+						void *payload, void *auxiliary)
+{
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct boot_rom_helper  *rom     =  this->rom;
+	unsigned char           *p;
+	unsigned char           *a;
+	unsigned int            bit;
+	unsigned char           mask;
+	unsigned char           from_data;
+	unsigned char           from_oob;
+
+	/* Check if we're doing block mark swapping. */
+
+	if (!rom->swap_block_mark)
+		return;
+
+	/*
+	 * If control arrives here, we're swapping. Make some convenience
+	 * variables.
+	 */
+
+	bit = nfc_geo->block_mark_bit_offset;
+	p   = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset;
+	a   = auxiliary;
+
+	/*
+	 * Get the byte from the data area that overlays the block mark. Since
+	 * the ECC engine applies its own view to the bits in the page, the
+	 * physical block mark won't (in general) appear on a byte boundary in
+	 * the data.
+	 */
+
+	from_data = (p[0] >> bit) | (p[1] << (8 - bit));
+
+	/* Get the byte from the OOB. */
+
+	from_oob = a[0];
+
+	/* Swap them. */
+
+	a[0] = from_data;
+
+	mask = (0x1 << bit) - 1;
+	p[0] = (p[0] & mask) | (from_oob << bit);
+
+	mask = ~0 << bit;
+	p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
+
+}
+
+/**
+ * mil_ecc_read_page() - MTD Interface ecc.read_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the destination buffer.
+ */
+static int mil_ecc_read_page(struct mtd_info *mtd,
+					struct nand_chip *nand, uint8_t *buf)
+{
+	struct gpmi_nfc_data    *this    = nand->priv;
+	struct device           *dev     =  this->dev;
+	struct nfc_hal          *nfc     =  this->nfc;
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct mil              *mil     = &this->mil;
+	void                    *payload_virt   =  0;
+	dma_addr_t              payload_phys    = ~0;
+	void                    *auxiliary_virt =  0;
+	dma_addr_t              auxiliary_phys  = ~0;
+	unsigned int            i;
+	unsigned char           *status;
+	unsigned int            failed;
+	unsigned int            corrected;
+	int                     error = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_page]\n");
+
+	gpmi_nfc_add_event("> mil_ecc_read_page", 1);
+
+	/*
+	 * Set up DMA.
+	 *
+	 * Notice that we don't try to use the caller's buffer as the auxiliary.
+	 * We need to do a lot of fiddling to deliver the OOB, so there's no
+	 * point.
+	 */
+
+	error = mil_incoming_buffer_dma_begin(this, buf, mtd->writesize,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					&payload_virt, &payload_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__);
+		error = -ENOMEM;
+		goto exit_payload;
+	}
+
+	auxiliary_virt = mil->auxiliary_virt;
+	auxiliary_phys = mil->auxiliary_phys;
+
+	/* Ask the NFC. */
+
+	error = nfc->read_page(this, mil->current_chip,
+						payload_phys, auxiliary_phys);
+
+	if (error) {
+		dev_err(dev, "[%s] Error in ECC-based read: %d\n",
+							__func__, error);
+		goto exit_nfc;
+	}
+
+	/* Handle block mark swapping. */
+
+	mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
+
+	/* Loop over status bytes, accumulating ECC status. */
+
+	failed    = 0;
+	corrected = 0;
+
+	status = ((unsigned char *) auxiliary_virt) +
+					nfc_geo->auxiliary_status_offset;
+
+	for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) {
+
+		if ((*status == 0x00) || (*status == 0xff))
+			continue;
+
+		if (*status == 0xfe) {
+			failed++;
+			continue;
+		}
+
+		corrected += *status;
+
+	}
+
+	/* Propagate ECC status to the owning MTD. */
+
+	mtd->ecc_stats.failed    += failed;
+	mtd->ecc_stats.corrected += corrected;
+
+	/*
+	 * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
+	 * details about our policy for delivering the OOB.
+	 *
+	 * We fill the caller's buffer with set bits, and then copy the block
+	 * mark to th caller's buffer. Note that, if block mark swapping was
+	 * necessary, it has already been done, so we can rely on the first
+	 * byte of the auxiliary buffer to contain the block mark.
+	 */
+
+	memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+
+	/* Return. */
+
+exit_nfc:
+	mil_incoming_buffer_dma_end(this, buf, mtd->writesize,
+					mil->payload_virt, mil->payload_phys,
+					nfc_geo->payload_size_in_bytes,
+					payload_virt, payload_phys);
+exit_payload:
+
+	gpmi_nfc_add_event("< mil_ecc_read_page", -1);
+
+	return error;
+
+}
+
+/**
+ * mil_ecc_write_page() - MTD Interface ecc.write_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the source buffer.
+ */
+static void mil_ecc_write_page(struct mtd_info *mtd,
+				struct nand_chip *nand, const uint8_t *buf)
+{
+	struct gpmi_nfc_data    *this    = nand->priv;
+	struct device           *dev     =  this->dev;
+	struct nfc_hal          *nfc     =  this->nfc;
+	struct nfc_geometry     *nfc_geo = &this->nfc_geometry;
+	struct boot_rom_helper  *rom     =  this->rom;
+	struct mil              *mil     = &this->mil;
+	const void              *payload_virt   =  0;
+	dma_addr_t              payload_phys    = ~0;
+	const void              *auxiliary_virt =  0;
+	dma_addr_t              auxiliary_phys  = ~0;
+	int                     error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_write_page]\n");
+
+	gpmi_nfc_add_event("> mil_ecc_write_page", 1);
+
+	/* Set up DMA. */
+
+	if (rom->swap_block_mark) {
+
+		/*
+		 * If control arrives here, we're doing block mark swapping.
+		 * Since we can't modify the caller's buffers, we must copy them
+		 * into our own.
+		 */
+
+		memcpy(mil->payload_virt, buf, mtd->writesize);
+		payload_virt = mil->payload_virt;
+		payload_phys = mil->payload_phys;
+
+		memcpy(mil->auxiliary_virt, nand->oob_poi, mtd->oobsize);
+		auxiliary_virt = mil->auxiliary_virt;
+		auxiliary_phys = mil->auxiliary_phys;
+
+		/* Handle block mark swapping. */
+
+		mil_handle_block_mark_swapping(this,
+				(void *) payload_virt, (void *) auxiliary_virt);
+
+	} else {
+
+		/*
+		 * If control arrives here, we're not doing block mark swapping,
+		 * so we can to try and use the caller's buffers.
+		 */
+
+		error = mil_outgoing_buffer_dma_begin(this,
+				buf, mtd->writesize,
+				mil->payload_virt, mil->payload_phys,
+				nfc_geo->payload_size_in_bytes,
+				&payload_virt, &payload_phys);
+
+		if (error) {
+			dev_err(dev, "[%s] Inadequate payload DMA buffer\n",
+								__func__);
+			goto exit_payload;
+		}
+
+		error = mil_outgoing_buffer_dma_begin(this,
+				nand->oob_poi, mtd->oobsize,
+				mil->auxiliary_virt, mil->auxiliary_phys,
+				nfc_geo->auxiliary_size_in_bytes,
+				&auxiliary_virt, &auxiliary_phys);
+
+		if (error) {
+			dev_err(dev, "[%s] Inadequate auxiliary DMA buffer\n",
+								__func__);
+			goto exit_auxiliary;
+		}
+
+	}
+
+	/* Ask the NFC. */
+
+	error = nfc->send_page(this, mil->current_chip,
+						payload_phys, auxiliary_phys);
+
+	if (error)
+		dev_err(dev, "[%s] Error in ECC-based write: %d\n",
+							__func__, error);
+
+	/* Return. */
+
+	if (!rom->swap_block_mark)
+		mil_outgoing_buffer_dma_end(this, nand->oob_poi, mtd->oobsize,
+				mil->auxiliary_virt, mil->auxiliary_phys,
+				nfc_geo->auxiliary_size_in_bytes,
+				auxiliary_virt, auxiliary_phys);
+exit_auxiliary:
+	if (!rom->swap_block_mark)
+		mil_outgoing_buffer_dma_end(this, buf, mtd->writesize,
+				mil->payload_virt, mil->payload_phys,
+				nfc_geo->payload_size_in_bytes,
+				payload_virt, payload_phys);
+exit_payload:
+
+	gpmi_nfc_add_event("< mil_ecc_write_page", -1);
+
+}
+
+/**
+ * mil_hook_read_oob() - Hooked MTD Interface read_oob().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the raw_oob_mode field in
+ * struct mil for more information about this.
+ *
+ * @mtd:   A pointer to the MTD.
+ * @from:  The starting address to read.
+ * @ops:   Describes the operation.
+ */
+static int mil_hook_read_oob(struct mtd_info *mtd,
+					loff_t from, struct mtd_oob_ops *ops)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->raw_oob_mode = ops->mode == MTD_OOB_RAW;
+	ret = mil->hooked_read_oob(mtd, from, ops);
+	mil->raw_oob_mode = false;
+	return ret;
+}
+
+/**
+ * mil_hook_write_oob() - Hooked MTD Interface write_oob().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the raw_oob_mode field in
+ * struct mil for more information about this.
+ *
+ * @mtd:   A pointer to the MTD.
+ * @to:    The starting address to write.
+ * @ops:   Describes the operation.
+ */
+static int mil_hook_write_oob(struct mtd_info *mtd,
+					loff_t to, struct mtd_oob_ops *ops)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->raw_oob_mode = ops->mode == MTD_OOB_RAW;
+	ret = mil->hooked_write_oob(mtd, to, ops);
+	mil->raw_oob_mode = false;
+	return ret;
+}
+
+/**
+ * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the marking_a_bad_block field
+ * in struct mil for more information about this.
+ *
+ * @mtd:  A pointer to the MTD.
+ * @ofs:  Byte address of the block to mark.
+ */
+static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	register struct nand_chip  *chip = mtd->priv;
+	struct gpmi_nfc_data       *this = chip->priv;
+	struct mil                 *mil  = &this->mil;
+	int                        ret;
+
+	mil->marking_a_bad_block = true;
+	ret = mil->hooked_block_markbad(mtd, ofs);
+	mil->marking_a_bad_block = false;
+	return ret;
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
+ *
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ *    write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ *    true state of the block mark, no matter where that block mark appears in
+ *    the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ *    allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ *    return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ *    page, using the conventional definition of which bytes are data and which
+ *    are OOB. This gives the caller a way to see the actual, physical bytes
+ *    in the page, without the distortions applied by our ECC engine.
+ *
+ *
+ * What we do for this specific read operation depends on two questions:
+ *
+ * 1) Are we doing a "raw" read, or an ECC-based read?
+ *
+ * 2) Are we using block mark swapping or transcription?
+ *
+ * There are four cases, illustrated by the following Karnaugh map:
+ *
+ *                    |           Raw           |         ECC-based       |
+ *       -------------+-------------------------+-------------------------+
+ *                    | Read the conventional   |                         |
+ *                    | OOB at the end of the   |                         |
+ *       Swapping     | page and return it. It  |                         |
+ *                    | contains exactly what   |                         |
+ *                    | we want.                | Read the block mark and |
+ *       -------------+-------------------------+ return it in a buffer   |
+ *                    | Read the conventional   | full of set bits.       |
+ *                    | OOB at the end of the   |                         |
+ *                    | page and also the block |                         |
+ *       Transcribing | mark in the metadata.   |                         |
+ *                    | Copy the block mark     |                         |
+ *                    | into the first byte of  |                         |
+ *                    | the OOB.                |                         |
+ *       -------------+-------------------------+-------------------------+
+ *
+ * Note that we break rule #4 in the Transcribing/Raw case because we're not
+ * giving an accurate view of the actual, physical bytes in the page (we're
+ * overwriting the block mark). That's OK because it's more important to follow
+ * rule #2.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * Since our OOB *is* covered by ECC, we need this information. So, we hook the
+ * ecc.read_oob and ecc.write_oob function pointers in the owning
+ * struct mtd_info with our own functions. These hook functions set the
+ * raw_oob_mode field so that, when control finally arrives here, we'll know
+ * what to do.
+ *
+ * @mtd:     A pointer to the owning MTD.
+ * @nand:    A pointer to the owning NAND Flash MTD.
+ * @page:    The page number to read.
+ * @sndcmd:  Indicates this function should send a command to the chip before
+ *           reading the out-of-band bytes. This is only false for small page
+ *           chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+							int page, int sndcmd)
+{
+	struct gpmi_nfc_data      *this     = nand->priv;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct boot_rom_helper    *rom      =  this->rom;
+	int                       block_mark_column;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_oob] "
+		"page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No");
+
+	gpmi_nfc_add_event("> mil_ecc_read_oob", 1);
+
+	/*
+	 * First, fill in the OOB buffer. If we're doing a raw read, we need to
+	 * get the bytes from the physical page. If we're not doing a raw read,
+	 * we need to fill the buffer with set bits.
+	 */
+
+	if (mil->raw_oob_mode) {
+
+		/*
+		 * If control arrives here, we're doing a "raw" read. Send the
+		 * command to read the conventional OOB.
+		 */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0,
+				physical->page_data_size_in_bytes, page);
+
+		/* Read out the conventional OOB. */
+
+		nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+
+	} else {
+
+		/*
+		 * If control arrives here, we're not doing a "raw" read. Fill
+		 * the OOB buffer with set bits.
+		 */
+
+		memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	}
+
+	/*
+	 * Now, we want to make sure the block mark is correct. In the
+	 * Swapping/Raw case, we already have it. Otherwise, we need to
+	 * explicitly read it.
+	 */
+
+	if (!(rom->swap_block_mark && mil->raw_oob_mode)) {
+
+		/* First, figure out where the block mark is. */
+
+		if (rom->swap_block_mark)
+			block_mark_column = physical->page_data_size_in_bytes;
+		else
+			block_mark_column = 0;
+
+		/* Send the command to read the block mark. */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0, block_mark_column, page);
+
+		/* Read the block mark into the first byte of the OOB buffer. */
+
+		nand->oob_poi[0] = nand->read_byte(mtd);
+
+	}
+
+	/*
+	 * Return true, indicating that the next call to this function must send
+	 * a command.
+	 */
+
+	gpmi_nfc_add_event("< mil_ecc_read_oob", -1);
+
+	return true;
+
+}
+
+/**
+ * mil_ecc_write_oob() - MTD Interface ecc.write_oob().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @page:  The page number to write.
+ */
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+					struct nand_chip *nand, int page)
+{
+	struct gpmi_nfc_data      *this     = nand->priv;
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct boot_rom_helper    *rom      =  this->rom;
+	uint8_t                   block_mark = 0;
+	int                       block_mark_column;
+	int                       status;
+	int                       error = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL2,
+			"[gpmi_nfc ecc_write_oob] page: 0x%06x\n", page);
+
+	gpmi_nfc_add_event("> mil_ecc_write_oob", -1);
+
+	/*
+	 * There are fundamental incompatibilities between the i.MX GPMI NFC and
+	 * the NAND Flash MTD model that make it essentially impossible to write
+	 * the out-of-band bytes.
+	 *
+	 * We permit *ONE* exception. If the *intent* of writing the OOB is to
+	 * mark a block bad, we can do that.
+	 */
+
+	if (!mil->marking_a_bad_block) {
+		dev_emerg(dev, "This driver doesn't support writing the OOB\n");
+		WARN_ON(1);
+		error = -EIO;
+		goto exit;
+	}
+
+	/*
+	 * If control arrives here, we're marking a block bad. First, figure out
+	 * where the block mark is.
+	 *
+	 * If we're using swapping, the block mark is in the conventional
+	 * location. Otherwise, we're using transcription, and the block mark
+	 * appears in the first byte of the page.
+	 */
+
+	if (rom->swap_block_mark)
+		block_mark_column = physical->page_data_size_in_bytes;
+	else
+		block_mark_column = 0;
+
+	/* Write the block mark. */
+
+	nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
+	nand->write_buf(mtd, &block_mark, 1);
+	nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = nand->waitfunc(mtd, nand);
+
+	/* Check if it worked. */
+
+	if (status & NAND_STATUS_FAIL)
+		error = -EIO;
+
+	/* Return. */
+
+exit:
+
+	gpmi_nfc_add_event("< mil_ecc_write_oob", -1);
+
+	return error;
+
+}
+
+/**
+ * mil_block_bad - Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
+ * which indicates that all blocks should be reported good.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ *
+ * @mtd:      Ignored.
+ * @ofs:      Ignored.
+ * @getchip:  Ignored.
+ */
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+	return 0;
+}
+
+/**
+ * mil_set_physical_geometry() - Set up the physical medium geometry.
+ *
+ * This function retrieves the physical geometry information discovered by
+ * nand_scan(), corrects it, and records it in the per-device data structure.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_physical_geometry(struct gpmi_nfc_data  *this)
+{
+	struct mil                *mil      = &this->mil;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nand_chip          *nand     = &mil->nand;
+	struct nand_device_info   *info     = &this->device_info;
+	unsigned int              block_size_in_pages;
+	unsigned int              chip_size_in_blocks;
+	unsigned int              chip_size_in_pages;
+	uint64_t                  medium_size_in_bytes;
+
+	/*
+	 * Record the number of physical chips that MTD found.
+	 */
+
+	physical->chip_count = nand->numchips;
+
+	/*
+	 * We know the total size of a page. We need to break that down into the
+	 * data size and OOB size. The data size is the largest power of two
+	 * that will fit in the given page size. The OOB size is what's left
+	 * over.
+	 */
+
+	physical->page_data_size_in_bytes =
+				1 << (fls(info->page_total_size_in_bytes) - 1);
+
+	physical->page_oob_size_in_bytes =
+				info->page_total_size_in_bytes -
+					physical->page_data_size_in_bytes;
+
+	/*
+	 * Now that we know the page data size, we can multiply this by the
+	 * number of pages in a block to compute the block size.
+	 */
+
+	physical->block_size_in_bytes =
+		physical->page_data_size_in_bytes * info->block_size_in_pages;
+
+	/* Get the chip size. */
+
+	physical->chip_size_in_bytes = info->chip_size_in_bytes;
+
+	/* Compute some interesting facts. */
+
+	block_size_in_pages  =
+			physical->block_size_in_bytes >>
+				(fls(physical->page_data_size_in_bytes) - 1);
+	chip_size_in_pages   =
+			physical->chip_size_in_bytes >>
+				(fls(physical->page_data_size_in_bytes) - 1);
+	chip_size_in_blocks  =
+			physical->chip_size_in_bytes >>
+				(fls(physical->block_size_in_bytes) - 1);
+	medium_size_in_bytes =
+			physical->chip_size_in_bytes * physical->chip_count;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("-----------------\n");
+	pr_info("Physical Geometry\n");
+	pr_info("-----------------\n");
+	pr_info("Chip Count             : %d\n", physical->chip_count);
+	pr_info("Page Data Size in Bytes: %u (0x%x)\n",
+			physical->page_data_size_in_bytes,
+			physical->page_data_size_in_bytes);
+	pr_info("Page OOB Size in Bytes : %u\n",
+			physical->page_oob_size_in_bytes);
+	pr_info("Block Size in Bytes    : %u (0x%x)\n",
+			physical->block_size_in_bytes,
+			physical->block_size_in_bytes);
+	pr_info("Block Size in Pages    : %u (0x%x)\n",
+			block_size_in_pages,
+			block_size_in_pages);
+	pr_info("Chip Size in Bytes     : %llu (0x%llx)\n",
+			physical->chip_size_in_bytes,
+			physical->chip_size_in_bytes);
+	pr_info("Chip Size in Pages     : %u (0x%x)\n",
+			chip_size_in_pages, chip_size_in_pages);
+	pr_info("Chip Size in Blocks    : %u (0x%x)\n",
+			chip_size_in_blocks, chip_size_in_blocks);
+	pr_info("Medium Size in Bytes   : %llu (0x%llx)\n",
+			medium_size_in_bytes, medium_size_in_bytes);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_nfc_geometry() - Set up the NFC geometry.
+ *
+ * This function calls the NFC HAL to select an NFC geometry that is compatible
+ * with the medium's physical geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_nfc_geometry(struct gpmi_nfc_data  *this)
+{
+	struct nfc_hal       *nfc =  this->nfc;
+#if defined(DETAILED_INFO)
+	struct nfc_geometry  *geo = &this->nfc_geometry;
+#endif
+	/* Set the NFC geometry. */
+
+	if (nfc->set_geometry(this))
+		return !0;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("------------\n");
+	pr_info("NFC Geometry\n");
+	pr_info("------------\n");
+	pr_info("ECC Algorithm          : %s\n", geo->ecc_algorithm);
+	pr_info("ECC Strength           : %u\n", geo->ecc_strength);
+	pr_info("Page Size in Bytes     : %u\n", geo->page_size_in_bytes);
+	pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
+	pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
+	pr_info("ECC Chunk Count        : %u\n", geo->ecc_chunk_count);
+	pr_info("Payload Size in Bytes  : %u\n", geo->payload_size_in_bytes);
+	pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
+	pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+	pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+	pr_info("Block Mark Bit Offset  : %u\n", geo->block_mark_bit_offset);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_boot_rom_helper_geometry() - Set up the Boot ROM Helper geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data  *this)
+{
+	struct boot_rom_helper    *rom =  this->rom;
+#if defined(DETAILED_INFO)
+	struct boot_rom_geometry  *geo = &this->rom_geometry;
+#endif
+
+	/* Set the Boot ROM Helper geometry. */
+
+	if (rom->set_geometry(this))
+		return !0;
+
+	/* Report. */
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("-----------------\n");
+	pr_info("Boot ROM Geometry\n");
+	pr_info("-----------------\n");
+	pr_info("Boot Area Count            : %u\n", geo->boot_area_count);
+	pr_info("Boot Area Size in Bytes    : %u (0x%x)\n",
+		geo->boot_area_size_in_bytes, geo->boot_area_size_in_bytes);
+	pr_info("Stride Size in Pages       : %u\n", geo->stride_size_in_pages);
+	pr_info("Search Area Stride Exponent: %u\n",
+					geo->search_area_stride_exponent);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_mtd_geometry() - Set up the MTD geometry.
+ *
+ * This function adjusts the owning MTD data structures to match the logical
+ * geometry we've chosen.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_mtd_geometry(struct gpmi_nfc_data *this)
+{
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct mil                *mil      = &this->mil;
+	struct nand_ecclayout     *layout   = &mil->oob_layout;
+	struct nand_chip          *nand     = &mil->nand;
+	struct mtd_info           *mtd      = &mil->mtd;
+
+	/* Configure the struct nand_ecclayout. */
+
+	layout->eccbytes          = 0;
+	layout->oobavail          = physical->page_oob_size_in_bytes;
+	layout->oobfree[0].offset = 0;
+	layout->oobfree[0].length = physical->page_oob_size_in_bytes;
+
+	/* Configure the struct mtd_info. */
+
+	mtd->size        = nand->numchips * physical->chip_size_in_bytes;
+	mtd->erasesize   = physical->block_size_in_bytes;
+	mtd->writesize   = physical->page_data_size_in_bytes;
+	mtd->ecclayout   = layout;
+	mtd->oobavail    = mtd->ecclayout->oobavail;
+	mtd->oobsize     = mtd->ecclayout->oobavail + mtd->ecclayout->eccbytes;
+	mtd->subpage_sft = 0; /* We don't support sub-page writing. */
+
+	/* Configure the struct nand_chip. */
+
+	nand->chipsize         = physical->chip_size_in_bytes;
+	nand->page_shift       = ffs(mtd->writesize) - 1;
+	nand->pagemask         = (nand->chipsize >> nand->page_shift) - 1;
+	nand->subpagesize      = mtd->writesize >> mtd->subpage_sft;
+	nand->phys_erase_shift = ffs(mtd->erasesize) - 1;
+	nand->bbt_erase_shift  = nand->phys_erase_shift;
+	nand->oob_poi          = nand->buffers->databuf + mtd->writesize;
+	nand->ecc.layout       = layout;
+	if (nand->chipsize & 0xffffffff)
+		nand->chip_shift = ffs((unsigned) nand->chipsize) - 1;
+	else
+		nand->chip_shift =
+				ffs((unsigned) (nand->chipsize >> 32)) + 32 - 1;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_set_geometry() - Set up the medium geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_set_geometry(struct gpmi_nfc_data  *this)
+{
+	struct device        *dev      =  this->dev;
+	struct nfc_geometry  *nfc_geo  = &this->nfc_geometry;
+	struct mil           *mil      = &this->mil;
+
+
+	/* Free the memory for read ID case */
+	if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt))
+		dma_free_coherent(dev, nfc_geo->payload_size_in_bytes,
+				mil->page_buffer_virt, mil->page_buffer_phys);
+
+	/* Set up the various layers of geometry, in this specific order. */
+
+	if (mil_set_physical_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_nfc_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_boot_rom_helper_geometry(this))
+		return -ENXIO;
+
+	if (mil_set_mtd_geometry(this))
+		return -ENXIO;
+
+	/*
+	 * Allocate the page buffer.
+	 *
+	 * Both the payload buffer and the auxiliary buffer must appear on
+	 * 32-bit boundaries. We presume the size of the payload buffer is a
+	 * power of two and is much larger than four, which guarantees the
+	 * auxiliary buffer will appear on a 32-bit boundary.
+	 */
+
+	mil->page_buffer_size = nfc_geo->payload_size_in_bytes +
+					nfc_geo->auxiliary_size_in_bytes;
+
+	mil->page_buffer_virt =
+		dma_alloc_coherent(dev, mil->page_buffer_size,
+					&mil->page_buffer_phys, GFP_DMA);
+
+	if (!mil->page_buffer_virt)
+		return -ENOMEM;
+
+	/* Slice up the page buffer. */
+
+	mil->payload_virt = mil->page_buffer_virt;
+	mil->payload_phys = mil->page_buffer_phys;
+
+	mil->auxiliary_virt = ((char *) mil->payload_virt) +
+						nfc_geo->payload_size_in_bytes;
+	mil->auxiliary_phys = mil->payload_phys +
+						nfc_geo->payload_size_in_bytes;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_pre_bbt_scan() - Prepare for the BBT scan.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_pre_bbt_scan(struct gpmi_nfc_data  *this)
+{
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_helper    *rom      =  this->rom;
+	struct mil                *mil      = &this->mil;
+	struct nand_chip          *nand     = &mil->nand;
+	struct mtd_info           *mtd      = &mil->mtd;
+	unsigned int              block_count;
+	unsigned int              block;
+	int                       chip;
+	int                       page;
+	loff_t                    byte;
+	uint8_t                   block_mark;
+	int                       error;
+
+	/*
+	 * Check if we can use block mark swapping, which enables us to leave
+	 * the block marks where they are. If so, we don't need to do anything
+	 * at all.
+	 */
+
+	if (rom->swap_block_mark)
+		return 0;
+
+	/*
+	 * If control arrives here, we can't use block mark swapping, which
+	 * means we're forced to use transcription. First, scan for the
+	 * transcription stamp. If we find it, then we don't have to do
+	 * anything -- the block marks are already transcribed.
+	 */
+
+	if (rom->check_transcription_stamp(this))
+		return 0;
+
+	/*
+	 * If control arrives here, we couldn't find a transcription stamp, so
+	 * so we presume the block marks are in the conventional location.
+	 */
+
+	pr_info("Transcribing bad block marks...\n");
+
+	/* Compute the number of blocks in the entire medium. */
+
+	block_count =
+		physical->chip_size_in_bytes >> nand->phys_erase_shift;
+
+	/*
+	 * Loop over all the blocks in the medium, transcribing block marks as
+	 * we go.
+	 */
+
+	for (block = 0; block < block_count; block++) {
+
+		/*
+		 * Compute the chip, page and byte addresses for this block's
+		 * conventional mark.
+		 */
+
+		chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+		page = block << (nand->phys_erase_shift - nand->page_shift);
+		byte = block <<  nand->phys_erase_shift;
+
+		/* Select the chip. */
+
+		nand->select_chip(mtd, chip);
+
+		/* Send the command to read the conventional block mark. */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0,
+				physical->page_data_size_in_bytes, page);
+
+		/* Read the conventional block mark. */
+
+		block_mark = nand->read_byte(mtd);
+
+		/*
+		 * Check if the block is marked bad. If so, we need to mark it
+		 * again, but this time the result will be a mark in the
+		 * location where we transcribe block marks.
+		 *
+		 * Notice that we have to explicitly set the marking_a_bad_block
+		 * member before we call through the block_markbad function
+		 * pointer in the owning struct nand_chip. If we could call
+		 * though the block_markbad function pointer in the owning
+		 * struct mtd_info, which we have hooked, then this would be
+		 * taken care of for us. Unfortunately, we can't because that
+		 * higher-level code path will do things like consulting the
+		 * in-memory bad block table -- which doesn't even exist yet!
+		 * So, we have to call at a lower level and handle some details
+		 * ourselves.
+		 */
+
+		if (block_mark != 0xff) {
+			pr_info("Transcribing mark in block %u\n", block);
+			mil->marking_a_bad_block = true;
+			error = nand->block_markbad(mtd, byte);
+			mil->marking_a_bad_block = false;
+			if (error)
+				dev_err(dev, "Failed to mark block bad with "
+							"error %d\n", error);
+		}
+
+		/* Deselect the chip. */
+
+		nand->select_chip(mtd, -1);
+
+	}
+
+	/* Write the stamp that indicates we've transcribed the block marks. */
+
+	rom->write_transcription_stamp(this);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_scan_bbt() - MTD Interface scan_bbt().
+ *
+ * The HIL calls this function once, when it initializes the NAND Flash MTD.
+ *
+ * Nominally, the purpose of this function is to look for or create the bad
+ * block table. In fact, since the HIL calls this function at the very end of
+ * the initialization process started by nand_scan(), and the HIL doesn't have a
+ * more formal mechanism, everyone "hooks" this function to continue the
+ * initialization process.
+ *
+ * At this point, the physical NAND Flash chips have been identified and
+ * counted, so we know the physical geometry. This enables us to make some
+ * important configuration decisions.
+ *
+ * The return value of this function propogates directly back to this driver's
+ * call to nand_scan(). Anything other than zero will cause this driver to
+ * tear everything down and declare failure.
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip         *nand = mtd->priv;
+	struct gpmi_nfc_data     *this = nand->priv;
+	struct nfc_hal           *nfc  =  this->nfc;
+	struct mil               *mil  = &this->mil;
+	int                      saved_chip_number;
+	uint8_t                  id_bytes[NAND_DEVICE_ID_BYTE_COUNT];
+	struct nand_device_info  *info;
+	struct gpmi_nfc_timing   timing;
+	int                      error;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc scan_bbt] \n");
+
+	/*
+	 * Tell MTD users that the out-of-band area can't be written.
+	 *
+	 * This flag is not part of the standard kernel source tree. It comes
+	 * from a patch that touches both MTD and JFFS2.
+	 *
+	 * The problem is that, without this patch, JFFS2 believes it can write
+	 * the data area and the out-of-band area separately. This is wrong for
+	 * two reasons:
+	 *
+	 *     1)  Our NFC distributes out-of-band bytes throughout the page,
+	 *         intermingled with the data, and covered by the same ECC.
+	 *         Thus, it's not possible to write the out-of-band bytes and
+	 *         data bytes separately.
+	 *
+	 *     2)  Large page (MLC) Flash chips don't support partial page
+	 *         writes. You must write the entire page at a time. Thus, even
+	 *         if our NFC didn't force you to write out-of-band and data
+	 *         bytes together, it would *still* be a bad idea to do
+	 *         otherwise.
+	 */
+
+	mtd->flags &= ~MTD_OOB_WRITEABLE;
+
+	/*
+	 * MTD identified the attached NAND Flash devices, but we have a much
+	 * better database that we want to consult. First, we need to gather all
+	 * the ID bytes from the first chip (MTD only read the first two).
+	 */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	nand->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
+	nand->read_buf(mtd, id_bytes, NAND_DEVICE_ID_BYTE_COUNT);
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Look up this device in our database. */
+
+	info = nand_device_get_info(id_bytes);
+
+	/* Check if we understand this device. */
+
+	if (!info) {
+		pr_err("Unrecognized NAND Flash device.\n");
+		return !0;
+	}
+
+	/* Display the information we discovered. */
+
+	#if defined(DETAILED_INFO)
+	pr_info("-----------------------------\n");
+	pr_info("NAND Flash Device Information\n");
+	pr_info("-----------------------------\n");
+	nand_device_print_info(info);
+	#endif
+
+	/*
+	 * Copy the device info into the per-device data. We can't just keep
+	 * the pointer because that storage is reclaimed after initialization.
+	 */
+
+	this->device_info = *info;
+	this->device_info.description = kstrdup(info->description, GFP_KERNEL);
+
+	/* Set up geometry. */
+
+	error = mil_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/* Set up timing. */
+
+	timing.data_setup_in_ns        = info->data_setup_in_ns;
+	timing.data_hold_in_ns         = info->data_hold_in_ns;
+	timing.address_setup_in_ns     = info->address_setup_in_ns;
+	timing.gpmi_sample_delay_in_ns = info->gpmi_sample_delay_in_ns;
+	timing.tREA_in_ns              = info->tREA_in_ns;
+	timing.tRLOH_in_ns             = info->tRLOH_in_ns;
+	timing.tRHOH_in_ns             = info->tRHOH_in_ns;
+
+	error = nfc->set_timing(this, &timing);
+
+	if (error)
+		return error;
+
+	/* Prepare for the BBT scan. */
+
+	error = mil_pre_bbt_scan(this);
+
+	if (error)
+		return error;
+
+	/* We use the reference implementation for bad block management. */
+
+	error = nand_default_bbt(mtd);
+
+	if (error)
+		return error;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_boot_areas_init() - Initializes boot areas.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_boot_areas_init(struct gpmi_nfc_data *this)
+{
+	struct device                  *dev      =  this->dev;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct boot_rom_geometry       *rom      = &this->rom_geometry;
+	struct mil                     *mil      = &this->mil;
+	struct mtd_info                *mtd      = &mil->mtd;
+	struct nand_chip               *nand     = &mil->nand;
+	int                            mtd_support_is_adequate;
+	unsigned int                   i;
+	struct mtd_partition           partitions[4];
+	struct mtd_info                *search_mtd;
+	struct mtd_info                *chip_0_remainder_mtd = 0;
+	struct mtd_info                *medium_remainder_mtd = 0;
+	struct mtd_info                *concatenate[2];
+
+	/*
+	 * Here we declare the static strings we use to name partitions. We use
+	 * static strings because, as of 2.6.31, the partitioning code *always*
+	 * registers the partition MTDs it creates and leaves behind *no* other
+	 * trace of its work. So, once we've created a partition, we must search
+	 * the master MTD table to find the MTDs we created. Since we're using
+	 * static strings, we can simply search the master table for an MTD with
+	 * a name field pointing to a known address.
+	 */
+
+	static char  *chip_0_boot_name      = "gpmi-nfc-0-boot";
+	static char  *chip_0_remainder_name = "gpmi-nfc-0-remainder";
+	static char  *chip_1_boot_name      = "gpmi-nfc-1-boot";
+	static char  *medium_remainder_name = "gpmi-nfc-remainder";
+	static char  *general_use_name      = "gpmi-nfc-general-use";
+
+	/* Check if we're protecting the boot areas.*/
+
+	if (!rom->boot_area_count) {
+
+		/*
+		 * If control arrives here, we're not protecting the boot areas.
+		 * In this case, there are not boot area partitons, and the main
+		 * MTD is the general use MTD.
+		 */
+
+		mil->general_use_mtd = &mil->mtd;
+
+		return 0;
+
+	}
+
+	/*
+	 * If control arrives here, we're protecting the boot areas. Check if we
+	 * have the MTD support we need.
+	 */
+
+	pr_info("Boot area protection is enabled.\n");
+
+	if (rom->boot_area_count > 1) {
+
+		/*
+		 * If the Boot ROM wants more than one boot area, then we'll
+		 * need to create partitions *and* concatenate them.
+		 */
+
+		#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+			mtd_support_is_adequate = true;
+		#else
+			mtd_support_is_adequate = false;
+		#endif
+
+	} else if (rom->boot_area_count == 1) {
+
+		/*
+		 * If the Boot ROM wants only one boot area, then we only need
+		 * to create partitions -- we don't need to concatenate them.
+		 */
+
+		#if defined(CONFIG_MTD_PARTITIONS)
+			mtd_support_is_adequate = true;
+		#else
+			mtd_support_is_adequate = false;
+		#endif
+
+	} else {
+
+		/*
+		 * If control arrives here, we're protecting the boot area, but
+		 * somehow the boot area count was set to zero. This doesn't
+		 * make any sense.
+		 */
+
+		dev_err(dev, "Internal error: boot area count is "
+						"incorrectly set to zero.");
+		return -ENXIO;
+
+	}
+
+	if (!mtd_support_is_adequate) {
+		dev_err(dev, "Configured MTD support is inadequate to "
+						"protect the boot area(s).");
+		return -ENXIO;
+	}
+
+	/*
+	 * If control arrives here, we're protecting boot areas and we have
+	 * everything we need to do so.
+	 *
+	 * We have special code to handle the case for one boot area.
+	 *
+	 * The code that handles "more than one" boot area actually only handles
+	 * two. We *could* write the general case, but that would take a lot of
+	 * time to both write and test -- and, right now, we don't have a chip
+	 * that cares.
+	 */
+
+	/* Check if a boot area is larger than a single chip. */
+
+	if (rom->boot_area_size_in_bytes > physical->chip_size_in_bytes) {
+		dev_emerg(dev, "Boot area size is larger than a chip");
+		return -ENXIO;
+	}
+
+	if (rom->boot_area_count == 1) {
+
+#if defined(CONFIG_MTD_PARTITIONS)
+
+		/*
+		 * We partition the medium like so:
+		 *
+		 * +------+----------------------------------------------------+
+		 * | Boot |                    General Use                     |
+		 * +------+----------------------------------------------------+
+		 */
+
+		/* Chip 0 Boot */
+
+		partitions[0].name       = chip_0_boot_name;
+		partitions[0].offset     = 0;
+		partitions[0].size       = rom->boot_area_size_in_bytes;
+		partitions[0].mask_flags = 0;
+
+		/* General Use */
+
+		partitions[1].name       = general_use_name;
+		partitions[1].offset     = rom->boot_area_size_in_bytes;
+		partitions[1].size       = MTDPART_SIZ_FULL;
+		partitions[1].mask_flags = 0;
+
+		/* Construct and register the partitions. */
+
+		add_mtd_partitions(mtd, partitions, 2);
+
+		/* Find the general use MTD. */
+
+		for (i = 0; i < MAX_MTD_DEVICES; i++) {
+
+			/* Get the current MTD so we can examine it. */
+
+			search_mtd = get_mtd_device(0, i);
+
+			/* Check if we got nonsense. */
+
+			if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV)))
+				continue;
+
+			/* Check if the current MTD is one of our remainders. */
+
+			if (search_mtd->name == general_use_name)
+				mil->general_use_mtd = search_mtd;
+
+			/* Put the MTD back. We only wanted a quick look. */
+
+			put_mtd_device(search_mtd);
+
+		}
+
+		if (!mil->general_use_mtd) {
+			dev_emerg(dev, "Can't find general use MTD");
+			BUG();
+		}
+
+#endif
+
+	} else if (rom->boot_area_count == 2) {
+
+#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+
+		/*
+		 * If control arrives here, there is more than one boot area.
+		 * We partition the medium and concatenate the remainders like
+		 * so:
+		 *
+		 *  --- Chip 0 ---   --- Chip 1 --- ... ------- Chip N -------
+		 * /              \ /                                         \
+		 * +----+----------+----+--------------- ... ------------------+
+		 * |Boot|Remainder |Boot|              Remainder               |
+		 * +----+----------+----+--------------- ... ------------------+
+		 *      |          |   /                                      /
+		 *      |          |  /                                      /
+		 *      |          | /                                      /
+		 *      |          |/                                      /
+		 *      +----------+----------- ... ----------------------+
+		 *      |                   General Use                   |
+		 *      +---------------------- ... ----------------------+
+		 *
+		 * Notice that the results we leave in the master MTD table
+		 * look like this:
+		 *
+		 *    * Chip 0 Boot Area
+		 *    * Chip 1 Boot Area
+		 *    * General Use
+		 *
+		 * Some user space programs expect the boot partitions to
+		 * appear first. This is naive, but let's try not to cause
+		 * any trouble, where we can avoid it.
+		 */
+
+		/* Chip 0 Boot */
+
+		partitions[0].name       = chip_0_boot_name;
+		partitions[0].offset     = 0;
+		partitions[0].size       = rom->boot_area_size_in_bytes;
+		partitions[0].mask_flags = 0;
+
+		/* Chip 1 Boot */
+
+		partitions[1].name       = chip_1_boot_name;
+		partitions[1].offset     = nand->chipsize;
+		partitions[1].size       = rom->boot_area_size_in_bytes;
+		partitions[1].mask_flags = 0;
+
+		/* Chip 0 Remainder */
+
+		partitions[2].name       = chip_0_remainder_name;
+		partitions[2].offset     = rom->boot_area_size_in_bytes;
+		partitions[2].size       = nand->chipsize -
+						rom->boot_area_size_in_bytes;
+		partitions[2].mask_flags = 0;
+
+		/* Medium Remainder */
+
+		partitions[3].name       = medium_remainder_name;
+		partitions[3].offset     = nand->chipsize +
+						rom->boot_area_size_in_bytes;
+		partitions[3].size       = MTDPART_SIZ_FULL;
+		partitions[3].mask_flags = 0;
+
+		/* Construct and register the partitions. */
+
+		add_mtd_partitions(mtd, partitions, 4);
+
+		/* Find the remainder partitions. */
+
+		for (i = 0; i < MAX_MTD_DEVICES; i++) {
+
+			/* Get the current MTD so we can examine it. */
+
+			search_mtd = get_mtd_device(0, i);
+
+			/* Check if we got nonsense. */
+
+			if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV)))
+				continue;
+
+			/* Check if the current MTD is one of our remainders. */
+
+			if (search_mtd->name == chip_0_remainder_name)
+				chip_0_remainder_mtd = search_mtd;
+
+			if (search_mtd->name == medium_remainder_name)
+				medium_remainder_mtd = search_mtd;
+
+			/* Put the MTD back. We only wanted a quick look. */
+
+			put_mtd_device(search_mtd);
+
+		}
+
+		if (!chip_0_remainder_mtd || !medium_remainder_mtd) {
+			dev_emerg(dev, "Can't find remainder partitions");
+			BUG();
+		}
+
+		/*
+		 * Unregister the remainder MTDs. Note that we are *not*
+		 * destroying these MTDs -- we're just removing from the
+		 * globally-visible list. There's no need for anyone to see
+		 * these.
+		 */
+
+		del_mtd_device(chip_0_remainder_mtd);
+		del_mtd_device(medium_remainder_mtd);
+
+		/* Concatenate the remainders and register the result. */
+
+		concatenate[0] = chip_0_remainder_mtd;
+		concatenate[1] = medium_remainder_mtd;
+
+		mil->general_use_mtd = mtd_concat_create(concatenate,
+							2, general_use_name);
+
+		add_mtd_device(mil->general_use_mtd);
+
+#endif
+
+	} else {
+		dev_err(dev, "Boot area count greater than two is "
+							"unimplemented.\n");
+		return -ENXIO;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_boot_areas_exit() - Shuts down boot areas.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_boot_areas_exit(struct gpmi_nfc_data *this)
+{
+	struct boot_rom_geometry  *rom = &this->rom_geometry;
+	struct mil                *mil = &this->mil;
+	struct mtd_info           *mtd = &mil->mtd;
+
+	/* Check if we're protecting the boot areas.*/
+
+	if (!rom->boot_area_count) {
+
+		/*
+		 * If control arrives here, we're not protecting the boot areas.
+		 * That means we never created any boot area partitions, and the
+		 * general use MTD is just the main MTD.
+		 */
+
+		mil->general_use_mtd = 0;
+
+		return;
+
+	}
+
+	/*
+	 * If control arrives here, we're protecting the boot areas.
+	 *
+	 * Start by checking if there is more than one boot area. If so, then
+	 * we both partitioned the medium and then concatenated some of the
+	 * partitions to form the general use MTD. The first step is to get rid
+	 * of the concatenation.
+	 */
+
+	#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT)
+		if (rom->boot_area_count > 1) {
+				del_mtd_device(mil->general_use_mtd);
+				mtd_concat_destroy(mil->general_use_mtd);
+		}
+	#endif
+
+	/*
+	 * At this point, we're left only with the partitions of the main MTD.
+	 * Delete them.
+	 */
+
+	#if defined(CONFIG_MTD_PARTITIONS)
+		del_mtd_partitions(mtd);
+	#endif
+
+	/* The general use MTD no longer exists. */
+
+	mil->general_use_mtd = 0;
+
+}
+
+/**
+ * mil_construct_ubi_partitions() - Constructs partitions for UBI.
+ *
+ * MTD uses a 64-bit value to express the size of MTDs, but UBI is still using
+ * a 32-bit value. For this reason, UBI can't work on top of an MTD with size
+ * greater than 2GiB. In this function, we examine the general use MTD and, if
+ * it's larger than 2GiB, we construct a set of partitions for that MTD such
+ * that none are too large for UBI to comprehend.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_construct_ubi_partitions(struct gpmi_nfc_data *this)
+{
+#if defined(CONFIG_MTD_PARTITIONS)
+	struct device                  *dev   =  this->dev;
+	struct mil                     *mil   = &this->mil;
+	unsigned int                   partition_count;
+	struct mtd_partition           *partitions;
+	unsigned int                   name_size;
+	char                           *names;
+	unsigned int                   memory_block_size;
+	unsigned int                   i;
+
+	static const char              *name_prefix = "gpmi-nfc-ubi-";
+
+	/*
+	 * If the general use MTD isn't larger than 2GiB, we have nothing to do.
+	 */
+
+	if (mil->general_use_mtd->size <= SZ_2G)
+		return;
+
+	/*
+	 * If control arrives here, the general use MTD is larger than 2GiB. We
+	 * need to split it up into some number of partitions. Find out how many
+	 * 2GiB partitions we'll be creating.
+	 */
+
+	partition_count = mil->general_use_mtd->size >> 31;
+
+	/*
+	 * If the MTD size doesn't evenly divide by 2GiB, we'll need another
+	 * partition to hold the extra.
+	 */
+
+	if (mil->general_use_mtd->size & ((1 << 30) - 1))
+		partition_count++;
+
+	/*
+	 * We're going to allocate a single memory block to contain all the
+	 * partition structures and their names. Calculate how large it must be.
+	 */
+
+	name_size = strlen(name_prefix) + 4;
+
+	memory_block_size = (sizeof(*partitions) + name_size) * partition_count;
+
+	/*
+	 * Attempt to allocate the block.
+	 */
+
+	partitions = kzalloc(memory_block_size, GFP_KERNEL);
+
+	if (!partitions) {
+		dev_err(dev, "Could not allocate memory for UBI partitions.\n");
+		return;
+	}
+
+	names = (char *)(partitions + partition_count);
+
+	/* Loop over partitions, filling in the details. */
+
+	for (i = 0; i < partition_count; i++) {
+
+		partitions[i].name   = names;
+		partitions[i].size   = SZ_2G;
+		partitions[i].offset = MTDPART_OFS_NXTBLK;
+
+		sprintf(names, "%s%u", name_prefix, i);
+		names += name_size;
+
+	}
+
+	/* Adjust the last partition to take up the remainder. */
+
+	partitions[i - 1].size = MTDPART_SIZ_FULL;
+
+	/* Record everything in the device data structure.  */
+
+	mil->partitions           = partitions;
+	mil->partition_count      = partition_count;
+	mil->ubi_partition_memory = partitions;
+
+#endif
+}
+
+/**
+ * mil_partitions_init() - Initializes partitions.
+ *
+ * @this:  Per-device data.
+ */
+static int mil_partitions_init(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata =  this->pdata;
+	struct mil                     *mil   = &this->mil;
+	struct mtd_info                *mtd   = &mil->mtd;
+	int                            error;
+
+	/*
+	 * Set up the boot areas. When this function returns, if there has been
+	 * no error, the boot area partitions (if any) will have been created
+	 * and registered. Also, the general_use_mtd field will point to an MTD
+	 * we can use.
+	 */
+
+	error = mil_boot_areas_init(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * If we've been told to, register the MTD that represents the entire
+	 * medium. Normally, we don't register the main MTD because we only want
+	 * to expose the medium through the boot area partitions and the general
+	 * use partition.
+	 *
+	 * We do this *after* setting up the boot areas because, for historical
+	 * reasons, we like the lowest-numbered MTDs to be the boot areas.
+	 */
+
+	if (register_main_mtd) {
+		pr_info("Registering the main MTD.\n");
+		add_mtd_device(mtd);
+	}
+
+#if defined(CONFIG_MTD_PARTITIONS)
+
+	/*
+	 * If control arrives here, partitioning is available.
+	 *
+	 * There are three possible sets of partitions we might apply, in order
+	 * of decreasing priority:
+	 *
+	 * 1) Partitions dynamically discovered from sources defined by the
+	 *    platform. These can come from, for example, the command line or
+	 *    a partition table.
+	 *
+	 * 2) Partitions attached to the platform data.
+	 *
+	 * 3) Partitions we generate to deal with limitations in UBI.
+	 *
+	 * Recall that the pointer to the general use MTD *may* just point to
+	 * the main MTD.
+	 */
+
+	/*
+	 * First, try to get partition information from the sources defined by
+	 * the platform.
+	 */
+
+	if (pdata->partition_source_types)
+		mil->partition_count =
+			parse_mtd_partitions(mil->general_use_mtd,
+						pdata->partition_source_types,
+						&mil->partitions, 0);
+
+	/*
+	 * Check if we got anything. If not, then accept whatever partitions are
+	 * attached to the platform data.
+	 */
+
+	if ((mil->partition_count <= 0) && (pdata->partitions)) {
+		mil->partition_count = mil->partition_count;
+		mil->partitions      = mil->partitions;
+	}
+
+	/*
+	 * If we still don't have any partitions to apply, then we might want to
+	 * apply some of our own, to account for UBI's limitations.
+	 */
+
+	if (!mil->partition_count)
+		mil_construct_ubi_partitions(this);
+
+	/* If we came up with any partitions, apply them. */
+
+	if (mil->partition_count)
+		add_mtd_partitions(mil->general_use_mtd,
+					mil->partitions,
+					mil->partition_count);
+
+#endif
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mil_partitions_exit() - Shuts down partitions.
+ *
+ * @this:  Per-device data.
+ */
+static void mil_partitions_exit(struct gpmi_nfc_data *this)
+{
+	struct mil       *mil   = &this->mil;
+	struct mtd_info  *mtd   = &mil->mtd;
+
+	/* Check if we applied any partitions to the general use MTD. */
+
+	#if defined(CONFIG_MTD_PARTITIONS)
+
+		if (mil->partition_count)
+			del_mtd_partitions(mil->general_use_mtd);
+
+		kfree(mil->ubi_partition_memory);
+
+	#endif
+
+	/*
+	 * If we were told to register the MTD that represents the entire
+	 * medium, unregister it now. Note that this does *not* "destroy" the
+	 * MTD - it merely unregisters it. That's important because all our
+	 * other MTDs depend on this one.
+	 */
+
+	if (register_main_mtd)
+		del_mtd_device(mtd);
+
+	/* Tear down the boot areas. */
+
+	mil_boot_areas_exit(this);
+
+}
+
+/**
+ * gpmi_nfc_mil_init() - Initializes the MTD Interface Layer.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_mil_init(struct gpmi_nfc_data *this)
+{
+	struct device                  *dev   =  this->dev;
+	struct gpmi_nfc_platform_data  *pdata =  this->pdata;
+	struct mil                     *mil   = &this->mil;
+	struct mtd_info                *mtd   = &mil->mtd;
+	struct nand_chip               *nand  = &mil->nand;
+	static struct nand_ecclayout   fake_ecc_layout;
+	int                            error = 0;
+
+	/* Initialize MIL data. */
+
+	mil->current_chip   = -1;
+	mil->command_length =  0;
+
+	mil->page_buffer_virt =  0;
+	mil->page_buffer_phys = ~0;
+	mil->page_buffer_size =  0;
+
+	/* Initialize the MTD data structures. */
+
+	mtd->priv  = nand;
+	mtd->name  = "gpmi-nfc-main";
+	mtd->owner = THIS_MODULE;
+	nand->priv = this;
+
+	/*
+	 * Signal Control
+	 */
+
+	nand->cmd_ctrl = mil_cmd_ctrl;
+
+	/*
+	 * Chip Control
+	 *
+	 * We rely on the reference implementations of:
+	 *     - cmdfunc
+	 *     - waitfunc
+	 */
+
+	nand->dev_ready   = mil_dev_ready;
+	nand->select_chip = mil_select_chip;
+
+	/*
+	 * Low-level I/O
+	 *
+	 * We don't support a 16-bit NAND Flash bus, so we don't implement
+	 * read_word.
+	 *
+	 * We rely on the reference implentation of verify_buf.
+	 */
+
+	nand->read_byte = mil_read_byte;
+	nand->read_buf  = mil_read_buf;
+	nand->write_buf = mil_write_buf;
+
+	/*
+	 * ECC Control
+	 *
+	 * None of these functions are necessary for us:
+	 *     - ecc.hwctl
+	 *     - ecc.calculate
+	 *     - ecc.correct
+	 */
+
+	/*
+	 * ECC-aware I/O
+	 *
+	 * We rely on the reference implementations of:
+	 *     - ecc.read_page_raw
+	 *     - ecc.write_page_raw
+	 */
+
+	nand->ecc.read_page  = mil_ecc_read_page;
+	nand->ecc.write_page = mil_ecc_write_page;
+
+	/*
+	 * High-level I/O
+	 *
+	 * We rely on the reference implementations of:
+	 *     - write_page
+	 *     - erase_cmd
+	 */
+
+	nand->ecc.read_oob  = mil_ecc_read_oob;
+	nand->ecc.write_oob = mil_ecc_write_oob;
+
+	/*
+	 * Bad Block Management
+	 *
+	 * We rely on the reference implementations of:
+	 *     - block_bad
+	 *     - block_markbad
+	 */
+
+	nand->block_bad = mil_block_bad;
+	nand->scan_bbt  = mil_scan_bbt;
+
+	/*
+	 * Error Recovery Functions
+	 *
+	 * We don't fill in the errstat function pointer because it's optional
+	 * and we don't have a need for it.
+	 */
+
+	/*
+	 * Set up NAND Flash options. Specifically:
+	 *
+	 *     - Disallow partial page writes.
+	 */
+
+	nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+	/*
+	 * Tell the NAND Flash MTD system that we'll be handling ECC with our
+	 * own hardware. It turns out that we still have to fill in the ECC size
+	 * because the MTD code will divide by it -- even though it doesn't
+	 * actually care.
+	 */
+
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.size = 1;
+
+	/*
+	 * Install a "fake" ECC layout.
+	 *
+	 * We'll be calling nand_scan() to do the final MTD setup. If we haven't
+	 * already chosen an ECC layout, then nand_scan() will choose one based
+	 * on the part geometry it discovers. Unfortunately, it doesn't make
+	 * good choices. It would be best if we could install the correct ECC
+	 * layout now, before we call nand_scan(). We can't do that because we
+	 * don't know the medium geometry yet. Here, we install a "fake" ECC
+	 * layout just to stop nand_scan() from trying to pick one for itself.
+	 * Later, when we know the medium geometry, we'll install the correct
+	 * one.
+	 *
+	 * Of course, this tactic depends critically on the MTD code not doing
+	 * an I/O operation that depends on the ECC layout being sensible. This
+	 * is in fact the case.
+	 */
+
+	memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
+
+	nand->ecc.layout = &fake_ecc_layout;
+
+	/* Allocate a command buffer. */
+
+	mil->cmd_virt =
+		dma_alloc_coherent(dev,
+			MIL_COMMAND_BUFFER_SIZE, &mil->cmd_phys, GFP_DMA);
+
+	if (!mil->cmd_virt) {
+		error = -ENOMEM;
+		goto exit_cmd_allocation;
+	}
+
+
+	/* Allocate buf  read ID case */
+	this->nfc_geometry.payload_size_in_bytes = 1024;
+	mil->page_buffer_virt =
+		dma_alloc_coherent(dev,
+				this->nfc_geometry.payload_size_in_bytes,
+				&mil->page_buffer_phys, GFP_DMA);
+
+	if (!mil->page_buffer_virt) {
+		error = -ENOMEM;
+		goto exit_buf_allocation;
+	}
+
+	/* Slice up the page buffer. */
+	mil->payload_virt = mil->page_buffer_virt;
+	mil->payload_phys = mil->page_buffer_phys;
+
+	/*
+	 * Ask the NAND Flash system to scan for chips.
+	 *
+	 * This will fill in reference implementations for all the members of
+	 * the MTD structures that we didn't set, and will make the medium fully
+	 * usable.
+	 */
+
+	pr_info("Scanning for NAND Flash chips...\n");
+
+	error = nand_scan(mtd, pdata->max_chip_count);
+
+	if (error) {
+		dev_err(dev, "Chip scan failed\n");
+		goto exit_nand_scan;
+	}
+
+	/*
+	 * Hook some operations at the MTD level. See the descriptions of the
+	 * saved function pointer fields for details about why we hook these.
+	 */
+
+	mil->hooked_read_oob      = mtd->read_oob;
+	mtd->read_oob             = mil_hook_read_oob;
+
+	mil->hooked_write_oob     = mtd->write_oob;
+	mtd->write_oob            = mil_hook_write_oob;
+
+	mil->hooked_block_markbad = mtd->block_markbad;
+	mtd->block_markbad        = mil_hook_block_markbad;
+
+	/* Construct partitions as necessary. */
+
+	error = mil_partitions_init(this);
+
+	if (error)
+		goto exit_partitions;
+
+	/* Return success. */
+
+	return 0;
+
+	/* Control arrives here if something went wrong. */
+
+exit_partitions:
+	nand_release(&mil->mtd);
+exit_nand_scan:
+	dma_free_coherent(dev,
+			this->nfc_geometry.payload_size_in_bytes,
+			mil->page_buffer_virt, mil->page_buffer_phys);
+	mil->page_buffer_virt = 0;
+	mil->page_buffer_phys = ~0;
+exit_buf_allocation:
+	dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE,
+			mil->cmd_virt, mil->cmd_phys);
+	mil->cmd_virt =  0;
+	mil->cmd_phys = ~0;
+exit_cmd_allocation:
+
+	return error;
+
+}
+
+/**
+ * gpmi_nfc_mil_exit() - Shuts down the MTD Interface Layer.
+ *
+ * @this:  Per-device data.
+ */
+void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this)
+{
+	struct device  *dev = this->dev;
+	struct mil     *mil = &this->mil;
+
+	/* Shut down partitions as necessary. */
+
+	mil_partitions_exit(this);
+
+	/* Get MTD to let go of our MTD. */
+
+	nand_release(&mil->mtd);
+
+	/* Free the page buffer, if it's been allocated. */
+
+	if (mil->page_buffer_virt)
+		dma_free_coherent(dev, mil->page_buffer_size,
+				mil->page_buffer_virt, mil->page_buffer_phys);
+
+	mil->page_buffer_size =  0;
+	mil->page_buffer_virt =  0;
+	mil->page_buffer_phys = ~0;
+
+	/* Free the command buffer, if it's been allocated. */
+
+	if (mil->cmd_virt)
+		dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE,
+						mil->cmd_virt, mil->cmd_phys);
+
+	mil->cmd_virt =  0;
+	mil->cmd_phys = ~0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c
new file mode 100644
index 000000000000..0cd0b39141fd
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c
@@ -0,0 +1,59 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * gpmi_nfc_rom_helper_set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this)
+{
+	struct boot_rom_geometry  *geometry = &this->rom_geometry;
+
+	/*
+	 * Set the boot block stride size.
+	 *
+	 * In principle, we should be reading this from the OTP bits, since
+	 * that's where the ROM is going to get it. In fact, we don't have any
+	 * way to read the OTP bits, so we go with the default and hope for the
+	 * best.
+	 */
+
+	geometry->stride_size_in_pages = 64;
+
+	/*
+	 * Set the search area stride exponent.
+	 *
+	 * In principle, we should be reading this from the OTP bits, since
+	 * that's where the ROM is going to get it. In fact, we don't have any
+	 * way to read the OTP bits, so we go with the default and hope for the
+	 * best.
+	 */
+
+	geometry->search_area_stride_exponent = 2;
+
+	/* Return success. */
+
+	return 0;
+
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c
new file mode 100644
index 000000000000..35321cc25546
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c
@@ -0,0 +1,297 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/*
+ * Useful variables for Boot ROM Helper version 0.
+ */
+
+static const char  *fingerprint = "STMP";
+
+/**
+ * set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct physical_geometry       *physical = &this->physical_geometry;
+	struct boot_rom_geometry       *geometry = &this->rom_geometry;
+	int                             error;
+
+	/* Version-independent geometry. */
+
+	error = gpmi_nfc_rom_helper_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * Check if the platform data indicates we are to protect the boot area.
+	 */
+
+	if (!pdata->boot_area_size_in_bytes) {
+		geometry->boot_area_count         = 0;
+		geometry->boot_area_size_in_bytes = 0;
+		return 0;
+	}
+
+	/*
+	 * If control arrives here, we are supposed to set up partitions to
+	 * protect the boot areas. In this version of the ROM, the number of
+	 * boot areas and their size depends on the number of chips.
+	 */
+
+	if (physical->chip_count == 1) {
+		geometry->boot_area_count = 1;
+		geometry->boot_area_size_in_bytes =
+					pdata->boot_area_size_in_bytes * 2;
+	} else {
+		geometry->boot_area_count = 2;
+		geometry->boot_area_size_in_bytes =
+					pdata->boot_area_size_in_bytes;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * check_transcription_stamp() - Checks for a transcription stamp.
+ *
+ * Returns 0 if a stamp is not found.
+ *
+ * @this:  Per-device data.
+ */
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_geometry  *rom_geo  = &this->rom_geometry;
+	struct mil                *mil      = &this->mil;
+	struct mtd_info           *mtd      = &mil->mtd;
+	struct nand_chip          *nand     = &mil->nand;
+	unsigned int              search_area_size_in_strides;
+	unsigned int              stride;
+	unsigned int              page;
+	loff_t                    byte;
+	uint8_t                   *buffer = nand->buffers->databuf;
+	int                       saved_chip_number;
+	int                       found_an_ncb_fingerprint = false;
+
+	/* Compute the number of strides in a search area. */
+
+	search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+	/* Select chip 0. */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	/*
+	 * Loop through the first search area, looking for the NCB fingerprint.
+	 */
+
+	pr_info("Scanning for an NCB fingerprint...\n");
+
+	for (stride = 0; stride < search_area_size_in_strides; stride++) {
+
+		/* Compute the page and byte addresses. */
+
+		page = stride * rom_geo->stride_size_in_pages;
+		byte = page   * physical->page_data_size_in_bytes;
+
+		pr_info("  Looking for a fingerprint in page 0x%x\n", page);
+
+		/*
+		 * Read the NCB fingerprint. The fingerprint is four bytes long
+		 * and starts in the 12th byte of the page.
+		 */
+
+		nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+		nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+		/* Look for the fingerprint. */
+
+		if (!memcmp(buffer, fingerprint,
+					strlen(fingerprint))) {
+			found_an_ncb_fingerprint = true;
+			break;
+		}
+
+	}
+
+	/* Deselect chip 0. */
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Return. */
+
+	if (found_an_ncb_fingerprint)
+		pr_info("  Found a fingerprint\n");
+	else
+		pr_info("  No fingerprint found\n");
+
+	return found_an_ncb_fingerprint;
+
+}
+
+/**
+ * write_transcription_stamp() - Writes a transcription stamp.
+ *
+ * @this:  Per-device data.
+ */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+	struct device             *dev      =  this->dev;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct boot_rom_geometry  *rom_geo  = &this->rom_geometry;
+	struct mil                *mil      = &this->mil;
+	struct mtd_info           *mtd      = &mil->mtd;
+	struct nand_chip          *nand     = &mil->nand;
+	unsigned int              block_size_in_pages;
+	unsigned int              search_area_size_in_strides;
+	unsigned int              search_area_size_in_pages;
+	unsigned int              search_area_size_in_blocks;
+	unsigned int              block;
+	unsigned int              stride;
+	unsigned int              page;
+	loff_t                    byte;
+	uint8_t                   *buffer = nand->buffers->databuf;
+	int                       saved_chip_number;
+	int                       status;
+
+	/* Compute the search area geometry. */
+
+	block_size_in_pages = physical->block_size_in_bytes >>
+				(ffs(physical->page_data_size_in_bytes) - 1);
+
+	search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+	search_area_size_in_pages = search_area_size_in_strides *
+						rom_geo->stride_size_in_pages;
+
+	search_area_size_in_blocks =
+		  (search_area_size_in_pages + (block_size_in_pages - 1)) /
+		/*-------------------------------------------------------*/
+				    block_size_in_pages;
+
+	#if defined(DETAILED_INFO)
+
+	pr_info("--------------------\n");
+	pr_info("Search Area Geometry\n");
+	pr_info("--------------------\n");
+	pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+	pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+	pr_info("Search Area Size in Pages  : %u", search_area_size_in_pages);
+
+	#endif
+
+	/* Select chip 0. */
+
+	saved_chip_number = mil->current_chip;
+	nand->select_chip(mtd, 0);
+
+	/* Loop over blocks in the first search area, erasing them. */
+
+	pr_info("Erasing the search area...\n");
+
+	for (block = 0; block < search_area_size_in_blocks; block++) {
+
+		/* Compute the page address. */
+
+		page = block * block_size_in_pages;
+
+		/* Erase this block. */
+
+		pr_info("  Erasing block 0x%x\n", block);
+
+		nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+		nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+		/* Wait for the erase to finish. */
+
+		status = nand->waitfunc(mtd, nand);
+
+		if (status & NAND_STATUS_FAIL)
+			dev_err(dev, "[%s] Erase failed.\n", __func__);
+
+	}
+
+	/* Write the NCB fingerprint into the page buffer. */
+
+	memset(buffer, ~0, mtd->writesize);
+	memset(nand->oob_poi, ~0, mtd->oobsize);
+
+	memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+	/* Loop through the first search area, writing NCB fingerprints. */
+
+	pr_info("Writing NCB fingerprints...\n");
+
+	for (stride = 0; stride < search_area_size_in_strides; stride++) {
+
+		/* Compute the page and byte addresses. */
+
+		page = stride * rom_geo->stride_size_in_pages;
+		byte = page   * physical->page_data_size_in_bytes;
+
+		/* Write the first page of the current stride. */
+
+		pr_info("  Writing an NCB fingerprint in page 0x%x\n", page);
+
+		nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+		nand->ecc.write_page_raw(mtd, nand, buffer);
+		nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+		/* Wait for the write to finish. */
+
+		status = nand->waitfunc(mtd, nand);
+
+		if (status & NAND_STATUS_FAIL)
+			dev_err(dev, "[%s] Write failed.\n", __func__);
+
+	}
+
+	/* Deselect chip 0. */
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+
+struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v0 = {
+	.version                   = 0,
+	.description               = "Single/dual-chip boot area, "
+						"no block mark swapping",
+	.swap_block_mark           = false,
+	.set_geometry              = set_geometry,
+	.check_transcription_stamp = check_transcription_stamp,
+	.write_transcription_stamp = write_transcription_stamp,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c
new file mode 100644
index 000000000000..49cb329ccdd4
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c
@@ -0,0 +1,82 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "gpmi-nfc.h"
+
+/**
+ * set_geometry() - Sets geometry for the Boot ROM Helper.
+ *
+ * @this:  Per-device data.
+ */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct boot_rom_geometry       *geometry = &this->rom_geometry;
+	int                            error;
+
+	/* Version-independent geometry. */
+
+	error = gpmi_nfc_rom_helper_set_geometry(this);
+
+	if (error)
+		return error;
+
+	/*
+	 * Check if the platform data indicates we are to protect the boot area.
+	 */
+
+	if (!pdata->boot_area_size_in_bytes) {
+		geometry->boot_area_count         = 0;
+		geometry->boot_area_size_in_bytes = 0;
+		return 0;
+	}
+
+	/*
+	 * If control arrives here, we are supposed to set up partitions to
+	 * protect the boot areas. In this version of the ROM, we support only
+	 * one boot area.
+	 */
+
+	geometry->boot_area_count = 1;
+
+	/*
+	 * Use the platform's boot area size.
+	 */
+
+	geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+
+struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v1 = {
+	.version                   = 1,
+	.description               = "Single-chip boot area, "
+						"block mark swapping supported",
+	.swap_block_mark           = true,
+	.set_geometry              = set_geometry,
+	.check_transcription_stamp = 0,
+	.write_transcription_stamp = 0,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
new file mode 100644
index 000000000000..9b0074532917
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
@@ -0,0 +1,645 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
+#define __DRIVERS_MTD_NAND_GPMI_NFC_H
+
+/* Linux header files. */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+#include <linux/gpmi-nfc.h>
+#include <asm/sizes.h>
+
+/* Platform header files. */
+
+#include <mach/system.h>
+#include <mach/dmaengine.h>
+#include <mach/clock.h>
+
+/* Driver header files. */
+
+#include "../nand_device_info.h"
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Macros
+ *------------------------------------------------------------------------------
+ */
+
+/* Define this macro to enable detailed information messages. */
+
+#define DETAILED_INFO
+
+/* Define this macro to enable event reporting. */
+
+/*#define EVENT_REPORTING*/
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Data Structures
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * struct resources - The collection of resources the driver needs.
+ *
+ * @gpmi_regs:         A pointer to the GPMI registers.
+ * @bch_regs:          A pointer to the BCH registers.
+ * @bch_interrupt:     The BCH interrupt number.
+ * @dma_low_channel:   The low  DMA channel.
+ * @dma_high_channel:  The high DMA channel.
+ * @dma_interrupt:     The DMA interrupt number.
+ * @clock:             A pointer to the struct clk for the NFC's clock.
+ */
+
+struct resources {
+	void          *gpmi_regs;
+	void          *bch_regs;
+	unsigned int  bch_low_interrupt;
+	unsigned int  bch_high_interrupt;
+	unsigned int  dma_low_channel;
+	unsigned int  dma_high_channel;
+	unsigned int  dma_low_interrupt;
+	unsigned int  dma_high_interrupt;
+	struct clk    *clock;
+};
+
+/**
+ * struct mil - State for the MTD Interface Layer.
+ *
+ * @nand:                    The NAND Flash MTD data structure that represents
+ *                           the NAND Flash medium.
+ * @mtd:                     The MTD data structure that represents the NAND
+ *                           Flash medium.
+ * @oob_layout:              A structure that describes how bytes are laid out
+ *                           in the OOB.
+ * @general_use_mtd:         A pointer to an MTD we export for general use.
+ *                           This *may* simply be a pointer to the mtd field, if
+ *                           we've been instructed NOT to protect the boot
+ *                           areas.
+ * @partitions:              A pointer to a set of partitions applied to the
+ *                           general use MTD.
+ * @partition_count:         The number of partitions.
+ * @ubi_partition_memory:    If not NULL, a block of memory used to create a set
+ *                           of partitions that help with the problem that UBI
+ *                           can't handle an MTD larger than 2GiB.
+ * @current_chip:            The chip currently selected by the NAND Fash MTD
+ *                           code. A negative value indicates that no chip is
+ *                           selected.
+ * @command_length:          The length of the command that appears in the
+ *                           command buffer (see cmd_virt, below).
+ * @inject_ecc_error:        Indicates the driver should inject a "fake" ECC
+ *                           error into the next read operation that uses ECC.
+ *                           User space programs can set this value through the
+ *                           sysfs node of the same name. If this value is less
+ *                           than zero, the driver will inject an uncorrectable
+ *                           ECC error. If this value is greater than zero, the
+ *                           driver will inject that number of correctable
+ *                           errors, capped by the maximum possible number of
+ *                           errors that could appear in a single read.
+ * @ignore_bad_block_marks:  Indicates we are ignoring bad block marks.
+ * @saved_bbt:               A saved pointer to the in-memory NAND Flash MTD bad
+ *                           block table. See show_device_ignorebad() for more
+ *                           details.
+ * @raw_oob_mode:            Indicates the OOB is to be read/written in "raw"
+ *                           mode. See mil_ecc_read_oob() for details.
+ * @hooked_read_oob:         A pointer to the ecc.read_oob() function we
+ *                           "hooked." See mil_ecc_read_oob() for details.
+ * @hooked_write_oob:        A pointer to the ecc.write_oob() function pointer
+ *                           we "hooked." See mil_ecc_read_oob() for details.
+ * @marking_a_bad_block:     Indicates the caller is marking a bad block. See
+ *                           mil_ecc_write_oob() for details.
+ * @hooked_block_markbad:    A pointer to the block_markbad() function we
+ *                           we "hooked." See mil_ecc_write_oob() for details.
+ * @cmd_virt:                A pointer to a DMA-coherent buffer in which we
+ *                           accumulate command bytes before we give them to the
+ *                           NFC layer. See mil_cmd_ctrl() for more details.
+ * @cmd_phys:                The physical address for the cmd_virt buffer.
+ * @page_buffer_virt:        A pointer to a DMA-coherent buffer we use for
+ *                           reading and writing pages. This buffer includes
+ *                           space for both the payload data and the auxiliary
+ *                           data (including status bytes, but not syndrome
+ *                           bytes).
+ * @page_buffer_phys:        The physical address for the page_buffer_virt
+ *                           buffer.
+ * @page_buffer_size:        The size of the page buffer.
+ * @payload_virt:            A pointer to a location in the page buffer used
+ *                           for payload bytes. The size of this buffer is
+ *                           determined by struct nfc_geometry.
+ * @payload_phys:            The physical address for payload_virt.
+ * @payload_size:            The size of the payload area in the page buffer.
+ * @auxiliary_virt:          A pointer to a location in the page buffer used
+ *                           for auxiliary bytes. The size of this buffer is
+ *                           determined by struct nfc_geometry.
+ * @auxiliary_phys:          The physical address for auxiliary_virt.
+ * @auxiliary_size:          The size of the auxiliary area in the page buffer.
+ */
+
+#define MIL_COMMAND_BUFFER_SIZE (10)
+
+struct mil {
+
+	/* MTD Data Structures */
+
+	struct nand_chip       nand;
+	struct mtd_info        mtd;
+	struct nand_ecclayout  oob_layout;
+
+	/* Partitioning and Boot Area Protection */
+
+	struct mtd_info        *general_use_mtd;
+	struct mtd_partition   *partitions;
+	unsigned int           partition_count;
+	void                   *ubi_partition_memory;
+
+	/* General-use Variables */
+
+	int                    current_chip;
+	unsigned int           command_length;
+	int                    inject_ecc_error;
+	int                    ignore_bad_block_marks;
+	void                   *saved_bbt;
+
+	/* MTD Function Pointer Hooks */
+
+	int                    raw_oob_mode;
+	int                    (*hooked_read_oob)(struct mtd_info *mtd,
+					loff_t from, struct mtd_oob_ops *ops);
+	int                    (*hooked_write_oob)(struct mtd_info *mtd,
+					loff_t to, struct mtd_oob_ops *ops);
+
+	int                    marking_a_bad_block;
+	int                    (*hooked_block_markbad)(struct mtd_info *mtd,
+					loff_t ofs);
+
+	/* DMA Buffers */
+
+	char                   *cmd_virt;
+	dma_addr_t             cmd_phys;
+
+	void                   *page_buffer_virt;
+	dma_addr_t             page_buffer_phys;
+	unsigned int           page_buffer_size;
+
+	void                   *payload_virt;
+	dma_addr_t             payload_phys;
+
+	void                   *auxiliary_virt;
+	dma_addr_t             auxiliary_phys;
+
+};
+
+/**
+ * struct physical_geometry - Physical geometry description.
+ *
+ * This structure describes the physical geometry of the medium.
+ *
+ * @chip_count:                    The number of chips in the medium.
+ * @chip_size_in_bytes:            The size, in bytes, of a single chip
+ *                                 (excluding the out-of-band bytes).
+ * @block_size_in_bytes:           The size, in bytes, of a single block
+ *                                 (excluding the out-of-band bytes).
+ * @page_data_size_in_bytes:       The size, in bytes, of the data area in a
+ *                                 page (excluding the out-of-band bytes).
+ * @page_oob_size_in_bytes:        The size, in bytes, of the out-of-band area
+ *                                 in a page.
+ */
+
+struct physical_geometry {
+	unsigned int  chip_count;
+	uint64_t      chip_size_in_bytes;
+	unsigned int  block_size_in_bytes;
+	unsigned int  page_data_size_in_bytes;
+	unsigned int  page_oob_size_in_bytes;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry.
+ *
+ * @ecc_algorithm:            The human-readable name of the ECC algorithm
+ *                            (e.g., "Reed-Solomon" or "BCH").
+ * @ecc_strength:             A number that describes the strength of the ECC
+ *                            algorithm.
+ * @page_size_in_bytes:       The size, in bytes, of a physical page, including
+ *                            both data and OOB.
+ * @metadata_size_in_bytes:   The size, in bytes, of the metadata.
+ * @ecc_chunk_size_in_bytes:  The size, in bytes, of a single ECC chunk. Note
+ *                            the first chunk in the page includes both data and
+ *                            metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count:          The number of ECC chunks in the page,
+ * @payload_size_in_bytes:    The size, in bytes, of the payload buffer.
+ * @auxiliary_size_in_bytes:  The size, in bytes, of the auxiliary buffer.
+ * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
+ *                            the ECC status appears.
+ * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ */
+
+struct nfc_geometry {
+	char          *ecc_algorithm;
+	unsigned int  ecc_strength;
+	unsigned int  page_size_in_bytes;
+	unsigned int  metadata_size_in_bytes;
+	unsigned int  ecc_chunk_size_in_bytes;
+	unsigned int  ecc_chunk_count;
+	unsigned int  payload_size_in_bytes;
+	unsigned int  auxiliary_size_in_bytes;
+	unsigned int  auxiliary_status_offset;
+	unsigned int  block_mark_byte_offset;
+	unsigned int  block_mark_bit_offset;
+};
+
+/**
+ * struct boot_rom_geometry - Boot ROM geometry description.
+ *
+ * This structure encapsulates decisions made by the Boot ROM Helper.
+ *
+ * @boot_area_count:             The number of boot areas. The first boot area
+ *                               appears at the beginning of chip 0, the next
+ *                               at the beginning of chip 1, etc.
+ * @boot_area_size_in_bytes:     The size, in bytes, of each boot area.
+ * @stride_size_in_pages:        The size of a boot block stride, in pages.
+ * @search_area_stride_exponent: The logarithm to base 2 of the size of a
+ *                               search area in boot block strides.
+ */
+
+struct boot_rom_geometry {
+	unsigned int  boot_area_count;
+	unsigned int  boot_area_size_in_bytes;
+	unsigned int  stride_size_in_pages;
+	unsigned int  search_area_stride_exponent;
+};
+
+/**
+ * struct gpmi_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev:                 A pointer to the owning struct device.
+ * @pdev:                A pointer to the owning struct platform_device.
+ * @pdata:               A pointer to the device's platform data.
+ * @resources:           Information about system resources used by this driver.
+ * @device_info:         A structure that contains detailed information about
+ *                       the NAND Flash device.
+ * @physical_geometry:   A description of the medium's physical geometry.
+ * @nfc:                 A pointer to a structure that represents the underlying
+ *                       NFC hardware.
+ * @nfc_geometry:        A description of the medium geometry as viewed by the
+ *                       NFC.
+ * @rom:                 A pointer to a structure that represents the underlying
+ *                       Boot ROM.
+ * @rom_geometry:        A description of the medium geometry as viewed by the
+ *                       Boot ROM.
+ * @mil:                 A collection of information used by the MTD Interface
+ *                       Layer.
+ */
+
+struct gpmi_nfc_data {
+
+	/* System Interface */
+	struct device                  *dev;
+	struct platform_device         *pdev;
+	struct gpmi_nfc_platform_data  *pdata;
+
+	/* Resources */
+	struct resources               resources;
+
+	/* Flash Hardware */
+	struct nand_device_info        device_info;
+	struct physical_geometry       physical_geometry;
+
+	/* NFC HAL */
+	struct nfc_hal                 *nfc;
+	struct nfc_geometry            nfc_geometry;
+
+	/* Boot ROM Helper */
+	struct boot_rom_helper         *rom;
+	struct boot_rom_geometry       rom_geometry;
+
+	/* MTD Interface Layer */
+	struct mil                     mil;
+
+};
+
+/**
+ * struct gpmi_nfc_timing - GPMI NFC timing parameters.
+ *
+ * This structure contains the fundamental timing attributes for the NAND Flash
+ * bus and the GPMI NFC hardware.
+ *
+ * @data_setup_in_ns:         The data setup time, in nanoseconds. Usually the
+ *                            maximum of tDS and tWP. A negative value
+ *                            indicates this characteristic isn't known.
+ * @data_hold_in_ns:          The data hold time, in nanoseconds. Usually the
+ *                            maximum of tDH, tWH and tREH. A negative value
+ *                            indicates this characteristic isn't known.
+ * @address_setup_in_ns:      The address setup time, in nanoseconds. Usually
+ *                            the maximum of tCLS, tCS and tALS. A negative
+ *                            value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns:  A GPMI-specific timing parameter. A negative value
+ *                            indicates this characteristic isn't known.
+ * @tREA_in_ns:               tREA, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ * @tRLOH_in_ns:              tRLOH, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ * @tRHOH_in_ns:              tRHOH, in nanoseconds, from the data sheet. A
+ *                            negative value indicates this characteristic isn't
+ *                            known.
+ */
+
+struct gpmi_nfc_timing {
+	int8_t  data_setup_in_ns;
+	int8_t  data_hold_in_ns;
+	int8_t  address_setup_in_ns;
+	int8_t  gpmi_sample_delay_in_ns;
+	int8_t  tREA_in_ns;
+	int8_t  tRLOH_in_ns;
+	int8_t  tRHOH_in_ns;
+};
+
+/**
+ * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters.
+ *
+ * This structure contains timing information expressed in a form directly
+ * usable by the GPMI NFC hardware.
+ *
+ * @data_setup_in_cycles:      The data setup time, in cycles.
+ * @data_hold_in_cycles:       The data hold time, in cycles.
+ * @address_setup_in_cycles:   The address setup time, in cycles.
+ * @use_half_periods:          Indicates the clock is running slowly, so the
+ *                             NFC DLL should use half-periods.
+ * @sample_delay_factor:       The sample delay factor.
+ */
+
+struct gpmi_nfc_hardware_timing {
+	uint8_t  data_setup_in_cycles;
+	uint8_t  data_hold_in_cycles;
+	uint8_t  address_setup_in_cycles;
+	bool     use_half_periods;
+	uint8_t  sample_delay_factor;
+};
+
+/**
+ * struct nfc_hal - GPMI NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @version:                     The NFC hardware version.
+ * @description:                 A pointer to a human-readable description of
+ *                               the NFC hardware.
+ * @max_chip_count:              The maximum number of chips the NFC can
+ *                               possibly support (this value is a constant for
+ *                               each NFC version). This may *not* be the actual
+ *                               number of chips connected.
+ * @max_data_setup_cycles:       The maximum number of data setup cycles that
+ *                               can be expressed in the hardware.
+ * @internal_data_setup_in_ns:   The time, in ns, that the NFC hardware requires
+ *                               for data read internal setup. In the Reference
+ *                               Manual, see the chapter "High-Speed NAND
+ *                               Timing" for more details.
+ * @max_sample_delay_factor:     The maximum sample delay factor that can be
+ *                               expressed in the hardware.
+ * @max_dll_clock_period_in_ns:  The maximum period of the GPMI clock that the
+ *                               sample delay DLL hardware can possibly work
+ *                               with (the DLL is unusable with longer periods).
+ *                               If the full-cycle period is greater than HALF
+ *                               this value, the DLL must be configured to use
+ *                               half-periods.
+ * @max_dll_delay_in_ns:         The maximum amount of delay, in ns, that the
+ *                               DLL can implement.
+ * @dma_descriptors:             A pool of DMA descriptors.
+ * @isr_dma_channel:             The DMA channel with which the NFC HAL is
+ *                               working. We record this here so the ISR knows
+ *                               which DMA channel to acknowledge.
+ * @dma_done:                    The completion structure used for DMA
+ *                               interrupts.
+ * @bch_done:                    The completion structure used for BCH
+ *                               interrupts.
+ * @timing:                      The current timing configuration.
+ * @clock_frequency_in_hz:       The clock frequency, in Hz, during the current
+ *                               I/O transaction. If no I/O transaction is in
+ *                               progress, this is the clock frequency during
+ *                               the most recent I/O transaction.
+ * @hardware_timing:             The hardware timing configuration in effect
+ *                               during the current I/O transaction. If no I/O
+ *                               transaction is in progress, this is the
+ *                               hardware timing configuration during the most
+ *                               recent I/O transaction.
+ * @init:                        Initializes the NFC hardware and data
+ *                               structures. This function will be called after
+ *                               everything has been set up for communication
+ *                               with the NFC itself, but before the platform
+ *                               has set up off-chip communication. Thus, this
+ *                               function must not attempt to communicate with
+ *                               the NAND Flash hardware.
+ * @set_geometry:                Configures the NFC hardware and data structures
+ *                               to match the physical NAND Flash geometry.
+ * @set_geometry:                Configures the NFC hardware and data structures
+ *                               to match the physical NAND Flash geometry.
+ * @set_timing:                  Configures the NFC hardware and data structures
+ *                               to match the given NAND Flash bus timing.
+ * @get_timing:                  Returns the the clock frequency, in Hz, and
+ *                               the hardware timing configuration during the
+ *                               current I/O transaction. If no I/O transaction
+ *                               is in progress, this is the timing state during
+ *                               the most recent I/O transaction.
+ * @exit:                        Shuts down the NFC hardware and data
+ *                               structures. This function will be called after
+ *                               the platform has shut down off-chip
+ *                               communication but while communication with the
+ *                               NFC itself still works.
+ * @clear_bch:                   Clears a BCH interrupt (intended to be called
+ *                               by a more general interrupt handler to do
+ *                               device-specific clearing).
+ * @is_ready:                    Returns true if the given chip is ready.
+ * @begin:                       Begins an interaction with the NFC. This
+ *                               function must be called before *any* of the
+ *                               following functions so the NFC can prepare
+ *                               itself.
+ * @end:                         Ends interaction with the NFC. This function
+ *                               should be called to give the NFC a chance to,
+ *                               among other things, enter a lower-power state.
+ * @send_command:                Sends the given buffer of command bytes.
+ * @send_data:                   Sends the given buffer of data bytes.
+ * @read_data:                   Reads data bytes into the given buffer.
+ * @send_page:                   Sends the given given data and OOB bytes,
+ *                               using the ECC engine.
+ * @read_page:                   Reads a page through the ECC engine and
+ *                               delivers the data and OOB bytes to the given
+ *                               buffers.
+ */
+
+#define  NFC_DMA_DESCRIPTOR_COUNT  (4)
+
+struct nfc_hal {
+
+	/* Hardware attributes. */
+
+	const unsigned int      version;
+	const char              *description;
+	const unsigned int      max_chip_count;
+	const unsigned int      max_data_setup_cycles;
+	const unsigned int      internal_data_setup_in_ns;
+	const unsigned int      max_sample_delay_factor;
+	const unsigned int      max_dll_clock_period_in_ns;
+	const unsigned int      max_dll_delay_in_ns;
+
+	/* Working variables. */
+
+	struct mxs_dma_desc     *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT];
+	int                     isr_dma_channel;
+	struct completion       dma_done;
+	struct completion       bch_done;
+	struct gpmi_nfc_timing  timing;
+	unsigned long           clock_frequency_in_hz;
+
+	/* Configuration functions. */
+
+	int   (*init)        (struct gpmi_nfc_data *);
+	int   (*set_geometry)(struct gpmi_nfc_data *);
+	int   (*set_timing)  (struct gpmi_nfc_data *,
+					const struct gpmi_nfc_timing *);
+	void  (*get_timing)  (struct gpmi_nfc_data *,
+					unsigned long *clock_frequency_in_hz,
+					struct gpmi_nfc_hardware_timing *);
+	void  (*exit)        (struct gpmi_nfc_data *);
+
+	/* Call these functions to begin and end I/O. */
+
+	void  (*begin)       (struct gpmi_nfc_data *);
+	void  (*end)         (struct gpmi_nfc_data *);
+
+	/* Call these I/O functions only between begin() and end(). */
+
+	void  (*clear_bch)   (struct gpmi_nfc_data *);
+	int   (*is_ready)    (struct gpmi_nfc_data *, unsigned chip);
+	int   (*send_command)(struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*send_data)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*read_data)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t buffer, unsigned length);
+	int   (*send_page)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary);
+	int   (*read_page)   (struct gpmi_nfc_data *, unsigned chip,
+				dma_addr_t payload, dma_addr_t auxiliary);
+};
+
+/**
+ * struct boot_rom_helper - Boot ROM Helper
+ *
+ * This structure embodies the interface to an object that assists the driver
+ * in making decisions that relate to the Boot ROM.
+ *
+ * @version:                    The Boot ROM version.
+ * @description:                A pointer to a human-readable description of the
+ *                              Boot ROM.
+ * @swap_block_mark:            Indicates that the Boot ROM will swap the block
+ *                              mark with the first byte of the OOB.
+ * @set_geometry:               Configures the Boot ROM geometry.
+ * @check_transcription_stamp:  Checks for a transcription stamp. This pointer
+ *                              is ignored if swap_block_mark is set.
+ * @write_transcription_stamp:  Writes a transcription stamp. This pointer
+ *                              is ignored if swap_block_mark is set.
+ */
+
+struct boot_rom_helper {
+	const unsigned int  version;
+	const char          *description;
+	const int           swap_block_mark;
+	int  (*set_geometry)             (struct gpmi_nfc_data *);
+	int  (*check_transcription_stamp)(struct gpmi_nfc_data *);
+	int  (*write_transcription_stamp)(struct gpmi_nfc_data *);
+};
+
+/*
+ *------------------------------------------------------------------------------
+ * External Symbols
+ *------------------------------------------------------------------------------
+ */
+
+/* Event Reporting */
+
+#if defined(EVENT_REPORTING)
+	extern void gpmi_nfc_start_event_trace(char *description);
+	extern void gpmi_nfc_add_event(char *description, int delta);
+	extern void gpmi_nfc_stop_event_trace(char *description);
+	extern void gpmi_nfc_dump_event_trace(void);
+#else
+	#define gpmi_nfc_start_event_trace(description)  do {} while (0)
+	#define gpmi_nfc_add_event(description, delta)   do {} while (0)
+	#define gpmi_nfc_stop_event_trace(description)   do {} while (0)
+	#define gpmi_nfc_dump_event_trace()              do {} while (0)
+#endif
+
+/* NFC HAL Common Services */
+
+extern irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie);
+extern irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie);
+extern int gpmi_nfc_dma_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int  dma_channel);
+extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+					struct gpmi_nfc_hardware_timing *hw);
+
+/* NFC HAL Structures */
+
+extern struct nfc_hal  gpmi_nfc_hal_v0;
+extern struct nfc_hal  gpmi_nfc_hal_v1;
+extern struct nfc_hal  gpmi_nfc_hal_v2;
+
+/* Boot ROM Helper Common Services */
+
+extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this);
+
+/* Boot ROM Helper Structures */
+
+extern struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v0;
+extern struct boot_rom_helper  gpmi_nfc_boot_rom_helper_v1;
+
+/* MTD Interface Layer */
+
+extern int  gpmi_nfc_mil_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this);
+
+#endif
diff --git a/drivers/mtd/nand/imx_nfc.c b/drivers/mtd/nand/imx_nfc.c
new file mode 100644
index 000000000000..65f72b4e468a
--- /dev/null
+++ b/drivers/mtd/nand/imx_nfc.c
@@ -0,0 +1,8286 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mtd/partitions.h>
+#include <linux/io.h>
+
+#define DRIVER_VERSION "1.0"
+
+/* Define this macro to enable event reporting. */
+
+#define EVENT_REPORTING
+
+/*
+ * For detailed information that will be helpful in understanding this driver,
+ * see:
+ *
+ *     Documentation/imx_nfc.txt
+ */
+
+/*
+ * Macros that describe NFC hardware have names of the form:
+ *
+ *     NFC_*
+ *
+ * Macros that apply only to specific versions of the NFC have names of the
+ * following form:
+ *
+ *     NFC_<M>_<N>_*
+ *
+ * where:
+ *
+ *     <M> is the major version of the NFC hardware.
+ *     <N> is the minor version of the NFC hardware.
+ *
+ * The minor version can be 'X', which means that the macro applies to *all*
+ * NFCs of the same major version.
+ *
+ * For NFC versions with only one set of registers, macros that give offsets
+ * against the base address have names of the form:
+ *
+ *     *<RegisterName>_REG_OFF
+ *
+ * Macros that give the position of a field's LSB within a given register have
+ * names of the form:
+ *
+ *     *<RegisterName>_<FieldName>_POS
+ *
+ * Macros that mask a field within a given register have names of the form:
+ *
+ *     *<RegisterName>_<FieldName>_MSK
+ */
+
+/*
+ * Macro definitions for ALL NFC versions.
+ */
+
+#define NFC_MAIN_BUF_SIZE  (512)
+
+/*
+ * Macro definitions for version 1.0 NFCs.
+ */
+
+#define NFC_1_0_BUF_SIZE_REG_OFF             (0x00)
+#define NFC_1_0_BUF_ADDR_REG_OFF             (0x04)
+#define NFC_1_0_FLASH_ADDR_REG_OFF           (0x06)
+#define NFC_1_0_FLASH_CMD_REG_OFF            (0x08)
+#define NFC_1_0_CONFIG_REG_OFF               (0x0A)
+#define NFC_1_0_ECC_STATUS_RESULT_REG_OFF    (0x0C)
+#define NFC_1_0_RSLTMAIN_AREA_REG_OFF        (0x0E)
+#define NFC_1_0_RSLTSPARE_AREA_REG_OFF       (0x10)
+#define NFC_1_0_WRPROT_REG_OFF               (0x12)
+#define NFC_1_0_UNLOCKSTART_BLKADDR_REG_OFF  (0x14)
+#define NFC_1_0_UNLOCKEND_BLKADDR_REG_OFF    (0x16)
+#define NFC_1_0_NF_WRPRST_REG_OFF            (0x18)
+
+#define NFC_1_0_CONFIG1_REG_OFF              (0x1A)
+#define NFC_1_0_CONFIG1_NF_CE_POS            (7)
+#define NFC_1_0_CONFIG1_NF_CE_MSK            (0x1 << 7)
+
+#define NFC_1_0_CONFIG2_REG_OFF              (0x1C)
+
+/*
+* Macro definitions for version 2.X NFCs.
+*/
+
+#define NFC_2_X_FLASH_ADDR_REG_OFF   (0x06)
+#define NFC_2_X_FLASH_CMD_REG_OFF    (0x08)
+#define NFC_2_X_CONFIG_REG_OFF       (0x0A)
+
+#define NFC_2_X_WR_PROT_REG_OFF      (0x12)
+
+#define NFC_2_X_NF_WR_PR_ST_REG_OFF  (0x18)
+
+#define NFC_2_X_CONFIG2_REG_OFF      (0x1C)
+#define NFC_2_X_CONFIG2_FCMD_POS     (0)
+#define NFC_2_X_CONFIG2_FCMD_MSK     (0x1 << 0)
+#define NFC_2_X_CONFIG2_FADD_POS     (1)
+#define NFC_2_X_CONFIG2_FADD_MSK     (0x1 << 1)
+#define NFC_2_X_CONFIG2_FDI_POS      (2)
+#define NFC_2_X_CONFIG2_FDI_MSK      (0x1 << 2)
+#define NFC_2_X_CONFIG2_FDO_POS      (3)
+#define NFC_2_X_CONFIG2_FDO_MSK      (0x7 << 3)
+#define NFC_2_X_CONFIG2_INT_POS      (15)
+#define NFC_2_X_CONFIG2_INT_MSK      (0x1 << 15)
+
+/*
+* Macro definitions for version 2.0 NFCs.
+*/
+
+#define NFC_2_0_BUF_ADDR_REG_OFF       (0x04)
+#define NFC_2_0_BUF_ADDR_RBA_POS       (0)
+#define NFC_2_0_BUF_ADDR_RBA_MSK       (0xf << 0)
+
+#define NFC_2_0_ECC_STATUS_REG_OFF     (0x0C)
+#define NFC_2_0_ECC_STATUS_NOSER1_POS  (0)
+#define NFC_2_0_ECC_STATUS_NOSER1_MSK  (0xF << 0)
+#define NFC_2_0_ECC_STATUS_NOSER2_POS  (4)
+#define NFC_2_0_ECC_STATUS_NOSER2_MSK  (0xF << 4)
+#define NFC_2_0_ECC_STATUS_NOSER3_POS  (8)
+#define NFC_2_0_ECC_STATUS_NOSER3_MSK  (0xF << 8)
+#define NFC_2_0_ECC_STATUS_NOSER4_POS  (12)
+#define NFC_2_0_ECC_STATUS_NOSER4_MSK  (0xF << 12)
+
+#define NFC_2_0_CONFIG1_REG_OFF        (0x1A)
+#define NFC_2_0_CONFIG1_SP_EN_POS      (2)
+#define NFC_2_0_CONFIG1_SP_EN_MSK      (0x1 << 2)
+#define NFC_2_0_CONFIG1_ECC_EN_POS     (3)
+#define NFC_2_0_CONFIG1_ECC_EN_MSK     (0x1 << 3)
+#define NFC_2_0_CONFIG1_INT_MSK_POS    (4)
+#define NFC_2_0_CONFIG1_INT_MSK_MSK    (0x1 << 4)
+#define NFC_2_0_CONFIG1_NF_BIG_POS     (5)
+#define NFC_2_0_CONFIG1_NF_BIG_MSK     (0x1 << 5)
+#define NFC_2_0_CONFIG1_NFC_RST_POS    (6)
+#define NFC_2_0_CONFIG1_NFC_RST_MSK    (0x1 << 6)
+#define NFC_2_0_CONFIG1_NF_CE_POS      (7)
+#define NFC_2_0_CONFIG1_NF_CE_MSK      (0x1 << 7)
+#define NFC_2_0_CONFIG1_ONE_CYLE_POS   (8)
+#define NFC_2_0_CONFIG1_ONE_CYLE_MSK   (0x1 << 8)
+#define NFC_2_0_CONFIG1_MLC_POS        (9)
+#define NFC_2_0_CONFIG1_MLC_MSK        (0x1 << 9)
+
+#define NFC_2_0_UNLOCK_START_REG_OFF   (0x14)
+#define NFC_2_0_UNLOCK_END_REG_OFF     (0x16)
+
+/*
+* Macro definitions for version 2.1 NFCs.
+*/
+
+#define NFC_2_1_BUF_ADDR_REG_OFF        (0x04)
+#define NFC_2_1_BUF_ADDR_RBA_POS        (0)
+#define NFC_2_1_BUF_ADDR_RBA_MSK        (0x7 << 0)
+#define NFC_2_1_BUF_ADDR_CS_POS         (4)
+#define NFC_2_1_BUF_ADDR_CS_MSK         (0x3 << 4)
+
+#define NFC_2_1_ECC_STATUS_REG_OFF      (0x0C)
+#define NFC_2_1_ECC_STATUS_NOSER1_POS   (0)
+#define NFC_2_1_ECC_STATUS_NOSER1_MSK   (0xF << 0)
+#define NFC_2_1_ECC_STATUS_NOSER2_POS   (4)
+#define NFC_2_1_ECC_STATUS_NOSER2_MSK   (0xF << 4)
+#define NFC_2_1_ECC_STATUS_NOSER3_POS   (8)
+#define NFC_2_1_ECC_STATUS_NOSER3_MSK   (0xF << 8)
+#define NFC_2_1_ECC_STATUS_NOSER4_POS   (12)
+#define NFC_2_1_ECC_STATUS_NOSER4_MSK   (0xF << 12)
+
+#define NFC_2_1_CONFIG1_REG_OFF         (0x1A)
+#define NFC_2_1_CONFIG1_ECC_MODE_POS    (0)
+#define NFC_2_1_CONFIG1_ECC_MODE_MSK    (0x1 << 0)
+#define NFC_2_1_CONFIG1_DMA_MODE_POS    (1)
+#define NFC_2_1_CONFIG1_DMA_MODE_MSK    (0x1 << 1)
+#define NFC_2_1_CONFIG1_SP_EN_POS       (2)
+#define NFC_2_1_CONFIG1_SP_EN_MSK       (0x1 << 2)
+#define NFC_2_1_CONFIG1_ECC_EN_POS      (3)
+#define NFC_2_1_CONFIG1_ECC_EN_MSK      (0x1 << 3)
+#define NFC_2_1_CONFIG1_INT_MSK_POS     (4)
+#define NFC_2_1_CONFIG1_INT_MSK_MSK     (0x1 << 4)
+#define NFC_2_1_CONFIG1_NF_BIG_POS      (5)
+#define NFC_2_1_CONFIG1_NF_BIG_MSK      (0x1 << 5)
+#define NFC_2_1_CONFIG1_NFC_RST_POS     (6)
+#define NFC_2_1_CONFIG1_NFC_RST_MSK     (0x1 << 6)
+#define NFC_2_1_CONFIG1_NF_CE_POS       (7)
+#define NFC_2_1_CONFIG1_NF_CE_MSK       (0x1 << 7)
+#define NFC_2_1_CONFIG1_SYM_POS         (8)
+#define NFC_2_1_CONFIG1_SYM_MSK         (0x1 << 8)
+#define NFC_2_1_CONFIG1_PPB_POS         (9)
+#define NFC_2_1_CONFIG1_PPB_MSK         (0x3 << 9)
+#define NFC_2_1_CONFIG1_FP_INT_POS      (11)
+#define NFC_2_1_CONFIG1_FP_INT_MSK      (0x1 << 11)
+
+#define NFC_2_1_UNLOCK_START_0_REG_OFF  (0x20)
+#define NFC_2_1_UNLOCK_END_0_REG_OFF    (0x22)
+#define NFC_2_1_UNLOCK_START_1_REG_OFF  (0x24)
+#define NFC_2_1_UNLOCK_END_1_REG_OFF    (0x26)
+#define NFC_2_1_UNLOCK_START_2_REG_OFF  (0x28)
+#define NFC_2_1_UNLOCK_END_2_REG_OFF    (0x2A)
+#define NFC_2_1_UNLOCK_START_3_REG_OFF  (0x2C)
+#define NFC_2_1_UNLOCK_END_3_REG_OFF    (0x2E)
+
+/*
+* Macro definitions for version 3.X NFCs.
+*/
+
+/*
+* Macro definitions for version 3.1 NFCs.
+*/
+
+#define NFC_3_1_FLASH_ADDR_CMD_REG_OFF          (0x00)
+#define NFC_3_1_CONFIG1_REG_OFF                 (0x04)
+#define NFC_3_1_ECC_STATUS_RESULT_REG_OFF       (0x08)
+#define NFC_3_1_LAUNCH_NFC_REG_OFF              (0x0C)
+
+#define NFC_3_1_WRPROT_REG_OFF                  (0x00)
+#define NFC_3_1_WRPROT_UNLOCK_BLK_ADD0_REG_OFF  (0x04)
+#define NFC_3_1_CONFIG2_REG_OFF                 (0x14)
+#define NFC_3_1_IPC_REG_OFF                     (0x18)
+
+/*
+* Macro definitions for version 3.2 NFCs.
+*/
+
+#define NFC_3_2_CMD_REG_OFF                (0x00)
+
+#define NFC_3_2_ADD0_REG_OFF               (0x04)
+#define NFC_3_2_ADD1_REG_OFF               (0x08)
+#define NFC_3_2_ADD2_REG_OFF               (0x0C)
+#define NFC_3_2_ADD3_REG_OFF               (0x10)
+#define NFC_3_2_ADD4_REG_OFF               (0x14)
+#define NFC_3_2_ADD5_REG_OFF               (0x18)
+#define NFC_3_2_ADD6_REG_OFF               (0x1C)
+#define NFC_3_2_ADD7_REG_OFF               (0x20)
+#define NFC_3_2_ADD8_REG_OFF               (0x24)
+#define NFC_3_2_ADD9_REG_OFF               (0x28)
+#define NFC_3_2_ADD10_REG_OFF              (0x2C)
+#define NFC_3_2_ADD11_REG_OFF              (0x30)
+
+#define NFC_3_2_CONFIG1_REG_OFF            (0x34)
+#define NFC_3_2_CONFIG1_SP_EN_POS          (0)
+#define NFC_3_2_CONFIG1_SP_EN_MSK          (0x1 << 0)
+#define NFC_3_2_CONFIG1_NF_CE_POS          (1)
+#define NFC_3_2_CONFIG1_NF_CE_MSK          (0x1 << 1)
+#define NFC_3_2_CONFIG1_RST_POS            (2)
+#define NFC_3_2_CONFIG1_RST_MSK            (0x1 << 2)
+#define NFC_3_2_CONFIG1_RBA_POS            (4)
+#define NFC_3_2_CONFIG1_RBA_MSK            (0x7 << 4)
+#define NFC_3_2_CONFIG1_ITER_POS           (8)
+#define NFC_3_2_CONFIG1_ITER_MSK           (0xf << 8)
+#define NFC_3_2_CONFIG1_CS_POS             (12)
+#define NFC_3_2_CONFIG1_CS_MSK             (0x7 << 12)
+#define NFC_3_2_CONFIG1_STATUS_POS         (16)
+#define NFC_3_2_CONFIG1_STATUS_MSK         (0xFFFF<<16)
+
+#define NFC_3_2_ECC_STATUS_REG_OFF         (0x38)
+#define NFC_3_2_ECC_STATUS_NOBER1_POS      (0)
+#define NFC_3_2_ECC_STATUS_NOBER1_MSK      (0xF << 0)
+#define NFC_3_2_ECC_STATUS_NOBER2_POS      (4)
+#define NFC_3_2_ECC_STATUS_NOBER2_MSK      (0xF << 4)
+#define NFC_3_2_ECC_STATUS_NOBER3_POS      (8)
+#define NFC_3_2_ECC_STATUS_NOBER3_MSK      (0xF << 8)
+#define NFC_3_2_ECC_STATUS_NOBER4_POS      (12)
+#define NFC_3_2_ECC_STATUS_NOBER4_MSK      (0xF << 12)
+#define NFC_3_2_ECC_STATUS_NOBER5_POS      (16)
+#define NFC_3_2_ECC_STATUS_NOBER5_MSK      (0xF << 16)
+#define NFC_3_2_ECC_STATUS_NOBER6_POS      (20)
+#define NFC_3_2_ECC_STATUS_NOBER6_MSK      (0xF << 20)
+#define NFC_3_2_ECC_STATUS_NOBER7_POS      (24)
+#define NFC_3_2_ECC_STATUS_NOBER7_MSK      (0xF << 24)
+#define NFC_3_2_ECC_STATUS_NOBER8_POS      (28)
+#define NFC_3_2_ECC_STATUS_NOBER8_MSK      (0xF << 28)
+
+
+#define NFC_3_2_STATUS_SUM_REG_OFF         (0x3C)
+#define NFC_3_2_STATUS_SUM_NAND_SUM_POS    (0x0)
+#define NFC_3_2_STATUS_SUM_NAND_SUM_MSK    (0xFF << 0)
+#define NFC_3_2_STATUS_SUM_ECC_SUM_POS     (8)
+#define NFC_3_2_STATUS_SUM_ECC_SUM_MSK     (0xFF << 8)
+
+#define NFC_3_2_LAUNCH_REG_OFF             (0x40)
+#define NFC_3_2_LAUNCH_FCMD_POS            (0)
+#define NFC_3_2_LAUNCH_FCMD_MSK            (0x1 << 0)
+#define NFC_3_2_LAUNCH_FADD_POS            (1)
+#define NFC_3_2_LAUNCH_FADD_MSK            (0x1 << 1)
+#define NFC_3_2_LAUNCH_FDI_POS             (2)
+#define NFC_3_2_LAUNCH_FDI_MSK             (0x1 << 2)
+#define NFC_3_2_LAUNCH_FDO_POS             (3)
+#define NFC_3_2_LAUNCH_FDO_MSK             (0x7 << 3)
+#define NFC_3_2_LAUNCH_AUTO_PROG_POS       (6)
+#define NFC_3_2_LAUNCH_AUTO_PROG_MSK       (0x1 << 6)
+#define NFC_3_2_LAUNCH_AUTO_READ_POS       (7)
+#define NFC_3_2_LAUNCH_AUTO_READ_MSK       (0x1 << 7)
+#define NFC_3_2_LAUNCH_AUTO_ERASE_POS      (9)
+#define NFC_3_2_LAUNCH_AUTO_ERASE_MSK      (0x1 << 9)
+#define NFC_3_2_LAUNCH_COPY_BACK0_POS      (10)
+#define NFC_3_2_LAUNCH_COPY_BACK0_MSK      (0x1 << 10)
+#define NFC_3_2_LAUNCH_COPY_BACK1_POS      (11)
+#define NFC_3_2_LAUNCH_COPY_BACK1_MSK      (0x1 << 11)
+#define NFC_3_2_LAUNCH_AUTO_STATUS_POS     (12)
+#define NFC_3_2_LAUNCH_AUTO_STATUS_MSK     (0x1 << 12)
+
+#define NFC_3_2_WRPROT_REG_OFF             (0x00)
+#define NFC_3_2_WRPROT_WPC_POS             (0)
+#define NFC_3_2_WRPROT_WPC_MSK             (0x7 << 0)
+#define NFC_3_2_WRPROT_CS2L_POS            (3)
+#define NFC_3_2_WRPROT_CS2L_MSK            (0x7 << 3)
+#define NFC_3_2_WRPROT_BLS_POS             (6)
+#define NFC_3_2_WRPROT_BLS_MSK             (0x3 << 6)
+#define NFC_3_2_WRPROT_LTS0_POS            (8)
+#define NFC_3_2_WRPROT_LTS0_MSK            (0x1 << 8)
+#define NFC_3_2_WRPROT_LS0_POS             (9)
+#define NFC_3_2_WRPROT_LS0_MSK             (0x1 << 9)
+#define NFC_3_2_WRPROT_US0_POS             (10)
+#define NFC_3_2_WRPROT_US0_MSK             (0x1 << 10)
+#define NFC_3_2_WRPROT_LTS1_POS            (11)
+#define NFC_3_2_WRPROT_LTS1_MSK            (0x1 << 11)
+#define NFC_3_2_WRPROT_LS1_POS             (12)
+#define NFC_3_2_WRPROT_LS1_MSK             (0x1 << 12)
+#define NFC_3_2_WRPROT_US1_POS             (13)
+#define NFC_3_2_WRPROT_US1_MSK             (0x1 << 13)
+#define NFC_3_2_WRPROT_LTS2_POS            (14)
+#define NFC_3_2_WRPROT_LTS2_MSK            (0x1 << 14)
+#define NFC_3_2_WRPROT_LS2_POS             (15)
+#define NFC_3_2_WRPROT_LS2_MSK             (0x1 << 15)
+#define NFC_3_2_WRPROT_US2_POS             (16)
+#define NFC_3_2_WRPROT_US2_MSK             (0x1 << 16)
+#define NFC_3_2_WRPROT_LTS3_POS            (17)
+#define NFC_3_2_WRPROT_LTS3_MSK            (0x1 << 17)
+#define NFC_3_2_WRPROT_LS3_POS             (18)
+#define NFC_3_2_WRPROT_LS3_MSK             (0x1 << 18)
+#define NFC_3_2_WRPROT_US3_POS             (19)
+#define NFC_3_2_WRPROT_US3_MSK             (0x1 << 19)
+#define NFC_3_2_WRPROT_LTS4_POS            (20)
+#define NFC_3_2_WRPROT_LTS4_MSK            (0x1 << 20)
+#define NFC_3_2_WRPROT_LS4_POS             (21)
+#define NFC_3_2_WRPROT_LS4_MSK             (0x1 << 21)
+#define NFC_3_2_WRPROT_US4_POS             (22)
+#define NFC_3_2_WRPROT_US4_MSK             (0x1 << 22)
+#define NFC_3_2_WRPROT_LTS5_POS            (23)
+#define NFC_3_2_WRPROT_LTS5_MSK            (0x1 << 23)
+#define NFC_3_2_WRPROT_LS5_POS             (24)
+#define NFC_3_2_WRPROT_LS5_MSK             (0x1 << 24)
+#define NFC_3_2_WRPROT_US5_POS             (25)
+#define NFC_3_2_WRPROT_US5_MSK             (0x1 << 25)
+#define NFC_3_2_WRPROT_LTS6_POS            (26)
+#define NFC_3_2_WRPROT_LTS6_MSK            (0x1 << 26)
+#define NFC_3_2_WRPROT_LS6_POS             (27)
+#define NFC_3_2_WRPROT_LS6_MSK             (0x1 << 27)
+#define NFC_3_2_WRPROT_US6_POS             (28)
+#define NFC_3_2_WRPROT_US6_MSK             (0x1 << 28)
+#define NFC_3_2_WRPROT_LTS7_POS            (29)
+#define NFC_3_2_WRPROT_LTS7_MSK            (0x1 << 29)
+#define NFC_3_2_WRPROT_LS7_POS             (30)
+#define NFC_3_2_WRPROT_LS7_MSK             (0x1 << 30)
+#define NFC_3_2_WRPROT_US7_POS             (31)
+#define NFC_3_2_WRPROT_US7_MSK             (0x1 << 31)
+
+#define NFC_3_2_UNLOCK_BLK_ADD0_REG_OFF    (0x04)
+#define NFC_3_2_UNLOCK_BLK_ADD0_USBA0_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD0_USBA0_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD0_UEBA0_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD0_UEBA0_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD1_REG_OFF    (0x08)
+#define NFC_3_2_UNLOCK_BLK_ADD1_USBA1_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD1_USBA1_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD1_UEBA1_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD1_UEBA1_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD2_REG_OFF    (0x0C)
+#define NFC_3_2_UNLOCK_BLK_ADD2_USBA2_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD2_USBA2_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD2_UEBA2_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD2_UEBA2_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD3_REG_OFF    (0x10)
+#define NFC_3_2_UNLOCK_BLK_ADD3_USBA3_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD3_USBA3_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD3_UEBA3_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD3_UEBA3_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD4_REG_OFF    (0x14)
+#define NFC_3_2_UNLOCK_BLK_ADD4_USBA4_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD4_USBA4_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD4_UEBA4_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD4_UEBA4_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD5_REG_OFF    (0x18)
+#define NFC_3_2_UNLOCK_BLK_ADD5_USBA5_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD5_USBA5_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD5_UEBA5_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD5_UEBA5_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD6_REG_OFF    (0x1C)
+#define NFC_3_2_UNLOCK_BLK_ADD6_USBA6_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD6_USBA6_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD6_UEBA6_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD6_UEBA6_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_UNLOCK_BLK_ADD7_REG_OFF    (0x20)
+#define NFC_3_2_UNLOCK_BLK_ADD7_USBA7_POS  (0)
+#define NFC_3_2_UNLOCK_BLK_ADD7_USBA7_MSK  (0xFFFF << 0)
+#define NFC_3_2_UNLOCK_BLK_ADD7_UEBA7_POS  (16)
+#define NFC_3_2_UNLOCK_BLK_ADD7_UEBA7_MSK  (0xFFFF<<16)
+
+#define NFC_3_2_CONFIG2_REG_OFF            (0x24)
+#define NFC_3_2_CONFIG2_PS_POS             (0)
+#define NFC_3_2_CONFIG2_PS_MSK             (0x3 << 0)
+#define NFC_3_2_CONFIG2_SYM_POS            (2)
+#define NFC_3_2_CONFIG2_SYM_MSK            (0x1 << 2)
+#define NFC_3_2_CONFIG2_ECC_EN_POS         (3)
+#define NFC_3_2_CONFIG2_ECC_EN_MSK         (0x1 << 3)
+#define NFC_3_2_CONFIG2_CMD_PHASES_POS     (4)
+#define NFC_3_2_CONFIG2_CMD_PHASES_MSK     (0x1 << 4)
+#define NFC_3_2_CONFIG2_ADDR_PHASES0_POS   (5)
+#define NFC_3_2_CONFIG2_ADDR_PHASES0_MSK   (0x1 << 5)
+#define NFC_3_2_CONFIG2_ECC_MODE_POS       (6)
+#define NFC_3_2_CONFIG2_ECC_MODE_MSK       (0x1 << 6)
+#define NFC_3_2_CONFIG2_PPB_POS            (7)
+#define NFC_3_2_CONFIG2_PPB_MSK            (0x3 << 7)
+#define NFC_3_2_CONFIG2_EDC_POS            (9)
+#define NFC_3_2_CONFIG2_EDC_MSK            (0x7 << 9)
+#define NFC_3_2_CONFIG2_ADDR_PHASES1_POS   (12)
+#define NFC_3_2_CONFIG2_ADDR_PHASES1_MSK   (0x3 << 12)
+#define NFC_3_2_CONFIG2_AUTO_DONE_MSK_POS  (14)
+#define NFC_3_2_CONFIG2_AUTO_DONE_MSK_MSK  (0x1 << 14)
+#define NFC_3_2_CONFIG2_INT_MSK_POS        (15)
+#define NFC_3_2_CONFIG2_INT_MSK_MSK        (0x1 << 15)
+#define NFC_3_2_CONFIG2_SPAS_POS           (16)
+#define NFC_3_2_CONFIG2_SPAS_MSK           (0xFF << 16)
+#define NFC_3_2_CONFIG2_ST_CMD_POS         (24)
+#define NFC_3_2_CONFIG2_ST_CMD_MSK         (0xFF << 24)
+
+#define NFC_3_2_CONFIG3_REG_OFF            (0x28)
+#define NFC_3_2_CONFIG3_ADD_OP_POS         (0)
+#define NFC_3_2_CONFIG3_ADD_OP_MSK         (0x3 << 0)
+#define NFC_3_2_CONFIG3_TOO_POS            (2)
+#define NFC_3_2_CONFIG3_TOO_MSK            (0x1 << 2)
+#define NFC_3_2_CONFIG3_FW_POS             (3)
+#define NFC_3_2_CONFIG3_FW_MSK             (0x1 << 3)
+#define NFC_3_2_CONFIG3_SB2R_POS           (4)
+#define NFC_3_2_CONFIG3_SB2R_MSK           (0x7 << 4)
+#define NFC_3_2_CONFIG3_NF_BIG_POS         (7)
+#define NFC_3_2_CONFIG3_NF_BIG_MSK         (0x1 << 7)
+#define NFC_3_2_CONFIG3_SBB_POS            (8)
+#define NFC_3_2_CONFIG3_SBB_MSK            (0x7 << 8)
+#define NFC_3_2_CONFIG3_DMA_MODE_POS       (11)
+#define NFC_3_2_CONFIG3_DMA_MODE_MSK       (0x1 << 11)
+#define NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS (12)
+#define NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK (0x7 << 12)
+#define NFC_3_2_CONFIG3_RBB_MODE_POS       (15)
+#define NFC_3_2_CONFIG3_RBB_MODE_MSK       (0x1 << 15)
+#define NFC_3_2_CONFIG3_FMP_POS            (16)
+#define NFC_3_2_CONFIG3_FMP_MSK            (0xF << 16)
+#define NFC_3_2_CONFIG3_NO_SDMA_POS        (20)
+#define NFC_3_2_CONFIG3_NO_SDMA_MSK        (0x1 << 20)
+
+#define NFC_3_2_IPC_REG_OFF                (0x2C)
+#define NFC_3_2_IPC_CREQ_POS               (0)
+#define NFC_3_2_IPC_CREQ_MSK               (0x1 << 0)
+#define NFC_3_2_IPC_CACK_POS               (1)
+#define NFC_3_2_IPC_CACK_MSK               (0x1 << 1)
+#define NFC_3_2_IPC_DMA_STATUS_POS         (26)
+#define NFC_3_2_IPC_DMA_STATUS_MSK         (0x3 << 26)
+#define NFC_3_2_IPC_RB_B_POS               (28)
+#define NFC_3_2_IPC_RB_B_MSK               (0x1 << 28)
+#define NFC_3_2_IPC_LPS_POS                (29)
+#define NFC_3_2_IPC_LPS_MSK                (0x1 << 29)
+#define NFC_3_2_IPC_AUTO_PROG_DONE_POS     (30)
+#define NFC_3_2_IPC_AUTO_PROG_DONE_MSK     (0x1 << 30)
+#define NFC_3_2_IPC_INT_POS                (31)
+#define NFC_3_2_IPC_INT_MSK                (0x1 << 31)
+
+#define NFC_3_2_AXI_ERR_ADD_REG_OFF        (0x30)
+
+/**
+ * enum override - Choices for overrides.
+ *
+ * Some functions of this driver can be overriden at run time. This is a
+ * convenient enumerated type for all such options.
+ */
+
+enum override {
+	NEVER         = -1,
+	DRIVER_CHOICE =  0,
+	ALWAYS        =  1,
+};
+
+/**
+ * struct physical_geometry - Physical geometry description.
+ *
+ * This structure describes the physical geometry of the medium.
+ *
+ * @chip_count:      The number of chips in the medium.
+ * @chip_size:       The size, in bytes, of a single chip (excluding the
+ *                   out-of-band bytes).
+ * @block_size:      The size, in bytes, of a single block (excluding the
+ *                   out-of-band bytes).
+ * @page_data_size:  The size, in bytes, of the data area in a page (excluding
+ *                   the out-of-band bytes).
+ * @page_oob_size:   The size, in bytes, of the out-of-band area in a page.
+ */
+
+struct physical_geometry {
+	unsigned int  chip_count;
+	uint64_t      chip_size;
+	unsigned int  block_size;
+	unsigned int  page_data_size;
+	unsigned int  page_oob_size;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry, which may be
+ * different from the physical geometry (for example, we treat pages that are
+ * physically 2K+112 as if they are 2K+64).
+ *
+ * @page_data_size:  The size of the data area in a page (excluding the
+ *                   out-of-band bytes). This is almost certain to be the same
+ *                   as the physical data size.
+ * @page_oob_size:   The size of the out-of-band area in a page. This may be
+ *                   different from the physical OOB size.
+ * @ecc_algorithm:   The name of the ECC algorithm (e.g., "Reed-Solomon" or
+ *                   "BCH").
+ * @ecc_strength:    A number that describes the strength of the ECC algorithm.
+ *                   For example, various i.MX SoC's support ECC-1, ECC-4 or
+ *                   ECC-8 of the Reed-Solomon ECC algorithm.
+ * @buffer_count:    The number of main/spare buffers used with this geometry.
+ * @spare_buf_size:  The number of bytes held in each spare buffer.
+ * @spare_buf_spill: The number of extra bytes held in the last spare buffer.
+ * @mtd_layout:      The MTD layout that best matches the geometry described by
+ *                   the rest of this structure. The logical layer might not use
+ *                   this structure, especially when interleaving.
+ */
+
+struct nfc_geometry {
+	const unsigned int     page_data_size;
+	const unsigned int     page_oob_size;
+	const char             *ecc_algorithm;
+	const int              ecc_strength;
+	const unsigned int     buffer_count;
+	const unsigned int     spare_buf_size;
+	const unsigned int     spare_buf_spill;
+	struct nand_ecclayout  mtd_layout;
+};
+
+/**
+ * struct logical_geometry - Logical geometry description.
+ *
+ * This structure describes the logical geometry we expose to MTD. This geometry
+ * may be different from the physical or NFC geometries, especially when
+ * interleaving.
+ *
+ * @chip_count:      The number of chips in the medium.
+ * @chip_size:       The size, in bytes, of a single chip (excluding the
+ *                   out-of-band bytes).
+ * @usable_size:     The size, in bytes, of the medium that MTD can actually
+ *                   use. This may be less than the chip size multiplied by the
+ *                   number of chips.
+ * @block_size:      The size, in bytes, of a single block (excluding the
+ *                   out-of-band bytes).
+ * @page_data_size:  The size of the data area in a page (excluding the
+ *                   out-of-band bytes).
+ * @page_oob_size:   The size of the out-of-band area in a page.
+ */
+
+struct logical_geometry {
+	unsigned int           chip_count;
+	uint32_t               chip_size;
+	uint32_t               usable_size;
+	unsigned int           block_size;
+	unsigned int           page_data_size;
+	unsigned int           page_oob_size;
+	struct nand_ecclayout  *mtd_layout;
+};
+
+/**
+ * struct imx_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev:                 A pointer to the owning struct device.
+ * @pdev:                A pointer to the owning struct platform_device.
+ * @pdata:               A pointer to the device's platform data.
+ * @buffers:             A pointer to the NFC buffers.
+ * @primary_regs:        A pointer to the NFC primary registers.
+ * @secondary_regs:      A pointer to the NFC secondary registers.
+ * @clock:               A pointer to the NFC struct clk.
+ * @interrupt:           The NFC interrupt number.
+ * @physical_geometry:   A description of the medium's physical geometry.
+ * @nfc:                 A pointer to the NFC HAL.
+ * @nfc_geometry:        A description of the medium geometry as viewed by the
+ *                       NFC.
+ * @done:                The struct completion we use to handle interrupts.
+ * @logical_geometry:    A description of the logical geometry exposed to MTD.
+ * @interrupt_override:  Can override how the driver uses interrupts when
+ *                       waiting for the NFC.
+ * @auto_op_override:    Can override whether the driver uses automatic NFC
+ *                       operations.
+ * @inject_ecc_error:    Indicates that the driver should inject an ECC error in
+ *                       the next read operation that uses ECC. User space
+ *                       programs can set this value through the sysfs node of
+ *                       the same name. If this value is less than zero, the
+ *                       driver will inject an uncorrectable ECC error. If this
+ *                       value is greater than zero, the driver will inject that
+ *                       number of correctable errors, capped at whatever
+ *                       possible maximum currently applies.
+ * @current_chip:        The chip currently selected by the NAND Fash MTD HIL.
+ *                       A negative value indicates that no chip is selected.
+ *                       We use this field to detect when the HIL begins and
+ *                       ends essential transactions. This helps us to know when
+ *                       we should turn the NFC clock on or off.
+ * @command:             The last command the HIL tried to send by calling
+ *                       cmdfunc(). Later functions use this information to
+ *                       adjust their behavior. The sentinel value ~0 indicates
+ *                       no command.
+ * @command_is_new:      Indicates the command has just come down to cmdfunc()
+ *                       from the HIL and hasn't yet been handled. Other
+ *                       functions use this to adjust their behavior.
+ * @page_address:        The current page address of interest. For reads, this
+ *                       information arrives in calls to cmdfunc(), but we don't
+ *                       actually use it until later.
+ * @nand:                The data structure that represents this NAND Flash
+ *                       medium to the MTD NAND Flash system.
+ * @mtd:                 The data structure that represents this NAND Flash
+ *                       medium to MTD.
+ * @partitions:          A pointer to a set of partitions collected from one of
+ *                       several possible sources (e.g., the boot loader, the
+ *                       kernel command line, etc.). See the global variable
+ *                       partition_source_types for the list of partition
+ *                       sources we examine. If this member is NULL, then no
+ *                       partitions were discovered.
+ * @partition_count:     The number of discovered partitions.
+ */
+
+struct imx_nfc_data {
+
+	/* System Interface */
+	struct device                 *dev;
+	struct platform_device        *pdev;
+
+	/* Platform Configuration */
+	struct imx_nfc_platform_data  *pdata;
+	void                          *buffers;
+	void                          *primary_regs;
+	void                          *secondary_regs;
+	struct clk                    *clock;
+	unsigned int                  interrupt;
+
+	/* Flash Hardware */
+	struct physical_geometry      physical_geometry;
+
+	/* NFC HAL and NFC Utilities */
+	struct nfc_hal                *nfc;
+	struct nfc_geometry           *nfc_geometry;
+	struct completion             done;
+
+	/* Medium Abstraction Layer */
+	struct logical_geometry       logical_geometry;
+	enum override                 interrupt_override;
+	enum override                 auto_op_override;
+	int                           inject_ecc_error;
+
+	/* MTD Interface Layer */
+	int                           current_chip;
+	unsigned int                  command;
+	int                           command_is_new;
+	int                           page_address;
+
+	/* NAND Flash MTD */
+	struct nand_chip              nand;
+
+	/* MTD */
+	struct mtd_info               mtd;
+	struct mtd_partition          *partitions;
+	unsigned int                  partition_count;
+
+};
+
+/**
+ * struct nfc_hal - i.MX NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @major_version:       The major version number of the NFC to which this
+ *                       structure applies.
+ * @minor_version:       The minor version number of the NFC to which this
+ *                       structure applies.
+ * @max_chip_count:      The maximum number of chips the NFC can possibly
+ *                       support. This may *not* be the actual number of chips
+ *                       currently connected. This value is constant for NFC's
+ *                       of a given version.
+ * @max_buffer_count:    The number of main/spare buffers available in the NFC's
+ *                       memory. This value is constant for NFC's of a given
+ *                       version.
+ * @spare_buf_stride:    The stride, in bytes, from the beginning of one spare
+ *                       buffer to the beginning of the next one. This value is
+ *                       constant for NFC's of a given version.
+ * @has_secondary_regs:  Indicates if the NFC has a secondary register set that
+ *                       must be mapped in.
+ * @can_be_symmetric:    Indicates if the NFC supports a "symmetric" clock. When
+ *                       the clock is "symmetric," the hardware waits one NFC
+ *                       clock for every read/write cycle. When the clock is
+ *                       "asymmetric," the hardware waits two NFC clocks for
+ *                       every read/write cycle.
+ * @init:                Initializes the NFC and any version-specific data
+ *                       structures. This function will be called after
+ *                       everything has been set up for communication with the
+ *                       NFC itself, but before the platform has set up off-chip
+ *                       communication. Thus, this function must not attempt to
+ *                       communicate with the NAND Flash hardware. A non-zero
+ *                       return value indicates failure.
+ * @set_geometry:        Based on the physical geometry, this function selects
+ *                       an NFC geometry structure and configures the NFC
+ *                       hardware to match. A  non-zero return value indicates
+ *                       failure.
+ * @exit:                Shuts down the NFC and cleans up version-specific data
+ *                       structures. This function will be called after the
+ *                       platform has shut down off-chip communication but while
+ *                       communication with the NFC still works.
+ * @set_closest_cycle:   Configures the hardware to make the NAND Flash bus
+ *                       cycle period as close as possible to the given cycle
+ *                       period. This function is called during boot up and may
+ *                       assume that, at the time it's called, the parent clock
+ *                       is running at the highest rate it will ever run. Thus,
+ *                       this function need never worry that the NAND Flash bus
+ *                       will run faster and potentially make it impossible to
+ *                       communicate with the NAND Flash device -- it will only
+ *                       run slower.
+ * @mask_interrupt:      Masks the NFC's interrupt.
+ * @unmask_interrupt:    Unmasks the NFC's interrupt.
+ * @clear_interrupt:     Clears the NFC's interrupt.
+ * @is_interrupting:     Returns true if the NFC is interrupting.
+ * @is_ready:            Returns true if all the chips in the medium are ready.
+ *                       This member may be set to NULL, which indicates that
+ *                       the underlying NFC hardware doesn't expose  ready/busy
+ *                       signals.
+ * @set_force_ce:        If passed true, forces the hardware chip enable signal
+ *                       for the current chip to be asserted always. If passed
+ *                       false, causes the chip enable signal to be asserted
+ *                       only during I/O.
+ * @set_ecc:             Sets ECC on or off.
+ * @get_ecc_status:      Examines the hardware ECC status and returns:
+ *                           == 0  =>  No errors.
+ *                           >  0  =>  The number of corrected errors.
+ *                           <  0  =>  There were uncorrectable errors.
+ * @get_symmetric:       Gets the current symmetric clock setting. For versions
+ *                       that don't support symmetric clocks, this function
+ *                       always returns false.
+ * @set_symmetric:       For versions that support symmetric clocks, sets
+ *                       whether or not the clock is symmetric.
+ * @select_chip:         Selects the current chip.
+ * @command_cycle:       Sends a command code and then returns immediately
+ *                       *without* waiting for the NFC to finish.
+ * @write_cycle:         Applies a single write cycle to the current chip,
+ * 			 sending the given byte, and waiting for the NFC to
+ *                       finish.
+ * @read_cycle:          Applies a single read cycle to the current chip and
+ *                       returns the result, necessarily waiting for the NFC to
+ *                       finish. The width of the result is the same as the
+ *                       width of the Flash bus.
+ * @read_page:           Applies read cycles to the current chip to read an
+ *                       entire page into the NFC. Note that ECC is enabled or
+ *                       disabled with the set_ecc function pointer (see above).
+ *                       This function waits for the NFC to finish before
+ *                       returning.
+ * @send_page:           Applies write cycles to send an entire page from the
+ *                       NFC to the current chip. Note that ECC is enabled or
+ *                       disabled with the set_ecc function pointer (see above).
+ *                       This function waits for the NFC to finish before
+ *                       returning.
+ * @start_auto_read:     Starts an automatic read operation. A NULL pointer
+ *                       indicates automatic read operations aren't available
+ *                       with this NFC version.
+ * @wait_for_auto_read:  Blocks until an automatic read operation is ready for
+ *                       the CPU to copy a page out of the NFC.
+ * @resume_auto_read:    Resumes an automatic read operation after the CPU has
+ *                       copied a page out.
+ * @start_auto_write:    Starts an automatic write operation. A NULL pointer
+ *                       indicates automatic write operations aren't available
+ *                       with this NFC version.
+ * @wait_for_auto_write: Blocks until an automatic write operation is ready for
+ *                       the CPU to copy a page into the NFC.
+ * @start_auto_erase:    Starts an automatic erase operation. A NULL pointer
+ *                       indicates automatic erase operations aren't available
+ *                       with this NFC version.
+ */
+
+struct nfc_hal {
+	const unsigned int  major_version;
+	const unsigned int  minor_version;
+	const unsigned int  max_chip_count;
+	const unsigned int  max_buffer_count;
+	const unsigned int  spare_buf_stride;
+	const int           has_secondary_regs;
+	const int           can_be_symmetric;
+	int       (*init)               (struct imx_nfc_data *);
+	int       (*set_geometry)       (struct imx_nfc_data *);
+	void      (*exit)               (struct imx_nfc_data *);
+	int       (*set_closest_cycle)  (struct imx_nfc_data *, unsigned ns);
+	void      (*mask_interrupt)     (struct imx_nfc_data *);
+	void      (*unmask_interrupt)   (struct imx_nfc_data *);
+	void      (*clear_interrupt)    (struct imx_nfc_data *);
+	int       (*is_interrupting)    (struct imx_nfc_data *);
+	int       (*is_ready)           (struct imx_nfc_data *);
+	void      (*set_force_ce)       (struct imx_nfc_data *, int on);
+	void      (*set_ecc)            (struct imx_nfc_data *, int on);
+	int       (*get_ecc_status)     (struct imx_nfc_data *);
+	int       (*get_symmetric)      (struct imx_nfc_data *);
+	void      (*set_symmetric)      (struct imx_nfc_data *, int on);
+	void      (*select_chip)        (struct imx_nfc_data *, int chip);
+	void      (*command_cycle)      (struct imx_nfc_data *, unsigned cmd);
+	void      (*write_cycle)        (struct imx_nfc_data *, unsigned byte);
+	unsigned  (*read_cycle)         (struct imx_nfc_data *);
+	void      (*read_page)          (struct imx_nfc_data *);
+	void      (*send_page)          (struct imx_nfc_data *);
+	int       (*start_auto_read)    (struct imx_nfc_data *,
+		unsigned start, unsigned count, unsigned column, unsigned page);
+	int       (*wait_for_auto_read) (struct imx_nfc_data *);
+	int       (*resume_auto_read)   (struct imx_nfc_data *);
+	int       (*start_auto_write)   (struct imx_nfc_data *,
+		unsigned start, unsigned count, unsigned column, unsigned page);
+	int       (*wait_for_auto_write)(struct imx_nfc_data *);
+	int       (*start_auto_erase)   (struct imx_nfc_data *,
+		unsigned start, unsigned count, unsigned page);
+};
+
+/*
+ * This variable controls whether or not probing is enabled. If false, then
+ * the driver will refuse to probe. The "enable" module parameter controls the
+ * value of this variable.
+ */
+
+static int imx_nfc_module_enable = true;
+
+#ifdef EVENT_REPORTING
+
+/*
+ * This variable controls whether the driver reports event information by
+ * printing to the console. The "report_events" module parameter controls the
+ * value of this variable.
+ */
+
+static int imx_nfc_module_report_events; /* implicitly initialized false*/
+
+#endif
+
+/*
+ * This variable potentially overrides the driver's choice to interleave. The
+ * "interleave_override" module parameter controls the value of this variable.
+ */
+
+static enum override imx_nfc_module_interleave_override = DRIVER_CHOICE;
+
+/*
+ * When set, this variable forces the driver to use the bytewise copy functions
+ * to get data in and out of the NFC. This is intended for testing, not typical
+ * use.
+ */
+
+static int imx_nfc_module_force_bytewise_copy; /* implicitly initialized false*/
+
+/*
+ * The list of algorithms we use to get partition information from the
+ * environment.
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *partition_source_types[] = { "cmdlinepart", NULL };
+#endif
+
+/*
+ * The following structures describe the NFC geometries we support.
+ *
+ * Notice that pieces of some structure definitions are commented out and edited
+ * because various parts of the MTD system can't handle the way our hardware
+ * formats the out-of-band area.
+ *
+ * Here are the problems:
+ *
+ * - struct nand_ecclayout expects no more than 64 ECC bytes.
+ *
+ *     The eccpos member of struct nand_ecclayout can't hold more than 64 ECC
+ *     byte positions. Some of our formats have more so, unedited, they won't
+ *     even compile. We comment out all ECC byte positions after the 64th one.
+ *
+ * - struct nand_ecclayout expects no more than 8 free spans.
+ *
+ *     The oobfree member of struct nand_ecclayout can't hold more than 8 free
+ *     spans. Some of our formats have more so, unedited, they won't even
+ *     compile. We comment out all free spans after the eighth one.
+ *
+ * - The MEMGETOOBSEL command in the mtdchar driver.
+ *
+ *     The mtdchar ioctl command MEMGETOOBSEL checks the number of ECC bytes
+ *     against the length of the eccpos array in struct nand_oobinfo
+ *     (see include/mtd/mtd-abi.h). This array can handle up to 32 ECC bytes,
+ *     but some of our formats have more.
+ *
+ *     To make this work, we cap the value assigned to eccbytes at 32.
+ *
+ *     Notice that struct nand_oobinfo, used by mtdchar, is *different* from the
+ *     struct nand_ecclayout that MTD uses internally. The latter structure
+ *     can accomodate up to 64 ECC byte positions. Thus, we declare up to 64
+ *     ECC byte positions here, even if the advertised number of ECC bytes is
+ *     less.
+ *
+ *     This command is obsolete and, if no one used it, we wouldn't care about
+ *     this problem. Unfortunately The nandwrite program uses it, and everyone
+ *     expects nandwrite to work (it's how everyone usually lays down their
+ *     JFFS2 file systems).
+ */
+
+static struct nfc_geometry  nfc_geometry_512_16_RS_ECC1 = {
+	.page_data_size  = 512,
+	.page_oob_size   = 16,
+	.ecc_algorithm   = "Reed-Solomon",
+	.ecc_strength    = 1,
+	.buffer_count    = 1,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 5,
+		.eccpos   = {6, 7, 8, 9, 10},
+		.oobavail = 11,
+		.oobfree  = { {0, 6}, {11, 5} },
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_512_16_RS_ECC4 = {
+	.page_data_size  = 512,
+	.page_oob_size   = 16,
+	.ecc_algorithm   = "Reed-Solomon",
+	.ecc_strength    = 4,
+	.buffer_count    = 1,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 9,
+		.eccpos   = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+		.oobavail = 7,
+		.oobfree  = { {0, 7} },
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_512_16_BCH_ECC4 = {
+	.page_data_size  = 512,
+	.page_oob_size   = 16,
+	.ecc_algorithm   = "BCH",
+	.ecc_strength    = 4,
+	.buffer_count    = 1,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 8,
+		.eccpos   = {8, 9, 10, 11, 12, 13, 14, 15},
+		.oobavail = 8,
+		.oobfree  = { {0, 8} },
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_2K_64_RS_ECC4 = {
+	.page_data_size  = 2048,
+	.page_oob_size   = 64,
+	.ecc_algorithm   = "Reed-Solomon",
+	.ecc_strength    = 4,
+	.buffer_count    = 4,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 32 /*9 * 4*/, /* See notes above. */
+		.eccpos   = {
+
+			(0*16)+7 , (0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11,
+			(0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15,
+
+			(1*16)+7 , (1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11,
+			(1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15,
+
+			(2*16)+7 , (2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11,
+			(2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15,
+
+			(3*16)+7 , (3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11,
+			(3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15,
+
+		},
+		.oobavail = 7 * 4,
+		.oobfree  = {
+			{(0*16)+0, 7},
+			{(1*16)+0, 7},
+			{(2*16)+0, 7},
+			{(3*16)+0, 7},
+		},
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_2K_64_BCH_ECC4 = {
+	.page_data_size  = 2048,
+	.page_oob_size   = 64,
+	.ecc_algorithm   = "BCH",
+	.ecc_strength    = 4,
+	.buffer_count    = 4,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 8 * 4,
+		.eccpos   = {
+
+			(0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11,
+			(0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15,
+
+			(1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11,
+			(1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15,
+
+			(2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11,
+			(2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15,
+
+			(3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11,
+			(3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15,
+
+		},
+		.oobavail = 8 * 4,
+		.oobfree  = {
+			{(0*16)+0, 8},
+			{(1*16)+0, 8},
+			{(2*16)+0, 8},
+			{(3*16)+0, 8},
+		},
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_4K_128_BCH_ECC4 = {
+	.page_data_size  = 4096,
+	.page_oob_size   = 128,
+	.ecc_algorithm   = "BCH",
+	.ecc_strength    = 4,
+	.buffer_count    = 8,
+	.spare_buf_size  = 16,
+	.spare_buf_spill = 0,
+	.mtd_layout = {
+		.eccbytes = 8 * 8,
+		.eccpos   = {
+
+			(0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11,
+			(0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15,
+
+			(1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11,
+			(1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15,
+
+			(2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11,
+			(2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15,
+
+			(3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11,
+			(3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15,
+
+			(4*16)+8 , (4*16)+9 , (4*16)+10, (4*16)+11,
+			(4*16)+12, (4*16)+13, (4*16)+14, (4*16)+15,
+
+			(5*16)+8 , (5*16)+9 , (5*16)+10, (5*16)+11,
+			(5*16)+12, (5*16)+13, (5*16)+14, (5*16)+15,
+
+			(6*16)+8 , (6*16)+9 , (6*16)+10, (6*16)+11,
+			(6*16)+12, (6*16)+13, (6*16)+14, (6*16)+15,
+
+			(7*16)+8 , (7*16)+9 , (7*16)+10, (7*16)+11,
+			(7*16)+12, (7*16)+13, (7*16)+14, (7*16)+15,
+
+		},
+		.oobavail = 8 * 8,
+		.oobfree  = {
+			{(0*16)+0, 8},
+			{(1*16)+0, 8},
+			{(2*16)+0, 8},
+			{(3*16)+0, 8},
+			{(4*16)+0, 8},
+			{(5*16)+0, 8},
+			{(6*16)+0, 8},
+			{(7*16)+0, 8},
+		},
+	}
+};
+
+static struct nfc_geometry  nfc_geometry_4K_218_BCH_ECC8 = {
+	.page_data_size  = 4096,
+	.page_oob_size   = 218,
+	.ecc_algorithm   = "BCH",
+	.ecc_strength    = 8,
+	.buffer_count    = 8,
+	.spare_buf_size  = 26,
+	.spare_buf_spill = 10,
+	.mtd_layout = {
+		.eccbytes = 32 /*10 * 8*/, /* See notes above. */
+		.eccpos   = {
+
+			(0*26)+12, (0*26)+13, (0*26)+14, (0*26)+15, (0*26)+16,
+			(0*26)+17, (0*26)+18, (0*26)+19, (0*26)+20, (0*26)+21,
+
+			(1*26)+12, (1*26)+13, (1*26)+14, (1*26)+15, (1*26)+16,
+			(1*26)+17, (1*26)+18, (1*26)+19, (1*26)+20, (1*26)+21,
+
+			(2*26)+12, (2*26)+13, (2*26)+14, (2*26)+15, (2*26)+16,
+			(2*26)+17, (2*26)+18, (2*26)+19, (2*26)+20, (2*26)+21,
+
+			(3*26)+12, (3*26)+13, (3*26)+14, (3*26)+15, (3*26)+16,
+			(3*26)+17, (3*26)+18, (3*26)+19, (3*26)+20, (3*26)+21,
+
+			(4*26)+12, (4*26)+13, (4*26)+14, (4*26)+15, (4*26)+16,
+			(4*26)+17, (4*26)+18, (4*26)+19, (4*26)+20, (4*26)+21,
+
+			(5*26)+12, (5*26)+13, (5*26)+14, (5*26)+15, (5*26)+16,
+			(5*26)+17, (5*26)+18, (5*26)+19, (5*26)+20, (5*26)+21,
+
+			(6*26)+12, (6*26)+13, (6*26)+14, (6*26)+15,
+			/*  See notes above.
+			(6*26)+16,
+			(6*26)+17, (6*26)+18, (6*26)+19, (6*26)+20, (6*26)+21,
+
+			(7*26)+12, (7*26)+13, (7*26)+14, (7*26)+15, (7*26)+16,
+			(7*26)+17, (7*26)+18, (7*26)+19, (7*26)+20, (7*26)+21,
+			*/
+
+		},
+		.oobavail = 96 /*(16 * 8) + 10*/, /* See notes above. */
+		.oobfree  = {
+			{(0*26)+0, 12}, {(0*26)+22, 4},
+			{(1*26)+0, 12}, {(1*26)+22, 4},
+			{(2*26)+0, 12}, {(2*26)+22, 4},
+			{(3*26)+0, 48}, /* See notes above. */
+			/* See notes above.
+			{(3*26)+0, 12}, {(3*26)+22, 4},
+			{(4*26)+0, 12}, {(4*26)+22, 4},
+			{(5*26)+0, 12}, {(5*26)+22, 4},
+			{(6*26)+0, 12}, {(6*26)+22, 4},
+			{(7*26)+0, 12}, {(7*26)+22, 4 + 10},
+			*/
+		},
+	}
+};
+
+/*
+ * When the logical geometry differs from the NFC geometry (e.g.,
+ * interleaving), we synthesize a layout rather than use the one that comes with
+ * the NFC geometry. See mal_set_logical_geometry().
+ */
+
+static struct nand_ecclayout  synthetic_layout;
+
+/*
+ * These structures describe how the BBT code will find block marks in the OOB
+ * area of a page. Don't be confused by the fact that this is the same type used
+ * to describe bad block tables. Some of the same information is needed, so the
+ * designers use the same structure for two conceptually distinct functions.
+ */
+
+static uint8_t block_mark_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr small_page_block_mark_descriptor = {
+	.options = NAND_BBT_SCAN2NDPAGE,
+	.offs    = 5,
+	.len     = 1,
+	.pattern = block_mark_pattern,
+};
+
+static struct nand_bbt_descr large_page_block_mark_descriptor = {
+	.options = NAND_BBT_SCAN2NDPAGE,
+	.offs    = 0,
+	.len     = 2,
+	.pattern = block_mark_pattern,
+};
+
+/*
+ * Bad block table descriptors for the main and mirror tables.
+ */
+
+static uint8_t bbt_main_pattern[]   = { 'B', 'b', 't', '0' };
+static uint8_t bbt_mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descriptor = {
+	.options =
+		NAND_BBT_LASTBLOCK |
+		NAND_BBT_CREATE    |
+		NAND_BBT_WRITE     |
+		NAND_BBT_2BIT      |
+		NAND_BBT_VERSION   |
+		NAND_BBT_PERCHIP,
+	.offs      = 0,
+	.len       = 4,
+	.veroffs   = 4,
+	.maxblocks = 4,
+	.pattern   = bbt_main_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descriptor = {
+	.options =
+		NAND_BBT_LASTBLOCK |
+		NAND_BBT_CREATE    |
+		NAND_BBT_WRITE     |
+		NAND_BBT_2BIT      |
+		NAND_BBT_VERSION   |
+		NAND_BBT_PERCHIP,
+	.offs      = 0,
+	.len       = 4,
+	.veroffs   = 4,
+	.maxblocks = 4,
+	.pattern   = bbt_mirror_pattern,
+};
+
+#ifdef EVENT_REPORTING
+
+/**
+ * struct event - A single record in the event trace.
+ *
+ * @time:         The time at which the event occurred.
+ * @nesting:      Indicates function call nesting.
+ * @description:  A description of the event.
+ */
+
+struct event {
+	ktime_t       time;
+	unsigned int  nesting;
+	char          *description;
+};
+
+/**
+ * The event trace.
+ *
+ * @overhead:  The delay to take a time stamp and nothing else.
+ * @nesting:   The current nesting level.
+ * @overflow:  Indicates the trace overflowed.
+ * @next:      Index of the next event to write.
+ * @events:    The array of events.
+ */
+
+#define MAX_EVENT_COUNT  (200)
+
+static struct {
+	ktime_t       overhead;
+	int           nesting;
+	int           overflow;
+	unsigned int  next;
+	struct event  events[MAX_EVENT_COUNT];
+} event_trace;
+
+/**
+ * reset_event_trace() - Resets the event trace.
+ */
+static void reset_event_trace(void)
+{
+	event_trace.nesting  = 0;
+	event_trace.overflow = false;
+	event_trace.next     = 0;
+}
+
+/**
+ * add_event() - Adds an event to the event trace.
+ *
+ * @description:  A description of the event.
+ * @delta:        A delta to the nesting level for this event [-1, 0, 1].
+ */
+static inline void add_event(char *description, int delta)
+{
+	struct event  *event;
+
+	if (!imx_nfc_module_report_events)
+		return;
+
+	if (event_trace.overflow)
+		return;
+
+	if (event_trace.next >= MAX_EVENT_COUNT) {
+		event_trace.overflow = true;
+		return;
+	}
+
+	event = event_trace.events + event_trace.next;
+
+	event->time = ktime_get();
+
+	event->description = description;
+
+	if (!delta)
+		event->nesting = event_trace.nesting;
+	else if (delta < 0) {
+		event->nesting = event_trace.nesting - 1;
+		event_trace.nesting -= 2;
+	} else {
+		event->nesting = event_trace.nesting + 1;
+		event_trace.nesting += 2;
+	}
+
+	if (event_trace.nesting < 0)
+		event_trace.nesting = 0;
+
+	event_trace.next++;
+
+}
+
+/**
+ * add_state_event_l() - Adds an event to display some state.
+ *
+ * @address:   The address to examine.
+ * @mask:      A mask to apply to the contents of the given address.
+ * @clear:     An event message to add if the result is zero.
+ * @not_zero:  An event message to add if the result is not zero.
+ */
+static void add_state_event_l(void *address, uint32_t mask,
+						char *zero, char *not_zero)
+{
+	int  state;
+	state = !!(__raw_readl(address) & mask);
+	if (state)
+		add_event(not_zero, 0);
+	else
+		add_event(zero, 0);
+}
+
+/**
+ * start_event_trace() - Starts an event trace and adds the first event.
+ *
+ * @description:  A description of the first event.
+ */
+static void start_event_trace(char *description)
+{
+
+	ktime_t  t0;
+	ktime_t  t1;
+
+	if (!imx_nfc_module_report_events)
+		return;
+
+	reset_event_trace();
+
+	t0 = ktime_get();
+	t1 = ktime_get();
+
+	event_trace.overhead = ktime_sub(t1, t0);
+
+	add_event(description, 1);
+
+}
+
+/**
+ * dump_event_trace() - Dumps the event trace.
+ */
+static void dump_event_trace(void)
+{
+	unsigned int  i;
+	time_t        seconds;
+	long          nanoseconds;
+	char          line[100];
+	int           o;
+	struct event  *first_event;
+	struct event  *last_event;
+	struct event  *matching_event;
+	struct event  *event;
+	ktime_t       delta;
+
+	/* Check if event reporting is turned off. */
+
+	if (!imx_nfc_module_report_events)
+		return;
+
+	/* Print important facts about this event trace. */
+
+	printk(KERN_DEBUG "\n+--------------\n");
+
+	printk(KERN_DEBUG "|  Overhead    : [%d:%d]\n",
+				event_trace.overhead.tv.sec,
+				event_trace.overhead.tv.nsec);
+
+	if (!event_trace.next) {
+		printk(KERN_DEBUG "|  No Events\n");
+		return;
+	}
+
+	first_event = event_trace.events;
+	last_event  = event_trace.events + (event_trace.next - 1);
+
+	delta = ktime_sub(last_event->time, first_event->time);
+	printk(KERN_DEBUG "|  Elapsed Time: [%d:%d]\n",
+						delta.tv.sec, delta.tv.nsec);
+
+	if (event_trace.overflow)
+		printk(KERN_DEBUG "|  Overflow!\n");
+
+	/* Print the events in this history. */
+
+	for (i = 0, event = event_trace.events;
+					i < event_trace.next; i++, event++) {
+
+		/* Get the delta between this event and the previous event. */
+
+		if (!i) {
+			seconds     = 0;
+			nanoseconds = 0;
+		} else {
+			delta = ktime_sub(event[0].time, event[-1].time);
+			seconds     = delta.tv.sec;
+			nanoseconds = delta.tv.nsec;
+		}
+
+		/* Print the current event. */
+
+		o = 0;
+
+		o = snprintf(line, sizeof(line) - o, "|  [%ld:% 10ld]%*s %s",
+							seconds, nanoseconds,
+							event->nesting, "",
+							event->description);
+		/* Check if this is the last event in a nested series. */
+
+		if (i && (event[0].nesting < event[-1].nesting)) {
+
+			for (matching_event = event - 1;; matching_event--) {
+
+				if (matching_event < event_trace.events) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(event->time,
+							matching_event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" <%d:%d]", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		/* Check if this is the first event in a nested series. */
+
+		if ((i < event_trace.next - 1) &&
+				(event[0].nesting < event[1].nesting)) {
+
+			for (matching_event = event + 1;; matching_event++) {
+
+				if (matching_event >=
+					(event_trace.events+event_trace.next)) {
+					matching_event = 0;
+					break;
+				}
+
+				if (matching_event->nesting == event->nesting)
+					break;
+
+			}
+
+			if (matching_event) {
+				delta = ktime_sub(matching_event->time,
+								event->time);
+				o += snprintf(line + o, sizeof(line) - o,
+						" [%d:%d>", delta.tv.sec,
+								delta.tv.nsec);
+			}
+
+		}
+
+		printk(KERN_DEBUG "%s\n", line);
+
+	}
+
+	printk(KERN_DEBUG "+--------------\n");
+
+}
+
+/**
+ * stop_event_trace() - Stops an event trace.
+ *
+ * @description:  A description of the last event.
+ */
+static void stop_event_trace(char *description)
+{
+	struct event  *event;
+
+	if (!imx_nfc_module_report_events)
+		return;
+
+	/*
+	 * We want the end of the trace, no matter what happens. If the trace
+	 * has already overflowed, or is about to, just jam this event into the
+	 * last spot. Otherwise, add this event like any other.
+	 */
+
+	if (event_trace.overflow || (event_trace.next >= MAX_EVENT_COUNT)) {
+		event = event_trace.events + (MAX_EVENT_COUNT - 1);
+		event->time = ktime_get();
+		event->description = description;
+		event->nesting     = 0;
+	} else {
+		add_event(description, -1);
+	}
+
+	dump_event_trace();
+	reset_event_trace();
+
+}
+
+#else /* EVENT_REPORTING */
+
+#define start_event_trace(description)                   do {} while (0)
+#define add_event(description, delta)                    do {} while (0)
+#define add_state_event_l(address, mask, zero, not_zero) do {} while (0)
+#define stop_event_trace(description)                    do {} while (0)
+#define dump_event_trace()                               do {} while (0)
+
+#endif /* EVENT_REPORTING */
+
+/**
+ * unimplemented() - Announces intentionally unimplemented features.
+ *
+ * @this:  Per-device data.
+ * @msg:   A message about the unimplemented feature.
+ */
+static inline void unimplemented(struct imx_nfc_data *this, const char * msg)
+{
+	dev_err(this->dev, "Intentionally unimplemented: %s", msg);
+}
+
+/**
+ * raw_read_mask_w() - Reads masked bits in a 16-bit hardware register.
+ */
+static inline uint16_t raw_read_mask_w(uint16_t mask, void *address)
+{
+	return __raw_readw(address) & mask;
+}
+
+/**
+ * raw_set_mask_w() - Sets bits in a 16-bit hardware register.
+ */
+static inline void raw_set_mask_w(uint16_t mask, void *address)
+{
+	__raw_writew(__raw_readw(address) | mask, address);
+}
+
+/**
+ * raw_clr_mask_w() - Clears bits in a 16-bit hardware register.
+ */
+static inline void raw_clr_mask_w(uint16_t mask, void *address)
+{
+	__raw_writew(__raw_readw(address) & (~mask), address);
+}
+
+/**
+ * raw_read_mask_l() - Reads masked bits in a 32-bit hardware register.
+ */
+static inline uint32_t raw_read_mask_l(uint32_t mask, void *address)
+{
+	return __raw_readl(address) & mask;
+}
+
+/**
+ * raw_set_mask_l() - Sets bits in a 32-bit hardware register.
+ */
+static inline void raw_set_mask_l(uint32_t mask, void *address)
+{
+	__raw_writel(__raw_readl(address) | mask, address);
+}
+
+/**
+ * raw_clr_mask_l() - Clears bits in a 32-bit hardware register.
+ */
+static inline void raw_clr_mask_l(uint32_t mask, void *address)
+{
+	__raw_writel(__raw_readl(address) & (~mask), address);
+}
+
+/**
+ * is_large_page_chip() - Returns true for large page media.
+ *
+ * @this:  Per-device data.
+ */
+static inline int is_large_page_chip(struct imx_nfc_data *this)
+{
+	return (this->physical_geometry.page_data_size > 512);
+}
+
+/**
+ * is_small_page_chip() - Returns true for small page media.
+ *
+ * @this:  Per-device data.
+ */
+static inline int is_small_page_chip(struct imx_nfc_data *this)
+{
+	return !is_large_page_chip(this);
+}
+
+/**
+ * get_cycle_in_ns() - Returns the given device's cycle period, in ns.
+ *
+ * @this:  Per-device data.
+ */
+static inline unsigned get_cycle_in_ns(struct imx_nfc_data *this)
+{
+	unsigned long  cycle_in_ns;
+
+	cycle_in_ns = 1000000000 / clk_get_rate(this->clock);
+
+	if (!this->nfc->get_symmetric(this))
+		cycle_in_ns *= 2;
+
+	return cycle_in_ns;
+
+}
+
+/**
+ * nfc_util_set_best_cycle() - Sets the closest possible NAND Flash bus cycle.
+ *
+ * This function computes the clock setup that will best approximate the given
+ * target Flash bus cycle period.
+ *
+ * For some NFC versions, we can make the clock "symmetric." When the clock
+ * is "symmetric," the hardware waits one NFC clock for every read/write cycle.
+ * When the clock is "asymmetric," the hardware waits two NFC clocks for every
+ * read/write cycle. Thus, making the clock asymmetric essentially divides the
+ * NFC clock by two.
+ *
+ * We compute the target frequency that matches the given target period. We then
+ * discover the closest available match with that frequency and the closest
+ * available match with double that frequency (for use with an asymmetric
+ * clock). We implement the best choice of original clock and symmetric or
+ * asymmetric setting, preferring symmetric clocks.
+ *
+ * @this:      Per-device data.
+ * @ns:        The target cycle period, in nanoseconds.
+ * @no_asym:   Disallow making the clock asymmetric.
+ * @no_sym:    Disallow making the clock  symmetric.
+ */
+static int nfc_util_set_best_cycle(struct imx_nfc_data *this,
+				unsigned int ns, int no_asym, int no_sym)
+{
+	unsigned long  target_hz;
+	long           symmetric_hz;
+	long           symmetric_delta_hz;
+	long           asymmetric_hz;
+	long           asymmetric_delta_hz;
+	unsigned long  best_hz;
+	int            best_symmetry_setting;
+	struct device  *dev = this->dev;
+
+	/* The target cycle period must be greater than zero. */
+
+	if (!ns)
+		return -EINVAL;
+
+	/* Compute the target frequency. */
+
+	target_hz = 1000000000 / ns;
+
+	/* Find out how close we can get with a symmetric clock. */
+
+	if (!no_sym && this->nfc->can_be_symmetric)
+		symmetric_hz = clk_round_rate(this->clock, target_hz);
+	else
+		symmetric_hz = -EINVAL;
+
+	/* Find out how close we can get with an asymmetric clock. */
+
+	if (!no_asym)
+		asymmetric_hz = clk_round_rate(this->clock, target_hz * 2);
+	else
+		asymmetric_hz = -EINVAL;
+
+	/* Does anything work at all? */
+
+	if ((symmetric_hz == -EINVAL) && (asymmetric_hz == -EINVAL)) {
+		dev_err(dev, "Can't support Flash bus cycle of %uns\n", ns);
+		return -EINVAL;
+	}
+
+	/* Discover the best match. */
+
+	if ((symmetric_hz != -EINVAL) && (asymmetric_hz != -EINVAL)) {
+
+		symmetric_delta_hz  = target_hz - symmetric_hz;
+		asymmetric_delta_hz = target_hz - (asymmetric_hz / 2);
+
+		if (symmetric_delta_hz <= asymmetric_delta_hz)
+			best_symmetry_setting = true;
+		else
+			best_symmetry_setting = false;
+
+	} else if (symmetric_hz != -EINVAL) {
+		best_symmetry_setting = true;
+	} else {
+		best_symmetry_setting = false;
+	}
+
+	best_hz = best_symmetry_setting ? symmetric_hz : asymmetric_hz;
+
+	/* Implement the best match. */
+
+	this->nfc->set_symmetric(this, best_symmetry_setting);
+
+	return clk_set_rate(this->clock, best_hz);
+
+}
+
+/**
+ * nfc_util_wait_for_the_nfc() - Waits for the NFC to finish an operation.
+ *
+ * @this:     Per-device data.
+ * @use_irq:  Indicates that we should wait for an interrupt rather than polling
+ *            and delaying.
+ */
+static void nfc_util_wait_for_the_nfc(struct imx_nfc_data *this, int use_irq)
+{
+	unsigned       spin_count;
+	struct device  *dev = this->dev;
+
+	/* Apply the override, if any. */
+
+	switch (this->interrupt_override) {
+
+	case NEVER:
+		use_irq = false;
+		break;
+
+	case DRIVER_CHOICE:
+		break;
+
+	case ALWAYS:
+		use_irq = true;
+		break;
+
+	}
+
+	/* Check if we're using interrupts. */
+
+	if (use_irq) {
+
+		/*
+		 * If control arrives here, the caller wants to use interrupts.
+		 * Presumably, this operation is known to take a very long time.
+		 */
+
+		if (this->nfc->is_interrupting(this)) {
+			add_event("Waiting for the NFC (early interrupt)", 1);
+			this->nfc->clear_interrupt(this);
+		} else {
+			add_event("Waiting for the NFC (interrupt)", 1);
+			this->nfc->unmask_interrupt(this);
+			wait_for_completion(&this->done);
+		}
+
+		add_event("NFC done", -1);
+
+	} else {
+
+		/*
+		 * If control arrives here, the caller doesn't want to use
+		 * interrupts. Presumably, this operation is too quick to
+		 * justify the overhead. Leave the interrupt masked, and loop
+		 * until the interrupt bit lights up, or we time out.
+		 *
+		 * We spin for a maximum of about 2ms before declaring a time
+		 * out. No operation we could possibly spin on should take that
+		 * long.
+		 */
+
+		spin_count = 2000;
+
+		add_event("Waiting for the NFC (polling)", 1);
+
+		for (; spin_count > 0; spin_count--) {
+
+			if (this->nfc->is_interrupting(this)) {
+				this->nfc->clear_interrupt(this);
+				add_event("NFC done", -1);
+				return;
+			}
+
+			udelay(1);
+
+		}
+
+		/* Timed out. */
+
+		add_event("Timed out", -1);
+
+		dev_err(dev, "[wait_for_the_nfc] ===== Time Out =====\n");
+		dump_event_trace();
+
+	}
+
+}
+
+/**
+ *  nfc_util_bytewise_copy_from_nfc_mem() - Copies bytes from the NFC memory.
+ *
+ * @from:  A pointer to the source memory.
+ * @to:    A pointer to the destination memory.
+ * @size:  The number of bytes to copy.
+ */
+static void nfc_util_bytewise_copy_from_nfc_mem(const void *from,
+							void *to, size_t n)
+{
+	unsigned int   i;
+	const uint8_t  *f = from;
+	uint8_t        *t = to;
+	uint16_t       *p;
+	uint16_t       x;
+
+	for (i = 0; i < n; i++, f++, t++) {
+
+		p = (uint16_t *) (((unsigned long) f) & ~((unsigned long) 1));
+
+		x = __raw_readw(p);
+
+		if (((unsigned long) f) & 0x1)
+			*t = (x >> 8) & 0xff;
+		else
+			*t = (x >> 0) & 0xff;
+
+	}
+
+}
+
+/**
+ * nfc_util_bytewise_copy_to_nfc_mem() - Copies bytes to the NFC memory.
+ *
+ * @from:  A pointer to the source memory.
+ * @to:    A pointer to the destination memory.
+ * @size:  The number of bytes to copy.
+ */
+static void nfc_util_bytewise_copy_to_nfc_mem(const void *from,
+							void *to, size_t n)
+{
+	unsigned int   i;
+	const uint8_t  *f = from;
+	uint8_t        *t = to;
+	uint16_t       *p;
+	uint16_t       x;
+
+	for (i = 0; i < n; i++, f++, t++) {
+
+		p = (uint16_t *) (((unsigned long) t) & ~((unsigned long) 1));
+
+		x = __raw_readw(p);
+
+		if (((unsigned long) t) & 0x1)
+			((uint8_t *)(&x))[1] = *f;
+		else
+			((uint8_t *)(&x))[0] = *f;
+
+		__raw_writew(x, p);
+
+	}
+
+}
+
+/**
+ * nfc_util_copy_from_nfc_mem() - Copies from the NFC memory to main memory.
+ *
+ * @from:  A pointer to the source memory.
+ * @to:    A pointer to the destination memory.
+ * @size:  The number of bytes to copy.
+ */
+static void nfc_util_copy_from_nfc_mem(const void *from, void *to, size_t n)
+{
+	unsigned int  chunk_count;
+
+	/*
+	 * Check if we're testing bytewise copies.
+	 */
+
+	if (imx_nfc_module_force_bytewise_copy)
+		goto force_bytewise_copy;
+
+	/*
+	 * We'd like to use memcpy to get data out of the NFC but, because that
+	 * memory responds only to 16- and 32-byte reads, we can only do so
+	 * safely if both the start and end of both the source and destination
+	 * are perfectly aligned on 4-byte boundaries.
+	 */
+
+	if (!(((unsigned long) from) & 0x3) && !(((unsigned long) to) & 0x3)) {
+
+		/*
+		 * If control arrives here, both the source and destination are
+		 * aligned on 4-byte boundaries. Compute the number of whole,
+		 * 4-byte chunks we can move.
+		 */
+
+		chunk_count = n / 4;
+
+		/*
+		 * Move all the chunks we can, and then update the pointers and
+		 * byte count to show what's left.
+		 */
+
+		if (chunk_count) {
+			memcpy(to, from, chunk_count * 4);
+			from += chunk_count * 4;
+			to   += chunk_count * 4;
+			n    -= chunk_count * 4;
+		}
+
+	}
+
+	/*
+	 * Move what's left.
+	 */
+
+force_bytewise_copy:
+
+	nfc_util_bytewise_copy_from_nfc_mem(from, to, n);
+
+}
+
+/**
+ * nfc_util_copy_to_nfc_mem() - Copies from main memory to the NFC memory.
+ *
+ * @from:  A pointer to the source memory.
+ * @to:    A pointer to the destination memory.
+ * @size:  The number of bytes to copy.
+ */
+static void nfc_util_copy_to_nfc_mem(const void *from, void *to, size_t n)
+{
+	unsigned int  chunk_count;
+
+	/*
+	 * Check if we're testing bytewise copies.
+	 */
+
+	if (imx_nfc_module_force_bytewise_copy)
+		goto force_bytewise_copy;
+
+	/*
+	 * We'd like to use memcpy to get data into the NFC but, because that
+	 * memory responds only to 16- and 32-byte writes, we can only do so
+	 * safely if both the start and end of both the source and destination
+	 * are perfectly aligned on 4-byte boundaries.
+	 */
+
+	if (!(((unsigned long) from) & 0x3) && !(((unsigned long) to) & 0x3)) {
+
+		/*
+		 * If control arrives here, both the source and destination are
+		 * aligned on 4-byte boundaries. Compute the number of whole,
+		 * 4-byte chunks we can move.
+		 */
+
+		chunk_count = n / 4;
+
+		/*
+		 * Move all the chunks we can, and then update the pointers and
+		 * byte count to show what's left.
+		 */
+
+		if (chunk_count) {
+			memcpy(to, from, chunk_count * 4);
+			from += chunk_count * 4;
+			to   += chunk_count * 4;
+			n    -= chunk_count * 4;
+		}
+
+	}
+
+	/*
+	 * Move what's left.
+	 */
+
+force_bytewise_copy:
+
+	nfc_util_bytewise_copy_to_nfc_mem(from, to, n);
+
+}
+
+/**
+ * nfc_util_copy_from_the_nfc() - Copies bytes out of the NFC.
+ *
+ * This function makes the data in the NFC look like a contiguous, model page.
+ *
+ * @this:   Per-device data.
+ * @start:  The index of the starting byte in the NFC.
+ * @buf:    A pointer to the destination buffer.
+ * @len:    The number of bytes to copy out.
+ */
+static void nfc_util_copy_from_the_nfc(struct imx_nfc_data *this,
+			unsigned int start, uint8_t *buf, unsigned int len)
+{
+	unsigned int         i;
+	unsigned int         count;
+	unsigned int         offset;
+	unsigned int         data_size;
+	unsigned int         oob_size;
+	unsigned int         total_size;
+	void                 *spare_base;
+	unsigned int         first_spare;
+	void                 *from;
+	struct nfc_geometry  *geometry = this->nfc_geometry;
+
+	/*
+	 * During initialization, the HIL will attempt to read ID bytes. For
+	 * some NFC hardware versions, the ID bytes are deposited in the NFC
+	 * memory, so this function will be called to deliver them. At that
+	 * point, we won't know the NFC geometry. That's OK because we're only
+	 * going to be reading a byte at a time.
+	 *
+	 * If we don't yet know the NFC geometry, just plug in some values that
+	 * make things work for now.
+	 */
+
+	if (unlikely(!geometry)) {
+		data_size = NFC_MAIN_BUF_SIZE;
+		oob_size  = 0;
+	} else {
+		data_size = geometry->page_data_size;
+		oob_size  = geometry->page_oob_size;
+	}
+
+	total_size = data_size + oob_size;
+
+	/* Validate. */
+
+	if ((start >= total_size) || ((start + len) > total_size)) {
+		dev_err(this->dev, "Bad copy from NFC memory: [%u, %u]\n",
+								start, len);
+		return;
+	}
+
+	/* Check if we're copying anything at all. */
+
+	if (!len)
+		return;
+
+	/* Check if anything comes from the main area. */
+
+	if (start < data_size) {
+
+		/* Compute the bytes to copy from the main area. */
+
+		count = min(len, data_size - start);
+
+		/* Copy. */
+
+		nfc_util_copy_from_nfc_mem(this->buffers + start, buf, count);
+
+		buf   += count;
+		start += count;
+		len   -= count;
+
+	}
+
+	/* Check if we're done. */
+
+	if (!len)
+		return;
+
+	/* Compute the base address of the spare buffers. */
+
+	spare_base = this->buffers +
+			(this->nfc->max_buffer_count * NFC_MAIN_BUF_SIZE);
+
+	/* Discover in which spare buffer the copying begins. */
+
+	first_spare = (start - data_size) / geometry->spare_buf_size;
+
+	/* Check if anything comes from the regular spare buffer area. */
+
+	if (first_spare < geometry->buffer_count) {
+
+		/* Start copying from spare buffers. */
+
+		for (i = first_spare; i < geometry->buffer_count; i++) {
+
+			/* Compute the offset into this spare area. */
+
+			offset = start -
+				(data_size + (geometry->spare_buf_size * i));
+
+			/* Compute the address of that offset. */
+
+			from = spare_base + offset +
+					(this->nfc->spare_buf_stride * i);
+
+			/* Compute the bytes to copy from this spare area. */
+
+			count = min(len, geometry->spare_buf_size - offset);
+
+			/* Copy. */
+
+			nfc_util_copy_from_nfc_mem(from, buf, count);
+
+			buf   += count;
+			start += count;
+			len   -= count;
+
+		}
+
+	}
+
+	/* Check if we're done. */
+
+	if (!len)
+		return;
+
+	/* Compute the offset into the extra spare area. */
+
+	offset = start -
+		(data_size + (geometry->spare_buf_size*geometry->buffer_count));
+
+	/* Compute the address of that offset. */
+
+	from = spare_base + offset +
+			(this->nfc->spare_buf_stride * geometry->buffer_count);
+
+	/* Compute the bytes to copy from the extra spare area. */
+
+	count = min(len, geometry->spare_buf_spill - offset);
+
+	/* Copy. */
+
+	nfc_util_copy_from_nfc_mem(from, buf, count);
+
+}
+
+/**
+ * nfc_util_copy_to_the_nfc() - Copies bytes into the NFC memory.
+ *
+ * This function makes the data in the NFC look like a contiguous, model page.
+ *
+ * @this:   Per-device data.
+ * @buf:   A pointer to the source buffer.
+ * @start: The index of the starting byte in the NFC memory.
+ * @len:   The number of bytes to copy in.
+ */
+static void nfc_util_copy_to_the_nfc(struct imx_nfc_data *this,
+		const uint8_t *buf, unsigned int start, unsigned int len)
+{
+	unsigned int         i;
+	unsigned int         count;
+	unsigned int         offset;
+	unsigned int         data_size;
+	unsigned int         oob_size;
+	unsigned int         total_size;
+	void                 *spare_base;
+	unsigned int         first_spare;
+	void                 *to;
+	struct nfc_geometry  *geometry = this->nfc_geometry;
+
+	/* Establish some important facts. */
+
+	data_size  = geometry->page_data_size;
+	oob_size   = geometry->page_oob_size;
+	total_size = data_size + oob_size;
+
+	/* Validate. */
+
+	if ((start >= total_size) || ((start + len) > total_size)) {
+		dev_err(this->dev, "Bad copy to NFC memory: [%u, %u]\n",
+								start, len);
+		return;
+	}
+
+	/* Check if we're copying anything at all. */
+
+	if (!len)
+		return;
+
+	/* Check if anything goes to the main area. */
+
+	if (start < data_size) {
+
+		/* Compute the bytes to copy to the main area. */
+
+		count = min(len, data_size - start);
+
+		/* Copy. */
+
+		nfc_util_copy_to_nfc_mem(buf, this->buffers + start, count);
+
+		buf   += count;
+		start += count;
+		len   -= count;
+
+	}
+
+	/* Check if we're done. */
+
+	if (!len)
+		return;
+
+	/* Compute the base address of the spare buffers. */
+
+	spare_base = this->buffers +
+			(this->nfc->max_buffer_count * NFC_MAIN_BUF_SIZE);
+
+	/* Discover in which spare buffer the copying begins. */
+
+	first_spare = (start - data_size) / geometry->spare_buf_size;
+
+	/* Check if anything goes to the regular spare buffer area. */
+
+	if (first_spare < geometry->buffer_count) {
+
+		/* Start copying to spare buffers. */
+
+		for (i = first_spare; i < geometry->buffer_count; i++) {
+
+			/* Compute the offset into this spare area. */
+
+			offset = start -
+				(data_size + (geometry->spare_buf_size * i));
+
+			/* Compute the address of that offset. */
+
+			to = spare_base + offset +
+					(this->nfc->spare_buf_stride * i);
+
+			/* Compute the bytes to copy to this spare area. */
+
+			count = min(len, geometry->spare_buf_size - offset);
+
+			/* Copy. */
+
+			nfc_util_copy_to_nfc_mem(buf, to, count);
+
+			buf   += count;
+			start += count;
+			len   -= count;
+
+		}
+
+	}
+
+	/* Check if we're done. */
+
+	if (!len)
+		return;
+
+	/* Compute the offset into the extra spare area. */
+
+	offset = start -
+		(data_size + (geometry->spare_buf_size*geometry->buffer_count));
+
+	/* Compute the address of that offset. */
+
+	to = spare_base + offset +
+			(this->nfc->spare_buf_stride * geometry->buffer_count);
+
+	/* Compute the bytes to copy to the extra spare area. */
+
+	count = min(len, geometry->spare_buf_spill - offset);
+
+	/* Copy. */
+
+	nfc_util_copy_to_nfc_mem(buf, to, count);
+
+}
+
+/**
+ * nfc_util_isr() - i.MX NFC ISR.
+ *
+ * @irq:      The arriving interrupt number.
+ * @context:  A cookie for this ISR.
+ */
+static irqreturn_t nfc_util_isr(int irq, void *cookie)
+{
+	struct imx_nfc_data  *this = cookie;
+	this->nfc->mask_interrupt(this);
+	this->nfc->clear_interrupt(this);
+	complete(&this->done);
+	return IRQ_HANDLED;
+}
+
+/**
+ * nfc_util_send_cmd() - Sends a command to the current chip, without waiting.
+ *
+ * @this:     Per-device data.
+ * @command:  The command code.
+ */
+
+static void nfc_util_send_cmd(struct imx_nfc_data *this, unsigned int command)
+{
+
+	add_event("Entering nfc_util_send_cmd", 1);
+
+	this->nfc->command_cycle(this, command);
+
+	add_event("Exiting nfc_util_send_cmd", -1);
+
+}
+
+/**
+ * nfc_util_send_cmd_and_addrs() - Sends a cmd and addrs to the current chip.
+ *
+ * This function conveniently combines sending a command, and then sending
+ * optional addresses, waiting for the NFC to finish will all steps.
+ *
+ * @this:     Per-device data.
+ * @command:  The command code.
+ * @column:   The column address to send, or -1 if no column address applies.
+ * @page:     The page address to send, or -1 if no page address applies.
+ */
+
+static void nfc_util_send_cmd_and_addrs(struct imx_nfc_data *this,
+					unsigned command, int column, int page)
+{
+	uint32_t  page_mask;
+
+	add_event("Entering nfc_util_send_cmd_and_addrs", 1);
+
+	/* Send the command.*/
+
+	add_event("Sending the command...", 0);
+
+	nfc_util_send_cmd(this, command);
+
+	nfc_util_wait_for_the_nfc(this, false);
+
+	/* Send the addresses. */
+
+	add_event("Sending the addresses...", 0);
+
+	if (column != -1) {
+
+		this->nfc->write_cycle(this, (column >> 0) & 0xff);
+
+		if (is_large_page_chip(this))
+			this->nfc->write_cycle(this, (column >> 8) & 0xff);
+
+	}
+
+	if (page != -1) {
+
+		page_mask = this->nand.pagemask;
+
+		do {
+			this->nfc->write_cycle(this, page & 0xff);
+			page_mask >>= 8;
+			page      >>= 8;
+		} while (page_mask != 0);
+
+	}
+
+	add_event("Exiting nfc_util_send_cmd_and_addrs", -1);
+
+}
+
+/**
+ * nfc_2_x_exit() - Version-specific shut down.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_x_exit(struct imx_nfc_data *this)
+{
+}
+
+/**
+ * nfc_2_x_clear_interrupt() - Clears an interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_x_clear_interrupt(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+	raw_clr_mask_w(NFC_2_X_CONFIG2_INT_MSK, base + NFC_2_X_CONFIG2_REG_OFF);
+}
+
+/**
+ * nfc_2_x_is_interrupting() - Returns the interrupt bit status.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_2_x_is_interrupting(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+	return raw_read_mask_w(NFC_2_X_CONFIG2_INT_MSK,
+						base + NFC_2_X_CONFIG2_REG_OFF);
+}
+
+/**
+ * nfc_2_x_command_cycle() - Sends a command.
+ *
+ * @this:     Per-device data.
+ * @command:  The command code.
+ */
+static void nfc_2_x_command_cycle(struct imx_nfc_data *this, unsigned command)
+{
+	void  *base = this->primary_regs;
+
+	/* Write the command we want to send. */
+
+	__raw_writew(command, base + NFC_2_X_FLASH_CMD_REG_OFF);
+
+	/* Launch a command cycle. */
+
+	__raw_writew(NFC_2_X_CONFIG2_FCMD_MSK, base + NFC_2_X_CONFIG2_REG_OFF);
+
+}
+
+/**
+ * nfc_2_x_write_cycle() - Writes a single byte.
+ *
+ * @this:  Per-device data.
+ * @byte:  The byte.
+ */
+static void nfc_2_x_write_cycle(struct imx_nfc_data *this, unsigned int byte)
+{
+	void  *base = this->primary_regs;
+
+	/* Give the NFC the byte we want to write. */
+
+	__raw_writew(byte, base + NFC_2_X_FLASH_ADDR_REG_OFF);
+
+	/* Launch an address cycle.
+	 *
+	 * This is *sort* of a hack, but not really. The intent of the NFC
+	 * design is for this operation to send an address byte. In fact, the
+	 * NFC neither knows nor cares what we're sending. It justs runs a write
+	 * cycle.
+	 */
+
+	__raw_writew(NFC_2_X_CONFIG2_FADD_MSK, base + NFC_2_X_CONFIG2_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, false);
+
+}
+
+/**
+ * nfc_2_0_init() - Version-specific hardware initialization.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_2_0_init(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+
+	/* Initialize the interrupt machinery. */
+
+	this->nfc->mask_interrupt(this);
+	this->nfc->clear_interrupt(this);
+
+	/* Unlock the NFC memory. */
+
+	__raw_writew(0x2, base + NFC_2_X_CONFIG_REG_OFF);
+
+	/* Set the unlocked block range to cover the entire medium. */
+
+	__raw_writew(0 , base + NFC_2_0_UNLOCK_START_REG_OFF);
+	__raw_writew(~0, base + NFC_2_0_UNLOCK_END_REG_OFF);
+
+	/* Unlock all blocks. */
+
+	__raw_writew(0x4, base + NFC_2_X_WR_PROT_REG_OFF);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * nfc_2_0_mask_interrupt() - Masks interrupts.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_0_mask_interrupt(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+	raw_set_mask_w(NFC_2_0_CONFIG1_INT_MSK_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+}
+
+/**
+ * nfc_2_0_unmask_interrupt() - Unmasks interrupts.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_0_unmask_interrupt(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+	raw_clr_mask_w(NFC_2_0_CONFIG1_INT_MSK_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+}
+
+/**
+ * nfc_2_0_set_ecc() - Turns ECC on or off.
+ *
+ * @this:  Per-device data.
+ * @on:    Indicates if ECC should be on or off.
+ */
+static void nfc_2_0_set_ecc(struct imx_nfc_data *this, int on)
+{
+	void  *base = this->primary_regs;
+
+	if (on)
+		raw_set_mask_w(NFC_2_0_CONFIG1_ECC_EN_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+	else
+		raw_clr_mask_w(NFC_2_0_CONFIG1_ECC_EN_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+
+}
+
+/**
+ * nfc_2_0_get_ecc_status() - Reports ECC errors.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_2_0_get_ecc_status(struct imx_nfc_data *this)
+{
+	unsigned int  i;
+	void          *base = this->primary_regs;
+	uint16_t      status_reg;
+	unsigned int  buffer_status[4];
+	int           status;
+
+	/* Get the entire status register. */
+
+	status_reg = __raw_readw(base + NFC_2_0_ECC_STATUS_REG_OFF);
+
+	/* Pick out the status for each buffer. */
+
+	buffer_status[0] = (status_reg & NFC_2_0_ECC_STATUS_NOSER1_MSK)
+					>> NFC_2_0_ECC_STATUS_NOSER1_POS;
+
+	buffer_status[1] = (status_reg & NFC_2_0_ECC_STATUS_NOSER2_MSK)
+					>> NFC_2_0_ECC_STATUS_NOSER2_POS;
+
+	buffer_status[2] = (status_reg & NFC_2_0_ECC_STATUS_NOSER3_MSK)
+					>> NFC_2_0_ECC_STATUS_NOSER3_POS;
+
+	buffer_status[3] = (status_reg & NFC_2_0_ECC_STATUS_NOSER4_MSK)
+					>> NFC_2_0_ECC_STATUS_NOSER4_POS;
+
+	/* Loop through the buffers we're actually using. */
+
+	status = 0;
+
+	for (i = 0; i < this->nfc_geometry->buffer_count; i++) {
+
+		if (buffer_status[i] > this->nfc_geometry->ecc_strength) {
+			status = -1;
+			break;
+		}
+
+		status += buffer_status[i];
+
+	}
+
+	/* Return the final result. */
+
+	return status;
+
+}
+
+/**
+ * nfc_2_0_get_symmetric() - Indicates if the clock is symmetric.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_2_0_get_symmetric(struct imx_nfc_data *this)
+{
+	void  *base = this->primary_regs;
+
+	return !!raw_read_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+
+}
+
+/**
+ * nfc_2_0_set_symmetric() - Turns symmetric clock mode on or off.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_0_set_symmetric(struct imx_nfc_data *this, int on)
+{
+	void  *base = this->primary_regs;
+
+	if (on)
+		raw_set_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+	else
+		raw_clr_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK,
+						base + NFC_2_0_CONFIG1_REG_OFF);
+
+}
+
+/**
+ * nfc_2_0_set_geometry() - Configures for the medium geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_2_0_set_geometry(struct imx_nfc_data *this)
+{
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	/* Select an NFC geometry. */
+
+	switch (physical->page_data_size) {
+
+	case 512:
+		this->nfc_geometry = &nfc_geometry_512_16_RS_ECC4;
+		break;
+
+	case 2048:
+		this->nfc_geometry = &nfc_geometry_2K_64_RS_ECC4;
+		break;
+
+	default:
+		dev_err(this->dev, "NFC can't handle page size: %u",
+						physical->page_data_size);
+		return !0;
+		break;
+
+	}
+
+	/*
+	 * This NFC version receives page size information from a register
+	 * that's external to the NFC. We must rely on platform-specific code
+	 * to set this register for us.
+	 */
+
+	return this->pdata->set_page_size(physical->page_data_size);
+
+}
+
+/**
+ * nfc_2_0_select_chip() - Selects the current chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip number to select, or -1 to select no chip.
+ */
+static void nfc_2_0_select_chip(struct imx_nfc_data *this, int chip)
+{
+}
+
+/**
+ * nfc_2_0_read_cycle() - Applies a single read cycle to the current chip.
+ *
+ * @this:  Per-device data.
+ */
+static unsigned int nfc_2_0_read_cycle(struct imx_nfc_data *this)
+{
+	uint8_t       byte;
+	unsigned int  result;
+	void          *base = this->primary_regs;
+
+	/* Read into main buffer 0. */
+
+	__raw_writew(0x0, base + NFC_2_0_BUF_ADDR_REG_OFF);
+
+	/* Launch a "Data Out" operation. */
+
+	__raw_writew(0x4 << NFC_2_X_CONFIG2_FDO_POS,
+						base + NFC_2_X_CONFIG2_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, false);
+
+	/* Get the result from the NFC memory. */
+
+	nfc_util_copy_from_the_nfc(this, 0, &byte, 1);
+	result = byte;
+
+	/* Return the results. */
+
+	return result;
+
+}
+
+/**
+ * nfc_2_0_read_page() - Reads a page from the current chip into the NFC.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_0_read_page(struct imx_nfc_data *this)
+{
+	unsigned int  i;
+	void          *base = this->primary_regs;
+
+	/* Loop over the number of buffers in use. */
+
+	for (i = 0; i < this->nfc_geometry->buffer_count; i++) {
+
+		/* Make the NFC read into the current buffer. */
+
+		__raw_writew(i << NFC_2_0_BUF_ADDR_RBA_POS,
+					base + NFC_2_0_BUF_ADDR_REG_OFF);
+
+		/* Launch a page data out operation. */
+
+		__raw_writew(0x1 << NFC_2_X_CONFIG2_FDO_POS,
+					base + NFC_2_X_CONFIG2_REG_OFF);
+
+		/* Wait for the NFC to finish. */
+
+		nfc_util_wait_for_the_nfc(this, true);
+
+	}
+
+}
+
+/**
+ * nfc_2_0_send_page() - Sends a page from the NFC to the current chip.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_2_0_send_page(struct imx_nfc_data *this)
+{
+	unsigned int  i;
+	void          *base = this->primary_regs;
+
+	/* Loop over the number of buffers in use. */
+
+	for (i = 0; i < this->nfc_geometry->buffer_count; i++) {
+
+		/* Make the NFC send from the current buffer. */
+
+		__raw_writew(i << NFC_2_0_BUF_ADDR_RBA_POS,
+					base + NFC_2_0_BUF_ADDR_REG_OFF);
+
+		/* Launch a page data in operation. */
+
+		__raw_writew(0x1 << NFC_2_X_CONFIG2_FDI_POS,
+					base + NFC_2_X_CONFIG2_REG_OFF);
+
+		/* Wait for the NFC to finish. */
+
+		nfc_util_wait_for_the_nfc(this, true);
+
+	}
+
+}
+
+/**
+ * nfc_3_2_init() - Hardware initialization.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_init(struct imx_nfc_data *this)
+{
+	int           error;
+	unsigned int  no_sdma;
+	unsigned int  fmp;
+	unsigned int  rbb_mode;
+	unsigned int  num_of_devices;
+	unsigned int  dma_mode;
+	unsigned int  sbb;
+	unsigned int  nf_big;
+	unsigned int  sb2r;
+	unsigned int  fw;
+	unsigned int  too;
+	unsigned int  add_op;
+	uint32_t      config3;
+	void          *primary_base   = this->primary_regs;
+	void          *secondary_base = this->secondary_regs;
+
+	/* Initialize the interrupt machinery. */
+
+	this->nfc->mask_interrupt(this);
+	this->nfc->clear_interrupt(this);
+
+	/* Set up the clock. */
+
+	error = this->nfc->set_closest_cycle(this,
+					this->pdata->target_cycle_in_ns);
+
+	if (error)
+		return !0;
+
+	/* We never read the spare area alone. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_SP_EN_MSK,
+				primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Tell the NFC the "Read Status" command code. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG2_ST_CMD_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+	raw_set_mask_l(NAND_CMD_STATUS << NFC_3_2_CONFIG2_ST_CMD_POS,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+	/*
+	 * According to erratum ENGcm09051, the CONFIG3 register doesn't reset
+	 * correctly, so we need to re-build the entire register just in case.
+	 */
+
+	/*
+	 * Set the NO_SDMA bit to tell the NFC that we are NOT using SDMA. If
+	 * you clear this bit (to indicates you *are* using SDMA), but you
+	 * don't actually set up SDMA, the NFC has been observed to crash the
+	 * hardware when it asserts its DMA request signals. In the future, we
+	 * *may* use SDMA, but it's not worth the effort at this writing.
+	 */
+
+	no_sdma = 0x1;
+
+	/*
+	 * Set the default FIFO Mode Protection (128 bytes). FMP doesn't work if
+	 * the NO_SDMA bit is set.
+	 */
+
+	fmp = 0x2;
+
+	/*
+	 * The rbb_mode bit determines how the NFC figures out whether chips are
+	 * ready during automatic operations only (this has no effect on atomic
+	 * operations). The two choices are either to monitor the ready/busy
+	 * signals, or to read the status register. We monitor the ready/busy
+	 * signals.
+	 */
+
+	rbb_mode = 0x1;
+
+	/*
+	 * We don't yet know how many devices are connected. We'll find out in
+	 * out in nfc_3_2_set_geometry().
+	 */
+
+	num_of_devices = 0;
+
+	/* Set the default DMA mode. */
+
+	dma_mode = 0x0;
+
+	/* Set the default status busy bit. */
+
+	sbb = 0x6;
+
+	/* Little-endian (the default). */
+
+	nf_big = 0x0;
+
+	/* Set the default (standard) status bit to record. */
+
+	sb2r = 0x0;
+
+	/* We support only 8-bit Flash bus width. */
+
+	fw = 0x1;
+
+	/* We don't support "two-on-one." */
+
+	too = 0x0;
+
+	/* Set the addressing option. */
+
+	add_op = 0x3;
+
+	/* Set the CONFIG3 register. */
+
+	config3 = 0;
+
+	config3 |= no_sdma        << NFC_3_2_CONFIG3_NO_SDMA_POS;
+	config3 |= fmp            << NFC_3_2_CONFIG3_FMP_POS;
+	config3 |= rbb_mode       << NFC_3_2_CONFIG3_RBB_MODE_POS;
+	config3 |= num_of_devices << NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS;
+	config3 |= dma_mode       << NFC_3_2_CONFIG3_DMA_MODE_POS;
+	config3 |= sbb            << NFC_3_2_CONFIG3_SBB_POS;
+	config3 |= nf_big         << NFC_3_2_CONFIG3_NF_BIG_POS;
+	config3 |= sb2r           << NFC_3_2_CONFIG3_SB2R_POS;
+	config3 |= fw             << NFC_3_2_CONFIG3_FW_POS;
+	config3 |= too            << NFC_3_2_CONFIG3_TOO_POS;
+	config3 |= add_op         << NFC_3_2_CONFIG3_ADD_OP_POS;
+
+	__raw_writel(config3, secondary_base + NFC_3_2_CONFIG3_REG_OFF);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * nfc_3_2_set_geometry() - Configures for the medium geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_set_geometry(struct imx_nfc_data *this)
+{
+	unsigned int              ps;
+	unsigned int              cmd_phases;
+	unsigned int              pages_per_chip;
+	unsigned int              addr_phases0;
+	unsigned int              addr_phases1;
+	unsigned int              pages_per_block;
+	unsigned int              ecc_mode;
+	unsigned int              ppb;
+	unsigned int              spas;
+	unsigned int              mask;
+	uint32_t                  config2;
+	unsigned int              num_of_devices;
+	uint32_t                  config3;
+	unsigned int              x;
+	unsigned int              chip;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	void                      *secondary_base = this->secondary_regs;
+
+	/*
+	 * Select an NFC geometry based on the physical geometry and the
+	 * capabilities of this NFC.
+	 */
+
+	switch (physical->page_data_size) {
+
+	case 512:
+		this->nfc_geometry = &nfc_geometry_512_16_BCH_ECC4;
+		ps = 0;
+		break;
+
+	case 2048:
+		this->nfc_geometry = &nfc_geometry_2K_64_BCH_ECC4;
+		ps = 1;
+		break;
+
+	case 4096:
+
+		switch (this->physical_geometry.page_oob_size) {
+
+		case 128:
+			this->nfc_geometry = &nfc_geometry_4K_128_BCH_ECC4;
+			break;
+
+		case 218:
+			this->nfc_geometry = &nfc_geometry_4K_218_BCH_ECC8;
+			break;
+
+		default:
+			dev_err(this->dev,
+				"NFC can't handle page geometry: %u+%u",
+				physical->page_data_size,
+				physical->page_oob_size);
+			return !0;
+			break;
+
+		}
+
+		ps = 2;
+
+		break;
+
+	default:
+		dev_err(this->dev, "NFC can't handle page size: %u",
+						physical->page_data_size);
+		return !0;
+		break;
+
+	}
+
+	/* Compute the ECC mode. */
+
+	switch (this->nfc_geometry->ecc_strength) {
+
+	case 4:
+		ecc_mode = 0;
+		break;
+
+	case 8:
+		ecc_mode = 1;
+		break;
+
+	default:
+		dev_err(this->dev, "NFC can't handle ECC strength: %u",
+					this->nfc_geometry->ecc_strength);
+		return !0;
+		break;
+
+	}
+
+	/* Compute the pages per block. */
+
+	pages_per_block = physical->block_size / physical->page_data_size;
+
+	switch (pages_per_block) {
+	case 32:
+		ppb = 0;
+		break;
+	case 64:
+		ppb = 1;
+		break;
+	case 128:
+		ppb = 2;
+		break;
+	case 256:
+		ppb = 3;
+		break;
+	default:
+		dev_err(this->dev, "NFC can't handle pages per block: %d",
+							pages_per_block);
+		return !0;
+		break;
+	}
+
+	/*
+	 * The hardware needs to know the physical size of the spare area, in
+	 * units of half-words (16 bits). This may be different from the amount
+	 * of the spare area we actually expose to MTD. For example, for for
+	 * 2K+112, we only expose 64 spare bytes, but the hardware needs to know
+	 * the real facts.
+	 */
+
+	spas = this->physical_geometry.page_oob_size >> 1;
+
+	/*
+	 * The number of command phases needed to read a page is directly
+	 * dependent on whether this is a small page or large page device. Large
+	 * page devices need more address phases, terminated by a second command
+	 * phase.
+	 */
+
+	cmd_phases = is_large_page_chip(this) ? 1 : 0;
+
+	/*
+	 * The num_adr_phases1 field contains the number of phases needed to
+	 * transmit addresses for read and program operations. This is the sum
+	 * of the number of phases for a page address and the number of phases
+	 * for a column address.
+	 *
+	 * The number of phases for a page address is the number of bytes needed
+	 * to contain a page address.
+	 *
+	 * The number of phases for a column address is the number of bytes
+	 * needed to contain a column address.
+	 *
+	 * After computing the sum, we subtract three because a value of zero in
+	 * this field indicates three address phases, and this is the minimum
+	 * number of phases the hardware can comprehend.
+	 *
+	 * We compute the number of phases based on the *physical* geometry, not
+	 * the NFC geometry. For example, even if we are treating a very large
+	 * device as if it contains fewer pages than it actually does, the
+	 * hardware still needs the additional address phases.
+	 */
+
+	pages_per_chip =
+		physical->chip_size >> (fls(physical->page_data_size) - 1);
+
+	addr_phases1 = (fls(pages_per_chip) >> 3) + 1;
+
+	addr_phases1 += (fls(physical->page_data_size) >> 3) + 1;
+
+	addr_phases1 -= 3;
+
+	/*
+	 * The num_adr_phases0 field contains the number of phases needed to
+	 * transmit a page address for an erase operation. That is, this is
+	 * the value of addr_phases1, less the number of phases for the column
+	 * address.
+	 *
+	 * The hardware expresses this phase count as one or two cycles less
+	 * than the count indicated by add_phases1 (see the reference manual).
+	 */
+
+	addr_phases0 = is_large_page_chip(this) ? 1 : 0;
+
+	/* Set the CONFIG2 register. */
+
+	mask =
+		NFC_3_2_CONFIG2_PS_MSK           |
+		NFC_3_2_CONFIG2_CMD_PHASES_MSK   |
+		NFC_3_2_CONFIG2_ADDR_PHASES0_MSK |
+		NFC_3_2_CONFIG2_ECC_MODE_MSK     |
+		NFC_3_2_CONFIG2_PPB_MSK          |
+		NFC_3_2_CONFIG2_ADDR_PHASES1_MSK |
+		NFC_3_2_CONFIG2_SPAS_MSK         ;
+
+	config2 = __raw_readl(secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+	config2 &= ~mask;
+
+	config2 |= ps           << NFC_3_2_CONFIG2_PS_POS;
+	config2 |= cmd_phases   << NFC_3_2_CONFIG2_CMD_PHASES_POS;
+	config2 |= addr_phases0 << NFC_3_2_CONFIG2_ADDR_PHASES0_POS;
+	config2 |= ecc_mode     << NFC_3_2_CONFIG2_ECC_MODE_POS;
+	config2 |= ppb          << NFC_3_2_CONFIG2_PPB_POS;
+	config2 |= addr_phases1 << NFC_3_2_CONFIG2_ADDR_PHASES1_POS;
+	config2 |= spas         << NFC_3_2_CONFIG2_SPAS_POS;
+
+	config2 = __raw_writel(config2,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+	/*
+	 * Compute the num_of_devices field.
+	 *
+	 * It's very important to set this field correctly. This controls the
+	 * set of ready/busy lines to which the NFC listens with automatic
+	 * transactions. If this number is too large, the NFC will listen to
+	 * ready/busy signals that are electrically floating, or it will try to
+	 * read the status registers of chips that don't exist. Conversely, if
+	 * the number is too small, the NFC could believe an operation is
+	 * finished when some chips are still busy.
+	 */
+
+	num_of_devices = physical->chip_count - 1;
+
+	/* Set the CONFIG3 register. */
+
+	mask = NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK;
+
+	config3 = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF);
+
+	config3 &= ~mask;
+
+	config3 |= num_of_devices << NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS;
+
+	__raw_writel(config3, secondary_base + NFC_3_2_CONFIG3_REG_OFF);
+
+	/*
+	 * Check if the physical chip count is a power of 2. If not, then
+	 * automatic operations aren't available. This is because we use an
+	 * addressing option (see the ADD_OP field of CONFIG3) that requires
+	 * a number of chips that is a power of 2.
+	 */
+
+	if (ffs(physical->chip_count) != fls(physical->chip_count)) {
+		this->nfc->start_auto_read  = 0;
+		this->nfc->start_auto_write = 0;
+		this->nfc->start_auto_erase = 0;
+	}
+
+	/* Unlock the NFC RAM. */
+
+	x = __raw_readl(secondary_base + NFC_3_2_WRPROT_REG_OFF);
+	x &= ~NFC_3_2_WRPROT_BLS_MSK;
+	x |= 0x2  << NFC_3_2_WRPROT_BLS_POS;
+	__raw_writel(x, secondary_base + NFC_3_2_WRPROT_REG_OFF);
+
+	/* Loop over chip selects, setting the unlocked ranges. */
+
+	for (chip = 0; chip < this->nfc->max_chip_count; chip++) {
+
+		/* Set the unlocked range to cover the entire chip.*/
+
+		__raw_writel(0xffff0000, secondary_base +
+				NFC_3_2_UNLOCK_BLK_ADD0_REG_OFF + (chip * 4));
+
+		/* Unlock. */
+
+		x = __raw_readl(secondary_base + NFC_3_2_WRPROT_REG_OFF);
+		x &= ~(NFC_3_2_WRPROT_CS2L_MSK | NFC_3_2_WRPROT_WPC_MSK);
+		x |= chip << NFC_3_2_WRPROT_CS2L_POS;
+		x |= 0x4  << NFC_3_2_WRPROT_WPC_POS ;
+		__raw_writel(x, secondary_base + NFC_3_2_WRPROT_REG_OFF);
+
+	}
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * nfc_3_2_exit() - Hardware cleanup.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_exit(struct imx_nfc_data *this)
+{
+}
+
+/**
+ * nfc_3_2_set_closest_cycle() - Version-specific hardware cleanup.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_set_closest_cycle(struct imx_nfc_data *this, unsigned ns)
+{
+	struct clk     *parent_clock;
+	unsigned long  parent_clock_rate_in_hz;
+	unsigned long  sym_low_clock_rate_in_hz;
+	unsigned long  asym_low_clock_rate_in_hz;
+	unsigned int   sym_high_cycle_in_ns;
+	unsigned int   asym_high_cycle_in_ns;
+
+	/*
+	 * According to ENGcm09121:
+	 *
+	 *  - If the NFC is set to SYMMETRIC mode, the NFC clock divider must
+	 *    divide the EMI Slow Clock by NO MORE THAN 4.
+	 *
+	 *  - If the NFC is set for ASYMMETRIC mode, the NFC clock divider must
+	 *    divide the EMI Slow Clock by NO MORE THAN 3.
+	 *
+	 * We need to compute the corresponding cycle time constraints. Start
+	 * by getting information about the parent clock.
+	 */
+
+	parent_clock            = clk_get_parent(this->clock);
+	parent_clock_rate_in_hz = clk_get_rate(parent_clock);
+
+	/* Compute the limit frequencies. */
+
+	sym_low_clock_rate_in_hz  = parent_clock_rate_in_hz / 4;
+	asym_low_clock_rate_in_hz = parent_clock_rate_in_hz / 3;
+
+	/* Compute the corresponding limit cycle periods. */
+
+	sym_high_cycle_in_ns  = 1000000000 / sym_low_clock_rate_in_hz;
+	asym_high_cycle_in_ns = (1000000000 / asym_low_clock_rate_in_hz) * 2;
+
+	/* Attempt to implement the given cycle. */
+
+	return nfc_util_set_best_cycle(this, ns,
+			ns > asym_high_cycle_in_ns, ns > sym_high_cycle_in_ns);
+
+}
+
+/**
+ * nfc_3_2_mask_interrupt() - Masks interrupts.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_mask_interrupt(struct imx_nfc_data *this)
+{
+	void  *secondary_base = this->secondary_regs;
+	raw_set_mask_l(NFC_3_2_CONFIG2_INT_MSK_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+}
+
+/**
+ * nfc_3_2_unmask_interrupt() - Unmasks interrupts.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_unmask_interrupt(struct imx_nfc_data *this)
+{
+	void  *secondary_base = this->secondary_regs;
+	raw_clr_mask_l(NFC_3_2_CONFIG2_INT_MSK_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+}
+
+/**
+ * nfc_3_2_clear_interrupt() - Clears an interrupt.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_clear_interrupt(struct imx_nfc_data *this)
+{
+	int   done;
+	void  *secondary_base = this->secondary_regs;
+
+	/* Request IP bus interface access. */
+
+	raw_set_mask_l(NFC_3_2_IPC_CREQ_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+	/* Wait for access. */
+
+	do
+		done = !!raw_read_mask_l(NFC_3_2_IPC_CACK_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+	while (!done);
+
+	/* Clear the interrupt. */
+
+	raw_clr_mask_l(NFC_3_2_IPC_INT_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+	/* Release the IP bus interface. */
+
+	raw_clr_mask_l(NFC_3_2_IPC_CREQ_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_is_interrupting() - Returns the interrupt bit status.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_is_interrupting(struct imx_nfc_data *this)
+{
+	void  *secondary_base = this->secondary_regs;
+	return !!raw_read_mask_l(NFC_3_2_IPC_INT_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+}
+
+/**
+ * nfc_3_2_is_ready() - Returns the ready/busy status.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_is_ready(struct imx_nfc_data *this)
+{
+	void  *secondary_base = this->secondary_regs;
+	return !!raw_read_mask_l(NFC_3_2_IPC_RB_B_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+}
+
+/**
+ * nfc_3_2_set_force_ce() - Can force CE to be asserted always.
+ *
+ * @this:  Per-device data.
+ * @on:    Indicates if the hardware CE signal should be asserted always.
+ */
+static void nfc_3_2_set_force_ce(struct imx_nfc_data *this, int on)
+{
+	void  *primary_base = this->primary_regs;
+
+	if (on)
+		raw_set_mask_l(NFC_3_2_CONFIG1_NF_CE_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+	else
+		raw_clr_mask_l(NFC_3_2_CONFIG1_NF_CE_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_set_ecc() - Turns ECC on or off.
+ *
+ * @this:  Per-device data.
+ * @on:    Indicates if ECC should be on or off.
+ */
+static void nfc_3_2_set_ecc(struct imx_nfc_data *this, int on)
+{
+	void  *secondary_base = this->secondary_regs;
+
+	if (on)
+		raw_set_mask_l(NFC_3_2_CONFIG2_ECC_EN_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+	else
+		raw_clr_mask_l(NFC_3_2_CONFIG2_ECC_EN_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_get_ecc_status() - Reports ECC errors.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_get_ecc_status(struct imx_nfc_data *this)
+{
+	unsigned int  i;
+	void          *base = this->primary_regs;
+	uint16_t      status_reg;
+	unsigned int  buffer_status[8];
+	int           status;
+
+	/* Get the entire status register. */
+
+	status_reg = __raw_readw(base + NFC_3_2_ECC_STATUS_REG_OFF);
+
+	/* Pick out the status for each buffer. */
+
+	buffer_status[0] = (status_reg & NFC_3_2_ECC_STATUS_NOBER1_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER1_POS;
+
+	buffer_status[1] = (status_reg & NFC_3_2_ECC_STATUS_NOBER2_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER2_POS;
+
+	buffer_status[2] = (status_reg & NFC_3_2_ECC_STATUS_NOBER3_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER3_POS;
+
+	buffer_status[3] = (status_reg & NFC_3_2_ECC_STATUS_NOBER4_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER4_POS;
+
+	buffer_status[4] = (status_reg & NFC_3_2_ECC_STATUS_NOBER5_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER5_POS;
+
+	buffer_status[5] = (status_reg & NFC_3_2_ECC_STATUS_NOBER6_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER6_POS;
+
+	buffer_status[6] = (status_reg & NFC_3_2_ECC_STATUS_NOBER7_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER7_POS;
+
+	buffer_status[7] = (status_reg & NFC_3_2_ECC_STATUS_NOBER8_MSK)
+					>> NFC_3_2_ECC_STATUS_NOBER8_POS;
+
+	/* Loop through the buffers we're actually using. */
+
+	status = 0;
+
+	for (i = 0; i < this->nfc_geometry->buffer_count; i++) {
+
+		if (buffer_status[i] > this->nfc_geometry->ecc_strength) {
+			status = -1;
+			break;
+		}
+
+		status += buffer_status[i];
+
+	}
+
+	/* Return the final result. */
+
+	return status;
+
+}
+
+/**
+ * nfc_3_2_get_symmetric() - Indicates if the clock is symmetric.
+ *
+ * @this:  Per-device data.
+ */
+static int nfc_3_2_get_symmetric(struct imx_nfc_data *this)
+{
+	void  *secondary_base = this->secondary_regs;
+
+	return !!raw_read_mask_w(NFC_3_2_CONFIG2_SYM_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_set_symmetric() - Turns symmetric clock mode on or off.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_set_symmetric(struct imx_nfc_data *this, int on)
+{
+	void  *secondary_base = this->secondary_regs;
+
+	if (on)
+		raw_set_mask_l(NFC_3_2_CONFIG2_SYM_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+	else
+		raw_clr_mask_l(NFC_3_2_CONFIG2_SYM_MSK,
+				secondary_base + NFC_3_2_CONFIG2_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_select_chip() - Selects the current chip.
+ *
+ * @this:  Per-device data.
+ * @chip:  The chip number to select, or -1 to select no chip.
+ */
+static void nfc_3_2_select_chip(struct imx_nfc_data *this, int chip)
+{
+	unsigned long  x;
+	void           *primary_base = this->primary_regs;
+
+	if (chip < 0)
+		return;
+
+	x = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	x &= ~NFC_3_2_CONFIG1_CS_MSK;
+
+	x |= (chip << NFC_3_2_CONFIG1_CS_POS) & NFC_3_2_CONFIG1_CS_MSK;
+
+	__raw_writel(x, primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_command_cycle() - Sends a command.
+ *
+ * @this:     Per-device data.
+ * @command:  The command code.
+ */
+static void nfc_3_2_command_cycle(struct imx_nfc_data *this, unsigned command)
+{
+	void  *primary_base = this->primary_regs;
+
+	/* Write the command we want to send. */
+
+	__raw_writel(command, primary_base + NFC_3_2_CMD_REG_OFF);
+
+	/* Launch a command cycle. */
+
+	__raw_writel(NFC_3_2_LAUNCH_FCMD_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_write_cycle() - writes a single byte.
+ *
+ * @this:  Per-device data.
+ * @byte:  The byte.
+ */
+static void nfc_3_2_write_cycle(struct imx_nfc_data *this, unsigned int byte)
+{
+	void  *primary_base = this->primary_regs;
+
+	/* Give the NFC the byte we want to write. */
+
+	__raw_writel(byte, primary_base + NFC_3_2_ADD0_REG_OFF);
+
+	/* Launch an address cycle.
+	 *
+	 * This is *sort* of a hack, but not really. The intent of the NFC
+	 * design is for this operation to send an address byte. In fact, the
+	 * NFC neither knows nor cares what we're sending. It justs runs a write
+	 * cycle.
+	 */
+
+	__raw_writel(NFC_3_2_LAUNCH_FADD_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, false);
+
+}
+
+/**
+ * nfc_3_2_read_cycle() - Applies a single read cycle to the current chip.
+ *
+ * @this:  Per-device data.
+ */
+static unsigned int nfc_3_2_read_cycle(struct imx_nfc_data *this)
+{
+	unsigned int  result;
+	void          *primary_base = this->primary_regs;
+
+	/* Launch a "Data Out" operation. */
+
+	__raw_writel(0x4 << NFC_3_2_LAUNCH_FDO_POS,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, false);
+
+	/* Get the result. */
+
+	result = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF)
+						>> NFC_3_2_CONFIG1_STATUS_POS;
+	result &= 0xff;
+
+	/* Return the result. */
+
+	return result;
+
+}
+
+/**
+ * nfc_3_2_read_page() - Reads a page into the NFC memory.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_read_page(struct imx_nfc_data *this)
+{
+	void  *primary_base = this->primary_regs;
+
+	/* Start reading into buffer 0. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Launch a page data out operation. */
+
+	__raw_writel(0x1 << NFC_3_2_LAUNCH_FDO_POS,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, true);
+
+}
+
+/**
+ * nfc_3_2_send_page() - Sends a page from the NFC to the current chip.
+ *
+ * @this:  Per-device data.
+ */
+static void nfc_3_2_send_page(struct imx_nfc_data *this)
+{
+	void  *primary_base = this->primary_regs;
+
+	/* Start sending from buffer 0. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Launch a page data in operation. */
+
+	__raw_writel(NFC_3_2_LAUNCH_FDI_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, true);
+
+}
+
+/**
+ * nfc_3_2_add_state_events() - Adds events to display important state.
+ *
+ * @this:   Per-device data.
+ */
+static void nfc_3_2_add_state_events(struct imx_nfc_data *this)
+{
+#ifdef EVENT_REPORTING
+	void  *secondary_base = this->secondary_regs;
+
+	add_state_event_l
+		(
+		secondary_base + NFC_3_2_IPC_REG_OFF,
+		NFC_3_2_IPC_INT_MSK,
+		"  Interrupt     : 0",
+		"  Interrupt     : X"
+		);
+
+	add_state_event_l
+		(
+		secondary_base + NFC_3_2_IPC_REG_OFF,
+		NFC_3_2_IPC_AUTO_PROG_DONE_MSK,
+		"  auto_prog_done: 0",
+		"  auto_prog_done: X"
+		);
+
+	add_state_event_l
+		(
+		secondary_base + NFC_3_2_IPC_REG_OFF,
+		NFC_3_2_IPC_RB_B_MSK,
+		"  Medium        : Busy",
+		"  Medium        : Ready"
+		);
+#endif
+}
+
+/**
+ * nfc_3_2_get_auto_loop_params() - Gets automatic operation loop parameters.
+ *
+ * This function and the corresponding "setter" enable the automatic operations
+ * to keep some state as they iterate over chips.
+ *
+ * The most "obvious" way to save state would be to allocate a private data
+ * structure and hang it off the owning struct nfc_hal. On the other hand,
+ * writing the code to allocate the memory and then release it when the NFC
+ * shuts down is annoying - and we have some perfectly good memory in the NFC
+ * hardware that we can use. Since we only use two commands at a time, we can
+ * stash our loop limits and loop index in the top 16 bits of the NAND_CMD
+ * register. To paraphrase the reference manual:
+ *
+ *
+ * NAND_CMD
+ *
+ * |<--  4 bits  -->|<--  4 bits -->|<--          8 bits          -->|
+ * +----------------+---------------+--------------------------------+
+ * |     First      |     Last      |           Loop Index           |
+ * +----------------+---------------+--------------------------------+
+ * |         NAND COMMAND1          |         NAND COMMAND0          |
+ * +--------------------------------+--------------------------------+
+ * |<--         16 bits          -->|<--         16 bits          -->|
+ *
+ *
+ * @this:   Per-device data.
+ * @first:  A pointer to a variable that will receive the first chip number.
+ * @last:   A pointer to a variable that will receive the last chip number.
+ * @index:  A pointer to a variable that will receive the current chip number.
+ */
+static void nfc_3_2_get_auto_loop_params(struct imx_nfc_data *this,
+			unsigned *first, unsigned *last, unsigned *index)
+{
+	uint32_t  x;
+	void      *primary_base = this->primary_regs;
+
+	x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF);
+
+	*first = (x >> 28) & 0x0f;
+	*last  = (x >> 24) & 0x0f;
+	*index = (x >> 16) & 0xff;
+
+}
+
+/**
+ * nfc_3_2_set_auto_loop_params() - Sets automatic operation loop parameters.
+ *
+ * See nfc_3_2_get_auto_loop_params() for detailed information about these
+ * functions.
+ *
+ * @this:   Per-device data.
+ * @first:  The first chip number.
+ * @last:   The last chip number.
+ * @index:  The current chip number.
+ */
+static void nfc_3_2_set_auto_loop_params(struct imx_nfc_data *this,
+				unsigned first, unsigned last, unsigned index)
+{
+	uint32_t  x;
+	void      *primary_base = this->primary_regs;
+
+	x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF);
+
+	x &= 0x0000ffff;
+	x |= (first & 0x0f) << 28;
+	x |= (last  & 0x0f) << 24;
+	x |= (index & 0xff) << 16;
+
+	__raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF);
+
+}
+
+/**
+ * nfc_3_2_get_auto_addresses() - Gets automatic operation addresses.
+ *
+ * @this:    Per-device data.
+ * @group:   The address group number.
+ * @chip:    A pointer to a variable that will receive the chip number.
+ * @column:  A pointer to a variable that will receive the column address.
+ *           A NULL pointer indicates there is no column address.
+ * @page:    A pointer to a variable that will receive the page address.
+ */
+static void nfc_3_2_get_auto_addresses(struct imx_nfc_data *this,
+	unsigned group, unsigned *chip, unsigned *column, unsigned *page)
+{
+	uint32_t                  x;
+	unsigned int              chip_count;
+	unsigned int              cs_width;
+	unsigned int              cs_mask;
+	unsigned int              page_lsbs;
+	unsigned int              page_msbs;
+	uint32_t                  *low;
+	uint16_t                  *high;
+	void                      *primary_base   = this->primary_regs;
+	void                      *secondary_base = this->secondary_regs;
+
+	/*
+	 * The width of the chip select field depends on the number of connected
+	 * chips.
+	 *
+	 * Notice that these computations work only if the number of chips is a
+	 * power of 2. In fact, that is a fundamental limitation for using
+	 * automatic operations.
+	 */
+
+	x = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF);
+
+	chip_count =
+		(x & NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK) >>
+					NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS;
+	chip_count++;
+
+	cs_width = ffs(chip_count) - 1;
+	cs_mask  = chip_count - 1;
+
+	/* Construct pointers to the pieces of the given address group. */
+
+	low = primary_base + NFC_3_2_ADD0_REG_OFF;
+	low += group;
+
+	high = primary_base + NFC_3_2_ADD8_REG_OFF;
+	high += group;
+
+	/* Check if there's a column address. */
+
+	if (column) {
+
+		/*
+		 * The low 32 bits of the address group look like this:
+		 *
+		 *      16 - n     n
+		 * | <-  bits  ->|<->|<-  16 bits   ->|
+		 * +-------------+---+----------------+
+		 * |  Page LSBs  |CS |     Column     |
+		 * +-------------+---+----------------+
+		 */
+
+		x = __raw_readl(low);
+
+		*column   = x & 0xffff;
+		*chip     = (x >> 16) & cs_mask;
+		page_lsbs = x >> (16 + cs_width);
+
+		/* The high 16 bits contain the MSB's of the page address. */
+
+		page_msbs = __raw_readw(high);
+
+		*page = (page_msbs << (16 - cs_width)) | page_lsbs;
+
+	} else {
+
+		/*
+		 * The low 32 bits of the address group look like this:
+		 *
+		 *                                 n
+		 * | <-     (32 - n) bits      ->|<->|
+		 * +-----------------------------+---+
+		 * |          Page LSBs          |CS |
+		 * +-----------------------------+---+
+		 */
+
+		x = __raw_readl(low);
+
+		*chip     = x &  cs_mask;
+		page_lsbs = x >> cs_width;
+
+		/* The high 16 bits contain the MSB's of the page address. */
+
+		page_msbs = __raw_readw(high);
+
+		*page = (page_msbs << (32 - cs_width)) | page_lsbs;
+
+	}
+
+}
+
+/**
+ * nfc_3_2_set_auto_addresses() - Sets automatic operation addresses.
+ *
+ * @this:    Per-device data.
+ * @group:   The address group number.
+ * @chip:    The chip number.
+ * @column:  The column address. The sentinel value ~0 indicates that there is
+ *           no column address.
+ * @page:    The page address.
+ */
+static void nfc_3_2_set_auto_addresses(struct imx_nfc_data *this,
+		unsigned group, unsigned chip, unsigned column, unsigned page)
+{
+	uint32_t                  x;
+	unsigned                  chip_count;
+	unsigned int              cs_width;
+	unsigned int              cs_mask;
+	uint32_t                  *low;
+	uint16_t                  *high;
+	void                      *primary_base = this->primary_regs;
+	void                      *secondary_base = this->secondary_regs;
+
+	/*
+	 * The width of the chip select field depends on the number of connected
+	 * chips.
+	 *
+	 * Notice that these computations work only if the number of chips is a
+	 * power of 2. In fact, that is a fundamental limitation for using
+	 * automatic operations.
+	 */
+
+	x = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF);
+
+	chip_count =
+		(x & NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK) >>
+					NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS;
+	chip_count++;
+
+	cs_width = ffs(chip_count) - 1;
+	cs_mask  = chip_count - 1;
+
+	/* Construct pointers to the pieces of the given address group. */
+
+	low = primary_base + NFC_3_2_ADD0_REG_OFF;
+	low += group;
+
+	high = primary_base + NFC_3_2_ADD8_REG_OFF;
+	high += group;
+
+	/* Check if we have a column address. */
+
+	if (column != ~0) {
+
+		/*
+		 * The low 32 bits of the address group look like this:
+		 *
+		 *      16 - n     n
+		 * | <-  bits  ->|<->|<-  16 bits   ->|
+		 * +-------------+---+----------------+
+		 * |  Page LSBs  |CS |     Column     |
+		 * +-------------+---+----------------+
+		 */
+
+		x  = 0;
+		x |= column & 0xffff;
+		x |= (chip & cs_mask) << 16;
+		x |= page << (16 + cs_width);
+
+		__raw_writel(x, low);
+
+		/* The high 16 bits contain the MSB's of the page address. */
+
+		x = (page >> (16 - cs_width)) & 0xffff;
+
+		__raw_writew(x, high);
+
+	} else {
+
+		/*
+		 * The low 32 bits of the address group look like this:
+		 *
+		 *                                 n
+		 * | <-     (32 - n) bits      ->|<->|
+		 * +-----------------------------+---+
+		 * |          Page LSBs          |CS |
+		 * +-----------------------------+---+
+		 */
+
+		x  = 0;
+		x |= chip & cs_mask;
+		x |= page << cs_width;
+
+		__raw_writel(x, low);
+
+		/* The high 16 bits contain the MSB's of the page address. */
+
+		x = (page >> (32 - cs_width)) & 0xffff;
+
+		__raw_writew(x, high);
+
+	}
+
+}
+
+/**
+ * nfc_3_2_start_auto_read() - Starts an automatic read.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ * @start:  The first physical chip number on which to operate.
+ * @count:  The number of physical chips on which to operate.
+ * @column: The column address.
+ * @page:   The page address.
+ */
+static int nfc_3_2_start_auto_read(struct imx_nfc_data *this,
+		unsigned start, unsigned count, unsigned column, unsigned page)
+{
+	uint32_t  x;
+	int       return_value = 0;
+	void      *primary_base = this->primary_regs;
+
+	add_event("Entering nfc_3_2_start_auto_read", 1);
+
+	/* Check for nonsense. */
+
+	if ((start > 7) || (!count) || (count > 8)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Set state. */
+
+	nfc_3_2_set_auto_loop_params(this, start, start + count - 1, start);
+	nfc_3_2_set_auto_addresses(this, 0, start, column, page);
+
+	/* Set up for ONE iteration at a time. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_ITER_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Reset to buffer 0. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/*
+	 * Set up the commands. Note that the number of command phases was
+	 * configured in the set_geometry() function so, even though we're
+	 * giving both commands here, they won't necessarily both be used.
+	 */
+
+	x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF);
+
+	x &= 0xffff0000;
+	x |= NAND_CMD_READ0     << 0;
+	x |= NAND_CMD_READSTART << 8;
+
+	__raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF);
+
+	/* Launch the operation. */
+
+	add_event("Launching", 0);
+
+	__raw_writel(NFC_3_2_LAUNCH_AUTO_READ_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_start_auto_read", -1);
+
+	return return_value;
+
+}
+
+/**
+ * nfc_3_2_wait_for_auto_read() - Waits until auto read is ready for the CPU.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ */
+static int nfc_3_2_wait_for_auto_read(struct imx_nfc_data *this)
+{
+	unsigned int  first;
+	unsigned int  last;
+	unsigned int  index;
+	int           return_value = 0;
+
+	add_event("Entering nfc_3_2_wait_for_auto_read", 1);
+
+	/* Get state. */
+
+	nfc_3_2_get_auto_loop_params(this, &first, &last, &index);
+
+	/* This function should be called for every chip. */
+
+	if ((index < first) || (index > last)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Wait for the NFC to completely finish and interrupt. */
+
+	nfc_util_wait_for_the_nfc(this, true);
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_wait_for_auto_read", -1);
+
+	return return_value;
+
+}
+
+/**
+ * nfc_3_2_resume_auto_read() - Resumes auto read after CPU intervention.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ */
+static int nfc_3_2_resume_auto_read(struct imx_nfc_data *this)
+{
+	unsigned int  first;
+	unsigned int  last;
+	unsigned int  index;
+	unsigned int  chip;
+	unsigned int  column;
+	unsigned int  page;
+	int           return_value = 0;
+	void          *primary_base = this->primary_regs;
+
+	add_event("Entering nfc_3_2_resume_auto_read", 1);
+
+	/* Get state. */
+
+	nfc_3_2_get_auto_loop_params(this, &first, &last, &index);
+	nfc_3_2_get_auto_addresses(this, 0, &chip, &column, &page);
+
+	/* This function should be called for every chip, except the last. */
+
+	if ((index < first) || (index >= last)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Move to the next chip. */
+
+	index++;
+
+	/* Update state. */
+
+	nfc_3_2_set_auto_loop_params(this, first, last, index);
+	nfc_3_2_set_auto_addresses(this, 0, index, column, page);
+
+	/* Reset to buffer 0. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Launch the operation. */
+
+	add_event("Launching", 0);
+
+	__raw_writel(NFC_3_2_LAUNCH_AUTO_READ_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_resume_auto_read", -1);
+
+	return return_value;
+
+}
+
+/**
+ * nfc_3_2_start_auto_write() - Starts an automatic write.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ * @start:  The first physical chip number on which to operate.
+ * @count:  The number of physical chips on which to operate.
+ * @column: The column address.
+ * @page:   The page address.
+ */
+static int nfc_3_2_start_auto_write(struct imx_nfc_data *this,
+		unsigned start, unsigned count, unsigned column, unsigned page)
+{
+	uint32_t  x;
+	int       return_value = 0;
+	void      *primary_base   = this->primary_regs;
+	void      *secondary_base = this->secondary_regs;
+
+	add_event("Entering nfc_3_2_start_auto_write", 1);
+
+	/* Check for nonsense. */
+
+	if ((start > 7) || (!count) || (count > 8)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Set state. */
+
+	nfc_3_2_set_auto_loop_params(this, start, start + count - 1, start);
+	nfc_3_2_set_auto_addresses(this, 0, start, column, page);
+
+	/* Set up for ONE iteration at a time. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_ITER_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Set up the commands. */
+
+	x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF);
+
+	x &= 0xffff0000;
+	x |= NAND_CMD_SEQIN    << 0;
+	x |= NAND_CMD_PAGEPROG << 8;
+
+	__raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF);
+
+	/* Clear the auto_prog_done bit. */
+
+	raw_clr_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_start_auto_write", -1);
+
+	return return_value;
+
+}
+
+/**
+ * nfc_3_2_wait_for_auto_write() - Waits for auto write to be writey for the CPU.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ */
+static int nfc_3_2_wait_for_auto_write(struct imx_nfc_data *this)
+{
+	unsigned int  first;
+	unsigned int  last;
+	unsigned int  index;
+	unsigned int  chip;
+	unsigned int  column;
+	unsigned int  page;
+	uint32_t      x;
+	int           interrupt;
+	int           transmitted;
+	int           ready;
+	int           return_value = 0;
+	void          *primary_base   = this->primary_regs;
+	void          *secondary_base = this->secondary_regs;
+
+	add_event("Entering nfc_3_2_wait_for_auto_write", 1);
+
+	/* Get state. */
+
+	nfc_3_2_get_auto_loop_params(this, &first, &last, &index);
+	nfc_3_2_get_auto_addresses(this, 0, &chip, &column, &page);
+
+	/* This function should be called for every chip. */
+
+	if ((index < first) || (index > last)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Reset to buffer 0. */
+
+	raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK,
+					primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Launch the operation. */
+
+	nfc_3_2_add_state_events(this);
+
+	add_event("Launching", 0);
+
+	__raw_writel(NFC_3_2_LAUNCH_AUTO_PROG_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+	nfc_3_2_add_state_events(this);
+
+	/* Wait for the NFC to transmit the page. */
+
+	add_event("Spinning while the NFC transmits the page...", 0);
+
+	do
+		transmitted = !!raw_read_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+	while (!transmitted);
+
+	/*
+	 * When control arrives here, the auto_prog_done bit is set. This
+	 * indicates the NFC has finished transmitting the current page. The CPU
+	 * is now free to write the next page into the NFC's memory. The Flash
+	 * hardware is still busy programming the page into its storage array.
+	 *
+	 * Clear the auto_prog_done bit. This is analogous to acknowledging an
+	 * interrupt.
+	 */
+
+	nfc_3_2_add_state_events(this);
+
+	add_event("Acknowledging the page...", 0);
+
+	raw_clr_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+	nfc_3_2_add_state_events(this);
+
+	/*
+	 * If this is *not* the last iteration, move to the next chip and return
+	 * to the caller so he can put the next page in the NFC buffer.
+	 */
+
+	if (index < last) {
+
+		add_event("Moving to the next chip...", 0);
+
+		index++;
+
+		nfc_3_2_set_auto_loop_params(this, first, last, index);
+		nfc_3_2_set_auto_addresses(this, 0, index, column, page);
+
+		goto exit;
+
+	}
+
+	/*
+	 * If control arrives here, this is the last iteration, so it's time to
+	 * close out the entire operation. We need to wait for the medium to be
+	 * ready and then acknowledge the final interrupt.
+	 *
+	 * Because of the way the NFC hardware works, the code here requires a
+	 * bit of explanation. The most important rule is:
+	 *
+	 *         During automatic operations, the NFC sets its
+	 *         interrupt bit *whenever* it sees the ready/busy
+	 *         signal transition from "Busy" to "Ready".
+	 *
+	 * Recall that the ready/busy signals from all the chips in the medium
+	 * are "wire-anded." Thus, the NFC will only see that the medium is
+	 * ready if *all* chips are ready.
+	 *
+	 * Because of variability in NAND Flash timing, the medium *may* have
+	 * become ready during previous iterations, which means the interrupt
+	 * bit *may* be set at this moment. This is a "left-over" interrupt, and
+	 * can complicate our logic.
+	 *
+	 * The two bits of state that interest us here are the interrupt bit
+	 * and the ready/busy bit. It boils down to the following truth table:
+	 *
+	 * | Interrupt  | Ready/Busy | Description
+	 * +------------+------------+---------------
+	 * |            |            | Busy medium and no left-over interrupt.
+	 * |     0      |     0      | The final interrupt will arrive in the
+	 * |            |            | future.
+	 * +------------+------------+---------------
+	 * |            |            | Ready medium and no left-over interrupt.
+	 * |     0      |     1      | There will be no final interrupt. This
+	 * |            |            | case should be impossible.
+	 * +------------+------------+---------------
+	 * |            |            | Busy medium and left-over interrupt.
+	 * |     1      |     0      | The final interrupt will arrive in the
+	 * |            |            | future. This is the hard case.
+	 * +------------+------------+---------------
+	 * |            |            | Ready medium and left-over interrupt.
+	 * |     1      |     1      | The final interrupt has already
+	 * |            |            | arrived. Acknowledge it and exit.
+	 * +------------+------------+---------------
+	 *
+	 * Case #3 is a small problem. If we clear the interrupt, we may or may
+	 * not have another interrupt following.
+	 */
+
+	/* Sample the IPC register. */
+
+	x = __raw_readl(secondary_base + NFC_3_2_IPC_REG_OFF);
+
+	interrupt = !!(x & NFC_3_2_IPC_INT_MSK);
+	ready     = !!(x & NFC_3_2_IPC_RB_B_MSK);
+
+	/* Check for the easy cases. */
+
+	if (!interrupt && !ready) {
+		add_event("Waiting for the final interrupt..." , 0);
+		nfc_util_wait_for_the_nfc(this, true);
+		goto exit;
+	} else if (!interrupt && ready) {
+		add_event("Done." , 0);
+		goto exit;
+	} else if (interrupt && ready) {
+		add_event("Acknowledging the final interrupt..." , 0);
+		nfc_util_wait_for_the_nfc(this, false);
+		goto exit;
+
+	}
+
+	/*
+	 * If control arrives here, we hit case #3. Begin by acknowledging the
+	 * interrupt we have right now.
+	 */
+
+	add_event("Clearing the left-over interrupt..." , 0);
+	nfc_util_wait_for_the_nfc(this, false);
+
+	/*
+	 * Check the ready/busy bit again. If the medium is still busy, then
+	 * we're going to get one more interrupt.
+	 */
+
+	ready = !!raw_read_mask_l(NFC_3_2_IPC_RB_B_MSK,
+					secondary_base + NFC_3_2_IPC_REG_OFF);
+
+	if (!ready) {
+		add_event("Waiting for the final interrupt..." , 0);
+		nfc_util_wait_for_the_nfc(this, true);
+	}
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_wait_for_auto_write", -1);
+
+	return return_value;
+
+}
+
+/**
+ * nfc_3_2_start_auto_erase() - Starts an automatic erase.
+ *
+ * This function returns 0 if everything went well.
+ *
+ * @this:   Per-device data.
+ * @start:  The first physical chip number on which to operate.
+ * @count:  The number of physical chips on which to operate.
+ * @page:   The page address.
+ */
+static int nfc_3_2_start_auto_erase(struct imx_nfc_data *this,
+				unsigned start, unsigned count, unsigned page)
+{
+	uint32_t  x;
+	unsigned  i;
+	int       return_value = 0;
+	void      *primary_base = this->primary_regs;
+
+	add_event("Entering nfc_3_2_start_auto_erase", 1);
+
+	/* Check for nonsense. */
+
+	if ((start > 7) || (!count) || (count > 8)) {
+		return_value = !0;
+		goto exit;
+	}
+
+	/* Set up the commands. */
+
+	x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF);
+
+	x &= 0xffff0000;
+	x |= NAND_CMD_ERASE1 << 0;
+	x |= NAND_CMD_ERASE2 << 8;
+
+	__raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF);
+
+	/* Set the iterations. */
+
+	x = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	x &= ~NFC_3_2_CONFIG1_ITER_MSK;
+	x |= ((count - 1) << NFC_3_2_CONFIG1_ITER_POS) &
+						NFC_3_2_CONFIG1_ITER_MSK;
+
+	__raw_writel(x, primary_base + NFC_3_2_CONFIG1_REG_OFF);
+
+	/* Loop over chips, setting up the address groups. */
+
+	for (i = 0; i < count; i++)
+		nfc_3_2_set_auto_addresses(this, i, start + i, ~0, page);
+
+	/* Launch the operation. */
+
+	add_event("Launching", 0);
+
+	__raw_writel(NFC_3_2_LAUNCH_AUTO_ERASE_MSK,
+					primary_base + NFC_3_2_LAUNCH_REG_OFF);
+
+exit:	/* Return. */
+
+	add_event("Exiting nfc_3_2_start_auto_erase", -1);
+
+	return return_value;
+
+}
+
+/*
+ * At this point, we've defined all the version-specific primitives. We're now
+ * ready to construct the NFC HAL structures for every version.
+ */
+
+struct nfc_hal nfc_1_0_hal = {
+		.major_version       = 1,
+		.minor_version       = 0,
+		.max_chip_count      = 1,
+		.max_buffer_count    = 4,
+		.spare_buf_stride    = 16,
+		.has_secondary_regs  = 0,
+		.can_be_symmetric    = 0,
+	};
+
+struct nfc_hal nfc_2_0_hal = {
+		.major_version       = 2,
+		.minor_version       = 0,
+		.max_chip_count      = 1,
+		.max_buffer_count    = 4,
+		.spare_buf_stride    = 16,
+		.has_secondary_regs  = false,
+		.can_be_symmetric    = true,
+		.init                = nfc_2_0_init,
+		.set_geometry        = nfc_2_0_set_geometry,
+		.exit                = nfc_2_x_exit,
+		.mask_interrupt      = nfc_2_0_mask_interrupt,
+		.unmask_interrupt    = nfc_2_0_unmask_interrupt,
+		.clear_interrupt     = nfc_2_x_clear_interrupt,
+		.is_interrupting     = nfc_2_x_is_interrupting,
+		.is_ready            = 0, /* Ready/Busy not exposed. */
+		.set_ecc             = nfc_2_0_set_ecc,
+		.get_ecc_status      = nfc_2_0_get_ecc_status,
+		.get_symmetric       = nfc_2_0_get_symmetric,
+		.set_symmetric       = nfc_2_0_set_symmetric,
+		.select_chip         = nfc_2_0_select_chip,
+		.command_cycle       = nfc_2_x_command_cycle,
+		.write_cycle         = nfc_2_x_write_cycle,
+		.read_cycle          = nfc_2_0_read_cycle,
+		.read_page           = nfc_2_0_read_page,
+		.send_page           = nfc_2_0_send_page,
+		.start_auto_read     = 0, /* Not supported. */
+		.wait_for_auto_read  = 0, /* Not supported. */
+		.resume_auto_read    = 0, /* Not supported. */
+		.start_auto_write    = 0, /* Not supported. */
+		.wait_for_auto_write = 0, /* Not supported. */
+		.start_auto_erase    = 0, /* Not supported. */
+	};
+
+struct nfc_hal nfc_2_1_hal = {
+		.major_version       = 2,
+		.minor_version       = 1,
+		.max_chip_count      = 4,
+		.max_buffer_count    = 8,
+		.spare_buf_stride    = 64,
+		.has_secondary_regs  = 0,
+		.can_be_symmetric    = !0,
+	};
+
+struct nfc_hal nfc_3_1_hal = {
+		.major_version       = 3,
+		.minor_version       = 1,
+		.max_chip_count      = 4,
+		.max_buffer_count    = 8,
+		.spare_buf_stride    = 64,
+		.has_secondary_regs  = !0,
+		.can_be_symmetric    = !0,
+	};
+
+struct nfc_hal nfc_3_2_hal = {
+		.major_version       = 3,
+		.minor_version       = 2,
+		.max_chip_count      = 8,
+		.max_buffer_count    = 8,
+		.spare_buf_stride    = 64,
+		.has_secondary_regs  = true,
+		.can_be_symmetric    = true,
+		.init                = nfc_3_2_init,
+		.set_geometry        = nfc_3_2_set_geometry,
+		.exit                = nfc_3_2_exit,
+		.set_closest_cycle   = nfc_3_2_set_closest_cycle,
+		.mask_interrupt      = nfc_3_2_mask_interrupt,
+		.unmask_interrupt    = nfc_3_2_unmask_interrupt,
+		.clear_interrupt     = nfc_3_2_clear_interrupt,
+		.is_interrupting     = nfc_3_2_is_interrupting,
+		.is_ready            = nfc_3_2_is_ready,
+		.set_force_ce        = nfc_3_2_set_force_ce,
+		.set_ecc             = nfc_3_2_set_ecc,
+		.get_ecc_status      = nfc_3_2_get_ecc_status,
+		.get_symmetric       = nfc_3_2_get_symmetric,
+		.set_symmetric       = nfc_3_2_set_symmetric,
+		.select_chip         = nfc_3_2_select_chip,
+		.command_cycle       = nfc_3_2_command_cycle,
+		.write_cycle         = nfc_3_2_write_cycle,
+		.read_cycle          = nfc_3_2_read_cycle,
+		.read_page           = nfc_3_2_read_page,
+		.send_page           = nfc_3_2_send_page,
+		.start_auto_read     = nfc_3_2_start_auto_read,
+		.wait_for_auto_read  = nfc_3_2_wait_for_auto_read,
+		.resume_auto_read    = nfc_3_2_resume_auto_read,
+		.start_auto_write    = nfc_3_2_start_auto_write,
+		.wait_for_auto_write = nfc_3_2_wait_for_auto_write,
+		.start_auto_erase    = nfc_3_2_start_auto_erase,
+	};
+
+/*
+ * This array has a pointer to every NFC HAL structure. The probing process will
+ * find the one that matches the version given by the platform.
+ */
+
+struct nfc_hal  *(nfc_hals[]) = {
+	&nfc_1_0_hal,
+	&nfc_2_0_hal,
+	&nfc_2_1_hal,
+	&nfc_3_1_hal,
+	&nfc_3_2_hal,
+};
+
+/**
+ * mal_init() - Initialize the Medium Abstraction Layer.
+ *
+ * @this:  Per-device data.
+ */
+static void mal_init(struct imx_nfc_data  *this)
+{
+	this->interrupt_override = DRIVER_CHOICE;
+	this->auto_op_override   = DRIVER_CHOICE;
+	this->inject_ecc_error   = 0;
+}
+
+/**
+ * mal_set_physical_geometry() - Set up the physical medium geometry.
+ *
+ * This function retrieves the physical geometry information discovered by
+ * nand_scan(), corrects it, and records it in the per-device data structure.
+ *
+ * @this:  Per-device data.
+ */
+static int mal_set_physical_geometry(struct imx_nfc_data  *this)
+{
+	struct mtd_info           *mtd  = &this->mtd;
+	struct nand_chip          *nand = &this->nand;
+	struct device             *dev  = this->dev;
+	uint8_t                   manufacturer_id;
+	uint8_t                   device_id;
+	unsigned int              block_size_in_pages;
+	unsigned int              chip_size_in_blocks;
+	unsigned int              chip_size_in_pages;
+	uint64_t                  medium_size_in_bytes;
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	/*
+	 * Begin by transcribing exactly what the MTD code discovered. If there
+	 * are any mistakes, we'll fix them in a moment.
+	 */
+
+	physical->chip_count     = nand->numchips;
+	physical->chip_size      = nand->chipsize;
+	physical->block_size     = mtd->erasesize;
+	physical->page_data_size = mtd->writesize;
+	physical->page_oob_size  = mtd->oobsize;
+
+	/* Read some of the ID bytes from the first NAND Flash chip. */
+
+	nand->select_chip(mtd, 0);
+
+	nfc_util_send_cmd_and_addrs(this, NAND_CMD_READID, 0x00, -1);
+
+	manufacturer_id = nand->read_byte(mtd);
+	device_id       = nand->read_byte(mtd);
+
+	/*
+	 * Most manufacturers sell 4K page devices with 218 out-of-band bytes
+	 * per page to accomodate ECC-8.
+	 *
+	 * Samsung and Hynix claim their parts have better reliability, so they
+	 * only need ECC-4 and they have only 128 out-of-band bytes.
+	 *
+	 * The MTD code pays no attention to the manufacturer ID (something that
+	 * eventually will have to change), so it believes that all 4K pages
+	 * have 218 out-of-band bytes.
+	 *
+	 * We correct that mistake here.
+	 */
+
+	if (physical->page_data_size == 4096) {
+		if ((manufacturer_id == NAND_MFR_SAMSUNG) ||
+					(manufacturer_id == NAND_MFR_HYNIX)) {
+			physical->page_oob_size = 128;
+		}
+	}
+
+	/* Compute some interesting facts. */
+
+	block_size_in_pages  =
+		physical->block_size / physical->page_data_size;
+	chip_size_in_pages   =
+		physical->chip_size >> (fls(physical->page_data_size) - 1);
+	chip_size_in_blocks  =
+		physical->chip_size >> (fls(physical->block_size) - 1);
+	medium_size_in_bytes =
+		physical->chip_size * physical->chip_count;
+
+	/* Report. */
+
+	dev_dbg(dev, "-----------------\n");
+	dev_dbg(dev, "Physical Geometry\n");
+	dev_dbg(dev, "-----------------\n");
+	dev_dbg(dev, "Chip Count             : %d\n", physical->chip_count);
+	dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n",
+			physical->page_data_size, physical->page_data_size);
+	dev_dbg(dev, "Page OOB Size in Bytes : %u\n",
+			physical->page_oob_size);
+	dev_dbg(dev, "Block Size in Bytes    : %u (0x%x)\n",
+			physical->block_size, physical->block_size);
+	dev_dbg(dev, "Block Size in Pages    : %u (0x%x)\n",
+			block_size_in_pages, block_size_in_pages);
+	dev_dbg(dev, "Chip Size in Bytes     : %llu (0x%llx)\n",
+			physical->chip_size, physical->chip_size);
+	dev_dbg(dev, "Chip Size in Pages     : %u (0x%x)\n",
+			chip_size_in_pages, chip_size_in_pages);
+	dev_dbg(dev, "Chip Size in Blocks    : %u (0x%x)\n",
+			chip_size_in_blocks, chip_size_in_blocks);
+	dev_dbg(dev, "Medium Size in Bytes   : %llu (0x%llx)\n",
+			medium_size_in_bytes, medium_size_in_bytes);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mal_set_nfc_geometry() - Set up the NFC geometry.
+ *
+ * This function calls the NFC HAL to select an NFC geometry that is compatible
+ * with the medium's physical geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mal_set_nfc_geometry(struct imx_nfc_data  *this)
+{
+	struct device        *dev = this->dev;
+	struct nfc_geometry  *nfc;
+
+	/* Set the NFC geometry. */
+
+	if (this->nfc->set_geometry(this))
+		return !0;
+
+	/* Get a pointer to the new NFC geometry information. */
+
+	nfc = this->nfc_geometry;
+
+	/* Report. */
+
+	dev_dbg(dev, "------------\n");
+	dev_dbg(dev, "NFC Geometry\n");
+	dev_dbg(dev, "------------\n");
+	dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n",
+				nfc->page_data_size, nfc->page_data_size);
+	dev_dbg(dev, "Page OOB Size in Bytes : %u\n", nfc->page_oob_size);
+	dev_dbg(dev, "ECC Algorithm          : %s\n", nfc->ecc_algorithm);
+	dev_dbg(dev, "ECC Strength           : %d\n", nfc->ecc_strength);
+	dev_dbg(dev, "Buffer Count           : %u\n", nfc->buffer_count);
+	dev_dbg(dev, "Spare Buffer Size      : %u\n", nfc->spare_buf_size);
+	dev_dbg(dev, "Spare Buffer Spillover : %u\n", nfc->spare_buf_spill);
+	dev_dbg(dev, "Auto Read Available    : %s\n",
+				this->nfc->start_auto_read  ? "Yes" : "No");
+	dev_dbg(dev, "Auto Write Available   : %s\n",
+				this->nfc->start_auto_write ? "Yes" : "No");
+	dev_dbg(dev, "Auto Erase Available   : %s\n",
+				this->nfc->start_auto_erase ? "Yes" : "No");
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mal_set_logical_geometry() - Set up the logical medium geometry.
+ *
+ * This function constructs the logical geometry that we will expose to MTD,
+ * based on the physical and NFC geometries, and whether or not interleaving is
+ * on.
+ *
+ * @this:  Per-device data.
+ */
+static int mal_set_logical_geometry(struct imx_nfc_data  *this)
+{
+	const uint32_t            max_medium_size_in_bytes = ~0;
+	int                       we_are_interleaving;
+	uint64_t                  physical_medium_size_in_bytes;
+	unsigned int              usable_blocks;
+	unsigned int              block_size_in_pages;
+	unsigned int              chip_size_in_blocks;
+	unsigned int              chip_size_in_pages;
+	unsigned int              usable_medium_size_in_pages;
+	unsigned int              usable_medium_size_in_blocks;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nfc_geometry       *nfc      =  this->nfc_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+	struct device             *dev      =  this->dev;
+
+	/* Figure out if we're interleaving. */
+
+	we_are_interleaving = this->pdata->interleave;
+
+	switch (imx_nfc_module_interleave_override) {
+
+	case NEVER:
+		we_are_interleaving = false;
+		break;
+
+	case DRIVER_CHOICE:
+		break;
+
+	case ALWAYS:
+		we_are_interleaving = true;
+		break;
+
+	}
+
+	/* Compute the physical size of the medium. */
+
+	physical_medium_size_in_bytes =
+				physical->chip_count * physical->chip_size;
+
+	/* Compute the logical geometry. */
+
+	if (!we_are_interleaving) {
+
+		/*
+		 * At this writing, MTD uses unsigned 32-bit variables to
+		 * represent the size of the medium. If the physical medium is
+		 * larger than that, the logical medium must be smaller. Here,
+		 * we compute the total number of physical blocks in the medium
+		 * that we can actually use.
+		 */
+
+		if (physical_medium_size_in_bytes <= max_medium_size_in_bytes) {
+			usable_blocks =
+				physical_medium_size_in_bytes >>
+						(ffs(physical->block_size) - 1);
+		} else {
+			usable_blocks =
+				max_medium_size_in_bytes / physical->block_size;
+		}
+
+		/* Set up the logical geometry.
+		 *
+		 * Notice that the usable medium size is not necessarily the
+		 * same as the chip size multiplied by the number of physical
+		 * chips. We can't afford to touch the physical chip size
+		 * because the NAND Flash MTD code *requires* it to be a power
+		 * of 2.
+		 */
+
+		logical->chip_count     = physical->chip_count;
+		logical->chip_size      = physical->chip_size;
+		logical->usable_size    = usable_blocks * physical->block_size;
+		logical->block_size     = physical->block_size;
+		logical->page_data_size = nfc->page_data_size;
+
+		/* Use the MTD layout that best matches the NFC geometry. */
+
+		logical->mtd_layout    = &nfc->mtd_layout;
+		logical->page_oob_size = nfc->mtd_layout.eccbytes +
+						nfc->mtd_layout.oobavail;
+
+	} else {
+
+		/*
+		 * If control arrives here, we are interleaving. Specifically,
+		 * we are "horizontally concatenating" the pages in all the
+		 * physical chips.
+		 *
+		 * - A logical page will be the size of a physical page
+		 *   multiplied by the number of physical chips.
+		 *
+		 * - A logical block will have the same number of pages as a
+		 *   physical block but, since the logical page size is larger,
+		 *   the logical block size is larger.
+		 *
+		 * - The entire medium will appear to be a single chip.
+		 *
+		 * At this writing, MTD uses unsigned 32-bit variables to
+		 * represent the size of the medium. If the physical medium is
+		 * larger than that, the logical medium must be smaller.
+		 *
+		 * The NAND Flash MTD code represents the size of a single chip
+		 * as an unsigned 32-bit value. It also *requires* that the size
+		 * of a chip be a power of two. Thus, the largest possible chip
+		 * size is 2GiB.
+		 *
+		 * When interleaving, the entire medium appears to be one chip.
+		 * Thus, when interleaving, the largest possible medium size is
+		 * 2GiB.
+		 */
+
+		if (physical_medium_size_in_bytes <= max_medium_size_in_bytes) {
+			logical->chip_size =
+				0x1 << (fls(physical_medium_size_in_bytes) - 1);
+		} else {
+			logical->chip_size =
+				0x1 << (fls(max_medium_size_in_bytes) - 1);
+		}
+
+		/*
+		 * If control arrives here, we're interleaving. The logical
+		 * geometry is very different from the physical geometry.
+		 */
+
+		logical->chip_count     = 1;
+		logical->usable_size    = logical->chip_size;
+		logical->block_size     =
+				physical->block_size * physical->chip_count;
+		logical->page_data_size =
+				nfc->page_data_size * physical->chip_count;
+
+		/*
+		 * Since the logical geometry doesn't match the physical
+		 * geometry, we can't use the MTD layout that matches the
+		 * NFC geometry. We synthesize one here.
+		 *
+		 * Our "logical" OOB will be the concatenation of the first 5
+		 * bytes of the "physical" OOB of every chip. This has some
+		 * important properties:
+		 *
+		 * - This will make the block mark of every physical chip
+		 *   visible (even for small page chips, which put their block
+		 *   mark in the 5th OOB byte).
+		 *
+		 * - None of the NFC controllers put ECC in the first 5 OOB
+		 *   bytes, so this layout exposes no ECC.
+		 */
+
+		logical->page_oob_size = 5 * physical->chip_count;
+
+		synthetic_layout.eccbytes = 0;
+		synthetic_layout.oobavail = 5 * physical->chip_count;
+		synthetic_layout.oobfree[0].offset = 0;
+		synthetic_layout.oobfree[0].length = synthetic_layout.oobavail;
+
+		/* Install the synthetic layout. */
+
+		logical->mtd_layout = &synthetic_layout;
+
+	}
+
+	/* Compute some interesting facts. */
+
+	block_size_in_pages = logical->block_size / logical->page_data_size;
+	chip_size_in_pages  = logical->chip_size / logical->page_data_size;
+	chip_size_in_blocks = logical->chip_size / logical->block_size;
+	usable_medium_size_in_pages =
+				logical->usable_size / logical->page_data_size;
+	usable_medium_size_in_blocks =
+				logical->usable_size / logical->block_size;
+
+	/* Report. */
+
+	dev_dbg(dev, "----------------\n");
+	dev_dbg(dev, "Logical Geometry\n");
+	dev_dbg(dev, "----------------\n");
+	dev_dbg(dev, "Chip Count             : %d\n", logical->chip_count);
+	dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n",
+		logical->page_data_size, logical->page_data_size);
+	dev_dbg(dev, "Page OOB Size in Bytes : %u\n",
+		logical->page_oob_size);
+	dev_dbg(dev, "Block Size in Bytes    : %u (0x%x)\n",
+		logical->block_size, logical->block_size);
+	dev_dbg(dev, "Block Size in Pages    : %u (0x%x)\n",
+		block_size_in_pages, block_size_in_pages);
+	dev_dbg(dev, "Chip Size in Bytes     : %u (0x%x)\n",
+		logical->chip_size, logical->chip_size);
+	dev_dbg(dev, "Chip Size in Pages     : %u (0x%x)\n",
+		chip_size_in_pages, chip_size_in_pages);
+	dev_dbg(dev, "Chip Size in Blocks    : %u (0x%x)\n",
+		chip_size_in_blocks, chip_size_in_blocks);
+	dev_dbg(dev, "Physical Size in Bytes : %llu (0x%llx)\n",
+		physical_medium_size_in_bytes, physical_medium_size_in_bytes);
+	dev_dbg(dev, "Usable Size in Bytes   : %u (0x%x)\n",
+		logical->usable_size, logical->usable_size);
+	dev_dbg(dev, "Usable Size in Pages   : %u (0x%x)\n",
+		usable_medium_size_in_pages, usable_medium_size_in_pages);
+	dev_dbg(dev, "Usable Size in Blocks  : %u (0x%x)\n",
+		usable_medium_size_in_blocks, usable_medium_size_in_blocks);
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mal_set_mtd_geometry() - Set up the MTD geometry.
+ *
+ * This function adjusts the owning MTD data structures to match the logical
+ * geometry we've chosen.
+ *
+ * @this:  Per-device data.
+ */
+static int mal_set_mtd_geometry(struct imx_nfc_data *this)
+{
+	struct logical_geometry  *logical = &this->logical_geometry;
+	struct mtd_info          *mtd     = &this->mtd;
+	struct nand_chip         *nand    = &this->nand;
+
+	/* Configure the struct mtd_info. */
+
+	mtd->size        = logical->usable_size;
+	mtd->erasesize   = logical->block_size;
+	mtd->writesize   = logical->page_data_size;
+	mtd->ecclayout   = logical->mtd_layout;
+	mtd->oobavail    = mtd->ecclayout->oobavail;
+	mtd->oobsize     = mtd->ecclayout->oobavail + mtd->ecclayout->eccbytes;
+	mtd->subpage_sft = 0; /* We don't support sub-page writing. */
+
+	/* Configure the struct nand_chip. */
+
+	nand->numchips         = logical->chip_count;
+	nand->chipsize         = logical->chip_size;
+	nand->page_shift       = ffs(logical->page_data_size) - 1;
+	nand->pagemask         = (nand->chipsize >> nand->page_shift) - 1;
+	nand->subpagesize      = mtd->writesize >> mtd->subpage_sft;
+	nand->phys_erase_shift = ffs(logical->block_size) - 1;
+	nand->bbt_erase_shift  = nand->phys_erase_shift;
+	nand->chip_shift       = ffs(logical->chip_size) - 1;
+	nand->oob_poi          = nand->buffers->databuf+logical->page_data_size;
+	nand->ecc.layout       = logical->mtd_layout;
+
+	/* Set up the pattern that describes block marks. */
+
+	if (is_small_page_chip(this))
+		nand->badblock_pattern = &small_page_block_mark_descriptor;
+	else
+		nand->badblock_pattern = &large_page_block_mark_descriptor;
+
+	/* Return success. */
+
+	return 0;
+}
+
+/**
+ * mal_set_geometry() - Set up the medium geometry.
+ *
+ * @this:  Per-device data.
+ */
+static int mal_set_geometry(struct imx_nfc_data  *this)
+{
+
+	/* Set up the various layers of geometry, in this specific order. */
+
+	if (mal_set_physical_geometry(this))
+		return !0;
+
+	if (mal_set_nfc_geometry(this))
+		return !0;
+
+	if (mal_set_logical_geometry(this))
+		return !0;
+
+	if (mal_set_mtd_geometry(this))
+		return !0;
+
+	/* Return success. */
+
+	return 0;
+
+}
+
+/**
+ * mal_reset() - Resets the given chip.
+ *
+ * This is the fully-generalized reset operation, including support for
+ * interleaving. All reset operations funnel through here.
+ *
+ * @this:  Per-device data.
+ * @chip:  The logical chip of interest.
+ */
+static void mal_reset(struct imx_nfc_data *this, unsigned chip)
+{
+	int                       we_are_interleaving;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              i;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	add_event("Entering mal_get_status", 1);
+
+	/* Establish some important facts. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+
+	/* Choose the loop bounds. */
+
+	if (we_are_interleaving) {
+		start = 0;
+		end   = physical->chip_count;
+	} else {
+		start = chip;
+		end   = start + 1;
+	}
+
+	/* Loop over physical chips. */
+
+	add_event("Looping over physical chips...", 0);
+
+	for (i = start; i < end; i++) {
+
+		/* Select the current chip. */
+
+		this->nfc->select_chip(this, i);
+
+		/* Reset the current chip. */
+
+		add_event("Resetting...", 0);
+
+		nfc_util_send_cmd(this, NAND_CMD_RESET);
+		nfc_util_wait_for_the_nfc(this, false);
+
+	}
+
+	add_event("Exiting mal_get_status", -1);
+
+}
+
+/**
+ * mal_get_status() - Abstracted status retrieval.
+ *
+ * For media with a single chip, or concatenated chips, the HIL explicitly
+ * addresses a single chip at a time and wants the status from that chip only.
+ *
+ * For interleaved media, we must combine the individual chip states. At this
+ * writing, the NAND MTD system knows about the following bits in status
+ * registers:
+ *
+ *    +------------------------+-------+---------+
+ *    |                        |       | Combine |
+ *    |         Macro          | Value |  With   |
+ *    +------------------------+-------+---------+
+ *    | NAND_STATUS_FAIL       |  0x01 |    OR   |
+ *    | NAND_STATUS_FAIL_N1    |  0x02 |    OR   |
+ *    | NAND_STATUS_TRUE_READY |  0x20 |   AND   |
+ *    | NAND_STATUS_READY      |  0x40 |   AND   |
+ *    | NAND_STATUS_WP         |  0x80 |   AND   |
+ *    +------------------------+-------+---------+
+ *
+ * @this:  Per-device data.
+ * @chip:  The logical chip of interest.
+ */
+static uint8_t mal_get_status(struct imx_nfc_data *this, unsigned chip)
+{
+	int                       we_are_interleaving;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              i;
+	unsigned int              x;
+	unsigned int              or_mask;
+	unsigned int              and_mask;
+	uint8_t                   status;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	add_event("Entering mal_get_status", 1);
+
+	/* Establish some important facts. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+
+	/* Compute the masks we need. */
+
+	or_mask  = NAND_STATUS_FAIL | NAND_STATUS_FAIL_N1;
+	and_mask = NAND_STATUS_TRUE_READY | NAND_STATUS_READY | NAND_STATUS_WP;
+
+	/* Assume the chip is successful, ready and writeable. */
+
+	status = and_mask & ~or_mask;
+
+	/* Choose the loop bounds. */
+
+	if (we_are_interleaving) {
+		start = 0;
+		end   = physical->chip_count;
+	} else {
+		start = chip;
+		end   = start + 1;
+	}
+
+	/* Loop over physical chips. */
+
+	add_event("Looping over physical chips...", 0);
+
+	for (i = start; i < end; i++) {
+
+		/* Select the current chip. */
+
+		this->nfc->select_chip(this, i);
+
+		/* Get the current chip's status. */
+
+		add_event("Sending the command...", 0);
+
+		nfc_util_send_cmd(this, NAND_CMD_STATUS);
+		nfc_util_wait_for_the_nfc(this, false);
+
+		add_event("Reading the status...", 0);
+
+		x = this->nfc->read_cycle(this);
+
+		/* Fold this chip's status into the combined status. */
+
+		status |= (x & or_mask);
+		status &= (x & and_mask) | or_mask;
+
+	}
+
+	add_event("Exiting mal_get_status", -1);
+
+	return status;
+
+}
+
+/**
+ * mal_read_a_page() - Abstracted page read.
+ *
+ * This function returns the ECC status for the entire read operation. A
+ * positive return value indicates the number of errors that were corrected
+ * (symbol errors for Reed-Solomon hardware engines, bit errors for BCH hardware
+ * engines). A negative return value indicates that the ECC engine failed to
+ * correct all errors and the data is corrupted. A zero return value indicates
+ * there were no errors at all.
+ *
+ * @this:    Per-device data.
+ * @use_ecc: Indicates if we're to use ECC.
+ * @chip:    The logical chip of interest.
+ * @page:    The logical page number to read.
+ * @data:    A pointer to the destination data buffer. If this pointer is null,
+ *           that indicates the caller doesn't want the data.
+ * @oob:     A pointer to the destination OOB buffer. If this pointer is null,
+ *           that indicates the caller doesn't want the OOB.
+ */
+static int mal_read_a_page(struct imx_nfc_data *this, int use_ecc,
+		unsigned chip, unsigned page, uint8_t *data, uint8_t *oob)
+{
+	int                       we_are_interleaving;
+	int                       use_automatic_op;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              current_chip;
+	unsigned int              oob_bytes_to_copy;
+	unsigned int              data_bytes_to_copy;
+	int                       status;
+	unsigned int              worst_case_ecc_status;
+	int                       return_value = 0;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nfc_geometry       *nfc      = this->nfc_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	add_event("Entering mal_read_a_page", 1);
+
+	/* Establish some important facts. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+	use_automatic_op    = !!this->nfc->start_auto_read;
+
+	/* Apply the automatic operation override, if any. */
+
+	switch (this->auto_op_override) {
+
+	case NEVER:
+		use_automatic_op = false;
+		break;
+
+	case DRIVER_CHOICE:
+		break;
+
+	case ALWAYS:
+		if (this->nfc->start_auto_read)
+			use_automatic_op = true;
+		break;
+
+	}
+
+	/* Set up ECC. */
+
+	this->nfc->set_ecc(this, use_ecc);
+
+	/* Check if we're interleaving and set up the loop iterations. */
+
+	if (we_are_interleaving) {
+
+		start = 0;
+		end   = physical->chip_count;
+
+		data_bytes_to_copy =
+			this->logical_geometry.page_data_size /
+					this->physical_geometry.chip_count;
+		oob_bytes_to_copy =
+			this->logical_geometry.page_oob_size /
+					this->physical_geometry.chip_count;
+
+	} else {
+
+		start = chip;
+		end   = start + 1;
+
+		data_bytes_to_copy = this->logical_geometry.page_data_size;
+		oob_bytes_to_copy  = this->logical_geometry.page_oob_size;
+
+	}
+
+	/* If we're using the automatic operation, start it now. */
+
+	if (use_automatic_op) {
+		add_event("Starting the automatic operation...", 0);
+		this->nfc->start_auto_read(this, start, end - start, 0, page);
+	}
+
+	/* Loop over physical chips. */
+
+	add_event("Looping over physical chips...", 0);
+
+	for (current_chip = start; current_chip < end; current_chip++) {
+
+		/* Check if we're using the automatic operation. */
+
+		if (use_automatic_op) {
+
+			add_event("Waiting...", 0);
+			this->nfc->wait_for_auto_read(this);
+
+		} else {
+
+			/* Select the current chip. */
+
+			this->nfc->select_chip(this, current_chip);
+
+			/* Set up the chip. */
+
+			add_event("Sending the command and addresses...", 0);
+
+			nfc_util_send_cmd_and_addrs(this,
+						NAND_CMD_READ0, 0, page);
+
+			if (is_large_page_chip(this)) {
+				add_event("Sending the final command...", 0);
+				nfc_util_send_cmd(this, NAND_CMD_READSTART);
+			}
+
+			/* Wait till the page is ready. */
+
+			add_event("Waiting for the page to arrive...", 0);
+
+			nfc_util_wait_for_the_nfc(this, true);
+
+			/* Read the page. */
+
+			add_event("Reading the page...", 0);
+
+			this->nfc->read_page(this);
+
+		}
+
+		/* Copy a page out of the NFC. */
+
+		add_event("Copying from the NFC...", 0);
+
+		if (oob) {
+			nfc_util_copy_from_the_nfc(this,
+				nfc->page_data_size, oob, oob_bytes_to_copy);
+			oob += oob_bytes_to_copy;
+		}
+
+		if (data) {
+			nfc_util_copy_from_the_nfc(this,
+						0, data, data_bytes_to_copy);
+			data += data_bytes_to_copy;
+		}
+
+		/*
+		 * If we're using ECC, and we haven't already seen an ECC
+		 * failure, continue to gather ECC status. Note that, if we
+		 * *do* see an ECC failure, we continue to read because the
+		 * client might want the data for forensic purposes.
+		 */
+
+		if (use_ecc && (return_value >= 0)) {
+
+			add_event("Getting ECC status...", 0);
+
+			status = this->nfc->get_ecc_status(this);
+
+			if (status >= 0)
+				return_value += status;
+			else
+				return_value = -1;
+
+		}
+
+		/* Check if we're using the automatic operation. */
+
+		if (use_automatic_op) {
+
+			/*
+			 * If this is not the last iteration, resume the
+			 * automatic operation.
+			 */
+
+			if (current_chip < (end - 1)) {
+				add_event("Resuming...", 0);
+				this->nfc->resume_auto_read(this);
+			}
+
+		}
+
+	}
+
+	/* Check if we're supposed to inject an ECC error. */
+
+	if (use_ecc && this->inject_ecc_error) {
+
+		/* Inject the appropriate error. */
+
+		if (this->inject_ecc_error < 0) {
+
+			add_event("Injecting an uncorrectable error...", 0);
+
+			return_value = -1;
+
+		} else {
+
+			add_event("Injecting correctable errors...", 0);
+
+			worst_case_ecc_status =
+				physical->chip_count *
+				nfc->buffer_count *
+				nfc->ecc_strength;
+
+			if (this->inject_ecc_error > worst_case_ecc_status)
+				return_value = worst_case_ecc_status;
+			else
+				return_value = this->inject_ecc_error;
+
+		}
+
+		/* Stop injecting further errors. */
+
+		this->inject_ecc_error = 0;
+
+	}
+
+	/* Return. */
+
+	add_event("Exiting mal_read_a_page", -1);
+
+	return return_value;
+
+}
+
+/**
+ * mal_write_a_page() - Abstracted page write.
+ *
+ * This function returns zero if the operation succeeded, or -EIO if the
+ * operation failed.
+ *
+ * @this:    Per-device data.
+ * @use_ecc: Indicates if we're to use ECC.
+ * @chip:    The logical chip of interest.
+ * @page:    The logical page number to write.
+ * @data:    A pointer to the source data buffer.
+ * @oob:     A pointer to the source OOB buffer.
+ */
+static int mal_write_a_page(struct imx_nfc_data *this, int use_ecc,
+	unsigned chip, unsigned page, const uint8_t *data, const uint8_t *oob)
+{
+	int                       we_are_interleaving;
+	int                       use_automatic_op;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              current_chip;
+	unsigned int              oob_bytes_to_copy;
+	unsigned int              data_bytes_to_copy;
+	int                       return_value = 0;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct nfc_geometry       *nfc      = this->nfc_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	add_event("Entering mal_write_a_page", 1);
+
+	/* Establish some important facts. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+	use_automatic_op    = !!this->nfc->start_auto_write;
+
+	/* Apply the automatic operation override, if any. */
+
+	switch (this->auto_op_override) {
+
+	case NEVER:
+		use_automatic_op = false;
+		break;
+
+	case DRIVER_CHOICE:
+		break;
+
+	case ALWAYS:
+		if (this->nfc->start_auto_write)
+			use_automatic_op = true;
+		break;
+
+	}
+
+	/* Set up ECC. */
+
+	this->nfc->set_ecc(this, use_ecc);
+
+	/* Check if we're interleaving and set up the loop iterations. */
+
+	if (we_are_interleaving) {
+
+		start = 0;
+		end   = physical->chip_count;
+
+		data_bytes_to_copy =
+			this->logical_geometry.page_data_size /
+					this->physical_geometry.chip_count;
+		oob_bytes_to_copy =
+			this->logical_geometry.page_oob_size /
+					this->physical_geometry.chip_count;
+
+	} else {
+
+		start = chip;
+		end   = start + 1;
+
+		data_bytes_to_copy = this->logical_geometry.page_data_size;
+		oob_bytes_to_copy  = this->logical_geometry.page_oob_size;
+
+	}
+
+	/* If we're using the automatic operation, start the hardware now. */
+
+	if (use_automatic_op) {
+		add_event("Starting the automatic operation...", 0);
+		this->nfc->start_auto_write(this, start, end - start, 0, page);
+	}
+
+	/* Loop over physical chips. */
+
+	add_event("Looping over physical chips...", 0);
+
+	for (current_chip = start; current_chip < end; current_chip++) {
+
+		/* Copy a page into the NFC. */
+
+		add_event("Copying to the NFC...", 0);
+
+		nfc_util_copy_to_the_nfc(this, oob, nfc->page_data_size,
+							oob_bytes_to_copy);
+		oob += oob_bytes_to_copy;
+
+		nfc_util_copy_to_the_nfc(this, data, 0, data_bytes_to_copy);
+
+		data += data_bytes_to_copy;
+
+		/* Check if we're using the automatic operation. */
+
+		if (use_automatic_op) {
+
+			/* Wait for the write operation to finish. */
+
+			add_event("Waiting...", 0);
+
+			this->nfc->wait_for_auto_write(this);
+
+		} else {
+
+			/* Select the current chip. */
+
+			this->nfc->select_chip(this, current_chip);
+
+			/* Set up the chip. */
+
+			add_event("Sending the command and addresses...", 0);
+
+			nfc_util_send_cmd_and_addrs(this,
+						NAND_CMD_SEQIN, 0, page);
+
+			/* Send the page. */
+
+			add_event("Sending the page...", 0);
+
+			this->nfc->send_page(this);
+
+			/* Start programming the page. */
+
+			add_event("Programming the page...", 0);
+
+			nfc_util_send_cmd(this, NAND_CMD_PAGEPROG);
+
+			/* Wait until the page is finished. */
+
+			add_event("Waiting...", 0);
+
+			nfc_util_wait_for_the_nfc(this, true);
+
+		}
+
+	}
+
+	/* Get status. */
+
+	add_event("Gathering status...", 0);
+
+	if (mal_get_status(this, chip) & NAND_STATUS_FAIL) {
+		add_event("Bad status", 0);
+		return_value = -EIO;
+	} else {
+		add_event("Good status", 0);
+	}
+
+	/* Return. */
+
+	add_event("Exiting mal_write_a_page", -1);
+
+	return return_value;
+
+}
+
+/**
+ * mal_erase_a_block() - Abstract block erase operation.
+ *
+ * Note that this function does *not* wait for the operation to finish. The
+ * caller is expected to call waitfunc() at some later time.
+ *
+ * @this:  Per-device data.
+ * @chip:  The logical chip of interest.
+ * @page:  A logical page address that identifies the block to erase.
+ */
+static void mal_erase_a_block(struct imx_nfc_data *this,
+						unsigned chip, unsigned page)
+{
+	int                       we_are_interleaving;
+	int                       use_automatic_op;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              i;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	add_event("Entering mal_erase_a_block", 1);
+
+	/* Establish some important facts. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+	use_automatic_op    = !!this->nfc->start_auto_erase;
+
+	/* Apply the automatic operation override, if any. */
+
+	switch (this->auto_op_override) {
+
+	case NEVER:
+		use_automatic_op = false;
+		break;
+
+	case DRIVER_CHOICE:
+		break;
+
+	case ALWAYS:
+		if (this->nfc->start_auto_erase)
+			use_automatic_op = true;
+		break;
+
+	}
+
+	/* Choose the loop bounds. */
+
+	if (we_are_interleaving) {
+		start = 0;
+		end   = physical->chip_count;
+	} else {
+		start = chip;
+		end   = start + 1;
+	}
+
+	/* Check if we're using the automatic operation. */
+
+	if (use_automatic_op) {
+
+		/*
+		 * Start the operation. Note that we don't wait for it to
+		 * finish because the HIL will call our waitfunc().
+		 */
+
+		add_event("Starting the automatic operation...", 0);
+
+		this->nfc->start_auto_erase(this, start, end - start, page);
+
+	} else {
+
+		/* Loop over physical chips. */
+
+		add_event("Looping over physical chips...", 0);
+
+		for (i = start; i < end; i++) {
+
+			/* Select the current chip. */
+
+			this->nfc->select_chip(this, i);
+
+			/* Set up the chip. */
+
+			nfc_util_send_cmd_and_addrs(this,
+						NAND_CMD_ERASE1, -1, page);
+
+			/* Start the erase. */
+
+			nfc_util_send_cmd(this, NAND_CMD_ERASE2);
+
+			/*
+			 * If this is the last time through the loop, break out
+			 * now so we don't try to wait (the HIL will call our
+			 * waitfunc() for the final wait).
+			 */
+
+			if (i >= (end - 1))
+				break;
+
+			/* Wait for the erase on the current chip to finish. */
+
+			nfc_util_wait_for_the_nfc(this, true);
+
+		}
+
+	}
+
+	add_event("Exiting mal_erase_a_block", -1);
+
+}
+
+/**
+ * mal_is_block_bad() - Abstract bad block check.
+ *
+ * @this:    Per-device data.
+ * @chip:    The logical chip of interest.
+ * @page:    The logical page number to read.
+ */
+ #if 0
+
+/* TODO: Finish this function and plug it in. */
+
+static int mal_is_block_bad(struct imx_nfc_data *this,
+						unsigned chip, unsigned page)
+{
+	int                       we_are_interleaving;
+	unsigned int              start;
+	unsigned int              end;
+	unsigned int              i;
+	uint8_t                   *p;
+	int                       return_value = 0;
+	struct nand_chip          *nand = &this->nand;
+	struct physical_geometry  *physical = &this->physical_geometry;
+	struct logical_geometry   *logical  = &this->logical_geometry;
+
+	/* Figure out if we're interleaving. */
+
+	we_are_interleaving = logical->chip_count != physical->chip_count;
+
+	/*
+	 * We're about to use the NAND Flash MTD layer's buffer, so invalidate
+	 * the page cache.
+	 */
+
+	this->nand.pagebuf = -1;
+
+	/*
+	 * Read the OOB of the given page, using the NAND Flash MTD's buffer.
+	 *
+	 * Notice that ECC is off, which it *must* be when scanning block marks.
+	 */
+
+	mal_read_a_page(this, false,
+		this->current_chip, this->page_address, 0, nand->oob_poi);
+
+	/* Choose the loop bounds. */
+
+	if (we_are_interleaving) {
+		start = 0;
+		end   = physical->chip_count;
+	} else {
+		start = chip;
+		end   = start + 1;
+	}
+
+	/* Start scanning at the beginning of the OOB data. */
+
+	p = nand->oob_poi;
+
+	/* Loop over physical chips. */
+
+	add_event("Looping over physical chips...", 0);
+
+	for (i = start; i < end; i++, p += 5) {
+
+		/* Examine the OOB for this chip. */
+
+		if (p[nand->badblockpos] != 0xff) {
+			return_value = !0;
+			break;
+		}
+
+	}
+
+	/* Return. */
+
+	return return_value;
+
+}
+#endif
+
+/**
+ * mil_init() - Initializes the MTD Interface Layer.
+ *
+ * @this:    Per-device data.
+ */
+static void mil_init(struct imx_nfc_data *this)
+{
+	this->current_chip   = -1;    /* No chip is selected yet. */
+	this->command_is_new = false; /* No command yet.          */
+}
+
+/**
+ * mil_cmd_ctrl() - MTD Interface cmd_ctrl()
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @dat:  The data signals to present to the chip.
+ * @ctrl: The control signals to present to the chip.
+ */
+static void mil_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_dev_ready() - MTD Interface dev_ready()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ */
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc dev_ready]\n");
+
+	add_event("Entering mil_dev_ready", 1);
+
+	if (this->nfc->is_ready(this)) {
+		add_event("Exiting mil_dev_ready - Returning ready", -1);
+		return !0;
+	} else {
+		add_event("Exiting mil_dev_ready - Returning busy", -1);
+		return 0;
+	}
+
+}
+
+/**
+ * mil_select_chip() - MTD Interface select_chip()
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @chip:  The chip number to select, or -1 to select no chip.
+ */
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc select_chip] chip: %d\n", chip);
+
+	/* Figure out what kind of transition this is. */
+
+	if ((this->current_chip < 0) && (chip >= 0)) {
+		start_event_trace("Entering mil_select_chip");
+		if (this->pdata->force_ce)
+			this->nfc->set_force_ce(this, true);
+		clk_enable(this->clock);
+		add_event("Exiting mil_select_chip", -1);
+	} else if ((this->current_chip >= 0) && (chip < 0)) {
+		add_event("Entering mil_select_chip", 1);
+		if (this->pdata->force_ce)
+			this->nfc->set_force_ce(this, false);
+		clk_disable(this->clock);
+		stop_event_trace("Exiting mil_select_chip");
+	} else {
+		add_event("Entering mil_select_chip", 1);
+		add_event("Exiting mil_select_chip", -1);
+	}
+
+	this->current_chip = chip;
+
+}
+
+/**
+ * mil_cmdfunc() - MTD Interface cmdfunc()
+ *
+ * This function handles NAND Flash command codes from the HIL. Since only the
+ * HIL calls this function (none of the reference implementations we use do), it
+ * needs to handle very few command codes.
+ *
+ * @mtd:      A pointer to the owning MTD.
+ * @command:  The command code.
+ * @column:   The column address associated with this command code, or -1 if no
+ *            column address applies.
+ * @page:     The page address associated with this command code, or -1 if no
+ *            page address applies.
+ */
+static void mil_cmdfunc(struct mtd_info *mtd,
+					unsigned command, int column, int page)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc cmdfunc] command: 0x%02x, "
+		"column: 0x%04x, page: 0x%06x\n", command, column, page);
+
+	add_event("Entering mil_cmdfunc", 1);
+
+	/* Record the command and the fact that it hasn't yet been sent. */
+
+	this->command        = command;
+	this->command_is_new = true;
+
+	/*
+	 * Process the command code.
+	 *
+	 * Note the default case to trap unrecognized codes. Thus, every command
+	 * we support must have a case here, even if we don't have to do any
+	 * pre-processing work. If the HIL changes and starts sending commands
+	 * we haven't explicitly implemented, this will warn us.
+	 */
+
+	switch (command) {
+
+	case NAND_CMD_READ0:
+		add_event("NAND_CMD_READ0", 0);
+		/*
+		 * After calling this function to send the command and
+		 * addresses, the HIL will call ecc.read_page() or
+		 * ecc.read_page_raw() to collect the data.
+		 *
+		 * The column address from the HIL is always zero. The only
+		 * information we need to keep from this call is the page
+		 * address.
+		 */
+		this->page_address = page;
+		break;
+
+	case NAND_CMD_STATUS:
+		add_event("NAND_CMD_STATUS", 0);
+		/*
+		 * After calling this function to send the command, the HIL
+		 * will call read_byte() once to collect the status.
+		 */
+		break;
+
+	case NAND_CMD_READID:
+		add_event("NAND_CMD_READID", 0);
+		/*
+		 * After calling this function to send the command, the HIL
+		 * will call read_byte() repeatedly to collect ID bytes.
+		 */
+		break;
+
+	case NAND_CMD_RESET:
+		add_event("NAND_CMD_RESET", 0);
+		mal_reset(this, this->current_chip);
+		break;
+
+	default:
+		dev_emerg(this->dev, "Unsupported NAND Flash command code: "
+							"0x%02x\n", command);
+		BUG();
+		break;
+
+	}
+
+	add_event("Exiting mil_cmdfunc", -1);
+
+}
+
+/**
+ * mil_waitfunc() - MTD Interface waifunc()
+ *
+ * This function blocks until the current chip is ready and then returns the
+ * contents of the chip's status register. The HIL only calls this function
+ * after starting an erase operation.
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ */
+static int mil_waitfunc(struct mtd_info *mtd, struct nand_chip *nand)
+{
+	int                  status;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc waitfunc]\n");
+
+	add_event("Entering mil_waitfunc", 1);
+
+	/* Wait for the NFC to finish. */
+
+	nfc_util_wait_for_the_nfc(this, true);
+
+	/* Get the status. */
+
+	status = mal_get_status(this, this->current_chip);
+
+	add_event("Exiting mil_waitfunc", -1);
+
+	return status;
+
+}
+
+/**
+ * mil_read_byte() - MTD Interface read_byte().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+	uint8_t              byte = 0;
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	add_event("Entering mil_read_byte", 1);
+
+	/*
+	 * The command sent by the HIL before it called this function determines
+	 * how we get the byte we're going to return.
+	 */
+
+	switch (this->command) {
+
+	case NAND_CMD_STATUS:
+		add_event("NAND_CMD_STATUS", 0);
+		byte = mal_get_status(this, this->current_chip);
+		break;
+
+	case NAND_CMD_READID:
+		add_event("NAND_CMD_READID", 0);
+
+		/*
+		 * Check if the command is new. If so, then the HIL just
+		 * recently called cmdfunc(), so the current chip isn't selected
+		 * and the command hasn't been sent to the chip.
+		 */
+
+		if (this->command_is_new) {
+			add_event("Sending the \"Read ID\" command...", 0);
+			this->nfc->select_chip(this, this->current_chip);
+			nfc_util_send_cmd_and_addrs(this,
+							NAND_CMD_READID, 0, -1);
+			this->command_is_new = false;
+		}
+
+		/* Read the ID byte. */
+
+		add_event("Reading the ID byte...", 0);
+
+		byte = this->nfc->read_cycle(this);
+
+		break;
+
+	default:
+		dev_emerg(this->dev, "Unsupported NAND Flash command code: "
+						"0x%02x\n", this->command);
+		BUG();
+		break;
+
+	}
+
+	DEBUG(MTD_DEBUG_LEVEL2,
+			"[imx_nfc read_byte] Returning: 0x%02x\n", byte);
+
+	add_event("Exiting mil_read_byte", -1);
+
+	return byte;
+
+}
+
+/**
+ * mil_read_word() - MTD Interface read_word().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static uint16_t mil_read_word(struct mtd_info *mtd)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+	return 0;
+}
+
+/**
+ * mil_read_buf() - MTD Interface read_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The destination buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_write_buf() - MTD Interface write_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The source buffer.
+ * @len:  The number of bytes to read.
+ */
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_verify_buf() - MTD Interface verify_buf().
+ *
+ * @mtd:  A pointer to the owning MTD.
+ * @buf:  The destination buffer.
+ * @len:  The number of bytes to read.
+ */
+static int mil_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+	return 0;
+}
+
+/**
+ * mil_ecc_hwctl() - MTD Interface ecc.hwctl().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @mode:  The ECC mode.
+ */
+static void mil_ecc_hwctl(struct mtd_info *mtd, int mode)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_ecc_calculate() - MTD Interface ecc.calculate().
+ *
+ * @mtd:       A pointer to the owning MTD.
+ * @dat:       A pointer to the source data.
+ * @ecc_code:  A pointer to a buffer that will receive the resulting ECC.
+ */
+static int mil_ecc_calculate(struct mtd_info *mtd,
+					const uint8_t *dat, uint8_t *ecc_code)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+	return 0;
+}
+
+/**
+ * mil_ecc_correct() - MTD Interface ecc.correct().
+ *
+ * @mtd:       A pointer to the owning MTD.
+ * @dat:       A pointer to the source data.
+ * @read_ecc:  A pointer to the ECC that was read from the medium.
+ * @calc_ecc:  A pointer to the ECC that was calculated for the source data.
+ */
+static int mil_ecc_correct(struct mtd_info *mtd,
+			uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+	return 0;
+}
+
+/**
+ * mil_ecc_read_page() - MTD Interface ecc.read_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the destination buffer.
+ */
+static int mil_ecc_read_page(struct mtd_info *mtd,
+					struct nand_chip *nand, uint8_t *buf)
+{
+	int                  ecc_status;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_page]\n");
+
+	add_event("Entering mil_ecc_read_page", 1);
+
+	/* Read the page. */
+
+	ecc_status =
+		mal_read_a_page(this, true, this->current_chip,
+					this->page_address, buf, nand->oob_poi);
+
+	/* Propagate ECC information. */
+
+	if (ecc_status < 0) {
+		add_event("ECC Failure", 0);
+		mtd->ecc_stats.failed++;
+	} else if (ecc_status > 0) {
+		add_event("ECC Corrections", 0);
+		mtd->ecc_stats.corrected += ecc_status;
+	}
+
+	add_event("Exiting mil_ecc_read_page", -1);
+
+	return 0;
+
+}
+
+/**
+ * mil_ecc_read_page_raw() - MTD Interface ecc.read_page_raw().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the destination buffer.
+ */
+static int mil_ecc_read_page_raw(struct mtd_info *mtd,
+					struct nand_chip *nand, uint8_t *buf)
+{
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_page_raw]\n");
+
+	add_event("Entering mil_ecc_read_page_raw", 1);
+
+	mal_read_a_page(this, false, this->current_chip,
+					this->page_address, buf, nand->oob_poi);
+
+	add_event("Exiting mil_ecc_read_page_raw", -1);
+
+	return 0;
+
+}
+
+/**
+ * mil_ecc_write_page() - MTD Interface ecc.write_page().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the source buffer.
+ */
+static void mil_ecc_write_page(struct mtd_info *mtd,
+				struct nand_chip *nand, const uint8_t *buf)
+{
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_ecc_write_page_raw() - MTD Interface ecc.write_page_raw().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @buf:   A pointer to the source buffer.
+ */
+static void mil_ecc_write_page_raw(struct mtd_info *mtd,
+				struct nand_chip *nand, const uint8_t *buf)
+{
+	struct imx_nfc_data  *this = nand->priv;
+	unimplemented(this, __func__);
+}
+
+/**
+ * mil_write_page() - MTD Interface ecc.write_page().
+ *
+ * @mtd:     A pointer to the owning MTD.
+ * @nand:    A pointer to the owning NAND Flash MTD.
+ * @buf:     A pointer to the source buffer.
+ * @page:    The page number to write.
+ * @cached:  Indicates cached programming (ignored).
+ * @raw:     Indicates not to use ECC.
+ */
+static int mil_write_page(struct mtd_info *mtd,
+		struct nand_chip *nand, const uint8_t *buf,
+		int page, int cached, int raw)
+{
+	int                  return_value;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc write_page]\n");
+
+	add_event("Entering mil_write_page", 1);
+
+	return_value = mal_write_a_page(this, !raw,
+				this->current_chip, page, buf, nand->oob_poi);
+
+	add_event("Exiting mil_write_page", -1);
+
+	return return_value;
+
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface read_oob().
+ *
+ * @mtd:     A pointer to the owning MTD.
+ * @nand:    A pointer to the owning NAND Flash MTD.
+ * @page:    The page number to read.
+ * @sndcmd:  Indicates this function should send a command to the chip before
+ *           reading the out-of-band bytes. This is only false for small page
+ *           chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+							int page, int sndcmd)
+{
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_oob] "
+		"page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No");
+
+	add_event("Entering mil_ecc_read_oob", 1);
+
+	mal_read_a_page(this, false,
+				this->current_chip, page, 0, nand->oob_poi);
+
+	add_event("Exiting mil_ecc_read_oob", -1);
+
+	/*
+	 * Return true, indicating that the next call to this function must send
+	 * a command.
+	 */
+
+	return true;
+
+}
+
+/**
+ * mil_ecc_write_oob() - MTD Interface write_oob().
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @nand:  A pointer to the owning NAND Flash MTD.
+ * @page:  The page number to write.
+ */
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+					struct nand_chip *nand, int page)
+{
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_write_oob] page: 0x%06x\n", page);
+
+	/*
+	 * There are fundamental incompatibilities between the i.MX NFC and the
+	 * NAND Flash MTD model that make it essentially impossible to write the
+	 * out-of-band bytes.
+	 */
+
+	dev_emerg(this->dev, "This driver doesn't support writing the OOB\n");
+	WARN_ON(1);
+
+	/* Return status. */
+
+	return -EIO;
+
+}
+
+/**
+ * mil_erase_cmd() - MTD Interface erase_cmd().
+ *
+ * We set the erase_cmd pointer in struct nand_chip to point to this function.
+ * Thus, the HIL will call here for all erase operations.
+ *
+ * Strictly speaking, since the erase_cmd pointer is marked "Internal," we
+ * shouldn't be doing this. However, the only reason the HIL uses that pointer
+ * is to install a different function for erasing conventional NAND Flash or AND
+ * Flash. Since AND Flash is obsolete and we don't support it, this isn't
+ * important.
+ *
+ * Furthermore, to cleanly implement interleaving (which is critical to speeding
+ * up erase operations), we want to "hook into" the operation at the highest
+ * semantic level possible. If we don't hook this function, then the only way
+ * we'll know that an erase is happening is when the HIL calls cmdfunc() with
+ * an erase command. Implementing interleaving at that level is roughly a
+ * billion times less desirable.
+ *
+ * This function does *not* wait for the operation to finish. The HIL will call
+ * waitfunc() later to wait for the operation to finish.
+ *
+ * @mtd:   A pointer to the owning MTD.
+ * @page:  A page address that identifies the block to erase.
+ */
+static void mil_erase_cmd(struct mtd_info *mtd, int page)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc erase_cmd] page: 0x%06x\n", page);
+
+	add_event("Entering mil_erase_cmd", 1);
+
+	mal_erase_a_block(this, this->current_chip, page);
+
+	add_event("Exiting mil_erase_cmd", -1);
+
+}
+
+/**
+ * mil_block_bad() - MTD Interface block_bad().
+ *
+ * @mtd:      A pointer to the owning MTD.
+ * @ofs:      The offset of the block of interest, from the start of the medium.
+ * @getchip:  Indicates this function must acquire the MTD before using it.
+ */
+#if 0
+
+/* TODO: Finish this function and plug it in. */
+
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+	unsigned int         chip;
+	unsigned int         page;
+	int                  return_value;
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc block_bad] page: 0x%06x\n", page);
+
+	add_event("Entering mil_block_bad", 1);
+
+	/* Compute the logical chip number that contains the given offset. */
+
+	chip = (unsigned int) (ofs >> nand->chip_shift);
+
+	/* Compute the logical page address within the logical chip. */
+
+	page = ((unsigned int) (ofs >> nand->page_shift)) & nand->pagemask;
+
+	/* Check if the block is bad. */
+
+	return_value = mal_is_block_bad(this, chip, page);
+
+	if (return_value)
+		add_event("Bad block", 0);
+
+	/* Return. */
+
+	add_event("Exiting mil_block_bad", -1);
+
+	return return_value;
+
+}
+#endif
+
+/**
+ * mil_scan_bbt() - MTD Interface scan_bbt().
+ *
+ * The HIL calls this function once, when it initializes the NAND Flash MTD.
+ *
+ * Nominally, the purpose of this function is to look for or create the bad
+ * block table. In fact, since the HIL calls this function at the very end of
+ * the initialization process started by nand_scan(), and the HIL doesn't have a
+ * more formal mechanism, everyone "hooks" this function to continue the
+ * initialization process.
+ *
+ * At this point, the physical NAND Flash chips have been identified and
+ * counted, so we know the physical geometry. This enables us to make some
+ * important configuration decisions.
+ *
+ * The return value of this function propogates directly back to this driver's
+ * call to nand_scan(). Anything other than zero will cause this driver to
+ * tear everything down and declare failure.
+ *
+ * @mtd:  A pointer to the owning MTD.
+ */
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip     *nand = mtd->priv;
+	struct imx_nfc_data  *this = nand->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc scan_bbt] \n");
+
+	add_event("Entering mil_scan_bbt", 1);
+
+	/*
+	 * We replace the erase_cmd() function that the MTD NAND Flash system
+	 * has installed with our own. See mil_erase_cmd() for the reasons.
+	 */
+
+	nand->erase_cmd = mil_erase_cmd;
+
+	/*
+	 * Tell MTD users that the out-of-band area can't be written.
+	 *
+	 * This flag is not part of the standard kernel source tree. It comes
+	 * from a patch that touches both MTD and JFFS2.
+	 *
+	 * The problem is that, without this patch, JFFS2 believes it can write
+	 * the data area and the out-of-band area separately. This is wrong for
+	 * two reasons:
+	 *
+	 *     1)  Our NFC distributes out-of-band bytes throughout the page,
+	 *         intermingled with the data, and covered by the same ECC.
+	 *         Thus, it's not possible to write the out-of-band bytes and
+	 *         data bytes separately.
+	 *
+	 *     2)  Large page (MLC) Flash chips don't support partial page
+	 *         writes. You must write the entire page at a time. Thus, even
+	 *         if our NFC didn't force you to write out-of-band and data
+	 *         bytes together, it would *still* be a bad idea to do
+	 *         otherwise.
+	 */
+
+	mtd->flags &= ~MTD_OOB_WRITEABLE;
+
+	/* Set up geometry. */
+
+	mal_set_geometry(this);
+
+	/* We use the reference implementation for bad block management. */
+
+	add_event("Exiting mil_scan_bbt", -1);
+
+	return nand_scan_bbt(mtd, nand->badblock_pattern);
+
+}
+
+/**
+ * parse_bool_param() - Parses the value of a boolean parameter string.
+ *
+ * @s: The string to parse.
+ */
+static int parse_bool_param(const char *s)
+{
+
+	if (!strcmp(s, "1") || !strcmp(s, "on") ||
+				!strcmp(s, "yes") ||	!strcmp(s, "true")) {
+		return 1;
+	} else if (!strcmp(s, "0") || !strcmp(s, "off") ||
+				!strcmp(s, "no") || !strcmp(s, "false")) {
+		return 0;
+	} else {
+		return -1;
+	}
+
+}
+
+/**
+ * set_module_enable() - Controls whether this driver is enabled.
+ *
+ * Note that this state can be controlled from the command line. Disabling this
+ * driver is sometimes useful for debugging.
+ *
+ * @s:   The new value of the parameter.
+ * @kp:  The owning kernel parameter.
+ */
+static int set_module_enable(const char *s, struct kernel_param *kp)
+{
+
+	switch (parse_bool_param(s)) {
+
+	case 1:
+		imx_nfc_module_enable = true;
+		break;
+
+	case 0:
+		imx_nfc_module_enable = false;
+		break;
+
+	default:
+		return -EINVAL;
+		break;
+
+	}
+
+	return 0;
+
+}
+
+/**
+ * get_module_enable() - Indicates whether this driver is enabled.
+ *
+ * @p:   A pointer to a (small) buffer that will receive the response.
+ * @kp:  The owning kernel parameter.
+ */
+static int get_module_enable(char *p, struct kernel_param *kp)
+{
+	p[0] = imx_nfc_module_enable ? '1' : '0';
+	p[1] = 0;
+	return 1;
+}
+
+#ifdef EVENT_REPORTING
+
+/**
+ * set_module_report_events() - Controls whether this driver reports events.
+ *
+ * @s:   The new value of the parameter.
+ * @kp:  The owning kernel parameter.
+ */
+static int set_module_report_events(const char *s, struct kernel_param *kp)
+{
+
+	switch (parse_bool_param(s)) {
+
+	case 1:
+		imx_nfc_module_report_events = true;
+		break;
+
+	case 0:
+		imx_nfc_module_report_events = false;
+		reset_event_trace();
+		break;
+
+	default:
+		return -EINVAL;
+		break;
+
+	}
+
+	return 0;
+
+}
+
+/**
+ * get_module_report_events() - Indicates whether the driver reports events.
+ *
+ * @p:   A pointer to a (small) buffer that will receive the response.
+ * @kp:  The owning kernel parameter.
+ */
+static int get_module_report_events(char *p, struct kernel_param *kp)
+{
+	p[0] = imx_nfc_module_report_events ? '1' : '0';
+	p[1] = 0;
+	return 1;
+}
+
+/**
+ * set_module_dump_events() - Forces the driver to dump current events.
+ *
+ * @s:   The new value of the parameter.
+ * @kp:  The owning kernel parameter.
+ */
+static int set_module_dump_events(const char *s, struct kernel_param *kp)
+{
+	dump_event_trace();
+	return 0;
+}
+
+#endif /*EVENT_REPORTING*/
+
+/**
+ * set_module_interleave_override() - Controls the interleave override.
+ *
+ * @s:   The new value of the parameter.
+ * @kp:  The owning kernel parameter.
+ */
+static int set_module_interleave_override(const char *s,
+							struct kernel_param *kp)
+{
+
+	if      (!strcmp(s, "-1"))
+		imx_nfc_module_interleave_override = NEVER;
+	else if (!strcmp(s, "0"))
+		imx_nfc_module_interleave_override = DRIVER_CHOICE;
+	else if (!strcmp(s, "1"))
+		imx_nfc_module_interleave_override = ALWAYS;
+	else
+		return -EINVAL;
+
+	return 0;
+
+}
+
+/**
+ * get_module_interleave_override() - Indicates the interleave override state.
+ *
+ * @p:   A pointer to a (small) buffer that will receive the response.
+ * @kp:  The owning kernel parameter.
+ */
+static int get_module_interleave_override(char *p, struct kernel_param *kp)
+{
+	return sprintf(p, "%d", imx_nfc_module_interleave_override);
+}
+
+/**
+ * set_force_bytewise_copy() - Controls forced bytewise copy from/to the NFC.
+ *
+ * @s:   The new value of the parameter.
+ * @kp:  The owning kernel parameter.
+ */
+static int set_module_force_bytewise_copy(const char *s,
+							struct kernel_param *kp)
+{
+
+	switch (parse_bool_param(s)) {
+
+	case 1:
+		imx_nfc_module_force_bytewise_copy = true;
+		break;
+
+	case 0:
+		imx_nfc_module_force_bytewise_copy = false;
+		break;
+
+	default:
+		return -EINVAL;
+		break;
+
+	}
+
+	return 0;
+
+}
+
+/**
+ * get_force_bytewise_copy() - Indicates whether bytewise copy is being forced.
+ *
+ * @p:   A pointer to a (small) buffer that will receive the response.
+ * @kp:  The owning kernel parameter.
+ */
+static int get_module_force_bytewise_copy(char *p, struct kernel_param *kp)
+{
+	p[0] = imx_nfc_module_force_bytewise_copy ? '1' : '0';
+	p[1] = 0;
+	return 1;
+}
+
+/* Module attributes that appear in sysfs. */
+
+module_param_call(enable, set_module_enable, get_module_enable, 0, 0444);
+MODULE_PARM_DESC(enable, "enables/disables probing");
+
+#ifdef EVENT_REPORTING
+module_param_call(report_events,
+		set_module_report_events, get_module_report_events, 0, 0644);
+MODULE_PARM_DESC(report_events, "enables/disables event reporting");
+
+module_param_call(dump_events, set_module_dump_events, 0, 0, 0644);
+MODULE_PARM_DESC(dump_events, "forces current event dump");
+#endif
+
+module_param_call(interleave_override, set_module_interleave_override,
+				get_module_interleave_override, 0, 0444);
+MODULE_PARM_DESC(interleave_override, "overrides interleaving choice");
+
+module_param_call(force_bytewise_copy, set_module_force_bytewise_copy,
+				get_module_force_bytewise_copy, 0, 0644);
+MODULE_PARM_DESC(force_bytewise_copy, "forces bytewise copy from/to NFC");
+
+/**
+ * show_device_platform_info() - Shows the device's platform information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_platform_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                           o = 0;
+	unsigned int                  i;
+	void                          *buffer_base;
+	void                          *primary_base;
+	void                          *secondary_base;
+	unsigned int                  interrupt_number;
+	struct resource               *r;
+	struct imx_nfc_data           *this  = dev_get_drvdata(dev);
+	struct platform_device        *pdev  = this->pdev;
+	struct imx_nfc_platform_data  *pdata = this->pdata;
+	struct mtd_partition          *partition;
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					IMX_NFC_BUFFERS_ADDR_RES_NAME);
+
+	buffer_base = (void *) r->start;
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME);
+
+	primary_base = (void *) r->start;
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME);
+
+	secondary_base = (void *) r->start;
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+					IMX_NFC_INTERRUPT_RES_NAME);
+
+	interrupt_number = r->start;
+
+	o += sprintf(buf,
+		"NFC Major Version       : %u\n"
+		"NFC Minor Version       : %u\n"
+		"Force CE                : %s\n"
+		"Target Cycle in ns      : %u\n"
+		"Clock Name              : %s\n"
+		"Interleave              : %s\n"
+		"Buffer Base             : 0x%p\n"
+		"Primary Registers Base  : 0x%p\n"
+		"Secondary Registers Base: 0x%p\n"
+		"Interrupt Number        : %u\n"
+		,
+		pdata->nfc_major_version,
+		pdata->nfc_minor_version,
+		pdata->force_ce ? "Yes" : "No",
+		pdata->target_cycle_in_ns,
+		pdata->clock_name,
+		pdata->interleave ? "Yes" : "No",
+		buffer_base,
+		primary_base,
+		secondary_base,
+		interrupt_number
+		);
+
+	#ifdef CONFIG_MTD_PARTITIONS
+
+		o += sprintf(buf + o,
+			"Partition Count         : %u\n"
+			,
+			pdata->partition_count
+		);
+
+		/* Loop over partitions. */
+
+		for (i = 0; i < pdata->partition_count; i++) {
+
+			partition = pdata->partitions + i;
+
+			o += sprintf(buf+o, "  [%d]\n", i);
+			o += sprintf(buf+o, "  Name  : %s\n", partition->name);
+
+			switch (partition->offset) {
+
+			case MTDPART_OFS_NXTBLK:
+				o += sprintf(buf+o, "  Offset: "
+							"MTDPART_OFS_NXTBLK\n");
+				break;
+			case MTDPART_OFS_APPEND:
+				o += sprintf(buf+o, "  Offset: "
+							"MTDPART_OFS_APPEND\n");
+				break;
+			default:
+				o += sprintf(buf+o, "  Offset: %u (%u MiB)\n",
+					partition->offset,
+					partition->offset / (1024 * 1024));
+				break;
+
+			}
+
+			if (partition->size == MTDPART_SIZ_FULL) {
+				o += sprintf(buf+o, "  Size  : "
+							"MTDPART_SIZ_FULL\n");
+			} else {
+				o += sprintf(buf+o, "  Size  : %u (%u MiB)\n",
+					partition->size,
+					partition->size / (1024 * 1024));
+			}
+
+		}
+
+	#endif
+
+	return o;
+
+}
+
+/**
+ * show_device_physical_geometry() - Shows the physical Flash device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_physical_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data       *this     = dev_get_drvdata(dev);
+	struct physical_geometry  *physical = &this->physical_geometry;
+
+	return sprintf(buf,
+		"Chip Count             : %u\n"
+		"Chip Size in Bytes     : %llu\n"
+		"Block Size in Bytes    : %u\n"
+		"Page Data Size in Bytes: %u\n"
+		"Page OOB Size in Bytes : %u\n"
+		,
+		physical->chip_count,
+		physical->chip_size,
+		physical->block_size,
+		physical->page_data_size,
+		physical->page_oob_size
+	);
+
+}
+
+/**
+ * show_device_nfc_info() - Shows the NFC-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	unsigned long        parent_clock_rate_in_hz;
+	unsigned long        clock_rate_in_hz;
+	struct clk           *parent_clock;
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+	struct nfc_hal       *nfc  = this->nfc;
+
+	parent_clock            = clk_get_parent(this->clock);
+	parent_clock_rate_in_hz = clk_get_rate(parent_clock);
+	clock_rate_in_hz        = clk_get_rate(this->clock);
+
+	return sprintf(buf,
+		"Major Version           : %u\n"
+		"Minor Version           : %u\n"
+		"Max Chip Count          : %u\n"
+		"Max Buffer Count        : %u\n"
+		"Spare Buffer Stride     : %u\n"
+		"Has Secondary Registers : %s\n"
+		"Can Be Symmetric        : %s\n"
+		"Exposes Ready/Busy      : %s\n"
+		"Parent Clock Rate in Hz : %lu\n"
+		"Clock Rate in Hz        : %lu\n"
+		"Symmetric Clock         : %s\n"
+		,
+		nfc->major_version,
+		nfc->minor_version,
+		nfc->max_chip_count,
+		nfc->max_buffer_count,
+		nfc->spare_buf_stride,
+		nfc->has_secondary_regs ? "Yes" : "No",
+		nfc->can_be_symmetric ? "Yes" : "No",
+		nfc->is_ready ? "Yes" : "No",
+		parent_clock_rate_in_hz,
+		clock_rate_in_hz,
+		this->nfc->get_symmetric(this) ? "Yes" : "No"
+	);
+
+}
+
+/**
+ * show_device_nfc_geometry() - Shows the NFC view of the device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_nfc_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	return sprintf(buf,
+		"Page Data Size in Bytes : %u\n"
+		"Page OOB Size in Bytes  : %u\n"
+		"ECC Algorithm           : %s\n"
+		"ECC Strength            : %u\n"
+		"Buffers in Use          : %u\n"
+		"Spare Buffer Size in Use: %u\n"
+		"Spare Buffer Spillover  : %u\n"
+		,
+		this->nfc_geometry->page_data_size,
+		this->nfc_geometry->page_oob_size,
+		this->nfc_geometry->ecc_algorithm,
+		this->nfc_geometry->ecc_strength,
+		this->nfc_geometry->buffer_count,
+		this->nfc_geometry->spare_buf_size,
+		this->nfc_geometry->spare_buf_spill
+	);
+
+}
+
+/**
+ * show_device_logical_geometry() - Shows the logical device geometry.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_logical_geometry(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data      *this    = dev_get_drvdata(dev);
+	struct logical_geometry  *logical = &this->logical_geometry;
+
+	return sprintf(buf,
+		"Chip Count             : %u\n"
+		"Chip Size in Bytes     : %u\n"
+		"Usable Size in Bytes   : %u\n"
+		"Block Size in Bytes    : %u\n"
+		"Page Data Size in Bytes: %u\n"
+		"Page OOB Size in Bytes : %u\n"
+		,
+		logical->chip_count,
+		logical->chip_size,
+		logical->usable_size,
+		logical->block_size,
+		logical->page_data_size,
+		logical->page_oob_size
+	);
+
+}
+
+/**
+ * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_nand_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct imx_nfc_data        *this = dev_get_drvdata(dev);
+	struct nand_chip           *nand = &this->nand;
+
+	o += sprintf(buf + o,
+		"Options              : 0x%08x\n"
+		"Chip Count           : %u\n"
+		"Chip Size            : %lu\n"
+		"Minimum Writable Size: %u\n"
+		"Page Shift           : %u\n"
+		"Page Mask            : 0x%x\n"
+		"Block Shift          : %u\n"
+		"BBT Block Shift      : %u\n"
+		"Chip Shift           : %u\n"
+		"Block Mark Offset    : %u\n"
+		"Cached Page Number   : %d\n"
+		,
+		nand->options,
+		nand->numchips,
+		nand->chipsize,
+		nand->subpagesize,
+		nand->page_shift,
+		nand->pagemask,
+		nand->phys_erase_shift,
+		nand->bbt_erase_shift,
+		nand->chip_shift,
+		nand->badblockpos,
+		nand->pagebuf
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count       : %u\n"
+		,
+		nand->ecc.layout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= nand->ecc.layout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				nand->ecc.layout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes  : %u\n"
+		,
+		nand->ecc.layout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < nand->ecc.layout->oobavail; i++) {
+
+		j += nand->ecc.layout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			nand->ecc.layout->oobfree[i].offset,
+			nand->ecc.layout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+ * show_device_mtd_info() - Shows the device's MTD-specific information.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_mtd_info(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                        o = 0;
+	unsigned int               i;
+	unsigned int               j;
+	static const unsigned int  columns = 8;
+	struct imx_nfc_data        *this = dev_get_drvdata(dev);
+	struct mtd_info            *mtd  = &this->mtd;
+
+	o += sprintf(buf + o,
+		"Name               : %s\n"
+		"Type               : %u\n"
+		"Flags              : 0x%08x\n"
+		"Size in Bytes      : %u\n"
+		"Erase Region Count : %d\n"
+		"Erase Size in Bytes: %u\n"
+		"Write Size in Bytes: %u\n"
+		"OOB Size in Bytes  : %u\n"
+		"Errors Corrected   : %u\n"
+		"Failed Reads       : %u\n"
+		"Bad Block Count    : %u\n"
+		"BBT Block Count    : %u\n"
+		,
+		mtd->name,
+		mtd->type,
+		mtd->flags,
+		mtd->size,
+		mtd->numeraseregions,
+		mtd->erasesize,
+		mtd->writesize,
+		mtd->oobsize,
+		mtd->ecc_stats.corrected,
+		mtd->ecc_stats.failed,
+		mtd->ecc_stats.badblocks,
+		mtd->ecc_stats.bbtblocks
+	);
+
+	o += sprintf(buf + o,
+		"ECC Byte Count     : %u\n"
+		,
+		mtd->ecclayout->eccbytes
+	);
+
+	/* Loop over rows. */
+
+	for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) {
+
+		/* Loop over columns within rows. */
+
+		for (j = 0; j < columns; j++) {
+
+			if (((i * columns) + j) >= mtd->ecclayout->eccbytes)
+				break;
+
+			o += sprintf(buf + o, " %3u",
+				mtd->ecclayout->eccpos[(i * columns) + j]);
+
+		}
+
+		o += sprintf(buf + o, "\n");
+
+	}
+
+	o += sprintf(buf + o,
+		"OOB Available Bytes: %u\n"
+		,
+		mtd->ecclayout->oobavail
+	);
+
+	j = 0;
+
+	for (i = 0; j < mtd->ecclayout->oobavail; i++) {
+
+		j += mtd->ecclayout->oobfree[i].length;
+
+		o += sprintf(buf + o,
+			"  [%3u, %2u]\n"
+			,
+			mtd->ecclayout->oobfree[i].offset,
+			mtd->ecclayout->oobfree[i].length
+		);
+
+	}
+
+	return o;
+
+}
+
+/**
+ * show_device_bbt_pages() - Shows the pages in which BBT's appear.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_bbt_pages(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	int                  o = 0;
+	unsigned int         i;
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+	struct nand_chip     *nand = &this->nand;
+
+	/* Loop over main BBT pages. */
+
+	if (nand->bbt_td)
+		for (i = 0; i < NAND_MAX_CHIPS; i++)
+			o += sprintf(buf + o, "%d: 0x%08x\n",
+						i, nand->bbt_td->pages[i]);
+
+	/* Loop over mirror BBT pages. */
+
+	if (nand->bbt_md)
+		for (i = 0; i < NAND_MAX_CHIPS; i++)
+			o += sprintf(buf + o, "%d: 0x%08x\n",
+						i, nand->bbt_md->pages[i]);
+
+	return o;
+
+}
+
+/**
+ * show_device_cycle_in_ns() - Shows the device's cycle in ns.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_cycle_in_ns(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+	return sprintf(buf, "%u\n", get_cycle_in_ns(this));
+}
+
+/**
+ * store_device_cycle_in_ns() - Sets the device's cycle in ns.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_cycle_in_ns(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	int                  error;
+	unsigned long        new_cycle_in_ns;
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the new cycle period. */
+
+	if (strict_strtoul(buf, 0, &new_cycle_in_ns))
+		return -EINVAL;
+
+	/* Try to implement the new cycle period. */
+
+	error = this->nfc->set_closest_cycle(this, new_cycle_in_ns);
+
+	if (error)
+		return -EINVAL;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * show_device_interrupt_override() - Shows the device's interrupt override.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_interrupt_override(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	switch (this->interrupt_override) {
+
+	case NEVER:
+		return sprintf(buf, "-1\n");
+		break;
+
+	case DRIVER_CHOICE:
+		return sprintf(buf, "0\n");
+		break;
+
+	case ALWAYS:
+		return sprintf(buf, "1\n");
+		break;
+
+	default:
+		return sprintf(buf, "?\n");
+		break;
+
+	}
+
+}
+
+/**
+ * store_device_interrupt_override() - Sets the device's interrupt override.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_interrupt_override(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	if      (!strcmp(buf, "-1"))
+		this->interrupt_override = NEVER;
+	else if (!strcmp(buf, "0"))
+		this->interrupt_override = DRIVER_CHOICE;
+	else if (!strcmp(buf, "1"))
+		this->interrupt_override = ALWAYS;
+	else
+		return -EINVAL;
+
+	return size;
+
+}
+
+/**
+ * show_device_auto_op_override() - Shows the device's automatic op override.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_auto_op_override(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	switch (this->auto_op_override) {
+
+	case NEVER:
+		return sprintf(buf, "-1\n");
+		break;
+
+	case DRIVER_CHOICE:
+		return sprintf(buf, "0\n");
+		break;
+
+	case ALWAYS:
+		return sprintf(buf, "1\n");
+		break;
+
+	default:
+		return sprintf(buf, "?\n");
+		break;
+
+	}
+
+}
+
+/**
+ * store_device_auto_op_override() - Sets the device's automatic op override.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_auto_op_override(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	if      (!strcmp(buf, "-1"))
+		this->auto_op_override = NEVER;
+	else if (!strcmp(buf, "0"))
+		this->auto_op_override = DRIVER_CHOICE;
+	else if (!strcmp(buf, "1"))
+		this->auto_op_override = ALWAYS;
+	else
+		return -EINVAL;
+
+	return size;
+
+}
+
+/**
+ * show_device_inject_ecc_error() - Shows the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_inject_ecc_error(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", this->inject_ecc_error);
+
+}
+
+/**
+ * store_device_inject_ecc_error() - Sets the device's error injection flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_inject_ecc_error(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	unsigned long        new_inject_ecc_error;
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	/* Look for nonsense. */
+
+	if (!size)
+		return -EINVAL;
+
+	/* Try to understand the new cycle period. */
+
+	if (strict_strtol(buf, 0, &new_inject_ecc_error))
+		return -EINVAL;
+
+	/* Store the value. */
+
+	this->inject_ecc_error = new_inject_ecc_error;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/**
+ * store_device_invalidate_page_cache() - Invalidates the device's page cache.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_invalidate_page_cache(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct imx_nfc_data  *this = dev_get_drvdata(dev);
+
+	/* Invalidate the page cache. */
+
+	this->nand.pagebuf = -1;
+
+	/* Return success. */
+
+	return size;
+
+}
+
+/* Device attributes that appear in sysfs. */
+
+static DEVICE_ATTR(platform_info    , 0444, show_device_platform_info    , 0);
+static DEVICE_ATTR(physical_geometry, 0444, show_device_physical_geometry, 0);
+static DEVICE_ATTR(nfc_info         , 0444, show_device_nfc_info         , 0);
+static DEVICE_ATTR(nfc_geometry     , 0444, show_device_nfc_geometry     , 0);
+static DEVICE_ATTR(logical_geometry , 0444, show_device_logical_geometry , 0);
+static DEVICE_ATTR(mtd_nand_info    , 0444, show_device_mtd_nand_info    , 0);
+static DEVICE_ATTR(mtd_info         , 0444, show_device_mtd_info         , 0);
+static DEVICE_ATTR(bbt_pages        , 0444, show_device_bbt_pages        , 0);
+
+static DEVICE_ATTR(cycle_in_ns, 0644,
+	show_device_cycle_in_ns, store_device_cycle_in_ns);
+
+static DEVICE_ATTR(interrupt_override, 0644,
+	show_device_interrupt_override, store_device_interrupt_override);
+
+static DEVICE_ATTR(auto_op_override, 0644,
+	show_device_auto_op_override, store_device_auto_op_override);
+
+static DEVICE_ATTR(inject_ecc_error, 0644,
+	show_device_inject_ecc_error, store_device_inject_ecc_error);
+
+static DEVICE_ATTR(invalidate_page_cache, 0644,
+	0, store_device_invalidate_page_cache);
+
+static struct device_attribute *device_attributes[] = {
+	&dev_attr_platform_info,
+	&dev_attr_physical_geometry,
+	&dev_attr_nfc_info,
+	&dev_attr_nfc_geometry,
+	&dev_attr_logical_geometry,
+	&dev_attr_mtd_nand_info,
+	&dev_attr_mtd_info,
+	&dev_attr_bbt_pages,
+	&dev_attr_cycle_in_ns,
+	&dev_attr_interrupt_override,
+	&dev_attr_auto_op_override,
+	&dev_attr_inject_ecc_error,
+	&dev_attr_invalidate_page_cache,
+};
+
+/**
+ * validate_the_platform() - Validates information about the platform.
+ *
+ * Note that this function doesn't validate the NFC version. That's done when
+ * the probing process attempts to configure for the specific hardware version.
+ *
+ * @pdev:	A pointer to the platform device.
+ */
+static int validate_the_platform(struct platform_device *pdev)
+{
+	struct device                 *dev   = &pdev->dev;
+	struct imx_nfc_platform_data  *pdata = pdev->dev.platform_data;
+
+	/* Validate the clock name. */
+
+	if (!pdata->clock_name) {
+		dev_err(dev, "No clock name\n");
+		return -ENXIO;
+	}
+
+	/* Validate the partitions. */
+
+	if ((pdata->partitions && (!pdata->partition_count)) ||
+			(!pdata->partitions && (pdata->partition_count))) {
+		dev_err(dev, "Bad partition data\n");
+		return -ENXIO;
+	}
+
+	/* Return success */
+
+	return 0;
+
+}
+
+/**
+ * set_up_the_nfc_hal() - Sets up for the specific NFC hardware HAL.
+ *
+ * @this:  Per-device data.
+ */
+static int set_up_the_nfc_hal(struct imx_nfc_data *this)
+{
+	unsigned int                  i;
+	struct nfc_hal                *p;
+	struct imx_nfc_platform_data  *pdata = this->pdata;
+
+	for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) {
+
+		p = nfc_hals[i];
+
+		/*
+		 * Restrict to 3.2 until others are fully implemented.
+		 *
+		 * TODO: Remove this.
+		 */
+
+		if ((p->major_version != 3) && (p->minor_version != 2))
+			continue;
+
+		if ((p->major_version == pdata->nfc_major_version) &&
+			(p->minor_version == pdata->nfc_minor_version)) {
+			this->nfc = p;
+			return 0;
+			break;
+		}
+
+	}
+
+	dev_err(this->dev, "Unkown NFC version %d.%d\n",
+			pdata->nfc_major_version, pdata->nfc_minor_version);
+
+	return !0;
+
+}
+
+/**
+ * acquire_resources() - Tries to acquire resources.
+ *
+ * @this:  Per-device data.
+ */
+static int acquire_resources(struct imx_nfc_data *this)
+{
+
+	int                           error  = 0;
+	struct platform_device        *pdev  = this->pdev;
+	struct device                 *dev   = this->dev;
+	struct imx_nfc_platform_data  *pdata = this->pdata;
+	struct resource               *r;
+
+	/* Find the buffers and map them. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+						IMX_NFC_BUFFERS_ADDR_RES_NAME);
+
+	if (!r) {
+		dev_err(dev, "Can't get '%s'\n", IMX_NFC_BUFFERS_ADDR_RES_NAME);
+		error = -ENXIO;
+		goto exit_buffers;
+	}
+
+	this->buffers = ioremap(r->start, r->end - r->start + 1);
+
+	if (!this->buffers) {
+		dev_err(dev, "Can't remap buffers\n");
+		error = -EIO;
+		goto exit_buffers;
+	}
+
+	/* Find the primary registers and map them. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME);
+
+	if (!r) {
+		dev_err(dev, "Can't get '%s'\n",
+					IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME);
+		error = -ENXIO;
+		goto exit_primary_registers;
+	}
+
+	this->primary_regs = ioremap(r->start, r->end - r->start + 1);
+
+	if (!this->primary_regs) {
+		dev_err(dev, "Can't remap the primary registers\n");
+		error = -EIO;
+		goto exit_primary_registers;
+	}
+
+	/* Check for secondary registers. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME);
+
+	if (r && !this->nfc->has_secondary_regs) {
+
+		dev_err(dev, "Resource '%s' should not be present\n",
+					IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME);
+		error = -ENXIO;
+		goto exit_secondary_registers;
+
+	}
+
+	if (this->nfc->has_secondary_regs) {
+
+		if (!r) {
+			dev_err(dev, "Can't get '%s'\n",
+					IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME);
+			error = -ENXIO;
+			goto exit_secondary_registers;
+		}
+
+		this->secondary_regs = ioremap(r->start, r->end - r->start + 1);
+
+		if (!this->secondary_regs) {
+			dev_err(dev,
+				"Can't remap the secondary registers\n");
+			error = -EIO;
+			goto exit_secondary_registers;
+		}
+
+	}
+
+	/* Find out what our interrupt is and try to own it. */
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+						IMX_NFC_INTERRUPT_RES_NAME);
+
+	if (!r) {
+		dev_err(dev, "Can't get '%s'\n", IMX_NFC_INTERRUPT_RES_NAME);
+		error = -ENXIO;
+		goto exit_irq;
+	}
+
+	this->interrupt = r->start;
+
+	error = request_irq(this->interrupt,
+				nfc_util_isr, 0, this->dev->bus_id, this);
+
+	if (error) {
+		dev_err(dev, "Can't own interrupt %d\n", this->interrupt);
+		goto exit_irq;
+	}
+
+	/* Find out the name of our clock and try to own it. */
+
+	this->clock = clk_get(dev, pdata->clock_name);
+
+	if (this->clock == ERR_PTR(-ENOENT)) {
+		dev_err(dev, "Can't get clock '%s'\n", pdata->clock_name);
+		error = -ENXIO;
+		goto exit_clock;
+	}
+
+	/* Return success. */
+
+	return 0;
+
+	/* Error return paths begin here. */
+
+exit_clock:
+	free_irq(this->interrupt, this);
+exit_irq:
+	if (this->secondary_regs)
+		iounmap(this->secondary_regs);
+exit_secondary_registers:
+	iounmap(this->primary_regs);
+exit_primary_registers:
+	iounmap(this->buffers);
+exit_buffers:
+	return error;
+
+}
+
+/**
+ * release_resources() - Releases resources.
+ *
+ * @this:  Per-device data.
+ */
+static void release_resources(struct imx_nfc_data *this)
+{
+
+	/* Release our clock. */
+
+	clk_disable(this->clock);
+	clk_put(this->clock);
+
+	/* Release our interrupt. */
+
+	free_irq(this->interrupt, this);
+
+	/* Release mapped memory. */
+
+	iounmap(this->buffers);
+	iounmap(this->primary_regs);
+	if (this->secondary_regs)
+		iounmap(this->secondary_regs);
+
+}
+
+/**
+ * register_with_mtd() - Registers this medium with MTD.
+ *
+ * @this:  Per-device data.
+ */
+static int register_with_mtd(struct imx_nfc_data *this)
+{
+	int                           error  = 0;
+	struct mtd_info               *mtd   = &this->mtd;
+	struct nand_chip              *nand  = &this->nand;
+	struct device                 *dev   = this->dev;
+	struct imx_nfc_platform_data  *pdata = this->pdata;
+
+	/* Link the MTD structures together, along with our own data. */
+
+	mtd->priv  = nand;
+	nand->priv = this;
+
+	/* Prepare the MTD structure. */
+
+	mtd->owner = THIS_MODULE;
+
+	/*
+	 * Signal Control Functions
+	 */
+
+	nand->cmd_ctrl = mil_cmd_ctrl;
+
+	/*
+	 * Chip Control Functions
+	 *
+	 * Not all of our NFC hardware versions expose Ready/Busy signals. For
+	 * versions that don't, the is_ready function pointer will be NULL. In
+	 * those cases, we leave the dev_ready member unassigned, which will
+	 * cause the HIL to use a reference implementation's algorithm to
+	 * discover when the hardware is ready.
+	 */
+
+	nand->select_chip = mil_select_chip;
+	nand->cmdfunc     = mil_cmdfunc;
+	nand->waitfunc    = mil_waitfunc;
+
+	if (this->nfc->is_ready)
+		nand->dev_ready = mil_dev_ready;
+
+	/*
+	 * Low-level I/O Functions
+	 */
+
+	nand->read_byte  = mil_read_byte;
+	nand->read_word  = mil_read_word;
+	nand->read_buf   = mil_read_buf;
+	nand->write_buf  = mil_write_buf;
+	nand->verify_buf = mil_verify_buf;
+
+	/*
+	 * ECC Control Functions
+	 */
+
+	nand->ecc.hwctl     = mil_ecc_hwctl;
+	nand->ecc.calculate = mil_ecc_calculate;
+	nand->ecc.correct   = mil_ecc_correct;
+
+	/*
+	 * ECC-Aware I/O Functions
+	 */
+
+	nand->ecc.read_page      = mil_ecc_read_page;
+	nand->ecc.read_page_raw  = mil_ecc_read_page_raw;
+	nand->ecc.write_page     = mil_ecc_write_page;
+	nand->ecc.write_page_raw = mil_ecc_write_page_raw;
+
+	/*
+	 * High-level I/O Functions
+	 */
+
+	nand->write_page    = mil_write_page;
+	nand->ecc.read_oob  = mil_ecc_read_oob;
+	nand->ecc.write_oob = mil_ecc_write_oob;
+
+	/*
+	 * Bad Block Marking Functions
+	 *
+	 * We want to use the reference block_bad and block_markbad
+	 * implementations, so we don't assign those members.
+	 */
+
+	nand->scan_bbt = mil_scan_bbt;
+
+	/*
+	 * Error Recovery Functions
+	 *
+	 * We don't fill in the errstat function pointer because it's optional
+	 * and we don't have a need for it.
+	 */
+
+	/*
+	 * Device Attributes
+	 *
+	 * We don't fill in the chip_delay member because we don't have a need
+	 * for it.
+	 *
+	 * We support only 8-bit Flash bus width.
+	 */
+
+	/*
+	 * ECC Attributes
+	 *
+	 * Members that aren't set here are configured by a version-specific
+	 * set_geometry() function.
+	 */
+
+	nand->ecc.mode    = NAND_ECC_HW;
+	nand->ecc.size    = NFC_MAIN_BUF_SIZE;
+	nand->ecc.prepad  = 0;
+	nand->ecc.postpad = 0;
+
+	/*
+	 * Bad Block Management Attributes
+	 *
+	 * We don't fill in the following attributes:
+	 *
+	 *     badblockpos
+	 *     bbt
+	 *     badblock_pattern
+	 *     bbt_erase_shift
+	 *
+	 * These attributes aren't hardware-specific, and the HIL makes fine
+	 * choices without our help.
+	 */
+
+	nand->options |= NAND_USE_FLASH_BBT;
+	nand->bbt_td   = &bbt_main_descriptor;
+	nand->bbt_md   = &bbt_mirror_descriptor;
+
+	/*
+	 * Device Control
+	 *
+	 * We don't fill in the controller attribute. In principle, we could set
+	 * up a structure to represent the controller. However, since it's
+	 * vanishingly improbable that we'll have more than one medium behind
+	 * the controller, it's not worth the effort. We let the HIL handle it.
+	 */
+
+	/*
+	 * Memory-mapped I/O
+	 *
+	 * We don't fill in the following attributes:
+	 *
+	 *     IO_ADDR_R
+	 *     IO_ADDR_W
+	 *
+	 * None of these are necessary because we don't have a memory-mapped
+	 * implementation.
+	 */
+
+	/*
+	 * Install a "fake" ECC layout.
+	 *
+	 * We'll be calling nand_scan() to do the final MTD setup. If we haven't
+	 * already chosen an ECC layout, then nand_scan() will choose one based
+	 * on the part geometry it discovers. Unfortunately, it doesn't make
+	 * good choices. It would be best if we could install the correct ECC
+	 * layout now, before we call nand_scan(). We can't do that because we
+	 * don't know the medium geometry yet. Here, we install a "fake" ECC
+	 * layout just to stop nand_scan() from trying to pick on for itself.
+	 * Later, in imx_nfc_scan_bbt(), when we know the medium geometry, we'll
+	 * install the correct choice.
+	 *
+	 * Of course, this tactic depends critically on nand_scan() not using
+	 * the fake layout before we can install a good one. This is in fact the
+	 * case.
+	 */
+
+	nand->ecc.layout = &nfc_geometry_512_16_RS_ECC1.mtd_layout;
+
+	/*
+	 * Ask the NAND Flash system to scan for chips.
+	 *
+	 * This will fill in reference implementations for all the members of
+	 * the MTD structures that we didn't set, and will make the medium fully
+	 * usable.
+	 */
+
+	error = nand_scan(mtd, this->nfc->max_chip_count);
+
+	if (error) {
+		dev_err(dev, "Chip scan failed\n");
+		error = -ENXIO;
+		goto exit_scan;
+	}
+
+	/* Register the MTD that represents the entire medium. */
+
+	mtd->name = "NAND Flash Medium";
+
+	add_mtd_device(mtd);
+
+	/* Check if we're doing partitions and register MTD's accordingly. */
+
+	#ifdef CONFIG_MTD_PARTITIONS
+
+		/*
+		 * Look for partition information. If we find some, install
+		 * them. Otherwise, use the partitions handed to us by the
+		 * platform.
+		 */
+
+		this->partition_count =
+			parse_mtd_partitions(mtd, partition_source_types,
+							&this->partitions, 0);
+
+		if ((this->partition_count <= 0) && (pdata->partitions)) {
+			this->partition_count = pdata->partition_count;
+			this->partitions      = pdata->partitions;
+		}
+
+		if (this->partitions)
+			add_mtd_partitions(mtd, this->partitions,
+							this->partition_count);
+
+	#endif
+
+	/* Return success. */
+
+	return 0;
+
+	/* Error return paths begin here. */
+
+exit_scan:
+	return error;
+
+}
+
+/**
+ * unregister_with_mtd() - Unregisters this medium with MTD.
+ *
+ * @this:  Per-device data.
+ */
+static void unregister_with_mtd(struct imx_nfc_data *this)
+{
+
+	/* Get MTD to let go. */
+
+	nand_release(&this->mtd);
+
+}
+
+/**
+ * manage_sysfs_files() - Creates/removes sysfs files for this device.
+ *
+ * @this:  Per-device data.
+ */
+static void manage_sysfs_files(struct imx_nfc_data *this, int create)
+{
+	int                      error;
+	unsigned int             i;
+	struct device_attribute  **attr;
+
+	for (i = 0, attr = device_attributes;
+			i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+		if (create) {
+			error = device_create_file(this->dev, *attr);
+			if (error) {
+				while (--attr >= device_attributes)
+					device_remove_file(this->dev, *attr);
+				return;
+			}
+		} else {
+			device_remove_file(this->dev, *attr);
+		}
+
+	}
+
+}
+
+/**
+ * imx_nfc_probe() - Probes for a device and, if possible, takes ownership.
+ *
+ * @pdev:  A pointer to the platform device.
+ */
+static int imx_nfc_probe(struct platform_device *pdev)
+{
+	int                           error  = 0;
+	char                          *symmetric_clock;
+	struct clk                    *parent_clock;
+	unsigned long                 parent_clock_rate_in_hz;
+	unsigned long                 parent_clock_rate_in_mhz;
+	unsigned long                 nfc_clock_rate_in_hz;
+	unsigned long                 nfc_clock_rate_in_mhz;
+	unsigned long                 clock_divisor;
+	unsigned long                 cycle_in_ns;
+	struct device                 *dev   = &pdev->dev;
+	struct imx_nfc_platform_data  *pdata = pdev->dev.platform_data;
+	struct imx_nfc_data           *this  = 0;
+
+	/* Say hello. */
+
+	dev_info(dev, "Probing...\n");
+
+	/* Check if we're enabled. */
+
+	if (!imx_nfc_module_enable) {
+		dev_info(dev, "Disabled\n");
+		return -ENXIO;
+	}
+
+	/* Validate the platform device data. */
+
+	error = validate_the_platform(pdev);
+
+	if (error)
+		goto exit_validate_platform;
+
+	/* Allocate memory for the per-device data. */
+
+	this = kzalloc(sizeof(*this), GFP_KERNEL);
+
+	if (!this) {
+		dev_err(dev, "Failed to allocate per-device memory\n");
+		error = -ENOMEM;
+		goto exit_allocate_this;
+	}
+
+	/* Link our per-device data to the owning device. */
+
+	platform_set_drvdata(pdev, this);
+
+	/* Fill in the convenience pointers in our per-device data. */
+
+	this->pdev  = pdev;
+	this->dev   = &pdev->dev;
+	this->pdata = pdata;
+
+	/* Initialize the interrupt service pathway. */
+
+	init_completion(&this->done);
+
+	/* Set up the NFC HAL. */
+
+	error = set_up_the_nfc_hal(this);
+
+	if (error)
+		goto exit_set_up_nfc_hal;
+
+	/* Attempt to acquire the resources we need. */
+
+	error = acquire_resources(this);
+
+	if (error)
+		goto exit_acquire_resources;
+
+	/* Initialize the NFC HAL. */
+
+	if (this->nfc->init(this)) {
+		error = -ENXIO;
+		goto exit_nfc_init;
+	}
+
+	/* Tell the platform we're bringing this device up. */
+
+	if (pdata->init)
+		error = pdata->init();
+
+	if (error)
+		goto exit_platform_init;
+
+	/* Report. */
+
+	parent_clock             = clk_get_parent(this->clock);
+	parent_clock_rate_in_hz  = clk_get_rate(parent_clock);
+	parent_clock_rate_in_mhz = parent_clock_rate_in_hz / 1000000;
+	nfc_clock_rate_in_hz     = clk_get_rate(this->clock);
+	nfc_clock_rate_in_mhz    = nfc_clock_rate_in_hz / 1000000;
+
+	clock_divisor   = parent_clock_rate_in_hz / nfc_clock_rate_in_hz;
+	symmetric_clock = this->nfc->get_symmetric(this) ? "Yes" : "No";
+	cycle_in_ns     = get_cycle_in_ns(this);
+
+	dev_dbg(dev, "-------------\n");
+	dev_dbg(dev, "Configuration\n");
+	dev_dbg(dev, "-------------\n");
+	dev_dbg(dev, "NFC Version      : %d.%d\n"  , this->nfc->major_version,
+						     this->nfc->minor_version);
+	dev_dbg(dev, "Buffers          : 0x%p\n"   , this->buffers);
+	dev_dbg(dev, "Primary Regs     : 0x%p\n"   , this->primary_regs);
+	dev_dbg(dev, "Secondary Regs   : 0x%p\n"   , this->secondary_regs);
+	dev_dbg(dev, "Interrupt        : %u\n"     , this->interrupt);
+	dev_dbg(dev, "Clock Name       : %s\n"     , pdata->clock_name);
+	dev_dbg(dev, "Parent Clock Rate: %lu Hz (%lu MHz)\n",
+						     parent_clock_rate_in_hz,
+						     parent_clock_rate_in_mhz);
+	dev_dbg(dev, "Clock Divisor    : %lu\n",     clock_divisor);
+	dev_dbg(dev, "NFC Clock Rate   : %lu Hz (%lu MHz)\n",
+						     nfc_clock_rate_in_hz,
+						     nfc_clock_rate_in_mhz);
+	dev_dbg(dev, "Symmetric Clock  : %s\n"     , symmetric_clock);
+	dev_dbg(dev, "Actual Cycle     : %lu ns\n" , cycle_in_ns);
+	dev_dbg(dev, "Target Cycle     : %u ns\n"  , pdata->target_cycle_in_ns);
+
+	/* Initialize the Medium Abstraction Layer. */
+
+	mal_init(this);
+
+	/* Initialize the MTD Interface Layer. */
+
+	mil_init(this);
+
+	/* Register this medium with MTD. */
+
+	error = register_with_mtd(this);
+
+	if (error)
+		goto exit_mtd_registration;
+
+	/* Create sysfs entries for this device. */
+
+	manage_sysfs_files(this, true);
+
+	/* Return success. */
+
+	return 0;
+
+	/* Error return paths begin here. */
+
+exit_mtd_registration:
+	if (pdata->exit)
+		pdata->exit();
+exit_platform_init:
+	this->nfc->exit(this);
+exit_nfc_init:
+exit_acquire_resources:
+exit_set_up_nfc_hal:
+	platform_set_drvdata(pdev, NULL);
+	kfree(this);
+exit_allocate_this:
+exit_validate_platform:
+	return error;
+
+}
+
+/**
+ * imx_nfc_remove() - Dissociates this driver from the given device.
+ *
+ * @pdev:  A pointer to the device.
+ */
+static int __exit imx_nfc_remove(struct platform_device *pdev)
+{
+	struct imx_nfc_data  *this  = platform_get_drvdata(pdev);
+
+	/* Remove sysfs entries for this device. */
+
+	manage_sysfs_files(this, false);
+
+	/* Unregister with the NAND Flash MTD system. */
+
+	unregister_with_mtd(this);
+
+	/* Tell the platform we're shutting down this device. */
+
+	if (this->pdata->exit)
+		this->pdata->exit();
+
+	/* Shut down the NFC. */
+
+	this->nfc->exit(this);
+
+	/* Release our resources. */
+
+	release_resources(this);
+
+	/* Unlink our per-device data from the platform device. */
+
+	platform_set_drvdata(pdev, NULL);
+
+	/* Free our per-device data. */
+
+	kfree(this);
+
+	/* Return success. */
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+/**
+ * suspend() - Puts the NFC in a low power state.
+ *
+ * Refer to Documentation/driver-model/driver.txt for more information.
+ *
+ * @pdev:  A pointer to the device.
+ * @state: The new power state.
+ */
+
+static int imx_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int                  error = 0;
+	struct imx_nfc_data  *this = platform_get_drvdata(pdev);
+	struct mtd_info      *mtd  = &this->mtd;
+	struct device        *dev  = &this->pdev->dev;
+
+	dev_dbg(dev, "Suspending...\n");
+
+	/* Suspend MTD's use of this device. */
+
+	error = mtd->suspend(mtd);
+
+	/* Suspend the actual hardware. */
+
+	clk_disable(this->clock);
+
+	return error;
+
+}
+
+/**
+ * resume() - Brings the NFC back from a low power state.
+ *
+ * Refer to Documentation/driver-model/driver.txt for more information.
+ *
+ * @pdev:  A pointer to the device.
+ */
+static int imx_nfc_resume(struct platform_device *pdev)
+{
+	struct imx_nfc_data  *this = platform_get_drvdata(pdev);
+	struct mtd_info      *mtd  = &this->mtd;
+	struct device        *dev  = &this->pdev->dev;
+
+	dev_dbg(dev, "Resuming...\n");
+
+	/* Resume MTD's use of this device. */
+
+	mtd->resume(mtd);
+
+	return 0;
+
+}
+
+#else
+
+#define suspend  NULL
+#define resume   NULL
+
+#endif  /* CONFIG_PM */
+
+/*
+ * This structure represents this driver to the platform management system.
+ */
+static struct platform_driver imx_nfc_driver = {
+	.driver = {
+		.name = IMX_NFC_DRIVER_NAME,
+	},
+	.probe   = imx_nfc_probe,
+	.remove  = __exit_p(imx_nfc_remove),
+	.suspend = imx_nfc_suspend,
+	.resume  = imx_nfc_resume,
+};
+
+/**
+ * imx_nfc_init() - Initializes this module.
+ */
+static int __init imx_nfc_init(void)
+{
+
+	pr_info("i.MX NFC driver %s\n", DRIVER_VERSION);
+
+	/* Register this driver with the platform management system. */
+
+	if (platform_driver_register(&imx_nfc_driver) != 0) {
+		pr_err("i.MX NFC driver registration failed\n");
+		return -ENODEV;
+	}
+
+	return 0;
+
+}
+
+/**
+ * imx_nfc_exit() - Deactivates this module.
+ */
+static void __exit imx_nfc_exit(void)
+{
+	pr_debug("i.MX NFC driver exiting...\n");
+	platform_driver_unregister(&imx_nfc_driver);
+}
+
+module_init(imx_nfc_init);
+module_exit(imx_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/mxc_nd.c b/drivers/mtd/nand/mxc_nd.c
new file mode 100644
index 000000000000..fc95af3bd442
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nd.c
@@ -0,0 +1,1413 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <asm/io.h>
+#include <asm/mach/flash.h>
+
+#include "mxc_nd.h"
+
+#define DVR_VER "2.1"
+
+struct mxc_mtd_s {
+	struct mtd_info mtd;
+	struct nand_chip nand;
+	struct mtd_partition *parts;
+	struct device *dev;
+};
+
+static struct mxc_mtd_s *mxc_nand_data;
+
+/*
+ * Define delays in microsec for NAND device operations
+ */
+#define TROP_US_DELAY   2000
+/*
+ * Macros to get half word and bit positions of ECC
+ */
+#define COLPOS(x) ((x) >> 4)
+#define BITPOS(x) ((x) & 0xf)
+
+/* Define single bit Error positions in Main & Spare area */
+#define MAIN_SINGLEBIT_ERROR 0x4
+#define SPARE_SINGLEBIT_ERROR 0x1
+
+struct nand_info {
+	bool bSpareOnly;
+	bool bStatusRequest;
+	u16 colAddr;
+};
+
+static struct nand_info g_nandfc_info;
+
+#ifdef CONFIG_MTD_NAND_MXC_SWECC
+static int hardware_ecc = 0;
+#else
+static int hardware_ecc = 1;
+#endif
+
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+static int Ecc_disabled;
+#endif
+
+static int is2k_Pagesize = 0;
+
+static struct clk *nfc_clk;
+
+/*
+ * OOB placement block for use with hardware ecc generation
+ */
+static struct nand_ecclayout nand_hw_eccoob_8 = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {{0, 5}, {11, 5}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_16 = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {{0, 6}, {12, 4}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_2k = {
+	.eccbytes = 20,
+	.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
+		   38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
+	.oobfree = {
+		    {.offset = 0,
+		     .length = 5},
+
+		    {.offset = 11,
+		     .length = 10},
+
+		    {.offset = 27,
+		     .length = 10},
+
+		    {.offset = 43,
+		     .length = 10},
+
+		    {.offset = 59,
+		     .length = 5}
+		    }
+};
+
+/*!
+ * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors
+ */
+
+/*!
+ * @file mxc_nd.c
+ *
+ * @brief This file contains the hardware specific layer for NAND Flash on
+ * MXC processor
+ *
+ * @ingroup NAND_MTD
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
+#endif
+
+static wait_queue_head_t irq_waitq;
+
+static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
+{
+	NFC_CONFIG1 |= NFC_INT_MSK;	/* Disable interrupt */
+	wake_up(&irq_waitq);
+
+	return IRQ_RETVAL(1);
+}
+
+/*!
+ * This function polls the NANDFC to wait for the basic operation to complete by
+ * checking the INT bit of config2 register.
+ *
+ * @param       maxRetries     number of retry attempts (separated by 1 us)
+ * @param       param           parameter for debug
+ * @param       useirq         True if IRQ should be used rather than polling
+ */
+static void wait_op_done(int maxRetries, u16 param, bool useirq)
+{
+	if (useirq) {
+		if ((NFC_CONFIG2 & NFC_INT) == 0) {
+			NFC_CONFIG1 &= ~NFC_INT_MSK;	/* Enable interrupt */
+			wait_event(irq_waitq, NFC_CONFIG2 & NFC_INT);
+		}
+		NFC_CONFIG2 &= ~NFC_INT;
+	} else {
+		while (maxRetries-- > 0) {
+			if (NFC_CONFIG2 & NFC_INT) {
+				NFC_CONFIG2 &= ~NFC_INT;
+				break;
+			}
+			udelay(1);
+		}
+		if (maxRetries <= 0)
+			DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
+			      __FUNCTION__, param);
+	}
+}
+
+/*!
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ *
+ * @param       cmd     command for NAND Flash
+ * @param       useirq  True if IRQ should be used rather than polling
+ */
+static void send_cmd(u16 cmd, bool useirq)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq);
+
+	NFC_FLASH_CMD = (u16) cmd;
+	NFC_CONFIG2 = NFC_CMD;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, cmd, useirq);
+}
+
+/*!
+ * This function sends an address (or partial address) to the
+ * NAND device.  The address is used to select the source/destination for
+ * a NAND command.
+ *
+ * @param       addr    address to be written to NFC.
+ * @param       islast  True if this is the last address cycle for command
+ */
+static void send_addr(u16 addr, bool islast)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, islast);
+
+	NFC_FLASH_ADDR = addr;
+	NFC_CONFIG2 = NFC_ADDR;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, addr, islast);
+}
+
+/*!
+ * This function requests the NANDFC to initate the transfer
+ * of data currently in the NANDFC RAM buffer to the NAND device.
+ *
+ * @param	buf_id	      Specify Internal RAM Buffer number (0-3)
+ * @param       bSpareOnly    set true if only the spare area is transferred
+ */
+static void send_prog_page(u8 buf_id, bool bSpareOnly)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", bSpareOnly);
+
+	/* NANDFC buffer 0 is used for page read/write */
+
+	NFC_BUF_ADDR = buf_id;
+
+	/* Configure spare or page+spare access */
+	if (!is2k_Pagesize) {
+		if (bSpareOnly) {
+			NFC_CONFIG1 |= NFC_SP_EN;
+		} else {
+			NFC_CONFIG1 &= ~(NFC_SP_EN);
+		}
+	}
+	NFC_CONFIG2 = NFC_INPUT;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, bSpareOnly, true);
+}
+
+/*!
+ * This function will correct the single bit ECC error
+ *
+ * @param  buf_id	Specify Internal RAM Buffer number (0-3)
+ * @param  eccpos 	Ecc byte and bit position
+ * @param  bSpareOnly  	set to true if only spare area needs correction
+ */
+
+static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, bool bSpareOnly)
+{
+	u16 col;
+	u8 pos;
+	volatile u16 *buf;
+
+	/* Get col & bit position of error
+	   these macros works for both 8 & 16 bits */
+	col = COLPOS(eccpos);	/* Get half-word position */
+	pos = BITPOS(eccpos);	/* Get bit position */
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos);
+
+	/* Set the pointer for main / spare area */
+	if (!bSpareOnly) {
+		buf = (volatile u16 *)(MAIN_AREA0 + col + (256 * buf_id));
+	} else {
+		buf = (volatile u16 *)(SPARE_AREA0 + col + (8 * buf_id));
+	}
+
+	/* Fix the data */
+	*buf ^= (1 << pos);
+}
+
+/*!
+ * This function will maintains state of single bit Error
+ * in Main & spare  area
+ *
+ * @param buf_id	Specify Internal RAM Buffer number (0-3)
+ * @param spare  	set to true if only spare area needs correction
+ */
+static void mxc_nd_correct_ecc(u8 buf_id, bool spare)
+{
+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+	static int lastErrMain = 0, lastErrSpare = 0;	/* To maintain single bit
+							   error in previous page */
+#endif
+	u16 value, ecc_status;
+	/* Read the ECC result */
+	ecc_status = NFC_ECC_STATUS_RESULT;
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status);
+
+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+	/* Check for Error in Mainarea */
+	if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
+		/* Check for error in previous page */
+		if (lastErrMain && !spare) {
+			value = NFC_RSLTMAIN_AREA;
+			/* Correct single bit error in Mainarea
+			   NFC will not correct the error in
+			   current page */
+			mxc_nd_correct_error(buf_id, value, false);
+		} else {
+			/* Set if single bit error in current page */
+			lastErrMain = 1;
+		}
+	} else {
+		/* Reset if no single bit error in current page */
+		lastErrMain = 0;
+	}
+
+	/* Check for Error in Sparearea */
+	if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
+		/* Check for error in previous page */
+		if (lastErrSpare) {
+			value = NFC_RSLTSPARE_AREA;
+			/* Correct single bit error in Mainarea
+			   NFC will not correct the error in
+			   current page */
+			mxc_nd_correct_error(buf_id, value, true);
+		} else {
+			/* Set if single bit error in current page */
+			lastErrSpare = 1;
+		}
+	} else {
+		/* Reset if no single bit error in current page */
+		lastErrSpare = 0;
+	}
+#else
+	if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR)
+	    || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) {
+		if (Ecc_disabled) {
+			if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
+				value = NFC_RSLTMAIN_AREA;
+				/* Correct single bit error in Mainarea
+				   NFC will not correct the error in
+				   current page */
+				mxc_nd_correct_error(buf_id, value, false);
+			}
+			if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
+				value = NFC_RSLTSPARE_AREA;
+				/* Correct single bit error in Mainarea
+				   NFC will not correct the error in
+				   current page */
+				mxc_nd_correct_error(buf_id, value, true);
+			}
+
+		} else {
+			/* Disable ECC  */
+			NFC_CONFIG1 &= ~(NFC_ECC_EN);
+			Ecc_disabled = 1;
+		}
+	} else if (ecc_status == 0) {
+		if (Ecc_disabled) {
+			/* Enable ECC */
+			NFC_CONFIG1 |= NFC_ECC_EN;
+			Ecc_disabled = 0;
+		}
+	} else {
+		/* 2-bit Error  Do nothing */
+	}
+#endif				/* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */
+
+}
+
+/*!
+ * This function requests the NANDFC to initated the transfer
+ * of data from the NAND device into in the NANDFC ram buffer.
+ *
+ * @param  	buf_id		Specify Internal RAM Buffer number (0-3)
+ * @param       bSpareOnly    	set true if only the spare area is transferred
+ */
+static void send_read_page(u8 buf_id, bool bSpareOnly)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", bSpareOnly);
+
+	/* NANDFC buffer 0 is used for page read/write */
+	NFC_BUF_ADDR = buf_id;
+
+	/* Configure spare or page+spare access */
+	if (!is2k_Pagesize) {
+		if (bSpareOnly) {
+			NFC_CONFIG1 |= NFC_SP_EN;
+		} else {
+			NFC_CONFIG1 &= ~(NFC_SP_EN);
+		}
+	}
+
+	NFC_CONFIG2 = NFC_OUTPUT;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, bSpareOnly, true);
+
+	/* If there are single bit errors in
+	   two consecutive page reads then
+	   the error is not  corrected by the
+	   NFC for the second page.
+	   Correct single bit error in driver */
+
+	mxc_nd_correct_ecc(buf_id, bSpareOnly);
+}
+
+/*!
+ * This function requests the NANDFC to perform a read of the
+ * NAND device ID.
+ */
+static void send_read_id(void)
+{
+	struct nand_chip *this = &mxc_nand_data->nand;
+
+	/* NANDFC buffer 0 is used for device ID output */
+	NFC_BUF_ADDR = 0x0;
+
+	/* Read ID into main buffer */
+	NFC_CONFIG1 &= (~(NFC_SP_EN));
+	NFC_CONFIG2 = NFC_ID;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, 0, true);
+
+	if (this->options & NAND_BUSWIDTH_16) {
+		volatile u16 *mainBuf = MAIN_AREA0;
+
+		/*
+		 * Pack the every-other-byte result for 16-bit ID reads
+		 * into every-byte as the generic code expects and various
+		 * chips implement.
+		 */
+
+		mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8);
+		mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8);
+		mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8);
+	}
+}
+
+/*!
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ *
+ * @return  device status
+ */
+static u16 get_dev_status(void)
+{
+	volatile u16 *mainBuf = MAIN_AREA1;
+	u32 store;
+	u16 ret;
+	/* Issue status request to NAND device */
+
+	/* store the main area1 first word, later do recovery */
+	store = *((u32 *) mainBuf);
+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	NFC_BUF_ADDR = 1;
+
+	/* Read status into main buffer */
+	NFC_CONFIG1 &= (~(NFC_SP_EN));
+	NFC_CONFIG2 = NFC_STATUS;
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, 0, true);
+
+	/* Status is placed in first word of main buffer */
+	/* get status, then recovery area 1 data */
+	ret = mainBuf[0];
+	*((u32 *) mainBuf) = store;
+
+	return ret;
+}
+
+/*!
+ * This functions is used by upper layer to checks if device is ready
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ *
+ * @return  0 if device is busy else 1
+ */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)
+{
+	/*
+	 * NFC handles R/B internally.Therefore,this function
+	 * always returns status as ready.
+	 */
+	return 1;
+}
+
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	/*
+	 * If HW ECC is enabled, we turn it on during init.  There is
+	 * no need to enable again here.
+	 */
+}
+
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char * dat,
+				 u_char * read_ecc, u_char * calc_ecc)
+{
+	/*
+	 * 1-Bit errors are automatically corrected in HW.  No need for
+	 * additional correction.  2-Bit errors cannot be corrected by
+	 * HW ECC, so we need to return failure
+	 */
+	u16 ecc_status = NFC_ECC_STATUS_RESULT;
+
+	if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
+		DEBUG(MTD_DEBUG_LEVEL0,
+		      "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
+				  u_char * ecc_code)
+{
+	/*
+	 * Just return success.  HW ECC does not read/write the NFC spare
+	 * buffer.  Only the FLASH spare area contains the calcuated ECC.
+	 */
+	return 0;
+}
+
+/*!
+ * This function reads byte from the NAND Flash
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ *
+ * @return    data read from the NAND Flash
+ */
+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+	u_char retVal = 0;
+	u16 col, rdWord;
+	volatile u16 *mainBuf = MAIN_AREA0;
+	volatile u16 *spareBuf = SPARE_AREA0;
+
+	/* Check for status request */
+	if (g_nandfc_info.bStatusRequest) {
+		return (get_dev_status() & 0xFF);
+	}
+
+	/* Get column for 16-bit access */
+	col = g_nandfc_info.colAddr >> 1;
+
+	/* If we are accessing the spare region */
+	if (g_nandfc_info.bSpareOnly) {
+		rdWord = spareBuf[col];
+	} else {
+		rdWord = mainBuf[col];
+	}
+
+	/* Pick upper/lower byte of word from RAM buffer */
+	if (g_nandfc_info.colAddr & 0x1) {
+		retVal = (rdWord >> 8) & 0xFF;
+	} else {
+		retVal = rdWord & 0xFF;
+	}
+
+	/* Update saved column address */
+	g_nandfc_info.colAddr++;
+
+	return retVal;
+}
+
+/*!
+  * This function reads word from the NAND Flash
+  *
+  * @param       mtd     MTD structure for the NAND Flash
+  *
+  * @return    data read from the NAND Flash
+  */
+static u16 mxc_nand_read_word(struct mtd_info *mtd)
+{
+	u16 col;
+	u16 rdWord, retVal;
+	volatile u16 *p;
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_read_word(col = %d)\n", g_nandfc_info.colAddr);
+
+	col = g_nandfc_info.colAddr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	if (col < mtd->writesize)
+		p = (MAIN_AREA0) + (col >> 1);
+	else
+		p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1);
+
+	if (col & 1) {
+		rdWord = *p;
+		retVal = (rdWord >> 8) & 0xff;
+		rdWord = *(p + 1);
+		retVal |= (rdWord << 8) & 0xff00;
+
+	} else {
+		retVal = *p;
+
+	}
+
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col + 2;
+
+	return retVal;
+}
+
+/*!
+ * This function writes data of length \b len to buffer \b buf. The data to be
+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
+ * Operation by the NFC, the data is written to NAND Flash
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be written to NAND Flash
+ * @param       len     number of bytes to be written
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+			       const u_char * buf, int len)
+{
+	int n;
+	int col;
+	int i = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_write_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr,
+	      len);
+
+	col = g_nandfc_info.colAddr;
+
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	n = mtd->writesize + mtd->oobsize - col;
+	n = min(len, n);
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n);
+
+	while (n) {
+		volatile u32 *p;
+		if (col < mtd->writesize)
+			p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
+		else
+			p = (volatile u32 *)((ulong) (SPARE_AREA0) -
+					     mtd->writesize + (col & ~3));
+
+		DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __FUNCTION__,
+		      __LINE__, p);
+
+		if (((col | (int)&buf[i]) & 3) || n < 16) {
+			u32 data = 0;
+
+			if (col & 3 || n < 4)
+				data = *p;
+
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					data = (data & 0xffffff00) |
+					    (buf[i++] << 0);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					data = (data & 0xffff00ff) |
+					    (buf[i++] << 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					data = (data & 0xff00ffff) |
+					    (buf[i++] << 16);
+					n--;
+					col++;
+				}
+			case 3:
+				if (n) {
+					data = (data & 0x00ffffff) |
+					    (buf[i++] << 24);
+					n--;
+					col++;
+				}
+			}
+
+			*p = data;
+		} else {
+			int m = mtd->writesize - col;
+
+			if (col >= mtd->writesize)
+				m += mtd->oobsize;
+
+			m = min(n, m) & ~3;
+
+			DEBUG(MTD_DEBUG_LEVEL3,
+			      "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
+			      __FUNCTION__, __LINE__, n, m, i, col);
+
+			memcpy((void *)(p), &buf[i], m);
+			col += m;
+			i += m;
+			n -= m;
+		}
+	}
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col;
+
+}
+
+/*!
+ * This function id is used to read the data buffer from the NAND Flash. To
+ * read the data from NAND Flash first the data output cycle is initiated by
+ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
+ * then copied to buffer \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be read from NAND Flash
+ * @param       len     number of bytes to be read
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+
+	int n;
+	int col;
+	int i = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_read_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr,
+	      len);
+
+	col = g_nandfc_info.colAddr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
+		col += mtd->writesize;
+
+	n = mtd->writesize + mtd->oobsize - col;
+	n = min(len, n);
+
+	while (n) {
+		volatile u32 *p;
+
+		if (col < mtd->writesize)
+			p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
+		else
+			p = (volatile u32 *)((ulong) (SPARE_AREA0) -
+					     mtd->writesize + (col & ~3));
+
+		if (((col | (int)&buf[i]) & 3) || n < 16) {
+			u32 data;
+
+			data = *p;
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					buf[i++] = (u8) (data);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					buf[i++] = (u8) (data >> 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					buf[i++] = (u8) (data >> 16);
+					n--;
+					col++;
+				}
+			case 3:
+				if (n) {
+					buf[i++] = (u8) (data >> 24);
+					n--;
+					col++;
+				}
+			}
+		} else {
+			int m = mtd->writesize - col;
+
+			if (col >= mtd->writesize)
+				m += mtd->oobsize;
+
+			m = min(n, m) & ~3;
+			memcpy(&buf[i], (void *)(p), m);
+			col += m;
+			i += m;
+			n -= m;
+		}
+	}
+	/* Update saved column address */
+	g_nandfc_info.colAddr = col;
+
+}
+
+/*!
+ * This function is used by the upper layer to verify the data in NAND Flash
+ * with the data in the \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be verified
+ * @param       len     length of the data to be verified
+ *
+ * @return      -EFAULT if error else 0
+ *
+ */
+static int
+mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+	return -EFAULT;
+}
+
+/*!
+ * This function is used by upper layer for select and deselect of the NAND
+ * chip
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       chip    val indicating select or deselect
+ */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
+	if (chip > 0) {
+		DEBUG(MTD_DEBUG_LEVEL0,
+		      "ERROR:  Illegal chip select (chip = %d)\n", chip);
+		return;
+	}
+
+	if (chip == -1) {
+		NFC_CONFIG1 &= (~(NFC_CE));
+		return;
+	}
+
+	NFC_CONFIG1 |= NFC_CE;
+#endif
+
+	switch (chip) {
+	case -1:
+		/* Disable the NFC clock */
+		clk_disable(nfc_clk);
+		break;
+	case 0:
+		/* Enable the NFC clock */
+		clk_enable(nfc_clk);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*!
+ * This function is used by the upper layer to write command to NAND Flash for
+ * different operations to be carried out on NAND Flash
+ *
+ * @param       mtd             MTD structure for the NAND Flash
+ * @param       command         command for NAND Flash
+ * @param       column          column offset for the page read
+ * @param       page_addr       page to be read from NAND Flash
+ */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+			     int column, int page_addr)
+{
+	bool useirq = true;
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+	      command, column, page_addr);
+
+	/*
+	 * Reset command state information
+	 */
+	g_nandfc_info.bStatusRequest = false;
+
+	/* Reset column address to 0 */
+	g_nandfc_info.colAddr = 0;
+
+	/*
+	 * Command pre-processing step
+	 */
+	switch (command) {
+
+	case NAND_CMD_STATUS:
+		g_nandfc_info.bStatusRequest = true;
+		break;
+
+	case NAND_CMD_READ0:
+		g_nandfc_info.colAddr = column;
+		g_nandfc_info.bSpareOnly = false;
+		useirq = false;
+		break;
+
+	case NAND_CMD_READOOB:
+		g_nandfc_info.colAddr = column;
+		g_nandfc_info.bSpareOnly = true;
+		useirq = false;
+		if (is2k_Pagesize)
+			command = NAND_CMD_READ0;	/* only READ0 is valid */
+		break;
+
+	case NAND_CMD_SEQIN:
+		if (column >= mtd->writesize) {
+			if (is2k_Pagesize) {
+				/**
+				  * FIXME: before send SEQIN command for write OOB,
+				  * We must read one page out.
+				  * For K9F1GXX has no READ1 command to set current HW
+				  * pointer to spare area, we must write the whole page including OOB together.
+				  */
+				/* call itself to read a page */
+				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+						 page_addr);
+			}
+			g_nandfc_info.colAddr = column - mtd->writesize;
+			g_nandfc_info.bSpareOnly = true;
+			/* Set program pointer to spare region */
+			if (!is2k_Pagesize)
+				send_cmd(NAND_CMD_READOOB, false);
+		} else {
+			g_nandfc_info.bSpareOnly = false;
+			g_nandfc_info.colAddr = column;
+			/* Set program pointer to page start */
+			if (!is2k_Pagesize)
+				send_cmd(NAND_CMD_READ0, false);
+		}
+		useirq = false;
+		break;
+
+	case NAND_CMD_PAGEPROG:
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+		if (Ecc_disabled) {
+			/* Enable Ecc for page writes */
+			NFC_CONFIG1 |= NFC_ECC_EN;
+		}
+#endif
+
+		send_prog_page(0, g_nandfc_info.bSpareOnly);
+
+		if (is2k_Pagesize) {
+			/* data in 4 areas datas */
+			send_prog_page(1, g_nandfc_info.bSpareOnly);
+			send_prog_page(2, g_nandfc_info.bSpareOnly);
+			send_prog_page(3, g_nandfc_info.bSpareOnly);
+		}
+
+		break;
+
+	case NAND_CMD_ERASE1:
+		useirq = false;
+		break;
+	}
+
+	/*
+	 * Write out the command to the device.
+	 */
+	send_cmd(command, useirq);
+
+	/*
+	 * Write out column address, if necessary
+	 */
+	if (column != -1) {
+		/*
+		 * MXC NANDFC can only perform full page+spare or
+		 * spare-only read/write.  When the upper layers
+		 * layers perform a read/write buf operation,
+		 * we will used the saved column adress to index into
+		 * the full page.
+		 */
+		send_addr(0, page_addr == -1);
+		if (is2k_Pagesize)
+			/* another col addr cycle for 2k page */
+			send_addr(0, false);
+	}
+
+	/*
+	 * Write out page address, if necessary
+	 */
+	if (page_addr != -1) {
+		send_addr((page_addr & 0xff), false);	/* paddr_0 - p_addr_7 */
+
+		if (is2k_Pagesize) {
+			/* One more address cycle for higher density devices */
+			if (mtd->size >= 0x10000000) {
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, false);
+				send_addr((page_addr >> 16) & 0xff, true);
+			} else
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, true);
+		} else {
+			/* One more address cycle for higher density devices */
+			if (mtd->size >= 0x4000000) {
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, false);
+				send_addr((page_addr >> 16) & 0xff, true);
+			} else
+				/* paddr_8 - paddr_15 */
+				send_addr((page_addr >> 8) & 0xff, true);
+		}
+	}
+
+	/*
+	 * Command post-processing step
+	 */
+	switch (command) {
+
+	case NAND_CMD_RESET:
+		break;
+
+	case NAND_CMD_READOOB:
+	case NAND_CMD_READ0:
+		if (is2k_Pagesize) {
+			/* send read confirm command */
+			send_cmd(NAND_CMD_READSTART, true);
+			/* read for each AREA */
+			send_read_page(0, g_nandfc_info.bSpareOnly);
+			send_read_page(1, g_nandfc_info.bSpareOnly);
+			send_read_page(2, g_nandfc_info.bSpareOnly);
+			send_read_page(3, g_nandfc_info.bSpareOnly);
+		} else {
+			send_read_page(0, g_nandfc_info.bSpareOnly);
+		}
+		break;
+
+	case NAND_CMD_READID:
+		send_read_id();
+		break;
+
+	case NAND_CMD_PAGEPROG:
+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
+		if (Ecc_disabled) {
+			/* Disble Ecc after page writes */
+			NFC_CONFIG1 &= ~(NFC_ECC_EN);
+		}
+#endif
+		break;
+
+	case NAND_CMD_STATUS:
+		break;
+
+	case NAND_CMD_ERASE2:
+		break;
+	}
+}
+
+/* Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks. */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr smallpage_memorybased = {
+	.options = NAND_BBT_SCAN2NDPAGE,
+	.offs = 5,
+	.len = 1,
+	.pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern
+};
+
+/* Generic flash bbt decriptors
+*/
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+static int mxc_nand_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	/* Config before scanning */
+	/* Do not rely on NFMS_BIT, set/clear NFMS bit based on mtd->writesize */
+	if (mtd->writesize == 2048) {
+		NFMS |= (1 << NFMS_BIT);
+		is2k_Pagesize = 1;
+	} else {
+		if ((NFMS >> NFMS_BIT) & 0x1) {	/* This case strangly happened on MXC91321 P1.2.2 */
+			printk(KERN_INFO
+			       "Oops... NFMS Bit set for 512B Page, resetting it. [RCSR: 0x%08x]\n",
+			       NFMS);
+			NFMS &= ~(1 << NFMS_BIT);
+		}
+		is2k_Pagesize = 0;
+	}
+
+	if (is2k_Pagesize)
+		this->ecc.layout = &nand_hw_eccoob_2k;
+
+	/* jffs2 not write oob */
+	mtd->flags &= ~MTD_OOB_WRITEABLE;
+
+	/* use flash based bbt */
+	this->bbt_td = &bbt_main_descr;
+	this->bbt_md = &bbt_mirror_descr;
+
+	/* update flash based bbt */
+	this->options |= NAND_USE_FLASH_BBT;
+
+	if (!this->badblock_pattern) {
+		if (mtd->writesize == 2048)
+			this->badblock_pattern = &smallpage_memorybased;
+		else
+			this->badblock_pattern = (mtd->writesize > 512) ?
+			    &largepage_memorybased : &smallpage_memorybased;
+	}
+	/* Build bad block table */
+	return nand_scan_bbt(mtd, this->badblock_pattern);
+}
+
+#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
+static void mxc_low_erase(struct mtd_info *mtd)
+{
+
+	struct nand_chip *this = mtd->priv;
+	unsigned int page_addr, addr;
+	u_char status;
+
+	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n");
+	for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) {
+		page_addr = addr / mtd->writesize;
+		mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr);
+		mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1);
+		mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
+		status = mxc_nand_read_byte(mtd);
+		if (status & NAND_STATUS_FAIL) {
+			printk(KERN_ERR
+			       "ERASE FAILED(block = %d,status = 0x%x)\n",
+			       addr / mtd->erasesize, status);
+		}
+	}
+
+}
+#endif
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and
+ *                remove functions
+ *
+ * @return  The function always returns 0.
+ */
+static int __init mxcnd_probe(struct platform_device *pdev)
+{
+	struct nand_chip *this;
+	struct mtd_info *mtd;
+	struct flash_platform_data *flash = pdev->dev.platform_data;
+	int nr_parts = 0;
+
+	int err = 0;
+	/* Allocate memory for MTD device structure and private data */
+	mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL);
+	if (!mxc_nand_data) {
+		printk(KERN_ERR "%s: failed to allocate mtd_info\n",
+		       __FUNCTION__);
+		err = -ENOMEM;
+		goto out;
+	}
+	memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
+
+	mxc_nand_data->dev = &pdev->dev;
+	/* structures must be linked */
+	this = &mxc_nand_data->nand;
+	mtd = &mxc_nand_data->mtd;
+	mtd->priv = this;
+	mtd->owner = THIS_MODULE;
+
+	/* 50 us command delay time */
+	this->chip_delay = 5;
+
+	this->priv = mxc_nand_data;
+	this->dev_ready = mxc_nand_dev_ready;
+	this->cmdfunc = mxc_nand_command;
+	this->select_chip = mxc_nand_select_chip;
+	this->read_byte = mxc_nand_read_byte;
+	this->read_word = mxc_nand_read_word;
+	this->write_buf = mxc_nand_write_buf;
+	this->read_buf = mxc_nand_read_buf;
+	this->verify_buf = mxc_nand_verify_buf;
+	this->scan_bbt = mxc_nand_scan_bbt;
+
+	nfc_clk = clk_get(&pdev->dev, "nfc_clk");
+	clk_enable(nfc_clk);
+
+	NFC_CONFIG1 |= NFC_INT_MSK;
+	init_waitqueue_head(&irq_waitq);
+	err = request_irq(MXC_INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL);
+	if (err) {
+		goto out_1;
+	}
+
+	if (hardware_ecc) {
+		this->ecc.calculate = mxc_nand_calculate_ecc;
+		this->ecc.hwctl = mxc_nand_enable_hwecc;
+		this->ecc.correct = mxc_nand_correct_data;
+		this->ecc.mode = NAND_ECC_HW;
+		this->ecc.size = 512;
+		this->ecc.bytes = 3;
+		this->ecc.layout = &nand_hw_eccoob_8;
+		NFC_CONFIG1 |= NFC_ECC_EN;
+	} else {
+		this->ecc.mode = NAND_ECC_SOFT;
+	}
+
+	/* Reset NAND */
+	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+	/* preset operation */
+	/* Unlock the internal RAM Buffer */
+	NFC_CONFIG = 0x2;
+
+	/* Blocks to be unlocked */
+	NFC_UNLOCKSTART_BLKADDR = 0x0;
+	NFC_UNLOCKEND_BLKADDR = 0x4000;
+
+	/* Unlock Block Command for given address range */
+	NFC_WRPROT = 0x4;
+
+	/* NAND bus width determines access funtions used by upper layer */
+	if (flash->width == 2) {
+		this->options |= NAND_BUSWIDTH_16;
+		this->ecc.layout = &nand_hw_eccoob_16;
+	} else {
+		this->options |= 0;
+	}
+
+	is2k_Pagesize = 0;
+
+	/* Scan to find existence of the device */
+	if (nand_scan(mtd, 1)) {
+		DEBUG(MTD_DEBUG_LEVEL0,
+		      "MXC_ND: Unable to find any NAND device.\n");
+		err = -ENXIO;
+		goto out_1;
+	}
+
+	/* Register the partitions */
+#ifdef CONFIG_MTD_PARTITIONS
+	nr_parts =
+	    parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0);
+	if (nr_parts > 0)
+		add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts);
+	else if (flash->parts)
+		add_mtd_partitions(mtd, flash->parts, flash->nr_parts);
+	else
+#endif
+	{
+		pr_info("Registering %s as whole device\n", mtd->name);
+		add_mtd_device(mtd);
+	}
+#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
+	/* Erase all the blocks of a NAND */
+	mxc_low_erase(mtd);
+#endif
+
+	platform_set_drvdata(pdev, mtd);
+	return 0;
+
+      out_1:
+	kfree(mxc_nand_data);
+      out:
+	return err;
+
+}
+
+ /*!
+  * Dissociates the driver from the device.
+  *
+  * @param   pdev  the device structure used to give information on which
+  *
+  * @return  The function always returns 0.
+  */
+
+static int __exit mxcnd_remove(struct platform_device *pdev)
+{
+	struct mtd_info *mtd = platform_get_drvdata(pdev);
+
+	clk_put(nfc_clk);
+	platform_set_drvdata(pdev, NULL);
+
+	if (mxc_nand_data) {
+		nand_release(mtd);
+		free_irq(MXC_INT_NANDFC, NULL);
+		kfree(mxc_nand_data);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This function is called to put the NAND in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device information structure
+ *
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+
+static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mtd_info *info = platform_get_drvdata(pdev);
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
+	if (info)
+		ret = info->suspend(info);
+
+	/* Disable the NFC clock */
+	clk_disable(nfc_clk);
+
+	return ret;
+}
+
+/*!
+ * This function is called to bring the NAND back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device information structure
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxcnd_resume(struct platform_device *pdev)
+{
+	struct mtd_info *info = platform_get_drvdata(pdev);
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
+	/* Enable the NFC clock */
+	clk_enable(nfc_clk);
+
+	if (info) {
+		info->resume(info);
+	}
+
+	return ret;
+}
+
+#else
+#define mxcnd_suspend   NULL
+#define mxcnd_resume    NULL
+#endif				/* CONFIG_PM */
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcnd_driver = {
+	.driver = {
+		   .name = "mxc_nand_flash",
+		   },
+	.probe = mxcnd_probe,
+	.remove = __exit_p(mxcnd_remove),
+	.suspend = mxcnd_suspend,
+	.resume = mxcnd_resume,
+};
+
+/*!
+ * Main initialization routine
+ * @return  0 if successful; non-zero otherwise
+ */
+static int __init mxc_nd_init(void)
+{
+	/* Register the device driver structure. */
+	pr_info("MXC MTD nand Driver %s\n", DVR_VER);
+	if (platform_driver_register(&mxcnd_driver) != 0) {
+		printk(KERN_ERR "Driver register failed for mxcnd_driver\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+/*!
+ * Clean up routine
+ */
+static void __exit mxc_nd_cleanup(void)
+{
+	/* Unregister the device structure */
+	platform_driver_unregister(&mxcnd_driver);
+}
+
+module_init(mxc_nd_init);
+module_exit(mxc_nd_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC NAND MTD driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/mxc_nd.h b/drivers/mtd/nand/mxc_nd.h
new file mode 100644
index 000000000000..e38a9a637c1d
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nd.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_nd.h
+ *
+ * @brief This file contains the NAND Flash Controller register information.
+ *
+ *
+ * @ingroup NAND_MTD
+ */
+
+#ifndef __MXC_ND_H__
+#define __MXC_ND_H__
+
+#include <mach/hardware.h>
+
+/*
+ * Addresses for NFC registers
+ */
+#define NFC_BUF_SIZE            (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE00)))
+#define NFC_BUF_ADDR            (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE04)))
+#define NFC_FLASH_ADDR          (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE06)))
+#define NFC_FLASH_CMD           (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE08)))
+#define NFC_CONFIG              (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0A)))
+#define NFC_ECC_STATUS_RESULT   (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0C)))
+#define NFC_RSLTMAIN_AREA       (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0E)))
+#define NFC_RSLTSPARE_AREA      (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE10)))
+#define NFC_WRPROT              (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE12)))
+#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE14)))
+#define NFC_UNLOCKEND_BLKADDR   (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE16)))
+#define NFC_NF_WRPRST           (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE18)))
+#define NFC_CONFIG1             (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1A)))
+#define NFC_CONFIG2             (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1C)))
+
+/*!
+ * Addresses for NFC RAM BUFFER Main area 0
+ */
+#define MAIN_AREA0        (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x000)
+#define MAIN_AREA1        (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x200)
+#define MAIN_AREA2        (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x400)
+#define MAIN_AREA3        (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x600)
+
+/*!
+ * Addresses for NFC SPARE BUFFER Spare area 0
+ */
+#define SPARE_AREA0       (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x800)
+#define SPARE_AREA1       (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x810)
+#define SPARE_AREA2       (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x820)
+#define SPARE_AREA3       (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x830)
+
+/*!
+ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
+ * operation
+ */
+#define NFC_CMD            0x1
+
+/*!
+ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
+ * operation
+ */
+#define NFC_ADDR           0x2
+
+/*!
+ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
+ * operation
+ */
+#define NFC_INPUT          0x4
+
+/*!
+ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output
+ * operation
+ */
+#define NFC_OUTPUT         0x8
+
+/*!
+ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
+ * operation
+ */
+#define NFC_ID             0x10
+
+/*!
+ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status
+ * operation
+ */
+#define NFC_STATUS         0x20
+
+/*!
+ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
+ * operation
+ */
+#define NFC_INT            0x8000
+
+#define NFC_SP_EN           (1 << 2)
+#define NFC_ECC_EN          (1 << 3)
+#define NFC_INT_MSK         (1 << 4)
+#define NFC_BIG             (1 << 5)
+#define NFC_RST             (1 << 6)
+#define NFC_CE              (1 << 7)
+#define NFC_ONE_CYCLE       (1 << 8)
+
+#endif				/* MXCND_H */
diff --git a/drivers/mtd/nand/mxc_nd2.c b/drivers/mtd/nand/mxc_nd2.c
new file mode 100644
index 000000000000..a82af567ff8c
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nd2.c
@@ -0,0 +1,1625 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/flash.h>
+#include <asm/io.h>
+#include "mxc_nd2.h"
+#include "nand_device_info.h"
+
+#define DVR_VER "3.0"
+
+/* Global address Variables */
+static void __iomem *nfc_axi_base, *nfc_ip_base;
+
+struct mxc_mtd_s {
+	struct mtd_info mtd;
+	struct nand_chip nand;
+	struct mtd_partition *parts;
+	struct device *dev;
+	int disable_bi_swap; /* disable bi swap */
+};
+
+static struct mxc_mtd_s *mxc_nand_data;
+
+/*
+ * Define delay timeout value
+ */
+#define TROP_US_DELAY   (1000 * 1000)
+
+struct nand_info {
+	bool bStatusRequest;
+	u16 colAddr;
+};
+
+static struct nand_info g_nandfc_info;
+
+#ifdef CONFIG_MTD_NAND_MXC_SWECC
+static int hardware_ecc = 0;
+#else
+static int hardware_ecc = 1;
+#endif
+
+static u8 num_of_interleave = 1;
+
+static u8 *data_buf;
+static u8 *oob_buf;
+
+static int g_page_mask;
+
+static struct clk *nfc_clk;
+
+/*
+ * OOB placement block for use with hardware ecc generation
+ */
+static struct nand_ecclayout nand_hw_eccoob_512 = {
+	.eccbytes = 9,
+	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+	.oobavail = 4,
+	.oobfree = {{0, 4}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_2k = {
+	.eccbytes = 9,
+	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+	.oobavail = 4,
+	.oobfree = {{2, 4}}
+};
+
+static struct nand_ecclayout nand_hw_eccoob_4k = {
+	.eccbytes = 9,
+	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+	.oobavail = 4,
+	.oobfree = {{2, 4}}
+};
+
+/*!
+ * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors
+ */
+
+/*!
+ * @file mxc_nd2.c
+ *
+ * @brief This file contains the hardware specific layer for NAND Flash on
+ * MXC processor
+ *
+ * @ingroup NAND_MTD
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
+#endif
+
+static wait_queue_head_t irq_waitq;
+
+static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
+{
+	/* Disable Interuupt */
+	raw_write(raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK, REG_NFC_INTRRUPT);
+	wake_up(&irq_waitq);
+
+	return IRQ_HANDLED;
+}
+
+static void mxc_nand_bi_swap(struct mtd_info *mtd)
+{
+	u16 ma, sa, nma, nsa;
+
+	if (!IS_LARGE_PAGE_NAND)
+		return;
+
+	/* Disable bi swap if the user set disable_bi_swap at sys entry */
+	if (mxc_nand_data->disable_bi_swap)
+		return;
+
+	ma = __raw_readw(BAD_BLK_MARKER_MAIN);
+	sa = __raw_readw(BAD_BLK_MARKER_SP);
+
+	nma = (ma & 0xFF00) | (sa >> 8);
+	nsa = (sa & 0x00FF) | (ma << 8);
+
+	__raw_writew(nma, BAD_BLK_MARKER_MAIN);
+	__raw_writew(nsa, BAD_BLK_MARKER_SP);
+}
+
+static void nfc_memcpy(void *dest, void *src, int len)
+{
+	u8 *d = dest;
+	u8 *s = src;
+
+	while (len > 0) {
+		if (len >= 4) {
+			*(u32 *)d = *(u32 *)s;
+			d += 4;
+			s += 4;
+			len -= 4;
+		} else {
+			*(u16 *)d = *(u16 *)s;
+			len -= 2;
+			break;
+		}
+	}
+
+	if (len)
+		BUG();
+}
+
+/*
+ * Functions to transfer data to/from spare erea.
+ */
+static void
+copy_spare(struct mtd_info *mtd, void *pbuf, void *pspare, int len, bool bfrom)
+{
+	u16 i, j;
+	u16 m = mtd->oobsize;
+	u16 n = mtd->writesize >> 9;
+	u8 *d = (u8 *) pbuf;
+	u8 *s = (u8 *) pspare;
+	u16 t = SPARE_LEN;
+
+	m /= num_of_interleave;
+	n /= num_of_interleave;
+
+	j = (m / n >> 1) << 1;
+
+	if (bfrom) {
+		for (i = 0; i < n - 1; i++)
+			nfc_memcpy(&d[i * j], &s[i * t], j);
+
+		/* the last section */
+		nfc_memcpy(&d[i * j], &s[i * t], len - i * j);
+	} else {
+		for (i = 0; i < n - 1; i++)
+			nfc_memcpy(&s[i * t], &d[i * j], j);
+
+		/* the last section */
+		nfc_memcpy(&s[i * t], &d[i * j], len - i * j);
+	}
+}
+
+/*!
+ * This function polls the NFC to wait for the basic operation to complete by
+ * checking the INT bit of config2 register.
+ *
+ * @param       maxRetries     number of retry attempts (separated by 1 us)
+ * @param       useirq         True if IRQ should be used rather than polling
+ */
+static void wait_op_done(int maxRetries, bool useirq)
+{
+	if (useirq) {
+		if ((raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) == 0) {
+			/* enable interrupt */
+			raw_write(raw_read(REG_NFC_INTRRUPT) & ~NFC_INT_MSK,
+				  REG_NFC_INTRRUPT);
+			if (!wait_event_timeout(irq_waitq,
+				(raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT),
+				msecs_to_jiffies(TROP_US_DELAY / 1000)) > 0) {
+				/* disable interrupt */
+				raw_write(raw_read(REG_NFC_INTRRUPT)
+				| NFC_INT_MSK, REG_NFC_INTRRUPT);
+
+				printk(KERN_WARNING "%s(%d): INT not set\n",
+						__func__, __LINE__);
+				return;
+			}
+		}
+		WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) &
+				  ~NFC_OPS_STAT), REG_NFC_OPS_STAT);
+	} else {
+		while (1) {
+			maxRetries--;
+			if (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) {
+				WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) &
+						  ~NFC_OPS_STAT),
+						 REG_NFC_OPS_STAT);
+				break;
+			}
+			udelay(1);
+			if (maxRetries <= 0) {
+				printk(KERN_WARNING "%s(%d): INT not set\n",
+						__func__, __LINE__);
+				break;
+			}
+		}
+	}
+}
+
+static inline void send_atomic_cmd(u16 cmd, bool useirq)
+{
+	/* fill command */
+	raw_write(cmd, REG_NFC_FLASH_CMD);
+
+	/* send out command */
+	raw_write(NFC_CMD, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, useirq);
+}
+
+static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr);
+static int mxc_check_ecc_status(struct mtd_info *mtd);
+
+#ifdef NFC_AUTO_MODE_ENABLE
+/*!
+ * This function handle the interleave related work
+ * @param	mtd	mtd info
+ * @param	cmd	command
+ */
+static void auto_cmd_interleave(struct mtd_info *mtd, u16 cmd)
+{
+	u32 i, page_addr, ncs;
+	u32 j = num_of_interleave;
+	struct nand_chip *this = mtd->priv;
+	u32 addr_low = raw_read(NFC_FLASH_ADDR0);
+	u32 addr_high = raw_read(NFC_FLASH_ADDR8);
+	u8 *dbuf = data_buf;
+	u8 *obuf = oob_buf;
+	u32 dlen = mtd->writesize / j;
+	u32 olen = mtd->oobsize / j;
+
+	/* adjust the addr value
+	 * since ADD_OP mode is 01
+	 */
+	if (cmd == NAND_CMD_ERASE2)
+		page_addr = addr_low;
+	else
+		page_addr = addr_low >> 16 | addr_high << 16;
+
+	ncs = page_addr >> (this->chip_shift - this->page_shift);
+
+	if (j > 1) {
+		page_addr *= j;
+	} else {
+		page_addr *= this->numchips;
+		page_addr += ncs;
+	}
+
+	switch (cmd) {
+	case NAND_CMD_PAGEPROG:
+		for (i = 0; i < j; i++) {
+			/* reset addr cycle */
+			mxc_do_addr_cycle(mtd, 0, page_addr++);
+
+			/* data transfer */
+			memcpy(MAIN_AREA0, dbuf, dlen);
+			copy_spare(mtd, obuf, SPARE_AREA0, olen, false);
+			mxc_nand_bi_swap(mtd);
+
+			/* update the value */
+			dbuf += dlen;
+			obuf += olen;
+
+			NFC_SET_RBA(0);
+			raw_write(NFC_AUTO_PROG, REG_NFC_OPS);
+
+			/* wait auto_prog_done bit set */
+			while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE)) ;
+		}
+
+		wait_op_done(TROP_US_DELAY, true);
+		while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB)) ;
+
+		break;
+	case NAND_CMD_READSTART:
+		for (i = 0; i < j; i++) {
+			/* reset addr cycle */
+			mxc_do_addr_cycle(mtd, 0, page_addr++);
+
+			NFC_SET_RBA(0);
+			raw_write(NFC_AUTO_READ, REG_NFC_OPS);
+			wait_op_done(TROP_US_DELAY, true);
+
+			/* check ecc error */
+			mxc_check_ecc_status(mtd);
+
+			/* data transfer */
+			mxc_nand_bi_swap(mtd);
+			memcpy(dbuf, MAIN_AREA0, dlen);
+			copy_spare(mtd, obuf, SPARE_AREA0, olen, true);
+
+			/* update the value */
+			dbuf += dlen;
+			obuf += olen;
+		}
+		break;
+	case NAND_CMD_ERASE2:
+		for (i = 0; i < j; i++) {
+			mxc_do_addr_cycle(mtd, -1, page_addr++);
+			raw_write(NFC_AUTO_ERASE, REG_NFC_OPS);
+			wait_op_done(TROP_US_DELAY, true);
+		}
+		break;
+	case NAND_CMD_RESET:
+		for (i = 0; i < j; i++) {
+			if (j > 1)
+				NFC_SET_NFC_ACTIVE_CS(i);
+			send_atomic_cmd(cmd, false);
+		}
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+static void send_addr(u16 addr, bool useirq);
+
+/*!
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ *
+ * @param       cmd     command for NAND Flash
+ * @param       useirq  True if IRQ should be used rather than polling
+ */
+static void send_cmd(struct mtd_info *mtd, u16 cmd, bool useirq)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq);
+
+#ifdef NFC_AUTO_MODE_ENABLE
+	switch (cmd) {
+	case NAND_CMD_READ0:
+	case NAND_CMD_READOOB:
+		raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD);
+		break;
+	case NAND_CMD_SEQIN:
+	case NAND_CMD_ERASE1:
+		raw_write(cmd, REG_NFC_FLASH_CMD);
+		break;
+	case NAND_CMD_PAGEPROG:
+	case NAND_CMD_ERASE2:
+	case NAND_CMD_READSTART:
+		raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT,
+			  REG_NFC_FLASH_CMD);
+		auto_cmd_interleave(mtd, cmd);
+		break;
+	case NAND_CMD_READID:
+		send_atomic_cmd(cmd, useirq);
+		send_addr(0, false);
+		break;
+	case NAND_CMD_RESET:
+		auto_cmd_interleave(mtd, cmd);
+		break;
+	case NAND_CMD_STATUS:
+		send_atomic_cmd(cmd, useirq);
+		break;
+	default:
+		break;
+	}
+#else
+	send_atomic_cmd(cmd, useirq);
+#endif
+}
+
+/*!
+ * This function sends an address (or partial address) to the
+ * NAND device.  The address is used to select the source/destination for
+ * a NAND command.
+ *
+ * @param       addr    address to be written to NFC.
+ * @param       useirq  True if IRQ should be used rather than polling
+ */
+static void send_addr(u16 addr, bool useirq)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, useirq);
+
+	/* fill address */
+	raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR);
+
+	/* send out address */
+	raw_write(NFC_ADDR, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, useirq);
+}
+
+/*!
+ * This function requests the NFC to initate the transfer
+ * of data currently in the NFC RAM buffer to the NAND device.
+ *
+ * @param	buf_id	      Specify Internal RAM Buffer number
+ */
+static void send_prog_page(u8 buf_id)
+{
+#ifndef NFC_AUTO_MODE_ENABLE
+	DEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__);
+
+	/* set ram buffer id */
+	NFC_SET_RBA(buf_id);
+
+	/* transfer data from NFC ram to nand */
+	raw_write(NFC_INPUT, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, true);
+#endif
+}
+
+/*!
+ * This function requests the NFC to initated the transfer
+ * of data from the NAND device into in the NFC ram buffer.
+ *
+ * @param  	buf_id		Specify Internal RAM Buffer number
+ */
+static void send_read_page(u8 buf_id)
+{
+#ifndef NFC_AUTO_MODE_ENABLE
+	DEBUG(MTD_DEBUG_LEVEL3, "%s(%d)\n", __FUNCTION__, buf_id);
+
+	/* set ram buffer id */
+	NFC_SET_RBA(buf_id);
+
+	/* transfer data from nand to NFC ram */
+	raw_write(NFC_OUTPUT, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, true);
+#endif
+}
+
+/*!
+ * This function requests the NFC to perform a read of the
+ * NAND device ID.
+ */
+static void send_read_id(void)
+{
+	/* Set RBA bits for BUFFER0 */
+	NFC_SET_RBA(0);
+
+	/* Read ID into main buffer */
+	raw_write(NFC_ID, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, false);
+
+}
+
+#ifdef NFC_AUTO_MODE_ENABLE
+static inline void read_dev_status(u16 *status)
+{
+	u32 mask = 0xFF << 16;
+
+	/* use atomic mode to read status instead
+	   of using auto mode,auto-mode has issues
+	   and the status is not correct.
+	*/
+	raw_write(NFC_STATUS, REG_NFC_OPS);
+
+	wait_op_done(TROP_US_DELAY, true);
+
+	*status = (raw_read(NFC_CONFIG1) & mask) >> 16;
+
+}
+#endif
+
+/*!
+ * This function requests the NFC to perform a read of the
+ * NAND device status and returns the current status.
+ *
+ * @return  device status
+ */
+static u16 get_dev_status(void)
+{
+#ifdef NFC_AUTO_MODE_ENABLE
+	int i;
+	u16 status = 0;
+	for (i = 0; i < num_of_interleave; i++) {
+
+		/* set ative cs */
+		NFC_SET_NFC_ACTIVE_CS(i);
+
+		/* FIXME, NFC Auto erase may have
+		 * problem, have to pollingit until
+		 * the nand get idle, otherwise
+		 * it may get error
+		 */
+		read_dev_status(&status);
+		if (status & NAND_STATUS_FAIL)
+			break;
+	}
+
+	return status;
+#else
+	volatile u16 *mainBuf = MAIN_AREA1;
+	u8 val = 1;
+	u16 ret;
+
+	/* Set ram buffer id */
+	NFC_SET_RBA(val);
+
+	/* Read status into main buffer */
+	raw_write(NFC_STATUS, REG_NFC_OPS);
+
+	/* Wait for operation to complete */
+	wait_op_done(TROP_US_DELAY, true);
+
+	/* Status is placed in first word of main buffer */
+	/* get status, then recovery area 1 data */
+	ret = *mainBuf;
+
+	return ret;
+#endif
+}
+
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN);
+	return;
+}
+
+/*
+ * Function to record the ECC corrected/uncorrected errors resulted
+ * after a page read. This NFC detects and corrects upto to 4 symbols
+ * of 9-bits each.
+ */
+static int mxc_check_ecc_status(struct mtd_info *mtd)
+{
+	u32 ecc_stat, err;
+	int no_subpages = 1;
+	int ret = 0;
+	u8 ecc_bit_mask = 0xf;
+
+	no_subpages = mtd->writesize >> 9;
+
+	no_subpages /= num_of_interleave;
+
+	ecc_stat = GET_NFC_ECC_STATUS();
+	do {
+		err = ecc_stat & ecc_bit_mask;
+		if (err == ecc_bit_mask) {
+			mtd->ecc_stats.failed++;
+			printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
+			return -1;
+		} else {
+			ret += err;
+		}
+		ecc_stat >>= 4;
+	} while (--no_subpages);
+
+	pr_debug("Correctable ECC Error(%d)\n", ret);
+
+	return ret;
+}
+
+/*
+ * Function to correct the detected errors. This NFC corrects all the errors
+ * detected. So this function just return 0.
+ */
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char * dat,
+				 u_char * read_ecc, u_char * calc_ecc)
+{
+	return 0;
+}
+
+/*
+ * Function to calculate the ECC for the data to be stored in the Nand device.
+ * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC
+ * CONTROL blocks are responsible for detection  and correction of up to
+ * 8 symbols of 9 bits each in 528 byte page.
+ * So this function is just return 0.
+ */
+
+static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
+				  u_char * ecc_code)
+{
+	return 0;
+}
+
+/*!
+ * This function id is used to read the data buffer from the NAND Flash. To
+ * read the data from NAND Flash first the data output cycle is initiated by
+ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
+ * then copied to buffer \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be read from NAND Flash
+ * @param       len     number of bytes to be read
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+	u16 col = g_nandfc_info.colAddr;
+
+	if (mtd->writesize) {
+
+		int j = mtd->writesize - col;
+		int n = mtd->oobsize + j;
+
+		n = min(n, len);
+
+		if (j > 0) {
+			if (n > j) {
+				memcpy(buf, &data_buf[col], j);
+				memcpy(buf + j, &oob_buf[0], n - j);
+			} else {
+				memcpy(buf, &data_buf[col], n);
+			}
+		} else {
+			col -= mtd->writesize;
+			memcpy(buf, &oob_buf[col], len);
+		}
+
+		/* update */
+		g_nandfc_info.colAddr += n;
+
+	} else {
+		/* At flash identify phase,
+		 * mtd->writesize has not been
+		 * set correctly, it should
+		 * be zero.And len will less 2
+		 */
+		memcpy(buf, &data_buf[col], len);
+
+		/* update */
+		g_nandfc_info.colAddr += len;
+	}
+
+}
+
+/*!
+ * This function reads byte from the NAND Flash
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ *
+ * @return    data read from the NAND Flash
+ */
+static uint8_t mxc_nand_read_byte(struct mtd_info *mtd)
+{
+	uint8_t ret;
+
+	/* Check for status request */
+	if (g_nandfc_info.bStatusRequest) {
+		return (get_dev_status() & 0xFF);
+	}
+
+	mxc_nand_read_buf(mtd, &ret, 1);
+
+	return ret;
+}
+
+/*!
+  * This function reads word from the NAND Flash
+  *
+  * @param     mtd     MTD structure for the NAND Flash
+  *
+  * @return    data read from the NAND Flash
+  */
+static u16 mxc_nand_read_word(struct mtd_info *mtd)
+{
+	u16 ret;
+
+	mxc_nand_read_buf(mtd, (uint8_t *) &ret, sizeof(u16));
+
+	return ret;
+}
+
+/*!
+ * This function reads byte from the NAND Flash
+ *
+ * @param     mtd     MTD structure for the NAND Flash
+ *
+ * @return    data read from the NAND Flash
+ */
+static u_char mxc_nand_read_byte16(struct mtd_info *mtd)
+{
+	/* Check for status request */
+	if (g_nandfc_info.bStatusRequest) {
+		return (get_dev_status() & 0xFF);
+	}
+
+	return mxc_nand_read_word(mtd) & 0xFF;
+}
+
+/*!
+ * This function writes data of length \b len from buffer \b buf to the NAND
+ * internal RAM buffer's MAIN area 0.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be written to NAND Flash
+ * @param       len     number of bytes to be written
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+			       const u_char * buf, int len)
+{
+	u16 col = g_nandfc_info.colAddr;
+	int j = mtd->writesize - col;
+	int n = mtd->oobsize + j;
+
+	n = min(n, len);
+
+	if (j > 0) {
+		if (n > j) {
+			memcpy(&data_buf[col], buf, j);
+			memcpy(&oob_buf[0], buf + j, n - j);
+		} else {
+			memcpy(&data_buf[col], buf, n);
+		}
+	} else {
+		col -= mtd->writesize;
+		memcpy(&oob_buf[col], buf, len);
+	}
+
+	/* update */
+	g_nandfc_info.colAddr += n;
+}
+
+/*!
+ * This function is used by the upper layer to verify the data in NAND Flash
+ * with the data in the \b buf.
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       buf     data to be verified
+ * @param       len     length of the data to be verified
+ *
+ * @return      -EFAULT if error else 0
+ *
+ */
+static int mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
+			       int len)
+{
+	u_char *s = data_buf;
+
+	const u_char *p = buf;
+
+	for (; len > 0; len--) {
+		if (*p++ != *s++)
+			return -EFAULT;
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is used by upper layer for select and deselect of the NAND
+ * chip
+ *
+ * @param       mtd     MTD structure for the NAND Flash
+ * @param       chip    val indicating select or deselect
+ */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+
+	switch (chip) {
+	case -1:
+		/* Disable the NFC clock */
+		clk_disable(nfc_clk);
+		break;
+	case 0 ... 7:
+		/* Enable the NFC clock */
+		clk_enable(nfc_clk);
+
+		NFC_SET_NFC_ACTIVE_CS(chip);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*
+ * Function to perform the address cycles.
+ */
+static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
+{
+#ifdef NFC_AUTO_MODE_ENABLE
+
+	if (page_addr != -1 && column != -1) {
+		u32 mask = 0xFFFF;
+		/* the column address */
+		raw_write(column & mask, NFC_FLASH_ADDR0);
+		raw_write((raw_read(NFC_FLASH_ADDR0) |
+			   ((page_addr & mask) << 16)), NFC_FLASH_ADDR0);
+		/* the row address */
+		raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) |
+			   ((page_addr & (mask << 16)) >> 16)),
+			  NFC_FLASH_ADDR8);
+	} else if (page_addr != -1) {
+		raw_write(page_addr, NFC_FLASH_ADDR0);
+		raw_write(0, NFC_FLASH_ADDR8);
+	}
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n",
+	      raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8));
+#else
+
+	u32 page_mask = g_page_mask;
+
+	if (column != -1) {
+		send_addr(column & 0xFF, true);
+		if (IS_2K_PAGE_NAND) {
+			/* another col addr cycle for 2k page */
+			send_addr((column >> 8) & 0xF, true);
+		} else if (IS_4K_PAGE_NAND) {
+			/* another col addr cycle for 4k page */
+			send_addr((column >> 8) & 0x1F, true);
+		}
+	}
+	if (page_addr != -1) {
+		do {
+			send_addr((page_addr & 0xff), true);
+			page_mask >>= 8;
+			page_addr >>= 8;
+		} while (page_mask != 0);
+	}
+#endif
+}
+
+/*!
+ * This function is used by the upper layer to write command to NAND Flash for
+ * different operations to be carried out on NAND Flash
+ *
+ * @param       mtd             MTD structure for the NAND Flash
+ * @param       command         command for NAND Flash
+ * @param       column          column offset for the page read
+ * @param       page_addr       page to be read from NAND Flash
+ */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+			     int column, int page_addr)
+{
+	bool useirq = true;
+
+	DEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+	      command, column, page_addr);
+	/*
+	 * Reset command state information
+	 */
+	g_nandfc_info.bStatusRequest = false;
+
+	/*
+	 * Command pre-processing step
+	 */
+	switch (command) {
+	case NAND_CMD_STATUS:
+		g_nandfc_info.colAddr = 0;
+		g_nandfc_info.bStatusRequest = true;
+		break;
+
+	case NAND_CMD_READ0:
+		g_nandfc_info.colAddr = column;
+		break;
+
+	case NAND_CMD_READOOB:
+		g_nandfc_info.colAddr = column;
+		command = NAND_CMD_READ0;
+		break;
+
+	case NAND_CMD_SEQIN:
+		if (column != 0) {
+
+			/* FIXME: before send SEQIN command for
+			 * partial write,We need read one page out.
+			 * FSL NFC does not support partial write
+			 * It alway send out 512+ecc+512+ecc ...
+			 * for large page nand flash. But for small
+			 * page nand flash, it did support SPARE
+			 * ONLY operation. But to make driver
+			 * simple. We take the same as large page,read
+			 * whole page out and update. As for MLC nand
+			 * NOP(num of operation) = 1. Partial written
+			 * on one programed page is not allowed! We
+			 * can't limit it on the driver, it need the
+			 * upper layer applicaiton take care it
+			 */
+
+			mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
+		}
+
+		g_nandfc_info.colAddr = column;
+		column = 0;
+
+		break;
+
+	case NAND_CMD_PAGEPROG:
+#ifndef NFC_AUTO_MODE_ENABLE
+		/* FIXME:the NFC interal buffer
+		 * access has some limitation, it
+		 * does not allow byte access. To
+		 * make the code simple and ease use
+		 * not every time check the address
+		 * alignment.Use the temp buffer
+		 * to accomadate the data.since We
+		 * know data_buf will be at leat 4
+		 * byte alignment, so we can use
+		 * memcpy safely
+		 */
+		nfc_memcpy(MAIN_AREA0, data_buf, mtd->writesize);
+		copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, false);
+		mxc_nand_bi_swap(mtd);
+#endif
+
+		if (IS_LARGE_PAGE_NAND)
+			PROG_PAGE();
+		else
+			send_prog_page(0);
+
+		break;
+
+	case NAND_CMD_ERASE1:
+		break;
+	case NAND_CMD_ERASE2:
+		break;
+	}
+
+	/*
+	 * Write out the command to the device.
+	 */
+	send_cmd(mtd, command, useirq);
+
+	mxc_do_addr_cycle(mtd, column, page_addr);
+
+	/*
+	 * Command post-processing step
+	 */
+	switch (command) {
+
+	case NAND_CMD_READOOB:
+	case NAND_CMD_READ0:
+		if (IS_LARGE_PAGE_NAND) {
+			/* send read confirm command */
+			send_cmd(mtd, NAND_CMD_READSTART, true);
+			/* read for each AREA */
+			READ_PAGE();
+		} else {
+			send_read_page(0);
+		}
+
+#ifndef NFC_AUTO_MODE_ENABLE
+		/* FIXME, the NFC interal buffer
+		 * access has some limitation, it
+		 * does not allow byte access. To
+		 * make the code simple and ease use
+		 * not every time check the address
+		 * alignment.Use the temp buffer
+		 * to accomadate the data.since We
+		 * know data_buf will be at leat 4
+		 * byte alignment, so we can use
+		 * memcpy safely
+		 */
+		mxc_nand_bi_swap(mtd);
+		nfc_memcpy(data_buf, MAIN_AREA0, mtd->writesize);
+		copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, true);
+#endif
+
+		break;
+
+	case NAND_CMD_READID:
+		send_read_id();
+		g_nandfc_info.colAddr = column;
+		nfc_memcpy(data_buf, MAIN_AREA0, 2048);
+
+		break;
+	}
+}
+
+static int mxc_nand_read_oob(struct mtd_info *mtd,
+			     struct nand_chip *chip, int page, int sndcmd)
+{
+	if (sndcmd) {
+
+		chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+		sndcmd = 0;
+	}
+
+	memcpy(chip->oob_poi, oob_buf, mtd->oobsize);
+
+	return sndcmd;
+}
+
+static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+			      uint8_t * buf)
+{
+
+#ifndef NFC_AUTO_MODE_ENABLE
+	mxc_check_ecc_status(mtd);
+#endif
+
+	memcpy(buf, data_buf, mtd->writesize);
+	memcpy(chip->oob_poi, oob_buf, mtd->oobsize);
+
+	return 0;
+}
+
+static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t * buf)
+{
+	memcpy(data_buf, buf, mtd->writesize);
+	memcpy(oob_buf, chip->oob_poi, mtd->oobsize);
+
+}
+
+/* Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks. */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr smallpage_memorybased = {
+	.options = NAND_BBT_SCAN2NDPAGE,
+	.offs = 5,
+	.len = 1,
+	.pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern
+};
+
+/* Generic flash bbt decriptors
+*/
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs = 0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+static int mxc_nand_scan_bbt(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	g_page_mask = this->pagemask;
+
+	if (IS_2K_PAGE_NAND) {
+		NFC_SET_NFMS(1 << NFMS_NF_PG_SZ);
+		this->ecc.layout = &nand_hw_eccoob_2k;
+	} else if (IS_4K_PAGE_NAND) {
+		NFC_SET_NFMS(1 << NFMS_NF_PG_SZ);
+		this->ecc.layout = &nand_hw_eccoob_4k;
+	} else {
+		this->ecc.layout = &nand_hw_eccoob_512;
+	}
+
+	/* propagate ecc.layout to mtd_info */
+	mtd->ecclayout = this->ecc.layout;
+
+	/* jffs2 not write oob */
+	mtd->flags &= ~MTD_OOB_WRITEABLE;
+
+	/* fix up the offset */
+	largepage_memorybased.offs = BAD_BLK_MARKER_OOB_OFFS;
+
+	/* keep compatible for bbt table with old soc */
+	if (cpu_is_mx53()) {
+		bbt_mirror_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2;
+		bbt_main_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2;
+	}
+
+	/* use flash based bbt */
+	this->bbt_td = &bbt_main_descr;
+	this->bbt_md = &bbt_mirror_descr;
+
+	/* update flash based bbt */
+	this->options |= NAND_USE_FLASH_BBT;
+
+	if (!this->badblock_pattern) {
+		this->badblock_pattern = (mtd->writesize > 512) ?
+		    &largepage_memorybased : &smallpage_memorybased;
+	}
+
+	/* Build bad block table */
+	return nand_scan_bbt(mtd, this->badblock_pattern);
+}
+
+static int mxc_get_resources(struct platform_device *pdev)
+{
+	struct resource *r;
+	int error = 0;
+
+#define	MXC_NFC_NO_IP_REG \
+	(cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx32() || cpu_is_mx35())
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		error = -ENXIO;
+		goto out_0;
+	}
+	nfc_axi_base = ioremap(r->start, resource_size(r));
+
+	if (!MXC_NFC_NO_IP_REG) {
+		r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!r) {
+			error = -ENXIO;
+			goto out_1;
+		}
+	}
+	nfc_ip_base = ioremap(r->start, resource_size(r));
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!r) {
+		error = -ENXIO;
+		goto out_2;
+	}
+
+	init_waitqueue_head(&irq_waitq);
+	error = request_irq(r->start, mxc_nfc_irq, 0, "mxc_nd", NULL);
+	if (error)
+		goto out_3;
+
+	return 0;
+out_3:
+out_2:
+	if (!MXC_NFC_NO_IP_REG)
+		iounmap(nfc_ip_base);
+out_1:
+	iounmap(nfc_axi_base);
+out_0:
+	return error;
+}
+
+static void mxc_nfc_init(void)
+{
+	/* Disable interrupt */
+	raw_write((raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK), REG_NFC_INTRRUPT);
+
+	/* disable spare enable */
+	raw_write(raw_read(REG_NFC_SP_EN) & ~NFC_SP_EN, REG_NFC_SP_EN);
+
+	/* Unlock the internal RAM Buffer */
+	raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS);
+
+	if (!(cpu_is_mx53())) {
+		/* Blocks to be unlocked */
+		UNLOCK_ADDR(0x0, 0xFFFF);
+
+		/* Unlock Block Command for given address range */
+		raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
+	}
+
+	/* Enable symetric mode by default except mx37TO1.0 */
+	if (!(cpu_is_mx37_rev(CHIP_REV_1_0) == 1))
+		raw_write(raw_read(REG_NFC_ONE_CYCLE) |
+			  NFC_ONE_CYCLE, REG_NFC_ONE_CYCLE);
+}
+
+static int mxc_alloc_buf(void)
+{
+	int err = 0;
+
+	data_buf = kzalloc(NAND_MAX_PAGESIZE, GFP_KERNEL);
+	if (!data_buf) {
+		printk(KERN_ERR "%s: failed to allocate data_buf\n", __func__);
+		err = -ENOMEM;
+		goto out;
+	}
+	oob_buf = kzalloc(NAND_MAX_OOBSIZE, GFP_KERNEL);
+	if (!oob_buf) {
+		printk(KERN_ERR "%s: failed to allocate oob_buf\n", __func__);
+		err = -ENOMEM;
+		goto out;
+	}
+
+      out:
+	return err;
+}
+
+static void mxc_free_buf(void)
+{
+	kfree(data_buf);
+	kfree(oob_buf);
+}
+
+int nand_scan_mid(struct mtd_info *mtd)
+{
+	int i;
+	uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT];
+	struct nand_chip *this = mtd->priv;
+	struct nand_device_info  *dev_info;
+
+	if (!IS_LARGE_PAGE_NAND)
+		return 0;
+
+	/* Read ID bytes from the first NAND Flash chip. */
+	this->select_chip(mtd, 0);
+
+	this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	for (i = 0; i < NAND_DEVICE_ID_BYTE_COUNT; i++)
+		id_bytes[i] = this->read_byte(mtd);
+
+	/* Get information about this device, based on the ID bytes. */
+	dev_info = nand_device_get_info(id_bytes);
+
+	/* Check if we understand this device. */
+	if (!dev_info) {
+		printk(KERN_ERR "Unrecognized NAND Flash device.\n");
+		return !0;
+	}
+
+	/* Correct mtd setting */
+	this->chipsize = dev_info->chip_size_in_bytes;
+	mtd->size = dev_info->chip_size_in_bytes * this->numchips;
+	mtd->writesize = dev_info->page_total_size_in_bytes & ~0x3ff;
+	mtd->oobsize = dev_info->page_total_size_in_bytes & 0x3ff;
+	mtd->erasesize = dev_info->block_size_in_pages * mtd->writesize;
+
+	/* limit to 2G size due to Kernel
+	 * larger 4G space support,need fix
+	 * it later
+	 */
+	if ((u32)mtd->size == 0) {
+		mtd->size = (u32)(1 << 31);
+		this->numchips = 1;
+		this->chipsize = mtd->size;
+	}
+
+	/* Calculate the address shift from the page size */
+	this->page_shift = ffs(mtd->writesize) - 1;
+	/* Convert chipsize to number of pages per chip -1. */
+	this->pagemask = (this->chipsize >> this->page_shift) - 1;
+
+	this->bbt_erase_shift = this->phys_erase_shift =
+		ffs(mtd->erasesize) - 1;
+	this->chip_shift = ffs(this->chipsize) - 1;
+
+	return 0;
+}
+
+/*!
+ * show_device_disable_bi_swap()
+ * Shows the value of the 'disable_bi_swap' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer that will receive a representation of the attribute.
+ */
+static ssize_t show_device_disable_bi_swap(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%d\n", mxc_nand_data->disable_bi_swap);
+}
+
+/*!
+ * store_device_disable_bi_swap()
+ * Sets the value of the 'disable_bi_swap' flag.
+ *
+ * @dev:   The device of interest.
+ * @attr:  The attribute of interest.
+ * @buf:   A buffer containing a new attribute value.
+ * @size:  The size of the buffer.
+ */
+static ssize_t store_device_disable_bi_swap(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	const char *p = buf;
+	unsigned long v;
+
+	/* Try to make sense of what arrived from user space. */
+
+	if (strict_strtoul(p, 0, &v) < 0)
+		return size;
+
+	if (v > 0)
+		v = 1;
+	mxc_nand_data->disable_bi_swap = v;
+	return size;
+
+}
+
+static DEVICE_ATTR(disable_bi_swap, 0644,
+	show_device_disable_bi_swap, store_device_disable_bi_swap);
+static struct device_attribute *device_attributes[] = {
+	&dev_attr_disable_bi_swap,
+};
+/*!
+ * manage_sysfs_files() - Creates/removes sysfs files for this device.
+ *
+ * @create: create/remove the sys entry.
+ */
+static void manage_sysfs_files(int create)
+{
+	struct device *dev = mxc_nand_data->dev;
+	int error;
+	unsigned int i;
+	struct device_attribute **attr;
+
+	for (i = 0, attr = device_attributes;
+			i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+		if (create) {
+			error = device_create_file(dev, *attr);
+			if (error) {
+				while (--attr >= device_attributes)
+					device_remove_file(dev, *attr);
+				return;
+			}
+		} else {
+			device_remove_file(dev, *attr);
+		}
+	}
+
+}
+
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and
+ *                remove functions
+ *
+ * @return  The function always returns 0.
+ */
+static int __init mxcnd_probe(struct platform_device *pdev)
+{
+	struct nand_chip *this;
+	struct mtd_info *mtd;
+	struct flash_platform_data *flash = pdev->dev.platform_data;
+	int nr_parts = 0, err = 0;
+
+	/* get the resource */
+	err = mxc_get_resources(pdev);
+	if (err)
+		goto out;
+
+	/* init the nfc */
+	mxc_nfc_init();
+
+	/* init data buf */
+	if (mxc_alloc_buf())
+		goto out;
+
+	/* Allocate memory for MTD device structure and private data */
+	mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL);
+	if (!mxc_nand_data) {
+		printk(KERN_ERR "%s: failed to allocate mtd_info\n",
+		       __FUNCTION__);
+		err = -ENOMEM;
+		goto out;
+	}
+
+	memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
+
+	mxc_nand_data->dev = &pdev->dev;
+	/* structures must be linked */
+	this = &mxc_nand_data->nand;
+	mtd = &mxc_nand_data->mtd;
+	mtd->priv = this;
+	mtd->owner = THIS_MODULE;
+
+	this->priv = mxc_nand_data;
+	this->cmdfunc = mxc_nand_command;
+	this->select_chip = mxc_nand_select_chip;
+	this->read_byte = mxc_nand_read_byte;
+	this->read_word = mxc_nand_read_word;
+	this->write_buf = mxc_nand_write_buf;
+	this->read_buf = mxc_nand_read_buf;
+	this->verify_buf = mxc_nand_verify_buf;
+	this->scan_bbt = mxc_nand_scan_bbt;
+
+	/* NAND bus width determines access funtions used by upper layer */
+	if (flash->width == 2) {
+		this->read_byte = mxc_nand_read_byte16;
+		this->options |= NAND_BUSWIDTH_16;
+		NFC_SET_NFMS(1 << NFMS_NF_DWIDTH);
+	} else {
+		NFC_SET_NFMS(0);
+	}
+
+	nfc_clk = clk_get(&pdev->dev, "nfc_clk");
+	clk_enable(nfc_clk);
+
+	if (hardware_ecc) {
+		this->ecc.read_page = mxc_nand_read_page;
+		this->ecc.write_page = mxc_nand_write_page;
+		this->ecc.read_oob = mxc_nand_read_oob;
+		this->ecc.layout = &nand_hw_eccoob_512;
+		this->ecc.calculate = mxc_nand_calculate_ecc;
+		this->ecc.hwctl = mxc_nand_enable_hwecc;
+		this->ecc.correct = mxc_nand_correct_data;
+		this->ecc.mode = NAND_ECC_HW;
+		this->ecc.size = 512;
+		this->ecc.bytes = 9;
+		raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN),
+			  REG_NFC_ECC_EN);
+	} else {
+		this->ecc.mode = NAND_ECC_SOFT;
+		raw_write((raw_read(REG_NFC_ECC_EN) & ~NFC_ECC_EN),
+			  REG_NFC_ECC_EN);
+	}
+
+	/* config the gpio */
+	if (flash->init)
+		flash->init();
+
+	/* Reset NAND */
+	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+	/* Scan to find existence of the device */
+	if (nand_scan_ident(mtd, NFC_GET_MAXCHIP_SP())
+		|| nand_scan_mid(mtd)
+		|| nand_scan_tail(mtd)) {
+		DEBUG(MTD_DEBUG_LEVEL0,
+		      "MXC_ND2: Unable to find any NAND device.\n");
+		err = -ENXIO;
+		goto out_1;
+	}
+
+	/* Register the partitions */
+#ifdef CONFIG_MTD_PARTITIONS
+	nr_parts =
+	    parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0);
+	if (nr_parts > 0)
+		add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts);
+	else if (flash->parts)
+		add_mtd_partitions(mtd, flash->parts, flash->nr_parts);
+	else
+#endif
+	{
+		pr_info("Registering %s as whole device\n", mtd->name);
+		add_mtd_device(mtd);
+	}
+
+	/* Create sysfs entries for this device. */
+	manage_sysfs_files(true);
+
+	platform_set_drvdata(pdev, mtd);
+
+	return 0;
+
+      out_1:
+	kfree(mxc_nand_data);
+      out:
+	return err;
+
+}
+
+ /*!
+  * Dissociates the driver from the device.
+  *
+  * @param   pdev  the device structure used to give information on which
+  *
+  * @return  The function always returns 0.
+  */
+
+static int __exit mxcnd_remove(struct platform_device *pdev)
+{
+	struct mtd_info *mtd = platform_get_drvdata(pdev);
+	struct flash_platform_data *flash = pdev->dev.platform_data;
+
+	if (flash->exit)
+		flash->exit();
+
+	manage_sysfs_files(false);
+	mxc_free_buf();
+
+	clk_disable(nfc_clk);
+	clk_put(nfc_clk);
+	platform_set_drvdata(pdev, NULL);
+
+	if (mxc_nand_data) {
+		nand_release(mtd);
+		free_irq(MXC_INT_NANDFC, NULL);
+		kfree(mxc_nand_data);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This function is called to put the NAND in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device information structure
+ *
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+
+static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND suspend\n");
+
+	/* Disable the NFC clock */
+	clk_disable(nfc_clk);
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the NAND back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device information structure
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxcnd_resume(struct platform_device *pdev)
+{
+	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND resume\n");
+
+	/* Enable the NFC clock */
+	clk_enable(nfc_clk);
+
+	return 0;
+}
+
+#else
+#define mxcnd_suspend   NULL
+#define mxcnd_resume    NULL
+#endif				/* CONFIG_PM */
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcnd_driver = {
+	.driver = {
+		   .name = "mxc_nandv2_flash",
+		   },
+	.probe = mxcnd_probe,
+	.remove = __exit_p(mxcnd_remove),
+	.suspend = mxcnd_suspend,
+	.resume = mxcnd_resume,
+};
+
+/*!
+ * Main initialization routine
+ * @return  0 if successful; non-zero otherwise
+ */
+static int __init mxc_nd_init(void)
+{
+	/* Register the device driver structure. */
+	pr_info("MXC MTD nand Driver %s\n", DVR_VER);
+	if (platform_driver_register(&mxcnd_driver) != 0) {
+		printk(KERN_ERR "Driver register failed for mxcnd_driver\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+/*!
+ * Clean up routine
+ */
+static void __exit mxc_nd_cleanup(void)
+{
+	/* Unregister the device structure */
+	platform_driver_unregister(&mxcnd_driver);
+}
+
+module_init(mxc_nd_init);
+module_exit(mxc_nd_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC NAND MTD driver Version 2-5");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/mxc_nd2.h b/drivers/mtd/nand/mxc_nd2.h
new file mode 100644
index 000000000000..c80970fdc95a
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nd2.h
@@ -0,0 +1,712 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_nd2.h
+ *
+ * @brief This file contains the NAND Flash Controller register information.
+ *
+ *
+ * @ingroup NAND_MTD
+ */
+
+#ifndef __MXC_ND2_H__
+#define __MXC_ND2_H__
+
+#include <mach/hardware.h>
+
+#define IS_2K_PAGE_NAND         ((mtd->writesize / num_of_interleave) \
+						== NAND_PAGESIZE_2KB)
+#define IS_4K_PAGE_NAND         ((mtd->writesize / num_of_interleave) \
+						== NAND_PAGESIZE_4KB)
+#define IS_LARGE_PAGE_NAND      ((mtd->writesize / num_of_interleave) > 512)
+
+#define GET_NAND_OOB_SIZE	(mtd->oobsize / num_of_interleave)
+#define GET_NAND_PAGE_SIZE      (mtd->writesize / num_of_interleave)
+
+#define NAND_PAGESIZE_2KB	2048
+#define NAND_PAGESIZE_4KB	4096
+
+/*
+ * main area for bad block marker is in the last data section
+ * the spare area for swapped bad block marker is the second
+ * byte of last spare section
+ */
+#define NAND_SECTIONS        (GET_NAND_PAGE_SIZE >> 9)
+#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1)
+#define NAND_CHUNKS	     (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION))
+
+#define BAD_BLK_MARKER_MAIN_OFFS \
+	(GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION)
+
+#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN)
+
+#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION)
+
+#define BAD_BLK_MARKER_MAIN  \
+	((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS)
+
+#define BAD_BLK_MARKER_SP  \
+	((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS)
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3
+/*
+ * For V3 NFC registers Definition
+ */
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1)	/* mx37 */
+#define MXC_INT_NANDFC			MXC_INT_EMI
+#define NFC_FLASH_ADDR_CMD		(nfc_axi_base + 0x1E00)
+#define NFC_CONFIG1			(nfc_axi_base + 0x1E04)
+#define NFC_ECC_STATUS_RESULT		(nfc_axi_base + 0x1E08)
+#define LAUNCH_NFC			(nfc_axi_base + 0x1E0c)
+#define NFC_WRPROT			(nfc_ip_base + 0x00)
+#define NFC_WRPROT_UNLOCK_BLK_ADD0	(nfc_ip_base + 0x04)
+#define NFC_CONFIG2			(nfc_ip_base + 0x14)
+#define NFC_IPC				(nfc_ip_base + 0x18)
+#elif defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)	/* mx51 */
+#define MXC_INT_NANDFC			MXC_INT_NFC
+#define NFC_AUTO_MODE_ENABLE
+#define NFC_FLASH_CMD			(nfc_axi_base + 0x1E00)
+#define NFC_FLASH_ADDR0      		(nfc_axi_base + 0x1E04)
+#define NFC_FLASH_ADDR8			(nfc_axi_base + 0x1E24)
+#define NFC_CONFIG1         		(nfc_axi_base + 0x1E34)
+#define NFC_ECC_STATUS_RESULT		(nfc_axi_base + 0x1E38)
+#define NFC_ECC_STATUS_SUM		(nfc_axi_base + 0x1E3C)
+#define LAUNCH_NFC			(nfc_axi_base + 0x1E40)
+#define NFC_WRPROT			(nfc_ip_base + 0x00)
+#define NFC_WRPROT_UNLOCK_BLK_ADD0	(nfc_ip_base + 0x04)
+#define NFC_CONFIG2			(nfc_ip_base + 0x24)
+#define NFC_CONFIG3			(nfc_ip_base + 0x28)
+#define NFC_IPC				(nfc_ip_base + 0x2C)
+#define NFC_DELAY_LINE			(nfc_ip_base + 0x34)
+#else				/* skye */
+#define NFC_FLASH_ADDR_CMD		(nfc_axi_base + 0xE00)
+#define NFC_CONFIG1			(nfc_axi_base + 0xE04)
+#define NFC_ECC_STATUS_RESULT		(nfc_axi_base + 0xE08)
+#define LAUNCH_NFC			(nfc_axi_base + 0xE0C)
+#define NFC_WRPROT			(nfc_ip_base + 0x00)
+#define NFC_WRPROT_UNLOCK_BLK_ADD0	(nfc_ip_base + 0x04)
+#define NFC_CONFIG2			(nfc_ip_base + 0x14)
+#define NFC_IPC				(nfc_ip_base + 0x18)
+#endif
+/*!
+ * Addresses for NFC RAM BUFFER Main area 0
+ */
+#define MAIN_AREA0        		((u16 *)(nfc_axi_base + 0x000))
+#define MAIN_AREA1        		((u16 *)(nfc_axi_base + 0x200))
+
+/*!
+ * Addresses for NFC SPARE BUFFER Spare area 0
+ */
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) ||	\
+    defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
+#define SPARE_AREA0       		((u16 *)(nfc_axi_base + 0x1000))
+#define SPARE_LEN			64
+#define SPARE_COUNT			8
+#define SPARE_SIZE			(SPARE_LEN * SPARE_COUNT)
+#else
+#define SPARE_AREA0       		((u16 *)(nfc_axi_base + 0x800))
+#define SPARE_LEN			16
+#define SPARE_COUNT			4
+#define SPARE_SIZE			(SPARE_LEN * SPARE_COUNT)
+#endif
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) ||	\
+    defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
+#define NFC_SPAS_WIDTH 8
+#define NFC_SPAS_SHIFT 16
+
+#define NFC_SET_SPAS(v)			\
+	raw_write((((raw_read(NFC_CONFIG2) & \
+	NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \
+	NFC_CONFIG2)
+
+#define NFC_SET_ECC_MODE(v)		\
+do { \
+	if (cpu_is_mx53() > 0) { \
+		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(3 << 6)) | \
+					NFC_ECC_MODE_16), NFC_CONFIG2); \
+		else \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(3 << 6)) & \
+					NFC_ECC_MODE_4), NFC_CONFIG2); \
+	} else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { \
+		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6)) | \
+					NFC_ECC_MODE_8), NFC_CONFIG2); \
+		else \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6)) & \
+					NFC_ECC_MODE_4), NFC_CONFIG2); \
+	} else { \
+		if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6))), NFC_CONFIG2); \
+		else \
+			raw_write(((raw_read(NFC_CONFIG2) & \
+					~(1 << 6)) | \
+					NFC_ECC_MODE_4), NFC_CONFIG2); \
+	} \
+} while (0)
+
+#define WRITE_NFC_IP_REG(val,reg) 			\
+	do {	 					\
+		raw_write(raw_read(NFC_IPC) | NFC_IPC_CREQ, NFC_IPC);	\
+		while (!(raw_read(NFC_IPC) & NFC_IPC_ACK)) \
+			; \
+		raw_write(val, reg);			\
+		raw_write(raw_read(NFC_IPC) & ~NFC_IPC_CREQ, NFC_IPC);	\
+	} while(0)
+
+#else
+#define NFC_SET_SPAS(v)
+#define NFC_SET_ECC_MODE(v)
+#define NFC_SET_NFMS(v)	(NFMS |= (v))
+
+#define WRITE_NFC_IP_REG(val,reg) \
+	raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT),  \
+	REG_NFC_OPS_STAT)
+#endif
+
+#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT);
+
+/*!
+ * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for
+ * Specific operation
+ */
+#define NFC_CMD            		0x1
+#define NFC_ADDR           		0x2
+#define NFC_INPUT          		0x4
+#define NFC_OUTPUT         		0x8
+#define NFC_ID             		0x10
+#define NFC_STATUS         		0x20
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2	/* mx51 */
+#define NFC_AUTO_PROG 			0x40
+#define NFC_AUTO_READ           	0x80
+#define NFC_AUTO_ERASE          	0x200
+#define NFC_COPY_BACK_0			0x400
+#define NFC_COPY_BACK_1         	0x800
+#define NFC_AUTO_STATE          	0x1000
+#endif
+
+/* Bit Definitions for NFC_IPC*/
+#define NFC_OPS_STAT			(1 << 31)
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2	/* mx51 */
+#define NFC_OP_DONE			(1 << 30)
+#define NFC_RB				(1 << 28)
+#define NFC_PS_WIDTH 			2
+#define NFC_PS_SHIFT 			0
+#define NFC_PS_512	 		0
+#define NFC_PS_2K	 		1
+#define NFC_PS_4K    			2
+#else
+#define NFC_RB				(1 << 29)
+#endif
+
+#define NFC_ONE_CYCLE			(1 << 2)
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2	/* mx51 */
+#define NFC_INT_MSK			(1 << 15)
+#define NFC_AUTO_PROG_DONE_MSK 		(1 << 14)
+#define NFC_NUM_ADDR_PHASE1_WIDTH   	2
+#define NFC_NUM_ADDR_PHASE1_SHIFT  	12
+
+#define NFC_NUM_ADDR_PHASE0_WIDTH 	1
+#define NFC_NUM_ADDR_PHASE0_SHIFT  	5
+
+#define NFC_ONE_LESS_PHASE1 		0
+#define NFC_TWO_LESS_PHASE1 		1
+
+#define NFC_FLASH_ADDR_SHIFT		0
+#else
+#define NFC_INT_MSK			(1 << 4)
+#define NFC_BIG				(1 << 5)
+#define NFC_FLASH_ADDR_SHIFT		16
+#endif
+
+#define NFC_UNLOCK_END_ADDR_SHIFT	16
+
+/* Bit definition for NFC_CONFIGRATION_1 */
+#define NFC_SP_EN			(1 << 0)
+#define NFC_CE				(1 << 1)
+#define NFC_RST				(1 << 2)
+#define NFC_ECC_EN			(1 << 3)
+
+#define NFC_FIELD_RESET(width, shift) ~(((1 << (width)) - 1) << (shift))
+
+#define NFC_RBA_SHIFT       		4
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) ||	\
+    defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)	/* mx51 */
+#define NFC_RBA_WIDTH			3
+#else
+#define NFC_RBA_WIDTH			2
+#endif
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)	/* mx51 */
+#define NFC_ITERATION_SHIFT 8
+#define NFC_ITERATION_WIDTH 4
+#define NFC_ACTIVE_CS_SHIFT 12
+#define NFC_ACTIVE_CS_WIDTH 3
+/* bit definition for CONFIGRATION3 */
+#define NFC_NO_SDMA			(1 << 20)
+#define NFC_FMP_SHIFT 			16
+#define NFC_FMP_WIDTH			4
+#define NFC_RBB_MODE			(1 << 15)
+#define NFC_NUM_OF_DEVICES_SHIFT 	12
+#define NFC_NUM_OF_DEVICES_WIDTH 	4
+#define NFC_DMA_MODE_SHIFT 		11
+#define NFC_DMA_MODE_WIDTH  		1
+#define NFC_SBB_SHIFT 			8
+#define NFC_SBB_WIDTH 			3
+#define NFC_BIG				(1 << 7)
+#define NFC_SB2R_SHIFT 			4
+#define NFC_SB2R_WIDTH			3
+#define NFC_FW_SHIFT    		3
+#define NFC_FW_WIDTH 			1
+#define NFC_TOO				(1 << 2)
+#define NFC_ADD_OP_SHIFT 		0
+#define NFC_ADD_OP_WIDTH		2
+#define NFC_FW_8 			1
+#define NFC_FW_16			0
+#define NFC_ST_CMD_SHITF		24
+#define NFC_ST_CMD_WIDTH		8
+#endif
+
+#define NFC_PPB_32			(0 << 7)
+#define NFC_PPB_64			(1 << 7)
+#define NFC_PPB_128			(2 << 7)
+#define NFC_PPB_256			(3 << 7)
+#define NFC_PPB_RESET			~(3 << 7)
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
+#define NFC_BLS_LOCKED			(0 << 6)
+#define NFC_BLS_LOCKED_DEFAULT		(1 << 6)
+#define NFC_BLS_UNLCOKED		(2 << 6)
+#define NFC_BLS_RESET			(~(3 << 6))
+#else
+#define NFC_BLS_LOCKED                  (0 << 16)
+#define NFC_BLS_LOCKED_DEFAULT          (1 << 16)
+#define NFC_BLS_UNLCOKED                (2 << 16)
+#define NFC_BLS_RESET                   (~(3 << 16))
+#endif
+
+#define NFC_WPC_LOCK_TIGHT		1
+#define NFC_WPC_LOCK			(1 << 1)
+#define NFC_WPC_UNLOCK			(1 << 2)
+#define NFC_WPC_RESET			~(7)
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \
+    defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
+#define NFC_ECC_MODE_4    		(0x0 << 6)
+#define NFC_ECC_MODE_8			(0x1 << 6)
+#define NFC_ECC_MODE_14                 (0x3 << 6)
+#define NFC_ECC_MODE_16                 (0x3 << 6)
+#define NFC_SPAS_16			8
+#define NFC_SPAS_64		 	32
+#define NFC_SPAS_128			64
+#define NFC_SPAS_112			56
+#define NFC_SPAS_218		 	109
+#define NFC_IPC_CREQ			(1 << 0)
+#define NFC_IPC_ACK			(1 << 1)
+#endif
+
+#define REG_NFC_OPS_STAT		NFC_IPC
+#define REG_NFC_INTRRUPT		NFC_CONFIG2
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2
+#define REG_NFC_FLASH_ADDR		NFC_FLASH_ADDR0
+#define REG_NFC_FLASH_CMD		NFC_FLASH_CMD
+#else
+#define REG_NFC_FLASH_ADDR		NFC_FLASH_ADDR_CMD
+#define REG_NFC_FLASH_CMD		NFC_FLASH_ADDR_CMD
+#endif
+#define REG_NFC_OPS			LAUNCH_NFC
+#define REG_NFC_SET_RBA			NFC_CONFIG1
+#define REG_NFC_RB			NFC_IPC
+#define REG_NFC_ECC_EN			NFC_CONFIG2
+#define REG_NFC_ECC_STATUS_RESULT	NFC_ECC_STATUS_RESULT
+#define REG_NFC_CE			NFC_CONFIG1
+#define REG_NFC_RST			NFC_CONFIG1
+#define REG_NFC_PPB			NFC_CONFIG2
+#define REG_NFC_SP_EN			NFC_CONFIG1
+#define REG_NFC_BLS			NFC_WRPROT
+#define REG_UNLOCK_BLK_ADD0		NFC_WRPROT_UNLOCK_BLK_ADD0
+#define REG_UNLOCK_BLK_ADD1		NFC_WRPROT_UNLOCK_BLK_ADD1
+#define REG_UNLOCK_BLK_ADD2		NFC_WRPROT_UNLOCK_BLK_ADD2
+#define REG_UNLOCK_BLK_ADD3		NFC_WRPROT_UNLOCK_BLK_ADD3
+#define REG_NFC_WPC			NFC_WRPROT
+#define REG_NFC_ONE_CYCLE		NFC_CONFIG2
+
+/* NFC V3 Specific MACRO functions definitions */
+#define raw_write(v,a)		__raw_writel(v,a)
+#define raw_read(a)		__raw_readl(a)
+
+/* Set RBA buffer id*/
+#define NFC_SET_RBA(val)       \
+	raw_write((raw_read(REG_NFC_SET_RBA) & \
+	(NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \
+	((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA);
+
+#define NFC_SET_PS(val)       \
+	raw_write((raw_read(NFC_CONFIG2) & \
+	(NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \
+	((val) << NFC_PS_SHIFT), NFC_CONFIG2);
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2
+#define UNLOCK_ADDR(start_addr,end_addr)     \
+{ \
+	int i = 0; \
+	for (; i < NAND_MAX_CHIPS; i++)  \
+	raw_write(start_addr | \
+	(end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \
+	REG_UNLOCK_BLK_ADD0 + (i << 2)); \
+}
+#define NFC_SET_NFC_ACTIVE_CS(val) \
+	raw_write((raw_read(NFC_CONFIG1) & \
+	(NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \
+	((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1);
+
+#define NFC_GET_MAXCHIP_SP() 		8
+
+#else
+#define UNLOCK_ADDR(start_addr,end_addr)     \
+	raw_write(start_addr | \
+	(end_addr << NFC_UNLOCK_END_ADDR_SHIFT), REG_UNLOCK_BLK_ADD0);
+
+#define NFC_SET_NFC_ACTIVE_CS(val)
+#define NFC_GET_MAXCHIP_SP() 		1
+#endif
+
+#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val )
+#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val )
+#define CHECK_NFC_RB    raw_read(REG_NFC_RB) & NFC_RB
+
+#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2)
+#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \
+	raw_write((raw_read(NFC_CONFIG2) & \
+	(NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \
+	NFC_NUM_ADDR_PHASE1_SHIFT))) | \
+	((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2);
+
+#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \
+	raw_write((raw_read(NFC_CONFIG2) & \
+	(NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \
+	NFC_NUM_ADDR_PHASE0_SHIFT))) | \
+	((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2);
+
+#define NFC_SET_NFC_ITERATION(val) \
+	raw_write((raw_read(NFC_CONFIG1) & \
+	(NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \
+	((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1);
+
+#define NFC_SET_FW(val) \
+	raw_write((raw_read(NFC_CONFIG3) & \
+	(NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \
+	((val) << NFC_FW_SHIFT), NFC_CONFIG3);
+
+#define NFC_SET_NUM_OF_DEVICE(val) \
+	raw_write((raw_read(NFC_CONFIG3) & \
+	(NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \
+	NFC_NUM_OF_DEVICES_SHIFT))) | \
+	((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3);
+
+#define NFC_SET_ADD_OP_MODE(val) \
+	 raw_write((raw_read(NFC_CONFIG3) & \
+	(NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \
+	((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3);
+
+#define NFC_SET_ADD_CS_MODE(val) \
+{ \
+	NFC_SET_ADD_OP_MODE(val); \
+	NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \
+}
+
+#define NFC_SET_ST_CMD(val) \
+	raw_write((raw_read(NFC_CONFIG2) & \
+	(NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \
+	NFC_ST_CMD_SHITF))) | \
+	((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2);
+
+#define NFMS_NF_DWIDTH 0
+#define NFMS_NF_PG_SZ  1
+#define NFC_CMD_1_SHIFT 8
+
+#define NUM_OF_ADDR_CYCLE (fls(g_page_mask) >> 3)
+#define SET_NFC_DELAY_LINE(val) raw_write((val), NFC_DELAY_LINE)
+
+/*should set the fw,ps,spas,ppb*/
+#define NFC_SET_NFMS(v)	\
+do {	\
+	if (!(v)) \
+		NFC_SET_FW(NFC_FW_8);	\
+	if (((v) & (1 << NFMS_NF_DWIDTH)))	\
+		NFC_SET_FW(NFC_FW_16);	\
+	if (((v) & (1 << NFMS_NF_PG_SZ))) {	\
+		if (IS_2K_PAGE_NAND) {	\
+			NFC_SET_PS(NFC_PS_2K);	\
+			NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
+			NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
+		} else if (IS_4K_PAGE_NAND) {       \
+			NFC_SET_PS(NFC_PS_4K);	\
+			NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
+			NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
+		} else {	\
+			NFC_SET_PS(NFC_PS_512);	\
+			NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \
+			NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \
+		}	\
+		NFC_SET_ADD_CS_MODE(1); \
+		NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1);	\
+		NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
+		NFC_SET_ST_CMD(0x70); \
+		raw_write(raw_read(NFC_CONFIG3) | NFC_NO_SDMA, NFC_CONFIG3); \
+		raw_write(raw_read(NFC_CONFIG3) | NFC_RBB_MODE, NFC_CONFIG3); \
+		if (cpu_is_mx51()) \
+			SET_NFC_DELAY_LINE(0); \
+	} \
+} while (0)
+#endif
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_1
+#define NFC_SET_NFMS(v)
+#endif
+
+#define READ_PAGE()	send_read_page(0)
+#define PROG_PAGE() 	send_prog_page(0)
+
+#elif CONFIG_ARCH_MXC_HAS_NFC_V2
+
+/*
+ * For V1/V2 NFC registers Definition
+ */
+
+/*
+ * Addresses for NFC registers
+ */
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define NFC_REG_BASE			(nfc_axi_base + 0x1000)
+#else
+#define NFC_REG_BASE			nfc_axi_base
+#endif
+#define NFC_BUF_SIZE            	(NFC_REG_BASE + 0xE00)
+#define NFC_BUF_ADDR            	(NFC_REG_BASE + 0xE04)
+#define NFC_FLASH_ADDR          	(NFC_REG_BASE + 0xE06)
+#define NFC_FLASH_CMD           	(NFC_REG_BASE + 0xE08)
+#define NFC_CONFIG              	(NFC_REG_BASE + 0xE0A)
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define NFC_ECC_STATUS_RESULT		(NFC_REG_BASE + 0xE0C)
+#define NFC_ECC_STATUS_RESULT_1		(NFC_REG_BASE + 0xE0C)
+#define NFC_ECC_STATUS_RESULT_2		(NFC_REG_BASE + 0xE0E)
+#define NFC_SPAS			(NFC_REG_BASE + 0xE10)
+#else
+#define NFC_ECC_STATUS_RESULT   	(NFC_REG_BASE + 0xE0C)
+#define NFC_RSLTMAIN_AREA       	(NFC_REG_BASE + 0xE0E)
+#define NFC_RSLTSPARE_AREA      	(NFC_REG_BASE + 0xE10)
+#endif
+#define NFC_WRPROT              	(NFC_REG_BASE + 0xE12)
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define NFC_UNLOCKSTART_BLKADDR  	(NFC_REG_BASE + 0xE20)
+#define NFC_UNLOCKEND_BLKADDR    	(NFC_REG_BASE + 0xE22)
+#define NFC_UNLOCKSTART_BLKADDR1 	(NFC_REG_BASE + 0xE24)
+#define NFC_UNLOCKEND_BLKADDR1   	(NFC_REG_BASE + 0xE26)
+#define NFC_UNLOCKSTART_BLKADDR2 	(NFC_REG_BASE + 0xE28)
+#define NFC_UNLOCKEND_BLKADDR2   	(NFC_REG_BASE + 0xE2A)
+#define NFC_UNLOCKSTART_BLKADDR3 	(NFC_REG_BASE + 0xE2C)
+#define NFC_UNLOCKEND_BLKADDR3   	(NFC_REG_BASE + 0xE2E)
+#else
+#define NFC_UNLOCKSTART_BLKADDR  	(NFC_REG_BASE + 0xE14)
+#define NFC_UNLOCKEND_BLKADDR    	(NFC_REG_BASE + 0xE16)
+#endif
+#define NFC_NF_WRPRST            	(NFC_REG_BASE + 0xE18)
+#define NFC_CONFIG1              	(NFC_REG_BASE + 0xE1A)
+#define NFC_CONFIG2              	(NFC_REG_BASE + 0xE1C)
+
+/*!
+ * Addresses for NFC RAM BUFFER Main area 0
+ */
+#define MAIN_AREA0      		(u16 *)(nfc_axi_base + 0x000)
+#define MAIN_AREA1      		(u16 *)(nfc_axi_base + 0x200)
+
+/*!
+ * Addresses for NFC SPARE BUFFER Spare area 0
+ */
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define SPARE_AREA0     		(u16 *)(nfc_axi_base + 0x1000)
+#define SPARE_LEN			64
+#define SPARE_COUNT			8
+#else
+#define SPARE_AREA0     		(u16 *)(nfc_axi_base + 0x800)
+#define SPARE_LEN       		16
+#define SPARE_COUNT     		4
+#endif
+#define SPARE_SIZE      		(SPARE_LEN * SPARE_COUNT)
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define REG_NFC_ECC_MODE NFC_CONFIG1
+#define SPAS_SHIFT		(0)
+#define REG_NFC_SPAS NFC_SPAS
+#define SPAS_MASK	(0xFF00)
+
+#define NFC_SET_SPAS(v)			\
+	raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | ((v<<SPAS_SHIFT))), \
+								REG_NFC_SPAS)
+
+#define NFC_SET_ECC_MODE(v) 		 \
+do {	\
+	if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112)  {	\
+		raw_write((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_8), \
+							REG_NFC_ECC_MODE); \
+	} else {	\
+		raw_write((raw_read(REG_NFC_ECC_MODE) | NFC_ECC_MODE_4), \
+							REG_NFC_ECC_MODE); \
+	}	\
+} while (0)
+
+#define GET_ECC_STATUS()  __raw_readl(REG_NFC_ECC_STATUS_RESULT);
+#define NFC_SET_NFMS(v) \
+do { \
+	if (((v) & (1 << NFMS_NF_PG_SZ))) { \
+		if (IS_2K_PAGE_NAND) { \
+			(NFMS |= 0x00000100); \
+			(NFMS &= ~0x00000200); \
+			NFC_SET_SPAS(NFC_SPAS_64); \
+		} else if (IS_4K_PAGE_NAND) { \
+			(NFMS &= ~0x00000100); \
+			(NFMS |= 0x00000200); \
+			GET_NAND_OOB_SIZE == 128 ? \
+			NFC_SET_SPAS(NFC_SPAS_128) : \
+			NFC_SET_SPAS(NFC_SPAS_218); \
+		} else { \
+			printk(KERN_ERR "Err for setting page/oob size"); \
+		} \
+		NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
+	} \
+} while (0)
+#else
+#define NFC_SET_SPAS(v)
+#define NFC_SET_ECC_MODE(v)
+#define GET_ECC_STATUS()  raw_read(REG_NFC_ECC_STATUS_RESULT);
+#define NFC_SET_NFMS(v)     (NFMS |= (v))
+#endif
+
+#define WRITE_NFC_IP_REG(val,reg) \
+	raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT),  \
+	REG_NFC_OPS_STAT)
+
+#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT);
+
+/*!
+ * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for
+ * Specific operation
+ */
+#define NFC_CMD            		0x1
+#define NFC_ADDR           		0x2
+#define NFC_INPUT          		0x4
+#define NFC_OUTPUT         		0x8
+#define NFC_ID             		0x10
+#define NFC_STATUS         		0x20
+
+/* Bit Definitions */
+#define NFC_OPS_STAT			(1 << 15)
+#define NFC_SP_EN           		(1 << 2)
+#define NFC_ECC_EN          		(1 << 3)
+#define NFC_INT_MSK         		(1 << 4)
+#define NFC_BIG             		(1 << 5)
+#define NFC_RST             		(1 << 6)
+#define NFC_CE              		(1 << 7)
+#define NFC_ONE_CYCLE       		(1 << 8)
+#define NFC_BLS_LOCKED			0
+#define NFC_BLS_LOCKED_DEFAULT		1
+#define NFC_BLS_UNLCOKED		2
+#define NFC_WPC_LOCK_TIGHT		1
+#define NFC_WPC_LOCK			(1 << 1)
+#define NFC_WPC_UNLOCK			(1 << 2)
+#define NFC_FLASH_ADDR_SHIFT 		0
+#define NFC_UNLOCK_END_ADDR_SHIFT	0
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define NFC_ECC_MODE_4    		 (1<<0)
+#define NFC_ECC_MODE_8			 ~(1<<0)
+#define NFC_SPAS_16			 8
+#define NFC_SPAS_64			 32
+#define NFC_SPAS_112			 56
+#define NFC_SPAS_128			 64
+#define NFC_SPAS_218			 109
+#endif
+/* NFC Register Mapping */
+#define REG_NFC_OPS_STAT		NFC_CONFIG2
+#define REG_NFC_INTRRUPT		NFC_CONFIG1
+#define REG_NFC_FLASH_ADDR		NFC_FLASH_ADDR
+#define REG_NFC_FLASH_CMD		NFC_FLASH_CMD
+#define REG_NFC_OPS			NFC_CONFIG2
+#define REG_NFC_SET_RBA			NFC_BUF_ADDR
+#define REG_NFC_ECC_EN			NFC_CONFIG1
+#define REG_NFC_ECC_STATUS_RESULT  	NFC_ECC_STATUS_RESULT
+#define REG_NFC_CE			NFC_CONFIG1
+#define REG_NFC_SP_EN			NFC_CONFIG1
+#define REG_NFC_BLS			NFC_CONFIG
+#define REG_NFC_WPC			NFC_WRPROT
+#define REG_START_BLKADDR      		NFC_UNLOCKSTART_BLKADDR
+#define REG_END_BLKADDR        		NFC_UNLOCKEND_BLKADDR
+#define REG_NFC_RST			NFC_CONFIG1
+#define REG_NFC_ONE_CYCLE		NFC_CONFIG1
+
+/* NFC V1/V2 Specific MACRO functions definitions */
+
+#define raw_write(v,a)                  __raw_writew(v,a)
+#define raw_read(a)                     __raw_readw(a)
+
+#define NFC_SET_BLS(val)  		val
+
+#define UNLOCK_ADDR(start_addr,end_addr)		\
+{							\
+	raw_write(start_addr,REG_START_BLKADDR);	\
+        raw_write(end_addr,REG_END_BLKADDR);		\
+}
+
+#define NFC_SET_NFC_ACTIVE_CS(val)
+#define NFC_GET_MAXCHIP_SP() 		1
+#define NFC_SET_WPC(val)                val
+
+#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA);
+
+#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1
+#define READ_PAGE()	send_read_page(0)
+#define PROG_PAGE() 	send_prog_page(0)
+#else
+#define READ_PAGE()   \
+do {                     \
+	send_read_page(0);  \
+	send_read_page(1);  \
+	send_read_page(2);  \
+	send_read_page(3);  \
+} while (0)
+
+#define PROG_PAGE()   \
+do {                     \
+	send_prog_page(0);  \
+	send_prog_page(1);  \
+	send_prog_page(2);  \
+	send_prog_page(3);  \
+} while (0)
+#endif
+#define CHECK_NFC_RB            1
+
+#endif
+
+#endif				/* __MXC_ND2_H__ */
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 8c21b89d2d0c..472a08f55790 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1090,7 +1090,7 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  *
  * Internal function. Called with chip held.
  */
-static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
+int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
 	int chipnr, page, realpage, col, bytes, aligned;
@@ -1218,6 +1218,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 
 	return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
 }
+EXPORT_SYMBOL(nand_do_read_ops);
 
 /**
  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
@@ -1800,7 +1801,7 @@ static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
  *
  * NAND write with ECC
  */
-static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
+int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
 	int chipnr, realpage, page, blockmask, column;
@@ -1892,6 +1893,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 		ops->oobretlen = ops->ooblen;
 	return ret;
 }
+EXPORT_SYMBOL(nand_do_write_ops);
 
 /**
  * nand_write - [MTD Interface] NAND write with ECC
@@ -2281,6 +2283,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 	/* Return more or less happy */
 	return ret;
 }
+EXPORT_SYMBOL_GPL(nand_erase_nand);
 
 /**
  * nand_sync - [MTD Interface] sync
@@ -2478,7 +2481,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		mtd->writesize = 1024 << (extid & 0x3);
 		extid >>= 2;
 		/* Calc oobsize */
-		mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
+		mtd->oobsize = (*maf_id == 0x2c && dev_id == 0xd5) ?
+			218 : (8 << (extid & 0x01)) * (mtd->writesize >> 9);
 		extid >>= 2;
 		/* Calc blocksize. Blocksize is multiples of 64KiB */
 		mtd->erasesize = (64 * 1024) << (extid & 0x03);
diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c
new file mode 100644
index 000000000000..1ab1d1d21811
--- /dev/null
+++ b/drivers/mtd/nand/nand_device_info.c
@@ -0,0 +1,2297 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/sizes.h>
+#include <linux/mtd/nand.h>
+
+#include "nand_device_info.h"
+
+/*
+ * Type 2
+ */
+static struct nand_device_info nand_device_info_table_type_2[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 30,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"NAND01GW3",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 30,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 35,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9F1F08",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 30,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG0S3",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 32,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"NAND02GW3",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 30,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UF082G2M, HY27UG082G2M, HY27UG082G1M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F2G08",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9F2G08U0M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG1S3",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 32,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 10,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UH084G2M, HY27UG084G2M, HY27UH084G1M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F4G08",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TH58NVG2S3",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 32,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 30,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UH088G2M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"NAND08GW3BxANx",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F8G08FABWG",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 32,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 32,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{true}
+};
+
+/*
+ * Large MLC
+ */
+static struct nand_device_info nand_device_info_table_large_mlc[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG1D4BFT00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 35,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TH58NVG3D4xFT00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 35,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 35,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TH58NVG4D4xFT00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x45,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 35,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 0,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG2D4BFT00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9G4G08U0M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 45,
+	.data_hold_in_ns          = 25,
+	.address_setup_in_ns      = 50,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UT084G2M, HY27UU088G5M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x20,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 40,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 30,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"NAND04GW3C2AN1E",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9G8G08U0M, K9HAG08U1M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 60,
+	.data_hold_in_ns          = 30,
+	.address_setup_in_ns      = 50,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UV08AG5M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"Intel JS29F08G08AAMiB1 and Micron MT29F8G08MAA; "
+	"Intel JS29F08G08CAMiB1 and Micron MT29F16G08QAA",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9LAG08U0M K9HBG08U1M K9GAG08U0M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"Intel JS29F32G08FAMiB1 and Micron MT29F32G08TAA",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F4G08",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x89,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"JS29F08G08AAMiB2, JS29F08G08CAMiB2",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x89,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"JS29F32G08FAMiB2",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"HY27UW08CGFM",
+	},
+	{true}
+};
+
+/*
+ * Type 7
+ */
+static struct nand_device_info nand_device_info_table_type_7[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F8G08FABWG",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F4G08AAA",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xdc,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 512LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 12,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9F4G08",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 35,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9K8G08UXM, K9NBG08U5A, K9WAG08U1A",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 12,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9WAG08UXM",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xda,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 256LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9F2G08U0A",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xf1,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 128LL*SZ_1M,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 2*SZ_1K + 64,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 12,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9F1F08",
+	},
+	{true}
+};
+
+/*
+ * Type 8
+ */
+static struct nand_device_info nand_device_info_table_type_8[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9GAG08U0M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9LBG08U0M (32Gb), K9HCG08U1M (64Gb), K9MDG08U5M (128Gb)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 0,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"H27UAG, H27UBG",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 23,
+	.data_hold_in_ns          = 20,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 0,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"H27UCG",
+	},
+	{true}
+};
+
+/*
+ * Type 9
+ */
+static struct nand_device_info nand_device_info_table_type_9[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG3D1DTG00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TC58NVG4D1DTG00",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 10,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"TH58NVG6D1DTG20",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x89,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 10,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"JS29F16G08AAMC1, JS29F32G08CAMC1",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F16G08MAA, MT29F32G08QAA",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F64G08TAA (32Gb), MT29F32G08CBAAA (32Gb) MT29F64G08CFAAA (64Gb)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd9,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 8LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 10,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"MT29F128G08CJAAA",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x89,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 10,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"JSF64G08FAMC1",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"K9LBG08U0D",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 8,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9GAG08U0D, K9LBG08U1D, K9HCG08U5D",
+	},
+	{true}
+};
+
+/*
+ * Type 10
+ */
+static struct nand_device_info nand_device_info_table_type_10[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd3,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 1LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd5,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 25,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 30,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	"K9NCG08U5M",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 64,
+	.page_total_size_in_bytes = 4*SZ_1K + 128,
+	.ecc_strength_in_bits     = 4,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 15,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = -1,
+	.tRLOH_in_ns              = -1,
+	.tRHOH_in_ns              = -1,
+	NULL,
+	},
+	{true}
+};
+
+/*
+ * Type 11
+ */
+static struct nand_device_info nand_device_info_table_type_11[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 8*SZ_1K + 376,
+	.ecc_strength_in_bits     = 14,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 8,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 25,
+	"TC58NVG5D2ELAM8 (4GB), TH58NVG6D2ELAM8 (8GB)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x98,
+	.device_code              = 0xde,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 8LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 8*SZ_1K + 376,
+	.ecc_strength_in_bits     = 14,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 8,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 25,
+	"TH58NVG7D2ELAM8",
+	},
+	{true}
+};
+
+/*
+ * Type 15
+ */
+static struct nand_device_info nand_device_info_table_type_15[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xec,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 8*SZ_1K + 436,
+	.ecc_strength_in_bits     = 16,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 20,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 25,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 25,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"K9GBG08U0M (4GB, 1CE); K9LCG08U1M (8GB, 2CE); K9HDG08U5M (16GB, 4CE)",
+	},
+	{true}
+};
+
+/*
+ * BCH ECC12
+ */
+static struct nand_device_info nand_device_info_table_bch_ecc12[] __initdata =
+{
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 224,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"H27UBG8T2M (4GB, 1CE), H27UCG8UDM (8GB, 2CE), H27UDG8VEM (16GB, 4CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0xad,
+	.device_code              = 0xde,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 8LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 224,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"H27UEG8YEM (32GB, 4CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd7,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 10,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 16,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"MT29F32G08CBAAA (4GB, 1CE), MT29F64G08CFAAA (8GB, 2CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0xd9,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 8LL*SZ_1G,
+	.block_size_in_pages      = 128,
+	.page_total_size_in_bytes = 4*SZ_1K + 218,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 10,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 15,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 16,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"MT29F128G08CJAAA (16GB, 2CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0x48,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 2LL*SZ_1G,
+	.block_size_in_pages      = 256,
+	.page_total_size_in_bytes = 4*SZ_1K + 224,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"MT29F16G08CBABA (2GB, 1CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0x68,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 4LL*SZ_1G,
+	.block_size_in_pages      = 256,
+	.page_total_size_in_bytes = 4*SZ_1K + 224,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"MT29F32G08CBABA (4GB, 1CE); "
+	"MT29F64G08CEABA (8GB, 2CE); "
+	"MT29F64G08CFABA (8GB, 2CE)",
+	},
+	{
+	.end_of_table             = false,
+	.manufacturer_code        = 0x2c,
+	.device_code              = 0x88,
+	.cell_technology          = NAND_DEVICE_CELL_TECH_MLC,
+	.chip_size_in_bytes       = 8LL*SZ_1G,
+	.block_size_in_pages      = 256,
+	.page_total_size_in_bytes = 4*SZ_1K + 224,
+	.ecc_strength_in_bits     = 12,
+	.ecc_size_in_bytes        = 512,
+	.data_setup_in_ns         = 15,
+	.data_hold_in_ns          = 10,
+	.address_setup_in_ns      = 20,
+	.gpmi_sample_delay_in_ns  = 6,
+	.tREA_in_ns               = 20,
+	.tRLOH_in_ns              = 5,
+	.tRHOH_in_ns              = 15,
+	"MT29F128G08CJABA (16GB, 2CE); "
+	"MT29F128G08CKABA (16GB, 2CE); "
+	"MT29F256G08CUABA (32GB, 4CE)",
+	},
+	{true}
+};
+
+/*
+ * The following macros make it convenient to extract information from an ID
+ * byte array. All these macros begin with the prefix "ID_".
+ *
+ * Macros of the form:
+ *
+ *         ID_GET_[<manufacturer>_[<modifier>_]]<field>
+ *
+ * extract the given field from an ID byte array. Macros of the form:
+ *
+ *         ID_[<manufacturer>_[<modifier>_]]<field>_<meaning>
+ *
+ * contain the value for the given field that has the given meaning.
+ *
+ * If the <manufacturer> appears, it means this macro represents a view of this
+ * field that is specific to the given manufacturer.
+ *
+ * If the <modifier> appears, it means this macro represents a view of this
+ * field that the given manufacturer applies only under specific conditions.
+ *
+ * Here is a simple example:
+ *
+ *         ID_PAGE_SIZE_CODE_2K
+ *
+ * This macro has the value of the "Page Size" field that indicates the page
+ * size is 2K.
+ *
+ * A more complicated example:
+ *
+ *         ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K  (0x2)
+ *
+ * This macro has the value of the "Page Size" field for Samsung parts that
+ * indicates the page size is 8K. However, this interpretation is only correct
+ * for devices that return 6 ID bytes.
+ */
+
+/* Byte 1 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_1(id)    ((id)[0])
+
+#define ID_GET_MFR_CODE(id)  ID_GET_BYTE_1(id)
+
+/* Byte 2 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_2(id)                           ((id)[1])
+
+#define ID_GET_DEVICE_CODE(id)                      ID_GET_BYTE_2(id)
+    #define ID_SAMSUNG_DEVICE_CODE_1_GBIT           (0xf1)
+    #define ID_SAMSUNG_DEVICE_CODE_2_GBIT           (0xda)
+    #define ID_HYNIX_DEVICE_CODE_ECC12              (0xd7)
+    #define ID_HYNIX_DEVICE_CODE_ECC12_LARGE        (0xde)
+    #define ID_MICRON_DEVICE_CODE_ECC12             (0xd7) /* ECC12        */
+    #define ID_MICRON_DEVICE_CODE_ECC12_LARGE       (0xd9) /* ECC12 8GB/CE */
+    #define ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE  (0x48) /* L63B  2GB/CE */
+    #define ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE  (0x68) /* L63B  4GB/CE */
+    #define ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE  (0x88) /* L63B  8GB/CE */
+
+/* Byte 3 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_3(id)               ((id)[2])
+
+#define ID_GET_DIE_COUNT_CODE(id)       ((ID_GET_BYTE_3(id) >> 0) & 0x3)
+
+#define ID_GET_CELL_TYPE_CODE(id)       ((ID_GET_BYTE_3(id) >> 2) & 0x3)
+    #define ID_CELL_TYPE_CODE_SLC       (0x0) /* All others => MLC. */
+
+#define ID_GET_SAMSUNG_SIMUL_PROG(id)   ((ID_GET_BYTE_3(id) >> 4) & 0x3)
+
+#define ID_GET_MICRON_SIMUL_PROG(id)    ((ID_GET_BYTE_3(id) >> 4) & 0x3)
+
+#define ID_GET_CACHE_PROGRAM(id)        ((ID_GET_BYTE_3(id) >> 7) & 0x1)
+
+/* Byte 4 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_4(id)                       ((id)[3])
+    #define ID_HYNIX_BYTE_4_ECC12_DEVICE        (0x25)
+
+#define ID_GET_PAGE_SIZE_CODE(id)               ((ID_GET_BYTE_4(id) >> 0) & 0x3)
+    #define ID_PAGE_SIZE_CODE_1K                (0x0)
+    #define ID_PAGE_SIZE_CODE_2K                (0x1)
+    #define ID_PAGE_SIZE_CODE_4K                (0x2)
+    #define ID_PAGE_SIZE_CODE_8K                (0x3)
+    #define ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2)
+
+#define ID_GET_OOB_SIZE_CODE(id)                ((ID_GET_BYTE_4(id) >> 2) & 0x1)
+
+#define ID_GET_BLOCK_SIZE_CODE(id)              ((ID_GET_BYTE_4(id) >> 4) & 0x3)
+
+/* Byte 5 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_5(id)                  ((id)[4])
+    #define ID_MICRON_BYTE_5_ECC12         (0x84)
+
+#define ID_GET_SAMSUNG_ECC_LEVEL_CODE(id)  ((ID_GET_BYTE_5(id) >> 4) & 0x7)
+    #define ID_SAMSUNG_ECC_LEVEL_CODE_8    (0x03)
+    #define ID_SAMSUNG_ECC_LEVEL_CODE_24   (0x05)
+
+#define ID_GET_PLANE_COUNT_CODE(id)        ((ID_GET_BYTE_5(id) >> 2) & 0x3)
+
+/* Byte 6 ------------------------------------------------------------------- */
+
+#define ID_GET_BYTE_6(id)                        ((id)[5])
+    #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K  (0x54)
+    #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_4K  (0x13)
+
+#define ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id)   ((ID_GET_BYTE_6(id)>>0) & 0x7)
+    #define ID_SAMSUNG_DEVICE_VERSION_CODE_40NM  (0x01)
+
+/* -------------------------------------------------------------------------- */
+
+void nand_device_print_info(struct nand_device_info *info)
+{
+	unsigned    i;
+	const char  *mfr_name;
+	const char  *cell_technology_name;
+	uint64_t    chip_size;
+	const char  *chip_size_units;
+	unsigned    page_data_size_in_bytes;
+	unsigned    page_oob_size_in_bytes;
+
+	/* Check for nonsense. */
+
+	if (!info)
+		return;
+
+	/* Prepare the manufacturer name. */
+
+	mfr_name = "Unknown";
+
+	for (i = 0; nand_manuf_ids[i].id; i++) {
+		if (nand_manuf_ids[i].id == info->manufacturer_code) {
+			mfr_name = nand_manuf_ids[i].name;
+			break;
+		}
+	}
+
+	/* Prepare the name of the cell technology. */
+
+	switch (info->cell_technology) {
+	case NAND_DEVICE_CELL_TECH_SLC:
+		cell_technology_name = "SLC";
+		break;
+	case NAND_DEVICE_CELL_TECH_MLC:
+		cell_technology_name = "MLC";
+		break;
+	default:
+		cell_technology_name = "Unknown";
+		break;
+	}
+
+	/* Prepare the chip size. */
+
+	if ((info->chip_size_in_bytes >= SZ_1G) &&
+					!(info->chip_size_in_bytes % SZ_1G)) {
+		chip_size       = info->chip_size_in_bytes / ((uint64_t) SZ_1G);
+		chip_size_units = "GiB";
+	} else if ((info->chip_size_in_bytes >= SZ_1M) &&
+					!(info->chip_size_in_bytes % SZ_1M)) {
+		chip_size       = info->chip_size_in_bytes / ((uint64_t) SZ_1M);
+		chip_size_units = "MiB";
+	} else {
+		chip_size       = info->chip_size_in_bytes;
+		chip_size_units = "B";
+	}
+
+	/* Prepare the page geometry. */
+
+	page_data_size_in_bytes = (1<<(fls(info->page_total_size_in_bytes)-1));
+	page_oob_size_in_bytes  = info->page_total_size_in_bytes -
+							page_data_size_in_bytes;
+
+	/* Print the information. */
+
+	printk(KERN_INFO "Manufacturer      : %s (0x%02x)\n",  mfr_name,
+						info->manufacturer_code);
+	printk(KERN_INFO "Device Code       : 0x%02x\n", info->device_code);
+	printk(KERN_INFO "Cell Technology   : %s\n", cell_technology_name);
+	printk(KERN_INFO "Chip Size         : %llu %s\n", chip_size,
+							chip_size_units);
+	printk(KERN_INFO "Pages per Block   : %u\n",
+						info->block_size_in_pages);
+	printk(KERN_INFO "Page Geometry     : %u+%u\n", page_data_size_in_bytes,
+						page_oob_size_in_bytes);
+	printk(KERN_INFO "ECC Strength      : %u bits\n",
+						info->ecc_strength_in_bits);
+	printk(KERN_INFO "ECC Size          : %u B\n", info->ecc_size_in_bytes);
+	printk(KERN_INFO "Data Setup Time   : %u ns\n", info->data_setup_in_ns);
+	printk(KERN_INFO "Data Hold Time    : %u ns\n", info->data_hold_in_ns);
+	printk(KERN_INFO "Address Setup Time: %u ns\n",
+						info->address_setup_in_ns);
+	printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
+						info->gpmi_sample_delay_in_ns);
+	if (info->tREA_in_ns >= 0)
+		printk(KERN_INFO "tREA              : %u ns\n",
+							info->tREA_in_ns);
+	else
+		printk(KERN_INFO "tREA              : Unknown\n");
+	if (info->tREA_in_ns >= 0)
+		printk(KERN_INFO "tRLOH             : %u ns\n",
+							info->tRLOH_in_ns);
+	else
+		printk(KERN_INFO "tRLOH             : Unknown\n");
+	if (info->tREA_in_ns >= 0)
+		printk(KERN_INFO "tRHOH             : %u ns\n",
+							info->tRHOH_in_ns);
+	else
+		printk(KERN_INFO "tRHOH             : Unknown\n");
+	if (info->description)
+		printk(KERN_INFO "Description       : %s\n", info->description);
+	else
+		printk(KERN_INFO "Description       : <None>\n");
+
+}
+
+static struct nand_device_info *nand_device_info_search(
+	struct nand_device_info *table, uint8_t mfr_code, uint8_t device_code)
+{
+
+	for (; !table->end_of_table; table++) {
+		if (table->manufacturer_code != mfr_code)
+			continue;
+		if (table->device_code != device_code)
+			continue;
+		return table;
+	}
+
+	return 0;
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_toshiba(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an SLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
+		/* Type 2 */
+		return nand_device_info_search(nand_device_info_table_type_2,
+				ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
+	}
+
+	/*
+	 * Look for 8K page Toshiba MLC devices.
+	 *
+	 * The page size field in byte 4 can't be used because the field was
+	 * redefined in the 8K parts so the value meaning "8K page" is the same
+	 * as the value meaning "4K page" on the 4K page devices.
+	 *
+	 * The only identifiable difference between the 4K and 8K page Toshiba
+	 * devices with a device code of 0xd7 is the undocumented 6th ID byte.
+	 * The 4K device returns a value of 0x13 and the 8K a value of 0x54.
+	 * Toshiba has verified that this is an acceptable method to distinguish
+	 * the two device families.
+	 */
+
+	if (ID_GET_BYTE_6(id) == ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K) {
+		/* Type 11 */
+		table = nand_device_info_table_type_11;
+	} else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+		/* Type 9 */
+		table = nand_device_info_table_type_9;
+	} else {
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+	}
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_samsung(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an MLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
+
+		/* Is this a Samsung 8K Page MLC device with 16 bit ECC? */
+		if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
+					ID_SAMSUNG_ECC_LEVEL_CODE_24) &&
+		    (ID_GET_PAGE_SIZE_CODE(id) ==
+					ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K)) {
+			/* Type 15 */
+			table = nand_device_info_table_type_15;
+		}
+		/* Is this a Samsung 42nm ECC8 device with a 6 byte ID? */
+		else if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
+					ID_SAMSUNG_ECC_LEVEL_CODE_8) &&
+			(ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ==
+					ID_SAMSUNG_DEVICE_VERSION_CODE_40NM)) {
+			/* Type 9 */
+			table = nand_device_info_table_type_9;
+		} else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+			/* Type 8 */
+			table = nand_device_info_table_type_8;
+		} else {
+			/* Large MLC */
+			table = nand_device_info_table_large_mlc;
+		}
+
+	} else {
+
+		/* Check the page size first. */
+		if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+			/* Type 10 */
+			table = nand_device_info_table_type_10;
+		}
+		/* Check the chip size. */
+		else if (ID_GET_DEVICE_CODE(id) ==
+						ID_SAMSUNG_DEVICE_CODE_1_GBIT) {
+			if (!ID_GET_CACHE_PROGRAM(id)) {
+				/*
+				 * 128 MiB Samsung chips without cache program
+				 * are Type 7.
+				 *
+				 * The K9F1G08U0B does not support multi-plane
+				 * program, so the if statement below cannot be
+				 * used to identify it.
+				 */
+				table = nand_device_info_table_type_7;
+
+			} else {
+				/* Smaller sizes are Type 2 by default. */
+				table = nand_device_info_table_type_2;
+			}
+		} else {
+			/* Check number of simultaneously programmed pages. */
+			if (ID_GET_SAMSUNG_SIMUL_PROG(id) &&
+						ID_GET_PLANE_COUNT_CODE(id)) {
+				/* Type 7 */
+				table = nand_device_info_table_type_7;
+			} else {
+				/* Type 2 */
+				table = nand_device_info_table_type_2;
+			}
+
+		}
+
+	}
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_stmicro(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an SLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC)
+		/* Type 2 */
+		table = nand_device_info_table_type_2;
+	else
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_hynix(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an SLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
+		/* Type 2 */
+		return nand_device_info_search(nand_device_info_table_type_2,
+				ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
+	}
+
+	/*
+	 * Check for ECC12 devices.
+	 *
+	 * We look at the 4th ID byte to distinguish some Hynix ECC12 devices
+	 * from the similar ECC8 part. For example H27UBG8T2M (ECC12) 4th byte
+	 * is 0x25, whereas H27UDG8WFM (ECC8) 4th byte is 0xB6.
+	 */
+
+	if ((ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12 &&
+			ID_GET_BYTE_4(id) == ID_HYNIX_BYTE_4_ECC12_DEVICE) ||
+	    (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_LARGE)) {
+		/* BCH ECC 12 */
+		table = nand_device_info_table_bch_ecc12;
+	} else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+		/*
+		 * So far, all other Samsung and Hynix 4K page devices are
+		 * Type 8.
+		 */
+		table = nand_device_info_table_type_8;
+	} else
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_micron(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an SLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
+
+		/* Check number of simultaneously programmed pages. */
+
+		if (ID_GET_MICRON_SIMUL_PROG(id)) {
+			/* Type 7 */
+			table = nand_device_info_table_type_7;
+		} else {
+			/* Zero simultaneously programmed pages means Type 2. */
+			table = nand_device_info_table_type_2;
+		}
+
+		return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+	}
+
+	/*
+	 * We look at the 5th ID byte to distinguish some Micron ECC12 NANDs
+	 * from the similar ECC8 part.
+	 *
+	 * For example MT29F64G08CFAAA (ECC12) 5th byte is 0x84, whereas
+	 * MT29F64G08TAA (ECC8) 5th byte is 0x78.
+	 *
+	 * We also have a special case for the Micron L63B family
+	 * (256 page/block), which has unique device codes but no ID fields that
+	 * can easily be used to distinguish the family.
+	 */
+
+	if ((ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12 &&
+				ID_GET_BYTE_5(id) == ID_MICRON_BYTE_5_ECC12)  ||
+	   (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_LARGE)      ||
+	   (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE) ||
+	   (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE) ||
+	   (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE)) {
+		/* BCH ECC 12 */
+		table = nand_device_info_table_bch_ecc12;
+	} else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+		/* Toshiba devices with 4K pages are Type 9. */
+		table = nand_device_info_table_type_9;
+	} else {
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+	}
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_sandisk(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+	} else {
+		/* Type 2 */
+		table = nand_device_info_table_type_2;
+	}
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+static struct nand_device_info * __init nand_device_info_fn_intel(const uint8_t id[])
+{
+	struct nand_device_info  *table;
+
+	/* Check for an SLC device. */
+
+	if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
+		/* Type 2 */
+		return nand_device_info_search(nand_device_info_table_type_2,
+				ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
+	}
+
+	if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
+		/* Type 9 */
+		table = nand_device_info_table_type_9;
+	} else {
+		/* Large MLC */
+		table = nand_device_info_table_large_mlc;
+	}
+
+	return nand_device_info_search(table, ID_GET_MFR_CODE(id),
+							ID_GET_DEVICE_CODE(id));
+
+}
+
+/**
+ * struct nand_device_type_info - Information about a NAND Flash type.
+ *
+ * @name:   A human-readable name for this type.
+ * @table:  The device info table for this type.
+ */
+
+struct nand_device_type_info {
+	struct nand_device_info  *table;
+	const char               *name;
+};
+
+/*
+ * A table that maps manufacturer IDs to device information tables.
+ */
+
+static struct nand_device_type_info  nand_device_type_directory[] __initdata =
+{
+	{nand_device_info_table_type_2,    "Type 2"   },
+	{nand_device_info_table_large_mlc, "Large MLC"},
+	{nand_device_info_table_type_7,    "Type 7"   },
+	{nand_device_info_table_type_8,    "Type 8"   },
+	{nand_device_info_table_type_9,    "Type 9"   },
+	{nand_device_info_table_type_10,   "Type 10"  },
+	{nand_device_info_table_type_11,   "Type 11"  },
+	{nand_device_info_table_type_15,   "Type 15"  },
+	{nand_device_info_table_bch_ecc12, "BCH ECC12"},
+	{0, 0},
+};
+
+/**
+ * struct nand_device_mfr_info - Information about a NAND Flash manufacturer.
+ *
+ * @id:     The value of the first NAND Flash ID byte, which identifies the
+ *          manufacturer.
+ * @fn:     A pointer to a function to use for identifying devices from the
+ *          given manufacturer.
+ */
+
+struct nand_device_mfr_info {
+	uint8_t                  id;
+	struct nand_device_info  *(*fn)(const uint8_t id[]);
+};
+
+/*
+ * A table that maps manufacturer IDs to device information tables.
+ */
+
+static struct nand_device_mfr_info  nand_device_mfr_directory[] __initdata =
+{
+	{
+	.id = NAND_MFR_TOSHIBA,
+	.fn = nand_device_info_fn_toshiba,
+	},
+	{
+	.id = NAND_MFR_SAMSUNG,
+	.fn = nand_device_info_fn_samsung,
+	},
+	{
+	.id = NAND_MFR_FUJITSU,
+	.fn = 0,
+	},
+	{
+	.id = NAND_MFR_NATIONAL,
+	.fn = 0,
+	},
+	{
+	.id = NAND_MFR_RENESAS,
+	.fn = 0,
+	},
+	{
+	.id = NAND_MFR_STMICRO,
+	.fn = nand_device_info_fn_stmicro,
+	},
+	{
+	.id = NAND_MFR_HYNIX,
+	.fn = nand_device_info_fn_hynix,
+	},
+	{
+	.id = NAND_MFR_MICRON,
+	.fn = nand_device_info_fn_micron,
+	},
+	{
+	.id = NAND_MFR_AMD,
+	.fn = 0,
+	},
+	{
+	.id = NAND_MFR_SANDISK,
+	.fn = nand_device_info_fn_sandisk,
+	},
+	{
+	.id = NAND_MFR_INTEL,
+	.fn = nand_device_info_fn_intel,
+	},
+	{0, 0}
+};
+
+/**
+ * nand_device_info_test_table - Validate a device info table.
+ *
+ * This function runs tests on the given device info table to check that it
+ * meets the current assumptions.
+ */
+
+static void __init nand_device_info_test_table(
+			struct nand_device_info *table, const char * name)
+{
+	unsigned  i;
+	unsigned  j;
+	uint8_t   mfr_code;
+	uint8_t   device_code;
+
+	/* Loop over entries in this table. */
+
+	for (i = 0; !table[i].end_of_table; i++) {
+
+		/* Get discriminating attributes of the current device. */
+
+		mfr_code    = table[i].manufacturer_code;
+		device_code = table[i].device_code;
+
+		/* Compare with the remaining devices in this table. */
+
+		for (j = i + 1; !table[j].end_of_table; j++) {
+			if ((mfr_code    == table[j].manufacturer_code) &&
+			    (device_code == table[j].device_code))
+				goto error;
+		}
+
+	}
+
+	return;
+
+error:
+
+	printk(KERN_EMERG
+		"\n== NAND Flash device info table failed validity check ==\n");
+
+	printk(KERN_EMERG "\nDevice Info Table: %s\n", name);
+	printk(KERN_EMERG "\nTable Index %u\n", i);
+	nand_device_print_info(table + i);
+	printk(KERN_EMERG "\nTable Index %u\n", j);
+	nand_device_print_info(table + j);
+	printk(KERN_EMERG "\n");
+
+	BUG();
+
+}
+
+/**
+ * nand_device_info_test_data - Test the NAND Flash device data.
+ */
+
+static void __init nand_device_info_test_data(void)
+{
+
+	unsigned  i;
+
+	for (i = 0; nand_device_type_directory[i].name; i++) {
+		nand_device_info_test_table(
+					nand_device_type_directory[i].table,
+					nand_device_type_directory[i].name);
+	}
+
+}
+
+struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
+{
+	unsigned                 i;
+	uint8_t                  mfr_id = ID_GET_MFR_CODE(id);
+	struct nand_device_info  *(*fn)(const uint8_t id[]) = 0;
+
+	/* Test the data. */
+
+	nand_device_info_test_data();
+
+	/* Look for information about this manufacturer. */
+
+	for (i = 0; nand_device_mfr_directory[i].id; i++) {
+		if (nand_device_mfr_directory[i].id == mfr_id) {
+			fn = nand_device_mfr_directory[i].fn;
+			break;
+		}
+	}
+
+	if (!fn)
+		return 0;
+
+	/*
+	 * If control arrives here, we found both a table of device information,
+	 * and a function we can use to identify the current device. Attempt to
+	 * identify the device and return the result.
+	 */
+
+	return fn(id);
+
+}
diff --git a/drivers/mtd/nand/nand_device_info.h b/drivers/mtd/nand/nand_device_info.h
new file mode 100644
index 000000000000..a5f56e913ec6
--- /dev/null
+++ b/drivers/mtd/nand/nand_device_info.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DRIVERS_NAND_DEVICE_INFO_H
+#define __DRIVERS_NAND_DEVICE_INFO_H
+
+ /*
+  * The number of ID bytes to read from the NAND Flash device and hand over to
+  * the identification system.
+  */
+
+#define NAND_DEVICE_ID_BYTE_COUNT  (6)
+
+ /*
+  * The number of ID bytes to read from the NAND Flash device and hand over to
+  * the identification system.
+  */
+
+enum nand_device_cell_technology {
+	NAND_DEVICE_CELL_TECH_SLC = 0,
+	NAND_DEVICE_CELL_TECH_MLC = 1,
+};
+
+/**
+ * struct nand_device_info - Information about a single NAND Flash device.
+ *
+ * This structure contains all the *essential* information about a NAND Flash
+ * device, derived from the device's data sheet. For each manufacturer, we have
+ * an array of these structures.
+ *
+ * @end_of_table:              If true, marks the end of a table of device
+ *                             information.
+ * @manufacturer_code:         The manufacturer code (1st ID byte) reported by
+ *                             the device.
+ * @device_code:               The device code (2nd ID byte) reported by the
+ *                             device.
+ * @cell_technology:           The storage cell technology.
+ * @chip_size_in_bytes:        The total size of the storage behind a single
+ *                             chip select, in bytes. Notice that this is *not*
+ *                             necessarily the total size of the storage in a
+ *                             *package*, which may contain several chips.
+ * @block_size_in_pages:       The number of pages in a block.
+ * @page_total_size_in_bytes:  The total size of a page, in bytes, including
+ *                             both the data and the OOB.
+ * @ecc_strength_in_bits:      The strength of the ECC called for by the
+ *                             manufacturer, in number of correctable bits.
+ * @ecc_size_in_bytes:         The size of the data block over which the
+ *                             manufacturer calls for the given ECC algorithm
+ *                             and strength.
+ * @data_setup_in_ns:          The data setup time, in nanoseconds. Usually the
+ *                             maximum of tDS and tWP. A negative value
+ *                             indicates this characteristic isn't known.
+ * @data_hold_in_ns:           The data hold time, in nanoseconds. Usually the
+ *                             maximum of tDH, tWH and tREH. A negative value
+ *                             indicates this characteristic isn't known.
+ * @address_setup_in_ns:       The address setup time, in nanoseconds. Usually
+ *                             the maximum of tCLS, tCS and tALS. A negative
+ *                             value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns:   A GPMI-specific timing parameter. A negative
+ *                             value indicates this characteristic isn't known.
+ * @tREA_in_ns:                tREA, in nanoseconds, from the data sheet. A
+ *                             negative value indicates this characteristic
+ *                             isn't known.
+ * @tRLOH_in_ns:               tRLOH, in nanoseconds, from the data sheet. A
+ *                             negative value indicates this characteristic
+ *                             isn't known.
+ * @tRHOH_in_ns:               tRHOH, in nanoseconds, from the data sheet. A
+ *                             negative value indicates this characteristic
+ *                             isn't known.
+ */
+
+struct nand_device_info {
+
+	/* End of table marker */
+
+	bool      end_of_table;
+
+	/* Manufacturer and Device codes */
+
+	uint8_t   manufacturer_code;
+	uint8_t   device_code;
+
+	/* Technology */
+
+	enum nand_device_cell_technology  cell_technology;
+
+	/* Geometry */
+
+	uint64_t  chip_size_in_bytes;
+	uint32_t  block_size_in_pages;
+	uint16_t  page_total_size_in_bytes;
+
+	/* ECC */
+
+	uint8_t   ecc_strength_in_bits;
+	uint16_t  ecc_size_in_bytes;
+
+	/* Timing */
+
+	int8_t    data_setup_in_ns;
+	int8_t    data_hold_in_ns;
+	int8_t    address_setup_in_ns;
+	int8_t    gpmi_sample_delay_in_ns;
+	int8_t    tREA_in_ns;
+	int8_t    tRLOH_in_ns;
+	int8_t    tRHOH_in_ns;
+
+	/* Description */
+
+	const char  *description;
+
+};
+
+/**
+ * nand_device_get_info - Get info about a device based on ID bytes.
+ *
+ * @id_bytes:  An array of NAND_DEVICE_ID_BYTE_COUNT ID bytes retrieved from the
+ *             NAND Flash device.
+ */
+
+struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
+
+/**
+ * nand_device_print_info - Prints information about a NAND Flash device.
+ *
+ * @info  A pointer to a NAND Flash device information structure.
+ */
+
+void nand_device_print_info(struct nand_device_info *info);
+
+#endif
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 69ee2c90eb0b..ade32230848f 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -109,6 +109,9 @@ struct nand_flash_dev nand_flash_ids[] = {
 	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
 	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
 
+	/* 32 Gigabit ,only use 2G due to the linux mtd limitation*/
+	{"NAND 4GiB 3,3V 8-bit",	0xD7, 0, 2048, 0, LP_OPTIONS},
+
 	/*
 	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
 	 * have a strange page/block layout !  The chosen minimum erasesize is
@@ -140,6 +143,8 @@ struct nand_manufacturers nand_manuf_ids[] = {
 	{NAND_MFR_HYNIX, "Hynix"},
 	{NAND_MFR_MICRON, "Micron"},
 	{NAND_MFR_AMD, "AMD"},
+	{NAND_MFR_SANDISK, "SanDisk"},
+	{NAND_MFR_INTEL, "Intel"},
 	{0x0, "Unknown"}
 };
 
diff --git a/drivers/mtd/ubiblock.c b/drivers/mtd/ubiblock.c
new file mode 100644
index 000000000000..a2327f5d1014
--- /dev/null
+++ b/drivers/mtd/ubiblock.c
@@ -0,0 +1,589 @@
+/*
+ * Direct UBI block device access
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Based on mtdblock by:
+ * (C) 2000-2003 Nicolas Pitre <nico@cam.org>
+ * (C) 1999-2003 David Woodhouse <dwmw2@infradead.org>
+ */
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+#include <linux/genhd.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/blktrans.h>
+#include <linux/mtd/ubi.h>
+#include <linux/mutex.h>
+#include <linux/workqueue.h>
+
+#include "mtdcore.h"
+
+static LIST_HEAD(ubiblk_devices);
+
+/**
+ * ubiblk_dev - the structure representing translation layer
+ *
+ * @m: interface to mtd_blktrans
+ * @ubi_num: UBI device number
+ * @ubi_vol: UBI volume ID
+ * @usecount: reference count
+ *
+ * @cache_mutex: protects access to cache_data
+ * @cache_data: content of the cached LEB
+ * @cache_offset: offset of cached data on UBI volume, in bytes
+ * @cache_size: cache size in bytes, usually equal to LEB size
+ */
+struct ubiblk_dev {
+	struct mtd_blktrans_dev m;
+
+	int 			ubi_num;
+	int			ubi_vol;
+	int			usecount;
+	struct ubi_volume_desc *ubi;
+
+	struct mutex 		cache_mutex;
+	unsigned char 	       *cache_data;
+	unsigned long 		cache_offset;
+	unsigned int 		cache_size;
+
+	enum {
+		STATE_EMPTY,
+		STATE_CLEAN,
+		STATE_DIRTY
+	} cache_state;
+
+	struct list_head 	list;
+
+	struct work_struct	unbind;
+};
+
+static int ubiblock_open(struct mtd_blktrans_dev *mbd);
+static int ubiblock_release(struct mtd_blktrans_dev *mbd);
+static int ubiblock_flush(struct mtd_blktrans_dev *mbd);
+static int ubiblock_readsect(struct mtd_blktrans_dev *mbd,
+			      unsigned long block, char *buf);
+static int ubiblock_writesect(struct mtd_blktrans_dev *mbd,
+			      unsigned long block, char *buf);
+static int ubiblock_getgeo(struct mtd_blktrans_dev *mbd,
+		struct hd_geometry *geo);
+static void *ubiblk_add(int ubi_num, int ubi_vol_id);
+static void *ubiblk_add_locked(int ubi_num, int ubi_vol_id);
+static int ubiblk_del(struct ubiblk_dev *u);
+static int ubiblk_del_locked(struct ubiblk_dev *u);
+
+/*
+ * These two routines are just to satify mtd_blkdev's requirements
+ */
+static void ubiblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)
+{
+	return;
+}
+
+static void ubiblock_remove_dev(struct mtd_blktrans_dev *mbd)
+{
+	return;
+}
+
+static struct mtd_blktrans_ops ubiblock_tr = {
+
+	.name		= "ubiblk",
+	.major		= 0,			/* assign dynamically  */
+	.part_bits	= 3,			/* allow up to 8 parts */
+	.blksize 	= 512,
+
+	.open		= ubiblock_open,
+	.release	= ubiblock_release,
+	.flush		= ubiblock_flush,
+	.readsect	= ubiblock_readsect,
+	.writesect	= ubiblock_writesect,
+	.getgeo		= ubiblock_getgeo,
+
+	.add_mtd	= ubiblock_add_mtd,
+	.remove_dev	= ubiblock_remove_dev,
+	.owner		= THIS_MODULE,
+};
+
+static int ubiblock_getgeo(struct mtd_blktrans_dev *bdev,
+		struct hd_geometry *geo)
+{
+	return -ENOTTY;
+}
+
+/**
+ * ubiblk_write_cached_data - flush the cache to the UBI volume
+ */
+static int ubiblk_write_cached_data(struct ubiblk_dev *u)
+{
+	int ret;
+
+	if (u->cache_state != STATE_DIRTY)
+		return 0;
+
+	pr_debug("%s: volume %d:%d, writing at %lx of size %x\n",
+		__func__, u->ubi_num, u->ubi_vol,
+		u->cache_offset, u->cache_size);
+
+	ret = ubi_write(u->ubi, u->cache_offset / u->cache_size,
+			u->cache_data, 0, u->cache_size);
+	pr_debug("leb_write status %d\n", ret);
+
+	u->cache_state = STATE_EMPTY;
+	return ret;
+}
+
+/**
+ * ubiblk_do_cached_write - cached write the data to the UBI volume
+ *
+ * @u: ubiblk_dev
+ * @pos: offset on the block device
+ * @len: buffer length
+ * @buf: buffer itself
+ *
+ * if buffer contains one or more whole sectors (=LEBs), write them to the
+ * volume. Otherwise, fill the cache that will be flushed later
+ */
+static int ubiblk_do_cached_write(struct ubiblk_dev *u, unsigned long pos,
+			    int len, const char *buf)
+{
+	unsigned int sect_size = u->cache_size,
+		size, offset;
+	unsigned long sect_start;
+	int ret = 0;
+	int leb;
+
+	pr_debug("%s: volume %d:%d, writing at pos %lx of size %x\n",
+		__func__, u->ubi_num, u->ubi_vol, pos, len);
+
+	while (len > 0) {
+		leb = pos / sect_size;
+		sect_start = leb * sect_size;
+		offset = pos - sect_start;
+		size = sect_size - offset;
+
+		if (size > len)
+			size = len;
+
+		if (size == sect_size) {
+			/*
+			 * We are covering a whole sector.  Thus there is no
+			 * need to bother with the cache while it may still be
+			 * useful for other partial writes.
+			 */
+			ret = ubi_leb_change(u->ubi, leb,
+					buf, size, UBI_UNKNOWN);
+			if (ret)
+				goto out;
+		} else {
+			/* Partial sector: need to use the cache */
+
+			if (u->cache_state == STATE_DIRTY &&
+			    u->cache_offset != sect_start) {
+				ret = ubiblk_write_cached_data(u);
+				if (ret)
+					goto out;
+			}
+
+			if (u->cache_state == STATE_EMPTY ||
+			    u->cache_offset != sect_start) {
+				/* fill the cache with the current sector */
+				u->cache_state = STATE_EMPTY;
+				ret = ubi_leb_read(u->ubi, leb,
+					u->cache_data, 0, u->cache_size, 0);
+				if (ret)
+					return ret;
+				ret = ubi_leb_unmap(u->ubi, leb);
+				if (ret)
+					return ret;
+				ret = ubi_leb_unmap(u->ubi, leb);
+				if (ret)
+					return ret;
+				u->cache_offset = sect_start;
+				u->cache_state = STATE_CLEAN;
+			}
+
+			/* write data to our local cache */
+			memcpy(u->cache_data + offset, buf, size);
+			u->cache_state = STATE_DIRTY;
+		}
+
+		buf += size;
+		pos += size;
+		len -= size;
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * ubiblk_do_cached_read - cached read the data from ubi volume
+ *
+ * @u: ubiblk_dev
+ * @pos: offset on the block device
+ * @len: buffer length
+ * @buf: preallocated buffer
+ *
+ * Cached LEB will be used if possible; otherwise data will be using
+ * ubi_leb_read
+ */
+static int ubiblk_do_cached_read(struct ubiblk_dev *u, unsigned long pos,
+			   int len, char *buf)
+{
+	unsigned int sect_size = u->cache_size;
+	int err = 0;
+	unsigned long sect_start;
+	unsigned offset, size;
+	int leb;
+
+	pr_debug("%s: read at 0x%lx, size 0x%x\n",
+			__func__, pos, len);
+
+	while (len > 0) {
+
+		leb = pos/sect_size;
+		sect_start = leb*sect_size;
+		offset = pos - sect_start;
+		size = sect_size - offset;
+
+		if (size > len)
+			size = len;
+
+		/*
+		 * Check if the requested data is already cached
+		 * Read the requested amount of data from our internal
+		 * cache if it contains what we want, otherwise we read
+		 * the data directly from flash.
+		 */
+		if (u->cache_state != STATE_EMPTY &&
+		    u->cache_offset == sect_start) {
+			pr_debug("%s: cached, returning back from cache\n",
+					__func__);
+			memcpy(buf, u->cache_data + offset, size);
+			err = 0;
+		} else {
+			pr_debug("%s: pos = %ld, reading leb = %d\n",
+					__func__, pos, leb);
+			err = ubi_leb_read(u->ubi, leb, buf, offset, size, 0);
+			if (err)
+				goto out;
+		}
+
+		buf += size;
+		pos += size;
+		len -= size;
+	}
+
+out:
+	return err;
+}
+
+/**
+ * ubiblock_writesect - write the sector
+ *
+ * Allocate the cache, if necessary and perform actual write using
+ * ubiblk_do_cached_write
+ */
+static int ubiblock_writesect(struct mtd_blktrans_dev *mbd,
+			      unsigned long block, char *buf)
+{
+	struct ubiblk_dev *u = container_of(mbd, struct ubiblk_dev, m);
+
+	if (unlikely(!u->cache_data)) {
+		u->cache_data = vmalloc(u->cache_size);
+		if (!u->cache_data)
+			return -EAGAIN;
+	}
+	return ubiblk_do_cached_write(u, block<<9, 512, buf);
+}
+
+/**
+ * ubiblk_readsect - read the sector
+ *
+ * Allocate the cache, if necessary, and perform actual read using
+ * ubiblk_do_cached_read
+ */
+static int ubiblock_readsect(struct mtd_blktrans_dev *mbd,
+			      unsigned long block, char *buf)
+{
+	struct ubiblk_dev *u = container_of(mbd, struct ubiblk_dev, m);
+
+	if (unlikely(!u->cache_data)) {
+		u->cache_data = vmalloc(u->cache_size);
+		if (!u->cache_data)
+			return -EAGAIN;
+	}
+	return ubiblk_do_cached_read(u, block<<9, 512, buf);
+}
+
+static int ubiblk_flush_locked(struct ubiblk_dev *u)
+{
+	ubiblk_write_cached_data(u);
+	ubi_sync(u->ubi_num);
+	return 0;
+}
+
+static int ubiblock_flush(struct mtd_blktrans_dev *mbd)
+{
+	struct ubiblk_dev *u = container_of(mbd, struct ubiblk_dev, m);
+
+	mutex_lock(&u->cache_mutex);
+	ubiblk_flush_locked(u);
+	mutex_unlock(&u->cache_mutex);
+	return 0;
+}
+
+
+static int ubiblock_open(struct mtd_blktrans_dev *mbd)
+{
+	struct ubiblk_dev *u = container_of(mbd, struct ubiblk_dev, m);
+
+	if (u->usecount == 0) {
+		u->ubi = ubi_open_volume(u->ubi_num, u->ubi_vol,
+				UBI_READWRITE);
+		if (IS_ERR(u->ubi))
+			return PTR_ERR(u->ubi);
+	}
+	u->usecount++;
+	return 0;
+}
+
+static int ubiblock_release(struct mtd_blktrans_dev *mbd)
+{
+	struct ubiblk_dev *u = container_of(mbd, struct ubiblk_dev, m);
+
+	if (--u->usecount == 0) {
+		mutex_lock(&u->cache_mutex);
+		ubiblk_flush_locked(u);
+		vfree(u->cache_data);
+		u->cache_data = NULL;
+		mutex_unlock(&u->cache_mutex);
+		ubi_close_volume(u->ubi);
+		u->ubi = NULL;
+	}
+	return 0;
+}
+
+/*
+ * sysfs routines. The ubiblk creates two entries under /sys/block/ubiblkX:
+ *  - volume, R/O, which is read like "ubi0:volume_name"
+ *  - unbind, W/O; when user writes something here, the block device is
+ *  removed
+ *
+ *  unbind schedules a work item to perform real unbind, because sysfs entry
+ *  handler cannot delete itself :)
+ */
+ssize_t volume_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct gendisk *gd = dev_to_disk(dev);
+	struct mtd_blktrans_dev *m = gd->private_data;
+	struct ubiblk_dev *u = container_of(m, struct ubiblk_dev, m);
+
+	return sprintf(buf, "%d:%d\n", u->ubi_num, u->ubi_vol);
+}
+
+static void ubiblk_unbind(struct work_struct *ws)
+{
+	struct ubiblk_dev *u = container_of(ws, struct ubiblk_dev, unbind);
+
+	ubiblk_del(u);
+}
+
+ssize_t unbind_store(struct device *dev, struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+	struct gendisk *gd = dev_to_disk(dev);
+	struct mtd_blktrans_dev *m = gd->private_data;
+	struct ubiblk_dev *u = container_of(m, struct ubiblk_dev, m);
+
+	INIT_WORK(&u->unbind, ubiblk_unbind);
+	schedule_work(&u->unbind);
+	return count;
+}
+
+DEVICE_ATTR(unbind, 0644, NULL, unbind_store);
+DEVICE_ATTR(volume, 0644, volume_show, NULL);
+
+static int ubiblk_sysfs(struct gendisk *hd, int add)
+{
+	int r = 0;
+
+	if (add) {
+		r = device_create_file(disk_to_dev(hd), &dev_attr_unbind);
+		if (r < 0)
+			goto out;
+		r = device_create_file(disk_to_dev(hd), &dev_attr_volume);
+		if (r < 0)
+			goto out1;
+		return 0;
+	}
+
+	device_remove_file(disk_to_dev(hd), &dev_attr_unbind);
+out1:
+	device_remove_file(disk_to_dev(hd), &dev_attr_volume);
+out:
+	return r;
+}
+
+
+/**
+ * add the FTL by registering it with mtd_blkdevs
+ */
+static void *ubiblk_add(int ubi_num, int ubi_vol_id)
+{
+	void *p;
+
+	mutex_lock(&mtd_table_mutex);
+	p = ubiblk_add_locked(ubi_num, ubi_vol_id);
+	mutex_unlock(&mtd_table_mutex);
+	return p;
+}
+
+static void *ubiblk_add_locked(int ubi_num, int ubi_vol_id)
+{
+	struct ubiblk_dev *u = kzalloc(sizeof(*u), GFP_KERNEL);
+	struct ubi_volume_info uvi;
+	struct ubi_volume_desc *ubi;
+
+	if (!u) {
+		u = ERR_PTR(-ENOMEM);
+		goto out;
+	}
+
+	ubi = ubi_open_volume(ubi_num, ubi_vol_id, UBI_READONLY);
+	if (IS_ERR(u->ubi)) {
+		pr_err("cannot open the volume\n");
+		u = (void *)u->ubi;
+		goto out;
+	}
+
+	ubi_get_volume_info(ubi, &uvi);
+	ubi_close_volume(ubi);
+
+	pr_debug("adding volume of size %d (used_size %lld), LEB size %d\n",
+		uvi.size, uvi.used_bytes, uvi.usable_leb_size);
+
+	u->m.mtd = NULL;
+	u->m.devnum = -1;
+	u->m.size = uvi.used_bytes >> 9;
+	u->m.tr = &ubiblock_tr;
+
+	u->ubi_num = ubi_num;
+	u->ubi_vol = ubi_vol_id;
+
+	mutex_init(&u->cache_mutex);
+	u->cache_state = STATE_EMPTY;
+	u->cache_size = uvi.usable_leb_size;
+	u->cache_data = NULL;
+	u->usecount = 0;
+	INIT_LIST_HEAD(&u->list);
+
+	list_add_tail(&u->list, &ubiblk_devices);
+	add_mtd_blktrans_dev(&u->m);
+	ubiblk_sysfs(u->m.blkcore_priv, true);
+out:
+	return u;
+}
+
+static int ubiblk_del(struct ubiblk_dev *u)
+{
+	int r;
+	mutex_lock(&mtd_table_mutex);
+	r = ubiblk_del_locked(u);
+	mutex_unlock(&mtd_table_mutex);
+	return r;
+}
+
+static int ubiblk_del_locked(struct ubiblk_dev *u)
+{
+	if (u->usecount != 0)
+		return -EBUSY;
+	ubiblk_sysfs(u->m.blkcore_priv, false);
+	del_mtd_blktrans_dev(&u->m);
+	list_del(&u->list);
+	BUG_ON(u->cache_data != NULL); /* who did not free the cache ?! */
+	kfree(u);
+	return 0;
+}
+
+static struct ubiblk_dev *ubiblk_find(int num, int vol)
+{
+	struct ubiblk_dev *pos;
+
+	list_for_each_entry(pos, &ubiblk_devices, list)
+		if (pos->ubi_num == num && pos->ubi_vol == vol)
+			return pos;
+	return NULL;
+}
+
+static int ubiblock_notification(struct notifier_block *blk,
+		unsigned long type, void *v)
+{
+	struct ubi_notification *nt = v;
+	struct ubiblk_dev *u;
+
+	switch (type) {
+	case UBI_VOLUME_ADDED:
+		ubiblk_add(nt->vi.ubi_num, nt->vi.vol_id);
+		break;
+	case UBI_VOLUME_REMOVED:
+		u = ubiblk_find(nt->vi.ubi_num, nt->vi.vol_id);
+		if (u)
+			ubiblk_del(u);
+		break;
+	case UBI_VOLUME_RENAMED:
+	case UBI_VOLUME_RESIZED:
+		break;
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block ubiblock_nb = {
+	.notifier_call = ubiblock_notification,
+};
+
+static int __init ubiblock_init(void)
+{
+	int r;
+
+	r = register_mtd_blktrans(&ubiblock_tr);
+	if (r)
+		goto out;
+	r = ubi_register_volume_notifier(&ubiblock_nb, 0);
+	if (r)
+		goto out_unreg;
+	return 0;
+
+out_unreg:
+	deregister_mtd_blktrans(&ubiblock_tr);
+out:
+	return 0;
+}
+
+static void __exit ubiblock_exit(void)
+{
+	ubi_unregister_volume_notifier(&ubiblock_nb);
+	deregister_mtd_blktrans(&ubiblock_tr);
+}
+
+module_init(ubiblock_init);
+module_exit(ubiblock_exit);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Caching block device emulation access to UBI devices");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig
new file mode 100644
index 000000000000..b26c1dc11ad6
--- /dev/null
+++ b/drivers/mxc/Kconfig
@@ -0,0 +1,40 @@
+# drivers/video/mxc/Kconfig
+
+if ARCH_MXC
+
+menu "MXC support drivers"
+
+config MXC_IPU
+	bool "Image Processing Unit Driver"
+	depends on !ARCH_MX21
+	depends on !ARCH_MX27
+	depends on !ARCH_MX25
+	select MXC_IPU_V1 if !ARCH_MX37 && !ARCH_MX5
+	select MXC_IPU_V3 if ARCH_MX37 || ARCH_MX5
+	select MXC_IPU_V3D if ARCH_MX37
+	select MXC_IPU_V3EX if ARCH_MX5
+	help
+	  If you plan to use the Image Processing unit, say
+	  Y here. IPU is needed by Framebuffer and V4L2 drivers.
+
+source "drivers/mxc/ipu/Kconfig"
+source "drivers/mxc/ipu3/Kconfig"
+
+source "drivers/mxc/ssi/Kconfig"
+source "drivers/mxc/dam/Kconfig"
+source "drivers/mxc/pmic/Kconfig"
+source "drivers/mxc/mcu_pmic/Kconfig"
+source "drivers/mxc/security/Kconfig"
+source "drivers/mxc/hmp4e/Kconfig"
+source "drivers/mxc/hw_event/Kconfig"
+source "drivers/mxc/vpu/Kconfig"
+source "drivers/mxc/asrc/Kconfig"
+source "drivers/mxc/bt/Kconfig"
+source "drivers/mxc/gps_ioctrl/Kconfig"
+source "drivers/mxc/mlb/Kconfig"
+source "drivers/mxc/adc/Kconfig"
+source "drivers/mxc/amd-gpu/Kconfig"
+
+endmenu
+
+endif
diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile
new file mode 100644
index 000000000000..5193fa50eb9f
--- /dev/null
+++ b/drivers/mxc/Makefile
@@ -0,0 +1,18 @@
+obj-$(CONFIG_MXC_IPU_V1)			+= ipu/
+obj-$(CONFIG_MXC_IPU_V3)			+= ipu3/
+obj-$(CONFIG_MXC_SSI)               	+= ssi/
+obj-$(CONFIG_MXC_DAM)               	+= dam/
+
+obj-$(CONFIG_MXC_PMIC_MC9SDZ60)		+= mcu_pmic/
+obj-$(CONFIG_MXC_PMIC)			+= pmic/
+
+obj-$(CONFIG_MXC_HMP4E)         	+= hmp4e/
+obj-y                                   += security/
+obj-$(CONFIG_MXC_VPU)                   += vpu/
+obj-$(CONFIG_MXC_HWEVENT)               += hw_event/
+obj-$(CONFIG_MXC_ASRC)                 += asrc/
+obj-$(CONFIG_MXC_BLUETOOTH)		+= bt/
+obj-$(CONFIG_GPS_IOCTRL)		+= gps_ioctrl/
+obj-$(CONFIG_MXC_MLB)                   += mlb/
+obj-$(CONFIG_IMX_ADC)                   += adc/
+obj-$(CONFIG_MXC_AMD_GPU)                   += amd-gpu/
diff --git a/drivers/mxc/adc/Kconfig b/drivers/mxc/adc/Kconfig
new file mode 100644
index 000000000000..91ad23bc7cbe
--- /dev/null
+++ b/drivers/mxc/adc/Kconfig
@@ -0,0 +1,14 @@
+#
+# i.MX ADC devices
+#
+
+menu "i.MX ADC support"
+
+config IMX_ADC
+	tristate "i.MX ADC"
+	depends on ARCH_MXC
+	default n
+	help
+	   This selects the Freescale i.MX on-chip ADC driver.
+
+endmenu
diff --git a/drivers/mxc/adc/Makefile b/drivers/mxc/adc/Makefile
new file mode 100644
index 000000000000..e21e48ee1185
--- /dev/null
+++ b/drivers/mxc/adc/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for i.MX adc devices.
+#
+obj-$(CONFIG_IMX_ADC)		+= imx_adc.o
diff --git a/drivers/mxc/adc/imx_adc.c b/drivers/mxc/adc/imx_adc.c
new file mode 100644
index 000000000000..0c77d6229d31
--- /dev/null
+++ b/drivers/mxc/adc/imx_adc.c
@@ -0,0 +1,1133 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file adc/imx_adc.c
+ * @brief This is the main file of i.MX ADC driver.
+ *
+ * @ingroup IMX_ADC
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/imx_adc.h>
+#include "imx_adc_reg.h"
+
+static int imx_adc_major;
+
+/*!
+ * Number of users waiting in suspendq
+ */
+static int swait;
+
+/*!
+ * To indicate whether any of the adc devices are suspending
+ */
+static int suspend_flag;
+
+/*!
+ * The suspendq is used by blocking application calls
+ */
+static wait_queue_head_t suspendq;
+static wait_queue_head_t tsq;
+
+static bool imx_adc_ready;
+static bool ts_data_ready;
+static int tsi_data = TSI_DATA;
+static unsigned short ts_data_buf[16];
+
+static struct class *imx_adc_class;
+static struct imx_adc_data *adc_data;
+
+static DECLARE_MUTEX(general_convert_mutex);
+static DECLARE_MUTEX(ts_convert_mutex);
+
+unsigned long tsc_base;
+
+int is_imx_adc_ready(void)
+{
+	return imx_adc_ready;
+}
+EXPORT_SYMBOL(is_imx_adc_ready);
+
+void tsc_clk_enable(void)
+{
+	unsigned long reg;
+
+	clk_enable(adc_data->adc_clk);
+
+	reg = __raw_readl(tsc_base + TGCR);
+	reg |= TGCR_IPG_CLK_EN;
+	__raw_writel(reg, tsc_base + TGCR);
+}
+
+void tsc_clk_disable(void)
+{
+	unsigned long reg;
+
+	clk_disable(adc_data->adc_clk);
+
+	reg = __raw_readl(tsc_base + TGCR);
+	reg &= ~TGCR_IPG_CLK_EN;
+	__raw_writel(reg, tsc_base + TGCR);
+}
+
+void tsc_self_reset(void)
+{
+	unsigned long reg;
+
+	reg = __raw_readl(tsc_base + TGCR);
+	reg |= TGCR_TSC_RST;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	while (__raw_readl(tsc_base + TGCR) & TGCR_TSC_RST)
+		continue;
+}
+
+/* Internal reference */
+void tsc_intref_enable(void)
+{
+	unsigned long reg;
+
+	reg = __raw_readl(tsc_base + TGCR);
+	reg |= TGCR_INTREFEN;
+	__raw_writel(reg, tsc_base + TGCR);
+}
+
+/* initialize touchscreen */
+void imx_tsc_init(void)
+{
+	unsigned long reg;
+	int lastitemid;
+
+	/* Level sense */
+	reg = __raw_readl(tsc_base + TCQCR);
+	reg &= ~CQCR_PD_CFG;  /* edge sensitive */
+	reg |= (0xf << CQCR_FIFOWATERMARK_SHIFT);  /* watermark */
+	__raw_writel(reg, tsc_base + TCQCR);
+
+	/* Configure 4-wire */
+	reg = TSC_4WIRE_PRECHARGE;
+	reg |= CC_IGS;
+	__raw_writel(reg, tsc_base + TCC0);
+
+	reg = TSC_4WIRE_TOUCH_DETECT;
+	reg |= 3 << CC_NOS_SHIFT;	/* 4 samples */
+	reg |= 32 << CC_SETTLING_TIME_SHIFT;	/* it's important! */
+	__raw_writel(reg, tsc_base + TCC1);
+
+	reg = TSC_4WIRE_X_MEASUMENT;
+	reg |= 3 << CC_NOS_SHIFT;	/* 4 samples */
+	reg |= 16 << CC_SETTLING_TIME_SHIFT;	/* settling time */
+	__raw_writel(reg, tsc_base + TCC2);
+
+	reg = TSC_4WIRE_Y_MEASUMENT;
+	reg |= 3 << CC_NOS_SHIFT;	/* 4 samples */
+	reg |= 16 << CC_SETTLING_TIME_SHIFT;	/* settling time */
+	__raw_writel(reg, tsc_base + TCC3);
+
+	reg = (TCQ_ITEM_TCC0 << TCQ_ITEM7_SHIFT) |
+	      (TCQ_ITEM_TCC0 << TCQ_ITEM6_SHIFT) |
+	      (TCQ_ITEM_TCC1 << TCQ_ITEM5_SHIFT) |
+	      (TCQ_ITEM_TCC0 << TCQ_ITEM4_SHIFT) |
+	      (TCQ_ITEM_TCC3 << TCQ_ITEM3_SHIFT) |
+	      (TCQ_ITEM_TCC2 << TCQ_ITEM2_SHIFT) |
+	      (TCQ_ITEM_TCC1 << TCQ_ITEM1_SHIFT) |
+	      (TCQ_ITEM_TCC0 << TCQ_ITEM0_SHIFT);
+	__raw_writel(reg, tsc_base + TCQ_ITEM_7_0);
+
+	lastitemid = 5;
+	reg = __raw_readl(tsc_base + TCQCR);
+	reg = (reg & ~CQCR_LAST_ITEM_ID_MASK) |
+	      (lastitemid << CQCR_LAST_ITEM_ID_SHIFT);
+	__raw_writel(reg, tsc_base + TCQCR);
+
+	/* Config idle for 4-wire */
+	reg = TSC_4WIRE_PRECHARGE;
+	__raw_writel(reg, tsc_base + TICR);
+
+	reg = TSC_4WIRE_TOUCH_DETECT;
+	__raw_writel(reg, tsc_base + TICR);
+
+	/* pen down mask */
+	reg = __raw_readl(tsc_base + TCQCR);
+	reg &= ~CQCR_PD_MSK;
+	__raw_writel(reg, tsc_base + TCQCR);
+	reg = __raw_readl(tsc_base + TCQMR);
+	reg &= ~TCQMR_PD_IRQ_MSK;
+	__raw_writel(reg, tsc_base + TCQMR);
+
+	/* Debounce time = dbtime*8 adc clock cycles */
+	reg = __raw_readl(tsc_base + TGCR);
+	reg &= ~TGCR_PDBTIME_MASK;
+	reg |= TGCR_PDBTIME128 | TGCR_HSYNC_EN;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	/* pen down enable */
+	reg = __raw_readl(tsc_base + TGCR);
+	reg |= TGCR_PDB_EN;
+	__raw_writel(reg, tsc_base + TGCR);
+	reg |= TGCR_PD_EN;
+	__raw_writel(reg, tsc_base + TGCR);
+}
+
+static irqreturn_t imx_adc_interrupt(int irq, void *dev_id)
+{
+	unsigned long reg;
+
+	if (__raw_readl(tsc_base + TGSR) & 0x4) {
+		/* deep sleep wakeup interrupt */
+		/* clear tgsr */
+		__raw_writel(0,  tsc_base + TGSR);
+		/* clear deep sleep wakeup irq */
+		reg = __raw_readl(tsc_base + TGCR);
+		reg &= ~TGCR_SLPC;
+		__raw_writel(reg, tsc_base + TGCR);
+		/* un-mask pen down and pen down irq */
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_PD_MSK;
+		__raw_writel(reg, tsc_base + TCQCR);
+		reg = __raw_readl(tsc_base + TCQMR);
+		reg &= ~TCQMR_PD_IRQ_MSK;
+		__raw_writel(reg, tsc_base + TCQMR);
+	} else if ((__raw_readl(tsc_base + TGSR) & 0x1) &&
+		   (__raw_readl(tsc_base + TCQSR) & 0x1)) {
+
+		/* mask pen down detect irq */
+		reg = __raw_readl(tsc_base + TCQMR);
+		reg |= TCQMR_PD_IRQ_MSK;
+		__raw_writel(reg, tsc_base + TCQMR);
+
+		ts_data_ready = 1;
+		wake_up_interruptible(&tsq);
+	}
+	return IRQ_HANDLED;
+}
+
+enum IMX_ADC_STATUS imx_adc_read_general(unsigned short *result)
+{
+	unsigned long reg;
+	unsigned int data_num = 0;
+
+	reg = __raw_readl(tsc_base + GCQCR);
+	reg |= CQCR_FQS;
+	__raw_writel(reg, tsc_base + GCQCR);
+
+	while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EOQ))
+		continue;
+	reg = __raw_readl(tsc_base + GCQCR);
+	reg &= ~CQCR_FQS;
+	__raw_writel(reg, tsc_base + GCQCR);
+	reg = __raw_readl(tsc_base + GCQSR);
+	reg |= CQSR_EOQ;
+	__raw_writel(reg, tsc_base + GCQSR);
+
+	while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EMPT)) {
+		result[data_num] = __raw_readl(tsc_base + GCQFIFO) >>
+				 GCQFIFO_ADCOUT_SHIFT;
+		data_num++;
+	}
+	return IMX_ADC_SUCCESS;
+}
+
+/*!
+ * This function will get raw (X,Y) value by converting the voltage
+ * @param        touch_sample Pointer to touch sample
+ *
+ * return        This funciton returns 0 if successful.
+ *
+ *
+ */
+enum IMX_ADC_STATUS imx_adc_read_ts(struct t_touch_screen *touch_sample,
+				    int wait_tsi)
+{
+	unsigned long reg;
+	int data_num = 0;
+	int detect_sample1, detect_sample2;
+
+	memset(ts_data_buf, 0, sizeof ts_data_buf);
+	touch_sample->valid_flag = 1;
+
+	if (wait_tsi) {
+		/* Config idle for 4-wire */
+		reg = TSC_4WIRE_TOUCH_DETECT;
+		__raw_writel(reg, tsc_base + TICR);
+
+		/* Pen interrupt starts new conversion queue */
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_QSM_MASK;
+		reg |= CQCR_QSM_PEN;
+		__raw_writel(reg, tsc_base + TCQCR);
+
+		/* unmask pen down detect irq */
+		reg = __raw_readl(tsc_base + TCQMR);
+		reg &= ~TCQMR_PD_IRQ_MSK;
+		__raw_writel(reg, tsc_base + TCQMR);
+
+		wait_event_interruptible(tsq, ts_data_ready);
+		while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ))
+			continue;
+
+		/* stop the conversion */
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_QSM_MASK;
+		__raw_writel(reg, tsc_base + TCQCR);
+		reg = CQSR_PD | CQSR_EOQ;
+		__raw_writel(reg, tsc_base + TCQSR);
+
+		/* change configuration for FQS mode */
+		tsi_data = TSI_DATA;
+		reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) |
+		      CC_XPULSW;
+		__raw_writel(reg, tsc_base + TICR);
+	} else {
+		/* FQS semaphore */
+		down(&ts_convert_mutex);
+
+		reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) |
+		      CC_XPULSW;
+		__raw_writel(reg, tsc_base + TICR);
+
+		/* FQS */
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_QSM_MASK;
+		reg |= CQCR_QSM_FQS;
+		__raw_writel(reg, tsc_base + TCQCR);
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg |= CQCR_FQS;
+		__raw_writel(reg, tsc_base + TCQCR);
+		while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ))
+			continue;
+
+		/* stop FQS */
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_QSM_MASK;
+		__raw_writel(reg, tsc_base + TCQCR);
+		reg = __raw_readl(tsc_base + TCQCR);
+		reg &= ~CQCR_FQS;
+		__raw_writel(reg, tsc_base + TCQCR);
+
+		/* clear status bit */
+		reg = __raw_readl(tsc_base + TCQSR);
+		reg |= CQSR_EOQ;
+		__raw_writel(reg, tsc_base + TCQSR);
+		tsi_data = FQS_DATA;
+
+		/* Config idle for 4-wire */
+		reg = TSC_4WIRE_PRECHARGE;
+		__raw_writel(reg, tsc_base + TICR);
+
+		reg = TSC_4WIRE_TOUCH_DETECT;
+		__raw_writel(reg, tsc_base + TICR);
+
+	}
+
+	while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EMPT)) {
+		reg = __raw_readl(tsc_base + TCQFIFO);
+		ts_data_buf[data_num] = reg;
+		data_num++;
+	}
+
+	touch_sample->x_position1 = ts_data_buf[4] >> 4;
+	touch_sample->x_position2 = ts_data_buf[5] >> 4;
+	touch_sample->x_position3 = ts_data_buf[6] >> 4;
+	touch_sample->y_position1 = ts_data_buf[9] >> 4;
+	touch_sample->y_position2 = ts_data_buf[10] >> 4;
+	touch_sample->y_position3 = ts_data_buf[11] >> 4;
+
+	detect_sample1 = ts_data_buf[0];
+	detect_sample2 = ts_data_buf[12];
+
+	if ((detect_sample1 > 0x6000) || (detect_sample2 > 0x6000))
+		touch_sample->valid_flag = 0;
+
+	ts_data_ready = 0;
+
+	if (!(touch_sample->x_position1 ||
+	      touch_sample->x_position2 || touch_sample->x_position3))
+		touch_sample->contact_resistance = 0;
+	else
+		touch_sample->contact_resistance = 1;
+
+	if (tsi_data == FQS_DATA)
+		up(&ts_convert_mutex);
+	return IMX_ADC_SUCCESS;
+}
+
+/*!
+ * This function performs filtering and rejection of excessive noise prone
+ * sampl.
+ *
+ * @param        ts_curr     Touch screen value
+ *
+ * @return       This function returns 0 on success, -1 otherwise.
+ */
+static int imx_adc_filter(struct t_touch_screen *ts_curr)
+{
+
+	unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3;
+	unsigned int sample_sumx, sample_sumy;
+	static unsigned int prev_x[FILTLEN], prev_y[FILTLEN];
+	int index = 0;
+	unsigned int y_curr, x_curr;
+	static int filt_count;
+	/* Added a variable filt_type to decide filtering at run-time */
+	unsigned int filt_type = 0;
+
+	/* ignore the data converted when pen down and up */
+	if ((ts_curr->contact_resistance == 0) || tsi_data == TSI_DATA) {
+		ts_curr->x_position = 0;
+		ts_curr->y_position = 0;
+		filt_count = 0;
+		return 0;
+	}
+	/* ignore the data valid */
+	if (ts_curr->valid_flag == 0)
+		return -1;
+
+	ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2);
+	ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3);
+	ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3);
+	if ((ydiff1 > DELTA_Y_MAX) ||
+	    (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) {
+		pr_debug("imx_adc_filter: Ret pos 1\n");
+		return -1;
+	}
+
+	xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2);
+	xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3);
+	xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3);
+
+	if ((xdiff1 > DELTA_X_MAX) ||
+	    (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) {
+		pr_debug("imx_adc_filter: Ret pos 2\n");
+		return -1;
+	}
+	/* Compute two closer values among the three available Y readouts */
+
+	if (ydiff1 < ydiff2) {
+		if (ydiff1 < ydiff3) {
+			/* Sample 0 & 1 closest together */
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position2;
+		} else {
+			/* Sample 0 & 2 closest together */
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position3;
+		}
+	} else {
+		if (ydiff2 < ydiff3) {
+			/* Sample 1 & 2 closest together */
+			sample_sumy = ts_curr->y_position2 +
+			    ts_curr->y_position3;
+		} else {
+			/* Sample 0 & 2 closest together */
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position3;
+		}
+	}
+
+	/*
+	 * Compute two closer values among the three available X
+	 * readouts
+	 */
+	if (xdiff1 < xdiff2) {
+		if (xdiff1 < xdiff3) {
+			/* Sample 0 & 1 closest together */
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position2;
+		} else {
+			/* Sample 0 & 2 closest together */
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position3;
+		}
+	} else {
+		if (xdiff2 < xdiff3) {
+			/* Sample 1 & 2 closest together */
+			sample_sumx = ts_curr->x_position2 +
+			    ts_curr->x_position3;
+		} else {
+			/* Sample 0 & 2 closest together */
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position3;
+		}
+	}
+
+	/*
+	 * Wait FILTER_MIN_DELAY number of samples to restart
+	 * filtering
+	 */
+	if (filt_count < FILTER_MIN_DELAY) {
+		/*
+		 * Current output is the average of the two closer
+		 * values and no filtering is used
+		 */
+		y_curr = (sample_sumy / 2);
+		x_curr = (sample_sumx / 2);
+		ts_curr->y_position = y_curr;
+		ts_curr->x_position = x_curr;
+		filt_count++;
+
+	} else {
+		if (abs(sample_sumx - (prev_x[0] + prev_x[1])) >
+		    (DELTA_X_MAX * 16)) {
+			pr_debug("imx_adc_filter: : Ret pos 3\n");
+			return -1;
+		}
+		if (abs(sample_sumy - (prev_y[0] + prev_y[1])) >
+		    (DELTA_Y_MAX * 16)) {
+			pr_debug("imx_adc_filter: : Ret pos 4\n");
+			return -1;
+		}
+		sample_sumy /= 2;
+		sample_sumx /= 2;
+		/* Use hard filtering if the sample difference < 10 */
+		if ((abs(sample_sumy - prev_y[0]) > 10) ||
+		    (abs(sample_sumx - prev_x[0]) > 10))
+			filt_type = 1;
+
+		/*
+		 * Current outputs are the average of three previous
+		 * values and the present readout
+		 */
+		y_curr = sample_sumy;
+		for (index = 0; index < FILTLEN; index++) {
+			if (filt_type == 0)
+				y_curr = y_curr + (prev_y[index]);
+			else
+				y_curr = y_curr + (prev_y[index] / 3);
+		}
+		if (filt_type == 0)
+			y_curr = y_curr >> 2;
+		else
+			y_curr = y_curr >> 1;
+		ts_curr->y_position = y_curr;
+
+		x_curr = sample_sumx;
+		for (index = 0; index < FILTLEN; index++) {
+			if (filt_type == 0)
+				x_curr = x_curr + (prev_x[index]);
+			else
+				x_curr = x_curr + (prev_x[index] / 3);
+		}
+		if (filt_type == 0)
+			x_curr = x_curr >> 2;
+		else
+			x_curr = x_curr >> 1;
+		ts_curr->x_position = x_curr;
+
+	}
+
+	/* Update previous X and Y values */
+	for (index = (FILTLEN - 1); index > 0; index--) {
+		prev_x[index] = prev_x[index - 1];
+		prev_y[index] = prev_y[index - 1];
+	}
+
+	/*
+	 * Current output will be the most recent past for the
+	 * next sample
+	 */
+	prev_y[0] = y_curr;
+	prev_x[0] = x_curr;
+
+	return 0;
+
+}
+
+/*!
+ * This function retrieves the current touch screen (X,Y) coordinates.
+ *
+ * @param        touch_sample Pointer to touch sample.
+ *
+ * @return       This function returns IMX_ADC_SUCCESS if successful.
+ */
+enum IMX_ADC_STATUS imx_adc_get_touch_sample(struct t_touch_screen
+					     *touch_sample, int wait_tsi)
+{
+	if (imx_adc_read_ts(touch_sample, wait_tsi))
+		return IMX_ADC_ERROR;
+	if (!imx_adc_filter(touch_sample))
+		return IMX_ADC_SUCCESS;
+	else
+		return IMX_ADC_ERROR;
+}
+EXPORT_SYMBOL(imx_adc_get_touch_sample);
+
+void imx_adc_set_hsync(int on)
+{
+	unsigned long reg;
+	if (imx_adc_ready) {
+		reg = __raw_readl(tsc_base + TGCR);
+		if (on)
+			reg |= TGCR_HSYNC_EN;
+		else
+			reg &= ~TGCR_HSYNC_EN;
+		__raw_writel(reg, tsc_base + TGCR);
+	}
+}
+EXPORT_SYMBOL(imx_adc_set_hsync);
+
+/*!
+ * This is the suspend of power management for the i.MX ADC API.
+ * It supports SAVE and POWER_DOWN state.
+ *
+ * @param        pdev           the device
+ * @param        state          the state
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int imx_adc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	unsigned long reg;
+
+	/* Config idle for 4-wire */
+	reg = TSC_4WIRE_PRECHARGE;
+	__raw_writel(reg, tsc_base + TICR);
+
+	reg = TSC_4WIRE_TOUCH_DETECT;
+	__raw_writel(reg, tsc_base + TICR);
+
+	/* enable deep sleep wake up */
+	reg = __raw_readl(tsc_base + TGCR);
+	reg |= TGCR_SLPC;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	/* mask pen down and pen down irq */
+	reg = __raw_readl(tsc_base + TCQCR);
+	reg |= CQCR_PD_MSK;
+	__raw_writel(reg, tsc_base + TCQCR);
+	reg = __raw_readl(tsc_base + TCQMR);
+	reg |= TCQMR_PD_IRQ_MSK;
+	__raw_writel(reg, tsc_base + TCQMR);
+
+	/* Set power mode to off */
+	reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK;
+	reg |= TGCR_POWER_OFF;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		enable_irq_wake(adc_data->irq);
+	} else {
+		suspend_flag = 1;
+		tsc_clk_disable();
+	}
+	return 0;
+};
+
+/*!
+ * This is the resume of power management for the i.MX adc API.
+ * It supports RESTORE state.
+ *
+ * @param        pdev           the device
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int imx_adc_resume(struct platform_device *pdev)
+{
+	unsigned long reg;
+
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(adc_data->irq);
+	} else {
+		suspend_flag = 0;
+		tsc_clk_enable();
+		while (swait > 0) {
+			swait--;
+			wake_up_interruptible(&suspendq);
+		}
+	}
+
+	/* recover power mode */
+	reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK;
+	reg |= TGCR_POWER_SAVE;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	return 0;
+}
+
+/*!
+ * This function implements the open method on an i.MX ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int imx_adc_open(struct inode *inode, struct file *file)
+{
+	while (suspend_flag) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, !suspend_flag))
+			return -ERESTARTSYS;
+	}
+	pr_debug("imx_adc : imx_adc_open()\n");
+	return 0;
+}
+
+/*!
+ * This function implements the release method on an i.MX ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int imx_adc_free(struct inode *inode, struct file *file)
+{
+	pr_debug("imx_adc : imx_adc_free()\n");
+	return 0;
+}
+
+/*!
+ * This function initializes all ADC registers with default values. This
+ * function also registers the interrupt events.
+ *
+ * @return       This function returns IMX_ADC_SUCCESS if successful.
+ */
+int imx_adc_init(void)
+{
+	unsigned long reg;
+
+	pr_debug("imx_adc_init()\n");
+
+	if (suspend_flag)
+		return -EBUSY;
+
+	tsc_clk_enable();
+
+	/* Reset */
+	tsc_self_reset();
+
+	/* Internal reference */
+	tsc_intref_enable();
+
+	/* Set power mode */
+	reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK;
+	reg |= TGCR_POWER_SAVE;
+	__raw_writel(reg, tsc_base + TGCR);
+
+	imx_tsc_init();
+
+	return IMX_ADC_SUCCESS;
+}
+EXPORT_SYMBOL(imx_adc_init);
+
+/*!
+ * This function disables the ADC, de-registers the interrupt events.
+ *
+ * @return       This function returns IMX_ADC_SUCCESS if successful.
+ */
+enum IMX_ADC_STATUS imx_adc_deinit(void)
+{
+	pr_debug("imx_adc_deinit()\n");
+
+	return IMX_ADC_SUCCESS;
+}
+EXPORT_SYMBOL(imx_adc_deinit);
+
+/*!
+ * This function triggers a conversion and returns one sampling result of one
+ * channel.
+ *
+ * @param        channel   The channel to be sampled
+ * @param        result    The pointer to the conversion result. The memory
+ *                         should be allocated by the caller of this function.
+ *
+ * @return       This function returns IMX_ADC_SUCCESS if successful.
+ */
+enum IMX_ADC_STATUS imx_adc_convert(enum t_channel channel,
+				    unsigned short *result)
+{
+	unsigned long reg;
+	int lastitemid;
+	struct t_touch_screen touch_sample;
+
+	switch (channel) {
+
+	case TS_X_POS:
+		imx_adc_get_touch_sample(&touch_sample, 0);
+		result[0] = touch_sample.x_position;
+
+		/* if no pen down ,recover the register configuration */
+		if (touch_sample.contact_resistance == 0) {
+			reg = __raw_readl(tsc_base + TCQCR);
+			reg &= ~CQCR_QSM_MASK;
+			reg |= CQCR_QSM_PEN;
+			__raw_writel(reg, tsc_base + TCQCR);
+
+			reg = __raw_readl(tsc_base + TCQMR);
+			reg &= ~TCQMR_PD_IRQ_MSK;
+			__raw_writel(reg, tsc_base + TCQMR);
+		}
+		break;
+
+	case TS_Y_POS:
+		imx_adc_get_touch_sample(&touch_sample, 0);
+		result[1] = touch_sample.y_position;
+
+		/* if no pen down ,recover the register configuration */
+		if (touch_sample.contact_resistance == 0) {
+			reg = __raw_readl(tsc_base + TCQCR);
+			reg &= ~CQCR_QSM_MASK;
+			reg |= CQCR_QSM_PEN;
+			__raw_writel(reg, tsc_base + TCQCR);
+
+			reg = __raw_readl(tsc_base + TCQMR);
+			reg &= ~TCQMR_PD_IRQ_MSK;
+			__raw_writel(reg, tsc_base + TCQMR);
+		}
+		break;
+
+	case GER_PURPOSE_ADC0:
+		down(&general_convert_mutex);
+
+		lastitemid = 0;
+		reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) |
+		      (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS;
+		__raw_writel(reg, tsc_base + GCQCR);
+
+		reg = TSC_GENERAL_ADC_GCC0;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC0);
+
+		imx_adc_read_general(result);
+		up(&general_convert_mutex);
+		break;
+
+	case GER_PURPOSE_ADC1:
+		down(&general_convert_mutex);
+
+		lastitemid = 0;
+		reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) |
+		      (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS;
+		__raw_writel(reg, tsc_base + GCQCR);
+
+		reg = TSC_GENERAL_ADC_GCC1;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC0);
+
+		imx_adc_read_general(result);
+		up(&general_convert_mutex);
+		break;
+
+	case GER_PURPOSE_ADC2:
+		down(&general_convert_mutex);
+
+		lastitemid = 0;
+		reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) |
+		      (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS;
+		__raw_writel(reg, tsc_base + GCQCR);
+
+		reg = TSC_GENERAL_ADC_GCC2;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC0);
+
+		imx_adc_read_general(result);
+		up(&general_convert_mutex);
+		break;
+
+	case GER_PURPOSE_MULTICHNNEL:
+		down(&general_convert_mutex);
+
+		reg = TSC_GENERAL_ADC_GCC0;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC0);
+
+		reg = TSC_GENERAL_ADC_GCC1;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC1);
+
+		reg = TSC_GENERAL_ADC_GCC2;
+		reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT);
+		__raw_writel(reg, tsc_base + GCC2);
+
+		reg = (GCQ_ITEM_GCC2 << GCQ_ITEM2_SHIFT) |
+		      (GCQ_ITEM_GCC1 << GCQ_ITEM1_SHIFT) |
+		      (GCQ_ITEM_GCC0 << GCQ_ITEM0_SHIFT);
+		__raw_writel(reg, tsc_base + GCQ_ITEM_7_0);
+
+		lastitemid = 2;
+		reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) |
+		      (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS;
+		__raw_writel(reg, tsc_base + GCQCR);
+
+		imx_adc_read_general(result);
+		up(&general_convert_mutex);
+		break;
+	default:
+		pr_debug("%s: bad channel number\n", __func__);
+		return IMX_ADC_ERROR;
+	}
+
+	return IMX_ADC_SUCCESS;
+}
+EXPORT_SYMBOL(imx_adc_convert);
+
+/*!
+ * This function triggers a conversion and returns sampling results of each
+ * specified channel.
+ *
+ * @param        channels  This input parameter is bitmap to specify channels
+ *                         to be sampled.
+ * @param        result    The pointer to array to store sampling results.
+ *                         The memory should be allocated by the caller of this
+ *                         function.
+ *
+ * @return       This function returns IMX_ADC_SUCCESS if successful.
+ */
+enum IMX_ADC_STATUS imx_adc_convert_multichnnel(enum t_channel channels,
+						unsigned short *result)
+{
+	imx_adc_convert(GER_PURPOSE_MULTICHNNEL, result);
+	return IMX_ADC_SUCCESS;
+}
+EXPORT_SYMBOL(imx_adc_convert_multichnnel);
+
+/*!
+ * This function implements IOCTL controls on an i.MX ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int imx_adc_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	struct t_adc_convert_param *convert_param;
+
+	if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D'))
+		return -ENOTTY;
+
+	while (suspend_flag) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, !suspend_flag))
+			return -ERESTARTSYS;
+	}
+
+	switch (cmd) {
+	case IMX_ADC_INIT:
+		pr_debug("init adc\n");
+		CHECK_ERROR(imx_adc_init());
+		break;
+
+	case IMX_ADC_DEINIT:
+		pr_debug("deinit adc\n");
+		CHECK_ERROR(imx_adc_deinit());
+		break;
+
+	case IMX_ADC_CONVERT:
+		convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL);
+		if (convert_param == NULL)
+			return -ENOMEM;
+		if (copy_from_user(convert_param,
+				   (struct t_adc_convert_param *)arg,
+				   sizeof(*convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(imx_adc_convert(convert_param->channel,
+						  convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((struct t_adc_convert_param *)arg,
+				 convert_param, sizeof(*convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case IMX_ADC_CONVERT_MULTICHANNEL:
+		convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL);
+		if (convert_param == NULL)
+			return -ENOMEM;
+		if (copy_from_user(convert_param,
+				   (struct t_adc_convert_param *)arg,
+				   sizeof(*convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(imx_adc_convert_multichnnel
+				  (convert_param->channel,
+				   convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((struct t_adc_convert_param *)arg,
+				 convert_param, sizeof(*convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	default:
+		pr_debug("imx_adc_ioctl: unsupported ioctl command 0x%x\n",
+			 cmd);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct file_operations imx_adc_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = imx_adc_ioctl,
+	.open = imx_adc_open,
+	.release = imx_adc_free,
+};
+
+static int imx_adc_module_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	int retval;
+	struct device *temp_class;
+	struct resource *res;
+	void __iomem *base;
+
+	/* ioremap the base address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "No TSC base address provided\n");
+		goto err_out0;
+	}
+	base = ioremap(res->start, res->end - res->start);
+	if (base == NULL) {
+		dev_err(&pdev->dev, "failed to rebase TSC base address\n");
+		goto err_out0;
+	}
+	tsc_base = (unsigned long)base;
+
+	/* create the chrdev */
+	imx_adc_major = register_chrdev(0, "imx_adc", &imx_adc_fops);
+
+	if (imx_adc_major < 0) {
+		dev_err(&pdev->dev, "Unable to get a major for imx_adc\n");
+		return imx_adc_major;
+	}
+	init_waitqueue_head(&suspendq);
+	init_waitqueue_head(&tsq);
+
+	imx_adc_class = class_create(THIS_MODULE, "imx_adc");
+	if (IS_ERR(imx_adc_class)) {
+		dev_err(&pdev->dev, "Error creating imx_adc class.\n");
+		ret = PTR_ERR(imx_adc_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(imx_adc_class, NULL,
+				   MKDEV(imx_adc_major, 0), NULL, "imx_adc");
+	if (IS_ERR(temp_class)) {
+		dev_err(&pdev->dev, "Error creating imx_adc class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	adc_data = kmalloc(sizeof(struct imx_adc_data), GFP_KERNEL);
+	if (adc_data == NULL)
+		return -ENOMEM;
+	adc_data->irq = platform_get_irq(pdev, 0);
+	retval = request_irq(adc_data->irq, imx_adc_interrupt,
+			     0, MOD_NAME, MOD_NAME);
+	if (retval) {
+		return retval;
+	}
+	adc_data->adc_clk = clk_get(&pdev->dev, "tchscrn_clk");
+
+	ret = imx_adc_init();
+
+	if (ret != IMX_ADC_SUCCESS) {
+		dev_err(&pdev->dev, "Error in imx_adc_init.\n");
+		goto err_out4;
+	}
+	imx_adc_ready = 1;
+
+	/* By default, devices should wakeup if they can */
+	/* So TouchScreen is set as "should wakeup" as it can */
+	device_init_wakeup(&pdev->dev, 1);
+
+	pr_info("i.MX ADC at 0x%x irq %d\n", (unsigned int)res->start,
+		adc_data->irq);
+	return ret;
+
+err_out4:
+	device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0));
+err_out2:
+	class_destroy(imx_adc_class);
+err_out1:
+	unregister_chrdev(imx_adc_major, "imx_adc");
+err_out0:
+	return ret;
+}
+
+static int imx_adc_module_remove(struct platform_device *pdev)
+{
+	imx_adc_ready = 0;
+	imx_adc_deinit();
+	device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0));
+	class_destroy(imx_adc_class);
+	unregister_chrdev(imx_adc_major, "imx_adc");
+	free_irq(adc_data->irq, MOD_NAME);
+	kfree(adc_data);
+	pr_debug("i.MX ADC successfully removed\n");
+	return 0;
+}
+
+static struct platform_driver imx_adc_driver = {
+	.driver = {
+		   .name = "imx_adc",
+		   },
+	.suspend = imx_adc_suspend,
+	.resume = imx_adc_resume,
+	.probe = imx_adc_module_probe,
+	.remove = imx_adc_module_remove,
+};
+
+/*
+ * Initialization and Exit
+ */
+static int __init imx_adc_module_init(void)
+{
+	pr_debug("i.MX ADC driver loading...\n");
+	return platform_driver_register(&imx_adc_driver);
+}
+
+static void __exit imx_adc_module_exit(void)
+{
+	platform_driver_unregister(&imx_adc_driver);
+	pr_debug("i.MX ADC driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+module_init(imx_adc_module_init);
+module_exit(imx_adc_module_exit);
+
+MODULE_DESCRIPTION("i.MX ADC device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/adc/imx_adc_reg.h b/drivers/mxc/adc/imx_adc_reg.h
new file mode 100644
index 000000000000..8ae776038fbc
--- /dev/null
+++ b/drivers/mxc/adc/imx_adc_reg.h
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#ifndef __IMX_ADC_H__
+#define __IMX_ADC_H__
+
+/* TSC General Config Register */
+#define TGCR                  0x000
+#define TGCR_IPG_CLK_EN       (1 << 0)
+#define TGCR_TSC_RST          (1 << 1)
+#define TGCR_FUNC_RST         (1 << 2)
+#define TGCR_SLPC             (1 << 4)
+#define TGCR_STLC             (1 << 5)
+#define TGCR_HSYNC_EN         (1 << 6)
+#define TGCR_HSYNC_POL        (1 << 7)
+#define TGCR_POWERMODE_SHIFT  8
+#define TGCR_POWER_OFF        (0x0 << TGCR_POWERMODE_SHIFT)
+#define TGCR_POWER_SAVE       (0x1 << TGCR_POWERMODE_SHIFT)
+#define TGCR_POWER_ON         (0x3 << TGCR_POWERMODE_SHIFT)
+#define TGCR_POWER_MASK       (0x3 << TGCR_POWERMODE_SHIFT)
+#define TGCR_INTREFEN         (1 << 10)
+#define TGCR_ADCCLKCFG_SHIFT  16
+#define TGCR_PD_EN            (1 << 23)
+#define TGCR_PDB_EN           (1 << 24)
+#define TGCR_PDBTIME_SHIFT    25
+#define TGCR_PDBTIME128       (0x3f << TGCR_PDBTIME_SHIFT)
+#define TGCR_PDBTIME_MASK     (0x7f << TGCR_PDBTIME_SHIFT)
+
+/* TSC General Status Register */
+#define TGSR                  0x004
+#define TCQ_INT               (1 << 0)
+#define GCQ_INT               (1 << 1)
+#define SLP_INT               (1 << 2)
+#define TCQ_DMA               (1 << 16)
+#define GCQ_DMA               (1 << 17)
+
+/* TSC IDLE Config Register */
+#define TICR                  0x008
+
+/* TouchScreen Convert Queue FIFO Register */
+#define TCQFIFO               0x400
+/* TouchScreen Convert Queue Control Register */
+#define TCQCR                 0x404
+#define CQCR_QSM_SHIFT        0
+#define CQCR_QSM_STOP         (0x0 << CQCR_QSM_SHIFT)
+#define CQCR_QSM_PEN          (0x1 << CQCR_QSM_SHIFT)
+#define CQCR_QSM_FQS          (0x2 << CQCR_QSM_SHIFT)
+#define CQCR_QSM_FQS_PEN      (0x3 << CQCR_QSM_SHIFT)
+#define CQCR_QSM_MASK         (0x3 << CQCR_QSM_SHIFT)
+#define CQCR_FQS              (1 << 2)
+#define CQCR_RPT              (1 << 3)
+#define CQCR_LAST_ITEM_ID_SHIFT   4
+#define CQCR_LAST_ITEM_ID_MASK    (0xf << CQCR_LAST_ITEM_ID_SHIFT)
+#define CQCR_FIFOWATERMARK_SHIFT  8
+#define CQCR_FIFOWATERMARK_MASK   (0xf << CQCR_FIFOWATERMARK_SHIFT)
+#define CQCR_REPEATWAIT_SHIFT     12
+#define CQCR_REPEATWAIT_MASK      (0xf << CQCR_REPEATWAIT_SHIFT)
+#define CQCR_QRST             (1 << 16)
+#define CQCR_FRST             (1 << 17)
+#define CQCR_PD_MSK           (1 << 18)
+#define CQCR_PD_CFG           (1 << 19)
+
+/* TouchScreen Convert Queue Status Register */
+#define TCQSR                 0x408
+#define CQSR_PD               (1 << 0)
+#define CQSR_EOQ              (1 << 1)
+#define CQSR_FOR              (1 << 4)
+#define CQSR_FUR              (1 << 5)
+#define CQSR_FER              (1 << 6)
+#define CQSR_EMPT             (1 << 13)
+#define CQSR_FULL             (1 << 14)
+#define CQSR_FDRY             (1 << 15)
+
+/* TouchScreen Convert Queue Mask Register */
+#define TCQMR                 0x40c
+#define TCQMR_PD_IRQ_MSK      (1 << 0)
+#define TCQMR_EOQ_IRQ_MSK     (1 << 1)
+#define TCQMR_FOR_IRQ_MSK     (1 << 4)
+#define TCQMR_FUR_IRQ_MSK     (1 << 5)
+#define TCQMR_FER_IRQ_MSK     (1 << 6)
+#define TCQMR_PD_DMA_MSK      (1 << 16)
+#define TCQMR_EOQ_DMA_MSK     (1 << 17)
+#define TCQMR_FOR_DMA_MSK     (1 << 20)
+#define TCQMR_FUR_DMA_MSK     (1 << 21)
+#define TCQMR_FER_DMA_MSK     (1 << 22)
+#define TCQMR_FDRY_DMA_MSK    (1 << 31)
+
+/* TouchScreen Convert Queue ITEM 7~0 */
+#define TCQ_ITEM_7_0          0x420
+
+/* TouchScreen Convert Queue ITEM 15~8 */
+#define TCQ_ITEM_15_8         0x424
+
+#define TCQ_ITEM7_SHIFT       28
+#define TCQ_ITEM6_SHIFT       24
+#define TCQ_ITEM5_SHIFT       20
+#define TCQ_ITEM4_SHIFT       16
+#define TCQ_ITEM3_SHIFT       12
+#define TCQ_ITEM2_SHIFT       8
+#define TCQ_ITEM1_SHIFT       4
+#define TCQ_ITEM0_SHIFT       0
+
+#define TCQ_ITEM_TCC0         0x0
+#define TCQ_ITEM_TCC1         0x1
+#define TCQ_ITEM_TCC2         0x2
+#define TCQ_ITEM_TCC3         0x3
+#define TCQ_ITEM_TCC4         0x4
+#define TCQ_ITEM_TCC5         0x5
+#define TCQ_ITEM_TCC6         0x6
+#define TCQ_ITEM_TCC7         0x7
+#define TCQ_ITEM_GCC7         0x8
+#define TCQ_ITEM_GCC6         0x9
+#define TCQ_ITEM_GCC5         0xa
+#define TCQ_ITEM_GCC4         0xb
+#define TCQ_ITEM_GCC3         0xc
+#define TCQ_ITEM_GCC2         0xd
+#define TCQ_ITEM_GCC1         0xe
+#define TCQ_ITEM_GCC0         0xf
+
+/* TouchScreen Convert Config 0-7 */
+#define TCC0                  0x440
+#define TCC1                  0x444
+#define TCC2                  0x448
+#define TCC3                  0x44c
+#define TCC4                  0x450
+#define TCC5                  0x454
+#define TCC6                  0x458
+#define TCC7                  0x45c
+#define CC_PEN_IACK           (1 << 1)
+#define CC_SEL_REFN_SHIFT     2
+#define CC_SEL_REFN_YNLR      (0x1 << CC_SEL_REFN_SHIFT)
+#define CC_SEL_REFN_AGND      (0x2 << CC_SEL_REFN_SHIFT)
+#define CC_SEL_REFN_MASK      (0x3 << CC_SEL_REFN_SHIFT)
+#define CC_SELIN_SHIFT        4
+#define CC_SELIN_XPUL         (0x0 << CC_SELIN_SHIFT)
+#define CC_SELIN_YPLL         (0x1 << CC_SELIN_SHIFT)
+#define CC_SELIN_XNUR         (0x2 << CC_SELIN_SHIFT)
+#define CC_SELIN_YNLR         (0x3 << CC_SELIN_SHIFT)
+#define CC_SELIN_WIPER        (0x4 << CC_SELIN_SHIFT)
+#define CC_SELIN_INAUX0       (0x5 << CC_SELIN_SHIFT)
+#define CC_SELIN_INAUX1       (0x6 << CC_SELIN_SHIFT)
+#define CC_SELIN_INAUX2       (0x7 << CC_SELIN_SHIFT)
+#define CC_SELIN_MASK         (0x7 << CC_SELIN_SHIFT)
+#define CC_SELREFP_SHIFT      7
+#define CC_SELREFP_YPLL       (0x0 << CC_SELREFP_SHIFT)
+#define CC_SELREFP_XPUL       (0x1 << CC_SELREFP_SHIFT)
+#define CC_SELREFP_EXT        (0x2 << CC_SELREFP_SHIFT)
+#define CC_SELREFP_INT        (0x3 << CC_SELREFP_SHIFT)
+#define CC_SELREFP_MASK       (0x3 << CC_SELREFP_SHIFT)
+#define CC_XPULSW             (1 << 9)
+#define CC_XNURSW_SHIFT       10
+#define CC_XNURSW_HIGH        (0x0 << CC_XNURSW_SHIFT)
+#define CC_XNURSW_OFF         (0x1 << CC_XNURSW_SHIFT)
+#define CC_XNURSW_LOW         (0x3 << CC_XNURSW_SHIFT)
+#define CC_XNURSW_MASK        (0x3 << CC_XNURSW_SHIFT)
+#define CC_YPLLSW_SHIFT       12
+#define CC_YPLLSW_MASK        (0x3 << CC_YPLLSW_SHIFT)
+#define CC_YNLRSW             (1 << 14)
+#define CC_WIPERSW            (1 << 15)
+#define CC_NOS_SHIFT          16
+#define CC_YPLLSW_HIGH        (0x0 << CC_NOS_SHIFT)
+#define CC_YPLLSW_OFF         (0x1 << CC_NOS_SHIFT)
+#define CC_YPLLSW_LOW         (0x3 << CC_NOS_SHIFT
+#define CC_NOS_MASK           (0xf << CC_NOS_SHIFT)
+#define CC_IGS                (1 << 20)
+#define CC_SETTLING_TIME_SHIFT 24
+#define CC_SETTLING_TIME_MASK (0xff << CC_SETTLING_TIME_SHIFT)
+
+#define TSC_4WIRE_PRECHARGE    0x158c
+#define TSC_4WIRE_TOUCH_DETECT 0x578e
+
+#define TSC_4WIRE_X_MEASUMENT  0x1c90
+#define TSC_4WIRE_Y_MEASUMENT  0x4604
+
+#define TSC_GENERAL_ADC_GCC0   0x17dc
+#define TSC_GENERAL_ADC_GCC1   0x17ec
+#define TSC_GENERAL_ADC_GCC2   0x17fc
+
+/* GeneralADC Convert Queue FIFO Register */
+#define GCQFIFO                0x800
+#define GCQFIFO_ADCOUT_SHIFT   4
+#define GCQFIFO_ADCOUT_MASK    (0xfff << GCQFIFO_ADCOUT_SHIFT)
+/* GeneralADC Convert Queue Control Register */
+#define GCQCR                  0x804
+/* GeneralADC Convert Queue Status Register */
+#define GCQSR                  0x808
+/* GeneralADC Convert Queue Mask Register */
+#define GCQMR                  0x80c
+
+/* GeneralADC Convert Queue ITEM 7~0 */
+#define GCQ_ITEM_7_0           0x820
+/* GeneralADC Convert Queue ITEM 15~8 */
+#define GCQ_ITEM_15_8          0x824
+
+#define GCQ_ITEM7_SHIFT        28
+#define GCQ_ITEM6_SHIFT        24
+#define GCQ_ITEM5_SHIFT        20
+#define GCQ_ITEM4_SHIFT        16
+#define GCQ_ITEM3_SHIFT        12
+#define GCQ_ITEM2_SHIFT        8
+#define GCQ_ITEM1_SHIFT        4
+#define GCQ_ITEM0_SHIFT        0
+
+#define GCQ_ITEM_GCC0          0x0
+#define GCQ_ITEM_GCC1          0x1
+#define GCQ_ITEM_GCC2          0x2
+#define GCQ_ITEM_GCC3          0x3
+
+/* GeneralADC Convert Config 0-7 */
+#define GCC0                   0x840
+#define GCC1                   0x844
+#define GCC2                   0x848
+#define GCC3                   0x84c
+#define GCC4                   0x850
+#define GCC5                   0x854
+#define GCC6                   0x858
+#define GCC7                   0x85c
+
+/* TSC Test Register R/W */
+#define TTR                    0xc00
+/* TSC Monitor Register 1, 2 */
+#define MNT1                   0xc04
+#define MNT2                   0xc04
+
+#define DETECT_ITEM_ID_1       1
+#define DETECT_ITEM_ID_2       5
+#define TS_X_ITEM_ID           2
+#define TS_Y_ITEM_ID           3
+#define TSI_DATA               1
+#define FQS_DATA               0
+
+#endif				/* __IMX_ADC_H__ */
diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig
new file mode 100644
index 000000000000..629d8cbbc989
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Kconfig
@@ -0,0 +1,13 @@
+#
+# Bluetooth configuration
+#
+
+menu "MXC GPU support"
+
+config MXC_AMD_GPU
+	tristate "MXC GPU support"
+	depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 || ARCH_MX50
+	---help---
+         Say Y to get the GPU driver support.
+
+endmenu
diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile
new file mode 100644
index 000000000000..84cf02e5b3a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Makefile
@@ -0,0 +1,31 @@
+EXTRA_CFLAGS := \
+	-D_LINUX \
+	-I$(obj)/include \
+	-I$(obj)/include/api \
+	-I$(obj)/include/ucode \
+	-I$(obj)/platform/hal/linux \
+	-I$(obj)/os/include \
+	-I$(obj)/os/kernel/include \
+	-I$(obj)/os/user/include
+
+obj-$(CONFIG_MXC_AMD_GPU) += gpu.o
+gpu-objs += 	common/gsl_cmdstream.o \
+		common/gsl_cmdwindow.o \
+		common/gsl_context.o \
+		common/gsl_debug_pm4.o \
+		common/gsl_device.o \
+		common/gsl_drawctxt.o \
+		common/gsl_driver.o \
+		common/gsl_g12.o \
+		common/gsl_intrmgr.o \
+		common/gsl_memmgr.o \
+		common/gsl_mmu.o \
+		common/gsl_ringbuffer.o \
+		common/gsl_sharedmem.o \
+		common/gsl_yamato.o \
+		platform/hal/linux/gsl_linux_map.o \
+		platform/hal/linux/gsl_kmod.o \
+		platform/hal/linux/gsl_hal.o \
+		platform/hal/linux/gsl_kmod_cleanup.o \
+		platform/hal/linux/misc.o \
+		os/kernel/src/linux/kos_lib.o
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdstream.c b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
new file mode 100644
index 000000000000..338192c7ba32
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
@@ -0,0 +1,239 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdstream_init(gsl_device_t *device)
+{
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_close(gsl_device_t *device)
+{
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+    gsl_timestamp_t   timestamp = -1;
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id=%d gsl_timestamp_type_t type=%d)\n", device_id, type );
+#if (defined(GSL_BLD_G12) && defined(IRQTHREAD_POLL))
+    kos_event_signal(device->irqthread_event);
+#endif
+    if (type == GSL_TIMESTAMP_CONSUMED)
+    {
+        // start-of-pipeline timestamp
+        GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    else if (type == GSL_TIMESTAMP_RETIRED)
+    {
+		// end-of-pipeline timestamp
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_readtimestamp. Return value %d\n", timestamp );
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API gsl_timestamp_t
+kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+	gsl_timestamp_t timestamp = -1;
+	GSL_API_MUTEX_LOCK();
+	timestamp = kgsl_cmdstream_readtimestamp0(device_id, type);
+	GSL_API_MUTEX_UNLOCK();
+	return timestamp;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    
+    kgsl_device_active(device);
+     
+    if (device->ftbl.cmdstream_issueibcmds)
+    {
+        status = device->ftbl.cmdstream_issueibcmds(device, drawctxt_index, ibaddr, sizedwords, timestamp, flags);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    if (device->ftbl.device_addtimestamp)
+    {
+        status = device->ftbl.device_addtimestamp(device, timestamp);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API
+int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+	int status = GSL_FAILURE;
+	if (device->ftbl.device_waittimestamp)
+    {
+        status = device->ftbl.device_waittimestamp(device, timestamp, timeout);
+    }
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_cmdstream_memqueue_drain(gsl_device_t *device)
+{
+    gsl_memnode_t     *memnode, *nextnode, *freehead;
+    gsl_timestamp_t   timestamp, ts_processed;
+    gsl_memqueue_t    *memqueue = &device->memqueue;
+    // check head
+    if (memqueue->head == NULL)
+    {
+        return;
+    }
+    // get current EOP timestamp
+    ts_processed = kgsl_cmdstream_readtimestamp0(device->id, GSL_TIMESTAMP_RETIRED);
+    timestamp = memqueue->head->timestamp;
+    // check head timestamp
+    if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000)))
+    {
+        return;
+    }
+    memnode  = memqueue->head;
+    freehead = memqueue->head;
+    // get node list to free
+    for(;;)
+    {
+        nextnode  = memnode->next;
+        if (nextnode == NULL)
+        {
+            // entire queue drained
+            memqueue->head = NULL;
+            memqueue->tail = NULL;
+            break;
+        }
+        timestamp = nextnode->timestamp;
+        if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -20000)))
+        {
+            // drained up to a point
+            memqueue->head = nextnode;
+            memnode->next  = NULL;
+            break;
+        }
+        memnode = nextnode;
+    }
+    // free nodes
+    while (freehead)
+    {
+        memnode  = freehead;
+        freehead = memnode->next;
+        kgsl_sharedmem_free0(&memnode->memdesc, memnode->pid);
+        kos_free(memnode);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type)
+{
+    gsl_memnode_t  *memnode;
+    gsl_device_t   *device = &gsl_driver.device[device_id-1];
+    gsl_memqueue_t *memqueue;
+    (void)type; // unref. For now just use EOP timestamp
+
+	GSL_API_MUTEX_LOCK();
+
+	memqueue = &device->memqueue;
+
+    memnode  = kos_malloc(sizeof(gsl_memnode_t));
+
+    if (!memnode)
+    {
+        // other solution is to idle and free which given that the upper level driver probably wont check, probably a better idea
+		GSL_API_MUTEX_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    memnode->timestamp = timestamp;
+    memnode->pid       = GSL_CALLER_PROCESSID_GET();
+    memnode->next      = NULL;
+    kos_memcpy(&memnode->memdesc, memdesc, sizeof(gsl_memdesc_t));
+
+    // add to end of queue
+    if (memqueue->tail != NULL)
+    {
+        memqueue->tail->next = memnode;
+        memqueue->tail       = memnode;
+    }
+    else
+    {
+        KOS_ASSERT(memqueue->head == NULL);
+        memqueue->head = memnode;
+        memqueue->tail = memnode;
+    }
+
+	GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+static int kgsl_cmdstream_timestamp_cmp(gsl_timestamp_t ts_new, gsl_timestamp_t ts_old)
+{
+	gsl_timestamp_t ts_diff = ts_new - ts_old;
+	return (ts_diff >= 0) || (ts_diff < -20000);
+}
+
+int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp)
+{
+	gsl_timestamp_t ts_processed;
+	ts_processed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED);
+	return kgsl_cmdstream_timestamp_cmp(ts_processed, timestamp);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
new file mode 100644
index 000000000000..4d70da5b25c8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
@@ -0,0 +1,136 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#ifdef GSL_BLD_G12
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CMDWINDOW_TARGET_MASK       0x000000FF
+#define GSL_CMDWINDOW_ADDR_MASK         0x00FFFF00
+#define GSL_CMDWINDOW_TARGET_SHIFT      0
+#define GSL_CMDWINDOW_ADDR_SHIFT        8
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdwindow_init(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_cmdwindow_close(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+#endif // GSL_BLD_G12
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+#ifdef GSL_BLD_G12
+    gsl_device_t  *device;
+    unsigned int  cmdwinaddr;
+    unsigned int  cmdstream;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_cmdwindow_write( gsl_device_id_t device_id=%d, gsl_cmdwindow_t target=%d, unsigned int addr=0x%08x, unsigned int data=0x%08x)\n", device_id, target, addr, data );
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (target < GSL_CMDWINDOW_MIN || target > GSL_CMDWINDOW_MAX)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid target.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if ((!(device->flags & GSL_FLAGS_INITIALIZED) && target == GSL_CMDWINDOW_MMU) ||
+        (!(device->flags & GSL_FLAGS_STARTED)     && target != GSL_CMDWINDOW_MMU))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device state to write to selected targer.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // set command stream
+    if (target == GSL_CMDWINDOW_MMU)
+    {
+#ifdef GSL_NO_MMU
+        return (GSL_SUCCESS);
+#endif
+        cmdstream = ADDR_VGC_MMUCOMMANDSTREAM;
+    }
+    else
+    {
+        cmdstream = ADDR_VGC_COMMANDSTREAM;
+    }
+
+
+    // set command window address
+    cmdwinaddr  = ((target << GSL_CMDWINDOW_TARGET_SHIFT) & GSL_CMDWINDOW_TARGET_MASK);
+    cmdwinaddr |= ((addr   << GSL_CMDWINDOW_ADDR_SHIFT)   & GSL_CMDWINDOW_ADDR_MASK);
+
+#ifndef GSL_NO_MMU
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, GSL_CALLER_PROCESSID_GET());
+#endif
+
+    // write command window address
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, cmdwinaddr);
+
+    // write data
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, data);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameter
+    (void) device_id;
+    (void) target;
+    (void) addr;
+    (void) data;
+
+    return (GSL_FAILURE);
+#endif // GSL_BLD_G12
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_cmdwindow_write0(device_id, target, addr, data);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_context.c b/drivers/mxc/amd-gpu/common/gsl_context.c
new file mode 100644
index 000000000000..c999247b3afd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_context.c
@@ -0,0 +1,74 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_context.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+KGSL_API int
+kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_create)
+    {
+        status = device->ftbl.context_create(device, type, drawctxt_id, flags);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_destroy)
+    {
+        status = device->ftbl.context_destroy(device, drawctxt_id);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
new file mode 100644
index 000000000000..847df8dbe386
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#if defined(_WIN32) && defined (GSL_BLD_YAMATO)
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+
+//#define PM4_DEBUG_USE_MEMBUF
+
+#ifdef PM4_DEBUG_USE_MEMBUF
+
+#define MEMBUF_SIZE 100000
+#define BUFFER_END_MARGIN 1000
+char memBuf[MEMBUF_SIZE];
+static int writePtr = 0;
+static unsigned int lineNumber = 0;
+//#define fprintf(A,...); writePtr += sprintf( memBuf+writePtr, __VA_ARGS__ ); sprintf( memBuf+writePtr, "###" ); if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) { memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); writePtr = 0; }
+#define FILE char
+#define fopen(X,Y) 0
+#define fclose(X)
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    (void)_File;
+
+    va_start(ap, _Format);
+    if( writePtr > 0 && memBuf[writePtr-1] == '\n' )
+    {
+        // Add line number if last written character was newline
+        writePtr += sprintf( memBuf+writePtr, "%d: ", lineNumber++ );
+    }
+    ret = vsprintf(memBuf+writePtr, _Format, ap);
+    writePtr += ret;
+    sprintf( memBuf+writePtr, "###" );
+    if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) 
+    { 
+        memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); 
+        writePtr = 0;
+    }
+
+    va_end(ap);
+
+    return ret;
+}
+
+#else
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    va_start(ap, _Format);
+    ret = vfprintf(_File, _Format, ap);
+    va_end(ap);
+    fflush(_File);
+    return ret;
+}
+
+#endif
+
+#ifndef    _WIN32_WCE
+#define PM4_DUMPFILE    "pm4dump.txt"
+#else
+#define PM4_DUMPFILE    "\\Release\\pm4dump.txt"
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define EXPAND_OPCODE(opcode) ((opcode << 8) | PM4_PKT_MASK)
+
+#define GetString_uint                       GetString_int
+#define GetString_fixed12_4(val, szValue)    GetString_fixed(val, 12, 4, szValue)
+#define GetString_signedint15(val, szValue)  GetString_signedint(val, 15, szValue)
+
+// Need a prototype for this function
+void WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer);
+
+static int indirectionLevel = 0;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void WriteDWORD(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x", dwValue);
+}
+
+void WriteDWORD2(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x\n", dwValue);
+}
+
+//----------------------------------------------------------------------------
+
+// Generate the GetString_## functions for enumerated types
+#define START_ENUMTYPE(__type)                      \
+void GetString_##__type(unsigned int val, char* szValue)   \
+{                                                   \
+    switch(val)                                     \
+    {
+
+#define GENERATE_ENUM(__enumname, __val)            \
+        case __val:                                 \
+            kos_strcpy(szValue, #__enumname);        \
+            break;
+
+#define END_ENUMTYPE(__type)                        \
+        default:                                    \
+            sprintf(szValue, "Unknown: %d", val);   \
+            break;                                  \
+    }                                               \
+}
+
+#include _YAMATO_GENENUM_H
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_hex(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "0x%x", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_float(unsigned int val, char* szValue)
+{
+    float fval = *((float*) &val);
+    sprintf(szValue, "%.4f", fval);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_bool(unsigned int val, char* szValue)
+{
+    if (val)
+    {
+        kos_strcpy(szValue, "TRUE");
+    }
+    else
+    {
+        kos_strcpy(szValue, "FALSE");
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void GetString_int(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_intMinusOne(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d+1", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_signedint(unsigned int val, unsigned int dwNumBits, char* szValue)
+{
+    int nValue = val;
+
+    if (val & (1<<(dwNumBits-1)))
+    {
+        nValue |= 0xffffffff << dwNumBits;
+    }
+
+    sprintf(szValue, "%d", nValue);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_fixed(unsigned int val, unsigned int dwNumInt, unsigned int dwNumFrac, char* szValue)
+{
+
+   (void) dwNumInt;     // unreferenced formal parameter
+
+    if (val>>dwNumFrac == 0)
+    {
+        // Integer part is 0 - just print out the fractional part
+        sprintf(szValue, "%d/%d",
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+    else
+    {
+        // Print out as a mixed fraction
+        sprintf(szValue, "%d %d/%d",
+            val>>dwNumFrac,
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Register(unsigned int dwBaseIndex, unsigned int dwValue, char* pszString)
+{
+    char szValue[64];
+    char szField[128];
+
+    // Empty the string
+    pszString[0] = '\0';
+
+    switch(dwBaseIndex)
+    {
+#define START_REGISTER(__reg)               \
+        case mm##__reg:                     \
+            {                               \
+                reg##__reg reg;             \
+                reg.u32All = dwValue;       \
+                strcat(pszString, #__reg ", (");
+
+#define GENERATE_FIELD(__name, __type)                                \
+                GetString_##__type(reg.bitfields.__name, szValue);    \
+                sprintf(szField, #__name " = %s, ", szValue);         \
+                strcat(pszString, szField);
+
+#define END_REGISTER(__reg)                           \
+                pszString[strlen(pszString)-2]='\0';  \
+                strcat(pszString, ")");               \
+            }                                         \
+            break;
+
+#include _YAMATO_GENREG_H
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Type3Opcode(unsigned int opcode, char* pszValue)
+{
+switch(EXPAND_OPCODE(opcode))
+    {
+#define TYPE3SWITCH(__opcode)                  \
+        case PM4_PACKET3_##__opcode:           \
+            kos_strcpy(pszValue, #__opcode);    \
+            break;
+
+        TYPE3SWITCH(NOP)
+        TYPE3SWITCH(IB_PREFETCH_END)
+        TYPE3SWITCH(SUBBLK_PREFETCH)
+
+        TYPE3SWITCH(INSTR_PREFETCH)
+        TYPE3SWITCH(REG_RMW)
+        TYPE3SWITCH(DRAW_INDX)
+        TYPE3SWITCH(VIZ_QUERY)
+        TYPE3SWITCH(SET_STATE)
+        TYPE3SWITCH(WAIT_FOR_IDLE)
+        TYPE3SWITCH(IM_LOAD)
+        TYPE3SWITCH(IM_LOAD_IMMEDIATE)
+        TYPE3SWITCH(SET_CONSTANT)
+        TYPE3SWITCH(LOAD_CONSTANT_CONTEXT)
+        TYPE3SWITCH(LOAD_ALU_CONSTANT)
+
+        TYPE3SWITCH(DRAW_INDX_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2)
+        TYPE3SWITCH(INDIRECT_BUFFER_PFD)
+        TYPE3SWITCH(INVALIDATE_STATE)
+        TYPE3SWITCH(WAIT_REG_MEM)
+        TYPE3SWITCH(MEM_WRITE)
+        TYPE3SWITCH(REG_TO_MEM)
+        TYPE3SWITCH(INDIRECT_BUFFER)
+
+        TYPE3SWITCH(CP_INTERRUPT)
+        TYPE3SWITCH(COND_EXEC)
+        TYPE3SWITCH(COND_WRITE)
+        TYPE3SWITCH(EVENT_WRITE)
+        TYPE3SWITCH(INSTR_MATCH)
+        TYPE3SWITCH(ME_INIT)
+        TYPE3SWITCH(CONST_PREFETCH)
+        TYPE3SWITCH(MEM_WRITE_CNTR)
+
+        TYPE3SWITCH(SET_BIN_MASK)
+        TYPE3SWITCH(SET_BIN_SELECT)
+        TYPE3SWITCH(WAIT_REG_EQ)
+        TYPE3SWITCH(WAIT_REG_GTE)
+        TYPE3SWITCH(INCR_UPDT_STATE)
+        TYPE3SWITCH(INCR_UPDT_CONST)
+        TYPE3SWITCH(INCR_UPDT_INSTR)
+        TYPE3SWITCH(EVENT_WRITE_SHD)
+        TYPE3SWITCH(EVENT_WRITE_CFL)
+        TYPE3SWITCH(EVENT_WRITE_ZPD)
+        TYPE3SWITCH(WAIT_UNTIL_READ)
+        TYPE3SWITCH(WAIT_IB_PFD_COMPLETE)
+        TYPE3SWITCH(CONTEXT_UPDATE)
+
+        default:
+            sprintf(pszValue, "Unknown: %d", opcode);
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type0(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type0 header = *((pm4_type0*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-0 packet (BASE_INDEX = 0x%x, ONE_REG_WR = %d, COUNT = %d+1)\n",
+        header.base_index, header.one_reg_wr, header.count);   
+
+    // Now go through and write the dwNumDWORDs 
+    for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+    {
+        char szRegister[1024];
+        unsigned int dwRegIndex;
+        unsigned int dwRegValue = *(pBuffer++);
+
+        if (header.one_reg_wr)
+        {
+            dwRegIndex = header.base_index;
+        }
+        else
+        {
+            dwRegIndex = header.base_index + dwIndex;
+        }
+
+        WriteDWORD(pFile, dwRegValue);
+        // Write register string based on fields
+        GetString_Register(dwRegIndex, dwRegValue, szRegister);
+        printString(pFile, "    // %s\n", szRegister);
+
+        // Write actual unsigned int
+        
+    }
+
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type2(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    unsigned int* pBuffer = *ppBuffer;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-2 packet\n");
+    
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+AnalyzePacketType(FILE *pFile, unsigned int dwHeader, unsigned int**ppBuffer)
+{
+    switch(dwHeader & PM4_PKT_MASK)
+    {
+    case PM4_TYPE0_PKT:
+        WritePM4Packet_Type0(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE1_PKT:
+        break;
+
+    case PM4_TYPE2_PKT:
+        WritePM4Packet_Type2(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE3_PKT:
+        WritePM4Packet_Type3(pFile, dwHeader, ppBuffer);
+        break;
+    }
+}
+
+void 
+WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type3 header = *((pm4_type3*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+    char szOpcode[64];
+
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        unsigned int *pIndirectBuffer = (unsigned int *) *(pBuffer++); // ordinal 2 of IB packet is an address
+        unsigned int *pIndirectBufferEnd = pIndirectBuffer + *(pBuffer++); // ordinal 3 of IB packet is size
+        unsigned int gpuaddr = kgsl_sharedmem_convertaddr((unsigned int) pIndirectBuffer, 1);
+
+        indirectionLevel++;
+
+        WriteDWORD2(pFile, dwHeader);
+        WriteDWORD2(pFile, gpuaddr);
+        WriteDWORD2(pFile, (unsigned int) (pIndirectBufferEnd-pIndirectBuffer));
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "Start_IB1, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+        else
+        {
+            printString(pFile, "Start_IB2, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+
+        while(pIndirectBuffer < pIndirectBufferEnd)
+        {
+            unsigned int _dwHeader = *(pIndirectBuffer++);
+
+            AnalyzePacketType(pFile, _dwHeader, &pIndirectBuffer);
+        }
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "End_IB1\n");
+        }
+        else
+        {
+            printString(pFile, "End_IB2\n");
+        }
+
+        indirectionLevel--;
+    }
+    else
+    {
+        unsigned int registerAddr = 0xffffffff;
+        char szRegister[1024];
+
+        GetString_Type3Opcode(header.it_opcode, szOpcode);
+
+        WriteDWORD(pFile, dwHeader);
+        printString(pFile, "    // Type-3 packet (PREDICATE = %d, IT_OPCODE = %s, COUNT = %d+1)\n",
+            header.predicate, szOpcode, header.count);
+        
+        // Go through each command
+        for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+        {
+            // Check for a register write
+            if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_SET_CONSTANT) && (((*pBuffer) >> 16) == 0x4))
+                registerAddr = (*pBuffer) & 0xffff;
+
+            // Write unsigned int
+            WriteDWORD(pFile, *pBuffer);
+
+            // Starting at Ordinal 2 is actual register values
+            if((dwIndex > 0) && (registerAddr != 0xffffffff))
+            {
+                // Write register string based on address
+                GetString_Register(registerAddr + 0x2000, *pBuffer, szRegister);
+                printString(pFile, "    // %s\n", szRegister);
+                registerAddr++;
+            }
+            else
+            {
+                // Write out newline if we aren't augmenting with register fields
+                printString(pFile, "\n");
+            }
+
+            pBuffer++;
+        }
+    }
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpInitParams(unsigned int dwEDRAMBase, unsigned int dwEDRAMSize)
+{
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "InitParams, edrambase=0x%x, edramsize=%d\n",
+        dwEDRAMBase, dwEDRAMSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpSwapBuffers(unsigned int dwAddress, unsigned int dwWidth,
+    unsigned int dwHeight, unsigned int dwPitch, unsigned int dwAlignedHeight, unsigned int dwBitsPerPixel)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "SwapBuffers, address=0x%08x, width=%d, height=%d, pitch=%d, alignedheight=%d, bpp=%d\n",
+        dwAddress, dwWidth, dwHeight, dwPitch, dwAlignedHeight, dwBitsPerPixel);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegSpace(gsl_device_t *device)
+{
+    int           regsPerLine = 0x20;
+    unsigned int  dwOffset;
+    unsigned int  value;
+
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_RegisterSpace\n");
+    
+    for (dwOffset = 0; dwOffset < device->regspace.sizebytes; dwOffset += 4)
+    {
+        if (dwOffset % regsPerLine == 0)
+        {
+           printString(pFile, "    0x%08x   ", dwOffset);
+        }
+
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (dwOffset >> 2), &value);
+
+        printString(pFile, " 0x%08x", value);
+
+        if (((dwOffset + 4) % regsPerLine == 0) && ((dwOffset + 4) < device->regspace.sizebytes))
+        {
+           printString(pFile, "\n");
+        }
+    }
+
+    printString(pFile, "\nEnd_RegisterSpace\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpAllocateMemory(unsigned int dwSize, unsigned int dwFlags, unsigned int dwAddress,
+    unsigned int dwActualSize)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "AllocateMemory, size=%d, flags=0x%x, address=0x%x, actualSize=%d\n",
+        dwSize, dwFlags, dwAddress, dwActualSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFreeMemory(unsigned int dwAddress)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FreeMemory, address=0x%x\n", dwAddress);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+    unsigned int dwNumDWORDs;
+    unsigned int dwIndex;
+    unsigned int *pDataPtr;
+
+    printString(pFile, "StartWriteMemory, address=0x%x, size=%d\n", dwAddress, dwSize);
+
+    // Now write the data, in dwNumDWORDs
+    dwNumDWORDs = dwSize >> 2;
+
+    // If there are spillover bytes into the next dword, increment the amount dumped out here.
+    // The reader needs to take care of not overwriting the nonvalid bytes
+    if((dwSize % 4) != 0)
+        dwNumDWORDs++;
+
+    for (dwIndex = 0, pDataPtr = (unsigned int *)pData; dwIndex < dwNumDWORDs; dwIndex++, pDataPtr++)
+    {
+        WriteDWORD2(pFile, *pDataPtr);
+    }
+
+    printString(pFile, "EndWriteMemory\n");
+
+    fclose(pFile);
+}
+
+void 
+Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+//    unsigned int* pDataPtr;
+
+    printString(pFile, "SetMemory, address=0x%x, size=%d, value=0x%x\n",
+        dwAddress, dwSize, pData);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+void 
+Yamato_ConvertIBAddr(unsigned int dwHeader, unsigned int *pBuffer, int gpuToHost)
+{
+    unsigned int hostaddr;
+    unsigned int *ibend;
+    unsigned int *addr;
+    unsigned int *ib    = pBuffer;
+    pm4_type3    header = *((pm4_type3*) &dwHeader);
+
+    // convert ib1 base address
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        if (gpuToHost)
+        {
+            // from gpu to host
+            *ib = kgsl_sharedmem_convertaddr(*ib, 0);
+
+            hostaddr = *ib;
+        }
+        else
+        {
+            // from host to gpu
+            hostaddr = *ib;
+            *ib = kgsl_sharedmem_convertaddr(*ib, 1);
+        }
+
+        // walk through ib1 and convert any ib2 base address
+
+        ib    = (unsigned int *) hostaddr;
+        ibend = (unsigned int *) (ib + *(++pBuffer));
+
+        while (ib < ibend)
+        {
+            dwHeader = *(ib);
+            header   = *((pm4_type3*) (&dwHeader));
+
+            switch(dwHeader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                ib += header.count + 2;
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                ib++;
+                break;
+
+            case PM4_TYPE3_PKT:
+                if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+                   (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+                {
+                    addr = ib + 1;
+                    if (gpuToHost)
+                    {
+                        // from gpu to host
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 0);
+                    }
+                    else
+                    {
+                        // from host to gpu
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 1);
+                    }
+                }
+                ib += header.count + 2;
+                break;
+            }
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpPM4(unsigned int* pBuffer, unsigned int sizeDWords)
+{
+    unsigned int *pBufferEnd = pBuffer + sizeDWords;
+    unsigned int *tmp;
+
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_PM4Buffer\n");//, count=%d\n", sizeDWords);
+
+    // So look at the first unsigned int - should be a header
+    while(pBuffer < pBufferEnd)
+    {
+        unsigned int dwHeader = *(pBuffer++);
+
+        //printString(pFile, "  Start_Packet\n");
+        switch(dwHeader & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                WritePM4Packet_Type0(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                WritePM4Packet_Type2(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE3_PKT:
+                indirectionLevel = 0;
+                tmp = pBuffer;
+                Yamato_ConvertIBAddr(dwHeader, tmp, 1);
+                WritePM4Packet_Type3(pFile, dwHeader, &pBuffer);
+                Yamato_ConvertIBAddr(dwHeader, tmp, 0);
+                break;
+        }
+        //printString(pFile, "  End_Packet\n");
+    }
+
+    printString(pFile, "End_PM4Buffer\n");
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value)
+{
+    FILE *pFile;
+
+    // Build a Type-0 packet that maps to this register write
+    unsigned int pBuffer[100], *pBuf = &pBuffer[1];
+
+    // Don't dump CP_RB_WPTR (switch statement may be necessary here for future additions)
+    if(dwAddress == mmCP_RB_WPTR)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    pBuffer[0] = dwAddress;
+    pBuffer[1] = value;
+
+    printString(pFile, "StartRegisterWrite\n");
+    WritePM4Packet_Type0(pFile, pBuffer[0], &pBuf);
+    printString(pFile, "EndRegisterWrite\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFbStart(gsl_device_t *device)
+{
+    FILE *pFile;
+
+    static int firstCall = 0;
+
+    // We only want to call this once
+    if(firstCall)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FbStart, value=0x%x\n", device->mmu.mpu_base);
+    printString(pFile, "FbSize, value=0x%x\n", device->mmu.mpu_range);
+
+    fclose(pFile);
+
+    firstCall = 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height)
+{
+    FILE *pFile;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "DumpWindow, addr=0x%x, width=0x%x, height=0x%x\n", addr, width, height);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+#ifdef _DEBUG
+
+#define ADDRESS_STACK_SIZE 256
+#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF)
+#define IF_REGISTER_IN_RANGE(reg, base, count)         \
+    offset = (reg) - (base);                           \
+    if(offset >= 0 && offset <= (count) - 2)
+#define GET_CP_CONSTANT_DATA(x) (*((x) + offset + 2))
+
+static const char format2bpp[] =
+{
+    2,  // COLORX_4_4_4_4 
+    2,  // COLORX_1_5_5_5 
+    2,  // COLORX_5_6_5 
+    1,  // COLORX_8 
+    2,  // COLORX_8_8 
+    4,  // COLORX_8_8_8_8 
+    4,  // COLORX_S8_8_8_8 
+    2,  // COLORX_16_FLOAT 
+    4,  // COLORX_16_16_FLOAT 
+    8,  // COLORX_16_16_16_16_FLOAT 
+    4,  // COLORX_32_FLOAT 
+    8,  // COLORX_32_32_FLOAT 
+    16, // COLORX_32_32_32_32_FLOAT ,
+    1,  // COLORX_2_3_3 
+    3,  // COLORX_8_8_8
+};
+
+static unsigned int kgsl_dumpx_addr_count = 0; //unique command buffer addresses encountered
+static int kgsl_dumpx_handle_type3(unsigned int* hostaddr, int count)
+{
+    // For swap detection we need to find the below declared static values, and detect DI during EDRAM copy
+    static unsigned int width = 0, height = 0, format = 0, baseaddr = 0, iscopy = 0;
+
+    static unsigned int addr_stack[ADDRESS_STACK_SIZE];
+    static unsigned int size_stack[ADDRESS_STACK_SIZE];
+    int swap = 0; // have we encountered a swap during recursion (return value)
+
+    switch(GET_PM4_TYPE3_OPCODE(hostaddr))
+    {
+        case PM4_INDIRECT_BUFFER_PFD:
+        case PM4_INDIRECT_BUFFER:
+        {
+            // traverse indirect buffers
+            unsigned int i;
+            unsigned int ibaddr = *(hostaddr+1);
+            unsigned int ibsize = *(hostaddr+2);
+            
+            // is this address already in encountered?
+            for(i = 0; i < kgsl_dumpx_addr_count && addr_stack[i] != ibaddr; i++);
+            
+            if(kgsl_dumpx_addr_count == i)
+            {
+                // yes it was, store the address so we don't dump this buffer twice
+                addr_stack[kgsl_dumpx_addr_count] = ibaddr;
+                // just for sanity checking
+                size_stack[kgsl_dumpx_addr_count++] = ibsize; 
+                KOS_ASSERT(kgsl_dumpx_addr_count < ADDRESS_STACK_SIZE);
+
+                // recursively follow the indirect link and update swap if indirect buffer had resolve
+                swap |= kgsl_dumpx_parse_ibs(ibaddr, ibsize); 
+            }
+            else
+            {
+                KOS_ASSERT(size_stack[i] == ibsize);
+            }
+        } 
+        break;
+
+        case PM4_SET_CONSTANT:
+        if((*(hostaddr+1) >> 16) == 0x4)
+        {   
+            // parse register writes, and figure out framebuffer configuration
+
+            unsigned int regaddr = (*(hostaddr + 1) & 0xFFFF) + 0x2000; //dword address in register space
+            int offset; // used by the macros
+
+            IF_REGISTER_IN_RANGE(mmPA_SC_WINDOW_SCISSOR_BR, regaddr, count)
+            {
+                // found write to PA_SC_WINDOW_SCISSOR_BR, we use this to detect current
+                // width and height of the framebuffer (TODO: find more reliable way of achieving this)
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                width  = data & 0xFFFF;
+                height = data >> 16;
+            }
+            
+            IF_REGISTER_IN_RANGE(mmRB_MODECONTROL, regaddr, count)
+            {
+                // found write to RB_MODECONTROL, we use this to find out if next DI is resolve
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                iscopy = (data & RB_MODECONTROL__EDRAM_MODE_MASK) == (EDRAM_COPY << RB_MODECONTROL__EDRAM_MODE__SHIFT);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_BASE, regaddr, count)
+            {
+                // found write to RB_COPY_DEST_BASE, we use this to find out the framebuffer base address
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                baseaddr = (data & RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_INFO, regaddr, count)
+            {
+               // found write to RB_COPY_DEST_INFO, we use this to find out the framebuffer format
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                format = (data & RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT;
+            }             
+        }
+        break;
+
+        case PM4_DRAW_INDX:
+        case PM4_DRAW_INDX_2:
+        {
+            // DI found
+            // check if it is resolve
+            if(iscopy && !swap)
+            {
+                // printf("resolve: %ix%i @ 0x%08x, format = 0x%08x\n", width, height, baseaddr, format);
+                KOS_ASSERT(format < 15);
+
+                // yes it was and we need to update color buffer config because this is the first bin
+                // dumpx framebuffer base address, and dimensions
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_AWH, (unsigned int)baseaddr, width, height, " ");
+
+                // find aligned width
+                width = (width + 31) & ~31;
+
+                //dump bytes-per-pixel and aligned width
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_FS, format2bpp[format], width, 0, " ");
+                swap = 1;
+            }
+            
+        }
+        break;
+
+        default:
+        break;
+    }
+    return swap;
+}
+           
+// Traverse IBs and dump them to test vector. Detect swap by inspecting register 
+// writes, keeping note of the current state, and dump framebuffer config to test vector 
+int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords)
+{
+    static unsigned int level = 0; //recursion level
+
+    int swap = 0; // have we encountered a swap during recursion (return value)
+    unsigned int *hostaddr;
+    int dwords_left = sizedwords; //dwords left in the current command buffer
+
+    level++;
+
+    KOS_ASSERT(sizeof(unsigned int *) == sizeof(unsigned int));
+    KOS_ASSERT(level <= 2);
+    hostaddr = (unsigned int *)kgsl_sharedmem_convertaddr(gpuaddr, 0);    
+
+    // dump the IB to test vector
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, gpuaddr, (unsigned int)hostaddr, sizedwords*4, "kgsl_dumpx_write_ibs"));
+
+    while(dwords_left)
+    {
+        int count = 0; //dword count including packet header
+
+        switch(*hostaddr >> 30)
+        {
+        case 0x0: // type-0
+            count = (*hostaddr >> 16)+2;
+            break;
+        case 0x1: // type-1
+            count = 2;
+            break;
+        case 0x3: // type-3
+            count = ((*hostaddr >> 16) & 0x3fff) + 2;
+            swap |= kgsl_dumpx_handle_type3(hostaddr, count);
+            break; // type-3
+        default:
+            KOS_ASSERT(!"unknown packet type");
+        }
+        
+        // jump to next packet
+        dwords_left -= count;
+        hostaddr += count;
+        KOS_ASSERT(dwords_left >= 0 && "PM4 parsing error");
+    }
+
+    level--;
+
+    // if this is the starting level of recursion, we are done. clean-up
+    if(level == 0) kgsl_dumpx_addr_count = 0;
+
+    return swap;
+}
+#endif
+
+#endif // WIN32
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c
new file mode 100644
index 000000000000..0aedf1154beb
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_device.c
@@ -0,0 +1,663 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE void
+kgsl_device_getfunctable(gsl_deviceid_t device_id, gsl_functable_t *ftbl)
+{
+    switch (device_id)
+    {
+#ifdef GSL_BLD_YAMATO
+    case GSL_DEVICE_YAMATO:
+        kgsl_yamato_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_YAMATO
+#ifdef GSL_BLD_G12
+    case GSL_DEVICE_G12:
+        kgsl_g12_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_G12
+    default:
+        break;
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id)
+{
+    int              status = GSL_SUCCESS;
+    gsl_devconfig_t  config;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_init(gsl_device_t *device=0x%08x, gsl_deviceid_t device_id=%D )\n", device, device_id );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    kos_memset(device, 0, sizeof(gsl_device_t));
+
+    // if device configuration is present
+    if (kgsl_hal_getdevconfig(device_id, &config) == GSL_SUCCESS)
+    {
+        kgsl_device_getfunctable(device_id, &device->ftbl);
+
+        kos_memcpy(&device->regspace,  &config.regspace,  sizeof(gsl_memregion_t));
+#ifdef GSL_BLD_YAMATO
+        kos_memcpy(&device->gmemspace, &config.gmemspace, sizeof(gsl_memregion_t));
+#endif // GSL_BLD_YAMATO
+
+        device->refcnt        = 0;
+        device->id            = device_id;
+
+#ifndef GSL_NO_MMU
+        device->mmu.config    = config.mmu_config;
+        device->mmu.mpu_base  = config.mpu_base;
+        device->mmu.mpu_range = config.mpu_range;
+        device->mmu.va_base   = config.va_base;
+        device->mmu.va_range  = config.va_range;
+#endif
+
+        if (device->ftbl.device_init)
+        {
+            status = device->ftbl.device_init(device);
+        }
+        else
+        {
+            status = GSL_FAILURE_NOTINITIALIZED;
+        }
+
+        // allocate memory store
+        status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS, sizeof(gsl_devmemstore_t), &device->memstore);
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // dumpx needs this to be in EMEM0 aperture
+            kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+            status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE, sizeof(gsl_devmemstore_t), &device->memstore);
+        });
+
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+        kgsl_sharedmem_set0(&device->memstore, 0, 0, device->memstore.size);
+
+        // init memqueue
+        device->memqueue.head = NULL;
+        device->memqueue.tail = NULL;
+
+        // init cmdstream
+        status = kgsl_cmdstream_init(device);
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+
+#ifndef _LINUX		
+        // Create timestamp event
+        device->timestamp_event = kos_event_create(0);
+        if( !device->timestamp_event )
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+#else
+		// Create timestamp wait queue
+		init_waitqueue_head(&device->timestamp_waitq);
+#endif	
+
+        //
+        //  Read the chip ID after the device has been initialized.
+        //
+        device->chip_id       = kgsl_hal_getchipid(device->id);
+    }
+
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_close(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device );
+
+    if (!(device->flags & GSL_FLAGS_INITIALIZED)) {
+	return status;
+    }
+
+    /* make sure the device is stopped before close
+       kgsl_device_close is only called for last running caller process
+    */
+    while (device->refcnt > 0) {
+	GSL_API_MUTEX_UNLOCK();
+	kgsl_device_stop(device->id);
+	GSL_API_MUTEX_LOCK();
+    }
+
+    // close cmdstream
+    status = kgsl_cmdstream_close(device);
+    if( status != GSL_SUCCESS ) return status;
+
+    if (device->ftbl.device_close) {
+	status = device->ftbl.device_close(device);
+    }
+
+    // DumpX allocates memstore from MMU aperture
+    if ((device->refcnt == 0) && device->memstore.hostptr
+	&& !(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX))
+    {
+	kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+    }
+
+#ifndef _LINUX	
+    // destroy timestamp event
+    if(device->timestamp_event)
+    {
+        kos_event_signal(device->timestamp_event);  // wake up waiting threads before destroying the structure
+        kos_event_destroy( device->timestamp_event );
+        device->timestamp_event = 0;
+    }
+#else
+    wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif	
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_close. Return value %B\n", status );
+    
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_destroy(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_destroy(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_destroy)
+        {
+            status = device->ftbl.device_destroy(device);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_destroy. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_attachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            device->callerprocess[pindex] = pid;
+
+            status = kgsl_mmu_attachcallback(&device->mmu, pid);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_attachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_detachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            status |= kgsl_mmu_detachcallback(&device->mmu, pid);
+
+            device->callerprocess[pindex] = 0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_detachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status  = GSL_SUCCESS;
+    gsl_device_t  *device = &gsl_driver.device[device_id-1];        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_getproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    switch (type)
+    {
+    case GSL_PROP_SHMEM:
+        {
+        gsl_shmemprop_t  *shem = (gsl_shmemprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shmemprop_t));
+
+        shem->numapertures   = gsl_driver.shmem.numapertures;
+        shem->aperture_mask  = GSL_APERTURE_MASK;
+        shem->aperture_shift = GSL_APERTURE_SHIFT;
+
+        break;
+        }
+
+    case GSL_PROP_SHMEM_APERTURES:
+        {
+        int i;
+        gsl_apertureprop_t  *aperture = (gsl_apertureprop_t *) value;
+
+        KOS_ASSERT(sizebytes == (sizeof(gsl_apertureprop_t) * gsl_driver.shmem.numapertures));
+
+        for (i = 0; i < gsl_driver.shmem.numapertures; i++)
+        {
+            if (gsl_driver.shmem.apertures[i].memarena)
+            {
+                aperture->gpuaddr  = GSL_APERTURE_GETGPUADDR(gsl_driver.shmem, i);
+                aperture->hostaddr = GSL_APERTURE_GETHOSTADDR(gsl_driver.shmem, i);
+            }
+            else
+            {
+                aperture->gpuaddr  = 0x0;
+                aperture->hostaddr = 0x0;
+            }
+            aperture++;
+        }
+
+        break;
+        }
+
+    case GSL_PROP_DEVICE_SHADOW:
+        {
+        gsl_shadowprop_t  *shadowprop = (gsl_shadowprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shadowprop_t));
+
+        kos_memset(shadowprop, 0, sizeof(gsl_shadowprop_t));
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+        if (device->memstore.hostptr)
+        {
+            shadowprop->hostaddr = (unsigned int) device->memstore.hostptr;
+            shadowprop->size     = device->memstore.size;
+            shadowprop->flags    = GSL_FLAGS_INITIALIZED;
+        }
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+        break;
+        }
+
+    default:
+        {
+        if (device->ftbl.device_getproperty)
+        {
+            status = device->ftbl.device_getproperty(device, type, value, sizebytes);
+        }
+
+        break;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_getproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status = GSL_SUCCESS;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_setproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_setproperty)
+        {
+            status = device->ftbl.device_setproperty(device, type, value, sizebytes);
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_setproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_start(gsl_deviceid_t device_id=%D, gsl_flags_t flags=%d)\n", device_id, flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+    
+    kgsl_device_active(device);
+    
+    if (!(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        GSL_API_MUTEX_UNLOCK();
+
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_ERROR, "ERROR: Trying to start uninitialized device.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    device->refcnt++;
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // start device in safe mode
+    if (flags & GSL_FLAGS_SAFEMODE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_INFO, "Running the device in safe mode.\n" );
+        device->flags |= GSL_FLAGS_SAFEMODE;
+    }
+
+    if (device->ftbl.device_start)
+    {
+        status = device->ftbl.device_start(device, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_stop(gsl_deviceid_t device_id)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_stop(gsl_deviceid_t device_id=%D)\n", device_id );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        KOS_ASSERT(device->refcnt);
+
+        device->refcnt--;
+
+        if (device->refcnt == 0)
+        {
+            if (device->ftbl.device_stop)
+            {
+                status = device->ftbl.device_stop(device);
+            }
+        }
+        else
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_stop. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_idle(gsl_deviceid_t device_id=%D, unsigned int timeout=%d)\n", device_id, timeout );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    kgsl_device_active(device);
+    
+    if (device->ftbl.device_idle)
+    {
+        status = device->ftbl.device_idle(device, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_idle. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) // Would otherwise flood the log
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                        "--> int kgsl_device_regread(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int *value=0x%08x)\n", device_id, offsetwords, value );
+#endif
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(value);
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regread)
+    {
+        status = device->ftbl.device_regread(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR )
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regread. Return value %B\n", status );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_regwrite(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int value=0x%08x)\n", device_id, offsetwords, value );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regwrite)
+    {
+        status = device->ftbl.device_regwrite(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regwrite. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_waitirq(gsl_deviceid_t device_id=%D, gsl_intrid_t intr_id=%d, unsigned int *count=0x%08x, unsigned int timout=0x%08x)\n", device_id, intr_id, count, timeout);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->ftbl.device_waitirq)
+    {
+        status = device->ftbl.device_waitirq(device, intr_id, count, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_waitirq. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_runpending(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_runpending(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_runpending)
+        {
+            status = device->ftbl.device_runpending(device);
+        }
+    }
+
+    // free any pending freeontimestamps
+    kgsl_cmdstream_memqueue_drain(device);
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_runpending. Return value %B\n", status );
+
+    return (status);
+}
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_drawctxt.c b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
new file mode 100644
index 000000000000..afa44e618794
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
@@ -0,0 +1,1796 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <asm/div64.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+//#define DISABLE_SHADOW_WRITES
+
+/*
+//////////////////////////////////////////////////////////////////////////////
+//
+// Memory Map for Register, Constant & Instruction Shadow, and Command Buffers (34.5KB)
+//
+// +---------------------+------------+-------------+---+---------------------+
+// | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow |
+// +---------------------+------------+-------------+---+---------------------+
+//   ________________________________/               \___________________
+//  /                                                                    \
+// +--------------+-----------+------+-----------+------------------------+
+// | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused  |
+// +--------------+-----------+------+-----------+------------------------+
+//
+//       8K - ALU Constant Shadow (8K aligned)
+//       4K - H/W Register Shadow (8K aligned)
+//       9K - Command and Vertex Buffers
+//              - Indirect command buffer : Const/Reg restore
+//                      - includes Loop & Bool const shadows
+//              - Indirect command buffer : Const/Reg save
+//              - Quad vertices & texture coordinates
+//              - Indirect command buffer : Gmem save
+//              - Indirect command buffer : Gmem restore
+//              - Unused (padding to 8KB boundary)
+//      <1K - Texture Constant Shadow (768 bytes) (8K aligned)
+//      18K - Shader Instruction Shadow
+//              - 6K vertex (32 byte aligned)
+//              - 6K pixel  (32 byte aligned)
+//              - 6K shared (32 byte aligned)
+//
+// Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes
+// 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of
+// 16 bytes per constant.  If the texture constants were transfered this way,
+// the Command & Vertex Buffers section would extend past the 16K boundary.
+// By moving the texture constant shadow area to start at 16KB boundary, we
+// only require approximately 40 bytes more memory, but are able to use the
+// LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up
+// context switching.
+//
+// [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool
+// constants would require an additional 8KB each, for alignment.]
+//
+//////////////////////////////////////////////////////////////////////////////
+*/
+
+//////////////////////////////////////////////////////////////////////////////
+// Constants
+//////////////////////////////////////////////////////////////////////////////
+
+
+
+
+#define ALU_CONSTANTS           2048                // DWORDS
+#define NUM_REGISTERS           1024                // DWORDS
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_LEN          9216            // DWORDS
+#else
+    #define CMD_BUFFER_LEN          3072            // DWORDS
+#endif
+#define TEX_CONSTANTS           (32*6)              // DWORDS
+#define BOOL_CONSTANTS          8                   // DWORDS
+#define LOOP_CONSTANTS          56                  // DWORDS
+#define SHADER_INSTRUCT_LOG2    9U                  // 2^n == SHADER_INSTRUCTIONS
+
+#if defined(PM4_IM_STORE)
+#define SHADER_INSTRUCT         (1<<SHADER_INSTRUCT_LOG2)   // 96-bit instructions
+#else
+#define SHADER_INSTRUCT         0
+#endif
+
+// LOAD_CONSTANT_CONTEXT shadow size
+#define LCC_SHADOW_SIZE         0x2000              // 8KB
+
+#define ALU_SHADOW_SIZE         LCC_SHADOW_SIZE     // 8KB
+#define REG_SHADOW_SIZE         0x1000              // 4KB
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_SIZE         0x9000          // 36KB
+#else
+    #define CMD_BUFFER_SIZE         0x3000          // 12KB
+#endif
+#define TEX_SHADOW_SIZE         (TEX_CONSTANTS*4)   // 768 bytes
+#define SHADER_SHADOW_SIZE      (SHADER_INSTRUCT*12)// 6KB
+
+#define REG_OFFSET              LCC_SHADOW_SIZE
+#define CMD_OFFSET              (REG_OFFSET + REG_SHADOW_SIZE)
+#define TEX_OFFSET              (CMD_OFFSET + CMD_BUFFER_SIZE)
+#define SHADER_OFFSET           ((TEX_OFFSET + TEX_SHADOW_SIZE + 32) & ~31)
+
+#define CONTEXT_SIZE            (SHADER_OFFSET + 3 * SHADER_SHADOW_SIZE)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// temporary work structure
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct
+{
+    unsigned int    *start;         // Command & Vertex buffer start
+    unsigned int    *cmd;           // Next available dword in C&V buffer
+
+    // address of buffers, needed when creating IB1 command buffers.
+    gpuaddr_t       bool_shadow;    // Address where bool constants are shadowed
+    gpuaddr_t       loop_shadow;    // Address where loop constants are shadowed
+
+#if defined(PM4_IM_STORE)
+    gpuaddr_t       shader_shared;  // Address of shared shader instruction shadow
+    gpuaddr_t       shader_vertex;  // Address of vertex shader instruction shadow
+    gpuaddr_t       shader_pixel;   // Address of pixel shader instruction shadow
+#endif
+
+    gpuaddr_t       reg_values[2];  // Addresses in command buffer where separately handled registers are saved
+    gpuaddr_t       chicken_restore;// Address where the TP0_CHICKEN register value is written
+    gpuaddr_t       gmem_base;      // Base gpu address of GMEM
+}
+ctx_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to calculate IEEE754 single precision float values without FPU
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uint2float( unsigned int uintval )
+{
+    unsigned int exp = 0;
+    unsigned int frac = 0;
+    unsigned int u = uintval;
+
+    // Handle zero separately
+    if( uintval == 0 ) return 0;
+
+    // Find log2 of u
+    if(u>=0x10000) { exp+=16; u>>=16; }
+    if(u>=0x100  ) { exp+=8;  u>>=8;  }
+    if(u>=0x10   ) { exp+=4;  u>>=4;  }
+    if(u>=0x4    ) { exp+=2;  u>>=2;  }
+    if(u>=0x2    ) { exp+=1;  u>>=1;  }
+
+    // Calculate fraction
+    frac = ( uintval & ( ~( 1 << exp ) ) ) << ( 23 - exp );
+
+    // Exp is biased by 127 and shifted 23 bits
+    exp = ( exp + 127 ) << 23;
+
+    return ( exp | frac );
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to divide two unsigned ints and return the result as a floating point value
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uintdivide(unsigned int a, unsigned int b)
+{
+#ifdef _LINUX
+    uint64_t a_fixed = a << 16;
+    uint64_t b_fixed = b << 16;
+#else
+    unsigned int a_fixed = a << 16;
+    unsigned int b_fixed = b << 16;
+#endif
+    // Assume the result is 0.fraction
+    unsigned int fraction;
+    unsigned int exp = 126;
+
+    if( b == 0 ) return 0;
+
+#ifdef _LINUX
+    a_fixed = a_fixed << 32;
+	do_div(a_fixed, b_fixed);
+    fraction = (unsigned int)a_fixed;
+#else
+    fraction = ((unsigned int)((((__int64)a_fixed) << 32) / (__int64)b_fixed));
+#endif
+
+    if( fraction == 0 ) return 0;
+
+    // Normalize
+    while( !(fraction & (1<<31)) )
+    {
+        fraction <<= 1;
+        exp--;
+    }
+    // Remove hidden bit
+    fraction <<= 1;
+
+    // Round
+    if( ( fraction & 0x1ff ) > 256 )
+    {
+        int rounded = 0;
+        int i = 9;
+
+        // Do the bit addition
+        while( !rounded )
+        {
+            if( fraction & (1<<i) )
+            {
+                // 1b + 1b = 0b, carry = 1
+                fraction &= ~(1<<i);
+                i++;
+            }
+            else
+            {
+                fraction |= (1<<i);
+                rounded = 1;
+            }
+        }
+    }
+
+    // Use 23 most significant bits for the fraction
+    fraction >>= 9;
+
+    return ( ( exp << 23 ) | fraction );
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context save (gmem -> sys)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4  P;
+// void main(void)
+// {
+//   gl_Position = P;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_VTX_PGM_LEN    0x12
+
+static const unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = {
+    0x00011003, 0x00001000, 0xc2000000,
+    0x00001004, 0x00001000, 0xc4000000,
+    0x00001005, 0x00002000, 0x00000000,
+    0x1cb81000, 0x00398a88, 0x00000003,
+    0x140f803e, 0x00000000, 0xe2010100,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision highp float;
+// uniform   vec4  clear_color;
+// void main(void)
+// {
+//    gl_FragColor = clear_color;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_FRAG_PGM_LEN   0x0c
+
+static const unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = {
+    0x00000000, 0x1002c400, 0x10000000,
+    0x00001003, 0x00002000, 0x00000000,
+    0x140f8000, 0x00000000, 0x22000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context restore (sys -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4 position;
+// attribute vec4 texcoord;
+// varying   vec4 texcoord0;
+// void main()
+// {
+//    gl_Position = position;
+//    texcoord0 = texcoord;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_VTX_PGM_LEN    0x18
+
+static const unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = {
+    0x00052003, 0x00001000, 0xc2000000, 0x00001005,
+    0x00001000, 0xc4000000, 0x00001006, 0x10071000,
+    0x20000000, 0x18981000, 0x0039ba88, 0x00000003,
+    0x12982000, 0x40257b08, 0x00000002, 0x140f803e,
+    0x00000000, 0xe2010100, 0x140f8000, 0x00000000,
+    0xe2020200, 0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision mediump   float;
+// uniform   sampler2D tex0;
+// varying   vec4      texcoord0;
+// void main()
+// {
+//    gl_FragColor = texture2D(tex0, texcoord0.xy);
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_FRAG_PGM_LEN   0x0f
+
+static const unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = {
+    0x00011002, 0x00001000, 0xc4000000, 0x00001003,
+    0x10041000, 0x20000000, 0x10000001, 0x1ffff688,
+    0x00000002, 0x140f8000, 0x00000000, 0xe2000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// shader texture constants (sysmem -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_TEX_CONST_LEN  6
+
+static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] =
+{
+    // Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat,RFMode=ZeroClamp-1,Dim=1:2d
+    0x00000002,  // Pitch = TBD
+
+    // Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, NearestClamp=1:OGL Mode
+    0x00000806,  // Address[31:12] = TBD
+
+    // Width, Height, EndianSwap=0:None
+    0, // Width & Height = TBD
+
+    // NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, Mip=2:BaseMap
+    0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23,
+
+    // VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, Dim3d=0
+    0,
+
+    // BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, Dim=1:2d, MipPacking=0
+    1 << 9  // Mip Address[31:12] = TBD
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for copying GMEM to context shadow
+//////////////////////////////////////////////////////////////////////////////
+
+#define QUAD_LEN                12
+
+static unsigned int gmem_copy_quad[QUAD_LEN] = {
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000
+};
+
+#define TEXCOORD_LEN            8
+
+static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
+    0x00000000, 0x3f800000,
+    0x3f800000, 0x3f800000,
+    0x00000000, 0x00000000,
+    0x3f800000, 0x00000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// shader linkage info
+//////////////////////////////////////////////////////////////////////////////
+
+#define SHADER_CONST_ADDR       (11 * 6 + 3)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// gmem command buffer length
+//////////////////////////////////////////////////////////////////////////////
+
+#define PM4_REG(reg)            ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+config_gmemsize(gmem_shadow_t *shadow, int gmem_size)
+{
+    int w=64, h=64; // 16KB surface, minimum
+
+    // convert from bytes to 32-bit words
+    gmem_size = (gmem_size + 3)/4;
+
+    // find the right surface size, close to a square.
+    while (w * h < gmem_size)
+        if (w < h)
+            w *= 2;
+        else
+            h *= 2;
+
+    shadow->width  = w;
+    shadow->pitch  = w;
+    shadow->height = h;
+
+    shadow->size = shadow->pitch * shadow->height * 4;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int
+gpuaddr(unsigned int *cmd, gsl_memdesc_t *memdesc)
+{
+    return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+create_ib1(gsl_drawctxt_t *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end)
+{
+    cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    cmd[1] = gpuaddr(start, &drawctxt->gpustate);
+    cmd[2] = end - start;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+program_shader(unsigned int *cmds, int vtxfrag, const unsigned int *shader_pgm, int dwords)
+{
+    // load the patched vertex shader stream
+    *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords);
+    *cmds++ = vtxfrag;                      // 0=vertex shader, 1=fragment shader
+    *cmds++ = ( (0 << 16) | dwords );       // instruction start & size (in 32-bit words)
+
+    kos_memcpy(cmds, shader_pgm, dwords<<2);
+    cmds += dwords;
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+reg_to_mem(unsigned int *cmds, gpuaddr_t dst, gpuaddr_t src, int dwords)
+{
+    while (dwords-- > 0)
+    {
+        *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *cmds++ = src++;
+        *cmds++ = dst;
+        dst += 4;
+    }
+
+    return cmds;
+}
+
+
+
+#ifdef DISABLE_SHADOW_WRITES
+
+static void build_reg_to_mem_range(unsigned int start, unsigned int end, unsigned int** cmd, /*ctx_t *ctx, unsigned int* offset) //*/gsl_drawctxt_t *drawctxt)
+{
+    unsigned int i = start;
+
+    for(i=start; i<=end; i++)
+    {
+        *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *(*cmd)++ = i | (1<<30);
+        *(*cmd)++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + (i-0x2000)*4;
+    }
+}
+
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// chicken restore
+//////////////////////////////////////////////////////////////////////////////
+static unsigned int*
+build_chicken_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmds = start;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate);
+    *cmds++ = 0x00000000;
+
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds);
+
+    return cmds;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context save
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// save h/w regs, alu constants, texture contants, etc. ...
+//   requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regsave_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+#ifdef DISABLE_SHADOW_WRITES
+    // Write HW registers into shadow
+    build_reg_to_mem_range(mmRB_SURFACE_INFO, mmRB_DEPTH_INFO, &cmd, drawctxt);
+    build_reg_to_mem_range(mmCOHER_DEST_BASE_0, mmPA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_MAX_VTX_INDX, mmRB_FOG_COLOR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_STENCILREFMASK_BF, mmPA_CL_VPORT_ZOFFSET, &cmd, drawctxt);
+    build_reg_to_mem_range(mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_DEPTHCONTROL, mmRB_MODECONTROL, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POINT_SIZE, mmPA_SC_LINE_STIPPLE, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_VIZ_QUERY, mmPA_SC_VIZ_QUERY, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_LINE_CNTL, mmSQ_PS_CONST, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_AA_MASK, mmPA_SC_AA_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_VERTEX_REUSE_BLOCK_CNTL, mmRB_DEPTH_CLEAR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_SAMPLE_COUNT_CTL, mmRB_COLOR_DEST_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, drawctxt);
+
+    // Copy ALU constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, mmSQ_CONSTANT_0, ALU_CONSTANTS);
+
+    // Copy Tex constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, mmSQ_FETCH_0, TEX_CONSTANTS);
+#else
+    // H/w registers are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+    *cmd++ = 4 << 16;                       // regs, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // ALU constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+    *cmd++ = 0 << 16;                       // ALU, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // Tex constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+    *cmd++ = 1 << 16;                       // Tex, start=0
+    *cmd++ = 0x0;                           // count = 0
+#endif
+
+
+
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_GPR_MANAGEMENT;
+    *cmd++ = ctx->reg_values[0];
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmTP0_CHICKEN;
+    *cmd++ = ctx->reg_values[1];
+
+    // Copy Boolean constants
+    cmd = reg_to_mem(cmd, ctx->bool_shadow, mmSQ_CF_BOOLEANS, BOOL_CONSTANTS);
+
+    // Copy Loop constants
+    cmd = reg_to_mem(cmd, ctx->loop_shadow, mmSQ_CF_LOOP, LOOP_CONSTANTS);
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_save, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from graphics memory to system memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_gmem2sys_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_save_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // --------------
+    // program shader
+    // --------------
+
+    // load shader vtx constants ... 5 dwords
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR;
+    *cmds++ = 0;
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;      // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                   // limit = 12 dwords
+
+    // Invalidate L2 cache to make sure vertices are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10010001;
+    *cmds++ = 0x00000008;
+
+
+    // --------------
+    // resolve
+    // --------------
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;               // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+    {
+        KOS_ASSERT((ctx->gmem_base & 0xFFF) == 0);   // gmem base assumed 4K aligned.
+        *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+    }
+    else
+        cmds++;
+
+    // disable Z
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (0 << 16) | 0;
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (unsigned int) ((1U << 31) | (0 << 16) | 0);
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000; // -1.0f
+    *cmds++ = 0x0;
+
+    // load the COPY state
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6);
+    *cmds++ = PM4_REG(mmRB_COPY_CONTROL);
+    *cmds++ = 0;                                                // RB_COPY_CONTROL
+
+    *cmds++ = (shadow->gmemshadow.gpuaddr+shadow->offset*4) & 0xfffff000;   // RB_COPY_DEST_BASE
+
+    *cmds++ = shadow->pitch >> 5;           // RB_COPY_DEST_PITCH
+    *cmds++ = 0x0003c058;                   // Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,MaskWrite:R=G=B=A=1
+
+    {
+        // Calculate the new offset based on the adjusted base
+        unsigned int addr = (shadow->gmemshadow.gpuaddr+shadow->offset*4);
+        unsigned int offset = (addr-(addr&0xfffff000))/4;
+
+        kos_assert( (offset & 0xfffff000) == 0 ); // Make sure we stay in offsetx field.
+
+        *cmds++ = offset;
+    }
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x6;                          // EDRAM copy
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_save, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context restore
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from system memory to graphics memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_sys2gmem_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_restore_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // ----------------
+    // shader constants
+    // ----------------
+
+    // vertex buffer constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7);
+
+    *cmds++ = (0x1 << 16) | (9 * 6);
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;          // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                       // limit = 12 dwords
+    *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3;         // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000020;                       // limit = 8 dwords
+    *cmds++ = 0;
+    *cmds++ = 0;
+
+    // Invalidate L2 cache to make sure vertices and texture coordinates are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10030002;
+    *cmds++ = 0x00000008;
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_VIZ_QUERY);
+    *cmds++ = 0x0;        //mmPA_SC_VIZ_QUERY
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLORCONTROL);
+    *cmds++ = 0x00000c20; // RB_COLORCONTROL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmVGT_VERTEX_REUSE_BLOCK_CNTL);
+    *cmds++ = 0x00000002; //mmVGT_VERTEX_REUSE_BLOCK_CNTL
+    *cmds++ = 0x00000002; //mmVGT_OUT_DEALLOC_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmSQ_INTERPOLATOR_CNTL);
+    //*cmds++ = 0x0000ffff; //mmSQ_INTERPOLATOR_CNTL
+    *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_CONFIG);
+    *cmds++ = 0x00000000; //mmPA_SC_AA_CONFIG
+
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // texture constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1));
+    *cmds++ = (0x1 << 16) | (0 * 6);
+    kos_memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN<<2);
+    cmds[0] |= (shadow->pitch >> 5) << 22;
+    cmds[1] |= shadow->gmemshadow.gpuaddr;
+    cmds[2] |= (shadow->width+shadow->offset_x-1) | (shadow->height+shadow->offset_y-1) << 13;
+    cmds += SYS2GMEM_TEX_CONST_LEN;
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = drawctxt->context_gmem_shadow.pitch; // GMEM pitch is equal to context GMEM shadow pitch
+
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+        *cmds++ = (COLORX_8_8_8_8 << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+    else
+        cmds++;
+
+    // RB_DEPTHCONTROL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;                            // disable Z
+
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (0 << 16) | 0;
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (unsigned int) ((1U << 31) | (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x);
+    *cmds++ = (drawctxt->context_gmem_shadow.height << 16) | drawctxt->context_gmem_shadow.width;
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;                   // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000;
+    *cmds++ = 0x0;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_MASK);
+    *cmds++ = 0x0000000f;                   // R = G = B = 1:enabled
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_DEST_MASK);
+    *cmds++ = 0xffffffff;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_WRAPPING_0);
+    *cmds++ = 0x00000000;
+    *cmds++ = 0x00000000;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x4;                          // draw pixels with color and depth/stencil component
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_restore, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// restore h/w regs, alu constants, texture constants, etc. ...
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned *
+reg_range(unsigned int *cmd, unsigned int start, unsigned int end)
+{
+    *cmd++ = PM4_REG(start);                // h/w regs, start addr
+    *cmd++ = end - start + 1;               // count
+    return cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regrestore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+
+    //*cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    //*cmd++ = 0;
+
+    // H/W Registers
+    cmd++; // deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???);
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; // Force mismatch
+#else
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+#endif
+
+    cmd = reg_range(cmd, mmRB_SURFACE_INFO,                 mmPA_SC_SCREEN_SCISSOR_BR);
+    cmd = reg_range(cmd, mmPA_SC_WINDOW_OFFSET,             mmPA_SC_WINDOW_SCISSOR_BR);
+    cmd = reg_range(cmd, mmVGT_MAX_VTX_INDX,                mmPA_CL_VPORT_ZOFFSET);
+    cmd = reg_range(cmd, mmSQ_PROGRAM_CNTL,                 mmSQ_WRAPPING_1);
+    cmd = reg_range(cmd, mmRB_DEPTHCONTROL,                 mmRB_MODECONTROL);
+    cmd = reg_range(cmd, mmPA_SU_POINT_SIZE,                mmPA_SC_VIZ_QUERY/*mmVGT_ENHANCE*/);
+    cmd = reg_range(cmd, mmPA_SC_LINE_CNTL,                 mmRB_COLOR_DEST_MASK);
+    cmd = reg_range(cmd, mmPA_SU_POLY_OFFSET_FRONT_SCALE,   mmPA_SU_POLY_OFFSET_BACK_OFFSET);
+
+    // Now we know how many register blocks we have, we can compute command length
+    start[0] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd-start)-1);
+#ifdef DISABLE_SHADOW_WRITES
+    start[2] |= (0<<24) | (4 << 16);    // Disable shadowing.
+#else
+    start[2] |= (1<<24) | (4 << 16);    // Enable shadowing for the entire register block.
+#endif
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type0_packet(mmSQ_GPR_MANAGEMENT, 1);
+    ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00040400;
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+    *cmd++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00000000;
+
+    // ALU Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (0<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (0<<16) | 0;
+#endif
+    *cmd++ = ALU_CONSTANTS;
+
+
+    // Texture Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (1<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (1<<16) | 0;
+#endif
+    *cmd++ = TEX_CONSTANTS;
+
+
+    // Boolean Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS);
+    *cmd++ = (2<<16) | 0;
+
+    // the next BOOL_CONSTANT dwords is the shadow area for boolean constants.
+    ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += BOOL_CONSTANTS;
+
+
+    // Loop Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS);
+    *cmd++ = (3<<16) | 0;
+
+    // the next LOOP_CONSTANTS dwords is the shadow area for loop constants.
+    ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += LOOP_CONSTANTS;
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_restore, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for saving/restoring gmem
+//////////////////////////////////////////////////////////////////////////////
+
+static void set_gmem_copy_quad( gmem_shadow_t* shadow )
+{
+    unsigned int tex_offset[2];
+
+    // set vertex buffer values
+
+    gmem_copy_quad[1] = uint2float( shadow->height + shadow->gmem_offset_y );
+    gmem_copy_quad[3] = uint2float( shadow->width + shadow->gmem_offset_x );
+    gmem_copy_quad[4] = uint2float( shadow->height + shadow->gmem_offset_y );
+    gmem_copy_quad[9] = uint2float( shadow->width + shadow->gmem_offset_x );
+
+    gmem_copy_quad[0] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[6] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[7] = uint2float( shadow->gmem_offset_y );
+    gmem_copy_quad[10] = uint2float( shadow->gmem_offset_y );
+
+    tex_offset[0] = uintdivide( shadow->offset_x, (shadow->offset_x+shadow->width) );
+    tex_offset[1] = uintdivide( shadow->offset_y, (shadow->offset_y+shadow->height) );
+
+    gmem_copy_texcoord[0] = gmem_copy_texcoord[4] = tex_offset[0];
+    gmem_copy_texcoord[5] = gmem_copy_texcoord[7] = tex_offset[1];
+
+    // copy quad data to vertex buffer
+    kos_memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
+
+    // copy tex coord data to tex coord buffer
+    kos_memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, TEXCOORD_LEN << 2);
+}
+
+
+static void
+build_quad_vtxbuff(gsl_drawctxt_t *drawctxt, ctx_t *ctx, gmem_shadow_t* shadow)
+{
+    unsigned int *cmd = ctx->cmd;
+
+    // quad vertex buffer location
+    shadow->quad_vertices.hostptr = cmd;
+    shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += QUAD_LEN;
+
+    // tex coord buffer location (in GPU space)
+    shadow->quad_texcoords.hostptr = cmd;
+    shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+
+
+    cmd += TEXCOORD_LEN;
+
+    set_gmem_copy_quad(shadow);
+
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_shader_save_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *cmd = ctx->cmd;
+    unsigned int *save, *restore, *fixup;
+#if defined(PM4_IM_STORE)
+    unsigned int *startSizeVtx, *startSizePix, *startSizeShared;
+#endif
+    unsigned int *partition1;
+    unsigned int *shaderBases, *partition2;
+
+#if defined(PM4_IM_STORE)
+    // compute vertex, pixel and shared instruction shadow GPU addresses
+    ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
+    ctx->shader_pixel  = ctx->shader_vertex + SHADER_SHADOW_SIZE;
+    ctx->shader_shared = ctx->shader_pixel  + SHADER_SHADOW_SIZE;
+#endif
+
+
+    //-------------------------------------------------------------------
+    // restore shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    restore = cmd;  // start address
+
+    // Invalidate Vertex & Pixel instruction code address and sizes
+    *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1);
+    *cmd++ = 0x00000300;                        // 0x100 = Vertex, 0x200 = Pixel
+
+    // Restore previous shader vertex & pixel instruction bases.
+    *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1);
+    shaderBases = cmd++;                        // TBD #5: shader bases (from fixup)
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSQ_INST_STORE_MANAGMENT, 1);
+    partition1 = cmd++;                         // TBD #4a: partition info (from save)
+
+#if defined(PM4_IM_STORE)
+    // load vertex shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;          // 0x0 = Vertex
+    startSizeVtx = cmd++;                       // TBD #1: start/size (from save)
+
+    // load pixel shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;           // 0x1 = Pixel
+    startSizePix = cmd++;                       // TBD #2: start/size (from save)
+
+    // load shared shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_shared + 0x2;          // 0x2 = Shared
+    startSizeShared = cmd++;                    // TBD #3: start/size (from save)
+#endif
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd);
+
+
+    //-------------------------------------------------------------------
+    // fixup SET_SHADER_BASES data
+    //
+    // since self-modifying PM4 code is being used here, a seperate
+    // command buffer is used for this fixup operation, to ensure the
+    // commands are not read by the PM4 engine before the data fields
+    // have been written.
+    //-------------------------------------------------------------------
+
+    fixup = cmd;        // start address
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSCRATCH_REG2, 1);
+    partition2 = cmd++;                                 // TBD #4b: partition info (from save)
+
+    // mask off unused bits, then OR with shader instruction memory size
+    *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = 0x0FFF0FFF;                                // AND off invalid bits.
+    *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2-5U) << 29);               // OR in instruction memory size
+
+    // write the computed value to the SET_SHADER_BASES data field
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); // TBD #5: shader bases (to restore)
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd);
+
+
+    //-------------------------------------------------------------------
+    // save shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    save = cmd;     // start address
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+    // Fetch the SQ_INST_STORE_MANAGMENT register value,
+    // Store the value in the data fields of the SET_CONSTANT commands above.
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition1, &drawctxt->gpustate);      // TBD #4a: partition info (to restore)
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition2, &drawctxt->gpustate);      // TBD #4b: partition info (to fixup)
+
+#if defined(PM4_IM_STORE)
+    // Store the vertex shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;                      // 0x0 = Vertex
+    *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate);    // TBD #1: start/size (to restore)
+
+    // store the pixel shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;                       // 0x1 = Pixel
+    *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate);    // TBD #2: start/size (to restore)
+
+    // Store the shared shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_shared + 0x2;                      // 0x2 = Shared
+    *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); // TBD #3: start/size (to restore)
+#endif
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+
+
+    // Create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_save, save, cmd);
+
+
+    ctx->cmd = cmd;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create buffers for saving/restoring registers and constants
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gpustate_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    gsl_flags_t flags;
+
+    flags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_EMEM | GSL_MEMFLAGS_ALIGN8K));
+
+    // allocate memory to allow HW to save sub-blocks for efficient context save/restore
+    if (kgsl_sharedmem_alloc0(device->id, flags, CONTEXT_SIZE, &drawctxt->gpustate) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW;
+
+    // Blank out h/w register, constant, and command buffer shadows.
+    kgsl_sharedmem_set0(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE);
+
+    // set-up command and vertex buffer pointers
+    ctx->cmd = ctx->start = (unsigned int *) ((char *)drawctxt->gpustate.hostptr + CMD_OFFSET);
+
+    // build indirect command buffers to save & restore regs/constants
+    build_regrestore_cmds(drawctxt, ctx);
+    build_regsave_cmds(drawctxt, ctx);
+
+    build_shader_save_restore_cmds(drawctxt, ctx);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Allocate GMEM shadow buffer
+//////////////////////////////////////////////////////////////////////////////
+static int
+allocate_gmem_shadow_buffer(gsl_device_t *device, gsl_drawctxt_t *drawctxt)
+{
+    // allocate memory for GMEM shadow
+    if (kgsl_sharedmem_alloc0(device->id, (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K),
+        drawctxt->context_gmem_shadow.size, &drawctxt->context_gmem_shadow.gmemshadow) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    // blank out gmem shadow.
+    kgsl_sharedmem_set0(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, drawctxt->context_gmem_shadow.size);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create GMEM save/restore specific stuff
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gmem_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int i;
+    config_gmemsize(&drawctxt->context_gmem_shadow, device->gmemspace.sizebytes);
+    ctx->gmem_base = device->gmemspace.gpu_base;
+
+    if( drawctxt->flags & CTXT_FLAGS_GMEM_SHADOW )
+    {
+        if( allocate_gmem_shadow_buffer(device, drawctxt) != GSL_SUCCESS )
+            return GSL_FAILURE;
+    }
+    else
+    {
+        kos_memset( &drawctxt->context_gmem_shadow.gmemshadow, 0, sizeof( gsl_memdesc_t ) );
+    }
+
+    // build quad vertex buffer
+    build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    // build TP0_CHICKEN register restore command buffer
+    ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx);
+
+    // build indirect command buffers to save & restore gmem
+    drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd;
+    ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+    drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd;
+    ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        // build quad vertex buffer
+        build_quad_vtxbuff(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        // build indirect command buffers to save & restore gmem
+        drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd;
+        ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd;
+        ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+    }
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// init draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_init(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// close draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_close(gsl_device_t *device)
+{
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create a new drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_drawctxt_t  *drawctxt;
+    int             index;
+    ctx_t           ctx;
+
+    kgsl_device_active(device);
+    
+    if (device->drawctxt_count >= GSL_CONTEXT_MAX)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // find a free context slot
+    index = 0;
+    while (index < GSL_CONTEXT_MAX)
+    {
+        if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE)
+            break;
+
+        index++;
+    }
+
+    if (index >= GSL_CONTEXT_MAX)
+    {
+        return (GSL_FAILURE);
+    }
+
+    drawctxt = &device->drawctxt[index];
+
+    kos_memset( &drawctxt->context_gmem_shadow, 0, sizeof( gmem_shadow_t ) );
+
+	drawctxt->pid   = GSL_CALLER_PROCESSID_GET();
+    drawctxt->flags = CTXT_FLAGS_IN_USE;
+    drawctxt->type  = type;
+
+    device->drawctxt_count++;
+
+    // create context shadows, when not running in safe mode
+    if (!(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        if (create_gpustate_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            return (GSL_FAILURE);
+        }
+
+        // Save the shader instruction memory on context switching
+        drawctxt->flags |= CTXT_FLAGS_SHADER_SAVE;
+
+        if(!(flags & GSL_CONTEXT_NO_GMEM_ALLOC))
+            drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW;
+
+        // Clear out user defined GMEM shadow buffer structs
+        kos_memset( drawctxt->user_gmem_shadow, 0, sizeof(gmem_shadow_t)*GSL_MAX_GMEM_SHADOW_BUFFERS );
+
+        // create gmem shadow
+        if (create_gmem_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            return (GSL_FAILURE);
+        }
+
+
+        KOS_ASSERT(ctx.cmd - ctx.start <= CMD_BUFFER_LEN);
+    }
+
+    *drawctxt_id = index;
+
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy a drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+    gsl_drawctxt_t *drawctxt;
+
+    drawctxt = &device->drawctxt[drawctxt_id];
+
+    if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+    {
+        // deactivate context
+        if (device->drawctxt_active == drawctxt)
+        {
+            // no need to save GMEM or shader, the context is being destroyed.
+            drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | CTXT_FLAGS_SHADER_SAVE);
+
+            kgsl_drawctxt_switch(device, GSL_CONTEXT_NONE, 0);
+        }
+
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // destroy state shadow, if allocated
+        if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+            kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+
+        // destroy gmem shadow, if allocated
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+
+        drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+		drawctxt->pid   = 0;
+
+        device->drawctxt_count--;
+        KOS_ASSERT(device->drawctxt_count >= 0);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Binds a user specified buffer as GMEM shadow area
+//
+// gmem_rect:   defines the rectangle that is copied from GMEM. X and Y
+//              coordinates need to be multiples of 8 after conversion to 32bpp.
+//              X, Y, width, and height need to be at 32-bit boundary to avoid
+//              rounding.
+//
+// shadow_x & shadow_y: Position in GMEM shadow buffer where the contents of
+//                      gmem_rect is copied. Both must be multiples of 8 after
+//                      conversion to 32bpp. They also need to be at 32-bit
+//                      boundary to avoid rounding.
+//
+// shadow_buffer:   Description of the GMEM shadow buffer. BPP needs to be
+//                  8, 16, 32, 64, or 128. Enabled tells if the buffer is
+//                  used or not (values 0 and 1). All the other buffer
+//                  parameters are ignored when enabled=0.
+//
+// buffer_id: Two different buffers can be defined. Use buffer IDs 0 and 1.
+//
+//
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    gsl_device_t   *device;
+    gsl_drawctxt_t *drawctxt;
+    gmem_shadow_t  *shadow; // Shadow struct being modified
+    unsigned int    i;
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    drawctxt = &device->drawctxt[drawctxt_id];
+
+    shadow = &drawctxt->user_gmem_shadow[buffer_id];
+
+    if( !shadow_buffer->enabled )
+    {
+        // Disable shadow
+        shadow->gmemshadow.size = 0;
+    }
+    else
+    {
+        // Binding to a buffer
+        unsigned int width, height, gmem_x, gmem_y, gmem_width, gmem_height, pixel_ratio;
+
+        KOS_ASSERT(shadow_buffer->stride_bytes%4 == 0);
+
+        // Convert to 32bpp pixel units
+        if( shadow_buffer->bpp <= 32 )
+        {
+            KOS_ASSERT(32%shadow_buffer->bpp==0);
+            pixel_ratio = 32/shadow_buffer->bpp;
+            KOS_ASSERT(gmem_rect->x%pixel_ratio==0); // Needs to be at 32bit boundary
+            gmem_x = gmem_rect->x/pixel_ratio;
+            KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8
+            KOS_ASSERT(gmem_rect->y%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_y = gmem_rect->y/pixel_ratio;
+            KOS_ASSERT(gmem_y%8==0);  // Needs to be a multiple of 8
+            KOS_ASSERT(gmem_rect->width%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_width = gmem_rect->width/pixel_ratio;
+            KOS_ASSERT(gmem_rect->height%pixel_ratio==0);  // Needs to be at 32bit boundary
+            gmem_height = gmem_rect->height/pixel_ratio;
+            KOS_ASSERT(shadow_x%pixel_ratio==0);  // Needs to be at 32bit boundary
+            shadow_x = shadow_x/pixel_ratio;
+            KOS_ASSERT(shadow_x%8==0);  // Needs to be a multiple of 8
+            KOS_ASSERT(shadow_y%pixel_ratio==0);  // Needs to be at 32bit boundary
+            shadow_y = shadow_y/pixel_ratio;
+            KOS_ASSERT(shadow_y%8==0);  // Needs to be a multiple of 8
+        }
+        else
+        {
+            KOS_ASSERT(shadow_buffer->bpp==64 || shadow_buffer->bpp==128);
+            pixel_ratio = shadow_buffer->bpp/32;
+            gmem_x = gmem_rect->x*pixel_ratio;
+            KOS_ASSERT(gmem_x%8==0); // Needs to be a multiple of 8
+            gmem_y = gmem_rect->y*pixel_ratio;
+            KOS_ASSERT(gmem_y%8==0);  // Needs to be a multiple of 8
+            gmem_width = gmem_rect->width*pixel_ratio;
+            gmem_height = gmem_rect->height*pixel_ratio;
+            shadow_x = shadow_x*pixel_ratio;
+            KOS_ASSERT(shadow_x%8==0);  // Needs to be a multiple of 8
+            shadow_y = shadow_y*pixel_ratio;
+            KOS_ASSERT(shadow_y%8==0);  // Needs to be a multiple of 8
+        }
+
+        KOS_ASSERT( buffer_id >= 0 && buffer_id < GSL_MAX_GMEM_SHADOW_BUFFERS );
+
+        width = gmem_width < drawctxt->context_gmem_shadow.width ? gmem_width : drawctxt->context_gmem_shadow.width;
+        height = gmem_height < drawctxt->context_gmem_shadow.height ? gmem_height : drawctxt->context_gmem_shadow.height;
+
+        drawctxt->user_gmem_shadow[buffer_id].width = width;
+        drawctxt->user_gmem_shadow[buffer_id].height = height;
+        drawctxt->user_gmem_shadow[buffer_id].pitch = shadow_buffer->stride_bytes/4;
+
+        kos_memcpy( &drawctxt->user_gmem_shadow[buffer_id].gmemshadow, &shadow_buffer->data, sizeof( gsl_memdesc_t ) );
+        // Calculate offset
+        drawctxt->user_gmem_shadow[buffer_id].offset = (int)shadow_buffer->stride_bytes/4*((int)shadow_y-(int)gmem_y)+(int)shadow_x-(int)gmem_x;
+
+        drawctxt->user_gmem_shadow[buffer_id].offset_x = shadow_x;
+        drawctxt->user_gmem_shadow[buffer_id].offset_y = shadow_y;
+        drawctxt->user_gmem_shadow[buffer_id].gmem_offset_x = gmem_x;
+        drawctxt->user_gmem_shadow[buffer_id].gmem_offset_y = gmem_y;
+
+        drawctxt->user_gmem_shadow[buffer_id].size = drawctxt->user_gmem_shadow[buffer_id].gmemshadow.size;
+
+        // Modify quad vertices
+        set_gmem_copy_quad(shadow);
+
+        // Modify commands
+        build_gmem2sys_cmds(drawctxt, NULL, shadow);
+        build_sys2gmem_cmds(drawctxt, NULL, shadow);
+
+        // Release context GMEM shadow if found
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+    }
+
+    // Enable GMEM shadowing if we have any of the user buffers enabled
+    drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW;
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+        {
+            drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// switch drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags)
+{
+    gsl_drawctxt_t *active_ctxt = device->drawctxt_active;
+
+	if (drawctxt != GSL_CONTEXT_NONE)
+	{
+		if(0) // flags & GSL_CONTEXT_SAVE_GMEM )
+		{
+			// Set the flag in context so that the save is done when this context is switched out.
+			drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE;
+		}
+		else
+		{
+			// Remove GMEM saving flag from the context
+			drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE;
+		}
+	}
+
+    // already current?
+    if (active_ctxt == drawctxt)
+    {
+        return;
+    }
+
+    // save old context, when not running in safe mode
+    if (active_ctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        // save registers and constants.
+        kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3, active_ctxt->pid);
+
+        if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE)
+        {
+            // save shader partitioning and instructions.
+			kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->shader_save, 3, active_ctxt->pid);
+
+            // fixup shader partitioning parameter for SET_SHADER_BASES.
+			kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->shader_fixup, 3, active_ctxt->pid);
+
+            active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE;
+        }
+
+        if (active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW && active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE )
+        {
+            // save gmem.  (note: changes shader.  shader must already be saved.)
+
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( active_ctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->user_gmem_shadow[i].gmem_save, 3, active_ctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->context_gmem_shadow.gmem_save, 3, active_ctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+            }
+
+            active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE;
+        }
+    }
+
+    device->drawctxt_active = drawctxt;
+
+    // restore new context, when not running in safe mode
+    if (drawctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, drawctxt->gpustate.gpuaddr, (unsigned int)drawctxt->gpustate.hostptr, LCC_SHADOW_SIZE + REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE , "kgsl_drawctxt_switch"));
+
+        // restore gmem.  (note: changes shader.  shader must not already be restored.)
+        if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE)
+        {
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, drawctxt->user_gmem_shadow[i].gmem_restore, 3, drawctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, drawctxt->context_gmem_shadow.gmem_restore, 3, drawctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+            }
+
+            drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
+        }
+
+        // restore registers and constants.
+		kgsl_ringbuffer_issuecmds(device, 0, drawctxt->reg_restore, 3, drawctxt->pid);
+
+        // restore shader instructions & partitioning.
+        if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE)
+        {
+			kgsl_ringbuffer_issuecmds(device, 0, drawctxt->shader_restore, 3, drawctxt->pid);
+        }
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy all drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+int
+kgsl_drawctxt_destroyall(gsl_device_t *device)
+{
+    int             i;
+    gsl_drawctxt_t  *drawctxt;
+
+    for (i = 0; i < GSL_CONTEXT_MAX; i++)
+    {
+        drawctxt = &device->drawctxt[i];
+
+        if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+        {
+            // destroy state shadow, if allocated
+            if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+                kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+            // destroy gmem shadow, if allocated
+            if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+            {
+                kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+                drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+            }
+
+            drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+
+            device->drawctxt_count--;
+            KOS_ASSERT(device->drawctxt_count >= 0);
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c
new file mode 100644
index 000000000000..1d1564022b19
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_driver.c
@@ -0,0 +1,330 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PROCESSID_NONE          0x00000000
+
+#define GSL_DRVFLAGS_EXTERNAL       0x10000000
+#define GSL_DRVFLAGS_INTERNAL       0x20000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// globals
+//////////////////////////////////////////////////////////////////////////////
+#ifndef KGSL_USER_MODE
+static gsl_flags_t  gsl_driver_initialized = 0;
+gsl_driver_t        gsl_driver;
+#else
+extern gsl_flags_t  gsl_driver_initialized;
+extern gsl_driver_t gsl_driver;
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_driver_init0(gsl_flags_t flags, gsl_flags_t flags_debug)
+{
+    int  status = GSL_SUCCESS;
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+#ifdef GSL_LOG
+        // Uncomment these to enable logging.
+        //kgsl_log_init();
+        //kgsl_log_open_stdout( KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+        //kgsl_log_open_file( "c:\\kgsl_log.txt", KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+#endif
+        kos_memset(&gsl_driver, 0, sizeof(gsl_driver_t));
+
+        GSL_API_MUTEX_CREATE();
+    }
+
+#ifdef _DEBUG
+    // set debug flags on every entry, and prior to hal initialization
+    gsl_driver.flags_debug |= flags_debug;
+#else
+    (void) flags_debug;     // unref formal parameter
+#endif // _DEBUG
+
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        KGSL_DEBUG_DUMPX_OPEN("dumpx.tb", 0);
+        KGSL_DEBUG_DUMPX( BB_DUMP_ENABLE, 0, 0, 0, " ");
+    });
+
+    KGSL_DEBUG_TBDUMP_OPEN("tbdump.txt");
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // init hal
+        status = kgsl_hal_init();
+
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver_initialized |= flags;
+            gsl_driver_initialized |= GSL_FLAGS_INITIALIZED0;
+        }
+
+        GSL_API_MUTEX_UNLOCK();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_close0(gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    if ((gsl_driver_initialized & GSL_FLAGS_INITIALIZED0) && (gsl_driver_initialized & flags))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // close hall
+        status = kgsl_hal_close();
+
+        GSL_API_MUTEX_UNLOCK();
+
+        GSL_API_MUTEX_FREE();
+
+#ifdef GSL_LOG
+        kgsl_log_close();
+#endif
+
+        gsl_driver_initialized &= ~flags;
+        gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED0;
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            KGSL_DEBUG_DUMPX_CLOSE();
+        });
+
+        KGSL_DEBUG_TBDUMP_CLOSE();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_init()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_init0(GSL_DRVFLAGS_EXTERNAL, 0));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_close()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_close0(GSL_DRVFLAGS_EXTERNAL));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_entry(gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    int           index, i;
+    unsigned int  pid;
+
+    if (kgsl_driver_init0(GSL_DRVFLAGS_INTERNAL, flags) != GSL_SUCCESS)
+    {
+        return (GSL_FAILURE);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_entry( gsl_flags_t flags=%d )\n", flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    pid = GSL_CALLER_PROCESSID_GET();
+
+    // if caller process has not already opened access
+    status = kgsl_driver_getcallerprocessindex(pid, &index);
+    if (status != GSL_SUCCESS)
+    {
+        // then, add caller pid to process table
+        status = kgsl_driver_getcallerprocessindex(GSL_PROCESSID_NONE, &index);
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver.callerprocess[index] = pid;
+            gsl_driver.refcnt++;
+        }
+    }
+
+    if (status == GSL_SUCCESS)
+    {
+        if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+        {
+            // init memory apertures
+            status = kgsl_sharedmem_init(&gsl_driver.shmem);
+            if (status == GSL_SUCCESS)
+            {
+                // init devices
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+                    status = kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1));
+                    if (status != GSL_SUCCESS)
+                    {
+			continue;
+                    }
+                }
+            }
+
+            if (status == GSL_SUCCESS)
+            {
+                gsl_driver_initialized |= GSL_FLAGS_INITIALIZED;
+            }
+        }
+
+        // walk through process attach callbacks
+        if (status == GSL_SUCCESS)
+        {
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                status = kgsl_device_attachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+        }
+
+        // if something went wrong
+        if (status != GSL_SUCCESS)
+        {
+            // then, remove caller pid from process table
+            if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+            {
+                gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+                gsl_driver.refcnt--;
+            }
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_entry. Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_exit0(unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  index, i;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (gsl_driver_initialized & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+        {
+            // walk through process detach callbacks
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                // Empty the freememqueue of this device
+                kgsl_cmdstream_memqueue_drain(&gsl_driver.device[i]);
+
+                // Detach callback
+                status = kgsl_device_detachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+
+            // last running caller process
+            if (gsl_driver.refcnt - 1 == 0)
+            {
+                // close devices
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+                    kgsl_device_close(&gsl_driver.device[i]);
+                }
+
+                // shutdown memory apertures
+                kgsl_sharedmem_close(&gsl_driver.shmem);
+
+                gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED;
+            }
+
+            // remove caller pid from process table
+            gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+            gsl_driver.refcnt--;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_driver_close0(GSL_DRVFLAGS_INTERNAL);
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_exit(void)
+{
+    int status;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_exit()\n" );
+
+    status = kgsl_driver_exit0(GSL_CALLER_PROCESSID_GET());
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_exit(). Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_destroy(unsigned int pid)
+{
+    return (kgsl_driver_exit0(pid));
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_g12.c b/drivers/mxc/amd-gpu/common/gsl_g12.c
new file mode 100644
index 000000000000..513f6728a842
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_g12.c
@@ -0,0 +1,987 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "kos_libapi.h"
+#include "gsl_cmdstream.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+#ifdef GSL_BLD_G12
+#define GSL_TIMESTAMP_EPSILON   20000
+#define GSL_IRQ_TIMEOUT         200
+
+
+//----------------------------------------------------------------------------
+
+#define GSL_HAL_NUMCMDBUFFERS           5
+#define GSL_HAL_CMDBUFFERSIZE           (1024 + 13) * sizeof(unsigned int)
+
+#define     ALIGN_IN_BYTES( dim, alignment ) ( ( (dim) + (alignment-1) ) & ~(alignment-1) )
+
+
+#ifdef _Z180
+#define     NUMTEXUNITS                         4
+#define     TEXUNITREGCOUNT                     25
+#define     VG_REGCOUNT                         0x39
+#define     GSL_HAL_EDGE0BUFSIZE                0x3E8+64
+#define     GSL_HAL_EDGE1BUFSIZE                0x8000+64
+#define     GSL_HAL_EDGE2BUFSIZE                0x80020+64
+#define     GSL_HAL_EDGE0REG                    ADDR_VGV1_CBUF
+#define     GSL_HAL_EDGE1REG                    ADDR_VGV1_BBUF
+#define     GSL_HAL_EDGE2REG                    ADDR_VGV1_EBUF
+#else
+#define     NUMTEXUNITS                          2
+#define     TEXUNITREGCOUNT                      24
+#define     VG_REGCOUNT                          0x3A
+#define     L1TILESIZE                           64
+#define     GSL_HAL_EDGE0BUFSIZE                 L1TILESIZE*L1TILESIZE*4+64
+#define     GSL_HAL_EDGE1BUFSIZE                 L1TILESIZE*L1TILESIZE*16+64
+#define     GSL_HAL_EDGE0REG                     ADDR_VGV1_CBASE1
+#define     GSL_HAL_EDGE1REG                     ADDR_VGV1_UBASE2
+#endif
+
+#define     PACKETSIZE_BEGIN        3
+#define     PACKETSIZE_G2DCOLOR     2
+#define     PACKETSIZE_TEXUNIT      (TEXUNITREGCOUNT*2)
+#define     PACKETSIZE_REG          (VG_REGCOUNT*2)
+#define     PACKETSIZE_STATE        (PACKETSIZE_TEXUNIT*NUMTEXUNITS + PACKETSIZE_REG + PACKETSIZE_BEGIN + PACKETSIZE_G2DCOLOR)
+#define     PACKETSIZE_STATESTREAM   ALIGN_IN_BYTES((PACKETSIZE_STATE*sizeof(unsigned int)), 32) / sizeof(unsigned int) 
+
+//----------------------------------------------------------------------------
+
+typedef struct
+{
+    unsigned int id;
+   // unsigned int regs[];
+}gsl_hal_z1xxdrawctx_t;
+
+typedef struct
+{
+  unsigned int      offs;
+  unsigned int      curr;
+  unsigned int      prevctx;
+
+  gsl_memdesc_t     e0;
+  gsl_memdesc_t     e1;
+  gsl_memdesc_t     e2;
+  unsigned int*     cmdbuf[GSL_HAL_NUMCMDBUFFERS];
+  gsl_memdesc_t     cmdbufdesc[GSL_HAL_NUMCMDBUFFERS];
+  gsl_timestamp_t   timestamp[GSL_HAL_NUMCMDBUFFERS];
+
+  unsigned int      numcontext;
+}gsl_z1xx_t;
+
+static gsl_z1xx_t   g_z1xx      = {0}; 
+
+//----------------------------------------------------------------------------
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp);
+static int kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags);
+static int kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+static int kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+static unsigned int drawctx_id  = 0;
+static int kgsl_g12_idle(gsl_device_t *device, unsigned int timeout);
+#ifndef _LINUX
+static void irq_thread(void);
+#endif
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_g12_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // non-error condition interrupt
+        case GSL_INTR_G12_G2D:
+#ifdef _LINUX
+			queue_work(device->irq_workq, &(device->irq_work));
+			break;
+#endif		
+#ifndef _Z180
+        case GSL_INTR_G12_FBC:
+#endif //_Z180
+            // signal intr completion event
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        // error condition interrupt
+        case GSL_INTR_G12_FIFO:
+            device->ftbl.device_destroy(device);
+            break;
+
+        case GSL_INTR_G12_MH:
+            // don't do anything. this is handled by the MMU manager
+            break;
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_isr(gsl_device_t *device)
+{
+    unsigned int           status;
+#ifdef _DEBUG
+    REG_MH_MMU_PAGE_FAULT  page_fault = {0};
+    REG_MH_AXI_ERROR       axi_error  = {0};
+#endif // DEBUG
+
+    // determine if G12 is interrupting
+    device->ftbl.device_regread(device, (ADDR_VGC_IRQSTATUS >> 2), &status);
+
+    if (status)
+    {
+        // if G12 MH is interrupting, clear MH block interrupt first, then master G12 MH interrupt
+        if (status & (1 << VGC_IRQSTATUS_MH_FSHIFT))
+        {
+#ifdef _DEBUG
+            // obtain mh error information
+            device->ftbl.device_regread(device, ADDR_MH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+            device->ftbl.device_regread(device, ADDR_MH_AXI_ERROR, (unsigned int *)&axi_error);
+#endif // DEBUG
+
+            kgsl_intr_decode(device, GSL_INTR_BLOCK_G12_MH);
+        }
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_G12);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+#ifndef GSL_NO_MMU
+    REG_MH_MMU_INVALIDATE  mh_mmu_invalidate = {0};
+
+    // unreferenced formal parameter
+	(void) pid;
+
+    mh_mmu_invalidate.INVALIDATE_ALL = 1;
+    mh_mmu_invalidate.INVALIDATE_TC  = 1;
+
+    device->ftbl.device_regwrite(device, reg_invalidate, *(unsigned int *) &mh_mmu_invalidate);
+#else
+    (void)device;
+    (void)reg_invalidate;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	// unreferenced formal parameter
+	(void) pid;
+#ifndef GSL_NO_MMU
+    device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+	device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+#else
+    (void)device;
+    (void)reg_ptbase;
+    (void)reg_varange;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _LINUX
+static void kgsl_g12_updatetimestamp(gsl_device_t *device)
+{
+	unsigned int count = 0;
+	device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &count);
+	count >>= 8;
+	count &= 255;
+	device->timestamp += count;	
+	kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &device->timestamp, 4, 0);
+}
+
+//----------------------------------------------------------------------------
+
+static void kgsl_g12_irqtask(struct work_struct *work)
+{
+	gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1];
+	kgsl_g12_updatetimestamp(device);
+	wake_up_interruptible_all(&device->timestamp_waitq);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE; 
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    // setup MH arbiter - MH offsets are considered to be dword based, therefore no down shift
+    device->ftbl.device_regwrite(device, ADDR_MH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_g12_mharb);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // enable irq
+    device->ftbl.device_regwrite(device, (ADDR_VGC_IRQENABLE >> 2), 0x3);
+
+#ifndef GSL_NO_MMU
+    // enable master interrupt for G12 MH
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_MH, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_MH);
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+#endif
+
+#ifdef IRQTHREAD_POLL
+    // Create event to trigger IRQ polling thread
+    device->irqthread_event = kos_event_create(0);
+#endif
+
+    // enable interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_G2D,  kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FIFO, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_G2D);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_FIFO);
+
+#ifndef _Z180
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FBC,  kgsl_g12_intrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+    // create thread for IRQ handling
+#if defined(__SYMBIAN32__)
+    kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#elif defined(_LINUX)
+	device->irq_workq = create_singlethread_workqueue("z1xx_workq");
+	INIT_WORK(&device->irq_work, kgsl_g12_irqtask);
+#else
+    #pragma warning(disable:4152)
+    device->irq_thread_handle = kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_close(gsl_device_t *device)
+{
+    int status = GSL_FAILURE; 
+
+    if (device->refcnt == 0)
+    {
+        // wait pending interrupts before shutting down G12 intr thread to
+        // empty irq counters. Otherwise there's a possibility to have them in
+        // registers next time systems starts up and this results in a hang.
+        status = device->ftbl.device_idle(device, 1000);
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+#ifndef _LINUX
+        kos_thread_destroy(device->irq_thread_handle);
+#else
+		destroy_workqueue(device->irq_workq);
+#endif
+
+        // shutdown command window
+        kgsl_cmdwindow_close(device);
+
+#ifndef GSL_NO_MMU
+        // shutdown mmu
+        kgsl_mmu_close(device);
+#endif
+        // disable interrupts
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_MH);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_G2D);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FIFO);
+#ifndef _Z180
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->ftbl.device_idle(device, GSL_TIMEOUT_NONE);
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+
+#if defined(__SYMBIAN32__)
+        while(device->irq_thread)
+        {
+            kos_sleep(20);
+        }
+#endif
+        drawctx_id = 0;
+
+        KOS_ASSERT(g_z1xx.numcontext == 0);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    //todo: hard reset core?
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    (void) flags;       // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // init command window
+    status = kgsl_cmdwindow_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    KOS_ASSERT(g_z1xx.numcontext == 0);
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_stop(gsl_device_t *device)
+{
+    int status;
+
+    KOS_ASSERT(device->refcnt == 0);
+
+    /* wait for device to idle before setting it's clock off */
+    status = device->ftbl.device_idle(device, 1000);
+    KOS_ASSERT(status == GSL_SUCCESS);
+
+    status = kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+    // unreferenced formal parameter
+    (void) sizebytes;
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id   = device->id;
+        devinfo->chip_id     = (gsl_chipid_t)device->chip_id;
+#ifndef GSL_NO_MMU
+        devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu);
+#endif
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+    // unreferenced formal parameters
+    (void) device;          
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+        }
+
+        status = GSL_SUCCESS;
+    }
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_g12_idle(gsl_device_t *device, unsigned int timeout)
+{
+	if ( device->flags & GSL_FLAGS_STARTED )
+	{
+		for ( ; ; )
+		{
+			gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0( device->id, GSL_TIMESTAMP_RETIRED );
+			gsl_timestamp_t ts_diff = retired - device->current_timestamp;
+			if ( ts_diff >= 0 || ts_diff < -GSL_TIMESTAMP_EPSILON )
+				break;
+			kos_sleep(10);
+		}
+	}
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int    
+kgsl_g12_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    // G12 MH register values can only be retrieved via dedicated read registers
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+#ifdef _Z180
+        device->ftbl.device_regwrite(device, (ADDR_VGC_MH_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_VGC_MH_READ_ADDR >> 2), value);
+#else
+        device->ftbl.device_regwrite(device, (ADDR_MMU_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_MMU_READ_DATA >> 2), value);
+#endif
+    }
+    else
+    {
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    // G12 MH registers can only be written via the command window
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+        kgsl_cmdwindow_write0(device->id, GSL_CMDWINDOW_MMU, offsetwords, value);
+    }
+    else
+    {
+        GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+#ifdef VG_HDK
+    (void)timeout;
+#endif
+
+#ifndef _Z180
+    if (intr_id == GSL_INTR_G12_G2D || intr_id == GSL_INTR_G12_FBC)
+#else
+        if (intr_id == GSL_INTR_G12_G2D)
+#endif //_Z180
+        {
+#ifndef VG_HDK
+            if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+            {
+                // wait until intr completion event is received and check that 
+                // the interrupt is still enabled. If event is received, but
+                // interrupt is not enabled any more, the driver is shutting 
+                // down and event structure is not valid anymore.
+#ifndef VG_HDK
+                if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS && kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+                {
+                    unsigned int cntrs;
+                    int          i;
+                    kgsl_device_active(device);
+#ifndef VG_HDK
+                    kos_event_reset(device->intr.evnt[intr_id]);
+                    device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &cntrs);
+#else
+                    device->ftbl.device_regread(device, (0x38 >> 2), &cntrs);
+#endif
+
+                    for (i = 0; i < GSL_G12_INTR_COUNT; i++) 
+                    {
+                        int intrcnt = cntrs >> ((8 * i)) & 255;
+
+                        // maximum allowed counter value is 254. if set to 255 then something has gone wrong
+                        if (intrcnt && (intrcnt < 0xFF))
+                        {
+                            device->intrcnt[i] += intrcnt;
+                        }
+                    }
+
+                    *count = device->intrcnt[intr_id - GSL_INTR_G12_MH];
+                    device->intrcnt[intr_id - GSL_INTR_G12_MH] = 0;
+                    status = GSL_SUCCESS;
+                }
+#ifndef VG_HDK
+                else
+                {
+                    status = GSL_FAILURE_TIMEOUT;
+                }
+#endif
+            }
+        }
+    else if(intr_id == GSL_INTR_FOOBAR)
+    {
+        if (kgsl_intr_isenabled(&device->intr, GSL_INTR_G12_G2D) == GSL_SUCCESS)
+        {
+            kos_event_signal(device->intr.evnt[GSL_INTR_G12_G2D]);
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+	                                              kgsl_cmdstream_check_timestamp(device->id, timestamp),
+												  msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+}
+
+int
+kgsl_g12_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_g12_init;
+    ftbl->device_close          = kgsl_g12_close;
+    ftbl->device_destroy        = kgsl_g12_destroy;
+    ftbl->device_start          = kgsl_g12_start;
+    ftbl->device_stop           = kgsl_g12_stop;
+    ftbl->device_getproperty    = kgsl_g12_getproperty;
+    ftbl->device_setproperty    = kgsl_g12_setproperty;
+    ftbl->device_idle           = kgsl_g12_idle;
+    ftbl->device_regread        = kgsl_g12_regread;
+    ftbl->device_regwrite       = kgsl_g12_regwrite;
+    ftbl->device_waitirq        = kgsl_g12_waitirq;
+	ftbl->device_waittimestamp  = kgsl_g12_waittimestamp;
+    ftbl->device_runpending     = NULL;
+    ftbl->device_addtimestamp   = kgsl_g12_addtimestamp;
+    ftbl->intr_isr              = kgsl_g12_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_g12_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_g12_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_g12_issueibcmds;
+    ftbl->context_create        = kgsl_g12_context_create;
+    ftbl->context_destroy       = kgsl_g12_context_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static void addmarker(gsl_z1xx_t* z1xx)
+{
+    KOS_ASSERT(z1xx);
+    {
+        unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+        /* todo: use symbolic values */
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = (0x8000|5);
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = 5;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    }
+}
+
+//----------------------------------------------------------------------------
+static void beginpacket(gsl_z1xx_t* z1xx, gpuaddr_t cmd, unsigned int nextcnt)
+{
+    unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+   
+    p[z1xx->offs++] = 0x7C000176;
+    p[z1xx->offs++] = 5;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = 0x7C000275;
+    p[z1xx->offs++] = cmd;
+    p[z1xx->offs++] = 0x1000|nextcnt;  // nextcount
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    unsigned int ofs      = PACKETSIZE_STATESTREAM*sizeof(unsigned int);
+    unsigned int cnt      = 5;
+    unsigned int cmd      = ibaddr; 
+    unsigned int nextbuf  = (g_z1xx.curr+1)%GSL_HAL_NUMCMDBUFFERS;
+    unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].gpuaddr;
+    unsigned int nextcnt  = 0x9000|5;
+    gsl_memdesc_t tmp     = {0};
+    gsl_timestamp_t processed_timestamp;
+
+    (void) flags;
+
+    // read what is the latest timestamp device have processed
+    GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+
+	/* wait for the next buffer's timestamp to occur */
+    while(processed_timestamp < g_z1xx.timestamp[nextbuf])
+    {
+#ifndef _LINUX	
+		kos_event_wait(device->timestamp_event, 1000);
+		kos_event_reset(device->timestamp_event);
+#else
+		kgsl_cmdstream_waittimestamp(device->id, g_z1xx.timestamp[nextbuf], 1000);
+#endif		
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+    }
+	
+    *timestamp = g_z1xx.timestamp[nextbuf] = device->current_timestamp + 1;
+
+    /* context switch */
+    if (drawctxt_index != (int)g_z1xx.prevctx)
+    {
+        cnt = PACKETSIZE_STATESTREAM;
+        ofs = 0; 
+    }
+    g_z1xx.prevctx = drawctxt_index;
+
+    g_z1xx.offs = 10;
+    beginpacket(&g_z1xx, cmd+ofs, cnt);
+
+    tmp.gpuaddr=ibaddr+(sizedwords*sizeof(unsigned int));
+    kgsl_sharedmem_write0(&tmp, 4, &nextaddr, 4, false);
+    kgsl_sharedmem_write0(&tmp, 8, &nextcnt,  4, false);
+
+    /* sync mem */ 
+    kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false);
+
+    g_z1xx.offs = 0;
+    g_z1xx.curr = nextbuf;
+
+    /* increment mark counter */
+    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags);
+    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+
+    /* increment consumed timestamp */
+    device->current_timestamp++;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    int status = 0;
+    int i;
+    int cmd;
+	gsl_flags_t gslflags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGNPAGE);
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) type;
+    //(void) drawctxt_id;
+    (void) flags;
+    
+    kgsl_device_active(device);
+    
+    if (g_z1xx.numcontext==0)
+    {
+         /* todo: move this to device create or start. Error checking!! */ 
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            status = kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_CMDBUFFERSIZE, &g_z1xx.cmdbufdesc[i]);
+            KOS_ASSERT(status == GSL_SUCCESS);          
+            g_z1xx.cmdbuf[i]=kos_malloc(GSL_HAL_CMDBUFFERSIZE);
+            KOS_ASSERT(g_z1xx.cmdbuf[i]);
+            kos_memset((void*)g_z1xx.cmdbuf[i], 0, GSL_HAL_CMDBUFFERSIZE);
+                  
+            g_z1xx.curr = i;
+            g_z1xx.offs = 0;
+            addmarker(&g_z1xx);
+            status = kgsl_sharedmem_write0(&g_z1xx.cmdbufdesc[i],0, g_z1xx.cmdbuf[i],  (512 + 13) * sizeof(unsigned int), false);
+            KOS_ASSERT(status == GSL_SUCCESS);
+        }
+        g_z1xx.curr = 0;
+        cmd = (int)(((VGV3_NEXTCMD_JUMP) & VGV3_NEXTCMD_NEXTCMD_FMASK)<< VGV3_NEXTCMD_NEXTCMD_FSHIFT);
+
+        /* set cmd stream buffer to hw */
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_MODE, 4);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTADDR, g_z1xx.cmdbufdesc[0].gpuaddr );
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTCMD,  cmd | 5);
+
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+        /* Edge buffer setup todo: move register setup to own function. 
+           This function can be then called, if power managemnet is used and clocks are turned off and then on.
+        */ 
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE0BUFSIZE, &g_z1xx.e0);
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE1BUFSIZE, &g_z1xx.e1);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e0, 0, 0, GSL_HAL_EDGE0BUFSIZE);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e1, 0, 0, GSL_HAL_EDGE1BUFSIZE);
+
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE0REG, g_z1xx.e0.gpuaddr);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE1REG, g_z1xx.e1.gpuaddr);
+#ifdef _Z180
+        kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE2BUFSIZE, &g_z1xx.e2);
+        kgsl_sharedmem_set0(&g_z1xx.e2, 0, 0, GSL_HAL_EDGE2BUFSIZE);
+        kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE2REG, g_z1xx.e2.gpuaddr);
+#endif  
+        KOS_ASSERT(status == GSL_SUCCESS);
+    } 
+
+    if(g_z1xx.numcontext < GSL_CONTEXT_MAX)
+    {
+        g_z1xx.numcontext++;
+        *drawctxt_id=g_z1xx.numcontext;
+        status = GSL_SUCCESS;
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) drawctxt_id;
+
+    g_z1xx.numcontext--;
+    if (g_z1xx.numcontext<0)
+    {
+        g_z1xx.numcontext=0;
+        return (GSL_FAILURE);
+    }
+
+    if (g_z1xx.numcontext==0)
+    {
+        int i;
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            kgsl_sharedmem_free0(&g_z1xx.cmdbufdesc[i], GSL_CALLER_PROCESSID_GET());
+            kos_free(g_z1xx.cmdbuf[i]);
+        }
+        kgsl_sharedmem_free0(&g_z1xx.e0, GSL_CALLER_PROCESSID_GET());
+        kgsl_sharedmem_free0(&g_z1xx.e1, GSL_CALLER_PROCESSID_GET());
+#ifdef _Z180
+        kgsl_sharedmem_free0(&g_z1xx.e2, GSL_CALLER_PROCESSID_GET());
+#endif
+        kos_memset(&g_z1xx,0,sizeof(gsl_z1xx_t));
+    }
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+#if !defined GSL_BLD_YAMATO && (!defined __SYMBIAN32__ || defined __WINSCW__)
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    (void)device_id;
+    (void)drawctxt_id;
+    (void)gmem_rect;
+    (void)shadow_x;
+    (void)shadow_y;
+    (void)shadow_buffer;
+    (void)buffer_id;
+    return (GSL_FAILURE);
+}
+#endif
+//----------------------------------------------------------------------------
+
+#ifndef _LINUX
+static void irq_thread(void)
+{
+	int error = 0;
+    unsigned int irq_count;
+    gsl_device_t* device  = &gsl_driver.device[GSL_DEVICE_G12-1];
+    gsl_timestamp_t timestamp;
+
+    while( !error )
+    {
+#ifdef IRQTHREAD_POLL
+        if(kos_event_wait(device->irqthread_event, GSL_IRQ_TIMEOUT)==GSL_SUCCESS)
+        {
+            kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT);
+#else
+
+        if( kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT) == GSL_SUCCESS )
+        {
+#endif
+            /* Read a timestamp value */
+#ifdef VG_HDK            
+            timestamp = device->timestamp;
+#else
+            GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&timestamp);
+#endif
+            /* Increase the timestamp value */
+            timestamp += irq_count;
+
+            KOS_ASSERT( timestamp <= device->current_timestamp );
+            /* Write the new timestamp value */
+#ifdef VG_HDK
+            device->timestamp = timestamp;
+#else
+            kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &timestamp, 4, false);
+#endif
+
+            /* Notify timestamp event */
+#ifndef _LINUX
+            kos_event_signal( device->timestamp_event );
+#else
+            wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+        }
+        else
+        {
+            /* Timeout */
+
+           
+            if(!(device->flags&GSL_FLAGS_INITIALIZED))
+            {
+                /* if device is closed -> thread exit */
+#if defined(__SYMBIAN32__)
+                device->irq_thread = 0;
+#endif
+                return;
+            }
+        }
+    }
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp)
+{    
+    device->current_timestamp++;
+    *timestamp = device->current_timestamp;
+ 
+    return (GSL_SUCCESS);
+}
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_intrmgr.c b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
new file mode 100644
index 000000000000..2c8b278dfe7a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
@@ -0,0 +1,305 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_INTRID_VALIDATE(id) (((id) < 0) || ((id) >= GSL_INTR_COUNT))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static const gsl_intrblock_reg_t * 
+kgsl_intr_id2block(gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i;
+
+    // interrupt id to hw block
+    for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+    {
+        block = &gsl_cfg_intrblock_reg[i];
+
+        if (block->first_id <= id && id <= block->last_id) 
+        {
+            return (block);
+        }
+    }
+
+    return (NULL);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id)
+{
+    const gsl_intrblock_reg_t  *block = &gsl_cfg_intrblock_reg[block_id];
+    gsl_intrid_t               id;
+    unsigned int               status;
+
+    // read the block's interrupt status bits
+    device->ftbl.device_regread(device, block->status_reg, &status);
+
+    // mask off any interrupts which are disabled
+    status &= device->intr.enabled[block->id];
+
+    // acknowledge the block's interrupts
+    device->ftbl.device_regwrite(device, block->clear_reg, status);
+
+    // loop through the block's masks, determine which interrupt bits are active, and call callback (or TODO queue DPC)
+    for (id = block->first_id; id <= block->last_id; id++) 
+    {
+        if (status & gsl_cfg_intr_mask[id])
+        {
+            device->intr.handler[id].callback(id, device->intr.handler[id].cookie);
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API void
+kgsl_intr_isr()
+{
+    gsl_deviceid_t  device_id;
+    gsl_device_t    *device;
+
+    // loop through the devices, and call device specific isr
+    for (device_id = (gsl_deviceid_t)(GSL_DEVICE_ANY + 1); device_id <= GSL_DEVICE_MAX; device_id++)
+    {
+        device = &gsl_driver.device[device_id-1];    // device_id is 1 based
+
+        if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_active(device);
+            device->ftbl.intr_isr(device);
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_init(gsl_device_t *device)
+{
+    if (device->ftbl.intr_isr == NULL)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        return (GSL_SUCCESS);
+    }
+
+    device->intr.device  = device;
+    device->intr.flags  |= GSL_FLAGS_INITIALIZED;
+
+    // os_interrupt_setcallback(YAMATO_INTR, kgsl_intr_isr);
+    // os_interrupt_enable(YAMATO_INTR);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_close(gsl_device_t *device)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i, id;
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        // check if there are any enabled interrupts lingering around
+        for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+        {
+            if (device->intr.enabled[i]) 
+            {
+                block = &gsl_cfg_intrblock_reg[i];
+
+                // loop through the block's masks, disable interrupts which active
+                for (id = block->first_id; id <= block->last_id; id++) 
+                {
+                    if (device->intr.enabled[i] & gsl_cfg_intr_mask[id])
+                    {
+                        kgsl_intr_disable(&device->intr, (gsl_intrid_t)id);
+                    }
+                }
+            }
+        }
+
+        kos_memset(&device->intr, 0, sizeof(gsl_intr_t));
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (mask && !(enabled & mask))
+    {
+        intr->evnt[id] = kos_event_create(0);
+
+        enabled                 |= mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id))
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (enabled & mask) 
+    {
+        enabled                 &= ~mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+
+        kos_event_signal(intr->evnt[id]); // wake up waiting threads before destroying the event
+        kos_event_destroy(intr->evnt[id]);
+        intr->evnt[id] = 0;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie)
+{
+    if (GSL_INTRID_VALIDATE(id) || callback == NULL) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback != NULL) 
+    {
+        if (intr->handler[id].callback == callback && intr->handler[id].cookie == cookie) 
+        {
+            return (GSL_FAILURE_ALREADYINITIALIZED);
+        } 
+        else 
+        {
+            return (GSL_FAILURE_NOMOREAVAILABLE);
+        }
+    }
+
+    intr->handler[id].callback = callback;
+    intr->handler[id].cookie   = cookie;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    kgsl_intr_disable(intr, id);
+
+    intr->handler[id].callback = NULL;
+    intr->handler[id].cookie   = NULL;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    int                        status = GSL_FAILURE;
+    const gsl_intrblock_reg_t  *block = kgsl_intr_id2block(id);
+
+    if (block != NULL)
+    {
+        // check if interrupt is enabled
+        if (intr->enabled[block->id] & gsl_cfg_intr_mask[id])
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_log.c b/drivers/mxc/amd-gpu/common/gsl_log.c
new file mode 100644
index 000000000000..79a14a5f4b21
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_log.c
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifdef GSL_LOG
+
+#define _CRT_SECURE_NO_WARNINGS
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <string.h>
+#include "gsl.h"
+
+#define KGSL_OUTPUT_TYPE_MEMBUF 0
+#define KGSL_OUTPUT_TYPE_STDOUT 1
+#define KGSL_OUTPUT_TYPE_FILE   2
+
+#define REG_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+#define INTRID_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+
+typedef struct log_output
+{
+    unsigned char       type;
+    unsigned int        flags;
+    oshandle_t         file;
+
+    struct log_output*  next;
+} log_output_t;
+
+static log_output_t* outputs = NULL;
+
+static oshandle_t   log_mutex = NULL;
+static char         buffer[256];
+static char         buffer2[256];
+static int          log_initialized = 0;
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_init()
+{
+    log_mutex = kos_mutex_create( "log_mutex" );
+
+    log_initialized = 1;
+    
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_close()
+{
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Go throught output list and free every node
+    while( outputs != NULL )
+    {
+        log_output_t* temp = outputs->next;
+        
+        switch( outputs->type )
+        {
+            case KGSL_OUTPUT_TYPE_FILE:
+                kos_fclose( outputs->file );
+            break;
+        }
+
+        kos_free( outputs );
+        outputs = temp;
+    }
+
+    kos_mutex_free( log_mutex );
+
+    log_initialized = 0;
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_stdout( unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_STDOUT;
+    output->flags = log_flags;
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_file( char* filename, unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_FILE;
+    output->flags = log_flags;
+    output->file = kos_fopen( filename, "w" );
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_flush_membuf( char* filename, int memBufId )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+//----------------------------------------------------------------------------
+
+int kgsl_log_write( unsigned int log_flags, char* format, ... )
+{
+    char            *c = format;
+    char            *b = buffer;
+    char            *p1, *p2;
+    log_output_t*   output;
+    va_list         arguments;
+
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Acquire mutex lock as we are using shared buffer for the string parsing
+    kos_mutex_lock( log_mutex );
+
+    // Add separator
+    *(b++) = '|'; *(b++) = ' ';
+
+    va_start( arguments, format );
+
+    while( 1 )
+    {
+        // Find the first occurence of %
+        p1 = strchr( c, '%' );
+        if( !p1 ) 
+        {
+            // No more % characters -> copy rest of the string
+            strcpy( b, c );
+
+            break;
+        }
+
+        // Find the second occurence of % and handle the string until that point
+        p2 = strchr( p1+1, '%' );
+
+        // If not found, just use the end of the buffer
+        if( !p2 ) p2 = strchr( p1+1, '\0' );
+
+        // Break the string to this point
+        kos_memcpy( buffer2, c, p2-c );
+        *(buffer2+(unsigned int)(p2-c)) = '\0';
+
+        switch( *(p1+1) )
+        {
+            // gsl_memdesc_t
+            case 'M':
+            {
+                gsl_memdesc_t val = va_arg( arguments, gsl_memdesc_t );
+                // Handle string before %M
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %M
+                b += sprintf( b, "[hostptr=0x%08x, gpuaddr=0x%08x]", val.hostptr, val.gpuaddr );
+                // Handle string after %M
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // GSL_SUCCESS/GSL_FAILURE
+            case 'B':
+            {
+                int val = va_arg( arguments, int );
+                // Handle string before %B
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %B
+                if( val == GSL_SUCCESS )
+                    b += sprintf( b, "%s", "GSL_SUCCESS" );
+                else
+                    b += sprintf( b, "%s", "GSL_FAILURE" );
+                // Handle string after %B
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // gsl_deviceid_t
+            case 'D':
+            {
+                gsl_deviceid_t val = va_arg( arguments, gsl_deviceid_t );
+                // Handle string before %D
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %D
+                switch( val )
+                {
+                    case GSL_DEVICE_ANY:
+                        b += sprintf( b, "%s", "GSL_DEVICE_ANY" );
+                    break;
+                    case GSL_DEVICE_YAMATO:
+                        b += sprintf( b, "%s", "GSL_DEVICE_YAMATO" );
+                    break;
+                    case GSL_DEVICE_G12:
+                        b += sprintf( b, "%s", "GSL_DEVICE_G12" );
+                    break;
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN DEVICE" );
+                    break;
+                }
+                // Handle string after %D
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+            
+            // gsl_intrid_t
+            case 'I':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                // Handle string before %I
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %I
+                switch( val )
+                {
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_SW_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_T0_PACKET_IN_IB );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_OPCODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RESERVED_BIT_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB2_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB1_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RING_BUFFER );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_DISPLAY_UPDATE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_GUI_IDLE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_PS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_VS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH );
+                    INTRID_OUTPUT( GSL_INTR_G12_G2D );
+                    INTRID_OUTPUT( GSL_INTR_G12_FIFO );
+#ifndef _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_FBC );
+#endif // _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_COUNT );
+                    INTRID_OUTPUT( GSL_INTR_FOOBAR );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN INTERRUPT ID" );
+                    break;
+                }
+                // Handle string after %I
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // Register offset
+            case 'R':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                
+                // Handle string before %R
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %R
+                switch( val )
+                {
+                    REG_OUTPUT( mmPA_CL_VPORT_XSCALE ); REG_OUTPUT( mmPA_CL_VPORT_XOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_YSCALE );
+                    REG_OUTPUT( mmPA_CL_VPORT_YOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_ZSCALE ); REG_OUTPUT( mmPA_CL_VPORT_ZOFFSET );
+                    REG_OUTPUT( mmPA_CL_VTE_CNTL ); REG_OUTPUT( mmPA_CL_CLIP_CNTL ); REG_OUTPUT( mmPA_CL_GB_VERT_CLIP_ADJ );
+                    REG_OUTPUT( mmPA_CL_GB_VERT_DISC_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_CLIP_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_DISC_ADJ );
+                    REG_OUTPUT( mmPA_CL_ENHANCE ); REG_OUTPUT( mmPA_SC_ENHANCE ); REG_OUTPUT( mmPA_SU_VTX_CNTL );
+                    REG_OUTPUT( mmPA_SU_POINT_SIZE ); REG_OUTPUT( mmPA_SU_POINT_MINMAX ); REG_OUTPUT( mmPA_SU_LINE_CNTL );
+                    REG_OUTPUT( mmPA_SU_FACE_DATA ); REG_OUTPUT( mmPA_SU_SC_MODE_CNTL ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_SCALE );
+                    REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_OFFSET ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_SCALE ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_OFFSET );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_SELECT );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER1_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_LOW );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER2_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_HI );
+                    REG_OUTPUT( mmPA_SC_WINDOW_OFFSET ); REG_OUTPUT( mmPA_SC_AA_CONFIG ); REG_OUTPUT( mmPA_SC_AA_MASK );
+                    REG_OUTPUT( mmPA_SC_LINE_STIPPLE ); REG_OUTPUT( mmPA_SC_LINE_CNTL ); REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_TL );
+                    REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_BR ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_TL ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_BR );
+                    REG_OUTPUT( mmPA_SC_VIZ_QUERY ); REG_OUTPUT( mmPA_SC_VIZ_QUERY_STATUS ); REG_OUTPUT( mmPA_SC_LINE_STIPPLE_STATE );
+                    REG_OUTPUT( mmPA_SC_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_CL_CNTL_STATUS ); REG_OUTPUT( mmPA_SU_CNTL_STATUS ); REG_OUTPUT( mmPA_SC_CNTL_STATUS );
+                    REG_OUTPUT( mmPA_SU_DEBUG_CNTL ); REG_OUTPUT( mmPA_SU_DEBUG_DATA ); REG_OUTPUT( mmPA_SC_DEBUG_CNTL );
+                    REG_OUTPUT( mmPA_SC_DEBUG_DATA ); REG_OUTPUT( mmGFX_COPY_STATE ); REG_OUTPUT( mmVGT_DRAW_INITIATOR );
+                    REG_OUTPUT( mmVGT_EVENT_INITIATOR ); REG_OUTPUT( mmVGT_DMA_BASE ); REG_OUTPUT( mmVGT_DMA_SIZE );
+                    REG_OUTPUT( mmVGT_BIN_BASE ); REG_OUTPUT( mmVGT_BIN_SIZE ); REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MIN );
+                    REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MAX ); REG_OUTPUT( mmVGT_IMMED_DATA ); REG_OUTPUT( mmVGT_MAX_VTX_INDX );
+                    REG_OUTPUT( mmVGT_MIN_VTX_INDX ); REG_OUTPUT( mmVGT_INDX_OFFSET ); REG_OUTPUT( mmVGT_VERTEX_REUSE_BLOCK_CNTL );
+                    REG_OUTPUT( mmVGT_OUT_DEALLOC_CNTL ); REG_OUTPUT( mmVGT_MULTI_PRIM_IB_RESET_INDX ); REG_OUTPUT( mmVGT_ENHANCE );
+                    REG_OUTPUT( mmVGT_VTX_VECT_EJECT_REG ); REG_OUTPUT( mmVGT_LAST_COPY_STATE ); REG_OUTPUT( mmVGT_DEBUG_CNTL );
+                    REG_OUTPUT( mmVGT_DEBUG_DATA ); REG_OUTPUT( mmVGT_CNTL_STATUS ); REG_OUTPUT( mmVGT_CRC_SQ_DATA );
+                    REG_OUTPUT( mmVGT_CRC_SQ_CTRL ); REG_OUTPUT( mmVGT_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER1_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER2_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER3_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER0_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER1_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER3_HI ); REG_OUTPUT( mmTC_CNTL_STATUS ); REG_OUTPUT( mmTCR_CHICKEN );
+                    REG_OUTPUT( mmTCF_CHICKEN ); REG_OUTPUT( mmTCM_CHICKEN ); REG_OUTPUT( mmTCR_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTCR_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCR_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCR_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTP_TC_CLKGATE_CNTL );
+                    REG_OUTPUT( mmTPC_CNTL_STATUS ); REG_OUTPUT( mmTPC_DEBUG0 ); REG_OUTPUT( mmTPC_DEBUG1 );
+                    REG_OUTPUT( mmTPC_CHICKEN ); REG_OUTPUT( mmTP0_CNTL_STATUS ); REG_OUTPUT( mmTP0_DEBUG );
+                    REG_OUTPUT( mmTP0_CHICKEN ); REG_OUTPUT( mmTP0_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTP0_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCM_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCM_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER1_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER4_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER6_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER7_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER9_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER10_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER3_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER4_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER6_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER7_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER9_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER10_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER3_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER4_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER6_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER7_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER9_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER10_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_LOW ); REG_OUTPUT( mmTCF_DEBUG ); REG_OUTPUT( mmTCA_FIFO_DEBUG );
+                    REG_OUTPUT( mmTCA_PROBE_DEBUG ); REG_OUTPUT( mmTCA_TPC_DEBUG ); REG_OUTPUT( mmTCB_CORE_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG0_DEBUG ); REG_OUTPUT( mmTCB_TAG1_DEBUG ); REG_OUTPUT( mmTCB_TAG2_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG3_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_WALKER_DEBUG );
+                    REG_OUTPUT( mmTCB_FETCH_GEN_PIPE0_DEBUG ); REG_OUTPUT( mmTCD_INPUT0_DEBUG ); REG_OUTPUT( mmTCD_DEGAMMA_DEBUG );
+                    REG_OUTPUT( mmTCD_DXTMUX_SCTARB_DEBUG ); REG_OUTPUT( mmTCD_DXTC_ARB_DEBUG ); REG_OUTPUT( mmTCD_STALLS_DEBUG );
+                    REG_OUTPUT( mmTCO_STALLS_DEBUG ); REG_OUTPUT( mmTCO_QUAD0_DEBUG0 ); REG_OUTPUT( mmTCO_QUAD0_DEBUG1 );
+                    REG_OUTPUT( mmSQ_GPR_MANAGEMENT ); REG_OUTPUT( mmSQ_FLOW_CONTROL ); REG_OUTPUT( mmSQ_INST_STORE_MANAGMENT );
+                    REG_OUTPUT( mmSQ_RESOURCE_MANAGMENT ); REG_OUTPUT( mmSQ_EO_RT ); REG_OUTPUT( mmSQ_DEBUG_MISC );
+                    REG_OUTPUT( mmSQ_ACTIVITY_METER_CNTL ); REG_OUTPUT( mmSQ_ACTIVITY_METER_STATUS ); REG_OUTPUT( mmSQ_INPUT_ARB_PRIORITY );
+                    REG_OUTPUT( mmSQ_THREAD_ARB_PRIORITY ); REG_OUTPUT( mmSQ_VS_WATCHDOG_TIMER ); REG_OUTPUT( mmSQ_PS_WATCHDOG_TIMER );
+                    REG_OUTPUT( mmSQ_INT_CNTL ); REG_OUTPUT( mmSQ_INT_STATUS ); REG_OUTPUT( mmSQ_INT_ACK );
+                    REG_OUTPUT( mmSQ_DEBUG_INPUT_FSM ); REG_OUTPUT( mmSQ_DEBUG_CONST_MGR_FSM ); REG_OUTPUT( mmSQ_DEBUG_TP_FSM );
+                    REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_0 ); REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_1 ); REG_OUTPUT( mmSQ_DEBUG_EXP_ALLOC );
+                    REG_OUTPUT( mmSQ_DEBUG_PTR_BUFF ); REG_OUTPUT( mmSQ_DEBUG_GPR_VTX ); REG_OUTPUT( mmSQ_DEBUG_GPR_PIX );
+                    REG_OUTPUT( mmSQ_DEBUG_TB_STATUS_SEL ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_0 ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_1 );
+                    REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATUS_REG ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_0 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_1 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_2 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_3 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER3_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER2_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER3_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER3_HI ); REG_OUTPUT( mmSX_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSX_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSX_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_ALU_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_2 ); REG_OUTPUT( mmSQ_CONSTANT_0 );
+                    REG_OUTPUT( mmSQ_CONSTANT_1 ); REG_OUTPUT( mmSQ_CONSTANT_2 ); REG_OUTPUT( mmSQ_CONSTANT_3 );
+                    REG_OUTPUT( mmSQ_FETCH_0 ); REG_OUTPUT( mmSQ_FETCH_1 ); REG_OUTPUT( mmSQ_FETCH_2 );
+                    REG_OUTPUT( mmSQ_FETCH_3 ); REG_OUTPUT( mmSQ_FETCH_4 ); REG_OUTPUT( mmSQ_FETCH_5 );
+                    REG_OUTPUT( mmSQ_CONSTANT_VFETCH_0 ); REG_OUTPUT( mmSQ_CONSTANT_VFETCH_1 ); REG_OUTPUT( mmSQ_CONSTANT_T2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_T3 ); REG_OUTPUT( mmSQ_CF_BOOLEANS ); REG_OUTPUT( mmSQ_CF_LOOP );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_0 ); REG_OUTPUT( mmSQ_CONSTANT_RT_1 ); REG_OUTPUT( mmSQ_CONSTANT_RT_2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_0 ); REG_OUTPUT( mmSQ_FETCH_RT_1 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_2 ); REG_OUTPUT( mmSQ_FETCH_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_4 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_5 ); REG_OUTPUT( mmSQ_CF_RT_BOOLEANS ); REG_OUTPUT( mmSQ_CF_RT_LOOP );
+                    REG_OUTPUT( mmSQ_VS_PROGRAM ); REG_OUTPUT( mmSQ_PS_PROGRAM ); REG_OUTPUT( mmSQ_CF_PROGRAM_SIZE );
+                    REG_OUTPUT( mmSQ_INTERPOLATOR_CNTL ); REG_OUTPUT( mmSQ_PROGRAM_CNTL ); REG_OUTPUT( mmSQ_WRAPPING_0 );
+                    REG_OUTPUT( mmSQ_WRAPPING_1 ); REG_OUTPUT( mmSQ_VS_CONST ); REG_OUTPUT( mmSQ_PS_CONST );
+                    REG_OUTPUT( mmSQ_CONTEXT_MISC ); REG_OUTPUT( mmSQ_CF_RD_BASE ); REG_OUTPUT( mmSQ_DEBUG_MISC_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_MISC_1 ); REG_OUTPUT( mmMH_ARBITER_CONFIG ); REG_OUTPUT( mmMH_CLNT_AXI_ID_REUSE );
+                    REG_OUTPUT( mmMH_INTERRUPT_MASK ); REG_OUTPUT( mmMH_INTERRUPT_STATUS ); REG_OUTPUT( mmMH_INTERRUPT_CLEAR );
+                    REG_OUTPUT( mmMH_AXI_ERROR ); REG_OUTPUT( mmMH_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmMH_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmMH_PERFCOUNTER0_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER1_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmMH_PERFCOUNTER1_LOW ); REG_OUTPUT( mmMH_PERFCOUNTER0_HI ); REG_OUTPUT( mmMH_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmMH_DEBUG_CTRL ); REG_OUTPUT( mmMH_DEBUG_DATA ); REG_OUTPUT( mmMH_AXI_HALT_CONTROL );
+                    REG_OUTPUT( mmMH_MMU_CONFIG ); REG_OUTPUT( mmMH_MMU_VA_RANGE ); REG_OUTPUT( mmMH_MMU_PT_BASE );
+                    REG_OUTPUT( mmMH_MMU_PAGE_FAULT ); REG_OUTPUT( mmMH_MMU_TRAN_ERROR ); REG_OUTPUT( mmMH_MMU_INVALIDATE );
+                    REG_OUTPUT( mmMH_MMU_MPU_BASE ); REG_OUTPUT( mmMH_MMU_MPU_END ); REG_OUTPUT( mmWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_ISYNC_CNTL ); REG_OUTPUT( mmRBBM_STATUS ); REG_OUTPUT( mmRBBM_DSPLY );
+                    REG_OUTPUT( mmRBBM_RENDER_LATEST ); REG_OUTPUT( mmRBBM_RTL_RELEASE ); REG_OUTPUT( mmRBBM_PATCH_RELEASE );
+                    REG_OUTPUT( mmRBBM_AUXILIARY_CONFIG ); REG_OUTPUT( mmRBBM_PERIPHID0 ); REG_OUTPUT( mmRBBM_PERIPHID1 );
+                    REG_OUTPUT( mmRBBM_PERIPHID2 ); REG_OUTPUT( mmRBBM_PERIPHID3 ); REG_OUTPUT( mmRBBM_CNTL );
+                    REG_OUTPUT( mmRBBM_SKEW_CNTL ); REG_OUTPUT( mmRBBM_SOFT_RESET ); REG_OUTPUT( mmRBBM_PM_OVERRIDE1 );
+                    REG_OUTPUT( mmRBBM_PM_OVERRIDE2 ); REG_OUTPUT( mmGC_SYS_IDLE ); REG_OUTPUT( mmNQWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_DEBUG_OUT ); REG_OUTPUT( mmRBBM_DEBUG_CNTL ); REG_OUTPUT( mmRBBM_DEBUG );
+                    REG_OUTPUT( mmRBBM_READ_ERROR ); REG_OUTPUT( mmRBBM_WAIT_IDLE_CLOCKS ); REG_OUTPUT( mmRBBM_INT_CNTL );
+                    REG_OUTPUT( mmRBBM_INT_STATUS ); REG_OUTPUT( mmRBBM_INT_ACK ); REG_OUTPUT( mmMASTER_INT_SIGNAL );
+                    REG_OUTPUT( mmRBBM_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_LO ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmCP_RB_BASE ); REG_OUTPUT( mmCP_RB_CNTL ); REG_OUTPUT( mmCP_RB_RPTR_ADDR );
+                    REG_OUTPUT( mmCP_RB_RPTR ); REG_OUTPUT( mmCP_RB_RPTR_WR ); REG_OUTPUT( mmCP_RB_WPTR );
+                    REG_OUTPUT( mmCP_RB_WPTR_DELAY ); REG_OUTPUT( mmCP_RB_WPTR_BASE ); REG_OUTPUT( mmCP_IB1_BASE );
+                    REG_OUTPUT( mmCP_IB1_BUFSZ ); REG_OUTPUT( mmCP_IB2_BASE ); REG_OUTPUT( mmCP_IB2_BUFSZ );
+                    REG_OUTPUT( mmCP_ST_BASE ); REG_OUTPUT( mmCP_ST_BUFSZ ); REG_OUTPUT( mmCP_QUEUE_THRESHOLDS );
+                    REG_OUTPUT( mmCP_MEQ_THRESHOLDS ); REG_OUTPUT( mmCP_CSQ_AVAIL ); REG_OUTPUT( mmCP_STQ_AVAIL );
+                    REG_OUTPUT( mmCP_MEQ_AVAIL ); REG_OUTPUT( mmCP_CSQ_RB_STAT ); REG_OUTPUT( mmCP_CSQ_IB1_STAT );
+                    REG_OUTPUT( mmCP_CSQ_IB2_STAT ); REG_OUTPUT( mmCP_NON_PREFETCH_CNTRS ); REG_OUTPUT( mmCP_STQ_ST_STAT );
+                    REG_OUTPUT( mmCP_MEQ_STAT ); REG_OUTPUT( mmCP_MIU_TAG_STAT ); REG_OUTPUT( mmCP_CMD_INDEX );
+                    REG_OUTPUT( mmCP_CMD_DATA ); REG_OUTPUT( mmCP_ME_CNTL ); REG_OUTPUT( mmCP_ME_STATUS );
+                    REG_OUTPUT( mmCP_ME_RAM_WADDR ); REG_OUTPUT( mmCP_ME_RAM_RADDR ); REG_OUTPUT( mmCP_ME_RAM_DATA );
+                    REG_OUTPUT( mmCP_ME_RDADDR ); REG_OUTPUT( mmCP_DEBUG ); REG_OUTPUT( mmSCRATCH_REG0 );
+                    REG_OUTPUT( mmSCRATCH_REG1 ); REG_OUTPUT( mmSCRATCH_REG2 ); REG_OUTPUT( mmSCRATCH_REG3 );
+                    REG_OUTPUT( mmSCRATCH_REG4 ); REG_OUTPUT( mmSCRATCH_REG5 ); REG_OUTPUT( mmSCRATCH_REG6 );
+                    REG_OUTPUT( mmSCRATCH_REG7 );
+                    REG_OUTPUT( mmSCRATCH_UMSK ); REG_OUTPUT( mmSCRATCH_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR_SWM );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_DATA_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_SRC ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR );
+                    REG_OUTPUT( mmCP_ME_PS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_DATA_SWM );
+                    REG_OUTPUT( mmCP_ME_CF_EVENT_SRC ); REG_OUTPUT( mmCP_ME_CF_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_CF_EVENT_DATA );
+                    REG_OUTPUT( mmCP_ME_NRT_ADDR ); REG_OUTPUT( mmCP_ME_NRT_DATA ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_ADDR ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_DATA ); REG_OUTPUT( mmCP_INT_CNTL );
+                    REG_OUTPUT( mmCP_INT_STATUS ); REG_OUTPUT( mmCP_INT_ACK ); REG_OUTPUT( mmCP_PFP_UCODE_ADDR );
+                    REG_OUTPUT( mmCP_PFP_UCODE_DATA ); REG_OUTPUT( mmCP_PERFMON_CNTL ); REG_OUTPUT( mmCP_PERFCOUNTER_SELECT );
+                    REG_OUTPUT( mmCP_PERFCOUNTER_LO ); REG_OUTPUT( mmCP_PERFCOUNTER_HI ); REG_OUTPUT( mmCP_BIN_MASK_LO );
+                    REG_OUTPUT( mmCP_BIN_MASK_HI ); REG_OUTPUT( mmCP_BIN_SELECT_LO ); REG_OUTPUT( mmCP_BIN_SELECT_HI );
+                    REG_OUTPUT( mmCP_NV_FLAGS_0 ); REG_OUTPUT( mmCP_NV_FLAGS_1 ); REG_OUTPUT( mmCP_NV_FLAGS_2 );
+                    REG_OUTPUT( mmCP_NV_FLAGS_3 ); REG_OUTPUT( mmCP_STATE_DEBUG_INDEX ); REG_OUTPUT( mmCP_STATE_DEBUG_DATA );
+                    REG_OUTPUT( mmCP_PROG_COUNTER ); REG_OUTPUT( mmCP_STAT ); REG_OUTPUT( mmBIOS_0_SCRATCH );
+                    REG_OUTPUT( mmBIOS_1_SCRATCH ); REG_OUTPUT( mmBIOS_2_SCRATCH ); REG_OUTPUT( mmBIOS_3_SCRATCH );
+                    REG_OUTPUT( mmBIOS_4_SCRATCH ); REG_OUTPUT( mmBIOS_5_SCRATCH ); REG_OUTPUT( mmBIOS_6_SCRATCH );
+                    REG_OUTPUT( mmBIOS_7_SCRATCH ); REG_OUTPUT( mmBIOS_8_SCRATCH ); REG_OUTPUT( mmBIOS_9_SCRATCH );
+                    REG_OUTPUT( mmBIOS_10_SCRATCH ); REG_OUTPUT( mmBIOS_11_SCRATCH ); REG_OUTPUT( mmBIOS_12_SCRATCH );
+                    REG_OUTPUT( mmBIOS_13_SCRATCH ); REG_OUTPUT( mmBIOS_14_SCRATCH ); REG_OUTPUT( mmBIOS_15_SCRATCH );
+                    REG_OUTPUT( mmCOHER_SIZE_PM4 ); REG_OUTPUT( mmCOHER_BASE_PM4 ); REG_OUTPUT( mmCOHER_STATUS_PM4 );
+                    REG_OUTPUT( mmCOHER_SIZE_HOST ); REG_OUTPUT( mmCOHER_BASE_HOST ); REG_OUTPUT( mmCOHER_STATUS_HOST );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_0 ); REG_OUTPUT( mmCOHER_DEST_BASE_1 ); REG_OUTPUT( mmCOHER_DEST_BASE_2 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_3 ); REG_OUTPUT( mmCOHER_DEST_BASE_4 ); REG_OUTPUT( mmCOHER_DEST_BASE_5 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_6 ); REG_OUTPUT( mmCOHER_DEST_BASE_7 ); REG_OUTPUT( mmRB_SURFACE_INFO );
+                    REG_OUTPUT( mmRB_COLOR_INFO ); REG_OUTPUT( mmRB_DEPTH_INFO ); REG_OUTPUT( mmRB_STENCILREFMASK );
+                    REG_OUTPUT( mmRB_ALPHA_REF ); REG_OUTPUT( mmRB_COLOR_MASK ); REG_OUTPUT( mmRB_BLEND_RED );
+                    REG_OUTPUT( mmRB_BLEND_GREEN ); REG_OUTPUT( mmRB_BLEND_BLUE ); REG_OUTPUT( mmRB_BLEND_ALPHA );
+                    REG_OUTPUT( mmRB_FOG_COLOR ); REG_OUTPUT( mmRB_STENCILREFMASK_BF ); REG_OUTPUT( mmRB_DEPTHCONTROL );
+                    REG_OUTPUT( mmRB_BLENDCONTROL ); REG_OUTPUT( mmRB_COLORCONTROL ); REG_OUTPUT( mmRB_MODECONTROL );
+                    REG_OUTPUT( mmRB_COLOR_DEST_MASK ); REG_OUTPUT( mmRB_COPY_CONTROL ); REG_OUTPUT( mmRB_COPY_DEST_BASE );
+                    REG_OUTPUT( mmRB_COPY_DEST_PITCH ); REG_OUTPUT( mmRB_COPY_DEST_INFO ); REG_OUTPUT( mmRB_COPY_DEST_PIXEL_OFFSET );
+                    REG_OUTPUT( mmRB_DEPTH_CLEAR ); REG_OUTPUT( mmRB_SAMPLE_COUNT_CTL ); REG_OUTPUT( mmRB_SAMPLE_COUNT_ADDR );
+                    REG_OUTPUT( mmRB_BC_CONTROL ); REG_OUTPUT( mmRB_EDRAM_INFO ); REG_OUTPUT( mmRB_CRC_RD_PORT );
+                    REG_OUTPUT( mmRB_CRC_CONTROL ); REG_OUTPUT( mmRB_CRC_MASK ); REG_OUTPUT( mmRB_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmRB_PERFCOUNTER0_LOW ); REG_OUTPUT( mmRB_PERFCOUNTER0_HI ); REG_OUTPUT( mmRB_TOTAL_SAMPLES );
+                    REG_OUTPUT( mmRB_ZPASS_SAMPLES ); REG_OUTPUT( mmRB_ZFAIL_SAMPLES ); REG_OUTPUT( mmRB_SFAIL_SAMPLES );
+                    REG_OUTPUT( mmRB_DEBUG_0 ); REG_OUTPUT( mmRB_DEBUG_1 ); REG_OUTPUT( mmRB_DEBUG_2 );
+                    REG_OUTPUT( mmRB_DEBUG_3 ); REG_OUTPUT( mmRB_DEBUG_4 ); REG_OUTPUT( mmRB_FLAG_CONTROL );
+                    REG_OUTPUT( mmRB_BC_SPARES ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_ENUMS ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_MOREENUMS );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN REGISTER OFFSET" );
+                    break;
+                }
+                // Handle string after %R
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+
+            default:
+            {
+                int val = va_arg( arguments, int );
+                // Standard format. Use vsprintf.
+                b += sprintf( b, buffer2, val );
+            }
+            break;
+        }
+        
+
+        c = p2;
+    }
+
+    // Add this string to all outputs
+    output = outputs;
+
+    while( output != NULL )
+    {
+        // Filter according to the flags
+        if( ( output->flags & log_flags ) == log_flags )
+        {
+            // Passed the filter. Now commit this message.
+            switch( output->type )
+            {
+                case KGSL_OUTPUT_TYPE_MEMBUF:
+                    // TODO
+                break;
+
+                case KGSL_OUTPUT_TYPE_STDOUT:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        printf( "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        printf( "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        printf( "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    printf( buffer );
+                break;
+                
+                case KGSL_OUTPUT_TYPE_FILE:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        kos_fprintf( output->file, "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        kos_fprintf( output->file, "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        kos_fprintf( output->file, "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    kos_fprintf( output->file, buffer );
+                break;
+            }
+        }
+            
+        output = output->next;
+    }
+
+    va_end( arguments );
+
+    kos_mutex_unlock( log_mutex );
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
new file mode 100644
index 000000000000..75f250ae59b1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
@@ -0,0 +1,949 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENAPRIV_SIGNATURE_MASK         0x0000FFFF
+#define GSL_MEMARENAPRIV_APERTUREID_MASK        0xF0000000
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK    0x0F000000
+
+#define GSL_MEMARENAPRIV_SIGNATURE_SHIFT        0
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT   24
+#define GSL_MEMARENAPRIV_APERTUREID_SHIFT       28
+
+#define GSL_MEMARENA_INSTANCE_SIGNATURE         0x0000CAFE
+
+#ifdef GSL_STATS_MEM
+#define GSL_MEMARENA_STATS(x)   x
+#else
+#define GSL_MEMARENA_STATS(x)
+#endif // GSL_STATS_MEM
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_LOCK()                 kos_mutex_lock(memarena->mutex)
+#define GSL_MEMARENA_UNLOCK()               kos_mutex_unlock(memarena->mutex)
+
+#define GSL_MEMARENA_SET_SIGNATURE          (memarena->priv |= ((GSL_MEMARENA_INSTANCE_SIGNATURE << GSL_MEMARENAPRIV_SIGNATURE_SHIFT) & GSL_MEMARENAPRIV_SIGNATURE_MASK))
+#define GSL_MEMARENA_SET_MMU_VIRTUALIZED    (memarena->priv |= ((mmu_virtualized << GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK))
+#define GSL_MEMARENA_SET_ID                 (memarena->priv |= ((aperture_id << GSL_MEMARENAPRIV_APERTUREID_SHIFT) & GSL_MEMARENAPRIV_APERTUREID_MASK))
+
+#define GSL_MEMARENA_GET_SIGNATURE          ((memarena->priv & GSL_MEMARENAPRIV_SIGNATURE_MASK)   >> GSL_MEMARENAPRIV_SIGNATURE_SHIFT)
+#define GSL_MEMARENA_IS_MMU_VIRTUALIZED     ((memarena->priv & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK) >> GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT)
+#define GSL_MEMARENA_GET_ID                 ((memarena->priv & GSL_MEMARENAPRIV_APERTUREID_MASK)  >> GSL_MEMARENAPRIV_APERTUREID_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  validate
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_VALIDATE(memarena)                                 \
+    KOS_ASSERT(memarena);                                               \
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)  \
+    {                                                                   \
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,   \
+                        "ERROR: Memarena validation failed.\n" );       \
+        return (GSL_FAILURE);                                           \
+    }
+
+//////////////////////////////////////////////////////////////////////////////
+//  block alignment shift count
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignmentshift(gsl_flags_t flags)
+{
+    int alignshift = ((flags & GSL_MEMFLAGS_ALIGN_MASK) >> GSL_MEMFLAGS_ALIGN_SHIFT);
+    if (alignshift == 0)
+        alignshift = 5; //  32 bytes is the minimum alignment boundary
+    return (alignshift);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  address alignment
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignaddr(unsigned int address, int shift)
+{
+    //
+    //  the value of the returned address is guaranteed to be an even multiple
+    //  of the block alignment shift specified.
+    //
+    unsigned int alignedbaseaddr = ((address) >> shift) << shift;
+    if (alignedbaseaddr < address)
+    {
+        alignedbaseaddr += (1 << shift);
+    }
+    return (alignedbaseaddr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                         memory management API
+//////////////////////////////////////////////////////////////////////////////
+
+OSINLINE memblk_t*
+kgsl_memarena_getmemblknode(gsl_memarena_t *memarena)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t  *nodepool    = memarena->nodepool;
+    memblk_t        *memblk      = NULL;
+    int             allocnewpool = 1;
+    int             i;
+
+    if (nodepool)
+    {
+        // walk through list of existing pools
+        for ( ; ; )
+        {
+            // if there is a pool with a free memblk node
+            if (nodepool->priv != (1 << GSL_MEMARENA_NODE_POOL_MAX)-1)
+            {
+                // get index of the first free memblk node
+                for (i = 0; i < GSL_MEMARENA_NODE_POOL_MAX; i++)
+                {
+                    if (((nodepool->priv >> i) & 0x1) == 0)
+                    {
+                        break;
+                    }
+                }
+
+                // mark memblk node as used
+                nodepool->priv |= 1 << i;
+
+                memblk                = &nodepool->memblk[i];
+                memblk->nodepoolindex = i;
+                memblk->blkaddr       = 0;
+                memblk->blksize       = 0;
+
+                allocnewpool = 0;
+
+                break;
+            }
+            else        
+            {
+                nodepool = nodepool->next;
+
+                if (nodepool == memarena->nodepool)
+                {
+                    // no free memblk node found
+                    break;
+                }
+            }
+        }
+    }
+
+    // if no existing pool has a free memblk node
+    if (allocnewpool)
+    {
+        // alloc new pool of memblk nodes
+        nodepool = ((gsl_nodepool_t *)kos_malloc(sizeof(gsl_nodepool_t)));
+        if (nodepool)
+        {
+            kos_memset(nodepool, 0, sizeof(gsl_nodepool_t));
+
+            if (memarena->nodepool)
+            {
+                nodepool->next                 = memarena->nodepool->next;
+                nodepool->prev                 = memarena->nodepool;
+                memarena->nodepool->next->prev = nodepool;
+                memarena->nodepool->next       = nodepool;
+            }
+            else
+            {
+                nodepool->next = nodepool;
+                nodepool->prev = nodepool;
+            }
+
+            // reposition pool head
+            memarena->nodepool = nodepool;
+
+            // mark memblk node as used
+            nodepool->priv       |= 0x1;
+
+            memblk                = &nodepool->memblk[0];
+            memblk->nodepoolindex = 0;
+        }
+    }
+
+    KOS_ASSERT(memblk);
+
+    return (memblk);
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    return ((memblk_t *)kos_malloc(sizeof(memblk_t)));
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_memarena_releasememblknode(gsl_memarena_t *memarena, memblk_t *memblk)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t *nodepool = memarena->nodepool;
+
+    KOS_ASSERT(memblk);
+    KOS_ASSERT(nodepool);
+
+    // locate pool to which this memblk node belongs
+    while (((unsigned int) memblk) < ((unsigned int) nodepool) || 
+           ((unsigned int) memblk) > ((unsigned int) nodepool) + sizeof(gsl_nodepool_t))
+    {
+        nodepool = nodepool->prev;
+
+        KOS_ASSERT(nodepool != memarena->nodepool);
+    }
+
+    // mark memblk node as unused
+    nodepool->priv &= ~(1 << memblk->nodepoolindex);
+
+    // free pool when all its memblk nodes are unused
+    if (nodepool->priv == 0)
+    {
+        if (nodepool != nodepool->prev)
+        {
+            // reposition pool head
+            if (nodepool == memarena->nodepool)
+            {
+                memarena->nodepool = nodepool->prev;
+            }
+
+            nodepool->prev->next = nodepool->next;
+            nodepool->next->prev = nodepool->prev;
+        }
+        else
+        {
+            memarena->nodepool = NULL;
+        }
+
+        kos_free((void *)nodepool);
+    }
+    else
+    {
+        // leave pool head in last pool a memblk node was released
+        memarena->nodepool = nodepool;
+    }
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    kos_free((void *)memblk);
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+gsl_memarena_t*
+kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes)
+{
+    static int      count = 0;
+    char            name[100], id_str[2];
+    int             len;
+    gsl_memarena_t  *memarena;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_memarena_t* kgsl_memarena_create(int aperture_id=%d, gpuaddr_t gpubaseaddr=0x%08x, int sizebytes=%d)\n", aperture_id, gpubaseaddr, sizebytes );
+
+    memarena = (gsl_memarena_t *)kos_malloc(sizeof(gsl_memarena_t));
+
+    if (!memarena) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,
+                        "ERROR: Memarena allocation failed.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "<-- kgsl_memarena_create. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    kos_memset(memarena, 0, sizeof(gsl_memarena_t));
+
+    GSL_MEMARENA_SET_SIGNATURE;
+    GSL_MEMARENA_SET_MMU_VIRTUALIZED;
+    GSL_MEMARENA_SET_ID;
+
+    // define unique mutex for each memory arena instance
+    id_str[0] = (char) (count + '0');
+    id_str[1] = '\0';
+    kos_strcpy(name, "GSL_memory_arena_");
+    len = kos_strlen(name);
+    kos_strcpy(&name[len], id_str);
+
+    memarena->mutex = kos_mutex_create(name);
+
+    // set up the memory arena
+    memarena->hostbaseaddr = hostbaseaddr;
+    memarena->gpubaseaddr  = gpubaseaddr;
+    memarena->sizebytes    = sizebytes;
+
+    // allocate a memory block in free list which represents all memory in arena
+    memarena->freelist.head          = kgsl_memarena_getmemblknode(memarena);
+    memarena->freelist.head->blkaddr = 0;
+    memarena->freelist.head->blksize = memarena->sizebytes;
+    memarena->freelist.head->next    = memarena->freelist.head;
+    memarena->freelist.head->prev    = memarena->freelist.head;
+    memarena->freelist.allocrover    = memarena->freelist.head;
+    memarena->freelist.freerover     = memarena->freelist.head;
+
+    count++;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_create. Return value: 0x%08x\n", memarena );
+
+    return (memarena);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_destroy(gsl_memarena_t *memarena)
+{
+    int       status = GSL_SUCCESS;
+    memblk_t  *p, *next;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_destroy(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    GSL_MEMARENA_LOCK();
+
+#ifdef _DEBUG
+    // memory leak check
+    if (memarena->freelist.head->blksize != memarena->sizebytes)
+    {
+        if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+        {
+            // external memory leak detected
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL,
+                            "ERROR: External memory leak detected.\n" );
+            return (GSL_FAILURE);
+        }
+    }
+#endif // _DEBUG
+
+    p = memarena->freelist.head;
+    do
+    {
+        next = p->next;
+        kgsl_memarena_releasememblknode(memarena, p);
+        p = next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (memarena->mutex)
+    {
+        kos_mutex_free(memarena->mutex);
+    }
+
+    kos_free((void *)memarena);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_destroy. Return value: %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_isvirtualized(gsl_memarena_t *memarena)
+{
+    // mmu virtualization enabled
+    return (GSL_MEMARENA_IS_MMU_VIRTUALIZED);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_checkconsistency(gsl_memarena_t *memarena)
+{
+    memblk_t *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkconsistency(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    // go through list of free blocks and make sure there are no detectable errors
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->next->blkaddr != memarena->freelist.head->blkaddr)
+        {
+            if (p->prev->next->blkaddr  != p->blkaddr || 
+                p->next->prev->blkaddr  != p->blkaddr ||
+                p->blkaddr + p->blksize >= p->next->blkaddr)
+            {
+                KOS_ASSERT(0);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+        p = p->next;
+
+    } while (p != memarena->freelist.head);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    KOS_ASSERT(stats);
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    kos_memcpy(stats, &memarena->stats, sizeof(gsl_memarena_stats_t));
+    
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) memarena;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena, int bytesneeded)
+{
+    memblk_t  *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena=0x%08x, int bytesneeded=%d)\n", memarena, bytesneeded );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (bytesneeded < 1)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal number of bytes needed.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_MEMARENA_LOCK();
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->blksize >= (unsigned int)bytesneeded)
+        {
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_SUCCESS );
+            return (GSL_SUCCESS);
+        }
+
+        p = p->next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+
+    return (GSL_FAILURE);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc)
+{
+    int           result = GSL_FAILURE_OUTOFMEM;
+    memblk_t      *ptrfree, *ptrlast, *p;
+    unsigned int  blksize;
+    unsigned int  baseaddr, alignedbaseaddr, alignfragment;
+    int           freeblk, alignmentshift;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid size for memory allocation.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    //
+    // go through the list of free blocks.  check to find block which can satisfy the alloc request
+    //
+    // if no block can satisfy the alloc request this implies that the memory is too fragmented
+    // and the requestor needs to free up other memory blocks and re-request the allocation
+    //
+    // if we do find a block that can satisfy the alloc request then reduce the size of free block
+    // by blksize and return the address after allocating the memory.  if the free block size becomes
+    // 0 then remove this node from the free list
+    //
+    // there would be no node on the free list if all available memory were to be allocated.  
+    // handling an empty list would require executing error checking code in the main branch which 
+    // is not desired.  instead, the free list will have at least one node at all times. This node 
+    // could have a block size of zero
+    //
+    // we use a next fit allocation mechanism that uses a roving pointer on a circular free block list. 
+    // the pointer is advanced along the chain when searching for a fit. Thus each allocation begins
+    // looking where the previous one finished. 
+    //
+
+    // when allocating from external memory aperture, round up size of requested block to multiple of page size if needed
+    if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+    {
+        if ((flags & GSL_MEMFLAGS_FORCEPAGESIZE) || GSL_MEMARENA_IS_MMU_VIRTUALIZED)
+        {
+            if (size & (GSL_PAGESIZE-1))
+            {
+                size = ((size >> GSL_PAGESIZE_SHIFT) + 1) << GSL_PAGESIZE_SHIFT;
+            }
+        }
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    // adjust size of requested block to include alignment
+    blksize = (unsigned int)((size + ((1 << alignmentshift) - 1)) >> alignmentshift) << alignmentshift;
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    ptrfree = memarena->freelist.allocrover;
+    ptrlast = memarena->freelist.head->prev;
+    freeblk = 0;
+
+    do
+    { 
+        // align base address
+        baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr;
+        alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift);
+       
+        alignfragment = alignedbaseaddr - baseaddr;
+
+        if (ptrfree->blksize >= blksize + alignfragment)
+        {
+            result  = GSL_SUCCESS;
+            freeblk = 1;
+
+            memdesc->gpuaddr = alignedbaseaddr;
+            memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr);
+            memdesc->size    = blksize;
+
+            if (alignfragment > 0)
+            {
+                // insert new node to handle newly created (small) fragment
+                p = kgsl_memarena_getmemblknode(memarena);
+                p->blkaddr = ptrfree->blkaddr;
+                p->blksize = alignfragment;
+
+                p->next = ptrfree;
+                p->prev = ptrfree->prev;
+                ptrfree->prev->next = p;
+                ptrfree->prev       = p;
+
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = p;
+                }
+            }
+
+            ptrfree->blkaddr += alignfragment + blksize;
+            ptrfree->blksize -= alignfragment + blksize;
+
+            memarena->freelist.allocrover = ptrfree;
+
+            if (ptrfree->blksize == 0 && ptrfree != ptrlast)
+            {
+                ptrfree->prev->next = ptrfree->next;
+                ptrfree->next->prev = ptrfree->prev;
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.allocrover)
+                {
+                    memarena->freelist.allocrover = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.freerover)
+                {
+                    memarena->freelist.freerover = ptrfree->prev;
+                }
+                p       = ptrfree;
+                ptrfree = ptrfree->prev;
+                kgsl_memarena_releasememblknode(memarena, p);
+            }
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (!freeblk && ptrfree != memarena->freelist.allocrover);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMARENA_STATS(
+        {   
+            int i = 0;
+            while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+            {
+                i++;
+            }
+            i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+            memarena->stats.allocs_pagedistribution[i]++;
+        });
+
+        GSL_MEMARENA_STATS(memarena->stats.allocs_success++);
+    }
+    else
+    {
+        GSL_MEMARENA_STATS(memarena->stats.allocs_fail++);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", result );
+        
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc)
+{
+    //
+    // request to free a malloc'ed block from the memory arena
+    // add this block to the free list
+    // adding a block to the free list requires the following:
+    // going through the list of free blocks to decide where to add this free block (based on address)
+    // coalesce free blocks
+    //
+    memblk_t      *ptrfree, *ptrend, *p;
+    int           mallocfreeblk, clockwise;
+    unsigned int  addrtofree;
+    
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_memarena_free(gsl_memarena_t *memarena=0x%08x, gsl_memdesc_t *memdesc=%M)\n", memarena, memdesc );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check size of malloc'ed block 
+    if (memdesc->size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal size for the memdesc.\n" );
+        KOS_ASSERT(0);
+
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check address range
+    KOS_ASSERT( memarena->gpubaseaddr <= memdesc->gpuaddr);
+    KOS_ASSERT((memarena->gpubaseaddr + memarena->sizebytes) >= memdesc->gpuaddr + memdesc->size);
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency of memory map, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    addrtofree    = memdesc->gpuaddr - memarena->gpubaseaddr;
+    mallocfreeblk = 1;
+
+    if (addrtofree < memarena->freelist.head->blkaddr)
+    {
+        // add node to head of free list
+
+        if (addrtofree + memdesc->size == memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head->blkaddr  = addrtofree;
+            memarena->freelist.head->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+
+        ptrfree = memarena->freelist.head->prev;
+    }
+    else if (addrtofree >= memarena->freelist.head->prev->blkaddr)
+    {
+        // add node to tail of free list
+
+        ptrfree = memarena->freelist.head->prev;
+
+        if (ptrfree->blkaddr + ptrfree->blksize == addrtofree)
+        {
+            ptrfree->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+    }
+    else
+    {
+        // determine range of free list nodes to traverse and orientation in which to traverse them
+        // keep this code segment unrolled for performance reasons!
+        if (addrtofree > memarena->freelist.freerover->blkaddr)
+        {
+            if (addrtofree - memarena->freelist.freerover->blkaddr < memarena->freelist.head->prev->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.freerover;       // rover
+                ptrend    = memarena->freelist.head->prev;      // tail
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.head->prev->prev; // tail
+                ptrend    = memarena->freelist.freerover->prev;  // rover
+                clockwise = 0;
+            }
+        }
+        else
+        {
+            if (addrtofree - memarena->freelist.head->blkaddr < memarena->freelist.freerover->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.head;            // head
+                ptrend    = memarena->freelist.freerover;       // rover
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.freerover->prev; // rover
+                ptrend    = memarena->freelist.head->prev;      // head
+                clockwise = 0;
+            }
+        }
+
+        // traverse the nodes
+        do
+        {
+            if ((addrtofree >= ptrfree->blkaddr + ptrfree->blksize) && 
+                (addrtofree + memdesc->size <= ptrfree->next->blkaddr))
+            {
+                if (addrtofree == ptrfree->blkaddr + ptrfree->blksize)
+                {
+                    memblk_t  *next;
+
+                    ptrfree->blksize += memdesc->size;
+                    next              = ptrfree->next;
+
+                    if (ptrfree->blkaddr + ptrfree->blksize == next->blkaddr)
+                    {
+                        ptrfree->blksize += next->blksize;
+                        ptrfree->next     = next->next;
+                        next->next->prev  = ptrfree;
+
+                        if (next == memarena->freelist.allocrover)
+                        {
+                            memarena->freelist.allocrover = ptrfree;
+                        }
+
+                        kgsl_memarena_releasememblknode(memarena, next);
+                    }
+
+                    mallocfreeblk = 0;
+                }
+                else if (addrtofree + memdesc->size == ptrfree->next->blkaddr)
+                {
+                    ptrfree->next->blkaddr  = addrtofree;
+                    ptrfree->next->blksize += memdesc->size;
+
+                    mallocfreeblk  = 0;
+                }
+
+                break;
+            }
+
+            if (clockwise)
+            {
+                ptrfree = ptrfree->next;
+            }
+            else
+            {
+                ptrfree = ptrfree->prev;
+            }
+
+        } while (ptrfree != ptrend);
+    }
+
+    // this free block could not be coalesced, so create a new free block
+    // and add it to the free list in the memory arena
+    if (mallocfreeblk)
+    {
+        p = kgsl_memarena_getmemblknode(memarena);
+        p->blkaddr = addrtofree;
+        p->blksize = memdesc->size;
+
+        p->next             = ptrfree->next;
+        p->prev             = ptrfree;
+        ptrfree->next->prev = p;
+        ptrfree->next       = p;
+
+        if (p->blkaddr < memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head = p;
+        }
+
+        memarena->freelist.freerover = p;
+    }
+    else
+    {
+        memarena->freelist.freerover = ptrfree;
+    }
+
+    GSL_MEMARENA_UNLOCK();
+
+    GSL_MEMARENA_STATS(
+    {   
+        int i = 0;
+        while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+        {
+            i++;
+        }
+        i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+        memarena->stats.frees_pagedistribution[i]++;
+    });
+
+    GSL_MEMARENA_STATS(memarena->stats.frees++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void *          
+kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr)
+{
+    //
+    // get the host mapped address for a hardware device address
+    //
+
+    void  *hostptr = NULL;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena=0x%08x, gpuaddr_t gpuaddr=0x%08x)\n", memarena, gpuaddr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    // check address range
+    KOS_ASSERT(gpuaddr >= memarena->gpubaseaddr);
+    KOS_ASSERT(gpuaddr <  memarena->gpubaseaddr + memarena->sizebytes);
+
+    hostptr = (void *)((gpuaddr - memarena->gpubaseaddr) + memarena->hostbaseaddr);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", hostptr );
+
+    return (hostptr);
+}
+
+//----------------------------------------------------------------------------
+
+gpuaddr_t           
+kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr)
+{
+    //
+    // get the hardware device address for a host mapped address
+    //
+
+    gpuaddr_t  gpuaddr = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena=0x%08x, void *hostptr=0x%08x)\n", memarena, hostptr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", 0 );
+        return (0);
+    }
+
+    // check address range
+    KOS_ASSERT(hostptr >= (void *)memarena->hostbaseaddr);
+    KOS_ASSERT(hostptr <  (void *)(memarena->hostbaseaddr + memarena->sizebytes));
+    
+    gpuaddr = ((unsigned int)hostptr - memarena->hostbaseaddr) + memarena->gpubaseaddr;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", gpuaddr );
+
+    return (gpuaddr);
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int    
+kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags)
+{
+    memblk_t      *ptrfree;
+    unsigned int  blocksize, largestblocksize = 0;
+    int           alignmentshift; 
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x)\n", memarena, flags );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", 0 );
+        return (0);
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    GSL_MEMARENA_LOCK();
+
+    ptrfree = memarena->freelist.head;
+
+    do
+    {
+        blocksize = ptrfree->blksize - (ptrfree->blkaddr - ((ptrfree->blkaddr >> alignmentshift) << alignmentshift));
+
+        if (blocksize > largestblocksize)
+        {
+            largestblocksize = blocksize;
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (ptrfree != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", largestblocksize );
+
+    return (largestblocksize);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c
new file mode 100644
index 000000000000..310677d926f0
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c
@@ -0,0 +1,1036 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------
+// pte debug
+// ---------
+
+typedef struct _gsl_pte_debug_t
+{
+    unsigned int    write     :1;
+    unsigned int    read      :1;
+    unsigned int    reserved  :10;
+    unsigned int    phyaddr   :20;
+} gsl_pte_debug_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PT_ENTRY_SIZEBYTES              4
+#define GSL_PT_EXTRA_ENTRIES                16
+
+#define GSL_PT_PAGE_WRITE                   0x00000001
+#define GSL_PT_PAGE_READ                    0x00000002
+
+#define GSL_PT_PAGE_AP_MASK                 0x00000003
+#define GSL_PT_PAGE_ADDR_MASK               ~(GSL_PAGESIZE-1)
+
+#define GSL_MMUFLAGS_TLBFLUSH               0x80000000
+
+#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS   (sizeof(unsigned char) * 8)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// constants
+//////////////////////////////////////////////////////////////////////////////
+const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), GSL_PT_PAGE_READ, GSL_PT_PAGE_WRITE, 0};
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_PT_ENTRY_GET(va)                ((va - pagetable->va_base) >> GSL_PAGESIZE_SHIFT)
+#define GSL_PT_VIRT_GET(pte)                (pagetable->va_base + (pte * GSL_PAGESIZE))
+
+#define GSL_PT_MAP_APDEFAULT                GSL_PT_PAGE_AP[0]
+
+#define GSL_PT_MAP_GET(pte)                 *((unsigned int *)(((unsigned int)pagetable->base.hostptr) + ((pte) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_PT_MAP_GETADDR(pte)             (GSL_PT_MAP_GET(pte) & GSL_PT_PAGE_ADDR_MASK)
+
+#define GSL_PT_MAP_DEBUG(pte)               ((gsl_pte_debug_t*) &GSL_PT_MAP_GET(pte))
+
+#define GSL_PT_MAP_SETBITS(pte, bits)       (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+#define GSL_PT_MAP_SETADDR(pte, pageaddr)   (GSL_PT_MAP_GET(pte)  = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK))
+
+#define GSL_PT_MAP_RESET(pte)               (GSL_PT_MAP_GET(pte)  = 0)
+#define GSL_PT_MAP_RESETBITS(pte, bits)     (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+
+#define GSL_MMU_VIRT_TO_PAGE(va)            *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_MMU_VIRT_TO_PHYS(va)            ((GSL_MMU_VIRT_TO_PAGE(va) & GSL_PT_PAGE_ADDR_MASK) + (va & (GSL_PAGESIZE-1)))
+
+#define GSL_TLBFLUSH_FILTER_GET(superpte)       *((unsigned char *)(((unsigned int)mmu->tlbflushfilter.base) + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte)  (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))
+#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte)   (GSL_TLBFLUSH_FILTER_GET((superpte)) & (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_RESET()             kos_memset(mmu->tlbflushfilter.base, 0, mmu->tlbflushfilter.size)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// process index in pagetable object table
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_getprocessindex(unsigned int pid, int *pindex)
+{
+    int status = GSL_SUCCESS;
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+    if (kgsl_driver_getcallerprocessindex(pid, pindex) != GSL_SUCCESS)
+    {
+        status = GSL_FAILURE;
+    }
+#else
+    (void) pid;      // unreferenced formal parameter
+    *pindex = 0;
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+    return (status);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// pagetable object for current caller process
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE gsl_pagetable_t*
+kgsl_mmu_getpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    int pindex = 0;
+    if (kgsl_mmu_getprocessindex(pid, &pindex) == GSL_SUCCESS)
+    {
+        return (mmu->pagetable[pindex]);
+    }
+    else
+    {
+        return (NULL);
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_mh_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_mmu_t     *mmu = (gsl_mmu_t *) cookie;
+    unsigned int   devindex = mmu->device->id-1;        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_mh_ntrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    // error condition interrupt
+    if (id == gsl_cfg_mh_intr[devindex].AXI_READ_ERROR  ||
+        id == gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR ||
+        id == gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT)
+    {
+        mmu->device->ftbl.device_destroy(mmu->device);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mh_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_mmu_debug(gsl_mmu_t *mmu, gsl_mmu_debug_t *regs)
+{
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+
+    kos_memset(regs, 0, sizeof(gsl_mmu_debug_t));
+
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].CONFIG,     &regs->config);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_BASE,   &regs->mpu_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_END,    &regs->mpu_end);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].VA_RANGE,   &regs->va_range);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE,    &regs->pt_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PAGE_FAULT, &regs->page_fault);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, &regs->trans_error);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, &regs->invalidate);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable)
+{
+    unsigned int     pte;
+    unsigned int     data;
+    gsl_pte_debug_t  *pte_debug;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable=0x%08x)\n", pagetable );
+
+    if (pagetable->last_superpte % GSL_PT_SUPER_PTE != 0)
+    {
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // go through page table and make sure there are no detectable errors
+    pte = 0;
+    while (pte < pagetable->max_entries)
+    {
+        pte_debug = GSL_PT_MAP_DEBUG(pte);
+
+        if (GSL_PT_MAP_GETADDR(pte) != 0)
+        {
+            // pte is in use
+
+            // access first couple bytes of a page
+            data = *((unsigned int *)GSL_PT_VIRT_GET(pte));
+        }
+
+        pte++;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (kgsl_mmu_getprocessindex(pid, &pindex) != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+        return (GSL_FAILURE);
+    }
+
+    pagetable = mmu->pagetable[pindex];
+
+    // if pagetable object exists for current "current device mmu"/"current caller process" combination
+    if (pagetable)
+    {
+        // no more "device mmu"/"caller process" combinations attached to current pagetable object
+        if (pagetable->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // memory leak check
+            if (pagetable->last_superpte != 0 || GSL_PT_MAP_GETADDR(pagetable->last_superpte))
+            {
+                /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                {
+                    KOS_ASSERT(0);
+                    return (GSL_FAILURE);
+                }
+            }
+#endif // _DEBUG
+
+            if (pagetable->base.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&pagetable->base, GSL_CALLER_PROCESSID_GET());
+            }
+
+            kos_free(pagetable);
+
+            // clear pagetable object reference for all "device mmu"/"current caller process" combinations
+            for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+            {
+                tmp_device = &gsl_driver.device[tmp_id-1];
+
+                if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+                {
+                    tmp_device->mmu.pagetable[pindex] = NULL;
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_pagetable_t*
+kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // create pagetable object for "current device mmu"/"current caller
+    // process" combination. If none exists, setup a new pagetable object.
+    //
+    int              status         = GSL_SUCCESS;
+    gsl_pagetable_t  *tmp_pagetable = NULL;
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_flags_t      flags;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    status = kgsl_mmu_getprocessindex(pid, &pindex);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+    // if pagetable object does not already exists for "current device mmu"/"current caller process" combination
+    if (!mmu->pagetable[pindex])
+    {
+        // then, check if pagetable object already exists for any "other device mmu"/"current caller process" combination
+        for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+        {
+            tmp_device = &gsl_driver.device[tmp_id-1];
+
+            if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+            {
+                if (tmp_device->mmu.pagetable[pindex])
+                {
+                    tmp_pagetable = tmp_device->mmu.pagetable[pindex];
+                    break;
+                }
+            }
+        }
+
+        // pagetable object exists
+        if (tmp_pagetable)
+        {
+            KOS_ASSERT(tmp_pagetable->va_base  == mmu->va_base);
+            KOS_ASSERT(tmp_pagetable->va_range == mmu->va_range);
+
+            // set pagetable object reference
+            mmu->pagetable[pindex] = tmp_pagetable;
+        }
+        // create new pagetable object
+        else
+        {
+            mmu->pagetable[pindex] = (void *)kos_malloc(sizeof(gsl_pagetable_t));
+            if (!mmu->pagetable[pindex])
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate pagetable object.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+                return (NULL);
+            }
+
+            kos_memset(mmu->pagetable[pindex], 0, sizeof(gsl_pagetable_t));
+
+			mmu->pagetable[pindex]->pid           = pid;
+            mmu->pagetable[pindex]->refcnt        = 0;
+            mmu->pagetable[pindex]->va_base       = mmu->va_base;
+            mmu->pagetable[pindex]->va_range      = mmu->va_range;
+            mmu->pagetable[pindex]->last_superpte = 0;
+            mmu->pagetable[pindex]->max_entries   = (mmu->va_range >> GSL_PAGESIZE_SHIFT) + GSL_PT_EXTRA_ENTRIES;
+
+            // allocate page table memory
+            flags  = (GSL_MEMFLAGS_ALIGN4K | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(mmu->device->id, flags, mmu->pagetable[pindex]->max_entries * GSL_PT_ENTRY_SIZEBYTES, &mmu->pagetable[pindex]->base);
+
+            if (status == GSL_SUCCESS)
+            {
+                // reset page table entries
+                kgsl_sharedmem_set0(&mmu->pagetable[pindex]->base, 0, 0, mmu->pagetable[pindex]->base.size);
+
+                KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MMU_TBLADDR, mmu->pagetable[pindex]->base.gpuaddr, 0, mmu->pagetable[pindex]->base.size, "kgsl_mmu_init"));
+            }
+            else
+            {
+                kgsl_mmu_destroypagetableobject(mmu, pid);
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", mmu->pagetable[pindex] );
+
+    return (mmu->pagetable[pindex]);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid)
+{
+    //
+    // set device mmu to use current caller process's page table
+    //
+    int              status   = GSL_SUCCESS;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_pagetable_t* kgsl_mmu_setpagetable(gsl_device_t *device=0x%08x)\n", device );
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+		// page table not current, then setup mmu to use new specified page table
+		if (mmu->hwpagetable->pid != pid)
+		{
+			gsl_pagetable_t  *pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+			if (pagetable)
+			{
+				mmu->hwpagetable = pagetable;
+
+				// flag tlb flush	
+				mmu->flags |= GSL_MMUFLAGS_TLBFLUSH;
+
+				status = mmu->device->ftbl.mmu_setpagetable(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, pagetable->base.gpuaddr, pid);
+
+				GSL_MMU_STATS(mmu->stats.pt.switches++);
+			}
+			else
+			{
+				status = GSL_FAILURE;
+			}
+		}
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+        // if needed, invalidate device specific tlb
+		if ((mmu->flags & GSL_MMUFLAGS_TLBFLUSH) && status == GSL_SUCCESS)
+        {
+            mmu->flags &= ~GSL_MMUFLAGS_TLBFLUSH;
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+			status = mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+		}
+	}
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_setpagetable. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_init(gsl_device_t *device)
+{
+    //
+    // intialize device mmu
+    //
+    // call this with the global lock held
+    //
+    int              status;
+    gsl_flags_t      flags;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+#ifdef _DEBUG
+    gsl_mmu_debug_t  regs;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_init(gsl_device_t *device=0x%08x)\n", device );
+
+    if (device->ftbl.mmu_tlbinvalidate == NULL || device->ftbl.mmu_setpagetable == NULL ||
+        !(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_INFO, "MMU already initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // setup backward reference
+    mmu->device = device;
+
+    // disable MMU when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        mmu->config = 0x00000000;
+    }
+
+    // setup MMU and sub-client behavior
+    device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, mmu->config);
+
+    // enable axi interrupts
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+
+    mmu->refcnt  = 0;
+    mmu->flags  |= GSL_FLAGS_INITIALIZED0;
+
+    // MMU enabled
+    if (mmu->config & 0x1)
+    {
+        // idle device
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // make sure aligned to pagesize
+        KOS_ASSERT((mmu->mpu_base & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+        KOS_ASSERT(((mmu->mpu_base + mmu->mpu_range) & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+
+        // define physical memory range accessible by the core
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_BASE, mmu->mpu_base);
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_END,  mmu->mpu_base + mmu->mpu_range);
+
+        // enable page fault interrupt
+        kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT, kgsl_mh_intrcallback, (void *) mmu);
+        kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+        mmu->flags |= GSL_FLAGS_INITIALIZED;
+
+        // sub-client MMU lookups require address translation
+        if ((mmu->config & ~0x1) > 0)
+        {
+            // make sure virtual address range is a multiple of 64Kb
+            KOS_ASSERT((mmu->va_range & ((1 << 16)-1)) == 0);
+
+            // setup pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+            if (!pagetable)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            mmu->hwpagetable = pagetable;
+
+            // create tlb flush filter to track dirty superPTE's -- one bit per superPTE
+            mmu->tlbflushfilter.size = (mmu->va_range / (GSL_PAGESIZE * GSL_PT_SUPER_PTE * 8)) + 1;
+            mmu->tlbflushfilter.base = (unsigned int *)kos_malloc(mmu->tlbflushfilter.size);
+            if (!mmu->tlbflushfilter.base)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+            // set page table base
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].PT_BASE, mmu->hwpagetable->base.gpuaddr);
+
+            // define virtual address range
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].VA_RANGE, (mmu->hwpagetable->va_base | (mmu->hwpagetable->va_range >> 16)));
+
+            // allocate memory used for completing r/w operations that cannot be mapped by the MMU
+            flags  = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(device->id, flags, 32, &mmu->dummyspace);
+            if (status != GSL_SUCCESS)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate dummy space memory.\n" );
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", status );
+                return (status);
+            }
+
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, mmu->dummyspace.gpuaddr);
+
+            // call device specific tlb invalidate
+			device->ftbl.mmu_tlbinvalidate(device, gsl_cfg_mmu_reg[devindex].INVALIDATE, mmu->hwpagetable->pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+
+            mmu->flags |= GSL_FLAGS_STARTED;
+        }
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_debug(&device->mmu, &regs));
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid)
+{
+    //
+    // map physical pages into the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    unsigned int     i, phyaddr, ap;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+    int              flushtlb;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_map(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, gsl_scatterlist_t *scatterlist=%M, gsl_flags_t flags=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, scatterlist, flags, pid );
+
+    KOS_ASSERT(scatterlist);
+
+    if (scatterlist->num <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: num pages is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // get gpu access permissions
+    ap = GSL_PT_PAGE_AP[((flags & GSL_MEMFLAGS_GPUAP_MASK) >> GSL_MEMFLAGS_GPUAP_SHIFT)];
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (scatterlist->num-1)));
+    flushtlb = 0;
+
+    if (!GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        // tlb needs to be flushed when the first and last pte are not at superpte boundaries
+        if ((ptefirst & (GSL_PT_SUPER_PTE-1)) != 0 || ((ptelast+1) & (GSL_PT_SUPER_PTE-1)) != 0)
+        {
+            flushtlb = 1;
+        }
+
+        // create page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            if (scatterlist->contiguous)
+            {
+                phyaddr = scatterlist->pages[0] + ((pte-ptefirst) * GSL_PAGESIZE);
+            }
+            else
+            {
+                phyaddr = scatterlist->pages[pte-ptefirst];
+            }
+
+            GSL_PT_MAP_SETADDR(pte, phyaddr);
+            GSL_PT_MAP_SETBITS(pte, ap);
+
+            // tlb needs to be flushed when a dirty superPTE gets backed
+            if ((pte & (GSL_PT_SUPER_PTE-1)) == 0)
+            {
+                if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE))
+                {
+                    flushtlb = 1;
+                }
+            }
+
+            KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map"));
+        }
+
+        if (flushtlb)
+        {
+            // every device's tlb needs to be flushed because the current page table is shared among all devices
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                if (gsl_driver.device[i].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    gsl_driver.device[i].mmu.flags |= GSL_MMUFLAGS_TLBFLUSH;
+                }
+            }
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte > pagetable->last_superpte)
+        {
+            pagetable->last_superpte = superpte;
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.maps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid)
+{
+    //
+    // remove mappings in the specified address range from the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_unmap(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, int range=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, range, pid );
+
+    if (range <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    if (GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1));
+        GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+
+        // remove page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            GSL_PT_MAP_RESET(pte);
+
+            superpte = pte - (pte & (GSL_PT_SUPER_PTE-1));
+            if (pte == superpte)
+            {
+                GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+            }
+
+			KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte, *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_unmap, reset superPTE"));
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte == pagetable->last_superpte && pagetable->last_superpte >= GSL_PT_SUPER_PTE)
+        {
+            do
+            {
+                pagetable->last_superpte -= GSL_PT_SUPER_PTE;
+            } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE);
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.unmaps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    // invalidate tlb, debug only
+	KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid));
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid)
+{
+    //
+    // obtain scatter list of physical pages for the given gpu address range.
+    // if all pages are physically contiguous they are coalesced into a single
+    // scatterlist entry.
+    //
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast;
+    unsigned int     contiguous = 1;
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    if (range <= 0 || scatterlist->num != numpages)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_getmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        return (GSL_FAILURE);
+    }
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    // determine whether pages are physically contiguous
+    if (numpages > 1)
+    {
+        for (pte = ptefirst; pte <= ptelast-1; pte++)
+        {
+            if (GSL_PT_MAP_GETADDR(pte) + GSL_PAGESIZE != GSL_PT_MAP_GETADDR(pte+1))
+            {
+                contiguous = 0;
+                break;
+            }
+        }
+    }
+
+    if (!contiguous)
+    {
+        // populate scatter list
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            scatterlist->pages[pte-ptefirst] = GSL_PT_MAP_GETADDR(pte);
+        }
+    }
+    else
+    {
+        // coalesce physically contiguous pages into a single scatter list entry
+        scatterlist->pages[0] = GSL_PT_MAP_GETADDR(ptefirst);
+    }
+
+    scatterlist->contiguous = contiguous;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_close(gsl_device_t *device)
+{
+    //
+    // close device mmu
+    //
+    // call this with the global lock held
+    //
+    gsl_mmu_t     *mmu     = &device->mmu;
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+#ifdef _DEBUG
+    int           i;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_close(gsl_device_t *device=0x%08x)\n", device );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // terminate pagetable object
+            kgsl_mmu_destroypagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+        }
+
+        // no more processes attached to current device mmu
+        if (mmu->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // check if there are any orphaned pagetable objects lingering around
+            for (i = 0; i < GSL_MMU_PAGETABLE_MAX; i++)
+            {
+                if (mmu->pagetable[i])
+                {
+                    /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                    /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                    if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                    {
+                        KOS_ASSERT(0);
+                        return (GSL_FAILURE);
+                    }
+                }
+            }
+#endif // _DEBUG
+
+            // disable mh interrupts
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+            // disable MMU
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, 0x00000000);
+
+            if (mmu->tlbflushfilter.base)
+            {
+                kos_free(mmu->tlbflushfilter.base);
+            }
+
+            if (mmu->dummyspace.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&mmu->dummyspace, GSL_CALLER_PROCESSID_GET());
+            }
+
+            mmu->flags &= ~GSL_FLAGS_STARTED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_close. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // attach process
+    //
+    // call this with the global lock held
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_attachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // attach to current device mmu
+        mmu->refcnt++;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // attach to pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt++;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_attachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // detach process
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_detachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // detach from current device mmu
+        mmu->refcnt--;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // detach from pagetable object
+            pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt--;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_detachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats)
+{
+#ifdef GSL_STATS_MMU
+    int              status = GSL_SUCCESS;
+
+    KOS_ASSERT(stats);
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+		kos_memcpy(stats, &mmu->stats, sizeof(gsl_mmustats_t));
+    }
+    else
+    {
+		kos_memset(stats, 0, sizeof(gsl_mmustats_t));
+    }
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) mmu;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MMU
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_bist(gsl_mmu_t *mmu)
+{
+    // unreferenced formal parameter
+    (void) mmu;
+
+    return (GSL_SUCCESS);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
new file mode 100644
index 000000000000..c4b62b0174d2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
@@ -0,0 +1,1154 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+#ifdef GSL_BLD_YAMATO
+
+//////////////////////////////////////////////////////////////////////////////
+// ucode
+//////////////////////////////////////////////////////////////////////////////
+#define uint32 unsigned int
+
+#include "pm4_microcode.inl"
+#include "pfp_microcode_nrt.inl"
+
+#undef  uint32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_RB_NOP_SIZEDWORDS               2               // default is 2
+#define GSL_RB_PROTECTED_MODE_CONTROL       0x00000000      // protected mode error checking below register address 0x800
+                                                            // note: if CP_INTERRUPT packet is used then checking needs
+                                                            // to change to below register address 0x7C8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  ringbuffer size log2 quadwords equivalent
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords)
+{
+    unsigned int sizelog2quadwords = 0;
+    int i = sizedwords >> 1;
+    while (i >>= 1)
+    {
+       sizelog2quadwords++;
+    }
+    return (sizelog2quadwords);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// private prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+static void     kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug);
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_cp_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_ringbuffer_t  *rb = (gsl_ringbuffer_t *) cookie;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_cp_intrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_CP_T0_PACKET_IN_IB:
+        case GSL_INTR_YDX_CP_OPCODE_ERROR:
+        case GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR:
+        case GSL_INTR_YDX_CP_RESERVED_BIT_ERROR:
+        case GSL_INTR_YDX_CP_IB_ERROR:
+
+            rb->device->ftbl.device_destroy(rb->device);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_CP_SW_INT:
+        case GSL_INTR_YDX_CP_IB2_INT:
+        case GSL_INTR_YDX_CP_IB1_INT:
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+
+            // signal intr completion event
+            kos_event_signal(rb->device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cp_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_watchdog()
+{
+    gsl_ringbuffer_t  *rb = &(gsl_driver.device[GSL_DEVICE_YAMATO-1]).ringbuffer;       // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_ringbuffer_watchdog()\n" );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        // ringbuffer is currently not empty
+        if (rb->rptr != rb->wptr)
+        {
+            // and a rptr sample was taken during interval n-1
+            if (rb->watchdog.flags & GSL_FLAGS_ACTIVE)
+            {
+                // and the rptr did not advance between interval n-1 and n
+                if (rb->rptr == rb->watchdog.rptr_sample)
+                {
+                    // then the core has hung
+                    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_FATAL,
+                                     "ERROR: Watchdog detected core hung.\n" );
+
+                    rb->device->ftbl.device_destroy(rb->device);
+                    return;
+                }
+            }
+
+            // save rptr sample for interval n
+            rb->watchdog.flags       |= GSL_FLAGS_ACTIVE;
+            rb->watchdog.rptr_sample  = rb->rptr;
+        }
+        else
+        {
+            // clear rptr sample for interval n
+            rb->watchdog.flags &= ~GSL_FLAGS_ACTIVE;
+        }
+
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_watchdog.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+OSINLINE void
+kgsl_ringbuffer_checkregister(unsigned int reg, int pmodecheck)
+{
+	if (pmodecheck)
+	{
+		// check for register protection mode violation
+		if (reg <= (GSL_RB_PROTECTED_MODE_CONTROL & 0x3FFF))
+		{
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register protection mode violation.\n" );
+			KOS_ASSERT(0);
+		}
+	}
+
+	// range check register offset 
+	if (reg > (gsl_driver.device[GSL_DEVICE_YAMATO-1].regspace.sizebytes >> 2))
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register out of range.\n" );
+		KOS_ASSERT(0);
+	}
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type0(unsigned int header, unsigned int** cmds, int pmodeoff)
+{
+    pm4_type0     pm4header = *((pm4_type0*) &header);
+    unsigned int  reg;
+
+    if (pm4header.one_reg_wr)
+    {
+        reg = pm4header.base_index;
+    }
+    else
+    {
+        reg = pm4header.base_index + pm4header.count;
+    }
+
+	kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type3(unsigned int header, unsigned int** cmds, int indirection, int pmodeoff)
+{
+    pm4_type3     pm4header = *((pm4_type3*) &header);
+    unsigned int  *ordinal2 = *cmds;
+    unsigned int  *ibcmds, *end;
+    unsigned int  reg, length;
+
+	// check indirect buffer level
+	if (indirection > 2)
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Only two levels of indirection supported.\n" );
+		KOS_ASSERT(0);
+	}
+
+    switch(pm4header.it_opcode)
+    {
+    case PM4_INDIRECT_BUFFER:
+    case PM4_INDIRECT_BUFFER_PFD:
+
+        // determine ib host base and end address
+        ibcmds = (unsigned int*) kgsl_sharedmem_convertaddr(*ordinal2, 0);
+        end    = ibcmds + *(ordinal2 + 1);
+
+        // walk through the ib
+        while(ibcmds < end)
+        {
+            unsigned int tmpheader = *(ibcmds++);
+
+            switch(tmpheader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(tmpheader, &ibcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(tmpheader, &ibcmds, (indirection + 1), pmodeoff);
+                break;
+            }
+        }
+        break;
+
+    case PM4_ME_INIT:
+
+        if(indirection != 0)
+        {
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: ME INIT packet cannot reside in an ib.\n" );
+            KOS_ASSERT(0);
+        }
+        break;
+
+    case PM4_REG_RMW:
+
+        reg = (*ordinal2) & 0x1FFF;
+
+		kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+        break;
+
+    case PM4_SET_CONSTANT:
+
+        if((((*ordinal2) >> 16) & 0xFF) == 0x4)         // incremental register update
+        {
+            reg    = 0x2000 + ((*ordinal2) & 0x3FF);    // gfx decode space address starts at 0x2000
+            length = pm4header.count - 1;
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_LOAD_CONSTANT_CONTEXT:
+
+        if(((*(ordinal2 + 1) >> 16) & 0xFF) == 0x4)      // incremental register update
+        {
+            reg    = 0x2000 + (*(ordinal2 + 1) & 0x3FF); // gfx decode space address starts at 0x2000
+            length = *(ordinal2 + 2);
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_COND_WRITE:
+
+        if(((*ordinal2) & 0x00000100) == 0x0)           // write to register
+        {
+            reg = *(ordinal2 + 4) & 0x3FFF;
+
+			kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+        }
+        break;
+    }
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeoff)
+{
+    unsigned int *ringcmds = cmds;
+    unsigned int *end      = cmds + sizedwords;
+
+    while(ringcmds < end)
+    {
+        unsigned int header = *(ringcmds++);
+
+        switch(header & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(header, &ringcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(header, &ringcmds, 0, pmodeoff);
+                break;
+        }
+    }
+}
+
+#endif // _DEBUG
+
+//----------------------------------------------------------------------------
+
+static void
+kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb)
+{
+    unsigned int value;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    KOS_ASSERT(rb->wptr != 0);
+
+    kgsl_device_active(rb->device);
+    
+    GSL_RB_UPDATE_WPTR_POLLING(rb);
+
+    // send the wptr to the hw
+    rb->device->ftbl.device_regwrite(rb->device, mmCP_RB_WPTR, rb->wptr);
+
+    // force wptr register to be updated
+    do
+    {
+        rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, &value);
+    } while (value != rb->wptr);
+
+    rb->flags |= GSL_FLAGS_ACTIVE;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_submit.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb, unsigned int numcmds, int wptr_ahead)
+{
+    int           nopcount;
+    unsigned int  freecmds;
+    unsigned int  *cmds;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d, int wptr_ahead=%d)\n",
+                    rb, numcmds, wptr_ahead );
+
+
+    // if wptr ahead, fill the remaining with NOPs
+    if (wptr_ahead)
+    {
+        nopcount = rb->sizedwords - rb->wptr - 1;   // -1 for header
+
+        cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+        GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount));
+        rb->wptr++;
+
+        kgsl_ringbuffer_submit(rb);
+
+        rb->wptr = 0;
+
+        GSL_RB_STATS(rb->stats.wraps++);
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RBWAIT, GSL_DEVICE_YAMATO, rb->wptr, numcmds, "kgsl_ringbuffer_waitspace"));
+
+    // wait for space in ringbuffer
+    for( ; ; )
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        freecmds = rb->rptr - rb->wptr;
+
+        if ((freecmds == 0) || (freecmds > numcmds))
+        {
+            break;
+        }
+
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static unsigned int *
+kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb, unsigned int numcmds)
+{
+    unsigned int  *ptr;
+    int           status = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static unsigned int* kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d)\n",
+                    rb, numcmds );
+
+    KOS_ASSERT(numcmds < rb->sizedwords);
+
+    // update host copy of read pointer when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+    }
+
+    // check for available space
+    if (rb->wptr >= rb->rptr)
+    {
+        // wptr ahead or equal to rptr
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+    else
+    {
+        // wptr behind rptr
+        if ((rb->wptr + numcmds) >= rb->rptr)
+        {
+            status  = kgsl_ringbuffer_waitspace(rb, numcmds, 0);
+        }
+
+        // check for remaining space
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+
+    ptr       = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+    rb->wptr += numcmds;
+
+    if (status == GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", ptr );
+        return (ptr);
+    }
+    else
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_start(gsl_ringbuffer_t *rb)
+{
+    int           status;
+    cp_rb_cntl_u  cp_rb_cntl;
+    int           i;
+    unsigned int  *cmds;
+    gsl_device_t  *device = rb->device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // clear memptrs values
+    kgsl_sharedmem_set0(&rb->memptrs_desc, 0, 0, sizeof(gsl_rbmemptrs_t));
+
+    // clear ringbuffer
+    kgsl_sharedmem_set0(&rb->buffer_desc, 0, 0x12341234, (rb->sizedwords << 2));
+
+    // setup WPTR polling address
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
+
+    // setup WPTR delay
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_DELAY, 0/*0x70000010*/);
+
+    // setup RB_CNTL
+    device->ftbl.device_regread(device, mmCP_RB_CNTL, (unsigned int *)&cp_rb_cntl);
+
+    cp_rb_cntl.f.rb_bufsz       = gsl_ringbuffer_sizelog2quadwords(rb->sizedwords); // size of ringbuffer
+    cp_rb_cntl.f.rb_blksz       = rb->blksizequadwords;                             // quadwords to read before updating mem RPTR
+    cp_rb_cntl.f.rb_poll_en     = GSL_RB_CNTL_POLL_EN;                              // WPTR polling
+    cp_rb_cntl.f.rb_no_update   = GSL_RB_CNTL_NO_UPDATE;                            // mem RPTR writebacks
+
+    device->ftbl.device_regwrite(device, mmCP_RB_CNTL, cp_rb_cntl.val);
+
+    // setup RB_BASE
+    device->ftbl.device_regwrite(device, mmCP_RB_BASE, rb->buffer_desc.gpuaddr);
+
+    // setup RPTR_ADDR
+    device->ftbl.device_regwrite(device, mmCP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET);
+
+    // explicitly clear all cp interrupts when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_regwrite(device, mmCP_INT_ACK, 0xFFFFFFFF);
+    }
+
+    // setup scratch/timestamp addr
+    device->ftbl.device_regwrite(device, mmSCRATCH_ADDR, device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp));
+
+    // setup scratch/timestamp mask
+    device->ftbl.device_regwrite(device, mmSCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK);
+
+    // load the CP ucode
+    device->ftbl.device_regwrite(device, mmCP_DEBUG, 0x02000000);
+    device->ftbl.device_regwrite(device, mmCP_ME_RAM_WADDR, 0);
+
+    for (i = 0; i < PM4_MICROCODE_SIZE; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][0]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][1]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][2]);
+    }
+
+    // load the prefetch parser ucode
+    device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_ADDR, 0);
+
+    for ( i = 0; i < PFP_MICROCODE_SIZE_NRT; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_DATA, aPFP_Microcode_nrt[i]);
+    }
+
+    // queue thresholds ???
+    device->ftbl.device_regwrite(device, mmCP_QUEUE_THRESHOLDS, 0x000C0804);
+
+    // reset pointers
+    rb->rptr = 0;
+    rb->wptr = 0;
+
+    // init timestamp
+    rb->timestamp    = 0;
+    GSL_RB_INIT_TIMESTAMP(rb);
+
+    // clear ME_HALT to start micro engine
+    device->ftbl.device_regwrite(device, mmCP_ME_CNTL, 0);
+
+    // ME_INIT
+    cmds  = kgsl_ringbuffer_addcmds(rb, 19);
+
+    GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT);
+    GSL_RB_WRITE(cmds, 0x000003ff);                         // All fields present (bits 9:0)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable/Enable Real-Time Stream processing (present but ignored)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Enable (2D to 3D) and (3D to 2D) implicit synchronization (present but ignored)
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_SURFACE_INFO));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_WINDOW_OFFSET));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmVGT_MAX_VTX_INDX));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmSQ_PROGRAM_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_DEPTHCONTROL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POINT_SIZE));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_LINE_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POLY_OFFSET_FRONT_SCALE));
+    GSL_RB_WRITE(cmds, 0x80000180);                         // Vertex and Pixel Shader Start Addresses in instructions (3 DWORDS per instruction)
+    GSL_RB_WRITE(cmds, 0x00000001);                         // Maximum Contexts
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Write Confirm Interval and The CP will wait the wait_interval * 16 clocks between polling
+    GSL_RB_WRITE(cmds, 0x00000000);                         // NQ and External Memory Swap
+    GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL);      // Protected mode error checking
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable header dumping and Header dump address
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Header dump size
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4((unsigned int *)rb->buffer_desc.hostptr, 19, 1));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4((unsigned int *)rb->buffer_desc.hostptr, 19));
+
+    kgsl_ringbuffer_submit(rb);
+
+    // idle device to validate ME INIT
+    status = device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+    if (status == GSL_SUCCESS)
+    {
+        rb->flags |= GSL_FLAGS_STARTED;
+    }
+
+    // enable cp interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_SW_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB2_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB1_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_SW_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB2_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB1_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        // disable cp interrupts
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_SW_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB2_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB1_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+        // ME_HALT
+        rb->device->ftbl.device_regwrite(rb->device, mmCP_ME_CNTL, 0x10000000);
+
+        rb->flags &= ~GSL_FLAGS_STARTED;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_stop. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_init(gsl_device_t *device)
+{
+    int               status;
+    gsl_flags_t       flags;
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_init(gsl_device_t *device=0x%08x)\n", device );
+
+    rb->device           = device;
+    rb->sizedwords       = (2 << gsl_cfg_rb_sizelog2quadwords);
+    rb->blksizequadwords = gsl_cfg_rb_blksizequadwords;
+
+    // allocate memory for ringbuffer, needs to be double octword aligned
+    // align on page from contiguous physical memory
+    flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_STRICTREQUEST)); /* set MMU table for ringbuffer */
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, (rb->sizedwords << 2), &rb->buffer_desc);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_SET, (unsigned int)rb->buffer_desc.gpuaddr, (unsigned int)rb->buffer_desc.hostptr, 0, "kgsl_ringbuffer_init"));
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // allocate memory for polling and timestamps
+    flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = GSL_MEMFLAGS_ALIGN32);
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, sizeof(gsl_rbmemptrs_t), &rb->memptrs_desc);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // overlay structure on memptrs memory
+    rb->memptrs = (gsl_rbmemptrs_t *)rb->memptrs_desc.hostptr;
+
+    rb->flags |= GSL_FLAGS_INITIALIZED;
+
+	// validate command stream data when running in safe mode
+	if (device->flags & GSL_FLAGS_SAFEMODE)
+	{
+		gsl_driver.flags_debug |= GSL_DBGFLAGS_PM4CHECK;
+	}
+
+    // start ringbuffer
+    status = kgsl_ringbuffer_start(rb);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_close(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    // stop ringbuffer
+    kgsl_ringbuffer_stop(rb);
+
+    // free buffer
+    if (rb->buffer_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->buffer_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    // free memory pointers
+    if (rb->memptrs_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->memptrs_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    rb->flags &= ~GSL_FLAGS_INITIALIZED;
+
+    kos_memset(rb, 0, sizeof(gsl_ringbuffer_t));
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_close. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmds, int sizedwords, unsigned int pid)
+{
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+    unsigned int      pmodesizedwords;
+    unsigned int      *ringcmds;
+    unsigned int      timestamp;
+
+    pmodeoff = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device=0x%08x, int pmodeoff=%d, unsigned int *cmds=0x%08x, int sizedwords=%d, unsigned int pid=0x%08x)\n",
+                     device, pmodeoff, cmds, sizedwords, pid );
+
+	if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+	{
+		return (0);
+	}
+
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, pid);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4(cmds, sizedwords, pmodeoff));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4(cmds, sizedwords));
+
+    // reserve space to temporarily turn off protected mode error checking if needed
+    pmodesizedwords = pmodeoff ? 8 : 0;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+    pmodesizedwords += 2;
+#endif        
+    // allocate space in ringbuffer
+    ringcmds = kgsl_ringbuffer_addcmds(rb, pmodesizedwords + sizedwords + 6);
+
+    if (pmodeoff)
+    {
+        // disable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = 0x00000000;
+    }
+
+    // copy the cmds to the ringbuffer
+    kos_memcpy(ringcmds, cmds, (sizedwords << 2));
+
+    ringcmds += sizedwords;
+
+    if (pmodeoff)
+    {
+        *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        *ringcmds++ = 0;
+
+        // re-enable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = GSL_RB_PROTECTED_MODE_CONTROL;
+    }
+
+    // increment timestamp
+    rb->timestamp++;
+    timestamp = rb->timestamp;
+
+    // start-of-pipeline and end-of-pipeline timestamps
+    *ringcmds++ = pm4_type0_packet(mmCP_TIMESTAMP, 1);
+    *ringcmds++ = rb->timestamp;
+    *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3);
+    *ringcmds++ = CACHE_FLUSH_TS;
+    *ringcmds++ = device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp);
+    *ringcmds++ = rb->timestamp;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT    
+    *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1);
+    *ringcmds++ = 0x80000000;
+#endif
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (pmodesizedwords + sizedwords + 6) << 2, "kgsl_ringbuffer_issuecmds"));
+
+    // issue the commands
+    kgsl_ringbuffer_submit(rb);
+
+    // stats
+    GSL_RB_STATS(rb->stats.wordstotal += sizedwords);
+    GSL_RB_STATS(rb->stats.issues++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issuecmds. Return value %d\n", timestamp );
+
+    // return timestamp of issued commands
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags)
+{
+    unsigned int  link[3];
+    int dumpx_swap;
+    (void)dumpx_swap; // used only when BB_DUMPX is defined
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issueibcmds(gsl_device_t device=%0x%08x, int drawctxt_index=%d, gpuaddr_t ibaddr=0x%08x, int sizedwords=%d, gsl_timestamp_t *timestamp=0x%08x)\n",
+                     device, drawctxt_index, ibaddr, sizedwords, timestamp );
+
+    if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(ibaddr);
+    KOS_ASSERT(sizedwords);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, dumpx_swap = kgsl_dumpx_parse_ibs(ibaddr, sizedwords));
+
+	// context switch if needed
+	kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags);
+
+    link[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    link[1] = ibaddr;
+    link[2] = sizedwords;
+
+	*timestamp = kgsl_ringbuffer_issuecmds(device, 0, &link[0], 3, GSL_CALLER_PROCESSID_GET());
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+    else
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // insert wait for idle after every IB1
+            // this is conservative but works reliably and is ok even for performance simulations
+            device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+        });
+    }
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        if(dumpx_swap)
+        {
+            KGSL_DEBUG_DUMPX( BB_DUMP_EXPORT_CBUF, 0, 0, 0, "resolve");
+            KGSL_DEBUG_DUMPX( BB_DUMP_FLUSH,0,0,0," ");
+        }
+    });
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug)
+{
+    kos_memset(rb_debug, 0, sizeof(gsl_rb_debug_t));
+
+    rb_debug->pm4_ucode_rel = PM4_MICROCODE_VERSION;
+    rb_debug->pfp_ucode_rel = PFP_MICROCODE_VERSION;
+
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_BASE,      (unsigned int *)&rb_debug->cp_rb_base);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_CNTL,      (unsigned int *)&rb_debug->cp_rb_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR_ADDR, (unsigned int *)&rb_debug->cp_rb_rptr_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR,      (unsigned int *)&rb_debug->cp_rb_rptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR,      (unsigned int *)&rb_debug->cp_rb_wptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR_BASE, (unsigned int *)&rb_debug->cp_rb_wptr_base);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_UMSK,    (unsigned int *)&rb_debug->scratch_umsk);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_ADDR,    (unsigned int *)&rb_debug->scratch_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_CNTL,      (unsigned int *)&rb_debug->cp_me_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_STATUS,    (unsigned int *)&rb_debug->cp_me_status);
+    rb->device->ftbl.device_regread(rb->device, mmCP_DEBUG,        (unsigned int *)&rb_debug->cp_debug);
+    rb->device->ftbl.device_regread(rb->device, mmCP_STAT,         (unsigned int *)&rb_debug->cp_stat);
+    rb->device->ftbl.device_regread(rb->device, mmRBBM_STATUS,     (unsigned int *)&rb_debug->rbbm_status);
+    rb_debug->sop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_CONSUMED);
+    rb_debug->eop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_RETIRED);
+}
+#endif
+
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats)
+{
+#ifdef GSL_STATS_RINGBUFFER
+    KOS_ASSERT(stats);
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    kos_memcpy(stats, &rb->stats, sizeof(gsl_rbstats_t));
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) rb;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_RINGBUFFER
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb)
+{
+    unsigned int    *cmds;
+    unsigned int    temp, k, j;
+    int             status;
+    int             i;
+#ifdef _DEBUG
+    gsl_rb_debug_t  rb_debug;
+#endif
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple nop submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_nop_packet(1));
+    GSL_RB_WRITE(cmds, 0xDEADBEEF);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    // simple scratch submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+    GSL_RB_WRITE(cmds, 0xFEEDF00D);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+    if (temp != 0xFEEDF00D)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple wraps
+    for (i = 0; i < 256; i+=2)
+    {
+        j    = ((rb->sizedwords >> 2) - 256) + i;
+
+        cmds = kgsl_ringbuffer_addcmds(rb, j);
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        k = 0;
+
+        while (k < j)
+        {
+            k+=2;
+            GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+            GSL_RB_WRITE(cmds, k);
+        }
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+
+        rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+        if (temp != k)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+    }
+
+    // max size submits, TODO do this at least with regreads
+    for (i = 0; i < 256; i++)
+    {
+        cmds = kgsl_ringbuffer_addcmds(rb, (rb->sizedwords >> 2));
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        GSL_RB_WRITE(cmds, pm4_nop_packet((rb->sizedwords >> 2) - 1));
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+    }
+
+    // submit load with randomness
+
+#ifdef GSL_RB_USE_MEM_TIMESTAMP
+    // scratch memptr validate
+#endif // GSL_RB_USE_MEM_TIMESTAMP
+
+#ifdef GSL_RB_USE_MEM_RPTR
+    // rptr memptr validate
+#endif // GSL_RB_USE_MEM_RPTR
+
+#ifdef  GSL_RB_USE_WPTR_POLLING
+    // wptr memptr validate
+#endif // GSL_RB_USE_WPTR_POLLING
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_sharedmem.c b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
new file mode 100644
index 000000000000..51e66f97c52e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
@@ -0,0 +1,937 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SHMEM_APERTURE_MARK(aperture_id)    \
+    (shmem->priv |= (((aperture_id + 1) << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK))
+
+#define GSL_SHMEM_APERTURE_ISMARKED(aperture_id)    \
+    (((shmem->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT) & (aperture_id + 1))
+
+#define GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id)                                                       \
+    aperture_id = (gsl_apertureid_t)((flags & GSL_MEMFLAGS_APERTURE_MASK) >> GSL_MEMFLAGS_APERTURE_SHIFT);  \
+    KOS_ASSERT(aperture_id < GSL_APERTURE_MAX);
+
+#define GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id)                                                     \
+    channel_id = (gsl_channelid_t)((flags & GSL_MEMFLAGS_CHANNEL_MASK) >> GSL_MEMFLAGS_CHANNEL_SHIFT);  \
+    KOS_ASSERT(channel_id < GSL_CHANNEL_MAX);
+
+#define GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index)   \
+    memdesc->priv = (memdesc->priv & ~GSL_APERTURE_MASK) | ((aperture_index << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK);
+
+#define GSL_MEMDESC_DEVICE_SET(memdesc, device_id)  \
+    memdesc->priv = (memdesc->priv & ~GSL_DEVICEID_MASK) | ((device_id << GSL_DEVICEID_SHIFT) & GSL_DEVICEID_MASK);
+
+#define GSL_MEMDESC_EXTALLOC_SET(memdesc, flag) \
+    memdesc->priv = (memdesc->priv & ~GSL_EXTALLOC_MASK) | ((flag << GSL_EXTALLOC_SHIFT) & GSL_EXTALLOC_MASK);
+
+#define GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index)                           \
+    KOS_ASSERT(memdesc);                                                            \
+    aperture_index = ((memdesc->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT);   \
+    KOS_ASSERT(aperture_index < GSL_SHMEM_MAX_APERTURES);
+
+#define GSL_MEMDESC_DEVICE_GET(memdesc, device_id)                                              \
+    KOS_ASSERT(memdesc);                                                                        \
+    device_id = (gsl_deviceid_t)((memdesc->priv & GSL_DEVICEID_MASK) >> GSL_DEVICEID_SHIFT);    \
+    KOS_ASSERT(device_id <= GSL_DEVICE_MAX);
+
+#define GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)  \
+    ((memdesc->priv & GSL_EXTALLOC_MASK) >> GSL_EXTALLOC_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// aperture index in shared memory object
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_sharedmem_getapertureindex(gsl_sharedmem_t *shmem, gsl_apertureid_t aperture_id, gsl_channelid_t channel_id)
+{
+    KOS_ASSERT(shmem->aperturelookup[aperture_id][channel_id] < shmem->numapertures);
+
+    return (shmem->aperturelookup[aperture_id][channel_id]);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_sharedmem_init(gsl_sharedmem_t *shmem)
+{
+    int                i;
+    int                status;
+    gsl_shmemconfig_t  config;
+    int                mmu_virtualized;
+    gsl_apertureid_t   aperture_id;
+    gsl_channelid_t    channel_id;
+    unsigned int       hostbaseaddr;
+    gpuaddr_t          gpubaseaddr;
+    int                sizebytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_init(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    status = kgsl_hal_getshmemconfig(&config);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to get sharedmem config.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", status );
+        return (status);
+    }
+
+    shmem->numapertures = config.numapertures;
+
+    for (i = 0; i < shmem->numapertures; i++)
+    {
+        aperture_id     = config.apertures[i].id;
+        channel_id      = config.apertures[i].channel;
+        hostbaseaddr    = config.apertures[i].hostbase;
+        gpubaseaddr     = config.apertures[i].gpubase;
+        sizebytes       = config.apertures[i].sizebytes;
+        mmu_virtualized = 0;
+
+        // handle mmu virtualized aperture
+        if (aperture_id == GSL_APERTURE_MMU)
+        {
+            mmu_virtualized = 1;
+            aperture_id     = GSL_APERTURE_EMEM;
+        }
+
+        // make sure aligned to page size
+        KOS_ASSERT((gpubaseaddr & ((1 << GSL_PAGESIZE_SHIFT) - 1)) == 0);
+
+        // make a multiple of page size
+        sizebytes = (sizebytes & ~((1 << GSL_PAGESIZE_SHIFT) - 1));
+
+        if (sizebytes > 0)
+        {
+            shmem->apertures[i].memarena = kgsl_memarena_create(aperture_id, mmu_virtualized, hostbaseaddr, gpubaseaddr, sizebytes);
+
+            if (!shmem->apertures[i].memarena)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate memarena.\n" );
+                kgsl_sharedmem_close(shmem);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            shmem->apertures[i].id       = aperture_id;
+            shmem->apertures[i].channel  = channel_id;
+            shmem->apertures[i].numbanks = 1;
+
+            // create aperture lookup table
+            if (GSL_SHMEM_APERTURE_ISMARKED(aperture_id))
+            {
+                // update "current aperture_id"/"current channel_id" index
+                shmem->aperturelookup[aperture_id][channel_id] = i;
+            }
+            else
+            {
+                // initialize "current aperture_id"/"channel_id" indexes
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    shmem->aperturelookup[aperture_id][channel_id] = i;
+                }
+
+                GSL_SHMEM_APERTURE_MARK(aperture_id);
+            }
+        }
+    }
+
+    shmem->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_close(gsl_sharedmem_t *shmem)
+{
+    int  i;
+    int  result = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_close(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                result = kgsl_memarena_destroy(shmem->apertures[i].memarena);
+            }
+        }
+
+        kos_memset(shmem, 0, sizeof(gsl_sharedmem_t));
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_close. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    gsl_deviceid_t    tmp_id;
+    int               aperture_index, org_index;
+    int               result  = GSL_FAILURE;
+    gsl_mmu_t         *mmu    = NULL;
+    gsl_sharedmem_t   *shmem  = &gsl_driver.shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_alloc(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, int sizebytes=%d, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, sizebytes, memdesc );
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc);
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    // get mmu reference
+    mmu = &gsl_driver.device[device_id-1].mmu;
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    //do not proceed if it is a strict request, the aperture requested is not present, and the MMU is enabled
+    if (!((flags & GSL_MEMFLAGS_STRICTREQUEST) && aperture_id != shmem->apertures[aperture_index].id && kgsl_mmu_isenabled(mmu)))
+    {
+        // do allocation
+        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+        // if allocation failed
+        if (result != GSL_SUCCESS)
+        {
+            org_index = aperture_index;
+
+            // then failover to other channels within the current aperture
+            for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+            {
+                aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                if (aperture_index != org_index)
+                {
+                    // do allocation
+                    result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                    if (result == GSL_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            // if allocation still has not succeeded, then failover to EMEM/MMU aperture, but
+            // not if it's a strict request and the MMU is enabled
+            if (result != GSL_SUCCESS && aperture_id != GSL_APERTURE_EMEM
+                && !((flags & GSL_MEMFLAGS_STRICTREQUEST) && kgsl_mmu_isenabled(mmu)))
+            {
+                aperture_id = GSL_APERTURE_EMEM;
+
+                // try every channel
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                    if (aperture_index != org_index)
+                    {
+                        // do allocation
+                        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                        if (result == GSL_SUCCESS)
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+        GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            gsl_scatterlist_t scatterlist;
+
+            scatterlist.contiguous = 0;
+            scatterlist.num        = memdesc->size / GSL_PAGESIZE;
+
+            if (memdesc->size & (GSL_PAGESIZE-1))
+            {
+                scatterlist.num++;
+            }
+
+            scatterlist.pages = kos_malloc(sizeof(unsigned int) * scatterlist.num);
+            if (scatterlist.pages)
+            {
+                // allocate physical pages
+                result = kgsl_hal_allocphysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                if (result == GSL_SUCCESS)
+                {
+                    result = kgsl_mmu_map(mmu, memdesc->gpuaddr, &scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                    if (result != GSL_SUCCESS)
+                    {
+                        kgsl_hal_freephysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                    }
+                }
+
+                kos_free(scatterlist.pages);
+            }
+            else
+            {
+                result = GSL_FAILURE;
+            }
+
+            if (result != GSL_SUCCESS)
+            {
+                kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+            }
+        }
+    }
+
+    KGSL_DEBUG_TBDUMP_SETMEM( memdesc->gpuaddr, 0, memdesc->size );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_alloc0(device_id, flags, sizebytes, memdesc);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_free(gsl_memdesc_t *memdesc=%M)\n", memdesc );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status |= kgsl_mmu_unmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, pid);
+
+            if (!GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+            {
+                status |= kgsl_hal_freephysical(memdesc->gpuaddr, memdesc->size / GSL_PAGESIZE, NULL);
+            }
+        }
+
+        kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+
+        // clear descriptor
+        kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_free. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_free(gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+    GSL_API_MUTEX_LOCK();
+    status = kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET());
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_read(gsl_memdesc_t *memdesc=%M, void *dst=0x%08x, unsigned int offsetbytes=%d, unsigned int sizebytes=%d)\n",
+                    memdesc, dst, offsetbytes, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(dst);
+    KOS_ASSERT(sizebytes);
+
+    if (memdesc->gpuaddr < shmem->apertures[aperture_index].memarena->gpubaseaddr)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (memdesc->gpuaddr + sizebytes > shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_READ(dst, shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, sizebytes, touserspace);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_read0(memdesc, dst, offsetbytes, sizebytes, touserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_write(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, void *src=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, src, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(src);
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_WRITE(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, src, sizebytes, fromuserspace);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMWRITE((memdesc->gpuaddr + offsetbytes), sizebytes, src));
+
+    KGSL_DEBUG_TBDUMP_SYNCMEM( (memdesc->gpuaddr + offsetbytes), src, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_write0(memdesc, offsetbytes, src, sizebytes, fromuserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_set(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, unsigned int value=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, value, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_SET(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, value, sizebytes);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMSET((memdesc->gpuaddr + offsetbytes), sizebytes, value));
+
+    KGSL_DEBUG_TBDUMP_SETMEM( (memdesc->gpuaddr + offsetbytes), value, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_set0(memdesc, offsetbytes, value, sizebytes);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API unsigned int
+kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    int               aperture_index;
+    unsigned int      result = 0;
+    gsl_sharedmem_t   *shmem;
+
+    // device_id is ignored at this level, it would be used with per-device memarena's
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x)\n",
+                    device_id, flags );
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    GSL_API_MUTEX_LOCK();
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", 0 );
+        return (0);
+    }
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    if (aperture_id == shmem->apertures[aperture_index].id)
+    {
+        result = kgsl_memarena_getlargestfreeblock(shmem->apertures[aperture_index].memarena, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc)
+{
+    int              status = GSL_FAILURE;
+    gsl_sharedmem_t  *shmem = &gsl_driver.shmem;
+    int              aperture_index;
+    gsl_deviceid_t   tmp_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_map(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, gsl_scatterlist_t scatterlist=%M, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, memdesc, scatterlist );
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        aperture_index = kgsl_sharedmem_getapertureindex(shmem, GSL_APERTURE_EMEM, GSL_CHANNEL_1);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            KOS_ASSERT(scatterlist->num);
+            KOS_ASSERT(scatterlist->pages);
+
+            status = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, scatterlist->num *GSL_PAGESIZE, memdesc);
+            if (status == GSL_SUCCESS)
+            {
+                GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+                GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+                // mark descriptor's memory as externally allocated -- i.e. outside GSL
+                GSL_MEMDESC_EXTALLOC_SET(memdesc, 1);
+
+                status = kgsl_mmu_map(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                if (status != GSL_SUCCESS)
+                {
+                    kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc)
+{
+    return (kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET()));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_getmap(gsl_memdesc_t *memdesc=%M, gsl_scatterlist_t scatterlist=%M)\n",
+                    memdesc, scatterlist );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        KOS_ASSERT(scatterlist->num);
+        KOS_ASSERT(scatterlist->pages);
+        KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+        KOS_ASSERT((memdesc->gpuaddr + memdesc->size) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+        kos_memset(scatterlist->pages, 0, sizeof(unsigned int) * scatterlist->num);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status = kgsl_mmu_getmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, scatterlist, GSL_CALLER_PROCESSID_GET());
+        }
+        else
+        {
+            // coalesce physically contiguous pages into a single scatter list entry
+            scatterlist->pages[0]   = memdesc->gpuaddr;
+            scatterlist->contiguous = 1;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_getmap. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    int  status = GSL_SUCCESS;
+    int  i;
+
+    KOS_ASSERT(stats);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                stats->apertures[i].id      = shmem->apertures[i].id;
+                stats->apertures[i].channel = shmem->apertures[i].channel;
+
+                status |= kgsl_memarena_querystats(shmem->apertures[i].memarena, &stats->apertures[i].memarena);
+            }
+        }
+    }
+    else
+    {
+        kos_memset(stats, 0, sizeof(gsl_sharedmem_stats_t));
+    }
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) shmem;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int
+kgsl_sharedmem_convertaddr(unsigned int addr, int type)
+{
+    gsl_sharedmem_t  *shmem  = &gsl_driver.shmem;
+    unsigned int     cvtaddr = 0;
+    unsigned int     gpubaseaddr, hostbaseaddr, sizebytes;
+    int              i;
+
+    if ((shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            hostbaseaddr = shmem->apertures[i].memarena->hostbaseaddr;
+            gpubaseaddr  = shmem->apertures[i].memarena->gpubaseaddr;
+            sizebytes    = shmem->apertures[i].memarena->sizebytes;
+
+            // convert from gpu to host
+            if (type == 0)
+            {
+                if (addr >= gpubaseaddr && addr < (gpubaseaddr + sizebytes))
+                {
+                    cvtaddr = hostbaseaddr + (addr - gpubaseaddr);
+                    break;
+                }
+            }
+            // convert from host to gpu
+            else if (type == 1)
+            {
+                if (addr >= hostbaseaddr && addr < (hostbaseaddr + sizebytes))
+                {
+                    cvtaddr = gpubaseaddr + (addr - hostbaseaddr);
+                    break;
+                }
+            }
+        }
+    }
+
+    return (cvtaddr);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation)
+{
+    int status  = GSL_FAILURE;
+
+    /* unreferenced formal parameter */
+    (void)memdesc;
+    (void)offsetbytes;
+    (void)sizebytes;
+    (void)operation;
+
+    /* do cache operation */
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr)
+{
+    int status  = GSL_FAILURE;
+
+    memdesc->gpuaddr = (gpuaddr_t)hostptr;  /* map physical address with hostptr    */
+    memdesc->hostptr = hostptr;             /* set virtual address also in memdesc  */
+
+    /* unreferenced formal parameter */
+    (void)device_id;
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_tbdump.c b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
new file mode 100644
index 000000000000..e22cf894f7b2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
@@ -0,0 +1,228 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <stdio.h>
+#ifdef WIN32
+#include <windows.h>
+#endif
+#include "gsl.h"
+#include "gsl_tbdump.h"
+#include "kos_libapi.h"
+
+#ifdef TBDUMP
+
+typedef struct TBDump_
+{
+    void* file;
+} TBDump;
+
+
+static TBDump g_tb;
+static oshandle_t tbdump_mutex = 0;
+#define TBDUMP_MUTEX_LOCK() if( tbdump_mutex ) kos_mutex_lock( tbdump_mutex )
+#define TBDUMP_MUTEX_UNLOCK() if( tbdump_mutex ) kos_mutex_unlock( tbdump_mutex )
+
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+
+static void tbdump_printline(const char* format, ...)
+{
+    if(g_tb.file)
+    {
+        va_list va;
+        va_start(va, format);
+        vfprintf((FILE*)g_tb.file, format, va);
+        va_end(va);
+        fprintf((FILE*)g_tb.file, "\n");
+    }
+}
+
+static void tbdump_printinfo(const char* message )
+{
+    tbdump_printline("15 %s", message);
+}
+
+static void tbdump_getmemhex(char* buffer, unsigned int addr, unsigned int sizewords)
+{
+    unsigned int i = 0;
+    static const char* hexChars = "0123456789abcdef";
+    unsigned char* ptr = (unsigned char*)addr;
+
+    for (i = 0; i < sizewords; i++)
+    {
+        buffer[(sizewords - i) * 2 - 1] = hexChars[ptr[i] & 0x0f];
+        buffer[(sizewords - i) * 2 - 2] = hexChars[ptr[i] >> 4];
+    }
+    buffer[sizewords * 2] = '\0';
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_open(char* filename)
+{
+    if( !tbdump_mutex ) tbdump_mutex = kos_mutex_create( "TBDUMP_MUTEX" );
+
+    kos_memset( &g_tb, 0, sizeof( g_tb ) );
+
+    g_tb.file = kos_fopen( filename, "wt" );
+
+    tbdump_printinfo("reset");
+    tbdump_printline("0");
+    tbdump_printline("1 00000000 00000eff");
+
+    /* Enable interrupts */
+    tbdump_printline("1 00000000 00000003");
+}
+
+void tbdump_close()
+{
+    TBDUMP_MUTEX_LOCK();
+
+    kos_fclose( g_tb.file );
+    g_tb.file = 0;
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    if( tbdump_mutex ) kos_mutex_free( tbdump_mutex );
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes)
+{
+    /* Align starting address and size */
+    unsigned int beg = addr;
+    unsigned int end = addr+sizebytes;
+    char buffer[65];
+
+    TBDUMP_MUTEX_LOCK();
+
+    beg = (beg+15) & ~15;
+    end &= ~15;
+
+    if( sizebytes <= 16 )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, sizebytes, buffer);
+
+        TBDUMP_MUTEX_UNLOCK();
+        return;
+    }
+
+    /* Handle unaligned start */
+    if( beg != addr )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, beg-addr, buffer);
+
+        src += beg-addr;
+    }
+
+    /* Dump the memory writes */
+    while( beg < end )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("2 %08x %s", beg, buffer);
+
+        beg += 16;
+        src += 16;
+    }
+
+    /* Handle unaligned end */
+    if( end != addr+sizebytes )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", end, (addr+sizebytes)-end, buffer);
+    }
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("19 %08x 4 %i %032x", addr, (sizebytes+3)/4, value );
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_slavewrite(unsigned int addr, unsigned int value)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("1 %08x %08x", addr, value);
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+
+KGSL_API int
+kgsl_tbdump_waitirq()
+{
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printinfo("wait irq");
+    tbdump_printline("10");
+
+    /* ACK IRQ */
+    tbdump_printline("1 00000418 00000003");
+    tbdump_printline("18 00000018 00000000 # slave read & assert");
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+KGSL_API int
+kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height)
+{
+    static char filename[20];
+    static int numframe = 0;
+
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+    #pragma warning(disable:4996)
+    sprintf( filename, "tbdump_%08d.bmp", numframe++ );
+
+    tbdump_printline("13 %s %d %08x %d %d %d 0", filename, format, (unsigned int)addr, stride, width, height);
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+#endif /* TBDUMP */
diff --git a/drivers/mxc/amd-gpu/common/gsl_yamato.c b/drivers/mxc/amd-gpu/common/gsl_yamato.c
new file mode 100644
index 000000000000..d74c9efe2f36
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_yamato.c
@@ -0,0 +1,886 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+#include "gsl_ringbuffer.h"
+#include "gsl_drawctxt.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kgsl_yamato_gmeminit(gsl_device_t *device)
+{
+    rb_edram_info_u rb_edram_info = {0};
+    unsigned int    gmem_size;
+    unsigned int    edram_value = 0;
+
+    // make sure edram range is aligned to size
+    KOS_ASSERT((device->gmemspace.gpu_base  & (device->gmemspace.sizebytes - 1)) == 0);
+
+    // get edram_size value equivalent
+    gmem_size = (device->gmemspace.sizebytes >> 14);
+    while (gmem_size >>= 1)
+    {
+       edram_value++;
+    }
+
+    rb_edram_info.f.edram_size         = edram_value;
+    rb_edram_info.f.edram_mapping_mode = 0;                                     // EDRAM_MAP_UPPER
+    rb_edram_info.f.edram_range        = (device->gmemspace.gpu_base >> 14);    // must be aligned to size
+
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, (unsigned int)rb_edram_info.val);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_yamato_gmemclose(gsl_device_t *device)
+{
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, 0x00000000);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_rbbmintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_RBBM_READ_ERROR:
+
+            device->ftbl.device_destroy(device);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_RBBM_DISPLAY_UPDATE:
+        case GSL_INTR_YDX_RBBM_GUI_IDLE:
+
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_cpintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+#ifndef _LINUX		
+              kos_event_signal(device->timestamp_event);
+#else
+			  wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+            break;
+        default:
+            break;
+    }
+}
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_sqintrcallback(gsl_intrid_t id, void *cookie)
+{
+    (void) cookie;      // unreferenced formal parameter
+	/*gsl_device_t  *device = (gsl_device_t *) cookie;*/
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_SQ_PS_WATCHDOG:
+        case GSL_INTR_YDX_SQ_VS_WATCHDOG:
+
+			// todo: take appropriate action
+
+			break;
+
+		default:
+
+			break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+static int
+kgsl_yamato_bist(gsl_device_t *device)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  link[2];
+
+    if (!(device->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    status = kgsl_ringbuffer_bist(&device->ringbuffer);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    // interrupt bist
+    link[0] = pm4_type3_packet(PM4_INTERRUPT, 1);
+    link[1] = CP_INT_CNTL__RB_INT_MASK;
+	kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, GSL_CALLER_PROCESSID_GET());
+
+    status = kgsl_mmu_bist(&device->mmu);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    return (status);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_isr(gsl_device_t *device)
+{
+    unsigned int            status;
+#ifdef _DEBUG
+    mh_mmu_page_fault_u     page_fault        = {0};
+    mh_axi_error_u          axi_error         = {0};
+    mh_clnt_axi_id_reuse_u  clnt_axi_id_reuse = {0};
+    rbbm_read_error_u       read_error        = {0};
+#endif // DEBUG
+
+    // determine if yamato is interrupting, and if so, which block
+    device->ftbl.device_regread(device, mmMASTER_INT_SIGNAL, &status);
+
+    if (status & MASTER_INT_SIGNAL__MH_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain mh error information
+        device->ftbl.device_regread(device, mmMH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+        device->ftbl.device_regread(device, mmMH_AXI_ERROR, (unsigned int *)&axi_error);
+        device->ftbl.device_regread(device, mmMH_CLNT_AXI_ID_REUSE, (unsigned int *)&clnt_axi_id_reuse);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_MH);
+    }
+
+    if (status & MASTER_INT_SIGNAL__CP_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_CP);
+    }
+
+    if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain rbbm error information
+        device->ftbl.device_regread(device, mmRBBM_READ_ERROR, (unsigned int *)&read_error);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_RBBM);
+    }
+
+    if (status & MASTER_INT_SIGNAL__SQ_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_SQ);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+	unsigned int		 link[2];
+    mh_mmu_invalidate_u  mh_mmu_invalidate = {0};
+
+    mh_mmu_invalidate.f.invalidate_all = 1;
+    mh_mmu_invalidate.f.invalidate_tc  = 1;
+
+	// if possible, invalidate via command stream, otherwise via direct register writes
+	if (device->flags & GSL_FLAGS_STARTED)
+	{
+		link[0] = pm4_type0_packet(reg_invalidate, 1);
+		link[1] = mh_mmu_invalidate.val;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, pid);
+	}
+	else
+	{
+
+        device->ftbl.device_regwrite(device, reg_invalidate, mh_mmu_invalidate.val);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	unsigned int  link[25];
+
+    // if there is an active draw context, set via command stream,
+	if (device->flags & GSL_FLAGS_STARTED)
+    {
+        // wait for graphics pipe to be idle
+        link[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        link[1] = 0x00000000;
+
+        // set page table base
+        link[2] = pm4_type0_packet(reg_ptbase, 1);
+		link[3] = ptbase;
+
+        // HW workaround: to resolve MMU page fault interrupts caused by the VGT. It prevents 
+		// the CP PFP from filling the VGT DMA request fifo too early, thereby ensuring that 
+		// the VGT will not fetch vertex/bin data until after the page table base register 
+		// has been updated.
+		//
+		// Two null DRAW_INDX_BIN packets are inserted right after the page table base update, 
+		// followed by a wait for idle. The null packets will fill up the VGT DMA request 
+		// fifo and prevent any further vertex/bin updates from occurring until the wait 
+		// has finished.
+		link[4]  = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+		link[5]  = (0x4 << 16) | (mmPA_SU_SC_MODE_CNTL - 0x2000);
+		link[6]  = 0;          // disable faceness generation
+		link[7]  = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
+		link[8]  = device->mmu.dummyspace.gpuaddr;
+		link[9]  = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[10] = 0;          // viz query info
+		link[11] = 0x0003C004; // draw indicator
+		link[12] = 0;          // bin base
+		link[13] = 3;          // bin size
+		link[14] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[15] = 6;          // dma size
+		link[16] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[17] = 0;          // viz query info
+		link[18] = 0x0003C004; // draw indicator
+		link[19] = 0;          // bin base
+		link[20] = 3;          // bin size
+		link[21] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[22] = 6;          // dma size
+		link[23] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+		link[24] = 0x00000000;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 25, pid);
+	}
+	else
+	{
+		device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+		device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE;
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    //We need to make sure all blocks are powered up and clocked before
+    //issuing a soft reset.  The overrides will be turned off (set to 0)
+    //later in kgsl_yamato_start.
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+
+    // soft reset
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0xFFFFFFFF);
+    kos_sleep(50);
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0x00000000);
+
+    // RBBM control
+    device->ftbl.device_regwrite(device, mmRBBM_CNTL, 0x00004442);
+
+    // setup MH arbiter
+    device->ftbl.device_regwrite(device, mmMH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_yamato_mharb);
+
+    // SQ_*_PROGRAM
+    device->ftbl.device_regwrite(device, mmSQ_VS_PROGRAM, 0x00000000);
+    device->ftbl.device_regwrite(device, mmSQ_PS_PROGRAM, 0x00000000);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    return(status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_close(gsl_device_t *device)
+{
+    if (device->refcnt == 0)
+    {
+        // shutdown mmu
+        kgsl_mmu_close(device);
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    // todo: - hard reset core?
+
+    kgsl_drawctxt_destroyall(device);
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  pm1, pm2;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPFBSTART(device));
+
+    (void) flags;      // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // default power management override when running in safe mode
+    pm1 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0xFFFFFFFE : 0x00000000;
+    pm2 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0x000000FF : 0x00000000;
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, pm1);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, pm2);
+
+    // enable rbbm interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+	kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_yamato_cpintrcallback, (void *) device);    
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+
+    // enable sq interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    // init gmem
+    kgsl_yamato_gmeminit(device);
+
+    // init ring buffer
+    status = kgsl_ringbuffer_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init draw context
+    status = kgsl_drawctxt_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_BIST, kgsl_yamato_bist(device));
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_stop(gsl_device_t *device)
+{
+    // disable rbbm interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+    // disable sq interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    kgsl_drawctxt_close(device);
+
+    // shutdown ringbuffer
+    kgsl_ringbuffer_close(&device->ringbuffer);
+
+    // shutdown gmem
+    kgsl_yamato_gmemclose(device);
+
+    if(device->refcnt == 0)
+    {
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    }
+
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id         = device->id;
+        devinfo->chip_id           = (gsl_chipid_t)device->chip_id;
+        devinfo->mmu_enabled       = kgsl_mmu_isenabled(&device->mmu);
+        devinfo->gmem_hostbaseaddr = device->gmemspace.mmio_virt_base;
+        devinfo->gmem_gpubaseaddr  = device->gmemspace.gpu_base;
+        devinfo->gmem_sizebytes    = device->gmemspace.sizebytes;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;           // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            if (power->flags & GSL_PWRFLAGS_OVERRIDE_ON)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+            }
+            else if (power->flags & GSL_PWRFLAGS_OVERRIDE_OFF)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0x00000000);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0x00000000);
+            }
+            else
+            {
+                kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+            }
+        }
+
+        status = GSL_SUCCESS;
+    }
+    else if (type == GSL_PROP_DEVICE_DMI)
+    {
+        gsl_dmiprop_t  *dmi = (gsl_dmiprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_dmiprop_t));
+
+        //
+        //  In order to enable DMI, it must not already be enabled.
+        //
+        switch (dmi->flags)
+        {
+            case GSL_DMIFLAGS_ENABLE_SINGLE:
+            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                if (!gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_TRUE;
+                    gsl_driver.dmi_mode  = dmi->flags;
+                    gsl_driver.dmi_frame = -1;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_DISABLE:
+                //
+                //  To disable, we must be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_FALSE;
+                    gsl_driver.dmi_mode  = -1;
+                    gsl_driver.dmi_frame = -2;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_NEXT_BUFFER:
+                //
+                //  Going to the next buffer is dependent upon what mod we are in with respect to single, double, or triple buffering.
+                //  DMI must also be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    unsigned int    cmdbuf[10];
+                    unsigned int    *cmds = &cmdbuf[0];
+                    int             size;
+
+                    if (gsl_driver.dmi_frame == -1)
+                    {
+                        size = 8;
+
+                        *cmds++ =  pm4_type0_packet(mmRBBM_DSPLY, 1);
+                        switch (gsl_driver.dmi_mode)
+                        {
+                            case GSL_DMIFLAGS_ENABLE_SINGLE:
+                                gsl_driver.dmi_max_frame = 1;
+                                *cmds++ = 0x041000410;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                                gsl_driver.dmi_max_frame = 2;
+                                *cmds++ = 0x041000510;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_TRIPLE:
+                                gsl_driver.dmi_max_frame = 3;
+                                *cmds++ = 0x041000610;
+                                break;
+                        }
+                    }
+                    else
+                    {
+                        size = 6;
+                    }
+
+
+                    //
+                    //  Wait for 3D core to be idle and wait for vsync
+                    //
+                    *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                    *cmds++ = 0x00008000;           //  3d idle
+                    // *cmds++ = 0x00008008;         //  3d idle & vsync
+
+                    //
+                    //  Update the render latest register.
+                    //
+                    *cmds++ =  pm4_type0_packet(mmRBBM_RENDER_LATEST, 1);
+                    switch (gsl_driver.dmi_frame)
+                    {
+                        case 0:
+                            //
+                            //  Render frame 0
+                            //
+                            *cmds++ = 0;
+                            //
+                            //  Wait for our max frame # indicator to be de-asserted
+                            //
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000008 << gsl_driver.dmi_max_frame;
+                            gsl_driver.dmi_frame = 1;
+                            break;
+                        case -1:
+                        case 1:
+                            //
+                            //  Render frame 1
+                            //
+                            *cmds++ = 1;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000010;   //  Wait for frame 0 to be deasserted
+                            gsl_driver.dmi_frame = 2;
+                            break;
+                        case 2:
+                            //
+                            //  Render frame 2
+                            //
+                            *cmds++ = 2;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000020;   //  Wait for frame 1 to be deasserted
+                            gsl_driver.dmi_frame = 0;
+                            break;
+                    }
+                    
+                    // issue the commands
+                    kgsl_ringbuffer_issuecmds(device, 1, &cmdbuf[0], size, GSL_CALLER_PROCESSID_GET());
+
+                    gsl_driver.dmi_frame %= gsl_driver.dmi_max_frame;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            default:
+                status = GSL_FAILURE;
+                break;
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_idle(gsl_device_t *device, unsigned int timeout)
+{
+    int               status  = GSL_FAILURE;
+    gsl_ringbuffer_t  *rb     = &device->ringbuffer;
+    rbbm_status_u     rbbm_status;
+
+    (void) timeout;      // unreferenced formal parameter
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_REGPOLL, device->id, mmRBBM_STATUS, 0x80000000, "kgsl_yamato_idle"));
+
+    // first, wait until the CP has consumed all the commands in the ring buffer
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        do
+        {
+            GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        } while (rb->rptr != rb->wptr);
+    }
+
+    // now, wait for the GPU to finish its operations
+    for ( ; ; )
+    {
+        device->ftbl.device_regread(device, mmRBBM_STATUS, (unsigned int *)&rbbm_status);
+
+        if (!(rbbm_status.val & 0x80000000))
+        {
+            status = GSL_SUCCESS;
+            break;
+        }
+
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+            {
+                if (!(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX_WITHOUT_IFH))
+                {
+                    if(offsetwords == mmCP_RB_RPTR || offsetwords == mmCP_RB_WPTR)
+                    {
+                        *value = device->ringbuffer.wptr;
+                        return (GSL_SUCCESS);
+                    }
+                }
+            });
+
+    GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPREGWRITE(offsetwords, value));
+
+    GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+
+    if (intr_id == GSL_INTR_YDX_CP_IB1_INT || intr_id == GSL_INTR_YDX_CP_IB2_INT ||
+        intr_id == GSL_INTR_YDX_CP_SW_INT  || intr_id == GSL_INTR_YDX_RBBM_DISPLAY_UPDATE)
+    {
+        if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+        {
+            // wait until intr completion event is received
+            if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS)
+            {
+                *count = 1;
+                status = GSL_SUCCESS;
+            }
+            else
+            {
+                status = GSL_FAILURE_TIMEOUT;
+            }
+        }
+    }
+
+    return (status);
+}
+
+int
+kgsl_yamato_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+	                                              kgsl_cmdstream_check_timestamp(device->id, timestamp),
+												  msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+#else
+	return (GSL_SUCCESS);
+#endif
+}
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_runpending(gsl_device_t *device)
+{
+    (void) device;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_yamato_init;
+    ftbl->device_close          = kgsl_yamato_close;
+    ftbl->device_destroy        = kgsl_yamato_destroy;
+    ftbl->device_start          = kgsl_yamato_start;
+    ftbl->device_stop           = kgsl_yamato_stop;
+    ftbl->device_getproperty    = kgsl_yamato_getproperty;
+    ftbl->device_setproperty    = kgsl_yamato_setproperty;
+    ftbl->device_idle           = kgsl_yamato_idle;
+	ftbl->device_waittimestamp  = kgsl_yamato_waittimestamp;
+    ftbl->device_regread        = kgsl_yamato_regread;
+    ftbl->device_regwrite       = kgsl_yamato_regwrite;
+    ftbl->device_waitirq        = kgsl_yamato_waitirq;
+    ftbl->device_runpending     = kgsl_yamato_runpending;
+    ftbl->intr_isr              = kgsl_yamato_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_yamato_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_yamato_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_ringbuffer_issueibcmds;
+    ftbl->context_create        = kgsl_drawctxt_create;
+    ftbl->context_destroy       = kgsl_drawctxt_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
new file mode 100644
index 000000000000..dfe61295e9ef
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
@@ -0,0 +1,327 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef PFP_MICROCODE_NRT_H
+#define PFP_MICROCODE_NRT_H
+
+#define PFP_MICROCODE_VERSION 308308
+
+#define PFP_MICROCODE_SIZE_NRT 288
+
+uint32 aPFP_Microcode_nrt[PFP_MICROCODE_SIZE_NRT]={
+0xc60400,
+0x7e424b,
+0xa00000,
+0x7e828b,
+0x800001,
+0xc60400,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xc62c00,
+0xc80c35,
+0x98c000,
+0xc80c35,
+0x880000,
+0xc80c1d,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc61000,
+0x978003,
+0xcc4003,
+0xd60004,
+0x800000,
+0xcd0003,
+0x9783e8,
+0xc60400,
+0x800000,
+0xc60400,
+0x84000b,
+0xc60800,
+0x98c00c,
+0xc61000,
+0xcc4003,
+0xc61400,
+0xc61800,
+0x7d6d40,
+0xcd401e,
+0x978003,
+0xcd801e,
+0xd60004,
+0x800000,
+0xcd0003,
+0x800000,
+0xd6001f,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc60c00,
+0xcc4003,
+0xcc8003,
+0xccc003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0xc60800,
+0x348c08,
+0x98c006,
+0xc80c1e,
+0x98c000,
+0xc80c1e,
+0x800041,
+0xcc8007,
+0xcc8008,
+0xcc4003,
+0x800000,
+0xcc8003,
+0xc60400,
+0x1a9c07,
+0xca8821,
+0x95c3b9,
+0xc8102c,
+0x98800a,
+0x329418,
+0x9a4004,
+0xcc6810,
+0x042401,
+0xd00143,
+0xd00162,
+0xcd0002,
+0x7d514c,
+0xcd4003,
+0x9b8007,
+0x06a801,
+0x964003,
+0xc28000,
+0xcf4003,
+0x800001,
+0xc60400,
+0x800045,
+0xc60400,
+0x800001,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc8102d,
+0x349402,
+0x99000b,
+0xc8182e,
+0xcd4002,
+0xcd8002,
+0xd001e3,
+0xd001c3,
+0xccc003,
+0xcc801c,
+0xcd801d,
+0x800001,
+0xc60400,
+0xd00203,
+0x800000,
+0xd001c3,
+0xc8081f,
+0xc60c00,
+0xc80c20,
+0x988000,
+0xc8081f,
+0xcc4003,
+0xccc003,
+0xd60003,
+0xccc022,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xc81c2f,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc81030,
+0x99c000,
+0xc81c2f,
+0xcc8021,
+0xcc4020,
+0x990011,
+0xc107ff,
+0xd00223,
+0xd00243,
+0x345402,
+0x7cb18b,
+0x7d95cc,
+0xcdc002,
+0xccc002,
+0xd00263,
+0x978005,
+0xccc003,
+0xc60800,
+0x80008a,
+0xc60c00,
+0x800000,
+0xd00283,
+0x97836b,
+0xc60400,
+0xd6001f,
+0x800001,
+0xc60400,
+0xd2000d,
+0xcc000d,
+0x800000,
+0xcc000d,
+0xc60800,
+0xc60c00,
+0xca1433,
+0xd022a0,
+0xcce000,
+0x99435c,
+0xcce005,
+0x800000,
+0x062001,
+0xc60800,
+0xc60c00,
+0xd202c3,
+0xcc8003,
+0xccc003,
+0xcce027,
+0x800000,
+0x062001,
+0xca0831,
+0x9883ff,
+0xca0831,
+0xd6001f,
+0x800001,
+0xc60400,
+0x0a2001,
+0x800001,
+0xc60400,
+0xd20009,
+0xd2000a,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xd2000b,
+0xd2000c,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xcc0023,
+0xcc4003,
+0xce0003,
+0x800000,
+0xd60003,
+0xd00303,
+0xcc0024,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00323,
+0xcc0025,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00343,
+0xcc0026,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0x280401,
+0xd20001,
+0xcc4001,
+0xcc4006,
+0x8400e7,
+0xc40802,
+0xc40c02,
+0xcc402b,
+0x98831f,
+0xc63800,
+0x8400e7,
+0xcf802b,
+0x800000,
+0xd6001f,
+0xcc001f,
+0x880000,
+0xcc001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x0100c8,
+0x0200cd,
+0x0300d2,
+0x050004,
+0x1000d7,
+0x1700b6,
+0x220010,
+0x230038,
+0x250044,
+0x27005e,
+0x2d0070,
+0x2e007c,
+0x4b0009,
+0x34001d,
+0x36002d,
+0x3700a8,
+0x3b009b,
+0x3f009f,
+0x4400d9,
+0x4800c3,
+0x5000b9,
+0x5100be,
+0x5500c9,
+0x5600ce,
+0x5700d3,
+0x5d00b0,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
new file mode 100644
index 000000000000..03f6f4cd35e4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
@@ -0,0 +1,815 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef PM4_MICROCODE_H
+#define PM4_MICROCODE_H
+
+#define PM4_MICROCODE_VERSION 300684
+
+#define PM4_MICROCODE_SIZE 768
+
+
+#ifdef _PRIMLIB_INCLUDE
+extern uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3];
+#else
+uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x004 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x34e00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000000, 0x00294582, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0284620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404803, 0x021 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x0000a1fd, 0x0029462c, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x021 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00001000, 0x00281223, 0x000 },
+    { 0x00001000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x0000000e, 0x00404811, 0x000 },
+    { 0x00000394, 0x00204411, 0x000 },
+    { 0x00000001, 0xc0404811, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000008, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x14e00000, 0x02d },
+    { 0x00000007, 0x00404811, 0x000 },
+    { 0x00000008, 0x00404811, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x051 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x060 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0xc0404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000000, 0x00400000, 0x051 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x00000612, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000600, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000605, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x0000060a, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0xc0680a20, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00001fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x2b2 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x06d },
+    { 0x00000000, 0xc0401800, 0x070 },
+    { 0x00001fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x073 },
+    { 0x00000000, 0xc0401c00, 0x076 },
+    { 0x00001fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x2b2 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000010, 0x40210a20, 0x000 },
+    { 0x000000ff, 0x00280a22, 0x000 },
+    { 0x000007ff, 0x40280e20, 0x000 },
+    { 0x00000002, 0x00221e23, 0x000 },
+    { 0x00000005, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x084 },
+    { 0xa100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x088 },
+    { 0x00000000, 0x0020162d, 0x000 },
+    { 0x00004000, 0x00500e23, 0x097 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x08c },
+    { 0x00000001, 0x0020162d, 0x000 },
+    { 0x00004800, 0x00500e23, 0x097 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x090 },
+    { 0x00000003, 0x0020162d, 0x000 },
+    { 0x00004900, 0x00500e23, 0x097 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x094 },
+    { 0x00000002, 0x0020162d, 0x000 },
+    { 0x00004908, 0x00500e23, 0x097 },
+    { 0x00000012, 0x0020162d, 0x000 },
+    { 0x00002000, 0x00300e23, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x00000000, 0x00294483, 0x000 },
+    { 0x00000000, 0x40201800, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x9300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404806, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x0000001f, 0x00211a25, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000007ff, 0x00280e25, 0x000 },
+    { 0x00000010, 0x00211225, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ae },
+    { 0x00000000, 0x00203622, 0x000 },
+    { 0x00004000, 0x00504a23, 0x0bd },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b2 },
+    { 0x00000001, 0x00203622, 0x000 },
+    { 0x00004800, 0x00504a23, 0x0bd },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b6 },
+    { 0x00000003, 0x00203622, 0x000 },
+    { 0x00004900, 0x00504a23, 0x0bd },
+    { 0x00000003, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ba },
+    { 0x00000002, 0x00203622, 0x000 },
+    { 0x00004908, 0x00504a23, 0x0bd },
+    { 0x00000012, 0x00203622, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x00002000, 0x00304a23, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x0a4 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040578, 0x00604411, 0x2b2 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0cd },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x00000010, 0x00280a23, 0x000 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x00400000, 0x0d6 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000007, 0x00280a23, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0dd },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x04e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e2 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x02e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e7 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ec },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000005, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f1 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x08e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x000 },
+    { 0x00000008, 0x00210a23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x11b },
+    { 0x00000000, 0xc0204400, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x102 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x0cd },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x107 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x113 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00404810, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00007fff, 0x00281a22, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00200c10, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x80000000, 0x00281a22, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x132 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00300c67, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000001ea, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x13b },
+    { 0x9e00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x13e },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0080480b, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0xe0000000, 0xc0484a20, 0x000 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00493a2e, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000001, 0x00303e2f, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x172 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x175 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000009, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x17d },
+    { 0x00000000, 0x00600000, 0x2af },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x180 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x183 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000002, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x18d },
+    { 0x00000004, 0xc0203620, 0x000 },
+    { 0x00000005, 0xc0203620, 0x000 },
+    { 0x00000006, 0xc0203620, 0x000 },
+    { 0x00000007, 0xc0203620, 0x000 },
+    { 0x00000008, 0xc0203620, 0x000 },
+    { 0x00000009, 0xc0203620, 0x000 },
+    { 0x0000000a, 0xc0203620, 0x000 },
+    { 0x0000000b, 0xc0203620, 0x000 },
+    { 0x00000003, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b5 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00293a2e, 0x000 },
+    { 0x00000004, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1bd },
+    { 0xa300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x0000000a, 0xc0220e20, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x000021f4, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00614a2c, 0x2af },
+    { 0x00000005, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c0 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000006, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c6 },
+    { 0x9c00ffff, 0x00204411, 0x000 },
+    { 0x0000001f, 0x40214a20, 0x000 },
+    { 0x9600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000007, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1d0 },
+    { 0x3fffffff, 0x00283a2e, 0x000 },
+    { 0xc0000000, 0x40280e20, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x18000000, 0x40280e20, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0202c00, 0x000 },
+    { 0x00000000, 0x0020480b, 0x000 },
+    { 0x00000008, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1dc },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000015, 0x00203623, 0x000 },
+    { 0x00000002, 0x40221220, 0x000 },
+    { 0x00000000, 0x00301083, 0x000 },
+    { 0x00000014, 0x00203624, 0x000 },
+    { 0x00000003, 0xc0210e20, 0x000 },
+    { 0x10000000, 0x00280e23, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000003ff, 0x00280e22, 0x000 },
+    { 0x00000018, 0x00211222, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x0020108d, 0x000 },
+    { 0x00002000, 0x00291224, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294984, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x1de },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00003fff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x1fb },
+    { 0x00000000, 0x2ae00000, 0x205 },
+    { 0x20000080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000000, 0x00401c0c, 0x1f9 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000000, 0x00404811, 0x205 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x23a },
+    { 0x00000000, 0x28e00000, 0x205 },
+    { 0x00800080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x202 },
+    { 0x00000000, 0x00401c0c, 0x203 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x20c },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000000c, 0x0020162d, 0x000 },
+    { 0x0000000d, 0x00201a2d, 0x000 },
+    { 0xffdfffff, 0x00483a2e, 0x210 },
+    { 0x00000004, 0x00204811, 0x000 },
+    { 0x0000000e, 0x0020162d, 0x000 },
+    { 0x0000000f, 0x00201a2d, 0x000 },
+    { 0xffefffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x002f0067, 0x000 },
+    { 0x00000000, 0x04e00000, 0x205 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x8900ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00601010, 0x28c },
+    { 0x0000000c, 0x00221e24, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x22d },
+    { 0x20000000, 0x00293a2e, 0x000 },
+    { 0x000021f7, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000d, 0x00203630, 0x000 },
+    { 0x9100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x23000000, 0x000 },
+    { 0x8d00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x00800000, 0x00293a2e, 0x000 },
+    { 0x000021f6, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000e, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000f, 0x00203630, 0x000 },
+    { 0x9200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x25000000, 0x000 },
+    { 0x8e00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00304a24, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000003, 0x40280a20, 0x000 },
+    { 0xffffffe0, 0xc0280e20, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24a },
+    { 0x000021f6, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00494624, 0x24c },
+    { 0x000021f7, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00294624, 0x000 },
+    { 0x00000000, 0x00600000, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000000, 0x00481630, 0x258 },
+    { 0x00000fff, 0x00281630, 0x000 },
+    { 0x0000000c, 0x00211a30, 0x000 },
+    { 0x00000fff, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00040d02, 0x00604411, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x25d },
+    { 0x00000010, 0x00211e30, 0x000 },
+    { 0x00000fff, 0x00482630, 0x267 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x261 },
+    { 0x00000fff, 0x00281e30, 0x000 },
+    { 0x00000200, 0x00402411, 0x267 },
+    { 0x00000000, 0x00281e30, 0x000 },
+    { 0x00000010, 0x00212630, 0x000 },
+    { 0x00000010, 0x00211a30, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000003, 0x00381625, 0x000 },
+    { 0x00000003, 0x00381a26, 0x000 },
+    { 0x00000003, 0x00381e27, 0x000 },
+    { 0x00000003, 0x00382629, 0x000 },
+    { 0x00005000, 0x00302629, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00005000, 0x00302225, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00202810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00200810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x002f0128, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x282 },
+    { 0x00005000, 0x00302227, 0x000 },
+    { 0x0000000c, 0x00300e23, 0x000 },
+    { 0x00000003, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x270 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x04000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x289 },
+    { 0x00000000, 0xc0600000, 0x28c },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x0ec00000, 0x28e },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x00000000, 0x0020280c, 0x000 },
+    { 0x00000011, 0x0020262d, 0x000 },
+    { 0x00000000, 0x002f012c, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x295 },
+    { 0x00000000, 0x00403011, 0x296 },
+    { 0x00000400, 0x0030322c, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x0000000a, 0x0021262c, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0x00000000, 0x14c00000, 0x29d },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x299 },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000021f4, 0x0029462c, 0x000 },
+    { 0x0000000a, 0x00214a2a, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0xdf7fffff, 0x00283a2e, 0x000 },
+    { 0x00000010, 0x0080362a, 0x000 },
+    { 0x9700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480c, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00810130, 0x000 },
+    { 0x00000000, 0x00203011, 0x000 },
+    { 0x00000010, 0x0080362c, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x2b2 },
+    { 0x9f00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x2b5 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
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+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
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+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00020143, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x01dd0002, 0x000 },
+    { 0x006301ee, 0x00280012, 0x000 },
+    { 0x00020002, 0x00020026, 0x000 },
+    { 0x00020002, 0x01ec0002, 0x000 },
+    { 0x00790242, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00200012, 0x00020016, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x011b00c5, 0x00020125, 0x000 },
+    { 0x00020141, 0x00020002, 0x000 },
+    { 0x00c50002, 0x0143002e, 0x000 },
+    { 0x00a2016b, 0x00020145, 0x000 },
+    { 0x00020002, 0x01200002, 0x000 },
+    { 0x00020002, 0x010f0103, 0x000 },
+    { 0x00090002, 0x000e000e, 0x000 },
+    { 0x0058003d, 0x00600002, 0x000 },
+    { 0x000200c1, 0x0002028a, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x000502b1, 0x00020008, 0x000 },
+};
+
+#endif
+static const uint32 ME_JUMP_TABLE_START = 740;
+static const uint32 ME_JUMP_TABLE_END   = 768;
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
new file mode 100644
index 000000000000..7ec10b0c2556
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
@@ -0,0 +1,86 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+	
+#ifndef __GSL_DISPLAYAPI_H
+#define __GSL_DISPLAYAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLDISPLAY_EXPORTS
+#define DISP_API                    OS_DLLEXPORT
+#else
+#define DISP_API                    OS_DLLIMPORT
+#endif // __GSLDISPLAY_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DISPLAY_PANEL_TOSHIBA_640x480     0
+#define GSL_DISPLAY_PANEL_HITACHI_240x320     1
+#define GSL_DISPLAY_PANEL_DEFAULT             GSL_DISPLAY_PANEL_TOSHIBA_640x480
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef int     gsl_display_id_t;
+typedef int     gsl_surface_id_t;
+
+typedef struct _gsl_displaymode_t {
+    int panel_id;
+    int width;
+    int height;
+    int bpp;
+    int orientation;
+    int frequency;
+} gsl_displaymode_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+DISP_API gsl_display_id_t   gsl_display_open(gsl_devhandle_t devhandle, int panel_id);
+DISP_API int                gsl_display_close(gsl_display_id_t display_id);
+DISP_API int                gsl_display_getcount(void);
+DISP_API int                gsl_display_setmode(gsl_display_id_t display_id, gsl_displaymode_t displaymode);
+DISP_API int                gsl_display_getmode(gsl_display_id_t display_id, gsl_displaymode_t *displaymode);
+DISP_API gsl_surface_id_t   gsl_display_setsurface(gsl_display_id_t display_id, void *buffer);
+DISP_API int                gsl_display_getactivesurface(gsl_display_id_t display_id, void **buffer);
+DISP_API int                gsl_display_flipsurface(gsl_display_id_t display_id, gsl_surface_id_t surface_id);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __GSL_DISPLAYAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
new file mode 100644
index 000000000000..8476f5a95969
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
@@ -0,0 +1,135 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KLIBAPI_H
+#define __GSL_KLIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLLIB_EXPORTS
+#define KGSL_API                    OS_DLLEXPORT
+#else
+#ifdef __KERNEL_MODE__
+#define KGSL_API                    extern
+#else
+#define KGSL_API                    OS_DLLIMPORT
+#endif
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLLIB_NAME            "AMD GSL Kernel Library"
+#define KGSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  library API
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_driver_init(void);
+KGSL_API int                kgsl_driver_close(void);
+KGSL_API int                kgsl_driver_entry(gsl_flags_t flags);
+KGSL_API int                kgsl_driver_exit(void);
+KGSL_API int                kgsl_driver_destroy(unsigned int pid);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_device_stop(gsl_deviceid_t device_id);
+KGSL_API int                kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout);
+KGSL_API int                kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value);
+KGSL_API int                kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value);
+KGSL_API int                kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  command API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+KGSL_API gsl_timestamp_t    kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout);
+KGSL_API int                kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+KGSL_API int                kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp);
+KGSL_API int                kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp);
+
+////////////////////////////////////////////////////////////////////////////
+//  context API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+KGSL_API int                kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id);
+KGSL_API int                kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_free(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+KGSL_API int                kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+KGSL_API int                kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+KGSL_API unsigned int       kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist);
+KGSL_API int                kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+KGSL_API int                kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  interrupt API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API void               kgsl_intr_isr(void);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_tbdump_waitirq(void);
+KGSL_API int                kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_KLIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_libapi.h b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
new file mode 100644
index 000000000000..7a5be862f3ee
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LIBAPI_H
+#define __GSL_LIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLLIB_EXPORTS
+#define GSL_API                 OS_DLLEXPORT
+#else
+#define GSL_API                 OS_DLLIMPORT
+#endif // __GSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSLLIB_NAME            "AMD GSL User Library"
+#define GSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_library_open(gsl_flags_t flags);
+GSL_API int                     gsl_library_close(void);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_devhandle_t         gsl_device_open(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_device_close(gsl_devhandle_t devhandle);
+GSL_API int                     gsl_device_idle(gsl_devhandle_t devhandle, unsigned int timeout);
+GSL_API int                     gsl_device_getcount(void);
+GSL_API int                     gsl_device_getinfo(gsl_devhandle_t devhandle, gsl_devinfo_t *devinfo);
+GSL_API int                     gsl_device_setpowerstate(gsl_devhandle_t devhandle, gsl_flags_t flags);
+GSL_API int                     gsl_device_setdmistate(gsl_devhandle_t devhandle,  gsl_flags_t flags);
+GSL_API int                     gsl_device_waitirq(gsl_devhandle_t devhandle, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+GSL_API int                     gsl_device_waittimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, unsigned int timeout);
+GSL_API int                     gsl_device_addtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t *timestamp);
+
+//////////////////////////////////////////////////////////////////////////////
+//  direct register API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_register_read(gsl_devhandle_t devhandle, unsigned int offsetwords, unsigned int *data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  command API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_cp_issueibcommands(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, gpuaddr_t ibaddr, unsigned int sizewords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+GSL_API gsl_timestamp_t         gsl_cp_readtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_checktimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_freememontimestamp(gsl_devhandle_t devhandle, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_v3_issuecommand(gsl_devhandle_t devhandle, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_ctxthandle_t        gsl_context_create(gsl_devhandle_t devhandle, gsl_context_type_t type, gsl_flags_t flags);
+GSL_API int                     gsl_context_destroy(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle);
+GSL_API int                     gsl_context_bind_gmem_shadow(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_memory_alloc(gsl_deviceid_t device_id, unsigned int sizebytes, gsl_flags_t flags, gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_free(gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write(const gsl_memdesc_t *memdesc, void *src, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write_multiple(const gsl_memdesc_t *memdesc, void *src, unsigned int srcstridebytes, unsigned int dststridebytes, unsigned int blocksizebytes, unsigned int numblocks, unsigned int offsetbytes);
+GSL_API unsigned int            gsl_memory_getlargestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_memory_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+GSL_API int                     gsl_memory_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+GSL_API int                     gsl_memory_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+#ifdef _DIRECT_MAPPED
+GSL_API unsigned int            gsl_sharedmem_gethostaddr(const gsl_memdesc_t *memdesc);
+#endif // _DIRECT_MAPPED
+
+//////////////////////////////////////////////////////////////////////////////
+//  address translation API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_translate_physaddr(void* virtAddr, unsigned int* physAddr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_tbdump_waitirq();
+GSL_API int                     gsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+//////////////////////////////////////////////////////////////////////////////
+//  OS specific APIs - need to go into their own gsl_libapi_platform.h file
+//////////////////////////////////////////////////////////////////////////////
+#ifdef WM7
+GSL_API int                     gsl_kos_wm7_surfobjfromhbitmap(HBITMAP hbitmap, SURFOBJ *surfobj);
+#endif // WM7
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_LIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
new file mode 100644
index 000000000000..891c7b645ad6
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
@@ -0,0 +1,157 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PM4TYPES_H
+#define __GSL_PM4TYPES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet mask
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_PKT_MASK                0xc0000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet types
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_TYPE0_PKT               ((unsigned int)0 << 30)
+#define PM4_TYPE1_PKT               ((unsigned int)1 << 30)
+#define PM4_TYPE2_PKT               ((unsigned int)2 << 30)
+#define PM4_TYPE3_PKT               ((unsigned int)3 << 30)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// type3 packets
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_ME_INIT                 0x48    // initialize CP's micro-engine
+
+#define PM4_NOP                     0x10    // skip N 32-bit words to get to the next packet
+
+#define PM4_INDIRECT_BUFFER         0x3f    // indirect buffer dispatch.  prefetch parser uses this packet type to determine whether to pre-fetch the IB
+#define PM4_INDIRECT_BUFFER_PFD     0x37    // indirect buffer dispatch.  same as IB, but init is pipelined
+
+#define PM4_WAIT_FOR_IDLE           0x26    // wait for the IDLE state of the engine
+#define PM4_WAIT_REG_MEM            0x3c    // wait until a register or memory location is a specific value
+#define PM4_WAIT_REG_EQ             0x52    // wait until a register location is equal to a specific value
+#define PM4_WAT_REG_GTE             0x53    // wait until a register location is >= a specific value
+#define PM4_WAIT_UNTIL_READ         0x5c    // wait until a read completes
+#define PM4_WAIT_IB_PFD_COMPLETE    0x5d    // wait until all base/size writes from an IB_PFD packet have completed
+
+#define PM4_REG_RMW                 0x21    // register read/modify/write
+#define PM4_REG_TO_MEM              0x3e    // reads register in chip and writes to memory
+#define PM4_MEM_WRITE               0x3d    // write N 32-bit words to memory
+#define PM4_MEM_WRITE_CNTR          0x4f    // write CP_PROG_COUNTER value to memory
+#define PM4_COND_EXEC               0x44    // conditional execution of a sequence of packets
+#define PM4_COND_WRITE              0x45    // conditional write to memory or register
+
+#define PM4_EVENT_WRITE             0x46    // generate an event that creates a write to memory when completed
+#define PM4_EVENT_WRITE_SHD         0x58    // generate a VS|PS_done event
+#define PM4_EVENT_WRITE_CFL         0x59    // generate a cache flush done event
+#define PM4_EVENT_WRITE_ZPD         0x5b    // generate a z_pass done event
+
+#define PM4_DRAW_INDX               0x22    // initiate fetch of index buffer and draw
+#define PM4_DRAW_INDX_2             0x36    // draw using supplied indices in packet
+#define PM4_DRAW_INDX_BIN           0x34    // initiate fetch of index buffer and binIDs and draw
+#define PM4_DRAW_INDX_2_BIN         0x35    // initiate fetch of bin IDs and draw using supplied indices
+
+#define PM4_VIZ_QUERY               0x23    // begin/end initiator for viz query extent processing
+#define PM4_SET_STATE               0x25    // fetch state sub-blocks and initiate shader code DMAs
+#define PM4_SET_CONSTANT            0x2d    // load constant into chip and to memory
+#define PM4_IM_LOAD                 0x27    // load sequencer instruction memory (pointer-based)
+#define PM4_IM_LOAD_IMMEDIATE       0x2b    // load sequencer instruction memory (code embedded in packet)
+#define PM4_LOAD_CONSTANT_CONTEXT   0x2e    // load constants from a location in memory
+#define PM4_INVALIDATE_STATE        0x3b    // selective invalidation of state pointers
+
+#define PM4_SET_SHADER_BASES        0x4A    // dynamically changes shader instruction memory partition
+#define PM4_SET_BIN_BASE_OFFSET     0x4B    // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet
+#define PM4_SET_BIN_MASK            0x50    // sets the 64-bit BIN_MASK register in the PFP
+#define PM4_SET_BIN_SELECT          0x51    // sets the 64-bit BIN_SELECT register in the PFP
+
+#define PM4_CONTEXT_UPDATE          0x5e    // updates the current context, if needed
+#define PM4_INTERRUPT               0x40    // generate interrupt from the command stream
+
+#define PM4_IM_STORE                0x2c    // copy sequencer instruction memory to system memory
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet header building macros
+//////////////////////////////////////////////////////////////////////////////
+#define pm4_type0_packet(regindx, cnt)                      (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((regindx) & 0x7FFF))
+#define pm4_type0_packet_for_sameregister(regindx, cnt)     (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((1 << 15) | ((regindx) & 0x7FFF))
+#define pm4_type1_packet(reg0, reg1)                        (PM4_TYPE1_PKT                      | ((reg1) << 12) | (reg0))
+#define pm4_type3_packet(opcode, cnt)                       (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8))
+#define pm4_predicated_type3_packet(opcode, cnt)            (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8) | 0x1))
+#define pm4_nop_packet(cnt)                                 (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (PM4_NOP << 8))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet headers
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_HDR_ME_INIT                 pm4_type3_packet(PM4_ME_INIT, 18)
+#define PM4_HDR_INDIRECT_BUFFER_PFD     pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2)
+#define PM4_HDR_INDIRECT_BUFFER         pm4_type3_packet(PM4_INDIRECT_BUFFER, 2)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -----------------------
+// pm4 type0 packet header
+// -----------------------
+typedef struct __pm4_type0
+{
+    unsigned int       base_index  :15;
+    unsigned int       one_reg_wr  :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type0;
+
+// -----------------------
+// pm4 type2 packet header
+// -----------------------
+typedef struct __pm4_type2
+{
+    unsigned int       reserved    :30;
+    unsigned int       type        :2;
+} pm4_type2;
+
+// -----------------------
+// pm4 type3 packet header
+// -----------------------
+typedef struct __pm4_type3
+{
+    unsigned int       predicate   :1;
+    unsigned int       reserved1   :7;
+    unsigned int       it_opcode   :7;
+    unsigned int       reserved2   :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type3;
+
+#endif  // __GSL_PM4TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_properties.h b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
new file mode 100644
index 000000000000..520761fe3490
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
@@ -0,0 +1,94 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PROPERTIES_H
+#define __GSL_PROPERTIES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// property types
+// --------------
+typedef enum _gsl_property_type_t
+{
+    GSL_PROP_DEVICE_INFO      = 0x00000001,
+    GSL_PROP_DEVICE_SHADOW    = 0x00000002,
+    GSL_PROP_DEVICE_POWER     = 0x00000003,
+    GSL_PROP_SHMEM            = 0x00000004,
+    GSL_PROP_SHMEM_APERTURES  = 0x00000005,
+    GSL_PROP_DEVICE_DMI       = 0x00000006
+} gsl_property_type_t;
+
+// -----------------
+// aperture property
+// -----------------
+typedef struct _gsl_apertureprop_t {
+    unsigned int  gpuaddr;
+    unsigned int  hostaddr;
+} gsl_apertureprop_t;
+
+// --------------
+// shmem property
+// --------------
+typedef struct _gsl_shmemprop_t {
+    int                 numapertures;
+    unsigned int        aperture_mask;
+    unsigned int        aperture_shift;
+    gsl_apertureprop_t  *aperture;
+} gsl_shmemprop_t;
+
+// -----------------------------
+// device shadow memory property
+// -----------------------------
+typedef struct _gsl_shadowprop_t {
+    unsigned int  hostaddr;
+    unsigned int  size;
+    gsl_flags_t   flags;
+} gsl_shadowprop_t;
+
+// ---------------------
+// device power property
+// ---------------------
+typedef struct _gsl_powerprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_powerprop_t;
+
+
+// ---------------------
+// device DMI property
+// ---------------------
+typedef struct _gsl_dmiprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_dmiprop_t;
+
+#endif  // __GSL_PROPERTIES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_types.h b/drivers/mxc/amd-gpu/include/api/gsl_types.h
new file mode 100644
index 000000000000..99f389deee84
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_types.h
@@ -0,0 +1,478 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TYPES_H
+#define __GSL_TYPES_H
+
+#include "stddef.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// status
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SUCCESS                     OS_SUCCESS                  
+#define GSL_FAILURE                     OS_FAILURE                  
+#define GSL_FAILURE_SYSTEMERROR         OS_FAILURE_SYSTEMERROR      
+#define GSL_FAILURE_DEVICEERROR         OS_FAILURE_DEVICEERROR  
+#define GSL_FAILURE_OUTOFMEM            OS_FAILURE_OUTOFMEM         
+#define GSL_FAILURE_BADPARAM            OS_FAILURE_BADPARAM         
+#define GSL_FAILURE_OFFSETINVALID       OS_FAILURE_OFFSETINVALID
+#define GSL_FAILURE_NOTSUPPORTED        OS_FAILURE_NOTSUPPORTED     
+#define GSL_FAILURE_NOMOREAVAILABLE     OS_FAILURE_NOMOREAVAILABLE  
+#define GSL_FAILURE_NOTINITIALIZED      OS_FAILURE_NOTINITIALIZED 
+#define GSL_FAILURE_ALREADYINITIALIZED  OS_FAILURE_ALREADYINITIALIZED
+#define GSL_FAILURE_TIMEOUT             OS_FAILURE_TIMEOUT
+
+
+//////////////////////////////////////////////////////////////////////////////
+// memory allocation flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMFLAGS_ANY                0x00000000      // dont care
+
+#define GSL_MEMFLAGS_CHANNELANY         0x00000000
+#define GSL_MEMFLAGS_CHANNEL1           0x00000000
+#define GSL_MEMFLAGS_CHANNEL2           0x00000001
+#define GSL_MEMFLAGS_CHANNEL3           0x00000002
+#define GSL_MEMFLAGS_CHANNEL4           0x00000003
+                                        
+#define GSL_MEMFLAGS_BANKANY            0x00000000
+#define GSL_MEMFLAGS_BANK1              0x00000010
+#define GSL_MEMFLAGS_BANK2              0x00000020
+#define GSL_MEMFLAGS_BANK3              0x00000040
+#define GSL_MEMFLAGS_BANK4              0x00000080
+                                        
+#define GSL_MEMFLAGS_DIRANY             0x00000000
+#define GSL_MEMFLAGS_DIRTOP             0x00000100
+#define GSL_MEMFLAGS_DIRBOT             0x00000200
+                                        
+#define GSL_MEMFLAGS_APERTUREANY        0x00000000
+#define GSL_MEMFLAGS_EMEM               0x00000000
+#define GSL_MEMFLAGS_CONPHYS            0x00001000
+                                        
+#define GSL_MEMFLAGS_ALIGNANY           0x00000000      // minimum alignment is 32 bytes 
+#define GSL_MEMFLAGS_ALIGN32            0x00000000
+#define GSL_MEMFLAGS_ALIGN64            0x00060000
+#define GSL_MEMFLAGS_ALIGN128           0x00070000
+#define GSL_MEMFLAGS_ALIGN256           0x00080000
+#define GSL_MEMFLAGS_ALIGN512           0x00090000
+#define GSL_MEMFLAGS_ALIGN1K            0x000A0000
+#define GSL_MEMFLAGS_ALIGN2K            0x000B0000
+#define GSL_MEMFLAGS_ALIGN4K            0x000C0000
+#define GSL_MEMFLAGS_ALIGN8K            0x000D0000
+#define GSL_MEMFLAGS_ALIGN16K           0x000E0000
+#define GSL_MEMFLAGS_ALIGN32K           0x000F0000
+#define GSL_MEMFLAGS_ALIGN64K           0x00100000
+#define GSL_MEMFLAGS_ALIGNPAGE          GSL_MEMFLAGS_ALIGN4K
+
+#define GSL_MEMFLAGS_GPUREADWRITE       0x00000000
+#define GSL_MEMFLAGS_GPUREADONLY        0x01000000
+#define GSL_MEMFLAGS_GPUWRITEONLY       0x02000000
+#define GSL_MEMFLAGS_GPUNOACCESS        0x04000000
+
+#define GSL_MEMFLAGS_FORCEPAGESIZE      0x40000000
+#define GSL_MEMFLAGS_STRICTREQUEST      0x80000000      // fail the alloc if the flags cannot be honored 
+                    
+#define GSL_MEMFLAGS_CHANNEL_MASK       0x0000000F
+#define GSL_MEMFLAGS_BANK_MASK          0x000000F0
+#define GSL_MEMFLAGS_DIR_MASK           0x00000F00
+#define GSL_MEMFLAGS_APERTURE_MASK      0x0000F000
+#define GSL_MEMFLAGS_ALIGN_MASK         0x00FF0000
+#define GSL_MEMFLAGS_GPUAP_MASK         0x0F000000
+
+#define GSL_MEMFLAGS_CHANNEL_SHIFT      0
+#define GSL_MEMFLAGS_BANK_SHIFT         4
+#define GSL_MEMFLAGS_DIR_SHIFT          8
+#define GSL_MEMFLAGS_APERTURE_SHIFT     12
+#define GSL_MEMFLAGS_ALIGN_SHIFT        16
+#define GSL_MEMFLAGS_GPUAP_SHIFT        24
+
+
+//////////////////////////////////////////////////////////////////////////////
+// debug flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DBGFLAGS_ALL                0xFFFFFFFF
+#define GSL_DBGFLAGS_DEVICE             0x00000001
+#define GSL_DBGFLAGS_CTXT               0x00000002
+#define GSL_DBGFLAGS_MEMMGR             0x00000004
+#define GSL_DBGFLAGS_MMU                0x00000008
+#define GSL_DBGFLAGS_POWER              0x00000010
+#define GSL_DBGFLAGS_IRQ                0x00000020
+#define GSL_DBGFLAGS_BIST               0x00000040
+#define GSL_DBGFLAGS_PM4                0x00000080
+#define GSL_DBGFLAGS_PM4MEM             0x00000100
+#define GSL_DBGFLAGS_PM4CHECK           0x00000200
+#define GSL_DBGFLAGS_DUMPX              0x00000400
+#define GSL_DBGFLAGS_DUMPX_WITHOUT_IFH  0x00000800
+#define GSL_DBGFLAGS_IFH                0x00001000
+#define GSL_DBGFLAGS_NULL               0x00002000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// generic flag values
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_FLAGS_NORMALMODE            0x00000000
+#define GSL_FLAGS_SAFEMODE              0x00000001
+#define GSL_FLAGS_INITIALIZED0          0x00000002
+#define GSL_FLAGS_INITIALIZED           0x00000004
+#define GSL_FLAGS_STARTED               0x00000008
+#define GSL_FLAGS_ACTIVE                0x00000010
+#define GSL_FLAGS_RESERVED0             0x00000020
+#define GSL_FLAGS_RESERVED1             0x00000040
+#define GSL_FLAGS_RESERVED2             0x00000080
+
+
+//////////////////////////////////////////////////////////////////////////////
+// power flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PWRFLAGS_POWER_OFF          0x00000001
+#define GSL_PWRFLAGS_POWER_ON           0x00000002
+#define GSL_PWRFLAGS_CLK_ON             0x00000004
+#define GSL_PWRFLAGS_CLK_OFF            0x00000008
+#define GSL_PWRFLAGS_OVERRIDE_ON        0x00000010
+#define GSL_PWRFLAGS_OVERRIDE_OFF       0x00000020
+
+//////////////////////////////////////////////////////////////////////////////
+// DMI flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DMIFLAGS_ENABLE_SINGLE      0x00000001  //  Single buffered DMI
+#define GSL_DMIFLAGS_ENABLE_DOUBLE      0x00000002  //  Double buffered DMI
+#define GSL_DMIFLAGS_ENABLE_TRIPLE      0x00000004  //  Triple buffered DMI
+#define GSL_DMIFLAGS_DISABLE            0x00000008
+#define GSL_DMIFLAGS_NEXT_BUFFER        0x00000010
+
+//////////////////////////////////////////////////////////////////////////////
+// cache flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CACHEFLAGS_CLEAN            0x00000001  /* flush cache          */
+#define GSL_CACHEFLAGS_INVALIDATE       0x00000002  /* invalidate cache     */
+#define GSL_CACHEFLAGS_WRITECLEAN       0x00000004  /* flush write cache    */
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CONTEXT_MAX             20
+#define GSL_CONTEXT_NONE            0
+#define GSL_CONTEXT_SAVE_GMEM       1
+#define GSL_CONTEXT_NO_GMEM_ALLOC   2
+
+
+//////////////////////////////////////////////////////////////////////////////
+// other
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_TIMEOUT_NONE                        0
+#define GSL_TIMEOUT_DEFAULT                     0xFFFFFFFF
+
+#ifdef _LINUX
+#define GSL_PAGESIZE                            PAGE_SIZE
+#define GSL_PAGESIZE_SHIFT                      PAGE_SHIFT
+#else
+#define GSL_PAGESIZE                            0x1000
+#define GSL_PAGESIZE_SHIFT                      12
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+typedef unsigned int        gsl_devhandle_t;
+typedef unsigned int        gsl_ctxthandle_t;
+typedef int                 gsl_timestamp_t;
+typedef unsigned int        gsl_flags_t;
+typedef unsigned int        gpuaddr_t;
+
+// ---------
+// device id
+// ---------
+typedef enum _gsl_deviceid_t
+{
+    GSL_DEVICE_ANY    = 0,
+    GSL_DEVICE_YAMATO = 1,
+    GSL_DEVICE_G12    = 2,
+    GSL_DEVICE_MAX    = 2,
+
+    GSL_DEVICE_FOOBAR = 0x7FFFFFFF
+} gsl_deviceid_t;
+
+// ----------------
+// chip revision id
+// ----------------
+//
+// coreid:8 majorrev:8 minorrev:8 patch:8
+// 
+// coreid = 0x00 = YAMATO_DX
+// coreid = 0x80 = G12
+//
+
+#define COREID(x)   ((((unsigned int)x & 0xFF) << 24))
+#define MAJORID(x)  ((((unsigned int)x & 0xFF) << 16))
+#define MINORID(x)  ((((unsigned int)x & 0xFF) <<  8))
+#define PATCHID(x)  ((((unsigned int)x & 0xFF) <<  0))
+
+typedef enum _gsl_chipid_t
+{
+    GSL_CHIPID_YAMATODX_REV13   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV14   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV20   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV21   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV211  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV22   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x02) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV23   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV231  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV24   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV25   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV251  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x01)),
+    GSL_CHIPID_G12_REV00        = (int)(COREID(0x80) | MAJORID(0x00) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_ERROR            = (int)0xFFFFFFFF
+
+} gsl_chipid_t;
+
+#undef COREID
+#undef MAJORID
+#undef MINORID
+#undef PATCHID
+
+// -----------
+// device info
+// -----------
+typedef struct _gsl_devinfo_t {
+
+    gsl_deviceid_t  device_id;          // ID of this device
+    gsl_chipid_t    chip_id;
+    int             mmu_enabled;        // mmu address translation enabled
+    unsigned int    gmem_gpubaseaddr;
+    void *          gmem_hostbaseaddr;  // if gmem_hostbaseaddr is NULL, we would know its not mapped into mmio space
+    unsigned int    gmem_sizebytes;
+
+} gsl_devinfo_t;
+
+// -------------------
+// device memory store
+// -------------------
+typedef struct _gsl_devmemstore_t {
+    volatile unsigned int  soptimestamp;
+    unsigned int           sbz;
+    volatile unsigned int  eoptimestamp;
+    unsigned int           sbz2;
+} gsl_devmemstore_t;
+
+#define GSL_DEVICE_MEMSTORE_OFFSET(field)       offsetof(gsl_devmemstore_t, field)
+
+// -----------
+// aperture id
+// -----------
+typedef enum _gsl_apertureid_t
+{
+    GSL_APERTURE_EMEM   = (GSL_MEMFLAGS_EMEM),
+    GSL_APERTURE_PHYS   = (GSL_MEMFLAGS_CONPHYS >> GSL_MEMFLAGS_APERTURE_SHIFT),
+    GSL_APERTURE_MMU    = (GSL_APERTURE_EMEM | 0x10000000),
+    GSL_APERTURE_MAX    = 2,
+
+    GSL_APERTURE_FOOBAR = 0x7FFFFFFF
+} gsl_apertureid_t;
+
+// ----------
+// channel id
+// ----------
+typedef enum _gsl_channelid_t
+{
+    GSL_CHANNEL_1      = (GSL_MEMFLAGS_CHANNEL1 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_2      = (GSL_MEMFLAGS_CHANNEL2 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_3      = (GSL_MEMFLAGS_CHANNEL3 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_4      = (GSL_MEMFLAGS_CHANNEL4 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_MAX    = 4,
+
+    GSL_CHANNEL_FOOBAR = 0x7FFFFFFF
+} gsl_channelid_t;
+
+// ----------------------
+// page access permission
+// ----------------------
+typedef enum _gsl_ap_t
+{
+    GSL_AP_NULL   = 0x0,
+    GSL_AP_R      = 0x1,
+    GSL_AP_W      = 0x2,
+    GSL_AP_RW     = 0x3,
+    GSL_AP_X      = 0x4,
+    GSL_AP_RWX    = 0x5,
+    GSL_AP_MAX    = 0x6,
+
+    GSL_AP_FOOBAR = 0x7FFFFFFF
+} gsl_ap_t;
+
+// -------------
+// memory region
+// -------------
+typedef struct _gsl_memregion_t {
+    unsigned char  *mmio_virt_base;
+    unsigned int   mmio_phys_base;
+    gpuaddr_t      gpu_base;
+    unsigned int   sizebytes;
+} gsl_memregion_t;
+
+// ------------------------
+// shared memory allocation
+// ------------------------
+typedef struct _gsl_memdesc_t {
+    void          *hostptr;
+    gpuaddr_t      gpuaddr;
+    int            size;
+    unsigned int   priv;                // private
+    unsigned int   priv2;               // private
+
+} gsl_memdesc_t;
+
+// ---------------------------------
+// physical page scatter/gatter list
+// ---------------------------------
+typedef struct _gsl_scatterlist_t {
+    int           contiguous;       // flag whether pages on the list are physically contiguous
+    unsigned int  num;
+    unsigned int  *pages;
+} gsl_scatterlist_t;
+
+// --------------
+// mem free queue
+// --------------
+//
+// this could be compressed down into the just the memdesc for the node
+//
+typedef struct _gsl_memnode_t {
+    gsl_timestamp_t       timestamp;
+    gsl_memdesc_t         memdesc;
+    unsigned int          pid;
+    struct _gsl_memnode_t *next;
+} gsl_memnode_t;
+
+typedef struct _gsl_memqueue_t {
+    gsl_memnode_t   *head;
+    gsl_memnode_t   *tail;
+} gsl_memqueue_t;
+
+// ------------
+// timestamp id
+// ------------
+typedef enum _gsl_timestamp_type_t
+{
+    GSL_TIMESTAMP_CONSUMED = 1, // start-of-pipeline timestamp
+    GSL_TIMESTAMP_RETIRED  = 2, // end-of-pipeline timestamp
+    GSL_TIMESTAMP_MAX      = 2,
+
+    GSL_TIMESTAMP_FOOBAR   = 0x7FFFFFFF
+} gsl_timestamp_type_t;
+
+// ------------
+// context type
+// ------------
+typedef enum _gsl_context_type_t
+{
+    GSL_CONTEXT_TYPE_GENERIC = 1,
+    GSL_CONTEXT_TYPE_OPENGL  = 2,
+    GSL_CONTEXT_TYPE_OPENVG  = 3,
+
+    GSL_CONTEXT_TYPE_FOOBAR  = 0x7FFFFFFF
+} gsl_context_type_t;
+
+// ---------
+// rectangle
+// ---------
+typedef struct _gsl_rect_t {
+    unsigned int x;
+    unsigned int y;
+    unsigned int width;
+    unsigned int height;
+} gsl_rect_t;
+
+// -----------------------
+// pixel buffer descriptor
+// -----------------------
+typedef struct _gsl_buffer_desc_t {
+    gsl_memdesc_t data;
+    unsigned int stride_bytes;
+    unsigned int bpp;
+    unsigned int enabled;
+} gsl_buffer_desc_t;
+
+// ---------------------
+// command window target
+// ---------------------
+typedef enum _gsl_cmdwindow_t
+{
+    GSL_CMDWINDOW_MIN     = 0x00000000,
+    GSL_CMDWINDOW_2D      = 0x00000000,
+    GSL_CMDWINDOW_3D      = 0x00000001,     // legacy
+    GSL_CMDWINDOW_MMU     = 0x00000002,
+    GSL_CMDWINDOW_ARBITER = 0x000000FF,
+    GSL_CMDWINDOW_MAX     = 0x000000FF,
+
+    GSL_CMDWINDOW_FOOBAR  = 0x7FFFFFFF
+} gsl_cmdwindow_t;
+
+// ------------
+// interrupt id
+// ------------
+typedef enum _gsl_intrid_t
+{
+  GSL_INTR_YDX_MH_AXI_READ_ERROR = 0,
+  GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+  GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_YDX_CP_SW_INT,
+  GSL_INTR_YDX_CP_T0_PACKET_IN_IB,
+  GSL_INTR_YDX_CP_OPCODE_ERROR,
+  GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR,
+  GSL_INTR_YDX_CP_RESERVED_BIT_ERROR,
+  GSL_INTR_YDX_CP_IB_ERROR,
+  GSL_INTR_YDX_CP_IB2_INT,
+  GSL_INTR_YDX_CP_IB1_INT,
+  GSL_INTR_YDX_CP_RING_BUFFER,
+
+  GSL_INTR_YDX_RBBM_READ_ERROR,
+  GSL_INTR_YDX_RBBM_DISPLAY_UPDATE,
+  GSL_INTR_YDX_RBBM_GUI_IDLE,
+
+  GSL_INTR_YDX_SQ_PS_WATCHDOG,
+  GSL_INTR_YDX_SQ_VS_WATCHDOG,
+
+  GSL_INTR_G12_MH,
+  GSL_INTR_G12_G2D,
+  GSL_INTR_G12_FIFO,
+#ifndef _Z180
+  GSL_INTR_G12_FBC,
+#endif // _Z180
+
+  GSL_INTR_G12_MH_AXI_READ_ERROR,
+  GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+  GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_COUNT,
+
+  GSL_INTR_FOOBAR = 0x7FFFFFFF
+} gsl_intrid_t;
+
+#endif  // __GSL_TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_utils.h b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
new file mode 100644
index 000000000000..1078b634173d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_UTILS_H
+#define __GSL_UTILS_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_QUADPOW2_TO_SIZEBYTES(quadpow2)     (8 << (quadpow2))
+#define GSL_QUADPOW2_TO_SIZEDWORDS(quadpow2)    (2 << (quadpow2))
+#define GSL_POW2TEST(size)                      ((size) && !((size) & ((size) - 1)))
+#define GSL_POW2ALIGN_DOWN(addr, alignsize)     ((addr) & ~((alignsize) - 1));
+#define GSL_POW2ALIGN_UP(addr, alignsize)       (((addr) + ((alignsize) - 1)) & ~((alignsize) - 1))
+
+
+#endif  // __GSL_UTILS_H
diff --git a/drivers/mxc/amd-gpu/include/gsl.h b/drivers/mxc/amd-gpu/include/gsl.h
new file mode 100644
index 000000000000..07d8e97dcee3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_H
+#define __GSL_H
+
+//#define __KGSLLIB_EXPORTS
+#define __KERNEL_MODE__
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  forward typedefs
+//////////////////////////////////////////////////////////////////////////////
+//struct _gsl_device_t;
+typedef struct _gsl_device_t    gsl_device_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  includes
+//////////////////////////////////////////////////////////////////////////////
+#include "gsl_buildconfig.h"
+
+#include "kos_libapi.h"
+
+#include "gsl_klibapi.h"
+
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+
+#include "gsl_pm4types.h"
+#include "gsl_utils.h"
+#include "gsl_drawctxt.h"
+#include "gsl_ringbuffer.h"
+#endif
+
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+
+#include "gsl_cmdwindow.h"
+#endif
+
+#include "gsl_debug.h"
+#include "gsl_mmu.h"
+#include "gsl_memmgr.h"
+#include "gsl_sharedmem.h"
+#include "gsl_intrmgr.h"
+#include "gsl_cmdstream.h"
+#include "gsl_device.h"
+#include "gsl_driver.h"
+#include "gsl_log.h"
+
+#include "gsl_config.h"
+
+#endif // __GSL_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h
new file mode 100644
index 000000000000..cda8dae511fe
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL__BUILDCONFIG_H
+#define __GSL__BUILDCONFIG_H
+
+#define GSL_BLD_YAMATO
+#define GSL_BLD_G12
+
+#define GSL_LOCKING_COURSEGRAIN
+
+#define GSL_STATS_MEM
+#define GSL_STATS_RINGBUFFER
+#define GSL_STATS_MMU
+
+#define GSL_RB_USE_MEM_RPTR
+#define GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_TIMESTAMP_INTERUPT
+/* #define GSL_RB_USE_WPTR_POLLING */
+
+/* #define GSL_MMU_TRANSLATION_ENABLED */
+/* #define GSL_MMU_PAGETABLE_PERPROCESS */
+
+#define GSL_CALLER_PROCESS_MAX      10
+#define GSL_SHMEM_MAX_APERTURES     3
+
+#endif /* __GSL__BUILDCONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdstream.h b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
new file mode 100644
index 000000000000..550d5d0005ab
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDSTREAM_H
+#define __GSL_CMDSTREAM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)
+#else
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4, false)
+#endif
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   (*((int*)data) = (gsl_driver.device[GSL_DEVICE_G12-1]).timestamp)
+#else
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4, false)
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+gsl_timestamp_t kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+void kgsl_cmdstream_memqueue_drain(gsl_device_t *device);
+int kgsl_cmdstream_init(gsl_device_t *device);
+int kgsl_cmdstream_close(gsl_device_t *device);
+
+#endif  // __GSL_CMDSTREAM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
new file mode 100644
index 000000000000..0152dd75a631
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDWINDOW_H
+#define __GSL_CMDWINDOW_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifndef _Z180
+#define GSL_G12_INTR_COUNT                  4
+#else
+#define GSL_G12_INTR_COUNT                  3
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_cmdwindow_init(gsl_device_t *device);
+int     kgsl_cmdwindow_close(gsl_device_t *device);
+int     kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+#endif // __GSL_CMDWINDOW_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_config.h b/drivers/mxc/amd-gpu/include/gsl_config.h
new file mode 100644
index 000000000000..aa911b4096a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_config.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL__CONFIG_H
+#define __GSL__CONFIG_H
+
+/* ------------------------
+ * Yamato ringbuffer config
+ * ------------------------ */
+static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K;
+static const unsigned int gsl_cfg_rb_blksizequadwords  = GSL_RB_SIZE_16;
+
+/* ------------------------
+ * Yamato MH arbiter config
+ * ------------------------ */
+static const mh_arbiter_config_t  gsl_cfg_yamato_mharb = {
+    0x10,   /* same_page_limit */
+    0,      /* same_page_granularity  */
+    1,      /* l1_arb_enable */
+    1,      /* l1_arb_hold_enable */
+    0,      /* l2_arb_control */
+    1,      /* page_size */
+    1,      /* tc_reorder_enable */
+    1,      /* tc_arb_hold_enable */
+    1,      /* in_flight_limit_enable */
+    0x8,    /* in_flight_limit */
+    1,      /* cp_clnt_enable */
+    1,      /* vgt_clnt_enable */
+    1,      /* tc_clnt_enable */
+    1,      /* rb_clnt_enable */
+    1,      /* pa_clnt_enable */
+};
+
+/* ---------------------
+ * G12 MH arbiter config
+ * --------------------- */
+static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = {
+    0x10,   /* SAME_PAGE_LIMIT */
+    0,      /* SAME_PAGE_GRANULARITY */
+    1,      /* L1_ARB_ENABLE */
+    1,      /* L1_ARB_HOLD_ENABLE */
+    0,      /* L2_ARB_CONTROL */
+    1,      /* PAGE_SIZE */
+    1,      /* TC_REORDER_ENABLE */
+    1,      /* TC_ARB_HOLD_ENABLE */
+    0,      /* IN_FLIGHT_LIMIT_ENABLE */
+    0x8,    /* IN_FLIGHT_LIMIT */
+    1,      /* CP_CLNT_ENABLE */
+    1,      /* VGT_CLNT_ENABLE */
+    1,      /* TC_CLNT_ENABLE */
+    1,      /* RB_CLNT_ENABLE */
+    1,      /* PA_CLNT_ENABLE */
+};
+
+/* -----------------------------
+ * interrupt block register data
+ * ----------------------------- */
+static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = {
+    {   /* Yamato MH */
+	GSL_INTR_BLOCK_YDX_MH,
+	GSL_INTR_YDX_MH_AXI_READ_ERROR,
+	GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+	mmMH_INTERRUPT_STATUS,
+	mmMH_INTERRUPT_CLEAR,
+	mmMH_INTERRUPT_MASK
+    },
+    {   /* Yamato CP */
+	GSL_INTR_BLOCK_YDX_CP,
+	GSL_INTR_YDX_CP_SW_INT,
+	GSL_INTR_YDX_CP_RING_BUFFER,
+	mmCP_INT_STATUS,
+	mmCP_INT_ACK,
+	mmCP_INT_CNTL
+    },
+    {   /* Yamato RBBM */
+	GSL_INTR_BLOCK_YDX_RBBM,
+	GSL_INTR_YDX_RBBM_READ_ERROR,
+	GSL_INTR_YDX_RBBM_GUI_IDLE,
+	mmRBBM_INT_STATUS,
+	mmRBBM_INT_ACK,
+	mmRBBM_INT_CNTL
+    },
+    {   /* Yamato SQ */
+	GSL_INTR_BLOCK_YDX_SQ,
+	GSL_INTR_YDX_SQ_PS_WATCHDOG,
+	GSL_INTR_YDX_SQ_VS_WATCHDOG,
+	mmSQ_INT_STATUS,
+	mmSQ_INT_ACK,
+	mmSQ_INT_CNTL
+    },
+    {   /* G12 */
+	GSL_INTR_BLOCK_G12,
+	GSL_INTR_G12_MH,
+#ifndef _Z180
+	GSL_INTR_G12_FBC,
+#else
+	GSL_INTR_G12_FIFO,
+#endif /* _Z180 */
+	(ADDR_VGC_IRQSTATUS >> 2),
+	(ADDR_VGC_IRQSTATUS >> 2),
+	(ADDR_VGC_IRQENABLE >> 2)
+    },
+    {   /* G12 MH */
+	GSL_INTR_BLOCK_G12_MH,
+	GSL_INTR_G12_MH_AXI_READ_ERROR,
+	GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+	ADDR_MH_INTERRUPT_STATUS,       /* G12 MH offsets are considered to be dword based, therefore no down shift */
+	ADDR_MH_INTERRUPT_CLEAR,
+	ADDR_MH_INTERRUPT_MASK
+    },
+};
+
+/* -----------------------
+ * interrupt mask bit data
+ * ----------------------- */
+static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = {
+    MH_INTERRUPT_MASK__AXI_READ_ERROR,
+    MH_INTERRUPT_MASK__AXI_WRITE_ERROR,
+    MH_INTERRUPT_MASK__MMU_PAGE_FAULT,
+
+    CP_INT_CNTL__SW_INT_MASK,
+    CP_INT_CNTL__T0_PACKET_IN_IB_MASK,
+    CP_INT_CNTL__OPCODE_ERROR_MASK,
+    CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK,
+    CP_INT_CNTL__RESERVED_BIT_ERROR_MASK,
+    CP_INT_CNTL__IB_ERROR_MASK,
+    CP_INT_CNTL__IB2_INT_MASK,
+    CP_INT_CNTL__IB1_INT_MASK,
+    CP_INT_CNTL__RB_INT_MASK,
+
+    RBBM_INT_CNTL__RDERR_INT_MASK,
+    RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK,
+    RBBM_INT_CNTL__GUI_IDLE_INT_MASK,
+
+    SQ_INT_CNTL__PS_WATCHDOG_MASK,
+    SQ_INT_CNTL__VS_WATCHDOG_MASK,
+
+    (1 << VGC_IRQENABLE_MH_FSHIFT),
+    (1 << VGC_IRQENABLE_G2D_FSHIFT),
+    (1 << VGC_IRQENABLE_FIFO_FSHIFT),
+#ifndef _Z180
+    (1 << VGC_IRQENABLE_FBC_FSHIFT),
+#endif
+    (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT),
+};
+
+/* -----------------
+ * mmu register data
+ * ----------------- */
+static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = {
+    {   /* Yamato */
+	mmMH_MMU_CONFIG,
+	mmMH_MMU_MPU_BASE,
+	mmMH_MMU_MPU_END,
+	mmMH_MMU_VA_RANGE,
+	mmMH_MMU_PT_BASE,
+	mmMH_MMU_PAGE_FAULT,
+	mmMH_MMU_TRAN_ERROR,
+	mmMH_MMU_INVALIDATE,
+    },
+    {   /* G12 - MH offsets are considered to be dword based, therefore no down shift */
+	ADDR_MH_MMU_CONFIG,
+	ADDR_MH_MMU_MPU_BASE,
+	ADDR_MH_MMU_MPU_END,
+	ADDR_MH_MMU_VA_RANGE,
+	ADDR_MH_MMU_PT_BASE,
+	ADDR_MH_MMU_PAGE_FAULT,
+	ADDR_MH_MMU_TRAN_ERROR,
+	ADDR_MH_MMU_INVALIDATE,
+    },
+};
+
+/* -----------------
+ * mh interrupt data
+ * ----------------- */
+static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] =
+{
+    {   /* Yamato */
+	GSL_INTR_YDX_MH_AXI_READ_ERROR,
+	GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+	GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+    },
+    {   /* G12 */
+	GSL_INTR_G12_MH_AXI_READ_ERROR,
+	GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+	GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+    }
+};
+
+#endif /* __GSL__CONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_context.h b/drivers/mxc/amd-gpu/include/gsl_context.h
new file mode 100644
index 000000000000..6e83bdb34036
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_context.h
@@ -0,0 +1,45 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CONTEXT_H
+#define __GSL_CONTEXT_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+#endif  // __GSL_CONTEXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_debug.h b/drivers/mxc/amd-gpu/include/gsl_debug.h
new file mode 100644
index 000000000000..1275278f9eae
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_debug.h
@@ -0,0 +1,126 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEBUG_H
+#define __GSL_DEBUG_H
+
+#ifdef BB_DUMPX
+#include "dumpx.h"
+#endif
+
+#ifdef TBDUMP
+#include "gsl_tbdump.h"
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+#define KGSL_DEBUG(flag, action)                            if (gsl_driver.flags_debug & flag) {action;}
+#ifdef GSL_BLD_YAMATO
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                Yamato_DumpPM4((cmds), (sizedwords))
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                Yamato_DumpRegisterWrite((addr), (value))
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      Yamato_DumpWriteMemory(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       Yamato_DumpSetMemory(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)                      Yamato_DumpFbStart(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)                     Yamato_DumpRegSpace(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          Yamato_DumpWindow(addr, width, height)
+#else
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       
+#define KGSL_DEBUG_DUMPFBSTART(device)                      
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          
+#endif
+#ifdef TBDUMP
+
+#define KGSL_DEBUG_TBDUMP_OPEN(filename)                    tbdump_open(filename)
+#define KGSL_DEBUG_TBDUMP_CLOSE()                           tbdump_close()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)     tbdump_syncmem((unsigned int)addr, (unsigned int)src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)    tbdump_setmem((unsigned int)addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)           tbdump_slavewrite(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()                         tbdump_waitirq()
+
+#else
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif
+#ifdef BB_DUMPX
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)              dumpx_open((filename), (param))
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)    dumpx(cmd, (par1), (par2), (par3), (comment))
+#define KGSL_DEBUG_DUMPX_CLOSE()                            dumpx_close()
+#else
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+#define KGSL_DEBUG_DUMPX_CLOSE()
+#endif
+#else
+#define KGSL_DEBUG(flag, action)
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif // _DEBUG
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_BLD_YAMATO
+void            Yamato_DumpPM4(unsigned int *cmds, unsigned int sizedwords);
+void            Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value);
+void            Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData);
+void            Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData);
+void            Yamato_DumpFbStart(gsl_device_t *device);
+void            Yamato_DumpRegSpace(gsl_device_t *device);
+#ifdef _WIN32
+void            Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height);
+#endif
+#endif
+#ifdef _DEBUG
+int             kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords);
+#endif //_DEBUG
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_device.h b/drivers/mxc/amd-gpu/include/gsl_device.h
new file mode 100644
index 000000000000..433dc6963dfd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_device.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEVICE_H
+#define __GSL_DEVICE_H
+
+#ifdef _LINUX
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// function table
+// --------------
+typedef struct _gsl_functable_t {
+    int (*device_init)            (gsl_device_t *device);
+    int (*device_close)           (gsl_device_t *device);
+    int (*device_destroy)         (gsl_device_t *device);
+    int (*device_start)           (gsl_device_t *device, gsl_flags_t flags);
+    int (*device_stop)            (gsl_device_t *device);
+    int (*device_getproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_setproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_idle)            (gsl_device_t *device, unsigned int timeout);
+    int (*device_regread)         (gsl_device_t *device, unsigned int offsetwords, unsigned int *value);
+    int (*device_regwrite)        (gsl_device_t *device, unsigned int offsetwords, unsigned int value);
+    int (*device_waitirq)         (gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+	int (*device_waittimestamp)   (gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout);
+    int (*device_runpending)      (gsl_device_t *device);
+    int (*device_addtimestamp)    (gsl_device_t *device_id, gsl_timestamp_t *timestamp);
+    int (*intr_isr)               (gsl_device_t *device);
+	int (*mmu_tlbinvalidate)      (gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid);
+	int (*mmu_setpagetable)       (gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid);
+    int (*cmdstream_issueibcmds)  (gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+    int (*context_create)         (gsl_device_t *device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+    int (*context_destroy)        (gsl_device_t *device_id, unsigned int drawctxt_id);
+} gsl_functable_t;
+
+// -------------
+// device object 
+// -------------
+struct _gsl_device_t {
+
+    unsigned int      refcnt;
+    unsigned int      callerprocess[GSL_CALLER_PROCESS_MAX];    // caller process table
+    gsl_functable_t   ftbl;
+    gsl_flags_t       flags;
+    gsl_deviceid_t    id;
+    unsigned int      chip_id;
+    gsl_memregion_t   regspace;
+    gsl_intr_t        intr;
+    gsl_memdesc_t     memstore;
+    gsl_memqueue_t    memqueue; // queue of memfrees pending timestamp elapse 
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+    unsigned int      memstoreshadow[GSL_CALLER_PROCESS_MAX];
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifndef GSL_NO_MMU
+    gsl_mmu_t         mmu;
+#endif // GSL_NO_MMU
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t   gmemspace;
+    gsl_ringbuffer_t  ringbuffer;
+    unsigned int      drawctxt_count;
+    gsl_drawctxt_t    *drawctxt_active;
+    gsl_drawctxt_t    drawctxt[GSL_CONTEXT_MAX];
+#endif // GSL_BLD_YAMATO
+
+#ifdef GSL_BLD_G12
+    unsigned int      intrcnt[GSL_G12_INTR_COUNT];
+    gsl_timestamp_t   current_timestamp;
+    gsl_timestamp_t   timestamp;
+#ifndef _LINUX	
+    unsigned int      irq_thread;
+    oshandle_t        irq_thread_handle;
+#endif
+#ifdef IRQTHREAD_POLL
+    oshandle_t        irqthread_event;
+#endif
+#endif // GSL_BLD_G12
+#ifndef _LINUX	
+    oshandle_t        timestamp_event;
+#else
+	wait_queue_head_t timestamp_waitq;
+	struct workqueue_struct	*irq_workq;
+	struct work_struct irq_work;	
+#endif
+    void              *autogate;
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id);
+int     kgsl_device_close(gsl_device_t *device);
+int     kgsl_device_destroy(gsl_device_t *device);
+int     kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_runpending(gsl_device_t *device);
+
+int     kgsl_yamato_getfunctable(gsl_functable_t *ftbl);
+int     kgsl_g12_getfunctable(gsl_functable_t *ftbl);
+
+int kgsl_clock(gsl_deviceid_t dev, int enable);
+int kgsl_device_active(gsl_device_t *dev);
+int kgsl_device_clock(gsl_deviceid_t id, int enable);
+int kgsl_device_autogate_init(gsl_device_t *dev);
+void kgsl_device_autogate_exit(gsl_device_t *dev);
+
+
+#endif  // __GSL_DEVICE_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_display.h b/drivers/mxc/amd-gpu/include/gsl_display.h
new file mode 100644
index 000000000000..82300647b3ef
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_display.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DISPLAY_H
+#define __GSL_DISPLAY_H
+
+#define __GSLDISPLAY_EXPORTS
+
+#include "gsl_libapi.h"
+#include "gsl_klibapi.h"    // hack to enable direct reg write
+#include "gsl_displayapi.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_LIB_MAXDISPLAYS     1
+#define GSL_LIB_MAXSURFACES     3
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef struct _gsl_display_t {
+    int                   numdisplays;
+    gsl_displaymode_t     mode[GSL_LIB_MAXDISPLAYS];
+    gsl_devhandle_t       devhandle;
+} gsl_display_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     gsl_display_hitachi_240x320_tft_init(int display_id);
+int     gsl_display_toshiba_640x480_tft_init(int display_id);
+
+#endif // __GSL_DISPLAY_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_drawctxt.h b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
new file mode 100644
index 000000000000..15b8097828af
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
@@ -0,0 +1,110 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRAWCTXT_H
+#define __GSL_DRAWCTXT_H
+
+//////////////////////////////////////////////////////////////////////////////
+// Flags
+//////////////////////////////////////////////////////////////////////////////
+
+#define CTXT_FLAGS_NOT_IN_USE       0x00000000
+#define CTXT_FLAGS_IN_USE           0x00000001
+
+#define CTXT_FLAGS_STATE_SHADOW     0x00000010  // state shadow memory allocated
+
+#define CTXT_FLAGS_GMEM_SHADOW      0x00000100  // gmem shadow memory allocated
+#define CTXT_FLAGS_GMEM_SAVE        0x00000200  // gmem must be copied to shadow
+#define CTXT_FLAGS_GMEM_RESTORE     0x00000400  // gmem can be restored from shadow
+
+#define CTXT_FLAGS_SHADER_SAVE      0x00002000  // shader must be copied to shadow
+#define CTXT_FLAGS_SHADER_RESTORE   0x00004000  // shader can be restored from shadow
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------
+// draw context
+// ------------
+
+typedef struct _gmem_shadow_t
+{
+    gsl_memdesc_t   gmemshadow;     // Shadow buffer address
+
+    // 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x 256 rows.
+    // width & height must be a multiples of 32, in case tiled textures are used.
+    unsigned int    size;       // Size of surface used to store GMEM
+    unsigned int    width;          // Width of surface used to store GMEM
+    unsigned int    height;         // Height of surface used to store GMEM
+    unsigned int    pitch;          // Pitch of surface used to store GMEM
+    int             offset;
+    unsigned int    offset_x;
+    unsigned int    offset_y;
+    unsigned int    gmem_offset_x;
+    unsigned int    gmem_offset_y;
+
+    unsigned int*   gmem_save_commands;
+    unsigned int*   gmem_restore_commands;
+    unsigned int    gmem_save[3];
+    unsigned int    gmem_restore[3];
+
+    gsl_memdesc_t   quad_vertices;
+    gsl_memdesc_t   quad_texcoords;
+} gmem_shadow_t;
+
+#define GSL_MAX_GMEM_SHADOW_BUFFERS 2
+
+typedef struct _gsl_drawctxt_t {
+	unsigned int        pid;
+    gsl_flags_t         flags;
+    gsl_context_type_t  type;
+    gsl_memdesc_t       gpustate;
+    
+    unsigned int        reg_save[3];
+    unsigned int        reg_restore[3];
+    unsigned int        shader_save[3];
+    unsigned int        shader_fixup[3];
+    unsigned int        shader_restore[3];
+    unsigned int        chicken_restore[3];
+    gmem_shadow_t       context_gmem_shadow;    // Information of the GMEM shadow that is created in context create
+    gmem_shadow_t       user_gmem_shadow[GSL_MAX_GMEM_SHADOW_BUFFERS]; // User defined GMEM shadow buffers
+} gsl_drawctxt_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_drawctxt_init(gsl_device_t *device);
+int     kgsl_drawctxt_close(gsl_device_t *device);
+int     kgsl_drawctxt_destroyall(gsl_device_t *device);
+void    kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags);
+int     kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+int     kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+
+#endif  // __GSL_DRAWCTXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_driver.h b/drivers/mxc/amd-gpu/include/gsl_driver.h
new file mode 100644
index 000000000000..1e1d43da431d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_driver.h
@@ -0,0 +1,105 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRIVER_H
+#define __GSL_DRIVER_H
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_DEDICATED_PROCESS
+#define GSL_CALLER_PROCESSID_GET()      kos_callerprocess_getid()
+#else
+#define GSL_CALLER_PROCESSID_GET()      kos_process_getid()
+#endif // GSL_DEDICATED_PROCESS
+
+#ifdef GSL_LOCKING_COURSEGRAIN
+#define GSL_API_MUTEX_CREATE()          gsl_driver.mutex = kos_mutex_create("gsl_global"); \
+                                        if (!gsl_driver.mutex) {return (GSL_FAILURE);}
+#define GSL_API_MUTEX_LOCK()            kos_mutex_lock(gsl_driver.mutex)
+#define GSL_API_MUTEX_UNLOCK()          kos_mutex_unlock(gsl_driver.mutex)
+#define GSL_API_MUTEX_FREE()            kos_mutex_free(gsl_driver.mutex); gsl_driver.mutex = 0;
+#else
+#define GSL_API_MUTEX_CREATE()
+#define GSL_API_MUTEX_LOCK()        
+#define GSL_API_MUTEX_UNLOCK()      
+#define GSL_API_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// driver object 
+// -------------
+typedef struct _gsl_driver_t {
+    gsl_flags_t      flags_debug;
+    int              refcnt;
+    unsigned int     callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table
+    oshandle_t       mutex;                                 // global API mutex
+    void             *hal;
+    gsl_sharedmem_t  shmem;
+    gsl_device_t     device[GSL_DEVICE_MAX];
+    int              dmi_state;     //  OS_TRUE = enabled, OS_FALSE otherwise
+    gsl_flags_t      dmi_mode;      //  single, double, or triple buffering
+    int              dmi_frame;     //  set to -1 when DMI is enabled
+    int              dmi_max_frame; //  indicates the maximum frame # that we will support
+} gsl_driver_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// external variable declarations
+//////////////////////////////////////////////////////////////////////////////
+extern gsl_driver_t  gsl_driver;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_driver_getcallerprocessindex(unsigned int pid, int *index)
+{
+    int  i;
+
+    // obtain index in caller process table
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        if (gsl_driver.callerprocess[i] == pid)
+        {
+            *index = i;            
+            return (GSL_SUCCESS);
+        }
+    }
+
+    return (GSL_FAILURE);
+}
+
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h
new file mode 100644
index 000000000000..fa26b1f23119
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_hal.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HALAPI_H
+#define __GSL_HALAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/*
+#include "gsl_buildconfig.h"
+#include "kos_libapi.h"
+#include "gsl_klibapi.h"
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+#endif
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+#endif
+#include "gsl_hwaccess.h"
+*/
+
+#include "gsl.h"
+#include "gsl_hwaccess.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// linkage
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLHAL_EXPORTS
+#define KGSLHAL_API                 OS_DLLEXPORT
+#else
+#define KGSLHAL_API
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLHAL_NAME            "AMD GSL Kernel HAL"
+#define KGSLHAL_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_HAL_REG_READ(device_id, gpubase, offsetwords, value)    kgsl_hwaccess_regread(device_id, gpubase, (offsetwords), (value))
+#define GSL_HAL_REG_WRITE(device_id, gpubase, offsetwords, value)   kgsl_hwaccess_regwrite(device_id, gpubase, (offsetwords), (value))
+
+#define GSL_HAL_MEM_READ(dst, gpubase, gpuoffset, sizebytes, touserspace)        kgsl_hwaccess_memread(dst, gpubase, (gpuoffset), (sizebytes), touserspace)
+#define GSL_HAL_MEM_WRITE(gpubase, gpuoffset, src, sizebytes, fromuserspace)     kgsl_hwaccess_memwrite(gpubase, (gpuoffset), src, (sizebytes), fromuserspace)
+#define GSL_HAL_MEM_SET(gpubase, gpuoffset, value, sizebytes)                    kgsl_hwaccess_memset(gpubase, (gpuoffset), (value), (sizebytes))
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// device config
+// -------------
+typedef struct _gsl_devconfig_t {
+
+    gsl_memregion_t  regspace;
+
+    unsigned int     mmu_config;
+    gpuaddr_t        mpu_base;
+    int              mpu_range;
+    gpuaddr_t        va_base;
+    unsigned int     va_range;
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t  gmemspace;
+#endif // GSL_BLD_YAMATO
+
+} gsl_devconfig_t;
+
+// ----------------------
+// memory aperture config
+// ----------------------
+typedef struct _gsl_apertureconfig_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    unsigned int      hostbase;
+    unsigned int      gpubase;
+    unsigned int      sizebytes;
+} gsl_apertureconfig_t;
+
+// --------------------
+// shared memory config
+// --------------------
+typedef struct _gsl_shmemconfig_t 
+{
+    int                   numapertures;
+    gsl_apertureconfig_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_shmemconfig_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  HAL API
+//////////////////////////////////////////////////////////////////////////////
+KGSLHAL_API int             kgsl_hal_init(void);
+KGSLHAL_API int             kgsl_hal_close(void);
+KGSLHAL_API int             kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config);
+KGSLHAL_API int             kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config);
+KGSLHAL_API int             kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value);
+KGSLHAL_API gsl_chipid_t    kgsl_hal_getchipid(gsl_deviceid_t device_id);
+KGSLHAL_API int             kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+KGSLHAL_API int             kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_HALAPI_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_halconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h
new file mode 100644
index 000000000000..64f48e9d068e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL_HALCONFIG_H
+#define __GSL_HALCONFIG_H
+
+#define GSL_HAL_GPUBASE_REG_YDX         0x30000000
+#define GSL_HAL_SIZE_REG_YDX            0x00020000            /* 128KB */
+
+#define GSL_HAL_SIZE_REG_G12            0x00001000            /* 4KB */
+
+#if defined(GSL_MMU_TRANSLATION_ENABLED)
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x01800000            /* 24MB */
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00400000            /* 4MB */
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00400000            /* 4MB */
+#else
+#define GSL_HAL_SHMEM_SIZE_EMEM1        0x00D00000            /* 13MB */
+#define GSL_HAL_SHMEM_SIZE_EMEM2        0x00200000            /* 2MB */
+#define GSL_HAL_SHMEM_SIZE_PHYS         0x00100000            /* 1MB */
+#endif
+
+#endif  /* __GSL_HALCONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_intrmgr.h b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
new file mode 100644
index 000000000000..f46f6d8e6a86
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
@@ -0,0 +1,104 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_INTRMGR_H
+#define __GSL_INTRMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------------------------------
+// block which can generate an interrupt
+// -------------------------------------
+typedef enum _gsl_intrblock_t
+{
+    GSL_INTR_BLOCK_YDX_MH = 0,
+    GSL_INTR_BLOCK_YDX_CP,
+    GSL_INTR_BLOCK_YDX_RBBM,
+    GSL_INTR_BLOCK_YDX_SQ,
+    GSL_INTR_BLOCK_G12,
+    GSL_INTR_BLOCK_G12_MH,
+
+    GSL_INTR_BLOCK_COUNT,
+} gsl_intrblock_t;
+
+// ------------------------
+// interrupt block register
+// ------------------------
+typedef struct _gsl_intrblock_reg_t
+{
+    gsl_intrblock_t  id;
+    gsl_intrid_t     first_id;
+    gsl_intrid_t     last_id;
+    unsigned int     status_reg;
+    unsigned int     clear_reg;
+    unsigned int     mask_reg;
+} gsl_intrblock_reg_t;
+
+// --------
+// callback
+// --------
+typedef void (*gsl_intr_callback_t)(gsl_intrid_t id, void *cookie);
+
+// -----------------
+// interrupt routine
+// -----------------
+typedef struct _gsl_intr_handler_t
+{
+    gsl_intr_callback_t callback;
+    void *              cookie;
+} gsl_intr_handler_t;
+
+// -----------------
+// interrupt manager
+// -----------------
+typedef struct _gsl_intr_t
+{
+    gsl_flags_t         flags;
+    gsl_device_t        *device;
+    unsigned int        enabled[GSL_INTR_BLOCK_COUNT];
+    gsl_intr_handler_t  handler[GSL_INTR_COUNT];
+    oshandle_t          evnt[GSL_INTR_COUNT];
+} gsl_intr_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_intr_init(gsl_device_t *device);
+int             kgsl_intr_close(gsl_device_t *device);
+int             kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie);
+int             kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id);
+void            kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id);
+
+#endif  // __GSL_INTMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ioctl.h b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
new file mode 100644
index 000000000000..0f1983e4c770
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
@@ -0,0 +1,238 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _GSL_IOCTL_H
+#define _GSL_IOCTL_H
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct _kgsl_device_start_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+} kgsl_device_start_t;
+
+typedef struct _kgsl_device_stop_t {
+    gsl_deviceid_t  device_id;
+} kgsl_device_stop_t;
+
+typedef struct _kgsl_device_idle_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    timeout;
+} kgsl_device_idle_t;
+
+typedef struct _kgsl_device_getproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    unsigned int    *value;
+    unsigned int    sizebytes;
+} kgsl_device_getproperty_t;
+
+typedef struct _kgsl_device_setproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    void        *value;
+    unsigned int    sizebytes;
+} kgsl_device_setproperty_t;
+
+typedef struct _kgsl_device_regread_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    *value;
+} kgsl_device_regread_t;
+
+typedef struct _kgsl_device_regwrite_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    value;
+} kgsl_device_regwrite_t;
+
+typedef struct _kgsl_device_waitirq_t {
+    gsl_deviceid_t  device_id;
+    gsl_intrid_t    intr_id;
+    unsigned int    *count;
+    unsigned int    timeout;
+} kgsl_device_waitirq_t;
+
+typedef struct _kgsl_cmdstream_issueibcmds_t {
+    gsl_deviceid_t  device_id;
+    int     drawctxt_index;
+    gpuaddr_t   ibaddr;
+    int     sizedwords;
+    gsl_timestamp_t *timestamp;
+    gsl_flags_t flags;
+} kgsl_cmdstream_issueibcmds_t;
+
+typedef struct _kgsl_cmdstream_readtimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_timestamp_type_t    type;
+    gsl_timestamp_t *timestamp;
+} kgsl_cmdstream_readtimestamp_t;
+
+typedef struct _kgsl_cmdstream_freememontimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    gsl_timestamp_t timestamp;
+    gsl_timestamp_type_t    type;
+} kgsl_cmdstream_freememontimestamp_t;
+
+typedef struct _kgsl_cmdstream_waittimestamp_t {
+    gsl_deviceid_t  device_id;
+	gsl_timestamp_t timestamp;
+    unsigned int    timeout;
+} kgsl_cmdstream_waittimestamp_t;
+
+typedef struct _kgsl_cmdwindow_write_t {
+    gsl_deviceid_t  device_id;
+    gsl_cmdwindow_t target;
+    unsigned int    addr;
+    unsigned int    data;
+} kgsl_cmdwindow_write_t;
+
+typedef struct _kgsl_context_create_t {
+    gsl_deviceid_t  device_id;
+    gsl_context_type_t  type;
+    unsigned int    *drawctxt_id;
+    gsl_flags_t flags;
+} kgsl_context_create_t;
+
+typedef struct _kgsl_context_destroy_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    drawctxt_id;
+} kgsl_context_destroy_t;
+
+typedef struct _kgsl_drawctxt_bind_gmem_shadow_t {
+    gsl_deviceid_t device_id;
+    unsigned int drawctxt_id;
+    const gsl_rect_t* gmem_rect;
+    unsigned int shadow_x;
+    unsigned int shadow_y;
+    const gsl_buffer_desc_t* shadow_buffer;
+    unsigned int buffer_id;
+} kgsl_drawctxt_bind_gmem_shadow_t;
+
+typedef struct _kgsl_sharedmem_alloc_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    int     sizebytes;
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_alloc_t;
+
+typedef struct _kgsl_sharedmem_free_t {
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_free_t;
+
+typedef struct _kgsl_sharedmem_read_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    *dst;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_read_t;
+
+typedef struct _kgsl_sharedmem_write_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    *src;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_write_t;
+
+typedef struct _kgsl_sharedmem_set_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    value;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_set_t;
+
+typedef struct _kgsl_sharedmem_largestfreeblock_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    unsigned int    *largestfreeblock;
+} kgsl_sharedmem_largestfreeblock_t;
+
+typedef struct _kgsl_sharedmem_cacheoperation_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+    unsigned int    operation;
+} kgsl_sharedmem_cacheoperation_t;
+
+typedef struct _kgsl_sharedmem_fromhostpointer_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    void        *hostptr;
+} kgsl_sharedmem_fromhostpointer_t;
+
+typedef struct _kgsl_add_timestamp_t {
+    gsl_deviceid_t device_id;
+    gsl_timestamp_t *timestamp;
+} kgsl_add_timestamp_t;
+
+typedef struct _kgsl_device_clock_t {
+    gsl_deviceid_t device; /* GSL_DEVICE_YAMATO = 1, GSL_DEVICE_G12 = 2 */
+    int enable; /* 0: disable, 1: enable */
+} kgsl_device_clock_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// ioctl numbers
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_MAGIC                               0xF9
+#define IOCTL_KGSL_DEVICE_START                 _IOW(GSL_MAGIC, 0x20, struct _kgsl_device_start_t)
+#define IOCTL_KGSL_DEVICE_STOP                  _IOW(GSL_MAGIC, 0x21, struct _kgsl_device_stop_t)
+#define IOCTL_KGSL_DEVICE_IDLE                  _IOW(GSL_MAGIC, 0x22, struct _kgsl_device_idle_t)
+#define IOCTL_KGSL_DEVICE_GETPROPERTY           _IOWR(GSL_MAGIC, 0x23, struct _kgsl_device_getproperty_t)
+#define IOCTL_KGSL_DEVICE_SETPROPERTY           _IOW(GSL_MAGIC, 0x24, struct _kgsl_device_setproperty_t)
+#define IOCTL_KGSL_DEVICE_REGREAD               _IOWR(GSL_MAGIC, 0x25, struct _kgsl_device_regread_t)
+#define IOCTL_KGSL_DEVICE_REGWRITE              _IOW(GSL_MAGIC, 0x26, struct _kgsl_device_regwrite_t)
+#define IOCTL_KGSL_DEVICE_WAITIRQ               _IOWR(GSL_MAGIC, 0x27, struct _kgsl_device_waitirq_t)
+#define IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS        _IOWR(GSL_MAGIC, 0x28, struct _kgsl_cmdstream_issueibcmds_t)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP      _IOWR(GSL_MAGIC, 0x29, struct _kgsl_cmdstream_readtimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(GSL_MAGIC, 0x2A, struct _kgsl_cmdstream_freememontimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP      _IOW(GSL_MAGIC, 0x2B, struct _kgsl_cmdstream_waittimestamp_t)
+#define IOCTL_KGSL_CMDWINDOW_WRITE              _IOW(GSL_MAGIC, 0x2C, struct _kgsl_cmdwindow_write_t)
+#define IOCTL_KGSL_CONTEXT_CREATE               _IOWR(GSL_MAGIC, 0x2D, struct _kgsl_context_create_t)
+#define IOCTL_KGSL_CONTEXT_DESTROY              _IOW(GSL_MAGIC, 0x2E, struct _kgsl_context_destroy_t)
+#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW    _IOW(GSL_MAGIC, 0x2F, struct _kgsl_drawctxt_bind_gmem_shadow_t)
+#define IOCTL_KGSL_SHAREDMEM_ALLOC              _IOWR(GSL_MAGIC, 0x30, struct _kgsl_sharedmem_alloc_t)
+#define IOCTL_KGSL_SHAREDMEM_FREE               _IOW(GSL_MAGIC, 0x31, struct _kgsl_sharedmem_free_t)
+#define IOCTL_KGSL_SHAREDMEM_READ               _IOWR(GSL_MAGIC, 0x32, struct _kgsl_sharedmem_read_t)
+#define IOCTL_KGSL_SHAREDMEM_WRITE              _IOW(GSL_MAGIC, 0x33, struct _kgsl_sharedmem_write_t)
+#define IOCTL_KGSL_SHAREDMEM_SET                _IOW(GSL_MAGIC, 0x34, struct _kgsl_sharedmem_set_t)
+#define IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK   _IOWR(GSL_MAGIC, 0x35, struct _kgsl_sharedmem_largestfreeblock_t)
+#define IOCTL_KGSL_SHAREDMEM_CACHEOPERATION     _IOW(GSL_MAGIC, 0x36, struct _kgsl_sharedmem_cacheoperation_t)
+#define IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER    _IOW(GSL_MAGIC, 0x37, struct _kgsl_sharedmem_fromhostpointer_t)
+#define IOCTL_KGSL_ADD_TIMESTAMP                _IOWR(GSL_MAGIC, 0x38, struct _kgsl_add_timestamp_t)
+#define IOCTL_KGSL_DRIVER_EXIT		        _IOWR(GSL_MAGIC, 0x39, NULL)
+#define IOCTL_KGSL_DEVICE_CLOCK			_IOWR(GSL_MAGIC, 0x60, struct _kgsl_device_clock_t)
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/gsl_log.h b/drivers/mxc/amd-gpu/include/gsl_log.h
new file mode 100644
index 000000000000..dbb7e4c6ef96
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_log.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LOG_H
+#define __GSL_LOG_H
+
+#define KGSL_LOG_GROUP_DRIVER       0x00000001
+#define KGSL_LOG_GROUP_DEVICE       0x00000002
+#define KGSL_LOG_GROUP_COMMAND      0x00000004
+#define KGSL_LOG_GROUP_CONTEXT      0x00000008
+#define KGSL_LOG_GROUP_MEMORY       0x00000010
+#define KGSL_LOG_GROUP_ALL          0x000000ff
+
+#define KGSL_LOG_LEVEL_ALL          0x0000ff00
+#define KGSL_LOG_LEVEL_TRACE        0x00003f00
+#define KGSL_LOG_LEVEL_DEBUG        0x00001f00
+#define KGSL_LOG_LEVEL_INFO         0x00000f00
+#define KGSL_LOG_LEVEL_WARN         0x00000700
+#define KGSL_LOG_LEVEL_ERROR        0x00000300
+#define KGSL_LOG_LEVEL_FATAL        0x00000100
+
+#define KGSL_LOG_TIMESTAMP          0x00010000
+#define KGSL_LOG_THREAD_ID          0x00020000
+#define KGSL_LOG_PROCESS_ID         0x00040000
+
+#ifdef GSL_LOG
+
+int kgsl_log_init(void);
+int kgsl_log_close(void);
+int kgsl_log_open_stdout( unsigned int log_flags );
+int kgsl_log_write( unsigned int log_flags, char* format, ... );
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags );
+int kgsl_log_open_file( char* filename, unsigned int log_flags );
+int kgsl_log_flush_membuf( char* filename, int memBufId );
+
+#else
+
+// Empty function definitions
+OSINLINE int kgsl_log_init(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_close(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_stdout( unsigned int log_flags ) { (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_write( unsigned int log_flags, char* format, ... ) { (void)log_flags; (void)format; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) { (void)memBufId; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_file( char* filename, unsigned int log_flags ) { (void)filename; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_flush_membuf( char* filename, int memBufId ) { (void) filename; (void) memBufId; return GSL_SUCCESS; }
+
+#endif
+
+#endif // __GSL_LOG_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_memmgr.h b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
new file mode 100644
index 000000000000..ef9ad93ea96e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
@@ -0,0 +1,122 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MEMMGR_H
+#define __GSL_MEMMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_NODE_POOL_MAX      32                              // max is 32
+
+#define GSL_MEMARENA_PAGE_DIST_MAX      12                              // 4MB
+
+//#define GSL_MEMARENA_NODE_POOL_ENABLED
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------------
+// memory arena stats
+// ------------------
+typedef struct _gsl_memarena_stats_t {
+    __int64  bytes_read;
+    __int64  bytes_written;
+    __int64  allocs_success;
+    __int64  allocs_fail;
+    __int64  frees;
+    __int64  allocs_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; // 0=0--(4K-1), 1=4--(8K-1), 2=8--(16K-1),... max-1=(GSL_PAGESIZE<<(max-1))--infinity
+    __int64  frees_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX];
+} gsl_memarena_stats_t;
+
+// ------------
+// memory block
+// ------------
+typedef struct _memblk_t {
+    unsigned int      blkaddr;
+    unsigned int      blksize;
+    struct _memblk_t  *next;
+    struct _memblk_t  *prev;
+    int               nodepoolindex;
+} memblk_t;
+
+// ----------------------
+// memory block free list
+// ----------------------
+typedef struct _gsl_freelist_t {
+    memblk_t  *head;
+    memblk_t  *allocrover;
+    memblk_t  *freerover;
+} gsl_freelist_t;
+
+// ----------------------
+// memory block node pool
+// ----------------------
+typedef struct _gsl_nodepool_t {
+    unsigned int            priv;
+    memblk_t                memblk[GSL_MEMARENA_NODE_POOL_MAX];
+    struct _gsl_nodepool_t  *next;
+    struct _gsl_nodepool_t  *prev;
+} gsl_nodepool_t;
+
+// -------------------
+// memory arena object
+// -------------------
+typedef struct _gsl_memarena_t {
+    oshandle_t      mutex;
+    unsigned int    gpubaseaddr;
+    unsigned int    hostbaseaddr;
+    unsigned int    sizebytes;
+    gsl_nodepool_t  *nodepool;
+    gsl_freelist_t  freelist;
+    unsigned int    priv;
+
+#ifdef GSL_STATS_MEM
+    gsl_memarena_stats_t  stats;
+#endif // GSL_STATS_MEM
+
+} gsl_memarena_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+gsl_memarena_t* kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes);
+int             kgsl_memarena_destroy(gsl_memarena_t *memarena);
+int             kgsl_memarena_isvirtualized(gsl_memarena_t *memarena);
+int             kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats);
+int             kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc);
+void            kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc);
+void*           kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr);
+unsigned int    kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr);
+unsigned int    kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags);
+
+#endif  // __GSL_MEMMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_mmu.h b/drivers/mxc/amd-gpu/include/gsl_mmu.h
new file mode 100644
index 000000000000..868c5156f290
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_mmu.h
@@ -0,0 +1,183 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MMU_H
+#define __GSL_MMU_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_STATS_MMU
+#define GSL_MMU_STATS(x) x
+#else
+#define GSL_MMU_STATS(x)
+#endif // GSL_STATS_MMU
+
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+#define GSL_MMU_PAGETABLE_MAX               GSL_CALLER_PROCESS_MAX      // all device mmu's share a single page table per process
+#else
+#define GSL_MMU_PAGETABLE_MAX               1                           // all device mmu's share a single global page table
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+#define GSL_PT_SUPER_PTE                    8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ---------
+// mmu debug
+// ---------
+typedef struct _gsl_mmu_debug_t {
+    unsigned int  config;
+    unsigned int  mpu_base;
+    unsigned int  mpu_end;
+    unsigned int  va_range;
+    unsigned int  pt_base;
+    unsigned int  page_fault;
+    unsigned int  trans_error;
+    unsigned int  invalidate;
+} gsl_mmu_debug_t;
+#endif // _DEBUG
+
+// ------------
+// mmu register
+// ------------
+typedef struct _gsl_mmu_reg_t
+{
+    unsigned int  CONFIG;
+    unsigned int  MPU_BASE;
+    unsigned int  MPU_END;
+    unsigned int  VA_RANGE;
+    unsigned int  PT_BASE;
+    unsigned int  PAGE_FAULT;
+    unsigned int  TRAN_ERROR;
+    unsigned int  INVALIDATE;
+} gsl_mmu_reg_t;
+
+// ------------
+// mh interrupt
+// ------------
+typedef struct _gsl_mh_intr_t
+{
+    gsl_intrid_t  AXI_READ_ERROR;
+    gsl_intrid_t  AXI_WRITE_ERROR;
+    gsl_intrid_t  MMU_PAGE_FAULT;
+} gsl_mh_intr_t;
+
+// ----------------
+// page table stats
+// ----------------
+typedef struct _gsl_ptstats_t {
+    __int64  maps;
+    __int64  unmaps;
+	__int64  switches;
+} gsl_ptstats_t;
+
+// ---------
+// mmu stats
+// ---------
+typedef struct _gsl_mmustats_t {
+	gsl_ptstats_t  pt;
+	__int64        tlbflushes;
+} gsl_mmustats_t;
+
+// -----------------
+// page table object
+// -----------------
+typedef struct _gsl_pagetable_t {
+	unsigned int   pid;
+    unsigned int   refcnt;
+    gsl_memdesc_t  base;
+    gpuaddr_t      va_base;
+    unsigned int   va_range;
+    unsigned int   last_superpte;
+    unsigned int   max_entries;
+} gsl_pagetable_t;
+
+// -------------------------
+// tlb flush filter object
+// -------------------------
+typedef struct _gsl_tlbflushfilter_t {
+    unsigned int  *base;
+    unsigned int  size;
+} gsl_tlbflushfilter_t;
+
+// ----------
+// mmu object
+// ----------
+typedef struct _gsl_mmu_t {
+    unsigned int          refcnt;
+    gsl_flags_t           flags;
+    gsl_device_t          *device;
+    unsigned int          config;
+    gpuaddr_t             mpu_base;
+    int                   mpu_range;
+    gpuaddr_t             va_base;
+    unsigned int          va_range;
+    gsl_memdesc_t         dummyspace;
+    gsl_tlbflushfilter_t  tlbflushfilter;
+    gsl_pagetable_t       *hwpagetable;                     // current page table object being used by device mmu
+    gsl_pagetable_t       *pagetable[GSL_MMU_PAGETABLE_MAX];    // page table object table
+#ifdef GSL_STATS_MMU
+	gsl_mmustats_t        stats;
+#endif  // GSL_STATS_MMU
+} gsl_mmu_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_isenabled(gsl_mmu_t *mmu)
+{
+    // address translation enabled
+    int enabled = ((mmu)->flags & GSL_FLAGS_STARTED) ? 1 : 0;
+
+    return (enabled);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int    kgsl_mmu_init(gsl_device_t *device);
+int    kgsl_mmu_close(gsl_device_t *device);
+int    kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid);
+int    kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid);
+int    kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid);
+int    kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid);
+int    kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats);
+int    kgsl_mmu_bist(gsl_mmu_t *mmu);
+
+#endif // __GSL_MMU_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
new file mode 100644
index 000000000000..6081c396f6e4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
@@ -0,0 +1,235 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_RINGBUFFER_H
+#define __GSL_RINGBUFFER_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+// ringbuffer sizes log2quadword
+#define     GSL_RB_SIZE_8                        0
+#define     GSL_RB_SIZE_16                       1
+#define     GSL_RB_SIZE_32                       2
+#define     GSL_RB_SIZE_64                       3
+#define     GSL_RB_SIZE_128                      4
+#define     GSL_RB_SIZE_256                      5
+#define     GSL_RB_SIZE_512                      6
+#define     GSL_RB_SIZE_1K                       7
+#define     GSL_RB_SIZE_2K                       8
+#define     GSL_RB_SIZE_4K                       9
+#define     GSL_RB_SIZE_8K                      10
+#define     GSL_RB_SIZE_16K                     11
+#define     GSL_RB_SIZE_32K                     12
+#define     GSL_RB_SIZE_64K                     13
+#define     GSL_RB_SIZE_128K                    14
+#define     GSL_RB_SIZE_256K                    15
+#define     GSL_RB_SIZE_512K                    16
+#define     GSL_RB_SIZE_1M                      17
+#define     GSL_RB_SIZE_2M                      18
+#define     GSL_RB_SIZE_4M                      19
+
+// offsets into memptrs
+#define GSL_RB_MEMPTRS_RPTR_OFFSET              0
+#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET          (GSL_RB_MEMPTRS_RPTR_OFFSET + sizeof(unsigned int))
+
+// dword base address of the GFX decode space
+#define GSL_HAL_SUBBLOCK_OFFSET(reg)            ((unsigned int)((reg) - (0x2000)))
+
+// CP timestamp register
+#define mmCP_TIMESTAMP                          mmSCRATCH_REG0
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ----------------
+// ringbuffer debug
+// ----------------
+typedef struct _gsl_rb_debug_t {
+    unsigned int        pm4_ucode_rel;
+    unsigned int        pfp_ucode_rel;
+    unsigned int        cp_rb_base;
+    cp_rb_cntl_u        cp_rb_cntl;
+    unsigned int        cp_rb_rptr_addr;
+    unsigned int        cp_rb_rptr;
+    unsigned int        cp_rb_wptr;
+    unsigned int        cp_rb_wptr_base;
+    scratch_umsk_u      scratch_umsk;
+    unsigned int        scratch_addr;
+    cp_me_cntl_u        cp_me_cntl;
+    cp_me_status_u      cp_me_status;
+    cp_debug_u          cp_debug;
+    cp_stat_u           cp_stat;
+    rbbm_status_u       rbbm_status;
+    unsigned int        sop_timestamp;
+    unsigned int        eop_timestamp;
+} gsl_rb_debug_t;
+#endif // _DEBUG
+
+// -------------------
+// ringbuffer watchdog
+// -------------------
+typedef struct _gsl_rbwatchdog_t {
+    gsl_flags_t   flags;
+    unsigned int  rptr_sample;
+} gsl_rbwatchdog_t;
+
+// ------------------
+// memory ptr objects
+// ------------------
+#ifdef __GNUC__
+#pragma pack(push, 1)
+#else
+#pragma pack(push)
+#pragma pack(1)
+#endif
+typedef struct _gsl_rbmemptrs_t {
+    volatile int  rptr;
+    int           wptr_poll;
+} gsl_rbmemptrs_t;
+#pragma pack(pop)
+
+// -----
+// stats
+// -----
+typedef struct _gsl_rbstats_t {
+    __int64  wraps;
+    __int64  issues;
+    __int64  wordstotal;
+} gsl_rbstats_t;
+
+
+// -----------------
+// ringbuffer object
+// -----------------
+typedef struct _gsl_ringbuffer_t {
+
+    gsl_device_t      *device;
+    gsl_flags_t       flags;
+
+    gsl_memdesc_t     buffer_desc;              // allocated memory descriptor
+    gsl_memdesc_t     memptrs_desc;
+
+    gsl_rbmemptrs_t   *memptrs;
+
+    unsigned int      sizedwords;               // ring buffer size dwords
+    unsigned int      blksizequadwords;
+
+    unsigned int      wptr;                     // write pointer offset in dwords from baseaddr
+    unsigned int      rptr;                     // read pointer  offset in dwords from baseaddr
+    gsl_timestamp_t   timestamp;
+
+
+    gsl_rbwatchdog_t  watchdog;
+
+#ifdef GSL_STATS_RINGBUFFER
+    gsl_rbstats_t     stats;
+#endif // GSL_STATS_RINGBUFFER
+
+} gsl_ringbuffer_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+
+// ----------
+// ring write
+// ----------
+#define GSL_RB_WRITE(ring, data)        \
+      KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_WRT, (unsigned int)ring, data, 0, "GSL_RB_WRITE")); \
+      *(unsigned int *)(ring)++ = (unsigned int)(data);
+
+// ---------
+// timestamp
+// ---------
+#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+#define GSL_RB_USE_MEM_TIMESTAMP
+#endif //GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifdef  GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x1     // enable timestamp (...scratch0) memory shadowing
+#define GSL_RB_INIT_TIMESTAMP(rb)
+
+#else
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x0     // disable
+#define GSL_RB_INIT_TIMESTAMP(rb)           kgsl_device_regwrite((rb)->device->id, mmCP_TIMESTAMP, 0);
+#endif // GSL_RB_USE_MEMTIMESTAMP
+
+// --------
+// mem rptr
+// --------
+#ifdef  GSL_RB_USE_MEM_RPTR
+#define GSL_RB_CNTL_NO_UPDATE               0x0     // enable
+#define GSL_RB_GET_READPTR(rb, data)        kgsl_sharedmem_read0(&(rb)->memptrs_desc, (data), GSL_RB_MEMPTRS_RPTR_OFFSET, 4, false)
+#else
+#define GSL_RB_CNTL_NO_UPDATE               0x1     // disable
+#define GSL_RB_GET_READPTR(rb, data)        (rb)->device->fbtl.device_regread((rb)->device, mmCP_RB_RPTR,(data))
+#endif // GSL_RB_USE_MEMRPTR
+
+// ------------
+// wptr polling
+// ------------
+#ifdef  GSL_RB_USE_WPTR_POLLING
+#define GSL_RB_CNTL_POLL_EN                 0x1     // enable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)      (rb)->memptrs->wptr_poll = (rb)->wptr
+#else
+#define GSL_RB_CNTL_POLL_EN                 0x0     // disable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)
+#endif  // GSL_RB_USE_WPTR_POLLING
+
+// -----
+// stats
+// -----
+#ifdef GSL_STATS_RINGBUFFER
+#define GSL_RB_STATS(x) x
+#else
+#define GSL_RB_STATS(x)
+#endif // GSL_STATS_RINGBUFFER
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_ringbuffer_init(gsl_device_t *device);
+int             kgsl_ringbuffer_close(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_start(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb);
+gsl_timestamp_t	kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmdaddr, int sizedwords, unsigned int pid);
+int             kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+void            kgsl_ringbuffer_watchdog(void);
+
+int             kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats);
+int             kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb);
+
+#endif  // __GSL_RINGBUFFER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_sharedmem.h b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
new file mode 100644
index 000000000000..bb9692cc1e44
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
@@ -0,0 +1,110 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_SHAREDMEM_H
+#define __GSL_SHAREDMEM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_APERTURE_MASK                   0x000000FF
+#define GSL_DEVICEID_MASK                   0x0000FF00
+#define GSL_EXTALLOC_MASK                   0x000F0000
+
+#define GSL_APERTURE_SHIFT                  0
+#define GSL_DEVICEID_SHIFT                  8
+#define GSL_EXTALLOC_SHIFT                  16
+
+#define GSL_APERTURE_GETGPUADDR(shmem, aperture_index)  \
+    shmem.apertures[aperture_index].memarena->gpubaseaddr;
+
+#define GSL_APERTURE_GETHOSTADDR(shmem, aperture_index) \
+    shmem.apertures[aperture_index].memarena->hostbaseaddr;
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------------------
+// memory aperture stats
+// ---------------------
+typedef struct _gsl_aperture_stats_t
+{
+    gsl_apertureid_t      id;
+    gsl_channelid_t       channel;
+    gsl_memarena_stats_t  memarena;
+} gsl_aperture_stats_t;
+
+// -------------------
+// shared memory stats
+// -------------------
+typedef struct _gsl_sharedmem_stats_t
+{
+    gsl_aperture_stats_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_sharedmem_stats_t;
+
+// ---------------
+// memory aperture
+// ---------------
+typedef struct _gsl_aperture_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    int               numbanks;
+    gsl_memarena_t    *memarena;
+} gsl_aperture_t;
+
+// --------------------
+// shared memory object
+// --------------------
+typedef struct _gsl_sharedmem_t
+{
+    gsl_flags_t     flags;
+    unsigned int    priv;
+    int             numapertures;
+    gsl_aperture_t  apertures[GSL_SHMEM_MAX_APERTURES]; 
+    int             aperturelookup[GSL_APERTURE_MAX][GSL_CHANNEL_MAX];
+} gsl_sharedmem_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_sharedmem_init(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_close(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+int             kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid);
+int             kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+int             kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+int             kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+int             kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats);
+unsigned int    kgsl_sharedmem_convertaddr(unsigned int addr, int type);
+
+#endif // __GSL_SHAREDMEM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_tbdump.h b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
new file mode 100644
index 000000000000..53b30a8442e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TBDUMP_H
+#define __GSL_TBDUMP_H
+
+void tbdump_open(char* filename);
+void tbdump_close();
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes);
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes);
+void tbdump_slavewrite(unsigned int addr, unsigned int value);
+
+#endif // __GSL_TBDUMP_H
diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
new file mode 100644
index 000000000000..d12d419822a2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _G12_H
+#define _G12_H
+
+#ifdef _Z180
+#include "vgc/vgregs_z180.h"
+#include "vgc/vgenums_z180.h"
+#else
+#include "vgc/vgregs_z160.h"
+#include "vgc/vgenums_z160.h"
+#endif
+
+#endif // _G12_H
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
new file mode 100644
index 000000000000..911c22fbbba6
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
@@ -0,0 +1,291 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_ENUMS_H
+#define __REGS_ENUMS_H
+
+typedef enum _BB_CULL {
+    BB_CULL_NONE                     = 0,
+    BB_CULL_CW                       = 1,
+    BB_CULL_CCW                      = 2,
+} BB_CULL;
+
+typedef enum _BB_TEXTUREADDRESS {
+    BB_TADDRESS_WRAP                 = 0,
+    BB_TADDRESS_CLAMP                = 1,
+    BB_TADDRESS_BORDER               = 2,
+    BB_TADDRESS_MIRROR               = 4,
+    BB_TADDRESS_MIRRORCLAMP          = 5,   // Not supported on G3x cores
+    BB_TADDRESS_MIRRORBORDER         = 6,   // Not supported on G3x cores
+} BB_TEXTUREADDRESS;
+
+typedef enum _BB_TEXTYPE {
+    BB_TEXTYPE_4444                  = 0,
+    BB_TEXTYPE_1555                  = 1,
+    BB_TEXTYPE_5551                  = 2,
+    BB_TEXTYPE_565                   = 3,
+    BB_TEXTYPE_8888                  = 4,
+    BB_TEXTYPE_8                     = 5,
+    BB_TEXTYPE_88                    = 6,
+    BB_TEXTYPE_4                     = 7,
+    BB_TEXTYPE_44                    = 8,
+    BB_TEXTYPE_UYVY                  = 9,
+    BB_TEXTYPE_YUY2                  = 10,
+    BB_TEXTYPE_YVYU                  = 11,
+    BB_TEXTYPE_DXT1                  = 12,
+    BB_TEXTYPE_PACKMAN               = 13,
+    BB_TEXTYPE_PACKMAN_ALPHA4        = 14,
+    BB_TEXTYPE_1F16                  = 15,
+    BB_TEXTYPE_2F16                  = 16,
+    BB_TEXTYPE_4F16                  = 17,
+    BB_TEXTYPE_IPACKMAN_RGB          = 18,
+    BB_TEXTYPE_IPACKMAN_RGBA         = 19,
+} BB_TEXTYPE;
+
+typedef enum _BB_CMPFUNC {
+    BB_CMP_NEVER                     = 0,
+    BB_CMP_LESS                      = 1,
+    BB_CMP_EQUAL                     = 2,
+    BB_CMP_LESSEQUAL                 = 3,
+    BB_CMP_GREATER                   = 4,
+    BB_CMP_NOTEQUAL                  = 5,
+    BB_CMP_GREATEREQUAL              = 6,
+    BB_CMP_ALWAYS                    = 7,
+} BB_CMPFUNC;
+
+typedef enum _BB_STENCILOP {
+    BB_STENCILOP_KEEP                = 0,
+    BB_STENCILOP_ZERO                = 1,
+    BB_STENCILOP_REPLACE             = 2,
+    BB_STENCILOP_INCRSAT             = 3,
+    BB_STENCILOP_DECRSAT             = 4,
+    BB_STENCILOP_INVERT              = 5,
+    BB_STENCILOP_INCR                = 6,
+    BB_STENCILOP_DECR                = 7,
+} BB_STENCILOP;
+
+typedef enum _BB_PRIMITIVETYPE {
+    BB_PT_POINTLIST                  = 0,
+    BB_PT_LINELIST                   = 1,
+    BB_PT_LINESTRIP                  = 2,
+    BB_PT_TRIANGLELIST               = 3,
+    BB_PT_TRIANGLESTRIP              = 4,
+    BB_PT_TRIANGLEFAN                = 5,
+} BB_PRIMITIVETYPE;
+
+typedef enum _BB_TEXTUREFILTERTYPE {
+    BB_TEXF_NONE                     = 0,   // filtering disabled (valid for mip filter only)
+    BB_TEXF_POINT                    = 1,   // nearest
+    BB_TEXF_LINEAR                   = 2,   // linear interpolation
+} BB_TEXTUREFILTERTYPE;
+
+typedef enum _BB_BUFFER {
+    BB_BUFFER_PPCODE                 = 0,   // Pixel processor code
+    BB_BUFFER_UNUSED                 = 1,   // Unused
+    BB_BUFFER_CBUF                   = 2,   // Color buffer
+    BB_BUFFER_ZBUF                   = 3,   // Z buffer
+    BB_BUFFER_AUXBUF0                = 4,   // AUX0 buffer
+    BB_BUFFER_AUXBUF1                = 5,   // AUX1 buffer
+    BB_BUFFER_AUXBUF2                = 6,   // AUX2 buffer
+    BB_BUFFER_AUXBUF3                = 7,   // AUX3 buffer
+} BB_BUFFER;
+
+typedef enum _BB_COLORFORMAT {
+    BB_COLOR_ARGB4444                = 0,
+    BB_COLOR_ARGB0565                = 1,
+    BB_COLOR_ARGB1555                = 2,
+    BB_COLOR_RGBA5551                = 3,
+    BB_COLOR_ARGB8888                = 4,
+    BB_COLOR_R16                     = 5,
+    BB_COLOR_RG1616                  = 6,
+    BB_COLOR_ARGB16161616            = 7,
+    BB_COLOR_D16                     = 8,
+    BB_COLOR_S4D12                   = 9,
+    BB_COLOR_S1D15                   = 10,
+    BB_COLOR_X8D24                   = 11,
+    BB_COLOR_S8D24                   = 12,
+    BB_COLOR_X2D30                   = 13,
+} BB_COLORFORMAT;
+
+typedef enum _BB_PP_REGCONFIG {
+    BB_PP_REGCONFIG_1                = 0,
+    BB_PP_REGCONFIG_2                = 1,
+    BB_PP_REGCONFIG_3                = 8,
+    BB_PP_REGCONFIG_4                = 2,
+    BB_PP_REGCONFIG_6                = 9,
+    BB_PP_REGCONFIG_8                = 3,
+    BB_PP_REGCONFIG_12               = 10,
+    BB_PP_REGCONFIG_16               = 4,
+    BB_PP_REGCONFIG_24               = 11,
+    BB_PP_REGCONFIG_32               = 5,
+} BB_PP_REGCONFIG;
+
+typedef enum _G2D_read_t {
+    G2D_READ_DST                     = 0,
+    G2D_READ_SRC1                    = 1,
+    G2D_READ_SRC2                    = 2,
+    G2D_READ_SRC3                    = 3,
+} G2D_read_t;
+
+typedef enum _G2D_format_t {
+    G2D_1                            = 0,   // foreground & background
+    G2D_1BW                          = 1,   // black & white
+    G2D_4                            = 2,
+    G2D_8                            = 3,   // alpha
+    G2D_4444                         = 4,
+    G2D_1555                         = 5,
+    G2D_0565                         = 6,
+    G2D_8888                         = 7,
+    G2D_YUY2                         = 8,
+    G2D_UYVY                         = 9,
+    G2D_YVYU                         = 10,
+    G2D_4444_RGBA                    = 11,
+    G2D_5551_RGBA                    = 12,
+    G2D_8888_RGBA                    = 13,
+    G2D_A8                           = 14,  // for alpha texture only
+} G2D_format_t;
+
+typedef enum _G2D_wrap_t {
+    G2D_WRAP_CLAMP                   = 0,
+    G2D_WRAP_REPEAT                  = 1,
+    G2D_WRAP_MIRROR                  = 2,
+    G2D_WRAP_BORDER                  = 3,
+} G2D_wrap_t;
+
+typedef enum _G2D_BLEND_OP {
+    G2D_BLENDOP_ADD                  = 0,
+    G2D_BLENDOP_SUB                  = 1,
+    G2D_BLENDOP_MIN                  = 2,
+    G2D_BLENDOP_MAX                  = 3,
+} G2D_BLEND_OP;
+
+typedef enum _G2D_GRAD_OP {
+    G2D_GRADOP_DOT                   = 0,
+    G2D_GRADOP_RCP                   = 1,
+    G2D_GRADOP_SQRTMUL               = 2,
+    G2D_GRADOP_SQRTADD               = 3,
+} G2D_GRAD_OP;
+
+typedef enum _G2D_BLEND_SRC {
+    G2D_BLENDSRC_ZERO                = 0,   // One with invert
+    G2D_BLENDSRC_SOURCE              = 1,   // Paint with coverage alpha applied
+    G2D_BLENDSRC_DESTINATION         = 2,
+    G2D_BLENDSRC_IMAGE               = 3,   // Second texture
+    G2D_BLENDSRC_TEMP0               = 4,
+    G2D_BLENDSRC_TEMP1               = 5,
+    G2D_BLENDSRC_TEMP2               = 6,
+} G2D_BLEND_SRC;
+
+typedef enum _G2D_BLEND_DST {
+    G2D_BLENDDST_IGNORE              = 0,   // Ignore destination
+    G2D_BLENDDST_TEMP0               = 1,
+    G2D_BLENDDST_TEMP1               = 2,
+    G2D_BLENDDST_TEMP2               = 3,
+} G2D_BLEND_DST;
+
+typedef enum _G2D_BLEND_CONST {
+    G2D_BLENDSRC_CONST0              = 0,
+    G2D_BLENDSRC_CONST1              = 1,
+    G2D_BLENDSRC_CONST2              = 2,
+    G2D_BLENDSRC_CONST3              = 3,
+    G2D_BLENDSRC_CONST4              = 4,
+    G2D_BLENDSRC_CONST5              = 5,
+    G2D_BLENDSRC_CONST6              = 6,
+    G2D_BLENDSRC_CONST7              = 7,
+} G2D_BLEND_CONST;
+
+typedef enum _V3_NEXTCMD {
+    VGV3_NEXTCMD_CONTINUE            = 0,   // Continue reading at current address, COUNT gives size of next packet.
+    VGV3_NEXTCMD_JUMP                = 1,   // Jump to CALLADDR, COUNT gives size of next packet.
+    VGV3_NEXTCMD_CALL                = 2,   // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue.
+    VGV3_NEXTCMD_CALLV2TRUE          = 3,   // Not supported.
+    VGV3_NEXTCMD_CALLV2FALSE         = 4,   // Not supported.
+    VGV3_NEXTCMD_ABORT               = 5,   // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost.
+} V3_NEXTCMD;
+
+typedef enum _V3_FORMAT {
+    VGV3_FORMAT_S8                   = 0,   // Signed 8 bit data (4 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S16                  = 1,   // Signed 16 bit data (2 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S32                  = 2,   // Signed 32 bit data => VGV2-float
+    VGV3_FORMAT_F32                  = 3,   // IEEE 32-bit floating point => VGV2-float
+    VGV3_FORMAT_RAW                  = 4,   // No conversion
+} V3_FORMAT;
+
+typedef enum _V2_ACTION {
+    VGV2_ACTION_END                  = 0,   // end previous path
+    VGV2_ACTION_MOVETOOPEN           = 1,   // end previous path, C1=C4, start new open subpath
+    VGV2_ACTION_MOVETOCLOSED         = 2,   // end previous path, C1=C4, start new closed subpath
+    VGV2_ACTION_LINETO               = 3,   // line C1,C4
+    VGV2_ACTION_CUBICTO              = 4,   // cubic C1,C2,C3,C4.
+    VGV2_ACTION_QUADTO               = 5,   // quadratic C1,C3,C4.
+    VGV2_ACTION_SCUBICTO             = 6,   // smooth cubic C1,C4.
+    VGV2_ACTION_SQUADTO              = 7,   // smooth quadratic C1,C3,C4.
+    VGV2_ACTION_VERTEXTO             = 8,   // half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOOPEN         = 9,   // moveto open + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOCLOSED       = 10,  // moveto closed + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_MOVETOMOVE           = 11,  // end previous path, C1=C4, move but do not start a subpath
+    VGV2_ACTION_FLUSH                = 15,  // end previous path and block following regwrites until all lines sent
+} V2_ACTION;
+
+typedef enum _V2_CAP {
+    VGV2_CAP_BUTT                    = 0,   // butt caps (straight line overlappin starting point
+    VGV2_CAP_ROUND                   = 1,   // round caps (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_CAP_SQUARE                  = 2,   // square caps (square centered on starting point)
+} V2_CAP;
+
+typedef enum _V2_JOIN {
+    VGV2_JOIN_MITER                  = 0,   // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL.
+    VGV2_JOIN_ROUND                  = 1,   // round joins (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_JOIN_BEVEL                  = 2,   // bevel joins (ends of both sides are connected with a single line)
+} V2_JOIN;
+
+enum
+{
+    G2D_GRADREG_X        = 0,  // also usable as temp
+    G2D_GRADREG_Y        = 1,  // also usable as temp
+    G2D_GRADREG_OUTX     = 8,
+    G2D_GRADREG_OUTY     = 9,
+    G2D_GRADREG_C0       = 16,
+    G2D_GRADREG_C1       = 17,
+    G2D_GRADREG_C2       = 18,
+    G2D_GRADREG_C3       = 19,
+    G2D_GRADREG_C4       = 20,
+    G2D_GRADREG_C5       = 21,
+    G2D_GRADREG_C6       = 22,
+    G2D_GRADREG_C7       = 23,
+    G2D_GRADREG_C8       = 24,
+    G2D_GRADREG_C9       = 25,
+    G2D_GRADREG_C10      = 26,
+    G2D_GRADREG_C11      = 27,
+    G2D_GRADREG_ZERO     = 28,
+    G2D_GRADREG_ONE      = 29,
+    G2D_GRADREG_MINUSONE = 30,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
new file mode 100644
index 000000000000..1660bc1c12a9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
@@ -0,0 +1,3775 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_G4X_DRIVER_H
+#define __REGS_G4X_DRIVER_H
+
+#ifndef _LINUX
+#include <assert.h>
+#else
+#ifndef assert
+#define assert(expr)
+#endif
+#endif
+
+//-----------------------------------------------------
+// REGISTER ADDRESSES
+//-----------------------------------------------------
+
+#define ADDR_FBC_BASE                    0x84
+#define ADDR_FBC_DATA                    0x86
+#define ADDR_FBC_HEIGHT                  0x8a
+#define ADDR_FBC_START                   0x8e
+#define ADDR_FBC_STRIDE                  0x8c
+#define ADDR_FBC_WIDTH                   0x88
+#define ADDR_VGC_CLOCKEN                 0x508
+#define ADDR_VGC_COMMANDSTREAM           0x0
+#define ADDR_VGC_FIFOFREE                0x7c0
+#define ADDR_VGC_IRQENABLE               0x438
+#define ADDR_VGC_IRQSTATUS               0x418
+#define ADDR_VGC_IRQ_ACTIVE_CNT          0x4e0
+#define ADDR_VGC_MMUCOMMANDSTREAM        0x3fc
+#define ADDR_VGC_REVISION                0x400
+#define ADDR_VGC_SYSSTATUS               0x410
+#define ADDR_G2D_ALPHABLEND              0xc
+#define ADDR_G2D_BACKGROUND              0xb
+#define ADDR_G2D_BASE0                   0x0
+#define ADDR_G2D_BASE1                   0x2
+#define ADDR_G2D_BASE2                   0x4
+#define ADDR_G2D_BASE3                   0x6
+#define ADDR_G2D_BLENDERCFG              0x11
+#define ADDR_G2D_BLEND_A0                0x14
+#define ADDR_G2D_BLEND_A1                0x15
+#define ADDR_G2D_BLEND_A2                0x16
+#define ADDR_G2D_BLEND_A3                0x17
+#define ADDR_G2D_BLEND_C0                0x18
+#define ADDR_G2D_BLEND_C1                0x19
+#define ADDR_G2D_BLEND_C2                0x1a
+#define ADDR_G2D_BLEND_C3                0x1b
+#define ADDR_G2D_BLEND_C4                0x1c
+#define ADDR_G2D_BLEND_C5                0x1d
+#define ADDR_G2D_BLEND_C6                0x1e
+#define ADDR_G2D_BLEND_C7                0x1f
+#define ADDR_G2D_CFG0                    0x1
+#define ADDR_G2D_CFG1                    0x3
+#define ADDR_G2D_CFG2                    0x5
+#define ADDR_G2D_CFG3                    0x7
+#define ADDR_G2D_COLOR                   0xff
+#define ADDR_G2D_CONFIG                  0xe
+#define ADDR_G2D_CONST0                  0xb0
+#define ADDR_G2D_CONST1                  0xb1
+#define ADDR_G2D_CONST2                  0xb2
+#define ADDR_G2D_CONST3                  0xb3
+#define ADDR_G2D_CONST4                  0xb4
+#define ADDR_G2D_CONST5                  0xb5
+#define ADDR_G2D_CONST6                  0xb6
+#define ADDR_G2D_CONST7                  0xb7
+#define ADDR_G2D_FOREGROUND              0xa
+#define ADDR_G2D_GRADIENT                0xd0
+#define ADDR_G2D_IDLE                    0xfe
+#define ADDR_G2D_INPUT                   0xf
+#define ADDR_G2D_MASK                    0x10
+#define ADDR_G2D_ROP                     0xd
+#define ADDR_G2D_SCISSORX                0x8
+#define ADDR_G2D_SCISSORY                0x9
+#define ADDR_G2D_SXY                     0xf2
+#define ADDR_G2D_SXY2                    0xf3
+#define ADDR_G2D_VGSPAN                  0xf4
+#define ADDR_G2D_WIDTHHEIGHT             0xf1
+#define ADDR_G2D_XY                      0xf0
+#define ADDR_GRADW_BORDERCOLOR           0xd4
+#define ADDR_GRADW_CONST0                0xc0
+#define ADDR_GRADW_CONST1                0xc1
+#define ADDR_GRADW_CONST2                0xc2
+#define ADDR_GRADW_CONST3                0xc3
+#define ADDR_GRADW_CONST4                0xc4
+#define ADDR_GRADW_CONST5                0xc5
+#define ADDR_GRADW_CONST6                0xc6
+#define ADDR_GRADW_CONST7                0xc7
+#define ADDR_GRADW_CONST8                0xc8
+#define ADDR_GRADW_CONST9                0xc9
+#define ADDR_GRADW_CONSTA                0xca
+#define ADDR_GRADW_CONSTB                0xcb
+#define ADDR_GRADW_INST0                 0xe0
+#define ADDR_GRADW_INST1                 0xe1
+#define ADDR_GRADW_INST2                 0xe2
+#define ADDR_GRADW_INST3                 0xe3
+#define ADDR_GRADW_INST4                 0xe4
+#define ADDR_GRADW_INST5                 0xe5
+#define ADDR_GRADW_INST6                 0xe6
+#define ADDR_GRADW_INST7                 0xe7
+#define ADDR_GRADW_TEXBASE               0xd3
+#define ADDR_GRADW_TEXCFG                0xd1
+#define ADDR_GRADW_TEXSIZE               0xd2
+#define ADDR_MH_ARBITER_CONFIG           0xa40
+#define ADDR_MH_AXI_ERROR                0xa45
+#define ADDR_MH_AXI_HALT_CONTROL         0xa50
+#define ADDR_MH_CLNT_AXI_ID_REUSE        0xa41
+#define ADDR_MH_DEBUG_CTRL               0xa4e
+#define ADDR_MH_DEBUG_DATA               0xa4f
+#define ADDR_MH_INTERRUPT_CLEAR          0xa44
+#define ADDR_MH_INTERRUPT_MASK           0xa42
+#define ADDR_MH_INTERRUPT_STATUS         0xa43
+#define ADDR_MH_MMU_CONFIG               0x40
+#define ADDR_MH_MMU_INVALIDATE           0x45
+#define ADDR_MH_MMU_MPU_BASE             0x46
+#define ADDR_MH_MMU_MPU_END              0x47
+#define ADDR_MH_MMU_PAGE_FAULT           0x43
+#define ADDR_MH_MMU_PT_BASE              0x42
+#define ADDR_MH_MMU_TRAN_ERROR           0x44
+#define ADDR_MH_MMU_VA_RANGE             0x41
+#define ADDR_MH_PERFCOUNTER0_CONFIG      0xa47
+#define ADDR_MH_PERFCOUNTER0_HI          0xa49
+#define ADDR_MH_PERFCOUNTER0_LOW         0xa48
+#define ADDR_MH_PERFCOUNTER0_SELECT      0xa46
+#define ADDR_MH_PERFCOUNTER1_CONFIG      0xa4b
+#define ADDR_MH_PERFCOUNTER1_HI          0xa4d
+#define ADDR_MH_PERFCOUNTER1_LOW         0xa4c
+#define ADDR_MH_PERFCOUNTER1_SELECT      0xa4a
+#define ADDR_MMU_READ_ADDR               0x510
+#define ADDR_MMU_READ_DATA               0x518
+#define ADDR_VGV1_CBASE1                 0x2a
+#define ADDR_VGV1_CFG1                   0x27
+#define ADDR_VGV1_CFG2                   0x28
+#define ADDR_VGV1_DIRTYBASE              0x29
+#define ADDR_VGV1_FILL                   0x23
+#define ADDR_VGV1_SCISSORX               0x24
+#define ADDR_VGV1_SCISSORY               0x25
+#define ADDR_VGV1_TILEOFS                0x22
+#define ADDR_VGV1_UBASE2                 0x2b
+#define ADDR_VGV1_VTX0                   0x20
+#define ADDR_VGV1_VTX1                   0x21
+#define ADDR_VGV2_ACCURACY               0x60
+#define ADDR_VGV2_ACTION                 0x6f
+#define ADDR_VGV2_ARCCOS                 0x62
+#define ADDR_VGV2_ARCSIN                 0x63
+#define ADDR_VGV2_ARCTAN                 0x64
+#define ADDR_VGV2_BBOXMAXX               0x5c
+#define ADDR_VGV2_BBOXMAXY               0x5d
+#define ADDR_VGV2_BBOXMINX               0x5a
+#define ADDR_VGV2_BBOXMINY               0x5b
+#define ADDR_VGV2_BIAS                   0x5f
+#define ADDR_VGV2_C1X                    0x40
+#define ADDR_VGV2_C1XREL                 0x48
+#define ADDR_VGV2_C1Y                    0x41
+#define ADDR_VGV2_C1YREL                 0x49
+#define ADDR_VGV2_C2X                    0x42
+#define ADDR_VGV2_C2XREL                 0x4a
+#define ADDR_VGV2_C2Y                    0x43
+#define ADDR_VGV2_C2YREL                 0x4b
+#define ADDR_VGV2_C3X                    0x44
+#define ADDR_VGV2_C3XREL                 0x4c
+#define ADDR_VGV2_C3Y                    0x45
+#define ADDR_VGV2_C3YREL                 0x4d
+#define ADDR_VGV2_C4X                    0x46
+#define ADDR_VGV2_C4XREL                 0x4e
+#define ADDR_VGV2_C4Y                    0x47
+#define ADDR_VGV2_C4YREL                 0x4f
+#define ADDR_VGV2_CLIP                   0x68
+#define ADDR_VGV2_FIRST                  0x40
+#define ADDR_VGV2_LAST                   0x6f
+#define ADDR_VGV2_MITER                  0x66
+#define ADDR_VGV2_MODE                   0x6e
+#define ADDR_VGV2_RADIUS                 0x65
+#define ADDR_VGV2_SCALE                  0x5e
+#define ADDR_VGV2_THINRADIUS             0x61
+#define ADDR_VGV2_XFSTXX                 0x56
+#define ADDR_VGV2_XFSTXY                 0x58
+#define ADDR_VGV2_XFSTYX                 0x57
+#define ADDR_VGV2_XFSTYY                 0x59
+#define ADDR_VGV2_XFXA                   0x54
+#define ADDR_VGV2_XFXX                   0x50
+#define ADDR_VGV2_XFXY                   0x52
+#define ADDR_VGV2_XFYA                   0x55
+#define ADDR_VGV2_XFYX                   0x51
+#define ADDR_VGV2_XFYY                   0x53
+#define ADDR_VGV3_CONTROL                0x70
+#define ADDR_VGV3_FIRST                  0x70
+#define ADDR_VGV3_LAST                   0x7f
+#define ADDR_VGV3_MODE                   0x71
+#define ADDR_VGV3_NEXTADDR               0x75
+#define ADDR_VGV3_NEXTCMD                0x76
+#define ADDR_VGV3_VGBYPASS               0x77
+#define ADDR_VGV3_WRITE                  0x73
+#define ADDR_VGV3_WRITEADDR              0x72
+#define ADDR_VGV3_WRITEDMI               0x7d
+#define ADDR_VGV3_WRITEF32               0x7b
+#define ADDR_VGV3_WRITEIFPAUSED          0x74
+#define ADDR_VGV3_WRITERAW               0x7c
+#define ADDR_VGV3_WRITES16               0x79
+#define ADDR_VGV3_WRITES32               0x7a
+#define ADDR_VGV3_WRITES8                0x78
+
+// FBC_BASE
+typedef struct _REG_FBC_BASE {
+    unsigned BASE                : 32;
+} REG_FBC_BASE;
+
+// FBC_DATA
+typedef struct _REG_FBC_DATA {
+    unsigned DATA                : 32;
+} REG_FBC_DATA;
+
+// FBC_HEIGHT
+typedef struct _REG_FBC_HEIGHT {
+    unsigned HEIGHT              : 11;
+} REG_FBC_HEIGHT;
+
+// FBC_START
+typedef struct _REG_FBC_START {
+    unsigned DUMMY               : 1;
+} REG_FBC_START;
+
+// FBC_STRIDE
+typedef struct _REG_FBC_STRIDE {
+    unsigned STRIDE              : 11;
+} REG_FBC_STRIDE;
+
+// FBC_WIDTH
+typedef struct _REG_FBC_WIDTH {
+    unsigned WIDTH               : 11;
+} REG_FBC_WIDTH;
+
+// VGC_CLOCKEN
+typedef struct _REG_VGC_CLOCKEN {
+    unsigned BCACHE              : 1;
+    unsigned G2D_VGL3            : 1;
+    unsigned VG_L1L2             : 1;
+    unsigned RESERVED            : 3;
+} REG_VGC_CLOCKEN;
+
+// VGC_COMMANDSTREAM
+typedef struct _REG_VGC_COMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_COMMANDSTREAM;
+
+// VGC_FIFOFREE
+typedef struct _REG_VGC_FIFOFREE {
+    unsigned FREE                : 1;
+} REG_VGC_FIFOFREE;
+
+// VGC_IRQENABLE
+typedef struct _REG_VGC_IRQENABLE {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQENABLE;
+
+// VGC_IRQSTATUS
+typedef struct _REG_VGC_IRQSTATUS {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQSTATUS;
+
+// VGC_IRQ_ACTIVE_CNT
+typedef struct _REG_VGC_IRQ_ACTIVE_CNT {
+    unsigned MH                  : 8;
+    unsigned G2D                 : 8;
+    unsigned ERRORS              : 8;
+    unsigned FBC                 : 8;
+} REG_VGC_IRQ_ACTIVE_CNT;
+
+// VGC_MMUCOMMANDSTREAM
+typedef struct _REG_VGC_MMUCOMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_MMUCOMMANDSTREAM;
+
+// VGC_REVISION
+typedef struct _REG_VGC_REVISION {
+    unsigned MINOR_REVISION      : 4;
+    unsigned MAJOR_REVISION      : 4;
+} REG_VGC_REVISION;
+
+// VGC_SYSSTATUS
+typedef struct _REG_VGC_SYSSTATUS {
+    unsigned RESET               : 1;
+} REG_VGC_SYSSTATUS;
+
+// G2D_ALPHABLEND
+typedef struct _REG_G2D_ALPHABLEND {
+    unsigned ALPHA               : 8;
+    unsigned OBS_ENABLE          : 1;
+    unsigned CONSTANT            : 1;
+    unsigned INVERT              : 1;
+    unsigned OPTIMIZE            : 1;
+    unsigned MODULATE            : 1;
+    unsigned INVERTMASK          : 1;
+    unsigned PREMULTIPLYDST      : 1;
+    unsigned MASKTOALPHA         : 1;
+} REG_G2D_ALPHABLEND;
+
+// G2D_BACKGROUND
+typedef struct _REG_G2D_BACKGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_BACKGROUND;
+
+// G2D_BASE0
+typedef struct _REG_G2D_BASE0 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE0;
+
+// G2D_BASE1
+typedef struct _REG_G2D_BASE1 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE1;
+
+// G2D_BASE2
+typedef struct _REG_G2D_BASE2 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE2;
+
+// G2D_BASE3
+typedef struct _REG_G2D_BASE3 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE3;
+
+// G2D_BLENDERCFG
+typedef struct _REG_G2D_BLENDERCFG {
+    unsigned PASSES              : 3;
+    unsigned ALPHAPASSES         : 2;
+    unsigned ENABLE              : 1;
+    unsigned OOALPHA             : 1;
+    unsigned OBS_DIVALPHA        : 1;
+    unsigned NOMASK              : 1;
+} REG_G2D_BLENDERCFG;
+
+// G2D_BLEND_A0
+typedef struct _REG_G2D_BLEND_A0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A0;
+
+// G2D_BLEND_A1
+typedef struct _REG_G2D_BLEND_A1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A1;
+
+// G2D_BLEND_A2
+typedef struct _REG_G2D_BLEND_A2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A2;
+
+// G2D_BLEND_A3
+typedef struct _REG_G2D_BLEND_A3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A3;
+
+// G2D_BLEND_C0
+typedef struct _REG_G2D_BLEND_C0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C0;
+
+// G2D_BLEND_C1
+typedef struct _REG_G2D_BLEND_C1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C1;
+
+// G2D_BLEND_C2
+typedef struct _REG_G2D_BLEND_C2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C2;
+
+// G2D_BLEND_C3
+typedef struct _REG_G2D_BLEND_C3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C3;
+
+// G2D_BLEND_C4
+typedef struct _REG_G2D_BLEND_C4 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C4;
+
+// G2D_BLEND_C5
+typedef struct _REG_G2D_BLEND_C5 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C5;
+
+// G2D_BLEND_C6
+typedef struct _REG_G2D_BLEND_C6 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C6;
+
+// G2D_BLEND_C7
+typedef struct _REG_G2D_BLEND_C7 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C7;
+
+// G2D_CFG0
+typedef struct _REG_G2D_CFG0 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG0;
+
+// G2D_CFG1
+typedef struct _REG_G2D_CFG1 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG1;
+
+// G2D_CFG2
+typedef struct _REG_G2D_CFG2 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG2;
+
+// G2D_CFG3
+typedef struct _REG_G2D_CFG3 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG3;
+
+// G2D_COLOR
+typedef struct _REG_G2D_COLOR {
+    unsigned ARGB                : 32;
+} REG_G2D_COLOR;
+
+// G2D_CONFIG
+typedef struct _REG_G2D_CONFIG {
+    unsigned DST                 : 1;
+    unsigned SRC1                : 1;
+    unsigned SRC2                : 1;
+    unsigned SRC3                : 1;
+    unsigned SRCCK               : 1;
+    unsigned DSTCK               : 1;
+    unsigned ROTATE              : 2;
+    unsigned OBS_GAMMA           : 1;
+    unsigned IGNORECKALPHA       : 1;
+    unsigned DITHER              : 1;
+    unsigned WRITESRGB           : 1;
+    unsigned ARGBMASK            : 4;
+    unsigned ALPHATEX            : 1;
+    unsigned PALMLINES           : 1;
+    unsigned NOLASTPIXEL         : 1;
+    unsigned NOPROTECT           : 1;
+} REG_G2D_CONFIG;
+
+// G2D_CONST0
+typedef struct _REG_G2D_CONST0 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST0;
+
+// G2D_CONST1
+typedef struct _REG_G2D_CONST1 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST1;
+
+// G2D_CONST2
+typedef struct _REG_G2D_CONST2 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST2;
+
+// G2D_CONST3
+typedef struct _REG_G2D_CONST3 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST3;
+
+// G2D_CONST4
+typedef struct _REG_G2D_CONST4 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST4;
+
+// G2D_CONST5
+typedef struct _REG_G2D_CONST5 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST5;
+
+// G2D_CONST6
+typedef struct _REG_G2D_CONST6 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST6;
+
+// G2D_CONST7
+typedef struct _REG_G2D_CONST7 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST7;
+
+// G2D_FOREGROUND
+typedef struct _REG_G2D_FOREGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_FOREGROUND;
+
+// G2D_GRADIENT
+typedef struct _REG_G2D_GRADIENT {
+    unsigned INSTRUCTIONS        : 3;
+    unsigned INSTRUCTIONS2       : 3;
+    unsigned ENABLE              : 1;
+    unsigned ENABLE2             : 1;
+    unsigned SEL                 : 1;
+} REG_G2D_GRADIENT;
+
+// G2D_IDLE
+typedef struct _REG_G2D_IDLE {
+    unsigned IRQ                 : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V3                  : 1;
+} REG_G2D_IDLE;
+
+// G2D_INPUT
+typedef struct _REG_G2D_INPUT {
+    unsigned COLOR               : 1;
+    unsigned SCOORD1             : 1;
+    unsigned SCOORD2             : 1;
+    unsigned COPYCOORD           : 1;
+    unsigned VGMODE              : 1;
+    unsigned LINEMODE            : 1;
+} REG_G2D_INPUT;
+
+// G2D_MASK
+typedef struct _REG_G2D_MASK {
+    unsigned YMASK               : 12;
+    unsigned XMASK               : 12;
+} REG_G2D_MASK;
+
+// G2D_ROP
+typedef struct _REG_G2D_ROP {
+    unsigned ROP                 : 16;
+} REG_G2D_ROP;
+
+// G2D_SCISSORX
+typedef struct _REG_G2D_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned RIGHT               : 11;
+} REG_G2D_SCISSORX;
+
+// G2D_SCISSORY
+typedef struct _REG_G2D_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned BOTTOM              : 11;
+} REG_G2D_SCISSORY;
+
+// G2D_SXY
+typedef struct _REG_G2D_SXY {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY;
+
+// G2D_SXY2
+typedef struct _REG_G2D_SXY2 {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY2;
+
+// G2D_VGSPAN
+typedef struct _REG_G2D_VGSPAN {
+    int WIDTH               : 12;
+    unsigned PAD                 : 4;
+    unsigned COVERAGE            : 4;
+} REG_G2D_VGSPAN;
+
+// G2D_WIDTHHEIGHT
+typedef struct _REG_G2D_WIDTHHEIGHT {
+    int HEIGHT              : 12;
+    unsigned PAD                 : 4;
+    int WIDTH               : 12;
+} REG_G2D_WIDTHHEIGHT;
+
+// G2D_XY
+typedef struct _REG_G2D_XY {
+    int Y                   : 12;
+    unsigned PAD                 : 4;
+    int X                   : 12;
+} REG_G2D_XY;
+
+// GRADW_BORDERCOLOR
+typedef struct _REG_GRADW_BORDERCOLOR {
+    unsigned COLOR               : 32;
+} REG_GRADW_BORDERCOLOR;
+
+// GRADW_CONST0
+typedef struct _REG_GRADW_CONST0 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST0;
+
+// GRADW_CONST1
+typedef struct _REG_GRADW_CONST1 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST1;
+
+// GRADW_CONST2
+typedef struct _REG_GRADW_CONST2 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST2;
+
+// GRADW_CONST3
+typedef struct _REG_GRADW_CONST3 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST3;
+
+// GRADW_CONST4
+typedef struct _REG_GRADW_CONST4 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST4;
+
+// GRADW_CONST5
+typedef struct _REG_GRADW_CONST5 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST5;
+
+// GRADW_CONST6
+typedef struct _REG_GRADW_CONST6 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST6;
+
+// GRADW_CONST7
+typedef struct _REG_GRADW_CONST7 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST7;
+
+// GRADW_CONST8
+typedef struct _REG_GRADW_CONST8 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST8;
+
+// GRADW_CONST9
+typedef struct _REG_GRADW_CONST9 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST9;
+
+// GRADW_CONSTA
+typedef struct _REG_GRADW_CONSTA {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTA;
+
+// GRADW_CONSTB
+typedef struct _REG_GRADW_CONSTB {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTB;
+
+// GRADW_INST0
+typedef struct _REG_GRADW_INST0 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST0;
+
+// GRADW_INST1
+typedef struct _REG_GRADW_INST1 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST1;
+
+// GRADW_INST2
+typedef struct _REG_GRADW_INST2 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST2;
+
+// GRADW_INST3
+typedef struct _REG_GRADW_INST3 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST3;
+
+// GRADW_INST4
+typedef struct _REG_GRADW_INST4 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST4;
+
+// GRADW_INST5
+typedef struct _REG_GRADW_INST5 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST5;
+
+// GRADW_INST6
+typedef struct _REG_GRADW_INST6 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST6;
+
+// GRADW_INST7
+typedef struct _REG_GRADW_INST7 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST7;
+
+// GRADW_TEXBASE
+typedef struct _REG_GRADW_TEXBASE {
+    unsigned ADDR                : 32;
+} REG_GRADW_TEXBASE;
+
+// GRADW_TEXCFG
+typedef struct _REG_GRADW_TEXCFG {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned WRAPU               : 2;
+    unsigned WRAPV               : 2;
+    unsigned BILIN               : 1;
+    unsigned SRGB                : 1;
+    unsigned PREMULTIPLY         : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned TEX2D               : 1;
+    unsigned SWAPBITS            : 1;
+} REG_GRADW_TEXCFG;
+
+// GRADW_TEXSIZE
+typedef struct _REG_GRADW_TEXSIZE {
+    unsigned WIDTH               : 11;
+    unsigned HEIGHT              : 11;
+} REG_GRADW_TEXSIZE;
+
+// MH_ARBITER_CONFIG
+typedef struct _REG_MH_ARBITER_CONFIG {
+    unsigned SAME_PAGE_LIMIT     : 6;
+    unsigned SAME_PAGE_GRANULARITY : 1;
+    unsigned L1_ARB_ENABLE       : 1;
+    unsigned L1_ARB_HOLD_ENABLE  : 1;
+    unsigned L2_ARB_CONTROL      : 1;
+    unsigned PAGE_SIZE           : 3;
+    unsigned TC_REORDER_ENABLE   : 1;
+    unsigned TC_ARB_HOLD_ENABLE  : 1;
+    unsigned IN_FLIGHT_LIMIT_ENABLE : 1;
+    unsigned IN_FLIGHT_LIMIT     : 6;
+    unsigned CP_CLNT_ENABLE      : 1;
+    unsigned VGT_CLNT_ENABLE     : 1;
+    unsigned TC_CLNT_ENABLE      : 1;
+    unsigned RB_CLNT_ENABLE      : 1;
+    unsigned PA_CLNT_ENABLE      : 1;
+} REG_MH_ARBITER_CONFIG;
+
+// MH_AXI_ERROR
+typedef struct _REG_MH_AXI_ERROR {
+    unsigned AXI_READ_ID         : 3;
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ID        : 3;
+    unsigned AXI_WRITE_ERROR     : 1;
+} REG_MH_AXI_ERROR;
+
+// MH_AXI_HALT_CONTROL
+typedef struct _REG_MH_AXI_HALT_CONTROL {
+    unsigned AXI_HALT            : 1;
+} REG_MH_AXI_HALT_CONTROL;
+
+// MH_CLNT_AXI_ID_REUSE
+typedef struct _REG_MH_CLNT_AXI_ID_REUSE {
+    unsigned CPW_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned RBW_ID              : 3;
+    unsigned PAD2                : 1;
+    unsigned MMUR_ID             : 3;
+    unsigned PAD3                : 1;
+    unsigned PAW_ID              : 3;
+} REG_MH_CLNT_AXI_ID_REUSE;
+
+// MH_DEBUG_CTRL
+typedef struct _REG_MH_DEBUG_CTRL {
+    unsigned INDEX               : 6;
+} REG_MH_DEBUG_CTRL;
+
+// MH_DEBUG_DATA
+typedef struct _REG_MH_DEBUG_DATA {
+    unsigned DATA                : 32;
+} REG_MH_DEBUG_DATA;
+
+// MH_INTERRUPT_CLEAR
+typedef struct _REG_MH_INTERRUPT_CLEAR {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_CLEAR;
+
+// MH_INTERRUPT_MASK
+typedef struct _REG_MH_INTERRUPT_MASK {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_MASK;
+
+// MH_INTERRUPT_STATUS
+typedef struct _REG_MH_INTERRUPT_STATUS {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_STATUS;
+
+// MH_MMU_CONFIG
+typedef struct _REG_MH_MMU_CONFIG {
+    unsigned MMU_ENABLE          : 1;
+    unsigned SPLIT_MODE_ENABLE   : 1;
+    unsigned PAD                 : 2;
+    unsigned RB_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_R0_CLNT_BEHAVIOR : 2;
+    unsigned CP_R1_CLNT_BEHAVIOR : 2;
+    unsigned CP_R2_CLNT_BEHAVIOR : 2;
+    unsigned CP_R3_CLNT_BEHAVIOR : 2;
+    unsigned CP_R4_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R0_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R1_CLNT_BEHAVIOR : 2;
+    unsigned TC_R_CLNT_BEHAVIOR  : 2;
+    unsigned PA_W_CLNT_BEHAVIOR  : 2;
+} REG_MH_MMU_CONFIG;
+
+// MH_MMU_INVALIDATE
+typedef struct _REG_MH_MMU_INVALIDATE {
+    unsigned INVALIDATE_ALL      : 1;
+    unsigned INVALIDATE_TC       : 1;
+} REG_MH_MMU_INVALIDATE;
+
+// MH_MMU_MPU_BASE
+typedef struct _REG_MH_MMU_MPU_BASE {
+    unsigned ZERO                : 12;
+    unsigned MPU_BASE            : 20;
+} REG_MH_MMU_MPU_BASE;
+
+// MH_MMU_MPU_END
+typedef struct _REG_MH_MMU_MPU_END {
+    unsigned ZERO                : 12;
+    unsigned MPU_END             : 20;
+} REG_MH_MMU_MPU_END;
+
+// MH_MMU_PAGE_FAULT
+typedef struct _REG_MH_MMU_PAGE_FAULT {
+    unsigned PAGE_FAULT          : 1;
+    unsigned OP_TYPE             : 1;
+    unsigned CLNT_BEHAVIOR       : 2;
+    unsigned AXI_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned MPU_ADDRESS_OUT_OF_RANGE : 1;
+    unsigned ADDRESS_OUT_OF_RANGE : 1;
+    unsigned READ_PROTECTION_ERROR : 1;
+    unsigned WRITE_PROTECTION_ERROR : 1;
+    unsigned REQ_VA              : 20;
+} REG_MH_MMU_PAGE_FAULT;
+
+// MH_MMU_PT_BASE
+typedef struct _REG_MH_MMU_PT_BASE {
+    unsigned ZERO                : 12;
+    unsigned PT_BASE             : 20;
+} REG_MH_MMU_PT_BASE;
+
+// MH_MMU_TRAN_ERROR
+typedef struct _REG_MH_MMU_TRAN_ERROR {
+    unsigned ZERO                : 5;
+    unsigned TRAN_ERROR          : 27;
+} REG_MH_MMU_TRAN_ERROR;
+
+// MH_MMU_VA_RANGE
+typedef struct _REG_MH_MMU_VA_RANGE {
+    unsigned NUM_64KB_REGIONS    : 12;
+    unsigned VA_BASE             : 20;
+} REG_MH_MMU_VA_RANGE;
+
+// MH_PERFCOUNTER0_CONFIG
+typedef struct _REG_MH_PERFCOUNTER0_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER0_CONFIG;
+
+// MH_PERFCOUNTER0_HI
+typedef struct _REG_MH_PERFCOUNTER0_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER0_HI;
+
+// MH_PERFCOUNTER0_LOW
+typedef struct _REG_MH_PERFCOUNTER0_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER0_LOW;
+
+// MH_PERFCOUNTER0_SELECT
+typedef struct _REG_MH_PERFCOUNTER0_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER0_SELECT;
+
+// MH_PERFCOUNTER1_CONFIG
+typedef struct _REG_MH_PERFCOUNTER1_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER1_CONFIG;
+
+// MH_PERFCOUNTER1_HI
+typedef struct _REG_MH_PERFCOUNTER1_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER1_HI;
+
+// MH_PERFCOUNTER1_LOW
+typedef struct _REG_MH_PERFCOUNTER1_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER1_LOW;
+
+// MH_PERFCOUNTER1_SELECT
+typedef struct _REG_MH_PERFCOUNTER1_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER1_SELECT;
+
+// MMU_READ_ADDR
+typedef struct _REG_MMU_READ_ADDR {
+    unsigned ADDR                : 15;
+} REG_MMU_READ_ADDR;
+
+// MMU_READ_DATA
+typedef struct _REG_MMU_READ_DATA {
+    unsigned DATA                : 32;
+} REG_MMU_READ_DATA;
+
+// VGV1_CBASE1
+typedef struct _REG_VGV1_CBASE1 {
+    unsigned ADDR                : 32;
+} REG_VGV1_CBASE1;
+
+// VGV1_CFG1
+typedef struct _REG_VGV1_CFG1 {
+    unsigned WINDRULE            : 1;
+} REG_VGV1_CFG1;
+
+// VGV1_CFG2
+typedef struct _REG_VGV1_CFG2 {
+    unsigned AAMODE              : 2;
+} REG_VGV1_CFG2;
+
+// VGV1_DIRTYBASE
+typedef struct _REG_VGV1_DIRTYBASE {
+    unsigned ADDR                : 32;
+} REG_VGV1_DIRTYBASE;
+
+// VGV1_FILL
+typedef struct _REG_VGV1_FILL {
+    unsigned INHERIT             : 1;
+} REG_VGV1_FILL;
+
+// VGV1_SCISSORX
+typedef struct _REG_VGV1_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned PAD                 : 5;
+    unsigned RIGHT               : 11;
+} REG_VGV1_SCISSORX;
+
+// VGV1_SCISSORY
+typedef struct _REG_VGV1_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned PAD                 : 5;
+    unsigned BOTTOM              : 11;
+} REG_VGV1_SCISSORY;
+
+// VGV1_TILEOFS
+typedef struct _REG_VGV1_TILEOFS {
+    unsigned X                   : 12;
+    unsigned Y                   : 12;
+    unsigned LEFTMOST            : 1;
+} REG_VGV1_TILEOFS;
+
+// VGV1_UBASE2
+typedef struct _REG_VGV1_UBASE2 {
+    unsigned ADDR                : 32;
+} REG_VGV1_UBASE2;
+
+// VGV1_VTX0
+typedef struct _REG_VGV1_VTX0 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX0;
+
+// VGV1_VTX1
+typedef struct _REG_VGV1_VTX1 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX1;
+
+// VGV2_ACCURACY
+typedef struct _REG_VGV2_ACCURACY {
+    unsigned F                   : 24;
+} REG_VGV2_ACCURACY;
+
+// VGV2_ACTION
+typedef struct _REG_VGV2_ACTION {
+    unsigned ACTION              : 4;
+} REG_VGV2_ACTION;
+
+// VGV2_ARCCOS
+typedef struct _REG_VGV2_ARCCOS {
+    unsigned F                   : 24;
+} REG_VGV2_ARCCOS;
+
+// VGV2_ARCSIN
+typedef struct _REG_VGV2_ARCSIN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCSIN;
+
+// VGV2_ARCTAN
+typedef struct _REG_VGV2_ARCTAN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCTAN;
+
+// VGV2_BBOXMAXX
+typedef struct _REG_VGV2_BBOXMAXX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXX;
+
+// VGV2_BBOXMAXY
+typedef struct _REG_VGV2_BBOXMAXY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXY;
+
+// VGV2_BBOXMINX
+typedef struct _REG_VGV2_BBOXMINX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINX;
+
+// VGV2_BBOXMINY
+typedef struct _REG_VGV2_BBOXMINY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINY;
+
+// VGV2_BIAS
+typedef struct _REG_VGV2_BIAS {
+    unsigned F                   : 24;
+} REG_VGV2_BIAS;
+
+// VGV2_C1X
+typedef struct _REG_VGV2_C1X {
+    unsigned F                   : 24;
+} REG_VGV2_C1X;
+
+// VGV2_C1XREL
+typedef struct _REG_VGV2_C1XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1XREL;
+
+// VGV2_C1Y
+typedef struct _REG_VGV2_C1Y {
+    unsigned F                   : 24;
+} REG_VGV2_C1Y;
+
+// VGV2_C1YREL
+typedef struct _REG_VGV2_C1YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1YREL;
+
+// VGV2_C2X
+typedef struct _REG_VGV2_C2X {
+    unsigned F                   : 24;
+} REG_VGV2_C2X;
+
+// VGV2_C2XREL
+typedef struct _REG_VGV2_C2XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2XREL;
+
+// VGV2_C2Y
+typedef struct _REG_VGV2_C2Y {
+    unsigned F                   : 24;
+} REG_VGV2_C2Y;
+
+// VGV2_C2YREL
+typedef struct _REG_VGV2_C2YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2YREL;
+
+// VGV2_C3X
+typedef struct _REG_VGV2_C3X {
+    unsigned F                   : 24;
+} REG_VGV2_C3X;
+
+// VGV2_C3XREL
+typedef struct _REG_VGV2_C3XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3XREL;
+
+// VGV2_C3Y
+typedef struct _REG_VGV2_C3Y {
+    unsigned F                   : 24;
+} REG_VGV2_C3Y;
+
+// VGV2_C3YREL
+typedef struct _REG_VGV2_C3YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3YREL;
+
+// VGV2_C4X
+typedef struct _REG_VGV2_C4X {
+    unsigned F                   : 24;
+} REG_VGV2_C4X;
+
+// VGV2_C4XREL
+typedef struct _REG_VGV2_C4XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4XREL;
+
+// VGV2_C4Y
+typedef struct _REG_VGV2_C4Y {
+    unsigned F                   : 24;
+} REG_VGV2_C4Y;
+
+// VGV2_C4YREL
+typedef struct _REG_VGV2_C4YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4YREL;
+
+// VGV2_CLIP
+typedef struct _REG_VGV2_CLIP {
+    unsigned F                   : 24;
+} REG_VGV2_CLIP;
+
+// VGV2_FIRST
+typedef struct _REG_VGV2_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_FIRST;
+
+// VGV2_LAST
+typedef struct _REG_VGV2_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_LAST;
+
+// VGV2_MITER
+typedef struct _REG_VGV2_MITER {
+    unsigned F                   : 24;
+} REG_VGV2_MITER;
+
+// VGV2_MODE
+typedef struct _REG_VGV2_MODE {
+    unsigned MAXSPLIT            : 4;
+    unsigned CAP                 : 2;
+    unsigned JOIN                : 2;
+    unsigned STROKE              : 1;
+    unsigned STROKESPLIT         : 1;
+    unsigned FULLSPLIT           : 1;
+    unsigned NODOTS              : 1;
+    unsigned OPENFILL            : 1;
+    unsigned DROPLEFT            : 1;
+    unsigned DROPOTHER           : 1;
+    unsigned SYMMETRICJOINS      : 1;
+    unsigned SIMPLESTROKE        : 1;
+    unsigned SIMPLECLIP          : 1;
+    int EXPONENTADD         : 6;
+} REG_VGV2_MODE;
+
+// VGV2_RADIUS
+typedef struct _REG_VGV2_RADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_RADIUS;
+
+// VGV2_SCALE
+typedef struct _REG_VGV2_SCALE {
+    unsigned F                   : 24;
+} REG_VGV2_SCALE;
+
+// VGV2_THINRADIUS
+typedef struct _REG_VGV2_THINRADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_THINRADIUS;
+
+// VGV2_XFSTXX
+typedef struct _REG_VGV2_XFSTXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXX;
+
+// VGV2_XFSTXY
+typedef struct _REG_VGV2_XFSTXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXY;
+
+// VGV2_XFSTYX
+typedef struct _REG_VGV2_XFSTYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYX;
+
+// VGV2_XFSTYY
+typedef struct _REG_VGV2_XFSTYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYY;
+
+// VGV2_XFXA
+typedef struct _REG_VGV2_XFXA {
+    unsigned F                   : 24;
+} REG_VGV2_XFXA;
+
+// VGV2_XFXX
+typedef struct _REG_VGV2_XFXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFXX;
+
+// VGV2_XFXY
+typedef struct _REG_VGV2_XFXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFXY;
+
+// VGV2_XFYA
+typedef struct _REG_VGV2_XFYA {
+    unsigned F                   : 24;
+} REG_VGV2_XFYA;
+
+// VGV2_XFYX
+typedef struct _REG_VGV2_XFYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFYX;
+
+// VGV2_XFYY
+typedef struct _REG_VGV2_XFYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFYY;
+
+// VGV3_CONTROL
+typedef struct _REG_VGV3_CONTROL {
+    unsigned MARKADD             : 12;
+    unsigned DMIWAITCHMASK       : 4;
+    unsigned PAUSE               : 1;
+    unsigned ABORT               : 1;
+    unsigned WRITE               : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V0SYNC              : 1;
+    unsigned DMIWAITBUF          : 3;
+} REG_VGV3_CONTROL;
+
+// VGV3_FIRST
+typedef struct _REG_VGV3_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_FIRST;
+
+// VGV3_LAST
+typedef struct _REG_VGV3_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_LAST;
+
+// VGV3_MODE
+typedef struct _REG_VGV3_MODE {
+    unsigned FLIPENDIAN          : 1;
+    unsigned UNUSED              : 1;
+    unsigned WRITEFLUSH          : 1;
+    unsigned DMIPAUSETYPE        : 1;
+    unsigned DMIRESET            : 1;
+} REG_VGV3_MODE;
+
+// VGV3_NEXTADDR
+typedef struct _REG_VGV3_NEXTADDR {
+    unsigned CALLADDR            : 32;
+} REG_VGV3_NEXTADDR;
+
+// VGV3_NEXTCMD
+typedef struct _REG_VGV3_NEXTCMD {
+    unsigned COUNT               : 12;
+    unsigned NEXTCMD             : 3;
+    unsigned MARK                : 1;
+    unsigned CALLCOUNT           : 12;
+} REG_VGV3_NEXTCMD;
+
+// VGV3_VGBYPASS
+typedef struct _REG_VGV3_VGBYPASS {
+    unsigned BYPASS              : 1;
+} REG_VGV3_VGBYPASS;
+
+// VGV3_WRITE
+typedef struct _REG_VGV3_WRITE {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITE;
+
+// VGV3_WRITEADDR
+typedef struct _REG_VGV3_WRITEADDR {
+    unsigned ADDR                : 32;
+} REG_VGV3_WRITEADDR;
+
+// VGV3_WRITEDMI
+typedef struct _REG_VGV3_WRITEDMI {
+    unsigned CHANMASK            : 4;
+    unsigned BUFFER              : 3;
+} REG_VGV3_WRITEDMI;
+
+// VGV3_WRITEF32
+typedef struct _REG_VGV3_WRITEF32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITEF32;
+
+// VGV3_WRITEIFPAUSED
+typedef struct _REG_VGV3_WRITEIFPAUSED {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITEIFPAUSED;
+
+// VGV3_WRITERAW
+typedef struct _REG_VGV3_WRITERAW {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITERAW;
+
+// VGV3_WRITES16
+typedef struct _REG_VGV3_WRITES16 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES16;
+
+// VGV3_WRITES32
+typedef struct _REG_VGV3_WRITES32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES32;
+
+// VGV3_WRITES8
+typedef struct _REG_VGV3_WRITES8 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES8;
+
+// Register address, down shift, AND mask
+#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE
+#define FBC_BASE_BASE_FSHIFT 0
+#define FBC_BASE_BASE_FMASK 0xffffffff
+#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA
+#define FBC_DATA_DATA_FSHIFT 0
+#define FBC_DATA_DATA_FMASK 0xffffffff
+#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT
+#define FBC_HEIGHT_HEIGHT_FSHIFT 0
+#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff
+#define FBC_START_DUMMY_FADDR ADDR_FBC_START
+#define FBC_START_DUMMY_FSHIFT 0
+#define FBC_START_DUMMY_FMASK 0x1
+#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE
+#define FBC_STRIDE_STRIDE_FSHIFT 0
+#define FBC_STRIDE_STRIDE_FMASK 0x7ff
+#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH
+#define FBC_WIDTH_WIDTH_FSHIFT 0
+#define FBC_WIDTH_WIDTH_FMASK 0x7ff
+#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_BCACHE_FSHIFT 0
+#define VGC_CLOCKEN_BCACHE_FMASK 0x1
+#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1
+#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1
+#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2
+#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1
+#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_RESERVED_FSHIFT 3
+#define VGC_CLOCKEN_RESERVED_FMASK 0x7
+#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM
+#define VGC_COMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE
+#define VGC_FIFOFREE_FREE_FSHIFT 0
+#define VGC_FIFOFREE_FREE_FMASK 0x1
+#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_MH_FSHIFT 0
+#define VGC_IRQENABLE_MH_FMASK 0x1
+#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_G2D_FSHIFT 1
+#define VGC_IRQENABLE_G2D_FMASK 0x1
+#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FIFO_FSHIFT 2
+#define VGC_IRQENABLE_FIFO_FMASK 0x1
+#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FBC_FSHIFT 3
+#define VGC_IRQENABLE_FBC_FMASK 0x1
+#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_MH_FSHIFT 0
+#define VGC_IRQSTATUS_MH_FMASK 0x1
+#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_G2D_FSHIFT 1
+#define VGC_IRQSTATUS_G2D_FMASK 0x1
+#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FIFO_FSHIFT 2
+#define VGC_IRQSTATUS_FIFO_FMASK 0x1
+#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FBC_FSHIFT 3
+#define VGC_IRQSTATUS_FBC_FMASK 0x1
+#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0
+#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8
+#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24
+#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff
+#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM
+#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MINOR_REVISION_FSHIFT 0
+#define VGC_REVISION_MINOR_REVISION_FMASK 0xf
+#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4
+#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf
+#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS
+#define VGC_SYSSTATUS_RESET_FSHIFT 0
+#define VGC_SYSSTATUS_RESET_FMASK 0x1
+#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_ALPHA_FSHIFT 0
+#define G2D_ALPHABLEND_ALPHA_FMASK 0xff
+#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8
+#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1
+#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9
+#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1
+#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERT_FSHIFT 10
+#define G2D_ALPHABLEND_INVERT_FMASK 0x1
+#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11
+#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1
+#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MODULATE_FSHIFT 12
+#define G2D_ALPHABLEND_MODULATE_FMASK 0x1
+#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13
+#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1
+#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15
+#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1
+#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND
+#define G2D_BACKGROUND_COLOR_FSHIFT 0
+#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff
+#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0
+#define G2D_BASE0_ADDR_FSHIFT 0
+#define G2D_BASE0_ADDR_FMASK 0xffffffff
+#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1
+#define G2D_BASE1_ADDR_FSHIFT 0
+#define G2D_BASE1_ADDR_FMASK 0xffffffff
+#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2
+#define G2D_BASE2_ADDR_FSHIFT 0
+#define G2D_BASE2_ADDR_FMASK 0xffffffff
+#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3
+#define G2D_BASE3_ADDR_FSHIFT 0
+#define G2D_BASE3_ADDR_FMASK 0xffffffff
+#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_PASSES_FSHIFT 0
+#define G2D_BLENDERCFG_PASSES_FMASK 0x7
+#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3
+#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3
+#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ENABLE_FSHIFT 5
+#define G2D_BLENDERCFG_ENABLE_FMASK 0x1
+#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6
+#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_NOMASK_FSHIFT 8
+#define G2D_BLENDERCFG_NOMASK_FMASK 0x1
+#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_OPERATION_FSHIFT 0
+#define G2D_BLEND_A0_OPERATION_FMASK 0x3
+#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_A_FSHIFT 2
+#define G2D_BLEND_A0_DST_A_FMASK 0x3
+#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_B_FSHIFT 4
+#define G2D_BLEND_A0_DST_B_FMASK 0x3
+#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_C_FSHIFT 6
+#define G2D_BLEND_A0_DST_C_FMASK 0x3
+#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_A_FSHIFT 8
+#define G2D_BLEND_A0_AR_A_FMASK 0x1
+#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_B_FSHIFT 9
+#define G2D_BLEND_A0_AR_B_FMASK 0x1
+#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_C_FSHIFT 10
+#define G2D_BLEND_A0_AR_C_FMASK 0x1
+#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_D_FSHIFT 11
+#define G2D_BLEND_A0_AR_D_FMASK 0x1
+#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_A_FSHIFT 12
+#define G2D_BLEND_A0_INV_A_FMASK 0x1
+#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_B_FSHIFT 13
+#define G2D_BLEND_A0_INV_B_FMASK 0x1
+#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_C_FSHIFT 14
+#define G2D_BLEND_A0_INV_C_FMASK 0x1
+#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_D_FSHIFT 15
+#define G2D_BLEND_A0_INV_D_FMASK 0x1
+#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_A_FSHIFT 16
+#define G2D_BLEND_A0_SRC_A_FMASK 0x7
+#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_B_FSHIFT 19
+#define G2D_BLEND_A0_SRC_B_FMASK 0x7
+#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_C_FSHIFT 22
+#define G2D_BLEND_A0_SRC_C_FMASK 0x7
+#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_D_FSHIFT 25
+#define G2D_BLEND_A0_SRC_D_FMASK 0x7
+#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_A_FSHIFT 28
+#define G2D_BLEND_A0_CONST_A_FMASK 0x1
+#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_B_FSHIFT 29
+#define G2D_BLEND_A0_CONST_B_FMASK 0x1
+#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_C_FSHIFT 30
+#define G2D_BLEND_A0_CONST_C_FMASK 0x1
+#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_D_FSHIFT 31
+#define G2D_BLEND_A0_CONST_D_FMASK 0x1
+#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_OPERATION_FSHIFT 0
+#define G2D_BLEND_A1_OPERATION_FMASK 0x3
+#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_A_FSHIFT 2
+#define G2D_BLEND_A1_DST_A_FMASK 0x3
+#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_B_FSHIFT 4
+#define G2D_BLEND_A1_DST_B_FMASK 0x3
+#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_C_FSHIFT 6
+#define G2D_BLEND_A1_DST_C_FMASK 0x3
+#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_A_FSHIFT 8
+#define G2D_BLEND_A1_AR_A_FMASK 0x1
+#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_B_FSHIFT 9
+#define G2D_BLEND_A1_AR_B_FMASK 0x1
+#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_C_FSHIFT 10
+#define G2D_BLEND_A1_AR_C_FMASK 0x1
+#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_D_FSHIFT 11
+#define G2D_BLEND_A1_AR_D_FMASK 0x1
+#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_A_FSHIFT 12
+#define G2D_BLEND_A1_INV_A_FMASK 0x1
+#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_B_FSHIFT 13
+#define G2D_BLEND_A1_INV_B_FMASK 0x1
+#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_C_FSHIFT 14
+#define G2D_BLEND_A1_INV_C_FMASK 0x1
+#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_D_FSHIFT 15
+#define G2D_BLEND_A1_INV_D_FMASK 0x1
+#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_A_FSHIFT 16
+#define G2D_BLEND_A1_SRC_A_FMASK 0x7
+#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_B_FSHIFT 19
+#define G2D_BLEND_A1_SRC_B_FMASK 0x7
+#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_C_FSHIFT 22
+#define G2D_BLEND_A1_SRC_C_FMASK 0x7
+#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_D_FSHIFT 25
+#define G2D_BLEND_A1_SRC_D_FMASK 0x7
+#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_A_FSHIFT 28
+#define G2D_BLEND_A1_CONST_A_FMASK 0x1
+#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_B_FSHIFT 29
+#define G2D_BLEND_A1_CONST_B_FMASK 0x1
+#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_C_FSHIFT 30
+#define G2D_BLEND_A1_CONST_C_FMASK 0x1
+#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_D_FSHIFT 31
+#define G2D_BLEND_A1_CONST_D_FMASK 0x1
+#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_OPERATION_FSHIFT 0
+#define G2D_BLEND_A2_OPERATION_FMASK 0x3
+#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_A_FSHIFT 2
+#define G2D_BLEND_A2_DST_A_FMASK 0x3
+#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_B_FSHIFT 4
+#define G2D_BLEND_A2_DST_B_FMASK 0x3
+#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_C_FSHIFT 6
+#define G2D_BLEND_A2_DST_C_FMASK 0x3
+#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_A_FSHIFT 8
+#define G2D_BLEND_A2_AR_A_FMASK 0x1
+#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_B_FSHIFT 9
+#define G2D_BLEND_A2_AR_B_FMASK 0x1
+#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_C_FSHIFT 10
+#define G2D_BLEND_A2_AR_C_FMASK 0x1
+#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_D_FSHIFT 11
+#define G2D_BLEND_A2_AR_D_FMASK 0x1
+#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_A_FSHIFT 12
+#define G2D_BLEND_A2_INV_A_FMASK 0x1
+#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_B_FSHIFT 13
+#define G2D_BLEND_A2_INV_B_FMASK 0x1
+#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_C_FSHIFT 14
+#define G2D_BLEND_A2_INV_C_FMASK 0x1
+#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_D_FSHIFT 15
+#define G2D_BLEND_A2_INV_D_FMASK 0x1
+#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_A_FSHIFT 16
+#define G2D_BLEND_A2_SRC_A_FMASK 0x7
+#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_B_FSHIFT 19
+#define G2D_BLEND_A2_SRC_B_FMASK 0x7
+#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_C_FSHIFT 22
+#define G2D_BLEND_A2_SRC_C_FMASK 0x7
+#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_D_FSHIFT 25
+#define G2D_BLEND_A2_SRC_D_FMASK 0x7
+#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_A_FSHIFT 28
+#define G2D_BLEND_A2_CONST_A_FMASK 0x1
+#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_B_FSHIFT 29
+#define G2D_BLEND_A2_CONST_B_FMASK 0x1
+#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_C_FSHIFT 30
+#define G2D_BLEND_A2_CONST_C_FMASK 0x1
+#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_D_FSHIFT 31
+#define G2D_BLEND_A2_CONST_D_FMASK 0x1
+#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_OPERATION_FSHIFT 0
+#define G2D_BLEND_A3_OPERATION_FMASK 0x3
+#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_A_FSHIFT 2
+#define G2D_BLEND_A3_DST_A_FMASK 0x3
+#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_B_FSHIFT 4
+#define G2D_BLEND_A3_DST_B_FMASK 0x3
+#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_C_FSHIFT 6
+#define G2D_BLEND_A3_DST_C_FMASK 0x3
+#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_A_FSHIFT 8
+#define G2D_BLEND_A3_AR_A_FMASK 0x1
+#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_B_FSHIFT 9
+#define G2D_BLEND_A3_AR_B_FMASK 0x1
+#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_C_FSHIFT 10
+#define G2D_BLEND_A3_AR_C_FMASK 0x1
+#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_D_FSHIFT 11
+#define G2D_BLEND_A3_AR_D_FMASK 0x1
+#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_A_FSHIFT 12
+#define G2D_BLEND_A3_INV_A_FMASK 0x1
+#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_B_FSHIFT 13
+#define G2D_BLEND_A3_INV_B_FMASK 0x1
+#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_C_FSHIFT 14
+#define G2D_BLEND_A3_INV_C_FMASK 0x1
+#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_D_FSHIFT 15
+#define G2D_BLEND_A3_INV_D_FMASK 0x1
+#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_A_FSHIFT 16
+#define G2D_BLEND_A3_SRC_A_FMASK 0x7
+#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_B_FSHIFT 19
+#define G2D_BLEND_A3_SRC_B_FMASK 0x7
+#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_C_FSHIFT 22
+#define G2D_BLEND_A3_SRC_C_FMASK 0x7
+#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_D_FSHIFT 25
+#define G2D_BLEND_A3_SRC_D_FMASK 0x7
+#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_A_FSHIFT 28
+#define G2D_BLEND_A3_CONST_A_FMASK 0x1
+#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_B_FSHIFT 29
+#define G2D_BLEND_A3_CONST_B_FMASK 0x1
+#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_C_FSHIFT 30
+#define G2D_BLEND_A3_CONST_C_FMASK 0x1
+#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_D_FSHIFT 31
+#define G2D_BLEND_A3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_OPERATION_FSHIFT 0
+#define G2D_BLEND_C0_OPERATION_FMASK 0x3
+#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_A_FSHIFT 2
+#define G2D_BLEND_C0_DST_A_FMASK 0x3
+#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_B_FSHIFT 4
+#define G2D_BLEND_C0_DST_B_FMASK 0x3
+#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_C_FSHIFT 6
+#define G2D_BLEND_C0_DST_C_FMASK 0x3
+#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_A_FSHIFT 8
+#define G2D_BLEND_C0_AR_A_FMASK 0x1
+#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_B_FSHIFT 9
+#define G2D_BLEND_C0_AR_B_FMASK 0x1
+#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_C_FSHIFT 10
+#define G2D_BLEND_C0_AR_C_FMASK 0x1
+#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_D_FSHIFT 11
+#define G2D_BLEND_C0_AR_D_FMASK 0x1
+#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_A_FSHIFT 12
+#define G2D_BLEND_C0_INV_A_FMASK 0x1
+#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_B_FSHIFT 13
+#define G2D_BLEND_C0_INV_B_FMASK 0x1
+#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_C_FSHIFT 14
+#define G2D_BLEND_C0_INV_C_FMASK 0x1
+#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_D_FSHIFT 15
+#define G2D_BLEND_C0_INV_D_FMASK 0x1
+#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_A_FSHIFT 16
+#define G2D_BLEND_C0_SRC_A_FMASK 0x7
+#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_B_FSHIFT 19
+#define G2D_BLEND_C0_SRC_B_FMASK 0x7
+#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_C_FSHIFT 22
+#define G2D_BLEND_C0_SRC_C_FMASK 0x7
+#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_D_FSHIFT 25
+#define G2D_BLEND_C0_SRC_D_FMASK 0x7
+#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_A_FSHIFT 28
+#define G2D_BLEND_C0_CONST_A_FMASK 0x1
+#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_B_FSHIFT 29
+#define G2D_BLEND_C0_CONST_B_FMASK 0x1
+#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_C_FSHIFT 30
+#define G2D_BLEND_C0_CONST_C_FMASK 0x1
+#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_D_FSHIFT 31
+#define G2D_BLEND_C0_CONST_D_FMASK 0x1
+#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_OPERATION_FSHIFT 0
+#define G2D_BLEND_C1_OPERATION_FMASK 0x3
+#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_A_FSHIFT 2
+#define G2D_BLEND_C1_DST_A_FMASK 0x3
+#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_B_FSHIFT 4
+#define G2D_BLEND_C1_DST_B_FMASK 0x3
+#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_C_FSHIFT 6
+#define G2D_BLEND_C1_DST_C_FMASK 0x3
+#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_A_FSHIFT 8
+#define G2D_BLEND_C1_AR_A_FMASK 0x1
+#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_B_FSHIFT 9
+#define G2D_BLEND_C1_AR_B_FMASK 0x1
+#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_C_FSHIFT 10
+#define G2D_BLEND_C1_AR_C_FMASK 0x1
+#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_D_FSHIFT 11
+#define G2D_BLEND_C1_AR_D_FMASK 0x1
+#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_A_FSHIFT 12
+#define G2D_BLEND_C1_INV_A_FMASK 0x1
+#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_B_FSHIFT 13
+#define G2D_BLEND_C1_INV_B_FMASK 0x1
+#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_C_FSHIFT 14
+#define G2D_BLEND_C1_INV_C_FMASK 0x1
+#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_D_FSHIFT 15
+#define G2D_BLEND_C1_INV_D_FMASK 0x1
+#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_A_FSHIFT 16
+#define G2D_BLEND_C1_SRC_A_FMASK 0x7
+#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_B_FSHIFT 19
+#define G2D_BLEND_C1_SRC_B_FMASK 0x7
+#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_C_FSHIFT 22
+#define G2D_BLEND_C1_SRC_C_FMASK 0x7
+#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_D_FSHIFT 25
+#define G2D_BLEND_C1_SRC_D_FMASK 0x7
+#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_A_FSHIFT 28
+#define G2D_BLEND_C1_CONST_A_FMASK 0x1
+#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_B_FSHIFT 29
+#define G2D_BLEND_C1_CONST_B_FMASK 0x1
+#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_C_FSHIFT 30
+#define G2D_BLEND_C1_CONST_C_FMASK 0x1
+#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_D_FSHIFT 31
+#define G2D_BLEND_C1_CONST_D_FMASK 0x1
+#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_OPERATION_FSHIFT 0
+#define G2D_BLEND_C2_OPERATION_FMASK 0x3
+#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_A_FSHIFT 2
+#define G2D_BLEND_C2_DST_A_FMASK 0x3
+#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_B_FSHIFT 4
+#define G2D_BLEND_C2_DST_B_FMASK 0x3
+#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_C_FSHIFT 6
+#define G2D_BLEND_C2_DST_C_FMASK 0x3
+#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_A_FSHIFT 8
+#define G2D_BLEND_C2_AR_A_FMASK 0x1
+#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_B_FSHIFT 9
+#define G2D_BLEND_C2_AR_B_FMASK 0x1
+#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_C_FSHIFT 10
+#define G2D_BLEND_C2_AR_C_FMASK 0x1
+#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_D_FSHIFT 11
+#define G2D_BLEND_C2_AR_D_FMASK 0x1
+#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_A_FSHIFT 12
+#define G2D_BLEND_C2_INV_A_FMASK 0x1
+#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_B_FSHIFT 13
+#define G2D_BLEND_C2_INV_B_FMASK 0x1
+#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_C_FSHIFT 14
+#define G2D_BLEND_C2_INV_C_FMASK 0x1
+#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_D_FSHIFT 15
+#define G2D_BLEND_C2_INV_D_FMASK 0x1
+#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_A_FSHIFT 16
+#define G2D_BLEND_C2_SRC_A_FMASK 0x7
+#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_B_FSHIFT 19
+#define G2D_BLEND_C2_SRC_B_FMASK 0x7
+#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_C_FSHIFT 22
+#define G2D_BLEND_C2_SRC_C_FMASK 0x7
+#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_D_FSHIFT 25
+#define G2D_BLEND_C2_SRC_D_FMASK 0x7
+#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_A_FSHIFT 28
+#define G2D_BLEND_C2_CONST_A_FMASK 0x1
+#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_B_FSHIFT 29
+#define G2D_BLEND_C2_CONST_B_FMASK 0x1
+#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_C_FSHIFT 30
+#define G2D_BLEND_C2_CONST_C_FMASK 0x1
+#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_D_FSHIFT 31
+#define G2D_BLEND_C2_CONST_D_FMASK 0x1
+#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_OPERATION_FSHIFT 0
+#define G2D_BLEND_C3_OPERATION_FMASK 0x3
+#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_A_FSHIFT 2
+#define G2D_BLEND_C3_DST_A_FMASK 0x3
+#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_B_FSHIFT 4
+#define G2D_BLEND_C3_DST_B_FMASK 0x3
+#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_C_FSHIFT 6
+#define G2D_BLEND_C3_DST_C_FMASK 0x3
+#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_A_FSHIFT 8
+#define G2D_BLEND_C3_AR_A_FMASK 0x1
+#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_B_FSHIFT 9
+#define G2D_BLEND_C3_AR_B_FMASK 0x1
+#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_C_FSHIFT 10
+#define G2D_BLEND_C3_AR_C_FMASK 0x1
+#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_D_FSHIFT 11
+#define G2D_BLEND_C3_AR_D_FMASK 0x1
+#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_A_FSHIFT 12
+#define G2D_BLEND_C3_INV_A_FMASK 0x1
+#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_B_FSHIFT 13
+#define G2D_BLEND_C3_INV_B_FMASK 0x1
+#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_C_FSHIFT 14
+#define G2D_BLEND_C3_INV_C_FMASK 0x1
+#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_D_FSHIFT 15
+#define G2D_BLEND_C3_INV_D_FMASK 0x1
+#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_A_FSHIFT 16
+#define G2D_BLEND_C3_SRC_A_FMASK 0x7
+#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_B_FSHIFT 19
+#define G2D_BLEND_C3_SRC_B_FMASK 0x7
+#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_C_FSHIFT 22
+#define G2D_BLEND_C3_SRC_C_FMASK 0x7
+#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_D_FSHIFT 25
+#define G2D_BLEND_C3_SRC_D_FMASK 0x7
+#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_A_FSHIFT 28
+#define G2D_BLEND_C3_CONST_A_FMASK 0x1
+#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_B_FSHIFT 29
+#define G2D_BLEND_C3_CONST_B_FMASK 0x1
+#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_C_FSHIFT 30
+#define G2D_BLEND_C3_CONST_C_FMASK 0x1
+#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_D_FSHIFT 31
+#define G2D_BLEND_C3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_OPERATION_FSHIFT 0
+#define G2D_BLEND_C4_OPERATION_FMASK 0x3
+#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_A_FSHIFT 2
+#define G2D_BLEND_C4_DST_A_FMASK 0x3
+#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_B_FSHIFT 4
+#define G2D_BLEND_C4_DST_B_FMASK 0x3
+#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_C_FSHIFT 6
+#define G2D_BLEND_C4_DST_C_FMASK 0x3
+#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_A_FSHIFT 8
+#define G2D_BLEND_C4_AR_A_FMASK 0x1
+#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_B_FSHIFT 9
+#define G2D_BLEND_C4_AR_B_FMASK 0x1
+#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_C_FSHIFT 10
+#define G2D_BLEND_C4_AR_C_FMASK 0x1
+#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_D_FSHIFT 11
+#define G2D_BLEND_C4_AR_D_FMASK 0x1
+#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_A_FSHIFT 12
+#define G2D_BLEND_C4_INV_A_FMASK 0x1
+#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_B_FSHIFT 13
+#define G2D_BLEND_C4_INV_B_FMASK 0x1
+#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_C_FSHIFT 14
+#define G2D_BLEND_C4_INV_C_FMASK 0x1
+#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_D_FSHIFT 15
+#define G2D_BLEND_C4_INV_D_FMASK 0x1
+#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_A_FSHIFT 16
+#define G2D_BLEND_C4_SRC_A_FMASK 0x7
+#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_B_FSHIFT 19
+#define G2D_BLEND_C4_SRC_B_FMASK 0x7
+#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_C_FSHIFT 22
+#define G2D_BLEND_C4_SRC_C_FMASK 0x7
+#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_D_FSHIFT 25
+#define G2D_BLEND_C4_SRC_D_FMASK 0x7
+#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_A_FSHIFT 28
+#define G2D_BLEND_C4_CONST_A_FMASK 0x1
+#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_B_FSHIFT 29
+#define G2D_BLEND_C4_CONST_B_FMASK 0x1
+#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_C_FSHIFT 30
+#define G2D_BLEND_C4_CONST_C_FMASK 0x1
+#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_D_FSHIFT 31
+#define G2D_BLEND_C4_CONST_D_FMASK 0x1
+#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_OPERATION_FSHIFT 0
+#define G2D_BLEND_C5_OPERATION_FMASK 0x3
+#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_A_FSHIFT 2
+#define G2D_BLEND_C5_DST_A_FMASK 0x3
+#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_B_FSHIFT 4
+#define G2D_BLEND_C5_DST_B_FMASK 0x3
+#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_C_FSHIFT 6
+#define G2D_BLEND_C5_DST_C_FMASK 0x3
+#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_A_FSHIFT 8
+#define G2D_BLEND_C5_AR_A_FMASK 0x1
+#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_B_FSHIFT 9
+#define G2D_BLEND_C5_AR_B_FMASK 0x1
+#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_C_FSHIFT 10
+#define G2D_BLEND_C5_AR_C_FMASK 0x1
+#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_D_FSHIFT 11
+#define G2D_BLEND_C5_AR_D_FMASK 0x1
+#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_A_FSHIFT 12
+#define G2D_BLEND_C5_INV_A_FMASK 0x1
+#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_B_FSHIFT 13
+#define G2D_BLEND_C5_INV_B_FMASK 0x1
+#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_C_FSHIFT 14
+#define G2D_BLEND_C5_INV_C_FMASK 0x1
+#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_D_FSHIFT 15
+#define G2D_BLEND_C5_INV_D_FMASK 0x1
+#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_A_FSHIFT 16
+#define G2D_BLEND_C5_SRC_A_FMASK 0x7
+#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_B_FSHIFT 19
+#define G2D_BLEND_C5_SRC_B_FMASK 0x7
+#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_C_FSHIFT 22
+#define G2D_BLEND_C5_SRC_C_FMASK 0x7
+#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_D_FSHIFT 25
+#define G2D_BLEND_C5_SRC_D_FMASK 0x7
+#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_A_FSHIFT 28
+#define G2D_BLEND_C5_CONST_A_FMASK 0x1
+#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_B_FSHIFT 29
+#define G2D_BLEND_C5_CONST_B_FMASK 0x1
+#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_C_FSHIFT 30
+#define G2D_BLEND_C5_CONST_C_FMASK 0x1
+#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_D_FSHIFT 31
+#define G2D_BLEND_C5_CONST_D_FMASK 0x1
+#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_OPERATION_FSHIFT 0
+#define G2D_BLEND_C6_OPERATION_FMASK 0x3
+#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_A_FSHIFT 2
+#define G2D_BLEND_C6_DST_A_FMASK 0x3
+#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_B_FSHIFT 4
+#define G2D_BLEND_C6_DST_B_FMASK 0x3
+#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_C_FSHIFT 6
+#define G2D_BLEND_C6_DST_C_FMASK 0x3
+#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_A_FSHIFT 8
+#define G2D_BLEND_C6_AR_A_FMASK 0x1
+#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_B_FSHIFT 9
+#define G2D_BLEND_C6_AR_B_FMASK 0x1
+#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_C_FSHIFT 10
+#define G2D_BLEND_C6_AR_C_FMASK 0x1
+#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_D_FSHIFT 11
+#define G2D_BLEND_C6_AR_D_FMASK 0x1
+#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_A_FSHIFT 12
+#define G2D_BLEND_C6_INV_A_FMASK 0x1
+#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_B_FSHIFT 13
+#define G2D_BLEND_C6_INV_B_FMASK 0x1
+#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_C_FSHIFT 14
+#define G2D_BLEND_C6_INV_C_FMASK 0x1
+#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_D_FSHIFT 15
+#define G2D_BLEND_C6_INV_D_FMASK 0x1
+#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_A_FSHIFT 16
+#define G2D_BLEND_C6_SRC_A_FMASK 0x7
+#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_B_FSHIFT 19
+#define G2D_BLEND_C6_SRC_B_FMASK 0x7
+#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_C_FSHIFT 22
+#define G2D_BLEND_C6_SRC_C_FMASK 0x7
+#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_D_FSHIFT 25
+#define G2D_BLEND_C6_SRC_D_FMASK 0x7
+#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_A_FSHIFT 28
+#define G2D_BLEND_C6_CONST_A_FMASK 0x1
+#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_B_FSHIFT 29
+#define G2D_BLEND_C6_CONST_B_FMASK 0x1
+#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_C_FSHIFT 30
+#define G2D_BLEND_C6_CONST_C_FMASK 0x1
+#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_D_FSHIFT 31
+#define G2D_BLEND_C6_CONST_D_FMASK 0x1
+#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_OPERATION_FSHIFT 0
+#define G2D_BLEND_C7_OPERATION_FMASK 0x3
+#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_A_FSHIFT 2
+#define G2D_BLEND_C7_DST_A_FMASK 0x3
+#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_B_FSHIFT 4
+#define G2D_BLEND_C7_DST_B_FMASK 0x3
+#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_C_FSHIFT 6
+#define G2D_BLEND_C7_DST_C_FMASK 0x3
+#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_A_FSHIFT 8
+#define G2D_BLEND_C7_AR_A_FMASK 0x1
+#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_B_FSHIFT 9
+#define G2D_BLEND_C7_AR_B_FMASK 0x1
+#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_C_FSHIFT 10
+#define G2D_BLEND_C7_AR_C_FMASK 0x1
+#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_D_FSHIFT 11
+#define G2D_BLEND_C7_AR_D_FMASK 0x1
+#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_A_FSHIFT 12
+#define G2D_BLEND_C7_INV_A_FMASK 0x1
+#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_B_FSHIFT 13
+#define G2D_BLEND_C7_INV_B_FMASK 0x1
+#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_C_FSHIFT 14
+#define G2D_BLEND_C7_INV_C_FMASK 0x1
+#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_D_FSHIFT 15
+#define G2D_BLEND_C7_INV_D_FMASK 0x1
+#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_A_FSHIFT 16
+#define G2D_BLEND_C7_SRC_A_FMASK 0x7
+#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_B_FSHIFT 19
+#define G2D_BLEND_C7_SRC_B_FMASK 0x7
+#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_C_FSHIFT 22
+#define G2D_BLEND_C7_SRC_C_FMASK 0x7
+#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_D_FSHIFT 25
+#define G2D_BLEND_C7_SRC_D_FMASK 0x7
+#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_A_FSHIFT 28
+#define G2D_BLEND_C7_CONST_A_FMASK 0x1
+#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_B_FSHIFT 29
+#define G2D_BLEND_C7_CONST_B_FMASK 0x1
+#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_C_FSHIFT 30
+#define G2D_BLEND_C7_CONST_C_FMASK 0x1
+#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_D_FSHIFT 31
+#define G2D_BLEND_C7_CONST_D_FMASK 0x1
+#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDE_FSHIFT 0
+#define G2D_CFG0_STRIDE_FMASK 0xfff
+#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_FORMAT_FSHIFT 12
+#define G2D_CFG0_FORMAT_FMASK 0xf
+#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_TILED_FSHIFT 16
+#define G2D_CFG0_TILED_FMASK 0x1
+#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SRGB_FSHIFT 17
+#define G2D_CFG0_SRGB_FMASK 0x1
+#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPWORDS_FSHIFT 18
+#define G2D_CFG0_SWAPWORDS_FMASK 0x1
+#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBYTES_FSHIFT 19
+#define G2D_CFG0_SWAPBYTES_FMASK 0x1
+#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPALL_FSHIFT 20
+#define G2D_CFG0_SWAPALL_FMASK 0x1
+#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPRB_FSHIFT 21
+#define G2D_CFG0_SWAPRB_FMASK 0x1
+#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBITS_FSHIFT 22
+#define G2D_CFG0_SWAPBITS_FMASK 0x1
+#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDESIGN_FSHIFT 23
+#define G2D_CFG0_STRIDESIGN_FMASK 0x1
+#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDE_FSHIFT 0
+#define G2D_CFG1_STRIDE_FMASK 0xfff
+#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_FORMAT_FSHIFT 12
+#define G2D_CFG1_FORMAT_FMASK 0xf
+#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_TILED_FSHIFT 16
+#define G2D_CFG1_TILED_FMASK 0x1
+#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SRGB_FSHIFT 17
+#define G2D_CFG1_SRGB_FMASK 0x1
+#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPWORDS_FSHIFT 18
+#define G2D_CFG1_SWAPWORDS_FMASK 0x1
+#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBYTES_FSHIFT 19
+#define G2D_CFG1_SWAPBYTES_FMASK 0x1
+#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPALL_FSHIFT 20
+#define G2D_CFG1_SWAPALL_FMASK 0x1
+#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPRB_FSHIFT 21
+#define G2D_CFG1_SWAPRB_FMASK 0x1
+#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBITS_FSHIFT 22
+#define G2D_CFG1_SWAPBITS_FMASK 0x1
+#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDESIGN_FSHIFT 23
+#define G2D_CFG1_STRIDESIGN_FMASK 0x1
+#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDE_FSHIFT 0
+#define G2D_CFG2_STRIDE_FMASK 0xfff
+#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_FORMAT_FSHIFT 12
+#define G2D_CFG2_FORMAT_FMASK 0xf
+#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_TILED_FSHIFT 16
+#define G2D_CFG2_TILED_FMASK 0x1
+#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SRGB_FSHIFT 17
+#define G2D_CFG2_SRGB_FMASK 0x1
+#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPWORDS_FSHIFT 18
+#define G2D_CFG2_SWAPWORDS_FMASK 0x1
+#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBYTES_FSHIFT 19
+#define G2D_CFG2_SWAPBYTES_FMASK 0x1
+#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPALL_FSHIFT 20
+#define G2D_CFG2_SWAPALL_FMASK 0x1
+#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPRB_FSHIFT 21
+#define G2D_CFG2_SWAPRB_FMASK 0x1
+#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBITS_FSHIFT 22
+#define G2D_CFG2_SWAPBITS_FMASK 0x1
+#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDESIGN_FSHIFT 23
+#define G2D_CFG2_STRIDESIGN_FMASK 0x1
+#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDE_FSHIFT 0
+#define G2D_CFG3_STRIDE_FMASK 0xfff
+#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_FORMAT_FSHIFT 12
+#define G2D_CFG3_FORMAT_FMASK 0xf
+#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_TILED_FSHIFT 16
+#define G2D_CFG3_TILED_FMASK 0x1
+#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SRGB_FSHIFT 17
+#define G2D_CFG3_SRGB_FMASK 0x1
+#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPWORDS_FSHIFT 18
+#define G2D_CFG3_SWAPWORDS_FMASK 0x1
+#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBYTES_FSHIFT 19
+#define G2D_CFG3_SWAPBYTES_FMASK 0x1
+#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPALL_FSHIFT 20
+#define G2D_CFG3_SWAPALL_FMASK 0x1
+#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPRB_FSHIFT 21
+#define G2D_CFG3_SWAPRB_FMASK 0x1
+#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBITS_FSHIFT 22
+#define G2D_CFG3_SWAPBITS_FMASK 0x1
+#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDESIGN_FSHIFT 23
+#define G2D_CFG3_STRIDESIGN_FMASK 0x1
+#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR
+#define G2D_COLOR_ARGB_FSHIFT 0
+#define G2D_COLOR_ARGB_FMASK 0xffffffff
+#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DST_FSHIFT 0
+#define G2D_CONFIG_DST_FMASK 0x1
+#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC1_FSHIFT 1
+#define G2D_CONFIG_SRC1_FMASK 0x1
+#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC2_FSHIFT 2
+#define G2D_CONFIG_SRC2_FMASK 0x1
+#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC3_FSHIFT 3
+#define G2D_CONFIG_SRC3_FMASK 0x1
+#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRCCK_FSHIFT 4
+#define G2D_CONFIG_SRCCK_FMASK 0x1
+#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DSTCK_FSHIFT 5
+#define G2D_CONFIG_DSTCK_FMASK 0x1
+#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ROTATE_FSHIFT 6
+#define G2D_CONFIG_ROTATE_FMASK 0x3
+#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8
+#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1
+#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9
+#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1
+#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DITHER_FSHIFT 10
+#define G2D_CONFIG_DITHER_FMASK 0x1
+#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_WRITESRGB_FSHIFT 11
+#define G2D_CONFIG_WRITESRGB_FMASK 0x1
+#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ARGBMASK_FSHIFT 12
+#define G2D_CONFIG_ARGBMASK_FMASK 0xf
+#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ALPHATEX_FSHIFT 16
+#define G2D_CONFIG_ALPHATEX_FMASK 0x1
+#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_PALMLINES_FSHIFT 17
+#define G2D_CONFIG_PALMLINES_FMASK 0x1
+#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18
+#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1
+#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOPROTECT_FSHIFT 19
+#define G2D_CONFIG_NOPROTECT_FMASK 0x1
+#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0
+#define G2D_CONST0_ARGB_FSHIFT 0
+#define G2D_CONST0_ARGB_FMASK 0xffffffff
+#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1
+#define G2D_CONST1_ARGB_FSHIFT 0
+#define G2D_CONST1_ARGB_FMASK 0xffffffff
+#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2
+#define G2D_CONST2_ARGB_FSHIFT 0
+#define G2D_CONST2_ARGB_FMASK 0xffffffff
+#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3
+#define G2D_CONST3_ARGB_FSHIFT 0
+#define G2D_CONST3_ARGB_FMASK 0xffffffff
+#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4
+#define G2D_CONST4_ARGB_FSHIFT 0
+#define G2D_CONST4_ARGB_FMASK 0xffffffff
+#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5
+#define G2D_CONST5_ARGB_FSHIFT 0
+#define G2D_CONST5_ARGB_FMASK 0xffffffff
+#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6
+#define G2D_CONST6_ARGB_FSHIFT 0
+#define G2D_CONST6_ARGB_FMASK 0xffffffff
+#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7
+#define G2D_CONST7_ARGB_FSHIFT 0
+#define G2D_CONST7_ARGB_FMASK 0xffffffff
+#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND
+#define G2D_FOREGROUND_COLOR_FSHIFT 0
+#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff
+#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0
+#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7
+#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3
+#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7
+#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE_FSHIFT 6
+#define G2D_GRADIENT_ENABLE_FMASK 0x1
+#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE2_FSHIFT 7
+#define G2D_GRADIENT_ENABLE2_FMASK 0x1
+#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_SEL_FSHIFT 8
+#define G2D_GRADIENT_SEL_FMASK 0x1
+#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_IRQ_FSHIFT 0
+#define G2D_IDLE_IRQ_FMASK 0x1
+#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_BCFLUSH_FSHIFT 1
+#define G2D_IDLE_BCFLUSH_FMASK 0x1
+#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_V3_FSHIFT 2
+#define G2D_IDLE_V3_FMASK 0x1
+#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COLOR_FSHIFT 0
+#define G2D_INPUT_COLOR_FMASK 0x1
+#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD1_FSHIFT 1
+#define G2D_INPUT_SCOORD1_FMASK 0x1
+#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD2_FSHIFT 2
+#define G2D_INPUT_SCOORD2_FMASK 0x1
+#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COPYCOORD_FSHIFT 3
+#define G2D_INPUT_COPYCOORD_FMASK 0x1
+#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_VGMODE_FSHIFT 4
+#define G2D_INPUT_VGMODE_FMASK 0x1
+#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_LINEMODE_FSHIFT 5
+#define G2D_INPUT_LINEMODE_FMASK 0x1
+#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_YMASK_FSHIFT 0
+#define G2D_MASK_YMASK_FMASK 0xfff
+#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_XMASK_FSHIFT 12
+#define G2D_MASK_XMASK_FMASK 0xfff
+#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP
+#define G2D_ROP_ROP_FSHIFT 0
+#define G2D_ROP_ROP_FMASK 0xffff
+#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_LEFT_FSHIFT 0
+#define G2D_SCISSORX_LEFT_FMASK 0x7ff
+#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_RIGHT_FSHIFT 11
+#define G2D_SCISSORX_RIGHT_FMASK 0x7ff
+#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_TOP_FSHIFT 0
+#define G2D_SCISSORY_TOP_FMASK 0x7ff
+#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_BOTTOM_FSHIFT 11
+#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff
+#define G2D_SXY_Y_FADDR ADDR_G2D_SXY
+#define G2D_SXY_Y_FSHIFT 0
+#define G2D_SXY_Y_FMASK 0x7ff
+#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY
+#define G2D_SXY_PAD_FSHIFT 11
+#define G2D_SXY_PAD_FMASK 0x1f
+#define G2D_SXY_X_FADDR ADDR_G2D_SXY
+#define G2D_SXY_X_FSHIFT 16
+#define G2D_SXY_X_FMASK 0x7ff
+#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_Y_FSHIFT 0
+#define G2D_SXY2_Y_FMASK 0x7ff
+#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_PAD_FSHIFT 11
+#define G2D_SXY2_PAD_FMASK 0x1f
+#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_X_FSHIFT 16
+#define G2D_SXY2_X_FMASK 0x7ff
+#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_WIDTH_FSHIFT 0
+#define G2D_VGSPAN_WIDTH_FMASK 0xfff
+#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_PAD_FSHIFT 12
+#define G2D_VGSPAN_PAD_FMASK 0xf
+#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_COVERAGE_FSHIFT 16
+#define G2D_VGSPAN_COVERAGE_FMASK 0xf
+#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0
+#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff
+#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12
+#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf
+#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16
+#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff
+#define G2D_XY_Y_FADDR ADDR_G2D_XY
+#define G2D_XY_Y_FSHIFT 0
+#define G2D_XY_Y_FMASK 0xfff
+#define G2D_XY_PAD_FADDR ADDR_G2D_XY
+#define G2D_XY_PAD_FSHIFT 12
+#define G2D_XY_PAD_FMASK 0xf
+#define G2D_XY_X_FADDR ADDR_G2D_XY
+#define G2D_XY_X_FSHIFT 16
+#define G2D_XY_X_FMASK 0xfff
+#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR
+#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0
+#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff
+#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0
+#define GRADW_CONST0_VALUE_FSHIFT 0
+#define GRADW_CONST0_VALUE_FMASK 0xffff
+#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1
+#define GRADW_CONST1_VALUE_FSHIFT 0
+#define GRADW_CONST1_VALUE_FMASK 0xffff
+#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2
+#define GRADW_CONST2_VALUE_FSHIFT 0
+#define GRADW_CONST2_VALUE_FMASK 0xffff
+#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3
+#define GRADW_CONST3_VALUE_FSHIFT 0
+#define GRADW_CONST3_VALUE_FMASK 0xffff
+#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4
+#define GRADW_CONST4_VALUE_FSHIFT 0
+#define GRADW_CONST4_VALUE_FMASK 0xffff
+#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5
+#define GRADW_CONST5_VALUE_FSHIFT 0
+#define GRADW_CONST5_VALUE_FMASK 0xffff
+#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6
+#define GRADW_CONST6_VALUE_FSHIFT 0
+#define GRADW_CONST6_VALUE_FMASK 0xffff
+#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7
+#define GRADW_CONST7_VALUE_FSHIFT 0
+#define GRADW_CONST7_VALUE_FMASK 0xffff
+#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8
+#define GRADW_CONST8_VALUE_FSHIFT 0
+#define GRADW_CONST8_VALUE_FMASK 0xffff
+#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9
+#define GRADW_CONST9_VALUE_FSHIFT 0
+#define GRADW_CONST9_VALUE_FMASK 0xffff
+#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA
+#define GRADW_CONSTA_VALUE_FSHIFT 0
+#define GRADW_CONSTA_VALUE_FMASK 0xffff
+#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB
+#define GRADW_CONSTB_VALUE_FSHIFT 0
+#define GRADW_CONSTB_VALUE_FMASK 0xffff
+#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_E_FSHIFT 0
+#define GRADW_INST0_SRC_E_FMASK 0x1f
+#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_D_FSHIFT 5
+#define GRADW_INST0_SRC_D_FMASK 0x1f
+#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_C_FSHIFT 10
+#define GRADW_INST0_SRC_C_FMASK 0x1f
+#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_B_FSHIFT 15
+#define GRADW_INST0_SRC_B_FMASK 0x1f
+#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_A_FSHIFT 20
+#define GRADW_INST0_SRC_A_FMASK 0x1f
+#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_DST_FSHIFT 25
+#define GRADW_INST0_DST_FMASK 0xf
+#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_OPCODE_FSHIFT 29
+#define GRADW_INST0_OPCODE_FMASK 0x3
+#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_E_FSHIFT 0
+#define GRADW_INST1_SRC_E_FMASK 0x1f
+#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_D_FSHIFT 5
+#define GRADW_INST1_SRC_D_FMASK 0x1f
+#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_C_FSHIFT 10
+#define GRADW_INST1_SRC_C_FMASK 0x1f
+#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_B_FSHIFT 15
+#define GRADW_INST1_SRC_B_FMASK 0x1f
+#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_A_FSHIFT 20
+#define GRADW_INST1_SRC_A_FMASK 0x1f
+#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_DST_FSHIFT 25
+#define GRADW_INST1_DST_FMASK 0xf
+#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_OPCODE_FSHIFT 29
+#define GRADW_INST1_OPCODE_FMASK 0x3
+#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_E_FSHIFT 0
+#define GRADW_INST2_SRC_E_FMASK 0x1f
+#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_D_FSHIFT 5
+#define GRADW_INST2_SRC_D_FMASK 0x1f
+#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_C_FSHIFT 10
+#define GRADW_INST2_SRC_C_FMASK 0x1f
+#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_B_FSHIFT 15
+#define GRADW_INST2_SRC_B_FMASK 0x1f
+#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_A_FSHIFT 20
+#define GRADW_INST2_SRC_A_FMASK 0x1f
+#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_DST_FSHIFT 25
+#define GRADW_INST2_DST_FMASK 0xf
+#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_OPCODE_FSHIFT 29
+#define GRADW_INST2_OPCODE_FMASK 0x3
+#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_E_FSHIFT 0
+#define GRADW_INST3_SRC_E_FMASK 0x1f
+#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_D_FSHIFT 5
+#define GRADW_INST3_SRC_D_FMASK 0x1f
+#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_C_FSHIFT 10
+#define GRADW_INST3_SRC_C_FMASK 0x1f
+#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_B_FSHIFT 15
+#define GRADW_INST3_SRC_B_FMASK 0x1f
+#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_A_FSHIFT 20
+#define GRADW_INST3_SRC_A_FMASK 0x1f
+#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_DST_FSHIFT 25
+#define GRADW_INST3_DST_FMASK 0xf
+#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_OPCODE_FSHIFT 29
+#define GRADW_INST3_OPCODE_FMASK 0x3
+#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_E_FSHIFT 0
+#define GRADW_INST4_SRC_E_FMASK 0x1f
+#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_D_FSHIFT 5
+#define GRADW_INST4_SRC_D_FMASK 0x1f
+#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_C_FSHIFT 10
+#define GRADW_INST4_SRC_C_FMASK 0x1f
+#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_B_FSHIFT 15
+#define GRADW_INST4_SRC_B_FMASK 0x1f
+#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_A_FSHIFT 20
+#define GRADW_INST4_SRC_A_FMASK 0x1f
+#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_DST_FSHIFT 25
+#define GRADW_INST4_DST_FMASK 0xf
+#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_OPCODE_FSHIFT 29
+#define GRADW_INST4_OPCODE_FMASK 0x3
+#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_E_FSHIFT 0
+#define GRADW_INST5_SRC_E_FMASK 0x1f
+#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_D_FSHIFT 5
+#define GRADW_INST5_SRC_D_FMASK 0x1f
+#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_C_FSHIFT 10
+#define GRADW_INST5_SRC_C_FMASK 0x1f
+#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_B_FSHIFT 15
+#define GRADW_INST5_SRC_B_FMASK 0x1f
+#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_A_FSHIFT 20
+#define GRADW_INST5_SRC_A_FMASK 0x1f
+#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_DST_FSHIFT 25
+#define GRADW_INST5_DST_FMASK 0xf
+#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_OPCODE_FSHIFT 29
+#define GRADW_INST5_OPCODE_FMASK 0x3
+#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_E_FSHIFT 0
+#define GRADW_INST6_SRC_E_FMASK 0x1f
+#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_D_FSHIFT 5
+#define GRADW_INST6_SRC_D_FMASK 0x1f
+#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_C_FSHIFT 10
+#define GRADW_INST6_SRC_C_FMASK 0x1f
+#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_B_FSHIFT 15
+#define GRADW_INST6_SRC_B_FMASK 0x1f
+#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_A_FSHIFT 20
+#define GRADW_INST6_SRC_A_FMASK 0x1f
+#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_DST_FSHIFT 25
+#define GRADW_INST6_DST_FMASK 0xf
+#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_OPCODE_FSHIFT 29
+#define GRADW_INST6_OPCODE_FMASK 0x3
+#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_E_FSHIFT 0
+#define GRADW_INST7_SRC_E_FMASK 0x1f
+#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_D_FSHIFT 5
+#define GRADW_INST7_SRC_D_FMASK 0x1f
+#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_C_FSHIFT 10
+#define GRADW_INST7_SRC_C_FMASK 0x1f
+#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_B_FSHIFT 15
+#define GRADW_INST7_SRC_B_FMASK 0x1f
+#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_A_FSHIFT 20
+#define GRADW_INST7_SRC_A_FMASK 0x1f
+#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_DST_FSHIFT 25
+#define GRADW_INST7_DST_FMASK 0xf
+#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_OPCODE_FSHIFT 29
+#define GRADW_INST7_OPCODE_FMASK 0x3
+#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE
+#define GRADW_TEXBASE_ADDR_FSHIFT 0
+#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff
+#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_STRIDE_FSHIFT 0
+#define GRADW_TEXCFG_STRIDE_FMASK 0xfff
+#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_FORMAT_FSHIFT 12
+#define GRADW_TEXCFG_FORMAT_FMASK 0xf
+#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TILED_FSHIFT 16
+#define GRADW_TEXCFG_TILED_FMASK 0x1
+#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPU_FSHIFT 17
+#define GRADW_TEXCFG_WRAPU_FMASK 0x3
+#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPV_FSHIFT 19
+#define GRADW_TEXCFG_WRAPV_FMASK 0x3
+#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_BILIN_FSHIFT 21
+#define GRADW_TEXCFG_BILIN_FMASK 0x1
+#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SRGB_FSHIFT 22
+#define GRADW_TEXCFG_SRGB_FMASK 0x1
+#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23
+#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1
+#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24
+#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25
+#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1
+#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPALL_FSHIFT 26
+#define GRADW_TEXCFG_SWAPALL_FMASK 0x1
+#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPRB_FSHIFT 27
+#define GRADW_TEXCFG_SWAPRB_FMASK 0x1
+#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TEX2D_FSHIFT 28
+#define GRADW_TEXCFG_TEX2D_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29
+#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1
+#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_WIDTH_FSHIFT 0
+#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff
+#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11
+#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1
+#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3
+#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1
+#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7
+#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL_INDEX_FSHIFT 0
+#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f
+#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA
+#define MH_DEBUG_DATA_DATA_FSHIFT 0
+#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0
+#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PAD_FSHIFT 2
+#define MH_MMU_CONFIG_PAD_FMASK 0x3
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1
+#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0
+#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12
+#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff
+#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_ZERO_FSHIFT 0
+#define MH_MMU_MPU_END_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_MPU_END_FSHIFT 12
+#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4
+#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7
+#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7
+#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12
+#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff
+#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_ZERO_FSHIFT 0
+#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12
+#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff
+#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0
+#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff
+#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12
+#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff
+#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR
+#define MMU_READ_ADDR_ADDR_FSHIFT 0
+#define MMU_READ_ADDR_ADDR_FMASK 0x7fff
+#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA
+#define MMU_READ_DATA_DATA_FSHIFT 0
+#define MMU_READ_DATA_DATA_FMASK 0xffffffff
+#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1
+#define VGV1_CBASE1_ADDR_FSHIFT 0
+#define VGV1_CBASE1_ADDR_FMASK 0xffffffff
+#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1
+#define VGV1_CFG1_WINDRULE_FSHIFT 0
+#define VGV1_CFG1_WINDRULE_FMASK 0x1
+#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2
+#define VGV1_CFG2_AAMODE_FSHIFT 0
+#define VGV1_CFG2_AAMODE_FMASK 0x3
+#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE
+#define VGV1_DIRTYBASE_ADDR_FSHIFT 0
+#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff
+#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL
+#define VGV1_FILL_INHERIT_FSHIFT 0
+#define VGV1_FILL_INHERIT_FMASK 0x1
+#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_LEFT_FSHIFT 0
+#define VGV1_SCISSORX_LEFT_FMASK 0x7ff
+#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_PAD_FSHIFT 11
+#define VGV1_SCISSORX_PAD_FMASK 0x1f
+#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_RIGHT_FSHIFT 16
+#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff
+#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_TOP_FSHIFT 0
+#define VGV1_SCISSORY_TOP_FMASK 0x7ff
+#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_PAD_FSHIFT 11
+#define VGV1_SCISSORY_PAD_FMASK 0x1f
+#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_BOTTOM_FSHIFT 16
+#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff
+#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_X_FSHIFT 0
+#define VGV1_TILEOFS_X_FMASK 0xfff
+#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_Y_FSHIFT 12
+#define VGV1_TILEOFS_Y_FMASK 0xfff
+#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24
+#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1
+#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2
+#define VGV1_UBASE2_ADDR_FSHIFT 0
+#define VGV1_UBASE2_ADDR_FMASK 0xffffffff
+#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_X_FSHIFT 0
+#define VGV1_VTX0_X_FMASK 0xffff
+#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_Y_FSHIFT 16
+#define VGV1_VTX0_Y_FMASK 0xffff
+#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_X_FSHIFT 0
+#define VGV1_VTX1_X_FMASK 0xffff
+#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_Y_FSHIFT 16
+#define VGV1_VTX1_Y_FMASK 0xffff
+#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY
+#define VGV2_ACCURACY_F_FSHIFT 0
+#define VGV2_ACCURACY_F_FMASK 0xffffff
+#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION
+#define VGV2_ACTION_ACTION_FSHIFT 0
+#define VGV2_ACTION_ACTION_FMASK 0xf
+#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS
+#define VGV2_ARCCOS_F_FSHIFT 0
+#define VGV2_ARCCOS_F_FMASK 0xffffff
+#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN
+#define VGV2_ARCSIN_F_FSHIFT 0
+#define VGV2_ARCSIN_F_FMASK 0xffffff
+#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN
+#define VGV2_ARCTAN_F_FSHIFT 0
+#define VGV2_ARCTAN_F_FMASK 0xffffff
+#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX
+#define VGV2_BBOXMAXX_F_FSHIFT 0
+#define VGV2_BBOXMAXX_F_FMASK 0xffffff
+#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY
+#define VGV2_BBOXMAXY_F_FSHIFT 0
+#define VGV2_BBOXMAXY_F_FMASK 0xffffff
+#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX
+#define VGV2_BBOXMINX_F_FSHIFT 0
+#define VGV2_BBOXMINX_F_FMASK 0xffffff
+#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY
+#define VGV2_BBOXMINY_F_FSHIFT 0
+#define VGV2_BBOXMINY_F_FMASK 0xffffff
+#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS
+#define VGV2_BIAS_F_FSHIFT 0
+#define VGV2_BIAS_F_FMASK 0xffffff
+#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X
+#define VGV2_C1X_F_FSHIFT 0
+#define VGV2_C1X_F_FMASK 0xffffff
+#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL
+#define VGV2_C1XREL_F_FSHIFT 0
+#define VGV2_C1XREL_F_FMASK 0xffffff
+#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y
+#define VGV2_C1Y_F_FSHIFT 0
+#define VGV2_C1Y_F_FMASK 0xffffff
+#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL
+#define VGV2_C1YREL_F_FSHIFT 0
+#define VGV2_C1YREL_F_FMASK 0xffffff
+#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X
+#define VGV2_C2X_F_FSHIFT 0
+#define VGV2_C2X_F_FMASK 0xffffff
+#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL
+#define VGV2_C2XREL_F_FSHIFT 0
+#define VGV2_C2XREL_F_FMASK 0xffffff
+#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y
+#define VGV2_C2Y_F_FSHIFT 0
+#define VGV2_C2Y_F_FMASK 0xffffff
+#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL
+#define VGV2_C2YREL_F_FSHIFT 0
+#define VGV2_C2YREL_F_FMASK 0xffffff
+#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X
+#define VGV2_C3X_F_FSHIFT 0
+#define VGV2_C3X_F_FMASK 0xffffff
+#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL
+#define VGV2_C3XREL_F_FSHIFT 0
+#define VGV2_C3XREL_F_FMASK 0xffffff
+#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y
+#define VGV2_C3Y_F_FSHIFT 0
+#define VGV2_C3Y_F_FMASK 0xffffff
+#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL
+#define VGV2_C3YREL_F_FSHIFT 0
+#define VGV2_C3YREL_F_FMASK 0xffffff
+#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X
+#define VGV2_C4X_F_FSHIFT 0
+#define VGV2_C4X_F_FMASK 0xffffff
+#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL
+#define VGV2_C4XREL_F_FSHIFT 0
+#define VGV2_C4XREL_F_FMASK 0xffffff
+#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y
+#define VGV2_C4Y_F_FSHIFT 0
+#define VGV2_C4Y_F_FMASK 0xffffff
+#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL
+#define VGV2_C4YREL_F_FSHIFT 0
+#define VGV2_C4YREL_F_FMASK 0xffffff
+#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP
+#define VGV2_CLIP_F_FSHIFT 0
+#define VGV2_CLIP_F_FMASK 0xffffff
+#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST
+#define VGV2_FIRST_DUMMY_FSHIFT 0
+#define VGV2_FIRST_DUMMY_FMASK 0x1
+#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST
+#define VGV2_LAST_DUMMY_FSHIFT 0
+#define VGV2_LAST_DUMMY_FMASK 0x1
+#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER
+#define VGV2_MITER_F_FSHIFT 0
+#define VGV2_MITER_F_FMASK 0xffffff
+#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_MAXSPLIT_FSHIFT 0
+#define VGV2_MODE_MAXSPLIT_FMASK 0xf
+#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_CAP_FSHIFT 4
+#define VGV2_MODE_CAP_FMASK 0x3
+#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_JOIN_FSHIFT 6
+#define VGV2_MODE_JOIN_FMASK 0x3
+#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKE_FSHIFT 8
+#define VGV2_MODE_STROKE_FMASK 0x1
+#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKESPLIT_FSHIFT 9
+#define VGV2_MODE_STROKESPLIT_FMASK 0x1
+#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_FULLSPLIT_FSHIFT 10
+#define VGV2_MODE_FULLSPLIT_FMASK 0x1
+#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_NODOTS_FSHIFT 11
+#define VGV2_MODE_NODOTS_FMASK 0x1
+#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_OPENFILL_FSHIFT 12
+#define VGV2_MODE_OPENFILL_FMASK 0x1
+#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPLEFT_FSHIFT 13
+#define VGV2_MODE_DROPLEFT_FMASK 0x1
+#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPOTHER_FSHIFT 14
+#define VGV2_MODE_DROPOTHER_FMASK 0x1
+#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15
+#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1
+#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16
+#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1
+#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLECLIP_FSHIFT 17
+#define VGV2_MODE_SIMPLECLIP_FMASK 0x1
+#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_EXPONENTADD_FSHIFT 18
+#define VGV2_MODE_EXPONENTADD_FMASK 0x3f
+#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS
+#define VGV2_RADIUS_F_FSHIFT 0
+#define VGV2_RADIUS_F_FMASK 0xffffff
+#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE
+#define VGV2_SCALE_F_FSHIFT 0
+#define VGV2_SCALE_F_FMASK 0xffffff
+#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS
+#define VGV2_THINRADIUS_F_FSHIFT 0
+#define VGV2_THINRADIUS_F_FMASK 0xffffff
+#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX
+#define VGV2_XFSTXX_F_FSHIFT 0
+#define VGV2_XFSTXX_F_FMASK 0xffffff
+#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY
+#define VGV2_XFSTXY_F_FSHIFT 0
+#define VGV2_XFSTXY_F_FMASK 0xffffff
+#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX
+#define VGV2_XFSTYX_F_FSHIFT 0
+#define VGV2_XFSTYX_F_FMASK 0xffffff
+#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY
+#define VGV2_XFSTYY_F_FSHIFT 0
+#define VGV2_XFSTYY_F_FMASK 0xffffff
+#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA
+#define VGV2_XFXA_F_FSHIFT 0
+#define VGV2_XFXA_F_FMASK 0xffffff
+#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX
+#define VGV2_XFXX_F_FSHIFT 0
+#define VGV2_XFXX_F_FMASK 0xffffff
+#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY
+#define VGV2_XFXY_F_FSHIFT 0
+#define VGV2_XFXY_F_FMASK 0xffffff
+#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA
+#define VGV2_XFYA_F_FSHIFT 0
+#define VGV2_XFYA_F_FMASK 0xffffff
+#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX
+#define VGV2_XFYX_F_FSHIFT 0
+#define VGV2_XFYX_F_FMASK 0xffffff
+#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY
+#define VGV2_XFYY_F_FSHIFT 0
+#define VGV2_XFYY_F_FMASK 0xffffff
+#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_MARKADD_FSHIFT 0
+#define VGV3_CONTROL_MARKADD_FMASK 0xfff
+#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12
+#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf
+#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_PAUSE_FSHIFT 16
+#define VGV3_CONTROL_PAUSE_FMASK 0x1
+#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_ABORT_FSHIFT 17
+#define VGV3_CONTROL_ABORT_FMASK 0x1
+#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_WRITE_FSHIFT 18
+#define VGV3_CONTROL_WRITE_FMASK 0x1
+#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_BCFLUSH_FSHIFT 19
+#define VGV3_CONTROL_BCFLUSH_FMASK 0x1
+#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_V0SYNC_FSHIFT 20
+#define VGV3_CONTROL_V0SYNC_FMASK 0x1
+#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21
+#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7
+#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST
+#define VGV3_FIRST_DUMMY_FSHIFT 0
+#define VGV3_FIRST_DUMMY_FMASK 0x1
+#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST
+#define VGV3_LAST_DUMMY_FSHIFT 0
+#define VGV3_LAST_DUMMY_FMASK 0x1
+#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_FLIPENDIAN_FSHIFT 0
+#define VGV3_MODE_FLIPENDIAN_FMASK 0x1
+#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_UNUSED_FSHIFT 1
+#define VGV3_MODE_UNUSED_FMASK 0x1
+#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_WRITEFLUSH_FSHIFT 2
+#define VGV3_MODE_WRITEFLUSH_FMASK 0x1
+#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3
+#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1
+#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIRESET_FSHIFT 4
+#define VGV3_MODE_DMIRESET_FMASK 0x1
+#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR
+#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0
+#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff
+#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_COUNT_FSHIFT 0
+#define VGV3_NEXTCMD_COUNT_FMASK 0xfff
+#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12
+#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7
+#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_MARK_FSHIFT 15
+#define VGV3_NEXTCMD_MARK_FMASK 0x1
+#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16
+#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff
+#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS
+#define VGV3_VGBYPASS_BYPASS_FSHIFT 0
+#define VGV3_VGBYPASS_BYPASS_FMASK 0x1
+#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE
+#define VGV3_WRITE_VALUE_FSHIFT 0
+#define VGV3_WRITE_VALUE_FMASK 0xffffffff
+#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR
+#define VGV3_WRITEADDR_ADDR_FSHIFT 0
+#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff
+#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0
+#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf
+#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_BUFFER_FSHIFT 4
+#define VGV3_WRITEDMI_BUFFER_FMASK 0x7
+#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ADDR_FSHIFT 0
+#define VGV3_WRITEF32_ADDR_FMASK 0xff
+#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_COUNT_FSHIFT 8
+#define VGV3_WRITEF32_COUNT_FMASK 0xff
+#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_LOOP_FSHIFT 16
+#define VGV3_WRITEF32_LOOP_FMASK 0xf
+#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ACTION_FSHIFT 20
+#define VGV3_WRITEF32_ACTION_FMASK 0xf
+#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_FORMAT_FSHIFT 24
+#define VGV3_WRITEF32_FORMAT_FMASK 0x7
+#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED
+#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0
+#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff
+#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ADDR_FSHIFT 0
+#define VGV3_WRITERAW_ADDR_FMASK 0xff
+#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_COUNT_FSHIFT 8
+#define VGV3_WRITERAW_COUNT_FMASK 0xff
+#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_LOOP_FSHIFT 16
+#define VGV3_WRITERAW_LOOP_FMASK 0xf
+#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ACTION_FSHIFT 20
+#define VGV3_WRITERAW_ACTION_FMASK 0xf
+#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_FORMAT_FSHIFT 24
+#define VGV3_WRITERAW_FORMAT_FMASK 0x7
+#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ADDR_FSHIFT 0
+#define VGV3_WRITES16_ADDR_FMASK 0xff
+#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_COUNT_FSHIFT 8
+#define VGV3_WRITES16_COUNT_FMASK 0xff
+#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_LOOP_FSHIFT 16
+#define VGV3_WRITES16_LOOP_FMASK 0xf
+#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ACTION_FSHIFT 20
+#define VGV3_WRITES16_ACTION_FMASK 0xf
+#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_FORMAT_FSHIFT 24
+#define VGV3_WRITES16_FORMAT_FMASK 0x7
+#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ADDR_FSHIFT 0
+#define VGV3_WRITES32_ADDR_FMASK 0xff
+#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_COUNT_FSHIFT 8
+#define VGV3_WRITES32_COUNT_FMASK 0xff
+#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_LOOP_FSHIFT 16
+#define VGV3_WRITES32_LOOP_FMASK 0xf
+#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ACTION_FSHIFT 20
+#define VGV3_WRITES32_ACTION_FMASK 0xf
+#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_FORMAT_FSHIFT 24
+#define VGV3_WRITES32_FORMAT_FMASK 0x7
+#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ADDR_FSHIFT 0
+#define VGV3_WRITES8_ADDR_FMASK 0xff
+#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_COUNT_FSHIFT 8
+#define VGV3_WRITES8_COUNT_FMASK 0xff
+#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_LOOP_FSHIFT 16
+#define VGV3_WRITES8_LOOP_FMASK 0xf
+#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ACTION_FSHIFT 20
+#define VGV3_WRITES8_ACTION_FMASK 0xf
+#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_FORMAT_FSHIFT 24
+#define VGV3_WRITES8_FORMAT_FMASK 0x7
+typedef struct {
+    unsigned RS[256];
+    unsigned GRADW[2][40];
+} regstate_t;
+
+#define GRADW_WINDOW_START 0xc0
+#define GRADW_WINDOW_LEN 0x28
+#define GRADW_WINDOW_NUM 0x2
+
+static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        return (RS->GRADW[win][addr-0xc0] >>
+                shift) & mask;
+    }
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | 
+                   ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) {
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data)
+#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETREG(reg, data) __setreg__(&RS, reg, data)
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h
new file mode 100644
index 000000000000..05cae6c46403
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _YAMATO_H
+#define _YAMATO_H
+
+#ifndef qLittleEndian
+#define qLittleEndian
+#endif
+
+#if defined(_YDX14)
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 14 header files\r\n")
+#endif
+#include "yamato/14/yamato_enum.h"
+#include "yamato/14/yamato_ipt.h"
+#include "yamato/14/yamato_mask.h"
+#include "yamato/14/yamato_offset.h"
+#include "yamato/14/yamato_registers.h"
+#include "yamato/14/yamato_shift.h"
+#include "yamato/14/yamato_struct.h"
+#include "yamato/14/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/14/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/14/yamato_genreg.h"
+#else
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 22 header files\r\n")
+#endif
+#include "yamato/22/yamato_enum.h"
+#include "yamato/22/yamato_ipt.h"
+#include "yamato/22/yamato_mask.h"
+#include "yamato/22/yamato_offset.h"
+#include "yamato/22/yamato_registers.h"
+#include "yamato/22/yamato_shift.h"
+#include "yamato/22/yamato_struct.h"
+#include "yamato/22/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/22/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/22/yamato_genreg.h"
+#endif
+
+#endif // _YAMATO_H
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
new file mode 100644
index 000000000000..144e9151fd8a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
@@ -0,0 +1,1895 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
new file mode 100644
index 000000000000..87a454a1e38a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
new file mode 100644
index 000000000000..f7efe31bc8a8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
@@ -0,0 +1,3404 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(CULL_FRONT, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(BRES_CNTL, int)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+    GENERATE_FIELD(CURRENT_PTR, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(NUM_INDICES, uint)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(FACENESS_RESET, int)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(DST_STATE_ID, int)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(LOD_CNTL, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_BUSY, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(TT_MODE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(tca_rts, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(FW_tpc_rts, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(tp0_full, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(capture_tca_rts, int)
+    GENERATE_FIELD(captue_state_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(sector_format512, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(access512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(valid_left_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(left_done, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(setquads_to_send, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(quad_sel_left, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(arb_RTR, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc0_arb_rts, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(ipbuf_busy, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_pstate, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(dcmp_mux_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(pstate, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(n0_stall, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_incoming_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(fifo_busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(TIMEBASE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_VSR_LD, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(ARB_TR_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(BUSY_Q, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(BUSY, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(LOOP_ID, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_2, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(SRC_SEL, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_X, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(STRIDE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(TYPE, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ON, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_ON_PIX, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(PAw_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(CPw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ID, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(VA_BASE, int)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(REQ_VA, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(PAGE_FAULT, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(PATCH_REVISION, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(DESIGNER0, int)
+    GENERATE_FIELD(PARTNUMBER1, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(REVISION, int)
+    GENERATE_FIELD(DESIGNER1, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(CONTINUATION, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_COUNT, int)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_RTR, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ERROR, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ADDRESS, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(MH_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(RB_BUFSZ, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_ST_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(ROQ_END, int)
+    GENERATE_FIELD(MEQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB2_COUNTER, int)
+    GENERATE_FIELD(IB1_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_WPTR, int)
+    GENERATE_FIELD(MEQ_RPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_0_STAT, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+    GENERATE_FIELD(CMD_INDEX, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_STATMUX, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(RB_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(SW_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(RB_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(SW_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(RB_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(SW_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+    GENERATE_FIELD(PERFMON_STATE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(END_RCVD_15, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_0, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(END_RCVD_31, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_16, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(END_RCVD_47, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_32, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(END_RCVD_63, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_48, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(CP_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_BASE, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(RESERVED1, bool)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILREF, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(RESERVED3, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_RED, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_BLUE, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_RED, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(RESERVED5, bool)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_Y, uint)
+    GENERATE_FIELD(OFFSET_X, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(RESERVED6, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
new file mode 100644
index 000000000000..f31b2a74d1fa
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
@@ -0,0 +1,5920 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+/*
+*   yamato_mask.h
+*
+*   Register Spec Release:  Chip Spec 1.0
+*
+*
+*    (c) 2000 ATI Technologies Inc.  (unpublished)
+*
+*    All rights reserved.  This notice is intended as a precaution against
+*    inadvertent publication and does not imply publication or any waiver
+*    of confidentiality.  The year included in the foregoing notice is the
+*    year of creation of the work.
+*
+*/
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
new file mode 100644
index 000000000000..ec7c7e126612
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
@@ -0,0 +1,590 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
new file mode 100644
index 000000000000..17379dcfa0e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
new file mode 100644
index 000000000000..3cd315f903db
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
@@ -0,0 +1,14292 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+/*
+*   yamato_registers.h
+*
+*   Register Spec Release:  Chip Spec 1.0
+*
+*
+*    (c) 2000 ATI Technologies Inc.  (unpublished)
+*
+*    All rights reserved.  This notice is intended as a precaution against
+*    inadvertent publication and does not imply publication or any waiver
+*    of confidentiality.  The year included in the foregoing notice is the
+*    year of creation of the work.
+*
+*/
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 2;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                                 : 2;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
new file mode 100644
index 000000000000..10807b43ea44
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
@@ -0,0 +1,4183 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
new file mode 100644
index 000000000000..9e9c7282dcdb
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
@@ -0,0 +1,52571 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 2;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
new file mode 100644
index 000000000000..6968abb48bd7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
new file mode 100644
index 000000000000..ba259a6c9d5f
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
@@ -0,0 +1,169 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamatoix_h
+#define _yamatoix_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+// [SUDEBUGIND] : Indirect Registers
+
+#define ixCLIPPER_DEBUG_REG00                      0x0000
+#define ixCLIPPER_DEBUG_REG01                      0x0001
+#define ixCLIPPER_DEBUG_REG02                      0x0002
+#define ixCLIPPER_DEBUG_REG03                      0x0003
+#define ixCLIPPER_DEBUG_REG04                      0x0004
+#define ixCLIPPER_DEBUG_REG05                      0x0005
+#define ixCLIPPER_DEBUG_REG09                      0x0009
+#define ixCLIPPER_DEBUG_REG10                      0x000A
+#define ixCLIPPER_DEBUG_REG11                      0x000B
+#define ixCLIPPER_DEBUG_REG12                      0x000C
+#define ixCLIPPER_DEBUG_REG13                      0x000D
+#define ixSXIFCCG_DEBUG_REG0                       0x0011
+#define ixSXIFCCG_DEBUG_REG1                       0x0012
+#define ixSXIFCCG_DEBUG_REG2                       0x0013
+#define ixSXIFCCG_DEBUG_REG3                       0x0014
+#define ixSETUP_DEBUG_REG0                         0x0015
+#define ixSETUP_DEBUG_REG1                         0x0016
+#define ixSETUP_DEBUG_REG2                         0x0017
+#define ixSETUP_DEBUG_REG3                         0x0018
+#define ixSETUP_DEBUG_REG4                         0x0019
+#define ixSETUP_DEBUG_REG5                         0x001A
+
+// [SCDEBUGIND] : Indirect Registers
+
+#define ixSC_DEBUG_0                               0x0000
+#define ixSC_DEBUG_1                               0x0001
+#define ixSC_DEBUG_2                               0x0002
+#define ixSC_DEBUG_3                               0x0003
+#define ixSC_DEBUG_4                               0x0004
+#define ixSC_DEBUG_5                               0x0005
+#define ixSC_DEBUG_6                               0x0006
+#define ixSC_DEBUG_7                               0x0007
+#define ixSC_DEBUG_8                               0x0008
+#define ixSC_DEBUG_9                               0x0009
+#define ixSC_DEBUG_10                              0x000A
+#define ixSC_DEBUG_11                              0x000B
+#define ixSC_DEBUG_12                              0x000C
+
+// [VGTDEBUGIND] : Indirect Registers
+
+#define ixVGT_DEBUG_REG0                           0x0000
+#define ixVGT_DEBUG_REG1                           0x0001
+#define ixVGT_DEBUG_REG3                           0x0003
+#define ixVGT_DEBUG_REG6                           0x0006
+#define ixVGT_DEBUG_REG7                           0x0007
+#define ixVGT_DEBUG_REG8                           0x0008
+#define ixVGT_DEBUG_REG9                           0x0009
+#define ixVGT_DEBUG_REG10                          0x000A
+#define ixVGT_DEBUG_REG12                          0x000C
+#define ixVGT_DEBUG_REG13                          0x000D
+#define ixVGT_DEBUG_REG14                          0x000E
+#define ixVGT_DEBUG_REG15                          0x000F
+#define ixVGT_DEBUG_REG16                          0x0010
+#define ixVGT_DEBUG_REG17                          0x0011
+#define ixVGT_DEBUG_REG18                          0x0012
+#define ixVGT_DEBUG_REG20                          0x0014
+#define ixVGT_DEBUG_REG21                          0x0015
+
+// [MHDEBUGIND] : Indirect Registers
+
+#define ixMH_DEBUG_REG00                           0x0000
+#define ixMH_DEBUG_REG01                           0x0001
+#define ixMH_DEBUG_REG02                           0x0002
+#define ixMH_DEBUG_REG03                           0x0003
+#define ixMH_DEBUG_REG04                           0x0004
+#define ixMH_DEBUG_REG05                           0x0005
+#define ixMH_DEBUG_REG06                           0x0006
+#define ixMH_DEBUG_REG07                           0x0007
+#define ixMH_DEBUG_REG08                           0x0008
+#define ixMH_DEBUG_REG09                           0x0009
+#define ixMH_DEBUG_REG10                           0x000A
+#define ixMH_DEBUG_REG11                           0x000B
+#define ixMH_DEBUG_REG12                           0x000C
+#define ixMH_DEBUG_REG13                           0x000D
+#define ixMH_DEBUG_REG14                           0x000E
+#define ixMH_DEBUG_REG15                           0x000F
+#define ixMH_DEBUG_REG16                           0x0010
+#define ixMH_DEBUG_REG17                           0x0011
+#define ixMH_DEBUG_REG18                           0x0012
+#define ixMH_DEBUG_REG19                           0x0013
+#define ixMH_DEBUG_REG20                           0x0014
+#define ixMH_DEBUG_REG21                           0x0015
+#define ixMH_DEBUG_REG22                           0x0016
+#define ixMH_DEBUG_REG23                           0x0017
+#define ixMH_DEBUG_REG24                           0x0018
+#define ixMH_DEBUG_REG25                           0x0019
+#define ixMH_DEBUG_REG26                           0x001A
+#define ixMH_DEBUG_REG27                           0x001B
+#define ixMH_DEBUG_REG28                           0x001C
+#define ixMH_DEBUG_REG29                           0x001D
+#define ixMH_DEBUG_REG30                           0x001E
+#define ixMH_DEBUG_REG31                           0x001F
+#define ixMH_DEBUG_REG32                           0x0020
+#define ixMH_DEBUG_REG33                           0x0021
+#define ixMH_DEBUG_REG34                           0x0022
+#define ixMH_DEBUG_REG35                           0x0023
+#define ixMH_DEBUG_REG36                           0x0024
+#define ixMH_DEBUG_REG37                           0x0025
+#define ixMH_DEBUG_REG38                           0x0026
+#define ixMH_DEBUG_REG39                           0x0027
+#define ixMH_DEBUG_REG40                           0x0028
+#define ixMH_DEBUG_REG41                           0x0029
+#define ixMH_DEBUG_REG42                           0x002A
+#define ixMH_DEBUG_REG43                           0x002B
+#define ixMH_DEBUG_REG44                           0x002C
+#define ixMH_DEBUG_REG45                           0x002D
+#define ixMH_DEBUG_REG46                           0x002E
+#define ixMH_DEBUG_REG47                           0x002F
+#define ixMH_DEBUG_REG48                           0x0030
+#define ixMH_DEBUG_REG49                           0x0031
+#define ixMH_DEBUG_REG50                           0x0032
+#define ixMH_DEBUG_REG51                           0x0033
+#define ixMH_DEBUG_REG52                           0x0034
+#define ixMH_DEBUG_REG53                           0x0035
+#define ixMH_DEBUG_REG54                           0x0036
+#define ixMH_DEBUG_REG55                           0x0037
+#define ixMH_DEBUG_REG56                           0x0038
+#define ixMH_DEBUG_REG57                           0x0039
+#define ixMH_DEBUG_REG58                           0x003A
+#define ixMH_DEBUG_REG59                           0x003B
+#define ixMH_DEBUG_REG60                           0x003C
+#define ixMH_DEBUG_REG61                           0x003D
+#define ixMH_DEBUG_REG62                           0x003E
+#define ixMH_DEBUG_REG63                           0x003F
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
+#endif // _yamatob_h
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
new file mode 100644
index 000000000000..ab11205f1092
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
@@ -0,0 +1,1867 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ SPARE33 = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_ALU1_ACTIVE_VTX_SIMD3 = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_ALU1_ACTIVE_PIX_SIMD3 = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_SYNC_ALU_STALL_SIMD3_VTX = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_SYNC_ALU_STALL_SIMD3_PIX = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_CONSTANTS_USED_SIMD3 = 85,
+ SQ_CONSTANTS_SENT_SP_SIMD3 = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_W_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
new file mode 100644
index 000000000000..f2f4dec63daa
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
@@ -0,0 +1,1674 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(SPARE33, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_W_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
new file mode 100644
index 000000000000..d44be483e953
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
@@ -0,0 +1,3310 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SST_0_ABS_MOD, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int)
+    GENERATE_FIELD(VSYNC_ACTIVE, int)
+    GENERATE_FIELD(USE_DISPLAY_ID0, int)
+    GENERATE_FIELD(USE_DISPLAY_ID1, int)
+    GENERATE_FIELD(USE_DISPLAY_ID2, int)
+    GENERATE_FIELD(SW_CNTL, int)
+    GENERATE_FIELD(NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED9, bool)
+    GENERATE_FIELD(RESERVED10, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
new file mode 100644
index 000000000000..0e32e421d0a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
new file mode 100644
index 000000000000..ad3d829bc94e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
@@ -0,0 +1,5739 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fpos_MASK                              0x00000010L
+#define SC_DEBUG_7__fpos                                   0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fpos_MASK                              0x00100000L
+#define SC_DEBUG_8__fpos                                   0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK           0x00000040L
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD                0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK           0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD                0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000400L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00000800L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00001000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00002000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00004000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00008000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00010000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00020000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00040000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00080000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00100000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00400000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x01000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x04000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BE_q_MASK                       0x00003fc0L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00004000L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00004000L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00008000L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00008000L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00010000L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00020000L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00020000L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00040000L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00040000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00100000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00100000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00200000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00200000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00400000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00400000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00800000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00800000L
+#define MH_DEBUG_REG01__RB_BE_q_MASK                       0xff000000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x0001c000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x00060000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG08__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG09__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG09__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG09__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG10__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG11__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG11__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG14__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG14__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG17__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG17__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG17__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG17__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG17__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG17__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG17__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG17__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG17__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG17__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG17__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG17__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG17__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG17__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG17__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG17__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG17__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG17__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG17__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG17__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG17__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG17__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG17__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG17__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG17__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG17__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG17__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG17__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG17__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG18__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG18__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG18__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG18__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG18__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG18__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG18__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG18__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG18__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG18__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG18__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG18__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG18__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG18__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG18__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG18__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG18__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG18__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG18__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG18__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG18__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG18__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG18__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG18__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG20__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG20__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG20__REG_RE                             0x00010000L
+#define MH_DEBUG_REG20__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG20__REG_WE                             0x00020000L
+#define MH_DEBUG_REG20__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG20__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK           0x00000001L
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req                0x00000001L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK           0x00000002L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack                0x00000002L
+#define MH_DEBUG_REG22__MH_RBBM_busy_MASK                  0x00000004L
+#define MH_DEBUG_REG22__MH_RBBM_busy                       0x00000004L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK          0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int               0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK         0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int              0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK       0x00000020L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int            0x00000020L
+#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK                   0x00000040L
+#define MH_DEBUG_REG22__GAT_CLK_ENA                        0x00000040L
+#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK                   0x00000080L
+#define MH_DEBUG_REG22__AXI_RDY_ENA                        0x00000080L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK       0x00000100L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override            0x00000100L
+#define MH_DEBUG_REG22__CNT_q_MASK                         0x00007e00L
+#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK                   0x00008000L
+#define MH_DEBUG_REG22__TCD_EMPTY_q                        0x00008000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK                  0x00010000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY                       0x00010000L
+#define MH_DEBUG_REG22__MH_BUSY_d_MASK                     0x00020000L
+#define MH_DEBUG_REG22__MH_BUSY_d                          0x00020000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK                 0x00040000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY                      0x00040000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00080000L
+#define MH_DEBUG_REG22__CP_SEND_q_MASK                     0x00100000L
+#define MH_DEBUG_REG22__CP_SEND_q                          0x00100000L
+#define MH_DEBUG_REG22__CP_RTR_q_MASK                      0x00200000L
+#define MH_DEBUG_REG22__CP_RTR_q                           0x00200000L
+#define MH_DEBUG_REG22__VGT_SEND_q_MASK                    0x00400000L
+#define MH_DEBUG_REG22__VGT_SEND_q                         0x00400000L
+#define MH_DEBUG_REG22__VGT_RTR_q_MASK                     0x00800000L
+#define MH_DEBUG_REG22__VGT_RTR_q                          0x00800000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK                 0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q                      0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG22__RB_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG22__RB_SEND_q                          0x04000000L
+#define MH_DEBUG_REG22__RB_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__RB_RTR_q                           0x08000000L
+#define MH_DEBUG_REG22__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG22__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG22__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG22__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG22__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG22__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG23__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG23__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG23__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG23__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG23__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG23__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG23__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG23__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG23__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG23__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG23__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG23__ARB_QUAL_MASK                      0x01000000L
+#define MH_DEBUG_REG23__ARB_QUAL                           0x01000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK                   0x02000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ                        0x02000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ                       0x04000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK                   0x08000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ                        0x08000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK             0x20000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK                  0x20000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG24__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG24__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG24__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG24__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG24__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG24__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG24__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG24__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG24__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG24__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG24__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG24__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG24__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG24__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG25__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK          0x000001c0L
+#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK                0x00000e00L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK         0x00001000L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d              0x00001000L
+#define MH_DEBUG_REG25__ARB_HOLD_MASK                      0x00002000L
+#define MH_DEBUG_REG25__ARB_HOLD                           0x00002000L
+#define MH_DEBUG_REG25__ARB_RTR_q_MASK                     0x00004000L
+#define MH_DEBUG_REG25__ARB_RTR_q                          0x00004000L
+#define MH_DEBUG_REG25__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG25__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG25__CLNT_REQ_MASK                      0x000f0000L
+#define MH_DEBUG_REG25__RECENT_d_0_MASK                    0x00700000L
+#define MH_DEBUG_REG25__RECENT_d_1_MASK                    0x03800000L
+#define MH_DEBUG_REG25__RECENT_d_2_MASK                    0x1c000000L
+#define MH_DEBUG_REG25__RECENT_d_3_MASK                    0xe0000000L
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG26__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG26__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG26__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG26__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG26__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG26__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG26__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG26__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG26__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG26__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG26__ARB_WINNER_MASK                    0x70000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG28__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG28__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG28__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG28__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG29__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG29__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG29__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG29__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG29__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG29__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG31__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG32__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG33__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG34__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG39__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG39__MMU_RTR_MASK                       0x00000002L
+#define MH_DEBUG_REG39__MMU_RTR                            0x00000002L
+#define MH_DEBUG_REG39__ARB_ID_q_MASK                      0x0000001cL
+#define MH_DEBUG_REG39__ARB_WRITE_q_MASK                   0x00000020L
+#define MH_DEBUG_REG39__ARB_WRITE_q                        0x00000020L
+#define MH_DEBUG_REG39__ARB_BLEN_q_MASK                    0x00000040L
+#define MH_DEBUG_REG39__ARB_BLEN_q                         0x00000040L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK                0x00000080L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY                     0x00000080L
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK                0x00000700L
+#define MH_DEBUG_REG39__MMU_WE_MASK                        0x00000800L
+#define MH_DEBUG_REG39__MMU_WE                             0x00000800L
+#define MH_DEBUG_REG39__ARQ_RTR_MASK                       0x00001000L
+#define MH_DEBUG_REG39__ARQ_RTR                            0x00001000L
+#define MH_DEBUG_REG39__MMU_ID_MASK                        0x0000e000L
+#define MH_DEBUG_REG39__MMU_WRITE_MASK                     0x00010000L
+#define MH_DEBUG_REG39__MMU_WRITE                          0x00010000L
+#define MH_DEBUG_REG39__MMU_BLEN_MASK                      0x00020000L
+#define MH_DEBUG_REG39__MMU_BLEN                           0x00020000L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG40__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG40__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG40__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG41__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG41__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG41__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG42__WDB_WE                             0x00000001L
+#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK                  0x00000002L
+#define MH_DEBUG_REG42__WDB_RTR_SKID                       0x00000002L
+#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK                   0x000003fcL
+#define MH_DEBUG_REG42__ARB_WLAST_MASK                     0x00000400L
+#define MH_DEBUG_REG42__ARB_WLAST                          0x00000400L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK                0x00000800L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY                     0x00000800L
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK                0x0001f000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK                  0x00020000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q                       0x00020000L
+#define MH_DEBUG_REG42__WDB_WDC_WID_MASK                   0x001c0000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK                 0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST                      0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK                 0x3fc00000L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK              0xffffffffL
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK             0xffffffffL
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG47__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG47__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG47__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG47__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG47__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG47__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG47__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG47__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG47__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG47__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG48__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG48__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG48__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG48__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG48__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG48__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG48__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG48__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG48__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG48__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG48__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG48__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK               0x00ffffffL
+#define MH_DEBUG_REG50__ARB_ID_q_MASK                      0x07000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q_MASK                   0x08000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q                        0x08000000L
+#define MH_DEBUG_REG50__client_behavior_q_MASK             0x30000000L
+#define MH_DEBUG_REG50__ARB_WE_MASK                        0x40000000L
+#define MH_DEBUG_REG50__ARB_WE                             0x40000000L
+#define MH_DEBUG_REG50__MMU_RTR_MASK                       0x80000000L
+#define MH_DEBUG_REG50__MMU_RTR                            0x80000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG51__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG51__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG51__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG51__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG51__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG51__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG51__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG51__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG51__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG51__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG51__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG51__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG51__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG51__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG51__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG51__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG51__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG52__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG52__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG52__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG52__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG52__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG52__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG52__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG52__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG52__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG52__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG52__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG52__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG52__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG52__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG52__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG52__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG53__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG53__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG53__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG53__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG53__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG54__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG54__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG54__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG54__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG54__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK                0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE                     0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK                0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE                     0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK                0x00000004L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE                     0x00000004L
+#define RBBM_DSPLY__VSYNC_ACTIVE_MASK                      0x00000008L
+#define RBBM_DSPLY__VSYNC_ACTIVE                           0x00000008L
+#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK                   0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID0                        0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK                   0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID1                        0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK                   0x00000040L
+#define RBBM_DSPLY__USE_DISPLAY_ID2                        0x00000040L
+#define RBBM_DSPLY__SW_CNTL_MASK                           0x00000080L
+#define RBBM_DSPLY__SW_CNTL                                0x00000080L
+#define RBBM_DSPLY__NUM_BUFS_MASK                          0x00000300L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID_MASK                 0x00000003L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__RESERVED9_MASK                      0x40000000L
+#define RB_BC_CONTROL__RESERVED9                           0x40000000L
+#define RB_BC_CONTROL__RESERVED10_MASK                     0x80000000L
+#define RB_BC_CONTROL__RESERVED10                          0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
new file mode 100644
index 000000000000..6a229a8e79e2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
@@ -0,0 +1,581 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x01CC
+#define mmCP_IB1_BUFSZ                 0x01CD
+#define mmCP_IB2_BASE                  0x01CE
+#define mmCP_IB2_BUFSZ                 0x01CF
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x045F
+#define mmCP_PFP_UCODE_DATA            0x0460
+#define mmCP_PERFMON_CNTL              0x01F5
+#define mmCP_PERFCOUNTER_SELECT        0x01E6
+#define mmCP_PERFCOUNTER_LO            0x01E7
+#define mmCP_PERFCOUNTER_HI            0x01E8
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
new file mode 100644
index 000000000000..7e293b371bcd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
new file mode 100644
index 000000000000..b021d446a229
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
@@ -0,0 +1,13962 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                            fpos : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                            fpos : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                                 : 3;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 3;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                         RB_BE_q : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BE_q : 8;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             CIB_MH_axi_halt_req : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int             CIB_MH_axi_halt_req : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          WDB_WE : 1;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                          WDB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BUFFER_ID : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                       BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int                                 : 15;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int                                 : 15;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                                 : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 28;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int                      RESERVED10 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED10 : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
new file mode 100644
index 000000000000..2049d0f7bd14
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
@@ -0,0 +1,4078 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fpos__SHIFT                            0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fpos__SHIFT                            0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT         0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000a
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000b
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000c
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000d
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000e
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x0000000f
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000011
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000013
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001a
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BE_q__SHIFT                     0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x0000000e
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x0000000f
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x00000011
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x00000013
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x00000014
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x00000015
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000016
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000017
+#define MH_DEBUG_REG01__RB_BE_q__SHIFT                     0x00000018
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000e
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000011
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG08__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG09__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG11__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG17__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG17__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG17__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG17__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG17__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG17__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG17__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG17__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG17__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG17__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG17__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG17__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG17__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG17__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG17__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG17__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG18__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG18__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG18__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG18__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG18__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG18__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG18__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG18__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG18__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG18__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG18__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG18__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG18__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG20__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG20__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG20__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG20__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT         0x00000000
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT         0x00000001
+#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT                0x00000002
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT        0x00000003
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT       0x00000004
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000005
+#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT                 0x00000006
+#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT                 0x00000007
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT     0x00000008
+#define MH_DEBUG_REG22__CNT_q__SHIFT                       0x00000009
+#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT                 0x0000000f
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT                0x00000010
+#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT                   0x00000011
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT               0x00000012
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013
+#define MH_DEBUG_REG22__CP_SEND_q__SHIFT                   0x00000014
+#define MH_DEBUG_REG22__CP_RTR_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT                  0x00000016
+#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT                   0x00000017
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT               0x00000018
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG22__RB_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG22__RB_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG22__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG22__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG23__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG23__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG23__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG23__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG23__ARB_QUAL__SHIFT                    0x00000018
+#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT                 0x00000019
+#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT                 0x0000001b
+#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT           0x0000001d
+#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG24__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG24__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG24__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG24__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG25__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT        0x00000006
+#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT              0x00000009
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT       0x0000000c
+#define MH_DEBUG_REG25__ARB_HOLD__SHIFT                    0x0000000d
+#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT                   0x0000000e
+#define MH_DEBUG_REG25__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG25__CLNT_REQ__SHIFT                    0x00000010
+#define MH_DEBUG_REG25__RECENT_d_0__SHIFT                  0x00000014
+#define MH_DEBUG_REG25__RECENT_d_1__SHIFT                  0x00000017
+#define MH_DEBUG_REG25__RECENT_d_2__SHIFT                  0x0000001a
+#define MH_DEBUG_REG25__RECENT_d_3__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG26__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG26__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG26__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG26__ARB_WINNER__SHIFT                  0x0000001c
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG28__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG29__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG29__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG39__MMU_RTR__SHIFT                     0x00000001
+#define MH_DEBUG_REG39__ARB_ID_q__SHIFT                    0x00000002
+#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT                 0x00000005
+#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT                  0x00000006
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT              0x00000007
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT              0x00000008
+#define MH_DEBUG_REG39__MMU_WE__SHIFT                      0x0000000b
+#define MH_DEBUG_REG39__ARQ_RTR__SHIFT                     0x0000000c
+#define MH_DEBUG_REG39__MMU_ID__SHIFT                      0x0000000d
+#define MH_DEBUG_REG39__MMU_WRITE__SHIFT                   0x00000010
+#define MH_DEBUG_REG39__MMU_BLEN__SHIFT                    0x00000011
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG40__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG41__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG41__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT                 0x00000002
+#define MH_DEBUG_REG42__ARB_WLAST__SHIFT                   0x0000000a
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT              0x0000000b
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT              0x0000000c
+#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT                0x00000011
+#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT                 0x00000012
+#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT               0x00000015
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT               0x00000016
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT            0x00000000
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT           0x00000000
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG47__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG47__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG47__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG47__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG47__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG48__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG48__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG48__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG48__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT             0x00000000
+#define MH_DEBUG_REG50__ARB_ID_q__SHIFT                    0x00000018
+#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT                 0x0000001b
+#define MH_DEBUG_REG50__client_behavior_q__SHIFT           0x0000001c
+#define MH_DEBUG_REG50__ARB_WE__SHIFT                      0x0000001e
+#define MH_DEBUG_REG50__MMU_RTR__SHIFT                     0x0000001f
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG51__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG51__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG51__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG51__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG51__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG52__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG52__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG52__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG52__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG52__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG52__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG52__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG53__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG54__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT              0x00000000
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT              0x00000001
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT              0x00000002
+#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT                    0x00000003
+#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT                 0x00000004
+#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT                 0x00000005
+#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT                 0x00000006
+#define RBBM_DSPLY__SW_CNTL__SHIFT                         0x00000007
+#define RBBM_DSPLY__NUM_BUFS__SHIFT                        0x00000008
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT               0x00000000
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__RESERVED9__SHIFT                    0x0000001e
+#define RB_BC_CONTROL__RESERVED10__SHIFT                   0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
new file mode 100644
index 000000000000..80b9106759e3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
@@ -0,0 +1,51301 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1
+#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE   1
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1
+#define RBBM_DSPLY_SW_CNTL_SIZE        1
+#define RBBM_DSPLY_NUM_BUFS_SIZE       2
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2
+#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT  3
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6
+#define RBBM_DSPLY_SW_CNTL_SHIFT       7
+#define RBBM_DSPLY_NUM_BUFS_SHIFT      8
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004
+#define RBBM_DSPLY_VSYNC_ACTIVE_MASK   0x00000008
+#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010
+#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020
+#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040
+#define RBBM_DSPLY_SW_CNTL_MASK        0x00000080
+#define RBBM_DSPLY_NUM_BUFS_MASK       0x00000300
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \
+      RBBM_DSPLY_VSYNC_ACTIVE_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \
+      RBBM_DSPLY_SW_CNTL_MASK | \
+      RBBM_DSPLY_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \
+     ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \
+      (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \
+      (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \
+      (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \
+      (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \
+      (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \
+      (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \
+      (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \
+      (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int                                : 22;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int                                : 22;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(buffer_id) \
+     ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+          unsigned int                                : 30;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 30;
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int                                : 6;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 6;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 21;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 21;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  12
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  14
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00000800
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00001000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00002000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00004000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 5;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BE_q_SIZE    8
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_RB_BE_q_SIZE    8
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BE_q_SHIFT   6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  18
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  23
+#define MH_DEBUG_REG01_RB_BE_q_SHIFT   24
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BE_q_MASK    0x00003fc0
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00008000
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00010000
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00020000
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00040000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00400000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00800000
+#define MH_DEBUG_REG01_RB_BE_q_MASK    0xff000000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BE_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_RB_BE_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   14
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x0001c000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x00060000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 13;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG08_VGT_MH_send_MASK | \
+      MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_TC_MH_send_MASK | \
+      MH_DEBUG_REG09_TC_MH_mask_MASK | \
+      MH_DEBUG_REG09_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_TC_MH_info_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG11_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG11_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG14_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG14_RB_MH_send_MASK | \
+      MH_DEBUG_REG14_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG15(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_AVALID_q_SIZE   1
+#define MH_DEBUG_REG17_AREADY_q_SIZE   1
+#define MH_DEBUG_REG17_AID_q_SIZE      3
+#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG17_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG17_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG17_ARID_q_SIZE     3
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG17_RVALID_q_SIZE   1
+#define MH_DEBUG_REG17_RREADY_q_SIZE   1
+#define MH_DEBUG_REG17_RLAST_q_SIZE    1
+#define MH_DEBUG_REG17_RID_q_SIZE      3
+#define MH_DEBUG_REG17_WVALID_q_SIZE   1
+#define MH_DEBUG_REG17_WREADY_q_SIZE   1
+#define MH_DEBUG_REG17_WLAST_q_SIZE    1
+#define MH_DEBUG_REG17_WID_q_SIZE      3
+#define MH_DEBUG_REG17_BVALID_q_SIZE   1
+#define MH_DEBUG_REG17_BREADY_q_SIZE   1
+#define MH_DEBUG_REG17_BID_q_SIZE      3
+
+#define MH_DEBUG_REG17_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG17_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG17_AID_q_SHIFT     2
+#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG17_ARID_q_SHIFT    10
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG17_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG17_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG17_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG17_RID_q_SHIFT     18
+#define MH_DEBUG_REG17_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG17_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG17_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG17_WID_q_SHIFT     24
+#define MH_DEBUG_REG17_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG17_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG17_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG17_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG17_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG17_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG17_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG17_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG17_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG17_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG17_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG17_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG17_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG17_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG17_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG17_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG17_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG17_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG17_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG17_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_AVALID_q_MASK | \
+      MH_DEBUG_REG17_AREADY_q_MASK | \
+      MH_DEBUG_REG17_AID_q_MASK | \
+      MH_DEBUG_REG17_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG17_ARVALID_q_MASK | \
+      MH_DEBUG_REG17_ARREADY_q_MASK | \
+      MH_DEBUG_REG17_ARID_q_MASK | \
+      MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG17_RVALID_q_MASK | \
+      MH_DEBUG_REG17_RREADY_q_MASK | \
+      MH_DEBUG_REG17_RLAST_q_MASK | \
+      MH_DEBUG_REG17_RID_q_MASK | \
+      MH_DEBUG_REG17_WVALID_q_MASK | \
+      MH_DEBUG_REG17_WREADY_q_MASK | \
+      MH_DEBUG_REG17_WLAST_q_MASK | \
+      MH_DEBUG_REG17_WID_q_MASK | \
+      MH_DEBUG_REG17_BVALID_q_MASK | \
+      MH_DEBUG_REG17_BREADY_q_MASK | \
+      MH_DEBUG_REG17_BID_q_MASK)
+
+#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG17_BID_q_SHIFT))
+
+#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT)
+
+#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_AVALID_q_SIZE   1
+#define MH_DEBUG_REG18_AREADY_q_SIZE   1
+#define MH_DEBUG_REG18_AID_q_SIZE      3
+#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG18_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG18_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG18_ARID_q_SIZE     3
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG18_WVALID_q_SIZE   1
+#define MH_DEBUG_REG18_WREADY_q_SIZE   1
+#define MH_DEBUG_REG18_WLAST_q_SIZE    1
+#define MH_DEBUG_REG18_WID_q_SIZE      3
+#define MH_DEBUG_REG18_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG18_BVALID_q_SIZE   1
+#define MH_DEBUG_REG18_BREADY_q_SIZE   1
+#define MH_DEBUG_REG18_BID_q_SIZE      3
+
+#define MH_DEBUG_REG18_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG18_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG18_AID_q_SHIFT     2
+#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG18_ARID_q_SHIFT    9
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG18_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG18_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG18_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG18_WID_q_SHIFT     16
+#define MH_DEBUG_REG18_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG18_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG18_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG18_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG18_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG18_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG18_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG18_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG18_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG18_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG18_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG18_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG18_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG18_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG18_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG18_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG18_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG18_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_AVALID_q_MASK | \
+      MH_DEBUG_REG18_AREADY_q_MASK | \
+      MH_DEBUG_REG18_AID_q_MASK | \
+      MH_DEBUG_REG18_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG18_ARVALID_q_MASK | \
+      MH_DEBUG_REG18_ARREADY_q_MASK | \
+      MH_DEBUG_REG18_ARID_q_MASK | \
+      MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG18_WVALID_q_MASK | \
+      MH_DEBUG_REG18_WREADY_q_MASK | \
+      MH_DEBUG_REG18_WLAST_q_MASK | \
+      MH_DEBUG_REG18_WID_q_MASK | \
+      MH_DEBUG_REG18_WSTRB_q_MASK | \
+      MH_DEBUG_REG18_BVALID_q_MASK | \
+      MH_DEBUG_REG18_BREADY_q_MASK | \
+      MH_DEBUG_REG18_BID_q_MASK)
+
+#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG18_BID_q_SHIFT))
+
+#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT)
+
+#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG20_REG_A_SIZE      14
+#define MH_DEBUG_REG20_REG_RE_SIZE     1
+#define MH_DEBUG_REG20_REG_WE_SIZE     1
+#define MH_DEBUG_REG20_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG20_REG_A_SHIFT     2
+#define MH_DEBUG_REG20_REG_RE_SHIFT    16
+#define MH_DEBUG_REG20_REG_WE_SHIFT    17
+#define MH_DEBUG_REG20_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG20_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG20_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG20_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG20_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG20_REG_A_MASK | \
+      MH_DEBUG_REG20_REG_RE_MASK | \
+      MH_DEBUG_REG20_REG_WE_MASK | \
+      MH_DEBUG_REG20_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG21_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG21_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_REG_WD_MASK)
+
+#define MH_DEBUG_REG21(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG22_CNT_q_SIZE      6
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG22_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG22_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG22_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG22_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG22_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8
+#define MH_DEBUG_REG22_CNT_q_SHIFT     9
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16
+#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19
+#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20
+#define MH_DEBUG_REG22_CP_RTR_q_SHIFT  21
+#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22
+#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26
+#define MH_DEBUG_REG22_RB_RTR_q_SHIFT  27
+#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002
+#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020
+#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040
+#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100
+#define MH_DEBUG_REG22_CNT_q_MASK      0x00007e00
+#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000
+#define MH_DEBUG_REG22_MH_BUSY_d_MASK  0x00020000
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000
+#define MH_DEBUG_REG22_CP_SEND_q_MASK  0x00100000
+#define MH_DEBUG_REG22_CP_RTR_q_MASK   0x00200000
+#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG22_VGT_RTR_q_MASK  0x00800000
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG22_RB_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG22_RB_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG22_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG22_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG22_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \
+      MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \
+      MH_DEBUG_REG22_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \
+      MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG22_CNT_q_MASK | \
+      MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG22_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG22_CP_SEND_q_MASK | \
+      MH_DEBUG_REG22_CP_RTR_q_MASK | \
+      MH_DEBUG_REG22_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG22_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG22_RB_SEND_q_MASK | \
+      MH_DEBUG_REG22_RB_RTR_q_MASK | \
+      MH_DEBUG_REG22_RDC_VALID_MASK | \
+      MH_DEBUG_REG22_RDC_RLAST_MASK | \
+      MH_DEBUG_REG22_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG22_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \
+      (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \
+      (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG23_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG23_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG23_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG23_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG23_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG23_ARB_QUAL_SHIFT  24
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG23_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG23_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG23_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG23_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG23_ARB_QUAL_MASK   0x01000000
+#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG23_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG23_EFF1_WIN_MASK | \
+      MH_DEBUG_REG23_KILL_EFF1_MASK | \
+      MH_DEBUG_REG23_ARB_HOLD_MASK | \
+      MH_DEBUG_REG23_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_ARB_QUAL_MASK | \
+      MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG23_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG24_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG24_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG24_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG24_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG24_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG24_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG24_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG24_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG24_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG24_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG24_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG24_ARB_WINNER_MASK | \
+      MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_ARB_QUAL_MASK | \
+      MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_EFF1_WIN_MASK | \
+      MH_DEBUG_REG24_KILL_EFF1_MASK | \
+      MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG25_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG25_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG25_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG25_CLNT_REQ_SIZE   4
+#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12
+#define MH_DEBUG_REG25_ARB_HOLD_SHIFT  13
+#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14
+#define MH_DEBUG_REG25_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG25_CLNT_REQ_SHIFT  16
+#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20
+#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23
+#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26
+#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0
+#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000
+#define MH_DEBUG_REG25_ARB_HOLD_MASK   0x00002000
+#define MH_DEBUG_REG25_ARB_RTR_q_MASK  0x00004000
+#define MH_DEBUG_REG25_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG25_CLNT_REQ_MASK   0x000f0000
+#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000
+#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000
+#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000
+#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG25_ARB_WINNER_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG25_ARB_HOLD_MASK | \
+      MH_DEBUG_REG25_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG25_EFF1_WIN_MASK | \
+      MH_DEBUG_REG25_CLNT_REQ_MASK | \
+      MH_DEBUG_REG25_RECENT_d_0_MASK | \
+      MH_DEBUG_REG25_RECENT_d_1_MASK | \
+      MH_DEBUG_REG25_RECENT_d_2_MASK | \
+      MH_DEBUG_REG25_RECENT_d_3_MASK)
+
+#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT))
+
+#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG26_WLAST_q_SIZE    1
+#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG26_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG26_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_MH_written_MASK | \
+      MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG26_WLAST_q_MASK | \
+      MH_DEBUG_REG26_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG26_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_CP_MH_write_MASK | \
+      MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int                                : 1;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int                                : 1;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG28_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG28_TC_MH_send_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG29_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG29_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG29_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG29_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG29_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG29_TC_MH_send_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG29_KILL_EFF1_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_TC_MH_send_MASK | \
+      MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_TC_MH_send_MASK | \
+      MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_ARB_WE_SIZE     1
+#define MH_DEBUG_REG39_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG39_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG39_MMU_WE_SIZE     1
+#define MH_DEBUG_REG39_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG39_MMU_ID_SIZE     3
+#define MH_DEBUG_REG39_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG39_MMU_BLEN_SIZE   1
+
+#define MH_DEBUG_REG39_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG39_MMU_RTR_SHIFT   1
+#define MH_DEBUG_REG39_ARB_ID_q_SHIFT  2
+#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5
+#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8
+#define MH_DEBUG_REG39_MMU_WE_SHIFT    11
+#define MH_DEBUG_REG39_ARQ_RTR_SHIFT   12
+#define MH_DEBUG_REG39_MMU_ID_SHIFT    13
+#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16
+#define MH_DEBUG_REG39_MMU_BLEN_SHIFT  17
+
+#define MH_DEBUG_REG39_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG39_MMU_RTR_MASK    0x00000002
+#define MH_DEBUG_REG39_ARB_ID_q_MASK   0x0000001c
+#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020
+#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700
+#define MH_DEBUG_REG39_MMU_WE_MASK     0x00000800
+#define MH_DEBUG_REG39_ARQ_RTR_MASK    0x00001000
+#define MH_DEBUG_REG39_MMU_ID_MASK     0x0000e000
+#define MH_DEBUG_REG39_MMU_WRITE_MASK  0x00010000
+#define MH_DEBUG_REG39_MMU_BLEN_MASK   0x00020000
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_ARB_WE_MASK | \
+      MH_DEBUG_REG39_MMU_RTR_MASK | \
+      MH_DEBUG_REG39_ARB_ID_q_MASK | \
+      MH_DEBUG_REG39_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG39_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG39_MMU_WE_MASK | \
+      MH_DEBUG_REG39_ARQ_RTR_MASK | \
+      MH_DEBUG_REG39_MMU_ID_MASK | \
+      MH_DEBUG_REG39_MMU_WRITE_MASK | \
+      MH_DEBUG_REG39_MMU_BLEN_MASK)
+
+#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \
+     ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT))
+
+#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int                                : 14;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int                                : 14;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_ARB_WE_SIZE     1
+#define MH_DEBUG_REG40_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG40_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG40_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG40_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG40_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG40_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG40_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_ARB_WE_MASK | \
+      MH_DEBUG_REG40_ARB_ID_q_MASK | \
+      MH_DEBUG_REG40_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_MMU_WE_SIZE     1
+#define MH_DEBUG_REG41_MMU_ID_SIZE     3
+#define MH_DEBUG_REG41_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG41_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG41_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG41_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG41_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG41_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG41_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_MMU_WE_MASK | \
+      MH_DEBUG_REG41_MMU_ID_MASK | \
+      MH_DEBUG_REG41_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_WDB_WE_SIZE     1
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG42_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG42_WDB_WE_SHIFT    0
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2
+#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17
+#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22
+
+#define MH_DEBUG_REG42_WDB_WE_MASK     0x00000001
+#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002
+#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc
+#define MH_DEBUG_REG42_ARB_WLAST_MASK  0x00000400
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000
+#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_WDB_WE_MASK | \
+      MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \
+      MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG42_ARB_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int                                : 2;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK)
+
+#define MH_DEBUG_REG43(arb_wdata_q_31_0) \
+     ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK)
+
+#define MH_DEBUG_REG44(arb_wdata_q_63_32) \
+     ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RVALID_q_SIZE   1
+#define MH_DEBUG_REG47_RREADY_q_SIZE   1
+#define MH_DEBUG_REG47_RLAST_q_SIZE    1
+#define MH_DEBUG_REG47_BVALID_q_SIZE   1
+#define MH_DEBUG_REG47_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG47_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG47_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG47_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG47_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG47_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG47_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG47_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG47_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG47_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG47_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RVALID_q_MASK | \
+      MH_DEBUG_REG47_RREADY_q_MASK | \
+      MH_DEBUG_REG47_RLAST_q_MASK | \
+      MH_DEBUG_REG47_BVALID_q_MASK | \
+      MH_DEBUG_REG47_BREADY_q_MASK)
+
+#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG48_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG48_RDC_RID_SIZE    3
+#define MH_DEBUG_REG48_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG48_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG48_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG48_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG48_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG48_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG48_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG48_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_RID_MASK | \
+      MH_DEBUG_REG48_RDC_RLAST_MASK | \
+      MH_DEBUG_REG48_RDC_RRESP_MASK | \
+      MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG49(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24
+#define MH_DEBUG_REG50_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG50_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG50_ARB_WE_SIZE     1
+#define MH_DEBUG_REG50_MMU_RTR_SIZE    1
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG50_ARB_ID_q_SHIFT  24
+#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27
+#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28
+#define MH_DEBUG_REG50_ARB_WE_SHIFT    30
+#define MH_DEBUG_REG50_MMU_RTR_SHIFT   31
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff
+#define MH_DEBUG_REG50_ARB_ID_q_MASK   0x07000000
+#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000
+#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000
+#define MH_DEBUG_REG50_ARB_WE_MASK     0x40000000
+#define MH_DEBUG_REG50_MMU_RTR_MASK    0x80000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \
+      MH_DEBUG_REG50_ARB_ID_q_MASK | \
+      MH_DEBUG_REG50_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG50_client_behavior_q_MASK | \
+      MH_DEBUG_REG50_ARB_WE_MASK | \
+      MH_DEBUG_REG50_MMU_RTR_MASK)
+
+#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \
+     ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT))
+
+#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_stage1_valid_SIZE 1
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG51_tag_match_q_SIZE 1
+#define MH_DEBUG_REG51_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG51_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG51_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG51_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG51_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG51_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG51_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG51_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG51_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_stage1_valid_MASK | \
+      MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG51_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG51_tag_match_q_MASK | \
+      MH_DEBUG_REG51_tag_miss_q_MASK | \
+      MH_DEBUG_REG51_va_in_range_q_MASK | \
+      MH_DEBUG_REG51_MMU_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG52_MMU_WE_SIZE     1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG52_stage1_valid_SIZE 1
+#define MH_DEBUG_REG52_stage2_valid_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG52_tag_match_q_SIZE 1
+#define MH_DEBUG_REG52_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG52_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG52_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG52_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG52_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG52_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG52_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_ARQ_RTR_MASK | \
+      MH_DEBUG_REG52_MMU_WE_MASK | \
+      MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG52_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG52_stage1_valid_MASK | \
+      MH_DEBUG_REG52_stage2_valid_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK | \
+      MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG52_tag_match_q_MASK | \
+      MH_DEBUG_REG52_tag_miss_q_MASK | \
+      MH_DEBUG_REG52_va_in_range_q_MASK | \
+      MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG52_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG53_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG53_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG53_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG53_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG53_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_TAG0_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG53_TAG1_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG54_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG54_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG54_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG54_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG54_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_TAG2_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG54_TAG3_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG55_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG4_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG5_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG56_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG6_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG7_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG57_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG8_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG9_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG58_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG10_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG11_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG59_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG12_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG13_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG60_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG14_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG15_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG61(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG62(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 8;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 8;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 5;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int                                : 5;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fpos_SIZE           1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fpos_SHIFT          4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fpos_MASK           0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fpos_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fpos << SC_DEBUG_7_fpos_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fpos(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fpos_SIZE           1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fpos_SHIFT          20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fpos_MASK           0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fpos_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fpos << SC_DEBUG_8_fpos_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fpos(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int                                : 3;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK)
+
+#define VGT_BIN_SIZE(num_words) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 8;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int                                : 8;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 28;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 28;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_RESERVED9_SIZE   1
+#define RB_BC_CONTROL_RESERVED10_SIZE  1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_RESERVED9_SHIFT  30
+#define RB_BC_CONTROL_RESERVED10_SHIFT 31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_RESERVED9_MASK   0x40000000
+#define RB_BC_CONTROL_RESERVED10_MASK  0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_RESERVED9_MASK | \
+      RB_BC_CONTROL_RESERVED10_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \
+      (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
new file mode 100644
index 000000000000..1feebebda054
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
@@ -0,0 +1,540 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
new file mode 100644
index 000000000000..15cfbebf2907
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
@@ -0,0 +1,1897 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
new file mode 100644
index 000000000000..87a454a1e38a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
new file mode 100644
index 000000000000..d04379887b78
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
@@ -0,0 +1,3405 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(CLAMPED_FACENESS, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(FACENESS_RESET, int)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(PAw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(RESERVED1, bool)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(RESERVED3, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(RESERVED5, bool)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(RESERVED6, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
new file mode 100644
index 000000000000..0e32e421d0a3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
new file mode 100644
index 000000000000..52ced9af774c
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
@@ -0,0 +1,5908 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK          0x10000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS               0x10000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
new file mode 100644
index 000000000000..83be5f82ed8c
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
new file mode 100644
index 000000000000..17379dcfa0e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
new file mode 100644
index 000000000000..bcc28f133b08
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
@@ -0,0 +1,14280 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int                                 : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
new file mode 100644
index 000000000000..69677996b133
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
@@ -0,0 +1,4184 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT        0x0000001c
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
new file mode 100644
index 000000000000..78d4924ef79d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
@@ -0,0 +1,52583 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  rbbm_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  mh_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  pa_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  vgt_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sq_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sx_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tp_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  tc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  sc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*****************************************************************************************************************
+ *
+ *  bc_reg.h
+ *
+ *  Register Spec Release:  Block Spec 1.0
+ *
+ *   (c) 2000 ATI Technologies Inc.  (unpublished)
+ *
+ *   All rights reserved.  This notice is intended as a precaution against
+ *   inadvertent publication and does not imply publication or any waiver
+ *   of confidentiality.  The year included in the foregoing notice is the
+ *   year of creation of the work.
+ *
+ *****************************************************************************************************************/
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
new file mode 100644
index 000000000000..6968abb48bd7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/os/include/os_types.h b/drivers/mxc/amd-gpu/os/include/os_types.h
new file mode 100644
index 000000000000..e7ecd90f8952
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/include/os_types.h
@@ -0,0 +1,138 @@
+ /* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __OSTYPES_H
+#define __OSTYPES_H
+
+//////////////////////////////////////////////////////////////////////////////
+//   status
+//////////////////////////////////////////////////////////////////////////////
+#define OS_SUCCESS                       0
+#define OS_FAILURE                      -1
+#define OS_FAILURE_SYSTEMERROR          -2
+#define OS_FAILURE_DEVICEERROR          -3
+#define OS_FAILURE_OUTOFMEM             -4
+#define OS_FAILURE_BADPARAM             -5
+#define OS_FAILURE_NOTSUPPORTED         -6
+#define OS_FAILURE_NOMOREAVAILABLE      -7
+#define OS_FAILURE_NOTINITIALIZED       -8
+#define OS_FAILURE_ALREADYINITIALIZED   -9
+#define OS_FAILURE_TIMEOUT              -10
+
+
+//////////////////////////////////////////////////////////////////////////////
+// inline
+//////////////////////////////////////////////////////////////////////////////
+#ifndef OSINLINE
+#ifdef _LINUX
+#define OSINLINE    static __inline
+#else
+#define OSINLINE    __inline
+#endif
+#endif // OSINLINE
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  values
+//////////////////////////////////////////////////////////////////////////////
+#define OS_INFINITE             0xFFFFFFFF
+#define OS_TLS_OUTOFINDEXES     0xFFFFFFFF
+#define OS_TRUE                         1
+#define OS_FALSE                        0
+
+#ifndef NULL
+#define NULL                    (void *)0x0
+#endif  // !NULL
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+
+//
+// oshandle_t
+//
+typedef void *          oshandle_t;
+#define OS_HANDLE_NULL  (oshandle_t)0x0
+
+//
+// os_sysinfo_t
+//
+typedef struct _os_sysinfo_t {
+    int     cpu_mhz;
+    int     cpu_type;
+    int     cpu_version;
+    int     os_type;
+    int     os_version;
+    int     sysmem_size;
+    int     page_size;
+    int     max_path;
+    int     tls_slots;
+    int     endianness;     // 0 == little_endian, 1 == big_endian
+} os_sysinfo_t;
+
+
+//
+// os_stats_t
+//
+#ifdef _LINUX
+typedef long long __int64;
+typedef unsigned long long __uint64;
+#else
+typedef unsigned __int64 __uint64;
+#endif
+
+typedef struct _os_stats_t {
+    __int64     heap_allocs;
+    __int64     heap_frees;
+    __int64     heap_alloc_bytes;
+    __int64     shared_heap_allocs;
+    __int64     shared_heap_frees;
+    __int64     shared_heap_alloc_bytes;
+    __int64     objects_alloc;
+    __int64     objects_free;
+} os_stats_t;
+
+
+typedef enum {
+    OS_PROTECTION_GLOBAL,   // inter process
+    OS_PROTECTION_LOCAL,    // process local
+    OS_PROTECTION_NONE,     // none
+} os_protection_t;
+
+typedef struct _os_cputimer_t {
+    int refcount;                   // Reference count
+    int enabled;                    // Counter is enabled
+    int size;                       // Number of counters
+    __int64  start_time;            // start time in cpu ticks
+    __int64  end_time;              // end time in cpu ticks
+    __int64  timer_frequency;       // cpu ticks per second
+    __int64  *counter_array;        // number of ticks for each counter
+} os_cputimer_t;
+
+#endif  // __OSTYPES_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
new file mode 100644
index 000000000000..a02c396c22a9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
@@ -0,0 +1,813 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __KOSAPI_H
+#define __KOSAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "os_types.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   entrypoint abstraction
+//////////////////////////////////////////////////////////////////////////////
+
+
+#if defined(_WIN32) && !defined (_WIN32_WCE) && !defined(__SYMBIAN32__)
+#define KOS_DLLEXPORT   __declspec(dllexport)
+#define KOS_DLLIMPORT   __declspec(dllimport)
+#elif defined(_WIN32) && defined (_WIN32_WCE)
+#define KOS_DLLEXPORT   __declspec(dllexport)   
+#define KOS_DLLIMPORT
+#else
+#define KOS_DLLEXPORT   extern
+#define KOS_DLLIMPORT   
+#endif // _WIN32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   KOS lib entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KOSLIB_EXPORTS
+#define KOS_API         KOS_DLLEXPORT
+#else
+#define KOS_API         KOS_DLLIMPORT
+#endif // __KOSLIB_EXPORTS
+
+//////////////////////////////////////////////////////////////////////////////
+//                             assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void                    kos_assert_hook(const char* file, int line, int expression);
+
+#if defined(DEBUG) || defined(DBG) || defined (_DBG) || defined (_DEBUG)
+
+#if defined(_WIN32) && !defined(__SYMBIAN32__) || defined(_WIN32_WCE)
+#include <assert.h>
+#define KOS_ASSERT(expression)  assert(expression)
+#elif defined(_BREW)
+#include <assert.h>
+#define KOS_ASSERT(expression)  kos_assert_hook(__FILE__, __LINE__, expression)
+#elif defined(__SYMBIAN32__)
+//#include <assert.h>
+//#define   KOS_ASSERT(expression)  assert(expression)
+#define KOS_ASSERT(expression)  /**/
+#elif defined(__ARM__)
+#define KOS_ASSERT(expression)
+#elif defined(_LINUX)
+#define KOS_ASSERT(expression) //kos_assert_hook(__FILE__, __LINE__, (int)(expression))
+#endif
+
+#else
+
+#define KOS_ASSERT(expression)
+
+#endif // DEBUG || DBG || _DBG
+
+#if defined(_WIN32) && defined(_DEBUG) && !defined(_WIN32_WCE) && !defined(__SYMBIAN32__)
+#pragma warning ( push, 3 )
+#include <crtdbg.h>
+#pragma warning  (pop)
+#define KOS_MALLOC_DBG(size)    _malloc_dbg(size, _NORMAL_BLOCK, __FILE__, __LINE__)
+#else
+#define KOS_MALLOC_DBG(size)    kos_malloc(int size)
+#endif // _WIN32 _DEBUG
+
+#define kos_assert(expression)  KOS_ASSERT(expression)
+#define kos_malloc_dbg(size)    KOS_MALLOC_DBG(size)
+
+#ifdef UNDER_CE
+#define KOS_PAGE_SIZE 0x1000
+#endif
+
+typedef enum mutexIndex mutexIndex_t;
+//////////////////////////////////////////////////////////////////////////////
+//  Interprocess shared memory initialization 
+//////////////////////////////////////////////////////////////////////////////
+// TODO: still valid?
+KOS_API int             kos_sharedmem_create(unsigned int map_addr, unsigned int size);
+KOS_API int             kos_sharedmem_destroy(void);
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process. Clears the reserved memory.
+ *
+ *
+ * \param   int num     Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing memory for a kernel side process.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* memblock  Pointer to the old memory block.
+ * \param   int size        Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_realloc(void* memblock, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved memory block from the kernel side process.
+ *
+ *
+ * \param   void* memblock  Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_free(void* memblock);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable automatic memory leak checking performed at program exit.
+ *
+ *
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_enable_memoryleakcheck(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes. Clears the reserved memory.
+ *
+ *
+ * \param   int num Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing user/kernel shared memory block.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* ptr   Pointer to the old memory block.
+ * \param   int size    Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_shared_realloc(void* ptr, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved shared memory block.
+ *
+ *
+ * \param   void* ptr   Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/
+ KOS_API void           kos_shared_free(void* ptr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Copies the values of num bytes from the location pointed by src
+ *          directly to the memory block pointed by dst.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Amount of bytes to copy.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memcpy(void* dst, const void* src, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Fills the destination memory block with the given value.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   int value   Value to be written to each destination address.
+ * \param   void* count Number of bytes to be set to the value.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memset(void* dst, int value, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two memory blocks.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Number of bytes to compare.
+ * \return  Zero if identical, >0 if first nonmatching byte is greater in dst.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_memcmp(void* dst, void* src, int count);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocates a physically contiguous memory block.
+ *
+ *
+ * \param   void** virt_addr    Pointer where to store the virtual address of the reserved block.
+ * \param   void** phys_addr    Pointer where to store the physical address of the reserved block.
+ * \param   int pages           Number of pages to reserve (default page size = 4096 bytes).
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_alloc_physical(void** virt_addr, void** phys_addr, int pages);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a physically contiguous allocated memory block.
+ *
+ *
+ * \param   void* virt_addr     Virtual address of the memory block.
+ * \param   int pages           Number of pages.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_free_physical(void* virt_addr, int pages);
+
+KOS_API void            kos_memoryfence(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination memory.
+ * \param   void* strsource     Pointer to the source string.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcpy(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy with given length.
+ *
+ *
+ * \param   void* destination   Pointer to destination memory.
+ * \param   void* source        Pointer to the source string.
+ * \param   int length          Amount of bytes to copy.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strncpy(char* destination, const char* source, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Append source string to destination string.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination string.
+ * \param   void* strsource         Pointer to the source string.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcat(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compare two strings.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strcmp(const char* string1, const char* string2);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two strings of given length.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strncmp(const char* string1, const char* string2, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Calculates the length of a string..
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Lenght of the string in bytes.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strlen(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert an numeric ascii string to integer value.
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_atoi(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert string to unsigned long integer.
+ *
+ *
+ * \param   void* nptr      Pointer to the string.
+ * \param   char** endptr   If not null, will be set to point to the next character after the number.
+ * \param   int base        Base defining the type of the numeric string.
+ * \return  Unsigned integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_strtoul(const char* nptr, char** endptr, int base);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a mutex instance.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_create(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get a handle to an already existing mutex.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_open(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_free(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Lock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lock(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex, if already locked returns immediately.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_locktry(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex by waiting for its release. Returns without locking if the
+ * mutex is already locked and cannot be acquired within the given period.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \param   int millisecondstowait  Time to wait for the mutex to be available.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lockwait(oshandle_t mutexhandle, int millisecondstowait);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unlock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_unlock(oshandle_t mutexhandle);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Increments (increases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be incremented.
+ * \return  Returns the new incremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_incr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be decremented.
+ * \return  Returns the new decremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_decr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic replacement of a value.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \return  Returns the old value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchg(int* ptr, int value);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform an atomic compare-and-exchange operation on the specified values. Compares the two specified 32-bit values and exchanges
+* with another 32-bit value based on the outcome of the comparison.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \param   int compvalue Value to be compared with.
+ * \return  Returns the initial value of the first given parameter.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_compxchg(int* ptr, int value, int compvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic addition of two 32-bit values.
+ *
+ *
+ * \param   int* ptr Pointer to the target value.
+ * \param   int value Value to be added to the target.
+ * \return  Returns the initial value of the target.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchgadd(int* ptr, int value);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create an event semaphore.
+ *
+ *
+ * \param   int a_manualReset Selection for performing reset manually (or by the system).
+ * \return  Returns an handle to the created semaphore.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_event_create(int a_manualReset);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_destroy(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Signal an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_signal(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Reset an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_reset(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Wait for an event semaphore to be freed and acquire it.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \param   int a_milliSeconds Time to wait.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_wait(oshandle_t a_event, int a_milliSeconds);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  interrupt handler API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_enable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Disable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_disable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Set the callback function for an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_setcallback(int interrupt, void* handler);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Remove a callback function from an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_clearcallback(int interrupt, void* handler);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  thread and process API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate an entry from the thread local storage table.
+ *
+ *
+ * \return  Index of the reserved entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_tls_alloc(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free an entry from the thread local storage table.
+ *
+ *
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_free(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Read the value of an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \return  Returns the value of the entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_tls_read(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Write a value to an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \param   void* tlsvalue          Value to be written.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_write(unsigned int tlsindex, void* tlsvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Put the thread to sleep for the given time period.
+ *
+ *
+ * \param   unsigned int milliseconds   Time in milliseconds.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_sleep(unsigned int milliseconds);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current process.
+ *
+ *
+ * \return  Returns the process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_process_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current caller process.
+ *
+ *
+ * \return  Returns the caller process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_callerprocess_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current thread.
+ *
+ *
+ * \return  Returns the thread id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_thread_getid(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a new thread.
+ *
+ *
+ * \param   oshandle_t a_function Handle to the function to be executed in the thread.
+ * \param   unsigned int* a_threadId Pointer to a value where to store the ID of the new thread.
+ * \return  Returns an handle to the created thread.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_thread_create(oshandle_t a_function, unsigned int* a_threadId);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy the given thread.
+ *
+ *
+ * \param   oshandle_t a_task Handle to the thread to be destroyed.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_thread_destroy( oshandle_t a_task );
+
+//////////////////////////////////////////////////////////////////////////////
+//  timing API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the current time as a timestamp.
+ *
+ *
+ * \return  Returns the timestamp.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_timestamp(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Map the given library (not required an all OS'es).
+ *
+ *
+ * \param   char* libraryname   The name string of the lib.
+ * \return  Returns a handle for the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_lib_map(char* libraryname);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unmap the given library.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns an error code incase of an error.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_lib_unmap(oshandle_t libhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the address of a lib.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns a pointer to the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_lib_getaddr(oshandle_t libhandle, char* procname);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get device system info.
+ *
+ * \param   os_sysinfo_t* sysinfo   Pointer to the destination sysinfo structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_sysinfo(os_sysinfo_t* sysinfo);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get system status info.
+ *
+ * \param   os_stats_t* stats   Pointer to the destination stats structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_stats(os_stats_t* stats);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_start(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_end(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_start_ex( mutexIndex_t a_index );
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end_ex( mutexIndex_t a_index );
+
+//////////////////////////////////////////////////////////////////////////////
+//  file API
+//////////////////////////////////////////////////////////////////////////////
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Opens a file
+ *
+ * \param   const char* filename    Name of the file to open.
+ * \param   const char* mode        Mode used for file opening. See fopen.
+ * \return  Returns file handle or NULL if error.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_fopen(const char* filename, const char* mode);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Writes to a file
+ *
+ * \param   oshandle_t file     Handle of the file to write to.
+ * \param   const char* format  Format string. See fprintf.
+ * \return  Returns the number of bytes written
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fprintf(oshandle_t file, const char* format, ...);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Closes a file
+ *
+ * \param   oshandle_t file     Handle of the file to close.
+ * \return  Returns zero if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fclose(oshandle_t file);
+
+#ifdef  __SYMBIAN32__
+KOS_API void kos_create_dfc(void);
+KOS_API void kos_signal_dfc(void);
+KOS_API void kos_enter_critical_section();
+KOS_API void kos_leave_critical_section();
+#endif  // __SYMBIAN32__
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif  // __KOSAPI_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
new file mode 100644
index 000000000000..4ead84ffe0dc
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
@@ -0,0 +1,661 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/limits.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/mutex.h>
+#include <asm/atomic.h>
+#include <asm/current.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include "kos_libapi.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+//#define KOS_STATS_ENABLE
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define KOS_MALLOC(s)               kmalloc(s, GFP_KERNEL)
+#define KOS_CALLOC(num, size)       kcalloc(num, size, GFP_KERNEL)
+#define KOS_REALLOC(p, s)           krealloc(p, s, GFP_KERNEL)
+#define KOS_FREE(p)                 kfree(p); p = 0
+#define KOS_DBGFLAGS_SET(flag)
+
+//////////////////////////////////////////////////////////////////////////////
+// stats
+//////////////////////////////////////////////////////////////////////////////
+#ifdef KOS_STATS_ENABLE
+os_stats_t kos_stats = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KOS_STATS(x) x
+#else
+#define KOS_STATS(x)
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void
+kos_assert_hook(const char* file, int line, int expression)
+{
+    if (expression)
+    {
+        return;
+    }
+    else
+    {
+        printk(KERN_ERR "Assertion failed at %s:%d!\n", file, line);
+        //BUG();
+    }
+
+    // put breakpoint here
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_malloc(int size)
+{
+    void* ptr = KOS_MALLOC(size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_calloc(int num, int size)
+{
+    void* ptr = KOS_CALLOC(num, size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += (size * num));
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_realloc(void* ptr, int size)
+{
+    void* newptr;
+
+    KOS_ASSERT(ptr);
+    newptr = KOS_REALLOC(ptr, size);
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_free(void* ptr)
+{
+    KOS_STATS(kos_stats.heap_frees++);
+
+    KOS_FREE(ptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_shared_malloc(int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared alloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_calloc(int num, int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared calloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += (size * num));
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_realloc(void* ptr, int size)
+{
+    void* newptr;
+    (void) ptr;      // unreferenced formal parameter
+    (void) size;     // unreferenced formal parameter
+
+    newptr = NULL; // shared realloc
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_shared_free(void* ptr)
+{
+    (void) ptr;      // unreferenced formal parameter
+    KOS_ASSERT(0);   // not implemented
+
+    KOS_STATS(kos_stats.shared_heap_frees++);
+
+    // shared free
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory access API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_memcpy(void* dst, const void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcpy(dst, src, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_memset(void* dst, int value, int count)
+{
+    KOS_ASSERT(dst);
+    return memset(dst, value, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_memcmp(void* dst, void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcmp(dst, src, count);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API int
+kos_alloc_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    *virt_addr = dma_alloc_coherent(NULL, pages*PAGE_SIZE, (dma_addr_t*)*phys_addr, GFP_DMA | GFP_KERNEL);
+    return *virt_addr ? OS_SUCCESS : OS_FAILURE;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_free_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_map_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) phys_addr;     // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_unmap_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_memoryfence(void)
+{
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_enable_memoryleakcheck(void)
+{
+    // perform automatic leak checking at program exit
+    KOS_DBGFLAGS_SET(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API char*
+kos_strcpy(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcpy(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strncpy(char* destination, const char* source, int length)
+{
+    KOS_ASSERT(destination);
+    KOS_ASSERT(source);
+    return strncpy(destination, source, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strcat(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcat(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strcmp(const char* string1, const char* string2)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strcmp(string1, string2);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strncmp(const char* string1, const char* string2, int length)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strncmp(string1, string2, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strlen(const char* string)
+{
+    KOS_ASSERT(string);
+    return strlen(string);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API oshandle_t
+kos_mutex_create(const char *name)
+{
+	struct mutex *mutex = KOS_MALLOC(sizeof(struct mutex));
+	if (!mutex)
+		return 0;
+	mutex_init(mutex);
+	return mutex;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API oshandle_t
+kos_mutex_open(const char *name)
+{
+	// not implemented
+	return 0;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_free(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_FREE(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_lock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (mutex_lock_interruptible(mutex) == -EINTR)
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_locktry(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (!mutex_trylock(mutex))
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_unlock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_ASSERT(mutex_is_locked(mutex));
+	mutex_unlock(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API unsigned int
+kos_process_getid(void)
+{
+	return current->tgid;
+}
+
+//----------------------------------------------------------------------------
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Creates new event semaphore
+ * \param           uint32 a_manualReset
+ *                  When this param is zero, system automatically resets the
+ *                  event state to nonsignaled after waiting thread has been
+ *                  released
+ * \return          oshandle_t
+*//* ------------------------------------------------------------------- */
+KOS_API oshandle_t
+kos_event_create(int a_manualReset)
+{
+    struct completion *comp = KOS_MALLOC(sizeof(struct completion));
+
+    KOS_ASSERT(comp);
+    if(!comp)
+    {
+        return (oshandle_t)NULL;
+    }
+
+    init_completion(comp);
+
+    return (oshandle_t)comp;
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Frees event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_destroy(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+//  KOS_ASSERT(completion_done(comp));
+
+    KOS_FREE(comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Signals event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_signal(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    complete_all(comp);     // perhaps complete_all?
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Resets event semaphore state to nonsignaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_reset(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    INIT_COMPLETION(*comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Waits event semaphore to be signaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_wait(oshandle_t a_event, int a_milliSeconds)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    if(a_milliSeconds == OS_INFINITE)
+    {
+        wait_for_completion_killable(comp);
+    }
+    else
+    {
+        // should interpret milliseconds really to jiffies?
+        if(!wait_for_completion_timeout(comp, msecs_to_jiffies(a_milliSeconds)))
+        {
+            return (OS_FAILURE);
+        }
+    }
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_sleep(unsigned int milliseconds)
+{
+    msleep(milliseconds);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kos_get_endianness(void)
+{
+    int  value;
+    char* ptr;
+
+    value = 0x01FFFF00;
+
+    ptr = (char*)&value;
+
+    KOS_ASSERT((*ptr == 0x00) || (*ptr == 0x01));
+
+    return (int)*ptr;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_get_sysinfo(os_sysinfo_t* sysinfo)
+{
+    KOS_ASSERT(sysinfo);
+    if (!sysinfo) return (OS_FAILURE);
+
+    sysinfo->cpu_mhz            = 0;
+    sysinfo->cpu_type           = 0;
+    sysinfo->cpu_version        = 0;
+    sysinfo->os_type            = 0;
+    sysinfo->os_version         = 0;
+    sysinfo->sysmem_size        = 0;
+    sysinfo->page_size          = 0x1000;
+    sysinfo->max_path           = PATH_MAX;
+//  sysinfo->tls_slots          = TLS_MINIMUM_AVAILABLE - 1;
+    sysinfo->endianness         = kos_get_endianness();
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef KOS_STATS_ENABLE
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    kos_memcpy(stats, &kos_stats, sizeof(os_stats_t));
+    return (OS_SUCCESS);
+}
+#else
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    return (OS_FAILURE);
+}
+#endif // KOS_STATS
+
+/*-------------------------------------------------------------------*//*!
+ * \brief Sync block API
+ *        Same mutex needed from different blocks of driver
+ *//*-------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+
+static struct mutex* syncblock_mutex = 0;
+
+KOS_API int kos_syncblock_start(void)
+{
+    int return_value;
+
+    if(!syncblock_mutex)
+    {
+        syncblock_mutex = kos_mutex_create("syncblock");
+    }
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_lock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end(void)
+{
+    int return_value;
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_unlock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+
+KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId)
+{
+	struct task_struct *task = kthread_run(a_function, 0, "kos_thread_%p", a_threadId);
+	*a_threadId = (unsigned int)task;
+	return (oshandle_t)task;
+}
+
+KOS_API void kos_thread_destroy( oshandle_t a_task )
+{
+	kthread_stop((struct task_struct *)a_task);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c
new file mode 100644
index 000000000000..45632d8f8688
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c
@@ -0,0 +1,570 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#include "gsl_hal.h"
+#include "gsl_halconfig.h"
+#include "gsl_linux_map.h"
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/vmalloc.h>
+
+#include <asm/atomic.h>
+#include <linux/uaccess.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+#define GSL_HAL_MEM1                        0
+#define GSL_HAL_MEM2                        1
+#define GSL_HAL_MEM3                        2
+
+/* #define GSL_HAL_DEBUG */
+
+typedef struct _gsl_hal_t {
+    gsl_memregion_t z160_regspace;
+    gsl_memregion_t z430_regspace;
+    gsl_memregion_t memchunk;
+    gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES];
+    unsigned int has_z160;
+    unsigned int has_z430;
+} gsl_hal_t;
+
+extern phys_addr_t gpu_2d_regbase;
+extern int gpu_2d_regsize;
+extern phys_addr_t gpu_3d_regbase;
+extern int gpu_3d_regsize;
+extern int gmem_size;
+extern phys_addr_t gpu_reserved_mem;
+extern int gpu_reserved_mem_size;
+
+
+KGSLHAL_API int
+kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    /* allocate physically contiguous memory */
+
+	int i;
+	void *va;
+
+	va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE);
+
+	if (!va)
+		return GSL_FAILURE_OUTOFMEM;
+
+	for (i = 0; i < numpages; i++) {
+		scattergatterlist[i] = page_to_phys(vmalloc_to_page(va));
+		va += PAGE_SIZE;
+	}
+
+	return GSL_SUCCESS;
+}
+
+/* --------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    /* free physical memory */
+
+	gsl_linux_map_free(virtaddr);
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_init(void)
+{
+    gsl_hal_t *hal;
+    unsigned long totalsize, mem1size;
+    unsigned int va, pa;
+
+    if (gsl_driver.hal) {
+	return GSL_FAILURE_ALREADYINITIALIZED;
+    }
+
+    gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t));
+
+    if (!gsl_driver.hal) {
+	return GSL_FAILURE_OUTOFMEM;
+    }
+
+    kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t));
+
+
+    /* overlay structure on hal memory */
+    hal = (gsl_hal_t *) gsl_driver.hal;
+
+    if (gpu_3d_regbase && gpu_3d_regsize) {
+	hal->has_z430 = 1;
+    } else {
+	hal->has_z430 = 0;
+    }
+
+    if (gpu_2d_regbase && gpu_2d_regsize) {
+	hal->has_z160 = 1;
+    } else {
+	hal->has_z160 = 0;
+    }
+
+    /* setup register space */
+    if (hal->has_z430) {
+	hal->z430_regspace.mmio_phys_base = gpu_3d_regbase;
+	hal->z430_regspace.sizebytes = gpu_3d_regsize;
+	hal->z430_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes);
+
+	if (hal->z430_regspace.mmio_virt_base == NULL) {
+	    return GSL_FAILURE_SYSTEMERROR;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->z430_regspace.sizebytes      = 0x%08x\n", __func__, hal->z430_regspace.sizebytes);
+#endif
+    }
+
+    if (hal->has_z160) {
+	hal->z160_regspace.mmio_phys_base = gpu_2d_regbase;
+	hal->z160_regspace.sizebytes = gpu_2d_regsize;
+	hal->z160_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes);
+
+	if (hal->z160_regspace.mmio_virt_base == NULL) {
+	    return GSL_FAILURE_SYSTEMERROR;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->z160_regspace.sizebytes      = 0x%08x\n", __func__, hal->z160_regspace.sizebytes);
+#endif
+    }
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+    mem1size = GSL_HAL_SHMEM_SIZE_EMEM1;
+    if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) {
+	pa = gpu_reserved_mem;
+	va = (unsigned int)ioremap(gpu_reserved_mem, totalsize);
+    } else {
+	va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+    }
+#else
+    if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) {
+	totalsize = gpu_reserved_mem_size;
+	pa = gpu_reserved_mem;
+	va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size);
+    } else {
+	gpu_reserved_mem = 0;
+	totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS;
+	va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+    }
+    mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS);
+#endif
+
+    if (va) {
+	kos_memset((void *)va, 0, totalsize);
+
+	hal->memchunk.mmio_virt_base = (void *)va;
+	hal->memchunk.mmio_phys_base = pa;
+	hal->memchunk.sizebytes      = totalsize;
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memchunk.sizebytes      = 0x%08x\n", __func__, hal->memchunk.sizebytes);
+#endif
+
+	hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
+	hal->memspace[GSL_HAL_MEM2].gpu_base       = pa;
+	hal->memspace[GSL_HAL_MEM2].sizebytes      = GSL_HAL_SHMEM_SIZE_EMEM2;
+	va += GSL_HAL_SHMEM_SIZE_EMEM2;
+	pa += GSL_HAL_SHMEM_SIZE_EMEM2;
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes);
+#endif
+
+	hal->memspace[GSL_HAL_MEM3].mmio_virt_base  = (void *) va;
+	hal->memspace[GSL_HAL_MEM3].gpu_base        = pa;
+	hal->memspace[GSL_HAL_MEM3].sizebytes       = GSL_HAL_SHMEM_SIZE_PHYS;
+	va += GSL_HAL_SHMEM_SIZE_PHYS;
+	pa += GSL_HAL_SHMEM_SIZE_PHYS;
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes);
+#endif
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	gsl_linux_map_init();
+	hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START;
+	hal->memspace[GSL_HAL_MEM1].gpu_base       = GSL_LINUX_MAP_RANGE_START;
+	hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#else
+	hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va;
+	hal->memspace[GSL_HAL_MEM1].gpu_base       = pa;
+	hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+#endif
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes);
+#endif
+    } else {
+	kgsl_hal_close();
+	return GSL_FAILURE_SYSTEMERROR;
+    }
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_close(void)
+{
+    gsl_hal_t  *hal;
+
+    if (gsl_driver.hal) {
+	/* overlay structure on hal memory */
+	hal = (gsl_hal_t *) gsl_driver.hal;
+
+	/* unmap registers */
+	if (hal->has_z430 && hal->z430_regspace.mmio_virt_base) {
+	    iounmap(hal->z430_regspace.mmio_virt_base);
+	}
+
+	if (hal->has_z160 && hal->z160_regspace.mmio_virt_base) {
+	    iounmap(hal->z160_regspace.mmio_virt_base);
+	}
+
+	/* free physical block */
+	if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) {
+	    iounmap(hal->memchunk.mmio_virt_base);
+	} else {
+	    dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base);
+	}
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	gsl_linux_map_destroy();
+#endif
+
+	/* release hal struct */
+	kos_memset(hal, 0, sizeof(gsl_hal_t));
+	kos_free(gsl_driver.hal);
+	gsl_driver.hal = NULL;
+    }
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config)
+{
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_shmemconfig_t));
+
+    if (hal) {
+	config->numapertures = GSL_SHMEM_MAX_APERTURES;
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	config->apertures[0].id        = GSL_APERTURE_MMU;
+#else
+	config->apertures[0].id        = GSL_APERTURE_EMEM;
+#endif
+	config->apertures[0].channel   = GSL_CHANNEL_1;
+	config->apertures[0].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base;
+	config->apertures[0].gpubase   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+	config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes;
+
+	config->apertures[1].id        = GSL_APERTURE_EMEM;
+	config->apertures[1].channel   = GSL_CHANNEL_2;
+	config->apertures[1].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base;
+	config->apertures[1].gpubase   = hal->memspace[GSL_HAL_MEM2].gpu_base;
+	config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes;
+
+	config->apertures[2].id        = GSL_APERTURE_PHYS;
+	config->apertures[2].channel   = GSL_CHANNEL_1;
+	config->apertures[2].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base;
+	config->apertures[2].gpubase   = hal->memspace[GSL_HAL_MEM3].gpu_base;
+	config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes;
+
+	status = GSL_SUCCESS;
+    }
+
+    return status;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config)
+{
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_devconfig_t));
+
+    if (hal) {
+	switch (device_id) {
+	case GSL_DEVICE_YAMATO:
+	{
+	    if (hal->has_z430) {
+		mh_mmu_config_u      mmu_config   = {0};
+
+		config->gmemspace.gpu_base        = 0;
+		config->gmemspace.mmio_virt_base  = 0;
+		config->gmemspace.mmio_phys_base  = 0;
+		if (gmem_size) {
+		    config->gmemspace.sizebytes = gmem_size;
+		} else {
+		    config->gmemspace.sizebytes = 0;
+		}
+
+		config->regspace.gpu_base         = 0;
+		config->regspace.mmio_virt_base   = (unsigned char *)hal->z430_regspace.mmio_virt_base;
+		config->regspace.mmio_phys_base   = (unsigned int) hal->z430_regspace.mmio_phys_base;
+		config->regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+
+		mmu_config.f.mmu_enable           = 1;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		mmu_config.f.split_mode_enable    = 0;
+		mmu_config.f.rb_w_clnt_behavior   = 1;
+		mmu_config.f.cp_w_clnt_behavior   = 1;
+		mmu_config.f.cp_r0_clnt_behavior  = 1;
+		mmu_config.f.cp_r1_clnt_behavior  = 1;
+		mmu_config.f.cp_r2_clnt_behavior  = 1;
+		mmu_config.f.cp_r3_clnt_behavior  = 1;
+		mmu_config.f.cp_r4_clnt_behavior  = 1;
+		mmu_config.f.vgt_r0_clnt_behavior = 1;
+		mmu_config.f.vgt_r1_clnt_behavior = 1;
+		mmu_config.f.tc_r_clnt_behavior   = 1;
+		mmu_config.f.pa_w_clnt_behavior   = 1;
+#endif /* GSL_MMU_TRANSLATION_ENABLED */
+
+		config->mmu_config                = mmu_config.val;
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		config->va_base                   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+		config->va_range                  = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+		config->va_base                   = 0x00000000;
+		config->va_range                  = 0x00000000;
+#endif /* GSL_MMU_TRANSLATION_ENABLED */
+
+		/* turn off memory protection unit by setting acceptable physical address range to include all pages */
+		config->mpu_base                  = 0x00000000; /* hal->memchunk.mmio_virt_base; */
+		config->mpu_range                 = 0xFFFFF000; /* hal->memchunk.sizebytes; */
+		status = GSL_SUCCESS;
+	    }
+	    break;
+	}
+
+	case GSL_DEVICE_G12:
+	{
+		mh_mmu_config_u      mmu_config   = {0};
+
+		config->regspace.gpu_base       = 0;
+		config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base;
+		config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base;
+		config->regspace.sizebytes      = GSL_HAL_SIZE_REG_G12;
+
+		mmu_config.f.mmu_enable           = 1;
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+		config->mmu_config              = 0x00555551;
+		config->va_base                 = hal->memspace[GSL_HAL_MEM1].gpu_base;
+		config->va_range                = hal->memspace[GSL_HAL_MEM1].sizebytes;
+#else
+		config->mmu_config              = mmu_config.val;
+		config->va_base                 = 0x00000000;
+		config->va_range                = 0x00000000;
+#endif /* GSL_MMU_TRANSLATION_ENABLED */
+
+		config->mpu_base                = 0x00000000; /* (unsigned int) hal->memchunk.mmio_virt_base; */
+		config->mpu_range               = 0xFFFFF000; /* hal->memchunk.sizebytes; */
+
+		status = GSL_SUCCESS;
+		break;
+	}
+
+	default:
+		break;
+	}
+    }
+
+    return status;
+}
+
+/*----------------------------------------------------------------------------
+ * kgsl_hal_getchipid
+ *
+ * The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE
+ *----------------------------------------------------------------------------
+ */
+KGSLHAL_API gsl_chipid_t
+kgsl_hal_getchipid(gsl_deviceid_t device_id)
+{
+    gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal;
+    gsl_device_t *device = &gsl_driver.device[device_id-1];
+    gsl_chipid_t chipid = 0;
+    unsigned int coreid, majorid, minorid, patchid, revid;
+
+    if (hal->has_z430 && (device_id == GSL_DEVICE_YAMATO)) {
+	device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid);
+	coreid &= 0xF;
+
+	device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid);
+	majorid = (majorid >> 4) & 0xF;
+
+	device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid);
+
+	minorid = ((revid >> 0) & 0xFF); /* this is a 16bit field, but extremely unlikely it would ever get this high */
+
+	patchid = ((revid >> 16) & 0xFF);
+
+	chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0));
+    }
+
+    return chipid;
+}
+
+/* --------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value)
+{
+	gsl_device_t *device = &gsl_driver.device[device_id-1];
+	struct clk *gpu_clk = NULL;
+	struct clk *garb_clk = NULL;
+	struct clk *emi_garb_clk = NULL;
+
+	/* unreferenced formal parameters */
+	(void) value;
+
+	switch (device_id) {
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		garb_clk = clk_get(0, "garb_clk");
+		emi_garb_clk = clk_get(0, "emi_garb_clk");
+		break;
+	default:
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (!gpu_clk) {
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	switch (state) {
+	case GSL_PWRFLAGS_CLK_ON:
+		break;
+	case GSL_PWRFLAGS_POWER_ON:
+		clk_enable(gpu_clk);
+		if (garb_clk) {
+			clk_enable(garb_clk);
+		}
+		if (emi_garb_clk) {
+			clk_enable(emi_garb_clk);
+		}
+		kgsl_device_autogate_init(&gsl_driver.device[device_id-1]);
+		break;
+	case GSL_PWRFLAGS_CLK_OFF:
+		break;
+	case GSL_PWRFLAGS_POWER_OFF:
+		if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) {
+			return GSL_FAILURE_DEVICEERROR;
+		}
+		kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]);
+		clk_disable(gpu_clk);
+		if (garb_clk) {
+			clk_disable(garb_clk);
+		}
+		if (emi_garb_clk) {
+			clk_disable(emi_garb_clk);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return GSL_SUCCESS;
+}
+
+KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable)
+{
+	struct clk *gpu_clk = NULL;
+	struct clk *garb_clk = NULL;
+	struct clk *emi_garb_clk = NULL;
+
+	switch (dev) {
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		garb_clk = clk_get(0, "garb_clk");
+		emi_garb_clk = clk_get(0, "emi_garb_clk");
+		break;
+	default:
+		printk(KERN_ERR "GPU device %d is invalid!\n", dev);
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (IS_ERR(gpu_clk)) {
+		printk(KERN_ERR "%s: GPU clock get failed!\n", __func__);
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (enable) {
+		clk_enable(gpu_clk);
+		if (garb_clk) {
+		    clk_enable(garb_clk);
+		}
+		if (emi_garb_clk) {
+		    clk_enable(emi_garb_clk);
+		}
+	} else {
+		clk_disable(gpu_clk);
+		if (garb_clk) {
+		    clk_disable(garb_clk);
+		}
+		if (emi_garb_clk) {
+		    clk_disable(emi_garb_clk);
+		}
+	}
+
+	return GSL_SUCCESS;
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
new file mode 100644
index 000000000000..65eadb1e79cf
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
@@ -0,0 +1,155 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HWACCESS_LINUX_H
+#define __GSL_HWACCESS_LINUX_H
+
+#ifdef _LINUX
+#include "gsl_linux_map.h"
+#endif
+
+#include <linux/io.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
+OSINLINE void
+kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+    {
+        gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace);
+    }
+    else
+#endif
+    {
+        mb();
+        dsb();
+        if (touserspace)
+        {
+            if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+    if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+    {
+        gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace);
+    }
+    else
+#endif
+    {
+        mb();
+        dsb();
+        if (fromuserspace)
+        {
+            if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	if(gpubase >= GSL_LINUX_MAP_RANGE_START && gpubase < GSL_LINUX_MAP_RANGE_END)
+		gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes);
+	else
+#endif
+    {
+        mb();
+        dsb();
+        kos_memset((void *)(gpubase + gpuoffset), value, sizebytes);
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int *data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    
+    mb();
+    dsb();
+    *data = __raw_readl(reg);
+    mb();
+    dsb();
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    mb();
+    dsb();
+    __raw_writel(data, reg);
+    mb();
+    dsb();
+}
+#endif  // __GSL_HWACCESS_WINCE_MX51_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
new file mode 100644
index 000000000000..6aaaa745a84d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
@@ -0,0 +1,963 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl_types.h"
+#include "gsl.h"
+#include "gsl_buildconfig.h"
+#include "gsl_halconfig.h"
+#include "gsl_ioctl.h"
+#include "gsl_kmod_cleanup.h"
+#include "gsl_linux_map.h"
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <asm/uaccess.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+
+static int gpu_2d_irq, gpu_3d_irq;
+
+phys_addr_t gpu_2d_regbase;
+int gpu_2d_regsize;
+phys_addr_t gpu_3d_regbase;
+int gpu_3d_regsize;
+int gmem_size;
+phys_addr_t gpu_reserved_mem;
+int gpu_reserved_mem_size;
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr);
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr);
+static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg);
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma);
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+static int gsl_kmod_open(struct inode *inode, struct file *fd);
+static int gsl_kmod_release(struct inode *inode, struct file *fd);
+static irqreturn_t z160_irq_handler(int irq, void *dev_id);
+static irqreturn_t z430_irq_handler(int irq, void *dev_id);
+
+static int gsl_kmod_major;
+static struct class *gsl_kmod_class;
+DEFINE_MUTEX(gsl_mutex);
+
+static const struct file_operations gsl_kmod_fops =
+{
+    .owner = THIS_MODULE,
+    .read = gsl_kmod_read,
+    .write = gsl_kmod_write,
+    .ioctl = gsl_kmod_ioctl,
+    .mmap = gsl_kmod_mmap,
+    .open = gsl_kmod_open,
+    .release = gsl_kmod_release
+};
+
+static struct vm_operations_struct gsl_kmod_vmops =
+{
+	.fault = gsl_kmod_fault,
+};
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg)
+{
+    int kgslStatus = GSL_FAILURE;
+
+    switch (cmd) {
+    case IOCTL_KGSL_DEVICE_START:
+        {
+            kgsl_device_start_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_start_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_start(param.device_id, param.flags);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_STOP:
+        {
+            kgsl_device_stop_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_stop_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_stop(param.device_id);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_IDLE:
+        {
+            kgsl_device_idle_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_idle_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_idle(param.device_id, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_GETPROPERTY:
+        {
+            kgsl_device_getproperty_t param;
+            void *tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_getproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kmalloc(param.sizebytes, GFP_KERNEL);
+            if (!tmp)
+            {
+                printk(KERN_ERR "%s:kmalloc error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_getproperty(param.device_id, param.type, tmp, param.sizebytes);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, tmp, param.sizebytes))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    kfree(tmp);
+                    break;
+                }
+            }
+            else
+            {
+                printk(KERN_ERR "%s: kgsl_device_getproperty error\n", __func__);
+            }
+            kfree(tmp);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_SETPROPERTY:
+        {
+            kgsl_device_setproperty_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_setproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_setproperty(param.device_id, param.type, param.value, param.sizebytes);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_device_setproperty error\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGREAD:
+        {
+            kgsl_device_regread_t param;
+            unsigned int tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regread_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regread(param.device_id, param.offsetwords, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, &tmp, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGWRITE:
+        {
+            kgsl_device_regwrite_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regwrite_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regwrite(param.device_id, param.offsetwords, param.value);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_WAITIRQ:
+        {
+            kgsl_device_waitirq_t param;
+            unsigned int count;
+
+            printk(KERN_ERR "IOCTL_KGSL_DEVICE_WAITIRQ obsoleted!\n");
+//          kgslStatus = -ENOTTY; break;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_waitirq_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_waitirq(param.device_id, param.intr_id, &count, param.timeout);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.count, &count, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS:
+        {
+            kgsl_cmdstream_issueibcmds_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_issueibcmds_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_issueibcmds(param.device_id, param.drawctxt_index, param.ibaddr, param.sizedwords, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP:
+        {
+            kgsl_cmdstream_readtimestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_readtimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_cmdstream_readtimestamp(param.device_id, param.type);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP:
+        {
+            int err;
+            kgsl_cmdstream_freememontimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_freememontimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, param.memdesc);
+            if(err)
+            {
+                /* tried to remove a block of memory that is not allocated! 
+                 * NOTE that -EINVAL is Linux kernel's error codes! 
+                 * the drivers error codes COULD mix up with kernel's. */
+                kgslStatus = -EINVAL;
+            }
+            else
+            {
+                kgslStatus = kgsl_cmdstream_freememontimestamp(param.device_id,
+                                                               param.memdesc,
+                                                               param.timestamp,
+                                                               param.type);
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP:
+        {
+            kgsl_cmdstream_waittimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_waittimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_waittimestamp(param.device_id, param.timestamp, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_CMDWINDOW_WRITE:
+        {
+            kgsl_cmdwindow_write_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdwindow_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdwindow_write(param.device_id, param.target, param.addr, param.data);
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_CREATE:
+        {
+            kgsl_context_create_t param;
+            unsigned int tmp;
+            int tmpStatus;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_create_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_create(param.device_id, param.type, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.drawctxt_id, &tmp, sizeof(unsigned int)))
+                {
+                    tmpStatus = kgsl_context_destroy(param.device_id, tmp);
+                    /* is asserting ok? Basicly we should return the error from copy_to_user
+                     * but will the user space interpret it correctly? Will the user space 
+                     * always check against GSL_SUCCESS  or GSL_FAILURE as they are not the only
+                     * return values.
+                     */
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_device_context_to_array(fd, param.device_id, tmp);
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_DESTROY:
+        {
+            kgsl_context_destroy_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_destroy_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_destroy(param.device_id, param.drawctxt_id);
+            del_device_context_from_array(fd, param.device_id, param.drawctxt_id);
+            break;
+        }
+    case IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW:
+        {
+            kgsl_drawctxt_bind_gmem_shadow_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_drawctxt_bind_gmem_shadow_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_drawctxt_bind_gmem_shadow(param.device_id, param.drawctxt_id, param.gmem_rect, param.shadow_x, param.shadow_y, param.shadow_buffer, param.buffer_id);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_ALLOC:
+        {
+            kgsl_sharedmem_alloc_t param;
+            gsl_memdesc_t tmp;
+            int tmpStatus;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_alloc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_alloc(param.device_id, param.flags, param.sizebytes, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    tmpStatus = kgsl_sharedmem_free(&tmp);
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_memblock_to_allocated_list(fd, &tmp);
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FREE:
+        {
+            kgsl_sharedmem_free_t param;
+            gsl_memdesc_t tmp;
+            int err;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_free_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&tmp, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, &tmp);
+            if(err)
+            {
+                printk(KERN_ERR "%s: tried to free memdesc that was not allocated!\n", __func__);
+                kgslStatus = err;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_free(&tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_READ:
+        {
+            kgsl_sharedmem_read_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_read_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_read(&memdesc, param.dst, param.offsetbytes, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_read failed\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_WRITE:
+        {
+            kgsl_sharedmem_write_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_write(&memdesc, param.offsetbytes, param.src, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_write failed\n", __func__);
+            }
+            
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_SET:
+        {
+            kgsl_sharedmem_set_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_set_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_set(&memdesc, param.offsetbytes, param.value, param.sizebytes);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK:
+        {
+            kgsl_sharedmem_largestfreeblock_t param;
+            unsigned int largestfreeblock;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_largestfreeblock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            largestfreeblock = kgsl_sharedmem_largestfreeblock(param.device_id, param.flags);
+            if (copy_to_user(param.largestfreeblock, &largestfreeblock, sizeof(unsigned int)))
+            {
+                printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_CACHEOPERATION:
+        {
+            kgsl_sharedmem_cacheoperation_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_cacheoperation_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_cacheoperation(&memdesc, param.offsetbytes, param.sizebytes, param.operation);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER:
+        {
+            kgsl_sharedmem_fromhostpointer_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_fromhostpointer_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_fromhostpointer(param.device_id, &memdesc, param.hostptr);
+            break;
+        }
+    case IOCTL_KGSL_ADD_TIMESTAMP:
+        {
+            kgsl_add_timestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_add_timestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_add_timestamp(param.device_id, &tmp);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    
+    case IOCTL_KGSL_DEVICE_CLOCK:
+        {
+            kgsl_device_clock_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_clock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_clock(param.device, param.enable);
+            break;
+        }
+    default:
+        kgslStatus = -ENOTTY;
+        break;
+    }
+
+    return kgslStatus;
+}
+
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma)
+{
+    int status = 0;
+    unsigned long start = vma->vm_start;
+    unsigned long pfn = vma->vm_pgoff;
+    unsigned long size = vma->vm_end - vma->vm_start;
+    unsigned long prot = pgprot_writecombine(vma->vm_page_prot);
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	unsigned long addr = vma->vm_pgoff << PAGE_SHIFT;
+	void *va;
+#endif
+
+#ifdef GSL_MMU_TRANSLATION_ENABLED
+	if (addr < GSL_LINUX_MAP_RANGE_END && addr >= GSL_LINUX_MAP_RANGE_START)
+	{
+		va = gsl_linux_map_find(addr);
+		while (size > 0)
+		{
+			if (remap_pfn_range(vma, start, vmalloc_to_pfn(va), PAGE_SIZE, prot))
+			{
+				return -EAGAIN;
+			}
+			start += PAGE_SIZE;
+			va += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+	}
+	else
+#endif
+	{
+		if (remap_pfn_range(vma, start, pfn, size, prot))
+		{
+			status = -EAGAIN;
+		}
+	}
+
+    vma->vm_ops = &gsl_kmod_vmops;
+
+    return status;
+}
+
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+    return VM_FAULT_SIGBUS;
+}
+
+static int gsl_kmod_open(struct inode *inode, struct file *fd)
+{
+    gsl_flags_t flags = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    if (kgsl_driver_entry(flags) != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_entry error\n", __func__);
+        err = -EIO;  // TODO: not sure why did it fail?
+    }
+    else
+    {
+        /* allocate per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)kzalloc(
+                                             sizeof(struct gsl_kmod_per_fd_data),
+                                             GFP_KERNEL);
+        if(datp)
+        {
+            init_created_contexts_array(datp->created_contexts_array[0]);
+            INIT_LIST_HEAD(&datp->allocated_blocks_head);
+
+            fd->private_data = (void *)datp;
+        }
+        else
+        {
+            err = -ENOMEM;
+        }
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static int gsl_kmod_release(struct inode *inode, struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    /* make sure contexts are destroyed */
+    del_all_devices_contexts(fd);
+
+    if (kgsl_driver_exit() != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_exit error\n", __func__);
+        err = -EIO; // TODO: find better error code
+    }
+    else
+    {
+        /* release per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+        del_all_memblocks_from_allocated_list(fd);
+        kfree(datp);
+        fd->private_data = 0;
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static struct class *gsl_kmod_class;
+
+static irqreturn_t z160_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr();
+    return IRQ_HANDLED;
+}
+
+static irqreturn_t z430_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr();
+    return IRQ_HANDLED;
+}
+
+static int gpu_probe(struct platform_device *pdev)
+{
+    int i;
+    struct resource *res;
+    struct device *dev;
+
+    for(i = 0; i < 2; i++){
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+        if (!res) {
+            if (i == 0) {
+                printk(KERN_ERR "gpu: unable to get gpu irq\n");
+                return -ENODEV;
+            } else {
+                break;
+            }
+        }
+        if(strcmp(res->name, "gpu_2d_irq") == 0){
+            gpu_2d_irq = res->start;
+        }else if(strcmp(res->name, "gpu_3d_irq") == 0){
+            gpu_3d_irq = res->start;
+        }
+    }
+
+    for(i = 0; i < 4; i++){
+        res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+        if (!res) {
+            gpu_2d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gpu_3d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gmem_size = 0;
+            gpu_reserved_mem = 0;
+            gpu_reserved_mem_size = 0;
+            break;
+        }else{
+            if(strcmp(res->name, "gpu_2d_registers") == 0){
+                gpu_2d_regbase = res->start;
+                gpu_2d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_3d_registers") == 0){
+                gpu_3d_regbase = res->start;
+                gpu_3d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_graphics_mem") == 0){
+                gmem_size = res->end - res->start + 1;
+             }else if(strcmp(res->name, "gpu_reserved_mem") == 0){
+                gpu_reserved_mem = res->start;
+                gpu_reserved_mem_size = res->end - res->start + 1;
+            }
+        }
+    }
+
+    if (kgsl_driver_init() != GSL_SUCCESS)
+    {
+        printk(KERN_ERR "%s: kgsl_driver_init error\n", __func__);
+        goto kgsl_driver_init_error;
+    }
+
+    if (gpu_3d_irq > 0)
+    {
+	if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) {
+	    printk(KERN_ERR "%s: request_irq error\n", __func__);
+	    gpu_3d_irq = 0;
+	    goto request_irq_error;
+	}
+    }
+
+    if (gpu_2d_irq > 0)
+    {
+	if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) {
+	    printk(KERN_ERR "2D Acceleration Enabled, OpenVG Disabled!\n");
+	    gpu_2d_irq = 0;
+	}
+    }
+
+    gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops);
+    gsl_kmod_vmops.fault = gsl_kmod_fault;
+
+    if (gsl_kmod_major <= 0)
+    {
+        pr_err("%s: register_chrdev error\n", __func__);
+        goto register_chrdev_error;
+    }
+
+    gsl_kmod_class = class_create(THIS_MODULE, "gsl_kmod");
+
+    if (IS_ERR(gsl_kmod_class))
+    {
+        pr_err("%s: class_create error\n", __func__);
+        goto class_create_error;
+    }
+
+    #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28))
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), "gsl_kmod");
+    #else
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), NULL,"gsl_kmod");
+    #endif
+
+    if (!IS_ERR(dev))
+    {
+    //    gsl_kmod_data.device = dev;
+        return 0;
+    }
+
+    pr_err("%s: device_create error\n", __func__);
+
+class_create_error:
+    class_destroy(gsl_kmod_class);
+
+register_chrdev_error:
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+
+request_irq_error:
+kgsl_driver_init_error:
+    kgsl_driver_close();
+    return 0;   // TODO: return proper error code
+}
+
+static int gpu_remove(struct platform_device *pdev)
+{
+    device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0));
+    class_destroy(gsl_kmod_class);
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+
+    if (gpu_3d_irq)
+    {
+        free_irq(gpu_3d_irq, NULL);
+    }
+
+    if (gpu_2d_irq)
+    {
+        free_irq(gpu_2d_irq, NULL);
+    }
+
+    kgsl_driver_close();
+    return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_OFF;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+
+static int gpu_resume(struct platform_device *pdev)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_ON;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+#else
+#define	gpu_suspend	NULL
+#define	gpu_resume	NULL
+#endif /* !CONFIG_PM */
+
+/*! Driver definition
+ */
+static struct platform_driver gpu_driver = {
+    .driver = {
+        .name = "mxc_gpu",
+        },
+    .probe = gpu_probe,
+    .remove = gpu_remove,
+    .suspend = gpu_suspend,
+    .resume = gpu_resume,
+};
+
+static int __init gsl_kmod_init(void)
+{
+     return platform_driver_register(&gpu_driver);
+}
+
+static void __exit gsl_kmod_exit(void)
+{
+     platform_driver_unregister(&gpu_driver);
+}
+
+module_init(gsl_kmod_init);
+module_exit(gsl_kmod_exit);
+MODULE_AUTHOR("Advanced Micro Devices");
+MODULE_DESCRIPTION("AMD graphics core driver for i.MX");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
new file mode 100644
index 000000000000..3685a5756baf
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
@@ -0,0 +1,269 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_kmod_cleanup.h"
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+
+/*
+ * Local helper functions to check and convert device/context id's (1 based)
+ * to index (0 based).
+ */
+static u32 device_id_to_device_index(gsl_deviceid_t device_id)
+{
+    KOS_ASSERT((GSL_DEVICE_ANY < device_id) && 
+               (device_id <= GSL_DEVICE_MAX));
+    return (u32)(device_id - 1);
+}
+
+/* 
+ * Local helper function to check and get pointer to per file descriptor data 
+ */
+static struct gsl_kmod_per_fd_data *get_fd_private_data(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp; 
+
+    KOS_ASSERT(fd);
+    datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+    KOS_ASSERT(datp);
+    return datp;
+}
+
+static s8 *find_first_entry_with(s8 *subarray, s8 context_id)
+{
+    s8 *entry = NULL;
+    int i;
+
+//printk(KERN_DEBUG "At %s, ctx_id = %d\n", __func__, context_id);
+
+    KOS_ASSERT(context_id >= EMPTY_ENTRY);    
+    KOS_ASSERT(context_id <= GSL_CONTEXT_MAX);  // TODO: check the bound.
+
+    for(i = 0; i < GSL_CONTEXT_MAX; i++)        // TODO: check the bound.
+    {
+        if(subarray[i] == (s8)context_id)
+        {
+            entry = &subarray[i];
+            break;
+        }
+    }
+
+    return entry;
+}
+
+
+/*
+ * Add a memdesc into a list of allocated memory blocks for this file 
+ * descriptor. The list is build in such a way that it implements FIFO (i.e.
+ * list). Traces of tiger, tiger_ri and VG11 CTs should be analysed to make
+ * informed choice.
+ *
+ * NOTE! gsl_memdesc_ts are COPIED so user space should NOT change them.
+ */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block)
+{
+    int err = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *lisp;
+    struct list_head *head;
+
+    KOS_ASSERT(allocated_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    /* allocate and put new entry in the list of allocated memory descriptors */
+    lisp = (struct gsl_kmod_alloc_list *)kzalloc(sizeof(struct gsl_kmod_alloc_list), GFP_KERNEL);
+    if(lisp)
+    {
+        INIT_LIST_HEAD(&lisp->node);
+
+        /* builds FIFO (list_add() would build LIFO) */
+        list_add_tail(&lisp->node, head);
+        memcpy(&lisp->allocated_block, allocated_block, sizeof(gsl_memdesc_t));
+        lisp->allocation_number = datp->maximum_number_of_blocks;
+//        printk(KERN_DEBUG "List entry #%u allocated\n", lisp->allocation_number);
+
+        datp->maximum_number_of_blocks++;
+        datp->number_of_allocated_blocks++;
+
+        err = 0;
+    }
+    else
+    {
+        printk(KERN_ERR "%s: Could not allocate new list element\n", __func__);
+        err = -ENOMEM;
+    }
+
+    return err;
+}
+
+/* Delete a previously allocated memdesc from a list of allocated memory blocks */
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+//    int is_different;
+
+    KOS_ASSERT(freed_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    KOS_ASSERT(datp->number_of_allocated_blocks > 0);
+
+    if(!list_empty(head))
+    {
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            if(cursor->allocated_block.gpuaddr == freed_block->gpuaddr)
+            {
+//                is_different = memcmp(&cursor->allocated_block, freed_block, sizeof(gsl_memdesc_t));
+//                KOS_ASSERT(!is_different);
+
+                list_del(&cursor->node);
+//                printk(KERN_DEBUG "List entry #%u freed\n", cursor->allocation_number);
+                kfree(cursor);
+                datp->number_of_allocated_blocks--;
+                return 0;
+            }
+        }
+    }
+    return -EINVAL; // tried to free entry not existing or from empty list.
+}
+
+/* Delete all previously allocated memdescs from a list */
+int del_all_memblocks_from_allocated_list(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    if(!list_empty(head))
+    {
+        printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n");
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr);
+            kgsl_sharedmem_free(&cursor->allocated_block);
+            list_del(&cursor->node);
+            kfree(cursor);
+        }
+    }
+
+    KOS_ASSERT(list_empty(head));
+    datp->number_of_allocated_blocks = 0;
+
+    return 0;
+}
+
+void init_created_contexts_array(s8 *array)
+{
+    memset((void*)array, EMPTY_ENTRY, GSL_DEVICE_MAX * GSL_CONTEXT_MAX);
+}
+
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    s8 *entry;
+    s8 *subarray;
+    u32 device_index = device_id_to_device_index(device_id);
+
+    datp = get_fd_private_data(fd);
+
+    subarray = datp->created_contexts_array[device_index];
+    entry = find_first_entry_with(subarray, EMPTY_ENTRY);
+
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    KOS_ASSERT(context_id < 127);
+    *entry = (s8)context_id;
+}
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    u32 device_index = device_id_to_device_index(device_id);
+    s8 *entry;
+    s8 *subarray;
+
+    datp = get_fd_private_data(fd);
+
+    KOS_ASSERT(context_id < 127);
+    subarray = &(datp->created_contexts_array[device_index][0]);
+    entry = find_first_entry_with(subarray, context_id);
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    *entry = EMPTY_ENTRY;
+}
+
+void del_all_devices_contexts(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    gsl_deviceid_t id;
+    u32 device_index;
+    u32 ctx_array_index;
+    s8 ctx;
+    int err;
+    
+    datp = get_fd_private_data(fd);
+
+    /* device_id is 1 based */
+    for(id = GSL_DEVICE_ANY + 1; id <= GSL_DEVICE_MAX; id++)
+    {
+        device_index = device_id_to_device_index(id);
+        for(ctx_array_index = 0; ctx_array_index < GSL_CONTEXT_MAX; ctx_array_index++)
+        {
+            ctx = datp->created_contexts_array[device_index][ctx_array_index];
+            if(ctx != EMPTY_ENTRY)
+            {
+                err = kgsl_context_destroy(id, ctx);
+                if(err != GSL_SUCCESS)
+                {
+                    printk(KERN_ERR "%s: could not destroy context %d on device id = %u\n", __func__, ctx, id);
+                }
+                else
+                {
+                    printk(KERN_DEBUG "%s: Destroyed context %d on device id = %u\n", __func__, ctx, id);
+                }
+            }
+        }
+    }
+}
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
new file mode 100644
index 000000000000..475ee3be2e50
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
@@ -0,0 +1,90 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KMOD_CLEANUP_H
+#define __GSL_KMOD_CLEANUP_H
+#include "gsl_types.h"
+
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+
+#if (GSL_CONTEXT_MAX > 127)
+    #error created_contexts_array supports context numbers only 127 or less.
+#endif
+
+static const s8 EMPTY_ENTRY = -1;
+
+/* A structure to make list of allocated memory blocks. List per fd. */
+/* should probably be allocated from slab cache to minimise fragmentation */
+struct gsl_kmod_alloc_list
+{
+    struct list_head node;
+    gsl_memdesc_t allocated_block;
+    u32 allocation_number;
+};
+
+/* A structure to hold abovementioned list of blocks. Contain per fd data. */
+struct gsl_kmod_per_fd_data
+{
+    struct list_head allocated_blocks_head; // list head
+    u32 maximum_number_of_blocks;
+    u32 number_of_allocated_blocks;
+    s8 created_contexts_array[GSL_DEVICE_MAX][GSL_CONTEXT_MAX];
+};
+
+
+/* 
+ * prototypes 
+ */
+
+/* allocated memory block tracking */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block);
+
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block);
+
+int del_all_memblocks_from_allocated_list(struct file *fd);
+
+/* created contexts tracking */
+void init_created_contexts_array(s8 *array);
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id);
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id);
+
+void del_all_devices_contexts(struct file *fd);
+
+#endif  // __GSL_KMOD_CLEANUP_H
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
new file mode 100644
index 000000000000..7fee7b814411
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
@@ -0,0 +1,221 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+
+#include "gsl_linux_map.h"
+
+struct gsl_linux_map
+{
+	struct list_head list;
+	unsigned int gpu_addr;
+	void *kernel_virtual_addr;
+	unsigned int size;
+};
+
+static LIST_HEAD(gsl_linux_map_list);
+static DEFINE_MUTEX(gsl_linux_map_mutex);
+
+int gsl_linux_map_init()
+{
+	mutex_lock(&gsl_linux_map_mutex);
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+	mutex_unlock(&gsl_linux_map_mutex);
+
+	return 0;
+}
+
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+	void *va;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel));
+	if(va == NULL){
+		mutex_unlock(&gsl_linux_map_mutex);
+		return NULL;
+	}
+
+	map = (struct gsl_linux_map *)kmalloc(sizeof(*map), GFP_KERNEL);
+	map->gpu_addr = gpu_addr;
+	map->kernel_virtual_addr = va;
+	map->size = size;
+
+	INIT_LIST_HEAD(&map->list);
+	list_add_tail(&map->list, &gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return va;
+}
+
+void gsl_linux_map_free(unsigned int gpu_addr)
+{
+	int found = 0;
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			found = 1;
+			break;
+		}
+	}
+
+	if(found){
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+}
+
+void *gsl_linux_map_find(unsigned int gpu_addr)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *src = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (touserspace)
+                        {
+                            return (void *)copy_to_user(dst, map->kernel_virtual_addr + gpuoffset - map->gpu_addr, sizebytes);
+                        }
+                        else
+                        {
+	                    return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *dst = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (fromuserspace)
+                        {
+                            return (void *)copy_from_user(map->kernel_virtual_addr + gpuoffset - map->gpu_addr, src, sizebytes);
+                        }
+                        else
+                        {
+                            return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *ptr = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+			return memset(ptr, value, sizebytes);
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+int gsl_linux_map_destroy()
+{
+	struct gsl_linux_map * map;
+	struct list_head *p, *tmp;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each_safe(p, tmp, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return 0;
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
new file mode 100644
index 000000000000..0469d2b912be
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LINUX_MAP_H__
+#define __GSL_LINUX_MAP_H__
+
+#include "gsl_halconfig.h"
+
+#define GSL_LINUX_MAP_RANGE_START (1024*1024)
+#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1)
+
+int gsl_linux_map_init(void);
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size);
+void gsl_linux_map_free(unsigned int gpu_addr);
+void *gsl_linux_map_find(unsigned int gpu_addr);
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace);
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace);
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes);
+int gsl_linux_map_destroy(void);
+
+#endif
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
new file mode 100644
index 000000000000..a356f334b187
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <gsl.h>
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+typedef struct _gsl_autogate_t {
+    struct timer_list timer;	
+    spinlock_t lock;
+    int active;
+    int timeout;
+    gsl_device_t *dev;
+} gsl_autogate_t;
+
+
+#define KGSL_DEVICE_IDLE_TIMEOUT 5000	/* unit ms */
+
+int kgsl_device_active(gsl_device_t *dev)
+{
+	unsigned long flags;
+	gsl_autogate_t *autogate = dev->autogate;
+	if (!autogate) {
+		printk(KERN_ERR "%s: autogate has exited!\n", __func__);
+		return 0;
+	}
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active);
+
+	spin_lock_irqsave(&autogate->lock, flags);
+	if (!autogate->active)
+		kgsl_clock(autogate->dev->id, 1);
+	autogate->active = 1;
+	mod_timer(&autogate->timer, jiffies + msecs_to_jiffies(autogate->timeout));
+	spin_unlock_irqrestore(&autogate->lock, flags);
+	return 0;
+}
+
+static void kgsl_device_inactive(unsigned long data)
+{
+	gsl_autogate_t *autogate = (gsl_autogate_t *)data;
+	unsigned long flags;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active);
+	del_timer(&autogate->timer);
+	spin_lock_irqsave(&autogate->lock, flags);
+	WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id);
+	autogate->active = 0;
+	/* idle check may sleep, so don't use it */
+//	if (autogate->dev->ftbl.device_idle) 
+//		autogate->dev->ftbl.device_idle(autogate->dev, GSL_TIMEOUT_DEFAULT);
+	kgsl_clock(autogate->dev->id, 0);
+	spin_unlock_irqrestore(&autogate->lock, flags);
+}
+
+int kgsl_device_clock(gsl_deviceid_t id, int enable)
+{
+	int ret = GSL_SUCCESS;
+	gsl_device_t *device;
+
+	device = &gsl_driver.device[id-1];       // device_id is 1 based
+	if (device->flags & GSL_FLAGS_INITIALIZED) {
+		if (enable)
+			kgsl_device_active(device);
+		else
+			kgsl_device_inactive((unsigned long)device);
+	} else {
+		printk(KERN_ERR "%s: Dev %d clock is already off!\n", __func__, id);
+		ret = GSL_FAILURE;
+	}
+	
+	return ret;
+}
+
+int kgsl_device_autogate_init(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate;
+
+//	printk(KERN_ERR "%s:%d id %d\n", __func__, __LINE__, dev->id);
+	autogate = kmalloc(sizeof(gsl_autogate_t), GFP_KERNEL);
+	if (!autogate) {
+		printk(KERN_ERR "%s: out of memory!\n", __func__);
+		return -ENOMEM;
+	}
+	autogate->dev = dev;
+	autogate->active = 1;
+	spin_lock_init(&autogate->lock);
+	autogate->timeout = KGSL_DEVICE_IDLE_TIMEOUT;
+	init_timer(&autogate->timer);
+	autogate->timer.expires = jiffies + msecs_to_jiffies(autogate->timeout);
+	autogate->timer.function = kgsl_device_inactive;
+	autogate->timer.data = (unsigned long)autogate;
+	add_timer(&autogate->timer);
+	dev->autogate = autogate;
+	return 0;
+}
+
+void kgsl_device_autogate_exit(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate = dev->autogate;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id,  autogate->active);
+	if (autogate->active)
+		del_timer(&autogate->timer);
+	else
+		kgsl_clock(autogate->dev->id, 1);
+
+	kfree(autogate);
+	dev->autogate = NULL;
+
+}
diff --git a/drivers/mxc/asrc/Kconfig b/drivers/mxc/asrc/Kconfig
new file mode 100644
index 000000000000..a4c66b19f067
--- /dev/null
+++ b/drivers/mxc/asrc/Kconfig
@@ -0,0 +1,13 @@
+#
+# ASRC configuration
+#
+
+menu "MXC Asynchronous Sample Rate Converter support"
+
+config MXC_ASRC
+	tristate "ASRC support"
+	depends on ARCH_MX35
+	---help---
+         Say Y to get the ASRC service.
+
+endmenu
diff --git a/drivers/mxc/asrc/Makefile b/drivers/mxc/asrc/Makefile
new file mode 100644
index 000000000000..0d2487d389c7
--- /dev/null
+++ b/drivers/mxc/asrc/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the kernel Asynchronous Sample Rate Converter driver
+#
+
+ifeq ($(CONFIG_ARCH_MX35),y)
+	obj-$(CONFIG_MXC_ASRC) += mxc_asrc.o
+endif
diff --git a/drivers/mxc/asrc/mxc_asrc.c b/drivers/mxc/asrc/mxc_asrc.c
new file mode 100644
index 000000000000..14a5135d83d0
--- /dev/null
+++ b/drivers/mxc/asrc/mxc_asrc.c
@@ -0,0 +1,1692 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_asrc.c
+ *
+ * @brief MXC Asynchronous Sample Rate Converter
+ *
+ * @ingroup SOUND
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/dma-mapping.h>
+#include <linux/mxc_asrc.h>
+#include <asm/irq.h>
+#include <asm/memory.h>
+#include <mach/dma.h>
+
+static int asrc_major;
+static struct class *asrc_class;
+#define ASRC_PROC_PATH        "driver/asrc"
+
+#define ASRC_RATIO_DECIMAL_DEPTH 26
+
+DEFINE_SPINLOCK(data_lock);
+DEFINE_SPINLOCK(input_int_lock);
+DEFINE_SPINLOCK(output_int_lock);
+
+#define AICPA		0	/* Input Clock Divider A Offset */
+#define AICDA		3	/* Input Clock Prescaler A Offset */
+#define AICPB           6	/* Input Clock Divider B Offset */
+#define AICDB           9	/* Input Clock Prescaler B Offset */
+#define AOCPA           12	/* Output Clock Divider A Offset */
+#define AOCDA           15	/* Output Clock Prescaler A Offset */
+#define AOCPB           18	/* Output Clock Divider B Offset */
+#define AOCDB           21	/* Output Clock Prescaler B Offset */
+#define AICPC           0	/* Input Clock Divider C Offset */
+#define AICDC           3	/* Input Clock Prescaler C Offset */
+#define AOCDC           6	/* Output Clock Prescaler C Offset */
+#define AOCPC           9	/* Output Clock Divider C Offset */
+
+char *asrc_pair_id[] = {
+	[0] = "ASRC RX PAIR A",
+	[1] = "ASRC TX PAIR A",
+	[2] = "ASRC RX PAIR B",
+	[3] = "ASRC TX PAIR B",
+	[4] = "ASRC RX PAIR C",
+	[5] = "ASRC TX PAIR C",
+};
+
+enum asrc_status {
+	ASRC_ASRSTR_AIDEA = 0x01,
+	ASRC_ASRSTR_AIDEB = 0x02,
+	ASRC_ASRSTR_AIDEC = 0x04,
+	ASRC_ASRSTR_AODFA = 0x08,
+	ASRC_ASRSTR_AODFB = 0x10,
+	ASRC_ASRSTR_AODFC = 0x20,
+	ASRC_ASRSTR_AOLE = 0x40,
+	ASRC_ASRSTR_FPWT = 0x80,
+	ASRC_ASRSTR_AIDUA = 0x100,
+	ASRC_ASRSTR_AIDUB = 0x200,
+	ASRC_ASRSTR_AIDUC = 0x400,
+	ASRC_ASRSTR_AODOA = 0x800,
+	ASRC_ASRSTR_AODOB = 0x1000,
+	ASRC_ASRSTR_AODOC = 0x2000,
+	ASRC_ASRSTR_AIOLA = 0x4000,
+	ASRC_ASRSTR_AIOLB = 0x8000,
+	ASRC_ASRSTR_AIOLC = 0x10000,
+	ASRC_ASRSTR_AOOLA = 0x20000,
+	ASRC_ASRSTR_AOOLB = 0x40000,
+	ASRC_ASRSTR_AOOLC = 0x80000,
+	ASRC_ASRSTR_ATQOL = 0x100000,
+	ASRC_ASRSTR_DSLCNT = 0x200000,
+};
+
+/* Sample rates are aligned with that defined in pcm.h file */
+static const unsigned char asrc_process_table[][8][2] = {
+	/* 32kHz 44.1kHz 48kHz   64kHz   88.2kHz 96kHz  176kHz   192kHz */
+/*5512Hz*/
+	{{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},
+/*8kHz*/
+	{{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},
+/*11025Hz*/
+	{{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},
+/*16kHz*/
+	{{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},
+/*22050Hz*/
+	{{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},
+/*32kHz*/
+	{{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},},
+/*44.1kHz*/
+	{{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},
+/*48kHz*/
+	{{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},
+/*64kHz*/
+	{{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},},
+/*88.2kHz*/
+	{{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},
+/*96kHz*/
+	{{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},
+/*176kHz*/
+	{{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},
+/*192kHz*/
+	{{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},
+};
+
+static const unsigned char asrc_divider_table[] = {
+/*5500Hz 8kHz 11025Hz 16kHz 22050kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176400Hz 192kHz*/
+	0x07, 0x15, 0x06, 0x14, 0x05, 0x13, 0x04, 0x04, 0x12, 0x03, 0x03, 0x02,
+	0x02,
+};
+
+static struct asrc_data *g_asrc_data;
+static struct proc_dir_entry *proc_asrc;
+static unsigned long asrc_vrt_base_addr;
+static struct mxc_asrc_platform_data *mxc_asrc_data;
+
+static int asrc_set_clock_ratio(enum asrc_pair_index index,
+				int input_sample_rate, int output_sample_rate)
+{
+	int i;
+	int integ = 0;
+	unsigned long reg_val = 0;
+
+	if (output_sample_rate == 0)
+		return -1;
+	while (input_sample_rate >= output_sample_rate) {
+		input_sample_rate -= output_sample_rate;
+		integ++;
+	}
+	reg_val |= (integ << 26);
+
+	for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) {
+		if ((input_sample_rate * 2) >= output_sample_rate) {
+			reg_val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i));
+			input_sample_rate =
+			    input_sample_rate * 2 - output_sample_rate;
+		} else
+			input_sample_rate = input_sample_rate << 1;
+
+		if (input_sample_rate == 0)
+			break;
+	}
+
+	__raw_writel(reg_val,
+		     (asrc_vrt_base_addr + ASRC_ASRIDRLA_REG + (index << 3)));
+	__raw_writel((reg_val >> 24),
+		     (asrc_vrt_base_addr + ASRC_ASRIDRHA_REG + (index << 3)));
+	return 0;
+}
+
+static int asrc_set_process_configuration(enum asrc_pair_index index,
+					  int input_sample_rate,
+					  int output_sample_rate)
+{
+	int i = 0, j = 0;
+	unsigned long reg;
+	switch (input_sample_rate) {
+	case 5512:
+		i = 0;
+	case 8000:
+		i = 1;
+		break;
+	case 11025:
+		i = 2;
+		break;
+	case 16000:
+		i = 3;
+		break;
+	case 22050:
+		i = 4;
+		break;
+	case 32000:
+		i = 5;
+		break;
+	case 44100:
+		i = 6;
+		break;
+	case 48000:
+		i = 7;
+		break;
+	case 64000:
+		i = 8;
+		break;
+	case 88200:
+		i = 9;
+		break;
+	case 96000:
+		i = 10;
+		break;
+	case 176400:
+		i = 11;
+		break;
+	case 192000:
+		i = 12;
+		break;
+	default:
+		return -1;
+	}
+
+	switch (output_sample_rate) {
+	case 32000:
+		j = 0;
+		break;
+	case 44100:
+		j = 1;
+		break;
+	case 48000:
+		j = 2;
+		break;
+	case 64000:
+		j = 3;
+		break;
+	case 88200:
+		j = 4;
+		break;
+	case 96000:
+		j = 5;
+		break;
+	case 176400:
+		j = 6;
+		break;
+	case 192000:
+		j = 7;
+		break;
+	default:
+		return -1;
+	}
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG);
+	reg &= ~(0x0f << (6 + (index << 2)));
+	reg |=
+	    ((asrc_process_table[i][j][0] << (6 + (index << 2))) |
+	     (asrc_process_table[i][j][1] << (8 + (index << 2))));
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCFG_REG);
+
+	return 0;
+}
+
+static int asrc_get_asrck_clock_divider(int sample_rate)
+{
+	int i = 0;
+	switch (sample_rate) {
+	case 5500:
+		i = 0;
+		break;
+	case 8000:
+		i = 1;
+		break;
+	case 11025:
+		i = 2;
+		break;
+	case 16000:
+		i = 3;
+		break;
+	case 22050:
+		i = 4;
+		break;
+	case 32000:
+		i = 5;
+		break;
+	case 44100:
+		i = 6;
+		break;
+	case 48000:
+		i = 7;
+		break;
+	case 64000:
+		i = 8;
+		break;
+	case 88200:
+		i = 9;
+		break;
+	case 96000:
+		i = 10;
+		break;
+	case 176400:
+		i = 11;
+		break;
+	case 192000:
+		i = 12;
+		break;
+	default:
+		return -1;
+	}
+
+	return asrc_divider_table[i];
+}
+
+int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
+{
+	int err = 0;
+	unsigned long lock_flags;
+	spin_lock_irqsave(&data_lock, lock_flags);
+
+	if (chn_num > 2) {
+		if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active
+		    || (chn_num > g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_max))
+			err = -EBUSY;
+		else {
+			*index = ASRC_PAIR_C;
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_num = chn_num;
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].active = 1;
+		}
+	} else {
+		if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active ||
+		    (g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_max == 0)) {
+			if (g_asrc_data->asrc_pair[ASRC_PAIR_B].
+			    active
+			    || (g_asrc_data->asrc_pair[ASRC_PAIR_B].
+				chn_max == 0))
+				err = -EBUSY;
+			else {
+				*index = ASRC_PAIR_B;
+				g_asrc_data->asrc_pair[ASRC_PAIR_B].chn_num = 2;
+				g_asrc_data->asrc_pair[ASRC_PAIR_B].active = 1;
+			}
+		} else {
+			*index = ASRC_PAIR_A;
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_num = 2;
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].active = 1;
+		}
+	}
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+	return err;
+}
+
+EXPORT_SYMBOL(asrc_req_pair);
+
+void asrc_release_pair(enum asrc_pair_index index)
+{
+	unsigned long reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&data_lock, lock_flags);
+	g_asrc_data->asrc_pair[index].active = 0;
+	g_asrc_data->asrc_pair[index].overload_error = 0;
+	/********Disable PAIR*************/
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	reg &= ~(1 << (index + 1));
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+}
+
+EXPORT_SYMBOL(asrc_release_pair);
+
+int asrc_config_pair(struct asrc_config *config)
+{
+	int err = 0;
+	int reg, tmp, channel_num;
+	unsigned long lock_flags;
+	/* Set the channel number */
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+	spin_lock_irqsave(&data_lock, lock_flags);
+	g_asrc_data->asrc_pair[config->pair].chn_num = config->channel_num;
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+	reg &=
+	    ~((0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)) <<
+	      (mxc_asrc_data->channel_bits * config->pair));
+	if (mxc_asrc_data->channel_bits > 3)
+		channel_num = config->channel_num;
+	else
+		channel_num = (config->channel_num + 1) / 2;
+	tmp = channel_num << (mxc_asrc_data->channel_bits * config->pair);
+	reg |= tmp;
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+
+	/* Set the clock source */
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCSR_REG);
+	tmp = ~(0x0f << (config->pair << 2));
+	reg &= tmp;
+	tmp = ~(0x0f << (12 + (config->pair << 2)));
+	reg &= tmp;
+	reg |=
+	    ((config->inclk << (config->pair << 2)) | (config->
+						       outclk << (12 +
+								  (config->
+								   pair <<
+								   2))));
+
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCSR_REG);
+
+	/* default setting */
+	/* automatic selection for processing mode */
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	reg |= (1 << (20 + config->pair));
+	reg &= ~(1 << (14 + (config->pair << 1)));
+
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRRA_REG);
+	reg &= 0xffbfffff;
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRRA_REG);
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	reg = reg & (~(1 << 23));
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+
+	/* Default Clock Divider Setting */
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG);
+	if (config->pair == ASRC_PAIR_A) {
+		reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG);
+		reg &= 0xfc0fc0;
+		/* Input Part */
+		if ((config->inclk & 0x0f) == INCLK_SPDIF_RX)
+			reg |= 7 << AICPA;
+		else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX)
+			reg |= 6 << AICPA;
+		else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 input_sample_rate);
+			reg |= tmp << AICPA;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AICPA;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AICPA;
+			else
+				err = -EFAULT;
+		}
+		/* Output Part */
+		if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX)
+			reg |= 7 << AOCPA;
+		else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX)
+			reg |= 6 << AOCPA;
+		else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 output_sample_rate);
+			reg |= tmp << AOCPA;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AOCPA;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AOCPA;
+			else
+				err = -EFAULT;
+		}
+
+		__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG);
+
+	} else if (config->pair == ASRC_PAIR_B) {
+		reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG);
+		reg &= 0x03f03f;
+		/* Input Part */
+		if ((config->inclk & 0x0f) == INCLK_SPDIF_RX)
+			reg |= 7 << AICPB;
+		else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX)
+			reg |= 6 << AICPB;
+		else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 input_sample_rate);
+			reg |= tmp << AICPB;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AICPB;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AICPB;
+			else
+				err = -EFAULT;
+		}
+		/* Output Part */
+		if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX)
+			reg |= 7 << AOCPB;
+		else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX)
+			reg |= 6 << AOCPB;
+		else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 output_sample_rate);
+			reg |= tmp << AOCPB;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AOCPB;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AOCPB;
+			else
+				err = -EFAULT;
+		}
+
+		__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG);
+
+	} else {
+		reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR2_REG);
+		reg &= 0;
+		/* Input Part */
+		if ((config->inclk & 0x0f) == INCLK_SPDIF_RX)
+			reg |= 7 << AICPC;
+		else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX)
+			reg |= 6 << AICPC;
+		else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 input_sample_rate);
+			reg |= tmp << AICPC;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AICPC;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AICPC;
+			else
+				err = -EFAULT;
+		}
+		/* Output Part */
+		if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX)
+			reg |= 7 << AOCPC;
+		else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX)
+			reg |= 6 << AOCPC;
+		else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) {
+			tmp =
+			    asrc_get_asrck_clock_divider(config->
+							 output_sample_rate);
+			reg |= tmp << AOCPC;
+		} else {
+			if (config->word_width == 16 || config->word_width == 8)
+				reg |= 5 << AOCPC;
+			else if (config->word_width == 32
+				 || config->word_width == 24)
+				reg |= 6 << AOCPC;
+			else
+				err = -EFAULT;
+		}
+		__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR2_REG);
+
+	}
+
+	/* check whether ideal ratio is a must */
+	if ((config->inclk & 0x0f) == INCLK_NONE) {
+		reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+		reg &= ~(1 << (20 + config->pair));
+		reg |= (0x03 << (13 + (config->pair << 1)));
+		__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+		err = asrc_set_clock_ratio(config->pair,
+					   config->input_sample_rate,
+					   config->output_sample_rate);
+		if (err < 0)
+			return err;
+
+		err = asrc_set_process_configuration(config->pair,
+						     config->input_sample_rate,
+						     config->
+						     output_sample_rate);
+		if (err < 0)
+			return err;
+	} else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) {
+		if (config->input_sample_rate == 44100
+		    || config->input_sample_rate == 88200) {
+			pr_info
+			    ("ASRC core clock cann't support sample rate %d\n",
+			     config->input_sample_rate);
+			err = -EFAULT;
+		}
+	} else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) {
+		if (config->output_sample_rate == 44100
+		    || config->output_sample_rate == 88200) {
+			pr_info
+			    ("ASRC core clock cann't support sample rate %d\n",
+			     config->input_sample_rate);
+			err = -EFAULT;
+		}
+	}
+
+	return err;
+}
+
+EXPORT_SYMBOL(asrc_config_pair);
+
+void asrc_start_conv(enum asrc_pair_index index)
+{
+	int reg, reg_1;
+	unsigned long lock_flags;
+	int i;
+
+	spin_lock_irqsave(&data_lock, lock_flags);
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	if ((reg & 0x0E) == 0)
+		clk_enable(mxc_asrc_data->asrc_audio_clk);
+	reg |= (1 << (1 + index));
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG);
+	while (!(reg & (1 << (index + 21))))
+		reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG);
+	reg_1 = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG);
+
+	reg = 0;
+	for (i = 0; i < 20; i++) {
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+		__raw_writel(reg,
+			     asrc_vrt_base_addr + ASRC_ASRDIA_REG +
+			     (index << 3));
+	}
+
+	__raw_writel(0x40, asrc_vrt_base_addr + ASRC_ASRIER_REG);
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+	return;
+}
+
+EXPORT_SYMBOL(asrc_start_conv);
+
+void asrc_stop_conv(enum asrc_pair_index index)
+{
+	int reg;
+	unsigned long lock_flags;
+	spin_lock_irqsave(&data_lock, lock_flags);
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	reg &= ~(1 << (1 + index));
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+	if ((reg & 0x0E) == 0)
+		clk_disable(mxc_asrc_data->asrc_audio_clk);
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+	return;
+}
+
+EXPORT_SYMBOL(asrc_stop_conv);
+
+/*!
+ * @brief asrc interrupt handler
+ */
+static irqreturn_t asrc_isr(int irq, void *dev_id)
+{
+	unsigned long status;
+	int reg = 0x40;
+
+	status = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG);
+	if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 1) {
+		if (status & ASRC_ASRSTR_ATQOL)
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |=
+			    ASRC_TASK_Q_OVERLOAD;
+		if (status & ASRC_ASRSTR_AOOLA)
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |=
+			    ASRC_OUTPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AIOLA)
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |=
+			    ASRC_INPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AODOA)
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |=
+			    ASRC_OUTPUT_BUFFER_OVERFLOW;
+		if (status & ASRC_ASRSTR_AIDUA)
+			g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |=
+			    ASRC_INPUT_BUFFER_UNDERRUN;
+	} else if (g_asrc_data->asrc_pair[ASRC_PAIR_B].active == 1) {
+		if (status & ASRC_ASRSTR_ATQOL)
+			g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |=
+			    ASRC_TASK_Q_OVERLOAD;
+		if (status & ASRC_ASRSTR_AOOLB)
+			g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |=
+			    ASRC_OUTPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AIOLB)
+			g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |=
+			    ASRC_INPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AODOB)
+			g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |=
+			    ASRC_OUTPUT_BUFFER_OVERFLOW;
+		if (status & ASRC_ASRSTR_AIDUB)
+			g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |=
+			    ASRC_INPUT_BUFFER_UNDERRUN;
+	} else if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active == 1) {
+		if (status & ASRC_ASRSTR_ATQOL)
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |=
+			    ASRC_TASK_Q_OVERLOAD;
+		if (status & ASRC_ASRSTR_AOOLC)
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |=
+			    ASRC_OUTPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AIOLC)
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |=
+			    ASRC_INPUT_TASK_OVERLOAD;
+		if (status & ASRC_ASRSTR_AODOC)
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |=
+			    ASRC_OUTPUT_BUFFER_OVERFLOW;
+		if (status & ASRC_ASRSTR_AIDUC)
+			g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |=
+			    ASRC_INPUT_BUFFER_UNDERRUN;
+	}
+
+	/* try to clean the overload error  */
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRSTR_REG);
+
+	return IRQ_HANDLED;
+}
+
+void asrc_get_status(struct asrc_status_flags *flags)
+{
+	unsigned long lock_flags;
+	enum asrc_pair_index index;
+
+	spin_lock_irqsave(&data_lock, lock_flags);
+	index = flags->index;
+	flags->overload_error = g_asrc_data->asrc_pair[index].overload_error;
+
+	spin_unlock_irqrestore(&data_lock, lock_flags);
+	return;
+}
+
+EXPORT_SYMBOL(asrc_get_status);
+
+static int mxc_init_asrc(void)
+{
+	/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
+	__raw_writel(0x0001, asrc_vrt_base_addr + ASRC_ASRCTR_REG);
+
+	/* Enable overflow interrupt */
+	__raw_writel(0x00, asrc_vrt_base_addr + ASRC_ASRIER_REG);
+
+	/* Default 6: 2: 2 channel assignment */
+	__raw_writel((0x06 << mxc_asrc_data->channel_bits *
+		      2) | (0x02 << mxc_asrc_data->channel_bits) | 0x02,
+		     asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+
+	/* Parameter Registers recommended settings */
+	__raw_writel(0x7fffff, asrc_vrt_base_addr + ASRC_ASRPM1_REG);
+	__raw_writel(0x255555, asrc_vrt_base_addr + ASRC_ASRPM2_REG);
+	__raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM3_REG);
+	__raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM4_REG);
+	__raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM5_REG);
+
+	__raw_writel(0x001f00, asrc_vrt_base_addr + ASRC_ASRTFR1);
+
+	/* Set the processing clock for 76KHz, 133M  */
+	__raw_writel(0x06D6, asrc_vrt_base_addr + ASRC_ASR76K_REG);
+
+	/* Set the processing clock for 56KHz, 133M */
+	__raw_writel(0x0947, asrc_vrt_base_addr + ASRC_ASR56K_REG);
+
+	if (request_irq(MXC_INT_ASRC, asrc_isr, 0, "asrc", NULL))
+		return -1;
+
+	return 0;
+}
+
+static int asrc_get_output_buffer_size(int input_buffer_size,
+				       int input_sample_rate,
+				       int output_sample_rate)
+{
+	int i = 0;
+	int outbuffer_size = 0;
+	int outsample = output_sample_rate;
+	while (outsample >= input_sample_rate) {
+		++i;
+		outsample -= input_sample_rate;
+	}
+	outbuffer_size = i * input_buffer_size;
+	i = 1;
+	while (((input_buffer_size >> i) > 2) && (outsample != 0)) {
+		if (((outsample << 1) - input_sample_rate) >= 0) {
+			outsample = (outsample << 1) - input_sample_rate;
+			outbuffer_size += (input_buffer_size >> i);
+		} else {
+			outsample = outsample << 1;
+		}
+		i++;
+	}
+	outbuffer_size = (outbuffer_size >> 3) << 3;
+	return outbuffer_size;
+}
+
+static void asrc_input_dma_callback(void *data, int error, unsigned int count)
+{
+	struct asrc_pair_params *params;
+	struct dma_block *block;
+	mxc_dma_requestbuf_t dma_request;
+	unsigned long lock_flags;
+
+	params = data;
+
+	spin_lock_irqsave(&input_int_lock, lock_flags);
+	params->input_queue_empty--;
+	if (!list_empty(&params->input_queue)) {
+		block =
+		    list_entry(params->input_queue.next,
+			       struct dma_block, queue);
+		dma_request.src_addr = (dma_addr_t) block->dma_paddr;
+		dma_request.dst_addr =
+		    (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + (params->index << 3));
+		dma_request.num_of_bytes = block->length;
+		mxc_dma_config(params->input_dma_channel, &dma_request,
+			       1, MXC_DMA_MODE_WRITE);
+		list_del(params->input_queue.next);
+		list_add_tail(&block->queue, &params->input_done_queue);
+		params->input_queue_empty++;
+	}
+	params->input_counter++;
+	wake_up_interruptible(&params->input_wait_queue);
+	spin_unlock_irqrestore(&input_int_lock, lock_flags);
+	return;
+}
+
+static void asrc_output_dma_callback(void *data, int error, unsigned int count)
+{
+	struct asrc_pair_params *params;
+	struct dma_block *block;
+	mxc_dma_requestbuf_t dma_request;
+	unsigned long lock_flags;
+
+	params = data;
+
+	spin_lock_irqsave(&output_int_lock, lock_flags);
+	params->output_queue_empty--;
+
+	if (!list_empty(&params->output_queue)) {
+		block =
+		    list_entry(params->output_queue.next,
+			       struct dma_block, queue);
+		dma_request.src_addr =
+		    (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + (params->index << 3));
+		dma_request.dst_addr = (dma_addr_t) block->dma_paddr;
+		dma_request.num_of_bytes = block->length;
+		mxc_dma_config(params->output_dma_channel, &dma_request,
+			       1, MXC_DMA_MODE_READ);
+		list_del(params->output_queue.next);
+		list_add_tail(&block->queue, &params->output_done_queue);
+		params->output_queue_empty++;
+	}
+	params->output_counter++;
+	wake_up_interruptible(&params->output_wait_queue);
+	spin_unlock_irqrestore(&output_int_lock, lock_flags);
+	return;
+}
+
+static void mxc_free_dma_buf(struct asrc_pair_params *params)
+{
+	int i;
+	for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) {
+		if (params->input_dma[i].dma_vaddr != NULL) {
+			dma_free_coherent(0,
+					  params->input_buffer_size,
+					  params->input_dma[i].
+					  dma_vaddr,
+					  params->input_dma[i].dma_paddr);
+			params->input_dma[i].dma_vaddr = NULL;
+		}
+		if (params->output_dma[i].dma_vaddr != NULL) {
+			dma_free_coherent(0,
+					  params->output_buffer_size,
+					  params->output_dma[i].
+					  dma_vaddr,
+					  params->output_dma[i].dma_paddr);
+			params->output_dma[i].dma_vaddr = NULL;
+		}
+	}
+
+	return;
+}
+
+static int mxc_allocate_dma_buf(struct asrc_pair_params *params)
+{
+	int i;
+	for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) {
+		params->input_dma[i].dma_vaddr =
+		    dma_alloc_coherent(0, params->input_buffer_size,
+				       &params->input_dma[i].dma_paddr,
+				       GFP_DMA | GFP_KERNEL);
+		if (params->input_dma[i].dma_vaddr == NULL) {
+			mxc_free_dma_buf(params);
+			pr_info("can't allocate buff\n");
+			return -ENOBUFS;
+		}
+	}
+	for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) {
+		params->output_dma[i].dma_vaddr =
+		    dma_alloc_coherent(0,
+				       params->output_buffer_size,
+				       &params->output_dma[i].dma_paddr,
+				       GFP_DMA | GFP_KERNEL);
+		if (params->output_dma[i].dma_vaddr == NULL) {
+			mxc_free_dma_buf(params);
+			return -ENOBUFS;
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * asrc interface - ioctl function
+ *
+ * @param inode      struct inode *
+ *
+ * @param file       struct file *
+ *
+ * @param cmd    unsigned int
+ *
+ * @param arg        unsigned long
+ *
+ * @return           0 success, ENODEV for invalid device instance,
+ *                   -1 for other errors.
+ */
+static int asrc_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, unsigned long arg)
+{
+	int err = 0;
+	struct asrc_pair_params *params;
+	params = file->private_data;
+
+	if (down_interruptible(&params->busy_lock))
+		return -EBUSY;
+	switch (cmd) {
+	case ASRC_REQ_PAIR:
+		{
+			struct asrc_req req;
+			if (copy_from_user(&req, (void __user *)arg,
+					   sizeof(struct asrc_req))) {
+				err = -EFAULT;
+				break;
+			}
+			err = asrc_req_pair(req.chn_num, &req.index);
+			if (err < 0)
+				break;
+			params->pair_hold = 1;
+			params->index = req.index;
+			if (copy_to_user
+			    ((void __user *)arg, &req, sizeof(struct asrc_req)))
+				err = -EFAULT;
+
+			break;
+		}
+	case ASRC_CONFIG_PAIR:
+		{
+			struct asrc_config config;
+			mxc_dma_device_t rx_id, tx_id;
+			char *rx_name, *tx_name;
+			int channel = -1;
+			if (copy_from_user
+			    (&config, (void __user *)arg,
+			     sizeof(struct asrc_config))) {
+				err = -EFAULT;
+				break;
+			}
+			err = asrc_config_pair(&config);
+			if (err < 0)
+				break;
+			params->output_buffer_size =
+			    asrc_get_output_buffer_size(config.
+							dma_buffer_size,
+							config.
+							input_sample_rate,
+							config.
+							output_sample_rate);
+			params->input_buffer_size = config.dma_buffer_size;
+			if (config.buffer_num > ASRC_DMA_BUFFER_NUM)
+				params->buffer_num = ASRC_DMA_BUFFER_NUM;
+			else
+				params->buffer_num = config.buffer_num;
+			err = mxc_allocate_dma_buf(params);
+			if (err < 0)
+				break;
+
+			/* TBD - need to update when new SDMA interface ready */
+			if (config.pair == ASRC_PAIR_A) {
+				rx_id = MXC_DMA_ASRC_A_RX;
+				tx_id = MXC_DMA_ASRC_A_TX;
+				rx_name = asrc_pair_id[0];
+				tx_name = asrc_pair_id[1];
+			} else if (config.pair == ASRC_PAIR_B) {
+				rx_id = MXC_DMA_ASRC_B_RX;
+				tx_id = MXC_DMA_ASRC_B_TX;
+				rx_name = asrc_pair_id[2];
+				tx_name = asrc_pair_id[3];
+			} else {
+				rx_id = MXC_DMA_ASRC_C_RX;
+				tx_id = MXC_DMA_ASRC_C_TX;
+				rx_name = asrc_pair_id[4];
+				tx_name = asrc_pair_id[5];
+			}
+			channel = mxc_dma_request(rx_id, rx_name);
+			params->input_dma_channel = channel;
+			err = mxc_dma_callback_set(channel, (mxc_dma_callback_t)
+						   asrc_input_dma_callback,
+						   (void *)params);
+			channel = mxc_dma_request(tx_id, tx_name);
+			params->output_dma_channel = channel;
+			err = mxc_dma_callback_set(channel, (mxc_dma_callback_t)
+						   asrc_output_dma_callback,
+						   (void *)params);
+			/* TBD - need to update when new SDMA interface ready */
+			params->input_queue_empty = 0;
+			params->output_queue_empty = 0;
+			INIT_LIST_HEAD(&params->input_queue);
+			INIT_LIST_HEAD(&params->input_done_queue);
+			INIT_LIST_HEAD(&params->output_queue);
+			INIT_LIST_HEAD(&params->output_done_queue);
+			init_waitqueue_head(&params->input_wait_queue);
+			init_waitqueue_head(&params->output_wait_queue);
+
+			if (copy_to_user
+			    ((void __user *)arg, &config,
+			     sizeof(struct asrc_config)))
+				err = -EFAULT;
+			break;
+		}
+	case ASRC_QUERYBUF:
+		{
+			struct asrc_querybuf buffer;
+			if (copy_from_user
+			    (&buffer, (void __user *)arg,
+			     sizeof(struct asrc_querybuf))) {
+				err = -EFAULT;
+				break;
+			}
+			buffer.input_offset =
+			    (unsigned long)params->input_dma[buffer.
+							     buffer_index].
+			    dma_paddr;
+			buffer.input_length = params->input_buffer_size;
+			buffer.output_offset =
+			    (unsigned long)params->output_dma[buffer.
+							      buffer_index].
+			    dma_paddr;
+			buffer.output_length = params->output_buffer_size;
+			if (copy_to_user
+			    ((void __user *)arg, &buffer,
+			     sizeof(struct asrc_querybuf)))
+				err = -EFAULT;
+			break;
+		}
+	case ASRC_RELEASE_PAIR:
+		{
+			enum asrc_pair_index index;
+			if (copy_from_user
+			    (&index, (void __user *)arg,
+			     sizeof(enum asrc_pair_index))) {
+				err = -EFAULT;
+				break;
+			}
+
+			mxc_dma_free(params->input_dma_channel);
+			mxc_dma_free(params->output_dma_channel);
+			mxc_free_dma_buf(params);
+			asrc_release_pair(index);
+			params->pair_hold = 0;
+			break;
+		}
+	case ASRC_Q_INBUF:
+		{
+			struct asrc_buffer buf;
+			struct dma_block *block;
+			mxc_dma_requestbuf_t dma_request;
+			unsigned long lock_flags;
+			if (copy_from_user
+			    (&buf, (void __user *)arg,
+			     sizeof(struct asrc_buffer))) {
+				err = -EFAULT;
+				break;
+			}
+			spin_lock_irqsave(&input_int_lock, lock_flags);
+			params->input_dma[buf.index].index = buf.index;
+			params->input_dma[buf.index].length = buf.length;
+			list_add_tail(&params->input_dma[buf.index].
+				      queue, &params->input_queue);
+			if (params->asrc_active == 0
+			    || params->input_queue_empty == 0) {
+				block =
+				    list_entry(params->input_queue.next,
+					       struct dma_block, queue);
+				dma_request.src_addr =
+				    (dma_addr_t) block->dma_paddr;
+				dma_request.dst_addr =
+				    (ASRC_BASE_ADDR + ASRC_ASRDIA_REG +
+				     (params->index << 3));
+				dma_request.num_of_bytes = block->length;
+				mxc_dma_config(params->
+					       input_dma_channel,
+					       &dma_request, 1,
+					       MXC_DMA_MODE_WRITE);
+				params->input_queue_empty++;
+				list_del(params->input_queue.next);
+				list_add_tail(&block->queue,
+					      &params->input_done_queue);
+			}
+
+			spin_unlock_irqrestore(&input_int_lock, lock_flags);
+			break;
+		}
+	case ASRC_DQ_INBUF:{
+			struct asrc_buffer buf;
+			struct dma_block *block;
+			unsigned long lock_flags;
+			if (copy_from_user
+			    (&buf, (void __user *)arg,
+			     sizeof(struct asrc_buffer))) {
+				err = -EFAULT;
+				break;
+			}
+			/* if ASRC is inactive, nonsense to DQ buffer */
+			if (params->asrc_active == 0) {
+				err = -EFAULT;
+				buf.buf_valid = ASRC_BUF_NA;
+				if (copy_to_user
+				    ((void __user *)arg, &buf,
+				     sizeof(struct asrc_buffer)))
+					err = -EFAULT;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout
+			    (params->input_wait_queue,
+			     params->input_counter != 0, 10 * HZ)) {
+				pr_info
+				    ("ASRC_DQ_INBUF timeout counter %x\n",
+				     params->input_counter);
+				err = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				pr_info("ASRC_DQ_INBUF interrupt received\n");
+				err = -ERESTARTSYS;
+				break;
+			}
+			spin_lock_irqsave(&input_int_lock, lock_flags);
+			params->input_counter--;
+			block =
+			    list_entry(params->input_done_queue.next,
+				       struct dma_block, queue);
+			list_del(params->input_done_queue.next);
+			spin_unlock_irqrestore(&input_int_lock, lock_flags);
+			buf.index = block->index;
+			buf.length = block->length;
+			buf.buf_valid = ASRC_BUF_AV;
+			if (copy_to_user
+			    ((void __user *)arg, &buf,
+			     sizeof(struct asrc_buffer)))
+				err = -EFAULT;
+
+			break;
+		}
+	case ASRC_Q_OUTBUF:{
+			struct asrc_buffer buf;
+			struct dma_block *block;
+			mxc_dma_requestbuf_t dma_request;
+			unsigned long lock_flags;
+			if (copy_from_user
+			    (&buf, (void __user *)arg,
+			     sizeof(struct asrc_buffer))) {
+				err = -EFAULT;
+				break;
+			}
+			spin_lock_irqsave(&output_int_lock, lock_flags);
+			params->output_dma[buf.index].index = buf.index;
+			params->output_dma[buf.index].length = buf.length;
+			list_add_tail(&params->output_dma[buf.index].
+				      queue, &params->output_queue);
+			if (params->asrc_active == 0
+			    || params->output_queue_empty == 0) {
+				block =
+				    list_entry(params->output_queue.
+					       next, struct dma_block, queue);
+				dma_request.src_addr =
+				    (ASRC_BASE_ADDR + ASRC_ASRDOA_REG +
+				     (params->index << 3));
+				dma_request.dst_addr =
+				    (dma_addr_t) block->dma_paddr;
+				dma_request.num_of_bytes = block->length;
+				mxc_dma_config(params->
+					       output_dma_channel,
+					       &dma_request, 1,
+					       MXC_DMA_MODE_READ);
+				list_del(params->output_queue.next);
+				list_add_tail(&block->queue,
+					      &params->output_done_queue);
+				params->output_queue_empty++;
+			}
+
+			spin_unlock_irqrestore(&output_int_lock, lock_flags);
+			break;
+		}
+	case ASRC_DQ_OUTBUF:{
+			struct asrc_buffer buf;
+			struct dma_block *block;
+			unsigned long lock_flags;
+			if (copy_from_user
+			    (&buf, (void __user *)arg,
+			     sizeof(struct asrc_buffer))) {
+				err = -EFAULT;
+				break;
+			}
+			/* if ASRC is inactive, nonsense to DQ buffer */
+			if (params->asrc_active == 0) {
+				buf.buf_valid = ASRC_BUF_NA;
+				err = -EFAULT;
+				if (copy_to_user
+				    ((void __user *)arg, &buf,
+				     sizeof(struct asrc_buffer)))
+					err = -EFAULT;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout
+			    (params->output_wait_queue,
+			     params->output_counter != 0, 10 * HZ)) {
+				pr_info
+				    ("ASRC_DQ_OUTBUF timeout counter %x\n",
+				     params->output_counter);
+				err = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				pr_info("ASRC_DQ_INBUF interrupt received\n");
+				err = -ERESTARTSYS;
+				break;
+			}
+			spin_lock_irqsave(&output_int_lock, lock_flags);
+			params->output_counter--;
+			block =
+			    list_entry(params->output_done_queue.next,
+				       struct dma_block, queue);
+			list_del(params->output_done_queue.next);
+			spin_unlock_irqrestore(&output_int_lock, lock_flags);
+			buf.index = block->index;
+			buf.length = block->length;
+			buf.buf_valid = ASRC_BUF_AV;
+			if (copy_to_user
+			    ((void __user *)arg, &buf,
+			     sizeof(struct asrc_buffer)))
+				err = -EFAULT;
+
+			break;
+		}
+	case ASRC_START_CONV:{
+			enum asrc_pair_index index;
+			unsigned long lock_flags;
+			if (copy_from_user
+			    (&index, (void __user *)arg,
+			     sizeof(enum asrc_pair_index))) {
+				err = -EFAULT;
+				break;
+			}
+
+			spin_lock_irqsave(&input_int_lock, lock_flags);
+			if (params->input_queue_empty == 0) {
+				err = -EFAULT;
+				pr_info
+				    ("ASRC_START_CONV - no block available\n");
+				break;
+			}
+			spin_unlock_irqrestore(&input_int_lock, lock_flags);
+			params->asrc_active = 1;
+
+			asrc_start_conv(index);
+			mxc_dma_enable(params->input_dma_channel);
+			mxc_dma_enable(params->output_dma_channel);
+			break;
+		}
+	case ASRC_STOP_CONV:{
+			enum asrc_pair_index index;
+			if (copy_from_user
+			    (&index, (void __user *)arg,
+			     sizeof(enum asrc_pair_index))) {
+				err = -EFAULT;
+				break;
+			}
+			mxc_dma_disable(params->input_dma_channel);
+			mxc_dma_disable(params->output_dma_channel);
+			asrc_stop_conv(index);
+			params->asrc_active = 0;
+			break;
+		}
+	case ASRC_STATUS:{
+			struct asrc_status_flags flags;
+			if (copy_from_user
+			    (&flags, (void __user *)arg,
+			     sizeof(struct asrc_status_flags))) {
+				err = -EFAULT;
+				break;
+			}
+			asrc_get_status(&flags);
+			if (copy_to_user
+			    ((void __user *)arg, &flags,
+			     sizeof(struct asrc_status_flags)))
+				err = -EFAULT;
+			break;
+		}
+	case ASRC_FLUSH:{
+			/* flush input dma buffer */
+			unsigned long lock_flags;
+			mxc_dma_device_t rx_id, tx_id;
+			char *rx_name, *tx_name;
+			int channel = -1;
+			spin_lock_irqsave(&input_int_lock, lock_flags);
+			while (!list_empty(&params->input_queue))
+				list_del(params->input_queue.next);
+			while (!list_empty(&params->input_done_queue))
+				list_del(params->input_done_queue.next);
+			params->input_counter = 0;
+			params->input_queue_empty = 0;
+			spin_unlock_irqrestore(&input_int_lock, lock_flags);
+
+			/* flush output dma buffer */
+			spin_lock_irqsave(&output_int_lock, lock_flags);
+			while (!list_empty(&params->output_queue))
+				list_del(params->output_queue.next);
+			while (!list_empty(&params->output_done_queue))
+				list_del(params->output_done_queue.next);
+			params->output_counter = 0;
+			params->output_queue_empty = 0;
+			spin_unlock_irqrestore(&output_int_lock, lock_flags);
+
+			/* release DMA and request again */
+			mxc_dma_free(params->input_dma_channel);
+			mxc_dma_free(params->output_dma_channel);
+			if (params->index == ASRC_PAIR_A) {
+				rx_id = MXC_DMA_ASRC_A_RX;
+				tx_id = MXC_DMA_ASRC_A_TX;
+				rx_name = asrc_pair_id[0];
+				tx_name = asrc_pair_id[1];
+			} else if (params->index == ASRC_PAIR_B) {
+				rx_id = MXC_DMA_ASRC_B_RX;
+				tx_id = MXC_DMA_ASRC_B_TX;
+				rx_name = asrc_pair_id[2];
+				tx_name = asrc_pair_id[3];
+			} else {
+				rx_id = MXC_DMA_ASRC_C_RX;
+				tx_id = MXC_DMA_ASRC_C_TX;
+				rx_name = asrc_pair_id[4];
+				tx_name = asrc_pair_id[5];
+			}
+			channel = mxc_dma_request(rx_id, rx_name);
+			params->input_dma_channel = channel;
+			err = mxc_dma_callback_set(channel, (mxc_dma_callback_t)
+						   asrc_input_dma_callback,
+						   (void *)params);
+			channel = mxc_dma_request(tx_id, tx_name);
+			params->output_dma_channel = channel;
+			err = mxc_dma_callback_set(channel, (mxc_dma_callback_t)
+						   asrc_output_dma_callback,
+						   (void *)params);
+
+			break;
+		}
+	default:
+		break;
+	}
+
+	up(&params->busy_lock);
+	return err;
+}
+
+/*!
+ * asrc interface - open function
+ *
+ * @param inode        structure inode *
+ *
+ * @param file         structure file *
+ *
+ * @return  status    0 success, ENODEV invalid device instance,
+ *      ENOBUFS failed to allocate buffer, ERESTARTSYS interrupted by user
+ */
+static int mxc_asrc_open(struct inode *inode, struct file *file)
+{
+	int err = 0;
+	struct asrc_pair_params *pair_params;
+	if (signal_pending(current))
+		return -EINTR;
+	pair_params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL);
+	if (pair_params == NULL) {
+		pr_debug("Failed to allocate pair_params\n");
+		err = -ENOBUFS;
+	}
+
+	init_MUTEX(&pair_params->busy_lock);
+	file->private_data = pair_params;
+	return err;
+}
+
+/*!
+ * asrc interface - close function
+ *
+ * @param inode    struct inode *
+ * @param file        structure file *
+ *
+ * @return status     0 Success, EINTR busy lock error, ENOBUFS remap_page error
+ */
+static int mxc_asrc_close(struct inode *inode, struct file *file)
+{
+	struct asrc_pair_params *pair_params;
+	pair_params = file->private_data;
+	if (pair_params->asrc_active == 1) {
+		mxc_dma_disable(pair_params->input_dma_channel);
+		mxc_dma_disable(pair_params->output_dma_channel);
+		asrc_stop_conv(pair_params->index);
+		wake_up_interruptible(&pair_params->input_wait_queue);
+		wake_up_interruptible(&pair_params->output_wait_queue);
+	}
+	if (pair_params->pair_hold == 1) {
+		mxc_dma_free(pair_params->input_dma_channel);
+		mxc_dma_free(pair_params->output_dma_channel);
+		mxc_free_dma_buf(pair_params);
+		asrc_release_pair(pair_params->index);
+	}
+	kfree(pair_params);
+	file->private_data = NULL;
+	return 0;
+}
+
+/*!
+ * asrc interface - mmap function
+ *
+ * @param file        structure file *
+ *
+ * @param vma         structure vm_area_struct *
+ *
+ * @return status     0 Success, EINTR busy lock error, ENOBUFS remap_page error
+ */
+static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	unsigned long size;
+	int res = 0;
+	size = vma->vm_end - vma->vm_start;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot))
+		return -ENOBUFS;
+
+	vma->vm_flags &= ~VM_IO;
+	return res;
+}
+
+static struct file_operations asrc_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = asrc_ioctl,
+	.mmap = mxc_asrc_mmap,
+	.open = mxc_asrc_open,
+	.release = mxc_asrc_close,
+};
+
+static int asrc_read_proc_attr(char *page, char **start, off_t off,
+			       int count, int *eof, void *data)
+{
+	unsigned long reg;
+	int len = 0;
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+
+	len += sprintf(page, "ANCA: %d\n",
+		       (int)(reg &
+			     (0xFFFFFFFF >>
+			      (32 - mxc_asrc_data->channel_bits))));
+	len +=
+	    sprintf(page + len, "ANCB: %d\n",
+		    (int)((reg >> mxc_asrc_data->
+			   channel_bits) & (0xFFFFFFFF >> (32 -
+							   mxc_asrc_data->
+							   channel_bits))));
+	len +=
+	    sprintf(page + len, "ANCC: %d\n",
+		    (int)((reg >> (mxc_asrc_data->channel_bits * 2)) &
+			  (0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits))));
+
+	if (off > len)
+		return 0;
+
+	*eof = (len <= count) ? 1 : 0;
+	*start = page + off;
+
+	return min(count, len - (int)off);
+}
+
+static int asrc_write_proc_attr(struct file *file, const char *buffer,
+				unsigned long count, void *data)
+{
+	char buf[50];
+	unsigned long reg;
+	int na, nb, nc;
+	int total;
+	if (count > 48)
+		return -EINVAL;
+	if (copy_from_user(buf, buffer, count)) {
+		pr_debug("Attr proc write, Failed to copy buffer from user\n");
+		return -EFAULT;
+	}
+
+	reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+	sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc);
+	if (mxc_asrc_data->channel_bits > 3)
+		total = 10;
+	else
+		total = 5;
+	if ((na + nb + nc) != total) {
+		pr_info("Wrong ASRCNR settings\n");
+		return -EFAULT;
+	}
+	reg = na | (nb << mxc_asrc_data->
+		    channel_bits) | (nc << (mxc_asrc_data->channel_bits * 2));
+
+	__raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG);
+
+	return count;
+}
+
+static void asrc_proc_create(void)
+{
+	struct proc_dir_entry *proc_attr;
+	proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL);
+	if (proc_asrc) {
+		proc_attr = create_proc_entry("ChSettings",
+					      S_IFREG | S_IRUGO |
+					      S_IWUSR, proc_asrc);
+		if (proc_attr) {
+			proc_attr->read_proc = asrc_read_proc_attr;
+			proc_attr->write_proc = asrc_write_proc_attr;
+			proc_attr->size = 48;
+			proc_attr->uid = proc_attr->gid = 0;
+		} else {
+			remove_proc_entry(ASRC_PROC_PATH, NULL);
+			pr_info("Failed to create proc attribute entry \n");
+		}
+	} else {
+		pr_info("ASRC: Failed to create proc entry %s\n",
+			ASRC_PROC_PATH);
+	}
+}
+
+/*!
+ * Entry point for the asrc device
+ *
+ * @param	pdev Pionter to the registered platform device
+ * @return  Error code indicating success or failure
+ */
+static int mxc_asrc_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct resource *res;
+	struct device *temp_class;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOENT;
+
+	g_asrc_data = kzalloc(sizeof(struct asrc_data), GFP_KERNEL);
+
+	if (g_asrc_data == NULL) {
+		pr_info("Failed to allocate g_asrc_data\n");
+		return -ENOMEM;
+	}
+
+	g_asrc_data->asrc_pair[0].chn_max = 2;
+	g_asrc_data->asrc_pair[1].chn_max = 2;
+	g_asrc_data->asrc_pair[2].chn_max = 6;
+	g_asrc_data->asrc_pair[0].overload_error = 0;
+	g_asrc_data->asrc_pair[1].overload_error = 0;
+	g_asrc_data->asrc_pair[2].overload_error = 0;
+
+	asrc_major = register_chrdev(asrc_major, "mxc_asrc", &asrc_fops);
+	if (asrc_major < 0) {
+		pr_info("Unable to register asrc device\n");
+		err = -EBUSY;
+		goto error;
+	}
+
+	asrc_class = class_create(THIS_MODULE, "mxc_asrc");
+	if (IS_ERR(asrc_class)) {
+		err = PTR_ERR(asrc_class);
+		goto err_out_chrdev;
+	}
+
+	temp_class = device_create(asrc_class, NULL, MKDEV(asrc_major, 0),
+				   NULL, "mxc_asrc");
+	if (IS_ERR(temp_class)) {
+		err = PTR_ERR(temp_class);
+		goto err_out_class;
+	}
+
+	asrc_vrt_base_addr =
+	    (unsigned long)ioremap(res->start, res->end - res->start + 1);
+
+	mxc_asrc_data =
+	    (struct mxc_asrc_platform_data *)pdev->dev.platform_data;
+	clk_enable(mxc_asrc_data->asrc_core_clk);
+
+	asrc_proc_create();
+	err = mxc_init_asrc();
+	if (err < 0)
+		goto err_out_class;
+
+	goto out;
+
+      err_out_class:
+	clk_disable(mxc_asrc_data->asrc_core_clk);
+	device_destroy(asrc_class, MKDEV(asrc_major, 0));
+	class_destroy(asrc_class);
+      err_out_chrdev:
+	unregister_chrdev(asrc_major, "mxc_asrc");
+      error:
+	kfree(g_asrc_data);
+      out:
+	pr_info("mxc_asrc registered\n");
+	return err;
+}
+
+/*!
+ * Exit asrc device
+ *
+ * @param	pdev Pionter to the registered platform device
+ * @return  Error code indicating success or failure
+ */
+static int mxc_asrc_remove(struct platform_device *pdev)
+{
+	free_irq(MXC_INT_ASRC, NULL);
+	kfree(g_asrc_data);
+	clk_disable(mxc_asrc_data->asrc_core_clk);
+	mxc_asrc_data = NULL;
+	iounmap((unsigned long __iomem *)asrc_vrt_base_addr);
+	remove_proc_entry("ChSettings", proc_asrc);
+	remove_proc_entry(ASRC_PROC_PATH, NULL);
+	device_destroy(asrc_class, MKDEV(asrc_major, 0));
+	class_destroy(asrc_class);
+	unregister_chrdev(asrc_major, "mxc_asrc");
+	return 0;
+}
+
+/*! mxc asrc driver definition
+ *
+ */
+static struct platform_driver mxc_asrc_driver = {
+	.driver = {
+		   .name = "mxc_asrc",
+		   },
+	.probe = mxc_asrc_probe,
+	.remove = mxc_asrc_remove,
+};
+
+/*!
+ * Register asrc driver
+ *
+ */
+static __init int asrc_init(void)
+{
+	int ret;
+	ret = platform_driver_register(&mxc_asrc_driver);
+	return ret;
+}
+
+/*!
+ * Exit and free the asrc data
+ *
+ */ static void __exit asrc_exit(void)
+{
+	platform_driver_unregister(&mxc_asrc_driver);
+	return;
+}
+
+module_init(asrc_init);
+module_exit(asrc_exit);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Asynchronous Sample Rate Converter");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/bt/Kconfig b/drivers/mxc/bt/Kconfig
new file mode 100644
index 000000000000..9dbfbe57a14f
--- /dev/null
+++ b/drivers/mxc/bt/Kconfig
@@ -0,0 +1,13 @@
+#
+# Bluetooth configuration
+#
+
+menu "MXC Bluetooth support"
+
+config MXC_BLUETOOTH
+	tristate "MXC Bluetooth support"
+	depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS
+	---help---
+         Say Y to get the third party Bluetooth service.
+
+endmenu
diff --git a/drivers/mxc/bt/Makefile b/drivers/mxc/bt/Makefile
new file mode 100644
index 000000000000..91bc4cff380e
--- /dev/null
+++ b/drivers/mxc/bt/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for the kernel Bluetooth power-on/reset
+#
+obj-$(CONFIG_MXC_BLUETOOTH) += mxc_bt.o
diff --git a/drivers/mxc/bt/mxc_bt.c b/drivers/mxc/bt/mxc_bt.c
new file mode 100644
index 000000000000..ae08b379ef70
--- /dev/null
+++ b/drivers/mxc/bt/mxc_bt.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_bt.c
+ *
+ * @brief MXC Thirty party Bluetooth
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+
+static struct regulator *bt_vdd;
+static struct regulator *bt_vdd_parent;
+static struct regulator *bt_vusb;
+static struct regulator *bt_vusb_parent;
+
+/*!
+  * This function poweron the bluetooth hardware module
+  *
+  * @param      pdev    Pointer to the platform device
+  * @return              0 on success, -1 otherwise.
+  */
+static int mxc_bt_probe(struct platform_device *pdev)
+{
+	struct mxc_bt_platform_data *platform_data;
+	platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data;
+	if (platform_data->bt_vdd) {
+		bt_vdd = regulator_get(&pdev->dev, platform_data->bt_vdd);
+		regulator_enable(bt_vdd);
+	}
+	if (platform_data->bt_vdd_parent) {
+		bt_vdd_parent =
+		    regulator_get(&pdev->dev, platform_data->bt_vdd_parent);
+		regulator_enable(bt_vdd_parent);
+	}
+	if (platform_data->bt_vusb) {
+		bt_vusb = regulator_get(&pdev->dev, platform_data->bt_vusb);
+		regulator_enable(bt_vusb);
+	}
+	if (platform_data->bt_vusb_parent) {
+		bt_vusb_parent =
+		    regulator_get(&pdev->dev, platform_data->bt_vusb_parent);
+		regulator_enable(bt_vusb_parent);
+	}
+
+	if (platform_data->bt_reset != NULL)
+		platform_data->bt_reset();
+	return 0;
+
+}
+
+/*!
+  * This function poweroff the bluetooth hardware module
+  *
+  * @param      pdev    Pointer to the platform device
+  * @return              0 on success, -1 otherwise.
+  */
+static int mxc_bt_remove(struct platform_device *pdev)
+{
+	struct mxc_bt_platform_data *platform_data;
+	platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data;
+	if (bt_vdd) {
+		regulator_disable(bt_vdd);
+		regulator_put(bt_vdd);
+	}
+	if (bt_vdd_parent) {
+		regulator_disable(bt_vdd_parent);
+		regulator_put(bt_vdd_parent);
+	}
+	if (bt_vusb) {
+		regulator_disable(bt_vusb);
+		regulator_put(bt_vusb);
+	}
+	if (bt_vusb_parent) {
+		regulator_disable(bt_vusb_parent);
+		regulator_put(bt_vusb_parent);
+	}
+	return 0;
+
+}
+
+static struct platform_driver bluetooth_driver = {
+	.driver = {
+		   .name = "mxc_bt",
+		   },
+	.probe = mxc_bt_probe,
+	.remove = mxc_bt_remove,
+};
+
+/*!
+ * Register bluetooth driver module
+ *
+ */
+static __init int bluetooth_init(void)
+{
+	return platform_driver_register(&bluetooth_driver);
+}
+
+/*!
+ * Exit and free the bluetooth module
+ *
+ */
+static void __exit bluetooth_exit(void)
+{
+	platform_driver_unregister(&bluetooth_driver);
+}
+
+module_init(bluetooth_init);
+module_exit(bluetooth_exit);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC Thirty party Bluetooth");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/dam/Kconfig b/drivers/mxc/dam/Kconfig
new file mode 100644
index 000000000000..7b4bee92f648
--- /dev/null
+++ b/drivers/mxc/dam/Kconfig
@@ -0,0 +1,13 @@
+#
+# DAM API configuration
+#
+
+menu "MXC Digital Audio Multiplexer support"
+
+config MXC_DAM
+	tristate "DAM support"
+	depends on ARCH_MXC
+	---help---
+	  Say Y to get the Digital Audio Multiplexer services API available on MXC platform.
+
+endmenu
diff --git a/drivers/mxc/dam/Makefile b/drivers/mxc/dam/Makefile
new file mode 100644
index 000000000000..b5afdc143dfa
--- /dev/null
+++ b/drivers/mxc/dam/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the kernel Digital Audio MUX (DAM) device driver.
+#
+
+ifeq ($(CONFIG_ARCH_MX27),y)
+	obj-$(CONFIG_MXC_DAM) += dam_v1.o
+else
+	obj-$(CONFIG_MXC_DAM) += dam.o
+endif
diff --git a/drivers/mxc/dam/dam.c b/drivers/mxc/dam/dam.c
new file mode 100644
index 000000000000..532b02f65bb2
--- /dev/null
+++ b/drivers/mxc/dam/dam.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dam.c
+ * @brief This is the brief documentation for this dam.c file.
+ *
+ * This file contains the implementation of the DAM driver main services
+ *
+ * @ingroup DAM
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include "dam.h"
+
+/*!
+ * This include to define bool type, false and true definitions.
+ */
+#include <mach/hardware.h>
+
+#define ModifyRegister32(a,b,c)	(c = ( ( (c)&(~(a)) ) | (b) ))
+
+#define DAM_VIRT_BASE_ADDR	IO_ADDRESS(AUDMUX_BASE_ADDR)
+
+#ifndef _reg_DAM_PTCR1
+#define    _reg_DAM_PTCR1   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x00)))
+#endif
+
+#ifndef _reg_DAM_PDCR1
+#define    _reg_DAM_PDCR1  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x04)))
+#endif
+
+#ifndef _reg_DAM_PTCR2
+#define    _reg_DAM_PTCR2   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x08)))
+#endif
+
+#ifndef _reg_DAM_PDCR2
+#define    _reg_DAM_PDCR2  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x0C)))
+#endif
+
+#ifndef _reg_DAM_PTCR3
+#define    _reg_DAM_PTCR3   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x10)))
+#endif
+
+#ifndef _reg_DAM_PDCR3
+#define    _reg_DAM_PDCR3  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x14)))
+#endif
+
+#ifndef _reg_DAM_PTCR4
+#define    _reg_DAM_PTCR4   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x18)))
+#endif
+
+#ifndef _reg_DAM_PDCR4
+#define    _reg_DAM_PDCR4  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x1C)))
+#endif
+
+#ifndef _reg_DAM_PTCR5
+#define    _reg_DAM_PTCR5   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x20)))
+#endif
+
+#ifndef _reg_DAM_PDCR5
+#define    _reg_DAM_PDCR5  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x24)))
+#endif
+
+#ifndef _reg_DAM_PTCR6
+#define    _reg_DAM_PTCR6   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x28)))
+#endif
+
+#ifndef _reg_DAM_PDCR6
+#define    _reg_DAM_PDCR6  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x2C)))
+#endif
+
+#ifndef _reg_DAM_PTCR7
+#define    _reg_DAM_PTCR7   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x30)))
+#endif
+
+#ifndef _reg_DAM_PDCR7
+#define    _reg_DAM_PDCR7  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x34)))
+#endif
+
+#ifndef _reg_DAM_CNMCR
+#define    _reg_DAM_CNMCR   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x38)))
+#endif
+
+#ifndef _reg_DAM_PTCR
+#define    _reg_DAM_PTCR(a)   (*((volatile unsigned long *) \
+                              (DAM_VIRT_BASE_ADDR + a*8)))
+#endif
+
+#ifndef _reg_DAM_PDCR
+#define    _reg_DAM_PDCR(a)   (*((volatile unsigned long *) \
+                              (DAM_VIRT_BASE_ADDR + 4 + a*8)))
+#endif
+
+/*!
+ * PTCR Registers bit shift definitions
+ */
+#define dam_synchronous_mode_shift               11
+#define dam_receive_clock_select_shift           12
+#define dam_receive_clock_direction_shift        16
+#define dam_receive_frame_sync_select_shift      17
+#define dam_receive_frame_sync_direction_shift   21
+#define dam_transmit_clock_select_shift          22
+#define dam_transmit_clock_direction_shift       26
+#define dam_transmit_frame_sync_select_shift     27
+#define dam_transmit_frame_sync_direction_shift  31
+#define dam_selection_mask                      0xF
+
+/*!
+ * HPDCR Register bit shift definitions
+ */
+#define dam_internal_network_mode_shift           0
+#define dam_mode_shift                            8
+#define dam_transmit_receive_switch_shift        12
+#define dam_receive_data_select_shift            13
+
+/*!
+ * HPDCR Register bit masq definitions
+ */
+#define dam_mode_masq                          0x03
+#define dam_internal_network_mode_mask         0xFF
+
+/*!
+ * CNMCR Register bit shift definitions
+ */
+#define dam_ce_bus_port_cntlow_shift              0
+#define dam_ce_bus_port_cnthigh_shift             8
+#define dam_ce_bus_port_clkpol_shift             16
+#define dam_ce_bus_port_fspol_shift              17
+#define dam_ce_bus_port_enable_shift             18
+
+#define DAM_NAME   "dam"
+
+EXPORT_SYMBOL(dam_select_mode);
+EXPORT_SYMBOL(dam_select_RxClk_direction);
+EXPORT_SYMBOL(dam_select_RxClk_source);
+EXPORT_SYMBOL(dam_select_RxD_source);
+EXPORT_SYMBOL(dam_select_RxFS_direction);
+EXPORT_SYMBOL(dam_select_RxFS_source);
+EXPORT_SYMBOL(dam_select_TxClk_direction);
+EXPORT_SYMBOL(dam_select_TxClk_source);
+EXPORT_SYMBOL(dam_select_TxFS_direction);
+EXPORT_SYMBOL(dam_select_TxFS_source);
+EXPORT_SYMBOL(dam_set_internal_network_mode_mask);
+EXPORT_SYMBOL(dam_set_synchronous);
+EXPORT_SYMBOL(dam_switch_Tx_Rx);
+EXPORT_SYMBOL(dam_reset_register);
+
+/*!
+ * This function selects the operation mode of the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        the_mode          the operation mode of the port
+ *
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_select_mode(dam_port port, dam_mode the_mode)
+{
+	int result;
+	result = 0;
+
+	ModifyRegister32(dam_mode_masq << dam_mode_shift,
+			 the_mode << dam_mode_shift, _reg_DAM_PDCR(port));
+
+	return result;
+}
+
+/*!
+ * This function controls Receive clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx clock signal direction
+ */
+void dam_select_RxClk_direction(dam_port port, signal_direction direction)
+{
+	ModifyRegister32(1 << dam_receive_clock_direction_shift,
+			 direction << dam_receive_clock_direction_shift,
+			 _reg_DAM_PTCR(port));
+}
+
+/*!
+ * This function controls Receive clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxClk_source(dam_port p_config,
+			     bool from_RxClk, dam_port p_source)
+{
+	ModifyRegister32(dam_selection_mask << dam_receive_clock_select_shift,
+			 ((from_RxClk << 3) | p_source) <<
+			 dam_receive_clock_select_shift,
+			 _reg_DAM_PTCR(p_config));
+}
+
+/*!
+ * This function selects the source port for the RxD data.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        p_source          the source port
+ */
+void dam_select_RxD_source(dam_port p_config, dam_port p_source)
+{
+	ModifyRegister32(dam_selection_mask << dam_receive_data_select_shift,
+			 p_source << dam_receive_data_select_shift,
+			 _reg_DAM_PDCR(p_config));
+}
+
+/*!
+ * This function controls Receive Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx Frame Sync signal direction
+ */
+void dam_select_RxFS_direction(dam_port port, signal_direction direction)
+{
+	ModifyRegister32(1 << dam_receive_frame_sync_direction_shift,
+			 direction << dam_receive_frame_sync_direction_shift,
+			 _reg_DAM_PTCR(port));
+}
+
+/*!
+ * This function controls Receive Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxFS_source(dam_port p_config,
+			    bool from_RxFS, dam_port p_source)
+{
+	ModifyRegister32(dam_selection_mask <<
+			 dam_receive_frame_sync_select_shift,
+			 ((from_RxFS << 3) | p_source) <<
+			 dam_receive_frame_sync_select_shift,
+			 _reg_DAM_PTCR(p_config));
+}
+
+/*!
+ * This function controls Transmit clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx clock signal direction
+ */
+void dam_select_TxClk_direction(dam_port port, signal_direction direction)
+{
+	ModifyRegister32(1 << dam_transmit_clock_direction_shift,
+			 direction << dam_transmit_clock_direction_shift,
+			 _reg_DAM_PTCR(port));
+}
+
+/*!
+ * This function controls Transmit clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxClk_source(dam_port p_config,
+			     bool from_RxClk, dam_port p_source)
+{
+	ModifyRegister32(dam_selection_mask << dam_transmit_clock_select_shift,
+			 ((from_RxClk << 3) | p_source) <<
+			 dam_transmit_clock_select_shift,
+			 _reg_DAM_PTCR(p_config));
+}
+
+/*!
+ * This function controls Transmit Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx Frame Sync signal direction
+ */
+void dam_select_TxFS_direction(dam_port port, signal_direction direction)
+{
+	ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift,
+			 direction << dam_transmit_frame_sync_direction_shift,
+			 _reg_DAM_PTCR(port));
+}
+
+/*!
+ * This function controls Transmit Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxFS_source(dam_port p_config,
+			    bool from_RxFS, dam_port p_source)
+{
+	ModifyRegister32(dam_selection_mask <<
+			 dam_transmit_frame_sync_select_shift,
+			 ((from_RxFS << 3) | p_source) <<
+			 dam_transmit_frame_sync_select_shift,
+			 _reg_DAM_PTCR(p_config));
+}
+
+/*!
+ * This function sets a bit mask that selects the port from which of the RxD
+ * signals are to be ANDed together for internal network mode.
+ * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1.
+ * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing.
+ *
+ * @param        port              the DAM port to configure
+ * @param        bit_mask          the bit mask
+ *
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask)
+{
+	int result;
+	result = 0;
+
+	ModifyRegister32(dam_internal_network_mode_mask <<
+			 dam_internal_network_mode_shift,
+			 bit_mask << dam_internal_network_mode_shift,
+			 _reg_DAM_PDCR(port));
+
+	return result;
+}
+
+/*!
+ * This function controls whether or not the port is in synchronous mode.
+ * When the synchronous mode is selected, the receive and the transmit sections
+ * use common clock and frame sync signals.
+ * When the synchronous mode is not selected, separate clock and frame sync
+ * signals are used for the transmit and the receive sections.
+ * The defaut value is the synchronous mode selected.
+ *
+ * @param        port              the DAM port to configure
+ * @param        synchronous       the state to assign
+ */
+void dam_set_synchronous(dam_port port, bool synchronous)
+{
+	ModifyRegister32(1 << dam_synchronous_mode_shift,
+			 synchronous << dam_synchronous_mode_shift,
+			 _reg_DAM_PTCR(port));
+}
+
+/*!
+ * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD)
+ * to (Da-RxD, Db-TxD).
+ * This default signal configuration is Da-TxD, Db-RxD.
+ *
+ * @param        port              the DAM port to configure
+ * @param        value             the switch state
+ */
+void dam_switch_Tx_Rx(dam_port port, bool value)
+{
+	ModifyRegister32(1 << dam_transmit_receive_switch_shift,
+			 value << dam_transmit_receive_switch_shift,
+			 _reg_DAM_PDCR(port));
+}
+
+/*!
+ * This function resets the two registers of the selected port.
+ *
+ * @param        port              the DAM port to reset
+ */
+void dam_reset_register(dam_port port)
+{
+	ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PTCR(port));
+	ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PDCR(port));
+}
+
+/*!
+ * This function implements the init function of the DAM device.
+ * This function is called when the module is loaded.
+ *
+ * @return       This function returns 0.
+ */
+static int __init dam_init(void)
+{
+	return 0;
+}
+
+/*!
+ * This function implements the exit function of the SPI device.
+ * This function is called when the module is unloaded.
+ *
+ */
+static void __exit dam_exit(void)
+{
+}
+
+module_init(dam_init);
+module_exit(dam_exit);
+
+MODULE_DESCRIPTION("DAM char device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/dam/dam.h b/drivers/mxc/dam/dam.h
new file mode 100644
index 000000000000..cb9ead53f689
--- /dev/null
+++ b/drivers/mxc/dam/dam.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+ /*!
+  * @defgroup DAM Digital Audio Multiplexer (AUDMUX) Driver
+  */
+
+ /*!
+  * @file dam.h
+  * @brief This is the brief documentation for this dam.h file.
+  *
+  * This header file contains DAM driver functions prototypes.
+  *
+  * @ingroup DAM
+  */
+
+#ifndef __MXC_DAM_H__
+#define __MXC_DAM_H__
+
+/*!
+ * This enumeration describes the Digital Audio Multiplexer mode.
+ */
+typedef enum {
+
+	/*!
+	 * Normal mode
+	 */
+	normal_mode = 0,
+
+	/*!
+	 * Internal network mode
+	 */
+	internal_network_mode = 1,
+
+	/*!
+	 * CE bus network mode
+	 */
+	CE_bus_network_mode = 2
+} dam_mode;
+
+/*!
+ * This enumeration describes the port.
+ */
+typedef enum {
+
+	/*!
+	 * The port 1
+	 */
+	port_1 = 0,
+
+	/*!
+	 * The port 2
+	 */
+	port_2 = 1,
+
+	/*!
+	 * The port 3
+	 */
+	port_3 = 2,
+
+	/*!
+	 * The port 4
+	 */
+	port_4 = 3,
+
+	/*!
+	 * The port 5
+	 */
+	port_5 = 4,
+
+	/*!
+	 * The port 6
+	 */
+	port_6 = 5,
+
+	/*!
+	 * The port 7
+	 */
+	port_7 = 6
+} dam_port;
+
+/*!
+ * This enumeration describes the signal direction.
+ */
+typedef enum {
+
+	/*!
+	 * Signal In
+	 */
+	signal_in = 0,
+
+	/*!
+	 * Signal Out
+	 */
+	signal_out = 1
+} signal_direction;
+
+/*!
+ * Test purpose definition
+ */
+#define TEST_DAM 1
+
+#ifdef TEST_DAM
+
+#define DAM_IOCTL 0x55
+#define DAM_CONFIG_SSI1_MC13783 _IOWR(DAM_IOCTL, 1, int)
+#define DAM_CONFIG_SSI2_MC13783 _IOWR(DAM_IOCTL, 2, int)
+#define DAM_CONFIG_SSI_NETWORK_MODE_MC13783 _IOWR(DAM_IOCTL, 3, int)
+#endif
+
+/*!
+ * This function selects the operation mode of the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        the_mode          the operation mode of the port
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_select_mode(dam_port port, dam_mode the_mode);
+
+/*!
+ * This function controls Receive clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx clock signal direction
+ */
+void dam_select_RxClk_direction(dam_port port, signal_direction direction);
+
+/*!
+ * This function controls Receive clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxClk_source(dam_port p_config, bool from_RxClk,
+			     dam_port p_source);
+
+/*!
+ * This function selects the source port for the RxD data.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        p_source          the source port
+ */
+void dam_select_RxD_source(dam_port p_config, dam_port p_source);
+
+/*!
+ * This function controls Receive Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx Frame Sync signal direction
+ */
+void dam_select_RxFS_direction(dam_port port, signal_direction direction);
+
+/*!
+ * This function controls Receive Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxFS_source(dam_port p_config, bool from_RxFS,
+			    dam_port p_source);
+
+/*!
+ * This function controls Transmit clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx clock signal direction
+ */
+void dam_select_TxClk_direction(dam_port port, signal_direction direction);
+
+/*!
+ * This function controls Transmit clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxClk_source(dam_port p_config, bool from_RxClk,
+			     dam_port p_source);
+
+/*!
+ * This function controls Transmit Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx Frame Sync signal direction
+ */
+void dam_select_TxFS_direction(dam_port port, signal_direction direction);
+
+/*!
+ * This function controls Transmit Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxFS_source(dam_port p_config, bool from_RxFS,
+			    dam_port p_source);
+
+/*!
+ * This function sets a bit mask that selects the port from which of
+ * the RxD signals are to be ANDed together for internal network mode.
+ * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1.
+ * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing.
+ *
+ * @param        port              the DAM port to configure
+ * @param        bit_mask          the bit mask
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask);
+
+/*!
+ * This function controls whether or not the port is in synchronous mode.
+ * When the synchronous mode is selected, the receive and the transmit sections
+ * use common clock and frame sync signals.
+ * When the synchronous mode is not selected, separate clock and frame sync
+ * signals are used for the transmit and the receive sections.
+ * The defaut value is the synchronous mode selected.
+ *
+ * @param        port              the DAM port to configure
+ * @param        synchronous       the state to assign
+ */
+void dam_set_synchronous(dam_port port, bool synchronous);
+
+/*!
+ * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) to
+ * (Da-RxD, Db-TxD).
+ * This default signal configuration is Da-TxD, Db-RxD.
+ *
+ * @param        port              the DAM port to configure
+ * @param        value             the switch state
+ */
+void dam_switch_Tx_Rx(dam_port port, bool value);
+
+/*!
+ * This function resets the two registers of the selected port.
+ *
+ * @param        port              the DAM port to reset
+ */
+void dam_reset_register(dam_port port);
+
+#endif
diff --git a/drivers/mxc/dam/dam_v1.c b/drivers/mxc/dam/dam_v1.c
new file mode 100644
index 000000000000..0fc88bb98a38
--- /dev/null
+++ b/drivers/mxc/dam/dam_v1.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dam_v1.c
+ * @brief This is the brief documentation for this dam_v1.c file.
+ *
+ * This file contains the implementation of the DAM driver main services
+ *
+ * @ingroup DAM
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <asm/uaccess.h>
+#include "dam.h"
+
+/*!
+ * This include to define bool type, false and true definitions.
+ */
+#include <mach/hardware.h>
+
+#define DAM_VIRT_BASE_ADDR	IO_ADDRESS(AUDMUX_BASE_ADDR)
+
+#define ModifyRegister32(a,b,c)	do{\
+	__raw_writel( ((__raw_readl(c)) & (~(a))) | (b),(c) );\
+}while(0)
+
+#ifndef _reg_DAM_HPCR1
+#define    _reg_DAM_HPCR1   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x00)))
+#endif
+
+#ifndef _reg_DAM_HPCR2
+#define    _reg_DAM_HPCR2   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x04)))
+#endif
+
+#ifndef _reg_DAM_HPCR3
+#define    _reg_DAM_HPCR3   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x08)))
+#endif
+
+#ifndef _reg_DAM_PPCR1
+#define    _reg_DAM_PPCR1   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x10)))
+#endif
+
+#ifndef _reg_DAM_PPCR2
+#define    _reg_DAM_PPCR2  (*((volatile unsigned long *) \
+                           (DAM_VIRT_BASE_ADDR + 0x14)))
+#endif
+
+#ifndef _reg_DAM_PPCR3
+#define    _reg_DAM_PPCR3   (*((volatile unsigned long *) \
+                            (DAM_VIRT_BASE_ADDR + 0x1c)))
+#endif
+
+#ifndef _reg_DAM_HPCR
+#define    _reg_DAM_HPCR(a)   ((volatile unsigned long *) \
+                              (DAM_VIRT_BASE_ADDR + (a)*4))
+#endif
+
+#ifndef _reg_DAM_PPCR
+#define    _reg_DAM_PPCR(a)   ((volatile unsigned long *) \
+                              (DAM_VIRT_BASE_ADDR + 0x0c + (0x04 << (a-3)) ))
+#endif
+
+/*!
+ * HPCR/PPCR Registers bit shift definitions
+ */
+#define dam_transmit_frame_sync_direction_shift  31
+#define dam_transmit_clock_direction_shift       30
+#define dam_transmit_frame_sync_select_shift     26
+#define dam_transmit_clock_select_shift          26
+#define dam_receive_frame_sync_direction_shift   25
+#define dam_receive_clock_direction_shift        24
+#define dam_receive_clock_select_shift           20
+#define dam_receive_frame_sync_select_shift      20
+
+#define dam_receive_data_select_shift            13
+#define dam_synchronous_mode_shift               12
+
+#define dam_transmit_receive_switch_shift        10
+
+#define dam_mode_shift                            8
+#define dam_internal_network_mode_shift           0
+
+/*!
+ * HPCR/PPCR Register bit masq definitions
+ */
+//#define dam_selection_mask              0xF
+#define dam_fs_selection_mask             0xF
+#define dam_clk_selection_mask            0xF
+#define dam_dat_selection_mask		        0x7
+//#define dam_mode_masq                   0x03
+#define dam_internal_network_mode_mask    0xFF
+
+/*!
+ * HPCR/PPCR Register reset value definitions
+ */
+#define dam_hpcr_default_value 0x00001000
+#define dam_ppcr_default_value 0x00001000
+
+#define DAM_NAME   "dam"
+static struct class *mxc_dam_class;
+
+EXPORT_SYMBOL(dam_select_mode);
+EXPORT_SYMBOL(dam_select_RxClk_direction);
+EXPORT_SYMBOL(dam_select_RxClk_source);
+EXPORT_SYMBOL(dam_select_RxD_source);
+EXPORT_SYMBOL(dam_select_RxFS_direction);
+EXPORT_SYMBOL(dam_select_RxFS_source);
+EXPORT_SYMBOL(dam_select_TxClk_direction);
+EXPORT_SYMBOL(dam_select_TxClk_source);
+EXPORT_SYMBOL(dam_select_TxFS_direction);
+EXPORT_SYMBOL(dam_select_TxFS_source);
+EXPORT_SYMBOL(dam_set_internal_network_mode_mask);
+EXPORT_SYMBOL(dam_set_synchronous);
+EXPORT_SYMBOL(dam_switch_Tx_Rx);
+EXPORT_SYMBOL(dam_reset_register);
+
+/*!
+ * DAM major
+ */
+#ifdef TEST_DAM
+static int major_dam;
+
+typedef struct _mxc_cfg {
+	int reg;
+	int val;
+} mxc_cfg;
+
+#endif
+
+/*!
+ * This function selects the operation mode of the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        the_mode          the operation mode of the port
+ *
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_select_mode(dam_port port, dam_mode the_mode)
+{
+	int result;
+	result = 0;
+
+	if (port >= 3)
+		the_mode = normal_mode;
+	ModifyRegister32(1 << dam_mode_shift,
+			 the_mode << dam_mode_shift, _reg_DAM_HPCR(port));
+
+	return result;
+}
+
+/*!
+ * This function controls Receive clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx clock signal direction
+ */
+void dam_select_RxClk_direction(dam_port port, signal_direction direction)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_receive_clock_direction_shift,
+				 direction << dam_receive_clock_direction_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_receive_clock_direction_shift,
+				 direction << dam_receive_clock_direction_shift,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function controls Receive clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxClk_source(dam_port p_config,
+			     bool from_RxClk, dam_port p_source)
+{
+	if (p_config < 3) {
+		ModifyRegister32(dam_clk_selection_mask <<
+				 dam_receive_clock_select_shift,
+				 ((from_RxClk << 3) | p_source) <<
+				 dam_receive_clock_select_shift,
+				 _reg_DAM_HPCR(p_config));
+	} else {
+		ModifyRegister32(dam_clk_selection_mask <<
+				 dam_receive_clock_select_shift,
+				 ((from_RxClk << 3) | p_source) <<
+				 dam_receive_clock_select_shift,
+				 _reg_DAM_PPCR(p_config));
+	}
+	return;
+}
+
+/*!
+ * This function selects the source port for the RxD data.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        p_source          the source port
+ */
+void dam_select_RxD_source(dam_port p_config, dam_port p_source)
+{
+	if (p_config < 3) {
+		ModifyRegister32(dam_dat_selection_mask <<
+				 dam_receive_data_select_shift,
+				 p_source << dam_receive_data_select_shift,
+				 _reg_DAM_HPCR(p_config));
+	} else {
+		ModifyRegister32(dam_dat_selection_mask <<
+				 dam_receive_data_select_shift,
+				 p_source << dam_receive_data_select_shift,
+				 _reg_DAM_PPCR(p_config));
+	}
+	return;
+}
+
+/*!
+ * This function controls Receive Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Rx Frame Sync signal direction
+ */
+void dam_select_RxFS_direction(dam_port port, signal_direction direction)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_receive_frame_sync_direction_shift,
+				 direction <<
+				 dam_receive_frame_sync_direction_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_receive_frame_sync_direction_shift,
+				 direction <<
+				 dam_receive_frame_sync_direction_shift,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function controls Receive Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_RxFS_source(dam_port p_config,
+			    bool from_RxFS, dam_port p_source)
+{
+	if (p_config < 3) {
+		ModifyRegister32(dam_fs_selection_mask <<
+				 dam_receive_frame_sync_select_shift,
+				 ((from_RxFS << 3) | p_source) <<
+				 dam_receive_frame_sync_select_shift,
+				 _reg_DAM_HPCR(p_config));
+	} else {
+		ModifyRegister32(dam_fs_selection_mask <<
+				 dam_receive_frame_sync_select_shift,
+				 ((from_RxFS << 3) | p_source) <<
+				 dam_receive_frame_sync_select_shift,
+				 _reg_DAM_PPCR(p_config));
+	}
+	return;
+}
+
+/*!
+ * This function controls Transmit clock signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx clock signal direction
+ */
+void dam_select_TxClk_direction(dam_port port, signal_direction direction)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_transmit_clock_direction_shift,
+				 direction <<
+				 dam_transmit_clock_direction_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_transmit_clock_direction_shift,
+				 direction <<
+				 dam_transmit_clock_direction_shift,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function controls Transmit clock signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxClk        the signal comes from RxClk or TxClk of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxClk_source(dam_port p_config,
+			     bool from_RxClk, dam_port p_source)
+{
+	if (p_config < 3) {
+		ModifyRegister32(dam_clk_selection_mask <<
+				 dam_transmit_clock_select_shift,
+				 ((from_RxClk << 3) | p_source) <<
+				 dam_transmit_clock_select_shift,
+				 _reg_DAM_HPCR(p_config));
+	} else {
+		ModifyRegister32(dam_clk_selection_mask <<
+				 dam_transmit_clock_select_shift,
+				 ((from_RxClk << 3) | p_source) <<
+				 dam_transmit_clock_select_shift,
+				 _reg_DAM_PPCR(p_config));
+	}
+	return;
+}
+
+/*!
+ * This function controls Transmit Frame Sync signal direction for the port.
+ *
+ * @param        port              the DAM port to configure
+ * @param        direction         the Tx Frame Sync signal direction
+ */
+void dam_select_TxFS_direction(dam_port port, signal_direction direction)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift,
+				 direction <<
+				 dam_transmit_frame_sync_direction_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift,
+				 direction <<
+				 dam_transmit_frame_sync_direction_shift,
+				 _reg_DAM_HPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function controls Transmit Frame Sync signal source for the port.
+ *
+ * @param        p_config          the DAM port to configure
+ * @param        from_RxFS         the signal comes from RxFS or TxFS of
+ *                                 the source port
+ * @param        p_source          the source port
+ */
+void dam_select_TxFS_source(dam_port p_config,
+			    bool from_RxFS, dam_port p_source)
+{
+	if (p_config < 3) {
+		ModifyRegister32(dam_fs_selection_mask <<
+				 dam_transmit_frame_sync_select_shift,
+				 ((from_RxFS << 3) | p_source) <<
+				 dam_transmit_frame_sync_select_shift,
+				 _reg_DAM_HPCR(p_config));
+	} else {
+		ModifyRegister32(dam_fs_selection_mask <<
+				 dam_transmit_frame_sync_select_shift,
+				 ((from_RxFS << 3) | p_source) <<
+				 dam_transmit_frame_sync_select_shift,
+				 _reg_DAM_PPCR(p_config));
+	}
+	return;
+}
+
+/*!
+ * This function sets a bit mask that selects the port from which of the RxD
+ * signals are to be ANDed together for internal network mode.
+ * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1.
+ * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing.
+ *
+ * @param        port              the DAM port to configure
+ * @param        bit_mask          the bit mask
+ *
+ * @return       This function returns the result of the operation
+ *               (0 if successful, -1 otherwise).
+ */
+int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask)
+{
+	int result;
+	result = 0;
+
+	ModifyRegister32(dam_internal_network_mode_mask <<
+			 dam_internal_network_mode_shift,
+			 bit_mask << dam_internal_network_mode_shift,
+			 _reg_DAM_HPCR(port));
+	return result;
+}
+
+/*!
+ * This function controls whether or not the port is in synchronous mode.
+ * When the synchronous mode is selected, the receive and the transmit sections
+ * use common clock and frame sync signals.
+ * When the synchronous mode is not selected, separate clock and frame sync
+ * signals are used for the transmit and the receive sections.
+ * The defaut value is the synchronous mode selected.
+ *
+ * @param        port              the DAM port to configure
+ * @param        synchronous       the state to assign
+ */
+void dam_set_synchronous(dam_port port, bool synchronous)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_synchronous_mode_shift,
+				 synchronous << dam_synchronous_mode_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_synchronous_mode_shift,
+				 synchronous << dam_synchronous_mode_shift,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD)
+ * to (Da-RxD, Db-TxD).
+ * This default signal configuration is Da-TxD, Db-RxD.
+ *
+ * @param        port              the DAM port to configure
+ * @param        value             the switch state
+ */
+void dam_switch_Tx_Rx(dam_port port, bool value)
+{
+	if (port < 3) {
+		ModifyRegister32(1 << dam_transmit_receive_switch_shift,
+				 value << dam_transmit_receive_switch_shift,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(1 << dam_transmit_receive_switch_shift,
+				 value << dam_transmit_receive_switch_shift,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+/*!
+ * This function resets the two registers of the selected port.
+ *
+ * @param        port              the DAM port to reset
+ */
+void dam_reset_register(dam_port port)
+{
+	if (port < 3) {
+		ModifyRegister32(0xFFFFFFFF, dam_hpcr_default_value,
+				 _reg_DAM_HPCR(port));
+	} else {
+		ModifyRegister32(0xFFFFFFFF, dam_ppcr_default_value,
+				 _reg_DAM_PPCR(port));
+	}
+	return;
+}
+
+#ifdef TEST_DAM
+
+/*!
+ * This function implements IOCTL controls on a DAM device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter :\n
+ * DAM_CONFIG_SSI1:\n
+ * data from port 1 to port 4, clock and FS from port 1 (SSI1)\n
+ * DAM_CONFIG_SSI2:\n
+ * data from port 2 to port 5, clock and FS from port 2 (SSI2)\n
+ * DAM_CONFIG_SSI_NETWORK_MODE:\n
+ * network mode for mix digital with data from port 1 to port4,\n
+ * data from port 2 to port 4, clock and FS from port 1 (SSI1)
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int dam_ioctl(struct inode *inode,
+		     struct file *file, unsigned int cmd, unsigned long arg)
+{
+	return 0;
+}
+
+/*!
+ * This function implements the open method on a DAM device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ *
+ * @return       This function returns 0.
+ */
+static int dam_open(struct inode *inode, struct file *file)
+{
+	/* DBG_PRINTK("ssi : dam_open()\n"); */
+	return 0;
+}
+
+/*!
+ * This function implements the release method on a DAM device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ *
+ * @return       This function returns 0.
+ */
+static int dam_free(struct inode *inode, struct file *file)
+{
+	/* DBG_PRINTK("ssi : dam_free()\n"); */
+	return 0;
+}
+
+/*!
+ * This structure defines file operations for a DAM device.
+ */
+static struct file_operations dam_fops = {
+
+	/*!
+	 * the owner
+	 */
+	.owner = THIS_MODULE,
+
+	/*!
+	 * the ioctl operation
+	 */
+	.ioctl = dam_ioctl,
+
+	/*!
+	 * the open operation
+	 */
+	.open = dam_open,
+
+	/*!
+	 * the release operation
+	 */
+	.release = dam_free,
+};
+
+#endif
+
+/*!
+ * This function implements the init function of the DAM device.
+ * This function is called when the module is loaded.
+ *
+ * @return       This function returns 0.
+ */
+static int __init dam_init(void)
+{
+#ifdef TEST_DAM
+	struct device *temp_class;
+	printk(KERN_DEBUG "dam : dam_init(void) \n");
+
+	major_dam = register_chrdev(0, DAM_NAME, &dam_fops);
+	if (major_dam < 0) {
+		printk(KERN_WARNING "Unable to get a major for dam");
+		return major_dam;
+	}
+
+	mxc_dam_class = class_create(THIS_MODULE, DAM_NAME);
+	if (IS_ERR(mxc_dam_class)) {
+		goto err_out;
+	}
+
+	temp_class = device_create(mxc_dam_class, NULL,
+				   MKDEV(major_dam, 0), NULL, DAM_NAME);
+	if (IS_ERR(temp_class)) {
+		goto err_out;
+	}
+#endif
+	return 0;
+
+      err_out:
+	printk(KERN_ERR "Error creating dam class device.\n");
+	device_destroy(mxc_dam_class, MKDEV(major_dam, 0));
+	class_destroy(mxc_dam_class);
+	unregister_chrdev(major_dam, DAM_NAME);
+	return -1;
+}
+
+/*!
+ * This function implements the exit function of the SPI device.
+ * This function is called when the module is unloaded.
+ *
+ */
+static void __exit dam_exit(void)
+{
+#ifdef TEST_DAM
+	device_destroy(mxc_dam_class, MKDEV(major_dam, 0));
+	class_destroy(mxc_dam_class);
+	unregister_chrdev(major_dam, DAM_NAME);
+	printk(KERN_DEBUG "dam : successfully unloaded\n");
+#endif
+}
+
+module_init(dam_init);
+module_exit(dam_exit);
+
+MODULE_DESCRIPTION("DAM char device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/gps_ioctrl/Kconfig b/drivers/mxc/gps_ioctrl/Kconfig
new file mode 100644
index 000000000000..0a85d1636dd7
--- /dev/null
+++ b/drivers/mxc/gps_ioctrl/Kconfig
@@ -0,0 +1,13 @@
+#
+# BROADCOM GPS configuration
+#
+
+menu "Broadcom GPS ioctrl support"
+
+config GPS_IOCTRL
+	tristate "GPS ioctrl support"
+	depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS
+	---help---
+	  Say Y to enable Broadcom GPS ioctrl on MXC platform.
+
+endmenu
diff --git a/drivers/mxc/gps_ioctrl/Makefile b/drivers/mxc/gps_ioctrl/Makefile
new file mode 100644
index 000000000000..c52d7c9f151c
--- /dev/null
+++ b/drivers/mxc/gps_ioctrl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the GPIO device driver module.
+#
+obj-$(CONFIG_GPS_IOCTRL) 	+= gps_gpiodrv.o
+gps_gpiodrv-objs := agpsgpiodev.o
diff --git a/drivers/mxc/gps_ioctrl/agpsgpiodev.c b/drivers/mxc/gps_ioctrl/agpsgpiodev.c
new file mode 100644
index 000000000000..2f64274bf37c
--- /dev/null
+++ b/drivers/mxc/gps_ioctrl/agpsgpiodev.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file agpsgpiodev.c
+ *
+ * @brief Main file for GPIO kernel module. Contains driver entry/exit
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>		/* Async notification */
+#include <linux/uaccess.h>	/* for get_user, put_user, access_ok */
+#include <linux/sched.h>	/* jiffies */
+#include <linux/poll.h>
+#include <linux/device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/cdev.h>
+#include <mach/hardware.h>
+#include "agpsgpiodev.h"
+
+extern void gpio_gps_active(void);
+extern void gpio_gps_inactive(void);
+extern int gpio_gps_access(int para);
+
+struct mxc_gps_platform_data *mxc_gps_ioctrl_data;
+static int Device_Open;		/* Only allow a single user of this device */
+static struct cdev mxc_gps_cdev;
+static dev_t agps_gpio_dev;
+static struct class *gps_class;
+static struct device *gps_class_dev;
+
+/* Write GPIO from user space */
+static int ioctl_writegpio(int arg)
+{
+
+	/* Bit 0 of arg identifies the GPIO pin to write:
+	   0 = GPS_RESET_GPIO, 1 = GPS_POWER_GPIO.
+	   Bit 1 of arg identifies the value to write (0 or 1). */
+
+	/* Bit 2 should be 0 to show this access is write */
+	return gpio_gps_access(arg & (~0x4));
+}
+
+/* Read GPIO from user space */
+static int ioctl_readgpio(int arg)
+{
+	/* Bit 0 of arg identifies the GPIO pin to read:
+	   0 = GPS_RESET_GPIO. 1 = GPS_POWER_GPIO
+	   Bit 2 should be 1 to show this access is read */
+	return gpio_gps_access(arg | 0x4);
+}
+
+static int device_open(struct inode *inode, struct file *fp)
+{
+	/* We don't want to talk to two processes at the same time. */
+	if (Device_Open) {
+		printk(KERN_DEBUG "device_open() - Returning EBUSY. \
+			Device already open... \n");
+		return -EBUSY;
+	}
+	Device_Open++;		/* BUGBUG : Not protected! */
+	try_module_get(THIS_MODULE);
+
+	return 0;
+}
+
+static int device_release(struct inode *inode, struct file *fp)
+{
+	/* We're now ready for our next caller */
+	Device_Open--;
+	module_put(THIS_MODULE);
+
+	return 0;
+}
+
+static int device_ioctl(struct inode *inode, struct file *fp,
+			unsigned int cmd, unsigned long arg)
+{
+	int err = 0;
+
+	/* Extract the type and number bitfields, and don't decode wrong cmds.
+	   Return ENOTTY (inappropriate ioctl) before access_ok() */
+	if (_IOC_TYPE(cmd) != MAJOR_NUM) {
+		printk(KERN_ERR
+		       "device_ioctl() - Error! IOC_TYPE = %d. Expected %d\n",
+		       _IOC_TYPE(cmd), MAJOR_NUM);
+		return -ENOTTY;
+	}
+	if (_IOC_NR(cmd) > IOCTL_MAXNUMBER) {
+		printk(KERN_ERR
+		       "device_ioctl() - Error!"
+		       "IOC_NR = %d greater than max supported(%d)\n",
+		       _IOC_NR(cmd), IOCTL_MAXNUMBER);
+		return -ENOTTY;
+	}
+
+	/* The direction is a bitmask, and VERIFY_WRITE catches R/W transfers.
+	   `Type' is user-oriented, while access_ok is kernel-oriented, so the
+	   concept of "read" and "write" is reversed. I think this is primarily
+	   for good coding practice. You can easily do any kind of R/W access
+	   without these checks and IOCTL code can be implemented "randomly"! */
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		err =
+		    !access_ok(VERIFY_WRITE, (void __user *)arg,
+			       _IOC_SIZE(cmd));
+
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		err =
+		    !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd));
+	if (err) {
+		printk(KERN_ERR
+		       "device_ioctl() - Error! User arg not valid"
+		       "for selected access (R/W/RW). Cmd %d\n",
+		       _IOC_TYPE(cmd));
+		return -EFAULT;
+	}
+
+	/* Note: Read and writing data to user buffer can be done using regular
+	   pointer stuff but we may also use get_user() or put_user() */
+
+	/* Cmd and arg has been verified... */
+	switch (cmd) {
+	case IOCTL_WRITEGPIO:
+		return ioctl_writegpio((int)arg);
+	case IOCTL_READGPIO:
+		return ioctl_readgpio((int)arg);
+	default:
+		printk(KERN_ERR "device_ioctl() - Invalid IOCTL (0x%x)\n", cmd);
+		return EINVAL;
+	}
+	return 0;
+}
+
+struct file_operations Fops = {
+	.ioctl = device_ioctl,
+	.open = device_open,
+	.release = device_release,
+};
+
+/* Initialize the module - Register the character device */
+int init_chrdev(struct device *dev)
+{
+	int ret, gps_major;
+
+	ret = alloc_chrdev_region(&agps_gpio_dev, 1, 1,	"agps_gpio");
+	gps_major = MAJOR(agps_gpio_dev);
+	if (ret < 0) {
+		dev_err(dev, "can't get major %d\n", gps_major);
+		goto err3;
+	}
+
+	cdev_init(&mxc_gps_cdev, &Fops);
+	mxc_gps_cdev.owner = THIS_MODULE;
+
+	ret = cdev_add(&mxc_gps_cdev, agps_gpio_dev, 1);
+	if (ret) {
+		dev_err(dev, "can't add cdev\n");
+		goto err2;
+	}
+
+	/* create class and device for udev information */
+	gps_class = class_create(THIS_MODULE, "gps");
+	if (IS_ERR(gps_class)) {
+		dev_err(dev, "failed to create gps class\n");
+		ret = -ENOMEM;
+		goto err1;
+	}
+
+	gps_class_dev = device_create(gps_class, NULL, MKDEV(gps_major, 1), NULL,
+					AGPSGPIO_DEVICE_FILE_NAME);
+	if (IS_ERR(gps_class_dev)) {
+		dev_err(dev, "failed to create gps gpio class device\n");
+		ret = -ENOMEM;
+		goto err0;
+	}
+
+	return 0;
+err0:
+	class_destroy(gps_class);
+err1:
+	cdev_del(&mxc_gps_cdev);
+err2:
+	unregister_chrdev_region(agps_gpio_dev, 1);
+err3:
+	return ret;
+}
+
+/* Cleanup - unregister the appropriate file from /proc. */
+void cleanup_chrdev(void)
+{
+	/* destroy gps device class */
+	device_destroy(gps_class, MKDEV(MAJOR(agps_gpio_dev), 1));
+	class_destroy(gps_class);
+
+	/* Unregister the device */
+	cdev_del(&mxc_gps_cdev);
+	unregister_chrdev_region(agps_gpio_dev, 1);
+}
+
+/*!
+ * This function initializes the driver in terms of memory of the soundcard
+ * and some basic HW clock settings.
+ *
+ * @return              0 on success, -1 otherwise.
+ */
+static int __init gps_ioctrl_probe(struct platform_device *pdev)
+{
+	struct regulator *gps_regu;
+
+	mxc_gps_ioctrl_data =
+	    (struct mxc_gps_platform_data *)pdev->dev.platform_data;
+
+	/* open GPS GPO3 1v8 for GL gps support */
+	if (mxc_gps_ioctrl_data->core_reg != NULL) {
+		mxc_gps_ioctrl_data->gps_regu_core =
+		    regulator_get(&(pdev->dev), mxc_gps_ioctrl_data->core_reg);
+		gps_regu = mxc_gps_ioctrl_data->gps_regu_core;
+		if (!IS_ERR_VALUE((u32)gps_regu)) {
+			regulator_set_voltage(gps_regu, 1800000, 1800000);
+			regulator_enable(gps_regu);
+		} else {
+			return -1;
+		}
+	}
+	/* open GPS GPO1 2v8 for GL gps support */
+	if (mxc_gps_ioctrl_data->analog_reg != NULL) {
+		mxc_gps_ioctrl_data->gps_regu_analog =
+		    regulator_get(&(pdev->dev),
+				  mxc_gps_ioctrl_data->analog_reg);
+		gps_regu = mxc_gps_ioctrl_data->gps_regu_analog;
+		if (!IS_ERR_VALUE((u32)gps_regu)) {
+			regulator_set_voltage(gps_regu, 2800000, 2800000);
+			regulator_enable(gps_regu);
+		} else {
+			return -1;
+		}
+	}
+	gpio_gps_active();
+
+	/* Register character device */
+	init_chrdev(&(pdev->dev));
+	return 0;
+}
+
+static int gps_ioctrl_remove(struct platform_device *pdev)
+{
+	struct regulator *gps_regu;
+
+	mxc_gps_ioctrl_data =
+	    (struct mxc_gps_platform_data *)pdev->dev.platform_data;
+
+	/* Character device cleanup.. */
+	cleanup_chrdev();
+	gpio_gps_inactive();
+
+	/* close GPS GPO3 1v8 for GL gps */
+	gps_regu = mxc_gps_ioctrl_data->gps_regu_core;
+	if (mxc_gps_ioctrl_data->core_reg != NULL) {
+		regulator_disable(gps_regu);
+		regulator_put(gps_regu);
+	}
+	/* close GPS GPO1 2v8 for GL gps */
+	gps_regu = mxc_gps_ioctrl_data->gps_regu_analog;
+	if (mxc_gps_ioctrl_data->analog_reg != NULL) {
+		regulator_disable(gps_regu);
+		regulator_put(gps_regu);
+	}
+
+	return 0;
+}
+
+static int gps_ioctrl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	/* PowerEn toggle off */
+	ioctl_writegpio(0x1);
+	return 0;
+}
+
+static int gps_ioctrl_resume(struct platform_device *pdev)
+{
+	/* PowerEn pull up */
+	ioctl_writegpio(0x3);
+	return 0;
+}
+
+static struct platform_driver gps_ioctrl_driver = {
+	.probe = gps_ioctrl_probe,
+	.remove = gps_ioctrl_remove,
+	.suspend = gps_ioctrl_suspend,
+	.resume = gps_ioctrl_resume,
+	.driver = {
+		   .name = "gps_ioctrl",
+		   },
+};
+
+/*!
+ * Entry point for GPS ioctrl module.
+ *
+ */
+static int __init gps_ioctrl_init(void)
+{
+	return platform_driver_register(&gps_ioctrl_driver);
+}
+
+/*!
+ * unloading module.
+ *
+ */
+static void __exit gps_ioctrl_exit(void)
+{
+	platform_driver_unregister(&gps_ioctrl_driver);
+}
+
+module_init(gps_ioctrl_init);
+module_exit(gps_ioctrl_exit);
+MODULE_DESCRIPTION("GPIO DEVICE DRIVER");
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/gps_ioctrl/agpsgpiodev.h b/drivers/mxc/gps_ioctrl/agpsgpiodev.h
new file mode 100644
index 000000000000..815890578f4a
--- /dev/null
+++ b/drivers/mxc/gps_ioctrl/agpsgpiodev.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file agpsgpiodev.h
+ *
+ * @brief head file of Simple character device interface for AGPS kernel module.
+ *
+ * @ingroup
+ */
+
+#ifndef AGPSGPIODEV_H
+#define AGPSGPIODEV_H
+
+#include <linux/ioctl.h>
+
+#define USE_BLOCKING		/* Test driver with blocking calls */
+#undef USE_FASYNC		/* Test driver with async notification */
+
+/* The major device number. We can't rely on dynamic registration any more
+   because ioctls need to know it */
+#define MAJOR_NUM 100
+
+#define IOCTL_WRITEGPIO   _IOWR(MAJOR_NUM, 1, char *)
+#define IOCTL_READGPIO    _IOR(MAJOR_NUM, 2, char *)
+#define IOCTL_MAXNUMBER   2
+
+/* The name of the device file */
+#define AGPSGPIO_DEVICE_FILE_NAME "agpsgpio"
+
+/* Exported prototypes */
+int init_chrdev(struct device *dev);
+void cleanup_chrdev(void);
+void wakeup(void);
+
+#endif
diff --git a/drivers/mxc/hmp4e/Kconfig b/drivers/mxc/hmp4e/Kconfig
new file mode 100644
index 000000000000..fdd7dbc041ba
--- /dev/null
+++ b/drivers/mxc/hmp4e/Kconfig
@@ -0,0 +1,24 @@
+#
+# MPEG4 Encoder kernel module  configuration
+#
+
+menu "MXC MPEG4 Encoder Kernel module support"
+
+config MXC_HMP4E
+	tristate "MPEG4 Encoder support"
+	depends on ARCH_MXC
+	depends on !ARCH_MX27
+	default y
+	---help---
+	  Say Y to get the MPEG4 Encoder kernel module available on
+	  MXC platform.
+
+config MXC_HMP4E_DEBUG
+	bool "MXC MPEG4 Debug messages"
+	depends on MXC_HMP4E != n
+	default n
+	---help---
+	  Say Y here if you need the Encoder driver to print debug messages.
+	  This is an option for developers, most people should say N here.
+
+endmenu
diff --git a/drivers/mxc/hmp4e/Makefile b/drivers/mxc/hmp4e/Makefile
new file mode 100644
index 000000000000..0efe11fbdbc8
--- /dev/null
+++ b/drivers/mxc/hmp4e/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the MPEG4 Encoder kernel module.
+
+obj-$(CONFIG_MXC_HMP4E) 		+= mxc_hmp4e.o
+
+ifeq ($(CONFIG_MXC_HMP4E_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/mxc/hmp4e/mxc_hmp4e.c b/drivers/mxc/hmp4e/mxc_hmp4e.c
new file mode 100644
index 000000000000..38b84329d459
--- /dev/null
+++ b/drivers/mxc/hmp4e/mxc_hmp4e.c
@@ -0,0 +1,812 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Encoder device driver (kernel module)
+ *
+ * Copyright (C) 2005  Hantro Products Oy.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>		/*  __init,__exit directives */
+#include <linux/mm.h>		/* remap_page_range / remap_pfn_range */
+#include <linux/fs.h>		/* for struct file_operations */
+#include <linux/errno.h>	/* standard error codes */
+#include <linux/platform_device.h>	/* for device registeration for PM */
+#include <linux/delay.h>	/* for msleep_interruptible */
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>	/* for dma_alloc_consistent */
+#include <linux/clk.h>
+#include <asm/uaccess.h>	/* for ioctl __get_user, __put_user */
+#include <mach/hardware.h>
+#include "mxc_hmp4e.h"		/* MPEG4 encoder specific */
+
+/* here's all the must remember stuff */
+typedef struct {
+	ulong buffaddr;
+	u32 buffsize;
+	ulong iobaseaddr;
+	u32 iosize;
+	volatile u32 *hwregs;
+	u32 irq;
+	u16 hwid_offset;
+	u16 intr_offset;
+	u16 busy_offset;
+	u16 type;		/* Encoder type, CIF = 0, VGA = 1 */
+	u16 clk_gate;
+	u16 busy_val;
+	struct fasync_struct *async_queue;
+#ifdef CONFIG_PM
+	s32 suspend_state;
+	wait_queue_head_t power_queue;
+#endif
+} hmp4e_t;
+
+/* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/
+static s32 hmp4e_major;
+
+static u32 hmp4e_phys;
+static struct class *hmp4e_class;
+static hmp4e_t hmp4e_data;
+
+/*! MPEG4 enc clock handle. */
+static struct clk *hmp4e_clk;
+
+/*
+ * avoid "enable_irq(x) unbalanced from ..."
+ * error messages from the kernel, since {ena,dis}able_irq()
+ * calls are stacked in kernel.
+ */
+static bool irq_enable = false;
+
+ulong base_port = MPEG4_ENC_BASE_ADDR;
+u32 irq = MXC_INT_MPEG4_ENCODER;
+
+module_param(base_port, long, 000);
+module_param(irq, int, 000);
+
+/*!
+ * These variables store the register values when HMP4E is in suspend mode.
+ */
+#ifdef CONFIG_PM
+u32 io_regs[64];
+#endif
+
+static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma);
+static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma);
+static void hmp4e_reset(hmp4e_t * dev);
+irqreturn_t hmp4e_isr(s32 irq, void *dev_id);
+
+/*!
+ * This funtion is called to write h/w register.
+ *
+ * @param   val		value to be written into the register
+ * @param   offset	register offset
+ *
+ */
+static inline void hmp4e_write(u32 val, u32 offset)
+{
+	hmp4e_t *dev = &hmp4e_data;
+	__raw_writel(val, (dev->hwregs + offset));
+}
+
+/*!
+ * This funtion is called to read h/w register.
+ *
+ * @param   offset	register offset
+ *
+ * @return  This function returns the value read from the register.
+ *
+ */
+static inline u32 hmp4e_read(u32 offset)
+{
+	hmp4e_t *dev = &hmp4e_data;
+	u32 val;
+
+	val = __raw_readl(dev->hwregs + offset);
+
+	return val;
+}
+
+/*!
+ * The device's mmap method. The VFS has kindly prepared the process's
+ * vm_area_struct for us, so we examine this to see what was requested.
+ *
+ * @param   filp	pointer to struct file
+ * @param   vma		pointer to struct vma_area_struct
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	s32 result;
+	ulong offset = vma->vm_pgoff << PAGE_SHIFT;
+
+	pr_debug("hmp4e_mmap: size = %lu off = 0x%08lx\n",
+		 (unsigned long)(vma->vm_end - vma->vm_start), offset);
+
+	if (offset == 0) {
+		result = hmp4e_map_buffer(filp, vma);
+	} else if (offset == hmp4e_data.iobaseaddr) {
+		result = hmp4e_map_hwregs(filp, vma);
+	} else {
+		pr_debug("hmp4e: mmap invalid value\n");
+		result = -EINVAL;
+	}
+
+	return result;
+}
+
+/*!
+ * This funtion is called to handle ioctls.
+ *
+ * @param   inode	pointer to struct inode
+ * @param   filp	pointer to struct file
+ * @param   cmd		ioctl command
+ * @param   arg		user data
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_ioctl(struct inode *inode, struct file *filp,
+		       u32 cmd, ulong arg)
+{
+	s32 err = 0, retval = 0;
+	ulong offset = 0;
+	hmp4e_t *dev = &hmp4e_data;
+	write_t bwrite;
+
+#ifdef CONFIG_PM
+	wait_event_interruptible(hmp4e_data.power_queue,
+				 hmp4e_data.suspend_state == 0);
+#endif
+
+	/*
+	 * extract the type and number bitfields, and don't decode
+	 * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
+	 */
+	if (_IOC_TYPE(cmd) != HMP4E_IOC_MAGIC) {
+		pr_debug("hmp4e: ioctl invalid magic\n");
+		return -ENOTTY;
+	}
+
+	if (_IOC_NR(cmd) > HMP4E_IOC_MAXNR) {
+		pr_debug("hmp4e: ioctl exceeds max ioctl\n");
+		return -ENOTTY;
+	}
+
+	/*
+	 * the direction is a bitmask, and VERIFY_WRITE catches R/W
+	 * transfers. `Type' is user-oriented, while
+	 * access_ok is kernel-oriented, so the concept of "read" and
+	 * "write" is reversed
+	 */
+	if (_IOC_DIR(cmd) & _IOC_READ) {
+		err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
+	} else if (_IOC_DIR(cmd) & _IOC_WRITE) {
+		err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
+	}
+
+	if (err) {
+		pr_debug("hmp4e: ioctl invalid direction\n");
+		return -EFAULT;
+	}
+
+	switch (cmd) {
+	case HMP4E_IOCHARDRESET:
+		break;
+
+	case HMP4E_IOCGBUFBUSADDRESS:
+		retval = __put_user((ulong) hmp4e_phys, (u32 *) arg);
+		break;
+
+	case HMP4E_IOCGBUFSIZE:
+		retval = __put_user(hmp4e_data.buffsize, (u32 *) arg);
+		break;
+
+	case HMP4E_IOCSREGWRITE:
+		if (dev->type != 1) {	/* This ioctl only for VGA */
+			pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n");
+			retval = -EINVAL;
+			break;
+		}
+
+		retval = __copy_from_user(&bwrite, (u32 *) arg,
+					  sizeof(write_t));
+
+		if (bwrite.offset <= hmp4e_data.iosize - 4) {
+			hmp4e_write(bwrite.data, (bwrite.offset / 4));
+		} else {
+			pr_debug("hmp4e: HMP4E_IOCSREGWRITE failed\n");
+			retval = -EFAULT;
+		}
+		break;
+
+	case HMP4E_IOCXREGREAD:
+		if (dev->type != 1) {	/* This ioctl only for VGA */
+			pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n");
+			retval = -EINVAL;
+			break;
+		}
+
+		retval = __get_user(offset, (ulong *) arg);
+		if (offset <= hmp4e_data.iosize - 4) {
+			__put_user(hmp4e_read((offset / 4)), (ulong *) arg);
+		} else {
+			pr_debug("hmp4e: HMP4E_IOCXREGREAD failed\n");
+			retval = -EFAULT;
+		}
+		break;
+
+	case HMP4E_IOCGHWOFFSET:
+		__put_user(hmp4e_data.iobaseaddr, (ulong *) arg);
+		break;
+
+	case HMP4E_IOCGHWIOSIZE:
+		__put_user(hmp4e_data.iosize, (u32 *) arg);
+		break;
+
+	case HMP4E_IOC_CLI:
+		if (irq_enable == true) {
+			disable_irq(hmp4e_data.irq);
+			irq_enable = false;
+		}
+		break;
+
+	case HMP4E_IOC_STI:
+		if (irq_enable == false) {
+			enable_irq(hmp4e_data.irq);
+			irq_enable = true;
+		}
+		break;
+
+	default:
+		pr_debug("unknown case %x\n", cmd);
+	}
+
+	return retval;
+}
+
+/*!
+ * This funtion is called when the device is opened.
+ *
+ * @param   inode	pointer to struct inode
+ * @param   filp	pointer to struct file
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_open(struct inode *inode, struct file *filp)
+{
+	hmp4e_t *dev = &hmp4e_data;
+
+	filp->private_data = (void *)dev;
+
+	if (request_irq(dev->irq, hmp4e_isr, 0, "mxc_hmp4e", dev) != 0) {
+		pr_debug("hmp4e: request irq failed\n");
+		return -EBUSY;
+	}
+
+	if (irq_enable == false) {
+		irq_enable = true;
+	}
+	clk_enable(hmp4e_clk);
+	return 0;
+}
+
+static s32 hmp4e_fasync(s32 fd, struct file *filp, s32 mode)
+{
+	hmp4e_t *dev = (hmp4e_t *) filp->private_data;
+	return fasync_helper(fd, filp, mode, &dev->async_queue);
+}
+
+/*!
+ * This funtion is called when the device is closed.
+ *
+ * @param   inode	pointer to struct inode
+ * @param   filp	pointer to struct file
+ *
+ * @return  This function returns 0.
+ *
+ */
+static s32 hmp4e_release(struct inode *inode, struct file *filp)
+{
+	hmp4e_t *dev = (hmp4e_t *) filp->private_data;
+
+	/* this is necessary if user process exited asynchronously */
+	if (irq_enable == true) {
+		disable_irq(dev->irq);
+		irq_enable = false;
+	}
+
+	/* reset hardware */
+	hmp4e_reset(&hmp4e_data);
+
+	/* free the encoder IRQ */
+	free_irq(dev->irq, (void *)dev);
+
+	/* remove this filp from the asynchronusly notified filp's */
+	hmp4e_fasync(-1, filp, 0);
+	clk_disable(hmp4e_clk);
+	return 0;
+}
+
+/* VFS methods */
+static struct file_operations hmp4e_fops = {
+	.owner = THIS_MODULE,
+	.open = hmp4e_open,
+	.release = hmp4e_release,
+	.ioctl = hmp4e_ioctl,
+	.mmap = hmp4e_mmap,
+	.fasync = hmp4e_fasync,
+};
+
+/*!
+ * This funtion allocates physical contigous memory.
+ *
+ * @param   size 	size of memory to be allocated
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_alloc(u32 size)
+{
+	hmp4e_data.buffsize = PAGE_ALIGN(size);
+	hmp4e_data.buffaddr =
+	    (ulong) dma_alloc_coherent(NULL, hmp4e_data.buffsize,
+				       (dma_addr_t *) & hmp4e_phys,
+				       GFP_DMA | GFP_KERNEL);
+
+	if (hmp4e_data.buffaddr == 0) {
+		printk(KERN_ERR "hmp4e: couldn't allocate data buffer\n");
+		return -ENOMEM;
+	}
+
+	memset((s8 *) hmp4e_data.buffaddr, 0, hmp4e_data.buffsize);
+	return 0;
+}
+
+/*!
+ * This funtion frees the DMAed memory.
+ */
+static void hmp4e_free(void)
+{
+	if (hmp4e_data.buffaddr != 0) {
+		dma_free_coherent(NULL, hmp4e_data.buffsize,
+				  (void *)hmp4e_data.buffaddr, hmp4e_phys);
+		hmp4e_data.buffaddr = 0;
+	}
+}
+
+/*!
+ * This funtion maps the shared buffer in memory.
+ *
+ * @param   filp 	pointer to struct file
+ * @param   vma		pointer to struct vm_area_struct
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma)
+{
+	ulong phys;
+	ulong start = (u32) vma->vm_start;
+	ulong size = (u32) (vma->vm_end - vma->vm_start);
+
+	/* if userspace tries to mmap beyond end of our buffer, fail */
+	if (size > hmp4e_data.buffsize) {
+		pr_debug("hmp4e: hmp4e_map_buffer, invalid size\n");
+		return -EINVAL;
+	}
+
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	phys = hmp4e_phys;
+
+	if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, size,
+			    vma->vm_page_prot)) {
+		pr_debug("hmp4e: failed mmapping shared buffer\n");
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*!
+ * This funtion maps the h/w register space in memory.
+ *
+ * @param   filp 	pointer to struct file
+ * @param   vma		pointer to struct vm_area_struct
+ *
+ * @return  This function returns 0 if successful or -ve value on error.
+ *
+ */
+static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma)
+{
+	ulong phys;
+	ulong start = (unsigned long)vma->vm_start;
+	ulong size = (unsigned long)(vma->vm_end - vma->vm_start);
+
+	/* if userspace tries to mmap beyond end of our buffer, fail */
+	if (size > PAGE_SIZE) {
+		pr_debug("hmp4e: hmp4e_map_hwregs, invalid size\n");
+		return -EINVAL;
+	}
+
+	vma->vm_flags |= VM_RESERVED | VM_IO;
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* Remember this won't work for vmalloc()d memory ! */
+	phys = hmp4e_data.iobaseaddr;
+
+	if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, hmp4e_data.iosize,
+			    vma->vm_page_prot)) {
+		pr_debug("hmp4e: failed mmapping HW registers\n");
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is the interrupt service routine.
+ *
+ * @param   irq		the irq number
+ * @param   dev_id	driver data when ISR was regiatered
+ *
+ * @return  The return value is IRQ_HANDLED.
+ *
+ */
+irqreturn_t hmp4e_isr(s32 irq, void *dev_id)
+{
+	hmp4e_t *dev = (hmp4e_t *) dev_id;
+	u32 offset = dev->intr_offset;
+
+	u32 irq_status = hmp4e_read(offset);
+
+	/* clear enc IRQ */
+	hmp4e_write(irq_status & (~0x01), offset);
+
+	if (dev->async_queue)
+		kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is called to reset the encoder.
+ *
+ * @param   dev	 pointer to struct hmp4e_data
+ *
+ */
+static void hmp4e_reset(hmp4e_t * dev)
+{
+	s32 i;
+
+	/* enable HCLK for register reset */
+	hmp4e_write(dev->clk_gate, 0);
+
+	/* Reset registers, except ECR0 (0x00) and ID (read-only) */
+	for (i = 1; i < (dev->iosize / 4); i += 1) {
+		if (i == dev->hwid_offset)	/* ID is read only */
+			continue;
+
+		/* Only for CIF, not used */
+		if ((dev->type == 0) && (i == 14))
+			continue;
+
+		hmp4e_write(0, i);
+	}
+
+	/* disable HCLK */
+	hmp4e_write(0, 0);
+	return;
+}
+
+/*!
+ * This function is called during the driver binding process. This function
+ * does the hardware initialization.
+ *
+ * @param   dev   the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions
+ *
+ * @return  The function returns 0 if successful.
+ */
+static s32 hmp4e_probe(struct platform_device *pdev)
+{
+	s32 result;
+	u32 hwid;
+	struct device *temp_class;
+
+	hmp4e_data.iobaseaddr = base_port;
+	hmp4e_data.irq = irq;
+	hmp4e_data.buffaddr = 0;
+
+	/* map hw i/o registers into kernel space */
+	hmp4e_data.hwregs = (volatile void *)IO_ADDRESS(hmp4e_data.iobaseaddr);
+
+	hmp4e_clk = clk_get(&pdev->dev, "mpeg4_clk");
+	if (IS_ERR(hmp4e_clk)) {
+		printk(KERN_INFO "hmp4e: Unable to get clock\n");
+		return -EIO;
+	}
+
+	clk_enable(hmp4e_clk);
+
+	/* check hw id for encoder signature */
+	hwid = hmp4e_read(7);
+	if ((hwid & 0xffff) == 0x1882) {	/* CIF first */
+		hmp4e_data.type = 0;
+		hmp4e_data.iosize = (16 * 4);
+		hmp4e_data.hwid_offset = 7;
+		hmp4e_data.intr_offset = 5;
+		hmp4e_data.clk_gate = (1 << 1);
+		hmp4e_data.buffsize = 512000;
+		hmp4e_data.busy_offset = 0;
+		hmp4e_data.busy_val = 1;
+	} else {
+		hwid = hmp4e_read((0x88 / 4));
+		if ((hwid & 0xffff0000) == 0x52510000) {	/* VGA */
+			hmp4e_data.type = 1;
+			hmp4e_data.iosize = (35 * 4);
+			hmp4e_data.hwid_offset = (0x88 / 4);
+			hmp4e_data.intr_offset = (0x10 / 4);
+			hmp4e_data.clk_gate = (1 << 12);
+			hmp4e_data.buffsize = 1048576;
+			hmp4e_data.busy_offset = (0x10 / 4);
+			hmp4e_data.busy_val = (1 << 1);
+		} else {
+			printk(KERN_INFO "hmp4e: HW ID not found\n");
+			goto error1;
+		}
+	}
+
+	/* Reset hardware */
+	hmp4e_reset(&hmp4e_data);
+
+	/* allocate memory shared with ewl */
+	result = hmp4e_alloc(hmp4e_data.buffsize);
+	if (result < 0)
+		goto error1;
+
+	result = register_chrdev(hmp4e_major, "hmp4e", &hmp4e_fops);
+	if (result <= 0) {
+		pr_debug("hmp4e: unable to get major %d\n", hmp4e_major);
+		goto error2;
+	}
+
+	hmp4e_major = result;
+
+	hmp4e_class = class_create(THIS_MODULE, "hmp4e");
+	if (IS_ERR(hmp4e_class)) {
+		pr_debug("Error creating hmp4e class.\n");
+		goto error3;
+	}
+
+	temp_class = device_create(hmp4e_class, NULL, MKDEV(hmp4e_major, 0), NULL,
+				   "hmp4e");
+	if (IS_ERR(temp_class)) {
+		pr_debug("Error creating hmp4e class device.\n");
+		goto error4;
+	}
+
+	platform_set_drvdata(pdev, &hmp4e_data);
+
+#ifdef CONFIG_PM
+	hmp4e_data.async_queue = NULL;
+	hmp4e_data.suspend_state = 0;
+	init_waitqueue_head(&hmp4e_data.power_queue);
+#endif
+
+	printk(KERN_INFO "hmp4e: %s encoder initialized\n",
+	       hmp4e_data.type ? "VGA" : "CIF");
+	clk_disable(hmp4e_clk);
+	return 0;
+
+      error4:
+	class_destroy(hmp4e_class);
+      error3:
+	unregister_chrdev(hmp4e_major, "hmp4e");
+      error2:
+	hmp4e_free();
+      error1:
+	clk_disable(hmp4e_clk);
+	clk_put(hmp4e_clk);
+	printk(KERN_INFO "hmp4e: module not inserted\n");
+	return -EIO;
+}
+
+/*!
+ * Dissociates the driver.
+ *
+ * @param   dev   the device structure
+ *
+ * @return  The function always returns 0.
+ */
+static s32 hmp4e_remove(struct platform_device *pdev)
+{
+	device_destroy(hmp4e_class, MKDEV(hmp4e_major, 0));
+	class_destroy(hmp4e_class);
+	unregister_chrdev(hmp4e_major, "hmp4e");
+	hmp4e_free();
+	clk_disable(hmp4e_clk);
+	clk_put(hmp4e_clk);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This is the suspend of power management for the Hantro MPEG4 module
+ *
+ * @param        dev            the device
+ * @param        state          the state
+ *
+ * @return       This function always returns 0.
+ */
+static s32 hmp4e_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	s32 i;
+	hmp4e_t *pdata = &hmp4e_data;
+
+	/*
+	 * how many times msleep_interruptible will be called before
+	 * giving up
+	 */
+	s32 timeout = 10;
+
+	pr_debug("hmp4e: Suspend\n");
+	hmp4e_data.suspend_state = 1;
+
+	/* check if encoder is currently running */
+	while ((hmp4e_read(pdata->busy_offset) & (pdata->busy_val)) &&
+	       --timeout) {
+		pr_debug("hmp4e: encoder is running, going to sleep\n");
+		msleep_interruptible((unsigned int)30);
+	}
+
+	if (!timeout) {
+		pr_debug("hmp4e: timeout suspending, resetting encoder\n");
+		hmp4e_write(hmp4e_read(pdata->busy_offset) &
+			    (~pdata->busy_val), pdata->busy_offset);
+	}
+
+	/* first read register 0 */
+	io_regs[0] = hmp4e_read(0);
+
+	/* then override HCLK to make sure other registers can be read */
+	hmp4e_write(pdata->clk_gate, 0);
+
+	/* read other registers */
+	for (i = 1; i < (pdata->iosize / 4); i += 1) {
+
+		/* Only for CIF, not used */
+		if ((pdata->type == 0) && (i == 14))
+			continue;
+
+		io_regs[i] = hmp4e_read(i);
+	}
+
+	/* restore value of register 0 */
+	hmp4e_write(io_regs[0], 0);
+
+	/* stop HCLK */
+	hmp4e_write(0, 0);
+	clk_disable(hmp4e_clk);
+	return 0;
+};
+
+/*!
+ * This is the resume of power management for the Hantro MPEG4 module
+ * It suports RESTORE state.
+ *
+ * @param        pdev            the platform device
+ *
+ * @return       This function always returns 0
+ */
+static s32 hmp4e_resume(struct platform_device *pdev)
+{
+	s32 i;
+	u32 status;
+	hmp4e_t *pdata = &hmp4e_data;
+
+	pr_debug("hmp4e: Resume\n");
+	clk_enable(hmp4e_clk);
+
+	/* override HCLK to make sure registers can be written */
+	hmp4e_write(pdata->clk_gate, 0x00);
+
+	for (i = 1; i < (pdata->iosize / 4); i += 1) {
+		if (i == pdata->hwid_offset)	/* Read only */
+			continue;
+
+		/* Only for CIF, not used */
+		if ((pdata->type == 0) && (i == 14))
+			continue;
+
+		hmp4e_write(io_regs[i], i);
+	}
+
+	/* write register 0 last */
+	hmp4e_write(io_regs[0], 0x00);
+
+	/* Clear the suspend flag */
+	hmp4e_data.suspend_state = 0;
+
+	/* Unblock the wait queue */
+	wake_up_interruptible(&hmp4e_data.power_queue);
+
+	/* Continue operations */
+	status = hmp4e_read(pdata->intr_offset);
+	if (status & 0x1) {
+		hmp4e_write(status & (~0x01), pdata->intr_offset);
+		if (hmp4e_data.async_queue)
+			kill_fasync(&hmp4e_data.async_queue, SIGIO, POLL_IN);
+	}
+
+	return 0;
+};
+
+#endif
+
+static struct platform_driver hmp4e_driver = {
+	.driver = {
+		   .name = "mxc_hmp4e",
+		   },
+	.probe = hmp4e_probe,
+	.remove = hmp4e_remove,
+#ifdef CONFIG_PM
+	.suspend = hmp4e_suspend,
+	.resume = hmp4e_resume,
+#endif
+};
+
+static s32 __init hmp4e_init(void)
+{
+	printk(KERN_INFO "hmp4e: init\n");
+	platform_driver_register(&hmp4e_driver);
+	return 0;
+}
+
+static void __exit hmp4e_cleanup(void)
+{
+	platform_driver_unregister(&hmp4e_driver);
+	printk(KERN_INFO "hmp4e: module removed\n");
+}
+
+module_init(hmp4e_init);
+module_exit(hmp4e_cleanup);
+
+/* module description */
+MODULE_AUTHOR("Hantro Products Oy");
+MODULE_DESCRIPTION("Device driver for Hantro's hardware based MPEG4 encoder");
+MODULE_SUPPORTED_DEVICE("5251/4251 MPEG4 Encoder");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/hmp4e/mxc_hmp4e.h b/drivers/mxc/hmp4e/mxc_hmp4e.h
new file mode 100644
index 000000000000..f58831716346
--- /dev/null
+++ b/drivers/mxc/hmp4e/mxc_hmp4e.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Encoder device driver (kernel module headers)
+ *
+ * Copyright (C) 2005  Hantro Products Oy.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+#ifndef _HMP4ENC_H_
+#define _HMP4ENC_H_
+#include <linux/ioctl.h>	/* needed for the _IOW etc stuff used later */
+
+/* this is for writing data through ioctl to registers*/
+typedef struct {
+	unsigned long data;
+	unsigned long offset;
+} write_t;
+
+/*
+ * Ioctl definitions
+ */
+
+/* Use 'k' as magic number */
+#define HMP4E_IOC_MAGIC  'k'
+/*
+ * S means "Set" through a ptr,
+ * T means "Tell" directly with the argument value
+ * G means "Get": reply by setting through a pointer
+ * Q means "Query": response is on the return value
+ * X means "eXchange": G and S atomically
+ * H means "sHift": T and Q atomically
+ */
+#define HMP4E_IOCGBUFBUSADDRESS	_IOR(HMP4E_IOC_MAGIC,  1, unsigned long *)
+#define HMP4E_IOCGBUFSIZE	_IOR(HMP4E_IOC_MAGIC,  2, unsigned int *)
+#define HMP4E_IOCGHWOFFSET     	_IOR(HMP4E_IOC_MAGIC,  3, unsigned long *)
+#define HMP4E_IOCGHWIOSIZE     	_IOR(HMP4E_IOC_MAGIC,  4, unsigned int *)
+#define HMP4E_IOC_CLI          	_IO(HMP4E_IOC_MAGIC,   5)
+#define HMP4E_IOC_STI          	_IO(HMP4E_IOC_MAGIC,   6)
+#define HMP4E_IOCHARDRESET 	_IO(HMP4E_IOC_MAGIC,   7)
+#define HMP4E_IOCSREGWRITE	_IOW(HMP4E_IOC_MAGIC,  8, write_t)
+#define HMP4E_IOCXREGREAD	_IOWR(HMP4E_IOC_MAGIC, 9, unsigned long)
+
+#define HMP4E_IOC_MAXNR 9
+
+#endif				/* !_HMP4ENC_H_ */
diff --git a/drivers/mxc/hw_event/Kconfig b/drivers/mxc/hw_event/Kconfig
new file mode 100644
index 000000000000..bcf479689501
--- /dev/null
+++ b/drivers/mxc/hw_event/Kconfig
@@ -0,0 +1,11 @@
+menu "MXC HARDWARE EVENT"
+
+config MXC_HWEVENT
+	bool "MXC Hardware Event Handler"
+	default y
+	depends on ARCH_MXC
+	help
+	  If you plan to use the Hardware Event Handler in the MXC, say
+	  Y here. If unsure, select Y.
+
+endmenu
diff --git a/drivers/mxc/hw_event/Makefile b/drivers/mxc/hw_event/Makefile
new file mode 100644
index 000000000000..a53fe2b45e04
--- /dev/null
+++ b/drivers/mxc/hw_event/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MXC_HWEVENT)	+= mxc_hw_event.o
diff --git a/drivers/mxc/hw_event/mxc_hw_event.c b/drivers/mxc/hw_event/mxc_hw_event.c
new file mode 100644
index 000000000000..5451c1c68859
--- /dev/null
+++ b/drivers/mxc/hw_event/mxc_hw_event.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * mxc_hw_event.c
+ * Collect the hardware events, send to user by netlink
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netlink.h>
+#include <linux/sched.h>
+#include <linux/list.h>
+#include <linux/signal.h>
+#include <linux/freezer.h>
+#include <linux/kthread.h>
+#include <net/sock.h>
+
+#include <mach/hw_events.h>
+
+#define EVENT_POOL_SIZE	10
+
+struct hw_event_elem {
+	struct mxc_hw_event event;
+	struct list_head list;
+};
+
+static struct sock *nl_event_sock;	/* netlink socket */
+static struct list_head event_head;
+static struct list_head free_head;
+static struct hw_event_elem events_pool[EVENT_POOL_SIZE];	/* event pool */
+static DEFINE_SPINLOCK(list_lock);
+static DECLARE_WAIT_QUEUE_HEAD(event_wq);
+static unsigned int seq;	/* send seq */
+static int initialized;
+static struct task_struct *hwevent_kthread;
+
+/*!
+ * main HW event handler thread
+ */
+static int hw_event_thread(void *data)
+{
+	struct sk_buff *skb = NULL;
+	struct nlmsghdr *nlh = NULL;
+	unsigned int size;
+	struct hw_event_elem *event, *n;
+	LIST_HEAD(tmp_head);
+	DEFINE_WAIT(wait);
+
+	while (1) {
+
+		prepare_to_wait(&event_wq, &wait, TASK_INTERRUPTIBLE);
+		/* wait for event coming */
+		if (!freezing(current) && !kthread_should_stop() &&
+		    list_empty(&event_head))
+			schedule();
+		finish_wait(&event_wq, &wait);
+
+		try_to_freeze();
+
+		if (kthread_should_stop())
+			break;
+
+		/* fetch event from list */
+		spin_lock_irq(&list_lock);
+		tmp_head = event_head;
+		tmp_head.prev->next = &tmp_head;
+		tmp_head.next->prev = &tmp_head;
+		/* clear the event list head */
+		INIT_LIST_HEAD(&event_head);
+		spin_unlock_irq(&list_lock);
+
+		list_for_each_entry_safe(event, n, &tmp_head, list) {
+
+			size = NLMSG_SPACE(sizeof(struct mxc_hw_event));
+			skb = alloc_skb(size, GFP_KERNEL);
+			if (!skb) {
+				/* if failed alloc skb, we drop this event */
+				printk(KERN_WARNING
+				       "mxc_hw_event: skb_alloc() failed\n");
+				goto alloc_failure;
+			}
+
+			/* put the netlink header struct to skb */
+			nlh =
+			    NLMSG_PUT(skb, 0, seq++, NLMSG_DONE,
+				      size - sizeof(*nlh));
+
+			/* fill the netlink data */
+			memcpy((struct mxc_hw_event *)NLMSG_DATA(nlh),
+			       &event->event, sizeof(struct mxc_hw_event));
+
+			/* free the event node, set to unused */
+			spin_lock_irq(&list_lock);
+			list_move(&event->list, &free_head);
+			spin_unlock_irq(&list_lock);
+
+			/* send to all process that create this socket */
+			NETLINK_CB(skb).pid = 0;	/* sender pid */
+			NETLINK_CB(skb).dst_group = HW_EVENT_GROUP;
+			/* broadcast the event */
+			netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP,
+					  GFP_KERNEL);
+
+			continue;
+		      nlmsg_failure:
+			printk(KERN_WARNING
+			       "mxc_hw_event: No tailroom for NLMSG in skb\n");
+		      alloc_failure:
+			/* free the event node, set to unused */
+			spin_lock_irq(&list_lock);
+			list_del(&event->list);
+			list_add_tail(&event->list, &free_head);
+			spin_unlock_irq(&list_lock);
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ *
+ * @priority the event priority, REALTIME, EMERENCY, NORMAL
+ * @new_event event id to be send
+ */
+int hw_event_send(int priority, struct mxc_hw_event *new_event)
+{
+	unsigned int size;
+	struct sk_buff *skb = NULL;
+	struct nlmsghdr *nlh = NULL;
+	struct mxc_hw_event *event;
+	struct hw_event_elem *event_elem;
+	int ret;
+	unsigned long flag;
+	struct list_head *list_node;
+
+	if (!initialized) {
+		pr_info("HW Event module has not been initialized\n");
+		return -1;
+	}
+
+	if (priority == HWE_HIGH_PRIORITY) {
+		/**
+		 * the most high priority event,
+		 * we send it immediatly.
+		 */
+
+		size = NLMSG_SPACE(sizeof(struct mxc_hw_event));
+
+		/* alloc skb */
+		if (in_interrupt()) {
+			skb = alloc_skb(size, GFP_ATOMIC);
+		} else {
+			skb = alloc_skb(size, GFP_KERNEL);
+		}
+		if (!skb) {
+			/* if failed alloc skb, we drop this event */
+			printk(KERN_WARNING
+			       "hw_event send: skb_alloc() failed\n");
+			goto send_later;
+		}
+
+		/* put the netlink header struct to skb */
+		nlh = NLMSG_PUT(skb, 0, seq++, NLMSG_DONE, size - sizeof(*nlh));
+
+		/* fill the netlink data */
+		event = (struct mxc_hw_event *)NLMSG_DATA(nlh);
+		memcpy(event, new_event, sizeof(struct mxc_hw_event));
+
+		/* send to all process that create this socket */
+		NETLINK_CB(skb).pid = 0;	/* sender pid */
+		NETLINK_CB(skb).dst_group = HW_EVENT_GROUP;
+		/* broadcast the event */
+		ret = netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP,
+					in_interrupt()? GFP_ATOMIC :
+					GFP_KERNEL);
+		if (ret) {
+
+		      nlmsg_failure:
+			/* send failed */
+			kfree_skb(skb);
+			goto send_later;
+		}
+
+		return 0;
+	}
+
+      send_later:
+	spin_lock_irqsave(&list_lock, flag);
+	if (list_empty(&free_head)) {
+		spin_unlock_irqrestore(&list_lock, flag);
+		/* no more free event node */
+		printk(KERN_WARNING "mxc_event send: no more free node\n");
+		return -1;
+	}
+
+	/* get a free node from free list, and added to event list */
+	list_node = free_head.next;
+	/* fill event */
+	event_elem = list_entry(list_node, struct hw_event_elem, list);
+	event_elem->event = *new_event;
+	list_move(list_node, &event_head);
+	spin_unlock_irqrestore(&list_lock, flag);
+
+	wake_up(&event_wq);
+
+	return 0;
+}
+
+static int __init mxc_hw_event_init(void)
+{
+	int i;
+
+	/* initial the list head for event and free */
+	INIT_LIST_HEAD(&free_head);
+	INIT_LIST_HEAD(&event_head);
+
+	/* initial the free list */
+	for (i = 0; i < EVENT_POOL_SIZE; i++)
+		list_add_tail(&events_pool[i].list, &free_head);
+
+	/* create netlink kernel sock */
+	nl_event_sock =
+	    netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0, NULL, NULL,
+				  THIS_MODULE);
+	if (!nl_event_sock) {
+		printk(KERN_WARNING
+		       "mxc_hw_event: Fail to create netlink socket.\n");
+		return 1;
+	}
+
+	hwevent_kthread = kthread_run(hw_event_thread, NULL, "hwevent");
+	if (IS_ERR(hwevent_kthread)) {
+		printk(KERN_WARNING
+		       "mxc_hw_event: Fail to create hwevent thread.\n");
+		return 1;
+	}
+
+	initialized = 1;
+
+	return 0;
+}
+
+static void __exit mxc_hw_event_exit(void)
+{
+	kthread_stop(hwevent_kthread);
+	/* wait for thread completion */
+	sock_release(nl_event_sock->sk_socket);
+}
+
+module_init(mxc_hw_event_init);
+module_exit(mxc_hw_event_exit);
+
+EXPORT_SYMBOL(hw_event_send);
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/ipu/Kconfig b/drivers/mxc/ipu/Kconfig
new file mode 100644
index 000000000000..919cb598c294
--- /dev/null
+++ b/drivers/mxc/ipu/Kconfig
@@ -0,0 +1,4 @@
+config MXC_IPU_V1
+	bool
+
+source "drivers/mxc/ipu/pf/Kconfig"
diff --git a/drivers/mxc/ipu/Makefile b/drivers/mxc/ipu/Makefile
new file mode 100644
index 000000000000..4e9f19f9afa5
--- /dev/null
+++ b/drivers/mxc/ipu/Makefile
@@ -0,0 +1,5 @@
+obj-$(CONFIG_MXC_IPU_V1) = mxc_ipu.o
+
+mxc_ipu-objs := ipu_common.o ipu_sdc.o ipu_adc.o ipu_ic.o ipu_csi.o ipu_device.o ipu_calc_stripes_sizes.o
+
+obj-$(CONFIG_MXC_IPU_PF)        +=   pf/
diff --git a/drivers/mxc/ipu/ipu_adc.c b/drivers/mxc/ipu/ipu_adc.c
new file mode 100644
index 000000000000..78bfa0d19381
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_adc.c
@@ -0,0 +1,689 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_adc.c
+ *
+ * @brief IPU ADC functions
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+/*#define ADC_CHAN1_SA_MASK 0xFF800000 */
+
+static void _ipu_set_cmd_data_mappings(display_port_t disp,
+				       uint32_t pixel_fmt, int ifc_width);
+
+int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp,
+			      mcu_mode_t cmd, int16_t x_pos, int16_t y_pos)
+{
+	uint32_t reg;
+	uint32_t start_addr, stride;
+	unsigned long lock_flags;
+	uint32_t size;
+
+	size = 0;
+
+	switch (disp) {
+	case DISP0:
+		reg = __raw_readl(ADC_DISP0_CONF);
+		stride = reg & ADC_DISP_CONF_SL_MASK;
+		break;
+	case DISP1:
+		reg = __raw_readl(ADC_DISP1_CONF);
+		stride = reg & ADC_DISP_CONF_SL_MASK;
+		break;
+	case DISP2:
+		reg = __raw_readl(ADC_DISP2_CONF);
+		stride = reg & ADC_DISP_CONF_SL_MASK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (stride == 0)
+		return -EINVAL;
+
+	stride++;
+	start_addr = (y_pos * stride) + x_pos;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	reg = __raw_readl(ADC_CONF);
+
+	switch (chan) {
+	case ADC_SYS1:
+		reg &= ~0x00FF4000;
+		reg |=
+		    ((uint32_t) size << 21 | (uint32_t) disp << 19 | (uint32_t)
+		     cmd << 16);
+
+		__raw_writel(start_addr, ADC_SYSCHA1_SA);
+		break;
+
+	case ADC_SYS2:
+		reg &= ~0xFF008000;
+		reg |=
+		    ((uint32_t) size << 29 | (uint32_t) disp << 27 | (uint32_t)
+		     cmd << 24);
+
+		__raw_writel(start_addr, ADC_SYSCHA2_SA);
+		break;
+
+	case CSI_PRP_VF_ADC:
+	case MEM_PRP_VF_ADC:
+		reg &= ~0x000000F9;
+		reg |=
+		    ((uint32_t) size << 5 | (uint32_t) disp << 3 |
+		     ADC_CONF_PRP_EN);
+
+		__raw_writel(start_addr, ADC_PRPCHAN_SA);
+		break;
+
+	case MEM_PP_ADC:
+		reg &= ~0x00003F02;
+		reg |=
+		    ((uint32_t) size << 10 | (uint32_t) disp << 8 |
+		     ADC_CONF_PP_EN);
+
+		__raw_writel(start_addr, ADC_PPCHAN_SA);
+		break;
+	default:
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -1;
+		break;
+	}
+	__raw_writel(reg, ADC_CONF);
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+
+int32_t _ipu_adc_uninit_channel(ipu_channel_t chan)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	reg = __raw_readl(ADC_CONF);
+
+	switch (chan) {
+	case ADC_SYS1:
+		reg &= ~0x00FF4000;
+		break;
+	case ADC_SYS2:
+		reg &= ~0xFF008000;
+		break;
+	case CSI_PRP_VF_ADC:
+	case MEM_PRP_VF_ADC:
+		reg &= ~0x000000F9;
+		break;
+	case MEM_PP_ADC:
+		reg &= ~0x00003F02;
+		break;
+	default:
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -1;
+		break;
+	}
+	__raw_writel(reg, ADC_CONF);
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+
+int32_t ipu_adc_write_template(display_port_t disp, uint32_t * pCmd, bool write)
+{
+	uint32_t ima_addr = 0;
+	uint32_t row_nu;
+	int i;
+
+	/* Set IPU_IMA_ADDR (IPU Internal Memory Access Address) */
+	/* MEM_NU = 0x0001 (CPM) */
+	/* ROW_NU = 2*N ( N is channel number) */
+	/* WORD_NU = 0  */
+	if (write) {
+		row_nu = (uint32_t) disp *2 * ATM_ADDR_RANGE;
+	} else {
+		row_nu = ((uint32_t) disp * 2 + 1) * ATM_ADDR_RANGE;
+	}
+
+	/* form template addr for IPU_IMA_ADDR */
+	ima_addr = (0x3 << 16 /*Template memory */  | row_nu << 3);
+
+	__raw_writel(ima_addr, IPU_IMA_ADDR);
+
+	/* write template data for IPU_IMA_DATA */
+	for (i = 0; i < TEMPLATE_BUF_SIZE; i++)
+		/* only DATA field are needed */
+		__raw_writel(pCmd[i], IPU_IMA_DATA);
+
+	return 0;
+}
+
+int32_t
+ipu_adc_write_cmd(display_port_t disp, cmddata_t type,
+		  uint32_t cmd, const uint32_t * params, uint16_t numParams)
+{
+	uint16_t i;
+	int disable_di = 0;
+	u32 reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	reg = __raw_readl(IPU_CONF);
+	if ((reg & IPU_CONF_DI_EN) == 0) {
+		disable_di = 1;
+		reg |= IPU_CONF_DI_EN;
+		__raw_writel(reg, IPU_CONF);
+	}
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	__raw_writel((uint32_t) ((type ? 0x0 : 0x1) | disp << 1 | 0x10),
+		     DI_DISP_LLA_CONF);
+	__raw_writel(cmd, DI_DISP_LLA_DATA);
+	udelay(3);
+
+	__raw_writel((uint32_t) (0x10 | disp << 1 | 0x11), DI_DISP_LLA_CONF);
+	for (i = 0; i < numParams; i++) {
+		__raw_writel(params[i], DI_DISP_LLA_DATA);
+		udelay(3);
+	}
+
+	if (disable_di) {
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+		reg = __raw_readl(IPU_CONF);
+		reg &= ~IPU_CONF_DI_EN;
+		__raw_writel(reg, IPU_CONF);
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	}
+
+	return 0;
+}
+
+int32_t ipu_adc_set_update_mode(ipu_channel_t channel,
+				ipu_adc_update_mode_t mode,
+				uint32_t refresh_rate, unsigned long addr,
+				uint32_t * size)
+{
+	int32_t err = 0;
+	uint32_t ref_per, reg, src = 0;
+	unsigned long lock_flags;
+	uint32_t ipu_freq;
+
+	ipu_freq = clk_get_rate(g_ipu_clk);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPU_FS_DISP_FLOW);
+	reg &= ~FS_AUTO_REF_PER_MASK;
+	switch (mode) {
+	case IPU_ADC_REFRESH_NONE:
+		src = 0;
+		break;
+	case IPU_ADC_AUTO_REFRESH:
+		if (refresh_rate == 0) {
+			err = -EINVAL;
+			goto err0;
+		}
+		ref_per = ipu_freq / ((1UL << 17) * refresh_rate);
+		ref_per--;
+		reg |= ref_per << FS_AUTO_REF_PER_OFFSET;
+
+		src = FS_SRC_AUTOREF;
+		break;
+	case IPU_ADC_AUTO_REFRESH_SNOOP:
+		if (refresh_rate == 0) {
+			err = -EINVAL;
+			goto err0;
+		}
+		ref_per = ipu_freq / ((1UL << 17) * refresh_rate);
+		ref_per--;
+		reg |= ref_per << FS_AUTO_REF_PER_OFFSET;
+
+		src = FS_SRC_AUTOREF_SNOOP;
+		break;
+	case IPU_ADC_SNOOPING:
+		src = FS_SRC_SNOOP;
+		break;
+	}
+
+	switch (channel) {
+	case ADC_SYS1:
+		reg &= ~FS_ADC1_SRC_SEL_MASK;
+		reg |= src << FS_ADC1_SRC_SEL_OFFSET;
+		break;
+	case ADC_SYS2:
+		reg &= ~FS_ADC2_SRC_SEL_MASK;
+		reg |= src << FS_ADC2_SRC_SEL_OFFSET;
+		break;
+	default:
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -EINVAL;
+	}
+	__raw_writel(reg, IPU_FS_DISP_FLOW);
+
+	/* Setup bus snooping */
+	if ((mode == IPU_ADC_AUTO_REFRESH_SNOOP) || (mode == IPU_ADC_SNOOPING)) {
+		err = mxc_snoop_set_config(0, addr, *size);
+		if (err > 0) {
+			*size = err;
+			err = 0;
+		}
+	} else {
+		mxc_snoop_set_config(0, 0, 0);
+	}
+
+      err0:
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return err;
+}
+
+int32_t ipu_adc_get_snooping_status(uint32_t * statl, uint32_t * stath)
+{
+	return mxc_snoop_get_status(0, statl, stath);
+}
+
+int32_t ipu_adc_init_panel(display_port_t disp,
+			   uint16_t width, uint16_t height,
+			   uint32_t pixel_fmt,
+			   uint32_t stride,
+			   ipu_adc_sig_cfg_t sig,
+			   display_addressing_t addr,
+			   uint32_t vsync_width, vsync_t mode)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+	uint32_t ser_conf;
+	uint32_t disp_conf;
+	uint32_t adc_disp_conf;
+	uint32_t adc_disp_vsync;
+	uint32_t old_pol;
+
+	if ((disp != DISP1) && (disp != DISP2) &&
+	    (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL)) {
+		return -EINVAL;
+	}
+/*        adc_disp_conf = ((uint32_t)((((size == 3)||(size == 2))?1:0)<<14) |  */
+/*                         (uint32_t)addr<<12 | (stride-1)); */
+	adc_disp_conf = (uint32_t) addr << 12 | (stride - 1);
+
+	_ipu_set_cmd_data_mappings(disp, pixel_fmt, sig.ifc_width);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	disp_conf = __raw_readl(DI_DISP_IF_CONF);
+	old_pol = __raw_readl(DI_DISP_SIG_POL);
+	adc_disp_vsync = __raw_readl(ADC_DISP_VSYNC);
+
+	switch (disp) {
+	case DISP0:
+		__raw_writel(adc_disp_conf, ADC_DISP0_CONF);
+		__raw_writel((((height - 1) << 16) | (width - 1)),
+			     ADC_DISP0_SS);
+
+		adc_disp_vsync &= ~(ADC_DISP_VSYNC_D0_MODE_MASK |
+				    ADC_DISP_VSYNC_D0_WIDTH_MASK);
+		adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode;
+
+		old_pol &= ~0x2000003FL;
+		old_pol |= sig.data_pol | sig.cs_pol << 1 |
+		    sig.addr_pol << 2 | sig.read_pol << 3 |
+		    sig.write_pol << 4 | sig.Vsync_pol << 5 |
+		    sig.burst_pol << 29;
+		__raw_writel(old_pol, DI_DISP_SIG_POL);
+
+		disp_conf &= ~0x0000001FL;
+		disp_conf |= (sig.burst_mode << 3) | (sig.ifc_mode << 1) |
+		    DI_CONF_DISP0_EN;
+		__raw_writel(disp_conf, DI_DISP_IF_CONF);
+		break;
+	case DISP1:
+		__raw_writel(adc_disp_conf, ADC_DISP1_CONF);
+		__raw_writel((((height - 1) << 16) | (width - 1)),
+			     ADC_DISP12_SS);
+
+		adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK |
+				    ADC_DISP_VSYNC_D12_WIDTH_MASK);
+		adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode;
+
+		old_pol &= ~0x4000FF00L;
+		old_pol |= (sig.Vsync_pol << 6 | sig.data_pol << 8 |
+			    sig.cs_pol << 9 | sig.addr_pol << 10 |
+			    sig.read_pol << 11 | sig.write_pol << 12 |
+			    sig.clk_pol << 14 | sig.burst_pol << 30);
+		__raw_writel(old_pol, DI_DISP_SIG_POL);
+
+		disp_conf &= ~0x00003F00L;
+		if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) {
+			ser_conf = (sig.ifc_width - 1) <<
+			    DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET;
+			if (sig.ser_preamble_len) {
+				ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN;
+				ser_conf |= sig.ser_preamble <<
+				    DI_SER_DISPx_CONF_PREAMBLE_OFFSET;
+				ser_conf |= (sig.ser_preamble_len - 1) <<
+				    DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET;
+			}
+
+			ser_conf |=
+			    sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET;
+
+			if (sig.burst_mode == IPU_ADC_BURST_SERIAL)
+				ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN;
+			__raw_writel(ser_conf, DI_SER_DISP1_CONF);
+		} else {	/* parallel interface */
+			disp_conf |= (uint32_t) (sig.burst_mode << 12);
+		}
+		disp_conf |= (sig.ifc_mode << 9) | DI_CONF_DISP1_EN;
+		__raw_writel(disp_conf, DI_DISP_IF_CONF);
+		break;
+	case DISP2:
+		__raw_writel(adc_disp_conf, ADC_DISP2_CONF);
+		__raw_writel((((height - 1) << 16) | (width - 1)),
+			     ADC_DISP12_SS);
+
+		adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK |
+				    ADC_DISP_VSYNC_D12_WIDTH_MASK);
+		adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode;
+
+		old_pol &= ~0x80FF0000L;
+		temp = (uint32_t) (sig.data_pol << 16 | sig.cs_pol << 17 |
+				   sig.addr_pol << 18 | sig.read_pol << 19 |
+				   sig.write_pol << 20 | sig.Vsync_pol << 6 |
+				   sig.burst_pol << 31 | sig.clk_pol << 22);
+		__raw_writel(temp | old_pol, DI_DISP_SIG_POL);
+
+		disp_conf &= ~0x003F0000L;
+		if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) {
+			ser_conf = (sig.ifc_width - 1) <<
+			    DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET;
+			if (sig.ser_preamble_len) {
+				ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN;
+				ser_conf |= sig.ser_preamble <<
+				    DI_SER_DISPx_CONF_PREAMBLE_OFFSET;
+				ser_conf |= (sig.ser_preamble_len - 1) <<
+				    DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET;
+
+			}
+
+			ser_conf |=
+			    sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET;
+
+			if (sig.burst_mode == IPU_ADC_BURST_SERIAL)
+				ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN;
+			__raw_writel(ser_conf, DI_SER_DISP2_CONF);
+		} else {	/* parallel interface */
+			disp_conf |= (uint32_t) (sig.burst_mode << 20);
+		}
+		disp_conf |= (sig.ifc_mode << 17) | DI_CONF_DISP2_EN;
+		__raw_writel(disp_conf, DI_DISP_IF_CONF);
+		break;
+	default:
+		break;
+	}
+
+	__raw_writel(adc_disp_vsync, ADC_DISP_VSYNC);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read,
+				uint32_t cycle_time,
+				uint32_t up_time,
+				uint32_t down_time,
+				uint32_t read_latch_time, uint32_t pixel_clk)
+{
+	uint32_t reg;
+	uint32_t time_conf3 = 0;
+	uint32_t clk_per;
+	uint32_t up_per;
+	uint32_t down_per;
+	uint32_t read_per;
+	uint32_t pixclk_per = 0;
+	uint32_t ipu_freq;
+
+	ipu_freq = clk_get_rate(g_ipu_clk);
+
+	clk_per = (cycle_time * (ipu_freq / 1000L) * 16L) / 1000000L;
+	up_per = (up_time * (ipu_freq / 1000L) * 4L) / 1000000L;
+	down_per = (down_time * (ipu_freq / 1000L) * 4L) / 1000000L;
+
+	reg = (clk_per << DISPx_IF_CLK_PER_OFFSET) |
+	    (up_per << DISPx_IF_CLK_UP_OFFSET) |
+	    (down_per << DISPx_IF_CLK_DOWN_OFFSET);
+
+	if (read) {
+		read_per =
+		    (read_latch_time * (ipu_freq / 1000L) * 4L) / 1000000L;
+		if (pixel_clk)
+			pixclk_per = (ipu_freq * 16L) / pixel_clk;
+		time_conf3 = (read_per << DISPx_IF_CLK_READ_EN_OFFSET) |
+		    (pixclk_per << DISPx_PIX_CLK_PER_OFFSET);
+	}
+
+	dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_1/2 = 0x%08X\n", reg);
+	dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_3 = 0x%08X\n", time_conf3);
+
+	switch (disp) {
+	case DISP0:
+		if (read) {
+			__raw_writel(reg, DI_DISP0_TIME_CONF_2);
+			__raw_writel(time_conf3, DI_DISP0_TIME_CONF_3);
+		} else {
+			__raw_writel(reg, DI_DISP0_TIME_CONF_1);
+		}
+		break;
+	case DISP1:
+		if (read) {
+			__raw_writel(reg, DI_DISP1_TIME_CONF_2);
+			__raw_writel(time_conf3, DI_DISP1_TIME_CONF_3);
+		} else {
+			__raw_writel(reg, DI_DISP1_TIME_CONF_1);
+		}
+		break;
+	case DISP2:
+		if (read) {
+			__raw_writel(reg, DI_DISP2_TIME_CONF_2);
+			__raw_writel(time_conf3, DI_DISP2_TIME_CONF_3);
+		} else {
+			__raw_writel(reg, DI_DISP2_TIME_CONF_1);
+		}
+		break;
+	default:
+		return -EINVAL;
+		break;
+	}
+
+	return 0;
+}
+
+struct ipu_adc_di_map {
+	uint32_t map_byte1;
+	uint32_t map_byte2;
+	uint32_t map_byte3;
+	uint32_t cycle_cnt;
+};
+
+static const struct ipu_adc_di_map di_mappings[] = {
+	[0] = {
+	       /* RGB888, 8-bit bus */
+	       .map_byte1 = 0x1600AAAA,
+	       .map_byte2 = 0x00E05555,
+	       .map_byte2 = 0x00070000,
+	       .cycle_cnt = 3,
+	       },
+	[1] = {
+	       /* RGB666, 8-bit bus */
+	       .map_byte1 = 0x1C00AAAF,
+	       .map_byte2 = 0x00E0555F,
+	       .map_byte3 = 0x0007000F,
+	       .cycle_cnt = 3,
+	       },
+	[2] = {
+	       /* RGB565, 8-bit bus */
+	       .map_byte1 = 0x008055BF,
+	       .map_byte2 = 0x0142015F,
+	       .map_byte3 = 0x0007003F,
+	       .cycle_cnt = 2,
+	       },
+	[3] = {
+	       /* RGB888, 24-bit bus */
+	       .map_byte1 = 0x0007000F,
+	       .map_byte2 = 0x000F000F,
+	       .map_byte3 = 0x0017000F,
+	       .cycle_cnt = 1,
+	       },
+	[4] = {
+	       /* RGB666, 18-bit bus */
+	       .map_byte1 = 0x0005000F,
+	       .map_byte2 = 0x000B000F,
+	       .map_byte3 = 0x0011000F,
+	       .cycle_cnt = 1,
+	       },
+	[5] = {
+	       /* RGB565, 16-bit bus */
+	       .map_byte1 = 0x0004003F,
+	       .map_byte2 = 0x000A000F,
+	       .map_byte3 = 0x000F003F,
+	       .cycle_cnt = 1,
+	       },
+};
+
+/* Private methods */
+static void _ipu_set_cmd_data_mappings(display_port_t disp,
+				       uint32_t pixel_fmt, int ifc_width)
+{
+	uint32_t reg;
+	u32 map = 0;
+
+	if (ifc_width == 8) {
+		switch (pixel_fmt) {
+		case IPU_PIX_FMT_BGR24:
+			map = 0;
+			break;
+		case IPU_PIX_FMT_RGB666:
+			map = 1;
+			break;
+		case IPU_PIX_FMT_RGB565:
+			map = 2;
+			break;
+		default:
+			break;
+		}
+	} else if (ifc_width >= 16) {
+		switch (pixel_fmt) {
+		case IPU_PIX_FMT_BGR24:
+			map = 3;
+			break;
+		case IPU_PIX_FMT_RGB666:
+			map = 4;
+			break;
+		case IPU_PIX_FMT_RGB565:
+			map = 5;
+			break;
+		default:
+			break;
+		}
+	}
+
+	switch (disp) {
+	case DISP0:
+		if (ifc_width == 8) {
+			__raw_writel(0x00070000, DI_DISP0_CB0_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP0_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP);
+		} else {
+			__raw_writel(0x00070000, DI_DISP0_CB0_MAP);
+			__raw_writel(0x000F0000, DI_DISP0_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP);
+		}
+		__raw_writel(di_mappings[map].map_byte1, DI_DISP0_DB0_MAP);
+		__raw_writel(di_mappings[map].map_byte2, DI_DISP0_DB1_MAP);
+		__raw_writel(di_mappings[map].map_byte3, DI_DISP0_DB2_MAP);
+		reg = __raw_readl(DI_DISP_ACC_CC);
+		reg &= ~DISP0_IF_CLK_CNT_D_MASK;
+		reg |= (di_mappings[map].cycle_cnt - 1) <<
+		    DISP0_IF_CLK_CNT_D_OFFSET;
+		__raw_writel(reg, DI_DISP_ACC_CC);
+		break;
+	case DISP1:
+		if (ifc_width == 8) {
+			__raw_writel(0x00070000, DI_DISP1_CB0_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP1_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP);
+		} else {
+			__raw_writel(0x00070000, DI_DISP1_CB0_MAP);
+			__raw_writel(0x000F0000, DI_DISP1_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP);
+		}
+		__raw_writel(di_mappings[map].map_byte1, DI_DISP1_DB0_MAP);
+		__raw_writel(di_mappings[map].map_byte2, DI_DISP1_DB1_MAP);
+		__raw_writel(di_mappings[map].map_byte3, DI_DISP1_DB2_MAP);
+		reg = __raw_readl(DI_DISP_ACC_CC);
+		reg &= ~DISP1_IF_CLK_CNT_D_MASK;
+		reg |= (di_mappings[map].cycle_cnt - 1) <<
+		    DISP1_IF_CLK_CNT_D_OFFSET;
+		__raw_writel(reg, DI_DISP_ACC_CC);
+		break;
+	case DISP2:
+		if (ifc_width == 8) {
+			__raw_writel(0x00070000, DI_DISP2_CB0_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP2_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP);
+		} else {
+			__raw_writel(0x00070000, DI_DISP2_CB0_MAP);
+			__raw_writel(0x000F0000, DI_DISP2_CB1_MAP);
+			__raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP);
+		}
+		__raw_writel(di_mappings[map].map_byte1, DI_DISP2_DB0_MAP);
+		__raw_writel(di_mappings[map].map_byte2, DI_DISP2_DB1_MAP);
+		__raw_writel(di_mappings[map].map_byte3, DI_DISP2_DB2_MAP);
+		reg = __raw_readl(DI_DISP_ACC_CC);
+		reg &= ~DISP2_IF_CLK_CNT_D_MASK;
+		reg |= (di_mappings[map].cycle_cnt - 1) <<
+		    DISP2_IF_CLK_CNT_D_OFFSET;
+		__raw_writel(reg, DI_DISP_ACC_CC);
+		break;
+	default:
+		break;
+	}
+}
+
+void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset)
+{
+	/*TODO*/
+}
+
+int ipu_init_async_panel(int disp, int type, uint32_t cycle_time,
+			 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
+{
+	/*TODO:uniform interface for ipu async panel init*/
+	return -1;
+}
+
+EXPORT_SYMBOL(ipu_adc_write_template);
+EXPORT_SYMBOL(ipu_adc_write_cmd);
+EXPORT_SYMBOL(ipu_adc_set_update_mode);
+EXPORT_SYMBOL(ipu_adc_init_panel);
+EXPORT_SYMBOL(ipu_adc_init_ifc_timing);
diff --git a/drivers/mxc/ipu/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu/ipu_calc_stripes_sizes.c
new file mode 100644
index 000000000000..09c7664a07e5
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_calc_stripes_sizes.c
@@ -0,0 +1,374 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_calc_stripes_sizes.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/module.h>
+#include <linux/ipu.h>
+#include <asm/div64.h>
+
+#define BPP_32 0
+#define BPP_16 3
+#define BPP_8 5
+#define BPP_24 1
+#define BPP_12 4
+#define BPP_18 2
+
+static u64 _do_div(u64 a, u32 b)
+{
+	u64 div;
+	div = a;
+	do_div(div, b);
+	return div;
+}
+
+static u32 truncate(u32 up, /* 0: down; else: up */
+					u64 a, /* must be non-negative */
+					u32 b)
+{
+	u32 d;
+	u64 div;
+	div = _do_div(a, b);
+	d = b * (div >> 32);
+	if (up && (a > (((u64)d) << 32)))
+		return d+b;
+	else
+		return d;
+}
+
+static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
+{/* return input_f */
+	unsigned int f_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		f_calculated = 16;
+		break;
+
+	case IPU_PIX_FMT_NV12:
+		f_calculated = 8;
+		break;
+
+	default:
+		f_calculated = 0;
+		break;
+
+	}
+	if (!f_calculated) {
+		switch (bpp) {
+		case BPP_32:
+			f_calculated = 2;
+			break;
+
+		case BPP_16:
+			f_calculated = 4;
+			break;
+
+		case BPP_8:
+		case BPP_24:
+			f_calculated = 8;
+			break;
+
+		case BPP_12:
+			f_calculated = 16;
+			break;
+
+		case BPP_18:
+			f_calculated = 32;
+			break;
+
+		default:
+			f_calculated = 0;
+			break;
+			}
+		}
+	return f_calculated;
+}
+
+
+static unsigned int m_calc(unsigned int pfs)
+{
+	unsigned int m_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+		m_calculated = 8;
+		break;
+
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		m_calculated = 2;
+		break;
+
+	default:
+		m_calculated = 1;
+		break;
+
+	}
+	return m_calculated;
+}
+
+
+/* Stripe parameters calculator */
+/**************************************************************************
+Notes:
+MSW = the maximal width allowed for a stripe
+	i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
+cirr = the maximal inverse resizing ratio for which overlap in the input
+	is requested; typically cirr~2
+equal_stripes:
+	0: each stripe is allowed to have independent parameters
+		for maximal image quality
+	1: the stripes are requested to have identical parameters
+	(except the base address), for maximal performance
+If performance is the top priority (above image quality)
+	Avoid overlap, by setting CIRR = 0
+		This will also force effectively identical_stripes = 1
+	Choose IF & OF that corresponds to the same IOX/SX for both stripes
+	Choose IFW & OFW such that
+	IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
+	The function returns an error status:
+	0: no error
+	1: invalid input parameters -> aborted without result
+		Valid parameters should satisfy the following conditions
+		IFW <= OFW, otherwise downsizing is required
+					 - which is not supported yet
+		4 <= IFW,OFW, so some interpolation may be needed even without overlap
+		IM, OM, IF, OF should not vanish
+		2*IF <= IFW
+		so the frame can be split to two equal stripes, even without overlap
+		2*(OF+IF/irr_opt) <= OFW
+		so a valid positive INW exists even for equal stripes
+		OF <= MSW, otherwise, the left stripe cannot be sufficiently large
+		MSW < OFW, so splitting to stripes is required
+		OFW <= 2*MSW, so two stripes are sufficient
+		(this also implies that 2<=MSW)
+	2: OF is not a multiple of OM - not fully-supported yet
+	Output is produced but OW is not guaranited to be a multiple of OM
+	4: OFW reduced to be a multiple of OM
+	8: CIRR > 1: truncated to 1
+	Overlap is not supported (and not needed) y for upsizing)
+**************************************************************************/
+int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
+			   /* input frame width;>1 */
+			   unsigned int output_frame_width, /* output frame width; >1 */
+			   const unsigned int maximal_stripe_width,
+			   /* the maximal width allowed for a stripe */
+			   const unsigned long long cirr, /* see above */
+			   const unsigned int equal_stripes, /* see above */
+			   u32 input_pixelformat,/* pixel format after of read channel*/
+			   u32 output_pixelformat,/* pixel format after of write channel*/
+			   struct stripe_param *left,
+			   struct stripe_param *right)
+{
+	const unsigned int irr_frac_bits = 13;
+	const unsigned long irr_steps = 1 << irr_frac_bits;
+	const u64 dirr = ((u64)1) << (32 - 2);
+	/* The maximum relative difference allowed between the irrs */
+	const u64 cr = ((u64)4) << 32;
+	/* The importance ratio between the two terms in the cost function below */
+
+	unsigned int status;
+	unsigned int temp;
+	unsigned int onw_min;
+	unsigned int inw, onw, inw_best = 0;
+	/* number of pixels in the left stripe NOT hidden by the right stripe */
+	u64 irr_opt; /* the optimal inverse resizing ratio */
+	u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
+	u64 dinw; /* the misalignment between the stripes */
+	/* (measured in units of input columns) */
+	u64 difwl, difwr;
+	/* The number of input columns not reflected in the output */
+	/* the resizing ratio used for the right stripe is */
+	/*   left->irr and right->irr respectively */
+	u64 cost, cost_min;
+	u64 div; /* result of division */
+
+	unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
+
+	status = 0;
+
+	/* M, F calculations */
+	/* read back pfs from params */
+
+	input_f = f_calc(input_pixelformat, 0, NULL);
+	input_m = 16;
+	/* BPP should be used in the out_F calc */
+	/* Temporarily not used */
+	/* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */
+
+	output_f = 16;
+	output_m = m_calc(output_pixelformat);
+
+
+	if ((output_frame_width < input_frame_width) || (input_frame_width < 4)
+	    || (output_frame_width < 4))
+		return 1;
+
+	irr_opt = _do_div((((u64)(input_frame_width - 1)) << 32),
+			  (output_frame_width - 1));
+	rr_opt = _do_div((((u64)(output_frame_width - 1)) << 32),
+			 (input_frame_width - 1));
+
+	if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
+	    || (input_frame_width < (2 * input_f))
+	    || ((((u64)output_frame_width) << 32) <
+		(2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
+	    || (maximal_stripe_width < output_f)
+	    || (output_frame_width <= maximal_stripe_width)
+	    || ((2 * maximal_stripe_width) < output_frame_width))
+		return 1;
+
+	if (output_f % output_m)
+		status += 2;
+
+	temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
+	if (temp < output_frame_width) {
+		output_frame_width = temp;
+		status += 4;
+	}
+
+	if (equal_stripes) {
+		if ((irr_opt > cirr) /* overlap in the input is not requested */
+		    && ((input_frame_width % (input_m << 1)) == 0)
+		    && ((input_frame_width % (input_f << 1)) == 0)
+		    && ((output_frame_width % (output_m << 1)) == 0)
+		    && ((output_frame_width % (output_f << 1)) == 0)) {
+			/* without overlap */
+			left->input_width = right->input_width = right->input_column =
+				input_frame_width >> 1;
+			left->output_width = right->output_width = right->output_column =
+				output_frame_width >> 1;
+			left->input_column = right->input_column = 0;
+			div = _do_div(((((u64)irr_steps) << 32) *
+				       (right->input_width - 1)), (right->output_width - 1));
+			left->irr = right->irr = truncate(0, div, 1);
+		} else { /* with overlap */
+			onw = truncate(0, (((u64)output_frame_width) << 32) >> 1,
+				       output_f);
+			inw = truncate(0, onw * irr_opt, input_f);
+			/* this is the maximal inw which allows the same resizing ratio */
+			/* in both stripes */
+			onw = truncate(1, (inw * rr_opt), output_f);
+			div = _do_div((((u64)(irr_steps * inw)) <<
+				       32), onw);
+			left->irr = right->irr = truncate(0, div, 1);
+			left->output_width = right->output_width =
+				output_frame_width - onw;
+			/* These are valid assignments for output_width, */
+			/* assuming output_f is a multiple of output_m */
+			div = (((u64)(left->output_width-1) * (left->irr)) << 32);
+			div = (((u64)1) << 32) + _do_div(div, irr_steps);
+
+			left->input_width = right->input_width = truncate(1, div, input_m);
+
+			div = _do_div((((u64)((right->output_width - 1) * right->irr)) <<
+				       32), irr_steps);
+			difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+			div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+			left->input_column = truncate(0, div, input_f);
+
+
+			/* This splits the truncated input columns evenly */
+			/*    between the left and right margins */
+			right->input_column = left->input_column + inw;
+			left->output_column = 0;
+			right->output_column = onw;
+		}
+	} else { /* independent stripes */
+		onw_min = output_frame_width - maximal_stripe_width;
+		/* onw is a multiple of output_f, in the range */
+		/* [max(output_f,output_frame_width-maximal_stripe_width),*/
+		/*min(output_frame_width-2,maximal_stripe_width)] */
+		/* definitely beyond the cost of any valid setting */
+		cost_min = (((u64)input_frame_width) << 32) + cr;
+		onw = truncate(0, ((u64)maximal_stripe_width), output_f);
+		if (output_frame_width - onw == 1)
+			onw -= output_f; /*  => onw and output_frame_width-1-onw are positive */
+		inw = truncate(0, onw * irr_opt, input_f);
+		/* this is the maximal inw which allows the same resizing ratio */
+		/* in both stripes */
+		onw = truncate(1, inw * rr_opt, output_f);
+		do {
+			div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+			left->irr = truncate(0, div, 1);
+			div = _do_div((((u64)(onw * left->irr)) << 32),
+				      irr_steps);
+			dinw = (((u64)inw) << 32) - div;
+
+			div = _do_div((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
+				       32), irr_steps);
+
+			difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+
+			cost = difwl + (((u64)(cr * dinw)) >> 32);
+
+			if (cost < cost_min) {
+				inw_best = inw;
+				cost_min = cost;
+			}
+
+			inw -= input_f;
+			onw = truncate(1, inw * rr_opt, output_f);
+			/* This is the minimal onw which allows the same resizing ratio */
+			/*     in both stripes */
+		} while (onw >= onw_min);
+
+		inw = inw_best;
+		onw = truncate(1, inw * rr_opt, output_f);
+		div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+		left->irr = truncate(0, div, 1);
+
+		left->output_width = onw;
+		right->output_width = output_frame_width - onw;
+		/* These are valid assignments for output_width, */
+		/* assuming output_f is a multiple of output_m */
+		left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
+		right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
+					      32, input_m);
+
+		div = _do_div((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
+			       32), (right->output_width - 1));
+		right->irr = truncate(0, div, 1);
+		temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
+		if (temp < right->irr)
+			right->irr = temp;
+		div = _do_div(((u64)((right->output_width - 1) * right->irr) <<
+			       32), irr_steps);
+		difwr = (u64)(input_frame_width - 1 - inw) - div;
+
+
+		div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+		left->input_column = truncate(0, div, input_f);
+
+		/* This splits the truncated input columns evenly */
+		/*    between the left and right margins */
+		right->input_column = left->input_column + inw;
+		left->output_column = 0;
+		right->output_column = onw;
+	}
+	return status;
+}
+EXPORT_SYMBOL(ipu_calc_stripes_sizes);
diff --git a/drivers/mxc/ipu/ipu_common.c b/drivers/mxc/ipu/ipu_common.c
new file mode 100644
index 000000000000..a1dc566e7f8f
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_common.c
@@ -0,0 +1,1970 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_common.c
+ *
+ * @brief This file contains the IPU driver common API functions.
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+/*
+ * This type definition is used to define a node in the GPIO interrupt queue for
+ * registered interrupts for GPIO pins. Each node contains the GPIO signal number
+ * associated with the ISR and the actual ISR function pointer.
+ */
+struct ipu_irq_node {
+	irqreturn_t(*handler) (int, void *);	/*!< the ISR */
+	const char *name;	/*!< device associated with the interrupt */
+	void *dev_id;		/*!< some unique information for the ISR */
+	__u32 flags;		/*!< not used */
+};
+
+/* Globals */
+struct clk *g_ipu_clk;
+struct clk *g_ipu_csi_clk;
+static struct clk *dfm_clk;
+int g_ipu_irq[2];
+int g_ipu_hw_rev;
+bool g_sec_chan_en[21];
+uint32_t g_channel_init_mask;
+DEFINE_SPINLOCK(ipu_lock);
+struct device *g_ipu_dev;
+
+static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT];
+static const char driver_name[] = "mxc_ipu";
+
+static uint32_t g_ipu_config = 0;
+static uint32_t g_channel_init_mask_backup = 0;
+static bool g_csi_used = false;
+
+/* Static functions */
+static irqreturn_t ipu_irq_handler(int irq, void *desc);
+static void _ipu_pf_init(ipu_channel_params_t * params);
+static void _ipu_pf_uninit(void);
+
+inline static uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+	return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) :
+		((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF)
+		 : (((uint32_t) ch >> 16) & 0xFF)));
+};
+
+inline static uint32_t DMAParamAddr(uint32_t dma_ch)
+{
+	return (0x10000 | (dma_ch << 4));
+};
+
+/*!
+ * This function is called by the driver framework to initialize the IPU
+ * hardware.
+ *
+ * @param       dev       The device structure for the IPU passed in by the framework.
+ *
+ * @return      This function returns 0 on success or negative error code on error
+ */
+static
+int ipu_probe(struct platform_device *pdev)
+{
+//      struct platform_device *pdev = to_platform_device(dev);
+	struct mxc_ipu_config *ipu_conf = pdev->dev.platform_data;
+
+	spin_lock_init(&ipu_lock);
+
+	g_ipu_dev = &pdev->dev;
+	g_ipu_hw_rev = ipu_conf->rev;
+
+	/* Register IPU interrupts */
+	g_ipu_irq[0] = platform_get_irq(pdev, 0);
+	if (g_ipu_irq[0] < 0)
+		return -EINVAL;
+
+	if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, driver_name, 0) != 0) {
+		dev_err(g_ipu_dev, "request SYNC interrupt failed\n");
+		return -EBUSY;
+	}
+	/* Some platforms have 2 IPU interrupts */
+	g_ipu_irq[1] = platform_get_irq(pdev, 1);
+	if (g_ipu_irq[1] >= 0) {
+		if (request_irq
+		    (g_ipu_irq[1], ipu_irq_handler, 0, driver_name, 0) != 0) {
+			dev_err(g_ipu_dev, "request ERR interrupt failed\n");
+			return -EBUSY;
+		}
+	}
+
+	/* Enable IPU and CSI clocks */
+	/* Get IPU clock freq */
+	g_ipu_clk = clk_get(&pdev->dev, "ipu_clk");
+	dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk));
+
+	g_ipu_csi_clk = clk_get(&pdev->dev, "csi_clk");
+
+	dfm_clk = clk_get(NULL, "dfm_clk");
+
+	clk_enable(g_ipu_clk);
+
+	/* resetting the CONF register of the IPU */
+	__raw_writel(0x00000000, IPU_CONF);
+
+	__raw_writel(0x00100010L, DI_HSP_CLK_PER);
+
+	/* Set SDC refresh channels as high priority */
+	__raw_writel(0x0000C000L, IDMAC_CHA_PRI);
+
+	/* Set to max back to back burst requests */
+	__raw_writel(0x00000000L, IDMAC_CONF);
+
+	register_ipu_device();
+
+	return 0;
+}
+
+/*!
+ * This function is called to initialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to initalize.
+ *
+ * @param       params  Input parameter containing union of channel initialization
+ *                      parameters.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t * params)
+{
+	uint32_t ipu_conf;
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel));
+
+	if ((channel != MEM_SDC_BG) && (channel != MEM_SDC_FG) &&
+	    (channel != MEM_ROT_ENC_MEM) && (channel != MEM_ROT_VF_MEM) &&
+	    (channel != MEM_ROT_PP_MEM) && (channel != CSI_MEM)
+	    && (params == NULL)) {
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	ipu_conf = __raw_readl(IPU_CONF);
+	if (ipu_conf == 0) {
+		clk_enable(g_ipu_clk);
+	}
+
+	if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+		dev_err(g_ipu_dev, "Warning: channel already initialized %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	switch (channel) {
+	case CSI_PRP_VF_MEM:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_prpvf(params, true);
+		break;
+	case CSI_PRP_VF_ADC:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg | (FS_DEST_ADC << FS_PRPVF_DEST_SEL_OFFSET),
+			     IPU_FS_PROC_FLOW);
+
+		_ipu_adc_init_channel(CSI_PRP_VF_ADC,
+				      params->csi_prp_vf_adc.disp,
+				      WriteTemplateNonSeq,
+				      params->csi_prp_vf_adc.out_left,
+				      params->csi_prp_vf_adc.out_top);
+
+		_ipu_ic_init_prpvf(params, true);
+		break;
+	case MEM_PRP_VF_MEM:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_prpvf(params, false);
+		break;
+	case MEM_ROT_VF_MEM:
+		_ipu_ic_init_rotate_vf(params);
+		break;
+	case CSI_PRP_ENC_MEM:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
+		_ipu_ic_init_prpenc(params, true);
+		break;
+	case MEM_PRP_ENC_MEM:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
+		_ipu_ic_init_prpenc(params, false);
+		break;
+	case MEM_ROT_ENC_MEM:
+		_ipu_ic_init_rotate_enc(params);
+		break;
+	case MEM_PP_ADC:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg | (FS_DEST_ADC << FS_PP_DEST_SEL_OFFSET),
+			     IPU_FS_PROC_FLOW);
+
+		_ipu_adc_init_channel(MEM_PP_ADC, params->mem_pp_adc.disp,
+				      WriteTemplateNonSeq,
+				      params->mem_pp_adc.out_left,
+				      params->mem_pp_adc.out_top);
+
+		if (params->mem_pp_adc.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_pp(params);
+		break;
+	case MEM_PP_MEM:
+		if (params->mem_pp_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_pp(params);
+		break;
+	case MEM_ROT_PP_MEM:
+		_ipu_ic_init_rotate_pp(params);
+		break;
+	case CSI_MEM:
+		_ipu_ic_init_csi(params);
+		break;
+
+	case MEM_PF_Y_MEM:
+	case MEM_PF_U_MEM:
+	case MEM_PF_V_MEM:
+		/* Enable PF block */
+		_ipu_pf_init(params);
+		break;
+
+	case MEM_SDC_BG:
+		break;
+	case MEM_SDC_FG:
+		break;
+	case ADC_SYS1:
+		_ipu_adc_init_channel(ADC_SYS1, params->adc_sys1.disp,
+				      params->adc_sys1.ch_mode,
+				      params->adc_sys1.out_left,
+				      params->adc_sys1.out_top);
+		break;
+	case ADC_SYS2:
+		_ipu_adc_init_channel(ADC_SYS2, params->adc_sys2.disp,
+				      params->adc_sys2.ch_mode,
+				      params->adc_sys2.out_left,
+				      params->adc_sys2.out_top);
+		break;
+	default:
+		dev_err(g_ipu_dev, "Missing channel initialization\n");
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	/* Enable IPU sub module */
+	g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+
+	if (g_channel_init_mask & 0x00000066L) {	/*CSI */
+		ipu_conf |= IPU_CONF_CSI_EN;
+		if (cpu_is_mx31() || cpu_is_mx32()) {
+			g_csi_used = true;
+		}
+	}
+	if (g_channel_init_mask & 0x00001FFFL) {	/*IC */
+		ipu_conf |= IPU_CONF_IC_EN;
+	}
+	if (g_channel_init_mask & 0x00000A10L) {	/*ROT */
+		ipu_conf |= IPU_CONF_ROT_EN;
+	}
+	if (g_channel_init_mask & 0x0001C000L) {	/*SDC */
+		ipu_conf |= IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	}
+	if (g_channel_init_mask & 0x00061140L) {	/*ADC */
+		ipu_conf |= IPU_CONF_ADC_EN | IPU_CONF_DI_EN;
+	}
+	if (g_channel_init_mask & 0x00380000L) {	/*PF */
+		ipu_conf |= IPU_CONF_PF_EN;
+	}
+	__raw_writel(ipu_conf, IPU_CONF);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+/*!
+ * This function is called to uninitialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to uninitalize.
+ */
+void ipu_uninit_channel(ipu_channel_t channel)
+{
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t dma, mask = 0;
+	uint32_t ipu_conf;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		dev_err(g_ipu_dev, "Channel already uninitialized %d\n",
+			IPU_CHAN_ID(channel));
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return;
+	}
+
+	/* Make sure channel is disabled */
+	/* Get input and output dma channels */
+	dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	if (dma != IDMA_CHAN_INVALID)
+		mask |= 1UL << dma;
+	dma = channel_2_dma(channel, IPU_INPUT_BUFFER);
+	if (dma != IDMA_CHAN_INVALID)
+		mask |= 1UL << dma;
+	/* Get secondary input dma channel */
+	if (g_sec_chan_en[IPU_CHAN_ID(channel)]) {
+		dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER);
+		if (dma != IDMA_CHAN_INVALID) {
+			mask |= 1UL << dma;
+		}
+	}
+	if (mask & __raw_readl(IDMAC_CHA_EN)) {
+		dev_err(g_ipu_dev,
+			"Channel %d is not disabled, disable first\n",
+			IPU_CHAN_ID(channel));
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return;
+	}
+
+	/* Reset the double buffer */
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL);
+	__raw_writel(reg & ~mask, IPU_CHA_DB_MODE_SEL);
+
+	g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
+
+	switch (channel) {
+	case CSI_MEM:
+		_ipu_ic_uninit_csi();
+		break;
+	case CSI_PRP_VF_ADC:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg & ~FS_PRPVF_DEST_SEL_MASK, IPU_FS_PROC_FLOW);
+
+		_ipu_adc_uninit_channel(CSI_PRP_VF_ADC);
+
+		/* Fall thru */
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		_ipu_ic_uninit_prpvf();
+		break;
+	case MEM_PRP_VF_ADC:
+		break;
+	case MEM_ROT_VF_MEM:
+		_ipu_ic_uninit_rotate_vf();
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		_ipu_ic_uninit_prpenc();
+		break;
+	case MEM_ROT_ENC_MEM:
+		_ipu_ic_uninit_rotate_enc();
+		break;
+	case MEM_PP_ADC:
+		reg = __raw_readl(IPU_FS_PROC_FLOW);
+		__raw_writel(reg & ~FS_PP_DEST_SEL_MASK, IPU_FS_PROC_FLOW);
+
+		_ipu_adc_uninit_channel(MEM_PP_ADC);
+
+		/* Fall thru */
+	case MEM_PP_MEM:
+		_ipu_ic_uninit_pp();
+		break;
+	case MEM_ROT_PP_MEM:
+		_ipu_ic_uninit_rotate_pp();
+		break;
+
+	case MEM_PF_Y_MEM:
+		_ipu_pf_uninit();
+		break;
+	case MEM_PF_U_MEM:
+	case MEM_PF_V_MEM:
+		break;
+
+	case MEM_SDC_BG:
+		break;
+	case MEM_SDC_FG:
+		break;
+	case ADC_SYS1:
+		_ipu_adc_uninit_channel(ADC_SYS1);
+		break;
+	case ADC_SYS2:
+		_ipu_adc_uninit_channel(ADC_SYS2);
+		break;
+	case MEM_SDC_MASK:
+	case CHAN_NONE:
+		break;
+	}
+
+	g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	ipu_conf = __raw_readl(IPU_CONF);
+	if ((g_channel_init_mask & 0x00000066L) == 0) {	/*CSI */
+		ipu_conf &= ~IPU_CONF_CSI_EN;
+	}
+	if ((g_channel_init_mask & 0x00001FFFL) == 0) {	/*IC */
+		ipu_conf &= ~IPU_CONF_IC_EN;
+	}
+	if ((g_channel_init_mask & 0x00000A10L) == 0) {	/*ROT */
+		ipu_conf &= ~IPU_CONF_ROT_EN;
+	}
+	if ((g_channel_init_mask & 0x0001C000L) == 0) {	/*SDC */
+		ipu_conf &= ~IPU_CONF_SDC_EN;
+	}
+	if ((g_channel_init_mask & 0x00061140L) == 0) {	/*ADC */
+		ipu_conf &= ~IPU_CONF_ADC_EN;
+	}
+	if ((g_channel_init_mask & 0x0007D140L) == 0) {	/*DI */
+		ipu_conf &= ~IPU_CONF_DI_EN;
+	}
+	if ((g_channel_init_mask & 0x00380000L) == 0) {	/*PF */
+		ipu_conf &= ~IPU_CONF_PF_EN;
+	}
+	__raw_writel(ipu_conf, IPU_CONF);
+	if (ipu_conf == 0) {
+		clk_disable(g_ipu_clk);
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer. Pixel
+ *                              format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       rot_mode        Input parameter for rotation setting of buffer.
+ *                              A rotation setting other than \b IPU_ROTATE_VERT_FLIP
+ *                              should only be used for input buffers of rotation
+ *                              channels.
+ *
+ * @param       phyaddr_0       Input parameter buffer 0 physical address.
+ *
+ * @param       phyaddr_1       Input parameter buffer 1 physical address.
+ *                              Setting this to a value other than NULL enables
+ *                              double buffering mode.
+ *
+ * @param       u		       	private u offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param       v		       	private v offset for additional cropping,
+ *								zero if not used.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				ipu_rotate_mode_t rot_mode,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				uint32_t u, uint32_t v)
+{
+	uint32_t params[10];
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t dma_chan;
+
+	dma_chan = channel_2_dma(channel, type);
+
+	if (stride < width * bytes_per_pixel(pixel_fmt))
+		stride = width * bytes_per_pixel(pixel_fmt);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (stride % 4) {
+		dev_err(g_ipu_dev,
+			"Stride must be 32-bit aligned, stride = %d\n", stride);
+		return -EINVAL;
+	}
+	/* IC channels' width must be multiple of 8 pixels     */
+	if ((dma_chan <= 13) && (width % 8)) {
+		dev_err(g_ipu_dev, "width must be 8 pixel multiple\n");
+		return -EINVAL;
+	}
+	/* Build parameter memory data for DMA channel */
+	_ipu_ch_param_set_size(params, pixel_fmt, width, height, stride, u, v);
+	_ipu_ch_param_set_buffer(params, phyaddr_0, phyaddr_1);
+	_ipu_ch_param_set_rotation(params, rot_mode);
+	/* Some channels (rotation) have restriction on burst length */
+	if ((dma_chan == 10) || (dma_chan == 11) || (dma_chan == 13)) {
+		_ipu_ch_param_set_burst_size(params, 8);
+	} else if (dma_chan == 24) {	/* PF QP channel */
+		_ipu_ch_param_set_burst_size(params, 4);
+	} else if (dma_chan == 25) {	/* PF H264 BS channel */
+		_ipu_ch_param_set_burst_size(params, 16);
+	} else if (((dma_chan == 14) || (dma_chan == 15)) &&
+		   pixel_fmt == IPU_PIX_FMT_RGB565) {
+		_ipu_ch_param_set_burst_size(params, 16);
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	_ipu_write_param_mem(DMAParamAddr(dma_chan), params, 10);
+
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL);
+	if (phyaddr_1) {
+		reg |= 1UL << dma_chan;
+	} else {
+		reg &= ~(1UL << dma_chan);
+	}
+	__raw_writel(reg, IPU_CHA_DB_MODE_SEL);
+
+	/* Reset to buffer 0 */
+	__raw_writel(1UL << dma_chan, IPU_CHA_CUR_BUF);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+/*!
+ * This function is called to update the physical address of a buffer for
+ * a logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for which buffer number to update.
+ *                              0 or 1 are the only valid values.
+ *
+ * @param       phyaddr         Input parameter buffer physical address.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail. This function will fail if the buffer is set to ready.
+ */
+int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				  uint32_t bufNum, dma_addr_t phyaddr)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (bufNum == 0) {
+		reg = __raw_readl(IPU_CHA_BUF0_RDY);
+		if (reg & (1UL << dma_chan)) {
+			spin_unlock_irqrestore(&ipu_lock, lock_flags);
+			return -EACCES;
+		}
+		__raw_writel(DMAParamAddr(dma_chan) + 0x0008UL, IPU_IMA_ADDR);
+		__raw_writel(phyaddr, IPU_IMA_DATA);
+	} else {
+		reg = __raw_readl(IPU_CHA_BUF1_RDY);
+		if (reg & (1UL << dma_chan)) {
+			spin_unlock_irqrestore(&ipu_lock, lock_flags);
+			return -EACCES;
+		}
+		__raw_writel(DMAParamAddr(dma_chan) + 0x0009UL, IPU_IMA_ADDR);
+		__raw_writel(phyaddr, IPU_IMA_DATA);
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	dev_dbg(g_ipu_dev, "IPU: update IDMA ch %d buf %d = 0x%08X\n",
+		dma_chan, bufNum, phyaddr);
+	return 0;
+}
+
+/*!
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       u				predefined private u offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param       v				predefined private v offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param		vertical_offset vertical offset for Y coordinate
+ * 								in the existed frame
+ *
+ *
+ * @param		horizontal_offset horizontal offset for X coordinate
+ * 								in the existed frame
+ *
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ *              This function will fail if any buffer is set to ready.
+ */
+
+int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				uint32_t u, uint32_t v,
+				uint32_t vertical_offset, uint32_t horizontal_offset)
+{
+	uint32_t reg;
+	int ret = 0;
+	unsigned long lock_flags;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	ret = -EACCES;
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_update_channel_offset);
+
+/*!
+ * This function is called to set a channel's buffer as ready.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for which buffer number set to
+ *                              ready state.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
+			  uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0) {
+		/*Mark buffer 0 as ready. */
+		__raw_writel(1UL << dma_chan, IPU_CHA_BUF0_RDY);
+	} else {
+		/*Mark buffer 1 as ready. */
+		__raw_writel(1UL << dma_chan, IPU_CHA_BUF1_RDY);
+	}
+	return 0;
+}
+
+/*!
+ * This function check buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+int32_t ipu_check_buffer_busy(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0)
+		reg = __raw_readl(IPU_CHA_BUF0_RDY);
+	else
+		reg = __raw_readl(IPU_CHA_BUF1_RDY);
+
+	if (reg & (1UL << dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_check_buffer_busy);
+
+/*!
+ * This function links 2 channels together for automatic frame
+ * synchronization. The output of the source channel is linked to the input of
+ * the destination channel.
+ *
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	unsigned long lock_flags;
+	uint32_t out_dma;
+	uint32_t in_dma;
+	bool isProc;
+	uint32_t value;
+	uint32_t mask;
+	uint32_t offset;
+	uint32_t fs_proc_flow;
+	uint32_t fs_disp_flow;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW);
+	fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW);
+
+	out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER));
+	in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER));
+
+	/* PROCESS THE OUTPUT DMA CH */
+	switch (out_dma) {
+		/*VF-> */
+	case IDMA_IC_1:
+		pr_debug("Link VF->");
+		isProc = true;
+		mask = FS_PRPVF_DEST_SEL_MASK;
+		offset = FS_PRPVF_DEST_SEL_OFFSET;
+		value = (in_dma == IDMA_IC_11) ? FS_DEST_ROT :	/*->VF_ROT */
+		    (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 :	/* ->ADC1 */
+		    (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 :	/* ->ADC2 */
+		    (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG :	/*->SDC_BG */
+		    (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG :	/*->SDC_FG */
+		    (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 :	/*->ADC1 */
+		    /* ->ADCDirect */
+		    0;
+		break;
+
+		/*VF_ROT-> */
+	case IDMA_IC_9:
+		pr_debug("Link VF_ROT->");
+		isProc = true;
+		mask = FS_PRPVF_ROT_DEST_SEL_MASK;
+		offset = FS_PRPVF_ROT_DEST_SEL_OFFSET;
+		value = (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 :	/*->ADC1 */
+		    (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 :	/* ->ADC2 */
+		    (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG :	/*->SDC_BG */
+		    (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG :	/*->SDC_FG */
+		    0;
+		break;
+
+		/*ENC-> */
+	case IDMA_IC_0:
+		pr_debug("Link ENC->");
+		isProc = true;
+		mask = 0;
+		offset = 0;
+		value = (in_dma == IDMA_IC_10) ? FS_PRPENC_DEST_SEL :	/*->ENC_ROT	*/
+		    0;
+		break;
+
+		/*PP-> */
+	case IDMA_IC_2:
+		pr_debug("Link PP->");
+		isProc = true;
+		mask = FS_PP_DEST_SEL_MASK;
+		offset = FS_PP_DEST_SEL_OFFSET;
+		value = (in_dma == IDMA_IC_13) ? FS_DEST_ROT :	/*->PP_ROT */
+		    (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 :	/* ->ADC1 */
+		    (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 :	/* ->ADC2 */
+		    (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG :	/*->SDC_BG */
+		    (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG :	/*->SDC_FG */
+		    /* ->ADCDirect */
+		    0;
+		break;
+
+		/*PP_ROT-> */
+	case IDMA_IC_12:
+		pr_debug("Link PP_ROT->");
+		isProc = true;
+		mask = FS_PP_ROT_DEST_SEL_MASK;
+		offset = FS_PP_ROT_DEST_SEL_OFFSET;
+		value = (in_dma == IDMA_IC_5) ? FS_DEST_ROT :	/*->PP */
+		    (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 :	/* ->ADC1 */
+		    (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 :	/* ->ADC2 */
+		    (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG :	/*->SDC_BG */
+		    (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG :	/*->SDC_FG */
+		    0;
+		break;
+
+		/*PF-> */
+	case IDMA_PF_Y_OUT:
+	case IDMA_PF_U_OUT:
+	case IDMA_PF_V_OUT:
+		pr_debug("Link PF->");
+		isProc = true;
+		mask = FS_PF_DEST_SEL_MASK;
+		offset = FS_PF_DEST_SEL_OFFSET;
+		value = (in_dma == IDMA_IC_5) ? FS_PF_DEST_PP :
+		    (in_dma == IDMA_IC_13) ? FS_PF_DEST_ROT : 0;
+		break;
+
+		/* Invalid Chainings: ENC_ROT-> */
+	default:
+		pr_debug("Link Invalid->");
+		value = 0;
+		break;
+
+	}
+
+	if (value) {
+		if (isProc) {
+			fs_proc_flow &= ~mask;
+			fs_proc_flow |= (value << offset);
+		} else {
+			fs_disp_flow &= ~mask;
+			fs_disp_flow |= (value << offset);
+		}
+	} else {
+		dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n",
+			out_dma, in_dma);
+		return -EINVAL;
+	}
+
+	/* PROCESS THE INPUT DMA CH */
+	switch (in_dma) {
+		/* ->VF_ROT */
+	case IDMA_IC_11:
+		pr_debug("VF_ROT\n");
+		isProc = true;
+		mask = 0;
+		offset = 0;
+		value = (out_dma == IDMA_IC_1) ? FS_PRPVF_ROT_SRC_SEL :	/*VF-> */
+		    0;
+		break;
+
+		/* ->ENC_ROT */
+	case IDMA_IC_10:
+		pr_debug("ENC_ROT\n");
+		isProc = true;
+		mask = 0;
+		offset = 0;
+		value = (out_dma == IDMA_IC_0) ? FS_PRPENC_ROT_SRC_SEL :	/*ENC-> */
+		    0;
+		break;
+
+		/* ->PP */
+	case IDMA_IC_5:
+		pr_debug("PP\n");
+		isProc = true;
+		mask = FS_PP_SRC_SEL_MASK;
+		offset = FS_PP_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_IC_12) ? FS_PP_SRC_ROT :	/*PP_ROT-> */
+		    0;
+		break;
+
+		/* ->PP_ROT */
+	case IDMA_IC_13:
+		pr_debug("PP_ROT\n");
+		isProc = true;
+		mask = FS_PP_ROT_SRC_SEL_MASK;
+		offset = FS_PP_ROT_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF :	/*PF-> */
+		    (out_dma == IDMA_IC_2) ? FS_ROT_SRC_PP :	/*PP-> */
+		    0;
+		break;
+
+		/* ->SDC_BG */
+	case IDMA_SDC_BG:
+		pr_debug("SDC_BG\n");
+		isProc = false;
+		mask = FS_SDC_BG_SRC_SEL_MASK;
+		offset = FS_SDC_BG_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF :	/*VF_ROT-> */
+		    (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP :	/*PP_ROT-> */
+		    (out_dma == IDMA_IC_1) ? FS_SRC_VF :	/*VF-> */
+		    (out_dma == IDMA_IC_2) ? FS_SRC_PP :	/*PP-> */
+		    0;
+		break;
+
+		/* ->SDC_FG */
+	case IDMA_SDC_FG:
+		pr_debug("SDC_FG\n");
+		isProc = false;
+		mask = FS_SDC_FG_SRC_SEL_MASK;
+		offset = FS_SDC_FG_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF :	/*VF_ROT-> */
+		    (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP :	/*PP_ROT-> */
+		    (out_dma == IDMA_IC_1) ? FS_SRC_VF :	/*VF-> */
+		    (out_dma == IDMA_IC_2) ? FS_SRC_PP :	/*PP-> */
+		    0;
+		break;
+
+		/* ->ADC1 */
+	case IDMA_ADC_SYS1_WR:
+		pr_debug("ADC_SYS1\n");
+		isProc = false;
+		mask = FS_ADC1_SRC_SEL_MASK;
+		offset = FS_ADC1_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF :	/*VF_ROT-> */
+		    (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP :	/*PP_ROT-> */
+		    (out_dma == IDMA_IC_1) ? FS_SRC_VF :	/*VF-> */
+		    (out_dma == IDMA_IC_2) ? FS_SRC_PP :	/*PP-> */
+		    0;
+		break;
+
+		/* ->ADC2 */
+	case IDMA_ADC_SYS2_WR:
+		pr_debug("ADC_SYS2\n");
+		isProc = false;
+		mask = FS_ADC2_SRC_SEL_MASK;
+		offset = FS_ADC2_SRC_SEL_OFFSET;
+		value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF :	/*VF_ROT-> */
+		    (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP :	/*PP_ROT-> */
+		    (out_dma == IDMA_IC_1) ? FS_SRC_VF :	/*VF-> */
+		    (out_dma == IDMA_IC_2) ? FS_SRC_PP :	/*PP-> */
+		    0;
+		break;
+
+		/*Invalid chains: */
+		/* ->ENC, ->VF, ->PF, ->VF_COMBINE, ->PP_COMBINE */
+	default:
+		pr_debug("Invalid\n");
+		value = 0;
+		break;
+
+	}
+
+	if (value) {
+		if (isProc) {
+			fs_proc_flow &= ~mask;
+			fs_proc_flow |= (value << offset);
+		} else {
+			fs_disp_flow &= ~mask;
+			fs_disp_flow |= (value << offset);
+		}
+	} else {
+		dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n",
+			out_dma, in_dma);
+		return -EINVAL;
+	}
+
+	__raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW);
+	__raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+
+/*!
+ * This function unlinks 2 channels and disables automatic frame
+ * synchronization.
+ *
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	unsigned long lock_flags;
+	uint32_t out_dma;
+	uint32_t in_dma;
+	uint32_t fs_proc_flow;
+	uint32_t fs_disp_flow;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW);
+	fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW);
+
+	out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER));
+	in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER));
+
+	/*clear the src_ch's output destination */
+	switch (out_dma) {
+		/*VF-> */
+	case IDMA_IC_1:
+		pr_debug("Unlink VF->");
+		fs_proc_flow &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+
+		/*VF_ROT-> */
+	case IDMA_IC_9:
+		pr_debug("Unlink VF_Rot->");
+		fs_proc_flow &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
+		break;
+
+		/*ENC-> */
+	case IDMA_IC_0:
+		pr_debug("Unlink ENC->");
+		fs_proc_flow &= ~FS_PRPENC_DEST_SEL;
+		break;
+
+		/*PP-> */
+	case IDMA_IC_2:
+		pr_debug("Unlink PP->");
+		fs_proc_flow &= ~FS_PP_DEST_SEL_MASK;
+		break;
+
+		/*PP_ROT-> */
+	case IDMA_IC_12:
+		pr_debug("Unlink PP_ROT->");
+		fs_proc_flow &= ~FS_PP_ROT_DEST_SEL_MASK;
+		break;
+
+		/*PF-> */
+	case IDMA_PF_Y_OUT:
+	case IDMA_PF_U_OUT:
+	case IDMA_PF_V_OUT:
+		pr_debug("Unlink PF->");
+		fs_proc_flow &= ~FS_PF_DEST_SEL_MASK;
+		break;
+
+	default:		/*ENC_ROT->     */
+		pr_debug("Unlink Invalid->");
+		break;
+	}
+
+	/*clear the dest_ch's input source */
+	switch (in_dma) {
+	/*->VF_ROT*/
+	case IDMA_IC_11:
+		pr_debug("VF_ROT\n");
+		fs_proc_flow &= ~FS_PRPVF_ROT_SRC_SEL;
+		break;
+
+	/*->Enc_ROT*/
+	case IDMA_IC_10:
+		pr_debug("ENC_ROT\n");
+		fs_proc_flow &= ~FS_PRPENC_ROT_SRC_SEL;
+		break;
+
+	/*->PP*/
+	case IDMA_IC_5:
+		pr_debug("PP\n");
+		fs_proc_flow &= ~FS_PP_SRC_SEL_MASK;
+		break;
+
+	/*->PP_ROT*/
+	case IDMA_IC_13:
+		pr_debug("PP_ROT\n");
+		fs_proc_flow &= ~FS_PP_ROT_SRC_SEL_MASK;
+		break;
+
+	/*->SDC_FG*/
+	case IDMA_SDC_FG:
+		pr_debug("SDC_FG\n");
+		fs_disp_flow &= ~FS_SDC_FG_SRC_SEL_MASK;
+		break;
+
+	/*->SDC_BG*/
+	case IDMA_SDC_BG:
+		pr_debug("SDC_BG\n");
+		fs_disp_flow &= ~FS_SDC_BG_SRC_SEL_MASK;
+		break;
+
+	/*->ADC1*/
+	case IDMA_ADC_SYS1_WR:
+		pr_debug("ADC_SYS1\n");
+		fs_disp_flow &= ~FS_ADC1_SRC_SEL_MASK;
+		break;
+
+	/*->ADC2*/
+	case IDMA_ADC_SYS2_WR:
+		pr_debug("ADC_SYS2\n");
+		fs_disp_flow &= ~FS_ADC2_SRC_SEL_MASK;
+		break;
+
+	default:		/*->VF, ->ENC, ->VF_COMBINE, ->PP_COMBINE, ->PF*/
+		pr_debug("Invalid\n");
+		break;
+	}
+
+	__raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW);
+	__raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+
+/*!
+ * This function check whether a logical channel was enabled.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 1 while request channel is enabled or
+ *              0 for not enabled.
+ */
+int32_t ipu_is_channel_busy(ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER);
+
+	reg = __raw_readl(IDMAC_CHA_EN);
+
+	if (reg & ((1UL << out_dma) | (1UL << in_dma)))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(ipu_is_channel_busy);
+
+/*!
+ * This function enables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_channel(ipu_channel_t channel)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+	uint32_t in_dma;
+	uint32_t sec_dma;
+	uint32_t out_dma;
+	uint32_t chan_mask = 0;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IDMAC_CHA_EN);
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	if (out_dma != IDMA_CHAN_INVALID)
+		reg |= 1UL << out_dma;
+	in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER);
+	if (in_dma != IDMA_CHAN_INVALID)
+		reg |= 1UL << in_dma;
+
+	/* Get secondary input dma channel */
+	if (g_sec_chan_en[IPU_CHAN_ID(channel)]) {
+		sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER);
+		if (sec_dma != IDMA_CHAN_INVALID) {
+			reg |= 1UL << sec_dma;
+		}
+	}
+
+	__raw_writel(reg | chan_mask, IDMAC_CHA_EN);
+
+	if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) {
+		_ipu_ic_enable_task(channel);
+	} else if (channel == MEM_SDC_BG) {
+		dev_dbg(g_ipu_dev, "Initializing SDC BG\n");
+		_ipu_sdc_bg_init(NULL);
+	} else if (channel == MEM_SDC_FG) {
+		dev_dbg(g_ipu_dev, "Initializing SDC FG\n");
+		_ipu_sdc_fg_init(NULL);
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+
+/*!
+ * This function clear buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	/*TODO*/
+}
+EXPORT_SYMBOL(ipu_clear_buffer_ready);
+
+uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type)
+{
+	uint32_t reg, dma_chan;
+
+	dma_chan = channel_2_dma(channel, type);
+
+	reg = __raw_readl(IPU_CHA_CUR_BUF);
+	if (reg & (1UL << dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
+
+/*!
+ * This function disables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       wait_for_stop   Flag to set whether to wait for channel end
+ *                              of frame or return immediately.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+	uint32_t sec_dma;
+	uint32_t in_dma;
+	uint32_t out_dma;
+	uint32_t chan_mask = 0;
+	uint32_t timeout;
+	uint32_t eof_intr;
+	uint32_t enabled;
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	if (out_dma != IDMA_CHAN_INVALID)
+		chan_mask = 1UL << out_dma;
+	in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER);
+	if (in_dma != IDMA_CHAN_INVALID)
+		chan_mask |= 1UL << in_dma;
+	sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER);
+	if (sec_dma != IDMA_CHAN_INVALID)
+		chan_mask |= 1UL << sec_dma;
+
+	if (wait_for_stop && channel != MEM_SDC_FG && channel != MEM_SDC_BG) {
+		timeout = 40;
+		while ((__raw_readl(IDMAC_CHA_BUSY) & chan_mask) ||
+		       (_ipu_channel_status(channel) == TASK_STAT_ACTIVE)) {
+			timeout--;
+			msleep(10);
+			if (timeout == 0) {
+				printk
+				    (KERN_INFO
+				     "MXC IPU: Warning - timeout waiting for channel to stop,\n"
+				     "\tbuf0_rdy = 0x%08X, buf1_rdy = 0x%08X\n"
+				     "\tbusy = 0x%08X, tstat = 0x%08X\n\tmask = 0x%08X\n",
+				     __raw_readl(IPU_CHA_BUF0_RDY),
+				     __raw_readl(IPU_CHA_BUF1_RDY),
+				     __raw_readl(IDMAC_CHA_BUSY),
+				     __raw_readl(IPU_TASKS_STAT), chan_mask);
+				break;
+			}
+		}
+		dev_dbg(g_ipu_dev, "timeout = %d * 10ms\n", 40 - timeout);
+	}
+	/* SDC BG and FG must be disabled before DMA is disabled */
+	if ((channel == MEM_SDC_BG) || (channel == MEM_SDC_FG)) {
+
+		if (channel == MEM_SDC_BG)
+			eof_intr = IPU_IRQ_SDC_BG_EOF;
+		else
+			eof_intr = IPU_IRQ_SDC_FG_EOF;
+
+		/* Wait for any buffer flips to finsh */
+		timeout = 4;
+		while (timeout &&
+		       ((__raw_readl(IPU_CHA_BUF0_RDY) & chan_mask) ||
+			(__raw_readl(IPU_CHA_BUF1_RDY) & chan_mask))) {
+			msleep(10);
+			timeout--;
+		}
+
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+		ipu_clear_irq(eof_intr);
+		if (channel == MEM_SDC_BG)
+			enabled = _ipu_sdc_bg_uninit();
+		else
+			enabled = _ipu_sdc_fg_uninit();
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+		if (enabled && wait_for_stop) {
+			timeout = 5;
+		} else {
+			timeout = 0;
+		}
+		while (timeout && !ipu_get_irq_status(eof_intr)) {
+			msleep(5);
+			timeout--;
+		}
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	/* Disable IC task */
+	if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) {
+		_ipu_ic_disable_task(channel);
+	}
+
+	/* Disable DMA channel(s) */
+	reg = __raw_readl(IDMAC_CHA_EN);
+	__raw_writel(reg & ~chan_mask, IDMAC_CHA_EN);
+
+	/* Clear DMA related interrupts */
+	__raw_writel(chan_mask, IPU_INT_STAT_1);
+	__raw_writel(chan_mask, IPU_INT_STAT_2);
+	__raw_writel(chan_mask, IPU_INT_STAT_4);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+int32_t ipu_enable_csi(uint32_t csi)
+{
+	return 0;
+}
+
+
+int32_t ipu_disable_csi(uint32_t csi)
+{
+	return 0;
+}
+
+static
+irqreturn_t ipu_irq_handler(int irq, void *desc)
+{
+	uint32_t line_base = 0;
+	uint32_t line;
+	irqreturn_t result = IRQ_NONE;
+	uint32_t int_stat;
+
+	int_stat = __raw_readl(IPU_INT_STAT_1);
+	int_stat &= __raw_readl(IPU_INT_CTRL_1);
+	__raw_writel(int_stat, IPU_INT_STAT_1);
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		line += line_base - 1;
+		result |=
+		    ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id);
+	}
+
+	line_base = 32;
+	int_stat = __raw_readl(IPU_INT_STAT_2);
+	int_stat &= __raw_readl(IPU_INT_CTRL_2);
+	__raw_writel(int_stat, IPU_INT_STAT_2);
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		line += line_base - 1;
+		result |=
+		    ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id);
+	}
+
+	line_base = 64;
+	int_stat = __raw_readl(IPU_INT_STAT_3);
+	int_stat &= __raw_readl(IPU_INT_CTRL_3);
+	__raw_writel(int_stat, IPU_INT_STAT_3);
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		line += line_base - 1;
+		result |=
+		    ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id);
+	}
+
+	line_base = 96;
+	int_stat = __raw_readl(IPU_INT_STAT_4);
+	int_stat &= __raw_readl(IPU_INT_CTRL_4);
+	__raw_writel(int_stat, IPU_INT_STAT_4);
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		line += line_base - 1;
+		result |=
+		    ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id);
+	}
+
+	line_base = 128;
+	int_stat = __raw_readl(IPU_INT_STAT_5);
+	int_stat &= __raw_readl(IPU_INT_CTRL_5);
+	__raw_writel(int_stat, IPU_INT_STAT_5);
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		line += line_base - 1;
+		result |=
+		    ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id);
+	}
+
+	return result;
+}
+
+/*!
+ * This function enables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to enable interrupt for.
+ *
+ */
+void ipu_enable_irq(uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
+	reg |= IPUIRQ_2_MASK(irq);
+	__raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * This function disables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to disable interrupt for.
+ *
+ */
+void ipu_disable_irq(uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
+	reg &= ~IPUIRQ_2_MASK(irq);
+	__raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * This function clears the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to clear interrupt for.
+ *
+ */
+void ipu_clear_irq(uint32_t irq)
+{
+	__raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+}
+
+/*!
+ * This function returns the current interrupt status for the specified interrupt
+ * line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @return      Returns true if the interrupt is pending/asserted or false if
+ *              the interrupt is not pending.
+ */
+bool ipu_get_irq_status(uint32_t irq)
+{
+	uint32_t reg = __raw_readl(IPUIRQ_2_STATREG(irq));
+
+	if (reg & IPUIRQ_2_MASK(irq))
+		return true;
+	else
+		return false;
+}
+
+/*!
+ * This function registers an interrupt handler function for the specified
+ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       handler         Input parameter for address of the handler
+ *                              function.
+ *
+ * @param       irq_flags       Flags for interrupt mode. Currently not used.
+ *
+ * @param       devname         Input parameter for string name of driver
+ *                              registering the handler.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be passed
+ *                              to the handler.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int ipu_request_irq(uint32_t irq,
+		    irqreturn_t(*handler) (int, void *),
+		    uint32_t irq_flags, const char *devname, void *dev_id)
+{
+	unsigned long lock_flags;
+
+	BUG_ON(irq >= IPU_IRQ_COUNT);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (ipu_irq_list[irq].handler != NULL) {
+		dev_err(g_ipu_dev,
+			"ipu_request_irq - handler already installed on irq %d\n",
+			irq);
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	ipu_irq_list[irq].handler = handler;
+	ipu_irq_list[irq].flags = irq_flags;
+	ipu_irq_list[irq].dev_id = dev_id;
+	ipu_irq_list[irq].name = devname;
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	ipu_enable_irq(irq);	/* enable the interrupt */
+
+	return 0;
+}
+
+/*!
+ * This function unregisters an interrupt handler for the specified interrupt
+ * line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be passed
+ *                              to the handler. This must match value passed to
+ *                              ipu_request_irq().
+ *
+ */
+void ipu_free_irq(uint32_t irq, void *dev_id)
+{
+	ipu_disable_irq(irq);	/* disable the interrupt */
+
+	if (ipu_irq_list[irq].dev_id == dev_id) {
+		ipu_irq_list[irq].handler = NULL;
+	}
+}
+
+/*!
+ * This function sets the post-filter pause row for h.264 mode.
+ *
+ * @param       pause_row       The last row to process before pausing.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ *
+ */
+int32_t ipu_pf_set_pause_row(uint32_t pause_row)
+{
+	int32_t retval = 0;
+	uint32_t timeout = 5;
+	unsigned long lock_flags;
+	uint32_t reg;
+
+	reg = __raw_readl(IPU_TASKS_STAT);
+	while ((reg & TSTAT_PF_MASK) && ((reg & TSTAT_PF_H264_PAUSE) == 0)) {
+		timeout--;
+		msleep(5);
+		if (timeout == 0) {
+			dev_err(g_ipu_dev, "PF Timeout - tstat = 0x%08X\n",
+				__raw_readl(IPU_TASKS_STAT));
+			retval = -ETIMEDOUT;
+			goto err0;
+		}
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(PF_CONF);
+
+	/* Set the pause row */
+	if (pause_row) {
+		reg &= ~PF_CONF_PAUSE_ROW_MASK;
+		reg |= PF_CONF_PAUSE_EN | pause_row << PF_CONF_PAUSE_ROW_SHIFT;
+	} else {
+		reg &= ~(PF_CONF_PAUSE_EN | PF_CONF_PAUSE_ROW_MASK);
+	}
+	__raw_writel(reg, PF_CONF);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+      err0:
+	return retval;
+}
+
+/* Private functions */
+void _ipu_write_param_mem(uint32_t addr, uint32_t * data, uint32_t numWords)
+{
+	for (; numWords > 0; numWords--) {
+		dev_dbg(g_ipu_dev,
+			"write param mem - addr = 0x%08X, data = 0x%08X\n",
+			addr, *data);
+		__raw_writel(addr, IPU_IMA_ADDR);
+		__raw_writel(*data++, IPU_IMA_DATA);
+		addr++;
+		if ((addr & 0x7) == 5) {
+			addr &= ~0x7;	/* set to word 0 */
+			addr += 8;	/* increment to next row */
+		}
+	}
+}
+
+static void _ipu_pf_init(ipu_channel_params_t * params)
+{
+	uint32_t reg;
+
+	/*Setup the type of filtering required */
+	switch (params->mem_pf_mem.operation) {
+	case PF_MPEG4_DEBLOCK:
+	case PF_MPEG4_DERING:
+	case PF_MPEG4_DEBLOCK_DERING:
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true;
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false;
+		break;
+	case PF_H264_DEBLOCK:
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true;
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = true;
+		break;
+	default:
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false;
+		g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false;
+		return;
+		break;
+	}
+	reg = params->mem_pf_mem.operation;
+	__raw_writel(reg, PF_CONF);
+}
+
+static void _ipu_pf_uninit(void)
+{
+	__raw_writel(0x0L, PF_CONF);
+	g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false;
+	g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false;
+}
+
+uint32_t _ipu_channel_status(ipu_channel_t channel)
+{
+	uint32_t stat = 0;
+	uint32_t task_stat_reg = __raw_readl(IPU_TASKS_STAT);
+
+	switch (channel) {
+	case CSI_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
+		    TSTAT_CSI2MEM_OFFSET;
+		break;
+	case CSI_PRP_VF_ADC:
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_ADC:
+	case MEM_PRP_VF_MEM:
+		stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
+		    TSTAT_ENC_ROT_OFFSET;
+		break;
+	case MEM_PP_ADC:
+	case MEM_PP_MEM:
+		stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
+		break;
+
+	case MEM_PF_Y_MEM:
+	case MEM_PF_U_MEM:
+	case MEM_PF_V_MEM:
+		stat = (task_stat_reg & TSTAT_PF_MASK) >> TSTAT_PF_OFFSET;
+		break;
+	case MEM_SDC_BG:
+		break;
+	case MEM_SDC_FG:
+		break;
+	case ADC_SYS1:
+		stat =
+		    (task_stat_reg & TSTAT_ADCSYS1_MASK) >>
+		    TSTAT_ADCSYS1_OFFSET;
+		break;
+	case ADC_SYS2:
+		stat =
+		    (task_stat_reg & TSTAT_ADCSYS2_MASK) >>
+		    TSTAT_ADCSYS2_OFFSET;
+		break;
+	case MEM_SDC_MASK:
+	default:
+		stat = TASK_STAT_IDLE;
+		break;
+	}
+	return stat;
+}
+
+uint32_t bytes_per_pixel(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:	/*generic data */
+	case IPU_PIX_FMT_RGB332:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YUV422P:
+		return 1;
+		break;
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		return 2;
+		break;
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 3;
+		break;
+	case IPU_PIX_FMT_GENERIC_32:	/*generic data */
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_ABGR32:
+		return 4;
+		break;
+	default:
+		return 1;
+		break;
+	}
+	return 0;
+}
+
+void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3])
+{
+	/* TODO */
+}
+EXPORT_SYMBOL(ipu_set_csc_coefficients);
+
+ipu_color_space_t format_to_colorspace(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_RGB32:
+		return RGB;
+		break;
+
+	default:
+		return YCbCr;
+		break;
+	}
+	return RGB;
+
+}
+
+static u32 saved_disp3_time_conf;
+static bool in_lpdr_mode;
+static struct clk *default_ipu_parent_clk;
+
+int ipu_lowpwr_display_enable(void)
+{
+	unsigned long rate, div;
+	struct clk *parent_clk = g_ipu_clk;
+
+	if (in_lpdr_mode || IS_ERR(dfm_clk)) {
+		return -EINVAL;
+	}
+
+	if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) {
+		dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n");
+		return -EINVAL;
+	}
+
+	default_ipu_parent_clk = clk_get_parent(g_ipu_clk);
+	in_lpdr_mode = true;
+
+	/* Calculate current pixel clock rate */
+	rate = clk_get_rate(g_ipu_clk) * 16;
+	saved_disp3_time_conf = __raw_readl(DI_DISP3_TIME_CONF);
+	div = saved_disp3_time_conf & 0xFFF;
+	rate /= div;
+	rate *= 4;		/* min hsp clk is 4x pixel clk */
+
+	/* Initialize DFM clock */
+	rate = clk_round_rate(dfm_clk, rate);
+	clk_set_rate(dfm_clk, rate);
+	clk_enable(dfm_clk);
+
+	/* Wait for next VSYNC */
+	__raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC),
+		     IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC));
+	while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) &
+		IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0)
+		msleep_interruptible(1);
+
+	/* Set display clock divider to divide by 4 */
+	__raw_writel(((0x8) << 22) | 0x40, DI_DISP3_TIME_CONF);
+
+	clk_set_parent(parent_clk, dfm_clk);
+
+	return 0;
+}
+
+int ipu_lowpwr_display_disable(void)
+{
+	struct clk *parent_clk = g_ipu_clk;
+
+	if (!in_lpdr_mode || IS_ERR(dfm_clk)) {
+		return -EINVAL;
+	}
+
+	if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) {
+		dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n");
+		return -EINVAL;
+	}
+
+	in_lpdr_mode = false;
+
+	/* Wait for next VSYNC */
+	__raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC),
+		     IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC));
+	while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) &
+		IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0)
+		msleep_interruptible(1);
+
+	__raw_writel(saved_disp3_time_conf, DI_DISP3_TIME_CONF);
+	clk_set_parent(parent_clk, default_ipu_parent_clk);
+	clk_disable(dfm_clk);
+
+	return 0;
+}
+
+static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	if (cpu_is_mx31() || cpu_is_mx32()) {
+		/* work-around for i.Mx31 SR mode after camera related test */
+		if (g_csi_used) {
+			g_ipu_config = __raw_readl(IPU_CONF);
+			clk_enable(g_ipu_csi_clk);
+			__raw_writel(0x51, IPU_CONF);
+			g_channel_init_mask_backup = g_channel_init_mask;
+			g_channel_init_mask |= 2;
+		}
+	} else if (cpu_is_mx35()) {
+		g_ipu_config = __raw_readl(IPU_CONF);
+		/* Disable the clock of display otherwise the backlight cannot
+		 * be close after camera/tvin related test */
+		__raw_writel(g_ipu_config & 0xfbf, IPU_CONF);
+	}
+
+	return 0;
+}
+
+static int ipu_resume(struct platform_device *pdev)
+{
+	if (cpu_is_mx31() || cpu_is_mx32()) {
+		/* work-around for i.Mx31 SR mode after camera related test */
+		if (g_csi_used) {
+			__raw_writel(g_ipu_config, IPU_CONF);
+			clk_disable(g_ipu_csi_clk);
+			g_channel_init_mask = g_channel_init_mask_backup;
+		}
+	} else if (cpu_is_mx35()) {
+		__raw_writel(g_ipu_config, IPU_CONF);
+    }
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcipu_driver = {
+	.driver = {
+		   .name = "mxc_ipu",
+		   },
+	.probe = ipu_probe,
+	.suspend = ipu_suspend,
+	.resume = ipu_resume,
+};
+
+int32_t __init ipu_gen_init(void)
+{
+	int32_t ret;
+
+	ret = platform_driver_register(&mxcipu_driver);
+	return 0;
+}
+
+subsys_initcall(ipu_gen_init);
+
+static void __exit ipu_gen_uninit(void)
+{
+	if (g_ipu_irq[0])
+		free_irq(g_ipu_irq[0], 0);
+	if (g_ipu_irq[1])
+		free_irq(g_ipu_irq[1], 0);
+
+	platform_driver_unregister(&mxcipu_driver);
+}
+
+module_exit(ipu_gen_uninit);
+
+EXPORT_SYMBOL(ipu_init_channel);
+EXPORT_SYMBOL(ipu_uninit_channel);
+EXPORT_SYMBOL(ipu_init_channel_buffer);
+EXPORT_SYMBOL(ipu_unlink_channels);
+EXPORT_SYMBOL(ipu_update_channel_buffer);
+EXPORT_SYMBOL(ipu_select_buffer);
+EXPORT_SYMBOL(ipu_link_channels);
+EXPORT_SYMBOL(ipu_enable_channel);
+EXPORT_SYMBOL(ipu_disable_channel);
+EXPORT_SYMBOL(ipu_enable_csi);
+EXPORT_SYMBOL(ipu_disable_csi);
+EXPORT_SYMBOL(ipu_enable_irq);
+EXPORT_SYMBOL(ipu_disable_irq);
+EXPORT_SYMBOL(ipu_clear_irq);
+EXPORT_SYMBOL(ipu_get_irq_status);
+EXPORT_SYMBOL(ipu_request_irq);
+EXPORT_SYMBOL(ipu_free_irq);
+EXPORT_SYMBOL(ipu_pf_set_pause_row);
+EXPORT_SYMBOL(bytes_per_pixel);
diff --git a/drivers/mxc/ipu/ipu_csi.c b/drivers/mxc/ipu/ipu_csi.c
new file mode 100644
index 000000000000..58d58c10af51
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_csi.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_csi.c
+ *
+ * @brief IPU CMOS Sensor interface functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+
+static bool gipu_csi_get_mclk_flag = false;
+static int csi_mclk_flag = 0;
+
+extern void gpio_sensor_suspend(bool flag);
+
+/*!
+ * ipu_csi_init_interface
+ *    Sets initial values for the CSI registers.
+ *    The width and height of the sensor and the actual frame size will be
+ *    set to the same values.
+ * @param       width        Sensor width
+ * @param       height       Sensor height
+ * @param       pixel_fmt    pixel format
+ * @param       sig          ipu_csi_signal_cfg_t structure
+ *
+ * @return      0 for success, -EINVAL for error
+ */
+int32_t
+ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt,
+		       ipu_csi_signal_cfg_t sig)
+{
+	uint32_t data = 0;
+
+	/* Set SENS_DATA_FORMAT bits (8 and 9)
+	   RGB or YUV444 is 0 which is current value in data so not set explicitly
+	   This is also the default value if attempts are made to set it to
+	   something invalid. */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_UYVY:
+		data = CSI_SENS_CONF_DATA_FMT_YUV422;
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR24:
+		data = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
+		break;
+	case IPU_PIX_FMT_GENERIC:
+		data = CSI_SENS_CONF_DATA_FMT_BAYER;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set the CSI_SENS_CONF register remaining fields */
+	data |= sig.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
+	    sig.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
+	    sig.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
+	    sig.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
+	    sig.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
+	    sig.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
+	    sig.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
+	    sig.sens_clksrc << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
+
+	__raw_writel(data, CSI_SENS_CONF);
+
+	/* Setup frame size     */
+	__raw_writel(width | height << 16, CSI_SENS_FRM_SIZE);
+
+	__raw_writel(width << 16, CSI_FLASH_STROBE_1);
+	__raw_writel(height << 16 | 0x22, CSI_FLASH_STROBE_2);
+
+	/* Set CCIR registers */
+	if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
+		__raw_writel(0x40030, CSI_CCIR_CODE_1);
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3);
+	} else if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
+		__raw_writel(0xD07DF, CSI_CCIR_CODE_1);
+		__raw_writel(0x40596, CSI_CCIR_CODE_2);
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3);
+	}
+
+	dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n",
+		__raw_readl(CSI_SENS_CONF));
+	dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
+		__raw_readl(CSI_ACT_FRM_SIZE));
+
+	return 0;
+}
+
+/*!
+ * ipu_csi_flash_strobe
+ *
+ * @param       flag         true to turn on flash strobe
+ *
+ * @return      0 for success
+ */
+void ipu_csi_flash_strobe(bool flag)
+{
+	if (flag == true) {
+		__raw_writel(__raw_readl(CSI_FLASH_STROBE_2) | 0x1,
+			     CSI_FLASH_STROBE_2);
+	}
+}
+
+/*!
+ * ipu_csi_enable_mclk
+ *
+ * @param       src         enum define which source to control the clk
+ *                          CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C
+ * @param       flag        true to enable mclk, false to disable mclk
+ * @param       wait        true to wait 100ms make clock stable, false not wait
+ *
+ * @return      0 for success
+ */
+int32_t ipu_csi_enable_mclk(int src, bool flag, bool wait)
+{
+	if (flag == true) {
+		csi_mclk_flag |= src;
+	} else {
+		csi_mclk_flag &= ~src;
+	}
+
+	if (gipu_csi_get_mclk_flag == flag)
+		return 0;
+
+	if (flag == true) {
+		clk_enable(g_ipu_csi_clk);
+		if (wait == true)
+			msleep(10);
+		/*printk("enable csi clock from source %d\n", src);     */
+		gipu_csi_get_mclk_flag = true;
+	} else if (csi_mclk_flag == 0) {
+		clk_disable(g_ipu_csi_clk);
+		/*printk("disable csi clock from source %d\n", src); */
+		gipu_csi_get_mclk_flag = flag;
+	}
+
+	return 0;
+}
+
+/*!
+ * ipu_csi_read_mclk_flag
+ *
+ * @return  csi_mclk_flag
+ */
+int ipu_csi_read_mclk_flag(void)
+{
+	return csi_mclk_flag;
+}
+
+/*!
+ * ipu_csi_get_window_size
+ *
+ * @param       width        pointer to window width
+ * @param       height       pointer to window height
+ * @param       dummy        dummy for IPUv1 to keep the same interface with IPUv3
+ *
+ */
+void ipu_csi_get_window_size(uint32_t *width, uint32_t *height,
+		uint32_t dummy)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(CSI_ACT_FRM_SIZE);
+	*width = (reg & 0xFFFF) + 1;
+	*height = (reg >> 16 & 0xFFFF) + 1;
+}
+
+/*!
+ * ipu_csi_set_window_size
+ *
+ * @param       width        window width
+ * @param       height       window height
+ * @param       dummy        dummy for IPUv1 to keep the same interface with IPUv3
+ *
+ */
+void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t dummy)
+{
+	__raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
+}
+
+/*!
+ * ipu_csi_set_window_pos
+ *
+ * @param       left        uint32 window x start
+ * @param       top         uint32 window y start
+ * @param       dummy       dummy for IPUv1 to keep the same interface with IPUv3
+ *
+ */
+void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t dummy)
+{
+	uint32_t temp = __raw_readl(CSI_OUT_FRM_CTRL);
+	temp &= 0xffff0000;
+	temp = top | (left << 8) | temp;
+	__raw_writel(temp, CSI_OUT_FRM_CTRL);
+}
+
+/* Exported symbols for modules. */
+EXPORT_SYMBOL(ipu_csi_set_window_pos);
+EXPORT_SYMBOL(ipu_csi_set_window_size);
+EXPORT_SYMBOL(ipu_csi_get_window_size);
+EXPORT_SYMBOL(ipu_csi_read_mclk_flag);
+EXPORT_SYMBOL(ipu_csi_enable_mclk);
+EXPORT_SYMBOL(ipu_csi_flash_strobe);
+EXPORT_SYMBOL(ipu_csi_init_interface);
diff --git a/drivers/mxc/ipu/ipu_device.c b/drivers/mxc/ipu/ipu_device.c
new file mode 100644
index 000000000000..5fd1c51ec9b1
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_device.c
@@ -0,0 +1,696 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_device.c
+ *
+ * @brief This file contains the IPU driver device interface and fops functions.
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+/* Strucutures and variables for exporting MXC IPU as device*/
+
+#define MAX_Q_SIZE 10
+
+static int mxc_ipu_major;
+static struct class *mxc_ipu_class;
+
+DEFINE_SPINLOCK(queue_lock);
+static DECLARE_MUTEX(user_mutex);
+
+static wait_queue_head_t waitq;
+static int pending_events = 0;
+int read_ptr = 0;
+int write_ptr = 0;
+
+ipu_event_info events[MAX_Q_SIZE];
+
+int register_ipu_device(void);
+
+/* Static functions */
+
+int get_events(ipu_event_info *p)
+{
+	unsigned long flags;
+	int ret = 0, i, cnt, found = 0;
+	spin_lock_irqsave(&queue_lock, flags);
+	if (pending_events != 0) {
+		if (write_ptr > read_ptr)
+			cnt = write_ptr - read_ptr;
+		else
+			cnt = MAX_Q_SIZE - read_ptr + write_ptr;
+		for (i = 0; i < cnt; i++) {
+			if (p->irq == events[read_ptr].irq) {
+				*p = events[read_ptr];
+				events[read_ptr].irq = 0;
+				read_ptr++;
+				if (read_ptr >= MAX_Q_SIZE)
+					read_ptr = 0;
+				found = 1;
+				break;
+			}
+
+			if (events[read_ptr].irq) {
+				events[write_ptr] = events[read_ptr];
+				events[read_ptr].irq = 0;
+				write_ptr++;
+				if (write_ptr >= MAX_Q_SIZE)
+					write_ptr = 0;
+			} else
+				pending_events--;
+
+			read_ptr++;
+			if (read_ptr >= MAX_Q_SIZE)
+				read_ptr = 0;
+		}
+		if (found)
+			pending_events--;
+		else
+			ret = -1;
+	} else {
+		ret = -1;
+	}
+
+	spin_unlock_irqrestore(&queue_lock, flags);
+	return ret;
+}
+
+static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id)
+{
+	ipu_event_info e;
+
+	e.irq = irq;
+	e.dev = dev_id;
+	events[write_ptr] = e;
+	write_ptr++;
+	if (write_ptr >= MAX_Q_SIZE)
+		write_ptr = 0;
+	pending_events++;
+	/* Wakeup any blocking user context */
+	wake_up_interruptible(&waitq);
+	return IRQ_HANDLED;
+}
+
+static int mxc_ipu_open(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+	return ret;
+}
+static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+
+	case IPU_INIT_CHANNEL:
+		{
+			ipu_channel_parm parm;
+			if (copy_from_user
+			    (&parm, (ipu_channel_parm *) arg,
+			     sizeof(ipu_channel_parm))) {
+				return -EFAULT;
+			}
+			if (!parm.flag) {
+				ret =
+				    ipu_init_channel(parm.channel,
+						     &parm.params);
+			} else {
+				ret = ipu_init_channel(parm.channel, NULL);
+			}
+		}
+		break;
+
+	case IPU_UNINIT_CHANNEL:
+		{
+			ipu_channel_t ch;
+			int __user *argp = (void __user *)arg;
+			if (get_user(ch, argp))
+				return -EFAULT;
+			ipu_uninit_channel(ch);
+		}
+		break;
+
+	case IPU_INIT_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+			    (&parm, (ipu_channel_buf_parm *) arg,
+			     sizeof(ipu_channel_buf_parm))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_init_channel_buffer(parm.channel, parm.type,
+						    parm.pixel_fmt,
+						    parm.width, parm.height,
+						    parm.stride,
+						    parm.rot_mode,
+						    parm.phyaddr_0,
+						    parm.phyaddr_1,
+						    parm.u_offset,
+						    parm.v_offset);
+
+		}
+		break;
+
+	case IPU_UPDATE_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+			    (&parm, (ipu_channel_buf_parm *) arg,
+			     sizeof(ipu_channel_buf_parm))) {
+				return -EFAULT;
+			}
+			if ((parm.phyaddr_0 != (dma_addr_t) NULL)
+			    && (parm.phyaddr_1 == (dma_addr_t) NULL)) {
+				ret =
+				    ipu_update_channel_buffer(parm.channel,
+							      parm.type,
+							      parm.bufNum,
+							      parm.phyaddr_0);
+			} else if ((parm.phyaddr_0 == (dma_addr_t) NULL)
+				   && (parm.phyaddr_1 != (dma_addr_t) NULL)) {
+				ret =
+				    ipu_update_channel_buffer(parm.channel,
+							      parm.type,
+							      parm.bufNum,
+							      parm.phyaddr_1);
+			} else {
+				ret = -1;
+			}
+
+		}
+		break;
+	case IPU_SELECT_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+			    (&parm, (ipu_channel_buf_parm *) arg,
+			     sizeof(ipu_channel_buf_parm))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_select_buffer(parm.channel, parm.type,
+					      parm.bufNum);
+
+		}
+		break;
+	case IPU_LINK_CHANNELS:
+		{
+			ipu_channel_link link;
+			if (copy_from_user
+			    (&link, (ipu_channel_link *) arg,
+			     sizeof(ipu_channel_link))) {
+				return -EFAULT;
+			}
+			ret = ipu_link_channels(link.src_ch, link.dest_ch);
+
+		}
+		break;
+	case IPU_UNLINK_CHANNELS:
+		{
+			ipu_channel_link link;
+			if (copy_from_user
+			    (&link, (ipu_channel_link *) arg,
+			     sizeof(ipu_channel_link))) {
+				return -EFAULT;
+			}
+			ret = ipu_unlink_channels(link.src_ch, link.dest_ch);
+
+		}
+		break;
+	case IPU_ENABLE_CHANNEL:
+		{
+			ipu_channel_t ch;
+			int __user *argp = (void __user *)arg;
+			if (get_user(ch, argp))
+				return -EFAULT;
+			ipu_enable_channel(ch);
+		}
+		break;
+	case IPU_DISABLE_CHANNEL:
+		{
+			ipu_channel_info info;
+			if (copy_from_user
+			    (&info, (ipu_channel_info *) arg,
+			     sizeof(ipu_channel_info))) {
+				return -EFAULT;
+			}
+			ret = ipu_disable_channel(info.channel, info.stop);
+		}
+		break;
+	case IPU_ENABLE_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_enable_irq(irq);
+		}
+		break;
+	case IPU_DISABLE_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_disable_irq(irq);
+		}
+		break;
+	case IPU_CLEAR_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_clear_irq(irq);
+		}
+		break;
+	case IPU_FREE_IRQ:
+		{
+			ipu_irq_info info;
+			if (copy_from_user
+			    (&info, (ipu_irq_info *) arg,
+			     sizeof(ipu_irq_info))) {
+				return -EFAULT;
+			}
+			ipu_free_irq(info.irq, info.dev_id);
+		}
+		break;
+	case IPU_REQUEST_IRQ_STATUS:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ret = ipu_get_irq_status(irq);
+		}
+		break;
+	case IPU_SDC_INIT_PANEL:
+		{
+			ipu_sdc_panel_info sinfo;
+			if (copy_from_user
+			    (&sinfo, (ipu_sdc_panel_info *) arg,
+			     sizeof(ipu_sdc_panel_info))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_sdc_init_panel(sinfo.panel, sinfo.pixel_clk,
+					       sinfo.width, sinfo.height,
+					       sinfo.pixel_fmt,
+					       sinfo.hStartWidth,
+					       sinfo.hSyncWidth,
+					       sinfo.hEndWidth,
+					       sinfo.vStartWidth,
+					       sinfo.vSyncWidth,
+					       sinfo.vEndWidth, sinfo.signal);
+		}
+		break;
+	case IPU_SDC_SET_WIN_POS:
+		{
+			ipu_sdc_window_pos pos;
+			if (copy_from_user
+			    (&pos, (ipu_sdc_window_pos *) arg,
+			     sizeof(ipu_sdc_window_pos))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_disp_set_window_pos(pos.channel, pos.x_pos,
+						   pos.y_pos);
+
+		}
+		break;
+	case IPU_SDC_SET_GLOBAL_ALPHA:
+		{
+			ipu_sdc_global_alpha g;
+			if (copy_from_user
+			    (&g, (ipu_sdc_global_alpha *) arg,
+			     sizeof(ipu_sdc_global_alpha))) {
+				return -EFAULT;
+			}
+			ret = ipu_sdc_set_global_alpha(g.enable, g.alpha);
+		}
+		break;
+	case IPU_SDC_SET_COLOR_KEY:
+		{
+			ipu_sdc_color_key c;
+			if (copy_from_user
+			    (&c, (ipu_sdc_color_key *) arg,
+			     sizeof(ipu_sdc_color_key))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_sdc_set_color_key(c.channel, c.enable,
+						  c.colorKey);
+		}
+		break;
+	case IPU_SDC_SET_BRIGHTNESS:
+		{
+			uint8_t b;
+			int __user *argp = (void __user *)arg;
+			if (get_user(b, argp))
+				return -EFAULT;
+			ret = ipu_sdc_set_brightness(b);
+
+		}
+		break;
+	case IPU_REGISTER_GENERIC_ISR:
+		{
+			ipu_event_info info;
+			if (copy_from_user
+			    (&info, (ipu_event_info *) arg,
+			     sizeof(ipu_event_info))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_request_irq(info.irq, mxc_ipu_generic_handler,
+					    0, "video_sink", info.dev);
+		}
+		break;
+	case IPU_GET_EVENT:
+		/* User will have to allocate event_type structure and pass the pointer in arg */
+		{
+			ipu_event_info info;
+			int r = -1;
+
+			if (copy_from_user
+					(&info, (ipu_event_info *) arg,
+					 sizeof(ipu_event_info)))
+				return -EFAULT;
+
+			r = get_events(&info);
+			if (r == -1) {
+				wait_event_interruptible_timeout(waitq,
+						(pending_events != 0), 2 * HZ);
+				r = get_events(&info);
+			}
+			ret = -1;
+			if (r == 0) {
+				if (!copy_to_user((ipu_event_info *) arg,
+					&info, sizeof(ipu_event_info)))
+					ret = 0;
+			}
+		}
+		break;
+	case IPU_ADC_WRITE_TEMPLATE:
+		{
+			ipu_adc_template temp;
+			if (copy_from_user
+			    (&temp, (ipu_adc_template *) arg, sizeof(temp))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_write_template(temp.disp, temp.pCmd,
+						   temp.write);
+		}
+		break;
+	case IPU_ADC_UPDATE:
+		{
+			ipu_adc_update update;
+			if (copy_from_user
+			    (&update, (ipu_adc_update *) arg, sizeof(update))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_set_update_mode(update.channel, update.mode,
+						    update.refresh_rate,
+						    update.addr, update.size);
+		}
+		break;
+	case IPU_ADC_SNOOP:
+		{
+			ipu_adc_snoop snoop;
+			if (copy_from_user
+			    (&snoop, (ipu_adc_snoop *) arg, sizeof(snoop))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_get_snooping_status(snoop.statl,
+							snoop.stath);
+		}
+		break;
+	case IPU_ADC_CMD:
+		{
+			ipu_adc_cmd cmd;
+			if (copy_from_user
+			    (&cmd, (ipu_adc_cmd *) arg, sizeof(cmd))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_write_cmd(cmd.disp, cmd.type, cmd.cmd,
+					      cmd.params, cmd.numParams);
+		}
+		break;
+	case IPU_ADC_INIT_PANEL:
+		{
+			ipu_adc_panel panel;
+			if (copy_from_user
+			    (&panel, (ipu_adc_panel *) arg, sizeof(panel))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_init_panel(panel.disp, panel.width,
+					       panel.height, panel.pixel_fmt,
+					       panel.stride, panel.signal,
+					       panel.addr, panel.vsync_width,
+					       panel.mode);
+		}
+		break;
+	case IPU_ADC_IFC_TIMING:
+		{
+			ipu_adc_ifc_timing t;
+			if (copy_from_user
+			    (&t, (ipu_adc_ifc_timing *) arg, sizeof(t))) {
+				return -EFAULT;
+			}
+			ret =
+			    ipu_adc_init_ifc_timing(t.disp, t.read,
+						    t.cycle_time, t.up_time,
+						    t.down_time,
+						    t.read_latch_time,
+						    t.pixel_clk);
+		}
+		break;
+	case IPU_CSI_INIT_INTERFACE:
+		{
+			ipu_csi_interface c;
+			if (copy_from_user
+			    (&c, (ipu_csi_interface *) arg, sizeof(c)))
+				return -EFAULT;
+			ret =
+			    ipu_csi_init_interface(c.width, c.height,
+						   c.pixel_fmt, c.signal);
+		}
+		break;
+	case IPU_CSI_ENABLE_MCLK:
+		{
+			ipu_csi_mclk m;
+			if (copy_from_user(&m, (ipu_csi_mclk *) arg, sizeof(m)))
+				return -EFAULT;
+			ret = ipu_csi_enable_mclk(m.src, m.flag, m.wait);
+		}
+		break;
+	case IPU_CSI_READ_MCLK_FLAG:
+		{
+			ret = ipu_csi_read_mclk_flag();
+		}
+		break;
+	case IPU_CSI_FLASH_STROBE:
+		{
+			bool strobe;
+			int __user *argp = (void __user *)arg;
+			if (get_user(strobe, argp))
+				return -EFAULT;
+			ipu_csi_flash_strobe(strobe);
+		}
+		break;
+	case IPU_CSI_GET_WIN_SIZE:
+		{
+			ipu_csi_window_size w;
+			int dummy = 0;
+			ipu_csi_get_window_size(&w.width, &w.height, dummy);
+			if (copy_to_user
+			    ((ipu_csi_window_size *) arg, &w, sizeof(w)))
+				return -EFAULT;
+		}
+		break;
+	case IPU_CSI_SET_WIN_SIZE:
+		{
+			ipu_csi_window_size w;
+			int dummy = 0;
+			if (copy_from_user
+			    (&w, (ipu_csi_window_size *) arg, sizeof(w)))
+				return -EFAULT;
+			ipu_csi_set_window_size(w.width, w.height, dummy);
+		}
+		break;
+	case IPU_CSI_SET_WINDOW:
+		{
+			ipu_csi_window p;
+			int dummy = 0;
+			if (copy_from_user
+			    (&p, (ipu_csi_window *) arg, sizeof(p)))
+				return -EFAULT;
+			ipu_csi_set_window_pos(p.left, p.top, dummy);
+		}
+		break;
+	case IPU_PF_SET_PAUSE_ROW:
+		{
+			uint32_t p;
+			int __user *argp = (void __user *)arg;
+			if (get_user(p, argp))
+				return -EFAULT;
+			ret = ipu_pf_set_pause_row(p);
+		}
+		break;
+	case IPU_ALOC_MEM:
+		{
+			ipu_mem_info info;
+			if (copy_from_user
+					(&info, (ipu_mem_info *) arg,
+					 sizeof(ipu_mem_info)))
+				return -EFAULT;
+
+			info.vaddr = dma_alloc_coherent(0,
+					PAGE_ALIGN(info.size),
+					&info.paddr,
+					GFP_DMA | GFP_KERNEL);
+			if (info.vaddr == 0) {
+				printk(KERN_ERR "dma alloc failed!\n");
+				return -ENOBUFS;
+			}
+			if (copy_to_user((ipu_mem_info *) arg, &info,
+					sizeof(ipu_mem_info)) > 0)
+				return -EFAULT;
+		}
+		break;
+	case IPU_FREE_MEM:
+		{
+			ipu_mem_info info;
+			if (copy_from_user
+					(&info, (ipu_mem_info *) arg,
+					 sizeof(ipu_mem_info)))
+				return -EFAULT;
+
+			if (info.vaddr != 0)
+				dma_free_coherent(0, PAGE_ALIGN(info.size),
+						info.vaddr, info.paddr);
+			else
+				return -EFAULT;
+		}
+		break;
+	case IPU_IS_CHAN_BUSY:
+		{
+			ipu_channel_t chan;
+			if (copy_from_user
+					(&chan, (ipu_channel_t *)arg,
+					 sizeof(ipu_channel_t)))
+				return -EFAULT;
+
+			if (ipu_is_channel_busy(chan))
+				ret = 1;
+			else
+				ret = 0;
+		}
+		break;
+	default:
+		break;
+
+	}
+	return ret;
+}
+
+static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+				vma->vm_end - vma->vm_start,
+				vma->vm_page_prot)) {
+		printk(KERN_ERR
+				"mmap failed!\n");
+		return -ENOBUFS;
+	}
+	return 0;
+}
+
+static int mxc_ipu_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static struct file_operations mxc_ipu_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_ipu_open,
+	.mmap = mxc_ipu_mmap,
+	.release = mxc_ipu_release,
+	.ioctl = mxc_ipu_ioctl
+};
+
+int register_ipu_device()
+{
+	int ret = 0;
+	struct device *temp;
+	mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
+	if (mxc_ipu_major < 0) {
+		printk(KERN_ERR
+		       "Unable to register Mxc Ipu as a char device\n");
+		return mxc_ipu_major;
+	}
+
+	mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu");
+	if (IS_ERR(mxc_ipu_class)) {
+		printk(KERN_ERR "Unable to create class for Mxc Ipu\n");
+		ret = PTR_ERR(mxc_ipu_class);
+		goto err1;
+	}
+
+	temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0), NULL,
+			     "mxc_ipu");
+
+	if (IS_ERR(temp)) {
+		printk(KERN_ERR "Unable to create class device for Mxc Ipu\n");
+		ret = PTR_ERR(temp);
+		goto err2;
+	}
+	spin_lock_init(&queue_lock);
+	init_waitqueue_head(&waitq);
+	return ret;
+
+      err2:
+	class_destroy(mxc_ipu_class);
+      err1:
+	unregister_chrdev(mxc_ipu_major, "mxc_ipu");
+	return ret;
+
+}
diff --git a/drivers/mxc/ipu/ipu_ic.c b/drivers/mxc/ipu/ipu_ic.c
new file mode 100644
index 000000000000..cdf823a2760b
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_ic.c
@@ -0,0 +1,592 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_ic.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+enum {
+	IC_TASK_VIEWFINDER,
+	IC_TASK_ENCODER,
+	IC_TASK_POST_PROCESSOR
+};
+
+extern int g_ipu_hw_rev;
+static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format);
+static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize,
+				uint32_t * resizeCoeff,
+				uint32_t * downsizeCoeff);
+
+void _ipu_ic_enable_task(ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = __raw_readl(IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_ADC:
+	case MEM_PRP_VF_ADC:
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_ADC:
+	case MEM_PP_MEM:
+		ic_conf |= IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf |= IC_CONF_PP_ROT_EN;
+		break;
+	case CSI_MEM:
+		// ???
+		ic_conf |= IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_disable_task(ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = __raw_readl(IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_ADC:
+	case MEM_PRP_VF_ADC:
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_ADC:
+	case MEM_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_ROT_EN;
+		break;
+	case CSI_MEM:
+		// ???
+		ic_conf &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN);
+		break;
+	default:
+		break;
+	}
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_init_prpvf(ipu_channel_params_t * params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	_calc_resize_coeffs(params->mem_prp_vf_mem.in_height,
+			    params->mem_prp_vf_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+
+	/* Setup horizontal resizing */
+	_calc_resize_coeffs(params->mem_prp_vf_mem.in_width,
+			    params->mem_prp_vf_mem.out_width,
+			    &resizeCoeff, &downsizeCoeff);
+	reg |= (downsizeCoeff << 14) | resizeCoeff;
+
+	__raw_writel(reg, IC_PRP_VF_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			_init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt);
+			ic_conf |= IC_CONF_PRPVF_CSC1;	/* Enable RGB->YCBCR CSC */
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			_init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB);
+			ic_conf |= IC_CONF_PRPVF_CSC1;	/* Enable YCBCR->RGB CSC */
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_prp_vf_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PRPVF_CMB;
+
+		/* need transparent CSC1 conversion */
+		_init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB);
+		ic_conf |= IC_CONF_PRPVF_CSC1;	/* Enable RGB->RGB CSC */
+
+		if (params->mem_prp_vf_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+		} else {
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+		}
+
+		if (params->mem_prp_vf_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+		} else {
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+		}
+	} else {
+		ic_conf &= ~IC_CONF_PP_CMB;
+	}
+
+#ifndef CONFIG_VIRTIO_SUPPORT	/* Setting RWS_EN doesn't work in Virtio */
+	if (src_is_csi) {
+		ic_conf &= ~IC_CONF_RWS_EN;
+	} else {
+		ic_conf |= IC_CONF_RWS_EN;
+	}
+#endif
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpvf(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
+		 IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_vf(ipu_channel_params_t * params)
+{
+}
+
+void _ipu_ic_uninit_rotate_vf(void)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_PRPVF_ROT_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_csi(ipu_channel_params_t * params)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_CSI_MEM_WR_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_uninit_csi(void)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_prpenc(ipu_channel_params_t * params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	_calc_resize_coeffs(params->mem_prp_enc_mem.in_height,
+			    params->mem_prp_enc_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+
+	/* Setup horizontal resizing */
+	_calc_resize_coeffs(params->mem_prp_enc_mem.in_width,
+			    params->mem_prp_enc_mem.out_width,
+			    &resizeCoeff, &downsizeCoeff);
+	reg |= (downsizeCoeff << 14) | resizeCoeff;
+
+	__raw_writel(reg, IC_PRP_ENC_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* TODO: ERROR! */
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			_init_csc(IC_TASK_ENCODER, YCbCr, RGB);
+			ic_conf |= IC_CONF_PRPENC_CSC1;	/* Enable YCBCR->RGB CSC */
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (src_is_csi) {
+		ic_conf &= ~IC_CONF_RWS_EN;
+	} else {
+		ic_conf |= IC_CONF_RWS_EN;
+	}
+
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpenc(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_enc(ipu_channel_params_t * params)
+{
+}
+
+void _ipu_ic_uninit_rotate_enc(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_ROT_EN);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_pp(ipu_channel_params_t * params)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	_calc_resize_coeffs(params->mem_pp_mem.in_height,
+			    params->mem_pp_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+
+	/* Setup horizontal resizing */
+	_calc_resize_coeffs(params->mem_pp_mem.in_width,
+			    params->mem_pp_mem.out_width,
+			    &resizeCoeff, &downsizeCoeff);
+	reg |= (downsizeCoeff << 14) | resizeCoeff;
+
+	__raw_writel(reg, IC_PP_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			_init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt);
+			ic_conf |= IC_CONF_PP_CSC2;	/* Enable RGB->YCBCR CSC */
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			_init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB);
+			ic_conf |= IC_CONF_PP_CSC1;	/* Enable YCBCR->RGB CSC */
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_pp_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PP_CMB;
+
+		/* need transparent CSC1 conversion */
+		_init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB);
+		ic_conf |= IC_CONF_PP_CSC1;	/* Enable RGB->RGB CSC */
+
+		if (params->mem_pp_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+		} else {
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+		}
+
+		if (params->mem_pp_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+		} else {
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+		}
+	} else {
+		ic_conf &= ~IC_CONF_PP_CMB;
+	}
+
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_pp(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
+		 IC_CONF_PP_CMB);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_pp(ipu_channel_params_t * params)
+{
+}
+
+void _ipu_ic_uninit_rotate_pp(void)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_PP_ROT_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format)
+{
+/*     Y = R *  .299 + G *  .587 + B *  .114;
+       U = R * -.169 + G * -.332 + B *  .500 + 128.;
+       V = R *  .500 + G * -.419 + B * -.0813 + 128.;*/
+	static const uint32_t rgb2ycbcr_coeff[4][3] = {
+		{0x004D, 0x0096, 0x001D},
+		{0x01D5, 0x01AB, 0x0080},
+		{0x0080, 0x0195, 0x01EB},
+		{0x0000, 0x0200, 0x0200},	/* A0, A1, A2 */
+	};
+
+	/* transparent RGB->RGB matrix for combining
+	 */
+	static const uint32_t rgb2rgb_coeff[4][3] = {
+		{0x0080, 0x0000, 0x0000},
+		{0x0000, 0x0080, 0x0000},
+		{0x0000, 0x0000, 0x0080},
+		{0x0000, 0x0000, 0x0000},	/* A0, A1, A2 */
+	};
+
+/*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+       G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+       B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
+	static const uint32_t ycbcr2rgb_coeff[4][3] = {
+		{149, 0, 204},
+		{149, 462, 408},
+		{149, 255, 0},
+		{8192 - 446, 266, 8192 - 554},	/* A0, A1, A2 */
+	};
+
+	uint32_t param[2];
+	uint32_t address = 0;
+
+	if (g_ipu_hw_rev > 1) {
+		if (ic_task == IC_TASK_VIEWFINDER) {
+			address = 0x645 << 3;
+		} else if (ic_task == IC_TASK_ENCODER) {
+			address = 0x321 << 3;
+		} else if (ic_task == IC_TASK_POST_PROCESSOR) {
+			address = 0x96C << 3;
+		} else {
+			BUG();
+		}
+	} else {
+		if (ic_task == IC_TASK_VIEWFINDER) {
+			address = 0x5a5 << 3;
+		} else if (ic_task == IC_TASK_ENCODER) {
+			address = 0x2d1 << 3;
+		} else if (ic_task == IC_TASK_POST_PROCESSOR) {
+			address = 0x87c << 3;
+		} else {
+			BUG();
+		}
+	}
+
+	if ((in_format == YCbCr) && (out_format == RGB)) {
+		/* Init CSC1 (YCbCr->RGB) */
+		param[0] =
+		    (ycbcr2rgb_coeff[3][0] << 27) | (ycbcr2rgb_coeff[0][0] <<
+						     18) |
+		    (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
+		/* scale = 2, sat = 0 */
+		param[1] = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (ycbcr2rgb_coeff[3][1] << 27) | (ycbcr2rgb_coeff[0][1] <<
+						     18) |
+		    (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
+		param[1] = (ycbcr2rgb_coeff[3][1] >> 5);
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (ycbcr2rgb_coeff[3][2] << 27) | (ycbcr2rgb_coeff[0][2] <<
+						     18) |
+		    (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
+		param[1] = (ycbcr2rgb_coeff[3][2] >> 5);
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+	} else if ((in_format == RGB) && (out_format == YCbCr)) {
+		/* Init CSC1 (RGB->YCbCr) */
+		param[0] =
+		    (rgb2ycbcr_coeff[3][0] << 27) | (rgb2ycbcr_coeff[0][0] <<
+						     18) |
+		    (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
+		/* scale = 1, sat = 0 */
+		param[1] = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (rgb2ycbcr_coeff[3][1] << 27) | (rgb2ycbcr_coeff[0][1] <<
+						     18) |
+		    (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
+		param[1] = (rgb2ycbcr_coeff[3][1] >> 5);
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (rgb2ycbcr_coeff[3][2] << 27) | (rgb2ycbcr_coeff[0][2] <<
+						     18) |
+		    (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
+		param[1] = (rgb2ycbcr_coeff[3][2] >> 5);
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+	} else if ((in_format == RGB) && (out_format == RGB)) {
+		/* Init CSC1 */
+		param[0] =
+		    (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
+		    (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
+		/* scale = 2, sat = 0 */
+		param[1] = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
+
+		_ipu_write_param_mem(address, param, 2);
+
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
+		    (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
+		param[1] = (rgb2rgb_coeff[3][1] >> 5);
+
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+
+		param[0] =
+		    (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
+		    (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
+		param[1] = (rgb2rgb_coeff[3][2] >> 5);
+
+		address += 1L << 3;
+		_ipu_write_param_mem(address, param, 2);
+
+		dev_dbg(g_ipu_dev,
+			"addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n",
+			address, param[0], param[1]);
+	} else {
+		dev_err(g_ipu_dev, "Unsupported color space conversion\n");
+	}
+}
+
+static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize,
+				uint32_t * resizeCoeff,
+				uint32_t * downsizeCoeff)
+{
+	uint32_t tempSize;
+	uint32_t tempDownsize;
+
+	/* Cannot downsize more than 8:1 */
+	if ((outSize << 3) < inSize) {
+		return false;
+	}
+	/* compute downsizing coefficient */
+	tempDownsize = 0;
+	tempSize = inSize;
+	while ((tempSize >= outSize * 2) && (tempDownsize < 2)) {
+		tempSize >>= 1;
+		tempDownsize++;
+	}
+	*downsizeCoeff = tempDownsize;
+
+	/* compute resizing coefficient using the following equation:
+	   resizeCoeff = M*(SI -1)/(SO - 1)
+	   where M = 2^13, SI - input size, SO - output size    */
+	*resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
+	if (*resizeCoeff >= 16384L) {
+		dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n");
+		*resizeCoeff = 0x3FFF;
+	}
+
+	dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, "
+		"downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
+		*downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
+		((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
+
+	return true;
+}
diff --git a/drivers/mxc/ipu/ipu_param_mem.h b/drivers/mxc/ipu/ipu_param_mem.h
new file mode 100644
index 000000000000..07bd03a81e3f
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_param_mem.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PARAM_MEM_H__
+#define __INCLUDE_IPU_PARAM_MEM_H__
+
+#include <linux/types.h>
+
+static __inline void _ipu_ch_param_set_size(uint32_t * params,
+					    uint32_t pixel_fmt, uint16_t width,
+					    uint16_t height, uint16_t stride,
+					    uint32_t u, uint32_t v)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	memset(params, 0, 40);
+
+	params[3] =
+	    (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - 1) << 24);
+	params[4] = (uint32_t) (height - 1) >> 8;
+	params[7] = (uint32_t) (stride - 1) << 3;
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+		/*Represents 8-bit Generic data */
+		params[7] |= 3 | (7UL << (81 - 64)) | (31L << (89 - 64));	/* BPP & PFS */
+		params[8] = 2;	/* SAT = use 32-bit access */
+		break;
+	case IPU_PIX_FMT_GENERIC_32:
+		/*Represents 32-bit Generic data */
+		params[7] |= (7UL << (81 - 64)) | (7L << (89 - 64));	/* BPP & PFS */
+		params[8] = 2;	/* SAT = use 32-bit access */
+		break;
+	case IPU_PIX_FMT_RGB565:
+		params[7] |= 2L | (4UL << (81 - 64)) | (7L << (89 - 64));	/* BPP & PFS */
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (0UL << (99 - 96)) |	/* Red bit offset */
+		    (5UL << (104 - 96)) |	/* Green bit offset     */
+		    (11UL << (109 - 96)) |	/* Blue bit offset */
+		    (16UL << (114 - 96)) |	/* Alpha bit offset     */
+		    (4UL << (119 - 96)) |	/* Red bit width - 1 */
+		    (5UL << (122 - 96)) |	/* Green bit width - 1 */
+		    (4UL << (125 - 96));	/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_BGR24:	/* 24 BPP & RGB PFS */
+		params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64));
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (8UL << (104 - 96)) |	/* Green bit offset     */
+		    (16UL << (109 - 96)) |	/* Blue bit offset */
+		    (24UL << (114 - 96)) |	/* Alpha bit offset     */
+		    (7UL << (119 - 96)) |	/* Red bit width - 1 */
+		    (7UL << (122 - 96)) |	/* Green bit width - 1 */
+		    (uint32_t) (7UL << (125 - 96));	/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_RGB24:	/* 24 BPP & RGB PFS     */
+		params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64));
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (16UL << (99 - 96)) |	/* Red bit offset */
+		    (8UL << (104 - 96)) |	/* Green bit offset */
+		    (0UL << (109 - 96)) |	/* Blue bit offset */
+		    (24UL << (114 - 96)) |	/* Alpha bit offset */
+		    (7UL << (119 - 96)) |	/* Red bit width - 1 */
+		    (7UL << (122 - 96)) |	/* Green bit width - 1 */
+		    (uint32_t) (7UL << (125 - 96));	/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+		/* BPP & pixel fmt */
+		params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64));
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (8UL << (99 - 96)) |	/* Red bit offset */
+		    (16UL << (104 - 96)) |	/* Green bit offset     */
+		    (24UL << (109 - 96)) |	/* Blue bit offset */
+		    (0UL << (114 - 96)) |	/* Alpha bit offset     */
+		    (7UL << (119 - 96)) |	/* Red bit width - 1 */
+		    (7UL << (122 - 96)) |	/* Green bit width - 1 */
+		    (uint32_t) (7UL << (125 - 96));	/* Blue bit width - 1 */
+		params[9] = 7;	/* Alpha bit width - 1 */
+		break;
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+		/* BPP & pixel fmt */
+		params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64));
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (24UL << (99 - 96)) |	/* Red bit offset */
+		    (16UL << (104 - 96)) |	/* Green bit offset     */
+		    (8UL << (109 - 96)) |	/* Blue bit offset */
+		    (0UL << (114 - 96)) |	/* Alpha bit offset     */
+		    (7UL << (119 - 96)) |	/* Red bit width - 1 */
+		    (7UL << (122 - 96)) |	/* Green bit width - 1 */
+		    (uint32_t) (7UL << (125 - 96));	/* Blue bit width - 1 */
+		params[9] = 7;	/* Alpha bit width - 1 */
+		break;
+	case IPU_PIX_FMT_ABGR32:
+		/* BPP & pixel fmt */
+		params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64));
+		params[8] = 2 |	/* SAT = 32-bit access */
+		    (0UL << (99 - 96)) |	/* Alpha bit offset     */
+		    (8UL << (104 - 96)) |	/* Blue bit offset */
+		    (16UL << (109 - 96)) |	/* Green bit offset     */
+		    (24UL << (114 - 96)) |	/* Red bit offset */
+		    (7UL << (119 - 96)) |	/* Alpha bit width - 1 */
+		    (7UL << (122 - 96)) |	/* Blue bit width - 1 */
+		    (uint32_t) (7UL << (125 - 96));	/* Green bit width - 1 */
+		params[9] = 7;	/* Red bit width - 1 */
+		break;
+	case IPU_PIX_FMT_UYVY:
+		/* BPP & pixel format */
+		params[7] |= 2 | (6UL << 17) | (7 << (89 - 64));
+		params[8] = 2;	/* SAT = 32-bit access */
+		break;
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		/* BPP & pixel format */
+		params[7] |= 3 | (3UL << 17) | (7 << (89 - 64));
+		params[8] = 2;	/* SAT = 32-bit access */
+		u_offset = (u == 0) ? stride * height : u;
+		v_offset = (v == 0) ? u_offset + u_offset / 4 : v;
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		/* BPP & pixel format */
+		params[7] |= 3 | (2UL << 17) | (7 << (89 - 64));
+		params[8] = 2;	/* SAT = 32-bit access */
+		v_offset = (v == 0) ? stride * height : v;
+		u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		/* BPP & pixel format */
+		params[7] |= 3 | (2UL << 17) | (7 << (89 - 64));
+		params[8] = 2;	/* SAT = 32-bit access */
+		u_offset = (u == 0) ? stride * height : u;
+		v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
+		break;
+	default:
+		dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+
+	params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32));
+	params[2] = u_offset >> (64 - 53);
+	params[2] |= v_offset << (79 - 64);
+	params[3] |= v_offset >> (96 - 79);
+}
+
+static __inline void _ipu_ch_param_set_burst_size(uint32_t * params,
+						  uint16_t burst_pixels)
+{
+	params[7] &= ~(0x3FL << (89 - 64));
+	params[7] |= (uint32_t) (burst_pixels - 1) << (89 - 64);
+};
+
+static __inline void _ipu_ch_param_set_buffer(uint32_t * params,
+					      dma_addr_t buf0, dma_addr_t buf1)
+{
+	params[5] = buf0;
+	params[6] = buf1;
+};
+
+static __inline void _ipu_ch_param_set_rotation(uint32_t * params,
+						ipu_rotate_mode_t rot)
+{
+	params[7] |= (uint32_t) rot << (84 - 64);
+};
+
+void _ipu_write_param_mem(uint32_t addr, uint32_t * data, uint32_t numWords);
+
+#endif
diff --git a/drivers/mxc/ipu/ipu_prv.h b/drivers/mxc/ipu/ipu_prv.h
new file mode 100644
index 000000000000..b76a2f2357fd
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_prv.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PRV_H__
+#define __INCLUDE_IPU_PRV_H__
+
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <mach/hardware.h>
+
+/* Globals */
+extern struct device *g_ipu_dev;
+extern spinlock_t ipu_lock;
+extern struct clk *g_ipu_clk;
+extern struct clk *g_ipu_csi_clk;
+
+int register_ipu_device(void);
+ipu_color_space_t format_to_colorspace(uint32_t fmt);
+
+uint32_t _ipu_channel_status(ipu_channel_t channel);
+
+void _ipu_sdc_fg_init(ipu_channel_params_t * params);
+uint32_t _ipu_sdc_fg_uninit(void);
+void _ipu_sdc_bg_init(ipu_channel_params_t * params);
+uint32_t _ipu_sdc_bg_uninit(void);
+
+void _ipu_ic_enable_task(ipu_channel_t channel);
+void _ipu_ic_disable_task(ipu_channel_t channel);
+void _ipu_ic_init_prpvf(ipu_channel_params_t * params, bool src_is_csi);
+void _ipu_ic_uninit_prpvf(void);
+void _ipu_ic_init_rotate_vf(ipu_channel_params_t * params);
+void _ipu_ic_uninit_rotate_vf(void);
+void _ipu_ic_init_csi(ipu_channel_params_t * params);
+void _ipu_ic_uninit_csi(void);
+void _ipu_ic_init_prpenc(ipu_channel_params_t * params, bool src_is_csi);
+void _ipu_ic_uninit_prpenc(void);
+void _ipu_ic_init_rotate_enc(ipu_channel_params_t * params);
+void _ipu_ic_uninit_rotate_enc(void);
+void _ipu_ic_init_pp(ipu_channel_params_t * params);
+void _ipu_ic_uninit_pp(void);
+void _ipu_ic_init_rotate_pp(ipu_channel_params_t * params);
+void _ipu_ic_uninit_rotate_pp(void);
+
+int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp,
+			      mcu_mode_t cmd, int16_t x_pos, int16_t y_pos);
+int32_t _ipu_adc_uninit_channel(ipu_channel_t chan);
+
+#endif				/* __INCLUDE_IPU_PRV_H__ */
diff --git a/drivers/mxc/ipu/ipu_regs.h b/drivers/mxc/ipu/ipu_regs.h
new file mode 100644
index 000000000000..d3ac76ea7834
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_regs.h
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_regs.h
+ *
+ * @brief IPU Register definitions
+ *
+ * @ingroup IPU
+ */
+#ifndef __IPU_REGS_INCLUDED__
+#define __IPU_REGS_INCLUDED__
+
+#define IPU_REG_BASE    IO_ADDRESS(IPU_CTRL_BASE_ADDR)
+
+/* Register addresses */
+/* IPU Common registers */
+#define IPU_CONF                (IPU_REG_BASE + 0x0000)
+#define IPU_CHA_BUF0_RDY        (IPU_REG_BASE + 0x0004)
+#define IPU_CHA_BUF1_RDY        (IPU_REG_BASE + 0x0008)
+#define IPU_CHA_DB_MODE_SEL     (IPU_REG_BASE + 0x000C)
+#define IPU_CHA_CUR_BUF         (IPU_REG_BASE + 0x0010)
+#define IPU_FS_PROC_FLOW        (IPU_REG_BASE + 0x0014)
+#define IPU_FS_DISP_FLOW        (IPU_REG_BASE + 0x0018)
+#define IPU_TASKS_STAT          (IPU_REG_BASE + 0x001C)
+#define IPU_IMA_ADDR            (IPU_REG_BASE + 0x0020)
+#define IPU_IMA_DATA            (IPU_REG_BASE + 0x0024)
+#define IPU_INT_CTRL_1          (IPU_REG_BASE + 0x0028)
+#define IPU_INT_CTRL_2          (IPU_REG_BASE + 0x002C)
+#define IPU_INT_CTRL_3          (IPU_REG_BASE + 0x0030)
+#define IPU_INT_CTRL_4          (IPU_REG_BASE + 0x0034)
+#define IPU_INT_CTRL_5          (IPU_REG_BASE + 0x0038)
+#define IPU_INT_STAT_1          (IPU_REG_BASE + 0x003C)
+#define IPU_INT_STAT_2          (IPU_REG_BASE + 0x0040)
+#define IPU_INT_STAT_3          (IPU_REG_BASE + 0x0044)
+#define IPU_INT_STAT_4          (IPU_REG_BASE + 0x0048)
+#define IPU_INT_STAT_5          (IPU_REG_BASE + 0x004C)
+#define IPU_BRK_CTRL_1          (IPU_REG_BASE + 0x0050)
+#define IPU_BRK_CTRL_2          (IPU_REG_BASE + 0x0054)
+#define IPU_BRK_STAT            (IPU_REG_BASE + 0x0058)
+#define IPU_DIAGB_CTRL          (IPU_REG_BASE + 0x005C)
+/* CMOS Sensor Interface Registers */
+#define CSI_SENS_CONF           (IPU_REG_BASE + 0x0060)
+#define CSI_SENS_FRM_SIZE       (IPU_REG_BASE + 0x0064)
+#define CSI_ACT_FRM_SIZE        (IPU_REG_BASE + 0x0068)
+#define CSI_OUT_FRM_CTRL        (IPU_REG_BASE + 0x006C)
+#define CSI_TST_CTRL            (IPU_REG_BASE + 0x0070)
+#define CSI_CCIR_CODE_1         (IPU_REG_BASE + 0x0074)
+#define CSI_CCIR_CODE_2         (IPU_REG_BASE + 0x0078)
+#define CSI_CCIR_CODE_3         (IPU_REG_BASE + 0x007C)
+#define CSI_FLASH_STROBE_1      (IPU_REG_BASE + 0x0080)
+#define CSI_FLASH_STROBE_2      (IPU_REG_BASE + 0x0084)
+/* Image Converter Registers */
+#define IC_CONF                 (IPU_REG_BASE + 0x0088)
+#define IC_PRP_ENC_RSC          (IPU_REG_BASE + 0x008C)
+#define IC_PRP_VF_RSC           (IPU_REG_BASE + 0x0090)
+#define IC_PP_RSC               (IPU_REG_BASE + 0x0094)
+#define IC_CMBP_1               (IPU_REG_BASE + 0x0098)
+#define IC_CMBP_2               (IPU_REG_BASE + 0x009C)
+#define PF_CONF                 (IPU_REG_BASE + 0x00A0)
+#define IDMAC_CONF              (IPU_REG_BASE + 0x00A4)
+#define IDMAC_CHA_EN            (IPU_REG_BASE + 0x00A8)
+#define IDMAC_CHA_PRI           (IPU_REG_BASE + 0x00AC)
+#define IDMAC_CHA_BUSY          (IPU_REG_BASE + 0x00B0)
+/* SDC Registers */
+#define SDC_COM_CONF            (IPU_REG_BASE + 0x00B4)
+#define SDC_GW_CTRL             (IPU_REG_BASE + 0x00B8)
+#define SDC_FG_POS              (IPU_REG_BASE + 0x00BC)
+#define SDC_BG_POS              (IPU_REG_BASE + 0x00C0)
+#define SDC_CUR_POS             (IPU_REG_BASE + 0x00C4)
+#define SDC_PWM_CTRL            (IPU_REG_BASE + 0x00C8)
+#define SDC_CUR_MAP             (IPU_REG_BASE + 0x00CC)
+#define SDC_HOR_CONF            (IPU_REG_BASE + 0x00D0)
+#define SDC_VER_CONF            (IPU_REG_BASE + 0x00D4)
+#define SDC_SHARP_CONF_1        (IPU_REG_BASE + 0x00D8)
+#define SDC_SHARP_CONF_2        (IPU_REG_BASE + 0x00DC)
+/* ADC Registers */
+#define ADC_CONF                (IPU_REG_BASE + 0x00E0)
+#define ADC_SYSCHA1_SA          (IPU_REG_BASE + 0x00E4)
+#define ADC_SYSCHA2_SA          (IPU_REG_BASE + 0x00E8)
+#define ADC_PRPCHAN_SA          (IPU_REG_BASE + 0x00EC)
+#define ADC_PPCHAN_SA           (IPU_REG_BASE + 0x00F0)
+#define ADC_DISP0_CONF          (IPU_REG_BASE + 0x00F4)
+#define ADC_DISP0_RD_AP         (IPU_REG_BASE + 0x00F8)
+#define ADC_DISP0_RDM           (IPU_REG_BASE + 0x00FC)
+#define ADC_DISP0_SS            (IPU_REG_BASE + 0x0100)
+#define ADC_DISP1_CONF          (IPU_REG_BASE + 0x0104)
+#define ADC_DISP1_RD_AP         (IPU_REG_BASE + 0x0108)
+#define ADC_DISP1_RDM           (IPU_REG_BASE + 0x010C)
+#define ADC_DISP12_SS           (IPU_REG_BASE + 0x0110)
+#define ADC_DISP2_CONF          (IPU_REG_BASE + 0x0114)
+#define ADC_DISP2_RD_AP         (IPU_REG_BASE + 0x0118)
+#define ADC_DISP2_RDM           (IPU_REG_BASE + 0x011C)
+#define ADC_DISP_VSYNC          (IPU_REG_BASE + 0x0120)
+/* Display Interface re(sters */
+#define DI_DISP_IF_CONF         (IPU_REG_BASE + 0x0124)
+#define DI_DISP_SIG_POL         (IPU_REG_BASE + 0x0128)
+#define DI_SER_DISP1_CONF       (IPU_REG_BASE + 0x012C)
+#define DI_SER_DISP2_CONF       (IPU_REG_BASE + 0x0130)
+#define DI_HSP_CLK_PER          (IPU_REG_BASE + 0x0134)
+#define DI_DISP0_TIME_CONF_1    (IPU_REG_BASE + 0x0138)
+#define DI_DISP0_TIME_CONF_2    (IPU_REG_BASE + 0x013C)
+#define DI_DISP0_TIME_CONF_3    (IPU_REG_BASE + 0x0140)
+#define DI_DISP1_TIME_CONF_1    (IPU_REG_BASE + 0x0144)
+#define DI_DISP1_TIME_CONF_2    (IPU_REG_BASE + 0x0148)
+#define DI_DISP1_TIME_CONF_3    (IPU_REG_BASE + 0x014C)
+#define DI_DISP2_TIME_CONF_1    (IPU_REG_BASE + 0x0150)
+#define DI_DISP2_TIME_CONF_2    (IPU_REG_BASE + 0x0154)
+#define DI_DISP2_TIME_CONF_3    (IPU_REG_BASE + 0x0158)
+#define DI_DISP3_TIME_CONF      (IPU_REG_BASE + 0x015C)
+#define DI_DISP0_DB0_MAP        (IPU_REG_BASE + 0x0160)
+#define DI_DISP0_DB1_MAP        (IPU_REG_BASE + 0x0164)
+#define DI_DISP0_DB2_MAP        (IPU_REG_BASE + 0x0168)
+#define DI_DISP0_CB0_MAP        (IPU_REG_BASE + 0x016C)
+#define DI_DISP0_CB1_MAP        (IPU_REG_BASE + 0x0170)
+#define DI_DISP0_CB2_MAP        (IPU_REG_BASE + 0x0174)
+#define DI_DISP1_DB0_MAP        (IPU_REG_BASE + 0x0178)
+#define DI_DISP1_DB1_MAP        (IPU_REG_BASE + 0x017C)
+#define DI_DISP1_DB2_MAP        (IPU_REG_BASE + 0x0180)
+#define DI_DISP1_CB0_MAP        (IPU_REG_BASE + 0x0184)
+#define DI_DISP1_CB1_MAP        (IPU_REG_BASE + 0x0188)
+#define DI_DISP1_CB2_MAP        (IPU_REG_BASE + 0x018C)
+#define DI_DISP2_DB0_MAP        (IPU_REG_BASE + 0x0190)
+#define DI_DISP2_DB1_MAP        (IPU_REG_BASE + 0x0194)
+#define DI_DISP2_DB2_MAP        (IPU_REG_BASE + 0x0198)
+#define DI_DISP2_CB0_MAP        (IPU_REG_BASE + 0x019C)
+#define DI_DISP2_CB1_MAP        (IPU_REG_BASE + 0x01A0)
+#define DI_DISP2_CB2_MAP        (IPU_REG_BASE + 0x01A4)
+#define DI_DISP3_B0_MAP         (IPU_REG_BASE + 0x01A8)
+#define DI_DISP3_B1_MAP         (IPU_REG_BASE + 0x01AC)
+#define DI_DISP3_B2_MAP         (IPU_REG_BASE + 0x01B0)
+#define DI_DISP_ACC_CC          (IPU_REG_BASE + 0x01B4)
+#define DI_DISP_LLA_CONF        (IPU_REG_BASE + 0x01B8)
+#define DI_DISP_LLA_DATA        (IPU_REG_BASE + 0x01BC)
+
+#define IPUIRQ_2_STATREG(int)   (IPU_INT_STAT_1 + 4*(int>>5))
+#define IPUIRQ_2_CTRLREG(int)   (IPU_INT_CTRL_1 + 4*(int>>5))
+#define IPUIRQ_2_MASK(int)      (1UL << (int & 0x1F))
+
+enum {
+	IPU_CONF_CSI_EN = 0x00000001,
+	IPU_CONF_IC_EN = 0x00000002,
+	IPU_CONF_ROT_EN = 0x00000004,
+	IPU_CONF_PF_EN = 0x00000008,
+	IPU_CONF_SDC_EN = 0x00000010,
+	IPU_CONF_ADC_EN = 0x00000020,
+	IPU_CONF_DI_EN = 0x00000040,
+	IPU_CONF_DU_EN = 0x00000080,
+	IPU_CONF_PXL_ENDIAN = 0x00000100,
+
+	FS_PRPVF_ROT_SRC_SEL = 0x00000040,
+	FS_PRPENC_ROT_SRC_SEL = 0x00000020,
+	FS_PRPENC_DEST_SEL = 0x00000010,
+	FS_PP_SRC_SEL_MASK = 0x00000300,
+	FS_PP_SRC_SEL_OFFSET = 8,
+	FS_PP_ROT_SRC_SEL_MASK = 0x00000C00,
+	FS_PP_ROT_SRC_SEL_OFFSET = 10,
+	FS_PF_DEST_SEL_MASK = 0x00003000,
+	FS_PF_DEST_SEL_OFFSET = 12,
+	FS_PRPVF_DEST_SEL_MASK = 0x00070000,
+	FS_PRPVF_DEST_SEL_OFFSET = 16,
+	FS_PRPVF_ROT_DEST_SEL_MASK = 0x00700000,
+	FS_PRPVF_ROT_DEST_SEL_OFFSET = 20,
+	FS_PP_DEST_SEL_MASK = 0x07000000,
+	FS_PP_DEST_SEL_OFFSET = 24,
+	FS_PP_ROT_DEST_SEL_MASK = 0x70000000,
+	FS_PP_ROT_DEST_SEL_OFFSET = 28,
+	FS_VF_IN_VALID = 0x00000002,
+	FS_ENC_IN_VALID = 0x00000001,
+
+	FS_SDC_BG_SRC_SEL_MASK = 0x00000007,
+	FS_SDC_BG_SRC_SEL_OFFSET = 0,
+	FS_SDC_FG_SRC_SEL_MASK = 0x00000070,
+	FS_SDC_FG_SRC_SEL_OFFSET = 4,
+	FS_ADC1_SRC_SEL_MASK = 0x00000700,
+	FS_ADC1_SRC_SEL_OFFSET = 8,
+	FS_ADC2_SRC_SEL_MASK = 0x00007000,
+	FS_ADC2_SRC_SEL_OFFSET = 12,
+	FS_AUTO_REF_PER_MASK = 0x03FF0000,
+	FS_AUTO_REF_PER_OFFSET = 16,
+
+	FS_DEST_ARM = 0,
+	FS_DEST_ROT = 1,
+	FS_DEST_PP = 1,
+	FS_DEST_ADC1 = 2,
+	FS_DEST_ADC2 = 3,
+	FS_DEST_SDC_BG = 4,
+	FS_DEST_SDC_FG = 5,
+	FS_DEST_ADC = 6,
+
+	FS_SRC_ARM = 0,
+	FS_PP_SRC_PF = 1,
+	FS_PP_SRC_ROT = 2,
+
+	FS_ROT_SRC_PP = 1,
+	FS_ROT_SRC_PF = 2,
+
+	FS_PF_DEST_PP = 1,
+	FS_PF_DEST_ROT = 2,
+
+	FS_SRC_ROT_VF = 1,
+	FS_SRC_ROT_PP = 2,
+	FS_SRC_VF = 3,
+	FS_SRC_PP = 4,
+	FS_SRC_SNOOP = 5,
+	FS_SRC_AUTOREF = 6,
+	FS_SRC_AUTOREF_SNOOP = 7,
+
+	TSTAT_PF_H264_PAUSE = 0x00000001,
+	TSTAT_CSI2MEM_MASK = 0x0000000C,
+	TSTAT_CSI2MEM_OFFSET = 2,
+	TSTAT_VF_MASK = 0x00000600,
+	TSTAT_VF_OFFSET = 9,
+	TSTAT_VF_ROT_MASK = 0x000C0000,
+	TSTAT_VF_ROT_OFFSET = 18,
+	TSTAT_ENC_MASK = 0x00000180,
+	TSTAT_ENC_OFFSET = 7,
+	TSTAT_ENC_ROT_MASK = 0x00030000,
+	TSTAT_ENC_ROT_OFFSET = 16,
+	TSTAT_PP_MASK = 0x00001800,
+	TSTAT_PP_OFFSET = 11,
+	TSTAT_PP_ROT_MASK = 0x00300000,
+	TSTAT_PP_ROT_OFFSET = 20,
+	TSTAT_PF_MASK = 0x00C00000,
+	TSTAT_PF_OFFSET = 22,
+	TSTAT_ADCSYS1_MASK = 0x03000000,
+	TSTAT_ADCSYS1_OFFSET = 24,
+	TSTAT_ADCSYS2_MASK = 0x0C000000,
+	TSTAT_ADCSYS2_OFFSET = 26,
+
+	TASK_STAT_IDLE = 0,
+	TASK_STAT_ACTIVE = 1,
+	TASK_STAT_WAIT4READY = 2,
+
+	/* Register bits */
+	SDC_COM_TFT_COLOR = 0x00000001UL,
+	SDC_COM_FG_EN = 0x00000010UL,
+	SDC_COM_GWSEL = 0x00000020UL,
+	SDC_COM_GLB_A = 0x00000040UL,
+	SDC_COM_KEY_COLOR_G = 0x00000080UL,
+	SDC_COM_BG_EN = 0x00000200UL,
+	SDC_COM_SHARP = 0x00001000UL,
+
+	SDC_V_SYNC_WIDTH_L = 0x00000001UL,
+
+	ADC_CONF_PRP_EN = 0x00000001L,
+	ADC_CONF_PP_EN = 0x00000002L,
+	ADC_CONF_MCU_EN = 0x00000004L,
+
+	ADC_DISP_CONF_SL_MASK = 0x00000FFFL,
+	ADC_DISP_CONF_TYPE_MASK = 0x00003000L,
+	ADC_DISP_CONF_TYPE_XY = 0x00002000L,
+
+	ADC_DISP_VSYNC_D0_MODE_MASK = 0x00000003L,
+	ADC_DISP_VSYNC_D0_WIDTH_MASK = 0x003F0000L,
+	ADC_DISP_VSYNC_D12_MODE_MASK = 0x0000000CL,
+	ADC_DISP_VSYNC_D12_WIDTH_MASK = 0x3F000000L,
+
+	/* Image Converter Register bits */
+	IC_CONF_PRPENC_EN = 0x00000001,
+	IC_CONF_PRPENC_CSC1 = 0x00000002,
+	IC_CONF_PRPENC_ROT_EN = 0x00000004,
+	IC_CONF_PRPVF_EN = 0x00000100,
+	IC_CONF_PRPVF_CSC1 = 0x00000200,
+	IC_CONF_PRPVF_CSC2 = 0x00000400,
+	IC_CONF_PRPVF_CMB = 0x00000800,
+	IC_CONF_PRPVF_ROT_EN = 0x00001000,
+	IC_CONF_PP_EN = 0x00010000,
+	IC_CONF_PP_CSC1 = 0x00020000,
+	IC_CONF_PP_CSC2 = 0x00040000,
+	IC_CONF_PP_CMB = 0x00080000,
+	IC_CONF_PP_ROT_EN = 0x00100000,
+	IC_CONF_IC_GLB_LOC_A = 0x10000000,
+	IC_CONF_KEY_COLOR_EN = 0x20000000,
+	IC_CONF_RWS_EN = 0x40000000,
+	IC_CONF_CSI_MEM_WR_EN = 0x80000000,
+
+	IDMA_CHAN_INVALID = 0x000000FF,
+	IDMA_IC_0 = 0x00000001,
+	IDMA_IC_1 = 0x00000002,
+	IDMA_IC_2 = 0x00000004,
+	IDMA_IC_3 = 0x00000008,
+	IDMA_IC_4 = 0x00000010,
+	IDMA_IC_5 = 0x00000020,
+	IDMA_IC_6 = 0x00000040,
+	IDMA_IC_7 = 0x00000080,
+	IDMA_IC_8 = 0x00000100,
+	IDMA_IC_9 = 0x00000200,
+	IDMA_IC_10 = 0x00000400,
+	IDMA_IC_11 = 0x00000800,
+	IDMA_IC_12 = 0x00001000,
+	IDMA_IC_13 = 0x00002000,
+	IDMA_SDC_BG = 0x00004000,
+	IDMA_SDC_FG = 0x00008000,
+	IDMA_SDC_MASK = 0x00010000,
+	IDMA_SDC_PARTIAL = 0x00020000,
+	IDMA_ADC_SYS1_WR = 0x00040000,
+	IDMA_ADC_SYS2_WR = 0x00080000,
+	IDMA_ADC_SYS1_CMD = 0x00100000,
+	IDMA_ADC_SYS2_CMD = 0x00200000,
+	IDMA_ADC_SYS1_RD = 0x00400000,
+	IDMA_ADC_SYS2_RD = 0x00800000,
+	IDMA_PF_QP = 0x01000000,
+	IDMA_PF_BSP = 0x02000000,
+	IDMA_PF_Y_IN = 0x04000000,
+	IDMA_PF_U_IN = 0x08000000,
+	IDMA_PF_V_IN = 0x10000000,
+	IDMA_PF_Y_OUT = 0x20000000,
+	IDMA_PF_U_OUT = 0x40000000,
+	IDMA_PF_V_OUT = 0x80000000,
+
+	CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
+	CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0x00000000L,
+	CSI_SENS_CONF_DATA_FMT_YUV422 = 0x00000200L,
+	CSI_SENS_CONF_DATA_FMT_BAYER = 0x00000300L,
+
+	CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
+	CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
+	CSI_SENS_CONF_DATA_POL_SHIFT = 2,
+	CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
+	CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
+	CSI_SENS_CONF_SENS_CLKSRC_SHIFT = 7,
+	CSI_SENS_CONF_DATA_WIDTH_SHIFT = 10,
+	CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
+	CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
+
+	PF_CONF_TYPE_MASK = 0x00000007,
+	PF_CONF_TYPE_SHIFT = 0,
+	PF_CONF_PAUSE_EN = 0x00000010,
+	PF_CONF_RESET = 0x00008000,
+	PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
+	PF_CONF_PAUSE_ROW_SHIFT = 16,
+
+	/* DI_DISP_SIG_POL bits */
+	DI_D3_VSYNC_POL_SHIFT = 28,
+	DI_D3_HSYNC_POL_SHIFT = 27,
+	DI_D3_DRDY_SHARP_POL_SHIFT = 26,
+	DI_D3_CLK_POL_SHIFT = 25,
+	DI_D3_DATA_POL_SHIFT = 24,
+
+	/* DI_DISP_IF_CONF bits */
+	DI_D3_CLK_IDLE_SHIFT = 26,
+	DI_D3_CLK_SEL_SHIFT = 25,
+	DI_D3_DATAMSK_SHIFT = 24,
+
+	DISPx_IF_CLK_DOWN_OFFSET = 22,
+	DISPx_IF_CLK_UP_OFFSET = 12,
+	DISPx_IF_CLK_PER_OFFSET = 0,
+	DISPx_IF_CLK_READ_EN_OFFSET = 16,
+	DISPx_PIX_CLK_PER_OFFSET = 0,
+
+	DI_CONF_DISP0_EN = 0x00000001L,
+	DI_CONF_DISP0_IF_MODE_OFFSET = 1,
+	DI_CONF_DISP0_BURST_MODE_OFFSET = 3,
+	DI_CONF_DISP1_EN = 0x00000100L,
+	DI_CONF_DISP1_IF_MODE_OFFSET = 9,
+	DI_CONF_DISP1_BURST_MODE_OFFSET = 12,
+	DI_CONF_DISP2_EN = 0x00010000L,
+	DI_CONF_DISP2_IF_MODE_OFFSET = 17,
+	DI_CONF_DISP2_BURST_MODE_OFFSET = 20,
+
+	DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET = 16,
+	DI_SER_DISPx_CONF_PREAMBLE_OFFSET = 8,
+	DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET = 4,
+	DI_SER_DISPx_CONF_RW_CFG_OFFSET = 1,
+	DI_SER_DISPx_CONF_BURST_MODE_EN = 0x01000000L,
+	DI_SER_DISPx_CONF_PREAMBLE_EN = 0x00000001L,
+
+	/* DI_DISP_ACC_CC */
+	DISP0_IF_CLK_CNT_D_MASK = 0x00000003L,
+	DISP0_IF_CLK_CNT_D_OFFSET = 0,
+	DISP0_IF_CLK_CNT_C_MASK = 0x0000000CL,
+	DISP0_IF_CLK_CNT_C_OFFSET = 2,
+	DISP1_IF_CLK_CNT_D_MASK = 0x00000030L,
+	DISP1_IF_CLK_CNT_D_OFFSET = 4,
+	DISP1_IF_CLK_CNT_C_MASK = 0x000000C0L,
+	DISP1_IF_CLK_CNT_C_OFFSET = 6,
+	DISP2_IF_CLK_CNT_D_MASK = 0x00000300L,
+	DISP2_IF_CLK_CNT_D_OFFSET = 8,
+	DISP2_IF_CLK_CNT_C_MASK = 0x00000C00L,
+	DISP2_IF_CLK_CNT_C_OFFSET = 10,
+	DISP3_IF_CLK_CNT_MASK = 0x00003000L,
+	DISP3_IF_CLK_CNT_OFFSET = 12,
+};
+
+#endif
diff --git a/drivers/mxc/ipu/ipu_sdc.c b/drivers/mxc/ipu/ipu_sdc.c
new file mode 100644
index 000000000000..a36eb6dc6a4e
--- /dev/null
+++ b/drivers/mxc/ipu/ipu_sdc.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_sdc.c
+ *
+ * @brief IPU SDC submodule API functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+static uint32_t g_h_start_width;
+static uint32_t g_v_start_width;
+
+static const uint32_t di_mappings[] = {
+	0x1600AAAA, 0x00E05555, 0x00070000, 3,	/* RGB888 */
+	0x0005000F, 0x000B000F, 0x0011000F, 1,	/* RGB666 */
+	0x0011000F, 0x000B000F, 0x0005000F, 1,	/* BGR666 */
+	0x0004003F, 0x000A000F, 0x000F003F, 1	/* RGB565 */
+};
+
+/*!
+ * This function is called to initialize a synchronous LCD panel.
+ *
+ * @param       panel           The type of panel.
+ *
+ * @param       pixel_clk       Desired pixel clock frequency in Hz.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer. Pixel
+ *                              format is a FOURCC ASCII code.
+ *
+ * @param       width           The width of panel in pixels.
+ *
+ * @param       height          The height of panel in pixels.
+ *
+ * @param       hStartWidth     The number of pixel clocks between the HSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
+ *                              clocks.
+ *
+ * @param       hEndWidth       The number of pixel clocks between the end of
+ *                              valid data and the HSYNC signal for next line.
+ *
+ * @param       vStartWidth     The number of lines between the VSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       vSyncWidth      The width of the VSYNC signal in units of lines
+ *
+ * @param       vEndWidth       The number of lines between the end of valid
+ *                              data and the VSYNC signal for next frame.
+ *
+ * @param       sig             Bitfield of signal polarities for LCD interface.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_sdc_init_panel(ipu_panel_t panel,
+			   uint32_t pixel_clk,
+			   uint16_t width, uint16_t height,
+			   uint32_t pixel_fmt,
+			   uint16_t h_start_width, uint16_t h_sync_width,
+			   uint16_t h_end_width, uint16_t v_start_width,
+			   uint16_t v_sync_width, uint16_t v_end_width,
+			   ipu_di_signal_cfg_t sig)
+{
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t old_conf;
+	uint32_t div;
+
+	dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height);
+
+	if ((v_sync_width == 0) || (h_sync_width == 0))
+		return EINVAL;
+
+	/* Init panel size and blanking periods */
+	reg =
+	    ((uint32_t) (h_sync_width - 1) << 26) |
+	    ((uint32_t) (width + h_sync_width + h_start_width + h_end_width - 1)
+	     << 16);
+	__raw_writel(reg, SDC_HOR_CONF);
+
+	reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
+	    ((uint32_t)
+	     (height + v_sync_width + v_start_width + v_end_width - 1) << 16);
+	__raw_writel(reg, SDC_VER_CONF);
+
+	g_h_start_width = h_start_width + h_sync_width;
+	g_v_start_width = v_start_width + v_sync_width;
+
+	switch (panel) {
+	case IPU_PANEL_SHARP_TFT:
+		__raw_writel(0x00FD0102L, SDC_SHARP_CONF_1);
+		__raw_writel(0x00F500F4L, SDC_SHARP_CONF_2);
+		__raw_writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	case IPU_PANEL_TFT:
+		__raw_writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	default:
+		return EINVAL;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	/* Init clocking */
+
+	/* Calculate divider */
+	/* fractional part is 4 bits so simply multiple by 2^4 to get fractional part */
+	dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk);
+	div = (clk_get_rate(g_ipu_clk) * 16) / pixel_clk;
+	if (div < 0x40) {	/* Divider less than 4 */
+		dev_dbg(g_ipu_dev,
+			"InitPanel() - Pixel clock divider less than 1\n");
+		div = 0x40;
+	}
+	/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less fraction bits */
+	/* Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing debug     */
+	/* DISP3_IF_CLK_UP_WR is 0 */
+	__raw_writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
+
+	/* DI settings */
+	old_conf = __raw_readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
+	    sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
+	    sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
+	__raw_writel(old_conf, DI_DISP_IF_CONF);
+
+	old_conf = __raw_readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
+	    sig.clk_pol << DI_D3_CLK_POL_SHIFT |
+	    sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
+	    sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
+	    sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
+	__raw_writel(old_conf, DI_DISP_SIG_POL);
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_RGB24:
+		__raw_writel(di_mappings[0], DI_DISP3_B0_MAP);
+		__raw_writel(di_mappings[1], DI_DISP3_B1_MAP);
+		__raw_writel(di_mappings[2], DI_DISP3_B2_MAP);
+		__raw_writel(__raw_readl(DI_DISP_ACC_CC) |
+			     ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
+		break;
+	case IPU_PIX_FMT_RGB666:
+		__raw_writel(di_mappings[4], DI_DISP3_B0_MAP);
+		__raw_writel(di_mappings[5], DI_DISP3_B1_MAP);
+		__raw_writel(di_mappings[6], DI_DISP3_B2_MAP);
+		__raw_writel(__raw_readl(DI_DISP_ACC_CC) |
+			     ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
+		break;
+	case IPU_PIX_FMT_BGR666:
+		__raw_writel(di_mappings[8], DI_DISP3_B0_MAP);
+		__raw_writel(di_mappings[9], DI_DISP3_B1_MAP);
+		__raw_writel(di_mappings[10], DI_DISP3_B2_MAP);
+		__raw_writel(__raw_readl(DI_DISP_ACC_CC) |
+			     ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
+		break;
+	default:
+		__raw_writel(di_mappings[12], DI_DISP3_B0_MAP);
+		__raw_writel(di_mappings[13], DI_DISP3_B1_MAP);
+		__raw_writel(di_mappings[14], DI_DISP3_B2_MAP);
+		__raw_writel(__raw_readl(DI_DISP_ACC_CC) |
+			     ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
+		break;
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	dev_dbg(g_ipu_dev, "DI_DISP_IF_CONF = 0x%08X\n",
+		__raw_readl(DI_DISP_IF_CONF));
+	dev_dbg(g_ipu_dev, "DI_DISP_SIG_POL = 0x%08X\n",
+		__raw_readl(DI_DISP_SIG_POL));
+	dev_dbg(g_ipu_dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
+		__raw_readl(DI_DISP3_TIME_CONF));
+
+	return 0;
+}
+
+/*!
+ * This function sets the foreground and background plane global alpha blending
+ * modes.
+ *
+ * @param       enable          Boolean to enable or disable global alpha
+ *                              blending. If disabled, per pixel blending is used.
+ *
+ * @param       alpha           Global alpha value.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (enable) {
+		reg = __raw_readl(SDC_GW_CTRL) & 0x00FFFFFFL;
+		__raw_writel(reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
+
+		reg = __raw_readl(SDC_COM_CONF);
+		__raw_writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+	} else {
+		reg = __raw_readl(SDC_COM_CONF);
+		__raw_writel(reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+/*!
+ * This function sets the transparent color key for SDC graphic plane.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable color key
+ *
+ * @param       colorKey        24-bit RGB color to use as transparent color key.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable,
+			      uint32_t color_key)
+{
+	uint32_t reg, sdc_conf;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	sdc_conf = __raw_readl(SDC_COM_CONF);
+	if (channel == MEM_SDC_BG) {
+		sdc_conf &= ~SDC_COM_GWSEL;
+	} else {
+		sdc_conf |= SDC_COM_GWSEL;
+	}
+
+	if (enable) {
+		reg = __raw_readl(SDC_GW_CTRL) & 0xFF000000L;
+		__raw_writel(reg | (color_key & 0x00FFFFFFL), SDC_GW_CTRL);
+
+		sdc_conf |= SDC_COM_KEY_COLOR_G;
+	} else {
+		sdc_conf &= ~SDC_COM_KEY_COLOR_G;
+	}
+	__raw_writel(sdc_conf, SDC_COM_CONF);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+
+int32_t ipu_sdc_set_brightness(uint8_t value)
+{
+	__raw_writel(0x03000000UL | value << 16, SDC_PWM_CTRL);
+	return 0;
+}
+
+/*!
+ * This function sets the window position of the foreground or background plane.
+ * modes.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       x_pos           The X coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @param       y_pos           The Y coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @return      This function returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos,
+			       int16_t y_pos)
+{
+	x_pos += g_h_start_width;
+	y_pos += g_v_start_width;
+
+	if (channel == MEM_SDC_BG) {
+		__raw_writel((x_pos << 16) | y_pos, SDC_BG_POS);
+	} else if (channel == MEM_SDC_FG) {
+		__raw_writel((x_pos << 16) | y_pos, SDC_FG_POS);
+	} else {
+		return EINVAL;
+	}
+	return 0;
+}
+
+void _ipu_sdc_fg_init(ipu_channel_params_t * params)
+{
+	uint32_t reg;
+	(void)params;
+
+	/* Enable FG channel */
+	reg = __raw_readl(SDC_COM_CONF);
+	__raw_writel(reg | SDC_COM_FG_EN | SDC_COM_BG_EN, SDC_COM_CONF);
+}
+
+uint32_t _ipu_sdc_fg_uninit(void)
+{
+	uint32_t reg;
+
+	/* Disable FG channel */
+	reg = __raw_readl(SDC_COM_CONF);
+	__raw_writel(reg & ~SDC_COM_FG_EN, SDC_COM_CONF);
+
+	return (reg & SDC_COM_FG_EN);
+}
+
+void _ipu_sdc_bg_init(ipu_channel_params_t * params)
+{
+	uint32_t reg;
+	(void)params;
+
+	/* Enable FG channel */
+	reg = __raw_readl(SDC_COM_CONF);
+	__raw_writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+}
+
+uint32_t _ipu_sdc_bg_uninit(void)
+{
+	uint32_t reg;
+
+	/* Disable BG channel */
+	reg = __raw_readl(SDC_COM_CONF);
+	__raw_writel(reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
+
+	return (reg & SDC_COM_BG_EN);
+}
+
+/* Exported symbols for modules. */
+EXPORT_SYMBOL(ipu_sdc_init_panel);
+EXPORT_SYMBOL(ipu_sdc_set_global_alpha);
+EXPORT_SYMBOL(ipu_sdc_set_color_key);
+EXPORT_SYMBOL(ipu_sdc_set_brightness);
+EXPORT_SYMBOL(ipu_disp_set_window_pos);
diff --git a/drivers/mxc/ipu/pf/Kconfig b/drivers/mxc/ipu/pf/Kconfig
new file mode 100644
index 000000000000..fa5a777cf727
--- /dev/null
+++ b/drivers/mxc/ipu/pf/Kconfig
@@ -0,0 +1,7 @@
+config MXC_IPU_PF
+	tristate "MXC MPEG4/H.264 Post Filter Driver"
+	depends on MXC_IPU_V1
+    default y
+	help
+        Driver for MPEG4 dering and deblock and H.264 deblock
+        using MXC IPU h/w
diff --git a/drivers/mxc/ipu/pf/Makefile b/drivers/mxc/ipu/pf/Makefile
new file mode 100644
index 000000000000..641adf4be4bd
--- /dev/null
+++ b/drivers/mxc/ipu/pf/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MXC_IPU_PF) += mxc_pf.o
diff --git a/drivers/mxc/ipu/pf/mxc_pf.c b/drivers/mxc/ipu/pf/mxc_pf.c
new file mode 100644
index 000000000000..744152415e3a
--- /dev/null
+++ b/drivers/mxc/ipu/pf/mxc_pf.c
@@ -0,0 +1,993 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_pf.c
+ *
+ * @brief MXC IPU MPEG4/H.264 Post-filtering driver
+ *
+ * User-level API for IPU Hardware MPEG4/H.264 Post-filtering.
+ *
+ * @ingroup MXC_PF
+ */
+
+#include <linux/pagemap.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/ipu.h>
+#include <linux/mxc_pf.h>
+
+struct mxc_pf_data {
+	pf_operation_t mode;
+	u32 pf_enabled;
+	u32 width;
+	u32 height;
+	u32 stride;
+	uint32_t qp_size;
+	dma_addr_t qp_paddr;
+	void *qp_vaddr;
+	pf_buf buf[PF_MAX_BUFFER_CNT];
+	void *buf_vaddr[PF_MAX_BUFFER_CNT];
+	wait_queue_head_t pf_wait;
+	volatile int done_mask;
+	volatile int wait_mask;
+	volatile int busy_flag;
+	struct semaphore busy_lock;
+};
+
+static struct mxc_pf_data pf_data;
+static u8 open_count = 0;
+static struct class *mxc_pf_class;
+
+/*
+ * Function definitions
+ */
+
+static irqreturn_t mxc_pf_irq_handler(int irq, void *dev_id)
+{
+	struct mxc_pf_data *pf = dev_id;
+
+	if (irq == IPU_IRQ_PF_Y_OUT_EOF) {
+		pf->done_mask |= PF_WAIT_Y;
+	} else if (irq == IPU_IRQ_PF_U_OUT_EOF) {
+		pf->done_mask |= PF_WAIT_U;
+	} else if (irq == IPU_IRQ_PF_V_OUT_EOF) {
+		pf->done_mask |= PF_WAIT_V;
+	} else {
+		return IRQ_NONE;
+	}
+
+	if (pf->wait_mask && ((pf->done_mask & pf->wait_mask) == pf->wait_mask)) {
+		wake_up_interruptible(&pf->pf_wait);
+	}
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function handles PF_IOCTL_INIT calls. It initializes the PF channels,
+ * interrupt handlers, and channel buffers.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              error.
+ */
+static int mxc_pf_init(pf_init_params * pf_init)
+{
+	int err;
+	ipu_channel_params_t params;
+	u32 w;
+	u32 stride;
+	u32 h;
+	u32 qp_size = 0;
+	u32 qp_stride;
+
+	if ((pf_init->pf_mode > 4) || (pf_init->width > 1024) ||
+	    (pf_init->height > 1024) || (pf_init->stride < pf_init->width)) {
+		return -EINVAL;
+	}
+
+	pf_data.mode = pf_init->pf_mode;
+	w = pf_data.width = pf_init->width;
+	h = pf_data.height = pf_init->height;
+	stride = pf_data.stride = pf_init->stride;
+	pf_data.qp_size = pf_init->qp_size;
+
+	memset(&params, 0, sizeof(params));
+	params.mem_pf_mem.operation = pf_data.mode;
+	err = ipu_init_channel(MEM_PF_Y_MEM, &params);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error initializing channel\n");
+		goto err0;
+	}
+
+	err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER,
+				      IPU_PIX_FMT_GENERIC, w, h, stride,
+				      IPU_ROTATE_NONE, 0, 0, 0, 0);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error initializing Y input buffer\n");
+		goto err0;
+	}
+
+	err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER,
+				      IPU_PIX_FMT_GENERIC, w, h, stride,
+				      IPU_ROTATE_NONE, 0, 0, 0, 0);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error initializing Y output buffer\n");
+		goto err0;
+	}
+
+	w = w / 2;
+	h = h / 2;
+	stride = stride / 2;
+
+	if (pf_data.mode != PF_MPEG4_DERING) {
+		err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h, stride,
+					      IPU_ROTATE_NONE, 0, 0, 0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing U input buffer\n");
+			goto err0;
+		}
+
+		err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h, stride,
+					      IPU_ROTATE_NONE, 0, 0, 0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing U output buffer\n");
+			goto err0;
+		}
+
+		err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h, stride,
+					      IPU_ROTATE_NONE, 0, 0, 0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing V input buffer\n");
+			goto err0;
+		}
+
+		err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h, stride,
+					      IPU_ROTATE_NONE, 0, 0, 0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing V output buffer\n");
+			goto err0;
+		}
+	}
+
+	/*Setup Channel QF and BSC Params */
+	if (pf_data.mode == PF_H264_DEBLOCK) {
+		w = ((pf_data.width + 15) / 16);
+		h = (pf_data.height + 15) / 16;
+		qp_stride = w;
+		qp_size = 4 * qp_stride * h;
+		pr_debug("H264 QP width = %d, height = %d\n", w, h);
+		err = ipu_init_channel_buffer(MEM_PF_Y_MEM,
+					      IPU_SEC_INPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC_32, w, h,
+					      qp_stride, IPU_ROTATE_NONE, 0, 0,
+					      0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing H264 QP buffer\n");
+			goto err0;
+		}
+/*                w = (pf_data.width + 3) / 4; */
+		w *= 4;
+		h *= 4;
+		qp_stride = w;
+		err = ipu_init_channel_buffer(MEM_PF_U_MEM,
+					      IPU_SEC_INPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h,
+					      qp_stride, IPU_ROTATE_NONE, 0, 0,
+					      0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing H264 BSB buffer\n");
+			goto err0;
+		}
+		qp_size += qp_stride * h;
+	} else {		/* MPEG4 mode */
+
+		w = (pf_data.width + 15) / 16;
+		h = (pf_data.height + 15) / 16;
+		qp_stride = (w + 3) & ~0x3UL;
+		pr_debug("MPEG4 QP width = %d, height = %d, stride = %d\n",
+			 w, h, qp_stride);
+		err = ipu_init_channel_buffer(MEM_PF_Y_MEM,
+					      IPU_SEC_INPUT_BUFFER,
+					      IPU_PIX_FMT_GENERIC, w, h,
+					      qp_stride, IPU_ROTATE_NONE, 0, 0,
+					      0, 0);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error initializing MPEG4 QP buffer\n");
+			goto err0;
+		}
+		qp_size = qp_stride * h;
+	}
+
+	/* Support 2 QP buffers */
+	qp_size *= 2;
+
+	if (pf_data.qp_size > qp_size)
+		qp_size = pf_data.qp_size;
+	else
+		pf_data.qp_size = qp_size;
+
+	pf_data.qp_vaddr = dma_alloc_coherent(NULL, pf_data.qp_size,
+					      &pf_data.qp_paddr,
+					      GFP_KERNEL | GFP_DMA);
+	if (!pf_data.qp_vaddr)
+		return -ENOMEM;
+
+	pf_init->qp_paddr = pf_data.qp_paddr;
+	pf_init->qp_size = pf_data.qp_size;
+
+	return 0;
+
+      err0:
+	return err;
+}
+
+/*!
+ * This function handles PF_IOCTL_UNINIT calls. It uninitializes the PF
+ * channels and interrupt handlers.
+ *
+ * @return      This function returns 0 on success or negative error code
+ *              on error.
+ */
+static int mxc_pf_uninit(void)
+{
+	pf_data.pf_enabled = 0;
+	ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF);
+	ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF);
+	ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF);
+
+	ipu_disable_channel(MEM_PF_Y_MEM, true);
+	ipu_disable_channel(MEM_PF_U_MEM, true);
+	ipu_disable_channel(MEM_PF_V_MEM, true);
+	ipu_uninit_channel(MEM_PF_Y_MEM);
+	ipu_uninit_channel(MEM_PF_U_MEM);
+	ipu_uninit_channel(MEM_PF_V_MEM);
+
+	if (pf_data.qp_vaddr) {
+		dma_free_coherent(NULL, pf_data.qp_size, pf_data.qp_vaddr,
+				  pf_data.qp_paddr);
+		pf_data.qp_vaddr = NULL;
+	}
+
+	return 0;
+}
+
+/*!
+ * This function handles PF_IOCTL_REQBUFS calls. It initializes the PF channels
+ * and channel buffers.
+ *
+ * @param       reqbufs         Input/Output Structure containing buffer mode,
+ *                              type, offset, and size. The offset and size of
+ *                              the buffer are returned for PF_MEMORY_MMAP mode.
+ *
+ * @return      This function returns 0 on success or negative error code
+ *              on error.
+ */
+static int mxc_pf_reqbufs(pf_reqbufs_params * reqbufs)
+{
+	int err;
+	uint32_t buf_size;
+	int i;
+	int alloc_cnt = 0;
+	pf_buf *buf = pf_data.buf;
+	if (reqbufs->count > PF_MAX_BUFFER_CNT) {
+		reqbufs->count = PF_MAX_BUFFER_CNT;
+	}
+	/* Deallocate mmapped buffers */
+	if (reqbufs->count == 0) {
+		for (i = 0; i < PF_MAX_BUFFER_CNT; i++) {
+			if (buf[i].index != -1) {
+				dma_free_coherent(NULL, buf[i].size,
+						  pf_data.buf_vaddr[i],
+						  buf[i].offset);
+				pf_data.buf_vaddr[i] = NULL;
+				buf[i].index = -1;
+				buf[i].size = 0;
+			}
+		}
+		return 0;
+	}
+
+	buf_size = (pf_data.stride * pf_data.height * 3) / 2;
+	if (reqbufs->req_size > buf_size) {
+		buf_size = reqbufs->req_size;
+		pr_debug("using requested buffer size of %d\n", buf_size);
+	} else {
+		reqbufs->req_size = buf_size;
+		pr_debug("using default buffer size of %d\n", buf_size);
+	}
+
+	for (i = 0; alloc_cnt < reqbufs->count; i++) {
+		buf[i].index = i;
+		buf[i].size = buf_size;
+		pf_data.buf_vaddr[i] = dma_alloc_coherent(NULL, buf[i].size,
+							  &buf[i].offset,
+							  GFP_KERNEL | GFP_DMA);
+		if (!pf_data.buf_vaddr[i] || !buf[i].offset) {
+			printk(KERN_ERR
+			       "mxc_pf: unable to allocate IPU buffers.\n");
+			err = -ENOMEM;
+			goto err0;
+		}
+		pr_debug("Allocated buffer %d at paddr 0x%08X, vaddr %p\n",
+			 i, buf[i].offset, pf_data.buf_vaddr[i]);
+
+		alloc_cnt++;
+	}
+
+	return 0;
+      err0:
+	for (i = 0; i < alloc_cnt; i++) {
+		dma_free_coherent(NULL, buf[i].size, pf_data.buf_vaddr[i],
+				  buf[i].offset);
+		pf_data.buf_vaddr[i] = NULL;
+		buf[i].index = -1;
+		buf[i].size = 0;
+	}
+	return err;
+}
+
+/*!
+ * This function handles PF_IOCTL_START calls. It sets the PF channel buffers
+ * addresses and starts the channels
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              error.
+ */
+static int mxc_pf_start(pf_buf * in, pf_buf * out, int qp_buf)
+{
+	int err;
+	dma_addr_t y_in_paddr;
+	dma_addr_t u_in_paddr;
+	dma_addr_t v_in_paddr;
+	dma_addr_t p1_in_paddr;
+	dma_addr_t p2_in_paddr;
+	dma_addr_t y_out_paddr;
+	dma_addr_t u_out_paddr;
+	dma_addr_t v_out_paddr;
+
+	/* H.264 requires output buffer equal to input */
+	if (pf_data.mode == PF_H264_DEBLOCK)
+		out = in;
+
+	y_in_paddr = in->offset + in->y_offset;
+	if (in->u_offset)
+		u_in_paddr = in->offset + in->u_offset;
+	else
+		u_in_paddr = y_in_paddr + (pf_data.stride * pf_data.height);
+	if (in->v_offset)
+		v_in_paddr = in->offset + in->v_offset;
+	else
+		v_in_paddr = u_in_paddr + (pf_data.stride * pf_data.height) / 4;
+	p1_in_paddr = pf_data.qp_paddr;
+	if (qp_buf)
+		p1_in_paddr += pf_data.qp_size / 2;
+
+	if (pf_data.mode == PF_H264_DEBLOCK) {
+		p2_in_paddr = p1_in_paddr +
+		    ((pf_data.width + 15) / 16) *
+		    ((pf_data.height + 15) / 16) * 4;
+	} else {
+		p2_in_paddr = 0;
+	}
+
+	pr_debug("y_in_paddr = 0x%08X\nu_in_paddr = 0x%08X\n"
+		 "v_in_paddr = 0x%08X\n"
+		 "qp_paddr = 0x%08X\nbsb_paddr = 0x%08X\n",
+		 y_in_paddr, u_in_paddr, v_in_paddr, p1_in_paddr, p2_in_paddr);
+
+	y_out_paddr = out->offset + out->y_offset;
+	if (out->u_offset)
+		u_out_paddr = out->offset + out->u_offset;
+	else
+		u_out_paddr = y_out_paddr + (pf_data.stride * pf_data.height);
+	if (out->v_offset)
+		v_out_paddr = out->offset + out->v_offset;
+	else
+		v_out_paddr =
+		    u_out_paddr + (pf_data.stride * pf_data.height) / 4;
+
+	pr_debug("y_out_paddr = 0x%08X\nu_out_paddr = 0x%08X\n"
+		 "v_out_paddr = 0x%08X\n",
+		 y_out_paddr, u_out_paddr, v_out_paddr);
+
+	pf_data.done_mask = 0;
+
+	ipu_enable_irq(IPU_IRQ_PF_Y_OUT_EOF);
+	if (pf_data.mode != PF_MPEG4_DERING) {
+		ipu_enable_irq(IPU_IRQ_PF_U_OUT_EOF);
+		ipu_enable_irq(IPU_IRQ_PF_V_OUT_EOF);
+	}
+
+	err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0,
+					y_in_paddr);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error setting Y input buffer\n");
+		goto err0;
+	}
+
+	err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0,
+					y_out_paddr);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error setting Y output buffer\n");
+		goto err0;
+	}
+
+	if (pf_data.mode != PF_MPEG4_DERING) {
+		err =
+		    ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0,
+					      u_in_paddr);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error setting U input buffer\n");
+			goto err0;
+		}
+
+		err =
+		    ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER,
+					      0, u_out_paddr);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error setting U output buffer\n");
+			goto err0;
+		}
+
+		err =
+		    ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0,
+					      v_in_paddr);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error setting V input buffer\n");
+			goto err0;
+		}
+
+		err =
+		    ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER,
+					      0, v_out_paddr);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error setting V output buffer\n");
+			goto err0;
+		}
+	}
+
+	err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0,
+					p1_in_paddr);
+	if (err < 0) {
+		printk(KERN_ERR "mxc_pf: error setting QP buffer\n");
+		goto err0;
+	}
+
+	if (pf_data.mode == PF_H264_DEBLOCK) {
+
+		err = ipu_update_channel_buffer(MEM_PF_U_MEM,
+						IPU_SEC_INPUT_BUFFER, 0,
+						p2_in_paddr);
+		if (err < 0) {
+			printk(KERN_ERR
+			       "mxc_pf: error setting H264 BSB buffer\n");
+			goto err0;
+		}
+		ipu_select_buffer(MEM_PF_U_MEM, IPU_SEC_INPUT_BUFFER, 0);
+	}
+
+	ipu_select_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0);
+	ipu_select_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0);
+	ipu_select_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0);
+	if (pf_data.mode != PF_MPEG4_DERING) {
+		ipu_select_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0);
+		ipu_select_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0);
+	}
+
+	if (!pf_data.pf_enabled) {
+		pf_data.pf_enabled = 1;
+		if (pf_data.mode != PF_MPEG4_DERING) {
+			ipu_enable_channel(MEM_PF_V_MEM);
+			ipu_enable_channel(MEM_PF_U_MEM);
+		}
+		ipu_enable_channel(MEM_PF_Y_MEM);
+	}
+
+	return 0;
+      err0:
+	return err;
+}
+
+/*!
+ * Post Filter driver open function. This function implements the Linux
+ * file_operations.open() API function.
+ *
+ * @param       inode           struct inode *
+ *
+ * @param       filp            struct file *
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              error.
+ */
+static int mxc_pf_open(struct inode *inode, struct file *filp)
+{
+	int i;
+
+	if (open_count) {
+		return -EBUSY;
+	}
+
+	open_count++;
+
+	memset(&pf_data, 0, sizeof(pf_data));
+	for (i = 0; i < PF_MAX_BUFFER_CNT; i++) {
+		pf_data.buf[i].index = -1;
+	}
+	init_waitqueue_head(&pf_data.pf_wait);
+	init_MUTEX(&pf_data.busy_lock);
+
+	pf_data.busy_flag = 1;
+
+	ipu_request_irq(IPU_IRQ_PF_Y_OUT_EOF, mxc_pf_irq_handler,
+			0, "mxc_ipu_pf", &pf_data);
+
+	ipu_request_irq(IPU_IRQ_PF_U_OUT_EOF, mxc_pf_irq_handler,
+			0, "mxc_ipu_pf", &pf_data);
+
+	ipu_request_irq(IPU_IRQ_PF_V_OUT_EOF, mxc_pf_irq_handler,
+			0, "mxc_ipu_pf", &pf_data);
+
+	ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF);
+	ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF);
+	ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF);
+
+	return 0;
+}
+
+/*!
+ * Post Filter driver release function. This function implements the Linux
+ * file_operations.release() API function.
+ *
+ * @param       inode           struct inode *
+ *
+ * @param       filp            struct file *
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              error.
+ */
+static int mxc_pf_release(struct inode *inode, struct file *filp)
+{
+	pf_reqbufs_params req_buf;
+
+	if (open_count) {
+		mxc_pf_uninit();
+
+		/* Free any allocated buffers */
+		req_buf.count = 0;
+		mxc_pf_reqbufs(&req_buf);
+
+		ipu_free_irq(IPU_IRQ_PF_V_OUT_EOF, &pf_data);
+		ipu_free_irq(IPU_IRQ_PF_U_OUT_EOF, &pf_data);
+		ipu_free_irq(IPU_IRQ_PF_Y_OUT_EOF, &pf_data);
+		open_count--;
+	}
+	return 0;
+}
+
+/*!
+ * Post Filter driver ioctl function. This function implements the Linux
+ * file_operations.ioctl() API function.
+ *
+ * @param       inode           struct inode *
+ *
+ * @param       filp            struct file *
+ *
+ * @param       cmd             IOCTL command to handle
+ *
+ * @param       arg             Pointer to arguments for IOCTL
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              error.
+ */
+static int mxc_pf_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+
+	switch (cmd) {
+	case PF_IOCTL_INIT:
+		{
+			pf_init_params pf_init;
+
+			pr_debug("PF_IOCTL_INIT\n");
+			if (copy_from_user(&pf_init, (void *)arg,
+					   _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			retval = mxc_pf_init(&pf_init);
+			if (retval < 0)
+				break;
+			pf_init.qp_paddr = pf_data.qp_paddr;
+			pf_init.qp_size = pf_data.qp_size;
+
+			/* Return size of memory allocated */
+			if (copy_to_user((void *)arg, &pf_init, _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			pf_data.busy_flag = 0;
+			break;
+		}
+	case PF_IOCTL_UNINIT:
+		pr_debug("PF_IOCTL_UNINIT\n");
+		retval = mxc_pf_uninit();
+		break;
+	case PF_IOCTL_REQBUFS:
+		{
+			pf_reqbufs_params reqbufs;
+			pr_debug("PF_IOCTL_REQBUFS\n");
+
+			if (copy_from_user
+			    (&reqbufs, (void *)arg, _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			retval = mxc_pf_reqbufs(&reqbufs);
+
+			/* Return size of memory allocated */
+			if (copy_to_user((void *)arg, &reqbufs, _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			break;
+		}
+	case PF_IOCTL_QUERYBUF:
+		{
+			pf_buf buf;
+			pr_debug("PF_IOCTL_QUERYBUF\n");
+
+			if (copy_from_user(&buf, (void *)arg, _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if ((buf.index < 0) ||
+			    (buf.index >= PF_MAX_BUFFER_CNT) ||
+			    (pf_data.buf[buf.index].index != buf.index)) {
+				retval = -EINVAL;
+				break;
+			}
+			/* Return size of memory allocated */
+			if (copy_to_user((void *)arg, &pf_data.buf[buf.index],
+					 _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			break;
+		}
+	case PF_IOCTL_START:
+		{
+			int index;
+			pf_start_params start_params;
+			pr_debug("PF_IOCTL_START\n");
+
+			if (pf_data.busy_flag) {
+				retval = -EBUSY;
+				break;
+			}
+
+			if (copy_from_user(&start_params, (void *)arg,
+					   _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+			if (start_params.h264_pause_row >=
+			    ((pf_data.height + 15) / 16)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			pf_data.busy_flag = 1;
+
+			index = start_params.in.index;
+			if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) {
+				if (pf_data.buf[index].offset !=
+				    start_params.in.offset) {
+					retval = -EINVAL;
+					break;
+				}
+			}
+
+			index = start_params.out.index;
+			if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) {
+				if (pf_data.buf[index].offset !=
+				    start_params.out.offset) {
+					retval = -EINVAL;
+					break;
+				}
+			}
+
+			ipu_pf_set_pause_row(start_params.h264_pause_row);
+
+			/*Update y, u, v buffers in DMA Channels */
+			if ((retval =
+			     mxc_pf_start(&start_params.in, &start_params.out,
+					  start_params.qp_buf))
+			    < 0) {
+				break;
+			}
+
+			pr_debug("PF_IOCTL_START - processing started\n");
+
+			if (!start_params.wait) {
+				break;
+			}
+
+			pr_debug("PF_IOCTL_START - waiting for completion\n");
+
+			pf_data.wait_mask = PF_WAIT_ALL;
+			/* Fall thru to wait */
+		}
+	case PF_IOCTL_WAIT:
+		{
+			if (!pf_data.wait_mask)
+				pf_data.wait_mask = (u32) arg;
+
+			if (pf_data.mode == PF_MPEG4_DERING)
+				pf_data.wait_mask &= PF_WAIT_Y;
+
+			if (!pf_data.wait_mask) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (!wait_event_interruptible_timeout(pf_data.pf_wait,
+							      ((pf_data.
+								done_mask &
+								pf_data.
+								wait_mask) ==
+							       pf_data.
+							       wait_mask),
+							      1 * HZ)) {
+				pr_debug
+				    ("PF_IOCTL_WAIT: timeout, done_mask = %d\n",
+				     pf_data.done_mask);
+				retval = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				pr_debug("PF_IOCTL_WAIT: interrupt received\n");
+				retval = -ERESTARTSYS;
+				break;
+			}
+			pf_data.busy_flag = 0;
+			pf_data.wait_mask = 0;
+
+			pr_debug("PF_IOCTL_WAIT - finished\n");
+			break;
+		}
+	case PF_IOCTL_RESUME:
+		{
+			int pause_row;
+			pr_debug("PF_IOCTL_RESUME\n");
+
+			if (pf_data.busy_flag == 0) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (copy_from_user(&pause_row, (void *)arg,
+					   _IOC_SIZE(cmd))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (pause_row >= ((pf_data.height + 15) / 16)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			ipu_pf_set_pause_row(pause_row);
+			break;
+		}
+
+	default:
+		printk(KERN_ERR "ipu_pf_ioctl not supported ioctl\n");
+		retval = -1;
+	}
+
+	if (retval < 0)
+		pr_debug("return = %d\n", retval);
+	return retval;
+}
+
+/*!
+ * Post Filter driver mmap function. This function implements the Linux
+ * file_operations.mmap() API function for mapping driver buffers to user space.
+ *
+ * @param       file            struct file *
+ *
+ * @param       vma             structure vm_area_struct *
+ *
+ * @return      0 Success, EINTR busy lock error,
+ *                      ENOBUFS remap_page error.
+ */
+static int mxc_pf_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	unsigned long size = vma->vm_end - vma->vm_start;
+	int res = 0;
+
+	pr_debug("pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
+		 vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* make this _really_ smp-safe */
+	if (down_interruptible(&pf_data.busy_lock))
+		return -EINTR;
+
+	/* make buffers write-thru cacheable */
+	vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) &
+				     ~L_PTE_BUFFERABLE);
+
+	if (remap_pfn_range(vma, vma->vm_start,
+			    vma->vm_pgoff, size, vma->vm_page_prot)) {
+		printk(KERN_ERR "mxc_pf: remap_pfn_range failed\n");
+		res = -ENOBUFS;
+		goto mmap_exit;
+	}
+
+	vma->vm_flags &= ~VM_IO;	/* using shared anonymous pages */
+
+      mmap_exit:
+	up(&pf_data.busy_lock);
+	return res;
+}
+
+/*!
+ * Post Filter driver fsync function. This function implements the Linux
+ * file_operations.fsync() API function.
+ *
+ * The user must call fsync() before reading an output buffer. This
+ * call flushes the L1 and L2 caches
+ *
+ * @param filp          structure file *
+ *
+ * @param dentry        struct dentry *
+ *
+ * @param datasync      unused
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+int mxc_pf_fsync(struct file *filp, struct dentry *dentry, int datasync)
+{
+	flush_cache_all();
+	outer_flush_all();
+	return 0;
+}
+
+/*!
+ * Post Filter driver poll function. This function implements the Linux
+ * file_operations.poll() API function.
+ *
+ * @param file       structure file *
+ *
+ * @param wait       structure poll_table *
+ *
+ * @return  status   POLLIN | POLLRDNORM
+ */
+static unsigned int mxc_pf_poll(struct file *file, poll_table * wait)
+{
+	wait_queue_head_t *queue = NULL;
+	int res = POLLIN | POLLRDNORM;
+
+	if (down_interruptible(&pf_data.busy_lock))
+		return -EINTR;
+
+	queue = &pf_data.pf_wait;
+	poll_wait(file, queue, wait);
+
+	up(&pf_data.busy_lock);
+
+	return res;
+}
+
+/*!
+ * File operation structure functions pointers.
+ */
+static struct file_operations mxc_pf_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_pf_open,
+	.release = mxc_pf_release,
+	.ioctl = mxc_pf_ioctl,
+	.poll = mxc_pf_poll,
+	.mmap = mxc_pf_mmap,
+	.fsync = mxc_pf_fsync,
+};
+
+static int mxc_pf_major = 0;
+
+/*!
+ * Post Filter driver module initialization function.
+ */
+int mxc_pf_dev_init(void)
+{
+	int ret = 0;
+	struct device *temp_class;
+
+	mxc_pf_major = register_chrdev(0, "mxc_ipu_pf", &mxc_pf_fops);
+
+	if (mxc_pf_major < 0) {
+		printk(KERN_INFO "Unable to get a major for mxc_ipu_pf");
+		return mxc_pf_major;
+	}
+
+	mxc_pf_class = class_create(THIS_MODULE, "mxc_ipu_pf");
+	if (IS_ERR(mxc_pf_class)) {
+		printk(KERN_ERR "Error creating mxc_ipu_pf class.\n");
+		ret = PTR_ERR(mxc_pf_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(mxc_pf_class, NULL, MKDEV(mxc_pf_major, 0), NULL,
+				   "mxc_ipu_pf");
+	if (IS_ERR(temp_class)) {
+		printk(KERN_ERR "Error creating mxc_ipu_pf class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	printk(KERN_INFO "IPU Post-filter loading\n");
+
+	return 0;
+
+      err_out2:
+	class_destroy(mxc_pf_class);
+      err_out1:
+	unregister_chrdev(mxc_pf_major, "mxc_ipu_pf");
+	return ret;
+}
+
+/*!
+ * Post Filter driver module exit function.
+ */
+static void mxc_pf_exit(void)
+{
+	if (mxc_pf_major > 0) {
+		device_destroy(mxc_pf_class, MKDEV(mxc_pf_major, 0));
+		class_destroy(mxc_pf_class);
+		unregister_chrdev(mxc_pf_major, "mxc_ipu_pf");
+	}
+}
+
+module_init(mxc_pf_dev_init);
+module_exit(mxc_pf_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC MPEG4/H.264 Postfilter Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/ipu3/Kconfig b/drivers/mxc/ipu3/Kconfig
new file mode 100644
index 000000000000..0ae0ffa9e19d
--- /dev/null
+++ b/drivers/mxc/ipu3/Kconfig
@@ -0,0 +1,5 @@
+config MXC_IPU_V3
+	bool
+
+config MXC_IPU_V3D
+	bool
diff --git a/drivers/mxc/ipu3/Makefile b/drivers/mxc/ipu3/Makefile
new file mode 100644
index 000000000000..aa3e7b1bb501
--- /dev/null
+++ b/drivers/mxc/ipu3/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o
+
+mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o ipu_calc_stripes_sizes.o
+
diff --git a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
new file mode 100644
index 000000000000..5d5e0b9155a0
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_calc_stripes_sizes.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/module.h>
+#include <linux/ipu.h>
+#include <asm/div64.h>
+
+#define BPP_32 0
+#define BPP_16 3
+#define BPP_8 5
+#define BPP_24 1
+#define BPP_12 4
+#define BPP_18 2
+
+static u64 _do_div(u64 a, u32 b)
+{
+	u64 div;
+	div = a;
+	do_div(div, b);
+	return div;
+}
+
+static u32 truncate(u32 up, /* 0: down; else: up */
+					u64 a, /* must be non-negative */
+					u32 b)
+{
+	u32 d;
+	u64 div;
+	div = _do_div(a, b);
+	d = b * (div >> 32);
+	if (up && (a > (((u64)d) << 32)))
+		return d+b;
+	else
+		return d;
+}
+
+static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
+{/* return input_f */
+	unsigned int f_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		f_calculated = 16;
+		break;
+
+	case IPU_PIX_FMT_NV12:
+		f_calculated = 8;
+		break;
+
+	default:
+		f_calculated = 0;
+		break;
+
+	}
+	if (!f_calculated) {
+		switch (bpp) {
+		case BPP_32:
+			f_calculated = 2;
+			break;
+
+		case BPP_16:
+			f_calculated = 4;
+			break;
+
+		case BPP_8:
+		case BPP_24:
+			f_calculated = 8;
+			break;
+
+		case BPP_12:
+			f_calculated = 16;
+			break;
+
+		case BPP_18:
+			f_calculated = 32;
+			break;
+
+		default:
+			f_calculated = 0;
+			break;
+			}
+		}
+	return f_calculated;
+}
+
+
+static unsigned int m_calc(unsigned int pfs)
+{
+	unsigned int m_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+		m_calculated = 8;
+		break;
+
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		m_calculated = 2;
+		break;
+
+	default:
+		m_calculated = 1;
+		break;
+
+	}
+	return m_calculated;
+}
+
+
+/* Stripe parameters calculator */
+/**************************************************************************
+Notes:
+MSW = the maximal width allowed for a stripe
+	i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
+cirr = the maximal inverse resizing ratio for which overlap in the input
+	is requested; typically cirr~2
+equal_stripes:
+	0: each stripe is allowed to have independent parameters
+		for maximal image quality
+	1: the stripes are requested to have identical parameters
+	(except the base address), for maximal performance
+If performance is the top priority (above image quality)
+	Avoid overlap, by setting CIRR = 0
+		This will also force effectively identical_stripes = 1
+	Choose IF & OF that corresponds to the same IOX/SX for both stripes
+	Choose IFW & OFW such that
+	IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
+	The function returns an error status:
+	0: no error
+	1: invalid input parameters -> aborted without result
+		Valid parameters should satisfy the following conditions
+		IFW <= OFW, otherwise downsizing is required
+					 - which is not supported yet
+		4 <= IFW,OFW, so some interpolation may be needed even without overlap
+		IM, OM, IF, OF should not vanish
+		2*IF <= IFW
+		so the frame can be split to two equal stripes, even without overlap
+		2*(OF+IF/irr_opt) <= OFW
+		so a valid positive INW exists even for equal stripes
+		OF <= MSW, otherwise, the left stripe cannot be sufficiently large
+		MSW < OFW, so splitting to stripes is required
+		OFW <= 2*MSW, so two stripes are sufficient
+		(this also implies that 2<=MSW)
+	2: OF is not a multiple of OM - not fully-supported yet
+	Output is produced but OW is not guaranited to be a multiple of OM
+	4: OFW reduced to be a multiple of OM
+	8: CIRR > 1: truncated to 1
+	Overlap is not supported (and not needed) y for upsizing)
+**************************************************************************/
+int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
+			   /* input frame width;>1 */
+			   unsigned int output_frame_width, /* output frame width; >1 */
+			   const unsigned int maximal_stripe_width,
+			   /* the maximal width allowed for a stripe */
+			   const unsigned long long cirr, /* see above */
+			   const unsigned int equal_stripes, /* see above */
+			   u32 input_pixelformat,/* pixel format after of read channel*/
+			   u32 output_pixelformat,/* pixel format after of write channel*/
+			   struct stripe_param *left,
+			   struct stripe_param *right)
+{
+	const unsigned int irr_frac_bits = 13;
+	const unsigned long irr_steps = 1 << irr_frac_bits;
+	const u64 dirr = ((u64)1) << (32 - 2);
+	/* The maximum relative difference allowed between the irrs */
+	const u64 cr = ((u64)4) << 32;
+	/* The importance ratio between the two terms in the cost function below */
+
+	unsigned int status;
+	unsigned int temp;
+	unsigned int onw_min;
+	unsigned int inw, onw, inw_best = 0;
+	/* number of pixels in the left stripe NOT hidden by the right stripe */
+	u64 irr_opt; /* the optimal inverse resizing ratio */
+	u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
+	u64 dinw; /* the misalignment between the stripes */
+	/* (measured in units of input columns) */
+	u64 difwl, difwr;
+	/* The number of input columns not reflected in the output */
+	/* the resizing ratio used for the right stripe is */
+	/*   left->irr and right->irr respectively */
+	u64 cost, cost_min;
+	u64 div; /* result of division */
+
+	unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
+
+	status = 0;
+
+	/* M, F calculations */
+	/* read back pfs from params */
+
+	input_f = f_calc(input_pixelformat, 0, NULL);
+	input_m = 16;
+	/* BPP should be used in the out_F calc */
+	/* Temporarily not used */
+	/* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */
+
+	output_f = 16;
+	output_m = m_calc(output_pixelformat);
+
+
+	if ((input_frame_width < 4) || (output_frame_width < 4))
+		return 1;
+
+	irr_opt = _do_div((((u64)(input_frame_width - 1)) << 32),
+			  (output_frame_width - 1));
+	rr_opt = _do_div((((u64)(output_frame_width - 1)) << 32),
+			 (input_frame_width - 1));
+
+	if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
+	    || (input_frame_width < (2 * input_f))
+	    || ((((u64)output_frame_width) << 32) <
+		(2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
+	    || (maximal_stripe_width < output_f)
+	    || (output_frame_width <= maximal_stripe_width)
+	    || ((2 * maximal_stripe_width) < output_frame_width))
+		return 1;
+
+	if (output_f % output_m)
+		status += 2;
+
+	temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
+	if (temp < output_frame_width) {
+		output_frame_width = temp;
+		status += 4;
+	}
+
+	if (equal_stripes) {
+		if ((irr_opt > cirr) /* overlap in the input is not requested */
+		    && ((input_frame_width % (input_m << 1)) == 0)
+		    && ((input_frame_width % (input_f << 1)) == 0)
+		    && ((output_frame_width % (output_m << 1)) == 0)
+		    && ((output_frame_width % (output_f << 1)) == 0)) {
+			/* without overlap */
+			left->input_width = right->input_width = right->input_column =
+				input_frame_width >> 1;
+			left->output_width = right->output_width = right->output_column =
+				output_frame_width >> 1;
+			left->input_column = 0;
+			div = _do_div(((((u64)irr_steps) << 32) *
+				       (right->input_width - 1)), (right->output_width - 1));
+			left->irr = right->irr = truncate(0, div, 1);
+		} else { /* with overlap */
+			onw = truncate(0, (((u64)output_frame_width - 1) << 32) >> 1,
+				       output_f);
+			inw = truncate(0, onw * irr_opt, input_f);
+			/* this is the maximal inw which allows the same resizing ratio */
+			/* in both stripes */
+			onw = truncate(1, (inw * rr_opt), output_f);
+			div = _do_div((((u64)(irr_steps * inw)) <<
+				       32), onw);
+			left->irr = right->irr = truncate(0, div, 1);
+			left->output_width = right->output_width =
+				output_frame_width - onw;
+			/* These are valid assignments for output_width, */
+			/* assuming output_f is a multiple of output_m */
+			div = (((u64)(left->output_width-1) * (left->irr)) << 32);
+			div = (((u64)1) << 32) + _do_div(div, irr_steps);
+
+			left->input_width = right->input_width = truncate(1, div, input_m);
+
+			div = _do_div((((u64)((right->output_width - 1) * right->irr)) <<
+				       32), irr_steps);
+			difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+			div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+			left->input_column = truncate(0, div, input_f);
+
+
+			/* This splits the truncated input columns evenly */
+			/*    between the left and right margins */
+			right->input_column = left->input_column + inw;
+			left->output_column = 0;
+			right->output_column = onw;
+		}
+	} else { /* independent stripes */
+		onw_min = output_frame_width - maximal_stripe_width;
+		/* onw is a multiple of output_f, in the range */
+		/* [max(output_f,output_frame_width-maximal_stripe_width),*/
+		/*min(output_frame_width-2,maximal_stripe_width)] */
+		/* definitely beyond the cost of any valid setting */
+		cost_min = (((u64)input_frame_width) << 32) + cr;
+		onw = truncate(0, ((u64)maximal_stripe_width), output_f);
+		if (output_frame_width - onw == 1)
+			onw -= output_f; /*  => onw and output_frame_width-1-onw are positive */
+		inw = truncate(0, onw * irr_opt, input_f);
+		/* this is the maximal inw which allows the same resizing ratio */
+		/* in both stripes */
+		onw = truncate(1, inw * rr_opt, output_f);
+		do {
+			div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+			left->irr = truncate(0, div, 1);
+			div = _do_div((((u64)(onw * left->irr)) << 32),
+				      irr_steps);
+			dinw = (((u64)inw) << 32) - div;
+
+			div = _do_div((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
+				       32), irr_steps);
+
+			difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+
+			cost = difwl + (((u64)(cr * dinw)) >> 32);
+
+			if (cost < cost_min) {
+				inw_best = inw;
+				cost_min = cost;
+			}
+
+			inw -= input_f;
+			onw = truncate(1, inw * rr_opt, output_f);
+			/* This is the minimal onw which allows the same resizing ratio */
+			/*     in both stripes */
+		} while (onw >= onw_min);
+
+		inw = inw_best;
+		onw = truncate(1, inw * rr_opt, output_f);
+		div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+		left->irr = truncate(0, div, 1);
+
+		left->output_width = onw;
+		right->output_width = output_frame_width - onw;
+		/* These are valid assignments for output_width, */
+		/* assuming output_f is a multiple of output_m */
+		left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
+		right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
+					      32, input_m);
+
+		div = _do_div((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
+			       32), (right->output_width - 1));
+		right->irr = truncate(0, div, 1);
+		temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
+		if (temp < right->irr)
+			right->irr = temp;
+		div = _do_div(((u64)((right->output_width - 1) * right->irr) <<
+			       32), irr_steps);
+		difwr = (u64)(input_frame_width - 1 - inw) - div;
+
+
+		div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+		left->input_column = truncate(0, div, input_f);
+
+		/* This splits the truncated input columns evenly */
+		/*    between the left and right margins */
+		right->input_column = left->input_column + inw;
+		left->output_column = 0;
+		right->output_column = onw;
+	}
+	return status;
+}
+EXPORT_SYMBOL(ipu_calc_stripes_sizes);
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c
new file mode 100644
index 000000000000..f7510cf65b60
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_capture.c
@@ -0,0 +1,741 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_capture.c
+ *
+ * @brief IPU capture dase functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/ipu.h>
+#include <linux/clk.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+
+/*!
+ * ipu_csi_init_interface
+ *	Sets initial values for the CSI registers.
+ *	The width and height of the sensor and the actual frame size will be
+ *	set to the same values.
+ * @param	width		Sensor width
+ * @param       height		Sensor height
+ * @param       pixel_fmt	pixel format
+ * @param       cfg_param	ipu_csi_signal_cfg_t structure
+ * @param       csi             csi 0 or csi 1
+ *
+ * @return      0 for success, -EINVAL for error
+ */
+int32_t
+ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt,
+	ipu_csi_signal_cfg_t cfg_param)
+{
+	uint32_t data = 0;
+	uint32_t csi = cfg_param.csi;
+	unsigned long lock_flags;
+
+	/* Set SENS_DATA_FORMAT bits (8, 9 and 10)
+	   RGB or YUV444 is 0 which is current value in data so not set
+	   explicitly
+	   This is also the default value if attempts are made to set it to
+	   something invalid. */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_YUYV:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
+		break;
+	case IPU_PIX_FMT_UYVY:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR24:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
+		break;
+	case IPU_PIX_FMT_GENERIC:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
+		break;
+	case IPU_PIX_FMT_RGB565:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
+		break;
+	case IPU_PIX_FMT_RGB555:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set the CSI_SENS_CONF register remaining fields */
+	data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
+		cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
+		cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
+		cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
+		cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
+		cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
+		cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
+		cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
+		cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
+		cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
+		cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	__raw_writel(data, CSI_SENS_CONF(csi));
+
+	/* Setup sensor frame size */
+	__raw_writel((width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE(csi));
+
+	/* Set CCIR registers */
+	if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
+		__raw_writel(0x40030, CSI_CCIR_CODE_1(csi));
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));
+	} else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
+		_ipu_csi_ccir_err_detection_enable(csi);
+		/* Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
+		   Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 */
+		__raw_writel(0xD07DF, CSI_CCIR_CODE_1(csi));
+		/* Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
+		   Field1ActiveEnd = 0x4, Field1ActiveStart = 0 */
+		__raw_writel(0x40596, CSI_CCIR_CODE_2(csi));
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));
+	} else if ((cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {
+		_ipu_csi_ccir_err_detection_enable(csi);
+		__raw_writel(0x40030, CSI_CCIR_CODE_1(csi));
+		__raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));
+	} else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) ||
+		   (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) {
+		_ipu_csi_ccir_err_detection_disable(csi);
+	}
+
+	dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n",
+		__raw_readl(CSI_SENS_CONF(csi)));
+	dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
+		__raw_readl(CSI_ACT_FRM_SIZE(csi)));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_csi_init_interface);
+
+/*! _ipu_csi_mclk_set
+ *
+ * @param	pixel_clk   desired pixel clock frequency in Hz
+ * @param	csi         csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_mclk_set(uint32_t pixel_clk, uint32_t csi)
+{
+	uint32_t temp;
+	uint32_t div_ratio;
+
+	div_ratio = (clk_get_rate(g_ipu_clk) / pixel_clk) - 1;
+
+	if (div_ratio > 0xFF || div_ratio < 0) {
+		dev_dbg(g_ipu_dev, "The value of pixel_clk extends normal range\n");
+		return -EINVAL;
+	}
+
+	temp = __raw_readl(CSI_SENS_CONF(csi));
+	temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
+	__raw_writel(temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
+			CSI_SENS_CONF(csi));
+
+	return 0;
+}
+
+/*!
+ * ipu_csi_enable_mclk
+ *
+ * @param	csi         csi 0 or csi 1
+ * @param       flag        true to enable mclk, false to disable mclk
+ * @param       wait        true to wait 100ms make clock stable, false not wait
+ *
+ * @return      Returns 0 on success
+ */
+int ipu_csi_enable_mclk(int csi, bool flag, bool wait)
+{
+	struct clk *clk;
+
+	if (flag) {
+		if (cpu_is_mx53()) {
+			if (csi == 0) {
+				clk = clk_get(NULL, "ssi_ext1_clk");
+				clk_enable(clk);
+				clk_put(clk);
+			} else {
+				pr_err("invalid csi num %d\n", csi);
+				return -EINVAL;
+			}
+		} else
+			clk_enable(g_csi_clk[csi]);
+		if (wait == true)
+			msleep(10);
+	} else {
+		if (cpu_is_mx53()) {
+			if (csi == 0) {
+				clk = clk_get(NULL, "ssi_ext1_clk");
+				clk_disable(clk);
+				clk_put(clk);
+			} else {
+				pr_err("invalid csi num %d\n", csi);
+				return -EINVAL;
+			}
+		} else
+			clk_disable(g_csi_clk[csi]);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_csi_enable_mclk);
+
+/*!
+ * ipu_csi_get_window_size
+ *
+ * @param	width	pointer to window width
+ * @param	height	pointer to window height
+ * @param	csi	csi 0 or csi 1
+ */
+void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, uint32_t csi)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(CSI_ACT_FRM_SIZE(csi));
+	*width = (reg & 0xFFFF) + 1;
+	*height = (reg >> 16 & 0xFFFF) + 1;
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_csi_get_window_size);
+
+/*!
+ * ipu_csi_set_window_size
+ *
+ * @param	width	window width
+ * @param       height	window height
+ * @param       csi	csi 0 or csi 1
+ */
+void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t csi)
+{
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	__raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_csi_set_window_size);
+
+/*!
+ * ipu_csi_set_window_pos
+ *
+ * @param       left	uint32 window x start
+ * @param       top	uint32 window y start
+ * @param       csi	csi 0 or csi 1
+ */
+void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_OUT_FRM_CTRL(csi));
+	temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
+	temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
+	__raw_writel(temp, CSI_OUT_FRM_CTRL(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_csi_set_window_pos);
+
+/*!
+ * _ipu_csi_horizontal_downsize_enable
+ *	Enable horizontal downsizing(decimation) by 2.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_horizontal_downsize_enable(uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_OUT_FRM_CTRL(csi));
+	temp |= CSI_HORI_DOWNSIZE_EN;
+	__raw_writel(temp, CSI_OUT_FRM_CTRL(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * _ipu_csi_horizontal_downsize_disable
+ *	Disable horizontal downsizing(decimation) by 2.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_horizontal_downsize_disable(uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_OUT_FRM_CTRL(csi));
+	temp &= ~CSI_HORI_DOWNSIZE_EN;
+	__raw_writel(temp, CSI_OUT_FRM_CTRL(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * _ipu_csi_vertical_downsize_enable
+ *	Enable vertical downsizing(decimation) by 2.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_vertical_downsize_enable(uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_OUT_FRM_CTRL(csi));
+	temp |= CSI_VERT_DOWNSIZE_EN;
+	__raw_writel(temp, CSI_OUT_FRM_CTRL(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * _ipu_csi_vertical_downsize_disable
+ *	Disable vertical downsizing(decimation) by 2.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_vertical_downsize_disable(uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_OUT_FRM_CTRL(csi));
+	temp &= ~CSI_VERT_DOWNSIZE_EN;
+	__raw_writel(temp, CSI_OUT_FRM_CTRL(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * ipu_csi_set_test_generator
+ *
+ * @param	active       1 for active and 0 for inactive
+ * @param       r_value	     red value for the generated pattern of even pixel
+ * @param       g_value      green value for the generated pattern of even
+ *			     pixel
+ * @param       b_value      blue value for the generated pattern of even pixel
+ * @param	pixel_clk   desired pixel clock frequency in Hz
+ * @param       csi          csi 0 or csi 1
+ */
+void ipu_csi_set_test_generator(bool active, uint32_t r_value,
+	uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_TST_CTRL(csi));
+
+	if (active == false) {
+		temp &= ~CSI_TEST_GEN_MODE_EN;
+		__raw_writel(temp, CSI_TST_CTRL(csi));
+	} else {
+		/* Set sensb_mclk div_ratio*/
+		_ipu_csi_mclk_set(pix_clk, csi);
+
+		temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
+			CSI_TEST_GEN_B_MASK);
+		temp |= CSI_TEST_GEN_MODE_EN;
+		temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
+			(g_value << CSI_TEST_GEN_G_SHIFT) |
+			(b_value << CSI_TEST_GEN_B_SHIFT);
+		__raw_writel(temp, CSI_TST_CTRL(csi));
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_csi_set_test_generator);
+
+/*!
+ * _ipu_csi_ccir_err_detection_en
+ *	Enable error detection and correction for
+ *	CCIR interlaced mode with protection bit.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_ccir_err_detection_enable(uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = __raw_readl(CSI_CCIR_CODE_1(csi));
+	temp |= CSI_CCIR_ERR_DET_EN;
+	__raw_writel(temp, CSI_CCIR_CODE_1(csi));
+}
+
+/*!
+ * _ipu_csi_ccir_err_detection_disable
+ *	Disable error detection and correction for
+ *	CCIR interlaced mode with protection bit.
+ *
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_ccir_err_detection_disable(uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = __raw_readl(CSI_CCIR_CODE_1(csi));
+	temp &= ~CSI_CCIR_ERR_DET_EN;
+	__raw_writel(temp, CSI_CCIR_CODE_1(csi));
+}
+
+/*!
+ * _ipu_csi_set_mipi_di
+ *
+ * @param	num	MIPI data identifier 0-3 handled by CSI
+ * @param	di_val	data identifier value
+ * @param	csi	csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_mipi_di(uint32_t num, uint32_t di_val, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+	unsigned long lock_flags;
+
+	if (di_val > 0xFFL) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_MIPI_DI(csi));
+
+	switch (num) {
+	case IPU_CSI_MIPI_DI0:
+		temp &= ~CSI_MIPI_DI0_MASK;
+		temp |= (di_val << CSI_MIPI_DI0_SHIFT);
+		__raw_writel(temp, CSI_MIPI_DI(csi));
+		break;
+	case IPU_CSI_MIPI_DI1:
+		temp &= ~CSI_MIPI_DI1_MASK;
+		temp |= (di_val << CSI_MIPI_DI1_SHIFT);
+		__raw_writel(temp, CSI_MIPI_DI(csi));
+		break;
+	case IPU_CSI_MIPI_DI2:
+		temp &= ~CSI_MIPI_DI2_MASK;
+		temp |= (di_val << CSI_MIPI_DI2_SHIFT);
+		__raw_writel(temp, CSI_MIPI_DI(csi));
+		break;
+	case IPU_CSI_MIPI_DI3:
+		temp &= ~CSI_MIPI_DI3_MASK;
+		temp |= (di_val << CSI_MIPI_DI3_SHIFT);
+		__raw_writel(temp, CSI_MIPI_DI(csi));
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_csi_set_skip_isp
+ *
+ * @param	skip		select frames to be skipped and set the
+ *				correspond bits to 1
+ * @param	max_ratio	number of frames in a skipping set and the
+ * 				maximum value of max_ratio is 5
+ * @param	csi		csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_skip_isp(uint32_t skip, uint32_t max_ratio, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+	unsigned long lock_flags;
+
+	if (max_ratio > 5) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_SKIP(csi));
+	temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK);
+	temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) |
+		(skip << CSI_SKIP_ISP_SHIFT);
+	__raw_writel(temp, CSI_SKIP(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_csi_set_skip_smfc
+ *
+ * @param	skip		select frames to be skipped and set the
+ *				correspond bits to 1
+ * @param	max_ratio	number of frames in a skipping set and the
+ *				maximum value of max_ratio is 5
+ * @param	id		csi to smfc skipping id
+ * @param	csi		csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_skip_smfc(uint32_t skip, uint32_t max_ratio,
+	uint32_t id, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+	unsigned long lock_flags;
+
+	if (max_ratio > 5 || id > 3) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(CSI_SKIP(csi));
+	temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
+			CSI_SKIP_SMFC_MASK);
+	temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
+			(id << CSI_ID_2_SKIP_SHIFT) |
+			(skip << CSI_SKIP_SMFC_SHIFT);
+	__raw_writel(temp, CSI_SKIP(csi));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_smfc_init
+ *	Map CSI frames to IDMAC channels.
+ *
+ * @param	channel		IDMAC channel 0-3
+ * @param	mipi_id		mipi id number 0-3
+ * @param	csi		csi0 or csi1
+ */
+void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = __raw_readl(SMFC_MAP);
+
+	switch (channel) {
+	case CSI_MEM0:
+		temp &= ~SMFC_MAP_CH0_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT;
+		break;
+	case CSI_MEM1:
+		temp &= ~SMFC_MAP_CH1_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT;
+		break;
+	case CSI_MEM2:
+		temp &= ~SMFC_MAP_CH2_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT;
+		break;
+	case CSI_MEM3:
+		temp &= ~SMFC_MAP_CH3_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT;
+		break;
+	default:
+		return;
+	}
+
+	__raw_writel(temp, SMFC_MAP);
+}
+
+/*!
+ * _ipu_smfc_set_wmc
+ *	Caution: The number of required channels,  the enabled channels
+ *	and the FIFO size per channel are configured restrictedly.
+ *
+ * @param	channel		IDMAC channel 0-3
+ * @param	set		set 1 or clear 0
+ * @param	level		water mark level when FIFO is on the
+ *				relative size
+ */
+void _ipu_smfc_set_wmc(ipu_channel_t channel, bool set, uint32_t level)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(SMFC_WMC);
+
+	switch (channel) {
+	case CSI_MEM0:
+		if (set == true) {
+			temp &= ~SMFC_WM0_SET_MASK;
+			temp |= level << SMFC_WM0_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM0_CLR_MASK;
+			temp |= level << SMFC_WM0_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM1:
+		if (set == true) {
+			temp &= ~SMFC_WM1_SET_MASK;
+			temp |= level << SMFC_WM1_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM1_CLR_MASK;
+			temp |= level << SMFC_WM1_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM2:
+		if (set == true) {
+			temp &= ~SMFC_WM2_SET_MASK;
+			temp |= level << SMFC_WM2_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM2_CLR_MASK;
+			temp |= level << SMFC_WM2_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM3:
+		if (set == true) {
+			temp &= ~SMFC_WM3_SET_MASK;
+			temp |= level << SMFC_WM3_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM3_CLR_MASK;
+			temp |= level << SMFC_WM3_CLR_SHIFT;
+		}
+		break;
+	default:
+		return;
+	}
+
+	__raw_writel(temp, SMFC_WMC);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * _ipu_smfc_set_burst_size
+ *
+ * @param	channel		IDMAC channel 0-3
+ * @param	bs		burst size of IDMAC channel,
+ *				the value programmed here shoud be BURST_SIZE-1
+ */
+void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs)
+{
+	uint32_t temp;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	temp = __raw_readl(SMFC_BS);
+
+	switch (channel) {
+	case CSI_MEM0:
+		temp &= ~SMFC_BS0_MASK;
+		temp |= bs << SMFC_BS0_SHIFT;
+		break;
+	case CSI_MEM1:
+		temp &= ~SMFC_BS1_MASK;
+		temp |= bs << SMFC_BS1_SHIFT;
+		break;
+	case CSI_MEM2:
+		temp &= ~SMFC_BS2_MASK;
+		temp |= bs << SMFC_BS2_SHIFT;
+		break;
+	case CSI_MEM3:
+		temp &= ~SMFC_BS3_MASK;
+		temp |= bs << SMFC_BS3_SHIFT;
+		break;
+	default:
+		return;
+	}
+
+	__raw_writel(temp, SMFC_BS);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+
+/*!
+ * _ipu_csi_init
+ *
+ * @param	channel      IDMAC channel
+ * @param	csi	     csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_init(ipu_channel_t channel, uint32_t csi)
+{
+	uint32_t csi_sens_conf, csi_dest;
+	int retval = 0;
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		csi_dest = CSI_DATA_DEST_IDMAC;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case CSI_PRP_VF_MEM:
+		csi_dest = CSI_DATA_DEST_IC;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	csi_sens_conf = __raw_readl(CSI_SENS_CONF(csi));
+	csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
+	__raw_writel(csi_sens_conf | (csi_dest <<
+		CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF(csi));
+err:
+	return retval;
+}
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
new file mode 100644
index 000000000000..b7a67688070b
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -0,0 +1,2595 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_common.c
+ *
+ * @brief This file contains the IPU driver common API functions.
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/clk.h>
+#include <mach/clock.h>
+#include <mach/mxc_dvfs.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+struct ipu_irq_node {
+	irqreturn_t(*handler) (int, void *);	/*!< the ISR */
+	const char *name;	/*!< device associated with the interrupt */
+	void *dev_id;		/*!< some unique information for the ISR */
+	__u32 flags;		/*!< not used */
+};
+
+/* Globals */
+struct clk *g_ipu_clk;
+bool g_ipu_clk_enabled;
+struct clk *g_di_clk[2];
+struct clk *g_pixel_clk[2];
+struct clk *g_csi_clk[2];
+unsigned char g_dc_di_assignment[10];
+ipu_channel_t g_ipu_csi_channel[2];
+int g_ipu_irq[2];
+int g_ipu_hw_rev;
+bool g_sec_chan_en[24];
+bool g_thrd_chan_en[24];
+uint32_t g_channel_init_mask;
+uint32_t g_channel_enable_mask;
+DEFINE_SPINLOCK(ipu_lock);
+struct device *g_ipu_dev;
+
+static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT];
+static const char driver_name[] = "mxc_ipu";
+
+static int ipu_dc_use_count;
+static int ipu_dp_use_count;
+static int ipu_dmfc_use_count;
+static int ipu_smfc_use_count;
+static int ipu_ic_use_count;
+static int ipu_rot_use_count;
+static int ipu_vdi_use_count;
+static int ipu_di_use_count[2];
+static int ipu_csi_use_count[2];
+/* Set to the follow using IC direct channel, default non */
+static ipu_channel_t using_ic_dirct_ch;
+
+/* for power gating */
+static uint32_t ipu_conf_reg;
+static uint32_t ic_conf_reg;
+static uint32_t ipu_cha_db_mode_reg[4];
+static uint32_t ipu_cha_cur_buf_reg[4];
+static uint32_t idma_enable_reg[2];
+static uint32_t buf_ready_reg[8];
+
+u32 *ipu_cm_reg;
+u32 *ipu_idmac_reg;
+u32 *ipu_dp_reg;
+u32 *ipu_ic_reg;
+u32 *ipu_dc_reg;
+u32 *ipu_dc_tmpl_reg;
+u32 *ipu_dmfc_reg;
+u32 *ipu_di_reg[2];
+u32 *ipu_smfc_reg;
+u32 *ipu_csi_reg[2];
+u32 *ipu_cpmem_base;
+u32 *ipu_tpmem_base;
+u32 *ipu_disp_base[2];
+u32 *ipu_vdi_reg;
+
+/* Static functions */
+static irqreturn_t ipu_irq_handler(int irq, void *desc);
+
+static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+	return ((uint32_t) ch >> (6 * type)) & 0x3F;
+};
+
+static inline int _ipu_is_ic_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
+}
+
+static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
+{
+	return (dma_chan == 14 || dma_chan == 15);
+}
+
+/* Either DP BG or DP FG can be graphic window */
+static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
+{
+	return (dma_chan == 23 || dma_chan == 27);
+}
+
+static inline int _ipu_is_irt_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 45) && (dma_chan <= 50));
+}
+
+static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 23) && (dma_chan <= 29));
+}
+
+static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 0) && (dma_chan <= 3));
+}
+
+#define idma_is_valid(ch)	(ch != NO_DMA)
+#define idma_mask(ch)		(idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
+#define idma_is_set(reg, dma)	(__raw_readl(reg(dma)) & idma_mask(dma))
+
+static void _ipu_pixel_clk_recalc(struct clk *clk)
+{
+	u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+	if (div == 0)
+		clk->rate = 0;
+	else
+		clk->rate = (clk->parent->rate * 16) / div;
+}
+
+static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div, div1;
+	u32 tmp;
+	/*
+	 * Calculate divider
+	 * Fractional part is 4 bits,
+	 * so simply multiply by 2^4 to get fractional part.
+	 */
+	tmp = (clk->parent->rate * 16);
+	div = tmp / rate;
+
+	if (div < 0x10)            /* Min DI disp clock divider is 1 */
+		div = 0x10;
+	if (div & ~0xFEF)
+		div &= 0xFF8;
+	else {
+		div1 = div & 0xFE0;
+		if ((tmp/div1 - tmp/div) < rate / 4)
+			div = div1;
+		else
+			div &= 0xFF8;
+	}
+	return (clk->parent->rate * 16) / div;
+}
+
+static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div = (clk->parent->rate * 16) / rate;
+
+	__raw_writel(div, DI_BS_CLKGEN0(clk->id));
+
+	/* Setup pixel clock timing */
+	/* FIXME: needs to be more flexible */
+	/* Down time is half of period */
+	__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
+
+	clk->rate = (clk->parent->rate * 16) / div;
+	return 0;
+}
+
+static int _ipu_pixel_clk_enable(struct clk *clk)
+{
+	u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+	disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
+	__raw_writel(disp_gen, IPU_DISP_GEN);
+
+	start_dvfs_per();
+
+	return 0;
+}
+
+static void _ipu_pixel_clk_disable(struct clk *clk)
+{
+	u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+	disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
+	__raw_writel(disp_gen, IPU_DISP_GEN);
+
+	start_dvfs_per();
+}
+
+static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
+
+	if (parent == g_ipu_clk)
+		di_gen &= ~DI_GEN_DI_CLK_EXT;
+	else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+		di_gen |= DI_GEN_DI_CLK_EXT;
+	else
+		return -EINVAL;
+
+	__raw_writel(di_gen, DI_GENERAL(clk->id));
+	_ipu_pixel_clk_recalc(clk);
+	return 0;
+}
+
+static struct clk pixel_clk[] = {
+	{
+	.name = "pixel_clk",
+	.id = 0,
+	.recalc = _ipu_pixel_clk_recalc,
+	.set_rate = _ipu_pixel_clk_set_rate,
+	.round_rate = _ipu_pixel_clk_round_rate,
+	.set_parent = _ipu_pixel_clk_set_parent,
+	.enable = _ipu_pixel_clk_enable,
+	.disable = _ipu_pixel_clk_disable,
+	},
+	{
+	.name = "pixel_clk",
+	.id = 1,
+	.recalc = _ipu_pixel_clk_recalc,
+	.set_rate = _ipu_pixel_clk_set_rate,
+	.round_rate = _ipu_pixel_clk_round_rate,
+	.set_parent = _ipu_pixel_clk_set_parent,
+	.enable = _ipu_pixel_clk_enable,
+	.disable = _ipu_pixel_clk_disable,
+	},
+};
+
+/*!
+ * This function is called by the driver framework to initialize the IPU
+ * hardware.
+ *
+ * @param	dev	The device structure for the IPU passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int ipu_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct mxc_ipu_config *plat_data = pdev->dev.platform_data;
+	unsigned long ipu_base;
+
+	spin_lock_init(&ipu_lock);
+
+	g_ipu_hw_rev = plat_data->rev;
+
+	g_ipu_dev = &pdev->dev;
+
+	/* Register IPU interrupts */
+	g_ipu_irq[0] = platform_get_irq(pdev, 0);
+	if (g_ipu_irq[0] < 0)
+		return -EINVAL;
+
+	if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, pdev->name, 0) != 0) {
+		dev_err(g_ipu_dev, "request SYNC interrupt failed\n");
+		return -EBUSY;
+	}
+	/* Some platforms have 2 IPU interrupts */
+	g_ipu_irq[1] = platform_get_irq(pdev, 1);
+	if (g_ipu_irq[1] >= 0) {
+		if (request_irq
+		    (g_ipu_irq[1], ipu_irq_handler, 0, pdev->name, 0) != 0) {
+			dev_err(g_ipu_dev, "request ERR interrupt failed\n");
+			return -EBUSY;
+		}
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res))
+		return -ENODEV;
+
+	ipu_base = res->start;
+	if (g_ipu_hw_rev == 3)	/* IPUv3M */
+		ipu_base += IPUV3M_REG_BASE;
+	else			/* IPUv3D, v3E, v3EX */
+		ipu_base += IPU_REG_BASE;
+
+	ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
+	ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
+	ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
+	/* DP Registers are accessed thru the SRM */
+	ipu_dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
+	ipu_dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
+	ipu_dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
+	ipu_di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
+	ipu_di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
+	ipu_smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
+	ipu_csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
+	ipu_csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
+	ipu_cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, PAGE_SIZE);
+	ipu_tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
+	ipu_dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
+	ipu_disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
+	ipu_vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
+
+	dev_dbg(g_ipu_dev, "IPU VDI Regs = %p\n", ipu_vdi_reg);
+	dev_dbg(g_ipu_dev, "IPU CM Regs = %p\n", ipu_cm_reg);
+	dev_dbg(g_ipu_dev, "IPU IC Regs = %p\n", ipu_ic_reg);
+	dev_dbg(g_ipu_dev, "IPU IDMAC Regs = %p\n", ipu_idmac_reg);
+	dev_dbg(g_ipu_dev, "IPU DP Regs = %p\n", ipu_dp_reg);
+	dev_dbg(g_ipu_dev, "IPU DC Regs = %p\n", ipu_dc_reg);
+	dev_dbg(g_ipu_dev, "IPU DMFC Regs = %p\n", ipu_dmfc_reg);
+	dev_dbg(g_ipu_dev, "IPU DI0 Regs = %p\n", ipu_di_reg[0]);
+	dev_dbg(g_ipu_dev, "IPU DI1 Regs = %p\n", ipu_di_reg[1]);
+	dev_dbg(g_ipu_dev, "IPU SMFC Regs = %p\n", ipu_smfc_reg);
+	dev_dbg(g_ipu_dev, "IPU CSI0 Regs = %p\n", ipu_csi_reg[0]);
+	dev_dbg(g_ipu_dev, "IPU CSI1 Regs = %p\n", ipu_csi_reg[1]);
+	dev_dbg(g_ipu_dev, "IPU CPMem = %p\n", ipu_cpmem_base);
+	dev_dbg(g_ipu_dev, "IPU TPMem = %p\n", ipu_tpmem_base);
+	dev_dbg(g_ipu_dev, "IPU DC Template Mem = %p\n", ipu_dc_tmpl_reg);
+	dev_dbg(g_ipu_dev, "IPU Display Region 1 Mem = %p\n", ipu_disp_base[1]);
+
+	g_pixel_clk[0] = &pixel_clk[0];
+	clk_register(g_pixel_clk[0]);
+	g_pixel_clk[1] = &pixel_clk[1];
+	clk_register(g_pixel_clk[1]);
+
+	/* Enable IPU and CSI clocks */
+	/* Get IPU clock freq */
+	g_ipu_clk = clk_get(&pdev->dev, "ipu_clk");
+	dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk));
+
+	if (plat_data->reset)
+		plat_data->reset();
+
+	clk_set_parent(g_pixel_clk[0], g_ipu_clk);
+	clk_set_parent(g_pixel_clk[1], g_ipu_clk);
+	clk_enable(g_ipu_clk);
+
+	g_di_clk[0] = plat_data->di_clk[0];
+	g_di_clk[1] = plat_data->di_clk[1];
+
+	g_csi_clk[0] = clk_get(&pdev->dev, "csi_mclk1");
+	g_csi_clk[1] = clk_get(&pdev->dev, "csi_mclk2");
+
+	__raw_writel(0x807FFFFF, IPU_MEM_RST);
+	while (__raw_readl(IPU_MEM_RST) & 0x80000000) ;
+
+	_ipu_init_dc_mappings();
+
+	/* Enable error interrupts by default */
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
+
+	/* DMFC Init */
+	_ipu_dmfc_init(DMFC_NORMAL, 1);
+
+	/* Set sync refresh channels and CSI->mem channel as high priority */
+	__raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
+
+	/* Set MCU_T to divide MCU access window into 2 */
+	__raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
+
+	clk_disable(g_ipu_clk);
+
+	register_ipu_device();
+
+	return 0;
+}
+
+int ipu_remove(struct platform_device *pdev)
+{
+	if (g_ipu_irq[0])
+		free_irq(g_ipu_irq[0], 0);
+	if (g_ipu_irq[1])
+		free_irq(g_ipu_irq[1], 0);
+
+	clk_put(g_ipu_clk);
+
+	iounmap(ipu_cm_reg);
+	iounmap(ipu_ic_reg);
+	iounmap(ipu_idmac_reg);
+	iounmap(ipu_dc_reg);
+	iounmap(ipu_dp_reg);
+	iounmap(ipu_dmfc_reg);
+	iounmap(ipu_di_reg[0]);
+	iounmap(ipu_di_reg[1]);
+	iounmap(ipu_smfc_reg);
+	iounmap(ipu_csi_reg[0]);
+	iounmap(ipu_csi_reg[1]);
+	iounmap(ipu_cpmem_base);
+	iounmap(ipu_tpmem_base);
+	iounmap(ipu_dc_tmpl_reg);
+	iounmap(ipu_disp_base[1]);
+	iounmap(ipu_vdi_reg);
+
+	return 0;
+}
+
+void ipu_dump_registers(void)
+{
+	printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
+	printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
+	printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_EN(0)));
+	printk(KERN_DEBUG "IDMAC_CHA_EN2 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_EN(32)));
+	printk(KERN_DEBUG "IDMAC_CHA_PRI1 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_PRI(0)));
+	printk(KERN_DEBUG "IDMAC_CHA_PRI2 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_PRI(32)));
+	printk(KERN_DEBUG "IDMAC_BAND_EN1 = \t0x%08X\n",
+	       __raw_readl(IDMAC_BAND_EN(0)));
+	printk(KERN_DEBUG "IDMAC_BAND_EN2 = \t0x%08X\n",
+	       __raw_readl(IDMAC_BAND_EN(32)));
+	printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+	       __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
+	printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+	       __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
+	printk(KERN_DEBUG "DMFC_WR_CHAN = \t0x%08X\n",
+	       __raw_readl(DMFC_WR_CHAN));
+	printk(KERN_DEBUG "DMFC_WR_CHAN_DEF = \t0x%08X\n",
+	       __raw_readl(DMFC_WR_CHAN_DEF));
+	printk(KERN_DEBUG "DMFC_DP_CHAN = \t0x%08X\n",
+	       __raw_readl(DMFC_DP_CHAN));
+	printk(KERN_DEBUG "DMFC_DP_CHAN_DEF = \t0x%08X\n",
+	       __raw_readl(DMFC_DP_CHAN_DEF));
+	printk(KERN_DEBUG "DMFC_IC_CTRL = \t0x%08X\n",
+	       __raw_readl(DMFC_IC_CTRL));
+	printk(KERN_DEBUG "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW1));
+	printk(KERN_DEBUG "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW2));
+	printk(KERN_DEBUG "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW3));
+	printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_DISP_FLOW1));
+}
+
+/*!
+ * This function is called to initialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to init.
+ *
+ * @param       params  Input parameter containing union of channel
+ *                      initialization parameters.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
+{
+	int ret = 0;
+	uint32_t ipu_conf;
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel));
+
+	/* re-enable error interrupts every time a channel is initialized */
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
+	__raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
+
+	if (g_ipu_clk_enabled == false) {
+		stop_dvfs_per();
+		g_ipu_clk_enabled = true;
+		clk_enable(g_ipu_clk);
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+		dev_err(g_ipu_dev, "Warning: channel already initialized %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	ipu_conf = __raw_readl(IPU_CONF);
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		if (params->csi_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		ipu_smfc_use_count++;
+		g_ipu_csi_channel[params->csi_mem.csi] = channel;
+
+		/*SMFC setting*/
+		if (params->csi_mem.mipi_en) {
+			ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+				params->csi_mem.csi));
+			_ipu_smfc_init(channel, params->csi_mem.mipi_id,
+				params->csi_mem.csi);
+		} else {
+			ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+				params->csi_mem.csi));
+			_ipu_smfc_init(channel, 0, params->csi_mem.csi);
+		}
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(channel, params->csi_mem.csi);
+		break;
+	case CSI_PRP_ENC_MEM:
+		if (params->csi_prp_enc_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+		if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
+			ret = -EINVAL;
+			goto err;
+		}
+		using_ic_dirct_ch = CSI_PRP_ENC_MEM;
+
+		ipu_ic_use_count++;
+		g_ipu_csi_channel[params->csi_prp_enc_mem.csi] = channel;
+
+		/*Without SMFC, CSI only support parallel data source*/
+		ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+			params->csi_prp_enc_mem.csi));
+
+		/*CSI0/1 feed into IC*/
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+		if (params->csi_prp_enc_mem.csi)
+			ipu_conf |= IPU_CONF_CSI_SEL;
+		else
+			ipu_conf &= ~IPU_CONF_CSI_SEL;
+
+		/*PRP skip buffer in memory, only valid when RWS_EN is true*/
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(channel, params->csi_prp_enc_mem.csi);
+		_ipu_ic_init_prpenc(params, true);
+		break;
+	case CSI_PRP_VF_MEM:
+		if (params->csi_prp_vf_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+		if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
+			ret = -EINVAL;
+			goto err;
+		}
+		using_ic_dirct_ch = CSI_PRP_VF_MEM;
+
+		ipu_ic_use_count++;
+		g_ipu_csi_channel[params->csi_prp_vf_mem.csi] = channel;
+
+		/*Without SMFC, CSI only support parallel data source*/
+		ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+			params->csi_prp_vf_mem.csi));
+
+		/*CSI0/1 feed into IC*/
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+		if (params->csi_prp_vf_mem.csi)
+			ipu_conf |= IPU_CONF_CSI_SEL;
+		else
+			ipu_conf &= ~IPU_CONF_CSI_SEL;
+
+		/*PRP skip buffer in memory, only valid when RWS_EN is true*/
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(channel, params->csi_prp_vf_mem.csi);
+		_ipu_ic_init_prpvf(params, true);
+		break;
+	case MEM_PRP_VF_MEM:
+		ipu_ic_use_count++;
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		if (params->mem_prp_vf_mem.alpha_chan_en)
+			g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_prpvf(params, false);
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		if ((using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
+		     (using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
+			ret = -EINVAL;
+			goto err;
+		}
+		using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
+		ipu_ic_use_count++;
+		ipu_vdi_use_count++;
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		reg &= ~FS_VDI_SRC_SEL_MASK;
+		__raw_writel(reg , IPU_FS_PROC_FLOW1);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		_ipu_ic_init_prpvf(params, false);
+		_ipu_vdi_init(channel, params);
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+		_ipu_vdi_init(channel, params);
+		break;
+	case MEM_VDI_PRP_VF_MEM_N:
+		_ipu_vdi_init(channel, params);
+		break;
+	case MEM_ROT_VF_MEM:
+		ipu_ic_use_count++;
+		ipu_rot_use_count++;
+		_ipu_ic_init_rotate_vf(params);
+		break;
+	case MEM_PRP_ENC_MEM:
+		ipu_ic_use_count++;
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+		_ipu_ic_init_prpenc(params, false);
+		break;
+	case MEM_ROT_ENC_MEM:
+		ipu_ic_use_count++;
+		ipu_rot_use_count++;
+		_ipu_ic_init_rotate_enc(params);
+		break;
+	case MEM_PP_MEM:
+		if (params->mem_pp_mem.graphics_combine_en)
+			g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		if (params->mem_pp_mem.alpha_chan_en)
+			g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+		_ipu_ic_init_pp(params);
+		ipu_ic_use_count++;
+		break;
+	case MEM_ROT_PP_MEM:
+		_ipu_ic_init_rotate_pp(params);
+		ipu_ic_use_count++;
+		ipu_rot_use_count++;
+		break;
+	case MEM_DC_SYNC:
+		if (params->mem_dc_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		g_dc_di_assignment[1] = params->mem_dc_sync.di;
+		_ipu_dc_init(1, params->mem_dc_sync.di,
+			     params->mem_dc_sync.interlaced,
+			     params->mem_dc_sync.out_pixel_fmt);
+		ipu_di_use_count[params->mem_dc_sync.di]++;
+		ipu_dc_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	case MEM_BG_SYNC:
+		if (params->mem_dp_bg_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		if (params->mem_dp_bg_sync.alpha_chan_en)
+			g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
+		_ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
+		_ipu_dc_init(5, params->mem_dp_bg_sync.di,
+			     params->mem_dp_bg_sync.interlaced,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
+		ipu_di_use_count[params->mem_dp_bg_sync.di]++;
+		ipu_dc_use_count++;
+		ipu_dp_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	case MEM_FG_SYNC:
+		_ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
+			     params->mem_dp_fg_sync.out_pixel_fmt);
+
+		if (params->mem_dp_fg_sync.alpha_chan_en)
+			g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		ipu_dc_use_count++;
+		ipu_dp_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	case DIRECT_ASYNC0:
+		if (params->direct_async.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		g_dc_di_assignment[8] = params->direct_async.di;
+		_ipu_dc_init(8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
+		ipu_di_use_count[params->direct_async.di]++;
+		ipu_dc_use_count++;
+		break;
+	case DIRECT_ASYNC1:
+		if (params->direct_async.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		g_dc_di_assignment[9] = params->direct_async.di;
+		_ipu_dc_init(9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
+		ipu_di_use_count[params->direct_async.di]++;
+		ipu_dc_use_count++;
+		break;
+	default:
+		dev_err(g_ipu_dev, "Missing channel initialization\n");
+		break;
+	}
+
+	/* Enable IPU sub module */
+	g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+
+	__raw_writel(ipu_conf, IPU_CONF);
+
+err:
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_init_channel);
+
+/*!
+ * This function is called to uninitialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to uninit.
+ */
+void ipu_uninit_channel(ipu_channel_t channel)
+{
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t in_dma, out_dma = 0;
+	uint32_t ipu_conf;
+
+	if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		dev_err(g_ipu_dev, "Channel already uninitialized %d\n",
+			IPU_CHAN_ID(channel));
+		return;
+	}
+
+	/* Make sure channel is disabled */
+	/* Get input and output dma channels */
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+
+	if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
+	    idma_is_set(IDMAC_CHA_EN, out_dma)) {
+		dev_err(g_ipu_dev,
+			"Channel %d is not disabled, disable first\n",
+			IPU_CHAN_ID(channel));
+		return;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	ipu_conf = __raw_readl(IPU_CONF);
+
+	/* Reset the double buffer */
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
+	__raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
+	__raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
+
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
+		g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
+		g_thrd_chan_en[IPU_CHAN_ID(channel)] = false;
+	}
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		ipu_smfc_use_count--;
+		if (g_ipu_csi_channel[0] == channel) {
+			g_ipu_csi_channel[0] = CHAN_NONE;
+		} else if (g_ipu_csi_channel[1] == channel) {
+			g_ipu_csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case CSI_PRP_ENC_MEM:
+		ipu_ic_use_count--;
+		if (using_ic_dirct_ch == CSI_PRP_ENC_MEM)
+			using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpenc();
+		if (g_ipu_csi_channel[0] == channel) {
+			g_ipu_csi_channel[0] = CHAN_NONE;
+		} else if (g_ipu_csi_channel[1] == channel) {
+			g_ipu_csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case CSI_PRP_VF_MEM:
+		ipu_ic_use_count--;
+		if (using_ic_dirct_ch == CSI_PRP_VF_MEM)
+			using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpvf();
+		if (g_ipu_csi_channel[0] == channel) {
+			g_ipu_csi_channel[0] = CHAN_NONE;
+		} else if (g_ipu_csi_channel[1] == channel) {
+			g_ipu_csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case MEM_PRP_VF_MEM:
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_prpvf();
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ipu_ic_use_count--;
+		ipu_vdi_use_count--;
+		if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
+			using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpvf();
+		_ipu_vdi_uninit();
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+	case MEM_VDI_PRP_VF_MEM_N:
+		break;
+	case MEM_ROT_VF_MEM:
+		ipu_rot_use_count--;
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_rotate_vf();
+		break;
+	case MEM_PRP_ENC_MEM:
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_prpenc();
+		reg = __raw_readl(IPU_FS_PROC_FLOW1);
+		__raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_ROT_ENC_MEM:
+		ipu_rot_use_count--;
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_rotate_enc();
+		break;
+	case MEM_PP_MEM:
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_pp();
+		break;
+	case MEM_ROT_PP_MEM:
+		ipu_rot_use_count--;
+		ipu_ic_use_count--;
+		_ipu_ic_uninit_rotate_pp();
+		break;
+	case MEM_DC_SYNC:
+		_ipu_dc_uninit(1);
+		ipu_di_use_count[g_dc_di_assignment[1]]--;
+		ipu_dc_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	case MEM_BG_SYNC:
+		_ipu_dp_uninit(channel);
+		_ipu_dc_uninit(5);
+		ipu_di_use_count[g_dc_di_assignment[5]]--;
+		ipu_dc_use_count--;
+		ipu_dp_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	case MEM_FG_SYNC:
+		_ipu_dp_uninit(channel);
+		ipu_dc_use_count--;
+		ipu_dp_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	case DIRECT_ASYNC0:
+		_ipu_dc_uninit(8);
+		ipu_di_use_count[g_dc_di_assignment[8]]--;
+		ipu_dc_use_count--;
+		break;
+	case DIRECT_ASYNC1:
+		_ipu_dc_uninit(9);
+		ipu_di_use_count[g_dc_di_assignment[9]]--;
+		ipu_dc_use_count--;
+		break;
+	default:
+		break;
+	}
+
+	g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	if (ipu_ic_use_count == 0)
+		ipu_conf &= ~IPU_CONF_IC_EN;
+	if (ipu_vdi_use_count == 0) {
+		ipu_conf &= ~IPU_CONF_ISP_EN;
+		ipu_conf &= ~IPU_CONF_VDI_EN;
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+	}
+	if (ipu_rot_use_count == 0)
+		ipu_conf &= ~IPU_CONF_ROT_EN;
+	if (ipu_dc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DC_EN;
+	if (ipu_dp_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DP_EN;
+	if (ipu_dmfc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DMFC_EN;
+	if (ipu_di_use_count[0] == 0) {
+		ipu_conf &= ~IPU_CONF_DI0_EN;
+	}
+	if (ipu_di_use_count[1] == 0) {
+		ipu_conf &= ~IPU_CONF_DI1_EN;
+	}
+	if (ipu_smfc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_SMFC_EN;
+
+	__raw_writel(ipu_conf, IPU_CONF);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	if (ipu_conf == 0) {
+		clk_disable(g_ipu_clk);
+		g_ipu_clk_enabled = false;
+	}
+
+	WARN_ON(ipu_ic_use_count < 0);
+	WARN_ON(ipu_vdi_use_count < 0);
+	WARN_ON(ipu_rot_use_count < 0);
+	WARN_ON(ipu_dc_use_count < 0);
+	WARN_ON(ipu_dp_use_count < 0);
+	WARN_ON(ipu_dmfc_use_count < 0);
+	WARN_ON(ipu_smfc_use_count < 0);
+}
+EXPORT_SYMBOL(ipu_uninit_channel);
+
+/*!
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       rot_mode        Input parameter for rotation setting of buffer.
+ *                              A rotation setting other than
+ *                              IPU_ROTATE_VERT_FLIP
+ *                              should only be used for input buffers of
+ *                              rotation channels.
+ *
+ * @param       phyaddr_0       Input parameter buffer 0 physical address.
+ *
+ * @param       phyaddr_1       Input parameter buffer 1 physical address.
+ *                              Setting this to a value other than NULL enables
+ *                              double buffering mode.
+ *
+ * @param       u		private u offset for additional cropping,
+ *				zero if not used.
+ *
+ * @param       v		private v offset for additional cropping,
+ *				zero if not used.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				ipu_rotate_mode_t rot_mode,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				uint32_t u, uint32_t v)
+{
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t dma_chan;
+	uint32_t burst_size;
+
+	dma_chan = channel_2_dma(channel, type);
+	if (!idma_is_valid(dma_chan))
+		return -EINVAL;
+
+	if (stride < width * bytes_per_pixel(pixel_fmt))
+		stride = width * bytes_per_pixel(pixel_fmt);
+
+	if (stride % 4) {
+		dev_err(g_ipu_dev,
+			"Stride not 32-bit aligned, stride = %d\n", stride);
+		return -EINVAL;
+	}
+	/* IC & IRT channels' width must be multiple of 8 pixels */
+	if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
+		&& (width % 8)) {
+		dev_err(g_ipu_dev, "Width must be 8 pixel multiple\n");
+		return -EINVAL;
+	}
+
+	/* Build parameter memory data for DMA channel */
+	_ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
+			   phyaddr_0, phyaddr_1);
+
+	/* Set correlative channel parameter of local alpha channel */
+	if ((_ipu_is_ic_graphic_chan(dma_chan) ||
+	     _ipu_is_dp_graphic_chan(dma_chan)) &&
+	    (g_thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
+		_ipu_ch_param_set_alpha_use_separate_channel(dma_chan, true);
+		_ipu_ch_param_set_alpha_buffer_memory(dma_chan);
+		_ipu_ch_param_set_alpha_condition_read(dma_chan);
+		/* fix alpha width as 8 and burst size as 16*/
+		_ipu_ch_params_set_alpha_width(dma_chan, 8);
+		_ipu_ch_param_set_burst_size(dma_chan, 16);
+	} else if (_ipu_is_ic_graphic_chan(dma_chan) &&
+		   ipu_pixel_format_has_alpha(pixel_fmt))
+		_ipu_ch_param_set_alpha_use_separate_channel(dma_chan, false);
+
+	if (rot_mode)
+		_ipu_ch_param_set_rotation(dma_chan, rot_mode);
+
+	/* IC and ROT channels have restriction of 8 or 16 pix burst length */
+	if (_ipu_is_ic_chan(dma_chan)) {
+		if ((width % 16) == 0)
+			_ipu_ch_param_set_burst_size(dma_chan, 16);
+		else
+			_ipu_ch_param_set_burst_size(dma_chan, 8);
+	} else if (_ipu_is_irt_chan(dma_chan)) {
+		_ipu_ch_param_set_burst_size(dma_chan, 8);
+		_ipu_ch_param_set_block_mode(dma_chan);
+	} else if (_ipu_is_dmfc_chan(dma_chan)) {
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+		_ipu_dmfc_set_wait4eot(dma_chan, width);
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	}
+
+	if (_ipu_chan_is_interlaced(channel)) {
+		_ipu_ch_param_set_interlaced_scan(dma_chan);
+	}
+
+	if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
+		burst_size = _ipu_ch_param_get_burst_size(dma_chan);
+		_ipu_ic_idma_init(dma_chan, width, height, burst_size,
+			rot_mode);
+	} else if (_ipu_is_smfc_chan(dma_chan)) {
+		burst_size = _ipu_ch_param_get_burst_size(dma_chan);
+		if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
+			((_ipu_ch_param_get_bpp(dma_chan) == 5) ||
+			(_ipu_ch_param_get_bpp(dma_chan) == 3)))
+			burst_size = burst_size >> 4;
+		else
+			burst_size = burst_size >> 2;
+		_ipu_smfc_set_burst_size(channel, burst_size-1);
+	}
+
+	if (idma_is_set(IDMAC_CHA_PRI, dma_chan) && !cpu_is_mx53())
+		_ipu_ch_param_set_high_priority(dma_chan);
+
+	_ipu_ch_param_dump(dma_chan);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
+	if (phyaddr_1)
+		reg |= idma_mask(dma_chan);
+	else
+		reg &= ~idma_mask(dma_chan);
+	__raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+	/* Reset to buffer 0 */
+	__raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_channel_buffer);
+
+/*!
+ * This function is called to update the physical address of a buffer for
+ * a logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for buffer number to update.
+ *                              0 or 1 are the only valid values.
+ *
+ * @param       phyaddr         Input parameter buffer physical address.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail. This function will fail if the buffer is set to ready.
+ */
+int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				  uint32_t bufNum, dma_addr_t phyaddr)
+{
+	uint32_t reg;
+	int ret = 0;
+	unsigned long lock_flags;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (bufNum == 0)
+		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+	else
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
+
+	if ((reg & idma_mask(dma_chan)) == 0)
+		_ipu_ch_param_set_buffer(dma_chan, bufNum, phyaddr);
+	else
+		ret = -EACCES;
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_update_channel_buffer);
+
+
+/*!
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       u		predefined private u offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param       v		predefined private v offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param			vertical_offset vertical offset for Y coordinate
+ * 								in the existed frame
+ *
+ *
+ * @param			horizontal_offset horizontal offset for X coordinate
+ * 								in the existed frame
+ *
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ *              This function will fail if any buffer is set to ready.
+ */
+
+int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				uint32_t u, uint32_t v,
+				uint32_t vertical_offset, uint32_t horizontal_offset)
+{
+	int ret = 0;
+	unsigned long lock_flags;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if ((__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
+		(__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)))
+		ret = -EACCES;
+	else
+		_ipu_ch_offset_update(dma_chan, pixel_fmt, width, height, stride,
+				      u, v, 0, vertical_offset, horizontal_offset);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_update_channel_offset);
+
+
+/*!
+ * This function is called to set a channel's buffer as ready.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for which buffer number set to
+ *                              ready state.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
+			  uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0) {
+		/*Mark buffer 0 as ready. */
+		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+		__raw_writel(idma_mask(dma_chan) | reg,
+			     IPU_CHA_BUF0_RDY(dma_chan));
+	} else {
+		/*Mark buffer 1 as ready. */
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
+		__raw_writel(idma_mask(dma_chan) | reg,
+			     IPU_CHA_BUF1_RDY(dma_chan));
+	}
+	return 0;
+}
+EXPORT_SYMBOL(ipu_select_buffer);
+
+/*!
+ * This function is called to set a channel's buffer as ready.
+ *
+ * @param       bufNum          Input parameter for which buffer number set to
+ *                              ready state.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum)
+{
+
+	uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
+	uint32_t mask_bit =
+		idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
+		idma_mask(dma_chan)|
+		idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
+	uint32_t reg;
+
+	if (bufNum == 0) {
+		/*Mark buffer 0 as ready. */
+		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+		__raw_writel(mask_bit | reg, IPU_CHA_BUF0_RDY(dma_chan));
+	} else {
+		/*Mark buffer 1 as ready. */
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
+		__raw_writel(mask_bit | reg, IPU_CHA_BUF1_RDY(dma_chan));
+	}
+	return 0;
+}
+EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
+
+#define NA	-1
+static int proc_dest_sel[] =
+  { 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
+    0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
+static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
+  NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
+static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
+  NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
+
+
+/*!
+ * This function links 2 channels together for automatic frame
+ * synchronization. The output of the source channel is linked to the input of
+ * the destination channel.
+ *
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	int retval = 0;
+	unsigned long lock_flags;
+	uint32_t fs_proc_flow1;
+	uint32_t fs_proc_flow2;
+	uint32_t fs_proc_flow3;
+	uint32_t fs_disp_flow1;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
+	fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
+	fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
+	fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
+
+	switch (src_ch) {
+	case CSI_MEM0:
+		fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC0_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM1:
+		fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC1_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM2:
+		fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC2_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM3:
+		fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC3_DEST_SEL_OFFSET;
+		break;
+	case CSI_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_PRPENC_DEST_SEL_OFFSET;
+		break;
+	case CSI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PP_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PP_ROT_DEST_SEL_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPENC_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPENC_ROT_DEST_SEL_OFFSET;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_ROT_DEST_SEL_OFFSET;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	switch (dest_ch) {
+	case MEM_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PP_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PRPENC_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PRPVF_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_DC_SYNC:
+		fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
+		break;
+	case MEM_BG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_SYNC0_SRC_SEL_OFFSET;
+		break;
+	case MEM_FG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_SYNC1_SRC_SEL_OFFSET;
+		break;
+	case MEM_DC_ASYNC:
+		fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
+		break;
+	case MEM_BG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_ASYNC0_SRC_SEL_OFFSET;
+		break;
+	case MEM_FG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_ASYNC1_SRC_SEL_OFFSET;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	__raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
+	__raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
+	__raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
+	__raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
+
+err:
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_link_channels);
+
+/*!
+ * This function unlinks 2 channels and disables automatic frame
+ * synchronization.
+ *
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	int retval = 0;
+	unsigned long lock_flags;
+	uint32_t fs_proc_flow1;
+	uint32_t fs_proc_flow2;
+	uint32_t fs_proc_flow3;
+	uint32_t fs_disp_flow1;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
+	fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
+	fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
+	fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
+
+	switch (src_ch) {
+	case CSI_MEM0:
+		fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
+		break;
+	case CSI_MEM1:
+		fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
+		break;
+	case CSI_MEM2:
+		fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
+		break;
+	case CSI_MEM3:
+		fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
+		break;
+	case CSI_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		break;
+	case CSI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	switch (dest_ch) {
+	case MEM_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_DC_SYNC:
+		fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
+		break;
+	case MEM_BG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
+		break;
+	case MEM_FG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
+		break;
+	case MEM_DC_ASYNC:
+		fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
+		break;
+	case MEM_BG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
+		break;
+	case MEM_FG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	__raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
+	__raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
+	__raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
+	__raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
+
+err:
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_unlink_channels);
+
+/*!
+ * This function check whether a logical channel was enabled.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 1 while request channel is enabled or
+ *              0 for not enabled.
+ */
+int32_t ipu_is_channel_busy(ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+	if (reg & idma_mask(in_dma))
+		return 1;
+	reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+	if (reg & idma_mask(out_dma))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(ipu_is_channel_busy);
+
+/*!
+ * This function enables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_channel(ipu_channel_t channel)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+	uint32_t ipu_conf;
+	uint32_t in_dma;
+	uint32_t out_dma;
+	uint32_t sec_dma;
+	uint32_t thrd_dma;
+
+	if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
+		dev_err(g_ipu_dev, "Warning: channel already enabled %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	ipu_conf = __raw_readl(IPU_CONF);
+	if (ipu_di_use_count[0] > 0) {
+		ipu_conf |= IPU_CONF_DI0_EN;
+	}
+	if (ipu_di_use_count[1] > 0) {
+		ipu_conf |= IPU_CONF_DI1_EN;
+	}
+	if (ipu_dp_use_count > 0)
+		ipu_conf |= IPU_CONF_DP_EN;
+	if (ipu_dc_use_count > 0)
+		ipu_conf |= IPU_CONF_DC_EN;
+	if (ipu_dmfc_use_count > 0)
+		ipu_conf |= IPU_CONF_DMFC_EN;
+	if (ipu_ic_use_count > 0)
+		ipu_conf |= IPU_CONF_IC_EN;
+	if (ipu_vdi_use_count > 0) {
+		ipu_conf |= IPU_CONF_ISP_EN;
+		ipu_conf |= IPU_CONF_VDI_EN;
+		ipu_conf |= IPU_CONF_IC_INPUT;
+	}
+	if (ipu_rot_use_count > 0)
+		ipu_conf |= IPU_CONF_ROT_EN;
+	if (ipu_smfc_use_count > 0)
+		ipu_conf |= IPU_CONF_SMFC_EN;
+	__raw_writel(ipu_conf, IPU_CONF);
+
+	if (idma_is_valid(in_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+		__raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+		__raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+	}
+
+	if ((g_sec_chan_en[IPU_CHAN_ID(channel)]) &&
+		((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
+		 (channel == MEM_VDI_PRP_VF_MEM))) {
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
+		__raw_writel(reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
+	}
+	if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
+		((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+		reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
+		__raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		reg = __raw_readl(IDMAC_SEP_ALPHA);
+		__raw_writel(reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
+	} else if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
+		   ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+		reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
+		__raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+		reg = __raw_readl(IDMAC_SEP_ALPHA);
+		__raw_writel(reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
+	}
+
+	if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
+	    (channel == MEM_FG_SYNC)) {
+		reg = __raw_readl(IDMAC_WM_EN(in_dma));
+		__raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+
+		_ipu_dp_dc_enable(channel);
+	}
+
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
+		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
+		_ipu_ic_enable_task(channel);
+
+	g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_enable_channel);
+
+/*!
+ * This function check buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+int32_t ipu_check_buffer_busy(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0)
+		reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
+	else
+		reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
+
+	if (reg & idma_mask(dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_check_buffer_busy);
+
+/*!
+ * This function clear buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	unsigned long lock_flags;
+	uint32_t dma_ch = channel_2_dma(channel, type);
+
+	if (!idma_is_valid(dma_ch))
+		return;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	__raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
+	if (bufNum == 0) {
+		if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
+			__raw_writel(idma_mask(dma_ch),
+					IPU_CHA_BUF0_RDY(dma_ch));
+		}
+	} else {
+		if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
+			__raw_writel(idma_mask(dma_ch),
+					IPU_CHA_BUF1_RDY(dma_ch));
+		}
+	}
+	__raw_writel(0x0, IPU_GPR); /* write one to set */
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_clear_buffer_ready);
+
+static irqreturn_t disable_chan_irq_handler(int irq, void *dev_id)
+{
+	struct completion *comp = dev_id;
+
+	complete(comp);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function disables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       wait_for_stop   Flag to set whether to wait for channel end
+ *                              of frame or return immediately.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+	uint32_t in_dma;
+	uint32_t out_dma;
+	uint32_t sec_dma = NO_DMA;
+	uint32_t thrd_dma = NO_DMA;
+
+	if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		dev_err(g_ipu_dev, "Channel already disabled %d\n",
+			IPU_CHAN_ID(channel));
+		return 0;
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	if ((idma_is_valid(in_dma) &&
+		!idma_is_set(IDMAC_CHA_EN, in_dma))
+		&& (idma_is_valid(out_dma) &&
+		!idma_is_set(IDMAC_CHA_EN, out_dma)))
+		return -EINVAL;
+
+	if (g_sec_chan_en[IPU_CHAN_ID(channel)])
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+	if (g_thrd_chan_en[IPU_CHAN_ID(channel)]) {
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+	}
+
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		int timeout = 50;
+		int irq;
+
+		_ipu_dp_dc_disable(channel, false);
+
+		/*
+		 * wait for display channel EOF then disable IDMAC,
+		 * it avoid NFB4EOF error.
+		 */
+		if (channel == MEM_BG_SYNC)
+			irq = IPU_IRQ_BG_SYNC_EOF;
+		if (channel == MEM_FG_SYNC)
+			irq = IPU_IRQ_FG_SYNC_EOF;
+		else
+			irq = IPU_IRQ_DC_SYNC_EOF;
+		__raw_writel(IPUIRQ_2_MASK(irq),
+			     IPUIRQ_2_STATREG(irq));
+		while ((__raw_readl(IPUIRQ_2_STATREG(irq)) &
+			IPUIRQ_2_MASK(irq)) == 0) {
+			msleep(10);
+			timeout -= 10;
+			if (timeout <= 0)
+				break;
+		}
+	} else if (wait_for_stop) {
+		while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
+		       idma_is_set(IDMAC_CHA_BUSY, out_dma) ||
+			(g_sec_chan_en[IPU_CHAN_ID(channel)] &&
+			idma_is_set(IDMAC_CHA_BUSY, sec_dma)) ||
+			(g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
+			idma_is_set(IDMAC_CHA_BUSY, thrd_dma))) {
+			uint32_t ret, irq = 0xffffffff;
+			DECLARE_COMPLETION_ONSTACK(disable_comp);
+
+			if (idma_is_set(IDMAC_CHA_BUSY, out_dma))
+				irq = out_dma;
+			if (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
+				idma_is_set(IDMAC_CHA_BUSY, sec_dma))
+				irq = sec_dma;
+			if (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
+				idma_is_set(IDMAC_CHA_BUSY, thrd_dma))
+				irq = thrd_dma;
+			if (idma_is_set(IDMAC_CHA_BUSY, in_dma))
+				irq = in_dma;
+
+			if (irq == 0xffffffff) {
+				dev_err(g_ipu_dev, "warning: no channel busy, break\n");
+				break;
+			}
+			ret = ipu_request_irq(irq, disable_chan_irq_handler, 0, NULL, &disable_comp);
+			if (ret < 0) {
+				dev_err(g_ipu_dev, "irq %d in use\n", irq);
+				break;
+			} else {
+				ret = wait_for_completion_timeout(&disable_comp, msecs_to_jiffies(200));
+				ipu_free_irq(irq, &disable_comp);
+				if (ret == 0) {
+					ipu_dump_registers();
+					dev_err(g_ipu_dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
+					break;
+				}
+			}
+		}
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		reg = __raw_readl(IDMAC_WM_EN(in_dma));
+		__raw_writel(reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+	}
+
+	/* Disable IC task */
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
+		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
+		_ipu_ic_disable_task(channel);
+
+	/* Disable DMA channel(s) */
+	if (idma_is_valid(in_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+		__raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+		__raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+		__raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+		__raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
+	}
+	if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
+		__raw_writel(reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
+		__raw_writel(idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
+	}
+	if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
+		__raw_writel(reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+		if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
+			reg = __raw_readl(IDMAC_SEP_ALPHA);
+			__raw_writel(reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
+		} else {
+			reg = __raw_readl(IDMAC_SEP_ALPHA);
+			__raw_writel(reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
+		}
+		__raw_writel(idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
+	}
+
+	g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	/* Set channel buffers NOT to be ready */
+	if (idma_is_valid(in_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
+	}
+	if (idma_is_valid(out_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
+	}
+	if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 1);
+	}
+	if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 1);
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disable_channel);
+
+/*!
+ * This function enables CSI.
+ *
+ * @param       csi	csi num 0 or 1
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_csi(uint32_t csi)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	if (csi > 1) {
+		dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	ipu_csi_use_count[csi]++;
+
+	if (ipu_csi_use_count[csi] == 1) {
+		reg = __raw_readl(IPU_CONF);
+		if (csi == 0)
+			__raw_writel(reg | IPU_CONF_CSI0_EN, IPU_CONF);
+		else
+			__raw_writel(reg | IPU_CONF_CSI1_EN, IPU_CONF);
+	}
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_enable_csi);
+
+/*!
+ * This function disables CSI.
+ *
+ * @param       csi	csi num 0 or 1
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_csi(uint32_t csi)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	if (csi > 1) {
+		dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+	ipu_csi_use_count[csi]--;
+
+	if (ipu_csi_use_count[csi] == 0) {
+		reg = __raw_readl(IPU_CONF);
+		if (csi == 0)
+			__raw_writel(reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
+		else
+			__raw_writel(reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
+	}
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disable_csi);
+
+static irqreturn_t ipu_irq_handler(int irq, void *desc)
+{
+	int i;
+	uint32_t line;
+	irqreturn_t result = IRQ_NONE;
+	uint32_t int_stat;
+	const int err_reg[] = { 5, 6, 9, 10, 0 };
+	const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
+
+	for (i = 0;; i++) {
+		if (err_reg[i] == 0)
+			break;
+		int_stat = __raw_readl(IPU_INT_STAT(err_reg[i]));
+		int_stat &= __raw_readl(IPU_INT_CTRL(err_reg[i]));
+		if (int_stat) {
+			__raw_writel(int_stat, IPU_INT_STAT(err_reg[i]));
+			dev_err(g_ipu_dev,
+				"IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
+				err_reg[i], int_stat);
+			/* Disable interrupts so we only get error once */
+			int_stat =
+			    __raw_readl(IPU_INT_CTRL(err_reg[i])) & ~int_stat;
+			__raw_writel(int_stat, IPU_INT_CTRL(err_reg[i]));
+		}
+	}
+
+	for (i = 0;; i++) {
+		if (int_reg[i] == 0)
+			break;
+		int_stat = __raw_readl(IPU_INT_STAT(int_reg[i]));
+		int_stat &= __raw_readl(IPU_INT_CTRL(int_reg[i]));
+		__raw_writel(int_stat, IPU_INT_STAT(int_reg[i]));
+		while ((line = ffs(int_stat)) != 0) {
+			line--;
+			int_stat &= ~(1UL << line);
+			line += (int_reg[i] - 1) * 32;
+			result |=
+			    ipu_irq_list[line].handler(line,
+						       ipu_irq_list[line].
+						       dev_id);
+		}
+	}
+
+	return result;
+}
+
+/*!
+ * This function enables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to enable interrupt for.
+ *
+ */
+void ipu_enable_irq(uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
+	reg |= IPUIRQ_2_MASK(irq);
+	__raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+}
+EXPORT_SYMBOL(ipu_enable_irq);
+
+/*!
+ * This function disables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to disable interrupt for.
+ *
+ */
+void ipu_disable_irq(uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
+	reg &= ~IPUIRQ_2_MASK(irq);
+	__raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+}
+EXPORT_SYMBOL(ipu_disable_irq);
+
+/*!
+ * This function clears the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to clear interrupt for.
+ *
+ */
+void ipu_clear_irq(uint32_t irq)
+{
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	__raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+}
+EXPORT_SYMBOL(ipu_clear_irq);
+
+/*!
+ * This function returns the current interrupt status for the specified
+ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @return      Returns true if the interrupt is pending/asserted or false if
+ *              the interrupt is not pending.
+ */
+bool ipu_get_irq_status(uint32_t irq)
+{
+	uint32_t reg;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	reg = __raw_readl(IPUIRQ_2_STATREG(irq));
+
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	if (reg & IPUIRQ_2_MASK(irq))
+		return true;
+	else
+		return false;
+}
+EXPORT_SYMBOL(ipu_get_irq_status);
+
+/*!
+ * This function registers an interrupt handler function for the specified
+ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       handler         Input parameter for address of the handler
+ *                              function.
+ *
+ * @param       irq_flags       Flags for interrupt mode. Currently not used.
+ *
+ * @param       devname         Input parameter for string name of driver
+ *                              registering the handler.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be
+ *                              passed to the handler.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int ipu_request_irq(uint32_t irq,
+		    irqreturn_t(*handler) (int, void *),
+		    uint32_t irq_flags, const char *devname, void *dev_id)
+{
+	unsigned long lock_flags;
+
+	BUG_ON(irq >= IPU_IRQ_COUNT);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (ipu_irq_list[irq].handler != NULL) {
+		dev_err(g_ipu_dev,
+			"handler already installed on irq %d\n", irq);
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	ipu_irq_list[irq].handler = handler;
+	ipu_irq_list[irq].flags = irq_flags;
+	ipu_irq_list[irq].dev_id = dev_id;
+	ipu_irq_list[irq].name = devname;
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	ipu_enable_irq(irq);	/* enable the interrupt */
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_request_irq);
+
+/*!
+ * This function unregisters an interrupt handler for the specified interrupt
+ * line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be passed
+ *                              to the handler. This must match value passed to
+ *                              ipu_request_irq().
+ *
+ */
+void ipu_free_irq(uint32_t irq, void *dev_id)
+{
+	ipu_disable_irq(irq);	/* disable the interrupt */
+
+	if (ipu_irq_list[irq].dev_id == dev_id)
+		ipu_irq_list[irq].handler = NULL;
+}
+EXPORT_SYMBOL(ipu_free_irq);
+
+uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type)
+{
+	uint32_t reg, dma_chan;
+
+	dma_chan = channel_2_dma(channel, type);
+	if (!idma_is_valid(dma_chan))
+		return -EINVAL;
+
+	reg = __raw_readl(IPU_CHA_CUR_BUF(dma_chan/32));
+	if (reg & idma_mask(dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
+
+uint32_t _ipu_channel_status(ipu_channel_t channel)
+{
+	uint32_t stat = 0;
+	uint32_t task_stat_reg = __raw_readl(IPU_PROC_TASK_STAT);
+
+	switch (channel) {
+	case MEM_PRP_VF_MEM:
+		stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
+		    TSTAT_ENC_ROT_OFFSET;
+		break;
+	case MEM_PP_MEM:
+		stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
+		break;
+
+	default:
+		stat = TASK_STAT_IDLE;
+		break;
+	}
+	return stat;
+}
+
+int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
+	int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
+
+	/* enable target channel */
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IDMAC_CHA_EN(to_dma));
+	__raw_writel(reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
+
+	g_channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	/* switch dp dc */
+	_ipu_dp_dc_disable(from_ch, true);
+
+	/* disable source channel */
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(IDMAC_CHA_EN(from_dma));
+	__raw_writel(reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
+	__raw_writel(idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
+
+	g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_swap_channel);
+
+uint32_t bytes_per_pixel(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:	/*generic data */
+	case IPU_PIX_FMT_RGB332:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YUV422P:
+		return 1;
+		break;
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		return 2;
+		break;
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 3;
+		break;
+	case IPU_PIX_FMT_GENERIC_32:	/*generic data */
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+		return 4;
+		break;
+	default:
+		return 1;
+		break;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(bytes_per_pixel);
+
+ipu_color_space_t format_to_colorspace(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+	case IPU_PIX_FMT_LVDS666:
+	case IPU_PIX_FMT_LVDS888:
+		return RGB;
+		break;
+
+	default:
+		return YCbCr;
+		break;
+	}
+	return RGB;
+}
+
+bool ipu_pixel_format_has_alpha(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_ABGR32:
+		return true;
+		break;
+	default:
+		return false;
+		break;
+	}
+	return false;
+}
+
+void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3])
+{
+	_ipu_dp_set_csc_coefficients(channel, param);
+}
+EXPORT_SYMBOL(ipu_set_csc_coefficients);
+
+static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	if (g_ipu_clk_enabled) {
+		/* save and disable enabled channels*/
+		idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0));
+		idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32));
+		while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0])
+			|| (__raw_readl(IDMAC_CHA_BUSY(32)) &
+				idma_enable_reg[1])) {
+			/* disable channel not busy already */
+			uint32_t chan_should_disable, timeout = 1000, time = 0;
+
+			chan_should_disable =
+				__raw_readl(IDMAC_CHA_BUSY(0))
+					^ idma_enable_reg[0];
+			__raw_writel((~chan_should_disable) &
+					idma_enable_reg[0], IDMAC_CHA_EN(0));
+			chan_should_disable =
+				__raw_readl(IDMAC_CHA_BUSY(1))
+					^ idma_enable_reg[1];
+			__raw_writel((~chan_should_disable) &
+					idma_enable_reg[1], IDMAC_CHA_EN(32));
+			msleep(2);
+			time += 2;
+			if (time >= timeout)
+				return -1;
+		}
+		__raw_writel(0, IDMAC_CHA_EN(0));
+		__raw_writel(0, IDMAC_CHA_EN(32));
+
+		/* save double buffer select regs */
+		ipu_cha_db_mode_reg[0] = __raw_readl(IPU_CHA_DB_MODE_SEL(0));
+		ipu_cha_db_mode_reg[1] = __raw_readl(IPU_CHA_DB_MODE_SEL(32));
+		ipu_cha_db_mode_reg[2] =
+			__raw_readl(IPU_ALT_CHA_DB_MODE_SEL(0));
+		ipu_cha_db_mode_reg[3] =
+			__raw_readl(IPU_ALT_CHA_DB_MODE_SEL(32));
+
+		/* save current buffer regs */
+		ipu_cha_cur_buf_reg[0] = __raw_readl(IPU_CHA_CUR_BUF(0));
+		ipu_cha_cur_buf_reg[1] = __raw_readl(IPU_CHA_CUR_BUF(32));
+		ipu_cha_cur_buf_reg[2] = __raw_readl(IPU_ALT_CUR_BUF0);
+		ipu_cha_cur_buf_reg[3] = __raw_readl(IPU_ALT_CUR_BUF1);
+
+		/* save sub-modules status and disable all */
+		ic_conf_reg = __raw_readl(IC_CONF);
+		__raw_writel(0, IC_CONF);
+		ipu_conf_reg = __raw_readl(IPU_CONF);
+		__raw_writel(0, IPU_CONF);
+
+		/* save buf ready regs */
+		buf_ready_reg[0] = __raw_readl(IPU_CHA_BUF0_RDY(0));
+		buf_ready_reg[1] = __raw_readl(IPU_CHA_BUF0_RDY(32));
+		buf_ready_reg[2] = __raw_readl(IPU_CHA_BUF1_RDY(0));
+		buf_ready_reg[3] = __raw_readl(IPU_CHA_BUF1_RDY(32));
+		buf_ready_reg[4] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(0));
+		buf_ready_reg[5] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(32));
+		buf_ready_reg[6] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(0));
+		buf_ready_reg[7] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(32));
+	}
+
+	mxc_pg_enable(pdev);
+
+	return 0;
+}
+
+static int ipu_resume(struct platform_device *pdev)
+{
+	mxc_pg_disable(pdev);
+
+	if (g_ipu_clk_enabled) {
+
+		/* restore buf ready regs */
+		__raw_writel(buf_ready_reg[0], IPU_CHA_BUF0_RDY(0));
+		__raw_writel(buf_ready_reg[1], IPU_CHA_BUF0_RDY(32));
+		__raw_writel(buf_ready_reg[2], IPU_CHA_BUF1_RDY(0));
+		__raw_writel(buf_ready_reg[3], IPU_CHA_BUF1_RDY(32));
+		__raw_writel(buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0));
+		__raw_writel(buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32));
+		__raw_writel(buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0));
+		__raw_writel(buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32));
+
+		/* re-enable sub-modules*/
+		__raw_writel(ipu_conf_reg, IPU_CONF);
+		__raw_writel(ic_conf_reg, IC_CONF);
+
+		/* restore double buffer select regs */
+		__raw_writel(ipu_cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0));
+		__raw_writel(ipu_cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32));
+		__raw_writel(ipu_cha_db_mode_reg[2],
+				IPU_ALT_CHA_DB_MODE_SEL(0));
+		__raw_writel(ipu_cha_db_mode_reg[3],
+				IPU_ALT_CHA_DB_MODE_SEL(32));
+
+		/* restore current buffer select regs */
+		__raw_writel(~(ipu_cha_cur_buf_reg[0]), IPU_CHA_CUR_BUF(0));
+		__raw_writel(~(ipu_cha_cur_buf_reg[1]), IPU_CHA_CUR_BUF(32));
+		__raw_writel(~(ipu_cha_cur_buf_reg[2]), IPU_ALT_CUR_BUF0);
+		__raw_writel(~(ipu_cha_cur_buf_reg[3]), IPU_ALT_CUR_BUF1);
+
+		/* restart idma channel*/
+		__raw_writel(idma_enable_reg[0], IDMAC_CHA_EN(0));
+		__raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32));
+	} else {
+		clk_enable(g_ipu_clk);
+		_ipu_dmfc_init(dmfc_type_setup, 1);
+		_ipu_init_dc_mappings();
+
+		/* Set sync refresh channels as high priority */
+		__raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
+		clk_disable(g_ipu_clk);
+	}
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcipu_driver = {
+	.driver = {
+		   .name = "mxc_ipu",
+		   },
+	.probe = ipu_probe,
+	.remove = ipu_remove,
+	.suspend_late = ipu_suspend,
+	.resume_early = ipu_resume,
+};
+
+int32_t __init ipu_gen_init(void)
+{
+	int32_t ret;
+
+	ret = platform_driver_register(&mxcipu_driver);
+	return 0;
+}
+
+subsys_initcall(ipu_gen_init);
+
+static void __exit ipu_gen_uninit(void)
+{
+	platform_driver_unregister(&mxcipu_driver);
+}
+
+module_exit(ipu_gen_uninit);
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
new file mode 100644
index 000000000000..20360ee1264a
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -0,0 +1,518 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_device.c
+ *
+ * @brief This file contains the IPUv3 driver device interface and fops functions.
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <asm/cacheflush.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+/* Strucutures and variables for exporting MXC IPU as device*/
+
+static int mxc_ipu_major;
+static struct class *mxc_ipu_class;
+
+DEFINE_SPINLOCK(event_lock);
+
+struct ipu_dev_irq_info {
+	wait_queue_head_t waitq;
+	int irq_pending;
+} irq_info[480];
+
+int register_ipu_device(void);
+
+/* Static functions */
+
+int get_events(ipu_event_info *p)
+{
+	unsigned long flags;
+	int ret = 0;
+
+	spin_lock_irqsave(&event_lock, flags);
+	if (irq_info[p->irq].irq_pending > 0)
+		irq_info[p->irq].irq_pending--;
+	else
+		ret = -1;
+	spin_unlock_irqrestore(&event_lock, flags);
+
+	return ret;
+}
+
+static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id)
+{
+	irq_info[irq].irq_pending++;
+
+	/* Wakeup any blocking user context */
+	wake_up_interruptible(&(irq_info[irq].waitq));
+	return IRQ_HANDLED;
+}
+
+static int mxc_ipu_open(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+	return ret;
+}
+static int mxc_ipu_ioctl(struct inode *inode, struct file *file,
+		unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case IPU_INIT_CHANNEL:
+		{
+			ipu_channel_parm parm;
+
+			if (copy_from_user
+					(&parm, (ipu_channel_parm *) arg,
+					 sizeof(ipu_channel_parm)))
+				return -EFAULT;
+
+			if (!parm.flag) {
+				ret =
+					ipu_init_channel(parm.channel,
+							&parm.params);
+			} else {
+				ret = ipu_init_channel(parm.channel, NULL);
+			}
+		}
+		break;
+	case IPU_UNINIT_CHANNEL:
+		{
+		ipu_channel_t ch;
+		int __user *argp = (void __user *)arg;
+		if (get_user(ch, argp))
+				return -EFAULT;
+			ipu_uninit_channel(ch);
+		}
+		break;
+	case IPU_INIT_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+				(&parm, (ipu_channel_buf_parm *) arg,
+				sizeof(ipu_channel_buf_parm)))
+				return -EFAULT;
+
+			ret =
+				ipu_init_channel_buffer(
+						parm.channel, parm.type,
+						parm.pixel_fmt,
+						parm.width, parm.height,
+						parm.stride,
+						parm.rot_mode,
+						parm.phyaddr_0,
+						parm.phyaddr_1,
+						parm.u_offset,
+						parm.v_offset);
+
+		}
+		break;
+	case IPU_UPDATE_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+				(&parm, (ipu_channel_buf_parm *) arg,
+				sizeof(ipu_channel_buf_parm)))
+				return -EFAULT;
+
+			if ((parm.phyaddr_0 != (dma_addr_t) NULL)
+				&& (parm.phyaddr_1 == (dma_addr_t) NULL)) {
+				ret =
+					ipu_update_channel_buffer(
+							parm.channel,
+							parm.type,
+							parm.bufNum,
+							parm.phyaddr_0);
+			} else if ((parm.phyaddr_0 == (dma_addr_t) NULL)
+				&& (parm.phyaddr_1 != (dma_addr_t) NULL)) {
+				ret =
+					ipu_update_channel_buffer(
+							parm.channel,
+							parm.type,
+							parm.bufNum,
+							parm.phyaddr_1);
+			} else {
+				ret = -1;
+			}
+
+		}
+		break;
+	case IPU_SELECT_CHANNEL_BUFFER:
+		{
+			ipu_channel_buf_parm parm;
+			if (copy_from_user
+				(&parm, (ipu_channel_buf_parm *) arg,
+				sizeof(ipu_channel_buf_parm)))
+				return -EFAULT;
+
+			ret =
+				ipu_select_buffer(parm.channel,
+					parm.type, parm.bufNum);
+
+		}
+		break;
+	case IPU_SELECT_MULTI_VDI_BUFFER:
+		{
+			uint32_t parm;
+			if (copy_from_user
+				(&parm, (uint32_t *) arg,
+				sizeof(uint32_t)))
+				return -EFAULT;
+
+			ret = ipu_select_multi_vdi_buffer(parm);
+		}
+		break;
+	case IPU_LINK_CHANNELS:
+		{
+			ipu_channel_link link;
+			if (copy_from_user
+				(&link, (ipu_channel_link *) arg,
+				sizeof(ipu_channel_link)))
+				return -EFAULT;
+
+			ret = ipu_link_channels(link.src_ch,
+				link.dest_ch);
+
+		}
+		break;
+	case IPU_UNLINK_CHANNELS:
+		{
+			ipu_channel_link link;
+			if (copy_from_user
+				(&link, (ipu_channel_link *) arg,
+				sizeof(ipu_channel_link)))
+				return -EFAULT;
+
+			ret = ipu_unlink_channels(link.src_ch,
+				link.dest_ch);
+
+		}
+		break;
+	case IPU_ENABLE_CHANNEL:
+		{
+			ipu_channel_t ch;
+			int __user *argp = (void __user *)arg;
+			if (get_user(ch, argp))
+				return -EFAULT;
+			ipu_enable_channel(ch);
+		}
+		break;
+	case IPU_DISABLE_CHANNEL:
+		{
+			ipu_channel_info info;
+			if (copy_from_user
+				(&info, (ipu_channel_info *) arg,
+				 sizeof(ipu_channel_info)))
+				return -EFAULT;
+
+			ret = ipu_disable_channel(info.channel,
+				info.stop);
+		}
+		break;
+	case IPU_ENABLE_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_enable_irq(irq);
+		}
+		break;
+	case IPU_DISABLE_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_disable_irq(irq);
+		}
+		break;
+	case IPU_CLEAR_IRQ:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ipu_clear_irq(irq);
+		}
+		break;
+	case IPU_FREE_IRQ:
+		{
+			ipu_irq_info info;
+
+			if (copy_from_user
+					(&info, (ipu_irq_info *) arg,
+					 sizeof(ipu_irq_info)))
+				return -EFAULT;
+
+			ipu_free_irq(info.irq, info.dev_id);
+			irq_info[info.irq].irq_pending = 0;
+		}
+		break;
+	case IPU_REQUEST_IRQ_STATUS:
+		{
+			uint32_t irq;
+			int __user *argp = (void __user *)arg;
+			if (get_user(irq, argp))
+				return -EFAULT;
+			ret = ipu_get_irq_status(irq);
+		}
+		break;
+	case IPU_REGISTER_GENERIC_ISR:
+		{
+			ipu_event_info info;
+			if (copy_from_user
+					(&info, (ipu_event_info *) arg,
+					 sizeof(ipu_event_info)))
+				return -EFAULT;
+
+			ret =
+				ipu_request_irq(info.irq,
+					mxc_ipu_generic_handler,
+					0, "video_sink", info.dev);
+			if (ret == 0)
+				init_waitqueue_head(&(irq_info[info.irq].waitq));
+		}
+		break;
+	case IPU_GET_EVENT:
+		/* User will have to allocate event_type
+		structure and pass the pointer in arg */
+		{
+			ipu_event_info info;
+			int r = -1;
+
+			if (copy_from_user
+					(&info, (ipu_event_info *) arg,
+					 sizeof(ipu_event_info)))
+				return -EFAULT;
+
+			r = get_events(&info);
+			if (r == -1) {
+				if ((file->f_flags & O_NONBLOCK) &&
+					(irq_info[info.irq].irq_pending == 0))
+					return -EAGAIN;
+				wait_event_interruptible_timeout(irq_info[info.irq].waitq,
+						(irq_info[info.irq].irq_pending != 0), 2 * HZ);
+				r = get_events(&info);
+			}
+			ret = -1;
+			if (r == 0) {
+				if (!copy_to_user((ipu_event_info *) arg,
+					&info, sizeof(ipu_event_info)))
+					ret = 0;
+			}
+		}
+		break;
+	case IPU_ALOC_MEM:
+		{
+			ipu_mem_info info;
+			if (copy_from_user
+					(&info, (ipu_mem_info *) arg,
+					 sizeof(ipu_mem_info)))
+				return -EFAULT;
+
+			info.vaddr = dma_alloc_coherent(0,
+					PAGE_ALIGN(info.size),
+					&info.paddr,
+					GFP_DMA | GFP_KERNEL);
+			if (info.vaddr == 0) {
+				printk(KERN_ERR "dma alloc failed!\n");
+				return -ENOBUFS;
+			}
+			if (copy_to_user((ipu_mem_info *) arg, &info,
+					sizeof(ipu_mem_info)) > 0)
+				return -EFAULT;
+		}
+		break;
+	case IPU_FREE_MEM:
+		{
+			ipu_mem_info info;
+			if (copy_from_user
+					(&info, (ipu_mem_info *) arg,
+					 sizeof(ipu_mem_info)))
+				return -EFAULT;
+
+			if (info.vaddr)
+				dma_free_coherent(0, PAGE_ALIGN(info.size),
+					info.vaddr, info.paddr);
+			else
+				return -EFAULT;
+		}
+		break;
+	case IPU_IS_CHAN_BUSY:
+		{
+			ipu_channel_t chan;
+			if (copy_from_user
+					(&chan, (ipu_channel_t *)arg,
+					 sizeof(ipu_channel_t)))
+				return -EFAULT;
+
+			if (ipu_is_channel_busy(chan))
+				ret = 1;
+			else
+				ret = 0;
+		}
+		break;
+	case IPU_CALC_STRIPES_SIZE:
+		{
+			ipu_stripe_parm stripe_parm;
+
+			if (copy_from_user (&stripe_parm, (ipu_stripe_parm *)arg,
+					 sizeof(ipu_stripe_parm)))
+				return -EFAULT;
+			ipu_calc_stripes_sizes(stripe_parm.input_width,
+						stripe_parm.output_width,
+						stripe_parm.maximal_stripe_width,
+						stripe_parm.cirr,
+						stripe_parm.equal_stripes,
+						stripe_parm.input_pixelformat,
+						stripe_parm.output_pixelformat,
+						&stripe_parm.left,
+						&stripe_parm.right);
+			if (copy_to_user((ipu_stripe_parm *) arg, &stripe_parm,
+					sizeof(ipu_stripe_parm)) > 0)
+				return -EFAULT;
+		}
+		break;
+	case IPU_UPDATE_BUF_OFFSET:
+		{
+			ipu_buf_offset_parm offset_parm;
+
+			if (copy_from_user (&offset_parm, (ipu_buf_offset_parm *)arg,
+					 sizeof(ipu_buf_offset_parm)))
+				return -EFAULT;
+			ret = ipu_update_channel_offset(offset_parm.channel,
+							offset_parm.type,
+							offset_parm.pixel_fmt,
+							offset_parm.width,
+							offset_parm.height,
+							offset_parm.stride,
+							offset_parm.u_offset,
+							offset_parm.v_offset,
+							offset_parm.vertical_offset,
+							offset_parm.horizontal_offset);
+		}
+		break;
+	case IPU_CSC_UPDATE:
+		{
+			int param[5][3];
+			ipu_csc_update csc;
+			if (copy_from_user(&csc, (void *) arg,
+					   sizeof(ipu_csc_update)))
+				return -EFAULT;
+			if (copy_from_user(&param[0][0], (void *) csc.param,
+					   sizeof(param)))
+				return -EFAULT;
+			ipu_set_csc_coefficients(csc.channel, param);
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+				vma->vm_end - vma->vm_start,
+				vma->vm_page_prot)) {
+		printk(KERN_ERR
+				"mmap failed!\n");
+		return -ENOBUFS;
+	}
+	return 0;
+}
+
+static int mxc_ipu_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+int mxc_ipu_fsync(struct file *filp, struct dentry *dentry, int datasync)
+{
+	flush_cache_all();
+	outer_flush_all();
+	return 0;
+}
+
+static struct file_operations mxc_ipu_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_ipu_open,
+	.mmap = mxc_ipu_mmap,
+	.release = mxc_ipu_release,
+	.ioctl = mxc_ipu_ioctl,
+	.fsync = mxc_ipu_fsync
+};
+
+int register_ipu_device()
+{
+	int ret = 0;
+	struct device *temp;
+	mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
+	if (mxc_ipu_major < 0) {
+		printk(KERN_ERR
+			"Unable to register Mxc Ipu as a char device\n");
+		return mxc_ipu_major;
+	}
+
+	mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu");
+	if (IS_ERR(mxc_ipu_class)) {
+		printk(KERN_ERR "Unable to create class for Mxc Ipu\n");
+		ret = PTR_ERR(mxc_ipu_class);
+		goto err1;
+	}
+
+	temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0),
+			NULL, "mxc_ipu");
+
+	if (IS_ERR(temp)) {
+		printk(KERN_ERR "Unable to create class device for Mxc Ipu\n");
+		ret = PTR_ERR(temp);
+		goto err2;
+	}
+	spin_lock_init(&event_lock);
+
+	return ret;
+
+err2:
+	class_destroy(mxc_ipu_class);
+err1:
+	unregister_chrdev(mxc_ipu_major, "mxc_ipu");
+	return ret;
+
+}
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
new file mode 100644
index 000000000000..ea64707468a0
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -0,0 +1,1836 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_disp.c
+ *
+ * @brief IPU display submodule API functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/clk.h>
+#include <asm/atomic.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/clock.h>
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+enum csc_type_t {
+	RGB2YUV = 0,
+	YUV2RGB,
+	RGB2RGB,
+	YUV2YUV,
+	CSC_NONE,
+	CSC_NUM
+};
+
+struct dp_csc_param_t {
+	int mode;
+	void *coeff;
+};
+
+#define SYNC_WAVE 0
+#define ASYNC_SER_WAVE 6
+
+/* DC display ID assignments */
+#define DC_DISP_ID_SYNC(di)	(di)
+#define DC_DISP_ID_SERIAL	2
+#define DC_DISP_ID_ASYNC	3
+
+int dmfc_type_setup;
+static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
+
+void _ipu_dmfc_init(int dmfc_type, int first)
+{
+	u32 dmfc_wr_chan, dmfc_dp_chan;
+
+	if (first) {
+		if (dmfc_type_setup > dmfc_type)
+			dmfc_type = dmfc_type_setup;
+		else
+			dmfc_type_setup = dmfc_type;
+
+		/* disable DMFC-IC channel*/
+		__raw_writel(0x2, DMFC_IC_CTRL);
+	} else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
+		printk(KERN_DEBUG "DMFC high resolution has set, will not change\n");
+		return;
+	} else
+		dmfc_type_setup = dmfc_type;
+
+	if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
+		/* 1 - segment 0~3;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		printk(KERN_INFO "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000088;
+		dmfc_dp_chan = 0x00009694;
+		dmfc_size_28 = 256*4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128*4;
+		dmfc_size_23 = 128*4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 2~5;
+		 * 5F - segement 6,7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		printk(KERN_INFO "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x0000968a;
+		dmfc_size_28 = 128*4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128*4;
+		dmfc_size_23 = 256*4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
+		/* 5B - segement 0~3;
+		 * 5F - segement 4~7;
+		 * 1, 1C, 2C and 6B, 6F unused;
+		 */
+		printk(KERN_INFO "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
+		dmfc_wr_chan = 0x00000000;
+		dmfc_dp_chan = 0x00008c88;
+		dmfc_size_28 = 0;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 256*4;
+		dmfc_size_23 = 256*4;
+	} else {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		printk(KERN_INFO "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x00009694;
+		dmfc_size_28 = 128*4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128*4;
+		dmfc_size_23 = 128*4;
+	}
+	__raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
+	__raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
+	__raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
+	/* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
+	__raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
+}
+
+static int __init dmfc_setup(char *options)
+{
+	get_option(&options, &dmfc_type_setup);
+	if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
+		dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
+	return 1;
+}
+__setup("dmfc=", dmfc_setup);
+
+static bool _ipu_update_dmfc_used_size(int dma_chan, int width, int dmfc_size)
+{
+	u32 fifo_size_5f = 1;
+	u32 dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN);
+
+	if ((width > 352) && (dmfc_size == (256 * 4)))
+		fifo_size_5f = 1;
+	else if (width > 176)
+		fifo_size_5f = 2;
+	else if (width > 88)
+		fifo_size_5f = 3;
+	else if (width > 44)
+		fifo_size_5f = 4;
+	else if (width > 22)
+		fifo_size_5f = 5;
+	else if (width > 11)
+		fifo_size_5f = 6;
+	else if (width > 6)
+		fifo_size_5f = 7;
+	else
+		return false;
+
+	if (dma_chan == 27) {
+		dmfc_dp_chan &= ~DMFC_FIFO_SIZE_5F;
+		dmfc_dp_chan |= fifo_size_5f << 11;
+		__raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
+	}
+
+	return true;
+}
+
+void _ipu_dmfc_set_wait4eot(int dma_chan, int width)
+{
+	u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
+
+	if (width >= HIGH_RESOLUTION_WIDTH) {
+		if (dma_chan == 23)
+			_ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
+		else if (dma_chan == 28)
+			_ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
+	}
+
+	if (dma_chan == 23) { /*5B*/
+		if (dmfc_size_23/width > 3)
+			dmfc_gen1 |= 1UL << 20;
+		else
+			dmfc_gen1 &= ~(1UL << 20);
+	} else if (dma_chan == 24) { /*6B*/
+		if (dmfc_size_24/width > 1)
+			dmfc_gen1 |= 1UL << 22;
+		else
+			dmfc_gen1 &= ~(1UL << 22);
+	} else if (dma_chan == 27) { /*5F*/
+		if (!_ipu_update_dmfc_used_size(dma_chan, width, dmfc_size_27))
+			dmfc_gen1 |= 1UL << 21;
+		else
+			dmfc_gen1 &= ~(1UL << 21);
+	} else if (dma_chan == 28) { /*1*/
+		if (dmfc_size_28/width > 2)
+			dmfc_gen1 |= 1UL << 16;
+		else
+			dmfc_gen1 &= ~(1UL << 16);
+	} else if (dma_chan == 29) { /*6F*/
+		if (dmfc_size_29/width > 1)
+			dmfc_gen1 |= 1UL << 23;
+		else
+			dmfc_gen1 &= ~(1UL << 23);
+	}
+
+	__raw_writel(dmfc_gen1, DMFC_GENERAL1);
+}
+
+static void _ipu_di_data_wave_config(int di,
+				     int wave_gen,
+				     int access_size, int component_size)
+{
+	u32 reg;
+	reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
+	    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
+	__raw_writel(reg, DI_DW_GEN(di, wave_gen));
+}
+
+static void _ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
+				    int up, int down)
+{
+	u32 reg;
+
+	reg = __raw_readl(DI_DW_GEN(di, wave_gen));
+	reg &= ~(0x3 << (di_pin * 2));
+	reg |= set << (di_pin * 2);
+	__raw_writel(reg, DI_DW_GEN(di, wave_gen));
+
+	__raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
+}
+
+static void _ipu_di_sync_config(int di, int wave_gen,
+				int run_count, int run_src,
+				int offset_count, int offset_src,
+				int repeat_count, int cnt_clr_src,
+				int cnt_polarity_gen_en,
+				int cnt_polarity_clr_src,
+				int cnt_polarity_trigger_src,
+				int cnt_up, int cnt_down)
+{
+	u32 reg;
+
+	if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
+		(cnt_up >= 0x400) || (cnt_down >= 0x400)) {
+		dev_err(g_ipu_dev, "DI%d counters out of range.\n", di);
+		return;
+	}
+
+	reg = (run_count << 19) | (++run_src << 16) |
+	    (offset_count << 3) | ++offset_src;
+	__raw_writel(reg, DI_SW_GEN0(di, wave_gen));
+	reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
+	    (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
+	reg |= (cnt_down << 16) | cnt_up;
+	if (repeat_count == 0) {
+		/* Enable auto reload */
+		reg |= 0x10000000;
+	}
+	__raw_writel(reg, DI_SW_GEN1(di, wave_gen));
+	reg = __raw_readl(DI_STP_REP(di, wave_gen));
+	reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
+	reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
+	__raw_writel(reg, DI_STP_REP(di, wave_gen));
+}
+
+static void _ipu_dc_map_link(int current_map,
+			     int base_map_0, int buf_num_0,
+			     int base_map_1, int buf_num_1,
+			     int base_map_2, int buf_num_2)
+{
+	int ptr_0 = base_map_0 * 3 + buf_num_0;
+	int ptr_1 = base_map_1 * 3 + buf_num_1;
+	int ptr_2 = base_map_2 * 3 + buf_num_2;
+	int ptr;
+	u32 reg;
+	ptr = (ptr_2 << 10) +  (ptr_1 << 5) + ptr_0;
+
+	reg = __raw_readl(DC_MAP_CONF_PTR(current_map));
+	reg &= ~(0x1F << ((16 * (current_map & 0x1))));
+	reg |= ptr << ((16 * (current_map & 0x1)));
+	__raw_writel(reg, DC_MAP_CONF_PTR(current_map));
+}
+
+static void _ipu_dc_map_config(int map, int byte_num, int offset, int mask)
+{
+	int ptr = map * 3 + byte_num;
+	u32 reg;
+
+	reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
+	reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
+	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
+	__raw_writel(reg, DC_MAP_CONF_VAL(ptr));
+
+	reg = __raw_readl(DC_MAP_CONF_PTR(map));
+	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
+	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
+	__raw_writel(reg, DC_MAP_CONF_PTR(map));
+}
+
+static void _ipu_dc_map_clear(int map)
+{
+	u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
+	__raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
+		     DC_MAP_CONF_PTR(map));
+}
+
+static void _ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
+			       int wave, int glue, int sync)
+{
+	u32 reg;
+	int stop = 1;
+
+	reg = sync;
+	reg |= (glue << 4);
+	reg |= (++wave << 11);
+	reg |= (++map << 15);
+	reg |= (operand << 20) & 0xFFF00000;
+	__raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
+
+	reg = (operand >> 12);
+	reg |= opcode << 4;
+	reg |= (stop << 9);
+	__raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
+}
+
+static void _ipu_dc_link_event(int chan, int event, int addr, int priority)
+{
+	u32 reg;
+	u32 address_shift;
+	if (event < DC_EVEN_UGDE0) {
+		reg = __raw_readl(DC_RL_CH(chan, event));
+		reg &= ~(0xFFFF << (16 * (event & 0x1)));
+		reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
+		__raw_writel(reg, DC_RL_CH(chan, event));
+	} else {
+		reg = __raw_readl(DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+		if ((event - DC_EVEN_UGDE0) & 0x1) {
+			reg &= ~(0x2FF << 16);
+			reg |= (addr << 16);
+			reg |= priority ? (2 << 24) : 0x0;
+		} else {
+			reg &= ~0xFC00FFFF;
+			if (priority)
+				chan = (chan >> 1) +
+					((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
+			else
+				chan = 0x7;
+			address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
+			reg |= (addr << address_shift) | (priority << 3) | chan;
+		}
+		__raw_writel(reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+	}
+}
+
+/*     Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
+       U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
+       V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;*/
+static const int rgb2ycbcr_coeff[5][3] = {
+	{0x4D, 0x96, 0x1D},
+	{-0x2B, -0x55, 0x80},
+	{0x80, -0x6B, -0x15},
+	{0x0000, 0x0200, 0x0200},	/* B0, B1, B2 */
+	{0x2, 0x2, 0x2},	/* S0, S1, S2 */
+};
+
+/*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+       G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+       B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
+static const int ycbcr2rgb_coeff[5][3] = {
+	{0x095, 0x000, 0x0CC},
+	{0x095, 0x3CE, 0x398},
+	{0x095, 0x0FF, 0x000},
+	{0x3E42, 0x010A, 0x3DD6},	/*B0,B1,B2 */
+	{0x1, 0x1, 0x1},	/*S0,S1,S2 */
+};
+
+#define mask_a(a) ((u32)(a) & 0x3FF)
+#define mask_b(b) ((u32)(b) & 0x3FFF)
+
+/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
+static int _rgb_to_yuv(int n, int red, int green, int blue)
+{
+	int c;
+	c = red * rgb2ycbcr_coeff[n][0];
+	c += green * rgb2ycbcr_coeff[n][1];
+	c += blue * rgb2ycbcr_coeff[n][2];
+	c /= 16;
+	c += rgb2ycbcr_coeff[3][n] * 4;
+	c += 8;
+	c /= 16;
+	if (c < 0)
+		c = 0;
+	if (c > 255)
+		c = 255;
+	return c;
+}
+
+/*
+ * Row is for BG: 	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ * Column is for FG:	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ */
+static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
+{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
+{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
+{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
+{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
+};
+
+static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
+static int color_key_4rgb = 1;
+
+void __ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
+			bool srm_mode_update)
+{
+	u32 reg;
+	const int (*coeff)[5][3];
+
+	if (dp_csc_param.mode >= 0) {
+		reg = __raw_readl(DP_COM_CONF(dp));
+		reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+		reg |= dp_csc_param.mode;
+		__raw_writel(reg, DP_COM_CONF(dp));
+	}
+
+	coeff = dp_csc_param.coeff;
+
+	if (coeff) {
+		__raw_writel(mask_a((*coeff)[0][0]) |
+				(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
+		__raw_writel(mask_a((*coeff)[0][2]) |
+				(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
+		__raw_writel(mask_a((*coeff)[1][1]) |
+				(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
+		__raw_writel(mask_a((*coeff)[2][0]) |
+				(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
+		__raw_writel(mask_a((*coeff)[2][2]) |
+				(mask_b((*coeff)[3][0]) << 16) |
+				((*coeff)[4][0] << 30), DP_CSC_0(dp));
+		__raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
+				(mask_b((*coeff)[3][2]) << 16) |
+				((*coeff)[4][2] << 30), DP_CSC_1(dp));
+	}
+
+	if (srm_mode_update) {
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+	}
+}
+
+int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+		 uint32_t out_pixel_fmt)
+{
+	int in_fmt, out_fmt;
+	int dp;
+	int partial = false;
+	uint32_t reg;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = true;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = false;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = false;
+	} else {
+		return -EINVAL;
+	}
+
+	in_fmt = format_to_colorspace(in_pixel_fmt);
+	out_fmt = format_to_colorspace(out_pixel_fmt);
+
+	if (partial) {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				fg_csc_type = RGB2RGB;
+			else
+				fg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				fg_csc_type = YUV2RGB;
+			else
+				fg_csc_type = YUV2YUV;
+		}
+	} else {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				bg_csc_type = RGB2RGB;
+			else
+				bg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				bg_csc_type = YUV2RGB;
+			else
+				bg_csc_type = YUV2YUV;
+		}
+	}
+
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	reg = __raw_readl(DP_COM_CONF(dp));
+	if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
+			(((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+			 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+			 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+			 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
+		int red, green, blue;
+		int y, u, v;
+		uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
+
+		dev_dbg(g_ipu_dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = _rgb_to_yuv(0, red, green, blue);
+		u = _rgb_to_yuv(1, red, green, blue);
+		v = _rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
+		__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp));
+		color_key_4rgb = 0;
+
+		dev_dbg(g_ipu_dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
+	}
+
+	__ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], true);
+
+	return 0;
+}
+
+void _ipu_dp_uninit(ipu_channel_t channel)
+{
+	int dp;
+	int partial = false;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = true;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = false;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = false;
+	} else {
+		return;
+	}
+
+	if (partial)
+		fg_csc_type = CSC_NONE;
+	else
+		bg_csc_type = CSC_NONE;
+
+	__ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], false);
+}
+
+void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
+{
+	u32 reg = 0;
+
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		if (interlaced) {
+			_ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
+			_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
+			_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
+		} else {
+			if (di) {
+				_ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
+				_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
+				_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 4, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 9, 5);
+					_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 8, 5);
+				}
+			} else {
+				_ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
+				_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
+				_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 7, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 10, 5);
+					_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 11, 5);
+				}
+			}
+		}
+		_ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+
+		reg = 0x2;
+		reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+		reg |= di << 2;
+		if (interlaced)
+			reg |= DC_WR_CH_CONF_FIELD_MODE;
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		/* async channels */
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
+
+		reg = 0x3;
+		reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+	}
+	__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+	__raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
+
+	__raw_writel(0x00000084, DC_GEN);
+}
+
+void _ipu_dc_uninit(int dc_chan)
+{
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		_ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 0, 0);
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
+		_ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
+	}
+}
+
+int _ipu_chan_is_interlaced(ipu_channel_t channel)
+{
+	if (channel == MEM_DC_SYNC)
+		return !!(__raw_readl(DC_WR_CH_CONF_1) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
+		return !!(__raw_readl(DC_WR_CH_CONF_5) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	return 0;
+}
+
+void _ipu_dp_dc_enable(ipu_channel_t channel)
+{
+	int di;
+	uint32_t reg;
+	uint32_t dc_chan;
+	int irq = 0;
+
+	if (channel == MEM_FG_SYNC)
+		irq = IPU_IRQ_DP_SF_END;
+	else if (channel == MEM_DC_SYNC)
+		dc_chan = 1;
+	else if (channel == MEM_BG_SYNC)
+		dc_chan = 5;
+	else
+		return;
+
+	if (channel == MEM_FG_SYNC) {
+		/* Enable FG channel */
+		reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+		__raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
+
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+		return;
+	}
+
+	di = g_dc_di_assignment[dc_chan];
+
+	/* Make sure other DC sync channel is not assigned same DI */
+	reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
+	if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
+		reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
+		reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
+		__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+	}
+
+	reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+	reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
+	__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+	clk_enable(g_pixel_clk[di]);
+}
+
+static bool dc_swap;
+
+static irqreturn_t dc_irq_handler(int irq, void *dev_id)
+{
+	struct completion *comp = dev_id;
+
+	complete(comp);
+	return IRQ_HANDLED;
+}
+
+void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap)
+{
+	int ret;
+	unsigned long lock_flags;
+	uint32_t reg;
+	uint32_t csc;
+	uint32_t dc_chan;
+	int irq = 0;
+	int timeout = 50;
+	DECLARE_COMPLETION_ONSTACK(dc_comp);
+
+	dc_swap = swap;
+
+	if (channel == MEM_DC_SYNC) {
+		dc_chan = 1;
+		irq = IPU_IRQ_DC_FC_1;
+	} else if (channel == MEM_BG_SYNC) {
+		dc_chan = 5;
+		irq = IPU_IRQ_DP_SF_END;
+	} else if (channel == MEM_FG_SYNC) {
+		/* Disable FG channel */
+		dc_chan = 5;
+
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+
+		reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+		csc = reg & DP_COM_CONF_CSC_DEF_MASK;
+		if (csc == DP_COM_CONF_CSC_DEF_FG)
+			reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+
+		reg &= ~DP_COM_CONF_FG_EN;
+		__raw_writel(reg, DP_COM_CONF(DP_SYNC));
+
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+		__raw_writel(IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
+			     IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
+		while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
+			IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
+			msleep(2);
+			timeout -= 2;
+			if (timeout <= 0)
+				break;
+		}
+		return;
+	} else {
+		return;
+	}
+
+	if (!dc_swap)
+		__raw_writel(IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0
+			+ g_dc_di_assignment[dc_chan]),
+		     IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0
+			+ g_dc_di_assignment[dc_chan]));
+	ipu_clear_irq(irq);
+	ret = ipu_request_irq(irq, dc_irq_handler, 0, NULL, &dc_comp);
+	if (ret < 0) {
+		dev_err(g_ipu_dev, "DC irq %d in use\n", irq);
+		return;
+	}
+	ret = wait_for_completion_timeout(&dc_comp, msecs_to_jiffies(50));
+
+	dev_dbg(g_ipu_dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
+	ipu_free_irq(irq, &dc_comp);
+
+	if (dc_swap) {
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+		/* Swap DC channel 1 and 5 settings, and disable old dc chan */
+		reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+		__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		reg ^= DC_WR_CH_CONF_PROG_DI_ID;
+		__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	} else {
+		spin_lock_irqsave(&ipu_lock, lock_flags);
+		reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+		reg = __raw_readl(IPU_DISP_GEN);
+		if (g_dc_di_assignment[dc_chan])
+			reg &= ~DI1_COUNTER_RELEASE;
+		else
+			reg &= ~DI0_COUNTER_RELEASE;
+		__raw_writel(reg, IPU_DISP_GEN);
+
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		/* Clock is already off because it must be done quickly, but
+		   we need to fix the ref count */
+		clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
+
+		if (__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0
+			+ g_dc_di_assignment[dc_chan])) &
+			IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0
+			+ g_dc_di_assignment[dc_chan]))
+			dev_dbg(g_ipu_dev,
+				"VSyncPre occurred before DI%d disable\n",
+				g_dc_di_assignment[dc_chan]);
+	}
+}
+
+void _ipu_init_dc_mappings(void)
+{
+	/* IPU_PIX_FMT_RGB24 */
+	_ipu_dc_map_clear(0);
+	_ipu_dc_map_config(0, 0, 7, 0xFF);
+	_ipu_dc_map_config(0, 1, 15, 0xFF);
+	_ipu_dc_map_config(0, 2, 23, 0xFF);
+
+	/* IPU_PIX_FMT_RGB666 */
+	_ipu_dc_map_clear(1);
+	_ipu_dc_map_config(1, 0, 5, 0xFC);
+	_ipu_dc_map_config(1, 1, 11, 0xFC);
+	_ipu_dc_map_config(1, 2, 17, 0xFC);
+
+	/* IPU_PIX_FMT_YUV444 */
+	_ipu_dc_map_clear(2);
+	_ipu_dc_map_config(2, 0, 15, 0xFF);
+	_ipu_dc_map_config(2, 1, 23, 0xFF);
+	_ipu_dc_map_config(2, 2, 7, 0xFF);
+
+	/* IPU_PIX_FMT_RGB565 */
+	_ipu_dc_map_clear(3);
+	_ipu_dc_map_config(3, 0, 4, 0xF8);
+	_ipu_dc_map_config(3, 1, 10, 0xFC);
+	_ipu_dc_map_config(3, 2, 15, 0xF8);
+
+	/* IPU_PIX_FMT_LVDS666 */
+	_ipu_dc_map_clear(4);
+	_ipu_dc_map_config(4, 0, 5, 0xFC);
+	_ipu_dc_map_config(4, 1, 13, 0xFC);
+	_ipu_dc_map_config(4, 2, 21, 0xFC);
+
+	/* IPU_PIX_FMT_VYUY 16bit width */
+	_ipu_dc_map_clear(5);
+	_ipu_dc_map_config(5, 0, 7, 0xFF);
+	_ipu_dc_map_config(5, 1, 0, 0x0);
+	_ipu_dc_map_config(5, 2, 15, 0xFF);
+	_ipu_dc_map_clear(6);
+	_ipu_dc_map_config(6, 0, 0, 0x0);
+	_ipu_dc_map_config(6, 1, 7, 0xFF);
+	_ipu_dc_map_config(6, 2, 15, 0xFF);
+
+	/* IPU_PIX_FMT_UYUV 16bit width */
+	_ipu_dc_map_clear(7);
+	_ipu_dc_map_link(7, 6, 0, 6, 1, 6, 2);
+	_ipu_dc_map_clear(8);
+	_ipu_dc_map_link(8, 5, 0, 5, 1, 5, 2);
+
+	/* IPU_PIX_FMT_YUYV 16bit width */
+	_ipu_dc_map_clear(9);
+	_ipu_dc_map_link(9, 5, 2, 5, 1, 5, 0);
+	_ipu_dc_map_clear(10);
+	_ipu_dc_map_link(10, 5, 1, 5, 2, 5, 0);
+
+	/* IPU_PIX_FMT_YVYU 16bit width */
+	_ipu_dc_map_clear(11);
+	_ipu_dc_map_link(11, 5, 1, 5, 2, 5, 0);
+	_ipu_dc_map_clear(12);
+	_ipu_dc_map_link(12, 5, 2, 5, 1, 5, 0);
+}
+
+int _ipu_pixfmt_to_map(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:
+	case IPU_PIX_FMT_RGB24:
+		return 0;
+	case IPU_PIX_FMT_RGB666:
+		return 1;
+	case IPU_PIX_FMT_YUV444:
+		return 2;
+	case IPU_PIX_FMT_RGB565:
+		return 3;
+	case IPU_PIX_FMT_LVDS666:
+		return 4;
+	case IPU_PIX_FMT_VYUY:
+		return 6;
+	case IPU_PIX_FMT_UYVY:
+		return 8;
+	case IPU_PIX_FMT_YUYV:
+		return 10;
+	case IPU_PIX_FMT_YVYU:
+		return 12;
+	}
+
+	return -1;
+}
+
+/*!
+ * This function sets the colorspace for of dp.
+ * modes.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       param         	If it's not NULL, update the csc table
+ *                              with this parameter.
+ *
+ * @return      N/A
+ */
+void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3])
+{
+	int dp;
+	struct dp_csc_param_t dp_csc_param;
+
+	if (channel == MEM_FG_SYNC)
+		dp = DP_SYNC;
+	else if (channel == MEM_BG_SYNC)
+		dp = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0)
+		dp = DP_ASYNC0;
+	else
+		return;
+
+	dp_csc_param.mode = -1;
+	dp_csc_param.coeff = param;
+	__ipu_dp_csc_setup(dp, dp_csc_param, true);
+}
+
+/*!
+ * This function is called to adapt synchronous LCD panel to IPU restriction.
+ *
+ */
+void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
+				      uint16_t width, uint16_t height,
+				      uint16_t h_start_width,
+				      uint16_t h_end_width,
+				      uint16_t v_start_width,
+				      uint16_t *v_end_width)
+{
+	if (*v_end_width < 2) {
+		uint16_t total_width = width + h_start_width + h_end_width;
+		uint16_t total_height_old = height + v_start_width + (*v_end_width);
+		uint16_t total_height_new = height + v_start_width + 2;
+		*v_end_width = 2;
+		*pixel_clk = (*pixel_clk) * total_width * total_height_new /
+			(total_width * total_height_old);
+		dev_err(g_ipu_dev, "WARNING: adapt panel end blank lines\n");
+	}
+}
+
+/*!
+ * This function is called to initialize a synchronous LCD panel.
+ *
+ * @param       disp            The DI the panel is attached to.
+ *
+ * @param       pixel_clk       Desired pixel clock frequency in Hz.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           The width of panel in pixels.
+ *
+ * @param       height          The height of panel in pixels.
+ *
+ * @param       hStartWidth     The number of pixel clocks between the HSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
+ *                              clocks.
+ *
+ * @param       hEndWidth       The number of pixel clocks between the end of
+ *                              valid data and the HSYNC signal for next line.
+ *
+ * @param       vStartWidth     The number of lines between the VSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       vSyncWidth      The width of the VSYNC signal in units of lines
+ *
+ * @param       vEndWidth       The number of lines between the end of valid
+ *                              data and the VSYNC signal for next frame.
+ *
+ * @param       sig             Bitfield of signal polarities for LCD interface.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
+			    uint16_t width, uint16_t height,
+			    uint32_t pixel_fmt,
+			    uint16_t h_start_width, uint16_t h_sync_width,
+			    uint16_t h_end_width, uint16_t v_start_width,
+			    uint16_t v_sync_width, uint16_t v_end_width,
+			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+{
+	unsigned long lock_flags;
+	uint32_t field0_offset = 0;
+	uint32_t field1_offset;
+	uint32_t reg;
+	uint32_t di_gen, vsync_cnt;
+	uint32_t div, rounded_pixel_clk;
+	uint32_t h_total, v_total;
+	int map;
+	int ipu_freq_scaling_enabled = 0;
+	struct clk *di_parent;
+
+	dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height);
+
+	if ((v_sync_width == 0) || (h_sync_width == 0))
+		return EINVAL;
+
+	adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
+					 h_start_width, h_end_width,
+					 v_start_width, &v_end_width);
+	h_total = width + h_sync_width + h_start_width + h_end_width;
+	v_total = height + v_sync_width + v_start_width + v_end_width;
+
+	/* Init clocking */
+	dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk);
+
+	if (sig.ext_clk) {
+		/* Set the  PLL to be an even multiple of the pixel clock. not round div for tvout*/
+		if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
+				(clk_get_usecount(g_pixel_clk[1]) == 0)) {
+			di_parent = clk_get_parent(g_di_clk[disp]);
+			if (strcmp(di_parent->name, "tve_clk") != 0 &&
+			    strcmp(di_parent->name, "ldb_di0_clk") != 0 &&
+			    strcmp(di_parent->name, "ldb_di1_clk") != 0)  {
+				rounded_pixel_clk = pixel_clk * 2;
+				while (rounded_pixel_clk < 150000000)
+					rounded_pixel_clk += pixel_clk * 2;
+				clk_set_rate(di_parent, rounded_pixel_clk);
+				clk_set_rate(g_di_clk[disp], pixel_clk);
+			}
+		}
+		clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+	} else {
+		if (clk_get_usecount(g_pixel_clk[disp]) != 0)
+			clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
+	}
+	rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
+	clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
+	msleep(5);
+	/* Get integer portion of divider */
+	div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / rounded_pixel_clk;
+
+	ipu_freq_scaling_enabled = dvfs_per_pixel_clk_limit();
+
+	if (ipu_freq_scaling_enabled) {
+		/* Enable for a divide by 2 clock change. */
+		reg = __raw_readl(IPU_PM);
+		reg &= ~(0x7f << 7);
+		reg |= 0x20 << 7;
+		reg &= ~(0x7f << 23);
+		reg |= 0x20 << 23;
+		__raw_writel(reg, IPU_PM);
+	}
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	_ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
+	_ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
+
+	map = _ipu_pixfmt_to_map(pixel_fmt);
+	if (map < 0) {
+		dev_dbg(g_ipu_dev, "IPU_DISP: No MAP\n");
+		spin_unlock_irqrestore(&ipu_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	di_gen = __raw_readl(DI_GENERAL(disp));
+
+	if (sig.interlaced) {
+		if (cpu_is_mx51_rev(CHIP_REV_2_0)) {
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					1, 				/* counter */
+					h_total/2 - 1, 	/* run count */
+					DI_SYNC_CLK,		 /* run_resolution */
+					0, 				/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 				/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					0				/* COUNT DOWN */
+					);
+
+			/* Field 1 VSYNC waveform */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					2, 				/* counter */
+					h_total - 1, 		/* run count */
+					DI_SYNC_CLK,		/* run_resolution */
+					0, 				/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 				/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					4				/* COUNT DOWN */
+					);
+
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					3, 				/* counter */
+					v_total*2 - 1, 	/* run count */
+					DI_SYNC_INT_HSYNC,	/* run_resolution */
+					1, 				/* offset */
+					DI_SYNC_INT_HSYNC, 	/* offset resolution */
+					0, 				/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					4				/* COUNT DOWN */
+					);
+
+			/* Active Field ? */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					4, 				/* counter */
+					v_total/2 - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					v_start_width, 	/*  offset */
+					DI_SYNC_HSYNC, 	/* offset resolution */
+					2, 				/* repeat count */
+					DI_SYNC_VSYNC, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					0				/* COUNT DOWN */
+					);
+
+			/* Active Line */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					5, 				/* counter */
+					0, 				/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					0, 				/*  offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					height/2, 		/* repeat count */
+					4, 				/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					0				/* COUNT DOWN */
+					);
+
+			/* Field 0 VSYNC waveform */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					6, 				/* counter */
+					v_total - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					0, 				/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 				/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL  */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					0				/* COUNT DOWN */
+					);
+
+			/* DC VSYNC waveform */
+			vsync_cnt = 7;
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					7, 				/* counter */
+					v_total/2 - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution  */
+					9, 				/* offset  */
+					DI_SYNC_HSYNC, 	/* offset resolution */
+					2, 				/* repeat count */
+					DI_SYNC_VSYNC, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					0				/* COUNT DOWN */
+					);
+
+			/* active pixel waveform */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					8, 				/* counter */
+					0, 	/* run count  */
+					DI_SYNC_CLK,	/* run_resolution */
+					h_start_width, 				/* offset  */
+					DI_SYNC_CLK, 	/* offset resolution */
+					width, 				/* repeat count  */
+					5, 	/* CNT_CLR_SEL  */
+					0, 				/* CNT_POLARITY_GEN_EN  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL  */
+					0, 				/* COUNT UP  */
+					0				/* COUNT DOWN */
+					);
+
+			/* ??? */
+			_ipu_di_sync_config(
+					disp, 			/* display */
+					9, 				/* counter */
+					v_total - 1, 	/* run count */
+					DI_SYNC_INT_HSYNC,	/* run_resolution */
+					v_total/2, 			/* offset  */
+					DI_SYNC_INT_HSYNC, 	/* offset resolution  */
+					0, 				/* repeat count */
+					DI_SYNC_HSYNC, 	/* CNT_CLR_SEL */
+					0, 				/* CNT_POLARITY_GEN_EN  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 				/* COUNT UP */
+					4				/* COUNT DOWN */
+					);
+
+			/* set gentime select and tag sel */
+			reg = __raw_readl(DI_SW_GEN1(disp, 9));
+			reg &= 0x1FFFFFFF;
+			reg |= (3-1)<<29 | 0x00008000;
+			__raw_writel(reg, DI_SW_GEN1(disp, 9));
+
+			__raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
+
+			/* set y_sel = 1 */
+			di_gen |= 0x10000000;
+			di_gen |= DI_GEN_POLARITY_5;
+			di_gen |= DI_GEN_POLARITY_8;
+		} else {
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			field1_offset = v_sync_width + v_start_width + height / 2 +
+				v_end_width;
+			if (sig.odd_field_first) {
+				field0_offset = field1_offset - 1;
+				field1_offset = 0;
+			}
+			v_total += v_start_width + v_end_width;
+
+			/* Field 1 VSYNC waveform */
+			_ipu_di_sync_config(disp, 2, v_total - 1, 1,
+					field0_offset,
+					field0_offset ? 1 : DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 0,
+					DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
+
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(disp, 3, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
+					DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
+
+			/* Active Field ? */
+			_ipu_di_sync_config(disp, 4,
+					field0_offset ?
+					field0_offset : field1_offset - 2,
+					1, v_start_width + v_sync_width, 1, 2, 2,
+					0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
+
+			/* Active Line */
+			_ipu_di_sync_config(disp, 5, 0, 1,
+					0, DI_SYNC_NONE,
+					height / 2, 4, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			/* Field 0 VSYNC waveform */
+			_ipu_di_sync_config(disp, 6, v_total - 1, 1,
+					0, DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			/* DC VSYNC waveform */
+			vsync_cnt = 7;
+			_ipu_di_sync_config(disp, 7, 0, 1,
+					field1_offset,
+					field1_offset ? 1 : DI_SYNC_NONE,
+					1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
+
+			/* active pixel waveform */
+			_ipu_di_sync_config(disp, 8, 0, DI_SYNC_CLK,
+					h_sync_width + h_start_width, DI_SYNC_CLK,
+					width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE,
+					0, 0);
+
+			/* ??? */
+			_ipu_di_sync_config(disp, 9, v_total - 1, 2,
+					0, DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			reg = __raw_readl(DI_SW_GEN1(disp, 9));
+			reg |= 0x8000;
+			__raw_writel(reg, DI_SW_GEN1(disp, 9));
+
+			__raw_writel(v_sync_width + v_start_width +
+					v_end_width + height / 2 - 1, DI_SCR_CONF(disp));
+		}
+
+		/* Init template microcode */
+		_ipu_dc_write_tmpl(0, WROD(0), 0, map, SYNC_WAVE, 0, 8);
+
+		if (sig.Hsync_pol)
+			di_gen |= DI_GEN_POLARITY_3;
+		if (sig.Vsync_pol)
+			di_gen |= DI_GEN_POLARITY_2;
+	} else {
+		/* Setup internal HSYNC waveform */
+		_ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+		/* Setup external (delayed) HSYNC waveform */
+		_ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
+				    DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
+				    0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				    DI_SYNC_CLK, 0, h_sync_width * 2);
+		/* Setup VSYNC waveform */
+		vsync_cnt = DI_SYNC_VSYNC;
+		_ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
+				    DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
+				    DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				    DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
+		__raw_writel(v_total - 1, DI_SCR_CONF(disp));
+
+		/* Setup active data waveform to sync with DC */
+		_ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
+				    v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
+				    DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
+				    DI_SYNC_NONE, 0, 0);
+		_ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
+				    h_sync_width + h_start_width, DI_SYNC_CLK,
+				    width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
+				    0);
+
+		/* reset all unused counters */
+		__raw_writel(0, DI_SW_GEN0(disp, 6));
+		__raw_writel(0, DI_SW_GEN1(disp, 6));
+		__raw_writel(0, DI_SW_GEN0(disp, 7));
+		__raw_writel(0, DI_SW_GEN1(disp, 7));
+		__raw_writel(0, DI_SW_GEN0(disp, 8));
+		__raw_writel(0, DI_SW_GEN1(disp, 8));
+		__raw_writel(0, DI_SW_GEN0(disp, 9));
+		__raw_writel(0, DI_SW_GEN1(disp, 9));
+
+		reg = __raw_readl(DI_STP_REP(disp, 6));
+		reg &= 0x0000FFFF;
+		__raw_writel(reg, DI_STP_REP(disp, 6));
+		__raw_writel(0, DI_STP_REP(disp, 7));
+		__raw_writel(0, DI_STP_REP(disp, 9));
+
+		if (ipu_freq_scaling_enabled) {
+			h_total = ((width + h_start_width +
+					h_sync_width) / 2) - 2;
+			_ipu_di_sync_config(disp, 6, 1, 0,
+				2, DI_SYNC_CLK,
+				h_total,
+				DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
+				DI_SYNC_NONE, 0, 0);
+		}
+
+		/* Init template microcode */
+		if (disp) {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5);
+				_ipu_dc_write_tmpl(9, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+				/* configure user events according to DISP NUM */
+				__raw_writel((width - 1), DC_UGDE_3(disp));
+			}
+		   _ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+		   _ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+		   _ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+		} else {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5);
+				_ipu_dc_write_tmpl(11, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+				/* configure user events according to DISP NUM */
+				__raw_writel(width - 1, DC_UGDE_3(disp));
+			}
+		   _ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+		   _ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+		   _ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+		}
+
+		if (sig.Hsync_pol)
+			di_gen |= DI_GEN_POLARITY_2;
+		if (sig.Vsync_pol)
+			di_gen |= DI_GEN_POLARITY_3;
+
+		if (ipu_freq_scaling_enabled)
+			/* Set the clock to stop at counter 6. */
+			di_gen |= 0x6000000;
+	}
+	/* changinc DISP_CLK polarity: it can be wrong for some applications */
+	if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+		(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+		(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+		(pixel_fmt == IPU_PIX_FMT_VYUY))
+			di_gen |= 0x00020000;
+
+	__raw_writel(di_gen, DI_GENERAL(disp));
+
+	if (!ipu_freq_scaling_enabled)
+		__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+					0x00000002, DI_SYNC_AS_GEN(disp));
+	else {
+		if (sig.interlaced)
+			__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+					0x00000002, DI_SYNC_AS_GEN(disp));
+		else
+			__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
+					DI_SYNC_AS_GEN(disp));
+	}
+
+	reg = __raw_readl(DI_POL(disp));
+	reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
+	if (sig.enable_pol)
+		reg |= DI_POL_DRDY_POLARITY_15;
+	if (sig.data_pol)
+		reg |= DI_POL_DRDY_DATA_POLARITY;
+	__raw_writel(reg, DI_POL(disp));
+
+	__raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_sync_panel);
+
+
+int ipu_init_async_panel(int disp, int type, uint32_t cycle_time,
+			 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
+{
+	unsigned long lock_flags;
+	int map;
+	u32 ser_conf = 0;
+	u32 div;
+	u32 di_clk = clk_get_rate(g_ipu_clk);
+
+	/* round up cycle_time, then calcalate the divider using scaled math */
+	cycle_time += (1000000000UL / di_clk) - 1;
+	div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
+
+	map = _ipu_pixfmt_to_map(pixel_fmt);
+	if (map < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (type == IPU_PANEL_SERIAL) {
+		__raw_writel((div << 24) | ((sig.ifc_width - 1) << 4),
+			     DI_DW_GEN(disp, ASYNC_SER_WAVE));
+
+		_ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_CS,
+					0, 0, (div * 2) + 1);
+		_ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
+					1, div, div * 2);
+		_ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
+					2, 0, 0);
+
+		_ipu_dc_write_tmpl(0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0);
+
+		/* Configure DC for serial panel */
+		__raw_writel(0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
+
+		if (sig.clk_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
+		if (sig.data_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
+		if (sig.rs_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
+		if (sig.cs_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
+		__raw_writel(ser_conf, DI_SER_CONF(disp));
+	}
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_async_panel);
+
+/*!
+ * This function sets the foreground and background plane global alpha blending
+ * modes. This function also sets the DP graphic plane according to the
+ * parameter of IPUv3 DP channel.
+ *
+ * @param	channel		IPUv3 DP channel
+ *
+ * @param       enable          Boolean to enable or disable global alpha
+ *                              blending. If disabled, local blending is used.
+ *
+ * @param       alpha           Global alpha value.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, bool enable,
+				  uint8_t alpha)
+{
+	uint32_t reg;
+	uint32_t flow;
+	unsigned long lock_flags;
+	bool bg_chan;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
+	    channel == MEM_BG_ASYNC1)
+		bg_chan = true;
+	else
+		bg_chan = false;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	if (bg_chan) {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	}
+
+	if (enable) {
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+		__raw_writel(reg | ((uint32_t) alpha << 24),
+			     DP_GRAPH_WIND_CTRL(flow));
+
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	}
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_global_alpha);
+
+/*!
+ * This function sets the transparent color key for SDC graphic plane.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable color key
+ *
+ * @param       colorKey        24-bit RGB color for transparent color key.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_color_key(ipu_channel_t channel, bool enable,
+			       uint32_t color_key)
+{
+	uint32_t reg, flow;
+	int y, u, v;
+	int red, green, blue;
+	unsigned long lock_flags;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	color_key_4rgb = 1;
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+			((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+			((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+			((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
+
+		dev_dbg(g_ipu_dev, "color key 0x%x need change to yuv fmt\n", color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = _rgb_to_yuv(0, red, green, blue);
+		u = _rgb_to_yuv(1, red, green, blue);
+		v = _rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		color_key_4rgb = 0;
+
+		dev_dbg(g_ipu_dev, "color key change to yuv fmt 0x%x\n", color_key);
+	}
+
+	if (enable) {
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
+		__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	}
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_color_key);
+
+/*!
+ * This function sets the gamma correction for DP output.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable gamma correction.
+ *
+ * @param       constk        	Gamma piecewise linear approximation constk coeff.
+ *
+ * @param       slopek        	Gamma piecewise linear approximation slopek coeff.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_gamma_correction(ipu_channel_t channel, bool enable, int constk[], int slopek[])
+{
+	uint32_t reg, flow, i;
+	unsigned long lock_flags;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	for (i = 0; i < 8; i++)
+		__raw_writel((constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
+	for (i = 0; i < 4; i++)
+		__raw_writel((slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
+			((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
+
+	reg = __raw_readl(DP_COM_CONF(flow));
+	if (enable) {
+		if ((bg_csc_type == RGB2YUV) || (bg_csc_type == YUV2YUV))
+			reg |= DP_COM_CONF_GAMMA_YUV_EN;
+		else
+			reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
+		__raw_writel(reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
+	} else
+		__raw_writel(reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
+
+/*!
+ * This function sets the window position of the foreground or background plane.
+ * modes.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       x_pos           The X coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @param       y_pos           The Y coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos,
+				int16_t y_pos)
+{
+	u32 reg;
+	unsigned long lock_flags;
+	uint32_t flow = 0;
+
+	if (channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	__raw_writel((x_pos << 16) | y_pos, DP_FG_POS(flow));
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_window_pos);
+
+int32_t ipu_disp_get_window_pos(ipu_channel_t channel, int16_t *x_pos,
+				int16_t *y_pos)
+{
+	u32 reg;
+	unsigned long lock_flags;
+	uint32_t flow = 0;
+
+	if (channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+	spin_lock_irqsave(&ipu_lock, lock_flags);
+
+	reg = __raw_readl(DP_FG_POS(flow));
+
+	*x_pos = (reg >> 16) & 0x7FF;
+	*y_pos = reg & 0x7FF;
+
+	spin_unlock_irqrestore(&ipu_lock, lock_flags);
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_get_window_pos);
+
+void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset)
+{
+	if (channel == DIRECT_ASYNC0)
+		__raw_writel(value, ipu_disp_base[0] + offset);
+	else if (channel == DIRECT_ASYNC1)
+		__raw_writel(value, ipu_disp_base[1] + offset);
+}
+EXPORT_SYMBOL(ipu_disp_direct_write);
+
+void ipu_reset_disp_panel(void)
+{
+	uint32_t tmp;
+
+	tmp = __raw_readl(DI_GENERAL(1));
+	__raw_writel(tmp | 0x08, DI_GENERAL(1));
+	msleep(10); /* tRES >= 100us */
+	tmp = __raw_readl(DI_GENERAL(1));
+	__raw_writel(tmp & ~0x08, DI_GENERAL(1));
+	msleep(60);
+
+	return;
+}
+EXPORT_SYMBOL(ipu_reset_disp_panel);
diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c
new file mode 100644
index 000000000000..8bb28c929620
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_ic.c
@@ -0,0 +1,826 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_ic.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+enum {
+	IC_TASK_VIEWFINDER,
+	IC_TASK_ENCODER,
+	IC_TASK_POST_PROCESSOR
+};
+
+static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format, int csc_index);
+static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize,
+				uint32_t *resizeCoeff,
+				uint32_t *downsizeCoeff);
+
+void _ipu_vdi_set_top_field_man(bool top_field_0)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(VDI_C);
+	if (top_field_0)
+		reg &= ~VDI_C_TOP_FIELD_MAN_1;
+	else
+		reg |= VDI_C_TOP_FIELD_MAN_1;
+	__raw_writel(reg, VDI_C);
+}
+
+void _ipu_vdi_set_motion(ipu_motion_sel motion_sel)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(VDI_C);
+	reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
+	if (motion_sel == HIGH_MOTION)
+		reg |= VDI_C_MOT_SEL_FULL;
+	else if (motion_sel == MED_MOTION)
+		reg |= VDI_C_MOT_SEL_MED;
+	else
+		reg |= VDI_C_MOT_SEL_LOW;
+
+	__raw_writel(reg, VDI_C);
+}
+
+void ic_dump_register(void)
+{
+	printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", __raw_readl(IC_CONF));
+	printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
+	       __raw_readl(IC_PRP_ENC_RSC));
+	printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
+	       __raw_readl(IC_PRP_VF_RSC));
+	printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", __raw_readl(IC_PP_RSC));
+	printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", __raw_readl(IC_IDMAC_1));
+	printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", __raw_readl(IC_IDMAC_2));
+	printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", __raw_readl(IC_IDMAC_3));
+}
+
+void _ipu_ic_enable_task(ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = __raw_readl(IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_EN;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_MEM:
+		ic_conf |= IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf |= IC_CONF_PP_ROT_EN;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_disable_task(ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = __raw_readl(IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_EN;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_ROT_EN;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params)
+{
+	uint32_t reg;
+	uint32_t pixel_fmt;
+
+	reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
+	  (params->mem_prp_vf_mem.in_width-1);
+	__raw_writel(reg, VDI_FSIZE);
+
+	/* Full motion, only vertical filter is used
+	   Burst size is 4 accesses */
+	pixel_fmt =
+	    (params->mem_prp_vf_mem.in_pixel_fmt ==
+	     V4L2_PIX_FMT_YUV422P) ? VDI_C_CH_422 : VDI_C_CH_420;
+
+	reg = __raw_readl(VDI_C);
+	reg |= pixel_fmt;
+	switch (channel) {
+	case MEM_VDI_PRP_VF_MEM:
+		reg |= VDI_C_BURST_SIZE2_4;
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+		reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
+		break;
+	case MEM_VDI_PRP_VF_MEM_N:
+		reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(reg, VDI_C);
+
+	_ipu_vdi_set_top_field_man(false);
+
+	_ipu_vdi_set_motion(params->mem_prp_vf_mem.motion_sel);
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_RWS_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_vdi_uninit(void)
+{
+	__raw_writel(0, VDI_FSIZE);
+	__raw_writel(0, VDI_C);
+}
+
+void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	_calc_resize_coeffs(params->mem_prp_vf_mem.in_height,
+			    params->mem_prp_vf_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_prp_vf_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(params->mem_prp_vf_mem.in_width,
+				params->mem_prp_vf_mem.out_width,
+				&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else
+		reg |= params->mem_prp_vf_mem.outh_resize_ratio;
+
+	__raw_writel(reg, IC_PRP_VF_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_prp_vf_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PRPVF_CMB;
+
+		if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
+			/* need transparent CSC1 conversion */
+			_init_csc(IC_TASK_VIEWFINDER, RGB, RGB, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;  /* Enable RGB->RGB CSC */
+		}
+		in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
+		out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
+		if (in_fmt == RGB) {
+			if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+				/* Enable RGB->YCBCR CSC2 */
+				_init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
+				ic_conf |= IC_CONF_PRPVF_CSC2;
+			}
+		}
+		if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+			if (out_fmt == RGB) {
+				/* Enable YCBCR->RGB CSC2 */
+				_init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
+				ic_conf |= IC_CONF_PRPVF_CSC2;
+			} else {
+				/* TODO: Support YUV<->YCbCr conversion? */
+			}
+		}
+
+		if (params->mem_prp_vf_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+			reg = __raw_readl(IC_CMBP_1);
+			reg &= ~(0xff);
+			reg |= params->mem_prp_vf_mem.alpha;
+			__raw_writel(reg, IC_CMBP_1);
+		} else
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+
+		if (params->mem_prp_vf_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+			__raw_writel(params->mem_prp_vf_mem.key_color,
+					IC_CMBP_2);
+		} else
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+	} else {
+		ic_conf &= ~IC_CONF_PRPVF_CMB;
+	}
+
+	if (src_is_csi)
+		ic_conf &= ~IC_CONF_RWS_EN;
+	else
+		ic_conf |= IC_CONF_RWS_EN;
+
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpvf(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
+		 IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_vf(void)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_PRPVF_ROT_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	_calc_resize_coeffs(params->mem_prp_enc_mem.in_height,
+			    params->mem_prp_enc_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+	reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_prp_enc_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(params->mem_prp_enc_mem.in_width,
+				params->mem_prp_enc_mem.out_width,
+				&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else
+		reg |= params->mem_prp_enc_mem.outh_resize_ratio;
+
+	__raw_writel(reg, IC_PRP_ENC_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(IC_TASK_ENCODER, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PRPENC_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(IC_TASK_ENCODER, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PRPENC_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (src_is_csi)
+		ic_conf &= ~IC_CONF_RWS_EN;
+	else
+		ic_conf |= IC_CONF_RWS_EN;
+
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpenc(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_enc(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_ROT_EN);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_pp(ipu_channel_params_t *params)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	if (!(params->mem_pp_mem.outv_resize_ratio)) {
+		_calc_resize_coeffs(params->mem_pp_mem.in_height,
+			    params->mem_pp_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+		reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+	} else {
+		reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
+	}
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_pp_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(params->mem_pp_mem.in_width,
+							params->mem_pp_mem.out_width,
+							&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else {
+		reg |= params->mem_pp_mem.outh_resize_ratio;
+	}
+
+	__raw_writel(reg, IC_PP_RSC);
+
+	ic_conf = __raw_readl(IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PP_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PP_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_pp_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PP_CMB;
+
+		if (!(ic_conf & IC_CONF_PP_CSC1)) {
+			/* need transparent CSC1 conversion */
+			_init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
+			ic_conf |= IC_CONF_PP_CSC1;  /* Enable RGB->RGB CSC */
+		}
+
+		in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
+		out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
+		if (in_fmt == RGB) {
+			if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+				/* Enable RGB->YCBCR CSC2 */
+				_init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
+				ic_conf |= IC_CONF_PP_CSC2;
+			}
+		}
+		if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+			if (out_fmt == RGB) {
+				/* Enable YCBCR->RGB CSC2 */
+				_init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
+				ic_conf |= IC_CONF_PP_CSC2;
+			} else {
+				/* TODO: Support YUV<->YCbCr conversion? */
+			}
+		}
+
+		if (params->mem_pp_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+			reg = __raw_readl(IC_CMBP_1);
+			reg &= ~(0xff00);
+			reg |= (params->mem_pp_mem.alpha << 8);
+			__raw_writel(reg, IC_CMBP_1);
+		} else
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+
+		if (params->mem_pp_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+			__raw_writel(params->mem_pp_mem.key_color,
+					IC_CMBP_2);
+		} else
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+	} else {
+		ic_conf &= ~IC_CONF_PP_CMB;
+	}
+
+	__raw_writel(ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_pp(void)
+{
+	uint32_t reg;
+
+	reg = __raw_readl(IC_CONF);
+	reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
+		 IC_CONF_PP_CMB);
+	__raw_writel(reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_pp(void)
+{
+	uint32_t reg;
+	reg = __raw_readl(IC_CONF);
+	reg &= ~IC_CONF_PP_ROT_EN;
+	__raw_writel(reg, IC_CONF);
+}
+
+int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height,
+		      int burst_size, ipu_rotate_mode_t rot)
+{
+	u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
+	u32 temp_rot = bitrev8(rot) >> 5;
+	bool need_hor_flip = false;
+
+	if ((burst_size != 8) && (burst_size != 16)) {
+		dev_dbg(g_ipu_dev, "Illegal burst length for IC\n");
+		return -EINVAL;
+	}
+
+	width--;
+	height--;
+
+	if (temp_rot & 0x2)	/* Need horizontal flip */
+		need_hor_flip = true;
+
+	ic_idmac_1 = __raw_readl(IC_IDMAC_1);
+	ic_idmac_2 = __raw_readl(IC_IDMAC_2);
+	ic_idmac_3 = __raw_readl(IC_IDMAC_3);
+	if (dma_chan == 22) {	/* PP output - CB2 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
+
+	} else if (dma_chan == 11) {	/* PP Input - CB5 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
+	} else if (dma_chan == 47) {	/* PP Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
+	}
+
+	if (dma_chan == 12) {	/* PRP Input - CB6 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
+	}
+
+	if (dma_chan == 20) {	/* PRP ENC output - CB0 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
+
+	} else if (dma_chan == 45) {	/* PRP ENC Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
+	}
+
+	if (dma_chan == 21) {	/* PRP VF output - CB1 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
+
+	} else if (dma_chan == 46) {	/* PRP VF Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
+	}
+
+	if (dma_chan == 14) {	/* PRP VF graphics combining input - CB3 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
+	} else if (dma_chan == 15) {	/* PP graphics combining input - CB4 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
+	}
+
+	__raw_writel(ic_idmac_1, IC_IDMAC_1);
+	__raw_writel(ic_idmac_2, IC_IDMAC_2);
+	__raw_writel(ic_idmac_3, IC_IDMAC_3);
+
+	return 0;
+}
+
+static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format, int csc_index)
+{
+
+/*     Y = R *  .299 + G *  .587 + B *  .114;
+       U = R * -.169 + G * -.332 + B *  .500 + 128.;
+       V = R *  .500 + G * -.419 + B * -.0813 + 128.;*/
+	static const uint32_t rgb2ycbcr_coeff[4][3] = {
+		{0x004D, 0x0096, 0x001D},
+		{0x01D5, 0x01AB, 0x0080},
+		{0x0080, 0x0195, 0x01EB},
+		{0x0000, 0x0200, 0x0200},	/* A0, A1, A2 */
+	};
+
+	/* transparent RGB->RGB matrix for combining
+	 */
+	static const uint32_t rgb2rgb_coeff[4][3] = {
+		{0x0080, 0x0000, 0x0000},
+		{0x0000, 0x0080, 0x0000},
+		{0x0000, 0x0000, 0x0080},
+		{0x0000, 0x0000, 0x0000},	/* A0, A1, A2 */
+	};
+
+/*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+       G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+       B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
+	static const uint32_t ycbcr2rgb_coeff[4][3] = {
+		{149, 0, 204},
+		{149, 462, 408},
+		{149, 255, 0},
+		{8192 - 446, 266, 8192 - 554},	/* A0, A1, A2 */
+	};
+
+	uint32_t param;
+	uint32_t *base = NULL;
+
+	if (ic_task == IC_TASK_ENCODER) {
+		base = ipu_tpmem_base + 0x2008 / 4;
+	} else if (ic_task == IC_TASK_VIEWFINDER) {
+		if (csc_index == 1)
+			base = ipu_tpmem_base + 0x4028 / 4;
+		else
+			base = ipu_tpmem_base + 0x4040 / 4;
+	} else if (ic_task == IC_TASK_POST_PROCESSOR) {
+		if (csc_index == 1)
+			base = ipu_tpmem_base + 0x6060 / 4;
+		else
+			base = ipu_tpmem_base + 0x6078 / 4;
+	} else {
+		BUG();
+	}
+
+	if ((in_format == YCbCr) && (out_format == RGB)) {
+		/* Init CSC (YCbCr->RGB) */
+		param = (ycbcr2rgb_coeff[3][0] << 27) |
+			(ycbcr2rgb_coeff[0][0] << 18) |
+			(ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
+		__raw_writel(param, base++);
+		/* scale = 2, sat = 0 */
+		param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
+		__raw_writel(param, base++);
+
+		param = (ycbcr2rgb_coeff[3][1] << 27) |
+			(ycbcr2rgb_coeff[0][1] << 18) |
+			(ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
+		__raw_writel(param, base++);
+		param = (ycbcr2rgb_coeff[3][1] >> 5);
+		__raw_writel(param, base++);
+
+		param = (ycbcr2rgb_coeff[3][2] << 27) |
+			(ycbcr2rgb_coeff[0][2] << 18) |
+			(ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
+		__raw_writel(param, base++);
+		param = (ycbcr2rgb_coeff[3][2] >> 5);
+		__raw_writel(param, base++);
+	} else if ((in_format == RGB) && (out_format == YCbCr)) {
+		/* Init CSC (RGB->YCbCr) */
+		param = (rgb2ycbcr_coeff[3][0] << 27) |
+			(rgb2ycbcr_coeff[0][0] << 18) |
+			(rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
+		__raw_writel(param, base++);
+		/* scale = 1, sat = 0 */
+		param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
+		__raw_writel(param, base++);
+
+		param = (rgb2ycbcr_coeff[3][1] << 27) |
+			(rgb2ycbcr_coeff[0][1] << 18) |
+			(rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
+		__raw_writel(param, base++);
+		param = (rgb2ycbcr_coeff[3][1] >> 5);
+		__raw_writel(param, base++);
+
+		param = (rgb2ycbcr_coeff[3][2] << 27) |
+			(rgb2ycbcr_coeff[0][2] << 18) |
+			(rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
+		__raw_writel(param, base++);
+		param = (rgb2ycbcr_coeff[3][2] >> 5);
+		__raw_writel(param, base++);
+	} else if ((in_format == RGB) && (out_format == RGB)) {
+		/* Init CSC */
+		param =
+		    (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
+		    (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
+		__raw_writel(param, base++);
+		/* scale = 2, sat = 0 */
+		param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
+		__raw_writel(param, base++);
+
+		param =
+		    (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
+		    (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
+		__raw_writel(param, base++);
+		param = (rgb2rgb_coeff[3][1] >> 5);
+		__raw_writel(param, base++);
+
+		param =
+		    (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
+		    (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
+		__raw_writel(param, base++);
+		param = (rgb2rgb_coeff[3][2] >> 5);
+		__raw_writel(param, base++);
+	} else {
+		dev_err(g_ipu_dev, "Unsupported color space conversion\n");
+	}
+}
+
+static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize,
+				uint32_t *resizeCoeff,
+				uint32_t *downsizeCoeff)
+{
+	uint32_t tempSize;
+	uint32_t tempDownsize;
+
+	/* Input size cannot be more than 4096 */
+	/* Output size cannot be more than 1024 */
+	if ((inSize > 4096) || (outSize > 1024))
+		return false;
+
+	/* Cannot downsize more than 8:1 */
+	if ((outSize << 3) < inSize)
+		return false;
+
+	/* Compute downsizing coefficient */
+	/* Output of downsizing unit cannot be more than 1024 */
+	tempDownsize = 0;
+	tempSize = inSize;
+	while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
+	       (tempDownsize < 2)) {
+		tempSize >>= 1;
+		tempDownsize++;
+	}
+	*downsizeCoeff = tempDownsize;
+
+	/* compute resizing coefficient using the following equation:
+	   resizeCoeff = M*(SI -1)/(SO - 1)
+	   where M = 2^13, SI - input size, SO - output size    */
+	*resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
+	if (*resizeCoeff >= 16384L) {
+		dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n");
+		*resizeCoeff = 0x3FFF;
+	}
+
+	dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, "
+		"downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
+		*downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
+		((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
+
+	return true;
+}
+
+void _ipu_vdi_toggle_top_field_man()
+{
+	uint32_t reg;
+	uint32_t mask_reg;
+
+	reg = __raw_readl(VDI_C);
+	mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
+	if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
+		reg &= ~VDI_C_TOP_FIELD_MAN_1;
+	else
+		reg |= VDI_C_TOP_FIELD_MAN_1;
+
+	__raw_writel(reg, VDI_C);
+}
+
diff --git a/drivers/mxc/ipu3/ipu_param_mem.h b/drivers/mxc/ipu3/ipu_param_mem.h
new file mode 100644
index 000000000000..30e6dc1005ba
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_param_mem.h
@@ -0,0 +1,562 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PARAM_MEM_H__
+#define __INCLUDE_IPU_PARAM_MEM_H__
+
+#include <linux/types.h>
+#include <linux/bitrev.h>
+
+extern u32 *ipu_cpmem_base;
+
+struct ipu_ch_param_word {
+	uint32_t data[5];
+	uint32_t res[3];
+};
+
+struct ipu_ch_param {
+	struct ipu_ch_param_word word[2];
+};
+
+#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
+
+#define _param_word(base, w) \
+	(((struct ipu_ch_param *)(base))->word[(w)].data)
+
+#define ipu_ch_param_set_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	_param_word(base, w)[i] |= (v) << off; \
+	if (((bit)+(size)-1)/32 > i) { \
+		_param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
+	} \
+}
+
+#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp = _param_word(base, w)[i]; \
+	temp &= ~(mask << off); \
+	_param_word(base, w)[i] = temp | (v) << off; \
+	if (((bit)+(size)-1)/32 > i) { \
+		temp = _param_word(base, w)[i + 1]; \
+		temp &= ~(mask >> (32 - off)); \
+		_param_word(base, w)[i + 1] = \
+			temp | ((v) >> (off ? (32 - off) : 0)); \
+	} \
+}
+
+#define ipu_ch_param_read_field(base, w, bit, size) ({ \
+	u32 temp2; \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp1 = _param_word(base, w)[i]; \
+	temp1 = mask & (temp1 >> off); \
+	if (((bit)+(size)-1)/32 > i) { \
+		temp2 = _param_word(base, w)[i + 1]; \
+		temp2 &= mask >> (off ? (32 - off) : 0); \
+		temp1 |= temp2 << (off ? (32 - off) : 0); \
+	} \
+	temp1; \
+})
+
+static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p,
+					      int red_width, int red_offset,
+					      int green_width, int green_offset,
+					      int blue_width, int blue_offset,
+					      int alpha_width, int alpha_offset)
+{
+	/* Setup red width and offset */
+	ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
+	ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
+	/* Setup green width and offset */
+	ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
+	ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
+	/* Setup blue width and offset */
+	ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
+	ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
+	/* Setup alpha width and offset */
+	ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
+	ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
+}
+
+static inline void _ipu_ch_param_dump(int ch)
+{
+	struct ipu_ch_param *p = ipu_ch_param_addr(ch);
+	pr_debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
+		 p->word[0].data[3], p->word[0].data[4]);
+	pr_debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
+		 p->word[1].data[3], p->word[1].data[4]);
+	pr_debug("PFS 0x%x, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
+	pr_debug("BPP 0x%x, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
+	pr_debug("NPB 0x%x\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
+
+	pr_debug("FW %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
+	pr_debug("FH %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
+	pr_debug("Stride %d\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
+
+	pr_debug("Width0 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
+	pr_debug("Width1 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
+	pr_debug("Width2 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
+	pr_debug("Width3 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
+	pr_debug("Offset0 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
+	pr_debug("Offset1 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
+	pr_debug("Offset2 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
+	pr_debug("Offset3 %d\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
+}
+
+static inline void _ipu_ch_param_init(int ch,
+				      uint32_t pixel_fmt, uint32_t width,
+				      uint32_t height, uint32_t stride,
+				      uint32_t u, uint32_t v,
+				      uint32_t uv_stride, dma_addr_t addr0,
+				      dma_addr_t addr1)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	struct ipu_ch_param params;
+
+	memset(&params, 0, sizeof(params));
+
+	ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
+
+	if ((ch == 8) || (ch == 9) || (ch == 10)) {
+		ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
+	} else {
+		ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
+	}
+
+	/* EBA is 8-byte aligned */
+	ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
+	ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
+	if (addr0%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
+	if (addr1%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+		/*Represents 8-bit Generic data */
+		ipu_ch_param_set_field(&params, 0, 107, 3, 5);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 6);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 63);	/* burst size */
+
+		break;
+	case IPU_PIX_FMT_GENERIC_32:
+		/*Represents 32-bit Generic data */
+		break;
+	case IPU_PIX_FMT_RGB565:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
+		break;
+	case IPU_PIX_FMT_BGR24:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
+		break;
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
+		break;
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
+		break;
+	case IPU_PIX_FMT_ABGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_UYVY:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0xA);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		break;
+	case IPU_PIX_FMT_YUYV:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0x8);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		break;
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		ipu_ch_param_set_field(&params, 1, 85, 4, 2);	/* pix format */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * height;
+		v_offset = u_offset + (uv_stride * height / 2);
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
+		}
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = (v == 0) ? stride * height : v;
+		u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = (u == 0) ? stride * height : u;
+		v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
+		break;
+	case IPU_PIX_FMT_NV12:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 4);	/* pix format */
+		uv_stride = stride;
+		u_offset = (u == 0) ? stride * height : u;
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		}
+		break;
+	default:
+		dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+	/*set burst size to 16*/
+
+
+	if (uv_stride)
+		ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
+
+	/* Get the uv offset from user when need cropping */
+	if (u || v) {
+		u_offset = u;
+		v_offset = v;
+	}
+
+	/* UBO and VBO are 22-bit and 8-byte aligned */
+	if (u_offset/8 > 0x3fffff)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's U offset exceeds IPU limitation\n", ch);
+	if (v_offset/8 > 0x3fffff)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's V offset is not 8-byte aligned\n", ch);
+
+	ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
+	ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
+
+	pr_debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
+	memcpy(ipu_ch_param_addr(ch), &params, sizeof(params));
+};
+
+static inline void _ipu_ch_param_set_burst_size(uint32_t ch,
+						uint16_t burst_pixels)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 78, 7,
+			       burst_pixels - 1);
+};
+
+static inline int _ipu_ch_param_get_burst_size(uint32_t ch)
+{
+	return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7) + 1;
+};
+
+static inline int _ipu_ch_param_get_bpp(uint32_t ch)
+{
+	return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3);
+};
+
+static inline void _ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
+					    dma_addr_t phyaddr)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
+			       phyaddr / 8);
+};
+
+static inline void _ipu_ch_param_set_rotation(uint32_t ch,
+					      ipu_rotate_mode_t rot)
+{
+	u32 temp_rot = bitrev8(rot) >> 5;
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 119, 3, temp_rot);
+};
+
+static inline void _ipu_ch_param_set_block_mode(uint32_t ch)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 117, 2, 1);
+};
+
+static inline void _ipu_ch_param_set_alpha_use_separate_channel(uint32_t ch,
+								bool option)
+{
+	if (option) {
+		ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 89, 1, 1);
+	} else {
+		ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 89, 1, 0);
+	}
+};
+
+static inline void _ipu_ch_param_set_alpha_condition_read(uint32_t ch)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 149, 1, 1);
+};
+
+static inline void _ipu_ch_param_set_alpha_buffer_memory(uint32_t ch)
+{
+	int alp_mem_idx;
+
+	switch (ch) {
+	case 14: /* PRP graphic */
+		alp_mem_idx = 0;
+		break;
+	case 15: /* PP graphic */
+		alp_mem_idx = 1;
+		break;
+	case 23: /* DP BG SYNC graphic */
+		alp_mem_idx = 4;
+		break;
+	case 27: /* DP FG SYNC graphic */
+		alp_mem_idx = 2;
+		break;
+	default:
+		dev_err(g_ipu_dev, "unsupported correlative channel of local "
+			"alpha channel\n");
+		return;
+	}
+
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 90, 3, alp_mem_idx);
+};
+
+static inline void _ipu_ch_param_set_interlaced_scan(uint32_t ch)
+{
+	u32 stride;
+	ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 113, 1, 1);
+	stride = ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14) + 1;
+	/* ILO is 20-bit and 8-byte aligned */
+	if (stride/8 > 0xfffff)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's ILO exceeds IPU limitation\n", ch);
+	if (stride%8)
+		dev_warn(g_ipu_dev,
+			 "IDMAC%d's ILO is not 8-byte aligned\n", ch);
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 58, 20, stride / 8);
+	stride *= 2;
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
+};
+
+static inline void _ipu_ch_param_set_high_priority(uint32_t ch)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
+};
+
+/* IDMAC U/V offset changing support */
+/* U and V input is not affected, */
+/* the update is done by new calculation according to */
+/* vertical_offset and horizontal_offset */
+static inline void _ipu_ch_offset_update(int ch,
+					uint32_t pixel_fmt,
+					uint32_t width,
+					uint32_t height,
+					uint32_t stride,
+					uint32_t u,
+					uint32_t v,
+					uint32_t uv_stride,
+					uint32_t vertical_offset,
+					uint32_t horizontal_offset)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	uint32_t u_fix = 0;
+	uint32_t v_fix = 0;
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+	case IPU_PIX_FMT_GENERIC_32:
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_ABGR32:
+	case IPU_PIX_FMT_UYVY:
+	case IPU_PIX_FMT_YUYV:
+		break;
+
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset / 2) +
+					horizontal_offset / 2;
+		v_offset = u_offset + (uv_stride * height / 2);
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset) +
+					horizontal_offset / 2;
+		u_offset = v_offset + uv_stride * height;
+		u_fix = u ? (u + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset) +
+					horizontal_offset / 2;
+		v_offset = u_offset + uv_stride * height;
+		u_fix = u ? (u + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+		break;
+
+	case IPU_PIX_FMT_NV12:
+		uv_stride = stride;
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset / 2) +
+					horizontal_offset;
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
+					horizontal_offset -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+
+		break;
+	default:
+		dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+
+
+
+	if (u_fix > u_offset)
+		u_offset = u_fix;
+
+	if (v_fix > v_offset)
+		v_offset = v_fix;
+
+	/* UBO and VBO are 22-bit and 8-byte aligned */
+	if (u_offset/8 > 0x3fffff)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's U offset exceeds IPU limitation\n", ch);
+	if (v_offset/8 > 0x3fffff)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(g_ipu_dev,
+			"IDMAC%d's V offset is not 8-byte aligned\n", ch);
+
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
+
+};
+
+static inline void _ipu_ch_params_set_alpha_width(uint32_t ch, int alpha_width)
+{
+	ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 125, 3, alpha_width - 1);
+};
+
+#endif
diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
new file mode 100644
index 000000000000..4e62b256889f
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PRV_H__
+#define __INCLUDE_IPU_PRV_H__
+
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <mach/hardware.h>
+
+/* Globals */
+extern struct device *g_ipu_dev;
+extern spinlock_t ipu_lock;
+extern bool g_ipu_clk_enabled;
+extern struct clk *g_ipu_clk;
+extern struct clk *g_di_clk[2];
+extern struct clk *g_pixel_clk[2];
+extern struct clk *g_csi_clk[2];
+extern unsigned char g_dc_di_assignment[];
+extern int g_ipu_hw_rev;
+extern int dmfc_type_setup;
+
+#define IDMA_CHAN_INVALID	0xFF
+#define HIGH_RESOLUTION_WIDTH	1024
+
+struct ipu_channel {
+	u8 video_in_dma;
+	u8 alpha_in_dma;
+	u8 graph_in_dma;
+	u8 out_dma;
+};
+
+enum ipu_dmfc_type {
+	DMFC_NORMAL = 0,
+	DMFC_HIGH_RESOLUTION_DC,
+	DMFC_HIGH_RESOLUTION_DP,
+	DMFC_HIGH_RESOLUTION_ONLY_DP,
+};
+
+int register_ipu_device(void);
+ipu_color_space_t format_to_colorspace(uint32_t fmt);
+bool ipu_pixel_format_has_alpha(uint32_t fmt);
+
+void ipu_dump_registers(void);
+
+uint32_t _ipu_channel_status(ipu_channel_t channel);
+
+void _ipu_init_dc_mappings(void);
+int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+		 uint32_t out_pixel_fmt);
+void _ipu_dp_uninit(ipu_channel_t channel);
+void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
+void _ipu_dc_uninit(int dc_chan);
+void _ipu_dp_dc_enable(ipu_channel_t channel);
+void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap);
+void _ipu_dmfc_init(int dmfc_type, int first);
+void _ipu_dmfc_set_wait4eot(int dma_chan, int width);
+int _ipu_chan_is_interlaced(ipu_channel_t channel);
+
+void _ipu_ic_enable_task(ipu_channel_t channel);
+void _ipu_ic_disable_task(ipu_channel_t channel);
+void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi);
+void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params);
+void _ipu_vdi_uninit(void);
+void _ipu_ic_uninit_prpvf(void);
+void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_vf(void);
+void _ipu_ic_init_csi(ipu_channel_params_t *params);
+void _ipu_ic_uninit_csi(void);
+void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi);
+void _ipu_ic_uninit_prpenc(void);
+void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_enc(void);
+void _ipu_ic_init_pp(ipu_channel_params_t *params);
+void _ipu_ic_uninit_pp(void);
+void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_pp(void);
+int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height,
+		      int burst_size, ipu_rotate_mode_t rot);
+void _ipu_vdi_toggle_top_field_man(void);
+int _ipu_csi_init(ipu_channel_t channel, uint32_t csi);
+void ipu_csi_set_test_generator(bool active, uint32_t r_value,
+		uint32_t g_value, uint32_t b_value,
+		uint32_t pix_clk, uint32_t csi);
+void _ipu_csi_ccir_err_detection_enable(uint32_t csi);
+void _ipu_csi_ccir_err_detection_disable(uint32_t csi);
+void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
+void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs);
+void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]);
+
+#endif				/* __INCLUDE_IPU_PRV_H__ */
diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h
new file mode 100644
index 000000000000..19fde8846aa7
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_regs.h
@@ -0,0 +1,668 @@
+/*
+ * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_regs.h
+ *
+ * @brief IPU Register definitions
+ *
+ * @ingroup IPU
+ */
+#ifndef __IPU_REGS_INCLUDED__
+#define __IPU_REGS_INCLUDED__
+
+#define IPU_DISP0_BASE		0x00000000
+#define IPU_MCU_T_DEFAULT	8
+#define IPU_DISP1_BASE		(IPU_MCU_T_DEFAULT << 25)
+#define IPU_REG_BASE		0x1E000000
+#define IPUV3M_REG_BASE		0x06000000
+
+#define IPU_CM_REG_BASE		0x00000000
+#define IPU_IDMAC_REG_BASE	0x00008000
+#define IPU_ISP_REG_BASE	0x00010000
+#define IPU_DP_REG_BASE		0x00018000
+#define IPU_IC_REG_BASE		0x00020000
+#define IPU_IRT_REG_BASE	0x00028000
+#define IPU_CSI0_REG_BASE	0x00030000
+#define IPU_CSI1_REG_BASE	0x00038000
+#define IPU_DI0_REG_BASE	0x00040000
+#define IPU_DI1_REG_BASE	0x00048000
+#define IPU_SMFC_REG_BASE	0x00050000
+#define IPU_DC_REG_BASE		0x00058000
+#define IPU_DMFC_REG_BASE	0x00060000
+#define IPU_VDI_REG_BASE	0x00068000
+#define IPU_CPMEM_REG_BASE	0x01000000
+#define IPU_LUT_REG_BASE	0x01020000
+#define IPU_SRM_REG_BASE	0x01040000
+#define IPU_TPM_REG_BASE	0x01060000
+#define IPU_DC_TMPL_REG_BASE	0x01080000
+#define IPU_ISP_TBPR_REG_BASE	0x010C0000
+
+
+extern u32 *ipu_cm_reg;
+extern u32 *ipu_idmac_reg;
+extern u32 *ipu_dp_reg;
+extern u32 *ipu_ic_reg;
+extern u32 *ipu_dc_reg;
+extern u32 *ipu_dc_tmpl_reg;
+extern u32 *ipu_dmfc_reg;
+extern u32 *ipu_di_reg[];
+extern u32 *ipu_smfc_reg;
+extern u32 *ipu_csi_reg[];
+extern u32 *ipu_tpmem_base;
+extern u32 *ipu_disp_base[];
+extern u32 *ipu_vdi_reg;
+
+/* Register addresses */
+/* IPU Common registers */
+#define IPU_CONF		(ipu_cm_reg)
+
+#define IPU_SRM_PRI1		(ipu_cm_reg + 0x00A0/4)
+#define IPU_SRM_PRI2		(ipu_cm_reg + 0x00A4/4)
+#define IPU_FS_PROC_FLOW1	(ipu_cm_reg + 0x00A8/4)
+#define IPU_FS_PROC_FLOW2	(ipu_cm_reg + 0x00AC/4)
+#define IPU_FS_PROC_FLOW3	(ipu_cm_reg + 0x00B0/4)
+#define IPU_FS_DISP_FLOW1	(ipu_cm_reg + 0x00B4/4)
+#define IPU_FS_DISP_FLOW2	(ipu_cm_reg + 0x00B8/4)
+#define IPU_SKIP		(ipu_cm_reg + 0x00BC/4)
+#define IPU_DISP_ALT_CONF	(ipu_cm_reg + 0x00C0/4)
+#define IPU_DISP_GEN		(ipu_cm_reg + 0x00C4/4)
+#define IPU_DISP_ALT1		(ipu_cm_reg + 0x00C8/4)
+#define IPU_DISP_ALT2		(ipu_cm_reg + 0x00CC/4)
+#define IPU_DISP_ALT3		(ipu_cm_reg + 0x00D0/4)
+#define IPU_DISP_ALT4		(ipu_cm_reg + 0x00D4/4)
+#define IPU_SNOOP		(ipu_cm_reg + 0x00D8/4)
+#define IPU_MEM_RST		(ipu_cm_reg + 0x00DC/4)
+#define IPU_PM			(ipu_cm_reg + 0x00E0/4)
+#define IPU_GPR			(ipu_cm_reg + 0x00E4/4)
+#define IPU_CHA_DB_MODE_SEL(ch)	(ipu_cm_reg + 0x0150/4 + (ch / 32))
+#define IPU_ALT_CHA_DB_MODE_SEL(ch) (ipu_cm_reg + 0x0168/4 + (ch / 32))
+#define IPU_CHA_CUR_BUF(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x023C/4 + (ch / 32)) : \
+				  (ipu_cm_reg + 0x0124/4 + (ch / 32)); })
+#define IPU_ALT_CUR_BUF0	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0244/4) : \
+				  (ipu_cm_reg + 0x012C/4); })
+#define IPU_ALT_CUR_BUF1	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0248/4) : \
+				  (ipu_cm_reg + 0x0130/4); })
+#define IPU_SRM_STAT		({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x024C/4) : \
+				  (ipu_cm_reg + 0x0134/4); })
+#define IPU_PROC_TASK_STAT	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0250/4) : \
+				  (ipu_cm_reg + 0x0138/4); })
+#define IPU_DISP_TASK_STAT	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0254/4) : \
+				  (ipu_cm_reg + 0x013C/4); })
+#define IPU_CHA_BUF0_RDY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0268/4 + (ch / 32)) : \
+				  (ipu_cm_reg + 0x0140/4 + (ch / 32)); })
+#define IPU_CHA_BUF1_RDY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0270/4 + (ch / 32)) : \
+				  (ipu_cm_reg + 0x0148/4 + (ch / 32)); })
+#define IPU_ALT_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
+				   (ipu_cm_reg + 0x0278/4 + (ch / 32)) : \
+				   (ipu_cm_reg + 0x0158/4 + (ch / 32)); })
+#define IPU_ALT_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
+				   (ipu_cm_reg + 0x0280/4 + (ch / 32)) : \
+				   (ipu_cm_reg + 0x0160/4 + (ch / 32)); })
+
+#define IPU_INT_CTRL(n)		(ipu_cm_reg + 0x003C/4 + ((n) - 1))
+#define IPU_INT_CTRL_IRQ(irq)	IPU_INT_CTRL(((irq) / 32))
+#define IPU_INT_STAT_IRQ(irq)	IPU_INT_STAT(((irq) / 32))
+#define IPU_INT_STAT(n)		({g_ipu_hw_rev >= 2 ? \
+				  (ipu_cm_reg + 0x0200/4 + ((n) - 1)) : \
+				  (ipu_cm_reg + 0x00E8/4 + ((n) - 1)); })
+
+#define IPUIRQ_2_STATREG(irq)	(IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_CTRLREG(irq)	(IPU_INT_CTRL(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq)	(1UL << ((irq) & 0x1F))
+
+#define VDI_FSIZE (ipu_vdi_reg)
+#define VDI_C (ipu_vdi_reg + 0x0004/4)
+
+/* CMOS Sensor Interface Registers */
+#define CSI_SENS_CONF(csi)	(ipu_csi_reg[csi])
+#define CSI_SENS_FRM_SIZE(csi)	(ipu_csi_reg[csi] + 0x0004/4)
+#define CSI_ACT_FRM_SIZE(csi)	(ipu_csi_reg[csi] + 0x0008/4)
+#define CSI_OUT_FRM_CTRL(csi)	(ipu_csi_reg[csi] + 0x000C/4)
+#define CSI_TST_CTRL(csi)	(ipu_csi_reg[csi] + 0x0010/4)
+#define CSI_CCIR_CODE_1(csi)	(ipu_csi_reg[csi] + 0x0014/4)
+#define CSI_CCIR_CODE_2(csi)	(ipu_csi_reg[csi] + 0x0018/4)
+#define CSI_CCIR_CODE_3(csi)	(ipu_csi_reg[csi] + 0x001C/4)
+#define CSI_MIPI_DI(csi)	(ipu_csi_reg[csi] + 0x0020/4)
+#define CSI_SKIP(csi)		(ipu_csi_reg[csi] + 0x0024/4)
+#define CSI_CPD_CTRL(csi)	(ipu_csi_reg[csi] + 0x0028/4)
+#define CSI_CPD_RC(csi, n)	(ipu_csi_reg[csi] + 0x002C/4 + n)
+#define CSI_CPD_RS(csi, n)	(ipu_csi_reg[csi] + 0x004C/4 + n)
+#define CSI_CPD_GRC(csi, n)	(ipu_csi_reg[csi] + 0x005C/4 + n)
+#define CSI_CPD_GRS(csi, n)	(ipu_csi_reg[csi] + 0x007C/4 + n)
+#define CSI_CPD_GBC(csi, n)	(ipu_csi_reg[csi] + 0x008C/4 + n)
+#define CSI_CPD_GBS(csi, n)	(ipu_csi_reg[csi] + 0x00AC/4 + n)
+#define CSI_CPD_BC(csi, n)	(ipu_csi_reg[csi] + 0x00BC/4 + n)
+#define CSI_CPD_BS(csi, n)	(ipu_csi_reg[csi] + 0x00DC/4 + n)
+#define CSI_CPD_OFFSET1(csi)	(ipu_csi_reg[csi] + 0x00EC/4)
+#define CSI_CPD_OFFSET2(csi)	(ipu_csi_reg[csi] + 0x00F0/4)
+
+/*SMFC Registers */
+#define SMFC_MAP	(ipu_smfc_reg)
+#define SMFC_WMC	(ipu_smfc_reg + 0x0004/4)
+#define SMFC_BS		(ipu_smfc_reg + 0x0008/4)
+
+/* Image Converter Registers */
+#define IC_CONF			(ipu_ic_reg)
+#define IC_PRP_ENC_RSC		(ipu_ic_reg + 0x0004/4)
+#define IC_PRP_VF_RSC		(ipu_ic_reg + 0x0008/4)
+#define IC_PP_RSC		(ipu_ic_reg + 0x000C/4)
+#define IC_CMBP_1		(ipu_ic_reg + 0x0010/4)
+#define IC_CMBP_2		(ipu_ic_reg + 0x0014/4)
+#define IC_IDMAC_1		(ipu_ic_reg + 0x0018/4)
+#define IC_IDMAC_2		(ipu_ic_reg + 0x001C/4)
+#define IC_IDMAC_3		(ipu_ic_reg + 0x0020/4)
+#define IC_IDMAC_4		(ipu_ic_reg + 0x0024/4)
+
+#define IDMAC_CONF		(ipu_idmac_reg + 0x0000)
+#define IDMAC_CHA_EN(ch)	(ipu_idmac_reg + 0x0004/4 + (ch/32))
+#define IDMAC_SEP_ALPHA		(ipu_idmac_reg + 0x000C/4)
+#define IDMAC_ALT_SEP_ALPHA	(ipu_idmac_reg + 0x0010/4)
+#define IDMAC_CHA_PRI(ch)	(ipu_idmac_reg + 0x0014/4 + (ch/32))
+#define IDMAC_WM_EN(ch)		(ipu_idmac_reg + 0x001C/4 + (ch/32))
+#define IDMAC_CH_LOCK_EN_1	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0024/4) : 0; })
+#define IDMAC_CH_LOCK_EN_2	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0028/4) : \
+				  (ipu_idmac_reg + 0x0024/4); })
+#define IDMAC_SUB_ADDR_0	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x002C/4) : \
+				  (ipu_idmac_reg + 0x0028/4); })
+#define IDMAC_SUB_ADDR_1	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0030/4) : \
+				  (ipu_idmac_reg + 0x002C/4); })
+#define IDMAC_SUB_ADDR_2	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0034/4) : \
+				  (ipu_idmac_reg + 0x0030/4); })
+#define IDMAC_BAND_EN(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0040/4 + (ch/32)) : \
+				  (ipu_idmac_reg + 0x0034/4 + (ch/32)); })
+#define IDMAC_CHA_BUSY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (ipu_idmac_reg + 0x0100/4 + (ch/32)) : \
+				  (ipu_idmac_reg + 0x0040/4 + (ch/32)); })
+
+#define DI_GENERAL(di)		(ipu_di_reg[di])
+#define DI_BS_CLKGEN0(di)	(ipu_di_reg[di] + 0x0004/4)
+#define DI_BS_CLKGEN1(di)	(ipu_di_reg[di] + 0x0008/4)
+
+#define DI_SW_GEN0(di, gen)	(ipu_di_reg[di] + 0x000C/4 + (gen - 1))
+#define DI_SW_GEN1(di, gen)	(ipu_di_reg[di] + 0x0030/4 + (gen - 1))
+#define DI_STP_REP(di, gen)	(ipu_di_reg[di] + 0x0148/4 + (gen - 1)/2)
+#define DI_SYNC_AS_GEN(di)	(ipu_di_reg[di] + 0x0054/4)
+#define DI_DW_GEN(di, gen)	(ipu_di_reg[di] + 0x0058/4 + gen)
+#define DI_DW_SET(di, gen, set)	(ipu_di_reg[di] + 0x0088/4 + gen + 0xC*set)
+#define DI_SER_CONF(di)		(ipu_di_reg[di] + 0x015C/4)
+#define DI_SSC(di)		(ipu_di_reg[di] + 0x0160/4)
+#define DI_POL(di)		(ipu_di_reg[di] + 0x0164/4)
+#define DI_AW0(di)		(ipu_di_reg[di] + 0x0168/4)
+#define DI_AW1(di)		(ipu_di_reg[di] + 0x016C/4)
+#define DI_SCR_CONF(di)		(ipu_di_reg[di] + 0x0170/4)
+#define DI_STAT(di)		(ipu_di_reg[di] + 0x0174/4)
+
+#define DMFC_RD_CHAN		(ipu_dmfc_reg)
+#define DMFC_WR_CHAN		(ipu_dmfc_reg + 0x0004/4)
+#define DMFC_WR_CHAN_DEF	(ipu_dmfc_reg + 0x0008/4)
+#define DMFC_DP_CHAN		(ipu_dmfc_reg + 0x000C/4)
+#define DMFC_DP_CHAN_DEF	(ipu_dmfc_reg + 0x0010/4)
+#define DMFC_GENERAL1		(ipu_dmfc_reg + 0x0014/4)
+#define DMFC_GENERAL2		(ipu_dmfc_reg + 0x0018/4)
+#define DMFC_IC_CTRL		(ipu_dmfc_reg + 0x001C/4)
+#define DMFC_STAT		(ipu_dmfc_reg + 0x0020/4)
+
+#define DC_MAP_CONF_PTR(n)	(ipu_dc_reg + 0x0108/4 + n/2)
+#define DC_MAP_CONF_VAL(n)	(ipu_dc_reg + 0x0144/4 + n/2)
+
+#define _RL_CH_2_OFFSET(ch)	((ch == 0) ? 8 : ( \
+				 (ch == 1) ? 0x24 : ( \
+				 (ch == 2) ? 0x40 : ( \
+				 (ch == 5) ? 0x64 : ( \
+				 (ch == 6) ? 0x80 : ( \
+				 (ch == 8) ? 0x9C : ( \
+				 (ch == 9) ? 0xBC : (-1))))))))
+#define DC_RL_CH(ch, evt)	(ipu_dc_reg + _RL_CH_2_OFFSET(ch)/4 + evt/2)
+
+#define DC_EVT_NF		0
+#define DC_EVT_NL		1
+#define DC_EVT_EOF		2
+#define DC_EVT_NFIELD		3
+#define DC_EVT_EOL		4
+#define DC_EVT_EOFIELD		5
+#define DC_EVT_NEW_ADDR		6
+#define DC_EVT_NEW_CHAN		7
+#define DC_EVT_NEW_DATA		8
+
+#define DC_EVT_NEW_ADDR_W_0	0
+#define DC_EVT_NEW_ADDR_W_1	1
+#define DC_EVT_NEW_CHAN_W_0	2
+#define DC_EVT_NEW_CHAN_W_1	3
+#define DC_EVT_NEW_DATA_W_0	4
+#define DC_EVT_NEW_DATA_W_1	5
+#define DC_EVT_NEW_ADDR_R_0	6
+#define DC_EVT_NEW_ADDR_R_1	7
+#define DC_EVT_NEW_CHAN_R_0	8
+#define DC_EVT_NEW_CHAN_R_1	9
+#define DC_EVT_NEW_DATA_R_0	10
+#define DC_EVT_NEW_DATA_R_1	11
+#define DC_EVEN_UGDE0 		12
+#define DC_ODD_UGDE0 		13
+#define DC_EVEN_UGDE1 		14
+#define DC_ODD_UGDE1 		15
+#define DC_EVEN_UGDE2 		16
+#define DC_ODD_UGDE2 		17
+#define DC_EVEN_UGDE3 		18
+#define DC_ODD_UGDE3 		19
+
+#define dc_ch_offset(ch) \
+({ \
+	const u8 _offset[] = { \
+		0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \
+	_offset[ch]; \
+})
+#define DC_WR_CH_CONF(ch)	(ipu_dc_reg + dc_ch_offset(ch)/4)
+#define DC_WR_CH_ADDR(ch)	(ipu_dc_reg + dc_ch_offset(ch)/4 + 4/4)
+
+#define DC_WR_CH_CONF_1		(ipu_dc_reg + 0x001C/4)
+#define DC_WR_CH_ADDR_1		(ipu_dc_reg + 0x0020/4)
+#define DC_WR_CH_CONF_5		(ipu_dc_reg + 0x005C/4)
+#define DC_WR_CH_ADDR_5		(ipu_dc_reg + 0x0060/4)
+#define DC_GEN			(ipu_dc_reg + 0x00D4/4)
+#define DC_DISP_CONF1(disp)	(ipu_dc_reg + 0x00D8/4 + disp)
+#define DC_DISP_CONF2(disp)	(ipu_dc_reg + 0x00E8/4 + disp)
+#define DC_STAT			(ipu_dc_reg + 0x01C8/4)
+#define DC_UGDE_0(evt)		(ipu_dc_reg + 0x0174/4 + evt*4)
+#define DC_UGDE_1(evt)		(ipu_dc_reg + 0x0178/4 + evt*4)
+#define DC_UGDE_2(evt)		(ipu_dc_reg + 0x017C/4 + evt*4)
+#define DC_UGDE_3(evt)		(ipu_dc_reg + 0x0180/4 + evt*4)
+
+#define DP_SYNC 0
+#define DP_ASYNC0 0x60
+#define DP_ASYNC1 0xBC
+#define DP_COM_CONF(flow)	(ipu_dp_reg + flow/4)
+#define DP_GRAPH_WIND_CTRL(flow) (ipu_dp_reg + 0x0004/4 + flow/4)
+#define DP_FG_POS(flow)		(ipu_dp_reg + 0x0008/4 + flow/4)
+#define DP_GAMMA_C(flow, i)	(ipu_dp_reg + 0x0014/4 + flow/4 + i)
+#define DP_GAMMA_S(flow, i)	(ipu_dp_reg + 0x0034/4 + flow/4 + i)
+#define DP_CSC_A_0(flow)	(ipu_dp_reg + 0x0044/4 + flow/4)
+#define DP_CSC_A_1(flow)	(ipu_dp_reg + 0x0048/4 + flow/4)
+#define DP_CSC_A_2(flow)	(ipu_dp_reg + 0x004C/4 + flow/4)
+#define DP_CSC_A_3(flow)	(ipu_dp_reg + 0x0050/4 + flow/4)
+#define DP_CSC_0(flow)		(ipu_dp_reg + 0x0054/4 + flow/4)
+#define DP_CSC_1(flow)		(ipu_dp_reg + 0x0058/4 + flow/4)
+
+enum {
+	IPU_CONF_CSI0_EN = 0x00000001,
+	IPU_CONF_CSI1_EN = 0x00000002,
+	IPU_CONF_IC_EN = 0x00000004,
+	IPU_CONF_ROT_EN = 0x00000008,
+	IPU_CONF_ISP_EN = 0x00000010,
+	IPU_CONF_DP_EN = 0x00000020,
+	IPU_CONF_DI0_EN = 0x00000040,
+	IPU_CONF_DI1_EN = 0x00000080,
+	IPU_CONF_DMFC_EN = 0x00000400,
+	IPU_CONF_SMFC_EN = 0x00000100,
+	IPU_CONF_DC_EN = 0x00000200,
+	IPU_CONF_VDI_EN = 0x00001000,
+	IPU_CONF_IDMAC_DIS = 0x00400000,
+	IPU_CONF_IC_DMFC_SEL = 0x02000000,
+	IPU_CONF_IC_DMFC_SYNC = 0x04000000,
+	IPU_CONF_VDI_DMFC_SYNC = 0x08000000,
+	IPU_CONF_CSI0_DATA_SOURCE = 0x10000000,
+	IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28,
+	IPU_CONF_CSI1_DATA_SOURCE = 0x20000000,
+	IPU_CONF_IC_INPUT = 0x40000000,
+	IPU_CONF_CSI_SEL = 0x80000000,
+
+	DI0_COUNTER_RELEASE = 0x01000000,
+	DI1_COUNTER_RELEASE = 0x02000000,
+
+	FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00,
+	FS_PRPVF_ROT_SRC_SEL_OFFSET = 8,
+	FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F,
+	FS_PRPENC_ROT_SRC_SEL_OFFSET = 0,
+	FS_PP_ROT_SRC_SEL_MASK = 0x000F0000,
+	FS_PP_ROT_SRC_SEL_OFFSET = 16,
+	FS_PP_SRC_SEL_MASK = 0x0000F000,
+	FS_PP_SRC_SEL_OFFSET = 12,
+	FS_PRP_SRC_SEL_MASK = 0x0F000000,
+	FS_PRP_SRC_SEL_OFFSET = 24,
+	FS_VF_IN_VALID = 0x80000000,
+	FS_ENC_IN_VALID = 0x40000000,
+	FS_VDI_SRC_SEL_MASK = 0x30000000,
+	FS_VDI_SRC_SEL_OFFSET = 28,
+
+
+	FS_PRPENC_DEST_SEL_MASK = 0x0000000F,
+	FS_PRPENC_DEST_SEL_OFFSET = 0,
+	FS_PRPVF_DEST_SEL_MASK = 0x000000F0,
+	FS_PRPVF_DEST_SEL_OFFSET = 4,
+	FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00,
+	FS_PRPVF_ROT_DEST_SEL_OFFSET = 8,
+	FS_PP_DEST_SEL_MASK = 0x0000F000,
+	FS_PP_DEST_SEL_OFFSET = 12,
+	FS_PP_ROT_DEST_SEL_MASK = 0x000F0000,
+	FS_PP_ROT_DEST_SEL_OFFSET = 16,
+	FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000,
+	FS_PRPENC_ROT_DEST_SEL_OFFSET = 20,
+
+	FS_SMFC0_DEST_SEL_MASK = 0x0000000F,
+	FS_SMFC0_DEST_SEL_OFFSET = 0,
+	FS_SMFC1_DEST_SEL_MASK = 0x00000070,
+	FS_SMFC1_DEST_SEL_OFFSET = 4,
+	FS_SMFC2_DEST_SEL_MASK = 0x00000780,
+	FS_SMFC2_DEST_SEL_OFFSET = 7,
+	FS_SMFC3_DEST_SEL_MASK = 0x00003800,
+	FS_SMFC3_DEST_SEL_OFFSET = 11,
+
+	FS_DC1_SRC_SEL_MASK = 0x00F00000,
+	FS_DC1_SRC_SEL_OFFSET = 20,
+	FS_DC2_SRC_SEL_MASK = 0x000F0000,
+	FS_DC2_SRC_SEL_OFFSET = 16,
+	FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F,
+	FS_DP_SYNC0_SRC_SEL_OFFSET = 0,
+	FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0,
+	FS_DP_SYNC1_SRC_SEL_OFFSET = 4,
+	FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00,
+	FS_DP_ASYNC0_SRC_SEL_OFFSET = 8,
+	FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000,
+	FS_DP_ASYNC1_SRC_SEL_OFFSET = 12,
+
+	FS_AUTO_REF_PER_MASK = 0,
+	FS_AUTO_REF_PER_OFFSET = 16,
+
+	TSTAT_VF_MASK = 0x0000000C,
+	TSTAT_VF_OFFSET = 2,
+	TSTAT_VF_ROT_MASK = 0x00000300,
+	TSTAT_VF_ROT_OFFSET = 8,
+	TSTAT_ENC_MASK = 0x00000003,
+	TSTAT_ENC_OFFSET = 0,
+	TSTAT_ENC_ROT_MASK = 0x000000C0,
+	TSTAT_ENC_ROT_OFFSET = 6,
+	TSTAT_PP_MASK = 0x00000030,
+	TSTAT_PP_OFFSET = 4,
+	TSTAT_PP_ROT_MASK = 0x00000C00,
+	TSTAT_PP_ROT_OFFSET = 10,
+
+	TASK_STAT_IDLE = 0,
+	TASK_STAT_ACTIVE = 1,
+	TASK_STAT_WAIT4READY = 2,
+
+	/* Image Converter Register bits */
+	IC_CONF_PRPENC_EN = 0x00000001,
+	IC_CONF_PRPENC_CSC1 = 0x00000002,
+	IC_CONF_PRPENC_ROT_EN = 0x00000004,
+	IC_CONF_PRPVF_EN = 0x00000100,
+	IC_CONF_PRPVF_CSC1 = 0x00000200,
+	IC_CONF_PRPVF_CSC2 = 0x00000400,
+	IC_CONF_PRPVF_CMB = 0x00000800,
+	IC_CONF_PRPVF_ROT_EN = 0x00001000,
+	IC_CONF_PP_EN = 0x00010000,
+	IC_CONF_PP_CSC1 = 0x00020000,
+	IC_CONF_PP_CSC2 = 0x00040000,
+	IC_CONF_PP_CMB = 0x00080000,
+	IC_CONF_PP_ROT_EN = 0x00100000,
+	IC_CONF_IC_GLB_LOC_A = 0x10000000,
+	IC_CONF_KEY_COLOR_EN = 0x20000000,
+	IC_CONF_RWS_EN = 0x40000000,
+	IC_CONF_CSI_MEM_WR_EN = 0x80000000,
+
+	IC_IDMAC_1_CB0_BURST_16 = 0x00000001,
+	IC_IDMAC_1_CB1_BURST_16 = 0x00000002,
+	IC_IDMAC_1_CB2_BURST_16 = 0x00000004,
+	IC_IDMAC_1_CB3_BURST_16 = 0x00000008,
+	IC_IDMAC_1_CB4_BURST_16 = 0x00000010,
+	IC_IDMAC_1_CB5_BURST_16 = 0x00000020,
+	IC_IDMAC_1_CB6_BURST_16 = 0x00000040,
+	IC_IDMAC_1_CB7_BURST_16 = 0x00000080,
+	IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800,
+	IC_IDMAC_1_PRPENC_ROT_OFFSET = 11,
+	IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000,
+	IC_IDMAC_1_PRPVF_ROT_OFFSET = 14,
+	IC_IDMAC_1_PP_ROT_MASK = 0x000E0000,
+	IC_IDMAC_1_PP_ROT_OFFSET = 17,
+	IC_IDMAC_1_PP_FLIP_RS = 0x00400000,
+	IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000,
+	IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000,
+
+	IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF,
+	IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0,
+	IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00,
+	IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10,
+	IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000,
+	IC_IDMAC_2_PP_HEIGHT_OFFSET = 20,
+
+	IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF,
+	IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0,
+	IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00,
+	IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10,
+	IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000,
+	IC_IDMAC_3_PP_WIDTH_OFFSET = 20,
+
+	CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
+	CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700,
+	CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L,
+	CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L,
+	CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L,
+	CSI_SENS_CONF_DATA_FMT_BAYER = 3L,
+	CSI_SENS_CONF_DATA_FMT_RGB565 = 4L,
+	CSI_SENS_CONF_DATA_FMT_RGB555 = 5L,
+	CSI_SENS_CONF_DATA_FMT_RGB444 = 6L,
+	CSI_SENS_CONF_DATA_FMT_JPEG = 7L,
+
+	CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
+	CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
+	CSI_SENS_CONF_DATA_POL_SHIFT = 2,
+	CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
+	CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
+	CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7,
+	CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11,
+	CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
+	CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
+
+	CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L,
+	CSI_SENS_CONF_DATA_DEST_SHIFT = 24,
+	CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L,
+	CSI_SENS_CONF_JPEG8_EN_SHIFT = 27,
+	CSI_SENS_CONF_JPEG_EN_SHIFT = 28,
+	CSI_SENS_CONF_FORCE_EOF_SHIFT = 29,
+	CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31,
+
+	CSI_DATA_DEST_ISP = 1L,
+	CSI_DATA_DEST_IC = 2L,
+	CSI_DATA_DEST_IDMAC = 4L,
+
+	CSI_CCIR_ERR_DET_EN = 0x01000000L,
+	CSI_HORI_DOWNSIZE_EN = 0x80000000L,
+	CSI_VERT_DOWNSIZE_EN = 0x40000000L,
+	CSI_TEST_GEN_MODE_EN = 0x01000000L,
+
+	CSI_HSC_MASK = 0x1FFF0000,
+	CSI_HSC_SHIFT = 16,
+	CSI_VSC_MASK = 0x00000FFF,
+	CSI_VSC_SHIFT = 0,
+
+	CSI_TEST_GEN_R_MASK = 0x000000FFL,
+	CSI_TEST_GEN_R_SHIFT = 0,
+	CSI_TEST_GEN_G_MASK = 0x0000FF00L,
+	CSI_TEST_GEN_G_SHIFT = 8,
+	CSI_TEST_GEN_B_MASK = 0x00FF0000L,
+	CSI_TEST_GEN_B_SHIFT = 16,
+
+	CSI_MIPI_DI0_MASK = 0x000000FFL,
+	CSI_MIPI_DI0_SHIFT = 0,
+	CSI_MIPI_DI1_MASK = 0x0000FF00L,
+	CSI_MIPI_DI1_SHIFT = 8,
+	CSI_MIPI_DI2_MASK = 0x00FF0000L,
+	CSI_MIPI_DI2_SHIFT = 16,
+	CSI_MIPI_DI3_MASK = 0xFF000000L,
+	CSI_MIPI_DI3_SHIFT = 24,
+
+	CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L,
+	CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16,
+	CSI_SKIP_ISP_MASK = 0x00F80000L,
+	CSI_SKIP_ISP_SHIFT = 19,
+	CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L,
+	CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0,
+	CSI_SKIP_SMFC_MASK = 0x000000F8L,
+	CSI_SKIP_SMFC_SHIFT = 3,
+	CSI_ID_2_SKIP_MASK = 0x00000300L,
+	CSI_ID_2_SKIP_SHIFT = 8,
+
+	CSI_COLOR_FIRST_ROW_MASK = 0x00000002L,
+	CSI_COLOR_FIRST_COMP_MASK = 0x00000001L,
+
+	SMFC_MAP_CH0_MASK = 0x00000007L,
+	SMFC_MAP_CH0_SHIFT = 0,
+	SMFC_MAP_CH1_MASK = 0x00000038L,
+	SMFC_MAP_CH1_SHIFT = 3,
+	SMFC_MAP_CH2_MASK = 0x000001C0L,
+	SMFC_MAP_CH2_SHIFT = 6,
+	SMFC_MAP_CH3_MASK = 0x00000E00L,
+	SMFC_MAP_CH3_SHIFT = 9,
+
+	SMFC_WM0_SET_MASK = 0x00000007L,
+	SMFC_WM0_SET_SHIFT = 0,
+	SMFC_WM1_SET_MASK = 0x000001C0L,
+	SMFC_WM1_SET_SHIFT = 6,
+	SMFC_WM2_SET_MASK = 0x00070000L,
+	SMFC_WM2_SET_SHIFT = 16,
+	SMFC_WM3_SET_MASK = 0x01C00000L,
+	SMFC_WM3_SET_SHIFT = 22,
+
+	SMFC_WM0_CLR_MASK = 0x00000038L,
+	SMFC_WM0_CLR_SHIFT = 3,
+	SMFC_WM1_CLR_MASK = 0x00000E00L,
+	SMFC_WM1_CLR_SHIFT = 9,
+	SMFC_WM2_CLR_MASK = 0x00380000L,
+	SMFC_WM2_CLR_SHIFT = 19,
+	SMFC_WM3_CLR_MASK = 0x0E000000L,
+	SMFC_WM3_CLR_SHIFT = 25,
+
+	SMFC_BS0_MASK = 0x0000000FL,
+	SMFC_BS0_SHIFT = 0,
+	SMFC_BS1_MASK = 0x000000F0L,
+	SMFC_BS1_SHIFT = 4,
+	SMFC_BS2_MASK = 0x00000F00L,
+	SMFC_BS2_SHIFT = 8,
+	SMFC_BS3_MASK = 0x0000F000L,
+	SMFC_BS3_SHIFT = 12,
+
+	PF_CONF_TYPE_MASK = 0x00000007,
+	PF_CONF_TYPE_SHIFT = 0,
+	PF_CONF_PAUSE_EN = 0x00000010,
+	PF_CONF_RESET = 0x00008000,
+	PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
+	PF_CONF_PAUSE_ROW_SHIFT = 16,
+
+	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
+	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
+
+	DI_GEN_DI_CLK_EXT = 0x100000,
+	DI_GEN_POLARITY_1 = 0x00000001,
+	DI_GEN_POLARITY_2 = 0x00000002,
+	DI_GEN_POLARITY_3 = 0x00000004,
+	DI_GEN_POLARITY_4 = 0x00000008,
+	DI_GEN_POLARITY_5 = 0x00000010,
+	DI_GEN_POLARITY_6 = 0x00000020,
+	DI_GEN_POLARITY_7 = 0x00000040,
+	DI_GEN_POLARITY_8 = 0x00000080,
+
+	DI_POL_DRDY_DATA_POLARITY = 0x00000080,
+	DI_POL_DRDY_POLARITY_15 = 0x00000010,
+
+	DI_VSYNC_SEL_OFFSET = 13,
+
+	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
+	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
+	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
+	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
+	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
+	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
+
+	DC_UGDE_0_ODD_EN = 0x02000000,
+	DC_UGDE_0_ID_CODED_MASK = 0x00000007,
+	DC_UGDE_0_ID_CODED_OFFSET = 0,
+	DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078,
+	DC_UGDE_0_EV_PRIORITY_OFFSET = 3,
+
+	DP_COM_CONF_FG_EN = 0x00000001,
+	DP_COM_CONF_GWSEL = 0x00000002,
+	DP_COM_CONF_GWAM = 0x00000004,
+	DP_COM_CONF_GWCKE = 0x00000008,
+	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
+	DP_COM_CONF_CSC_DEF_OFFSET = 8,
+	DP_COM_CONF_CSC_DEF_FG = 0x00000300,
+	DP_COM_CONF_CSC_DEF_BG = 0x00000200,
+	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
+	DP_COM_CONF_GAMMA_EN = 0x00001000,
+	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
+
+	DI_SER_CONF_LLA_SER_ACCESS = 0x00000020,
+	DI_SER_CONF_SERIAL_CLK_POL = 0x00000010,
+	DI_SER_CONF_SERIAL_DATA_POL = 0x00000008,
+	DI_SER_CONF_SERIAL_RS_POL = 0x00000004,
+	DI_SER_CONF_SERIAL_CS_POL = 0x00000002,
+	DI_SER_CONF_WAIT4SERIAL = 0x00000001,
+
+	VDI_C_CH_420 = 0x00000000,
+	VDI_C_CH_422 = 0x00000002,
+	VDI_C_MOT_SEL_FULL = 0x00000008,
+	VDI_C_MOT_SEL_LOW = 0x00000004,
+	VDI_C_MOT_SEL_MED = 0x00000000,
+	VDI_C_BURST_SIZE1_4 = 0x00000030,
+	VDI_C_BURST_SIZE2_4 = 0x00000300,
+	VDI_C_BURST_SIZE3_4 = 0x00003000,
+	VDI_C_VWM1_SET_1 = 0x00000000,
+	VDI_C_VWM1_CLR_2 = 0x00080000,
+	VDI_C_VWM3_SET_1 = 0x00000000,
+	VDI_C_VWM3_CLR_2 = 0x02000000,
+	VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
+	VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
+
+	DMFC_FIFO_SIZE_5F = 0x00003800,
+};
+
+enum di_pins {
+	DI_PIN11 = 0,
+	DI_PIN12 = 1,
+	DI_PIN13 = 2,
+	DI_PIN14 = 3,
+	DI_PIN15 = 4,
+	DI_PIN16 = 5,
+	DI_PIN17 = 6,
+	DI_PIN_CS = 7,
+
+	DI_PIN_SER_CLK = 0,
+	DI_PIN_SER_RS = 1,
+};
+
+enum di_sync_wave {
+	DI_SYNC_NONE = -1,
+	DI_SYNC_CLK = 0,
+	DI_SYNC_INT_HSYNC = 1,
+	DI_SYNC_HSYNC = 2,
+	DI_SYNC_VSYNC = 3,
+	DI_SYNC_DE = 5,
+};
+
+/* DC template opcodes */
+#define WROD(lf)		(0x18 | (lf << 1))
+
+#endif
diff --git a/drivers/mxc/mcu_pmic/Kconfig b/drivers/mxc/mcu_pmic/Kconfig
new file mode 100644
index 000000000000..cb6815e92d86
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/Kconfig
@@ -0,0 +1,17 @@
+#
+# PMIC Modules configuration
+#
+
+config MXC_PMIC_MC9S08DZ60
+	tristate "MC9S08DZ60 PMIC"
+	depends on ARCH_MXC && I2C
+	  ---help---
+	  This is the MXC MC9S08DZ60(MCU) PMIC support.
+
+config MXC_MC9SDZ60_RTC
+	tristate "MC9SDZ60 Real Time Clock (RTC) support"
+	depends on MXC_PMIC_MC9SDZ60
+	---help---
+	This is the MC9SDZ60 RTC module driver. This module provides kernel API
+	for RTC part of MC9SDZ60.
+	If you want MC9SDZ60 RTC support, you should say Y here
diff --git a/drivers/mxc/mcu_pmic/Makefile b/drivers/mxc/mcu_pmic/Makefile
new file mode 100644
index 000000000000..96aae94d5290
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the mc9sdz60 pmic drivers.
+#
+
+obj-$(CONFIG_MXC_PMIC_MC9SDZ60) += pmic_mc9sdz60_mod.o
+pmic_mc9sdz60_mod-objs := mcu_pmic_core.o max8660.o mc9s08dz60.o mcu_pmic_gpio.o
diff --git a/drivers/mxc/mcu_pmic/max8660.c b/drivers/mxc/mcu_pmic/max8660.c
new file mode 100644
index 000000000000..f48899f212f9
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/max8660.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file max8660.c
+ * @brief Driver for max8660
+ *
+ * @ingroup pmic
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/proc_fs.h>
+#include <linux/i2c.h>
+#include <linux/mfd/mc9s08dz60/pmic.h>
+#include <asm/uaccess.h>
+#include "mcu_pmic_core.h"
+#include "max8660.h"
+
+/* I2C bus id and device address of mcu */
+#define I2C1_BUS	0
+#define MAX8660_I2C_ADDR				0x68
+
+static struct i2c_client *max8660_i2c_client;
+
+    /* reg names for max8660
+       REG_MAX8660_OUTPUT_ENABLE_1,
+       REG_MAX8660_OUTPUT_ENABLE_2,
+       REG_MAX8660_VOLT__CHANGE_1,
+       REG_MAX8660_V3_TARGET_VOLT_1,
+       REG_MAX8660_V3_TARGET_VOLT_2,
+       REG_MAX8660_V4_TARGET_VOLT_1,
+       REG_MAX8660_V4_TARGET_VOLT_2,
+       REG_MAX8660_V5_TARGET_VOLT_1,
+       REG_MAX8660_V5_TARGET_VOLT_2,
+       REG_MAX8660_V6V7_TARGET_VOLT,
+       REG_MAX8660_FORCE_PWM
+     */
+
+    /* save down the reg values for the device is write only */
+static u8 max8660_reg_value_table[] =
+    { 0x0, 0x0, 0x0, 0x17, 0x17, 0x1F, 0x1F, 0x04, 0x04, 0x0, 0x0
+};
+static int max8660_dev_present;
+
+int is_max8660_present(void)
+{
+	return max8660_dev_present;
+}
+
+int max8660_get_buffered_reg_val(int reg_name, u8 *value)
+{
+	if (!max8660_dev_present)
+		return -1;
+	/* outof range */
+	if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1
+	    || reg_name > REG_MAX8660_FORCE_PWM)
+		return -1;
+	*value =
+	    max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1];
+	return 0;
+}
+int max8660_save_buffered_reg_val(int reg_name, u8 value)
+{
+
+	/* outof range */
+	if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1
+	    || reg_name > REG_MAX8660_FORCE_PWM)
+		return -1;
+	max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1] = value;
+	return 0;
+}
+
+int max8660_write_reg(u8 reg, u8 value)
+{
+	if (max8660_dev_present && (i2c_smbus_write_byte_data(
+		max8660_i2c_client, reg, value) >= 0))
+		return 0;
+	return -1;
+}
+
+/*!
+ * max8660 I2C attach function
+ *
+ * @param adapter            struct i2c_client *
+ * @return  0 for max8660 successfully detected
+ */
+static int max8660_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int retval;
+	max8660_i2c_client = client;
+	retval = i2c_smbus_write_byte_data(max8660_i2c_client,
+				MAX8660_OUTPUT_ENABLE_1, 0);
+	if (retval == 0) {
+		max8660_dev_present = 1;
+		pr_info("max8660 probed !\n");
+	} else {
+		max8660_dev_present = 0;
+		pr_info("max8660 not detected!\n");
+	}
+	return retval;
+}
+
+/*!
+ * max8660 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  0
+ */
+static int max8660_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id max8660_id[] = {
+	{ "max8660", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, max8660_id);
+
+static struct i2c_driver max8660_i2c_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "max8660",},
+	.probe = max8660_probe,
+	.remove = max8660_remove,
+	.id_table = max8660_id,
+};
+
+/* called by pmic core when init*/
+int max8660_init(void)
+{
+	int err;
+	err = i2c_add_driver(&max8660_i2c_driver);
+	return err;
+}
+void max8660_exit(void)
+{
+	i2c_del_driver(&max8660_i2c_driver);
+}
diff --git a/drivers/mxc/mcu_pmic/max8660.h b/drivers/mxc/mcu_pmic/max8660.h
new file mode 100644
index 000000000000..567784611d80
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/max8660.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file max8660.h
+ * @brief Driver for max8660
+ *
+ * @ingroup pmic
+ */
+#ifndef _MAX8660_H_
+#define _MAX8660_H_
+
+#ifdef __KERNEL__
+
+#define MAX8660_OUTPUT_ENABLE_1	0x10
+#define MAX8660_OUTPUT_ENABLE_2	0x12
+#define MAX8660_VOLT_CHANGE_CONTROL		0x20
+#define MAX8660_V3_TARGET_VOLT_1	0x23
+#define MAX8660_V3_TARGET_VOLT_2	0x24
+#define MAX8660_V4_TARGET_VOLT_1	0x29
+#define MAX8660_V4_TARGET_VOLT_2	0x2A
+#define MAX8660_V5_TARGET_VOLT_1	0x32
+#define MAX8660_V5_TARGET_VOLT_2	0x33
+#define MAX8660_V6V7_TARGET_VOLT	0x39
+#define MAX8660_FORCE_PWM			0x80
+
+int is_max8660_present(void);
+int max8660_write_reg(u8 reg, u8 value);
+int max8660_save_buffered_reg_val(int reg_name, u8 value);
+int max8660_get_buffered_reg_val(int reg_name, u8 *value);
+int max8660_init(void);
+void max8660_exit(void);
+
+extern int reg_max8660_probe(void);
+extern int reg_max8660_remove(void);
+
+#endif				/* __KERNEL__ */
+
+#endif				/* _MAX8660_H_ */
diff --git a/drivers/mxc/mcu_pmic/mc9s08dz60.c b/drivers/mxc/mcu_pmic/mc9s08dz60.c
new file mode 100644
index 000000000000..1e5da6319b12
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/mc9s08dz60.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+    /*!
+     * @file mc9s08dz60.c
+     * @brief Driver for MC9sdz60
+     *
+     * @ingroup pmic
+     */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/proc_fs.h>
+#include <linux/i2c.h>
+#include <linux/mfd/mc9s08dz60/core.h>
+
+#include <mach/clock.h>
+#include <linux/uaccess.h>
+#include "mc9s08dz60.h"
+
+/* I2C bus id and device address of mcu */
+#define I2C1_BUS	0
+#define MC9S08DZ60_I2C_ADDR	0xD2	/* 7bits I2C address */
+static struct i2c_client *mc9s08dz60_i2c_client;
+
+int mc9s08dz60_read_reg(u8 reg, u8 *value)
+{
+	*value = (u8) i2c_smbus_read_byte_data(mc9s08dz60_i2c_client, reg);
+	return 0;
+}
+
+int mc9s08dz60_write_reg(u8 reg, u8 value)
+{
+	if (i2c_smbus_write_byte_data(mc9s08dz60_i2c_client, reg, value) < 0)
+		return -1;
+	return 0;
+}
+
+static ssize_t mc9s08dz60_show(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	unsigned int i;
+	u8 value;
+	int offset = 7;
+
+	for (i = 0; i < 7; i++) {
+		mc9s08dz60_read_reg(i, &value);
+		pr_info("reg%02x: %02x\t", i, value);
+		mc9s08dz60_read_reg(i + offset, &value);
+		pr_info("reg%02x: %02x\t", i + offset, value);
+		mc9s08dz60_read_reg(i + offset * 2, &value);
+		pr_info("reg%02x: %02x\t", i + offset * 2, value);
+		mc9s08dz60_read_reg(i + offset * 3, &value);
+		pr_info("reg%02x: %02x\t", i + offset * 3, value);
+		mc9s08dz60_read_reg(i + offset * 4, &value);
+		pr_info("reg%02x: %02x\t", i + offset * 4, value);
+		mc9s08dz60_read_reg(i + offset * 5, &value);
+		pr_info("reg%02x: %02x\n", i + offset * 5, value);
+	}
+
+	return 0;
+}
+
+static ssize_t mc9s08dz60_store(struct device *dev,
+			     struct device_attribute *attr, const char *buf,
+			     size_t count)
+{
+	int ret;
+	unsigned long reg, new_value;
+	u8 value;
+	char *p;
+
+	strict_strtoul(buf, 16, &reg);
+
+	p = NULL;
+	p = memchr(buf, ' ', count);
+
+	if (p == NULL) {
+		mc9s08dz60_read_reg(reg, &value);
+		pr_info("reg%02lu: %06x\n", reg, value);
+		return count;
+	}
+
+	p += 1;
+
+	strict_strtoul(p, 16, &new_value);
+	value = new_value;
+
+	ret = mc9s08dz60_write_reg((u8)reg, value);
+	if (ret == 0)
+		pr_info("write reg%02lx: %06x\n", reg, value);
+	else
+		pr_info("register update failed\n");
+
+	return count;
+}
+
+static struct device_attribute mc9s08dz60_dev_attr = {
+	.attr = {
+		 .name = "mc9s08dz60_ctl",
+		 .mode = S_IRUSR | S_IWUSR,
+		 },
+	.show = mc9s08dz60_show,
+	.store = mc9s08dz60_store,
+};
+
+
+/*!
+ * mc9s08dz60 I2C attach function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  0
+ */
+static int mc9s08dz60_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int ret = 0;
+	struct mc9s08dz60 *mc9s08dz60 = NULL;
+	struct mc9s08dz60_platform_data *plat_data = client->dev.platform_data;
+	pr_info("mc9s08dz60 probing .... \n");
+
+	mc9s08dz60 = kzalloc(sizeof(struct mc9s08dz60), GFP_KERNEL);
+	if (mc9s08dz60 == NULL)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, mc9s08dz60);
+	mc9s08dz60->dev = &client->dev;
+	mc9s08dz60->i2c_client = client;
+
+	if (plat_data && plat_data->init) {
+		ret = plat_data->init(mc9s08dz60);
+		if (ret != 0)
+			return -1;
+	}
+
+	ret = device_create_file(&client->dev, &mc9s08dz60_dev_attr);
+	if (ret)
+		dev_err(&client->dev, "create device file failed!\n");
+
+
+	mc9s08dz60_i2c_client = client;
+
+	return 0;
+}
+
+/*!
+ * mc9s08dz60 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  0
+ */
+static int mc9s08dz60_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id mc9s08dz60_id[] = {
+	{ "mc9s08dz60", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id);
+
+static struct i2c_driver mc9s08dz60_i2c_driver = {
+	.driver = {.owner = THIS_MODULE,
+		   .name = "mc9s08dz60",
+		   },
+	.probe = mc9s08dz60_probe,
+	.remove = mc9s08dz60_remove,
+	.id_table = mc9s08dz60_id,
+};
+
+#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos))
+#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos))
+
+int mc9s08dz60_init(void)
+{
+	int err;
+	err = i2c_add_driver(&mc9s08dz60_i2c_driver);
+	return err;
+}
+void mc9s08dz60_exit(void)
+{
+	i2c_del_driver(&mc9s08dz60_i2c_driver);
+}
diff --git a/drivers/mxc/mcu_pmic/mc9s08dz60.h b/drivers/mxc/mcu_pmic/mc9s08dz60.h
new file mode 100644
index 000000000000..28b8746eeb12
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/mc9s08dz60.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc9s08dz60.h
+ * @brief Driver for mc9s08dz60
+ *
+ * @ingroup pmic
+ */
+#ifndef _MC9SDZ60_H_
+#define _MC9SDZ60_H_
+
+#define MCU_VERSION	0x00
+/*#define Reserved	0x01*/
+#define MCU_SECS		0x02
+#define MCU_MINS		0x03
+#define MCU_HRS			0x04
+#define MCU_DAY			0x05
+#define MCU_DATE		0x06
+#define MCU_MONTH		0x07
+#define MCU_YEAR		0x08
+
+#define MCU_ALARM_SECS	0x09
+#define MCU_ALARM_MINS	0x0A
+#define MCU_ALARM_HRS	0x0B
+/* #define Reserved	0x0C*/
+/* #define Reserved	0x0D*/
+#define MCU_TS_CONTROL	0x0E
+#define MCU_X_LOW	0x0F
+#define MCU_Y_LOW	0x10
+#define MCU_XY_HIGH	0x11
+#define MCU_X_LEFT_LOW	0x12
+#define MCU_X_LEFT_HIGH	0x13
+#define MCU_X_RIGHT	0x14
+#define MCU_Y_TOP_LOW	0x15
+#define MCU_Y_TOP_HIGH	0x16
+#define MCU_Y_BOTTOM	0x17
+/* #define Reserved	0x18*/
+/* #define Reserved	0x19*/
+#define MCU_RESET_1	0x1A
+#define MCU_RESET_2	0x1B
+#define MCU_POWER_CTL	0x1C
+#define MCU_DELAY_CONFIG	0x1D
+/* #define Reserved	0x1E */
+/* #define Reserved	0x1F */
+#define MCU_GPIO_1	0x20
+#define MCU_GPIO_2	0x21
+#define MCU_KPD_1	0x22
+#define MCU_KPD_2	0x23
+#define MCU_KPD_CONTROL	0x24
+#define MCU_INT_ENABLE_1	0x25
+#define MCU_INT_ENABLE_2	0x26
+#define MCU_INT_FLAG_1	0x27
+#define MCU_INT_FLAG_2	0x28
+#define MCU_DES_FLAG		0x29
+int mc9s08dz60_read_reg(u8 reg, u8 *value);
+int mc9s08dz60_write_reg(u8 reg, u8 value);
+int mc9s08dz60_init(void);
+void mc9s08dz60_exit(void);
+
+extern int reg_mc9s08dz60_probe(void);
+extern int reg_mc9s08dz60_remove(void);
+
+#endif	/* _MC9SDZ60_H_ */
diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_core.c b/drivers/mxc/mcu_pmic/mcu_pmic_core.c
new file mode 100644
index 000000000000..55b2f5fe6e3e
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/mcu_pmic_core.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc9s08dz60/mcu_pmic_core.c
+ * @brief This is the main file of mc9s08dz60 Power Control driver.
+ *
+ * @ingroup PMIC_POWER
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mfd/mc9s08dz60/pmic.h>
+#include <asm/ioctl.h>
+#include <asm/uaccess.h>
+#include <mach/gpio.h>
+
+#include "mcu_pmic_core.h"
+#include "mc9s08dz60.h"
+#include "max8660.h"
+
+/* bitfield macros for mcu pmic*/
+#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos))
+#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos))
+
+
+/* map reg names (enum pmic_reg in pmic_external.h) to real addr*/
+const static u8 mcu_pmic_reg_addr_table[] = {
+	MCU_VERSION,
+	MCU_SECS,
+	MCU_MINS,
+	MCU_HRS,
+	MCU_DAY,
+	MCU_DATE,
+	MCU_MONTH,
+	MCU_YEAR,
+	MCU_ALARM_SECS,
+	MCU_ALARM_MINS,
+	MCU_ALARM_HRS,
+	MCU_TS_CONTROL,
+	MCU_X_LOW,
+	MCU_Y_LOW,
+	MCU_XY_HIGH,
+	MCU_X_LEFT_LOW,
+	MCU_X_LEFT_HIGH,
+	MCU_X_RIGHT,
+	MCU_Y_TOP_LOW,
+	MCU_Y_TOP_HIGH,
+	MCU_Y_BOTTOM,
+	MCU_RESET_1,
+	MCU_RESET_2,
+	MCU_POWER_CTL,
+	MCU_DELAY_CONFIG,
+	MCU_GPIO_1,
+	MCU_GPIO_2,
+	MCU_KPD_1,
+	MCU_KPD_2,
+	MCU_KPD_CONTROL,
+	MCU_INT_ENABLE_1,
+	MCU_INT_ENABLE_2,
+	MCU_INT_FLAG_1,
+	MCU_INT_FLAG_2,
+	MCU_DES_FLAG,
+	MAX8660_OUTPUT_ENABLE_1,
+	MAX8660_OUTPUT_ENABLE_2,
+	MAX8660_VOLT_CHANGE_CONTROL,
+	MAX8660_V3_TARGET_VOLT_1,
+	MAX8660_V3_TARGET_VOLT_2,
+	MAX8660_V4_TARGET_VOLT_1,
+	MAX8660_V4_TARGET_VOLT_2,
+	MAX8660_V5_TARGET_VOLT_1,
+	MAX8660_V5_TARGET_VOLT_2,
+	MAX8660_V6V7_TARGET_VOLT,
+	MAX8660_FORCE_PWM
+};
+
+static int mcu_pmic_read(int reg_num, unsigned int *reg_val)
+{
+	int ret;
+	u8 value = 0;
+	/* mcu ops */
+	if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG)
+		ret = mc9s08dz60_read_reg(mcu_pmic_reg_addr_table[reg_num],
+					&value);
+	else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1
+		   && reg_num <= REG_MAX8660_FORCE_PWM)
+		ret = max8660_get_buffered_reg_val(reg_num, &value);
+	else
+		return -1;
+
+	if (ret < 0)
+		return -1;
+	*reg_val = value;
+
+	return 0;
+}
+
+static int mcu_pmic_write(int reg_num, const unsigned int reg_val)
+{
+	int ret;
+	u8 value = reg_val;
+	/* mcu ops */
+	if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG) {
+
+		ret =
+		    mc9s08dz60_write_reg(
+			mcu_pmic_reg_addr_table[reg_num], value);
+		if (ret < 0)
+			return -1;
+	} else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1
+		   && reg_num <= REG_MAX8660_FORCE_PWM) {
+		ret =
+		    max8660_write_reg(mcu_pmic_reg_addr_table[reg_num], value);
+
+		if (ret < 0)
+			return -1;
+
+		ret = max8660_save_buffered_reg_val(reg_num, value);
+	} else
+		return -1;
+
+	return 0;
+}
+
+int mcu_pmic_read_reg(int reg, unsigned int *reg_value,
+			  unsigned int reg_mask)
+{
+	int ret = 0;
+	unsigned int temp = 0;
+
+	ret = mcu_pmic_read(reg, &temp);
+	if (ret != 0)
+		return -1;
+	*reg_value = (temp & reg_mask);
+
+	pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value);
+
+	return ret;
+}
+
+
+int mcu_pmic_write_reg(int reg, unsigned int reg_value,
+			   unsigned int reg_mask)
+{
+	int ret = 0;
+	unsigned int temp = 0;
+
+	ret = mcu_pmic_read(reg, &temp);
+	if (ret != 0)
+		return -1;
+	temp = (temp & (~reg_mask)) | reg_value;
+
+	ret = mcu_pmic_write(reg, temp);
+	if (ret != 0)
+		return -1;
+
+	pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value);
+
+	return ret;
+}
+
+/*!
+ * make max8660 - mc9s08dz60 enter low-power mode
+ */
+static void pmic_power_off(void)
+{
+	mcu_pmic_write_reg(REG_MCU_POWER_CTL, 0x10, 0x10);
+}
+
+static int __init mcu_pmic_init(void)
+{
+	int err;
+
+	/* init chips */
+	err = max8660_init();
+	if (err)
+		goto fail1;
+
+	err = mc9s08dz60_init();
+	if (err)
+		goto fail1;
+
+	if (is_max8660_present()) {
+		pr_info("max8660 is present \n");
+		pm_power_off = pmic_power_off;
+	} else
+		pr_debug("max8660 is not present\n");
+	pr_info("mcu_pmic_init completed!\n");
+	return 0;
+
+fail1:
+	pr_err("mcu_pmic_init failed!\n");
+	return err;
+}
+
+static void __exit mcu_pmic_exit(void)
+{
+	reg_max8660_remove();
+	mc9s08dz60_exit();
+	max8660_exit();
+}
+
+subsys_initcall_sync(mcu_pmic_init);
+module_exit(mcu_pmic_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("mcu pmic driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_core.h b/drivers/mxc/mcu_pmic/mcu_pmic_core.h
new file mode 100644
index 000000000000..9ab07356f8a8
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/mcu_pmic_core.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mcu_pmic_core.h
+ * @brief Driver for max8660
+ *
+ * @ingroup pmic
+ */
+#ifndef _MCU_PMIC_CORE_H_
+#define _MCU_PMIC_CORE_H_
+
+#include <linux/mfd/mc9s08dz60/pmic.h>
+
+#define MAX8660_REG_START (REG_MCU_DES_FLAG + 1)
+enum {
+
+	/* reg names for max8660 */
+	REG_MAX8660_OUTPUT_ENABLE_1 = MAX8660_REG_START,
+	REG_MAX8660_OUTPUT_ENABLE_2,
+	REG_MAX8660_VOLT_CHANGE_CONTROL_1,
+	REG_MAX8660_V3_TARGET_VOLT_1,
+	REG_MAX8660_V3_TARGET_VOLT_2,
+	REG_MAX8660_V4_TARGET_VOLT_1,
+	REG_MAX8660_V4_TARGET_VOLT_2,
+	REG_MAX8660_V5_TARGET_VOLT_1,
+	REG_MAX8660_V5_TARGET_VOLT_2,
+	REG_MAX8660_V6V7_TARGET_VOLT,
+	REG_MAX8660_FORCE_PWM
+};
+
+
+#endif				/* _MCU_PMIC_CORE_H_ */
diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c b/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c
new file mode 100644
index 000000000000..dae00495e2b2
--- /dev/null
+++ b/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc9s08dz60/mcu_pmic_gpio.c
+ * @brief This is the main file of mc9s08dz60 Power Control driver.
+ *
+ * @ingroup PMIC_POWER
+ */
+
+/*
+ * Includes
+ */
+#include <linux/platform_device.h>
+#include <linux/mfd/mc9s08dz60/pmic.h>
+#include <linux/pmic_status.h>
+#include <linux/ioctl.h>
+
+#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos))
+#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos))
+
+int pmic_gpio_set_bit_val(int reg, unsigned int bit,
+				  unsigned int val)
+{
+	int reg_name;
+	u8 reg_mask = 0;
+
+	if (bit > 7)
+		return -1;
+
+	switch (reg) {
+	case MCU_GPIO_REG_RESET_1:
+		reg_name = REG_MCU_RESET_1;
+		break;
+	case MCU_GPIO_REG_RESET_2:
+		reg_name = REG_MCU_RESET_2;
+		break;
+	case MCU_GPIO_REG_POWER_CONTROL:
+		reg_name = REG_MCU_POWER_CTL;
+		break;
+	case MCU_GPIO_REG_GPIO_CONTROL_1:
+		reg_name = REG_MCU_GPIO_1;
+		break;
+	case MCU_GPIO_REG_GPIO_CONTROL_2:
+		reg_name = REG_MCU_GPIO_2;
+		break;
+	default:
+		return -1;
+	}
+
+	SET_BIT_IN_BYTE(reg_mask, bit);
+	if (0 == val)
+		CHECK_ERROR(mcu_pmic_write_reg(reg_name, 0, reg_mask));
+	else
+		CHECK_ERROR(mcu_pmic_write_reg(reg_name, reg_mask, reg_mask));
+
+	return 0;
+}
+EXPORT_SYMBOL(pmic_gpio_set_bit_val);
+
+int pmic_gpio_get_bit_val(int reg, unsigned int bit,
+				  unsigned int *val)
+{
+	int reg_name;
+	unsigned int reg_read_val;
+	u8 reg_mask = 0;
+
+	if (bit > 7)
+		return -1;
+
+	switch (reg) {
+	case MCU_GPIO_REG_RESET_1:
+		reg_name = REG_MCU_RESET_1;
+		break;
+	case MCU_GPIO_REG_RESET_2:
+		reg_name = REG_MCU_RESET_2;
+		break;
+	case MCU_GPIO_REG_POWER_CONTROL:
+		reg_name = REG_MCU_POWER_CTL;
+		break;
+	case MCU_GPIO_REG_GPIO_CONTROL_1:
+		reg_name = REG_MCU_GPIO_1;
+		break;
+	case MCU_GPIO_REG_GPIO_CONTROL_2:
+		reg_name = REG_MCU_GPIO_2;
+		break;
+	default:
+		return -1;
+	}
+
+	SET_BIT_IN_BYTE(reg_mask, bit);
+	CHECK_ERROR(mcu_pmic_read_reg(reg_name, &reg_read_val, reg_mask));
+	if (0 == reg_read_val)
+		*val = 0;
+	else
+		*val = 1;
+
+	return 0;
+}
+EXPORT_SYMBOL(pmic_gpio_get_bit_val);
+
+int pmic_gpio_get_designation_bit_val(unsigned int bit,
+					unsigned int *val)
+{
+	unsigned int reg_read_val;
+	u8 reg_mask = 0;
+
+	if (bit > 7)
+		return -1;
+
+	SET_BIT_IN_BYTE(reg_mask, bit);
+	CHECK_ERROR(
+		mcu_pmic_read_reg(REG_MCU_DES_FLAG, &reg_read_val, reg_mask));
+	if (0 == reg_read_val)
+		*val = 0;
+	else
+		*val = 1;
+
+	return 0;
+}
+EXPORT_SYMBOL(pmic_gpio_get_designation_bit_val);
diff --git a/drivers/mxc/mlb/Kconfig b/drivers/mxc/mlb/Kconfig
new file mode 100644
index 000000000000..7e3b16c2ddae
--- /dev/null
+++ b/drivers/mxc/mlb/Kconfig
@@ -0,0 +1,13 @@
+#
+# MLB configuration
+#
+
+menu "MXC Media Local Bus Driver"
+
+config MXC_MLB
+	tristate "MLB support"
+	depends on ARCH_MX35 || ARCH_MX53
+	---help---
+         Say Y to get the MLB support.
+
+endmenu
diff --git a/drivers/mxc/mlb/Makefile b/drivers/mxc/mlb/Makefile
new file mode 100644
index 000000000000..60662eb1c031
--- /dev/null
+++ b/drivers/mxc/mlb/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the kernel MLB driver
+#
+
+obj-$(CONFIG_MXC_MLB) += mxc_mlb.o
diff --git a/drivers/mxc/mlb/mxc_mlb.c b/drivers/mxc/mlb/mxc_mlb.c
new file mode 100644
index 000000000000..d463e383c759
--- /dev/null
+++ b/drivers/mxc/mlb/mxc_mlb.c
@@ -0,0 +1,1055 @@
+/*
+ * linux/drivers/mxc/mlb/mxc_mlb.c
+ *
+ * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/poll.h>
+#include <linux/cdev.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mxc_mlb.h>
+#include <linux/uaccess.h>
+#include <linux/iram_alloc.h>
+
+#include <mach/hardware.h>
+
+/*!
+ * MLB module memory map registers define
+ */
+#define MLB_REG_DCCR	0x0
+#define MLB_REG_SSCR	0x4
+#define MLB_REG_SDCR	0x8
+#define MLB_REG_SMCR	0xC
+#define MLB_REG_VCCR	0x1C
+#define MLB_REG_SBCR	0x20
+#define MLB_REG_ABCR	0x24
+#define MLB_REG_CBCR	0x28
+#define MLB_REG_IBCR	0x2C
+#define MLB_REG_CICR	0x30
+#define MLB_REG_CECRn	0x40
+#define MLB_REG_CSCRn	0x44
+#define MLB_REG_CCBCRn	0x48
+#define MLB_REG_CNBCRn	0x4C
+#define MLB_REG_LCBCRn	0x280
+
+#define MLB_DCCR_FS_OFFSET	28
+#define MLB_DCCR_EN		(1 << 31)
+#define MLB_DCCR_LBM_OFFSET	30
+#define MLB_DCCR_RESET		(1 << 23)
+#define MLB_CECR_CE		(1 << 31)
+#define MLB_CECR_TR		(1 << 30)
+#define MLB_CECR_CT_OFFSET	28
+#define MLB_CECR_MBS		(1 << 19)
+#define MLB_CSCR_CBPE		(1 << 0)
+#define MLB_CSCR_CBDB		(1 << 1)
+#define MLB_CSCR_CBD		(1 << 2)
+#define MLB_CSCR_CBS		(1 << 3)
+#define MLB_CSCR_BE		(1 << 4)
+#define MLB_CSCR_ABE		(1 << 5)
+#define MLB_CSCR_LFS		(1 << 6)
+#define MLB_CSCR_PBPE		(1 << 8)
+#define MLB_CSCR_PBDB		(1 << 9)
+#define MLB_CSCR_PBD		(1 << 10)
+#define MLB_CSCR_PBS		(1 << 11)
+#define MLB_CSCR_RDY		(1 << 16)
+#define MLB_CSCR_BM		(1 << 31)
+#define MLB_CSCR_BF		(1 << 30)
+#define MLB_SSCR_SDML		(1 << 5)
+
+#define MLB_CONTROL_TX_CHANN		(0 << 4)
+#define MLB_CONTROL_RX_CHANN		(1 << 4)
+#define MLB_ASYNC_TX_CHANN		(2 << 4)
+#define MLB_ASYNC_RX_CHANN		(3 << 4)
+
+#define MLB_MINOR_DEVICES		2
+#define MLB_CONTROL_DEV_NAME		"ctrl"
+#define MLB_ASYNC_DEV_NAME		"async"
+
+#define TX_CHANNEL			0
+#define RX_CHANNEL			1
+#define TX_CHANNEL_BUF_SIZE		1024
+#define RX_CHANNEL_BUF_SIZE		2*1024
+/* max package data size */
+#define ASYNC_PACKET_SIZE			1024
+#define CTRL_PACKET_SIZE			64
+#define RX_RING_NODES			10
+
+#define MLB_IRAM_SIZE			(MLB_MINOR_DEVICES * (TX_CHANNEL_BUF_SIZE + RX_CHANNEL_BUF_SIZE))
+#define _get_txchan(dev)		mlb_devinfo[dev].channels[TX_CHANNEL]
+#define _get_rxchan(dev)		mlb_devinfo[dev].channels[RX_CHANNEL]
+
+enum {
+	MLB_CTYPE_SYNC,
+	MLB_CTYPE_ISOC,
+	MLB_CTYPE_ASYNC,
+	MLB_CTYPE_CTRL,
+};
+
+/*!
+ * Rx ring buffer
+ */
+struct mlb_rx_ringnode {
+	int size;
+	char *data;
+};
+
+struct mlb_channel_info {
+
+	/* channel offset in memmap */
+	const unsigned int reg_offset;
+	/* channel address */
+	int address;
+	/*!
+	 * channel buffer start address
+	 * for Rx, buf_head pointer to a loop ring buffer
+	 */
+	unsigned long buf_head;
+	/* physical buffer head address */
+	unsigned long phy_head;
+	/* channel buffer size */
+	unsigned int buf_size;
+	/* channel buffer current ptr */
+	unsigned long buf_ptr;
+	/* buffer spin lock */
+	rwlock_t buf_lock;
+};
+
+struct mlb_dev_info {
+
+	/* device node name */
+	const char dev_name[20];
+	/* channel type */
+	const unsigned int channel_type;
+	/* channel info for tx/rx */
+	struct mlb_channel_info channels[2];
+	/* rx ring buffer */
+	struct mlb_rx_ringnode rx_bufs[RX_RING_NODES];
+	/* rx ring buffer read/write ptr */
+	unsigned int rdpos, wtpos;
+	/* exception event */
+	unsigned long ex_event;
+	/* channel started up or not */
+	atomic_t on;
+	/* device open count */
+	atomic_t opencnt;
+	/* wait queue head for channel */
+	wait_queue_head_t rd_wq;
+	wait_queue_head_t wt_wq;
+	/* spinlock for event access */
+	spinlock_t event_lock;
+};
+
+static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = {
+	{
+	 .dev_name = MLB_CONTROL_DEV_NAME,
+	 .channel_type = MLB_CTYPE_CTRL,
+	 .channels = {
+		      [0] = {
+			     .reg_offset = MLB_CONTROL_TX_CHANN,
+			     .buf_size = TX_CHANNEL_BUF_SIZE,
+			     .buf_lock =
+			     __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[0].
+						buf_lock),
+			     },
+		      [1] = {
+			     .reg_offset = MLB_CONTROL_RX_CHANN,
+			     .buf_size = RX_CHANNEL_BUF_SIZE,
+			     .buf_lock =
+			     __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[1].
+						buf_lock),
+			     },
+		      },
+	 .on = ATOMIC_INIT(0),
+	 .opencnt = ATOMIC_INIT(0),
+	 .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].rd_wq),
+	 .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].wt_wq),
+	 .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock),
+	 },
+	{
+	 .dev_name = MLB_ASYNC_DEV_NAME,
+	 .channel_type = MLB_CTYPE_ASYNC,
+	 .channels = {
+		      [0] = {
+			     .reg_offset = MLB_ASYNC_TX_CHANN,
+			     .buf_size = TX_CHANNEL_BUF_SIZE,
+			     .buf_lock =
+			     __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[0].
+						buf_lock),
+			     },
+		      [1] = {
+			     .reg_offset = MLB_ASYNC_RX_CHANN,
+			     .buf_size = RX_CHANNEL_BUF_SIZE,
+			     .buf_lock =
+			     __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[1].
+						buf_lock),
+			     },
+		      },
+	 .on = ATOMIC_INIT(0),
+	 .opencnt = ATOMIC_INIT(0),
+	 .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].rd_wq),
+	 .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].wt_wq),
+	 .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock),
+	 },
+};
+
+static struct regulator *reg_nvcc;	/* NVCC_MLB regulator */
+static struct clk *mlb_clk;
+static struct cdev mxc_mlb_dev;	/* chareset device */
+static dev_t dev;
+static struct class *mlb_class;	/* device class */
+static struct device *class_dev;
+static unsigned long mlb_base;	/* mlb module base address */
+static unsigned int irq;
+static unsigned long iram_base;
+static __iomem void *iram_addr;
+
+/*!
+ * Initial the MLB module device
+ */
+static void mlb_dev_init(void)
+{
+	unsigned long dccr_val;
+	unsigned long phyaddr;
+
+	/* reset the MLB module */
+	__raw_writel(MLB_DCCR_RESET, mlb_base + MLB_REG_DCCR);
+	while (__raw_readl(mlb_base + MLB_REG_DCCR)
+	       & MLB_DCCR_RESET) ;
+
+	/*!
+	 * Enable MLB device, disable loopback mode,
+	 * set default fps to 512, set mlb device address to 0
+	 */
+	dccr_val = MLB_DCCR_EN;
+	__raw_writel(dccr_val, mlb_base + MLB_REG_DCCR);
+
+	/* disable all the system interrupt */
+	__raw_writel(0x5F, mlb_base + MLB_REG_SMCR);
+
+	/* write async, control tx/rx base address */
+	phyaddr = _get_txchan(0).phy_head >> 16;
+	__raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_CBCR);
+	phyaddr = _get_txchan(1).phy_head >> 16;
+	__raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_ABCR);
+
+}
+
+static void mlb_dev_exit(void)
+{
+	__raw_writel(0, mlb_base + MLB_REG_DCCR);
+}
+
+/*!
+ * MLB receive start function
+ *
+ * load phy_head to next buf register to start next rx
+ * here use single-packet buffer, set start=end
+ */
+static void mlb_start_rx(int cdev_id)
+{
+	struct mlb_channel_info *chinfo = &_get_rxchan(cdev_id);
+	unsigned long next;
+
+	next = chinfo->phy_head & 0xFFFC;
+	/* load next buf */
+	__raw_writel((next << 16) | next, mlb_base +
+		     MLB_REG_CNBCRn + chinfo->reg_offset);
+	/* set ready bit to start next rx */
+	__raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn
+		     + chinfo->reg_offset);
+}
+
+/*!
+ * MLB transmit start function
+ * make sure aquiring the rw buf_lock, when calling this
+ */
+static void mlb_start_tx(int cdev_id)
+{
+	struct mlb_channel_info *chinfo = &_get_txchan(cdev_id);
+	unsigned long begin, end;
+
+	begin = chinfo->phy_head;
+	end = (chinfo->phy_head + chinfo->buf_ptr - chinfo->buf_head) & 0xFFFC;
+	/* load next buf */
+	__raw_writel((begin << 16) | end, mlb_base +
+		     MLB_REG_CNBCRn + chinfo->reg_offset);
+	/* set ready bit to start next tx */
+	__raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn
+		     + chinfo->reg_offset);
+}
+
+/*!
+ * Enable the MLB channel
+ */
+static void mlb_channel_enable(int chan_dev_id, int on)
+{
+	unsigned long tx_regval = 0, rx_regval = 0;
+	/*!
+	 * setup the direction, enable, channel type,
+	 * mode select, channel address and mask buf start
+	 */
+	if (on) {
+		unsigned int ctype = mlb_devinfo[chan_dev_id].channel_type;
+		tx_regval = MLB_CECR_CE | MLB_CECR_TR | MLB_CECR_MBS |
+		    (ctype << MLB_CECR_CT_OFFSET) |
+		    _get_txchan(chan_dev_id).address;
+		rx_regval = MLB_CECR_CE | MLB_CECR_MBS |
+		    (ctype << MLB_CECR_CT_OFFSET) |
+		    _get_rxchan(chan_dev_id).address;
+
+		atomic_set(&mlb_devinfo[chan_dev_id].on, 1);
+	} else {
+		atomic_set(&mlb_devinfo[chan_dev_id].on, 0);
+	}
+
+	/* update the rx/tx channel entry config */
+	__raw_writel(tx_regval, mlb_base + MLB_REG_CECRn +
+		     _get_txchan(chan_dev_id).reg_offset);
+	__raw_writel(rx_regval, mlb_base + MLB_REG_CECRn +
+		     _get_rxchan(chan_dev_id).reg_offset);
+
+	if (on)
+		mlb_start_rx(chan_dev_id);
+}
+
+/*!
+ * MLB interrupt handler
+ */
+void mlb_tx_isr(int minor, unsigned int cis)
+{
+	struct mlb_channel_info *chinfo = &_get_txchan(minor);
+
+	if (cis & MLB_CSCR_CBD) {
+		/* buffer done, reset the buf_ptr */
+		write_lock(&chinfo->buf_lock);
+		chinfo->buf_ptr = chinfo->buf_head;
+		write_unlock(&chinfo->buf_lock);
+		/* wake up the writer */
+		wake_up_interruptible(&mlb_devinfo[minor].wt_wq);
+	}
+}
+
+void mlb_rx_isr(int minor, unsigned int cis)
+{
+	struct mlb_channel_info *chinfo = &_get_rxchan(minor);
+	unsigned long end;
+	unsigned int len;
+
+	if (cis & MLB_CSCR_CBD) {
+
+		int wpos, rpos;
+
+		rpos = mlb_devinfo[minor].rdpos;
+		wpos = mlb_devinfo[minor].wtpos;
+
+		/* buffer done, get current buffer ptr */
+		end =
+		    __raw_readl(mlb_base + MLB_REG_CCBCRn + chinfo->reg_offset);
+		end >>= 16;	/* end here is phy */
+		len = end - (chinfo->phy_head & 0xFFFC);
+
+		/*!
+		 * copy packet from IRAM buf to ring buf.
+		 * if the wpos++ == rpos, drop this packet
+		 */
+		if (((wpos + 1) % RX_RING_NODES) != rpos) {
+
+#ifdef DEBUG
+			if (mlb_devinfo[minor].channel_type == MLB_CTYPE_CTRL) {
+				if (len > CTRL_PACKET_SIZE)
+					pr_debug
+					    ("mxc_mlb: ctrl packet"
+					     "overflow\n");
+			} else {
+				if (len > ASYNC_PACKET_SIZE)
+					pr_debug
+					    ("mxc_mlb: async packet"
+					     "overflow\n");
+			}
+#endif
+			memcpy(mlb_devinfo[minor].rx_bufs[wpos].data,
+			       (const void *)chinfo->buf_head, len);
+			mlb_devinfo[minor].rx_bufs[wpos].size = len;
+
+			/* update the ring wpos */
+			mlb_devinfo[minor].wtpos = (wpos + 1) % RX_RING_NODES;
+
+			/* wake up the reader */
+			wake_up_interruptible(&mlb_devinfo[minor].rd_wq);
+
+			pr_debug("recv package, len:%d, rdpos: %d, wtpos: %d\n",
+				 len, rpos, mlb_devinfo[minor].wtpos);
+		} else {
+			pr_debug
+			    ("drop package, due to no space, (%d,%d)\n",
+			     rpos, mlb_devinfo[minor].wtpos);
+		}
+
+		/* start next rx */
+		mlb_start_rx(minor);
+	}
+}
+
+static irqreturn_t mlb_isr(int irq, void *dev_id)
+{
+	unsigned long int_status, sscr, tx_cis, rx_cis;
+	struct mlb_dev_info *pdev;
+	int minor;
+
+	sscr = __raw_readl(mlb_base + MLB_REG_SSCR);
+	pr_debug("mxc_mlb: system interrupt:%lx\n", sscr);
+	__raw_writel(0x7F, mlb_base + MLB_REG_SSCR);
+
+	int_status = __raw_readl(mlb_base + MLB_REG_CICR) & 0xFFFF;
+	pr_debug("mxc_mlb: channel interrupt ids: %lx\n", int_status);
+
+	for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) {
+
+		pdev = &mlb_devinfo[minor];
+		tx_cis = rx_cis = 0;
+
+		/* get tx channel interrupt status */
+		if (int_status & (1 << (_get_txchan(minor).reg_offset >> 4)))
+			tx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn
+					     + _get_txchan(minor).reg_offset);
+		/* get rx channel interrupt status */
+		if (int_status & (1 << (_get_rxchan(minor).reg_offset >> 4)))
+			rx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn
+					     + _get_rxchan(minor).reg_offset);
+
+		if (!tx_cis && !rx_cis)
+			continue;
+
+		pr_debug("tx/rx int status: 0x%08lx/0x%08lx\n", tx_cis, rx_cis);
+		/* fill exception event */
+		spin_lock(&pdev->event_lock);
+		pdev->ex_event |= tx_cis & 0x303;
+		pdev->ex_event |= (rx_cis & 0x303) << 16;
+		spin_unlock(&pdev->event_lock);
+
+		/* clear the interrupt status */
+		__raw_writel(tx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn
+			     + _get_txchan(minor).reg_offset);
+		__raw_writel(rx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn
+			     + _get_rxchan(minor).reg_offset);
+
+		/* handel tx channel */
+		if (tx_cis)
+			mlb_tx_isr(minor, tx_cis);
+		/* handle rx channel */
+		if (rx_cis)
+			mlb_rx_isr(minor, rx_cis);
+
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mxc_mlb_open(struct inode *inode, struct file *filp)
+{
+	int minor;
+
+	minor = MINOR(inode->i_rdev);
+
+	if (minor < 0 || minor >= MLB_MINOR_DEVICES)
+		return -ENODEV;
+
+	/* open for each channel device */
+	if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0)
+		return -EBUSY;
+
+	/* reset the buffer read/write ptr */
+	_get_txchan(minor).buf_ptr = _get_txchan(minor).buf_head;
+	_get_rxchan(minor).buf_ptr = _get_rxchan(minor).buf_head;
+	mlb_devinfo[minor].rdpos = mlb_devinfo[minor].wtpos = 0;
+	mlb_devinfo[minor].ex_event = 0;
+
+	return 0;
+}
+
+static int mxc_mlb_release(struct inode *inode, struct file *filp)
+{
+	int minor;
+
+	minor = MINOR(inode->i_rdev);
+
+	/* clear channel settings and info */
+	mlb_channel_enable(minor, 0);
+
+	/* decrease the open count */
+	atomic_set(&mlb_devinfo[minor].opencnt, 0);
+
+	return 0;
+}
+
+static int mxc_mlb_ioctl(struct inode *inode, struct file *filp,
+			 unsigned int cmd, unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	unsigned long flags, event;
+	int minor;
+
+	minor = MINOR(inode->i_rdev);
+
+	switch (cmd) {
+
+	case MLB_CHAN_SETADDR:
+		{
+			unsigned int caddr;
+			/* get channel address from user space */
+			if (copy_from_user(&caddr, argp, sizeof(caddr))) {
+				pr_err("mxc_mlb: copy from user failed\n");
+				return -EFAULT;
+			}
+			_get_txchan(minor).address = (caddr >> 16) & 0xFFFF;
+			_get_rxchan(minor).address = caddr & 0xFFFF;
+			break;
+		}
+
+	case MLB_CHAN_STARTUP:
+		if (atomic_read(&mlb_devinfo[minor].on)) {
+			pr_debug("mxc_mlb: channel areadly startup\n");
+			break;
+		}
+		mlb_channel_enable(minor, 1);
+		break;
+	case MLB_CHAN_SHUTDOWN:
+		if (atomic_read(&mlb_devinfo[minor].on) == 0) {
+			pr_debug("mxc_mlb: channel areadly shutdown\n");
+			break;
+		}
+		mlb_channel_enable(minor, 0);
+		break;
+	case MLB_CHAN_GETEVENT:
+		/* get and clear the ex_event */
+		spin_lock_irqsave(&mlb_devinfo[minor].event_lock, flags);
+		event = mlb_devinfo[minor].ex_event;
+		mlb_devinfo[minor].ex_event = 0;
+		spin_unlock_irqrestore(&mlb_devinfo[minor].event_lock, flags);
+
+		if (event) {
+			if (copy_to_user(argp, &event, sizeof(event))) {
+				pr_err("mxc_mlb: copy to user failed\n");
+				return -EFAULT;
+			}
+		} else {
+			pr_debug("mxc_mlb: no exception event now\n");
+			return -EAGAIN;
+		}
+		break;
+	case MLB_SET_FPS:
+		{
+			unsigned int fps;
+			unsigned long dccr_val;
+
+			/* get fps from user space */
+			if (copy_from_user(&fps, argp, sizeof(fps))) {
+				pr_err("mxc_mlb: copy from user failed\n");
+				return -EFAULT;
+			}
+
+			/* check fps value */
+			if (fps != 256 && fps != 512 && fps != 1024) {
+				pr_debug("mxc_mlb: invalid fps argument\n");
+				return -EINVAL;
+			}
+
+			dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR);
+			dccr_val &= ~(0x3 << MLB_DCCR_FS_OFFSET);
+			dccr_val |= (fps >> 9) << MLB_DCCR_FS_OFFSET;
+			__raw_writel(dccr_val, mlb_base + MLB_REG_DCCR);
+			break;
+		}
+
+	case MLB_GET_VER:
+		{
+			unsigned long version;
+
+			/* get MLB device module version */
+			version = __raw_readl(mlb_base + MLB_REG_VCCR);
+
+			if (copy_to_user(argp, &version, sizeof(version))) {
+				pr_err("mxc_mlb: copy to user failed\n");
+				return -EFAULT;
+			}
+			break;
+		}
+
+	case MLB_SET_DEVADDR:
+		{
+			unsigned long dccr_val;
+			unsigned char devaddr;
+
+			/* get MLB device address from user space */
+			if (copy_from_user
+			    (&devaddr, argp, sizeof(unsigned char))) {
+				pr_err("mxc_mlb: copy from user failed\n");
+				return -EFAULT;
+			}
+
+			dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR);
+			dccr_val &= ~0xFF;
+			dccr_val |= devaddr;
+			__raw_writel(dccr_val, mlb_base + MLB_REG_DCCR);
+
+			break;
+		}
+	default:
+		pr_info("mxc_mlb: Invalid ioctl command\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*!
+ * MLB read routine
+ *
+ * Read the current received data from queued buffer,
+ * and free this buffer for hw to fill ingress data.
+ */
+static ssize_t mxc_mlb_read(struct file *filp, char __user *buf,
+			    size_t count, loff_t *f_pos)
+{
+	int minor, ret;
+	int size, rdpos;
+	struct mlb_rx_ringnode *rxbuf;
+
+	minor = MINOR(filp->f_dentry->d_inode->i_rdev);
+
+	rdpos = mlb_devinfo[minor].rdpos;
+	rxbuf = mlb_devinfo[minor].rx_bufs;
+
+	/* check the current rx buffer is available or not */
+	if (rdpos == mlb_devinfo[minor].wtpos) {
+		if (filp->f_flags & O_NONBLOCK)
+			return -EAGAIN;
+		/* if !O_NONBLOCK, we wait for recv packet */
+		ret = wait_event_interruptible(mlb_devinfo[minor].rd_wq,
+						(mlb_devinfo[minor].wtpos !=
+						rdpos));
+		if (ret < 0)
+			return ret;
+	}
+
+	size = rxbuf[rdpos].size;
+	if (size > count) {
+		/* the user buffer is too small */
+		pr_warning
+		    ("mxc_mlb: received data size is bigger than count\n");
+		return -EINVAL;
+	}
+
+	/* copy rx buffer data to user buffer */
+	if (copy_to_user(buf, rxbuf[rdpos].data, size)) {
+		pr_err("mxc_mlb: copy from user failed\n");
+		return -EFAULT;
+	}
+
+	/* update the read ptr */
+	mlb_devinfo[minor].rdpos = (rdpos + 1) % RX_RING_NODES;
+
+	*f_pos = 0;
+
+	return size;
+}
+
+/*!
+ * MLB write routine
+ *
+ * Copy the user data to tx channel buffer,
+ * and prepare the channel current/next buffer ptr.
+ */
+static ssize_t mxc_mlb_write(struct file *filp, const char __user *buf,
+			     size_t count, loff_t *f_pos)
+{
+	int minor;
+	unsigned long flags;
+	DEFINE_WAIT(__wait);
+	int ret;
+
+	minor = MINOR(filp->f_dentry->d_inode->i_rdev);
+
+	if (count > _get_txchan(minor).buf_size) {
+		/* too many data to write */
+		pr_warning("mxc_mlb: overflow write data\n");
+		return -EFBIG;
+	}
+
+	*f_pos = 0;
+
+	/* check the current tx buffer is used or not */
+	write_lock_irqsave(&_get_txchan(minor).buf_lock, flags);
+	if (_get_txchan(minor).buf_ptr != _get_txchan(minor).buf_head) {
+		write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags);
+
+		/* there's already some datas being transmit now */
+		if (filp->f_flags & O_NONBLOCK)
+			return -EAGAIN;
+
+		/* if !O_NONBLOCK, we wait for transmit finish */
+		for (;;) {
+			prepare_to_wait(&mlb_devinfo[minor].wt_wq,
+					&__wait, TASK_INTERRUPTIBLE);
+
+			write_lock_irqsave(&_get_txchan(minor).buf_lock, flags);
+			if (_get_txchan(minor).buf_ptr ==
+			    _get_txchan(minor).buf_head)
+				break;
+
+			write_unlock_irqrestore(&_get_txchan(minor).buf_lock,
+						flags);
+			if (!signal_pending(current)) {
+				schedule();
+				continue;
+			}
+			return -ERESTARTSYS;
+		}
+		finish_wait(&mlb_devinfo[minor].wt_wq, &__wait);
+	}
+
+	/* copy user buffer to tx buffer */
+	if (copy_from_user((void *)_get_txchan(minor).buf_ptr, buf, count)) {
+		pr_err("mxc_mlb: copy from user failed\n");
+		ret = -EFAULT;
+		goto out;
+	}
+	_get_txchan(minor).buf_ptr += count;
+
+	/* set current/next buffer start/end */
+	mlb_start_tx(minor);
+
+	ret = count;
+
+out:
+	write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags);
+	return ret;
+}
+
+static unsigned int mxc_mlb_poll(struct file *filp,
+				 struct poll_table_struct *wait)
+{
+	int minor;
+	unsigned int ret = 0;
+	unsigned long flags;
+
+	minor = MINOR(filp->f_dentry->d_inode->i_rdev);
+
+	poll_wait(filp, &mlb_devinfo[minor].rd_wq, wait);
+	poll_wait(filp, &mlb_devinfo[minor].wt_wq, wait);
+
+	/* check the tx buffer is avaiable or not */
+	read_lock_irqsave(&_get_txchan(minor).buf_lock, flags);
+	if (_get_txchan(minor).buf_ptr == _get_txchan(minor).buf_head)
+		ret |= POLLOUT | POLLWRNORM;
+	read_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags);
+
+	/* check the rx buffer filled or not */
+	if (mlb_devinfo[minor].rdpos != mlb_devinfo[minor].wtpos)
+		ret |= POLLIN | POLLRDNORM;
+
+	/* check the exception event */
+	if (mlb_devinfo[minor].ex_event)
+		ret |= POLLIN | POLLRDNORM;
+
+	return ret;
+}
+
+/*!
+ * char dev file operations structure
+ */
+static struct file_operations mxc_mlb_fops = {
+
+	.owner = THIS_MODULE,
+	.open = mxc_mlb_open,
+	.release = mxc_mlb_release,
+	.ioctl = mxc_mlb_ioctl,
+	.poll = mxc_mlb_poll,
+	.read = mxc_mlb_read,
+	.write = mxc_mlb_write,
+};
+
+/*!
+ * This function is called whenever the MLB device is detected.
+ */
+static int __devinit mxc_mlb_probe(struct platform_device *pdev)
+{
+	int ret, mlb_major, i, j;
+	struct mxc_mlb_platform_data *plat_data;
+	struct resource *res;
+	void __iomem *base, *bufaddr;
+	unsigned long phyaddr;
+
+	/* malloc the Rx ring buffer firstly */
+	for (i = 0; i < MLB_MINOR_DEVICES; i++) {
+		char *buf;
+		int bufsize;
+
+		if (mlb_devinfo[i].channel_type == MLB_CTYPE_ASYNC)
+			bufsize = ASYNC_PACKET_SIZE;
+		else
+			bufsize = CTRL_PACKET_SIZE;
+
+		buf = kmalloc(bufsize * RX_RING_NODES, GFP_KERNEL);
+		if (buf == NULL) {
+			ret = -ENOMEM;
+			dev_err(&pdev->dev, "can not alloc rx buffers\n");
+			goto err4;
+		}
+		for (j = 0; j < RX_RING_NODES; j++) {
+			mlb_devinfo[i].rx_bufs[j].data = buf;
+			buf += bufsize;
+		}
+	}
+
+	/**
+	 * Register MLB lld as two character devices
+	 * One for Packet date channel, the other for control data channel
+	 */
+	ret = alloc_chrdev_region(&dev, 0, MLB_MINOR_DEVICES, "mxc_mlb");
+	mlb_major = MAJOR(dev);
+
+	if (ret < 0) {
+		dev_err(&pdev->dev, "can't get major %d\n", mlb_major);
+		goto err3;
+	}
+
+	cdev_init(&mxc_mlb_dev, &mxc_mlb_fops);
+	mxc_mlb_dev.owner = THIS_MODULE;
+
+	ret = cdev_add(&mxc_mlb_dev, dev, MLB_MINOR_DEVICES);
+	if (ret) {
+		dev_err(&pdev->dev, "can't add cdev\n");
+		goto err2;
+	}
+
+	/* create class and device for udev information */
+	mlb_class = class_create(THIS_MODULE, "mlb");
+	if (IS_ERR(mlb_class)) {
+		dev_err(&pdev->dev, "failed to create mlb class\n");
+		ret = -ENOMEM;
+		goto err2;
+	}
+
+	for (i = 0; i < MLB_MINOR_DEVICES; i++) {
+
+		class_dev = device_create(mlb_class, NULL, MKDEV(mlb_major, i),
+					  NULL, mlb_devinfo[i].dev_name);
+		if (IS_ERR(class_dev)) {
+			dev_err(&pdev->dev, "failed to create mlb %s"
+				" class device\n", mlb_devinfo[i].dev_name);
+			ret = -ENOMEM;
+			goto err1;
+		}
+	}
+
+	/* get irq line */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "No mlb irq line provided\n");
+		goto err1;
+	}
+
+	irq = res->start;
+	/* request irq */
+	if (request_irq(irq, mlb_isr, 0, "mlb", NULL)) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		ret = -EBUSY;
+		goto err1;
+	}
+
+	/* ioremap from phy mlb to kernel space */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "No mlb base address provided\n");
+		goto err0;
+	}
+
+	base = ioremap(res->start, res->end - res->start);
+	dev_dbg(&pdev->dev, "mapped mlb base address: 0x%08x\n",
+		(unsigned int)base);
+
+	if (base == NULL) {
+		dev_err(&pdev->dev, "failed to do ioremap with mlb base\n");
+		goto err0;
+	}
+	mlb_base = (unsigned long)base;
+
+	/*!
+	 * get rx/tx buffer address from platform data
+	 * make sure the buf_address is 4bytes aligned
+	 *
+	 * -------------------   <-- plat_data->buf_address
+	 * | minor 0 tx buf  |
+	 *  -----------------
+	 * | minor 0 rx buf  |
+	 *  -----------------
+	 * |    ....         |
+	 *  -----------------
+	 * | minor n tx buf  |
+	 *  -----------------
+	 * | minor n rx buf  |
+	 * -------------------
+	 */
+
+	plat_data = (struct mxc_mlb_platform_data *)pdev->dev.platform_data;
+
+	bufaddr = iram_addr = iram_alloc(MLB_IRAM_SIZE, &iram_base);
+	phyaddr = iram_base;
+
+	for (i = 0; i < MLB_MINOR_DEVICES; i++) {
+		/* set the virtual and physical buf head address */
+		_get_txchan(i).buf_head = bufaddr;
+		_get_txchan(i).phy_head = phyaddr;
+
+		bufaddr += TX_CHANNEL_BUF_SIZE;
+		phyaddr += TX_CHANNEL_BUF_SIZE;
+
+		_get_rxchan(i).buf_head = (unsigned long)bufaddr;
+		_get_rxchan(i).phy_head = phyaddr;
+
+		bufaddr += RX_CHANNEL_BUF_SIZE;
+		phyaddr += RX_CHANNEL_BUF_SIZE;
+
+		dev_dbg(&pdev->dev, "phy_head: tx(%lx), rx(%lx)\n",
+			_get_txchan(i).phy_head, _get_rxchan(i).phy_head);
+		dev_dbg(&pdev->dev, "buf_head: tx(%lx), rx(%lx)\n",
+			_get_txchan(i).buf_head, _get_rxchan(i).buf_head);
+	}
+
+	/* enable GPIO */
+	gpio_mlb_active();
+
+	/* power on MLB */
+	reg_nvcc = regulator_get(&pdev->dev, plat_data->reg_nvcc);
+	/* set MAX LDO6 for NVCC to 2.5V */
+	regulator_set_voltage(reg_nvcc, 2500000, 2500000);
+	regulator_enable(reg_nvcc);
+
+	/* enable clock */
+	mlb_clk = clk_get(&pdev->dev, plat_data->mlb_clk);
+	clk_enable(mlb_clk);
+
+	/* initial MLB module */
+	mlb_dev_init();
+
+	return 0;
+
+err0:
+	free_irq(irq, NULL);
+err1:
+	for (--i; i >= 0; i--)
+		device_destroy(mlb_class, MKDEV(mlb_major, i));
+
+	class_destroy(mlb_class);
+err2:
+	cdev_del(&mxc_mlb_dev);
+err3:
+	unregister_chrdev_region(dev, MLB_MINOR_DEVICES);
+err4:
+	for (i = 0; i < MLB_MINOR_DEVICES; i++)
+		kfree(mlb_devinfo[i].rx_bufs[0].data);
+
+	return ret;
+}
+
+static int __devexit mxc_mlb_remove(struct platform_device *pdev)
+{
+	int i;
+
+	mlb_dev_exit();
+
+	/* disable mlb clock */
+	clk_disable(mlb_clk);
+	clk_put(mlb_clk);
+
+	/* disable mlb power */
+	regulator_disable(reg_nvcc);
+	regulator_put(reg_nvcc);
+
+	/* inactive GPIO */
+	gpio_mlb_inactive();
+
+	iram_free(iram_base, MLB_IRAM_SIZE);
+
+	/* iounmap */
+	iounmap((void *)mlb_base);
+
+	free_irq(irq, NULL);
+
+	/* destroy mlb device class */
+	for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--)
+		device_destroy(mlb_class, MKDEV(MAJOR(dev), i));
+	class_destroy(mlb_class);
+
+	/* Unregister the two MLB devices */
+	cdev_del(&mxc_mlb_dev);
+	unregister_chrdev_region(dev, MLB_MINOR_DEVICES);
+
+	for (i = 0; i < MLB_MINOR_DEVICES; i++)
+		kfree(mlb_devinfo[i].rx_bufs[0].data);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_mlb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int mxc_mlb_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define mxc_mlb_suspend NULL
+#define mxc_mlb_resume NULL
+#endif
+
+/*!
+ * platform driver structure for MLB
+ */
+static struct platform_driver mxc_mlb_driver = {
+	.driver = {
+		   .name = "mxc_mlb"},
+	.probe = mxc_mlb_probe,
+	.remove = __devexit_p(mxc_mlb_remove),
+	.suspend = mxc_mlb_suspend,
+	.resume = mxc_mlb_resume,
+};
+
+static int __init mxc_mlb_init(void)
+{
+	return platform_driver_register(&mxc_mlb_driver);
+}
+
+static void __exit mxc_mlb_exit(void)
+{
+	platform_driver_unregister(&mxc_mlb_driver);
+}
+
+module_init(mxc_mlb_init);
+module_exit(mxc_mlb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MLB low level driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/Kconfig b/drivers/mxc/pmic/Kconfig
new file mode 100644
index 000000000000..4ee91110fc03
--- /dev/null
+++ b/drivers/mxc/pmic/Kconfig
@@ -0,0 +1,64 @@
+#
+# PMIC device driver configuration
+#
+
+menu "MXC PMIC support"
+
+config MXC_PMIC
+	boolean
+
+config MXC_PMIC_MC13783
+	tristate "MC13783 PMIC"
+	depends on ARCH_MXC && SPI
+	select MXC_PMIC
+	---help---
+	  This is the MXC MC13783(PMIC) support. It include
+	  ADC, Audio, Battery, Connectivity, Light, Power and RTC.
+
+config MXC_PMIC_MC13892
+	tristate "MC13892 PMIC"
+	depends on ARCH_MXC && (I2C || SPI)
+	select MXC_PMIC
+	---help---
+	  This is the MXC MC13892(PMIC) support. It include
+	  ADC, Battery, Connectivity, Light, Power and RTC.
+
+config MXC_PMIC_I2C
+	bool "Support PMIC I2C Interface"
+	depends on MXC_PMIC_MC13892 && I2C
+
+config MXC_PMIC_SPI
+	bool "Support PMIC SPI Interface"
+	depends on (MXC_PMIC_MC13892 || MXC_PMIC_MC13783) && SPI
+
+config MXC_PMIC_MC34704
+	tristate "MC34704 PMIC"
+	depends on ARCH_MXC && I2C
+	select MXC_PMIC
+	  ---help---
+	  This is the MXC MC34704 PMIC support.
+
+config MXC_PMIC_MC9SDZ60
+	tristate "MC9sDZ60 PMIC"
+	depends on ARCH_MXC && I2C
+	select MXC_PMIC
+	  ---help---
+	  This is the MXC MC9sDZ60(MCU) PMIC support.
+
+config MXC_PMIC_CHARDEV
+	tristate "MXC PMIC device interface"
+	depends on MXC_PMIC
+	help
+	  Say Y here to use "pmic" device files, found in the /dev directory
+	  on the system.  They make it possible to have user-space programs
+	  use or controll PMIC. Mainly its useful for notifying PMIC events
+	  to user-space programs.
+
+comment "MXC PMIC Client Drivers"
+	depends on MXC_PMIC
+
+source "drivers/mxc/pmic/mc13783/Kconfig"
+
+source "drivers/mxc/pmic/mc13892/Kconfig"
+
+endmenu
diff --git a/drivers/mxc/pmic/Makefile b/drivers/mxc/pmic/Makefile
new file mode 100644
index 000000000000..385c07e8509f
--- /dev/null
+++ b/drivers/mxc/pmic/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the MXC PMIC drivers.
+#
+
+obj-y				+= core/
+obj-$(CONFIG_MXC_PMIC_MC13783)	+= mc13783/
+obj-$(CONFIG_MXC_PMIC_MC13892)	+= mc13892/
diff --git a/drivers/mxc/pmic/core/Makefile b/drivers/mxc/pmic/core/Makefile
new file mode 100644
index 000000000000..bb42231e3aa8
--- /dev/null
+++ b/drivers/mxc/pmic/core/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for the PMIC core drivers.
+#
+obj-$(CONFIG_MXC_PMIC_MC13783) += pmic_mc13783_mod.o
+pmic_mc13783_mod-objs := pmic_external.o pmic_event.o pmic_common.o pmic_core_spi.o mc13783.o
+
+obj-$(CONFIG_MXC_PMIC_MC13892) += pmic_mc13892_mod.o
+pmic_mc13892_mod-objs := pmic_external.o pmic_event.o pmic_common.o mc13892.o
+
+ifneq ($(CONFIG_MXC_PMIC_SPI),)
+pmic_mc13892_mod-objs += pmic_core_spi.o
+endif
+
+ifneq ($(CONFIG_MXC_PMIC_I2C),)
+pmic_mc13892_mod-objs += pmic_core_i2c.o
+endif
+
+obj-$(CONFIG_MXC_PMIC_MC34704) += pmic_mc34704_mod.o
+pmic_mc34704_mod-objs := pmic_external.o pmic_event.o mc34704.o
+
+obj-$(CONFIG_MXC_PMIC_CHARDEV)	+= pmic-dev.o
diff --git a/drivers/mxc/pmic/core/mc13783.c b/drivers/mxc/pmic/core/mc13783.c
new file mode 100644
index 000000000000..179cad815ebf
--- /dev/null
+++ b/drivers/mxc/pmic/core/mc13783.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic/core/mc13783.c
+ * @brief This file contains MC13783 specific PMIC code. This implementaion
+ * may differ for each PMIC chip.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13783/core.h>
+
+#include <asm/uaccess.h>
+
+#include "pmic.h"
+
+/*
+ * Defines
+ */
+#define EVENT_MASK_0			0x697fdf
+#define EVENT_MASK_1			0x3efffb
+#define MXC_PMIC_FRAME_MASK		0x00FFFFFF
+#define MXC_PMIC_MAX_REG_NUM		0x3F
+#define MXC_PMIC_REG_NUM_SHIFT		0x19
+#define MXC_PMIC_WRITE_BIT_SHIFT	31
+
+static unsigned int events_enabled0 = 0;
+static unsigned int events_enabled1 = 0;
+struct mxc_pmic pmic_drv_data;
+
+/*!
+ * This function is called to read a register on PMIC.
+ *
+ * @param        reg_num     number of the pmic register to be read
+ * @param        reg_val   return value of register
+ *
+ * @return       Returns 0 on success -1 on failure.
+ */
+int pmic_read(unsigned int reg_num, unsigned int *reg_val)
+{
+	unsigned int frame = 0;
+	int ret = 0;
+
+	if (reg_num > MXC_PMIC_MAX_REG_NUM)
+		return PMIC_ERROR;
+
+	frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT;
+
+	ret = spi_rw(pmic_drv_data.spi, (u8 *) & frame, 1);
+
+	*reg_val = frame & MXC_PMIC_FRAME_MASK;
+
+	return ret;
+}
+
+/*!
+ * This function is called to write a value to the register on PMIC.
+ *
+ * @param        reg_num     number of the pmic register to be written
+ * @param        reg_val   value to be written
+ *
+ * @return       Returns 0 on success -1 on failure.
+ */
+int pmic_write(int reg_num, const unsigned int reg_val)
+{
+	unsigned int frame = 0;
+	int ret = 0;
+
+	if (reg_num > MXC_PMIC_MAX_REG_NUM)
+		return PMIC_ERROR;
+
+	frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT);
+
+	frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT;
+
+	frame |= reg_val & MXC_PMIC_FRAME_MASK;
+
+	ret = spi_rw(pmic_drv_data.spi, (u8 *) & frame, 1);
+
+	return ret;
+}
+
+void *pmic_alloc_data(struct device *dev)
+{
+	struct mc13783 *mc13783;
+
+	mc13783 = kzalloc(sizeof(struct mc13783), GFP_KERNEL);
+	if (mc13783 == NULL)
+		return NULL;
+
+	mc13783->dev = dev;
+
+	return (void *)mc13783;
+}
+
+/*!
+ * This function initializes the SPI device parameters for this PMIC.
+ *
+ * @param    spi	the SPI slave device(PMIC)
+ *
+ * @return   None
+ */
+int pmic_spi_setup(struct spi_device *spi)
+{
+	/* Setup the SPI slave i.e.PMIC */
+	pmic_drv_data.spi = spi;
+
+	spi->mode = SPI_MODE_2 | SPI_CS_HIGH;
+	spi->bits_per_word = 32;
+
+	return spi_setup(spi);
+}
+
+/*!
+ * This function initializes the PMIC registers.
+ *
+ * @return   None
+ */
+int pmic_init_registers(void)
+{
+	CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_0, MXC_PMIC_FRAME_MASK));
+	CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_1, MXC_PMIC_FRAME_MASK));
+	CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_0, MXC_PMIC_FRAME_MASK));
+	CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_1, MXC_PMIC_FRAME_MASK));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function returns the PMIC version in system.
+ *
+ * @param 	ver	pointer to the pmic_version_t structure
+ *
+ * @return       This function returns PMIC version.
+ */
+void pmic_get_revision(pmic_version_t * ver)
+{
+	int rev_id = 0;
+	int rev1 = 0;
+	int rev2 = 0;
+	int finid = 0;
+	int icid = 0;
+
+	ver->id = PMIC_MC13783;
+	pmic_read(REG_REVISION, &rev_id);
+
+	rev1 = (rev_id & 0x018) >> 3;
+	rev2 = (rev_id & 0x007);
+	icid = (rev_id & 0x01C0) >> 6;
+	finid = (rev_id & 0x01E00) >> 9;
+
+	/* Ver 0.2 is actually 3.2a.  Report as 3.2 */
+	if ((rev1 == 0) && (rev2 == 2)) {
+		rev1 = 3;
+	}
+
+	if (rev1 == 0 || icid != 2) {
+		ver->revision = -1;
+		printk(KERN_NOTICE
+		       "mc13783: Not detected.\tAccess failed\t!!!\n");
+	} else {
+		ver->revision = ((rev1 * 10) + rev2);
+		printk(KERN_INFO "mc13783 Rev %d.%d FinVer %x detected\n", rev1,
+		       rev2, finid);
+	}
+
+	return;
+
+}
+
+/*!
+ * This function reads the interrupt status registers of PMIC
+ * and determine the current active events.
+ *
+ * @param 	active_events array pointer to be used to return active
+ *		event numbers.
+ *
+ * @return       This function returns PMIC version.
+ */
+unsigned int pmic_get_active_events(unsigned int *active_events)
+{
+	unsigned int count = 0;
+	unsigned int status0, status1;
+	int bit_set;
+
+	pmic_read(REG_INTERRUPT_STATUS_0, &status0);
+	pmic_read(REG_INTERRUPT_STATUS_1, &status1);
+	pmic_write(REG_INTERRUPT_STATUS_0, status0);
+	pmic_write(REG_INTERRUPT_STATUS_1, status1);
+	status0 &= events_enabled0;
+	status1 &= events_enabled1;
+
+	while (status0) {
+		bit_set = ffs(status0) - 1;
+		*(active_events + count) = bit_set;
+		count++;
+		status0 ^= (1 << bit_set);
+	}
+	while (status1) {
+		bit_set = ffs(status1) - 1;
+		*(active_events + count) = bit_set + 24;
+		count++;
+		status1 ^= (1 << bit_set);
+	}
+
+	return count;
+}
+
+/*!
+ * This function unsets a bit in mask register of pmic to unmask an event IT.
+ *
+ * @param	event 	the event to be unmasked
+ *
+ * @return    This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE.
+ */
+int pmic_event_unmask(type_event event)
+{
+	unsigned int event_mask = 0;
+	unsigned int mask_reg = 0;
+	unsigned int event_bit = 0;
+	int ret;
+
+	if (event < EVENT_E1HZI) {
+		mask_reg = REG_INTERRUPT_MASK_0;
+		event_mask = EVENT_MASK_0;
+		event_bit = (1 << event);
+		events_enabled0 |= event_bit;
+	} else {
+		event -= 24;
+		mask_reg = REG_INTERRUPT_MASK_1;
+		event_mask = EVENT_MASK_1;
+		event_bit = (1 << event);
+		events_enabled1 |= event_bit;
+	}
+
+	if ((event_bit & event_mask) == 0) {
+		pr_debug("Error: unmasking a reserved/unused event\n");
+		return PMIC_ERROR;
+	}
+
+	ret = pmic_write_reg(mask_reg, 0, event_bit);
+
+	pr_debug("Enable Event : %d\n", event);
+
+	return ret;
+}
+
+/*!
+ * This function sets a bit in mask register of pmic to disable an event IT.
+ *
+ * @param	event 	the event to be masked
+ *
+ * @return     This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE.
+ */
+int pmic_event_mask(type_event event)
+{
+	unsigned int event_mask = 0;
+	unsigned int mask_reg = 0;
+	unsigned int event_bit = 0;
+	int ret;
+
+	if (event < EVENT_E1HZI) {
+		mask_reg = REG_INTERRUPT_MASK_0;
+		event_mask = EVENT_MASK_0;
+		event_bit = (1 << event);
+		events_enabled0 &= ~event_bit;
+	} else {
+		event -= 24;
+		mask_reg = REG_INTERRUPT_MASK_1;
+		event_mask = EVENT_MASK_1;
+		event_bit = (1 << event);
+		events_enabled1 &= ~event_bit;
+	}
+
+	if ((event_bit & event_mask) == 0) {
+		pr_debug("Error: masking a reserved/unused event\n");
+		return PMIC_ERROR;
+	}
+
+	ret = pmic_write_reg(mask_reg, event_bit, event_bit);
+
+	pr_debug("Disable Event : %d\n", event);
+
+	return ret;
+}
+
+/*!
+ * This function is called to read all sensor bits of PMIC.
+ *
+ * @param        sensor    Sensor to be checked.
+ *
+ * @return       This function returns true if the sensor bit is high;
+ *               or returns false if the sensor bit is low.
+ */
+bool pmic_check_sensor(t_sensor sensor)
+{
+	unsigned int reg_val = 0;
+
+	CHECK_ERROR(pmic_read_reg
+		    (REG_INTERRUPT_SENSE_0, &reg_val, PMIC_ALL_BITS));
+
+	if ((1 << sensor) & reg_val)
+		return true;
+	else
+		return false;
+}
+
+/*!
+ * This function checks one sensor of PMIC.
+ *
+ * @param        sensor_bits  structure of all sensor bits.
+ *
+ * @return    This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE.
+ */
+
+PMIC_STATUS pmic_get_sensors(t_sensor_bits * sensor_bits)
+{
+	int sense_0 = 0;
+	int sense_1 = 0;
+
+	memset(sensor_bits, 0, sizeof(t_sensor_bits));
+
+	pmic_read_reg(REG_INTERRUPT_SENSE_0, &sense_0, 0xffffff);
+	pmic_read_reg(REG_INTERRUPT_SENSE_1, &sense_1, 0xffffff);
+
+	sensor_bits->sense_chgdets = (sense_0 & (1 << 6)) ? true : false;
+	sensor_bits->sense_chgovs = (sense_0 & (1 << 7)) ? true : false;
+	sensor_bits->sense_chgrevs = (sense_0 & (1 << 8)) ? true : false;
+	sensor_bits->sense_chgshorts = (sense_0 & (1 << 9)) ? true : false;
+	sensor_bits->sense_cccvs = (sense_0 & (1 << 10)) ? true : false;
+	sensor_bits->sense_chgcurrs = (sense_0 & (1 << 11)) ? true : false;
+	sensor_bits->sense_bpons = (sense_0 & (1 << 12)) ? true : false;
+	sensor_bits->sense_lobatls = (sense_0 & (1 << 13)) ? true : false;
+	sensor_bits->sense_lobaths = (sense_0 & (1 << 14)) ? true : false;
+	sensor_bits->sense_usb4v4s = (sense_0 & (1 << 16)) ? true : false;
+	sensor_bits->sense_usb2v0s = (sense_0 & (1 << 17)) ? true : false;
+	sensor_bits->sense_usb0v8s = (sense_0 & (1 << 18)) ? true : false;
+	sensor_bits->sense_id_floats = (sense_0 & (1 << 19)) ? true : false;
+	sensor_bits->sense_id_gnds = (sense_0 & (1 << 20)) ? true : false;
+	sensor_bits->sense_se1s = (sense_0 & (1 << 21)) ? true : false;
+	sensor_bits->sense_ckdets = (sense_0 & (1 << 22)) ? true : false;
+
+	sensor_bits->sense_onofd1s = (sense_1 & (1 << 3)) ? true : false;
+	sensor_bits->sense_onofd2s = (sense_1 & (1 << 4)) ? true : false;
+	sensor_bits->sense_onofd3s = (sense_1 & (1 << 5)) ? true : false;
+	sensor_bits->sense_pwrrdys = (sense_1 & (1 << 11)) ? true : false;
+	sensor_bits->sense_thwarnhs = (sense_1 & (1 << 12)) ? true : false;
+	sensor_bits->sense_thwarnls = (sense_1 & (1 << 13)) ? true : false;
+	sensor_bits->sense_clks = (sense_1 & (1 << 14)) ? true : false;
+	sensor_bits->sense_mc2bs = (sense_1 & (1 << 17)) ? true : false;
+	sensor_bits->sense_hsdets = (sense_1 & (1 << 18)) ? true : false;
+	sensor_bits->sense_hsls = (sense_1 & (1 << 19)) ? true : false;
+	sensor_bits->sense_alspths = (sense_1 & (1 << 20)) ? true : false;
+	sensor_bits->sense_ahsshorts = (sense_1 & (1 << 21)) ? true : false;
+	return PMIC_SUCCESS;
+}
+
+EXPORT_SYMBOL(pmic_check_sensor);
+EXPORT_SYMBOL(pmic_get_sensors);
diff --git a/drivers/mxc/pmic/core/mc13892.c b/drivers/mxc/pmic/core/mc13892.c
new file mode 100644
index 000000000000..9f232a4f5718
--- /dev/null
+++ b/drivers/mxc/pmic/core/mc13892.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic/core/mc13892.c
+ * @brief This file contains MC13892 specific PMIC code. This implementaion
+ * may differ for each PMIC chip.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/mfd/mc13892/core.h>
+
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+
+#include "pmic.h"
+
+/*
+ * Defines
+ */
+#define MC13892_I2C_RETRY_TIMES 10
+#define MXC_PMIC_FRAME_MASK		0x00FFFFFF
+#define MXC_PMIC_MAX_REG_NUM		0x3F
+#define MXC_PMIC_REG_NUM_SHIFT		0x19
+#define MXC_PMIC_WRITE_BIT_SHIFT		31
+
+static unsigned int events_enabled0;
+static unsigned int events_enabled1;
+static struct mxc_pmic pmic_drv_data;
+#ifndef CONFIG_MXC_PMIC_I2C
+struct i2c_client *mc13892_client;
+#endif
+
+int pmic_i2c_24bit_read(struct i2c_client *client, unsigned int reg_num,
+			unsigned int *value)
+{
+	unsigned char buf[3];
+	int ret;
+	int i;
+
+	memset(buf, 0, 3);
+	for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) {
+		ret = i2c_smbus_read_i2c_block_data(client, reg_num, 3, buf);
+		if (ret == 3)
+			break;
+		msleep(1);
+	}
+
+	if (ret == 3) {
+		*value = buf[0] << 16 | buf[1] << 8 | buf[2];
+		return ret;
+	} else {
+		pr_err("24bit read error, ret = %d\n", ret);
+		return -1;	/* return -1 on failure */
+	}
+}
+
+int pmic_i2c_24bit_write(struct i2c_client *client,
+			 unsigned int reg_num, unsigned int reg_val)
+{
+	char buf[3];
+	int ret;
+	int i;
+
+	buf[0] = (reg_val >> 16) & 0xff;
+	buf[1] = (reg_val >> 8) & 0xff;
+	buf[2] = (reg_val) & 0xff;
+
+	for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) {
+		ret = i2c_smbus_write_i2c_block_data(client, reg_num, 3, buf);
+		if (ret == 0)
+			break;
+		msleep(1);
+	}
+	if (i == MC13892_I2C_RETRY_TIMES)
+		pr_err("24bit write error, ret = %d\n", ret);
+
+	return ret;
+}
+
+int pmic_read(int reg_num, unsigned int *reg_val)
+{
+	unsigned int frame = 0;
+	int ret = 0;
+
+	if (pmic_drv_data.spi != NULL) {
+		if (reg_num > MXC_PMIC_MAX_REG_NUM)
+			return PMIC_ERROR;
+
+		frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT;
+
+		ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1);
+
+		*reg_val = frame & MXC_PMIC_FRAME_MASK;
+	} else {
+		if (mc13892_client == NULL)
+			return PMIC_ERROR;
+
+		if (pmic_i2c_24bit_read(mc13892_client, reg_num, reg_val) == -1)
+			return PMIC_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+int pmic_write(int reg_num, const unsigned int reg_val)
+{
+	unsigned int frame = 0;
+	int ret = 0;
+
+	if (pmic_drv_data.spi != NULL) {
+		if (reg_num > MXC_PMIC_MAX_REG_NUM)
+			return PMIC_ERROR;
+
+		frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT);
+
+		frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT;
+
+		frame |= reg_val & MXC_PMIC_FRAME_MASK;
+
+		ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1);
+
+		return ret;
+	} else {
+		if (mc13892_client == NULL)
+			return PMIC_ERROR;
+
+		return pmic_i2c_24bit_write(mc13892_client, reg_num, reg_val);
+	}
+}
+
+void *pmic_alloc_data(struct device *dev)
+{
+	struct mc13892 *mc13892;
+
+	mc13892 = kzalloc(sizeof(struct mc13892), GFP_KERNEL);
+	if (mc13892 == NULL)
+		return NULL;
+
+	mc13892->dev = dev;
+
+	return (void *)mc13892;
+}
+
+/*!
+ * This function initializes the SPI device parameters for this PMIC.
+ *
+ * @param    spi	the SPI slave device(PMIC)
+ *
+ * @return   None
+ */
+int pmic_spi_setup(struct spi_device *spi)
+{
+	/* Setup the SPI slave i.e.PMIC */
+	pmic_drv_data.spi = spi;
+
+	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
+	spi->bits_per_word = 32;
+
+	return spi_setup(spi);
+}
+
+int pmic_init_registers(void)
+{
+	CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF));
+	CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF));
+	CHECK_ERROR(pmic_write(REG_INT_STATUS0, 0xFFFFFF));
+	CHECK_ERROR(pmic_write(REG_INT_STATUS1, 0xFFFFFF));
+	/* disable auto charge */
+	if (machine_is_mx51_3ds())
+		CHECK_ERROR(pmic_write(REG_CHARGE, 0xB40003));
+
+	pm_power_off = mc13892_power_off;
+
+	return PMIC_SUCCESS;
+}
+
+unsigned int pmic_get_active_events(unsigned int *active_events)
+{
+	unsigned int count = 0;
+	unsigned int status0, status1;
+	int bit_set;
+
+	pmic_read(REG_INT_STATUS0, &status0);
+	pmic_read(REG_INT_STATUS1, &status1);
+	pmic_write(REG_INT_STATUS0, status0);
+	pmic_write(REG_INT_STATUS1, status1);
+	status0 &= events_enabled0;
+	status1 &= events_enabled1;
+
+	while (status0) {
+		bit_set = ffs(status0) - 1;
+		*(active_events + count) = bit_set;
+		count++;
+		status0 ^= (1 << bit_set);
+	}
+	while (status1) {
+		bit_set = ffs(status1) - 1;
+		*(active_events + count) = bit_set + 24;
+		count++;
+		status1 ^= (1 << bit_set);
+	}
+
+	return count;
+}
+
+#define EVENT_MASK_0			0x387fff
+#define EVENT_MASK_1			0x1177eb
+
+int pmic_event_unmask(type_event event)
+{
+	unsigned int event_mask = 0;
+	unsigned int mask_reg = 0;
+	unsigned int event_bit = 0;
+	int ret;
+
+	if (event < EVENT_1HZI) {
+		mask_reg = REG_INT_MASK0;
+		event_mask = EVENT_MASK_0;
+		event_bit = (1 << event);
+		events_enabled0 |= event_bit;
+	} else {
+		event -= 24;
+		mask_reg = REG_INT_MASK1;
+		event_mask = EVENT_MASK_1;
+		event_bit = (1 << event);
+		events_enabled1 |= event_bit;
+	}
+
+	if ((event_bit & event_mask) == 0) {
+		pr_debug("Error: unmasking a reserved/unused event\n");
+		return PMIC_ERROR;
+	}
+
+	ret = pmic_write_reg(mask_reg, 0, event_bit);
+
+	pr_debug("Enable Event : %d\n", event);
+
+	return ret;
+}
+
+int pmic_event_mask(type_event event)
+{
+	unsigned int event_mask = 0;
+	unsigned int mask_reg = 0;
+	unsigned int event_bit = 0;
+	int ret;
+
+	if (event < EVENT_1HZI) {
+		mask_reg = REG_INT_MASK0;
+		event_mask = EVENT_MASK_0;
+		event_bit = (1 << event);
+		events_enabled0 &= ~event_bit;
+	} else {
+		event -= 24;
+		mask_reg = REG_INT_MASK1;
+		event_mask = EVENT_MASK_1;
+		event_bit = (1 << event);
+		events_enabled1 &= ~event_bit;
+	}
+
+	if ((event_bit & event_mask) == 0) {
+		pr_debug("Error: masking a reserved/unused event\n");
+		return PMIC_ERROR;
+	}
+
+	ret = pmic_write_reg(mask_reg, event_bit, event_bit);
+
+	pr_debug("Disable Event : %d\n", event);
+
+	return ret;
+}
+
+/*!
+ * This function returns the PMIC version in system.
+ *
+ * @param 	ver	pointer to the pmic_version_t structure
+ *
+ * @return       This function returns PMIC version.
+ */
+void pmic_get_revision(pmic_version_t *ver)
+{
+	int rev_id = 0;
+	int rev1 = 0;
+	int rev2 = 0;
+	int finid = 0;
+	int icid = 0;
+
+	ver->id = PMIC_MC13892;
+	pmic_read(REG_IDENTIFICATION, &rev_id);
+
+	rev1 = (rev_id & 0x018) >> 3;
+	rev2 = (rev_id & 0x007);
+	icid = (rev_id & 0x01C0) >> 6;
+	finid = (rev_id & 0x01E00) >> 9;
+
+	ver->revision = ((rev1 * 10) + rev2);
+	printk(KERN_INFO "mc13892 Rev %d.%d FinVer %x detected\n", rev1,
+	       rev2, finid);
+}
+
+void mc13892_power_off(void)
+{
+	unsigned int value;
+
+	pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff);
+
+	value |= 0x000008;
+
+	pmic_write_reg(REG_POWER_CTL0, value, 0xffffff);
+}
diff --git a/drivers/mxc/pmic/core/mc34704.c b/drivers/mxc/pmic/core/mc34704.c
new file mode 100644
index 000000000000..f0ec05afe0ab
--- /dev/null
+++ b/drivers/mxc/pmic/core/mc34704.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic/core/mc34704.c
+ * @brief This file contains MC34704 specific PMIC code.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/mc34704/core.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+
+#include "pmic.h"
+
+/*
+ * Globals
+ */
+static pmic_version_t mxc_pmic_version = {
+	.id = PMIC_MC34704,
+	.revision = 0,
+};
+static unsigned int events_enabled;
+unsigned int active_events[MAX_ACTIVE_EVENTS];
+struct i2c_client *mc34704_client;
+static void pmic_trigger_poll(void);
+
+#define MAX_MC34704_REG 0x59
+static unsigned int mc34704_reg_readonly[MAX_MC34704_REG / 32 + 1] = {
+	(1 << 0x03) || (1 << 0x05) || (1 << 0x07) || (1 << 0x09) ||
+	    (1 << 0x0B) || (1 << 0x0E) || (1 << 0x11) || (1 << 0x14) ||
+	    (1 << 0x17) || (1 << 0x18),
+	0,
+};
+static unsigned int mc34704_reg_written[MAX_MC34704_REG / 32 + 1];
+static unsigned char mc34704_shadow_regs[MAX_MC34704_REG - 1];
+#define IS_READONLY(r) ((1 << ((r) % 32)) & mc34704_reg_readonly[(r) / 32])
+#define WAS_WRITTEN(r) ((1 << ((r) % 32)) & mc34704_reg_written[(r) / 32])
+#define MARK_WRITTEN(r) do { \
+	mc34704_reg_written[(r) / 32] |= (1 << ((r) % 32)); \
+} while (0)
+
+int pmic_read(int reg_nr, unsigned int *reg_val)
+{
+	int c;
+
+	/*
+	 * Use the shadow register if we've written to it
+	 */
+	if (WAS_WRITTEN(reg_nr)) {
+		*reg_val = mc34704_shadow_regs[reg_nr];
+		return PMIC_SUCCESS;
+	}
+
+	/*
+	 * Otherwise, actually read the real register.
+	 * Write-only registers will read as zero.
+	 */
+	c = i2c_smbus_read_byte_data(mc34704_client, reg_nr);
+	if (c == -1) {
+		pr_debug("mc34704: error reading register 0x%02x\n", reg_nr);
+		return PMIC_ERROR;
+	} else {
+		*reg_val = c;
+		return PMIC_SUCCESS;
+	}
+}
+
+int pmic_write(int reg_nr, const unsigned int reg_val)
+{
+	int ret;
+
+	ret = i2c_smbus_write_byte_data(mc34704_client, reg_nr, reg_val);
+	if (ret == -1) {
+		return PMIC_ERROR;
+	} else {
+		/*
+		 * Update our software copy of the register since you
+		 * can't read what you wrote.
+		 */
+		if (!IS_READONLY(reg_nr)) {
+			mc34704_shadow_regs[reg_nr] = reg_val;
+			MARK_WRITTEN(reg_nr);
+		}
+		return PMIC_SUCCESS;
+	}
+}
+
+unsigned int pmic_get_active_events(unsigned int *active_events)
+{
+	unsigned int count = 0;
+	unsigned int faults;
+	int bit_set;
+
+	/* Check for any relevant PMIC faults */
+	pmic_read(REG_MC34704_FAULTS, &faults);
+	faults &= events_enabled;
+
+	/*
+	 * Mask all active events, because there is no way to acknowledge
+	 * or dismiss them in the PMIC -- they're sticky.
+	 */
+	events_enabled &= ~faults;
+
+	/* Account for all unmasked faults */
+	while (faults) {
+		bit_set = ffs(faults) - 1;
+		*(active_events + count) = bit_set;
+		count++;
+		faults ^= (1 << bit_set);
+	}
+	return count;
+}
+
+int pmic_event_unmask(type_event event)
+{
+	unsigned int event_bit = 0;
+	unsigned int prior_events = events_enabled;
+
+	event_bit = (1 << event);
+	events_enabled |= event_bit;
+
+	pr_debug("Enable Event : %d\n", event);
+
+	/* start the polling task as needed */
+	if (events_enabled && prior_events == 0)
+		pmic_trigger_poll();
+
+	return 0;
+}
+
+int pmic_event_mask(type_event event)
+{
+	unsigned int event_bit = 0;
+
+	event_bit = (1 << event);
+	events_enabled &= ~event_bit;
+
+	pr_debug("Disable Event : %d\n", event);
+
+	return 0;
+}
+
+/*!
+ * PMIC event polling task.  This task is called periodically to poll
+ * for possible MC34704 events (No interrupt supplied by the hardware).
+ */
+static void pmic_event_task(struct work_struct *work);
+DECLARE_DELAYED_WORK(pmic_ws, pmic_event_task);
+
+static void pmic_trigger_poll(void)
+{
+	schedule_delayed_work(&pmic_ws, HZ / 10);
+}
+
+static void pmic_event_task(struct work_struct *work)
+{
+	unsigned int count = 0;
+	int i;
+
+	count = pmic_get_active_events(active_events);
+	pr_debug("active events number %d\n", count);
+
+	/* call handlers for all active events */
+	for (i = 0; i < count; i++)
+		pmic_event_callback(active_events[i]);
+
+	/* re-trigger this task, but only if somebody is watching */
+	if (events_enabled)
+		pmic_trigger_poll();
+
+	return;
+}
+
+pmic_version_t pmic_get_version(void)
+{
+	return mxc_pmic_version;
+}
+EXPORT_SYMBOL(pmic_get_version);
+
+int __devinit pmic_init_registers(void)
+{
+	/*
+	 * Set some registers to what they should be,
+	 * if for no other reason than to initialize our
+	 * software register copies.
+	 */
+	CHECK_ERROR(pmic_write(REG_MC34704_GENERAL2, 0x09));
+	CHECK_ERROR(pmic_write(REG_MC34704_VGSET1, 0));
+	CHECK_ERROR(pmic_write(REG_MC34704_REG2SET1, 0));
+	CHECK_ERROR(pmic_write(REG_MC34704_REG3SET1, 0));
+	CHECK_ERROR(pmic_write(REG_MC34704_REG4SET1, 0));
+	CHECK_ERROR(pmic_write(REG_MC34704_REG5SET1, 0));
+
+	return PMIC_SUCCESS;
+}
+
+static int __devinit is_chip_onboard(struct i2c_client *client)
+{
+	int val;
+
+	/*
+	 * This PMIC has no version or ID register, so just see
+	 * if it ACK's and returns 0 on some write-only register as
+	 * evidence of its presence.
+	 */
+	val = i2c_smbus_read_byte_data(client, REG_MC34704_GENERAL2);
+	if (val != 0)
+		return -1;
+
+	return 0;
+}
+
+static int __devinit pmic_probe(struct i2c_client *client,
+				const struct i2c_device_id *id)
+{
+	int ret = 0;
+	struct mc34704 *mc34704;
+	struct mc34704_platform_data *plat_data = client->dev.platform_data;
+
+	if (!plat_data || !plat_data->init)
+		return -ENODEV;
+
+	ret = is_chip_onboard(client);
+
+	if (ret == -1)
+		return -ENODEV;
+
+	mc34704 = kzalloc(sizeof(struct mc34704), GFP_KERNEL);
+	if (mc34704 == NULL)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, mc34704);
+	mc34704->dev = &client->dev;
+	mc34704->i2c_client = client;
+
+	mc34704_client = client;
+
+	/* Initialize the PMIC event handling */
+	pmic_event_list_init();
+
+	/* Initialize PMI registers */
+	if (pmic_init_registers() != PMIC_SUCCESS)
+		return PMIC_ERROR;
+
+	ret = plat_data->init(mc34704);
+	if (ret != 0)
+		return PMIC_ERROR;
+
+	dev_info(&client->dev, "Loaded\n");
+
+	return PMIC_SUCCESS;
+}
+
+static int pmic_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static int pmic_suspend(struct i2c_client *client, pm_message_t state)
+{
+	return 0;
+}
+
+static int pmic_resume(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id mc34704_id[] = {
+	{"mc34704", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, mc34704_id);
+
+static struct i2c_driver pmic_driver = {
+	.driver = {
+		   .name = "mc34704",
+		   .bus = NULL,
+		   },
+	.probe = pmic_probe,
+	.remove = pmic_remove,
+	.suspend = pmic_suspend,
+	.resume = pmic_resume,
+	.id_table = mc34704_id,
+};
+
+static int __init pmic_init(void)
+{
+	return i2c_add_driver(&pmic_driver);
+}
+
+static void __exit pmic_exit(void)
+{
+	i2c_del_driver(&pmic_driver);
+}
+
+/*
+ * Module entry points
+ */
+subsys_initcall_sync(pmic_init);
+module_exit(pmic_exit);
+
+MODULE_DESCRIPTION("MC34704 PMIC driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/core/pmic-dev.c b/drivers/mxc/pmic/core/pmic-dev.c
new file mode 100644
index 000000000000..1cb7ce311338
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic-dev.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All rights reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic-dev.c
+ * @brief This provides /dev interface to the user program. They make it
+ * possible to have user-space programs use or control PMIC. Mainly its
+ * useful for notifying PMIC events to user-space programs.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/kdev_t.h>
+#include <linux/circ_buf.h>
+#include <linux/major.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/pmic_external.h>
+
+#include <asm/uaccess.h>
+
+#define PMIC_NAME	"pmic"
+#define CIRC_BUF_MAX	16
+#define CIRC_ADD(elem,cir_buf,size)				\
+	down(&event_mutex);					\
+	if(CIRC_SPACE(cir_buf.head, cir_buf.tail, size)){	\
+		cir_buf.buf[cir_buf.head] = (char)elem;		\
+		cir_buf.head = (cir_buf.head + 1) & (size - 1);	\
+	} else {						\
+		pr_info("Failed to notify event to the user\n");\
+	}							\
+	up(&event_mutex);
+
+#define CIRC_REMOVE(elem,cir_buf,size)				\
+	down(&event_mutex);					\
+	if(CIRC_CNT(cir_buf.head, cir_buf.tail, size)){         \
+		elem = (int)cir_buf.buf[cir_buf.tail];          \
+		cir_buf.tail = (cir_buf.tail + 1) & (size - 1); \
+	} else {                                                \
+		elem = -1;                                      \
+		pr_info("No valid notified event\n");           \
+	}							\
+	up(&event_mutex);
+
+static int pmic_major;
+static struct class *pmic_class;
+static struct fasync_struct *pmic_dev_queue;
+
+static DECLARE_MUTEX(event_mutex);
+static struct circ_buf pmic_events;
+
+static void callbackfn(void *event)
+{
+	printk(KERN_INFO "\n\n DETECTED PMIC EVENT : %d\n\n",
+	       (unsigned int)event);
+}
+
+static void user_notify_callback(void *event)
+{
+	CIRC_ADD((int)event, pmic_events, CIRC_BUF_MAX);
+	kill_fasync(&pmic_dev_queue, SIGIO, POLL_IN);
+}
+
+/*!
+ * This function implements IOCTL controls on a PMIC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_dev_ioctl(struct inode *inode, struct file *file,
+			  unsigned int cmd, unsigned long arg)
+{
+	register_info reg_info;
+	pmic_event_callback_t event_sub;
+	type_event event;
+	int ret = 0;
+
+	if (_IOC_TYPE(cmd) != 'P')
+		return -ENOTTY;
+
+	switch (cmd) {
+	case PMIC_READ_REG:
+		if (copy_from_user(&reg_info, (register_info *) arg,
+				   sizeof(register_info))) {
+			return -EFAULT;
+		}
+		ret =
+		    pmic_read_reg(reg_info.reg, &(reg_info.reg_value),
+				  0x00ffffff);
+		pr_debug("read reg %d %x\n", reg_info.reg, reg_info.reg_value);
+		if (copy_to_user((register_info *) arg, &reg_info,
+				 sizeof(register_info))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_WRITE_REG:
+		if (copy_from_user(&reg_info, (register_info *) arg,
+				   sizeof(register_info))) {
+			return -EFAULT;
+		}
+		ret =
+		    pmic_write_reg(reg_info.reg, reg_info.reg_value,
+				   0x00ffffff);
+		pr_debug("write reg %d %x\n", reg_info.reg, reg_info.reg_value);
+		if (copy_to_user((register_info *) arg, &reg_info,
+				 sizeof(register_info))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_SUBSCRIBE:
+		if (get_user(event, (int __user *)arg)) {
+			return -EFAULT;
+		}
+		event_sub.func = callbackfn;
+		event_sub.param = (void *)event;
+		ret = pmic_event_subscribe(event, event_sub);
+		pr_debug("subscribe done\n");
+		break;
+
+	case PMIC_UNSUBSCRIBE:
+		if (get_user(event, (int __user *)arg)) {
+			return -EFAULT;
+		}
+		event_sub.func = callbackfn;
+		event_sub.param = (void *)event;
+		ret = pmic_event_unsubscribe(event, event_sub);
+		pr_debug("unsubscribe done\n");
+		break;
+
+	case PMIC_NOTIFY_USER:
+		if (get_user(event, (int __user *)arg)) {
+			return -EFAULT;
+		}
+		event_sub.func = user_notify_callback;
+		event_sub.param = (void *)event;
+		ret = pmic_event_subscribe(event, event_sub);
+		break;
+
+	case PMIC_GET_NOTIFY:
+		CIRC_REMOVE(event, pmic_events, CIRC_BUF_MAX);
+		if (put_user(event, (int __user *)arg)) {
+			return -EFAULT;
+		}
+		break;
+
+	default:
+		printk(KERN_ERR "%d unsupported ioctl command\n", (int)cmd);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function implements the open method on a PMIC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_dev_open(struct inode *inode, struct file *file)
+{
+	pr_debug("open\n");
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function implements the release method on a PMIC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ *
+ * @return       This function returns 0.
+ */
+static int pmic_dev_free(struct inode *inode, struct file *file)
+{
+	pr_debug("free\n");
+	return PMIC_SUCCESS;
+}
+
+static int pmic_dev_fasync(int fd, struct file *filp, int mode)
+{
+	return fasync_helper(fd, filp, mode, &pmic_dev_queue);
+}
+
+/*!
+ * This structure defines file operations for a PMIC device.
+ */
+static struct file_operations pmic_fops = {
+	/*!
+	 * the owner
+	 */
+	.owner = THIS_MODULE,
+	/*!
+	 * the ioctl operation
+	 */
+	.ioctl = pmic_dev_ioctl,
+	/*!
+	 * the open operation
+	 */
+	.open = pmic_dev_open,
+	/*!
+	 * the release operation
+	 */
+	.release = pmic_dev_free,
+	/*!
+	 * the release operation
+	 */
+	.fasync = pmic_dev_fasync,
+};
+
+/*!
+ * This function implements the init function of the PMIC char device.
+ * This function is called when the module is loaded. It registers
+ * the character device for PMIC to be used by user-space programs.
+ *
+ * @return       This function returns 0.
+ */
+static int __init pmic_dev_init(void)
+{
+	int ret = 0;
+	struct device *pmic_device;
+	pmic_version_t pmic_ver;
+
+	pmic_ver = pmic_get_version();
+	if (pmic_ver.revision < 0) {
+		printk(KERN_ERR "No PMIC device found\n");
+		return -ENODEV;
+	}
+
+	pmic_major = register_chrdev(0, PMIC_NAME, &pmic_fops);
+	if (pmic_major < 0) {
+		printk(KERN_ERR "unable to get a major for pmic\n");
+		return pmic_major;
+	}
+
+	pmic_class = class_create(THIS_MODULE, PMIC_NAME);
+	if (IS_ERR(pmic_class)) {
+		printk(KERN_ERR "Error creating pmic class.\n");
+		ret = PMIC_ERROR;
+		goto err;
+	}
+
+	pmic_device = device_create(pmic_class, NULL, MKDEV(pmic_major, 0), NULL,
+				    PMIC_NAME);
+	if (IS_ERR(pmic_device)) {
+		printk(KERN_ERR "Error creating pmic class device.\n");
+		ret = PMIC_ERROR;
+		goto err1;
+	}
+
+	pmic_events.buf = kmalloc(CIRC_BUF_MAX * sizeof(char), GFP_KERNEL);
+	if (NULL == pmic_events.buf) {
+		ret = -ENOMEM;
+		goto err2;
+	}
+	pmic_events.head = pmic_events.tail = 0;
+
+	printk(KERN_INFO "PMIC Character device: successfully loaded\n");
+	return ret;
+      err2:
+	device_destroy(pmic_class, MKDEV(pmic_major, 0));
+      err1:
+	class_destroy(pmic_class);
+      err:
+	unregister_chrdev(pmic_major, PMIC_NAME);
+	return ret;
+
+}
+
+/*!
+ * This function implements the exit function of the PMIC character device.
+ * This function is called when the module is unloaded. It unregisters
+ * the PMIC character device.
+ *
+ */
+static void __exit pmic_dev_exit(void)
+{
+	device_destroy(pmic_class, MKDEV(pmic_major, 0));
+	class_destroy(pmic_class);
+
+	unregister_chrdev(pmic_major, PMIC_NAME);
+
+	printk(KERN_INFO "PMIC Character device: successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+module_init(pmic_dev_init);
+module_exit(pmic_dev_exit);
+
+MODULE_DESCRIPTION("PMIC Protocol /dev entries driver");
+MODULE_AUTHOR("FreeScale");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/core/pmic.h b/drivers/mxc/pmic/core/pmic.h
new file mode 100644
index 000000000000..770fbb72a044
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __PMIC_H__
+#define __PMIC_H__
+
+ /*!
+  * @file pmic.h
+  * @brief This file contains prototypes of all the functions to be
+  * defined for each PMIC chip. The implementation of these may differ
+  * from PMIC chip to PMIC chip.
+  *
+  * @ingroup PMIC_CORE
+  */
+
+#include <linux/spi/spi.h>
+
+#define MAX_ACTIVE_EVENTS		10
+
+/*!
+ * This structure is a way for the PMIC core driver to define their own
+ * \b spi_device structure. This structure includes the core \b spi_device
+ * structure that is provided by Linux SPI Framework/driver as an
+ * element and may contain other elements that are required by core driver.
+ */
+struct mxc_pmic {
+	/*!
+	 * Master side proxy for an SPI slave device(PMIC)
+	 */
+	struct spi_device *spi;
+};
+
+/*!
+ * This function is called to transfer data to PMIC on SPI.
+ *
+ * @param    spi	the SPI slave device(PMIC)
+ * @param    buf   	the pointer to the data buffer
+ * @param    len    	the length of the data to be transferred
+ *
+ * @return   Returns 0 on success -1 on failure.
+ */
+static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
+{
+	struct spi_transfer t = {
+		.tx_buf = (const void *)buf,
+		.rx_buf = buf,
+		.len = len,
+		.cs_change = 0,
+		.delay_usecs = 0,
+	};
+	struct spi_message m;
+
+	spi_message_init(&m);
+	spi_message_add_tail(&t, &m);
+	if (spi_sync(spi, &m) != 0 || m.status != 0)
+		return PMIC_ERROR;
+	return (len - m.actual_length);
+}
+
+/*!
+ * This function returns the PMIC version in system.
+ *
+ * @param 	ver	pointer to the pmic_version_t structure
+ *
+ * @return       This function returns PMIC version.
+ */
+void pmic_get_revision(pmic_version_t * ver);
+
+/*!
+ * This function initializes the SPI device parameters for this PMIC.
+ *
+ * @param    spi	the SPI slave device(PMIC)
+ *
+ * @return   None
+ */
+int pmic_spi_setup(struct spi_device *spi);
+
+/*!
+ * This function initializes the PMIC registers.
+ *
+ * @return   None
+ */
+int pmic_init_registers(void);
+
+/*!
+ * This function reads the interrupt status registers of PMIC
+ * and determine the current active events.
+ *
+ * @param 	active_events array pointer to be used to return active
+ *		event numbers.
+ *
+ * @return       This function returns PMIC version.
+ */
+unsigned int pmic_get_active_events(unsigned int *active_events);
+
+/*!
+ * This function sets a bit in mask register of pmic to disable an event IT.
+ *
+ * @param	event 	the event to be masked
+ *
+ * @return     This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE.
+ */
+int pmic_event_mask(type_event event);
+
+/*!
+ * This function unsets a bit in mask register of pmic to unmask an event IT.
+ *
+ * @param	event 	the event to be unmasked
+ *
+ * @return    This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE.
+ */
+int pmic_event_unmask(type_event event);
+
+#ifdef CONFIG_MXC_PMIC_FIXARB
+extern PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi);
+#else
+static inline PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi)
+{
+	return PMIC_SUCCESS;
+}
+#endif
+
+void *pmic_alloc_data(struct device *dev);
+
+int pmic_start_event_thread(int irq_num);
+
+void pmic_stop_event_thread(void);
+
+#endif				/* __PMIC_H__ */
diff --git a/drivers/mxc/pmic/core/pmic_common.c b/drivers/mxc/pmic/core/pmic_common.c
new file mode 100644
index 000000000000..fe907ead762c
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic_common.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic_common.c
+ * @brief This is the common file for the PMIC Core/Protocol driver.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kthread.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+
+#include <asm/uaccess.h>
+
+#include "pmic.h"
+
+/*
+ * Global variables
+ */
+pmic_version_t mxc_pmic_version;
+unsigned int active_events[MAX_ACTIVE_EVENTS];
+
+
+static struct completion event_completion;
+static struct task_struct *tstask;
+
+static int pmic_event_thread_func(void *v)
+{
+	unsigned int loop;
+	unsigned int count = 0;
+	unsigned int irq = (int)v;
+
+	while (1) {
+		wait_for_completion_interruptible(
+				&event_completion);
+		if (kthread_should_stop())
+			break;
+
+		count = pmic_get_active_events(
+				active_events);
+		pr_debug("active events number %d\n", count);
+
+		for (loop = 0; loop < count; loop++)
+			pmic_event_callback(
+				active_events[loop]);
+		enable_irq(irq);
+	}
+
+	return 0;
+}
+
+int pmic_start_event_thread(int irq_num)
+{
+	int ret = 0;
+
+	if (tstask)
+		return ret;
+
+	init_completion(&event_completion);
+
+	tstask = kthread_run(pmic_event_thread_func,
+		(void *)irq_num, "pmic-event-thread");
+	ret = IS_ERR(tstask) ? -1 : 0;
+	if (IS_ERR(tstask))
+		tstask = NULL;
+	return ret;
+}
+
+void pmic_stop_event_thread(void)
+{
+	if (tstask) {
+		complete(&event_completion);
+		kthread_stop(tstask);
+	}
+}
+
+/*!
+ * This function is called when pmic interrupt occurs on the processor.
+ * It is the interrupt handler for the pmic module.
+ *
+ * @param        irq        the irq number
+ * @param        dev_id     the pointer on the device
+ *
+ * @return       The function returns IRQ_HANDLED when handled.
+ */
+irqreturn_t pmic_irq_handler(int irq, void *dev_id)
+{
+	disable_irq_nosync(irq);
+	complete(&event_completion);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to determine the PMIC type and its revision.
+ *
+ * @return      Returns the PMIC type and its revision.
+ */
+
+pmic_version_t pmic_get_version(void)
+{
+	return mxc_pmic_version;
+}
+EXPORT_SYMBOL(pmic_get_version);
diff --git a/drivers/mxc/pmic/core/pmic_core_i2c.c b/drivers/mxc/pmic/core/pmic_core_i2c.c
new file mode 100644
index 000000000000..d2f982efb2a1
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic_core_i2c.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic_core_i2c.c
+ * @brief This is the main file for the PMIC Core/Protocol driver. i2c
+ * should be providing the interface between the PMIC and the MCU.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
+#include <linux/mfd/mc13892/core.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+
+#include <asm/uaccess.h>
+#include <mach/hardware.h>
+
+#include "pmic.h"
+
+#define MC13892_GENERATION_ID_LSH	6
+#define MC13892_IC_ID_LSH		13
+
+#define MC13892_GENERATION_ID_WID	3
+#define MC13892_IC_ID_WID		6
+
+#define MC13892_GEN_ID_VALUE	0x7
+#define MC13892_IC_ID_VALUE		1
+
+/*
+ * Global variables
+ */
+struct i2c_client *mc13892_client;
+
+extern pmic_version_t mxc_pmic_version;
+extern irqreturn_t pmic_irq_handler(int irq, void *dev_id);
+/*
+ * Platform device structure for PMIC client drivers
+ */
+static struct platform_device adc_ldm = {
+	.name = "pmic_adc",
+	.id = 1,
+};
+static struct platform_device battery_ldm = {
+	.name = "pmic_battery",
+	.id = 1,
+};
+static struct platform_device power_ldm = {
+	.name = "pmic_power",
+	.id = 1,
+};
+static struct platform_device rtc_ldm = {
+	.name = "pmic_rtc",
+	.id = 1,
+};
+static struct platform_device light_ldm = {
+	.name = "pmic_light",
+	.id = 1,
+};
+static struct platform_device rleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'r',
+};
+static struct platform_device gleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'g',
+};
+static struct platform_device bleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'b',
+};
+
+static void pmic_pdev_register(struct device *dev)
+{
+	platform_device_register(&adc_ldm);
+
+	if (!cpu_is_mx53())
+		platform_device_register(&battery_ldm);
+
+	platform_device_register(&rtc_ldm);
+	platform_device_register(&power_ldm);
+	platform_device_register(&light_ldm);
+	platform_device_register(&rleds_ldm);
+	platform_device_register(&gleds_ldm);
+	platform_device_register(&bleds_ldm);
+}
+
+/*!
+ * This function unregisters platform device structures for
+ * PMIC client drivers.
+ */
+static void pmic_pdev_unregister(void)
+{
+	platform_device_unregister(&adc_ldm);
+	platform_device_unregister(&battery_ldm);
+	platform_device_unregister(&rtc_ldm);
+	platform_device_unregister(&power_ldm);
+	platform_device_unregister(&light_ldm);
+}
+
+static int __devinit is_chip_onboard(struct i2c_client *client)
+{
+	unsigned int ret = 0;
+
+	/*bind the right device to the driver */
+	if (pmic_i2c_24bit_read(client, REG_IDENTIFICATION, &ret) == -1)
+		return -1;
+
+	if (MC13892_GEN_ID_VALUE != BITFEXT(ret, MC13892_GENERATION_ID)) {
+		/*compare the address value */
+		dev_err(&client->dev,
+			"read generation ID 0x%x is not equal to 0x%x!\n",
+			BITFEXT(ret, MC13892_GENERATION_ID),
+			MC13892_GEN_ID_VALUE);
+		return -1;
+	}
+
+	return 0;
+}
+
+static ssize_t mc13892_show(struct device *dev,
+			    struct device_attribute *attr, char *buf)
+{
+	int i, value;
+	int offset = (REG_TEST4 + 1) / 4;
+
+	for (i = 0; i < offset; i++) {
+		pmic_read(i, &value);
+		pr_info("reg%02d: %06x\t\t", i, value);
+		pmic_read(i + offset, &value);
+		pr_info("reg%02d: %06x\t\t", i + offset, value);
+		pmic_read(i + offset * 2, &value);
+		pr_info("reg%02d: %06x\t\t", i + offset * 2, value);
+		pmic_read(i + offset * 3, &value);
+		pr_info("reg%02d: %06x\n", i + offset * 3, value);
+	}
+
+	return 0;
+}
+
+static ssize_t mc13892_store(struct device *dev,
+			     struct device_attribute *attr, const char *buf,
+			     size_t count)
+{
+	int reg, value, ret;
+	char *p;
+
+	reg = simple_strtoul(buf, NULL, 10);
+
+	p = NULL;
+	p = memchr(buf, ' ', count);
+
+	if (p == NULL) {
+		pmic_read(reg, &value);
+		pr_debug("reg%02d: %06x\n", reg, value);
+		return count;
+	}
+
+	p += 1;
+
+	value = simple_strtoul(p, NULL, 16);
+
+	ret = pmic_write(reg, value);
+	if (ret == 0)
+		pr_debug("write reg%02d: %06x\n", reg, value);
+	else
+		pr_debug("register update failed\n");
+
+	return count;
+}
+
+static struct device_attribute mc13892_dev_attr = {
+	.attr = {
+		 .name = "mc13892_ctl",
+		 .mode = S_IRUSR | S_IWUSR,
+		 },
+	.show = mc13892_show,
+	.store = mc13892_store,
+};
+
+static int __devinit pmic_probe(struct i2c_client *client,
+				const struct i2c_device_id *id)
+{
+	int ret = 0;
+	int pmic_irq;
+	struct mc13892 *mc13892;
+	struct mc13892_platform_data *plat_data = client->dev.platform_data;
+
+	ret = is_chip_onboard(client);
+	if (ret == -1)
+		return -ENODEV;
+
+	mc13892 = kzalloc(sizeof(struct mc13892), GFP_KERNEL);
+	if (mc13892 == NULL)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, mc13892);
+	mc13892->dev = &client->dev;
+	mc13892->i2c_client = client;
+
+	/* so far, we got matched chip on board */
+
+	mc13892_client = client;
+
+	/* Initialize the PMIC event handling */
+	pmic_event_list_init();
+
+	/* Initialize GPIO for PMIC Interrupt */
+	gpio_pmic_active();
+
+	/* Get the PMIC Version */
+	pmic_get_revision(&mxc_pmic_version);
+	if (mxc_pmic_version.revision < 0) {
+		dev_err((struct device *)client,
+			"PMIC not detected!!! Access Failed\n");
+		return -ENODEV;
+	} else {
+		dev_dbg((struct device *)client,
+			"Detected pmic core IC version number is %d\n",
+			mxc_pmic_version.revision);
+	}
+
+	/* Initialize the PMIC parameters */
+	ret = pmic_init_registers();
+	if (ret != PMIC_SUCCESS)
+		return PMIC_ERROR;
+
+	pmic_irq = (int)(client->irq);
+	if (pmic_irq == 0)
+		return PMIC_ERROR;
+
+	ret = pmic_start_event_thread(pmic_irq);
+	if (ret) {
+		pr_err("mc13892 pmic driver init: \
+			fail to start event thread\n");
+		return PMIC_ERROR;
+	}
+
+	/* Set and install PMIC IRQ handler */
+
+	set_irq_type(pmic_irq, IRQF_TRIGGER_HIGH);
+
+	ret =
+	    request_irq(pmic_irq, pmic_irq_handler, 0, "PMIC_IRQ",
+			0);
+
+	if (ret) {
+		dev_err(&client->dev, "request irq %d error!\n", pmic_irq);
+		return ret;
+	}
+	enable_irq_wake(pmic_irq);
+
+	if (plat_data && plat_data->init) {
+		ret = plat_data->init(mc13892);
+		if (ret != 0)
+			return PMIC_ERROR;
+	}
+
+	ret = device_create_file(&client->dev, &mc13892_dev_attr);
+	if (ret)
+		dev_err(&client->dev, "create device file failed!\n");
+
+	pmic_pdev_register(&client->dev);
+
+	dev_info(&client->dev, "Loaded\n");
+
+	return PMIC_SUCCESS;
+}
+
+static int pmic_remove(struct i2c_client *client)
+{
+	int pmic_irq = (int)(client->irq);
+
+	pmic_stop_event_thread();
+	free_irq(pmic_irq, 0);
+	pmic_pdev_unregister();
+	return 0;
+}
+
+static int pmic_suspend(struct i2c_client *client, pm_message_t state)
+{
+	return 0;
+}
+
+static int pmic_resume(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id mc13892_id[] = {
+	{"mc13892", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, mc13892_id);
+
+static struct i2c_driver pmic_driver = {
+	.driver = {
+		   .name = "mc13892",
+		   .bus = NULL,
+		   },
+	.probe = pmic_probe,
+	.remove = pmic_remove,
+	.suspend = pmic_suspend,
+	.resume = pmic_resume,
+	.id_table = mc13892_id,
+};
+
+static int __init pmic_init(void)
+{
+	return i2c_add_driver(&pmic_driver);
+}
+
+static void __exit pmic_exit(void)
+{
+	i2c_del_driver(&pmic_driver);
+}
+
+/*
+ * Module entry points
+ */
+subsys_initcall_sync(pmic_init);
+module_exit(pmic_exit);
+
+MODULE_DESCRIPTION("Core/Protocol driver for PMIC");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/core/pmic_core_spi.c b/drivers/mxc/pmic/core/pmic_core_spi.c
new file mode 100644
index 000000000000..300ae9aafdaa
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic_core_spi.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic_core_spi.c
+ * @brief This is the main file for the PMIC Core/Protocol driver. SPI
+ * should be providing the interface between the PMIC and the MCU.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/spi/spi.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+
+#include <asm/uaccess.h>
+
+#include "pmic.h"
+
+/*
+ * Static functions
+ */
+static void pmic_pdev_register(void);
+static void pmic_pdev_unregister(void);
+
+/*
+ * Platform device structure for PMIC client drivers
+ */
+static struct platform_device adc_ldm = {
+	.name = "pmic_adc",
+	.id = 1,
+};
+static struct platform_device battery_ldm = {
+	.name = "pmic_battery",
+	.id = 1,
+};
+static struct platform_device power_ldm = {
+	.name = "pmic_power",
+	.id = 1,
+};
+static struct platform_device rtc_ldm = {
+	.name = "pmic_rtc",
+	.id = 1,
+};
+static struct platform_device light_ldm = {
+	.name = "pmic_light",
+	.id = 1,
+};
+static struct platform_device rleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'r',
+};
+static struct platform_device gleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'g',
+};
+static struct platform_device bleds_ldm = {
+	.name = "pmic_leds",
+	.id = 'b',
+};
+
+/*
+ * External functions
+ */
+extern void pmic_event_list_init(void);
+extern void pmic_event_callback(type_event event);
+extern void gpio_pmic_active(void);
+extern irqreturn_t pmic_irq_handler(int irq, void *dev_id);
+extern pmic_version_t mxc_pmic_version;
+
+/*!
+ * This function registers platform device structures for
+ * PMIC client drivers.
+ */
+static void pmic_pdev_register(void)
+{
+	platform_device_register(&adc_ldm);
+	platform_device_register(&battery_ldm);
+	platform_device_register(&rtc_ldm);
+	platform_device_register(&power_ldm);
+	platform_device_register(&light_ldm);
+	platform_device_register(&rleds_ldm);
+	platform_device_register(&gleds_ldm);
+	platform_device_register(&bleds_ldm);
+}
+
+/*!
+ * This function unregisters platform device structures for
+ * PMIC client drivers.
+ */
+static void pmic_pdev_unregister(void)
+{
+	platform_device_unregister(&adc_ldm);
+	platform_device_unregister(&battery_ldm);
+	platform_device_unregister(&rtc_ldm);
+	platform_device_unregister(&power_ldm);
+	platform_device_unregister(&light_ldm);
+}
+
+/*!
+ * This function puts the SPI slave device in low-power mode/state.
+ *
+ * @param	spi	the SPI slave device
+ * @param	message	the power state to enter
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int pmic_suspend(struct spi_device *spi, pm_message_t message)
+{
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function brings the SPI slave device back from low-power mode/state.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int pmic_resume(struct spi_device *spi)
+{
+	return PMIC_SUCCESS;
+}
+
+static struct spi_driver pmic_driver;
+
+/*!
+ * This function is called whenever the SPI slave device is detected.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int __devinit pmic_probe(struct spi_device *spi)
+{
+	int ret = 0;
+	struct pmic_platform_data *plat_data = spi->dev.platform_data;
+
+	/* Initialize the PMIC parameters */
+	ret = pmic_spi_setup(spi);
+	if (ret != PMIC_SUCCESS) {
+		return PMIC_ERROR;
+	}
+
+	/* Initialize the PMIC event handling */
+	pmic_event_list_init();
+
+	/* Initialize GPIO for PMIC Interrupt */
+	gpio_pmic_active();
+
+	/* Get the PMIC Version */
+	pmic_get_revision(&mxc_pmic_version);
+	if (mxc_pmic_version.revision < 0) {
+		dev_err((struct device *)spi,
+			"PMIC not detected!!! Access Failed\n");
+		return -ENODEV;
+	} else {
+		dev_dbg((struct device *)spi,
+			"Detected pmic core IC version number is %d\n",
+			mxc_pmic_version.revision);
+	}
+
+	spi_set_drvdata(spi, pmic_alloc_data(&(spi->dev)));
+
+	/* Initialize the PMIC parameters */
+	ret = pmic_init_registers();
+	if (ret != PMIC_SUCCESS) {
+		kfree(spi_get_drvdata(spi));
+		spi_set_drvdata(spi, NULL);
+		return PMIC_ERROR;
+	}
+
+	ret = pmic_start_event_thread(spi->irq);
+	if (ret) {
+		pr_err("mc13892 pmic driver init: \
+			fail to start event thread\n");
+		kfree(spi_get_drvdata(spi));
+		spi_set_drvdata(spi, NULL);
+		return PMIC_ERROR;
+	}
+
+	/* Set and install PMIC IRQ handler */
+	set_irq_type(spi->irq, IRQF_TRIGGER_HIGH);
+	ret = request_irq(spi->irq, pmic_irq_handler, 0, "PMIC_IRQ", 0);
+	if (ret) {
+		kfree(spi_get_drvdata(spi));
+		spi_set_drvdata(spi, NULL);
+		dev_err((struct device *)spi, "gpio1: irq%d error.", spi->irq);
+		return ret;
+	}
+
+	enable_irq_wake(spi->irq);
+
+	if (plat_data && plat_data->init) {
+		ret = plat_data->init(spi_get_drvdata(spi));
+		if (ret != 0) {
+			kfree(spi_get_drvdata(spi));
+			spi_set_drvdata(spi, NULL);
+			return PMIC_ERROR;
+		}
+	}
+
+	power_ldm.dev.platform_data = spi->dev.platform_data;
+
+	pmic_pdev_register();
+
+	printk(KERN_INFO "Device %s probed\n", dev_name(&spi->dev));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is called whenever the SPI slave device is removed.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int __devexit pmic_remove(struct spi_device *spi)
+{
+	pmic_stop_event_thread();
+	free_irq(spi->irq, 0);
+
+	pmic_pdev_unregister();
+
+	printk(KERN_INFO "Device %s removed\n", dev_name(&spi->dev));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct spi_driver pmic_driver = {
+	.driver = {
+		   .name = "pmic_spi",
+		   .bus = &spi_bus_type,
+		   .owner = THIS_MODULE,
+		   },
+	.probe = pmic_probe,
+	.remove = __devexit_p(pmic_remove),
+	.suspend = pmic_suspend,
+	.resume = pmic_resume,
+};
+
+/*
+ * Initialization and Exit
+ */
+
+/*!
+ * This function implements the init function of the PMIC device.
+ * This function is called when the module is loaded. It registers
+ * the PMIC Protocol driver.
+ *
+ * @return       This function returns 0.
+ */
+static int __init pmic_init(void)
+{
+	return spi_register_driver(&pmic_driver);
+}
+
+/*!
+ * This function implements the exit function of the PMIC device.
+ * This function is called when the module is unloaded. It unregisters
+ * the PMIC Protocol driver.
+ *
+ */
+static void __exit pmic_exit(void)
+{
+	pr_debug("Unregistering the PMIC Protocol Driver\n");
+	spi_unregister_driver(&pmic_driver);
+}
+
+/*
+ * Module entry points
+ */
+subsys_initcall_sync(pmic_init);
+module_exit(pmic_exit);
+
+MODULE_DESCRIPTION("Core/Protocol driver for PMIC");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/core/pmic_event.c b/drivers/mxc/pmic/core/pmic_event.c
new file mode 100644
index 000000000000..2d1bebfef448
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic_event.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic_event.c
+ * @brief This file manage all event of PMIC component.
+ *
+ * It contains event subscription, unsubscription and callback
+ * launch methods implemeted.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include "pmic.h"
+
+/*!
+ * This structure is used to keep a list of subscribed
+ * callbacks for an event.
+ */
+typedef struct {
+	/*!
+	 * Keeps a list of subscribed clients to an event.
+	 */
+	struct list_head list;
+
+	/*!
+	 * Callback function with parameter, called when event occurs
+	 */
+	pmic_event_callback_t callback;
+} pmic_event_callback_list_t;
+
+/* Create a mutex to be used to prevent concurrent access to the event list */
+static DECLARE_MUTEX(event_mutex);
+
+/* This is a pointer to the event handler array. It defines the currently
+ * active set of events and user-defined callback functions.
+ */
+static struct list_head pmic_events[PMIC_MAX_EVENTS];
+
+/*!
+ * This function initializes event list for PMIC event handling.
+ *
+ */
+void pmic_event_list_init(void)
+{
+	int i;
+
+	for (i = 0; i < PMIC_MAX_EVENTS; i++) {
+		INIT_LIST_HEAD(&pmic_events[i]);
+	}
+
+	sema_init(&event_mutex, 1);
+	return;
+}
+
+/*!
+ * This function is used to subscribe on an event.
+ *
+ * @param	event   the event number to be subscribed
+ * @param	callback the callback funtion to be subscribed
+ *
+ * @return       This function returns 0 on SUCCESS, error on FAILURE.
+ */
+PMIC_STATUS pmic_event_subscribe(type_event event,
+				 pmic_event_callback_t callback)
+{
+	pmic_event_callback_list_t *new = NULL;
+
+	pr_debug("Event:%d Subscribe\n", event);
+
+	/* Check whether the event & callback are valid? */
+	if (event >= PMIC_MAX_EVENTS) {
+		pr_debug("Invalid Event:%d\n", event);
+		return -EINVAL;
+	}
+	if (NULL == callback.func) {
+		pr_debug("Null or Invalid Callback\n");
+		return -EINVAL;
+	}
+
+	/* Create a new linked list entry */
+	new = kmalloc(sizeof(pmic_event_callback_list_t), GFP_KERNEL);
+	if (NULL == new) {
+		return -ENOMEM;
+	}
+	/* Initialize the list node fields */
+	new->callback.func = callback.func;
+	new->callback.param = callback.param;
+	INIT_LIST_HEAD(&new->list);
+
+	/* Obtain the lock to access the list */
+	if (down_interruptible(&event_mutex)) {
+		kfree(new);
+		return PMIC_SYSTEM_ERROR_EINTR;
+	}
+
+	/* Unmask the requested event */
+	if (list_empty(&pmic_events[event])) {
+		if (pmic_event_unmask(event) != PMIC_SUCCESS) {
+			kfree(new);
+			up(&event_mutex);
+			return PMIC_ERROR;
+		}
+	}
+
+	/* Add this entry to the event list */
+	list_add_tail(&new->list, &pmic_events[event]);
+
+	/* Release the lock */
+	up(&event_mutex);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to unsubscribe on an event.
+ *
+ * @param	event   the event number to be unsubscribed
+ * @param	callback the callback funtion to be unsubscribed
+ *
+ * @return       This function returns 0 on SUCCESS, error on FAILURE.
+ */
+PMIC_STATUS pmic_event_unsubscribe(type_event event,
+				   pmic_event_callback_t callback)
+{
+	struct list_head *p;
+	struct list_head *n;
+	pmic_event_callback_list_t *temp = NULL;
+	int ret = PMIC_EVENT_NOT_SUBSCRIBED;
+
+	pr_debug("Event:%d Unsubscribe\n", event);
+
+	/* Check whether the event & callback are valid? */
+	if (event >= PMIC_MAX_EVENTS) {
+		pr_debug("Invalid Event:%d\n", event);
+		return -EINVAL;
+	}
+
+	if (NULL == callback.func) {
+		pr_debug("Null or Invalid Callback\n");
+		return -EINVAL;
+	}
+
+	/* Obtain the lock to access the list */
+	if (down_interruptible(&event_mutex)) {
+		return PMIC_SYSTEM_ERROR_EINTR;
+	}
+
+	/* Find the entry in the list */
+	list_for_each_safe(p, n, &pmic_events[event]) {
+		temp = list_entry(p, pmic_event_callback_list_t, list);
+		if (temp->callback.func == callback.func
+		    && temp->callback.param == callback.param) {
+			/* Remove the entry from the list */
+			list_del(p);
+			kfree(temp);
+			ret = PMIC_SUCCESS;
+			break;
+		}
+	}
+
+	/* Unmask the requested event */
+	if (list_empty(&pmic_events[event])) {
+		if (pmic_event_mask(event) != PMIC_SUCCESS) {
+			ret = PMIC_UNSUBSCRIBE_ERROR;
+		}
+	}
+
+	/* Release the lock */
+	up(&event_mutex);
+
+	return ret;
+}
+
+/*!
+ * This function calls all callback of a specific event.
+ *
+ * @param	event   the active event number
+ *
+ * @return 	None
+ */
+void pmic_event_callback(type_event event)
+{
+	struct list_head *p;
+	pmic_event_callback_list_t *temp = NULL;
+
+	/* Obtain the lock to access the list */
+	if (down_interruptible(&event_mutex)) {
+		return;
+	}
+
+	if (list_empty(&pmic_events[event])) {
+		pr_debug("PMIC Event:%d detected. No callback subscribed\n",
+			 event);
+		up(&event_mutex);
+		return;
+	}
+
+	list_for_each(p, &pmic_events[event]) {
+		temp = list_entry(p, pmic_event_callback_list_t, list);
+		temp->callback.func(temp->callback.param);
+	}
+
+	/* Release the lock */
+	up(&event_mutex);
+
+	return;
+
+}
+
+EXPORT_SYMBOL(pmic_event_subscribe);
+EXPORT_SYMBOL(pmic_event_unsubscribe);
diff --git a/drivers/mxc/pmic/core/pmic_external.c b/drivers/mxc/pmic/core/pmic_external.c
new file mode 100644
index 000000000000..bea23af3207d
--- /dev/null
+++ b/drivers/mxc/pmic/core/pmic_external.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file pmic_external.c
+ * @brief This file contains all external functions of PMIC drivers.
+ *
+ * @ingroup PMIC_CORE
+ */
+
+/*
+ * Includes
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+
+/*
+ * External Functions
+ */
+extern int pmic_read(int reg_num, unsigned int *reg_val);
+extern int pmic_write(int reg_num, const unsigned int reg_val);
+
+/*!
+ * This function is called by PMIC clients to read a register on PMIC.
+ *
+ * @param        reg        number of register
+ * @param        reg_value  return value of register
+ * @param        reg_mask   Bitmap mask indicating which bits to modify
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_read_reg(int reg, unsigned int *reg_value,
+			  unsigned int reg_mask)
+{
+	int ret = 0;
+	unsigned int temp = 0;
+
+	ret = pmic_read(reg, &temp);
+	if (ret != PMIC_SUCCESS) {
+		return PMIC_ERROR;
+	}
+	*reg_value = (temp & reg_mask);
+
+	pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value);
+
+	return ret;
+}
+
+/*!
+ * This function is called by PMIC clients to write a register on PMIC.
+ *
+ * @param        reg        number of register
+ * @param        reg_value  New value of register
+ * @param        reg_mask   Bitmap mask indicating which bits to modify
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_write_reg(int reg, unsigned int reg_value,
+			   unsigned int reg_mask)
+{
+	int ret = 0;
+	unsigned int temp = 0;
+
+	ret = pmic_read(reg, &temp);
+	if (ret != PMIC_SUCCESS) {
+		return PMIC_ERROR;
+	}
+	temp = (temp & (~reg_mask)) | reg_value;
+#ifdef CONFIG_MXC_PMIC_MC13783
+	if (reg == REG_POWER_MISCELLANEOUS)
+		temp &= 0xFFFE7FFF;
+#endif
+	ret = pmic_write(reg, temp);
+	if (ret != PMIC_SUCCESS) {
+		return PMIC_ERROR;
+	}
+
+	pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value);
+
+	return ret;
+}
+
+EXPORT_SYMBOL(pmic_read_reg);
+EXPORT_SYMBOL(pmic_write_reg);
diff --git a/drivers/mxc/pmic/mc13783/Kconfig b/drivers/mxc/pmic/mc13783/Kconfig
new file mode 100644
index 000000000000..02496c624e2e
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/Kconfig
@@ -0,0 +1,55 @@
+#
+# PMIC Modules configuration
+#
+
+config MXC_MC13783_ADC
+	tristate "MC13783 ADC support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 ADC module driver. This module provides kernel API
+	for the ADC system of MC13783.
+	It controls also the touch screen interface.
+	If you want MC13783 ADC support, you should say Y here
+
+config MXC_MC13783_AUDIO
+	tristate "MC13783 Audio support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 audio module driver. This module provides kernel API
+	for audio part of MC13783.
+	If you want MC13783 audio support, you should say Y here
+config MXC_MC13783_RTC
+	tristate "MC13783 Real Time Clock (RTC) support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 RTC module driver. This module provides kernel API
+	for RTC part of MC13783.
+	If you want MC13783 RTC support, you should say Y here
+config MXC_MC13783_LIGHT
+	tristate "MC13783 Light and Backlight support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 Light module driver. This module provides kernel API
+	for led and backlight control part of MC13783.
+	If you want MC13783 Light support, you should say Y here
+config MXC_MC13783_BATTERY
+	tristate "MC13783 Battery API support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 battery module driver. This module provides kernel API
+	for battery control part of MC13783.
+	If you want MC13783 battery support, you should say Y here
+config MXC_MC13783_CONNECTIVITY
+	tristate "MC13783 Connectivity API support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 connectivity module driver. This module provides kernel API
+	for USB/RS232 connectivity control part of MC13783.
+	If you want MC13783 connectivity support, you should say Y here
+config MXC_MC13783_POWER
+	tristate "MC13783 Power API support"
+	depends on MXC_PMIC_MC13783
+	---help---
+	This is the MC13783 power and supplies module driver. This module provides kernel API
+	for power and regulator control part of MC13783.
+	If you want MC13783 power support, you should say Y here
diff --git a/drivers/mxc/pmic/mc13783/Makefile b/drivers/mxc/pmic/mc13783/Makefile
new file mode 100644
index 000000000000..7bbba23f5ab9
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the mc13783 pmic drivers.
+#
+
+obj-$(CONFIG_MXC_MC13783_ADC) += pmic_adc-mod.o
+obj-$(CONFIG_MXC_MC13783_AUDIO) += pmic_audio-mod.o
+obj-$(CONFIG_MXC_MC13783_RTC) += pmic_rtc-mod.o
+obj-$(CONFIG_MXC_MC13783_LIGHT) += pmic_light-mod.o
+obj-$(CONFIG_MXC_MC13783_BATTERY) += pmic_battery-mod.o
+obj-$(CONFIG_MXC_MC13783_CONNECTIVITY) += pmic_convity-mod.o
+obj-$(CONFIG_MXC_MC13783_POWER) += pmic_power-mod.o
+pmic_adc-mod-objs := pmic_adc.o
+pmic_audio-mod-objs := pmic_audio.o
+pmic_rtc-mod-objs := pmic_rtc.o
+pmic_light-mod-objs := pmic_light.o
+pmic_battery-mod-objs := pmic_battery.o
+pmic_convity-mod-objs := pmic_convity.o
+pmic_power-mod-objs := pmic_power.o
diff --git a/drivers/mxc/pmic/mc13783/pmic_adc.c b/drivers/mxc/pmic/mc13783/pmic_adc.c
new file mode 100644
index 000000000000..1554faffd288
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_adc.c
@@ -0,0 +1,1542 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_adc.c
+ * @brief This is the main file of PMIC(mc13783) ADC driver.
+ *
+ * @ingroup PMIC_ADC
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/pmic_adc.h>
+#include <linux/pmic_status.h>
+
+#include "../core/pmic.h"
+#include "pmic_adc_defs.h"
+
+#define NB_ADC_REG      5
+
+static int pmic_adc_major;
+
+/* internal function */
+static void callback_tsi(void *);
+static void callback_adcdone(void *);
+static void callback_adcbisdone(void *);
+static void callback_adc_comp_high(void *);
+
+/*!
+ * Number of users waiting in suspendq
+ */
+static int swait = 0;
+
+/*!
+ * To indicate whether any of the adc devices are suspending
+ */
+static int suspend_flag = 0;
+
+/*!
+ * The suspendq is used by blocking application calls
+ */
+static wait_queue_head_t suspendq;
+
+static struct class *pmic_adc_class;
+
+/*
+ * ADC mc13783 API
+ */
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_adc_init);
+EXPORT_SYMBOL(pmic_adc_deinit);
+EXPORT_SYMBOL(pmic_adc_convert);
+EXPORT_SYMBOL(pmic_adc_convert_8x);
+EXPORT_SYMBOL(pmic_adc_convert_multichnnel);
+EXPORT_SYMBOL(pmic_adc_set_touch_mode);
+EXPORT_SYMBOL(pmic_adc_get_touch_mode);
+EXPORT_SYMBOL(pmic_adc_get_touch_sample);
+EXPORT_SYMBOL(pmic_adc_get_battery_current);
+EXPORT_SYMBOL(pmic_adc_active_comparator);
+EXPORT_SYMBOL(pmic_adc_deactive_comparator);
+
+static DECLARE_COMPLETION(adcdone_it);
+static DECLARE_COMPLETION(adcbisdone_it);
+static DECLARE_COMPLETION(adc_tsi);
+static pmic_event_callback_t tsi_event;
+static pmic_event_callback_t event_adc;
+static pmic_event_callback_t event_adc_bis;
+static pmic_event_callback_t adc_comp_h;
+static bool data_ready_adc_1;
+static bool data_ready_adc_2;
+static bool adc_ts;
+static bool wait_ts;
+static bool monitor_en;
+static bool monitor_adc;
+static t_check_mode wcomp_mode;
+static DECLARE_MUTEX(convert_mutex);
+
+void (*monitoring_cb) (void);	/*call back to be called when event is detected. */
+
+static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy);
+static t_adc_state adc_dev[2];
+
+static unsigned channel_num[] = {
+	0,
+	1,
+	3,
+	4,
+	2,
+	12,
+	13,
+	14,
+	15,
+	-1,
+	5,
+	6,
+	7,
+	8,
+	9,
+	10,
+	11,
+	7,
+	6,
+	-1,
+	-1,
+	-1,
+	-1,
+	5,
+	7
+};
+
+static bool pmic_adc_ready;
+
+int is_pmic_adc_ready()
+{
+	return pmic_adc_ready;
+}
+EXPORT_SYMBOL(is_pmic_adc_ready);
+
+
+/*!
+ * This is the suspend of power management for the mc13783 ADC API.
+ * It supports SAVE and POWER_DOWN state.
+ *
+ * @param        pdev           the device
+ * @param        state          the state
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	unsigned int reg_value = 0;
+	suspend_flag = 1;
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS));
+
+	return 0;
+};
+
+/*!
+ * This is the resume of power management for the mc13783 adc API.
+ * It supports RESTORE state.
+ *
+ * @param        pdev           the device
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_adc_resume(struct platform_device *pdev)
+{
+	/* nothing for mc13783 adc */
+	unsigned int adc_0_reg, adc_1_reg;
+	suspend_flag = 0;
+
+	/* let interrupt of TSI again */
+	adc_0_reg = ADC_WAIT_TSI_0;
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS));
+	adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts);
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS));
+
+	while (swait > 0) {
+		swait--;
+		wake_up_interruptible(&suspendq);
+	}
+
+	return 0;
+};
+
+/*
+ * Call back functions
+ */
+
+/*!
+ * This is the callback function called on TSI mc13783 event, used in synchronous call.
+ */
+static void callback_tsi(void *unused)
+{
+	pr_debug("*** TSI IT mc13783 PMIC_ADC_GET_TOUCH_SAMPLE ***\n");
+	if (wait_ts) {
+		complete(&adc_tsi);
+		pmic_event_mask(EVENT_TSI);
+	}
+}
+
+/*!
+ * This is the callback function called on ADCDone mc13783 event.
+ */
+static void callback_adcdone(void *unused)
+{
+	if (data_ready_adc_1) {
+		complete(&adcdone_it);
+	}
+}
+
+/*!
+ * This is the callback function called on ADCDone mc13783 event.
+ */
+static void callback_adcbisdone(void *unused)
+{
+	pr_debug("* adcdone bis it callback *\n");
+	if (data_ready_adc_2) {
+		complete(&adcbisdone_it);
+	}
+}
+
+/*!
+ * This is the callback function called on mc13783 event.
+ */
+static void callback_adc_comp_high(void *unused)
+{
+	pr_debug("* adc comp it high *\n");
+	if (wcomp_mode == CHECK_HIGH || wcomp_mode == CHECK_LOW_OR_HIGH) {
+		/* launch callback */
+		if (monitoring_cb != NULL) {
+			monitoring_cb();
+		}
+	}
+}
+
+/*!
+ * This function performs filtering and rejection of excessive noise prone
+ * samples.
+ *
+ * @param        ts_curr     Touch screen value
+ *
+ * @return       This function returns 0 on success, -1 otherwise.
+ */
+static int pmic_adc_filter(t_touch_screen * ts_curr)
+{
+	unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3;
+	unsigned int sample_sumx, sample_sumy;
+	static unsigned int prev_x[FILTLEN], prev_y[FILTLEN];
+	int index = 0;
+	unsigned int y_curr, x_curr;
+	static int filt_count = 0;
+	/* Added a variable filt_type to decide filtering at run-time */
+	unsigned int filt_type = 0;
+
+	if (ts_curr->contact_resistance == 0) {
+		ts_curr->x_position = 0;
+		ts_curr->y_position = 0;
+		filt_count = 0;
+		return 0;
+	}
+
+	ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2);
+	ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3);
+	ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3);
+	if ((ydiff1 > DELTA_Y_MAX) ||
+	    (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) {
+		pr_debug("pmic_adc_filter: Ret pos 1\n");
+		return -1;
+	}
+
+	xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2);
+	xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3);
+	xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3);
+
+	if ((xdiff1 > DELTA_X_MAX) ||
+	    (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) {
+		pr_debug("mc13783_adc_filter: Ret pos 2\n");
+		return -1;
+	}
+	/* Compute two closer values among the three available Y readouts */
+
+	if (ydiff1 < ydiff2) {
+		if (ydiff1 < ydiff3) {
+			// Sample 0 & 1 closest together
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position2;
+		} else {
+			// Sample 0 & 2 closest together
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position3;
+		}
+	} else {
+		if (ydiff2 < ydiff3) {
+			// Sample 1 & 2 closest together
+			sample_sumy = ts_curr->y_position2 +
+			    ts_curr->y_position3;
+		} else {
+			// Sample 0 & 2 closest together
+			sample_sumy = ts_curr->y_position1 +
+			    ts_curr->y_position3;
+		}
+	}
+
+	/*
+	 * Compute two closer values among the three available X
+	 * readouts
+	 */
+	if (xdiff1 < xdiff2) {
+		if (xdiff1 < xdiff3) {
+			// Sample 0 & 1 closest together
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position2;
+		} else {
+			// Sample 0 & 2 closest together
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position3;
+		}
+	} else {
+		if (xdiff2 < xdiff3) {
+			// Sample 1 & 2 closest together
+			sample_sumx = ts_curr->x_position2 +
+			    ts_curr->x_position3;
+		} else {
+			// Sample 0 & 2 closest together
+			sample_sumx = ts_curr->x_position1 +
+			    ts_curr->x_position3;
+		}
+	}
+	/*
+	 * Wait FILTER_MIN_DELAY number of samples to restart
+	 * filtering
+	 */
+	if (filt_count < FILTER_MIN_DELAY) {
+		/*
+		 * Current output is the average of the two closer
+		 * values and no filtering is used
+		 */
+		y_curr = (sample_sumy / 2);
+		x_curr = (sample_sumx / 2);
+		ts_curr->y_position = y_curr;
+		ts_curr->x_position = x_curr;
+		filt_count++;
+	} else {
+		if (abs(sample_sumx - (prev_x[0] + prev_x[1])) >
+		    (DELTA_X_MAX * 16)) {
+			pr_debug("pmic_adc_filter: : Ret pos 3\n");
+			return -1;
+		}
+		if (abs(sample_sumy - (prev_y[0] + prev_y[1])) >
+		    (DELTA_Y_MAX * 16)) {
+			return -1;
+		}
+		sample_sumy /= 2;
+		sample_sumx /= 2;
+		/* Use hard filtering if the sample difference < 10 */
+		if ((abs(sample_sumy - prev_y[0]) > 10) ||
+		    (abs(sample_sumx - prev_x[0]) > 10)) {
+			filt_type = 1;
+		}
+
+		/*
+		 * Current outputs are the average of three previous
+		 * values and the present readout
+		 */
+		y_curr = sample_sumy;
+		for (index = 0; index < FILTLEN; index++) {
+			if (filt_type == 0) {
+				y_curr = y_curr + (prev_y[index]);
+			} else {
+				y_curr = y_curr + (prev_y[index] / 3);
+			}
+		}
+		if (filt_type == 0) {
+			y_curr = y_curr >> 2;
+		} else {
+			y_curr = y_curr >> 1;
+		}
+		ts_curr->y_position = y_curr;
+
+		x_curr = sample_sumx;
+		for (index = 0; index < FILTLEN; index++) {
+			if (filt_type == 0) {
+				x_curr = x_curr + (prev_x[index]);
+			} else {
+				x_curr = x_curr + (prev_x[index] / 3);
+			}
+		}
+		if (filt_type == 0) {
+			x_curr = x_curr >> 2;
+		} else {
+			x_curr = x_curr >> 1;
+		}
+		ts_curr->x_position = x_curr;
+
+	}
+
+	/* Update previous X and Y values */
+	for (index = (FILTLEN - 1); index > 0; index--) {
+		prev_x[index] = prev_x[index - 1];
+		prev_y[index] = prev_y[index - 1];
+	}
+
+	/*
+	 * Current output will be the most recent past for the
+	 * next sample
+	 */
+	prev_y[0] = y_curr;
+	prev_x[0] = x_curr;
+
+	return 0;
+}
+
+/*!
+ * This function implements the open method on a MC13783 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_adc_open(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+	pr_debug("mc13783_adc : mc13783_adc_open()\n");
+	return 0;
+}
+
+/*!
+ * This function implements the release method on a MC13783 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_adc_free(struct inode *inode, struct file *file)
+{
+	pr_debug("mc13783_adc : mc13783_adc_free()\n");
+	return 0;
+}
+
+/*!
+ * This function initializes all ADC registers with default values. This
+ * function also registers the interrupt events.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+int pmic_adc_init(void)
+{
+	unsigned int reg_value = 0, i = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	for (i = 0; i < ADC_NB_AVAILABLE; i++) {
+		adc_dev[i] = ADC_FREE;
+	}
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS));
+	reg_value = 0x001000;
+	CHECK_ERROR(pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, reg_value,
+				   0xFFFFFF));
+
+	data_ready_adc_1 = false;
+	data_ready_adc_2 = false;
+	adc_ts = false;
+	wait_ts = false;
+	monitor_en = false;
+	monitor_adc = false;
+	wcomp_mode = CHECK_LOW;
+	monitoring_cb = NULL;
+	/* sub to ADCDone IT */
+	event_adc.param = NULL;
+	event_adc.func = callback_adcdone;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_ADCDONEI, event_adc));
+
+	/* sub to ADCDoneBis IT */
+	event_adc_bis.param = NULL;
+	event_adc_bis.func = callback_adcbisdone;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_ADCBISDONEI, event_adc_bis));
+
+	/* sub to Touch Screen IT */
+	tsi_event.param = NULL;
+	tsi_event.func = callback_tsi;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event));
+
+	/* ADC reading above high limit */
+	adc_comp_h.param = NULL;
+	adc_comp_h.func = callback_adc_comp_high;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_WHIGHI, adc_comp_h));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables the ADC, de-registers the interrupt events.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_deinit(void)
+{
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCDONEI, event_adc));
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCBISDONEI, event_adc_bis));
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event));
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_WHIGHI, adc_comp_h));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initializes adc_param structure.
+ *
+ * @param        adc_param     Structure to be initialized.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int mc13783_adc_init_param(t_adc_param * adc_param)
+{
+	int i = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	adc_param->delay = 0;
+	adc_param->conv_delay = false;
+	adc_param->single_channel = false;
+	adc_param->group = false;
+	adc_param->channel_0 = BATTERY_VOLTAGE;
+	adc_param->channel_1 = BATTERY_VOLTAGE;
+	adc_param->read_mode = 0;
+	adc_param->wait_tsi = 0;
+	adc_param->chrgraw_devide_5 = true;
+	adc_param->read_ts = false;
+	adc_param->ts_value.x_position = 0;
+	adc_param->ts_value.y_position = 0;
+	adc_param->ts_value.contact_resistance = 0;
+	for (i = 0; i <= MAX_CHANNEL; i++) {
+		adc_param->value[i] = 0;
+	}
+	return 0;
+}
+
+/*!
+ * This function starts the convert.
+ *
+ * @param        adc_param      contains all adc configuration and return value.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS mc13783_adc_convert(t_adc_param * adc_param)
+{
+	bool use_bis = false;
+	unsigned int adc_0_reg = 0, adc_1_reg = 0, reg_1 = 0, result_reg =
+	    0, i = 0;
+	unsigned int result = 0, temp = 0;
+	pmic_version_t mc13783_ver;
+	pr_debug("mc13783 ADC - mc13783_adc_convert ....\n");
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (adc_param->wait_tsi) {
+		/* we need to set ADCEN 1 for TSI interrupt on mc13783 1.x */
+		/* configure adc to wait tsi interrupt */
+		INIT_COMPLETION(adc_tsi);
+		pr_debug("mc13783 ADC - pmic_write_reg ....\n");
+		/*for ts don't use bis */
+		adc_0_reg = 0x001c00 | (ADC_BIS * 0);
+		pmic_event_unmask(EVENT_TSI);
+		CHECK_ERROR(pmic_write_reg
+			    (REG_ADC_0, adc_0_reg, PMIC_ALL_BITS));
+		/*for ts don't use bis */
+		adc_1_reg = 0x200001 | (ADC_BIS * 0);
+		CHECK_ERROR(pmic_write_reg
+			    (REG_ADC_1, adc_1_reg, PMIC_ALL_BITS));
+		pr_debug("wait tsi ....\n");
+		wait_ts = true;
+		wait_for_completion_interruptible(&adc_tsi);
+		wait_ts = false;
+	}
+	if (adc_param->read_ts == false)
+		down(&convert_mutex);
+	use_bis = mc13783_adc_request(adc_param->read_ts);
+	if (use_bis < 0) {
+		pr_debug("process has received a signal and got interrupted\n");
+		return -EINTR;
+	}
+
+	/* CONFIGURE ADC REG 0 */
+	adc_0_reg = 0;
+	adc_1_reg = 0;
+	if (adc_param->read_ts == false) {
+		adc_0_reg = adc_param->read_mode & 0x00003F;
+		/* add auto inc */
+		adc_0_reg |= ADC_INC;
+		if (use_bis) {
+			/* add adc bis */
+			adc_0_reg |= ADC_BIS;
+		}
+		mc13783_ver = pmic_get_version();
+		if (mc13783_ver.revision >= 20) {
+			if (adc_param->chrgraw_devide_5) {
+				adc_0_reg |= ADC_CHRGRAW_D5;
+			}
+		}
+		if (adc_param->single_channel) {
+			adc_1_reg |= ADC_SGL_CH;
+		}
+
+		if (adc_param->conv_delay) {
+			adc_1_reg |= ADC_ATO;
+		}
+
+		if (adc_param->group) {
+			adc_1_reg |= ADC_ADSEL;
+		}
+
+		if (adc_param->single_channel) {
+			adc_1_reg |= ADC_SGL_CH;
+		}
+
+		adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) &
+		    ADC_CH_0_MASK;
+		adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) &
+		    ADC_CH_1_MASK;
+	} else {
+		adc_0_reg = 0x003c00 | (ADC_BIS * use_bis) | ADC_INC;
+	}
+	pr_debug("Write Reg %i = %x\n", REG_ADC_0, adc_0_reg);
+	/*Change has been made here */
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg,
+				   ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 |
+				   0xfff00ff));
+	/* CONFIGURE ADC REG 1 */
+	if (adc_param->read_ts == false) {
+		adc_1_reg |= ADC_NO_ADTRIG;
+		adc_1_reg |= ADC_EN;
+		adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) &
+		    ADC_DELAY_MASK;
+		if (use_bis) {
+			adc_1_reg |= ADC_BIS;
+		}
+	} else {
+		/* configure and start convert to read x and y position */
+		/* configure to read 2 value in channel selection 1 & 2 */
+		adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG;
+	}
+	reg_1 = adc_1_reg;
+	if (use_bis == 0) {
+		data_ready_adc_1 = false;
+		adc_1_reg |= ASC_ADC;
+		data_ready_adc_1 = true;
+		pr_debug("Write Reg %i = %x\n", REG_ADC_1, adc_1_reg);
+		INIT_COMPLETION(adcdone_it);
+		CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg,
+					   ADC_SGL_CH | ADC_ATO | ADC_ADSEL
+					   | ADC_CH_0_MASK | ADC_CH_1_MASK |
+					   ADC_NO_ADTRIG | ADC_EN |
+					   ADC_DELAY_MASK | ASC_ADC | ADC_BIS));
+		pr_debug("wait adc done \n");
+		wait_for_completion_interruptible(&adcdone_it);
+		data_ready_adc_1 = false;
+	} else {
+		data_ready_adc_2 = false;
+		adc_1_reg |= ASC_ADC;
+		data_ready_adc_2 = true;
+		INIT_COMPLETION(adcbisdone_it);
+		CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, 0xFFFFFF));
+		temp = 0x800000;
+		CHECK_ERROR(pmic_write_reg(REG_ADC_3, temp, 0xFFFFFF));
+		temp = 0x001000;
+		pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, temp,
+			       0xFFFFFF);
+		pr_debug("wait adc done bis\n");
+		wait_for_completion_interruptible(&adcbisdone_it);
+		data_ready_adc_2 = false;
+	}
+	/* read result and store in adc_param */
+	result = 0;
+	if (use_bis == 0) {
+		result_reg = REG_ADC_2;
+	} else {
+		result_reg = REG_ADC_4;
+	}
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, 4 << ADC_CH_1_POS,
+				   ADC_CH_0_MASK | ADC_CH_1_MASK));
+
+	for (i = 0; i <= 3; i++) {
+		CHECK_ERROR(pmic_read_reg(result_reg, &result, PMIC_ALL_BITS));
+		pr_debug("result %i = %x\n", result_reg, result);
+		adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2);
+		adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14);
+	}
+	if (adc_param->read_ts) {
+		adc_param->ts_value.x_position = adc_param->value[2];
+		adc_param->ts_value.x_position1 = adc_param->value[0];
+		adc_param->ts_value.x_position2 = adc_param->value[1];
+		adc_param->ts_value.x_position3 = adc_param->value[2];
+		adc_param->ts_value.y_position1 = adc_param->value[3];
+		adc_param->ts_value.y_position2 = adc_param->value[4];
+		adc_param->ts_value.y_position3 = adc_param->value[5];
+		adc_param->ts_value.y_position = adc_param->value[5];
+		adc_param->ts_value.contact_resistance = adc_param->value[6];
+
+	}
+
+	/*if (adc_param->read_ts) {
+	   adc_param->ts_value.x_position = adc_param->value[2];
+	   adc_param->ts_value.y_position = adc_param->value[5];
+	   adc_param->ts_value.contact_resistance = adc_param->value[6];
+	   } */
+	mc13783_adc_release(use_bis);
+	if (adc_param->read_ts == false)
+		up(&convert_mutex);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function select the required read_mode for a specific channel.
+ *
+ * @param        channel   The channel to be sampled
+ *
+ * @return       This function returns the requires read_mode
+ */
+t_reading_mode mc13783_set_read_mode(t_channel channel)
+{
+	t_reading_mode read_mode = 0;
+
+	switch (channel) {
+	case LICELL:
+		read_mode = M_LITHIUM_CELL;
+		break;
+	case CHARGE_CURRENT:
+		read_mode = M_CHARGE_CURRENT;
+		break;
+	case BATTERY_CURRENT:
+		read_mode = M_BATTERY_CURRENT;
+		break;
+	case THERMISTOR:
+		read_mode = M_THERMISTOR;
+		break;
+	case DIE_TEMP:
+		read_mode = M_DIE_TEMPERATURE;
+		break;
+	case USB_ID:
+		read_mode = M_UID;
+		break;
+	default:
+		read_mode = 0;
+	}
+
+	return read_mode;
+}
+
+/*!
+ * This function triggers a conversion and returns one sampling result of one
+ * channel.
+ *
+ * @param        channel   The channel to be sampled
+ * @param        result    The pointer to the conversion result. The memory
+ *                         should be allocated by the caller of this function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result)
+{
+	t_adc_param adc_param;
+	PMIC_STATUS ret;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	channel = channel_num[channel];
+	if (channel == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+	mc13783_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert\n");
+	adc_param.read_ts = false;
+	adc_param.read_mode = mc13783_set_read_mode(channel);
+
+	adc_param.single_channel = true;
+	/* Find the group */
+	if ((channel >= 0) && (channel <= 7)) {
+		adc_param.channel_0 = channel;
+		adc_param.group = false;
+	} else if ((channel >= 8) && (channel <= 15)) {
+		adc_param.channel_0 = channel & 0x07;
+		adc_param.group = true;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+	ret = mc13783_adc_convert(&adc_param);
+	*result = adc_param.value[0];
+	return ret;
+}
+
+/*!
+ * This function triggers a conversion and returns eight sampling results of
+ * one channel.
+ *
+ * @param        channel   The channel to be sampled
+ * @param        result    The pointer to array to store eight sampling results.
+ *                         The memory should be allocated by the caller of this
+ *                         function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result)
+{
+	t_adc_param adc_param;
+	int i;
+	PMIC_STATUS ret;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	channel = channel_num[channel];
+
+	if (channel == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+	mc13783_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert_8x\n");
+	adc_param.read_ts = false;
+	adc_param.single_channel = true;
+	adc_param.read_mode = mc13783_set_read_mode(channel);
+	if ((channel >= 0) && (channel <= 7)) {
+		adc_param.channel_0 = channel;
+		adc_param.channel_1 = channel;
+		adc_param.group = false;
+	} else if ((channel >= 8) && (channel <= 15)) {
+		adc_param.channel_0 = channel & 0x07;
+		adc_param.channel_1 = channel & 0x07;
+		adc_param.group = true;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	ret = mc13783_adc_convert(&adc_param);
+	for (i = 0; i <= 7; i++) {
+		result[i] = adc_param.value[i];
+	}
+	return ret;
+}
+
+/*!
+ * This function triggers a conversion and returns sampling results of each
+ * specified channel.
+ *
+ * @param        channels  This input parameter is bitmap to specify channels
+ *                         to be sampled.
+ * @param        result    The pointer to array to store sampling results.
+ *                         The memory should be allocated by the caller of this
+ *                         function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_convert_multichnnel(t_channel channels,
+					 unsigned short *result)
+{
+	t_adc_param adc_param;
+	int i;
+	PMIC_STATUS ret;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mc13783_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert_multichnnel\n");
+
+	channels = channel_num[channels];
+
+	if (channels == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	adc_param.read_ts = false;
+	adc_param.single_channel = false;
+	if ((channels >= 0) && (channels <= 7)) {
+		adc_param.channel_0 = channels;
+		adc_param.channel_1 = ((channels + 4) % 4) + 4;
+		adc_param.group = false;
+	} else if ((channels >= 8) && (channels <= 15)) {
+		channels = channels & 0x07;
+		adc_param.channel_0 = channels;
+		adc_param.channel_1 = ((channels + 4) % 4) + 4;
+		adc_param.group = true;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+	adc_param.read_mode = 0x00003f;
+	adc_param.read_ts = false;
+	ret = mc13783_adc_convert(&adc_param);
+
+	for (i = 0; i <= 7; i++) {
+		result[i] = adc_param.value[i];
+	}
+	return ret;
+}
+
+/*!
+ * This function sets touch screen operation mode.
+ *
+ * @param        touch_mode   Touch screen operation mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode)
+{
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0,
+				   BITFVAL(MC13783_ADC0_TS_M, touch_mode),
+				   BITFMASK(MC13783_ADC0_TS_M)));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrieves the current touch screen operation mode.
+ *
+ * @param        touch_mode   Pointer to the retrieved touch screen operation
+ *                            mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode * touch_mode)
+{
+	unsigned int value;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	CHECK_ERROR(pmic_read_reg(REG_ADC_0, &value, PMIC_ALL_BITS));
+
+	*touch_mode = BITFEXT(value, MC13783_ADC0_TS_M);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrieves the current touch screen (X,Y) coordinates.
+ *
+ * @param        touch_sample Pointer to touch sample.
+ * @param        wait	indicates whether this call must block or not.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen * touch_sample, int wait)
+{
+	if (mc13783_adc_read_ts(touch_sample, wait) != 0)
+		return PMIC_ERROR;
+	if (0 == pmic_adc_filter(touch_sample))
+		return PMIC_SUCCESS;
+	else
+		return PMIC_ERROR;
+}
+
+/*!
+ * This function read the touch screen value.
+ *
+ * @param        ts_value    return value of touch screen
+ * @param        wait_tsi    if true, this function is synchronous (wait in TSI event).
+ *
+ * @return       This function returns 0.
+ */
+PMIC_STATUS mc13783_adc_read_ts(t_touch_screen * ts_value, int wait_tsi)
+{
+	t_adc_param param;
+	pr_debug("mc13783_adc : mc13783_adc_read_ts\n");
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	if (wait_ts) {
+		pr_debug("mc13783_adc : error TS busy \n");
+		return PMIC_ERROR;
+	}
+	mc13783_adc_init_param(&param);
+	param.wait_tsi = wait_tsi;
+	param.read_ts = true;
+	if (mc13783_adc_convert(&param) != 0)
+		return PMIC_ERROR;
+	/* check if x-y is ok */
+	if ((param.ts_value.x_position1 < TS_X_MAX) &&
+	    (param.ts_value.x_position1 >= TS_X_MIN) &&
+	    (param.ts_value.y_position1 < TS_Y_MAX) &&
+	    (param.ts_value.y_position1 >= TS_Y_MIN) &&
+	    (param.ts_value.x_position2 < TS_X_MAX) &&
+	    (param.ts_value.x_position2 >= TS_X_MIN) &&
+	    (param.ts_value.y_position2 < TS_Y_MAX) &&
+	    (param.ts_value.y_position2 >= TS_Y_MIN) &&
+	    (param.ts_value.x_position3 < TS_X_MAX) &&
+	    (param.ts_value.x_position3 >= TS_X_MIN) &&
+	    (param.ts_value.y_position3 < TS_Y_MAX) &&
+	    (param.ts_value.y_position3 >= TS_Y_MIN)) {
+		ts_value->x_position = param.ts_value.x_position;
+		ts_value->x_position1 = param.ts_value.x_position1;
+		ts_value->x_position2 = param.ts_value.x_position2;
+		ts_value->x_position3 = param.ts_value.x_position3;
+		ts_value->y_position = param.ts_value.y_position;
+		ts_value->y_position1 = param.ts_value.y_position1;
+		ts_value->y_position2 = param.ts_value.y_position2;
+		ts_value->y_position3 = param.ts_value.y_position3;
+		ts_value->contact_resistance =
+		    param.ts_value.contact_resistance + 1;
+
+	} else {
+		ts_value->x_position = 0;
+		ts_value->y_position = 0;
+		ts_value->contact_resistance = 0;
+
+	}
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function starts a Battery Current mode conversion.
+ *
+ * @param        mode      Conversion mode.
+ * @param        result    Battery Current measurement result.
+ *                         if \a mode = ADC_8CHAN_1X, the result is \n
+ *                             result[0] = (BATTP - BATT_I) \n
+ *                         if \a mode = ADC_1CHAN_8X, the result is \n
+ *                             result[0] = BATTP \n
+ *                             result[1] = BATT_I \n
+ *                             result[2] = BATTP \n
+ *                             result[3] = BATT_I \n
+ *                             result[4] = BATTP \n
+ *                             result[5] = BATT_I \n
+ *                             result[6] = BATTP \n
+ *                             result[7] = BATT_I
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_get_battery_current(t_conversion_mode mode,
+					 unsigned short *result)
+{
+	PMIC_STATUS ret;
+	t_channel channel;
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	channel = BATTERY_CURRENT;
+	if (mode == ADC_8CHAN_1X) {
+		ret = pmic_adc_convert(channel, result);
+	} else {
+		ret = pmic_adc_convert_8x(channel, result);
+	}
+	return ret;
+}
+
+/*!
+ * This function request a ADC.
+ *
+ * @return      This function returns index of ADC to be used (0 or 1) if successful.
+                return -1 if error.
+ */
+int mc13783_adc_request(bool read_ts)
+{
+	int adc_index = -1;
+	if (read_ts != 0) {
+		/*for ts we use bis=0 */
+		if (adc_dev[0] == ADC_USED)
+			return -1;
+		/*no wait here */
+		adc_dev[0] = ADC_USED;
+		adc_index = 0;
+	} else {
+		/*for other adc use bis = 1 */
+		if (adc_dev[1] == ADC_USED) {
+			return -1;
+			/*no wait here */
+		}
+		adc_dev[1] = ADC_USED;
+		adc_index = 1;
+	}
+	pr_debug("mc13783_adc : request ADC %d\n", adc_index);
+	return adc_index;
+}
+
+/*!
+ * This function release an ADC.
+ *
+ * @param        adc_index     index of ADC to be released.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int mc13783_adc_release(int adc_index)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+
+	pr_debug("mc13783_adc : release ADC %d\n", adc_index);
+	if ((adc_dev[adc_index] == ADC_MONITORING) ||
+	    (adc_dev[adc_index] == ADC_USED)) {
+		adc_dev[adc_index] = ADC_FREE;
+		wake_up(&queue_adc_busy);
+		return 0;
+	}
+	return -1;
+}
+
+/*!
+ * This function initializes monitoring structure.
+ *
+ * @param        monitor     Structure to be initialized.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int mc13783_adc_init_monitor_param(t_monitoring_param * monitor)
+{
+	pr_debug("mc13783_adc : init monitor\n");
+	monitor->delay = 0;
+	monitor->conv_delay = false;
+	monitor->channel = BATTERY_VOLTAGE;
+	monitor->read_mode = 0;
+	monitor->comp_low = 0;
+	monitor->comp_high = 0;
+	monitor->group = 0;
+	monitor->check_mode = CHECK_LOW_OR_HIGH;
+	monitor->callback = NULL;
+	return 0;
+}
+
+/*!
+ * This function actives the comparator.  When comparator is active and ADC
+ * is enabled, the 8th converted value will be digitally compared against the
+ * window defined by WLOW and WHIGH registers.
+ *
+ * @param        low      Comparison window low threshold (WLOW).
+ * @param        high     Comparison window high threshold (WHIGH).
+ * @param        channel  The channel to be sampled
+ * @param        callback Callback function to be called when the converted
+ *                        value is beyond the comparison window.  The callback
+ *                        function will pass a parameter of type
+ *                        \b t_comp_expection to indicate the reason of
+ *                        comparator exception.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_active_comparator(unsigned char low,
+				       unsigned char high,
+				       t_channel channel,
+				       t_comparator_cb callback)
+{
+	bool use_bis = false;
+	unsigned int adc_0_reg = 0, adc_1_reg = 0, adc_3_reg = 0;
+	t_monitoring_param monitoring;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	if (monitor_en) {
+		pr_debug("mc13783_adc : monitoring already configured\n");
+		return PMIC_ERROR;
+	}
+	monitor_en = true;
+	mc13783_adc_init_monitor_param(&monitoring);
+	monitoring.comp_low = low;
+	monitoring.comp_high = high;
+	monitoring.channel = channel;
+	monitoring.callback = (void *)callback;
+
+	use_bis = mc13783_adc_request(false);
+	if (use_bis < 0) {
+		pr_debug("mc13783_adc : request error\n");
+		return PMIC_ERROR;
+	}
+	monitor_adc = use_bis;
+
+	adc_0_reg = 0;
+
+	/* TO DO ADOUT CONFIGURE */
+	adc_0_reg = monitoring.read_mode & ADC_MODE_MASK;
+	if (use_bis) {
+		/* add adc bis */
+		adc_0_reg |= ADC_BIS;
+	}
+	adc_0_reg |= ADC_WCOMP;
+
+	/* CONFIGURE ADC REG 1 */
+	adc_1_reg = 0;
+	adc_1_reg |= ADC_EN;
+	if (monitoring.conv_delay) {
+		adc_1_reg |= ADC_ATO;
+	}
+	if (monitoring.group) {
+		adc_1_reg |= ADC_ADSEL;
+	}
+	adc_1_reg |= (monitoring.channel << ADC_CH_0_POS) & ADC_CH_0_MASK;
+	adc_1_reg |= (monitoring.delay << ADC_DELAY_POS) & ADC_DELAY_MASK;
+	if (use_bis) {
+		adc_1_reg |= ADC_BIS;
+	}
+
+	adc_3_reg |= (monitoring.comp_high << ADC_WCOMP_H_POS) &
+	    ADC_WCOMP_H_MASK;
+	adc_3_reg |= (monitoring.comp_low << ADC_WCOMP_L_POS) &
+	    ADC_WCOMP_L_MASK;
+	if (use_bis) {
+		adc_3_reg |= ADC_BIS;
+	}
+
+	wcomp_mode = monitoring.check_mode;
+	/* call back to be called when event is detected. */
+	monitoring_cb = monitoring.callback;
+
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_3, adc_3_reg, PMIC_ALL_BITS));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function deactivates the comparator.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_adc_deactive_comparator(void)
+{
+	unsigned int reg_value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	if (!monitor_en) {
+		pr_debug("mc13783_adc : adc monitoring free\n");
+		return PMIC_ERROR;
+	}
+
+	if (monitor_en) {
+		reg_value = ADC_BIS;
+	}
+
+	/* clear all reg value */
+	CHECK_ERROR(pmic_write_reg(REG_ADC_0, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC_3, reg_value, PMIC_ALL_BITS));
+
+	reg_value = 0;
+
+	if (monitor_adc) {
+		CHECK_ERROR(pmic_write_reg
+			    (REG_ADC_4, reg_value, PMIC_ALL_BITS));
+	} else {
+		CHECK_ERROR(pmic_write_reg
+			    (REG_ADC_2, reg_value, PMIC_ALL_BITS));
+	}
+
+	mc13783_adc_release(monitor_adc);
+	monitor_en = false;
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function implements IOCTL controls on a MC13783 ADC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_adc_ioctl(struct inode *inode, struct file *file,
+			  unsigned int cmd, unsigned long arg)
+{
+	t_adc_convert_param *convert_param;
+	t_touch_mode touch_mode;
+	t_touch_screen touch_sample;
+	unsigned short b_current;
+	t_adc_comp_param *comp_param;
+	if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D'))
+		return -ENOTTY;
+
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+
+	switch (cmd) {
+	case PMIC_ADC_INIT:
+		pr_debug("init adc\n");
+		CHECK_ERROR(pmic_adc_init());
+		break;
+
+	case PMIC_ADC_DEINIT:
+		pr_debug("deinit adc\n");
+		CHECK_ERROR(pmic_adc_deinit());
+		break;
+
+	case PMIC_ADC_CONVERT:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_adc_convert(convert_param->channel,
+						   convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_CONVERT_8X:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_adc_convert_8x(convert_param->channel,
+						      convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_CONVERT_MULTICHANNEL:
+		if ((convert_param = kmalloc(sizeof(t_adc_convert_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(convert_param, (t_adc_convert_param *) arg,
+				   sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_adc_convert_multichnnel
+				  (convert_param->channel,
+				   convert_param->result),
+				  (kfree(convert_param)));
+
+		if (copy_to_user((t_adc_convert_param *) arg, convert_param,
+				 sizeof(t_adc_convert_param))) {
+			kfree(convert_param);
+			return -EFAULT;
+		}
+		kfree(convert_param);
+		break;
+
+	case PMIC_ADC_SET_TOUCH_MODE:
+		CHECK_ERROR(pmic_adc_set_touch_mode((t_touch_mode) arg));
+		break;
+
+	case PMIC_ADC_GET_TOUCH_MODE:
+		CHECK_ERROR(pmic_adc_get_touch_mode(&touch_mode));
+		if (copy_to_user((t_touch_mode *) arg, &touch_mode,
+				 sizeof(t_touch_mode))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_ADC_GET_TOUCH_SAMPLE:
+		pr_debug("pmic_adc_ioctl: " "PMIC_ADC_GET_TOUCH_SAMPLE\n");
+		CHECK_ERROR(pmic_adc_get_touch_sample(&touch_sample, 1));
+		if (copy_to_user((t_touch_screen *) arg, &touch_sample,
+				 sizeof(t_touch_screen))) {
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_ADC_GET_BATTERY_CURRENT:
+		CHECK_ERROR(pmic_adc_get_battery_current(ADC_8CHAN_1X,
+							 &b_current));
+		if (copy_to_user((unsigned short *)arg, &b_current,
+				 sizeof(unsigned short))) {
+
+			return -EFAULT;
+		}
+		break;
+
+	case PMIC_ADC_ACTIVATE_COMPARATOR:
+		if ((comp_param = kmalloc(sizeof(t_adc_comp_param), GFP_KERNEL))
+		    == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(comp_param, (t_adc_comp_param *) arg,
+				   sizeof(t_adc_comp_param))) {
+			kfree(comp_param);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_adc_active_comparator(comp_param->wlow,
+							     comp_param->whigh,
+							     comp_param->
+							     channel,
+							     comp_param->
+							     callback),
+				  (kfree(comp_param)));
+		break;
+
+	case PMIC_ADC_DEACTIVE_COMPARATOR:
+		CHECK_ERROR(pmic_adc_deactive_comparator());
+		break;
+
+	default:
+		pr_debug("pmic_adc_ioctl: unsupported ioctl command 0x%x\n",
+			 cmd);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct file_operations mc13783_adc_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = pmic_adc_ioctl,
+	.open = pmic_adc_open,
+	.release = pmic_adc_free,
+};
+
+static int pmic_adc_module_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct device *temp_class;
+
+	pmic_adc_major = register_chrdev(0, "pmic_adc", &mc13783_adc_fops);
+
+	if (pmic_adc_major < 0) {
+		pr_debug(KERN_ERR "Unable to get a major for pmic_adc\n");
+		return pmic_adc_major;
+	}
+	init_waitqueue_head(&suspendq);
+
+	pmic_adc_class = class_create(THIS_MODULE, "pmic_adc");
+	if (IS_ERR(pmic_adc_class)) {
+		pr_debug(KERN_ERR "Error creating pmic_adc class.\n");
+		ret = PTR_ERR(pmic_adc_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(pmic_adc_class, NULL,
+				   MKDEV(pmic_adc_major, 0), NULL, "pmic_adc");
+	if (IS_ERR(temp_class)) {
+		pr_debug(KERN_ERR "Error creating pmic_adc class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	ret = pmic_adc_init();
+	if (ret != PMIC_SUCCESS) {
+		pr_debug(KERN_ERR "Error in pmic_adc_init.\n");
+		goto err_out4;
+	}
+
+	pmic_adc_ready = 1;
+	pr_debug(KERN_INFO "PMIC ADC successfully probed\n");
+	return ret;
+
+      err_out4:
+	device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0));
+      err_out2:
+	class_destroy(pmic_adc_class);
+      err_out1:
+	unregister_chrdev(pmic_adc_major, "pmic_adc");
+	return ret;
+}
+
+static int pmic_adc_module_remove(struct platform_device *pdev)
+{
+	pmic_adc_ready = 0;
+	pmic_adc_deinit();
+	device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0));
+	class_destroy(pmic_adc_class);
+	unregister_chrdev(pmic_adc_major, "pmic_adc");
+	pr_debug(KERN_INFO "PMIC ADC successfully removed\n");
+	return 0;
+}
+
+static struct platform_driver pmic_adc_driver_ldm = {
+	.driver = {
+		   .name = "pmic_adc",
+		   },
+	.suspend = pmic_adc_suspend,
+	.resume = pmic_adc_resume,
+	.probe = pmic_adc_module_probe,
+	.remove = pmic_adc_module_remove,
+};
+
+/*
+ * Initialization and Exit
+ */
+static int __init pmic_adc_module_init(void)
+{
+	pr_debug("PMIC ADC driver loading...\n");
+	return platform_driver_register(&pmic_adc_driver_ldm);
+}
+
+static void __exit pmic_adc_module_exit(void)
+{
+	platform_driver_unregister(&pmic_adc_driver_ldm);
+	pr_debug("PMIC ADC driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+module_init(pmic_adc_module_init);
+module_exit(pmic_adc_module_exit);
+
+MODULE_DESCRIPTION("PMIC ADC device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_adc_defs.h b/drivers/mxc/pmic/mc13783/pmic_adc_defs.h
new file mode 100644
index 000000000000..db1b08232c77
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_adc_defs.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_adc_defs.h
+ * @brief This header contains all defines for PMIC(mc13783) ADC driver.
+ *
+ * @ingroup PMIC_ADC
+ */
+
+#ifndef __MC13783_ADC__DEFS_H__
+#define __MC13783_ADC__DEFS_H__
+
+#define MC13783_ADC_DEVICE "/dev/mc13783_adc"
+
+#define         DEF_ADC_0     0x008000
+#define         DEF_ADC_3     0x000080
+
+#define ADC_NB_AVAILABLE        2
+
+#define MAX_CHANNEL             7
+
+/*
+ * Maximun allowed variation in the three X/Y co-ordinates acquired from
+ * touch-screen
+ */
+#define DELTA_Y_MAX             50
+#define DELTA_X_MAX             50
+
+/* Upon clearing the filter, this is the delay in restarting the filter */
+#define FILTER_MIN_DELAY        4
+
+/* Length of X and Y Touch screen filters */
+#define FILTLEN                 3
+
+#define TS_X_MAX                1000
+#define TS_Y_MAX                1000
+
+#define TS_X_MIN                80
+#define TS_Y_MIN                80
+
+#define MC13783_ADC0_TS_M_LSH	14
+#define MC13783_ADC0_TS_M_WID	3
+/*
+ * ADC 0
+ */
+#define ADC_WAIT_TSI_0		0x001C00
+
+/*
+ * ADC 1
+ */
+
+#define ADC_EN                  0x000001
+#define ADC_SGL_CH              0x000002
+#define ADC_ADSEL               0x000008
+#define ADC_CH_0_POS            5
+#define ADC_CH_0_MASK           0x0000E0
+#define ADC_CH_1_POS            8
+#define ADC_CH_1_MASK           0x000700
+#define ADC_DELAY_POS           11
+#define ADC_DELAY_MASK          0x07F800
+#define ADC_ATO                 0x080000
+#define ASC_ADC                 0x100000
+#define ADC_WAIT_TSI_1		0x300001
+#define ADC_CHRGRAW_D5          0x008000
+
+/*
+ * ADC 2 - 4
+ */
+#define ADD1_RESULT_MASK        0x00000FFC
+#define ADD2_RESULT_MASK        0x00FFC000
+#define ADC_TS_MASK             0x00FFCFFC
+
+/*
+ * ADC 3
+ */
+#define ADC_INC                 0x030000
+#define ADC_BIS                 0x800000
+
+/*
+ * ADC 3
+ */
+#define ADC_NO_ADTRIG           0x200000
+#define ADC_WCOMP               0x040000
+#define ADC_WCOMP_H_POS         0
+#define ADC_WCOMP_L_POS         9
+#define ADC_WCOMP_H_MASK        0x00003F
+#define ADC_WCOMP_L_MASK        0x007E00
+
+#define ADC_MODE_MASK           0x00003F
+
+/*
+ * Interrupt Status 0
+ */
+#define ADC_INT_BISDONEI        0x02
+
+/*!
+ * Define state mode of ADC.
+ */
+typedef enum adc_state {
+	/*!
+	 * Free.
+	 */
+	ADC_FREE,
+	/*!
+	 * Used.
+	 */
+	ADC_USED,
+	/*!
+	 * Monitoring
+	 */
+	ADC_MONITORING,
+} t_adc_state;
+
+/*!
+ * This enumeration, is used to configure the mode of ADC.
+ */
+typedef enum reading_mode {
+	/*!
+	 * Enables lithium cell reading
+	 */
+	M_LITHIUM_CELL = 0x000001,
+	/*!
+	 * Enables charge current reading
+	 */
+	M_CHARGE_CURRENT = 0x000002,
+	/*!
+	 * Enables battery current reading
+	 */
+	M_BATTERY_CURRENT = 0x000004,
+	/*!
+	 * Enables thermistor reading
+	 */
+	M_THERMISTOR = 0x000008,
+	/*!
+	 * Enables die temperature reading
+	 */
+	M_DIE_TEMPERATURE = 0x000010,
+	/*!
+	 * Enables UID reading
+	 */
+	M_UID = 0x000020,
+} t_reading_mode;
+
+/*!
+ * This enumeration, is used to configure the monitoring mode.
+ */
+typedef enum check_mode {
+	/*!
+	 * Comparator low level
+	 */
+	CHECK_LOW,
+	/*!
+	 * Comparator high level
+	 */
+	CHECK_HIGH,
+	/*!
+	 * Comparator low or high level
+	 */
+	CHECK_LOW_OR_HIGH,
+} t_check_mode;
+
+/*!
+ * This structure is used to configure and report adc value.
+ */
+typedef struct {
+	/*!
+	 * Delay before first conversion
+	 */
+	unsigned int delay;
+	/*!
+	 * sets the ATX bit for delay on all conversion
+	 */
+	bool conv_delay;
+	/*!
+	 * Sets the single channel mode
+	 */
+	bool single_channel;
+	/*!
+	 * Selects the set of inputs
+	 */
+	bool group;
+	/*!
+	 * Channel selection 1
+	 */
+	t_channel channel_0;
+	/*!
+	 * Channel selection 2
+	 */
+	t_channel channel_1;
+	/*!
+	 * Used to configure ADC mode with t_reading_mode
+	 */
+	t_reading_mode read_mode;
+	/*!
+	 * Sets the Touch screen mode
+	 */
+	bool read_ts;
+	/*!
+	 * Wait TSI event before touch screen reading
+	 */
+	bool wait_tsi;
+	/*!
+	 * Sets CHRGRAW scaling to divide by 5
+	 * Only supported on 2.0 and higher
+	 */
+	bool chrgraw_devide_5;
+	/*!
+	 * Return ADC values
+	 */
+	unsigned int value[8];
+	/*!
+	 * Return touch screen values
+	 */
+	t_touch_screen ts_value;
+} t_adc_param;
+
+/*!
+ * This structure is used to configure the monitoring mode of ADC.
+ */
+typedef struct {
+	/*!
+	 * Delay before first conversion
+	 */
+	unsigned int delay;
+	/*!
+	 * sets the ATX bit for delay on all conversion
+	 */
+	bool conv_delay;
+	/*!
+	 * Channel selection 1
+	 */
+	t_channel channel;
+	/*!
+	 * Selects the set of inputs
+	 */
+	bool group;
+	/*!
+	 * Used to configure ADC mode with t_reading_mode
+	 */
+	unsigned int read_mode;
+	/*!
+	 * Comparator low level in WCOMP mode
+	 */
+	unsigned int comp_low;
+	/*!
+	 * Comparator high level in WCOMP mode
+	 */
+	unsigned int comp_high;
+	/*!
+	 * Sets type of monitoring (low, high or both)
+	 */
+	t_check_mode check_mode;
+	/*!
+	 * Callback to be launched when event is detected
+	 */
+	void (*callback) (void);
+} t_monitoring_param;
+
+/*!
+ * This function performs filtering and rejection of excessive noise prone
+ * samples.
+ *
+ * @param        ts_curr     Touch screen value
+ *
+ * @return       This function returns 0 on success, -1 otherwise.
+ */
+static int pmic_adc_filter(t_touch_screen * ts_curr);
+
+/*!
+ * This function request a ADC.
+ *
+ * @return      This function returns index of ADC to be used (0 or 1) if successful.
+                return -1 if error.
+ */
+int mc13783_adc_request(bool read_ts);
+
+/*!
+ * This function is used to update buffer of touch screen value in read mode.
+ */
+void update_buffer(void);
+
+/*!
+ * This function release an ADC.
+ *
+ * @param        adc_index     index of ADC to be released.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int mc13783_adc_release(int adc_index);
+
+/*!
+ * This function select the required read_mode for a specific channel.
+ *
+ * @param        channel   The channel to be sampled
+ *
+ * @return       This function returns the requires read_mode
+ */
+t_reading_mode mc13783_set_read_mode(t_channel channel);
+
+/*!
+ * This function read the touch screen value.
+ *
+ * @param        touch_sample    return value of touch screen
+ * @param        wait_tsi    if true, this function is synchronous (wait in TSI event).
+ *
+ * @return       This function returns 0.
+ */
+PMIC_STATUS mc13783_adc_read_ts(t_touch_screen * touch_sample, int wait_tsi);
+
+#endif				/* __MC13783_ADC__DEFS_H__ */
diff --git a/drivers/mxc/pmic/mc13783/pmic_audio.c b/drivers/mxc/pmic/mc13783/pmic_audio.c
new file mode 100644
index 000000000000..6aab4b83f6ea
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_audio.c
@@ -0,0 +1,5876 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_audio.c
+ * @brief Implementation of the PMIC(mc13783) Audio driver APIs.
+ *
+ * The PMIC Audio driver and this API were developed to support the
+ * audio playback, recording, and mixing capabilities of the power
+ * management ICs that are available from Freescale Semiconductor, Inc.
+ *
+ * The following operating modes are supported:
+ *
+ * @verbatim
+       Operating Mode               mc13783
+       ---------------------------- -------
+       Stereo DAC Playback           Yes
+       Stereo DAC Input Mixing       Yes
+       Voice CODEC Playback          Yes
+       Voice CODEC Input Mixing      Yes
+       Voice CODEC Mono Recording    Yes
+       Voice CODEC Stereo Recording  Yes
+       Microphone Bias Control       Yes
+       Output Amplifier Control      Yes
+       Output Mixing Control         Yes
+       Input Amplifier Control       Yes
+       Master/Slave Mode Select      Yes
+       Anti Pop Bias Circuit Control Yes
+   @endverbatim
+ *
+ * Note that the Voice CODEC may also be referred to as the Telephone
+ * CODEC in the PMIC DTS documentation. Also note that, while the power
+ * management ICs do provide similar audio capabilities, each PMIC may
+ * support additional configuration settings and features. Therefore, it
+ * is highly recommended that the appropriate power management IC DTS
+ * documents be used in conjunction with this API interface.
+ *
+ * @ingroup PMIC_AUDIO
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>	/* For tasklet interface.              */
+#include <linux/platform_device.h>	/* For kernel module interface.        */
+#include <linux/init.h>
+#include <linux/spinlock.h>	/* For spinlock interface.             */
+#include <linux/pmic_adc.h>	/* For PMIC ADC driver interface.      */
+#include <linux/pmic_status.h>
+#include <mach/pmic_audio.h>	/* For PMIC Audio driver interface.    */
+
+/*
+ * mc13783 PMIC Audio API
+ */
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(MIN_STDAC_SAMPLING_RATE_HZ);
+EXPORT_SYMBOL(MAX_STDAC_SAMPLING_RATE_HZ);
+EXPORT_SYMBOL(pmic_audio_open);
+EXPORT_SYMBOL(pmic_audio_close);
+EXPORT_SYMBOL(pmic_audio_set_protocol);
+EXPORT_SYMBOL(pmic_audio_get_protocol);
+EXPORT_SYMBOL(pmic_audio_enable);
+EXPORT_SYMBOL(pmic_audio_disable);
+EXPORT_SYMBOL(pmic_audio_reset);
+EXPORT_SYMBOL(pmic_audio_reset_all);
+EXPORT_SYMBOL(pmic_audio_set_callback);
+EXPORT_SYMBOL(pmic_audio_clear_callback);
+EXPORT_SYMBOL(pmic_audio_get_callback);
+EXPORT_SYMBOL(pmic_audio_antipop_enable);
+EXPORT_SYMBOL(pmic_audio_antipop_disable);
+EXPORT_SYMBOL(pmic_audio_digital_filter_reset);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_clock);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_clock);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_rxtx_timeslot);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_rxtx_timeslot);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_secondary_txslot);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_secondary_txslot);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_config);
+EXPORT_SYMBOL(pmic_audio_vcodec_clear_config);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_config);
+EXPORT_SYMBOL(pmic_audio_vcodec_enable_bypass);
+EXPORT_SYMBOL(pmic_audio_vcodec_disable_bypass);
+EXPORT_SYMBOL(pmic_audio_stdac_set_clock);
+EXPORT_SYMBOL(pmic_audio_stdac_get_clock);
+EXPORT_SYMBOL(pmic_audio_stdac_set_rxtx_timeslot);
+EXPORT_SYMBOL(pmic_audio_stdac_get_rxtx_timeslot);
+EXPORT_SYMBOL(pmic_audio_stdac_set_config);
+EXPORT_SYMBOL(pmic_audio_stdac_clear_config);
+EXPORT_SYMBOL(pmic_audio_stdac_get_config);
+EXPORT_SYMBOL(pmic_audio_input_set_config);
+EXPORT_SYMBOL(pmic_audio_input_clear_config);
+EXPORT_SYMBOL(pmic_audio_input_get_config);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_mic);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_mic);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_mic_on_off);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_mic_on_off);
+EXPORT_SYMBOL(pmic_audio_vcodec_set_record_gain);
+EXPORT_SYMBOL(pmic_audio_vcodec_get_record_gain);
+EXPORT_SYMBOL(pmic_audio_vcodec_enable_micbias);
+EXPORT_SYMBOL(pmic_audio_vcodec_disable_micbias);
+EXPORT_SYMBOL(pmic_audio_vcodec_enable_mixer);
+EXPORT_SYMBOL(pmic_audio_vcodec_disable_mixer);
+EXPORT_SYMBOL(pmic_audio_stdac_enable_mixer);
+EXPORT_SYMBOL(pmic_audio_stdac_disable_mixer);
+EXPORT_SYMBOL(pmic_audio_output_set_port);
+EXPORT_SYMBOL(pmic_audio_output_get_port);
+EXPORT_SYMBOL(pmic_audio_output_clear_port);
+EXPORT_SYMBOL(pmic_audio_output_set_stereo_in_gain);
+EXPORT_SYMBOL(pmic_audio_output_get_stereo_in_gain);
+EXPORT_SYMBOL(pmic_audio_output_set_pgaGain);
+EXPORT_SYMBOL(pmic_audio_output_get_pgaGain);
+EXPORT_SYMBOL(pmic_audio_output_enable_mixer);
+EXPORT_SYMBOL(pmic_audio_output_disable_mixer);
+EXPORT_SYMBOL(pmic_audio_output_set_balance);
+EXPORT_SYMBOL(pmic_audio_output_get_balance);
+EXPORT_SYMBOL(pmic_audio_output_enable_mono_adder);
+EXPORT_SYMBOL(pmic_audio_output_disable_mono_adder);
+EXPORT_SYMBOL(pmic_audio_output_set_mono_adder_gain);
+EXPORT_SYMBOL(pmic_audio_output_get_mono_adder_gain);
+EXPORT_SYMBOL(pmic_audio_output_set_config);
+EXPORT_SYMBOL(pmic_audio_output_clear_config);
+EXPORT_SYMBOL(pmic_audio_output_get_config);
+EXPORT_SYMBOL(pmic_audio_output_enable_phantom_ground);
+EXPORT_SYMBOL(pmic_audio_output_disable_phantom_ground);
+EXPORT_SYMBOL(pmic_audio_set_autodetect);
+#ifdef DEBUG_AUDIO
+EXPORT_SYMBOL(pmic_audio_dump_registers);
+#endif				/* DEBUG_AUDIO */
+/*!
+ * Define the minimum sampling rate (in Hz) that is supported by the
+ * Stereo DAC.
+ */
+const unsigned MIN_STDAC_SAMPLING_RATE_HZ = 8000;
+
+/*!
+ * Define the maximum sampling rate (in Hz) that is supported by the
+ * Stereo DAC.
+ */
+const unsigned MAX_STDAC_SAMPLING_RATE_HZ = 96000;
+
+/*! @def SET_BITS
+ * Set a register field to a given value.
+ */
+#define SET_BITS(reg, field, value)    (((value) << reg.field.offset) & \
+                                        reg.field.mask)
+/*! @def GET_BITS
+ * Get the current value of a given register field.
+ */
+#define GET_BITS(reg, field, value)    (((value) & reg.field.mask) >> \
+                                        reg.field.offset)
+
+/*!
+ * @brief Define the possible states for a device handle.
+ *
+ * This enumeration is used to track the current state of each device handle.
+ */
+typedef enum {
+	HANDLE_FREE,		/*!< Handle is available for use. */
+	HANDLE_IN_USE		/*!< Handle is currently in use.  */
+} HANDLE_STATE;
+
+/*!
+ * @brief Identifies the hardware interrupt source.
+ *
+ * This enumeration identifies which of the possible hardware interrupt
+ * sources actually caused the current interrupt handler to be called.
+ */
+typedef enum {
+	CORE_EVENT_MC2BI,	/*!< Microphone Bias 2 detect. */
+	CORE_EVENT_HSDETI,	/*!< Detect Headset attach  */
+	CORE_EVENT_HSLI,	/*!< Detect Stereo Headset  */
+	CORE_EVENT_ALSPTHI,	/*!< Detect Thermal shutdown of ALSP  */
+	CORE_EVENT_AHSSHORTI	/*!< Detect Short circuit on AHS outputs  */
+} PMIC_CORE_EVENT;
+
+/*!
+ * @brief This structure is used to track the state of a microphone input.
+ */
+typedef struct {
+	PMIC_AUDIO_INPUT_PORT mic;	/*!< Microphone input port.      */
+	PMIC_AUDIO_INPUT_MIC_STATE micOnOff;	/*!< Microphone On/Off state.    */
+	PMIC_AUDIO_MIC_AMP_MODE ampMode;	/*!< Input amplifier mode.       */
+	PMIC_AUDIO_MIC_GAIN gain;	/*!< Input amplifier gain level. */
+} PMIC_MICROPHONE_STATE;
+
+/*!
+ * @brief Tracks whether a headset is currently attached or not.
+ */
+typedef enum {
+	NO_HEADSET,		/*!< No headset currently attached. */
+	HEADSET_ON		/*!< Headset has been attached.     */
+} HEADSET_STATUS;
+
+/*!
+ * @brief mc13783 only enum that indicates the path to output taken
+ * by the voice codec output
+ */
+typedef enum {
+	VCODEC_DIRECT_OUT,	/*!< Vcodec signal out direct */
+	VCODEC_MIXER_OUT	/*!< Output via the mixer     */
+} PMIC_AUDIO_VCODEC_OUTPUT_PATH;
+
+/*!
+ * @brief This structure is used to define a specific hardware register field.
+ *
+ * All hardware register fields are defined using an offset to the LSB
+ * and a mask. The offset is used to right shift a register value before
+ * applying the mask to actually obtain the value of the field.
+ */
+typedef struct {
+	const unsigned char offset;	/*!< Offset of LSB of register field.          */
+	const unsigned int mask;	/*!< Mask value used to isolate register field. */
+} REGFIELD;
+
+/*!
+ * @brief This structure lists all fields of the AUD_CODEC hardware register.
+ */
+typedef struct {
+	REGFIELD CDCSSISEL;	/*!< codec SSI bus select              */
+	REGFIELD CDCCLKSEL;	/*!< Codec clock input select          */
+	REGFIELD CDCSM;		/*!< Codec slave / master select       */
+	REGFIELD CDCBCLINV;	/*!< Codec bitclock inversion          */
+	REGFIELD CDCFSINV;	/*!< Codec framesync inversion         */
+	REGFIELD CDCFS;		/*!< Bus protocol selection - 2 bits   */
+	REGFIELD CDCCLK;	/*!< Codec clock setting - 3 bits      */
+	REGFIELD CDCFS8K16K;	/*!< Codec framesync select            */
+	REGFIELD CDCEN;		/*!< Codec enable                      */
+	REGFIELD CDCCLKEN;	/*!< Codec clocking enable             */
+	REGFIELD CDCTS;		/*!< Codec SSI tristate                */
+	REGFIELD CDCDITH;	/*!< Codec dithering                   */
+	REGFIELD CDCRESET;	/*!< Codec filter reset                */
+	REGFIELD CDCBYP;	/*!< Codec bypass                      */
+	REGFIELD CDCALM;	/*!< Codec analog loopback             */
+	REGFIELD CDCDLM;	/*!< Codec digital loopback            */
+	REGFIELD AUDIHPF;	/*!< Transmit high pass filter enable  */
+	REGFIELD AUDOHPF;	/*!< Receive high pass filter enable   */
+} REGISTER_AUD_CODEC;
+
+/*!
+ * @brief This variable is used to access the AUD_CODEC hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * AUD_CODEC hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_AUD_CODEC regAUD_CODEC = {
+	{0, 0x000001},		/* CDCSSISEL    */
+	{1, 0x000002},		/* CDCCLKSEL    */
+	{2, 0x000004},		/* CDCSM        */
+	{3, 0x000008},		/* CDCBCLINV    */
+	{4, 0x000010},		/* CDCFSINV     */
+	{5, 0x000060},		/* CDCFS        */
+	{7, 0x000380},		/* CDCCLK       */
+	{10, 0x000400},		/* CDCFS8K16K   */
+	{11, 0x000800},		/* CDCEN        */
+	{12, 0x001000},		/* CDCCLKEN     */
+	{13, 0x002000},		/* CDCTS        */
+	{14, 0x004000},		/* CDCDITH      */
+	{15, 0x008000},		/* CDCRESET     */
+	{16, 0x010000},		/* CDCBYP       */
+	{17, 0x020000},		/* CDCALM       */
+	{18, 0x040000},		/* CDCDLM       */
+	{19, 0x080000},		/* AUDIHPF      */
+	{20, 0x100000}		/* AUDOHPF      */
+	/* Unused       */
+	/* Unused       */
+	/* Unused       */
+
+};
+
+/*!
+ * @brief This structure lists all fields of the ST_DAC hardware register.
+ */
+ /* VVV */
+typedef struct {
+	REGFIELD STDCSSISEL;	/*!< Stereo DAC SSI bus select                            */
+	REGFIELD STDCCLKSEL;	/*!< Stereo DAC clock input select                        */
+	REGFIELD STDCSM;	/*!< Stereo DAC slave / master select                     */
+	REGFIELD STDCBCLINV;	/*!< Stereo DAC bitclock inversion                        */
+	REGFIELD STDCFSINV;	/*!< Stereo DAC framesync inversion                       */
+	REGFIELD STDCFS;	/*!< Bus protocol selection - 2 bits                      */
+	REGFIELD STDCCLK;	/*!< Stereo DAC clock setting - 3 bits                    */
+	REGFIELD STDCFSDLYB;	/*!< Stereo DAC framesync delay bar                       */
+	REGFIELD STDCEN;	/*!< Stereo DAC enable                                    */
+	REGFIELD STDCCLKEN;	/*!< Stereo DAC clocking enable                           */
+	REGFIELD STDCRESET;	/*!< Stereo DAC filter reset                              */
+	REGFIELD SPDIF;		/*!< Stereo DAC SSI SPDIF mode. Mode no longer available. */
+	REGFIELD SR;		/*!< Stereo DAC sample rate - 4 bits                      */
+} REGISTER_ST_DAC;
+
+/*!
+ * @brief This variable is used to access the ST_DAC hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * ST_DAC hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_ST_DAC regST_DAC = {
+	{0, 0x000001},		/* STDCSSISEL        */
+	{1, 0x000002},		/* STDCCLKSEL        */
+	{2, 0x000004},		/* STDCSM            */
+	{3, 0x000008},		/* STDCBCLINV        */
+	{4, 0x000010},		/* STDCFSINV         */
+	{5, 0x000060},		/* STDCFS            */
+	{7, 0x000380},		/* STDCCLK           */
+	{10, 0x000400},		/* STDCFSDLYB        */
+	{11, 0x000800},		/* STDCEN            */
+	{12, 0x001000},		/* STDCCLKEN         */
+	{15, 0x008000},		/* STDCRESET         */
+	{16, 0x010000},		/* SPDIF             */
+	{17, 0x1E0000}		/* SR                */
+};
+
+/*!
+ * @brief This structure lists all of the fields in the SSI_NETWORK hardware register.
+ */
+typedef struct {
+	REGFIELD CDCTXRXSLOT;	/*!< Codec timeslot assignment  - 2 bits                                  */
+	REGFIELD CDCTXSECSLOT;	/*!< Codec secondary transmit timeslot - 2 bits                           */
+	REGFIELD CDCRXSECSLOT;	/*!< Codec secondary receive timeslot - 2 bits                            */
+	REGFIELD CDCRXSECGAIN;	/*!< Codec secondary receive channel gain setting - 2 bits                */
+	REGFIELD CDCSUMGAIN;	/*!< Codec summed receive signal gain setting                             */
+	REGFIELD CDCFSDLY;	/*!< Codec framesync delay                                                */
+	REGFIELD STDCSLOTS;	/*!< Stereo DAC number of timeslots select  - 2 bits                      */
+	REGFIELD STDCRXSLOT;	/*!< Stereo DAC timeslot assignment - 2 bits                              */
+	REGFIELD STDCRXSECSLOT;	/*!< Stereo DAC secondary receive timeslot  - 2 bits                      */
+	REGFIELD STDCRXSECGAIN;	/*!< Stereo DAC secondary receive channel gain setting   - 2 bits         */
+	REGFIELD STDCSUMGAIN;	/*!< Stereo DAC summed receive signal gain setting                        */
+} REGISTER_SSI_NETWORK;
+
+/*!
+ * @brief This variable is used to access the SSI_NETWORK hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * SSI_NETWORK hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_SSI_NETWORK regSSI_NETWORK = {
+	{2, 0x00000c},		/* CDCTXRXSLOT          */
+	{4, 0x000030},		/* CDCTXSECSLOT         */
+	{6, 0x0000c0},		/* CDCRXSECSLOT         */
+	{8, 0x000300},		/* CDCRXSECGAIN         */
+	{10, 0x000400},		/* CDCSUMGAIN           */
+	{11, 0x000800},		/* CDCFSDLY             */
+	{12, 0x003000},		/* STDCSLOTS            */
+	{14, 0x00c000},		/* STDCRXSLOT           */
+	{16, 0x030000},		/* STDCRXSECSLOT        */
+	{18, 0x0c0000},		/* STDCRXSECGAIN        */
+	{20, 0x100000}		/* STDCSUMGAIN          */
+};
+
+/*!
+ * @brief This structure lists all fields of the AUDIO_TX hardware register.
+ *
+ *
+ */
+typedef struct {
+	REGFIELD MC1BEN;	/*!< Microphone bias 1 enable                                */
+	REGFIELD MC2BEN;	/*!< Microphone bias 2 enable                                */
+	REGFIELD MC2BDETDBNC;	/*!< Microphone bias detect debounce setting                 */
+	REGFIELD MC2BDETEN;	/*!< Microphone bias 2 detect enable                         */
+	REGFIELD AMC1REN;	/*!< Amplifier Amc1R enable                                  */
+	REGFIELD AMC1RITOV;	/*!< Amplifier Amc1R current to voltage mode enable          */
+	REGFIELD AMC1LEN;	/*!< Amplifier Amc1L enable                                  */
+	REGFIELD AMC1LITOV;	/*!< Amplifier Amc1L current to voltage mode enable          */
+	REGFIELD AMC2EN;	/*!< Amplifier Amc2 enable                                   */
+	REGFIELD AMC2ITOV;	/*!< Amplifier Amc2 current to voltage mode enable           */
+	REGFIELD ATXINEN;	/*!< Amplifier Atxin enable                                  */
+	REGFIELD ATXOUTEN;	/*!< Reserved for output TXOUT enable, currently not used    */
+	REGFIELD RXINREC;	/*!< RXINR/RXINL to voice CODEC ADC routing enable           */
+	REGFIELD PGATXR;	/*!< Transmit gain setting right - 5 bits                    */
+	REGFIELD PGATXL;	/*!< Transmit gain setting left  - 5 bits                    */
+} REGISTER_AUDIO_TX;
+
+/*!
+ * @brief This variable is used to access the AUDIO_TX hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * AUDIO_TX hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_AUDIO_TX regAUDIO_TX = {
+	{0, 0x000001},		/* MC1BEN              */
+	{1, 0x000002},		/* MC2BEN              */
+	{2, 0x000004},		/* MC2BDETDBNC         */
+	{3, 0x000008},		/* MC2BDETEN           */
+	{5, 0x000020},		/* AMC1REN             */
+	{6, 0x000040},		/* AMC1RITOV           */
+	{7, 0x000080},		/* AMC1LEN             */
+	{8, 0x000100},		/* AMC1LITOV           */
+	{9, 0x000200},		/* AMC2EN              */
+	{10, 0x000400},		/* AMC2ITOV            */
+	{11, 0x000800},		/* ATXINEN             */
+	{12, 0x001000},		/* ATXOUTEN            */
+	{13, 0x002000},		/* RXINREC             */
+	{14, 0x07c000},		/* PGATXR              */
+	{19, 0xf80000}		/* PGATXL              */
+};
+
+/*!
+ * @brief This structure lists all fields of the AUDIO_RX_0 hardware register.
+ */
+typedef struct {
+	REGFIELD VAUDIOON;	/*!<    Forces VAUDIO in active on mode               */
+	REGFIELD BIASEN;	/*!<    Audio bias enable                             */
+	REGFIELD BIASSPEED;	/*!<    Turn on ramp speed of the audio bias          */
+	REGFIELD ASPEN;		/*!<    Amplifier Asp enable                          */
+	REGFIELD ASPSEL;	/*!<    Asp input selector                            */
+	REGFIELD ALSPEN;	/*!<    Amplifier Alsp enable                         */
+	REGFIELD ALSPREF;	/*!<    Bias Alsp at common audio reference           */
+	REGFIELD ALSPSEL;	/*!<    Alsp input selector                           */
+	REGFIELD LSPLEN;	/*!<    Output LSPL enable                            */
+	REGFIELD AHSREN;	/*!<    Amplifier AhsR enable                         */
+	REGFIELD AHSLEN;	/*!<    Amplifier AhsL enable                         */
+	REGFIELD AHSSEL;	/*!<    Ahsr and Ahsl input selector                  */
+	REGFIELD HSPGDIS;	/*!<    Phantom ground disable                        */
+	REGFIELD HSDETEN;	/*!<    Headset detect enable                         */
+	REGFIELD HSDETAUTOB;	/*!<    Amplifier state determined by headset detect  */
+	REGFIELD ARXOUTREN;	/*!<    Output RXOUTR enable                          */
+	REGFIELD ARXOUTLEN;	/*!<    Output RXOUTL enable                          */
+	REGFIELD ARXOUTSEL;	/*!<    Arxout input selector                         */
+	REGFIELD CDCOUTEN;	/*!<    Output CDCOUT enable                          */
+	REGFIELD HSLDETEN;	/*!<    Headset left channel detect enable            */
+	REGFIELD ADDCDC;	/*!<    Adder channel codec selection                 */
+	REGFIELD ADDSTDC;	/*!<    Adder channel stereo DAC selection            */
+	REGFIELD ADDRXIN;	/*!<    Adder channel line in selection               */
+} REGISTER_AUDIO_RX_0;
+
+/*!
+ * @brief This variable is used to access the AUDIO_RX_0 hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * AUDIO_RX_0 hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_AUDIO_RX_0 regAUDIO_RX_0 = {
+	{0, 0x000001},		/* VAUDIOON    */
+	{1, 0x000002},		/* BIASEN      */
+	{2, 0x000004},		/* BIASSPEED   */
+	{3, 0x000008},		/* ASPEN       */
+	{4, 0x000010},		/* ASPSEL      */
+	{5, 0x000020},		/* ALSPEN      */
+	{6, 0x000040},		/* ALSPREF     */
+	{7, 0x000080},		/* ALSPSEL     */
+	{8, 0x000100},		/* LSPLEN      */
+	{9, 0x000200},		/* AHSREN      */
+	{10, 0x000400},		/* AHSLEN      */
+	{11, 0x000800},		/* AHSSEL      */
+	{12, 0x001000},		/* HSPGDIS     */
+	{13, 0x002000},		/* HSDETEN     */
+	{14, 0x004000},		/* HSDETAUTOB  */
+	{15, 0x008000},		/* ARXOUTREN   */
+	{16, 0x010000},		/* ARXOUTLEN   */
+	{17, 0x020000},		/* ARXOUTSEL   */
+	{18, 0x040000},		/* CDCOUTEN    */
+	{19, 0x080000},		/* HSLDETEN    */
+	{21, 0x200000},		/* ADDCDC      */
+	{22, 0x400000},		/* ADDSTDC     */
+	{23, 0x800000}		/* ADDRXIN     */
+};
+
+/*!
+ * @brief This structure lists all fields of the AUDIO_RX_1 hardware register.
+ */
+typedef struct {
+	REGFIELD PGARXEN;	/*!<    Codec receive PGA enable                 */
+	REGFIELD PGARX;		/*!<    Codec receive gain setting - 4 bits      */
+	REGFIELD PGASTEN;	/*!<    Stereo DAC PGA enable                    */
+	REGFIELD PGAST;		/*!<    Stereo DAC gain setting  - 4 bits        */
+	REGFIELD ARXINEN;	/*!<    Amplifier Arx enable                     */
+	REGFIELD ARXIN;		/*!<    Amplifier Arx additional gain setting    */
+	REGFIELD PGARXIN;	/*!<    PGArxin gain setting  - 4 bits           */
+	REGFIELD MONO;		/*!<    Mono adder setting   - 2 bits            */
+	REGFIELD BAL;		/*!<    Balance control      - 3 bits            */
+	REGFIELD BALLR;		/*!<    Left / right balance                     */
+} REGISTER_AUDIO_RX_1;
+
+/*!
+ * @brief This variable is used to access the AUDIO_RX_1 hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * AUDIO_RX_1 hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const REGISTER_AUDIO_RX_1 regAUDIO_RX_1 = {
+	{0, 0x000001},		/* PGARXEN    */
+	{1, 0x00001e},		/* PGARX      */
+	{5, 0x000020},		/* PGASTEN   */
+	{6, 0x0003c0},		/* PGAST       */
+	{10, 0x000400},		/* ARXINEN      */
+	{11, 0x000800},		/* ARXIN      */
+	{12, 0x00f000},		/* PGARXIN     */
+	{16, 0x030000},		/* MONO     */
+	{18, 0x1c0000},		/* BAL      */
+	{21, 0x200000}		/* BALLR      */
+};
+
+/*! Define a mask to access the entire hardware register. */
+static const unsigned int REG_FULLMASK = 0xffffff;
+
+/*! Reset value for the AUD_CODEC register. */
+static const unsigned int RESET_AUD_CODEC = 0x180027;
+
+/*! Reset value for the ST_DAC register.
+ *
+ *  Note that we avoid resetting any of the arbitration bits.
+ */
+static const unsigned int RESET_ST_DAC = 0x0E0004;
+
+/*! Reset value for the SSI_NETWORK register. */
+static const unsigned int RESET_SSI_NETWORK = 0x013060;
+
+/*! Reset value for the AUDIO_TX register.
+ *
+ *  Note that we avoid resetting any of the arbitration bits.
+ */
+static const unsigned int RESET_AUDIO_TX = 0x420000;
+
+/*! Reset value for the AUDIO_RX_0 register. */
+static const unsigned int RESET_AUDIO_RX_0 = 0x001000;
+
+/*! Reset value for the AUDIO_RX_1 register. */
+static const unsigned int RESET_AUDIO_RX_1 = 0x00D35A;
+
+/*! Reset mask for the SSI network Vcodec part. first 12 bits
+ * 0 - 11 */
+static const unsigned int REG_SSI_VCODEC_MASK = 0x000fff;
+
+/*! Reset mask for the SSI network STDAC part. last 12 bits
+ * 12 - 24 */
+static const unsigned int REG_SSI_STDAC_MASK = 0xfff000;
+
+/*! Constant NULL value for initializing/reseting the audio handles. */
+static const PMIC_AUDIO_HANDLE AUDIO_HANDLE_NULL = (PMIC_AUDIO_HANDLE) NULL;
+
+/*!
+ * @brief This structure maintains the current state of the Stereo DAC.
+ */
+typedef struct {
+	PMIC_AUDIO_HANDLE handle;	/*!< Handle used to access
+					   the Stereo DAC.         */
+	HANDLE_STATE handleState;	/*!< Current handle state.   */
+	PMIC_AUDIO_DATA_BUS busID;	/*!< Data bus used to access
+					   the Stereo DAC.         */
+	bool protocol_set;
+	PMIC_AUDIO_BUS_PROTOCOL protocol;	/*!< Data bus protocol.      */
+	PMIC_AUDIO_BUS_MODE masterSlave;	/*!< Master/Slave mode
+						   select.                 */
+	PMIC_AUDIO_NUMSLOTS numSlots;	/*!< Number of timeslots
+					   used.                   */
+	PMIC_AUDIO_CALLBACK callback;	/*!< Event notification
+					   callback function
+					   pointer.                */
+	PMIC_AUDIO_EVENTS eventMask;	/*!< Event notification mask. */
+	PMIC_AUDIO_CLOCK_IN_SOURCE clockIn;	/*!< Stereo DAC clock input
+						   source select.          */
+	PMIC_AUDIO_STDAC_SAMPLING_RATE samplingRate;	/*!< Stereo DAC sampling rate
+							   select.                 */
+	PMIC_AUDIO_STDAC_CLOCK_IN_FREQ clockFreq;	/*!< Stereo DAC clock input
+							   frequency.              */
+	PMIC_AUDIO_CLOCK_INVERT invert;	/*!< Stereo DAC clock signal
+					   invert select.          */
+	PMIC_AUDIO_STDAC_TIMESLOTS timeslot;	/*!< Stereo DAC data
+						   timeslots select.       */
+	PMIC_AUDIO_STDAC_CONFIG config;	/*!< Stereo DAC configuration
+					   options.                */
+} PMIC_AUDIO_STDAC_STATE;
+
+/*!
+ * @brief This variable maintains the current state of the Stereo DAC.
+ *
+ * This variable tracks the current state of the Stereo DAC audio hardware
+ * along with any information that is required by the device driver to
+ * manage the hardware (e.g., callback functions and event notification
+ * masks).
+ *
+ * The initial values represent the reset/power on state of the Stereo DAC.
+ */
+static PMIC_AUDIO_STDAC_STATE stDAC = {
+	(PMIC_AUDIO_HANDLE) NULL,	/* handle       */
+	HANDLE_FREE,		/* handleState  */
+	AUDIO_DATA_BUS_1,	/* busID        */
+	false,
+	NORMAL_MSB_JUSTIFIED_MODE,	/* protocol     */
+	BUS_MASTER_MODE,	/* masterSlave  */
+	USE_2_TIMESLOTS,	/* numSlots     */
+	(PMIC_AUDIO_CALLBACK) NULL,	/* callback     */
+	(PMIC_AUDIO_EVENTS) NULL,	/* eventMask    */
+	CLOCK_IN_CLIA,		/* clockIn      */
+	STDAC_RATE_44_1_KHZ,	/* samplingRate */
+	STDAC_CLI_13MHZ,	/* clockFreq    */
+	NO_INVERT,		/* invert       */
+	USE_TS0_TS1,		/* timeslot     */
+	(PMIC_AUDIO_STDAC_CONFIG) 0	/* config       */
+};
+
+/*!
+ * @brief This structure maintains the current state of the Voice CODEC.
+ */
+typedef struct {
+	PMIC_AUDIO_HANDLE handle;	/*!< Handle used to access
+					   the Voice CODEC.       */
+	HANDLE_STATE handleState;	/*!< Current handle state.  */
+	PMIC_AUDIO_DATA_BUS busID;	/*!< Data bus used to access
+					   the Voice CODEC.       */
+	bool protocol_set;
+	PMIC_AUDIO_BUS_PROTOCOL protocol;	/*!< Data bus protocol.     */
+	PMIC_AUDIO_BUS_MODE masterSlave;	/*!< Master/Slave mode
+						   select.                */
+	PMIC_AUDIO_NUMSLOTS numSlots;	/*!< Number of timeslots
+					   used.                  */
+	PMIC_AUDIO_CALLBACK callback;	/*!< Event notification
+					   callback function
+					   pointer.               */
+	PMIC_AUDIO_EVENTS eventMask;	/*!< Event notification
+					   mask.                  */
+	PMIC_AUDIO_CLOCK_IN_SOURCE clockIn;	/*!< Voice CODEC clock input
+						   source select.         */
+	PMIC_AUDIO_VCODEC_SAMPLING_RATE samplingRate;	/*!< Voice CODEC sampling
+							   rate select.           */
+	PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ clockFreq;	/*!< Voice CODEC clock input
+							   frequency.             */
+	PMIC_AUDIO_CLOCK_INVERT invert;	/*!< Voice CODEC clock
+					   signal invert select.  */
+	PMIC_AUDIO_VCODEC_TIMESLOT timeslot;	/*!< Voice CODEC data
+						   timeslot select.       */
+	PMIC_AUDIO_VCODEC_TIMESLOT secondaryTXtimeslot;
+
+	PMIC_AUDIO_VCODEC_CONFIG config;	/*!< Voice CODEC
+						   configuration
+						   options.            */
+	PMIC_MICROPHONE_STATE leftChannelMic;	/*!< Left channel
+						   microphone
+						   configuration.      */
+	PMIC_MICROPHONE_STATE rightChannelMic;	/*!< Right channel
+						   microphone
+						   configuration.      */
+} PMIC_AUDIO_VCODEC_STATE;
+
+/*!
+ * @brief This variable maintains the current state of the Voice CODEC.
+ *
+ * This variable tracks the current state of the Voice CODEC audio hardware
+ * along with any information that is required by the device driver to
+ * manage the hardware (e.g., callback functions and event notification
+ * masks).
+ *
+ * The initial values represent the reset/power on state of the Voice CODEC.
+ */
+static PMIC_AUDIO_VCODEC_STATE vCodec = {
+	(PMIC_AUDIO_HANDLE) NULL,	/* handle          */
+	HANDLE_FREE,		/* handleState     */
+	AUDIO_DATA_BUS_2,	/* busID           */
+	false,
+	NETWORK_MODE,		/* protocol        */
+	BUS_SLAVE_MODE,		/* masterSlave     */
+	USE_4_TIMESLOTS,	/* numSlots        */
+	(PMIC_AUDIO_CALLBACK) NULL,	/* callback        */
+	(PMIC_AUDIO_EVENTS) NULL,	/* eventMask       */
+	CLOCK_IN_CLIB,		/* clockIn         */
+	VCODEC_RATE_8_KHZ,	/* samplingRate    */
+	VCODEC_CLI_13MHZ,	/* clockFreq       */
+	NO_INVERT,		/* invert          */
+	USE_TS0,		/* timeslot pri    */
+	USE_TS2,		/* timeslot sec TX */
+	INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER,	/* config          */
+	/* leftChannelMic  */
+	{NO_MIC,		/*    mic          */
+	 MICROPHONE_OFF,	/*    micOnOff     */
+	 AMP_OFF,		/*    ampMode      */
+	 MIC_GAIN_0DB		/*    gain         */
+	 },
+	/* rightChannelMic */
+	{NO_MIC,		/*    mic          */
+	 MICROPHONE_OFF,	/*    micOnOff     */
+	 AMP_OFF,		/*    ampMode      */
+	 MIC_GAIN_0DB		/*    gain         */
+	 }
+};
+
+/*!
+ * @brief This maintains the current state of the External Stereo Input.
+ */
+typedef struct {
+	PMIC_AUDIO_HANDLE handle;	/*!< Handle used to access the
+					   External Stereo Inputs.     */
+	HANDLE_STATE handleState;	/*!< Current handle state.       */
+	PMIC_AUDIO_CALLBACK callback;	/*!< Event notification callback
+					   function pointer.           */
+	PMIC_AUDIO_EVENTS eventMask;	/*!< Event notification mask.    */
+	PMIC_AUDIO_STEREO_IN_GAIN inputGain;	/*!< External Stereo Input
+						   amplifier gain level.       */
+} PMIC_AUDIO_EXT_STEREO_IN_STATE;
+
+/*!
+ * @brief This maintains the current state of the External Stereo Input.
+ *
+ * This variable tracks the current state of the External Stereo Input audio
+ * hardware along with any information that is required by the device driver
+ * to manage the hardware (e.g., callback functions and event notification
+ * masks).
+ *
+ * The initial values represent the reset/power on state of the External
+ * Stereo Input.
+ */
+static PMIC_AUDIO_EXT_STEREO_IN_STATE extStereoIn = {
+	(PMIC_AUDIO_HANDLE) NULL,	/* handle      */
+	HANDLE_FREE,		/* handleState */
+	(PMIC_AUDIO_CALLBACK) NULL,	/* callback    */
+	(PMIC_AUDIO_EVENTS) NULL,	/* eventMask   */
+	STEREO_IN_GAIN_0DB	/* inputGain   */
+};
+
+/*!
+ * @brief This maintains the current state of the callback & Eventmask.
+ */
+typedef struct {
+	PMIC_AUDIO_CALLBACK callback;	/*!< Event notification callback
+					   function pointer.           */
+	PMIC_AUDIO_EVENTS eventMask;	/*!< Event notification mask.    */
+} PMIC_AUDIO_EVENT_STATE;
+
+static PMIC_AUDIO_EVENT_STATE event_state = {
+	(PMIC_AUDIO_CALLBACK) NULL,	/*Callback */
+	(PMIC_AUDIO_EVENTS) NULL,	/* EventMask */
+
+};
+
+/*!
+ * @brief This maintains the current state of the Audio Output Section.
+ */
+typedef struct {
+	PMIC_AUDIO_OUTPUT_PORT outputPort;	/*!< Current audio
+						   output port.     */
+	PMIC_AUDIO_OUTPUT_PGA_GAIN vCodecoutputPGAGain;	/*!< Output PGA gain
+							   level codec      */
+	PMIC_AUDIO_OUTPUT_PGA_GAIN stDacoutputPGAGain;	/*!< Output PGA gain
+							   level stDAC      */
+	PMIC_AUDIO_OUTPUT_PGA_GAIN extStereooutputPGAGain;	/*!< Output PGA gain
+								   level stereo ext */
+	PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceLeftGain;	/*!< Left channel
+							   balance gain
+							   level.           */
+	PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceRightGain;	/*!< Right channel
+								   balance gain
+								   level.           */
+	PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN monoAdderGain;	/*!< Mono adder gain
+								   level.           */
+	PMIC_AUDIO_OUTPUT_CONFIG config;	/*!< Audio output
+						   section config
+						   options.         */
+	PMIC_AUDIO_VCODEC_OUTPUT_PATH vCodecOut;
+
+} PMIC_AUDIO_AUDIO_OUTPUT_STATE;
+
+/*!
+ * @brief This variable maintains the current state of the Audio Output Section.
+ *
+ * This variable tracks the current state of the Audio Output Section.
+ *
+ * The initial values represent the reset/power on state of the Audio
+ * Output Section.
+ */
+static PMIC_AUDIO_AUDIO_OUTPUT_STATE audioOutput = {
+	(PMIC_AUDIO_OUTPUT_PORT) NULL,	/* outputPort       */
+	OUTPGA_GAIN_0DB,	/* outputPGAGain    */
+	OUTPGA_GAIN_0DB,	/* outputPGAGain    */
+	OUTPGA_GAIN_0DB,	/* outputPGAGain    */
+	BAL_GAIN_0DB,		/* balanceLeftGain  */
+	BAL_GAIN_0DB,		/* balanceRightGain */
+	MONOADD_GAIN_0DB,	/* monoAdderGain    */
+	(PMIC_AUDIO_OUTPUT_CONFIG) 0,	/* config           */
+	VCODEC_DIRECT_OUT
+};
+
+/*! The current headset status. */
+static HEADSET_STATUS headsetState = NO_HEADSET;
+
+/* Removed PTT variable */
+/*! Define a 1 ms wait interval that is needed to ensure that certain
+ *  hardware operations are successfully completed.
+ */
+static const unsigned long delay_1ms = (HZ / 1000);
+
+/*!
+ * @brief This spinlock is used to provide mutual exclusion.
+ *
+ * Create a spinlock that can be used to provide mutually exclusive
+ * read/write access to the globally accessible data structures
+ * that were defined above. Mutually exclusive access is required to
+ * ensure that the audio data structures are consistent at all times
+ * when possibly accessed by multiple threads of execution (for example,
+ * while simultaneously handling a user request and an interrupt event).
+ *
+ * We need to use a spinlock whenever we do need to provide mutual
+ * exclusion while possibly executing in a hardware interrupt context.
+ * Spinlocks should be held for the minimum time that is necessary
+ * because hardware interrupts are disabled while a spinlock is held.
+ *
+ */
+
+static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+/*!
+ * @brief This mutex is used to provide mutual exclusion.
+ *
+ * Create a mutex that can be used to provide mutually exclusive
+ * read/write access to the globally accessible data structures
+ * that were defined above. Mutually exclusive access is required to
+ * ensure that the audio data structures are consistent at all times
+ * when possibly accessed by multiple threads of execution.
+ *
+ * Note that we use a mutex instead of the spinlock whenever disabling
+ * interrupts while in the critical section is not required. This helps
+ * to minimize kernel interrupt handling latency.
+ */
+static DECLARE_MUTEX(mutex);
+
+/*!
+ * @brief Global variable to track currently active interrupt events.
+ *
+ * This global variable is used to keep track of all of the currently
+ * active interrupt events for the audio driver. Note that access to this
+ * variable may occur while within an interrupt context and, therefore,
+ * must be guarded by using a spinlock.
+ */
+/* static PMIC_CORE_EVENT eventID = 0; */
+
+/* Prototypes for all static audio driver functions. */
+/*
+static PMIC_STATUS pmic_audio_mic_boost_enable(void);
+static PMIC_STATUS pmic_audio_mic_boost_disable(void);*/
+static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle);
+static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle);
+
+static PMIC_STATUS pmic_audio_deregister(void *callback,
+					 PMIC_AUDIO_EVENTS * const eventMask);
+
+/*************************************************************************
+ * Audio device access APIs.
+ *************************************************************************
+ */
+
+/*!
+ * @name General Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Audio
+ * hardware.
+ */
+/*@{*/
+
+PMIC_STATUS pmic_audio_set_autodetect(int val)
+{
+	PMIC_STATUS status;
+	unsigned int reg_mask = 0, reg_write = 0;
+	reg_mask = SET_BITS(regAUDIO_RX_0, VAUDIOON, 1);
+	status = pmic_write_reg(REG_AUDIO_RX_0, reg_mask, reg_mask);
+	if (status != PMIC_SUCCESS)
+		return status;
+	reg_mask = 0;
+	if (val == 1) {
+		reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) |
+		    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+	} else {
+		reg_write = 0;
+	}
+	reg_mask =
+	    SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | SET_BITS(regAUDIO_RX_0,
+							   HSDETAUTOB, 1);
+	status = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask);
+
+	return status;
+}
+
+/*!
+ * @brief Request exclusive access to the PMIC Audio hardware.
+ *
+ * Attempt to open and gain exclusive access to a key PMIC audio hardware
+ * component (e.g., the Stereo DAC or the Voice CODEC). Depending upon the
+ * type of audio operation that is desired and the nature of the audio data
+ * stream, the Stereo DAC and/or the Voice CODEC will be a required hardware
+ * component and needs to be acquired by calling this function.
+ *
+ * If the open request is successful, then a numeric handle is returned
+ * and this handle must be used in all subsequent function calls to complete
+ * the configuration of either the Stereo DAC or the Voice CODEC and along
+ * with any other associated audio hardware components that will be needed.
+ *
+ * The same handle must also be used in the close call when use of the PMIC
+ * audio hardware is no longer required.
+ *
+ * The open request will fail if the requested audio hardware component has
+ * already been acquired by a previous open call but not yet closed.
+ *
+ * @param  handle          Device handle to be used for subsequent PMIC
+ *                              audio API calls.
+ * @param  device          The required PMIC audio hardware component.
+ *
+ * @retval      PMIC_SUCCESS         If the open request was successful
+ * @retval      PMIC_PARAMETER_ERROR If the handle argument is NULL.
+ * @retval      PMIC_ERROR           If the audio hardware component is
+ *                                   unavailable.
+ */
+PMIC_STATUS pmic_audio_open(PMIC_AUDIO_HANDLE * const handle,
+			    const PMIC_AUDIO_SOURCE device)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	if (handle == (PMIC_AUDIO_HANDLE *) NULL) {
+		/* Do not dereference a NULL pointer. */
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	/* We only need to acquire a mutex here because the interrupt handler
+	 * never modifies the device handle or device handle state. Therefore,
+	 * we don't need to worry about conflicts with the interrupt handler
+	 * or the need to execute in an interrupt context.
+	 *
+	 * But we do need a critical section here to avoid problems in case
+	 * multiple calls to pmic_audio_open() are made since we can only allow
+	 * one of them to succeed.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* Check the current device handle state and acquire the handle if
+	 * it is available.
+	 */
+
+	if ((device == STEREO_DAC) && (stDAC.handleState == HANDLE_FREE)) {
+		stDAC.handle = (PMIC_AUDIO_HANDLE) (&stDAC);
+		stDAC.handleState = HANDLE_IN_USE;
+		*handle = stDAC.handle;
+		rc = PMIC_SUCCESS;
+	} else if ((device == VOICE_CODEC)
+		   && (vCodec.handleState == HANDLE_FREE)) {
+		vCodec.handle = (PMIC_AUDIO_HANDLE) (&vCodec);
+		vCodec.handleState = HANDLE_IN_USE;
+		*handle = vCodec.handle;
+		rc = PMIC_SUCCESS;
+	} else if ((device == EXTERNAL_STEREO_IN) &&
+		   (extStereoIn.handleState == HANDLE_FREE)) {
+		extStereoIn.handle = (PMIC_AUDIO_HANDLE) (&extStereoIn);
+		extStereoIn.handleState = HANDLE_IN_USE;
+		*handle = extStereoIn.handle;
+		rc = PMIC_SUCCESS;
+	} else {
+		*handle = AUDIO_HANDLE_NULL;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Terminate further access to the PMIC audio hardware.
+ *
+ * Terminate further access to the PMIC audio hardware that was previously
+ * acquired by calling pmic_audio_open(). This now allows another thread to
+ * successfully call pmic_audio_open() to gain access.
+ *
+ * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as
+ * any associated audio input/output components that are no longer required.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the close request was successful.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ */
+PMIC_STATUS pmic_audio_close(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* We need a critical section here to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* We can now call pmic_audio_close_handle() to actually do the work. */
+	rc = pmic_audio_close_handle(handle);
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Configure the data bus protocol to be used.
+ *
+ * Provide the parameters needed to properly configure the audio data bus
+ * protocol so that data can be read/written to either the Stereo DAC or
+ * the Voice CODEC.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   busID           Select data bus to be used.
+ * @param   protocol        Select the data bus protocol.
+ * @param   masterSlave     Select the data bus timing mode.
+ * @param   numSlots        Define the number of timeslots (only if in
+ *                              master mode).
+ *
+ * @retval      PMIC_SUCCESS         If the protocol was successful configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or the protocol parameters
+ *                                   are invalid.
+ */
+PMIC_STATUS pmic_audio_set_protocol(const PMIC_AUDIO_HANDLE handle,
+				    const PMIC_AUDIO_DATA_BUS busID,
+				    const PMIC_AUDIO_BUS_PROTOCOL protocol,
+				    const PMIC_AUDIO_BUS_MODE masterSlave,
+				    const PMIC_AUDIO_NUMSLOTS numSlots)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int ST_DAC_MASK = SET_BITS(regST_DAC, STDCSSISEL, 1) |
+	    SET_BITS(regST_DAC, STDCFS, 3) | SET_BITS(regST_DAC, STDCSM, 1);
+
+	unsigned int reg_mask;
+	/*unsigned int VCODEC_MASK = SET_BITS(regAUD_CODEC, CDCSSISEL, 1) |
+	   SET_BITS(regAUD_CODEC, CDCFS, 3) | SET_BITS(regAUD_CODEC, CDCSM, 1); */
+
+	unsigned int SSI_NW_MASK = SET_BITS(regSSI_NETWORK, STDCSLOTS, 1);
+	unsigned int reg_value = 0;
+	unsigned int ssi_nw_value = 0;
+
+	/* Enter a critical section so that we can ensure only one
+	 * state change request is completed at a time.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (handle == (PMIC_AUDIO_HANDLE) NULL) {
+		rc = PMIC_PARAMETER_ERROR;
+	} else {
+		if ((handle == vCodec.handle) &&
+		    (vCodec.handleState == HANDLE_IN_USE)) {
+			if ((stDAC.handleState == HANDLE_IN_USE) &&
+			    (stDAC.busID == busID) && (stDAC.protocol_set)) {
+				pr_debug("The requested bus already in USE\n");
+				rc = PMIC_PARAMETER_ERROR;
+			} else if ((masterSlave == BUS_MASTER_MODE)
+				   && (numSlots != USE_4_TIMESLOTS)) {
+				pr_debug
+				    ("mc13783 supports only 4 slots in Master mode\n");
+				rc = PMIC_NOT_SUPPORTED;
+			} else if ((masterSlave == BUS_SLAVE_MODE)
+				   && (numSlots != USE_4_TIMESLOTS)) {
+				pr_debug
+				    ("Driver currently supports only 4 slots in Slave mode\n");
+				rc = PMIC_NOT_SUPPORTED;
+			} else if (!((protocol == NETWORK_MODE) ||
+				     (protocol == I2S_MODE))) {
+				pr_debug
+				    ("mc13783 Voice codec works only in Network and I2S modes\n");
+				rc = PMIC_NOT_SUPPORTED;
+			} else {
+				pr_debug
+				    ("Proceeding to configure Voice Codec\n");
+				if (busID == AUDIO_DATA_BUS_1) {
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCSSISEL,
+						     0);
+				} else {
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCSSISEL,
+						     1);
+				}
+				reg_mask = SET_BITS(regAUD_CODEC, CDCSSISEL, 1);
+				if (PMIC_SUCCESS !=
+				    pmic_write_reg(REG_AUDIO_CODEC,
+						   reg_value, reg_mask))
+					return PMIC_ERROR;
+
+				if (masterSlave == BUS_MASTER_MODE) {
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCSM, 0);
+				} else {
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCSM, 1);
+				}
+				reg_mask = SET_BITS(regAUD_CODEC, CDCSM, 1);
+				if (PMIC_SUCCESS !=
+				    pmic_write_reg(REG_AUDIO_CODEC,
+						   reg_value, reg_mask))
+					return PMIC_ERROR;
+
+				if (protocol == NETWORK_MODE) {
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCFS, 1);
+				} else {	/* protocol == I2S, other options have been already eliminated */
+					reg_value =
+					    SET_BITS(regAUD_CODEC, CDCFS, 2);
+				}
+				reg_mask = SET_BITS(regAUD_CODEC, CDCFS, 3);
+				if (PMIC_SUCCESS !=
+				    pmic_write_reg(REG_AUDIO_CODEC,
+						   reg_value, reg_mask))
+					return PMIC_ERROR;
+
+				ssi_nw_value =
+				    SET_BITS(regSSI_NETWORK, CDCFSDLY, 1);
+				/*if (pmic_write_reg
+				   (REG_AUDIO_CODEC, reg_value,
+				   VCODEC_MASK) != PMIC_SUCCESS) {
+				   rc = PMIC_ERROR;
+				   } else { */
+				vCodec.busID = busID;
+				vCodec.protocol = protocol;
+				vCodec.masterSlave = masterSlave;
+				vCodec.numSlots = numSlots;
+				vCodec.protocol_set = true;
+				//pmic_write_reg(REG_AUDIO_SSI_NETWORK, ssi_nw_value, ssi_nw_value);
+
+				pr_debug
+				    ("mc13783 Voice codec successfully configured\n");
+				rc = PMIC_SUCCESS;
+				//}
+
+			}
+
+		} else if ((handle == stDAC.handle) &&
+			   (stDAC.handleState == HANDLE_IN_USE)) {
+			if ((vCodec.handleState == HANDLE_IN_USE) &&
+			    (vCodec.busID == busID) && (vCodec.protocol_set)) {
+				pr_debug("The requested bus already in USE\n");
+				rc = PMIC_PARAMETER_ERROR;
+			} else if (((protocol == NORMAL_MSB_JUSTIFIED_MODE) ||
+				    (protocol == I2S_MODE))
+				   && (numSlots != USE_2_TIMESLOTS)) {
+				pr_debug
+				    ("STDAC uses only 2 slots in Normal and I2S modes\n");
+				rc = PMIC_PARAMETER_ERROR;
+			} else if ((protocol == NETWORK_MODE) &&
+				   !((numSlots == USE_2_TIMESLOTS) ||
+				     (numSlots == USE_4_TIMESLOTS) ||
+				     (numSlots == USE_8_TIMESLOTS))) {
+				pr_debug
+				    ("STDAC uses only 2,4 or 8 slots in Network mode\n");
+				rc = PMIC_PARAMETER_ERROR;
+			} else if (protocol == SPD_IF_MODE) {
+				pr_debug
+				    ("STDAC driver currently does not support SPD IF mode\n");
+				rc = PMIC_NOT_SUPPORTED;
+			} else {
+				pr_debug
+				    ("Proceeding to configure Stereo DAC\n");
+				if (busID == AUDIO_DATA_BUS_1) {
+					reg_value =
+					    SET_BITS(regST_DAC, STDCSSISEL, 0);
+				} else {
+					reg_value =
+					    SET_BITS(regST_DAC, STDCSSISEL, 1);
+				}
+				if (masterSlave == BUS_MASTER_MODE) {
+					reg_value |=
+					    SET_BITS(regST_DAC, STDCSM, 0);
+				} else {
+					reg_value |=
+					    SET_BITS(regST_DAC, STDCSM, 1);
+				}
+				if (protocol == NETWORK_MODE) {
+					reg_value |=
+					    SET_BITS(regST_DAC, STDCFS, 1);
+				} else if (protocol ==
+					   NORMAL_MSB_JUSTIFIED_MODE) {
+					reg_value |=
+					    SET_BITS(regST_DAC, STDCFS, 0);
+				} else {	/* I2S mode as the other option has already been eliminated */
+					reg_value |=
+					    SET_BITS(regST_DAC, STDCFS, 2);
+				}
+
+				if (pmic_write_reg
+				    (REG_AUDIO_STEREO_DAC,
+				     reg_value, ST_DAC_MASK) != PMIC_SUCCESS) {
+					rc = PMIC_ERROR;
+				} else {
+					if (numSlots == USE_2_TIMESLOTS) {
+						reg_value =
+						    SET_BITS(regSSI_NETWORK,
+							     STDCSLOTS, 3);
+					} else if (numSlots == USE_4_TIMESLOTS) {
+						reg_value =
+						    SET_BITS(regSSI_NETWORK,
+							     STDCSLOTS, 2);
+					} else {	/* Use 8 timeslots - L , R and 6 other */
+						reg_value =
+						    SET_BITS(regSSI_NETWORK,
+							     STDCSLOTS, 1);
+					}
+					if (pmic_write_reg
+					    (REG_AUDIO_SSI_NETWORK,
+					     reg_value,
+					     SSI_NW_MASK) != PMIC_SUCCESS) {
+						rc = PMIC_ERROR;
+					} else {
+						stDAC.busID = busID;
+						stDAC.protocol = protocol;
+						stDAC.protocol_set = true;
+						stDAC.masterSlave = masterSlave;
+						stDAC.numSlots = numSlots;
+						pr_debug
+						    ("mc13783 Stereo DAC successfully configured\n");
+						rc = PMIC_SUCCESS;
+					}
+				}
+
+			}
+		} else {
+			rc = PMIC_PARAMETER_ERROR;
+			/* Handle  can only be Voice Codec or Stereo DAC */
+			pr_debug("Handles only STDAC and VCODEC\n");
+		}
+
+	}
+	/* Exit critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Retrieve the current data bus protocol configuration.
+ *
+ * Retrieve the parameters that define the current audio data bus protocol.
+ *
+ * @param  handle          Device handle from pmic_audio_open() call.
+ * @param  busID           The data bus being used.
+ * @param  protocol        The data bus protocol being used.
+ * @param  masterSlave     The data bus timing mode being used.
+ * @param  numSlots        The number of timeslots being used (if in
+ *                              master mode).
+ *
+ * @retval      PMIC_SUCCESS         If the protocol was successful retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ */
+PMIC_STATUS pmic_audio_get_protocol(const PMIC_AUDIO_HANDLE handle,
+				    PMIC_AUDIO_DATA_BUS * const busID,
+				    PMIC_AUDIO_BUS_PROTOCOL * const protocol,
+				    PMIC_AUDIO_BUS_MODE * const masterSlave,
+				    PMIC_AUDIO_NUMSLOTS * const numSlots)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	if ((busID != (PMIC_AUDIO_DATA_BUS *) NULL) &&
+	    (protocol != (PMIC_AUDIO_BUS_PROTOCOL *) NULL) &&
+	    (masterSlave != (PMIC_AUDIO_BUS_MODE *) NULL) &&
+	    (numSlots != (PMIC_AUDIO_NUMSLOTS *) NULL)) {
+		/* Enter a critical section so that we return a consistent state. */
+		if (down_interruptible(&mutex))
+			return PMIC_SYSTEM_ERROR_EINTR;
+
+		if ((handle == stDAC.handle) &&
+		    (stDAC.handleState == HANDLE_IN_USE)) {
+			*busID = stDAC.busID;
+			*protocol = stDAC.protocol;
+			*masterSlave = stDAC.masterSlave;
+			*numSlots = stDAC.numSlots;
+			rc = PMIC_SUCCESS;
+		} else if ((handle == vCodec.handle) &&
+			   (vCodec.handleState == HANDLE_IN_USE)) {
+			*busID = vCodec.busID;
+			*protocol = vCodec.protocol;
+			*masterSlave = vCodec.masterSlave;
+			*numSlots = vCodec.numSlots;
+			rc = PMIC_SUCCESS;
+		}
+
+		/* Exit critical section. */
+		up(&mutex);
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Enable the Stereo DAC or the Voice CODEC.
+ *
+ * Explicitly enable the Stereo DAC or the Voice CODEC to begin audio
+ * playback or recording as required. This should only be done after
+ * successfully configuring all of the associated audio components (e.g.,
+ * microphones, amplifiers, etc.).
+ *
+ * Note that the timed delays used in this function are necessary to
+ * ensure reliable operation of the Voice CODEC and Stereo DAC. The
+ * Stereo DAC seems to be particularly sensitive and it has been observed
+ * to fail to generate the required master mode clock signals if it is
+ * not allowed enough time to initialize properly.
+ *
+ * @param      handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the device was successful enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ * @retval      PMIC_ERROR           If the device could not be enabled.
+ */
+PMIC_STATUS pmic_audio_enable(const PMIC_AUDIO_HANDLE handle)
+{
+	const unsigned int AUDIO_BIAS_ENABLE = SET_BITS(regAUDIO_RX_0,
+							VAUDIOON, 1);
+	const unsigned int STDAC_ENABLE = SET_BITS(regST_DAC, STDCEN, 1);
+	const unsigned int VCODEC_ENABLE = SET_BITS(regAUD_CODEC, CDCEN, 1);
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE,
+			       AUDIO_BIAS_ENABLE);
+		reg_mask =
+		    SET_BITS(regAUDIO_RX_0, HSDETEN,
+			     1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+		reg_write =
+		    SET_BITS(regAUDIO_RX_0, HSDETEN,
+			     1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+		rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask);
+		if (rc == PMIC_SUCCESS)
+			pr_debug("pmic_audio_enable\n");
+		/* We can enable the Stereo DAC. */
+		rc = pmic_write_reg(REG_AUDIO_STEREO_DAC,
+				    STDAC_ENABLE, STDAC_ENABLE);
+		/*pmic_read_reg(REG_AUDIO_STEREO_DAC, &reg_value); */
+		if (rc != PMIC_SUCCESS) {
+			pr_debug("Failed to enable the Stereo DAC\n");
+			rc = PMIC_ERROR;
+		}
+	} else if ((handle == vCodec.handle)
+		   && (vCodec.handleState == HANDLE_IN_USE)) {
+		/* Must first set the audio bias bit to power up the audio circuits. */
+		pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE,
+			       AUDIO_BIAS_ENABLE);
+		reg_mask = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) |
+		    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+		reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) |
+		    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+		rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask);
+
+		/* Then we can enable the Voice CODEC. */
+		rc = pmic_write_reg(REG_AUDIO_CODEC, VCODEC_ENABLE,
+				    VCODEC_ENABLE);
+
+		/* pmic_read_reg(REG_AUDIO_CODEC, &reg_value); */
+		if (rc != PMIC_SUCCESS) {
+			pr_debug("Failed to enable the Voice codec\n");
+			rc = PMIC_ERROR;
+		}
+	}
+	/* Exit critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Disable the Stereo DAC or the Voice CODEC.
+ *
+ * Explicitly disable the Stereo DAC or the Voice CODEC to end audio
+ * playback or recording as required.
+ *
+ * @param   	handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the device was successful disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ * @retval      PMIC_ERROR           If the device could not be disabled.
+ */
+PMIC_STATUS pmic_audio_disable(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int STDAC_DISABLE = SET_BITS(regST_DAC, STDCEN, 1);
+	const unsigned int VCODEC_DISABLE = SET_BITS(regAUD_CODEC, CDCEN, 1);
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, 0, STDAC_DISABLE);
+	} else if ((handle == vCodec.handle)
+		   && (vCodec.handleState == HANDLE_IN_USE)) {
+		rc = pmic_write_reg(REG_AUDIO_CODEC, 0, VCODEC_DISABLE);
+	}
+	if (rc == PMIC_SUCCESS) {
+		pr_debug("Disabled successfully\n");
+	}
+	/* Exit critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Reset the selected audio hardware control registers to their
+ *        power on state.
+ *
+ * This resets all of the audio hardware control registers currently
+ * associated with the device handle back to their power on states. For
+ * example, if the handle is associated with the Stereo DAC and a
+ * specific output port and output amplifiers, then this function will
+ * reset all of those components to their initial power on state.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the reset operation was successful.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ * @retval      PMIC_ERROR           If the reset was unsuccessful.
+ */
+PMIC_STATUS pmic_audio_reset(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	rc = pmic_audio_reset_device(handle);
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Reset all audio hardware control registers to their power on state.
+ *
+ * This resets all of the audio hardware control registers back to their
+ * power on states. Use this function with care since it also invalidates
+ * (i.e., automatically closes) all currently opened device handles.
+ *
+ * @retval      PMIC_SUCCESS         If the reset operation was successful.
+ * @retval      PMIC_ERROR           If the reset was unsuccessful.
+ */
+PMIC_STATUS pmic_audio_reset_all(void)
+{
+	PMIC_STATUS rc = PMIC_SUCCESS;
+	unsigned int audio_ssi_reset = 0;
+	unsigned int audio_rx1_reset = 0;
+	/* We need a critical section here to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* First close all opened device handles, also deregisters callbacks. */
+	pmic_audio_close_handle(stDAC.handle);
+	pmic_audio_close_handle(vCodec.handle);
+	pmic_audio_close_handle(extStereoIn.handle);
+
+	if (pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1,
+			   PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		audio_rx1_reset = 1;
+	}
+	if (pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK,
+			   PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		audio_ssi_reset = 1;
+	}
+	if (pmic_write_reg
+	    (REG_AUDIO_STEREO_DAC, RESET_ST_DAC,
+	     PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		/* Also reset the driver state information to match. Note that we
+		 * keep the device handle and event callback settings unchanged
+		 * since these don't affect the actual hardware and we rely on
+		 * the user to explicitly close the handle or deregister callbacks
+		 */
+		if (audio_ssi_reset) {
+			/* better to check if SSI is also reset as some fields are represennted in SSI reg */
+			stDAC.busID = AUDIO_DATA_BUS_1;
+			stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE;
+			stDAC.masterSlave = BUS_MASTER_MODE;
+			stDAC.protocol_set = false;
+			stDAC.numSlots = USE_2_TIMESLOTS;
+			stDAC.clockIn = CLOCK_IN_CLIA;
+			stDAC.samplingRate = STDAC_RATE_44_1_KHZ;
+			stDAC.clockFreq = STDAC_CLI_13MHZ;
+			stDAC.invert = NO_INVERT;
+			stDAC.timeslot = USE_TS0_TS1;
+			stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0;
+		}
+	}
+
+	if (pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC,
+			   PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		/* Also reset the driver state information to match. Note that we
+		 * keep the device handle and event callback settings unchanged
+		 * since these don't affect the actual hardware and we rely on
+		 * the user to explicitly close the handle or deregister callbacks
+		 */
+		if (audio_ssi_reset) {
+			vCodec.busID = AUDIO_DATA_BUS_2;
+			vCodec.protocol = NETWORK_MODE;
+			vCodec.masterSlave = BUS_SLAVE_MODE;
+			vCodec.protocol_set = false;
+			vCodec.numSlots = USE_4_TIMESLOTS;
+			vCodec.clockIn = CLOCK_IN_CLIB;
+			vCodec.samplingRate = VCODEC_RATE_8_KHZ;
+			vCodec.clockFreq = VCODEC_CLI_13MHZ;
+			vCodec.invert = NO_INVERT;
+			vCodec.timeslot = USE_TS0;
+			vCodec.config =
+			    INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER;
+		}
+	}
+
+	if (pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0,
+			   PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		/* Also reset the driver state information to match. */
+		audioOutput.outputPort = (PMIC_AUDIO_OUTPUT_PORT) NULL;
+		audioOutput.vCodecoutputPGAGain = OUTPGA_GAIN_0DB;
+		audioOutput.stDacoutputPGAGain = OUTPGA_GAIN_0DB;
+		audioOutput.extStereooutputPGAGain = OUTPGA_GAIN_0DB;
+		audioOutput.balanceLeftGain = BAL_GAIN_0DB;
+		audioOutput.balanceRightGain = BAL_GAIN_0DB;
+		audioOutput.monoAdderGain = MONOADD_GAIN_0DB;
+		audioOutput.config = (PMIC_AUDIO_OUTPUT_CONFIG) 0;
+		audioOutput.vCodecOut = VCODEC_DIRECT_OUT;
+	}
+
+	if (pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX,
+			   PMIC_ALL_BITS) != PMIC_SUCCESS) {
+		rc = PMIC_ERROR;
+	} else {
+		/* Also reset the driver state information to match. Note that we
+		 * reset the vCodec fields since all of the input/recording
+		 * devices are only connected to the Voice CODEC and are managed
+		 * as part of the Voice CODEC state.
+		 */
+		if (audio_rx1_reset) {
+			vCodec.leftChannelMic.mic = NO_MIC;
+			vCodec.leftChannelMic.micOnOff = MICROPHONE_OFF;
+			vCodec.leftChannelMic.ampMode = CURRENT_TO_VOLTAGE;
+			vCodec.leftChannelMic.gain = MIC_GAIN_0DB;
+			vCodec.rightChannelMic.mic = NO_MIC;
+			vCodec.rightChannelMic.micOnOff = MICROPHONE_OFF;
+			vCodec.rightChannelMic.ampMode = AMP_OFF;
+			vCodec.rightChannelMic.gain = MIC_GAIN_0DB;
+		}
+	}
+	/* Finally, also reset any global state variables. */
+	headsetState = NO_HEADSET;
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Set the Audio callback function.
+ *
+ * Register a callback function that will be used to signal PMIC audio
+ * events. For example, the OSS audio driver should register a callback
+ * function in order to be notified of headset connect/disconnect events.
+ *
+ * @param   func            A pointer to the callback function.
+ * @param   eventMask       A mask selecting events to be notified.
+ * @param   hs_state        To know the headset state.
+ *
+ *
+ *
+ * @retval      PMIC_SUCCESS         If the callback was successfully
+ *                                   registered.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid.
+ */
+PMIC_STATUS pmic_audio_set_callback(void *func,
+				    const PMIC_AUDIO_EVENTS eventMask,
+				    PMIC_HS_STATE * hs_state)
+{
+	unsigned long flags;
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	pmic_event_callback_t eventNotify;
+
+	/* We need to start a critical section here to ensure a consistent state
+	 * in case simultaneous calls to pmic_audio_set_callback() are made. In
+	 * that case, we must serialize the calls to ensure that the "callback"
+	 * and "eventMask" state variables are always consistent.
+	 *
+	 * Note that we don't actually need to acquire the spinlock until later
+	 * when we are finally ready to update the "callback" and "eventMask"
+	 * state variables which are shared with the interrupt handler.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	rc = PMIC_ERROR;
+	/* Register for PMIC events from the core protocol driver. */
+	if (eventMask & MICROPHONE_DETECTED) {
+		/* We need to register for the A1 amplifier interrupt. */
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_MC2BI);
+		rc = pmic_event_subscribe(EVENT_MC2BI, eventNotify);
+
+		if (rc != PMIC_SUCCESS) {
+			pr_debug
+			    ("%s: pmic_event_subscribe() for EVENT_HSDETI "
+			     "failed\n", __FILE__);
+			goto End;
+		}
+	}
+
+	if (eventMask & HEADSET_DETECTED) {
+		/* We need to register for the A1 amplifier interrupt. */
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_HSDETI);
+		rc = pmic_event_subscribe(EVENT_HSDETI, eventNotify);
+
+		if (rc != PMIC_SUCCESS) {
+			pr_debug
+			    ("%s: pmic_event_subscribe() for EVENT_HSDETI "
+			     "failed\n", __FILE__);
+			goto Cleanup_HDT;
+		}
+
+	}
+	if (eventMask & HEADSET_STEREO) {
+		/* We need to register for the A1 amplifier interrupt. */
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_HSLI);
+		rc = pmic_event_subscribe(EVENT_HSLI, eventNotify);
+
+		if (rc != PMIC_SUCCESS) {
+			pr_debug
+			    ("%s: pmic_event_subscribe() for EVENT_HSLI "
+			     "failed\n", __FILE__);
+			goto Cleanup_HST;
+		}
+	}
+	if (eventMask & HEADSET_THERMAL_SHUTDOWN) {
+		/* We need to register for the A1 amplifier interrupt. */
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_ALSPTHI);
+		rc = pmic_event_subscribe(EVENT_ALSPTHI, eventNotify);
+
+		if (rc != PMIC_SUCCESS) {
+			pr_debug
+			    ("%s: pmic_event_subscribe() for EVENT_ALSPTHI "
+			     "failed\n", __FILE__);
+			goto Cleanup_TSD;
+		}
+		pr_debug("Registered for EVENT_ALSPTHI\n");
+	}
+	if (eventMask & HEADSET_SHORT_CIRCUIT) {
+		/* We need to register for the A1 amplifier interrupt. */
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI);
+		rc = pmic_event_subscribe(EVENT_AHSSHORTI, eventNotify);
+
+		if (rc != PMIC_SUCCESS) {
+			pr_debug
+			    ("%s: pmic_event_subscribe() for EVENT_AHSSHORTI "
+			     "failed\n", __FILE__);
+			goto Cleanup_HShort;
+		}
+		pr_debug("Registered for EVENT_AHSSHORTI\n");
+	}
+
+	/* We also need the spinlock here to avoid possible problems
+	 * with the interrupt handler  when we update the
+	 * "callback" and "eventMask" state variables.
+	 */
+	spin_lock_irqsave(&lock, flags);
+
+	/* Successfully registered for all events. */
+	event_state.callback = func;
+	event_state.eventMask = eventMask;
+
+	/* The spinlock is no longer needed now that we've finished
+	 * updating the "callback" and "eventMask" state variables.
+	 */
+	spin_unlock_irqrestore(&lock, flags);
+
+	goto End;
+
+	/* This section unregisters any already registered events if we should
+	 * encounter an error partway through the registration process. Note
+	 * that we don't check the return status here since it is already set
+	 * to PMIC_ERROR before we get here.
+	 */
+      Cleanup_HShort:
+
+	if (eventMask & HEADSET_SHORT_CIRCUIT) {
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI);
+		pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify);
+	}
+
+      Cleanup_TSD:
+
+	if (eventMask & HEADSET_THERMAL_SHUTDOWN) {
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_ALSPTHI);
+		pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify);
+	}
+
+      Cleanup_HST:
+
+	if (eventMask & HEADSET_STEREO) {
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_HSLI);
+		pmic_event_unsubscribe(EVENT_HSLI, eventNotify);
+	}
+
+      Cleanup_HDT:
+
+	if (eventMask & HEADSET_DETECTED) {
+		eventNotify.func = func;
+		eventNotify.param = (void *)(CORE_EVENT_HSDETI);
+		pmic_event_unsubscribe(EVENT_HSDETI, eventNotify);
+	}
+
+      End:
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Deregisters the existing audio callback function.
+ *
+ * Deregister the callback function that was previously registered by calling
+ * pmic_audio_set_callback().
+ *
+ *
+ * @retval      PMIC_SUCCESS         If the callback was successfully
+ *                                   deregistered.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ */
+PMIC_STATUS pmic_audio_clear_callback(void)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* We need a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (event_state.callback != (PMIC_AUDIO_CALLBACK) NULL) {
+		rc = pmic_audio_deregister(&(event_state.callback),
+					   &(event_state.eventMask));
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Get the current audio callback function settings.
+ *
+ * Get the current callback function and event mask.
+ *
+ * @param   func            The current callback function.
+ * @param   eventMask       The current event selection mask.
+ *
+ * @retval      PMIC_SUCCESS         If the callback information was
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ */
+PMIC_STATUS pmic_audio_get_callback(PMIC_AUDIO_CALLBACK * const func,
+				    PMIC_AUDIO_EVENTS * const eventMask)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* We only need to acquire the mutex here because we will not be updating
+	 * anything that may affect the interrupt handler. We just need to ensure
+	 * that the callback fields are not changed while we are in the critical
+	 * section by calling either pmic_audio_set_callback() or
+	 * pmic_audio_clear_callback().
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((func != (PMIC_AUDIO_CALLBACK *) NULL) &&
+	    (eventMask != (PMIC_AUDIO_EVENTS *) NULL)) {
+
+		*func = event_state.callback;
+		*eventMask = event_state.eventMask;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Enable the anti-pop circuitry to avoid extra noise when inserting
+ *        or removing a external device (e.g., a headset).
+ *
+ * Enable the use of the built-in anti-pop circuitry to prevent noise from
+ * being generated when an external audio device is inserted or removed
+ * from an audio plug. A slow ramp speed may be needed to avoid extra noise.
+ *
+ * @param       rampSpeed       The desired anti-pop circuitry ramp speed.
+ *
+ * @retval      PMIC_SUCCESS         If the anti-pop circuitry was successfully
+ *                                   enabled.
+ * @retval      PMIC_ERROR           If the anti-pop circuitry could not be
+ *                                   enabled.
+ */
+PMIC_STATUS pmic_audio_antipop_enable(const PMIC_AUDIO_ANTI_POP_RAMP_SPEED
+				      rampSpeed)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASEN, 1) |
+	    SET_BITS(regAUDIO_RX_0, BIASSPEED, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	/*
+	 * Antipop is enabled by enabling the BIAS (BIASEN) and setting the
+	 * BIASSPEED .
+	 * BIASEN is just to make sure that BIAS is enabled
+	 */
+	reg_value = SET_BITS(regAUDIO_RX_0, BIASEN, 1)
+	    | SET_BITS(regAUDIO_RX_0, BIASSPEED, 0) | SET_BITS(regAUDIO_RX_0,
+							       HSLDETEN, 1);
+	rc = pmic_write_reg(REG_AUDIO_RX_0, reg_value, reg_mask);
+	return rc;
+}
+
+/*!
+ * @brief Disable the anti-pop circuitry.
+ *
+ * Disable the use of the built-in anti-pop circuitry to prevent noise from
+ * being generated when an external audio device is inserted or removed
+ * from an audio plug.
+ *
+ * @retval      PMIC_SUCCESS         If the anti-pop circuitry was successfully
+ *                                   disabled.
+ * @retval      PMIC_ERROR           If the anti-pop circuitry could not be
+ *                                   disabled.
+ */
+PMIC_STATUS pmic_audio_antipop_disable(void)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) |
+	    SET_BITS(regAUDIO_RX_0, BIASEN, 1);
+	const unsigned int reg_write = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) |
+	    SET_BITS(regAUDIO_RX_0, BIASEN, 0);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	/*
+	 * Antipop is disabled by setting BIASSPEED  = 0. BIASEN bit remains set
+	 * as only antipop needs to be disabled
+	 */
+	rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask);
+
+	return rc;
+}
+
+/*!
+ * @brief Performs a reset of the Voice CODEC/Stereo DAC digital filter.
+ *
+ * The digital filter should be reset whenever the clock or sampling rate
+ * configuration has been changed.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the digital filter was successfully
+ *                                   reset.
+ * @retval      PMIC_ERROR           If the digital filter could not be reset.
+ */
+PMIC_STATUS pmic_audio_digital_filter_reset(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regST_DAC, STDCRESET, 1);
+		if (pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_mask,
+				   reg_mask) != PMIC_SUCCESS) {
+			rc = PMIC_ERROR;
+		} else {
+			pr_debug("STDAC filter reset\n");
+		}
+
+	} else if ((handle == vCodec.handle) &&
+		   (vCodec.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regAUD_CODEC, CDCRESET, 1);
+		if (pmic_write_reg(REG_AUDIO_CODEC, reg_mask,
+				   reg_mask) != PMIC_SUCCESS) {
+			rc = PMIC_ERROR;
+		} else {
+			pr_debug("CODEC filter reset\n");
+		}
+	}
+	return rc;
+}
+
+/*!
+ * @brief Get the most recent PTT button voltage reading.
+ *
+ * This feature is not supported by mc13783
+ * @param       level                PTT button level.
+ *
+ * @retval      PMIC_SUCCESS         If the most recent PTT button voltage was
+ *                                   returned.
+ * @retval      PMIC_PARAMETER_ERROR If a NULL pointer argument was given.
+ */
+PMIC_STATUS pmic_audio_get_ptt_button_level(unsigned int *const level)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+}
+
+#ifdef DEBUG_AUDIO
+
+/*!
+ * @brief Provide a hexadecimal dump of all PMIC audio registers (DEBUG only)
+ *
+ * This function is intended strictly for debugging purposes only and will
+ * print the current values of the following PMIC registers:
+ *
+ * - AUD_CODEC
+ * - ST_DAC
+ * - AUDIO_RX_0
+ * - AUDIO_RX_1
+ * - AUDIO_TX
+ * - AUDIO_SSI_NW
+ *
+ * The register fields will not be decoded.
+ *
+ * Note that we don't dump any of the arbitration bits because we cannot
+ * access the true arbitration bit settings when reading the registers
+ * from the secondary SPI bus.
+ *
+ * Also note that we must not call this function with interrupts disabled,
+ * for example, while holding a spinlock, because calls to pmic_read_reg()
+ * eventually end up in the SPI driver which will want to perform a
+ * schedule() operation. If schedule() is called with interrupts disabled,
+ * then you will see messages like the following:
+ *
+ * BUG: scheduling while atomic: ...
+ *
+ */
+void pmic_audio_dump_registers(void)
+{
+	unsigned int reg_value = 0;
+
+	/* Dump the AUD_CODEC (Voice CODEC) register. */
+	if (pmic_read_reg(REG_AUDIO_CODEC, &reg_value, REG_FULLMASK)
+	    == PMIC_SUCCESS) {
+		pr_debug("Audio Codec = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read audio codec\n");
+	}
+
+	/* Dump the ST DAC (Stereo DAC) register. */
+	if (pmic_read_reg
+	    (REG_AUDIO_STEREO_DAC, &reg_value, REG_FULLMASK) == PMIC_SUCCESS) {
+		pr_debug("Stereo DAC = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read Stereo DAC\n");
+	}
+
+	/* Dump the SSI NW register. */
+	if (pmic_read_reg
+	    (REG_AUDIO_SSI_NETWORK, &reg_value, REG_FULLMASK) == PMIC_SUCCESS) {
+		pr_debug("SSI Network = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read SSI network\n");
+	}
+
+	/* Dump the Audio RX 0 register. */
+	if (pmic_read_reg(REG_AUDIO_RX_0, &reg_value, REG_FULLMASK)
+	    == PMIC_SUCCESS) {
+		pr_debug("Audio RX 0 = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read audio RX 0\n");
+	}
+
+	/* Dump the Audio RX 1 register. */
+	if (pmic_read_reg(REG_AUDIO_RX_1, &reg_value, REG_FULLMASK)
+	    == PMIC_SUCCESS) {
+		pr_debug("Audio RX 1 = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read audio RX 1\n");
+	}
+	/* Dump the Audio TX register. */
+	if (pmic_read_reg(REG_AUDIO_TX, &reg_value, REG_FULLMASK) ==
+	    PMIC_SUCCESS) {
+		pr_debug("Audio Tx = 0x%x\n", reg_value);
+	} else {
+		pr_debug("Failed to read audio TX\n");
+	}
+
+}
+
+#endif				/* DEBUG_AUDIO */
+
+/*@}*/
+
+/*************************************************************************
+ * General Voice CODEC configuration.
+ *************************************************************************
+ */
+
+/*!
+ * @name General Voice CODEC Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Voice
+ * CODEC hardware.
+ */
+/*@{*/
+
+/*!
+ * @brief Set the Voice CODEC clock source and operating characteristics.
+ *
+ * Define the Voice CODEC clock source and operating characteristics. This
+ * must be done before the Voice CODEC is enabled.
+ *
+ *
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       clockIn         Select the clock signal source.
+ * @param       clockFreq       Select the clock signal frequency.
+ * @param       samplingRate    Select the audio data sampling rate.
+ * @param       invert          Enable inversion of the frame sync and/or
+ *                              bit clock inputs.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC clock settings were
+ *                                   successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or clock configuration was
+ *                                   invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC clock configuration
+ *                                   could not be set.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_clock(const PMIC_AUDIO_HANDLE handle,
+					const PMIC_AUDIO_CLOCK_IN_SOURCE
+					clockIn,
+					const PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ
+					clockFreq,
+					const PMIC_AUDIO_VCODEC_SAMPLING_RATE
+					samplingRate,
+					const PMIC_AUDIO_CLOCK_INVERT invert)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* Validate all of the calling parameters. */
+	if (handle == (PMIC_AUDIO_HANDLE) NULL) {
+		rc = PMIC_PARAMETER_ERROR;
+	} else if ((handle == vCodec.handle) &&
+		   (vCodec.handleState == HANDLE_IN_USE)) {
+		if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if (!((clockFreq >= VCODEC_CLI_13MHZ)
+			     && (clockFreq <= VCODEC_CLI_33_6MHZ))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if ((samplingRate != VCODEC_RATE_8_KHZ)
+			   && (samplingRate != VCODEC_RATE_16_KHZ)) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if (!((invert >= NO_INVERT)
+			     && (invert <= INVERT_FRAMESYNC))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else {
+			/*reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7) |
+			   SET_BITS(regAUD_CODEC, CDCCLKSEL, 1) |
+			   SET_BITS(regAUD_CODEC, CDCFS8K16K, 1) |
+			   SET_BITS(regAUD_CODEC, CDCBCLINV, 1) |
+			   SET_BITS(regAUD_CODEC, CDCFSINV, 1); */
+			if (clockIn == CLOCK_IN_CLIA) {
+				reg_value =
+				    SET_BITS(regAUD_CODEC, CDCCLKSEL, 0);
+			} else {
+				reg_value =
+				    SET_BITS(regAUD_CODEC, CDCCLKSEL, 1);
+			}
+			reg_mask = SET_BITS(regAUD_CODEC, CDCCLKSEL, 1);
+			if (PMIC_SUCCESS !=
+			    pmic_write_reg(REG_AUDIO_CODEC,
+					   reg_value, reg_mask))
+				return PMIC_ERROR;
+
+			reg_value = 0;
+			if (clockFreq == VCODEC_CLI_13MHZ) {
+				reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 0);
+			} else if (clockFreq == VCODEC_CLI_15_36MHZ) {
+				reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 1);
+			} else if (clockFreq == VCODEC_CLI_16_8MHZ) {
+				reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 2);
+			} else if (clockFreq == VCODEC_CLI_26MHZ) {
+				reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 4);
+			} else {
+				reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 7);
+			}
+			reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7);
+			if (PMIC_SUCCESS !=
+			    pmic_write_reg(REG_AUDIO_CODEC,
+					   reg_value, reg_mask))
+				return PMIC_ERROR;
+
+			reg_value = 0;
+			reg_mask = 0;
+
+			if (samplingRate == VCODEC_RATE_8_KHZ) {
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCFS8K16K, 0);
+			} else {
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCFS8K16K, 1);
+			}
+			reg_mask = SET_BITS(regAUD_CODEC, CDCFS8K16K, 1);
+			if (PMIC_SUCCESS !=
+			    pmic_write_reg(REG_AUDIO_CODEC,
+					   reg_value, reg_mask))
+				return PMIC_ERROR;
+			reg_value = 0;
+			reg_mask =
+			    SET_BITS(regAUD_CODEC, CDCBCLINV,
+				     1) | SET_BITS(regAUD_CODEC, CDCFSINV, 1);
+
+			if (invert & INVERT_BITCLOCK) {
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCBCLINV, 1);
+			}
+			if (invert & INVERT_FRAMESYNC) {
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCFSINV, 1);
+			}
+			if (invert & NO_INVERT) {
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCBCLINV, 0);
+				reg_value |=
+				    SET_BITS(regAUD_CODEC, CDCFSINV, 0);
+			}
+			if (pmic_write_reg
+			    (REG_AUDIO_CODEC, reg_value,
+			     reg_mask) != PMIC_SUCCESS) {
+				rc = PMIC_ERROR;
+			} else {
+				pr_debug("CODEC clock set\n");
+				vCodec.clockIn = clockIn;
+				vCodec.clockFreq = clockFreq;
+				vCodec.samplingRate = samplingRate;
+				vCodec.invert = invert;
+			}
+
+		}
+
+	} else {
+		rc = PMIC_PARAMETER_ERROR;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the Voice CODEC clock source and operating characteristics.
+ *
+ * Get the current Voice CODEC clock source and operating characteristics.
+ *
+ * @param  	handle          Device handle from pmic_audio_open() call.
+ * @param  	clockIn         The clock signal source.
+ * @param  	clockFreq       The clock signal frequency.
+ * @param  	samplingRate    The audio data sampling rate.
+ * @param       invert          Inversion of the frame sync and/or
+ *                              bit clock inputs is enabled/disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC clock settings were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC clock configuration
+ *                                   could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_clock(const PMIC_AUDIO_HANDLE handle,
+					PMIC_AUDIO_CLOCK_IN_SOURCE *
+					const clockIn,
+					PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ *
+					const clockFreq,
+					PMIC_AUDIO_VCODEC_SAMPLING_RATE *
+					const samplingRate,
+					PMIC_AUDIO_CLOCK_INVERT * const invert)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure that we return a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) &&
+	    (clockFreq != (PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ *) NULL) &&
+	    (samplingRate != (PMIC_AUDIO_VCODEC_SAMPLING_RATE *) NULL) &&
+	    (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) {
+		*clockIn = vCodec.clockIn;
+		*clockFreq = vCodec.clockFreq;
+		*samplingRate = vCodec.samplingRate;
+		*invert = vCodec.invert;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the Voice CODEC primary audio channel timeslot.
+ *
+ * Set the Voice CODEC primary audio channel timeslot. This function must be
+ * used if the default timeslot for the primary audio channel is to be changed.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       timeslot        Select the primary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC primary audio channel
+ *                                   timeslot was successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or audio channel timeslot
+ *                                   was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC primary audio channel
+ *                                   timeslot could not be set.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle,
+						const PMIC_AUDIO_VCODEC_TIMESLOT
+						timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	const unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, 3);
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    ((timeslot == USE_TS0) || (timeslot == USE_TS1) ||
+	     (timeslot == USE_TS2) || (timeslot == USE_TS3))) {
+		reg_write = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, timeslot);
+
+		rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			vCodec.timeslot = timeslot;
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current Voice CODEC primary audio channel timeslot.
+ *
+ * Get the current Voice CODEC primary audio channel timeslot.
+ *
+ * @param	handle          Device handle from pmic_audio_open() call.
+ * @param       timeslot        The primary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC primary audio channel
+ *                                   timeslot was successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC primary audio channel
+ *                                   timeslot could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle,
+						PMIC_AUDIO_VCODEC_TIMESLOT *
+						const timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) {
+		*timeslot = vCodec.timeslot;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the Voice CODEC secondary recording audio channel timeslot.
+ *
+ * Set the Voice CODEC secondary audio channel timeslot. This function must be
+ * used if the default timeslot for the secondary audio channel is to be
+ * changed. The secondary audio channel timeslot is used to transmit the audio
+ * data that was recorded by the Voice CODEC from the secondary audio input
+ * channel.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   timeslot        Select the secondary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC secondary audio channel
+ *                                   timeslot was successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or audio channel timeslot
+ *                                   was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC secondary audio channel
+ *                                   timeslot could not be set.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_secondary_txslot(const PMIC_AUDIO_HANDLE
+						   handle,
+						   const
+						   PMIC_AUDIO_VCODEC_TIMESLOT
+						   timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, 3);
+	unsigned int reg_write = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		/* How to handle primary slot and secondary slot being the same */
+		if ((timeslot >= USE_TS0) && (timeslot <= USE_TS3)
+		    && (timeslot != vCodec.timeslot)) {
+			reg_write =
+			    SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, timeslot);
+
+			rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				vCodec.secondaryTXtimeslot = timeslot;
+			}
+		}
+
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the Voice CODEC secondary recording audio channel timeslot.
+ *
+ * Get the Voice CODEC secondary audio channel timeslot.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       timeslot        The secondary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC secondary audio channel
+ *                                   timeslot was successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC secondary audio channel
+ *                                   timeslot could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_secondary_txslot(const PMIC_AUDIO_HANDLE
+						   handle,
+						   PMIC_AUDIO_VCODEC_TIMESLOT *
+						   const timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) {
+		rc = PMIC_SUCCESS;
+		*timeslot = vCodec.secondaryTXtimeslot;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Set/Enable the Voice CODEC options.
+ *
+ * Set or enable various Voice CODEC options. The available options include
+ * the use of dithering, highpass digital filters, and loopback modes.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       config          The Voice CODEC options to enable.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC options were
+ *                                   successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or Voice CODEC options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC options could not be
+ *                                   successfully set/enabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_config(const PMIC_AUDIO_HANDLE handle,
+					 const PMIC_AUDIO_VCODEC_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (config & DITHERING) {
+			reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 0);
+			reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1);
+		}
+
+		if (config & INPUT_HIGHPASS_FILTER) {
+			reg_write |= SET_BITS(regAUD_CODEC, AUDIHPF, 1);
+			reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1);
+		}
+
+		if (config & OUTPUT_HIGHPASS_FILTER) {
+			reg_write |= SET_BITS(regAUD_CODEC, AUDOHPF, 1);
+			reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1);
+		}
+
+		if (config & DIGITAL_LOOPBACK) {
+			reg_write |= SET_BITS(regAUD_CODEC, CDCDLM, 1);
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1);
+		}
+
+		if (config & ANALOG_LOOPBACK) {
+			reg_write |= SET_BITS(regAUD_CODEC, CDCALM, 1);
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1);
+		}
+
+		if (config & VCODEC_MASTER_CLOCK_OUTPUTS) {
+			reg_write |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) |
+			    SET_BITS(regAUD_CODEC, CDCTS, 0);
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) |
+			    SET_BITS(regAUD_CODEC, CDCTS, 1);
+
+		}
+
+		if (config & TRISTATE_TS) {
+			reg_write |= SET_BITS(regAUD_CODEC, CDCTS, 1);
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1);
+		}
+
+		if (reg_mask == 0) {
+			/* We should not reach this point without having to configure
+			 * anything so we flag it as an error.
+			 */
+			rc = PMIC_ERROR;
+		} else {
+			rc = pmic_write_reg(REG_AUDIO_CODEC,
+					    reg_write, reg_mask);
+		}
+
+		if (rc == PMIC_SUCCESS) {
+			vCodec.config |= config;
+		}
+	}
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Clear/Disable the Voice CODEC options.
+ *
+ * Clear or disable various Voice CODEC options.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   config          The Voice CODEC options to be cleared/disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC options were
+ *                                   successfully cleared/disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or the Voice CODEC options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC options could not be
+ *                                   cleared/disabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_clear_config(const PMIC_AUDIO_HANDLE handle,
+					   const PMIC_AUDIO_VCODEC_CONFIG
+					   config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (config & DITHERING) {
+			reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1);
+			reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 1);
+		}
+
+		if (config & INPUT_HIGHPASS_FILTER) {
+			reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1);
+		}
+
+		if (config & OUTPUT_HIGHPASS_FILTER) {
+			reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1);
+		}
+
+		if (config & DIGITAL_LOOPBACK) {
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1);
+		}
+
+		if (config & ANALOG_LOOPBACK) {
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1);
+		}
+
+		if (config & VCODEC_MASTER_CLOCK_OUTPUTS) {
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1);
+		}
+
+		if (config & TRISTATE_TS) {
+			reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1);
+		}
+
+		if (reg_mask == 0) {
+			/* We should not reach this point without having to configure
+			 * anything so we flag it as an error.
+			 */
+			rc = PMIC_ERROR;
+		} else {
+			rc = pmic_write_reg(REG_AUDIO_CODEC,
+					    reg_write, reg_mask);
+		}
+
+		if (rc == PMIC_SUCCESS) {
+			vCodec.config |= config;
+		}
+
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current Voice CODEC options.
+ *
+ * Get the current Voice CODEC options.
+ *
+ * @param   	handle          Device handle from pmic_audio_open() call.
+ * @param	config          The current set of Voice CODEC options.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC options were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC options could not be
+ *                                   retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_config(const PMIC_AUDIO_HANDLE handle,
+					 PMIC_AUDIO_VCODEC_CONFIG *
+					 const config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (config != (PMIC_AUDIO_VCODEC_CONFIG *) NULL)) {
+		*config = vCodec.config;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Enable the Voice CODEC bypass audio pathway.
+ *
+ * Enables the Voice CODEC bypass pathway for audio data. This allows direct
+ * output of the voltages on the TX data bus line to the output amplifiers
+ * (bypassing the digital-to-analog converters within the Voice CODEC).
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC bypass was successfully
+ *                                   enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC bypass could not be
+ *                                   enabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_enable_bypass(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_write = SET_BITS(regAUD_CODEC, CDCBYP, 1);
+	const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask);
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Disable the Voice CODEC bypass audio pathway.
+ *
+ * Disables the Voice CODEC bypass pathway for audio data. This means that
+ * the TX data bus line will deliver digital data to the digital-to-analog
+ * converters within the Voice CODEC.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC bypass was successfully
+ *                                   disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC bypass could not be
+ *                                   disabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_disable_bypass(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_write = 0;
+	const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask);
+	}
+
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * General Stereo DAC configuration.
+ *************************************************************************
+ */
+
+/*!
+ * @name General Stereo DAC Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Stereo
+ * DAC hardware.
+ */
+/*@{*/
+
+/*!
+ * @brief Set the Stereo DAC clock source and operating characteristics.
+ *
+ * Define the Stereo DAC clock source and operating characteristics. This
+ * must be done before the Stereo DAC is enabled.
+ *
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   clockIn         Select the clock signal source.
+ * @param   clockFreq       Select the clock signal frequency.
+ * @param   samplingRate    Select the audio data sampling rate.
+ * @param   invert          Enable inversion of the frame sync and/or
+ *                              bit clock inputs.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC clock settings were
+ *                                   successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or clock configuration was
+ *                                   invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC clock configuration
+ *                                   could not be set.
+ */
+PMIC_STATUS pmic_audio_stdac_set_clock(const PMIC_AUDIO_HANDLE handle,
+				       const PMIC_AUDIO_CLOCK_IN_SOURCE clockIn,
+				       const PMIC_AUDIO_STDAC_CLOCK_IN_FREQ
+				       clockFreq,
+				       const PMIC_AUDIO_STDAC_SAMPLING_RATE
+				       samplingRate,
+				       const PMIC_AUDIO_CLOCK_INVERT invert)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+	/* Validate all of the calling parameters. */
+	if (handle == (PMIC_AUDIO_HANDLE) NULL) {
+		rc = PMIC_PARAMETER_ERROR;
+	} else if ((handle == stDAC.handle) &&
+		   (stDAC.handleState == HANDLE_IN_USE)) {
+		if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if ((stDAC.masterSlave == BUS_MASTER_MODE)
+			   && !((clockFreq >= STDAC_CLI_3_36864MHZ)
+				&& (clockFreq <= STDAC_CLI_33_6MHZ))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if ((stDAC.masterSlave == BUS_SLAVE_MODE)
+			   && !((clockFreq >= STDAC_MCLK_PLL_DISABLED)
+				&& (clockFreq <= STDAC_BCLK_IN_PLL))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if (!((samplingRate >= STDAC_RATE_8_KHZ)
+			     && (samplingRate <= STDAC_RATE_96_KHZ))) {
+			rc = PMIC_PARAMETER_ERROR;
+		}
+		/*
+		   else if(!((invert >= NO_INVERT) && (invert <= INVERT_FRAMESYNC)))
+		   {
+		   rc = PMIC_PARAMETER_ERROR;
+		   } */
+		else {
+			reg_mask = SET_BITS(regST_DAC, STDCCLK, 7) |
+			    SET_BITS(regST_DAC, STDCCLKSEL, 1) |
+			    SET_BITS(regST_DAC, SR, 15) |
+			    SET_BITS(regST_DAC, STDCBCLINV, 1) |
+			    SET_BITS(regST_DAC, STDCFSINV, 1);
+			if (clockIn == CLOCK_IN_CLIA) {
+				reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 0);
+			} else {
+				reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 1);
+			}
+			/* How to take care of sample rates in SLAVE mode */
+			if ((clockFreq == STDAC_CLI_3_36864MHZ)
+			    || ((clockFreq == STDAC_FSYNC_IN_PLL))) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 6);
+			} else if ((clockFreq == STDAC_CLI_12MHZ)
+				   || (clockFreq == STDAC_MCLK_PLL_DISABLED)) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 5);
+			} else if (clockFreq == STDAC_CLI_13MHZ) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 0);
+			} else if (clockFreq == STDAC_CLI_15_36MHZ) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 1);
+			} else if (clockFreq == STDAC_CLI_16_8MHZ) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 2);
+			} else if (clockFreq == STDAC_CLI_26MHZ) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 4);
+			} else if ((clockFreq == STDAC_CLI_33_6MHZ)
+				   || (clockFreq == STDAC_BCLK_IN_PLL)) {
+				reg_value |= SET_BITS(regST_DAC, STDCCLK, 7);
+			}
+
+			reg_value |= SET_BITS(regST_DAC, SR, samplingRate);
+
+			if (invert & INVERT_BITCLOCK) {
+				reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 1);
+			}
+			if (invert & INVERT_FRAMESYNC) {
+				reg_value |= SET_BITS(regST_DAC, STDCFSINV, 1);
+			}
+			if (invert & NO_INVERT) {
+				reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 0);
+				reg_value |= SET_BITS(regST_DAC, STDCFSINV, 0);
+			}
+			if (pmic_write_reg
+			    (REG_AUDIO_STEREO_DAC, reg_value,
+			     reg_mask) != PMIC_SUCCESS) {
+				rc = PMIC_ERROR;
+			} else {
+				pr_debug("STDAC clock set\n");
+				rc = PMIC_SUCCESS;
+				stDAC.clockIn = clockIn;
+				stDAC.clockFreq = clockFreq;
+				stDAC.samplingRate = samplingRate;
+				stDAC.invert = invert;
+			}
+
+		}
+
+	} else {
+		rc = PMIC_PARAMETER_ERROR;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the Stereo DAC clock source and operating characteristics.
+ *
+ * Get the current Stereo DAC clock source and operating characteristics.
+ *
+ * @param  handle          Device handle from pmic_audio_open() call.
+ * @param  clockIn         The clock signal source.
+ * @param  clockFreq       The clock signal frequency.
+ * @param  samplingRate    The audio data sampling rate.
+ * @param  invert          Inversion of the frame sync and/or
+ *                         bit clock inputs is enabled/disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC clock settings were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC clock configuration
+ *                                   could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_stdac_get_clock(const PMIC_AUDIO_HANDLE handle,
+				       PMIC_AUDIO_CLOCK_IN_SOURCE *
+				       const clockIn,
+				       PMIC_AUDIO_STDAC_SAMPLING_RATE *
+				       const samplingRate,
+				       PMIC_AUDIO_STDAC_CLOCK_IN_FREQ *
+				       const clockFreq,
+				       PMIC_AUDIO_CLOCK_INVERT * const invert)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) &&
+	    (stDAC.handleState == HANDLE_IN_USE) &&
+	    (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) &&
+	    (samplingRate != (PMIC_AUDIO_STDAC_SAMPLING_RATE *) NULL) &&
+	    (clockFreq != (PMIC_AUDIO_STDAC_CLOCK_IN_FREQ *) NULL) &&
+	    (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) {
+		*clockIn = stDAC.clockIn;
+		*samplingRate = stDAC.samplingRate;
+		*clockFreq = stDAC.clockFreq;
+		*invert = stDAC.invert;
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the Stereo DAC primary audio channel timeslot.
+ *
+ * Set the Stereo DAC primary audio channel timeslot. This function must be
+ * used if the default timeslot for the primary audio channel is to be changed.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param	timeslot        Select the primary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC primary audio channel
+ *                                   timeslot was successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or audio channel timeslot
+ *                                   was invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC primary audio channel
+ *                                   timeslot could not be set.
+ */
+PMIC_STATUS pmic_audio_stdac_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle,
+					       const PMIC_AUDIO_STDAC_TIMESLOTS
+					       timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSLOT, 3);
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		if ((timeslot == USE_TS0_TS1) || (timeslot == USE_TS2_TS3)
+		    || (timeslot == USE_TS4_TS5) || (timeslot == USE_TS6_TS7)) {
+			if (pmic_write_reg
+			    (REG_AUDIO_SSI_NETWORK, timeslot,
+			     reg_mask) != PMIC_SUCCESS) {
+				rc = PMIC_ERROR;
+			} else {
+				pr_debug("STDAC primary timeslot set\n");
+				stDAC.timeslot = timeslot;
+				rc = PMIC_SUCCESS;
+			}
+
+		} else {
+			rc = PMIC_PARAMETER_ERROR;
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current Stereo DAC primary audio channel timeslot.
+ *
+ * Get the current Stereo DAC primary audio channel timeslot.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   timeslot        The primary audio channel timeslot.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC primary audio channel
+ *                                   timeslot was successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC primary audio channel
+ *                                   timeslot could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_stdac_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle,
+					       PMIC_AUDIO_STDAC_TIMESLOTS *
+					       const timeslot)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) &&
+	    (stDAC.handleState == HANDLE_IN_USE) &&
+	    (timeslot != (PMIC_AUDIO_STDAC_TIMESLOTS *) NULL)) {
+		*timeslot = stDAC.timeslot;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set/Enable the Stereo DAC options.
+ *
+ * Set or enable various Stereo DAC options. The available options include
+ * resetting the digital filter and enabling the bus master clock outputs.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ * @param   config          The Stereo DAC options to enable.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC options were
+ *                                   successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or Stereo DAC options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC options could not be
+ *                                   successfully set/enabled.
+ */
+PMIC_STATUS pmic_audio_stdac_set_config(const PMIC_AUDIO_HANDLE handle,
+					const PMIC_AUDIO_STDAC_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		if (config & STDAC_MASTER_CLOCK_OUTPUTS) {
+			reg_write |= SET_BITS(regST_DAC, STDCCLKEN, 1);
+			reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1);
+		}
+
+		rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_write, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			stDAC.config |= config;
+			pr_debug("STDAC config set\n");
+
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Clear/Disable the Stereo DAC options.
+ *
+ * Clear or disable various Stereo DAC options.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       config          The Stereo DAC options to be cleared/disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC options were
+ *                                   successfully cleared/disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or the Stereo DAC options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC options could not be
+ *                                   cleared/disabled.
+ */
+PMIC_STATUS pmic_audio_stdac_clear_config(const PMIC_AUDIO_HANDLE handle,
+					  const PMIC_AUDIO_STDAC_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+
+		if (config & STDAC_MASTER_CLOCK_OUTPUTS) {
+			reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1);
+		}
+
+		if (reg_mask != 0) {
+			rc = pmic_write_reg(REG_AUDIO_STEREO_DAC,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				stDAC.config &= ~config;
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current Stereo DAC options.
+ *
+ * Get the current Stereo DAC options.
+ *
+ * @param   	handle          Device handle from pmic_audio_open() call.
+ * @param   	config          The current set of Stereo DAC options.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC options were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC options could not be
+ *                                   retrieved.
+ */
+PMIC_STATUS pmic_audio_stdac_get_config(const PMIC_AUDIO_HANDLE handle,
+					PMIC_AUDIO_STDAC_CONFIG * const config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == stDAC.handle) &&
+	    (stDAC.handleState == HANDLE_IN_USE) &&
+	    (config != (PMIC_AUDIO_STDAC_CONFIG *) NULL)) {
+		*config = stDAC.config;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * Audio input section configuration.
+ *************************************************************************
+ */
+
+/*!
+ * @name Audio Input Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC audio
+ * input hardware.
+ */
+/*@{*/
+
+/*!
+ * @brief Set/Enable the audio input section options.
+ *
+ * Set or enable various audio input section options. The only available
+ * option right now is to enable the automatic disabling of the microphone
+ * input amplifiers when a microphone/headset is inserted or removed.
+ * NOT SUPPORTED BY MC13783
+ *
+ * @param  	handle          Device handle from pmic_audio_open() call.
+ * @param   	config          The audio input section options to enable.
+ *
+ * @retval      PMIC_SUCCESS         If the audio input section options were
+ *                                   successfully configured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or audio input section
+ *                                   options were invalid.
+ * @retval      PMIC_ERROR           If the audio input section options could
+ *                                   not be successfully set/enabled.
+ */
+PMIC_STATUS pmic_audio_input_set_config(const PMIC_AUDIO_HANDLE handle,
+					const PMIC_AUDIO_INPUT_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+}
+
+/*!
+ * @brief Clear/Disable the audio input section options.
+ *
+ * Clear or disable various audio input section options.
+ *
+ * @param   	handle          Device handle from pmic_audio_open() call.
+ * @param   	config          The audio input section options to be
+ *                              cleared/disabled.
+ * NOT SUPPORTED BY MC13783
+ *
+ * @retval      PMIC_SUCCESS         If the audio input section options were
+ *                                   successfully cleared/disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or the audio input section
+ *                                   options were invalid.
+ * @retval      PMIC_ERROR           If the audio input section options could
+ *                                   not be cleared/disabled.
+ */
+PMIC_STATUS pmic_audio_input_clear_config(const PMIC_AUDIO_HANDLE handle,
+					  const PMIC_AUDIO_INPUT_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+
+}
+
+/*!
+ * @brief Get the current audio input section options.
+ *
+ * Get the current audio input section options.
+ *
+ * @param[in]   handle          Device handle from pmic_audio_open() call.
+ * @param[out]  config          The current set of audio input section options.
+ * NOT SUPPORTED BY MC13783
+ *
+ * @retval      PMIC_SUCCESS         If the audio input section options were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the audio input section options could
+ *                                   not be retrieved.
+ */
+PMIC_STATUS pmic_audio_input_get_config(const PMIC_AUDIO_HANDLE handle,
+					PMIC_AUDIO_INPUT_CONFIG * const config)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * Audio recording using the Voice CODEC.
+ *************************************************************************
+ */
+
+/*!
+ * @name Audio Recording Using the Voice CODEC Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Voice CODEC
+ * to perform audio recording.
+ */
+/*@{*/
+
+/*!
+ * @brief Select the microphone inputs to be used for Voice CODEC recording.
+ *
+ * Select left (mc13783-only) and right microphone inputs for Voice CODEC
+ * recording. It is possible to disable or not use a particular microphone
+ * input channel by specifying NO_MIC as a parameter.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       leftChannel     Select the left microphone input channel.
+ * @param       rightChannel    Select the right microphone input channel.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input channels were
+ *                                   successfully enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or microphone input ports
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the microphone input channels could
+ *                                   not be successfully enabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_mic(const PMIC_AUDIO_HANDLE handle,
+				      const PMIC_AUDIO_INPUT_PORT leftChannel,
+				      const PMIC_AUDIO_INPUT_PORT rightChannel)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (!((leftChannel == NO_MIC) || (leftChannel == MIC1_LEFT))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else if (!((rightChannel == NO_MIC)
+			     || (rightChannel == MIC1_RIGHT_MIC_MONO)
+			     || (rightChannel == TXIN_EXT)
+			     || (rightChannel == MIC2_AUX))) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else {
+			if (leftChannel == NO_MIC) {
+			} else {	/* Left channel MIC enable */
+				reg_mask = SET_BITS(regAUDIO_TX, AMC1LEN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 1);
+				reg_write = SET_BITS(regAUDIO_TX, AMC1LEN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 0);
+			}
+			/*For right channel enable one and clear the other two as well as RXINREC */
+			if (rightChannel == NO_MIC) {
+			} else if (rightChannel == MIC1_RIGHT_MIC_MONO) {
+				reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 1) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 1) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 1);
+				reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 0) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 0) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 0);
+			} else if (rightChannel == MIC2_AUX) {
+				reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 1) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 1) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 1);
+				reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 0) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 1) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 0);
+			} else {	/* TX line in */
+				reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 1) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 1) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 1);
+				reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) |
+				    SET_BITS(regAUDIO_TX, RXINREC, 0) |
+				    SET_BITS(regAUDIO_TX, AMC2EN, 0) |
+				    SET_BITS(regAUDIO_TX, ATXINEN, 1);
+			}
+
+			if (reg_mask == 0) {
+				rc = PMIC_PARAMETER_ERROR;
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_TX,
+						    reg_write, reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					pr_debug
+					    ("MIC inputs configured successfully\n");
+					vCodec.leftChannelMic.mic = leftChannel;
+					vCodec.rightChannelMic.mic =
+					    rightChannel;
+
+				}
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current microphone inputs being used for Voice CODEC
+ *        recording.
+ *
+ * Get the left (mc13783-only) and right microphone inputs currently being
+ * used for Voice CODEC recording.
+ *
+ * @param   	handle          Device handle from pmic_audio_open() call.
+ * @param 	leftChannel     The left microphone input channel.
+ * @param	rightChannel    The right microphone input channel.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input channels were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the microphone input channels could
+ *                                   not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_mic(const PMIC_AUDIO_HANDLE handle,
+				      PMIC_AUDIO_INPUT_PORT * const leftChannel,
+				      PMIC_AUDIO_INPUT_PORT *
+				      const rightChannel)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (leftChannel != (PMIC_AUDIO_INPUT_PORT *) NULL) &&
+	    (rightChannel != (PMIC_AUDIO_INPUT_PORT *) NULL)) {
+		*leftChannel = vCodec.leftChannelMic.mic;
+		*rightChannel = vCodec.rightChannelMic.mic;
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+	return rc;
+}
+
+/*!
+ * @brief Enable/disable the microphone input.
+ *
+ * This function enables/disables the current microphone input channel. The
+ * input amplifier is automatically turned off when the microphone input is
+ * disabled.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param       leftChannel     The left microphone input channel state.
+ * @param       rightChannel    the right microphone input channel state.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input channels were
+ *                                   successfully reconfigured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or microphone input states
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the microphone input channels could
+ *                                   not be reconfigured.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_mic_on_off(const PMIC_AUDIO_HANDLE handle,
+					     const PMIC_AUDIO_INPUT_MIC_STATE
+					     leftChannel,
+					     const PMIC_AUDIO_INPUT_MIC_STATE
+					     rightChannel)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+	unsigned int curr_left = 0;
+	unsigned int curr_right = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		curr_left = vCodec.leftChannelMic.mic;
+		curr_right = vCodec.rightChannelMic.mic;
+		if ((curr_left == NO_MIC) && (curr_right == NO_MIC)) {
+			rc = PMIC_PARAMETER_ERROR;
+		} else {
+			if (curr_left == MIC1_LEFT) {
+				if ((leftChannel == MICROPHONE_ON) &&
+				    (vCodec.leftChannelMic.micOnOff ==
+				     MICROPHONE_OFF)) {
+					/* Enable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1LEN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1LEN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC, 0);
+
+				} else if ((leftChannel == MICROPHONE_OFF) &&
+					   (vCodec.leftChannelMic.micOnOff ==
+					    MICROPHONE_ON)) {
+					/* Disable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1LEN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1LEN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC, 0);
+
+				} else {
+					/* Both are in same state . Nothing to be done */
+				}
+
+			}
+			if (curr_right == MIC1_RIGHT_MIC_MONO) {
+				if ((rightChannel == MICROPHONE_ON) &&
+				    (vCodec.leftChannelMic.micOnOff ==
+				     MICROPHONE_OFF)) {
+					/* Enable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 0);
+				} else if ((rightChannel == MICROPHONE_OFF)
+					   && (vCodec.leftChannelMic.micOnOff ==
+					       MICROPHONE_ON)) {
+					/* Disable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 0);
+				} else {
+					/* Both are in same state . Nothing to be done */
+				}
+			} else if (curr_right == MIC2_AUX) {
+				if ((rightChannel == MICROPHONE_ON)
+				    && (vCodec.leftChannelMic.micOnOff ==
+					MICROPHONE_OFF)) {
+					/* Enable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 0);
+				} else if ((rightChannel == MICROPHONE_OFF)
+					   && (vCodec.leftChannelMic.micOnOff ==
+					       MICROPHONE_ON)) {
+					/* Disable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 0);
+				} else {
+					/* Both are in same state . Nothing to be done */
+				}
+			} else if (curr_right == TXIN_EXT) {
+				if ((rightChannel == MICROPHONE_ON)
+				    && (vCodec.leftChannelMic.micOnOff ==
+					MICROPHONE_OFF)) {
+					/* Enable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+				} else if ((rightChannel == MICROPHONE_OFF)
+					   && (vCodec.leftChannelMic.micOnOff ==
+					       MICROPHONE_ON)) {
+					/* Disable the microphone */
+					reg_mask |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   1) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     1) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 1);
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1REN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   RXINREC,
+								   0) |
+					    SET_BITS(regAUDIO_TX, AMC2EN,
+						     0) | SET_BITS(regAUDIO_TX,
+								   ATXINEN, 0);
+				} else {
+					/* Both are in same state . Nothing to be done */
+				}
+			}
+			if (reg_mask == 0) {
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_TX,
+						    reg_write, reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					pr_debug
+					    ("MIC states configured successfully\n");
+					vCodec.leftChannelMic.micOnOff =
+					    leftChannel;
+					vCodec.rightChannelMic.micOnOff =
+					    rightChannel;
+				}
+			}
+		}
+
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Return the current state of the microphone inputs.
+ *
+ * This function returns the current state (on/off) of the microphone
+ * input channels.
+ *
+ * @param       handle          Device handle from pmic_audio_open() call.
+ * @param	leftChannel     The current left microphone input channel
+ *                              state.
+ * @param	rightChannel    the current right microphone input channel
+ *                              state.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input channel states
+ *                                   were successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the microphone input channel states
+ *                                   could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_mic_on_off(const PMIC_AUDIO_HANDLE handle,
+					     PMIC_AUDIO_INPUT_MIC_STATE *
+					     const leftChannel,
+					     PMIC_AUDIO_INPUT_MIC_STATE *
+					     const rightChannel)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (leftChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL) &&
+	    (rightChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL)) {
+		*leftChannel = vCodec.leftChannelMic.micOnOff;
+		*rightChannel = vCodec.rightChannelMic.micOnOff;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the microphone input amplifier mode and gain level.
+ *
+ * This function sets the current microphone input amplifier operating mode
+ * and gain level.
+ *
+ * @param       handle           Device handle from pmic_audio_open() call.
+ * @param       leftChannelMode  The left microphone input amplifier mode.
+ * @param       leftChannelGain  The left microphone input amplifier gain level.
+ * @param       rightChannelMode The right microphone input amplifier mode.
+ * @param       rightChannelGain The right microphone input amplifier gain
+ *                               level.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input amplifiers were
+ *                                   successfully reconfigured.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or microphone input amplifier
+ *                                   modes or gain levels were invalid.
+ * @retval      PMIC_ERROR           If the microphone input amplifiers could
+ *                                   not be reconfigured.
+ */
+PMIC_STATUS pmic_audio_vcodec_set_record_gain(const PMIC_AUDIO_HANDLE handle,
+					      const PMIC_AUDIO_MIC_AMP_MODE
+					      leftChannelMode,
+					      const PMIC_AUDIO_MIC_GAIN
+					      leftChannelGain,
+					      const PMIC_AUDIO_MIC_AMP_MODE
+					      rightChannelMode,
+					      const PMIC_AUDIO_MIC_GAIN
+					      rightChannelGain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (!(((leftChannelGain >= MIC_GAIN_MINUS_8DB)
+		       && (leftChannelGain <= MIC_GAIN_PLUS_23DB))
+		      && ((rightChannelGain >= MIC_GAIN_MINUS_8DB)
+			  && (rightChannelGain <= MIC_GAIN_PLUS_23DB)))) {
+			rc = PMIC_PARAMETER_ERROR;
+			pr_debug("VCODEC set record gain - wrong gain value\n");
+		} else if (((leftChannelMode != AMP_OFF)
+			    && (leftChannelMode != VOLTAGE_TO_VOLTAGE)
+			    && (leftChannelMode != CURRENT_TO_VOLTAGE))
+			   || ((rightChannelMode != VOLTAGE_TO_VOLTAGE)
+			       && (rightChannelMode != CURRENT_TO_VOLTAGE)
+			       && (rightChannelMode != AMP_OFF))) {
+			rc = PMIC_PARAMETER_ERROR;
+			pr_debug("VCODEC set record gain - wrong amp mode\n");
+		} else {
+			if (vCodec.leftChannelMic.mic == MIC1_LEFT) {
+				reg_mask = SET_BITS(regAUDIO_TX, AMC1LITOV, 1) |
+				    SET_BITS(regAUDIO_TX, PGATXL, 31);
+				if (leftChannelMode == VOLTAGE_TO_VOLTAGE) {
+					reg_write =
+					    SET_BITS(regAUDIO_TX, AMC1LITOV, 0);
+				} else {
+					reg_write =
+					    SET_BITS(regAUDIO_TX, AMC1LITOV, 1);
+				}
+				reg_write |=
+				    SET_BITS(regAUDIO_TX, PGATXL,
+					     leftChannelGain);
+			}
+			if (vCodec.rightChannelMic.mic == MIC1_RIGHT_MIC_MONO) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_TX, AMC1RITOV,
+					     1) | SET_BITS(regAUDIO_TX, PGATXR,
+							   31);
+				if (rightChannelMode == VOLTAGE_TO_VOLTAGE) {
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1RITOV, 0);
+				} else {
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC1RITOV, 1);
+				}
+				reg_write |=
+				    SET_BITS(regAUDIO_TX, PGATXR,
+					     rightChannelGain);
+			} else if (vCodec.rightChannelMic.mic == MIC2_AUX) {
+				reg_mask |= SET_BITS(regAUDIO_TX, AMC2ITOV, 1);
+				reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31);
+				if (rightChannelMode == VOLTAGE_TO_VOLTAGE) {
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC2ITOV, 0);
+				} else {
+					reg_write |=
+					    SET_BITS(regAUDIO_TX, AMC2ITOV, 1);
+				}
+				reg_write |=
+				    SET_BITS(regAUDIO_TX, PGATXR,
+					     rightChannelGain);
+			} else if (vCodec.rightChannelMic.mic == TXIN_EXT) {
+				reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31);
+				/* No current to voltage option for TX IN amplifier */
+				reg_write |=
+				    SET_BITS(regAUDIO_TX, PGATXR,
+					     rightChannelGain);
+			}
+
+			if (reg_mask == 0) {
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_TX,
+						    reg_write, reg_mask);
+				reg_write =
+				    SET_BITS(regAUDIO_TX, PGATXL,
+					     leftChannelGain);
+				reg_mask = SET_BITS(regAUDIO_TX, PGATXL, 31);
+				rc = pmic_write_reg(REG_AUDIO_TX,
+						    reg_write, reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					pr_debug("MIC amp mode and gain set\n");
+					vCodec.leftChannelMic.ampMode =
+					    leftChannelMode;
+					vCodec.leftChannelMic.gain =
+					    leftChannelGain;
+					vCodec.rightChannelMic.ampMode =
+					    rightChannelMode;
+					vCodec.rightChannelMic.gain =
+					    rightChannelGain;
+
+				}
+			}
+		}
+	}
+
+	/* Exit critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current microphone input amplifier mode and gain level.
+ *
+ * This function gets the current microphone input amplifier operating mode
+ * and gain level.
+ *
+ * @param	handle           Device handle from pmic_audio_open() call.
+ * @param	leftChannelMode  The left microphone input amplifier mode.
+ * @param	leftChannelGain  The left microphone input amplifier gain level.
+ * @param 	rightChannelMode The right microphone input amplifier mode.
+ * @param       rightChannelGain The right microphone input amplifier gain
+ *                               level.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone input amplifier modes
+ *                                   and gain levels were successfully
+ *                                   retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the microphone input amplifier modes
+ *                                   and gain levels could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_vcodec_get_record_gain(const PMIC_AUDIO_HANDLE handle,
+					      PMIC_AUDIO_MIC_AMP_MODE *
+					      const leftChannelMode,
+					      PMIC_AUDIO_MIC_GAIN *
+					      const leftChannelGain,
+					      PMIC_AUDIO_MIC_AMP_MODE *
+					      const rightChannelMode,
+					      PMIC_AUDIO_MIC_GAIN *
+					      const rightChannelGain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == vCodec.handle) &&
+	    (vCodec.handleState == HANDLE_IN_USE) &&
+	    (leftChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) &&
+	    (leftChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL) &&
+	    (rightChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) &&
+	    (rightChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL)) {
+		*leftChannelMode = vCodec.leftChannelMic.ampMode;
+		*leftChannelGain = vCodec.leftChannelMic.gain;
+		*rightChannelMode = vCodec.rightChannelMic.ampMode;
+		*rightChannelGain = vCodec.rightChannelMic.gain;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Enable a microphone bias circuit.
+ *
+ * This function enables one of the available microphone bias circuits.
+ *
+ * @param       handle           Device handle from pmic_audio_open() call.
+ * @param       biasCircuit      The microphone bias circuit to be enabled.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone bias circuit was
+ *                                   successfully enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or selected microphone bias
+ *                                   circuit was invalid.
+ * @retval      PMIC_ERROR           If the microphone bias circuit could not
+ *                                   be enabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_enable_micbias(const PMIC_AUDIO_HANDLE handle,
+					     const PMIC_AUDIO_MIC_BIAS
+					     biasCircuit)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (biasCircuit & MIC_BIAS1) {
+			reg_write = SET_BITS(regAUDIO_TX, MC1BEN, 1);
+			reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1);
+		}
+		if (biasCircuit & MIC_BIAS2) {
+			reg_write |= SET_BITS(regAUDIO_TX, MC2BEN, 1);
+			reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1);
+		}
+		if (reg_mask != 0) {
+			rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask);
+		}
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Disable a microphone bias circuit.
+ *
+ * This function disables one of the available microphone bias circuits.
+ *
+ * @param      handle           Device handle from pmic_audio_open() call.
+ * @param      biasCircuit      The microphone bias circuit to be disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the microphone bias circuit was
+ *                                   successfully disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or selected microphone bias
+ *                                   circuit was invalid.
+ * @retval      PMIC_ERROR           If the microphone bias circuit could not
+ *                                   be disabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_disable_micbias(const PMIC_AUDIO_HANDLE handle,
+					      const PMIC_AUDIO_MIC_BIAS
+					      biasCircuit)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (biasCircuit & MIC_BIAS1) {
+			reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1);
+		}
+
+		if (biasCircuit & MIC_BIAS2) {
+			reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1);
+		}
+
+		if (reg_mask != 0) {
+			rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask);
+		}
+	}
+
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * Audio Playback Using the Voice CODEC.
+ *************************************************************************
+ */
+
+/*!
+ * @name Audio Playback Using the Voice CODEC Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Voice CODEC
+ * to perform audio playback.
+ */
+/*@{*/
+
+/*!
+ * @brief Configure and enable the Voice CODEC mixer.
+ *
+ * This function configures and enables the Voice CODEC mixer.
+ *
+ * @param       handle              Device handle from pmic_audio_open() call.
+ * @param       rxSecondaryTimeslot The timeslot used for the secondary audio
+ *                                  channel.
+ * @param       gainIn              The secondary audio channel gain level.
+ * @param       gainOut             The mixer output gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC mixer was successfully
+ *                                   configured and enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or mixer configuration
+ *                                   was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC mixer could not be
+ *                                   reconfigured or enabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_enable_mixer(const PMIC_AUDIO_HANDLE handle,
+					   const PMIC_AUDIO_VCODEC_TIMESLOT
+					   rxSecondaryTimeslot,
+					   const PMIC_AUDIO_VCODEC_MIX_IN_GAIN
+					   gainIn,
+					   const PMIC_AUDIO_VCODEC_MIX_OUT_GAIN
+					   gainOut)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		if (!((rxSecondaryTimeslot >= USE_TS0)
+		      && (rxSecondaryTimeslot <= USE_TS3))) {
+			pr_debug
+			    ("VCODEC enable mixer - wrong sec rx timeslot\n");
+		} else if (!((gainIn >= VCODEC_NO_MIX)
+			     && (gainIn <= VCODEC_MIX_IN_MINUS_12DB))) {
+			pr_debug("VCODEC enable mixer - wrong mix in gain\n");
+
+		} else if (!((gainOut >= VCODEC_MIX_OUT_0DB)
+			     && (gainOut <= VCODEC_MIX_OUT_MINUS_6DB))) {
+			pr_debug("VCODEC enable mixer - wrong mix out gain\n");
+		} else {
+
+			reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECSLOT, 3) |
+			    SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 3) |
+			    SET_BITS(regSSI_NETWORK, CDCSUMGAIN, 1);
+			reg_write =
+			    SET_BITS(regSSI_NETWORK, CDCRXSECSLOT,
+				     rxSecondaryTimeslot) |
+			    SET_BITS(regSSI_NETWORK, CDCRXSECGAIN,
+				     gainIn) | SET_BITS(regSSI_NETWORK,
+							CDCSUMGAIN, gainOut);
+			rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+					    reg_write, reg_mask);
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Vcodec mixer enabled\n");
+			}
+		}
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Disable the Voice CODEC mixer.
+ *
+ * This function disables the Voice CODEC mixer.
+ *
+ * @param       handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the Voice CODEC mixer was successfully
+ *                                   disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Voice CODEC mixer could not be
+ *                                   disabled.
+ */
+PMIC_STATUS pmic_audio_vcodec_disable_mixer(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask;
+
+	if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 1);
+		rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+				    VCODEC_NO_MIX, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			pr_debug("Vcodec mixer disabled\n");
+		}
+
+	}
+
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * Audio Playback Using the Stereo DAC.
+ *************************************************************************
+ */
+
+/*!
+ * @name Audio Playback Using the Stereo DAC Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC Stereo DAC
+ * to perform audio playback.
+ */
+/*@{*/
+
+/*!
+ * @brief Configure and enable the Stereo DAC mixer.
+ *
+ * This function configures and enables the Stereo DAC mixer.
+ *
+ * @param      handle              Device handle from pmic_audio_open() call.
+ * @param      rxSecondaryTimeslot The timeslot used for the secondary audio
+ *                                  channel.
+ * @param      gainIn              The secondary audio channel gain level.
+ * @param      gainOut             The mixer output gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC mixer was successfully
+ *                                   configured and enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or mixer configuration
+ *                                   was invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC mixer could not be
+ *                                   reconfigured or enabled.
+ */
+PMIC_STATUS pmic_audio_stdac_enable_mixer(const PMIC_AUDIO_HANDLE handle,
+					  const PMIC_AUDIO_STDAC_TIMESLOTS
+					  rxSecondaryTimeslot,
+					  const PMIC_AUDIO_STDAC_MIX_IN_GAIN
+					  gainIn,
+					  const PMIC_AUDIO_STDAC_MIX_OUT_GAIN
+					  gainOut)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		if (!((rxSecondaryTimeslot >= USE_TS0_TS1)
+		      && (rxSecondaryTimeslot <= USE_TS6_TS7))) {
+			rc = PMIC_PARAMETER_ERROR;
+			pr_debug("STDAC enable mixer - wrong sec timeslot\n");
+		} else if (!((gainIn >= STDAC_NO_MIX)
+			     && (gainIn <= STDAC_MIX_IN_MINUS_12DB))) {
+			rc = PMIC_PARAMETER_ERROR;
+			pr_debug("STDAC enable mixer - wrong mix in gain\n");
+		} else if (!((gainOut >= STDAC_MIX_OUT_0DB)
+			     && (gainOut <= STDAC_MIX_OUT_MINUS_6DB))) {
+			rc = PMIC_PARAMETER_ERROR;
+			pr_debug("STDAC enable mixer - wrong mix out gain\n");
+		} else {
+
+			reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSECSLOT, 3) |
+			    SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 3) |
+			    SET_BITS(regSSI_NETWORK, STDCSUMGAIN, 1);
+			reg_write =
+			    SET_BITS(regSSI_NETWORK, STDCRXSECSLOT,
+				     rxSecondaryTimeslot) |
+			    SET_BITS(regSSI_NETWORK, STDCRXSECGAIN,
+				     gainIn) | SET_BITS(regSSI_NETWORK,
+							STDCSUMGAIN, gainOut);
+			rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+					    reg_write, reg_mask);
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("STDAC mixer enabled\n");
+			}
+		}
+
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Disable the Stereo DAC mixer.
+ *
+ * This function disables the Stereo DAC mixer.
+ *
+ * @param       handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the Stereo DAC mixer was successfully
+ *                                   disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the Stereo DAC mixer could not be
+ *                                   disabled.
+ */
+PMIC_STATUS pmic_audio_stdac_disable_mixer(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_write = 0;
+	const unsigned int reg_mask =
+	    SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask);
+	}
+
+	return rc;
+}
+
+/*@}*/
+
+/*************************************************************************
+ * Audio Output Control
+ *************************************************************************
+ */
+
+/*!
+ * @name Audio Output Section Setup and Configuration APIs
+ * Functions for general setup and configuration of the PMIC audio output
+ * section to support playback.
+ */
+/*@{*/
+
+/*!
+ * @brief Select the audio output ports.
+ *
+ * This function selects the audio output ports to be used. This also enables
+ * the appropriate output amplifiers.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   port                The audio output ports to be used.
+ *
+ * @retval      PMIC_SUCCESS         If the audio output ports were successfully
+ *                                   acquired.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or output ports were
+ *                                   invalid.
+ * @retval      PMIC_ERROR           If the audio output ports could not be
+ *                                   acquired.
+ */
+PMIC_STATUS pmic_audio_output_set_port(const PMIC_AUDIO_HANDLE handle,
+				       const PMIC_AUDIO_OUTPUT_PORT port)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) {
+		rc = PMIC_NOT_SUPPORTED;
+	} else {
+		if (((handle == stDAC.handle)
+		     && (stDAC.handleState == HANDLE_IN_USE))
+		    || ((handle == extStereoIn.handle)
+			&& (extStereoIn.handleState == HANDLE_IN_USE))
+		    || ((handle == vCodec.handle)
+			&& (vCodec.handleState == HANDLE_IN_USE)
+			&& (audioOutput.vCodecOut == VCODEC_MIXER_OUT))) {
+			/* Stereo signal and MIXER source needs to be routed to the port
+			   / Avoid Codec direct out */
+
+			if (port & MONO_SPEAKER) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ASPSEL, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ASPSEL, 1);
+			}
+			if (port & MONO_LOUDSPEAKER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPREF, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ALSPEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ALSPREF,
+							   1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPSEL, 1);
+			}
+			if (port & STEREO_HEADSET_LEFT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, AHSLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   AHSSEL, 1);
+			}
+			if (port & STEREO_HEADSET_RIGHT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) |
+				    SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, AHSREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   AHSSEL, 1);
+			}
+			if (port & STEREO_OUT_LEFT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+			}
+			if (port & STEREO_OUT_RIGHT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+			}
+			if (port & STEREO_LEFT_LOW_POWER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1);
+
+				reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1);
+			}
+		} else if ((handle == vCodec.handle)
+			   && (vCodec.handleState == HANDLE_IN_USE)
+			   && (audioOutput.vCodecOut = VCODEC_DIRECT_OUT)) {
+			if (port & MONO_SPEAKER) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ASPSEL, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ASPSEL, 0);
+			}
+			if (port & MONO_LOUDSPEAKER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPREF, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ALSPEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ALSPREF,
+							   1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPSEL, 0);
+			}
+
+			if (port & STEREO_HEADSET_LEFT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, AHSLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   AHSSEL, 0);
+			}
+			if (port & STEREO_HEADSET_RIGHT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) |
+				    SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, AHSREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   AHSSEL, 0);
+			}
+			if (port & STEREO_OUT_LEFT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 0);
+			}
+			if (port & STEREO_OUT_RIGHT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN,
+					     1) | SET_BITS(regAUDIO_RX_0,
+							   ARXOUTSEL, 0);
+			}
+			if (port & MONO_CDCOUT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1);
+
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1);
+			}
+		}
+
+		if (reg_mask == 0) {
+
+		} else {
+			rc = pmic_write_reg(REG_AUDIO_RX_0,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("output ports  enabled\n");
+				audioOutput.outputPort = port;
+
+			}
+		}
+	}
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Deselect/disable the audio output ports.
+ *
+ * This function disables the audio output ports that were previously enabled
+ * by calling pmic_audio_output_set_port().
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   port                The audio output ports to be disabled.
+ *
+ * @retval      PMIC_SUCCESS         If the audio output ports were successfully
+ *                                   disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or output ports were
+ *                                   invalid.
+ * @retval      PMIC_ERROR           If the audio output ports could not be
+ *                                   disabled.
+ */
+PMIC_STATUS pmic_audio_output_clear_port(const PMIC_AUDIO_HANDLE handle,
+					 const PMIC_AUDIO_OUTPUT_PORT port)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) {
+		rc = PMIC_NOT_SUPPORTED;
+	} else {
+		if (((handle == stDAC.handle)
+		     && (stDAC.handleState == HANDLE_IN_USE))
+		    || ((handle == extStereoIn.handle)
+			&& (extStereoIn.handleState == HANDLE_IN_USE))
+		    || ((handle == vCodec.handle)
+			&& (vCodec.handleState == HANDLE_IN_USE)
+			&& (audioOutput.vCodecOut = VCODEC_MIXER_OUT))) {
+			/* Stereo signal and MIXER source needs to be routed to the port /
+			   Avoid Codec direct out */
+			if (port & MONO_SPEAKER) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0);
+			}
+			if (port & MONO_LOUDSPEAKER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPREF, 1);
+
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ALSPEN,
+					     0) | SET_BITS(regAUDIO_RX_0,
+							   ALSPREF, 0);
+
+			}
+			if (port & STEREO_HEADSET_LEFT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1);
+				reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0);
+			}
+			if (port & STEREO_HEADSET_RIGHT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1);
+				reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0);
+			}
+			if (port & STEREO_OUT_LEFT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0);
+			}
+			if (port & STEREO_OUT_RIGHT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0);
+			}
+			if (port & STEREO_LEFT_LOW_POWER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1);
+				reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 0);
+			}
+		} else if ((handle == vCodec.handle)
+			   && (vCodec.handleState == HANDLE_IN_USE)
+			   && (audioOutput.vCodecOut = VCODEC_DIRECT_OUT)) {
+			if (port & MONO_SPEAKER) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0);
+			}
+			if (port & MONO_LOUDSPEAKER) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) |
+				    SET_BITS(regAUDIO_RX_0, ALSPREF, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ALSPEN,
+					     0) | SET_BITS(regAUDIO_RX_0,
+							   ALSPREF, 0);
+			}
+			if (port & STEREO_HEADSET_LEFT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1);
+				reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0);
+			}
+			if (port & STEREO_HEADSET_RIGHT) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1);
+				reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0);
+			}
+			if (port & STEREO_OUT_LEFT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0);
+			}
+			if (port & STEREO_OUT_RIGHT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0);
+			}
+			if (port & MONO_CDCOUT) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, CDCOUTEN, 0);
+			}
+		}
+#ifdef CONFIG_HEADSET_DETECT_ENABLE
+
+		if (port & STEREO_HEADSET_LEFT) {
+			reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1);
+			reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0);
+		}
+		if (port & STEREO_HEADSET_RIGHT) {
+			reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1);
+			reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0);
+		}
+#endif
+
+		if (reg_mask == 0) {
+
+		} else {
+			rc = pmic_write_reg(REG_AUDIO_RX_0,
+					    reg_write, reg_mask);
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("output ports disabled\n");
+				audioOutput.outputPort &= ~port;
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current audio output ports.
+ *
+ * This function retrieves the audio output ports that are currently being
+ * used.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   port                The audio output ports currently being used.
+ *
+ * @retval      PMIC_SUCCESS         If the audio output ports were successfully
+ *                                   retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the audio output ports could not be
+ *                                   retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_port(const PMIC_AUDIO_HANDLE handle,
+				       PMIC_AUDIO_OUTPUT_PORT * const port)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((((handle == stDAC.handle) &&
+	      (stDAC.handleState == HANDLE_IN_USE)) ||
+	     ((handle == vCodec.handle) &&
+	      (vCodec.handleState == HANDLE_IN_USE)) ||
+	     ((handle == extStereoIn.handle) &&
+	      (extStereoIn.handleState == HANDLE_IN_USE))) &&
+	    (port != (PMIC_AUDIO_OUTPUT_PORT *) NULL)) {
+		*port = audioOutput.outputPort;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the gain level for the external stereo inputs.
+ *
+ * This function sets the gain levels for the external stereo inputs.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The external stereo input gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the gain level was successfully set.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or gain level was invalid.
+ * @retval      PMIC_ERROR           If the gain level could not be set.
+ */
+PMIC_STATUS pmic_audio_output_set_stereo_in_gain(const PMIC_AUDIO_HANDLE handle,
+						 const PMIC_AUDIO_STEREO_IN_GAIN
+						 gain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1) |
+	    SET_BITS(regAUDIO_RX_1, ARXIN, 1);
+	unsigned int reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	/* The ARX amplifier for stereo is also enabled over here */
+
+	if ((gain == STEREO_IN_GAIN_0DB) || (gain == STEREO_IN_GAIN_PLUS_18DB)) {
+		if ((handle == extStereoIn.handle) &&
+		    (extStereoIn.handleState == HANDLE_IN_USE)) {
+
+			if (gain == STEREO_IN_GAIN_0DB) {
+				reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 1);
+			} else {
+				reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 0);
+			}
+
+			rc = pmic_write_reg(REG_AUDIO_RX_1,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Ext stereo gain set\n");
+				extStereoIn.inputGain = gain;
+
+			}
+
+		} else {
+			rc = PMIC_PARAMETER_ERROR;
+		}
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current gain level for the external stereo inputs.
+ *
+ * This function retrieves the current gain levels for the external stereo
+ * inputs.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The current external stereo input gain
+ *                                  level.
+ *
+ * @retval      PMIC_SUCCESS         If the gain level was successfully
+ *                                   retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the gain level could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_stereo_in_gain(const PMIC_AUDIO_HANDLE handle,
+						 PMIC_AUDIO_STEREO_IN_GAIN *
+						 const gain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == extStereoIn.handle) &&
+	    (extStereoIn.handleState == HANDLE_IN_USE) &&
+	    (gain != (PMIC_AUDIO_STEREO_IN_GAIN *) NULL)) {
+		*gain = extStereoIn.inputGain;
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Set the output PGA gain level.
+ *
+ * This function sets the audio output PGA gain level.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The output PGA gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the gain level was successfully set.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or gain level was invalid.
+ * @retval      PMIC_ERROR           If the gain level could not be set.
+ */
+PMIC_STATUS pmic_audio_output_set_pgaGain(const PMIC_AUDIO_HANDLE handle,
+					  const PMIC_AUDIO_OUTPUT_PGA_GAIN gain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = 0;
+	unsigned int reg_gain;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (!((gain >= OUTPGA_GAIN_MINUS_33DB)
+	      && (gain <= OUTPGA_GAIN_PLUS_6DB))) {
+		rc = PMIC_NOT_SUPPORTED;
+		pr_debug("output set PGA gain - wrong gain value\n");
+	} else {
+		reg_gain = gain + 2;
+		if ((handle == extStereoIn.handle) &&
+		    (extStereoIn.handleState == HANDLE_IN_USE)) {
+			reg_mask = SET_BITS(regAUDIO_RX_1, ARXIN, 15) |
+			    SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+			reg_write = SET_BITS(regAUDIO_RX_1, ARXIN, reg_gain) |
+			    SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		} else if ((handle == vCodec.handle) &&
+			   (vCodec.handleState == HANDLE_IN_USE)) {
+			reg_mask = SET_BITS(regAUDIO_RX_1, PGARX, 15);
+			reg_write = SET_BITS(regAUDIO_RX_1, PGARX, reg_gain);
+		} else if ((handle == stDAC.handle) &&
+			   (stDAC.handleState == HANDLE_IN_USE)) {
+			reg_mask = SET_BITS(regAUDIO_RX_1, PGAST, 15);
+			reg_write = SET_BITS(regAUDIO_RX_1, PGAST, reg_gain);
+		}
+
+		if (reg_mask == 0) {
+
+		} else {
+			rc = pmic_write_reg(REG_AUDIO_RX_1,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Output PGA gains set\n");
+
+				if (handle == stDAC.handle) {
+					audioOutput.stDacoutputPGAGain = gain;
+				} else if (handle == vCodec.handle) {
+					audioOutput.vCodecoutputPGAGain = gain;
+				} else {
+					audioOutput.extStereooutputPGAGain =
+					    gain;
+				}
+			} else {
+				pr_debug
+				    ("Error writing PGA gains to register\n");
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the output PGA gain level.
+ *
+ * This function retrieves the current audio output PGA gain level.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The current output PGA gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the gain level was successfully
+ *                                   retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the gain level could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_pgaGain(const PMIC_AUDIO_HANDLE handle,
+					  PMIC_AUDIO_OUTPUT_PGA_GAIN *
+					  const gain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (gain != (PMIC_AUDIO_OUTPUT_PGA_GAIN *) NULL) {
+		if ((handle == extStereoIn.handle) &&
+		    (extStereoIn.handleState == HANDLE_IN_USE)) {
+			*gain = audioOutput.extStereooutputPGAGain;
+			rc = PMIC_SUCCESS;
+		} else if ((handle == vCodec.handle) &&
+			   (vCodec.handleState == HANDLE_IN_USE)) {
+			*gain = audioOutput.vCodecoutputPGAGain;
+			rc = PMIC_SUCCESS;
+		} else if ((handle == stDAC.handle) &&
+			   (stDAC.handleState == HANDLE_IN_USE)) {
+			*gain = audioOutput.stDacoutputPGAGain;
+			rc = PMIC_SUCCESS;
+		} else {
+			rc = PMIC_PARAMETER_ERROR;
+		}
+	} else {
+		rc = PMIC_PARAMETER_ERROR;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Enable the output mixer.
+ *
+ * This function enables the output mixer for the audio stream that
+ * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or
+ * the external stereo inputs).
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the mixer was successfully enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the mixer could not be enabled.
+ */
+PMIC_STATUS pmic_audio_output_enable_mixer(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask_mix = 0;
+	unsigned int reg_write_mix = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) {
+		reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 1);
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1);
+	} else if ((handle == vCodec.handle) &&
+		   (vCodec.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 1);
+		audioOutput.vCodecOut = VCODEC_MIXER_OUT;
+
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1);
+	} else if ((handle == extStereoIn.handle) &&
+		   (extStereoIn.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+	}
+
+	if (reg_mask == 0) {
+
+	} else {
+		rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+
+			rc = pmic_write_reg(REG_AUDIO_RX_0,
+					    reg_write_mix, reg_mask_mix);
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Output PGA mixers enabled\n");
+				rc = PMIC_SUCCESS;
+			}
+
+		} else {
+			pr_debug("Error writing mixer enable to register\n");
+		}
+
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Disable the output mixer.
+ *
+ * This function disables the output mixer for the audio stream that
+ * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or
+ * the external stereo inputs).
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the mixer was successfully disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the mixer could not be disabled.
+ */
+PMIC_STATUS pmic_audio_output_disable_mixer(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+
+	unsigned int reg_mask_mix = 0;
+	unsigned int reg_write_mix = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+	if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) {
+		/*reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1);
+		   reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 0); */
+
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 0);
+	} else if ((handle == vCodec.handle) &&
+		   (vCodec.handleState == HANDLE_IN_USE)) {
+		reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 0);
+		audioOutput.vCodecOut = VCODEC_DIRECT_OUT;
+
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 0);
+	} else if ((handle == extStereoIn.handle) &&
+		   (extStereoIn.handleState == HANDLE_IN_USE)) {
+		/*reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		   reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0); */
+
+		reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+		reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+	}
+
+	if (reg_mask == 0) {
+
+	} else {
+		rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+
+			rc = pmic_write_reg(REG_AUDIO_RX_0,
+					    reg_write_mix, reg_mask_mix);
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Output PGA mixers disabled\n");
+			}
+		}
+	}
+	return rc;
+}
+
+/*!
+ * @brief Configure and enable the output balance amplifiers.
+ *
+ * This function configures and enables the output balance amplifiers.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   leftGain            The desired left channel gain level.
+ * @param   rightGain           The desired right channel gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the output balance amplifiers were
+ *                                   successfully configured and enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or gain levels were invalid.
+ * @retval      PMIC_ERROR           If the output balance amplifiers could not
+ *                                   be reconfigured or enabled.
+ */
+PMIC_STATUS pmic_audio_output_set_balance(const PMIC_AUDIO_HANDLE handle,
+					  const PMIC_AUDIO_OUTPUT_BALANCE_GAIN
+					  leftGain,
+					  const PMIC_AUDIO_OUTPUT_BALANCE_GAIN
+					  rightGain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask_ch = 0;
+	unsigned int reg_write_ch = 0;
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if (!((leftGain >= BAL_GAIN_MINUS_21DB) && (leftGain <= BAL_GAIN_0DB))) {
+		rc = PMIC_PARAMETER_ERROR;
+	} else if (!((rightGain >= BAL_GAIN_MINUS_21DB)
+		     && (rightGain <= BAL_GAIN_0DB))) {
+		rc = PMIC_PARAMETER_ERROR;
+	} else {
+		if (((handle == stDAC.handle) &&
+		     (stDAC.handleState == HANDLE_IN_USE)) ||
+		    ((handle == vCodec.handle) &&
+		     (vCodec.handleState == HANDLE_IN_USE)) ||
+		    ((handle == extStereoIn.handle) &&
+		     (extStereoIn.handleState == HANDLE_IN_USE))) {
+			/* In mc13783 only one channel can be attenuated wrt the other.
+			 * It is not possible to specify attenuation for both
+			 * This function will return an error if both channels
+			 * are required to be attenuated
+			 * The BALLR bit is set/reset depending on whether leftGain
+			 * or rightGain is specified*/
+			if ((rightGain == BAL_GAIN_0DB)
+			    && (leftGain == BAL_GAIN_0DB)) {
+				/* Nothing to be done */
+			} else if ((rightGain != BAL_GAIN_0DB)
+				   && (leftGain == BAL_GAIN_0DB)) {
+				/* Attenuate right channel */
+				reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7);
+				reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1);
+				reg_write =
+				    SET_BITS(regAUDIO_RX_1, BAL,
+					     (BAL_GAIN_0DB - rightGain));
+				/* The enum and the register values are reversed in order .. */
+				reg_write_ch =
+				    SET_BITS(regAUDIO_RX_1, BALLR, 0);
+				/* BALLR = 0 selects right channel for atten */
+			} else if ((rightGain == BAL_GAIN_0DB)
+				   && (leftGain != BAL_GAIN_0DB)) {
+				/* Attenuate left channel */
+
+				reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7);
+				reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1);
+				reg_write =
+				    SET_BITS(regAUDIO_RX_1, BAL,
+					     (BAL_GAIN_0DB - leftGain));
+				reg_write_ch =
+				    SET_BITS(regAUDIO_RX_1, BALLR, 1);
+				/* BALLR = 1 selects left channel for atten */
+			} else {
+				rc = PMIC_PARAMETER_ERROR;
+			}
+
+			if ((reg_mask == 0) || (reg_mask_ch == 0)) {
+
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_RX_1,
+						    reg_write_ch, reg_mask_ch);
+
+				if (rc == PMIC_SUCCESS) {
+					rc = pmic_write_reg(REG_AUDIO_RX_1,
+							    reg_write,
+							    reg_mask);
+
+					if (rc == PMIC_SUCCESS) {
+						pr_debug
+						    ("Output balance attenuation set\n");
+						audioOutput.balanceLeftGain =
+						    leftGain;
+						audioOutput.balanceRightGain =
+						    rightGain;
+					}
+				}
+			}
+		}
+	}
+	return rc;
+}
+
+/*!
+ * @brief Get the current output balance amplifier gain levels.
+ *
+ * This function retrieves the current output balance amplifier gain levels.
+ *
+ * @param   	handle              Device handle from pmic_audio_open() call.
+ * @param  	leftGain            The current left channel gain level.
+ * @param 	rightGain           The current right channel gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the output balance amplifier gain levels
+ *                                   were successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the output balance amplifier gain levels
+ *                                   could be retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_balance(const PMIC_AUDIO_HANDLE handle,
+					  PMIC_AUDIO_OUTPUT_BALANCE_GAIN *
+					  const leftGain,
+					  PMIC_AUDIO_OUTPUT_BALANCE_GAIN *
+					  const rightGain)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((((handle == stDAC.handle) &&
+	      (stDAC.handleState == HANDLE_IN_USE)) ||
+	     ((handle == vCodec.handle) &&
+	      (vCodec.handleState == HANDLE_IN_USE)) ||
+	     ((handle == extStereoIn.handle) &&
+	      (extStereoIn.handleState == HANDLE_IN_USE))) &&
+	    ((leftGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL) &&
+	     (rightGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL))) {
+		*leftGain = audioOutput.balanceLeftGain;
+		*rightGain = audioOutput.balanceRightGain;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Configure and enable the output mono adder.
+ *
+ * This function configures and enables the output mono adder.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   mode                The desired mono adder operating mode.
+ *
+ * @retval      PMIC_SUCCESS         If the mono adder was successfully
+ *                                   configured and enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or mono adder mode was
+ *                                   invalid.
+ * @retval      PMIC_ERROR           If the mono adder could not be reconfigured
+ *                                   or enabled.
+ */
+PMIC_STATUS pmic_audio_output_enable_mono_adder(const PMIC_AUDIO_HANDLE handle,
+						const PMIC_AUDIO_MONO_ADDER_MODE
+						mode)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_write = 0;
+	unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if ((mode >= MONO_ADDER_OFF) && (mode <= STEREO_OPPOSITE_PHASE)) {
+		if (((handle == stDAC.handle) &&
+		     (stDAC.handleState == HANDLE_IN_USE)) ||
+		    ((handle == vCodec.handle) &&
+		     (vCodec.handleState == HANDLE_IN_USE)) ||
+		    ((handle == extStereoIn.handle) &&
+		     (extStereoIn.handleState == HANDLE_IN_USE))) {
+			if (mode == MONO_ADDER_OFF) {
+				reg_write = SET_BITS(regAUDIO_RX_1, MONO, 0);
+			} else if (mode == MONO_ADD_LEFT_RIGHT) {
+				reg_write = SET_BITS(regAUDIO_RX_1, MONO, 2);
+			} else if (mode == MONO_ADD_OPPOSITE_PHASE) {
+				reg_write = SET_BITS(regAUDIO_RX_1, MONO, 3);
+			} else {	/* stereo opposite */
+
+				reg_write = SET_BITS(regAUDIO_RX_1, MONO, 1);
+			}
+
+			rc = pmic_write_reg(REG_AUDIO_RX_1,
+					    reg_write, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				pr_debug("Output mono adder mode set\n");
+
+			}
+
+		} else {
+			rc = PMIC_PARAMETER_ERROR;
+		}
+	} else {
+		rc = PMIC_PARAMETER_ERROR;
+	}
+	return rc;
+}
+
+/*!
+ * @brief Disable the output mono adder.
+ *
+ * This function disables the output mono adder.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the mono adder was successfully
+ *                                   disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the mono adder could not be disabled.
+ */
+PMIC_STATUS pmic_audio_output_disable_mono_adder(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_write = 0;
+	const unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	if (((handle == stDAC.handle) &&
+	     (stDAC.handleState == HANDLE_IN_USE)) ||
+	    ((handle == vCodec.handle) &&
+	     (vCodec.handleState == HANDLE_IN_USE)) ||
+	    ((handle == extStereoIn.handle) &&
+	     (extStereoIn.handleState == HANDLE_IN_USE))) {
+		rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask);
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Configure the mono adder output gain level.
+ *
+ * This function configures the mono adder output amplifier gain level.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The desired output gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the mono adder output amplifier gain
+ *                                   level was successfully set.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or gain level was invalid.
+ * @retval      PMIC_ERROR           If the mono adder output amplifier gain
+ *                                   level could not be reconfigured.
+ */
+PMIC_STATUS pmic_audio_output_set_mono_adder_gain(const PMIC_AUDIO_HANDLE
+						  handle,
+						  const
+						  PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN
+						  gain)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+}
+
+/*!
+ * @brief Get the current mono adder output gain level.
+ *
+ * This function retrieves the current mono adder output amplifier gain level.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   gain                The current output gain level.
+ *
+ * @retval      PMIC_SUCCESS         If the mono adder output amplifier gain
+ *                                   level was successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the mono adder output amplifier gain
+ *                                   level could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_mono_adder_gain(const PMIC_AUDIO_HANDLE
+						  handle,
+						  PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN
+						  * const gain)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+	return rc;
+}
+
+/*!
+ * @brief Set various audio output section options.
+ *
+ * This function sets one or more audio output section configuration
+ * options. The currently supported options include whether to disable
+ * the non-inverting mono speaker output, enabling the loudspeaker common
+ * bias circuit, enabling detection of headset insertion/removal, and
+ * whether to automatically disable the headset amplifiers when a headset
+ * insertion/removal has been detected.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   config              The desired audio output section
+ *                                  configuration options to be set.
+ *
+ * @retval      PMIC_SUCCESS         If the desired configuration options were
+ *                                   all successfully set.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or configuration options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the desired configuration options
+ *                                   could not be set.
+ */
+PMIC_STATUS pmic_audio_output_set_config(const PMIC_AUDIO_HANDLE handle,
+					 const PMIC_AUDIO_OUTPUT_CONFIG config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (((handle == stDAC.handle) &&
+	     (stDAC.handleState == HANDLE_IN_USE)) ||
+	    ((handle == vCodec.handle) &&
+	     (vCodec.handleState == HANDLE_IN_USE)) ||
+	    ((handle == extStereoIn.handle) &&
+	     (extStereoIn.handleState == HANDLE_IN_USE))) {
+		if (config & MONO_SPEAKER_INVERT_OUT_ONLY) {
+			/* If this is one of the parameters */
+			rc = PMIC_NOT_SUPPORTED;
+		} else {
+			if (config & MONO_LOUDSPEAKER_COMMON_BIAS) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 1);
+			}
+			if (config & HEADSET_DETECT_ENABLE) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, HSDETEN, 1);
+			}
+			if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+			}
+
+			if (reg_mask == 0) {
+				rc = PMIC_PARAMETER_ERROR;
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_RX_0,
+						    reg_write, reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					pr_debug("Output config set\n");
+					audioOutput.config |= config;
+
+				}
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Clear various audio output section options.
+ *
+ * This function clears one or more audio output section configuration
+ * options.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param   config              The desired audio output section
+ *                                  configuration options to be cleared.
+ *
+ * @retval      PMIC_SUCCESS         If the desired configuration options were
+ *                                   all successfully cleared.
+ * @retval      PMIC_PARAMETER_ERROR If the handle or configuration options
+ *                                   were invalid.
+ * @retval      PMIC_ERROR           If the desired configuration options
+ *                                   could not be cleared.
+ */
+PMIC_STATUS pmic_audio_output_clear_config(const PMIC_AUDIO_HANDLE handle,
+					   const PMIC_AUDIO_OUTPUT_CONFIG
+					   config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	/*unsigned int reg_write_RX = 0;
+	   unsigned int reg_mask_RX  = 0;
+	   unsigned int reg_write_TX = 0;
+	   unsigned int reg_mask_TX  = 0; */
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (((handle == stDAC.handle) &&
+	     (stDAC.handleState == HANDLE_IN_USE)) ||
+	    ((handle == vCodec.handle) &&
+	     (vCodec.handleState == HANDLE_IN_USE)) ||
+	    ((handle == extStereoIn.handle) &&
+	     (extStereoIn.handleState == HANDLE_IN_USE))) {
+		if (config & MONO_SPEAKER_INVERT_OUT_ONLY) {
+			/* If this is one of the parameters */
+			rc = PMIC_NOT_SUPPORTED;
+		} else {
+			if (config & MONO_LOUDSPEAKER_COMMON_BIAS) {
+				reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1);
+				reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 0);
+			}
+
+			if (config & HEADSET_DETECT_ENABLE) {
+				reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, HSDETEN, 0);
+			}
+
+			if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) {
+				reg_mask |=
+				    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1);
+				reg_write |=
+				    SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 0);
+			}
+
+			if (reg_mask == 0) {
+				rc = PMIC_PARAMETER_ERROR;
+			} else {
+				rc = pmic_write_reg(REG_AUDIO_RX_0,
+						    reg_write, reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					pr_debug("Output config cleared\n");
+					audioOutput.config &= ~config;
+
+				}
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Get the current audio output section options.
+ *
+ * This function retrieves the current audio output section configuration
+ * option settings.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ * @param  config              The current audio output section
+ *                                  configuration option settings.
+ *
+ * @retval      PMIC_SUCCESS         If the current configuration options were
+ *                                   successfully retrieved.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the current configuration options
+ *                                   could not be retrieved.
+ */
+PMIC_STATUS pmic_audio_output_get_config(const PMIC_AUDIO_HANDLE handle,
+					 PMIC_AUDIO_OUTPUT_CONFIG *
+					 const config)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Use a critical section to ensure a consistent hardware state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((((handle == stDAC.handle) &&
+	      (stDAC.handleState == HANDLE_IN_USE)) ||
+	     ((handle == vCodec.handle) &&
+	      (vCodec.handleState == HANDLE_IN_USE)) ||
+	     ((handle == extStereoIn.handle) &&
+	      (extStereoIn.handleState == HANDLE_IN_USE))) &&
+	    (config != (PMIC_AUDIO_OUTPUT_CONFIG *) NULL)) {
+		*config = audioOutput.config;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * @brief Enable the phantom ground circuit that is used to help identify
+ *        the type of headset that has been inserted.
+ *
+ * This function enables the phantom ground circuit that is used to help
+ * identify the type of headset (e.g., stereo or mono) that has been inserted.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the phantom ground circuit was
+ *                                   successfully enabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the phantom ground circuit could not
+ *                                   be enabled.
+ */
+PMIC_STATUS pmic_audio_output_enable_phantom_ground()
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	rc = pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask);
+	if (rc == PMIC_SUCCESS) {
+		pr_debug("Phantom ground enabled\n");
+
+	}
+	return rc;
+}
+
+/*!
+ * @brief Disable the phantom ground circuit that is used to help identify
+ *        the type of headset that has been inserted.
+ *
+ * This function disables the phantom ground circuit that is used to help
+ * identify the type of headset (e.g., stereo or mono) that has been inserted.
+ *
+ * @param   handle              Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the phantom ground circuit was
+ *                                   successfully disabled.
+ * @retval      PMIC_PARAMETER_ERROR If the handle was invalid.
+ * @retval      PMIC_ERROR           If the phantom ground circuit could not
+ *                                   be disabled.
+ */
+PMIC_STATUS pmic_audio_output_disable_phantom_ground()
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1);
+
+	/* No critical section required here since we are not updating any
+	 * global data.
+	 */
+
+	rc = pmic_write_reg(REG_AUDIO_RX_0, 1, reg_mask);
+	if (rc == PMIC_SUCCESS) {
+		pr_debug("Phantom ground disabled\n");
+
+	}
+	return rc;
+}
+
+/*@}*/
+
+/**************************************************************************
+ * Static functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name Audio Driver Internal Support Functions
+ * These non-exported internal functions are used to support the functionality
+ * of the exported audio APIs.
+ */
+/*@{*/
+
+/*!
+ * @brief Enables the 5.6V boost for the microphone bias 2 circuit.
+ *
+ * This function enables the switching regulator SW3 and configures it to
+ * provide the 5.6V boost that is required for driving the microphone bias 2
+ * circuit when using a 5-pole jack configuration (which is the case for the
+ * Sphinx board).
+ *
+ * @retval      PMIC_SUCCESS         The 5.6V boost was successfully enabled.
+ * @retval      PMIC_ERROR           Failed to enable the 5.6V boost.
+ */
+/*
+static PMIC_STATUS pmic_audio_mic_boost_enable(void)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+
+	return rc;
+}
+*/
+/*!
+ * @brief Disables the 5.6V boost for the microphone bias 2 circuit.
+ *
+ * This function disables the switching regulator SW3 to turn off the 5.6V
+ * boost for the microphone bias 2 circuit.
+ *
+ * @retval      PMIC_SUCCESS         The 5.6V boost was successfully disabled.
+ * @retval      PMIC_ERROR           Failed to disable the 5.6V boost.
+ */
+/*
+static PMIC_STATUS pmic_audio_mic_boost_disable(void)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+
+	return rc;
+}
+*/
+
+/*!
+ * @brief Free a device handle previously acquired by calling pmic_audio_open().
+ *
+ * Terminate further access to the PMIC audio hardware that was previously
+ * acquired by calling pmic_audio_open(). This now allows another thread to
+ * successfully call pmic_audio_open() to gain access.
+ *
+ * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as
+ * any associated audio input/output components that are no longer required.
+ *
+ * Also note that this function should only be called with the mutex already
+ * acquired.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the close request was successful.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ */
+static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+
+	/* Match up the handle to the audio device and then close it. */
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		/* Also shutdown the Stereo DAC hardware. The simplest way to
+		 * do this is to simply call pmic_audio_reset_device() which will
+		 * restore the ST_DAC register to it's initial power-on state.
+		 *
+		 * This will also shutdown the audio output section if no one
+		 * else is still using it.
+		 */
+		rc = pmic_audio_reset_device(stDAC.handle);
+
+		if (rc == PMIC_SUCCESS) {
+			stDAC.handle = AUDIO_HANDLE_NULL;
+			stDAC.handleState = HANDLE_FREE;
+		}
+	} else if ((handle == vCodec.handle) &&
+		   (vCodec.handleState == HANDLE_IN_USE)) {
+		/* Also shutdown the Voice CODEC and audio input hardware. The
+		 * simplest way to do this is to simply call pmic_audio_reset_device()
+		 * which will restore the AUD_CODEC register to it's initial
+		 * power-on state.
+		 *
+		 * This will also shutdown the audio output section if no one
+		 * else is still using it.
+		 */
+		rc = pmic_audio_reset_device(vCodec.handle);
+		if (rc == PMIC_SUCCESS) {
+			vCodec.handle = AUDIO_HANDLE_NULL;
+			vCodec.handleState = HANDLE_FREE;
+		}
+	} else if ((handle == extStereoIn.handle) &&
+		   (extStereoIn.handleState == HANDLE_IN_USE)) {
+
+		/* Call pmic_audio_reset_device() here to shutdown the audio output
+		 * section if no one else is still using it.
+		 */
+		rc = pmic_audio_reset_device(extStereoIn.handle);
+
+		if (rc == PMIC_SUCCESS) {
+			extStereoIn.handle = AUDIO_HANDLE_NULL;
+			extStereoIn.handleState = HANDLE_FREE;
+		}
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Reset the selected audio hardware control registers to their
+ *        power on state.
+ *
+ * This resets all of the audio hardware control registers currently
+ * associated with the device handle back to their power on states. For
+ * example, if the handle is associated with the Stereo DAC and a
+ * specific output port and output amplifiers, then this function will
+ * reset all of those components to their initial power on state.
+ *
+ * This function can only be called if the mutex has already been acquired.
+ *
+ * @param   handle          Device handle from pmic_audio_open() call.
+ *
+ * @retval      PMIC_SUCCESS         If the reset operation was successful.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ * @retval      PMIC_ERROR           If the reset was unsuccessful.
+ */
+static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	unsigned int reg_mask = 0;
+
+	if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) {
+		/* Also shutdown the audio output section if nobody else is using it.
+		   if ((vCodec.handleState == HANDLE_FREE) &&
+		   (extStereoIn.handleState == HANDLE_FREE))
+		   {
+		   pmic_write_reg(REG_RX_AUD_AMPS, RESET_RX_AUD_AMPS,
+		   REG_FULLMASK);
+		   } */
+
+		rc = pmic_write_reg(REG_AUDIO_STEREO_DAC,
+				    RESET_ST_DAC, REG_FULLMASK);
+
+		if (rc == PMIC_SUCCESS) {
+			rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+					    RESET_SSI_NETWORK,
+					    REG_SSI_STDAC_MASK);
+			if (rc == PMIC_SUCCESS) {
+				/* Also reset the driver state information to match. Note that we
+				 * keep the device handle and event callback settings unchanged
+				 * since these don't affect the actual hardware and we rely on
+				 * the user to explicitly close the handle or deregister callbacks
+				 */
+				stDAC.busID = AUDIO_DATA_BUS_1;
+				stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE;
+				stDAC.protocol_set = false;
+				stDAC.masterSlave = BUS_MASTER_MODE;
+				stDAC.numSlots = USE_2_TIMESLOTS;
+				stDAC.clockIn = CLOCK_IN_CLIA;
+				stDAC.samplingRate = STDAC_RATE_44_1_KHZ;
+				stDAC.clockFreq = STDAC_CLI_13MHZ;
+				stDAC.invert = NO_INVERT;
+				stDAC.timeslot = USE_TS0_TS1;
+				stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0;
+
+			}
+		}
+	} else if ((handle == vCodec.handle)
+		   && (vCodec.handleState == HANDLE_IN_USE)) {
+		/* Disable the audio input section when disabling the Voice CODEC. */
+		pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK);
+
+		rc = pmic_write_reg(REG_AUDIO_CODEC,
+				    RESET_AUD_CODEC, REG_FULLMASK);
+
+		if (rc == PMIC_SUCCESS) {
+			rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK,
+					    RESET_SSI_NETWORK,
+					    REG_SSI_VCODEC_MASK);
+			if (rc == PMIC_SUCCESS) {
+
+				/* Also reset the driver state information to match. Note that we
+				 * keep the device handle and event callback settings unchanged
+				 * since these don't affect the actual hardware and we rely on
+				 * the user to explicitly close the handle or deregister callbacks
+				 */
+				vCodec.busID = AUDIO_DATA_BUS_2;
+				vCodec.protocol = NETWORK_MODE;
+				vCodec.protocol_set = false;
+				vCodec.masterSlave = BUS_SLAVE_MODE;
+				vCodec.numSlots = USE_4_TIMESLOTS;
+				vCodec.clockIn = CLOCK_IN_CLIB;
+				vCodec.samplingRate = VCODEC_RATE_8_KHZ;
+				vCodec.clockFreq = VCODEC_CLI_13MHZ;
+				vCodec.invert = NO_INVERT;
+				vCodec.timeslot = USE_TS0;
+				vCodec.config =
+				    INPUT_HIGHPASS_FILTER |
+				    OUTPUT_HIGHPASS_FILTER;
+
+			}
+		}
+
+	} else if ((handle == extStereoIn.handle) &&
+		   (extStereoIn.handleState == HANDLE_IN_USE)) {
+		/* Disable the Ext stereo Amplifier and disable it as analog mixer input */
+		reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		pmic_write_reg(REG_AUDIO_RX_1, 0, reg_mask);
+
+		reg_mask = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+		pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask);
+
+		/* We don't need to reset any other registers for this case. */
+		rc = PMIC_SUCCESS;
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief Deregister the callback function and event mask currently associated
+ *        with an audio device handle.
+ *
+ * This function deregisters any existing callback function and event mask for
+ * the given audio device handle. This is done by either calling the
+ * pmic_audio_clear_callback() API or by closing the device handle.
+ *
+ * Note that this function should only be called with the mutex already
+ * acquired. We will also acquire the spinlock here to prevent possible
+ * race conditions with the interrupt handler.
+ *
+ * @param[in]   callback            The current event callback function pointer.
+ * @param[in]   eventMask           The current audio event mask.
+ *
+ * @retval      PMIC_SUCCESS         If the callback function and event mask
+ *                                   were both successfully deregistered.
+ * @retval      PMIC_ERROR           If either the callback function or the
+ *                                   event mask was not successfully
+ *                                   deregistered.
+ */
+
+static PMIC_STATUS pmic_audio_deregister(void *callback,
+					 PMIC_AUDIO_EVENTS * const eventMask)
+{
+	unsigned long flags;
+	pmic_event_callback_t eventNotify;
+	PMIC_STATUS rc = PMIC_SUCCESS;
+
+	/* Deregister each of the PMIC events that we had previously
+	 * registered for by calling pmic_event_subscribe().
+	 */
+	if (*eventMask & (HEADSET_DETECTED)) {
+		/* We need to deregister for the A1 amplifier interrupt. */
+		eventNotify.func = callback;
+		eventNotify.param = (void *)(CORE_EVENT_HSDETI);
+		if (pmic_event_unsubscribe(EVENT_HSDETI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			*eventMask &= ~(HEADSET_DETECTED);
+			pr_debug("Deregistered for EVENT_HSDETI\n");
+		} else {
+			rc = PMIC_ERROR;
+		}
+	}
+
+	if (*eventMask & (HEADSET_STEREO)) {
+		/* We need to deregister for the A1 amplifier interrupt. */
+		eventNotify.func = callback;
+		eventNotify.param = (void *)(CORE_EVENT_HSLI);
+		if (pmic_event_unsubscribe(EVENT_HSLI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			*eventMask &= ~(HEADSET_STEREO);
+			pr_debug("Deregistered for EVENT_HSLI\n");
+		} else {
+			rc = PMIC_ERROR;
+		}
+	}
+	if (*eventMask & (HEADSET_THERMAL_SHUTDOWN)) {
+		/* We need to deregister for the A1 amplifier interrupt. */
+		eventNotify.func = callback;
+		eventNotify.param = (void *)(CORE_EVENT_ALSPTHI);
+		if (pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			*eventMask &= ~(HEADSET_THERMAL_SHUTDOWN);
+			pr_debug("Deregistered for EVENT_ALSPTHI\n");
+		} else {
+			rc = PMIC_ERROR;
+		}
+	}
+	if (*eventMask & (HEADSET_SHORT_CIRCUIT)) {
+		/* We need to deregister for the A1 amplifier interrupt. */
+		eventNotify.func = callback;
+		eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI);
+		if (pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			*eventMask &= ~(HEADSET_SHORT_CIRCUIT);
+			pr_debug("Deregistered for EVENT_AHSSHORTI\n");
+		} else {
+			rc = PMIC_ERROR;
+		}
+	}
+
+	if (rc == PMIC_SUCCESS) {
+		/* We need to grab the spinlock here to create a critical section to
+		 * avoid any possible race conditions with the interrupt handler
+		 */
+		spin_lock_irqsave(&lock, flags);
+
+		/* Restore the initial reset values for the callback function
+		 * and event mask parameters. This should be NULL and zero,
+		 * respectively.
+		 */
+		callback = NULL;
+		*eventMask = 0;
+
+		/* Exit the critical section. */
+		spin_unlock_irqrestore(&lock, flags);
+	}
+
+	return rc;
+}
+
+/*!
+ * @brief enable/disable fm output.
+ *
+ * @param[in]   enable            true to enable false to disable
+ */
+PMIC_STATUS pmic_audio_fm_output_enable(bool enable)
+{
+	unsigned int reg_mask = 0;
+	unsigned int reg_write = 0;
+	PMIC_STATUS rc = PMIC_PARAMETER_ERROR;
+	if (enable) {
+		pmic_audio_antipop_enable(ANTI_POP_RAMP_FAST);
+		reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1);
+		reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 1);
+
+		reg_mask |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1);
+
+		reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+
+		reg_mask |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 0);
+	} else {
+		reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1);
+		reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 0);
+	}
+	rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask);
+	if (rc != PMIC_SUCCESS)
+		return rc;
+	if (enable) {
+		reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+	} else {
+		reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1);
+		reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0);
+	}
+	rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask);
+	return rc;
+}
+
+/*@}*/
+
+/**************************************************************************
+ * Module initialization and termination functions.
+ *
+ * Note that if this code is compiled into the kernel, then the
+ * module_init() function will be called within the device_initcall()
+ * group.
+ **************************************************************************
+ */
+
+/*!
+ * @name Audio Driver Loading/Unloading Functions
+ * These non-exported internal functions are used to support the audio
+ * device driver initialization and de-initialization operations.
+ */
+/*@{*/
+
+/*!
+ * @brief This is the audio device driver initialization function.
+ *
+ * This function is called by the kernel when this device driver is first
+ * loaded.
+ */
+static int __init mc13783_pmic_audio_init(void)
+{
+	printk(KERN_INFO "PMIC Audio driver loading...\n");
+
+	return 0;
+}
+
+/*!
+ * @brief This is the audio device driver de-initialization function.
+ *
+ * This function is called by the kernel when this device driver is about
+ * to be unloaded.
+ */
+static void __exit mc13783_pmic_audio_exit(void)
+{
+	printk(KERN_INFO "PMIC Audio driver unloading...\n");
+
+	/* Close all device handles that are still open. This will also
+	 * deregister any callbacks that may still be active.
+	 */
+	if (stDAC.handleState == HANDLE_IN_USE) {
+		pmic_audio_close(stDAC.handle);
+	}
+	if (vCodec.handleState == HANDLE_IN_USE) {
+		pmic_audio_close(vCodec.handle);
+	}
+	if (extStereoIn.handleState == HANDLE_IN_USE) {
+		pmic_audio_close(extStereoIn.handle);
+	}
+
+	/* Explicitly reset all of the audio registers so that there is no
+	 * possibility of leaving the  audio hardware in a state
+	 * where it can cause problems if there is no device driver loaded.
+	 */
+	pmic_write_reg(REG_AUDIO_STEREO_DAC, RESET_ST_DAC, REG_FULLMASK);
+	pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC, REG_FULLMASK);
+	pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK);
+	pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK, REG_FULLMASK);
+	pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0, REG_FULLMASK);
+	pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1, REG_FULLMASK);
+}
+
+/*@}*/
+
+/*
+ * Module entry points and description information.
+ */
+
+module_init(mc13783_pmic_audio_init);
+module_exit(mc13783_pmic_audio_exit);
+
+MODULE_DESCRIPTION("PMIC - mc13783 ADC driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_battery.c b/drivers/mxc/pmic/mc13783/pmic_battery.c
new file mode 100644
index 000000000000..775ebe77a5c0
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_battery.c
@@ -0,0 +1,1221 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_battery.c
+ * @brief This is the main file of PMIC(mc13783) Battery driver.
+ *
+ * @ingroup PMIC_BATTERY
+ */
+
+/*
+ * Includes
+ */
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+
+#include <linux/pmic_battery.h>
+#include <linux/pmic_adc.h>
+#include <linux/pmic_status.h>
+
+#include "pmic_battery_defs.h"
+
+#include <mach/pmic_power.h>
+#ifdef CONFIG_MXC_HWEVENT
+#include <mach/hw_events.h>
+#endif
+
+static int pmic_battery_major;
+
+/*!
+ * Number of users waiting in suspendq
+ */
+static int swait = 0;
+
+/*!
+ * To indicate whether any of the battery devices are suspending
+ */
+static int suspend_flag = 0;
+
+/*!
+ * The suspendq is used to block application calls
+ */
+static wait_queue_head_t suspendq;
+
+static struct class *pmic_battery_class;
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_batt_enable_charger);
+EXPORT_SYMBOL(pmic_batt_disable_charger);
+EXPORT_SYMBOL(pmic_batt_set_charger);
+EXPORT_SYMBOL(pmic_batt_get_charger_setting);
+EXPORT_SYMBOL(pmic_batt_get_charge_current);
+EXPORT_SYMBOL(pmic_batt_enable_eol);
+EXPORT_SYMBOL(pmic_batt_bp_enable_eol);
+EXPORT_SYMBOL(pmic_batt_disable_eol);
+EXPORT_SYMBOL(pmic_batt_set_out_control);
+EXPORT_SYMBOL(pmic_batt_set_threshold);
+EXPORT_SYMBOL(pmic_batt_led_control);
+EXPORT_SYMBOL(pmic_batt_set_reverse_supply);
+EXPORT_SYMBOL(pmic_batt_set_unregulated);
+EXPORT_SYMBOL(pmic_batt_set_5k_pull);
+EXPORT_SYMBOL(pmic_batt_event_subscribe);
+EXPORT_SYMBOL(pmic_batt_event_unsubscribe);
+
+static DECLARE_MUTEX(count_mutex);	/* open count mutex */
+static int open_count;		/* open count for device file */
+
+/*!
+ * Callback function for events, we want on MGN board
+ */
+static void callback_chg_detect(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	t_sensor_bits sensor;
+	struct mxc_hw_event event = { HWE_BAT_CHARGER_PLUG, 0 };
+
+	pr_debug("In callback_chg_detect\n");
+
+	/* get sensor values */
+	pmic_get_sensors(&sensor);
+
+	pr_debug("Callback, charger detect:%d\n", sensor.sense_chgdets);
+
+	if (sensor.sense_chgdets)
+		event.args = 1;
+	else
+		event.args = 0;
+	/* send hardware event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+static void callback_low_battery(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	struct mxc_hw_event event = { HWE_BAT_BATTERY_LOW, 0 };
+
+	pr_debug("In callback_low_battery\n");
+	/* send hardware event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+static void callback_power_fail(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	struct mxc_hw_event event = { HWE_BAT_POWER_FAILED, 0 };
+
+	pr_debug("In callback_power_fail\n");
+	/* send hardware event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+static void callback_chg_overvoltage(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	struct mxc_hw_event event = { HWE_BAT_CHARGER_OVERVOLTAGE, 0 };
+
+	pr_debug("In callback_chg_overvoltage\n");
+	/* send hardware event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+static void callback_chg_full(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	t_sensor_bits sensor;
+	struct mxc_hw_event event = { HWE_BAT_CHARGER_FULL, 0 };
+
+	pr_debug("In callback_chg_full\n");
+
+	/* disable charge function */
+	pmic_batt_disable_charger(BATT_MAIN_CHGR);
+
+	/* get charger sensor */
+	pmic_get_sensors(&sensor);
+
+	/* if did not detect the charger */
+	if (sensor.sense_chgdets)
+		return;
+	/* send hardware event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+/*!
+ * This is the suspend of power management for the pmic battery API.
+ * It suports SAVE and POWER_DOWN state.
+ *
+ * @param        pdev           the device
+ * @param        state          the state
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_battery_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+	unsigned int reg_value = 0;
+
+	suspend_flag = 1;
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, reg_value, PMIC_ALL_BITS));
+
+	return 0;
+};
+
+/*!
+ * This is the resume of power management for the pmic battery API.
+ * It suports RESTORE state.
+ *
+ * @param        pdev           the device
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_battery_resume(struct platform_device *pdev)
+{
+	suspend_flag = 0;
+	while (swait > 0) {
+		swait--;
+		wake_up_interruptible(&suspendq);
+	}
+
+	return 0;
+};
+
+/*!
+ * This function is used to start charging a battery. For different charger,
+ * different voltage and current range are supported. \n
+ *
+ *
+ * @param      chgr        Charger as defined in \b t_batt_charger.
+ * @param      c_voltage   Charging voltage.
+ * @param      c_current   Charging current.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_enable_charger(t_batt_charger chgr,
+				     unsigned char c_voltage,
+				     unsigned char c_current)
+{
+	unsigned int val, mask, reg;
+
+	val = 0;
+	mask = 0;
+	reg = 0;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	switch (chgr) {
+	case BATT_MAIN_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) |
+		    BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage);
+		mask = BITFMASK(MC13783_BATT_DAC_DAC) |
+		    BITFMASK(MC13783_BATT_DAC_V_DAC);
+		reg = REG_CHARGER;
+		break;
+
+	case BATT_CELL_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage) |
+		    BITFVAL(MC13783_BATT_DAC_COIN_CH_EN,
+			    MC13783_BATT_DAC_COIN_CH_EN_ENABLED);
+		mask = BITFMASK(MC13783_BATT_DAC_V_COIN) |
+		    BITFMASK(MC13783_BATT_DAC_COIN_CH_EN);
+		reg = REG_POWER_CONTROL_0;
+		break;
+
+	case BATT_TRCKLE_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current);
+		mask = BITFMASK(MC13783_BATT_DAC_TRCKLE);
+		reg = REG_CHARGER;
+		break;
+
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function turns off a charger.
+ *
+ * @param      chgr        Charger as defined in \b t_batt_charger.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_disable_charger(t_batt_charger chgr)
+{
+	unsigned int val, mask, reg;
+
+	val = 0;
+	mask = 0;
+	reg = 0;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+	switch (chgr) {
+	case BATT_MAIN_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_DAC, 0) |
+		    BITFVAL(MC13783_BATT_DAC_V_DAC, 0);
+		mask = BITFMASK(MC13783_BATT_DAC_DAC) |
+		    BITFMASK(MC13783_BATT_DAC_V_DAC);
+		reg = REG_CHARGER;
+		break;
+
+	case BATT_CELL_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_COIN_CH_EN,
+			      MC13783_BATT_DAC_COIN_CH_EN_DISABLED);
+		mask = BITFMASK(MC13783_BATT_DAC_COIN_CH_EN);
+		reg = REG_POWER_CONTROL_0;
+		break;
+
+	case BATT_TRCKLE_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_TRCKLE, 0);
+		mask = BITFMASK(MC13783_BATT_DAC_TRCKLE);
+		reg = REG_CHARGER;
+		break;
+
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to change the charger setting.
+ *
+ * @param      chgr        Charger as defined in \b t_batt_charger.
+ * @param      c_voltage   Charging voltage.
+ * @param      c_current   Charging current.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_set_charger(t_batt_charger chgr,
+				  unsigned char c_voltage,
+				  unsigned char c_current)
+{
+	unsigned int val, mask, reg;
+
+	val = 0;
+	mask = 0;
+	reg = 0;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	switch (chgr) {
+	case BATT_MAIN_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) |
+		    BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage);
+		mask = BITFMASK(MC13783_BATT_DAC_DAC) |
+		    BITFMASK(MC13783_BATT_DAC_V_DAC);
+		reg = REG_CHARGER;
+		break;
+
+	case BATT_CELL_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage);
+		mask = BITFMASK(MC13783_BATT_DAC_V_COIN);
+		reg = REG_POWER_CONTROL_0;
+		break;
+
+	case BATT_TRCKLE_CHGR:
+		val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current);
+		mask = BITFMASK(MC13783_BATT_DAC_TRCKLE);
+		reg = REG_CHARGER;
+		break;
+
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, val, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to retrive the charger setting.
+ *
+ * @param      chgr        Charger as defined in \b t_batt_charger.
+ * @param      c_voltage   Output parameter for charging voltage setting.
+ * @param      c_current   Output parameter for charging current setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_charger_setting(t_batt_charger chgr,
+					  unsigned char *c_voltage,
+					  unsigned char *c_current)
+{
+	unsigned int val, reg;
+
+	reg = 0;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	switch (chgr) {
+	case BATT_MAIN_CHGR:
+	case BATT_TRCKLE_CHGR:
+		reg = REG_CHARGER;
+		break;
+	case BATT_CELL_CHGR:
+		reg = REG_POWER_CONTROL_0;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &val, PMIC_ALL_BITS));
+
+	switch (chgr) {
+	case BATT_MAIN_CHGR:
+		*c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_DAC);;
+		*c_current = BITFEXT(val, MC13783_BATT_DAC_DAC);
+		break;
+
+	case BATT_CELL_CHGR:
+		*c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_COIN);
+		*c_current = 0;
+		break;
+
+	case BATT_TRCKLE_CHGR:
+		*c_voltage = 0;
+		*c_current = BITFEXT(val, MC13783_BATT_DAC_TRCKLE);
+		break;
+
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is retrives the main battery voltage.
+ *
+ * @param      b_voltage   Output parameter for voltage setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_batt_voltage(unsigned short *b_voltage)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+	channel = BATTERY_VOLTAGE;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*b_voltage = result[0];
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is retrives the main battery current.
+ *
+ * @param      b_current   Output parameter for current setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_batt_current(unsigned short *b_current)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	channel = BATTERY_CURRENT;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*b_current = result[0];
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is retrives the main battery temperature.
+ *
+ * @param      b_temper   Output parameter for temperature setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_batt_temperature(unsigned short *b_temper)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	channel = GEN_PURPOSE_AD5;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*b_temper = result[0];
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is retrives the main battery charging voltage.
+ *
+ * @param      c_voltage   Output parameter for charging voltage setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_charge_voltage(unsigned short *c_voltage)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	channel = CHARGE_VOLTAGE;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*c_voltage = result[0];
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is retrives the main battery charging current.
+ *
+ * @param      c_current   Output parameter for charging current setting.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_get_charge_current(unsigned short *c_current)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	channel = CHARGE_CURRENT;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*c_current = result[0];
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables End-of-Life comparator. Not supported on
+ * mc13783. Use pmic_batt_bp_enable_eol function.
+ *
+ * @param      threshold  End-of-Life threshold.
+ *
+ * @return     This function returns PMIC_UNSUPPORTED
+ */
+PMIC_STATUS pmic_batt_enable_eol(unsigned char threshold)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function enables End-of-Life comparator.
+ *
+ * @param      typical  Falling Edge Threshold threshold.
+ * 			@verbatim
+			BPDET	UVDET	LOBATL
+			____	_____   ___________
+			0	2.6	UVDET + 0.2
+			1	2.6	UVDET + 0.3
+			2	2.6	UVDET + 0.4
+			3	2.6	UVDET + 0.5
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_bp_enable_eol(t_bp_threshold typical)
+{
+	unsigned int val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN,
+		      MC13783_BATT_DAC_EOL_CMP_EN_ENABLE) |
+	    BITFVAL(MC13783_BATT_DAC_EOL_SEL, typical);
+	mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN) |
+	    BITFMASK(MC13783_BATT_DAC_EOL_SEL);
+
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables End-of-Life comparator.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_disable_eol(void)
+{
+	unsigned int val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN,
+		      MC13783_BATT_DAC_EOL_CMP_EN_DISABLE);
+	mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN);
+
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the output controls.
+ * It sets the FETOVRD and FETCTRL bits of mc13783
+ *
+ * @param        control        type of control.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_batt_set_out_control(t_control control)
+{
+	unsigned int val, mask;
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	switch (control) {
+	case CONTROL_HARDWARE:
+		val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 0) |
+		    BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0);
+		mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) |
+		    BITFMASK(MC13783_BATT_DAC_FETCTRL_EN);
+		break;
+	case CONTROL_BPFET_LOW:
+		val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) |
+		    BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0);
+		mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) |
+		    BITFMASK(MC13783_BATT_DAC_FETCTRL_EN);
+		break;
+	case CONTROL_BPFET_HIGH:
+		val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) |
+		    BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 1);
+		mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) |
+		    BITFMASK(MC13783_BATT_DAC_FETCTRL_EN);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets over voltage threshold.
+ *
+ * @param        threshold      value of over voltage threshold.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_batt_set_threshold(int threshold)
+{
+	unsigned int val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	if (threshold > BAT_THRESHOLD_MAX)
+		return PMIC_PARAMETER_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_OVCTRL, threshold);
+	mask = BITFMASK(MC13783_BATT_DAC_OVCTRL);
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function controls charge LED.
+ *
+ * @param      on   If on is ture, LED will be turned on,
+ *                  or otherwise, LED will be turned off.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_led_control(bool on)
+{
+	unsigned val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_LED_EN, on);
+	mask = BITFMASK(MC13783_BATT_DAC_LED_EN);
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets reverse supply mode.
+ *
+ * @param      enable     If enable is ture, reverse supply mode is enable,
+ *                        or otherwise, reverse supply mode is disabled.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_set_reverse_supply(bool enable)
+{
+	unsigned val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_REVERSE_SUPPLY, enable);
+	mask = BITFMASK(MC13783_BATT_DAC_REVERSE_SUPPLY);
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets unregulatored charging mode on main battery.
+ *
+ * @param      enable     If enable is ture, unregulated charging mode is
+ *                        enable, or otherwise, disabled.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_set_unregulated(bool enable)
+{
+	unsigned val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_UNREGULATED, enable);
+	mask = BITFMASK(MC13783_BATT_DAC_UNREGULATED);
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a 5K pull down at CHRGRAW.
+ * To be used in the dual path charging configuration.
+ *
+ * @param      enable     If enable is true, 5k pull down is
+ *                        enable, or otherwise, disabled.
+ *
+ * @return     This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_batt_set_5k_pull(bool enable)
+{
+	unsigned val, mask;
+
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	val = BITFVAL(MC13783_BATT_DAC_5K, enable);
+	mask = BITFMASK(MC13783_BATT_DAC_5K);
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to un/subscribe on battery event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ * @param        sub            define if Un/subscribe event.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS mc13783_battery_event(t_batt_event event, void *callback, bool sub)
+{
+	pmic_event_callback_t bat_callback;
+	type_event bat_event;
+
+	bat_callback.func = callback;
+	bat_callback.param = NULL;
+	switch (event) {
+	case BAT_IT_CHG_DET:
+		bat_event = EVENT_CHGDETI;
+		break;
+	case BAT_IT_CHG_OVERVOLT:
+		bat_event = EVENT_CHGOVI;
+		break;
+	case BAT_IT_CHG_REVERSE:
+		bat_event = EVENT_CHGREVI;
+		break;
+	case BAT_IT_CHG_SHORT_CIRCUIT:
+		bat_event = EVENT_CHGSHORTI;
+		break;
+	case BAT_IT_CCCV:
+		bat_event = EVENT_CCCVI;
+		break;
+	case BAT_IT_BELOW_THRESHOLD:
+		bat_event = EVENT_CHRGCURRI;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	if (sub == true) {
+		CHECK_ERROR(pmic_event_subscribe(bat_event, bat_callback));
+	} else {
+		CHECK_ERROR(pmic_event_unsubscribe(bat_event, bat_callback));
+	}
+	return 0;
+}
+
+/*!
+ * This function is used to subscribe on battery event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_batt_event_subscribe(t_batt_event event, void *callback)
+{
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	return mc13783_battery_event(event, callback, true);
+}
+
+/*!
+ * This function is used to un subscribe on battery event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_batt_event_unsubscribe(t_batt_event event, void *callback)
+{
+	if (suspend_flag == 1)
+		return PMIC_ERROR;
+
+	return mc13783_battery_event(event, callback, false);
+}
+
+/*!
+ * This function implements IOCTL controls on a PMIC Battery device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_battery_ioctl(struct inode *inode, struct file *file,
+			      unsigned int cmd, unsigned long arg)
+{
+	t_charger_setting *chgr_setting = NULL;
+	unsigned short c_current;
+	unsigned int bc_info;
+	t_eol_setting *eol_setting;
+
+	if (_IOC_TYPE(cmd) != 'p')
+		return -ENOTTY;
+
+	switch (cmd) {
+	case PMIC_BATT_CHARGER_CONTROL:
+		if ((chgr_setting = kmalloc(sizeof(t_charger_setting),
+					    GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(chgr_setting, (t_charger_setting *) arg,
+				   sizeof(t_charger_setting))) {
+			kfree(chgr_setting);
+			return -EFAULT;
+		}
+
+		if (chgr_setting->on != false) {
+			CHECK_ERROR_KFREE(pmic_batt_enable_charger
+					  (chgr_setting->chgr,
+					   chgr_setting->c_voltage,
+					   chgr_setting->c_current),
+					  (kfree(chgr_setting)));
+		} else {
+			CHECK_ERROR(pmic_batt_disable_charger
+				    (chgr_setting->chgr));
+		}
+
+		kfree(chgr_setting);
+		break;
+
+	case PMIC_BATT_SET_CHARGER:
+		if ((chgr_setting = kmalloc(sizeof(t_charger_setting),
+					    GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(chgr_setting, (t_charger_setting *) arg,
+				   sizeof(t_charger_setting))) {
+			kfree(chgr_setting);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_batt_set_charger(chgr_setting->chgr,
+							chgr_setting->c_voltage,
+							chgr_setting->
+							c_current),
+				  (kfree(chgr_setting)));
+
+		kfree(chgr_setting);
+		break;
+
+	case PMIC_BATT_GET_CHARGER:
+		if ((chgr_setting = kmalloc(sizeof(t_charger_setting),
+					    GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(chgr_setting, (t_charger_setting *) arg,
+				   sizeof(t_charger_setting))) {
+			kfree(chgr_setting);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_batt_get_charger_setting
+				  (chgr_setting->chgr, &chgr_setting->c_voltage,
+				   &chgr_setting->c_current),
+				  (kfree(chgr_setting)));
+		if (copy_to_user
+		    ((t_charger_setting *) arg, chgr_setting,
+		     sizeof(t_charger_setting))) {
+			return -EFAULT;
+		}
+
+		kfree(chgr_setting);
+		break;
+
+	case PMIC_BATT_GET_CHARGER_SENSOR:
+		{
+			t_sensor_bits sensor;
+			pmic_get_sensors(&sensor);
+			if (copy_to_user
+			    ((unsigned int *)arg, &sensor.sense_chgdets,
+			     sizeof(unsigned int)))
+				return -EFAULT;
+
+			break;
+		}
+	case PMIC_BATT_GET_BATTERY_VOLTAGE:
+		CHECK_ERROR(pmic_batt_get_batt_voltage(&c_current));
+		bc_info = (unsigned int)c_current * 2300 / 1023 + 2400;
+		if (copy_to_user((unsigned int *)arg, &bc_info,
+				 sizeof(unsigned int)))
+			return -EFAULT;
+
+		break;
+
+	case PMIC_BATT_GET_BATTERY_CURRENT:
+		CHECK_ERROR(pmic_batt_get_batt_current(&c_current));
+		bc_info = (unsigned int)c_current * 5750 / 1023;
+		if (copy_to_user((unsigned int *)arg, &bc_info,
+				 sizeof(unsigned int)))
+			return -EFAULT;
+		break;
+
+	case PMIC_BATT_GET_BATTERY_TEMPERATURE:
+		CHECK_ERROR(pmic_batt_get_batt_temperature(&c_current));
+		bc_info = (unsigned int)c_current;
+		if (copy_to_user((unsigned int *)arg, &bc_info,
+				 sizeof(unsigned int)))
+			return -EFAULT;
+
+		break;
+
+	case PMIC_BATT_GET_CHARGER_VOLTAGE:
+		CHECK_ERROR(pmic_batt_get_charge_voltage(&c_current));
+		bc_info = (unsigned int)c_current * 23000 / 1023;
+		if (copy_to_user((unsigned int *)arg, &bc_info,
+				 sizeof(unsigned int)))
+			return -EFAULT;
+
+		break;
+
+	case PMIC_BATT_GET_CHARGER_CURRENT:
+		CHECK_ERROR(pmic_batt_get_charge_current(&c_current));
+		bc_info = (unsigned int)c_current * 5750 / 1023;
+		if (copy_to_user((unsigned int *)arg, &bc_info,
+				 sizeof(unsigned int)))
+			return -EFAULT;
+
+		break;
+
+	case PMIC_BATT_EOL_CONTROL:
+		if ((eol_setting = kmalloc(sizeof(t_eol_setting), GFP_KERNEL))
+		    == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(eol_setting, (t_eol_setting *) arg,
+				   sizeof(t_eol_setting))) {
+			kfree(eol_setting);
+			return -EFAULT;
+		}
+
+		if (eol_setting->enable != false) {
+			CHECK_ERROR_KFREE(pmic_batt_bp_enable_eol
+					  (eol_setting->typical),
+					  (kfree(chgr_setting)));
+		} else {
+			CHECK_ERROR_KFREE(pmic_batt_disable_eol(),
+					  (kfree(chgr_setting)));
+		}
+
+		kfree(eol_setting);
+		break;
+
+	case PMIC_BATT_SET_OUT_CONTROL:
+		CHECK_ERROR(pmic_batt_set_out_control((t_control) arg));
+		break;
+
+	case PMIC_BATT_SET_THRESHOLD:
+		CHECK_ERROR(pmic_batt_set_threshold((int)arg));
+		break;
+
+	case PMIC_BATT_LED_CONTROL:
+		CHECK_ERROR(pmic_batt_led_control((bool) arg));
+		break;
+
+	case PMIC_BATT_REV_SUPP_CONTROL:
+		CHECK_ERROR(pmic_batt_set_reverse_supply((bool) arg));
+		break;
+
+	case PMIC_BATT_UNREG_CONTROL:
+		CHECK_ERROR(pmic_batt_set_unregulated((bool) arg));
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * This function implements the open method on a Pmic battery device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_battery_open(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+
+	/* check open count, if open firstly, register callbacks */
+	down(&count_mutex);
+	if (open_count++ > 0) {
+		up(&count_mutex);
+		return 0;
+	}
+
+	pr_debug("Subscribe the callbacks\n");
+	/* register battery event callback */
+	if (pmic_batt_event_subscribe(BAT_IT_CHG_DET, callback_chg_detect)) {
+		pr_debug("Failed to subscribe the charger detect callback\n");
+		goto event_err1;
+	}
+	if (pmic_power_event_sub(PWR_IT_LOBATLI, callback_power_fail)) {
+		pr_debug("Failed to subscribe the power failed callback\n");
+		goto event_err2;
+	}
+	if (pmic_power_event_sub(PWR_IT_LOBATHI, callback_low_battery)) {
+		pr_debug("Failed to subscribe the low battery callback\n");
+		goto event_err3;
+	}
+	if (pmic_batt_event_subscribe
+	    (BAT_IT_CHG_OVERVOLT, callback_chg_overvoltage)) {
+		pr_debug("Failed to subscribe the low battery callback\n");
+		goto event_err4;
+	}
+	if (pmic_batt_event_subscribe
+	    (BAT_IT_BELOW_THRESHOLD, callback_chg_full)) {
+		pr_debug("Failed to subscribe the charge full callback\n");
+		goto event_err5;
+	}
+
+	up(&count_mutex);
+
+	return 0;
+
+	/* un-subscribe the event callbacks */
+event_err5:
+	pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT,
+				    callback_chg_overvoltage);
+event_err4:
+	pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery);
+event_err3:
+	pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail);
+event_err2:
+	pmic_batt_event_unsubscribe(BAT_IT_CHG_DET, callback_chg_detect);
+event_err1:
+
+	open_count--;
+	up(&count_mutex);
+
+	return -EFAULT;
+
+}
+
+/*!
+ * This function implements the release method on a Pmic battery device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_battery_release(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+
+	/* check open count, if open firstly, register callbacks */
+	down(&count_mutex);
+	if (--open_count == 0) {
+		/* unregister these event callback */
+		pr_debug("Unsubscribe the callbacks\n");
+		pmic_batt_event_unsubscribe(BAT_IT_BELOW_THRESHOLD,
+					    callback_chg_full);
+		pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT,
+					    callback_chg_overvoltage);
+		pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery);
+		pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail);
+		pmic_batt_event_unsubscribe(BAT_IT_CHG_DET,
+					    callback_chg_detect);
+	}
+	up(&count_mutex);
+
+	return 0;
+}
+
+static struct file_operations pmic_battery_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = pmic_battery_ioctl,
+	.open = pmic_battery_open,
+	.release = pmic_battery_release,
+};
+
+static int pmic_battery_remove(struct platform_device *pdev)
+{
+	device_destroy(pmic_battery_class, MKDEV(pmic_battery_major, 0));
+	class_destroy(pmic_battery_class);
+	unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING);
+	return 0;
+}
+
+static int pmic_battery_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct device *temp_class;
+
+	pmic_battery_major = register_chrdev(0, PMIC_BATTERY_STRING,
+					     &pmic_battery_fops);
+
+	if (pmic_battery_major < 0) {
+		printk(KERN_ERR "Unable to get a major for pmic_battery\n");
+		return pmic_battery_major;
+	}
+	init_waitqueue_head(&suspendq);
+
+	pmic_battery_class = class_create(THIS_MODULE, PMIC_BATTERY_STRING);
+	if (IS_ERR(pmic_battery_class)) {
+		printk(KERN_ERR "Error creating PMIC battery class.\n");
+		ret = PTR_ERR(pmic_battery_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(pmic_battery_class, NULL,
+				   MKDEV(pmic_battery_major, 0), NULL,
+				   PMIC_BATTERY_STRING);
+	if (IS_ERR(temp_class)) {
+		printk(KERN_ERR "Error creating PMIC battery class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	pmic_batt_led_control(true);
+	pmic_batt_set_5k_pull(true);
+
+	printk(KERN_INFO "PMIC Battery successfully probed\n");
+
+	return ret;
+
+      err_out2:
+	class_destroy(pmic_battery_class);
+      err_out1:
+	unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING);
+	return ret;
+}
+
+static struct platform_driver pmic_battery_driver_ldm = {
+	.driver = {
+		   .name = "pmic_battery",
+		   .bus = &platform_bus_type,
+		   },
+	.suspend = pmic_battery_suspend,
+	.resume = pmic_battery_resume,
+	.probe = pmic_battery_probe,
+	.remove = pmic_battery_remove,
+};
+
+/*
+ * Init and Exit
+ */
+
+static int __init pmic_battery_init(void)
+{
+	pr_debug("PMIC Battery driver loading...\n");
+	return platform_driver_register(&pmic_battery_driver_ldm);
+}
+
+static void __exit pmic_battery_exit(void)
+{
+	platform_driver_unregister(&pmic_battery_driver_ldm);
+	pr_debug("PMIC Battery driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+module_init(pmic_battery_init);
+module_exit(pmic_battery_exit);
+
+MODULE_DESCRIPTION("pmic_battery driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_battery_defs.h b/drivers/mxc/pmic/mc13783/pmic_battery_defs.h
new file mode 100644
index 000000000000..9f66a185cd2f
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_battery_defs.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_battery_defs.h
+ * @brief This is the internal header for PMIC(mc13783) Battery driver.
+ *
+ * @ingroup PMIC_BATTERY
+ */
+
+#ifndef __PMIC_BATTERY_DEFS_H__
+#define __PMIC_BATTERY_DEFS_H__
+
+#define         PMIC_BATTERY_STRING    "pmic_battery"
+
+/* REG_CHARGE */
+#define MC13783_BATT_DAC_V_DAC_LSH		0
+#define MC13783_BATT_DAC_V_DAC_WID		3
+#define MC13783_BATT_DAC_DAC_LSH			3
+#define MC13783_BATT_DAC_DAC_WID			4
+#define	MC13783_BATT_DAC_TRCKLE_LSH		7
+#define	MC13783_BATT_DAC_TRCKLE_WID		3
+#define MC13783_BATT_DAC_FETOVRD_EN_LSH		10
+#define MC13783_BATT_DAC_FETOVRD_EN_WID		1
+#define MC13783_BATT_DAC_FETCTRL_EN_LSH		11
+#define MC13783_BATT_DAC_FETCTRL_EN_WID		1
+#define MC13783_BATT_DAC_REVERSE_SUPPLY_LSH	13
+#define MC13783_BATT_DAC_REVERSE_SUPPLY_WID	1
+#define MC13783_BATT_DAC_OVCTRL_LSH		15
+#define MC13783_BATT_DAC_OVCTRL_WID		2
+#define MC13783_BATT_DAC_UNREGULATED_LSH		17
+#define MC13783_BATT_DAC_UNREGULATED_WID		1
+#define MC13783_BATT_DAC_LED_EN_LSH		18
+#define MC13783_BATT_DAC_LED_EN_WID		1
+#define MC13783_BATT_DAC_5K_LSH			19
+#define MC13783_BATT_DAC_5K_WID			1
+
+#define         BITS_OUT_VOLTAGE        0
+#define         LONG_OUT_VOLTAGE        3
+#define         BITS_CURRENT_MAIN       3
+#define         LONG_CURRENT_MAIN       4
+#define         BITS_CURRENT_TRICKLE    7
+#define         LONG_CURRENT_TRICKLE    3
+#define         BIT_FETOVRD             10
+#define         BIT_FETCTRL             11
+#define         BIT_RVRSMODE            13
+#define         BITS_OVERVOLTAGE        15
+#define         LONG_OVERVOLTAGE        2
+#define         BIT_UNREGULATED         17
+#define         BIT_CHRG_LED            18
+#define         BIT_CHRGRAWPDEN         19
+
+/* REG_POWXER_CONTROL_0 */
+#define MC13783_BATT_DAC_V_COIN_LSH		20
+#define MC13783_BATT_DAC_V_COIN_WID		3
+#define MC13783_BATT_DAC_COIN_CH_EN_LSH		23
+#define MC13783_BATT_DAC_COIN_CH_EN_WID		1
+#define MC13783_BATT_DAC_COIN_CH_EN_ENABLED	1
+#define MC13783_BATT_DAC_COIN_CH_EN_DISABLED	0
+#define MC13783_BATT_DAC_EOL_CMP_EN_LSH		18
+#define MC13783_BATT_DAC_EOL_CMP_EN_WID		1
+#define MC13783_BATT_DAC_EOL_CMP_EN_ENABLE	1
+#define MC13783_BATT_DAC_EOL_CMP_EN_DISABLE	0
+#define MC13783_BATT_DAC_EOL_SEL_LSH		16
+#define MC13783_BATT_DAC_EOL_SEL_WID		2
+
+#define         DEF_VALUE               0
+
+#define         BAT_THRESHOLD_MAX       3
+
+#endif				/*  __PMIC_BATTERY_DEFS_H__ */
diff --git a/drivers/mxc/pmic/mc13783/pmic_convity.c b/drivers/mxc/pmic/mc13783/pmic_convity.c
new file mode 100644
index 000000000000..5d634ebebacf
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_convity.c
@@ -0,0 +1,2482 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_convity.c
+ * @brief Implementation of the PMIC Connectivity driver APIs.
+ *
+ * The PMIC connectivity device driver and this API were developed to support
+ * the external connectivity capabilities of several power management ICs that
+ * are available from Freescale Semiconductor, Inc.
+ *
+ * The following operating modes, in terms of external connectivity, are
+ * supported:
+ *
+ * @verbatim
+       Operating Mode     mc13783
+       ---------------    -------
+       USB (incl. OTG)     Yes
+       RS-232              Yes
+       CEA-936             Yes
+
+   @endverbatim
+ *
+ * @ingroup PMIC_CONNECTIVITY
+ */
+
+#include <linux/interrupt.h>	/* For tasklet interface.                  */
+#include <linux/platform_device.h>	/* For kernel module interface.            */
+#include <linux/spinlock.h>	/* For spinlock interface.                 */
+#include <linux/pmic_adc.h>	/* For PMIC ADC driver interface.          */
+#include <linux/pmic_status.h>
+#include <mach/pmic_convity.h>	/* For PMIC Connectivity driver interface. */
+
+/*
+ * mc13783 Connectivity API
+ */
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_convity_open);
+EXPORT_SYMBOL(pmic_convity_close);
+EXPORT_SYMBOL(pmic_convity_set_mode);
+EXPORT_SYMBOL(pmic_convity_get_mode);
+EXPORT_SYMBOL(pmic_convity_reset);
+EXPORT_SYMBOL(pmic_convity_set_callback);
+EXPORT_SYMBOL(pmic_convity_clear_callback);
+EXPORT_SYMBOL(pmic_convity_get_callback);
+EXPORT_SYMBOL(pmic_convity_usb_set_speed);
+EXPORT_SYMBOL(pmic_convity_usb_get_speed);
+EXPORT_SYMBOL(pmic_convity_usb_set_power_source);
+EXPORT_SYMBOL(pmic_convity_usb_get_power_source);
+EXPORT_SYMBOL(pmic_convity_usb_set_xcvr);
+EXPORT_SYMBOL(pmic_convity_usb_get_xcvr);
+EXPORT_SYMBOL(pmic_convity_usb_otg_set_dlp_duration);
+EXPORT_SYMBOL(pmic_convity_usb_otg_get_dlp_duration);
+EXPORT_SYMBOL(pmic_convity_usb_otg_set_config);
+EXPORT_SYMBOL(pmic_convity_usb_otg_clear_config);
+EXPORT_SYMBOL(pmic_convity_usb_otg_get_config);
+EXPORT_SYMBOL(pmic_convity_set_output);
+EXPORT_SYMBOL(pmic_convity_rs232_set_config);
+EXPORT_SYMBOL(pmic_convity_rs232_get_config);
+EXPORT_SYMBOL(pmic_convity_cea936_exit_signal);
+
+/*! @def SET_BITS
+ * Set a register field to a given value.
+ */
+
+#define SET_BITS(reg, field, value)    (((value) << reg.field.offset) & \
+                                        reg.field.mask)
+
+/*! @def GET_BITS
+ * Get the current value of a given register field.
+ */
+#define GET_BITS(reg, value)    (((value) & reg.mask) >> \
+                                 reg.offset)
+
+/*!
+ * @brief Define the possible states for a device handle.
+ *
+ * This enumeration is used to track the current state of each device handle.
+ */
+typedef enum {
+	HANDLE_FREE,		/*!< Handle is available for use. */
+	HANDLE_IN_USE		/*!< Handle is currently in use.  */
+} HANDLE_STATE;
+
+/*
+ * This structure is used to define a specific hardware register field.
+ *
+ * All hardware register fields are defined using an offset to the LSB
+ * and a mask. The offset is used to right shift a register value before
+ * applying the mask to actually obtain the value of the field.
+ */
+typedef struct {
+	const unsigned char offset;	/* Offset of LSB of register field.           */
+	const unsigned int mask;	/* Mask value used to isolate register field. */
+} REGFIELD;
+
+/*!
+ * @brief This structure is used to identify the fields in the USBCNTRL_REG_0 hardware register.
+ *
+ * This structure lists all of the fields within the USBCNTRL_REG_0 hardware
+ * register.
+ */
+typedef struct {
+	REGFIELD FSENB;		/*!< USB Full Speed Enable                            */
+	REGFIELD USB_SUSPEND;	/*!< USB Suspend Mode Enable                          */
+	REGFIELD USB_PU;	/*!< USB Pullup Enable                                */
+	REGFIELD UDP_PD;	/*!< USB Data Plus Pulldown Enable                    */
+	REGFIELD UDM_PD;	/*!< USB 150K UDP Pullup Enable                       */
+	REGFIELD DP150K_PU;	/*!< USB Pullup/Pulldown Override Enable              */
+	REGFIELD VBUSPDENB;	/*!< USB VBUS Pulldown NMOS Switch Enable             */
+	REGFIELD CURRENT_LIMIT;	/*!< USB Regulator Current Limit Setting-3 bits       */
+	REGFIELD DLP_SRP;	/*!< USB Data Line Pulsing Timer Enable               */
+	REGFIELD SE0_CONN;	/*!< USB Pullup Connect When SE0 Detected             */
+	REGFIELD USBXCVREN;	/*!< USB Transceiver Enabled When INTERFACE_MODE[2:0]=000 and RESETB=high */
+	REGFIELD PULLOVR;	/*!< 1K5 Pullup and UDP/UDM Pulldown Disable When UTXENB=Low             */
+	REGFIELD INTERFACE_MODE;	/*!< Connectivity Interface Mode Select-3 Bits        */
+	REGFIELD DATSE0;	/*!< USB Single or Differential Mode Select           */
+	REGFIELD BIDIR;		/*!< USB Unidirectional/Bidirectional Transmission    */
+	REGFIELD USBCNTRL;	/*!< USB Mode of Operation controlled By USBEN/SPI Pin */
+	REGFIELD IDPD;		/*!< USB UID Pulldown Enable                          */
+	REGFIELD IDPULSE;	/*!< USB Pulse to Gnd on UID Line Generated           */
+	REGFIELD IDPUCNTRL;	/*!< USB UID Pin pulled high By 5ua Curr Source       */
+	REGFIELD DMPULSE;	/*!< USB Positive pulse on the UDM Line Generated     */
+} USBCNTRL_REG_0;
+
+/*!
+ * @brief This variable is used to access the USBCNTRL_REG_0 hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * USBCNTRL_REG_0  hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const USBCNTRL_REG_0 regUSB0 = {
+	{0, 0x000001},		/*!< FSENB        */
+	{1, 0x000002},		/*!< USB_SUSPEND  */
+	{2, 0x000004},		/*!< USB_PU       */
+	{3, 0x000008},		/*!< UDP_PD       */
+	{4, 0x000010},		/*!< UDM_PD       */
+	{5, 0x000020},		/*!< DP150K_PU    */
+	{6, 0x000040},		/*!< VBUSPDENB    */
+	{7, 0x000380},		/*!< CURRENT_LIMIT */
+	{10, 0x000400},		/*!< DLP_SRP      */
+	{11, 0x000800},		/*!< SE0_CONN     */
+	{12, 0x001000},		/*!< USBXCVREN    */
+	{13, 0x002000},		/*!< PULLOVR      */
+	{14, 0x01c000},		/*!< INTERFACE_MODE */
+	{17, 0x020000},		/*!< DATSE0       */
+	{18, 0x040000},		/*!< BIDIR        */
+	{19, 0x080000},		/*!< USBCNTRL     */
+	{20, 0x100000},		/*!< IDPD         */
+	{21, 0x200000},		/*!< IDPULSE      */
+	{22, 0x400000},		/*!< IDPUCNTRL    */
+	{23, 0x800000}		/*!< DMPULSE      */
+
+};
+
+/*!
+ * @brief This structure is used to identify the fields in the USBCNTRL_REG_1 hardware register.
+ *
+ * This structure lists all of the fields within the USBCNTRL_REG_1 hardware
+ * register.
+ */
+typedef struct {
+	REGFIELD VUSBIN;	/*!< Controls The Input Source For VUSB             */
+	REGFIELD VUSB;		/*!< VUSB Output Voltage Select-High=3.3V Low=2.775V */
+	REGFIELD VUSBEN;	/*!< VUSB Output Enable-                            */
+	REGFIELD VBUSEN;	/*!< VBUS Output Enable-                            */
+	REGFIELD RSPOL;		/*!< Low=RS232 TX on UDM, RX on UDP
+				   High= RS232 TX on UDP, RX on UDM               */
+	REGFIELD RSTRI;		/*!< TX Forced To Tristate in RS232 Mode Only       */
+	REGFIELD ID100kPU;	/*!< 100k UID Pullup Enabled                        */
+} USBCNTRL_REG_1;
+
+/*!
+ * @brief This variable is used to access the USBCNTRL_REG_1 hardware register.
+ *
+ * This variable defines how to access all of the fields within the
+ * USBCNTRL_REG_1  hardware register. The initial values consist of the offset
+ * and mask values needed to access each of the register fields.
+ */
+static const USBCNTRL_REG_1 regUSB1 = {
+	{0, 0x000003},		/*!< VUSBIN-2 Bits  */
+	{2, 0x000004},		/*!< VUSB           */
+	{3, 0x000008},		/*!< VUSBEN         */
+	/*{4, 0x000010} *//*!< Reserved       */
+	{5, 0x000020},		/*!< VBUSEN         */
+	{6, 0x000040},		/*!< RSPOL          */
+	{7, 0x000080},		/*!< RSTRI          */
+	{8, 0x000100}		/*!< ID100kPU       */
+	/*!< 9-23 Unused    */
+};
+
+/*! Define a mask to access the entire hardware register. */
+static const unsigned int REG_FULLMASK = 0xffffff;
+
+/*! Define the mc13783 USBCNTRL_REG_0 register power on reset state. */
+static const unsigned int RESET_USBCNTRL_REG_0 = 0x080060;
+
+/*! Define the mc13783 USBCNTRL_REG_1 register power on reset state. */
+static const unsigned int RESET_USBCNTRL_REG_1 = 0x000006;
+
+static pmic_event_callback_t eventNotify;
+
+/*!
+ * @brief This structure is used to maintain the current device driver state.
+ *
+ * This structure maintains the current state of the connectivity driver. This
+ * includes both the PMIC hardware state as well as the device handle and
+ * callback states.
+ */
+
+typedef struct {
+	PMIC_CONVITY_HANDLE handle;	/*!< Device handle.   */
+	HANDLE_STATE handle_state;	/*!< Device handle
+					   state.           */
+	PMIC_CONVITY_MODE mode;	/*!< Device mode.     */
+	PMIC_CONVITY_CALLBACK callback;	/*!< Event callback function pointer. */
+	PMIC_CONVITY_EVENTS eventMask;	/*!< Event mask.      */
+	PMIC_CONVITY_USB_SPEED usbSpeed;	/*!< USB connection
+						   speed.           */
+	PMIC_CONVITY_USB_MODE usbMode;	/*!< USB connection
+					   mode.            */
+	PMIC_CONVITY_USB_POWER_IN usbPowerIn;	/*!< USB transceiver
+						   power source.    */
+	PMIC_CONVITY_USB_POWER_OUT usbPowerOut;	/*!< USB transceiver
+						   power output
+						   level.           */
+	PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode;	/*!< USB transceiver
+							   mode.            */
+	unsigned int usbDlpDuration;	/*!< USB Data Line
+					   Pulsing duration. */
+	PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg;	/*!< USB OTG
+						   configuration
+						   options.         */
+	PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal;	/*!< RS-232 internal
+							   connections.     */
+	PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal;	/*!< RS-232 external
+							   connections.     */
+} pmic_convity_state_struct;
+
+/*!
+ * @brief This structure is used to maintain the current device driver state.
+ *
+ * This structure maintains the current state of the driver in USB mode. This
+ * includes both the PMIC hardware state as well as the device handle and
+ * callback states.
+ */
+
+typedef struct {
+	PMIC_CONVITY_HANDLE handle;	/*!< Device handle.   */
+	HANDLE_STATE handle_state;	/*!< Device handle
+					   state.           */
+	PMIC_CONVITY_MODE mode;	/*!< Device mode.     */
+	PMIC_CONVITY_CALLBACK callback;	/*!< Event callback function pointer. */
+	PMIC_CONVITY_EVENTS eventMask;	/*!< Event mask.      */
+	PMIC_CONVITY_USB_SPEED usbSpeed;	/*!< USB connection
+						   speed.           */
+	PMIC_CONVITY_USB_MODE usbMode;	/*!< USB connection
+					   mode.            */
+	PMIC_CONVITY_USB_POWER_IN usbPowerIn;	/*!< USB transceiver
+						   power source.    */
+	PMIC_CONVITY_USB_POWER_OUT usbPowerOut;	/*!< USB transceiver
+						   power output
+						   level.           */
+	PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode;	/*!< USB transceiver
+							   mode.            */
+	unsigned int usbDlpDuration;	/*!< USB Data Line
+					   Pulsing duration. */
+	PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg;	/*!< USB OTG
+						   configuration
+						   options.         */
+} pmic_convity_usb_state;
+
+/*!
+ * @brief This structure is used to maintain the current device driver state.
+ *
+ * This structure maintains the current state of the driver in RS_232 mode. This
+ * includes both the PMIC hardware state as well as the device handle and
+ * callback states.
+ */
+
+typedef struct {
+	PMIC_CONVITY_HANDLE handle;	/*!< Device handle.   */
+	HANDLE_STATE handle_state;	/*!< Device handle
+					   state.           */
+	PMIC_CONVITY_MODE mode;	/*!< Device mode.     */
+	PMIC_CONVITY_CALLBACK callback;	/*!< Event callback function pointer. */
+	PMIC_CONVITY_EVENTS eventMask;	/*!< Event mask.      */
+	PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal;	/*!< RS-232 internal
+							   connections.     */
+	PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal;	/*!< RS-232 external
+							   connections.     */
+} pmic_convity_rs232_state;
+
+/*!
+ * @brief This structure is used to maintain the current device driver state.
+ *
+ * This structure maintains the current state of the driver in cea-936 mode. This
+ * includes both the PMIC hardware state as well as the device handle and
+ * callback states.
+ */
+
+typedef struct {
+	PMIC_CONVITY_HANDLE handle;	/*!< Device handle.   */
+	HANDLE_STATE handle_state;	/*!< Device handle
+					   state.           */
+	PMIC_CONVITY_MODE mode;	/*!< Device mode.     */
+	PMIC_CONVITY_CALLBACK callback;	/*!< Event callback function pointer. */
+	PMIC_CONVITY_EVENTS eventMask;	/*!< Event mask.      */
+
+} pmic_convity_cea936_state;
+
+/*!
+ * @brief Identifies the hardware interrupt source.
+ *
+ * This enumeration identifies which of the possible hardware interrupt
+ * sources actually caused the current interrupt handler to be called.
+ */
+typedef enum {
+	CORE_EVENT_4V4 = 1,	/*!< Detected USB 4.4 V event.              */
+	CORE_EVENT_2V0 = 2,	/*!< Detected USB 2.0 V event.              */
+	CORE_EVENT_0V8 = 4,	/*!< Detected USB 0.8 V event.              */
+	CORE_EVENT_ABDET = 8	/*!< Detected USB mini A-B connector event. */
+} PMIC_CORE_EVENT;
+
+/*!
+ * @brief This structure defines the reset/power on state for the Connectivity driver.
+ */
+static const pmic_convity_state_struct reset = {
+	0,
+	HANDLE_FREE,
+	USB,
+	NULL,
+	0,
+	USB_FULL_SPEED,
+	USB_PERIPHERAL,
+	USB_POWER_INTERNAL,
+	USB_POWER_3V3,
+	USB_TRANSCEIVER_OFF,
+	0,
+	USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH,
+	RS232_TX_USE0VM_RX_UDATVP,
+	RS232_TX_UDM_RX_UDP
+};
+
+/*!
+ * @brief This structure maintains the current state of the Connectivity driver.
+ *
+ * The initial values must be identical to the reset state defined by the
+ * #reset variable.
+ */
+static pmic_convity_usb_state usb = {
+	0,
+	HANDLE_FREE,
+	USB,
+	NULL,
+	0,
+	USB_FULL_SPEED,
+	USB_PERIPHERAL,
+	USB_POWER_INTERNAL,
+	USB_POWER_3V3,
+	USB_TRANSCEIVER_OFF,
+	0,
+	USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH,
+};
+
+/*!
+ * @brief This structure maintains the current state of the Connectivity driver.
+ *
+ * The initial values must be identical to the reset state defined by the
+ * #reset variable.
+ */
+static pmic_convity_rs232_state rs_232 = {
+	0,
+	HANDLE_FREE,
+	RS232_1,
+	NULL,
+	0,
+	RS232_TX_USE0VM_RX_UDATVP,
+	RS232_TX_UDM_RX_UDP
+};
+
+/*!
+ * @brief This structure maintains the current state of the Connectivity driver.
+ *
+ * The initial values must be identical to the reset state defined by the
+ * #reset variable.
+ */
+static pmic_convity_cea936_state cea_936 = {
+	0,
+	HANDLE_FREE,
+	CEA936_MONO,
+	NULL,
+	0,
+};
+
+/*!
+ * @brief This spinlock is used to provide mutual exclusion.
+ *
+ * Create a spinlock that can be used to provide mutually exclusive
+ * read/write access to the globally accessible "convity" data structure
+ * that was defined above. Mutually exclusive access is required to
+ * ensure that the convity data structure is consistent at all times
+ * when possibly accessed by multiple threads of execution (for example,
+ * while simultaneously handling a user request and an interrupt event).
+ *
+ * We need to use a spinlock sometimes because we need to provide mutual
+ * exclusion while handling a hardware interrupt.
+ */
+static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+
+/*!
+ * @brief This mutex is used to provide mutual exclusion.
+ *
+ * Create a mutex that can be used to provide mutually exclusive
+ * read/write access to the globally accessible data structures
+ * that were defined above. Mutually exclusive access is required to
+ * ensure that the Connectivity data structures are consistent at all
+ * times when possibly accessed by multiple threads of execution.
+ *
+ * Note that we use a mutex instead of the spinlock whenever disabling
+ * interrupts while in the critical section is not required. This helps
+ * to minimize kernel interrupt handling latency.
+ */
+static DECLARE_MUTEX(mutex);
+
+/* Prototype for the connectivity driver tasklet function. */
+static void pmic_convity_tasklet(struct work_struct *work);
+
+/*!
+ * @brief Tasklet handler for the connectivity driver.
+ *
+ * Declare a tasklet that will do most of the processing for all of the
+ * connectivity-related interrupt events (USB4.4VI, USB2.0VI, USB0.8VI,
+ * and AB_DETI). Note that we cannot do all of the required processing
+ * within the interrupt handler itself because we may need to call the
+ * ADC driver to measure voltages as well as calling any user-registered
+ * callback functions.
+ */
+DECLARE_WORK(convityTasklet, pmic_convity_tasklet);
+
+/*!
+ * @brief Global variable to track currently active interrupt events.
+ *
+ * This global variable is used to keep track of all of the currently
+ * active interrupt events for the connectivity driver. Note that access
+ * to this variable may occur while within an interrupt context and,
+ * therefore, must be guarded by using a spinlock.
+ */
+static PMIC_CORE_EVENT eventID = 0;
+
+/* Prototypes for all static connectivity driver functions. */
+static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode);
+static PMIC_STATUS pmic_convity_deregister_all(void);
+static void pmic_convity_event_handler(void *param);
+
+/**************************************************************************
+ * General setup and configuration functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name General Setup and Configuration Connectivity APIs
+ * Functions for setting up and configuring the connectivity hardware.
+ */
+/*@{*/
+
+/*!
+ * Attempt to open and gain exclusive access to the PMIC connectivity
+ * hardware. An initial operating mode must also be specified.
+ *
+ * If the open request is successful, then a numeric handle is returned
+ * and this handle must be used in all subsequent function calls. The
+ * same handle must also be used in the pmic_convity_close() call when use
+ * of the PMIC connectivity hardware is no longer required.
+ *
+ * @param       handle          device handle from open() call
+ * @param       mode            initial connectivity operating mode
+ *
+ * @return      PMIC_SUCCESS    if the open request was successful
+ */
+PMIC_STATUS pmic_convity_open(PMIC_CONVITY_HANDLE * const handle,
+			      const PMIC_CONVITY_MODE mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	if (handle == (PMIC_CONVITY_HANDLE *) NULL) {
+		/* Do not dereference a NULL pointer. */
+		return PMIC_ERROR;
+	}
+
+	/* We only need to acquire a mutex here because the interrupt handler
+	 * never modifies the device handle or device handle state. Therefore,
+	 * we don't need to worry about conflicts with the interrupt handler
+	 * or the need to execute in an interrupt context.
+	 *
+	 * But we do need a critical section here to avoid problems in case
+	 * multiple calls to pmic_convity_open() are made since we can only
+	 * allow one of them to succeed.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* Check the current device handle state and acquire the handle if
+	 * it is available.
+	 */
+	if ((usb.handle_state != HANDLE_FREE)
+	    && (rs_232.handle_state != HANDLE_FREE)
+	    && (cea_936.handle_state != HANDLE_FREE)) {
+
+		/* Cannot open the PMIC connectivity hardware at this time or an invalid
+		 * mode was requested.
+		 */
+		*handle = reset.handle;
+	} else {
+
+		if (mode == USB) {
+			usb.handle = (PMIC_CONVITY_HANDLE) (&usb);
+			usb.handle_state = HANDLE_IN_USE;
+		} else if ((mode == RS232_1) || (mode == RS232_2)) {
+			rs_232.handle = (PMIC_CONVITY_HANDLE) (&rs_232);
+			rs_232.handle_state = HANDLE_IN_USE;
+		} else if ((mode == CEA936_STEREO) || (mode == CEA936_MONO)
+			   || (mode == CEA936_TEST_LEFT)
+			   || (mode == CEA936_TEST_RIGHT)) {
+			cea_936.handle = (PMIC_CONVITY_HANDLE) (&cea_936);
+			cea_936.handle_state = HANDLE_IN_USE;
+
+		}
+		/* Let's begin by acquiring the connectivity device handle. */
+		/* Then we can try to set the desired operating mode. */
+		rc = pmic_convity_set_mode_internal(mode);
+
+		if (rc == PMIC_SUCCESS) {
+			/* Successfully set the desired operating mode, now return the
+			 * handle to the caller.
+			 */
+			if (mode == USB) {
+				*handle = usb.handle;
+			} else if ((mode == RS232_1) || (mode == RS232_2)) {
+				*handle = rs_232.handle;
+			} else if ((mode == CEA936_STEREO)
+				   || (mode == CEA936_MONO)
+				   || (mode == CEA936_TEST_LEFT)
+				   || (mode == CEA936_TEST_RIGHT)) {
+				*handle = cea_936.handle;
+			}
+		} else {
+			/* Failed to set the desired mode, return the handle to an unused
+			 * state.
+			 */
+			if (mode == USB) {
+				usb.handle = reset.handle;
+				usb.handle_state = reset.handle_state;
+			} else if ((mode == RS232_1) || (mode == RS232_2)) {
+				rs_232.handle = reset.handle;
+				rs_232.handle_state = reset.handle_state;
+			} else if ((mode == CEA936_STEREO)
+				   || (mode == CEA936_MONO)
+				   || (mode == CEA936_TEST_LEFT)
+				   || (mode == CEA936_TEST_RIGHT)) {
+				cea_936.handle = reset.handle;
+				cea_936.handle_state = reset.handle_state;
+			}
+
+			*handle = reset.handle;
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Terminate further access to the PMIC connectivity hardware. Also allows
+ * another process to call pmic_convity_open() to gain access.
+ *
+ * @param       handle          device handle from open() call
+ *
+ * @return      PMIC_SUCCESS    if the close request was successful
+ */
+PMIC_STATUS pmic_convity_close(const PMIC_CONVITY_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Begin a critical section here to avoid the possibility of race
+	 * conditions if multiple threads happen to call this function and
+	 * pmic_convity_open() at the same time.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	/* Confirm that the device handle matches the one assigned in the
+	 * pmic_convity_open() call and then close the connection.
+	 */
+	if (((handle == usb.handle) &&
+	     (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						      && (rs_232.handle_state ==
+							  HANDLE_IN_USE))
+	    || ((handle == cea_936.handle)
+		&& (cea_936.handle_state == HANDLE_IN_USE))) {
+		rc = PMIC_SUCCESS;
+
+		/* Deregister for all existing callbacks if necessary and make sure
+		 * that the event handling settings are consistent following the
+		 * close operation.
+		 */
+		if ((usb.callback != reset.callback)
+		    || (rs_232.callback != reset.callback)
+		    || (cea_936.callback != reset.callback)) {
+			/* Deregister the existing callback function and all registered
+			 * events before we completely close the handle.
+			 */
+			rc = pmic_convity_deregister_all();
+			if (rc == PMIC_SUCCESS) {
+
+			} else if (usb.eventMask != reset.eventMask) {
+				/* Having a non-zero eventMask without a callback function being
+				 * defined should never occur but let's just make sure here that
+				 * we keep things consistent.
+				 */
+				usb.eventMask = reset.eventMask;
+				/* Mark the connectivity device handle as being closed. */
+				usb.handle = reset.handle;
+				usb.handle_state = reset.handle_state;
+
+			} else if (rs_232.eventMask != reset.eventMask) {
+
+				rs_232.eventMask = reset.eventMask;
+				/* Mark the connectivity device handle as being closed. */
+				rs_232.handle = reset.handle;
+				rs_232.handle_state = reset.handle_state;
+
+			} else if (cea_936.eventMask != reset.eventMask) {
+				cea_936.eventMask = reset.eventMask;
+				/* Mark the connectivity device handle as being closed. */
+				cea_936.handle = reset.handle;
+				cea_936.handle_state = reset.handle_state;
+
+			}
+
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Change the current operating mode of the PMIC connectivity hardware.
+ * The available connectivity operating modes is hardware dependent and
+ * consists of one or more of the following: USB (including USB On-the-Go),
+ * RS-232, and CEA-936. Requesting an operating mode that is not supported
+ * by the PMIC hardware will return PMIC_NOT_SUPPORTED.
+ *
+ * @param       handle          device handle from
+					open() call
+ * @param       mode            desired operating mode
+ *
+ * @return      PMIC_SUCCESS    if the requested mode was successfully set
+ */
+PMIC_STATUS pmic_convity_set_mode(const PMIC_CONVITY_HANDLE handle,
+				  const PMIC_CONVITY_MODE mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (((handle == usb.handle) &&
+	     (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						      && (rs_232.handle_state ==
+							  HANDLE_IN_USE))
+	    || ((handle == cea_936.handle)
+		&& (cea_936.handle_state == HANDLE_IN_USE))) {
+		rc = pmic_convity_set_mode_internal(mode);
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the current operating mode for the PMIC connectivity hardware.
+ *
+ * @param       handle          device handle from open() call
+ * @param       mode            the current PMIC connectivity operating mode
+ *
+ * @return      PMIC_SUCCESS    if the requested mode was successfully set
+ */
+PMIC_STATUS pmic_convity_get_mode(const PMIC_CONVITY_HANDLE handle,
+				  PMIC_CONVITY_MODE * const mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((((handle == usb.handle) &&
+	      (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						       && (rs_232.
+							   handle_state ==
+							   HANDLE_IN_USE))
+	     || ((handle == cea_936.handle)
+		 && (cea_936.handle_state == HANDLE_IN_USE)))
+	    && (mode != (PMIC_CONVITY_MODE *) NULL)) {
+
+		*mode = usb.mode;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Restore all registers to the initial power-on/reset state.
+ *
+ * @param       handle          device handle from open() call
+ *
+ * @return      PMIC_SUCCESS    if the reset was successful
+ */
+PMIC_STATUS pmic_convity_reset(const PMIC_CONVITY_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+	if (((handle == usb.handle) &&
+	     (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						      && (rs_232.handle_state ==
+							  HANDLE_IN_USE))
+	    || ((handle == cea_936.handle)
+		&& (cea_936.handle_state == HANDLE_IN_USE))) {
+
+		/* Reset the PMIC Connectivity register to it's power on state. */
+		rc = pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0,
+				    REG_FULLMASK);
+
+		rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+				    RESET_USBCNTRL_REG_1, REG_FULLMASK);
+
+		if (rc == PMIC_SUCCESS) {
+			/* Also reset the device driver state data structure. */
+
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Register a callback function that will be used to signal PMIC connectivity
+ * events. For example, the USB subsystem should register a callback function
+ * in order to be notified of device connect/disconnect events. Note, however,
+ * that non-USB events may also be signalled depending upon the PMIC hardware
+ * capabilities. Therefore, the callback function must be able to properly
+ * handle all of the possible events if support for non-USB peripherals is
+ * also to be included.
+ *
+ * @param       handle          device handle from open() call
+ * @param       func            a pointer to the callback function
+ * @param       eventMask       a mask selecting events to be notified
+ *
+ * @return      PMIC_SUCCESS    if the callback was successful registered
+ */
+PMIC_STATUS pmic_convity_set_callback(const PMIC_CONVITY_HANDLE handle,
+				      const PMIC_CONVITY_CALLBACK func,
+				      const PMIC_CONVITY_EVENTS eventMask)
+{
+	unsigned long flags;
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* We need to start a critical section here to ensure a consistent state
+	 * in case simultaneous calls to pmic_convity_set_callback() are made. In
+	 * that case, we must serialize the calls to ensure that the "callback"
+	 * and "eventMask" state variables are always consistent.
+	 *
+	 * Note that we don't actually need to acquire the spinlock until later
+	 * when we are finally ready to update the "callback" and "eventMask"
+	 * state variables which are shared with the interrupt handler.
+	 */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+
+		/* Return an error if either the callback function or event mask
+		 * is not properly defined.
+		 *
+		 * It is also considered an error if a callback function has already
+		 * been defined. If you wish to register for a new set of events,
+		 * then you must first call pmic_convity_clear_callback() to
+		 * deregister the existing callback function and list of events
+		 * before trying to register a new callback function.
+		 */
+		if ((func == NULL) || (eventMask == 0)
+		    || (usb.callback != NULL)) {
+			rc = PMIC_ERROR;
+
+			/* Register for PMIC events from the core protocol driver. */
+		} else {
+
+			if ((eventMask & USB_DETECT_4V4_RISE) ||
+			    (eventMask & USB_DETECT_4V4_FALL)) {
+				/* We need to register for the 4.4V interrupt. */
+				//EVENT_USBI or EVENT_USB_44VI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_4V4);
+				rc = pmic_event_subscribe(EVENT_USBI,
+							  eventNotify);
+
+				if (rc != PMIC_SUCCESS) {
+					return rc;
+				}
+			}
+
+			if ((eventMask & USB_DETECT_2V0_RISE) ||
+			    (eventMask & USB_DETECT_2V0_FALL)) {
+				/* We need to register for the 2.0V interrupt. */
+				//EVENT_USB_20VI or EVENT_USBI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_2V0);
+				rc = pmic_event_subscribe(EVENT_USBI,
+							  eventNotify);
+
+				if (rc != PMIC_SUCCESS) {
+					goto Cleanup_4V4;
+				}
+			}
+
+			if ((eventMask & USB_DETECT_0V8_RISE) ||
+			    (eventMask & USB_DETECT_0V8_FALL)) {
+				/* We need to register for the 0.8V interrupt. */
+				//EVENT_USB_08VI or EVENT_USBI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_0V8);
+				rc = pmic_event_subscribe(EVENT_USBI,
+							  eventNotify);
+
+				if (rc != PMIC_SUCCESS) {
+					goto Cleanup_2V0;
+				}
+			}
+
+			if ((eventMask & USB_DETECT_MINI_A) ||
+			    (eventMask & USB_DETECT_MINI_B)
+			    || (eventMask & USB_DETECT_NON_USB_ACCESSORY)
+			    || (eventMask & USB_DETECT_FACTORY_MODE)) {
+				/* We need to register for the AB_DET interrupt. */
+				//EVENT_AB_DETI or EVENT_IDI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_ABDET);
+				rc = pmic_event_subscribe(EVENT_IDI,
+							  eventNotify);
+
+				if (rc != PMIC_SUCCESS) {
+					goto Cleanup_0V8;
+				}
+			}
+
+			/* Use a critical section to maintain a consistent state. */
+			spin_lock_irqsave(&lock, flags);
+
+			/* Successfully registered for all events. */
+			usb.callback = func;
+			usb.eventMask = eventMask;
+			spin_unlock_irqrestore(&lock, flags);
+
+			goto End;
+
+			/* This section unregisters any already registered events if we should
+			 * encounter an error partway through the registration process. Note
+			 * that we don't check the return status here since it is already set
+			 * to PMIC_ERROR before we get here.
+			 */
+		      Cleanup_0V8:
+
+			if ((eventMask & USB_DETECT_0V8_RISE) ||
+			    (eventMask & USB_DETECT_0V8_FALL)) {
+				//EVENT_USB_08VI or EVENT_USBI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_0V8);
+				pmic_event_unsubscribe(EVENT_USBI, eventNotify);
+				goto End;
+			}
+
+		      Cleanup_2V0:
+
+			if ((eventMask & USB_DETECT_2V0_RISE) ||
+			    (eventMask & USB_DETECT_2V0_FALL)) {
+				//EVENT_USB_20VI or EVENT_USBI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_2V0);
+				pmic_event_unsubscribe(EVENT_USBI, eventNotify);
+				goto End;
+			}
+
+		      Cleanup_4V4:
+
+			if ((eventMask & USB_DETECT_4V4_RISE) ||
+			    (eventMask & USB_DETECT_4V4_FALL)) {
+				//EVENT_USB_44VI or EVENT_USBI
+				eventNotify.func = pmic_convity_event_handler;
+				eventNotify.param = (void *)(CORE_EVENT_4V4);
+				pmic_event_unsubscribe(EVENT_USBI, eventNotify);
+			}
+		}
+		/* Exit the critical section. */
+
+	}
+      End:up(&mutex);
+	return rc;
+
+}
+
+/*!
+ * Clears the current callback function. If this function returns successfully
+ * then all future Connectivity events will only be handled by the default
+ * handler within the Connectivity driver.
+ *
+ * @param       handle          device handle from open() call
+ *
+ * @return      PMIC_SUCCESS    if the callback was successful cleared
+ */
+PMIC_STATUS pmic_convity_clear_callback(const PMIC_CONVITY_HANDLE handle)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+	if (((handle == usb.handle) &&
+	     (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						      && (rs_232.handle_state ==
+							  HANDLE_IN_USE))
+	    || ((handle == cea_936.handle)
+		&& (cea_936.handle_state == HANDLE_IN_USE))) {
+
+		rc = pmic_convity_deregister_all();
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the current callback function and event mask.
+ *
+ * @param       handle          device handle from open() call
+ * @param       func            the current callback function
+ * @param       eventMask       the current event selection mask
+ *
+ * @return      PMIC_SUCCESS    if the callback information was successful
+ *                              retrieved
+ */
+PMIC_STATUS pmic_convity_get_callback(const PMIC_CONVITY_HANDLE handle,
+				      PMIC_CONVITY_CALLBACK * const func,
+				      PMIC_CONVITY_EVENTS * const eventMask)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+	if ((((handle == usb.handle) &&
+	      (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle)
+						       && (rs_232.
+							   handle_state ==
+							   HANDLE_IN_USE))
+	     || ((handle == cea_936.handle)
+		 && (cea_936.handle_state == HANDLE_IN_USE)))
+	    && (func != (PMIC_CONVITY_CALLBACK *) NULL)
+	    && (eventMask != (PMIC_CONVITY_EVENTS *) NULL)) {
+		*func = usb.callback;
+		*eventMask = usb.eventMask;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+
+	up(&mutex);
+
+	return rc;
+}
+
+/*@*/
+
+/**************************************************************************
+ * USB-specific configuration and setup functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name USB and USB-OTG Connectivity APIs
+ * Functions for controlling USB and USB-OTG connectivity.
+ */
+/*@{*/
+
+/*!
+ * Set the USB transceiver speed.
+ *
+ * @param       handle          device handle from open() call
+ * @param       speed           the desired USB transceiver speed
+ *
+ * @return      PMIC_SUCCESS    if the transceiver speed was successfully set
+ */
+PMIC_STATUS pmic_convity_usb_set_speed(const PMIC_CONVITY_HANDLE handle,
+				       const PMIC_CONVITY_USB_SPEED speed)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = SET_BITS(regUSB0, FSENB, 1);
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if (handle == (rs_232.handle || cea_936.handle)) {
+		return PMIC_PARAMETER_ERROR;
+	} else {
+		if ((handle == usb.handle) &&
+		    (usb.handle_state == HANDLE_IN_USE)) {
+			/* Validate the function parameters and if they are valid, then
+			 * configure the pull-up and pull-down resistors as required for
+			 * the desired operating mode.
+			 */
+			if ((speed == USB_HIGH_SPEED)) {
+				/*
+				 * The USB transceiver also does not support the high speed mode
+				 * (which is also optional under the USB OTG specification).
+				 */
+				rc = PMIC_NOT_SUPPORTED;
+			} else if ((speed != USB_LOW_SPEED)
+				   && (speed != USB_FULL_SPEED)) {
+				/* Final validity check on the speed parameter. */
+				rc = PMIC_ERROR;;
+			} else {
+				/* First configure the D+ and D- pull-up/pull-down resistors as
+				 * per the USB OTG specification.
+				 */
+				if (speed == USB_FULL_SPEED) {
+					/* Activate pull-up on D+ and pull-down on D-. */
+					reg_value =
+					    SET_BITS(regUSB0, UDM_PD, 1);
+				} else if (speed == USB_LOW_SPEED) {
+					/* Activate pull-up on D+ and pull-down on D-. */
+					reg_value = SET_BITS(regUSB0, FSENB, 1);
+				}
+
+				/* Now set the desired USB transceiver speed. Note that
+				 * USB_FULL_SPEED simply requires FSENB=0 (which it
+				 * already is).
+				 */
+
+				rc = pmic_write_reg(REG_USB, reg_value,
+						    reg_mask);
+
+				if (rc == PMIC_SUCCESS) {
+					usb.usbSpeed = speed;
+				}
+			}
+		}
+	}
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the USB transceiver speed.
+ *
+ * @param       handle          device handle from open() call
+ * @param       speed           the current USB transceiver speed
+ * @param       mode            the current USB transceiver mode
+ *
+ * @return      PMIC_SUCCESS    if the transceiver speed was successfully
+ *                              obtained
+ */
+PMIC_STATUS pmic_convity_usb_get_speed(const PMIC_CONVITY_HANDLE handle,
+				       PMIC_CONVITY_USB_SPEED * const speed,
+				       PMIC_CONVITY_USB_MODE * const mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) &&
+	    (usb.handle_state == HANDLE_IN_USE) &&
+	    (speed != (PMIC_CONVITY_USB_SPEED *) NULL) &&
+	    (mode != (PMIC_CONVITY_USB_MODE *) NULL)) {
+		*speed = usb.usbSpeed;
+		*mode = usb.usbMode;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * This function enables/disables VUSB and VBUS output.
+ * This API configures the VUSBEN and VBUSEN bits of USB register
+ *
+ * @param       handle          device handle from open() call
+ * @param        out_type true, for VBUS
+ *                        false, for VUSB
+ * @param        out 	if true, output is enabled
+ *                      if false, output is disabled
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_convity_set_output(const PMIC_CONVITY_HANDLE handle,
+				    bool out_type, bool out)
+{
+
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+
+		if ((out_type == 0) && (out == 1)) {
+
+			reg_value = SET_BITS(regUSB1, VUSBEN, 1);
+			reg_mask = SET_BITS(regUSB1, VUSBEN, 1);
+
+			rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+					    reg_value, reg_mask);
+		} else if (out_type == 0 && out == 0) {
+			reg_mask = SET_BITS(regUSB1, VBUSEN, 1);
+
+			rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+					    reg_value, reg_mask);
+		} else if (out_type == 1 && out == 1) {
+
+			reg_value = SET_BITS(regUSB1, VBUSEN, 1);
+			reg_mask = SET_BITS(regUSB1, VBUSEN, 1);
+
+			rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+					    reg_value, reg_mask);
+		}
+
+		else if (out_type == 1 && out == 0) {
+
+			reg_mask = SET_BITS(regUSB1, VBUSEN, 1);
+			rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+					    reg_value, reg_mask);
+		}
+
+		/*else {
+
+		   rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+		   reg_value, reg_mask);
+		   } */
+	}
+
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Set the USB transceiver's power supply configuration.
+ *
+ * @param       handle          device handle from open() call
+ * @param       pwrin           USB transceiver regulator input power source
+ * @param       pwrout          USB transceiver regulator output power level
+ *
+ * @return      PMIC_SUCCESS    if the USB transceiver's power supply
+ *                              configuration was successfully set
+ */
+PMIC_STATUS pmic_convity_usb_set_power_source(const PMIC_CONVITY_HANDLE handle,
+					      const PMIC_CONVITY_USB_POWER_IN
+					      pwrin,
+					      const PMIC_CONVITY_USB_POWER_OUT
+					      pwrout)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+	/* SET_BITS(regUSB1, VUSBEN, 1) | SET_BITS(regUSB1, VBUSEN,
+	   1) | SET_BITS(regUSB1,
+	   VUSBIN,
+	   2) | */
+	//    SET_BITS(regUSB1, VUSB, 1);
+/*	    SET_BITS(regUSB1, VUSBIN, 1) | SET_BITS(regUSB1, VUSBEN,
+						    1) | SET_BITS(regUSB1,
+								  VBUSEN, 1);*/
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+
+		if (pwrin == USB_POWER_INTERNAL_BOOST) {
+			reg_value |= SET_BITS(regUSB1, VUSBIN, 0);
+			reg_mask = SET_BITS(regUSB1, VUSBIN, 1);
+		} else if (pwrin == USB_POWER_VBUS) {
+			reg_value |= SET_BITS(regUSB1, VUSBIN, 1);
+			reg_mask = SET_BITS(regUSB1, VUSBIN, 1);
+		}
+
+		else if (pwrin == USB_POWER_INTERNAL) {
+			reg_value |= SET_BITS(regUSB1, VUSBIN, 2);
+			reg_mask = SET_BITS(regUSB1, VUSBIN, 1);
+		}
+
+		if (pwrout == USB_POWER_3V3) {
+			reg_value |= SET_BITS(regUSB1, VUSB, 1);
+			reg_mask |= SET_BITS(regUSB1, VUSB, 1);
+		}
+
+		else if (pwrout == USB_POWER_2V775) {
+			reg_value |= SET_BITS(regUSB1, VUSB, 0);
+			reg_mask |= SET_BITS(regUSB1, VUSB, 1);
+		}
+		rc = pmic_write_reg(REG_CHARGE_USB_SPARE, reg_value, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			usb.usbPowerIn = pwrin;
+			usb.usbPowerOut = pwrout;
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the USB transceiver's current power supply configuration.
+ *
+ * @param       handle          device handle from open() call
+ * @param       pwrin           USB transceiver regulator input power source
+ * @param       pwrout          USB transceiver regulator output power level
+ *
+ * @return      PMIC_SUCCESS    if the USB transceiver's power supply
+ *                              configuration was successfully retrieved
+ */
+PMIC_STATUS pmic_convity_usb_get_power_source(const PMIC_CONVITY_HANDLE handle,
+					      PMIC_CONVITY_USB_POWER_IN *
+					      const pwrin,
+					      PMIC_CONVITY_USB_POWER_OUT *
+					      const pwrout)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) &&
+	    (usb.handle_state == HANDLE_IN_USE) &&
+	    (pwrin != (PMIC_CONVITY_USB_POWER_IN *) NULL) &&
+	    (pwrout != (PMIC_CONVITY_USB_POWER_OUT *) NULL)) {
+		*pwrin = usb.usbPowerIn;
+		*pwrout = usb.usbPowerOut;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Set the USB transceiver's operating mode.
+ *
+ * @param       handle          device handle from open() call
+ * @param       mode            desired operating mode
+ *
+ * @return      PMIC_SUCCESS    if the USB transceiver's operating mode
+ *                              was successfully configured
+ */
+PMIC_STATUS pmic_convity_usb_set_xcvr(const PMIC_CONVITY_HANDLE handle,
+				      const PMIC_CONVITY_USB_TRANSCEIVER_MODE
+				      mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+
+		if (mode == USB_TRANSCEIVER_OFF) {
+			reg_value = SET_BITS(regUSB0, USBXCVREN, 0);
+			reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1);
+
+			rc = pmic_write_reg(REG_USB, reg_value, reg_mask);
+
+		}
+
+		if (mode == USB_SINGLE_ENDED_UNIDIR) {
+			reg_value |=
+			    SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0,
+								    BIDIR, 0);
+			reg_mask |=
+			    SET_BITS(regUSB0, USB_SUSPEND,
+				     1) | SET_BITS(regUSB0, DATSE0,
+						   1) | SET_BITS(regUSB0, BIDIR,
+								 1);
+		} else if (mode == USB_SINGLE_ENDED_BIDIR) {
+			reg_value |=
+			    SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0,
+								    BIDIR, 1);
+			reg_mask |=
+			    SET_BITS(regUSB0, USB_SUSPEND,
+				     1) | SET_BITS(regUSB0, DATSE0,
+						   1) | SET_BITS(regUSB0, BIDIR,
+								 1);
+		} else if (mode == USB_DIFFERENTIAL_UNIDIR) {
+			reg_value |=
+			    SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0,
+								    BIDIR, 0);
+			reg_mask |=
+			    SET_BITS(regUSB0, USB_SUSPEND,
+				     1) | SET_BITS(regUSB0, DATSE0,
+						   1) | SET_BITS(regUSB0, BIDIR,
+								 1);
+		} else if (mode == USB_DIFFERENTIAL_BIDIR) {
+			reg_value |=
+			    SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0,
+								    BIDIR, 1);
+			reg_mask |=
+			    SET_BITS(regUSB0, USB_SUSPEND,
+				     1) | SET_BITS(regUSB0, DATSE0,
+						   1) | SET_BITS(regUSB0, BIDIR,
+								 1);
+		}
+
+		if (mode == USB_SUSPEND_ON) {
+			reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 1);
+			reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1);
+		} else if (mode == USB_SUSPEND_OFF) {
+			reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 0);
+			reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1);
+		}
+
+		if (mode == USB_OTG_SRP_DLP_START) {
+			reg_value |= SET_BITS(regUSB0, USB_PU, 0);
+			reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1);
+		} else if (mode == USB_OTG_SRP_DLP_STOP) {
+			reg_value &= SET_BITS(regUSB0, USB_PU, 1);
+			reg_mask |= SET_BITS(regUSB0, USB_PU, 1);
+		}
+
+		rc = pmic_write_reg(REG_USB, reg_value, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			usb.usbXcvrMode = mode;
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the USB transceiver's current operating mode.
+ *
+ * @param       handle          device handle from open() call
+ * @param       mode            current operating mode
+ *
+ * @return      PMIC_SUCCESS    if the USB transceiver's operating mode
+ *                              was successfully retrieved
+ */
+PMIC_STATUS pmic_convity_usb_get_xcvr(const PMIC_CONVITY_HANDLE handle,
+				      PMIC_CONVITY_USB_TRANSCEIVER_MODE *
+				      const mode)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) &&
+	    (usb.handle_state == HANDLE_IN_USE) &&
+	    (mode != (PMIC_CONVITY_USB_TRANSCEIVER_MODE *) NULL)) {
+		*mode = usb.usbXcvrMode;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Set the Data Line Pulse duration (in milliseconds) for the USB OTG
+ * Session Request Protocol.
+ *
+ * For mc13783, this feature is not supported.So return PMIC_NOT_SUPPORTED
+ *
+ * @param       handle          device handle from open() call
+ * @param       duration        the data line pulse duration (ms)
+ *
+ * @return      PMIC_SUCCESS    if the pulse duration was successfully set
+ */
+PMIC_STATUS pmic_convity_usb_otg_set_dlp_duration(const PMIC_CONVITY_HANDLE
+						  handle,
+						  const unsigned int duration)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+
+	/* The setting of the dlp duration is not supported by the mc13783 PMIC hardware. */
+
+	/* No critical section is required. */
+
+	if ((handle != usb.handle)
+	    || (usb.handle_state != HANDLE_IN_USE)) {
+		/* Must return error indication for invalid handle parameter to be
+		 * consistent with other APIs.
+		 */
+		rc = PMIC_ERROR;
+	}
+
+	return rc;
+}
+
+/*!
+ * Get the current Data Line Pulse duration (in milliseconds) for the USB
+ * OTG Session Request Protocol.
+ *
+ * @param       handle          device handle from open() call
+ * @param       duration        the data line pulse duration (ms)
+ *
+ * @return      PMIC_SUCCESS    if the pulse duration was successfully obtained
+ */
+PMIC_STATUS pmic_convity_usb_otg_get_dlp_duration(const PMIC_CONVITY_HANDLE
+						  handle,
+						  unsigned int *const duration)
+{
+	PMIC_STATUS rc = PMIC_NOT_SUPPORTED;
+
+	/* The setting of dlp duration is not supported by the mc13783 PMIC hardware. */
+
+	/* No critical section is required. */
+
+	if ((handle != usb.handle)
+	    || (usb.handle_state != HANDLE_IN_USE)) {
+		/* Must return error indication for invalid handle parameter to be
+		 * consistent with other APIs.
+		 */
+		rc = PMIC_ERROR;
+	}
+
+	return rc;
+}
+
+/*!
+ * Set the USB On-The-Go (OTG) configuration.
+ *
+ * @param       handle          device handle from open() call
+ * @param       cfg             desired USB OTG configuration
+ *
+ * @return      PMIC_SUCCESS    if the OTG configuration was successfully set
+ */
+PMIC_STATUS pmic_convity_usb_otg_set_config(const PMIC_CONVITY_HANDLE handle,
+					    const PMIC_CONVITY_USB_OTG_CONFIG
+					    cfg)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+		if (cfg & USB_OTG_SE0CONN) {
+			reg_value = SET_BITS(regUSB0, SE0_CONN, 1);
+			reg_mask = SET_BITS(regUSB0, SE0_CONN, 1);
+		}
+		if (cfg & USBXCVREN) {
+			reg_value |= SET_BITS(regUSB0, USBXCVREN, 1);
+			reg_mask |= SET_BITS(regUSB0, USBXCVREN, 1);
+		}
+
+		if (cfg & USB_OTG_DLP_SRP) {
+			reg_value |= SET_BITS(regUSB0, DLP_SRP, 1);
+			reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1);
+		}
+
+		if (cfg & USB_PULL_OVERRIDE) {
+			reg_value |= SET_BITS(regUSB0, PULLOVR, 1);
+			reg_mask |= SET_BITS(regUSB0, PULLOVR, 1);
+		}
+
+		if (cfg & USB_PU) {
+			reg_value |= SET_BITS(regUSB0, USB_PU, 1);
+			reg_mask |= SET_BITS(regUSB0, USB_PU, 1);
+		}
+
+		if (cfg & USB_UDM_PD) {
+			reg_value |= SET_BITS(regUSB0, UDM_PD, 1);
+			reg_mask |= SET_BITS(regUSB0, UDM_PD, 1);
+		}
+
+		if (cfg & USB_UDP_PD) {
+			reg_value |= SET_BITS(regUSB0, UDP_PD, 1);
+			reg_mask |= SET_BITS(regUSB0, UDP_PD, 1);
+		}
+
+		if (cfg & USB_DP150K_PU) {
+			reg_value |= SET_BITS(regUSB0, DP150K_PU, 1);
+			reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1);
+		}
+
+		if (cfg & USB_USBCNTRL) {
+			reg_value |= SET_BITS(regUSB0, USBCNTRL, 1);
+			reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1);
+		}
+
+		if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 0);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 1);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 2);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 3);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 4);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 5);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 6);
+		}
+		if (cfg & USB_VBUS_CURRENT_LIMIT_LOW) {
+			reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 7);
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 7);
+		}
+
+		if (cfg & USB_VBUS_PULLDOWN) {
+			reg_value |= SET_BITS(regUSB0, VBUSPDENB, 1);
+			reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1);
+		}
+
+		rc = pmic_write_reg(REG_USB, reg_value, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			if ((cfg & USB_VBUS_CURRENT_LIMIT_HIGH) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) ||
+			    (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS)) {
+				/* Make sure that the VBUS current limit state is
+				 * correctly set to either USB_VBUS_CURRENT_LIMIT_HIGH
+				 * or USB_VBUS_CURRENT_LIMIT_LOW but never both at the
+				 * same time.
+				 *
+				 * We guarantee this by first clearing both of the
+				 * status bits and then resetting the correct one.
+				 */
+				usb.usbOtgCfg &=
+				    ~(USB_VBUS_CURRENT_LIMIT_HIGH |
+				      USB_VBUS_CURRENT_LIMIT_LOW |
+				      USB_VBUS_CURRENT_LIMIT_LOW_10MS |
+				      USB_VBUS_CURRENT_LIMIT_LOW_20MS |
+				      USB_VBUS_CURRENT_LIMIT_LOW_30MS |
+				      USB_VBUS_CURRENT_LIMIT_LOW_40MS |
+				      USB_VBUS_CURRENT_LIMIT_LOW_50MS |
+				      USB_VBUS_CURRENT_LIMIT_LOW_60MS);
+			}
+
+			usb.usbOtgCfg |= cfg;
+		}
+	}
+	//}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Clears the USB On-The-Go (OTG) configuration. Multiple configuration settings
+ * may be OR'd together in a single call. However, selecting conflicting
+ * settings (e.g., multiple VBUS current limits) will result in undefined
+ * behavior.
+ *
+ * @param   handle          Device handle from open() call.
+ * @param   cfg             USB OTG configuration settings to be cleared.
+ *
+ * @retval      PMIC_SUCCESS         If the OTG configuration was successfully
+ *                                   cleared.
+ * @retval      PMIC_PARAMETER_ERROR If the handle is invalid.
+ * @retval      PMIC_NOT_SUPPORTED   If the desired USB OTG configuration is
+ *                                   not supported by the PMIC hardware.
+ */
+PMIC_STATUS pmic_convity_usb_otg_clear_config(const PMIC_CONVITY_HANDLE handle,
+					      const PMIC_CONVITY_USB_OTG_CONFIG
+					      cfg)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask = 0;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) {
+		/* if ((cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) ||
+		   (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) ||
+		   (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) ||
+		   (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) ||
+		   (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) ||
+		   (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS))
+		   {
+		   rc = PMIC_NOT_SUPPORTED;
+		   } */
+		//else
+
+		if (cfg & USB_OTG_SE0CONN) {
+			reg_mask = SET_BITS(regUSB0, SE0_CONN, 1);
+		}
+
+		if (cfg & USB_OTG_DLP_SRP) {
+			reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1);
+		}
+
+		if (cfg & USB_DP150K_PU) {
+			reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1);
+		}
+
+		if (cfg & USB_PULL_OVERRIDE) {
+			reg_mask |= SET_BITS(regUSB0, PULLOVR, 1);
+		}
+
+		if (cfg & USB_PU) {
+
+			reg_mask |= SET_BITS(regUSB0, USB_PU, 1);
+		}
+
+		if (cfg & USB_UDM_PD) {
+
+			reg_mask |= SET_BITS(regUSB0, UDM_PD, 1);
+		}
+
+		if (cfg & USB_UDP_PD) {
+
+			reg_mask |= SET_BITS(regUSB0, UDP_PD, 1);
+		}
+
+		if (cfg & USB_USBCNTRL) {
+			reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1);
+		}
+
+		if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 0);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 1);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 2);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 3);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 4);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 5);
+		} else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) {
+			reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 6);
+		}
+
+		if (cfg & USB_VBUS_PULLDOWN) {
+			//      reg_value |= SET_BITS(regUSB0, VBUSPDENB, 1);
+			reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1);
+		}
+
+		rc = pmic_write_reg(REG_USB, reg_value, reg_mask);
+
+		if (rc == PMIC_SUCCESS) {
+			usb.usbOtgCfg &= ~cfg;
+		}
+	}
+	//}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the current USB On-The-Go (OTG) configuration.
+ *
+ * @param       handle          device handle from open() call
+ * @param       cfg             the current USB OTG configuration
+ *
+ * @return      PMIC_SUCCESS    if the OTG configuration was successfully
+ *                              retrieved
+ */
+PMIC_STATUS pmic_convity_usb_otg_get_config(const PMIC_CONVITY_HANDLE handle,
+					    PMIC_CONVITY_USB_OTG_CONFIG *
+					    const cfg)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == usb.handle) &&
+	    (usb.handle_state == HANDLE_IN_USE) &&
+	    (cfg != (PMIC_CONVITY_USB_OTG_CONFIG *) NULL)) {
+		*cfg = usb.usbOtgCfg;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*@}*/
+
+/**************************************************************************
+ * RS-232-specific configuration and setup functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name RS-232 Serial Connectivity APIs
+ * Functions for controlling RS-232 serial connectivity.
+ */
+/*@{*/
+
+/*!
+ * Set the connectivity interface to the selected RS-232 operating
+ * configuration. Note that the RS-232 operating mode will be automatically
+ * overridden if the USB_EN is asserted at any time (e.g., when a USB device
+ * is attached). However, we will also automatically return to the RS-232
+ * mode once the USB device is detached.
+ *
+ * @param       handle          device handle from open() call
+ * @param       cfgInternal     RS-232 transceiver internal connections
+ * @param       cfgExternal     RS-232 transceiver external connections
+ *
+ * @return      PMIC_SUCCESS    if the requested mode was set
+ */
+PMIC_STATUS pmic_convity_rs232_set_config(const PMIC_CONVITY_HANDLE handle,
+					  const PMIC_CONVITY_RS232_INTERNAL
+					  cfgInternal,
+					  const PMIC_CONVITY_RS232_EXTERNAL
+					  cfgExternal)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value0 = 0, reg_value1 = 0;
+	unsigned int reg_mask = SET_BITS(regUSB1, RSPOL, 1);
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == rs_232.handle) && (rs_232.handle_state == HANDLE_IN_USE)) {
+		rc = PMIC_SUCCESS;
+
+		/* Validate the calling parameters. */
+		/*if ((cfgInternal !=  RS232_TX_USE0VM_RX_UDATVP) &&
+		   (cfgInternal != RS232_TX_RX_INTERNAL_DEFAULT) && (cfgInternal !=  RS232_TX_UDATVP_RX_URXVM))
+		   {
+
+		   rc = PMIC_NOT_SUPPORTED;
+		   } */
+		if (cfgInternal == RS232_TX_USE0VM_RX_UDATVP) {
+
+			reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1);
+
+		} else if (cfgInternal == RS232_TX_RX_INTERNAL_DEFAULT) {
+
+			reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1);
+			reg_mask |= SET_BITS(regUSB1, RSPOL, 1);
+
+		} else if (cfgInternal == RS232_TX_UDATVP_RX_URXVM) {
+
+			reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 2);
+			reg_value1 |= SET_BITS(regUSB1, RSPOL, 1);
+
+		} else if ((cfgExternal == RS232_TX_UDM_RX_UDP) ||
+			   (cfgExternal == RS232_TX_RX_EXTERNAL_DEFAULT)) {
+			/* Configure for TX on D+ and RX on D-. */
+			reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1);
+			reg_value1 |= SET_BITS(regUSB1, RSPOL, 0);
+		} else if (cfgExternal != RS232_TX_UDM_RX_UDP) {
+			/* Any other RS-232 configuration is an error. */
+			rc = PMIC_ERROR;
+		}
+
+		if (rc == PMIC_SUCCESS) {
+			/* Configure for TX on D- and RX on D+. */
+			rc = pmic_write_reg(REG_USB, reg_value0, reg_mask);
+
+			rc = pmic_write_reg(REG_CHARGE_USB_SPARE,
+					    reg_value1, reg_mask);
+
+			if (rc == PMIC_SUCCESS) {
+				rs_232.rs232CfgInternal = cfgInternal;
+				rs_232.rs232CfgExternal = cfgExternal;
+			}
+		}
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*!
+ * Get the connectivity interface's current RS-232 operating configuration.
+ *
+ * @param       handle          device handle from open() call
+ * @param       cfgInternal     RS-232 transceiver internal connections
+ * @param       cfgExternal     RS-232 transceiver external connections
+ *
+ * @return      PMIC_SUCCESS    if the requested mode was retrieved
+ */
+PMIC_STATUS pmic_convity_rs232_get_config(const PMIC_CONVITY_HANDLE handle,
+					  PMIC_CONVITY_RS232_INTERNAL *
+					  const cfgInternal,
+					  PMIC_CONVITY_RS232_EXTERNAL *
+					  const cfgExternal)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle == rs_232.handle) &&
+	    (rs_232.handle_state == HANDLE_IN_USE) &&
+	    (cfgInternal != (PMIC_CONVITY_RS232_INTERNAL *) NULL) &&
+	    (cfgExternal != (PMIC_CONVITY_RS232_EXTERNAL *) NULL)) {
+		*cfgInternal = rs_232.rs232CfgInternal;
+		*cfgExternal = rs_232.rs232CfgExternal;
+
+		rc = PMIC_SUCCESS;
+	}
+
+	/* Exit the critical section. */
+	up(&mutex);
+
+	return rc;
+}
+
+/*@}*/
+
+/**************************************************************************
+ * CEA-936-specific configuration and setup functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name CEA-936 Connectivity APIs
+ * Functions for controlling CEA-936 connectivity.
+ */
+/*@{*/
+
+/*!
+ * Signal the attached device to exit the current CEA-936 operating mode.
+ * Returns an error if the current operating mode is not CEA-936.
+ *
+ * @param       handle          device handle from open() call
+ * @param       signal          type of exit signal to be sent
+ *
+ * @return      PMIC_SUCCESS    if exit signal was sent
+ */
+PMIC_STATUS pmic_convity_cea936_exit_signal(const PMIC_CONVITY_HANDLE handle,
+					    const
+					    PMIC_CONVITY_CEA936_EXIT_SIGNAL
+					    signal)
+{
+	PMIC_STATUS rc = PMIC_ERROR;
+	unsigned int reg_value = 0;
+	unsigned int reg_mask =
+	    SET_BITS(regUSB0, IDPD, 1) | SET_BITS(regUSB0, IDPULSE, 1);
+
+	/* Use a critical section to maintain a consistent state. */
+	if (down_interruptible(&mutex))
+		return PMIC_SYSTEM_ERROR_EINTR;
+
+	if ((handle != cea_936.handle)
+	    || (cea_936.handle_state != HANDLE_IN_USE)) {
+		/* Must return error indication for invalid handle parameter to be
+		 * consistent with other APIs.
+		 */
+		rc = PMIC_ERROR;
+	} else if (signal == CEA936_UID_PULLDOWN_6MS) {
+		reg_value =
+		    SET_BITS(regUSB0, IDPULSE, 0) | SET_BITS(regUSB0, IDPD, 0);
+	} else if (signal == CEA936_UID_PULLDOWN_6MS) {
+		reg_value = SET_BITS(regUSB0, IDPULSE, 1);
+	} else if (signal == CEA936_UID_PULLDOWN) {
+		reg_value = SET_BITS(regUSB0, IDPD, 1);
+	} else if (signal == CEA936_UDMPULSE) {
+		reg_value = SET_BITS(regUSB0, DMPULSE, 1);
+	}
+
+	rc = pmic_write_reg(REG_USB, reg_value, reg_mask);
+
+	up(&mutex);
+
+	return rc;
+}
+
+/*@}*/
+
+/**************************************************************************
+ * Static functions.
+ **************************************************************************
+ */
+
+/*!
+ * @name Connectivity Driver Internal Support Functions
+ * These non-exported internal functions are used to support the functionality
+ * of the exported connectivity APIs.
+ */
+/*@{*/
+
+/*!
+ * This internal helper function sets the desired operating mode (either USB
+ * OTG or RS-232). It must be called with the mutex already acquired.
+ *
+ * @param       mode               the desired operating mode (USB or RS232)
+ *
+ * @return      PMIC_SUCCESS       if the desired operating mode was set
+ * @return      PMIC_NOT_SUPPORTED if the desired operating mode is invalid
+ */
+static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode)
+{
+	unsigned int reg_value0 = 0, reg_value1 = 0;
+	unsigned int reg_mask0 = 0, reg_mask1 = 0;
+
+	//unsigned int reg_mask1 = SET_BITS(regUSB1, VBUSEN, 1);
+
+	PMIC_STATUS rc = PMIC_SUCCESS;
+
+	switch (mode) {
+	case USB:
+		/* For the USB mode, we start by tri-stating the USB bus (by
+		 * setting VBUSEN = 0) until a device is connected (i.e.,
+		 * until we receive a 4.4V rising edge event). All pull-up
+		 * and pull-down resistors are also disabled until a USB
+		 * device is actually connected and we have determined which
+		 * device is the host and the desired USB bus speed.
+		 *
+		 * Also tri-state the RS-232 buffers (by setting RSTRI = 1).
+		 * This prevents the hardware from automatically returning to
+		 * the RS-232 mode when the USB device is detached.
+		 */
+
+		reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 0);
+		reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7);
+
+		/*reg_value1 = SET_BITS(regUSB1, RSTRI, 1); */
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+		/*      if (rc == PMIC_SUCCESS) {
+		   CHECK_ERROR(pmic_write_reg
+		   (REG_CHARGE_USB_SPARE,
+		   reg_value1, reg_mask1));
+		   } */
+
+		break;
+
+	case RS232_1:
+		/* For the RS-232 mode, we tri-state the USB bus (by setting
+		 * VBUSEN = 0) and enable the RS-232 transceiver (by setting
+		 * RS232ENB = 0).
+		 *
+		 * Note that even in the RS-232 mode, if a USB device is
+		 * plugged in, we will receive a 4.4V rising edge event which
+		 * will automatically disable the RS-232 transceiver and
+		 * tri-state the RS-232 buffers. This allows us to temporarily
+		 * switch over to USB mode while the USB device is attached.
+		 * The RS-232 transceiver and buffers will be automatically
+		 * re-enabled when the USB device is detached.
+		 */
+
+		/* Explicitly disconnect all of the USB pull-down resistors
+		 * and the VUSB power regulator here just to be safe.
+		 *
+		 * But we do connect the internal pull-up resistor on USB_D+
+		 * to avoid having an extra load on the USB_D+ line when in
+		 * RS-232 mode.
+		 */
+
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1) |
+		    SET_BITS(regUSB0, VBUSPDENB, 1) |
+		    SET_BITS(regUSB0, USB_PU, 1);
+		reg_mask0 =
+		    SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0,
+								    VBUSPDENB,
+								    1) |
+		    SET_BITS(regUSB0, USB_PU, 1);
+
+		reg_value1 = SET_BITS(regUSB1, RSPOL, 0);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+
+		if (rc == PMIC_SUCCESS) {
+			CHECK_ERROR(pmic_write_reg
+				    (REG_CHARGE_USB_SPARE,
+				     reg_value1, reg_mask1));
+		}
+		break;
+
+	case RS232_2:
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 2) |
+		    SET_BITS(regUSB0, VBUSPDENB, 1) |
+		    SET_BITS(regUSB0, USB_PU, 1);
+		reg_mask0 =
+		    SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0,
+								    VBUSPDENB,
+								    1) |
+		    SET_BITS(regUSB0, USB_PU, 1);
+
+		reg_value1 = SET_BITS(regUSB1, RSPOL, 1);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+
+		if (rc == PMIC_SUCCESS) {
+			CHECK_ERROR(pmic_write_reg
+				    (REG_CHARGE_USB_SPARE,
+				     reg_value1, reg_mask1));
+		}
+		break;
+
+	case CEA936_MONO:
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 4);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+		break;
+
+	case CEA936_STEREO:
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 5);
+		reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+		break;
+
+	case CEA936_TEST_RIGHT:
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 6);
+		reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+		break;
+
+	case CEA936_TEST_LEFT:
+		reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 7);
+		reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7);
+
+		rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0);
+		break;
+
+	default:
+		rc = PMIC_NOT_SUPPORTED;
+	}
+
+	if (rc == PMIC_SUCCESS) {
+		if (mode == USB) {
+			usb.mode = mode;
+		} else if ((mode == RS232_1) || (mode == RS232_1)) {
+			rs_232.mode = mode;
+		} else if ((mode == CEA936_MONO) || (mode == CEA936_STEREO) ||
+			   (mode == CEA936_TEST_RIGHT)
+			   || (mode == CEA936_TEST_LEFT)) {
+			cea_936.mode = mode;
+		}
+	}
+
+	return rc;
+}
+
+/*!
+ * This internal helper function deregisters all of the currently registered
+ * callback events. It must be called with the mutual exclusion spinlock
+ * already acquired.
+ *
+ * We've defined the event and callback deregistration code here as a separate
+ * function because it can be called by either the pmic_convity_close() or the
+ * pmic_convity_clear_callback() APIs. We also wanted to avoid any possible
+ * issues with having the same thread calling spin_lock_irq() twice.
+ *
+ * Note that the mutex must have already been acquired. We will also acquire
+ * the spinlock here to avoid any possible race conditions with the interrupt
+ * handler.
+ *
+ * @return      PMIC_SUCCESS    if all of the callback events were cleared
+ */
+static PMIC_STATUS pmic_convity_deregister_all(void)
+{
+	unsigned long flags;
+	PMIC_STATUS rc = PMIC_SUCCESS;
+
+	/* Deregister each of the PMIC events that we had previously
+	 * registered for by using pmic_event_subscribe().
+	 */
+
+	if ((usb.eventMask & USB_DETECT_MINI_A) ||
+	    (usb.eventMask & USB_DETECT_MINI_B) ||
+	    (usb.eventMask & USB_DETECT_NON_USB_ACCESSORY) ||
+	    (usb.eventMask & USB_DETECT_FACTORY_MODE)) {
+		//EVENT_AB_DETI or EVENT_IDI
+		eventNotify.func = pmic_convity_event_handler;
+		eventNotify.param = (void *)(CORE_EVENT_ABDET);
+
+		if (pmic_event_unsubscribe(EVENT_IDI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			/* Also acquire the spinlock here to avoid any possible race
+			 * conditions with the interrupt handler.
+			 */
+
+			spin_lock_irqsave(&lock, flags);
+
+			usb.eventMask &= ~(USB_DETECT_MINI_A |
+					   USB_DETECT_MINI_B |
+					   USB_DETECT_NON_USB_ACCESSORY |
+					   USB_DETECT_FACTORY_MODE);
+
+			spin_unlock_irqrestore(&lock, flags);
+		} else {
+			pr_debug
+			    ("%s: pmic_event_unsubscribe() for EVENT_AB_DETI failed\n",
+			     __FILE__);
+			rc = PMIC_ERROR;
+		}
+	}
+
+	else if ((usb.eventMask & USB_DETECT_0V8_RISE) ||
+		 (usb.eventMask & USB_DETECT_0V8_FALL)) {
+		//EVENT_USB_08VI or EVENT_USBI
+		eventNotify.func = pmic_convity_event_handler;
+		eventNotify.param = (void *)(CORE_EVENT_0V8);
+		if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			/* Also acquire the spinlock here to avoid any possible race
+			 * conditions with the interrupt handler.
+			 */
+			spin_lock_irqsave(&lock, flags);
+
+			usb.eventMask &= ~(USB_DETECT_0V8_RISE |
+					   USB_DETECT_0V8_FALL);
+
+			spin_unlock_irqrestore(&lock, flags);
+		} else {
+			pr_debug
+			    ("%s: pmic_event_unsubscribe() for EVENT_USB_08VI failed\n",
+			     __FILE__);
+			rc = PMIC_ERROR;
+		}
+
+	}
+
+	else if ((usb.eventMask & USB_DETECT_2V0_RISE) ||
+		 (usb.eventMask & USB_DETECT_2V0_FALL)) {
+		//EVENT_USB_20VI or EVENT_USBI
+		eventNotify.func = pmic_convity_event_handler;
+		eventNotify.param = (void *)(CORE_EVENT_2V0);
+		if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) ==
+		    PMIC_SUCCESS) {
+			/* Also acquire the spinlock here to avoid any possible race
+			 * conditions with the interrupt handler.
+			 */
+			spin_lock_irqsave(&lock, flags);
+
+			usb.eventMask &= ~(USB_DETECT_2V0_RISE |
+					   USB_DETECT_2V0_FALL);
+
+			spin_unlock_irqrestore(&lock, flags);
+		} else {
+			pr_debug
+			    ("%s: pmic_event_unsubscribe() for EVENT_USB_20VI failed\n",
+			     __FILE__);
+			rc = PMIC_ERROR;
+		}
+	}
+
+	else if ((usb.eventMask & USB_DETECT_4V4_RISE) ||
+		 (usb.eventMask & USB_DETECT_4V4_FALL)) {
+
+		//EVENT_USB_44VI or EVENT_USBI
+		eventNotify.func = pmic_convity_event_handler;
+		eventNotify.param = (void *)(CORE_EVENT_4V4);
+
+		if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) ==
+		    PMIC_SUCCESS) {
+
+			/* Also acquire the spinlock here to avoid any possible race
+			 * conditions with the interrupt handler.
+			 */
+			spin_lock_irqsave(&lock, flags);
+
+			usb.eventMask &= ~(USB_DETECT_4V4_RISE |
+					   USB_DETECT_4V4_FALL);
+
+			spin_unlock_irqrestore(&lock, flags);
+		} else {
+			pr_debug
+			    ("%s: pmic_event_unsubscribe() for EVENT_USB_44VI failed\n",
+			     __FILE__);
+			rc = PMIC_ERROR;
+		}
+	}
+
+	if (rc == PMIC_SUCCESS) {
+		/* Also acquire the spinlock here to avoid any possible race
+		 * conditions with the interrupt handler.
+		 */
+		spin_lock_irqsave(&lock, flags);
+
+		/* Restore the initial reset values for the callback function
+		 * and event mask parameters. This should be NULL and zero,
+		 * respectively.
+		 *
+		 * Note that we wait until the end here to fully reset everything
+		 * just in case some of the pmic_event_unsubscribe() calls above
+		 * failed for some reason (which normally shouldn't happen).
+		 */
+		usb.callback = reset.callback;
+		usb.eventMask = reset.eventMask;
+
+		spin_unlock_irqrestore(&lock, flags);
+	}
+	return rc;
+}
+
+/*!
+ * This is the default event handler for all connectivity-related events
+ * and hardware interrupts.
+ *
+ * @param       param           event ID
+ */
+static void pmic_convity_event_handler(void *param)
+{
+	unsigned long flags;
+
+	/* Update the global list of active interrupt events. */
+	spin_lock_irqsave(&lock, flags);
+	eventID |= (PMIC_CORE_EVENT) (param);
+	spin_unlock_irqrestore(&lock, flags);
+
+	/* Schedule the tasklet to be run as soon as it is convenient to do so. */
+	schedule_work(&convityTasklet);
+}
+
+/*!
+ * @brief This is the connectivity driver tasklet that handles interrupt events.
+ *
+ * This function is scheduled by the connectivity driver interrupt handler
+ * pmic_convity_event_handler() to complete the processing of all of the
+ * connectivity-related interrupt events.
+ *
+ * Since this tasklet runs with interrupts enabled, we can safely call
+ * the ADC driver, if necessary, to properly detect the type of USB connection
+ * that is being made and to call any user-registered callback functions.
+ *
+ * @param   arg                The parameter that was provided above in
+ *                                  the DECLARE_TASKLET() macro (unused).
+ */
+static void pmic_convity_tasklet(struct work_struct *work)
+{
+
+	PMIC_CONVITY_EVENTS activeEvents = 0;
+	unsigned long flags = 0;
+
+	/* Check the interrupt sense bits to determine exactly what
+	 * event just occurred.
+	 */
+	if (eventID & CORE_EVENT_4V4) {
+		spin_lock_irqsave(&lock, flags);
+		eventID &= ~CORE_EVENT_4V4;
+		spin_unlock_irqrestore(&lock, flags);
+
+		activeEvents |= pmic_check_sensor(SENSE_USB4V4S) ?
+		    USB_DETECT_4V4_RISE : USB_DETECT_4V4_FALL;
+
+		if (activeEvents & ~usb.eventMask) {
+			/* The default handler for 4.4 V rising/falling edge detection
+			 * is to simply ignore the event.
+			 */
+			;
+		}
+	}
+	if (eventID & CORE_EVENT_2V0) {
+		spin_lock_irqsave(&lock, flags);
+		eventID &= ~CORE_EVENT_2V0;
+		spin_unlock_irqrestore(&lock, flags);
+
+		activeEvents |= pmic_check_sensor(SENSE_USB2V0S) ?
+		    USB_DETECT_2V0_RISE : USB_DETECT_2V0_FALL;
+		if (activeEvents & ~usb.eventMask) {
+			/* The default handler for 2.0 V rising/falling edge detection
+			 * is to simply ignore the event.
+			 */
+			;
+		}
+	}
+	if (eventID & CORE_EVENT_0V8) {
+		spin_lock_irqsave(&lock, flags);
+		eventID &= ~CORE_EVENT_0V8;
+		spin_unlock_irqrestore(&lock, flags);
+
+		activeEvents |= pmic_check_sensor(SENSE_USB0V8S) ?
+		    USB_DETECT_0V8_RISE : USB_DETECT_0V8_FALL;
+
+		if (activeEvents & ~usb.eventMask) {
+			/* The default handler for 0.8 V rising/falling edge detection
+			 * is to simply ignore the event.
+			 */
+			;
+		}
+	}
+	if (eventID & CORE_EVENT_ABDET) {
+		spin_lock_irqsave(&lock, flags);
+		eventID &= ~CORE_EVENT_ABDET;
+		spin_unlock_irqrestore(&lock, flags);
+
+		activeEvents |= pmic_check_sensor(SENSE_ID_GNDS) ?
+		    USB_DETECT_MINI_A : 0;
+
+		activeEvents |= pmic_check_sensor(SENSE_ID_FLOATS) ?
+		    USB_DETECT_MINI_B : 0;
+	}
+
+	/* Begin a critical section here so that we don't register/deregister
+	 * for events or open/close the connectivity driver while the existing
+	 * event handler (if it is currently defined) is in the middle of handling
+	 * the current event.
+	 */
+	spin_lock_irqsave(&lock, flags);
+
+	/* Finally, call the user-defined callback function if required. */
+	if ((usb.handle_state == HANDLE_IN_USE) &&
+	    (usb.callback != NULL) && (activeEvents & usb.eventMask)) {
+		(*usb.callback) (activeEvents);
+	}
+
+	spin_unlock_irqrestore(&lock, flags);
+}
+
+/*@}*/
+
+/**************************************************************************
+ * Module initialization and termination functions.
+ *
+ * Note that if this code is compiled into the kernel, then the
+ * module_init() function will be called within the device_initcall()
+ * group.
+ **************************************************************************
+ */
+
+/*!
+ * @name Connectivity Driver Loading/Unloading Functions
+ * These non-exported internal functions are used to support the connectivity
+ * device driver initialization and de-initialization operations.
+ */
+/*@{*/
+
+/*!
+ * @brief This is the connectivity device driver initialization function.
+ *
+ * This function is called by the kernel when this device driver is first
+ * loaded.
+ */
+static int __init mc13783_pmic_convity_init(void)
+{
+	printk(KERN_INFO "PMIC Connectivity driver loading..\n");
+
+	return 0;
+}
+
+/*!
+ * @brief This is the Connectivity device driver de-initialization function.
+ *
+ * This function is called by the kernel when this device driver is about
+ * to be unloaded.
+ */
+static void __exit mc13783_pmic_convity_exit(void)
+{
+	printk(KERN_INFO "PMIC Connectivity driver unloading\n");
+
+	/* Close the device handle if it is still open. This will also
+	 * deregister any callbacks that may still be active.
+	 */
+	if (usb.handle_state == HANDLE_IN_USE) {
+		pmic_convity_close(usb.handle);
+	} else if (usb.handle_state == HANDLE_IN_USE) {
+		pmic_convity_close(rs_232.handle);
+	} else if (usb.handle_state == HANDLE_IN_USE) {
+		pmic_convity_close(cea_936.handle);
+	}
+
+	/* Reset the PMIC Connectivity register to it's power on state.
+	 * We should do this when unloading the module so that we don't
+	 * leave the hardware in a state which could cause problems when
+	 * no device driver is loaded.
+	 */
+	pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0, REG_FULLMASK);
+	pmic_write_reg(REG_CHARGE_USB_SPARE, RESET_USBCNTRL_REG_1,
+		       REG_FULLMASK);
+	/* Note that there is no need to reset the "convity" device driver
+	 * state structure to the reset state since we are in the final
+	 * stage of unloading the device driver. The device driver state
+	 * structure will be automatically and properly reinitialized if
+	 * this device driver is reloaded.
+	 */
+}
+
+/*@}*/
+
+/*
+ * Module entry points and description information.
+ */
+
+module_init(mc13783_pmic_convity_init);
+module_exit(mc13783_pmic_convity_exit);
+
+MODULE_DESCRIPTION("mc13783 Connectivity device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_light.c b/drivers/mxc/pmic/mc13783/pmic_light.c
new file mode 100644
index 000000000000..c28cbc3386c3
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_light.c
@@ -0,0 +1,2769 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_light.c
+ * @brief This is the main file of PMIC(mc13783) Light and Backlight driver.
+ *
+ * @ingroup PMIC_LIGHT
+ */
+
+/*
+ * Includes
+ */
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/pmic_light.h>
+#include <linux/pmic_status.h>
+#include "pmic_light_defs.h"
+
+#define NB_LIGHT_REG      6
+
+static int pmic_light_major;
+
+/*!
+ * Number of users waiting in suspendq
+ */
+static int swait = 0;
+
+/*!
+ * To indicate whether any of the light devices are suspending
+ */
+static int suspend_flag = 0;
+
+/*!
+ * The suspendq is used to block application calls
+ */
+static wait_queue_head_t suspendq;
+
+static struct class *pmic_light_class;
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_bklit_tcled_master_enable);
+EXPORT_SYMBOL(pmic_bklit_tcled_master_disable);
+EXPORT_SYMBOL(pmic_bklit_master_enable);
+EXPORT_SYMBOL(pmic_bklit_master_disable);
+EXPORT_SYMBOL(pmic_bklit_set_current);
+EXPORT_SYMBOL(pmic_bklit_get_current);
+EXPORT_SYMBOL(pmic_bklit_set_dutycycle);
+EXPORT_SYMBOL(pmic_bklit_get_dutycycle);
+EXPORT_SYMBOL(pmic_bklit_set_cycle_time);
+EXPORT_SYMBOL(pmic_bklit_get_cycle_time);
+EXPORT_SYMBOL(pmic_bklit_set_mode);
+EXPORT_SYMBOL(pmic_bklit_get_mode);
+EXPORT_SYMBOL(pmic_bklit_rampup);
+EXPORT_SYMBOL(pmic_bklit_off_rampup);
+EXPORT_SYMBOL(pmic_bklit_rampdown);
+EXPORT_SYMBOL(pmic_bklit_off_rampdown);
+EXPORT_SYMBOL(pmic_bklit_enable_edge_slow);
+EXPORT_SYMBOL(pmic_bklit_disable_edge_slow);
+EXPORT_SYMBOL(pmic_bklit_get_edge_slow);
+EXPORT_SYMBOL(pmic_bklit_set_strobemode);
+EXPORT_SYMBOL(pmic_tcled_enable);
+EXPORT_SYMBOL(pmic_tcled_disable);
+EXPORT_SYMBOL(pmic_tcled_get_mode);
+EXPORT_SYMBOL(pmic_tcled_ind_set_current);
+EXPORT_SYMBOL(pmic_tcled_ind_get_current);
+EXPORT_SYMBOL(pmic_tcled_ind_set_blink_pattern);
+EXPORT_SYMBOL(pmic_tcled_ind_get_blink_pattern);
+EXPORT_SYMBOL(pmic_tcled_fun_set_current);
+EXPORT_SYMBOL(pmic_tcled_fun_get_current);
+EXPORT_SYMBOL(pmic_tcled_fun_set_cycletime);
+EXPORT_SYMBOL(pmic_tcled_fun_get_cycletime);
+EXPORT_SYMBOL(pmic_tcled_fun_set_dutycycle);
+EXPORT_SYMBOL(pmic_tcled_fun_get_dutycycle);
+EXPORT_SYMBOL(pmic_tcled_fun_blendedramps);
+EXPORT_SYMBOL(pmic_tcled_fun_sawramps);
+EXPORT_SYMBOL(pmic_tcled_fun_blendedbowtie);
+EXPORT_SYMBOL(pmic_tcled_fun_chasinglightspattern);
+EXPORT_SYMBOL(pmic_tcled_fun_strobe);
+EXPORT_SYMBOL(pmic_tcled_fun_rampup);
+EXPORT_SYMBOL(pmic_tcled_get_fun_rampup);
+EXPORT_SYMBOL(pmic_tcled_fun_rampdown);
+EXPORT_SYMBOL(pmic_tcled_get_fun_rampdown);
+EXPORT_SYMBOL(pmic_tcled_fun_triode_on);
+EXPORT_SYMBOL(pmic_tcled_fun_triode_off);
+EXPORT_SYMBOL(pmic_tcled_enable_edge_slow);
+EXPORT_SYMBOL(pmic_tcled_disable_edge_slow);
+EXPORT_SYMBOL(pmic_tcled_enable_half_current);
+EXPORT_SYMBOL(pmic_tcled_disable_half_current);
+EXPORT_SYMBOL(pmic_tcled_enable_audio_modulation);
+EXPORT_SYMBOL(pmic_tcled_disable_audio_modulation);
+EXPORT_SYMBOL(pmic_bklit_set_boost_mode);
+EXPORT_SYMBOL(pmic_bklit_get_boost_mode);
+EXPORT_SYMBOL(pmic_bklit_config_boost_mode);
+EXPORT_SYMBOL(pmic_bklit_gets_boost_mode);
+
+/*!
+ * This is the suspend of power management for the pmic light API.
+ * It suports SAVE and POWER_DOWN state.
+ *
+ * @param        pdev           the device
+ * @param        state          the state
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_light_suspend(struct platform_device *dev, pm_message_t state)
+{
+	suspend_flag = 1;
+	/* switch off all leds and backlights */
+	CHECK_ERROR(pmic_light_init_reg());
+
+	return 0;
+};
+
+/*!
+ * This is the resume of power management for the pmic light API.
+ * It suports RESTORE state.
+ *
+ * @param        dev            the device
+ *
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_light_resume(struct platform_device *pdev)
+{
+	suspend_flag = 0;
+	while (swait > 0) {
+		swait--;
+		wake_up_interruptible(&suspendq);
+	}
+
+	return 0;
+};
+
+/*!
+ * This function enables backlight & tcled.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_tcled_master_enable(void)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	reg_value = BITFVAL(BIT_LEDEN, 1);
+	mask = BITFMASK(BIT_LEDEN);
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables backlight & tcled.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful
+ */
+PMIC_STATUS pmic_bklit_tcled_master_disable(void)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	reg_value = BITFVAL(BIT_LEDEN, 0);
+	mask = BITFMASK(BIT_LEDEN);
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables backlight. Not supported on mc13783
+ * Use pmic_bklit_tcled_master_enable.
+ *
+ * @return       This function returns PMIC_NOT_SUPPORTED
+ */
+PMIC_STATUS pmic_bklit_master_enable(void)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function disables backlight. Not supported on mc13783
+ * Use pmic_bklit_tcled_master_enable.
+ *
+ * @return       This function returns PMIC_NOT_SUPPORTED
+ */
+PMIC_STATUS pmic_bklit_master_disable(void)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function sets backlight current level.
+ *
+ * @param        channel   Backlight channel
+ * @param        level     Backlight current level, as the following table.
+ *                         @verbatim
+                               level     main & aux   keyboard
+                               ------    -----------  --------
+                                 0         0 mA         0 mA
+                                 1         3 mA         12 mA
+                                 2         6 mA         24 mA
+                                 3         9 mA         36 mA
+                                 4         12 mA        48 mA
+                                 5         15 mA        60 mA
+                                 6         18 mA        72 mA
+                                 7         21 mA        84 mA
+                            @endverbatim
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_set_current(t_bklit_channel channel, unsigned char level)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		value = BITFVAL(BIT_CL_MAIN, level);
+		mask = BITFMASK(BIT_CL_MAIN);
+		break;
+	case BACKLIGHT_LED2:
+		value = BITFVAL(BIT_CL_AUX, level);
+		mask = BITFMASK(BIT_CL_AUX);
+		break;
+	case BACKLIGHT_LED3:
+		value = BITFVAL(BIT_CL_KEY, level);
+		mask = BITFMASK(BIT_CL_KEY);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(LREG_2, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives backlight current level.
+ * The channels are not individually adjustable, hence
+ * the channel parameter is ignored.
+ *
+ * @param        channel   Backlight channel (Ignored because the
+ *                         channels are not individually adjustable)
+ * @param        level     Pointer to store backlight current level result.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_get_current(t_bklit_channel channel,
+				   unsigned char *level)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_CL_MAIN);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_CL_AUX);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_CL_KEY);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_2, &reg_value, mask));
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		*level = BITFEXT(reg_value, BIT_CL_MAIN);
+		break;
+	case BACKLIGHT_LED2:
+		*level = BITFEXT(reg_value, BIT_CL_AUX);
+		break;
+	case BACKLIGHT_LED3:
+		*level = BITFEXT(reg_value, BIT_CL_KEY);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a backlight channel duty cycle.
+ * LED perceived brightness for each zone may be individually set by setting
+ * duty cycle. The default setting is for 0% duty cycle; this keeps all zone
+ * drivers turned off even after the master enable command. Each LED current
+ * sink can be turned on and adjusted for brightness with an independent 4 bit
+ * word for a duty cycle ranging from 0% to 100% in approximately 6.7% steps.
+ *
+ * @param        channel   Backlight channel.
+ * @param        dc        Backlight duty cycle, as the following table.
+ *                         @verbatim
+                                dc        Duty Cycle (% On-time over Cycle Time)
+                               ------    ---------------------------------------
+                                  0        0%
+                                  1        6.7%
+                                  2        13.3%
+                                  3        20%
+                                  4        26.7%
+                                  5        33.3%
+                                  6        40%
+                                  7        46.7%
+                                  8        53.3%
+                                  9        60%
+                                 10        66.7%
+                                 11        73.3%
+                                 12        80%
+                                 13        86.7%
+                                 14        93.3%
+                                 15        100%
+                             @endverbatim
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_set_dutycycle(t_bklit_channel channel, unsigned char dc)
+{
+	unsigned int reg_value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (dc > 15) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_2, &reg_value, PMIC_ALL_BITS));
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		reg_value = reg_value & (~MASK_DUTY_CYCLE);
+		reg_value = reg_value | (dc << BIT_DUTY_CYCLE);
+		break;
+	case BACKLIGHT_LED2:
+		reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_AUX));
+		reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_AUX));
+		break;
+	case BACKLIGHT_LED3:
+		reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_KYD));
+		reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_KYD));
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(LREG_2, reg_value, PMIC_ALL_BITS));
+	return PMIC_SUCCESS;
+
+}
+
+/*!
+ * This function retrives a backlight channel duty cycle.
+ *
+ * @param        channel   Backlight channel.
+ * @param        dc        Pointer to backlight duty cycle.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_get_dutycycle(t_bklit_channel channel, unsigned char *dc)
+{
+	unsigned int reg_value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	CHECK_ERROR(pmic_read_reg(LREG_2, &reg_value, PMIC_ALL_BITS));
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		*dc = (int)((reg_value & (MASK_DUTY_CYCLE))
+			    >> BIT_DUTY_CYCLE);
+
+		break;
+	case BACKLIGHT_LED2:
+		*dc = (int)((reg_value & (MASK_DUTY_CYCLE << INDEX_AUX))
+			    >> (BIT_DUTY_CYCLE + INDEX_AUX));
+		break;
+	case BACKLIGHT_LED3:
+		*dc = (int)((reg_value & (MASK_DUTY_CYCLE <<
+					  INDEX_KYD)) >> (BIT_DUTY_CYCLE +
+							  INDEX_KYD));
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a backlight channel cycle time.
+ * Cycle Time is defined as the period of a complete cycle of
+ * Time_on + Time_off. The default Cycle Time is set to 0.01 seconds such that
+ * the 100 Hz on-off cycling is averaged out by the eye to eliminate
+ * flickering. Additionally, the Cycle Time can be programmed to intentionally
+ * extend the period of on-off cycles for a visual pulsating or blinking effect.
+ *
+ * @param        period    Backlight cycle time, as the following table.
+ *                         @verbatim
+                                period      Cycle Time
+                               --------    ------------
+                                  0          0.01 seconds
+                                  1          0.1 seconds
+                                  2          0.5 seconds
+                                  3          2 seconds
+                             @endverbatim
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_set_cycle_time(unsigned char period)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	if (period > 3) {
+		return PMIC_PARAMETER_ERROR;
+	}
+	mask = BITFMASK(BIT_PERIOD);
+	value = BITFVAL(BIT_PERIOD, period);
+	CHECK_ERROR(pmic_write_reg(LREG_2, value, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives a backlight channel cycle time setting.
+ *
+ * @param        period    Pointer to save backlight cycle time setting result.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_get_cycle_time(unsigned char *period)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mask = BITFMASK(BIT_PERIOD);
+	CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask));
+	*period = BITFEXT(value, BIT_PERIOD);
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets backlight operation mode. There are two modes of
+ * operations: current control and triode mode.
+ * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio
+ * coupling is not available in Triode Mode.
+ *
+ * @param        channel   Backlight channel.
+ * @param        mode      Backlight operation mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_set_mode(t_bklit_channel channel, t_bklit_mode mode)
+{
+	unsigned int reg_value = 0;
+	unsigned int clear_val = 0;
+	unsigned int triode_val = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_0, &reg_value, PMIC_ALL_BITS));
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		clear_val = ~(MASK_TRIODE_MAIN_BL);
+		triode_val = MASK_TRIODE_MAIN_BL;
+		break;
+	case BACKLIGHT_LED2:
+		clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY);
+		triode_val = (MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY);
+		break;
+	case BACKLIGHT_LED3:
+		clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_KEYPAD);
+		triode_val = (MASK_TRIODE_MAIN_BL << INDEX_KEYPAD);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	reg_value = (reg_value & clear_val);
+
+	if (mode == BACKLIGHT_TRIODE_MODE) {
+		reg_value = (reg_value | triode_val);
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, PMIC_ALL_BITS));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets backlight operation mode. There are two modes of
+ * operations: current control and triode mode.
+ * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio
+ * coupling is not available in Triode Mode.
+ *
+ * @param        channel   Backlight channel.
+ * @param        mode      Backlight operation mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_get_mode(t_bklit_channel channel, t_bklit_mode * mode)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_TRIODE_MAIN_BL);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_TRIODE_AUX_BL);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_TRIODE_KEY_BL);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_0, &reg_value, mask));
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		*mode = BITFEXT(reg_value, BIT_TRIODE_MAIN_BL);
+		break;
+	case BACKLIGHT_LED2:
+		*mode = BITFEXT(reg_value, BIT_TRIODE_AUX_BL);
+		break;
+	case BACKLIGHT_LED3:
+		*mode = BITFEXT(reg_value, BIT_TRIODE_KEY_BL);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function starts backlight brightness ramp up function; ramp time is
+ * fixed at 0.5 seconds.
+ *
+ * @param        channel   Backlight channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_rampup(t_bklit_channel channel)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_UP_MAIN_BL);
+		reg_value = BITFVAL(BIT_UP_MAIN_BL, 1);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_UP_AUX_BL);
+		reg_value = BITFVAL(BIT_UP_AUX_BL, 1);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_UP_KEY_BL);
+		reg_value = BITFVAL(BIT_UP_KEY_BL, 1);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function stops backlight brightness ramp up function;
+ *
+ * @param        channel   Backlight channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_off_rampup(t_bklit_channel channel)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_UP_MAIN_BL);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_UP_AUX_BL);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_UP_KEY_BL);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function starts backlight brightness ramp down function; ramp time is
+ * fixed at 0.5 seconds.
+ *
+ * @param        channel   Backlight channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_rampdown(t_bklit_channel channel)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_DOWN_MAIN_BL);
+		reg_value = BITFVAL(BIT_DOWN_MAIN_BL, 1);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_DOWN_AUX_BL);
+		reg_value = BITFVAL(BIT_DOWN_AUX_BL, 1);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_DOWN_KEY_BL);
+		reg_value = BITFVAL(BIT_DOWN_KEY_BL, 1);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function stops backlight brightness ramp down function.
+ *
+ * @param        channel   Backlight channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_off_rampdown(t_bklit_channel channel)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (channel) {
+	case BACKLIGHT_LED1:
+		mask = BITFMASK(BIT_DOWN_MAIN_BL);
+		break;
+	case BACKLIGHT_LED2:
+		mask = BITFMASK(BIT_DOWN_AUX_BL);
+		break;
+	case BACKLIGHT_LED3:
+		mask = BITFMASK(BIT_DOWN_KEY_BL);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables backlight analog edge slowing mode. Analog Edge
+ * Slowing slows down the transient edges to reduce the chance of coupling LED
+ * modulation activity into other circuits. Rise and fall times will be targeted
+ * for approximately 50usec.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_enable_edge_slow(void)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mask = BITFMASK(BIT_SLEWLIMBL);
+	value = BITFVAL(BIT_SLEWLIMBL, 1);
+	CHECK_ERROR(pmic_write_reg(LREG_2, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables backlight analog edge slowing mode. The backlight
+ * drivers will default to an <93>Instant On<94> mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_disable_edge_slow(void)
+{
+	unsigned int mask;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mask = BITFMASK(BIT_SLEWLIMBL);
+	CHECK_ERROR(pmic_write_reg(LREG_2, 0, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets backlight analog edge slowing mode. DThe backlight
+ *
+ * @param        edge      Edge slowing mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_bklit_get_edge_slow(bool * edge)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+	mask = BITFMASK(BIT_SLEWLIMBL);
+	CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask));
+	*edge = (bool) BITFEXT(value, BIT_SLEWLIMBL);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets backlight Strobe Light Pulsing mode.
+ *
+ * @param        channel   Backlight channel.
+ * @param        mode      Strobe Light Pulsing mode.
+ *
+ * @return       This function returns PMIC_NOT_SUPPORTED.
+ */
+PMIC_STATUS pmic_bklit_set_strobemode(t_bklit_channel channel,
+				      t_bklit_strobe_mode mode)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function enables tri-color LED.
+ *
+ * @param        mode      Tri-color LED operation mode.
+ * @param	 bank      Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_enable(t_tcled_mode mode, t_funlight_bank bank)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (mode) {
+	case TCLED_FUN_MODE:
+		switch (bank) {
+		case TCLED_FUN_BANK1:
+			mask = MASK_BK1_FL;
+			value = MASK_BK1_FL;
+			break;
+		case TCLED_FUN_BANK2:
+			mask = MASK_BK2_FL;
+			value = MASK_BK2_FL;
+			break;
+		case TCLED_FUN_BANK3:
+			mask = MASK_BK3_FL;
+			value = MASK_BK3_FL;
+			break;
+		default:
+			return PMIC_PARAMETER_ERROR;
+		}
+		break;
+	case TCLED_IND_MODE:
+		mask = MASK_BK1_FL | MASK_BK2_FL | MASK_BK3_FL;
+		break;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables tri-color LED.
+ *
+ * @param        bank      Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ *
+ */
+PMIC_STATUS pmic_tcled_disable(t_funlight_bank bank)
+{
+	unsigned int mask = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = MASK_BK1_FL;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = MASK_BK2_FL;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = MASK_BK3_FL;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, 0, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives tri-color LED operation mode.
+ *
+ * @param        mode      Pointer to Tri-color LED operation mode.
+ * @param        bank      Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_get_mode(t_tcled_mode * mode, t_funlight_bank bank)
+{
+	unsigned int val;
+	unsigned int mask;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = MASK_BK1_FL;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = MASK_BK2_FL;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = MASK_BK3_FL;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_0, &val, mask));
+
+	if (val) {
+		*mode = TCLED_FUN_MODE;
+	} else {
+		*mode = TCLED_IND_MODE;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a tri-color LED channel current level in indicator mode.
+ *
+ * @param        channel      Tri-color LED channel.
+ * @param        level        Current level.
+ * @param        bank         Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_ind_set_current(t_ind_channel channel,
+				       t_tcled_cur_level level,
+				       t_funlight_bank bank)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (level > TCLED_CUR_LEVEL_4) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		value = BITFVAL(BITS_CL_RED, level);
+		mask = BITFMASK(BITS_CL_RED);
+		break;
+	case TCLED_IND_GREEN:
+		value = BITFVAL(BITS_CL_GREEN, level);
+		mask = BITFMASK(BITS_CL_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		value = BITFVAL(BITS_CL_BLUE, level);
+		mask = BITFMASK(BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg_conf, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives a tri-color LED channel current level
+ * in indicator mode.
+ *
+ * @param        channel      Tri-color LED channel.
+ * @param        level        Pointer to current level.
+ * @param        bank         Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_ind_get_current(t_ind_channel channel,
+				       t_tcled_cur_level * level,
+				       t_funlight_bank bank)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		mask = BITFMASK(BITS_CL_RED);
+		break;
+	case TCLED_IND_GREEN:
+		mask = BITFMASK(BITS_CL_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		mask = BITFMASK(BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask));
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		*level = BITFEXT(value, BITS_CL_RED);
+		break;
+	case TCLED_IND_GREEN:
+		*level = BITFEXT(value, BITS_CL_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		*level = BITFEXT(value, BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a tri-color LED channel blinking pattern in indication
+ * mode.
+ *
+ * @param        channel      Tri-color LED channel.
+ * @param        pattern      Blinking pattern.
+ * @param        skip         If true, skip a cycle after each cycle.
+ * @param        bank         Selected tri-color bank
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_ind_set_blink_pattern(t_ind_channel channel,
+					     t_tcled_ind_blink_pattern pattern,
+					     bool skip, t_funlight_bank bank)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (skip == true) {
+		return PMIC_NOT_SUPPORTED;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		value = BITFVAL(BITS_DC_RED, pattern);
+		mask = BITFMASK(BITS_DC_RED);
+		break;
+	case TCLED_IND_GREEN:
+		value = BITFVAL(BITS_DC_GREEN, pattern);
+		mask = BITFMASK(BITS_DC_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		value = BITFVAL(BITS_DC_BLUE, pattern);
+		mask = BITFMASK(BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg_conf, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives a tri-color LED channel blinking pattern in
+ * indication mode.
+ *
+ * @param        channel      Tri-color LED channel.
+ * @param        pattern      Pointer to Blinking pattern.
+ * @param        skip         Pointer to a boolean varible indicating if skip
+ * @param        bank         Selected tri-color bank
+ *                            a cycle after each cycle.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_ind_get_blink_pattern(t_ind_channel channel,
+					     t_tcled_ind_blink_pattern *
+					     pattern, bool * skip,
+					     t_funlight_bank bank)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		mask = BITFMASK(BITS_DC_RED);
+		break;
+	case TCLED_IND_GREEN:
+		mask = BITFMASK(BITS_DC_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		mask = BITFMASK(BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask));
+
+	switch (channel) {
+	case TCLED_IND_RED:
+		*pattern = BITFEXT(value, BITS_DC_RED);
+		break;
+	case TCLED_IND_GREEN:
+		*pattern = BITFEXT(value, BITS_DC_GREEN);
+		break;
+	case TCLED_IND_BLUE:
+		*pattern = BITFEXT(value, BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a tri-color LED channel current level in Fun Light mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        level        Current level.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_set_current(t_funlight_bank bank,
+				       t_funlight_channel channel,
+				       t_tcled_cur_level level)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (level > TCLED_CUR_LEVEL_4) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		value = BITFVAL(BITS_CL_RED, level);
+		mask = BITFMASK(BITS_CL_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		value = BITFVAL(BITS_CL_GREEN, level);
+		mask = BITFMASK(BITS_CL_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		value = BITFVAL(BITS_CL_BLUE, level);
+		mask = BITFMASK(BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg_conf, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives a tri-color LED channel current level
+ * in Fun Light mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        level        Pointer to current level.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_get_current(t_funlight_bank bank,
+				       t_funlight_channel channel,
+				       t_tcled_cur_level * level)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = BITFMASK(BITS_CL_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = BITFMASK(BITS_CL_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = BITFMASK(BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask));
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		*level = BITFEXT(value, BITS_CL_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		*level = BITFEXT(value, BITS_CL_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		*level = BITFEXT(value, BITS_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets tri-color LED cycle time.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        ct           Cycle time.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_set_cycletime(t_funlight_bank bank,
+					 t_tcled_fun_cycle_time ct)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (ct > TC_CYCLE_TIME_4) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	value = BITFVAL(BIT_PERIOD, ct);
+	mask = BITFMASK(BIT_PERIOD);
+
+	CHECK_ERROR(pmic_write_reg(reg_conf, value, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives tri-color LED cycle time in Fun Light mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        ct           Pointer to cycle time.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_get_cycletime(t_funlight_bank bank,
+					 t_tcled_fun_cycle_time * ct)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask;
+	unsigned int value;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (*ct > TC_CYCLE_TIME_4) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	mask = BITFMASK(BIT_PERIOD);
+	CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask));
+
+	*ct = BITFVAL(BIT_PERIOD, value);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets a tri-color LED channel duty cycle in Fun Light mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        dc           Duty cycle.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_set_dutycycle(t_funlight_bank bank,
+					 t_funlight_channel channel,
+					 unsigned char dc)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		value = BITFVAL(BITS_DC_RED, dc);
+		mask = BITFMASK(BITS_DC_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		value = BITFVAL(BITS_DC_GREEN, dc);
+		mask = BITFMASK(BITS_DC_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		value = BITFVAL(BITS_DC_BLUE, dc);
+		mask = BITFMASK(BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg_conf, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives a tri-color LED channel duty cycle in Fun Light mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        dc           Pointer to duty cycle.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_get_dutycycle(t_funlight_bank bank,
+					 t_funlight_channel channel,
+					 unsigned char *dc)
+{
+	unsigned int reg_conf = 0;
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		reg_conf = LREG_3;
+		break;
+	case TCLED_FUN_BANK2:
+		reg_conf = LREG_4;
+		break;
+	case TCLED_FUN_BANK3:
+		reg_conf = LREG_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = BITFMASK(BITS_DC_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = BITFMASK(BITS_DC_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = BITFMASK(BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask));
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		*dc = BITFEXT(value, BITS_DC_RED);
+		break;
+	case TCLED_FUN_CHANNEL2:
+		*dc = BITFEXT(value, BITS_DC_GREEN);
+		break;
+	case TCLED_FUN_CHANNEL3:
+		*dc = BITFEXT(value, BITS_DC_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Blended Ramp fun light pattern.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        speed        Speed of pattern.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_blendedramps(t_funlight_bank bank,
+					t_tcled_fun_speed speed)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (speed) {
+	case TC_OFF:
+		value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF);
+		break;
+	case TC_SLOW:
+		value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_SLOW);
+		break;
+	case TC_FAST:
+		value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_FAST);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	mask = BITFMASK(BITS_FUN_LIGHT);
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Saw Ramp fun light pattern.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        speed        Speed of pattern.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_sawramps(t_funlight_bank bank,
+				    t_tcled_fun_speed speed)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (speed) {
+	case TC_OFF:
+		value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF);
+		break;
+	case TC_SLOW:
+		value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_SLOW);
+		break;
+	case TC_FAST:
+		value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_FAST);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	mask = BITFMASK(BITS_FUN_LIGHT);
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Blended Bowtie fun light pattern.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        speed        Speed of pattern.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_blendedbowtie(t_funlight_bank bank,
+					 t_tcled_fun_speed speed)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (speed) {
+	case TC_OFF:
+		value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF);
+		break;
+	case TC_SLOW:
+		value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_SLOW);
+		break;
+	case TC_FAST:
+		value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_FAST);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	mask = BITFMASK(BITS_FUN_LIGHT);
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Chasing Lights fun light pattern.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        pattern      Chasing light pattern mode.
+ * @param        speed        Speed of pattern.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_chasinglightspattern(t_funlight_bank bank,
+						t_chaselight_pattern pattern,
+						t_tcled_fun_speed speed)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	if (pattern > BGR) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (speed) {
+	case TC_OFF:
+		value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF);
+		break;
+	case TC_SLOW:
+		if (pattern == PMIC_RGB) {
+			value =
+			    BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_SLOW);
+		} else {
+			value =
+			    BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_SLOW);
+		}
+		break;
+	case TC_FAST:
+		if (pattern == PMIC_RGB) {
+			value =
+			    BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_FAST);
+		} else {
+			value =
+			    BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_FAST);
+		}
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	mask = BITFMASK(BITS_FUN_LIGHT);
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Strobe Mode fun light pattern.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        speed        Speed of pattern.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_strobe(t_funlight_bank bank,
+				  t_funlight_channel channel,
+				  t_tcled_fun_strobe_speed speed)
+{
+	/* not supported on mc13783 */
+
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function initiates Tri-color LED brightness Ramp Up function; Ramp time
+ * is fixed at 1 second.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        rampup       Ramp-up configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_rampup(t_funlight_bank bank,
+				  t_funlight_channel channel, bool rampup)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = LEDR1RAMPUP;
+		value = LEDR1RAMPUP;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = LEDR2RAMPUP;
+		value = LEDR2RAMPUP;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = LEDR3RAMPUP;
+		value = LEDR3RAMPUP;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = mask;
+		value = value;
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = mask * 2;
+		value = value * 2;
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = mask * 4;
+		value = value * 4;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if (!rampup) {
+		value = 0;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets Tri-color LED brightness Ramp Up function; Ramp time
+ * is fixed at 1 second.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        rampup       Ramp-up configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_get_fun_rampup(t_funlight_bank bank,
+				      t_funlight_channel channel, bool * rampup)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = LEDR1RAMPUP;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = LEDR2RAMPUP;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = LEDR3RAMPUP;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = mask;
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = mask * 2;
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = mask * 4;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask));
+	if (value) {
+		*rampup = true;
+	} else {
+		*rampup = false;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Tri-color LED brightness Ramp Down function; Ramp
+ * time is fixed at 1 second.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        rampdown     Ramp-down configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_rampdown(t_funlight_bank bank,
+				    t_funlight_channel channel, bool rampdown)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = LEDR1RAMPDOWN;
+		value = LEDR1RAMPDOWN;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = LEDR2RAMPDOWN;
+		value = LEDR2RAMPDOWN;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = LEDR3RAMPDOWN;
+		value = LEDR3RAMPDOWN;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = mask;
+		value = value;
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = mask * 2;
+		value = value * 2;
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = mask * 4;
+		value = value * 4;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if (!rampdown) {
+		value = 0;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function initiates Tri-color LED brightness Ramp Down function; Ramp
+ * time is fixed at 1 second.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ * @param        rampdown     Ramp-down configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_get_fun_rampdown(t_funlight_bank bank,
+					t_funlight_channel channel,
+					bool * rampdown)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = LEDR1RAMPDOWN;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = LEDR2RAMPDOWN;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = LEDR3RAMPDOWN;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (channel) {
+	case TCLED_FUN_CHANNEL1:
+		mask = mask;
+		break;
+	case TCLED_FUN_CHANNEL2:
+		mask = mask * 2;
+		break;
+	case TCLED_FUN_CHANNEL3:
+		mask = mask * 4;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask));
+	if (value) {
+		*rampdown = true;
+	} else {
+		*rampdown = false;
+	}
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables a Tri-color channel triode mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_triode_on(t_funlight_bank bank,
+				     t_funlight_channel channel)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = MASK_BK1_FL;
+		value = ENABLE_BK1_FL;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = MASK_BK2_FL;
+		value = ENABLE_BK2_FL;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = MASK_BK3_FL;
+		value = ENABLE_BK2_FL;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables a Tri-color LED channel triode mode.
+ *
+ * @param        bank         Tri-color LED bank
+ * @param        channel      Tri-color LED channel.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_fun_triode_off(t_funlight_bank bank,
+				      t_funlight_channel channel)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	switch (bank) {
+	case TCLED_FUN_BANK1:
+		mask = MASK_BK1_FL;
+		break;
+	case TCLED_FUN_BANK2:
+		mask = MASK_BK2_FL;
+		break;
+	case TCLED_FUN_BANK3:
+		mask = MASK_BK3_FL;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables Tri-color LED edge slowing.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_enable_edge_slow(void)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	value = BITFVAL(BIT_SLEWLIMTC, 1);
+	mask = BITFMASK(BIT_SLEWLIMTC);
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables Tri-color LED edge slowing.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_disable_edge_slow(void)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	value = BITFVAL(BIT_SLEWLIMTC, 0);
+	mask = BITFMASK(BIT_SLEWLIMTC);
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables Tri-color LED half current mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_enable_half_current(void)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	value = BITFVAL(BIT_TC1HALF, 1);
+	mask = BITFMASK(BIT_TC1HALF);
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function disables Tri-color LED half current mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_tcled_disable_half_current(void)
+{
+	unsigned int mask = 0;
+	unsigned int value = 0;
+
+	if (suspend_flag == 1) {
+		return -EBUSY;
+	}
+
+	value = BITFVAL(BIT_TC1HALF, 0);
+	mask = BITFMASK(BIT_TC1HALF);
+
+	CHECK_ERROR(pmic_write_reg(LREG_1, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables backlight or Tri-color LED audio modulation.
+ *
+ * @return       This function returns PMIC_NOT_SUPPORTED.
+ */
+PMIC_STATUS pmic_tcled_enable_audio_modulation(t_led_channel channel,
+					       t_aud_path path,
+					       t_aud_gain gain, bool lpf_bypass)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function disables backlight or Tri-color LED audio modulation.
+ *
+ * @return       This function returns PMIC_NOT_SUPPORTED.
+ */
+PMIC_STATUS pmic_tcled_disable_audio_modulation(void)
+{
+	return PMIC_NOT_SUPPORTED;
+}
+
+/*!
+ * This function enables the boost mode.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param       en_dis   Enable or disable the boost mode
+ *
+ * @return      This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_bklit_set_boost_mode(bool en_dis)
+{
+
+	pmic_version_t mc13783_ver;
+	unsigned int mask;
+	unsigned int value;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+
+		if (suspend_flag == 1) {
+			return -EBUSY;
+		}
+
+		value = BITFVAL(BIT_BOOSTEN, en_dis);
+		mask = BITFMASK(BIT_BOOSTEN);
+		CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets the boost mode.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param       en_dis   Enable or disable the boost mode
+ *
+ * @return      This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_bklit_get_boost_mode(bool * en_dis)
+{
+	pmic_version_t mc13783_ver;
+	unsigned int mask;
+	unsigned int value;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+
+		if (suspend_flag == 1) {
+			return -EBUSY;
+		}
+		mask = BITFMASK(BIT_BOOSTEN);
+		CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask));
+		*en_dis = BITFEXT(value, BIT_BOOSTEN);
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function sets boost mode configuration
+ * Only on mc13783 2.0 or higher
+ *
+ * @param    abms      Define adaptive boost mode selection
+ * @param    abr       Define adaptive boost reference
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_bklit_config_boost_mode(unsigned int abms, unsigned int abr)
+{
+	unsigned int conf_boost = 0;
+	unsigned int mask;
+	unsigned int value;
+	pmic_version_t mc13783_ver;
+
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		if (suspend_flag == 1) {
+			return -EBUSY;
+		}
+
+		if (abms > MAX_BOOST_ABMS) {
+			return PMIC_PARAMETER_ERROR;
+		}
+
+		if (abr > MAX_BOOST_ABR) {
+			return PMIC_PARAMETER_ERROR;
+		}
+
+		conf_boost = abms | (abr << 3);
+
+		value = BITFVAL(BITS_BOOST, conf_boost);
+		mask = BITFMASK(BITS_BOOST);
+		CHECK_ERROR(pmic_write_reg(LREG_0, value, mask));
+
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets boost mode configuration
+ * Only on mc13783 2.0 or higher
+ *
+ * @param    abms      Define adaptive boost mode selection
+ * @param    abr       Define adaptive boost reference
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_bklit_gets_boost_mode(unsigned int *abms, unsigned int *abr)
+{
+	unsigned int mask;
+	unsigned int value;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		if (suspend_flag == 1) {
+			return -EBUSY;
+		}
+
+		mask = BITFMASK(BITS_BOOST_ABMS);
+		CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask));
+		*abms = BITFEXT(value, BITS_BOOST_ABMS);
+
+		mask = BITFMASK(BITS_BOOST_ABR);
+		CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask));
+		*abr = BITFEXT(value, BITS_BOOST_ABR);
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function implements IOCTL controls on a PMIC Light device.
+ *
+
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_light_ioctl(struct inode *inode, struct file *file,
+			    unsigned int cmd, unsigned long arg)
+{
+	t_bklit_setting_param *bklit_setting = NULL;
+	t_tcled_enable_param *tcled_setting;
+	t_fun_param *fun_param;
+	t_tcled_ind_param *tcled_ind;
+
+	if (_IOC_TYPE(cmd) != 'p')
+		return -ENOTTY;
+
+	switch (cmd) {
+	case PMIC_BKLIT_TCLED_ENABLE:
+		pmic_bklit_tcled_master_enable();
+		break;
+
+	case PMIC_BKLIT_TCLED_DISABLE:
+		pmic_bklit_tcled_master_disable();
+		break;
+
+	case PMIC_BKLIT_ENABLE:
+		pmic_bklit_master_enable();
+		break;
+
+	case PMIC_BKLIT_DISABLE:
+		pmic_bklit_master_disable();
+		break;
+
+	case PMIC_SET_BKLIT:
+		if ((bklit_setting = kmalloc(sizeof(t_bklit_setting_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg,
+				   sizeof(t_bklit_setting_param))) {
+			kfree(bklit_setting);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_bklit_set_mode(bklit_setting->channel,
+						      bklit_setting->mode),
+				  (kfree(bklit_setting)));
+
+		CHECK_ERROR_KFREE(pmic_bklit_set_current(bklit_setting->channel,
+							 bklit_setting->
+							 current_level),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_set_dutycycle
+				  (bklit_setting->channel,
+				   bklit_setting->duty_cycle),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_set_cycle_time
+				  (bklit_setting->cycle_time),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_set_boost_mode
+				  (bklit_setting->en_dis),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_config_boost_mode
+				  (bklit_setting->abms, bklit_setting->abr),
+				  (kfree(bklit_setting)));
+		if (bklit_setting->edge_slow != false) {
+			CHECK_ERROR_KFREE(pmic_bklit_enable_edge_slow(),
+					  (kfree(bklit_setting)));
+		} else {
+			CHECK_ERROR_KFREE(pmic_bklit_disable_edge_slow(),
+					  (kfree(bklit_setting)));
+		}
+
+		kfree(bklit_setting);
+		break;
+
+	case PMIC_GET_BKLIT:
+		if ((bklit_setting = kmalloc(sizeof(t_bklit_setting_param),
+					     GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+
+		if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg,
+				   sizeof(t_bklit_setting_param))) {
+			kfree(bklit_setting);
+			return -EFAULT;
+		}
+
+		CHECK_ERROR_KFREE(pmic_bklit_get_current(bklit_setting->channel,
+							 &bklit_setting->
+							 current_level),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_get_cycle_time
+				  (&bklit_setting->cycle_time),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_get_dutycycle
+				  (bklit_setting->channel,
+				   &bklit_setting->duty_cycle),
+				  (kfree(bklit_setting)));
+		bklit_setting->strobe = BACKLIGHT_STROBE_NONE;
+		CHECK_ERROR_KFREE(pmic_bklit_get_mode(bklit_setting->channel,
+						      &bklit_setting->mode),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_get_edge_slow
+				  (&bklit_setting->edge_slow),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_get_boost_mode
+				  (&bklit_setting->en_dis),
+				  (kfree(bklit_setting)));
+		CHECK_ERROR_KFREE(pmic_bklit_gets_boost_mode
+				  (&bklit_setting->abms, &bklit_setting->abr),
+				  (kfree(bklit_setting)));
+
+		if (copy_to_user((t_bklit_setting_param *) arg, bklit_setting,
+				 sizeof(t_bklit_setting_param))) {
+			kfree(bklit_setting);
+			return -EFAULT;
+		}
+		kfree(bklit_setting);
+		break;
+
+	case PMIC_RAMPUP_BKLIT:
+		CHECK_ERROR(pmic_bklit_rampup((t_bklit_channel) arg));
+		break;
+
+	case PMIC_RAMPDOWN_BKLIT:
+		CHECK_ERROR(pmic_bklit_rampdown((t_bklit_channel) arg));
+		break;
+
+	case PMIC_OFF_RAMPUP_BKLIT:
+		CHECK_ERROR(pmic_bklit_off_rampup((t_bklit_channel) arg));
+		break;
+
+	case PMIC_OFF_RAMPDOWN_BKLIT:
+		CHECK_ERROR(pmic_bklit_off_rampdown((t_bklit_channel) arg));
+		break;
+
+	case PMIC_TCLED_ENABLE:
+		if ((tcled_setting = kmalloc(sizeof(t_tcled_enable_param),
+					     GFP_KERNEL))
+		    == NULL) {
+			return -ENOMEM;
+		}
+
+		if (copy_from_user(tcled_setting, (t_tcled_enable_param *) arg,
+				   sizeof(t_tcled_enable_param))) {
+			kfree(tcled_setting);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_tcled_enable(tcled_setting->mode,
+						    tcled_setting->bank),
+				  (kfree(bklit_setting)));
+		break;
+
+	case PMIC_TCLED_DISABLE:
+		CHECK_ERROR(pmic_tcled_disable((t_funlight_bank) arg));
+		break;
+
+	case PMIC_TCLED_PATTERN:
+		if ((fun_param = kmalloc(sizeof(t_fun_param),
+					 GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(fun_param,
+				   (t_fun_param *) arg, sizeof(t_fun_param))) {
+			kfree(fun_param);
+			return -EFAULT;
+		}
+
+		switch (fun_param->pattern) {
+		case BLENDED_RAMPS_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps
+					  (fun_param->bank, TC_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case BLENDED_RAMPS_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps
+					  (fun_param->bank, TC_FAST),
+					  (kfree(fun_param)));
+			break;
+
+		case SAW_RAMPS_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps
+					  (fun_param->bank, TC_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case SAW_RAMPS_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps
+					  (fun_param->bank, TC_FAST),
+					  (kfree(fun_param)));
+			break;
+
+		case BLENDED_BOWTIE_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie
+					  (fun_param->bank, TC_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case BLENDED_BOWTIE_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie
+					  (fun_param->bank, TC_FAST),
+					  (kfree(fun_param)));
+			break;
+
+		case STROBE_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_strobe
+					  (fun_param->bank, fun_param->channel,
+					   TC_STROBE_SLOW), (kfree(fun_param)));
+			break;
+
+		case STROBE_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_strobe
+					  (fun_param->bank,
+					   fun_param->channel, TC_STROBE_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case CHASING_LIGHT_RGB_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern
+					  (fun_param->bank, PMIC_RGB, TC_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case CHASING_LIGHT_RGB_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern
+					  (fun_param->bank, PMIC_RGB, TC_FAST),
+					  (kfree(fun_param)));
+			break;
+
+		case CHASING_LIGHT_BGR_SLOW:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern
+					  (fun_param->bank, BGR, TC_SLOW),
+					  (kfree(fun_param)));
+			break;
+
+		case CHASING_LIGHT_BGR_FAST:
+			CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern
+					  (fun_param->bank, BGR, TC_FAST),
+					  (kfree(fun_param)));
+			break;
+		}
+
+		kfree(fun_param);
+		break;
+
+	case PMIC_SET_TCLED:
+		if ((tcled_ind = kmalloc(sizeof(t_tcled_ind_param), GFP_KERNEL))
+		    == NULL) {
+			return -ENOMEM;
+		}
+
+		if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg,
+				   sizeof(t_tcled_ind_param))) {
+			kfree(tcled_ind);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_tcled_ind_set_current(tcled_ind->channel,
+							     tcled_ind->level,
+							     tcled_ind->bank),
+				  (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_ind_set_blink_pattern
+				  (tcled_ind->channel, tcled_ind->pattern,
+				   tcled_ind->skip, tcled_ind->bank),
+				  (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_fun_rampup
+				  (tcled_ind->bank, tcled_ind->channel,
+				   tcled_ind->rampup), (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_fun_rampdown
+				  (tcled_ind->bank, tcled_ind->channel,
+				   tcled_ind->rampdown), (kfree(tcled_ind)));
+		if (tcled_ind->half_current) {
+			CHECK_ERROR_KFREE(pmic_tcled_enable_half_current(),
+					  (kfree(tcled_ind)));
+		} else {
+			CHECK_ERROR_KFREE(pmic_tcled_disable_half_current(),
+					  (kfree(tcled_ind)));
+		}
+
+		kfree(tcled_ind);
+		break;
+
+	case PMIC_GET_TCLED:
+		if ((tcled_ind = kmalloc(sizeof(t_tcled_ind_param), GFP_KERNEL))
+		    == NULL) {
+			return -ENOMEM;
+		}
+		if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg,
+				   sizeof(t_tcled_ind_param))) {
+			kfree(tcled_ind);
+			return -EFAULT;
+		}
+		CHECK_ERROR_KFREE(pmic_tcled_ind_get_current(tcled_ind->channel,
+							     &tcled_ind->level,
+							     tcled_ind->bank),
+				  (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_ind_get_blink_pattern
+				  (tcled_ind->channel, &tcled_ind->pattern,
+				   &tcled_ind->skip, tcled_ind->bank),
+				  (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampup
+				  (tcled_ind->bank, tcled_ind->channel,
+				   &tcled_ind->rampup), (kfree(tcled_ind)));
+		CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampdown
+				  (tcled_ind->bank, tcled_ind->channel,
+				   &tcled_ind->rampdown), (kfree(tcled_ind)));
+		if (copy_to_user
+		    ((t_tcled_ind_param *) arg, tcled_ind,
+		     sizeof(t_tcled_ind_param))) {
+			return -EFAULT;
+		}
+		kfree(tcled_ind);
+
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*!
+ * This function initialize Light registers of mc13783 with 0.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int pmic_light_init_reg(void)
+{
+	CHECK_ERROR(pmic_write_reg(LREG_0, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(LREG_1, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(LREG_2, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(LREG_3, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(LREG_4, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(LREG_5, 0, PMIC_ALL_BITS));
+	return 0;
+}
+
+/*!
+ * This function implements the open method on a mc13783 light device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_light_open(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+	return 0;
+}
+
+/*!
+ * This function implements the release method on a mc13783 light device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_light_release(struct inode *inode, struct file *file)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+	return 0;
+}
+
+static struct file_operations pmic_light_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = pmic_light_ioctl,
+	.open = pmic_light_open,
+	.release = pmic_light_release,
+};
+
+static int pmic_light_remove(struct platform_device *pdev)
+{
+	device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0));
+	class_destroy(pmic_light_class);
+	unregister_chrdev(pmic_light_major, "pmic_light");
+	return 0;
+}
+
+static int pmic_light_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct device *temp_class;
+
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0))) {
+			return -ERESTARTSYS;
+		}
+	}
+	pmic_light_major = register_chrdev(0, "pmic_light", &pmic_light_fops);
+
+	if (pmic_light_major < 0) {
+		printk(KERN_ERR "Unable to get a major for pmic_light\n");
+		return pmic_light_major;
+	}
+	init_waitqueue_head(&suspendq);
+
+	pmic_light_class = class_create(THIS_MODULE, "pmic_light");
+	if (IS_ERR(pmic_light_class)) {
+		printk(KERN_ERR "Error creating pmic_light class.\n");
+		ret = PTR_ERR(pmic_light_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(pmic_light_class, NULL,
+				   MKDEV(pmic_light_major, 0), NULL,
+				   "pmic_light");
+	if (IS_ERR(temp_class)) {
+		printk(KERN_ERR "Error creating pmic_light class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	ret = pmic_light_init_reg();
+	if (ret != PMIC_SUCCESS) {
+		goto err_out3;
+	}
+
+	printk(KERN_INFO "PMIC Light successfully loaded\n");
+	return ret;
+
+      err_out3:
+	device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0));
+      err_out2:
+	class_destroy(pmic_light_class);
+      err_out1:
+	unregister_chrdev(pmic_light_major, "pmic_light");
+	return ret;
+}
+
+static struct platform_driver pmic_light_driver_ldm = {
+	.driver = {
+		   .name = "pmic_light",
+		   },
+	.suspend = pmic_light_suspend,
+	.resume = pmic_light_resume,
+	.probe = pmic_light_probe,
+	.remove = pmic_light_remove,
+};
+
+/*
+ * Initialization and Exit
+ */
+
+static int __init pmic_light_init(void)
+{
+	pr_debug("PMIC Light driver loading...\n");
+	return platform_driver_register(&pmic_light_driver_ldm);
+}
+static void __exit pmic_light_exit(void)
+{
+	platform_driver_unregister(&pmic_light_driver_ldm);
+	pr_debug("PMIC Light driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+subsys_initcall(pmic_light_init);
+module_exit(pmic_light_exit);
+
+MODULE_DESCRIPTION("PMIC_LIGHT");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_light_defs.h b/drivers/mxc/pmic/mc13783/pmic_light_defs.h
new file mode 100644
index 000000000000..80082363d9ed
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_light_defs.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_light_defs.h
+ * @brief This is the internal header PMIC(mc13783) Light and Backlight driver.
+ *
+ * @ingroup PMIC_LIGHT
+ */
+
+#ifndef __MC13783_LIGHT_DEFS_H__
+#define __MC13783_LIGHT_DEFS_H__
+
+#define LREG_0   REG_LED_CONTROL_0
+#define LREG_1   REG_LED_CONTROL_1
+#define LREG_2   REG_LED_CONTROL_2
+#define LREG_3   REG_LED_CONTROL_3
+#define LREG_4   REG_LED_CONTROL_4
+#define LREG_5   REG_LED_CONTROL_5
+
+/* REG_LED_CONTROL_0 */
+
+#define         BIT_LEDEN_LSH           0
+#define         BIT_LEDEN_WID           1
+#define         MASK_TRIODE_MAIN_BL     0x080
+#define         INDEX_AUXILIARY         1
+#define         INDEX_KEYPAD            2
+#define         BITS_FUN_LIGHT_LSH      17
+#define         BITS_FUN_LIGHT_WID      4
+#define         MASK_FUN_LIGHT          0x1E0000
+#define         MASK_BK1_FL             0x200000
+#define         ENABLE_BK1_FL           0x200000
+#define         MASK_BK2_FL             0x400000
+#define         ENABLE_BK2_FL           0x400000
+#define         MASK_BK3_FL             0x800000
+#define         ENABLE_BK3_FL           0x800000
+#define 	BIT_UP_MAIN_BL_LSH	1
+#define 	BIT_UP_MAIN_BL_WID	1
+#define 	BIT_UP_AUX_BL_LSH	2
+#define 	BIT_UP_AUX_BL_WID	1
+#define 	BIT_UP_KEY_BL_LSH	3
+#define 	BIT_UP_KEY_BL_WID	1
+#define 	BIT_DOWN_MAIN_BL_LSH	4
+#define 	BIT_DOWN_MAIN_BL_WID	1
+#define 	BIT_DOWN_AUX_BL_LSH	5
+#define 	BIT_DOWN_AUX_BL_WID	1
+#define 	BIT_DOWN_KEY_BL_LSH	6
+#define 	BIT_DOWN_KEY_BL_WID	1
+#define 	BIT_TRIODE_MAIN_BL_LSH	7
+#define 	BIT_TRIODE_MAIN_BL_WID	1
+#define 	BIT_TRIODE_AUX_BL_LSH	8
+#define 	BIT_TRIODE_AUX_BL_WID	1
+#define 	BIT_TRIODE_KEY_BL_LSH	9
+#define 	BIT_TRIODE_KEY_BL_WID	1
+
+#define         BIT_BOOSTEN_LSH         10
+#define         BIT_BOOSTEN_WID         1
+#define         BITS_BOOST_LSH          11
+#define         BITS_BOOST_WID          5
+#define         BITS_BOOST_ABMS_LSH     11
+#define         BITS_BOOST_ABMS_WID     3
+#define         BITS_BOOST_ABR_LSH      14
+#define         BITS_BOOST_ABR_WID      2
+
+#define         MAX_BOOST_ABMS          7
+#define         MAX_BOOST_ABR           3
+
+/* REG_LED_CONTROL_1 */
+
+#define         BIT_SLEWLIMTC_LSH       23
+#define         BIT_SLEWLIMTC_WID       1
+#define         BIT_TC1HALF_LSH         18
+#define         BIT_TC1HALF_WID         1
+#define         LEDR1RAMPUP             0x000001
+#define         LEDR2RAMPUP             0x000040
+#define         LEDR3RAMPUP             0x001000
+#define         LEDR1RAMPDOWN           0x000008
+#define         LEDR2RAMPDOWN           0x000200
+#define         LEDR3RAMPDOWN           0x008000
+
+/* REG_LED_CONTROL_2 */
+
+#define         BIT_SLEWLIMBL_LSH       23
+#define         BIT_SLEWLIMBL_WID       1
+#define         BIT_DUTY_CYCLE          9
+#define         MASK_DUTY_CYCLE         0x001E00
+#define         INDEX_AUX               4
+#define         INDEX_KYD               8
+#define         BIT_CL_MAIN_LSH		0
+#define         BIT_CL_MAIN_WID		3
+#define         BIT_CL_AUX_LSH		3
+#define         BIT_CL_AUX_WID		3
+#define         BIT_CL_KEY_LSH		6
+#define         BIT_CL_KEY_WID		3
+
+/* REG_LED_CONTROL_3 4 5 */
+#define         BITS_CL_RED_LSH         0
+#define         BITS_CL_RED_WID         2
+#define         BITS_CL_GREEN_LSH       2
+#define         BITS_CL_GREEN_WID       2
+#define         BITS_CL_BLUE_LSH        4
+#define         BITS_CL_BLUE_WID        2
+#define         BITS_DC_RED_LSH         6
+#define         BITS_DC_RED_WID         5
+#define         BITS_DC_GREEN_LSH       11
+#define         BITS_DC_GREEN_WID       5
+#define         BITS_DC_BLUE_LSH        16
+#define         BITS_DC_BLUE_WID        5
+#define         BIT_PERIOD_LSH          21
+#define         BIT_PERIOD_WID          2
+
+#define         DUTY_CYCLE_MAX          31
+
+/* Fun light pattern */
+#define		BLENDED_RAMPS_SLOW      	0
+#define		BLENDED_RAMPS_FAST      	1
+#define		SAW_RAMPS_SLOW  		2
+#define		SAW_RAMPS_FAST	     		3
+#define		BLENDED_INVERSE_RAMPS_SLOW	4
+#define		BLENDED_INVERSE_RAMPS_FAST	5
+#define		CHASING_LIGHTS_RGB_SLOW		6
+#define		CHASING_LIGHTS_RGB_FAST		7
+#define		CHASING_LIGHTS_BGR_SLOW		8
+#define		CHASING_LIGHTS_BGR_FAST		9
+#define		FUN_LIGHTS_OFF			15
+
+/*!
+ * This function initialize Light registers of mc13783 with 0.
+ *
+ * @return       This function returns 0 if successful.
+ */
+int pmic_light_init_reg(void);
+
+#endif				/*  __MC13783_LIGHT_DEFS_H__ */
diff --git a/drivers/mxc/pmic/mc13783/pmic_power.c b/drivers/mxc/pmic/mc13783/pmic_power.c
new file mode 100644
index 000000000000..8f877b887e16
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_power.c
@@ -0,0 +1,3146 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_power.c
+ * @brief This is the main file of PMIC(mc13783) Power driver.
+ *
+ * @ingroup PMIC_POWER
+ */
+
+/*
+ * Includes
+ */
+
+#include <linux/platform_device.h>
+#include <linux/ioctl.h>
+#include <linux/pmic_status.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <mach/pmic_power.h>
+
+#include "pmic_power_defs.h"
+
+#ifdef CONFIG_MXC_HWEVENT
+#include <mach/hw_events.h>
+#endif
+
+#include <asm/mach-types.h>
+
+#define MC13783_REGCTRL_GPOx_MASK 0x18000
+
+static bool VBKUP1_EN = false;
+static bool VBKUP2_EN = false;
+
+/*
+ * Power Pmic API
+ */
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_power_off);
+EXPORT_SYMBOL(pmic_power_set_pc_config);
+EXPORT_SYMBOL(pmic_power_get_pc_config);
+EXPORT_SYMBOL(pmic_power_regulator_on);
+EXPORT_SYMBOL(pmic_power_regulator_off);
+EXPORT_SYMBOL(pmic_power_regulator_set_voltage);
+EXPORT_SYMBOL(pmic_power_regulator_get_voltage);
+EXPORT_SYMBOL(pmic_power_regulator_set_config);
+EXPORT_SYMBOL(pmic_power_regulator_get_config);
+EXPORT_SYMBOL(pmic_power_vbkup2_auto_en);
+EXPORT_SYMBOL(pmic_power_get_vbkup2_auto_state);
+EXPORT_SYMBOL(pmic_power_bat_det_en);
+EXPORT_SYMBOL(pmic_power_get_bat_det_state);
+EXPORT_SYMBOL(pmic_power_vib_pin_en);
+EXPORT_SYMBOL(pmic_power_gets_vib_pin_state);
+EXPORT_SYMBOL(pmic_power_get_power_mode_sense);
+EXPORT_SYMBOL(pmic_power_set_regen_assig);
+EXPORT_SYMBOL(pmic_power_get_regen_assig);
+EXPORT_SYMBOL(pmic_power_set_regen_inv);
+EXPORT_SYMBOL(pmic_power_get_regen_inv);
+EXPORT_SYMBOL(pmic_power_esim_v_en);
+EXPORT_SYMBOL(pmic_power_gets_esim_v_state);
+EXPORT_SYMBOL(pmic_power_set_auto_reset_en);
+EXPORT_SYMBOL(pmic_power_get_auto_reset_en);
+EXPORT_SYMBOL(pmic_power_set_conf_button);
+EXPORT_SYMBOL(pmic_power_get_conf_button);
+EXPORT_SYMBOL(pmic_power_event_sub);
+EXPORT_SYMBOL(pmic_power_event_unsub);
+
+/*!
+ * This function is called to put the power in a low power state.
+ * Switching off the platform cannot be decided by
+ * the power module. It has to be handled by the
+ * client application.
+ *
+ * @param   pdev  the device structure used to give information on which power
+ *                device (0 through 3 channels) to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int pmic_power_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+};
+
+/*!
+ * This function is called to resume the power from a low power state.
+ *
+ * @param   pdev  the device structure used to give information on which power
+ *                device (0 through 3 channels) to suspend
+ *
+ * @return  The function always returns 0.
+ */
+static int pmic_power_resume(struct platform_device *pdev)
+{
+	return 0;
+};
+
+/*!
+ * This function sets user power off in power control register and thus powers
+ * off the phone.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+void pmic_power_off(void)
+{
+	unsigned int mask, value;
+
+	mask = BITFMASK(MC13783_PWRCTRL_USER_OFF_SPI);
+	value = BITFVAL(MC13783_PWRCTRL_USER_OFF_SPI,
+			MC13783_PWRCTRL_USER_OFF_SPI_ENABLE);
+
+	pmic_write_reg(REG_POWER_CONTROL_0, value, mask);
+}
+
+/*!
+ * This function sets the power control configuration.
+ *
+ * @param        pc_config   power control configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_set_pc_config(t_pc_config * pc_config)
+{
+	unsigned int pwrctrl_val_reg0 = 0;
+	unsigned int pwrctrl_val_reg1 = 0;
+	unsigned int pwrctrl_mask_reg0 = 0;
+	unsigned int pwrctrl_mask_reg1 = 0;
+
+	if (pc_config == NULL) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if (pc_config->pc_enable != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN,
+					    MC13783_PWRCTRL_PCEN_ENABLE);
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PCT,
+					    pc_config->pc_timer);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN,
+					    MC13783_PWRCTRL_PCEN_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PCEN);
+	pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PCT);
+
+	if (pc_config->pc_count_enable != false) {
+
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN,
+					    MC13783_PWRCTRL_PC_COUNT_EN_ENABLE);
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT,
+					    pc_config->pc_count);
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_MAX_CNT,
+					    pc_config->pc_max_count);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN,
+					    MC13783_PWRCTRL_PC_COUNT_EN_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PC_COUNT_EN);
+	pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PC_MAX_CNT) |
+	    BITFMASK(MC13783_PWRCTRL_PC_COUNT);
+
+	if (pc_config->warm_enable != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN,
+					    MC13783_PWRCTRL_WARM_EN_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN,
+					    MC13783_PWRCTRL_WARM_EN_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_WARM_EN);
+
+	if (pc_config->user_off_pc != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_USER_OFF_PC,
+					    MC13783_PWRCTRL_USER_OFF_PC_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN,
+					    MC13783_PWRCTRL_USER_OFF_PC_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_USER_OFF_PC);
+
+	if (pc_config->clk_32k_user_off != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF,
+					    MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF,
+					    MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_USER_OFF);
+
+	if (pc_config->clk_32k_enable != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN,
+					    MC13783_PWRCTRL_32OUT_EN_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN,
+					    MC13783_PWRCTRL_32OUT_EN_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_EN);
+
+	if (pc_config->en_vbkup1 != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN,
+					    MC13783_PWRCTRL_VBKUP_ENABLE);
+		VBKUP1_EN = true;
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN,
+					    MC13783_PWRCTRL_VBKUP_DISABLE);
+		VBKUP1_EN = false;
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_EN);
+
+	if (pc_config->en_vbkup2 != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN,
+					    MC13783_PWRCTRL_VBKUP_ENABLE);
+		VBKUP2_EN = true;
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN,
+					    MC13783_PWRCTRL_VBKUP_DISABLE);
+		VBKUP2_EN = false;
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_EN);
+
+	if (pc_config->auto_en_vbkup1 != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN,
+					    MC13783_PWRCTRL_VBKUP_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN,
+					    MC13783_PWRCTRL_VBKUP_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_AUTO_EN);
+
+	if (pc_config->auto_en_vbkup2 != false) {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN,
+					    MC13783_PWRCTRL_VBKUP_ENABLE);
+	} else {
+		pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN,
+					    MC13783_PWRCTRL_VBKUP_DISABLE);
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_AUTO_EN);
+
+	if (VBKUP1_EN != false) {
+		if (pc_config->vhold_voltage > 3
+		    || pc_config->vhold_voltage < 0) {
+			return PMIC_PARAMETER_ERROR;
+		} else {
+
+			pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1,
+						    pc_config->vhold_voltage);
+		}
+	}
+	if (VBKUP2_EN != false) {
+		if (pc_config->vhold_voltage > 3
+		    || pc_config->vhold_voltage < 0) {
+			return PMIC_PARAMETER_ERROR;
+		} else {
+			pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2,
+						    pc_config->vhold_voltage2);
+		}
+	}
+	pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1) |
+	    BITFMASK(MC13783_PWRCTRL_VBKUP2);
+
+	if (pc_config->mem_allon != false) {
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON,
+					    MC13783_PWRCTRL_MEM_ALLON_ENABLE);
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_TMR,
+					    pc_config->mem_timer);
+	} else {
+		pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON,
+					    MC13783_PWRCTRL_MEM_ALLON_DISABLE);
+	}
+	pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_MEM_ALLON) |
+	    BITFMASK(MC13783_PWRCTRL_MEM_TMR);
+
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0,
+				   pwrctrl_val_reg0, pwrctrl_mask_reg0));
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_1,
+				   pwrctrl_val_reg1, pwrctrl_mask_reg1));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives the power control configuration.
+ *
+ * @param        pc_config   pointer to power control configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_get_pc_config(t_pc_config * pc_config)
+{
+	unsigned int pwrctrl_val_reg0 = 0;
+	unsigned int pwrctrl_val_reg1 = 0;
+
+	if (pc_config == NULL) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0,
+				  &pwrctrl_val_reg0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_1,
+				  &pwrctrl_val_reg1, PMIC_ALL_BITS));
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PCEN)
+	    == MC13783_PWRCTRL_PCEN_ENABLE) {
+		pc_config->pc_enable = true;
+		pc_config->pc_timer = BITFEXT(pwrctrl_val_reg1,
+					      MC13783_PWRCTRL_PCT);
+
+	} else {
+		pc_config->pc_enable = false;
+		pc_config->pc_timer = 0;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PC_COUNT_EN)
+	    == MC13783_PWRCTRL_PCEN_ENABLE) {
+		pc_config->pc_count_enable = true;
+		pc_config->pc_count = BITFEXT(pwrctrl_val_reg1,
+					      MC13783_PWRCTRL_PC_COUNT);
+		pc_config->pc_max_count = BITFEXT(pwrctrl_val_reg1,
+						  MC13783_PWRCTRL_PC_MAX_CNT);
+	} else {
+		pc_config->pc_count_enable = false;
+		pc_config->pc_count = 0;
+		pc_config->pc_max_count = 0;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_WARM_EN)
+	    == MC13783_PWRCTRL_WARM_EN_ENABLE) {
+		pc_config->warm_enable = true;
+	} else {
+		pc_config->warm_enable = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_USER_OFF_PC)
+	    == MC13783_PWRCTRL_USER_OFF_PC_ENABLE) {
+		pc_config->user_off_pc = true;
+	} else {
+		pc_config->user_off_pc = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_USER_OFF)
+	    == MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE) {
+		pc_config->clk_32k_user_off = true;
+	} else {
+		pc_config->clk_32k_user_off = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_EN)
+	    == MC13783_PWRCTRL_32OUT_EN_ENABLE) {
+		pc_config->clk_32k_enable = true;
+	} else {
+		pc_config->clk_32k_enable = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_AUTO_EN)
+	    == MC13783_PWRCTRL_VBKUP_ENABLE) {
+		pc_config->auto_en_vbkup1 = true;
+	} else {
+		pc_config->auto_en_vbkup1 = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_AUTO_EN)
+	    == MC13783_PWRCTRL_VBKUP_ENABLE) {
+		pc_config->auto_en_vbkup2 = true;
+	} else {
+		pc_config->auto_en_vbkup2 = false;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_EN)
+	    == MC13783_PWRCTRL_VBKUP_ENABLE) {
+		pc_config->en_vbkup1 = true;
+		pc_config->vhold_voltage = BITFEXT(pwrctrl_val_reg0,
+						   MC13783_PWRCTRL_VBKUP1);
+	} else {
+		pc_config->en_vbkup1 = false;
+		pc_config->vhold_voltage = 0;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_EN)
+	    == MC13783_PWRCTRL_VBKUP_ENABLE) {
+		pc_config->en_vbkup2 = true;
+		pc_config->vhold_voltage2 = BITFEXT(pwrctrl_val_reg0,
+						    MC13783_PWRCTRL_VBKUP2);
+	} else {
+		pc_config->en_vbkup2 = false;
+		pc_config->vhold_voltage2 = 0;
+	}
+
+	if (BITFEXT(pwrctrl_val_reg1, MC13783_PWRCTRL_MEM_ALLON) ==
+	    MC13783_PWRCTRL_MEM_ALLON_ENABLE) {
+		pc_config->mem_allon = true;
+		pc_config->mem_timer = BITFEXT(pwrctrl_val_reg1,
+					       MC13783_PWRCTRL_MEM_TMR);
+	} else {
+		pc_config->mem_allon = false;
+		pc_config->mem_timer = 0;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function turns on a regulator.
+ *
+ * @param        regulator    The regulator to be truned on.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_on(t_pmic_regulator regulator)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_PLL:
+		reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN,
+				  MC13783_SWCTRL_PLL_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW3:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN,
+				  MC13783_SWCTRL_SW3_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN);
+		reg = REG_SWITCHERS_5;
+		break;
+	case REGU_VAUDIO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN,
+				  MC13783_REGCTRL_VAUDIO_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOHI:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN,
+				  MC13783_REGCTRL_VIOHI_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOLO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN,
+				  MC13783_REGCTRL_VIOLO_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN,
+				  MC13783_REGCTRL_VDIG_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VGEN:
+		reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN,
+				  MC13783_REGCTRL_VGEN_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN,
+				  MC13783_REGCTRL_VRFDIG_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFREF:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN,
+				  MC13783_REGCTRL_VRFREF_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFCP:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN,
+				  MC13783_REGCTRL_VRFCP_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VSIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN,
+				  MC13783_REGCTRL_VSIM_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VESIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN,
+				  MC13783_REGCTRL_VESIM_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VCAM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN,
+				  MC13783_REGCTRL_VCAM_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRFBG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN,
+				  MC13783_REGCTRL_VRFBG_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VVIB:
+		reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN,
+				  MC13783_REGCTRL_VVIB_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN,
+				  MC13783_REGCTRL_VRF1_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN,
+				  MC13783_REGCTRL_VRF2_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN,
+				  MC13783_REGCTRL_VMMC1_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN,
+				  MC13783_REGCTRL_VMMC2_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_GPO1:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN,
+				  MC13783_REGCTRL_GPO1_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO2:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN,
+				  MC13783_REGCTRL_GPO2_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO3:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN,
+				  MC13783_REGCTRL_GPO3_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO4:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN,
+				  MC13783_REGCTRL_GPO4_EN_ENABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function turns off a regulator.
+ *
+ * @param        regulator    The regulator to be truned off.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_off(t_pmic_regulator regulator)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_PLL:
+		reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN,
+				  MC13783_SWCTRL_PLL_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW3:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN,
+				  MC13783_SWCTRL_SW3_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN);
+		reg = REG_SWITCHERS_5;
+		break;
+	case REGU_VAUDIO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN,
+				  MC13783_REGCTRL_VAUDIO_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOHI:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN,
+				  MC13783_REGCTRL_VIOHI_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOLO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN,
+				  MC13783_REGCTRL_VIOLO_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN,
+				  MC13783_REGCTRL_VDIG_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VGEN:
+		reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN,
+				  MC13783_REGCTRL_VGEN_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN,
+				  MC13783_REGCTRL_VRFDIG_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFREF:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN,
+				  MC13783_REGCTRL_VRFREF_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFCP:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN,
+				  MC13783_REGCTRL_VRFCP_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VSIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN,
+				  MC13783_REGCTRL_VSIM_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VESIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN,
+				  MC13783_REGCTRL_VESIM_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VCAM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN,
+				  MC13783_REGCTRL_VCAM_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRFBG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN,
+				  MC13783_REGCTRL_VRFBG_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VVIB:
+		reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN,
+				  MC13783_REGCTRL_VVIB_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN,
+				  MC13783_REGCTRL_VRF1_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN,
+				  MC13783_REGCTRL_VRF2_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN,
+				  MC13783_REGCTRL_VMMC1_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN,
+				  MC13783_REGCTRL_VMMC2_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_GPO1:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN,
+				  MC13783_REGCTRL_GPO1_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO2:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN,
+				  MC13783_REGCTRL_GPO2_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO3:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN,
+				  MC13783_REGCTRL_GPO3_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	case REGU_GPO4:
+		reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN,
+				  MC13783_REGCTRL_GPO4_EN_DISABLE);
+		reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN);
+		reg = REG_POWER_MISCELLANEOUS;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the regulator output voltage.
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        voltage      The regulator output voltage.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_set_voltage(t_pmic_regulator regulator,
+					     t_regulator_voltage voltage)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		if ((voltage.sw1a < SW1A_0_9V) || (voltage.sw1a > SW1A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1A, voltage.sw1a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A);
+		reg = REG_SWITCHERS_0;
+		break;
+	case SW_SW1B:
+		if ((voltage.sw1b < SW1B_0_9V) || (voltage.sw1b > SW1B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1B, voltage.sw1b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1B);
+		reg = REG_SWITCHERS_1;
+		break;
+	case SW_SW2A:
+		if ((voltage.sw2a < SW2A_0_9V) || (voltage.sw2a > SW2A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2A, voltage.sw1a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW2A);
+		reg = REG_SWITCHERS_2;
+		break;
+	case SW_SW2B:
+		if ((voltage.sw2b < SW2B_0_9V) || (voltage.sw2b > SW2B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2B, voltage.sw2b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A);
+		reg = REG_SWITCHERS_3;
+		break;
+	case SW_SW3:
+		if (voltage.sw3 != SW3_5V) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW3, voltage.sw3);
+		reg_mask = BITFMASK(MC13783_SWSET_SW3);
+		reg = REG_SWITCHERS_5;
+		break;
+	case REGU_VIOLO:
+		if ((voltage.violo < VIOLO_1_2V) ||
+		    (voltage.violo > VIOLO_1_8V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VIOLO, voltage.violo);
+		reg_mask = BITFMASK(MC13783_REGSET_VIOLO);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VDIG:
+		if ((voltage.vdig < VDIG_1_2V) || (voltage.vdig > VDIG_1_8V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VDIG, voltage.vdig);
+		reg_mask = BITFMASK(MC13783_REGSET_VDIG);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VGEN:
+		if ((voltage.vgen < VGEN_1_2V) || (voltage.vgen > VGEN_2_4V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VGEN, voltage.vgen);
+		reg_mask = BITFMASK(MC13783_REGSET_VGEN);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VRFDIG:
+		if ((voltage.vrfdig < VRFDIG_1_2V) ||
+		    (voltage.vrfdig > VRFDIG_1_875V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VRFDIG, voltage.vrfdig);
+		reg_mask = BITFMASK(MC13783_REGSET_VRFDIG);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VRFREF:
+		if ((voltage.vrfref < VRFREF_2_475V) ||
+		    (voltage.vrfref > VRFREF_2_775V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VRFREF, voltage.vrfref);
+		reg_mask = BITFMASK(MC13783_REGSET_VRFREF);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VRFCP:
+		if ((voltage.vrfcp < VRFCP_2_7V) ||
+		    (voltage.vrfcp > VRFCP_2_775V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VRFCP, voltage.vrfcp);
+		reg_mask = BITFMASK(MC13783_REGSET_VRFCP);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VSIM:
+		if ((voltage.vsim < VSIM_1_8V) || (voltage.vsim > VSIM_2_9V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VSIM, voltage.vsim);
+		reg_mask = BITFMASK(MC13783_REGSET_VSIM);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VESIM:
+		if ((voltage.vesim < VESIM_1_8V) ||
+		    (voltage.vesim > VESIM_2_9V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VESIM, voltage.vesim);
+		reg_mask = BITFMASK(MC13783_REGSET_VESIM);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VCAM:
+		if ((voltage.vcam < VCAM_1_5V) || (voltage.vcam > VCAM_3V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VCAM, voltage.vcam);
+		reg_mask = BITFMASK(MC13783_REGSET_VCAM);
+		reg = REG_REGULATOR_SETTING_0;
+		break;
+	case REGU_VVIB:
+		if ((voltage.vvib < VVIB_1_3V) || (voltage.vvib > VVIB_3V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VVIB, voltage.vvib);
+		reg_mask = BITFMASK(MC13783_REGSET_VVIB);
+		reg = REG_REGULATOR_SETTING_1;
+		break;
+	case REGU_VRF1:
+		if ((voltage.vrf1 < VRF1_1_5V) || (voltage.vrf1 > VRF1_2_775V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VRF1, voltage.vrf1);
+		reg_mask = BITFMASK(MC13783_REGSET_VRF1);
+		reg = REG_REGULATOR_SETTING_1;
+		break;
+	case REGU_VRF2:
+		if ((voltage.vrf2 < VRF2_1_5V) || (voltage.vrf2 > VRF2_2_775V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VRF2, voltage.vrf2);
+		reg_mask = BITFMASK(MC13783_REGSET_VRF2);
+		reg = REG_REGULATOR_SETTING_1;
+		break;
+	case REGU_VMMC1:
+		if ((voltage.vmmc1 < VMMC1_1_6V) || (voltage.vmmc1 > VMMC1_3V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VMMC1, voltage.vmmc1);
+		reg_mask = BITFMASK(MC13783_REGSET_VMMC1);
+		reg = REG_REGULATOR_SETTING_1;
+		break;
+	case REGU_VMMC2:
+		if ((voltage.vmmc2 < VMMC2_1_6V) || (voltage.vmmc2 > VMMC2_3V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGSET_VMMC2, voltage.vmmc2);
+		reg_mask = BITFMASK(MC13783_REGSET_VMMC2);
+		reg = REG_REGULATOR_SETTING_1;
+		break;
+	case REGU_VAUDIO:
+	case REGU_VIOHI:
+	case REGU_VRFBG:
+	case REGU_GPO1:
+	case REGU_GPO2:
+	case REGU_GPO3:
+	case REGU_GPO4:
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives the regulator output voltage.
+ *
+ * @param        regulator    The regulator to be truned off.
+ * @param        voltage      Pointer to regulator output voltage.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_get_voltage(t_pmic_regulator regulator,
+					     t_regulator_voltage * voltage)
+{
+	unsigned int reg_val = 0;
+
+	if (regulator == SW_SW1A) {
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if (regulator == SW_SW1B) {
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if (regulator == SW_SW2A) {
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if (regulator == SW_SW2B) {
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if (regulator == SW_SW3) {
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if ((regulator == REGU_VIOLO) || (regulator == REGU_VDIG) ||
+		   (regulator == REGU_VGEN) ||
+		   (regulator == REGU_VRFDIG) ||
+		   (regulator == REGU_VRFREF) ||
+		   (regulator == REGU_VRFCP) ||
+		   (regulator == REGU_VSIM) ||
+		   (regulator == REGU_VESIM) || (regulator == REGU_VCAM)) {
+		CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+					  &reg_val, PMIC_ALL_BITS));
+	} else if ((regulator == REGU_VVIB) || (regulator == REGU_VRF1) ||
+		   (regulator == REGU_VRF2) ||
+		   (regulator == REGU_VMMC1) || (regulator == REGU_VMMC2)) {
+		CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1,
+					  &reg_val, PMIC_ALL_BITS));
+	}
+
+	switch (regulator) {
+	case SW_SW1A:
+		voltage->sw1a = BITFEXT(reg_val, MC13783_SWSET_SW1A);
+		break;
+	case SW_SW1B:
+		voltage->sw1b = BITFEXT(reg_val, MC13783_SWSET_SW1B);
+		break;
+	case SW_SW2A:
+		voltage->sw2a = BITFEXT(reg_val, MC13783_SWSET_SW2A);
+		break;
+	case SW_SW2B:
+		voltage->sw2b = BITFEXT(reg_val, MC13783_SWSET_SW2B);
+		break;
+	case SW_SW3:
+		voltage->sw3 = BITFEXT(reg_val, MC13783_SWSET_SW3);
+		break;
+	case REGU_VIOLO:
+		voltage->violo = BITFEXT(reg_val, MC13783_REGSET_VIOLO);
+		break;
+	case REGU_VDIG:
+		voltage->vdig = BITFEXT(reg_val, MC13783_REGSET_VDIG);
+		break;
+	case REGU_VGEN:
+		voltage->vgen = BITFEXT(reg_val, MC13783_REGSET_VGEN);
+		break;
+	case REGU_VRFDIG:
+		voltage->vrfdig = BITFEXT(reg_val, MC13783_REGSET_VRFDIG);
+		break;
+	case REGU_VRFREF:
+		voltage->vrfref = BITFEXT(reg_val, MC13783_REGSET_VRFREF);
+		break;
+	case REGU_VRFCP:
+		voltage->vrfcp = BITFEXT(reg_val, MC13783_REGSET_VRFCP);
+		break;
+	case REGU_VSIM:
+		voltage->vsim = BITFEXT(reg_val, MC13783_REGSET_VSIM);
+		break;
+	case REGU_VESIM:
+		voltage->vesim = BITFEXT(reg_val, MC13783_REGSET_VESIM);
+		break;
+	case REGU_VCAM:
+		voltage->vcam = BITFEXT(reg_val, MC13783_REGSET_VCAM);
+		break;
+	case REGU_VVIB:
+		voltage->vvib = BITFEXT(reg_val, MC13783_REGSET_VVIB);
+		break;
+	case REGU_VRF1:
+		voltage->vrf1 = BITFEXT(reg_val, MC13783_REGSET_VRF1);
+		break;
+	case REGU_VRF2:
+		voltage->vrf2 = BITFEXT(reg_val, MC13783_REGSET_VRF2);
+		break;
+	case REGU_VMMC1:
+		voltage->vmmc1 = BITFEXT(reg_val, MC13783_REGSET_VMMC1);
+		break;
+	case REGU_VMMC2:
+		voltage->vmmc2 = BITFEXT(reg_val, MC13783_REGSET_VMMC2);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the DVS voltage
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        dvs          The switch Dynamic Voltage Scaling
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_dvs(t_pmic_regulator regulator,
+					t_regulator_voltage dvs)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		if ((dvs.sw1a < SW1A_0_9V) || (dvs.sw1a > SW1A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1A_DVS, dvs.sw1a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS);
+		reg = REG_SWITCHERS_0;
+		break;
+	case SW_SW1B:
+		if ((dvs.sw1b < SW1B_0_9V) || (dvs.sw1b > SW1B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1B_DVS, dvs.sw1b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS);
+		reg = REG_SWITCHERS_1;
+		break;
+	case SW_SW2A:
+		if ((dvs.sw2a < SW2A_0_9V) || (dvs.sw2a > SW2A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2A_DVS, dvs.sw2a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS);
+		reg = REG_SWITCHERS_2;
+		break;
+	case SW_SW2B:
+		if ((dvs.sw2b < SW2B_0_9V) || (dvs.sw2b > SW2B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2B_DVS, dvs.sw2b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS);
+		reg = REG_SWITCHERS_3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the DVS voltage
+ *
+ * @param        regulator    The regulator to be handled.
+ * @param        dvs          The switch Dynamic Voltage Scaling
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_dvs(t_pmic_regulator regulator,
+					t_regulator_voltage * dvs)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS);
+		reg = REG_SWITCHERS_0;
+		break;
+	case SW_SW1B:
+		reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS);
+		reg = REG_SWITCHERS_1;
+		break;
+	case SW_SW2A:
+		reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS);
+		reg = REG_SWITCHERS_2;
+		break;
+	case SW_SW2B:
+		reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS);
+		reg = REG_SWITCHERS_3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		*dvs = (t_regulator_voltage) BITFEXT(reg_val,
+						     MC13783_SWSET_SW1A_DVS);
+		break;
+	case SW_SW1B:
+		*dvs = (t_regulator_voltage) BITFEXT(reg_val,
+						     MC13783_SWSET_SW1B_DVS);
+		break;
+	case SW_SW2A:
+		*dvs = (t_regulator_voltage) BITFEXT(reg_val,
+						     MC13783_SWSET_SW2A_DVS);
+		break;
+	case SW_SW2B:
+		*dvs = (t_regulator_voltage) BITFEXT(reg_val,
+						     MC13783_SWSET_SW2B_DVS);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the standiby voltage
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        stby         The switch standby voltage
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_stby(t_pmic_regulator regulator,
+					 t_regulator_voltage stby)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		if ((stby.sw1a < SW1A_0_9V) || (stby.sw1a > SW1A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1A_STDBY, stby.sw1a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY);
+		reg = REG_SWITCHERS_0;
+		break;
+	case SW_SW1B:
+		if ((stby.sw1b < SW1B_0_9V) || (stby.sw1b > SW1B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW1B_STDBY, stby.sw1b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY);
+		reg = REG_SWITCHERS_1;
+		break;
+	case SW_SW2A:
+		if ((stby.sw2a < SW2A_0_9V) || (stby.sw2a > SW2A_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2A_STDBY, stby.sw2a);
+		reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY);
+		reg = REG_SWITCHERS_2;
+		break;
+	case SW_SW2B:
+		if ((stby.sw2b < SW2B_0_9V) || (stby.sw2b > SW2B_2_2V)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_SWSET_SW2B_STDBY, stby.sw2b);
+		reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY);
+		reg = REG_SWITCHERS_3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the standiby voltage
+ *
+ * @param        regulator    The regulator to be handled.
+ * @param        stby         The switch standby voltage
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_stby(t_pmic_regulator regulator,
+					 t_regulator_voltage * stby)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY);
+		reg = REG_SWITCHERS_0;
+		break;
+	case SW_SW1B:
+		reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY);
+		reg = REG_SWITCHERS_1;
+		break;
+	case SW_SW2A:
+		reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY);
+		reg = REG_SWITCHERS_2;
+		break;
+	case SW_SW2B:
+		reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY);
+		reg = REG_SWITCHERS_3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		*stby = (t_regulator_voltage) BITFEXT(reg_val,
+						      MC13783_SWSET_SW1A_STDBY);
+		break;
+	case SW_SW1B:
+		*stby = (t_regulator_voltage) BITFEXT(reg_val,
+						      MC13783_SWSET_SW1B_STDBY);
+		break;
+	case SW_SW2A:
+		*stby = (t_regulator_voltage) BITFEXT(reg_val,
+						      MC13783_SWSET_SW2A_STDBY);
+		break;
+	case SW_SW2B:
+		*stby = (t_regulator_voltage) BITFEXT(reg_val,
+						      MC13783_SWSET_SW2B_STDBY);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the switchers mode.
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        mode	      The switcher mode
+ * @param        stby	      Switch between main and standby.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_mode(t_pmic_regulator regulator,
+					 t_regulator_sw_mode mode, bool stby)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+	unsigned int l_mode;
+
+	if (mode == SYNC_RECT) {
+		l_mode = MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN;
+	} else if (mode == NO_PULSE_SKIP) {
+		l_mode = MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN;
+	} else if (mode == PULSE_SKIP) {
+		l_mode = MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN;
+	} else if (mode == LOW_POWER) {
+		l_mode = MC13783_SWCTRL_SW_MODE_LOW_POWER_EN;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (regulator) {
+	case SW_SW1A:
+		if (stby) {
+			reg_val =
+			    BITFVAL(MC13783_SWCTRL_SW1A_STBY_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE);
+		} else {
+			reg_val = BITFVAL(MC13783_SWCTRL_SW1A_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE);
+		}
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		if (stby) {
+			reg_val =
+			    BITFVAL(MC13783_SWCTRL_SW1B_STBY_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE);
+		} else {
+			reg_val = BITFVAL(MC13783_SWCTRL_SW1B_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE);
+		}
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		if (stby) {
+			reg_val =
+			    BITFVAL(MC13783_SWCTRL_SW2A_STBY_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE);
+		} else {
+			reg_val = BITFVAL(MC13783_SWCTRL_SW2A_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE);
+		}
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		if (stby) {
+			reg_val =
+			    BITFVAL(MC13783_SWCTRL_SW2B_STBY_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE);
+		} else {
+			reg_val = BITFVAL(MC13783_SWCTRL_SW2B_MODE, l_mode);
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE);
+		}
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the switchers mode.
+ *
+ * @param        regulator    The regulator to be handled.
+ * @param        mode         The switcher mode.
+ * @param        stby         Switch between main and standby.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_mode(t_pmic_regulator regulator,
+					 t_regulator_sw_mode * mode, bool stby)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg = 0;
+	unsigned int l_mode = 0;
+
+	switch (regulator) {
+	case SW_SW1A:
+		if (stby) {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE);
+		} else {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE);
+		}
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		if (stby) {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE);
+		} else {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE);
+		}
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		if (stby) {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE);
+		} else {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE);
+		}
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		if (stby) {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE);
+		} else {
+			reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE);
+		}
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		if (stby) {
+			l_mode =
+			    BITFEXT(reg_val, MC13783_SWCTRL_SW1A_STBY_MODE);
+		} else {
+			l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_MODE);
+		}
+		break;
+	case SW_SW1B:
+		if (stby) {
+			l_mode =
+			    BITFEXT(reg_val, MC13783_SWCTRL_SW1B_STBY_MODE);
+		} else {
+			l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_MODE);
+		}
+		break;
+	case SW_SW2A:
+		if (stby) {
+			l_mode =
+			    BITFEXT(reg_val, MC13783_SWCTRL_SW2A_STBY_MODE);
+		} else {
+			l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_MODE);
+		}
+		break;
+	case SW_SW2B:
+		if (stby) {
+			l_mode =
+			    BITFEXT(reg_val, MC13783_SWCTRL_SW2B_STBY_MODE);
+		} else {
+			l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_MODE);
+		}
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if (l_mode == MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN) {
+		*mode = SYNC_RECT;
+	} else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN) {
+		*mode = NO_PULSE_SKIP;
+	} else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN) {
+		*mode = PULSE_SKIP;
+	} else if (l_mode == MC13783_SWCTRL_SW_MODE_LOW_POWER_EN) {
+		*mode = LOW_POWER;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the switch dvs speed
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        speed	      The dvs speed.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_dvs_speed(t_pmic_regulator regulator,
+					      t_switcher_dvs_speed speed)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+	if (speed > 3 || speed < 0) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW1A_DVS_SPEED, speed);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2A_DVS_SPEED, speed);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the switch dvs speed
+ *
+ * @param        regulator    The regulator to be handled.
+ * @param        speed        The dvs speed.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_dvs_speed(t_pmic_regulator regulator,
+					      t_switcher_dvs_speed * speed)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		*speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_DVS_SPEED);
+		break;
+	case SW_SW1B:
+		*speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_DVS_SPEED);
+		break;
+	case SW_SW2A:
+		*speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_DVS_SPEED);
+		break;
+	case SW_SW2B:
+		*speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_DVS_SPEED);
+		break;
+	default:
+		break;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the switch panic mode
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        panic_mode   Enable or disable panic mode
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_panic_mode(t_pmic_regulator regulator,
+					       bool panic_mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW1A_PANIC_MODE, panic_mode);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2A_PANIC_MODE, panic_mode);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the switch panic mode
+ *
+ * @param        regulator    The regulator to be handled
+ * @param        panic_mode   Enable or disable panic mode
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_panic_mode(t_pmic_regulator regulator,
+					       bool * panic_mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		*panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_PANIC_MODE);
+		break;
+	case SW_SW1B:
+		*panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_PANIC_MODE);
+		break;
+	case SW_SW2A:
+		*panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_PANIC_MODE);
+		break;
+	case SW_SW2B:
+		*panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_PANIC_MODE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the switch softstart mode
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        softstart    Enable or disable softstart.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_softstart(t_pmic_regulator regulator,
+					      bool softstart)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW1A_SOFTSTART, softstart);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2A_SOFTSTART, softstart);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the switch softstart mode
+ *
+ * @param        regulator    The regulator to be handled
+ * @param        softstart    Enable or disable softstart.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_softstart(t_pmic_regulator regulator,
+					      bool * softstart)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+
+	switch (regulator) {
+	case SW_SW1A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW1B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART);
+		reg = REG_SWITCHERS_4;
+		break;
+	case SW_SW2A:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART);
+		reg = REG_SWITCHERS_5;
+		break;
+	case SW_SW2B:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART);
+		reg = REG_SWITCHERS_5;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW1A:
+		*softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_SOFTSTART);
+		break;
+	case SW_SW1B:
+		*softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART);
+		break;
+	case SW_SW2A:
+		*softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_SOFTSTART);
+		break;
+	case SW_SW2B:
+		*softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART);
+		break;
+	default:
+		break;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the PLL multiplication factor
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        factor       The multiplication factor.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_set_factor(t_pmic_regulator regulator,
+					   t_switcher_factor factor)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	if (regulator != SW_PLL) {
+		return PMIC_PARAMETER_ERROR;
+	}
+	if (factor < FACTOR_28 || factor > FACTOR_35) {
+		return PMIC_PARAMETER_ERROR;
+	}
+	reg_val = BITFVAL(MC13783_SWCTRL_PLL_FACTOR, factor);
+	reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR);
+
+	CHECK_ERROR(pmic_write_reg(REG_SWITCHERS_4, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the PLL multiplication factor
+ *
+ * @param        regulator    The regulator to be handled
+ * @param        factor       The multiplication factor.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_switcher_get_factor(t_pmic_regulator regulator,
+					   t_switcher_factor * factor)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	if (regulator != SW_PLL) {
+		return PMIC_PARAMETER_ERROR;
+	}
+	reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR);
+
+	CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_4, &reg_val, reg_mask));
+
+	*factor = BITFEXT(reg_val, MC13783_SWCTRL_PLL_FACTOR);
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables or disables low power mode.
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        lp_mode      Select nominal or low power mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_set_lp_mode(t_pmic_regulator regulator,
+					     t_regulator_lp_mode lp_mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+	unsigned int l_mode, l_stby;
+
+	if (lp_mode == LOW_POWER_DISABLED) {
+		l_mode = MC13783_REGTRL_LP_MODE_DISABLE;
+		l_stby = MC13783_REGTRL_STBY_MODE_DISABLE;
+	} else if (lp_mode == LOW_POWER_CTRL_BY_PIN) {
+		l_mode = MC13783_REGTRL_LP_MODE_DISABLE;
+		l_stby = MC13783_REGTRL_STBY_MODE_ENABLE;
+	} else if (lp_mode == LOW_POWER_EN) {
+		l_mode = MC13783_REGTRL_LP_MODE_ENABLE;
+		l_stby = MC13783_REGTRL_STBY_MODE_DISABLE;
+	} else if (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN) {
+		l_mode = MC13783_REGTRL_LP_MODE_ENABLE;
+		l_stby = MC13783_REGTRL_STBY_MODE_ENABLE;
+	} else {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (regulator) {
+	case SW_SW3:
+		reg_val = BITFVAL(MC13783_SWCTRL_SW3_MODE, l_mode) |
+		    BITFVAL(MC13783_SWCTRL_SW3_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) |
+		    BITFMASK(MC13783_SWCTRL_SW3_STBY);
+		reg = REG_SWITCHERS_5;
+		break;
+	case REGU_VAUDIO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VAUDIO_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VAUDIO_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOHI:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VIOHI_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VIOHI_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOLO:
+		reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VIOLO_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VIOLO_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VDIG_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VDIG_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VDIG_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VGEN:
+		reg_val = BITFVAL(MC13783_REGCTRL_VGEN_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VGEN_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VGEN_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFDIG:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VRFDIG_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFDIG_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFREF:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VRFREF_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFREF_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFCP:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VRFCP_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFCP_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VSIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VSIM_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VSIM_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VSIM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VESIM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VESIM_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VESIM_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VESIM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VCAM:
+		reg_val = BITFVAL(MC13783_REGCTRL_VCAM_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VCAM_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VCAM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRFBG:
+		if ((lp_mode == LOW_POWER) ||
+		    (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN)) {
+			return PMIC_PARAMETER_ERROR;
+		}
+		reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_STBY, l_mode);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF1_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VRF1_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRF1_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VRF2_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VRF2_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRF2_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC1:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VMMC1_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VMMC1_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC2:
+		reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_MODE, l_mode) |
+		    BITFVAL(MC13783_REGCTRL_VMMC2_STBY, l_stby);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VMMC2_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets low power mode.
+ *
+ * @param        regulator    The regulator to be handled
+ * @param        lp_mode      Select nominal or low power mode.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_get_lp_mode(t_pmic_regulator regulator,
+					     t_regulator_lp_mode * lp_mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int reg;
+	unsigned int l_mode, l_stby;
+
+	switch (regulator) {
+	case SW_SW3:
+		reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) |
+		    BITFMASK(MC13783_SWCTRL_SW3_STBY);
+		reg = REG_SWITCHERS_5;
+		break;
+	case REGU_VAUDIO:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VAUDIO_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOHI:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VIOHI_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VIOLO:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VIOLO_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VDIG:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VDIG_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VGEN:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VGEN_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFDIG:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFDIG_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFREF:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFREF_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VRFCP:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRFCP_STBY);
+		reg = REG_REGULATOR_MODE_0;
+		break;
+	case REGU_VSIM:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VSIM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VESIM:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VESIM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VCAM:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VCAM_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRFBG:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF1:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRF1_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VRF2:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VRF2_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC1:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VMMC1_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	case REGU_VMMC2:
+		reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) |
+		    BITFMASK(MC13783_REGCTRL_VMMC2_STBY);
+		reg = REG_REGULATOR_MODE_1;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case SW_SW3:
+		l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW3_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_SWCTRL_SW3_STBY);
+		break;
+	case REGU_VAUDIO:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_STBY);
+		break;
+	case REGU_VIOHI:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_STBY);
+		break;
+	case REGU_VIOLO:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_STBY);
+		break;
+	case REGU_VDIG:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_STBY);
+		break;
+	case REGU_VGEN:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_STBY);
+		break;
+	case REGU_VRFDIG:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_STBY);
+		break;
+	case REGU_VRFREF:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_STBY);
+		break;
+	case REGU_VRFCP:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_STBY);
+		break;
+	case REGU_VSIM:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_STBY);
+		break;
+	case REGU_VESIM:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_STBY);
+		break;
+	case REGU_VCAM:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_STBY);
+		break;
+	case REGU_VRFBG:
+		l_mode = MC13783_REGTRL_LP_MODE_DISABLE;
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFBG_STBY);
+		break;
+	case REGU_VRF1:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_STBY);
+		break;
+	case REGU_VRF2:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_STBY);
+		break;
+	case REGU_VMMC1:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_STBY);
+		break;
+	case REGU_VMMC2:
+		l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_MODE);
+		l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_STBY);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) &&
+	    (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) {
+		*lp_mode = LOW_POWER_DISABLED;
+	} else if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) &&
+		   (l_stby == MC13783_REGTRL_STBY_MODE_ENABLE)) {
+		*lp_mode = LOW_POWER_CTRL_BY_PIN;
+	} else if ((l_mode == MC13783_REGTRL_LP_MODE_ENABLE) &&
+		   (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) {
+		*lp_mode = LOW_POWER_EN;
+	} else {
+		*lp_mode = LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the regulator configuration.
+ *
+ * @param        regulator    The regulator to be configured.
+ * @param        config       The regulator output configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_set_config(t_pmic_regulator regulator,
+					    t_regulator_config * config)
+{
+	if (config == NULL) {
+		return PMIC_ERROR;
+	}
+
+	switch (regulator) {
+	case SW_SW1A:
+	case SW_SW1B:
+	case SW_SW2A:
+	case SW_SW2B:
+		CHECK_ERROR(pmic_power_regulator_set_voltage
+			    (regulator, config->voltage));
+		CHECK_ERROR(pmic_power_switcher_set_dvs
+			    (regulator, config->voltage_lvs));
+		CHECK_ERROR(pmic_power_switcher_set_stby
+			    (regulator, config->voltage_stby));
+		CHECK_ERROR(pmic_power_switcher_set_mode
+			    (regulator, config->mode, false));
+		CHECK_ERROR(pmic_power_switcher_set_mode
+			    (regulator, config->stby_mode, true));
+		CHECK_ERROR(pmic_power_switcher_set_dvs_speed
+			    (regulator, config->dvs_speed));
+		CHECK_ERROR(pmic_power_switcher_set_panic_mode
+			    (regulator, config->panic_mode));
+		CHECK_ERROR(pmic_power_switcher_set_softstart
+			    (regulator, config->softstart));
+		break;
+	case SW_PLL:
+		CHECK_ERROR(pmic_power_switcher_set_factor
+			    (regulator, config->factor));
+		break;
+	case SW_SW3:
+	case REGU_VIOLO:
+	case REGU_VDIG:
+	case REGU_VGEN:
+	case REGU_VRFDIG:
+	case REGU_VRFREF:
+	case REGU_VRFCP:
+	case REGU_VSIM:
+	case REGU_VESIM:
+	case REGU_VCAM:
+	case REGU_VRF1:
+	case REGU_VRF2:
+	case REGU_VMMC1:
+	case REGU_VMMC2:
+		CHECK_ERROR(pmic_power_regulator_set_voltage
+			    (regulator, config->voltage));
+		CHECK_ERROR(pmic_power_regulator_set_lp_mode
+			    (regulator, config->lp_mode));
+		break;
+	case REGU_VVIB:
+		CHECK_ERROR(pmic_power_regulator_set_voltage
+			    (regulator, config->voltage));
+		break;
+	case REGU_VAUDIO:
+	case REGU_VIOHI:
+	case REGU_VRFBG:
+		CHECK_ERROR(pmic_power_regulator_set_lp_mode
+			    (regulator, config->lp_mode));
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function retrives the regulator output configuration.
+ *
+ * @param        regulator    The regulator to be truned off.
+ * @param        config       Pointer to regulator configuration.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_regulator_get_config(t_pmic_regulator regulator,
+					    t_regulator_config * config)
+{
+	if (config == NULL) {
+		return PMIC_ERROR;
+	}
+
+	switch (regulator) {
+	case SW_SW1A:
+	case SW_SW1B:
+	case SW_SW2A:
+	case SW_SW2B:
+		CHECK_ERROR(pmic_power_regulator_get_voltage
+			    (regulator, &config->voltage));
+		CHECK_ERROR(pmic_power_switcher_get_dvs
+			    (regulator, &config->voltage_lvs));
+		CHECK_ERROR(pmic_power_switcher_get_stby
+			    (regulator, &config->voltage_stby));
+		CHECK_ERROR(pmic_power_switcher_get_mode
+			    (regulator, &config->mode, false));
+		CHECK_ERROR(pmic_power_switcher_get_mode
+			    (regulator, &config->stby_mode, true));
+		CHECK_ERROR(pmic_power_switcher_get_dvs_speed
+			    (regulator, &config->dvs_speed));
+		CHECK_ERROR(pmic_power_switcher_get_panic_mode
+			    (regulator, &config->panic_mode));
+		CHECK_ERROR(pmic_power_switcher_get_softstart
+			    (regulator, &config->softstart));
+		break;
+	case SW_PLL:
+		CHECK_ERROR(pmic_power_switcher_get_factor
+			    (regulator, &config->factor));
+		break;
+	case SW_SW3:
+	case REGU_VIOLO:
+	case REGU_VDIG:
+	case REGU_VGEN:
+	case REGU_VRFDIG:
+	case REGU_VRFREF:
+	case REGU_VRFCP:
+	case REGU_VSIM:
+	case REGU_VESIM:
+	case REGU_VCAM:
+	case REGU_VRF1:
+	case REGU_VRF2:
+	case REGU_VMMC1:
+	case REGU_VMMC2:
+		CHECK_ERROR(pmic_power_regulator_get_voltage
+			    (regulator, &config->voltage));
+		CHECK_ERROR(pmic_power_regulator_get_lp_mode
+			    (regulator, &config->lp_mode));
+		break;
+	case REGU_VVIB:
+		CHECK_ERROR(pmic_power_regulator_get_voltage
+			    (regulator, &config->voltage));
+		break;
+	case REGU_VAUDIO:
+	case REGU_VIOHI:
+	case REGU_VRFBG:
+		CHECK_ERROR(pmic_power_regulator_get_lp_mode
+			    (regulator, &config->lp_mode));
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables automatically VBKUP2 in the memory hold modes.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        en           if true, enable VBKUP2AUTOMH
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_vbkup2_auto_en(bool en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_val = BITFVAL(MC13783_REGCTRL_VBKUP2AUTOMH, en);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH);
+
+		CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0,
+					   reg_val, reg_mask));
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets state of automatically VBKUP2.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        en           if true, VBKUP2AUTOMH is enabled
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_get_vbkup2_auto_state(bool * en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH);
+		CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0,
+					  &reg_val, reg_mask));
+		*en = BITFEXT(reg_val, MC13783_REGCTRL_VBKUP2AUTOMH);
+
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function enables battery detect function.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        en           if true, enable BATTDETEN
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_bat_det_en(bool en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_val = BITFVAL(MC13783_REGCTRL_BATTDETEN, en);
+		reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN);
+
+		CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0,
+					   reg_val, reg_mask));
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets state of battery detect function.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        en           if true, BATTDETEN is enabled
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_get_bat_det_state(bool * en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN);
+
+		CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0,
+					  &reg_val, reg_mask));
+		*en = BITFEXT(reg_val, MC13783_REGCTRL_BATTDETEN);
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function enables control of VVIB by VIBEN pin.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        en           if true, enable VIBPINCTRL
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_vib_pin_en(bool en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_val = BITFVAL(MC13783_REGCTRL_VIBPINCTRL, en);
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL);
+
+		CHECK_ERROR(pmic_write_reg(REG_POWER_MISCELLANEOUS,
+					   reg_val, reg_mask));
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets state of control of VVIB by VIBEN pin.
+ * Only on mc13783 2.0 or higher
+ * @param        en           if true, VIBPINCTRL is enabled
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_gets_vib_pin_state(bool * en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL);
+		CHECK_ERROR(pmic_read_reg(REG_POWER_MISCELLANEOUS,
+					  &reg_val, reg_mask));
+		*en = BITFEXT(reg_val, MC13783_REGCTRL_VIBPINCTRL);
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function returns power up sense value
+ *
+ * @param        p_up_sense     value of power up sense
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_power_get_power_mode_sense(struct t_p_up_sense * p_up_sense)
+{
+	unsigned int reg_value = 0;
+	CHECK_ERROR(pmic_read_reg(REG_POWER_UP_MODE_SENSE,
+				  &reg_value, PMIC_ALL_BITS));
+	p_up_sense->state_ictest = (STATE_ICTEST_MASK & reg_value);
+	p_up_sense->state_clksel = ((STATE_CLKSEL_MASK & reg_value)
+				    >> STATE_CLKSEL_BIT);
+	p_up_sense->state_pums1 = ((STATE_PUMS1_MASK & reg_value)
+				   >> STATE_PUMS1_BITS);
+	p_up_sense->state_pums2 = ((STATE_PUMS2_MASK & reg_value)
+				   >> STATE_PUMS2_BITS);
+	p_up_sense->state_pums3 = ((STATE_PUMS3_MASK & reg_value)
+				   >> STATE_PUMS3_BITS);
+	p_up_sense->state_chrgmode0 = ((STATE_CHRGM1_MASK & reg_value)
+				       >> STATE_CHRGM1_BITS);
+	p_up_sense->state_chrgmode1 = ((STATE_CHRGM2_MASK & reg_value)
+				       >> STATE_CHRGM2_BITS);
+	p_up_sense->state_umod = ((STATE_UMOD_MASK & reg_value)
+				  >> STATE_UMOD_BITS);
+	p_up_sense->state_usben = ((STATE_USBEN_MASK & reg_value)
+				   >> STATE_USBEN_BIT);
+	p_up_sense->state_sw_1a1b_joined = ((STATE_SW1A_J_B_MASK & reg_value)
+					    >> STATE_SW1A_J_B_BIT);
+	p_up_sense->state_sw_2a2b_joined = ((STATE_SW2A_J_B_MASK & reg_value)
+					    >> STATE_SW2A_J_B_BIT);
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function configures the Regen assignment for all regulator
+ *
+ * @param        regulator      type of regulator
+ * @param        en_dis         if true, the regulator is enabled by regen.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_set_regen_assig(t_pmic_regulator regulator, bool en_dis)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	switch (regulator) {
+	case REGU_VAUDIO:
+		reg_val = BITFVAL(MC13783_REGGEN_VAUDIO, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO);
+		break;
+	case REGU_VIOHI:
+		reg_val = BITFVAL(MC13783_REGGEN_VIOHI, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VIOHI);
+		break;
+	case REGU_VIOLO:
+		reg_val = BITFVAL(MC13783_REGGEN_VIOLO, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VIOLO);
+		break;
+	case REGU_VDIG:
+		reg_val = BITFVAL(MC13783_REGGEN_VDIG, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VDIG);
+		break;
+	case REGU_VGEN:
+		reg_val = BITFVAL(MC13783_REGGEN_VGEN, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VGEN);
+		break;
+	case REGU_VRFDIG:
+		reg_val = BITFVAL(MC13783_REGGEN_VRFDIG, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG);
+		break;
+	case REGU_VRFREF:
+		reg_val = BITFVAL(MC13783_REGGEN_VRFREF, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFREF);
+		break;
+	case REGU_VRFCP:
+		reg_val = BITFVAL(MC13783_REGGEN_VRFCP, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFCP);
+		break;
+	case REGU_VCAM:
+		reg_val = BITFVAL(MC13783_REGGEN_VCAM, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VCAM);
+		break;
+	case REGU_VRFBG:
+		reg_val = BITFVAL(MC13783_REGGEN_VRFBG, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFBG);
+		break;
+	case REGU_VRF1:
+		reg_val = BITFVAL(MC13783_REGGEN_VRF1, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRF1);
+		break;
+	case REGU_VRF2:
+		reg_val = BITFVAL(MC13783_REGGEN_VRF2, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VRF2);
+		break;
+	case REGU_VMMC1:
+		reg_val = BITFVAL(MC13783_REGGEN_VMMC1, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VMMC1);
+		break;
+	case REGU_VMMC2:
+		reg_val = BITFVAL(MC13783_REGGEN_VMMC2, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_VMMC2);
+		break;
+	case REGU_GPO1:
+		reg_val = BITFVAL(MC13783_REGGEN_GPO1, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO1);
+		break;
+	case REGU_GPO2:
+		reg_val = BITFVAL(MC13783_REGGEN_GPO2, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO2);
+		break;
+	case REGU_GPO3:
+		reg_val = BITFVAL(MC13783_REGGEN_GPO3, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO3);
+		break;
+	case REGU_GPO4:
+		reg_val = BITFVAL(MC13783_REGGEN_GPO4, en_dis);
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO4);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the Regen assignment for all regulator
+ *
+ * @param        regulator      type of regulator
+ * @param        en_dis         return value, if true :
+ *                              the regulator is enabled by regen.
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_get_regen_assig(t_pmic_regulator regulator,
+				       bool * en_dis)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	switch (regulator) {
+	case REGU_VAUDIO:
+		reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO);
+		break;
+	case REGU_VIOHI:
+		reg_mask = BITFMASK(MC13783_REGGEN_VIOHI);
+		break;
+	case REGU_VIOLO:
+		reg_mask = BITFMASK(MC13783_REGGEN_VIOLO);
+		break;
+	case REGU_VDIG:
+		reg_mask = BITFMASK(MC13783_REGGEN_VDIG);
+		break;
+	case REGU_VGEN:
+		reg_mask = BITFMASK(MC13783_REGGEN_VGEN);
+		break;
+	case REGU_VRFDIG:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG);
+		break;
+	case REGU_VRFREF:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFREF);
+		break;
+	case REGU_VRFCP:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFCP);
+		break;
+	case REGU_VCAM:
+		reg_mask = BITFMASK(MC13783_REGGEN_VCAM);
+		break;
+	case REGU_VRFBG:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRFBG);
+		break;
+	case REGU_VRF1:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRF1);
+		break;
+	case REGU_VRF2:
+		reg_mask = BITFMASK(MC13783_REGGEN_VRF2);
+		break;
+	case REGU_VMMC1:
+		reg_mask = BITFMASK(MC13783_REGGEN_VMMC1);
+		break;
+	case REGU_VMMC2:
+		reg_mask = BITFMASK(MC13783_REGGEN_VMMC2);
+		break;
+	case REGU_GPO1:
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO1);
+		break;
+	case REGU_GPO2:
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO2);
+		break;
+	case REGU_GPO3:
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO3);
+		break;
+	case REGU_GPO4:
+		reg_mask = BITFMASK(MC13783_REGGEN_GPO4);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, &reg_val, reg_mask));
+
+	switch (regulator) {
+	case REGU_VAUDIO:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VAUDIO);
+		break;
+	case REGU_VIOHI:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOHI);
+		break;
+	case REGU_VIOLO:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOLO);
+		break;
+	case REGU_VDIG:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VDIG);
+		break;
+	case REGU_VGEN:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VGEN);
+		break;
+	case REGU_VRFDIG:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFDIG);
+		break;
+	case REGU_VRFREF:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFREF);
+		break;
+	case REGU_VRFCP:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFCP);
+		break;
+	case REGU_VCAM:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VCAM);
+		break;
+	case REGU_VRFBG:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFBG);
+		break;
+	case REGU_VRF1:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF1);
+		break;
+	case REGU_VRF2:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF2);
+		break;
+	case REGU_VMMC1:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC1);
+		break;
+	case REGU_VMMC2:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC2);
+		break;
+	case REGU_GPO1:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO1);
+		break;
+	case REGU_GPO2:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO2);
+		break;
+	case REGU_GPO3:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO3);
+		break;
+	case REGU_GPO4:
+		*en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO4);
+		break;
+	default:
+		break;
+	}
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function sets the Regen polarity.
+ *
+ * @param        en_dis         If true regen is inverted.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_set_regen_inv(bool en_dis)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	reg_val = BITFVAL(MC13783_REGGEN_INV, en_dis);
+	reg_mask = BITFMASK(MC13783_REGGEN_INV);
+
+	CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets the Regen polarity.
+ *
+ * @param        en_dis         If true regen is inverted.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_get_regen_inv(bool * en_dis)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	reg_mask = BITFMASK(MC13783_REGGEN_INV);
+	CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, &reg_val, reg_mask));
+	*en_dis = BITFEXT(reg_val, MC13783_REGGEN_INV);
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function enables esim control voltage.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        vesim          if true, enable VESIMESIMEN
+ * @param        vmmc1          if true, enable VMMC1ESIMEN
+ * @param        vmmc2          if true, enable VMMC2ESIMEN
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_esim_v_en(bool vesim, bool vmmc1, bool vmmc2)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_val = BITFVAL(MC13783_REGGEN_VESIMESIM, vesim) |
+		    BITFVAL(MC13783_REGGEN_VMMC1ESIM, vesim) |
+		    BITFVAL(MC13783_REGGEN_VMMC2ESIM, vesim);
+		reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) |
+		    BITFMASK(MC13783_REGGEN_VMMC1ESIM) |
+		    BITFMASK(MC13783_REGGEN_VMMC2ESIM);
+		CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT,
+					   reg_val, reg_mask));
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function gets esim control voltage values.
+ * Only on mc13783 2.0 or higher
+ *
+ * @param        vesim          if true, enable VESIMESIMEN
+ * @param        vmmc1          if true, enable VMMC1ESIMEN
+ * @param        vmmc2          if true, enable VMMC2ESIMEN
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_gets_esim_v_state(bool * vesim, bool * vmmc1,
+					 bool * vmmc2)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	pmic_version_t mc13783_ver;
+	mc13783_ver = pmic_get_version();
+	if (mc13783_ver.revision >= 20) {
+		reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) |
+		    BITFMASK(MC13783_REGGEN_VMMC1ESIM) |
+		    BITFMASK(MC13783_REGGEN_VMMC2ESIM);
+		CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT,
+					  &reg_val, reg_mask));
+		*vesim = BITFEXT(reg_val, MC13783_REGGEN_VESIMESIM);
+		*vmmc1 = BITFEXT(reg_val, MC13783_REGGEN_VMMC1ESIM);
+		*vmmc2 = BITFEXT(reg_val, MC13783_REGGEN_VMMC2ESIM);
+		return PMIC_SUCCESS;
+	} else {
+		return PMIC_NOT_SUPPORTED;
+	}
+}
+
+/*!
+ * This function enables auto reset after a system reset.
+ *
+ * @param        en         if true, the auto reset is enabled
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_set_auto_reset_en(bool en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	reg_val = BITFVAL(MC13783_AUTO_RESTART, en);
+	reg_mask = BITFMASK(MC13783_AUTO_RESTART);
+
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets auto reset configuration.
+ *
+ * @param        en         if true, the auto reset is enabled
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_get_auto_reset_en(bool * en)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	reg_mask = BITFMASK(MC13783_AUTO_RESTART);
+	CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, &reg_val, reg_mask));
+	*en = BITFEXT(reg_val, MC13783_AUTO_RESTART);
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function configures a system reset on a button.
+ *
+ * @param       bt         type of button.
+ * @param       sys_rst    if true, enable the system reset on this button
+ * @param       deb_time   sets the debounce time on this button pin
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time)
+{
+	int max_val = 0;
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	max_val = (1 << MC13783_DEB_BT_ON1B_WID) - 1;
+	if (deb_time > max_val) {
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	switch (bt) {
+	case BT_ON1B:
+		reg_val = BITFVAL(MC13783_EN_BT_ON1B, sys_rst) |
+		    BITFVAL(MC13783_DEB_BT_ON1B, deb_time);
+		reg_mask = BITFMASK(MC13783_EN_BT_ON1B) |
+		    BITFMASK(MC13783_DEB_BT_ON1B);
+		break;
+	case BT_ON2B:
+		reg_val = BITFVAL(MC13783_EN_BT_ON2B, sys_rst) |
+		    BITFVAL(MC13783_DEB_BT_ON2B, deb_time);
+		reg_mask = BITFMASK(MC13783_EN_BT_ON2B) |
+		    BITFMASK(MC13783_DEB_BT_ON2B);
+		break;
+	case BT_ON3B:
+		reg_val = BITFVAL(MC13783_EN_BT_ON3B, sys_rst) |
+		    BITFVAL(MC13783_DEB_BT_ON3B, deb_time);
+		reg_mask = BITFMASK(MC13783_EN_BT_ON3B) |
+		    BITFMASK(MC13783_DEB_BT_ON3B);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function gets configuration of a button.
+ *
+ * @param       bt         type of button.
+ * @param       sys_rst    if true, the system reset is enabled on this button
+ * @param       deb_time   gets the debounce time on this button pin
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_get_conf_button(t_button bt,
+				       bool * sys_rst, int *deb_time)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+
+	switch (bt) {
+	case BT_ON1B:
+		reg_mask = BITFMASK(MC13783_EN_BT_ON1B) |
+		    BITFMASK(MC13783_DEB_BT_ON1B);
+		break;
+	case BT_ON2B:
+		reg_mask = BITFMASK(MC13783_EN_BT_ON2B) |
+		    BITFMASK(MC13783_DEB_BT_ON2B);
+		break;
+	case BT_ON3B:
+		reg_mask = BITFMASK(MC13783_EN_BT_ON3B) |
+		    BITFMASK(MC13783_DEB_BT_ON3B);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, &reg_val, reg_mask));
+
+	switch (bt) {
+	case BT_ON1B:
+		*sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON1B);
+		*deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON1B);
+		break;
+	case BT_ON2B:
+		*sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON2B);
+		*deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON2B);
+		break;
+	case BT_ON3B:
+		*sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON3B);
+		*deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON3B);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to un/subscribe on power event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ * @param        sub            define if Un/subscribe event.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_event(t_pwr_int event, void *callback, bool sub)
+{
+	pmic_event_callback_t power_callback;
+	type_event power_event;
+
+	power_callback.func = callback;
+	power_callback.param = NULL;
+	switch (event) {
+	case PWR_IT_BPONI:
+		power_event = EVENT_BPONI;
+		break;
+	case PWR_IT_LOBATLI:
+		power_event = EVENT_LOBATLI;
+		break;
+	case PWR_IT_LOBATHI:
+		power_event = EVENT_LOBATHI;
+		break;
+	case PWR_IT_ONOFD1I:
+		power_event = EVENT_ONOFD1I;
+		break;
+	case PWR_IT_ONOFD2I:
+		power_event = EVENT_ONOFD2I;
+		break;
+	case PWR_IT_ONOFD3I:
+		power_event = EVENT_ONOFD3I;
+		break;
+	case PWR_IT_SYSRSTI:
+		power_event = EVENT_SYSRSTI;
+		break;
+	case PWR_IT_PWRRDYI:
+		power_event = EVENT_PWRRDYI;
+		break;
+	case PWR_IT_PCI:
+		power_event = EVENT_PCI;
+		break;
+	case PWR_IT_WARMI:
+		power_event = EVENT_WARMI;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	if (sub == true) {
+		CHECK_ERROR(pmic_event_subscribe(power_event, power_callback));
+	} else {
+		CHECK_ERROR(pmic_event_unsubscribe
+			    (power_event, power_callback));
+	}
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to subscribe on power event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback)
+{
+	return pmic_power_event(event, callback, true);
+}
+
+/*!
+ * This function is used to un subscribe on power event IT.
+ *
+ * @param        event          type of event.
+ * @param        callback       event callback function.
+ *
+ * @return       This function returns 0 if successful.
+ */
+PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback)
+{
+	return pmic_power_event(event, callback, false);
+}
+
+void pmic_power_key_callback(void)
+{
+#ifdef CONFIG_MXC_HWEVENT
+	/*read the power key is pressed or up */
+	t_sensor_bits sense;
+	struct mxc_hw_event event = { HWE_POWER_KEY, 0 };
+
+	pmic_get_sensors(&sense);
+	if (sense.sense_onofd1s) {
+		pr_debug("PMIC Power key up\n");
+		event.args = PWRK_UNPRESS;
+	} else {
+		pr_debug("PMIC Power key pressed\n");
+		event.args = PWRK_PRESS;
+	}
+	/* send hw event */
+	hw_event_send(HWE_DEF_PRIORITY, &event);
+#endif
+}
+
+static irqreturn_t power_key_int(int irq, void *dev_id)
+{
+	pr_info(KERN_INFO "on-off key pressed\n");
+
+	return 0;
+}
+
+extern void gpio_power_key_active(void);
+
+/*
+ * Init and Exit
+ */
+
+static int pmic_power_probe(struct platform_device *pdev)
+{
+	int irq, ret;
+	struct pmic_platform_data *ppd;
+
+	/* configure on/off button */
+	gpio_power_key_active();
+
+	ppd = pdev->dev.platform_data;
+	if (ppd)
+		irq = ppd->power_key_irq;
+	else
+		goto done;
+
+	if (irq == 0) {
+		pr_info(KERN_INFO "PMIC Power has no platform data\n");
+		goto done;
+	}
+	set_irq_type(irq, IRQF_TRIGGER_RISING);
+
+	ret = request_irq(irq, power_key_int, 0, "power_key", 0);
+	if (ret)
+		pr_info(KERN_ERR "register on-off key interrupt failed\n");
+
+	set_irq_wake(irq, 1);
+
+      done:
+	pr_info(KERN_INFO "PMIC Power successfully probed\n");
+	return 0;
+}
+
+static struct platform_driver pmic_power_driver_ldm = {
+	.driver = {
+		   .name = "pmic_power",
+		   },
+	.suspend = pmic_power_suspend,
+	.resume = pmic_power_resume,
+	.probe = pmic_power_probe,
+	.remove = NULL,
+};
+
+static int __init pmic_power_init(void)
+{
+	pr_debug("PMIC Power driver loading..\n");
+	pmic_power_event_sub(PWR_IT_ONOFD1I, pmic_power_key_callback);
+	/* set power off hook to mc13783 power off */
+	pm_power_off = pmic_power_off;
+	return platform_driver_register(&pmic_power_driver_ldm);
+}
+static void __exit pmic_power_exit(void)
+{
+	pmic_power_event_unsub(PWR_IT_ONOFD1I, pmic_power_key_callback);
+	platform_driver_unregister(&pmic_power_driver_ldm);
+	pr_debug("PMIC Power driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+subsys_initcall_sync(pmic_power_init);
+module_exit(pmic_power_exit);
+
+MODULE_DESCRIPTION("pmic_power driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_power_defs.h b/drivers/mxc/pmic/mc13783/pmic_power_defs.h
new file mode 100644
index 000000000000..38e554146a70
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_power_defs.h
@@ -0,0 +1,509 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_power_defs.h
+ * @brief This is the internal header define of PMIC(mc13783) Power driver.
+ *
+ * @ingroup PMIC_POWER
+ */
+
+/*
+ * Includes
+ */
+
+#ifndef __MC13783_POWER_DEFS_H__
+#define __MC13783_POWER_DEFS_H__
+
+/*
+ * Power Up Mode Sense bits
+ */
+
+#define         STATE_ICTEST_MASK       0x000001
+
+#define         STATE_CLKSEL_BIT        1
+#define         STATE_CLKSEL_MASK       0x000002
+
+#define         STATE_PUMS1_BITS        2
+#define         STATE_PUMS1_MASK        0x00000C
+
+#define         STATE_PUMS2_BITS        4
+#define         STATE_PUMS2_MASK        0x000030
+
+#define         STATE_PUMS3_BITS        6
+#define         STATE_PUMS3_MASK        0x0000C0
+
+#define         STATE_CHRGM1_BITS       8
+#define         STATE_CHRGM1_MASK       0x000300
+
+#define         STATE_CHRGM2_BITS       10
+#define         STATE_CHRGM2_MASK       0x000C00
+
+#define         STATE_UMOD_BITS         12
+#define         STATE_UMOD_MASK         0x003000
+
+#define         STATE_USBEN_BIT         14
+#define         STATE_USBEN_MASK        0x004000
+
+#define         STATE_SW1A_J_B_BIT      15
+#define         STATE_SW1A_J_B_MASK     0x008000
+
+#define         STATE_SW2A_J_B_BIT      16
+#define         STATE_SW2A_J_B_MASK     0x010000
+
+#define         PC_COUNT_MAX            3
+#define         PC_COUNT_MIN            0
+/*
+ * Reg Regen
+ */
+#define MC13783_REGGEN_VAUDIO_LSH			0
+#define MC13783_REGGEN_VAUDIO_WID			1
+#define MC13783_REGGEN_VIOHI_LSH			1
+#define MC13783_REGGEN_VIOHI_WID			1
+#define MC13783_REGGEN_VIOLO_LSH			2
+#define MC13783_REGGEN_VIOLO_WID			1
+#define MC13783_REGGEN_VDIG_LSH			3
+#define MC13783_REGGEN_VDIG_WID			1
+#define MC13783_REGGEN_VGEN_LSH			4
+#define MC13783_REGGEN_VGEN_WID			1
+#define MC13783_REGGEN_VRFDIG_LSH			5
+#define MC13783_REGGEN_VRFDIG_WID			1
+#define MC13783_REGGEN_VRFREF_LSH			6
+#define MC13783_REGGEN_VRFREF_WID			1
+#define MC13783_REGGEN_VRFCP_LSH			7
+#define MC13783_REGGEN_VRFCP_WID			1
+#define MC13783_REGGEN_VCAM_LSH			8
+#define MC13783_REGGEN_VCAM_WID			1
+#define MC13783_REGGEN_VRFBG_LSH			9
+#define MC13783_REGGEN_VRFBG_WID			1
+#define MC13783_REGGEN_VRF1_LSH			10
+#define MC13783_REGGEN_VRF1_WID			1
+#define MC13783_REGGEN_VRF2_LSH			11
+#define MC13783_REGGEN_VRF2_WID			1
+#define MC13783_REGGEN_VMMC1_LSH			12
+#define MC13783_REGGEN_VMMC1_WID			1
+#define MC13783_REGGEN_VMMC2_LSH			13
+#define MC13783_REGGEN_VMMC2_WID			1
+#define MC13783_REGGEN_GPO1_LSH			16
+#define MC13783_REGGEN_GPO1_WID			1
+#define MC13783_REGGEN_GPO2_LSH			17
+#define MC13783_REGGEN_GPO2_WID			1
+#define MC13783_REGGEN_GPO3_LSH			18
+#define MC13783_REGGEN_GPO3_WID			1
+#define MC13783_REGGEN_GPO4_LSH			19
+#define MC13783_REGGEN_GPO4_WID			1
+#define MC13783_REGGEN_INV_LSH			20
+#define MC13783_REGGEN_INV_WID			1
+#define MC13783_REGGEN_VESIMESIM_LSH		21
+#define MC13783_REGGEN_VESIMESIM_WID		1
+#define MC13783_REGGEN_VMMC1ESIM_LSH		22
+#define MC13783_REGGEN_VMMC1ESIM_WID		1
+#define MC13783_REGGEN_VMMC2ESIM_LSH		23
+#define MC13783_REGGEN_VMMC2ESIM_WID		1
+
+/*
+ * Reg Power Control 0
+ */
+#define MC13783_PWRCTRL_PCEN_LSH			0
+#define MC13783_PWRCTRL_PCEN_WID			1
+#define MC13783_PWRCTRL_PCEN_ENABLE		1
+#define MC13783_PWRCTRL_PCEN_DISABLE		0
+#define MC13783_PWRCTRL_PC_COUNT_EN_LSH		1
+#define MC13783_PWRCTRL_PC_COUNT_EN_WID		1
+#define MC13783_PWRCTRL_PC_COUNT_EN_ENABLE	1
+#define MC13783_PWRCTRL_PC_COUNT_EN_DISABLE	0
+#define MC13783_PWRCTRL_WARM_EN_LSH		2
+#define MC13783_PWRCTRL_WARM_EN_WID		1
+#define MC13783_PWRCTRL_WARM_EN_ENABLE		1
+#define MC13783_PWRCTRL_WARM_EN_DISABLE		0
+#define MC13783_PWRCTRL_USER_OFF_SPI_LSH		3
+#define MC13783_PWRCTRL_USER_OFF_SPI_WID		1
+#define MC13783_PWRCTRL_USER_OFF_SPI_ENABLE	1
+#define MC13783_PWRCTRL_USER_OFF_PC_LSH		4
+#define MC13783_PWRCTRL_USER_OFF_PC_WID		1
+#define MC13783_PWRCTRL_USER_OFF_PC_ENABLE	1
+#define MC13783_PWRCTRL_USER_OFF_PC_DISABLE	0
+#define MC13783_PWRCTRL_32OUT_USER_OFF_LSH	5
+#define MC13783_PWRCTRL_32OUT_USER_OFF_WID	1
+#define MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE	1
+#define MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE	0
+#define MC13783_PWRCTRL_32OUT_EN_LSH		6
+#define MC13783_PWRCTRL_32OUT_EN_WID		1
+#define MC13783_PWRCTRL_32OUT_EN_ENABLE		1
+#define MC13783_PWRCTRL_32OUT_EN_DISABLE		0
+#define MC13783_REGCTRL_VBKUP2AUTOMH_LSH		7
+#define MC13783_REGCTRL_VBKUP2AUTOMH_WID		1
+#define MC13783_PWRCTRL_VBKUP1_EN_LSH		8
+#define MC13783_PWRCTRL_VBKUP1_EN_WID		1
+#define MC13783_PWRCTRL_VBKUP_ENABLE		1
+#define MC13783_PWRCTRL_VBKUP_DISABLE		0
+#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_LSH	9
+#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_WID	1
+#define MC13783_PWRCTRL_VBKUP1_LSH		10
+#define MC13783_PWRCTRL_VBKUP1_WID		2
+#define MC13783_PWRCTRL_VBKUP2_EN_LSH		12
+#define MC13783_PWRCTRL_VBKUP2_EN_WID		1
+#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_LSH	13
+#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_WID	1
+#define MC13783_PWRCTRL_VBKUP2_LSH		14
+#define MC13783_PWRCTRL_VBKUP2_WID		2
+#define MC13783_REGCTRL_BATTDETEN_LSH		19
+#define MC13783_REGCTRL_BATTDETEN_WID		1
+
+/*
+ * Reg Power Control 1
+ */
+#define MC13783_PWRCTRL_PCT_LSH		0
+#define MC13783_PWRCTRL_PCT_WID		8
+#define MC13783_PWRCTRL_PC_COUNT_LSH	8
+#define MC13783_PWRCTRL_PC_COUNT_WID	4
+#define MC13783_PWRCTRL_PC_MAX_CNT_LSH	12
+#define MC13783_PWRCTRL_PC_MAX_CNT_WID	4
+#define MC13783_PWRCTRL_MEM_TMR_LSH	16
+#define MC13783_PWRCTRL_MEM_TMR_WID	4
+#define MC13783_PWRCTRL_MEM_ALLON_LSH	20
+#define MC13783_PWRCTRL_MEM_ALLON_WID	1
+#define MC13783_PWRCTRL_MEM_ALLON_ENABLE	1
+#define MC13783_PWRCTRL_MEM_ALLON_DISABLE	0
+
+/*
+ * Reg Power Control 2
+ */
+#define MC13783_AUTO_RESTART_LSH	0
+#define MC13783_AUTO_RESTART_WID	1
+#define MC13783_EN_BT_ON1B_LSH		1
+#define MC13783_EN_BT_ON1B_WID		1
+#define MC13783_EN_BT_ON2B_LSH		2
+#define MC13783_EN_BT_ON2B_WID		1
+#define MC13783_EN_BT_ON3B_LSH		3
+#define MC13783_EN_BT_ON3B_WID		1
+#define MC13783_DEB_BT_ON1B_LSH		4
+#define MC13783_DEB_BT_ON1B_WID		2
+#define MC13783_DEB_BT_ON2B_LSH		6
+#define MC13783_DEB_BT_ON2B_WID		2
+#define MC13783_DEB_BT_ON3B_LSH		8
+#define MC13783_DEB_BT_ON3B_WID		2
+
+/*
+ * Reg Regulator Mode 0
+ */
+#define MC13783_REGCTRL_VAUDIO_EN_LSH	0
+#define MC13783_REGCTRL_VAUDIO_EN_WID	1
+#define MC13783_REGCTRL_VAUDIO_EN_ENABLE	1
+#define MC13783_REGCTRL_VAUDIO_EN_DISABLE	0
+#define MC13783_REGCTRL_VAUDIO_STBY_LSH	1
+#define MC13783_REGCTRL_VAUDIO_STBY_WID	1
+#define MC13783_REGCTRL_VAUDIO_MODE_LSH	2
+#define MC13783_REGCTRL_VAUDIO_MODE_WID	1
+#define MC13783_REGCTRL_VIOHI_EN_LSH	3
+#define MC13783_REGCTRL_VIOHI_EN_WID	1
+#define MC13783_REGCTRL_VIOHI_EN_ENABLE	1
+#define MC13783_REGCTRL_VIOHI_EN_DISABLE	0
+#define MC13783_REGCTRL_VIOHI_STBY_LSH	4
+#define MC13783_REGCTRL_VIOHI_STBY_WID	1
+#define MC13783_REGCTRL_VIOHI_MODE_LSH	5
+#define MC13783_REGCTRL_VIOHI_MODE_WID	1
+#define MC13783_REGCTRL_VIOLO_EN_LSH	6
+#define MC13783_REGCTRL_VIOLO_EN_WID	1
+#define MC13783_REGCTRL_VIOLO_EN_ENABLE	1
+#define MC13783_REGCTRL_VIOLO_EN_DISABLE	0
+#define MC13783_REGCTRL_VIOLO_STBY_LSH	7
+#define MC13783_REGCTRL_VIOLO_STBY_WID	1
+#define MC13783_REGCTRL_VIOLO_MODE_LSH	8
+#define MC13783_REGCTRL_VIOLO_MODE_WID	1
+#define MC13783_REGCTRL_VDIG_EN_LSH	9
+#define MC13783_REGCTRL_VDIG_EN_WID	1
+#define MC13783_REGCTRL_VDIG_EN_ENABLE	1
+#define MC13783_REGCTRL_VDIG_EN_DISABLE	0
+#define MC13783_REGCTRL_VDIG_STBY_LSH	10
+#define MC13783_REGCTRL_VDIG_STBY_WID	1
+#define MC13783_REGCTRL_VDIG_MODE_LSH	11
+#define MC13783_REGCTRL_VDIG_MODE_WID	1
+#define MC13783_REGCTRL_VGEN_EN_LSH	12
+#define MC13783_REGCTRL_VGEN_EN_WID	1
+#define MC13783_REGCTRL_VGEN_EN_ENABLE	1
+#define MC13783_REGCTRL_VGEN_EN_DISABLE	0
+#define MC13783_REGCTRL_VGEN_STBY_LSH	13
+#define MC13783_REGCTRL_VGEN_STBY_WID	1
+#define MC13783_REGCTRL_VGEN_MODE_LSH	14
+#define MC13783_REGCTRL_VGEN_MODE_WID	1
+#define MC13783_REGCTRL_VRFDIG_EN_LSH	15
+#define MC13783_REGCTRL_VRFDIG_EN_WID	1
+#define MC13783_REGCTRL_VRFDIG_EN_ENABLE	1
+#define MC13783_REGCTRL_VRFDIG_EN_DISABLE	0
+#define MC13783_REGCTRL_VRFDIG_STBY_LSH	16
+#define MC13783_REGCTRL_VRFDIG_STBY_WID	1
+#define MC13783_REGCTRL_VRFDIG_MODE_LSH	17
+#define MC13783_REGCTRL_VRFDIG_MODE_WID	1
+#define MC13783_REGCTRL_VRFREF_EN_LSH	18
+#define MC13783_REGCTRL_VRFREF_EN_WID	1
+#define MC13783_REGCTRL_VRFREF_EN_ENABLE	1
+#define MC13783_REGCTRL_VRFREF_EN_DISABLE	0
+#define MC13783_REGCTRL_VRFREF_STBY_LSH	19
+#define MC13783_REGCTRL_VRFREF_STBY_WID	1
+#define MC13783_REGCTRL_VRFREF_MODE_LSH	20
+#define MC13783_REGCTRL_VRFREF_MODE_WID	1
+#define MC13783_REGCTRL_VRFCP_EN_LSH	21
+#define MC13783_REGCTRL_VRFCP_EN_WID	1
+#define MC13783_REGCTRL_VRFCP_EN_ENABLE	1
+#define MC13783_REGCTRL_VRFCP_EN_DISABLE	0
+#define MC13783_REGCTRL_VRFCP_STBY_LSH	22
+#define MC13783_REGCTRL_VRFCP_STBY_WID	1
+#define MC13783_REGCTRL_VRFCP_MODE_LSH	23
+#define MC13783_REGCTRL_VRFCP_MODE_WID	1
+
+/*
+ * Reg Regulator Mode 1
+ */
+#define MC13783_REGCTRL_VSIM_EN_LSH	0
+#define MC13783_REGCTRL_VSIM_EN_WID	1
+#define MC13783_REGCTRL_VSIM_EN_ENABLE	1
+#define MC13783_REGCTRL_VSIM_EN_DISABLE	0
+#define MC13783_REGCTRL_VSIM_STBY_LSH	1
+#define MC13783_REGCTRL_VSIM_STBY_WID	1
+#define MC13783_REGCTRL_VSIM_MODE_LSH	2
+#define MC13783_REGCTRL_VSIM_MODE_WID	1
+#define MC13783_REGCTRL_VESIM_EN_LSH	3
+#define MC13783_REGCTRL_VESIM_EN_WID	1
+#define MC13783_REGCTRL_VESIM_EN_ENABLE	1
+#define MC13783_REGCTRL_VESIM_EN_DISABLE	0
+#define MC13783_REGCTRL_VESIM_STBY_LSH	4
+#define MC13783_REGCTRL_VESIM_STBY_WID	1
+#define MC13783_REGCTRL_VESIM_MODE_LSH	5
+#define MC13783_REGCTRL_VESIM_MODE_WID	1
+#define MC13783_REGCTRL_VCAM_EN_LSH	6
+#define MC13783_REGCTRL_VCAM_EN_WID	1
+#define MC13783_REGCTRL_VCAM_EN_ENABLE	1
+#define MC13783_REGCTRL_VCAM_EN_DISABLE	0
+#define MC13783_REGCTRL_VCAM_STBY_LSH	7
+#define MC13783_REGCTRL_VCAM_STBY_WID	1
+#define MC13783_REGCTRL_VCAM_MODE_LSH	8
+#define MC13783_REGCTRL_VCAM_MODE_WID	1
+#define	MC13783_REGCTRL_VRFBG_EN_LSH	9
+#define	MC13783_REGCTRL_VRFBG_EN_WID	1
+#define MC13783_REGCTRL_VRFBG_EN_ENABLE	1
+#define MC13783_REGCTRL_VRFBG_EN_DISABLE	0
+#define MC13783_REGCTRL_VRFBG_STBY_LSH	10
+#define MC13783_REGCTRL_VRFBG_STBY_WID	1
+#define MC13783_REGCTRL_VVIB_EN_LSH	11
+#define MC13783_REGCTRL_VVIB_EN_WID	1
+#define MC13783_REGCTRL_VVIB_EN_ENABLE	1
+#define MC13783_REGCTRL_VVIB_EN_DISABLE	0
+#define MC13783_REGCTRL_VRF1_EN_LSH	12
+#define MC13783_REGCTRL_VRF1_EN_WID	1
+#define MC13783_REGCTRL_VRF1_EN_ENABLE	1
+#define MC13783_REGCTRL_VRF1_EN_DISABLE	0
+#define MC13783_REGCTRL_VRF1_STBY_LSH	13
+#define MC13783_REGCTRL_VRF1_STBY_WID	1
+#define MC13783_REGCTRL_VRF1_MODE_LSH	14
+#define MC13783_REGCTRL_VRF1_MODE_WID	1
+#define MC13783_REGCTRL_VRF2_EN_LSH	15
+#define MC13783_REGCTRL_VRF2_EN_WID	1
+#define MC13783_REGCTRL_VRF2_EN_ENABLE	1
+#define MC13783_REGCTRL_VRF2_EN_DISABLE	0
+#define MC13783_REGCTRL_VRF2_STBY_LSH	16
+#define MC13783_REGCTRL_VRF2_STBY_WID	1
+#define MC13783_REGCTRL_VRF2_MODE_LSH	17
+#define MC13783_REGCTRL_VRF2_MODE_WID	1
+#define MC13783_REGCTRL_VMMC1_EN_LSH	18
+#define MC13783_REGCTRL_VMMC1_EN_WID	1
+#define MC13783_REGCTRL_VMMC1_EN_ENABLE	1
+#define MC13783_REGCTRL_VMMC1_EN_DISABLE	0
+#define MC13783_REGCTRL_VMMC1_STBY_LSH	19
+#define MC13783_REGCTRL_VMMC1_STBY_WID	1
+#define MC13783_REGCTRL_VMMC1_MODE_LSH	20
+#define MC13783_REGCTRL_VMMC1_MODE_WID	1
+#define MC13783_REGCTRL_VMMC2_EN_LSH	21
+#define MC13783_REGCTRL_VMMC2_EN_WID	1
+#define MC13783_REGCTRL_VMMC2_EN_ENABLE	1
+#define MC13783_REGCTRL_VMMC2_EN_DISABLE	0
+#define MC13783_REGCTRL_VMMC2_STBY_LSH	22
+#define MC13783_REGCTRL_VMMC2_STBY_WID	1
+#define MC13783_REGCTRL_VMMC2_MODE_LSH	23
+#define MC13783_REGCTRL_VMMC2_MODE_WID	1
+
+/*
+ * Reg Regulator Misc.
+ */
+#define MC13783_REGCTRL_GPO1_EN_LSH	6
+#define MC13783_REGCTRL_GPO1_EN_WID	1
+#define MC13783_REGCTRL_GPO1_EN_ENABLE	1
+#define MC13783_REGCTRL_GPO1_EN_DISABLE	0
+#define MC13783_REGCTRL_GPO2_EN_LSH	8
+#define MC13783_REGCTRL_GPO2_EN_WID	1
+#define MC13783_REGCTRL_GPO2_EN_ENABLE	1
+#define MC13783_REGCTRL_GPO2_EN_DISABLE	0
+#define MC13783_REGCTRL_GPO3_EN_LSH	10
+#define MC13783_REGCTRL_GPO3_EN_WID	1
+#define MC13783_REGCTRL_GPO3_EN_ENABLE	1
+#define MC13783_REGCTRL_GPO3_EN_DISABLE	0
+#define MC13783_REGCTRL_GPO4_EN_LSH	12
+#define MC13783_REGCTRL_GPO4_EN_WID	1
+#define MC13783_REGCTRL_GPO4_EN_ENABLE	1
+#define MC13783_REGCTRL_GPO4_EN_DISABLE	0
+#define MC13783_REGCTRL_VIBPINCTRL_LSH	14
+#define MC13783_REGCTRL_VIBPINCTRL_WID	1
+
+/*
+ * Reg Regulator Setting 0
+ */
+#define MC13783_REGSET_VIOLO_LSH		2
+#define MC13783_REGSET_VIOLO_WID		2
+#define MC13783_REGSET_VDIG_LSH		4
+#define MC13783_REGSET_VDIG_WID		2
+#define MC13783_REGSET_VGEN_LSH		6
+#define MC13783_REGSET_VGEN_WID		3
+#define MC13783_REGSET_VRFDIG_LSH		9
+#define MC13783_REGSET_VRFDIG_WID		2
+#define MC13783_REGSET_VRFREF_LSH		11
+#define MC13783_REGSET_VRFREF_WID		2
+#define MC13783_REGSET_VRFCP_LSH		13
+#define MC13783_REGSET_VRFCP_WID		1
+#define MC13783_REGSET_VSIM_LSH		14
+#define MC13783_REGSET_VSIM_WID		1
+#define MC13783_REGSET_VESIM_LSH		15
+#define MC13783_REGSET_VESIM_WID		1
+#define MC13783_REGSET_VCAM_LSH		16
+#define MC13783_REGSET_VCAM_WID		3
+
+/*
+ * Reg Regulator Setting 1
+ */
+#define MC13783_REGSET_VVIB_LSH		0
+#define MC13783_REGSET_VVIB_WID		2
+#define MC13783_REGSET_VRF1_LSH		2
+#define MC13783_REGSET_VRF1_WID		2
+#define MC13783_REGSET_VRF2_LSH		4
+#define MC13783_REGSET_VRF2_WID		2
+#define MC13783_REGSET_VMMC1_LSH		6
+#define MC13783_REGSET_VMMC1_WID		3
+#define MC13783_REGSET_VMMC2_LSH		9
+#define MC13783_REGSET_VMMC2_WID		3
+
+/*
+ * Reg Switcher 0
+ */
+#define MC13783_SWSET_SW1A_LSH		0
+#define MC13783_SWSET_SW1A_WID		6
+#define MC13783_SWSET_SW1A_DVS_LSH	6
+#define MC13783_SWSET_SW1A_DVS_WID	6
+#define MC13783_SWSET_SW1A_STDBY_LSH	12
+#define MC13783_SWSET_SW1A_STDBY_WID	6
+
+/*
+ * Reg Switcher 1
+ */
+#define MC13783_SWSET_SW1B_LSH		0
+#define MC13783_SWSET_SW1B_WID		6
+#define MC13783_SWSET_SW1B_DVS_LSH	6
+#define MC13783_SWSET_SW1B_DVS_WID	6
+#define MC13783_SWSET_SW1B_STDBY_LSH	12
+#define MC13783_SWSET_SW1B_STDBY_WID	6
+
+/*
+ * Reg Switcher 2
+ */
+#define MC13783_SWSET_SW2A_LSH		0
+#define MC13783_SWSET_SW2A_WID		6
+#define MC13783_SWSET_SW2A_DVS_LSH	6
+#define MC13783_SWSET_SW2A_DVS_WID	6
+#define MC13783_SWSET_SW2A_STDBY_LSH	12
+#define MC13783_SWSET_SW2A_STDBY_WID	6
+
+/*
+ * Reg Switcher 3
+ */
+#define MC13783_SWSET_SW2B_LSH		0
+#define MC13783_SWSET_SW2B_WID		6
+#define MC13783_SWSET_SW2B_DVS_LSH	6
+#define MC13783_SWSET_SW2B_DVS_WID	6
+#define MC13783_SWSET_SW2B_STDBY_LSH	12
+#define MC13783_SWSET_SW2B_STDBY_WID	6
+
+/*
+ * Reg Switcher 4
+ */
+#define MC13783_SWCTRL_SW1A_MODE_LSH		0
+#define MC13783_SWCTRL_SW1A_MODE_WID		2
+#define MC13783_SWCTRL_SW1A_STBY_MODE_LSH		2
+#define MC13783_SWCTRL_SW1A_STBY_MODE_WID		2
+#define MC13783_SWCTRL_SW1A_DVS_SPEED_LSH		6
+#define MC13783_SWCTRL_SW1A_DVS_SPEED_WID		2
+#define MC13783_SWCTRL_SW1A_PANIC_MODE_LSH	8
+#define MC13783_SWCTRL_SW1A_PANIC_MODE_WID	1
+#define MC13783_SWCTRL_SW1A_SOFTSTART_LSH		9
+#define MC13783_SWCTRL_SW1A_SOFTSTART_WID		1
+#define MC13783_SWCTRL_SW1B_MODE_LSH		10
+#define MC13783_SWCTRL_SW1B_MODE_WID		2
+#define MC13783_SWCTRL_SW1B_STBY_MODE_LSH		12
+#define MC13783_SWCTRL_SW1B_STBY_MODE_WID		2
+#define MC13783_SWCTRL_SW1B_DVS_SPEED_LSH		14
+#define MC13783_SWCTRL_SW1B_DVS_SPEED_WID		2
+#define MC13783_SWCTRL_SW1B_PANIC_MODE_LSH	16
+#define MC13783_SWCTRL_SW1B_PANIC_MODE_WID	1
+#define MC13783_SWCTRL_SW1B_SOFTSTART_LSH		17
+#define MC13783_SWCTRL_SW1B_SOFTSTART_WID		1
+#define MC13783_SWCTRL_PLL_EN_LSH			18
+#define MC13783_SWCTRL_PLL_EN_WID			1
+#define MC13783_SWCTRL_PLL_EN_ENABLE		1
+#define MC13783_SWCTRL_PLL_EN_DISABLE		0
+#define MC13783_SWCTRL_PLL_FACTOR_LSH		19
+#define MC13783_SWCTRL_PLL_FACTOR_WID		3
+
+/*
+ * Reg Switcher 5
+ */
+#define MC13783_SWCTRL_SW2A_MODE_LSH		0
+#define MC13783_SWCTRL_SW2A_MODE_WID		2
+#define MC13783_SWCTRL_SW2A_STBY_MODE_LSH		2
+#define MC13783_SWCTRL_SW2A_STBY_MODE_WID		2
+#define MC13783_SWCTRL_SW2A_DVS_SPEED_LSH		6
+#define MC13783_SWCTRL_SW2A_DVS_SPEED_WID		2
+#define MC13783_SWCTRL_SW2A_PANIC_MODE_LSH	8
+#define MC13783_SWCTRL_SW2A_PANIC_MODE_WID	1
+#define MC13783_SWCTRL_SW2A_SOFTSTART_LSH		9
+#define MC13783_SWCTRL_SW2A_SOFTSTART_WID		1
+#define MC13783_SWCTRL_SW2B_MODE_LSH		10
+#define MC13783_SWCTRL_SW2B_MODE_WID		2
+#define MC13783_SWCTRL_SW2B_STBY_MODE_LSH		12
+#define MC13783_SWCTRL_SW2B_STBY_MODE_WID		2
+#define MC13783_SWCTRL_SW2B_DVS_SPEED_LSH		14
+#define MC13783_SWCTRL_SW2B_DVS_SPEED_WID		2
+#define MC13783_SWCTRL_SW2B_PANIC_MODE_LSH	16
+#define MC13783_SWCTRL_SW2B_PANIC_MODE_WID	1
+#define MC13783_SWCTRL_SW2B_SOFTSTART_LSH		17
+#define MC13783_SWCTRL_SW2B_SOFTSTART_WID		1
+#define MC13783_SWSET_SW3_LSH			18
+#define MC13783_SWSET_SW3_WID			2
+#define MC13783_SWCTRL_SW3_EN_LSH			20
+#define MC13783_SWCTRL_SW3_EN_WID			2
+#define MC13783_SWCTRL_SW3_EN_ENABLE		1
+#define MC13783_SWCTRL_SW3_EN_DISABLE		0
+#define MC13783_SWCTRL_SW3_STBY_LSH		21
+#define MC13783_SWCTRL_SW3_STBY_WID		1
+#define MC13783_SWCTRL_SW3_MODE_LSH		22
+#define MC13783_SWCTRL_SW3_MODE_WID		1
+
+/*
+ * Switcher configuration
+ */
+#define MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN	0
+#define MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN	1
+#define MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN	2
+#define MC13783_SWCTRL_SW_MODE_LOW_POWER_EN	3
+#define MC13783_REGTRL_LP_MODE_ENABLE		1
+#define MC13783_REGTRL_LP_MODE_DISABLE		0
+#define MC13783_REGTRL_STBY_MODE_ENABLE		1
+#define MC13783_REGTRL_STBY_MODE_DISABLE		0
+
+#endif				/*  __MC13783_POWER_DEFS_H__ */
diff --git a/drivers/mxc/pmic/mc13783/pmic_rtc.c b/drivers/mxc/pmic/mc13783/pmic_rtc.c
new file mode 100644
index 000000000000..930ee45b55b8
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_rtc.c
@@ -0,0 +1,544 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13783/pmic_rtc.c
+ * @brief This is the main file of PMIC(mc13783) RTC driver.
+ *
+ * @ingroup PMIC_RTC
+ */
+
+/*
+ * Includes
+ */
+#include <linux/wait.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/pmic_rtc.h>
+#include <linux/pmic_status.h>
+
+#include "pmic_rtc_defs.h"
+
+#define PMIC_LOAD_ERROR_MSG		\
+"PMIC card was not correctly detected. Stop loading PMIC RTC driver\n"
+
+/*
+ * Global variables
+ */
+static int pmic_rtc_major;
+static void callback_alarm_asynchronous(void *);
+static void callback_alarm_synchronous(void *);
+static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait);
+static DECLARE_WAIT_QUEUE_HEAD(queue_alarm);
+static DECLARE_WAIT_QUEUE_HEAD(pmic_rtc_wait);
+static pmic_event_callback_t alarm_callback;
+static pmic_event_callback_t rtc_callback;
+static bool pmic_rtc_done = 0;
+static struct class *pmic_rtc_class;
+
+static DECLARE_MUTEX(mutex);
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_rtc_set_time);
+EXPORT_SYMBOL(pmic_rtc_get_time);
+EXPORT_SYMBOL(pmic_rtc_set_time_alarm);
+EXPORT_SYMBOL(pmic_rtc_get_time_alarm);
+EXPORT_SYMBOL(pmic_rtc_wait_alarm);
+EXPORT_SYMBOL(pmic_rtc_event_sub);
+EXPORT_SYMBOL(pmic_rtc_event_unsub);
+
+/*
+ * Real Time Clock Pmic API
+ */
+
+/*!
+ * This is the callback function called on TSI Pmic event, used in asynchronous
+ * call.
+ */
+static void callback_alarm_asynchronous(void *unused)
+{
+	pmic_rtc_done = true;
+}
+
+/*!
+ * This is the callback function is used in test code for (un)sub.
+ */
+static void callback_test_sub(void)
+{
+	printk(KERN_INFO "*****************************************\n");
+	printk(KERN_INFO "***** PMIC RTC 'Alarm IT CallBack' ******\n");
+	printk(KERN_INFO "*****************************************\n");
+}
+
+/*!
+ * This is the callback function called on TSI Pmic event, used in synchronous
+ * call.
+ */
+static void callback_alarm_synchronous(void *unused)
+{
+	printk(KERN_INFO "*** Alarm IT Pmic ***\n");
+	wake_up(&queue_alarm);
+}
+
+/*!
+ * This function wait the Alarm event
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_wait_alarm(void)
+{
+	DEFINE_WAIT(wait);
+	alarm_callback.func = callback_alarm_synchronous;
+	alarm_callback.param = NULL;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback));
+	prepare_to_wait(&queue_alarm, &wait, TASK_UNINTERRUPTIBLE);
+	schedule();
+	finish_wait(&queue_alarm, &wait);
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, alarm_callback));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function set the real time clock of PMIC
+ *
+ * @param        pmic_time  	value of date and time
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_set_time(struct timeval * pmic_time)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+
+	tod_reg_val = pmic_time->tv_sec % 86400;
+	day_reg_val = pmic_time->tv_sec / 86400;
+
+	mask = BITFMASK(MC13783_RTCTIME_TIME);
+	value = BITFVAL(MC13783_RTCTIME_TIME, tod_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask));
+
+	mask = BITFMASK(MC13783_RTCDAY_DAY);
+	value = BITFVAL(MC13783_RTCDAY_DAY, day_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function get the real time clock of PMIC
+ *
+ * @param        pmic_time  	return value of date and time
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_get_time(struct timeval * pmic_time)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+
+	mask = BITFMASK(MC13783_RTCTIME_TIME);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask));
+	tod_reg_val = BITFEXT(value, MC13783_RTCTIME_TIME);
+
+	mask = BITFMASK(MC13783_RTCDAY_DAY);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask));
+	day_reg_val = BITFEXT(value, MC13783_RTCDAY_DAY);
+
+	pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val &
+							    0x0001FFFF) +
+					    (unsigned long)(day_reg_val *
+							    86400));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function set the real time clock alarm of PMIC
+ *
+ * @param        pmic_time  	value of date and time
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval * pmic_time)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+	int ret;
+
+	if ((ret = down_interruptible(&mutex)) < 0)
+		return ret;
+
+	tod_reg_val = pmic_time->tv_sec % 86400;
+	day_reg_val = pmic_time->tv_sec / 86400;
+
+	mask = BITFMASK(MC13783_RTCALARM_TIME);
+	value = BITFVAL(MC13783_RTCALARM_TIME, tod_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask));
+
+	mask = BITFMASK(MC13783_RTCALARM_DAY);
+	value = BITFVAL(MC13783_RTCALARM_DAY, day_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask));
+	up(&mutex);
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function get the real time clock alarm of PMIC
+ *
+ * @param        pmic_time  	return value of date and time
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_get_time_alarm(struct timeval * pmic_time)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+
+	mask = BITFMASK(MC13783_RTCALARM_TIME);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask));
+	tod_reg_val = BITFEXT(value, MC13783_RTCALARM_TIME);
+
+	mask = BITFMASK(MC13783_RTCALARM_DAY);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask));
+	day_reg_val = BITFEXT(value, MC13783_RTCALARM_DAY);
+
+	pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val &
+							    0x0001FFFF) +
+					    (unsigned long)(day_reg_val *
+							    86400));
+
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to un/subscribe on RTC event IT.
+ *
+ * @param        event  	type of event.
+ * @param        callback  	event callback function.
+ * @param        sub      	define if Un/subscribe event.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_event(t_rtc_int event, void *callback, bool sub)
+{
+	type_event rtc_event;
+	if (callback == NULL) {
+		return PMIC_ERROR;
+	} else {
+		rtc_callback.func = callback;
+		rtc_callback.param = NULL;
+	}
+	switch (event) {
+	case RTC_IT_ALARM:
+		rtc_event = EVENT_TODAI;
+		break;
+	case RTC_IT_1HZ:
+		rtc_event = EVENT_E1HZI;
+		break;
+	case RTC_IT_RST:
+		rtc_event = EVENT_RTCRSTI;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	if (sub == true) {
+		CHECK_ERROR(pmic_event_subscribe(rtc_event, rtc_callback));
+	} else {
+		CHECK_ERROR(pmic_event_unsubscribe(rtc_event, rtc_callback));
+	}
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to subscribe on RTC event IT.
+ *
+ * @param        event  	type of event.
+ * @param        callback  	event callback function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_event_sub(t_rtc_int event, void *callback)
+{
+	CHECK_ERROR(pmic_rtc_event(event, callback, true));
+	return PMIC_SUCCESS;
+}
+
+/*!
+ * This function is used to un subscribe on RTC event IT.
+ *
+ * @param        event  	type of event.
+ * @param        callback  	event callback function.
+ *
+ * @return       This function returns PMIC_SUCCESS if successful.
+ */
+PMIC_STATUS pmic_rtc_event_unsub(t_rtc_int event, void *callback)
+{
+	CHECK_ERROR(pmic_rtc_event(event, callback, false));
+	return PMIC_SUCCESS;
+}
+
+/* Called without the kernel lock - fine */
+static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait)
+{
+	/*poll_wait(file, &pmic_rtc_wait, wait); */
+
+	if (pmic_rtc_done)
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+/*!
+ * This function implements IOCTL controls on a PMIC RTC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @param        cmd         the command
+ * @param        arg         the parameter
+ * @return       This function returns 0 if successful.
+ */
+static int pmic_rtc_ioctl(struct inode *inode, struct file *file,
+			  unsigned int cmd, unsigned long arg)
+{
+	struct timeval *pmic_time = NULL;
+
+	if (_IOC_TYPE(cmd) != 'p')
+		return -ENOTTY;
+
+	if (arg) {
+		if ((pmic_time = kmalloc(sizeof(struct timeval),
+					 GFP_KERNEL)) == NULL) {
+			return -ENOMEM;
+		}
+		/*      if (copy_from_user(pmic_time, (struct timeval *)arg,
+		   sizeof(struct timeval))) {
+		   return -EFAULT;
+		   } */
+	}
+
+	switch (cmd) {
+	case PMIC_RTC_SET_TIME:
+		if (copy_from_user(pmic_time, (struct timeval *)arg,
+				   sizeof(struct timeval))) {
+			return -EFAULT;
+		}
+		pr_debug("SET RTC\n");
+		CHECK_ERROR(pmic_rtc_set_time(pmic_time));
+		break;
+	case PMIC_RTC_GET_TIME:
+		if (copy_to_user((struct timeval *)arg, pmic_time,
+				 sizeof(struct timeval))) {
+			return -EFAULT;
+		}
+		pr_debug("GET RTC\n");
+		CHECK_ERROR(pmic_rtc_get_time(pmic_time));
+		break;
+	case PMIC_RTC_SET_ALARM:
+		if (copy_from_user(pmic_time, (struct timeval *)arg,
+				   sizeof(struct timeval))) {
+			return -EFAULT;
+		}
+		pr_debug("SET RTC ALARM\n");
+		CHECK_ERROR(pmic_rtc_set_time_alarm(pmic_time));
+		break;
+	case PMIC_RTC_GET_ALARM:
+		if (copy_to_user((struct timeval *)arg, pmic_time,
+				 sizeof(struct timeval))) {
+			return -EFAULT;
+		}
+		pr_debug("GET RTC ALARM\n");
+		CHECK_ERROR(pmic_rtc_get_time_alarm(pmic_time));
+		break;
+	case PMIC_RTC_WAIT_ALARM:
+		printk(KERN_INFO "WAIT ALARM...\n");
+		CHECK_ERROR(pmic_rtc_event_sub(RTC_IT_ALARM,
+					       callback_test_sub));
+		CHECK_ERROR(pmic_rtc_wait_alarm());
+		printk(KERN_INFO "ALARM DONE\n");
+		CHECK_ERROR(pmic_rtc_event_unsub(RTC_IT_ALARM,
+						 callback_test_sub));
+		break;
+	case PMIC_RTC_ALARM_REGISTER:
+		printk(KERN_INFO "PMIC RTC ALARM REGISTER\n");
+		alarm_callback.func = callback_alarm_asynchronous;
+		alarm_callback.param = NULL;
+		CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback));
+		break;
+	case PMIC_RTC_ALARM_UNREGISTER:
+		printk(KERN_INFO "PMIC RTC ALARM UNREGISTER\n");
+		alarm_callback.func = callback_alarm_asynchronous;
+		alarm_callback.param = NULL;
+		CHECK_ERROR(pmic_event_unsubscribe
+			    (EVENT_TODAI, alarm_callback));
+		pmic_rtc_done = false;
+		break;
+	default:
+		pr_debug("%d unsupported ioctl command\n", (int)cmd);
+		return -EINVAL;
+	}
+
+	if (arg) {
+		if (copy_to_user((struct timeval *)arg, pmic_time,
+				 sizeof(struct timeval))) {
+			return -EFAULT;
+		}
+		kfree(pmic_time);
+	}
+
+	return 0;
+}
+
+/*!
+ * This function implements the open method on a PMIC RTC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_rtc_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+/*!
+ * This function implements the release method on a PMIC RTC device.
+ *
+ * @param        inode       pointer on the node
+ * @param        file        pointer on the file
+ * @return       This function returns 0.
+ */
+static int pmic_rtc_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+/*!
+ * This function is called to put the RTC in a low power state.
+ * There is no need for power handlers for the RTC device.
+ * The RTC cannot be suspended.
+ *
+ * @param   pdev  the device structure used to give information on which RTC
+ *                device (0 through 3 channels) to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int pmic_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+/*!
+ * This function is called to resume the RTC from a low power state.
+ *
+ * @param   pdev  the device structure used to give information on which RTC
+ *                device (0 through 3 channels) to suspend
+ *
+ * @return  The function always returns 0.
+ */
+static int pmic_rtc_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+
+static struct file_operations pmic_rtc_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = pmic_rtc_ioctl,
+	.poll = pmic_rtc_poll,
+	.open = pmic_rtc_open,
+	.release = pmic_rtc_release,
+};
+
+static int pmic_rtc_remove(struct platform_device *pdev)
+{
+	device_destroy(pmic_rtc_class, MKDEV(pmic_rtc_major, 0));
+	class_destroy(pmic_rtc_class);
+	unregister_chrdev(pmic_rtc_major, "pmic_rtc");
+	return 0;
+}
+
+static int pmic_rtc_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct device *temp_class;
+
+	pmic_rtc_major = register_chrdev(0, "pmic_rtc", &pmic_rtc_fops);
+	if (pmic_rtc_major < 0) {
+		printk(KERN_ERR "Unable to get a major for pmic_rtc\n");
+		return pmic_rtc_major;
+	}
+
+	pmic_rtc_class = class_create(THIS_MODULE, "pmic_rtc");
+	if (IS_ERR(pmic_rtc_class)) {
+		printk(KERN_ERR "Error creating pmic rtc class.\n");
+		ret = PTR_ERR(pmic_rtc_class);
+		goto err_out1;
+	}
+
+	temp_class = device_create(pmic_rtc_class, NULL,
+				   MKDEV(pmic_rtc_major, 0), NULL,
+				   "pmic_rtc");
+	if (IS_ERR(temp_class)) {
+		printk(KERN_ERR "Error creating pmic rtc class device.\n");
+		ret = PTR_ERR(temp_class);
+		goto err_out2;
+	}
+
+	printk(KERN_INFO "PMIC RTC successfully probed\n");
+	return ret;
+
+      err_out2:
+	class_destroy(pmic_rtc_class);
+      err_out1:
+	unregister_chrdev(pmic_rtc_major, "pmic_rtc");
+	return ret;
+}
+
+static struct platform_driver pmic_rtc_driver_ldm = {
+	.driver = {
+		   .name = "pmic_rtc",
+		   .owner = THIS_MODULE,
+		   },
+	.suspend = pmic_rtc_suspend,
+	.resume = pmic_rtc_resume,
+	.probe = pmic_rtc_probe,
+	.remove = pmic_rtc_remove,
+};
+
+static int __init pmic_rtc_init(void)
+{
+	pr_debug("PMIC RTC driver loading...\n");
+	return platform_driver_register(&pmic_rtc_driver_ldm);
+}
+static void __exit pmic_rtc_exit(void)
+{
+	platform_driver_unregister(&pmic_rtc_driver_ldm);
+	pr_debug("PMIC RTC driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+subsys_initcall(pmic_rtc_init);
+module_exit(pmic_rtc_exit);
+
+MODULE_DESCRIPTION("Pmic_rtc driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h b/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h
new file mode 100644
index 000000000000..16e968dd9977
--- /dev/null
+++ b/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MC13783_RTC_DEFS_H__
+#define __MC13783_RTC_DEFS_H__
+
+/*!
+ * @file mc13783/pmic_rtc_defs.h
+ * @brief This is the internal header of PMIC(mc13783) RTC driver.
+ *
+ * @ingroup PMIC_RTC
+ */
+
+/*
+ * RTC Time
+ */
+#define MC13783_RTCTIME_TIME_LSH	0
+#define MC13783_RTCTIME_TIME_WID	17
+
+/*
+ * RTC Alarm
+ */
+#define MC13783_RTCALARM_TIME_LSH	0
+#define MC13783_RTCALARM_TIME_WID	17
+
+/*
+ * RTC Day
+ */
+#define MC13783_RTCDAY_DAY_LSH		0
+#define MC13783_RTCDAY_DAY_WID		15
+
+/*
+ * RTC Day alarm
+ */
+#define MC13783_RTCALARM_DAY_LSH	0
+#define MC13783_RTCALARM_DAY_WID	15
+
+#endif				/* __MC13783_RTC_DEFS_H__ */
diff --git a/drivers/mxc/pmic/mc13892/Kconfig b/drivers/mxc/pmic/mc13892/Kconfig
new file mode 100644
index 000000000000..930e06ab2282
--- /dev/null
+++ b/drivers/mxc/pmic/mc13892/Kconfig
@@ -0,0 +1,48 @@
+#
+# PMIC Modules configuration
+#
+
+config MXC_MC13892_ADC
+	tristate "MC13892 ADC support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 ADC module driver. This module provides kernel API
+	for the ADC system of MC13892.
+	It controls also the touch screen interface.
+	If you want MC13892 ADC support, you should say Y here
+
+config MXC_MC13892_RTC
+	tristate "MC13892 Real Time Clock (RTC) support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 RTC module driver. This module provides kernel API
+	for RTC part of MC13892.
+	If you want MC13892 RTC support, you should say Y here
+config MXC_MC13892_LIGHT
+	tristate "MC13892 Light and Backlight support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 Light module driver. This module provides kernel API
+	for led and backlight control part of MC13892.
+	If you want MC13892 Light support, you should say Y here
+config MXC_MC13892_BATTERY
+	tristate "MC13892 Battery API support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 battery module driver. This module provides kernel API
+	for battery control part of MC13892.
+	If you want MC13892 battery support, you should say Y here
+config MXC_MC13892_CONNECTIVITY
+	tristate "MC13892 Connectivity API support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 connectivity module driver. This module provides kernel API
+	for USB/RS232 connectivity control part of MC13892.
+	If you want MC13892 connectivity support, you should say Y here
+config MXC_MC13892_POWER
+	tristate "MC13892 Power API support"
+	depends on MXC_PMIC_MC13892
+	---help---
+	This is the MC13892 power and supplies module driver. This module provides kernel API
+	for power and regulator control part of MC13892.
+	If you want MC13892 power support, you should say Y here
diff --git a/drivers/mxc/pmic/mc13892/Makefile b/drivers/mxc/pmic/mc13892/Makefile
new file mode 100644
index 000000000000..0ed2b7eb4c11
--- /dev/null
+++ b/drivers/mxc/pmic/mc13892/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the mc13783 pmic drivers.
+#
+
+obj-$(CONFIG_MXC_MC13892_ADC) += pmic_adc.o
+#obj-$(CONFIG_MXC_MC13892_RTC) += pmic_rtc.o
+obj-$(CONFIG_MXC_MC13892_LIGHT) += pmic_light.o
+obj-$(CONFIG_MXC_MC13892_BATTERY) += pmic_battery.o
+#obj-$(CONFIG_MXC_MC13892_CONNECTIVITY) += pmic_convity.o
+#obj-$(CONFIG_MXC_MC13892_POWER) += pmic_power.o
diff --git a/drivers/mxc/pmic/mc13892/pmic_adc.c b/drivers/mxc/pmic/mc13892/pmic_adc.c
new file mode 100644
index 000000000000..cec4d6045974
--- /dev/null
+++ b/drivers/mxc/pmic/mc13892/pmic_adc.c
@@ -0,0 +1,984 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/device.h>
+
+#include <linux/pmic_adc.h>
+#include <linux/pmic_status.h>
+
+#include "../core/pmic.h"
+
+#define         DEF_ADC_0     0x008000
+#define         DEF_ADC_3     0x0001c0
+
+#define ADC_NB_AVAILABLE        2
+
+#define MAX_CHANNEL             7
+
+#define MC13892_ADC0_TS_M_LSH	14
+#define MC13892_ADC0_TS_M_WID	3
+
+/*
+ * Maximun allowed variation in the three X/Y co-ordinates acquired from
+ * touch-screen
+ */
+#define DELTA_Y_MAX             50
+#define DELTA_X_MAX             50
+
+/*
+ * ADC 0
+ */
+#define ADC_WAIT_TSI_0		0x001400
+
+#define ADC_INC                 0x030000
+#define ADC_BIS                 0x800000
+#define ADC_CHRGRAW_D5          0x008000
+
+/*
+ * ADC 1
+ */
+
+#define ADC_EN                  0x000001
+#define ADC_SGL_CH              0x000002
+#define ADC_ADSEL               0x000008
+#define ADC_CH_0_POS            5
+#define ADC_CH_0_MASK           0x0000E0
+#define ADC_CH_1_POS            8
+#define ADC_CH_1_MASK           0x000700
+#define ADC_DELAY_POS           11
+#define ADC_DELAY_MASK          0x07F800
+#define ADC_ATO                 0x080000
+#define ASC_ADC                 0x100000
+#define ADC_WAIT_TSI_1		0x200001
+#define ADC_NO_ADTRIG           0x200000
+
+/*
+ * ADC 2 - 4
+ */
+#define ADD1_RESULT_MASK        0x00000FFC
+#define ADD2_RESULT_MASK        0x00FFC000
+#define ADC_TS_MASK             0x00FFCFFC
+
+#define ADC_WCOMP               0x040000
+#define ADC_WCOMP_H_POS         0
+#define ADC_WCOMP_L_POS         9
+#define ADC_WCOMP_H_MASK        0x00003F
+#define ADC_WCOMP_L_MASK        0x007E00
+
+#define ADC_MODE_MASK           0x00003F
+
+#define ADC_INT_BISDONEI        0x02
+#define ADC_TSMODE_MASK 0x007000
+
+typedef enum adc_state {
+	ADC_FREE,
+	ADC_USED,
+	ADC_MONITORING,
+} t_adc_state;
+
+typedef enum reading_mode {
+	/*!
+	 * Enables lithium cell reading
+	 */
+	M_LITHIUM_CELL = 0x000001,
+	/*!
+	 * Enables charge current reading
+	 */
+	M_CHARGE_CURRENT = 0x000002,
+	/*!
+	 * Enables battery current reading
+	 */
+	M_BATTERY_CURRENT = 0x000004,
+} t_reading_mode;
+
+typedef struct {
+	/*!
+	 * Delay before first conversion
+	 */
+	unsigned int delay;
+	/*!
+	 * sets the ATX bit for delay on all conversion
+	 */
+	bool conv_delay;
+	/*!
+	 * Sets the single channel mode
+	 */
+	bool single_channel;
+	/*!
+	 * Channel selection 1
+	 */
+	t_channel channel_0;
+	/*!
+	 * Channel selection 2
+	 */
+	t_channel channel_1;
+	/*!
+	 * Used to configure ADC mode with t_reading_mode
+	 */
+	t_reading_mode read_mode;
+	/*!
+	 * Sets the Touch screen mode
+	 */
+	bool read_ts;
+	/*!
+	 * Wait TSI event before touch screen reading
+	 */
+	bool wait_tsi;
+	/*!
+	 * Sets CHRGRAW scaling to divide by 5
+	 * Only supported on 2.0 and higher
+	 */
+	bool chrgraw_devide_5;
+	/*!
+	 * Return ADC values
+	 */
+	unsigned int value[8];
+	/*!
+	 * Return touch screen values
+	 */
+	t_touch_screen ts_value;
+} t_adc_param;
+
+static int pmic_adc_filter(t_touch_screen *ts_curr);
+int mc13892_adc_request(bool read_ts);
+int mc13892_adc_release(int adc_index);
+t_reading_mode mc13892_set_read_mode(t_channel channel);
+PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *touch_sample, int wait_tsi);
+
+/* internal function */
+static void callback_tsi(void *);
+static void callback_adcdone(void *);
+static void callback_adcbisdone(void *);
+
+static int swait;
+
+static int suspend_flag;
+
+static wait_queue_head_t suspendq;
+
+/* EXPORTED FUNCTIONS */
+EXPORT_SYMBOL(pmic_adc_init);
+EXPORT_SYMBOL(pmic_adc_deinit);
+EXPORT_SYMBOL(pmic_adc_convert);
+EXPORT_SYMBOL(pmic_adc_convert_8x);
+EXPORT_SYMBOL(pmic_adc_set_touch_mode);
+EXPORT_SYMBOL(pmic_adc_get_touch_mode);
+EXPORT_SYMBOL(pmic_adc_get_touch_sample);
+
+static DECLARE_COMPLETION(adcdone_it);
+static DECLARE_COMPLETION(adcbisdone_it);
+static DECLARE_COMPLETION(adc_tsi);
+static pmic_event_callback_t tsi_event;
+static pmic_event_callback_t event_adc;
+static pmic_event_callback_t event_adc_bis;
+static bool data_ready_adc_1;
+static bool data_ready_adc_2;
+static bool adc_ts;
+static bool wait_ts;
+static bool monitor_en;
+static bool monitor_adc;
+static DECLARE_MUTEX(convert_mutex);
+
+static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy);
+static t_adc_state adc_dev[2];
+
+static unsigned channel_num[] = {
+	0,
+	1,
+	3,
+	4,
+	2,
+	0,
+	1,
+	3,
+	4,
+	-1,
+	5,
+	6,
+	7,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1
+};
+
+static bool pmic_adc_ready;
+
+int is_pmic_adc_ready()
+{
+	return pmic_adc_ready;
+}
+EXPORT_SYMBOL(is_pmic_adc_ready);
+
+
+static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	suspend_flag = 1;
+	CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS));
+
+	return 0;
+};
+
+static int pmic_adc_resume(struct platform_device *pdev)
+{
+	/* nothing for mc13892 adc */
+	unsigned int adc_0_reg, adc_1_reg, reg_mask;
+	suspend_flag = 0;
+
+	/* let interrupt of TSI again */
+	adc_0_reg = ADC_WAIT_TSI_0;
+	reg_mask = ADC_WAIT_TSI_0;
+	CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, reg_mask));
+	adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts);
+	CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS));
+
+	while (swait > 0) {
+		swait--;
+		wake_up_interruptible(&suspendq);
+	}
+
+	return 0;
+};
+
+static void callback_tsi(void *unused)
+{
+	pr_debug("*** TSI IT mc13892 PMIC_ADC_GET_TOUCH_SAMPLE ***\n");
+	if (wait_ts) {
+		complete(&adc_tsi);
+		pmic_event_mask(EVENT_TSI);
+	}
+}
+
+static void callback_adcdone(void *unused)
+{
+	if (data_ready_adc_1)
+		complete(&adcdone_it);
+}
+
+static void callback_adcbisdone(void *unused)
+{
+	pr_debug("* adcdone bis it callback *\n");
+	if (data_ready_adc_2)
+		complete(&adcbisdone_it);
+}
+
+static int pmic_adc_filter(t_touch_screen *ts_curr)
+{
+	unsigned int ydiff, xdiff;
+	unsigned int sample_sumx, sample_sumy;
+
+	if (ts_curr->contact_resistance == 0) {
+		ts_curr->x_position = 0;
+		ts_curr->y_position = 0;
+		return 0;
+	}
+
+	ydiff = abs(ts_curr->y_position1 - ts_curr->y_position2);
+	if (ydiff > DELTA_Y_MAX) {
+		pr_debug("pmic_adc_filter: Ret pos y\n");
+		return -1;
+	}
+
+	xdiff = abs(ts_curr->x_position1 - ts_curr->x_position2);
+	if (xdiff > DELTA_X_MAX) {
+		pr_debug("mc13892_adc_filter: Ret pos x\n");
+		return -1;
+	}
+
+	sample_sumx = ts_curr->x_position1 + ts_curr->x_position2;
+	sample_sumy = ts_curr->y_position1 + ts_curr->y_position2;
+
+	ts_curr->y_position = sample_sumy / 2;
+	ts_curr->x_position = sample_sumx / 2;
+
+	return 0;
+}
+
+int pmic_adc_init(void)
+{
+	unsigned int reg_value = 0, i = 0;
+
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	for (i = 0; i < ADC_NB_AVAILABLE; i++)
+		adc_dev[i] = ADC_FREE;
+
+	CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS));
+	reg_value = 0x001000;
+
+	data_ready_adc_1 = false;
+	data_ready_adc_2 = false;
+	adc_ts = false;
+	wait_ts = false;
+	monitor_en = false;
+	monitor_adc = false;
+
+	/* sub to ADCDone IT */
+	event_adc.param = NULL;
+	event_adc.func = callback_adcdone;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_ADCDONEI, event_adc));
+
+	/* sub to ADCDoneBis IT */
+	event_adc_bis.param = NULL;
+	event_adc_bis.func = callback_adcbisdone;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_ADCBISDONEI, event_adc_bis));
+
+	/* sub to Touch Screen IT */
+	tsi_event.param = NULL;
+	tsi_event.func = callback_tsi;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event));
+
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS pmic_adc_deinit(void)
+{
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCDONEI, event_adc));
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCBISDONEI, event_adc_bis));
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event));
+
+	return PMIC_SUCCESS;
+}
+
+int mc13892_adc_init_param(t_adc_param * adc_param)
+{
+	int i = 0;
+
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	adc_param->delay = 0;
+	adc_param->conv_delay = false;
+	adc_param->single_channel = false;
+	adc_param->channel_0 = BATTERY_VOLTAGE;
+	adc_param->channel_1 = BATTERY_VOLTAGE;
+	adc_param->read_mode = 0;
+	adc_param->wait_tsi = 0;
+	adc_param->chrgraw_devide_5 = true;
+	adc_param->read_ts = false;
+	adc_param->ts_value.x_position = 0;
+	adc_param->ts_value.y_position = 0;
+	adc_param->ts_value.contact_resistance = 0;
+	for (i = 0; i <= MAX_CHANNEL; i++)
+		adc_param->value[i] = 0;
+
+	return 0;
+}
+
+PMIC_STATUS mc13892_adc_convert(t_adc_param * adc_param)
+{
+	bool use_bis = false;
+	unsigned int adc_0_reg = 0, adc_1_reg = 0, reg_1 = 0, result_reg =
+	    0, i = 0;
+	unsigned int result = 0, temp = 0;
+	pmic_version_t mc13892_ver;
+	pr_debug("mc13892 ADC - mc13892_adc_convert ....\n");
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	if (adc_param->wait_tsi) {
+		/* configure adc to wait tsi interrupt */
+		INIT_COMPLETION(adc_tsi);
+
+		/*for ts don't use bis */
+		/*put ts in interrupt mode */
+		/* still kep reference? */
+		adc_0_reg = 0x001400 | (ADC_BIS * 0);
+		pmic_event_unmask(EVENT_TSI);
+		CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, PMIC_ALL_BITS));
+		/*for ts don't use bis */
+		adc_1_reg = 0x200001 | (ADC_BIS * 0);
+		CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS));
+		pr_debug("wait tsi ....\n");
+		wait_ts = true;
+		wait_for_completion_interruptible(&adc_tsi);
+		wait_ts = false;
+	}
+	down(&convert_mutex);
+	use_bis = mc13892_adc_request(adc_param->read_ts);
+	if (use_bis < 0) {
+		pr_debug("process has received a signal and got interrupted\n");
+		return -EINTR;
+	}
+
+	/* CONFIGURE ADC REG 0 */
+	adc_0_reg = 0;
+	adc_1_reg = 0;
+	if (adc_param->read_ts == false) {
+		adc_0_reg = adc_param->read_mode & 0x00003F;
+		/* add auto inc */
+		adc_0_reg |= ADC_INC;
+		if (use_bis) {
+			/* add adc bis */
+			adc_0_reg |= ADC_BIS;
+		}
+		mc13892_ver = pmic_get_version();
+		if (mc13892_ver.revision >= 20)
+			if (adc_param->chrgraw_devide_5)
+				adc_0_reg |= ADC_CHRGRAW_D5;
+
+		if (adc_param->single_channel)
+			adc_1_reg |= ADC_SGL_CH;
+
+		if (adc_param->conv_delay)
+			adc_1_reg |= ADC_ATO;
+
+		if (adc_param->single_channel)
+			adc_1_reg |= ADC_SGL_CH;
+
+		adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) &
+		    ADC_CH_0_MASK;
+		adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) &
+		    ADC_CH_1_MASK;
+	} else {
+		adc_0_reg = 0x002400 | (ADC_BIS * use_bis) | ADC_INC;
+	}
+	pr_debug("Write Reg %i = %x\n", REG_ADC0, adc_0_reg);
+	/*Change has been made here */
+	CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg,
+				   ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 |
+				   0xfff00ff));
+	/* CONFIGURE ADC REG 1 */
+	if (adc_param->read_ts == false) {
+		adc_1_reg |= ADC_NO_ADTRIG;
+		adc_1_reg |= ADC_EN;
+		adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) &
+		    ADC_DELAY_MASK;
+		if (use_bis)
+			adc_1_reg |= ADC_BIS;
+	} else {
+		/* configure and start convert to read x and y position */
+		/* configure to read 2 value in channel selection 1 & 2 */
+		adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG;
+		/* set ATOx = 5, it could be better for ts ADC */
+		adc_1_reg |= 0x002800;
+	}
+	reg_1 = adc_1_reg;
+	if (use_bis == 0) {
+		data_ready_adc_1 = false;
+		adc_1_reg |= ASC_ADC;
+		data_ready_adc_1 = true;
+		pr_debug("Write Reg %i = %x\n", REG_ADC1, adc_1_reg);
+		INIT_COMPLETION(adcdone_it);
+		CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg,
+					   ADC_SGL_CH | ADC_ATO | ADC_ADSEL
+					   | ADC_CH_0_MASK | ADC_CH_1_MASK |
+					   ADC_NO_ADTRIG | ADC_EN |
+					   ADC_DELAY_MASK | ASC_ADC | ADC_BIS));
+		pr_debug("wait adc done \n");
+		wait_for_completion_interruptible(&adcdone_it);
+		data_ready_adc_1 = false;
+	} else {
+		data_ready_adc_2 = false;
+		adc_1_reg |= ASC_ADC;
+		data_ready_adc_2 = true;
+		INIT_COMPLETION(adcbisdone_it);
+		CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, 0xFFFFFF));
+		temp = 0x800000;
+		CHECK_ERROR(pmic_write_reg(REG_ADC3, temp, 0xFFFFFF));
+		pr_debug("wait adc done bis\n");
+		wait_for_completion_interruptible(&adcbisdone_it);
+		data_ready_adc_2 = false;
+	}
+	/* read result and store in adc_param */
+	result = 0;
+	if (use_bis == 0)
+		result_reg = REG_ADC2;
+	else
+		result_reg = REG_ADC4;
+
+	CHECK_ERROR(pmic_write_reg(REG_ADC1, 4 << ADC_CH_1_POS,
+				   ADC_CH_0_MASK | ADC_CH_1_MASK));
+
+	for (i = 0; i <= 3; i++) {
+		CHECK_ERROR(pmic_read_reg(result_reg, &result, PMIC_ALL_BITS));
+		adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2);
+		adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14);
+		pr_debug("value[%d] = %d, value[%d] = %d\n",
+			 i, adc_param->value[i],
+			 i + 4, adc_param->value[i + 4]);
+	}
+	if (adc_param->read_ts) {
+		adc_param->ts_value.x_position = adc_param->value[0];
+		adc_param->ts_value.x_position1 = adc_param->value[0];
+		adc_param->ts_value.x_position2 = adc_param->value[1];
+		adc_param->ts_value.y_position = adc_param->value[3];
+		adc_param->ts_value.y_position1 = adc_param->value[3];
+		adc_param->ts_value.y_position2 = adc_param->value[4];
+		adc_param->ts_value.contact_resistance = adc_param->value[6];
+		CHECK_ERROR(pmic_write_reg(REG_ADC0, 0x0,
+				   ADC_TSMODE_MASK));
+	}
+
+	/*if (adc_param->read_ts) {
+	   adc_param->ts_value.x_position = adc_param->value[2];
+	   adc_param->ts_value.y_position = adc_param->value[5];
+	   adc_param->ts_value.contact_resistance = adc_param->value[6];
+	   } */
+	mc13892_adc_release(use_bis);
+	up(&convert_mutex);
+
+	return PMIC_SUCCESS;
+}
+
+t_reading_mode mc13892_set_read_mode(t_channel channel)
+{
+	t_reading_mode read_mode = 0;
+
+	switch (channel) {
+	case CHARGE_CURRENT:
+		read_mode = M_CHARGE_CURRENT;
+		break;
+	case BATTERY_CURRENT:
+		read_mode = M_BATTERY_CURRENT;
+		break;
+	default:
+		read_mode = 0;
+	}
+
+	return read_mode;
+}
+
+PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result)
+{
+	t_adc_param adc_param;
+	PMIC_STATUS ret;
+
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	channel = channel_num[channel];
+	if (channel == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+	mc13892_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert\n");
+	adc_param.read_ts = false;
+	adc_param.single_channel = true;
+	adc_param.read_mode = mc13892_set_read_mode(channel);
+
+	/* Find the group */
+	if (channel <= 7)
+		adc_param.channel_0 = channel;
+	else
+		return PMIC_PARAMETER_ERROR;
+
+	ret = mc13892_adc_convert(&adc_param);
+	*result = adc_param.value[0];
+	return ret;
+}
+
+PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result)
+{
+	t_adc_param adc_param;
+	int i;
+	PMIC_STATUS ret;
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	channel = channel_num[channel];
+
+	if (channel == -1) {
+		pr_debug("Wrong channel ID\n");
+		return PMIC_PARAMETER_ERROR;
+	}
+	mc13892_adc_init_param(&adc_param);
+	pr_debug("pmic_adc_convert_8x\n");
+	adc_param.read_ts = false;
+	adc_param.single_channel = true;
+	adc_param.read_mode = mc13892_set_read_mode(channel);
+
+	if (channel <= 7) {
+		adc_param.channel_0 = channel;
+		adc_param.channel_1 = channel;
+	} else
+		return PMIC_PARAMETER_ERROR;
+
+	ret = mc13892_adc_convert(&adc_param);
+	for (i = 0; i <= 7; i++)
+		result[i] = adc_param.value[i];
+
+	return ret;
+}
+
+PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode)
+{
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	CHECK_ERROR(pmic_write_reg(REG_ADC0,
+				   BITFVAL(MC13892_ADC0_TS_M, touch_mode),
+				   BITFMASK(MC13892_ADC0_TS_M)));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode * touch_mode)
+{
+	unsigned int value;
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	CHECK_ERROR(pmic_read_reg(REG_ADC0, &value, PMIC_ALL_BITS));
+
+	*touch_mode = BITFEXT(value, MC13892_ADC0_TS_M);
+
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen *touch_sample, int wait)
+{
+	if (mc13892_adc_read_ts(touch_sample, wait) != 0)
+		return PMIC_ERROR;
+	if (0 == pmic_adc_filter(touch_sample))
+		return PMIC_SUCCESS;
+	else
+		return PMIC_ERROR;
+}
+
+PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *ts_value, int wait_tsi)
+{
+	t_adc_param param;
+	pr_debug("mc13892_adc : mc13892_adc_read_ts\n");
+	if (suspend_flag == 1)
+		return -EBUSY;
+
+	if (wait_ts) {
+		pr_debug("mc13892_adc : error TS busy \n");
+		return PMIC_ERROR;
+	}
+	mc13892_adc_init_param(&param);
+	param.wait_tsi = wait_tsi;
+	param.read_ts = true;
+	if (mc13892_adc_convert(&param) != 0)
+		return PMIC_ERROR;
+	/* check if x-y is ok */
+	if (param.ts_value.contact_resistance < 1000) {
+		ts_value->x_position = param.ts_value.x_position;
+		ts_value->x_position1 = param.ts_value.x_position1;
+		ts_value->x_position2 = param.ts_value.x_position2;
+
+		ts_value->y_position = param.ts_value.y_position;
+		ts_value->y_position1 = param.ts_value.y_position1;
+		ts_value->y_position2 = param.ts_value.y_position2;
+
+		ts_value->contact_resistance =
+		    param.ts_value.contact_resistance + 1;
+
+	} else {
+		ts_value->x_position = 0;
+		ts_value->y_position = 0;
+		ts_value->contact_resistance = 0;
+
+	}
+	return PMIC_SUCCESS;
+}
+
+int mc13892_adc_request(bool read_ts)
+{
+	int adc_index = -1;
+	if (read_ts != 0) {
+		/*for ts we use bis=0 */
+		if (adc_dev[0] == ADC_USED)
+			return -1;
+		/*no wait here */
+		adc_dev[0] = ADC_USED;
+		adc_index = 0;
+	} else {
+		/*for other adc use bis = 1 */
+		if (adc_dev[1] == ADC_USED) {
+			return -1;
+			/*no wait here */
+		}
+		adc_dev[1] = ADC_USED;
+		adc_index = 1;
+	}
+	pr_debug("mc13892_adc : request ADC %d\n", adc_index);
+	return adc_index;
+}
+
+int mc13892_adc_release(int adc_index)
+{
+	while (suspend_flag == 1) {
+		swait++;
+		/* Block if the device is suspended */
+		if (wait_event_interruptible(suspendq, (suspend_flag == 0)))
+			return -ERESTARTSYS;
+	}
+
+	pr_debug("mc13892_adc : release ADC %d\n", adc_index);
+	if ((adc_dev[adc_index] == ADC_MONITORING) ||
+	    (adc_dev[adc_index] == ADC_USED)) {
+		adc_dev[adc_index] = ADC_FREE;
+		wake_up(&queue_adc_busy);
+		return 0;
+	}
+	return -1;
+}
+
+#ifdef DEBUG
+static t_adc_param adc_param_db;
+
+static ssize_t adc_info(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	int *value = adc_param_db.value;
+
+	pr_debug("adc_info\n");
+
+	pr_debug("ch0\t\t%d\n", adc_param_db.channel_0);
+	pr_debug("ch1\t\t%d\n", adc_param_db.channel_1);
+	pr_debug("d5\t\t%d\n", adc_param_db.chrgraw_devide_5);
+	pr_debug("conv delay\t%d\n", adc_param_db.conv_delay);
+	pr_debug("delay\t\t%d\n", adc_param_db.delay);
+	pr_debug("read mode\t%d\n", adc_param_db.read_mode);
+	pr_debug("read ts\t\t%d\n", adc_param_db.read_ts);
+	pr_debug("single ch\t%d\n", adc_param_db.single_channel);
+	pr_debug("wait ts int\t%d\n", adc_param_db.wait_tsi);
+	pr_debug("value0-3:\t%d\t%d\t%d\t%d\n", value[0], value[1],
+		 value[2], value[3]);
+	pr_debug("value4-7:\t%d\t%d\t%d\t%d\n", value[4], value[5],
+		 value[6], value[7]);
+
+	return 0;
+}
+
+enum {
+	ADC_SET_CH0 = 0,
+	ADC_SET_CH1,
+	ADC_SET_DV5,
+	ADC_SET_CON_DELAY,
+	ADC_SET_DELAY,
+	ADC_SET_RM,
+	ADC_SET_RT,
+	ADC_SET_S_CH,
+	ADC_SET_WAIT_TS,
+	ADC_INIT_P,
+	ADC_START,
+	ADC_TS,
+	ADC_TS_READ,
+	ADC_TS_CAL,
+	ADC_CMD_MAX
+};
+
+static const char *const adc_cmd[ADC_CMD_MAX] = {
+	[ADC_SET_CH0] = "ch0",
+	[ADC_SET_CH1] = "ch1",
+	[ADC_SET_DV5] = "dv5",
+	[ADC_SET_CON_DELAY] = "cd",
+	[ADC_SET_DELAY] = "dl",
+	[ADC_SET_RM] = "rm",
+	[ADC_SET_RT] = "rt",
+	[ADC_SET_S_CH] = "sch",
+	[ADC_SET_WAIT_TS] = "wt",
+	[ADC_INIT_P] = "init",
+	[ADC_START] = "start",
+	[ADC_TS] = "touch",
+	[ADC_TS_READ] = "touchr",
+	[ADC_TS_CAL] = "cal"
+};
+
+static int cmd(unsigned int index, int value)
+{
+	t_touch_screen ts;
+
+	switch (index) {
+	case ADC_SET_CH0:
+		adc_param_db.channel_0 = value;
+		break;
+	case ADC_SET_CH1:
+		adc_param_db.channel_1 = value;
+		break;
+	case ADC_SET_DV5:
+		adc_param_db.chrgraw_devide_5 = value;
+		break;
+	case ADC_SET_CON_DELAY:
+		adc_param_db.conv_delay = value;
+		break;
+	case ADC_SET_RM:
+		adc_param_db.read_mode = value;
+		break;
+	case ADC_SET_RT:
+		adc_param_db.read_ts = value;
+		break;
+	case ADC_SET_S_CH:
+		adc_param_db.single_channel = value;
+		break;
+	case ADC_SET_WAIT_TS:
+		adc_param_db.wait_tsi = value;
+		break;
+	case ADC_INIT_P:
+		mc13892_adc_init_param(&adc_param_db);
+		break;
+	case ADC_START:
+		mc13892_adc_convert(&adc_param_db);
+		break;
+	case ADC_TS:
+		pmic_adc_get_touch_sample(&ts, 1);
+		pr_debug("x = %d\n", ts.x_position);
+		pr_debug("y = %d\n", ts.y_position);
+		pr_debug("p = %d\n", ts.contact_resistance);
+		break;
+	case ADC_TS_READ:
+		pmic_adc_get_touch_sample(&ts, 0);
+		pr_debug("x = %d\n", ts.x_position);
+		pr_debug("y = %d\n", ts.y_position);
+		pr_debug("p = %d\n", ts.contact_resistance);
+		break;
+	case ADC_TS_CAL:
+		break;
+	default:
+		pr_debug("error command\n");
+		break;
+	}
+	return 0;
+}
+
+static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr,
+		       const char *buf, size_t count)
+{
+	int state = 0;
+	const char *const *s;
+	char *p, *q;
+	int error;
+	int len, value = 0;
+
+	pr_debug("adc_ctl\n");
+
+	q = NULL;
+	q = memchr(buf, ' ', count);
+
+	if (q != NULL) {
+		len = q - buf;
+		q += 1;
+		value = simple_strtoul(q, NULL, 10);
+	} else {
+		p = memchr(buf, '\n', count);
+		len = p ? p - buf : count;
+	}
+
+	for (s = &adc_cmd[state]; state < ADC_CMD_MAX; s++, state++) {
+		if (*s && !strncmp(buf, *s, len))
+			break;
+	}
+	if (state < ADC_CMD_MAX && *s)
+		error = cmd(state, value);
+	else
+		error = -EINVAL;
+
+	return count;
+}
+
+#else
+static ssize_t adc_info(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return 0;
+}
+
+static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr,
+		       const char *buf, size_t count)
+{
+	return count;
+}
+
+#endif
+
+static DEVICE_ATTR(adc, 0644, adc_info, adc_ctl);
+
+static int pmic_adc_module_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+
+	pr_debug("PMIC ADC start probe\n");
+	ret = device_create_file(&(pdev->dev), &dev_attr_adc);
+	if (ret) {
+		pr_debug("Can't create device file!\n");
+		return -ENODEV;
+	}
+
+	init_waitqueue_head(&suspendq);
+
+	ret = pmic_adc_init();
+	if (ret != PMIC_SUCCESS) {
+		pr_debug("Error in pmic_adc_init.\n");
+		goto rm_dev_file;
+	}
+
+	pmic_adc_ready = 1;
+	pr_debug("PMIC ADC successfully probed\n");
+	return 0;
+
+      rm_dev_file:
+	device_remove_file(&(pdev->dev), &dev_attr_adc);
+	return ret;
+}
+
+static int pmic_adc_module_remove(struct platform_device *pdev)
+{
+	pmic_adc_deinit();
+	pmic_adc_ready = 0;
+	pr_debug("PMIC ADC successfully removed\n");
+	return 0;
+}
+
+static struct platform_driver pmic_adc_driver_ldm = {
+	.driver = {
+		   .name = "pmic_adc",
+		   },
+	.suspend = pmic_adc_suspend,
+	.resume = pmic_adc_resume,
+	.probe = pmic_adc_module_probe,
+	.remove = pmic_adc_module_remove,
+};
+
+static int __init pmic_adc_module_init(void)
+{
+	pr_debug("PMIC ADC driver loading...\n");
+	return platform_driver_register(&pmic_adc_driver_ldm);
+}
+
+static void __exit pmic_adc_module_exit(void)
+{
+	platform_driver_unregister(&pmic_adc_driver_ldm);
+	pr_debug("PMIC ADC driver successfully unloaded\n");
+}
+
+module_init(pmic_adc_module_init);
+module_exit(pmic_adc_module_exit);
+
+MODULE_DESCRIPTION("PMIC ADC device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13892/pmic_battery.c b/drivers/mxc/pmic/mc13892/pmic_battery.c
new file mode 100644
index 000000000000..5849ab101191
--- /dev/null
+++ b/drivers/mxc/pmic/mc13892/pmic_battery.c
@@ -0,0 +1,634 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Includes
+ */
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+
+#include <linux/delay.h>
+#include <asm/mach-types.h>
+#include <linux/pmic_battery.h>
+#include <linux/pmic_adc.h>
+#include <linux/pmic_status.h>
+
+#define BIT_CHG_VOL_LSH		0
+#define BIT_CHG_VOL_WID		3
+
+#define BIT_CHG_CURR_LSH		3
+#define BIT_CHG_CURR_WID		4
+
+#define BIT_CHG_PLIM_LSH		15
+#define BIT_CHG_PLIM_WID		2
+
+#define BIT_CHG_DETS_LSH 6
+#define BIT_CHG_DETS_WID 1
+#define BIT_CHG_CURRS_LSH 11
+#define BIT_CHG_CURRS_WID 1
+
+#define TRICKLE_CHG_EN_LSH	7
+#define	LOW_POWER_BOOT_ACK_LSH	8
+#define BAT_TH_CHECK_DIS_LSH	9
+#define	BATTFET_CTL_EN_LSH	10
+#define BATTFET_CTL_LSH		11
+#define	REV_MOD_EN_LSH		13
+#define PLIM_DIS_LSH		17
+#define	CHG_LED_EN_LSH		18
+#define RESTART_CHG_STAT_LSH	20
+#define	AUTO_CHG_DIS_LSH	21
+#define CYCLING_DIS_LSH		22
+#define	VI_PROGRAM_EN_LSH	23
+
+#define TRICKLE_CHG_EN_WID	1
+#define	LOW_POWER_BOOT_ACK_WID	1
+#define BAT_TH_CHECK_DIS_WID	1
+#define	BATTFET_CTL_EN_WID	1
+#define BATTFET_CTL_WID		1
+#define	REV_MOD_EN_WID		1
+#define PLIM_DIS_WID		1
+#define	CHG_LED_EN_WID		1
+#define RESTART_CHG_STAT_WID	1
+#define	AUTO_CHG_DIS_WID	1
+#define CYCLING_DIS_WID		1
+#define	VI_PROGRAM_EN_WID	1
+
+#define ACC_STARTCC_LSH		0
+#define ACC_STARTCC_WID		1
+#define ACC_RSTCC_LSH		1
+#define ACC_RSTCC_WID		1
+#define ACC_CCFAULT_LSH		7
+#define ACC_CCFAULT_WID		7
+#define ACC_CCOUT_LSH		8
+#define ACC_CCOUT_WID		16
+#define ACC1_ONEC_LSH		0
+#define ACC1_ONEC_WID		15
+
+#define ACC_CALIBRATION 0x17
+#define ACC_START_COUNTER 0x07
+#define ACC_STOP_COUNTER 0x2
+#define ACC_CONTROL_BIT_MASK 0x1f
+#define ACC_ONEC_VALUE 2621
+#define ACC_COULOMB_PER_LSB 1
+#define ACC_CALIBRATION_DURATION_MSECS 20
+
+#define BAT_VOLTAGE_UNIT_UV 4692
+#define BAT_CURRENT_UNIT_UA 5870
+#define CHG_VOLTAGE_UINT_UV 23474
+#define CHG_MIN_CURRENT_UA 3500
+
+#define COULOMB_TO_UAH(c) (10000 * c / 36)
+
+enum chg_setting {
+       TRICKLE_CHG_EN,
+       LOW_POWER_BOOT_ACK,
+       BAT_TH_CHECK_DIS,
+       BATTFET_CTL_EN,
+       BATTFET_CTL,
+       REV_MOD_EN,
+       PLIM_DIS,
+       CHG_LED_EN,
+       RESTART_CHG_STAT,
+       AUTO_CHG_DIS,
+       CYCLING_DIS,
+       VI_PROGRAM_EN
+};
+
+static int pmic_set_chg_current(unsigned short curr)
+{
+	unsigned int mask;
+	unsigned int value;
+
+	value = BITFVAL(BIT_CHG_CURR, curr);
+	mask = BITFMASK(BIT_CHG_CURR);
+	CHECK_ERROR(pmic_write_reg(REG_CHARGE, value, mask));
+
+	return 0;
+}
+
+static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag)
+{
+
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+
+	switch (type) {
+	case TRICKLE_CHG_EN:
+		reg_value = BITFVAL(TRICKLE_CHG_EN, flag);
+		mask = BITFMASK(TRICKLE_CHG_EN);
+		break;
+	case LOW_POWER_BOOT_ACK:
+		reg_value = BITFVAL(LOW_POWER_BOOT_ACK, flag);
+		mask = BITFMASK(LOW_POWER_BOOT_ACK);
+		break;
+	case BAT_TH_CHECK_DIS:
+		reg_value = BITFVAL(BAT_TH_CHECK_DIS, flag);
+		mask = BITFMASK(BAT_TH_CHECK_DIS);
+		break;
+	case BATTFET_CTL_EN:
+		reg_value = BITFVAL(BATTFET_CTL_EN, flag);
+		mask = BITFMASK(BATTFET_CTL_EN);
+		break;
+	case BATTFET_CTL:
+		reg_value = BITFVAL(BATTFET_CTL, flag);
+		mask = BITFMASK(BATTFET_CTL);
+		break;
+	case REV_MOD_EN:
+		reg_value = BITFVAL(REV_MOD_EN, flag);
+		mask = BITFMASK(REV_MOD_EN);
+		break;
+	case PLIM_DIS:
+		reg_value = BITFVAL(PLIM_DIS, flag);
+		mask = BITFMASK(PLIM_DIS);
+		break;
+	case CHG_LED_EN:
+		reg_value = BITFVAL(CHG_LED_EN, flag);
+		mask = BITFMASK(CHG_LED_EN);
+		break;
+	case RESTART_CHG_STAT:
+		reg_value = BITFVAL(RESTART_CHG_STAT, flag);
+		mask = BITFMASK(RESTART_CHG_STAT);
+		break;
+	case AUTO_CHG_DIS:
+		reg_value = BITFVAL(AUTO_CHG_DIS, flag);
+		mask = BITFMASK(AUTO_CHG_DIS);
+		break;
+	case CYCLING_DIS:
+		reg_value = BITFVAL(CYCLING_DIS, flag);
+		mask = BITFMASK(CYCLING_DIS);
+		break;
+	case VI_PROGRAM_EN:
+		reg_value = BITFVAL(VI_PROGRAM_EN, flag);
+		mask = BITFMASK(VI_PROGRAM_EN);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_write_reg(REG_CHARGE, reg_value, mask));
+
+	return 0;
+}
+
+static int pmic_get_batt_voltage(unsigned short *voltage)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	channel = BATTERY_VOLTAGE;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*voltage = result[0];
+
+	return 0;
+}
+
+static int pmic_get_batt_current(unsigned short *curr)
+{
+	t_channel channel;
+	unsigned short result[8];
+
+	channel = BATTERY_CURRENT;
+	CHECK_ERROR(pmic_adc_convert(channel, result));
+	*curr = result[0];
+
+	return 0;
+}
+
+static int coulomb_counter_calibration;
+static unsigned int coulomb_counter_start_time_msecs;
+
+static int pmic_start_coulomb_counter(void)
+{
+	/* set scaler */
+	CHECK_ERROR(pmic_write_reg(REG_ACC1,
+		ACC_COULOMB_PER_LSB * ACC_ONEC_VALUE, BITFMASK(ACC1_ONEC)));
+
+	CHECK_ERROR(pmic_write_reg(
+		REG_ACC0, ACC_START_COUNTER, ACC_CONTROL_BIT_MASK));
+	coulomb_counter_start_time_msecs = jiffies_to_msecs(jiffies);
+	pr_debug("coulomb counter start time %u\n",
+		coulomb_counter_start_time_msecs);
+	return 0;
+}
+
+static int pmic_stop_coulomb_counter(void)
+{
+	CHECK_ERROR(pmic_write_reg(
+		REG_ACC0, ACC_STOP_COUNTER, ACC_CONTROL_BIT_MASK));
+	return 0;
+}
+
+static int pmic_calibrate_coulomb_counter(void)
+{
+	int ret;
+	unsigned int value;
+
+	/* set scaler */
+	CHECK_ERROR(pmic_write_reg(REG_ACC1,
+		0x1, BITFMASK(ACC1_ONEC)));
+
+	CHECK_ERROR(pmic_write_reg(
+		REG_ACC0, ACC_CALIBRATION, ACC_CONTROL_BIT_MASK));
+	msleep(ACC_CALIBRATION_DURATION_MSECS);
+
+	ret = pmic_read_reg(REG_ACC0, &value, BITFMASK(ACC_CCOUT));
+	if (ret != 0)
+		return -1;
+	value = BITFEXT(value, ACC_CCOUT);
+	pr_debug("calibrate value = %x\n", value);
+	coulomb_counter_calibration = (int)((s16)((u16) value));
+	pr_debug("coulomb_counter_calibration = %d\n",
+		coulomb_counter_calibration);
+
+	return 0;
+
+}
+
+static int pmic_get_charger_coulomb(int *coulomb)
+{
+	int ret;
+	unsigned int value;
+	int calibration;
+	unsigned int time_diff_msec;
+
+	ret = pmic_read_reg(REG_ACC0, &value, BITFMASK(ACC_CCOUT));
+	if (ret != 0)
+		return -1;
+	value = BITFEXT(value, ACC_CCOUT);
+	pr_debug("counter value = %x\n", value);
+	*coulomb = ((s16)((u16)value)) * ACC_COULOMB_PER_LSB;
+
+	if (abs(*coulomb) >= ACC_COULOMB_PER_LSB) {
+			/* calibrate */
+		time_diff_msec = jiffies_to_msecs(jiffies);
+		time_diff_msec =
+			(time_diff_msec > coulomb_counter_start_time_msecs) ?
+			(time_diff_msec - coulomb_counter_start_time_msecs) :
+			(0xffffffff - coulomb_counter_start_time_msecs
+			+ time_diff_msec);
+		calibration = coulomb_counter_calibration * (int)time_diff_msec
+			/ (ACC_ONEC_VALUE * ACC_CALIBRATION_DURATION_MSECS);
+		*coulomb -= calibration;
+	}
+
+	return 0;
+}
+
+static int pmic_restart_charging(void)
+{
+	pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1);
+	pmic_set_chg_misc(AUTO_CHG_DIS, 0);
+	pmic_set_chg_misc(VI_PROGRAM_EN, 1);
+	pmic_set_chg_current(0x8);
+	pmic_set_chg_misc(RESTART_CHG_STAT, 1);
+	return 0;
+}
+
+struct mc13892_dev_info {
+	struct device *dev;
+
+	unsigned short voltage_raw;
+	int voltage_uV;
+	unsigned short current_raw;
+	int current_uA;
+	int battery_status;
+	int full_counter;
+	int charger_online;
+	int charger_voltage_uV;
+	int accum_current_uAh;
+
+	struct power_supply bat;
+	struct power_supply charger;
+
+	struct workqueue_struct *monitor_wqueue;
+	struct delayed_work monitor_work;
+};
+
+#define mc13892_SENSER	25
+#define to_mc13892_dev_info(x) container_of((x), struct mc13892_dev_info, \
+					      bat);
+
+static enum power_supply_property mc13892_battery_props[] = {
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_CHARGE_NOW,
+	POWER_SUPPLY_PROP_STATUS,
+};
+
+static enum power_supply_property mc13892_charger_props[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+static int mc13892_charger_update_status(struct mc13892_dev_info *di)
+{
+	int ret;
+	unsigned int value;
+	int online;
+
+	ret = pmic_read_reg(REG_INT_SENSE0, &value, BITFMASK(BIT_CHG_DETS));
+
+	if (ret == 0) {
+		online = BITFEXT(value, BIT_CHG_DETS);
+		if (online != di->charger_online) {
+			di->charger_online = online;
+			dev_info(di->charger.dev, "charger status: %s\n",
+				online ? "online" : "offline");
+			power_supply_changed(&di->charger);
+
+			cancel_delayed_work(&di->monitor_work);
+			queue_delayed_work(di->monitor_wqueue,
+				&di->monitor_work, HZ / 10);
+			if (online) {
+				pmic_start_coulomb_counter();
+				pmic_restart_charging();
+			} else
+				pmic_stop_coulomb_counter();
+		}
+	}
+
+	return ret;
+}
+
+static int mc13892_charger_get_property(struct power_supply *psy,
+				       enum power_supply_property psp,
+				       union power_supply_propval *val)
+{
+	struct mc13892_dev_info *di =
+		container_of((psy), struct mc13892_dev_info, charger);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = di->charger_online;
+		return 0;
+	default:
+		break;
+	}
+	return -EINVAL;
+}
+
+static int mc13892_battery_read_status(struct mc13892_dev_info *di)
+{
+	int retval;
+	int coulomb;
+	retval = pmic_get_batt_voltage(&(di->voltage_raw));
+	if (retval == 0)
+		di->voltage_uV = di->voltage_raw * BAT_VOLTAGE_UNIT_UV;
+
+	retval = pmic_get_batt_current(&(di->current_raw));
+	if (retval == 0) {
+		if (di->current_raw & 0x200)
+			di->current_uA =
+				(0x1FF - (di->current_raw & 0x1FF)) *
+				BAT_CURRENT_UNIT_UA * (-1);
+		else
+			di->current_uA =
+				(di->current_raw & 0x1FF) * BAT_CURRENT_UNIT_UA;
+	}
+	retval = pmic_get_charger_coulomb(&coulomb);
+	if (retval == 0)
+		di->accum_current_uAh = COULOMB_TO_UAH(coulomb);
+
+	return retval;
+}
+
+static void mc13892_battery_update_status(struct mc13892_dev_info *di)
+{
+	unsigned int value;
+	int retval;
+	int old_battery_status = di->battery_status;
+
+	if (di->battery_status == POWER_SUPPLY_STATUS_UNKNOWN)
+		di->full_counter = 0;
+
+	if (di->charger_online) {
+		retval = pmic_read_reg(REG_INT_SENSE0,
+					&value, BITFMASK(BIT_CHG_CURRS));
+
+		if (retval == 0) {
+			value = BITFEXT(value, BIT_CHG_CURRS);
+			if (value)
+				di->battery_status =
+					POWER_SUPPLY_STATUS_CHARGING;
+			else
+				di->battery_status =
+					POWER_SUPPLY_STATUS_NOT_CHARGING;
+		}
+
+		if (di->battery_status == POWER_SUPPLY_STATUS_NOT_CHARGING)
+			di->full_counter++;
+		else
+			di->full_counter = 0;
+	} else {
+		di->battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
+		di->full_counter = 0;
+	}
+
+	dev_dbg(di->bat.dev, "bat status: %d\n",
+		di->battery_status);
+
+	if (di->battery_status != old_battery_status)
+		power_supply_changed(&di->bat);
+}
+
+static void mc13892_battery_work(struct work_struct *work)
+{
+	struct mc13892_dev_info *di = container_of(work,
+						     struct mc13892_dev_info,
+						     monitor_work.work);
+	const int interval = HZ * 60;
+
+	dev_dbg(di->dev, "%s\n", __func__);
+
+	mc13892_battery_update_status(di);
+	queue_delayed_work(di->monitor_wqueue, &di->monitor_work, interval);
+}
+
+static void charger_online_event_callback(void *para)
+{
+	struct mc13892_dev_info *di = (struct mc13892_dev_info *) para;
+	pr_info("\n\n DETECTED charger plug/unplug event\n");
+	mc13892_charger_update_status(di);
+}
+
+
+static int mc13892_battery_get_property(struct power_supply *psy,
+				       enum power_supply_property psp,
+				       union power_supply_propval *val)
+{
+	struct mc13892_dev_info *di = to_mc13892_dev_info(psy);
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		if (di->battery_status == POWER_SUPPLY_STATUS_UNKNOWN) {
+			mc13892_charger_update_status(di);
+			mc13892_battery_update_status(di);
+		}
+		val->intval = di->battery_status;
+		return 0;
+	default:
+		break;
+	}
+
+	mc13892_battery_read_status(di);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		val->intval = di->voltage_uV;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		val->intval = di->current_uA;
+		break;
+	case POWER_SUPPLY_PROP_CHARGE_NOW:
+		val->intval = di->accum_current_uAh;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+		val->intval = 3800000;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+		val->intval = 3300000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int pmic_battery_remove(struct platform_device *pdev)
+{
+	pmic_event_callback_t bat_event_callback;
+	struct mc13892_dev_info *di = platform_get_drvdata(pdev);
+
+	bat_event_callback.func = charger_online_event_callback;
+	bat_event_callback.param = (void *) di;
+	pmic_event_unsubscribe(EVENT_CHGDETI, bat_event_callback);
+
+	cancel_rearming_delayed_workqueue(di->monitor_wqueue,
+					  &di->monitor_work);
+	destroy_workqueue(di->monitor_wqueue);
+	power_supply_unregister(&di->bat);
+	power_supply_unregister(&di->charger);
+
+	kfree(di);
+
+	return 0;
+}
+
+static int pmic_battery_probe(struct platform_device *pdev)
+{
+	int retval = 0;
+	struct mc13892_dev_info *di;
+	pmic_event_callback_t bat_event_callback;
+	pmic_version_t pmic_version;
+
+	/* Only apply battery driver for MC13892 V2.0 due to ENGR108085 */
+	pmic_version = pmic_get_version();
+	if (pmic_version.revision < 20) {
+		pr_debug("Battery driver is only applied for MC13892 V2.0\n");
+		return -1;
+	}
+	if (machine_is_mx51_babbage() || machine_is_mx50_arm2()) {
+		pr_debug("mc13892 charger is not used for this platform\n");
+		return -1;
+	}
+
+	di = kzalloc(sizeof(*di), GFP_KERNEL);
+	if (!di) {
+		retval = -ENOMEM;
+		goto di_alloc_failed;
+	}
+
+	platform_set_drvdata(pdev, di);
+
+	di->dev	= &pdev->dev;
+	di->bat.name	= "mc13892_bat";
+	di->bat.type = POWER_SUPPLY_TYPE_BATTERY;
+	di->bat.properties = mc13892_battery_props;
+	di->bat.num_properties = ARRAY_SIZE(mc13892_battery_props);
+	di->bat.get_property = mc13892_battery_get_property;
+	di->bat.use_for_apm = 1;
+
+	di->battery_status = POWER_SUPPLY_STATUS_UNKNOWN;
+
+	retval = power_supply_register(&pdev->dev, &di->bat);
+	if (retval) {
+		dev_err(di->dev, "failed to register battery\n");
+		goto batt_failed;
+	}
+	di->charger.name	= "mc13892_charger";
+	di->charger.type = POWER_SUPPLY_TYPE_MAINS;
+	di->charger.properties = mc13892_charger_props;
+	di->charger.num_properties = ARRAY_SIZE(mc13892_charger_props);
+	di->charger.get_property = mc13892_charger_get_property;
+	retval = power_supply_register(&pdev->dev, &di->charger);
+	if (retval) {
+		dev_err(di->dev, "failed to register charger\n");
+		goto charger_failed;
+	}
+	INIT_DELAYED_WORK(&di->monitor_work, mc13892_battery_work);
+	di->monitor_wqueue = create_singlethread_workqueue(dev_name(&pdev->dev));
+	if (!di->monitor_wqueue) {
+		retval = -ESRCH;
+		goto workqueue_failed;
+	}
+	queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ * 10);
+
+	bat_event_callback.func = charger_online_event_callback;
+	bat_event_callback.param = (void *) di;
+	pmic_event_subscribe(EVENT_CHGDETI, bat_event_callback);
+
+	pmic_stop_coulomb_counter();
+	pmic_calibrate_coulomb_counter();
+	goto success;
+
+workqueue_failed:
+	power_supply_unregister(&di->charger);
+charger_failed:
+	power_supply_unregister(&di->bat);
+batt_failed:
+	kfree(di);
+di_alloc_failed:
+success:
+	dev_dbg(di->dev, "%s battery probed!\n", __func__);
+	return retval;
+
+
+	return 0;
+}
+
+static struct platform_driver pmic_battery_driver_ldm = {
+	.driver = {
+		   .name = "pmic_battery",
+		   .bus = &platform_bus_type,
+		   },
+	.probe = pmic_battery_probe,
+	.remove = pmic_battery_remove,
+};
+
+static int __init pmic_battery_init(void)
+{
+	pr_debug("PMIC Battery driver loading...\n");
+	return platform_driver_register(&pmic_battery_driver_ldm);
+}
+
+static void __exit pmic_battery_exit(void)
+{
+	platform_driver_unregister(&pmic_battery_driver_ldm);
+	pr_debug("PMIC Battery driver successfully unloaded\n");
+}
+
+module_init(pmic_battery_init);
+module_exit(pmic_battery_exit);
+
+MODULE_DESCRIPTION("pmic_battery driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/pmic/mc13892/pmic_light.c b/drivers/mxc/pmic/mc13892/pmic_light.c
new file mode 100644
index 000000000000..ae02430a1981
--- /dev/null
+++ b/drivers/mxc/pmic/mc13892/pmic_light.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mc13892/pmic_light.c
+ * @brief This is the main file of PMIC(mc13783) Light and Backlight driver.
+ *
+ * @ingroup PMIC_LIGHT
+ */
+
+/*
+ * Includes
+ */
+#define DEBUG
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/pmic_light.h>
+#include <linux/pmic_status.h>
+
+#define BIT_CL_MAIN_LSH		9
+#define BIT_CL_AUX_LSH		21
+#define BIT_CL_KEY_LSH		9
+#define BIT_CL_RED_LSH		9
+#define BIT_CL_GREEN_LSH	21
+#define BIT_CL_BLUE_LSH		9
+
+#define BIT_CL_MAIN_WID		3
+#define BIT_CL_AUX_WID		3
+#define BIT_CL_KEY_WID		3
+#define BIT_CL_RED_WID		3
+#define BIT_CL_GREEN_WID	3
+#define BIT_CL_BLUE_WID		3
+
+#define BIT_DC_MAIN_LSH		3
+#define BIT_DC_AUX_LSH		15
+#define BIT_DC_KEY_LSH		3
+#define BIT_DC_RED_LSH		3
+#define BIT_DC_GREEN_LSH	15
+#define BIT_DC_BLUE_LSH		3
+
+#define BIT_DC_MAIN_WID		6
+#define BIT_DC_AUX_WID		6
+#define BIT_DC_KEY_WID		6
+#define BIT_DC_RED_WID		6
+#define BIT_DC_GREEN_WID	6
+#define BIT_DC_BLUE_WID		6
+
+#define BIT_RP_MAIN_LSH		2
+#define BIT_RP_AUX_LSH		14
+#define BIT_RP_KEY_LSH		2
+#define BIT_RP_RED_LSH		2
+#define BIT_RP_GREEN_LSH	14
+#define BIT_RP_BLUE_LSH		2
+
+#define BIT_RP_MAIN_WID		1
+#define BIT_RP_AUX_WID		1
+#define BIT_RP_KEY_WID		1
+#define BIT_RP_RED_WID		1
+#define BIT_RP_GREEN_WID	1
+#define BIT_RP_BLUE_WID		1
+
+#define BIT_HC_MAIN_LSH		1
+#define BIT_HC_AUX_LSH		13
+#define BIT_HC_KEY_LSH		1
+
+#define BIT_HC_MAIN_WID		1
+#define BIT_HC_AUX_WID		1
+#define BIT_HC_KEY_WID		1
+
+#define BIT_BP_RED_LSH		0
+#define BIT_BP_GREEN_LSH	12
+#define BIT_BP_BLUE_LSH		0
+
+#define BIT_BP_RED_WID		2
+#define BIT_BP_GREEN_WID	2
+#define BIT_BP_BLUE_WID		2
+
+int pmic_light_init_reg(void)
+{
+	CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS));
+	CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS));
+
+	return 0;
+}
+
+static int pmic_light_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+};
+
+static int pmic_light_resume(struct platform_device *pdev)
+{
+	return 0;
+};
+
+PMIC_STATUS mc13892_bklit_set_hi_current(enum lit_channel channel, int mode)
+{
+	unsigned int mask;
+	unsigned int value;
+	int reg;
+
+	switch (channel) {
+	case LIT_MAIN:
+		value = BITFVAL(BIT_HC_MAIN, mode);
+		mask = BITFMASK(BIT_HC_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		value = BITFVAL(BIT_HC_AUX, mode);
+		mask = BITFMASK(BIT_HC_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		value = BITFVAL(BIT_HC_KEY, mode);
+		mask = BITFMASK(BIT_HC_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(reg, value, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_get_hi_current(enum lit_channel channel, int *mode)
+{
+	unsigned int mask;
+	int reg;
+
+	switch (channel) {
+	case LIT_MAIN:
+		mask = BITFMASK(BIT_HC_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		mask = BITFMASK(BIT_HC_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		mask = BITFMASK(BIT_HC_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, mode, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_set_current(enum lit_channel channel,
+				      unsigned char level)
+{
+	unsigned int mask;
+	unsigned int value;
+	int reg;
+
+	if (level > LIT_CURR_HI_42)
+		return PMIC_PARAMETER_ERROR;
+	else if (level >= LIT_CURR_HI_0) {
+		CHECK_ERROR(mc13892_bklit_set_hi_current(channel, 1));
+		level -= LIT_CURR_HI_0;
+	}
+
+	switch (channel) {
+	case LIT_MAIN:
+		value = BITFVAL(BIT_CL_MAIN, level);
+		mask = BITFMASK(BIT_CL_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		value = BITFVAL(BIT_CL_AUX, level);
+		mask = BITFMASK(BIT_CL_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		value = BITFVAL(BIT_CL_KEY, level);
+		mask = BITFMASK(BIT_CL_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		value = BITFVAL(BIT_CL_RED, level);
+		mask = BITFMASK(BIT_CL_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		value = BITFVAL(BIT_CL_GREEN, level);
+		mask = BITFMASK(BIT_CL_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		value = BITFVAL(BIT_CL_BLUE, level);
+		mask = BITFMASK(BIT_CL_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(reg, value, mask));
+
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_get_current(enum lit_channel channel,
+				      unsigned char *level)
+{
+	unsigned int reg_value = 0;
+	unsigned int mask = 0;
+	int reg, mode;
+
+	CHECK_ERROR(mc13892_bklit_get_hi_current(channel, &mode));
+
+	switch (channel) {
+	case LIT_MAIN:
+		mask = BITFMASK(BIT_CL_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		mask = BITFMASK(BIT_CL_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		mask = BITFMASK(BIT_CL_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		mask = BITFMASK(BIT_CL_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		mask = BITFMASK(BIT_CL_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		mask = BITFMASK(BIT_CL_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_value, mask));
+
+	switch (channel) {
+	case LIT_MAIN:
+		*level = BITFEXT(reg_value, BIT_CL_MAIN);
+		break;
+	case LIT_AUX:
+		*level = BITFEXT(reg_value, BIT_CL_AUX);
+		break;
+	case LIT_KEY:
+		*level = BITFEXT(reg_value, BIT_CL_KEY);
+		break;
+	case LIT_RED:
+		*level = BITFEXT(reg_value, BIT_CL_RED);
+		break;
+	case LIT_GREEN:
+		*level = BITFEXT(reg_value, BIT_CL_GREEN);
+		break;
+	case LIT_BLUE:
+		*level = BITFEXT(reg_value, BIT_CL_BLUE);
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	if (mode == 1)
+		*level += LIT_CURR_HI_0;
+
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_set_dutycycle(enum lit_channel channel,
+					unsigned char dc)
+{
+	unsigned int mask;
+	unsigned int value;
+	int reg;
+
+	switch (channel) {
+	case LIT_MAIN:
+		value = BITFVAL(BIT_DC_MAIN, dc);
+		mask = BITFMASK(BIT_DC_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		value = BITFVAL(BIT_DC_AUX, dc);
+		mask = BITFMASK(BIT_DC_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		value = BITFVAL(BIT_DC_KEY, dc);
+		mask = BITFMASK(BIT_DC_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		value = BITFVAL(BIT_DC_RED, dc);
+		mask = BITFMASK(BIT_DC_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		value = BITFVAL(BIT_DC_GREEN, dc);
+		mask = BITFMASK(BIT_DC_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		value = BITFVAL(BIT_DC_BLUE, dc);
+		mask = BITFMASK(BIT_DC_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(reg, value, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_get_dutycycle(enum lit_channel channel,
+					unsigned char *dc)
+{
+	unsigned int mask;
+	int reg;
+	unsigned int reg_value = 0;
+
+	switch (channel) {
+	case LIT_MAIN:
+		mask = BITFMASK(BIT_DC_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		mask = BITFMASK(BIT_DC_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		mask = BITFMASK(BIT_DC_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		mask = BITFMASK(BIT_DC_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		mask = BITFMASK(BIT_DC_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		mask = BITFMASK(BIT_DC_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &reg_value, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_set_ramp(enum lit_channel channel, int flag)
+{
+	unsigned int mask;
+	unsigned int value;
+	int reg;
+
+	switch (channel) {
+	case LIT_MAIN:
+		value = BITFVAL(BIT_RP_MAIN, flag);
+		mask = BITFMASK(BIT_RP_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		value = BITFVAL(BIT_RP_AUX, flag);
+		mask = BITFMASK(BIT_RP_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		value = BITFVAL(BIT_RP_KEY, flag);
+		mask = BITFMASK(BIT_RP_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		value = BITFVAL(BIT_RP_RED, flag);
+		mask = BITFMASK(BIT_RP_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		value = BITFVAL(BIT_RP_GREEN, flag);
+		mask = BITFMASK(BIT_RP_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		value = BITFVAL(BIT_RP_BLUE, flag);
+		mask = BITFMASK(BIT_RP_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(reg, value, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_get_ramp(enum lit_channel channel, int *flag)
+{
+	unsigned int mask;
+	int reg;
+
+	switch (channel) {
+	case LIT_MAIN:
+		mask = BITFMASK(BIT_RP_MAIN);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_AUX:
+		mask = BITFMASK(BIT_RP_AUX);
+		reg = REG_LED_CTL0;
+		break;
+	case LIT_KEY:
+		mask = BITFMASK(BIT_RP_KEY);
+		reg = REG_LED_CTL1;
+		break;
+	case LIT_RED:
+		mask = BITFMASK(BIT_RP_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		mask = BITFMASK(BIT_RP_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		mask = BITFMASK(BIT_RP_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, flag, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period)
+{
+	unsigned int mask;
+	unsigned int value;
+	int reg;
+
+	switch (channel) {
+	case LIT_RED:
+		value = BITFVAL(BIT_BP_RED, period);
+		mask = BITFMASK(BIT_BP_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		value = BITFVAL(BIT_BP_GREEN, period);
+		mask = BITFMASK(BIT_BP_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		value = BITFVAL(BIT_BP_BLUE, period);
+		mask = BITFMASK(BIT_BP_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+	CHECK_ERROR(pmic_write_reg(reg, value, mask));
+	return PMIC_SUCCESS;
+}
+
+PMIC_STATUS mc13892_bklit_get_blink_p(enum lit_channel channel, int *period)
+{
+	unsigned int mask;
+	int reg;
+
+	switch (channel) {
+	case LIT_RED:
+		mask = BITFMASK(BIT_BP_RED);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_GREEN:
+		mask = BITFMASK(BIT_BP_GREEN);
+		reg = REG_LED_CTL2;
+		break;
+	case LIT_BLUE:
+		mask = BITFMASK(BIT_BP_BLUE);
+		reg = REG_LED_CTL3;
+		break;
+	default:
+		return PMIC_PARAMETER_ERROR;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, period, mask));
+	return PMIC_SUCCESS;
+}
+
+EXPORT_SYMBOL(mc13892_bklit_set_current);
+EXPORT_SYMBOL(mc13892_bklit_get_current);
+EXPORT_SYMBOL(mc13892_bklit_set_dutycycle);
+EXPORT_SYMBOL(mc13892_bklit_get_dutycycle);
+EXPORT_SYMBOL(mc13892_bklit_set_ramp);
+EXPORT_SYMBOL(mc13892_bklit_get_ramp);
+EXPORT_SYMBOL(mc13892_bklit_set_blink_p);
+EXPORT_SYMBOL(mc13892_bklit_get_blink_p);
+
+static int pmic_light_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#ifdef DEBUG
+static ssize_t lit_info(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return 0;
+}
+
+enum {
+	SET_CURR = 0,
+	SET_DC,
+	SET_RAMP,
+	SET_BP,
+	SET_CH,
+	LIT_CMD_MAX
+};
+
+static const char *const lit_cmd[LIT_CMD_MAX] = {
+	[SET_CURR] = "cur",
+	[SET_DC] = "dc",
+	[SET_RAMP] = "ra",
+	[SET_BP] = "bp",
+	[SET_CH] = "ch"
+};
+
+static int cmd(unsigned int index, int value)
+{
+	static int ch = LIT_MAIN;
+	int ret = 0;
+
+	switch (index) {
+	case SET_CH:
+		ch = value;
+		break;
+	case SET_CURR:
+		pr_debug("set %d cur %d\n", ch, value);
+		ret = mc13892_bklit_set_current(ch, value);
+		break;
+	case SET_DC:
+		pr_debug("set %d dc %d\n", ch, value);
+		ret = mc13892_bklit_set_dutycycle(ch, value);
+		break;
+	case SET_RAMP:
+		pr_debug("set %d ramp %d\n", ch, value);
+		ret = mc13892_bklit_set_ramp(ch, value);
+		break;
+	case SET_BP:
+		pr_debug("set %d bp %d\n", ch, value);
+		ret = mc13892_bklit_set_blink_p(ch, value);
+		break;
+	default:
+		pr_debug("error command\n");
+		break;
+	}
+
+	if (ret == PMIC_SUCCESS)
+		pr_debug("command exec successfully!\n");
+
+	return 0;
+}
+
+static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr,
+		       const char *buf, size_t count)
+{
+	int state = 0;
+	const char *const *s;
+	char *p, *q;
+	int error;
+	int len, value = 0;
+
+	pr_debug("lit_ctl\n");
+
+	q = NULL;
+	q = memchr(buf, ' ', count);
+
+	if (q != NULL) {
+		len = q - buf;
+		q += 1;
+		value = simple_strtoul(q, NULL, 10);
+	} else {
+		p = memchr(buf, '\n', count);
+		len = p ? p - buf : count;
+	}
+
+	for (s = &lit_cmd[state]; state < LIT_CMD_MAX; s++, state++) {
+		if (*s && !strncmp(buf, *s, len))
+			break;
+	}
+	if (state < LIT_CMD_MAX && *s)
+		error = cmd(state, value);
+	else
+		error = -EINVAL;
+
+	return count;
+}
+
+#else
+static ssize_t lit_info(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	return 0;
+}
+
+static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr,
+		       const char *buf, size_t count)
+{
+	return count;
+}
+
+#endif
+
+static DEVICE_ATTR(lit, 0644, lit_info, lit_ctl);
+
+static int pmic_light_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+
+	pr_debug("PMIC ADC start probe\n");
+	ret = device_create_file(&(pdev->dev), &dev_attr_lit);
+	if (ret) {
+		pr_debug("Can't create device file!\n");
+		return -ENODEV;
+	}
+
+	pmic_light_init_reg();
+
+	pr_debug("PMIC Light successfully loaded\n");
+	return 0;
+}
+
+static struct platform_driver pmic_light_driver_ldm = {
+	.driver = {
+		   .name = "pmic_light",
+		   },
+	.suspend = pmic_light_suspend,
+	.resume = pmic_light_resume,
+	.probe = pmic_light_probe,
+	.remove = pmic_light_remove,
+};
+
+/*
+ * Initialization and Exit
+ */
+
+static int __init pmic_light_init(void)
+{
+	pr_debug("PMIC Light driver loading...\n");
+	return platform_driver_register(&pmic_light_driver_ldm);
+}
+static void __exit pmic_light_exit(void)
+{
+	platform_driver_unregister(&pmic_light_driver_ldm);
+	pr_debug("PMIC Light driver successfully unloaded\n");
+}
+
+/*
+ * Module entry points
+ */
+
+subsys_initcall(pmic_light_init);
+module_exit(pmic_light_exit);
+
+MODULE_DESCRIPTION("PMIC_LIGHT");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/security/Kconfig b/drivers/mxc/security/Kconfig
new file mode 100644
index 000000000000..875848b2c69c
--- /dev/null
+++ b/drivers/mxc/security/Kconfig
@@ -0,0 +1,64 @@
+menu "MXC Security Drivers"
+
+config MXC_SECURITY_SCC
+	tristate "MXC SCC Driver"
+	default n
+	---help---
+	  This module contains the core API's for accessing the SCC module.
+	  If you are unsure about this, say N here.
+
+config MXC_SECURITY_SCC2
+        tristate "MXC SCC2 Driver"
+        depends on ARCH_MX37 || ARCH_MX5
+        default n
+        ---help---
+          This module contains the core API's for accessing the SCC2 module.
+          If you are unsure about this, say N here.
+
+config SCC_DEBUG
+        bool "MXC SCC Module debugging"
+        depends on MXC_SECURITY_SCC || MXC_SECURITY_SCC2
+        ---help---
+        This is an option for use by developers; most people should
+        say N here.  This enables SCC module debugging.
+
+config MXC_SECURITY_RNG
+	tristate "MXC RNG Driver"
+	depends on ARCH_MXC
+	depends on !ARCH_MXC91321
+	depends on !ARCH_MX27
+	default n
+	select MXC_SECURITY_CORE
+	---help---
+	  This module contains the core API's for accessing the RNG module.
+	  If you are unsure about this, say N here.
+
+config MXC_RNG_TEST_DRIVER
+	bool "MXC RNG debug register"
+	depends on MXC_SECURITY_RNG
+	default n
+	---help---
+	  This option enables the RNG kcore driver to provide peek-poke facility
+	  into the RNG device registers. Enable this, only for development and
+	  testing purposes.
+config MXC_RNG_DEBUG
+        bool "MXC RNG Module Dubugging"
+        depends on MXC_SECURITY_RNG
+        default n
+        ---help---
+         This is an option for use by developers; most people should
+         say N here. This enables RNG module debugging.
+
+config MXC_DRYICE
+        tristate "MXC DryIce Driver"
+        depends on ARCH_MX25
+        default n
+        ---help---
+          This module contains the core API's for accessing the DryIce module.
+          If you are unsure about this, say N here.
+
+if (ARCH_MX37 || ARCH_MX5 || ARCH_MX27)
+source "drivers/mxc/security/sahara2/Kconfig"
+endif
+
+endmenu
diff --git a/drivers/mxc/security/Makefile b/drivers/mxc/security/Makefile
new file mode 100644
index 000000000000..f643a09a423d
--- /dev/null
+++ b/drivers/mxc/security/Makefile
@@ -0,0 +1,11 @@
+# Makefile for the Linux MXC Security API
+ifeq ($( SCC_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
+EXTRA_CFLAGS += -DMXC -DLINUX_KERNEL
+
+obj-$(CONFIG_MXC_SECURITY_SCC2) += scc2_driver.o
+obj-$(CONFIG_MXC_SECURITY_SCC) += mxc_scc.o
+obj-$(CONFIG_MXC_SECURITY_RNG) += rng/
+obj-$(CONFIG_MXC_SAHARA) += sahara2/
+obj-$(CONFIG_MXC_DRYICE) += dryice.o
diff --git a/drivers/mxc/security/dryice-regs.h b/drivers/mxc/security/dryice-regs.h
new file mode 100644
index 000000000000..b8d3858bdb7d
--- /dev/null
+++ b/drivers/mxc/security/dryice-regs.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+#ifndef __DRYICE_REGS_H__
+#define __DRYICE_REGS_H__
+
+/***********************************************************************
+ * DryIce Register Definitions
+ ***********************************************************************/
+
+/* DryIce Time Counter MSB Reg */
+#define DTCMR   0x00
+
+/* DryIce Time Counter LSB Reg */
+#define DTCLR   0x04
+
+/* DryIce Clock Alarm MSB Reg */
+#define DCAMR   0x08
+
+/* DryIce Clock Alarm LSB Reg */
+#define DCALR   0x0c
+
+/* DryIce Control Reg */
+#define DCR     0x10
+#define DCR_TDCHL   (1 << 30)  /* Tamper Detect Config Hard Lock */
+#define DCR_TDCSL   (1 << 29)  /* Tamper Detect COnfig Soft Lock */
+#define DCR_KSHL    (1 << 28)  /* Key Select Hard Lock */
+#define DCR_KSSL    (1 << 27)  /* Key Select Soft Lock */
+#define DCR_RKHL    (1 << 26)  /* Random Key Hard Lock */
+#define DCR_RKSL    (1 << 25)  /* Random Key Soft Lock */
+#define DCR_PKRHL   (1 << 24)  /* Programmed Key Read Hard Lock */
+#define DCR_PKRSL   (1 << 23)  /* Programmed Key Read Soft Lock */
+#define DCR_PKWHL   (1 << 22)  /* Programmed Key Write Hard Lock */
+#define DCR_PKWSL   (1 << 21)  /* Programmed Key Write Soft Lock */
+#define DCR_MCHL    (1 << 20)  /* Monotonic Counter Hard Lock */
+#define DCR_MCSL    (1 << 19)  /* Monotonic Counter Soft Lock */
+#define DCR_TCHL    (1 << 18)  /* Time Counter Hard Lock */
+#define DCR_TCSL    (1 << 17)  /* Time Counter Soft Lock */
+#define DCR_FSHL    (1 << 16)  /* Failure State Hard Lock */
+#define DCR_NSA     (1 << 15)  /* Non-Secure Access */
+#define DCR_OSCB    (1 << 14)  /* Oscillator Bypass */
+#define DCR_APE     (1 << 4)   /* Alarm Pin Enable */
+#define DCR_TCE     (1 << 3)   /* Time Counter Enable */
+#define DCR_MCE     (1 << 2)   /* Monotonic Counter Enable */
+#define DCR_SWR     (1 << 0)   /* Software Reset (w/o) */
+
+/* DryIce Status Reg */
+#define DSR     0x14
+#define DSR_WTD     (1 << 23)  /* Wire-mesh Tampering Detected */
+#define DSR_ETBD    (1 << 22)  /* External Tampering B Detected */
+#define DSR_ETAD    (1 << 21)  /* External Tampering A Detected */
+#define DSR_EBD     (1 << 20)  /* External Boot Detected */
+#define DSR_SAD     (1 << 19)  /* Security Alarm Detected */
+#define DSR_TTD     (1 << 18)  /* Temperature Tampering Detected */
+#define DSR_CTD     (1 << 17)  /* Clock Tampering Detected */
+#define DSR_VTD     (1 << 16)  /* Voltage Tampering Detected */
+#define DSR_KBF     (1 << 11)  /* Key Busy Flag */
+#define DSR_WBF     (1 << 10)  /* Write Busy Flag */
+#define DSR_WNF     (1 << 9)   /* Write Next Flag */
+#define DSR_WCF     (1 << 8)   /* Write Complete Flag */
+#define DSR_WEF     (1 << 7)   /* Write Error Flag */
+#define DSR_RKE     (1 << 6)   /* Random Key Error */
+#define DSR_RKV     (1 << 5)   /* Random Key Valid */
+#define DSR_CAF     (1 << 4)   /* Clock Alarm Flag */
+#define DSR_MCO     (1 << 3)   /* Monotonic Counter Overflow */
+#define DSR_TCO     (1 << 2)   /* Time Counter Overflow */
+#define DSR_NVF     (1 << 1)   /* Non-Valid Flag */
+#define DSR_SVF     (1 << 0)   /* Security Violation Flag */
+
+#define DSR_TAMPER_BITS (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD | \
+			 DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO)
+
+/* ensure that external tamper defs match register bits */
+#if DSR_WTD != DI_TAMPER_EVENT_WTD
+#error "Mismatch between DSR_WTD and DI_TAMPER_EVENT_WTD"
+#endif
+#if DSR_ETBD != DI_TAMPER_EVENT_ETBD
+#error "Mismatch between DSR_ETBD and DI_TAMPER_EVENT_ETBD"
+#endif
+#if DSR_ETAD != DI_TAMPER_EVENT_ETAD
+#error "Mismatch between DSR_ETAD and DI_TAMPER_EVENT_ETAD"
+#endif
+#if DSR_EBD != DI_TAMPER_EVENT_EBD
+#error "Mismatch between DSR_EBD and DI_TAMPER_EVENT_EBD"
+#endif
+#if DSR_SAD != DI_TAMPER_EVENT_SAD
+#error "Mismatch between DSR_SAD and DI_TAMPER_EVENT_SAD"
+#endif
+#if DSR_TTD != DI_TAMPER_EVENT_TTD
+#error "Mismatch between DSR_TTD and DI_TAMPER_EVENT_TTD"
+#endif
+#if DSR_CTD != DI_TAMPER_EVENT_CTD
+#error "Mismatch between DSR_CTD and DI_TAMPER_EVENT_CTD"
+#endif
+#if DSR_VTD != DI_TAMPER_EVENT_VTD
+#error "Mismatch between DSR_VTD and DI_TAMPER_EVENT_VTD"
+#endif
+#if DSR_MCO != DI_TAMPER_EVENT_MCO
+#error "Mismatch between DSR_MCO and DI_TAMPER_EVENT_MCO"
+#endif
+#if DSR_TCO != DI_TAMPER_EVENT_TCO
+#error "Mismatch between DSR_TCO and DI_TAMPER_EVENT_TCO"
+#endif
+
+/* DryIce Interrupt Enable Reg */
+#define DIER    0x18
+#define DIER_WNIE   (1 << 9)   /* Write Next Interrupt Enable */
+#define DIER_WCIE   (1 << 8)   /* Write Complete Interrupt Enable */
+#define DIER_WEIE   (1 << 7)   /* Write Error Interrupt Enable */
+#define DIER_RKIE   (1 << 5)   /* Random Key Interrupt Enable */
+#define DIER_CAIE   (1 << 4)   /* Clock Alarm Interrupt Enable */
+#define DIER_MOIE   (1 << 3)   /* Monotonic Overflow Interrupt En */
+#define DIER_TOIE   (1 << 2)   /* Time Overflow Interrupt Enable */
+#define DIER_SVIE   (1 << 0)   /* Security Violation Interrupt En */
+
+/* DryIce Monotonic Counter Reg */
+#define DMCR    0x1c
+
+/* DryIce Key Select Reg */
+#define DKSR    0x20
+#define DKSR_IIM_KEY           0x0
+#define DKSR_PROG_KEY          0x4
+#define DKSR_RAND_KEY          0x5
+#define DKSR_PROG_XOR_IIM_KEY  0x6
+#define DKSR_RAND_XOR_IIM_KEY  0x7
+
+/* DryIce Key Control Reg */
+#define DKCR    0x24
+#define DKCR_LRK    (1 << 0)   /* Load Random Key */
+
+/* DryIce Tamper Configuration Reg */
+#define DTCR    0x28
+#define DTCR_ETGFB_SHIFT  27   /* Ext Tamper Glitch Filter B */
+#define DTCR_ETGFB_MASK   0xf8000000
+#define DTCR_ETGFA_SHIFT  22   /* Ext Tamper Glitch Filter A */
+#define DTCR_ETGFA_MASK   0x07c00000
+#define DTCR_WTGF_SHIFT   17   /* Wire-mesh Tamper Glitch Filter */
+#define DTCR_WTGF_MASK    0x003e0000
+#define DTCR_WGFE   (1 << 16)  /* Wire-mesh Glitch Filter Enable */
+#define DTCR_SAOE   (1 << 15)  /* Security Alarm Output Enable */
+#define DTCR_MOE    (1 << 9)   /* Monotonic Overflow Enable */
+#define DTCR_TOE    (1 << 8)   /* Time Overflow Enable */
+#define DTCR_WTE    (1 << 7)   /* Wire-mesh Tampering Enable */
+#define DTCR_ETBE   (1 << 6)   /* External Tampering B Enable */
+#define DTCR_ETAE   (1 << 5)   /* External Tampering A Enable */
+#define DTCR_EBE    (1 << 4)   /* External Boot Enable */
+#define DTCR_SAIE   (1 << 3)   /* Security Alarm Input Enable */
+#define DTCR_TTE    (1 << 2)   /* Temperature Tamper Enable */
+#define DTCR_CTE    (1 << 1)   /* Clock Tamper Enable */
+#define DTCR_VTE    (1 << 0)   /* Voltage Tamper Enable */
+
+/* DryIce Analog Configuration Reg */
+#define DACR    0x2c
+#define DACR_VRC_SHIFT    6    /* Voltage Reference Configuration */
+#define DACR_VRC_MASK     0x000001c0
+#define DACR_HTDC_SHIFT   3    /* High Temperature Detect Configuration */
+#define DACR_HTDC_MASK    0x00000038
+#define DACR_LTDC_SHIFT   0    /* Low Temperature Detect Configuration */
+#define DACR_LTDC_MASK    0x00000007
+
+/* DryIce General Purpose Reg */
+#define DGPR    0x3c
+
+/* DryIce Programmed Key0-7 Regs */
+#define DPKR0   0x40
+#define DPKR1   0x44
+#define DPKR2   0x48
+#define DPKR3   0x4c
+#define DPKR4   0x50
+#define DPKR5   0x54
+#define DPKR6   0x58
+#define DPKR7   0x5c
+
+/* DryIce Random Key0-7 Regs */
+#define DRKR0   0x60
+#define DRKR1   0x64
+#define DRKR2   0x68
+#define DRKR3   0x6c
+#define DRKR4   0x70
+#define DRKR5   0x74
+#define DRKR6   0x78
+#define DRKR7   0x7c
+
+#define DI_ADDRESS_RANGE  (DRKR7 + 4)
+
+/*
+ * this doesn't really belong here but the
+ * portability layer doesn't include it
+ */
+#ifdef LINUX_KERNEL
+#define EXTERN_SYMBOL(symbol)  EXPORT_SYMBOL(symbol)
+#else
+#define EXTERN_SYMBOL(symbol)  do {} while (0)
+#endif
+
+#endif /* __DRYICE_REGS_H__ */
diff --git a/drivers/mxc/security/dryice.c b/drivers/mxc/security/dryice.c
new file mode 100644
index 000000000000..f7cefb6ae599
--- /dev/null
+++ b/drivers/mxc/security/dryice.c
@@ -0,0 +1,1123 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+#undef DI_DEBUG        /* enable debug messages */
+#undef DI_DEBUG_REGIO  /* show register read/write */
+#undef DI_TESTING      /* include test code */
+
+#ifdef DI_DEBUG
+#define di_debug(fmt, arg...) os_printk(KERN_INFO fmt, ##arg)
+#else
+#define di_debug(fmt, arg...) do {} while (0)
+#endif
+
+#define di_info(fmt, arg...) os_printk(KERN_INFO fmt, ##arg)
+#define di_warn(fmt, arg...) os_printk(KERN_WARNING fmt, ##arg)
+
+#include "sahara2/include/portable_os.h"
+#include "dryice.h"
+#include "dryice-regs.h"
+
+/* mask of the lock-related function flags */
+#define DI_FUNC_LOCK_FLAGS  (DI_FUNC_FLAG_READ_LOCK  | \
+			     DI_FUNC_FLAG_WRITE_LOCK | \
+			     DI_FUNC_FLAG_HARD_LOCK)
+
+/*
+ * dryice hardware states
+ */
+enum di_states {
+	DI_STATE_VALID = 0,
+	DI_STATE_NON_VALID,
+	DI_STATE_FAILURE,
+};
+
+/*
+ * todo list actions
+ */
+enum todo_actions {
+	TODO_ACT_WRITE_VAL,
+	TODO_ACT_WRITE_PTR,
+	TODO_ACT_WRITE_PTR32,
+	TODO_ACT_ASSIGN,
+	TODO_ACT_WAIT_RKG,
+};
+
+/*
+ * todo list status
+ */
+enum todo_status {
+	TODO_ST_LOADING,
+	TODO_ST_READY,
+	TODO_ST_PEND_WCF,
+	TODO_ST_PEND_RKG,
+	TODO_ST_DONE,
+};
+
+OS_DEV_INIT_DCL(dryice_init)
+OS_DEV_SHUTDOWN_DCL(dryice_exit)
+OS_DEV_ISR_DCL(dryice_norm_irq)
+OS_WAIT_OBJECT(done_queue);
+OS_WAIT_OBJECT(exit_queue);
+
+struct dryice_data {
+	int busy;               /* enforce exclusive access */
+	os_lock_t busy_lock;
+	int exit_flag;          /* don't start new operations */
+
+	uint32_t baseaddr;      /* physical base address */
+	void *ioaddr;           /* virtual base address */
+
+	/* interrupt handling */
+	struct irq_struct {
+		os_interrupt_id_t irq;
+		int set;
+	} irq_norm, irq_sec;
+
+	struct clk *clk;        /* clock control */
+
+	int key_programmed;     /* key has been programmed */
+	int key_selected;       /* key has been selected */
+
+	/* callback function and cookie */
+	void (*cb_func)(di_return_t rc, unsigned long cookie);
+	unsigned long cb_cookie;
+} *di = NULL;
+
+#define TODO_LIST_LEN	12
+static struct {
+	struct td {
+		enum todo_actions action;
+		uint32_t src;
+		uint32_t dst;
+		int num;
+	} list[TODO_LIST_LEN];
+	int cur;                /* current todo pointer */
+	int num;		/* number of todo's on the list */
+	int async;              /* non-zero if list is async */
+	int status;             /* current status of the list */
+	di_return_t rc;         /* return code generated by the list */
+} todo;
+
+/*
+ * dryice register read/write functions
+ */
+#ifdef DI_DEBUG_REGIO
+static uint32_t di_read(int reg)
+{
+	uint32_t val = os_read32(di->ioaddr + (reg));
+	di_info("di_read(0x%02x) = 0x%08x\n", reg, val);
+
+	return val;
+}
+
+static void di_write(uint32_t val, int reg)
+{
+	di_info("dryice_write_reg(0x%08x, 0x%02x)\n", val, reg);
+	os_write32(di->ioaddr + (reg), val);
+}
+#else
+#define di_read(reg)        os_read32(di->ioaddr + (reg))
+#define di_write(val, reg)  os_write32(di->ioaddr + (reg), val);
+#endif
+
+/*
+ * set the dryice busy flag atomically, allowing
+ * for case where the driver is trying to exit.
+ */
+static int di_busy_set(void)
+{
+	os_lock_context_t context;
+	int rc = 0;
+
+	os_lock_save_context(di->busy_lock, context);
+	if (di->exit_flag || di->busy)
+		rc = 1;
+	else
+		di->busy = 1;
+	os_unlock_restore_context(di->busy_lock, context);
+
+	return rc;
+}
+
+/*
+ * clear the dryice busy flag
+ */
+static inline void di_busy_clear(void)
+{
+	/* don't acquire the lock because the race is benign */
+	di->busy = 0;
+
+	if (di->exit_flag)
+		os_wake_sleepers(exit_queue);
+}
+
+/*
+ * return the current state of dryice
+ * (valid, non-valid, or failure)
+ */
+static enum di_states di_state(void)
+{
+	enum di_states state = DI_STATE_VALID;
+	uint32_t dsr = di_read(DSR);
+
+	if (dsr & DSR_NVF)
+		state = DI_STATE_NON_VALID;
+	else if (dsr & DSR_SVF)
+		state = DI_STATE_FAILURE;
+
+	return state;
+}
+
+#define DI_WRITE_LOOP_CNT 0x1000
+/*
+ * the write-error flag is something that shouldn't get set
+ * during normal operation.  if it's set something is terribly
+ * wrong.  the best we can do is try to clear the bit and hope
+ * that dryice will recover.  this situation is similar to an
+ * unexpected bus fault in terms of severity.
+ */
+static void try_to_clear_wef(void)
+{
+	int cnt;
+
+	while (1) {
+		di_write(DSR_WEF, DSR);
+		for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) {
+			if ((di_read(DSR) & DSR_WEF) == 0)
+				break;
+		}
+		di_warn("WARNING: DryIce cannot clear DSR_WEF "
+			"(Write Error Flag)!\n");
+	}
+}
+
+/*
+ * write a dryice register and loop, waiting for it
+ * to complete. use only during driver initialization.
+ * returns 0 on success or 1 on write failure.
+ */
+static int di_write_loop(uint32_t val, int reg)
+{
+	int rc = 0;
+	int cnt;
+
+	di_debug("FUNC: %s\n", __func__);
+	di_write(val, reg);
+
+	for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) {
+		uint32_t dsr = di_read(DSR);
+		if (dsr & DSR_WEF) {
+			try_to_clear_wef();
+			rc = 1;
+		}
+		if (dsr & DSR_WCF)
+			break;
+	}
+	di_debug("wait_write_loop looped %d times\n", cnt);
+	if (cnt == DI_WRITE_LOOP_CNT)
+		rc = 1;
+
+	if (rc)
+		di_warn("DryIce wait_write_done: WRITE ERROR!\n");
+	return rc;
+}
+
+/*
+ * initialize the todo list. must be called
+ * before adding items to the list.
+ */
+static void todo_init(int async_flag)
+{
+	di_debug("FUNC: %s\n", __func__);
+	todo.cur = 0;
+	todo.num = 0;
+	todo.async = async_flag;
+	todo.rc = 0;
+	todo.status = TODO_ST_LOADING;
+}
+
+/*
+ * perform the current action on the todo list
+ */
+#define TC  todo.list[todo.cur]
+void todo_cur(void)
+{
+	di_debug("FUNC: %s[%d]\n", __func__, todo.cur);
+	switch (TC.action) {
+	case TODO_ACT_WRITE_VAL:
+		di_debug("  TODO_ACT_WRITE_VAL\n");
+		/* enable the write-completion interrupt */
+		todo.status = TODO_ST_PEND_WCF;
+		di_write(di_read(DIER) | DIER_WCIE, DIER);
+
+		di_write(TC.src, TC.dst);
+		break;
+
+	case TODO_ACT_WRITE_PTR32:
+		di_debug("  TODO_ACT_WRITE_PTR32\n");
+		/* enable the write-completion interrupt */
+		todo.status = TODO_ST_PEND_WCF;
+		di_write(di_read(DIER) | DIER_WCIE, DIER);
+
+		di_write(*(uint32_t *)TC.src, TC.dst);
+		break;
+
+	case TODO_ACT_WRITE_PTR:
+		{
+			uint8_t *p = (uint8_t *)TC.src;
+			uint32_t val = 0;
+			int num = TC.num;
+
+			di_debug("  TODO_ACT_WRITE_PTR\n");
+			while (num--)
+				val = (val << 8) | *p++;
+
+			/* enable the write-completion interrupt */
+			todo.status = TODO_ST_PEND_WCF;
+			di_write(di_read(DIER) | DIER_WCIE, DIER);
+
+			di_write(val, TC.dst);
+		}
+		break;
+
+	case TODO_ACT_ASSIGN:
+		di_debug("  TODO_ACT_ASSIGN\n");
+		switch (TC.num) {
+		case 1:
+			*(uint8_t *)TC.dst = TC.src;
+			break;
+		case 2:
+			*(uint16_t *)TC.dst = TC.src;
+			break;
+		case 4:
+			*(uint32_t *)TC.dst = TC.src;
+			break;
+		default:
+			di_warn("Unexpected size in TODO_ACT_ASSIGN\n");
+			break;
+		}
+		break;
+
+	case TODO_ACT_WAIT_RKG:
+		di_debug("  TODO_ACT_WAIT_RKG\n");
+		/* enable the random-key interrupt */
+		todo.status = TODO_ST_PEND_RKG;
+		di_write(di_read(DIER) | DIER_RKIE, DIER);
+		break;
+
+	default:
+		di_debug("  TODO_ACT_NOOP\n");
+		break;
+	}
+}
+
+/*
+ * called when done with the todo list.
+ * if async, it does the callback.
+ * if blocking, it wakes up the caller.
+ */
+static void todo_done(di_return_t rc)
+{
+	todo.rc = rc;
+	todo.status = TODO_ST_DONE;
+	if (todo.async) {
+		di_busy_clear();
+		if (di->cb_func)
+			di->cb_func(rc, di->cb_cookie);
+	} else
+		os_wake_sleepers(done_queue);
+}
+
+/*
+ * performs the actions sequentially from the todo list
+ * until it encounters an item that isn't ready.
+ */
+static void todo_run(void)
+{
+	di_debug("FUNC: %s\n", __func__);
+	while (todo.status == TODO_ST_READY) {
+		if (todo.cur == todo.num) {
+			todo_done(0);
+			break;
+		}
+		todo_cur();
+		if (todo.status != TODO_ST_READY)
+			break;
+		todo.cur++;
+	}
+}
+
+/*
+ * kick off the todo list by making it ready
+ */
+static void todo_start(void)
+{
+	di_debug("FUNC: %s\n", __func__);
+	todo.status = TODO_ST_READY;
+	todo_run();
+}
+
+/*
+ * blocking callers sleep here until the todo list is done
+ */
+static int todo_wait_done(void)
+{
+	di_debug("FUNC: %s\n", __func__);
+	os_sleep(done_queue, todo.status == TODO_ST_DONE, 0);
+
+	return todo.rc;
+}
+
+/*
+ * add a dryice register write to the todo list.
+ * the value to be written is supplied.
+ */
+#define todo_write_val(val, reg) \
+		todo_add(TODO_ACT_WRITE_VAL, val, reg, 0)
+
+/*
+ * add a dryice register write to the todo list.
+ * "size" bytes pointed to by addr will be written.
+ */
+#define todo_write_ptr(addr, reg, size) \
+		todo_add(TODO_ACT_WRITE_PTR, (uint32_t)addr, reg, size)
+
+/*
+ * add a dryice register write to the todo list.
+ * the word pointed to by addr will be written.
+ */
+#define todo_write_ptr32(addr, reg) \
+		todo_add(TODO_ACT_WRITE_PTR32, (uint32_t)addr, reg, 0)
+
+/*
+ * add a dryice memory write to the todo list.
+ * object can only have a size of 1, 2, or 4 bytes.
+ */
+#define todo_assign(var, val) \
+		todo_add(TODO_ACT_ASSIGN, val, (uint32_t)&(var), sizeof(var))
+
+#define todo_wait_rkg() \
+		todo_add(TODO_ACT_WAIT_RKG, 0, 0, 0)
+
+static void todo_add(int action, uint32_t src, uint32_t dst, int num)
+{
+	struct td *p = &todo.list[todo.num];
+
+	di_debug("FUNC: %s\n", __func__);
+	if (todo.num == TODO_LIST_LEN) {
+		di_warn("WARNING: DryIce todo-list overflow!\n");
+		return;
+	}
+	p->action = action;
+	p->src = src;
+	p->dst = dst;
+	p->num = num;
+	todo.num++;
+}
+
+#if defined(DI_DEBUG) || defined(DI_TESTING)
+/*
+ * print out the contents of the dryice status register
+ * with all the bits decoded
+ */
+static void show_dsr(const char *heading)
+{
+	uint32_t dsr = di_read(DSR);
+
+	di_info("%s\n", heading);
+	if (dsr & DSR_TAMPER_BITS) {
+		if (dsr & DSR_WTD)
+			di_info("Wire-mesh Tampering Detected\n");
+		if (dsr & DSR_ETBD)
+			di_info("External Tampering B Detected\n");
+		if (dsr & DSR_ETAD)
+			di_info("External Tampering A Detected\n");
+		if (dsr & DSR_EBD)
+			di_info("External Boot Detected\n");
+		if (dsr & DSR_SAD)
+			di_info("Security Alarm Detected\n");
+		if (dsr & DSR_TTD)
+			di_info("Temperature Tampering Detected\n");
+		if (dsr & DSR_CTD)
+			di_info("Clock Tampering Detected\n");
+		if (dsr & DSR_VTD)
+			di_info("Voltage Tampering Detected\n");
+		if (dsr & DSR_MCO)
+			di_info("Monotonic Counter Overflow\n");
+		if (dsr & DSR_TCO)
+			di_info("Time Counter Overflow\n");
+	} else
+		di_info("No Tamper Events Detected\n");
+
+	di_info("%d Key Busy Flag\n",           !!(dsr & DSR_KBF));
+	di_info("%d Write Busy Flag\n",         !!(dsr & DSR_WBF));
+	di_info("%d Write Next Flag\n",         !!(dsr & DSR_WNF));
+	di_info("%d Write Complete Flag\n",     !!(dsr & DSR_WCF));
+	di_info("%d Write Error Flag\n",        !!(dsr & DSR_WEF));
+	di_info("%d Random Key Error\n",        !!(dsr & DSR_RKE));
+	di_info("%d Random Key Valid\n",        !!(dsr & DSR_RKV));
+	di_info("%d Clock Alarm Flag\n",        !!(dsr & DSR_CAF));
+	di_info("%d Non-Valid Flag\n",          !!(dsr & DSR_NVF));
+	di_info("%d Security Violation Flag\n", !!(dsr & DSR_SVF));
+}
+
+/*
+ * print out a key in hex
+ */
+static void print_key(const char *tag, uint8_t *key, int bits)
+{
+	int bytes = (bits + 7) / 8;
+
+	di_info("%s", tag);
+	while (bytes--)
+		os_printk("%02x", *key++);
+	os_printk("\n");
+}
+#endif  /* defined(DI_DEBUG) || defined(DI_TESTING) */
+
+/*
+ * dryice normal interrupt service routine
+ */
+OS_DEV_ISR(dryice_norm_irq)
+{
+	/* save dryice status register */
+	uint32_t dsr = di_read(DSR);
+
+	if (dsr & DSR_WCF) {
+		/* disable the write-completion interrupt */
+		di_write(di_read(DIER) & ~DIER_WCIE, DIER);
+
+		if (todo.status == TODO_ST_PEND_WCF) {
+			if (dsr & DSR_WEF) {
+				try_to_clear_wef();
+				todo_done(DI_ERR_WRITE);
+			} else {
+				todo.cur++;
+				todo.status = TODO_ST_READY;
+				todo_run();
+			}
+		}
+	} else if (dsr & (DSR_RKV | DSR_RKE)) {
+		/* disable the random-key-gen interrupt */
+		di_write(di_read(DIER) & ~DIER_RKIE, DIER);
+
+		if (todo.status == TODO_ST_PEND_RKG) {
+			if (dsr & DSR_RKE)
+				todo_done(DI_ERR_FAIL);
+			else {
+				todo.cur++;
+				todo.status = TODO_ST_READY;
+				todo_run();
+			}
+		}
+	}
+
+	os_dev_isr_return(1);
+}
+
+/* write loop with error handling -- for init only */
+#define di_write_loop_goto(val, reg, rc, label) \
+		do {if (di_write_loop(val, reg)) \
+		{rc = OS_ERROR_FAIL_S; goto label; } } while (0)
+
+/*
+ * dryice driver initialization
+ */
+OS_DEV_INIT(dryice_init)
+{
+	di_return_t rc = 0;
+
+	di_info("MXC DryIce driver\n");
+
+	/* allocate memory */
+	di = os_alloc_memory(sizeof(*di), GFP_KERNEL);
+	if (di == NULL) {
+		rc = OS_ERROR_NO_MEMORY_S;
+		goto err_alloc;
+	}
+	memset(di, 0, sizeof(*di));
+	di->baseaddr = DRYICE_BASE_ADDR;
+	di->irq_norm.irq = MXC_INT_DRYICE_NORM;
+	di->irq_sec.irq = MXC_INT_DRYICE_SEC;
+
+	/* map i/o registers */
+	di->ioaddr = os_map_device(di->baseaddr, DI_ADDRESS_RANGE);
+	if (di->ioaddr == NULL) {
+		rc = OS_ERROR_FAIL_S;
+		goto err_iomap;
+	}
+
+	/* allocate locks */
+	di->busy_lock = os_lock_alloc_init();
+	if (di->busy_lock == NULL) {
+		rc = OS_ERROR_NO_MEMORY_S;
+		goto err_locks;
+	}
+
+	/* enable clocks (is there a portable way to do this?) */
+	di->clk = clk_get(NULL, "dryice_clk");
+	clk_enable(di->clk);
+
+	/* register for interrupts */
+	/* os_register_interrupt() dosen't support an option to make the
+	    interrupt as shared. Replaced it with request_irq().*/
+	rc = request_irq(di->irq_norm.irq, dryice_norm_irq, IRQF_SHARED,
+				"dry_ice", di);
+	if (rc)
+		goto err_irqs;
+	else
+		di->irq_norm.set = 1;
+
+	/*
+	 * DRYICE HARDWARE INIT
+	 */
+
+#ifdef DI_DEBUG
+	show_dsr("DSR Pre-Initialization State");
+#endif
+
+	if (di_state() == DI_STATE_NON_VALID) {
+		uint32_t dsr = di_read(DSR);
+
+		di_debug("initializing from non-valid state\n");
+
+		/* clear security violation flag */
+		if (dsr & DSR_SVF)
+			di_write_loop_goto(DSR_SVF, DSR, rc, err_write);
+
+		/* clear tamper detect flags */
+		if (dsr & DSR_TAMPER_BITS)
+			di_write_loop_goto(DSR_TAMPER_BITS, DSR, rc, err_write);
+
+		/* initialize timers */
+		di_write_loop_goto(0, DTCLR, rc, err_write);
+		di_write_loop_goto(0, DTCMR, rc, err_write);
+		di_write_loop_goto(0, DMCR, rc, err_write);
+
+		/* clear non-valid flag */
+		di_write_loop_goto(DSR_NVF, DSR, rc, err_write);
+	}
+
+	/* set tamper events we are interested in watching */
+	di_write_loop_goto(DTCR_WTE | DTCR_ETBE | DTCR_ETAE, DTCR, rc,
+			   err_write);
+#ifdef DI_DEBUG
+	show_dsr("DSR Post-Initialization State");
+#endif
+	os_dev_init_return(OS_ERROR_OK_S);
+
+err_write:
+	/* unregister interrupts */
+	if (di->irq_norm.set)
+		os_deregister_interrupt(di->irq_norm.irq);
+	if (di->irq_sec.set)
+		os_deregister_interrupt(di->irq_sec.irq);
+
+	/* turn off clocks (is there a portable way to do this?) */
+	clk_disable(di->clk);
+	clk_put(di->clk);
+
+err_irqs:
+	/* unallocate locks */
+	os_lock_deallocate(di->busy_lock);
+
+err_locks:
+	/* unmap i/o registers */
+	os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE);
+
+err_iomap:
+	/* free the dryice struct */
+	os_free_memory(di);
+
+err_alloc:
+	os_dev_init_return(rc);
+}
+
+/*
+ * dryice driver exit routine
+ */
+OS_DEV_SHUTDOWN(dryice_exit)
+{
+	/* don't allow new operations */
+	di->exit_flag = 1;
+
+	/* wait for the current operation to complete */
+	os_sleep(exit_queue, di->busy == 0, 0);
+
+	/* unregister interrupts */
+	if (di->irq_norm.set)
+		os_deregister_interrupt(di->irq_norm.irq);
+	if (di->irq_sec.set)
+		os_deregister_interrupt(di->irq_sec.irq);
+
+	/* turn off clocks (is there a portable way to do this?) */
+	clk_disable(di->clk);
+	clk_put(di->clk);
+
+	/* unallocate locks */
+	os_lock_deallocate(di->busy_lock);
+
+	/* unmap i/o registers */
+	os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE);
+
+	/* free the dryice struct */
+	os_free_memory(di);
+
+	os_dev_shutdown_return(OS_ERROR_OK_S);
+}
+
+di_return_t dryice_set_programmed_key(const void *key_data, int key_bits,
+				      int flags)
+{
+	uint32_t dcr;
+	int key_bytes, reg;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (key_data == NULL) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+	if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+	if (flags & DI_FUNC_FLAG_WORD_KEY) {
+		if (key_bits % 32 || (uint32_t)key_data & 0x3) {
+			rc = DI_ERR_INVAL;
+			goto err;
+		}
+	}
+	if (di->key_programmed) {
+		rc = DI_ERR_INUSE;
+		goto err;
+	}
+	if (di_state() == DI_STATE_FAILURE) {
+		rc = DI_ERR_STATE;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_PKWHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_PKWSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	key_bytes = key_bits / 8;
+
+	todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0);
+
+	/* accomodate busses that can only do 32-bit transfers */
+	if (flags & DI_FUNC_FLAG_WORD_KEY) {
+		uint32_t *keyp = (void *)key_data;
+
+		for (reg = 0; reg < MAX_KEY_WORDS; reg++) {
+			if (reg < MAX_KEY_WORDS - key_bytes / 4)
+				todo_write_val(0, DPKR7 - reg * 4);
+			else {
+				todo_write_ptr32(keyp, DPKR7 - reg * 4);
+				keyp++;
+			}
+		}
+	} else {
+		uint8_t *keyp = (void *)key_data;
+
+		for (reg = 0; reg < MAX_KEY_WORDS; reg++) {
+			int size = key_bytes - (MAX_KEY_WORDS - reg - 1) * 4;
+			if (size <= 0)
+				todo_write_val(0, DPKR7 - reg * 4);
+			else {
+				if (size > 4)
+					size = 4;
+				todo_write_ptr(keyp, DPKR7 - reg * 4, size);
+				keyp += size;
+			}
+		}
+	}
+	todo_assign(di->key_programmed, 1);
+
+	if (flags & DI_FUNC_LOCK_FLAGS) {
+		dcr = di_read(DCR);
+		if (flags & DI_FUNC_FLAG_READ_LOCK) {
+			if (flags & DI_FUNC_FLAG_HARD_LOCK)
+				dcr |= DCR_PKRHL;
+			else
+				dcr |= DCR_PKRSL;
+		}
+		if (flags & DI_FUNC_FLAG_WRITE_LOCK) {
+			if (flags & DI_FUNC_FLAG_HARD_LOCK)
+				dcr |= DCR_PKWHL;
+			else
+				dcr |= DCR_PKWSL;
+		}
+		todo_write_val(dcr, DCR);
+	}
+	todo_start();
+
+	if (flags & DI_FUNC_FLAG_ASYNC)
+		return 0;
+
+	rc = todo_wait_done();
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_set_programmed_key);
+
+di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits)
+{
+	int reg, byte, key_bytes;
+	uint32_t dcr, dpkr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (key_data == NULL) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+	if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+	#if 0
+	if (!di->key_programmed) {
+		rc = DI_ERR_UNSET;
+		goto err;
+	}
+	#endif
+	if (di_state() == DI_STATE_FAILURE) {
+		rc = DI_ERR_STATE;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_PKRHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_PKRSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	key_bytes = key_bits / 8;
+
+	/* read key */
+	for (reg = 0; reg < MAX_KEY_WORDS; reg++) {
+		if (reg < (MAX_KEY_BYTES - key_bytes) / 4)
+			continue;
+		dpkr = di_read(DPKR7 - reg * 4);
+
+		for (byte = 0; byte < 4; byte++) {
+			if (reg * 4 + byte >= MAX_KEY_BYTES - key_bytes) {
+				int shift = 24 - byte * 8;
+				*key_data++ = (dpkr >> shift) & 0xff;
+			}
+		}
+		dpkr = 0;	/* cleared for security */
+	}
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_get_programmed_key);
+
+di_return_t dryice_release_programmed_key(void)
+{
+	uint32_t dcr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (!di->key_programmed) {
+		rc = DI_ERR_UNSET;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_PKWHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_PKWSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	di->key_programmed = 0;
+
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_release_programmed_key);
+
+di_return_t dryice_set_random_key(int flags)
+{
+	uint32_t dcr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (di_state() == DI_STATE_FAILURE) {
+		rc = DI_ERR_STATE;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_RKHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_RKSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0);
+
+	/* clear Random Key Error bit, if set */
+	if (di_read(DSR) & DSR_RKE)
+		todo_write_val(DSR_RKE, DCR);
+
+	/* load random key */
+	todo_write_val(DKCR_LRK, DKCR);
+
+	/* wait for RKV (valid) or RKE (error) */
+	todo_wait_rkg();
+
+	if (flags & DI_FUNC_LOCK_FLAGS) {
+		dcr = di_read(DCR);
+		if (flags & DI_FUNC_FLAG_WRITE_LOCK) {
+			if (flags & DI_FUNC_FLAG_HARD_LOCK)
+				dcr |= DCR_RKHL;
+			else
+				dcr |= DCR_RKSL;
+		}
+		todo_write_val(dcr, DCR);
+	}
+	todo_start();
+
+	if (flags & DI_FUNC_FLAG_ASYNC)
+		return 0;
+
+	rc = todo_wait_done();
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_set_random_key);
+
+di_return_t dryice_select_key(di_key_t key, int flags)
+{
+	uint32_t dcr, dksr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	switch (key) {
+	case DI_KEY_FK:
+		dksr = DKSR_IIM_KEY;
+		break;
+	case DI_KEY_PK:
+		dksr = DKSR_PROG_KEY;
+		break;
+	case DI_KEY_RK:
+		dksr = DKSR_RAND_KEY;
+		break;
+	case DI_KEY_FPK:
+		dksr = DKSR_PROG_XOR_IIM_KEY;
+		break;
+	case DI_KEY_FRK:
+		dksr = DKSR_RAND_XOR_IIM_KEY;
+		break;
+	default:
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+	if (di->key_selected) {
+		rc = DI_ERR_INUSE;
+		goto err;
+	}
+	if (di_state() != DI_STATE_VALID) {
+		rc = DI_ERR_STATE;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_KSHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_KSSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0);
+
+	/* select key */
+	todo_write_val(dksr, DKSR);
+
+	todo_assign(di->key_selected, 1);
+
+	if (flags & DI_FUNC_LOCK_FLAGS) {
+		dcr = di_read(DCR);
+		if (flags & DI_FUNC_FLAG_WRITE_LOCK) {
+			if (flags & DI_FUNC_FLAG_HARD_LOCK)
+				dcr |= DCR_KSHL;
+			else
+				dcr |= DCR_KSSL;
+		}
+		todo_write_val(dcr, DCR);
+	}
+	todo_start();
+
+	if (flags & DI_FUNC_FLAG_ASYNC)
+		return 0;
+
+	rc = todo_wait_done();
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_select_key);
+
+di_return_t dryice_check_key(di_key_t *key)
+{
+	uint32_t dksr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (key == NULL) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+
+	dksr = di_read(DKSR);
+
+	if (di_state() != DI_STATE_VALID) {
+		dksr = DKSR_IIM_KEY;
+		rc = DI_ERR_STATE;
+	} else if (dksr == DI_KEY_RK || dksr == DI_KEY_FRK) {
+		if (!(di_read(DSR) & DSR_RKV)) {
+			dksr = DKSR_IIM_KEY;
+			rc = DI_ERR_UNSET;
+		}
+	}
+	switch (dksr) {
+	case DKSR_IIM_KEY:
+		*key = DI_KEY_FK;
+		break;
+	case DKSR_PROG_KEY:
+		*key = DI_KEY_PK;
+		break;
+	case DKSR_RAND_KEY:
+		*key = DI_KEY_RK;
+		break;
+	case DKSR_PROG_XOR_IIM_KEY:
+		*key = DI_KEY_FPK;
+		break;
+	case DKSR_RAND_XOR_IIM_KEY:
+		*key = DI_KEY_FRK;
+		break;
+	}
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_check_key);
+
+di_return_t dryice_release_key_selection(void)
+{
+	uint32_t dcr;
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (!di->key_selected) {
+		rc = DI_ERR_UNSET;
+		goto err;
+	}
+	dcr = di_read(DCR);
+	if (dcr & DCR_KSHL) {
+		rc = DI_ERR_HLOCK;
+		goto err;
+	}
+	if (dcr & DCR_KSSL) {
+		rc = DI_ERR_SLOCK;
+		goto err;
+	}
+	di->key_selected = 0;
+
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_release_key_selection);
+
+di_return_t dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp,
+				    int flags)
+{
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	if (di_state() == DI_STATE_VALID) {
+		rc = DI_ERR_STATE;
+		goto err;
+	}
+	if (events == NULL) {
+		rc = DI_ERR_INVAL;
+		goto err;
+	}
+		*events = di_read(DSR) & DSR_TAMPER_BITS;
+	if (timestamp) {
+		if (di_state() == DI_STATE_NON_VALID)
+			*timestamp = di_read(DTCMR);
+		else
+			*timestamp = 0;
+	}
+err:
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_get_tamper_event);
+
+di_return_t dryice_register_callback(void (*func)(di_return_t,
+						  unsigned long cookie),
+				     unsigned long cookie)
+{
+	di_return_t rc = 0;
+
+	if (di_busy_set())
+		return DI_ERR_BUSY;
+
+	di->cb_func = func;
+	di->cb_cookie = cookie;
+
+	di_busy_clear();
+	return rc;
+}
+EXTERN_SYMBOL(dryice_register_callback);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("DryIce");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/security/dryice.h b/drivers/mxc/security/dryice.h
new file mode 100644
index 000000000000..8334b5098d31
--- /dev/null
+++ b/drivers/mxc/security/dryice.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+#ifndef __DRYICE_H__
+#define __DRYICE_H__
+
+
+/*!
+ * @file dryice.h
+ * @brief Definition of DryIce API.
+ */
+
+/*! @page dryice_api DryIce API
+ *
+ * Definition of the DryIce API.
+ *
+ * The DryIce API implements a software interface to the DryIce hardware
+ * block. Methods are provided to store, retrieve, generate, and  manage
+ * cryptographic keys and to monitor security tamper events.
+ *
+ * See @ref dryice_api for the DryIce API.
+ */
+
+/*!
+ * This defines the SCC key length (in bits)
+ */
+#define SCC_KEY_LEN     168
+
+/*!
+ * This defines the maximum key length (in bits)
+ */
+#define MAX_KEY_LEN     256
+#define MAX_KEY_BYTES	((MAX_KEY_LEN) / 8)
+#define MAX_KEY_WORDS	((MAX_KEY_LEN) / 32)
+
+/*!
+ * @name DryIce Function Flags
+ */
+/*@{*/
+#define DI_FUNC_FLAG_ASYNC       0x01  /*!< do not block */
+#define DI_FUNC_FLAG_READ_LOCK   0x02  /*!< set read lock for this resource */
+#define DI_FUNC_FLAG_WRITE_LOCK  0x04  /*!< set write lock for resource */
+#define DI_FUNC_FLAG_HARD_LOCK   0x08  /*!< locks will be hard (default soft) */
+#define DI_FUNC_FLAG_WORD_KEY    0x10  /*!< key provided as 32-bit words */
+/*@}*/
+
+/*!
+ * @name DryIce Tamper Events
+ */
+/*@{*/
+#define DI_TAMPER_EVENT_WTD   (1 << 23)  /*!< wire-mesh tampering det */
+#define DI_TAMPER_EVENT_ETBD  (1 << 22)  /*!< ext tampering det: input B */
+#define DI_TAMPER_EVENT_ETAD  (1 << 21)  /*!< ext tampering det: input A */
+#define DI_TAMPER_EVENT_EBD   (1 << 20)  /*!< external boot detected */
+#define DI_TAMPER_EVENT_SAD   (1 << 19)  /*!< security alarm detected */
+#define DI_TAMPER_EVENT_TTD   (1 << 18)  /*!< temperature tampering det */
+#define DI_TAMPER_EVENT_CTD   (1 << 17)  /*!< clock tampering det */
+#define DI_TAMPER_EVENT_VTD   (1 << 16)  /*!< voltage tampering det */
+#define DI_TAMPER_EVENT_MCO   (1 <<  3)  /*!< monotonic counter overflow */
+#define DI_TAMPER_EVENT_TCO   (1 <<  2)  /*!< time counter overflow */
+/*@}*/
+
+/*!
+ * DryIce Key Sources
+ */
+typedef enum di_key {
+	DI_KEY_FK,   /*!< the fused (IIM) key */
+	DI_KEY_PK,   /*!< the programmed key */
+	DI_KEY_RK,   /*!< the random key */
+	DI_KEY_FPK,  /*!< the programmed key XORed with the fused key */
+	DI_KEY_FRK,  /*!< the random key XORed with the fused key */
+} di_key_t;
+
+/*!
+ * DryIce Error Codes
+ */
+typedef enum dryice_return {
+	DI_SUCCESS = 0,  /*!< operation was successful */
+	DI_ERR_BUSY,     /*!< device or resource busy */
+	DI_ERR_STATE,    /*!< dryice is in incompatible state */
+	DI_ERR_INUSE,    /*!< resource is already in use */
+	DI_ERR_UNSET,    /*!< resource has not been initialized */
+	DI_ERR_WRITE,    /*!< error occurred during register write */
+	DI_ERR_INVAL,    /*!< invalid argument */
+	DI_ERR_FAIL,     /*!< operation failed */
+	DI_ERR_HLOCK,    /*!< resource is hard locked */
+	DI_ERR_SLOCK,    /*!< resource is soft locked */
+	DI_ERR_NOMEM,    /*!< out of memory */
+} di_return_t;
+
+/*!
+ * These functions define the DryIce API.
+ */
+
+/*!
+ * Write a given key to the Programmed Key registers in DryIce, and
+ * optionally lock the Programmed Key against either reading or further
+ * writing. The value is held until a call to the release_programmed_key
+ * interface is made, or until the appropriate HW reset if the write-lock
+ * flags are used.  Unused key bits will be zeroed.
+ *
+ * @param[in]  key_data   A pointer to the key data to be programmed, with
+ *                        the most significant byte or word first.  This
+ *                        will be interpreted as a byte pointer unless the
+ *                        WORD_KEY flag is set, in which case it will be
+ *                        treated as a word pointer and the key data will be
+ *                        read a word at a time, starting with the MSW.
+ *                        When called asynchronously, the data pointed to by
+ *                        key_data must persist until the operation completes.
+ *
+ * @param[in]  key_bits   The number of bits in the key to be stored.
+ *                        This must be a multiple of 8 and within the
+ *                        range of 0 and MAX_KEY_LEN.
+ *
+ * @param[in]  flags      This is a bit-wise OR of the flags to be passed
+ *                        to the function.  Flags can include:
+ *                        ASYNC, READ_LOCK, WRITE_LOCK, HARD_LOCK, and
+ *                        WORD_KEY.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, INVAL
+ *                        on invalid arguments, INUSE if key has already been
+ *                        programmed, STATE if DryIce is in the wrong state,
+ *                        HLOCK or SLOCK if the key registers are locked for
+ *                        writing, and WRITE if a write error occurs
+ *                        (See #di_return_t).
+ */
+extern di_return_t dryice_set_programmed_key(const void *key_data, int key_bits,
+					     int flags);
+
+/*!
+ * Read the Programmed Key registers and write the contents into a buffer.
+ *
+ * @param[out] key_data   A byte pointer to where the key data will be written,
+ *                        with the most significant byte being written first.
+ *
+ * @param[in]  key_bits   The number of bits of the key to be retrieved.
+ *                        This must be a multiple of 8 and within the
+ *                        range of 0 and MAX_KEY_LEN.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, INVAL
+ *                        on invalid arguments, UNSET if key has not been
+ *                        programmed, STATE if DryIce is in the wrong state,
+ *                        and HLOCK or SLOCK if the key registers are locked for
+ *                        reading (See #di_return_t).
+ */
+extern di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits);
+
+/*!
+ * Allow the set_programmed_key interface to be used to write a new
+ * Programmed Key to DryIce. Note that this interface does not overwrite
+ * the value in the Programmed Key registers.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy,
+ *                        UNSET if the key has not been previously set, and
+ *                        HLOCK or SLOCK if the key registers are locked for
+ *                        writing (See #di_return_t).
+ */
+extern di_return_t dryice_release_programmed_key(void);
+
+/*!
+ * Generate and load a new Random Key in DryIce, and optionally lock the
+ * Random Key against further change.
+ *
+ * @param[in]  flags      This is a bit-wise OR of the flags to be passed
+ *                        to the function.  Flags can include:
+ *                        ASYNC, READ_LOCK, WRITE_LOCK, and HARD_LOCK.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, STATE
+ *                        if DryIce is in the wrong state, FAIL if the key gen
+ *                        failed, HLOCK or SLOCK if the key registers are
+ *                        locked, and WRITE if a write error occurs
+ *                        (See #di_return_t).
+ */
+extern di_return_t dryice_set_random_key(int flags);
+
+/*!
+ * Set the key selection in DryIce to determine the key used by an
+ * encryption module such as SCC. The selection is held until a call to the
+ * Release Selected Key interface is made, or until the appropriate HW
+ * reset if the LOCK flags are used.
+ *
+ * @param[in]   key       The source of the key to be used by the SCC
+ *                        (See #di_key_t).
+ *
+ * @param[in]  flags      This is a bit-wise OR of the flags to be passed
+ *                        to the function.  Flags can include:
+ *                        ASYNC, WRITE_LOCK, and HARD_LOCK.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, INVAL
+ *                        on invalid arguments, INUSE if a selection has already
+ *                        been made, STATE if DryIce is in the wrong state,
+ *                        HLOCK or SLOCK if the selection register is locked,
+ *                        and WRITE if a write error occurs
+ */
+extern di_return_t dryice_select_key(di_key_t key, int flags);
+
+/*!
+ * Check which key will be used in the SCC. This is needed because in some
+ * DryIce states, the Key Select Register is overridden by a default value
+ * (the Fused/IIM key).
+ *
+ * @param[out] key        The source of the key that is currently selected for
+ *                        use by the SCC.  This may be different from the key
+ *                        specified by the dryice_select_key function
+ *                        (See #di_key_t).  This value is set even if an error
+ *                        code (except for BUSY) is returned.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, STATE if
+ *                        DryIce is in the wrong state, INVAL on invalid
+ *                        arguments, or UNSET if no key has been selected
+ *                        (See #di_return_t).
+ */
+extern di_return_t dryice_check_key(di_key_t *key);
+
+/*!
+ * Allow the dryice_select_key interface to be used to set a new key selection
+ * in DryIce. Note that this interface does not overwrite the value in DryIce.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, UNSET
+ *                        if the no selection has been made previously, and
+ *                        HLOCK or SLOCK if the selection register is locked
+ *                        (See #di_return_t).
+ */
+extern di_return_t dryice_release_key_selection(void);
+
+/*!
+ * Returns tamper-detection status bits. Also an optional timestamp when
+ * DryIce is in the Non-valid state. If DryIce is not in Failure or Non-valid
+ * state, this interface returns a failure code.
+ *
+ * @param[out] events     This is a bit-wise OR of the following events:
+ *                        WTD (Wire Mesh), ETBD (External Tamper B),
+ *                        ETAD (External Tamper A), EBD (External Boot),
+ *                        SAD (Security Alarm), TTD (Temperature Tamper),
+ *                        CTD (Clock Tamper), VTD (Voltage Tamper),
+ *                        MCO (Monolithic Counter Overflow), and
+ *                        TCO (Time Counter Overflow).
+ *
+ * @param[out] timestamp  This is the value of the time counter in seconds
+ *                        when the tamper occurred.  A timestamp will not be
+ *                        returned if a NULL pointer is specified.  If DryIce
+ *                        is not in the Non-valid state the time cannot be
+ *                        read, so a timestamp of 0 will be returned.
+ *
+ * @param[in]  flags      This is a bit-wise OR of the flags to be passed
+ *                        to the function.  Flags is ignored currently by
+ *                        this function.
+ *
+ * @return                Returns SUCCESS (0), BUSY if DryIce is busy, and
+ *                        INVAL on invalid arguments (See #di_return_t).
+ */
+extern di_return_t
+dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp, int flags);
+
+/*!
+ * Provide a callback function to be called upon the completion of DryIce calls
+ * that are executed asynchronously.
+ *
+ * @param[in]  func       This is a pointer to a function of type:
+ *                        void callback(di_return_t rc, unsigned long cookie)
+ *                        The return code of the async function is passed
+ *                        back in "rc" along with the cookie provided when
+ *                        registering the callback.
+ *
+ * @param[in]  cookie     This is an "opaque" cookie of type unsigned long that
+ *                        is returned on subsequent callbacks.  It may be of any
+ *                        value.
+ *
+ * @return                Returns SUCCESS (0), or BUSY if DryIce is busy
+ *                        (See #di_return_t).
+ */
+extern di_return_t dryice_register_callback(void (*func)(di_return_t rc,
+							 unsigned long cookie),
+					    unsigned long cookie);
+
+#endif /* __DRYICE_H__ */
diff --git a/drivers/mxc/security/mxc_scc.c b/drivers/mxc/security/mxc_scc.c
new file mode 100644
index 000000000000..8a6b0c2419b5
--- /dev/null
+++ b/drivers/mxc/security/mxc_scc.c
@@ -0,0 +1,2386 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_scc.c
+ *
+ * This is the driver code for the Security Controller (SCC).  It has no device
+ * driver interface, so no user programs may access it.  Its interaction with
+ * the Linux kernel is from calls to #scc_init() when the driver is loaded, and
+ * #scc_cleanup() should the driver be unloaded.  The driver uses locking and
+ * (task-sleep/task-wakeup) functions of the kernel.  It also registers itself
+ * to handle the interrupt line(s) from the SCC.
+ *
+ * Other drivers in the kernel may use the remaining API functions to get at
+ * the services of the SCC.  The main service provided is the Secure Memory,
+ * which allows encoding and decoding of secrets with a per-chip secret key.
+ *
+ * The SCC is single-threaded, and so is this module.  When the scc_crypt()
+ * routine is called, it will lock out other accesses to the function.  If
+ * another task is already in the module, the subsequent caller will spin on a
+ * lock waiting for the other access to finish.
+ *
+ * Note that long crypto operations could cause a task to spin for a while,
+ * preventing other kernel work (other than interrupt processing) to get done.
+ *
+ * The external (kernel module) interface is through the following functions:
+ * @li scc_get_configuration()
+ * @li scc_crypt()
+ * @li scc_zeroize_memories()
+ * @li scc_monitor_security_failure()
+ * @li scc_stop_monitoring_security_failure()
+ * @li scc_set_sw_alarm()
+ * @li scc_read_register()
+ * @li scc_write_register()
+ *
+ * All other functions are internal to the driver.
+ *
+ * @ingroup MXCSCC
+*/
+#include "sahara2/include/fsl_platform.h"
+#include "sahara2/include/portable_os.h"
+#include "mxc_scc_internals.h"
+
+#include <linux/delay.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+
+#include <linux/device.h>
+#include <mach/clock.h>
+#include <linux/device.h>
+
+#else
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#endif
+
+/*!
+ * This is the set of errors which signal that access to the SCM RAM has
+ * failed or will fail.
+ */
+#define SCM_ACCESS_ERRORS                                                  \
+       (SCM_ERR_USER_ACCESS | SCM_ERR_ILLEGAL_ADDRESS |                    \
+        SCM_ERR_ILLEGAL_MASTER | SCM_ERR_CACHEABLE_ACCESS |                \
+        SCM_ERR_UNALIGNED_ACCESS | SCM_ERR_BYTE_ACCESS |                   \
+        SCM_ERR_INTERNAL_ERROR | SCM_ERR_SMN_BLOCKING_ACCESS |             \
+        SCM_ERR_CIPHERING | SCM_ERR_ZEROIZING | SCM_ERR_BUSY)
+/******************************************************************************
+ *
+ *  Global / Static Variables
+ *
+ *****************************************************************************/
+
+/*!
+ * This is type void* so that a) it cannot directly be dereferenced,
+ * and b) pointer arithmetic on it will function in a 'normal way' for
+ * the offsets in scc_defines.h
+ *
+ * scc_base is the location in the iomap where the SCC's registers
+ * (and memory) start.
+ *
+ * The referenced data is declared volatile so that the compiler will
+ * not make any assumptions about the value of registers in the SCC,
+ * and thus will always reload the register into CPU memory before
+ * using it (i.e. wherever it is referenced in the driver).
+ *
+ * This value should only be referenced by the #SCC_READ_REGISTER and
+ * #SCC_WRITE_REGISTER macros and their ilk.  All dereferences must be
+ * 32 bits wide.
+ */
+static volatile void *scc_base;
+
+/*! Array to hold function pointers registered by
+    #scc_monitor_security_failure() and processed by
+    #scc_perform_callbacks() */
+static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void);
+
+/*! Structure returned by #scc_get_configuration() */
+static scc_config_t scc_configuration = {
+	.driver_major_version = SCC_DRIVER_MAJOR_VERSION_1,
+	.driver_minor_version = SCC_DRIVER_MINOR_VERSION_8,
+	.scm_version = -1,
+	.smn_version = -1,
+	.block_size_bytes = -1,
+	.black_ram_size_blocks = -1,
+	.red_ram_size_blocks = -1
+};
+
+/*! Key Control Information.  Integrity is controlled by use of
+    #scc_crypto_lock. */
+static struct scc_key_slot scc_key_info[SCC_KEY_SLOTS];
+
+/*! Internal flag to know whether SCC is in Failed state (and thus many
+ *  registers are unavailable).  Once it goes failed, it never leaves it. */
+static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL;
+
+/*! Flag to say whether interrupt handler has been registered for
+ * SMN interrupt */
+static int smn_irq_set = 0;
+
+/*! Flag to say whether interrupt handler has been registered for
+ * SCM interrupt */
+static int scm_irq_set = 0;
+
+/*! This lock protects the #scc_callbacks list as well as the @c
+ * callbacks_performed flag in #scc_perform_callbacks.  Since the data this
+ * protects may be read or written from either interrupt or base level, all
+ * operations should use the irqsave/irqrestore or similar to make sure that
+ * interrupts are inhibited when locking from base level.
+ */
+static spinlock_t scc_callbacks_lock = SPIN_LOCK_UNLOCKED;
+
+/*!
+ * Ownership of this lock prevents conflicts on the crypto operation in the SCC
+ * and the integrity of the #scc_key_info.
+ */
+static spinlock_t scc_crypto_lock = SPIN_LOCK_UNLOCKED;
+
+/*! Calculated once for quick reference to size of the unreserved space in one
+ *  RAM in SCM.
+ */
+static uint32_t scc_memory_size_bytes;
+
+/*! Calculated once for quick reference to size of SCM address space */
+static uint32_t scm_highest_memory_address;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18))
+#ifndef SCC_CLOCK_NOT_GATED
+/*! Pointer to SCC's clock information.  Initialized during scc_init(). */
+static struct clk *scc_clk = NULL;
+#endif
+#endif
+
+/*! The lookup table for an 8-bit value.  Calculated once
+ * by #scc_init_ccitt_crc().
+ */
+static uint16_t scc_crc_lookup_table[256];
+
+/*! Fixed padding for appending to plaintext to fill out a block */
+static uint8_t scc_block_padding[8] =
+    { SCC_DRIVER_PAD_CHAR, 0, 0, 0, 0, 0, 0, 0 };
+
+/******************************************************************************
+ *
+ *  Function Implementations - Externally Accessible
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/* fn scc_init()                                                             */
+/*****************************************************************************/
+/*!
+ *  Initialize the driver at boot time or module load time.
+ *
+ *  Register with the kernel as the interrupt handler for the SCC interrupt
+ *  line(s).
+ *
+ *  Map the SCC's register space into the driver's memory space.
+ *
+ *  Query the SCC for its configuration and status.  Save the configuration in
+ *  #scc_configuration and save the status in #scc_availability.  Called by the
+ *  kernel.
+ *
+ *  Do any locking/wait queue initialization which may be necessary.
+ *
+ *  The availability fuse may be checked, depending on platform.
+ */
+static int scc_init(void)
+{
+	uint32_t smn_status;
+	int i;
+	int return_value = -EIO;	/* assume error */
+	if (scc_availability == SCC_STATUS_INITIAL) {
+
+		/* Set this until we get an initial reading */
+		scc_availability = SCC_STATUS_CHECKING;
+
+		/* Initialize the constant for the CRC function */
+		scc_init_ccitt_crc();
+
+		/* initialize the callback table */
+		for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+			scc_callbacks[i] = 0;
+		}
+
+		/* Initialize key slots */
+		for (i = 0; i < SCC_KEY_SLOTS; i++) {
+			scc_key_info[i].offset = i * SCC_KEY_SLOT_SIZE;
+			scc_key_info[i].status = 0;	/* unassigned */
+		}
+
+		/* Enable the SCC clock on platforms where it is gated */
+#ifndef SCC_CLOCK_NOT_GATED
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+		mxc_clks_enable(SCC_CLK);
+#else
+
+		scc_clk = clk_get(NULL, "scc_clk");
+		if (scc_clk != ERR_PTR(ENOENT)) {
+			clk_enable(scc_clk);
+		}
+#endif				/* LINUX_VERSION_CODE */
+
+#endif				/* SCC_CLOCK_NOT_GATED */
+		/* See whether there is an SCC available */
+		if (0 && !SCC_ENABLED()) {
+			os_printk(KERN_ERR
+				  "SCC: Fuse for SCC is set to disabled.  Exiting.\n");
+		} else {
+			/* Map the SCC (SCM and SMN) memory on the internal bus into
+			   kernel address space */
+			scc_base = (void *)IO_ADDRESS(SCC_BASE);
+
+			/* If that worked, we can try to use the SCC */
+			if (scc_base == NULL) {
+				os_printk(KERN_ERR
+					  "SCC: Register mapping failed.  Exiting.\n");
+			} else {
+				/* Get SCM into 'clean' condition w/interrupts cleared &
+				   disabled */
+				SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+						   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+						   |
+						   SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+
+				/* Clear error status register (any write will do it) */
+				SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0);
+
+				/*
+				 * There is an SCC.  Determine its current state.  Side effect
+				 * is to populate scc_config and scc_availability
+				 */
+				smn_status = scc_grab_config_values();
+
+				/* Try to set up interrupt handler(s) */
+				if (scc_availability == SCC_STATUS_OK) {
+					if (setup_interrupt_handling() != 0) {
+						unsigned condition;
+			/*!
+			 * The error could be only that the SCM interrupt was
+			 * not set up.  This interrupt is always masked, so
+			 * that is not an issue.
+			 *
+			 * The SMN's interrupt may be shared on that line, it
+			 * may be separate, or it may not be wired.  Do what
+			 * is necessary to check its status.
+			 *
+			 * Although the driver is coded for possibility of not
+			 * having SMN interrupt, the fact that there is one
+			 * means it should be available and used.
+			 */
+#ifdef USE_SMN_INTERRUPT
+						condition = !smn_irq_set;	/* Separate. Check SMN binding */
+#elif !defined(NO_SMN_INTERRUPT)
+						condition = !scm_irq_set;	/* Shared. Check SCM binding */
+#else
+						condition = FALSE;	/*  SMN not wired at all.  Ignore. */
+#endif
+						/* setup was not able to set up SMN interrupt */
+						scc_availability =
+						    SCC_STATUS_UNIMPLEMENTED;
+					}	/* interrupt handling returned non-zero */
+				}	/* availability is OK */
+				if (scc_availability == SCC_STATUS_OK) {
+					/* Get SMN into 'clean' condition w/interrupts cleared &
+					   enabled */
+					SCC_WRITE_REGISTER(SMN_COMMAND,
+							   SMN_COMMAND_CLEAR_INTERRUPT
+							   |
+							   SMN_COMMAND_ENABLE_INTERRUPT);
+				}
+				/* availability is still OK */
+			}	/* if scc_base != NULL */
+
+		}		/* if SCC_ENABLED() */
+
+		/*
+		 * If status is SCC_STATUS_UNIMPLEMENTED or is still
+		 * SCC_STATUS_CHECKING, could be leaving here with the driver partially
+		 * initialized.  In either case, cleanup (which will mark the SCC as
+		 * UNIMPLEMENTED).
+		 */
+		if (scc_availability == SCC_STATUS_CHECKING ||
+		    scc_availability == SCC_STATUS_UNIMPLEMENTED) {
+			scc_cleanup();
+		} else {
+			return_value = 0;	/* All is well */
+		}
+	}
+	/* ! STATUS_INITIAL */
+	pr_debug("SCC: Driver Status is %s\n",
+		 (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" :
+		 (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" :
+		 (scc_availability ==
+		  SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED"
+		 : (scc_availability ==
+		    SCC_STATUS_OK) ? "OK" : (scc_availability ==
+					     SCC_STATUS_FAILED) ? "FAILED" :
+		 "UNKNOWN");
+
+	return return_value;
+}				/* scc_init */
+
+/*****************************************************************************/
+/* fn scc_cleanup()                                                          */
+/*****************************************************************************/
+/*!
+ * Perform cleanup before driver/module is unloaded by setting the machine
+ * state close to what it was when the driver was loaded.  This function is
+ * called when the kernel is shutting down or when this driver is being
+ * unloaded.
+ *
+ * A driver like this should probably never be unloaded, especially if there
+ * are other module relying upon the callback feature for monitoring the SCC
+ * status.
+ *
+ * In any case, cleanup the callback table (by clearing out all of the
+ * pointers).  Deregister the interrupt handler(s).  Unmap SCC registers.
+ *
+ */
+static void scc_cleanup(void)
+{
+	int i;
+
+	/* Mark the driver / SCC as unusable. */
+	scc_availability = SCC_STATUS_UNIMPLEMENTED;
+
+	/* Clear out callback table */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		scc_callbacks[i] = 0;
+	}
+
+	/* If SCC has been mapped in, clean it up and unmap it */
+	if (scc_base) {
+		/* For the SCM, disable interrupts, zeroize RAMs.  Interrupt
+		 * status will appear because zeroize will complete. */
+		SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+				   SCM_INTERRUPT_CTRL_MASK_INTERRUPTS |
+				   SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY);
+
+		/* For the SMN, clear and disable interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT);
+
+		/* remove virtual mapping */
+		iounmap((void *)scc_base);
+	}
+
+	/* Now that interrupts cannot occur, disassociate driver from the interrupt
+	 * lines.
+	 */
+
+	/* Deregister SCM interrupt handler */
+	if (scm_irq_set) {
+		os_deregister_interrupt(INT_SCC_SCM);
+	}
+
+	/* Deregister SMN interrupt handler */
+	if (smn_irq_set) {
+#ifdef USE_SMN_INTERRUPT
+		os_deregister_interrupt(INT_SCC_SMN);
+#endif
+	}
+	pr_debug("SCC driver cleaned up.\n");
+
+}				/* scc_cleanup */
+
+/*****************************************************************************/
+/* fn scc_get_configuration()                                                */
+/*****************************************************************************/
+scc_config_t *scc_get_configuration(void)
+{
+	/*
+	 * If some other driver calls scc before the kernel does, make sure that
+	 * this driver's initialization is performed.
+	 */
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+  /*!
+     * If there is no SCC, yet the driver exists, the value -1 will be in
+     * the #scc_config_t fields for other than the driver versions.
+     */
+	return &scc_configuration;
+}				/* scc_get_configuration */
+
+/*****************************************************************************/
+/* fn scc_zeroize_memories()                                                 */
+/*****************************************************************************/
+scc_return_t scc_zeroize_memories(void)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+	uint32_t status;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	if (scc_availability == SCC_STATUS_OK) {
+		unsigned long irq_flags;	/* for IRQ save/restore */
+
+		/* Lock access to crypto memory of the SCC */
+		spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+		/* Start the Zeroize by setting a bit in the SCM_INTERRUPT_CTRL
+		 * register */
+		SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+				   SCM_INTERRUPT_CTRL_MASK_INTERRUPTS
+				   | SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY);
+
+		scc_wait_completion();
+
+		/* Get any error info */
+		status = SCC_READ_REGISTER(SCM_ERROR_STATUS);
+
+		/* unlock the SCC */
+		spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+		if (!(status & SCM_ERR_ZEROIZE_FAILED)) {
+			return_status = SCC_RET_OK;
+		} else {
+			pr_debug
+			    ("SCC: Zeroize failed.  SCM Error Status is 0x%08x\n",
+			     status);
+		}
+
+		/* Clear out any status. */
+		SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+				   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+				   | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+
+		/* and any error status */
+		SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0);
+	}
+
+	return return_status;
+}				/* scc_zeroize_memories */
+
+/*****************************************************************************/
+/* fn scc_crypt()                                                            */
+/*****************************************************************************/
+scc_return_t
+scc_crypt(unsigned long count_in_bytes, const uint8_t * data_in,
+	  const uint8_t * init_vector,
+	  scc_enc_dec_t direction, scc_crypto_mode_t crypto_mode,
+	  scc_verify_t check_mode, uint8_t * data_out,
+	  unsigned long *count_out_bytes)
+
+{
+	scc_return_t return_code = SCC_RET_FAIL;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	(void)scc_update_state();	/* in case no interrupt line from SMN */
+
+	/* make initial error checks */
+	if (scc_availability != SCC_STATUS_OK
+	    || count_in_bytes == 0
+	    || data_in == 0
+	    || data_out == 0
+	    || (crypto_mode != SCC_CBC_MODE && crypto_mode != SCC_ECB_MODE)
+	    || (crypto_mode == SCC_CBC_MODE && init_vector == NULL)
+	    || (direction != SCC_ENCRYPT && direction != SCC_DECRYPT)
+	    || (check_mode == SCC_VERIFY_MODE_NONE &&
+		count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0)
+	    || (direction == SCC_DECRYPT &&
+		count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0)
+	    || (check_mode != SCC_VERIFY_MODE_NONE &&
+		check_mode != SCC_VERIFY_MODE_CCITT_CRC)) {
+		pr_debug
+		    ("SCC: scc_crypt() count_in_bytes_ok = %d; data_in_ok = %d;"
+		     " data_out_ok = %d; iv_ok = %d\n", !(count_in_bytes == 0),
+		     !(data_in == 0), !(data_out == 0),
+		     !(crypto_mode == SCC_CBC_MODE && init_vector == NULL));
+		pr_debug("SCC: scc_crypt() mode_ok=%d; direction_ok=%d;"
+			 " size_ok=%d, check_mode_ok=%d\n",
+			 !(crypto_mode != SCC_CBC_MODE
+			   && crypto_mode != SCC_ECB_MODE),
+			 !(direction != SCC_ENCRYPT
+			   && direction != SCC_DECRYPT),
+			 !((check_mode == SCC_VERIFY_MODE_NONE
+			    && count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0)
+			   || (direction == SCC_DECRYPT
+			       && count_in_bytes % SCC_BLOCK_SIZE_BYTES() !=
+			       0)), !(check_mode != SCC_VERIFY_MODE_NONE
+				      && check_mode !=
+				      SCC_VERIFY_MODE_CCITT_CRC));
+		pr_debug("SCC: scc_crypt() detected bad argument\n");
+	} else {
+		/* Start settings for write to SCM_CONTROL register  */
+		uint32_t scc_control = SCM_CONTROL_START_CIPHER;
+		unsigned long irq_flags;	/* for IRQ save/restore */
+
+		/* Lock access to crypto memory of the SCC */
+		spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+		/* Special needs for CBC Mode */
+		if (crypto_mode == SCC_CBC_MODE) {
+			scc_control |= SCM_CBC_MODE;	/* change default of ECB */
+			/* Put in Initial Context.  Vector registers are contiguous */
+			copy_to_scc(init_vector, SCM_INIT_VECTOR_0,
+				    SCC_BLOCK_SIZE_BYTES(), NULL);
+		}
+
+		/* Fill the RED_START register */
+		SCC_WRITE_REGISTER(SCM_RED_START,
+				   SCM_NON_RESERVED_OFFSET /
+				   SCC_BLOCK_SIZE_BYTES());
+
+		/* Fill the BLACK_START register */
+		SCC_WRITE_REGISTER(SCM_BLACK_START,
+				   SCM_NON_RESERVED_OFFSET /
+				   SCC_BLOCK_SIZE_BYTES());
+
+		if (direction == SCC_ENCRYPT) {
+			/* Check for sufficient space in data_out */
+			if (check_mode == SCC_VERIFY_MODE_NONE) {
+				if (*count_out_bytes < count_in_bytes) {
+					return_code =
+					    SCC_RET_INSUFFICIENT_SPACE;
+				}
+			} else {	/* SCC_VERIFY_MODE_CCITT_CRC */
+				/* Calculate extra bytes needed for crc (2) and block
+				   padding */
+				int padding_needed =
+				    CRC_SIZE_BYTES + SCC_BLOCK_SIZE_BYTES() -
+				    ((count_in_bytes + CRC_SIZE_BYTES)
+				     % SCC_BLOCK_SIZE_BYTES());
+
+				/* Verify space is available */
+				if (*count_out_bytes <
+				    count_in_bytes + padding_needed) {
+					return_code =
+					    SCC_RET_INSUFFICIENT_SPACE;
+				}
+			}
+			/* If did not detect space error, do the encryption */
+			if (return_code != SCC_RET_INSUFFICIENT_SPACE) {
+				return_code =
+				    scc_encrypt(count_in_bytes, data_in,
+						scc_control, data_out,
+						check_mode ==
+						SCC_VERIFY_MODE_CCITT_CRC,
+						count_out_bytes);
+			}
+
+		}
+		/* direction == SCC_ENCRYPT */
+		else {		/* SCC_DECRYPT */
+			/* Check for sufficient space in data_out */
+			if (check_mode == SCC_VERIFY_MODE_NONE) {
+				if (*count_out_bytes < count_in_bytes) {
+					return_code =
+					    SCC_RET_INSUFFICIENT_SPACE;
+				}
+			} else {	/* SCC_VERIFY_MODE_CCITT_CRC */
+				/* Do initial check.  Assume last block (of padding) and CRC
+				 * will get stripped.  After decipher is done and padding is
+				 * removed, will know exact value.
+				 */
+				int possible_size =
+				    (int)count_in_bytes - CRC_SIZE_BYTES -
+				    SCC_BLOCK_SIZE_BYTES();
+				if ((int)*count_out_bytes < possible_size) {
+					pr_debug
+					    ("SCC: insufficient decrypt space %ld/%d.\n",
+					     *count_out_bytes, possible_size);
+					return_code =
+					    SCC_RET_INSUFFICIENT_SPACE;
+				}
+			}
+
+			/* If did not detect space error, do the decryption */
+			if (return_code != SCC_RET_INSUFFICIENT_SPACE) {
+				return_code =
+				    scc_decrypt(count_in_bytes, data_in,
+						scc_control, data_out,
+						check_mode ==
+						SCC_VERIFY_MODE_CCITT_CRC,
+						count_out_bytes);
+			}
+
+		}		/* SCC_DECRYPT */
+
+		/* unlock the SCC */
+		spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	}			/* else no initial error */
+
+	return return_code;
+}				/* scc_crypt */
+
+/*****************************************************************************/
+/* fn scc_set_sw_alarm()                                                     */
+/*****************************************************************************/
+void scc_set_sw_alarm(void)
+{
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Update scc_availability based on current SMN status.  This might
+	 * perform callbacks.
+	 */
+	(void)scc_update_state();
+
+	/* if everything is OK, make it fail */
+	if (scc_availability == SCC_STATUS_OK) {
+
+		/* sound the alarm (and disable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_SET_SOFTWARE_ALARM);
+
+		scc_availability = SCC_STATUS_FAILED;	/* Remember what we've done */
+
+		/* In case SMN interrupt is not available, tell the world */
+		scc_perform_callbacks();
+	}
+
+	return;
+}				/* scc_set_sw_alarm */
+
+/*****************************************************************************/
+/* fn scc_monitor_security_failure()                                         */
+/*****************************************************************************/
+scc_return_t scc_monitor_security_failure(void callback_func(void))
+{
+	int i;
+	unsigned long irq_flags;	/* for IRQ save/restore */
+	scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS;
+	int function_stored = FALSE;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Acquire lock of callbacks table.  Could be spin_lock_irq() if this
+	 * routine were just called from base (not interrupt) level
+	 */
+	spin_lock_irqsave(&scc_callbacks_lock, irq_flags);
+
+	/* Search through table looking for empty slot */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		if (scc_callbacks[i] == callback_func) {
+			if (function_stored) {
+				/* Saved duplicate earlier.  Clear this later one. */
+				scc_callbacks[i] = NULL;
+			}
+			/* Exactly one copy is now stored */
+			return_status = SCC_RET_OK;
+			break;
+		} else if (scc_callbacks[i] == NULL && !function_stored) {
+			/* Found open slot.  Save it and remember */
+			scc_callbacks[i] = callback_func;
+			return_status = SCC_RET_OK;
+			function_stored = TRUE;
+		}
+	}
+
+	/* Free the lock */
+	spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags);
+
+	return return_status;
+}				/* scc_monitor_security_failure */
+
+/*****************************************************************************/
+/* fn scc_stop_monitoring_security_failure()                                 */
+/*****************************************************************************/
+void scc_stop_monitoring_security_failure(void callback_func(void))
+{
+	unsigned long irq_flags;	/* for IRQ save/restore */
+	int i;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Acquire lock of callbacks table.  Could be spin_lock_irq() if this
+	 * routine were just called from base (not interrupt) level
+	 */
+	spin_lock_irqsave(&scc_callbacks_lock, irq_flags);
+
+	/* Search every entry of the table for this function */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		if (scc_callbacks[i] == callback_func) {
+			scc_callbacks[i] = NULL;	/* found instance - clear it out */
+			break;
+		}
+	}
+
+	/* Free the lock */
+	spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags);
+
+	return;
+}				/* scc_stop_monitoring_security_failure */
+
+/*****************************************************************************/
+/* fn scc_read_register()                                                    */
+/*****************************************************************************/
+scc_return_t scc_read_register(int register_offset, uint32_t * value)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+	uint32_t smn_status;
+	uint32_t scm_status;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* First layer of protection -- completely unaccessible SCC */
+	if (scc_availability != SCC_STATUS_UNIMPLEMENTED) {
+
+		/* Second layer -- that offset is valid */
+		if (register_offset != SMN_BITBANK_DECREMENT &&	/* write only! */
+		    check_register_offset(register_offset) == SCC_RET_OK) {
+
+			/* Get current status / update local state */
+			smn_status = scc_update_state();
+			scm_status = SCC_READ_REGISTER(SCM_STATUS);
+
+			/*
+			 * Third layer - verify that the register being requested is
+			 * available in the current state of the SCC.
+			 */
+			if ((return_status =
+			     check_register_accessible(register_offset,
+						       smn_status,
+						       scm_status)) ==
+			    SCC_RET_OK) {
+				*value = SCC_READ_REGISTER(register_offset);
+			}
+		}
+	}
+
+	return return_status;
+}				/* scc_read_register */
+
+/*****************************************************************************/
+/* fn scc_write_register()                                                   */
+/*****************************************************************************/
+scc_return_t scc_write_register(int register_offset, uint32_t value)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+	uint32_t smn_status;
+	uint32_t scm_status;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* First layer of protection -- completely unaccessible SCC */
+	if (scc_availability != SCC_STATUS_UNIMPLEMENTED) {
+
+		/* Second layer -- that offset is valid */
+		if (!(register_offset == SCM_STATUS ||	/* These registers are */
+		      register_offset == SCM_CONFIGURATION ||	/*  Read Only */
+		      register_offset == SMN_BIT_COUNT ||
+		      register_offset == SMN_TIMER) &&
+		    check_register_offset(register_offset) == SCC_RET_OK) {
+
+			/* Get current status / update local state */
+			smn_status = scc_update_state();
+			scm_status = SCC_READ_REGISTER(SCM_STATUS);
+
+			/*
+			 * Third layer - verify that the register being requested is
+			 * available in the current state of the SCC.
+			 */
+			if (check_register_accessible
+			    (register_offset, smn_status, scm_status) == 0) {
+				SCC_WRITE_REGISTER(register_offset, value);
+				return_status = SCC_RET_OK;
+			}
+		}
+	}
+
+	return return_status;
+}				/* scc_write_register() */
+
+/******************************************************************************
+ *
+ *  Function Implementations - Internal
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/* fn scc_irq()                                                              */
+/*****************************************************************************/
+/*!
+ * This is the interrupt handler for the SCC.
+ *
+ * This function checks the SMN Status register to see whether it
+ * generated the interrupt, then it checks the SCM Status register to
+ * see whether it needs attention.
+ *
+ * If an SMN Interrupt is active, then the SCC state set to failure, and
+ * #scc_perform_callbacks() is invoked to notify any interested parties.
+ *
+ * The SCM Interrupt should be masked, as this driver uses polling to determine
+ * when the SCM has completed a crypto or zeroing operation.  Therefore, if the
+ * interrupt is active, the driver will just clear the interrupt and (re)mask.
+ *
+ */
+OS_DEV_ISR(scc_irq)
+{
+	uint32_t smn_status;
+	uint32_t scm_status;
+	int handled = 0;	/* assume interrupt isn't from SMN */
+#if defined(USE_SMN_INTERRUPT)
+	int smn_irq = INT_SCC_SMN;	/* SMN interrupt is on a line by itself */
+#elif defined (NO_SMN_INTERRUPT)
+	int smn_irq = -1;	/* not wired to CPU at all */
+#else
+	int smn_irq = INT_SCC_SCM;	/* SMN interrupt shares a line with SCM */
+#endif
+
+	/* Update current state... This will perform callbacks... */
+	smn_status = scc_update_state();
+
+	/* SMN is on its own interrupt line.  Verify the IRQ was triggered
+	 * before clearing the interrupt and marking it handled.  */
+	if ((os_dev_get_irq() == smn_irq) &&
+	    (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) {
+		SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT);
+		handled++;	/* tell kernel that interrupt was handled */
+	}
+
+	/* Check on the health of the SCM */
+	scm_status = SCC_READ_REGISTER(SCM_STATUS);
+
+	/* The driver masks interrupts, so this should never happen. */
+	if (os_dev_get_irq() == INT_SCC_SCM) {
+		/* but if it does, try to prevent it in the future */
+		SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+				   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+				   | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+		handled++;
+	}
+
+	/* Any non-zero value of handled lets kernel know we got something */
+	return IRQ_RETVAL(handled);
+}
+
+/*****************************************************************************/
+/* fn scc_perform_callbacks()                                                */
+/*****************************************************************************/
+/*! Perform callbacks registered by #scc_monitor_security_failure().
+ *
+ *  Make sure callbacks only happen once...  Since there may be some reason why
+ *  the interrupt isn't generated, this routine could be called from base(task)
+ *  level.
+ *
+ *  One at a time, go through #scc_callbacks[] and call any non-null pointers.
+ */
+static void scc_perform_callbacks(void)
+{
+	static int callbacks_performed = 0;
+	unsigned long irq_flags;	/* for IRQ save/restore */
+	int i;
+
+	/* Acquire lock of callbacks table and callbacks_performed flag */
+	spin_lock_irqsave(&scc_callbacks_lock, irq_flags);
+
+	if (!callbacks_performed) {
+		callbacks_performed = 1;
+
+		/* Loop over all of the entries in the table */
+		for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+			/* If not null, ... */
+			if (scc_callbacks[i]) {
+				scc_callbacks[i] ();	/* invoke the callback routine */
+			}
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags);
+
+	return;
+}
+
+/*****************************************************************************/
+/* fn copy_to_scc()                                                          */
+/*****************************************************************************/
+/*!
+ *  Move data from possibly unaligned source and realign for SCC, possibly
+ *  while calculating CRC.
+ *
+ *  Multiple calls can be made to this routine (without intervening calls to
+ *  #copy_from_scc(), as long as the sum total of bytes copied is a multiple of
+ *  four (SCC native word size).
+ *
+ *  @param[in]     from        Location in memory
+ *  @param[out]    to          Location in SCC
+ *  @param[in]     count_bytes Number of bytes to copy
+ *  @param[in,out] crc         Pointer to CRC.  Initial value must be
+ *                             #CRC_CCITT_START if this is the start of
+ *                             message.  Output is the resulting (maybe
+ *                             partial) CRC.  If NULL, no crc is calculated.
+ *
+ * @return  Zero - success.  Non-zero - SCM status bits defining failure.
+ */
+static uint32_t
+copy_to_scc(const uint8_t * from, uint32_t to, unsigned long count_bytes,
+	    uint16_t * crc)
+{
+	int i;
+	uint32_t scm_word;
+	uint16_t current_crc = 0;	/* local copy for fast access */
+	uint32_t status;
+
+	pr_debug("SCC: copying %ld bytes to 0x%0x.\n", count_bytes, to);
+
+	status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS;
+	if (status != 0) {
+		pr_debug
+		    ("SCC copy_to_scc(): Error status detected (before copy):"
+		     " %08x\n", status);
+		/* clear out errors left behind by somebody else */
+		SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status);
+	}
+
+	if (crc) {
+		current_crc = *crc;
+	}
+
+	/* Initialize value being built for SCM.  If we are starting 'clean',
+	 * set it to zero.  Otherwise pick up partial value which had been saved
+	 * earlier. */
+	if (SCC_BYTE_OFFSET(to) == 0) {
+		scm_word = 0;
+	} else {
+		scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(to));	/* recover */
+	}
+
+	/* Now build up SCM words and write them out when each is full */
+	for (i = 0; i < count_bytes; i++) {
+		uint8_t byte = *from++;	/* value from plaintext */
+
+#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE)
+		scm_word = (scm_word << 8) | byte;	/* add byte to SCM word */
+#else
+		scm_word = (byte << 24) | (scm_word >> 8);
+#endif
+		/* now calculate CCITT CRC */
+		if (crc) {
+			CALC_CRC(byte, current_crc);
+		}
+
+		to++;		/* bump location in SCM */
+
+		/* check for full word */
+		if (SCC_BYTE_OFFSET(to) == 0) {
+			SCC_WRITE_REGISTER((uint32_t) (to - 4), scm_word);	/* write it out */
+		}
+	}
+
+	/* If at partial word after previous loop, save it in SCM memory for
+	   next time. */
+	if (SCC_BYTE_OFFSET(to) != 0) {
+		SCC_WRITE_REGISTER(SCC_WORD_PTR(to), scm_word);	/* save */
+	}
+
+	/* Copy CRC back */
+	if (crc) {
+		*crc = current_crc;
+	}
+
+	status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS;
+	if (status != 0) {
+		pr_debug("SCC copy_to_scc(): Error status detected: %08x\n",
+			 status);
+		/* Clear any/all bits. */
+		SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status);
+	}
+	return status;
+}
+
+/*****************************************************************************/
+/* fn copy_from_scc()                                                        */
+/*****************************************************************************/
+/*!
+ *  Move data from aligned 32-bit source and place in (possibly unaligned)
+ *  target, and maybe calculate CRC at the same time.
+ *
+ *  Multiple calls can be made to this routine (without intervening calls to
+ *  #copy_to_scc(), as long as the sum total of bytes copied is be a multiple
+ *  of four.
+ *
+ *  @param[in]     from        Location in SCC
+ *  @param[out]    to          Location in memory
+ *  @param[in]     count_bytes Number of bytes to copy
+ *  @param[in,out] crc         Pointer to CRC.  Initial value must be
+ *                             #CRC_CCITT_START if this is the start of
+ *                             message.  Output is the resulting (maybe
+ *                             partial) CRC.  If NULL, crc is not calculated.
+ *
+ * @return  Zero - success.  Non-zero - SCM status bits defining failure.
+ */
+static uint32_t
+copy_from_scc(const uint32_t from, uint8_t * to, unsigned long count_bytes,
+	      uint16_t * crc)
+{
+	uint32_t running_from = from;
+	uint32_t scm_word;
+	uint16_t current_crc = 0;	/* local copy for fast access */
+	uint32_t status;
+	pr_debug("SCC: copying %ld bytes from 0x%x.\n", count_bytes, from);
+	status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS;
+	if (status != 0) {
+		pr_debug
+		    ("SCC copy_from_scc(): Error status detected (before copy):"
+		     " %08x\n", status);
+		/* clear out errors left behind by somebody else */
+		SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status);
+	}
+
+	if (crc) {
+		current_crc = *crc;
+	}
+
+	/* Read word which is sitting in SCM memory.  Ignore byte offset */
+	scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(running_from));
+
+	/* If necessary, move the 'first' byte into place */
+	if (SCC_BYTE_OFFSET(running_from) != 0) {
+#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE)
+		scm_word <<= 8 * SCC_BYTE_OFFSET(running_from);
+#else
+		scm_word >>= 8 * SCC_BYTE_OFFSET(running_from);
+#endif
+	}
+
+	/* Now build up SCM words and write them out when each is full */
+	while (count_bytes--) {
+		uint8_t byte;	/* value from plaintext */
+
+#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE)
+		byte = (scm_word & 0xff000000) >> 24;	/* pull byte out of SCM word */
+		scm_word <<= 8;	/* shift over to remove the just-pulled byte */
+#else
+		byte = (scm_word & 0xff);
+		scm_word >>= 8;	/* shift over to remove the just-pulled byte */
+#endif
+		*to++ = byte;	/* send byte to memory */
+
+		/* now calculate CRC */
+		if (crc) {
+			CALC_CRC(byte, current_crc);
+		}
+
+		running_from++;
+		/* check for empty word */
+		if (count_bytes && SCC_BYTE_OFFSET(running_from) == 0) {
+			/* read one in */
+			scm_word = SCC_READ_REGISTER((uint32_t) running_from);
+		}
+	}
+
+	if (crc) {
+		*crc = current_crc;
+	}
+
+	status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS;
+	if (status != 0) {
+		pr_debug("SCC copy_from_scc(): Error status detected: %08x\n",
+			 status);
+		/* Clear any/all bits. */
+		SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status);
+	}
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn scc_strip_padding()                                                    */
+/*****************************************************************************/
+/*!
+ *  Remove padding from plaintext.  Search backwards for #SCC_DRIVER_PAD_CHAR,
+ *  verifying that each byte passed over is zero (0).  Maximum number of bytes
+ *  to examine is 8.
+ *
+ *  @param[in]     from           Pointer to byte after end of message
+ *  @param[out]    count_bytes_stripped Number of padding bytes removed by this
+ *                                      function.
+ *
+ *  @return   #SCC_RET_OK if all goes, well, #SCC_RET_FAIL if padding was
+ *            not present.
+*/
+static scc_return_t
+scc_strip_padding(uint8_t * from, unsigned *count_bytes_stripped)
+{
+	int i = SCC_BLOCK_SIZE_BYTES();
+	scc_return_t return_code = SCC_RET_VERIFICATION_FAILED;
+
+	/*
+	 * Search backwards looking for the magic marker.  If it isn't found,
+	 * make sure that a 0 byte is there in its place.  Stop after the maximum
+	 * amount of padding (8 bytes) has been searched);
+	 */
+	while (i-- > 0) {
+		if (*--from == SCC_DRIVER_PAD_CHAR) {
+			*count_bytes_stripped = SCC_BLOCK_SIZE_BYTES() - i;
+			return_code = SCC_RET_OK;
+			break;
+		} else if (*from != 0) {	/* if not marker, check for 0 */
+			pr_debug("SCC: Found non-zero interim pad: 0x%x\n",
+				 *from);
+			break;
+		}
+	}
+
+	return return_code;
+}
+
+/*****************************************************************************/
+/* fn scc_update_state()                                                     */
+/*****************************************************************************/
+/*!
+ * Make certain SCC is still running.
+ *
+ * Side effect is to update #scc_availability and, if the state goes to failed,
+ * run #scc_perform_callbacks().
+ *
+ * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be
+ * in health check state)
+ *
+ * @return Current value of #SMN_STATUS register.
+ */
+static uint32_t scc_update_state(void)
+{
+	uint32_t smn_status_register = SMN_STATE_FAIL;
+	int smn_state;
+
+	/* if FAIL or UNIMPLEMENTED, don't bother */
+	if (scc_availability == SCC_STATUS_CHECKING ||
+	    scc_availability == SCC_STATUS_OK) {
+
+		smn_status_register = SCC_READ_REGISTER(SMN_STATUS);
+		smn_state = smn_status_register & SMN_STATUS_STATE_MASK;
+
+#ifdef SCC_BRINGUP
+		/* If in Health Check while booting, try to 'bringup' to Secure mode */
+		if (scc_availability == SCC_STATUS_CHECKING &&
+		    smn_state == SMN_STATE_HEALTH_CHECK) {
+			/* Code up a simple algorithm for the ASC */
+			SCC_WRITE_REGISTER(SMN_SEQUENCE_START, 0xaaaa);
+			SCC_WRITE_REGISTER(SMN_SEQUENCE_END, 0x5555);
+			SCC_WRITE_REGISTER(SMN_SEQUENCE_CHECK, 0x5555);
+			/* State should be SECURE now */
+			smn_status_register = SCC_READ_REGISTER(SMN_STATUS);
+			smn_state = smn_status_register & SMN_STATUS_STATE_MASK;
+		}
+#endif
+
+		/*
+		 * State should be SECURE or NON_SECURE for operation of the part.  If
+		 * FAIL, mark failed (i.e. limited access to registers).  Any other
+		 * state, mark unimplemented, as the SCC is unuseable.
+		 */
+		if (smn_state == SMN_STATE_SECURE
+		    || smn_state == SMN_STATE_NON_SECURE) {
+			/* Healthy */
+			scc_availability = SCC_STATUS_OK;
+		} else if (smn_state == SMN_STATE_FAIL) {
+			scc_availability = SCC_STATUS_FAILED;	/* uh oh - unhealthy */
+			scc_perform_callbacks();
+			os_printk(KERN_ERR "SCC: SCC went into FAILED mode\n");
+		} else {
+			/* START, ZEROIZE RAM, HEALTH CHECK, or unknown */
+			scc_availability = SCC_STATUS_UNIMPLEMENTED;	/* unuseable */
+			os_printk(KERN_ERR "SCC: SCC declared UNIMPLEMENTED\n");
+		}
+	}
+	/* if availability is initial or ok */
+	return smn_status_register;
+}
+
+/*****************************************************************************/
+/* fn scc_init_ccitt_crc()                                                   */
+/*****************************************************************************/
+/*!
+ * Populate the partial CRC lookup table.
+ *
+ * @return   none
+ *
+ */
+static void scc_init_ccitt_crc(void)
+{
+	int dividend;		/* index for lookup table */
+	uint16_t remainder;	/* partial value for a given dividend */
+	int bit;		/* index into bits of a byte */
+
+	/*
+	 * Compute the remainder of each possible dividend.
+	 */
+	for (dividend = 0; dividend < 256; ++dividend) {
+		/*
+		 * Start with the dividend followed by zeros.
+		 */
+		remainder = dividend << (8);
+
+		/*
+		 * Perform modulo-2 division, a bit at a time.
+		 */
+		for (bit = 8; bit > 0; --bit) {
+			/*
+			 * Try to divide the current data bit.
+			 */
+			if (remainder & 0x8000) {
+				remainder = (remainder << 1) ^ CRC_POLYNOMIAL;
+			} else {
+				remainder = (remainder << 1);
+			}
+		}
+
+		/*
+		 * Store the result into the table.
+		 */
+		scc_crc_lookup_table[dividend] = remainder;
+	}
+
+}				/* scc_init_ccitt_crc() */
+
+/*****************************************************************************/
+/* fn grab_config_values()                                                   */
+/*****************************************************************************/
+/*!
+ * grab_config_values() will read the SCM Configuration and SMN Status
+ * registers and store away version and size information for later use.
+ *
+ * @return The current value of the SMN Status register.
+ */
+static uint32_t scc_grab_config_values(void)
+{
+	uint32_t config_register;
+	uint32_t smn_status_register = SMN_STATE_FAIL;
+
+	if (scc_availability != SCC_STATUS_UNIMPLEMENTED) {
+		/* access the SCC - these are 'safe' registers */
+		config_register = SCC_READ_REGISTER(SCM_CONFIGURATION);
+		pr_debug("SCC Driver: SCM config is 0x%08x\n", config_register);
+
+		/* Get SMN status and update scc_availability */
+		smn_status_register = scc_update_state();
+		pr_debug("SCC Driver: SMN status is 0x%08x\n",
+			 smn_status_register);
+
+		/* save sizes and versions information for later use */
+		scc_configuration.block_size_bytes = (config_register &
+						      SCM_CFG_BLOCK_SIZE_MASK)
+		    >> SCM_CFG_BLOCK_SIZE_SHIFT;
+
+		scc_configuration.red_ram_size_blocks = (config_register &
+							 SCM_CFG_RED_SIZE_MASK)
+		    >> SCM_CFG_RED_SIZE_SHIFT;
+
+		scc_configuration.black_ram_size_blocks = (config_register &
+							   SCM_CFG_BLACK_SIZE_MASK)
+		    >> SCM_CFG_BLACK_SIZE_SHIFT;
+
+		scc_configuration.scm_version = (config_register
+						 & SCM_CFG_VERSION_ID_MASK)
+		    >> SCM_CFG_VERSION_ID_SHIFT;
+
+		scc_configuration.smn_version = (smn_status_register &
+						 SMN_STATUS_VERSION_ID_MASK)
+		    >> SMN_STATUS_VERSION_ID_SHIFT;
+
+		if (scc_configuration.scm_version != SCM_VERSION_1) {
+			scc_availability = SCC_STATUS_UNIMPLEMENTED;	/* Unknown version */
+		}
+
+		scc_memory_size_bytes = (SCC_BLOCK_SIZE_BYTES() *
+					 scc_configuration.
+					 black_ram_size_blocks)
+		    - SCM_NON_RESERVED_OFFSET;
+
+		/* This last is for driver consumption only */
+		scm_highest_memory_address = SCM_BLACK_MEMORY +
+		    (SCC_BLOCK_SIZE_BYTES() *
+		     scc_configuration.black_ram_size_blocks);
+	}
+
+	return smn_status_register;
+}				/* grab_config_values */
+
+/*****************************************************************************/
+/* fn setup_interrupt_handling()                                             */
+/*****************************************************************************/
+/*!
+ * Register the SCM and SMN interrupt handlers.
+ *
+ * Called from #scc_init()
+ *
+ * @return 0 on success
+ */
+static int setup_interrupt_handling(void)
+{
+	int smn_error_code = -1;
+	int scm_error_code = -1;
+
+	/* Disnable SCM interrupts */
+	SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+			   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+			   | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+
+#ifdef USE_SMN_INTERRUPT
+	/* Install interrupt service routine for SMN. */
+	smn_error_code = os_register_interrupt(SCC_DRIVER_NAME,
+					       INT_SCC_SMN, scc_irq);
+	if (smn_error_code != 0) {
+		os_printk
+		    ("SCC Driver: Error installing SMN Interrupt Handler: %d\n",
+		     smn_error_code);
+	} else {
+		smn_irq_set = 1;	/* remember this for cleanup */
+		/* Enable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND,
+				   SMN_COMMAND_CLEAR_INTERRUPT |
+				   SMN_COMMAND_ENABLE_INTERRUPT);
+	}
+#else
+	smn_error_code = 0;	/* no problems... will handle later */
+#endif
+
+	/*
+	 * Install interrupt service routine for SCM (or both together).
+	 */
+	scm_error_code = os_register_interrupt(SCC_DRIVER_NAME,
+					       INT_SCC_SCM, scc_irq);
+	if (scm_error_code != 0) {
+#ifndef MXC
+		os_printk
+		    ("SCC Driver: Error installing SCM Interrupt Handler: %d\n",
+		     scm_error_code);
+#else
+		os_printk
+		    ("SCC Driver: Error installing SCC Interrupt Handler: %d\n",
+		     scm_error_code);
+#endif
+	} else {
+		scm_irq_set = 1;	/* remember this for cleanup */
+#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT)
+		/* Enable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND,
+				   SMN_COMMAND_CLEAR_INTERRUPT |
+				   SMN_COMMAND_ENABLE_INTERRUPT);
+#endif
+	}
+
+	/* Return an error if one was encountered */
+	return scm_error_code ? scm_error_code : smn_error_code;
+}				/* setup_interrupt_handling */
+
+/*****************************************************************************/
+/* fn scc_do_crypto()                                                        */
+/*****************************************************************************/
+/*! Have the SCM perform the crypto function.
+ *
+ * Set up length register, and the store @c scm_control into control register
+ * to kick off the operation.  Wait for completion, gather status, clear
+ * interrupt / status.
+ *
+ * @param byte_count  number of bytes to perform in this operation
+ * @param scm_control Bit values to be set in @c SCM_CONTROL register
+ *
+ * @return 0 on success, value of #SCM_ERROR_STATUS on failure
+ */
+static uint32_t scc_do_crypto(int byte_count, uint32_t scm_control)
+{
+	int block_count = byte_count / SCC_BLOCK_SIZE_BYTES();
+	uint32_t crypto_status;
+
+	/* clear any outstanding flags */
+	SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+			   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+			   | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+
+	/* In length register, 0 means 1, etc. */
+	SCC_WRITE_REGISTER(SCM_LENGTH, block_count - 1);
+
+	/* set modes and kick off the operation */
+	SCC_WRITE_REGISTER(SCM_CONTROL, scm_control);
+
+	scc_wait_completion();
+
+	/* Mask for done and error bits */
+	crypto_status = SCC_READ_REGISTER(SCM_STATUS)
+	    & (SCM_STATUS_CIPHERING_DONE
+	       | SCM_STATUS_LENGTH_ERROR | SCM_STATUS_INTERNAL_ERROR);
+
+	/* Only done bit should be on */
+	if (crypto_status != SCM_STATUS_CIPHERING_DONE) {
+		/* Replace with error status instead */
+		crypto_status = SCC_READ_REGISTER(SCM_ERROR_STATUS);
+		pr_debug("SCM Failure: 0x%x\n", crypto_status);
+		if (crypto_status == 0) {
+			/* That came up 0.  Turn on arbitrary bit to signal error. */
+			crypto_status = SCM_ERR_INTERNAL_ERROR;
+		}
+	} else {
+		crypto_status = 0;
+	}
+
+	pr_debug("SCC: Done waiting.\n");
+
+	/* Clear out any status. */
+	SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL,
+			   SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT
+			   | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS);
+
+	/* And clear any error status */
+	SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0);
+
+	return crypto_status;
+}
+
+/*****************************************************************************/
+/* fn scc_encrypt()                                                          */
+/*****************************************************************************/
+/*!
+ * Perform an encryption on the input.  If @c verify_crc is true, a CRC must be
+ * calculated on the plaintext, and appended, with padding, before computing
+ * the ciphertext.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of plaintext
+ * @param[in]     data_in         Pointer to the plaintext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing ciphertext
+ * @param[in]     add_crc         Flag for computing CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+ */
+static scc_return_t
+scc_encrypt(uint32_t count_in_bytes, const uint8_t * data_in,
+	    uint32_t scm_control,
+	    uint8_t * data_out, int add_crc, unsigned long *count_out_bytes)
+
+{
+	scc_return_t return_code = SCC_RET_FAIL;	/* initialised for failure */
+	uint32_t input_bytes_left = count_in_bytes;	/* local copy */
+	uint32_t output_bytes_copied = 0;	/* running total */
+	uint32_t bytes_to_process;	/* multi-purpose byte counter */
+	uint16_t crc = CRC_CCITT_START;	/* running CRC value */
+	crc_t *crc_ptr = NULL;	/* Reset if CRC required */
+	/* byte address  into SCM RAM */
+	uint32_t scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET;
+	/* free RED RAM */
+	uint32_t scm_bytes_remaining = scc_memory_size_bytes;
+	/* CRC+padding holder */
+	uint8_t padding_buffer[PADDING_BUFFER_MAX_BYTES];
+	unsigned padding_byte_count = 0;	/* Reset if padding required */
+	uint32_t scm_error_status = 0;	/* No known SCM error initially */
+	uint32_t i; 	/* Counter for clear data loop */
+	uint32_t dirty_bytes;	/* Number of bytes of memory used
+					   temporarily during encryption,
+					   which need to be wiped after
+					   completion of the operation. */
+
+	/* Set location of CRC and prepare padding bytes if required */
+	if (add_crc != 0) {
+		crc_ptr = &crc;
+		padding_byte_count = SCC_BLOCK_SIZE_BYTES()
+		    - (count_in_bytes +
+		       CRC_SIZE_BYTES) % SCC_BLOCK_SIZE_BYTES();
+		memcpy(padding_buffer + CRC_SIZE_BYTES, scc_block_padding,
+		       padding_byte_count);
+	}
+
+	/* Process remaining input or padding data */
+	while (input_bytes_left > 0) {
+
+		/* Determine how much work to do this pass */
+		bytes_to_process = (input_bytes_left > scm_bytes_remaining) ?
+		    scm_bytes_remaining : input_bytes_left;
+
+		/* Copy plaintext into SCM RAM, calculating CRC if required */
+		copy_to_scc(data_in, scm_location, bytes_to_process, crc_ptr);
+
+		/* Adjust pointers & counters */
+		input_bytes_left -= bytes_to_process;
+		data_in += bytes_to_process;
+		scm_location += bytes_to_process;
+		scm_bytes_remaining -= bytes_to_process;
+
+		/* Add CRC and padding after the last byte is copied if required */
+		if ((input_bytes_left == 0) && (crc_ptr != NULL)) {
+
+			/* Copy CRC into padding buffer MSB first */
+			padding_buffer[0] = (crc >> 8) & 0xFF;
+			padding_buffer[1] = crc & 0xFF;
+
+			/* Reset pointers and counter */
+			data_in = padding_buffer;
+			input_bytes_left = CRC_SIZE_BYTES + padding_byte_count;
+			crc_ptr = NULL;	/* CRC no longer required */
+
+			/* Go round loop again to copy CRC and padding to SCM */
+			continue;
+		}
+
+		/* if no input and crc_ptr */
+		/* Now have block-sized plaintext in SCM to encrypt */
+		/* Encrypt plaintext; exit loop on error */
+		bytes_to_process = scm_location -
+		    (SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET);
+
+		if (output_bytes_copied + bytes_to_process > *count_out_bytes) {
+			return_code = SCC_RET_INSUFFICIENT_SPACE;
+			scm_error_status = -1;	/* error signal */
+			pr_debug
+			    ("SCC: too many ciphertext bytes for space available\n");
+			break;
+		}
+		pr_debug("SCC: Starting encryption. %x for %d bytes (%p/%p)\n",
+			 scm_control, bytes_to_process,
+			 (void *)SCC_READ_REGISTER(SCM_RED_START),
+			 (void *)SCC_READ_REGISTER(SCM_BLACK_START));
+		scm_error_status = scc_do_crypto(bytes_to_process, scm_control);
+		if (scm_error_status != 0) {
+			break;
+		}
+
+		/* Copy out ciphertext */
+		copy_from_scc(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET,
+			      data_out, bytes_to_process, NULL);
+
+		/* Adjust pointers and counters for next loop */
+		output_bytes_copied += bytes_to_process;
+		data_out += bytes_to_process;
+		scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET;
+		scm_bytes_remaining = scc_memory_size_bytes;
+
+	}			/* input_bytes_left > 0 */
+	/* Clear all red and black memory used during ephemeral encryption */
+	dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ?
+			scc_memory_size_bytes : count_in_bytes;
+
+	for (i = 0; i < dirty_bytes; i += 4) {
+		SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i,
+					   0);
+		SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET +
+					   i, 0);
+	}
+
+	/* If no SCM error, set OK status and save ouput byte count */
+	if (scm_error_status == 0) {
+		return_code = SCC_RET_OK;
+		*count_out_bytes = output_bytes_copied;
+	}
+
+	return return_code;
+}				/* scc_encrypt */
+
+/*****************************************************************************/
+/* fn scc_decrypt()                                                          */
+/*****************************************************************************/
+/*!
+ * Perform a decryption on the input.  If @c verify_crc is true, the last block
+ * (maybe the two last blocks) is special - it should contain a CRC and
+ * padding.  These must be stripped and verified.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of ciphertext
+ * @param[in]     data_in         Pointer to the ciphertext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing plaintext
+ * @param[in]     verify_crc      Flag for running CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+
+ */
+static scc_return_t
+scc_decrypt(uint32_t count_in_bytes, const uint8_t * data_in,
+	    uint32_t scm_control,
+	    uint8_t * data_out, int verify_crc, unsigned long *count_out_bytes)
+{
+	scc_return_t return_code = SCC_RET_FAIL;
+	uint32_t bytes_left = count_in_bytes;	/* local copy */
+	uint32_t bytes_copied = 0;	/* running total of bytes going to user */
+	uint32_t bytes_to_copy = 0;	/* Number in this encryption 'chunk' */
+	uint16_t crc = CRC_CCITT_START;	/* running CRC value */
+	/* next target for	ctext */
+	uint32_t scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET;
+	unsigned padding_byte_count;	/* number of bytes of padding stripped */
+	uint8_t last_two_blocks[2 * SCC_BLOCK_SIZE_BYTES()];	/* temp */
+	uint32_t scm_error_status = 0;	/* register value */
+	uint32_t i; 	/* Counter for clear data loop */
+	uint32_t dirty_bytes;	/* Number of bytes of memory used
+					   temporarily during decryption,
+					   which need to be wiped after
+					   completion of the operation. */
+
+	scm_control |= SCM_DECRYPT_MODE;
+
+	if (verify_crc) {
+		/* Save last two blocks (if there are at least two) of ciphertext for
+		   special treatment. */
+		bytes_left -= SCC_BLOCK_SIZE_BYTES();
+		if (bytes_left >= SCC_BLOCK_SIZE_BYTES()) {
+			bytes_left -= SCC_BLOCK_SIZE_BYTES();
+		}
+	}
+
+	/* Copy ciphertext into SCM BLACK memory */
+	while (bytes_left && scm_error_status == 0) {
+
+		/* Determine how much work to do this pass */
+		if (bytes_left > (scc_memory_size_bytes)) {
+			bytes_to_copy = scc_memory_size_bytes;
+		} else {
+			bytes_to_copy = bytes_left;
+		}
+
+		if (bytes_copied + bytes_to_copy > *count_out_bytes) {
+			scm_error_status = -1;
+			break;
+		}
+		copy_to_scc(data_in, scm_location, bytes_to_copy, NULL);
+		data_in += bytes_to_copy;	/* move pointer */
+
+		pr_debug("SCC: Starting decryption of %d bytes.\n",
+			 bytes_to_copy);
+
+		/*  Do the work, wait for completion */
+		scm_error_status = scc_do_crypto(bytes_to_copy, scm_control);
+
+		copy_from_scc(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET,
+			      data_out, bytes_to_copy, &crc);
+		bytes_copied += bytes_to_copy;
+		data_out += bytes_to_copy;
+		scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET;
+
+		/* Do housekeeping */
+		bytes_left -= bytes_to_copy;
+
+	}			/* while bytes_left */
+
+	/* At this point, either the process is finished, or this is verify mode */
+
+	if (scm_error_status == 0) {
+		if (!verify_crc) {
+			*count_out_bytes = bytes_copied;
+			return_code = SCC_RET_OK;
+		} else {
+			/* Verify mode.  There are one or two blocks of unprocessed
+			 * ciphertext sitting at data_in.  They need to be moved to the
+			 * SCM, decrypted, searched to remove padding, then the plaintext
+			 * copied back to the user (while calculating CRC, of course).
+			 */
+
+			/* Calculate ciphertext still left */
+			bytes_to_copy = count_in_bytes - bytes_copied;
+
+			copy_to_scc(data_in, scm_location, bytes_to_copy, NULL);
+			data_in += bytes_to_copy;	/* move pointer */
+
+			pr_debug("SCC: Finishing decryption (%d bytes).\n",
+				 bytes_to_copy);
+
+			/*  Do the work, wait for completion */
+			scm_error_status =
+			    scc_do_crypto(bytes_to_copy, scm_control);
+
+			if (scm_error_status == 0) {
+				/* Copy decrypted data back from SCM RED memory */
+				copy_from_scc(SCM_RED_MEMORY +
+					      SCM_NON_RESERVED_OFFSET,
+					      last_two_blocks, bytes_to_copy,
+					      NULL);
+
+				/* (Plaintext) + crc + padding should be in temp buffer */
+				if (scc_strip_padding
+				    (last_two_blocks + bytes_to_copy,
+				     &padding_byte_count) == SCC_RET_OK) {
+					bytes_to_copy -=
+					    padding_byte_count + CRC_SIZE_BYTES;
+
+					/* verify enough space in user buffer */
+					if (bytes_copied + bytes_to_copy <=
+					    *count_out_bytes) {
+						int i = 0;
+
+						/* Move out last plaintext and calc CRC */
+						while (i < bytes_to_copy) {
+							CALC_CRC(last_two_blocks
+								 [i], crc);
+							*data_out++ =
+							    last_two_blocks
+							    [i++];
+							bytes_copied++;
+						}
+
+						/* Verify the CRC by running over itself */
+						CALC_CRC(last_two_blocks
+							 [bytes_to_copy], crc);
+						CALC_CRC(last_two_blocks
+							 [bytes_to_copy + 1],
+							 crc);
+						if (crc == 0) {
+							/* Just fine ! */
+							*count_out_bytes =
+							    bytes_copied;
+							return_code =
+							    SCC_RET_OK;
+						} else {
+							return_code =
+							    SCC_RET_VERIFICATION_FAILED;
+							pr_debug
+							    ("SCC:  CRC values are %04x, %02x%02x\n",
+							     crc,
+							     last_two_blocks
+							     [bytes_to_copy],
+							     last_two_blocks
+							     [bytes_to_copy +
+							      1]);
+						}
+					}	/* if space available */
+				} /* if scc_strip_padding... */
+				else {
+					/* bad padding means bad verification */
+					return_code =
+					    SCC_RET_VERIFICATION_FAILED;
+				}
+			}
+			/* scm_error_status == 0 */
+		}		/* verify_crc */
+	}
+
+	/* scm_error_status == 0 */
+	/* Clear all red and black memory used during ephemeral decryption */
+	dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ?
+	    scc_memory_size_bytes : count_in_bytes;
+
+	for (i = 0; i < dirty_bytes; i += 4) {
+		SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i,
+				   0);
+		SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET +
+				   i, 0);
+	}
+	return return_code;
+}				/* scc_decrypt */
+
+/*****************************************************************************/
+/* fn scc_alloc_slot()                                                       */
+/*****************************************************************************/
+/*!
+ * Allocate a key slot to fit the requested size.
+ *
+ * @param value_size_bytes   Size of the key or other secure data
+ * @param owner_id           Value to tie owner to slot
+ * @param[out] slot          Handle to access or deallocate slot
+ *
+ * @return SCC_RET_OK on success, SCC_RET_INSUFFICIENT_SPACE if not slots of
+ *         requested size are available.
+ */
+scc_return_t
+scc_alloc_slot(uint32_t value_size_bytes, uint64_t owner_id, uint32_t * slot)
+{
+	scc_return_t status = SCC_RET_FAIL;
+	unsigned long irq_flags;
+
+	if (scc_availability != SCC_STATUS_OK) {
+		goto out;
+	}
+	/* ACQUIRE LOCK to prevent others from using SCC crypto */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	pr_debug("SCC: Allocating %d-byte slot for 0x%Lx\n",
+		 value_size_bytes, owner_id);
+
+	if ((value_size_bytes != 0) && (value_size_bytes <= SCC_MAX_KEY_SIZE)) {
+		int i;
+
+		for (i = 0; i < SCC_KEY_SLOTS; i++) {
+			if (scc_key_info[i].status == 0) {
+				scc_key_info[i].owner_id = owner_id;
+				scc_key_info[i].length = value_size_bytes;
+				scc_key_info[i].status = 1;	/* assigned! */
+				*slot = i;
+				status = SCC_RET_OK;
+				break;	/* exit 'for' loop */
+			}
+		}
+
+		if (status != SCC_RET_OK) {
+			status = SCC_RET_INSUFFICIENT_SPACE;
+		} else {
+			pr_debug("SCC: Allocated slot %d (0x%Lx)\n", i,
+				 owner_id);
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+      out:
+	return status;
+}
+
+/*****************************************************************************/
+/* fn verify_slot_access()                                                   */
+/*****************************************************************************/
+inline static scc_return_t
+verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len)
+{
+	scc_return_t status = SCC_RET_FAIL;
+	if (scc_availability != SCC_STATUS_OK) {
+		goto out;
+	}
+
+	if ((slot < SCC_KEY_SLOTS) && scc_key_info[slot].status
+	    && (scc_key_info[slot].owner_id == owner_id)
+	    && (access_len <= SCC_KEY_SLOT_SIZE)) {
+		status = SCC_RET_OK;
+		pr_debug("SCC: Verify on slot %d succeeded\n", slot);
+	} else {
+		if (slot >= SCC_KEY_SLOTS) {
+			pr_debug("SCC: Verify on bad slot (%d) failed\n", slot);
+		} else if (scc_key_info[slot].status) {
+			pr_debug("SCC: Verify on slot %d failed (%Lx) \n", slot,
+				 owner_id);
+		} else {
+			pr_debug
+			    ("SCC: Verify on slot %d failed: not allocated\n",
+			     slot);
+		}
+	}
+
+      out:
+	return status;
+}
+
+scc_return_t
+scc_verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len)
+{
+	return verify_slot_access(owner_id, slot, access_len);
+}
+
+/*****************************************************************************/
+/* fn scc_dealloc_slot()                                                     */
+/*****************************************************************************/
+scc_return_t scc_dealloc_slot(uint64_t owner_id, uint32_t slot)
+{
+	scc_return_t status;
+	unsigned long irq_flags;
+	int i;
+
+	/* ACQUIRE LOCK to prevent others from using SCC crypto */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	status = verify_slot_access(owner_id, slot, 0);
+
+	if (status == SCC_RET_OK) {
+		scc_key_info[slot].owner_id = 0;
+		scc_key_info[slot].status = 0;	/* unassign */
+
+		/* clear old info */
+		for (i = 0; i < SCC_KEY_SLOT_SIZE; i += 4) {
+			SCC_WRITE_REGISTER(SCM_RED_MEMORY +
+					   scc_key_info[slot].offset + i, 0);
+			SCC_WRITE_REGISTER(SCM_BLACK_MEMORY +
+					   scc_key_info[slot].offset + i, 0);
+		}
+		pr_debug("SCC: Deallocated slot %d\n", slot);
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn scc_load_slot()                                                        */
+/*****************************************************************************/
+/*!
+ * Load a value into a slot.
+ *
+ * @param owner_id      Value of owner of slot
+ * @param slot          Handle of slot
+ * @param key_data      Data to load into the slot
+ * @param key_length    Length, in bytes, of @c key_data to copy to SCC.
+ *
+ * @return SCC_RET_OK on success.  SCC_RET_FAIL will be returned if slot
+ * specified cannot be accessed for any reason, or SCC_RET_INSUFFICIENT_SPACE
+ * if @c key_length exceeds the size of the slot.
+ */
+scc_return_t
+scc_load_slot(uint64_t owner_id, uint32_t slot, const uint8_t * key_data,
+	      uint32_t key_length)
+{
+	scc_return_t status;
+	unsigned long irq_flags;
+
+	/* ACQUIRE LOCK to prevent others from using SCC crypto */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	status = verify_slot_access(owner_id, slot, key_length);
+	if ((status == SCC_RET_OK) && (key_data != NULL)) {
+		status = SCC_RET_FAIL;	/* reset expectations */
+
+		if (key_length > SCC_KEY_SLOT_SIZE) {
+			pr_debug
+			    ("SCC: scc_load_slot() rejecting key of %d bytes.\n",
+			     key_length);
+			status = SCC_RET_INSUFFICIENT_SPACE;
+		} else {
+			if (copy_to_scc(key_data,
+					SCM_RED_MEMORY +
+					scc_key_info[slot].offset, key_length,
+					NULL)) {
+				pr_debug("SCC: RED copy_to_scc() failed for"
+					 " scc_load_slot()\n");
+			} else {
+				if ((key_length % 4) != 0) {
+					uint32_t zeros = 0;
+
+					/* zero-pad to get remainder bytes in correct place */
+					copy_to_scc((uint8_t *) & zeros,
+						    SCM_RED_MEMORY
+						    +
+						    scc_key_info[slot].offset +
+						    key_length,
+						    4 - (key_length % 4), NULL);
+				}
+				status = SCC_RET_OK;
+			}
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	return status;
+}				/* scc_load_slot */
+
+scc_return_t
+scc_read_slot(uint64_t owner_id, uint32_t slot, uint32_t key_length,
+	      uint8_t * key_data)
+{
+	scc_return_t status;
+	unsigned long irq_flags;
+
+	/* ACQUIRE LOCK to prevent others from using SCC crypto */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	status = verify_slot_access(owner_id, slot, key_length);
+	if ((status == SCC_RET_OK) && (key_data != NULL)) {
+		status = SCC_RET_FAIL;	/* reset expectations */
+
+		if (key_length > SCC_KEY_SLOT_SIZE) {
+			pr_debug
+			    ("SCC: scc_read_slot() rejecting key of %d bytes.\n",
+			     key_length);
+			status = SCC_RET_INSUFFICIENT_SPACE;
+		} else {
+			if (copy_from_scc
+			    (SCM_RED_MEMORY + scc_key_info[slot].offset,
+			     key_data, key_length, NULL)) {
+				pr_debug("SCC: RED copy_from_scc() failed for"
+					 " scc_read_slot()\n");
+			} else {
+				status = SCC_RET_OK;
+			}
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	return status;
+}				/* scc_read_slot */
+
+/*****************************************************************************/
+/* fn scc_encrypt_slot()                                                     */
+/*****************************************************************************/
+/*!
+ * Encrypt the key data stored in a slot.
+ *
+ * @param owner_id      Value of owner of slot
+ * @param slot          Handle of slot
+ * @param length        Length, in bytes, of @c black_data
+ * @param black_data    Location to store result of encrypting RED data in slot
+ *
+ * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be
+ *         accessed for any reason.
+ */
+scc_return_t scc_encrypt_slot(uint64_t owner_id, uint32_t slot,
+			      uint32_t length, uint8_t * black_data)
+{
+	unsigned long irq_flags;
+	scc_return_t status;
+	uint32_t crypto_status;
+	uint32_t slot_offset =
+	    scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES();
+
+	/* ACQUIRE LOCK to prevent others from using crypto or releasing slot */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	status = verify_slot_access(owner_id, slot, length);
+	if (status == SCC_RET_OK) {
+		SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset);
+		SCC_WRITE_REGISTER(SCM_RED_START, slot_offset);
+
+		/* Use OwnerID as CBC IV to tie Owner to data */
+		SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id);
+		SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1,
+				   *(((uint32_t *) & owner_id) + 1));
+
+		/* Set modes and kick off the encryption */
+		crypto_status = scc_do_crypto(length,
+					      SCM_CONTROL_START_CIPHER |
+					      SCM_CBC_MODE);
+
+		if (crypto_status != 0) {
+			pr_debug("SCM encrypt red crypto failure: 0x%x\n",
+				 crypto_status);
+		} else {
+
+			/* Give blob back to caller */
+			if (!copy_from_scc
+			    (SCM_BLACK_MEMORY + scc_key_info[slot].offset,
+			     black_data, length, NULL)) {
+				status = SCC_RET_OK;
+				pr_debug("SCC: Encrypted slot %d\n", slot);
+			}
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn scc_decrypt_slot()                                                     */
+/*****************************************************************************/
+/*!
+ * Decrypt some black data and leave result in the slot.
+ *
+ * @param owner_id      Value of owner of slot
+ * @param slot          Handle of slot
+ * @param length        Length, in bytes, of @c black_data
+ * @param black_data    Location of data to dencrypt and store in slot
+ *
+ * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be
+ *         accessed for any reason.
+ */
+scc_return_t scc_decrypt_slot(uint64_t owner_id, uint32_t slot,
+			      uint32_t length, const uint8_t * black_data)
+{
+	unsigned long irq_flags;
+	scc_return_t status;
+	uint32_t crypto_status;
+	uint32_t slot_offset =
+	    scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES();
+
+	/* ACQUIRE LOCK to prevent others from using crypto or releasing slot */
+	spin_lock_irqsave(&scc_crypto_lock, irq_flags);
+
+	status = verify_slot_access(owner_id, slot, length);
+	if (status == SCC_RET_OK) {
+		status = SCC_RET_FAIL;	/* reset expectations */
+
+		/* Place black key in to BLACK RAM and set up the SCC */
+		copy_to_scc(black_data,
+			    SCM_BLACK_MEMORY + scc_key_info[slot].offset,
+			    length, NULL);
+
+		SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset);
+		SCC_WRITE_REGISTER(SCM_RED_START, slot_offset);
+
+		/* Use OwnerID as CBC IV to tie Owner to data */
+		SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id);
+		SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1,
+				   *(((uint32_t *) & owner_id) + 1));
+
+		/* Set modes and kick off the decryption */
+		crypto_status = scc_do_crypto(length,
+					      SCM_CONTROL_START_CIPHER
+					      | SCM_CBC_MODE |
+					      SCM_DECRYPT_MODE);
+
+		if (crypto_status != 0) {
+			pr_debug("SCM decrypt black crypto failure: 0x%x\n",
+				 crypto_status);
+		} else {
+			status = SCC_RET_OK;
+		}
+	}
+
+	spin_unlock_irqrestore(&scc_crypto_lock, irq_flags);
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn scc_get_slot_info()                                                    */
+/*****************************************************************************/
+/*!
+ * Determine address and value length for a give slot.
+ *
+ * @param owner_id      Value of owner of slot
+ * @param slot          Handle of slot
+ * @param address       Location to store kernel address of slot data
+ * @param value_size_bytes Location to store allocated length of data in slot.
+ *                         May be NULL if value is not needed by caller.
+ * @param slot_size_bytes  Location to store max length data in slot
+ *                         May be NULL if value is not needed by caller.
+ *
+ * @return SCC_RET_OK or error indication
+ */
+scc_return_t
+scc_get_slot_info(uint64_t owner_id, uint32_t slot, uint32_t * address,
+		  uint32_t * value_size_bytes, uint32_t * slot_size_bytes)
+{
+	scc_return_t status = verify_slot_access(owner_id, slot, 0);
+
+	if (status == SCC_RET_OK) {
+		*address =
+		    SCC_BASE + SCM_RED_MEMORY + scc_key_info[slot].offset;
+		if (value_size_bytes != NULL) {
+			*value_size_bytes = scc_key_info[slot].length;
+		}
+		if (slot_size_bytes != NULL) {
+			*slot_size_bytes = SCC_KEY_SLOT_SIZE;
+		}
+	}
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn scc_wait_completion()                                                  */
+/*****************************************************************************/
+/*!
+ * Poll looking for end-of-cipher indication. Only used
+ * if @c SCC_SCM_SLEEP is not defined.
+ *
+ * @internal
+ *
+ * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all
+ * the way up to five sets of spins for 1024 bytes.  (8- and 16-byte functions
+ * are done when we first look.  Zeroizing takes one pass around.
+ */
+static void scc_wait_completion(void)
+{
+	int i = 0;
+
+	/* check for completion by polling */
+	while (!is_cipher_done() && (i++ < SCC_CIPHER_MAX_POLL_COUNT)) {
+		udelay(10);
+	}
+	pr_debug("SCC: Polled DONE %d times\n", i);
+}				/* scc_wait_completion() */
+
+/*****************************************************************************/
+/* fn is_cipher_done()                                                       */
+/*****************************************************************************/
+/*!
+ * This function returns non-zero if SCM Status register indicates
+ * that a cipher has terminated or some other interrupt-generating
+ * condition has occurred.
+ */
+static int is_cipher_done(void)
+{
+	register uint32_t scm_status;
+	register int cipher_done;
+
+	scm_status = SCC_READ_REGISTER(SCM_STATUS);
+
+	/*
+	 * Done when 'SCM is currently performing a function' bits are zero
+	 */
+	cipher_done = !(scm_status & (SCM_STATUS_ZEROIZING |
+				      SCM_STATUS_CIPHERING));
+
+	return cipher_done;
+}				/* is_cipher_done() */
+
+/*****************************************************************************/
+/* fn offset_within_smn()                                                    */
+/*****************************************************************************/
+/*!
+ *  Check that the offset is with the bounds of the SMN register set.
+ *
+ *  @param[in]  register_offset    register offset of SMN.
+ *
+ *  @return   1 if true, 0 if false (not within SMN)
+ */
+static inline int offset_within_smn(uint32_t register_offset)
+{
+	return register_offset >= SMN_STATUS && register_offset <= SMN_TIMER;
+}
+
+/*****************************************************************************/
+/* fn offset_within_scm()                                                    */
+/*****************************************************************************/
+/*!
+ *  Check that the offset is with the bounds of the SCM register set.
+ *
+ *  @param[in]  register_offset    Register offset of SCM
+ *
+ *  @return   1 if true, 0 if false (not within SCM)
+ */
+static inline int offset_within_scm(uint32_t register_offset)
+{
+	return (register_offset >= SCM_RED_START)
+	    && (register_offset < scm_highest_memory_address);
+	/* Although this would cause trouble for zeroize testing, this change would
+	 * close a security whole which currently allows any kernel program to access
+	 * any location in RED RAM.  Perhaps enforce in non-SCC_DEBUG compiles?
+	 && (register_offset <= SCM_INIT_VECTOR_1); */
+}
+
+/*****************************************************************************/
+/* fn check_register_accessible()                                            */
+/*****************************************************************************/
+/*!
+ *  Given the current SCM and SMN status, verify that access to the requested
+ *  register should be OK.
+ *
+ *  @param[in]   register_offset  register offset within SCC
+ *  @param[in]   smn_status  recent value from #SMN_STATUS
+ *  @param[in]   scm_status  recent value from #SCM_STATUS
+ *
+ *  @return   #SCC_RET_OK if ok, #SCC_RET_FAIL if not
+ */
+static scc_return_t
+check_register_accessible(uint32_t register_offset, uint32_t smn_status,
+			  uint32_t scm_status)
+{
+	int error_code = SCC_RET_FAIL;
+
+	/* Verify that the register offset passed in is not among the verboten set
+	 * if the SMN is in Fail mode.
+	 */
+	if (offset_within_smn(register_offset)) {
+		if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) {
+			if (!((register_offset == SMN_STATUS) ||
+			      (register_offset == SMN_COMMAND) ||
+			      (register_offset == SMN_DEBUG_DETECT_STAT))) {
+				pr_debug
+				    ("SCC Driver: Note: Security State is in FAIL state.\n");
+			} /* register not a safe one */
+			else {
+				/* SMN is in  FAIL, but register is a safe one */
+				error_code = SCC_RET_OK;
+			}
+		} /* State is FAIL */
+		else {
+			/* State is not fail.  All registers accessible. */
+			error_code = SCC_RET_OK;
+		}
+	}
+	/* offset within SMN */
+	/*  Not SCM register.  Check for SCM busy. */
+	else if (offset_within_scm(register_offset)) {
+		/* This is the 'cannot access' condition in the SCM */
+		if ((scm_status & SCM_STATUS_BUSY)
+		    /* these are always available  - rest fail on busy */
+		    && !((register_offset == SCM_STATUS) ||
+			 (register_offset == SCM_ERROR_STATUS) ||
+			 (register_offset == SCM_INTERRUPT_CTRL) ||
+			 (register_offset == SCM_CONFIGURATION))) {
+			pr_debug
+			    ("SCC Driver: Note: Secure Memory is in BUSY state.\n");
+		} /* status is busy & register inaccessible */
+		else {
+			error_code = SCC_RET_OK;
+		}
+	}
+	/* offset within SCM */
+	return error_code;
+
+}				/* check_register_accessible() */
+
+/*****************************************************************************/
+/* fn check_register_offset()                                                */
+/*****************************************************************************/
+/*!
+ *  Check that the offset is with the bounds of the SCC register set.
+ *
+ *  @param[in]  register_offset    register offset of SMN.
+ *
+ * #SCC_RET_OK if ok, #SCC_RET_FAIL if not
+ */
+static scc_return_t check_register_offset(uint32_t register_offset)
+{
+	int return_value = SCC_RET_FAIL;
+
+	/* Is it valid word offset ? */
+	if (SCC_BYTE_OFFSET(register_offset) == 0) {
+		/* Yes. Is register within SCM? */
+		if (offset_within_scm(register_offset)) {
+			return_value = SCC_RET_OK;	/* yes, all ok */
+		}
+		/* Not in SCM.  Now look within the SMN */
+		else if (offset_within_smn(register_offset)) {
+			return_value = SCC_RET_OK;	/* yes, all ok */
+		}
+	}
+
+	return return_value;
+}
+
+#ifdef SCC_REGISTER_DEBUG
+
+/*****************************************************************************/
+/* fn dbg_scc_read_register()                                                */
+/*****************************************************************************/
+/*!
+ * Noisily read a 32-bit value to an SCC register.
+ * @param offset        The address of the register to read.
+ *
+ * @return  The register value
+ * */
+static uint32_t dbg_scc_read_register(uint32_t offset)
+{
+	uint32_t value;
+
+	value = readl(scc_base + offset);
+
+#ifndef SCC_RAM_DEBUG		/* print no RAM references */
+	if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) {
+#endif
+		pr_debug("SCC RD: 0x%4x : 0x%08x\n", offset, value);
+#ifndef SCC_RAM_DEBUG
+	}
+#endif
+
+	return value;
+}
+
+/*****************************************************************************/
+/* fn dbg_scc_write_register()                                               */
+/*****************************************************************************/
+/*
+ * Noisily read a 32-bit value to an SCC register.
+ * @param offset        The address of the register to written.
+ *
+ * @param value         The new register value
+ */
+static void dbg_scc_write_register(uint32_t offset, uint32_t value)
+{
+
+#ifndef SCC_RAM_DEBUG		/* print no RAM references */
+	if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) {
+#endif
+		pr_debug("SCC WR: 0x%4x : 0x%08x\n", offset, value);
+#ifndef SCC_RAM_DEBUG
+	}
+#endif
+
+	(void)writel(value, scc_base + offset);
+}
+
+#endif				/* SCC_REGISTER_DEBUG */
diff --git a/drivers/mxc/security/mxc_scc_internals.h b/drivers/mxc/security/mxc_scc_internals.h
new file mode 100644
index 000000000000..ffdbcf62514a
--- /dev/null
+++ b/drivers/mxc/security/mxc_scc_internals.h
@@ -0,0 +1,498 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MXC_SCC_INTERNALS_H__
+#define __MXC_SCC_INTERNALS_H__
+
+/*!
+ * @file mxc_scc_internals.h
+ *
+ * @brief This is intended to be the file which contains most or all of the code or
+ *  changes need to port the driver.  It also includes other definitions needed
+ *  by the driver.
+ *
+ *  This header file should only ever be included by scc_driver.c
+ *
+ *  Compile-time flags minimally needed:
+ *
+ *  @li Some sort of platform flag.
+ *  @li Some start-of-SCC consideration, such as SCC_BASE_ADDR
+ *
+ *  Some changes which could be made when porting this driver:
+ *  #SCC_SPIN_COUNT
+ *
+ * @ingroup MXCSCC
+ */
+#if 0
+#include <linux/version.h>	/* Current version Linux kernel */
+#include <linux/module.h>	/* Basic support for loadable modules,
+				   printk */
+#include <linux/init.h>		/* module_init, module_exit */
+#include <linux/kernel.h>	/* General kernel system calls */
+#include <linux/sched.h>	/* for interrupt.h */
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>	/* IRQ / interrupt definitions */
+#include <linux/io.h>		/* ioremap() */
+#endif
+#include <linux/mxc_scc_driver.h>
+
+/* Get handle on certain per-platform symbols */
+#ifdef TAHITI
+#include <asm/arch/mx2.h>
+
+/*
+ * Mark the SCC as always there... as Tahiti is not officially supported by
+ * driver.  Porting opportunity.
+ */
+#define SCC_ENABLED() (1)
+
+#elif defined(MXC)
+
+#include <mach/iim.h>
+#include <mach/mxc_scc.h>
+
+#ifdef SCC_FUSE
+
+/*
+ * This macro is used to determine whether the SCC is enabled/available
+ * on the platform.  This macro may need to be ported.
+ */
+#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0)
+
+#else
+
+#define SCC_ENABLED() (1)
+
+#endif
+
+#else				/* neither TAHITI nor MXC */
+
+#error Do not understand target architecture
+
+#endif				/* TAHITI */
+
+/* Temporarily define compile-time flags to make Doxygen happy. */
+#ifdef DOXYGEN_HACK
+/*! @addtogroup scccompileflags */
+/*! @{ */
+
+/*! @def NO_SMN_INTERRUPT
+ * The SMN interrupt is not wired to the CPU at all.
+ */
+#define NO_SMN_INTERRUPT
+
+/*!
+ * Register an interrupt handler for the SMN as well as
+ * the SCM.  In some implementations, the SMN is not connected at all (see
+ * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the
+ * SCM.  When defining this flag, the SMN interrupt should be on a separate
+ * line from the SCM interrupt.
+ */
+
+#define USE_SMN_INTERRUPT
+
+/*!
+ * Turn on generation of run-time operational, debug, and error messages
+ */
+#define SCC_DEBUG
+
+/*!
+ * Turn on generation of run-time logging of access to the SCM and SMN
+ * registers.
+ */
+#define SCC_REGISTER_DEBUG
+
+/*!
+ * Turn on generation of run-time logging of access to the SCM Red and
+ * Black memories.  Will only work if #SCC_REGISTER_DEBUG is also defined.
+ */
+#define SCC_RAM_DEBUG
+
+/*!
+ *  If the driver finds the SCC in HEALTH_CHECK state, go ahead and
+ *  run a quick ASC to bring it to SECURE state.
+ */
+#define SCC_BRINGUP
+
+/*!
+ * Expected to come from platform header files or compile command line.
+ * This symbol must be the address of the SCC
+ */
+#define SCC_BASE
+
+/*!
+ *  This must be the interrupt line number of the SCM interrupt.
+ */
+#define INT_SCM
+
+/*!
+ *  if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of
+ *  the SMN interrupt.
+ */
+#define INT_SMN
+
+/*!
+ * Define the number of Stored Keys which the SCC driver will make available.
+ * Value shall be from 0 to 20.  Default is zero (0).
+ */
+#define SCC_KEY_SLOTS
+
+/*!
+ * Make sure that this flag is defined if compiling for a Little-Endian
+ * platform.  Linux Kernel builds provide this flag.
+ */
+#define __LITTLE_ENDIAN
+
+/*!
+ * Make sure that this flag is defined if compiling for a Big-Endian platform.
+ * Linux Kernel builds provide this flag.
+ */
+#define __BIG_ENDIAN
+
+/*!
+ * Read a 32-bit register value from a 'peripheral'.  Standard Linux/Unix
+ * macro.
+ *
+ * @param offset   Bus address of register to be read
+ *
+ * @return The value of the register
+ */
+#define readl(offset)
+
+/*!
+ * Write a 32-bit value to a register in a 'peripheral'.  Standard Linux/Unix
+ * macro.
+ *
+ * @param value    The 32-bit value to store
+ * @param offset   Bus address of register to be written
+ *
+ * return (none)
+ */
+#define writel(value,offset)
+
+	   /*! @} *//* end group scccompileflags */
+
+#endif				/* DOXYGEN_HACK */
+
+/*!
+ * Define the number of Stored Keys which the SCC driver will make available.
+ * Value shall be from 0 to 20.  Default is zero (0).
+ */
+#define SCC_KEY_SLOTS 20
+
+#ifndef SCC_KEY_SLOTS
+#define SCC_KEY_SLOTS 0
+
+#else
+
+#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20)
+#error Bad value for SCC_KEY_SLOTS
+#endif
+
+/*!
+ * Maximum length of key/secret value which can be stored in SCC.
+ */
+#define SCC_MAX_KEY_SIZE 32
+
+/*!
+ * This is the size, in bytes, of each key slot, and therefore the maximum size
+ * of the wrapped key.
+ */
+#define SCC_KEY_SLOT_SIZE 32
+
+/*!
+ *  This is the offset into each RAM of the base of the area which is
+ *  not used for Stored Keys.
+ */
+#define SCM_NON_RESERVED_OFFSET (SCC_KEY_SLOTS * SCC_KEY_SLOT_SIZE)
+
+#endif
+
+/* These come for free with Linux, but may need to be set in a port. */
+#ifndef __BIG_ENDIAN
+#ifndef __LITTLE_ENDIAN
+#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined
+#endif
+#else
+#ifdef __LITTLE_ENDIAN
+#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined
+#endif
+#endif
+
+#ifndef SCC_CALLBACK_SIZE
+/*! The number of function pointers which can be stored in #scc_callbacks.
+ *  Defaults to 4, can be overridden with compile-line argument.
+ */
+#define SCC_CALLBACK_SIZE 4
+#endif
+
+/*! Initial CRC value for CCITT-CRC calculation. */
+#define CRC_CCITT_START 0xFFFF
+
+#ifdef TAHITI
+
+/*!
+ * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of
+ * registers are swapped in place.
+ */
+#define SCC_BASE       SMN_BASE_ADDR
+
+/*! The interrupt number for the SCC (SCM only!) on Tahiti */
+#define INT_SCC_SCM       62
+
+/*! Tahiti does not have the SMN interrupt wired to the CPU.  */
+#define NO_SMN_INTERRUPT
+
+#endif				/* TAHITI */
+
+/*! Number of times to spin between polling of SCC while waiting for cipher
+ *  or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */
+#define SCC_SPIN_COUNT 1000
+
+/*! Number of times to polling SCC while waiting for cipher
+ *  or zeroizing function to complete.  See also #SCC_SPIN_COUNT.  */
+#define SCC_CIPHER_MAX_POLL_COUNT 100
+
+/*!
+ * @def SCC_READ_REGISTER
+ * Read a 32-bit value from an SCC register.  Macro which depends upon
+ * #scc_base.  Linux readl()/writel() macros operate on 32-bit quantities, as
+ * do SCC register reads/writes.
+ *
+ * @param     offset  Register offset within SCC.
+ *
+ * @return    The value from the SCC's register.
+ */
+#ifndef SCC_REGISTER_DEBUG
+#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset))
+#else
+#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset)
+#endif
+
+/*!
+ * Write a 32-bit value to an SCC register.  Macro depends upon #scc_base.
+ * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC
+ * register reads/writes.
+ *
+ * @param   offset  Register offset within SCC.
+ * @param   value   32-bit value to store into the register
+ *
+ * @return   (void)
+ */
+#ifndef SCC_REGISTER_DEBUG
+#define SCC_WRITE_REGISTER(offset,value) (void)__raw_writel(value, scc_base+(offset))
+#else
+#define SCC_WRITE_REGISTER(offset,value) dbg_scc_write_register(offset, value)
+#endif
+
+/*!
+ * Calculates the byte offset into a word
+ *  @param   bp  The byte (char*) pointer
+ *  @return      The offset (0, 1, 2, or 3)
+ */
+#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t))
+
+/*!
+ * Converts (by rounding down) a byte pointer into a word pointer
+ *  @param  bp  The byte (char*) pointer
+ *  @return     The word (uint32_t) as though it were an aligned (uint32_t*)
+ */
+#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1))
+
+/*!
+ * Determine number of bytes in an SCC block
+ *
+ * @return Bytes / block
+ */
+#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes
+
+/*!
+ * Maximum number of additional bytes which may be added in CRC+padding mode.
+ */
+#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding))
+
+/*!
+ *  Shorthand (clearer, anyway) for number of bytes in a CRC.
+ */
+#define CRC_SIZE_BYTES (sizeof(crc_t))
+
+/*!
+ * The polynomial used in CCITT-CRC calculation
+ */
+#define CRC_POLYNOMIAL 0x1021
+
+/*!
+ * Calculate CRC on one byte of data
+ *
+ * @param[in,out] running_crc  A value of type crc_t where CRC is kept. This
+ *                             must be an rvalue and an lvalue.
+ * @param[in]     byte_value   The byte (uint8_t, char) to be put in the CRC
+ *
+ * @return      none
+ */
+#define CALC_CRC(byte_value,running_crc)  {                                  \
+    uint8_t data;                                                            \
+    data = (0xff&(byte_value)) ^ (running_crc >> 8);                         \
+    running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8);           \
+}
+
+/*! Value of 'beginning of padding' marker in driver-provided padding */
+#define SCC_DRIVER_PAD_CHAR  0x80
+
+/*! Name of the driver.  Used (on Linux, anyway) when registering interrupts */
+#define SCC_DRIVER_NAME "scc"
+
+/* Port -- these symbols are defined in Linux 2.6 and later.  They are defined
+ * here for backwards compatibility because this started life as a 2.4
+ * driver, and as a guide to portation to other platforms.
+ */
+
+#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+
+#define irqreturn_t void	/* Return type of an interrupt handler */
+
+#define IRQ_HANDLED		/* Would be '1' for handled -- as in return IRQ_HANDLED; */
+
+#define IRQ_NONE		/* would be '0' for not handled -- as in return IRQ_NONE; */
+
+#define IRQ_RETVAL(x)		/* Return x==0 (not handled) or non-zero (handled) */
+
+#endif				/* LINUX earlier than 2.5 */
+
+/* These are nice to have around */
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+/*! Provide a typedef for the CRC which can be used in encrypt/decrypt */
+typedef uint16_t crc_t;
+
+/*! Gives high-level view of state of the SCC */
+enum scc_status {
+	SCC_STATUS_INITIAL,	/*!< State of driver before ever checking */
+	SCC_STATUS_CHECKING,	/*!< Transient state while driver loading  */
+	SCC_STATUS_UNIMPLEMENTED,	/*!< SCC is non-existent or unuseable  */
+	SCC_STATUS_OK,		/*!< SCC is in Secure or Default state  */
+	SCC_STATUS_FAILED	/*!< In Failed state */
+};
+
+/*!
+ * Information about a key slot.
+ */
+struct scc_key_slot {
+	uint64_t owner_id;	/*!< Access control value. */
+	uint32_t length;	/*!< Length of value in slot. */
+	uint32_t offset;	/*!< Offset of value from start of each RAM. */
+	uint32_t status;	/*!< 0 = unassigned, 1 = assigned. */
+};
+
+/* Forward-declare a number routines which are not part of user api */
+static int scc_init(void);
+static void scc_cleanup(void);
+
+/* Forward defines of internal functions */
+OS_DEV_ISR(scc_irq);
+/*! Perform callbacks registered by #scc_monitor_security_failure().
+ *
+ *  Make sure callbacks only happen once...  Since there may be some reason why
+ *  the interrupt isn't generated, this routine could be called from base(task)
+ *  level.
+ *
+ *  One at a time, go through #scc_callbacks[] and call any non-null pointers.
+ */
+static void scc_perform_callbacks(void);
+static uint32_t copy_to_scc(const uint8_t * from, uint32_t to,
+			    unsigned long count_bytes, uint16_t * crc);
+static uint32_t copy_from_scc(const uint32_t from, uint8_t * to,
+			      unsigned long count_bytes, uint16_t * crc);
+static scc_return_t scc_strip_padding(uint8_t * from,
+				      unsigned *count_bytes_stripped);
+static uint32_t scc_update_state(void);
+static void scc_init_ccitt_crc(void);
+static uint32_t scc_grab_config_values(void);
+static int setup_interrupt_handling(void);
+/*!
+ * Perform an encryption on the input.  If @c verify_crc is true, a CRC must be
+ * calculated on the plaintext, and appended, with padding, before computing
+ * the ciphertext.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of plaintext
+ * @param[in]     data_in         Pointer to the plaintext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing ciphertext
+ * @param[in]     add_crc         Flag for computing CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+ */
+static scc_return_t scc_encrypt(uint32_t count_in_bytes,
+				const uint8_t * data_in,
+				uint32_t scm_control, uint8_t * data_out,
+				int add_crc, unsigned long *count_out_bytes);
+
+/*!
+ * Perform a decryption on the input.  If @c verify_crc is true, the last block
+ * (maybe the two last blocks) is special - it should contain a CRC and
+ * padding.  These must be stripped and verified.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of ciphertext
+ * @param[in]     data_in         Pointer to the ciphertext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing plaintext
+ * @param[in]     verify_crc      Flag for running CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+
+ */
+static scc_return_t scc_decrypt(uint32_t count_in_bytes,
+				const uint8_t * data_in,
+				uint32_t scm_control, uint8_t * data_out,
+				int verify_crc, unsigned long *count_out_bytes);
+
+static void scc_wait_completion(void);
+static int is_cipher_done(void);
+static scc_return_t check_register_accessible(uint32_t offset,
+					      uint32_t smn_status,
+					      uint32_t scm_status);
+static scc_return_t check_register_offset(uint32_t offset);
+
+#ifdef SCC_REGISTER_DEBUG
+static uint32_t dbg_scc_read_register(uint32_t offset);
+static void dbg_scc_write_register(uint32_t offset, uint32_t value);
+#endif
+
+/* For Linux kernel, export the API functions to other kernel modules */
+EXPORT_SYMBOL(scc_get_configuration);
+EXPORT_SYMBOL(scc_zeroize_memories);
+EXPORT_SYMBOL(scc_crypt);
+EXPORT_SYMBOL(scc_set_sw_alarm);
+EXPORT_SYMBOL(scc_monitor_security_failure);
+EXPORT_SYMBOL(scc_stop_monitoring_security_failure);
+EXPORT_SYMBOL(scc_read_register);
+EXPORT_SYMBOL(scc_write_register);
+EXPORT_SYMBOL(scc_alloc_slot);
+EXPORT_SYMBOL(scc_dealloc_slot);
+EXPORT_SYMBOL(scc_load_slot);
+EXPORT_SYMBOL(scc_encrypt_slot);
+EXPORT_SYMBOL(scc_decrypt_slot);
+EXPORT_SYMBOL(scc_get_slot_info);
+
+/* Tell Linux where to invoke driver at boot/module load time */
+module_init(scc_init);
+/* Tell Linux where to invoke driver on module unload  */
+module_exit(scc_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)");
+
+#endif				/* __MXC_SCC_INTERNALS_H__ */
diff --git a/drivers/mxc/security/rng/Makefile b/drivers/mxc/security/rng/Makefile
new file mode 100644
index 000000000000..7d3332e2e675
--- /dev/null
+++ b/drivers/mxc/security/rng/Makefile
@@ -0,0 +1,35 @@
+# Makefile for the Linux RNG Driver
+#
+# This makefile works within a kernel driver tree
+
+ # Makefile for rng_driver
+
+
+# Possible configurable paramters
+CFG_RNG += -DRNGA_MAX_REQUEST_SIZE=32
+
+#DBG_RNGA = -DRNGA_DEBUG
+#DBG_RNGA += -DRNGA_REGISTER_DEBUG
+#DBG_RNGA += -DRNGA_ENTROPY_DEBUG
+
+EXTRA_CFLAGS = -DLINUX_KERNEL $(CFG_RNG) $(DBG_RNG)
+
+
+ifeq ($(CONFIG_MXC_RNG_TEST_DRIVER),y)
+EXTRA_CFLAGS += -DRNG_REGISTER_PEEK_POKE
+endif
+ifeq ($(CONFIG_RNG_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
+
+
+EXTRA_CFLAGS += -Idrivers/mxc/security/rng/include -Idrivers/mxc/security/sahara2/include
+
+obj-$(CONFIG_MXC_SECURITY_RNG)	+= shw.o
+#shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o
+shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o  \
+            fsl_shw_sym.o  fsl_shw_wrap.o shw_dryice.o  des_key.o           \
+            shw_hash.o  shw_hmac.o
+
+obj-$(CONFIG_MXC_SECURITY_RNG)	+= rng.o
+rng-objs :=	rng_driver.o
diff --git a/drivers/mxc/security/rng/des_key.c b/drivers/mxc/security/rng/des_key.c
new file mode 100644
index 000000000000..62ff9b89eb3e
--- /dev/null
+++ b/drivers/mxc/security/rng/des_key.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/*!
+ * @file des_key.c
+ *
+ * This file implements the function #fsl_shw_permute1_bytes().
+ *
+ * The code was lifted from crypto++ v5.5.2, which is public domain code.  The
+ * code to handle words instead of bytes was extensively modified from the byte
+ * version and then converted to handle one to three keys at once.
+ *
+ */
+
+#include "shw_driver.h"
+#ifdef DIAG_SECURITY_FUNC
+#include "apihelp.h"
+#endif
+
+#ifndef __KERNEL__
+#include <asm/types.h>
+#include <linux/byteorder/little_endian.h>	/* or whichever is proper for target arch */
+#endif
+
+#ifdef DEBUG
+#undef DEBUG			/* TEMPORARY */
+#endif
+
+#if defined(DEBUG) || defined(SELF_TEST)
+static void DUMP_BYTES(const char *label, const uint8_t * data, int len)
+{
+	int i;
+
+	printf("%s: ", label);
+	for (i = 0; i < len; i++) {
+		printf("%02X", data[i]);
+		if ((i % 8 == 0) && (i != 0)) {
+			printf("_");	/* key separator */
+		}
+	}
+	printf("\n");
+}
+
+static void DUMP_WORDS(const char *label, const uint32_t * data, int len)
+{
+	int i, j;
+
+	printf("%s: ", label);
+	/* Dump the words in reverse order, so that they are intelligible */
+	for (i = len - 1; i >= 0; i--) {
+		for (j = 3; j >= 0; j--) {
+			uint32_t word = data[i];
+			printf("%02X", (word >> ((j * 8)) & 0xff));
+			if ((i != 0) && ((((i) * 4 + 5 + j) % 7) == 5))
+				printf("_");	/* key separator */
+		}
+		printf("|");	/* word separator */
+	}
+	printf("\n");
+}
+#else
+#define DUMP_BYTES(label, data,len)
+#define DUMP_WORDS(label, data,len)
+#endif
+
+/*!
+ * permuted choice table (key)
+ *
+ * Note that this table has had one subtracted from each element so that the
+ * code doesn't have to do it.
+ */
+static const uint8_t pc1[] = {
+	56, 48, 40, 32, 24, 16, 8,
+	0, 57, 49, 41, 33, 25, 17,
+	9, 1, 58, 50, 42, 34, 26,
+	18, 10, 2, 59, 51, 43, 35,
+	62, 54, 46, 38, 30, 22, 14,
+	6, 61, 53, 45, 37, 29, 21,
+	13, 5, 60, 52, 44, 36, 28,
+	20, 12, 4, 27, 19, 11, 3,
+};
+
+/*! bit 0 is left-most in byte */
+static const int bytebit[] = {
+	0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
+};
+
+/*!
+ * Convert a 3-key 3DES key into the first-permutation 168-bit version.
+ *
+ * This is the format of the input key:
+ *
+ * @verbatim
+   BIT:  |191                                 128|127                                  64|63                                    0|
+   BYTE: |  0 |  1 |  2 |  3 |  4 |  5 |  6 |  7 |  8 |  9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 |
+   KEY:  |                   0                   |                   1                   |                   2                   |
+  @endverbatim
+ *
+ * This is the format of the output key:
+ *
+ * @verbatim
+   BIT:  |167                            112|111                             56|55                               0|
+   BYTE: |  0 |  1 |  2 |  3 |  4 |  5 |  6 |  7 |  8 |  9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
+   KEY:  |                 1                |                 2                |                 3                |
+  @endverbatim
+ *
+ * @param[in]   key          bytes of 3DES key
+ * @param[out] permuted_key  21 bytes of permuted key
+ * @param[in]  key_count     How many DES keys (2 or 3)
+ */
+void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key,
+			    int key_count)
+{
+	int i;
+	int j;
+	int l;
+	int m;
+
+	DUMP_BYTES("Input key", key, 8 * key_count);
+
+	/* For each individual sub-key */
+	for (i = 0; i < 3; i++) {
+		DUMP_BYTES("(key)", key, 8);
+		memset(permuted_key, 0, 7);
+		/* For each bit of key */
+		for (j = 0; j < 56; j++) {	/* convert pc1 to bits of key */
+			l = pc1[j];	/* integer bit location  */
+			m = l & 07;	/* find bit              */
+			permuted_key[j >> 3] |= (((key[l >> 3] &	/* find which key byte l is in */
+						   bytebit[m])	/* and which bit of that byte */
+						  ? 0x80 : 0) >> (j % 8));	/* and store 1-bit result */
+		}
+		switch (i) {
+		case 0:
+			if (key_count != 1)
+				key += 8;	/* move on to second key */
+			break;
+		case 1:
+			if (key_count == 2)
+				key -= 8;	/* go back to first key */
+			else if (key_count == 3)
+				key += 8;	/* move on to third key */
+			break;
+		default:
+			break;
+		}
+		permuted_key += 7;
+	}
+	DUMP_BYTES("Output key (bytes)", permuted_key - 21, 21);
+}
+
+#ifdef SELF_TEST
+const uint8_t key1_in[] = {
+	/* FE01FE01FE01FE01_01FE01FE01FE01FE_FEFE0101FEFE0101 */
+	0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01,
+	0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE,
+	0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01
+};
+
+const uint32_t key1_word_in[] = {
+	0xFE01FE01, 0xFE01FE01,
+	0x01FE01FE, 0x01FE01FE,
+	0xFEFE0101, 0xFEFE0101
+};
+
+uint8_t exp_key1_out[] = {
+	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+	0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33
+};
+
+uint32_t exp_word_key1_out[] = {
+	0x33333333, 0xAA333333, 0xAAAAAAAA, 0x5555AAAA,
+	0x55555555, 0x00000055,
+};
+
+const uint8_t key2_in[] = {
+	0xEF, 0x10, 0xBB, 0xA4, 0x23, 0x49, 0x42, 0x58,
+	0x01, 0x28, 0x01, 0x4A, 0x10, 0xE4, 0x03, 0x59,
+	0xFE, 0x84, 0x30, 0x29, 0x8E, 0xF1, 0x10, 0x5A
+};
+
+const uint32_t key2_word_in[] = {
+	0xEF10BBA4, 0x23494258,
+	0x0128014A, 0x10E40359,
+	0xFE843029, 0x8EF1105A
+};
+
+uint8_t exp_key2_out[] = {
+	0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20,
+	0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1,
+	0x2D, 0xE9, 0x11, 0x39, 0x95
+};
+
+uint32_t exp_word_key2_out[] = {
+	0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8,
+	0xE11D8550, 0x0000000D
+};
+
+const uint8_t key3_in[] = {
+	0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C,
+	0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69,
+	0xB3, 0x7C, 0x98, 0xD8, 0xC9, 0x35, 0x57, 0x19
+};
+
+const uint32_t key3_word_in[] = {
+	0xEF10BBA4, 0x23494258,
+	0x0128014A, 0x10E40359,
+	0xFE843029, 0x8EF1105A
+};
+
+uint8_t exp_key3_out[] = {
+	0x02, 0x3E, 0x93, 0xA7, 0x9F, 0x18, 0xF1, 0x11,
+	0xC6, 0x96, 0x00, 0x62, 0xA8, 0x96, 0x02, 0x3E,
+	0x93, 0xA7, 0x9F, 0x18, 0xF1
+};
+
+uint32_t exp_word_key3_out[] = {
+	0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8,
+	0xE11D8550, 0x0000000D
+};
+
+const uint8_t key4_in[] = {
+	0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C,
+	0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69,
+};
+
+const uint32_t key4_word_in[] = {
+	0xEF10BBA4, 0x23494258,
+	0x0128014A, 0x10E40359,
+	0xFE843029, 0x8EF1105A
+};
+
+const uint8_t key5_in[] = {
+	0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C,
+	0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69,
+	0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C,
+};
+
+uint8_t exp_key4_out[] = {
+	0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20,
+	0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1,
+	0x2D, 0xE9, 0x11, 0x39, 0x95
+};
+
+uint32_t exp_word_key4_out[] = {
+	0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8,
+	0xE11D8550, 0x0000000D
+};
+
+const uint8_t key6_in[] = {
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+};
+
+uint8_t exp_key6_out[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+uint32_t exp_word_key6_out[] = {
+	0x00000000, 0x0000000, 0x0000000, 0x00000000,
+	0x00000000, 0x0000000
+};
+
+const uint8_t key7_in[] = {
+	/* 01FE01FE01FE01FE_FE01FE01FE01FE01_0101FEFE0101FEFE */
+	/*  0101FEFE0101FEFE_FE01FE01FE01FE01_01FE01FE01FE01FE */
+	0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE,
+	0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01,
+	0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE,
+};
+
+uint8_t exp_key7_out[] = {
+	0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x55,
+	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xaa, 0xaa,
+	0xaa, 0xaa, 0xaa, 0xaa, 0xaa
+};
+
+uint32_t exp_word_key7_out[] = {
+	0xcccccccc, 0x55cccccc, 0x55555555, 0xaaaa5555,
+	0xaaaaaaaa, 0x000000aa
+};
+
+int run_test(const uint8_t * key_in,
+	     const int key_count,
+	     const uint32_t * key_word_in,
+	     const uint8_t * exp_bytes_key_out,
+	     const uint32_t * exp_word_key_out)
+{
+	uint8_t key_out[22];
+	uint32_t word_key_out[6];
+	int failed = 0;
+
+	memset(key_out, 0x42, 22);
+	fsl_shw_permute1_bytes(key_in, key_out, key_count);
+	if (memcmp(key_out, exp_bytes_key_out, 21) != 0) {
+		printf("bytes_to_bytes: ERROR: \n");
+		DUMP_BYTES("key_in", key_in, 8 * key_count);
+		DUMP_BYTES("key_out", key_out, 21);
+		DUMP_BYTES("exp_out", exp_bytes_key_out, 21);
+		failed |= 1;
+	} else if (key_out[21] != 0x42) {
+		printf("bytes_to_bytes: ERROR: Buffer overflow 0x%02x\n",
+		       (int)key_out[21]);
+	} else {
+		printf("bytes_to_bytes: OK\n");
+	}
+#if 0
+	memset(word_key_out, 0x42, 21);
+	fsl_shw_permute1_bytes_to_words(key_in, word_key_out, key_count);
+	if (memcmp(word_key_out, exp_word_key_out, 21) != 0) {
+		printf("bytes_to_words: ERROR: \n");
+		DUMP_BYTES("key_in", key_in, 8 * key_count);
+		DUMP_WORDS("key_out", word_key_out, 6);
+		DUMP_WORDS("exp_out", exp_word_key_out, 6);
+		failed |= 1;
+	} else {
+		printf("bytes_to_words: OK\n");
+	}
+
+	if (key_word_in != NULL) {
+		memset(word_key_out, 0x42, 21);
+		fsl_shw_permute1_words_to_words(key_word_in, word_key_out);
+		if (memcmp(word_key_out, exp_word_key_out, 21) != 0) {
+			printf("words_to_words: ERROR: \n");
+			DUMP_BYTES("key_in", key_in, 24);
+			DUMP_WORDS("key_out", word_key_out, 6);
+			DUMP_WORDS("exp_out", exp_word_key_out, 6);
+			failed |= 1;
+		} else {
+			printf("words_to_words: OK\n");
+		}
+	}
+#endif
+
+	return failed;
+}				/* end fn run_test */
+
+int main()
+{
+	int failed = 0;
+
+	printf("key1\n");
+	failed |=
+	    run_test(key1_in, 3, key1_word_in, exp_key1_out, exp_word_key1_out);
+	printf("\nkey2\n");
+	failed |=
+	    run_test(key2_in, 3, key2_word_in, exp_key2_out, exp_word_key2_out);
+	printf("\nkey3\n");
+	failed |= run_test(key3_in, 3, NULL, exp_key3_out, exp_word_key3_out);
+	printf("\nkey4\n");
+	failed |= run_test(key4_in, 2, NULL, exp_key4_out, exp_word_key4_out);
+	printf("\nkey5\n");
+	failed |= run_test(key5_in, 3, NULL, exp_key4_out, exp_word_key4_out);
+	printf("\nkey6 - 3\n");
+	failed |= run_test(key6_in, 3, NULL, exp_key6_out, exp_word_key6_out);
+	printf("\nkey6 - 2\n");
+	failed |= run_test(key6_in, 2, NULL, exp_key6_out, exp_word_key6_out);
+	printf("\nkey6 - 1\n");
+	failed |= run_test(key6_in, 1, NULL, exp_key6_out, exp_word_key6_out);
+	printf("\nkey7\n");
+	failed |= run_test(key7_in, 3, NULL, exp_key7_out, exp_word_key7_out);
+	printf("\n");
+
+	if (failed != 0) {
+		printf("TEST FAILED\n");
+	}
+	return failed;
+}
+
+#endif				/* SELF_TEST */
diff --git a/drivers/mxc/security/rng/fsl_shw_hash.c b/drivers/mxc/security/rng/fsl_shw_hash.c
new file mode 100644
index 000000000000..60572862a0fa
--- /dev/null
+++ b/drivers/mxc/security/rng/fsl_shw_hash.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/*!
+ * @file fsl_shw_hash.c
+ *
+ * This file implements Cryptographic Hashing functions of the FSL SHW API
+ * for Sahara.  This does not include HMAC.
+ */
+
+#include "shw_driver.h"
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */
+/*!
+ * Hash a stream of data with a cryptographic hash algorithm.
+ *
+ * The flags in the @a hash_ctx control the operation of this function.
+ *
+ * Hashing functions work on 64 octets of message at a time.  Therefore, when
+ * any partial hashing of a long message is performed, the message @a length of
+ * each segment must be a multiple of 64.  When ready to
+ * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value.
+ *
+ * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a
+ * one-shot complete hash, including padding, will be performed.  The @a length
+ * may be any value.
+ *
+ * The first octets of a data stream can be hashed by setting the
+ * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags.  The @a length must be
+ * a multiple of 64.
+ *
+ * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by
+ * #FSL_HASH_FLAGS_SAVE.  The two in combination will allow a (multiple-of-64
+ * octets) 'middle sequence' of the data stream to be hashed with the
+ * beginning.  The @a length must again be a multiple of 64.
+ *
+ * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously
+ * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and
+ * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the
+ * stream.  The @a length may be any value.
+ *
+ * If the user program wants to do the padding for the hash, it can leave off
+ * the #FSL_HASH_FLAGS_FINALIZE flag.  The @a length must then be a multiple of
+ * 64 octets.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param[in,out] hash_ctx Hashing algorithm and state of the cipher.
+ * @param      msg       Pointer to the data to be hashed.
+ * @param      length    Length, in octets, of the @a msg.
+ * @param[out] result    If not null, pointer to where to store the hash
+ *                       digest.
+ * @param      result_len Number of octets to store in @a result.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_hco_t * hash_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)hash_ctx;
+	(void)msg;
+	(void)length;
+	(void)result;
+	(void)result_len;
+
+	return ret;
+}
diff --git a/drivers/mxc/security/rng/fsl_shw_hmac.c b/drivers/mxc/security/rng/fsl_shw_hmac.c
new file mode 100644
index 000000000000..4d2a104afcd8
--- /dev/null
+++ b/drivers/mxc/security/rng/fsl_shw_hmac.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/*!
+ * @file fsl_shw_hmac.c
+ *
+ * This file implements Hashed Message Authentication Code functions of the FSL
+ * SHW API.
+ */
+
+#include "shw_driver.h"
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */
+/*!
+ * Get the precompute information
+ *
+ *
+ * @param   user_ctx
+ * @param   key_info
+ * @param   hmac_ctx
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx,
+					 fsl_shw_sko_t * key_info,
+					 fsl_shw_hmco_t * hmac_ctx)
+{
+	fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)hmac_ctx;
+
+	return status;
+}
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */
+/*!
+ * Get the hmac
+ *
+ *
+ * @param         user_ctx    Info for acquiring memory
+ * @param         key_info
+ * @param         hmac_ctx
+ * @param         msg
+ * @param         length
+ * @param         result
+ * @param         result_len
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_sko_t * key_info,
+			      fsl_shw_hmco_t * hmac_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)hmac_ctx;
+	(void)msg;
+	(void)length;
+	(void)result;
+	(void)result_len;
+
+	return status;
+}
diff --git a/drivers/mxc/security/rng/fsl_shw_rand.c b/drivers/mxc/security/rng/fsl_shw_rand.c
new file mode 100644
index 000000000000..aa4d426c70fe
--- /dev/null
+++ b/drivers/mxc/security/rng/fsl_shw_rand.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/*!
+ * @file fsl_shw_rand.c
+ *
+ * This file implements Random Number Generation functions of the FSL SHW API
+ * in USER MODE for talking to a standalone RNGA/RNGC device driver.
+ *
+ * It contains the fsl_shw_get_random() and fsl_shw_add_entropy() functions.
+ *
+ * These routines will build a request block and pass it to the SHW driver.
+ */
+
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/fcntl.h>
+#include <sys/ioctl.h>
+#include <signal.h>
+
+#ifdef FSL_DEBUG
+#include <stdio.h>
+#include <errno.h>
+#include <string.h>
+#endif				/* FSL_DEBUG */
+
+#include "shw_driver.h"
+
+extern fsl_shw_return_t validate_uco(fsl_shw_uco_t * uco);
+
+#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC)
+
+/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */
+fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+				    uint32_t length, uint8_t * data)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* perform a sanity check / update uco */
+	ret = validate_uco(user_ctx);
+	if (ret == FSL_RETURN_OK_S) {
+		struct get_random_req *req = malloc(sizeof(*req));
+
+		if (req == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+		} else {
+
+			init_req(&req->hdr, user_ctx);
+			req->size = length;
+			req->random = data;
+
+			ret =
+			    send_req(SHW_USER_REQ_GET_RANDOM, &req->hdr,
+				     user_ctx);
+		}
+	}
+
+	return ret;
+}
+
+fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+				     uint32_t length, uint8_t * data)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* perform a sanity check on the uco */
+	ret = validate_uco(user_ctx);
+	if (ret == FSL_RETURN_OK_S) {
+		struct add_entropy_req *req = malloc(sizeof(*req));
+
+		if (req == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+		} else {
+			init_req(&req->hdr, user_ctx);
+			req->size = length;
+			req->entropy = data;
+
+			ret =
+			    send_req(SHW_USER_REQ_ADD_ENTROPY, &req->hdr,
+				     user_ctx);
+		}
+	}
+
+	return ret;
+}
+
+#else				/* no H/W RNG block */
+
+fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+				    uint32_t length, uint8_t * data)
+{
+
+	(void)user_ctx;
+	(void)length;
+	(void)data;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+				     uint32_t length, uint8_t * data)
+{
+
+	(void)user_ctx;
+	(void)length;
+	(void)data;
+
+	return FSL_RETURN_ERROR_S;
+}
+#endif
diff --git a/drivers/mxc/security/rng/fsl_shw_sym.c b/drivers/mxc/security/rng/fsl_shw_sym.c
new file mode 100644
index 000000000000..bbeb1e24bc48
--- /dev/null
+++ b/drivers/mxc/security/rng/fsl_shw_sym.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/*!
+ * @file fsl_shw_sym.c
+ *
+ * This file implements the Symmetric Cipher functions of the FSL SHW API. Its
+ * features are limited to what can be done with the combination of SCC and
+ * DryIce.
+ */
+#include "fsl_platform.h"
+#include "shw_driver.h"
+
+#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE)
+
+#include "../dryice.h"
+#include <linux/mxc_scc_driver.h>
+#ifdef DIAG_SECURITY_FUNC
+#include "apihelp.h"
+#endif
+
+#include <diagnostic.h>
+
+#define SYM_DECRYPT 0
+#define SYM_ENCRYPT 1
+
+extern fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key,
+					   di_key_t * di_keyp);
+
+/*! 'Initial' IV for presence of FSL_SYM_CTX_LOAD flag */
+static uint8_t zeros[8] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*!
+ * Common function for encryption and decryption
+ *
+ * This is for a device with DryIce.
+ *
+ * A key must either refer to a 'pure' HW key, or, if PRG or PRG_IIM,
+ * established, then that key will be programmed.  Then, the HW_key in the
+ * object will be selected.  After this setup, the ciphering will be performed
+ * by calling the SCC driver..
+ *
+ * The function 'releases' the reservations before it completes.
+ */
+fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_sko_t * key_info,
+			      fsl_shw_scco_t * sym_ctx,
+			      int encrypt,
+			      uint32_t length,
+			      const uint8_t * in, uint8_t * out)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+	int key_selected = 0;
+	uint8_t *iv = NULL;
+	unsigned long count_out = length;
+	di_key_t di_key = DI_KEY_PK;	/* default for user key */
+	di_key_t di_key_orig;	/* currently selected key */
+	di_key_t selected_key = -1;
+	di_return_t di_code;
+	scc_return_t scc_code;
+
+	/* For now, only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* No software keys allowed */
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+	}
+
+	/* The only algorithm the SCC supports */
+	if (key_info->algorithm != FSL_KEY_ALG_TDES) {
+		ret = FSL_RETURN_BAD_ALGORITHM_S;
+		goto out;
+	}
+
+	/* Validate key length */
+	if ((key_info->key_length != 16)
+	    && (key_info->key_length != 21)
+	    && (key_info->key_length != 24)) {
+		ret = FSL_RETURN_BAD_KEY_LENGTH_S;
+		goto out;
+	}
+
+	/* Validate data is multiple of DES/TDES block */
+	if ((length & 7) != 0) {
+		ret = FSL_RETURN_BAD_DATA_LENGTH_S;
+		goto out;
+	}
+
+	/* Do some setup according to where the key lives */
+	if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+		if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG)
+		    && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) {
+			ret = FSL_RETURN_ERROR_S;
+		}
+	} else if (key_info->flags & FSL_SKO_KEY_PRESENT) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+	} else if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) {
+		/*
+		 * No key present or established, just refer to HW
+		 * as programmed.
+		 */
+	} else {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* Now make proper selection */
+	ret = shw_convert_pf_key(key_info->pf_key, &di_key);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Determine the current DI key selection */
+	di_code = dryice_check_key(&di_key_orig);
+	if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Could not save current DI key state: %s\n",
+					  di_error_string(di_code));
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+
+	/* If the requested DI key is already selected, don't re-select it. */
+	if (di_key != di_key_orig) {
+	   di_code = dryice_select_key(di_key, 0);
+	   if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		  LOG_DIAG_ARGS("Error from select_key: %s\n",
+			      di_error_string(di_code));
+#endif
+		  ret = FSL_RETURN_INTERNAL_ERROR_S;
+		  goto out;
+	   }
+	}
+	key_selected = 1;
+
+	/* Verify that we are using the key we want */
+	di_code = dryice_check_key(&selected_key);
+	if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Error from check_key: %s\n",
+			      di_error_string(di_code));
+#endif
+		ret = FSL_RETURN_INTERNAL_ERROR_S;
+		goto out;
+	}
+
+	if (di_key != selected_key) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Wrong key in use: %d instead of %d\n\n",
+			      selected_key, di_key);
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+
+	if (sym_ctx->mode == FSL_SYM_MODE_CBC) {
+		if ((sym_ctx->flags & FSL_SYM_CTX_LOAD)
+		    && !(sym_ctx->flags & FSL_SYM_CTX_INIT)) {
+			iv = sym_ctx->context;
+		} else if ((sym_ctx->flags & FSL_SYM_CTX_INIT)
+			   && !(sym_ctx->flags & FSL_SYM_CTX_LOAD)) {
+			iv = zeros;
+		} else {
+			/* Exactly one must be set! */
+			ret = FSL_RETURN_BAD_FLAG_S;
+			goto out;
+		}
+	}
+
+	/* Now run the data through the SCC */
+	scc_code = scc_crypt(length, in, iv,
+			     encrypt ? SCC_ENCRYPT : SCC_DECRYPT,
+			     (sym_ctx->mode == FSL_SYM_MODE_ECB)
+			     ? SCC_ECB_MODE : SCC_CBC_MODE,
+			     SCC_VERIFY_MODE_NONE, out, &count_out);
+	if (scc_code != SCC_RET_OK) {
+		ret = FSL_RETURN_INTERNAL_ERROR_S;
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("scc_code from scc_crypt() is %d\n", scc_code);
+#endif
+		goto out;
+	}
+
+	if ((sym_ctx->mode == FSL_SYM_MODE_CBC)
+	    && (sym_ctx->flags & FSL_SYM_CTX_SAVE)) {
+		/* Save the context for the caller */
+		if (encrypt) {
+			/* Last ciphertext block ... */
+			memcpy(sym_ctx->context, out + length - 8, 8);
+		} else {
+			/* Last ciphertext block ... */
+			memcpy(sym_ctx->context, in + length - 8, 8);
+		}
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	if (key_selected) {
+		(void)dryice_release_key_selection();
+	}
+
+	return ret;
+}
+
+EXPORT_SYMBOL(fsl_shw_symmetric_encrypt);
+/*!
+ * Compute symmetric encryption
+ *
+ *
+ * @param    user_ctx
+ * @param    key_info
+ * @param    sym_ctx
+ * @param    length
+ * @param    pt
+ * @param    ct
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * pt, uint8_t * ct)
+{
+	fsl_shw_return_t ret;
+
+	ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT,
+			   length, pt, ct);
+
+	return ret;
+}
+
+EXPORT_SYMBOL(fsl_shw_symmetric_decrypt);
+/*!
+ * Compute symmetric decryption
+ *
+ *
+ * @param    user_ctx
+ * @param    key_info
+ * @param    sym_ctx
+ * @param    length
+ * @param    pt
+ * @param    ct
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * ct, uint8_t * pt)
+{
+	fsl_shw_return_t ret;
+
+	ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT,
+			   length, ct, pt);
+
+	return ret;
+}
+
+#else				/* __KERNEL__ && DRYICE */
+
+fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * pt, uint8_t * ct)
+{
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)sym_ctx;
+	(void)length;
+	(void)pt;
+	(void)ct;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * ct, uint8_t * pt)
+{
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)sym_ctx;
+	(void)length;
+	(void)ct;
+	(void)pt;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#endif				/* __KERNEL__ and DRYICE */
diff --git a/drivers/mxc/security/rng/fsl_shw_wrap.c b/drivers/mxc/security/rng/fsl_shw_wrap.c
new file mode 100644
index 000000000000..05f812c534e0
--- /dev/null
+++ b/drivers/mxc/security/rng/fsl_shw_wrap.c
@@ -0,0 +1,1301 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_wrap.c
+ *
+ * This file implements Key-Wrap (Black Key) and Key Establishment functions of
+ * the FSL SHW API for the SHW (non-SAHARA) driver.
+ *
+ * This is the Black Key information:
+ *
+ * <ul>
+ * <li> Ownerid is an 8-byte, user-supplied, value to keep KEY
+ *      confidential.</li>
+ * <li> KEY is a 1-32 byte value which starts in SCC RED RAM before
+ *     wrapping, and ends up there on unwrap.  Length is limited because of
+ *    size of SCC1 RAM.</li>
+ * <li> KEY' is the encrypted KEY</li>
+ * <li> LEN is a 1-byte (for now) byte-length of KEY</li>
+ * <li> ALG is a 1-byte value for the algorithm which which the key is
+ *    associated.  Values are defined by the FSL SHW API</li>
+ * <li> FLAGS is a 1-byte value contain information like "this key is for
+ *    software" (TBD)</li>
+ * <li> Ownerid, LEN, and ALG come from the user's "key_info" object, as does
+ *    the slot number where KEY already is/will be.</li>
+ * <li> T is a Nonce</li>
+ * <li> T' is the encrypted T</li>
+ * <li> KEK is a Key-Encryption Key for the user's Key</li>
+ * <li> ICV is the "Integrity Check Value" for the wrapped key</li>
+ * <li> Black Key is the string of bytes returned as the wrapped key</li>
+ * <li> Wrap Key is the user's choice for encrypting the nonce.  One of
+ *      the Fused Key, the Random Key, or the XOR of the two.
+ * </ul>
+<table border="0">
+<tr><TD align="right">BLACK_KEY <TD width="3">=<TD>ICV | T' | LEN | ALG |
+     FLAGS | KEY'</td></tr>
+<tr><td>&nbsp;</td></tr>
+
+<tr><th>To Wrap</th></tr>
+<tr><TD align="right">T</td> <TD width="3">=</td> <TD>RND()<sub>16</sub>
+    </td></tr>
+<tr><TD align="right">KEK</td><TD width="3">=</td><TD>HASH<sub>sha256</sub>(T |
+     Ownerid)<sub>16</sub></td></tr>
+<tr><TD align="right">KEY'<TD width="3">=</td><TD>
+     TDES<sub>cbc-enc</sub>(Key=KEK, Data=KEY, IV=Ownerid)</td></tr>
+<tr><TD align="right">ICV</td><TD width="3">=</td><td>HMAC<sub>sha256</sub>
+     (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')<sub>16</sub></td></tr>
+<tr><TD align="right">T'</td><TD width="3">=</td><TD>TDES<sub>ecb-enc</sub>
+     (Key=Wrap_Key, IV=Ownerid, Data=T)</td></tr>
+
+<tr><td>&nbsp;</td></tr>
+
+<tr><th>To Unwrap</th></tr>
+<tr><TD align="right">T</td><TD width="3">=</td><TD>TDES<sub>ecb-dec</sub>
+    (Key=Wrap_Key, IV=Ownerid, Data=T')</td></tr>
+<tr><TD align="right">ICV</td><TD width="3">=</td><td>HMAC<sub>sha256</sub>
+    (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')<sub>16</sub></td></tr>
+<tr><TD align="right">KEK</td><TD width="3">=</td><td>HASH<sub>sha256</sub>
+    (T | Ownerid)<sub>16</sub></td></tr>
+<tr><TD align="right">KEY<TD width="3">=</td><TD>TDES<sub>cbc-dec</sub>
+    (Key=KEK, Data=KEY', IV=Ownerid)</td></tr>
+</table>
+
+ * This code supports two types of keys: Software Keys and keys destined for
+ * (or residing in) the DryIce Programmed Key Register.
+ *
+ * Software Keys go to / from the keystore.
+ *
+ * PK keys go to / from the DryIce Programmed Key Register.
+ *
+ * This code only works on a platform with DryIce.  "software" keys go into
+ * the keystore.  "Program" keys go to the DryIce Programmed Key Register.
+ * As far as this code is concerned, the size of that register is 21 bytes,
+ * the size of a 3DES key with parity stripped.
+ *
+ * The maximum key size supported for wrapped/unwrapped keys depends upon
+ * LENGTH_LENGTH.  Currently, it is one byte, so the maximum key size is
+ * 255 bytes.  However, key objects cannot currently hold a key of this
+ * length, so a smaller key size is the max.
+ */
+
+#include "fsl_platform.h"
+
+/* This code only works in kernel mode */
+
+#include "shw_driver.h"
+#ifdef DIAG_SECURITY_FUNC
+#include "apihelp.h"
+#endif
+
+#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE)
+
+#include "../dryice.h"
+#include <linux/mxc_scc_driver.h>
+
+#include "portable_os.h"
+#include "fsl_shw_keystore.h"
+
+#include <diagnostic.h>
+
+#include "shw_hmac.h"
+#include "shw_hash.h"
+
+#define ICV_LENGTH 16
+#define T_LENGTH 16
+#define KEK_LENGTH 21
+#define LENGTH_LENGTH 1
+#define ALGORITHM_LENGTH 1
+#define FLAGS_LENGTH 1
+
+/* ICV | T' | LEN | ALG | FLAGS | KEY' */
+#define ICV_OFFSET       0
+#define T_PRIME_OFFSET   (ICV_OFFSET + ICV_LENGTH)
+#define LENGTH_OFFSET    (T_PRIME_OFFSET + T_LENGTH)
+#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH)
+#define FLAGS_OFFSET     (ALGORITHM_OFFSET + ALGORITHM_LENGTH)
+#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH)
+
+#define FLAGS_SW_KEY     0x01
+
+#define LENGTH_PATCH  8
+#define LENGTH_PATCH_MASK  (LENGTH_PATCH - 1)
+
+/*! rounded up from 168 bits to the next word size */
+#define HW_KEY_LEN_WORDS_BITS 192
+
+/*!
+ * Round a key length up to the TDES block size
+ *
+ * @param len         Length of key, in bytes
+ *
+ * @return Length rounded up, if necessary
+ */
+#define ROUND_LENGTH(len)                                                  \
+({                                                                         \
+    uint32_t orig_len = len;                                               \
+    uint32_t new_len;                                                      \
+                                                                           \
+   if ((orig_len & LENGTH_PATCH_MASK) != 0) {                              \
+       new_len = (orig_len + LENGTH_PATCH                                  \
+            - (orig_len & LENGTH_PATCH_MASK));                             \
+   }                                                                       \
+   else {                                                                  \
+       new_len = orig_len;                                                 \
+   }                                                                       \
+                                                                           \
+   new_len;                                                                \
+})
+
+/* This is the system keystore object */
+extern fsl_shw_kso_t system_keystore;
+
+#ifdef DIAG_SECURITY_FUNC
+static void dump(const char *name, const uint8_t * data, unsigned int len)
+{
+	os_printk("%s: ", name);
+	while (len > 0) {
+		os_printk("%02x ", (unsigned)*data++);
+		len--;
+	}
+	os_printk("\n");
+}
+#endif
+
+/*
+ * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag
+ * causes the T_block to go into the T field during a wrap operation.  This
+ * will make the black key value repeatable (for a given SCC secret key, or
+ * always if the default key is in use).
+ *
+ * Normally, a random sequence is used.
+ */
+#ifdef DO_REPEATABLE_WRAP
+/*!
+ * Block of zeroes which is maximum Symmetric block size, used for
+ * initializing context register, etc.
+ */
+static uint8_t T_block[16] = {
+	0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42,
+	0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42
+};
+#endif
+
+EXPORT_SYMBOL(fsl_shw_establish_key);
+EXPORT_SYMBOL(fsl_shw_read_key);
+EXPORT_SYMBOL(fsl_shw_extract_key);
+EXPORT_SYMBOL(fsl_shw_release_key);
+
+extern fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx,
+				   fsl_shw_sko_t * key_info);
+
+extern fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx,
+				  fsl_shw_sko_t * key_info,
+				  const uint8_t * key);
+
+extern fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info);
+
+/*!
+ * Initalialize SKO and SCCO used for T <==> T' cipher operation
+ *
+ * @param wrap_key  Which wrapping key user wants
+ * @param key_info  Key object for selecting wrap key
+ * @param wrap_ctx  Sym Context object for doing the cipher op
+ */
+static inline void init_wrap_key(fsl_shw_pf_key_t wrap_key,
+				 fsl_shw_sko_t * key_info,
+				 fsl_shw_scco_t * wrap_ctx)
+{
+	fsl_shw_sko_init_pf_key(key_info, FSL_KEY_ALG_TDES, wrap_key);
+	fsl_shw_scco_init(wrap_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_ECB);
+}
+
+/*!
+ * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY')
+ *
+ * @param  user_ctx      A user context from #fsl_shw_register_user().
+ * @param  T             Location of nonce (length is T_LENGTH bytes)
+ * @param  userid        Location of userid/ownerid
+ * @param  userid_len    Length, in bytes of @c userid
+ * @param  black_key     Beginning of Black Key region
+ * @param  key_length    Number of bytes of key' there are in @c black_key
+ * @param[out] hmac      Location to store ICV.  Will be tagged "USES" so
+ *                       sf routines will not try to free it.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t calc_icv(const uint8_t * T,
+				 const uint8_t * userid,
+				 unsigned int userid_len,
+				 const uint8_t * black_key,
+				 uint32_t key_length, uint8_t * hmac)
+{
+	fsl_shw_return_t code;
+	shw_hmac_state_t hmac_state;
+
+	/* Load up T as key for the HMAC */
+	code = shw_hmac_init(&hmac_state, T, T_LENGTH);
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Previous step loaded key; Now set up to hash the data */
+
+	/* Input - start with ownerid */
+	code = shw_hmac_update(&hmac_state, userid, userid_len);
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Still input  - Append black-key fields len, alg, key' */
+	code = shw_hmac_update(&hmac_state,
+			       (void *)black_key + LENGTH_OFFSET,
+			       (LENGTH_LENGTH
+				+ ALGORITHM_LENGTH
+				+ FLAGS_LENGTH + key_length));
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Output - computed ICV/HMAC */
+	code = shw_hmac_final(&hmac_state, hmac, ICV_LENGTH);
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+      out:
+
+	return code;
+}				/* calc_icv */
+
+/*!
+ * Compute and return the KEK (Key Encryption Key) from the inputs
+ *
+ * @param userid      The user's 'secret' for the key
+ * @param userid_len  Length, in bytes of @c userid
+ * @param T           The nonce
+ * @param[out] kek    Location to store the computed KEK. It will
+ *                    be 21 bytes long.
+ *
+ * @return the usual error code
+ */
+static fsl_shw_return_t calc_kek(const uint8_t * userid,
+				 unsigned int userid_len,
+				 const uint8_t * T, uint8_t * kek)
+{
+	fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S;
+	shw_hash_state_t hash_state;
+
+	code = shw_hash_init(&hash_state, FSL_HASH_ALG_SHA256);
+	if (code != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG_ARGS("Hash init failed: %s\n", fsl_error_string(code));
+#endif
+		goto out;
+	}
+
+	code = shw_hash_update(&hash_state, T, T_LENGTH);
+	if (code != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG_ARGS("Hash for T failed: %s\n",
+			      fsl_error_string(code));
+#endif
+		goto out;
+	}
+
+	code = shw_hash_update(&hash_state, userid, userid_len);
+	if (code != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Hash for userid failed: %s\n",
+			      fsl_error_string(code));
+#endif
+		goto out;
+	}
+
+	code = shw_hash_final(&hash_state, kek, KEK_LENGTH);
+	if (code != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Could not extract kek: %s\n",
+			      fsl_error_string(code));
+#endif
+		goto out;
+	}
+
+#if KEK_LENGTH != 21
+	{
+		uint8_t permuted_kek[21];
+
+		fsl_shw_permute1_bytes(kek, permuted_kek, KEK_LENGTH / 8);
+		memcpy(kek, permuted_kek, 21);
+		memset(permuted_kek, 0, sizeof(permuted_kek));
+	}
+#endif
+
+#ifdef DIAG_SECURITY_FUNC
+	dump("kek", kek, 21);
+#endif
+
+      out:
+
+	return code;
+}				/* end fn calc_kek */
+
+/*!
+ * Validate user's wrap key selection
+ *
+ * @param wrap_key   The user's desired wrapping key
+ */
+static fsl_shw_return_t check_wrap_key(fsl_shw_pf_key_t wrap_key)
+{
+	/* unable to use desired key */
+	fsl_shw_return_t ret = FSL_RETURN_NO_RESOURCE_S;
+
+	if ((wrap_key != FSL_SHW_PF_KEY_IIM) &&
+	    (wrap_key != FSL_SHW_PF_KEY_RND) &&
+	    (wrap_key != FSL_SHW_PF_KEY_IIM_RND)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Invalid wrap_key in key wrap/unwrap attempt");
+#endif
+		goto out;
+	}
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	return ret;
+}				/* end fn check_wrap_key */
+
+/*!
+ * Perform unwrapping of a black key into a RED slot
+ *
+ * @param         user_ctx      A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be unwrapped... key length, slot info, etc.
+ * @param         black_key     Encrypted key
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx,
+			       fsl_shw_sko_t * key_info,
+			       const uint8_t * black_key)
+{
+	fsl_shw_return_t ret;
+	uint8_t hmac[ICV_LENGTH];
+	uint8_t T[T_LENGTH];
+	uint8_t kek[KEK_LENGTH + 20];
+	int key_length = black_key[LENGTH_OFFSET];
+	int rounded_key_length = ROUND_LENGTH(key_length);
+	uint8_t key[rounded_key_length];
+	fsl_shw_sko_t t_key_info;
+	fsl_shw_scco_t t_key_ctx;
+	fsl_shw_sko_t kek_key_info;
+	fsl_shw_scco_t kek_ctx;
+	int unwrapping_sw_key = key_info->flags & FSL_SKO_KEY_SW_KEY;
+	int pk_needs_restoration = 0;	/* bool */
+	unsigned original_key_length = key_info->key_length;
+	int pk_was_held = 0;
+	uint8_t current_pk[21];
+	di_return_t di_code;
+
+	ret = check_wrap_key(user_ctx->wrap_key);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	if (black_key == NULL) {
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	dump("black", black_key, KEY_PRIME_OFFSET + key_length);
+#endif
+	/* Validate SW flags to prevent misuse */
+		if ((key_info->flags & FSL_SKO_KEY_SW_KEY)
+			&& !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) {
+			ret = FSL_RETURN_BAD_FLAG_S;
+			goto out;
+		}
+
+	/* Compute T = 3des-dec-ecb(wrap_key, T') */
+	init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx);
+	ret = fsl_shw_symmetric_decrypt(user_ctx, &t_key_info, &t_key_ctx,
+					T_LENGTH,
+					black_key + T_PRIME_OFFSET, T);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Recovery of nonce (T) failed");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+
+	/* Compute ICV = HMAC(T, ownerid | len | alg | flags | key' */
+	ret = calc_icv(T, (uint8_t *) & key_info->userid,
+		       sizeof(key_info->userid),
+		       black_key, original_key_length, hmac);
+
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Calculation of ICV failed");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Validating MAC of wrapped key");
+#endif
+
+	/* Check computed ICV against value in Black Key */
+	if (memcmp(black_key + ICV_OFFSET, hmac, ICV_LENGTH) != 0) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Computed ICV fails validation\n");
+#endif
+		ret = FSL_RETURN_AUTH_FAILED_S;
+		goto out;
+	}
+
+	/* Compute KEK = SHA256(T | ownerid). */
+	ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid),
+		       T, kek);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	if (unwrapping_sw_key) {
+		di_code = dryice_get_programmed_key(current_pk, 8 * 21);
+		if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS("Could not save current PK: %s\n",
+				      di_error_string(di_code));
+#endif
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+	}
+
+	/*
+	 * "Establish" the KEK in the PK.  If the PK was held and unwrapping a
+	 * software key, then release it and try again, but remember that we need
+	 * to leave it 'held' if we are unwrapping a software key.
+	 *
+	 * If the PK is held while we are unwrapping a key for the PK, then
+	 * the user didn't call release, so gets an error.
+	 */
+	di_code = dryice_set_programmed_key(kek, 8 * 21, 0);
+	if ((di_code == DI_ERR_INUSE) && unwrapping_sw_key) {
+		/* Temporarily reprogram the PK out from under the user */
+		pk_was_held = 1;
+		dryice_release_programmed_key();
+		di_code = dryice_set_programmed_key(kek, 8 * 21, 0);
+	}
+	if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Could not program KEK: %s\n",
+			      di_error_string(di_code));
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+
+	if (unwrapping_sw_key) {
+		pk_needs_restoration = 1;
+	}
+	dryice_release_programmed_key();	/* Because of previous 'set' */
+
+	/* Compute KEY = TDES-decrypt(KEK, KEY') */
+	fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES,
+				FSL_SHW_PF_KEY_PRG);
+	fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH);
+
+	fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC);
+	fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD);
+	fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid);
+#ifdef DIAG_SECURITY_FUNC
+	dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length);
+#endif
+	ret = fsl_shw_symmetric_decrypt(user_ctx, &kek_key_info, &kek_ctx,
+					rounded_key_length,
+					black_key + KEY_PRIME_OFFSET, key);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	dump("KEY", key, original_key_length);
+#endif
+	/* Now either put key into PK or into a slot */
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		ret = load_slot(user_ctx, key_info, key);
+	} else {
+		/*
+		 * Since we have just unwrapped a program key, it had
+		 * to have been wrapped as a program key, so it must
+		 * be 168 bytes long and permuted ...
+		 */
+		ret = dryice_set_programmed_key(key, 8 * key_length, 0);
+		if (ret != FSL_RETURN_OK_S) {
+			goto out;
+		}
+	}
+
+      out:
+	key_info->key_length = original_key_length;
+
+	if (pk_needs_restoration) {
+		di_code = dryice_set_programmed_key(current_pk, 8 * 21, 0);
+	}
+
+	if (!pk_was_held) {
+		dryice_release_programmed_key();
+	}
+
+	/* Erase tracks of confidential data */
+	memset(T, 0, T_LENGTH);
+	memset(key, 0, rounded_key_length);
+	memset(current_pk, 0, sizeof(current_pk));
+	memset(&t_key_info, 0, sizeof(t_key_info));
+	memset(&t_key_ctx, 0, sizeof(t_key_ctx));
+	memset(&kek_key_info, 0, sizeof(kek_key_info));
+	memset(&kek_ctx, 0, sizeof(kek_ctx));
+	memset(kek, 0, KEK_LENGTH);
+
+	return ret;
+}				/* unwrap */
+
+/*!
+ * Perform wrapping of a black key from a RED slot (or the PK register)
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be wrapped... key length, slot info, etc.
+ * @param      black_key        Place to store encrypted key
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx,
+			     fsl_shw_sko_t * key_info, uint8_t * black_key)
+{
+	fsl_shw_return_t ret = FSL_RETURN_OK_S;
+	fsl_shw_sko_t t_key_info;	/* for holding T */
+	fsl_shw_scco_t t_key_ctx;
+	fsl_shw_sko_t kek_key_info;
+	fsl_shw_scco_t kek_ctx;
+	unsigned original_key_length = key_info->key_length;
+	unsigned rounded_key_length;
+	uint8_t T[T_LENGTH];
+	uint8_t kek[KEK_LENGTH + 20];
+	uint8_t *red_key = 0;
+	int red_key_malloced = 0;	/* bool */
+	int pk_was_held = 0;	/* bool */
+	uint8_t saved_pk[21];
+	uint8_t pk_needs_restoration;	/* bool */
+	di_return_t di_code;
+
+	ret = check_wrap_key(user_ctx->wrap_key);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	if (black_key == NULL) {
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+
+	if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) {
+		if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG)
+		    && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) {
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+	} else {
+		if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) {
+			ret = FSL_RETURN_BAD_FLAG_S;	/* not established! */
+			goto out;
+		}
+	}
+
+	black_key[ALGORITHM_OFFSET] = key_info->algorithm;
+
+#ifndef DO_REPEATABLE_WRAP
+	/* Compute T = RND() */
+	ret = fsl_shw_get_random(user_ctx, T_LENGTH, T);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+#else
+	memcpy(T, T_block, T_LENGTH);
+#endif
+
+	/* Compute KEK = SHA256(T | ownerid). */
+	ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid),
+		       T, kek);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Calculation of KEK failed\n");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+
+	rounded_key_length = ROUND_LENGTH(original_key_length);
+
+	di_code = dryice_get_programmed_key(saved_pk, 8 * 21);
+	if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Could not save current PK: %s\n",
+			      di_error_string(di_code));
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+
+	/*
+	 * Load KEK into DI PKR.  Note that we are NOT permuting it before loading,
+	 * so we are using it as though it is a 168-bit key ready for the SCC.
+	 */
+	di_code = dryice_set_programmed_key(kek, 8 * 21, 0);
+	if (di_code == DI_ERR_INUSE) {
+		/* Temporarily reprogram the PK out from under the user */
+		pk_was_held = 1;
+		dryice_release_programmed_key();
+		di_code = dryice_set_programmed_key(kek, 8 * 21, 0);
+	}
+	if (di_code != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("Could not program KEK: %s\n",
+			      di_error_string(di_code));
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+	pk_needs_restoration = 1;
+	dryice_release_programmed_key();
+
+	/* Find red key */
+	if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) {
+		black_key[LENGTH_OFFSET] = 21;
+		rounded_key_length = 24;
+
+		red_key = saved_pk;
+	} else {
+		black_key[LENGTH_OFFSET] = key_info->key_length;
+
+		red_key = os_alloc_memory(key_info->key_length, 0);
+		if (red_key == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+			goto out;
+		}
+		red_key_malloced = 1;
+
+		ret = fsl_shw_read_key(user_ctx, key_info, red_key);
+		if (ret != FSL_RETURN_OK_S) {
+			goto out;
+		}
+	}
+
+#ifdef DIAG_SECURITY_FUNC
+	dump("KEY", red_key, black_key[LENGTH_OFFSET]);
+#endif
+	/* Compute KEY' = TDES-encrypt(KEK, KEY) */
+	fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES,
+				FSL_SHW_PF_KEY_PRG);
+	fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH);
+
+	fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC);
+	fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD);
+	fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid);
+	ret = fsl_shw_symmetric_encrypt(user_ctx, &kek_key_info, &kek_ctx,
+					rounded_key_length,
+					red_key, black_key + KEY_PRIME_OFFSET);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Encryption of KEY failed\n");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+
+	/* Set up flags info */
+	black_key[FLAGS_OFFSET] = 0;
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length);
+#endif
+	/* Compute and store ICV into Black Key */
+	ret = calc_icv(T,
+		       (uint8_t *) & key_info->userid,
+		       sizeof(key_info->userid),
+		       black_key, original_key_length, black_key + ICV_OFFSET);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Calculation of ICV failed\n");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+
+	/* Compute T' = 3des-enc-ecb(wrap_key, T); Result goes to Black Key */
+	init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx);
+	ret = fsl_shw_symmetric_encrypt(user_ctx, &t_key_info, &t_key_ctx,
+					T_LENGTH,
+					T, black_key + T_PRIME_OFFSET);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Encryption of nonce failed");
+#endif
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	dump("black", black_key, KEY_PRIME_OFFSET + black_key[LENGTH_OFFSET]);
+#endif
+
+      out:
+	if (pk_needs_restoration) {
+		dryice_set_programmed_key(saved_pk, 8 * 21, 0);
+	}
+
+	if (!pk_was_held) {
+		dryice_release_programmed_key();
+	}
+
+	if (red_key_malloced) {
+		memset(red_key, 0, key_info->key_length);
+		os_free_memory(red_key);
+	}
+
+	key_info->key_length = original_key_length;
+
+	/* Erase tracks of confidential data */
+	memset(T, 0, T_LENGTH);
+	memset(&t_key_info, 0, sizeof(t_key_info));
+	memset(&t_key_ctx, 0, sizeof(t_key_ctx));
+	memset(&kek_key_info, 0, sizeof(kek_key_info));
+	memset(&kek_ctx, 0, sizeof(kek_ctx));
+	memset(kek, 0, sizeof(kek));
+	memset(saved_pk, 0, sizeof(saved_pk));
+
+	return ret;
+}				/* wrap */
+
+static fsl_shw_return_t create(fsl_shw_uco_t * user_ctx,
+			       fsl_shw_sko_t * key_info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+	unsigned key_length = key_info->key_length;
+	di_return_t di_code;
+
+	if (!(key_info->flags & FSL_SKO_KEY_SW_KEY)) {
+		/* Must be creating key for PK */
+		if ((key_info->algorithm != FSL_KEY_ALG_TDES) ||
+		    ((key_info->key_length != 16)
+		     && (key_info->key_length != 21)	/* permuted 168-bit key */
+		     &&(key_info->key_length != 24))) {
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+
+		key_length = 21;	/* 168-bit PK */
+	}
+
+	/* operational block */
+	{
+		uint8_t key_value[key_length];
+
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Creating random key\n");
+#endif
+		ret = fsl_shw_get_random(user_ctx, key_length, key_value);
+		if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG("get_random for CREATE KEY failed\n");
+#endif
+			goto out;
+		}
+
+		if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+			ret = load_slot(user_ctx, key_info, key_value);
+		} else {
+			di_code =
+			    dryice_set_programmed_key(key_value, 8 * key_length,
+						      0);
+			if (di_code != 0) {
+#ifdef DIAG_SECURITY_FUNC
+				LOG_DIAG_ARGS("di set_pk failed: %s\n",
+					      di_error_string(di_code));
+#endif
+				ret = FSL_RETURN_ERROR_S;
+				goto out;
+			}
+			ret = FSL_RETURN_OK_S;
+		}
+		memset(key_value, 0, key_length);
+	}			/* end operational block */
+
+#ifdef DIAG_SECURITY_FUNC
+	if (ret != FSL_RETURN_OK_S) {
+		LOG_DIAG("Loading random key failed");
+	}
+#endif
+
+      out:
+
+	return ret;
+}				/* end fn create */
+
+static fsl_shw_return_t accept(fsl_shw_uco_t * user_ctx,
+			       fsl_shw_sko_t * key_info, const uint8_t * key)
+{
+	uint8_t permuted_key[21];
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	if (key == NULL) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("ACCEPT:  Red Key is NULL");
+#endif
+		ret = FSL_RETURN_ERROR_S;
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	dump("red", key, key_info->key_length);
+#endif
+	/* Only SW keys go into the keystore */
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+
+		/* Copy in safe number of bytes of Red key */
+		ret = load_slot(user_ctx, key_info, key);
+	} else {		/* not SW key */
+		di_return_t di_ret;
+
+		/* Only 3DES PGM key types can be established */
+		if (((key_info->pf_key != FSL_SHW_PF_KEY_PRG)
+		     && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG))
+		    || (key_info->algorithm != FSL_KEY_ALG_TDES)) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS
+			    ("ACCEPT:  Failed trying to establish non-PRG"
+			     " or invalid 3DES Key: iim%d, iim_prg%d, alg%d\n",
+			     (key_info->pf_key != FSL_SHW_PF_KEY_PRG),
+			     (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG),
+			     (key_info->algorithm != FSL_KEY_ALG_TDES));
+#endif
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+		if ((key_info->key_length != 16)
+		    && (key_info->key_length != 21)
+		    && (key_info->key_length != 24)) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS("ACCEPT:  Failed trying to establish"
+				      " invalid 3DES Key: len=%d (%d)\n",
+				      key_info->key_length,
+				      ((key_info->key_length != 16)
+				       && (key_info->key_length != 21)
+				       && (key_info->key_length != 24)));
+#endif
+			ret = FSL_RETURN_BAD_KEY_LENGTH_S;
+			goto out;
+		}
+
+		/* Convert key into 168-bit value and put it into PK */
+		if (key_info->key_length != 21) {
+			fsl_shw_permute1_bytes(key, permuted_key,
+					       key_info->key_length / 8);
+			di_ret =
+			    dryice_set_programmed_key(permuted_key, 168, 0);
+		} else {
+			/* Already permuted ! */
+			di_ret = dryice_set_programmed_key(key, 168, 0);
+		}
+		if (di_ret != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS
+			    ("ACCEPT:  DryIce error setting Program Key: %s",
+			     di_error_string(di_ret));
+#endif
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	memset(permuted_key, 0, 21);
+
+	return ret;
+}				/* end fn accept */
+
+/*!
+ * Place a key into a protected location for use only by cryptographic
+ * algorithms.
+ *
+ * This only needs to be used to a) unwrap a key, or b) set up a key which
+ * could be wrapped by calling #fsl_shw_extract_key() at some later time).
+ *
+ * The protected key will not be available for use until this operation
+ * successfully completes.
+ *
+ * @bug This whole discussion needs review.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be established.  In the create case, the key
+ *                              length must be set.
+ * @param      establish_type   How @a key will be interpreted to establish a
+ *                              key for use.
+ * @param key                   If @a establish_type is #FSL_KEY_WRAP_UNWRAP,
+ *                              this is the location of a wrapped key.  If
+ *                              @a establish_type is #FSL_KEY_WRAP_CREATE, this
+ *                              parameter can be @a NULL.  If @a establish_type
+ *                              is #FSL_KEY_WRAP_ACCEPT, this is the location
+ *                              of a plaintext key.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+				       fsl_shw_sko_t * key_info,
+				       fsl_shw_key_wrap_t establish_type,
+				       const uint8_t * key)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+	unsigned original_key_length = key_info->key_length;
+	unsigned rounded_key_length;
+	unsigned slot_allocated = 0;
+
+	/* For now, only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("%s: Non-blocking call not supported\n",
+			      __FUNCTION__);
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/*
+	   HW keys are always 'established', but otherwise do not allow user
+	   * to establish over the top of an established key.
+	 */
+	if ((key_info->flags & FSL_SKO_KEY_ESTABLISHED)
+	    && !(key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("%s: Key already established\n", __FUNCTION__);
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* @bug VALIDATE KEY flags here -- SW or PRG/IIM_PRG */
+
+	/* Write operations into SCC memory require word-multiple number of
+	 * bytes.  For ACCEPT and CREATE functions, the key length may need
+	 * to be rounded up.  Calculate. */
+	if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) {
+		rounded_key_length = original_key_length + LENGTH_PATCH
+		    - (original_key_length & LENGTH_PATCH_MASK);
+	} else {
+		rounded_key_length = original_key_length;
+	}
+
+	/* SW keys need a place to live */
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		ret = alloc_slot(user_ctx, key_info);
+		if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG("Slot allocation failed\n");
+#endif
+			goto out;
+		}
+		slot_allocated = 1;
+	}
+
+	switch (establish_type) {
+	case FSL_KEY_WRAP_CREATE:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Creating random key\n");
+#endif
+		ret = create(user_ctx, key_info);
+		break;
+
+	case FSL_KEY_WRAP_ACCEPT:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Accepting plaintext key\n");
+#endif
+		ret = accept(user_ctx, key_info, key);
+		break;
+
+	case FSL_KEY_WRAP_UNWRAP:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Unwrapping wrapped key\n");
+#endif
+		ret = unwrap(user_ctx, key_info, key);
+		break;
+
+	default:
+		ret = FSL_RETURN_BAD_FLAG_S;
+		break;
+	}			/* switch */
+
+      out:
+	if (ret != FSL_RETURN_OK_S) {
+		if (slot_allocated) {
+			(void)dealloc_slot(user_ctx, key_info);
+		}
+		key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED;
+	} else {
+		key_info->flags |= FSL_SKO_KEY_ESTABLISHED;
+	}
+
+	return ret;
+}				/* end fn fsl_shw_establish_key */
+
+/*!
+ * Wrap a key and retrieve the wrapped value.
+ *
+ * A wrapped key is a key that has been cryptographically obscured.  It is
+ * only able to be used with #fsl_shw_establish_key().
+ *
+ * This function will also release a software  key (see #fsl_shw_release_key())
+ * so it must be re-established before reuse. This is not true of PGM keys.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ * @param[out] covered_key      The location to store the 48-octet wrapped key.
+ *                              (This size is based upon the maximum key size
+ *                              of 32 octets).
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     uint8_t * covered_key)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* For now, only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Wrapping a key\n");
+#endif
+
+	if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("%s: Key not established\n", __FUNCTION__);
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+	/* Verify that a SW key info really belongs to a SW key */
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+	/*	  ret = FSL_RETURN_BAD_FLAG_S;
+		  goto out;*/
+	}
+
+	ret = wrap(user_ctx, key_info, covered_key);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		/* Need to deallocate on successful extraction */
+		(void)dealloc_slot(user_ctx, key_info);
+		/* Mark key not available in the flags */
+		key_info->flags &=
+		    ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT);
+		memset(key_info->key, 0, sizeof(key_info->key));
+	}
+
+      out:
+	return ret;
+}				/* end fn fsl_shw_extract_key */
+
+/*!
+ * De-establish a key so that it can no longer be accessed.
+ *
+ * The key will need to be re-established before it can again be used.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* For now, only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Not in blocking mode\n");
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Releasing a key\n");
+#endif
+
+	if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Key not established\n");
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		(void)dealloc_slot(user_ctx, key_info);
+		/* Turn off 'established' flag */
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("dealloc_slot() called\n");
+#endif
+		key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED;
+		ret = FSL_RETURN_OK_S;
+		goto out;
+	}
+
+	if ((key_info->pf_key == FSL_SHW_PF_KEY_PRG)
+	    || (key_info->pf_key == FSL_SHW_PF_KEY_IIM_PRG)) {
+		di_return_t di_ret;
+
+		di_ret = dryice_release_programmed_key();
+		if (di_ret != DI_SUCCESS) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS
+			    ("dryice_release_programmed_key() failed: %d\n",
+			     di_ret);
+#endif
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+	} else {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Neither SW nor HW key\n");
+#endif
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	return ret;
+}				/* end fn fsl_shw_release_key */
+
+fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+				  fsl_shw_sko_t * key_info, uint8_t * key)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+
+	/* Only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+	printk("Reading a key\n");
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Reading a key");
+#endif
+	if (key_info->flags & FSL_SKO_KEY_PRESENT) {
+		memcpy(key_info->key, key, key_info->key_length);
+		ret = FSL_RETURN_OK_S;
+	} else if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+	printk("key established\n");
+		if (key_info->keystore == NULL) {
+			printk("keystore is null\n");
+			/* First verify that the key access is valid */
+			ret =
+			    system_keystore.slot_verify_access(system_keystore.
+							       user_data,
+							       key_info->userid,
+							       key_info->
+							       handle);
+
+			printk("key in system keystore\n");
+
+			/* Key is in system keystore */
+			ret = keystore_slot_read(&system_keystore,
+						 key_info->userid,
+						 key_info->handle,
+						 key_info->key_length, key);
+		} else {
+		printk("key goes in user keystore.\n");
+			/* Key goes in user keystore */
+			ret = keystore_slot_read(key_info->keystore,
+						 key_info->userid,
+						 key_info->handle,
+						 key_info->key_length, key);
+		}
+	}
+
+      out:
+	return ret;
+}				/* end fn fsl_shw_read_key */
+
+#else				/* __KERNEL__ && DRYICE */
+
+/* User mode -- these functions are unsupported */
+
+fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+				       fsl_shw_sko_t * key_info,
+				       fsl_shw_key_wrap_t establish_type,
+				       const uint8_t * key)
+{
+	(void)user_ctx;
+	(void)key_info;
+	(void)establish_type;
+	(void)key;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     uint8_t * covered_key)
+{
+	(void)user_ctx;
+	(void)key_info;
+	(void)covered_key;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info)
+{
+	(void)user_ctx;
+	(void)key_info;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+				  fsl_shw_sko_t * key_info, uint8_t * key)
+{
+	(void)user_ctx;
+	(void)key_info;
+	(void)key;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+#endif				/* __KERNEL__ && DRYICE */
diff --git a/drivers/mxc/security/rng/include/rng_driver.h b/drivers/mxc/security/rng/include/rng_driver.h
new file mode 100644
index 000000000000..7d6d24dde915
--- /dev/null
+++ b/drivers/mxc/security/rng/include/rng_driver.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#ifndef RNG_DRIVER_H
+#define RNG_DRIVER_H
+
+#include "shw_driver.h"
+
+/* This is a Linux flag meaning 'compiling kernel code'...  */
+#ifndef __KERNEL__
+#include <inttypes.h>
+#include <stdlib.h>
+#include <memory.h>
+#else
+#include "../../sahara2/include/portable_os.h"
+#endif
+
+#include "../../sahara2/include/fsl_platform.h"
+
+/*! @file rng_driver.h
+ *
+ * @brief Header file to use the RNG driver.
+ *
+ *  @ingroup RNG
+ */
+
+#if defined(FSL_HAVE_RNGA)
+
+#include "rng_rnga.h"
+
+#elif defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC)
+
+#include "rng_rngc.h"
+
+#else				/* neither RNGA,  RNGB,  nor  RNGC */
+
+#error NO_RNG_TYPE_IDENTIFIED
+
+#endif
+
+/*****************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/*! Values from Version ID register  */
+enum rng_type {
+	/*! Type RNGA. */
+	RNG_TYPE_RNGA = 0,
+	/*! Type RNGB. */
+	RNG_TYPE_RNGB = 1,
+	/*! Type RNGC */
+	RNG_TYPE_RNGC = 2
+};
+
+/*!
+ * Return values (error codes) for kernel register interface functions
+ */
+typedef enum rng_return {
+	RNG_RET_OK = 0,		/*!< Function succeeded  */
+	RNG_RET_FAIL		/*!< Non-specific failure */
+} rng_return_t;
+
+/*****************************************************************************
+ * Data Structures
+ *****************************************************************************/
+/*!
+ * An entry in the RNG Work Queue.  Based upon standard SHW queue entry.
+ *
+ * This entry also gets saved (for non-blocking requests) in the user's result
+ * pool.  When the user picks up the request, the final processing (copy from
+ * data_local to data_user) will get made if status was good.
+ */
+typedef struct rng_work_entry {
+	struct shw_queue_entry_t hdr;	/*!< Standards SHW queue info.  */
+	uint32_t length;	/*!< Number of bytes still needed to satisfy request. */
+	uint32_t *data_local;	/*!< Where data from RNG FIFO gets placed. */
+	uint8_t *data_user;	/*!< Ultimate target of data.  */
+	unsigned completed;	/*!< Non-zero if job is done.  */
+} rng_work_entry_t;
+
+/*****************************************************************************
+ * Function Prototypes
+ *****************************************************************************/
+
+#ifdef RNG_REGISTER_PEEK_POKE
+/*!
+ * Read value from an RNG register.
+ * The offset will be checked for validity as well as whether it is
+ * accessible at the time of the call.
+ *
+ * This routine cannot be used to read the RNG's Output FIFO if the RNG is in
+ * High Assurance mode.
+ *
+ * @param[in]   register_offset  The (byte) offset within the RNG block
+ *                               of the register to be queried.  See
+ *                               RNG(A, C) registers for meanings.
+ * @param[out]  value            Pointer to where value from the register
+ *                               should be placed.
+ *
+ * @return                   See #rng_return_t.
+ */
+/* REQ-FSLSHW-PINTFC-API-LLF-001 */
+extern rng_return_t rng_read_register(uint32_t register_offset,
+				      uint32_t * value);
+
+/*!
+ * Write a new value into an RNG register.
+ *
+ * The offset will be checked for validity as well as whether it is
+ * accessible at the time of the call.
+ *
+ * @param[in]  register_offset  The (byte) offset within the RNG block
+ *                              of the register to be modified.  See
+ *                              RNG(A, C) registers for meanings.
+ * @param[in]  value            The value to store into the register.
+ *
+ * @return                   See #rng_return_t.
+ */
+/* REQ-FSLSHW-PINTFC-API-LLF-002 */
+extern rng_return_t rng_write_register(uint32_t register_offset,
+				       uint32_t value);
+#endif				/* RNG_REGISTER_PEEK_POKE */
+
+#endif				/* RNG_DRIVER_H */
diff --git a/drivers/mxc/security/rng/include/rng_internals.h b/drivers/mxc/security/rng/include/rng_internals.h
new file mode 100644
index 000000000000..62d195bf4df7
--- /dev/null
+++ b/drivers/mxc/security/rng/include/rng_internals.h
@@ -0,0 +1,680 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef RNG_INTERNALS_H
+#define RNG_INTERNALS_H
+
+/*! @file rng_internals.h
+ *
+ *  This file contains definitions which are internal to the RNG driver.
+ *
+ *  This header file should only ever be needed by rng_driver.c
+ *
+ *  Compile-time flags minimally needed:
+ *
+ *  @li Some sort of platform flag.  (FSL_HAVE_RNGA or FSL_HAVE_RNGC)
+ *
+ *  @ingroup RNG
+ */
+
+#include "portable_os.h"
+#include "shw_driver.h"
+#include "rng_driver.h"
+
+/*! @defgroup rngcompileflags RNG Compile Flags
+ *
+ * These are flags which are used to configure the RNG driver at compilation
+ * time.
+ *
+ * Most of them default to good values for normal operation, but some
+ * (#INT_RNG and #RNG_BASE_ADDR) need to be provided.
+ *
+ * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on
+ * a compile command) has defined a given preprocessor symbol.  If a given
+ * symbol is defined, then @c \#ifdef \<symbol\> will succeed.  Some symbols
+ * described below default to not having a definition, i.e. they are undefined.
+ *
+ */
+
+/*! @addtogroup rngcompileflags */
+/*! @{ */
+
+/*!
+ * This is the maximum number of times the driver will loop waiting for the
+ * RNG hardware to say that it has generated random data.  It prevents the
+ * driver from stalling forever should there be a hardware problem.
+ *
+ * Default value is 100.  It should be revisited as CPU clocks speed up.
+ */
+#ifndef RNG_MAX_TRIES
+#define RNG_MAX_TRIES 100
+#endif
+
+/* Temporarily define compile-time flags to make Doxygen happy and allow them
+   to get into the documentation. */
+#ifdef DOXYGEN_HACK
+
+/*!
+ * This symbol is the base address of the RNG in the CPU memory map.  It may
+ * come from some included header file, or it may come from the compile command
+ * line.  This symbol has no default, and the driver will not compile without
+ * it.
+ */
+#define RNG_BASE_ADDR
+#undef RNG_BASE_ADDR
+
+/*!
+ * This symbol is the Interrupt Number of the RNG in the CPU.  It may come
+ * from some included header file, or it may come from the compile command
+ * line.  This symbol has no default, and the driver will not compile without
+ * it.
+ */
+#define INT_RNG
+#undef INT_RNG
+
+/*!
+ * Defining this symbol will allow other kernel programs to call the
+ * #rng_read_register() and #rng_write_register() functions.  If this symbol is
+ * not defined, those functions will not be present in the driver.
+ */
+#define RNG_REGISTER_PEEK_POKE
+#undef RNG_REGISTER_PEEK_POKE
+
+/*!
+ * Turn on compilation of run-time operational, debug, and error messages.
+ *
+ * This flag is undefined by default.
+ */
+/* REQ-FSLSHW-DEBUG-001 */
+
+/*!
+ * Turn on compilation of run-time logging of access to the RNG registers,
+ * except for the RNG's Output FIFO register.  See #RNG_ENTROPY_DEBUG.
+ *
+ *  This flag is undefined by default
+ */
+#define RNG_REGISTER_DEBUG
+#undef  RNG_REGISTER_DEBUG
+
+/*!
+ * Turn on compilation of run-time logging of reading of the RNG's Output FIFO
+ * register.  This flag does nothing if #RNG_REGISTER_DEBUG is not defined.
+ *
+ *  This flag is undefined by default
+ */
+#define RNG_ENTROPY_DEBUG
+#undef  RNG_ENTROPY_DEBUG
+
+/*!
+ * If this flag is defined, the driver will not attempt to put the RNG into
+ * High Assurance mode.
+
+ * If it is undefined, the driver will attempt to put the RNG into High
+ * Assurance mode.  If RNG fails to go into High Assurance mode, the driver
+ * will fail to initialize.
+
+ * In either case, if the RNG is already in this mode, the driver will operate
+ * normally.
+ *
+ *  This flag is undefined by default.
+ */
+#define RNG_NO_FORCE_HIGH_ASSURANCE
+#undef RNG_NO_FORCE_HIGH_ASSURANCE
+
+/*!
+ * If this flag is defined, the driver will put the RNG into low power mode
+ * every opportunity.
+ *
+ *  This flag is undefined by default.
+ */
+#define RNG_USE_LOW_POWER_MODE
+#undef RNG_USE_LOW_POWER_MODE
+
+/*! @} */
+#endif				/* end DOXYGEN_HACK */
+
+/*!
+ * If this flag is defined, the driver will not attempt to put the RNG into
+ * High Assurance mode.
+
+ * If it is undefined, the driver will attempt to put the RNG into High
+ * Assurance mode.  If RNG fails to go into High Assurance mode, the driver
+ * will fail to initialize.
+
+ * In either case, if the RNG is already in this mode, the driver will operate
+ * normally.
+ *
+ */
+#define RNG_NO_FORCE_HIGH_ASSURANCE
+
+/*!
+ * Read a 32-bit value from an RNG register.  This macro depends upon
+ * #rng_base.  The os_read32() macro operates on 32-bit quantities, as do
+ * all RNG register reads.
+ *
+ * @param     offset  Register byte offset within RNG.
+ *
+ * @return    The value from the RNG's register.
+ */
+#ifndef RNG_REGISTER_DEBUG
+#define RNG_READ_REGISTER(offset) os_read32(rng_base+(offset))
+#else
+#define RNG_READ_REGISTER(offset) dbg_rng_read_register(offset)
+#endif
+
+/*!
+ * Write a 32-bit value to an RNG register.  This macro depends upon
+ * #rng_base.  The os_write32() macro operates on 32-bit quantities, as do
+ * all RNG register writes.
+ *
+ * @param   offset  Register byte offset within RNG.
+ * @param   value   32-bit value to store into the register
+ *
+ * @return   (void)
+ */
+#ifndef RNG_REGISTER_DEBUG
+#define RNG_WRITE_REGISTER(offset,value)                                    \
+    (void)os_write32(rng_base+(offset), value)
+#else
+#define RNG_WRITE_REGISTER(offset,value) dbg_rng_write_register(offset,value)
+#endif
+
+#ifndef RNG_DRIVER_NAME
+/*! @addtogroup rngcompileflags */
+/*! @{ */
+/*! Name the driver will use to register itself to the kernel as the driver. */
+#define RNG_DRIVER_NAME "rng"
+/*! @} */
+#endif
+
+/*!
+ * Calculate number of words needed to hold the given number of bytes.
+ *
+ * @param byte_count    Number of bytes
+ *
+ * @return              Number of words
+ */
+#define BYTES_TO_WORDS(byte_count)                                          \
+    (((byte_count)+sizeof(uint32_t)-1)/sizeof(uint32_t))
+
+/*! Gives high-level view of state of the RNG */
+typedef enum rng_status {
+	RNG_STATUS_INITIAL,	/*!< Driver status before ever starting. */
+	RNG_STATUS_CHECKING,	/*!< During driver initialization. */
+	RNG_STATUS_UNIMPLEMENTED,	/*!< Hardware is non-existent / unreachable. */
+	RNG_STATUS_OK,		/*!< Hardware is In Secure or Default state. */
+	RNG_STATUS_FAILED	/*!< Hardware is In Failed state / other fatal
+				   problem.  Driver is still able to read/write
+				   some registers, but cannot get Random
+				   data. */
+} rng_status_t;
+
+static shw_queue_t rng_work_queue;
+
+/*****************************************************************************
+ *
+ *  Function Declarations
+ *
+ *****************************************************************************/
+
+/* kernel interface functions */
+OS_DEV_INIT_DCL(rng_init);
+OS_DEV_TASK_DCL(rng_entropy_task);
+OS_DEV_SHUTDOWN_DCL(rng_shutdown);
+OS_DEV_ISR_DCL(rng_irq);
+
+#define RNG_ADD_QUEUE_ENTRY(pool, entry)                                    \
+      SHW_ADD_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry)
+
+#define RNG_REMOVE_QUEUE_ENTRY(pool, entry)                                 \
+      SHW_REMOVE_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry)
+#define  RNG_GET_WORK_ENTRY()                                               \
+      (rng_work_entry_t*)SHW_POP_FIRST_ENTRY(&rng_work_queue)
+
+/*!
+ * Add an work item to a work list.  Item will be marked incomplete.
+ *
+ * @param work Work entry to place at tail of list.
+ *
+ * @return none
+ */
+inline static void RNG_ADD_WORK_ENTRY(rng_work_entry_t * work)
+{
+	work->completed = FALSE;
+
+	SHW_ADD_QUEUE_ENTRY(&rng_work_queue, (shw_queue_entry_t *) work);
+
+	os_dev_schedule_task(rng_entropy_task);
+}
+
+/*!
+ * For #rng_check_register_accessible(), check read permission on given
+ * register.
+ */
+#define RNG_CHECK_READ 0
+
+/*!
+ * For #rng_check_register_accessible(), check write permission on given
+ * register.
+ */
+#define RNG_CHECK_WRITE 1
+
+/* Define different helper symbols based on RNG type */
+#ifdef FSL_HAVE_RNGA
+
+/******************************************************************************
+ *
+ *  RNGA support
+ *
+ *****************************************************************************/
+
+/*! Interrupt number for driver. */
+#if defined(MXC_INT_RNG)
+/* Most modern definition */
+#define INT_RNG MXC_INT_RNG
+#elif defined(MXC_INT_RNGA)
+#define INT_RNG MXC_INT_RNGA
+#else
+#define INT_RNG INT_RNGA
+#endif
+
+/*! Base (bus?) address of RNG component. */
+#define RNG_BASE_ADDR RNGA_BASE_ADDR
+
+/*! Read and return the status register. */
+#define RNG_GET_STATUS()                                                 \
+    RNG_READ_REGISTER(RNGA_STATUS)
+/*! Configure RNG for Auto seeding */
+#define RNG_AUTO_SEED()
+/* Put RNG for Seed Generation */
+#define RNG_SEED_GEN()
+/*!
+ * Return RNG Type value.  Should be RNG_TYPE_RNGA, RNG_TYPE_RNGB,
+ * or RNG_TYPE_RNGC.
+ */
+#define RNG_GET_RNG_TYPE()                                                \
+    ((RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_RNG_TYPE_MASK)       \
+     >> RNGA_CONTROL_RNG_TYPE_SHIFT)
+
+/*!
+ * Verify Type value of RNG.
+ *
+ * Returns true of OK, false if not.
+ */
+#define RNG_VERIFY_TYPE(type)                                             \
+    ((type) == RNG_TYPE_RNGA)
+
+/*! Returns non-zero if RNG device is reporting an error. */
+#define RNG_HAS_ERROR()                                                   \
+    (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_ERROR_INTERRUPT)
+/*! Returns non-zero if Bad Key is selected */
+#define RNG_HAS_BAD_KEY()     0
+/*! Return non-zero if Self Test Done */
+#define RNG_SELF_TEST_DONE()  0
+/*! Returns non-zero if RNG ring oscillators have failed. */
+#define RNG_OSCILLATOR_FAILED()                                           \
+    (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OSCILLATOR_DEAD)
+
+/*! Returns maximum number of 32-bit words in the RNG's output fifo. */
+#define RNG_GET_FIFO_SIZE()                                               \
+    ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK) \
+     >> RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT)
+
+/*! Returns number of 32-bit words currently in the RNG's output fifo. */
+#define RNG_GET_WORDS_IN_FIFO()                                            \
+    ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK) \
+     >> RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT)
+/* Configuring RNG for Self Test */
+#define RNG_SELF_TEST()
+/*! Get a random value from the RNG's output FIFO. */
+#define RNG_READ_FIFO()                                                  \
+    RNG_READ_REGISTER(RNGA_OUTPUT_FIFO)
+
+/*! Put entropy into the RNG's algorithm.
+ *  @param value  32-bit value to add to RNG's entropy.
+ **/
+#define RNG_ADD_ENTROPY(value)                                           \
+    RNG_WRITE_REGISTER(RNGA_ENTROPY, (value))
+/*! Return non-zero in case of Error during Self Test */
+#define RNG_CHECK_SELF_ERR() 0
+/*! Return non-zero in case of Error during Seed Generation */
+#define RNG_CHECK_SEED_ERR() 0
+/*! Get the RNG started at generating output. */
+#define RNG_GO()                                                         \
+{                                                                        \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);         \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_GO);         \
+}
+/*! To clear all Error Bits in Error Status Register */
+#define RNG_CLEAR_ERR()
+/*! Put RNG into High Assurance mode */
+#define RNG_SET_HIGH_ASSURANCE()                                              \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_HIGH_ASSURANCE);  \
+}
+
+/*! Return non-zero if the RNG is in High Assurance mode. */
+#define RNG_GET_HIGH_ASSURANCE()                                              \
+    (RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_HIGH_ASSURANCE)
+
+/*! Clear all status, error and otherwise. */
+#define RNG_CLEAR_ALL_STATUS()                                                \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_CLEAR_INTERRUPT); \
+}
+/* Return non-zero if RESEED Required */
+#define RNG_RESEED() 1
+
+/*! Return non-zero if Seeding is done */
+#define RNG_SEED_DONE()  1
+
+/*! Return non-zero if everything seems OK with the RNG. */
+#define RNG_WORKING()                                                    \
+    ((RNG_READ_REGISTER(RNGA_STATUS)                                     \
+      & (RNGA_STATUS_SLEEP | RNGA_STATUS_SECURITY_VIOLATION              \
+         | RNGA_STATUS_ERROR_INTERRUPT | RNGA_STATUS_FIFO_UNDERFLOW      \
+         | RNGA_STATUS_LAST_READ_STATUS )) == 0)
+
+/*! Put the RNG into sleep (low-power) mode. */
+#define RNG_SLEEP()                                                      \
+{                                                                        \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);         \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_SLEEP);      \
+}
+
+/*! Wake the RNG from sleep (low-power) mode. */
+#define RNG_WAKE()                                                       \
+{                                                                        \
+    uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);                  \
+     RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_SLEEP);    \
+}
+
+/*! Mask interrupts so that the driver/OS will not see them. */
+#define RNG_MASK_ALL_INTERRUPTS()                                             \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_MASK_INTERRUPTS); \
+}
+
+/*! Unmask interrupts so that the driver/OS will see them. */
+#define RNG_UNMASK_ALL_INTERRUPTS()                                           \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_MASK_INTERRUPTS);\
+}
+
+/*!
+ * @def RNG_PUT_RNG_TO_SLEEP()
+ *
+ * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will put the RNG
+ * to sleep (low power mode).
+ *
+ * @return none
+ */
+/*!
+ * @def RNG_WAKE_RNG_FROM_SLEEP()
+ *
+ * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will wake the RNG
+ * from sleep (low power mode).
+ *
+ * @return none
+ */
+#ifdef RNG_USE_LOW_POWER_MODE
+
+#define RNG_PUT_RNG_TO_SLEEP()                                                \
+    RNG_SLEEP()
+
+#define RNG_WAKE_FROM_SLEEP()                                                 \
+    RNG_WAKE()  1
+
+#else				/* not low power mode */
+
+#define RNG_PUT_RNG_TO_SLEEP()
+
+#define RNG_WAKE_FROM_SLEEP()
+
+#endif				/* Use low-power mode */
+
+#else				/* FSL_HAVE_RNGB or FSL_HAVE_RNGC */
+
+/******************************************************************************
+ *
+ *  RNGB and RNGC support
+ *
+ *****************************************************************************/
+/*
+ * The operational interfaces for RNGB and RNGC are almost identical, so
+ * the defines for RNGC work fine for both.  There are minor differences
+ * which will be treated within this conditional block.
+ */
+
+/*! Interrupt number for driver. */
+#if defined(MXC_INT_RNG)
+/* Most modern definition */
+#define INT_RNG MXC_INT_RNG
+#elif defined(MXC_INT_RNGC)
+#define INT_RNG MXC_INT_RNGC
+#elif defined(MXC_INT_RNGB)
+#define INT_RNG MXC_INT_RNGB
+#elif defined(INT_RNGC)
+#define INT_RNG INT_RNGC
+#else
+#error NO_INTERRUPT_DEFINED
+#endif
+
+/*! Base address of RNG component. */
+#ifdef FSL_HAVE_RNGB
+#define RNG_BASE_ADDR RNGB_BASE_ADDR
+#else
+#define RNG_BASE_ADDR RNGC_BASE_ADDR
+#endif
+
+/*! Read and return the status register. */
+#define RNG_GET_STATUS()                                                 \
+    RNG_READ_REGISTER(RNGC_ERROR)
+
+/*!
+ * Return RNG Type value.  Should be RNG_TYPE_RNGA or RNG_TYPE_RNGC.
+ */
+#define RNG_GET_RNG_TYPE()                                                \
+    ((RNG_READ_REGISTER(RNGC_VERSION_ID) & RNGC_VERID_RNG_TYPE_MASK)      \
+     >> RNGC_VERID_RNG_TYPE_SHIFT)
+
+/*!
+ * Verify Type value of RNG.
+ *
+ * Returns true of OK, false if not.
+ */
+#ifdef FSL_HAVE_RNGB
+#define RNG_VERIFY_TYPE(type)                                             \
+    ((type) == RNG_TYPE_RNGB)
+#else				/* RNGC */
+#define RNG_VERIFY_TYPE(type)                                             \
+    ((type) == RNG_TYPE_RNGC)
+#endif
+
+/*! Returns non-zero if RNG device is reporting an error. */
+#define RNG_HAS_ERROR()                                                   \
+    (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ERROR)
+/*! Returns non-zero if Bad Key is selected */
+#define RNG_HAS_BAD_KEY()                                                 \
+     (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_BAD_KEY)
+/*! Returns non-zero if RNG ring oscillators have failed. */
+#define RNG_OSCILLATOR_FAILED()                                           \
+    (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_OSC_ERR)
+
+/*! Returns maximum number of 32-bit words in the RNG's output fifo. */
+#define RNG_GET_FIFO_SIZE()                                               \
+    ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_SIZE_MASK)        \
+     >> RNGC_STATUS_FIFO_SIZE_SHIFT)
+
+/*! Returns number of 32-bit words currently in the RNG's output fifo. */
+#define RNG_GET_WORDS_IN_FIFO()                                           \
+    ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_LEVEL_MASK)       \
+     >> RNGC_STATUS_FIFO_LEVEL_SHIFT)
+
+/*! Get a random value from the RNG's output FIFO. */
+#define RNG_READ_FIFO()                                                   \
+    RNG_READ_REGISTER(RNGC_FIFO)
+
+/*! Put entropy into the RNG's algorithm.
+ *  @param value  32-bit value to add to RNG's entropy.
+ **/
+#ifdef FSL_HAVE_RNGB
+#define RNG_ADD_ENTROPY(value)                                             \
+    RNG_WRITE_REGISTER(RNGB_ENTROPY, value)
+#else				/* RNGC does not have Entropy register */
+#define RNG_ADD_ENTROPY(value)
+#endif
+/*! Wake the RNG from sleep (low-power) mode. */
+#define RNG_WAKE()  1
+/*! Get the RNG started at generating output. */
+#define RNG_GO()
+/*! Put RNG into High Assurance mode. */
+#define RNG_SET_HIGH_ASSURANCE()
+/*! Returns non-zero in case of Error during Self Test       */
+#define RNG_CHECK_SELF_ERR()                                                 \
+        (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_ST_ERR)
+/*! Return non-zero in case of Error during Seed Generation */
+#define RNG_CHECK_SEED_ERR()                                                 \
+        (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_STAT_ERR)
+
+/*! Configure RNG for Self Test */
+#define RNG_SELF_TEST()                                                       \
+{                                                                             \
+    register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND);              \
+    RNG_WRITE_REGISTER(RNGC_COMMAND, command                                  \
+                                    | RNGC_COMMAND_SELF_TEST);                \
+}
+/*! Clearing the Error bits in Error Status Register */
+#define RNG_CLEAR_ERR()                                                       \
+{                                                                             \
+    register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND);              \
+    RNG_WRITE_REGISTER(RNGC_COMMAND, command                                  \
+                                    | RNGC_COMMAND_CLEAR_ERROR);              \
+}
+
+/*! Return non-zero if Self Test Done */
+#define RNG_SELF_TEST_DONE()                                                  \
+         (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ST_DONE)
+/* Put RNG for SEED Generation */
+#define RNG_SEED_GEN()                                                        \
+{                                                                             \
+    register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND);              \
+    RNG_WRITE_REGISTER(RNGC_COMMAND, command                                  \
+                                    | RNGC_COMMAND_SEED);                     \
+}
+/* Return non-zero if RESEED Required */
+#define RNG_RESEED()                                                          \
+    (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_RESEED)
+
+/*! Return non-zero if the RNG is in High Assurance mode. */
+#define RNG_GET_HIGH_ASSURANCE() (RNG_READ_REGISTER(RNGC_STATUS) &            \
+                                  RNGC_STATUS_SEC_STATE)
+
+/*! Clear all status, error and otherwise. */
+#define RNG_CLEAR_ALL_STATUS()                                                \
+    RNG_WRITE_REGISTER(RNGC_COMMAND,                                          \
+                       RNGC_COMMAND_CLEAR_INTERRUPT                           \
+                       | RNGC_COMMAND_CLEAR_ERROR)
+
+/*! Return non-zero if everything seems OK with the RNG. */
+#define RNG_WORKING()                                                         \
+    ((RNG_READ_REGISTER(RNGC_ERROR)                                           \
+      & (RNGC_ERROR_STATUS_STAT_ERR | RNGC_ERROR_STATUS_RAND_ERR              \
+       | RNGC_ERROR_STATUS_FIFO_ERR | RNGC_ERROR_STATUS_ST_ERR |              \
+         RNGC_ERROR_STATUS_OSC_ERR  | RNGC_ERROR_STATUS_LFSR_ERR )) == 0)
+/*! Return Non zero if SEEDING is DONE */
+#define RNG_SEED_DONE()                                                       \
+     ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_SEED_DONE) != 0)
+
+/*! Put the RNG into sleep (low-power) mode. */
+#define RNG_SLEEP()
+
+/*! Wake the RNG from sleep (low-power) mode. */
+
+/*! Mask interrupts so that the driver/OS will not see them. */
+#define RNG_MASK_ALL_INTERRUPTS()                                             \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGC_CONTROL, control                                  \
+                                    | RNGC_CONTROL_MASK_DONE                  \
+                                    | RNGC_CONTROL_MASK_ERROR);               \
+}
+/*! Configuring RNGC for self Test. */
+
+#define RNG_AUTO_SEED()                                                       \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGC_CONTROL, control                                  \
+                                    | RNGC_CONTROL_AUTO_SEED);                \
+}
+
+/*! Unmask interrupts so that the driver/OS will see them. */
+#define RNG_UNMASK_ALL_INTERRUPTS()                                           \
+{                                                                             \
+    register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL);              \
+    RNG_WRITE_REGISTER(RNGC_CONTROL,                                          \
+                control & ~(RNGC_CONTROL_MASK_DONE|RNGC_CONTROL_MASK_ERROR)); \
+}
+
+/*! Put RNG to sleep if appropriate. */
+#define RNG_PUT_RNG_TO_SLEEP()
+
+/*! Wake RNG from sleep if necessary. */
+#define RNG_WAKE_FROM_SLEEP()
+
+#endif				/* RNG TYPE */
+
+/* internal functions */
+static os_error_code rng_map_RNG_memory(void);
+static os_error_code rng_setup_interrupt_handling(void);
+#ifdef RNG_REGISTER_PEEK_POKE
+inline static int rng_check_register_offset(uint32_t offset);
+inline static int rng_check_register_accessible(uint32_t offset,
+						int access_write);
+#endif				/*  DEBUG_RNG_REGISTERS */
+static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words);
+static os_error_code rng_grab_config_values(void);
+static void rng_cleanup(void);
+
+#ifdef FSL_HAVE_RNGA
+static void rng_sec_failure(void);
+#endif
+
+#ifdef RNG_REGISTER_DEBUG
+static uint32_t dbg_rng_read_register(uint32_t offset);
+static void dbg_rng_write_register(uint32_t offset, uint32_t value);
+#endif
+
+#if defined(LINUX_VERSION_CODE)
+
+EXPORT_SYMBOL(fsl_shw_add_entropy);
+EXPORT_SYMBOL(fsl_shw_get_random);
+
+#ifdef RNG_REGISTER_PEEK_POKE
+/* For Linux kernel, export the API functions to other kernel modules */
+EXPORT_SYMBOL(rng_read_register);
+EXPORT_SYMBOL(rng_write_register);
+#endif				/* DEBUG_RNG_REGISTERS */
+
+
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Device Driver for RNG");
+
+#endif				/* LINUX_VERSION_CODE */
+
+#endif				/* RNG_INTERNALS_H */
diff --git a/drivers/mxc/security/rng/include/rng_rnga.h b/drivers/mxc/security/rng/include/rng_rnga.h
new file mode 100644
index 000000000000..971064d51522
--- /dev/null
+++ b/drivers/mxc/security/rng/include/rng_rnga.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef RNG_RNGA_H
+#define RNG_RNGA_H
+
+/*! @defgroup rngaregs RNGA Registers
+ *  @ingroup RNG
+ * These are the definitions for the RNG registers and their offsets
+ * within the RNG.  They are used in the @c register_offset parameter of
+ * #rng_read_register() and #rng_write_register().
+ */
+/*! @addtogroup rngaregs */
+/*! @{ */
+
+/*! Control Register.  See @ref rngacontrolreg.  */
+#define RNGA_CONTROL                    0x00
+/*! Status Register. See @ref rngastatusreg. */
+#define RNGA_STATUS                     0x04
+/*! Register for adding to the Entropy of the RNG */
+#define RNGA_ENTROPY                    0x08
+/*! Register containing latest 32 bits of random value */
+#define RNGA_OUTPUT_FIFO                0x0c
+/*! Mode Register.  Non-secure mode access only.  See @ref rngmodereg. */
+#define RNGA_MODE                       0x10
+/*! Verification Control Register.  Non-secure mode access only.  See
+ *  @ref rngvfctlreg. */
+#define RNGA_VERIFICATION_CONTROL       0x14
+/*! Oscillator Control Counter Register.  Non-secure mode access only.
+ *  See @ref rngosccntctlreg. */
+#define RNGA_OSCILLATOR_CONTROL_COUNTER 0x18
+/*! Oscillator 1 Counter Register.  Non-secure mode access only.  See
+ *  @ref rngosccntreg. */
+#define RNGA_OSCILLATOR1_COUNTER        0x1c
+/*! Oscillator 2 Counter Register.  Non-secure mode access only.  See
+ *  @ref rngosccntreg. */
+#define RNGA_OSCILLATOR2_COUNTER        0x20
+/*! Oscillator Counter Status Register.  Non-secure mode access only.  See
+ *  @ref rngosccntstatreg. */
+#define RNGA_OSCILLATOR_COUNTER_STATUS  0x24
+/*! @} */
+
+/*! Total address space of the RNGA, in bytes */
+#define RNG_ADDRESS_RANGE 0x28
+
+/*! @defgroup rngacontrolreg RNGA Control Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngacontrolreg */
+/*! @{ */
+/*! These bits are unimplemented or reserved */
+#define RNGA_CONTROL_ZEROS_MASK      0x0fffffe0
+/*! 'RNG type' - should be 0 for RNGA */
+#define RNGA_CONTROL_RNG_TYPE_MASK   0xf0000000
+/*! Number of bits to shift the type to get it to LSB */
+#define RNGA_CONTROL_RNG_TYPE_SHIFT  28
+/*! Put RNG to sleep */
+#define RNGA_CONTROL_SLEEP           0x00000010
+/*! Clear interrupt & status */
+#define RNGA_CONTROL_CLEAR_INTERRUPT 0x00000008
+/*! Mask interrupt generation */
+#define RNGA_CONTROL_MASK_INTERRUPTS 0x00000004
+/*! Enter into Secure Mode.  Notify SCC of security violation should FIFO
+ *  underflow occur. */
+#define RNGA_CONTROL_HIGH_ASSURANCE  0x00000002
+/*! Load data into FIFO */
+#define RNGA_CONTROL_GO              0x00000001
+/*! @} */
+
+/*! @defgroup rngastatusreg RNGA Status Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngastatusreg */
+/*! @{ */
+/*! RNG Oscillator not working */
+#define RNGA_STATUS_OSCILLATOR_DEAD         0x80000000
+/*! These bits are undefined or reserved */
+#define RNGA_STATUS_ZEROS1_MASK             0x7f000000
+/*! How big FIFO is, in bytes */
+#define RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK   0x00ff0000
+/*! How many bits right to shift fifo size to make it LSB */
+#define RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT  16
+/*! How many bytes are currently in the FIFO */
+#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK  0x0000ff00
+/*! How many bits right to shift fifo level to make it LSB */
+#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT 8
+/*! These bits are undefined or reserved. */
+#define RNGA_STATUS_ZEROS2_MASK             0x000000e0
+/*! RNG is sleeping. */
+#define RNGA_STATUS_SLEEP                   0x00000010
+/*! Error detected. */
+#define RNGA_STATUS_ERROR_INTERRUPT         0x00000008
+/*! FIFO was empty on some read since last status read. */
+#define RNGA_STATUS_FIFO_UNDERFLOW          0x00000004
+/*! FIFO was empty on most recent read. */
+#define RNGA_STATUS_LAST_READ_STATUS        0x00000002
+/*! Security violation occurred.  Will only happen in High Assurance mode.  */
+#define RNGA_STATUS_SECURITY_VIOLATION      0x00000001
+/*! @} */
+
+/*! @defgroup rngmodereg RNG Mode Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngmodereg */
+/*! @{ */
+/*! These bits are undefined or reserved */
+#define RNGA_MODE_ZEROS_MASK                0xfffffffc
+/*! RNG is in / put RNG in Oscillator Frequency Test Mode. */
+#define RNGA_MODE_OSCILLATOR_FREQ_TEST      0x00000002
+/*! Put RNG in verification mode / RNG is in verification mode. */
+#define RNGA_MODE_VERIFICATION              0x00000001
+/*! @} */
+
+/*! @defgroup rngvfctlreg RNG Verification Control Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngvfctlreg */
+/*! @{ */
+/*! These bits are undefined or reserved. */
+#define RNGA_VFCTL_ZEROS_MASK               0xfffffff8
+/*! Reset the shift registers. */
+#define RNGA_VFCTL_RESET_SHIFT_REGISTERS    0x00000004
+/*! Drive shift registers from system clock. */
+#define RNGA_VFCTL_FORCE_SYSTEM_CLOCK       0x00000002
+/*! Turn off shift register clocks. */
+#define RNGA_VFCTL_SHIFT_CLOCK_OFF          0x00000001
+/*! @} */
+
+/*!
+ * @defgroup rngosccntctlreg RNG Oscillator Counter Control Register Definitions
+ * @ingroup RNG
+ */
+/*! @addtogroup rngosccntctlreg */
+/*! @{ */
+/*! These bits are undefined or reserved. */
+#define RNGA_OSCCR_ZEROS_MASK               0xfffc0000
+/*! Bits containing clock cycle counter */
+#define RNGA_OSCCR_CLOCK_CYCLES_MASK        0x0003ffff
+/*! Bits to shift right RNG_OSCCR_CLOCK_CYCLES_MASK */
+#define RNGA_OSCCR_CLOCK_CYCLES_SHIFT       0
+/*! @} */
+
+/*!
+ * @defgroup rngosccntreg RNG Oscillator (1 and 2) Counter Register Definitions
+ * @ingroup RNG
+ */
+/*! @addtogroup rngosccntreg */
+/*! @{ */
+/*! These bits are undefined or reserved. */
+#define RNGA_COUNTER_ZEROS_MASK             0xfff00000
+/*! Bits containing number of clock pulses received from the oscillator. */
+#define RNGA_COUNTER_PULSES_MASK            0x000fffff
+/*! Bits right to shift RNG_COUNTER_PULSES_MASK to make it LSB. */
+#define RNGA_COUNTER_PULSES_SHIFT           0
+/*! @} */
+
+/*!
+ * @defgroup rngosccntstatreg RNG Oscillator Counter Status Register Definitions
+ * @ingroup RNG
+ */
+/*! @addtogroup rngosccntstatreg */
+/*! @{ */
+/*! These bits are undefined or reserved. */
+#define RNGA_COUNTER_STATUS_ZEROS_MASK      0xfffffffc
+/*! Oscillator 2 has toggled 0x400 times */
+#define RNGA_COUNTER_STATUS_OSCILLATOR2     0x00000002
+/*! Oscillator 1 has toggled 0x400 times */
+#define RNGA_COUNTER_STATUS_OSCILLATOR1     0x00000001
+/*! @} */
+
+#endif				/* RNG_RNGA_H */
diff --git a/drivers/mxc/security/rng/include/rng_rngc.h b/drivers/mxc/security/rng/include/rng_rngc.h
new file mode 100644
index 000000000000..68effa622b87
--- /dev/null
+++ b/drivers/mxc/security/rng/include/rng_rngc.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+  * @file rng_rngc.h
+  *
+  * Definition of the registers for the RNGB and RNGC.	The names start with
+  * RNGC where they are in common or relate only to the RNGC;  the RNGB-only
+  * definitions begin with RNGB.
+  *
+  */
+
+#ifndef RNG_RNGC_H
+#define RNG_RNGC_H
+
+#define RNGC_VERSION_MAJOR3 3
+
+/*! @defgroup rngcregs RNGB/RNGC Registers
+ * These are the definitions for the RNG registers and their offsets
+ * within the RNG.  They are used in the @c register_offset parameter of
+ * #rng_read_register() and #rng_write_register().
+ *
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngcregs */
+/*! @{ */
+
+/*! RNGC Version ID Register R/W */
+#define RNGC_VERSION_ID 0x0000
+/*! RNGC Command Register R/W */
+#define RNGC_COMMAND 0x0004
+/*! RNGC Control Register R/W */
+#define RNGC_CONTROL 0x0008
+/*! RNGC Status Register R */
+#define RNGC_STATUS 0x000C
+/*! RNGC Error Status Register R */
+#define RNGC_ERROR 0x0010
+/*! RNGC FIFO Register W */
+#define RNGC_FIFO 0x0014
+/*! Undefined */
+#define RNGC_UNDEF_18 0x0018
+/*! RNGB Entropy Register W */
+#define RNGB_ENTROPY 0x0018
+/*! Undefined */
+#define RNGC_UNDEF_1C 0x001C
+/*! RNGC Verification Control Register1 R/W */
+#define RNGC_VERIFICATION_CONTROL 0x0020
+/*! Undefined */
+#define RNGC_UNDEF_24 0x0024
+/*! RNGB XKEY Data Register R */
+#define RNGB_XKEY 0x0024
+/*! RNGC Oscillator Counter Control Register1 R/W */
+#define RNGC_OSC_COUNTER_CONTROL 0x0028
+/*! RNGC Oscillator Counter Register1 R */
+#define RNGC_OSC_COUNTER 0x002C
+/*! RNGC Oscillator Counter Status Register1 R */
+#define RNGC_OSC_COUNTER_STATUS 0x0030
+/*! @} */
+
+/*! @defgroup rngcveridreg RNGB/RNGC Version ID Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngcveridreg */
+/*! @{ */
+/*! These bits are unimplemented or reserved */
+#define RNGC_VERID_ZEROS_MASK          0x0f000000
+/*! Mask for RNG TYPE */
+#define RNGC_VERID_RNG_TYPE_MASK       0xf0000000
+/*! Shift to make RNG TYPE be LSB */
+#define RNGC_VERID_RNG_TYPE_SHIFT      28
+/*! Mask for RNG Chip Version */
+#define RNGC_VERID_CHIP_VERSION_MASK   0x00ff0000
+/*! Shift to make RNG Chip version be LSB */
+#define RNGC_VERID_CHIP_VERSION_SHIFT  16
+/*! Mask for RNG Major Version */
+#define RNGC_VERID_VERSION_MAJOR_MASK  0x0000ff00
+/*! Shift to make RNG Major version be LSB */
+#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
+/*! Mask for RNG Minor Version */
+#define RNGC_VERID_VERSION_MINOR_MASK  0x000000ff
+/*! Shift to make RNG Minor version be LSB */
+#define RNGC_VERID_VERSION_MINOR_SHIFT 0
+/*! @} */
+
+/*! @defgroup rngccommandreg RNGB/RNGC Command Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngccommandreg */
+/*! @{ */
+/*! These bits are unimplemented or reserved. */
+#define RNGC_COMMAND_ZEROS_MASK      0xffffff8c
+/*! Perform a software reset of the RNGC. */
+#define RNGC_COMMAND_SOFTWARE_RESET          0x00000040
+/*! Clear error from Error Status register (and interrupt). */
+#define RNGC_COMMAND_CLEAR_ERROR             0x00000020
+/*! Clear interrupt & status. */
+#define RNGC_COMMAND_CLEAR_INTERRUPT         0x00000010
+/*! Start RNGC seed generation. */
+#define RNGC_COMMAND_SEED                    0x00000002
+/*! Perform a self test of (and reset) the RNGC. */
+#define RNGC_COMMAND_SELF_TEST               0x00000001
+/*! @} */
+
+/*! @defgroup rngccontrolreg RNGB/RNGC Control Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngccontrolreg */
+/*! @{ */
+/*! These bits are unimplemented or reserved */
+#define RNGC_CONTROL_ZEROS_MASK       0xfffffc8c
+/*! Allow access to verification registers. */
+#define RNGC_CONTROL_CTL_ACC          0x00000200
+/*! Put RNGC into deterministic verifcation mode. */
+#define RNGC_CONTROL_VERIF_MODE       0x00000100
+/*! Prevent RNGC from generating interrupts caused by errors. */
+#define RNGC_CONTROL_MASK_ERROR       0x00000040
+
+/*!
+ * Prevent RNGB/RNGC from generating interrupts after Seed Done or Self Test
+ * Mode completion.
+ */
+#define RNGC_CONTROL_MASK_DONE        0x00000020
+/*! Allow RNGC to generate a new seed whenever it is needed. */
+#define RNGC_CONTROL_AUTO_SEED        0x00000010
+/*! Set FIFO Underflow Response.*/
+#define RNGC_CONTROL_FIFO_UFLOW_MASK  0x00000003
+/*! Shift value to make FIFO Underflow Response be LSB. */
+#define RNGC_CONTROL_FIFO_UFLOW_SHIFT 0
+
+/*! @} */
+
+/*! @{  */
+/*! FIFO Underflow should cause ... */
+#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR 0
+/*! FIFO Underflow should cause ... */
+#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR2 1
+/*! FIFO Underflow should cause ... */
+#define RNGC_CONTROL_FIFO_UFLOW_BUS_XFR     2
+/*! FIFO Underflow should cause ... */
+#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_INTR  3
+/*! @} */
+
+/*! @defgroup rngcstatusreg RNGB/RNGC Status Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngcstatusreg */
+/*! @{ */
+/*! Unused or MBZ.  */
+#define RNGC_STATUS_ZEROS_MASK              0x003e0080
+/*!
+ * Statistical tests pass-fail.  Individual bits on indicate failure of a
+ * particular test.
+ */
+#define RNGC_STATUS_STAT_TEST_PF_MASK       0xff000000
+/*! Mask to get Statistical PF to be LSB. */
+#define RNGC_STATUS_STAT_TEST_PF_SHIFT      24
+/*!
+ * Self tests pass-fail.  Individual bits on indicate failure of a
+ * particular test.
+ */
+#define RNGC_STATUS_ST_PF_MASK              0x00c00000
+/*! Shift value to get Self Test PF field to be LSB. */
+#define RNGC_STATUS_ST_PF_SHIFT             22
+/* TRNG Self test pass-fail */
+#define RNGC_STATUS_ST_PF_TRNG              0x00800000
+/* PRNG Self test pass-fail */
+#define RNGC_STATUS_ST_PF_PRNG              0x00400000
+/*! Error detected in RNGC.  See Error Status register. */
+#define RNGC_STATUS_ERROR                   0x00010000
+/*! Size of the internal FIFO in 32-bit words. */
+#define RNGC_STATUS_FIFO_SIZE_MASK          0x0000f000
+/*! Shift value to get FIFO Size to be LSB. */
+#define RNGC_STATUS_FIFO_SIZE_SHIFT         12
+/*! The level (available data) of the internal FIFO in 32-bit words. */
+#define RNGC_STATUS_FIFO_LEVEL_MASK         0x00000f00
+/*! Shift value to get FIFO Level to be LSB. */
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT        8
+/*! A new seed is ready for use. */
+#define RNGC_STATUS_NEXT_SEED_DONE          0x00000040
+/*! The first seed has been generated. */
+#define RNGC_STATUS_SEED_DONE               0x00000020
+/*! Self Test has been completed. */
+#define RNGC_STATUS_ST_DONE                 0x00000010
+/*! Reseed is necessary. */
+#define RNGC_STATUS_RESEED                  0x00000008
+/*! RNGC is sleeping. */
+#define RNGC_STATUS_SLEEP                   0x00000004
+/*! RNGC is currently generating numbers, seeding, generating next seed, or
+    performing a self test. */
+#define RNGC_STATUS_BUSY                    0x00000002
+/*! RNGC is in secure state. */
+#define RNGC_STATUS_SEC_STATE               0x00000001
+
+/*! @} */
+
+/*! @defgroup rngcerrstatusreg RNGB/RNGC Error Status Register Definitions
+ *  @ingroup RNG
+ */
+/*! @addtogroup rngcerrstatusreg */
+/*! @{ */
+/*! Unused or MBZ. */
+#define RNGC_ERROR_STATUS_ZEROS_MASK        0xffffff80
+/*! Bad Key Error Status */
+#define RNGC_ERROR_STATUS_BAD_KEY          0x00000040
+/*! Random Compare Error.  Previous number matched the current number. */
+#define RNGC_ERROR_STATUS_RAND_ERR          0x00000020
+/*! FIFO Underflow.  FIFO was read while empty. */
+#define RNGC_ERROR_STATUS_FIFO_ERR          0x00000010
+/*! Statistic Error Statistic Test failed for the last seed. */
+#define RNGC_ERROR_STATUS_STAT_ERR          0x00000008
+/*! Self-test error.  Some self test has failed. */
+#define RNGC_ERROR_STATUS_ST_ERR            0x00000004
+/*!
+ * Oscillator Error.  The oscillator may be broken.  Clear by hard or soft
+ * reset.
+ */
+#define RNGC_ERROR_STATUS_OSC_ERR           0x00000002
+/*! LFSR Error.  Clear by hard or soft reset. */
+#define RNGC_ERROR_STATUS_LFSR_ERR          0x00000001
+
+/*! @} */
+
+/*! Total address space of the RNGB/RNGC registers, in bytes */
+#define RNG_ADDRESS_RANGE 0x34
+
+#endif /* RNG_RNGC_H */
diff --git a/drivers/mxc/security/rng/include/shw_driver.h b/drivers/mxc/security/rng/include/shw_driver.h
new file mode 100644
index 000000000000..cdf0cb3b1b0f
--- /dev/null
+++ b/drivers/mxc/security/rng/include/shw_driver.h
@@ -0,0 +1,2971 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#ifndef SHW_DRIVER_H
+#define SHW_DRIVER_H
+
+/* This is a Linux flag meaning 'compiling kernel code'...  */
+#ifndef __KERNEL__
+#include <inttypes.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <memory.h>
+#include <stdio.h>
+#else
+#include "../../sahara2/include/portable_os.h"
+#endif				/* __KERNEL__ */
+
+#include "../../sahara2/include/fsl_platform.h"
+
+/*! @file shw_driver.h
+ *
+ * @brief Header file to use the SHW driver.
+ *
+ * The SHW driver is used in two modes: By a user, from the FSL SHW API in user
+ * space, which goes through /dev/fsl_shw to make open(), ioctl(), and close()
+ * calls; and by other kernel modules/drivers, which use the FSL SHW API, parts
+ * of which are supported directly by the SHW driver.
+ *
+ * Testing is performed by using the apitest and kernel api test routines
+ * developed for the Sahara2 driver.
+  */
+/*#define DIAG_SECURITY_FUNC*/
+/*! Perform a security function.  */
+#define SHW_IOCTL_REQUEST 21
+
+/* This definition may need a new name, and needs to go somewhere which
+ * can determine platform, kernel vs. user, os, etc.
+ */
+#define copy_bytes(out, in, len) memcpy(out, in, len)
+
+
+/*!
+ * This is part of the IOCTL request type passed between kernel and user space.
+ * It is added to #SHW_IOCTL_REQUEST to generate the actual value.
+ */
+typedef enum shw_user_request_t {
+    SHW_USER_REQ_REGISTER_USER,    /*!< Initialize user-kernel discussion. */
+    SHW_USER_REQ_DEREGISTER_USER,  /*!< Terminate user-kernel discussion. */
+    SHW_USER_REQ_GET_RESULTS,      /*!< Get information on outstanding
+                                      results. */
+    SHW_USER_REQ_GET_CAPABILITIES, /*!< Get information on hardware support. */
+    SHW_USER_REQ_GET_RANDOM,       /*!< Get random data from RNG. */
+    SHW_USER_REQ_ADD_ENTROPY,      /*!< Add entropy to hardware RNG. */
+    SHW_USER_REQ_DROP_PERMS,       /*!< Diminish the permissions of a block of
+                                      secure memory */
+    SHW_USER_REQ_SSTATUS,          /*!< Check the status of a block of secure
+                                      memory */
+    SHW_USER_REQ_SFREE,            /*!< Free a block of secure memory */
+    SHW_USER_REQ_SCC_ENCRYPT,      /*!< Encrypt a region of user-owned secure
+                                     memory */
+    SHW_USER_REQ_SCC_DECRYPT,     /*!< Decrypt a region of user-owned secure
+                                     memory */
+} shw_user_request_t;
+
+
+/*!
+ * @typedef scc_partition_status_t
+ */
+/** Partition status information. */
+typedef enum fsl_shw_partition_status_t {
+    FSL_PART_S_UNUSABLE,          /*!< Partition not implemented */
+    FSL_PART_S_UNAVAILABLE,       /*!< Partition owned by other host */
+    FSL_PART_S_AVAILABLE,         /*!< Partition available */
+    FSL_PART_S_ALLOCATED,         /*!< Partition owned by host but not engaged
+                                   */
+    FSL_PART_S_ENGAGED,           /*!< Partition owned by host and engaged */
+} fsl_shw_partition_status_t;
+
+
+/*
+ * Structure passed during user ioctl() calls to manage secure partitions.
+ */
+typedef struct scc_partition_info_t {
+    uint32_t user_base;            /*!< Userspace pointer to base of partition */
+    uint32_t permissions;          /*!< Permissions to give the partition (only
+                                        used in call to _DROP_PERMS) */
+    fsl_shw_partition_status_t status;  /*!< Status of the partition */
+} scc_partition_info_t;
+
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+/*!
+ * Flags for the state of the User Context Object (#fsl_shw_uco_t).
+ */
+typedef enum fsl_shw_user_ctx_flags_t
+{
+  /*!
+     * API will block the caller until operation completes.  The result will be
+     * available in the return code.  If this is not set, user will have to get
+     * results using #fsl_shw_get_results().
+     */
+    FSL_UCO_BLOCKING_MODE = 0x01,
+  /*!
+     * User wants callback (at the function specified with
+     * #fsl_shw_uco_set_callback()) when the operation completes.  This flag is
+     * valid only if #FSL_UCO_BLOCKING_MODE is not set.
+     */
+    FSL_UCO_CALLBACK_MODE = 0x02,
+    /*! Do not free descriptor chain after driver (adaptor) finishes */
+    FSL_UCO_SAVE_DESC_CHAIN = 0x04,
+  /*!
+     * User has made at least one request with callbacks requested, so API is
+     * ready to handle others.
+     */
+    FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08,
+  /*!
+     * (virtual) pointer to descriptor chain is completely linked with physical
+     * (DMA) addresses, ready for the hardware.  This flag should not be used
+     * by FSL SHW API programs.
+     */
+    FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10,
+  /*!
+     * The user has changed the context but the changes have not been copied to
+     * the kernel driver.
+     */
+    FSL_UCO_CONTEXT_CHANGED = 0x20,
+    /*! Internal Use.  This context belongs to a user-mode API user. */
+    FSL_UCO_USERMODE_USER = 0x40,
+} fsl_shw_user_ctx_flags_t;
+
+
+/*!
+ * Return code for FSL_SHW library.
+ *
+ * These codes may be returned from a function call.  In non-blocking mode,
+ * they will appear as the status in a Result Object.
+ */
+/* REQ-FSLSHW-ERR-001 */
+typedef enum fsl_shw_return_t
+{
+  /*!
+     * No error.  As a function return code in Non-blocking mode, this may
+     * simply mean that the operation was accepted for eventual execution.
+     */
+    FSL_RETURN_OK_S = 0,
+	/*! Failure for non-specific reason. */
+    FSL_RETURN_ERROR_S,
+ /*!
+    * Operation failed because some resource was not able to be allocated.
+    */
+    FSL_RETURN_NO_RESOURCE_S,
+    /*! Crypto algorithm unrecognized or improper. */
+    FSL_RETURN_BAD_ALGORITHM_S,
+    /*! Crypto mode unrecognized or improper. */
+    FSL_RETURN_BAD_MODE_S,
+    /*! Flag setting unrecognized or inconsistent. */
+    FSL_RETURN_BAD_FLAG_S,
+    /*! Improper or unsupported key length for algorithm. */
+    FSL_RETURN_BAD_KEY_LENGTH_S,
+    /*! Improper parity in a (DES, TDES) key. */
+    FSL_RETURN_BAD_KEY_PARITY_S,
+  /*!
+     * Improper or unsupported data length for algorithm or internal buffer.
+     */
+    FSL_RETURN_BAD_DATA_LENGTH_S,
+    /*! Authentication / Integrity Check code check failed. */
+    FSL_RETURN_AUTH_FAILED_S,
+    /*! A memory error occurred. */
+    FSL_RETURN_MEMORY_ERROR_S,
+    /*! An error internal to the hardware occurred. */
+    FSL_RETURN_INTERNAL_ERROR_S,
+    /*! ECC detected Point at Infinity */
+    FSL_RETURN_POINT_AT_INFINITY_S,
+    /*! ECC detected No Point at Infinity */
+    FSL_RETURN_POINT_NOT_AT_INFINITY_S,
+    /*! GCD is One */
+    FSL_RETURN_GCD_IS_ONE_S,
+    /*! GCD is not One */
+    FSL_RETURN_GCD_IS_NOT_ONE_S,
+    /*! Candidate is Prime */
+    FSL_RETURN_PRIME_S,
+    /*! Candidate is not Prime */
+    FSL_RETURN_NOT_PRIME_S,
+    /*! N register loaded improperly with even value */
+    FSL_RETURN_EVEN_MODULUS_ERROR_S,
+    /*! Divisor is zero. */
+    FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S,
+    /*! Bad Exponent or Scalar value for Point Multiply */
+    FSL_RETURN_BAD_EXPONENT_ERROR_S,
+    /*! RNG hardware problem. */
+    FSL_RETURN_OSCILLATOR_ERROR_S,
+    /*! RNG hardware problem. */
+    FSL_RETURN_STATISTICS_ERROR_S,
+} fsl_shw_return_t;
+
+
+/*!
+ * Algorithm Identifier.
+ *
+ * Selection of algorithm will determine how large the block size of the
+ * algorithm is.   Context size is the same length unless otherwise specified.
+ * Selection of algorithm also affects the allowable key length.
+ */
+typedef enum fsl_shw_key_alg_t
+{
+  /*!
+     * Key will be used to perform an HMAC.  Key size is 1 to 64 octets.  Block
+     * size is 64 octets.
+     */
+    FSL_KEY_ALG_HMAC,
+  /*!
+     * Advanced Encryption Standard (Rijndael).  Block size is 16 octets.  Key
+     * size is 16 octets.  (The single choice of key size is a Sahara platform
+     * limitation.)
+     */
+    FSL_KEY_ALG_AES,
+  /*!
+     * Data Encryption Standard.  Block size is 8 octets.  Key size is 8
+     * octets.
+     */
+    FSL_KEY_ALG_DES,
+  /*!
+     * 2- or 3-key Triple DES.  Block size is 8 octets.  Key size is 16 octets
+     * for 2-key Triple DES, and 24 octets for 3-key.
+     */
+    FSL_KEY_ALG_TDES,
+  /*!
+     * ARC4.  No block size.  Context size is 259 octets.  Allowed key size is
+     * 1-16 octets.  (The choices for key size are a Sahara platform
+     * limitation.)
+     */
+    FSL_KEY_ALG_ARC4,
+} fsl_shw_key_alg_t;
+
+
+/*!
+ * Mode selector for Symmetric Ciphers.
+ *
+ * The selection of mode determines how a cryptographic algorithm will be
+ * used to process the plaintext or ciphertext.
+ *
+ * For all modes which are run block-by-block (that is, all but
+ * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text
+ * length which is multiple of the block size.  Except for #FSL_SYM_MODE_CTR,
+ * these block-by-block algorithms must also be passed a total number of octets
+ * which is a multiple of the block size.
+ *
+ * In modes which require that the total number of octets of data be a multiple
+ * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user
+ * has a total number of octets which are not a multiple of the block size, the
+ * user must perform any necessary padding to get to the correct data length.
+ */
+typedef enum fsl_shw_sym_mode_t
+{
+  /*!
+     * Stream.  There is no associated block size.  Any request to process data
+     * may be of any length.  This mode is only for ARC4 operations, and is
+     * also the only mode used for ARC4.
+     */
+    FSL_SYM_MODE_STREAM,
+
+  /*!
+     * Electronic Codebook.  Each block of data is encrypted/decrypted.  The
+     * length of the data stream must be a multiple of the block size.  This
+     * mode may be used for DES, 3DES, and AES.  The block size is determined
+     * by the algorithm.
+     */
+    FSL_SYM_MODE_ECB,
+  /*!
+     * Cipher-Block Chaining.  Each block of data is encrypted/decrypted and
+     * then "chained" with the previous block by an XOR function.  Requires
+     * context to start the XOR (previous block).  This mode may be used for
+     * DES, 3DES, and AES.  The block size is determined by the algorithm.
+     */
+    FSL_SYM_MODE_CBC,
+  /*!
+     * Counter.  The counter is encrypted, then XORed with a block of data.
+     * The counter is then incremented (using modulus arithmetic) for the next
+     * block. The final operation may be non-multiple of block size.  This mode
+     * may be used for AES.  The block size is determined by the algorithm.
+     */
+    FSL_SYM_MODE_CTR,
+} fsl_shw_sym_mode_t;
+
+
+/*!
+ * Algorithm selector for Cryptographic Hash functions.
+ *
+ * Selection of algorithm determines how large the context and digest will be.
+ * Context is the same size as the digest (resulting hash), unless otherwise
+ * specified.
+ */
+typedef enum fsl_shw_hash_alg_t
+{
+    FSL_HASH_ALG_MD5,           /*!< MD5 algorithm.  Digest is 16 octets. */
+    FSL_HASH_ALG_SHA1,          /*!< SHA-1 (aka SHA or SHA-160) algorithm.
+                                   Digest is 20 octets. */
+    FSL_HASH_ALG_SHA224,        /*!< SHA-224 algorithm.  Digest is 28 octets,
+                                   though context is 32 octets. */
+    FSL_HASH_ALG_SHA256         /*!< SHA-256 algorithm.  Digest is 32
+                                   octets. */
+} fsl_shw_hash_alg_t;
+
+
+/*!
+ * The type of Authentication-Cipher function which will be performed.
+ */
+typedef enum fsl_shw_acc_mode_t
+{
+  /*!
+     * CBC-MAC for Counter.  Requires context and modulus.  Final operation may
+     * be non-multiple of block size.  This mode may be used for AES.
+     */
+    FSL_ACC_MODE_CCM,
+  /*!
+     * SSL mode.  Not supported.  Combines HMAC and encrypt (or decrypt).
+     * Needs one key object for encryption, another for the HMAC.  The usual
+     * hashing and symmetric encryption algorithms are supported.
+     */
+    FSL_ACC_MODE_SSL
+} fsl_shw_acc_mode_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-HCO-001 */
+/*!
+ * Flags which control a Hash operation.
+ */
+typedef enum fsl_shw_hash_ctx_flags_t
+{
+    FSL_HASH_FLAGS_INIT = 0x01,     /*!< Context is empty.  Hash is started
+                                       from scratch, with a message-processed
+                                       count of zero. */
+    FSL_HASH_FLAGS_SAVE = 0x02,     /*!< Retrieve context from hardware after
+                                       hashing.  If used with the
+                                       #FSL_HASH_FLAGS_FINALIZE flag, the final
+                                       digest value will be saved in the
+                                       object. */
+    FSL_HASH_FLAGS_LOAD = 0x04,     /*!< Place context into hardware before
+                                       hashing. */
+    FSL_HASH_FLAGS_FINALIZE = 0x08, /*!< PAD message and perform final digest
+                                       operation.  If user message is
+                                       pre-padded, this flag should not be
+                                       used. */
+} fsl_shw_hash_ctx_flags_t;
+
+
+/*!
+ * Flags which control an HMAC operation.
+ *
+ * These may be combined by ORing them together.  See #fsl_shw_hmco_set_flags()
+ * and #fsl_shw_hmco_clear_flags().
+ */
+typedef enum fsl_shw_hmac_ctx_flags_t
+{
+    FSL_HMAC_FLAGS_INIT = 1,        /**< Message context is empty.  HMAC is
+                                       started from scratch (with key) or from
+                                       precompute of inner hash, depending on
+                                       whether
+                                       #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is
+                                       set. */
+    FSL_HMAC_FLAGS_SAVE = 2,        /**< Retrieve ongoing context from hardware
+                                       after hashing.  If used with the
+                                       #FSL_HMAC_FLAGS_FINALIZE flag, the final
+                                       digest value (HMAC) will be saved in the
+                                       object. */
+    FSL_HMAC_FLAGS_LOAD = 4,        /**< Place ongoing context into hardware
+                                       before hashing. */
+    FSL_HMAC_FLAGS_FINALIZE = 8,    /**< PAD message and perform final HMAC
+                                       operations of inner and outer hashes. */
+    FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16 /**< This means that the context
+                                        contains precomputed inner and outer
+                                        hash values. */
+} fsl_shw_hmac_ctx_flags_t;
+
+
+/**
+ * Flags to control use of the #fsl_shw_scco_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags()
+ */
+typedef enum fsl_shw_sym_ctx_flags_t
+{
+    /**
+     * Context is empty.  In ARC4, this means that the S-Box needs to be
+     * generated from the key.  In #FSL_SYM_MODE_CBC mode, this allows an IV of
+     * zero to be specified.  In #FSL_SYM_MODE_CTR mode, it means that an
+     * initial CTR value of zero is desired.
+     */
+    FSL_SYM_CTX_INIT = 1,
+    /**
+     * Load context from object into hardware before running cipher.  In
+     * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+     */
+    FSL_SYM_CTX_LOAD = 2,
+    /**
+     * Save context from hardware into object after running cipher.  In
+     * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+     */
+    FSL_SYM_CTX_SAVE = 4,
+    /**
+     * Context (SBox) is to be unwrapped and wrapped on each use.
+     * This flag is unsupported.
+     * */
+    FSL_SYM_CTX_PROTECT = 8,
+} fsl_shw_sym_ctx_flags_t;
+
+
+/**
+ * Flags which describe the state of the #fsl_shw_sko_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags()
+ */
+typedef enum fsl_shw_key_flags_t
+{
+    FSL_SKO_KEY_IGNORE_PARITY = 1, /*!< If algorithm is DES or 3DES, do not
+                                      validate the key parity bits. */
+    FSL_SKO_KEY_PRESENT = 2,       /*!< Clear key is present in the object. */
+    FSL_SKO_KEY_ESTABLISHED = 4,   /*!< Key has been established for use.  This
+                                       feature is not available for all
+                                       platforms, nor for all algorithms and
+                                       modes.*/
+    FSL_SKO_USE_SECRET_KEY = 8,    /*!< Use device-unique key.  Not always
+                                       available. */
+    FSL_SKO_KEY_SW_KEY = 16,	/*!< Clear key can be provided to the user */
+	FSL_SKO_KEY_SELECT_PF_KEY = 32,	/*!< Internal flag to show that this key
+					   references one of the hardware keys, and
+					   its value is in pf_key. */
+} fsl_shw_key_flags_t;
+
+
+/**
+ * Type of value which is associated with an established key.
+ */
+typedef uint64_t key_userid_t;
+
+
+/**
+ * Flags which describe the state of the #fsl_shw_acco_t.
+ *
+ * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used
+ * together, provide for a one-shot operation.
+ */
+typedef enum fsl_shw_auth_ctx_flags_t
+{
+    FSL_ACCO_CTX_INIT = 1,      /**< Initialize Context(s) */
+    FSL_ACCO_CTX_LOAD = 2,      /**< Load intermediate context(s).
+                                   This flag is unsupported. */
+    FSL_ACCO_CTX_SAVE = 4,      /**< Save intermediate context(s).
+                                   This flag is unsupported. */
+    FSL_ACCO_CTX_FINALIZE = 8,  /**< Create MAC during this operation. */
+    FSL_ACCO_NIST_CCM = 0x10,   /**< Formatting of CCM input data is
+                                    performed by calls to
+                                    #fsl_shw_ccm_nist_format_ctr_and_iv() and
+                                    #fsl_shw_ccm_nist_update_ctr_and_iv().  */
+}  fsl_shw_auth_ctx_flags_t;
+
+
+/**
+ * The operation which controls the behavior of #fsl_shw_establish_key().
+ *
+ * These values are passed to #fsl_shw_establish_key().
+ */
+typedef enum fsl_shw_key_wrap_t
+{
+    FSL_KEY_WRAP_CREATE,        /**< Generate a key from random values. */
+    FSL_KEY_WRAP_ACCEPT,        /**< Use the provided clear key. */
+    FSL_KEY_WRAP_UNWRAP         /**< Unwrap a previously wrapped key. */
+} fsl_shw_key_wrap_t;
+
+
+/**
+ *  Modulus Selector for CTR modes.
+ *
+ * The incrementing of the Counter value may be modified by a modulus.  If no
+ * modulus is needed or desired for AES, use #FSL_CTR_MOD_128.
+ */
+typedef enum fsl_shw_ctr_mod_t
+{
+    FSL_CTR_MOD_8,              /**< Run counter with modulus of 2^8. */
+    FSL_CTR_MOD_16,             /**< Run counter with modulus of 2^16. */
+    FSL_CTR_MOD_24,             /**< Run counter with modulus of 2^24. */
+    FSL_CTR_MOD_32,             /**< Run counter with modulus of 2^32. */
+    FSL_CTR_MOD_40,             /**< Run counter with modulus of 2^40. */
+    FSL_CTR_MOD_48,             /**< Run counter with modulus of 2^48. */
+    FSL_CTR_MOD_56,             /**< Run counter with modulus of 2^56. */
+    FSL_CTR_MOD_64,             /**< Run counter with modulus of 2^64. */
+    FSL_CTR_MOD_72,             /**< Run counter with modulus of 2^72. */
+    FSL_CTR_MOD_80,             /**< Run counter with modulus of 2^80. */
+    FSL_CTR_MOD_88,             /**< Run counter with modulus of 2^88. */
+    FSL_CTR_MOD_96,             /**< Run counter with modulus of 2^96. */
+    FSL_CTR_MOD_104,            /**< Run counter with modulus of 2^104. */
+    FSL_CTR_MOD_112,            /**< Run counter with modulus of 2^112. */
+    FSL_CTR_MOD_120,            /**< Run counter with modulus of 2^120. */
+    FSL_CTR_MOD_128             /**< Run counter with modulus of 2^128. */
+} fsl_shw_ctr_mod_t;
+
+
+/**
+ * A work type associated with a work/result queue request.
+ */
+typedef enum shw_work_type_t
+{
+    SHW_WORK_GET_RANDOM = 1,    /**< fsl_shw_get_random() request.  */
+    SHW_WORK_ADD_RANDOM,        /**< fsl_shw_add_entropy() request.  */
+} shw_work_type_t;
+
+
+/**
+ * Permissions flags for Secure Partitions
+ */
+typedef enum fsl_shw_permission_t
+{
+/** SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */
+    FSL_PERM_NO_ZEROIZE =       0x80000000,
+/** SCM Access Permission: Enforce trusted key read in  */
+    FSL_PERM_TRUSTED_KEY_READ = 0x40000000,
+/** SCM Access Permission: Ignore Supervisor/User mode in permission determination */
+    FSL_PERM_HD_S =             0x00000800,
+/** SCM Access Permission: Allow Read Access to  Host Domain */
+    FSL_PERM_HD_R =             0x00000400,
+/** SCM Access Permission: Allow Write Access to  Host Domain */
+    FSL_PERM_HD_W =             0x00000200,
+/** SCM Access Permission: Allow Execute Access to  Host Domain */
+    FSL_PERM_HD_X =             0x00000100,
+/** SCM Access Permission: Allow Read Access to Trusted Host Domain */
+    FSL_PERM_TH_R =             0x00000040,
+/** SCM Access Permission: Allow Write Access to Trusted Host Domain */
+    FSL_PERM_TH_W =             0x00000020,
+/** SCM Access Permission: Allow Read Access to Other/World Domain */
+    FSL_PERM_OT_R =             0x00000004,
+/** SCM Access Permission: Allow Write Access to Other/World Domain */
+    FSL_PERM_OT_W =             0x00000002,
+/** SCM Access Permission: Allow Execute Access to Other/World Domain */
+    FSL_PERM_OT_X =             0x00000001,
+} fsl_shw_permission_t;
+
+/*!
+ * Select the cypher mode to use for partition cover/uncover operations.
+ *
+ * They currently map directly to the values used in the SCC2 driver, but this
+ * is not guarinteed behavior.
+ */
+typedef enum fsl_shw_cypher_mode_t
+{
+    FSL_SHW_CYPHER_MODE_ECB = 1,       /*!< ECB mode */
+    FSL_SHW_CYPHER_MODE_CBC = 2,       /*!< CBC mode */
+} fsl_shw_cypher_mode_t;
+
+/*!
+ * Which platform key should be presented for cryptographic use.
+ */
+typedef enum fsl_shw_pf_key_t {
+	FSL_SHW_PF_KEY_IIM,	/*!< Present fused IIM key */
+	FSL_SHW_PF_KEY_PRG,	/*!< Present Program key */
+	FSL_SHW_PF_KEY_IIM_PRG,	/*!< Present IIM ^ Program key */
+	FSL_SHW_PF_KEY_IIM_RND,	/*!< Present Random key */
+	FSL_SHW_PF_KEY_RND,	/*!< Present IIM ^ Random key */
+} fsl_shw_pf_key_t;
+
+/*!
+ * The various security tamper events
+ */
+typedef enum fsl_shw_tamper_t {
+	FSL_SHW_TAMPER_NONE,	/*!< No error detected */
+	FSL_SHW_TAMPER_WTD,	/*!< wire-mesh tampering det */
+	FSL_SHW_TAMPER_ETBD,	/*!< ext tampering det: input B */
+	FSL_SHW_TAMPER_ETAD,	/*!< ext tampering det: input A */
+	FSL_SHW_TAMPER_EBD,	/*!< external boot detected */
+	FSL_SHW_TAMPER_SAD,	/*!< security alarm detected */
+	FSL_SHW_TAMPER_TTD,	/*!< temperature tampering det */
+	FSL_SHW_TAMPER_CTD,	/*!< clock tampering det */
+	FSL_SHW_TAMPER_VTD,	/*!< voltage tampering det */
+	FSL_SHW_TAMPER_MCO,	/*!< monotonic counter overflow */
+	FSL_SHW_TAMPER_TCO,	/*!< time counter overflow */
+} fsl_shw_tamper_t;
+
+/*
+ * Structure passed during user ioctl() calls to manage data stored in secure
+ * partitions.
+ */
+
+typedef struct scc_region_t {
+	uint32_t partition_base;	/*!< Base address of partition */
+	uint32_t offset;	/*!< Byte offset into partition */
+	uint32_t length;	/*!< Number of bytes in request */
+	uint8_t *black_data;	/*!< Address of cipher text */
+	uint64_t owner_id;	/*!< user's secret */
+	fsl_shw_cypher_mode_t cypher_mode;	/*!< ECB or CBC */
+	uint32_t IV[4];		/*!< IV for CBC mode */
+} scc_region_t;
+
+/******************************************************************************
+ * Data Structures
+ *****************************************************************************/
+
+/**
+ * Initialization Object
+ */
+typedef struct fsl_sho_ibo
+{
+} fsl_sho_ibo_t;
+
+
+/**
+ * Common Entry structure for work queues, results queues.
+ */
+typedef struct shw_queue_entry_t {
+    struct shw_queue_entry_t* next; /**< Next entry in queue. */
+    struct fsl_shw_uco_t*  user_ctx; /**< Associated user context. */
+    uint32_t         flags;     /**< User context flags at time of request. */
+    void (*callback)(struct fsl_shw_uco_t* uco); /**< Any callback request. */
+    uint32_t         user_ref;  /**< User's reference for this request. */
+    fsl_shw_return_t code;      /**< FSL SHW result of this operation. */
+    uint32_t         detail1;   /**< Any extra error info.  */
+    uint32_t         detail2;   /**< More any extra error info.  */
+    void*            user_mode_req; /**<  Pointer into user space.  */
+    uint32_t (*postprocess)(struct shw_queue_entry_t* q); /**< (internal)
+                                                           function to call
+                                                           when this operation
+                                                           completes.
+  */
+} shw_queue_entry_t;
+
+
+/**
+ * A queue.  Fields must be initialized to NULL before use.
+ */
+typedef struct shw_queue_t
+{
+    struct shw_queue_entry_t* head; /**< First entry in queue. */
+    struct shw_queue_entry_t* tail; /**< Last entry. */
+} shw_queue_t;
+
+
+/**
+ * Secure Partition information
+ */
+typedef struct fsl_shw_spo_t
+{
+    uint32_t                user_base;
+    void*                   kernel_base;
+    struct fsl_shw_spo_t*   next;
+} fsl_shw_spo_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-UCO-001 */
+/**
+ * User Context Object
+ */
+typedef struct fsl_shw_uco_t
+{
+    int           openfd;       /**< user-mode file descriptor */
+    uint32_t      user_ref;     /**< User's reference */
+    void (*callback)(struct fsl_shw_uco_t* uco); /**< User's callback fn  */
+    uint32_t      flags;             /**< from fsl_shw_user_ctx_flags_t */
+    unsigned      pool_size;    /**< maximum size of user result pool */
+#ifdef __KERNEL__
+    shw_queue_t   result_pool;  /**< where non-blocking results go */
+    os_process_handle_t  process; /**< remember for signalling User mode */
+    fsl_shw_spo_t* partition;    /**< chain of secure partitions owned by
+                                          the user */
+#endif
+    struct fsl_shw_uco_t* next; /**< To allow user-mode chaining of contexts,
+                                 for signalling and in kernel, to link user
+                                 contexts.  */
+    fsl_shw_pf_key_t wrap_key;	/*!< What key for ciphering T */
+} fsl_shw_uco_t;
+
+
+/* REQ-FSLSHW-PINTFC-API-GEN-006  ??  */
+/**
+ * Result object
+ */
+typedef struct fsl_shw_result_t
+{
+    uint32_t         user_ref;  /**< User's reference at time of request. */
+    fsl_shw_return_t code;      /**< Return code from request. */
+    uint32_t         detail1;   /**< Extra error info. Unused in SHW driver. */
+    uint32_t         detail2;   /**< Extra error info. Unused in SHW driver. */
+    void*            user_req;  /**< Pointer to original user request. */
+} fsl_shw_result_t;
+
+
+/**
+ * Keystore Object
+ */
+typedef struct fsl_shw_kso_t
+{
+#ifdef __KERNEL__
+    os_lock_t       lock;           /**< Pointer to lock that controls access to
+                                      the keystore. */
+#endif
+    void*           user_data;      /**< Pointer to user structure that handles
+                                      the internals of the keystore. */
+    fsl_shw_return_t (*data_init)        (fsl_shw_uco_t* user_ctx,
+                                          void** user_data);
+    void             (*data_cleanup)     (fsl_shw_uco_t* user_ctx,
+                                          void** user_data);
+    fsl_shw_return_t (*slot_verify_access)(void* user_data, uint64_t owner_id,
+                                          uint32_t slot);
+    fsl_shw_return_t (*slot_alloc)       (void* user_data, uint32_t size_bytes,
+                                          uint64_t owner_id, uint32_t* slot);
+    fsl_shw_return_t (*slot_dealloc)     (void* user_data,
+                                          uint64_t owner_id, uint32_t slot);
+    void*            (*slot_get_address) (void* user_data, uint32_t slot);
+    uint32_t         (*slot_get_base)    (void* user_data, uint32_t slot);
+    uint32_t         (*slot_get_offset)  (void* user_data, uint32_t slot);
+    uint32_t         (*slot_get_slot_size)  (void* user_data, uint32_t slot);
+} fsl_shw_kso_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-SKO-001 */
+/**
+ * Secret Key Context Object
+ */
+typedef struct fsl_shw_sko_t
+{
+    uint32_t          flags;    /**<  Flags from #fsl_shw_sym_ctx_flags_t. */
+    fsl_shw_key_alg_t algorithm; /**< Algorithm for this key. */
+    key_userid_t      userid;   /**< User's identifying value for Black key. */
+    uint32_t          handle;   /**< Reference in SCC driver for Red key. */
+    uint16_t          key_length;  /**< Length of stored key, in bytes. */
+    uint8_t           key[64];  /**< Bytes of stored key. */
+    struct fsl_shw_kso_t*   keystore;   /**< If present, key is in keystore */
+	fsl_shw_pf_key_t pf_key;	/*!< What key to select for use when this key
+					   is doing ciphering.  If FSL_SHW_PF_KEY_PRG
+					   or FSL_SHW_PF_KEY_PRG_IIM is the value, then
+					   a 'present' or 'established' key will be
+					   programed into the PK. */
+} fsl_shw_sko_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-CO-001 */
+/**
+ * Platform Capability Object
+ *
+ * Pointer to this structure is returned by fsl_shw_get_capabilities() and
+ * queried with the various fsl_shw_pco_() functions.
+ */
+typedef struct fsl_shw_pco_t
+{
+    int api_major;              /**< Major version number for API. */
+    int api_minor;              /**< Minor version number for API. */
+    int driver_major;           /**< Major version of some driver. */
+    int driver_minor;           /**< Minor version of some driver. */
+    unsigned sym_algorithm_count;           /**< Number of sym_algorithms. */
+    fsl_shw_key_alg_t*  sym_algorithms; /**< Pointer to array. */
+    unsigned sym_mode_count;    /**< Number of sym_modes. */
+    fsl_shw_sym_mode_t* sym_modes; /**< Pointer to array. */
+    unsigned hash_algorithm_count; /**< Number of hash_algorithms. */
+    fsl_shw_hash_alg_t* hash_algorithms; /**< Pointer to array */
+    uint8_t sym_support[5][4];  /**< indexed by key alg then mode */
+
+    int scc_driver_major;
+    int scc_driver_minor;
+    int scm_version;            /**< Version from SCM Configuration register */
+    int smn_version;            /**< Version from SMN Status register */
+    int block_size_bytes;       /**< Number of bytes per block of RAM; also
+                                   block size of the crypto algorithm. */
+    union {
+        struct scc_info {
+            int black_ram_size_blocks;  /**< Number of blocks of Black RAM */
+            int red_ram_size_blocks;    /**< Number of blocks of Red RAM */
+        } scc_info;
+        struct scc2_info {
+            int partition_size_bytes;   /**< Number of bytes in each partition */
+            int partition_count;        /**< Number of partitions on this platform */
+        } scc2_info;
+    } u;
+} fsl_shw_pco_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-HCO-001 */
+/**
+ * Hash Context Object
+ */
+typedef struct fsl_shw_hco_t /* fsl_shw_hash_context_object */
+{
+    fsl_shw_hash_alg_t       algorithm; /**< Algorithm for this context. */
+    uint32_t                 flags; /**< Flags from
+                                       #fsl_shw_hash_ctx_flags_t. */
+    uint8_t                  digest_length; /**< hash result length in bytes */
+    uint8_t                  context_length; /**< Context length in bytes */
+    uint8_t                  context_register_length; /**< in bytes */
+    uint32_t                 context[9]; /**< largest digest + msg size */
+} fsl_shw_hco_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-HCO-001 */
+/**
+ * HMAC Context Object
+ */
+typedef struct fsl_shw_hmco_t /* fsl_shw_hmac_context_object */
+{
+    fsl_shw_hash_alg_t       algorithm; /**< Hash algorithm for the HMAC. */
+    uint32_t                 flags; /**< Flags from
+                                       #fsl_shw_hmac_ctx_flags_t. */
+    uint8_t                  digest_length; /**< in bytes */
+    uint8_t                  context_length; /**< in bytes */
+    uint8_t                  context_register_length; /**< in bytes */
+    uint32_t                 ongoing_context[9]; /**< largest digest + msg
+                                                    size */
+    uint32_t                 inner_precompute[9]; /**< largest digest + msg
+                                                      size */
+    uint32_t                 outer_precompute[9]; /**< largest digest + msg
+                                                      size */
+} fsl_shw_hmco_t;
+
+
+/* REQ-FSLSHW-PINTFC-COA-SCCO-001 */
+/**
+ * Symmetric Crypto Context Object Context Object
+ */
+typedef struct fsl_shw_scco_t
+{
+    uint32_t                flags; /**< Flags from #fsl_shw_sym_ctx_flags_t. */
+    unsigned                block_size_bytes; /**< Both block and ctx size */
+    fsl_shw_sym_mode_t      mode; /**< Symmetric mode for this context. */
+    /* Could put modulus plus 16-octet context in union with arc4
+       sbox+ptrs... */
+    fsl_shw_ctr_mod_t       modulus_exp; /**< Exponent value for CTR modulus */
+    uint8_t                 context[8]; /**< Stored context.  Large enough
+                                             for 3DES.  */
+} fsl_shw_scco_t;
+
+
+/**
+ * Authenticate-Cipher Context Object
+
+ * An object for controlling the function of, and holding information about,
+ * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and
+ * #fsl_shw_auth_decrypt().
+ */
+typedef struct fsl_shw_acco_t
+{
+    uint32_t                 flags; /**< See #fsl_shw_auth_ctx_flags_t for
+                                       meanings */
+    fsl_shw_acc_mode_t       mode; /**< CCM only */
+    uint8_t                  mac_length; /**< User's value for length  */
+    unsigned                 q_length; /**< NIST parameter - */
+    fsl_shw_scco_t           cipher_ctx_info; /**< For running
+                                                 encrypt/decrypt. */
+    union {
+        fsl_shw_scco_t       CCM_ctx_info; /**< For running the CBC in
+                                              AES-CCM.  */
+        fsl_shw_hco_t        hash_ctx_info; /**< For running the hash */
+    } auth_info;                /**< "auth" info struct  */
+    uint8_t                  unencrypted_mac[16]; /**< max block size... */
+} fsl_shw_acco_t;
+
+
+/**
+ * Common header in request structures between User-mode API and SHW driver.
+ */
+struct shw_req_header {
+    uint32_t           flags;   /**< Flags - from user-mode context. */
+    uint32_t           user_ref; /**< Reference - from user-mode context. */
+    fsl_shw_return_t   code;    /**< Result code for operation. */
+};
+
+/**
+ *  Used by user-mode API to retrieve completed non-blocking results in
+ *  SHW_USER_REQ_GET_RESULTS ioctl().
+ */
+struct results_req {
+    struct shw_req_header hdr;  /**< Boilerplate. */
+    unsigned         requested; /**< number of results requested, */
+    unsigned         actual;    /**< number of results obtained. */
+    fsl_shw_result_t *results;  /**< pointer to memory to hold results. */
+};
+
+
+/**
+ * Used by user-mode API to retrieve hardware capabilities in
+ * SHW_USER_REQ_GET_CAPABILITIES ioctl().
+ */
+struct capabilities_req {
+    struct shw_req_header hdr;  /**< Boilerplate. */
+    unsigned         size;      /**< Size, in bytes, capabilities. */
+    fsl_shw_pco_t*   capabilities; /**< Place to copy out the info. */
+};
+
+
+/**
+ * Used by user-mode API to get a random number
+ */
+struct get_random_req {
+    struct shw_req_header hdr;  /**< Boilerplate. */
+    unsigned         size;      /**< Size, in bytes, of random. */
+    uint8_t*         random;    /**< Place to copy out the random number. */
+};
+
+
+/**
+ * Used by API to add entropy to a random number generator
+ */
+struct add_entropy_req {
+    struct shw_req_header hdr;  /**< Boilerplate. */
+    unsigned         size;      /**< Size, in bytes, of entropy. */
+    uint8_t*         entropy;   /**< Location of the entropy to be added. */
+};
+
+
+/******************************************************************************
+ * External variables
+ *****************************************************************************/
+#ifdef __KERNEL__
+extern os_lock_t shw_queue_lock;
+
+extern fsl_shw_uco_t* user_list;
+#endif
+
+
+/******************************************************************************
+ * Access Macros for Objects
+ *****************************************************************************/
+/**
+ * Get FSL SHW API version
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the API is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the API is to be stored.
+ */
+#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor)                   \
+do {                                                                          \
+    *(pcmajor) = (pcobject)->api_major;                                       \
+    *(pcminor) = (pcobject)->api_minor;                                       \
+} while (0)
+
+
+/**
+ * Get underlying driver version.
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the driver is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the driver is to be stored.
+ */
+#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor)            \
+do {                                                                          \
+    *(pcmajor) = (pcobject)->driver_major;                                    \
+    *(pcminor) = (pcobject)->driver_minor;                                    \
+} while (0)
+
+
+/**
+ * Get list of symmetric algorithms supported.
+ *
+ * @param pcobject           The Platform Capababilities Object to query.
+ * @param[out] pcalgorithms  A pointer to where to store the location of
+ *                           the list of algorithms.
+ * @param[out] pcacount      A pointer to where to store the number of
+ *                           algorithms in the list at @a algorithms.
+ */
+#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount)      \
+do {                                                                          \
+    *(pcalgorithms) = (pcobject)->sym_algorithms;                             \
+    *(pcacount) = (pcobject)->sym_algorithm_count;                            \
+} while (0)
+
+
+/**
+ * Get list of symmetric modes supported.
+ *
+ * @param pcobject        The Platform Capababilities Object to query.
+ * @param[out] gsmodes    A pointer to where to store the location of
+ *                        the list of modes.
+ * @param[out] gsacount   A pointer to where to store the number of
+ *                        algorithms in the list at @a modes.
+ */
+#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount)                \
+do {                                                                          \
+    *(gsmodes) = (pcobject)->sym_modes;                                       \
+    *(gsacount) = (pcobject)->sym_mode_count;                                 \
+} while (0)
+
+
+/**
+ * Get list of hash algorithms supported.
+ *
+ * @param pcobject           The Platform Capababilities Object to query.
+ * @param[out] gsalgorithms  A pointer which will be set to the list of
+ *                           algorithms.
+ * @param[out] gsacount      The number of algorithms in the list at @a
+ *                           algorithms.
+ */
+#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount)     \
+do {                                                                          \
+    *(gsalgorithms) = (pcobject)->hash_algorithms;                            \
+    *(gsacount) = (pcobject)->hash_algorithm_count;                           \
+} while (0)
+
+
+/**
+ * Determine whether the combination of a given symmetric algorithm and a given
+ * mode is supported.
+ *
+ * @param pcobject   The Platform Capababilities Object to query.
+ * @param pcalg      A Symmetric Cipher algorithm.
+ * @param pcmode     A Symmetric Cipher mode.
+ *
+ * @return 0 if combination is not supported, non-zero if supported.
+ */
+#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__)
+#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode)              \
+    ((pcobject)->sym_support[pcalg][pcmode])
+#else
+#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode)              \
+    0
+#endif
+
+/**
+ * Determine whether a given Encryption-Authentication mode is supported.
+ *
+ * @param pcobject  The Platform Capababilities Object to query.
+ * @param pcmode    The Authentication mode.
+ *
+ * @return 0 if mode is not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_auth_supported(pcobject, pcmode)                    \
+    0
+
+
+/**
+ * Determine whether Black Keys (key establishment / wrapping) is supported.
+ *
+ * @param pcobject  The Platform Capababilities Object to query.
+ *
+ * @return 0 if wrapping is not supported, non-zero if supported.
+ */
+#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__)
+#define fsl_shw_pco_check_black_key_supported(pcobject)                       \
+    1
+#else
+#define fsl_shw_pco_check_black_key_supported(pcobject)                       \
+    0
+
+#endif
+
+/*!
+ * Determine whether Programmed Key features are available
+ *
+ * @param pcobject          The Platform Capabilities Object to query.
+ *
+ * @return  1 if Programmed Key features are available, otherwise zero.
+ */
+#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__)
+#define fsl_shw_pco_check_pk_supported(pcobject)        \
+    1
+#else
+#define fsl_shw_pco_check_pk_supported(pcobject)        \
+    0
+#endif
+
+/*!
+ * Determine whether Software Key features are available
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return  1 if Software key features are available, otherwise zero.
+ */
+#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__)
+#define fsl_shw_pco_check_sw_keys_supported(pcobject)        \
+    1
+#else
+#define fsl_shw_pco_check_sw_keys_supported(pcobject)        \
+    0
+#endif
+
+/*!
+ * Get FSL SHW SCC driver version
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the SCC driver is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the SCC driver is to be stored.
+ */
+#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor)        \
+{                                                                             \
+    *(pcmajor) = (pcobject)->scc_driver_major;                                \
+    *(pcminor) = (pcobject)->scc_driver_minor;                                \
+}
+
+
+/**
+ * Get SCM hardware version
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @return               The SCM hardware version
+ */
+#define fsl_shw_pco_get_scm_version(pcobject)                                 \
+    ((pcobject)->scm_version)
+
+
+/**
+ * Get SMN hardware version
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @return               The SMN hardware version
+ */
+#define fsl_shw_pco_get_smn_version(pcobject)                                 \
+    ((pcobject)->smn_version)
+
+
+/**
+ * Get the size of an SCM block, in bytes
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @return               The size of an SCM block, in bytes.
+ */
+#define fsl_shw_pco_get_scm_block_size(pcobject)                              \
+    ((pcobject)->block_size_bytes)
+
+
+/**
+ * Get size of Black and Red RAM memory
+ *
+ * @param      pcobject    The Platform Capababilities Object to query.
+ * @param[out] black_size  A pointer to where the size of the Black RAM, in
+ *                         blocks, is to be placed.
+ * @param[out] red_size    A pointer to where the size of the Red RAM, in
+ *                         blocks, is to be placed.
+ */
+#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size)              \
+{                                                                             \
+    if ((pcobject)->scm_version == 1) {                                       \
+        *(black_size) = (pcobject)->u.scc_info.black_ram_size_blocks;           \
+        *(red_size)   = (pcobject)->u.scc_info.red_ram_size_blocks;             \
+    } else {                                                                  \
+        *(black_size) = 0;                                                    \
+        *(red_size)   = 0;                                                    \
+    }                                                                         \
+}
+
+
+/**
+ * Determine whether Secure Partitions are supported
+ *
+ * @param pcobject   The Platform Capababilities Object to query.
+ *
+ * @return 0 if secure partitions are not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_spo_supported(pcobject)                           \
+    ((pcobject)->scm_version == 2)
+
+
+/**
+ * Get the size of a Secure Partitions
+ *
+ * @param pcobject   The Platform Capababilities Object to query.
+ *
+ * @return Partition size, in bytes.  0 if Secure Partitions not supported.
+ */
+#define fsl_shw_pco_get_spo_size_bytes(pcobject)                            \
+    (((pcobject)->scm_version == 2) ?                                       \
+        ((pcobject)->u.scc2_info.partition_size_bytes) : 0 )                  \
+
+
+/**
+ * Get the number of Secure Partitions on this platform
+ *
+ * @param pcobject   The Platform Capababilities Object to query.
+ *
+ * @return Number of partitions. 0 if Secure Paritions not supported.  Note
+ *         that this returns the total number of partitions, not all may be
+ *         available to the user.
+ */
+#define fsl_shw_pco_get_spo_count(pcobject)                                 \
+    (((pcobject)->scm_version == 2) ?                                       \
+        ((pcobject)->u.scc2_info.partition_count) : 0 )                       \
+
+
+/*!
+ * Initialize a Secret Key Object.
+ *
+ * This function must be called before performing any other operation with
+ * the Object.
+ *
+ * @param skobject     The Secret Key Object to be initialized.
+ * @param skalgorithm  DES, AES, etc.
+ *
+ */
+#define fsl_shw_sko_init(skobject,skalgorithm)                          \
+{                                                                       \
+    fsl_shw_sko_t* skop = skobject;                                     \
+                                                                        \
+    skop->algorithm = skalgorithm;                                      \
+    skop->flags = 0;                                                    \
+    skop->keystore = NULL;                                              \
+    skop->pf_key = FSL_SHW_PF_KEY_PRG;                                  \
+}
+
+/*!
+ * Initialize a Secret Key Object to use a Platform Key register.
+ *
+ * This function must be called before performing any other operation with
+ * the Object.
+ *
+ * @param skobject     The Secret Key Object to be initialized.
+ * @param skalgorithm  DES, AES, etc.
+ * @param skhwkey      one of the fsl_shw_pf_key_t values.
+ *
+ */
+#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey)           \
+{                                                                       \
+    fsl_shw_sko_t* skop = skobject;                                     \
+    fsl_shw_key_alg_t alg = skalgorithm;                                \
+    fsl_shw_pf_key_t key = skhwkey;                                     \
+                                                                        \
+    skop->algorithm = alg;                                              \
+    if (alg == FSL_KEY_ALG_TDES) {                                      \
+        skop->key_length = 21;                                          \
+    }                                                                   \
+    skop->keystore = NULL;                                              \
+    skop->flags = FSL_SKO_KEY_SELECT_PF_KEY;                            \
+    skop->pf_key = key;                                                 \
+    if ((key == FSL_SHW_PF_KEY_IIM) || (key == FSL_SHW_PF_KEY_PRG)      \
+        || (key == FSL_SHW_PF_KEY_IIM_PRG)                              \
+        || (key == FSL_SHW_PF_KEY_IIM_RND)                              \
+        || (key == FSL_SHW_PF_KEY_RND)) {                               \
+        skop->flags |= FSL_SKO_KEY_ESTABLISHED;                         \
+    }                                                                   \
+}
+
+/*!
+ * Store a cleartext key in the key object.
+ *
+ * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and
+ * resetting the #FSL_SKO_KEY_ESTABLISHED flag.
+ *
+ * @param skobject     A variable of type #fsl_shw_sko_t.
+ * @param skkey        A pointer to the beginning of the key.
+ * @param skkeylen     The length, in octets, of the key.  The value should be
+ *                     appropriate to the key size supported by the algorithm.
+ *                     64 octets is the absolute maximum value allowed for this
+ *                     call.
+ */
+#define fsl_shw_sko_set_key(skobject, skkey, skkeylen)                       \
+{                                                                            \
+       (skobject)->key_length = skkeylen;                                    \
+       copy_bytes((skobject)->key, skkey, skkeylen);                         \
+       (skobject)->flags |= FSL_SKO_KEY_PRESENT;                             \
+       (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED;                        \
+}
+
+/**
+ * Set a size for the key.
+ *
+ * This function would normally be used when the user wants the key to be
+ * generated from a random source.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skkeylen   The length, in octets, of the key.  The value should be
+ *                   appropriate to the key size supported by the algorithm.
+ *                   64 octets is the absolute maximum value allowed for this
+ *                   call.
+ */
+#define fsl_shw_sko_set_key_length(skobject, skkeylen)                       \
+       (skobject)->key_length = skkeylen;
+
+
+/**
+ * Set the User ID associated with the key.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skuserid   The User ID to identify authorized users of the key.
+ */
+#define fsl_shw_sko_set_user_id(skobject, skuserid)                           \
+       (skobject)->userid = (skuserid)
+
+/**
+ * Establish a user Keystore to hold the key.
+ */
+#define fsl_shw_sko_set_keystore(skobject, user_keystore)                     \
+       (skobject)->keystore = (user_keystore)
+
+
+
+/**
+ * Set the establish key handle into a key object.
+ *
+ * The @a userid field will be used to validate the access to the unwrapped
+ * key.  This feature is not available for all platforms, nor for all
+ * algorithms and modes.
+ *
+ * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag
+ * will be cleared).
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skuserid   The User ID to verify this user is an authorized user of
+ *                   the key.
+ * @param skhandle   A @a handle from #fsl_shw_sko_get_established_info.
+ */
+#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle)        \
+{                                                                             \
+       (skobject)->userid = (skuserid);                                       \
+       (skobject)->handle = (skhandle);                                       \
+       (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED;                          \
+       (skobject)->flags &=                                                   \
+                       ~(FSL_SKO_KEY_PRESENT);   \
+}
+
+
+/**
+ * Retrieve the established-key handle from a key object.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skhandle   The location to store the @a handle of the unwrapped
+ *                   key.
+ */
+#define fsl_shw_sko_get_established_info(skobject, skhandle)                  \
+       *(skhandle) = (skobject)->handle
+
+
+/**
+ * Extract the algorithm from a key object.
+ *
+ * @param      skobject     The Key Object to be queried.
+ * @param[out] skalgorithm  A pointer to the location to store the algorithm.
+ */
+#define fsl_shw_sko_get_algorithm(skobject, skalgorithm)                      \
+       *(skalgorithm) = (skobject)->algorithm
+
+
+/**
+ * Retrieve the cleartext key from a key object that is stored in a user
+ * keystore.
+ *
+ * @param      skobject     The Key Object to be queried.
+ * @param[out] skkey        A pointer to the location to store the key.  NULL
+ *                          if the key is not stored in a user keystore.
+ */
+#define fsl_shw_sko_get_key(skobject, skkey)                                  \
+{                                                                             \
+    fsl_shw_kso_t* keystore = (skobject)->keystore;                           \
+    if (keystore != NULL) {                                                   \
+        *(skkey) = keystore->slot_get_address(keystore->user_data,            \
+                                              (skobject)->handle);            \
+    } else {                                                                  \
+        *(skkey) = NULL;                                                      \
+    }                                                                         \
+}
+
+
+/*!
+ * Determine the size of a wrapped key based upon the cleartext key's length.
+ *
+ * This function can be used to calculate the number of octets that
+ * #fsl_shw_extract_key() will write into the location at @a covered_key.
+ *
+ * If zero is returned at @a length, this means that the key length in
+ * @a key_info is not supported.
+ *
+ * @param      wkeyinfo         Information about a key to be wrapped.
+ * @param      wkeylen          Location to store the length of a wrapped
+ *                              version of the key in @a key_info.
+ */
+#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen)           \
+{                                                                       \
+    register fsl_shw_sko_t* kp = wkeyinfo;                              \
+    register uint32_t kl = kp->key_length;                              \
+    int key_blocks;                                                     \
+    int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */              \
+                                                                        \
+    if (kp->flags & FSL_SKO_KEY_SELECT_PF_KEY) {                        \
+        kl = 21;  /* 168-bit 3DES key */                                \
+    }                                                                   \
+    key_blocks = (kl + 7) / 8;                                          \
+    /* Round length up to 3DES block size for CBC mode */               \
+    *(wkeylen) = base_size + 8 * key_blocks;                            \
+}
+
+/*!
+ * Set some flags in the key object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param skobject     A variable of type #fsl_shw_sko_t.
+ * @param skflags      (One or more) ORed members of #fsl_shw_key_flags_t which
+ *                     are to be set.
+ */
+#define fsl_shw_sko_set_flags(skobject, skflags)                              \
+      (skobject)->flags |= (skflags)
+
+
+/**
+ * Clear some flags in the key object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param skobject      A variable of type #fsl_shw_sko_t.
+ * @param skflags       (One or more) ORed members of #fsl_shw_key_flags_t
+ *                      which are to be reset.
+ */
+#define fsl_shw_sko_clear_flags(skobject, skflags)                            \
+      (skobject)->flags &= ~(skflags)
+
+/**
+ * Initialize a User Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the User Context Object to initial values, and set the size
+ * of the results pool.  The mode will be set to a default of
+ * #FSL_UCO_BLOCKING_MODE.
+ *
+ * When using non-blocking operations, this sets the maximum number of
+ * operations which can be outstanding.  This number includes the counts of
+ * operations waiting to start, operation(s) being performed, and results which
+ * have not been retrieved.
+ *
+ * Changes to this value are ignored once user registration has completed.  It
+ * should be set to 1 if only blocking operations will ever be performed.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param usize        The maximum number of operations which can be
+ *                     outstanding.
+ */
+#ifdef __KERNEL__
+
+#define fsl_shw_uco_init(ucontext, usize)                                     \
+do {                                                                          \
+    fsl_shw_uco_t* uco = ucontext;                                            \
+                                                                              \
+    (uco)->pool_size = usize;                                                 \
+    (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED;           \
+    (uco)->openfd = -1;                                                       \
+    (uco)->callback = NULL;                                                   \
+    (uco)->partition = NULL;                                                  \
+    (uco)->wrap_key = FSL_SHW_PF_KEY_IIM;                                     \
+} while (0)
+
+#else /* __KERNEL__ */
+
+#define fsl_shw_uco_init(ucontext, usize)                                     \
+do {                                                                          \
+    fsl_shw_uco_t* uco = ucontext;                                            \
+                                                                              \
+    (uco)->pool_size = usize;                                                 \
+    (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED;           \
+    (uco)->openfd = -1;                                                       \
+    (uco)->callback = NULL;                                                   \
+    (uco)->wrap_key = FSL_SHW_PF_KEY_IIM;                                     \
+} while (0)
+
+#endif /* __KERNEL__ */
+
+
+/**
+ * Set the User Reference for the User Context.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uref         A value which will be passed back with a result.
+ */
+#define fsl_shw_uco_set_reference(ucontext, uref)                             \
+do {                                                                          \
+    fsl_shw_uco_t* uco = ucontext;                                            \
+                                                                              \
+    (uco)->user_ref = uref;                                                   \
+    (uco)->flags |= FSL_UCO_CONTEXT_CHANGED;                                  \
+} while (0)
+
+
+/**
+ * Set the User Reference for the User Context.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param ucallback    The function the API will invoke when an operation
+ *                     completes.
+ */
+#define fsl_shw_uco_set_callback(ucontext, ucallback)                         \
+do {                                                                          \
+    fsl_shw_uco_t* uco = ucontext;                                            \
+                                                                              \
+    (uco)->callback = ucallback;                                              \
+    (uco)->flags |= FSL_UCO_CONTEXT_CHANGED;                                  \
+} while (0)
+
+/**
+ * Set flags in the User Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uflags       ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+#define fsl_shw_uco_set_flags(ucontext, uflags)                               \
+      (ucontext)->flags |= (uflags) | FSL_UCO_CONTEXT_CHANGED
+
+
+/**
+ * Clear flags in the User Context.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uflags       ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+#define fsl_shw_uco_clear_flags(ucontext, uflags)                             \
+do {                                                                          \
+    fsl_shw_uco_t* uco = ucontext;                                            \
+                                                                              \
+    (uco)->flags &= ~(uflags);                                                \
+    (uco)->flags |= FSL_UCO_CONTEXT_CHANGED;                                  \
+} while (0)
+
+
+/**
+ * Retrieve the reference value from a Result Object.
+ *
+ * @param robject  The result object to query.
+ *
+ * @return The reference associated with the request.
+ */
+#define fsl_shw_ro_get_reference(robject)                                    \
+       (robject)->user_ref
+
+
+/**
+ * Retrieve the status code from a Result Object.
+ *
+ * @param robject  The result object to query.
+ *
+ * @return The status of the request.
+ */
+#define fsl_shw_ro_get_status(robject)                                       \
+       (robject)->code
+
+
+
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */
+/**
+ * Initialize a Hash Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the hash
+ * context object.
+ *
+ * @param      hcobject    The hash context to operate upon.
+ * @param      hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                         #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+#define fsl_shw_hco_init(hcobject, hcalgorithm)                               \
+do {                                                                          \
+     (hcobject)->algorithm = hcalgorithm;                                     \
+     (hcobject)->flags = 0;                                                   \
+     switch (hcalgorithm) {                                                   \
+     case FSL_HASH_ALG_MD5:                                                   \
+         (hcobject)->digest_length = 16;                                      \
+         (hcobject)->context_length = 16;                                     \
+         (hcobject)->context_register_length = 24;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA1:                                                  \
+         (hcobject)->digest_length = 20;                                      \
+         (hcobject)->context_length = 20;                                     \
+         (hcobject)->context_register_length = 24;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA224:                                                \
+         (hcobject)->digest_length = 28;                                      \
+         (hcobject)->context_length = 32;                                     \
+         (hcobject)->context_register_length = 36;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA256:                                                \
+         (hcobject)->digest_length = 32;                                      \
+         (hcobject)->context_length = 32;                                     \
+         (hcobject)->context_register_length = 36;                            \
+         break;                                                               \
+     default:                                                                 \
+         /* error ! */                                                        \
+         (hcobject)->digest_length = 1;                                       \
+         (hcobject)->context_length = 1;                                      \
+         (hcobject)->context_register_length = 1;                             \
+         break;                                                               \
+     }                                                                        \
+} while (0)
+
+
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-001 */
+/**
+ * Get the current hash value and message length from the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hcobject   The hash context to query.
+ * @param[out] hccontext  Pointer to the location of @a length octets where to
+ *                        store a copy of the current value of the digest.
+ * @param      hcclength  Number of octets of hash value to copy.
+ * @param[out] hcmsglen   Pointer to the location to store the number of octets
+ *                        already hashed.
+ */
+#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen)      \
+do {                                                                          \
+     memcpy(hccontext, (hcobject)->context, hcclength);                       \
+         if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224                     \
+             || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) {               \
+             *(hcmsglen) = (hcobject)->context[8];                            \
+         } else {                                                             \
+             *(hcmsglen) = (hcobject)->context[5];                            \
+         }                                                                    \
+} while (0)
+
+
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-002 */
+/**
+ * Get the hash algorithm from the hash context object.
+ *
+ * @param      hcobject    The hash context to query.
+ * @param[out] hcalgorithm Pointer to where the algorithm is to be stored.
+ */
+#define fsl_shw_hco_get_info(hcobject, hcalgorithm)                           \
+do {                                                                          \
+     *(hcalgorithm) = (hcobject)->algorithm;                                  \
+} while (0)
+
+
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-003 */
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */
+/**
+ * Set the current hash value and message length in the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hcobject  The hash context to operate upon.
+ * @param      hccontext Pointer to buffer of appropriate length to copy into
+ *                       the hash context object.
+ * @param      hcmsglen  The number of octets of the message which have
+ *                        already been hashed.
+ *
+ */
+#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen)                 \
+do {                                                                          \
+     memcpy((hcobject)->context, hccontext, (hcobject)->context_length);      \
+     if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224)                       \
+         || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) {                 \
+         (hcobject)->context[8] = hcmsglen;                                   \
+     } else {                                                                 \
+         (hcobject)->context[5] = hcmsglen;                                   \
+     }                                                                        \
+} while (0)
+
+
+/**
+ * Set flags in a Hash Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The hash context to be operated on.
+ * @param hcflags    The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+#define fsl_shw_hco_set_flags(hcobject, hcflags)                              \
+      (hcobject)->flags |= (hcflags)
+
+
+/**
+ * Clear flags in a Hash Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The hash context to be operated on.
+ * @param hcflags    The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+#define fsl_shw_hco_clear_flags(hcobject, hcflags)                            \
+      (hcobject)->flags &= ~(hcflags)
+
+
+/**
+ * Initialize an HMAC Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the HMAC
+ * context object.
+ *
+ * @param      hcobject    The HMAC context to operate upon.
+ * @param      hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                         #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+#define fsl_shw_hmco_init(hcobject, hcalgorithm)                              \
+    fsl_shw_hco_init(hcobject, hcalgorithm)
+
+
+/**
+ * Set flags in an HMAC Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The HMAC context to be operated on.
+ * @param hcflags    The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+#define fsl_shw_hmco_set_flags(hcobject, hcflags)                             \
+      (hcobject)->flags |= (hcflags)
+
+
+/**
+ * Clear flags in an HMAC Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The HMAC context to be operated on.
+ * @param hcflags    The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+#define fsl_shw_hmco_clear_flags(hcobject, hcflags)                           \
+      (hcobject)->flags &= ~(hcflags)
+
+
+/**
+ * Initialize a Symmetric Cipher Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  This will set the @a mode and @a algorithm and initialize the
+ * Object.
+ *
+ * @param scobject  The context object to operate on.
+ * @param scalg     The cipher algorithm this context will be used with.
+ * @param scmode    #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc.
+ *
+ */
+#define fsl_shw_scco_init(scobject, scalg, scmode)                            \
+do {                                                                          \
+      register uint32_t bsb;   /* block-size bytes */                         \
+                                                                              \
+      switch (scalg) {                                                        \
+      case FSL_KEY_ALG_AES:                                                   \
+          bsb = 16;                                                           \
+          break;                                                              \
+      case FSL_KEY_ALG_DES:                                                   \
+          /* fall through */                                                  \
+      case FSL_KEY_ALG_TDES:                                                  \
+          bsb = 8;                                                            \
+          break;                                                              \
+      case FSL_KEY_ALG_ARC4:                                                  \
+          bsb = 259;                                                          \
+          break;                                                              \
+      case FSL_KEY_ALG_HMAC:                                                  \
+          bsb = 1;  /* meaningless */                                         \
+          break;                                                              \
+      default:                                                                \
+          bsb = 00;                                                           \
+      }                                                                       \
+      (scobject)->block_size_bytes = bsb;                                     \
+      (scobject)->mode = scmode;                                              \
+      (scobject)->flags = 0;                                                  \
+} while (0)
+
+
+/**
+ * Set the flags for a Symmetric Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param scobject The context object to operate on.
+ * @param scflags  The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_scco_set_flags(scobject, scflags)                             \
+       (scobject)->flags |= (scflags)
+
+
+/**
+ * Clear some flags in a Symmetric Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param scobject The context object to operate on.
+ * @param scflags  The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_scco_clear_flags(scobject, scflags)                           \
+       (scobject)->flags &= ~(scflags)
+
+
+/**
+ * Set the Context (IV) for a Symmetric Cipher Context.
+ *
+ * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the
+ * context (the S-Box and pointers) for ARC4.  The full context size will
+ * be copied.
+ *
+ * @param scobject  The context object to operate on.
+ * @param sccontext A pointer to the buffer which contains the context.
+ *
+ */
+#define fsl_shw_scco_set_context(scobject, sccontext)                         \
+       memcpy((scobject)->context, sccontext,                                 \
+                  (scobject)->block_size_bytes)
+
+
+/**
+ * Get the Context for a Symmetric Cipher Context.
+ *
+ * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to
+ * retrieve context (the S-Box and pointers) for ARC4.  The full context
+ * will be copied.
+ *
+ * @param      scobject  The context object to operate on.
+ * @param[out] sccontext Pointer to location where context will be stored.
+ */
+#define fsl_shw_scco_get_context(scobject, sccontext)                         \
+       memcpy(sccontext, (scobject)->context, (scobject)->block_size_bytes)
+
+
+/**
+ * Set the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will set the Counter Value for CTR mode.
+ *
+ * @param scobject  The context object to operate on.
+ * @param sccounter The starting counter value.  The number of octets.
+ *                  copied will be the block size for the algorithm.
+ * @param scmodulus The modulus for controlling the incrementing of the
+ *                  counter.
+ *
+ */
+#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus)        \
+do {                                                                         \
+           if ((sccounter) != NULL) {                                        \
+               memcpy((scobject)->context, sccounter,                        \
+                          (scobject)->block_size_bytes);                     \
+           }                                                                 \
+           (scobject)->modulus_exp = scmodulus;                              \
+} while (0)
+
+
+/**
+ * Get the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will retrieve the Counter Value is for CTR mode.
+ *
+ * @param     scobject    The context object to query.
+ * @param[out] sccounter  Pointer to location to store the current counter
+ *                        value.  The number of octets copied will be the
+ *                        block size for the algorithm.
+ * @param[out] scmodulus  Pointer to location to store the modulus.
+ *
+ */
+#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus)        \
+do {                                                                         \
+           if ((sccounter) != NULL) {                                        \
+               memcpy(sccounter, (scobject)->context,                        \
+                          (scobject)->block_size_bytes);                     \
+           }                                                                 \
+           if ((scmodulus) != NULL) {                                        \
+               *(scmodulus) = (scobject)->modulus_exp;                       \
+           }                                                                 \
+} while (0)
+
+
+/**
+ * Initialize a Authentication-Cipher Context.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acmode    The mode for this object (only #FSL_ACC_MODE_CCM
+ *                  supported).
+ */
+#define fsl_shw_acco_init(acobject, acmode)                                   \
+do {                                                                          \
+       (acobject)->flags = 0;                                                 \
+       (acobject)->mode = (acmode);                                           \
+} while (0)
+
+
+/**
+ * Set the flags for a Authentication-Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acflags   The flags to set (one or more from
+ *                  #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_acco_set_flags(acobject, acflags)                             \
+       (acobject)->flags |= (acflags)
+
+
+/**
+ * Clear some flags in a Authentication-Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acflags   The flags to reset (one or more from
+ *                  #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_acco_clear_flags(acobject, acflags)                           \
+       (acobject)->flags &= ~(acflags)
+
+
+/**
+ * Set up the Authentication-Cipher Object for CCM mode.
+ *
+ * This will set the @a auth_object for CCM mode and save the @a ctr,
+ * and @a mac_length.  This function can be called instead of
+ * #fsl_shw_acco_init().
+ *
+ * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the
+ * MAC.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acalg     Cipher algorithm.  Only AES is supported.
+ * @param accounter The initial counter value.
+ * @param acmaclen  The number of octets used for the MAC.  Valid values are
+ *                  4, 6, 8, 10, 12, 14, and 16.
+ */
+/* Do we need to stash the +1 value of the CTR somewhere? */
+#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen)            \
+ do {                                                                         \
+      (acobject)->flags = 0;                                                  \
+      (acobject)->mode = FSL_ACC_MODE_CCM;                                    \
+      (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16;               \
+      (acobject)->cipher_ctx_info.block_size_bytes = 16;                      \
+      (acobject)->mac_length = acmaclen;                                      \
+      fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter,  \
+            FSL_CTR_MOD_128);                                                 \
+} while (0)
+
+
+/**
+ * Format the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will also set the IV and CTR values per Appendix A of NIST
+ * Special Publication 800-38C (May 2004).  It will also perform the
+ * #fsl_shw_acco_set_ccm() operation with information derived from this set of
+ * parameters.
+ *
+ * Note this function assumes the algorithm is AES.  It initializes the
+ * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the
+ * flags to be #FSL_ACCO_NIST_CCM.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param act       The number of octets used for the MAC.  Valid values are
+ *                  4, 6, 8, 10, 12, 14, and 16.
+ * @param acad      Number of octets of Associated Data (may be zero).
+ * @param acq       A value for the size of the length of @a q field.  Valid
+ *                  values are 1-8.
+ * @param acN       The Nonce (packet number or other changing value). Must
+ *                  be (15 - @a q_length) octets long.
+ * @param acQ       The value of Q (size of the payload in octets).
+ *
+ */
+#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\
+ do {                                                                         \
+        uint64_t Q = acQ;                                                     \
+        uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1);     \
+        unsigned i;                                                           \
+        uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15;      \
+        (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16;             \
+        (acobject)->cipher_ctx_info.block_size_bytes = 16;                    \
+        (acobject)->mode = FSL_ACC_MODE_CCM;                                  \
+        (acobject)->flags  = FSL_ACCO_NIST_CCM;                               \
+                                                                              \
+        /* Store away the MAC length (after calculating actual value */       \
+        (acobject)->mac_length = (act);                                       \
+        /* Set Flag field in Block 0 */                                       \
+        *((acobject)->auth_info.CCM_ctx_info.context) = bflag;                \
+        /* Set Nonce field in Block 0 */                                      \
+        memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN,             \
+                   15-(acq));                                                 \
+        /* Set Flag field in ctr */                                           \
+        *((acobject)->cipher_ctx_info.context) = (acq)-1;                     \
+        /* Update the Q (payload length) field of Block0 */                   \
+        (acobject)->q_length = acq;                                           \
+        for (i = 0; i < (acq); i++) {                                         \
+            *qptr-- = Q & 0xFF;                                               \
+            Q >>= 8;                                                          \
+        }                                                                     \
+        /* Set the Nonce field of the ctr */                                  \
+        memcpy((acobject)->cipher_ctx_info.context+1, acN, 15-(acq));         \
+        /* Clear the block counter field of the ctr */                        \
+        memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1);     \
+   } while (0)
+
+
+/**
+ * Update the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will set the IV and CTR values per Appendix A of NIST Special
+ * Publication 800-38C (May 2004).
+ *
+ * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has
+ * previously been called on the @a auth_object.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acN       The Nonce (packet number or other changing value). Must
+ *                  be (15 - @a q_length) octets long.
+ * @param acQ       The value of Q (size of the payload in octets).
+ *
+ */
+/* Do we need to stash the +1 value of the CTR somewhere? */
+#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ)                \
+  do {                                                                        \
+        uint64_t Q = acQ;                                                     \
+        unsigned i;                                                           \
+        uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15;      \
+                                                                              \
+        /* Update the Nonce field field of Block0 */                          \
+        memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN,             \
+               15 - (acobject)->q_length);                                    \
+        /* Update the Q (payload length) field of Block0 */                   \
+        for (i = 0; i < (acobject)->q_length; i++) {                          \
+            *qptr-- = Q & 0xFF;                                               \
+            Q >>= 8;                                                          \
+        }                                                                     \
+        /* Update the Nonce field of the ctr */                               \
+        memcpy((acobject)->cipher_ctx_info.context+1, acN,                    \
+               15 - (acobject)->q_length);                                    \
+   } while (0)
+
+
+/******************************************************************************
+ * Library functions
+ *****************************************************************************/
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-GEN-003 */
+/**
+ * Determine the hardware security capabilities of this platform.
+ *
+ * Though a user context object is passed into this function, it will always
+ * act in a non-blocking manner.
+ *
+ * @param  user_ctx   The user context which will be used for the query.
+ *
+ * @return  A pointer to the capabilities object.
+ */
+extern fsl_shw_pco_t* fsl_shw_get_capabilities(fsl_shw_uco_t* user_ctx);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-GEN-004 */
+/**
+ * Create an association between the the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which will be used for this association.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t* user_ctx);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-GEN-005 */
+/**
+ * Destroy the association between the the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which is no longer needed.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t* user_ctx);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-GEN-006 */
+/**
+ * Retrieve results from earlier operations.
+ *
+ * @param         user_ctx     The user's context.
+ * @param         result_size  The number of array elements of @a results.
+ * @param[in,out] results      Pointer to first of the (array of) locations to
+ *                             store results.
+ * @param[out]    result_count Pointer to store the number of results which
+ *                             were returned.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t* user_ctx,
+                                            unsigned result_size,
+                                            fsl_shw_result_t results[],
+                                            unsigned* result_count);
+
+/**
+ * Place a key into a protected location for use only by cryptographic
+ * algorithms.
+ *
+ * This only needs to be used to a) unwrap a key, or b) set up a key which
+ * could be wrapped with a later call to #fsl_shw_extract_key().  Normal
+ * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with
+ * #fsl_shw_sko_set_key() and used directly.
+ *
+ * The maximum key size supported for wrapped/unwrapped keys is 32 octets.
+ * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC
+ * key based on SHA-256.)  The key size is determined by the @a key_info.  The
+ * expected length of @a key can be determined by
+ * #fsl_shw_sko_calculate_wrapped_size()
+ *
+ * The protected key will not be available for use until this operation
+ * successfully completes.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be established.  In the create case, the key
+ *                              length must be set.
+ * @param      establish_type   How @a key will be interpreted to establish a
+ *                              key for use.
+ * @param key                   If @a establish_type is #FSL_KEY_WRAP_UNWRAP,
+ *                              this is the location of a wrapped key.  If
+ *                              @a establish_type is #FSL_KEY_WRAP_CREATE, this
+ *                              parameter can be @a NULL.  If @a establish_type
+ *                              is #FSL_KEY_WRAP_ACCEPT, this is the location
+ *                              of a plaintext key.
+ */
+extern fsl_shw_return_t fsl_shw_establish_key(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                fsl_shw_key_wrap_t establish_type,
+                                const uint8_t* key);
+
+
+/**
+ * Wrap a key and retrieve the wrapped value.
+ *
+ * A wrapped key is a key that has been cryptographically obscured.  It is
+ * only able to be used with #fsl_shw_establish_key().
+ *
+ * This function will also release the key (see #fsl_shw_release_key()) so
+ * that it must be re-established before reuse.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ * @param[out] covered_key      The location to store the wrapped key.
+ *                              (This size is based upon the maximum key size
+ *                              of 32 octets).
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                uint8_t* covered_key);
+
+/*!
+ * Read the key value from a key object.
+ *
+ * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with
+ * this call.  It has no effect on the status of the key store.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The referenced key.
+ * @param[out] key              The location to store the key value.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+					 fsl_shw_sko_t * key_info,
+					 uint8_t * key);
+
+/**
+ * De-establish a key so that it can no longer be accessed.
+ *
+ * The key will need to be re-established before it can again be used.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_release_key(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info);
+
+
+/*
+ * In userspace, partition assignments will be tracked using the user context.
+ * In kernel mode, partition assignments are based on address only.
+ */
+
+/**
+ * Allocate a block of secure memory
+ *
+ * @param       user_ctx        User context
+ * @param       size            Memory size (octets).  Note: currently only
+ *                              supports only single-partition sized blocks.
+ * @param       UMID            User Mode ID to use when registering the
+ *                              partition.
+ * @param       permissions     Permissions to initialize the partition with.
+ *                              Can be made by ORing flags from the
+ *                              #fsl_shw_permission_t.
+ *
+ * @return                      Address of the allocated memory.  NULL if the
+ *                              call was not successful.
+ */
+extern void *fsl_shw_smalloc(fsl_shw_uco_t* user_ctx,
+                             uint32_t size,
+                             const uint8_t* UMID,
+                             uint32_t permissions);
+
+
+/**
+ * Free a block of secure memory that was allocated with #fsl_shw_smalloc
+ *
+ * @param       user_ctx        User context
+ * @param       address         Address of the block of secure memory to be
+ *                              released.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_sfree(
+                                fsl_shw_uco_t* user_ctx,
+                                void* address);
+
+
+/**
+ * Check the status of a block of a secure memory that was allocated with
+ * #fsl_shw_smalloc
+ *
+ * @param       user_ctx        User context
+ * @param       address         Address of the block of secure memory to be
+ *                              released.
+ * @param       status          Status of the partition, of type
+ *                              #fsl_partition_status_t
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t* user_ctx,
+                                        void* address,
+                                        fsl_shw_partition_status_t* status);
+
+
+/**
+ * Diminish the permissions of a block of secure memory.  Note that permissions
+ * can only be revoked.
+ *
+ * @param       user_ctx        User context
+ * @param       address         Base address of the secure memory to work with
+ * @param       permissions     Permissions to initialize the partition with.
+ *                              Can be made by ORing flags from the
+ *                              #fsl_shw_permission_t.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_diminish_perms(
+        fsl_shw_uco_t* user_ctx,
+        void* address,
+        uint32_t permissions);
+
+extern fsl_shw_return_t do_scc_engage_partition(
+        fsl_shw_uco_t* user_ctx,
+        void* address,
+        const uint8_t* UMID,
+        uint32_t permissions);
+
+extern fsl_shw_return_t do_system_keystore_slot_alloc(
+        fsl_shw_uco_t* user_ctx,
+        uint32_t key_lenth,
+        uint64_t ownerid,
+        uint32_t *slot);
+
+extern fsl_shw_return_t do_system_keystore_slot_dealloc(
+        fsl_shw_uco_t* user_ctx,
+        uint64_t ownerid,
+        uint32_t slot);
+
+extern fsl_shw_return_t do_system_keystore_slot_load(
+        fsl_shw_uco_t* user_ctx,
+        uint64_t ownerid,
+        uint32_t slot,
+        const uint8_t *key,
+        uint32_t key_length);
+
+extern fsl_shw_return_t do_system_keystore_slot_encrypt(
+        fsl_shw_uco_t* user_ctx,
+        uint64_t ownerid,
+        uint32_t slot,
+        uint32_t key_length,
+        uint8_t* black_data);
+
+extern fsl_shw_return_t do_system_keystore_slot_decrypt(
+        fsl_shw_uco_t* user_ctx,
+        uint64_t ownerid,
+        uint32_t slot,
+        uint32_t key_length,
+        const uint8_t* black_data);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-COA-SKO */
+/* REQ-FSL-SHW-PINTFC-COA-SCCO */
+/* REQ-FSLSHW-PINTFC-API-BASIC-SYM-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+/**
+ * Encrypt a stream of data with a symmetric-key algorithm.
+ *
+ * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the
+ * flags of the @a sym_ctx object will control part of the operation of this
+ * function.  The #FSL_SYM_CTX_INIT flag means that there is no context info in
+ * the object.  The #FSL_SYM_CTX_LOAD means to use information in the
+ * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag
+ * means to update the object's context information after the operation has
+ * been performed.
+ *
+ * All of the data for an operation can be run through at once using the
+ * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using
+ * a @a length for the whole of the data.
+ *
+ * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function
+ * would "pick up" where the previous call left off, allowing the user to
+ * perform the larger function in smaller steps.
+ *
+ * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always
+ * be a multiple of the block size for the algorithm being used.  For proper
+ * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the
+ * block size until the last operation on the total octet stream.
+ *
+ * Some users of ARC4 may want to compute the context (S-Box and pointers) from
+ * the key before any data is available.  This may be done by running this
+ * function with a @a length of zero, with the init & save flags flags on in
+ * the @a sym_ctx.  Subsequent operations would then run as normal with the
+ * load and save flags.  Note that they key object is still required.
+ *
+ * @param         user_ctx  A user context from #fsl_shw_register_user().
+ * @param         key_info  Key and algorithm  being used for this operation.
+ * @param[in,out] sym_ctx   Info on cipher mode, state of the cipher.
+ * @param         length   Length, in octets, of the pt (and ct).
+ * @param         pt       pointer to plaintext to be encrypted.
+ * @param[out]    ct       pointer to where to store the resulting ciphertext.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ *
+ */
+extern fsl_shw_return_t fsl_shw_symmetric_encrypt(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                fsl_shw_scco_t* sym_ctx,
+                                uint32_t length,
+                                const uint8_t* pt,
+                                uint8_t* ct);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-COA-SKO */
+/* REQ-FSL-SHW-PINTFC-COA-SCCO */
+/* PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+/**
+ * Decrypt a stream of data with a symmetric-key algorithm.
+ *
+ * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the
+ * flags of the @a sym_ctx object will control part of the operation of this
+ * function.  The #FSL_SYM_CTX_INIT flag means that there is no context info in
+ * the object.  The #FSL_SYM_CTX_LOAD means to use information in the
+ * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag
+ * means to update the object's context information after the operation has
+ * been performed.
+ *
+ * All of the data for an operation can be run through at once using the
+ * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using
+ * a @a length for the whole of the data.
+ *
+ * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function
+ * would "pick up" where the previous call left off, allowing the user to
+ * perform the larger function in smaller steps.
+ *
+ * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always
+ * be a multiple of the block size for the algorithm being used.  For proper
+ * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the
+ * block size until the last operation on the total octet stream.
+ *
+ * Some users of ARC4 may want to compute the context (S-Box and pointers) from
+ * the key before any data is available.  This may be done by running this
+ * function with a @a length of zero, with the #FSL_SYM_CTX_INIT &
+ * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx.  Subsequent operations would
+ * then run as normal with the load & save flags.  Note that they key object is
+ * still required.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      key_info The key and algorithm being used in this operation.
+ * @param[in,out] sym_ctx Info on cipher mode, state of the cipher.
+ * @param      length   Length, in octets, of the ct (and pt).
+ * @param      ct       pointer to ciphertext to be decrypted.
+ * @param[out] pt       pointer to where to store the resulting plaintext.
+ *
+ * @return    A return code of type #fsl_shw_return_t
+ *
+ */
+extern fsl_shw_return_t fsl_shw_symmetric_decrypt(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                fsl_shw_scco_t* sym_ctx,
+                                uint32_t length,
+                                const uint8_t* ct,
+                                uint8_t* pt);
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-COA-HCO */
+/* REQ-FSLSHW-PINTFC-API-BASIC-HASH-005 */
+/**
+ * Hash a stream of data with a cryptographic hash algorithm.
+ *
+ * The flags in the @a hash_ctx control the operation of this function.
+ *
+ * Hashing functions work on 64 octets of message at a time.  Therefore, when
+ * any partial hashing of a long message is performed, the message @a length of
+ * each segment must be a multiple of 64.  When ready to
+ * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value.
+ *
+ * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a
+ * one-shot complete hash, including padding, will be performed.  The @a length
+ * may be any value.
+ *
+ * The first octets of a data stream can be hashed by setting the
+ * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags.  The @a length must be
+ * a multiple of 64.
+ *
+ * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by
+ * #FSL_HASH_FLAGS_SAVE.  The two in combination will allow a (multiple-of-64
+ * octets) 'middle sequence' of the data stream to be hashed with the
+ * beginning.  The @a length must again be a multiple of 64.
+ *
+ * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously
+ * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and
+ * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the
+ * stream.  The @a length may be any value.
+ *
+ * If the user program wants to do the padding for the hash, it can leave off
+ * the #FSL_HASH_FLAGS_FINALIZE flag.  The @a length must then be a multiple of
+ * 64 octets.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param[in,out] hash_ctx Hashing algorithm and state of the cipher.
+ * @param      msg       Pointer to the data to be hashed.
+ * @param      length    Length, in octets, of the @a msg.
+ * @param[out] result    If not null, pointer to where to store the hash
+ *                       digest.
+ * @param      result_len Number of octets to store in @a result.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hash(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_hco_t* hash_ctx,
+                                const uint8_t* msg,
+                                uint32_t length,
+                                uint8_t* result,
+                                uint32_t result_len);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-API-BASIC-HMAC-001 */
+/**
+ * Precompute the Key hashes for an HMAC operation.
+ *
+ * This function may be used to calculate the inner and outer precomputes,
+ * which are the hash contexts resulting from hashing the XORed key for the
+ * 'inner hash' and the 'outer hash', respectively, of the HMAC function.
+ *
+ * After execution of this function, the @a hmac_ctx will contain the
+ * precomputed inner and outer contexts, so that they may be used by
+ * #fsl_shw_hmac().  The flags of @a hmac_ctx will be updated with
+ * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence.  In addtion, the
+ * #FSL_HMAC_FLAGS_INIT flag will be set.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      key_info  The key being used in this operation.  Key must be
+ *                       1 to 64 octets long.
+ * @param[in,out] hmac_ctx The context which controls, by its flags and
+ *                         algorithm, the operation of this function.
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hmac_precompute(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                fsl_shw_hmco_t* hmac_ctx);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-BASIC-HMAC-002 */
+/**
+ * Continue, finalize, or one-shot an HMAC operation.
+ *
+ * There are a number of ways to use this function.  The flags in the
+ * @a hmac_ctx object will determine what operations occur.
+ *
+ * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from
+ * the @a key_info, or from the precomputed inner hash value in the
+ * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT.
+ *
+ * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued
+ * from the ongoing inner hash computation in the @a hmac_ctx.
+ *
+ * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed,
+ * the outer hash will be performed, and the @a result will be generated.
+ *
+ * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest
+ * value will be stored in the ongoing inner hash computation field of the @a
+ * hmac_ctx.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param key_info       If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx,
+ *                       this is the key being used in this operation, and the
+ *                       IPAD.  If #FSL_HMAC_FLAGS_INIT is set in the @a
+ *                       hmac_ctx and @a key_info is NULL, then
+ *                       #fsl_shw_hmac_precompute() has been used to populate
+ *                       the @a inner_precompute and @a outer_precompute
+ *                       contexts.  If #FSL_HMAC_FLAGS_INIT is not set, this
+ *                       parameter is ignored.
+
+ * @param[in,out] hmac_ctx The context which controls, by its flags and
+ *                       algorithm, the operation of this function.
+ * @param      msg               Pointer to the message to be hashed.
+ * @param      length            Length, in octets, of the @a msg.
+ * @param[out] result            Pointer, of @a result_len octets, to where to
+ *                               store the HMAC.
+ * @param      result_len        Length of @a result buffer.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hmac(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_sko_t* key_info,
+                                fsl_shw_hmco_t* hmac_ctx,
+                                const uint8_t* msg,
+                                uint32_t length,
+                                uint8_t* result,
+                                uint32_t result_len);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */
+/**
+ * Get random data.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    The number of octets of @a data being requested.
+ * @param[out] data      A pointer to a location of @a length octets to where
+ *                       random data will be returned.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_get_random(
+                                fsl_shw_uco_t* user_ctx,
+                                uint32_t length,
+                                uint8_t* data);
+
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-003 */
+/**
+ * Add entropy to random number generator.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    Number of bytes at @a data.
+ * @param      data      Entropy to add to random number generator.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_add_entropy(
+                                fsl_shw_uco_t* user_ctx,
+                                uint32_t length,
+                                uint8_t* data);
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-COA-SKO */
+/**
+ * Perform Generation-Encryption by doing a Cipher and a Hash.
+ *
+ * Generate the authentication value @a auth_value as well as encrypt the @a
+ * payload into @a ct (the ciphertext).  This is a one-shot function, so all of
+ * the @a auth_data and the total message @a payload must passed in one call.
+ * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT
+ * and #FSL_ACCO_CTX_FINALIZE.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      auth_ctx         Controlling object for Authenticate-decrypt.
+ * @param      cipher_key_info  The key being used for the cipher part of this
+ *                              operation.  In CCM mode, this key is used for
+ *                              both parts.
+ * @param      auth_key_info    The key being used for the authentication part
+ *                              of this operation.  In CCM mode, this key is
+ *                              ignored and may be NULL.
+ * @param      auth_data_length Length, in octets, of @a auth_data.
+ * @param      auth_data        Data to be authenticated but not encrypted.
+ * @param      payload_length   Length, in octets, of @a payload.
+ * @param      payload          Pointer to the plaintext to be encrypted.
+ * @param[out] ct               Pointer to the where the encrypted @a payload
+ *                              will be stored.  Must be @a payload_length
+ *                              octets long.
+ * @param[out] auth_value       Pointer to where the generated authentication
+ *                              field will be stored. Must be as many octets as
+ *                              indicated by MAC length in the @a function_ctx.
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_gen_encrypt(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_acco_t* auth_ctx,
+                                fsl_shw_sko_t* cipher_key_info,
+                                fsl_shw_sko_t* auth_key_info,
+                                uint32_t auth_data_length,
+                                const uint8_t* auth_data,
+                                uint32_t payload_length,
+                                const uint8_t* payload,
+                                uint8_t* ct,
+                                uint8_t* auth_value);
+
+/* REQ-FSL-SHW-PINTFC-COA-UCO */
+/* REQ-FSL-SHW-PINTFC-COA-SKO */
+/**
+ * Perform Authentication-Decryption in Cipher + Hash.
+ *
+ * This function will perform a one-shot decryption of a data stream as well as
+ * authenticate the authentication value.  This is a one-shot function, so all
+ * of the @a auth_data and the total message @a payload must passed in one
+ * call.  This also means that the flags in the @a auth_ctx must be
+ * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      auth_ctx         Controlling object for Authenticate-decrypt.
+ * @param      cipher_key_info  The key being used for the cipher part of this
+ *                              operation.  In CCM mode, this key is used for
+ *                              both parts.
+ * @param      auth_key_info    The key being used for the authentication part
+ *                              of this operation.  In CCM mode, this key is
+ *                              ignored and may be NULL.
+ * @param      auth_data_length Length, in octets, of @a auth_data.
+ * @param      auth_data        Data to be authenticated but not decrypted.
+ * @param      payload_length   Length, in octets, of @a ct and @a pt.
+ * @param      ct               Pointer to the encrypted input stream.
+ * @param      auth_value       The (encrypted) authentication value which will
+ *                              be authenticated.  This is the same data as the
+ *                              (output) @a auth_value argument to
+ *                              #fsl_shw_gen_encrypt().
+ * @param[out] payload          Pointer to where the plaintext resulting from
+ *                              the decryption will be stored.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_auth_decrypt(
+                                fsl_shw_uco_t* user_ctx,
+                                fsl_shw_acco_t* auth_ctx,
+                                fsl_shw_sko_t* cipher_key_info,
+                                fsl_shw_sko_t* auth_key_info,
+                                uint32_t auth_data_length,
+                                const uint8_t* auth_data,
+                                uint32_t payload_length,
+                                const uint8_t* ct,
+                                const uint8_t* auth_value,
+                                uint8_t* payload);
+
+/*!
+ * Cause the hardware to create a new random key for secure memory use.
+ *
+ * Have the hardware use the secure hardware random number generator to load a
+ * new secret key into the hardware random key register.  It will not be made
+ * active without a call to #fsl_shw_select_pf_key().
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+#ifdef __KERNEL__
+
+extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx);
+
+#else
+
+#define fsl_shw_gen_random_pf_key(user_ctx) FSL_RETURN_NO_RESOURCE_S
+
+#endif				/* __KERNEL__ */
+
+/*!
+ * Retrieve the detected tamper event.
+ *
+ * Note that if more than one event was detected, this routine will only ever
+ * return one of them.
+ *
+ * @param[in]  user_ctx         A user context from #fsl_shw_register_user().
+ * @param[out] tamperp          Location to store the tamper information.
+ * @param[out] timestampp       Locate to store timestamp from hardwhare when
+ *                              an event was detected.
+ *
+ *
+ * @return    A return code of type #fsl_shw_return_t (for instance, if the platform
+ *            is not in a fail state.
+ */
+#ifdef __KERNEL__
+
+extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_tamper_t * tamperp,
+						  uint64_t * timestampp);
+#else
+
+#define fsl_shw_read_tamper_event(user_ctx,tamperp,timestampp)         \
+    FSL_RETURN_NO_RESOURCE_S
+
+#endif				/* __KERNEL__ */
+
+/*****************************************************************************
+ *
+ * Functions internal to SHW driver.
+ *
+*****************************************************************************/
+
+fsl_shw_return_t
+do_scc_encrypt_region(fsl_shw_uco_t* user_ctx,
+                      void* partition_base, uint32_t offset_bytes,
+                      uint32_t byte_count, uint8_t* black_data,
+                      uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode);
+
+fsl_shw_return_t
+do_scc_decrypt_region(fsl_shw_uco_t* user_ctx,
+                      void* partition_base, uint32_t offset_bytes,
+                      uint32_t byte_count, const uint8_t* black_data,
+                      uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode);
+
+
+/*****************************************************************************
+ *
+ * Functions available to other SHW-family drivers.
+ *
+*****************************************************************************/
+
+#ifdef __KERNEL__
+/**
+ * Add an entry to a work/result queue.
+ *
+ * @param pool  Pointer to list structure
+ * @param entry Entry to place at tail of list
+ *
+ * @return void
+ */
+inline static void SHW_ADD_QUEUE_ENTRY(shw_queue_t* pool,
+                                       shw_queue_entry_t* entry)
+{
+    os_lock_context_t lock_context;
+
+    entry->next = NULL;
+    os_lock_save_context(shw_queue_lock, lock_context);
+
+    if (pool->tail != NULL) {
+        pool->tail->next = entry;
+    } else {
+        /* Queue was empty, so this is also the head. */
+        pool->head = entry;
+    }
+    pool->tail = entry;
+
+    os_unlock_restore_context(shw_queue_lock, lock_context);
+
+    return;
+
+
+}
+
+
+/**
+ * Get first entry on the queue and remove it from the queue.
+ *
+ * @return Pointer to first entry, or NULL if none.
+ */
+inline static shw_queue_entry_t* SHW_POP_FIRST_ENTRY(shw_queue_t* queue)
+{
+    shw_queue_entry_t* entry;
+    os_lock_context_t lock_context;
+
+    os_lock_save_context(shw_queue_lock, lock_context);
+
+    entry = queue->head;
+
+    if (entry != NULL) {
+        queue->head = entry->next;
+        entry->next = NULL;
+        /* If this was only entry, clear the tail. */
+        if (queue->tail == entry) {
+            queue->tail = NULL;
+        }
+    }
+
+    os_unlock_restore_context(shw_queue_lock, lock_context);
+
+    return entry;
+}
+
+
+
+/**
+ * Remove an entry from the list.
+ *
+ * If the entry not on the queue, no error will be returned.
+ *
+ * @param pool Pointer to work queue
+ * @param entry Entry to remove from queue
+ *
+ * @return void
+ *
+ */
+inline static void SHW_QUEUE_REMOVE_ENTRY(shw_queue_t* pool,
+                                   shw_queue_entry_t* entry)
+{
+    os_lock_context_t lock_context;
+
+    os_lock_save_context(shw_queue_lock, lock_context);
+
+    /* Check for quick case.*/
+    if (pool->head == entry) {
+        pool->head = entry->next;
+        entry->next = NULL;
+        if (pool->tail == entry) {
+            pool->tail = NULL;
+        }
+    } else {
+        register shw_queue_entry_t* prev = pool->head;
+
+        /* We know it is not the head, so start looking at entry after head. */
+        while (prev->next) {
+            if (prev->next != entry) {
+                prev = prev->next; /* Try another */
+                continue;
+            } else {
+                /* Unlink from chain. */
+                prev->next = entry->next;
+                entry->next = NULL;
+                /* If last in chain, update tail. */
+                if (pool->tail == entry) {
+                    pool->tail = prev;
+                }
+                break;
+            }
+        } /* while */
+    }
+
+    os_unlock_restore_context(shw_queue_lock, lock_context);
+
+    return;
+}
+#endif /* __KERNEL__ */
+
+
+/*****************************************************************************
+ *
+ * Functions available to User-Mode API functions
+ *
+ ****************************************************************************/
+#ifndef __KERNEL__
+
+
+ /**
+ * Sanity checks the user context object fields to ensure that they make some
+ * sense before passing the uco as a parameter.
+ *
+ * @brief Verify the user context object
+ *
+ * @param  uco  user context object
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t validate_uco(fsl_shw_uco_t *uco);
+
+
+/**
+ * Initialize a request block to go to the driver.
+ *
+ * @param hdr      Pointer to request block header
+ * @param user_ctx Pointer to user's context
+ *
+ * @return void
+ */
+inline static void init_req(struct shw_req_header* hdr,
+                            fsl_shw_uco_t* user_ctx)
+{
+    hdr->flags = user_ctx->flags;
+    hdr->user_ref = user_ctx->user_ref;
+    hdr->code = FSL_RETURN_ERROR_S;
+
+    return;
+}
+
+
+/**
+ * Send a request block off to the driver.
+ *
+ * If this is a non-blocking request, then req will be freed.
+ *
+ * @param type  The type of request being sent
+ * @param req   Pointer to the request block
+ * @param ctx   Pointer to user's context
+ *
+ * @return code from driver if ioctl() succeeded, otherwise
+ *              FSL_RETURN_INTERNAL_ERROR_S.
+ */
+inline static fsl_shw_return_t send_req(shw_user_request_t type,
+                                        struct shw_req_header* req,
+                                        fsl_shw_uco_t* ctx)
+{
+    fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+    unsigned blocking = ctx->flags & FSL_UCO_BLOCKING_MODE;
+    int code;
+
+    code = ioctl(ctx->openfd, SHW_IOCTL_REQUEST + type, req);
+
+    if (code == 0) {
+        if (blocking) {
+            ret = req->code;
+        } else {
+            ret = FSL_RETURN_OK_S;
+        }
+    } else {
+#ifdef FSL_DEBUG
+        fprintf(stderr, "SHW: send_req failed with (%d), %s\n", errno,
+                strerror(errno));
+#endif
+    }
+
+    if (blocking) {
+        free(req);
+    }
+
+    return ret;
+}
+
+
+#endif				/* no __KERNEL__ */
+
+#if defined(FSL_HAVE_DRYICE)
+/* Some kernel functions */
+void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key,
+			    int key_count);
+void fsl_shw_permute1_bytes_to_words(const uint8_t * key,
+				     uint32_t * permuted_key, int key_count);
+
+#define PFKEY_TO_STR(key_in)                                    \
+({                                                              \
+    di_key_t key = key_in;                                      \
+                                                                \
+    ((key == DI_KEY_FK) ? "IIM" :                               \
+     ((key == DI_KEY_PK) ? "PRG" :                              \
+      ((key == DI_KEY_RK) ? "RND" :                             \
+       ((key == DI_KEY_FPK) ? "IIM_PRG" :                       \
+        ((key == DI_KEY_FRK) ? "IIM_RND" : "unk")))));          \
+})
+
+#ifdef DIAG_SECURITY_FUNC
+extern const char *di_error_string(int code);
+#endif
+
+#endif				/* HAVE DRYICE */
+
+#endif				/* SHW_DRIVER_H */
diff --git a/drivers/mxc/security/rng/include/shw_hash.h b/drivers/mxc/security/rng/include/shw_hash.h
new file mode 100644
index 000000000000..d0e7eed0e1d2
--- /dev/null
+++ b/drivers/mxc/security/rng/include/shw_hash.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @file shw_hash.h
+ *
+ * This file contains definitions for use of the (internal) SHW hash
+ * software computation.  It defines the usual three steps:
+ *
+ * - #shw_hash_init()
+ * - #shw_hash_update()
+ * - #shw_hash_final()
+ *
+ * The only other item of note to callers is #SHW_HASH_LEN, which is the number
+ * of bytes calculated for the hash.
+ */
+
+#ifndef SHW_HASH_H
+#define SHW_HASH_H
+
+/*! Define which gives the number of bytes available in an hash result */
+#define SHW_HASH_LEN 32
+
+/* Define which matches block length in bytes of the underlying hash */
+#define SHW_HASH_BLOCK_LEN 64
+
+/* "Internal" define which matches SHA-256 state size (32-bit words) */
+#define SHW_HASH_STATE_WORDS 8
+
+/* "Internal" define which matches word length in blocks of the underlying
+   hash. */
+#define SHW_HASH_BLOCK_WORD_SIZE 16
+
+#define SHW_HASH_STATE_SIZE 32
+
+/*!
+ * State for a SHA-1/SHA-2 Hash
+ *
+ * (Note to maintainers: state needs to be updated to uint64_t to handle
+ * SHA-384/SHA-512)... And bit_count to uint128_t (heh).
+ */
+typedef struct shw_hash_state {
+	unsigned int partial_count_bytes;	/*!< Number of bytes of message sitting
+						 * in @c partial_block */
+	uint8_t partial_block[SHW_HASH_BLOCK_LEN];	/*!< Data waiting to be processed as a block  */
+	uint32_t state[SHW_HASH_STATE_WORDS];	/*!< Current hash state variables */
+	uint64_t bit_count;	/*!< Number of bits sent through the update function */
+} shw_hash_state_t;
+
+/*!
+ * Initialize the hash state structure
+ *
+ * @param state     Address of hash state structure.
+ * @param algorithm Which hash algorithm to use (must be FSL_HASH_ALG_SHA256)
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hash_init(shw_hash_state_t * state,
+			       fsl_shw_hash_alg_t algorithm);
+
+/*!
+ * Put data into the hash calculation
+ *
+ * @param state     Address of hash state structure.
+ * @param msg       Address of the message data for the hash.
+ * @param msg_len   Number of bytes of @c msg.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hash_update(shw_hash_state_t * state,
+				 const uint8_t * msg, unsigned int msg_len);
+
+/*!
+ * Calculate the final hash value
+ *
+ * @param state     Address of hash state structure.
+ * @param hash      Address of location to store the hash.
+ * @param hash_len  Number of bytes of @c hash to be stored.
+ *
+ * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if
+ * hash_len is too long, otherwise an error code.
+ */
+fsl_shw_return_t shw_hash_final(shw_hash_state_t * state,
+				uint8_t * hash, unsigned int hash_len);
+
+#endif				/* SHW_HASH_H */
diff --git a/drivers/mxc/security/rng/include/shw_hmac.h b/drivers/mxc/security/rng/include/shw_hmac.h
new file mode 100644
index 000000000000..99d373149f51
--- /dev/null
+++ b/drivers/mxc/security/rng/include/shw_hmac.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @file shw_hmac.h
+ *
+ * This file contains definitions for use of the (internal) SHW HMAC
+ * software computation.  It defines the usual three steps:
+ *
+ * - #shw_hmac_init()
+ * - #shw_hmac_update()
+ * - #shw_hmac_final()
+ *
+ * The only other item of note to callers is #SHW_HASH_LEN, which is the number
+ * of bytes calculated for the HMAC.
+ */
+
+#ifndef SHW_HMAC_H
+#define SHW_HMAC_H
+
+#include "shw_hash.h"
+
+/*!
+ * State for an HMAC
+ *
+ * Note to callers: This structure contains key material and should be kept in
+ * a secure location, such as internal RAM.
+ */
+typedef struct shw_hmac_state {
+	shw_hash_state_t inner_hash;	/*!< Current state of inner hash */
+	shw_hash_state_t outer_hash;	/*!< Current state of outer hash */
+} shw_hmac_state_t;
+
+/*!
+ * Initialize the HMAC state structure with the HMAC key
+ *
+ * @param state     Address of HMAC state structure.
+ * @param key       Address of the key to be used for the HMAC.
+ * @param key_len   Number of bytes of @c key.  This must not be greater than
+ *                  the block size of the underlying hash (#SHW_HASH_BLOCK_LEN).
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state,
+			       const uint8_t * key, unsigned int key_len);
+
+/*!
+ * Put data into the HMAC calculation
+ *
+ * @param state     Address of HMAC state structure.
+ * @param msg       Address of the message data for the HMAC.
+ * @param msg_len   Number of bytes of @c msg.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state,
+				 const uint8_t * msg, unsigned int msg_len);
+
+/*!
+ * Calculate the final HMAC
+ *
+ * @param state     Address of HMAC state structure.
+ * @param hmac      Address of location to store the HMAC.
+ * @param hmac_len  Number of bytes of @c mac to be stored.  Probably best if
+ *                  this value is no greater than #SHW_HASH_LEN.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state,
+				uint8_t * hmac, unsigned int hmac_len);
+
+#endif				/* SHW_HMAC_H */
diff --git a/drivers/mxc/security/rng/include/shw_internals.h b/drivers/mxc/security/rng/include/shw_internals.h
new file mode 100644
index 000000000000..c917ec813162
--- /dev/null
+++ b/drivers/mxc/security/rng/include/shw_internals.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef SHW_INTERNALS_H
+#define SHW_INTERNALS_H
+
+/*! @file shw_internals.h
+ *
+ *  This file contains definitions which are internal to the SHW driver.
+ *
+ *  This header file should only ever be included by shw_driver.c
+ *
+ *  Compile-time flags minimally needed:
+ *
+ *  @li Some sort of platform flag.
+ *
+ */
+
+#include "portable_os.h"
+#include "shw_driver.h"
+
+/*! @defgroup shwcompileflags SHW Compile Flags
+ *
+ * These are flags which are used to configure the SHW driver at compilation
+ * time.
+ *
+ * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on
+ * a compile command) has defined a given preprocessor symbol.  If a given
+ * symbol is defined, then @c \#ifdef \<symbol\> will succeed.  Some symbols
+ * described below default to not having a definition, i.e. they are undefined.
+ *
+ */
+
+/*! @addtogroup shwcompileflags */
+/*! @{ */
+#ifndef SHW_MAJOR_NODE
+/*!
+ * This should be configured in a Makefile/compile command line.  It is the
+ * value the driver will use to register itself as a device driver for a
+ * /dev/node file.  Zero means allow (Linux) to assign a value.  Any positive
+ * number will be attempted as the registration value, to allow for
+ * coordination with the creation/existence of a /dev/fsl_shw (for instance)
+ * file in the filesystem.
+ */
+#define SHW_MAJOR_NODE 0
+#endif
+
+/* Temporarily define compile-time flags to make Doxygen happy and allow them
+   to get into the documentation. */
+#ifdef DOXYGEN_HACK
+
+/*!
+ * Turn on compilation of run-time operational, debug, and error messages.
+ *
+ * This flag is undefined by default.
+ */
+/* REQ-FSLSHW-DEBUG-001 */
+#define SHW_DEBUG
+#undef SHW_DEBUG
+
+/*! @} */
+#endif				/* end DOXYGEN_HACK */
+
+#ifndef SHW_DRIVER_NAME
+/*! @addtogroup shwcompileflags */
+/*! @{ */
+/*! Name the driver will use to register itself to the kernel as the driver for
+ *  the #shw_major_node and interrupt handling. */
+#define SHW_DRIVER_NAME "fsl_shw"
+/*! @} */
+#endif
+/*#define SHW_DEBUG*/
+
+/*!
+ * Add a user context onto the list of registered users.
+ *
+ * Place it at the head of the #user_list queue.
+ *
+ * @param ctx  A pointer to a user context
+ *
+ * @return void
+ */
+inline static void SHW_ADD_USER(fsl_shw_uco_t * ctx)
+{
+	os_lock_context_t lock_context;
+
+	os_lock_save_context(shw_queue_lock, lock_context);
+	ctx->next = user_list;
+	user_list = ctx;
+	os_unlock_restore_context(shw_queue_lock, lock_context);
+
+}
+
+/*!
+ * Remove a user context from the list of registered users.
+ *
+ * @param ctx  A pointer to a user context
+ *
+ * @return void
+ *
+ */
+inline static void SHW_REMOVE_USER(fsl_shw_uco_t * ctx)
+{
+	fsl_shw_uco_t *prev_ctx = user_list;
+	os_lock_context_t lock_context;
+
+	os_lock_save_context(shw_queue_lock, lock_context);
+
+	if (prev_ctx == ctx) {
+		/* Found at head, so just set new head */
+		user_list = ctx->next;
+	} else {
+		for (; (prev_ctx != NULL); prev_ctx = prev_ctx->next) {
+			if (prev_ctx->next == ctx) {
+				prev_ctx->next = ctx->next;
+				break;
+			}
+		}
+	}
+	os_unlock_restore_context(shw_queue_lock, lock_context);
+}
+
+static void shw_user_callback(fsl_shw_uco_t * uco);
+
+/* internal functions */
+static os_error_code shw_setup_user_driver_interaction(void);
+static void shw_cleanup(void);
+
+static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco);
+static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx,
+				      void *user_mode_pco_request);
+static os_error_code get_results(fsl_shw_uco_t * user_ctx,
+				 void *user_mode_result_req);
+static os_error_code get_random(fsl_shw_uco_t * user_ctx,
+				void *user_mode_get_random_req);
+static os_error_code add_entropy(fsl_shw_uco_t * user_ctx,
+				 void *user_mode_add_entropy_req);
+
+void* wire_user_memory(void* address, uint32_t length, void** page_ctx);
+void unwire_user_memory(void** page_ctx);
+os_error_code map_user_memory(struct vm_area_struct* vma,
+                              uint32_t physical_addr, uint32_t size);
+os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size);
+
+#if defined(LINUX_VERSION_CODE)
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Device Driver for FSL SHW API");
+
+#endif				/* LINUX_VERSION_CODE */
+
+#endif				/* SHW_INTERNALS_H */
diff --git a/drivers/mxc/security/rng/rng_driver.c b/drivers/mxc/security/rng/rng_driver.c
new file mode 100644
index 000000000000..5664e11860fe
--- /dev/null
+++ b/drivers/mxc/security/rng/rng_driver.c
@@ -0,0 +1,1150 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*! @file rng_driver.c
+ *
+ * This is the driver code for the hardware Random Number Generator (RNG).
+ *
+ * It provides the following functions to callers:
+ *   fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t* user_ctx,
+ *                                       uint32_t length,
+ *                                       uint8_t* data);
+ *
+ *   fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t* user_ctx,
+ *                                        uint32_t length,
+ *                                        uint8_t* data);
+ *
+ * The life of the driver starts at boot (or module load) time, with a call by
+ * the kernel to #rng_init().  As part of initialization, a background task
+ * running #rng_entropy_task() will be created.
+ *
+ * The life of the driver ends when the kernel is shutting down (or the driver
+ * is being unloaded).  At this time, #rng_shutdown() is called.  No function
+ * will ever be called after that point.  In the case that the driver is
+ * reloaded, a new copy of the driver, with fresh global values, etc., is
+ * loaded, and there will be a new call to #rng_init().
+ *
+ * A call to fsl_shw_get_random() gets converted into a work entry which is
+ * queued and handed off to a background task for fulfilment.  This provides
+ * for a single thread of control for reading the RNG's FIFO register, which
+ * might otherwise underflow if not carefully managed.
+ *
+ * A call to fsl_shw_add_entropy() will cause the additional entropy to
+ * be passed directly into the hardware.
+ *
+ * In a debug configuration, it provides the following kernel functions:
+ * rng_return_t rng_read_register(uint32_t byte_offset, uint32_t* valuep);
+ * rng_return_t rng_write_register(uint32_t byte_offset, uint32_t value);
+ *  @ingroup RNG
+ */
+
+#include "portable_os.h"
+#include "fsl_shw.h"
+#include "rng_internals.h"
+
+#ifdef FSL_HAVE_SCC2
+#include <linux/mxc_scc2_driver.h>
+#else
+#include <linux/mxc_scc_driver.h>
+#endif
+
+#if defined(RNG_DEBUG) || defined(RNG_ENTROPY_DEBUG) ||                     \
+    defined(RNG_REGISTER_DEBUG)
+
+#include <diagnostic.h>
+
+#else
+
+#define LOG_KDIAG_ARGS(fmt, ...)
+#define LOG_KDIAG(diag)
+
+#endif
+
+/* These are often handy */
+#ifndef FALSE
+/*! Non-true value for arguments, return values. */
+#define FALSE 0
+#endif
+#ifndef TRUE
+/*! True value for arguments, return values. */
+#define TRUE 1
+#endif
+
+/******************************************************************************
+ *
+ *  Global / Static Variables
+ *
+ *****************************************************************************/
+
+/*!
+ * This is type void* so that a) it cannot directly be dereferenced, and b)
+ * pointer arithmetic on it will function for the byte offsets in rng_rnga.h
+ * and rng_rngc.h
+ *
+ * rng_base is the location in the iomap where the RNG's registers
+ * (and memory) start.
+ *
+ * The referenced data is declared volatile so that the compiler will
+ * not make any assumptions about the value of registers in the RNG,
+ * and thus will always reload the register into CPU memory before
+ * using it (i.e. wherever it is referenced in the driver).
+ *
+ * This value should only be referenced by the #RNG_READ_REGISTER and
+ * #RNG_WRITE_REGISTER macros and their ilk.  All dereferences must be
+ * 32 bits wide.
+ */
+static volatile void *rng_base;
+
+/*!
+ * Flag to say whether interrupt handler has been registered for RNG
+ * interrupt */
+static int rng_irq_set = FALSE;
+
+/*!
+ * Size of the RNG's OUTPUT_FIFO, in words.  Retrieved with
+ * #RNG_GET_FIFO_SIZE() during driver initialization.
+ */
+static int rng_output_fifo_size;
+
+/*! Major number for device driver. */
+static int rng_major;
+
+/*! Registration handle for registering driver with OS. */
+os_driver_reg_t rng_reg_handle;
+
+/*!
+ * Internal flag to know whether RNG is in Failed state (and thus many
+ * registers are unavailable).  If the value ever goes to #RNG_STATUS_FAILED,
+ * it will never change.
+ */
+static volatile rng_status_t rng_availability = RNG_STATUS_INITIAL;
+
+/*!
+ * Global lock for the RNG driver.  Mainly used for entries on the RNG work
+ * queue.
+ */
+static os_lock_t rng_queue_lock = NULL;
+
+/*!
+ * Queue for the RNG task to process.
+ */
+static shw_queue_t rng_work_queue;
+
+/*!
+ * Flag to say whether task initialization succeeded.
+ */
+static unsigned task_started = FALSE;
+/*!
+ * Waiting queue for RNG SELF TESTING
+ */
+static DECLARE_COMPLETION(rng_self_testing);
+static DECLARE_COMPLETION(rng_seed_done);
+/*!
+ *  Object for blocking-mode callers of RNG driver to sleep.
+ */
+OS_WAIT_OBJECT(rng_wait_queue);
+
+/******************************************************************************
+ *
+ *  Function Implementations - Externally Accessible
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/* fn rng_init()                                                             */
+/*****************************************************************************/
+/*!
+ * Initialize the driver.
+ *
+ * Set up the driver to have access to RNG device registers and verify that
+ * it appears to be a proper working device.
+ *
+ * Set up interrupt handling.  Assure RNG is ready to go and (possibly) set it
+ * into High Assurance mode.  Create a background task to run
+ * #rng_entropy_task().  Set up up a callback with the SCC driver should the
+ * security alarm go off.  Tell the kernel that the driver is here.
+ *
+ * This routine is called during kernel init or module load (insmod).
+ *
+ * The function will fail in one of two ways: Returning OK to the caller so
+ * that kernel startup / driver initialization completes, or returning an
+ * error.  In the success case, the function could set the rng_avaailability to
+ * RNG_STATUS_FAILED so that only minimal support (e.g. register peek / poke)
+ * is available in the driver.
+ *
+ * @return a call to os_dev_init_return()
+ */
+OS_DEV_INIT(rng_init)
+{
+	struct clk *clk;
+	os_error_code return_code = OS_ERROR_FAIL_S;
+	rng_availability = RNG_STATUS_CHECKING;
+
+#if !defined(FSL_HAVE_RNGA)
+	INIT_COMPLETION(rng_self_testing);
+	INIT_COMPLETION(rng_seed_done);
+#endif
+	rng_work_queue.head = NULL;
+	rng_work_queue.tail = NULL;
+
+	clk = clk_get(NULL, "rng_clk");
+
+	// Check that the clock was found
+	if (IS_ERR(clk)) {
+		LOG_KDIAG("RNG: Failed to find rng_clock.");
+		return_code = OS_ERROR_FAIL_S;
+		goto check_err;
+	}
+
+	clk_enable(clk);
+
+	os_printk(KERN_INFO "RNG Driver: Loading\n");
+
+	return_code = rng_map_RNG_memory();
+	if (return_code != OS_ERROR_OK_S) {
+		rng_availability = RNG_STATUS_UNIMPLEMENTED;
+		LOG_KDIAG_ARGS("RNG: Driver failed to map RNG registers. %d",
+			       return_code);
+		goto check_err;
+	}
+	LOG_KDIAG_ARGS("RNG Driver: rng_base is 0x%08x", (uint32_t) rng_base);
+	/*Check SCC keys are fused */
+	if (RNG_HAS_ERROR()) {
+		if (RNG_HAS_BAD_KEY()) {
+#ifdef RNG_DEBUG
+#if !defined(FSL_HAVE_RNGA)
+			LOG_KDIAG("ERROR: BAD KEYS SELECTED");
+			{
+				uint32_t rngc_status =
+				    RNG_READ_REGISTER(RNGC_STATUS);
+				uint32_t rngc_error =
+				    RNG_READ_REGISTER(RNGC_ERROR);
+				LOG_KDIAG_ARGS
+				    ("status register: %08x, error status: %08x",
+				     rngc_status, rngc_error);
+			}
+#endif
+#endif
+			rng_availability = RNG_STATUS_FAILED;
+			return_code = OS_ERROR_FAIL_S;
+			goto check_err;
+		}
+	}
+
+	/* Check RNG configuration and status */
+	return_code = rng_grab_config_values();
+	if (return_code != OS_ERROR_OK_S) {
+		rng_availability = RNG_STATUS_UNIMPLEMENTED;
+		goto check_err;
+	}
+
+	/* Masking All Interrupts */
+	/* They are unmasked later in rng_setup_interrupt_handling() */
+	RNG_MASK_ALL_INTERRUPTS();
+
+	RNG_WAKE();
+
+	/* Determine status of RNG */
+	if (RNG_OSCILLATOR_FAILED()) {
+		LOG_KDIAG("RNG Driver: RNG Oscillator is dead");
+		rng_availability = RNG_STATUS_FAILED;
+		goto check_err;
+	}
+
+	/* Oscillator not dead.  Setup interrupt code and start the RNG. */
+	if ((return_code = rng_setup_interrupt_handling()) == OS_ERROR_OK_S) {
+#if defined(FSL_HAVE_RNGA)
+		scc_return_t scc_code;
+#endif
+
+		RNG_GO();
+
+		/* Self Testing For RNG */
+		do {
+			RNG_CLEAR_ERR();
+
+			/* wait for Clearing Erring finished */
+			msleep(1);
+
+			RNG_UNMASK_ALL_INTERRUPTS();
+			RNG_SELF_TEST();
+#if !defined(FSL_HAVE_RNGA)
+			wait_for_completion(&rng_self_testing);
+#endif
+		} while (RNG_CHECK_SELF_ERR());
+
+		RNG_CLEAR_ALL_STATUS();
+		/* checking for RNG SEED done */
+		do {
+			RNG_CLEAR_ERR();
+			RNG_SEED_GEN();
+#if !defined(FSL_HAVE_RNGA)
+			wait_for_completion(&rng_seed_done);
+#endif
+		} while (RNG_CHECK_SEED_ERR());
+#ifndef RNG_NO_FORCE_HIGH_ASSURANCE
+		RNG_SET_HIGH_ASSURANCE();
+#endif
+		if (RNG_GET_HIGH_ASSURANCE()) {
+			LOG_KDIAG("RNG Driver: RNG is in High Assurance mode");
+		} else {
+#ifndef RNG_NO_FORCE_HIGH_ASSURANCE
+			LOG_KDIAG
+			    ("RNG Driver: RNG could not be put in High Assurance mode");
+			rng_availability = RNG_STATUS_FAILED;
+			goto check_err;
+#endif				/* RNG_NO_FORCE_HIGH_ASSURANCE */
+		}
+
+		/* Check that RNG is OK */
+		if (!RNG_WORKING()) {
+			LOG_KDIAG_ARGS
+			    ("RNG determined to be inoperable.  Status %08x",
+			     RNG_GET_STATUS());
+			/* Couldn't wake it up or other problem */
+			rng_availability = RNG_STATUS_FAILED;
+			goto check_err;
+		}
+
+		rng_queue_lock = os_lock_alloc_init();
+		if (rng_queue_lock == NULL) {
+			LOG_KDIAG("RNG: lock initialization failed");
+			rng_availability = RNG_STATUS_FAILED;
+			goto check_err;
+		}
+
+		return_code = os_create_task(rng_entropy_task);
+		if (return_code != OS_ERROR_OK_S) {
+			LOG_KDIAG("RNG: task initialization failed");
+			rng_availability = RNG_STATUS_FAILED;
+			goto check_err;
+		} else {
+			task_started = TRUE;
+		}
+#ifdef FSL_HAVE_RNGA
+		scc_code = scc_monitor_security_failure(rng_sec_failure);
+		if (scc_code != SCC_RET_OK) {
+			LOG_KDIAG_ARGS("Failed to register SCC callback: %d",
+				       scc_code);
+#ifndef RNG_NO_FORCE_HIGH_ASSURANCE
+			return_code = OS_ERROR_FAIL_S;
+			goto check_err;
+#endif
+		}
+#endif				/* FSL_HAVE_RNGA */
+		return_code = os_driver_init_registration(rng_reg_handle);
+		if (return_code != OS_ERROR_OK_S) {
+			goto check_err;
+		}
+		/* add power suspend here */
+		/* add power resume here */
+		return_code =
+		    os_driver_complete_registration(rng_reg_handle,
+						    rng_major, RNG_DRIVER_NAME);
+	}
+	/* RNG is working */
+
+      check_err:
+
+	/* If FIFO underflow or other error occurred during drain, this will fail,
+	 * as system will have been put into fail mode by SCC. */
+	if ((return_code == OS_ERROR_OK_S)
+	    && (rng_availability == RNG_STATUS_CHECKING)) {
+		RNG_PUT_RNG_TO_SLEEP();
+		rng_availability = RNG_STATUS_OK;	/* RNG & driver are ready */
+	} else if (return_code != OS_ERROR_OK_S) {
+		os_printk(KERN_ALERT "Driver initialization failed. %d",
+			  return_code);
+		rng_cleanup();
+	}
+
+	os_dev_init_return(return_code);
+
+}				/* rng_init */
+
+/*****************************************************************************/
+/* fn rng_shutdown()                                                         */
+/*****************************************************************************/
+/*!
+ * Prepare driver for exit.
+ *
+ * This is called during @c rmmod when the driver is unloading.
+ * Try to undo whatever was done during #rng_init(), to make the machine be
+ * in the same state, if possible.
+ *
+ * Calls rng_cleanup() to do all work, and then unmap device's register space.
+ */
+OS_DEV_SHUTDOWN(rng_shutdown)
+{
+	LOG_KDIAG("shutdown called");
+
+	rng_cleanup();
+
+	os_driver_remove_registration(rng_reg_handle);
+	if (rng_base != NULL) {
+		/* release the virtual memory map to the RNG */
+		os_unmap_device((void *)rng_base, RNG_ADDRESS_RANGE);
+		rng_base = NULL;
+	}
+
+	os_dev_shutdown_return(OS_ERROR_OK_S);
+}				/* rng_shutdown */
+
+/*****************************************************************************/
+/* fn rng_cleanup()                                                          */
+/*****************************************************************************/
+/*!
+ * Undo everything done by rng_init() and place driver in fail mode.
+ *
+ * Deregister from SCC, stop tasklet, shutdown the RNG.  Leave the register
+ * map in place in case other drivers call rng_read/write_register()
+ *
+ * @return void
+ */
+static void rng_cleanup(void)
+{
+	struct clk *clk;
+
+#ifdef FSL_HAVE_RNGA
+	scc_stop_monitoring_security_failure(rng_sec_failure);
+#endif
+
+	clk = clk_get(NULL, "rng_clk");
+	clk_disable(clk);
+	if (task_started) {
+		os_dev_stop_task(rng_entropy_task);
+	}
+
+	if (rng_base != NULL) {
+		/* mask off RNG interrupts */
+		RNG_MASK_ALL_INTERRUPTS();
+		RNG_SLEEP();
+
+		if (rng_irq_set) {
+			/* unmap the interrupts from the IRQ lines */
+			os_deregister_interrupt(INT_RNG);
+			rng_irq_set = FALSE;
+		}
+		LOG_KDIAG("Leaving rng driver status as failed");
+		rng_availability = RNG_STATUS_FAILED;
+	} else {
+		LOG_KDIAG("Leaving rng driver status as unimplemented");
+		rng_availability = RNG_STATUS_UNIMPLEMENTED;
+	}
+	LOG_KDIAG("Cleaned up");
+}				/* rng_cleanup */
+
+/*!
+ * Post-process routine for fsl_shw_get_random().
+ *
+ * This function will copy the random data generated by the background task
+ * into the user's buffer and then free the local buffer.
+ *
+ * @param gen_entry   The work request.
+ *
+ * @return 0 = meaning work completed, pass back result.
+ */
+static uint32_t finish_random(shw_queue_entry_t * gen_entry)
+{
+	rng_work_entry_t *work = (rng_work_entry_t *) gen_entry;
+
+	if (work->hdr.flags & FSL_UCO_USERMODE_USER) {
+		os_copy_to_user(work->data_user, work->data_local,
+				work->length);
+	} else {
+		memcpy(work->data_user, work->data_local, work->length);
+	}
+
+	os_free_memory(work->data_local);
+	work->data_local = NULL;
+
+	return 0;		/* means completed. */
+}
+
+/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */
+/*****************************************************************************/
+/* fn fsl_shw_get_random()                                                   */
+/*****************************************************************************/
+/*!
+ * Get random data.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    The number of octets of @a data being requested.
+ * @param data      A pointer to a location of @a length octets to where
+ *                       random data will be returned.
+ *
+ * @return     FSL_RETURN_NO_RESOURCE_S  A return code of type #fsl_shw_return_t.
+ *             FSL_RETURN_OK_S
+ */
+fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, uint32_t length,
+				    uint8_t * data)
+{
+	fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S;
+	/* Boost up length to cover any 'missing' bytes at end of a word */
+	uint32_t *buf = os_alloc_memory(length + 3, 0);
+	volatile rng_work_entry_t *work = os_alloc_memory(sizeof(*work), 0);
+
+	if ((rng_availability != RNG_STATUS_OK) || (buf == NULL)
+	    || (work == NULL)) {
+		if (rng_availability != RNG_STATUS_OK) {
+			LOG_KDIAG_ARGS("rng not available: %d\n",
+				       rng_availability);
+		} else {
+			LOG_KDIAG_ARGS
+			    ("Resource allocation failure: %d or %d bytes",
+			     length, sizeof(*work));
+		}
+		/* Cannot perform function.  Clean up and clear out. */
+		if (buf != NULL) {
+			os_free_memory(buf);
+		}
+		if (work != NULL) {
+			os_free_memory((void *)work);
+		}
+	} else {
+		unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE;
+
+		work->hdr.user_ctx = user_ctx;
+		work->hdr.flags = user_ctx->flags;
+		work->hdr.callback = user_ctx->callback;
+		work->hdr.user_ref = user_ctx->user_ref;
+		work->hdr.postprocess = finish_random;
+		work->length = length;
+		work->data_local = buf;
+		work->data_user = data;
+
+		RNG_ADD_WORK_ENTRY((rng_work_entry_t *) work);
+
+		if (blocking) {
+			os_sleep(rng_wait_queue, work->completed != FALSE,
+				 FALSE);
+			finish_random((shw_queue_entry_t *) work);
+			return_code = work->hdr.code;
+			os_free_memory((void *)work);
+		} else {
+			return_code = FSL_RETURN_OK_S;
+		}
+	}
+
+	return return_code;
+}				/* fsl_shw_get_entropy */
+
+/*****************************************************************************/
+/* fn fsl_shw_add_entropy()                                                  */
+/*****************************************************************************/
+/*!
+ * Add entropy to random number generator.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    Number of bytes at @a data.
+ * @param      data      Entropy to add to random number generator.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, uint32_t length,
+				     uint8_t * data)
+{
+	fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S;
+#if defined(FSL_HAVE_RNGC)
+	/* No Entropy Register in RNGC */
+	return_code = FSL_RETURN_OK_S;
+#else
+	uint32_t *local_data = NULL;
+	if (rng_availability == RNG_STATUS_OK) {
+		/* make 32-bit aligned place to hold data */
+		local_data = os_alloc_memory(length + 3, 0);
+		if (local_data == NULL) {
+			return_code = FSL_RETURN_NO_RESOURCE_S;
+		} else {
+			memcpy(local_data, data, length);
+
+			/* Copy one word at a time to hardware */
+			while (TRUE) {
+				register uint32_t *ptr = local_data;
+
+				RNG_ADD_ENTROPY(*ptr++);
+				if (length <= 4) {
+					break;
+				}
+				length -= 4;
+			}
+			return_code = FSL_RETURN_OK_S;
+			os_free_memory(local_data);
+		}		/* else local_data not NULL */
+
+	}
+#endif
+	/* rng_availability is OK */
+	return return_code;
+}				/* fsl_shw_add_entropy */
+
+#ifdef RNG_REGISTER_PEEK_POKE
+/*****************************************************************************/
+/* fn rng_read_register()                                                   */
+/*****************************************************************************/
+/*
+ * Debug routines to allow reading of RNG registers.
+ *
+ * This routine is only for accesses by other than this driver.
+ *
+ * @param register_offset  The byte offset of the register to be read.
+ * @param value            Pointer to store the value of the register.
+ *
+ * @return RNG_RET_OK or an error return.
+ */
+rng_return_t rng_read_register(uint32_t register_offset, uint32_t * value)
+{
+	rng_return_t return_code = RNG_RET_FAIL;
+
+	if ((rng_availability == RNG_STATUS_OK)
+	    || (rng_availability == RNG_STATUS_FAILED)) {
+		if ((rng_check_register_offset(register_offset)
+		     && rng_check_register_accessible(register_offset,
+						      RNG_CHECK_READ))) {
+			/* The guards let the check through */
+			*value = RNG_READ_REGISTER(register_offset);
+			return_code = RNG_RET_OK;
+		}
+	}
+
+	return return_code;
+}				/* rng_read_register */
+
+/*****************************************************************************/
+/* fn rng_write_register()                                                  */
+/*****************************************************************************/
+/*
+ * Debug routines to allow writing of RNG registers.
+ *
+ * This routine is only for accesses by other than this driver.
+ *
+ * @param register_offset  The byte offset of the register to be written.
+ * @param value            Value to store in the register.
+ *
+ * @return RNG_RET_OK or an error return.
+ */
+rng_return_t rng_write_register(uint32_t register_offset, uint32_t value)
+{
+	rng_return_t return_code = RNG_RET_FAIL;
+
+	if ((rng_availability == RNG_STATUS_OK)
+	    || (rng_availability == RNG_STATUS_FAILED)) {
+		if ((rng_check_register_offset(register_offset)
+		     && rng_check_register_accessible(register_offset,
+						      RNG_CHECK_WRITE))) {
+			RNG_WRITE_REGISTER(register_offset, value);
+			return_code = RNG_RET_OK;
+		}
+	}
+
+	return return_code;
+}				/* rng_write_register */
+#endif				/*  RNG_REGISTER_PEEK_POKE */
+
+/******************************************************************************
+ *
+ *  Function Implementations - Internal
+ *
+ *****************************************************************************/
+
+#ifdef RNG_REGISTER_PEEK_POKE
+/*****************************************************************************/
+/* fn check_register_offset()                                                */
+/*****************************************************************************/
+/*!
+ * Verify that the @c offset is appropriate for the RNG's register set.
+ *
+ * @param[in]  offset  The (byte) offset within the RNG block
+ *                     of the register to be accessed.  See
+ *                     RNG(A, C) register definitions for meanings.
+ *
+ * This routine is only for checking accesses by other than this driver.
+ *
+ * @return  0 if register offset out of bounds, 1 if ok to use
+ */
+inline int rng_check_register_offset(uint32_t offset)
+{
+	int return_code = FALSE;	/* invalid */
+
+	/* Make sure offset isn't too high and also that it is aligned to
+	 * aa 32-bit offset (multiple of four).
+	 */
+	if ((offset < RNG_ADDRESS_RANGE) && (offset % sizeof(uint32_t) == 0)) {
+		return_code = TRUE;	/* OK */
+	} else {
+		pr_debug("RNG: Denied access to offset %8x\n", offset);
+	}
+
+	return return_code;
+
+}				/* rng_check_register */
+
+/*****************************************************************************/
+/* fn check_register_accessible()                                            */
+/*****************************************************************************/
+/*!
+ * Make sure that register access is legal.
+ *
+ * Verify that, if in secure mode, only safe registers are used.
+ * For any register access, make sure that read-only registers are not written
+ * and that write-only registers are not read.  This check also disallows any
+ * access to the RNG's Output FIFO, to prevent other drivers from draining the
+ * FIFO and causing an underflow condition.
+ *
+ * This routine is only for checking accesses by other than this driver.
+ *
+ * @param  offset   The (byte) offset within the RNG block
+ *                      of the register to be accessed.  See
+ *                      @ref rngregs for meanings.
+ * @param access_write  0 for read, anything else for write
+ *
+ * @return 0 if invalid, 1 if OK.
+ */
+static int rng_check_register_accessible(uint32_t offset, int access_write)
+{
+	int return_code = FALSE;	/* invalid */
+	uint32_t secure = RNG_GET_HIGH_ASSURANCE();
+
+	/* First check for RNG in Secure Mode -- most registers inaccessible.
+	 * Also disallowing access to RNG_OUTPUT_FIFO except by the driver.
+	 */
+	if (!
+#ifdef FSL_HAVE_RNGA
+	    (secure &&
+	     ((offset == RNGA_OUTPUT_FIFO) ||
+	      (offset == RNGA_MODE) ||
+	      (offset == RNGA_VERIFICATION_CONTROL) ||
+	      (offset == RNGA_OSCILLATOR_CONTROL_COUNTER) ||
+	      (offset == RNGA_OSCILLATOR1_COUNTER) ||
+	      (offset == RNGA_OSCILLATOR2_COUNTER) ||
+	      (offset == RNGA_OSCILLATOR_COUNTER_STATUS)))
+#else				/* RNGB or RNGC */
+	    (secure &&
+	     ((offset == RNGC_FIFO) ||
+	      (offset == RNGC_VERIFICATION_CONTROL) ||
+	      (offset == RNGC_OSC_COUNTER_CONTROL) ||
+	      (offset == RNGC_OSC_COUNTER) ||
+	      (offset == RNGC_OSC_COUNTER_STATUS)))
+#endif
+	    ) {
+
+		/*  Passed that test.  Either not in high assurance, and/or are
+		   checking register that is always available.  Now check
+		   R/W permissions. */
+		if (access_write == RNG_CHECK_READ) {	/* read request */
+			/* Only the entropy register is write-only */
+#ifdef FSL_HAVE_RNGC
+			/* No registers are write-only */
+			return_code = TRUE;
+#else				/* else RNGA or RNGB */
+#ifdef FSL_HAVE_RNGA
+			if (1) {
+#else
+			if (!(offset == RNGB_ENTROPY)) {
+#endif
+				return_code = TRUE;	/* Let all others be read */
+			} else {
+				pr_debug
+				    ("RNG: Offset %04x denied read access\n",
+				     offset);
+			}
+#endif				/* RNGA or RNGB */
+		} /* read */
+		else {		/* access_write means write */
+			/* Check against list of non-writable registers */
+			if (!
+#ifdef FSL_HAVE_RNGA
+			    ((offset == RNGA_STATUS) ||
+			     (offset == RNGA_OUTPUT_FIFO) ||
+			     (offset == RNGA_OSCILLATOR1_COUNTER) ||
+			     (offset == RNGA_OSCILLATOR2_COUNTER) ||
+			     (offset == RNGA_OSCILLATOR_COUNTER_STATUS))
+#else				/* FSL_HAVE_RNGB or FSL_HAVE_RNGC */
+			    ((offset == RNGC_STATUS) ||
+			     (offset == RNGC_FIFO) ||
+			     (offset == RNGC_OSC_COUNTER) ||
+			     (offset == RNGC_OSC_COUNTER_STATUS))
+#endif
+			    ) {
+				return_code = TRUE;	/* can be written */
+			} else {
+				LOG_KDIAG_ARGS
+				    ("Offset %04x denied write access", offset);
+			}
+		}		/* write */
+	} /* not high assurance and inaccessible register... */
+	else {
+		LOG_KDIAG_ARGS("Offset %04x denied high-assurance access",
+			       offset);
+	}
+
+	return return_code;
+}				/* rng_check_register_accessible */
+#endif				/*  RNG_REGISTER_PEEK_POKE */
+
+/*****************************************************************************/
+/* fn rng_irq()                                                             */
+/*****************************************************************************/
+/*!
+ * This is the interrupt handler for the RNG.  It is only ever invoked if the
+ * RNG detects a FIFO Underflow error.
+ *
+ * If the error is a Security Violation, this routine will
+ * set the #rng_availability to #RNG_STATUS_FAILED, as the entropy pool may
+ * have been corrupted.  The RNG will also be placed into low power mode.  The
+ * SCC will have noticed the problem as well.
+ *
+ * The other possibility, if the RNG is not in High Assurance mode, would be
+ * simply a FIFO Underflow.  No special action, other than to
+ * clear the interrupt, is taken.
+ */
+OS_DEV_ISR(rng_irq)
+{
+	int handled = FALSE;	/* assume interrupt isn't from RNG */
+
+	LOG_KDIAG("rng irq!");
+
+	if (RNG_SEED_DONE()) {
+		complete(&rng_seed_done);
+		RNG_CLEAR_ALL_STATUS();
+		handled = TRUE;
+	}
+
+	if (RNG_SELF_TEST_DONE()) {
+		complete(&rng_self_testing);
+		RNG_CLEAR_ALL_STATUS();
+		handled = TRUE;
+	}
+	/* Look to see whether RNG needs attention */
+	if (RNG_HAS_ERROR()) {
+		if (RNG_GET_HIGH_ASSURANCE()) {
+			RNG_SLEEP();
+			rng_availability = RNG_STATUS_FAILED;
+			RNG_MASK_ALL_INTERRUPTS();
+		}
+		handled = TRUE;
+		/* Clear the interrupt */
+		RNG_CLEAR_ALL_STATUS();
+
+	}
+	os_dev_isr_return(handled);
+}				/* rng_irq */
+
+/*****************************************************************************/
+/* fn map_RNG_memory()                                                      */
+/*****************************************************************************/
+/*!
+ * Place the RNG's memory into kernel virtual space.
+ *
+ * @return OS_ERROR_OK_S on success, os_error_code on failure
+ */
+static os_error_code rng_map_RNG_memory(void)
+{
+	os_error_code error_code = OS_ERROR_FAIL_S;
+
+	rng_base = os_map_device(RNG_BASE_ADDR, RNG_ADDRESS_RANGE);
+	if (rng_base == NULL) {
+		/* failure ! */
+		LOG_KDIAG("RNG Driver: ioremap failed.");
+	} else {
+		error_code = OS_ERROR_OK_S;
+	}
+
+	return error_code;
+}				/* rng_map_RNG_memory */
+
+/*****************************************************************************/
+/* fn rng_setup_interrupt_handling()                                        */
+/*****************************************************************************/
+/*!
+ * Register #rng_irq() as the interrupt handler for #INT_RNG.
+ *
+ * @return OS_ERROR_OK_S on success, os_error_code on failure
+ */
+static os_error_code rng_setup_interrupt_handling(void)
+{
+	os_error_code error_code;
+
+	/*
+	 * Install interrupt service routine for the RNG. Ignore the
+	 * assigned IRQ number.
+	 */
+	error_code = os_register_interrupt(RNG_DRIVER_NAME, INT_RNG,
+					   OS_DEV_ISR_REF(rng_irq));
+	if (error_code != OS_ERROR_OK_S) {
+		LOG_KDIAG("RNG Driver: Error installing Interrupt Handler");
+	} else {
+		rng_irq_set = TRUE;
+		RNG_UNMASK_ALL_INTERRUPTS();
+	}
+
+	return error_code;
+}				/* rng_setup_interrupt_handling */
+
+/*****************************************************************************/
+/* fn rng_grab_config_values()                                               */
+/*****************************************************************************/
+/*!
+ * Read configuration information from the RNG.
+ *
+ * Sets #rng_output_fifo_size.
+ *
+ * @return  A error code indicating whether the part is the expected one.
+ */
+static os_error_code rng_grab_config_values(void)
+{
+	enum rng_type type;
+	os_error_code ret = OS_ERROR_FAIL_S;
+
+	/* Go for type, versions... */
+	type = RNG_GET_RNG_TYPE();
+
+	/* Make sure type is the one this code has been compiled for. */
+	if (RNG_VERIFY_TYPE(type)) {
+		rng_output_fifo_size = RNG_GET_FIFO_SIZE();
+		if (rng_output_fifo_size != 0) {
+			ret = OS_ERROR_OK_S;
+		}
+	}
+	if (ret != OS_ERROR_OK_S) {
+		LOG_KDIAG_ARGS
+		    ("Unknown or unexpected RNG type %d (FIFO size %d)."
+		     "  Failing driver initialization", type,
+		     rng_output_fifo_size);
+	}
+
+	return ret;
+}
+
+ /* rng_grab_config_values */
+
+/*****************************************************************************/
+/* fn rng_drain_fifo()                                                       */
+/*****************************************************************************/
+/*!
+ * This function copies words from the RNG FIFO into the caller's buffer.
+ *
+ *
+ * @param random_p    Location to copy random data
+ * @param count_words Number of words to copy
+ *
+ * @return An error code.
+ */
+static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words)
+{
+
+	int words_in_rng;	/* Number of words available now in RNG */
+	fsl_shw_return_t code = FSL_RETURN_ERROR_S;
+	int sequential_count = 0;	/* times through big while w/empty FIFO */
+	int fifo_empty_count = 0;	/* number of times FIFO was empty */
+	int max_sequential = 0;	/* max times 0 seen in a row */
+#if !defined(FSL_HAVE_RNGA)
+	int count_for_reseed = 0;
+	INIT_COMPLETION(rng_seed_done);
+#endif
+#if !defined(FSL_HAVE_RNGA)
+	if (RNG_RESEED()) {
+		do {
+			LOG_KDIAG("Reseeding RNG");
+
+			RNG_CLEAR_ERR();
+			RNG_SEED_GEN();
+			wait_for_completion(&rng_seed_done);
+			if (count_for_reseed == 3) {
+				os_printk(KERN_ALERT
+					  "Device was not able to enter RESEED Mode\n");
+				code = FSL_RETURN_INTERNAL_ERROR_S;
+			}
+			count_for_reseed++;
+		} while (RNG_CHECK_SEED_ERR());
+	}
+#endif
+	/* Copy all of them in.  Stop if pool fills. */
+	while ((rng_availability == RNG_STATUS_OK) && (count_words > 0)) {
+		/* Ask RNG how many words currently in FIFO */
+		words_in_rng = RNG_GET_WORDS_IN_FIFO();
+		if (words_in_rng == 0) {
+			++sequential_count;
+			fifo_empty_count++;
+			if (sequential_count > max_sequential) {
+				max_sequential = sequential_count;
+			}
+			if (sequential_count >= RNG_MAX_TRIES) {
+				LOG_KDIAG_ARGS("FIFO staying empty (%d)",
+					       words_in_rng);
+				code = FSL_RETURN_NO_RESOURCE_S;
+				break;
+			}
+		} else {
+			/* Found at least one word */
+			sequential_count = 0;
+			/* Now adjust: words_in_rng = MAX(count_words, words_in_rng) */
+			words_in_rng = (count_words < words_in_rng)
+			    ? count_words : words_in_rng;
+		}		/* else found words */
+
+#ifdef RNG_FORCE_FIFO_UNDERFLOW
+		/*
+		 * For unit test, force occasional extraction of more words than
+		 * available.  This should cause FIFO Underflow, and IRQ invocation.
+		 */
+		words_in_rng = count_words;
+#endif
+
+		/* Copy out all available & neeeded data */
+		while (words_in_rng-- > 0) {
+			*random_p++ = RNG_READ_FIFO();
+			count_words--;
+		}
+	}			/* while words still needed */
+
+	if (count_words == 0) {
+		code = FSL_RETURN_OK_S;
+	}
+	if (fifo_empty_count != 0) {
+		LOG_KDIAG_ARGS("FIFO empty %d times, max loop count %d",
+			       fifo_empty_count, max_sequential);
+	}
+
+	return code;
+}				/* rng_drain_fifo */
+
+/*****************************************************************************/
+/* fn rng_entropy_task()                                                     */
+/*****************************************************************************/
+/*!
+ * This is the background task of the driver.  It is scheduled by
+ * RNG_ADD_WORK_ENTRY().
+ *
+ * This will process each entry on the #rng_work_queue.  Blocking requests will
+ * cause sleepers to be awoken.  Non-blocking requests will be placed on the
+ * results queue, and if appropriate, the callback function will be invoked.
+ */
+OS_DEV_TASK(rng_entropy_task)
+{
+	rng_work_entry_t *work;
+
+	os_dev_task_begin();
+
+#ifdef RNG_ENTROPY_DEBUG
+	LOG_KDIAG("entropy task starting");
+#endif
+
+	while ((work = RNG_GET_WORK_ENTRY()) != NULL) {
+#ifdef RNG_ENTROPY_DEBUG
+		LOG_KDIAG_ARGS("found %d bytes of work at %p (%p)",
+			       work->length, work, work->data_local);
+#endif
+		work->hdr.code = rng_drain_fifo(work->data_local,
+						BYTES_TO_WORDS(work->length));
+		work->completed = TRUE;
+
+		if (work->hdr.flags & FSL_UCO_BLOCKING_MODE) {
+#ifdef RNG_ENTROPY_DEBUG
+			LOG_KDIAG("Waking queued processes");
+#endif
+			os_wake_sleepers(rng_wait_queue);
+		} else {
+			os_lock_context_t lock_context;
+
+			os_lock_save_context(rng_queue_lock, lock_context);
+			RNG_ADD_QUEUE_ENTRY(&work->hdr.user_ctx->result_pool,
+					    work);
+			os_unlock_restore_context(rng_queue_lock, lock_context);
+
+			if (work->hdr.flags & FSL_UCO_CALLBACK_MODE) {
+				if (work->hdr.callback != NULL) {
+					work->hdr.callback(work->hdr.user_ctx);
+				} else {
+#ifdef RNG_ENTROPY_DEBUG
+					LOG_KDIAG_ARGS
+					    ("Callback ptr for %p is NULL",
+					     work);
+#endif
+				}
+			}
+		}
+	}			/* while */
+
+#ifdef RNG_ENTROPY_DEBUG
+	LOG_KDIAG("entropy task ending");
+#endif
+
+	os_dev_task_return(OS_ERROR_OK_S);
+}				/* rng_entropy_task */
+
+#ifdef FSL_HAVE_RNGA
+/*****************************************************************************/
+/* fn rng_sec_failure()                                                      */
+/*****************************************************************************/
+/*!
+ * Function to handle "Security Alarm" indication from SCC.
+ *
+ * This function is registered with the Security Monitor ans the callback
+ * function for the RNG driver.  Upon alarm, it will shut down the driver so
+ * that no more random data can be retrieved.
+ *
+ * @return void
+ */
+static void rng_sec_failure(void)
+{
+	os_printk(KERN_ALERT "RNG Driver: Security Failure Alarm received.\n");
+
+	rng_cleanup();
+
+	return;
+}
+#endif
+
+#ifdef RNG_REGISTER_DEBUG
+/*****************************************************************************/
+/* fn dbg_rng_read_register()                                                */
+/*****************************************************************************/
+/*!
+ * Noisily read a 32-bit value to an RNG register.
+ * @param offset        The address of the register to read.
+ *
+ * @return  The register value
+ * */
+static uint32_t dbg_rng_read_register(uint32_t offset)
+{
+	uint32_t value;
+
+	value = os_read32(rng_base + offset);
+#ifndef RNG_ENTROPY_DEBUG
+	if (offset != RNG_OUTPUT_FIFO) {
+#endif
+		pr_debug("RNG RD: 0x%4x : 0x%08x\n", offset, value);
+#ifndef RNG_ENTROPY_DEBUG
+	}
+#endif
+	return value;
+}
+
+/*****************************************************************************/
+/* fn dbg_rng_write_register()                                               */
+/*****************************************************************************/
+/*!
+ * Noisily write a 32-bit value to an RNG register.
+ * @param offset        The address of the register to written.
+ *
+ * @param value         The new register value
+ */
+static void dbg_rng_write_register(uint32_t offset, uint32_t value)
+{
+	LOG_KDIAG_ARGS("WR: 0x%4x : 0x%08x", offset, value);
+	os_write32(value, rng_base + offset);
+	return;
+}
+
+#endif				/* RNG_REGISTER_DEBUG */
diff --git a/drivers/mxc/security/rng/shw_driver.c b/drivers/mxc/security/rng/shw_driver.c
new file mode 100644
index 000000000000..24c912245099
--- /dev/null
+++ b/drivers/mxc/security/rng/shw_driver.c
@@ -0,0 +1,2335 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*! @file shw_driver.c
+ *
+ * This is the user-mode driver code for the FSL Security Hardware (SHW) API.
+ * as well as the 'common' FSL SHW API code for kernel API users.
+ *
+ * Its interaction with the Linux kernel is from calls to shw_init() when the
+ * driver is loaded, and shw_shutdown() should the driver be unloaded.
+ *
+ * The User API (driver interface) is handled by the following functions:
+ * @li shw_open()    - handles open() system call on FSL SHW device
+ * @li shw_release() - handles close() system call on FSL SHW device
+ * @li shw_ioctl()    - handles ioctl() system call on FSL SHW device
+ *
+ * The driver also provides the following functions for kernel users of the FSL
+ * SHW API:
+ * @li fsl_shw_register_user()
+ * @li fsl_shw_deregister_user()
+ * @li fsl_shw_get_capabilities()
+ * @li fsl_shw_get_results()
+ *
+ * All other functions are internal to the driver.
+ *
+ * The life of the driver starts at boot (or module load) time, with a call by
+ * the kernel to shw_init().
+ *
+ * The life of the driver ends when the kernel is shutting down (or the driver
+ * is being unloaded).  At this time, shw_shutdown() is called.  No function
+ * will ever be called after that point.
+ *
+ * In the case that the driver is reloaded, a new copy of the driver, with
+ * fresh global values, etc., is loaded, and there will be a new call to
+ * shw_init().
+ *
+ * In user mode, the user's fsl_shw_register_user() call causes an open() event
+ * on the driver followed by a ioctl() with the registration information.  Any
+ * subsequent API calls by the user are handled through the ioctl() function
+ * and shuffled off to the appropriate routine (or driver) for service.  The
+ * fsl_shw_deregister_user() call by the user results in a close() function
+ * call on the driver.
+ *
+ * In kernel mode, the driver provides the functions fsl_shw_register_user(),
+ * fsl_shw_deregister_user(), fsl_shw_get_capabilities(), and
+ * fsl_shw_get_results().  Other parts of the API are provided by other
+ * drivers, if available, to support the cryptographic functions.
+ */
+
+#include "portable_os.h"
+#include "fsl_shw.h"
+#include "fsl_shw_keystore.h"
+
+#include "shw_internals.h"
+
+#ifdef FSL_HAVE_SCC2
+#include <linux/mxc_scc2_driver.h>
+#else
+#include <linux/mxc_scc_driver.h>
+#endif
+
+#ifdef SHW_DEBUG
+#include <diagnostic.h>
+#endif
+
+/******************************************************************************
+ *
+ *  Function Declarations
+ *
+ *****************************************************************************/
+
+/* kernel interface functions */
+OS_DEV_INIT_DCL(shw_init);
+OS_DEV_SHUTDOWN_DCL(shw_shutdown);
+OS_DEV_IOCTL_DCL(shw_ioctl);
+OS_DEV_MMAP_DCL(shw_mmap);
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_smalloc);
+EXPORT_SYMBOL(fsl_shw_sfree);
+EXPORT_SYMBOL(fsl_shw_sstatus);
+EXPORT_SYMBOL(fsl_shw_diminish_perms);
+EXPORT_SYMBOL(do_scc_encrypt_region);
+EXPORT_SYMBOL(do_scc_decrypt_region);
+
+EXPORT_SYMBOL(do_system_keystore_slot_alloc);
+EXPORT_SYMBOL(do_system_keystore_slot_dealloc);
+EXPORT_SYMBOL(do_system_keystore_slot_load);
+EXPORT_SYMBOL(do_system_keystore_slot_encrypt);
+EXPORT_SYMBOL(do_system_keystore_slot_decrypt);
+#endif
+
+static os_error_code
+shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx, uint32_t info);
+
+static os_error_code
+shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, uint32_t info);
+
+static os_error_code
+shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, uint32_t info);
+
+static os_error_code
+shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, uint32_t info);
+
+static os_error_code
+shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, uint32_t info);
+
+#ifdef FSL_HAVE_SCC2
+static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx,
+						uint32_t user_base,
+						void *kernel_base);
+static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx,
+						  uint32_t user_base);
+void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base);
+
+#endif				/* FSL_HAVE_SCC2 */
+
+/******************************************************************************
+ *
+ *  Global / Static Variables
+ *
+ *****************************************************************************/
+
+/*!
+ *  Major node (user/device interaction value) of this driver.
+ */
+static int shw_major_node = SHW_MAJOR_NODE;
+
+/*!
+ *  Flag to know whether the driver has been associated with its user device
+ *  node (e.g. /dev/shw).
+ */
+static int shw_device_registered = 0;
+
+/*!
+ * OS-dependent handle used for registering user interface of a driver.
+ */
+static os_driver_reg_t reg_handle;
+
+/*!
+ * Linked List of registered users of the API
+ */
+fsl_shw_uco_t *user_list;
+
+/*!
+ * This is the lock for all user request pools.  H/W component drivers may also
+ * use it for their own work queues.
+ */
+os_lock_t shw_queue_lock = NULL;
+
+/* This is the system keystore object */
+fsl_shw_kso_t system_keystore;
+
+#ifndef FSL_HAVE_SAHARA
+/*! Empty list of supported symmetric algorithms. */
+static fsl_shw_key_alg_t pf_syms[] = {
+};
+
+/*! Empty list of supported symmetric modes. */
+static fsl_shw_sym_mode_t pf_modes[] = {
+};
+
+/*! Empty list of supported hash algorithms. */
+static fsl_shw_hash_alg_t pf_hashes[] = {
+};
+#endif				/* no Sahara */
+
+/*! This matches SHW capabilities... */
+static fsl_shw_pco_t cap = {
+	1, 3,			/* api version number - major & minor */
+	2, 3,			/* driver version number - major & minor */
+	sizeof(pf_syms) / sizeof(fsl_shw_key_alg_t),	/* key alg count */
+	pf_syms,		/* key alg list ptr */
+	sizeof(pf_modes) / sizeof(fsl_shw_sym_mode_t),	/* sym mode count */
+	pf_modes,		/* modes list ptr */
+	sizeof(pf_hashes) / sizeof(fsl_shw_hash_alg_t),	/* hash alg count */
+	pf_hashes,		/* hash list ptr */
+	/*
+	 * The following table must be set to handle all values of key algorithm
+	 * and sym mode, and be in the correct order..
+	 */
+	{			/* Stream, ECB, CBC, CTR */
+	 {0, 0, 0, 0}
+	 ,			/* HMAC */
+	 {0, 0, 0, 0}
+	 ,			/* AES  */
+	 {0, 0, 0, 0}
+	 ,			/* DES */
+#ifdef FSL_HAVE_DRYICE
+	 {0, 1, 1, 0}
+	 ,			/* 3DES - ECB and CBC */
+#else
+	 {0, 0, 0, 0}
+	 ,			/* 3DES */
+#endif
+	 {0, 0, 0, 0}		/* ARC4 */
+	 }
+	,
+	0, 0,			/* SCC driver version */
+	0, 0, 0,		/* SCC version/capabilities */
+	{{0, 0}
+	 }
+	,			/* (filled in during OS_INIT) */
+};
+
+/* These are often handy */
+#ifndef FALSE
+/*! Not true.  Guaranteed to be zero. */
+#define FALSE 0
+#endif
+#ifndef TRUE
+/*! True.  Guaranteed to be non-zero. */
+#define TRUE 1
+#endif
+
+/******************************************************************************
+ *
+ *  Function Implementations - Externally Accessible
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/* fn shw_init()                                                             */
+/*****************************************************************************/
+/*!
+ * Initialize the driver.
+ *
+ * This routine is called during kernel init or module load (insmod).
+ *
+ * @return OS_ERROR_OK_S on success, errno on failure
+ */
+OS_DEV_INIT(shw_init)
+{
+	os_error_code error_code = OS_ERROR_NO_MEMORY_S;	/* assume failure */
+	scc_config_t *shw_capabilities;
+
+#ifdef SHW_DEBUG
+	LOG_KDIAG("SHW Driver: Loading");
+#endif
+
+	user_list = NULL;
+	shw_queue_lock = os_lock_alloc_init();
+
+	if (shw_queue_lock != NULL) {
+		error_code = shw_setup_user_driver_interaction();
+		if (error_code != OS_ERROR_OK_S) {
+#ifdef SHW_DEBUG
+			LOG_KDIAG_ARGS
+			    ("SHW Driver: Failed to setup user i/f: %d",
+			     error_code);
+#endif
+		}
+	}
+
+	/* queue_lock not NULL */
+	/* Fill in the SCC portion of the capabilities object */
+	shw_capabilities = scc_get_configuration();
+	cap.scc_driver_major = shw_capabilities->driver_major_version;
+	cap.scc_driver_minor = shw_capabilities->driver_minor_version;
+	cap.scm_version = shw_capabilities->scm_version;
+	cap.smn_version = shw_capabilities->smn_version;
+	cap.block_size_bytes = shw_capabilities->block_size_bytes;
+
+#ifdef FSL_HAVE_SCC
+	cap.u.scc_info.black_ram_size_blocks =
+	    shw_capabilities->black_ram_size_blocks;
+	cap.u.scc_info.red_ram_size_blocks =
+	    shw_capabilities->red_ram_size_blocks;
+#elif defined(FSL_HAVE_SCC2)
+	cap.u.scc2_info.partition_size_bytes =
+	    shw_capabilities->partition_size_bytes;
+	cap.u.scc2_info.partition_count = shw_capabilities->partition_count;
+#endif
+
+#if defined(FSL_HAVE_SCC2) || defined(FSL_HAVE_DRYICE)
+	if (error_code == OS_ERROR_OK_S) {
+		/* set up the system keystore, using the default keystore handler */
+		fsl_shw_init_keystore_default(&system_keystore);
+
+		if (fsl_shw_establish_keystore(NULL, &system_keystore)
+		    == FSL_RETURN_OK_S) {
+			error_code = OS_ERROR_OK_S;
+		} else {
+			error_code = OS_ERROR_FAIL_S;
+		}
+
+		if (error_code != OS_ERROR_OK_S) {
+#ifdef SHW_DEBUG
+			LOG_KDIAG_ARGS
+			    ("Registering the system keystore failed with error"
+			     " code: %d\n", error_code);
+#endif
+		}
+	}
+#endif				/* FSL_HAVE_SCC2 */
+
+	if (error_code != OS_ERROR_OK_S) {
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHW: Driver initialization failed. %d",
+			       error_code);
+#endif
+		shw_cleanup();
+	} else {
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: Driver initialization complete.");
+#endif
+	}
+
+	os_dev_init_return(error_code);
+}				/* shw_init */
+
+/*****************************************************************************/
+/* fn shw_shutdown()                                                         */
+/*****************************************************************************/
+/*!
+ * Prepare driver for exit.
+ *
+ * This is called during @c rmmod when the driver is unloading or when the
+ * kernel is shutting down.
+ *
+ * Calls shw_cleanup() to do all work to undo anything that happened during
+ * initialization or while driver was running.
+ */
+OS_DEV_SHUTDOWN(shw_shutdown)
+{
+
+#ifdef SHW_DEBUG
+	LOG_KDIAG("SHW: shutdown called");
+#endif
+	shw_cleanup();
+
+	os_dev_shutdown_return(OS_ERROR_OK_S);
+}				/* shw_shutdown */
+
+/*****************************************************************************/
+/* fn shw_cleanup()                                                          */
+/*****************************************************************************/
+/*!
+ * Prepare driver for shutdown.
+ *
+ * Remove the driver registration.
+ *
+ */
+static void shw_cleanup(void)
+{
+	if (shw_device_registered) {
+
+		/* Turn off the all association with OS */
+		os_driver_remove_registration(reg_handle);
+		shw_device_registered = 0;
+	}
+
+	if (shw_queue_lock != NULL) {
+		os_lock_deallocate(shw_queue_lock);
+	}
+#ifdef SHW_DEBUG
+	LOG_KDIAG("SHW Driver: Cleaned up");
+#endif
+}				/* shw_cleanup */
+
+/*****************************************************************************/
+/* fn shw_open()                                                             */
+/*****************************************************************************/
+/*!
+ * Handle @c open() call from user.
+ *
+ * @return OS_ERROR_OK_S on success (always!)
+ */
+OS_DEV_OPEN(shw_open)
+{
+	os_error_code status = OS_ERROR_OK_S;
+
+	os_dev_set_user_private(NULL);	/* Make sure */
+
+	os_dev_open_return(status);
+}				/* shw_open */
+
+/*****************************************************************************/
+/* fn shw_ioctl()                                                            */
+/*****************************************************************************/
+/*!
+ * Process an ioctl() request from user-mode API.
+ *
+ * This code determines which of the API requests the user has made and then
+ * sends the request off to the appropriate function.
+ *
+ * @return ioctl_return()
+ */
+OS_DEV_IOCTL(shw_ioctl)
+{
+	os_error_code code = OS_ERROR_FAIL_S;
+
+	fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS("SHW: IOCTL %d received", os_dev_get_ioctl_op());
+#endif
+	switch (os_dev_get_ioctl_op()) {
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_REGISTER_USER:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: register_user ioctl received");
+#endif
+		{
+			fsl_shw_uco_t *user_ctx =
+			    os_alloc_memory(sizeof(*user_ctx), 0);
+
+			if (user_ctx == NULL) {
+				code = OS_ERROR_NO_MEMORY_S;
+			} else {
+				code =
+				    init_uco(user_ctx,
+					     (fsl_shw_uco_t *)
+					     os_dev_get_ioctl_arg());
+				if (code == OS_ERROR_OK_S) {
+					os_dev_set_user_private(user_ctx);
+				} else {
+					os_free_memory(user_ctx);
+				}
+			}
+		}
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_DEREGISTER_USER:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: deregister_user ioctl received");
+#endif
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+			SHW_REMOVE_USER(user_ctx);
+		}
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RESULTS:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: get_results ioctl received");
+#endif
+		code = get_results(user_ctx,
+				   (struct results_req *)
+				   os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_CAPABILITIES:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: get_capabilities ioctl received");
+#endif
+		code = get_capabilities(user_ctx,
+					(fsl_shw_pco_t *)
+					os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RANDOM:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: get_random ioctl received");
+#endif
+		code = get_random(user_ctx,
+				  (struct get_random_req *)
+				  os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_ADD_ENTROPY:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: add_entropy ioctl received");
+#endif
+		code = add_entropy(user_ctx,
+				   (struct add_entropy_req *)
+				   os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_DROP_PERMS:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: drop permissions ioctl received");
+#endif
+		code =
+		    shw_handle_scc_drop_perms(user_ctx, os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_SSTATUS:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: sstatus ioctl received");
+#endif
+		code = shw_handle_scc_sstatus(user_ctx, os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_SFREE:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: sfree ioctl received");
+#endif
+		code = shw_handle_scc_sfree(user_ctx, os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_ENCRYPT:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: scc encrypt ioctl received");
+#endif
+		code = shw_handle_scc_encrypt(user_ctx, os_dev_get_ioctl_arg());
+		break;
+
+	case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_DECRYPT:
+#ifdef SHW_DEBUG
+		LOG_KDIAG("SHW: scc decrypt ioctl received");
+#endif
+		code = shw_handle_scc_decrypt(user_ctx, os_dev_get_ioctl_arg());
+		break;
+
+	default:
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHW: Unexpected ioctl %d",
+			       os_dev_get_ioctl_op());
+#endif
+		break;
+	}
+
+	os_dev_ioctl_return(code);
+}
+
+#ifdef FSL_HAVE_SCC2
+
+/*****************************************************************************/
+/* fn get_user_smid()                                                        */
+/*****************************************************************************/
+uint32_t get_user_smid(void *proc)
+{
+	/*
+	 * A real implementation would have some way to handle signed applications
+	 * which wouild be assigned distinct SMIDs.  For the reference
+	 * implementation, we show where this would be determined (here), but
+	 * always provide a fixed answer, thus not separating users at all.
+	 */
+
+	return 0x42eaae42;
+}
+
+/* user_base: userspace base address of the partition
+ * kernel_base: kernel mode base address of the partition
+ */
+static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx,
+						uint32_t user_base,
+						void *kernel_base)
+{
+	fsl_shw_spo_t *partition_info;
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	if (user_ctx == NULL) {
+		goto out;
+	}
+
+	partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL);
+
+	if (partition_info == NULL) {
+		goto out;
+	}
+
+	/* stuff the partition info, then put it at the front of the chain */
+	partition_info->user_base = user_base;
+	partition_info->kernel_base = kernel_base;
+	partition_info->next = user_ctx->partition;
+
+	user_ctx->partition = (struct fsl_shw_spo_t *)partition_info;
+
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS
+	    ("partition with user_base=%p, kernel_base=%p registered.",
+	     (void *)user_base, kernel_base);
+#endif
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+
+	return ret;
+}
+
+/* if the partition is in the users list, remove it */
+static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx,
+						  uint32_t user_base)
+{
+	fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition;
+	fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition;
+
+	while (curr != NULL) {
+		if (curr->user_base == user_base) {
+
+#ifdef SHW_DEBUG
+			LOG_KDIAG_ARGS
+			    ("deregister_user_partition: partition with "
+			     "user_base=%p, kernel_base=%p deregistered.\n",
+			     (void *)curr->user_base, curr->kernel_base);
+#endif
+
+			if (last == curr) {
+				user_ctx->partition = curr->next;
+				os_free_memory(curr);
+				return FSL_RETURN_OK_S;
+			} else {
+				last->next = curr->next;
+				os_free_memory(curr);
+				return FSL_RETURN_OK_S;
+			}
+		}
+		last = curr;
+		curr = (fsl_shw_spo_t *) curr->next;
+	}
+
+	return FSL_RETURN_ERROR_S;
+}
+
+/* Find the kernel-mode address of the partition.
+ * This can then be passed to the SCC functions.
+ */
+void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base)
+{
+	/* search through the partition chain to find one that matches the user base
+	 * address.
+	 */
+	fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition;
+
+	while (curr != NULL) {
+		if (curr->user_base == user_base) {
+			return curr->kernel_base;
+		}
+		curr = (fsl_shw_spo_t *) curr->next;
+	}
+	return NULL;
+}
+
+#endif				/* FSL_HAVE_SCC2 */
+
+/*!
+*******************************************************************************
+* This function implements the smalloc() function for userspace programs, by
+* making a call to the SCC2 mmap() function that acquires a region of secure
+* memory on behalf of the user, and then maps it into the users memory space.
+* Currently, the only memory size supported is that of a single SCC2 partition.
+* Requests for other sized memory regions will fail.
+*/
+OS_DEV_MMAP(shw_mmap)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+
+#ifdef FSL_HAVE_SCC2
+	{
+		scc_return_t scc_ret;
+		fsl_shw_return_t fsl_ret;
+		uint32_t partition_registered = FALSE;
+
+		uint32_t user_base;
+		void *partition_base;
+		uint32_t smid;
+		scc_config_t *scc_configuration;
+
+		int part_no = -1;
+		uint32_t part_phys;
+
+		fsl_shw_uco_t *user_ctx =
+		    (fsl_shw_uco_t *) os_dev_get_user_private();
+
+		/* Make sure that the user context is valid */
+		if (user_ctx == NULL) {
+			user_ctx =
+			    os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL);
+
+			if (user_ctx == NULL) {
+				status = OS_ERROR_NO_MEMORY_S;
+				goto out;
+			}
+			fsl_shw_register_user(user_ctx);
+			os_dev_set_user_private(user_ctx);
+		}
+
+		/* Determine the size of a secure partition */
+		scc_configuration = scc_get_configuration();
+
+		/* Check that the memory size requested is equal to the partition
+		 * size, and that the requested destination is on a page boundary.
+		 */
+		if (((os_mmap_user_base() % PAGE_SIZE) != 0) ||
+		    (os_mmap_memory_size() !=
+		     scc_configuration->partition_size_bytes)) {
+			status = OS_ERROR_BAD_ARG_S;
+			goto out;
+		}
+
+		/* Retrieve the SMID associated with the user */
+		smid = get_user_smid(user_ctx->process);
+
+		/* Attempt to allocate a secure partition */
+		scc_ret =
+		    scc_allocate_partition(smid, &part_no, &partition_base,
+					   &part_phys);
+		if (scc_ret != SCC_RET_OK) {
+			pr_debug
+			    ("SCC mmap() request failed to allocate partition;"
+			     " error %d\n", status);
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		pr_debug("scc_mmap() acquired partition %d at %08x\n",
+			 part_no, part_phys);
+
+		/* Record partition info in the user context */
+		user_base = os_mmap_user_base();
+		fsl_ret =
+		    register_user_partition(user_ctx, user_base,
+					    partition_base);
+
+		if (fsl_ret != FSL_RETURN_OK_S) {
+			pr_debug
+			    ("SCC mmap() request failed to register partition with user"
+			     " context, error: %d\n", fsl_ret);
+			status = OS_ERROR_FAIL_S;
+		}
+
+		partition_registered = TRUE;
+
+		status = map_user_memory(os_mmap_memory_ctx(), part_phys,
+					 os_mmap_memory_size());
+
+#ifdef SHW_DEBUG
+		if (status == OS_ERROR_OK_S) {
+			LOG_KDIAG_ARGS
+			    ("Partition allocated: user_base=%p, partition_base=%p.",
+			     (void *)user_base, partition_base);
+		}
+#endif
+
+	      out:
+		/* If there is an error it has to be handled here */
+		if (status != OS_ERROR_OK_S) {
+			/* if the partition was registered with the user, unregister it. */
+			if (partition_registered == TRUE) {
+				deregister_user_partition(user_ctx, user_base);
+			}
+
+			/* if the partition was allocated, deallocate it */
+			if (partition_base != NULL) {
+				scc_release_partition(partition_base);
+			}
+		}
+	}
+#endif				/* FSL_HAVE_SCC2 */
+
+	return status;
+}
+
+/*****************************************************************************/
+/* fn shw_release()                                                         */
+/*****************************************************************************/
+/*!
+ * Handle @c close() call from user.
+ * This is a Linux device driver interface routine.
+ *
+ * @return OS_ERROR_OK_S on success (always!)
+ */
+OS_DEV_CLOSE(shw_release)
+{
+	fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+	os_error_code code = OS_ERROR_OK_S;
+
+	if (user_ctx != NULL) {
+
+		fsl_shw_deregister_user(user_ctx);
+		os_free_memory(user_ctx);
+		os_dev_set_user_private(NULL);
+
+	}
+
+	os_dev_close_return(code);
+}				/* shw_release */
+
+/*****************************************************************************/
+/* fn shw_user_callback()                                                    */
+/*****************************************************************************/
+/*!
+ * FSL SHW User callback function.
+ *
+ * This function is set in the kernel version of the user context as the
+ * callback function when the user mode user wants a callback.  Its job is to
+ * inform the user process that results (may) be available.  It does this by
+ * sending a SIGUSR2 signal which is then caught by the user-mode FSL SHW
+ * library.
+ *
+ * @param user_ctx        Kernel version of uco associated with the request.
+ *
+ * @return void
+ */
+static void shw_user_callback(fsl_shw_uco_t * user_ctx)
+{
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS("SHW: Signalling callback user process for context %p\n",
+		       user_ctx);
+#endif
+	os_send_signal(user_ctx->process, SIGUSR2);
+}
+
+/*****************************************************************************/
+/* fn setup_user_driver_interaction()                                        */
+/*****************************************************************************/
+/*!
+ * Register the driver with the kernel as the driver for shw_major_node.  Note
+ * that this value may be zero, in which case the major number will be assigned
+ * by the OS.  shw_major_node is never modified.
+ *
+ * The open(), ioctl(), and close() handles for the driver ned to be registered
+ * with the kernel.  Upon success, shw_device_registered will be true;
+ *
+ * @return OS_ERROR_OK_S on success, or an os err code
+ */
+static os_error_code shw_setup_user_driver_interaction(void)
+{
+	os_error_code error_code;
+
+	os_driver_init_registration(reg_handle);
+	os_driver_add_registration(reg_handle, OS_FN_OPEN,
+				   OS_DEV_OPEN_REF(shw_open));
+	os_driver_add_registration(reg_handle, OS_FN_IOCTL,
+				   OS_DEV_IOCTL_REF(shw_ioctl));
+	os_driver_add_registration(reg_handle, OS_FN_CLOSE,
+				   OS_DEV_CLOSE_REF(shw_release));
+	os_driver_add_registration(reg_handle, OS_FN_MMAP,
+				   OS_DEV_MMAP_REF(shw_mmap));
+	error_code = os_driver_complete_registration(reg_handle, shw_major_node,
+						     SHW_DRIVER_NAME);
+
+	if (error_code != OS_ERROR_OK_S) {
+		/* failure ! */
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHW Driver: register device driver failed: %d",
+			       error_code);
+#endif
+	} else {		/* success */
+		shw_device_registered = TRUE;
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHW Driver:  Major node is %d\n",
+			       os_driver_get_major(reg_handle));
+#endif
+	}
+
+	return error_code;
+}				/* shw_setup_user_driver_interaction */
+
+/******************************************************************/
+/* User Mode Support                                              */
+/******************************************************************/
+
+/*!
+ * Initialze kernel User Context Object from User-space version.
+ *
+ * Copy user UCO into kernel UCO, set flags and fields for operation
+ * within kernel space.  Add user to driver's list of users.
+ *
+ * @param user_ctx        Pointer to kernel space UCO
+ * @param user_mode_uco   User pointer to user space version
+ *
+ * @return os_error_code
+ */
+static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco)
+{
+	os_error_code code;
+
+	code = os_copy_from_user(user_ctx, user_mode_uco, sizeof(*user_ctx));
+	if (code == OS_ERROR_OK_S) {
+		user_ctx->flags |= FSL_UCO_USERMODE_USER;
+		user_ctx->result_pool.head = NULL;
+		user_ctx->result_pool.tail = NULL;
+		user_ctx->process = os_get_process_handle();
+		user_ctx->callback = shw_user_callback;
+		SHW_ADD_USER(user_ctx);
+	}
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS("SHW: init uco returning %d (flags %x)",
+		       code, user_ctx->flags);
+#endif
+
+	return code;
+}
+
+/*!
+ * Copy array from kernel to user space.
+ *
+ * This routine will check bounds before trying to copy, and return failure
+ * on bounds violation or error during the copy.
+ *
+ * @param userloc   Location in userloc to place data.  If NULL, the function
+ *                  will do nothing (except return NULL).
+ * @param userend   Address beyond allowed copy region at @c userloc.
+ * @param data_start Location of data to be copied
+ * @param element_size  sizeof() an element
+ * @param element_count Number of elements of size element_size to copy.
+ * @return New value of userloc, or NULL if there was an error.
+ */
+inline static void *copy_array(void *userloc, void *userend, void *data_start,
+			       unsigned element_size, unsigned element_count)
+{
+	unsigned byte_count = element_size * element_count;
+
+	if ((userloc == NULL) || (userend == NULL)
+	    || ((userloc + byte_count) >= userend) ||
+	    (copy_to_user(userloc, data_start, byte_count) != OS_ERROR_OK_S)) {
+		userloc = NULL;
+	} else {
+		userloc += byte_count;
+	}
+
+	return userloc;
+}
+
+/*!
+ * Send an FSL SHW API return code up into the user-space request structure.
+ *
+ * @param user_header   User address of request block / request header
+ * @param result_code   The FSL SHW API code to be placed at header.code
+ *
+ * @return an os_error_code
+ *
+ * NOTE: This function assumes that the shw_req_header is at the beginning of
+ * each request structure.
+ */
+inline static os_error_code copy_fsl_code(void *user_header,
+					  fsl_shw_return_t result_code)
+{
+	return os_copy_to_user(user_header +
+			       offsetof(struct shw_req_header, code),
+			       &result_code, sizeof(result_code));
+}
+
+static os_error_code shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx,
+					       uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	scc_return_t scc_ret;
+	scc_partition_info_t partition_info;
+	void *kernel_base;
+
+	status =
+	    os_copy_from_user(&partition_info, (void *)info,
+			      sizeof(partition_info));
+
+	if (status != OS_ERROR_OK_S) {
+		goto out;
+	}
+
+	/* validate that the user owns this partition, and look up its handle */
+	kernel_base = lookup_user_partition(user_ctx, partition_info.user_base);
+
+	if (kernel_base == NULL) {
+		status = OS_ERROR_FAIL_S;
+#ifdef SHW_DEBUG
+		LOG_KDIAG("_scc_drop_perms(): failed to find partition\n");
+#endif
+		goto out;
+	}
+
+	/* call scc driver to perform the drop */
+	scc_ret = scc_diminish_permissions(kernel_base,
+					   partition_info.permissions);
+	if (scc_ret == SCC_RET_OK) {
+		status = OS_ERROR_OK_S;
+	} else {
+		status = OS_ERROR_FAIL_S;
+	}
+
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	scc_partition_info_t partition_info;
+	void *kernel_base;
+
+	status = os_copy_from_user(&partition_info,
+				   (void *)info, sizeof(partition_info));
+
+	if (status != OS_ERROR_OK_S) {
+		goto out;
+	}
+
+	/* validate that the user owns this partition, and look up its handle */
+	kernel_base = lookup_user_partition(user_ctx, partition_info.user_base);
+
+	if (kernel_base == NULL) {
+		status = OS_ERROR_FAIL_S;
+#ifdef SHW_DEBUG
+		LOG_KDIAG("Failed to find partition\n");
+#endif
+		goto out;
+	}
+
+	/* Call the SCC driver to ask about the partition status */
+	partition_info.status = scc_partition_status(kernel_base);
+
+	/* and copy the structure out */
+	status = os_copy_to_user((void *)info,
+				 &partition_info, sizeof(partition_info));
+
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx,
+					  uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		scc_partition_info_t partition_info;
+		void *kernel_base;
+		int ret;
+
+		status = os_copy_from_user(&partition_info,
+					   (void *)info,
+					   sizeof(partition_info));
+
+		/* check that the copy was successful */
+		if (status != OS_ERROR_OK_S) {
+			goto out;
+		}
+
+		/* validate that the user owns this partition, and look up its handle */
+		kernel_base =
+		    lookup_user_partition(user_ctx, partition_info.user_base);
+
+		if (kernel_base == NULL) {
+			status = OS_ERROR_FAIL_S;
+#ifdef SHW_DEBUG
+			LOG_KDIAG("failed to find partition\n");
+#endif				/*SHW_DEBUG */
+			goto out;
+		}
+
+		/* Unmap the memory region (see sys_munmap in mmap.c) */
+		ret = unmap_user_memory(partition_info.user_base, 8192);
+
+		/* If the memory was successfully released */
+		if (ret == OS_ERROR_OK_S) {
+
+			/* release the partition */
+			scc_release_partition(kernel_base);
+
+			/* and remove it from the users context */
+			deregister_user_partition(user_ctx,
+						  partition_info.user_base);
+
+			status = OS_ERROR_OK_S;
+
+		} else {
+#ifdef SHW_DEBUG
+			LOG_KDIAG("do_munmap not successful!");
+#endif
+		}
+
+	}
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code status = OS_ERROR_FAIL_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		fsl_shw_return_t retval;
+		scc_region_t region_info;
+		void *page_ctx = NULL;
+		void *black_addr = NULL;
+		void *partition_base = NULL;
+		scc_config_t *scc_configuration;
+
+		status =
+		    os_copy_from_user(&region_info, (void *)info,
+				      sizeof(region_info));
+
+		if (status != OS_ERROR_OK_S) {
+			goto out;
+		}
+
+		/* validate that the user owns this partition, and look up its handle */
+		partition_base = lookup_user_partition(user_ctx,
+						       region_info.
+						       partition_base);
+
+		if (partition_base == NULL) {
+			status = OS_ERROR_FAIL_S;
+#ifdef SHW_DEBUG
+			LOG_KDIAG("failed to find secure partition\n");
+#endif
+			goto out;
+		}
+
+		/* Check that the memory size requested is correct */
+		scc_configuration = scc_get_configuration();
+		if (region_info.offset + region_info.length >
+		    scc_configuration->partition_size_bytes) {
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		/* wire down black_data */
+		black_addr = wire_user_memory(region_info.black_data,
+					      region_info.length, &page_ctx);
+
+		if (black_addr == NULL) {
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		retval =
+		    do_scc_encrypt_region(NULL, partition_base,
+					  region_info.offset,
+					  region_info.length, black_addr,
+					  region_info.IV,
+					  region_info.cypher_mode);
+
+		if (retval == FSL_RETURN_OK_S) {
+			status = OS_ERROR_OK_S;
+		} else {
+			status = OS_ERROR_FAIL_S;
+		}
+
+		/* release black data */
+		unwire_user_memory(&page_ctx);
+	}
+      out:
+
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code status = OS_ERROR_FAIL_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		fsl_shw_return_t retval;
+		scc_region_t region_info;
+		void *page_ctx = NULL;
+		void *black_addr;
+		void *partition_base;
+		scc_config_t *scc_configuration;
+
+		status =
+		    os_copy_from_user(&region_info, (void *)info,
+				      sizeof(region_info));
+
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS
+		    ("partition_base: %p, offset: %i, length: %i, black data: %p",
+		     (void *)region_info.partition_base, region_info.offset,
+		     region_info.length, (void *)region_info.black_data);
+#endif
+
+		if (status != OS_ERROR_OK_S) {
+			goto out;
+		}
+
+		/* validate that the user owns this partition, and look up its handle */
+		partition_base = lookup_user_partition(user_ctx,
+						       region_info.
+						       partition_base);
+
+		if (partition_base == NULL) {
+			status = OS_ERROR_FAIL_S;
+#ifdef SHW_DEBUG
+			LOG_KDIAG("failed to find partition\n");
+#endif
+			goto out;
+		}
+
+		/* Check that the memory size requested is correct */
+		scc_configuration = scc_get_configuration();
+		if (region_info.offset + region_info.length >
+		    scc_configuration->partition_size_bytes) {
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		/* wire down black_data */
+		black_addr = wire_user_memory(region_info.black_data,
+					      region_info.length, &page_ctx);
+
+		if (black_addr == NULL) {
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		retval =
+		    do_scc_decrypt_region(NULL, partition_base,
+					  region_info.offset,
+					  region_info.length, black_addr,
+					  region_info.IV,
+					  region_info.cypher_mode);
+
+		if (retval == FSL_RETURN_OK_S) {
+			status = OS_ERROR_OK_S;
+		} else {
+			status = OS_ERROR_FAIL_S;
+		}
+
+		/* release black data */
+		unwire_user_memory(&page_ctx);
+	}
+      out:
+
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx,
+					       uint32_t key_length,
+					       uint64_t ownerid,
+					       uint32_t * slot)
+{
+	(void)user_ctx;
+	return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot);
+}
+
+fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot)
+{
+	(void)user_ctx;
+	return keystore_slot_dealloc(&system_keystore, ownerid, slot);
+}
+
+fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx,
+					      uint64_t ownerid,
+					      uint32_t slot,
+					      const uint8_t * key,
+					      uint32_t key_length)
+{
+	(void)user_ctx;
+	return keystore_slot_load(&system_keystore, ownerid, slot,
+				  (void *)key, key_length);
+}
+
+fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot,
+						 uint32_t key_length,
+						 uint8_t * black_data)
+{
+	(void)user_ctx;
+	return keystore_slot_encrypt(NULL, &system_keystore, ownerid,
+				     slot, key_length, black_data);
+}
+
+fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot,
+						 uint32_t key_length,
+						 const uint8_t * black_data)
+{
+	(void)user_ctx;
+	return keystore_slot_decrypt(NULL, &system_keystore, ownerid,
+				     slot, key_length, black_data);
+}
+
+fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx,
+					      uint64_t ownerid,
+					      uint32_t slot,
+					      uint32_t key_length,
+					      uint8_t * key_data)
+{
+	(void)user_ctx;
+
+	return keystore_slot_read(&system_keystore, ownerid,
+				  slot, key_length, key_data);
+}
+
+/*!
+ * Handle user-mode Get Capabilities request
+ *
+ * Right now, this function can only have a failure if the user has failed to
+ * provide a pointer to a location in user space with enough room to hold the
+ * fsl_shw_pco_t structure and any associated data.  It will treat this failure
+ * as an ioctl failure and return an ioctl error code, instead of treating it
+ * as an API failure.
+ *
+ * @param user_ctx    The kernel version of user's context
+ * @param user_mode_pco_request  Pointer to user-space request
+ *
+ * @return an os_error_code
+ */
+static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx,
+				      void *user_mode_pco_request)
+{
+	os_error_code code;
+	struct capabilities_req req;
+	fsl_shw_pco_t local_cap;
+
+	memcpy(&local_cap, &cap, sizeof(cap));
+	/* Initialize pointers to out-of-struct arrays */
+	local_cap.sym_algorithms = NULL;
+	local_cap.sym_modes = NULL;
+	local_cap.sym_modes = NULL;
+
+	code = os_copy_from_user(&req, user_mode_pco_request, sizeof(req));
+	if (code == OS_ERROR_OK_S) {
+		void *endcap;
+		void *user_bounds;
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHE: Received get_cap request: 0x%p/%u/0x%x",
+			       req.capabilities, req.size,
+			       sizeof(fsl_shw_pco_t));
+#endif
+		endcap = req.capabilities + 1;	/* point to end of structure */
+		user_bounds = (void *)req.capabilities + req.size;	/* end of area */
+
+		/* First verify that request is big enough for the main structure */
+		if (endcap >= user_bounds) {
+			endcap = NULL;	/* No! */
+		}
+
+		/* Copy any Symmetric Algorithm suppport */
+		if (cap.sym_algorithm_count != 0) {
+			local_cap.sym_algorithms = endcap;
+			endcap =
+			    copy_array(endcap, user_bounds, cap.sym_algorithms,
+				       sizeof(fsl_shw_key_alg_t),
+				       cap.sym_algorithm_count);
+		}
+
+		/* Copy any Symmetric Modes suppport */
+		if (cap.sym_mode_count != 0) {
+			local_cap.sym_modes = endcap;
+			endcap = copy_array(endcap, user_bounds, cap.sym_modes,
+					    sizeof(fsl_shw_sym_mode_t),
+					    cap.sym_mode_count);
+		}
+
+		/* Copy any Hash Algorithm suppport */
+		if (cap.hash_algorithm_count != 0) {
+			local_cap.hash_algorithms = endcap;
+			endcap =
+			    copy_array(endcap, user_bounds, cap.hash_algorithms,
+				       sizeof(fsl_shw_hash_alg_t),
+				       cap.hash_algorithm_count);
+		}
+
+		/* Now copy up the (possibly modified) main structure */
+		if (endcap != NULL) {
+			code =
+			    os_copy_to_user(req.capabilities, &local_cap,
+					    sizeof(cap));
+		}
+
+		if (endcap == NULL) {
+			code = OS_ERROR_BAD_ADDRESS_S;
+		}
+
+		/* And return the FSL SHW code in the request structure. */
+		if (code == OS_ERROR_OK_S) {
+			code =
+			    copy_fsl_code(user_mode_pco_request,
+					  FSL_RETURN_OK_S);
+		}
+	}
+
+	/* code may already be set to an error.  This is another error case.  */
+
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS("SHW: get capabilities returning %d", code);
+#endif
+
+	return code;
+}
+
+/*!
+ * Handle user-mode Get Results request
+ *
+ * Get arguments from user space into kernel space, then call
+ * fsl_shw_get_results, and then copy its return code and any results from
+ * kernel space back to user space.
+ *
+ * @param user_ctx    The kernel version of user's context
+ * @param user_mode_results_req  Pointer to user-space request
+ *
+ * @return an os_error_code
+ */
+static os_error_code get_results(fsl_shw_uco_t * user_ctx,
+				 void *user_mode_results_req)
+{
+	os_error_code code;
+	struct results_req req;
+	fsl_shw_result_t *results = NULL;
+	int loop;
+
+	code = os_copy_from_user(&req, user_mode_results_req, sizeof(req));
+	loop = 0;
+
+	if (code == OS_ERROR_OK_S) {
+		results = os_alloc_memory(req.requested * sizeof(*results), 0);
+		if (results == NULL) {
+			code = OS_ERROR_NO_MEMORY_S;
+		}
+	}
+
+	if (code == OS_ERROR_OK_S) {
+		fsl_shw_return_t err =
+		    fsl_shw_get_results(user_ctx, req.requested,
+					results, &req.actual);
+
+		/* Send API return code up to user. */
+		code = copy_fsl_code(user_mode_results_req, err);
+
+		if ((code == OS_ERROR_OK_S) && (err == FSL_RETURN_OK_S)) {
+			/* Now copy up the result count */
+			code = os_copy_to_user(user_mode_results_req
+					       + offsetof(struct results_req,
+							  actual), &req.actual,
+					       sizeof(req.actual));
+			if ((code == OS_ERROR_OK_S) && (req.actual != 0)) {
+				/* now copy up the results... */
+				code = os_copy_to_user(req.results, results,
+						       req.actual *
+						       sizeof(*results));
+			}
+		}
+	}
+
+	if (results != NULL) {
+		os_free_memory(results);
+	}
+
+	return code;
+}
+
+/*!
+ * Process header of user-mode request.
+ *
+ * Mark header as User Mode request.  Update UCO's flags and reference fields
+ * with current versions from the header.
+ *
+ * @param user_ctx  Pointer to kernel version of UCO.
+ * @param hdr       Pointer to common part of user request.
+ *
+ * @return void
+ */
+inline static void process_hdr(fsl_shw_uco_t * user_ctx,
+			       struct shw_req_header *hdr)
+{
+	hdr->flags |= FSL_UCO_USERMODE_USER;
+	user_ctx->flags = hdr->flags;
+	user_ctx->user_ref = hdr->user_ref;
+
+	return;
+}
+
+/*!
+ * Handle user-mode Get Random request
+ *
+ * @param user_ctx    The kernel version of user's context
+ * @param user_mode_get_random_req  Pointer to user-space request
+ *
+ * @return an os_error_code
+ */
+static os_error_code get_random(fsl_shw_uco_t * user_ctx,
+				void *user_mode_get_random_req)
+{
+	os_error_code code;
+	struct get_random_req req;
+
+	code = os_copy_from_user(&req, user_mode_get_random_req, sizeof(req));
+	if (code == OS_ERROR_OK_S) {
+		process_hdr(user_ctx, &req.hdr);
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS
+		    ("SHW: get_random() for %d bytes in %sblocking mode",
+		     req.size,
+		     (req.hdr.flags & FSL_UCO_BLOCKING_MODE) ? "" : "non-");
+#endif
+		req.hdr.code =
+		    fsl_shw_get_random(user_ctx, req.size, req.random);
+
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("SHW: get_random() returning %d", req.hdr.code);
+#endif
+
+		/* Copy FSL function status back to user */
+		code = copy_fsl_code(user_mode_get_random_req, req.hdr.code);
+	}
+
+	return code;
+}
+
+/*!
+ * Handle user-mode Add Entropy request
+ *
+ * @param user_ctx    Pointer to the kernel version of user's context
+ * @param user_mode_add_entropy_req  Address of user-space request
+ *
+ * @return an os_error_code
+ */
+static os_error_code add_entropy(fsl_shw_uco_t * user_ctx,
+				 void *user_mode_add_entropy_req)
+{
+	os_error_code code;
+	struct add_entropy_req req;
+	uint8_t *local_buffer = NULL;
+
+	code = os_copy_from_user(&req, user_mode_add_entropy_req, sizeof(req));
+	if (code == OS_ERROR_OK_S) {
+		local_buffer = os_alloc_memory(req.size, 0);	/* for random */
+		if (local_buffer != NULL) {
+			code =
+			    os_copy_from_user(local_buffer, req.entropy,
+					      req.size);
+		}
+		if (code == OS_ERROR_OK_S) {
+			req.hdr.code = fsl_shw_add_entropy(user_ctx, req.size,
+							   local_buffer);
+
+			code =
+			    copy_fsl_code(user_mode_add_entropy_req,
+					  req.hdr.code);
+		}
+	}
+
+	if (local_buffer != NULL) {
+		os_free_memory(local_buffer);
+	}
+
+	return code;
+}
+
+/******************************************************************/
+/* End User Mode Support                                          */
+/******************************************************************/
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_register_user);
+#endif
+/* REQ-S2LRD-PINTFC-API-GEN-004 */
+/*
+ * Handle user registration.
+ *
+ * @param  user_ctx   The user context for the registration.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx)
+{
+	fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S;
+
+	if ((user_ctx->flags & FSL_UCO_BLOCKING_MODE) &&
+	    (user_ctx->flags & FSL_UCO_CALLBACK_MODE)) {
+		code = FSL_RETURN_BAD_FLAG_S;
+		goto error_exit;
+	} else if (user_ctx->pool_size == 0) {
+		code = FSL_RETURN_NO_RESOURCE_S;
+		goto error_exit;
+	} else {
+		user_ctx->result_pool.head = NULL;
+		user_ctx->result_pool.tail = NULL;
+		SHW_ADD_USER(user_ctx);
+		code = FSL_RETURN_OK_S;
+	}
+
+      error_exit:
+	return code;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_deregister_user);
+#endif
+/* REQ-S2LRD-PINTFC-API-GEN-005 */
+/*!
+ * Destroy the association between the the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which is no longer needed.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx)
+{
+	shw_queue_entry_t *finished_request;
+	fsl_shw_return_t ret = FSL_RETURN_OK_S;
+
+	/* Clean up what we find in result pool. */
+	do {
+		os_lock_context_t lock_context;
+		os_lock_save_context(shw_queue_lock, lock_context);
+		finished_request = user_ctx->result_pool.head;
+
+		if (finished_request != NULL) {
+			SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool,
+					       finished_request);
+			os_unlock_restore_context(shw_queue_lock, lock_context);
+			os_free_memory(finished_request);
+		} else {
+			os_unlock_restore_context(shw_queue_lock, lock_context);
+		}
+	} while (finished_request != NULL);
+
+#ifdef FSL_HAVE_SCC2
+	{
+		fsl_shw_spo_t *partition;
+		struct mm_struct *mm = current->mm;
+
+		while ((user_ctx->partition != NULL)
+		       && (ret == FSL_RETURN_OK_S)) {
+
+			partition = user_ctx->partition;
+
+#ifdef SHW_DEBUG
+			LOG_KDIAG_ARGS
+			    ("Found an abandoned secure partition at %p, releasing",
+			     partition);
+#endif
+
+			/* It appears that current->mm is not valid if this is called from a
+			 * close routine (perhaps only if the program raised an exception that
+			 * caused it to close?)  If that is the case, then still free the
+			 * partition, but do not remove it from the memory space (dangerous?)
+			 */
+
+			if (mm == NULL) {
+#ifdef SHW_DEBUG
+				LOG_KDIAG
+				    ("Warning: no mm structure found, not unmapping "
+				     "partition from user memory\n");
+#endif
+			} else {
+				/* Unmap the memory region (see sys_munmap in mmap.c) */
+				/* Note that this assumes a single memory partition */
+				unmap_user_memory(partition->user_base, 8192);
+			}
+
+			/* If the memory was successfully released */
+			if (ret == OS_ERROR_OK_S) {
+				/* release the partition */
+				scc_release_partition(partition->kernel_base);
+
+				/* and remove it from the users context */
+				deregister_user_partition(user_ctx,
+							  partition->user_base);
+
+				ret = FSL_RETURN_OK_S;
+			} else {
+				ret = FSL_RETURN_ERROR_S;
+
+				goto out;
+			}
+		}
+	}
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+
+	SHW_REMOVE_USER(user_ctx);
+
+	return ret;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_get_results);
+#endif
+/* REQ-S2LRD-PINTFC-API-GEN-006 */
+fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx,
+				     unsigned result_size,
+				     fsl_shw_result_t results[],
+				     unsigned *result_count)
+{
+	shw_queue_entry_t *finished_request;
+	unsigned loop = 0;
+
+	do {
+		os_lock_context_t lock_context;
+
+		/* Protect state of user's result pool until we have retrieved and
+		 * remove the first entry, or determined that the pool is empty. */
+		os_lock_save_context(shw_queue_lock, lock_context);
+		finished_request = user_ctx->result_pool.head;
+
+		if (finished_request != NULL) {
+			uint32_t code = 0;
+
+			SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool,
+					       finished_request);
+			os_unlock_restore_context(shw_queue_lock, lock_context);
+
+			results[loop].user_ref = finished_request->user_ref;
+			results[loop].code = finished_request->code;
+			results[loop].detail1 = 0;
+			results[loop].detail2 = 0;
+			results[loop].user_req =
+			    finished_request->user_mode_req;
+			if (finished_request->postprocess != NULL) {
+				code =
+				    finished_request->
+				    postprocess(finished_request);
+			}
+
+			results[loop].code = finished_request->code;
+			os_free_memory(finished_request);
+			if (code == 0) {
+				loop++;
+			}
+		} else {	/* finished_request is NULL */
+			/* pool is empty */
+			os_unlock_restore_context(shw_queue_lock, lock_context);
+		}
+
+	} while ((loop < result_size) && (finished_request != NULL));
+
+	*result_count = loop;
+
+	return FSL_RETURN_OK_S;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_get_capabilities);
+#endif
+fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx)
+{
+
+	/* Unused */
+	(void)user_ctx;
+
+	return &cap;
+}
+
+#if !(defined(FSL_HAVE_SAHARA) || defined(FSL_HAVE_RNGA)                    \
+      || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC))
+
+#if defined(LINUX_VERSION_CODE)
+EXPORT_SYMBOL(fsl_shw_get_random);
+#endif
+fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+				    uint32_t length, uint8_t * data)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)length;
+	(void)data;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#if defined(LINUX_VERSION_CODE)
+EXPORT_SYMBOL(fsl_shw_add_entropy);
+#endif
+fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+				     uint32_t length, uint8_t * data)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)length;
+	(void)data;
+
+	return FSL_RETURN_ERROR_S;
+}
+#endif
+
+#if !defined(FSL_HAVE_DRYICE) && !defined(FSL_HAVE_SAHARA2)
+#if 0
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_symmetric_decrypt);
+#endif
+fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * ct, uint8_t * pt)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)sym_ctx;
+	(void)length;
+	(void)ct;
+	(void)pt;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_symmetric_encrypt);
+#endif
+fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * pt, uint8_t * ct)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)sym_ctx;
+	(void)length;
+	(void)pt;
+	(void)ct;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+/* DryIce support provided in separate file */
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_establish_key);
+#endif
+fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+				       fsl_shw_sko_t * key_info,
+				       fsl_shw_key_wrap_t establish_type,
+				       const uint8_t * key)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)establish_type;
+	(void)key;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_extract_key);
+#endif
+fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     uint8_t * covered_key)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)covered_key;
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_release_key);
+#endif
+fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info)
+{
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+
+	return FSL_RETURN_ERROR_S;
+}
+#endif
+#endif				/* SAHARA or DRYICE */
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_hash);
+#endif
+#if !defined(FSL_HAVE_SAHARA)
+fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_hco_t * hash_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)hash_ctx;
+	(void)msg;
+	(void)length;
+	(void)result;
+	(void)result_len;
+
+	return ret;
+}
+#endif
+
+#ifndef FSL_HAVE_SAHARA
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_hmac_precompute);
+#endif
+
+fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx,
+					 fsl_shw_sko_t * key_info,
+					 fsl_shw_hmco_t * hmac_ctx)
+{
+	fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)hmac_ctx;
+
+	return status;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_hmac);
+#endif
+
+fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_sko_t * key_info,
+			      fsl_shw_hmco_t * hmac_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)key_info;
+	(void)hmac_ctx;
+	(void)msg;
+	(void)length;
+	(void)result;
+	(void)result_len;
+
+	return status;
+}
+#endif
+
+/*!
+ * Call the proper function to encrypt a region of encrypted secure memory
+ *
+ * @brief
+ *
+ * @param   user_ctx        User context of the partition owner (NULL in kernel)
+ * @param   partition_base  Base address (physical) of the partition
+ * @param   offset_bytes    Offset from base address of the data to be encrypted
+ * @param   byte_count      Length of the message (bytes)
+ * @param   black_data      Pointer to where the encrypted data is stored
+ * @param   IV              IV to use for encryption
+ * @param   cypher_mode     Cyphering mode to use, specified by type
+ *                          #fsl_shw_cypher_mode_t
+ *
+ * @return  status
+ */
+fsl_shw_return_t
+do_scc_encrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode)
+{
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+#ifdef FSL_HAVE_SCC2
+
+	scc_return_t scc_ret;
+
+#ifdef SHW_DEBUG
+	uint32_t *owner_32 = (uint32_t *) & (owner_id);
+
+	LOG_KDIAG_ARGS
+	    ("partition base: %p, offset: %i, count: %i, black data: %p\n",
+	     partition_base, offset_bytes, byte_count, (void *)black_data);
+
+	LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]);
+#endif				/* SHW_DEBUG */
+	(void)user_ctx;
+
+	os_cache_flush_range(black_data, byte_count);
+
+	scc_ret =
+	    scc_encrypt_region((uint32_t) partition_base, offset_bytes,
+			       byte_count, __virt_to_phys(black_data), IV,
+			       cypher_mode);
+
+	if (scc_ret == SCC_RET_OK) {
+		retval = FSL_RETURN_OK_S;
+	} else {
+		retval = FSL_RETURN_ERROR_S;
+	}
+
+	/* The SCC2 DMA engine should have written to the black ram, so we need to
+	 * invalidate that region of memory.  Note that the red ram is not an
+	 * because it is mapped with the cache disabled.
+	 */
+	os_cache_inv_range(black_data, byte_count);
+
+#endif				/* FSL_HAVE_SCC2 */
+	return retval;
+}
+
+/*!
+ * Call the proper function to decrypt a region of encrypted secure memory
+ *
+ * @brief
+ *
+ * @param   user_ctx        User context of the partition owner (NULL in kernel)
+ * @param   partition_base  Base address (physical) of the partition
+ * @param   offset_bytes    Offset from base address that the decrypted data
+ *                          shall be placed
+ * @param   byte_count      Length of the message (bytes)
+ * @param   black_data      Pointer to where the encrypted data is stored
+ * @param   IV              IV to use for decryption
+ * @param   cypher_mode     Cyphering mode to use, specified by type
+ *                          #fsl_shw_cypher_mode_t
+ *
+ * @return  status
+ */
+fsl_shw_return_t
+do_scc_decrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, const uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode)
+{
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+
+#ifdef FSL_HAVE_SCC2
+
+	scc_return_t scc_ret;
+
+#ifdef SHW_DEBUG
+	uint32_t *owner_32 = (uint32_t *) & (owner_id);
+
+	LOG_KDIAG_ARGS
+	    ("partition base: %p, offset: %i, count: %i, black data: %p\n",
+	     partition_base, offset_bytes, byte_count, (void *)black_data);
+
+	LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]);
+#endif				/* SHW_DEBUG */
+
+	(void)user_ctx;
+
+	/* The SCC2 DMA engine will be reading from the black ram, so we need to
+	 * make sure that the data is pushed out of the cache.  Note that the red
+	 * ram is not an issue because it is mapped with the cache disabled.
+	 */
+	os_cache_flush_range(black_data, byte_count);
+
+	scc_ret =
+	    scc_decrypt_region((uint32_t) partition_base, offset_bytes,
+			       byte_count,
+			       (uint8_t *) __virt_to_phys(black_data), IV,
+			       cypher_mode);
+
+	if (scc_ret == SCC_RET_OK) {
+		retval = FSL_RETURN_OK_S;
+	} else {
+		retval = FSL_RETURN_ERROR_S;
+	}
+
+#endif				/* FSL_HAVE_SCC2 */
+
+	return retval;
+}
+
+void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx,
+		      uint32_t size, const uint8_t * UMID, uint32_t permissions)
+{
+#ifdef FSL_HAVE_SCC2
+	int part_no;
+	void *part_base;
+	uint32_t part_phys;
+	scc_config_t *scc_configuration;
+
+	/* Check that the memory size requested is correct */
+	scc_configuration = scc_get_configuration();
+	if (size != scc_configuration->partition_size_bytes) {
+		return NULL;
+	}
+
+	/* attempt to grab a partition. */
+	if (scc_allocate_partition(0, &part_no, &part_base, &part_phys)
+	    != SCC_RET_OK) {
+		return NULL;
+	}
+#ifdef SHW_DEBUG
+	LOG_KDIAG_ARGS("Partition_base: %p, partition_base_phys: %p\n",
+		       part_base, (void *)part_phys);
+#endif
+
+	if (scc_engage_partition(part_base, UMID, permissions)
+	    != SCC_RET_OK) {
+		/* Engagement failed, so the partition needs to be de-allocated */
+
+#ifdef SHW_DEBUG
+		LOG_KDIAG_ARGS("Failed to engage partition %p, de-allocating",
+			       part_base);
+#endif
+		scc_release_partition(part_base);
+
+		return NULL;
+	}
+
+	return part_base;
+
+#else				/* FSL_HAVE_SCC2 */
+
+	(void)user_ctx;
+	(void)size;
+	(void)UMID;
+	(void)permissions;
+	return NULL;
+
+#endif				/* FSL_HAVE_SCC2 */
+}
+
+/* Release a block of secure memory */
+fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address)
+{
+	(void)user_ctx;
+
+#ifdef FSL_HAVE_SCC2
+	if (scc_release_partition(address) == SCC_RET_OK) {
+		return FSL_RETURN_OK_S;
+	}
+#endif
+
+	return FSL_RETURN_ERROR_S;
+}
+
+/* Check the status of a block of secure memory */
+fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx,
+				 void *address,
+				 fsl_shw_partition_status_t * part_status)
+{
+	(void)user_ctx;
+
+#ifdef FSL_HAVE_SCC2
+	*part_status = scc_partition_status(address);
+
+	return FSL_RETURN_OK_S;
+#endif
+
+	return FSL_RETURN_ERROR_S;
+}
+
+/* Diminish permissions on some secure memory */
+fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx,
+					void *address, uint32_t permissions)
+{
+
+	(void)user_ctx;		/* unused parameter warning */
+
+#ifdef FSL_HAVE_SCC2
+	if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) {
+		return FSL_RETURN_OK_S;
+	}
+#endif
+	return FSL_RETURN_ERROR_S;
+}
+
+#ifndef FSL_HAVE_SAHARA
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_gen_encrypt);
+#endif
+
+fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_acco_t * auth_ctx,
+				     fsl_shw_sko_t * cipher_key_info,
+				     fsl_shw_sko_t * auth_key_info,
+				     uint32_t auth_data_length,
+				     const uint8_t * auth_data,
+				     uint32_t payload_length,
+				     const uint8_t * payload,
+				     uint8_t * ct, uint8_t * auth_value)
+{
+	volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)auth_ctx;
+	(void)cipher_key_info;
+	(void)auth_key_info;	/* save compilation warning */
+	(void)auth_data_length;
+	(void)auth_data;
+	(void)payload_length;
+	(void)payload;
+	(void)ct;
+	(void)auth_value;
+
+	return status;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_auth_decrypt);
+#endif
+/*!
+ * @brief Authenticate and decrypt a (CCM) stream.
+ *
+ * @param user_ctx         The user's context
+ * @param auth_ctx         Info on this Auth operation
+ * @param cipher_key_info  Key to encrypt payload
+ * @param auth_key_info    (unused - same key in CCM)
+ * @param auth_data_length Length in bytes of @a auth_data
+ * @param auth_data        Any auth-only data
+ * @param payload_length   Length in bytes of @a payload
+ * @param ct               The encrypted data
+ * @param auth_value       The authentication code to validate
+ * @param[out] payload     The location to store decrypted data
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx,
+				      fsl_shw_acco_t * auth_ctx,
+				      fsl_shw_sko_t * cipher_key_info,
+				      fsl_shw_sko_t * auth_key_info,
+				      uint32_t auth_data_length,
+				      const uint8_t * auth_data,
+				      uint32_t payload_length,
+				      const uint8_t * ct,
+				      const uint8_t * auth_value,
+				      uint8_t * payload)
+{
+	volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	/* Unused */
+	(void)user_ctx;
+	(void)auth_ctx;
+	(void)cipher_key_info;
+	(void)auth_key_info;	/* save compilation warning */
+	(void)auth_data_length;
+	(void)auth_data;
+	(void)payload_length;
+	(void)ct;
+	(void)auth_value;
+	(void)payload;
+
+	return status;
+}
+
+#endif				/* no SAHARA */
+
+#ifndef FSL_HAVE_DRYICE
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_gen_random_pf_key);
+#endif
+/*!
+ * Cause the hardware to create a new random key for secure memory use.
+ *
+ * Have the hardware use the secure hardware random number generator to load a
+ * new secret key into the hardware random key register.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx)
+{
+	volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S;
+
+	return status;
+}
+
+#endif				/* not have DRYICE */
+
+fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx, fsl_shw_sko_t * key_info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_alloc(user_ctx,
+						    key_info->key_length,
+						    key_info->userid,
+						    &(key_info->handle));
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("key length: %i, handle: %i",
+			      key_info->key_length, key_info->handle);
+#endif
+
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_alloc(key_info->keystore,
+					  key_info->key_length,
+					  key_info->userid,
+					  &(key_info->handle));
+	}
+
+	return ret;
+}				/* end fn alloc_slot */
+
+fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx,
+			   fsl_shw_sko_t * key_info, const uint8_t * key)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_load(user_ctx,
+						   key_info->userid,
+						   key_info->handle, key,
+						   key_info->key_length);
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_load(key_info->keystore,
+					 key_info->userid,
+					 key_info->handle, key,
+					 key_info->key_length);
+	}
+
+	return ret;
+}				/* end fn load_slot */
+
+fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_sko_t * key_info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		do_system_keystore_slot_dealloc(user_ctx,
+						key_info->userid,
+						key_info->handle);
+	} else {
+		/* Key goes in user keystore */
+		keystore_slot_dealloc(key_info->keystore,
+				      key_info->userid, key_info->handle);
+	}
+
+	key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT);
+
+	return ret;
+}				/* end fn slot_dealloc */
diff --git a/drivers/mxc/security/rng/shw_dryice.c b/drivers/mxc/security/rng/shw_dryice.c
new file mode 100644
index 000000000000..1fbd4bfef986
--- /dev/null
+++ b/drivers/mxc/security/rng/shw_dryice.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "shw_driver.h"
+#include "../dryice.h"
+
+#include <diagnostic.h>
+
+#ifdef FSL_HAVE_DRYICE
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_gen_random_pf_key);
+#endif
+/*!
+ * Cause the hardware to create a new random key for secure memory use.
+ *
+ * Have the hardware use the secure hardware random number generator to load a
+ * new secret key into the hardware random key register.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+	di_return_t di_ret;
+
+	/* For now, only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	di_ret = dryice_set_random_key(0);
+	if (di_ret != DI_SUCCESS) {
+		printk("dryice_set_random_key returned %d\n", di_ret);
+		goto out;
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	return ret;
+}
+
+#ifdef LINUX_VERSION_CODE
+EXPORT_SYMBOL(fsl_shw_read_tamper_event);
+#endif
+fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_tamper_t * tamperp,
+					   uint64_t * timestampp)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+	di_return_t di_ret;
+	uint32_t di_events = 0;
+	uint32_t di_time_stamp;
+
+	/* Only blocking mode calls are supported */
+	if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	di_ret = dryice_get_tamper_event(&di_events, &di_time_stamp, 0);
+	if ((di_ret != DI_SUCCESS) && (di_ret != DI_ERR_STATE)) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS("dryice_get_tamper_event returned %s\n",
+			      di_error_string(di_ret));
+#endif
+		goto out;
+	}
+
+	/* Pass time back to caller */
+	*timestampp = (uint64_t) di_time_stamp;
+
+	if (di_events & DI_TAMPER_EVENT_WTD) {
+		*tamperp = FSL_SHW_TAMPER_WTD;
+	} else if (di_events & DI_TAMPER_EVENT_ETBD) {
+		*tamperp = FSL_SHW_TAMPER_ETBD;
+	} else if (di_events & DI_TAMPER_EVENT_ETAD) {
+		*tamperp = FSL_SHW_TAMPER_ETAD;
+	} else if (di_events & DI_TAMPER_EVENT_EBD) {
+		*tamperp = FSL_SHW_TAMPER_EBD;
+	} else if (di_events & DI_TAMPER_EVENT_SAD) {
+		*tamperp = FSL_SHW_TAMPER_SAD;
+	} else if (di_events & DI_TAMPER_EVENT_TTD) {
+		*tamperp = FSL_SHW_TAMPER_TTD;
+	} else if (di_events & DI_TAMPER_EVENT_CTD) {
+		*tamperp = FSL_SHW_TAMPER_CTD;
+	} else if (di_events & DI_TAMPER_EVENT_VTD) {
+		*tamperp = FSL_SHW_TAMPER_VTD;
+	} else if (di_events & DI_TAMPER_EVENT_MCO) {
+		*tamperp = FSL_SHW_TAMPER_MCO;
+	} else if (di_events & DI_TAMPER_EVENT_TCO) {
+		*tamperp = FSL_SHW_TAMPER_TCO;
+	} else if (di_events != 0) {
+		/* Apparentliy a tamper type not known to this driver was detected */
+		goto out;
+	} else {
+		*tamperp = FSL_SHW_TAMPER_NONE;
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	return ret;
+}				/* end fn fsl_shw_read_tamper_event */
+#endif
+/*!
+ * Convert an SHW HW key reference into a DI driver key reference
+ *
+ * @param shw_pf_key   An SHW HW key value
+ * @param di_keyp      Location to store the equivalent DI driver key
+ *
+ * @return FSL_RETURN_OK_S, or error if key is unknown or cannot translate.
+ */
+fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key,
+				    di_key_t * di_keyp)
+{
+	fsl_shw_return_t ret = FSL_RETURN_BAD_FLAG_S;
+
+	switch (shw_pf_key) {
+	case FSL_SHW_PF_KEY_IIM:
+		*di_keyp = DI_KEY_FK;
+		break;
+	case FSL_SHW_PF_KEY_RND:
+		*di_keyp = DI_KEY_RK;
+		break;
+	case FSL_SHW_PF_KEY_IIM_RND:
+		*di_keyp = DI_KEY_FRK;
+		break;
+	case FSL_SHW_PF_KEY_PRG:
+		*di_keyp = DI_KEY_PK;
+		break;
+	case FSL_SHW_PF_KEY_IIM_PRG:
+		*di_keyp = DI_KEY_FPK;
+		break;
+	default:
+		goto out;
+	}
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+	return ret;
+}
+
+#ifdef DIAG_SECURITY_FUNC
+const char *di_error_string(int code)
+{
+	char *str = "unknown";
+
+	switch (code) {
+	case DI_SUCCESS:
+		str = "operation was successful";
+		break;
+	case DI_ERR_BUSY:
+		str = "device or resource busy";
+		break;
+	case DI_ERR_STATE:
+		str = "dryice is in incompatible state";
+		break;
+	case DI_ERR_INUSE:
+		str = "resource is already in use";
+		break;
+	case DI_ERR_UNSET:
+		str = "resource has not been initialized";
+		break;
+	case DI_ERR_WRITE:
+		str = "error occurred during register write";
+		break;
+	case DI_ERR_INVAL:
+		str = "invalid argument";
+		break;
+	case DI_ERR_FAIL:
+		str = "operation failed";
+		break;
+	case DI_ERR_HLOCK:
+		str = "resource is hard locked";
+		break;
+	case DI_ERR_SLOCK:
+		str = "resource is soft locked";
+		break;
+	case DI_ERR_NOMEM:
+		str = "out of memory";
+		break;
+	default:
+		break;
+	}
+
+	return str;
+}
+#endif				/* HAVE DRYICE */
diff --git a/drivers/mxc/security/rng/shw_hash.c b/drivers/mxc/security/rng/shw_hash.c
new file mode 100644
index 000000000000..d87e1b75a7bc
--- /dev/null
+++ b/drivers/mxc/security/rng/shw_hash.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file shw_hash.c
+ *
+ * This file contains implementations for use of the (internal) SHW hash
+ * software computation.  It defines the usual three steps:
+ *
+ * - #shw_hash_init()
+ * - #shw_hash_update()
+ * - #shw_hash_final()
+ *
+ * In support of the above functions, it also contains these functions:
+ * - #sha256_init()
+ * - #sha256_process_block()
+ *
+ *
+ * These functions depend upon the Linux Endian functions __be32_to_cpu(),
+ * __cpu_to_be32() to convert a 4-byte big-endian array to an integer and
+ * vice-versa.  For those without Linux, it should be pretty obvious what they
+ * do.
+ *
+ * The #shw_hash_update() and #shw_hash_final() functions are generic enough to
+ * support SHA-1/SHA-224/SHA-256, as needed.  Some extra tweaking would be
+ * necessary to get them to support SHA-384/SHA-512.
+ *
+ */
+
+#include "shw_driver.h"
+#include "shw_hash.h"
+
+#ifndef __KERNEL__
+#include <asm/types.h>
+#include <linux/byteorder/little_endian.h>	/* or whichever is proper for target arch */
+#define printk printf
+#endif
+
+/*!
+ * Rotate a value right by a number of bits.
+ *
+ * @param x   Word of data which needs rotating
+ * @param y   Number of bits to rotate
+ *
+ * @return The new value
+ */
+inline uint32_t rotr32fixed(uint32_t x, unsigned int y)
+{
+	return (uint32_t) ((x >> y) | (x << (32 - y)));
+}
+
+#define blk0(i) (W[i] = data[i])
+// Referencing parameters so many times is really poor practice.  Do not imitate these macros
+#define blk2(i) (W[i & 15] += s1(W[(i - 2) & 15]) + W[(i - 7) & 15] + s0(W[(i - 15) & 15]))
+
+#define Ch(x,y,z) (z ^ (x & (y ^ z)))
+#define Maj(x,y,z) ((x & y) | (z & (x | y)))
+
+#define a(i) T[(0 - i) & 7]
+#define b(i) T[(1 - i) & 7]
+#define c(i) T[(2 - i) & 7]
+#define d(i) T[(3 - i) & 7]
+#define e(i) T[(4 - i) & 7]
+#define f(i) T[(5 - i) & 7]
+#define g(i) T[(6 - i) & 7]
+#define h(i) T[(7 - i) & 7]
+
+// This is a bad way to write a multi-statement macro... and referencing 'i' so many
+// times is really poor practice.  Do not imitate.
+#define R(i) h(i) += S1( e(i)) + Ch(e(i), f(i), g(i)) + K[i + j] +(j ? blk2(i) : blk0(i));\
+        d(i) += h(i);h(i) += S0(a(i)) + Maj(a(i), b(i), c(i))
+
+// for SHA256
+#define S0(x) (rotr32fixed(x, 2) ^ rotr32fixed(x, 13) ^ rotr32fixed(x, 22))
+#define S1(x) (rotr32fixed(x, 6) ^ rotr32fixed(x, 11) ^ rotr32fixed(x, 25))
+#define s0(x) (rotr32fixed(x, 7) ^ rotr32fixed(x, 18) ^ (x >> 3))
+#define s1(x) (rotr32fixed(x, 17) ^ rotr32fixed(x, 19) ^ (x >> 10))
+
+/*!
+ * Initialize the Hash State
+ *
+ *  Constructs the SHA256 hash engine.
+ *  Specification:
+ *      State Size  = 32 bytes
+ *      Block Size  = 64 bytes
+ *      Digest Size = 32 bytes
+ *
+ * @param state     Address of hash state structure
+ *
+ */
+void sha256_init(shw_hash_state_t * state)
+{
+	state->bit_count = 0;
+	state->partial_count_bytes = 0;
+
+	state->state[0] = 0x6a09e667;
+	state->state[1] = 0xbb67ae85;
+	state->state[2] = 0x3c6ef372;
+	state->state[3] = 0xa54ff53a;
+	state->state[4] = 0x510e527f;
+	state->state[5] = 0x9b05688c;
+	state->state[6] = 0x1f83d9ab;
+	state->state[7] = 0x5be0cd19;
+}
+
+const uint32_t K[64] = {
+	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
+	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
+	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
+	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
+	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
+	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
+	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
+	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
+	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
+	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
+	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+/*!
+ * Hash a block of data into the SHA-256 hash state.
+ *
+ * This function hash the block of data in the @c partial_block
+ * element of the state structure into the state variables of the
+ * state structure.
+ *
+ * @param state     Address of hash state structure
+ *
+ */
+static void sha256_process_block(shw_hash_state_t * state)
+{
+	uint32_t W[16];
+	uint32_t T[8];
+	uint32_t stack_buffer[SHW_HASH_BLOCK_WORD_SIZE];
+	uint32_t *data = &stack_buffer[0];
+	uint8_t *input = state->partial_block;
+	unsigned int i;
+	unsigned int j;
+
+	/* Copy byte-oriented input block into word-oriented registers */
+	for (i = 0; i < SHW_HASH_BLOCK_LEN / sizeof(uint32_t);
+	     i++, input += sizeof(uint32_t)) {
+		stack_buffer[i] = __be32_to_cpu(*(uint32_t *) input);
+	}
+
+	/* Copy context->state[] to working vars */
+	memcpy(T, state->state, sizeof(T));
+
+	/* 64 operations, partially loop unrolled */
+	for (j = 0; j < SHW_HASH_BLOCK_LEN; j += 16) {
+		R(0);
+		R(1);
+		R(2);
+		R(3);
+		R(4);
+		R(5);
+		R(6);
+		R(7);
+		R(8);
+		R(9);
+		R(10);
+		R(11);
+		R(12);
+		R(13);
+		R(14);
+		R(15);
+	}
+	/* Add the working vars back into context.state[] */
+	state->state[0] += a(0);
+	state->state[1] += b(0);
+	state->state[2] += c(0);
+	state->state[3] += d(0);
+	state->state[4] += e(0);
+	state->state[5] += f(0);
+	state->state[6] += g(0);
+	state->state[7] += h(0);
+
+	/* Wipe variables */
+	memset(W, 0, sizeof(W));
+	memset(T, 0, sizeof(T));
+}
+
+/*!
+ * Initialize the hash state structure
+ *
+ * @param state     Address of hash state structure.
+ * @param alg Which hash algorithm to use (must be FSL_HASH_ALG_SHA1)
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hash_init(shw_hash_state_t * state, fsl_shw_hash_alg_t alg)
+{
+	if (alg != FSL_HASH_ALG_SHA256) {
+		return FSL_RETURN_BAD_ALGORITHM_S;
+	}
+
+	sha256_init(state);
+
+	return FSL_RETURN_OK_S;
+}
+
+/*!
+ * Add input bytes to the hash
+ *
+ * The bytes are added to the partial_block element of the hash state, and as
+ * the partial block is filled, it is processed by sha1_process_block().  This
+ * function also updates the bit_count element of the hash state.
+ *
+ * @param state     Address of hash state structure
+ * @param input     Address of bytes to add to the hash
+ * @param input_len Numbef of bytes at @c input
+ *
+ */
+fsl_shw_return_t shw_hash_update(shw_hash_state_t * state,
+				 const uint8_t * input, unsigned int input_len)
+{
+	unsigned int bytes_needed;	/* Needed to fill a block */
+	unsigned int bytes_to_copy;	/* to copy into the block */
+
+	/* Account for new data */
+	state->bit_count += 8 * input_len;
+
+	/*
+	 * Process input bytes into the ongoing block; process the block when it
+	 * gets full.
+	 */
+	while (input_len > 0) {
+		bytes_needed = SHW_HASH_BLOCK_LEN - state->partial_count_bytes;
+		bytes_to_copy = ((input_len < bytes_needed) ?
+				 input_len : bytes_needed);
+
+		/* Add in the bytes and do the accounting */
+		memcpy(state->partial_block + state->partial_count_bytes,
+		       input, bytes_to_copy);
+		input += bytes_to_copy;
+		input_len -= bytes_to_copy;
+		state->partial_count_bytes += bytes_to_copy;
+
+		/* Run a full block through the transform */
+		if (state->partial_count_bytes == SHW_HASH_BLOCK_LEN) {
+			sha256_process_block(state);
+			state->partial_count_bytes = 0;
+		}
+	}
+
+	return FSL_RETURN_OK_S;
+}				/* end fn shw_hash_update */
+
+/*!
+ * Finalize the hash
+ *
+ * Performs the finalize operation on the previous input data & returns the
+ * resulting digest.  The finalize operation performs the appropriate padding
+ * up to the block size.
+ *
+ * @param state     Address of hash state structure
+ * @param result    Location to store the hash result
+ * @param result_len Number of bytes of @c result to be stored.
+ *
+ * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if
+ * hash_len is too long, otherwise an error code.
+ */
+fsl_shw_return_t shw_hash_final(shw_hash_state_t * state, uint8_t * result,
+				unsigned int result_len)
+{
+	static const uint8_t pad[SHW_HASH_BLOCK_LEN * 2] = {
+		0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+	};
+
+	uint8_t data[sizeof(state->bit_count)];
+	uint32_t pad_length;
+	uint64_t bit_count = state->bit_count;
+	uint8_t hash[SHW_HASH_LEN];
+	int i;
+
+	if (result_len > SHW_HASH_LEN) {
+		return FSL_RETURN_BAD_DATA_LENGTH_S;
+	}
+
+	/* Save the length before padding. */
+	for (i = sizeof(state->bit_count) - 1; i >= 0; i--) {
+		data[i] = bit_count & 0xFF;
+		bit_count >>= 8;
+	}
+	pad_length = ((state->partial_count_bytes < 56) ?
+		      (56 - state->partial_count_bytes) :
+		      (120 - state->partial_count_bytes));
+
+	/* Pad to 56 bytes mod 64 (BLOCK_SIZE). */
+	shw_hash_update(state, pad, pad_length);
+
+	/*
+	 * Append the length.  This should trigger transform of the final block.
+	 */
+	shw_hash_update(state, data, sizeof(state->bit_count));
+
+	/* Copy the result into a byte array */
+	for (i = 0; i < SHW_HASH_STATE_WORDS; i++) {
+		*(uint32_t *) (hash + 4 * i) = __cpu_to_be32(state->state[i]);
+	}
+
+	/* And copy the result out to caller */
+	memcpy(result, hash, result_len);
+
+	return FSL_RETURN_OK_S;
+}				/* end fn shw_hash_final */
diff --git a/drivers/mxc/security/rng/shw_hmac.c b/drivers/mxc/security/rng/shw_hmac.c
new file mode 100644
index 000000000000..215f3d25055c
--- /dev/null
+++ b/drivers/mxc/security/rng/shw_hmac.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file shw_hmac.c
+ *
+ * This file contains implementations for use of the (internal) SHW HMAC
+ * software computation.  It defines the usual three steps:
+ *
+ * - #shw_hmac_init()
+ * - #shw_hmac_update()
+ * - #shw_hmac_final()
+ *
+ *
+ */
+
+#include "shw_driver.h"
+#include "shw_hmac.h"
+
+#ifndef __KERNEL__
+#include <asm/types.h>
+#include <linux/byteorder/little_endian.h>	/* or whichever is proper for target arch */
+#define printk printf
+#endif
+
+/*! XOR value for HMAC inner key */
+#define INNER_HASH_CONSTANT 0x36
+
+/*! XOR value for HMAC outer key */
+#define OUTER_HASH_CONSTANT 0x5C
+
+/*!
+ * Initialize the HMAC state structure with the HMAC key
+ *
+ * @param state     Address of HMAC state structure
+ * @param key       Address of the key to be used for the HMAC.
+ * @param key_len   Number of bytes of @c key.
+ *
+ * Convert the key into its equivalent inner and outer hash state objects.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state,
+			       const uint8_t * key, unsigned int key_len)
+{
+	fsl_shw_return_t code = FSL_RETURN_ERROR_S;
+	uint8_t first_block[SHW_HASH_BLOCK_LEN];
+	unsigned int i;
+
+	/* Don't bother handling the pre-hash. */
+	if (key_len > SHW_HASH_BLOCK_LEN) {
+		code = FSL_RETURN_BAD_KEY_LENGTH_S;
+		goto out;
+	}
+
+	/* Prepare inner hash */
+	for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) {
+		if (i < key_len) {
+			first_block[i] = key[i] ^ INNER_HASH_CONSTANT;
+		} else {
+			first_block[i] = INNER_HASH_CONSTANT;
+		}
+	}
+	code = shw_hash_init(&state->inner_hash, FSL_HASH_ALG_SHA256);
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	shw_hash_update(&state->inner_hash, first_block, SHW_HASH_BLOCK_LEN);
+
+	/* Prepare outer hash */
+	for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) {
+		if (i < key_len) {
+			first_block[i] = key[i] ^ OUTER_HASH_CONSTANT;
+		} else {
+			first_block[i] = OUTER_HASH_CONSTANT;
+		}
+	}
+	code = shw_hash_init(&state->outer_hash, FSL_HASH_ALG_SHA256);
+	if (code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	shw_hash_update(&state->outer_hash, first_block, SHW_HASH_BLOCK_LEN);
+
+	/* Wipe evidence of key */
+	memset(first_block, 0, SHW_HASH_BLOCK_LEN);
+
+      out:
+	return code;
+}
+
+/*!
+ * Put data into the HMAC calculation
+ *
+ * Send the msg data inner inner hash's update function.
+ *
+ * @param state     Address of HMAC state structure.
+ * @param msg       Address of the message data for the HMAC.
+ * @param msg_len   Number of bytes of @c msg.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state,
+				 const uint8_t * msg, unsigned int msg_len)
+{
+	shw_hash_update(&state->inner_hash, msg, msg_len);
+
+	return FSL_RETURN_OK_S;
+}
+
+/*!
+ * Calculate the final HMAC
+ *
+ * @param state     Address of HMAC state structure.
+ * @param hmac      Address of location to store the HMAC.
+ * @param hmac_len  Number of bytes of @c mac to be stored.  Probably best if
+ *                  this value is no greater than #SHW_HASH_LEN.
+ *
+ * This function finalizes the internal hash, and uses that result as
+ * data for the outer hash.  As many bytes of that result are passed
+ * to the user as desired.
+ *
+ * @return  FSL_RETURN_OK_S if all went well, otherwise an error code.
+ */
+fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state,
+				uint8_t * hmac, unsigned int hmac_len)
+{
+	uint8_t hash_result[SHW_HASH_LEN];
+
+	shw_hash_final(&state->inner_hash, hash_result, sizeof(hash_result));
+	shw_hash_update(&state->outer_hash, hash_result, SHW_HASH_LEN);
+
+	shw_hash_final(&state->outer_hash, hmac, hmac_len);
+
+	return FSL_RETURN_OK_S;
+}
diff --git a/drivers/mxc/security/rng/shw_memory_mapper.c b/drivers/mxc/security/rng/shw_memory_mapper.c
new file mode 100644
index 000000000000..71f1d301f02a
--- /dev/null
+++ b/drivers/mxc/security/rng/shw_memory_mapper.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+
+/**
+ * Memory management functions, from Sahara Crypto API
+ *
+ * This is a subset of the memory management functions from the Sahara Crypto
+ * API, and is intended to support user secure partitions.
+ */
+
+#include "portable_os.h"
+#include "fsl_shw.h"
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/pagemap.h>
+
+#ifdef SHW_DEBUG
+#include <diagnostic.h>
+#endif
+
+/* Page context structure.  Used by wire_user_memory and unwire_user_memory */
+typedef struct page_ctx_t {
+    uint32_t        count;
+    struct page   **local_pages;
+} page_ctx_t;
+
+/**
+*******************************************************************************
+* Map and wire down a region of user memory.
+*
+*
+* @param    address     Userspace address of the memory to wire
+* @param    length      Length of the memory region to wire
+* @param    page_ctx    Page context, to be passed to unwire_user_memory
+*
+* @return   (if successful) Kernel virtual address of the wired pages
+*/
+void* wire_user_memory(void* address, uint32_t length, void **page_ctx)
+{
+    void* kernel_black_addr = NULL;
+    int result = -1;
+    int page_index = 0;
+    page_ctx_t *page_context;
+    int nr_pages = 0;
+    unsigned long start_page;
+    fsl_shw_return_t status;
+
+    /* Determine the number of pages being used for this link */
+    nr_pages = (((unsigned long)(address) & ~PAGE_MASK)
+                + length + ~PAGE_MASK) >> PAGE_SHIFT;
+
+    start_page = (unsigned long)(address) & PAGE_MASK;
+
+    /* Allocate some memory to keep track of the wired user pages, so that
+     * they can be deallocated later.  The block of memory will contain both
+     * the structure and the array of pages.
+     */
+    page_context = kmalloc(sizeof(page_ctx_t)
+                           + nr_pages * sizeof(struct page *), GFP_KERNEL);
+
+    if (page_context == NULL) {
+        status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */
+#ifdef DIAG_DRV_IF
+        LOG_KDIAG("kmalloc() failed.");
+#endif
+        return NULL;
+    }
+
+    /* Set the page pointer to point to the allocated region of memory */
+    page_context->local_pages = (void*)page_context + sizeof(page_ctx_t);
+
+#ifdef DIAG_DRV_IF
+    LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p",
+                   (void *)page_context,
+                   (void *)(page_context->local_pages));
+#endif
+
+    /* Wire down the pages from user space */
+    down_read(&current->mm->mmap_sem);
+    result = get_user_pages(current, current->mm,
+                            start_page, nr_pages,
+                            WRITE, 0 /* noforce */,
+                            (page_context->local_pages), NULL);
+    up_read(&current->mm->mmap_sem);
+
+    if (result < nr_pages) {
+#ifdef DIAG_DRV_IF
+        LOG_KDIAG("get_user_pages() failed.");
+#endif
+        if (result > 0) {
+            for (page_index = 0; page_index < result; page_index++)
+                page_cache_release((page_context->local_pages[page_index]));
+
+            kfree(page_context);
+        }
+        return NULL;
+    }
+
+    kernel_black_addr = page_address(page_context->local_pages[0]) +
+                        ((unsigned long)address & ~PAGE_MASK);
+
+    page_context->count = nr_pages;
+    *page_ctx = page_context;
+
+    return kernel_black_addr;
+}
+
+
+/**
+*******************************************************************************
+* Release and unmap a region of user memory.
+*
+* @param    page_ctx    Page context from wire_user_memory
+*/
+void unwire_user_memory(void** page_ctx)
+{
+    int page_index = 0;
+    struct page_ctx_t *page_context = *page_ctx;
+
+#ifdef DIAG_DRV_IF
+    LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i",
+                   (void *)page_context,
+                   (void *)(page_context->local_pages),
+                   page_context->count);
+#endif
+
+    if ((page_context != NULL) && (page_context->local_pages != NULL)) {
+        for (page_index = 0; page_index < page_context->count; page_index++)
+            page_cache_release(page_context->local_pages[page_index]);
+
+        kfree(page_context);
+        *page_ctx = NULL;
+    }
+}
+
+
+/**
+*******************************************************************************
+* Map some physical memory into a users memory space
+*
+* @param    vma             Memory structure to map to
+* @param    physical_addr   Physical address of the memory to be mapped in
+* @param    size            Size of the memory to map (bytes)
+*
+* @return
+*/
+os_error_code
+map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr, uint32_t size)
+{
+    os_error_code retval;
+
+    /* Map the acquired partition into the user's memory space */
+    vma->vm_end = vma->vm_start + size;
+
+    /* set cache policy to uncached so that each write of the UMID and
+     * permissions get directly to the SCC2 in order to engage it
+     * properly.  Once the permissions have been written, it may be
+     * useful to provide a service for the user to request a different
+     * cache policy
+     */
+    vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+    /* Make sure that the user cannot fork() a child which will inherit
+     * this mapping, as it creates a security hole.  Likewise, do not
+     * allow the user to 'expand' his mapping beyond this partition.
+     */
+    vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND;
+
+    retval = remap_pfn_range(vma,
+                             vma->vm_start,
+                             __phys_to_pfn(physical_addr),
+                             size,
+                             vma->vm_page_prot);
+
+    return retval;
+}
+
+
+/**
+*******************************************************************************
+* Remove some memory from a user's memory space
+*
+* @param    user_addr       Userspace address of the memory to be unmapped
+* @param    size            Size of the memory to map (bytes)
+*
+* @return
+*/
+os_error_code
+unmap_user_memory(uint32_t user_addr, uint32_t size)
+{
+    os_error_code retval;
+    struct mm_struct *mm = current->mm;
+
+    /* Unmap the memory region (see sys_munmap in mmap.c) */
+    down_write(&mm->mmap_sem);
+    retval = do_munmap(mm, (unsigned long)user_addr, size);
+    up_write(&mm->mmap_sem);
+
+    return retval;
+}
diff --git a/drivers/mxc/security/sahara2/Kconfig b/drivers/mxc/security/sahara2/Kconfig
new file mode 100644
index 000000000000..ab4e6fdc2cfc
--- /dev/null
+++ b/drivers/mxc/security/sahara2/Kconfig
@@ -0,0 +1,35 @@
+menu "SAHARA2 Security Hardware Support"
+
+config MXC_SAHARA
+	tristate "Security Hardware Support (FSL SHW)"
+	---help---
+	  Provides driver and kernel mode API for using cryptographic
+	  accelerators.
+
+config MXC_SAHARA_USER_MODE
+	tristate "User Mode API for FSL SHW"
+	depends on MXC_SAHARA
+	---help---
+	  Provides kernel driver for User Mode API.
+
+config MXC_SAHARA_POLL_MODE
+	bool "Force driver to POLL for hardware completion."
+	depends on MXC_SAHARA
+	default n
+	---help---
+	  When this flag is yes, the driver will not use interrupts to
+	  determine when the hardware has completed a task, but instead
+	  will hold onto the CPU and continually poll the hardware until
+	  it completes.
+
+config MXC_SAHARA_POLL_MODE_TIMEOUT
+    hex "Poll loop timeout"
+    depends on MXC_SAHARA_POLL_MODE
+    default "0xFFFFFFFF"
+    help
+        To avoid infinite polling, a timeout is provided. Should the
+        timeout be reached, a fault is reported, indicating there must
+        be something wrong with SAHARA, and SAHARA is reset. The loop
+        will exit after the given number of iterations.
+
+endmenu
diff --git a/drivers/mxc/security/sahara2/Makefile b/drivers/mxc/security/sahara2/Makefile
new file mode 100644
index 000000000000..b515709be29b
--- /dev/null
+++ b/drivers/mxc/security/sahara2/Makefile
@@ -0,0 +1,47 @@
+# Makefile for the Linux Sahara2 driver
+#
+# This makefile works within a kernel driver tree
+
+# Need to augment this to support optionally building user-mode support
+API_SOURCES = fsl_shw_sym.c  fsl_shw_user.c  fsl_shw_hash.c  fsl_shw_auth.c \
+              fsl_shw_hmac.c  fsl_shw_rand.c  sf_util.c  km_adaptor.c  fsl_shw_keystore.c  \
+              fsl_shw_wrap.c \
+
+
+SOURCES = sah_driver_interface.c  sah_hardware_interface.c            \
+          sah_interrupt_handler.c  sah_queue.c  sah_queue_manager.c   \
+          sah_status_manager.c  sah_memory_mapper.c
+
+
+# Turn on for mostly full debugging
+# DIAGS = -DDIAG_DRV_STATUS -DDIAG_DRV_QUEUE -DDIAG_DRV_INTERRUPT -DDIAG_DRV_IF
+# DIAGS += -DDIAG_DURING_INTERRUPT
+
+# Turn on for lint-type checking
+#EXTRA_CFLAGS = -Wall -W -Wstrict-prototypes -Wmissing-prototypes
+EXTRA_CFLAGS += -DLINUX_KERNEL $(DIAGS)
+
+
+ifeq ($(CONFIG_MXC_SAHARA_POLL_MODE),y)
+EXTRA_CFLAGS += -DSAHARA_POLL_MODE
+EXTRA_CFLAGS += -DSAHARA_POLL_MODE_TIMEOUT=$(CONFIG_SAHARA_POLL_MODE_TIMEOUT)
+endif
+
+ifeq ($(CONFIG_MXC_SAHARA_USER_MODE),y)
+EXTRA_CFLAGS += -DSAHARA_USER_MODE
+SOURCES +=
+endif
+
+ifeq ($(CONFIG_PM),y)
+EXTRA_CFLAGS += -DSAHARA_POWER_MANAGMENT
+endif
+
+EXTRA_CFLAGS += -Idrivers/mxc/security/sahara2/include
+
+# handle buggy BSP -- uncomment if these are undefined during build
+#EXTRA_CFLAGS += -DSAHARA_BASE_ADDR=HAC_BASE_ADDR -DINT_SAHARA=INT_HAC_RTIC
+
+
+obj-$(CONFIG_MXC_SAHARA) += sahara.o
+
+sahara-objs := $(SOURCES:.c=.o) $(API_SOURCES:.c=.o)
diff --git a/drivers/mxc/security/sahara2/fsl_shw_auth.c b/drivers/mxc/security/sahara2/fsl_shw_auth.c
new file mode 100644
index 000000000000..d3100f01380a
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_auth.c
@@ -0,0 +1,706 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @file fsl_shw_auth.c
+ *
+ * This file contains the routines which do the combined encrypt+authentication
+ * functions.  For now, only AES-CCM is supported.
+ */
+
+#include "sahara.h"
+#include "adaptor.h"
+#include "sf_util.h"
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_gen_encrypt);
+EXPORT_SYMBOL(fsl_shw_auth_decrypt);
+#endif
+
+
+/*! Size of buffer to repetively sink useless CBC output */
+#define CBC_BUF_LEN 4096
+
+/*!
+ * Compute the size, in bytes, of the encoded auth length
+ *
+ * @param l    The actual associated data length
+ *
+ * @return The encoded length
+ */
+#define COMPUTE_NIST_AUTH_LEN_SIZE(l)                                         \
+({                                                                            \
+    unsigned val;                                                             \
+    uint32_t len = l;                                                         \
+    if (len == 0) {                                                           \
+        val = 0;                                                              \
+    } else if (len < 65280) {                                                 \
+        val = 2;                                                              \
+    } else {                    /* cannot handle >= 2^32 */                   \
+        val = 6;                                                              \
+    }                                                                         \
+    val;                                                                      \
+})
+
+/*!
+ * Store the encoded Auth Length into the Auth Data
+ *
+ * @param l    The actual Auth Length
+ * @param p    Location to store encoding (must be uint8_t*)
+ *
+ * @return void
+ */
+#define STORE_NIST_AUTH_LEN(l, p)                                             \
+{                                                                             \
+    register uint32_t L = l;                                                  \
+    if ((uint32_t)(l) < 65280) {                                              \
+        (p)[1] = L & 0xff;                                                    \
+        L >>= 8;                                                              \
+        (p)[0] = L & 0xff;                                                    \
+    } else {                    /* cannot handle >= 2^32 */                   \
+        int i;                                                                \
+        for (i = 5; i > 1; i--) {                                             \
+            (p)[i] = L & 0xff;                                                \
+            L >>= 8;                                                          \
+        }                                                                     \
+        (p)[1] = 0xfe;  /* Markers */                                         \
+        (p)[0] = 0xff;                                                        \
+    }                                                                         \
+}
+
+#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN)          \
+    || defined (USE_S2_CCM_ENCRYPT_CHAIN)
+/*! Buffer to repetively sink useless CBC output */
+static uint8_t cbc_buffer[CBC_BUF_LEN];
+#endif
+
+/*!
+ * Place to store useless output (while bumping CTR0 to CTR1, for instance.
+ * Must be maximum Symmetric block size
+ */
+static uint8_t garbage_output[16];
+
+/*!
+ * Block of zeroes which is maximum Symmetric block size, used for
+ * initializing context register, etc.
+ */
+static uint8_t block_zeros[16] = {
+	0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*!
+ * Append a descriptor chain which will compute CBC over the
+ * formatted associated data blocks.
+ *
+ * @param[in,out] link1       Where to append the new link
+ * @param[in,out] data_len    Location of current/updated auth-only data length
+ * @param         user_ctx    Info for acquiring memory
+ * @param         auth_ctx    Location of block0 value
+ * @param         auth_data   Unformatted associated data
+ * @param         auth_data_length Length in octets of @a auth_data
+ * @param[in,out] temp_buf    Location of in-process data.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static inline fsl_shw_return_t process_assoc_from_nist_params(sah_Link ** link1,
+							      uint32_t *
+							      data_len,
+							      fsl_shw_uco_t *
+							      user_ctx,
+							      fsl_shw_acco_t *
+							      auth_ctx,
+							      const uint8_t *
+							      auth_data,
+							      uint32_t
+							      auth_data_length,
+							      uint8_t **
+							      temp_buf)
+{
+	fsl_shw_return_t status;
+	uint32_t auth_size_length =
+	    COMPUTE_NIST_AUTH_LEN_SIZE(auth_data_length);
+	uint32_t auth_pad_length =
+	    auth_ctx->auth_info.CCM_ctx_info.block_size_bytes -
+	    (auth_data_length +
+	     auth_size_length) %
+	    auth_ctx->auth_info.CCM_ctx_info.block_size_bytes;
+
+	if (auth_pad_length ==
+	    auth_ctx->auth_info.CCM_ctx_info.block_size_bytes) {
+		auth_pad_length = 0;
+	}
+
+	/* Put in Block0 */
+	status = sah_Create_Link(user_ctx->mem_util, link1,
+				 auth_ctx->auth_info.CCM_ctx_info.context,
+				 auth_ctx->auth_info.CCM_ctx_info.
+				 block_size_bytes, SAH_USES_LINK_DATA);
+
+	if (auth_data_length != 0) {
+		if (status == FSL_RETURN_OK_S) {
+			/* Add on length preamble to auth data */
+			STORE_NIST_AUTH_LEN(auth_data_length, *temp_buf);
+			status = sah_Append_Link(user_ctx->mem_util, *link1,
+						 *temp_buf, auth_size_length,
+						 SAH_OWNS_LINK_DATA);
+			*temp_buf += auth_size_length;	/* 2, 6, or 10 bytes */
+		}
+
+		if (status == FSL_RETURN_OK_S) {
+			/* Add in auth data */
+			status = sah_Append_Link(user_ctx->mem_util, *link1,
+						 (uint8_t *) auth_data,
+						 auth_data_length,
+						 SAH_USES_LINK_DATA);
+		}
+
+		if ((status == FSL_RETURN_OK_S) && (auth_pad_length > 0)) {
+			status = sah_Append_Link(user_ctx->mem_util, *link1,
+						 block_zeros, auth_pad_length,
+						 SAH_USES_LINK_DATA);
+		}
+	}
+	/* ... if auth_data_length != 0 */
+	*data_len = auth_ctx->auth_info.CCM_ctx_info.block_size_bytes +
+	    auth_data_length + auth_size_length + auth_pad_length;
+
+	return status;
+}				/* end fn process_assoc_from_nist_params */
+
+/*!
+ * Add a Descriptor which will process with CBC the NIST preamble data
+ *
+ * @param     desc_chain   Current chain
+ * @param     user_ctx     User's context
+ * @param     auth_ctx     Inf
+ * @pararm    encrypt      0 => decrypt, non-zero => encrypt
+ * @param     auth_data    Additional auth data for this call
+ * @param     auth_data_length   Length in bytes of @a auth_data
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static inline fsl_shw_return_t add_assoc_preamble(sah_Head_Desc ** desc_chain,
+						  fsl_shw_uco_t * user_ctx,
+						  fsl_shw_acco_t * auth_ctx,
+						  int encrypt,
+						  const uint8_t * auth_data,
+						  uint32_t auth_data_length)
+{
+	uint8_t *temp_buf;
+	sah_Link *link1 = NULL;
+	sah_Link *link2 = NULL;
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+	uint32_t cbc_data_length = 0;
+	/* Assume AES */
+	uint32_t header = SAH_HDR_SKHA_ENC_DEC;
+	uint32_t temp_buf_flag;
+	unsigned chain_s2 = 1;
+
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN)
+	if (!encrypt) {
+		chain_s2 = 0;
+	}
+#endif
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN)
+	if (encrypt) {
+		chain_s2 = 0;
+	}
+#endif
+	/* Grab a block big enough for multiple uses so that only one allocate
+	 * request needs to be made.
+	 */
+	temp_buf =
+	    user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref,
+					  3 *
+					  auth_ctx->auth_info.CCM_ctx_info.
+					  block_size_bytes);
+
+	if (temp_buf == NULL) {
+		status = FSL_RETURN_NO_RESOURCE_S;
+		goto out;
+	}
+
+	if (auth_ctx->flags & FSL_ACCO_NIST_CCM) {
+		status = process_assoc_from_nist_params(&link1,
+							&cbc_data_length,
+							user_ctx,
+							auth_ctx,
+							auth_data,
+							auth_data_length,
+							&temp_buf);
+		if (status != FSL_RETURN_OK_S) {
+			goto out;
+		}
+		/* temp_buf has been referenced (and incremented).  Only 'own' it
+		 * once, at its first value.  Since the nist routine called above
+		 * bumps it...
+		 */
+		temp_buf_flag = SAH_USES_LINK_DATA;
+	} else {		/* if NIST */
+		status = sah_Create_Link(user_ctx->mem_util, &link1,
+					 (uint8_t *) auth_data,
+					 auth_data_length, SAH_USES_LINK_DATA);
+		if (status != FSL_RETURN_OK_S) {
+			goto out;
+		}
+		/* for next/first use of temp_buf */
+		temp_buf_flag = SAH_OWNS_LINK_DATA;
+		cbc_data_length = auth_data_length;
+	}			/* else not NIST */
+
+#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_ENCRYPT_CHAIN)   \
+    || defined (USE_S2_CCM_DECRYPT_CHAIN)
+
+	if (!chain_s2) {
+		header = SAH_HDR_SKHA_CBC_ICV
+		    ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0
+		    ^ sah_insert_skha_encrypt;
+	} else {
+		/*
+		 * Auth data links have been created.  Now create link for the
+		 * useless output of the CBC calculation.
+		 */
+		status = sah_Create_Link(user_ctx->mem_util, &link2,
+					 temp_buf,
+					 auth_ctx->auth_info.CCM_ctx_info.
+					 block_size_bytes,
+					 temp_buf_flag | SAH_OUTPUT_LINK);
+		if (status != FSL_RETURN_OK_S) {
+			goto out;
+		}
+
+		temp_buf += auth_ctx->auth_info.CCM_ctx_info.block_size_bytes;
+
+		cbc_data_length -=
+		    auth_ctx->auth_info.CCM_ctx_info.block_size_bytes;
+		if (cbc_data_length != 0) {
+			while ((status == FSL_RETURN_OK_S)
+			       && (cbc_data_length != 0)) {
+				uint32_t linklen =
+				    (cbc_data_length >
+				     CBC_BUF_LEN) ? CBC_BUF_LEN :
+				    cbc_data_length;
+
+				status =
+				    sah_Append_Link(user_ctx->mem_util, link2,
+						    cbc_buffer, linklen,
+						    SAH_USES_LINK_DATA |
+						    SAH_OUTPUT_LINK);
+				if (status != FSL_RETURN_OK_S) {
+					goto out;
+				}
+				cbc_data_length -= linklen;
+			}
+		}
+	}
+#else
+	header = SAH_HDR_SKHA_CBC_ICV
+	    ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0
+	    ^ sah_insert_skha_encrypt;
+#endif
+	/* Crank through auth data */
+	status = sah_Append_Desc(user_ctx->mem_util, desc_chain,
+				 header, link1, link2);
+
+      out:
+	if (status != FSL_RETURN_OK_S) {
+		if (link1 != NULL) {
+			sah_Destroy_Link(user_ctx->mem_util, link1);
+		}
+		if (link2 != NULL) {
+			sah_Destroy_Link(user_ctx->mem_util, link2);
+		}
+	}
+
+	(void)encrypt;
+	return status;
+}				/* add_assoc_preamble() */
+
+#if SUPPORT_SSL
+/*!
+ * Generate an SSL value
+ *
+ * @param         user_ctx         Info for acquiring memory
+ * @param         auth_ctx         Info for CTR0, size of MAC
+ * @param         cipher_key_info
+ * @param         auth_key_info
+ * @param         auth_data_length
+ * @param         auth_data
+ * @param         payload_length
+ * @param         payload
+ * @param         ct
+ * @param         auth_value
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t do_ssl_gen(fsl_shw_uco_t * user_ctx,
+				   fsl_shw_acco_t * auth_ctx,
+				   fsl_shw_sko_t * cipher_key_info,
+				   fsl_shw_sko_t * auth_key_info,
+				   uint32_t auth_data_length,
+				   const uint8_t * auth_data,
+				   uint32_t payload_length,
+				   const uint8_t * payload,
+				   uint8_t * ct, uint8_t * auth_value)
+{
+	SAH_SF_DCLS;
+	uint8_t *ptr1 = NULL;
+
+	/* Assume one-shot init-finalize... no precomputes */
+	header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^
+	    sah_insert_mdha_algorithm[auth_ctx->auth_info.hash_ctx_info.
+				      algorithm] ^ sah_insert_mdha_init ^
+	    sah_insert_mdha_ssl ^ sah_insert_mdha_pdata ^
+	    sah_insert_mdha_mac_full;
+
+	/* set up hmac */
+	DESC_IN_KEY(header, 0, NULL, auth_key_info);
+
+	/* This is wrong -- need to find 16 extra bytes of data from
+	 * somewhere */
+	DESC_IN_OUT(SAH_HDR_MDHA_HASH, payload_length, payload, 1, auth_value);
+
+	/* set up encrypt */
+	header = SAH_HDR_SKHA_SET_MODE_IV_KEY
+	    ^ sah_insert_skha_mode[auth_ctx->cipher_ctx_info.mode]
+	    ^ sah_insert_skha_encrypt
+	    ^ sah_insert_skha_algorithm[cipher_key_info->algorithm];
+
+	/* Honor 'no key parity checking' for DES and TDES */
+	if ((cipher_key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) &&
+	    ((cipher_key_info->algorithm == FSL_KEY_ALG_DES) ||
+	     (cipher_key_info->algorithm == FSL_KEY_ALG_TDES))) {
+		header ^= sah_insert_skha_no_key_parity;
+	}
+
+	if (auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_CTR) {
+		header ^=
+		    sah_insert_skha_modulus[auth_ctx->cipher_ctx_info.
+					    modulus_exp];
+	}
+
+	if ((auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_ECB)
+	    || (auth_ctx->cipher_ctx_info.flags & FSL_SYM_CTX_INIT)) {
+		ptr1 = block_zeros;
+	} else {
+		ptr1 = auth_ctx->cipher_ctx_info.context;
+	}
+
+	DESC_IN_KEY(header, auth_ctx->cipher_ctx_info.block_size_bytes, ptr1,
+		    cipher_key_info);
+
+	/* This is wrong -- need to find 16 extra bytes of data from
+	 * somewhere...
+	 */
+	if (payload_length != 0) {
+		DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC,
+			    payload_length, payload, payload_length, ct);
+	}
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	/* Eliminate compiler warnings until full implementation... */
+	(void)auth_data;
+	(void)auth_data_length;
+
+	return ret;
+}				/* do_ssl_gen() */
+#endif
+
+/*!
+ * @brief Generate a (CCM) auth code and encrypt the payload.
+ *
+ * This is a very complicated function.  Seven (or eight) descriptors are
+ * required to perform a CCM calculation.
+ *
+ * First:  Load CTR0 and key.
+ *
+ * Second: Run an octet of data through to bump to CTR1.  (This could be
+ * done in software, but software will have to bump and later decrement -
+ * or copy and bump.
+ *
+ * Third: (in Virtio) Load a descriptor with data of zeros for CBC IV.
+ *
+ * Fourth: Run any (optional) "additional data" through the CBC-mode
+ * portion of the algorithm.
+ *
+ * Fifth: Run the payload through in CCM mode.
+ *
+ * Sixth: Extract the unencrypted MAC.
+ *
+ * Seventh: Load CTR0.
+ *
+ * Eighth: Encrypt the MAC.
+ *
+ * @param user_ctx         The user's context
+ * @param auth_ctx         Info on this Auth operation
+ * @param cipher_key_info  Key to encrypt payload
+ * @param auth_key_info    (unused - same key in CCM)
+ * @param auth_data_length Length in bytes of @a auth_data
+ * @param auth_data        Any auth-only data
+ * @param payload_length   Length in bytes of @a payload
+ * @param payload          The data to encrypt
+ * @param[out] ct          The location to store encrypted data
+ * @param[out] auth_value  The location to store authentication code
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_acco_t * auth_ctx,
+				     fsl_shw_sko_t * cipher_key_info,
+				     fsl_shw_sko_t * auth_key_info,
+				     uint32_t auth_data_length,
+				     const uint8_t * auth_data,
+				     uint32_t payload_length,
+				     const uint8_t * payload,
+				     uint8_t * ct, uint8_t * auth_value)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	if (auth_ctx->mode == FSL_ACC_MODE_SSL) {
+#if SUPPORT_SSL
+		ret = do_ssl_gen(user_ctx, auth_ctx, cipher_key_info,
+				 auth_key_info, auth_data_length, auth_data,
+				 payload_length, payload, ct, auth_value);
+#else
+		ret = FSL_RETURN_BAD_MODE_S;
+#endif
+		goto out;
+	}
+
+	if (auth_ctx->mode != FSL_ACC_MODE_CCM) {
+		ret = FSL_RETURN_BAD_MODE_S;
+		goto out;
+	}
+
+	/* Only support INIT and FINALIZE flags right now. */
+	if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD |
+				FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE))
+	    != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* Load CTR0 and Key */
+	header = (SAH_HDR_SKHA_SET_MODE_IV_KEY
+		  ^ sah_insert_skha_mode_ctr
+		  ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt);
+	DESC_IN_KEY(header,
+		    auth_ctx->cipher_ctx_info.block_size_bytes,
+		    auth_ctx->cipher_ctx_info.context, cipher_key_info);
+
+	/* Encrypt dummy data to bump to CTR1 */
+	header = SAH_HDR_SKHA_ENC_DEC;
+	DESC_IN_OUT(header, auth_ctx->mac_length, garbage_output,
+		    auth_ctx->mac_length, garbage_output);
+
+#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_ENCRYPT_CHAIN)
+#ifndef NO_ZERO_IV_LOAD
+	header = (SAH_HDR_SKHA_SET_MODE_IV_KEY
+		  ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc);
+	DESC_IN_IN(header,
+		   auth_ctx->auth_info.CCM_ctx_info.block_size_bytes,
+		   block_zeros, 0, NULL);
+#endif
+#endif
+
+	ret = add_assoc_preamble(&desc_chain, user_ctx,
+				 auth_ctx, 1, auth_data, auth_data_length);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Process the payload */
+	header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC
+		  ^ sah_insert_skha_mode_ccm
+		  ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt);
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN)
+	header ^= sah_insert_skha_aux0;
+#endif
+	if (payload_length != 0) {
+		DESC_IN_OUT(header, payload_length, payload, payload_length,
+			    ct);
+	} else {
+		DESC_IN_OUT(header, 0, NULL, 0, NULL);
+	}			/* if payload_length */
+
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN)
+	/* Pull out the CBC-MAC value. */
+	DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL,
+		     auth_ctx->mac_length, auth_value);
+#else
+	/* Pull out the unencrypted CBC-MAC value. */
+	DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV,
+		     0, NULL, auth_ctx->mac_length, auth_ctx->unencrypted_mac);
+
+	/* Now load CTR0 in, and encrypt the MAC */
+	header = SAH_HDR_SKHA_SET_MODE_IV_KEY
+	    ^ sah_insert_skha_encrypt
+	    ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128;
+	DESC_IN_IN(header,
+		   auth_ctx->cipher_ctx_info.block_size_bytes,
+		   auth_ctx->cipher_ctx_info.context, 0, NULL);
+
+	header = SAH_HDR_SKHA_ENC_DEC;	/* Desc. #4 SKHA Enc/Dec */
+	DESC_IN_OUT(header,
+		    auth_ctx->mac_length, auth_ctx->unencrypted_mac,
+		    auth_ctx->mac_length, auth_value);
+#endif
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	(void)auth_key_info;
+	return ret;
+}				/* fsl_shw_gen_encrypt() */
+
+/*!
+ * @brief Authenticate and decrypt a (CCM) stream.
+ *
+ * @param user_ctx         The user's context
+ * @param auth_ctx         Info on this Auth operation
+ * @param cipher_key_info  Key to encrypt payload
+ * @param auth_key_info    (unused - same key in CCM)
+ * @param auth_data_length Length in bytes of @a auth_data
+ * @param auth_data        Any auth-only data
+ * @param payload_length   Length in bytes of @a payload
+ * @param ct               The encrypted data
+ * @param auth_value       The authentication code to validate
+ * @param[out] payload     The location to store decrypted data
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx,
+				      fsl_shw_acco_t * auth_ctx,
+				      fsl_shw_sko_t * cipher_key_info,
+				      fsl_shw_sko_t * auth_key_info,
+				      uint32_t auth_data_length,
+				      const uint8_t * auth_data,
+				      uint32_t payload_length,
+				      const uint8_t * ct,
+				      const uint8_t * auth_value,
+				      uint8_t * payload)
+{
+	SAH_SF_DCLS;
+#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN)
+	uint8_t *calced_auth = NULL;
+	unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE;
+#endif
+
+	SAH_SF_USER_CHECK();
+
+	/* Only support CCM */
+	if (auth_ctx->mode != FSL_ACC_MODE_CCM) {
+		ret = FSL_RETURN_BAD_MODE_S;
+		goto out;
+	}
+	/* Only support INIT and FINALIZE flags right now. */
+	if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD |
+				FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE))
+	    != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* Load CTR0 and Key */
+	header = SAH_HDR_SKHA_SET_MODE_IV_KEY
+	    ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128;
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN)
+	header ^= sah_insert_skha_aux0;
+#endif
+	DESC_IN_KEY(header,
+		    auth_ctx->cipher_ctx_info.block_size_bytes,
+		    auth_ctx->cipher_ctx_info.context, cipher_key_info);
+
+	/* Decrypt the MAC which the user passed in */
+	header = SAH_HDR_SKHA_ENC_DEC;
+	DESC_IN_OUT(header,
+		    auth_ctx->mac_length, auth_value,
+		    auth_ctx->mac_length, auth_ctx->unencrypted_mac);
+
+#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN)
+#ifndef NO_ZERO_IV_LOAD
+	header = (SAH_HDR_SKHA_SET_MODE_IV_KEY
+		  ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc);
+	DESC_IN_IN(header,
+		   auth_ctx->auth_info.CCM_ctx_info.block_size_bytes,
+		   block_zeros, 0, NULL);
+#endif
+#endif
+
+	ret = add_assoc_preamble(&desc_chain, user_ctx,
+				 auth_ctx, 0, auth_data, auth_data_length);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Process the payload */
+	header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC
+		  ^ sah_insert_skha_mode_ccm ^ sah_insert_skha_modulus_128);
+#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN)
+	header ^= sah_insert_skha_aux0;
+#endif
+	if (payload_length != 0) {
+		DESC_IN_OUT(header, payload_length, ct, payload_length,
+			    payload);
+	} else {
+		DESC_IN_OUT(header, 0, NULL, 0, NULL);
+	}
+
+#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN)
+	/* Now pull CBC context (unencrypted MAC) out for comparison. */
+	/* Need to allocate a place for it, to handle non-blocking mode
+	 * when this stack frame will disappear!
+	 */
+	calced_auth = DESC_TEMP_ALLOC(auth_ctx->mac_length);
+	header = SAH_HDR_SKHA_READ_CONTEXT_IV;
+	DESC_OUT_OUT(header, 0, NULL, auth_ctx->mac_length, calced_auth);
+	if (!blocking) {
+		/* get_results will need this for comparison */
+		desc_chain->out1_ptr = calced_auth;
+		desc_chain->out2_ptr = auth_ctx->unencrypted_mac;
+		desc_chain->out_len = auth_ctx->mac_length;
+	}
+#endif
+
+	SAH_SF_EXECUTE();
+
+#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN)
+	if (blocking && (ret == FSL_RETURN_OK_S)) {
+		unsigned i;
+		/* Validate the auth code */
+		for (i = 0; i < auth_ctx->mac_length; i++) {
+			if (calced_auth[i] != auth_ctx->unencrypted_mac[i]) {
+				ret = FSL_RETURN_AUTH_FAILED_S;
+				break;
+			}
+		}
+	}
+#endif
+
+      out:
+	SAH_SF_DESC_CLEAN();
+#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN)
+	DESC_TEMP_FREE(calced_auth);
+#endif
+
+	(void)auth_key_info;
+	return ret;
+}				/* fsl_shw_gen_decrypt() */
diff --git a/drivers/mxc/security/sahara2/fsl_shw_hash.c b/drivers/mxc/security/sahara2/fsl_shw_hash.c
new file mode 100644
index 000000000000..1551173c1c62
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_hash.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_hash.c
+ *
+ * This file implements Cryptographic Hashing functions of the FSL SHW API
+ * for Sahara.  This does not include HMAC.
+ */
+
+#include "sahara.h"
+#include "sf_util.h"
+
+#ifdef LINUX_KERNEL
+EXPORT_SYMBOL(fsl_shw_hash);
+#endif
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */
+/*!
+ * Hash a stream of data with a cryptographic hash algorithm.
+ *
+ * The flags in the @a hash_ctx control the operation of this function.
+ *
+ * Hashing functions work on 64 octets of message at a time.  Therefore, when
+ * any partial hashing of a long message is performed, the message @a length of
+ * each segment must be a multiple of 64.  When ready to
+ * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value.
+ *
+ * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a
+ * one-shot complete hash, including padding, will be performed.  The @a length
+ * may be any value.
+ *
+ * The first octets of a data stream can be hashed by setting the
+ * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags.  The @a length must be
+ * a multiple of 64.
+ *
+ * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by
+ * #FSL_HASH_FLAGS_SAVE.  The two in combination will allow a (multiple-of-64
+ * octets) 'middle sequence' of the data stream to be hashed with the
+ * beginning.  The @a length must again be a multiple of 64.
+ *
+ * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously
+ * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and
+ * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the
+ * stream.  The @a length may be any value.
+ *
+ * If the user program wants to do the padding for the hash, it can leave off
+ * the #FSL_HASH_FLAGS_FINALIZE flag.  The @a length must then be a multiple of
+ * 64 octets.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param[in,out] hash_ctx Hashing algorithm and state of the cipher.
+ * @param      msg       Pointer to the data to be hashed.
+ * @param      length    Length, in octets, of the @a msg.
+ * @param[out] result    If not null, pointer to where to store the hash
+ *                       digest.
+ * @param      result_len Number of octets to store in @a result.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_hco_t * hash_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	SAH_SF_DCLS;
+	unsigned ctx_flags = (hash_ctx->flags & (FSL_HASH_FLAGS_INIT
+						 | FSL_HASH_FLAGS_LOAD
+						 | FSL_HASH_FLAGS_SAVE
+						 | FSL_HASH_FLAGS_FINALIZE));
+
+	SAH_SF_USER_CHECK();
+
+	/* Reset expectations if user gets overly zealous. */
+	if (result_len > hash_ctx->digest_length) {
+		result_len = hash_ctx->digest_length;
+	}
+
+	/* Validate hash ctx flags.
+	 * Need INIT or LOAD but not both.
+	 * Need SAVE or digest ptr (both is ok).
+	 */
+	if (((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD))
+	     == (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD))
+	    || ((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) == 0)
+	    || (!(ctx_flags & FSL_HASH_FLAGS_SAVE) && (result == NULL))) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	if (ctx_flags & FSL_HASH_FLAGS_INIT) {
+		sah_Oct_Str out_ptr;
+		unsigned out_len;
+
+		/* Create desc to perform the initial hashing operation */
+		/* Desc. #8 w/INIT and algorithm */
+		header = SAH_HDR_MDHA_SET_MODE_HASH
+		    ^ sah_insert_mdha_init
+		    ^ sah_insert_mdha_algorithm[hash_ctx->algorithm];
+
+		/* If user wants one-shot, set padding operation. */
+		if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) {
+			header ^= sah_insert_mdha_pdata;
+		}
+
+		/* Determine where Digest will go - hash_ctx or result */
+		if (ctx_flags & FSL_HASH_FLAGS_SAVE) {
+			out_ptr = (sah_Oct_Str) hash_ctx->context;
+			out_len = hash_ctx->context_register_length;
+		} else {
+			out_ptr = result;
+			out_len = (result_len > hash_ctx->digest_length)
+			    ? hash_ctx->digest_length : result_len;
+		}
+
+		DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len,
+			    out_ptr);
+	} else {		/* not doing hash INIT */
+		void *out_ptr;
+		unsigned out_len;
+
+		/*
+		 * Build two descriptors -- one to load in context/set mode, the
+		 * other to compute & retrieve hash/context value.
+		 *
+		 * First up - Desc. #6 to load context.
+		 */
+		/* Desc. #8 w/algorithm */
+		header = SAH_HDR_MDHA_SET_MODE_MD_KEY
+		    ^ sah_insert_mdha_algorithm[hash_ctx->algorithm];
+
+		if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) {
+			header ^= sah_insert_mdha_pdata;
+		}
+
+		/* Message Digest (in) */
+		DESC_IN_IN(header,
+			   hash_ctx->context_register_length,
+			   (sah_Oct_Str) hash_ctx->context, 0, NULL);
+
+		if (ctx_flags & FSL_HASH_FLAGS_SAVE) {
+			out_ptr = hash_ctx->context;
+			out_len = hash_ctx->context_register_length;
+		} else {
+			out_ptr = result;
+			out_len = result_len;
+		}
+
+		/* Second -- run data through and retrieve ctx regs */
+		/* Desc. #10 - no mode register with this. */
+		header = SAH_HDR_MDHA_HASH;
+		DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len,
+			    out_ptr);
+	}			/* else not INIT */
+
+	/* Now that execution is rejoined, we can append another descriptor
+	   to extract the digest/context a second time, into the result. */
+	if ((ctx_flags & FSL_HASH_FLAGS_SAVE)
+	    && (result != NULL) && (result_len != 0)) {
+
+		header = SAH_HDR_MDHA_STORE_DIGEST;
+
+		/* Message Digest (out) */
+		DESC_IN_OUT(header, 0, NULL,
+			    (result_len > hash_ctx->digest_length)
+			    ? hash_ctx->digest_length : result_len, result);
+	}
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}				/* fsl_shw_hash() */
diff --git a/drivers/mxc/security/sahara2/fsl_shw_hmac.c b/drivers/mxc/security/sahara2/fsl_shw_hmac.c
new file mode 100644
index 000000000000..4184d9b280dd
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_hmac.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_hmac.c
+ *
+ * This file implements Hashed Message Authentication Code functions of the FSL
+ * SHW API for Sahara.
+ */
+
+#include "sahara.h"
+#include "sf_util.h"
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_hmac_precompute);
+EXPORT_SYMBOL(fsl_shw_hmac);
+#endif
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */
+/*!
+ * Get the precompute information
+ *
+ *
+ * @param   user_ctx
+ * @param   key_info
+ * @param   hmac_ctx
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx,
+					 fsl_shw_sko_t * key_info,
+					 fsl_shw_hmco_t * hmac_ctx)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	if ((key_info->algorithm != FSL_KEY_ALG_HMAC) ||
+	    (key_info->key_length > 64)) {
+		return FSL_RETURN_BAD_ALGORITHM_S;
+	} else if (key_info->key_length == 0) {
+		return FSL_RETURN_BAD_KEY_LENGTH_S;
+	}
+
+	/* Set up to start the Inner Calculation */
+	/* Desc. #8 w/IPAD, & INIT */
+	header = SAH_HDR_MDHA_SET_MODE_HASH
+	    ^ sah_insert_mdha_ipad
+	    ^ sah_insert_mdha_init
+	    ^ sah_insert_mdha_algorithm[hmac_ctx->algorithm];
+
+	DESC_KEY_OUT(header, key_info,
+		     hmac_ctx->context_register_length,
+		     (uint8_t *) hmac_ctx->inner_precompute);
+
+	/* Set up for starting Outer calculation */
+	/* exchange IPAD bit for OPAD bit */
+	header ^= (sah_insert_mdha_ipad ^ sah_insert_mdha_opad);
+
+	/* Theoretically, we can leave this link out and use the key which is
+	 * already in the register... however, if we do, the resulting opad
+	 * hash does not have the correct value when using the model. */
+	DESC_KEY_OUT(header, key_info,
+		     hmac_ctx->context_register_length,
+		     (uint8_t *) hmac_ctx->outer_precompute);
+
+	SAH_SF_EXECUTE();
+	if (ret == FSL_RETURN_OK_S) {
+		/* flag that precomputes have been entered in this hco
+		 * assume it'll first be used for initilizing */
+		hmac_ctx->flags |= (FSL_HMAC_FLAGS_INIT |
+				    FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT);
+	}
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */
+/*!
+ * Get the hmac
+ *
+ *
+ * @param         user_ctx    Info for acquiring memory
+ * @param         key_info
+ * @param         hmac_ctx
+ * @param         msg
+ * @param         length
+ * @param         result
+ * @param         result_len
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_sko_t * key_info,
+			      fsl_shw_hmco_t * hmac_ctx,
+			      const uint8_t * msg,
+			      uint32_t length,
+			      uint8_t * result, uint32_t result_len)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	/* check flag consistency */
+	/* Note that Final, Init, and Save are an illegal combination when a key
+	 * is being used. Because of the logic flow of this routine, that is
+	 * taken care of without being explict */
+	if (
+		   /* nothing to work on */
+		   (((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) == 0) &&
+		    ((hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD) == 0)) ||
+		   /* can't do both */
+		   ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) &&
+		    (hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD)) ||
+		   /* must be some output */
+		   (((hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) == 0) &&
+		    ((hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) == 0))) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* build descriptor #6 */
+
+	/* start building descriptor header */
+	header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^
+	    sah_insert_mdha_algorithm[hmac_ctx->algorithm] ^
+	    sah_insert_mdha_init;
+
+	/* if this is to finalize the digest, mark to pad last block */
+	if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) {
+		header ^= sah_insert_mdha_pdata;
+	}
+
+	/* Check if this is a one shot */
+	if ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) &&
+	    (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE)) {
+
+		header ^= sah_insert_mdha_hmac;
+
+		/* See if this uses Precomputes */
+		if (hmac_ctx->flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT) {
+			DESC_IN_IN(header,
+				   hmac_ctx->context_register_length,
+				   (uint8_t *) hmac_ctx->inner_precompute,
+				   hmac_ctx->context_length,
+				   (uint8_t *) hmac_ctx->outer_precompute);
+		} else {	/* Precomputes not requested, try using Key */
+			if (key_info->key != NULL) {
+				/* first, validate the key fields and related flag */
+				if ((key_info->key_length == 0)
+				    || (key_info->key_length > 64)) {
+					ret = FSL_RETURN_BAD_KEY_LENGTH_S;
+					goto out;
+				} else {
+					if (key_info->algorithm !=
+					    FSL_KEY_ALG_HMAC) {
+						ret =
+						    FSL_RETURN_BAD_ALGORITHM_S;
+						goto out;
+					}
+				}
+
+				/* finish building descriptor header (Key specific) */
+				header ^= sah_insert_mdha_mac_full;
+				DESC_IN_KEY(header, 0, NULL, key_info);
+			} else {	/* not using Key or Precomputes, so die */
+				ret = FSL_RETURN_BAD_FLAG_S;
+				goto out;
+			}
+		}
+	} else {		/* it's not a one shot, must be multi-step */
+		/* this the last chunk? */
+		if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) {
+			header ^= sah_insert_mdha_hmac;
+			DESC_IN_IN(header,
+				   hmac_ctx->context_register_length,
+				   (uint8_t *) hmac_ctx->ongoing_context,
+				   hmac_ctx->context_length,
+				   (uint8_t *) hmac_ctx->outer_precompute);
+		} else {	/* not last chunk */
+			uint8_t *ptr1;
+
+			if (hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) {
+				/* must be using precomputes, cannot 'chunk' message
+				 * starting with a key */
+				if (hmac_ctx->
+				    flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT)
+				{
+					ptr1 =
+					    (uint8_t *) hmac_ctx->
+					    inner_precompute;
+				} else {
+					ret = FSL_RETURN_NO_RESOURCE_S;
+					goto out;
+				}
+			} else {
+				ptr1 = (uint8_t *) hmac_ctx->ongoing_context;
+			}
+
+			if (ret != FSL_RETURN_OK_S) {
+				goto out;
+			}
+			DESC_IN_IN(header,
+				   hmac_ctx->context_register_length, ptr1,
+				   0, NULL);
+		}
+	}			/* multi-step */
+
+	/* build descriptor #10 & maybe 11 */
+	header = SAH_HDR_MDHA_HASH;
+
+	if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) {
+		/* check that the results parameters seem reasonable */
+		if ((result_len != 0) && (result != NULL)) {
+			if (result_len > hmac_ctx->context_register_length) {
+				result_len = hmac_ctx->context_register_length;
+			}
+
+			/* message in / digest out (descriptor #10) */
+			DESC_IN_OUT(header, length, msg, result_len, result);
+
+			/* see if descriptor #11 needs to be built */
+			if (hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) {
+				header = SAH_HDR_MDHA_STORE_DIGEST;
+				/* nothing in / context out */
+				DESC_IN_IN(header, 0, NULL,
+					   hmac_ctx->context_register_length,
+					   (uint8_t *) hmac_ctx->
+					   ongoing_context);
+			}
+		} else {
+			/* something wrong with result or its length */
+			ret = FSL_RETURN_BAD_DATA_LENGTH_S;
+		}
+	} else {		/* finalize not set, so store in ongoing context field */
+		if ((length % 64) == 0) {	/* this will change for 384/512 support */
+			/* message in / context out */
+			DESC_IN_OUT(header, length, msg,
+				    hmac_ctx->context_register_length,
+				    (uint8_t *) hmac_ctx->ongoing_context);
+		} else {
+			/* not final data, and not multiple of block length */
+			ret = FSL_RETURN_BAD_DATA_LENGTH_S;
+		}
+	}
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}				/* fsl_shw_hmac() */
diff --git a/drivers/mxc/security/sahara2/fsl_shw_keystore.c b/drivers/mxc/security/sahara2/fsl_shw_keystore.c
new file mode 100644
index 000000000000..5585b5b252a0
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_keystore.c
@@ -0,0 +1,837 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+ * @file fsl_shw_keystore.c
+ *
+ * File which implements a default keystore policy, for use as the system
+ * keystore.
+ */
+#include "fsl_platform.h"
+#include "fsl_shw.h"
+#include "fsl_shw_keystore.h"
+
+#if defined(DIAG_DRV_IF)
+#include <diagnostic.h>
+#endif
+
+#if !defined(FSL_HAVE_SCC2) && defined(__KERNEL__)
+#include <linux/mxc_scc_driver.h>
+#endif
+
+/* Define a semaphore to protect the keystore data */
+#ifdef __KERNEL__
+#define LOCK_INCLUDES os_lock_context_t context
+#define ACQUIRE_LOCK os_lock_save_context(keystore->lock, context)
+#define RELEASE_LOCK os_unlock_restore_context(keystore->lock, context);
+#else
+#define LOCK_INCLUDES
+#define ACQUIRE_LOCK
+#define RELEASE_LOCK
+#endif	/* __KERNEL__ */
+
+/*!
+ * Calculates the byte offset into a word
+ *  @param   bp  The byte (char*) pointer
+ *  @return      The offset (0, 1, 2, or 3)
+ */
+#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t))
+
+/*!
+ * Converts (by rounding down) a byte pointer into a word pointer
+ *  @param  bp  The byte (char*) pointer
+ *  @return     The word (uint32_t) as though it were an aligned (uint32_t*)
+ */
+#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1))
+
+/* Depending on the architecture, these functions should be defined
+ * differently.  On Platforms with SCC2, the functions use the secure
+ * partition interface and should be available in both user and kernel space.
+ * On platforms with SCC, they use the SCC keystore interface.  This is only
+ * available in kernel mode, so they should be stubbed out in user mode.
+ */
+#if defined(FSL_HAVE_SCC2) || (defined(FSL_HAVE_SCC) && defined(__KERNEL__))
+EXPORT_SYMBOL(fsl_shw_init_keystore);
+void fsl_shw_init_keystore(
+			    fsl_shw_kso_t *keystore,
+			    fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx,
+							   void **user_data),
+			    void (*data_cleanup) (fsl_shw_uco_t *user_ctx,
+						   void **user_data),
+			    fsl_shw_return_t(*slot_alloc) (void *user_data,
+							    uint32_t size,
+							    uint64_t owner_id,
+							    uint32_t *slot),
+			    fsl_shw_return_t(*slot_dealloc) (void *user_data,
+							      uint64_t
+							      owner_id,
+							      uint32_t slot),
+			    fsl_shw_return_t(*slot_verify_access) (void
+								    *user_data,
+								    uint64_t
+								    owner_id,
+								    uint32_t
+								    slot),
+			    void *(*slot_get_address) (void *user_data,
+							uint32_t handle),
+			    uint32_t(*slot_get_base) (void *user_data,
+						       uint32_t handle),
+			    uint32_t(*slot_get_offset) (void *user_data,
+							 uint32_t handle),
+			    uint32_t(*slot_get_slot_size) (void *user_data,
+							    uint32_t handle))
+{
+	keystore->data_init = data_init;
+	keystore->data_cleanup = data_cleanup;
+	keystore->slot_alloc = slot_alloc;
+	keystore->slot_dealloc = slot_dealloc;
+	keystore->slot_verify_access = slot_verify_access;
+	keystore->slot_get_address = slot_get_address;
+	keystore->slot_get_base = slot_get_base;
+	keystore->slot_get_offset = slot_get_offset;
+	keystore->slot_get_slot_size = slot_get_slot_size;
+}
+
+EXPORT_SYMBOL(fsl_shw_init_keystore_default);
+void fsl_shw_init_keystore_default(fsl_shw_kso_t *keystore)
+{
+	keystore->data_init = shw_kso_init_data;
+	keystore->data_cleanup = shw_kso_cleanup_data;
+	keystore->slot_alloc = shw_slot_alloc;
+	keystore->slot_dealloc = shw_slot_dealloc;
+	keystore->slot_verify_access = shw_slot_verify_access;
+	keystore->slot_get_address = shw_slot_get_address;
+	keystore->slot_get_base = shw_slot_get_base;
+	keystore->slot_get_offset = shw_slot_get_offset;
+	keystore->slot_get_slot_size = shw_slot_get_slot_size;
+}
+
+/*!
+ * Do any keystore specific initializations
+ */
+EXPORT_SYMBOL(fsl_shw_establish_keystore);
+fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx,
+						fsl_shw_kso_t *keystore)
+{
+	if (keystore->data_init == NULL) {
+		return FSL_RETURN_ERROR_S;
+	}
+
+    /* Call the data_init function for any user setup */
+    return keystore->data_init(user_ctx, &(keystore->user_data));
+}
+
+EXPORT_SYMBOL(fsl_shw_release_keystore);
+void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx,
+				 fsl_shw_kso_t *keystore)
+{
+
+    /* Call the data_cleanup function for any keystore cleanup.
+	  * NOTE: The keystore doesn't have any way of telling which keys are using
+	  * it, so it is up to the user program to manage their key objects
+	  * correctly.
+	  */
+	 if ((keystore != NULL) && (keystore->data_cleanup != NULL)) {
+		keystore->data_cleanup(user_ctx, &(keystore->user_data));
+	}
+	return;
+}
+
+fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size,
+				       uint64_t owner_id, uint32_t *slot)
+{
+	LOCK_INCLUDES;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+
+#ifdef DIAG_DRV_IF
+	    LOG_DIAG("In keystore_slot_alloc.");
+
+#endif
+	ACQUIRE_LOCK;
+	if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) {
+		goto out;
+	}
+
+#ifdef DIAG_DRV_IF
+	    LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot);
+
+#endif
+retval = keystore->slot_alloc(keystore->user_data, size, owner_id, slot);
+out:RELEASE_LOCK;
+	return retval;
+}
+
+fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore,
+					 uint64_t owner_id, uint32_t slot)
+{
+	LOCK_INCLUDES;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	ACQUIRE_LOCK;
+	if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) {
+		goto out;
+	}
+	retval =
+	    keystore->slot_dealloc(keystore->user_data, owner_id, slot);
+out:RELEASE_LOCK;
+	return retval;
+}
+
+fsl_shw_return_t
+keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot,
+		   const uint8_t * key_data, uint32_t key_length)
+{
+
+#ifdef FSL_HAVE_SCC2
+	    LOCK_INCLUDES;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	uint32_t slot_size;
+	uint32_t i;
+	uint8_t * slot_location;
+	ACQUIRE_LOCK;
+	if ((keystore->slot_verify_access == NULL) ||
+	      (keystore->user_data == NULL))
+		goto out;
+	if (keystore->
+	      slot_verify_access(keystore->user_data, owner_id,
+				 slot) !=FSL_RETURN_OK_S) {
+		retval = FSL_RETURN_AUTH_FAILED_S;
+		goto out;
+	}
+	slot_size = keystore->slot_get_slot_size(keystore->user_data, slot);
+	if (key_length > slot_size) {
+		retval = FSL_RETURN_BAD_DATA_LENGTH_S;
+		goto out;
+	}
+	slot_location = keystore->slot_get_address(keystore->user_data, slot);
+	for (i = 0; i < key_length; i++) {
+		slot_location[i] = key_data[i];
+	}
+	retval = FSL_RETURN_OK_S;
+out:RELEASE_LOCK;
+	return retval;
+
+#else	/* FSL_HAVE_SCC2 */
+	fsl_shw_return_t retval;
+	scc_return_t scc_ret;
+	scc_ret =
+	    scc_load_slot(owner_id, slot, (uint8_t *) key_data, key_length);
+	switch (scc_ret) {
+	case SCC_RET_OK:
+		retval = FSL_RETURN_OK_S;
+		break;
+	case SCC_RET_VERIFICATION_FAILED:
+		retval = FSL_RETURN_AUTH_FAILED_S;
+		break;
+	case SCC_RET_INSUFFICIENT_SPACE:
+		retval = FSL_RETURN_BAD_DATA_LENGTH_S;
+		break;
+	default:
+		retval = FSL_RETURN_ERROR_S;
+	}
+	return retval;
+
+#endif	/* FSL_HAVE_SCC2 */
+}
+
+fsl_shw_return_t
+keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot,
+		   uint32_t key_length, uint8_t * key_data)
+{
+#ifdef FSL_HAVE_SCC2
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	uint8_t *slot_addr;
+	uint32_t slot_size;
+
+	slot_addr = keystore->slot_get_address(keystore->user_data, slot);
+	slot_size = keystore->slot_get_slot_size(keystore->user_data, slot);
+
+	if (key_length > slot_size) {
+		retval = FSL_RETURN_BAD_KEY_LENGTH_S;
+		goto out;
+	}
+
+	memcpy(key_data, slot_addr, key_length);
+	retval = FSL_RETURN_OK_S;
+
+      out:
+	return retval;
+
+#else				/* Have SCC2 */
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	scc_return_t scc_ret;
+	printk("keystore SCC \n");
+
+	scc_ret =
+	    scc_read_slot(owner_id, slot, key_length, (uint8_t *) key_data);
+	printk("keystore SCC Ret value: %d \n", scc_ret);
+	switch (scc_ret) {
+	case SCC_RET_OK:
+		retval = FSL_RETURN_OK_S;
+		break;
+	case SCC_RET_VERIFICATION_FAILED:
+		retval = FSL_RETURN_AUTH_FAILED_S;
+		break;
+	case SCC_RET_INSUFFICIENT_SPACE:
+		retval = FSL_RETURN_BAD_DATA_LENGTH_S;
+		break;
+	default:
+		retval = FSL_RETURN_ERROR_S;
+	}
+
+	return retval;
+
+#endif				/* FSL_HAVE_SCC2 */
+}/* end fn keystore_slot_read */
+
+fsl_shw_return_t
+keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore,
+		      uint64_t owner_id, uint32_t slot, uint32_t length,
+		      uint8_t *destination)
+{
+
+#ifdef FSL_HAVE_SCC2
+	LOCK_INCLUDES;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	uint32_t slot_length;
+	uint32_t IV[4];
+	uint32_t * iv_ptr = (uint32_t *) & (owner_id);
+
+	/* Build the IV */
+	IV[0] = iv_ptr[0];
+	IV[1] = iv_ptr[1];
+	IV[2] = 0;
+	IV[3] = 0;
+	ACQUIRE_LOCK;
+
+	/* Ensure that the data will fit in the key slot */
+	slot_length =
+	    keystore->slot_get_slot_size(keystore->user_data, slot);
+	if (length > slot_length) {
+		goto out;
+	}
+
+	  /* Call scc encrypt function to encrypt the data. */
+	    retval = do_scc_encrypt_region(user_ctx,
+					   (void *)keystore->
+					   slot_get_base(keystore->user_data,
+							 slot),
+					   keystore->slot_get_offset(keystore->
+								      user_data,
+								      slot),
+					   length, destination, IV,
+					   FSL_SHW_CYPHER_MODE_CBC);
+	goto out;
+out:RELEASE_LOCK;
+	return retval;
+
+#else
+	scc_return_t retval;
+	retval = scc_encrypt_slot(owner_id, slot, length, destination);
+	if (retval == SCC_RET_OK)
+		return FSL_RETURN_OK_S;
+	return FSL_RETURN_ERROR_S;
+
+#endif	/* FSL_HAVE_SCC2 */
+}
+
+fsl_shw_return_t
+keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore,
+		      uint64_t owner_id, uint32_t slot, uint32_t length,
+		      const uint8_t *source)
+{
+
+#ifdef FSL_HAVE_SCC2
+	LOCK_INCLUDES;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+	uint32_t slot_length;
+	uint32_t IV[4];
+	uint32_t *iv_ptr = (uint32_t *) & (owner_id);
+
+    /* Build the IV */
+    IV[0] = iv_ptr[0];
+	IV[1] = iv_ptr[1];
+	IV[2] = 0;
+	IV[3] = 0;
+	ACQUIRE_LOCK;
+
+	/* Call scc decrypt function to decrypt the data. */
+
+	/* Ensure that the data will fit in the key slot */
+	    slot_length =
+	    keystore->slot_get_slot_size(keystore->user_data, slot);
+	if (length > slot_length)
+		goto out;
+
+	/* Call scc decrypt function to encrypt the data. */
+	    retval = do_scc_decrypt_region(user_ctx,
+					   (void *)keystore->
+					   slot_get_base(keystore->user_data,
+							 slot),
+					   keystore->slot_get_offset(keystore->
+								      user_data,
+								      slot),
+					   length, source, IV,
+					   FSL_SHW_CYPHER_MODE_CBC);
+	goto out;
+out:RELEASE_LOCK;
+	return retval;
+
+#else
+	scc_return_t retval;
+	retval = scc_decrypt_slot(owner_id, slot, length, source);
+	if (retval == SCC_RET_OK)
+		return FSL_RETURN_OK_S;
+	return FSL_RETURN_ERROR_S;
+
+#endif	/* FSL_HAVE_SCC2 */
+}
+
+#else	/* SCC in userspace */
+void fsl_shw_init_keystore(
+			    fsl_shw_kso_t *keystore,
+			    fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx,
+							   void **user_data),
+			    void (*data_cleanup) (fsl_shw_uco_t *user_ctx,
+						   void **user_data),
+			    fsl_shw_return_t(*slot_alloc) (void *user_data,
+							    uint32_t size,
+							    uint64_t owner_id,
+							    uint32_t *slot),
+			    fsl_shw_return_t(*slot_dealloc) (void *user_data,
+							      uint64_t
+							      owner_id,
+							      uint32_t slot),
+			    fsl_shw_return_t(*slot_verify_access) (void
+								    *user_data,
+								    uint64_t
+								    owner_id,
+								    uint32_t
+								    slot),
+			    void *(*slot_get_address) (void *user_data,
+							uint32_t handle),
+			    uint32_t(*slot_get_base) (void *user_data,
+						       uint32_t handle),
+			    uint32_t(*slot_get_offset) (void *user_data,
+							 uint32_t handle),
+			    uint32_t(*slot_get_slot_size) (void *user_data,
+							    uint32_t handle))
+{
+	(void)keystore;
+	(void)data_init;
+	(void)data_cleanup;
+	(void)slot_alloc;
+	(void)slot_dealloc;
+	(void)slot_verify_access;
+	(void)slot_get_address;
+	(void)slot_get_base;
+	(void)slot_get_offset;
+	(void)slot_get_slot_size;
+}
+
+void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore)
+{
+	(void)keystore;
+}
+fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx,
+						 fsl_shw_kso_t *keystore)
+{
+	(void)user_ctx;
+	(void)keystore;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx,
+				fsl_shw_kso_t *keystore)
+{
+	(void)user_ctx;
+	(void)keystore;
+	return;
+}
+
+fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size,
+					uint64_t owner_id, uint32_t *slot)
+{
+	(void)keystore;
+	(void)size;
+	(void)owner_id;
+	(void)slot;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore,
+					 uint64_t owner_id, uint32_t slot)
+{
+	(void)keystore;
+	(void)owner_id;
+	(void)slot;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t
+keystore_slot_load(fsl_shw_kso_t *keystore, uint64_t owner_id, uint32_t slot,
+		   const uint8_t *key_data, uint32_t key_length)
+{
+	(void)keystore;
+	(void)owner_id;
+	(void)slot;
+	(void)key_data;
+	(void)key_length;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t
+keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot,
+		   uint32_t key_length, uint8_t * key_data)
+{
+	(void)keystore;
+	(void)owner_id;
+	(void)slot;
+	(void)key_length;
+	(void)key_data;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t
+keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore,
+		      uint64_t owner_id, uint32_t slot, uint32_t length,
+		      const uint8_t *source)
+{
+	(void)user_ctx;
+	(void)keystore;
+	(void)owner_id;
+	(void)slot;
+	(void)length;
+	(void)source;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t
+keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore,
+		      uint64_t owner_id, uint32_t slot, uint32_t length,
+		      uint8_t *destination)
+{
+	(void)user_ctx;
+	(void)keystore;
+	(void)owner_id;
+	(void)slot;
+	(void)length;
+	(void)destination;
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+
+#endif	/* FSL_HAVE_SCC2 */
+
+/***** Default keystore implementation **************************************/
+
+#ifdef FSL_HAVE_SCC2
+    fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx,
+					void **user_data)
+{
+	int retval = FSL_RETURN_ERROR_S;
+	keystore_data_t *keystore_data = NULL;
+	fsl_shw_pco_t *capabilities = fsl_shw_get_capabilities(user_ctx);
+	uint32_t partition_size;
+	uint32_t slot_count;
+	uint32_t keystore_data_size;
+	uint8_t UMID[16] = {
+	0x42, 0, 0, 0, 0x43, 0, 0, 0, 0x19, 0, 0, 0, 0x59, 0, 0, 0};
+	uint32_t permissions =
+	    FSL_PERM_TH_R | FSL_PERM_TH_W | FSL_PERM_HD_R | FSL_PERM_HD_W |
+	    FSL_PERM_HD_X;
+
+	/* Look up the size of a partition to see how big to make the keystore */
+	partition_size = fsl_shw_pco_get_spo_size_bytes(capabilities);
+
+	/* Calculate the required size of the keystore data structure, based on the
+	  * number of keys that can fit in the partition.
+	  */
+	slot_count = partition_size / KEYSTORE_SLOT_SIZE;
+	keystore_data_size =
+	    sizeof(keystore_data_t) +
+	    slot_count * sizeof(keystore_data_slot_info_t);
+
+#ifdef __KERNEL__
+	keystore_data = os_alloc_memory(keystore_data_size, GFP_KERNEL);
+
+#else
+	keystore_data = malloc(keystore_data_size);
+
+#endif
+	if (keystore_data == NULL) {
+		retval = FSL_RETURN_NO_RESOURCE_S;
+		goto out;
+	}
+
+    /* Clear the memory (effectively clear all key assignments) */
+    memset(keystore_data, 0, keystore_data_size);
+
+   /* Place the slot information structure directly after the keystore data
+	* structure.
+	*/
+	    keystore_data->slot =
+	    (keystore_data_slot_info_t *) (keystore_data + 1);
+	keystore_data->slot_count = slot_count;
+
+	/* Retrieve a secure partition to put the keystore in. */
+	keystore_data->base_address =
+	    fsl_shw_smalloc(user_ctx, partition_size, UMID, permissions);
+	if (keystore_data->base_address == NULL) {
+		retval = FSL_RETURN_NO_RESOURCE_S;
+		goto out;
+	}
+	*user_data = keystore_data;
+	retval = FSL_RETURN_OK_S;
+out:if (retval != FSL_RETURN_OK_S) {
+		if (keystore_data != NULL) {
+			if (keystore_data->base_address != NULL)
+				fsl_shw_sfree(NULL,
+					       keystore_data->base_address);
+
+#ifdef __KERNEL__
+			    os_free_memory(keystore_data);
+
+#else
+			    free(keystore_data);
+
+#endif
+		}
+	}
+	return retval;
+}
+void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data)
+{
+	if (user_data != NULL) {
+		keystore_data_t * keystore_data =
+		    (keystore_data_t *) (*user_data);
+		fsl_shw_sfree(user_ctx, keystore_data->base_address);
+
+#ifdef __KERNEL__
+		    os_free_memory(*user_data);
+
+#else
+		    free(*user_data);
+
+#endif
+	}
+	return;
+}
+
+fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id,
+					  uint32_t slot)
+{
+	keystore_data_t * data = user_data;
+	if (data->slot[slot].owner == owner_id) {
+		return FSL_RETURN_OK_S;
+	} else {
+
+#ifdef DIAG_DRV_IF
+		    LOG_DIAG_ARGS("Access to slot %i fails.\n", slot);
+
+#endif
+		    return FSL_RETURN_AUTH_FAILED_S;
+	}
+}
+
+fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size,
+				   uint64_t owner_id, uint32_t *slot)
+{
+	keystore_data_t *data = user_data;
+	uint32_t i;
+	if (size > KEYSTORE_SLOT_SIZE)
+		return FSL_RETURN_BAD_KEY_LENGTH_S;
+	for (i = 0; i < data->slot_count; i++) {
+		if (data->slot[i].allocated == 0) {
+			data->slot[i].allocated = 1;
+			data->slot[i].owner = owner_id;
+			(*slot) = i;
+
+#ifdef DIAG_DRV_IF
+			    LOG_DIAG_ARGS("Keystore: allocated slot %i. Slot "
+					  "address: %p\n",
+					  (*slot),
+					  data->base_address +
+					  (*slot) * KEYSTORE_SLOT_SIZE);
+
+#endif
+			    return FSL_RETURN_OK_S;
+		}
+	}
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id,
+				    uint32_t slot)
+{
+	keystore_data_t * data = user_data;
+	(void)owner_id;
+	(void)slot;
+	if (slot >= data->slot_count)
+		return FSL_RETURN_ERROR_S;
+	if (data->slot[slot].allocated == 1) {
+		/* Forcibly remove the data from the keystore */
+		memset(shw_slot_get_address(user_data, slot), 0,
+		       KEYSTORE_SLOT_SIZE);
+		data->slot[slot].allocated = 0;
+		return FSL_RETURN_OK_S;
+	}
+	return FSL_RETURN_ERROR_S;
+}
+
+void *shw_slot_get_address(void *user_data, uint32_t slot)
+{
+	keystore_data_t * data = user_data;
+	if (slot >= data->slot_count)
+		return NULL;
+	return data->base_address + slot * KEYSTORE_SLOT_SIZE;
+}
+
+uint32_t shw_slot_get_base(void *user_data, uint32_t slot)
+{
+	keystore_data_t * data = user_data;
+
+	/* There could potentially be more than one secure partition object
+	  * associated with this keystore.  For now, there is just one.
+	  */
+	(void)slot;
+	return (uint32_t) (data->base_address);
+}
+
+uint32_t shw_slot_get_offset(void *user_data, uint32_t slot)
+{
+	keystore_data_t *data = user_data;
+	if (slot >= data->slot_count)
+		return FSL_RETURN_ERROR_S;
+	return (slot * KEYSTORE_SLOT_SIZE);
+}
+
+uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot)
+{
+	(void)user_data;
+	(void)slot;
+
+	/* All slots are the same size in the default implementation */
+	return KEYSTORE_SLOT_SIZE;
+}
+
+#else	/* FSL_HAVE_SCC2 */
+
+#ifdef __KERNEL__
+    fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx,
+					void **user_data)
+{
+
+   /* The SCC does its own initialization.  All that needs to be done here is
+	* make sure an SCC exists.
+	*/
+	*user_data = (void *)0xFEEDFEED;
+	return FSL_RETURN_OK_S;
+}
+void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data)
+{
+
+    /* The SCC does its own cleanup. */
+	*user_data = NULL;
+	return;
+}
+
+fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id,
+					  uint32_t slot)
+{
+
+	/* Zero is used for the size because the newer interface does bounds
+	  * checking later.
+	  */
+	scc_return_t retval;
+	retval = scc_verify_slot_access(owner_id, slot, 0);
+	if (retval == SCC_RET_OK) {
+		return FSL_RETURN_OK_S;
+	}
+	return FSL_RETURN_AUTH_FAILED_S;
+}
+
+fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size,
+				   uint64_t owner_id, uint32_t *slot)
+{
+	scc_return_t retval;
+
+#ifdef DIAG_DRV_IF
+	    LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot);
+
+#endif
+	retval = scc_alloc_slot(size, owner_id, slot);
+	if (retval == SCC_RET_OK)
+		return FSL_RETURN_OK_S;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id,
+				    uint32_t slot)
+{
+	scc_return_t retval;
+	retval = scc_dealloc_slot(owner_id, slot);
+	if (retval == SCC_RET_OK)
+		return FSL_RETURN_OK_S;
+
+	return FSL_RETURN_ERROR_S;
+}
+void *shw_slot_get_address(void *user_data, uint32_t slot)
+{
+	uint64_t owner_id = *((uint64_t *) user_data);
+	uint32_t address;
+	uint32_t value_size_bytes;
+	uint32_t slot_size_bytes;
+	scc_return_t scc_ret;
+	scc_ret =
+	    scc_get_slot_info(owner_id, slot, &address, &value_size_bytes,
+			      &slot_size_bytes);
+	if (scc_ret == SCC_RET_OK) {
+		return (void *)address;
+	}
+	return NULL;
+}
+
+uint32_t shw_slot_get_base(void *user_data, uint32_t slot)
+{
+	return 0;
+}
+
+uint32_t shw_slot_get_offset(void *user_data, uint32_t slot)
+{
+	return 0;
+}
+
+
+/* Return the size of the key slot, in octets */
+uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot)
+{
+	uint64_t owner_id = *((uint64_t *) user_data);
+	uint32_t address;
+	uint32_t value_size_bytes;
+	uint32_t slot_size_bytes;
+	scc_return_t scc_ret;
+	scc_ret =
+	    scc_get_slot_info(owner_id, slot, &address, &value_size_bytes,
+			      &slot_size_bytes);
+	if (scc_ret == SCC_RET_OK)
+		return slot_size_bytes;
+	return 0;
+}
+
+
+#endif	/* __KERNEL__ */
+
+#endif	/* FSL_HAVE_SCC2 */
+
+/*****************************************************************************/
diff --git a/drivers/mxc/security/sahara2/fsl_shw_rand.c b/drivers/mxc/security/sahara2/fsl_shw_rand.c
new file mode 100644
index 000000000000..566c9e5c1e0f
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_rand.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_rand.c
+ *
+ * This file implements Random Number Generation functions of the FSL SHW API
+ * for Sahara.
+ */
+
+#include "sahara.h"
+#include "sf_util.h"
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_get_random);
+#endif
+
+/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */
+/*!
+ * Get a random number
+ *
+ *
+ * @param    user_ctx
+ * @param    length
+ * @param    data
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+				    uint32_t length, uint8_t * data)
+{
+	SAH_SF_DCLS;
+
+	/* perform a sanity check on the uco */
+	ret = sah_validate_uco(user_ctx);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	header = SAH_HDR_RNG_GENERATE;	/* Desc. #18 */
+	DESC_OUT_OUT(header, length, data, 0, NULL);
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_add_entropy);
+#endif
+
+/*!
+ * Add entropy to a random number generator
+
+ * @param    user_ctx
+ * @param    length
+ * @param    data
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+				     uint32_t length, uint8_t * data)
+{
+	SAH_SF_DCLS;
+
+	/* perform a sanity check on the uco */
+	ret = sah_validate_uco(user_ctx);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	header = SAH_HDR_RNG_GENERATE;	/* Desc. #18 */
+
+	/* create descriptor #18. Generate random data */
+	DESC_IN_IN(header, 0, NULL, length, data)
+
+	    SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
diff --git a/drivers/mxc/security/sahara2/fsl_shw_sym.c b/drivers/mxc/security/sahara2/fsl_shw_sym.c
new file mode 100644
index 000000000000..454905bbcf68
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_sym.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_sym.c
+ *
+ * This file implements Symmetric Cipher functions of the FSL SHW API for
+ * Sahara.  This does not include CCM.
+ */
+
+#include "sahara.h"
+#include "fsl_platform.h"
+
+#include "sf_util.h"
+#include "adaptor.h"
+
+#ifdef LINUX_KERNEL
+EXPORT_SYMBOL(fsl_shw_symmetric_encrypt);
+EXPORT_SYMBOL(fsl_shw_symmetric_decrypt);
+#endif
+
+#if defined(NEED_CTR_WORKAROUND)
+/* CTR mode needs block-multiple data in/out */
+#define LENGTH_PATCH  (sym_ctx->block_size_bytes)
+#define LENGTH_PATCH_MASK  (sym_ctx->block_size_bytes-1)
+#else
+#define LENGTH_PATCH  0
+#define LENGTH_PATCH_MASK  0	/* du not use! */
+#endif
+
+/*!
+ * Block of zeroes which is maximum Symmetric block size, used for
+ * initializing context register, etc.
+ */
+static uint32_t block_zeros[4] = {
+	0, 0, 0, 0
+};
+
+typedef enum cipher_direction {
+	SYM_DECRYPT,
+	SYM_ENCRYPT
+} cipher_direction_t;
+
+/*!
+ * Create and run the chain for a symmetric-key operation.
+ *
+ * @param user_ctx    Who the user is
+ * @param key_info    What key is to be used
+ * @param sym_ctx     Info details about algorithm
+ * @param encrypt     0 = decrypt, non-zero = encrypt
+ * @param length      Number of octets at @a in and @a out
+ * @param in          Pointer to input data
+ * @param out         Location to store output data
+ *
+ * @return         The status of handing chain to driver,
+ *                 or an earlier argument/flag or allocation
+ *                 error.
+ */
+static fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     fsl_shw_scco_t * sym_ctx,
+				     cipher_direction_t encrypt,
+				     uint32_t length,
+				     const uint8_t * in, uint8_t * out)
+{
+	SAH_SF_DCLS;
+	uint8_t *sink = NULL;
+	sah_Link *link1 = NULL;
+	sah_Link *link2 = NULL;
+	sah_Oct_Str ptr1;
+	uint32_t size1 = sym_ctx->block_size_bytes;
+
+	SAH_SF_USER_CHECK();
+
+	/* Two different sets of chains, depending on algorithm */
+	if (key_info->algorithm == FSL_KEY_ALG_ARC4) {
+		if (sym_ctx->flags & FSL_SYM_CTX_INIT) {
+			/* Desc. #35 w/ARC4 - start from key */
+			header = SAH_HDR_ARC4_SET_MODE_KEY
+			    ^ sah_insert_skha_algorithm_arc4;
+
+			DESC_IN_KEY(header, 0, NULL, key_info);
+		} else {	/* load SBox */
+			/* Desc. #33 w/ARC4 and NO PERMUTE */
+			header = SAH_HDR_ARC4_SET_MODE_SBOX
+			    ^ sah_insert_skha_no_permute
+			    ^ sah_insert_skha_algorithm_arc4;
+			DESC_IN_IN(header, 256, sym_ctx->context,
+				   3, sym_ctx->context + 256);
+		}		/* load SBox */
+
+		/* Add in-out data descriptor to process the data */
+		if (length != 0) {
+			DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC, length, in, length,
+				    out);
+		}
+
+		/* Operation is done ... save what came out? */
+		if (sym_ctx->flags & FSL_SYM_CTX_SAVE) {
+			/* Desc. #34 - Read SBox, pointers */
+			header = SAH_HDR_ARC4_READ_SBOX;
+			DESC_OUT_OUT(header, 256, sym_ctx->context,
+				     3, sym_ctx->context + 256);
+		}
+	} else {		/* not ARC4 */
+		/* Doing 1- or 2- descriptor chain. */
+		/* Desc. #1 and algorithm and mode */
+		header = SAH_HDR_SKHA_SET_MODE_IV_KEY
+		    ^ sah_insert_skha_mode[sym_ctx->mode]
+		    ^ sah_insert_skha_algorithm[key_info->algorithm];
+
+		/* Honor 'no key parity checking' for DES and TDES */
+		if ((key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) &&
+		    ((key_info->algorithm == FSL_KEY_ALG_DES) ||
+		     (key_info->algorithm == FSL_KEY_ALG_TDES))) {
+			header ^= sah_insert_skha_no_key_parity;
+		}
+
+		/* Header by default is decrypting, so... */
+		if (encrypt == SYM_ENCRYPT) {
+			header ^= sah_insert_skha_encrypt;
+		}
+
+		if (sym_ctx->mode == FSL_SYM_MODE_CTR) {
+			header ^= sah_insert_skha_modulus[sym_ctx->modulus_exp];
+		}
+
+		if (sym_ctx->mode == FSL_SYM_MODE_ECB) {
+			ptr1 = NULL;
+			size1 = 0;
+		} else if (sym_ctx->flags & FSL_SYM_CTX_INIT) {
+			ptr1 = (uint8_t *) block_zeros;
+		} else {
+			ptr1 = sym_ctx->context;
+		}
+
+		DESC_IN_KEY(header, sym_ctx->block_size_bytes, ptr1, key_info);
+
+		/* Add in-out data descriptor */
+		if (length != 0) {
+			header = SAH_HDR_SKHA_ENC_DEC;
+			if (LENGTH_PATCH && (sym_ctx->mode == FSL_SYM_MODE_CTR)
+			    && ((length & LENGTH_PATCH_MASK) != 0)) {
+				sink = DESC_TEMP_ALLOC(LENGTH_PATCH);
+				ret =
+				    sah_Create_Link(user_ctx->mem_util, &link1,
+						    (uint8_t *) in, length,
+						    SAH_USES_LINK_DATA);
+				ret =
+				    sah_Append_Link(user_ctx->mem_util, link1,
+						    (uint8_t *) sink,
+						    LENGTH_PATCH -
+						    (length &
+						     LENGTH_PATCH_MASK),
+						    SAH_USES_LINK_DATA);
+				if (ret != FSL_RETURN_OK_S) {
+					goto out;
+				}
+				ret =
+				    sah_Create_Link(user_ctx->mem_util, &link2,
+						    out, length,
+						    SAH_USES_LINK_DATA |
+						    SAH_OUTPUT_LINK);
+				if (ret != FSL_RETURN_OK_S) {
+					goto out;
+				}
+				ret = sah_Append_Link(user_ctx->mem_util, link2,
+						      sink,
+						      LENGTH_PATCH -
+						      (length &
+						       LENGTH_PATCH_MASK),
+						      SAH_USES_LINK_DATA);
+				if (ret != FSL_RETURN_OK_S) {
+					goto out;
+				}
+				ret =
+				    sah_Append_Desc(user_ctx->mem_util,
+						    &desc_chain, header, link1,
+						    link2);
+				if (ret != FSL_RETURN_OK_S) {
+					goto out;
+				}
+				link1 = link2 = NULL;
+			} else {
+				DESC_IN_OUT(header, length, in, length, out);
+			}
+		}
+
+		/* Unload any desired context */
+		if (sym_ctx->flags & FSL_SYM_CTX_SAVE) {
+			DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL,
+				     sym_ctx->block_size_bytes,
+				     sym_ctx->context);
+		}
+
+	}			/* not ARC4 */
+
+	SAH_SF_EXECUTE();
+
+      out:
+	SAH_SF_DESC_CLEAN();
+	DESC_TEMP_FREE(sink);
+	if (LENGTH_PATCH) {
+		sah_Destroy_Link(user_ctx->mem_util, link1);
+		sah_Destroy_Link(user_ctx->mem_util, link2);
+	}
+
+	return ret;
+}
+
+/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+
+/*!
+ * Compute symmetric encryption
+ *
+ *
+ * @param    user_ctx
+ * @param    key_info
+ * @param    sym_ctx
+ * @param    length
+ * @param    pt
+ * @param    ct
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * pt, uint8_t * ct)
+{
+	fsl_shw_return_t ret;
+
+	ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT,
+			   length, pt, ct);
+
+	return ret;
+}
+
+/* PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+
+/*!
+ * Compute symmetric decryption
+ *
+ *
+ * @param    user_ctx
+ * @param    key_info
+ * @param    sym_ctx
+ * @param    length
+ * @param    pt
+ * @param    ct
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+					   fsl_shw_sko_t * key_info,
+					   fsl_shw_scco_t * sym_ctx,
+					   uint32_t length,
+					   const uint8_t * ct, uint8_t * pt)
+{
+	fsl_shw_return_t ret;
+
+	ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT,
+			   length, ct, pt);
+
+	return ret;
+}
diff --git a/drivers/mxc/security/sahara2/fsl_shw_user.c b/drivers/mxc/security/sahara2/fsl_shw_user.c
new file mode 100644
index 000000000000..49ec97e7662a
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_user.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_user.c
+ *
+ * This file implements user and platform capabilities functions of the FSL SHW
+ * API for Sahara
+ */
+#include "sahara.h"
+#include <adaptor.h>
+#include <sf_util.h>
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_get_capabilities);
+EXPORT_SYMBOL(fsl_shw_register_user);
+EXPORT_SYMBOL(fsl_shw_deregister_user);
+EXPORT_SYMBOL(fsl_shw_get_results);
+#endif				/* __KERNEL__ */
+
+struct cap_t {
+	unsigned populated;
+	union {
+		uint32_t buffer[sizeof(fsl_shw_pco_t)];
+		fsl_shw_pco_t pco;
+	};
+};
+
+static struct cap_t cap = {
+	0,
+	{}
+};
+
+/* REQ-S2LRD-PINTFC-API-GEN-003 */
+/*!
+ * Determine the hardware security capabilities of this platform.
+ *
+ * Though a user context object is passed into this function, it will always
+ * act in a non-blocking manner.
+ *
+ * @param  user_ctx   The user context which will be used for the query.
+ *
+ * @return  A pointer to the capabilities object.
+ */
+fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx)
+{
+	fsl_shw_pco_t *retval = NULL;
+
+	if (cap.populated) {
+		retval = &cap.pco;
+	} else {
+		if (get_capabilities(user_ctx, &cap.pco) == FSL_RETURN_OK_S) {
+			cap.populated = 1;
+			retval = &cap.pco;
+		}
+	}
+	return retval;
+}
+
+/* REQ-S2LRD-PINTFC-API-GEN-004 */
+
+/*!
+ * Create an association between the the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which will be used for this association.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx)
+{
+	return sah_register(user_ctx);
+}
+
+/* REQ-S2LRD-PINTFC-API-GEN-005 */
+
+/*!
+ * Destroy the association between the the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which is no longer needed.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx)
+{
+	return sah_deregister(user_ctx);
+}
+
+/* REQ-S2LRD-PINTFC-API-GEN-006 */
+
+/*!
+ * Retrieve results from earlier operations.
+ *
+ * @param         user_ctx     The user's context.
+ * @param         result_size  The number of array elements of @a results.
+ * @param[in,out] results      Pointer to first of the (array of) locations to
+ *                             store results.
+ * @param[out]    result_count Pointer to store the number of results which
+ *                             were returned.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx,
+				     unsigned result_size,
+				     fsl_shw_result_t results[],
+				     unsigned *result_count)
+{
+	fsl_shw_return_t status;
+
+	/* perform a sanity check on the uco */
+	status = sah_validate_uco(user_ctx);
+
+	/* if uco appears ok, build structure and pass to get results */
+	if (status == FSL_RETURN_OK_S) {
+		sah_results arg;
+
+		/* if requested is zero, it's done before it started */
+		if (result_size > 0) {
+			arg.requested = result_size;
+			arg.actual = result_count;
+			arg.results = results;
+			/* get the results */
+			status = sah_get_results(&arg, user_ctx);
+		}
+	}
+
+	return status;
+}
diff --git a/drivers/mxc/security/sahara2/fsl_shw_wrap.c b/drivers/mxc/security/sahara2/fsl_shw_wrap.c
new file mode 100644
index 000000000000..ebcf9a6bd7c2
--- /dev/null
+++ b/drivers/mxc/security/sahara2/fsl_shw_wrap.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_shw_wrap.c
+ *
+ * This file implements Key-Wrap (Black Key) functions of the FSL SHW API for
+ * Sahara.
+ *
+ * - Ownerid is an 8-byte, user-supplied, value to keep KEY confidential.
+ * - KEY is a 1-32 byte value which starts in SCC RED RAM before
+ *     wrapping, and ends up there on unwrap.  Length is limited because of
+ *    size of SCC1 RAM.
+ * - KEY' is the encrypted KEY
+ * - LEN is a 1-byte (for now) byte-length of KEY
+ * - ALG is a 1-byte value for the algorithm which which the key is
+ *    associated.  Values are defined by the FSL SHW API
+ * - Ownerid, LEN, and ALG come from the user's "key_info" object, as does the
+ *    slot number where KEY already is/will be.
+ * - T is a Nonce
+ * - T' is the encrypted T
+ * - KEK is a Key-Encryption Key for the user's Key
+ * - ICV is the "Integrity Check Value" for the wrapped key
+ * - Black Key is the string of bytes returned as the wrapped key
+<table>
+<tr><TD align="right">BLACK_KEY <TD width="3">=<TD>ICV | T' | LEN | ALG |
+     KEY'</td></tr>
+<tr><td>&nbsp;</td></tr>
+
+<tr><th>To Wrap</th></tr>
+<tr><TD align="right">T</td> <TD width="3">=</td> <TD>RND()<sub>16</sub>
+    </td></tr>
+<tr><TD align="right">KEK</td><TD width="3">=</td><TD>HASH<sub>sha256</sub>(T |
+     Ownerid)<sub>16</sub></td></tr>
+<tr><TD align="right">KEY'<TD width="3">=</td><TD>
+     AES<sub>ctr-enc</sub>(Key=KEK, CTR=0, Data=KEY)</td></tr>
+<tr><TD align="right">ICV</td><TD width="3">=</td><td>HMAC<sub>sha256</sub>
+     (Key=T, Data=Ownerid | LEN | ALG | KEY')<sub>16</sub></td></tr>
+<tr><TD align="right">T'</td><TD width="3">=</td><TD>TDES<sub>cbc-enc</sub>
+     (Key=SLID, IV=Ownerid, Data=T)</td></tr>
+
+<tr><td>&nbsp;</td></tr>
+
+<tr><th>To Unwrap</th></tr>
+<tr><TD align="right">T</td><TD width="3">=</td><TD>TDES<sub>ecb-dec</sub>
+    (Key=SLID, IV=Ownerid, Data=T')</sub></td></tr>
+<tr><TD align="right">ICV</td><TD width="3">=</td><td>HMAC<sub>sha256</sub>
+    (Key=T, Data=Ownerid | LEN | ALG | KEY')<sub>16</sub></td></tr>
+<tr><TD align="right">KEK</td><TD width="3">=</td><td>HASH<sub>sha256</sub>
+    (T | Ownerid)<sub>16</sub></td></tr>
+<tr><TD align="right">KEY<TD width="3">=</td><TD>AES<sub>ctr-dec</sub>
+    (Key=KEK, CTR=0, Data=KEY')</td></tr>
+</table>
+
+ */
+
+#include "sahara.h"
+#include "fsl_platform.h"
+#include "fsl_shw_keystore.h"
+
+#include "sf_util.h"
+#include "adaptor.h"
+
+#if defined(DIAG_SECURITY_FUNC)
+#include <diagnostic.h>
+#endif
+
+#if defined(NEED_CTR_WORKAROUND)
+/* CTR mode needs block-multiple data in/out */
+#define LENGTH_PATCH  16
+#define LENGTH_PATCH_MASK  0xF
+#else
+#define LENGTH_PATCH  4
+#define LENGTH_PATCH_MASK  3
+#endif
+
+#if LENGTH_PATCH
+#define ROUND_LENGTH(len)                                                  \
+({                                                                         \
+    uint32_t orig_len = len;                                               \
+    uint32_t new_len;                                                      \
+                                                                           \
+   if ((orig_len & LENGTH_PATCH_MASK) != 0) {                              \
+       new_len = (orig_len + LENGTH_PATCH                                  \
+            - (orig_len & LENGTH_PATCH_MASK));                             \
+   }                                                                       \
+   else {                                                                  \
+       new_len = orig_len;                                                 \
+   }                                                                       \
+       new_len;                                                            \
+})
+#else
+#define ROUND_LENGTH(len) (len)
+#endif
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(fsl_shw_establish_key);
+EXPORT_SYMBOL(fsl_shw_extract_key);
+EXPORT_SYMBOL(fsl_shw_release_key);
+EXPORT_SYMBOL(fsl_shw_read_key);
+#endif
+
+#define ICV_LENGTH 16
+#define T_LENGTH 16
+#define KEK_LENGTH 16
+#define LENGTH_LENGTH 1
+#define ALGORITHM_LENGTH 1
+#define FLAGS_LENGTH 1
+
+/* ICV | T' | LEN | ALG | KEY' */
+#define ICV_OFFSET       0
+#define T_PRIME_OFFSET   (ICV_OFFSET + ICV_LENGTH)
+#define LENGTH_OFFSET    (T_PRIME_OFFSET + T_LENGTH)
+#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH)
+#define FLAGS_OFFSET     (ALGORITHM_OFFSET + ALGORITHM_LENGTH)
+#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH)
+#define FLAGS_SW_KEY     0x01
+
+/*
+ * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag
+ * causes the T_block to go into the T field during a wrap operation.  This
+ * will make the black key value repeatable (for a given SCC secret key, or
+ * always if the default key is in use).
+ *
+ * Normally, a random sequence is used.
+ */
+#ifdef DO_REPEATABLE_WRAP
+/*!
+ * Block of zeroes which is maximum Symmetric block size, used for
+ * initializing context register, etc.
+ */
+static uint8_t T_block_[16] = {
+	0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42,
+	0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42
+};
+#endif
+
+/*!
+ * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY')
+ *
+ * @param  user_ctx      User's context for this operation
+ * @param  desc_chain    Descriptor chain to append to
+ * @param  t_key_info    T's key object
+ * @param  black_key     Beginning of Black Key region
+ * @param  key_length    Number of bytes of key' there are in @c black_key
+ * @param[out] hmac      Location to store ICV.  Will be tagged "USES" so
+ *                       sf routines will not try to free it.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static inline fsl_shw_return_t create_icv_calc(fsl_shw_uco_t * user_ctx,
+					       sah_Head_Desc ** desc_chain,
+					       fsl_shw_sko_t * t_key_info,
+					       const uint8_t * black_key,
+					       uint32_t key_length,
+					       uint8_t * hmac)
+{
+	fsl_shw_return_t sah_code;
+	uint32_t header;
+	sah_Link *link1 = NULL;
+	sah_Link *link2 = NULL;
+
+	/* Load up T as key for the HMAC */
+	header = (SAH_HDR_MDHA_SET_MODE_MD_KEY	/* #6 */
+		  ^ sah_insert_mdha_algorithm_sha256
+		  ^ sah_insert_mdha_init ^ sah_insert_mdha_hmac ^
+		  sah_insert_mdha_pdata ^ sah_insert_mdha_mac_full);
+	sah_code = sah_add_in_key_desc(header, NULL, 0, t_key_info,	/* Reference T in RED */
+				       user_ctx->mem_util, desc_chain);
+	if (sah_code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Previous step loaded key; Now set up to hash the data */
+	header = SAH_HDR_MDHA_HASH;	/* #10 */
+
+	/* Input - start with ownerid */
+	sah_code = sah_Create_Link(user_ctx->mem_util, &link1,
+				   (void *)&t_key_info->userid,
+				   sizeof(t_key_info->userid),
+				   SAH_USES_LINK_DATA);
+	if (sah_code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Still input  - Append black-key fields len, alg, key' */
+	sah_code = sah_Append_Link(user_ctx->mem_util, link1,
+				   (void *)black_key + LENGTH_OFFSET,
+				   (LENGTH_LENGTH
+				    + ALGORITHM_LENGTH
+				    + key_length), SAH_USES_LINK_DATA);
+
+	if (sah_code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	/* Output - computed ICV/HMAC */
+	sah_code = sah_Create_Link(user_ctx->mem_util, &link2,
+				   hmac, ICV_LENGTH,
+				   SAH_USES_LINK_DATA | SAH_OUTPUT_LINK);
+	if (sah_code != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	sah_code = sah_Append_Desc(user_ctx->mem_util, desc_chain,
+				   header, link1, link2);
+
+      out:
+	if (sah_code != FSL_RETURN_OK_S) {
+		(void)sah_Destroy_Link(user_ctx->mem_util, link1);
+		(void)sah_Destroy_Link(user_ctx->mem_util, link2);
+	}
+
+	return sah_code;
+}				/* create_icv_calc */
+
+/*!
+ * Perform unwrapping of a black key into a RED slot
+ *
+ * @param         user_ctx      A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be unwrapped... key length, slot info, etc.
+ * @param         black_key     Encrypted key
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx,
+			       fsl_shw_sko_t * key_info,
+			       const uint8_t * black_key)
+{
+	SAH_SF_DCLS;
+	uint8_t *hmac = NULL;
+	fsl_shw_sko_t t_key_info;
+	sah_Link *link1 = NULL;
+	sah_Link *link2 = NULL;
+	unsigned i;
+	unsigned rounded_key_length;
+	unsigned original_key_length = key_info->key_length;
+
+	hmac = DESC_TEMP_ALLOC(ICV_LENGTH);
+
+	/* Set up key_info for "T" - use same slot as eventual key */
+	fsl_shw_sko_init(&t_key_info, FSL_KEY_ALG_AES);
+	t_key_info.userid = key_info->userid;
+	t_key_info.handle = key_info->handle;
+	t_key_info.flags = key_info->flags;
+	t_key_info.key_length = T_LENGTH;
+	t_key_info.keystore = key_info->keystore;
+
+	/* Validate SW flags to prevent misuse */
+	if ((key_info->flags & FSL_SKO_KEY_SW_KEY)
+		&& !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	/* Compute T = SLID_decrypt(T'); leave in RED slot */
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_decrypt(user_ctx,
+					key_info->userid,
+				    t_key_info.handle,
+				    T_LENGTH,
+				    black_key + T_PRIME_OFFSET);
+
+	} else {
+			/* Key goes in user keystore */
+			ret = keystore_slot_decrypt(user_ctx,
+							key_info->keystore,
+							key_info->userid,
+							t_key_info.handle,
+							T_LENGTH,
+						    black_key + T_PRIME_OFFSET);
+	}
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Compute ICV = HMAC(T, ownerid | len | alg | key' */
+	ret = create_icv_calc(user_ctx, &desc_chain, &t_key_info,
+			      black_key, original_key_length, hmac);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Creation of sah_Key_Link failed due to bad key"
+			 " flag!\n");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Validating MAC of wrapped key");
+#endif
+	SAH_SF_EXECUTE();
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	SAH_SF_DESC_CLEAN();
+
+	/* Check computed ICV against value in Black Key */
+	for (i = 0; i < ICV_LENGTH; i++) {
+		if (black_key[ICV_OFFSET + i] != hmac[i]) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG_ARGS("computed ICV fails at offset %i\n", i);
+
+			{
+				char buff[300];
+				int a;
+				for (a = 0; a < ICV_LENGTH; a++)
+					sprintf(&(buff[a * 2]), "%02x",
+						black_key[ICV_OFFSET + a]);
+				buff[a * 2 + 1] = 0;
+				LOG_DIAG_ARGS("black key: %s", buff);
+
+				for (a = 0; a < ICV_LENGTH; a++)
+					sprintf(&(buff[a * 2]), "%02x",
+						hmac[a]);
+				buff[a * 2 + 1] = 0;
+				LOG_DIAG_ARGS("hmac:      %s", buff);
+			}
+#endif
+			ret = FSL_RETURN_AUTH_FAILED_S;
+			goto out;
+		}
+	}
+
+	/* This is no longer needed. */
+	DESC_TEMP_FREE(hmac);
+
+	/* Compute KEK = SHA256(T | ownerid).  Rewrite slot with value */
+	header = (SAH_HDR_MDHA_SET_MODE_HASH	/* #8 */
+		  ^ sah_insert_mdha_init
+		  ^ sah_insert_mdha_algorithm_sha256 ^ sah_insert_mdha_pdata);
+
+	/* Input - Start with T */
+	ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &t_key_info);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Still input - append ownerid */
+	ret = sah_Append_Link(user_ctx->mem_util, link1,
+			      (void *)&key_info->userid,
+			      sizeof(key_info->userid), SAH_USES_LINK_DATA);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Output - KEK goes into RED slot */
+	ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &t_key_info);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Put the Hash calculation into the chain. */
+	ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain,
+			      header, link1, link2);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	/* Compute KEY = AES-decrypt(KEK, KEY') */
+	header = (SAH_HDR_SKHA_SET_MODE_IV_KEY	/* #1 */
+		  ^ sah_insert_skha_mode_ctr
+		  ^ sah_insert_skha_algorithm_aes
+		  ^ sah_insert_skha_modulus_128);
+	/* Load KEK in as the key to use */
+	DESC_IN_KEY(header, 0, NULL, &t_key_info);
+
+	rounded_key_length = ROUND_LENGTH(original_key_length);
+	key_info->key_length = rounded_key_length;
+
+	/* Now set up for computation.  Result in RED */
+	header = SAH_HDR_SKHA_ENC_DEC;	/* #4 */
+	DESC_IN_KEY(header, rounded_key_length, black_key + KEY_PRIME_OFFSET,
+		    key_info);
+
+	/* Perform the operation */
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Decrypting key with KEK");
+#endif
+	SAH_SF_EXECUTE();
+
+      out:
+	key_info->key_length = original_key_length;
+	SAH_SF_DESC_CLEAN();
+
+	DESC_TEMP_FREE(hmac);
+
+	/* Erase tracks */
+	t_key_info.userid = 0xdeadbeef;
+	t_key_info.handle = 0xdeadbeef;
+
+	return ret;
+}				/* unwrap */
+
+/*!
+ * Perform wrapping of a black key from a RED slot
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be wrapped... key length, slot info, etc.
+ * @param      black_key        Place to store encrypted key
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx,
+			     fsl_shw_sko_t * key_info, uint8_t * black_key)
+{
+	SAH_SF_DCLS;
+	unsigned slots_allocated = 0;	/* boolean */
+	fsl_shw_sko_t T_key_info;	/* for holding T */
+	fsl_shw_sko_t KEK_key_info;	/* for holding KEK */
+	unsigned original_key_length = key_info->key_length;
+	unsigned rounded_key_length;
+	sah_Link *link1;
+	sah_Link *link2;
+
+	black_key[LENGTH_OFFSET] = key_info->key_length;
+	black_key[ALGORITHM_OFFSET] = key_info->algorithm;
+
+	memcpy(&T_key_info, key_info, sizeof(T_key_info));
+	fsl_shw_sko_set_key_length(&T_key_info, T_LENGTH);
+	T_key_info.algorithm = FSL_KEY_ALG_HMAC;
+
+	memcpy(&KEK_key_info, &T_key_info, sizeof(KEK_key_info));
+	KEK_key_info.algorithm = FSL_KEY_ALG_AES;
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_alloc(user_ctx,
+				T_LENGTH, key_info->userid,
+			    &T_key_info.handle);
+
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_alloc(key_info->keystore,
+				  T_LENGTH,
+				  key_info->userid, &T_key_info.handle);
+	}
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_alloc(user_ctx,
+				KEK_LENGTH, key_info->userid,
+				&KEK_key_info.handle);
+
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_alloc(key_info->keystore,
+			  KEK_LENGTH,  key_info->userid,
+			  &KEK_key_info.handle);
+	}
+
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("do_scc_slot_alloc() failed");
+#endif
+		if (key_info->keystore == NULL) {
+			/* Key goes in system keystore */
+			(void)do_system_keystore_slot_dealloc(user_ctx,
+				key_info->userid, T_key_info.handle);
+
+		} else {
+			/* Key goes in user keystore */
+			(void)keystore_slot_dealloc(key_info->keystore,
+					key_info->userid, T_key_info.handle);
+		}
+	} else {
+		slots_allocated = 1;
+	}
+
+	/* Set up to compute everything except T' ... */
+#ifndef DO_REPEATABLE_WRAP
+	/* Compute T = RND() */
+	header = SAH_HDR_RNG_GENERATE;	/* Desc. #18 */
+	DESC_KEY_OUT(header, &T_key_info, 0, NULL);
+#else
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_load(user_ctx,
+			   T_key_info.userid,
+			   T_key_info.handle, T_block,
+			   T_key_info.key_length);
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_load(key_info->keystore,
+				 T_key_info.userid,
+				 T_key_info.handle,
+				 T_block, T_key_info.key_length);
+	}
+
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+#endif
+
+	/* Compute KEK = SHA256(T | Ownerid) */
+	header = (SAH_HDR_MDHA_SET_MODE_HASH	/* #8 */
+		  ^ sah_insert_mdha_init
+		  ^ sah_insert_mdha_algorithm[FSL_HASH_ALG_SHA256]
+		  ^ sah_insert_mdha_pdata);
+	/* Input - Start with T */
+	ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &T_key_info);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	/* Still input - append ownerid */
+	ret = sah_Append_Link(user_ctx->mem_util, link1,
+			      (void *)&key_info->userid,
+			      sizeof(key_info->userid), SAH_USES_LINK_DATA);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	/* Output - KEK goes into RED slot */
+	ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &KEK_key_info);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+	/* Put the Hash calculation into the chain. */
+	ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain,
+			      header, link1, link2);
+	if (ret != FSL_RETURN_OK_S) {
+		goto out;
+	}
+#if defined(NEED_CTR_WORKAROUND)
+	rounded_key_length = ROUND_LENGTH(original_key_length);
+	key_info->key_length = rounded_key_length;
+#else
+	rounded_key_length = original_key_length;
+#endif
+	/* Compute KEY' = AES-encrypt(KEK, KEY) */
+	header = (SAH_HDR_SKHA_SET_MODE_IV_KEY	/* #1 */
+		  ^ sah_insert_skha_mode[FSL_SYM_MODE_CTR]
+		  ^ sah_insert_skha_algorithm[FSL_KEY_ALG_AES]
+		  ^ sah_insert_skha_modulus[FSL_CTR_MOD_128]);
+	/* Set up KEK as key to use */
+	DESC_IN_KEY(header, 0, NULL, &KEK_key_info);
+	header = SAH_HDR_SKHA_ENC_DEC;
+	DESC_KEY_OUT(header, key_info,
+		     key_info->key_length, black_key + KEY_PRIME_OFFSET);
+
+	/* Set up flags info */
+	black_key[FLAGS_OFFSET] = 0;
+	if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+		black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY;
+	}
+
+	/* Compute and store ICV into Black Key */
+	ret = create_icv_calc(user_ctx, &desc_chain, &T_key_info,
+			      black_key, original_key_length,
+			      black_key + ICV_OFFSET);
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Creation of sah_Key_Link failed due to bad key"
+			 " flag!\n");
+#endif				/*DIAG_SECURITY_FUNC */
+		goto out;
+	}
+
+	/* Now get Sahara to do the work. */
+#ifdef DIAG_SECURITY_FUNC
+	LOG_DIAG("Encrypting key with KEK");
+#endif
+	SAH_SF_EXECUTE();
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("sah_Descriptor_Chain_Execute() failed");
+#endif
+		goto out;
+	}
+
+	/* Compute T' = SLID_encrypt(T); Result goes to Black Key */
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_encrypt(user_ctx,
+					T_key_info.userid,  T_key_info.handle,
+					T_LENGTH, black_key + T_PRIME_OFFSET);
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_encrypt(user_ctx,
+					    key_info->keystore,
+					    T_key_info.userid,
+					    T_key_info.handle,
+					    T_LENGTH,
+					    black_key + T_PRIME_OFFSET);
+	}
+
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("do_scc_slot_encrypt() failed");
+#endif
+		goto out;
+	}
+
+      out:
+	key_info->key_length = original_key_length;
+
+	SAH_SF_DESC_CLEAN();
+	if (slots_allocated) {
+		if (key_info->keystore == NULL) {
+			/* Key goes in system keystore */
+			(void)do_system_keystore_slot_dealloc(user_ctx,
+							      key_info->userid,
+							      T_key_info.
+							      handle);
+			(void)do_system_keystore_slot_dealloc(user_ctx,
+							      key_info->userid,
+							      KEK_key_info.
+							      handle);
+		} else {
+			/* Key goes in user keystore */
+			(void)keystore_slot_dealloc(key_info->keystore,
+						    key_info->userid,
+				    T_key_info.handle);
+			(void)keystore_slot_dealloc(key_info->keystore,
+				    key_info->userid,
+				    KEK_key_info.handle);
+	    }
+	}
+
+	return ret;
+}				/* wrap */
+
+/*!
+ * Place a key into a protected location for use only by cryptographic
+ * algorithms.
+ *
+ * This only needs to be used to a) unwrap a key, or b) set up a key which
+ * could be wrapped with a later call to #fsl_shw_extract_key().  Normal
+ * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with
+ * #fsl_shw_sko_set_key() and used directly.
+ *
+ * The maximum key size supported for wrapped/unwrapped keys is 32 octets.
+ * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC
+ * key based on SHA-256.)  The key size is determined by the @a key_info.  The
+ * expected length of @a key can be determined by
+ * #fsl_shw_sko_calculate_wrapped_size()
+ *
+ * The protected key will not be available for use until this operation
+ * successfully completes.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be established.  In the create case, the key
+ *                              length must be set.
+ * @param      establish_type   How @a key will be interpreted to establish a
+ *                              key for use.
+ * @param key                   If @a establish_type is #FSL_KEY_WRAP_UNWRAP,
+ *                              this is the location of a wrapped key.  If
+ *                              @a establish_type is #FSL_KEY_WRAP_CREATE, this
+ *                              parameter can be @a NULL.  If @a establish_type
+ *                              is #FSL_KEY_WRAP_ACCEPT, this is the location
+ *                              of a plaintext key.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+				       fsl_shw_sko_t * key_info,
+				       fsl_shw_key_wrap_t establish_type,
+				       const uint8_t * key)
+{
+	SAH_SF_DCLS;
+	unsigned original_key_length = key_info->key_length;
+	unsigned rounded_key_length;
+	unsigned slot_allocated = 0;
+	uint32_t old_flags;
+
+	header = SAH_HDR_RNG_GENERATE;	/* Desc. #18 for rand */
+
+	/* TODO: THIS STILL NEEDS TO BE REFACTORED */
+
+	/* Write operations into SCC memory require word-multiple number of
+	 * bytes.  For ACCEPT and CREATE functions, the key length may need
+	 * to be rounded up.  Calculate. */
+	if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) {
+		rounded_key_length = original_key_length + LENGTH_PATCH
+		    - (original_key_length & LENGTH_PATCH_MASK);
+	} else {
+		rounded_key_length = original_key_length;
+	}
+
+	SAH_SF_USER_CHECK();
+
+	if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+#ifdef DIAG_SECURITY_FUNC
+			ret = FSL_RETURN_BAD_FLAG_S;
+			LOG_DIAG("Key already established\n");
+#endif
+	}
+
+
+	if (key_info->keystore == NULL) {
+		/* Key goes in system keystore */
+		ret = do_system_keystore_slot_alloc(user_ctx,
+						    key_info->key_length,
+						    key_info->userid,
+						    &(key_info->handle));
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG_ARGS
+		    ("key length: %i, handle: %i, rounded key length: %i",
+		     key_info->key_length, key_info->handle,
+		     rounded_key_length);
+#endif
+
+	} else {
+		/* Key goes in user keystore */
+		ret = keystore_slot_alloc(key_info->keystore,
+					  key_info->key_length,
+					  key_info->userid,
+					  &(key_info->handle));
+	}
+	if (ret != FSL_RETURN_OK_S) {
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Slot allocation failed\n");
+#endif
+		goto out;
+	}
+	slot_allocated = 1;
+
+	key_info->flags |= FSL_SKO_KEY_ESTABLISHED;
+	switch (establish_type) {
+	case FSL_KEY_WRAP_CREATE:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Creating random key\n");
+#endif
+		/* Use safe version of key length */
+		key_info->key_length = rounded_key_length;
+		/* Generate descriptor to put random value into */
+		DESC_KEY_OUT(header, key_info, 0, NULL);
+		/* Restore actual, desired key length */
+		key_info->key_length = original_key_length;
+
+		old_flags = user_ctx->flags;
+		/* Now put random value into key */
+		SAH_SF_EXECUTE();
+		/* Restore user's old flag value */
+		user_ctx->flags = old_flags;
+#ifdef DIAG_SECURITY_FUNC
+		if (ret == FSL_RETURN_OK_S) {
+			LOG_DIAG("ret is ok");
+		} else {
+			LOG_DIAG("ret is not ok");
+		}
+#endif
+		break;
+
+	case FSL_KEY_WRAP_ACCEPT:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Accepting plaintext key\n");
+#endif
+		if (key == NULL) {
+#ifdef DIAG_SECURITY_FUNC
+			LOG_DIAG("ACCEPT:  Red Key is NULL");
+#endif
+			ret = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+		/* Copy in safe number of bytes of Red key */
+		if (key_info->keystore == NULL) {
+			/* Key goes in system keystore */
+			ret = do_system_keystore_slot_load(user_ctx,
+						   key_info->userid,
+						   key_info->handle, key,
+						   rounded_key_length);
+		} else {
+			/* Key goes in user keystore */
+			ret = keystore_slot_load(key_info->keystore,
+								 key_info->userid,
+								 key_info->handle, key,
+								 key_info->key_length);
+		}
+		break;
+
+	case FSL_KEY_WRAP_UNWRAP:
+#ifdef DIAG_SECURITY_FUNC
+		LOG_DIAG("Unwrapping wrapped key\n");
+#endif
+		/* For now, disallow non-blocking calls. */
+		if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {
+			ret = FSL_RETURN_BAD_FLAG_S;
+		} else if (key == NULL) {
+			ret = FSL_RETURN_ERROR_S;
+		} else {
+			ret = unwrap(user_ctx, key_info, key);
+		}
+		break;
+
+	default:
+		ret = FSL_RETURN_BAD_FLAG_S;
+		break;
+	}			/* switch */
+
+      out:
+	if (slot_allocated && (ret != FSL_RETURN_OK_S)) {
+		fsl_shw_return_t scc_err;
+
+		if (key_info->keystore == NULL) {
+			/* Key goes in system keystore */
+			scc_err = do_system_keystore_slot_dealloc(user_ctx,
+						  key_info->userid,
+						  key_info->handle);
+		} else {
+			/* Key goes in user keystore */
+			scc_err = keystore_slot_dealloc(key_info->keystore,
+						key_info->userid,  key_info->handle);
+		}
+
+		key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED;
+	}
+
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}				/* fsl_shw_establish_key() */
+
+/*!
+ * Wrap a key and retrieve the wrapped value.
+ *
+ * A wrapped key is a key that has been cryptographically obscured.  It is
+ * only able to be used with #fsl_shw_establish_key().
+ *
+ * This function will also release the key (see #fsl_shw_release_key()) so
+ * that it must be re-established before reuse.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ * @param[out] covered_key      The location to store the 48-octet wrapped key.
+ *                              (This size is based upon the maximum key size
+ *                              of 32 octets).
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     uint8_t * covered_key)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	/* For now, only blocking mode calls are supported */
+	if (user_ctx->flags & FSL_UCO_BLOCKING_MODE) {
+		if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+			ret = wrap(user_ctx, key_info, covered_key);
+			if (ret != FSL_RETURN_OK_S) {
+				goto out;
+			}
+
+			/* Verify that a SW key info really belongs to a SW key */
+			if (key_info->flags & FSL_SKO_KEY_SW_KEY) {
+			/*  ret = FSL_RETURN_BAD_FLAG_S;
+			  goto out;*/
+			}
+
+			/* Need to deallocate on successful extraction */
+			if (key_info->keystore == NULL) {
+				/* Key goes in system keystore */
+				ret = do_system_keystore_slot_dealloc(user_ctx,
+						key_info->userid, key_info->handle);
+			} else {
+				/* Key goes in user keystore */
+				ret = keystore_slot_dealloc(key_info->keystore,
+						key_info->userid, key_info->handle);
+			}
+			/* Mark key not available in the flags */
+			key_info->flags &=
+			    ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT);
+		}
+	}
+
+out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
+
+/*!
+ * De-establish a key so that it can no longer be accessed.
+ *
+ * The key will need to be re-established before it can again be used.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+		if (key_info->keystore == NULL) {
+			/* Key goes in system keystore */
+			do_system_keystore_slot_dealloc(user_ctx,
+							key_info->userid,
+							key_info->handle);
+		} else {
+			/* Key goes in user keystore */
+			keystore_slot_dealloc(key_info->keystore,
+						key_info->userid,
+						key_info->handle);
+		}
+		key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED |
+				     FSL_SKO_KEY_PRESENT);
+	}
+
+out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
+
+fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+				  fsl_shw_sko_t * key_info, uint8_t * key)
+{
+	SAH_SF_DCLS;
+
+	SAH_SF_USER_CHECK();
+
+	if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)
+	    || !(key_info->flags & FSL_SKO_KEY_SW_KEY)) {
+		ret = FSL_RETURN_BAD_FLAG_S;
+		goto out;
+	}
+
+	if (key_info->keystore == NULL) {
+		/* Key lives in system keystore */
+		ret = do_system_keystore_slot_read(user_ctx,
+						   key_info->userid,
+						   key_info->handle,
+						   key_info->key_length, key);
+	} else {
+		/* Key lives in user keystore */
+		ret = keystore_slot_read(key_info->keystore,
+					 key_info->userid,
+					 key_info->handle,
+					 key_info->key_length, key);
+	}
+
+      out:
+	SAH_SF_DESC_CLEAN();
+
+	return ret;
+}
diff --git a/drivers/mxc/security/sahara2/include/adaptor.h b/drivers/mxc/security/sahara2/include/adaptor.h
new file mode 100644
index 000000000000..d2cb35b21e4c
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/adaptor.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file adaptor.h
+*
+* @brief The Adaptor component provides an interface to the device
+* driver.
+*
+* Intended to be used by the FSL SHW API, this can also be called directly
+*/
+
+#ifndef ADAPTOR_H
+#define ADAPTOR_H
+
+#include <sahara.h>
+
+/*!
+ * Structure passed during user ioctl() call to submit request.
+ */
+typedef struct sah_dar {
+	sah_Desc *desc_addr;	/*!< head of descriptor chain */
+	uint32_t uco_flags;	/*!< copy of fsl_shw_uco flags field */
+	uint32_t uco_user_ref;	/*!< copy of fsl_shw_uco user_ref */
+	uint32_t result;	/*!< result of descriptor chain request */
+	struct sah_dar *next;	/*!< for driver use */
+} sah_dar_t;
+
+/*!
+ * Structure passed during user ioctl() call to Register a user
+ */
+typedef struct sah_register {
+	uint32_t pool_size;	/*!< max number of outstanding requests possible */
+	uint32_t result;	/*!< result of registration request */
+} sah_register_t;
+
+/*!
+ * Structure passed during ioctl() call to request SCC operation
+ */
+typedef struct scc_data {
+	uint32_t length;	/*!< length of data */
+	uint8_t *in;		/*!< input data */
+	uint8_t *out;		/*!< output data */
+	unsigned direction;	/*!< encrypt or decrypt */
+	fsl_shw_sym_mode_t crypto_mode;	/*!< CBC or EBC */
+	uint8_t *init_vector;	/*!< initialization vector or NULL */
+} scc_data_t;
+
+/*!
+ * Structure passed during user ioctl() calls to manage stored keys and
+ * stored-key slots.
+ */
+typedef struct scc_slot_t {
+	uint64_t ownerid;	/*!< Owner's id to check/set permissions */
+	uint32_t key_length;	/*!< Length of key */
+	uint32_t slot;		/*!< Slot to operation on, or returned slot
+				   number. */
+	uint8_t *key;		/*!< User-memory pointer to key value */
+	fsl_shw_return_t code;	/*!< API return code from operation */
+} scc_slot_t;
+
+/*
+ * Structure passed during user ioctl() calls to manage data stored in secure
+ * partitions.
+ */
+typedef struct scc_region_t {
+    uint32_t partition_base;	/*!< User virtual address of the
+					   partition base. */
+	uint32_t offset;	/*!< Offset from the start of the
+				   partition where the cleartext data
+				   is located. */
+	uint32_t length;	/*!< Length of the region to be
+				   operated on */
+	uint8_t *black_data;	/*!< User virtual address of any black
+				   (encrypted) data. */
+	fsl_shw_cypher_mode_t cypher_mode;	/*!< Cypher mode to use in an encryt/
+						   decrypt operation. */
+	uint32_t IV[4];		/*!< Intialization vector to use in an
+				   encrypt/decrypt operation. */
+	fsl_shw_return_t code;	/*!< API return code from operation */
+} scc_region_t;
+
+/*
+ * Structure passed during user ioctl() calls to manage secure partitions.
+ */
+typedef struct scc_partition_info_t {
+    uint32_t user_base;            /**< Userspace pointer to base of partition */
+    uint32_t permissions;          /**< Permissions to give the partition (only
+                                        used in call to _DROP_PERMS) */
+	fsl_shw_partition_status_t status;	/*!< Status of the partition */
+} scc_partition_info_t;
+
+fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar,
+					       fsl_shw_uco_t * uco);
+fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco);
+fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx);
+fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx);
+fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx,
+							fsl_shw_pco_t *capabilities);
+
+#endif				/* ADAPTOR_H */
+
+/* End of adaptor.h */
diff --git a/drivers/mxc/security/sahara2/include/diagnostic.h b/drivers/mxc/security/sahara2/include/diagnostic.h
new file mode 100644
index 000000000000..57f84d4cbb05
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/diagnostic.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file    diagnostic.h
+*
+* @brief   Macros for outputting kernel and user space diagnostics.
+*/
+
+#ifndef DIAGNOSTIC_H
+#define DIAGNOSTIC_H
+
+#ifndef __KERNEL__		/* linux flag */
+#include <stdio.h>
+#endif
+#include "fsl_platform.h"
+
+#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4)
+#define DEV_NAME "sahara"
+#elif defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) ||                     \
+      defined(FSL_HAVE_RNGC)
+#define DEV_NAME "shw"
+#endif
+
+/*!
+********************************************************************
+* @brief   This macro logs diagnostic messages to stderr.
+*
+* @param   diag  String that must be logged, char *.
+*
+* @return   void
+*
+*/
+//#if defined DIAG_SECURITY_FUNC || defined DIAG_ADAPTOR
+#define LOG_DIAG(diag)                                              \
+({                                                                  \
+    const char* fname = strrchr(__FILE__, '/');                           \
+                                                                    \
+     sah_Log_Diag(fname ? fname+1 : __FILE__, __LINE__, diag);     \
+})
+
+#ifdef __KERNEL__
+
+#define LOG_DIAG_ARGS(fmt, ...)                                               \
+({                                                                            \
+    const char* fname = strrchr(__FILE__, '/');                               \
+    os_printk(KERN_ALERT "%s:%i: " fmt "\n",                                  \
+              fname ? fname+1 : __FILE__,                                     \
+              __LINE__,                                                       \
+              __VA_ARGS__);                                                   \
+})
+
+#else
+
+#define LOG_DIAG_ARGS(fmt, ...)                                               \
+({                                                                            \
+    const char* fname = strrchr(__FILE__, '/');                               \
+    printf("%s:%i: " fmt "\n",                                                \
+           fname ? fname+1 : __FILE__,                                        \
+           __LINE__,                                                          \
+           __VA_ARGS__);                                                      \
+})
+
+#ifndef __KERNEL__
+void sah_Log_Diag(char *source_name, int source_line, char *diag);
+#endif
+#endif /* if define DIAG_SECURITY_FUNC ... */
+
+#ifdef __KERNEL__
+/*!
+********************************************************************
+* @brief   This macro logs kernel diagnostic  messages to the kernel
+*          log.
+*
+* @param   diag  String that must be logged, char *.
+*
+* @return  As for printf()
+*/
+#if 0
+#if defined(DIAG_DRV_IF) || defined(DIAG_DRV_QUEUE) ||                        \
+  defined(DIAG_DRV_STATUS) || defined(DIAG_DRV_INTERRUPT) ||                  \
+   defined(DIAG_MEM) || defined(DIAG_SECURITY_FUNC) || defined(DIAG_ADAPTOR)
+#endif
+#endif
+
+#define LOG_KDIAG_ARGS(fmt, ...)                                              \
+({                                                                            \
+    os_printk (KERN_ALERT "%s (%s:%i): " fmt "\n",                            \
+               DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, __VA_ARGS__);              \
+})
+
+#define LOG_KDIAG(diag)                                                       \
+    os_printk (KERN_ALERT "%s (%s:%i): %s\n",                             \
+               DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, diag);
+
+#define sah_Log_Diag(n, l, d)                                                 \
+    os_printk(KERN_ALERT "%s:%i: %s\n", n, l, d)
+
+#else				/* not KERNEL */
+
+#define sah_Log_Diag(n, l, d)                                                 \
+    printf("%s:%i: %s\n", n, l, d)
+
+#endif				/* __KERNEL__ */
+
+#endif				/* DIAGNOSTIC_H */
diff --git a/drivers/mxc/security/sahara2/include/fsl_platform.h b/drivers/mxc/security/sahara2/include/fsl_platform.h
new file mode 100644
index 000000000000..a8b9080fe2f9
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/fsl_platform.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file fsl_platform.h
+ *
+ * Header file to isolate code which might be platform-dependent
+ */
+
+#ifndef FSL_PLATFORM_H
+#define FSL_PLATFORM_H
+
+#ifdef __KERNEL__
+#include "portable_os.h"
+#endif
+
+#if defined(FSL_PLATFORM_OTHER)
+
+/* Have Makefile or other method of setting FSL_HAVE_* flags */
+
+#elif defined(CONFIG_ARCH_MX3)	/* i.MX31 */
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RTIC
+#define FSL_HAVE_RNGA
+
+#elif defined(CONFIG_ARCH_MX21)
+
+#define FSL_HAVE_HAC
+#define FSL_HAVE_RNGA
+#define FSL_HAVE_SCC
+
+#elif defined(CONFIG_ARCH_MX25)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGB
+#define FSL_HAVE_RTIC3
+#define FSL_HAVE_DRYICE
+
+#elif defined(CONFIG_ARCH_MX27)
+
+#define FSL_HAVE_SAHARA2
+#define SUBMIT_MULTIPLE_DARS
+#define FSL_HAVE_RTIC
+#define FSL_HAVE_SCC
+#define ALLOW_LLO_DESCRIPTORS
+
+#elif defined(CONFIG_ARCH_MX35)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGC
+#define FSL_HAVE_RTIC
+
+#elif defined(CONFIG_ARCH_MX37)
+
+#define FSL_HAVE_SCC2
+#define FSL_HAVE_RNGC
+#define FSL_HAVE_RTIC2
+#define FSL_HAVE_SRTC
+
+#elif defined(CONFIG_ARCH_MX5)
+
+#define FSL_HAVE_SCC2
+#define FSL_HAVE_SAHARA4
+#define FSL_HAVE_RTIC3
+#define FSL_HAVE_SRTC
+#define NO_RESEED_WORKAROUND
+#define NEED_CTR_WORKAROUND
+#define USE_S2_CCM_ENCRYPT_CHAIN
+#define USE_S2_CCM_DECRYPT_CHAIN
+#define ALLOW_LLO_DESCRIPTORS
+
+#elif defined(CONFIG_ARCH_MXC91131)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGC
+#define FSL_HAVE_HAC
+
+#elif defined(CONFIG_ARCH_MXC91221)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGC
+#define FSL_HAVE_RTIC2
+
+#elif defined(CONFIG_ARCH_MXC91231)
+
+#define FSL_HAVE_SAHARA2
+#define FSL_HAVE_RTIC
+#define FSL_HAVE_SCC
+#define NO_OUTPUT_1K_CROSSING
+
+#elif defined(CONFIG_ARCH_MXC91311)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGC
+
+#elif defined(CONFIG_ARCH_MXC91314)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_SAHAR4
+#define FSL_HAVE_RTIC3
+#define NO_RESEED_WORKAROUND
+#define NEED_CTR_WORKAROUND
+#define USE_S2_CCM_ENCRYPT_CHAIN
+#define USE_S2_CCM_DECRYPT_CHAIN
+#define ALLOW_LLO_DESCRIPTORS
+
+#elif defined(CONFIG_ARCH_MXC91321)
+
+#define FSL_HAVE_SAHARA2
+#define FSL_HAVE_RTIC
+#define FSL_HAVE_SCC
+#define SCC_CLOCK_NOT_GATED
+#define NO_OUTPUT_1K_CROSSING
+
+#elif defined(CONFIG_ARCH_MXC92323)
+
+#define FSL_HAVE_SCC2
+#define FSL_HAVE_SAHARA4
+#define FSL_HAVE_PKHA
+#define FSL_HAVE_RTIC2
+#define NO_1K_CROSSING
+#define NO_RESEED_WORKAROUND
+#define NEED_CTR_WORKAROUND
+#define USE_S2_CCM_ENCRYPT_CHAIN
+#define USE_S2_CCM_DECRYPT_CHAIN
+#define ALLOW_LLO_DESCRIPTORS
+
+
+#elif  defined(CONFIG_ARCH_MXC91331)
+
+#define FSL_HAVE_SCC
+#define FSL_HAVE_RNGA
+#define FSL_HAVE_HAC
+#define FSL_HAVE_RTIC
+
+#elif defined(CONFIG_8548)
+
+#define FSL_HAVE_SEC2x
+
+#elif defined(CONFIG_MPC8374)
+
+#define FSL_HAVE_SEC3x
+
+#else
+
+#error UNKNOWN_PLATFORM
+
+#endif				/* platform checks */
+
+#endif				/* FSL_PLATFORM_H */
diff --git a/drivers/mxc/security/sahara2/include/fsl_shw.h b/drivers/mxc/security/sahara2/include/fsl_shw.h
new file mode 100644
index 000000000000..8f0159bef71a
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/fsl_shw.h
@@ -0,0 +1,2515 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * NOTE TO MAINTAINERS: Although this header file is *the* header file to be
+ * #include'd by FSL SHW programs, it does not itself make any definitions for
+ * the API.  Instead, it uses the fsl_platform.h file and / or compiler
+ * environment variables to determine which actual driver header file to
+ * include.  This allows different implementations to contain different
+ * implementations of the various objects, macros, etc., or even to change
+ * which functions are macros and which are not.
+ */
+
+/*!
+ * @file fsl_shw.h
+ *
+ * @brief Definition of the Freescale Security Hardware API.
+ *
+ * See @ref index for an overview of the API.
+ */
+
+/*!
+ * @if USE_MAINPAGE
+ * @mainpage Common API for Freescale Security Hardware (FSL SHW API)
+ * @endif
+ *
+ * @section intro_sec Introduction
+ *
+ * This is the interface definition for the Freescale Security Hardware API
+ * (FSL SHW API) for User Mode and Kernel Mode to access Freescale Security
+ * Hardware components for cryptographic acceleration. The API is intended to
+ * provide cross-platform access to security hardware components of Freescale.
+ *
+ * This documentation has not been approved, and should not be taken to
+ * mean anything definite about future direction.
+ *
+ * Some example code is provided to give some idea of usage of this API.
+ *
+ * Note: This first version has been defined around the capabilities of the
+ * Sahara2 cryptographic accelerator, and may be expanded in the future to
+ * provide support for other platforms.  The Platform Capabilities Object is
+ * intended as a way to allow programs to adapt to different platforms.
+ *
+ * The i.MX25 is an example of a platform without a SAHARA but yet has
+ * capabilities supported by this API.  These include #fsl_shw_get_random() and
+ * #fsl_shw_add_entropy(), and the use of Triple-DES (TDEA) cipher algorithm
+ * (with no checking of key parity supported) in ECB and CBC modes with @ref
+ * sym_sec.  See also the @ref di_sec for information on key handling, and @ref
+ * td_sec for detection of Tamper Events.  Only the random functions are
+ * available from user space on this platform.
+ *
+ * @section usr_ctx The User Context
+ *
+ * The User Context Object (#fsl_shw_uco_t) controls the interaction between
+ * the user program and the API.  It is initialized as part of user
+ * registration (#fsl_shw_register_user()), and is part of every interaction
+ * thereafter.
+ *
+ * @section pf_sec Platform Capabilities
+ *
+ * Since this API is not tied to one specific type of hardware or even one
+ * given version of a given type of hardware, the platform capabilities object
+ * could be used by a portable program to make choices about using software
+ * instead of hardware for certain operations.
+ *
+ * See the #fsl_shw_pco_t, returned by #fsl_shw_get_capabilities().
+ *
+ * @ref pcoops are provided to query its contents.
+ *
+ *
+ * @section sym_sec Symmetric-Key Encryption and Decryption
+ *
+ * Symmetric-Key encryption support is provided for the block cipher algorithms
+ * AES, DES, and Triple DES.  Modes supported are #FSL_SYM_MODE_ECB,
+ * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR, though not necessarily all modes
+ * for all algorithms.  There is also support for the stream cipher algorithm
+ * commonly known as ARC4.
+ *
+ * Encryption and decryption are performed by using the functions
+ * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt(), respectively.
+ * There are two objects which provide information about the operation of these
+ * functions.  They are the #fsl_shw_sko_t, to provide key and algorithm
+ * information; and the #fsl_shw_scco_t, to provide (and store) initial context
+ * or counter value information.
+ *
+ * CCM is not supported by these functions.  For information CCM support, see
+ * @ref cmb_sec.
+ *
+ *
+ * @section hash_sec Cryptographic Hashing
+ *
+ * Hashing is performed by fsl_shw_hash(). Control of the function is through
+ * flags in the #fsl_shw_hco_t.  The algorithms which are
+ * supported are listed in #fsl_shw_hash_alg_t.
+ *
+ * The hashing function works on octet streams.  If a user application needs to
+ * hash a bitstream, it will need to do its own padding of the last block.
+ *
+ *
+ * @section hmac_sec Hashed Message Authentication Codes
+ *
+ * An HMAC is a method of combining a hash and a key so that a message cannot
+ * be faked by a third party.
+ *
+ * The #fsl_shw_hmac() can be used by itself for one-shot or multi-step
+ * operations, or in combination with #fsl_shw_hmac_precompute() to provide the
+ * ability to compute and save the beginning hashes from a key one time, and
+ * then use #fsl_shw_hmac() to calculate an HMAC on each message as it is
+ * processed.
+ *
+ * The maximum key length which is directly supported by this API is 64 octets.
+ * If a longer key size is needed for HMAC, the user will have to hash the key
+ * and present the digest value as the key to be used by the HMAC functions.
+ *
+ *
+ * @section rnd_sec Random Numbers
+ *
+ * Support is available for acquiring random values from a
+ * cryptographically-strong random number generator.  See
+ * #fsl_shw_get_random().  The function #fsl_shw_add_entropy() may be used to
+ * add entropy to the random number generator.
+ *
+ *
+ * @section cmb_sec Combined Cipher and Authentication
+ *
+ * Some schemes require that messages be encrypted and that they also have an
+ * authentication code associated with the message. The function
+ * #fsl_shw_gen_encrypt() will generate the authentication code and encrypt the
+ * message.
+ *
+ * Upon receipt of such a message, the message must be decrypted and the
+ * authentication code validated.  The function
+ * #fsl_shw_auth_decrypt() will perform these steps.
+ *
+ * Only AES-CCM is supported.
+ *
+ *
+ * @section wrap_sec Wrapped Keys
+ *
+ * On platforms with a Secure Memory, the function #fsl_shw_establish_key() can
+ * be used to place a key into the System Keystore.  This key then can be used
+ * directly by the cryptographic hardware.  It later then be wrapped
+ * (cryptographically obscured) by #fsl_shw_extract_key() and stored for later
+ * use.  If a software key (#FSL_SKO_KEY_SW_KEY) was established, then its
+ * value can be retrieved with a call to #fsl_shw_read_key().
+ *
+ * The wrapping and unwrapping functions provide security against unauthorized
+ * use and detection of tampering.
+ *
+ * The functions can also be used with a User Keystore.
+ *
+ * @section smalloc_sec Secure Memory Allocation
+ *
+ * On platforms with multiple partitions of Secure Memory, the function
+ * #fsl_shw_smalloc() can be used to acquire a partition for private use.  The
+ * function #fsl_shw_diminish_perms() can then be used to revoke specific
+ * permissions on the partition, and #fsl_shw_sfree() can be used to release the
+ * partition.
+ *
+ * @section keystore_sec User Keystore
+ *
+ * User Keystore functionality is defined in fsl_shw_keystore.h.  See @ref
+ * user_keystore for details.  This is not supported on platforms without SCC2.
+ *
+ * @section di_sec Hardware key-select extensions - DryIce
+ *
+ * Some platforms have a component called DryIce which allows the software to
+ * control which key will be used by the secure memory encryption hardware.
+ * The choices are the secret per-chip Fused (IIM) Key, an unknown, hardware-
+ * generated Random Key, a software-written Programmed Key, or the IIM Key in
+ * combination with one of the others.  #fsl_shw_pco_check_pk_supported() can
+ * be used to determine whether this feature is available on the platform.
+ * The rest of this section will explain the symmetric ciphering and key
+ * operations which are available on such a platform.
+ *
+ * The function #fsl_shw_sko_init_pf_key() will set up a Secret Key Object to
+ * refer to one of the system's platform keys.  All keys which reference a
+ * platform key must use this initialization function, including a user-
+ * provided key value.  Keys which are intended for software encryption must
+ * use #fsl_shw_sko_init().
+ *
+ * To change the setting of the Programmed Key of the DryIce module,
+ * #fsl_shw_establish_key() must be called with a platform key object of type
+ * #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG.  The key will be go
+ * into the PK register of DryIce and not to the keystore.  Any symmetric
+ * operation which references either #FSL_SHW_PF_KEY_PRG or
+ * #FSL_SHW_PF_KEY_IIM_PRG will use the current PK value (possibly modified by
+ * the secret fused IIM key).  Before the Flatform Key can be changed, a call to
+ * #fsl_shw_release_key() or #fsl_shw_extract_key() must be made.  Neither
+ * function will change the value in the PK registers, and further ciphering
+ * can take place.
+ *
+ * When #fsl_shw_establish_key() is called to change the PK value, a plaintext
+ * key can be passed in with the #FSL_KEY_WRAP_ACCEPT argument or a previously
+ * wrapped key can be passed in with the #FSL_KEY_WRAP_UNWRAP argument.  If
+ * #FSL_KEY_WRAP_CREATE is passed in, then a random value will be loaded into
+ * the PK register.  The PK value can be wrapped by a call to
+ * #fsl_shw_extract_key() for later use with the #FSL_KEY_WRAP_UNWRAP argument.
+ *
+ * As an alternative to using only the fused key for @ref wrap_sec,
+ * #fsl_shw_uco_set_wrap_key() can be used to select either the random key or
+ * the random key with the fused key as the key which will be used to protect
+ * the one-time value used to wrap the key.  This allows for these
+ * wrapped keys to be dependent upon and therefore unrecoverable after a tamper
+ * event causes the erasure of the DryIce Random Key register.
+ *
+ * The software can request that the hardware generate a (new) Random Key for
+ * DryIce by calling #fsl_shw_gen_random_pf_key().
+ *
+ *
+ * @section td_sec Device Tamper-Detection
+ *
+ * Some platforms have a component which can detect certain types of tampering
+ * with the hardware.  #fsl_shw_read_tamper_event() API will allow the
+ * retrieval of the type of event which caused a tamper-detection failure.
+ *
+ */
+
+/*! @defgroup glossary Glossary
+ *
+ * @li @b AES - Advanced Encryption Standard - An NIST-created block cipher
+ *          originally knowns as Rijndael.
+ * @li @b ARC4 - ARCFOUR - An S-Box-based OFB mode stream cipher.
+ * @li @b CBC - Cipher-Block Chaining - Each encrypted block is XORed with the
+ *          result of the previous block's encryption.
+ * @li @b CCM - A way of combining CBC and CTR to perform cipher and
+ *        authentication.
+ * @li @b ciphertext - @a plaintext which has been encrypted in some fashion.
+ * @li @b context - Information on the state of a cryptographic operation,
+ *        excluding any key.  This could include IV, Counter Value, or SBox.
+ * @li @b CTR - A mode where a counter value is encrypted and then XORed with
+ *        the data.  After each block, the counter value is incremented.
+ * @li @b DES - Data Encryption Standard - An 8-octet-block cipher.
+ * @li @b ECB - Electronic Codebook - A straight encryption/decryption of the
+ *        data.
+ * @li @b hash - A cryptographically strong one-way function performed on data.
+ * @li @b HMAC - Hashed Message Authentication Code - A key-dependent one-way
+ *        hash result, used to verify authenticity of a message.  The equation
+ *        for an HMAC is hash((K + A) || hash((K + B) || msg)), where K is the
+ *        key, A is the constant for the outer hash, B is the constant for the
+ *        inner hash, and hash is the hashing function (MD5, SHA256, etc).
+ * @li @b IPAD - In an HMAC operation, the context generated by XORing the key
+ *        with a constant and then hashing that value as the first block of the
+ *        inner hash.
+ * @li @b IV - An "Initial Vector" or @a context for modes like CBC.
+ * @li @b MAC - A Message Authentication Code.  HMAC, hashing, and CCM all
+ *        produce a MAC.
+ * @li @b mode  - A way of using a cryptographic algorithm.  See ECB, CBC, etc.
+ * @li @b MD5 - Message Digest 5 - A one-way hash function.
+ * @li @b plaintext - Data which has not been encrypted, or has been decrypted
+ *        from @a ciphertext.
+ * @li @b OPAD - In an HMAC operation, the context generated by XORing the key
+ *        with a constant and then hashing that value as the first block of the
+ *        outer hash.
+ * @li @b SHA - Secure Hash Algorithm - A one-way hash function.
+ * @li @b TDES - AKA @b 3DES - Triple Data Encryption Standard - A method of
+ *        using two or three keys and DES to perform three operations (encrypt
+ *        decrypt encrypt) to create a new algorithm.
+ * @li @b XOR - Exclusive-OR.  A Boolean arithmetic function.
+ * @li @b Wrapped value - A (key) which has been encrypted into an opaque datum
+ *        which cannot be unwrapped (decrypted) for use except by an authorized
+ *        user.  Once created, the key is never visible, but may be used for
+ *        other cryptographic operations.
+ */
+
+#ifndef FSL_SHW_H
+#define FSL_SHW_H
+
+/* Set FSL_HAVE_* flags */
+
+#include "fsl_platform.h"
+
+#ifndef API_DOC
+
+#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4)
+
+#include "sahara.h"
+
+#else
+
+#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC)
+
+#include "rng_driver.h"
+
+#else
+
+#error FSL_SHW_API_platform_not_recognized
+
+#endif
+
+#endif				/* HAVE SAHARA */
+
+#else				/* API_DOC */
+
+#include <inttypes.h>		/* for uint32_t, etc. */
+#include <stdio.h>		/* Mainly for definition of NULL !! */
+
+/* These groups will appear in the order in which they are defined. */
+
+/*!
+ * @defgroup strgrp Objects
+ *
+ * These objects are used to pass information into and out of the API.  Through
+ * flags and other settings, they control the behavior of the @ref opfuns.
+ *
+ * They are manipulated and queried by use of the various access functions.
+ * There are different sets defined for each object.  See @ref objman.
+ */
+
+/*!
+ * @defgroup consgrp Enumerations and other Constants
+ *
+ * This collection of symbols comprise the values which can be passed into
+ * various functions to control how the API will work.
+ */
+
+/*! @defgroup opfuns Operational Functions
+ *
+ * These functions request that the underlying hardware perform cryptographic
+ * operations.  They are the heart of the API.
+ */
+
+/******  Organization the Object Operations under one group ! **********/
+/*! @defgroup objman Object-Manipulation Operations
+ *
+ */
+/*! @addtogroup objman
+    @{ */
+/*!
+ * @defgroup pcoops Platform Context Object Operations
+ *
+ * The Platform Context object is "read-only", so only query operations are
+ * provided for it.  It is returned by the #fsl_shw_get_capabilities()
+ * function.
+ */
+
+/*! @defgroup ucoops User Context Operations
+ *
+ * These operations should be the only access to the #fsl_shw_uco_t
+ * type/struct, as the internal members of the object are subject to change.
+ * The #fsl_shw_uco_init() function must be called before any other use of the
+ * object.
+ */
+
+/*!
+ * @defgroup rops Result Object Operations
+ *
+ * As the Result Object contains the result of one of the @ref opfuns.  The
+ * manipulations provided are query-only.  No initialization is needed for this
+ * object.
+ */
+
+/*!
+ * @defgroup skoops Secret Key Object Operations
+ *
+ * These operations should be the only access to the #fsl_shw_sko_t
+ * type/struct, as the internal members of that object are subject to change.
+ */
+
+/*!
+ * @defgroup ksoops Keystore Object Operations
+ *
+ * These operations should be the only access to the #fsl_shw_kso_t
+ * type/struct, as the internal members of that object are subject to change.
+ */
+
+/*!
+ * @defgroup hcops Hash Context Object Operations
+ *
+ * These operations should be the only access to the #fsl_shw_hco_t
+ * type/struct, as the internal members of that object are subject to change.
+ */
+
+/*!
+ * @defgroup hmcops HMAC Context Object Operations
+ *
+ * These operations should be the only access to the #fsl_shw_hmco_t
+ * type/struct, as the internal members of that object are subject to change.
+ */
+
+/*!
+ * @defgroup sccops Symmetric Cipher Context Operations
+ *
+ * These operations should be the only access to the #fsl_shw_scco_t
+ * type/struct, as the internal members of that object are subject to change
+ */
+
+/*! @defgroup accoops Authentication-Cipher Context Object Operations
+ *
+ * These functions operate on a #fsl_shw_acco_t.  Their purpose is to set
+ * flags, fields, etc., in order to control the operation of
+ * #fsl_shw_gen_encrypt() and #fsl_shw_auth_decrypt().
+ */
+
+	 /* @} *//************ END GROUPING of Object Manipulations *****************/
+
+/*! @defgroup miscfuns Miscellaneous Functions
+ *
+ * These functions are neither @ref opfuns nor @ref objman.  Their behavior
+ * does not depend upon the flags in the #fsl_shw_uco_t, yet they may involve
+ * more interaction with the library and the kernel than simply querying an
+ * object.
+ */
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+/*! @addtogroup consgrp
+    @{ */
+
+/*!
+ * Flags for the state of the User Context Object (#fsl_shw_uco_t).
+ *
+ * These flags describe how the @ref opfuns will operate.
+ */
+typedef enum fsl_shw_user_ctx_flags_t {
+	/*!
+	 * API will block the caller until operation completes.  The result will be
+	 * available in the return code.  If this is not set, user will have to get
+	 * results using #fsl_shw_get_results().
+	 */
+	FSL_UCO_BLOCKING_MODE,
+	/*!
+	 * User wants callback (at the function specified with
+	 * #fsl_shw_uco_set_callback()) when the operation completes.  This flag is
+	 * valid only if #FSL_UCO_BLOCKING_MODE is not set.
+	 */
+	FSL_UCO_CALLBACK_MODE,
+	/*! Do not free descriptor chain after driver (adaptor) finishes */
+	FSL_UCO_SAVE_DESC_CHAIN,
+	/*!
+	 * User has made at least one request with callbacks requested, so API is
+	 * ready to handle others.
+	 */
+	FSL_UCO_CALLBACK_SETUP_COMPLETE,
+	/*!
+	 * (virtual) pointer to descriptor chain is completely linked with physical
+	 * (DMA) addresses, ready for the hardware.  This flag should not be used
+	 * by FSL SHW API programs.
+	 */
+	FSL_UCO_CHAIN_PREPHYSICALIZED,
+	/*!
+	 * The user has changed the context but the changes have not been copied to
+	 * the kernel driver.
+	 */
+	FSL_UCO_CONTEXT_CHANGED,
+	/*! Internal Use.  This context belongs to a user-mode API user. */
+	FSL_UCO_USERMODE_USER,
+} fsl_shw_user_ctx_flags_t;
+
+/*!
+ * Return code for FSL_SHW library.
+ *
+ * These codes may be returned from a function call.  In non-blocking mode,
+ * they will appear as the status in a Result Object.
+ */
+typedef enum fsl_shw_return_t {
+	/*!
+	 * No error.  As a function return code in Non-blocking mode, this may
+	 * simply mean that the operation was accepted for eventual execution.
+	 */
+	FSL_RETURN_OK_S = 0,
+	/*! Failure for non-specific reason. */
+	FSL_RETURN_ERROR_S,
+	/*!
+	 * Operation failed because some resource was not able to be allocated.
+	 */
+	FSL_RETURN_NO_RESOURCE_S,
+	/*! Crypto algorithm unrecognized or improper. */
+	FSL_RETURN_BAD_ALGORITHM_S,
+	/*! Crypto mode unrecognized or improper. */
+	FSL_RETURN_BAD_MODE_S,
+	/*! Flag setting unrecognized or inconsistent. */
+	FSL_RETURN_BAD_FLAG_S,
+	/*! Improper or unsupported key length for algorithm. */
+	FSL_RETURN_BAD_KEY_LENGTH_S,
+	/*! Improper parity in a (DES, TDES) key. */
+	FSL_RETURN_BAD_KEY_PARITY_S,
+	/*!
+	 * Improper or unsupported data length for algorithm or internal buffer.
+	 */
+	FSL_RETURN_BAD_DATA_LENGTH_S,
+	/*! Authentication / Integrity Check code check failed. */
+	FSL_RETURN_AUTH_FAILED_S,
+	/*! A memory error occurred. */
+	FSL_RETURN_MEMORY_ERROR_S,
+	/*! An error internal to the hardware occurred. */
+	FSL_RETURN_INTERNAL_ERROR_S,
+	/*! ECC detected Point at Infinity */
+	FSL_RETURN_POINT_AT_INFINITY_S,
+	/*! ECC detected No Point at Infinity */
+	FSL_RETURN_POINT_NOT_AT_INFINITY_S,
+	/*! GCD is One */
+	FSL_RETURN_GCD_IS_ONE_S,
+	/*! GCD is not One */
+	FSL_RETURN_GCD_IS_NOT_ONE_S,
+	/*! Candidate is Prime */
+	FSL_RETURN_PRIME_S,
+	/*! Candidate is not Prime */
+	FSL_RETURN_NOT_PRIME_S,
+	/*! N register loaded improperly with even value */
+	FSL_RETURN_EVEN_MODULUS_ERROR_S,
+	/*! Divisor is zero. */
+	FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S,
+	/*! Bad Exponent or Scalar value for Point Multiply */
+	FSL_RETURN_BAD_EXPONENT_ERROR_S,
+	/*! RNG hardware problem. */
+	FSL_RETURN_OSCILLATOR_ERROR_S,
+	/*! RNG hardware problem. */
+	FSL_RETURN_STATISTICS_ERROR_S,
+} fsl_shw_return_t;
+
+/*!
+ * Algorithm Identifier.
+ *
+ * Selection of algorithm will determine how large the block size of the
+ * algorithm is.   Context size is the same length unless otherwise specified.
+ * Selection of algorithm also affects the allowable key length.
+ */
+typedef enum fsl_shw_key_alg_t {
+	FSL_KEY_ALG_HMAC,	/*!< Key will be used to perform an HMAC.  Key
+				   size is 1 to 64 octets.  Block size is 64
+				   octets. */
+	FSL_KEY_ALG_AES,	/*!< Advanced Encryption Standard (Rijndael).
+				   Block size is 16 octets.  Key size is 16
+				   octets.  (The single choice of key size is a
+				   Sahara platform limitation.) */
+	FSL_KEY_ALG_DES,	/*!< Data Encryption Standard.  Block size is
+				   8 octets.  Key size is 8 octets. */
+	FSL_KEY_ALG_TDES,	/*!< 2- or 3-key Triple DES.  Block size is 8
+				   octets.  Key size is 16 octets for 2-key
+				   Triple DES, and 24 octets for 3-key. */
+	FSL_KEY_ALG_ARC4	/*!< ARC4.  No block size.  Context size is 259
+				   octets.  Allowed key size is 1-16 octets.
+				   (The choices for key size are a Sahara
+				   platform limitation.) */
+} fsl_shw_key_alg_t;
+
+/*!
+ * Mode selector for Symmetric Ciphers.
+ *
+ * The selection of mode determines how a cryptographic algorithm will be
+ * used to process the plaintext or ciphertext.
+ *
+ * For all modes which are run block-by-block (that is, all but
+ * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text
+ * length which is multiple of the block size.  Except for #FSL_SYM_MODE_CTR,
+ * these block-by-block algorithms must also be passed a total number of octets
+ * which is a multiple of the block size.
+ *
+ * In modes which require that the total number of octets of data be a multiple
+ * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user
+ * has a total number of octets which are not a multiple of the block size, the
+ * user must perform any necessary padding to get to the correct data length.
+ */
+typedef enum fsl_shw_sym_mode_t {
+	/*!
+	 * Stream.  There is no associated block size.  Any request to process data
+	 * may be of any length.  This mode is only for ARC4 operations, and is
+	 * also the only mode used for ARC4.
+	 */
+	FSL_SYM_MODE_STREAM,
+
+	/*!
+	 * Electronic Codebook.  Each block of data is encrypted/decrypted.  The
+	 * length of the data stream must be a multiple of the block size.  This
+	 * mode may be used for DES, 3DES, and AES.  The block size is determined
+	 * by the algorithm.
+	 */
+	FSL_SYM_MODE_ECB,
+	/*!
+	 * Cipher-Block Chaining.  Each block of data is encrypted/decrypted and
+	 * then "chained" with the previous block by an XOR function.  Requires
+	 * context to start the XOR (previous block).  This mode may be used for
+	 * DES, 3DES, and AES.  The block size is determined by the algorithm.
+	 */
+	FSL_SYM_MODE_CBC,
+	/*!
+	 * Counter.  The counter is encrypted, then XORed with a block of data.
+	 * The counter is then incremented (using modulus arithmetic) for the next
+	 * block. The final operation may be non-multiple of block size.  This mode
+	 * may be used for AES.  The block size is determined by the algorithm.
+	 */
+	FSL_SYM_MODE_CTR,
+} fsl_shw_sym_mode_t;
+
+/*!
+ * Algorithm selector for Cryptographic Hash functions.
+ *
+ * Selection of algorithm determines how large the context and digest will be.
+ * Context is the same size as the digest (resulting hash), unless otherwise
+ * specified.
+ */
+typedef enum fsl_shw_hash_alg_t {
+	FSL_HASH_ALG_MD5,	/*!< MD5 algorithm.  Digest is 16 octets. */
+	FSL_HASH_ALG_SHA1,	/*!< SHA-1 (aka SHA or SHA-160) algorithm.
+				   Digest is 20 octets. */
+	FSL_HASH_ALG_SHA224,	/*!< SHA-224 algorithm.  Digest is 28 octets,
+				   though context is 32 octets. */
+	FSL_HASH_ALG_SHA256	/*!< SHA-256 algorithm.  Digest is 32
+				   octets. */
+} fsl_shw_hash_alg_t;
+
+/*!
+ * The type of Authentication-Cipher function which will be performed.
+ */
+typedef enum fsl_shw_acc_mode_t {
+	/*!
+	 * CBC-MAC for Counter.  Requires context and modulus.  Final operation may
+	 * be non-multiple of block size.  This mode may be used for AES.
+	 */
+	FSL_ACC_MODE_CCM,
+	/*!
+	 * SSL mode.  Not supported.  Combines HMAC and encrypt (or decrypt).
+	 * Needs one key object for encryption, another for the HMAC.  The usual
+	 * hashing and symmetric encryption algorithms are supported.
+	 */
+	FSL_ACC_MODE_SSL,
+} fsl_shw_acc_mode_t;
+
+/*!
+ * The operation which controls the behavior of #fsl_shw_establish_key().
+ *
+ * These values are passed to #fsl_shw_establish_key().
+ */
+typedef enum fsl_shw_key_wrap_t {
+	FSL_KEY_WRAP_CREATE,	/*!< Generate a key from random values. */
+	FSL_KEY_WRAP_ACCEPT,	/*!< Use the provided clear key. */
+	FSL_KEY_WRAP_UNWRAP	/*!< Unwrap a previously wrapped key. */
+} fsl_shw_key_wrap_t;
+
+/* REQ-S2LRD-PINTFC-COA-HCO-001 */
+/*!
+ * Flags which control a Hash operation.
+ *
+ *  These may be combined by ORing them together.  See #fsl_shw_hco_set_flags()
+ * and #fsl_shw_hco_clear_flags().
+ */
+typedef enum fsl_shw_hash_ctx_flags_t {
+	FSL_HASH_FLAGS_INIT = 1,	/*!< Context is empty.  Hash is started
+					   from scratch, with a message-processed
+					   count of zero. */
+	FSL_HASH_FLAGS_SAVE = 2,	/*!< Retrieve context from hardware after
+					   hashing.  If used with the
+					   #FSL_HASH_FLAGS_FINALIZE flag, the final
+					   digest value will be saved in the
+					   object. */
+	FSL_HASH_FLAGS_LOAD = 4,	/*!< Place context into hardware before
+					   hashing. */
+	FSL_HASH_FLAGS_FINALIZE = 8,	/*!< PAD message and perform final digest
+					   operation.  If user message is
+					   pre-padded, this flag should not be
+					   used. */
+} fsl_shw_hash_ctx_flags_t;
+
+/*!
+ * Flags which control an HMAC operation.
+ *
+ * These may be combined by ORing them together.  See #fsl_shw_hmco_set_flags()
+ * and #fsl_shw_hmco_clear_flags().
+ */
+typedef enum fsl_shw_hmac_ctx_flags_t {
+	FSL_HMAC_FLAGS_INIT = 1,	/*!< Message context is empty.  HMAC is
+					   started from scratch (with key) or from
+					   precompute of inner hash, depending on
+					   whether
+					   #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is
+					   set. */
+	FSL_HMAC_FLAGS_SAVE = 2,	/*!< Retrieve ongoing context from hardware
+					   after hashing.  If used with the
+					   #FSL_HMAC_FLAGS_FINALIZE flag, the final
+					   digest value (HMAC) will be saved in the
+					   object. */
+	FSL_HMAC_FLAGS_LOAD = 4,	/*!< Place ongoing context into hardware
+					   before hashing. */
+	FSL_HMAC_FLAGS_FINALIZE = 8,	/*!< PAD message and perform final HMAC
+					   operations of inner and outer hashes. */
+	FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16	/*!< This means that the context
+						   contains precomputed inner and outer
+						   hash values. */
+} fsl_shw_hmac_ctx_flags_t;
+
+/*!
+ * Flags to control use of the #fsl_shw_scco_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags()
+ */
+typedef enum fsl_shw_sym_ctx_flags_t {
+	/*!
+	 * Context is empty.  In ARC4, this means that the S-Box needs to be
+	 * generated from the key.  In #FSL_SYM_MODE_CBC mode, this allows an IV of
+	 * zero to be specified.  In #FSL_SYM_MODE_CTR mode, it means that an
+	 * initial CTR value of zero is desired.
+	 */
+	FSL_SYM_CTX_INIT = 1,
+	/*!
+	 * Load context from object into hardware before running cipher.  In
+	 * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+	 */
+	FSL_SYM_CTX_LOAD = 2,
+	/*!
+	 * Save context from hardware into object after running cipher.  In
+	 * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+	 */
+	FSL_SYM_CTX_SAVE = 4,
+	/*!
+	 * Context (SBox) is to be unwrapped and wrapped on each use.
+	 * This flag is unsupported.
+	 * */
+	FSL_SYM_CTX_PROTECT = 8,
+} fsl_shw_sym_ctx_flags_t;
+
+/*!
+ * Flags which describe the state of the #fsl_shw_sko_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags()
+ */
+typedef enum fsl_shw_key_flags_t {
+	FSL_SKO_KEY_IGNORE_PARITY = 1,	/*!< If algorithm is DES or 3DES, do not
+					   validate the key parity bits. */
+	FSL_SKO_KEY_PRESENT = 2,	/*!< Clear key is present in the object. */
+	FSL_SKO_KEY_ESTABLISHED = 4,	/*!< Key has been established for use.  This
+					   feature is not available for all
+					   platforms, nor for all algorithms and
+					   modes. */
+	FSL_SKO_KEY_SW_KEY = 8,	/*!< This key is for software use, and can
+				   be copied out of a keystore by its owner.
+				   The default is that they key is available
+				   only for hardware (or security driver)
+				   use. */
+} fsl_shw_key_flags_t;
+
+/*!
+ * Type of value which is associated with an established key.
+ */
+typedef uint64_t key_userid_t;
+
+/*!
+ * Flags which describe the state of the #fsl_shw_acco_t.
+ *
+ * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used
+ * together, provide for a one-shot operation.
+ */
+typedef enum fsl_shw_auth_ctx_flags_t {
+	FSL_ACCO_CTX_INIT = 1,	/*!< Initialize Context(s) */
+	FSL_ACCO_CTX_LOAD = 2,	/*!< Load intermediate context(s).
+				   This flag is unsupported. */
+	FSL_ACCO_CTX_SAVE = 4,	/*!< Save intermediate context(s).
+				   This flag is unsupported. */
+	FSL_ACCO_CTX_FINALIZE = 8,	/*!< Create MAC during this operation. */
+	FSL_ACCO_NIST_CCM = 16,	/*!< Formatting of CCM input data is
+				   performed by calls to
+				   #fsl_shw_ccm_nist_format_ctr_and_iv() and
+				   #fsl_shw_ccm_nist_update_ctr_and_iv().  */
+} fsl_shw_auth_ctx_flags_t;
+
+/*!
+ *  Modulus Selector for CTR modes.
+ *
+ * The incrementing of the Counter value may be modified by a modulus.  If no
+ * modulus is needed or desired for AES, use #FSL_CTR_MOD_128.
+ */
+typedef enum fsl_shw_ctr_mod_t {
+	FSL_CTR_MOD_8,		/*!< Run counter with modulus of 2^8. */
+	FSL_CTR_MOD_16,		/*!< Run counter with modulus of 2^16. */
+	FSL_CTR_MOD_24,		/*!< Run counter with modulus of 2^24. */
+	FSL_CTR_MOD_32,		/*!< Run counter with modulus of 2^32. */
+	FSL_CTR_MOD_40,		/*!< Run counter with modulus of 2^40. */
+	FSL_CTR_MOD_48,		/*!< Run counter with modulus of 2^48. */
+	FSL_CTR_MOD_56,		/*!< Run counter with modulus of 2^56. */
+	FSL_CTR_MOD_64,		/*!< Run counter with modulus of 2^64. */
+	FSL_CTR_MOD_72,		/*!< Run counter with modulus of 2^72. */
+	FSL_CTR_MOD_80,		/*!< Run counter with modulus of 2^80. */
+	FSL_CTR_MOD_88,		/*!< Run counter with modulus of 2^88. */
+	FSL_CTR_MOD_96,		/*!< Run counter with modulus of 2^96. */
+	FSL_CTR_MOD_104,	/*!< Run counter with modulus of 2^104. */
+	FSL_CTR_MOD_112,	/*!< Run counter with modulus of 2^112. */
+	FSL_CTR_MOD_120,	/*!< Run counter with modulus of 2^120. */
+	FSL_CTR_MOD_128		/*!< Run counter with modulus of 2^128. */
+} fsl_shw_ctr_mod_t;
+
+/*!
+ * Permissions flags for Secure Partitions
+ *
+ * They currently map directly to the SCC2 hardware values, but this is not
+ * guarinteed behavior.
+ */
+typedef enum fsl_shw_permission_t {
+/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */
+	FSL_PERM_NO_ZEROIZE,
+/*! SCM Access Permission: Enforce trusted key read in  */
+	FSL_PERM_TRUSTED_KEY_READ,
+/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */
+	FSL_PERM_HD_S,
+/*! SCM Access Permission: Allow Read Access to  Host Domain */
+	FSL_PERM_HD_R,
+/*! SCM Access Permission: Allow Write Access to  Host Domain */
+	FSL_PERM_HD_W,
+/*! SCM Access Permission: Allow Execute Access to  Host Domain */
+	FSL_PERM_HD_X,
+/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */
+	FSL_PERM_TH_R,
+/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */
+	FSL_PERM_TH_W,
+/*! SCM Access Permission: Allow Read Access to Other/World Domain */
+	FSL_PERM_OT_R,
+/*! SCM Access Permission: Allow Write Access to Other/World Domain */
+	FSL_PERM_OT_W,
+/*! SCM Access Permission: Allow Execute Access to Other/World Domain */
+	FSL_PERM_OT_X,
+} fsl_shw_permission_t;
+
+/*!
+ * Select the cypher mode to use for partition cover/uncover operations.
+ *
+ * They currently map directly to the values used in the SCC2 driver, but this
+ * is not guarinteed behavior.
+ */
+typedef enum fsl_shw_cypher_mode_t {
+	FSL_SHW_CYPHER_MODE_ECB,	/*!< ECB mode */
+	FSL_SHW_CYPHER_MODE_CBC,	/*!< CBC mode */
+} fsl_shw_cypher_mode_t;
+
+/*!
+ * Which platform key should be presented for cryptographic use.
+ */
+typedef enum fsl_shw_pf_key_t {
+	FSL_SHW_PF_KEY_IIM,	/*!< Present fused IIM key */
+	FSL_SHW_PF_KEY_PRG,	/*!< Present Program key */
+	FSL_SHW_PF_KEY_IIM_PRG,	/*!< Present IIM ^ Program key */
+	FSL_SHW_PF_KEY_IIM_RND,	/*!< Present Random key */
+	FSL_SHW_PF_KEY_RND,	/*!< Present IIM ^ Random key */
+} fsl_shw_pf_key_t;
+
+/*!
+ * The various security tamper events
+ */
+typedef enum fsl_shw_tamper_t {
+	FSL_SHW_TAMPER_NONE,	/*!< No error detected */
+	FSL_SHW_TAMPER_WTD,	/*!< wire-mesh tampering det */
+	FSL_SHW_TAMPER_ETBD,	/*!< ext tampering det: input B */
+	FSL_SHW_TAMPER_ETAD,	/*!< ext tampering det: input A */
+	FSL_SHW_TAMPER_EBD,	/*!< external boot detected */
+	FSL_SHW_TAMPER_SAD,	/*!< security alarm detected */
+	FSL_SHW_TAMPER_TTD,	/*!< temperature tampering det */
+	FSL_SHW_TAMPER_CTD,	/*!< clock tampering det */
+	FSL_SHW_TAMPER_VTD,	/*!< voltage tampering det */
+	FSL_SHW_TAMPER_MCO,	/*!< monotonic counter overflow */
+	FSL_SHW_TAMPER_TCO,	/*!< time counter overflow */
+} fsl_shw_tamper_t;
+
+/*! @} *//* consgrp */
+
+/******************************************************************************
+ * Data Structures
+ *****************************************************************************/
+/*! @addtogroup strgrp
+    @{ */
+
+/* REQ-S2LRD-PINTFC-COA-IBO-001 */
+/*!
+ * Application Initialization Object
+ *
+ * This object, the operations on it, and its interaction with the driver are
+ * TBD.
+ */
+typedef struct fsl_sho_ibo_t {
+} fsl_sho_ibo_t;
+
+/* REQ-S2LRD-PINTFC-COA-UCO-001 */
+/*!
+ * User Context Object
+ *
+ * This object must be initialized by a call to #fsl_shw_uco_init().  It must
+ * then be passed to #fsl_shw_register_user() before it can be used in any
+ * calls besides those in @ref ucoops.
+ *
+ * It contains the user's configuration for the API, for instance whether an
+ * operation should block, or instead should call back the user upon completion
+ * of the operation.
+ *
+ * See @ref ucoops for further information.
+ */
+typedef struct fsl_shw_uco_t {	/* fsl_shw_user_context_object */
+} fsl_shw_uco_t;
+
+/* REQ-S2LRD-PINTFC-API-GEN-006  ??  */
+/*!
+ * Result Object
+ *
+ * This object will contain success and failure information about a specific
+ * cryptographic request which has been made.
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref rops.
+ */
+typedef struct fsl_shw_result_t {	/* fsl_shw_result */
+} fsl_shw_result_t;
+
+/*!
+ * Keystore Object
+ *
+ * This object holds the context of a user keystore, including the functions
+ * that define the interface and pointers to where the key data is stored.  The
+ * user must supply a set of functions to handle keystore management, including
+ * slot allocation, deallocation, etc.  A default keystore manager is provided
+ * as part of the API.
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref ksoops.
+ */
+typedef struct fsl_shw_kso_t {	/* fsl_shw_keystore_object */
+} fsl_shw_kso_t;
+
+/* REQ-S2LRD-PINTFC-COA-SKO-001 */
+/*!
+ * Secret Key Object
+ *
+ * This object contains a key for a cryptographic operation, and information
+ * about its current state, its intended usage, etc.  It may instead contain
+ * information about a protected key, or an indication to use a platform-
+ * specific secret key.
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref skoops.
+ */
+typedef struct fsl_shw_sko_t {	/* fsl_shw_secret_key_object */
+} fsl_shw_sko_t;
+
+/* REQ-S2LRD-PINTFC-COA-CO-001 */
+/*!
+ * Platform Capabilities Object
+ *
+ * This object will contain information about the cryptographic features of the
+ * platform which the program is running on.
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.
+ *
+ * See @ref pcoops.
+ */
+typedef struct fsl_shw_pco_t {	/* fsl_shw_platform_capabilities_object */
+} fsl_shw_pco_t;
+
+/* REQ-S2LRD-PINTFC-COA-HCO-001 */
+/*!
+ * Hash Context Object
+ *
+ * This object contains information to control hashing functions.
+
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref hcops.
+ */
+typedef struct fsl_shw_hco_t {	/* fsl_shw_hash_context_object */
+} fsl_shw_hco_t;
+
+/*!
+ * HMAC Context Object
+ *
+ * This object contains information to control HMAC functions.
+
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref hmcops.
+ */
+typedef struct fsl_shw_hmco_t {	/* fsl_shw_hmac_context_object */
+} fsl_shw_hmco_t;
+
+/* REQ-S2LRD-PINTFC-COA-SCCO-001 */
+/*!
+ * Symmetric Cipher Context Object
+ *
+ * This object contains information to control Symmetric Ciphering encrypt and
+ * decrypt functions in #FSL_SYM_MODE_STREAM (ARC4), #FSL_SYM_MODE_ECB,
+ * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR modes and the
+ * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt() functions.
+ * CCM mode is controlled with the #fsl_shw_acco_t object.
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref sccops.
+ */
+typedef struct fsl_shw_scco_t {	/* fsl_shw_symmetric_cipher_context_object */
+} fsl_shw_scco_t;
+
+/*!
+ * Authenticate-Cipher Context Object
+
+ * An object for controlling the function of, and holding information about,
+ * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and
+ * #fsl_shw_auth_decrypt().
+ *
+ * No direct access to its members should be made by programs.  Instead, the
+ * object should be manipulated using the provided functions.  See @ref
+ * accoops.
+ */
+typedef struct fsl_shw_acco_t {	/* fsl_shw_authenticate_cipher_context_object */
+} fsl_shw_acco_t;
+	  /*! @} *//* strgrp */
+
+/******************************************************************************
+ * Access Macros for Objects
+ *****************************************************************************/
+/*! @addtogroup pcoops
+    @{ */
+
+/*!
+ * Get FSL SHW API version
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @param[out] major     A pointer to where the major version
+ *                       of the API is to be stored.
+ * @param[out] minor     A pointer to where the minor version
+ *                       of the API is to be stored.
+ */
+void fsl_shw_pco_get_version(const fsl_shw_pco_t * pc_info,
+			     uint32_t * major, uint32_t * minor);
+
+/*!
+ * Get underlying driver version.
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @param[out] major     A pointer to where the major version
+ *                       of the driver is to be stored.
+ * @param[out] minor     A pointer to where the minor version
+ *                       of the driver is to be stored.
+ */
+void fsl_shw_pco_get_driver_version(const fsl_shw_pco_t * pc_info,
+				    uint32_t * major, uint32_t * minor);
+
+/*!
+ * Get list of symmetric algorithms supported.
+ *
+ * @param pc_info   The Platform Capabilities Object to query.
+ * @param[out] algorithms A pointer to where to store the location of
+ *                        the list of algorithms.
+ * @param[out] algorithm_count A pointer to where to store the number of
+ *                             algorithms in the list at @a algorithms.
+ */
+void fsl_shw_pco_get_sym_algorithms(const fsl_shw_pco_t * pc_info,
+				    fsl_shw_key_alg_t * algorithms[],
+				    uint8_t * algorithm_count);
+
+/*!
+ * Get list of symmetric modes supported.
+ *
+ * @param pc_info         The Platform Capabilities Object to query.
+ * @param[out] modes      A pointer to where to store the location of
+ *                        the list of modes.
+ * @param[out] mode_count A pointer to where to store the number of
+ *                        algorithms in the list at @a modes.
+ */
+void fsl_shw_pco_get_sym_modes(const fsl_shw_pco_t * pc_info,
+			       fsl_shw_sym_mode_t * modes[],
+			       uint8_t * mode_count);
+
+/*!
+ * Get list of hash algorithms supported.
+ *
+ * @param pc_info         The Platform Capabilities Object to query.
+ * @param[out] algorithms A pointer which will be set to the list of
+ *                        algorithms.
+ * @param[out] algorithm_count The number of algorithms in the list at @a
+ *                             algorithms.
+ */
+void fsl_shw_pco_get_hash_algorithms(const fsl_shw_pco_t * pc_info,
+				     fsl_shw_hash_alg_t * algorithms[],
+				     uint8_t * algorithm_count);
+
+/*!
+ * Determine whether the combination of a given symmetric algorithm and a given
+ * mode is supported.
+ *
+ * @param pc_info    The Platform Capabilities Object to query.
+ * @param algorithm  A Symmetric Cipher algorithm.
+ * @param mode       A Symmetric Cipher mode.
+ *
+ * @return 0 if combination is not supported, non-zero if supported.
+ */
+int fsl_shw_pco_check_sym_supported(const fsl_shw_pco_t * pc_info,
+				    fsl_shw_key_alg_t algorithm,
+				    fsl_shw_sym_mode_t mode);
+
+/*!
+ * Determine whether a given Encryption-Authentication mode is supported.
+ *
+ * @param pc_info   The Platform Capabilities Object to query.
+ * @param mode       The Authentication mode.
+ *
+ * @return 0 if mode is not supported, non-zero if supported.
+ */
+int fsl_shw_pco_check_auth_supported(const fsl_shw_pco_t * pc_info,
+				     fsl_shw_acc_mode_t mode);
+
+/*!
+ * Determine whether Black Keys (key establishment / wrapping) is supported.
+ *
+ * @param pc_info  The Platform Capabilities Object to query.
+ *
+ * @return 0 if wrapping is not supported, non-zero if supported.
+ */
+int fsl_shw_pco_check_black_key_supported(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get FSL SHW SCC driver version
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @param[out] major     A pointer to where the major version
+ *                       of the SCC driver is to be stored.
+ * @param[out] minor     A pointer to where the minor version
+ *                       of the SCC driver is to be stored.
+ */
+void fsl_shw_pco_get_scc_driver_version(const fsl_shw_pco_t * pc_info,
+					uint32_t * major, uint32_t * minor);
+
+/*!
+ * Get SCM hardware version
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @return               The SCM hardware version
+ */
+uint32_t fsl_shw_pco_get_scm_version(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get SMN hardware version
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @return               The SMN hardware version
+ */
+uint32_t fsl_shw_pco_get_smn_version(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get the size of an SCM block, in bytes
+ *
+ * @param      pc_info   The Platform Capabilities Object to query.
+ * @return               The size of an SCM block, in bytes.
+ */
+uint32_t fsl_shw_pco_get_scm_block_size(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get size of Black and Red RAM memory
+ *
+ * @param      pc_info     The Platform Capabilities Object to query.
+ * @param[out] black_size  A pointer to where the size of the Black RAM, in
+ *                         blocks, is to be placed.
+ * @param[out] red_size    A pointer to where the size of the Red RAM, in
+ *                         blocks, is to be placed.
+ */
+void fsl_shw_pco_get_smn_size(const fsl_shw_pco_t * pc_info,
+			      uint32_t * black_size, uint32_t * red_size);
+
+/*!
+ * Determine whether Secure Partitions are supported
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return 0 if secure partitions are not supported, non-zero if supported.
+ */
+int fsl_shw_pco_check_spo_supported(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get the size of a Secure Partitions
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return Partition size, in bytes.  0 if Secure Partitions not supported.
+ */
+uint32_t fsl_shw_pco_get_spo_size_bytes(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Get the number of Secure Partitions on this platform
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return Number of partitions. 0 if Secure Partitions not supported.  Note
+ *         that this returns the total number of partitions, though
+ *         not all may be available to the user.
+ */
+uint32_t fsl_shw_pco_get_spo_count(const fsl_shw_pco_t * pc_info);
+
+/*!
+ * Determine whether Platform Key features are available
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return  1 if Programmed Key features are available, otherwise zero.
+ */
+int fsl_shw_pco_check_pk_supported(const fsl_shw_pco_t * pc_info);
+
+/*!
+  * Determine whether Software Key features are available
+  *
+  * @param pc_info 		 The Platform Capabilities Object to query.
+  *
+  * @return  1 if Software key features are available, otherwise zero.
+  */
+int fsl_shw_pco_check_sw_keys_supported(const fsl_shw_pco_t * pc_info);
+
+/*! @} *//* pcoops */
+
+/*! @addtogroup ucoops
+    @{ */
+
+/*!
+ * Initialize a User Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the User Context Object to initial values, and set the size
+ * of the results pool.  The mode will be set to a default of
+ * #FSL_UCO_BLOCKING_MODE.
+ *
+ * When using non-blocking operations, this sets the maximum number of
+ * operations which can be outstanding.  This number includes the counts of
+ * operations waiting to start, operation(s) being performed, and results which
+ * have not been retrieved.
+ *
+ * Changes to this value are ignored once user registration has completed.  It
+ * should be set to 1 if only blocking operations will ever be performed.
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param pool_size    The maximum number of operations which can be
+ *                     outstanding.
+ */
+void fsl_shw_uco_init(fsl_shw_uco_t * user_ctx, uint16_t pool_size);
+
+/*!
+ * Set the User Reference for the User Context.
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param reference    A value which will be passed back with a result.
+ */
+void fsl_shw_uco_set_reference(fsl_shw_uco_t * user_ctx, uint32_t reference);
+
+/*!
+ * Set the callback routine for the User Context.
+ *
+ * Note that the callback routine may be called when no results are available,
+ * and possibly even when no requests are outstanding.
+ *
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param callback_fn  The function the API will invoke when an operation
+ *                     completes.
+ */
+void fsl_shw_uco_set_callback(fsl_shw_uco_t * user_ctx,
+			      void (*callback_fn) (fsl_shw_uco_t * uco));
+
+/*!
+ * Set flags in the User Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param flags        ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+void fsl_shw_uco_set_flags(fsl_shw_uco_t * user_ctx, uint32_t flags);
+
+/*!
+ * Clear flags in the User Context.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param flags        ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+void fsl_shw_uco_clear_flags(fsl_shw_uco_t * user_ctx, uint32_t flags);
+
+/*!
+ * Select a key for the key-wrap key for key wrapping/unwrapping
+ *
+ * Without a call to this function, default is FSL_SHW_PF_KEY_IIM.  The wrap
+ * key is used to encrypt and decrypt the per-key random secret which is used
+ * to calculate the key which will encrypt/decrypt the user's key.
+ *
+ * @param user_ctx     The User Context object to operate on.
+ * @param pf_key       Which key to use.  Valid choices are
+ *                     #FSL_SHW_PF_KEY_IIM, #FSL_SHW_PF_KEY_RND, and
+ *                     #FSL_SHW_PF_KEY_IIM_RND.
+ */
+void fsl_shw_uco_set_wrap_key(fsl_shw_uco_t * user_ctx,
+			      fsl_shw_pf_key_t pf_key);
+
+	  /*! @} *//* ucoops */
+
+/*! @addtogroup rops
+    @{ */
+
+/*!
+ * Retrieve the status code from a Result Object.
+ *
+ * @param result   The result object to query.
+ *
+ * @return The status of the request.
+ */
+fsl_shw_return_t fsl_shw_ro_get_status(fsl_shw_result_t * result);
+
+/*!
+ * Retrieve the reference value from a Result Object.
+ *
+ * @param result   The result object to query.
+ *
+ * @return The reference associated with the request.
+ */
+uint32_t fsl_shw_ro_get_reference(fsl_shw_result_t * result);
+
+	 /* @} *//* rops */
+
+/*! @addtogroup skoops
+    @{ */
+
+/*!
+ * Initialize a Secret Key Object.
+ *
+ * This function or #fsl_shw_sko_init_pf_key() must be called before performing
+ * any other operation with the Object.
+ *
+ * @param key_info  The Secret Key Object to be initialized.
+ * @param algorithm DES, AES, etc.
+ *
+ */
+void fsl_shw_sko_init(fsl_shw_sko_t * key_info, fsl_shw_key_alg_t algorithm);
+
+/*!
+ * Initialize a Secret Key Object to use a Platform Key register.
+ *
+ * This function or #fsl_shw_sko_init() must be called before performing any
+ * other operation with the Object.  #fsl_shw_sko_set_key() does not work on
+ * a key object initialized in this way.
+ *
+ * If this function is used to initialize the key object, but no key is
+ * established with the key object, then the object will refer strictly to the
+ * key value specified by the @c pf_key selection.
+ *
+ * If the pf key is #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG, then the
+ * key object may be used with #fsl_shw_establish_key() to change the Program
+ * Key value.  When the pf key is neither #FSL_SHW_PF_KEY_PRG nor
+ * #FSL_SHW_PF_KEY_IIM_PRG, it is an error to call #fsl_shw_establish_key().
+ *
+ * @param key_info     The Secret Key Object to be initialized.
+ * @param algorithm    DES, AES, etc.
+ * @param pf_key       Which platform key is referenced.
+ */
+void fsl_shw_sko_init_pf_key(fsl_shw_sko_t * key_info,
+			     fsl_shw_key_alg_t algorithm,
+			     fsl_shw_pf_key_t pf_key);
+
+/*!
+ * Store a cleartext key in the key object.
+ *
+ * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag. It should
+ * not be used if there is a key established with the key object.  If there is,
+ * a call to #fsl_shw_release_key() should be made first.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param key          A pointer to the beginning of the key.
+ * @param key_length   The length, in octets, of the key.  The value should be
+ *                     appropriate to the key size supported by the algorithm.
+ *                     64 octets is the absolute maximum value allowed for this
+ *                     call.
+ */
+void fsl_shw_sko_set_key(fsl_shw_sko_t * key_object,
+			 const uint8_t * key, uint16_t key_length);
+
+/*!
+ * Set a size for the key.
+ *
+ * This function would normally be used when the user wants the key to be
+ * generated from a random source.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param key_length   The length, in octets, of the key.  The value should be
+ *                     appropriate to the key size supported by the algorithm.
+ *                     64 octets is the absolute maximum value allowed for this
+ *                     call.
+ */
+void fsl_shw_sko_set_key_length(fsl_shw_sko_t * key_object,
+				uint16_t key_length);
+
+/*!
+ * Set the User ID associated with the key.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param userid       The User ID to identify authorized users of the key.
+ */
+void fsl_shw_sko_set_user_id(fsl_shw_sko_t * key_object, key_userid_t userid);
+
+/*!
+ * Set the keystore that the key will be stored in.
+ *
+ * @param key_object    A variable of type #fsl_shw_sko_t.
+ * @param keystore      The keystore to place the key in.  This is a variable of
+ *                      type #fsl_shw_kso_t.
+ */
+void fsl_shw_sko_set_keystore(fsl_shw_sko_t * key_object,
+			      fsl_shw_kso_t * keystore);
+
+/*!
+ * Set the establish key handle into a key object.
+ *
+ * The @a userid field will be used to validate the access to the unwrapped
+ * key.  This feature is not available for all platforms, nor for all
+ * algorithms and modes.
+ *
+ * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT
+ * flag will be cleared).
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param userid       The User ID to verify this user is an authorized user of
+ *                     the key.
+ * @param handle       A @a handle from #fsl_shw_sko_get_established_info.
+ */
+void fsl_shw_sko_set_established_info(fsl_shw_sko_t * key_object,
+				      key_userid_t userid, uint32_t handle);
+
+/*!
+ * Extract the algorithm from a key object.
+ *
+ * @param      key_info  The Key Object to be queried.
+ * @param[out] algorithm A pointer to the location to store the algorithm.
+ */
+void fsl_shw_sko_get_algorithm(const fsl_shw_sko_t * key_info,
+			       fsl_shw_key_alg_t * algorithm);
+
+/*!
+ * Retrieve the cleartext key from a key object that is stored in a user
+ * keystore.
+ *
+ * @param      skobject     The Key Object to be queried.
+ * @param[out] skkey        A pointer to the location to store the key.  NULL
+ *                          if the key is not stored in a user keystore.
+ */
+void fsl_shw_sko_get_key(const fsl_shw_sko_t * skobject, void *skkey);
+
+/*!
+ * Retrieve the established-key handle from a key object.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param handle       The location to store the @a handle of the unwrapped
+ *                     key.
+ */
+void fsl_shw_sko_get_established_info(fsl_shw_sko_t * key_object,
+				      uint32_t * handle);
+
+/*!
+ * Determine the size of a wrapped key based upon the cleartext key's length.
+ *
+ * This function can be used to calculate the number of octets that
+ * #fsl_shw_extract_key() will write into the location at @a covered_key.
+ *
+ * If zero is returned at @a length, this means that the key length in
+ * @a key_info is not supported.
+ *
+ * @param      key_info         Information about a key to be wrapped.
+ * @param      length           Location to store the length of a wrapped
+ *                              version of the key in @a key_info.
+ */
+void fsl_shw_sko_calculate_wrapped_size(const fsl_shw_sko_t * key_info,
+					uint32_t * length);
+
+/*!
+ * Set some flags in the key object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param flags        (One or more) ORed members of #fsl_shw_key_flags_t which
+ *                     are to be set.
+ */
+void fsl_shw_sko_set_flags(fsl_shw_sko_t * key_object, uint32_t flags);
+
+/*!
+ * Clear some flags in the key object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param key_object   A variable of type #fsl_shw_sko_t.
+ * @param flags        (One or more) ORed members of #fsl_shw_key_flags_t which
+ *                      are to be reset.
+ */
+void fsl_shw_sko_clear_flags(fsl_shw_sko_t * key_object, uint32_t flags);
+
+	  /*! @} *//* end skoops */
+
+/*****************************************************************************/
+
+/*! @addtogroup hcops
+    @{ */
+
+/*****************************************************************************/
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 - partially */
+/*!
+ * Initialize a Hash Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the hash
+ * context object.
+ *
+ * @param      hash_ctx  The hash context to operate upon.
+ * @param      algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                       #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+void fsl_shw_hco_init(fsl_shw_hco_t * hash_ctx, fsl_shw_hash_alg_t algorithm);
+
+/*****************************************************************************/
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-001 */
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 */
+/*!
+ * Get the current hash value and message length from the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hash_ctx  The hash context to query.
+ * @param[out] digest    Pointer to the location of @a length octets where to
+ *                       store a copy of the current value of the digest.
+ * @param      length    Number of octets of hash value to copy.
+ * @param[out] msg_length Pointer to the location to store the number of octets
+ *                        already hashed.
+ */
+void fsl_shw_hco_get_digest(const fsl_shw_hco_t * hash_ctx, uint8_t * digest,
+			    uint8_t length, uint32_t * msg_length);
+
+/*****************************************************************************/
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 - partially */
+/*!
+ * Get the hash algorithm from the hash context object.
+ *
+ * @param      hash_ctx  The hash context to query.
+ * @param[out] algorithm Pointer to where the algorithm is to be stored.
+ */
+void fsl_shw_hco_get_info(const fsl_shw_hco_t * hash_ctx,
+			  fsl_shw_hash_alg_t * algorithm);
+
+/*****************************************************************************/
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-003 */
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 */
+/*!
+ * Set the current hash value and message length in the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hash_ctx  The hash context to operate upon.
+ * @param      context   Pointer to buffer of appropriate length to copy into
+ *                       the hash context object.
+ * @param      msg_length The number of octets of the message which have
+ *                        already been hashed.
+ *
+ */
+void fsl_shw_hco_set_digest(fsl_shw_hco_t * hash_ctx, const uint8_t * context,
+			    uint32_t msg_length);
+
+/*!
+ * Set flags in a Hash Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hash_ctx   The hash context to be operated on.
+ * @param flags      The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+void fsl_shw_hco_set_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags);
+
+/*!
+ * Clear flags in a Hash Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hash_ctx   The hash context to be operated on.
+ * @param flags      The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+void fsl_shw_hco_clear_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags);
+
+	  /*! @} *//* end hcops */
+
+/*****************************************************************************/
+
+/*! @addtogroup hmcops
+    @{ */
+
+/*!
+ * Initialize an HMAC Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the HMAC
+ * context object.
+ *
+ * @param      hmac_ctx  The HMAC context to operate upon.
+ * @param      algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                       #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+void fsl_shw_hmco_init(fsl_shw_hmco_t * hmac_ctx, fsl_shw_hash_alg_t algorithm);
+
+/*!
+ * Set flags in an HMAC Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hmac_ctx   The HMAC context to be operated on.
+ * @param flags      The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+void fsl_shw_hmco_set_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags);
+
+/*!
+ * Clear flags in an HMAC Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hmac_ctx   The HMAC context to be operated on.
+ * @param flags      The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+void fsl_shw_hmco_clear_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags);
+
+/*! @} */
+
+/*****************************************************************************/
+
+/*! @addtogroup sccops
+    @{ */
+
+/*!
+ * Initialize a Symmetric Cipher Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  This will set the @a mode and @a algorithm and initialize the
+ * Object.
+ *
+ * @param sym_ctx   The context object to operate on.
+ * @param algorithm The cipher algorithm this context will be used with.
+ * @param mode      #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc.
+ *
+ */
+void fsl_shw_scco_init(fsl_shw_scco_t * sym_ctx,
+		       fsl_shw_key_alg_t algorithm, fsl_shw_sym_mode_t mode);
+
+/*!
+ * Set the flags for a Symmetric Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param sym_ctx  The context object to operate on.
+ * @param flags    The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+void fsl_shw_scco_set_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags);
+
+/*!
+ * Clear some flags in a Symmetric Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param sym_ctx  The context object to operate on.
+ * @param flags    The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+void fsl_shw_scco_clear_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags);
+
+/*!
+ * Set the Context (IV) for a Symmetric Cipher Context.
+ *
+ * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the
+ * context (the S-Box and pointers) for ARC4.  The full context size will
+ * be copied.
+ *
+ * @param sym_ctx  The context object to operate on.
+ * @param context  A pointer to the buffer which contains the context.
+ *
+ */
+void fsl_shw_scco_set_context(fsl_shw_scco_t * sym_ctx, uint8_t * context);
+
+/*!
+ * Get the Context for a Symmetric Cipher Context.
+ *
+ * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to
+ * retrieve context (the S-Box and pointers) for ARC4.  The full context
+ * will be copied.
+ *
+ * @param      sym_ctx  The context object to operate on.
+ * @param[out] context  Pointer to location where context will be stored.
+ */
+void fsl_shw_scco_get_context(const fsl_shw_scco_t * sym_ctx,
+			      uint8_t * context);
+
+/*!
+ * Set the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will set the Counter Value for CTR mode.
+ *
+ * @param sym_ctx  The context object to operate on.
+ * @param counter  The starting counter value.  The number of octets.
+ *                 copied will be the block size for the algorithm.
+ * @param modulus  The modulus for controlling the incrementing of the counter.
+ *
+ */
+void fsl_shw_scco_set_counter_info(fsl_shw_scco_t * sym_ctx,
+				   const uint8_t * counter,
+				   fsl_shw_ctr_mod_t modulus);
+
+/*!
+ * Get the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will retrieve the Counter Value is for CTR mode.
+ *
+ * @param sym_ctx         The context object to query.
+ * @param[out] counter    Pointer to location to store the current counter
+ *                        value.  The number of octets copied will be the
+ *                        block size for the algorithm.
+ * @param[out] modulus    Pointer to location to store the modulus.
+ *
+ */
+void fsl_shw_scco_get_counter_info(const fsl_shw_scco_t * sym_ctx,
+				   uint8_t * counter,
+				   fsl_shw_ctr_mod_t * modulus);
+
+	  /*! @} *//* end sccops */
+
+/*****************************************************************************/
+
+/*! @addtogroup accoops
+    @{ */
+
+/*!
+ * Initialize a Authentication-Cipher Context.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param mode         The mode for this object (only #FSL_ACC_MODE_CCM
+ *                     supported).
+ */
+void fsl_shw_acco_init(fsl_shw_acco_t * auth_object, fsl_shw_acc_mode_t mode);
+
+/*!
+ * Set the flags for a Authentication-Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param flags        The flags to set (one or more from
+ *                     #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+void fsl_shw_acco_set_flags(fsl_shw_acco_t * auth_object, uint32_t flags);
+
+/*!
+ * Clear some flags in a Authentication-Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param flags        The flags to reset (one or more from
+ *                     #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+void fsl_shw_acco_clear_flags(fsl_shw_acco_t * auth_object, uint32_t flags);
+
+/*!
+ * Set up the Authentication-Cipher Object for CCM mode.
+ *
+ * This will set the @a auth_object for CCM mode and save the @a ctr,
+ * and @a mac_length.  This function can be called instead of
+ * #fsl_shw_acco_init().
+ *
+ * The parameter @a ctr is Counter Block 0, (counter value 0), which is for the
+ * MAC.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param algorithm    Cipher algorithm.  Only AES is supported.
+ * @param ctr          The initial counter value.
+ * @param mac_length   The number of octets used for the MAC.  Valid values are
+ *                     4, 6, 8, 10, 12, 14, and 16.
+ */
+void fsl_shw_acco_set_ccm(fsl_shw_acco_t * auth_object,
+			  fsl_shw_key_alg_t algorithm,
+			  const uint8_t * ctr, uint8_t mac_length);
+
+/*!
+ * Format the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will also set the IV and CTR values per Appendix A of NIST
+ * Special Publication 800-38C (May 2004).  It will also perform the
+ * #fsl_shw_acco_set_ccm() operation with information derived from this set of
+ * parameters.
+ *
+ * Note this function assumes the algorithm is AES.  It initializes the
+ * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the
+ * flags to be #FSL_ACCO_NIST_CCM.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param t_length     The number of octets used for the MAC.  Valid values are
+ *                     4, 6, 8, 10, 12, 14, and 16.
+ * @param ad_length    Number of octets of Associated Data (may be zero).
+ * @param q_length     A value for the size of the length of @a q field.  Valid
+ *                     values are 1-8.
+ * @param n            The Nonce (packet number or other changing value). Must
+ *                     be (15 - @a q_length) octets long.
+ * @param q            The value of Q (size of the payload in octets).
+ *
+ */
+void fsl_shw_ccm_nist_format_ctr_and_iv(fsl_shw_acco_t * auth_object,
+					uint8_t t_length,
+					uint32_t ad_length,
+					uint8_t q_length,
+					const uint8_t * n, uint32_t q);
+
+/*!
+ * Update the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will set the IV and CTR values per Appendix A of NIST Special
+ * Publication 800-38C (May 2004).
+ *
+ * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has
+ * previously been called on the @a auth_object.
+ *
+ * @param auth_object  Pointer to object to operate on.
+ * @param n             The Nonce (packet number or other changing value). Must
+ *                      be (15 - @a q_length) octets long.
+ * @param q             The value of Q (size of the payload in octets).
+ *
+ */
+void fsl_shw_ccm_nist_update_ctr_and_iv(fsl_shw_acco_t * auth_object,
+					const uint8_t * n, uint32_t q);
+
+	 /* @} *//* accoops */
+
+/******************************************************************************
+ * Library functions
+ *****************************************************************************/
+
+/*! @addtogroup miscfuns
+    @{ */
+
+/* REQ-S2LRD-PINTFC-API-GEN-003 */
+/*!
+ * Determine the hardware security capabilities of this platform.
+ *
+ * Though a user context object is passed into this function, it will always
+ * act in a non-blocking manner.
+ *
+ * @param  user_ctx   The user context which will be used for the query.
+ *
+ * @return  A pointer to the capabilities object.
+ */
+extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-004 */
+/*!
+ * Create an association between the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which will be used for this association.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-005 */
+/*!
+ * Destroy the association between the user and the provider of the API.
+ *
+ * @param  user_ctx   The user context which is no longer needed.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-006 */
+/*!
+ * Retrieve results from earlier operations.
+ *
+ * @param         user_ctx     The user's context.
+ * @param         result_size  The number of array elements of @a results.
+ * @param[in,out] results      Pointer to first of the (array of) locations to
+ *                             store results.
+ * @param[out]    result_count Pointer to store the number of results which
+ *                             were returned.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx,
+					    uint16_t result_size,
+					    fsl_shw_result_t results[],
+					    uint16_t * result_count);
+
+/*!
+ * Allocate a block of secure memory
+ *
+ * @param       user_ctx        User context
+ * @param       size            Memory size (octets).  Note: currently only
+ *                              supports only single-partition sized blocks.
+ * @param       UMID            User Mode ID to use when registering the
+ *                              partition.
+ * @param       permissions     Permissions to initialize the partition with.
+ *                              Can be made by ORing flags from the
+ *                              #fsl_shw_permission_t.
+ *
+ * @return                      Address of the allocated memory.  NULL if the
+ *                              call was not successful.
+ */
+extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx,
+			     uint32_t size,
+			     const uint8_t * UMID, uint32_t permissions);
+
+/*!
+ * Free a block of secure memory that was allocated with #fsl_shw_smalloc
+ *
+ * @param       user_ctx        User context
+ * @param       address         Address of the block of secure memory to be
+ *                              released.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address);
+
+/*!
+ * Diminish the permissions of a block of secure memory.  Note that permissions
+ * can only be revoked.
+ *
+ * @param       user_ctx        User context
+ * @param       address         Base address of the secure memory to work with
+ * @param       permissions     Permissions to initialize the partition with.
+ *                              Can be made by ORing flags from the
+ *                              #fsl_shw_permission_t.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx,
+					       void *address,
+					       uint32_t permissions);
+
+/*!
+ * @brief   Encrypt a region of secure memory using the hardware secret key
+ *
+ * @param       user_ctx        User context
+ * @param       partition_base  Base address of the partition
+ * @param       offset_bytes    Offset of data from the partition base
+ * @param       byte_count      Length of the data to encrypt
+ * @param       black_data      Location to store the encrypted data
+ * @param       IV              IV to use for the encryption routine
+ * @param       cypher_mode     Cyphering mode to use, specified by type
+ *                              #fsl_shw_cypher_mode_t
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+do_scc_encrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode);
+
+/*!
+ * @brief   Decrypt a region of secure memory using the hardware secret key
+ *
+ * @param       user_ctx        User context
+ * @param       partition_base  Base address of the partition
+ * @param       offset_bytes    Offset of data from the partition base
+ * @param       byte_count      Length of the data to encrypt
+ * @param       black_data      Location to store the encrypted data
+ * @param       IV              IV to use for the encryption routine
+ * @param       cypher_mode     Cyphering mode to use, specified by type
+ *                              #fsl_shw_cypher_mode_t
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+do_scc_decrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, const uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode);
+
+	  /*! @} *//* miscfuns */
+
+/*! @addtogroup opfuns
+    @{ */
+
+/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+/*!
+ * Encrypt a stream of data with a symmetric-key algorithm.
+ *
+ * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the
+ * flags of the @a sym_ctx object will control part of the operation of this
+ * function.  The #FSL_SYM_CTX_INIT flag means that there is no context info in
+ * the object.  The #FSL_SYM_CTX_LOAD means to use information in the
+ * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag
+ * means to update the object's context information after the operation has
+ * been performed.
+ *
+ * All of the data for an operation can be run through at once using the
+ * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using
+ * a @a length for the whole of the data.
+ *
+ * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function
+ * would "pick up" where the previous call left off, allowing the user to
+ * perform the larger function in smaller steps.
+ *
+ * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always
+ * be a multiple of the block size for the algorithm being used.  For proper
+ * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the
+ * block size until the last operation on the total octet stream.
+ *
+ * Some users of ARC4 may want to compute the context (S-Box and pointers) from
+ * the key before any data is available.  This may be done by running this
+ * function with a @a length of zero, with the init & save flags flags on in
+ * the @a sym_ctx.  Subsequent operations would then run as normal with the
+ * load and save flags.  Note that they key object is still required.
+ *
+ * @param         user_ctx  A user context from #fsl_shw_register_user().
+ * @param         key_info  Key and algorithm  being used for this operation.
+ * @param[in,out] sym_ctx   Info on cipher mode, state of the cipher.
+ * @param         length   Length, in octets, of the pt (and ct).
+ * @param         pt       pointer to plaintext to be encrypted.
+ * @param[out]    ct       pointer to where to store the resulting ciphertext.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ *
+ */
+extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_sko_t * key_info,
+						  fsl_shw_scco_t * sym_ctx,
+						  uint32_t length,
+						  const uint8_t * pt,
+						  uint8_t * ct);
+
+/* PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+/*!
+ * Decrypt a stream of data with a symmetric-key algorithm.
+ *
+ * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the
+ * flags of the @a sym_ctx object will control part of the operation of this
+ * function.  The #FSL_SYM_CTX_INIT flag means that there is no context info in
+ * the object.  The #FSL_SYM_CTX_LOAD means to use information in the
+ * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag
+ * means to update the object's context information after the operation has
+ * been performed.
+ *
+ * All of the data for an operation can be run through at once using the
+ * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using
+ * a @a length for the whole of the data.
+ *
+ * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function
+ * would "pick up" where the previous call left off, allowing the user to
+ * perform the larger function in smaller steps.
+ *
+ * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always
+ * be a multiple of the block size for the algorithm being used.  For proper
+ * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the
+ * block size until the last operation on the total octet stream.
+ *
+ * Some users of ARC4 may want to compute the context (S-Box and pointers) from
+ * the key before any data is available.  This may be done by running this
+ * function with a @a length of zero, with the #FSL_SYM_CTX_INIT &
+ * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx.  Subsequent operations would
+ * then run as normal with the load & save flags.  Note that they key object is
+ * still required.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      key_info The key and algorithm being used in this operation.
+ * @param[in,out] sym_ctx Info on cipher mode, state of the cipher.
+ * @param      length   Length, in octets, of the ct (and pt).
+ * @param      ct       pointer to ciphertext to be decrypted.
+ * @param[out] pt       pointer to where to store the resulting plaintext.
+ *
+ * @return    A return code of type #fsl_shw_return_t
+ *
+ */
+extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_sko_t * key_info,
+						  fsl_shw_scco_t * sym_ctx,
+						  uint32_t length,
+						  const uint8_t * ct,
+						  uint8_t * pt);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */
+/*!
+ * Hash a stream of data with a cryptographic hash algorithm.
+ *
+ * The flags in the @a hash_ctx control the operation of this function.
+ *
+ * Hashing functions work on 64 octets of message at a time.  Therefore, when
+ * any partial hashing of a long message is performed, the message @a length of
+ * each segment must be a multiple of 64.  When ready to
+ * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value.
+ *
+ * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a
+ * one-shot complete hash, including padding, will be performed.  The @a length
+ * may be any value.
+ *
+ * The first octets of a data stream can be hashed by setting the
+ * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags.  The @a length must be
+ * a multiple of 64.
+ *
+ * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by
+ * #FSL_HASH_FLAGS_SAVE.  The two in combination will allow a (multiple-of-64
+ * octets) 'middle sequence' of the data stream to be hashed with the
+ * beginning.  The @a length must again be a multiple of 64.
+ *
+ * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously
+ * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and
+ * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the
+ * stream.  The @a length may be any value.
+ *
+ * If the user program wants to do the padding for the hash, it can leave off
+ * the #FSL_HASH_FLAGS_FINALIZE flag.  The @a length must then be a multiple of
+ * 64 octets.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param[in,out] hash_ctx Hashing algorithm and state of the cipher.
+ * @param      msg       Pointer to the data to be hashed.
+ * @param      length    Length, in octets, of the @a msg.
+ * @param[out] result    If not null, pointer to where to store the hash
+ *                       digest.
+ * @param      result_len Number of octets to store in @a result.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_hco_t * hash_ctx,
+				     const uint8_t * msg,
+				     uint32_t length,
+				     uint8_t * result, uint32_t result_len);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */
+/*!
+ * Precompute the Key hashes for an HMAC operation.
+ *
+ * This function may be used to calculate the inner and outer precomputes,
+ * which are the hash contexts resulting from hashing the XORed key for the
+ * 'inner hash' and the 'outer hash', respectively, of the HMAC function.
+ *
+ * After execution of this function, the @a hmac_ctx will contain the
+ * precomputed inner and outer contexts, so that they may be used by
+ * #fsl_shw_hmac().  The flags of @a hmac_ctx will be updated with
+ * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence.  In addition, the
+ * #FSL_HMAC_FLAGS_INIT flag will be set.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      key_info  The key being used in this operation.  Key must be
+ *                       1 to 64 octets long.
+ * @param[in,out] hmac_ctx The context which controls, by its flags and
+ *                         algorithm, the operation of this function.
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx,
+						fsl_shw_sko_t * key_info,
+						fsl_shw_hmco_t * hmac_ctx);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */
+/*!
+ * Continue, finalize, or one-shot an HMAC operation.
+ *
+ * There are a number of ways to use this function.  The flags in the
+ * @a hmac_ctx object will determine what operations occur.
+ *
+ * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from
+ * the @a key_info, or from the precomputed inner hash value in the
+ * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT.
+ *
+ * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued
+ * from the ongoing inner hash computation in the @a hmac_ctx.
+ *
+ * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed,
+ * the outer hash will be performed, and the @a result will be generated.
+ *
+ * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest
+ * value will be stored in the ongoing inner hash computation field of the @a
+ * hmac_ctx.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param key_info       If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx,
+ *                       this is the key being used in this operation, and the
+ *                       IPAD.  If #FSL_HMAC_FLAGS_INIT is set in the @a
+ *                       hmac_ctx and @a key_info is NULL, then
+ *                       #fsl_shw_hmac_precompute() has been used to populate
+ *                       the @a inner_precompute and @a outer_precompute
+ *                       contexts.  If #FSL_HMAC_FLAGS_INIT is not set, this
+ *                       parameter is ignored.
+
+ * @param[in,out] hmac_ctx The context which controls, by its flags and
+ *                       algorithm, the operation of this function.
+ * @param      msg               Pointer to the message to be hashed.
+ * @param      length            Length, in octets, of the @a msg.
+ * @param[out] result            Pointer, of @a result_len octets, to where to
+ *                               store the HMAC.
+ * @param      result_len        Length of @a result buffer.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     fsl_shw_hmco_t * hmac_ctx,
+				     const uint8_t * msg,
+				     uint32_t length,
+				     uint8_t * result, uint32_t result_len);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */
+/*!
+ * Get random data.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    The number of octets of @a data being requested.
+ * @param[out] data      A pointer to a location of @a length octets to where
+ *                       random data will be returned.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+					   uint32_t length, uint8_t * data);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */
+/*!
+ * Add entropy to random number generator.
+ *
+ * @param      user_ctx  A user context from #fsl_shw_register_user().
+ * @param      length    Number of bytes at @a data.
+ * @param      data      Entropy to add to random number generator.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+					    uint32_t length, uint8_t * data);
+
+/*!
+ * Perform Generation-Encryption by doing a Cipher and a Hash.
+ *
+ * Generate the authentication value @a auth_value as well as encrypt the @a
+ * payload into @a ct (the ciphertext).  This is a one-shot function, so all of
+ * the @a auth_data and the total message @a payload must passed in one call.
+ * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT
+ * and #FSL_ACCO_CTX_FINALIZE.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      auth_ctx         Controlling object for Authenticate-decrypt.
+ * @param      cipher_key_info  The key being used for the cipher part of this
+ *                              operation.  In CCM mode, this key is used for
+ *                              both parts.
+ * @param      auth_key_info    The key being used for the authentication part
+ *                              of this operation.  In CCM mode, this key is
+ *                              ignored and may be NULL.
+ * @param      auth_data_length Length, in octets, of @a auth_data.
+ * @param      auth_data        Data to be authenticated but not encrypted.
+ * @param      payload_length   Length, in octets, of @a payload.
+ * @param      payload          Pointer to the plaintext to be encrypted.
+ * @param[out] ct               Pointer to the where the encrypted @a payload
+ *                              will be stored.  Must be @a payload_length
+ *                              octets long.
+ * @param[out] auth_value       Pointer to where the generated authentication
+ *                              field will be stored. Must be as many octets as
+ *                              indicated by MAC length in the @a function_ctx.
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_acco_t * auth_ctx,
+					    fsl_shw_sko_t * cipher_key_info,
+					    fsl_shw_sko_t * auth_key_info,
+					    uint32_t auth_data_length,
+					    const uint8_t * auth_data,
+					    uint32_t payload_length,
+					    const uint8_t * payload,
+					    uint8_t * ct, uint8_t * auth_value);
+
+/*!
+ * Perform Authentication-Decryption in Cipher + Hash.
+ *
+ * This function will perform a one-shot decryption of a data stream as well as
+ * authenticate the authentication value.  This is a one-shot function, so all
+ * of the @a auth_data and the total message @a payload must passed in one
+ * call.  This also means that the flags in the @a auth_ctx must be
+ * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      auth_ctx         Controlling object for Authenticate-decrypt.
+ * @param      cipher_key_info  The key being used for the cipher part of this
+ *                              operation.  In CCM mode, this key is used for
+ *                              both parts.
+ * @param      auth_key_info    The key being used for the authentication part
+ *                              of this operation.  In CCM mode, this key is
+ *                              ignored and may be NULL.
+ * @param      auth_data_length Length, in octets, of @a auth_data.
+ * @param      auth_data        Data to be authenticated but not decrypted.
+ * @param      payload_length   Length, in octets, of @a ct and @a pt.
+ * @param      ct               Pointer to the encrypted input stream.
+ * @param      auth_value       The (encrypted) authentication value which will
+ *                              be authenticated.  This is the same data as the
+ *                              (output) @a auth_value argument to
+ *                              #fsl_shw_gen_encrypt().
+ * @param[out] payload          Pointer to where the plaintext resulting from
+ *                              the decryption will be stored.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx,
+					     fsl_shw_acco_t * auth_ctx,
+					     fsl_shw_sko_t * cipher_key_info,
+					     fsl_shw_sko_t * auth_key_info,
+					     uint32_t auth_data_length,
+					     const uint8_t * auth_data,
+					     uint32_t payload_length,
+					     const uint8_t * ct,
+					     const uint8_t * auth_value,
+					     uint8_t * payload);
+
+/*!
+ * Establish the key in a protected location, which can be the system keystore,
+ * user keystore, or (on platforms that support it) as a Platform Key.
+ *
+ * By default, keys initialized with #fsl_shw_sko_init() will be placed into
+ * the system keystore.  The user can cause the key to be established in a
+ * user keystore by first calling #fsl_shw_sko_set_keystore() on the key.
+ * Normally, keys in the system keystore can only be used for hardware
+ * encrypt or decrypt operations, however if the #FSL_SKO_KEY_SW_KEY flag is
+ * applied using #fsl_shw_sko_set_flags(), the key will be established as a
+ * software key, which can then be read out using #fsl_shw_read_key().
+ *
+ * Keys initialized with #fsl_shw_sko_init_pf_key() are established as a
+ * Platform Key.  Their use is covered in @ref di_sec.
+ *
+ * This function only needs to be used when unwrapping a key, setting up a key
+ * which could be wrapped with a later call to #fsl_shw_extract_key(), or
+ * setting up a key as a Platform Key.  Normal cleartext keys can simply be
+ * placed into #fsl_shw_sko_t key objects with #fsl_shw_sko_set_key() and used
+ * directly.
+ *
+ * The maximum key size supported for wrapped/unwrapped keys is 32 octets.
+ * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC
+ * key based on SHA-256.)  The key size is determined by the @a key_info.  The
+ * expected length of @a key can be determined by
+ * #fsl_shw_sko_calculate_wrapped_size()
+ *
+ * The protected key will not be available for use until this operation
+ * successfully completes.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param[in,out] key_info      The information about the key to be which will
+ *                              be established.  In the create case, the key
+ *                              length must be set.
+ * @param      establish_type   How @a key will be interpreted to establish a
+ *                              key for use.
+ * @param key                   If @a establish_type is #FSL_KEY_WRAP_UNWRAP,
+ *                              this is the location of a wrapped key.  If
+ *                              @a establish_type is #FSL_KEY_WRAP_CREATE, this
+ *                              parameter can be @a NULL.  If @a establish_type
+ *                              is #FSL_KEY_WRAP_ACCEPT, this is the location
+ *                              of a plaintext key.
+ */
+extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+					      fsl_shw_sko_t * key_info,
+					      fsl_shw_key_wrap_t establish_type,
+					      const uint8_t * key);
+
+/*!
+ * Read the key value from a key object.
+ *
+ * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with
+ * this call.  It has no effect on the status of the key store.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The referenced key.
+ * @param[out] key              The location to store the key value.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+					 fsl_shw_sko_t * key_info,
+					 uint8_t * key);
+
+/*!
+ * Wrap a key and retrieve the wrapped value.
+ *
+ * A wrapped key is a key that has been cryptographically obscured.  It is
+ * only able to be used with keys that have been established by
+ * #fsl_shw_establish_key().
+ *
+ * For keys established in the system or user keystore, this function will
+ * also release the key (see #fsl_shw_release_key()) so that it must be re-
+ * established before reuse.  This function will not release keys that are
+ * established as a Platform Key, so a call to #fsl_shw_release_key() is
+ * necessary to release those keys.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ * @param[out] covered_key      The location to store the wrapped key.
+ *                              (This size is based upon the maximum key size
+ *                              of 32 octets).
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_sko_t * key_info,
+					    uint8_t * covered_key);
+
+/*!
+ * De-establish a key so that it can no longer be accessed.
+ *
+ * The key will need to be re-established before it can again be used.
+ *
+ * This feature is not available for all platforms, nor for all algorithms and
+ * modes.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ * @param      key_info         The information about the key to be deleted.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_sko_t * key_info);
+
+/*!
+ * Cause the hardware to create a new random key for use by the secure memory
+ * encryption hardware.
+ *
+ * Have the hardware use the secure hardware random number generator to load a
+ * new secret key into the system's Random Key register.
+ *
+ * @param      user_ctx         A user context from #fsl_shw_register_user().
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx);
+
+/*!
+ * Retrieve the detected tamper event.
+ *
+ * Note that if more than one event was detected, this routine will only ever
+ * return one of them.
+ *
+ * @param[in]  user_ctx         A user context from #fsl_shw_register_user().
+ * @param[out] tamperp          Location to store the tamper information.
+ * @param[out] timestampp       Locate to store timestamp from hardwhare when
+ *                              an event was detected.
+ *
+ *
+ * @return    A return code of type #fsl_shw_return_t (for instance, if the platform
+ *            is not in a fail state.
+ */
+extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_tamper_t * tamperp,
+						  uint64_t * timestampp);
+
+/*! @} *//* opfuns */
+
+/* Insert example code into the API documentation. */
+
+/*!
+ * @example apitest.c
+ */
+
+/*!
+ * @example sym.c
+ */
+
+/*!
+ * @example rand.c
+ */
+
+/*!
+ * @example hash.c
+ */
+
+/*!
+ * @example hmac1.c
+ */
+
+/*!
+ * @example hmac2.c
+ */
+
+/*!
+ * @example gen_encrypt.c
+ */
+
+/*!
+ * @example auth_decrypt.c
+ */
+
+/*!
+ * @example wrapped_key.c
+ */
+
+/*!
+ * @example smalloc.c
+ */
+
+/*!
+ * @example user_keystore.c
+ */
+
+/*!
+ * @example dryice.c
+ */
+
+#endif				/* API_DOC */
+
+#endif				/* FSL_SHW_H */
diff --git a/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h b/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h
new file mode 100644
index 000000000000..2a275da2dfa8
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+#ifndef FSL_SHW_KEYSTORE_H
+#define FSL_SHW_KEYSTORE_H
+
+/*!
+ * @file fsl_shw_keystore.h
+ *
+ * @brief Definition of the User Keystore API.
+ *
+ */
+
+/*! \page user_keystore User Keystore API
+ *
+ * Definition of the User Keystore API.
+ *
+ * On platforms with multiple partitions of Secure Memory, the Keystore Object
+ * (#fsl_shw_kso_t) is provided to allow users to manage a private keystore for
+ * use in software cryptographic routines.  The user can define a custom set of
+ * methods for managing their keystore, or use a default keystore handler.  The
+ * keystore is established by #fsl_shw_establish_keystore(), and released by
+ * #fsl_shw_release_keystore().  The intent of this design is to make the
+ * keystore implementation as flexible as possible.
+ *
+ * See @ref keystore_api for the generic keystore API, and @ref
+ * default_keystore for the default keystore implementation.
+ *
+ */
+
+/*!
+ * @defgroup keystore_api User Keystore API
+ *
+ * Keystore API
+ *
+ * These functions define the generic keystore API, which can be used in
+ * conjunction with a keystore implementation backend to support a user
+ * keystore.
+ */
+
+/*!
+ * @defgroup default_keystore Default Keystore Implementation
+ *
+ * Default Keystore Implementation
+ *
+ * These functions define the default keystore implementation, which is used
+ * for the system keystore and for user keystores initialized by
+ * #fsl_shw_init_keystore_default().  They can be used as-is or as a reference
+ * for creating a custom keystore handler.  It uses an entire Secure Memory
+ * partition, divided in to equal slots of length #KEYSTORE_SLOT_SIZE.  These
+ * functions are not intended to be used directly-  all user interaction with
+ * the keystore should be through the @ref keystore_api and the Wrapped Key
+ * interface.
+ *
+ * The current implementation is designed to work with both SCC and SCC2.
+ * Differences between the two versions are noted below.
+ */
+
+/*! @addtogroup keystore_api
+    @{ */
+
+#ifndef KEYSTORE_SLOT_SIZE
+/*! Size of each key slot, in octets.  This sets an upper bound on the size
+ * of a key that can placed in the keystore.
+ */
+#define KEYSTORE_SLOT_SIZE 32
+#endif
+
+/*!
+ * Initialize a Keystore Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object. It allows the user to associate a custom keystore interface by
+ * specifying the correct set of functions that will be used to perform actions
+ * on the keystore object.  To use the default keystore handler, the function
+ * #fsl_shw_init_keystore_default() can be used instead.
+ *
+ * @param keystore      The Keystore object to operate on.
+ * @param data_init     Keystore initialization function.  This function is
+ *                      responsible for initializing the keystore.  A
+ *                      user-defined object can be assigned to the user_data
+ *                      pointer, and will be passed to any function acting on
+ *                      that keystore.  It is called during
+ *                      #fsl_shw_establish_keystore().
+ * @param data_cleanup  Keystore cleanup function.  This function cleans up
+ *                      any data structures associated with the keyboard.  It
+ *                      is called by #fsl_shw_release_keystore().
+ * @param slot_alloc    Slot allocation function.  This function allocates a
+ *                      key slot, potentially based on size and owner id.  It
+ *                      is called by #fsl_shw_establish_key().
+ * @param slot_dealloc  Slot deallocation function.
+ * @param slot_verify_access Function to verify that a given Owner ID
+ *                           credential matches the given slot.
+ * @param slot_get_address   For SCC2: Get the virtual address (kernel or
+ *                           userspace) of the data stored in the slot.
+ *                           For SCC: Get the physical address of the data
+ *                           stored in the slot.
+ * @param slot_get_base      For SCC2: Get the (virtual) base address of the
+ *                           partition that the slot is located on.
+ *                           For SCC: Not implemented.
+ * @param slot_get_offset    For SCC2: Get the offset from the start of the
+ *                           partition that the slot data is located at (in
+ *                           octets)
+ *                           For SCC: Not implemented.
+ * @param slot_get_slot_size Get the size of the key slot, in octets.
+ */
+extern void fsl_shw_init_keystore(fsl_shw_kso_t * keystore,
+				  fsl_shw_return_t(*data_init) (fsl_shw_uco_t *
+								user_ctx,
+								void
+								**user_data),
+				  void (*data_cleanup) (fsl_shw_uco_t *
+							user_ctx,
+							void **user_data),
+				  fsl_shw_return_t(*slot_alloc) (void
+								 *user_data,
+								 uint32_t size,
+								 uint64_t
+								 owner_id,
+								 uint32_t *
+								 slot),
+				  fsl_shw_return_t(*slot_dealloc) (void
+								   *user_data,
+								   uint64_t
+								   owner_id,
+								   uint32_t
+								   slot),
+				  fsl_shw_return_t(*slot_verify_access) (void
+									 *user_data,
+									 uint64_t
+									 owner_id,
+									 uint32_t
+									 slot),
+				  void *(*slot_get_address) (void *user_data,
+							     uint32_t handle),
+				  uint32_t(*slot_get_base) (void *user_data,
+							    uint32_t handle),
+				  uint32_t(*slot_get_offset) (void *user_data,
+							      uint32_t handle),
+				  uint32_t(*slot_get_slot_size) (void
+								 *user_data,
+								 uint32_t
+								 handle));
+
+/*!
+ * Initialize a Keystore Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object. It sets the user keystore object up to use the default keystore
+ * handler.  If a custom keystore handler is desired, the function
+ * #fsl_shw_init_keystore() can be used instead.
+ *
+ * @param keystore      The Keystore object to operate on.
+ */
+extern void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore);
+
+/*!
+ * Establish a Keystore Object.
+ *
+ * This function establishes a keystore object that has been set up by a call
+ * to #fsl_shw_init_keystore().  It is a wrapper for the user-defined
+ * data_init() function, which is specified during keystore initialization.
+ *
+ * @param user_ctx      The user context that this keystore should be attached
+ *                      to
+ * @param keystore      The Keystore object to operate on.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t * user_ctx,
+						   fsl_shw_kso_t * keystore);
+
+/*!
+ * Release a Keystore Object.
+ *
+ * This function releases an established keystore object.  It is a wrapper for
+ * the user-defined data_cleanup() function, which is specified during keystore
+ * initialization.
+ *
+ * @param user_ctx      The user context that this keystore should be attached
+ *                      to.
+ * @param keystore      The Keystore object to operate on.
+ */
+extern void fsl_shw_release_keystore(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_kso_t * keystore);
+
+/*!
+ * Allocate a slot in the Keystore.
+ *
+ * This function attempts to allocate a slot to hold a key in the keystore.  It
+ * is called by #fsl_shw_establish_key() when establishing a Secure Key Object,
+ * if the key has been flagged to be stored in a user keystore by the
+ * #fsl_shw_sko_set_keystore() function.  It is a wrapper for the
+ * implementation-specific function slot_alloc().
+ *
+ * @param keystore      The Keystore object to operate on.
+ * @param[in] size      Size of the key to be stored (octets).
+ * @param[in] owner_id  ID of the key owner.
+ * @param[out] slot     If successful, assigned slot ID
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t * keystore,
+					    uint32_t size,
+					    uint64_t owner_id, uint32_t * slot);
+
+/*!
+ * Deallocate a slot in the Keystore.
+ *
+ * This function attempts to allocate a slot to hold a key in the keystore.
+ * It is called by #fsl_shw_extract_key() and #fsl_shw_release_key() when the
+ * key that it contains is to be released.  It is a wrapper for the
+ * implmentation-specific function slot_dealloc().
+
+ * @param keystore      The Keystore object to operate on.
+ * @param[in] owner_id  ID of the key owner.
+ * @param[in] slot     If successful, assigned slot ID.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t * keystore,
+					      uint64_t owner_id, uint32_t slot);
+
+/*!
+ * Load cleartext key data into a key slot
+ *
+ * This function loads a key slot with cleartext data.
+ *
+ * @param keystore      The Keystore object to operate on.
+ * @param[in] owner_id  ID of the key owner.
+ * @param[in] slot      If successful, assigned slot ID.
+ * @param[in] key_data  Pointer to the location of the cleartext key data.
+ * @param[in] key_length Length of the key data (octets).
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot,
+		   const uint8_t * key_data, uint32_t key_length);
+
+/*!
+ * Read cleartext key data from a key slot
+ *
+ * This function returns the key in a key slot.
+ *
+ * @param keystore      The Keystore object to operate on.
+ * @param[in]  owner_id   ID of the key owner.
+ * @param[in]  slot       ID of slot where key resides.
+ * @param[in]  key_length Length of the key data (octets).
+ * @param[out] key_data   Pointer to the location of the cleartext key data.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot,
+		   uint32_t key_length, uint8_t * key_data);
+
+/*!
+ * Encrypt a keyslot
+ *
+ * This function encrypts a key using the hardware secret key.
+ *
+ * @param user_ctx      User context
+ * @param keystore      The Keystore object to operate on.
+ * @param[in] owner_id  ID of the key owner.
+ * @param[in] slot      Slot ID of the key to encrypt.
+ * @param[in] length    Length of the key
+ * @param[out] destination  Pointer to the location where the encrypted data
+ *                          is to be stored.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+keystore_slot_encrypt(fsl_shw_uco_t * user_ctx,
+		      fsl_shw_kso_t * keystore, uint64_t owner_id,
+		      uint32_t slot, uint32_t length, uint8_t * destination);
+
+/*!
+ * Decrypt a keyslot
+ *
+ * This function decrypts a key using the hardware secret key.
+ *
+ * @param user_ctx      User context
+ * @param keystore      The Keystore object to operate on.
+ * @param[in] owner_id  ID of the key owner.
+ * @param[in] slot      Slot ID of the key to encrypt.
+ * @param[in] length    Length of the key
+ * @param[in] source    Pointer to the location where the encrypted data
+ *                      is stored.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+extern fsl_shw_return_t
+keystore_slot_decrypt(fsl_shw_uco_t * user_ctx,
+		      fsl_shw_kso_t * keystore, uint64_t owner_id,
+		      uint32_t slot, uint32_t length, const uint8_t * source);
+
+/* @} */
+
+/*! @addtogroup default_keystore
+    @{ */
+
+/*!
+ * Data structure to hold per-slot information
+ */
+typedef struct keystore_data_slot_info_t {
+	uint8_t allocated;	/*!< Track slot assignments */
+	uint64_t owner;		/*!< Owner IDs */
+	uint32_t key_length;	/*!< Size of the key */
+} keystore_data_slot_info_t;
+
+/*!
+ * Data structure to hold keystore information.
+ */
+typedef struct keystore_data_t {
+	void *base_address;	/*!< Base of the Secure Partition */
+	uint32_t slot_count;	/*!< Number of slots in the keystore */
+	struct keystore_data_slot_info_t *slot;	/*!< Per-slot information */
+} keystore_data_t;
+
+/*!
+ * Default keystore initialization routine.
+ *
+ * This function acquires a Secure Partition Object to store the keystore,
+ * divides it into slots of length #KEYSTORE_SLOT_SIZE, and builds a data
+ * structure to hold key information.
+ *
+ * @param user_ctx       User context
+ * @param[out] user_data Pointer to the location where the keystore data
+ *                       structure is to be stored.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t * user_ctx, void **user_data);
+
+/*!
+ * Default keystore cleanup routine.
+ *
+ * This function releases the Secure Partition Object and the memory holding
+ * the keystore data structure, that obtained by the shw_kso_init_data
+ * function.
+ *
+ * @param user_ctx          User context
+ * @param[in,out] user_data Pointer to the location where the keystore data
+ *                          structure is stored.
+ */
+void shw_kso_cleanup_data(fsl_shw_uco_t * user_ctx, void **user_data);
+
+/*!
+ * Default keystore slot access verification
+ *
+ * This function compares the supplied Owner ID to the registered owner of
+ * the key slot, to see if the supplied ID is correct.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] owner_id  Owner ID supplied as a credential.
+ * @param[in] slot      Requested slot
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id,
+					uint32_t slot);
+
+/*!
+ * Default keystore slot allocation
+ *
+ * This function first checks that the requested size is equal to or less than
+ * the maximum keystore slot size.  If so, it searches the keystore for a free
+ * key slot, and if found, marks it as used and returns a slot reference to the
+ * user.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] size      Size of the key data that will be stored in this slot
+ *                      (octets)
+ * @param[in] owner_id  Owner ID supplied as a credential.
+ * @param[out] slot     Requested slot
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size,
+				uint64_t owner_id, uint32_t * slot);
+
+/*!
+ * Default keystore slot deallocation
+ *
+ * This function releases the given key slot in the keystore, making it
+ * available to store a new key.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] owner_id  Owner ID supplied as a credential.
+ * @param[in] slot      Requested slot
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t shw_slot_dealloc(void *user_data,
+				  uint64_t owner_id, uint32_t slot);
+
+/*!
+ * Default keystore slot address lookup
+ *
+ * This function calculates the address where the key data is stored.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] slot      Requested slot
+ *
+ * @return    SCC2: Virtual address (kernel or userspace) of the key data.
+ *            SCC: Physical address of the key data.
+ */
+void *shw_slot_get_address(void *user_data, uint32_t slot);
+
+/*!
+ * Default keystore slot base address lookup
+ *
+ * This function calculates the base address of the Secure Partition on which
+ * the key data is located.  For the reference design, only one Secure
+ * Partition is used per Keystore, however in general, any number may be used.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] slot      Requested slot
+ *
+ * @return    SCC2: Secure Partition virtual (kernel or userspace) base address.
+ *            SCC: Secure Partition physical base address.
+ */
+uint32_t shw_slot_get_base(void *user_data, uint32_t slot);
+
+/*!
+ * Default keystore slot offset lookup
+ *
+ * This function calculates the offset from the base of the Secure Partition
+ * where the key data is located.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] slot      Requested slot
+ *
+ * @return    SCC2: Key data offset (octets)
+ *            SCC: Not implemented
+ */
+uint32_t shw_slot_get_offset(void *user_data, uint32_t slot);
+
+/*!
+ * Default keystore slot offset lookup
+ *
+ * This function returns the size of the given key slot.  In the reference
+ * implementation, all key slots are of the same size, however in general,
+ * the keystore slot sizes can be made variable.
+ *
+ * @param[in] user_data Pointer to the location where the keystore data
+ *                      structure stored.
+ * @param[in] slot      Requested slot
+ *
+ * @return    SCC2: Keystore slot size.
+ *            SCC: Not implemented
+ */
+uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot);
+
+/* @} */
+
+#endif /* FSL_SHW_KEYSTORE_H */
diff --git a/drivers/mxc/security/sahara2/include/linux_port.h b/drivers/mxc/security/sahara2/include/linux_port.h
new file mode 100644
index 000000000000..492bbf4f893d
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/linux_port.h
@@ -0,0 +1,1806 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file linux_port.h
+ *
+ * OS_PORT ported to Linux (2.6.9+ for now)
+ *
+ */
+
+ /*!
+  * @if USE_MAINPAGE
+  * @mainpage ==Linux version of== Generic OS API for STC Drivers
+  * @endif
+  *
+  * @section intro_sec Introduction
+  *
+  * This API / kernel programming environment blah blah.
+  *
+  * See @ref dkops "Driver-to-Kernel Operations" as a good place to start.
+  */
+
+#ifndef LINUX_PORT_H
+#define LINUX_PORT_H
+
+#define PORTABLE_OS_VERSION 101
+
+/* Linux Kernel Includes */
+#include <linux/version.h>	/* Current version Linux kernel */
+
+#if defined(CONFIG_MODVERSIONS) && ! defined(MODVERSIONS)
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+#include <linux/modversions.h>
+#endif
+#define MODVERSIONS
+#endif
+/*!
+ * __NO_VERSION__ defined due to Kernel module possibly spanning multiple
+ * files.
+ */
+#define __NO_VERSION__
+
+#include <linux/module.h>	/* Basic support for loadable modules,
+				   printk */
+#include <linux/init.h>		/* module_init, module_exit */
+#include <linux/kernel.h>	/* General kernel system calls */
+#include <linux/sched.h>	/* for interrupt.h */
+#include <linux/fs.h>		/* for inode */
+#include <linux/random.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>		/* kmalloc */
+
+#include <stdarg.h>
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+#include <linux/device.h>  /* used in dynamic power management */
+#else
+#include <linux/platform_device.h>  /* used in dynamic power management */
+#endif
+
+#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/clk.h>         /* clock en/disable for DPM */
+
+#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/uaccess.h>            /* copy_to_user(), copy_from_user() */
+#include <asm/io.h>                 /* ioremap() */
+#include <asm/irq.h>
+#include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
+
+#ifndef TRUE
+/*! Useful symbol for unsigned values used as flags. */
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+/*! Useful symbol for unsigned values used as flags. */
+#define FALSE 0
+#endif
+
+/* These symbols are defined in Linux 2.6 and later.  Include here for minimal
+ * support of 2.4 kernel.
+ **/
+#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+/*!
+ * Symbol defined somewhere in 2.5/2.6.  It is the return signature of an ISR.
+ */
+#define irqreturn_t void
+/*! Possible return value of 'modern' ISR routine. */
+#define IRQ_HANDLED
+/*! Method of generating value of 'modern' ISR routine. */
+#define IRQ_RETVAL(x)
+#endif
+
+/*!
+ * Type used for registering and deregistering interrupts.
+ */
+typedef int os_interrupt_id_t;
+
+/*!
+ * Type used as handle for a process
+ *
+ * See #os_get_process_handle() and #os_send_signal().
+ */
+/*
+ * The following should be defined this way, but it gets compiler errors
+ * on the current tool chain.
+ *
+ * typedef task_t *os_process_handle_t;
+ */
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+typedef task_t *os_process_handle_t;
+#else
+typedef struct task_struct *os_process_handle_t;
+#endif
+
+/*!
+ * Generic return code for functions which need such a thing.
+ *
+ * No knowledge should be assumed of the value of any of these symbols except
+ * that @c OS_ERROR_OK_S is guaranteed to be zero.
+ */
+typedef enum {
+	OS_ERROR_OK_S = 0,	/*!< Success  */
+	OS_ERROR_FAIL_S = -EIO,	/*!< Generic driver failure */
+	OS_ERROR_NO_MEMORY_S = -ENOMEM,	/*!< Failure to acquire/use memory  */
+	OS_ERROR_BAD_ADDRESS_S = -EFAULT,	/*!< Bad address  */
+	OS_ERROR_BAD_ARG_S = -EINVAL,	/*!< Bad input argument  */
+} os_error_code;
+
+/*!
+ * Handle to a lock.
+ */
+#ifdef CONFIG_PREEMPT_RT
+typedef raw_spinlock_t *os_lock_t;
+#else
+typedef spinlock_t *os_lock_t;
+#endif
+
+/*!
+ * Context while locking.
+ */
+typedef unsigned long os_lock_context_t;
+
+/*!
+ * Declare a wait object for sleeping/waking processes.
+ */
+#define OS_WAIT_OBJECT(name)                                            \
+    DECLARE_WAIT_QUEUE_HEAD(name##_qh)
+
+/*!
+ * Driver registration handle
+ *
+ * Used with #os_driver_init_registration(), #os_driver_add_registration(),
+ * and #os_driver_complete_registration().
+ */
+typedef struct {
+	unsigned reg_complete;	/*!< TRUE if next inits succeeded. */
+	dev_t dev;		/*!< dev_t for register_chrdev() */
+	struct file_operations fops;	/*!< struct for register_chrdev() */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13)
+	struct class_simple *cs;	/*!< results of class_simple_create() */
+#else
+	struct class *cs;	/*!< results of class_create() */
+#endif
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+	struct class_device *cd;	/*!< Result of class_device_create() */
+#else
+	struct device *cd;	/*!< Result of device_create() */
+#endif
+	unsigned power_complete;	/*!< TRUE if next inits succeeded */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	struct device_driver dd;	/*!< struct for register_driver() */
+#else
+	struct platform_driver dd;	/*!< struct for register_driver() */
+#endif
+	struct platform_device pd;	/*!< struct for platform_register_device() */
+} os_driver_reg_t;
+
+/*
+ *  Function types which can be associated with driver entry points.
+ *
+ *  Note that init and shutdown are absent.
+ */
+/*! @{ */
+/*! Keyword for registering open() operation handler. */
+#define OS_FN_OPEN open
+/*! Keyword for registering close() operation handler. */
+#define OS_FN_CLOSE release
+/*! Keyword for registering read() operation handler. */
+#define OS_FN_READ read
+/*! Keyword for registering write() operation handler. */
+#define OS_FN_WRITE write
+/*! Keyword for registering ioctl() operation handler. */
+#define OS_FN_IOCTL ioctl
+/*! Keyword for registering mmap() operation handler. */
+#define OS_FN_MMAP mmap
+/*! @} */
+
+/*!
+ * Function signature for the portable interrupt handler
+ *
+ * While it would be nice to know which interrupt is being serviced, the
+ * Least Common Denominator rule says that no arguments get passed in.
+ *
+ * @return  Zero if not handled, non-zero if handled.
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+typedef int (*os_interrupt_handler_t) (int, void *, struct pt_regs *);
+#else
+typedef int (*os_interrupt_handler_t) (int, void *);
+#endif
+
+/*!
+ * @defgroup dkops Driver-to-Kernel Operations
+ *
+ * These are the operations which drivers should call to get the OS to perform
+ * services.
+ */
+
+/*! @addtogroup dkops */
+/*! @{ */
+
+/*!
+ * Register an interrupt handler.
+ *
+ * @param driver_name    The name of the driver
+ * @param interrupt_id   The interrupt line to monitor (type
+ *                       #os_interrupt_id_t)
+ * @param function       The function to be called to handle an interrupt
+ *
+ * @return #os_error_code
+ */
+#define os_register_interrupt(driver_name, interrupt_id, function)            \
+     request_irq(interrupt_id, function, 0, driver_name, NULL)
+
+/*!
+ * Deregister an interrupt handler.
+ *
+ * @param interrupt_id   The interrupt line to stop monitoring
+ *
+ * @return #os_error_code
+ */
+#define os_deregister_interrupt(interrupt_id)                                 \
+     free_irq(interrupt_id, NULL)
+
+/*!
+ * INTERNAL implementation of os_driver_init_registration()
+ *
+ * @return An os error code.
+ */
+inline static int os_drv_do_init_reg(os_driver_reg_t * handle)
+{
+	memset(handle, 0, sizeof(*handle));
+	handle->fops.owner = THIS_MODULE;
+	handle->power_complete = FALSE;
+	handle->reg_complete = FALSE;
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	handle->dd.name = NULL;
+#else
+	handle->dd.driver.name = NULL;
+#endif
+
+	return OS_ERROR_OK_S;
+}
+
+/*!
+ * Initialize driver registration.
+ *
+ * If the driver handles open(), close(), ioctl(), read(), write(), or mmap()
+ * calls, then it needs to register their location with the kernel so that they
+ * get associated with the device.
+ *
+ * @param handle  The handle object to be used with this registration.  The
+ *                object must live (be in memory somewhere) at least until
+ *                os_driver_remove_registration() is called.
+ *
+ * @return A handle for further driver registration, or NULL if failed.
+ */
+#define os_driver_init_registration(handle)                                   \
+    os_drv_do_init_reg(&handle)
+
+/*!
+ * Add a function registration to driver registration.
+ *
+ * @param handle    A handle initialized by #os_driver_init_registration().
+ * @param name      Which function is being supported.
+ * @param function  The result of a call to a @c _REF version of one of the
+ *                  driver function signature macros
+ * @return void
+ */
+#define os_driver_add_registration(handle, name, function)                    \
+    do {handle.fops.name = (void*)(function); } while (0)
+
+/*!
+ * Record 'power suspend' function for the device.
+ *
+ * @param handle    A handle initialized by #os_driver_init_registration().
+ * @param function  Name of function to call on power suspend request
+ *
+ * Status: Provisional
+ *
+ * @return void
+ */
+#define os_driver_register_power_suspend(handle, function)                    \
+   handle.dd.suspend = function
+
+/*!
+ * Record 'power resume' function for the device.
+ *
+ * @param handle    A handle initialized by #os_driver_init_registration().
+ * @param function  Name of function to call on power resume request
+ *
+ * Status: Provisional
+ *
+ * @return void
+ */
+#define os_driver_register_resume(handle, function)                          \
+   handle.dd.resume = function
+
+/*!
+ * INTERNAL function of the Linux port of the OS API.   Implements the
+ * os_driver_complete_registration() function.
+ *
+ * @param handle    The handle used with #os_driver_init_registration().
+ * @param major      The major device number to be associated with the driver.
+ *                   If this value is zero, a major number may be assigned.
+ *                   See #os_driver_get_major() to determine final value.
+ *                   #os_driver_remove_registration().
+ * @param driver_name The driver name.  Can be used as part of 'device node'
+ *                   name on platforms which support such a feature.
+ *
+ * @return  An error code
+ */
+inline static int os_drv_do_reg(os_driver_reg_t * handle,
+				unsigned major, char *driver_name)
+{
+	os_error_code code = OS_ERROR_NO_MEMORY_S;
+	char *name = kmalloc(strlen(driver_name) + 1, 0);
+
+	if (name != NULL) {
+		memcpy(name, driver_name, strlen(driver_name) + 1);
+		code = OS_ERROR_OK_S;	/* OK so far */
+		/* If any chardev/POSIX routines were added, then do chrdev part */
+		if (handle->fops.open || handle->fops.release
+		    || handle->fops.read || handle->fops.write
+		    || handle->fops.ioctl || handle->fops.mmap) {
+
+			printk("ioctl pointer: %p.  mmap pointer: %p\n",
+			       handle->fops.ioctl, handle->fops.mmap);
+
+			/* this method is depricated, see:
+			 * http://lwn.net/Articles/126808/
+			 */
+			code =
+			    register_chrdev(major, driver_name, &handle->fops);
+
+			/* instead something like this: */
+#if 0
+			handle->dev = MKDEV(major, 0);
+			code =
+			    register_chrdev_region(handle->dev, 1, driver_name);
+			if (code < 0) {
+				code = OS_ERROR_FAIL_S;
+			} else {
+				cdev_init(&handle->cdev, &handle->fops);
+				code = cdev_add(&handle->cdev, major, 1);
+			}
+#endif
+
+			if (code < 0) {
+				code = OS_ERROR_FAIL_S;
+			} else {
+				if (code != 0) {
+					/* Zero was passed in for major; code is actual value */
+					handle->dev = MKDEV(code, 0);
+				} else {
+					handle->dev = MKDEV(major, 0);
+				}
+				code = OS_ERROR_OK_S;
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13)
+				handle->cs =
+				    class_simple_create(THIS_MODULE,
+							driver_name);
+				if (IS_ERR(handle->cs)) {
+					code = (os_error_code) handle->cs;
+					handle->cs = NULL;
+				} else {
+					handle->cd =
+					    class_simple_device_add(handle->cs,
+								    handle->dev,
+								    NULL,
+								    driver_name);
+					if (IS_ERR(handle->cd)) {
+						class_simple_device_remove
+						    (handle->dev);
+						unregister_chrdev(MAJOR
+								  (handle->dev),
+								  driver_name);
+						code =
+						    (os_error_code) handle->cs;
+						handle->cs = NULL;
+					} else {
+						handle->reg_complete = TRUE;
+					}
+				}
+#else
+				handle->cs =
+				    class_create(THIS_MODULE, driver_name);
+				if (IS_ERR(handle->cs)) {
+					code = (os_error_code) handle->cs;
+					handle->cs = NULL;
+				} else {
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+					handle->cd =
+					    class_device_create(handle->cs,
+								NULL,
+								handle->dev,
+								NULL,
+								driver_name);
+#else
+					handle->cd =
+					    device_create(handle->cs, NULL,
+							  handle->dev, NULL,
+							  driver_name);
+#endif
+					if (IS_ERR(handle->cd)) {
+						class_destroy(handle->cs);
+						unregister_chrdev(MAJOR
+								  (handle->dev),
+								  driver_name);
+						code =
+						    (os_error_code) handle->cs;
+						handle->cs = NULL;
+					} else {
+						handle->reg_complete = TRUE;
+					}
+				}
+#endif
+			}
+		}
+		/* ... fops routine registered */
+		/* Handle power management fns through separate interface */
+		if ((code == OS_ERROR_OK_S) &&
+		    (handle->dd.suspend || handle->dd.resume)) {
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+			handle->dd.name = name;
+			handle->dd.bus = &platform_bus_type;
+			code = driver_register(&handle->dd);
+#else
+			handle->dd.driver.name = name;
+			handle->dd.driver.bus = &platform_bus_type;
+			code = driver_register(&handle->dd.driver);
+#endif
+			if (code == OS_ERROR_OK_S) {
+				handle->pd.name = name;
+				handle->pd.id = 0;
+				code = platform_device_register(&handle->pd);
+				if (code != OS_ERROR_OK_S) {
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+					driver_unregister(&handle->dd);
+#else
+					driver_unregister(&handle->dd.driver);
+#endif
+				} else {
+					handle->power_complete = TRUE;
+				}
+			}
+		}		/* ... suspend or resume */
+	}			/* name != NULL */
+	return code;
+}
+
+/*!
+ * Finalize the driver registration with the kernel.
+ *
+ * Upon return from this call, the driver may begin receiving calls at the
+ * defined entry points.
+ *
+ * @param handle    The handle used with #os_driver_init_registration().
+ * @param major      The major device number to be associated with the driver.
+ *                   If this value is zero, a major number may be assigned.
+ *                   See #os_driver_get_major() to determine final value.
+ *                   #os_driver_remove_registration().
+ * @param driver_name The driver name.  Can be used as part of 'device node'
+ *                   name on platforms which support such a feature.
+ *
+ * @return  An error code
+ */
+#define os_driver_complete_registration(handle, major, driver_name)           \
+   os_drv_do_reg(&handle, major, driver_name)
+
+/*!
+ * Get driver Major Number from handle after a successful registration.
+ *
+ * @param   handle  A handle which has completed registration.
+ *
+ * @return The major number (if any) associated with the handle.
+ */
+#define os_driver_get_major(handle)                                           \
+    (handle.reg_complete ? MAJOR(handle.dev) : -1)
+
+/*!
+ * INTERNAL implemention of os_driver_remove_registration.
+ *
+ * @param handle    A handle initialized by #os_driver_init_registration().
+ *
+ * @return  An error code.
+ */
+inline static int os_drv_rmv_reg(os_driver_reg_t * handle)
+{
+	if (handle->reg_complete) {
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13)
+		if (handle->cd != NULL) {
+			class_simple_device_remove(handle->dev);
+			handle->cd = NULL;
+		}
+		if (handle->cs != NULL) {
+			class_simple_destroy(handle->cs);
+			handle->cs = NULL;
+		}
+		unregister_chrdev(MAJOR(handle->dev), handle->dd.name);
+#else
+		if (handle->cd != NULL) {
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+			class_device_destroy(handle->cs, handle->dev);
+#else
+			device_destroy(handle->cs, handle->dev);
+#endif
+			handle->cd = NULL;
+		}
+		if (handle->cs != NULL) {
+			class_destroy(handle->cs);
+			handle->cs = NULL;
+		}
+		unregister_chrdev(MAJOR(handle->dev), handle->dd.driver.name);
+#endif
+		handle->reg_complete = FALSE;
+	}
+	if (handle->power_complete) {
+		platform_device_unregister(&handle->pd);
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+		driver_unregister(&handle->dd);
+#else
+		driver_unregister(&handle->dd.driver);
+#endif
+		handle->power_complete = FALSE;
+	}
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	if (handle->dd.name != NULL) {
+		kfree(handle->dd.name);
+		handle->dd.name = NULL;
+	}
+#else
+	if (handle->dd.driver.name != NULL) {
+		kfree(handle->dd.driver.name);
+		handle->dd.driver.name = NULL;
+	}
+#endif
+	return OS_ERROR_OK_S;
+}
+
+/*!
+ * Remove the driver's registration with the kernel.
+ *
+ * Upon return from this call, the driver not receive any more calls at the
+ * defined entry points (other than ISR and shutdown).
+ *
+ * @param handle    A handle initialized by #os_driver_init_registration().
+ *
+ * @return  An error code.
+ */
+#define os_driver_remove_registration(handle)                                 \
+   os_drv_rmv_reg(&handle)
+
+/*!
+ * Register a driver with the Linux Device Model.
+ *
+ * @param   driver_information  The device_driver structure information
+ *
+ * @return  An error code.
+ *
+ * Status: denigrated in favor of #os_driver_complete_registration()
+ */
+#define os_register_to_driver(driver_information)                             \
+              driver_register(driver_information)
+
+/*!
+ * Unregister a driver from the Linux Device Model
+ *
+ * this routine unregisters from the Linux Device Model
+ *
+ * @param   driver_information  The device_driver structure information
+ *
+ * @return  An error code.
+ *
+ * Status: Denigrated. See #os_register_to_driver().
+ */
+#define os_unregister_from_driver(driver_information)                         \
+                driver_unregister(driver_information)
+
+/*!
+ * register a device to a driver
+ *
+ * this routine registers a drivers devices to the Linux Device Model
+ *
+ * @param   device_information  The platform_device structure information
+ *
+ * @return  An error code.
+ *
+ * Status: denigrated in favor of #os_driver_complete_registration()
+ */
+#define os_register_a_device(device_information)                              \
+    platform_device_register(device_information)
+
+/*!
+ * unregister a device from a driver
+ *
+ * this routine unregisters a drivers devices from the Linux Device Model
+ *
+ * @param   device_information  The platform_device structure information
+ *
+ * @return  An error code.
+ *
+ * Status: Denigrated.  See #os_register_a_device().
+ */
+#define os_unregister_a_device(device_information)                            \
+    platform_device_unregister(device_information)
+
+/*!
+ * Print a message to console / into log file.  After the @c msg argument a
+ * number of printf-style arguments may be added.  Types should be limited to
+ * printf string, char, octal, decimal, and hexadecimal types.  (This excludes
+ * pointers, and floating point).
+ *
+ * @param  msg    The main text of the message to be logged
+ * @param  s      The printf-style arguments which go with msg, if any
+ *
+ * @return (void)
+ */
+#define os_printk(...)                                                        \
+    (void) printk(__VA_ARGS__)
+
+/*!
+ * Prepare a task to execute the given function.  This should only be done once
+ * per function,, during the driver's initialization routine.
+ *
+ * @param task_fn   Name of the OS_DEV_TASK() function to be created.
+ *
+ * @return an OS ERROR code.
+ */
+#define os_create_task(function_name)                                         \
+    OS_ERROR_OK_S
+
+/*!
+ * Schedule execution of a task.
+ *
+ * @param function_name   The function associated with the task.
+ *
+ * @return (void)
+ */
+#define os_dev_schedule_task(function_name)                                   \
+    tasklet_schedule(&(function_name ## let))
+
+/*!
+ * Make sure that task is no longer running and will no longer run.
+ *
+ * This function will not return until both are true.  This is useful when
+ * shutting down a driver.
+ */
+#define os_dev_stop_task(function_name)                                       \
+do {                                                                          \
+    tasklet_disable(&(function_name ## let));                                 \
+    tasklet_kill(&(function_name ## let));                                    \
+} while (0)
+
+/*!
+ * Allocate some kernel memory
+ *
+ * @param amount   Number of 8-bit bytes to allocate
+ * @param flags    Some indication of purpose of memory (needs definition)
+ *
+ * @return  Pointer to allocated memory, or NULL if failed.
+ */
+#define os_alloc_memory(amount, flags)                                        \
+    (void*)kmalloc(amount, flags)
+
+/*!
+ * Free some kernel memory
+ *
+ * @param location  The beginning of the region to be freed.
+ *
+ * Do some OSes have separate free() functions which should be
+ * distinguished by passing in @c flags here, too? Don't some also require the
+ * size of the buffer being freed?
+ */
+#define os_free_memory(location)                                              \
+    kfree(location)
+
+/*!
+ * Allocate cache-coherent memory
+ *
+ * @param       amount     Number of bytes to allocate
+ * @param[out]  dma_addrp  Location to store physical address of allocated
+ *                         memory.
+ * @param       flags      Some indication of purpose of memory (needs
+ *                         definition).
+ *
+ * @return (virtual space) pointer to allocated memory, or NULL if failed.
+ *
+ */
+#define os_alloc_coherent(amount, dma_addrp, flags)                           \
+    (void*)dma_alloc_coherent(NULL, amount, dma_addrp, flags)
+
+/*!
+ * Free cache-coherent memory
+ *
+ * @param       size       Number of bytes which were allocated.
+ * @param       virt_addr  Virtual(kernel) address of memory.to be freed, as
+ *                         returned by #os_alloc_coherent().
+ * @param       dma_addr   Physical address of memory.to be freed, as returned
+ *                         by #os_alloc_coherent().
+ *
+ * @return void
+ *
+ */
+#define os_free_coherent(size, virt_addr, dma_addr)                           \
+    dma_free_coherent(NULL, size, virt_addr, dma_addr
+
+/*!
+ * Map an I/O space into kernel memory space
+ *
+ * @param start       The starting address of the (physical / io space) region
+ * @param range_bytes The number of bytes to map
+ *
+ * @return A pointer to the mapped area, or NULL on failure
+ */
+#define os_map_device(start, range_bytes)                                     \
+    (void*)ioremap_nocache((start), range_bytes)
+
+/*!
+ * Unmap an I/O space from kernel memory space
+ *
+ * @param start       The starting address of the (virtual) region
+ * @param range_bytes The number of bytes to unmap
+ *
+ * @return None
+ */
+#define os_unmap_device(start, range_bytes)                                   \
+    iounmap((void*)(start))
+
+/*!
+ * Copy data from Kernel space to User space
+ *
+ * @param to   The target location in user memory
+ * @param from The source location in kernel memory
+ * @param size The number of bytes to be copied
+ *
+ * @return #os_error_code
+ */
+#define os_copy_to_user(to, from, size)                                       \
+    ((copy_to_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S)
+
+/*!
+ * Copy data from User space to Kernel space
+ *
+ * @param to   The target location in kernel memory
+ * @param from The source location in user memory
+ * @param size The number of bytes to be copied
+ *
+ * @return #os_error_code
+ */
+#define os_copy_from_user(to, from, size)                                     \
+    ((copy_from_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S)
+
+/*!
+ * Read a 8-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+#define os_read8(register_address)                                            \
+    __raw_readb(register_address)
+
+/*!
+ * Write a 8-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+#define os_write8(register_address, value)                                    \
+    __raw_writeb(value, register_address)
+
+/*!
+ * Read a 16-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+#define os_read16(register_address)                                           \
+    __raw_readw(register_address)
+
+/*!
+ * Write a 16-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+#define os_write16(register_address, value)                                   \
+    __raw_writew(value, (uint32_t*)(register_address))
+
+/*!
+ * Read a 32-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+#define os_read32(register_address)                                           \
+    __raw_readl((uint32_t*)(register_address))
+
+/*!
+ * Write a 32-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+#define os_write32(register_address, value)                                   \
+    __raw_writel(value, register_address)
+
+/*!
+ * Read a 64-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+#define os_read64(register_address)                                           \
+     ERROR_UNIMPLEMENTED
+
+/*!
+ * Write a 64-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+#define os_write64(register_address, value)                                   \
+    ERROR_UNIMPLEMENTED
+
+/*!
+ * Delay some number of microseconds
+ *
+ * Note that this is a busy-loop, not a suspension of the task/process.
+ *
+ * @param  msecs   The number of microseconds to delay
+ *
+ * @return void
+ */
+#define os_mdelay mdelay
+
+/*!
+ * Calculate virtual address from physical address
+ *
+ * @param pa    Physical address
+ *
+ * @return virtual address
+ *
+ * @note this assumes that addresses are 32 bits wide
+ */
+#define os_va __va
+
+/*!
+ * Calculate physical address from virtual address
+ *
+ *
+ * @param va    Virtual address
+ *
+ * @return physical address
+ *
+ * @note this assumes that addresses are 32 bits wide
+ */
+#define os_pa __pa
+
+#ifdef CONFIG_PREEMPT_RT
+/*!
+ * Allocate and initialize a lock, returning a lock handle.
+ *
+ * The lock state will be initialized to 'unlocked'.
+ *
+ * @return A lock handle, or NULL if an error occurred.
+ */
+inline static os_lock_t os_lock_alloc_init(void)
+{
+	raw_spinlock_t *lockp;
+	lockp = (raw_spinlock_t *) kmalloc(sizeof(raw_spinlock_t), 0);
+	if (lockp) {
+		_raw_spin_lock_init(lockp);
+	} else {
+		printk("OS: lock init failed\n");
+	}
+
+	return lockp;
+}
+#else
+/*!
+ * Allocate and initialize a lock, returning a lock handle.
+ *
+ * The lock state will be initialized to 'unlocked'.
+ *
+ * @return A lock handle, or NULL if an error occurred.
+ */
+inline static os_lock_t os_lock_alloc_init(void)
+{
+	spinlock_t *lockp;
+	lockp = (spinlock_t *) kmalloc(sizeof(spinlock_t), 0);
+	if (lockp) {
+		spin_lock_init(lockp);
+	} else {
+		printk("OS: lock init failed\n");
+	}
+
+	return lockp;
+}
+#endif				/* CONFIG_PREEMPT_RT */
+
+/*!
+ * Acquire a lock.
+ *
+ * This function should only be called from an interrupt service routine.
+ *
+ * @param   lock_handle  A handle to the lock to acquire.
+ *
+ * @return void
+ */
+#define os_lock(lock_handle)                                              \
+   spin_lock(lock_handle)
+
+/*!
+ * Unlock a lock.  Lock must have been acquired by #os_lock().
+ *
+ * @param   lock_handle  A handle to the lock to unlock.
+ *
+ * @return void
+ */
+#define os_unlock(lock_handle)                                            \
+   spin_unlock(lock_handle)
+
+/*!
+ * Acquire a lock in non-ISR context
+ *
+ * This function will spin until the lock is available.
+ *
+ * @param lock_handle  A handle of the lock to acquire.
+ * @param context      Place to save the before-lock context
+ *
+ * @return void
+ */
+#define os_lock_save_context(lock_handle, context)                        \
+    spin_lock_irqsave(lock_handle, context)
+
+/*!
+ * Release a lock in non-ISR context
+ *
+ * @param lock_handle  A handle of the lock to release.
+ * @param context      Place where before-lock context was saved.
+ *
+ * @return void
+ */
+#define os_unlock_restore_context(lock_handle, context)                  \
+    spin_unlock_irqrestore(lock_handle, context)
+
+/*!
+ * Deallocate a lock handle.
+ *
+ * @param lock_handle   An #os_lock_t that has been allocated.
+ *
+ * @return void
+ */
+#define os_lock_deallocate(lock_handle)                                   \
+    kfree(lock_handle)
+
+/*!
+ * Determine process handle
+ *
+ * The process handle of the current user is returned.
+ *
+ * @return   A handle on the current process.
+ */
+#define os_get_process_handle()                                           \
+    current
+
+/*!
+ * Send a signal to a process
+ *
+ * @param  proc   A handle to the target process.
+ * @param  sig    The POSIX signal to send to that process.
+ */
+#define os_send_signal(proc, sig)                                         \
+    send_sig(sig, proc, 0);
+
+/*!
+ * Get some random bytes
+ *
+ * @param buf    The location to store the random data.
+ * @param count  The number of bytes to store.
+ *
+ * @return  void
+ */
+#define os_get_random_bytes(buf, count)                                   \
+    get_random_bytes(buf, count)
+
+/*!
+ * Go to sleep on an object.
+ *
+ * @param object    The object on which to sleep
+ * @param condition An expression to check for sleep completion.  Must be
+ *                  coded so that it can be referenced more than once inside
+ *                  macro, i.e., no ++ or other modifying expressions.
+ * @param atomic    Non-zero if sleep must not return until condition.
+ *
+ * @return error code -- OK or sleep interrupted??
+ */
+#define os_sleep(object, condition, atomic)                             \
+({                                                                      \
+    DEFINE_WAIT(_waitentry_);                                           \
+    os_error_code code = OS_ERROR_OK_S;                                 \
+                                                                        \
+    while (!(condition)) {                                              \
+        prepare_to_wait(&(object##_qh), &_waitentry_,                   \
+                        atomic ? 0 : TASK_INTERRUPTIBLE);               \
+        if (!(condition)) {                                             \
+            schedule();                                                 \
+        }                                                               \
+                                                                        \
+        finish_wait(&(object##_qh), &_waitentry_);                      \
+                                                                        \
+        if (!atomic && signal_pending(current)) {                       \
+            code = OS_ERROR_FAIL_S; /* NEED SOMETHING BETTER */         \
+            break;                                                      \
+        }                                                               \
+    };                                                                  \
+                                                                        \
+    code;                                                               \
+})
+
+/*!
+ * Wake up whatever is sleeping on sleep object
+ *
+ * @param object  The object on which things might be sleeping
+ *
+ * @return none
+ */
+#define os_wake_sleepers(object)                                        \
+    wake_up_interruptible(&(object##_qh));
+
+	  /*! @} *//* dkops */
+
+/******************************************************************************
+ *  Function signature-generating macros
+ *****************************************************************************/
+
+/*!
+ * @defgroup drsigs Driver Signatures
+ *
+ * These macros will define the entry point signatures for interrupt handlers;
+ * driver initialization and shutdown; device open/close; etc.
+ *
+ * There are two versions of each macro for a given Driver Entry Point.  The
+ * first version is used to define a function and its implementation in the
+ * driver.c file, e.g. #OS_DEV_INIT().
+ *
+ * The second form is used whenever a forward declaration (prototype) is
+ * needed.  It has the letters @c _DCL appended to the name of the defintion
+ * function, and takes only the first two arguments (driver_name and
+ * function_name).  These are not otherwise mentioned in this documenation.
+ *
+ * There is a third form used when a reference to a function is required, for
+ * instance when passing the routine as a pointer to a function.  It has the
+ * letters @c _REF appended to it, and takes only the first two arguments
+ * (driver_name and function_name).  These functions are not otherwise
+ * mentioned in this documentation.
+ *
+ * (Note that these two extra forms are required because of the
+ * possibility/likelihood of having a 'wrapper function' which invokes the
+ * generic function with expected arguments.  An alternative would be to have a
+ * generic function which isn't able to get at any arguments directly, but
+ * would be equipped with macros which could get at information passed in.
+ *
+ * Example:
+ *
+ * (in a header file)
+ * @code
+ * OS_DEV_INIT_DCL(widget, widget_init);
+ * @endcode
+ *
+ * (in an implementation file)
+ * @code
+ * OS_DEV_INIT(widget, widget_init)
+ * {
+ *     os_dev_init_return(TRUE);
+ * }
+ * @endcode
+ *
+ */
+
+/*! @addtogroup drsigs */
+/*! @{ */
+
+/*!
+ * Define a function which will handle device initialization
+ *
+ * This is tne driver initialization routine.  This is normally where the
+ * part would be initialized; queues, locks, interrupts handlers defined;
+ * long-term dynamic memory allocated for driver use; etc.
+ *
+ * @param function_name   The name of the portable initialization function.
+ *
+ * @return  A call to #os_dev_init_return()
+ *
+ */
+#define OS_DEV_INIT(function_name)                                            \
+module_init(function_name);                                                   \
+static int __init function_name (void)
+
+/*! Make declaration for driver init function.
+ * @param function_name foo
+ */
+#define OS_DEV_INIT_DCL(function_name)                                        \
+static int __init function_name (void);
+
+/*!
+ * Generate a function reference to the driver's init function.
+ * @param function_name   Name of the OS_DEV_INIT() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_INIT_REF(function_name)                                        \
+function_name
+
+/*!
+ * Define a function which will handle device shutdown
+ *
+ * This is the inverse of the #OS_DEV_INIT() routine.
+ *
+ * @param function_name   The name of the portable driver shutdown routine.
+ *
+ * @return  A call to #os_dev_shutdown_return()
+ *
+ */
+#define OS_DEV_SHUTDOWN(function_name)                                        \
+module_exit(function_name);                                                   \
+static void function_name(void)
+
+/*!
+ * Generate a function reference to the driver's shutdown function.
+ * @param function_name   Name of the OS_DEV_HUSTDOWN() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_SHUTDOWN_DCL(function_name)                                    \
+static void function_name(void);
+
+/*!
+ * Generate a reference to driver's shutdown function
+ * @param function_name   Name of the OS_DEV_HUSTDOWN() function.
+*/
+
+#define OS_DEV_SHUTDOWN_REF(function_name)                                    \
+function_name
+
+/*!
+ * Define a function which will open the device for a user.
+ *
+ * @param function_name The name of the driver open() function
+ *
+ * @return  A call to #os_dev_open_return()
+ */
+#define OS_DEV_OPEN(function_name)                                            \
+static int function_name(struct inode* inode_p_, struct file* file_p_)
+
+/*!
+ * Declare prototype for an open() function.
+ *
+ * @param function_name The name of the OS_DEV_OPEN() function.
+ */
+#define OS_DEV_OPEN_DCL(function_name)                                        \
+OS_DEV_OPEN(function_name);
+
+/*!
+ * Generate a function reference to the driver's open() function.
+ * @param function_name   Name of the OS_DEV_OPEN() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_OPEN_REF(function_name)                                        \
+function_name
+
+/*!
+ * Define a function which will handle a user's ioctl() request
+ *
+ * @param function_name The name of the driver ioctl() function
+ *
+ * @return A call to #os_dev_ioctl_return()
+ */
+#define OS_DEV_IOCTL(function_name)                                           \
+static int function_name(struct inode* inode_p_, struct file* file_p_,        \
+                     unsigned int cmd_, unsigned long data_)
+
+/*! Boo. */
+#define OS_DEV_IOCTL_DCL(function_name)                                       \
+OS_DEV_IOCTL(function_name);
+
+/*!
+ * Generate a function reference to the driver's ioctl() function.
+ * @param function_name   Name of the OS_DEV_IOCTL() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_IOCTL_REF(function_name)                                       \
+function_name
+
+/*!
+ * Define a function which will handle a user's mmap() request
+ *
+ * @param function_name The name of the driver mmap() function
+ *
+ * @return A call to #os_dev_ioctl_return()
+ */
+#define OS_DEV_MMAP(function_name)                                            \
+int function_name(struct file* file_p_, struct vm_area_struct* vma_)
+
+#define OS_DEV_MMAP_DCL(function_name)                                        \
+OS_DEV_MMAP(function_name);
+
+#define OS_DEV_MMAP_REF(function_name)                                        \
+function_name
+
+/* Retrieve the context to the memory structure that is to be MMAPed */
+#define os_mmap_memory_ctx() (vma_)
+
+/* Determine the size of the requested MMAP region*/
+#define os_mmap_memory_size() (vma_->vm_end - vma_->vm_start)
+
+/* Determine the base address of the requested MMAP region*/
+#define os_mmap_user_base() (vma_->vm_start)
+
+/*!
+ * Declare prototype for an read() function.
+ *
+ * @param function_name The name of the driver read function.
+ */
+#define OS_DEV_READ_DCL(function_name)                                        \
+OS_DEV_READ(function_name);
+
+/*!
+ * Generate a function reference to the driver's read() routine
+ * @param function_name   Name of the OS_DEV_READ() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_READ_REF(function_name)                                        \
+function_name
+
+/*!
+ * Define a function which will handle a user's write() request
+ *
+ * @param function_name The name of the driver write() function
+ *
+ * @return A call to #os_dev_write_return()
+ */
+#define OS_DEV_WRITE(function_name)                                           \
+static ssize_t function_name(struct file* file_p_, char* user_buffer_,        \
+                     size_t count_bytes_, loff_t* file_position_)
+
+/*!
+ * Declare prototype for an write() function.
+ *
+ * @param function_name The name of the driver write function.
+ */
+#define OS_DEV_WRITE_DCL(function_name)                                       \
+OS_DEV_WRITE(function_name);
+
+/*!
+ * Generate a function reference to the driver's write() routine
+ * @param function_name   Name of the OS_DEV_WRITE() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_WRITE_REF(function_name)                                       \
+function_name
+
+/*!
+ * Define a function which will close the device - opposite of OS_DEV_OPEN()
+ *
+ * @param function_name The name of the driver close() function
+ *
+ * @return A call to #os_dev_close_return()
+ */
+#define OS_DEV_CLOSE(function_name)                                           \
+static int function_name(struct inode* inode_p_, struct file* file_p_)
+
+/*!
+ * Declare prototype for an close() function
+ *
+ * @param function_name The name of the driver close() function.
+ */
+#define OS_DEV_CLOSE_DCL(function_name)                                       \
+OS_DEV_CLOSE(function_name);
+
+/*!
+ * Generate a function reference to the driver's close function.
+ * @param function_name   Name of the OS_DEV_CLOSE() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_CLOSE_REF(function_name)                                       \
+function_name
+
+/*!
+ * Define a function which will handle an interrupt
+ *
+ * No arguments are available to the generic function.  It must not invoke any
+ * OS functions which are illegal in a ISR.  It gets no parameters, and must
+ * have a call to #os_dev_isr_return() instead of any/all return statements.
+ *
+ * Example:
+ * @code
+ * OS_DEV_ISR(widget)
+ * {
+ *     os_dev_isr_return(1);
+ * }
+ * @endcode
+ *
+ * @param function_name The name of the driver ISR function
+ *
+ * @return   A call to #os_dev_isr_return()
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+#define OS_DEV_ISR(function_name)                                             \
+static irqreturn_t function_name(int N1_, void* N2_, struct pt_regs* N3_)
+#else
+#define OS_DEV_ISR(function_name)                                             \
+static irqreturn_t function_name(int N1_, void* N2_)
+#endif
+
+/*!
+ * Declare prototype for an ISR function.
+ *
+ * @param function_name The name of the driver ISR function.
+ */
+#define OS_DEV_ISR_DCL(function_name)                                         \
+OS_DEV_ISR(function_name);
+
+/*!
+ * Generate a function reference to the driver's interrupt service routine
+ * @param function_name   Name of the OS_DEV_ISR() function.
+ *
+ * @return A function pointer.
+ */
+#define OS_DEV_ISR_REF(function_name)                                         \
+function_name
+
+/*!
+ * Define a function which will operate as a background task / bottom half.
+ *
+ * Tasklet stuff isn't strictly limited to 'Device drivers', but leave it
+ * this namespace anyway.
+ *
+ * @param function_name The name of this background task function
+ *
+ * @return A call to #os_dev_task_return()
+ */
+#define OS_DEV_TASK(function_name)                                            \
+static void function_name(unsigned long data_)
+
+/*!
+ * Declare prototype for a background task / bottom half function
+ *
+ * @param function_name The name of this background task function
+ */
+#define OS_DEV_TASK_DCL(function_name)                                        \
+OS_DEV_TASK(function_name);                                                   \
+DECLARE_TASKLET(function_name ## let, function_name, 0);
+
+/*!
+ * Generate a reference to an #OS_DEV_TASK() function
+ *
+ * @param function_name   The name of the task being referenced.
+ */
+#define OS_DEV_TASK_REF(function_name)                                        \
+    (function_name ## let)
+
+	  /*! @} *//* drsigs */
+
+/*****************************************************************************
+ *  Functions/Macros for returning values from Driver Signature routines
+ *****************************************************************************/
+
+/*!
+ * Return from the #OS_DEV_INIT() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_init_return(code)                                             \
+    return code
+
+/*!
+ * Return from the #OS_DEV_SHUTDOWN() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_shutdown_return(code)                                         \
+    return
+
+/*!
+ * Return from the #OS_DEV_ISR() function
+ *
+ * The function should verify that it really was supposed to be called,
+ * and that its device needed attention, in order to properly set the
+ * return code.
+ *
+ * @param code    non-zero if interrupt handled, zero otherwise.
+ *
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+#define os_dev_isr_return(code)                                              \
+do {                                                                         \
+    /* Unused warnings */                                                    \
+    (void)N1_;                                                               \
+    (void)N2_;                                                               \
+    (void)N3_;                                                               \
+                                                                             \
+    return IRQ_RETVAL(code);                                                 \
+} while (0)
+#else
+#define os_dev_isr_return(code)                                              \
+do {                                                                         \
+    /* Unused warnings */                                                    \
+    (void)N1_;                                                               \
+    (void)N2_;                                                               \
+                                                                             \
+    return IRQ_RETVAL(code);                                                 \
+} while (0)
+#endif
+
+/*!
+ * Return from the #OS_DEV_OPEN() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_open_return(code)                                             \
+do {                                                                         \
+    int retcode = code;                                                      \
+                                                                             \
+    /* get rid of 'unused parameter' warnings */                             \
+    (void)inode_p_;                                                          \
+    (void)file_p_;                                                           \
+                                                                             \
+    return retcode;                                                          \
+} while (0)
+
+/*!
+ * Return from the #OS_DEV_IOCTL() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_ioctl_return(code)                                            \
+do {                                                                         \
+    int retcode = code;                                                      \
+                                                                             \
+    /* get rid of 'unused parameter' warnings */                             \
+    (void)inode_p_;                                                          \
+    (void)file_p_;                                                           \
+    (void)cmd_;                                                              \
+    (void)data_;                                                             \
+                                                                             \
+    return retcode;                                                          \
+} while (0)
+
+/*!
+ * Return from the #OS_DEV_READ() function
+ *
+ * @param code    Number of bytes read, or an error code to report failure.
+ *
+ */
+#define os_dev_read_return(code)                                             \
+do {                                                                         \
+    ssize_t retcode = code;                                                  \
+                                                                             \
+    /* get rid of 'unused parameter' warnings */                             \
+    (void)file_p_;                                                           \
+    (void)user_buffer_;                                                      \
+    (void)count_bytes_;                                                      \
+    (void)file_position_;                                                    \
+                                                                             \
+    return retcode;                                                          \
+} while (0)
+
+/*!
+ * Return from the #OS_DEV_WRITE() function
+ *
+ * @param code    Number of bytes written, or an error code to report failure.
+ *
+ */
+#define os_dev_write_return(code)                                            \
+do {                                                                         \
+    ssize_t retcode = code;                                                  \
+                                                                             \
+    /* get rid of 'unused parameter' warnings */                             \
+    (void)file_p_;                                                           \
+    (void)user_buffer_;                                                      \
+    (void)count_bytes_;                                                      \
+    (void)file_position_;                                                    \
+                                                                             \
+    return retcode;                                                          \
+} while (0)
+
+/*!
+ * Return from the #OS_DEV_CLOSE() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_close_return(code)                                            \
+do {                                                                         \
+    ssize_t retcode = code;                                                  \
+                                                                             \
+    /* get rid of 'unused parameter' warnings */                             \
+    (void)inode_p_;                                                          \
+    (void)file_p_;                                                           \
+                                                                             \
+    return retcode;                                                          \
+} while (0)
+
+/*!
+ * Start the #OS_DEV_TASK() function
+ *
+ * In some implementations, this could be turned into a label for
+ * the os_dev_task_return() call.
+ *
+ * @return none
+ */
+#define os_dev_task_begin()
+
+/*!
+ * Return from the #OS_DEV_TASK() function
+ *
+ * In some implementations, this could be turned into a sleep followed
+ * by a jump back to the os_dev_task_begin() call.
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+#define os_dev_task_return(code)                                             \
+do {                                                                         \
+    /* Unused warnings */                                                    \
+    (void)data_;                                                             \
+                                                                             \
+    return;                                                                  \
+} while (0)
+
+/*****************************************************************************
+ *  Functions/Macros for accessing arguments from Driver Signature routines
+ *****************************************************************************/
+
+/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions
+ *
+ */
+/* @addtogroup @drsigargs */
+/*! @{ */
+/*!
+ * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and
+ * #OS_DEV_WRITE() routines to check whether user is requesting read
+ * (permission)
+ */
+#define os_dev_is_flag_read()                                                 \
+   (file_p_->f_mode & FMODE_READ)
+
+/*!
+ * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and
+ * #OS_DEV_WRITE() routines to check whether user is requesting write
+ * (permission)
+ */
+#define os_dev_is_flag_write()                                                \
+   (file_p_->f_mode & FMODE_WRITE)
+
+/*!
+ * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and
+ * #OS_DEV_WRITE() routines to check whether user is requesting non-blocking
+ * I/O.
+ */
+#define os_dev_is_flag_nonblock()                                             \
+   (file_p_->f_flags & (O_NONBLOCK | O_NDELAY))
+
+/*!
+ * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine major device being
+ * accessed.
+ */
+#define os_dev_get_major()                                                    \
+    (imajor(inode_p_))
+
+/*!
+ * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine minor device being
+ * accessed.
+ */
+#define os_dev_get_minor()                                                    \
+    (iminor(inode_p_))
+
+/*!
+ * Used in #OS_DEV_IOCTL() to determine which operation the user wants
+ * performed.
+ *
+ * @return Value of the operation.
+ */
+#define os_dev_get_ioctl_op()                                                 \
+    (cmd_)
+
+/*!
+ * Used in #OS_DEV_IOCTL() to return the associated argument for the desired
+ * operation.
+ *
+ * @return    A value which can be cast to a struct pointer or used as
+ *            int/long.
+ */
+#define os_dev_get_ioctl_arg()                                                \
+    (data_)
+
+/*!
+ * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to access the requested
+ * byte count.
+ *
+ * @return  (unsigned) a count of bytes
+ */
+#define os_dev_get_count()                                                    \
+    ((unsigned)count_bytes_)
+
+/*!
+ * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to return the pointer
+ * byte count.
+ *
+ * @return   char* pointer to user buffer
+ */
+#define os_dev_get_user_buffer()                                              \
+    ((void*)user_buffer_)
+
+/*!
+ * Used in OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines to
+ * get the POSIX flags field for the associated open file).
+ *
+ * @return The flags associated with the file.
+ */
+#define os_dev_get_file_flags()                                               \
+    (file_p_->f_flags)
+
+/*!
+ * Set the driver's private structure associated with this file/open.
+ *
+ * Generally used during #OS_DEV_OPEN().  See #os_dev_get_user_private().
+ *
+ * @param  struct_p   The driver data structure to associate with this user.
+ */
+#define os_dev_set_user_private(struct_p)                                     \
+    file_p_->private_data = (void*)(struct_p)
+
+/*!
+ * Get the driver's private structure associated with this file.
+ *
+ * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(),
+ * #OS_DEV_IOCTL(), and #OS_DEV_CLOSE().  See #os_dev_set_user_private().
+ *
+ * @return   The driver data structure to associate with this user.
+ */
+#define os_dev_get_user_private()                                             \
+    ((void*)file_p_->private_data)
+
+/*!
+ * Get the IRQ associated with this call to the #OS_DEV_ISR() function.
+ *
+ * @return  The IRQ (integer) interrupt number.
+ */
+#define os_dev_get_irq()                                                      \
+    N1_
+
+	   /*! @} *//* drsigargs */
+
+/*!
+ * @defgroup cacheops Cache Operations
+ *
+ * These functions are for synchronizing processor cache with RAM.
+ */
+/*! @addtogroup cacheops */
+/*! @{ */
+
+/*!
+ * Flush and invalidate all cache lines.
+ */
+#if 0
+#define os_flush_cache_all()                                              \
+    flush_cache_all()
+#else
+/* Call ARM fn directly, in case L2cache=on3 not set */
+#define os_flush_cache_all()                                              \
+    v6_flush_kern_cache_all_L2()
+
+/*!
+ * ARM-routine to flush all cache.  Defined here, because it exists in no
+ * easy-access header file.  ARM-11 with L210 cache only!
+ */
+extern void v6_flush_kern_cache_all_L2(void);
+#endif
+
+/*
+ *  These macros are using part of the Linux DMA API.  They rely on the
+ *  map function to do nothing more than the equivalent clean/inv/flush
+ *  operation at the time of the mapping, and do nothing at an unmapping
+ *  call, which the Sahara driver code will never invoke.
+ */
+
+/*!
+ * Clean a range of addresses from the cache.  That is, write updates back
+ * to (RAM, next layer).
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ *
+ * @return void
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
+#define os_cache_clean_range(start,len)                                   \
+    dma_map_single(NULL, (void*)start, len, DMA_TO_DEVICE)
+#else
+#define os_cache_clean_range(start,len)                                   \
+{                                                                         \
+    void *s = (void*)start;                                               \
+    void *e = s + len;                                                    \
+    dmac_clean_range(s, e);                                               \
+    outer_clean_range(__pa(s), __pa(e));                                  \
+}
+#endif
+
+/*!
+ * Invalidate a range of addresses in the cache
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ *
+ * @return void
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
+#define os_cache_inv_range(start,len)                                     \
+    dma_map_single(NULL, (void*)start, len, DMA_FROM_DEVICE)
+#else
+#define os_cache_inv_range(start,len)                                     \
+{                                                                         \
+    void *s = (void*)start;                                               \
+    void *e = s + len;                                                    \
+    dmac_inv_range(s, e);                                                 \
+    outer_inv_range(__pa(s), __pa(e));                                    \
+}
+#endif
+
+/*!
+ * Flush a range of addresses from the cache.  That is, perform clean
+ * and invalidate
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ *
+ * @return void
+ */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
+#define os_cache_flush_range(start,len)                                   \
+    dma_map_single(NULL, (void*)start, len, DMA_BIDIRECTIONAL)
+#else
+#define os_cache_flush_range(start,len)                                   \
+{                                                                         \
+    void *s = (void*)start;                                               \
+    void *e = s + len;                                                    \
+    dmac_flush_range(s, e);                                               \
+    outer_flush_range(__pa(s), __pa(e));                                  \
+}
+#endif
+
+	  /*! @} *//* cacheops */
+
+#endif				/* LINUX_PORT_H */
diff --git a/drivers/mxc/security/sahara2/include/platform_abstractions.h b/drivers/mxc/security/sahara2/include/platform_abstractions.h
new file mode 100644
index 000000000000..c2f9c489eb0b
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/platform_abstractions.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @file platform_abstractions.h
+ */
diff --git a/drivers/mxc/security/sahara2/include/portable_os.h b/drivers/mxc/security/sahara2/include/portable_os.h
new file mode 100644
index 000000000000..e904b3222cbb
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/portable_os.h
@@ -0,0 +1,1453 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef PORTABLE_OS_H
+#define PORTABLE_OS_H
+
+/***************************************************************************/
+
+/*
+ * Add support for your target OS by checking appropriate flags and then
+ * including the appropriate file.  Don't forget to document the conditions
+ * in the later documentation section at the beginning of the
+ * DOXYGEN_PORTABLE_OS_DOC.
+ */
+
+#if defined(LINUX_KERNEL)
+
+#include "linux_port.h"
+
+#elif defined(PORTABLE_OS)
+
+#include "check_portability.h"
+
+#else
+
+#error Target OS unsupported or unspecified
+
+#endif
+
+
+/***************************************************************************/
+
+/*!
+ * @file portable_os.h
+ *
+ * This file should be included by portable driver code in order to gain access
+ * to the OS-specific header files.  It is the only OS-related header file that
+ * the writer of a portable driver should need.
+ *
+ * This file also contains the documentation for the common API.
+ *
+ * Begin reading the documentation for this file at the @ref index "main page".
+ *
+ */
+
+/*!
+ * @if USE_MAINPAGE
+ * @mainpage Generic OS API for STC Drivers
+ * @endif
+ *
+ * @section intro_sec Introduction
+ *
+ * This defines the API / kernel programming environment for portable drivers.
+ *
+ * This API is broken up into several functional areas.  It greatly limits the
+ * choices of a device-driver author, but at the same time should allow for
+ * greater portability of the resulting code.
+ *
+ * Each kernel-to-driver function (initialization function, interrupt service
+ * routine, etc.) has a 'portable signature' which must be used, and a specific
+ * function which must be called to generate the return statement.  There is
+ * one exception, a background task or "bottom half" routine, which instead has
+ * a specific structure which must be followed.  These signatures and function
+ * definitions are found in @ref drsigs.
+ *
+ * None of these kernel-to-driver functions seem to get any arguments passed to
+ * them.  Instead, there are @ref drsigargs which allow one of these functions
+ * to get at fairly generic parts of its calling arguments, if there are any.
+ *
+ * Almost every driver will have some need to call the operating system
+ * @ref dkops is the list of services which are available to the driver.
+ *
+ *
+ * @subsection warn_sec Warning
+ *
+ * The specifics of the types, values of the various enumerations
+ * (unless specifically stated, like = 0), etc., are only here for illustrative
+ * purposes.  No attempts should be made to make use of any specific knowledge
+ * gleaned from this documentation.  These types are only meant to be passed in
+ * and out of the API, and their contents are to be handled only by the
+ * provided OS-specific functions.
+ *
+ * Also, note that the function may be provided as macros in some
+ * implementations, or vice versa.
+ *
+ *
+ * @section dev_sec Writing a Portable Driver
+ *
+ * First off, writing a portable driver means calling no function in an OS
+ * except what is available through this header file.
+ *
+ * Secondly, all OS-called functions in your driver must be invoked and
+ * referenced through the signature routines.
+ *
+ * Thirdly, there might be some rules which you can get away with ignoring or
+ * violating on one OS, yet will cause your code not to be portable to a
+ * different OS.
+ *
+ *
+ * @section limit_sec Limitations
+ *
+ * This API is not expected to handle every type of driver which may be found
+ * in an operating system.  For example, it will not be able to handle the
+ * usual design for something like a UART driver, where there are multiple
+ * logical devices to access, because the design usually calls for some sort of
+ * indication to the #OS_DEV_TASK() function or OS_DEV_ISR() to indicate which
+ * channel is to be serviced by that instance of the task/function.  This sort
+ * of argument is missing in this API for functions like os_dev_schedule_task() and
+ * os_register_interrupt().
+ *
+ *
+ * @section port_guide Porting Guidelines
+ *
+ * This section is intended for a developer who needs to port the header file
+ * to an operating system which is not yet supported.
+ *
+ * This interface allows for a lot of flexibility when it comes to porting to
+ * an operating systems device driver interface.  There are three main areas to
+ * examine:  The use of Driver Routine Signatures, the use of Driver Argument
+ * Access functions, the Calls to Kernel Functions, and Data Types.
+ *
+ *
+ * @subsection port_sig Porting Driver Routine Signatures
+ *
+ * The three macros for each function (e.g. #OS_DEV_INIT(), #OS_DEV_INIT_DCL(),
+ * and #OS_DEV_INIT_REF()) allow the flexibility of having a 'wrapper' function
+ * with the OS-required signature, which would then call the user's function
+ * with some different signature.
+ *
+ * The first form would lay down the wrapper function, followed by the
+ * signature for the user function.  The second form would lay down just the
+ * signatures for both functions, and the last function would reference the
+ * wrapper function, since that is the interface function called by the OS.
+ *
+ * Note that the driver author has no visibility at all to the signature of the
+ * routines.  The author can access arguments only through a limited set of
+ * functions, and must return via another function.
+ *
+ * The Return Functions allow a lot of flexibility in converting the return
+ * value, or not returning a value at all.  These will likely be implemented as
+ * macros.
+ *
+ *
+ * @subsection port_arg Porting Driver Argument Access Functions
+ *
+ * The signatures defined by the guide will usually be replaced with macro
+ * definitions.
+ *
+ *
+ * @subsection port_dki Porting Calls to Kernel Functions
+ *
+ * The signatures defined by the guide may be replaced with macro definitions,
+ * if that makes more sense.
+ *
+ * Implementors are free to ignore arguments which are not applicable to their
+ * OS.
+ *
+ * @subsection port_datatypes Porting Data Types
+ *
+ *
+ */
+
+/***************************************************************************
+ * Compile flags
+ **************************************************************************/
+
+/*
+ * This compile flag should only be turned on when running doxygen to generate
+ * the API documentation.
+ */
+#ifdef DOXYGEN_PORTABLE_OS_DOC
+
+/*!
+ * @todo module_init()/module_cleanup() for Linux need to be added to OS
+ * abstractions.  Also need EXPORT_SYMBOL() equivalent??
+ *
+ */
+
+/* Drop OS differentation documentation here */
+
+/*!
+ * \#define this flag to build your driver as a Linux driver
+ */
+#define LINUX
+
+/* end OS differentation documentation */
+
+/*!
+ * Symbol to give version number of the implementation file.  Earliest
+ * definition is in version 1.1, with value 101 (to mean version 1.1)
+ */
+#define PORTABLE_OS_VERSION 101
+
+/*
+ * NOTICE: The following definitions (the rest of the file) are not meant ever
+ * to be compiled.  Instead, they are the documentation for the portable OS
+ * API, to be used by driver writers.
+ *
+ * Each individual OS port will define each of these types, functions, or
+ * macros as appropriate to the target OS. This is why they are under the
+ * DOXYGEN_PORTABLE_OS_DOC flag.
+ */
+
+/***************************************************************************
+ * Type definitions
+ **************************************************************************/
+
+/*!
+ * Type used for registering and deregistering interrupts.
+ *
+ * This is typically an interrupt channel number.
+ */
+typedef int os_interrupt_id_t;
+
+/*!
+ * Type used as handle for a process
+ *
+ * See #os_get_process_handle() and #os_send_signal().
+ */
+typedef int os_process_handle_t;
+
+/*!
+ * Generic return code for functions which need such a thing.
+ *
+ * No knowledge should be assumed of the value of any of these symbols except
+ * that @c OS_ERROR_OK_S is guaranteed to be zero.
+ *
+ * @todo Any other named values? What about (-EAGAIN?  -ERESTARTSYS? Are they
+ * too Linux/Unix-specific read()/write() return values) ?
+ */
+typedef enum {
+	OS_ERROR_OK_S = 0,	/*!< Success  */
+	OS_ERROR_FAIL_S,	/*!< Generic driver failure */
+	OS_ERROR_NO_MEMORY_S,	/*!< Failure to acquire/use memory  */
+	OS_ERROR_BAD_ADDRESS_S,	/*!< Bad address  */
+	OS_ERROR_BAD_ARG_S	/*!< Bad input argument */
+} os_error_code;
+
+/*!
+ * Handle to a lock.
+ */
+typedef int *os_lock_t;
+
+/*!
+ * Context while locking.
+ */
+typedef int os_lock_context_t;
+
+/*!
+ * An object which can be slept on and later used to wake any/all sleepers.
+ */
+typedef int os_sleep_object_t;
+
+/*!
+ * Driver registration handle
+ */
+typedef void *os_driver_reg_t;
+
+/*!
+ * Function signature for an #OS_DEV_INIT() function.
+ *
+ * @return  A call to os_dev_init_return() function.
+ */
+typedef void (*os_init_function_t) (void);
+
+/*!
+ * Function signature for an #OS_DEV_SHUTDOWN() function.
+ *
+ * @return  A call to os_dev_shutdown_return() function.
+ */
+typedef void (*os_shutdown_function_t) (void);
+
+/*!
+ * Function signature for a user-driver function.
+ *
+ * @return  A call to the appropriate os_dev_xxx_return() function.
+ */
+typedef void (*os_user_function_t) (void);
+
+/*!
+ * Function signature for the portable interrupt handler
+ *
+ * While it would be nice to know which interrupt is being serviced, the
+ * Least Common Denominator rule says that no arguments get passed in.
+ *
+ * @return  A call to #os_dev_isr_return()
+ */
+typedef void (*os_interrupt_handler_t) (void);
+
+/*!
+ * Function signature for a task function
+ *
+ * Many task function definitions get some sort of generic argument so that the
+ * same function can run across many (queues, channels, ...) as separate task
+ * instances.  This has been left out of this API.
+ *
+ * This function must be structured as documented by #OS_DEV_TASK().
+ *
+ */
+typedef void (*os_task_fn_t) (void);
+
+/*!
+ *  Function types which can be associated with driver entry points.  These are
+ *  used in os_driver_add_registration().
+ *
+ *  Note that init and shutdown are absent.
+ */
+typedef enum {
+	OS_FN_OPEN,		/*!< open() operation handler. */
+	OS_FN_CLOSE,		/*!< close() operation handler. */
+	OS_FN_READ,		/*!< read() operation handler. */
+	OS_FN_WRITE,		/*!< write() operation handler. */
+	OS_FN_IOCTL,		/*!< ioctl() operation handler. */
+	OS_FN_MMAP		/*!< mmap() operation handler. */
+} os_driver_fn_t;
+
+/***************************************************************************
+ * Driver-to-Kernel Operations
+ **************************************************************************/
+
+/*!
+ * @defgroup dkops Driver-to-Kernel Operations
+ *
+ * These are the operations which drivers should call to get the OS to perform
+ * services.
+ */
+
+/*! @addtogroup dkops */
+/*! @{ */
+
+/*!
+ * Register an interrupt handler.
+ *
+ * @param driver_name    The name of the driver
+ * @param interrupt_id   The interrupt line to monitor (type
+ *                       #os_interrupt_id_t)
+ * @param function       The function to be called to handle an interrupt
+ *
+ * @return #os_error_code
+ */
+os_error_code os_register_interrupt(char *driver_name,
+				    os_interrupt_id_t interrupt_id,
+				    os_interrupt_handler_t function);
+
+/*!
+ * Deregister an interrupt handler.
+ *
+ * @param interrupt_id   The interrupt line to stop monitoring
+ *
+ * @return #os_error_code
+ */
+os_error_code os_deregister_interrupt(os_interrupt_id_t interrupt_id);
+
+/*!
+ * Initialize driver registration.
+ *
+ * If the driver handles open(), close(), ioctl(), read(), write(), or mmap()
+ * calls, then it needs to register their location with the kernel so that they
+ * get associated with the device.
+ *
+ * @param handle  The handle object to be used with this registration.  The
+ *                object must live (be in memory somewhere) at least until
+ *                os_driver_remove_registration() is called.
+ *
+ * @return An os error code.
+ */
+os_error_code os_driver_init_registration(os_driver_reg_t handle);
+
+/*!
+ * Add a function registration to driver registration.
+ *
+ * @param handle    The handle used with #os_driver_init_registration().
+ * @param name      Which function is being supported.
+ * @param function  The result of a call to a @c _REF version of one of the
+ *                  driver function signature macros
+ *                  driver function signature macros
+ * @return void
+ */
+void os_driver_add_registration(os_driver_reg_t handle, os_driver_fn_t name,
+				void *function);
+
+/*!
+ * Finalize the driver registration with the kernel.
+ *
+ * Upon return from this call, the driver may begin receiving calls at the
+ * defined entry points.
+ *
+ * @param handle    The handle used with #os_driver_init_registration().
+ * @param major      The major device number to be associated with the driver.
+ *                   If this value is zero, a major number may be assigned.
+ *                   See #os_driver_get_major() to determine final value.
+ *                   #os_driver_remove_registration().
+ * @param driver_name The driver name.  Can be used as part of 'device node'
+ *                   name on platforms which support such a feature.
+ *
+ * @return  An error code
+ */
+os_error_code os_driver_complete_registration(os_driver_reg_t handle,
+					      int major, char *driver_name);
+
+/*!
+ * Get driver Major Number from handle after a successful registration.
+ *
+ * @param   handle  A handle which has completed registration.
+ *
+ * @return The major number (if any) associated with the handle.
+ */
+uint32_t os_driver_get_major(os_driver_reg_t handle);
+
+/*!
+ * Remove the driver's registration with the kernel.
+ *
+ * Upon return from this call, the driver not receive any more calls at the
+ * defined entry points (other than ISR and shutdown).
+ *
+ * @param major       The major device number to be associated with the driver.
+ * @param driver_name The driver name
+ *
+ * @return  An error code.
+ */
+os_error_code os_driver_remove_registration(int major, char *driver_name);
+
+/*!
+ * Print a message to console / into log file.  After the @c msg argument a
+ * number of printf-style arguments may be added.  Types should be limited to
+ * printf string, char, octal, decimal, and hexadecimal types.  (This excludes
+ * pointers, and floating point).
+ *
+ * @param  msg  The message to print to console / system log
+ *
+ * @return (void)
+ */
+void os_printk(char *msg, ...);
+
+/*!
+ * Allocate some kernel memory
+ *
+ * @param amount   Number of 8-bit bytes to allocate
+ * @param flags    Some indication of purpose of memory (needs definition)
+ *
+ * @return  Pointer to allocated memory, or NULL if failed.
+ */
+void *os_alloc_memory(unsigned amount, int flags);
+
+/*!
+ * Free some kernel memory
+ *
+ * @param location  The beginning of the region to be freed.
+ *
+ * Do some OSes have separate free() functions which should be
+ * distinguished by passing in @c flags here, too? Don't some also require the
+ * size of the buffer being freed?  Perhaps separate routines for each
+ * alloc/free pair (DMAable, etc.)?
+ */
+void os_free_memory(void *location);
+
+/*!
+ * Allocate cache-coherent memory
+ *
+ * @param       amount     Number of bytes to allocate
+ * @param[out]  dma_addrp  Location to store physical address of allocated
+ *                         memory.
+ * @param       flags      Some indication of purpose of memory (needs
+ *                         definition).
+ *
+ * @return (virtual space) pointer to allocated memory, or NULL if failed.
+ *
+ */
+void *os_alloc_coherent(unsigned amount, uint32_t * dma_addrp, int flags);
+
+/*!
+ * Free cache-coherent memory
+ *
+ * @param       size       Number of bytes which were allocated.
+ * @param[out]  virt_addr  Virtual(kernel) address of memory.to be freed, as
+ *                         returned by #os_alloc_coherent().
+ * @param[out]  dma_addr   Physical address of memory.to be freed, as returned
+ *                         by #os_alloc_coherent().
+ *
+ * @return void
+ *
+ */
+void os_free_coherent(unsigned size, void *virt_addr, uint32_t dma_addr);
+
+/*!
+ * Map an I/O space into kernel memory space
+ *
+ * @param start       The starting address of the (physical / io space) region
+ * @param range_bytes The number of bytes to map
+ *
+ * @return A pointer to the mapped area, or NULL on failure
+ */
+void *os_map_device(uint32_t start, unsigned range_bytes);
+
+/*!
+ * Unmap an I/O space from kernel memory space
+ *
+ * @param start       The starting address of the (virtual) region
+ * @param range_bytes The number of bytes to unmap
+ *
+ * @return None
+ */
+void os_unmap_device(void *start, unsigned range_bytes);
+
+/*!
+ * Copy data from Kernel space to User space
+ *
+ * @param to   The target location in user memory
+ * @param from The source location in kernel memory
+ * @param size The number of bytes to be copied
+ *
+ * @return #os_error_code
+ */
+os_error_code os_copy_to_user(void *to, void *from, unsigned size);
+
+/*!
+ * Copy data from User space to Kernel space
+ *
+ * @param to   The target location in kernel memory
+ * @param from The source location in user memory
+ * @param size The number of bytes to be copied
+ *
+ * @return #os_error_code
+ */
+os_error_code os_copy_from_user(void *to, void *from, unsigned size);
+
+/*!
+ * Read an 8-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+uint8_t os_read8(uint8_t * register_address);
+
+/*!
+ * Write an 8-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+void os_write8(uint8_t * register_address, uint8_t value);
+
+/*!
+ * Read a 16-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+uint16_t os_read16(uint16_t * register_address);
+
+/*!
+ * Write a 16-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+void os_write16(uint16_t * register_address, uint16_t value);
+
+/*!
+ * Read a 32-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+uint32_t os_read32(uint32_t * register_address);
+
+/*!
+ * Write a 32-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+void os_write32(uint32_t * register_address, uint32_t value);
+
+/*!
+ * Read a 64-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @return                  The value in the register
+ */
+uint64_t os_read64(uint64_t * register_address);
+
+/*!
+ * Write a 64-bit device register
+ *
+ * @param register_address  The (bus) address of the register to write to
+ * @param value             The value to write into the register
+ */
+void os_write64(uint64_t * register_address, uint64_t value);
+
+/*!
+ * Prepare a task to execute the given function.  This should only be done once
+ * per task, during the driver's initialization routine.
+ *
+ * @param task_fn   Name of the OS_DEV_TASK() function to be created.
+ *
+ * @return an OS ERROR code.
+ */
+os_error os_create_task(os_task_fn_t * task_fn);
+
+/*!
+ * Run the task associated with an #OS_DEV_TASK() function
+ *
+ * The task will begin execution sometime after or during this call.
+ *
+ * @param task_fn   Name of the OS_DEV_TASK() function to be scheduled.
+ *
+ * @return void
+ */
+void os_dev_schedule_task(os_task_fn_t * task_fn);
+
+/*!
+ * Make sure that task is no longer running and will no longer run.
+ *
+ * This function will not return until both are true.  This is useful when
+ * shutting down a driver.
+ *
+ * @param task_fn   Name of the OS_DEV_TASK() funciton to be stopped.
+ *
+ */
+void os_stop_task(os_task_fn_t * task_fn);
+
+/*!
+ * Delay some number of microseconds
+ *
+ * Note that this is a busy-loop, not a suspension of the task/process.
+ *
+ * @param  msecs   The number of microseconds to delay
+ *
+ * @return void
+ */
+void os_mdelay(unsigned long msecs);
+
+/*!
+ * Calculate virtual address from physical address
+ *
+ * @param pa    Physical address
+ *
+ * @return virtual address
+ *
+ * @note this assumes that addresses are 32 bits wide
+ */
+void *os_va(uint32_t pa);
+
+/*!
+ * Calculate physical address from virtual address
+ *
+ *
+ * @param va    Virtual address
+ *
+ * @return physical address
+ *
+ * @note this assumes that addresses are 32 bits wide
+ */
+uint32_t os_pa(void *va);
+
+/*!
+ * Allocate and initialize a lock, returning a lock handle.
+ *
+ * The lock state will be initialized to 'unlocked'.
+ *
+ * @return A lock handle, or NULL if an error occurred.
+ */
+os_lock_t os_lock_alloc_init(void);
+
+/*!
+ * Acquire a lock.
+ *
+ * This function should only be called from an interrupt service routine.
+ *
+ * @param   lock_handle  A handle to the lock to acquire.
+ *
+ * @return void
+ */
+void os_lock(os_lock_t lock_handle);
+
+/*!
+ * Unlock a lock.  Lock must have been acquired by #os_lock().
+ *
+ * @param   lock_handle  A handle to the lock to unlock.
+ *
+ * @return void
+ */
+void os_unlock(os_lock_t lock_handle);
+
+/*!
+ * Acquire a lock in non-ISR context
+ *
+ * This function will spin until the lock is available.
+ *
+ * @param lock_handle  A handle of the lock to acquire.
+ * @param context      Place to save the before-lock context
+ *
+ * @return void
+ */
+void os_lock_save_context(os_lock_t lock_handle, os_lock_context_t context);
+
+/*!
+ * Release a lock in non-ISR context
+ *
+ * @param lock_handle  A handle of the lock to release.
+ * @param context      Place where before-lock context was saved.
+ *
+ * @return void
+ */
+void os_unlock_restore_context(os_lock_t lock_handle,
+			       os_lock_context_t context);
+
+/*!
+ * Deallocate a lock handle.
+ *
+ * @param lock_handle   An #os_lock_t that has been allocated.
+ *
+ * @return void
+ */
+void os_lock_deallocate(os_lock_t lock_handle);
+
+/*!
+ * Determine process handle
+ *
+ * The process handle of the current user is returned.
+ *
+ * @return   A handle on the current process.
+ */
+os_process_handle_t os_get_process_handle();
+
+/*!
+ * Send a signal to a process
+ *
+ * @param  proc   A handle to the target process.
+ * @param  sig    The POSIX signal to send to that process.
+ */
+void os_send_signal(os_process_handle_t proc, int sig);
+
+/*!
+ * Get some random bytes
+ *
+ * @param buf    The location to store the random data.
+ * @param count  The number of bytes to store.
+ *
+ * @return  void
+ */
+void os_get_random_bytes(void *buf, unsigned count);
+
+/*!
+ * Go to sleep on an object.
+ *
+ * Example: code = os_sleep(my_queue, available_count == 0, 0);
+ *
+ * @param object    The object on which to sleep
+ * @param condition An expression to check for sleep completion.  Must be
+ *                  coded so that it can be referenced more than once inside
+ *                  macro, i.e., no ++ or other modifying expressions.
+ * @param atomic    Non-zero if sleep must not return until condition.
+ *
+ * @return error code -- OK or sleep interrupted??
+ */
+os_error_code os_sleep(os_sleep_object_t object, unsigned condition,
+		       unsigned atomic);
+
+/*!
+ * Wake up whatever is sleeping on sleep object
+ *
+ * @param object  The object on which things might be sleeping
+ *
+ * @return none
+ */
+void os_wake_sleepers(os_sleep_object_t object);
+
+	  /*! @} *//* dkops */
+
+/*****************************************************************************
+ *  Function-signature-generating macros
+ *****************************************************************************/
+
+/*!
+ * @defgroup drsigs Driver Function Signatures
+ *
+ * These macros will define the entry point signatures for interrupt handlers;
+ * driver initialization and shutdown; device open/close; etc.  They are to be
+ * used whenever the Kernel will call into the Driver.  They are not
+ * appropriate for driver calls to other routines in the driver.
+ *
+ * There are three versions of each macro for a given Driver Entry Point.  The
+ * first version is used to define a function and its implementation in the
+ * driver.c file, e.g. #OS_DEV_INIT().
+ *
+ * The second form is used whenever a forward declaration (prototype) is
+ * needed.  It has the letters @c _DCL appended to the name of the definition
+ * function.  These are not otherwise mentioned in this documenation.
+ *
+ * There is a third form used when a reference to a function is required, for
+ * instance when passing the routine as a pointer to a function.  It has the
+ * letters @c _REF appended to the name of the definition function
+ * (e.g. DEV_IOCTL_REF).
+ *
+ * Note that these two extra forms are required because of the possibility of
+ * having an invisible 'wrapper function' created by the os-specific header
+ * file which would need to be invoked by the operating system, and which in
+ * turn would invoke the generic function.
+ *
+ * Example:
+ *
+ * (in a header file)
+ * @code
+ * OS_DEV_INIT_DCL(widget_init);
+ * OS_DEV_ISR_DCL(widget_isr);
+ * @endcode
+ *
+ * (in an implementation file)
+ * @code
+ * OS_DEV_INIT(widget, widget_init)
+ * {
+ *
+ *     os_register_interrupt("widget", WIDGET_IRQ, OS_DEV_ISR_REF(widget_isr));
+ *
+ *     os_dev_init_return(OS_RETURN_NO_ERROR_S);
+ * }
+ *
+ * OS_DEV_ISR(widget_isr)
+ * {
+ *     os_dev_isr_return(TRUE);
+ * }
+ * @endcode
+ */
+
+/*! @addtogroup drsigs */
+/*! @{ */
+
+/*!
+ * Define a function which will handle device initialization
+ *
+ * This is tne driver initialization routine.  This is normally where the
+ * part would be initialized; queues, locks, interrupts handlers defined;
+ * long-term dynamic memory allocated for driver use; etc.
+ *
+ * @param function_name   The name of the portable initialization function.
+ *
+ * @return  A call to #os_dev_init_return()
+ *
+ */
+#define OS_DEV_INIT(function_name)
+
+/*!
+ * Define a function which will handle device shutdown
+ *
+ * This is the reverse of the #OS_DEV_INIT() routine.
+ *
+ * @param function_name   The name of the portable driver shutdown routine.
+ *
+ * @return  A call to #os_dev_shutdown_return()
+ */
+#define OS_DEV_SHUTDOWN(function_name)
+
+/*!
+ * Define a function which will open the device for a user.
+ *
+ * @param function_name The name of the driver open() function
+ *
+ * @return A call to #os_dev_open_return()
+ */
+#define OS_DEV_OPEN(function_name)
+
+/*!
+ * Define a function which will handle a user's ioctl() request
+ *
+ * @param function_name The name of the driver ioctl() function
+ *
+ * @return A call to #os_dev_ioctl_return()
+ */
+#define OS_DEV_IOCTL(function_name)
+
+/*!
+ * Define a function which will handle a user's read() request
+ *
+ * @param function_name The name of the driver read() function
+ *
+ * @return A call to #os_dev_read_return()
+ */
+#define OS_DEV_READ(function_name)
+
+/*!
+ * Define a function which will handle a user's write() request
+ *
+ * @param function_name The name of the driver write() function
+ *
+ * @return A call to #os_dev_write_return()
+ */
+#define OS_DEV_WRITE(function_name)
+
+/*!
+ * Define a function which will handle a user's mmap() request
+ *
+ * The mmap() function requests the driver to map some memory into user space.
+ *
+ * @todo Determine what support functions are needed for mmap() handling.
+ *
+ * @param function_name The name of the driver mmap() function
+ *
+ * @return A call to #os_dev_mmap_return()
+ */
+#define OS_DEV_MMAP(function_name)
+
+/*!
+ * Define a function which will close the device - opposite of OS_DEV_OPEN()
+ *
+ * @param function_name The name of the driver close() function
+ *
+ * @return A call to #os_dev_close_return()
+ */
+#define OS_DEV_CLOSE(function_name)
+
+/*!
+ * Define a function which will handle an interrupt
+ *
+ * No arguments are available to the generic function.  It must not invoke any
+ * OS functions which are illegal in a ISR.  It gets no parameters, and must
+ * have a call to #os_dev_isr_return() instead of any/all return statements.
+ *
+ * Example:
+ * @code
+ * OS_DEV_ISR(widget, widget_isr, WIDGET_IRQ_NUMBER)
+ * {
+ *     os_dev_isr_return(1);
+ * }
+ * @endcode
+ *
+ * @param function_name The name of the driver ISR function
+ *
+ * @return   A call to #os_dev_isr_return()
+ */
+#define OS_DEV_ISR(function_name)
+
+/*!
+ * Define a function which will operate as a background task / bottom half.
+ *
+ * The function implementation must be structured in the following manner:
+ * @code
+ * OS_DEV_TASK(widget_task)
+ * {
+ *     OS_DEV_TASK_SETUP(widget_task);
+ *
+ *     while OS_DEV_TASK_CONDITION(widget_task) }
+ *
+ *     };
+ * }
+ * @endcode
+ *
+ * @todo In some systems the OS_DEV_TASK_CONDITION() will be an action which
+ * will cause the task to sleep on some event triggered by os_run_task().  In
+ * others, the macro will reference a variable laid down by
+ * OS_DEV_TASK_SETUP() to make sure that the loop is only performed once.
+ *
+ * @param function_name The name of this background task function
+ */
+#define OS_DEV_TASK(function_name)
+
+	  /*! @} *//* drsigs */
+
+/*! @defgroup dclsigs Routines to declare Driver Signature routines
+ *
+ * These macros drop prototypes suitable for forward-declaration of
+ * @ref drsigs "function signatures".
+ */
+
+/*! @addtogroup dclsigs */
+/*! @{ */
+
+/*!
+ * Declare prototype for the device initialization function
+ *
+ * @param function_name   The name of the portable initialization function.
+ */
+#define OS_DEV_INIT_DCL(function_name)
+
+/*!
+ * Declare prototype for the device shutdown function
+ *
+ * @param function_name   The name of the portable driver shutdown routine.
+ *
+ * @return  A call to #os_dev_shutdown_return()
+ */
+#define OS_DEV_SHUTDOWN_DCL(function_name)
+
+/*!
+ * Declare prototype for the open() function.
+ *
+ * @param function_name The name of the driver open() function
+ *
+ * @return A call to #os_dev_open_return()
+ */
+#define OS_DEV_OPEN_DCL(function_name)
+
+/*!
+ * Declare prototype for the user's ioctl() request function
+ *
+ * @param function_name The name of the driver ioctl() function
+ *
+ * @return A call to #os_dev_ioctl_return()
+ */
+#define OS_DEV_IOCTL_DCL(function_name)
+
+/*!
+ * Declare prototype for the function a user's read() request
+ *
+ * @param function_name The name of the driver read() function
+ */
+#define OS_DEV_READ_DCL(function_name)
+
+/*!
+ * Declare prototype for the user's write() request function
+ *
+ * @param function_name The name of the driver write() function
+ */
+#define OS_DEV_WRITE_DCL(function_name)
+
+/*!
+ * Declare prototype for the user's mmap() request function
+ *
+ * @param function_name The name of the driver mmap() function
+ */
+#define OS_DEV_MMAP_DCL(function_name)
+
+/*!
+ * Declare prototype for the close function
+ *
+ * @param function_name The name of the driver close() function
+ *
+ * @return A call to #os_dev_close_return()
+ */
+#define OS_DEV_CLOSE_DCL(function_name)
+
+/*!
+ * Declare prototype for the interrupt handling function
+ *
+ * @param function_name The name of the driver ISR function
+ */
+#define OS_DEV_ISR_DCL(function_name)
+
+/*!
+ * Declare prototype for a background task / bottom half function
+ *
+ * @param function_name The name of this background task function
+ */
+#define OS_DEV_TASK_DCL(function_name)
+
+	  /*! @} *//* dclsigs */
+
+/*****************************************************************************
+ *  Functions for Returning Values from Driver Signature routines
+ *****************************************************************************/
+
+/*!
+ * @defgroup retfns Functions to Return Values from Driver Signature routines
+ */
+
+/*! @addtogroup retfns */
+/*! @{ */
+
+/*!
+ * Return from the #OS_DEV_INIT() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_init_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_SHUTDOWN() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_shutdown_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_ISR() function
+ *
+ * The function should verify that it really was supposed to be called,
+ * and that its device needed attention, in order to properly set the
+ * return code.
+ *
+ * @param code    non-zero if interrupt handled, zero otherwise.
+ *
+ */
+void os_dev_isr_return(int code);
+
+/*!
+ * Return from the #OS_DEV_OPEN() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_open_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_IOCTL() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_ioctl_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_READ() function
+ *
+ * @param code    Number of bytes read, or an error code to report failure.
+ *
+ */
+void os_dev_read_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_WRITE() function
+ *
+ * @param code    Number of bytes written, or an error code to report failure.
+ *
+ */
+void os_dev_write_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_MMAP() function
+ *
+ * @param code    Number of bytes written, or an error code to report failure.
+ *
+ */
+void os_dev_mmap_return(os_error_code code);
+
+/*!
+ * Return from the #OS_DEV_CLOSE() function
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_close_return(os_error_code code);
+
+/*!
+ * Start the #OS_DEV_TASK() function
+ *
+ * In some implementations, this could be turned into a label for
+ * the os_dev_task_return() call.
+ *
+ * For a more portable interface, should this take the sleep object as an
+ * argument???
+ *
+ * @return none
+ */
+void os_dev_task_begin(void);
+
+/*!
+ * Return from the #OS_DEV_TASK() function
+ *
+ * In some implementations, this could be turned into a sleep followed
+ * by a jump back to the os_dev_task_begin() call.
+ *
+ * @param code    An error code to report success or failure.
+ *
+ */
+void os_dev_task_return(os_error_code code);
+
+	  /*! @} *//* retfns */
+
+/*****************************************************************************
+ *  Functions/Macros for accessing arguments from Driver Signature routines
+ *****************************************************************************/
+
+/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions
+ *
+ */
+/* @addtogroup @drsigargs */
+/*! @{ */
+
+/*!
+ * Check whether user is requesting read (permission) on the file/device.
+ * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ()
+ * and #OS_DEV_WRITE() routines.
+ */
+int os_dev_is_flag_read(void);
+
+/*!
+ * Check whether user is requesting write (permission) on the file/device.
+ * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ()
+ * and #OS_DEV_WRITE() routines.
+ */
+int os_dev_is_flag_write(void);
+
+/*!
+ * Check whether user is requesting non-blocking I/O.  Usable in
+ * #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and
+ * #OS_DEV_WRITE() routines.
+ *
+ * @todo Specify required behavior when nonblock is requested and (sufficient?)
+ * data are not available to fulfill the request.
+ *
+ */
+int os_dev_is_flag_nonblock(void);
+
+/*!
+ * Determine which major device is being accessed.  Usable in #OS_DEV_OPEN()
+ * and #OS_DEV_CLOSE().
+ */
+int os_dev_get_major(void);
+
+/*!
+ * Determine which minor device is being accessed.  Usable in #OS_DEV_OPEN()
+ * and #OS_DEV_CLOSE().
+ */
+int os_dev_get_minor(void);
+
+/*!
+ * Determine which operation the user wants performed.  Usable in
+ * #OS_DEV_IOCTL().
+ *
+ * @return  Value of the operation.
+ *
+ * @todo Define some generic way to define the individual operations.
+ */
+unsigned os_dev_get_ioctl_op(void);
+
+/*!
+ * Retrieve the associated argument for the desired operation.  Usable in
+ * #OS_DEV_IOCTL().
+ *
+ * @return    A value which can be cast to a struct pointer or used as
+ *            int/long.
+ */
+os_dev_ioctl_arg_t os_dev_get_ioctl_arg(void);
+
+/*!
+ * Determine the requested byte count. This should be the size of buffer at
+ * #os_dev_get_user_buffer(). Usable in OS_DEV_READ() and OS_DEV_WRITE()
+ * routines.
+ *
+ * @return   A count of bytes
+ */
+unsigned os_dev_get_count(void);
+
+/*!
+ * Get the pointer to the user's data buffer. Usable in OS_DEV_READ(),
+ * OS_DEV_WRITE(), and OS_DEV_MMAP() routines.
+ *
+ * @return   Pointer to user buffer (in user space).  See #os_copy_to_user()
+ *           and #os_copy_from_user().
+ */
+void *os_dev_get_user_buffer(void);
+
+/*!
+ * Get the POSIX flags field for the associated open file.  Usable in
+ * OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines.
+ *
+ * @return The flags associated with the file.
+ */
+unsigned os_dev_get_file_flags(void);
+
+/*!
+ * Set the driver's private structure associated with this file/open.
+ *
+ * Generally used during #OS_DEV_OPEN().  May also be used during
+ * #OS_DEV_READ(), #OS_DEV_WRITE(), #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and
+ * #OS_DEV_CLOSE().  See also #os_dev_get_user_private().
+ *
+ * @param  struct_p   The driver data structure to associate with this user.
+ */
+void os_dev_set_user_private(void *struct_p);
+
+/*!
+ * Get the driver's private structure associated with this file.
+ *
+ * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(),
+ * #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and #OS_DEV_CLOSE().  See
+ * also #os_dev_set_user_private().
+ *
+ * @return   The driver data structure to associate with this user.
+ */
+void *os_dev_get_user_private(void);
+
+/*!
+ * Get the IRQ associated with this call to the #OS_DEV_ISR() function.
+ *
+ * @return  The IRQ (integer) interrupt number.
+ */
+int os_dev_get_irq(void);
+
+	  /*! @} *//* drsigargs */
+
+/*****************************************************************************
+ *  Functions for Generating References to Driver Routines
+ *****************************************************************************/
+
+/*!
+ * @defgroup drref Functions for Generating References to Driver Routines
+ *
+ * These functions will most likely be implemented as macros.  They are a
+ * necessary part of the portable API to guarantee portability.  The @c symbol
+ * type in here is the same symbol passed to the associated
+ * signature-generating macro.
+ *
+ * These macros must be used whenever referring to a
+ * @ref drsigs "driver signature function", for instance when storing or
+ * passing a pointer to the function.
+ */
+
+/*! @addtogroup drref */
+/*! @{ */
+
+/*!
+ * Generate a reference to an #OS_DEV_INIT() function
+ *
+ * @param function_name   The name of the init function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_init_function_t OS_DEV_INIT_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_SHUTDOWN() function
+ *
+ * @param function_name   The name of the shutdown function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_shutdown_function_t OS_DEV_SHUTDOWN_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_OPEN() function
+ *
+ * @param function_name   The name of the open function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_OPEN_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_CLOSE() function
+ *
+ * @param function_name   The name of the close function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_CLOSE_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_READ() function
+ *
+ * @param function_name   The name of the read function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_READ_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_WRITE() function
+ *
+ * @param function_name   The name of the write function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_WRITE_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_IOCTL() function
+ *
+ * @param function_name   The name of the ioctl function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_IOCTL_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_MMAP() function
+ *
+ * @param function_name   The name of the mmap function being referenced.
+ *
+ * @return A reference to the function
+ */
+os_user_function_t OS_DEV_MMAP_REF(symbol function_name);
+
+/*!
+ * Generate a reference to an #OS_DEV_ISR() function
+ *
+ * @param function_name   The name of the isr being referenced.
+ *
+ * @return a reference to the function
+ */
+os_interrupt_handler_t OS_DEV_ISR_REF(symbol function_name);
+
+	  /*! @} *//* drref */
+
+/*!
+ * Flush and invalidate all cache lines.
+ */
+void os_flush_cache_all(void);
+
+/*!
+ * Flush a range of addresses from the cache
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ */
+void os_cache_flush_range(void *start, uint32_t len);
+
+/*!
+ * Invalidate a range of addresses in the cache
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ */
+void os_cache_inv_range(void *start, uint32_t len);
+
+/*!
+ * Clean a range of addresses from the cache
+ *
+ * @param  start    Starting virtual address
+ * @param  len      Number of bytes to flush
+ */
+void os_cache_clean_range(void *start, uint32_t len);
+
+/*!
+  * @example widget.h
+  */
+
+/*!
+  * @example widget.c
+  */
+
+/*!
+  * @example rng_driver.h
+  */
+
+/*!
+  * @example rng_driver.c
+  */
+
+/*!
+  * @example shw_driver.h
+  */
+
+/*!
+  * @example shw_driver.c
+  */
+
+#endif				/* DOXYGEN_PORTABLE_OS_DOC */
+
+#endif				/* PORTABLE_OS_H */
diff --git a/drivers/mxc/security/sahara2/include/sah_driver_common.h b/drivers/mxc/security/sahara2/include/sah_driver_common.h
new file mode 100644
index 000000000000..7cfd32a30352
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_driver_common.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_driver_common.h
+*
+* @brief Provides types and defined values for use in the Driver Interface.
+*
+*/
+
+#ifndef SAH_DRIVER_COMMON_H
+#define SAH_DRIVER_COMMON_H
+
+#include "fsl_platform.h"
+#include <sahara.h>
+#include <adaptor.h>
+
+/** This specifies the permissions for the device file. It is equivalent to
+ * chmod 666.
+ */
+#define SAHARA_DEVICE_MODE S_IFCHR | S_IRUGO | S_IWUGO
+
+/**
+* The status of entries in the Queue.
+*
+******************************************************************************/
+typedef enum
+{
+    /** This state indicates that the entry is in the queue and awaits
+     *  execution on SAHARA. */
+    SAH_STATE_PENDING,
+    /** This state indicates that the entry has been written to the SAHARA
+     *  DAR. */
+    SAH_STATE_ON_SAHARA,
+    /** This state indicates that the entry is off of SAHARA, and is awaiting
+        post-processing. */
+    SAH_STATE_OFF_SAHARA,
+    /** This state indicates that the entry is successfully executed on SAHARA,
+        and it is finished with post-processing. */
+    SAH_STATE_COMPLETE,
+    /** This state indicates that the entry caused an error or fault on SAHARA,
+     *  and it is finished with post-processing. */
+    SAH_STATE_FAILED,
+    /** This state indicates that the entry was reset via the Reset IO
+     *  Control, and it is finished with post-processing. */
+    SAH_STATE_RESET,
+    /** This state indicates that the entry was signalled from user-space and
+     *  either in the DAR, IDAR or has finished executing pending Bottom Half
+     *  processing. */
+   SAH_STATE_IGNORE,
+    /** This state indicates that the entry was signalled from user-space and
+     *  has been processed by the bottom half. */
+   SAH_STATE_IGNORED
+} sah_Queue_Status;
+
+/* any of these conditions being true indicates the descriptor's processing
+ * is complete */
+#define SAH_DESC_PROCESSED(status)                             \
+                        (((status) == SAH_STATE_COMPLETE) ||   \
+                         ((status) == SAH_STATE_FAILED  ) ||   \
+                         ((status) == SAH_STATE_RESET   ))
+
+extern os_lock_t desc_queue_lock;
+
+extern uint32_t dar_count;
+extern uint32_t interrupt_count;
+extern uint32_t done1done2_count;
+extern uint32_t done1busy2_count;
+extern uint32_t done1_count;
+
+#ifdef FSL_HAVE_SCC2
+extern void *lookup_user_partition(fsl_shw_uco_t * user_ctx,
+				   uint32_t user_base);
+#endif
+
+int sah_get_results_pointers(fsl_shw_uco_t* user_ctx, uint32_t arg);
+fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t* user_ctx,
+                                           sah_results *arg);
+fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t *user_cts);
+fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t *user_cts);
+
+int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state);
+unsigned long sah_Handle_Poll(sah_Head_Desc *entry);
+
+#ifdef DIAG_DRV_IF
+/******************************************************************************
+* Descriptor and Link dumping functions.
+******************************************************************************/
+void sah_Dump_Chain(const sah_Desc *chain, dma_addr_t addr);
+#endif /* DIAG_DRV_IF */
+
+#endif  /* SAH_DRIVER_COMMON_H */
diff --git a/drivers/mxc/security/sahara2/include/sah_hardware_interface.h b/drivers/mxc/security/sahara2/include/sah_hardware_interface.h
new file mode 100644
index 000000000000..0933346fc223
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_hardware_interface.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_hardware_interface.h
+*
+* @brief Provides an interface to the SAHARA hardware registers.
+*
+*/
+
+#ifndef SAH_HARDWARE_INTERFACE_H
+#define SAH_HARDWARE_INTERFACE_H
+
+#include <sah_driver_common.h>
+#include <sah_status_manager.h>
+
+/* These values can be used with sah_HW_Write_Control(). */
+#ifdef SAHARA1
+/** Define platform as Little-Endian */
+#define CTRL_LITTLE_END     0x00000002
+/** Bit to cause endian change in transfers */
+#define CTRL_INT_EN         0x00000004
+/** Set High Assurance mode */
+#define CTRL_HA             0x00000008
+#else
+/** Bit to cause byte swapping in (data?) transfers */
+#define CTRL_BYTE_SWAP      0x00000001
+/** Bit to cause halfword swapping in (data?) transfers */
+#define CTRL_HALFWORD_SWAP  0x00000002
+/** Bit to cause endian change in (data?) transfers */
+#define CTRL_INT_EN         0x00000010
+/** Set High Assurance mode */
+#define CTRL_HA             0x00000020
+/** Disable High Assurance */
+#define CTRL_HA_DISABLE     0x00000040
+/** Reseed the RNG CHA */
+#define CTRL_RNG_RESEED     0x00000080
+#endif
+
+
+/* These values can be used with sah_HW_Write_Command(). */
+/** Reset the Sahara */
+#define CMD_RESET           0x00000001
+/** Set Sahara into Batch mode. */
+#define CMD_BATCH           0x00010000
+/** Clear the Sahara interrupt */
+#define CMD_CLR_INT_BIT     0x00000100
+/** Clear the Sahara error */
+#define CMD_CLR_ERROR_BIT   0x00000200
+
+
+/** error status register contains error */
+#define STATUS_ERROR 0x00000010
+
+/** Op status register contains op status */
+#define OP_STATUS 0x00000020
+
+
+/* High Level functions */
+int                sah_HW_Reset(void);
+fsl_shw_return_t   sah_HW_Set_HA(void);
+sah_Execute_Status sah_Wait_On_Sahara(void);
+
+/* Low Level functions */
+uint32_t    sah_HW_Read_Version(void);
+uint32_t    sah_HW_Read_Control(void);
+uint32_t    sah_HW_Read_Status(void);
+uint32_t    sah_HW_Read_Error_Status(void);
+uint32_t    sah_HW_Read_Op_Status(void);
+uint32_t    sah_HW_Read_DAR(void);
+uint32_t    sah_HW_Read_CDAR(void);
+uint32_t    sah_HW_Read_IDAR(void);
+uint32_t    sah_HW_Read_Fault_Address(void);
+uint32_t    sah_HW_Read_MM_Status(void);
+uint32_t    sah_HW_Read_Config(void);
+void        sah_HW_Write_Command(uint32_t command);
+void        sah_HW_Write_Control(uint32_t control);
+void        sah_HW_Write_DAR(uint32_t pointer);
+void        sah_HW_Write_Config(uint32_t configuration);
+
+#if defined DIAG_DRV_IF || defined(DO_DBG)
+
+void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr,
+		    unsigned length);
+#endif
+
+#endif  /* SAH_HARDWARE_INTERFACE_H */
+
+/* End of sah_hardware_interface.c */
diff --git a/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h b/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h
new file mode 100644
index 000000000000..8eb8690ff093
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_interrupt_handler.h
+*
+* @brief Provides a hardware interrupt handling mechanism for device driver.
+*
+*/
+/******************************************************************************
+*
+* CAUTION:
+*
+* MODIFICATION HISTORY:
+*
+* Date      Person     Change
+* 30/07/03  MW         Initial Creation
+*******************************************************************
+*/
+
+#ifndef SAH_INTERRUPT_HANDLER_H
+#define SAH_INTERRUPT_HANDLER_H
+
+#include <sah_driver_common.h>
+
+/******************************************************************************
+* External function declarations
+******************************************************************************/
+int sah_Intr_Init (wait_queue_head_t *wait_queue);
+void sah_Intr_Release (void);
+
+#endif  /* SAH_INTERRUPT_HANDLER_H */
diff --git a/drivers/mxc/security/sahara2/include/sah_kernel.h b/drivers/mxc/security/sahara2/include/sah_kernel.h
new file mode 100644
index 000000000000..13c1f170b9dc
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_kernel.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+* @file sah_kernel.h
+*
+* @brief Provides definitions for items that user-space and kernel-space share.
+*/
+/******************************************************************************
+*
+* This file needs to be PORTED to a non-Linux platform
+*/
+
+#ifndef SAH_KERNEL_H
+#define SAH_KERNEL_H
+
+#if defined(__KERNEL__)
+
+#if defined(CONFIG_ARCH_MXC91321) || defined(CONFIG_ARCH_MXC91231)     \
+    || defined(CONFIG_ARCH_MX27)  || defined(CONFIG_ARCH_MXC92323)
+#include <mach/hardware.h>
+#define SAHA_BASE_ADDR SAHARA_BASE_ADDR
+#define SAHARA_IRQ     MXC_INT_SAHARA
+#elif defined(CONFIG_ARCH_MX5)
+#include <mach/hardware.h>
+#define SAHA_BASE_ADDR SAHARA_BASE_ADDR
+#define SAHARA_IRQ     MXC_INT_SAHARA_H0
+#else
+#include <mach/mx2.h>
+#endif
+
+#endif				/* KERNEL */
+
+/* IO Controls */
+/* The magic number 'k' is reserved for the SPARC architecture. (See <kernel
+ * source root>/Documentation/ioctl-number.txt.
+ *
+ * Note: Numbers 8-13 were used in a previous version of the API and should
+ *       be avoided.
+ */
+#define SAH_IOC_MAGIC        'k'
+#define SAHARA_HWRESET       _IO(SAH_IOC_MAGIC, 0)
+#define SAHARA_SET_HA        _IO(SAH_IOC_MAGIC, 1)
+#define SAHARA_CHK_TEST_MODE _IOR(SAH_IOC_MAGIC,2, int)
+#define SAHARA_DAR           _IO(SAH_IOC_MAGIC, 3)
+#define SAHARA_GET_RESULTS   _IO(SAH_IOC_MAGIC, 4)
+#define SAHARA_REGISTER      _IO(SAH_IOC_MAGIC, 5)
+#define SAHARA_DEREGISTER    _IO(SAH_IOC_MAGIC, 6)
+/*                                              7 */
+/*                                              8 */
+/*                                              9 */
+/*                                             10 */
+/*                                             11 */
+/*                                             12 */
+/*                                             13 */
+
+#define SAHARA_SCC_DROP_PERMS _IOWR(SAH_IOC_MAGIC, 14, scc_partition_info_t)
+#define SAHARA_SCC_SFREE     _IOWR(SAH_IOC_MAGIC, 15, scc_partition_info_t)
+
+#define SAHARA_SK_ALLOC     _IOWR(SAH_IOC_MAGIC, 16, scc_slot_t)
+#define SAHARA_SK_DEALLOC   _IOWR(SAH_IOC_MAGIC, 17, scc_slot_t)
+#define SAHARA_SK_LOAD      _IOWR(SAH_IOC_MAGIC, 18, scc_slot_t)
+#define SAHARA_SK_UNLOAD    _IOWR(SAH_IOC_MAGIC, 19, scc_slot_t)
+#define SAHARA_SK_SLOT_ENC  _IOWR(SAH_IOC_MAGIC, 20, scc_slot_t)
+#define SAHARA_SK_SLOT_DEC  _IOWR(SAH_IOC_MAGIC, 21, scc_slot_t)
+
+#define SAHARA_SCC_ENCRYPT  _IOWR(SAH_IOC_MAGIC, 22, scc_region_t)
+#define SAHARA_SCC_DECRYPT  _IOWR(SAH_IOC_MAGIC, 23, scc_region_t)
+#define SAHARA_GET_CAPS     _IOWR(SAH_IOC_MAGIC, 24, fsl_shw_pco_t)
+
+#define SAHARA_SCC_SSTATUS  _IOWR(SAH_IOC_MAGIC, 25, scc_partition_info_t)
+
+#define SAHARA_SK_READ      _IOWR(SAH_IOC_MAGIC, 29, scc_slot_t)
+
+/*! This is the name that will appear in /proc/interrupts */
+#define SAHARA_NAME         "SAHARA"
+
+/*!
+ * SAHARA IRQ number. See page 9-239 of TLICS - Motorola Semiconductors H.K.
+ * TAHITI-Lite IC Specification, Rev 1.1, Feb 2003.
+ *
+ * TAHITI has two blocks of 32 interrupts. The SAHARA IRQ is number 27
+ * in the second block. This means that the SAHARA IRQ is 27 + 32 = 59.
+ */
+#ifndef SAHARA_IRQ
+#define SAHARA_IRQ          (27+32)
+#endif
+
+/*!
+ * Device file definition. The #ifndef is here to support the unit test code
+ * by allowing it to specify a different test device.
+ */
+#ifndef SAHARA_DEVICE_SHORT
+#define SAHARA_DEVICE_SHORT "sahara"
+#endif
+
+#ifndef SAHARA_DEVICE
+#define SAHARA_DEVICE       "/dev/"SAHARA_DEVICE_SHORT
+#endif
+
+#endif				/* SAH_KERNEL_H */
+
+/* End of sah_kernel.h */
diff --git a/drivers/mxc/security/sahara2/include/sah_memory_mapper.h b/drivers/mxc/security/sahara2/include/sah_memory_mapper.h
new file mode 100644
index 000000000000..838ce47cbf85
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_memory_mapper.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_memory_mapper.h
+*
+* @brief Re-creates SAHARA data structures in Kernel memory such that they are
+*       suitable for DMA.
+*
+*/
+
+#ifndef SAH_MEMORY_MAPPER_H
+#define SAH_MEMORY_MAPPER_H
+
+#include <sah_driver_common.h>
+#include <sah_queue_manager.h>
+
+
+/******************************************************************************
+* External function declarations
+******************************************************************************/
+sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx,
+					sah_Head_Desc * desc);
+
+sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr);
+
+sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * desc);
+
+sah_Link *sah_Physicalise_Links (sah_Link *ptr);
+
+sah_Head_Desc *sah_DePhysicalise_Descriptors (sah_Head_Desc *desc);
+
+sah_Link *sah_DePhysicalise_Links (sah_Link *ptr);
+
+sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx,
+			 sah_Link * ptr, sah_Link ** tail);
+
+
+void sah_Destroy_Descriptors (sah_Head_Desc *desc);
+
+void sah_Destroy_Links (sah_Link *link);
+
+void sah_Free_Chained_Descriptors (sah_Head_Desc *desc);
+
+void sah_Free_Chained_Links (sah_Link *link);
+
+int sah_Init_Mem_Map (void);
+
+void sah_Stop_Mem_Map (void);
+
+int sah_Block_Add_Page (int big);
+
+sah_Desc *sah_Alloc_Descriptor (void);
+sah_Head_Desc *sah_Alloc_Head_Descriptor (void);
+void sah_Free_Descriptor (sah_Desc *desc);
+void sah_Free_Head_Descriptor (sah_Head_Desc *desc);
+sah_Link *sah_Alloc_Link (void);
+void sah_Free_Link (sah_Link *link);
+
+void *wire_user_memory(void *address, uint32_t length, void **page_ctx);
+void unwire_user_memory(void **page_ctx);
+
+os_error_code map_user_memory(struct vm_area_struct *vma,
+			      uint32_t physical_addr, uint32_t size);
+os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size);
+
+#endif  /* SAH_MEMORY_MAPPER_H */
+
+/* End of sah_memory_mapper.h */
diff --git a/drivers/mxc/security/sahara2/include/sah_queue_manager.h b/drivers/mxc/security/sahara2/include/sah_queue_manager.h
new file mode 100644
index 000000000000..2dde5883e193
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_queue_manager.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_queue_manager.h
+*
+* @brief This file definitions for the Queue Manager.
+
+* The Queue Manager manages additions and removal from the queue and updates
+* the status of queue entries. It also calls sah_HW_* functions to interact
+* with the hardware.
+*
+*/
+
+#ifndef SAH_QUEUE_MANAGER_H
+#define SAH_QUEUE_MANAGER_H
+
+#include <sah_driver_common.h>
+#include <sah_status_manager.h>
+
+
+/*************************
+* Queue Manager Functions
+*************************/
+fsl_shw_return_t sah_Queue_Manager_Init(void);
+void             sah_Queue_Manager_Close(void);
+void             sah_Queue_Manager_Reset_Entries(void);
+void             sah_Queue_Manager_Append_Entry(sah_Head_Desc *entry);
+void             sah_Queue_Manager_Remove_Entry(sah_Head_Desc *entry);
+
+
+/*************************
+* Queue Functions
+*************************/
+sah_Queue *sah_Queue_Construct(void);
+void      sah_Queue_Destroy(sah_Queue *this);
+void      sah_Queue_Append_Entry(sah_Queue *this, sah_Head_Desc *entry);
+void      sah_Queue_Remove_Entry(sah_Queue *this);
+void      sah_Queue_Remove_Any_Entry(sah_Queue *this, sah_Head_Desc *entry);
+void      sah_postprocess_queue(unsigned long reset_flag);
+
+
+/*************************
+* Misc Releated Functions
+*************************/
+
+int              sah_blocking_mode(struct sah_Head_Desc *entry);
+fsl_shw_return_t sah_convert_error_status(uint32_t error_status);
+
+
+#endif  /* SAH_QUEUE_MANAGER_H */
+
+/* End of sah_queue_manager.h */
diff --git a/drivers/mxc/security/sahara2/include/sah_status_manager.h b/drivers/mxc/security/sahara2/include/sah_status_manager.h
new file mode 100644
index 000000000000..e38731bf4835
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sah_status_manager.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sah_status_manager.h
+*
+* @brief SAHARA Status Manager Types and Function Prototypes
+*
+* @author Stuart Holloway (SH)
+*
+*/
+
+#ifndef STATUS_MANAGER_H
+#define STATUS_MANAGER_H
+#include "sah_driver_common.h"
+#include "sahara.h"
+
+
+/******************************************************************************
+* User defined data types
+******************************************************************************/
+/**
+******************************************************************************
+* sah_Execute_Status
+* Types read from SAHARA Status Register, with additional state for Op Status
+******************************************************************************/
+typedef enum sah_Execute_Status
+{
+    /** Sahara is Idle. */
+    SAH_EXEC_IDLE = 0,
+    /** SAHARA is busy performing a resest or processing a decriptor chain. */
+    SAH_EXEC_BUSY = 1,
+    /** An error occurred while SAHARA executed the first descriptor. */
+    SAH_EXEC_ERROR1 = 2,
+    /** SAHARA has failed internally. */
+    SAH_EXEC_FAULT = 3,
+    /** SAHARA has finished processing a descriptor chain and is idle. */
+    SAH_EXEC_DONE1 = 4,
+    /** SAHARA has finished processing a descriptor chain, and is processing a
+     *   second chain.  */
+    SAH_EXEC_DONE1_BUSY2 = 5,
+    /** SAHARA has finished processing a descriptor chain, but has generated an
+     *   error while processing a second descriptor chain. */
+    SAH_EXEC_DONE1_ERROR2 = 6,
+    /** SAHARA has finished two descriptors. */
+    SAH_EXEC_DONE1_DONE2 = 7,
+    /** SAHARA has stopped, and first descriptor has Op Status, not Err  */
+    SAH_EXEC_OPSTAT1 = 0x20,
+} sah_Execute_Status;
+
+/**
+ * When this bit is on in a #sah_Execute_Status, it means that DONE1 is true.
+ */
+#define SAH_EXEC_DONE1_BIT  4
+
+/**
+ * Bits which make up the Sahara State
+ */
+#define SAH_EXEC_STATE_MASK 0x00000007
+
+/**
+*******************************************************************************
+* sah_Execute_Error
+* Types read from SAHARA Error Status Register
+******************************************************************************/
+typedef enum sah_Execute_Error
+{
+    /** No Error */
+    SAH_ERR_NONE = 0,
+    /** Header is not valid. */
+    SAH_ERR_HEADER = 1,
+    /** Descriptor length is not correct. */
+    SAH_ERR_DESC_LENGTH = 2,
+    /** Length or pointer field is zero while the other is non-zero.  */
+    SAH_ERR_DESC_POINTER = 3,
+    /** Length of the link is not a multiple of 4 and is not the last link */
+    SAH_ERR_LINK_LENGTH = 4,
+    /** The data pointer in a link is zero */
+    SAH_ERR_LINK_POINTER = 5,
+    /** Input Buffer reported an overflow */
+    SAH_ERR_INPUT_BUFFER = 6,
+    /** Output Buffer reported an underflow */
+    SAH_ERR_OUTPUT_BUFFER = 7,
+    /** Incorrect data in output buffer after CHA's has signalled 'done'. */
+    SAH_ERR_OUTPUT_BUFFER_STARVATION = 8,
+    /** Internal Hardware Failure. */
+    SAH_ERR_INTERNAL_STATE = 9,
+    /** Current Descriptor was not legal, but cause is unknown. */
+    SAH_ERR_GENERAL_DESCRIPTOR = 10,
+    /** Reserved pointer fields have been set to 1. */
+    SAH_ERR_RESERVED_FIELDS = 11,
+    /** Descriptor address error */
+    SAH_ERR_DESCRIPTOR_ADDRESS = 12,
+    /** Link address error */
+    SAH_ERR_LINK_ADDRESS = 13,
+    /** Processing error in CHA module */
+    SAH_ERR_CHA = 14,
+    /** Processing error during DMA */
+    SAH_ERR_DMA = 15
+} sah_Execute_Error;
+
+
+/**
+*******************************************************************************
+* sah_CHA_Error_Source
+* Types read from SAHARA Error Status Register for CHA Error Source
+*
+******************************************************************************/
+typedef enum sah_CHA_Error_Source
+{
+    /** No Error indicated in Source CHA Error. */
+    SAH_CHA_NO_ERROR = 0,
+    /** Error in SKHA module. */
+    SAH_CHA_SKHA_ERROR = 1,
+    /** Error in MDHA module. */
+    SAH_CHA_MDHA_ERROR = 2,
+    /** Error in RNG module.  */
+    SAH_CHA_RNG_ERROR = 3,
+    /** Error in PKHA module.  */
+    SAH_CHA_PKHA_ERROR = 4,
+} sah_CHA_Error_Source;
+
+/**
+******************************************************************************
+* sah_CHA_Error_Status
+* Types read from SAHARA Error Status Register for CHA Error Status
+*
+******************************************************************************/
+typedef enum sah_CHA_Error_Status
+{
+    /** No CHA error detected */
+    SAH_CHA_NO_ERR = 0x000,
+    /** Non-empty input buffer when complete. */
+    SAH_CHA_IP_BUF = 0x001,
+    /** Illegal Address Error. */
+    SAH_CHA_ADD_ERR = 0x002,
+    /** Illegal Mode Error.  */
+    SAH_CHA_MODE_ERR = 0x004,
+    /** Illegal Data Size Error. */
+    SAH_CHA_DATA_SIZE_ERR = 0x008,
+    /** Illegal Key Size Error. */
+    SAH_CHA_KEY_SIZE_ERR = 0x010,
+    /** Mode/Context/Key written during processing. */
+    SAH_CHA_PROC_ERR = 0x020,
+    /** Context Read During Processing. */
+    SAH_CHA_CTX_READ_ERR = 0x040,
+    /** Internal Hardware Error. */
+    SAH_CHA_INTERNAL_HW_ERR = 0x080,
+    /** Input Buffer not enabled or underflow. */
+    SAH_CHA_IP_BUFF_ERR = 0x100,
+    /** Output Buffer not enabled or overflow. */
+    SAH_CHA_OP_BUFF_ERR = 0x200,
+    /** DES key parity error (SKHA) */
+    SAH_CHA_DES_KEY_ERR = 0x400,
+    /** Reserved error code. */
+    SAH_CHA_RES = 0x800
+} sah_CHA_Error_Status;
+
+/**
+*****************************************************************************
+* sah_DMA_Error_Status
+* Types read from SAHARA Error Status Register for DMA Error Status
+******************************************************************************/
+typedef enum sah_DMA_Error_Status
+{
+    /** No DMA Error Code. */
+    SAH_DMA_NO_ERR = 0,
+    /** AHB terminated a bus cycle with an error. */
+    SAH_DMA_AHB_ERR = 2,
+    /** Internal IP bus cycle was terminated with an error termination. */
+    SAH_DMA_IP_ERR = 4,
+    /** Parity error detected on DMA command. */
+    SAH_DMA_PARITY_ERR = 6,
+    /** DMA was requested to cross a 256 byte internal address boundary. */
+    SAH_DMA_BOUNDRY_ERR = 8,
+    /** DMA controller is busy */
+    SAH_DMA_BUSY_ERR = 10,
+    /** Memory Bounds Error */
+    SAH_DMA_RESERVED_ERR = 12,
+    /** Internal DMA hardware error detected */
+    SAH_DMA_INT_ERR = 14
+} sah_DMA_Error_Status;
+
+/**
+*****************************************************************************
+* sah_DMA_Error_Size
+* Types read from SAHARA Error Status Register for DMA Error Size
+*
+******************************************************************************/
+typedef enum sah_DMA_Error_Size
+{
+    /** Error during Byte transfer.  */
+    SAH_DMA_SIZE_BYTE = 0,
+    /** Error during Half-word transfer. */
+    SAH_DMA_SIZE_HALF_WORD = 1,
+    /** Error during Word transfer. */
+    SAH_DMA_SIZE_WORD = 2,
+    /** Reserved DMA word size. */
+    SAH_DMA_SIZE_RES = 3
+} sah_DMA_Error_Size;
+
+
+
+
+extern bool sah_dpm_flag;
+
+/*************************
+* Status Manager Functions
+*************************/
+
+unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status);
+sah_Head_Desc *sah_Find_With_State (sah_Queue_Status status);
+int sah_dpm_init(void);
+void sah_dpm_close(void);
+void sah_Queue_Manager_Prime (sah_Head_Desc *entry);
+
+
+#endif  /* STATUS_MANAGER_H */
diff --git a/drivers/mxc/security/sahara2/include/sahara.h b/drivers/mxc/security/sahara2/include/sahara.h
new file mode 100644
index 000000000000..28f4e1448c29
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sahara.h
@@ -0,0 +1,2265 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sahara.h
+ *
+ * File which implements the FSL_SHW API when used on Sahara
+ */
+/*!
+ * @if USE_MAINPAGE
+ * @mainpage Sahara2 implemtation of FSL Security Hardware API
+ * @endif
+ *
+ */
+
+#define _DIAG_DRV_IF
+#define _DIAG_SECURITY_FUNC
+#define _DIAG_ADAPTOR
+
+#ifndef SAHARA2_API_H
+#define SAHARA2_API_H
+
+#ifdef DIAG_SECURITY_FUNC
+#include <diagnostic.h>
+#endif				/* DIAG_SECURITY_FUNC */
+
+/* This is a Linux flag... ? */
+#ifndef __KERNEL__
+#include <inttypes.h>
+#include <stdlib.h>
+#include <memory.h>
+#else
+#include "portable_os.h"
+#endif
+
+/* This definition may need a new name, and needs to go somewhere which
+ * can determine platform, kernel vs. user, os, etc.
+ */
+#define copy_bytes(out, in, len) memcpy(out, in, len)
+
+/* Does this belong here? */
+#ifndef SAHARA_DEVICE
+#define SAHARA_DEVICE "/dev/sahara"
+#endif
+
+/*!
+*******************************************************************************
+* @defgroup lnkflags Link Flags
+*
+* @brief Flags to show information about link data and link segments
+*
+******************************************************************************/
+/*! @addtogroup lnkflags
+ * @{
+ */
+
+/*!
+*******************************************************************************
+* This flag indicates that the data in a link is owned by the security
+* function component and this memory will be freed by the security function
+* component. To be used as part of the flag field of the sah_Link structure.
+******************************************************************************/
+#define SAH_OWNS_LINK_DATA          0x01
+
+/*!
+*******************************************************************************
+* The data in a link is not owned by the security function component and
+* therefore it will not attempt to free this memory. To be used as part of the
+* flag field of the sah_Link structure.
+******************************************************************************/
+#define SAH_USES_LINK_DATA          0x02
+
+/*!
+*******************************************************************************
+* The data in this link will change when the descriptor gets executed.
+******************************************************************************/
+#define SAH_OUTPUT_LINK             0x04
+
+/*!
+*******************************************************************************
+* The ptr and length in this link are really 'established key' info.  They
+* are to be converted to ptr/length before putting on request queue.
+******************************************************************************/
+#define SAH_KEY_IS_HIDDEN           0x08
+
+/*!
+*******************************************************************************
+* The link structure has been appended to the previous one by the driver.  It
+* needs to be removed before leaving the driver (and returning to API).
+******************************************************************************/
+#define SAH_REWORKED_LINK           0x10
+
+/*!
+*******************************************************************************
+* The length and data fields of this link contain the slot and user id
+* used to access the SCC stored key
+******************************************************************************/
+#define SAH_STORED_KEY_INFO         0x20
+
+/*!
+*******************************************************************************
+* The Data field points to a physical address, and does not need to be
+* processed by the driver.  Honored only in Kernel API.
+******************************************************************************/
+#define SAH_PREPHYS_DATA            0x40
+
+/*!
+*******************************************************************************
+* The link was inserted during the Physicalise procedure.  It is tagged so
+* it can be removed during DePhysicalise, thereby returning to the caller an
+* intact chain.
+******************************************************************************/
+#define SAH_LINK_INSERTED_LINK      0x80
+
+/*!
+*******************************************************************************
+* The Data field points to the location of the key, which is in a secure
+* partition held by the user.  The memory address needs to be converted to
+* kernel space manually, by looking through the partitions that the user holds.
+******************************************************************************/
+#define SAH_IN_USER_KEYSTORE       0x100
+
+/*!
+*******************************************************************************
+* sah_Link_Flags
+*
+* Type to be used for flags associated with a Link in security function.
+* These flags are used internally by the security function component only.
+*
+* Values defined at @ref lnkflags
+*
+* @brief typedef for flags field of sah_Link
+******************************************************************************/
+typedef uint32_t sah_Link_Flags;
+
+/*
+*******************************************************************************
+* Security Parameters Related Structures
+*
+* All of structures associated with API parameters
+*
+******************************************************************************/
+
+/*
+*******************************************************************************
+* Common Types
+*
+* All of structures used across several classes of crytography
+******************************************************************************/
+
+/*!
+*******************************************************************************
+* @brief Indefinite precision integer used for security operations on SAHARA
+* accelerator. The data will always be in little Endian format.
+******************************************************************************/
+typedef uint8_t *sah_Int;
+
+/*!
+*******************************************************************************
+* @brief Byte array used for block cipher and hash digest/MAC operations on
+* SAHARA accelerator. The Endian format will be as specified by the function
+* using the sah_Oct_Str.
+******************************************************************************/
+typedef uint8_t *sah_Oct_Str;
+
+/*!
+ * A queue of descriptor heads -- used to hold requests waiting for user to
+ * pick up the results. */
+typedef struct sah_Queue {
+	int count;		/*!< # entries in queue  */
+	struct sah_Head_Desc *head;	/*!< first entry in queue  */
+	struct sah_Head_Desc *tail;	/*!< last entry in queue   */
+} sah_Queue;
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+/*!
+ * Flags for the state of the User Context Object (#fsl_shw_uco_t).
+ */
+typedef enum fsl_shw_user_ctx_flags_t {
+	/*!
+	 * API will block the caller until operation completes.  The result will be
+	 * available in the return code.  If this is not set, user will have to get
+	 * results using #fsl_shw_get_results().
+	 */
+	FSL_UCO_BLOCKING_MODE = 0x01,
+	/*!
+	 * User wants callback (at the function specified with
+	 * #fsl_shw_uco_set_callback()) when the operation completes.  This flag is
+	 * valid only if #FSL_UCO_BLOCKING_MODE is not set.
+	 */
+	FSL_UCO_CALLBACK_MODE = 0x02,
+	/*! Do not free descriptor chain after driver (adaptor) finishes */
+	FSL_UCO_SAVE_DESC_CHAIN = 0x04,
+	/*!
+	 * User has made at least one request with callbacks requested, so API is
+	 * ready to handle others.
+	 */
+	FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08,
+	/*!
+	 * (virtual) pointer to descriptor chain is completely linked with physical
+	 * (DMA) addresses, ready for the hardware.  This flag should not be used
+	 * by FSL SHW API programs.
+	 */
+	FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10,
+	/*!
+	 * The user has changed the context but the changes have not been copied to
+	 * the kernel driver.
+	 */
+	FSL_UCO_CONTEXT_CHANGED = 0x20,
+	/*! Internal Use.  This context belongs to a user-mode API user. */
+	FSL_UCO_USERMODE_USER = 0x40,
+} fsl_shw_user_ctx_flags_t;
+
+/*!
+ * Return code for FSL_SHW library.
+ *
+ * These codes may be returned from a function call.  In non-blocking mode,
+ * they will appear as the status in a Result Object.
+ */
+typedef enum fsl_shw_return_t {
+	/*!
+	 * No error.  As a function return code in Non-blocking mode, this may
+	 * simply mean that the operation was accepted for eventual execution.
+	 */
+	FSL_RETURN_OK_S = 0,
+	/*! Failure for non-specific reason. */
+	FSL_RETURN_ERROR_S,
+	/*!
+	 * Operation failed because some resource was not able to be allocated.
+	 */
+	FSL_RETURN_NO_RESOURCE_S,
+	/*! Crypto algorithm unrecognized or improper. */
+	FSL_RETURN_BAD_ALGORITHM_S,
+	/*! Crypto mode unrecognized or improper. */
+	FSL_RETURN_BAD_MODE_S,
+	/*! Flag setting unrecognized or inconsistent. */
+	FSL_RETURN_BAD_FLAG_S,
+	/*! Improper or unsupported key length for algorithm. */
+	FSL_RETURN_BAD_KEY_LENGTH_S,
+	/*! Improper parity in a (DES, TDES) key. */
+	FSL_RETURN_BAD_KEY_PARITY_S,
+	/*!
+	 * Improper or unsupported data length for algorithm or internal buffer.
+	 */
+	FSL_RETURN_BAD_DATA_LENGTH_S,
+	/*! Authentication / Integrity Check code check failed. */
+	FSL_RETURN_AUTH_FAILED_S,
+	/*! A memory error occurred. */
+	FSL_RETURN_MEMORY_ERROR_S,
+	/*! An error internal to the hardware occurred. */
+	FSL_RETURN_INTERNAL_ERROR_S,
+	/*! ECC detected Point at Infinity */
+	FSL_RETURN_POINT_AT_INFINITY_S,
+	/*! ECC detected No Point at Infinity */
+	FSL_RETURN_POINT_NOT_AT_INFINITY_S,
+	/*! GCD is One */
+	FSL_RETURN_GCD_IS_ONE_S,
+	/*! GCD is not One */
+	FSL_RETURN_GCD_IS_NOT_ONE_S,
+	/*! Candidate is Prime */
+	FSL_RETURN_PRIME_S,
+	/*! Candidate is not Prime */
+	FSL_RETURN_NOT_PRIME_S,
+	/*! N register loaded improperly with even value */
+	FSL_RETURN_EVEN_MODULUS_ERROR_S,
+	/*! Divisor is zero. */
+	FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S,
+	/*! Bad Exponent or Scalar value for Point Multiply */
+	FSL_RETURN_BAD_EXPONENT_ERROR_S,
+	/*! RNG hardware problem. */
+	FSL_RETURN_OSCILLATOR_ERROR_S,
+	/*! RNG hardware problem. */
+	FSL_RETURN_STATISTICS_ERROR_S,
+} fsl_shw_return_t;
+
+/*!
+ * Algorithm Identifier.
+ *
+ * Selection of algorithm will determine how large the block size of the
+ * algorithm is.   Context size is the same length unless otherwise specified.
+ * Selection of algorithm also affects the allowable key length.
+ */
+typedef enum fsl_shw_key_alg_t {
+	/*!
+	 * Key will be used to perform an HMAC.  Key size is 1 to 64 octets.  Block
+	 * size is 64 octets.
+	 */
+	FSL_KEY_ALG_HMAC,
+	/*!
+	 * Advanced Encryption Standard (Rijndael).  Block size is 16 octets.  Key
+	 * size is 16 octets.  (The single choice of key size is a Sahara platform
+	 * limitation.)
+	 */
+	FSL_KEY_ALG_AES,
+	/*!
+	 * Data Encryption Standard.  Block size is 8 octets.  Key size is 8
+	 * octets.
+	 */
+	FSL_KEY_ALG_DES,
+	/*!
+	 * 2- or 3-key Triple DES.  Block size is 8 octets.  Key size is 16 octets
+	 * for 2-key Triple DES, and 24 octets for 3-key.
+	 */
+	FSL_KEY_ALG_TDES,
+	/*!
+	 * ARC4.  No block size.  Context size is 259 octets.  Allowed key size is
+	 * 1-16 octets.  (The choices for key size are a Sahara platform
+	 * limitation.)
+	 */
+	FSL_KEY_ALG_ARC4,
+	/*!
+	 * Private key of a public-private key-pair.  Max is 512 bits...
+	 */
+	FSL_KEY_PK_PRIVATE,
+} fsl_shw_key_alg_t;
+
+/*!
+ * Mode selector for Symmetric Ciphers.
+ *
+ * The selection of mode determines how a cryptographic algorithm will be
+ * used to process the plaintext or ciphertext.
+ *
+ * For all modes which are run block-by-block (that is, all but
+ * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text
+ * length which is multiple of the block size.  Except for #FSL_SYM_MODE_CTR,
+ * these block-by-block algorithms must also be passed a total number of octets
+ * which is a multiple of the block size.
+ *
+ * In modes which require that the total number of octets of data be a multiple
+ * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user
+ * has a total number of octets which are not a multiple of the block size, the
+ * user must perform any necessary padding to get to the correct data length.
+ */
+typedef enum fsl_shw_sym_mode_t {
+	/*!
+	 * Stream.  There is no associated block size.  Any request to process data
+	 * may be of any length.  This mode is only for ARC4 operations, and is
+	 * also the only mode used for ARC4.
+	 */
+	FSL_SYM_MODE_STREAM,
+
+	/*!
+	 * Electronic Codebook.  Each block of data is encrypted/decrypted.  The
+	 * length of the data stream must be a multiple of the block size.  This
+	 * mode may be used for DES, 3DES, and AES.  The block size is determined
+	 * by the algorithm.
+	 */
+	FSL_SYM_MODE_ECB,
+	/*!
+	 * Cipher-Block Chaining.  Each block of data is encrypted/decrypted and
+	 * then "chained" with the previous block by an XOR function.  Requires
+	 * context to start the XOR (previous block).  This mode may be used for
+	 * DES, 3DES, and AES.  The block size is determined by the algorithm.
+	 */
+	FSL_SYM_MODE_CBC,
+	/*!
+	 * Counter.  The counter is encrypted, then XORed with a block of data.
+	 * The counter is then incremented (using modulus arithmetic) for the next
+	 * block. The final operation may be non-multiple of block size.  This mode
+	 * may be used for AES.  The block size is determined by the algorithm.
+	 */
+	FSL_SYM_MODE_CTR,
+} fsl_shw_sym_mode_t;
+
+/*!
+ * Algorithm selector for Cryptographic Hash functions.
+ *
+ * Selection of algorithm determines how large the context and digest will be.
+ * Context is the same size as the digest (resulting hash), unless otherwise
+ * specified.
+ */
+typedef enum fsl_shw_hash_alg_t {
+	/*! MD5 algorithm.  Digest is 16 octets. */
+	FSL_HASH_ALG_MD5,
+	/*! SHA-1 (aka SHA or SHA-160) algorithm. Digest is 20 octets. */
+	FSL_HASH_ALG_SHA1,
+	/*!
+	 * SHA-224 algorithm.  Digest is 28 octets, though context is 32 octets.
+	 */
+	FSL_HASH_ALG_SHA224,
+	/*! SHA-256 algorithm.  Digest is 32 octets. */
+	FSL_HASH_ALG_SHA256
+} fsl_shw_hash_alg_t;
+
+/*!
+ * The type of Authentication-Cipher function which will be performed.
+ */
+typedef enum fsl_shw_acc_mode_t {
+	/*!
+	 * CBC-MAC for Counter.  Requires context and modulus.  Final operation may
+	 * be non-multiple of block size.  This mode may be used for AES.
+	 */
+	FSL_ACC_MODE_CCM,
+	/*!
+	 * SSL mode.  Not supported.  Combines HMAC and encrypt (or decrypt).
+	 * Needs one key object for encryption, another for the HMAC.  The usual
+	 * hashing and symmetric encryption algorithms are supported.
+	 */
+	FSL_ACC_MODE_SSL,
+} fsl_shw_acc_mode_t;
+
+/* REQ-S2LRD-PINTFC-COA-HCO-001 */
+/*!
+ * Flags which control a Hash operation.
+ */
+typedef enum fsl_shw_hash_ctx_flags_t {
+	/*!
+	 * Context is empty.  Hash is started from scratch, with a
+	 * message-processed count of zero.
+	 */
+	FSL_HASH_FLAGS_INIT = 0x01,
+	/*!
+	 *  Retrieve context from hardware after hashing.  If used with the
+	 *  #FSL_HASH_FLAGS_FINALIZE flag, the final digest value will be saved in
+	 *  the object.
+	 */
+	FSL_HASH_FLAGS_SAVE = 0x02,
+	/*! Place context into hardware before hashing. */
+	FSL_HASH_FLAGS_LOAD = 0x04,
+	/*!
+	 * PAD message and perform final digest operation.  If user message is
+	 * pre-padded, this flag should not be used.
+	 */
+	FSL_HASH_FLAGS_FINALIZE = 0x08,
+} fsl_shw_hash_ctx_flags_t;
+
+/*!
+ * Flags which control an HMAC operation.
+ *
+ * These may be combined by ORing them together.  See #fsl_shw_hmco_set_flags()
+ * and #fsl_shw_hmco_clear_flags().
+ */
+typedef enum fsl_shw_hmac_ctx_flags_t {
+	/*!
+	 * Message context is empty.  HMAC is started from scratch (with key) or
+	 * from precompute of inner hash, depending on whether
+	 * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is set.
+	 */
+	FSL_HMAC_FLAGS_INIT = 1,
+	/*!
+	 * Retrieve ongoing context from hardware after hashing.  If used with the
+	 * #FSL_HMAC_FLAGS_FINALIZE flag, the final digest value (HMAC) will be
+	 * saved in the object.
+	 */
+	FSL_HMAC_FLAGS_SAVE = 2,
+	/*! Place ongoing context into hardware before hashing. */
+	FSL_HMAC_FLAGS_LOAD = 4,
+	/*!
+	 * PAD message and perform final HMAC operations of inner and outer
+	 * hashes.
+	 */
+	FSL_HMAC_FLAGS_FINALIZE = 8,
+	/*!
+	 * This means that the context contains precomputed inner and outer hash
+	 * values.
+	 */
+	FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16,
+} fsl_shw_hmac_ctx_flags_t;
+
+/*!
+ * Flags to control use of the #fsl_shw_scco_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags()
+ */
+typedef enum fsl_shw_sym_ctx_flags_t {
+	/*!
+	 * Context is empty.  In ARC4, this means that the S-Box needs to be
+	 * generated from the key.  In #FSL_SYM_MODE_CBC mode, this allows an IV of
+	 * zero to be specified.  In #FSL_SYM_MODE_CTR mode, it means that an
+	 * initial CTR value of zero is desired.
+	 */
+	FSL_SYM_CTX_INIT = 1,
+	/*!
+	 * Load context from object into hardware before running cipher.  In
+	 * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+	 */
+	FSL_SYM_CTX_LOAD = 2,
+	/*!
+	 * Save context from hardware into object after running cipher.  In
+	 * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value.
+	 */
+	FSL_SYM_CTX_SAVE = 4,
+	/*!
+	 * Context (SBox) is to be unwrapped and wrapped on each use.
+	 * This flag is unsupported.
+	 * */
+	FSL_SYM_CTX_PROTECT = 8,
+} fsl_shw_sym_ctx_flags_t;
+
+/*!
+ * Flags which describe the state of the #fsl_shw_sko_t.
+ *
+ * These may be ORed together to get the desired effect.
+ * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags()
+ */
+typedef enum fsl_shw_key_flags_t {
+	/*! If algorithm is DES or 3DES, do not validate the key parity bits. */
+	FSL_SKO_KEY_IGNORE_PARITY = 1,
+	/*! Clear key is present in the object. */
+	FSL_SKO_KEY_PRESENT = 2,
+	/*!
+	 * Key has been established for use.  This feature is not available for all
+	 * platforms, nor for all algorithms and modes.
+	 */
+	FSL_SKO_KEY_ESTABLISHED = 4,
+	/*!
+	 * Key intended for user (software) use; can be read cleartext from the
+	 * keystore.
+	 */
+	FSL_SKO_KEY_SW_KEY = 8,
+} fsl_shw_key_flags_t;
+
+/*!
+ * Type of value which is associated with an established key.
+ */
+typedef uint64_t key_userid_t;
+
+/*!
+ * Flags which describe the state of the #fsl_shw_acco_t.
+ *
+ * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used
+ * together, provide for a one-shot operation.
+ */
+typedef enum fsl_shw_auth_ctx_flags_t {
+	/*! Initialize Context(s) */
+	FSL_ACCO_CTX_INIT = 1,
+	/*! Load intermediate context(s). This flag is unsupported. */
+	FSL_ACCO_CTX_LOAD = 2,
+	/*! Save intermediate context(s). This flag is unsupported. */
+	FSL_ACCO_CTX_SAVE = 4,
+	/*! Create MAC during this operation. */
+	FSL_ACCO_CTX_FINALIZE = 8,
+	/*!
+	 * Formatting of CCM input data is performed by calls to
+	 * #fsl_shw_ccm_nist_format_ctr_and_iv() and
+	 * #fsl_shw_ccm_nist_update_ctr_and_iv().
+	 */
+	FSL_ACCO_NIST_CCM = 0x10,
+} fsl_shw_auth_ctx_flags_t;
+
+/*!
+ * The operation which controls the behavior of #fsl_shw_establish_key().
+ *
+ * These values are passed to #fsl_shw_establish_key().
+ */
+typedef enum fsl_shw_key_wrap_t {
+	/*! Generate a key from random values. */
+	FSL_KEY_WRAP_CREATE,
+	/*! Use the provided clear key. */
+	FSL_KEY_WRAP_ACCEPT,
+	/*! Unwrap a previously wrapped key. */
+	FSL_KEY_WRAP_UNWRAP
+} fsl_shw_key_wrap_t;
+
+/*!
+ *  Modulus Selector for CTR modes.
+ *
+ * The incrementing of the Counter value may be modified by a modulus.  If no
+ * modulus is needed or desired for AES, use #FSL_CTR_MOD_128.
+ */
+typedef enum fsl_shw_ctr_mod_t {
+	FSL_CTR_MOD_8,		/*!< Run counter with modulus of 2^8. */
+	FSL_CTR_MOD_16,		/*!< Run counter with modulus of 2^16. */
+	FSL_CTR_MOD_24,		/*!< Run counter with modulus of 2^24. */
+	FSL_CTR_MOD_32,		/*!< Run counter with modulus of 2^32. */
+	FSL_CTR_MOD_40,		/*!< Run counter with modulus of 2^40. */
+	FSL_CTR_MOD_48,		/*!< Run counter with modulus of 2^48. */
+	FSL_CTR_MOD_56,		/*!< Run counter with modulus of 2^56. */
+	FSL_CTR_MOD_64,		/*!< Run counter with modulus of 2^64. */
+	FSL_CTR_MOD_72,		/*!< Run counter with modulus of 2^72. */
+	FSL_CTR_MOD_80,		/*!< Run counter with modulus of 2^80. */
+	FSL_CTR_MOD_88,		/*!< Run counter with modulus of 2^88. */
+	FSL_CTR_MOD_96,		/*!< Run counter with modulus of 2^96. */
+	FSL_CTR_MOD_104,	/*!< Run counter with modulus of 2^104. */
+	FSL_CTR_MOD_112,	/*!< Run counter with modulus of 2^112. */
+	FSL_CTR_MOD_120,	/*!< Run counter with modulus of 2^120. */
+	FSL_CTR_MOD_128		/*!< Run counter with modulus of 2^128. */
+} fsl_shw_ctr_mod_t;
+
+/*!
+ * Permissions flags for Secure Partitions
+ */
+typedef enum fsl_shw_permission_t {
+/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */
+	FSL_PERM_NO_ZEROIZE = 0x80000000,
+/*! SCM Access Permission: Enforce trusted key read in  */
+	FSL_PERM_TRUSTED_KEY_READ = 0x40000000,
+/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */
+	FSL_PERM_HD_S = 0x00000800,
+/*! SCM Access Permission: Allow Read Access to  Host Domain */
+	FSL_PERM_HD_R = 0x00000400,
+/*! SCM Access Permission: Allow Write Access to  Host Domain */
+	FSL_PERM_HD_W = 0x00000200,
+/*! SCM Access Permission: Allow Execute Access to  Host Domain */
+	FSL_PERM_HD_X = 0x00000100,
+/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */
+	FSL_PERM_TH_R = 0x00000040,
+/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */
+	FSL_PERM_TH_W = 0x00000020,
+/*! SCM Access Permission: Allow Read Access to Other/World Domain */
+	FSL_PERM_OT_R = 0x00000004,
+/*! SCM Access Permission: Allow Write Access to Other/World Domain */
+	FSL_PERM_OT_W = 0x00000002,
+/*! SCM Access Permission: Allow Execute Access to Other/World Domain */
+	FSL_PERM_OT_X = 0x00000001,
+} fsl_shw_permission_t;
+
+typedef enum fsl_shw_cypher_mode_t {
+	FSL_SHW_CYPHER_MODE_ECB = 1,	/*!< ECB mode */
+	FSL_SHW_CYPHER_MODE_CBC = 2,	/*!< CBC mode */
+} fsl_shw_cypher_mode_t;
+
+typedef enum fsl_shw_pf_key_t {
+	FSL_SHW_PF_KEY_IIM,	/*!< Present fused IIM key */
+	FSL_SHW_PF_KEY_PRG,	/*!< Present Program key */
+	FSL_SHW_PF_KEY_IIM_PRG,	/*!< Present IIM ^ Program key */
+	FSL_SHW_PF_KEY_IIM_RND,	/*!< Present Random key */
+	FSL_SHW_PF_KEY_RND,	/*!< Present IIM ^ Random key */
+} fsl_shw_pf_key_t;
+
+typedef enum fsl_shw_tamper_t {
+	FSL_SHW_TAMPER_NONE,	/*!< No error detected */
+	FSL_SHW_TAMPER_WTD,	/*!< wire-mesh tampering det */
+	FSL_SHW_TAMPER_ETBD,	/*!< ext tampering det: input B */
+	FSL_SHW_TAMPER_ETAD,	/*!< ext tampering det: input A */
+	FSL_SHW_TAMPER_EBD,	/*!< external boot detected */
+	FSL_SHW_TAMPER_SAD,	/*!< security alarm detected */
+	FSL_SHW_TAMPER_TTD,	/*!< temperature tampering det */
+	FSL_SHW_TAMPER_CTD,	/*!< clock tampering det */
+	FSL_SHW_TAMPER_VTD,	/*!< voltage tampering det */
+	FSL_SHW_TAMPER_MCO,	/*!< monotonic counter overflow */
+	FSL_SHW_TAMPER_TCO,	/*!< time counter overflow */
+} fsl_shw_tamper_t;
+
+/******************************************************************************
+ * Data Structures
+ *****************************************************************************/
+
+/*!
+ *
+ * @brief Structure type for descriptors
+ *
+ * The first five fields are passed to the hardware.
+ *
+ *****************************************************************************/
+#ifndef USE_NEW_PTRS		/* Experimental */
+
+typedef struct sah_Desc {
+	uint32_t header;	/*!< descriptor header value */
+	uint32_t len1;		/*!< number of data bytes in 'ptr1' buffer */
+	void *ptr1;		/*!< pointer to first sah_Link structure */
+	uint32_t len2;		/*!< number of data bytes in 'ptr2' buffer */
+	void *ptr2;		/*!< pointer to second sah_Link structure */
+	struct sah_Desc *next;	/*!< pointer to next descriptor */
+#ifdef __KERNEL__		/* This needs a better test */
+	/* These two must be last.  See sah_Copy_Descriptors */
+	struct sah_Desc *virt_addr;	/*!< Virtual (kernel) address of this
+					   descriptor. */
+	dma_addr_t dma_addr;	/*!< Physical (bus) address of this
+				   descriptor.  */
+	void *original_ptr1;	/*!< user's pointer to ptr1 */
+	void *original_ptr2;	/*!< user's pointer to ptr2 */
+	struct sah_Desc *original_next;	/*!< user's pointer to next */
+#endif
+} sah_Desc;
+
+#else
+
+typedef struct sah_Desc {
+	uint32_t header;	/*!< descriptor header value */
+	uint32_t len1;		/*!< number of data bytes in 'ptr1' buffer */
+	uint32_t hw_ptr1;	/*!< pointer to first sah_Link structure */
+	uint32_t len2;		/*!< number of data bytes in 'ptr2' buffer */
+	uint32_t hw_ptr2;	/*!< pointer to second sah_Link structure */
+	uint32_t hw_next;	/*!< pointer to next descriptor */
+	struct sah_Link *ptr1;	/*!< (virtual) pointer to first sah_Link structure */
+	struct sah_Link *ptr2;	/*!< (virtual) pointer to first sah_Link structure */
+	struct sah_Desc *next;	/*!< (virtual) pointer to next descriptor */
+#ifdef __KERNEL__		/* This needs a better test */
+	/* These two must be last.  See sah_Copy_Descriptors */
+	struct sah_Desc *virt_addr;	/*!< Virtual (kernel) address of this
+					   descriptor. */
+	dma_addr_t dma_addr;	/*!< Physical (bus) address of this
+				   descriptor.  */
+#endif
+} sah_Desc;
+
+#endif
+
+/*!
+*******************************************************************************
+* @brief The first descriptor in a chain
+******************************************************************************/
+typedef struct sah_Head_Desc {
+	sah_Desc desc;		/*!< whole struct - must be first */
+	struct fsl_shw_uco_t *user_info;	/*!< where result pool lives */
+	uint32_t user_ref;	/*!< at time of request */
+	uint32_t uco_flags;	/*!< at time of request */
+	uint32_t status;	/*!<  Status of queue entry */
+	uint32_t error_status;	/*!< If error, register from Sahara */
+	uint32_t fault_address;	/*!< If error, register from Sahara */
+	uint32_t op_status;	/*!< If error, register from Sahara */
+	fsl_shw_return_t result;	/*!< Result of running descriptor  */
+	struct sah_Head_Desc *next;	/*!< Next in queue  */
+	struct sah_Head_Desc *prev;	/*!< previous in queue  */
+	struct sah_Head_Desc *user_desc;	/*!< For API async get_results */
+	void *out1_ptr;		/*!< For async post-processing  */
+	void *out2_ptr;		/*!< For async post-processing  */
+	uint32_t out_len;	/*!< For async post-processing  */
+} sah_Head_Desc;
+
+/*!
+ * @brief Structure type for links
+ *
+ * The first three fields are used by hardware.
+ *****************************************************************************/
+#ifndef USE_NEW_PTRS
+
+typedef struct sah_Link {
+	size_t len;		/*!< len of 'data' buffer in bytes */
+	uint8_t *data;		/*!< buffer to store data */
+	struct sah_Link *next;	/*!< pointer to the next sah_Link storing
+				 * data */
+	sah_Link_Flags flags;	/*!< indicates the component that created the
+				 * data buffer. Security Function internal
+				 * information */
+	key_userid_t ownerid;	/*!< Auth code for established key */
+	uint32_t slot;		/*!< Location of the the established key */
+#ifdef __KERNEL__		/* This needs a better test */
+	/* These two elements must be last.  See sah_Copy_Links() */
+	struct sah_Link *virt_addr;
+	dma_addr_t dma_addr;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+	struct page *vm_info;
+#endif
+	uint8_t *original_data;	/*!< user's version of data pointer */
+	struct sah_Link *original_next;	/*!< user's version of next pointer */
+#ifdef SAH_COPY_DATA
+	uint8_t *copy_data;	/*!< Virtual address of acquired buffer */
+#endif
+#endif				/* kernel-only */
+} sah_Link;
+
+#else
+
+typedef struct sah_Link {
+	/*! len of 'data' buffer in bytes */
+	size_t len;
+	/*! buffer to store data */
+	uint32_t hw_data;
+	/*! Physical address */
+	uint32_t hw_next;
+	/*!
+	 * indicates the component that created the data buffer. Security Function
+	 * internal information
+	 */
+	sah_Link_Flags flags;
+	/*! (virtual) pointer to data */
+	uint8_t *data;
+	/*! (virtual) pointer to the next sah_Link storing data */
+	struct sah_Link *next;
+	/*! Auth code for established key */
+	key_userid_t ownerid;
+	/*! Location of the the established key */
+	uint32_t slot;
+#ifdef __KERNEL__		/* This needs a better test */
+	/* These two elements must be last.  See sah_Copy_Links() */
+	struct sah_Link *virt_addr;
+	dma_addr_t dma_addr;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+	struct page *vm_info;
+#endif
+#endif				/* kernel-only */
+} sah_Link;
+
+#endif
+
+/*!
+ * Initialization Object
+ */
+typedef struct fsl_sho_ibo_t {
+} fsl_sho_ibo_t;
+
+/* Imported from Sahara1 driver -- is it needed forever? */
+/*!
+*******************************************************************************
+* FIELDS
+*
+*   void * ref - parameter to be passed into the memory function calls
+*
+*   void * (*malloc)(void *ref, size_t n) - pointer to user's malloc function
+*
+*   void   (*free)(void *ref, void *ptr)  - pointer to user's free function
+*
+*   void * (*memcpy)(void *ref, void *dest, const void *src, size_t n) -
+*                                         pointer to user's memcpy function
+*
+*   void * (*memset)(void *ref, void *ptr, int ch, size_t n) - pointer to
+*                                         user's memset function
+*
+* @brief Structure for API memory utilities
+******************************************************************************/
+typedef struct sah_Mem_Util {
+	/*! Who knows.  Vestigial. */
+	void *mu_ref;
+	/*! Acquire buffer of size n bytes */
+	void *(*mu_malloc) (void *ref, size_t n);
+	/*! Acquire a sah_Head_Desc */
+	sah_Head_Desc *(*mu_alloc_head_desc) (void *ref);
+	/* Acquire a sah_Desc */
+	sah_Desc *(*mu_alloc_desc) (void *ref);
+	/* Acquire a sah_Link */
+	sah_Link *(*mu_alloc_link) (void *ref);
+	/*! Free buffer at ptr */
+	void (*mu_free) (void *ref, void *ptr);
+	/*! Free sah_Head_Desc at ptr */
+	void (*mu_free_head_desc) (void *ref, sah_Head_Desc * ptr);
+	/*! Free sah_Desc at ptr */
+	void (*mu_free_desc) (void *ref, sah_Desc * ptr);
+	/*! Free sah_Link at ptr */
+	void (*mu_free_link) (void *ref, sah_Link * ptr);
+	/*! Funciton which will copy n bytes from src to dest  */
+	void *(*mu_memcpy) (void *ref, void *dest, const void *src, size_t n);
+	/*! Set all n bytes of ptr to ch */
+	void *(*mu_memset) (void *ref, void *ptr, int ch, size_t n);
+} sah_Mem_Util;
+
+/*!
+ * Secure Partition information
+ *
+ * This holds the context to a single secure partition owned by the user.  It
+ * is only available in the kernel version of the User Context Object.
+ */
+typedef struct fsl_shw_spo_t {
+	uint32_t user_base;	/*!< Base address (user virtual) */
+	void *kernel_base;	/*!< Base address (kernel virtual) */
+	struct fsl_shw_spo_t *next;	/*!< Pointer to the next partition
+					   owned by the user.  NULL if this
+					   is the last partition. */
+} fsl_shw_spo_t;
+
+/* REQ-S2LRD-PINTFC-COA-UCO-001 */
+/*!
+ * User Context Object
+ */
+typedef struct fsl_shw_uco_t {
+	int sahara_openfd;	/*!< this should be kernel-only?? */
+	sah_Mem_Util *mem_util;	/*!< Memory utility fns  */
+	uint32_t user_ref;	/*!< User's reference */
+	void (*callback) (struct fsl_shw_uco_t * uco);	/*!< User's callback fn  */
+	uint32_t flags;		/*!< from fsl_shw_user_ctx_flags_t */
+	unsigned pool_size;	/*!< maximum size of user pool */
+#ifdef __KERNEL__
+	sah_Queue result_pool;	/*!< where non-blocking results go */
+	os_process_handle_t process;	/*!< remember for signalling User mode */
+	fsl_shw_spo_t *partition;	/*!< chain of secure partitions owned by
+					   the user */
+#else
+	struct fsl_shw_uco_t *next;	/*!< To allow user-mode chaining of contexts,
+					   for signalling.  */
+#endif
+} fsl_shw_uco_t;
+
+/* REQ-S2LRD-PINTFC-API-GEN-006  ??  */
+/*!
+ * Result object
+ */
+typedef struct fsl_shw_result_t {
+	uint32_t user_ref;
+	fsl_shw_return_t code;
+	uint32_t detail1;
+	uint32_t detail2;
+	sah_Head_Desc *user_desc;
+} fsl_shw_result_t;
+
+/*!
+ * Keystore Object
+ */
+typedef struct fsl_shw_kso_t {
+#ifdef __KERNEL__
+	os_lock_t lock;		/*!< Pointer to lock that controls access to
+				   the keystore. */
+#endif
+	void *user_data;	/*!< Pointer to user structure that handles
+				   the internals of the keystore. */
+	 fsl_shw_return_t(*data_init) (fsl_shw_uco_t * user_ctx,
+				       void **user_data);
+	void (*data_cleanup) (fsl_shw_uco_t * user_ctx, void **user_data);
+	 fsl_shw_return_t(*slot_verify_access) (void *user_data,
+						uint64_t owner_id,
+						uint32_t slot);
+	 fsl_shw_return_t(*slot_alloc) (void *user_data, uint32_t size_bytes,
+					uint64_t owner_id, uint32_t * slot);
+	 fsl_shw_return_t(*slot_dealloc) (void *user_data, uint64_t owner_id,
+					  uint32_t slot);
+	void *(*slot_get_address) (void *user_data, uint32_t slot);
+	 uint32_t(*slot_get_base) (void *user_data, uint32_t slot);
+	 uint32_t(*slot_get_offset) (void *user_data, uint32_t slot);
+	 uint32_t(*slot_get_slot_size) (void *user_data, uint32_t slot);
+} fsl_shw_kso_t;
+
+/* REQ-S2LRD-PINTFC-COA-SKO-001 */
+/*!
+ * Secret Key Context Object
+ */
+typedef struct fsl_shw_sko_t {
+	uint32_t flags;
+	fsl_shw_key_alg_t algorithm;
+	key_userid_t userid;
+	uint32_t handle;
+	uint16_t key_length;
+	uint8_t key[64];
+	struct fsl_shw_kso_t *keystore;	/*!< If present, key is in keystore */
+} fsl_shw_sko_t;
+
+/* REQ-S2LRD-PINTFC-COA-CO-001 */
+/*!
+ * @brief Platform Capability Object
+ */
+typedef struct fsl_shw_pco_t {	/* Consider turning these constants into symbols */
+	int api_major;
+	int api_minor;
+	int driver_major;
+	int driver_minor;
+	fsl_shw_key_alg_t sym_algorithms[4];
+	fsl_shw_sym_mode_t sym_modes[4];
+	fsl_shw_hash_alg_t hash_algorithms[4];
+	uint8_t sym_support[5][4];	/* indexed by key alg then mode */
+
+	int scc_driver_major;
+	int scc_driver_minor;
+	int scm_version;	/*!< Version from SCM Configuration register */
+	int smn_version;	/*!< Version from SMN Status register */
+	int block_size_bytes;	/*!< Number of bytes per block of RAM; also
+				   block size of the crypto algorithm. */
+	union {
+		struct {
+			int black_ram_size_blocks;	/*!< Number of blocks of Black RAM */
+			int red_ram_size_blocks;	/*!< Number of blocks of Red RAM */
+		} scc_info;
+		struct {
+			int partition_size_bytes;	/*!< Number of bytes in each partition */
+			int partition_count;	/*!< Number of partitions on this platform */
+		} scc2_info;
+	};
+} fsl_shw_pco_t;
+
+/* REQ-S2LRD-PINTFC-COA-HCO-001 */
+/*!
+ * Hash Context Object
+ */
+typedef struct fsl_shw_hco_t {	/* fsl_shw_hash_context_object */
+	fsl_shw_hash_alg_t algorithm;
+	uint32_t flags;
+	uint8_t digest_length;	/* in bytes */
+	uint8_t context_length;	/* in bytes */
+	uint8_t context_register_length;	/* in bytes */
+	uint32_t context[9];	/* largest digest + msg size */
+} fsl_shw_hco_t;
+
+/*!
+ * HMAC Context Object
+ */
+typedef struct fsl_shw_hmco_t {	/* fsl_shw_hmac_context_object */
+	fsl_shw_hash_alg_t algorithm;
+	uint32_t flags;
+	uint8_t digest_length;	/*!< in bytes */
+	uint8_t context_length;	/*!< in bytes */
+	uint8_t context_register_length;	/*!< in bytes */
+	uint32_t ongoing_context[9];	/*!< largest digest + msg
+					   size */
+	uint32_t inner_precompute[9];	/*!< largest digest + msg
+					   size */
+	uint32_t outer_precompute[9];	/*!< largest digest + msg
+					   size */
+} fsl_shw_hmco_t;
+
+/* REQ-S2LRD-PINTFC-COA-SCCO-001 */
+/*!
+ * Symmetric Crypto Context Object Context Object
+ */
+typedef struct fsl_shw_scco_t {
+	uint32_t flags;
+	unsigned block_size_bytes;	/* double duty block&ctx size */
+	fsl_shw_sym_mode_t mode;
+	/* Could put modulus plus 16-octet context in union with arc4
+	   sbox+ptrs... */
+	fsl_shw_ctr_mod_t modulus_exp;
+	uint8_t context[259];
+} fsl_shw_scco_t;
+
+/*!
+ * Authenticate-Cipher Context Object
+
+ * An object for controlling the function of, and holding information about,
+ * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and
+ * #fsl_shw_auth_decrypt().
+ */
+typedef struct fsl_shw_acco_t {
+	uint32_t flags;		/*!< See #fsl_shw_auth_ctx_flags_t for
+				   meanings */
+	fsl_shw_acc_mode_t mode;	/*!< CCM only */
+	uint8_t mac_length;	/*!< User's value for length  */
+	unsigned q_length;	/*!< NIST parameter - */
+	fsl_shw_scco_t cipher_ctx_info;	/*!< For running
+					   encrypt/decrypt. */
+	union {
+		fsl_shw_scco_t CCM_ctx_info;	/*!< For running the CBC in
+						   AES-CCM.  */
+		fsl_shw_hco_t hash_ctx_info;	/*!< For running the hash */
+	} auth_info;		/*!< "auth" info struct  */
+	uint8_t unencrypted_mac[16];	/*!< max block size... */
+} fsl_shw_acco_t;
+
+/*!
+ *  Used by Sahara API to retrieve completed non-blocking results.
+ */
+typedef struct sah_results {
+	unsigned requested;	/*!< number of results requested */
+	unsigned *actual;	/*!< number of results obtained */
+	fsl_shw_result_t *results;	/*!< pointer to memory to hold results */
+} sah_results;
+
+/*!
+ * @typedef scc_partition_status_t
+ */
+/*! Partition status information. */
+typedef enum fsl_shw_partition_status_t {
+	FSL_PART_S_UNUSABLE,	/*!< Partition not implemented */
+	FSL_PART_S_UNAVAILABLE,	/*!< Partition owned by other host */
+	FSL_PART_S_AVAILABLE,	/*!< Partition available */
+	FSL_PART_S_ALLOCATED,	/*!< Partition owned by host but not engaged
+				 */
+	FSL_PART_S_ENGAGED,	/*!< Partition owned by host and engaged */
+} fsl_shw_partition_status_t;
+
+/******************************************************************************
+ * Access Macros for Objects
+ *****************************************************************************/
+/*!
+ * Get FSL SHW API version
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the API is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the API is to be stored.
+ */
+#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor)                   \
+{                                                                             \
+    *(pcmajor) = (pcobject)->api_major;                                       \
+    *(pcminor) = (pcobject)->api_minor;                                       \
+}
+
+/*!
+ * Get underlying driver version.
+ *
+ * @param      pcobject  The Platform Capababilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the driver is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the driver is to be stored.
+ */
+#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor)            \
+{                                                                             \
+    *(pcmajor) = (pcobject)->driver_major;                                    \
+    *(pcminor) = (pcobject)->driver_minor;                                    \
+}
+
+/*!
+ * Get list of symmetric algorithms supported.
+ *
+ * @param pcobject           The Platform Capababilities Object to query.
+ * @param[out] pcalgorithms  A pointer to where to store the location of
+ *                           the list of algorithms.
+ * @param[out] pcacount      A pointer to where to store the number of
+ *                           algorithms in the list at @a algorithms.
+ */
+#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount)      \
+{                                                                             \
+    *(pcalgorithms) = (pcobject)->sym_algorithms;                             \
+    *(pcacount) = sizeof((pcobject)->sym_algorithms)/4;                       \
+}
+
+/*!
+ * Get list of symmetric modes supported.
+ *
+ * @param pcobject        The Platform Capababilities Object to query.
+ * @param[out] gsmodes    A pointer to where to store the location of
+ *                        the list of modes.
+ * @param[out] gsacount   A pointer to where to store the number of
+ *                        algorithms in the list at @a modes.
+ */
+#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount)                \
+{                                                                             \
+    *(gsmodes) = (pcobject)->sym_modes;                                       \
+    *(gsacount) = sizeof((pcobject)->sym_modes)/4;                            \
+}
+
+/*!
+ * Get list of hash algorithms supported.
+ *
+ * @param pcobject           The Platform Capababilities Object to query.
+ * @param[out] gsalgorithms  A pointer which will be set to the list of
+ *                           algorithms.
+ * @param[out] gsacount      The number of algorithms in the list at @a
+ *                           algorithms.
+ */
+#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount)     \
+{                                                                             \
+    *(gsalgorithms) = (pcobject)->hash_algorithms;                            \
+    *(gsacount) = sizeof((pcobject)->hash_algorithms)/4;                      \
+}
+
+/*!
+ * Determine whether the combination of a given symmetric algorithm and a given
+ * mode is supported.
+ *
+ * @param pcobject   The Platform Capababilities Object to query.
+ * @param pcalg      A Symmetric Cipher algorithm.
+ * @param pcmode     A Symmetric Cipher mode.
+ *
+ * @return 0 if combination is not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode)              \
+    ((pcobject)->sym_support[pcalg][pcmode])
+
+/*!
+ * Determine whether a given Encryption-Authentication mode is supported.
+ *
+ * @param pcobject  The Platform Capababilities Object to query.
+ * @param pcmode    The Authentication mode.
+ *
+ * @return 0 if mode is not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_auth_supported(pcobject, pcmode)                    \
+    ((pcmode == FSL_ACC_MODE_CCM) ? 1 : 0)
+
+/*!
+ * Determine whether Black Keys (key establishment / wrapping) is supported.
+ *
+ * @param pcobject  The Platform Capababilities Object to query.
+ *
+ * @return 0 if wrapping is not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_black_key_supported(pcobject)                     \
+    1
+
+/*!
+ * Determine whether Programmed Key features are available
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return  1 if Programmed Key features are available, otherwise zero.
+ */
+#define fsl_shw_pco_check_pk_supported(pcobject)        \
+    0
+
+/*!
+ * Determine whether Software Key features are available
+ *
+ * @param pc_info          The Platform Capabilities Object to query.
+ *
+ * @return  1 if Software key features are available, otherwise zero.
+ */
+#define fsl_shw_pco_check_sw_keys_supported(pcobject)        \
+    0
+
+/*!
+ * Get FSL SHW SCC driver version
+ *
+ * @param      pcobject  The Platform Capabilities Object to query.
+ * @param[out] pcmajor   A pointer to where the major version
+ *                       of the SCC driver is to be stored.
+ * @param[out] pcminor   A pointer to where the minor version
+ *                       of the SCC driver is to be stored.
+ */
+#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor)        \
+{                                                                             \
+    *(pcmajor) = (pcobject)->scc_driver_major;                                \
+    *(pcminor) = (pcobject)->scc_driver_minor;                                \
+}
+
+/*!
+ * Get SCM hardware version
+ *
+ * @param      pcobject  The Platform Capabilities Object to query.
+ * @return               The SCM hardware version
+ */
+#define fsl_shw_pco_get_scm_version(pcobject)                                 \
+    ((pcobject)->scm_version)
+
+/*!
+ * Get SMN hardware version
+ *
+ * @param      pcobject  The Platform Capabilities Object to query.
+ * @return               The SMN hardware version
+ */
+#define fsl_shw_pco_get_smn_version(pcobject)                                 \
+    ((pcobject)->smn_version)
+
+/*!
+ * Get the size of an SCM block, in bytes
+ *
+ * @param      pcobject  The Platform Capabilities Object to query.
+ * @return               The size of an SCM block, in bytes.
+ */
+#define fsl_shw_pco_get_scm_block_size(pcobject)                              \
+    ((pcobject)->block_size_bytes)
+
+/*!
+ * Get size of Black and Red RAM memory
+ *
+ * @param      pcobject    The Platform Capabilities Object to query.
+ * @param[out] black_size  A pointer to where the size of the Black RAM, in
+ *                         blocks, is to be placed.
+ * @param[out] red_size    A pointer to where the size of the Red RAM, in
+ *                         blocks, is to be placed.
+ */
+#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size)              \
+{                                                                             \
+    if ((pcobject)->scm_version == 1) {                                       \
+        *(black_size) = (pcobject)->scc_info.black_ram_size_blocks;           \
+        *(red_size)   = (pcobject)->scc_info.red_ram_size_blocks;             \
+    } else {                                                                  \
+        *(black_size) = 0;                                                    \
+        *(red_size)   = 0;                                                    \
+    }                                                                         \
+}
+
+/*!
+ * Determine whether Secure Partitions are supported
+ *
+ * @param pcobject   The Platform Capabilities Object to query.
+ *
+ * @return 0 if secure partitions are not supported, non-zero if supported.
+ */
+#define fsl_shw_pco_check_spo_supported(pcobject)                           \
+    ((pcobject)->scm_version == 2)
+
+/*!
+ * Get the size of a Secure Partitions
+ *
+ * @param pcobject   The Platform Capabilities Object to query.
+ *
+ * @return Partition size, in bytes.  0 if Secure Partitions not supported.
+ */
+#define fsl_shw_pco_get_spo_size_bytes(pcobject)                            \
+    (((pcobject)->scm_version == 2) ?                                       \
+        ((pcobject)->scc2_info.partition_size_bytes) : 0 )
+
+/*!
+ * Get the number of Secure Partitions on this platform
+ *
+ * @param pcobject   The Platform Capabilities Object to query.
+ *
+ * @return Number of partitions. 0 if Secure Paritions not supported.  Note
+ *         that this returns the total number of partitions, not all may be
+ *         available to the user.
+ */
+#define fsl_shw_pco_get_spo_count(pcobject)                                 \
+    (((pcobject)->scm_version == 2) ?                                       \
+        ((pcobject)->scc2_info.partition_count) : 0 )
+
+/*!
+ * Initialize a User Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the User Context Object to initial values, and set the size
+ * of the results pool.  The mode will be set to a default of
+ * #FSL_UCO_BLOCKING_MODE.
+ *
+ * When using non-blocking operations, this sets the maximum number of
+ * operations which can be outstanding.  This number includes the counts of
+ * operations waiting to start, operation(s) being performed, and results which
+ * have not been retrieved.
+ *
+ * Changes to this value are ignored once user registration has completed.  It
+ * should be set to 1 if only blocking operations will ever be performed.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param usize        The maximum number of operations which can be
+ *                     outstanding.
+ */
+#ifdef __KERNEL__
+#define fsl_shw_uco_init(ucontext, usize)                                     \
+{                                                                             \
+      (ucontext)->pool_size = usize;                                          \
+      (ucontext)->flags = FSL_UCO_BLOCKING_MODE;                              \
+      (ucontext)->sahara_openfd = -1;                                         \
+      (ucontext)->mem_util = NULL;                                            \
+      (ucontext)->partition = NULL;                                           \
+      (ucontext)->callback = NULL;                                            \
+}
+#else
+#define fsl_shw_uco_init(ucontext, usize)                                     \
+{                                                                             \
+      (ucontext)->pool_size = usize;                                          \
+      (ucontext)->flags = FSL_UCO_BLOCKING_MODE;                              \
+      (ucontext)->sahara_openfd = -1;                                         \
+      (ucontext)->mem_util = NULL;                                            \
+      (ucontext)->callback = NULL;                                            \
+}
+#endif
+
+/*!
+ * Set the User Reference for the User Context.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uref         A value which will be passed back with a result.
+ */
+#define fsl_shw_uco_set_reference(ucontext, uref)                             \
+      (ucontext)->user_ref = uref
+
+/*!
+ * Set the User Reference for the User Context.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param ucallback    The function the API will invoke when an operation
+ *                     completes.
+ */
+#define fsl_shw_uco_set_callback(ucontext, ucallback)                         \
+      (ucontext)->callback = ucallback
+
+/*!
+ * Set flags in the User Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uflags       ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+#define fsl_shw_uco_set_flags(ucontext, uflags)                               \
+      (ucontext)->flags |= (uflags)
+
+/*!
+ * Clear flags in the User Context.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param ucontext     The User Context object to operate on.
+ * @param uflags       ORed values from #fsl_shw_user_ctx_flags_t.
+ */
+#define fsl_shw_uco_clear_flags(ucontext, uflags)                             \
+      (ucontext)->flags &= ~(uflags)
+
+/*!
+ * Retrieve the reference value from a Result Object.
+ *
+ * @param robject  The result object to query.
+ *
+ * @return The reference associated with the request.
+ */
+#define fsl_shw_ro_get_reference(robject)                                    \
+       (robject)->user_ref
+
+/*!
+ * Retrieve the status code from a Result Object.
+ *
+ * @param robject  The result object to query.
+ *
+ * @return The status of the request.
+ */
+#define fsl_shw_ro_get_status(robject)                                       \
+       (robject)->code
+
+/*!
+ * Initialize a Secret Key Object.
+ *
+ * This function must be called before performing any other operation with
+ * the Object.
+ *
+ * @param skobject     The Secret Key Object to be initialized.
+ * @param skalgorithm  DES, AES, etc.
+ *
+ */
+#define fsl_shw_sko_init(skobject,skalgorithm)                               \
+{                                                                            \
+       (skobject)->algorithm = skalgorithm;                                  \
+       (skobject)->flags = 0;                                                \
+       (skobject)->keystore = NULL;                                          \
+}
+
+/*!
+ * Initialize a Secret Key Object to use a Platform Key register.
+ *
+ * This function must be called before performing any other operation with
+ * the Object.  INVALID on this platform.
+ *
+ * @param skobject     The Secret Key Object to be initialized.
+ * @param skalgorithm  DES, AES, etc.
+ * @param skhwkey      one of the fsl_shw_pf_key_t values.
+ *
+ */
+#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey)       \
+{                                                                   \
+    (skobject)->algorithm = -1;                                         \
+    (skobject)->flags = -1;                                             \
+    (skobject)->keystore = NULL;                                        \
+}
+
+/*!
+ * Store a cleartext key in the key object.
+ *
+ * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and
+ * resetting the #FSL_SKO_KEY_ESTABLISHED flag.
+ *
+ * @param skobject     A variable of type #fsl_shw_sko_t.
+ * @param skkey        A pointer to the beginning of the key.
+ * @param skkeylen     The length, in octets, of the key.  The value should be
+ *                     appropriate to the key size supported by the algorithm.
+ *                     64 octets is the absolute maximum value allowed for this
+ *                     call.
+ */
+#define fsl_shw_sko_set_key(skobject, skkey, skkeylen)                       \
+{                                                                            \
+       (skobject)->key_length = skkeylen;                                    \
+       copy_bytes((skobject)->key, skkey, skkeylen);                         \
+       (skobject)->flags |= FSL_SKO_KEY_PRESENT;                             \
+       (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED;                        \
+}
+
+/*!
+ * Set a size for the key.
+ *
+ * This function would normally be used when the user wants the key to be
+ * generated from a random source.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skkeylen   The length, in octets, of the key.  The value should be
+ *                   appropriate to the key size supported by the algorithm.
+ *                   64 octets is the absolute maximum value allowed for this
+ *                   call.
+ */
+#define fsl_shw_sko_set_key_length(skobject, skkeylen)                       \
+       (skobject)->key_length = skkeylen;
+
+/*!
+ * Set the User ID associated with the key.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skuserid   The User ID to identify authorized users of the key.
+ */
+#define fsl_shw_sko_set_user_id(skobject, skuserid)                           \
+       (skobject)->userid = (skuserid)
+
+/*!
+ * Establish a user Keystore to hold the key.
+ */
+#define fsl_shw_sko_set_keystore(skobject, user_keystore)                     \
+       (skobject)->keystore = (user_keystore)
+
+/*!
+ * Set the establish key handle into a key object.
+ *
+ * The @a userid field will be used to validate the access to the unwrapped
+ * key.  This feature is not available for all platforms, nor for all
+ * algorithms and modes.
+ *
+ * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag
+ * will be cleared).
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skuserid   The User ID to verify this user is an authorized user of
+ *                   the key.
+ * @param skhandle   A @a handle from #fsl_shw_sko_get_established_info.
+ */
+#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle)        \
+{                                                                             \
+       (skobject)->userid = (skuserid);                                       \
+       (skobject)->handle = (skhandle);                                       \
+       (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED;                          \
+       (skobject)->flags &=                                                   \
+                       ~(FSL_SKO_KEY_PRESENT);   \
+}
+
+/*!
+ * Retrieve the established-key handle from a key object.
+ *
+ * @param skobject   A variable of type #fsl_shw_sko_t.
+ * @param skhandle   The location to store the @a handle of the unwrapped
+ *                   key.
+ */
+#define fsl_shw_sko_get_established_info(skobject, skhandle)                  \
+       *(skhandle) = (skobject)->handle
+
+/*!
+ * Extract the algorithm from a key object.
+ *
+ * @param      skobject     The Key Object to be queried.
+ * @param[out] skalgorithm  A pointer to the location to store the algorithm.
+ */
+#define fsl_shw_sko_get_algorithm(skobject, skalgorithm)                      \
+       *(skalgorithm) = (skobject)->algorithm
+
+/*!
+ * Retrieve the cleartext key from a key object that is stored in a user
+ * keystore.
+ *
+ * @param      skobject     The Key Object to be queried.
+ * @param[out] skkey        A pointer to the location to store the key.  NULL
+ *                          if the key is not stored in a user keystore.
+ */
+#define fsl_shw_sko_get_key(skobject, skkey)                                  \
+{                                                                             \
+    fsl_shw_kso_t* keystore = (skobject)->keystore;                           \
+    if (keystore != NULL) {                                                   \
+        *(skkey) = keystore->slot_get_address(keystore->user_data,            \
+                                              (skobject)->handle);            \
+    } else {                                                                  \
+        *(skkey) = NULL;                                                      \
+    }                                                                         \
+}
+
+/*!
+ * Determine the size of a wrapped key based upon the cleartext key's length.
+ *
+ * This function can be used to calculate the number of octets that
+ * #fsl_shw_extract_key() will write into the location at @a covered_key.
+ *
+ * If zero is returned at @a length, this means that the key length in
+ * @a key_info is not supported.
+ *
+ * @param      wkeyinfo         Information about a key to be wrapped.
+ * @param      wkeylen          Location to store the length of a wrapped
+ *                              version of the key in @a key_info.
+ */
+#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen)           \
+{                                                                       \
+    register fsl_shw_sko_t* kp = wkeyinfo;                              \
+    register uint32_t kl = kp->key_length;                              \
+    int key_blocks = (kl + 15) / 16;                                    \
+    int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */              \
+                                                                        \
+    *(wkeylen) = base_size + 16 * key_blocks;                           \
+}
+
+/*!
+ * Set some flags in the key object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param skobject     A variable of type #fsl_shw_sko_t.
+ * @param skflags      (One or more) ORed members of #fsl_shw_key_flags_t which
+ *                     are to be set.
+ */
+#define fsl_shw_sko_set_flags(skobject, skflags)                              \
+      (skobject)->flags |= (skflags)
+
+/*!
+ * Clear some flags in the key object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param skobject      A variable of type #fsl_shw_sko_t.
+ * @param skflags       (One or more) ORed members of #fsl_shw_key_flags_t
+ *                      which are to be reset.
+ */
+#define fsl_shw_sko_clear_flags(skobject, skflags)                            \
+      (skobject)->flags &= ~(skflags)
+
+/*!
+ * Initialize a Hash Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the hash
+ * context object.
+ *
+ * @param      hcobject    The hash context to operate upon.
+ * @param      hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                         #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+#define fsl_shw_hco_init(hcobject, hcalgorithm)                               \
+{                                                                             \
+     (hcobject)->algorithm = hcalgorithm;                                     \
+     (hcobject)->flags = 0;                                                   \
+     switch (hcalgorithm) {                                                   \
+     case FSL_HASH_ALG_MD5:                                                   \
+         (hcobject)->digest_length = 16;                                      \
+         (hcobject)->context_length = 16;                                     \
+         (hcobject)->context_register_length = 24;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA1:                                                  \
+         (hcobject)->digest_length = 20;                                      \
+         (hcobject)->context_length = 20;                                     \
+         (hcobject)->context_register_length = 24;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA224:                                                \
+         (hcobject)->digest_length = 28;                                      \
+         (hcobject)->context_length = 32;                                     \
+         (hcobject)->context_register_length = 36;                            \
+         break;                                                               \
+     case FSL_HASH_ALG_SHA256:                                                \
+         (hcobject)->digest_length = 32;                                      \
+         (hcobject)->context_length = 32;                                     \
+         (hcobject)->context_register_length = 36;                            \
+         break;                                                               \
+     default:                                                                 \
+         /* error ! */                                                        \
+         (hcobject)->digest_length = 1;                                       \
+         (hcobject)->context_length = 1;                                      \
+         (hcobject)->context_register_length = 1;                             \
+         break;                                                               \
+     }                                                                        \
+}
+
+/*!
+ * Get the current hash value and message length from the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hcobject   The hash context to query.
+ * @param[out] hccontext  Pointer to the location of @a length octets where to
+ *                        store a copy of the current value of the digest.
+ * @param      hcclength  Number of octets of hash value to copy.
+ * @param[out] hcmsglen   Pointer to the location to store the number of octets
+ *                        already hashed.
+ */
+#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen)      \
+{                                                                             \
+     copy_bytes(hccontext, (hcobject)->context, hcclength);                   \
+         if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224                     \
+             || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) {               \
+             *(hcmsglen) = (hcobject)->context[8];                            \
+         } else {                                                             \
+             *(hcmsglen) = (hcobject)->context[5];                            \
+         }                                                                    \
+}
+
+/*!
+ * Get the hash algorithm from the hash context object.
+ *
+ * @param      hcobject    The hash context to query.
+ * @param[out] hcalgorithm Pointer to where the algorithm is to be stored.
+ */
+#define fsl_shw_hco_get_info(hcobject, hcalgorithm)                           \
+{                                                                             \
+     *(hcalgorithm) = (hcobject)->algorithm;                                  \
+}
+
+/*!
+ * Set the current hash value and message length in the hash context object.
+ *
+ * The algorithm must have already been specified.  See #fsl_shw_hco_init().
+ *
+ * @param      hcobject  The hash context to operate upon.
+ * @param      hccontext Pointer to buffer of appropriate length to copy into
+ *                       the hash context object.
+ * @param      hcmsglen  The number of octets of the message which have
+ *                        already been hashed.
+ *
+ */
+#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen)                 \
+{                                                                             \
+     copy_bytes((hcobject)->context, hccontext, (hcobject)->context_length);  \
+     if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224)                       \
+         || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) {                 \
+         (hcobject)->context[8] = hcmsglen;                                   \
+     } else {                                                                 \
+         (hcobject)->context[5] = hcmsglen;                                   \
+     }                                                                        \
+}
+
+/*!
+ * Set flags in a Hash Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The hash context to be operated on.
+ * @param hcflags    The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+#define fsl_shw_hco_set_flags(hcobject, hcflags)                              \
+      (hcobject)->flags |= (hcflags)
+
+/*!
+ * Clear flags in a Hash Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The hash context to be operated on.
+ * @param hcflags    The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hash_ctx_flags_t.
+ */
+#define fsl_shw_hco_clear_flags(hcobject, hcflags)                            \
+      (hcobject)->flags &= ~(hcflags)
+
+/*!
+ * Initialize an HMAC Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  It sets the current message length and hash algorithm in the HMAC
+ * context object.
+ *
+ * @param      hcobject    The HMAC context to operate upon.
+ * @param      hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5,
+ *                         #FSL_HASH_ALG_SHA256, etc).
+ *
+ */
+#define fsl_shw_hmco_init(hcobject, hcalgorithm)                              \
+    fsl_shw_hco_init(hcobject, hcalgorithm)
+
+/*!
+ * Set flags in an HMAC Context Object.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The HMAC context to be operated on.
+ * @param hcflags    The flags to be set in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+#define fsl_shw_hmco_set_flags(hcobject, hcflags)                             \
+      (hcobject)->flags |= (hcflags)
+
+/*!
+ * Clear flags in an HMAC Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param hcobject   The HMAC context to be operated on.
+ * @param hcflags    The flags to be reset in the context.  These can be ORed
+ *                   members of #fsl_shw_hmac_ctx_flags_t.
+ */
+#define fsl_shw_hmco_clear_flags(hcobject, hcflags)                           \
+      (hcobject)->flags &= ~(hcflags)
+
+/*!
+ * Initialize a Symmetric Cipher Context Object.
+ *
+ * This function must be called before performing any other operation with the
+ * Object.  This will set the @a mode and @a algorithm and initialize the
+ * Object.
+ *
+ * @param scobject  The context object to operate on.
+ * @param scalg     The cipher algorithm this context will be used with.
+ * @param scmode    #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc.
+ *
+ */
+#define fsl_shw_scco_init(scobject, scalg, scmode)                            \
+{                                                                             \
+      register uint32_t bsb;   /* block-size bytes */                         \
+                                                                              \
+      switch (scalg) {                                                        \
+      case FSL_KEY_ALG_AES:                                                   \
+          bsb = 16;                                                           \
+          break;                                                              \
+      case FSL_KEY_ALG_DES:                                                   \
+          /* fall through */                                                  \
+      case FSL_KEY_ALG_TDES:                                                  \
+          bsb = 8;                                                            \
+          break;                                                              \
+      case FSL_KEY_ALG_ARC4:                                                  \
+          bsb = 259;                                                          \
+          break;                                                              \
+      case FSL_KEY_ALG_HMAC:                                                  \
+          bsb = 1;  /* meaningless */                                         \
+          break;                                                              \
+      default:                                                                \
+          bsb = 00;                                                           \
+      }                                                                       \
+      (scobject)->block_size_bytes = bsb;                                     \
+      (scobject)->mode = scmode;                                              \
+      (scobject)->flags = 0;                                                  \
+}
+
+/*!
+ * Set the flags for a Symmetric Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param scobject The context object to operate on.
+ * @param scflags  The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_scco_set_flags(scobject, scflags)                             \
+       (scobject)->flags |= (scflags)
+
+/*!
+ * Clear some flags in a Symmetric Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param scobject The context object to operate on.
+ * @param scflags  The flags to reset (one or more values from
+ *                 #fsl_shw_sym_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_scco_clear_flags(scobject, scflags)                           \
+       (scobject)->flags &= ~(scflags)
+
+/*!
+ * Set the Context (IV) for a Symmetric Cipher Context.
+ *
+ * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the
+ * context (the S-Box and pointers) for ARC4.  The full context size will
+ * be copied.
+ *
+ * @param scobject  The context object to operate on.
+ * @param sccontext A pointer to the buffer which contains the context.
+ *
+ */
+#define fsl_shw_scco_set_context(scobject, sccontext)                         \
+       copy_bytes((scobject)->context, sccontext,                             \
+                  (scobject)->block_size_bytes)
+
+/*!
+ * Get the Context for a Symmetric Cipher Context.
+ *
+ * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to
+ * retrieve context (the S-Box and pointers) for ARC4.  The full context
+ * will be copied.
+ *
+ * @param      scobject  The context object to operate on.
+ * @param[out] sccontext Pointer to location where context will be stored.
+ */
+#define fsl_shw_scco_get_context(scobject, sccontext)                         \
+       copy_bytes(sccontext, (scobject)->context, (scobject)->block_size_bytes)
+
+/*!
+ * Set the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will set the Counter Value for CTR mode.
+ *
+ * @param scobject  The context object to operate on.
+ * @param sccounter The starting counter value.  The number of octets.
+ *                  copied will be the block size for the algorithm.
+ * @param scmodulus The modulus for controlling the incrementing of the
+ *                  counter.
+ *
+ */
+#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus)        \
+       {                                                                     \
+           if ((sccounter) != NULL) {                                        \
+               copy_bytes((scobject)->context, sccounter,                    \
+                          (scobject)->block_size_bytes);                     \
+           }                                                                 \
+           (scobject)->modulus_exp = scmodulus;                              \
+       }
+
+/*!
+ * Get the Counter Value for a Symmetric Cipher Context.
+ *
+ * This will retrieve the Counter Value is for CTR mode.
+ *
+ * @param     scobject    The context object to query.
+ * @param[out] sccounter  Pointer to location to store the current counter
+ *                        value.  The number of octets copied will be the
+ *                        block size for the algorithm.
+ * @param[out] scmodulus  Pointer to location to store the modulus.
+ *
+ */
+#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus)        \
+       {                                                                     \
+           if ((sccounter) != NULL) {                                        \
+               copy_bytes(sccounter, (scobject)->context,                    \
+                          (scobject)->block_size_bytes);                     \
+           }                                                                 \
+           if ((scmodulus) != NULL) {                                        \
+               *(scmodulus) = (scobject)->modulus_exp;                       \
+           }                                                                 \
+       }
+
+/*!
+ * Initialize a Authentication-Cipher Context.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acmode    The mode for this object (only #FSL_ACC_MODE_CCM
+ *                  supported).
+ */
+#define fsl_shw_acco_init(acobject, acmode)                                   \
+   {                                                                          \
+       (acobject)->flags = 0;                                                 \
+       (acobject)->mode = (acmode);                                           \
+   }
+
+/*!
+ * Set the flags for a Authentication-Cipher Context.
+ *
+ * Turns on the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acflags   The flags to set (one or more from
+ *                  #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_acco_set_flags(acobject, acflags)                             \
+       (acobject)->flags |= (acflags)
+
+/*!
+ * Clear some flags in a Authentication-Cipher Context Object.
+ *
+ * Turns off the flags specified in @a flags.  Other flags are untouched.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acflags   The flags to reset (one or more from
+ *                  #fsl_shw_auth_ctx_flags_t ORed together).
+ *
+ */
+#define fsl_shw_acco_clear_flags(acobject, acflags)                           \
+       (acobject)->flags &= ~(acflags)
+
+/*!
+ * Set up the Authentication-Cipher Object for CCM mode.
+ *
+ * This will set the @a auth_object for CCM mode and save the @a ctr,
+ * and @a mac_length.  This function can be called instead of
+ * #fsl_shw_acco_init().
+ *
+ * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the
+ * MAC.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acalg     Cipher algorithm.  Only AES is supported.
+ * @param accounter The initial counter value.
+ * @param acmaclen  The number of octets used for the MAC.  Valid values are
+ *                  4, 6, 8, 10, 12, 14, and 16.
+ */
+/* Do we need to stash the +1 value of the CTR somewhere? */
+#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen)            \
+{                                                                             \
+      (acobject)->flags = 0;                                                  \
+      (acobject)->mode = FSL_ACC_MODE_CCM;                                    \
+      (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16;               \
+      (acobject)->cipher_ctx_info.block_size_bytes = 16;                      \
+      (acobject)->mac_length = acmaclen;                                      \
+      fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter,  \
+            FSL_CTR_MOD_128);                                                 \
+}
+
+/*!
+ * Format the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will also set the IV and CTR values per Appendix A of NIST
+ * Special Publication 800-38C (May 2004).  It will also perform the
+ * #fsl_shw_acco_set_ccm() operation with information derived from this set of
+ * parameters.
+ *
+ * Note this function assumes the algorithm is AES.  It initializes the
+ * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the
+ * flags to be #FSL_ACCO_NIST_CCM.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param act       The number of octets used for the MAC.  Valid values are
+ *                  4, 6, 8, 10, 12, 14, and 16.
+ * @param acad      Number of octets of Associated Data (may be zero).
+ * @param acq       A value for the size of the length of @a q field.  Valid
+ *                  values are 1-8.
+ * @param acN       The Nonce (packet number or other changing value). Must
+ *                  be (15 - @a q_length) octets long.
+ * @param acQ       The value of Q (size of the payload in octets).
+ *
+ */
+/* Do we need to stash the +1 value of the CTR somewhere? */
+#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\
+    {                                                                         \
+        uint64_t Q = acQ;                                                     \
+        uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1);     \
+        unsigned i;                                                           \
+        uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15;      \
+        (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16;             \
+        (acobject)->cipher_ctx_info.block_size_bytes = 16;                    \
+        (acobject)->mode = FSL_ACC_MODE_CCM;                                  \
+        (acobject)->flags  = FSL_ACCO_NIST_CCM;                               \
+                                                                              \
+        /* Store away the MAC length (after calculating actual value */       \
+        (acobject)->mac_length = (act);                                       \
+        /* Set Flag field in Block 0 */                                       \
+        *((acobject)->auth_info.CCM_ctx_info.context) = bflag;                \
+        /* Set Nonce field in Block 0 */                                      \
+        copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN,         \
+                   15-(acq));                                                 \
+        /* Set Flag field in ctr */                                           \
+        *((acobject)->cipher_ctx_info.context) = (acq)-1;                     \
+        /* Update the Q (payload length) field of Block0 */                   \
+        (acobject)->q_length = acq;                                           \
+        for (i = 0; i < (acq); i++) {                                         \
+            *qptr-- = Q & 0xFF;                                               \
+            Q >>= 8;                                                          \
+        }                                                                     \
+        /* Set the Nonce field of the ctr */                                  \
+        copy_bytes((acobject)->cipher_ctx_info.context+1, acN, 15-(acq));     \
+        /* Clear the block counter field of the ctr */                        \
+        memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1);     \
+     }
+
+/*!
+ * Update the First Block (IV) & Initial Counter Value per NIST CCM.
+ *
+ * This function will set the IV and CTR values per Appendix A of NIST Special
+ * Publication 800-38C (May 2004).
+ *
+ * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has
+ * previously been called on the @a auth_object.
+ *
+ * @param acobject  Pointer to object to operate on.
+ * @param acN       The Nonce (packet number or other changing value). Must
+ *                  be (15 - @a q_length) octets long.
+ * @param acQ       The value of Q (size of the payload in octets).
+ *
+ */
+/* Do we need to stash the +1 value of the CTR somewhere? */
+#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ)                \
+     {                                                                        \
+        uint64_t Q = acQ;                                                     \
+        unsigned i;                                                           \
+        uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15;      \
+                                                                              \
+        /* Update the Nonce field field of Block0 */                          \
+        copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN,         \
+               15 - (acobject)->q_length);                                    \
+        /* Update the Q (payload length) field of Block0 */                   \
+        for (i = 0; i < (acobject)->q_length; i++) {                          \
+            *qptr-- = Q & 0xFF;                                               \
+            Q >>= 8;                                                          \
+        }                                                                     \
+        /* Update the Nonce field of the ctr */                               \
+        copy_bytes((acobject)->cipher_ctx_info.context+1, acN,                \
+               15 - (acobject)->q_length);                                    \
+     }
+
+/******************************************************************************
+ * Library functions
+ *****************************************************************************/
+/* REQ-S2LRD-PINTFC-API-GEN-003 */
+extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-004 */
+extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-005 */
+extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx);
+
+/* REQ-S2LRD-PINTFC-API-GEN-006 */
+extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx,
+					    unsigned result_size,
+					    fsl_shw_result_t results[],
+					    unsigned *result_count);
+
+extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx,
+					      fsl_shw_sko_t * key_info,
+					      fsl_shw_key_wrap_t establish_type,
+					      const uint8_t * key);
+
+extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_sko_t * key_info,
+					    uint8_t * covered_key);
+
+extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_sko_t * key_info);
+
+extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx,
+			     uint32_t size,
+			     const uint8_t * UMID, uint32_t permissions);
+
+extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address);
+
+extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx,
+					void *address,
+					fsl_shw_partition_status_t * status);
+
+extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx,
+					       void *address,
+					       uint32_t permissions);
+
+extern fsl_shw_return_t do_scc_engage_partition(fsl_shw_uco_t * user_ctx,
+						void *address,
+						const uint8_t * UMID,
+						uint32_t permissions);
+
+extern fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx,
+						      uint32_t key_lenth,
+						      uint64_t ownerid,
+						      uint32_t * slot);
+
+extern fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t *
+							user_ctx,
+							uint64_t ownerid,
+							uint32_t slot);
+
+extern fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx,
+						     uint64_t ownerid,
+						     uint32_t slot,
+						     const uint8_t * key,
+						     uint32_t key_length);
+
+extern fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx,
+						     uint64_t ownerid,
+						     uint32_t slot,
+						     uint32_t key_length,
+						     const uint8_t * key);
+
+extern fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t *
+							user_ctx,
+							uint64_t ownerid,
+							uint32_t slot,
+							uint32_t key_length,
+							uint8_t * black_data);
+
+extern fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t *
+							user_ctx,
+							uint64_t ownerid,
+							uint32_t slot,
+							uint32_t key_length,
+							const uint8_t *
+							black_data);
+
+extern fsl_shw_return_t
+do_scc_encrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode);
+
+extern fsl_shw_return_t
+do_scc_decrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, const uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode);
+
+extern fsl_shw_return_t
+system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot,
+			      uint32_t * address, uint32_t * slot_size_bytes);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_sko_t * key_info,
+						  fsl_shw_scco_t * sym_ctx,
+						  uint32_t length,
+						  const uint8_t * pt,
+						  uint8_t * ct);
+
+/* PINTFC-API-BASIC-SYM-002 */
+/* PINTFC-API-BASIC-SYM-ARC4-001 */
+/* PINTFC-API-BASIC-SYM-ARC4-002 */
+extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx,
+						  fsl_shw_sko_t * key_info,
+						  fsl_shw_scco_t * sym_ctx,
+						  uint32_t length,
+						  const uint8_t * ct,
+						  uint8_t * pt);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */
+extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_hco_t * hash_ctx,
+				     const uint8_t * msg,
+				     uint32_t length,
+				     uint8_t * result, uint32_t result_len);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */
+extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx,
+						fsl_shw_sko_t * key_info,
+						fsl_shw_hmco_t * hmac_ctx);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */
+extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx,
+				     fsl_shw_sko_t * key_info,
+				     fsl_shw_hmco_t * hmac_ctx,
+				     const uint8_t * msg,
+				     uint32_t length,
+				     uint8_t * result, uint32_t result_len);
+
+/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */
+extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx,
+					   uint32_t length, uint8_t * data);
+
+extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx,
+					    uint32_t length, uint8_t * data);
+
+extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx,
+					    fsl_shw_acco_t * auth_ctx,
+					    fsl_shw_sko_t * cipher_key_info,
+					    fsl_shw_sko_t * auth_key_info,
+					    uint32_t auth_data_length,
+					    const uint8_t * auth_data,
+					    uint32_t payload_length,
+					    const uint8_t * payload,
+					    uint8_t * ct, uint8_t * auth_value);
+
+extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx,
+					     fsl_shw_acco_t * auth_ctx,
+					     fsl_shw_sko_t * cipher_key_info,
+					     fsl_shw_sko_t * auth_key_info,
+					     uint32_t auth_data_length,
+					     const uint8_t * auth_data,
+					     uint32_t payload_length,
+					     const uint8_t * ct,
+					     const uint8_t * auth_value,
+					     uint8_t * payload);
+
+extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx,
+						fsl_shw_sko_t * key_info,
+						uint8_t * key);
+
+static inline fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t *
+							 user_ctx)
+{
+	(void)user_ctx;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+static inline fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t *
+							 user_ctx,
+							 fsl_shw_tamper_t *
+							 tamperp,
+							 uint64_t * timestampp)
+{
+	(void)user_ctx;
+	(void)tamperp;
+	(void)timestampp;
+
+	return FSL_RETURN_NO_RESOURCE_S;
+}
+
+fsl_shw_return_t sah_Append_Desc(const sah_Mem_Util * mu,
+				 sah_Head_Desc ** desc_head,
+				 const uint32_t header,
+				 sah_Link * link1, sah_Link * link2);
+
+/* Utility Function leftover from sahara1 API */
+void sah_Descriptor_Chain_Destroy(const sah_Mem_Util * mu,
+				  sah_Head_Desc ** desc_chain);
+
+/* Utility Function leftover from sahara1 API */
+fsl_shw_return_t sah_Descriptor_Chain_Execute(sah_Head_Desc * desc_chain,
+					      fsl_shw_uco_t * user_ctx);
+
+fsl_shw_return_t sah_Append_Link(const sah_Mem_Util * mu,
+				 sah_Link * link,
+				 uint8_t * p,
+				 const size_t length,
+				 const sah_Link_Flags flags);
+
+fsl_shw_return_t sah_Create_Link(const sah_Mem_Util * mu,
+				 sah_Link ** link,
+				 uint8_t * p,
+				 const size_t length,
+				 const sah_Link_Flags flags);
+
+fsl_shw_return_t sah_Create_Key_Link(const sah_Mem_Util * mu,
+				     sah_Link ** link,
+				     fsl_shw_sko_t * key_info);
+
+void sah_Destroy_Link(const sah_Mem_Util * mu, sah_Link * link);
+
+void sah_Postprocess_Results(fsl_shw_uco_t * user_ctx,
+			     sah_results * result_info);
+
+#endif				/* SAHARA2_API_H */
diff --git a/drivers/mxc/security/sahara2/include/sahara2_kernel.h b/drivers/mxc/security/sahara2/include/sahara2_kernel.h
new file mode 100644
index 000000000000..b833f0ab8f56
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sahara2_kernel.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define DRIVER_NAME sahara2
+
+#define SAHARA_MAJOR_NODE 78
+
+#include "portable_os.h"
+
+#include "platform_abstractions.h"
+
+/* Forward-declare prototypes using signature macros */
+
+OS_DEV_ISR_DCL(sahara2_isr);
+
+OS_DEV_INIT_DCL(sahara2_init);
+
+OS_DEV_SHUTDOWN_DCL(sahara2_shutdown);
+
+OS_DEV_OPEN_DCL(sahara2_open);
+
+OS_DEV_CLOSE_DCL(sahara2_release);
+
+OS_DEV_IOCTL_DCL(sahara2_ioctl);
+
+struct sahara2_kernel_user {
+	void *command_ring[32];
+};
+
+struct sahara2_sym_arg {
+	char *key;
+	unsigned key_len;
+};
+
+/*! These need to be added to Linux / OS abstractions */
+/*
+module_init(OS_DEV_INIT_REF(sahara2_init));
+module_cleanup(OS_DEV_SHUTDOWN_REF(sahara2_shutdown));
+*/
diff --git a/drivers/mxc/security/sahara2/include/sf_util.h b/drivers/mxc/security/sahara2/include/sf_util.h
new file mode 100644
index 000000000000..c0af0c96ff02
--- /dev/null
+++ b/drivers/mxc/security/sahara2/include/sf_util.h
@@ -0,0 +1,466 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sf_util.h
+*
+* @brief Header for Sahara Descriptor-chain building Functions
+*/
+#ifndef SF_UTIL_H
+#define SF_UTIL_H
+
+#include <fsl_platform.h>
+#include <sahara.h>
+
+/*! Header value for Sahara Descriptor  1 */
+#define SAH_HDR_SKHA_SET_MODE_IV_KEY  0x10880000
+/*! Header value for Sahara Descriptor  2 */
+#define SAH_HDR_SKHA_SET_MODE_ENC_DEC 0x108D0000
+/*! Header value for Sahara Descriptor  4 */
+#define SAH_HDR_SKHA_ENC_DEC          0x90850000
+/*! Header value for Sahara Descriptor  5 */
+#define SAH_HDR_SKHA_READ_CONTEXT_IV  0x10820000
+/*! Header value for Sahara Descriptor  6 */
+#define SAH_HDR_MDHA_SET_MODE_MD_KEY  0x20880000
+/*! Header value for Sahara Descriptor  8 */
+#define SAH_HDR_MDHA_SET_MODE_HASH    0x208D0000
+/*! Header value for Sahara Descriptor  10 */
+#define SAH_HDR_MDHA_HASH             0xA0850000
+/*! Header value for Sahara Descriptor  11 */
+#define SAH_HDR_MDHA_STORE_DIGEST     0x20820000
+/*! Header value for Sahara Descriptor  18 */
+#define SAH_HDR_RNG_GENERATE          0x308C0000
+/*! Header value for Sahara Descriptor 19 */
+#define SAH_HDR_PKHA_LD_N_E           0xC0800000
+/*! Header value for Sahara Descriptor 20 */
+#define SAH_HDR_PKHA_LD_A_EX_ST_B     0x408D0000
+/*! Header value for Sahara Descriptor 21 */
+#define SAH_HDR_PKHA_LD_N_EX_ST_B     0x408E0000
+/*! Header value for Sahara Descriptor 22 */
+#define SAH_HDR_PKHA_LD_A_B           0xC0830000
+/*! Header value for Sahara Descriptor 23 */
+#define SAH_HDR_PKHA_LD_A0_A1         0x40840000
+/*! Header value for Sahara Descriptor 24 */
+#define SAH_HDR_PKHA_LD_A2_A3         0xC0850000
+/*! Header value for Sahara Descriptor 25 */
+#define SAH_HDR_PKHA_LD_B0_B1         0xC0860000
+/*! Header value for Sahara Descriptor 26 */
+#define SAH_HDR_PKHA_LD_B2_B3         0x40870000
+/*! Header value for Sahara Descriptor 27 */
+#define SAH_HDR_PKHA_ST_A_B           0x40820000
+/*! Header value for Sahara Descriptor 28 */
+#define SAH_HDR_PKHA_ST_A0_A1         0x40880000
+/*! Header value for Sahara Descriptor 29 */
+#define SAH_HDR_PKHA_ST_A2_A3         0xC0890000
+/*! Header value for Sahara Descriptor 30 */
+#define SAH_HDR_PKHA_ST_B0_B1         0xC08A0000
+/*! Header value for Sahara Descriptor 31 */
+#define SAH_HDR_PKHA_ST_B2_B3         0x408B0000
+/*! Header value for Sahara Descriptor 32 */
+#define SAH_HDR_PKHA_EX_ST_B1         0xC08C0000
+/*! Header value for Sahara Descriptor 33 */
+#define SAH_HDR_ARC4_SET_MODE_SBOX    0x90890000
+/*! Header value for Sahara Descriptor 34 */
+#define SAH_HDR_ARC4_READ_SBOX        0x90860000
+/*! Header value for Sahara Descriptor 35 */
+#define SAH_HDR_ARC4_SET_MODE_KEY     0x90830000
+/*! Header value for Sahara Descriptor 36 */
+#define SAH_HDR_PKHA_LD_A3_B0         0x40810000
+/*! Header value for Sahara Descriptor 37 */
+#define SAH_HDR_PKHA_ST_B1_B2         0xC08F0000
+/*! Header value for Sahara Descriptor 38 */
+#define SAH_HDR_SKHA_CBC_ICV          0x10840000
+/*! Header value for Sahara Descriptor 39 */
+#define SAH_HDR_MDHA_ICV_CHECK        0xA08A0000
+
+/*! Header bit indicating "Link-List optimization" */
+#define SAH_HDR_LLO                   0x01000000
+
+#define SAH_SF_DCLS                                                         \
+    fsl_shw_return_t ret;                                                   \
+    unsigned sf_executed = 0;                                               \
+    sah_Head_Desc* desc_chain = NULL;                                       \
+    uint32_t header
+
+#define SAH_SF_USER_CHECK()                                                 \
+do {                                                                        \
+    ret = sah_validate_uco(user_ctx);                                       \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+} while (0)
+
+#define SAH_SF_EXECUTE()                                                    \
+do {                                                                        \
+    sf_executed = 1;                                                        \
+    ret = sah_Descriptor_Chain_Execute(desc_chain, user_ctx);               \
+} while (0)
+
+#define SAH_SF_DESC_CLEAN()                                                 \
+do {                                                                        \
+    if (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE)) {        \
+        sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc_chain);      \
+    }                                                                       \
+    (void) header;                                                          \
+} while (0)
+
+/*! Add Descriptor with two inputs */
+#define DESC_IN_IN(hdr, len1, ptr1, len2, ptr2)                             \
+{                                                                           \
+    ret = sah_add_two_in_desc(hdr, ptr1, len1, ptr2, len2,                  \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with two vectors */
+#define DESC_D_D(hdr, len1, ptr1, len2, ptr2)                               \
+{                                                                           \
+    ret = sah_add_two_d_desc(hdr, ptr1, len1, ptr2, len2,                   \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with input and a key */
+#define DESC_IN_KEY(hdr, len1, ptr1, key2)                                  \
+{                                                                           \
+    ret = sah_add_in_key_desc(hdr, ptr1, len1, key2,                        \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with input and an output */
+#define DESC_IN_OUT(hdr, len1, ptr1, len2, ptr2)                            \
+{                                                                           \
+    ret = sah_add_in_out_desc(hdr, ptr1, len1, ptr2, len2,                  \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with input and a key output */
+#define DESC_IN_KEYOUT(hdr, len1, ptr1, key2)                               \
+{                                                                           \
+    ret = sah_add_in_keyout_desc(hdr, ptr1, len1, key2,                     \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with a key and an output */
+#define DESC_KEY_OUT(hdr, key1, len2, ptr2)                                 \
+{                                                                           \
+    ret = sah_add_key_out_desc(hdr, key1, ptr2, len2,                       \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with two outputs */
+#define DESC_OUT_OUT(hdr, len1, ptr1, len2, ptr2)                           \
+{                                                                           \
+    ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2,                 \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+/*! Add Descriptor with output then input pointers */
+#define DESC_OUT_IN(hdr, len1, ptr1, len2, ptr2)                            \
+{                                                                           \
+    ret = sah_add_out_in_desc(hdr, ptr1, len1, ptr2, len2,                  \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+
+#ifdef SAH_SF_DEBUG
+/*! Add Descriptor with two outputs */
+#define DBG_DESC(hdr, len1, ptr1, len2, ptr2)                               \
+{                                                                           \
+    ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2,                 \
+                              user_ctx->mem_util, &desc_chain);             \
+    if (ret != FSL_RETURN_OK_S) {                                           \
+        goto out;                                                           \
+    }                                                                       \
+}
+#else
+#define DBG_DESC(hdr, len1, ptr1, len2, ptr2)
+#endif
+
+#ifdef __KERNEL__
+#define DESC_DBG_ON  ({console_loglevel = 8;})
+#define DESC_DBG_OFF ({console_loglevel = 7;})
+#else
+#define DESC_DBG_ON  system("echo 8 > /proc/sys/kernel/printk")
+#define DESC_DBG_OFF system("echo 7 > /proc/sys/kernel/printk")
+#endif
+
+#define DESC_TEMP_ALLOC(size)                                               \
+({                                                                          \
+    uint8_t* ptr;                                                           \
+    ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref,         \
+                                                   size);                   \
+    if (ptr == NULL) {                                                      \
+        ret = FSL_RETURN_NO_RESOURCE_S;                                     \
+        goto out;                                                           \
+    }                                                                       \
+                                                                            \
+    ptr;                                                                    \
+})
+
+#define DESC_TEMP_FREE(ptr)                                                 \
+({                                                                          \
+    if ((ptr != NULL) &&                                                    \
+        (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) {      \
+            user_ctx->mem_util->                                            \
+                mu_free(user_ctx->mem_util->mu_ref, ptr);                   \
+            ptr = NULL;                                                     \
+    }                                                                       \
+})
+
+/* Temporary implementation.  This needs to be in internal/secure RAM */
+#define DESC_TEMP_SECURE_ALLOC(size)                                        \
+({                                                                          \
+    uint8_t* ptr;                                                           \
+    ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref,         \
+                                                   size);                   \
+    if (ptr == NULL) {                                                      \
+        ret = FSL_RETURN_NO_RESOURCE_S;                                     \
+        goto out;                                                           \
+    }                                                                       \
+                                                                            \
+    ptr;                                                                    \
+})
+
+#define DESC_TEMP_SECURE_FREE(ptr, size)                                    \
+({                                                                          \
+    if ((ptr != NULL) &&                                                    \
+        (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) {      \
+            user_ctx->mem_util->mu_memset(user_ctx->mem_util->mu_ref,       \
+                                          ptr, 0, size);                    \
+                                                                            \
+            user_ctx->mem_util->                                            \
+                mu_free(user_ctx->mem_util->mu_ref, ptr);                   \
+            ptr = NULL;                                                     \
+    }                                                                       \
+})
+
+extern const uint32_t sah_insert_mdha_algorithm[];
+
+/*! @defgroup mdhaflags MDHA Mode Register Values
+ *
+ * These are bit fields and combinations of bit fields for setting the Mode
+ * Register portion of a Sahara Descriptor Header field.
+ *
+ * The parity bit has been set to ensure that these values have even parity,
+ * therefore using an Exclusive-OR operation against an existing header will
+ * preserve its parity.
+ *
+ * @addtogroup mdhaflags
+   @{
+ */
+#define sah_insert_mdha_icv_check 0x80001000
+#define sah_insert_mdha_ssl       0x80000400
+#define sah_insert_mdha_mac_full  0x80000200
+#define sah_insert_mdha_opad      0x80000080
+#define sah_insert_mdha_ipad      0x80000040
+#define sah_insert_mdha_init      0x80000020
+#define sah_insert_mdha_hmac      0x80000008
+#define sah_insert_mdha_pdata     0x80000004
+#define sah_insert_mdha_algorithm_sha224  0x00000003
+#define sah_insert_mdha_algorithm_sha256  0x80000002
+#define sah_insert_mdha_algorithm_md5     0x80000001
+#define sah_insert_mdha_algorithm_sha1    0x00000000
+/*! @} */
+
+extern const uint32_t sah_insert_skha_algorithm[];
+extern const uint32_t sah_insert_skha_mode[];
+extern const uint32_t sah_insert_skha_modulus[];
+
+/*! @defgroup skhaflags SKHA Mode Register Values
+ *
+ * These are bit fields and combinations of bit fields for setting the Mode
+ * Register portion of a Sahara Descriptor Header field.
+ *
+ * The parity bit has been set to ensure that these values have even parity,
+ * therefore using an Exclusive-OR operation against an existing header will
+ * preserve its parity.
+ *
+ * @addtogroup skhaflags
+   @{
+ */
+/*! */
+#define sah_insert_skha_modulus_128    0x00001e00
+#define sah_insert_skha_no_key_parity  0x80000100
+#define sah_insert_skha_ctr_last_block 0x80000020
+#define sah_insert_skha_suppress_cbc   0x80000020
+#define sah_insert_skha_no_permute     0x80000020
+#define sah_insert_skha_algorithm_arc4 0x00000003
+#define sah_insert_skha_algorithm_tdes 0x80000002
+#define sah_insert_skha_algorithm_des  0x80000001
+#define sah_insert_skha_algorithm_aes  0x00000000
+#define sah_insert_skha_aux0           0x80000020
+#define sah_insert_skha_mode_ctr       0x00000018
+#define sah_insert_skha_mode_ccm       0x80000010
+#define sah_insert_skha_mode_cbc       0x80000008
+#define sah_insert_skha_mode_ecb       0x00000000
+#define sah_insert_skha_encrypt        0x80000004
+#define sah_insert_skha_decrypt        0x00000000
+/*! @} */
+
+/*! @defgroup rngflags RNG Mode Register Values
+ *
+ */
+/*! */
+#define sah_insert_rng_gen_seed        0x80000001
+
+/*! @} */
+
+/*! @defgroup pkhaflags PKHA Mode Register Values
+ *
+ */
+/*! */
+#define sah_insert_pkha_soft_err_false         0x80000200
+#define sah_insert_pkha_soft_err_true          0x80000100
+
+#define sah_insert_pkha_rtn_clr_mem            0x80000001
+#define sah_insert_pkha_rtn_clr_eram           0x80000002
+#define sah_insert_pkha_rtn_mod_exp            0x00000003
+#define sah_insert_pkha_rtn_mod_r2modn         0x80000004
+#define sah_insert_pkha_rtn_mod_rrmodp         0x00000005
+#define sah_insert_pkha_rtn_ec_fp_aff_ptmul    0x00000006
+#define sah_insert_pkha_rtn_ec_f2m_aff_ptmul   0x80000007
+#define sah_insert_pkha_rtn_ec_fp_proj_ptmul   0x80000008
+#define sah_insert_pkha_rtn_ec_f2m_proj_ptmul  0x00000009
+#define sah_insert_pkha_rtn_ec_fp_add          0x0000000A
+#define sah_insert_pkha_rtn_ec_fp_double       0x8000000B
+#define sah_insert_pkha_rtn_ec_f2m_add         0x0000000C
+#define sah_insert_pkha_rtn_ec_f2m_double      0x8000000D
+#define sah_insert_pkha_rtn_f2m_r2modn         0x8000000E
+#define sah_insert_pkha_rtn_f2m_inv            0x0000000F
+#define sah_insert_pkha_rtn_mod_inv            0x80000010
+#define sah_insert_pkha_rtn_rsa_sstep          0x00000011
+#define sah_insert_pkha_rtn_mod_emodn          0x00000012
+#define sah_insert_pkha_rtn_f2m_emodn          0x80000013
+#define sah_insert_pkha_rtn_ec_fp_ptmul        0x00000014
+#define sah_insert_pkha_rtn_ec_f2m_ptmul       0x80000015
+#define sah_insert_pkha_rtn_f2m_gcd            0x80000016
+#define sah_insert_pkha_rtn_mod_gcd            0x00000017
+#define sah_insert_pkha_rtn_f2m_dbl_aff        0x00000018
+#define sah_insert_pkha_rtn_fp_dbl_aff         0x80000019
+#define sah_insert_pkha_rtn_f2m_add_aff        0x8000001A
+#define sah_insert_pkha_rtn_fp_add_aff         0x0000001B
+#define sah_insert_pkha_rtn_f2m_exp            0x8000001C
+#define sah_insert_pkha_rtn_mod_exp_teq        0x0000001D
+#define sah_insert_pkha_rtn_rsa_sstep_teq      0x0000001E
+#define sah_insert_pkha_rtn_f2m_multn          0x8000001F
+#define sah_insert_pkha_rtn_mod_multn          0x80000020
+#define sah_insert_pkha_rtn_mod_add            0x00000021
+#define sah_insert_pkha_rtn_mod_sub            0x00000022
+#define sah_insert_pkha_rtn_mod_mult1_mont     0x80000023
+#define sah_insert_pkha_rtn_mod_mult2_deconv   0x00000024
+#define sah_insert_pkha_rtn_f2m_add            0x80000025
+#define sah_insert_pkha_rtn_f2m_mult1_mont     0x80000026
+#define sah_insert_pkha_rtn_f2m_mult2_deconv   0x00000027
+#define sah_insert_pkha_rtn_miller_rabin       0x00000028
+#define sah_insert_pkha_rtn_mod_amodn          0x00000029
+#define sah_insert_pkha_rtn_f2m_amodn          0x8000002A
+/*! @} */
+
+/*! Add a descriptor with two input pointers */
+fsl_shw_return_t sah_add_two_in_desc(uint32_t header,
+				     const uint8_t * in1,
+				     uint32_t in1_length,
+				     const uint8_t * in2,
+				     uint32_t in2_length,
+				     const sah_Mem_Util * mu,
+				     sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with two 'data' pointers */
+fsl_shw_return_t sah_add_two_d_desc(uint32_t header,
+				    const uint8_t * in1,
+				    uint32_t in1_length,
+				    const uint8_t * in2,
+				    uint32_t in2_length,
+				    const sah_Mem_Util * mu,
+				    sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with an input and key pointer */
+fsl_shw_return_t sah_add_in_key_desc(uint32_t header,
+				     const uint8_t * in1,
+				     uint32_t in1_length,
+				     fsl_shw_sko_t * key_info,
+				     const sah_Mem_Util * mu,
+				     sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with two key pointers */
+fsl_shw_return_t sah_add_key_key_desc(uint32_t header,
+				      fsl_shw_sko_t * key_info1,
+				      fsl_shw_sko_t * key_info2,
+				      const sah_Mem_Util * mu,
+				      sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with two output pointers */
+fsl_shw_return_t sah_add_two_out_desc(uint32_t header,
+				      uint8_t * out1,
+				      uint32_t out1_length,
+				      uint8_t * out2,
+				      uint32_t out2_length,
+				      const sah_Mem_Util * mu,
+				      sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with an input and output pointer */
+fsl_shw_return_t sah_add_in_out_desc(uint32_t header,
+				     const uint8_t * in, uint32_t in_length,
+				     uint8_t * out, uint32_t out_length,
+				     const sah_Mem_Util * mu,
+				     sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with an input and key output pointer */
+fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header,
+					const uint8_t * in, uint32_t in_length,
+					fsl_shw_sko_t * key_info,
+					const sah_Mem_Util * mu,
+					sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with a key and an output pointer */
+fsl_shw_return_t sah_add_key_out_desc(uint32_t header,
+					  const fsl_shw_sko_t * key_info,
+				      uint8_t * out, uint32_t out_length,
+				      const sah_Mem_Util * mu,
+				      sah_Head_Desc ** desc_chain);
+
+/*! Add a descriptor with an output and input pointer */
+fsl_shw_return_t sah_add_out_in_desc(uint32_t header,
+				     uint8_t * out, uint32_t out_length,
+				     const uint8_t * in, uint32_t in_length,
+				     const sah_Mem_Util * mu,
+				     sah_Head_Desc ** desc_chain);
+
+/*! Verify that supplied User Context Object is valid */
+fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t * uco);
+
+#endif				/* SF_UTIL_H */
+
+/* End of sf_util.h */
diff --git a/drivers/mxc/security/sahara2/km_adaptor.c b/drivers/mxc/security/sahara2/km_adaptor.c
new file mode 100644
index 000000000000..50c4eac3c701
--- /dev/null
+++ b/drivers/mxc/security/sahara2/km_adaptor.c
@@ -0,0 +1,849 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file km_adaptor.c
+*
+* @brief The Adaptor component provides an interface to the
+*        driver for a kernel user.
+*/
+
+#include <adaptor.h>
+#include <sf_util.h>
+#include <sah_queue_manager.h>
+#include <sah_memory_mapper.h>
+#include <fsl_shw_keystore.h>
+#ifdef FSL_HAVE_SCC
+#include <linux/mxc_scc_driver.h>
+#elif defined (FSL_HAVE_SCC2)
+#include <linux/mxc_scc2_driver.h>
+#endif
+
+
+EXPORT_SYMBOL(adaptor_Exec_Descriptor_Chain);
+EXPORT_SYMBOL(sah_register);
+EXPORT_SYMBOL(sah_deregister);
+EXPORT_SYMBOL(sah_get_results);
+EXPORT_SYMBOL(fsl_shw_smalloc);
+EXPORT_SYMBOL(fsl_shw_sfree);
+EXPORT_SYMBOL(fsl_shw_sstatus);
+EXPORT_SYMBOL(fsl_shw_diminish_perms);
+EXPORT_SYMBOL(do_scc_encrypt_region);
+EXPORT_SYMBOL(do_scc_decrypt_region);
+EXPORT_SYMBOL(do_system_keystore_slot_alloc);
+EXPORT_SYMBOL(do_system_keystore_slot_dealloc);
+EXPORT_SYMBOL(do_system_keystore_slot_load);
+EXPORT_SYMBOL(do_system_keystore_slot_read);
+EXPORT_SYMBOL(do_system_keystore_slot_encrypt);
+EXPORT_SYMBOL(do_system_keystore_slot_decrypt);
+
+
+#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR)
+#include <diagnostic.h>
+#endif
+
+#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR)
+#define MAX_DUMP 16
+
+#define DIAG_MSG_SIZE   300
+static char Diag_msg[DIAG_MSG_SIZE];
+#endif
+
+/* This is the wait queue to this mode of driver */
+DECLARE_WAIT_QUEUE_HEAD(Wait_queue_km);
+
+/*! This matches Sahara2 capabilities... */
+fsl_shw_pco_t sahara2_capabilities = {
+	1, 3,			/* api version number - major & minor */
+	1, 6,			/* driver version number - major & minor */
+	{
+	 FSL_KEY_ALG_AES,
+	 FSL_KEY_ALG_DES,
+	 FSL_KEY_ALG_TDES,
+	 FSL_KEY_ALG_ARC4},
+	{
+	 FSL_SYM_MODE_STREAM,
+	 FSL_SYM_MODE_ECB,
+	 FSL_SYM_MODE_CBC,
+	 FSL_SYM_MODE_CTR},
+	{
+	 FSL_HASH_ALG_MD5,
+	 FSL_HASH_ALG_SHA1,
+	 FSL_HASH_ALG_SHA224,
+	 FSL_HASH_ALG_SHA256},
+	/*
+	 * The following table must be set to handle all values of key algorithm
+	 * and sym mode, and be in the correct order..
+	 */
+	{			/* Stream, ECB, CBC, CTR */
+	 {0, 0, 0, 0},		/* HMAC */
+	 {0, 1, 1, 1},		/* AES  */
+	 {0, 1, 1, 0},		/* DES */
+	 {0, 1, 1, 0},		/* 3DES */
+	 {1, 0, 0, 0}		/* ARC4 */
+	 },
+	0, 0,
+	0, 0, 0,
+	{{0, 0}}
+};
+
+#ifdef DIAG_ADAPTOR
+void km_Dump_Chain(const sah_Desc * chain);
+
+void km_Dump_Region(const char *prefix, const unsigned char *data,
+		    unsigned length);
+
+static void km_Dump_Link(const char *prefix, const sah_Link * link);
+
+void km_Dump_Words(const char *prefix, const unsigned *data, unsigned length);
+#endif
+
+/**** Memory routines ****/
+
+static void *my_malloc(void *ref, size_t n)
+{
+	register void *mem;
+
+#ifndef DIAG_MEM_ERRORS
+	mem = os_alloc_memory(n, GFP_KERNEL);
+
+#else
+	{
+		uint32_t rand;
+		/* are we feeling lucky ? */
+		os_get_random_bytes(&rand, sizeof(rand));
+		if ((rand % DIAG_MEM_CONST) == 0) {
+			mem = 0;
+		} else {
+			mem = os_alloc_memory(n, GFP_ATOMIC);
+		}
+	}
+#endif				/* DIAG_MEM_ERRORS */
+
+#ifdef DIAG_MEM
+	sprintf(Diag_msg, "API kmalloc: %p for %d\n", mem, n);
+	LOG_KDIAG(Diag_msg);
+#endif
+	ref = 0;		/* unused param warning */
+	return mem;
+}
+
+static sah_Head_Desc *my_alloc_head_desc(void *ref)
+{
+	register sah_Head_Desc *ptr;
+
+#ifndef DIAG_MEM_ERRORS
+	ptr = sah_Alloc_Head_Descriptor();
+
+#else
+	{
+		uint32_t rand;
+		/* are we feeling lucky ? */
+		os_get_random_bytes(&rand, sizeof(rand));
+		if ((rand % DIAG_MEM_CONST) == 0) {
+			ptr = 0;
+		} else {
+			ptr = sah_Alloc_Head_Descriptor();
+		}
+	}
+#endif
+	ref = 0;
+	return ptr;
+}
+
+static sah_Desc *my_alloc_desc(void *ref)
+{
+	register sah_Desc *ptr;
+
+#ifndef DIAG_MEM_ERRORS
+	ptr = sah_Alloc_Descriptor();
+
+#else
+	{
+		uint32_t rand;
+		/* are we feeling lucky ? */
+		os_get_random_bytes(&rand, sizeof(rand));
+		if ((rand % DIAG_MEM_CONST) == 0) {
+			ptr = 0;
+		} else {
+			ptr = sah_Alloc_Descriptor();
+		}
+	}
+#endif
+	ref = 0;
+	return ptr;
+}
+
+static sah_Link *my_alloc_link(void *ref)
+{
+	register sah_Link *ptr;
+
+#ifndef DIAG_MEM_ERRORS
+	ptr = sah_Alloc_Link();
+
+#else
+	{
+		uint32_t rand;
+		/* are we feeling lucky ? */
+		os_get_random_bytes(&rand, sizeof(rand));
+		if ((rand % DIAG_MEM_CONST) == 0) {
+			ptr = 0;
+		} else {
+			ptr = sah_Alloc_Link();
+		}
+	}
+#endif
+	ref = 0;
+	return ptr;
+}
+
+static void my_free(void *ref, void *ptr)
+{
+	ref = 0;		/* unused param warning */
+#ifdef DIAG_MEM
+	sprintf(Diag_msg, "API kfree: %p\n", ptr);
+	LOG_KDIAG(Diag_msg);
+#endif
+	os_free_memory(ptr);
+}
+
+static void my_free_head_desc(void *ref, sah_Head_Desc * ptr)
+{
+	sah_Free_Head_Descriptor(ptr);
+}
+
+static void my_free_desc(void *ref, sah_Desc * ptr)
+{
+	sah_Free_Descriptor(ptr);
+}
+
+static void my_free_link(void *ref, sah_Link * ptr)
+{
+	sah_Free_Link(ptr);
+}
+
+static void *my_memcpy(void *ref, void *dest, const void *src, size_t n)
+{
+	ref = 0;		/* unused param warning */
+	return memcpy(dest, src, n);
+}
+
+static void *my_memset(void *ref, void *ptr, int ch, size_t n)
+{
+	ref = 0;		/* unused param warning */
+	return memset(ptr, ch, n);
+}
+
+/*! Standard memory manipulation routines for kernel API. */
+static sah_Mem_Util std_kernelmode_mem_util = {
+	.mu_ref = 0,
+	.mu_malloc = my_malloc,
+	.mu_alloc_head_desc = my_alloc_head_desc,
+	.mu_alloc_desc = my_alloc_desc,
+	.mu_alloc_link = my_alloc_link,
+	.mu_free = my_free,
+	.mu_free_head_desc = my_free_head_desc,
+	.mu_free_desc = my_free_desc,
+	.mu_free_link = my_free_link,
+	.mu_memcpy = my_memcpy,
+	.mu_memset = my_memset
+};
+
+fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx,
+				  fsl_shw_pco_t * capabilities)
+{
+	scc_config_t *scc_capabilities;
+
+	/* Fill in the Sahara2 capabilities. */
+	memcpy(capabilities, &sahara2_capabilities, sizeof(fsl_shw_pco_t));
+
+	/* Fill in the SCC portion of the capabilities object */
+	scc_capabilities = scc_get_configuration();
+	capabilities->scc_driver_major = scc_capabilities->driver_major_version;
+	capabilities->scc_driver_minor = scc_capabilities->driver_minor_version;
+	capabilities->scm_version = scc_capabilities->scm_version;
+	capabilities->smn_version = scc_capabilities->smn_version;
+	capabilities->block_size_bytes = scc_capabilities->block_size_bytes;
+
+#ifdef FSL_HAVE_SCC
+	capabilities->scc_info.black_ram_size_blocks =
+	    scc_capabilities->black_ram_size_blocks;
+	capabilities->scc_info.red_ram_size_blocks =
+	    scc_capabilities->red_ram_size_blocks;
+#elif defined(FSL_HAVE_SCC2)
+	capabilities->scc2_info.partition_size_bytes =
+	    scc_capabilities->partition_size_bytes;
+	capabilities->scc2_info.partition_count =
+	    scc_capabilities->partition_count;
+#endif
+
+	return FSL_RETURN_OK_S;
+}
+
+/*!
+ * Sends a request to register this user
+ *
+ * @brief    Sends a request to register this user
+ *
+ * @param[in,out] user_ctx  part of the structure contains input parameters and
+ *                          part is filled in by the driver
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx)
+{
+	fsl_shw_return_t status;
+
+	/* this field is used in user mode to indicate a file open has occured.
+	 * it is used here, in kernel mode, to indicate that the uco is registered
+	 */
+	user_ctx->sahara_openfd = 0;	/* set to 'registered' */
+	user_ctx->mem_util = &std_kernelmode_mem_util;
+
+	/* check that uco is valid */
+	status = sah_validate_uco(user_ctx);
+
+	/*  If life is good, register this user */
+	if (status == FSL_RETURN_OK_S) {
+		status = sah_handle_registration(user_ctx);
+	}
+
+	if (status != FSL_RETURN_OK_S) {
+		user_ctx->sahara_openfd = -1;	/* set to 'not registered' */
+	}
+
+	return status;
+}
+
+/*!
+ * Sends a request to deregister this user
+ *
+ * @brief    Sends a request to deregister this user
+ *
+ * @param[in,out]  user_ctx   Info on user being deregistered.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx)
+{
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+
+	if (user_ctx->sahara_openfd == 0) {
+		status = sah_handle_deregistration(user_ctx);
+		user_ctx->sahara_openfd = -1;	/* set to 'no registered */
+	}
+
+	return status;
+}
+
+/*!
+ * Sends a request to get results for this user
+ *
+ * @brief    Sends a request to get results for this user
+ *
+ * @param[in,out] arg      Pointer to structure to collect results
+ * @param         uco      User's context
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco)
+{
+	fsl_shw_return_t code = sah_get_results_from_pool(uco, arg);
+
+	if ((code == FSL_RETURN_OK_S) && (arg->actual != 0)) {
+		sah_Postprocess_Results(uco, arg);
+	}
+
+	return code;
+}
+
+/*!
+ * This function writes the Descriptor Chain to the kernel driver.
+ *
+ * @brief    Writes the Descriptor Chain to the kernel driver.
+ *
+ * @param    dar   A pointer to a Descriptor Chain of type sah_Head_Desc
+ * @param    uco   The user context object
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar,
+					       fsl_shw_uco_t * uco)
+{
+	sah_Head_Desc *kernel_space_desc = NULL;
+	fsl_shw_return_t code = FSL_RETURN_OK_S;
+	int os_error_code = 0;
+	unsigned blocking_mode = dar->uco_flags & FSL_UCO_BLOCKING_MODE;
+
+#ifdef DIAG_ADAPTOR
+	km_Dump_Chain(&dar->desc);
+#endif
+
+	dar->user_info = uco;
+	dar->user_desc = dar;
+
+	/* This code has been shamelessly copied from sah_driver_interface.c */
+	/* It needs to be moved somewhere common ... */
+	kernel_space_desc = sah_Physicalise_Descriptors(dar);
+
+	if (kernel_space_desc == NULL) {
+		/* We may have failed due to a -EFAULT as well, but we will return
+		 * -ENOMEM since either way it is a memory related failure. */
+		code = FSL_RETURN_NO_RESOURCE_S;
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("sah_Physicalise_Descriptors() failed\n");
+#endif
+	} else {
+		if (blocking_mode) {
+#ifdef SAHARA_POLL_MODE
+			os_error_code = sah_Handle_Poll(dar);
+#else
+			os_error_code = sah_blocking_mode(dar);
+#endif
+			if (os_error_code != 0) {
+				code = FSL_RETURN_ERROR_S;
+			} else {	/* status of actual operation */
+				code = dar->result;
+			}
+		} else {
+#ifdef SAHARA_POLL_MODE
+			sah_Handle_Poll(dar);
+#else
+			/* just put someting in the DAR */
+			sah_Queue_Manager_Append_Entry(dar);
+#endif				/* SAHARA_POLL_MODE */
+		}
+	}
+
+	return code;
+}
+
+
+/* System keystore context, defined in sah_driver_interface.c */
+extern fsl_shw_kso_t system_keystore;
+
+fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx,
+					       uint32_t key_length,
+					       uint64_t ownerid,
+					       uint32_t * slot)
+{
+	(void)user_ctx;
+	return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot);
+}
+
+fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot)
+{
+	(void)user_ctx;
+	return keystore_slot_dealloc(&system_keystore, ownerid, slot);
+}
+
+fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx,
+					      uint64_t ownerid,
+					      uint32_t slot,
+					      const uint8_t * key,
+					      uint32_t key_length)
+{
+	(void)user_ctx;
+	return keystore_slot_load(&system_keystore, ownerid, slot,
+				  (void *)key, key_length);
+}
+
+fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx,
+					      uint64_t ownerid,
+					      uint32_t slot,
+					      uint32_t key_length,
+					      const uint8_t * key)
+{
+	(void)user_ctx;
+	return keystore_slot_read(&system_keystore, ownerid, slot,
+				  key_length, (void *)key);
+}
+
+fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot,
+						 uint32_t key_length,
+						 uint8_t * black_data)
+{
+	(void)user_ctx;
+	return keystore_slot_encrypt(NULL, &system_keystore, ownerid,
+				     slot, key_length, black_data);
+}
+
+fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx,
+						 uint64_t ownerid,
+						 uint32_t slot,
+						 uint32_t key_length,
+						 const uint8_t * black_data)
+{
+	(void)user_ctx;
+	return keystore_slot_decrypt(NULL, &system_keystore, ownerid,
+				     slot, key_length, black_data);
+}
+
+void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx,
+		      uint32_t size, const uint8_t * UMID, uint32_t permissions)
+{
+#ifdef FSL_HAVE_SCC2
+	int part_no;
+	void *part_base;
+	uint32_t part_phys;
+	scc_config_t *scc_configuration;
+
+	/* Check that the memory size requested is correct */
+	scc_configuration = scc_get_configuration();
+	if (size != scc_configuration->partition_size_bytes) {
+		return NULL;
+	}
+
+	/* Attempt to grab a partition. */
+	if (scc_allocate_partition(0, &part_no, &part_base, &part_phys)
+	    != SCC_RET_OK) {
+		return NULL;
+	}
+	printk(KERN_ALERT "In fsh_shw_smalloc (km): partition_base:%p "
+	       "partition_base_phys: %p\n", part_base, (void *)part_phys);
+
+	/* these bits should be in a separate function */
+	printk(KERN_ALERT "writing UMID and MAP to secure the partition\n");
+
+	scc_engage_partition(part_base, UMID, permissions);
+
+	(void)user_ctx;		/* unused param warning */
+
+	return part_base;
+#else				/* FSL_HAVE_SCC2 */
+	(void)user_ctx;
+	(void)size;
+	(void)UMID;
+	(void)permissions;
+	return NULL;
+#endif				/* FSL_HAVE_SCC2 */
+
+}
+
+fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address)
+{
+	(void)user_ctx;
+
+#ifdef FSL_HAVE_SCC2
+	if (scc_release_partition(address) == SCC_RET_OK) {
+		return FSL_RETURN_OK_S;
+	}
+#endif
+
+	return FSL_RETURN_ERROR_S;
+}
+
+fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx,
+				 void *address,
+				 fsl_shw_partition_status_t * status)
+{
+	(void)user_ctx;
+
+#ifdef FSL_HAVE_SCC2
+	*status = scc_partition_status(address);
+	return FSL_RETURN_OK_S;
+#endif
+
+	return FSL_RETURN_ERROR_S;
+}
+
+/* Diminish permissions on some secure memory */
+fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx,
+					void *address, uint32_t permissions)
+{
+
+	(void)user_ctx;		/* unused parameter warning */
+
+#ifdef FSL_HAVE_SCC2
+	if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) {
+		return FSL_RETURN_OK_S;
+	}
+#endif
+	return FSL_RETURN_ERROR_S;
+}
+
+/*
+ * partition_base - physical address of the partition
+ * offset - offset, in blocks, of the data from the start of the partition
+ * length - length, in bytes, of the data to be encrypted (multiple of 4)
+ * black_data - virtual address that the encrypted data should be stored at
+ * Note that this virtual address must be translatable using the __virt_to_phys
+ * macro; ie, it can't be a specially mapped address.  To do encryption with those
+ * addresses, use the scc_encrypt_region function directly.  This is to make
+ * this function compatible with the user mode declaration, which does not know
+ * the physical addresses of the data it is using.
+ */
+fsl_shw_return_t
+do_scc_encrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode)
+{
+	scc_return_t scc_ret;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+
+#ifdef FSL_HAVE_SCC2
+
+#ifdef DIAG_ADAPTOR
+	uint32_t *owner_32 = (uint32_t *) & (owner_id);
+
+	LOG_KDIAG_ARGS
+	    ("partition base: %p, offset: %i, count: %i, black data: %p\n",
+	     partition_base, offset_bytes, byte_count, (void *)black_data);
+#endif
+	(void)user_ctx;
+
+	os_cache_flush_range(black_data, byte_count);
+
+	scc_ret =
+	    scc_encrypt_region((uint32_t) partition_base, offset_bytes,
+			       byte_count, __virt_to_phys(black_data), IV,
+			       cypher_mode);
+
+	if (scc_ret == SCC_RET_OK) {
+		retval = FSL_RETURN_OK_S;
+	} else {
+		retval = FSL_RETURN_ERROR_S;
+	}
+
+	/* The SCC2 DMA engine should have written to the black ram, so we need to
+	 * invalidate that region of memory.  Note that the red ram is not an
+	 * because it is mapped with the cache disabled.
+	 */
+	os_cache_inv_range(black_data, byte_count);
+
+#else
+	(void)scc_ret;
+#endif				/* FSL_HAVE_SCC2 */
+
+	return retval;
+}
+
+/*!
+ * Call the proper function to decrypt a region of encrypted secure memory
+ *
+ * @brief
+ *
+ * @param   user_ctx        User context of the partition owner (NULL in kernel)
+ * @param   partition_base  Base address (physical) of the partition
+ * @param   offset_bytes    Offset from base address that the decrypted data
+ *                          shall be placed
+ * @param   byte_count      Length of the message (bytes)
+ * @param   black_data      Pointer to where the encrypted data is stored
+ * @param   owner_id
+ *
+ * @return  status
+ */
+
+fsl_shw_return_t
+do_scc_decrypt_region(fsl_shw_uco_t * user_ctx,
+		      void *partition_base, uint32_t offset_bytes,
+		      uint32_t byte_count, const uint8_t * black_data,
+		      uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode)
+{
+	scc_return_t scc_ret;
+	fsl_shw_return_t retval = FSL_RETURN_ERROR_S;
+
+#ifdef FSL_HAVE_SCC2
+
+#ifdef DIAG_ADAPTOR
+	uint32_t *owner_32 = (uint32_t *) & (owner_id);
+
+	LOG_KDIAG_ARGS
+	    ("partition base: %p, offset: %i, count: %i, black data: %p\n",
+	     partition_base, offset_bytes, byte_count, (void *)black_data);
+#endif
+
+	(void)user_ctx;
+
+	/* The SCC2 DMA engine will be reading from the black ram, so we need to
+	 * make sure that the data is pushed out of the cache.  Note that the red
+	 * ram is not an issue because it is mapped with the cache disabled.
+	 */
+	os_cache_flush_range(black_data, byte_count);
+
+	scc_ret =
+	    scc_decrypt_region((uint32_t) partition_base, offset_bytes,
+			       byte_count,
+			       (uint8_t *) __virt_to_phys(black_data), IV,
+			       cypher_mode);
+
+	if (scc_ret == SCC_RET_OK) {
+		retval = FSL_RETURN_OK_S;
+	} else {
+		retval = FSL_RETURN_ERROR_S;
+	}
+
+#else
+	(void)scc_ret;
+#endif				/* FSL_HAVE_SCC2 */
+
+	return retval;
+}
+
+#ifdef DIAG_ADAPTOR
+/*!
+ * Dump chain of descriptors to the log.
+ *
+ * @brief Dump descriptor chain
+ *
+ * @param    chain     Kernel virtual address of start of chain of descriptors
+ *
+ * @return   void
+ */
+void km_Dump_Chain(const sah_Desc * chain)
+{
+	while (chain != NULL) {
+		km_Dump_Words("Desc", (unsigned *)chain,
+			      6 /*sizeof(*chain)/sizeof(unsigned) */ );
+		/* place this definition elsewhere */
+		if (chain->ptr1) {
+			if (chain->header & SAH_HDR_LLO) {
+				km_Dump_Region(" Data1", chain->ptr1,
+					       chain->len1);
+			} else {
+				km_Dump_Link(" Link1", chain->ptr1);
+			}
+		}
+		if (chain->ptr2) {
+			if (chain->header & SAH_HDR_LLO) {
+				km_Dump_Region(" Data2", chain->ptr2,
+					       chain->len2);
+			} else {
+				km_Dump_Link(" Link2", chain->ptr2);
+			}
+		}
+
+		chain = chain->next;
+	}
+}
+
+/*!
+ * Dump chain of links to the log.
+ *
+ * @brief Dump chain of links
+ *
+ * @param    prefix    Text to put in front of dumped data
+ * @param    link      Kernel virtual address of start of chain of links
+ *
+ * @return   void
+ */
+static void km_Dump_Link(const char *prefix, const sah_Link * link)
+{
+	while (link != NULL) {
+		km_Dump_Words(prefix, (unsigned *)link,
+			      3 /* # words in h/w link */ );
+		if (link->flags & SAH_STORED_KEY_INFO) {
+#ifdef CAN_DUMP_SCC_DATA
+			uint32_t len;
+#endif
+
+#ifdef CAN_DUMP_SCC_DATA
+			{
+				char buf[50];
+
+				scc_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data,	/* RED key address */
+						  &len);	/* key length */
+				sprintf(buf, "  SCC slot %d: ", link->slot);
+				km_Dump_Words(buf,
+					      (void *)IO_ADDRESS((uint32_t)
+								 link->data),
+					      link->len / 4);
+			}
+#else
+			sprintf(Diag_msg, "  SCC slot %d", link->slot);
+			LOG_KDIAG(Diag_msg);
+#endif
+		} else if (link->data != NULL) {
+			km_Dump_Region("  Data", link->data, link->len);
+		}
+
+		link = link->next;
+	}
+}
+
+/*!
+ * Dump given region of data to the log.
+ *
+ * @brief Dump data
+ *
+ * @param    prefix    Text to put in front of dumped data
+ * @param    data      Kernel virtual address of start of region to dump
+ * @param    length    Amount of data to dump
+ *
+ * @return   void
+*/
+void km_Dump_Region(const char *prefix, const unsigned char *data,
+		    unsigned length)
+{
+	unsigned count;
+	char *output;
+	unsigned data_len;
+
+	sprintf(Diag_msg, "%s (%08X,%u):", prefix, (uint32_t) data, length);
+
+	/* Restrict amount of data to dump */
+	if (length > MAX_DUMP) {
+		data_len = MAX_DUMP;
+	} else {
+		data_len = length;
+	}
+
+	/* We've already printed some text in output buffer, skip over it */
+	output = Diag_msg + strlen(Diag_msg);
+
+	for (count = 0; count < data_len; count++) {
+		if (count % 4 == 0) {
+			*output++ = ' ';
+		}
+		sprintf(output, "%02X", *data++);
+		output += 2;
+	}
+
+	LOG_KDIAG(Diag_msg);
+}
+
+/*!
+ * Dump given wors of data to the log.
+ *
+ * @brief Dump data
+ *
+ * @param    prefix       Text to put in front of dumped data
+ * @param    data         Kernel virtual address of start of region to dump
+ * @param    word_count   Amount of data to dump
+ *
+ * @return   void
+*/
+void km_Dump_Words(const char *prefix, const unsigned *data,
+		   unsigned word_count)
+{
+	char *output;
+
+	sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, (uint32_t) data,
+		word_count);
+
+	/* We've already printed some text in output buffer, skip over it */
+	output = Diag_msg + strlen(Diag_msg);
+
+	while (word_count--) {
+		sprintf(output, "%08X ", *data++);
+		output += 9;
+	}
+
+	LOG_KDIAG(Diag_msg);
+}
+#endif
diff --git a/drivers/mxc/security/sahara2/sah_driver_interface.c b/drivers/mxc/security/sahara2/sah_driver_interface.c
new file mode 100644
index 000000000000..141fcbdf39dd
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_driver_interface.c
@@ -0,0 +1,2179 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sah_driver_interface.c
+*
+* @brief Provides a Linux Kernel Module interface to the SAHARA h/w device.
+*
+*/
+
+/* SAHARA Includes */
+#include <sah_driver_common.h>
+#include <sah_kernel.h>
+#include <sah_memory_mapper.h>
+#include <sah_queue_manager.h>
+#include <sah_status_manager.h>
+#include <sah_interrupt_handler.h>
+#include <sah_hardware_interface.h>
+#include <fsl_shw_keystore.h>
+#include <adaptor.h>
+#ifdef FSL_HAVE_SCC
+#include <linux/mxc_scc_driver.h>
+#else
+#include <linux/mxc_scc2_driver.h>
+#endif
+
+#ifdef DIAG_DRV_IF
+#include <diagnostic.h>
+#endif
+
+#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+#include <linux/devfs_fs_kernel.h>
+#else
+#include <linux/proc_fs.h>
+#endif
+
+#ifdef PERF_TEST
+#define interruptible_sleep_on(x) sah_Handle_Interrupt()
+#endif
+
+#define TEST_MODE_OFF 1
+#define TEST_MODE_ON 2
+
+/*! Version register on first deployments */
+#define SAHARA_VERSION2  2
+/*! Version register on MX27 */
+#define SAHARA_VERSION3  3
+/*! Version register on MXC92323 */
+#define SAHARA_VERSION4  4
+
+/******************************************************************************
+* Module function declarations
+******************************************************************************/
+
+OS_DEV_INIT_DCL(sah_init);
+OS_DEV_SHUTDOWN_DCL(sah_cleanup);
+OS_DEV_OPEN_DCL(sah_open);
+OS_DEV_CLOSE_DCL(sah_release);
+OS_DEV_IOCTL_DCL(sah_ioctl);
+OS_DEV_MMAP_DCL(sah_mmap);
+
+static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t* user_ctx,
+                                                 uint32_t info);
+
+static void sah_user_callback(fsl_shw_uco_t * user_ctx);
+static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t* user_ctx,
+                                          uint32_t info);
+static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t* user_ctx,
+                                          uint32_t info);
+static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t* user_ctx,
+                                               uint32_t info);
+static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t* user_ctx,
+                                            uint32_t info);
+static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t* user_ctx,
+                                            uint32_t info);
+
+#ifdef FSL_HAVE_SCC2
+static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx,
+						uint32_t user_base,
+						void *kernel_base);
+static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx,
+						  uint32_t user_base);
+#endif
+
+static os_error_code sah_handle_sk_slot_alloc(uint32_t info);
+static os_error_code sah_handle_sk_slot_dealloc(uint32_t info);
+static os_error_code sah_handle_sk_slot_load(uint32_t info);
+static os_error_code sah_handle_sk_slot_read(uint32_t info);
+static os_error_code sah_handle_sk_slot_decrypt(uint32_t info);
+static os_error_code sah_handle_sk_slot_encrypt(uint32_t info);
+
+/*! Boolean flag for whether interrupt handler needs to be released on exit */
+static unsigned interrupt_registered;
+
+static int handle_sah_ioctl_dar(fsl_shw_uco_t * filp, uint32_t user_space_desc);
+
+#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
+static int sah_read_procfs(char *buf,
+			   char **start,
+			   off_t offset, int count, int *eof, void *data);
+
+static int sah_write_procfs(struct file *file, const char __user * buffer,
+			    unsigned long count, void *data);
+#endif
+
+#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+
+/* This is a handle to the sahara DEVFS entry. */
+static devfs_handle_t Sahara_devfs_handle;
+
+#else
+
+/* Major number assigned to our device driver */
+static int Major;
+
+/* This is a handle to the sahara PROCFS entry */
+static struct proc_dir_entry *Sahara_procfs_handle;
+
+#endif
+
+uint32_t sah_hw_version;
+extern void *sah_virt_base;
+
+/* This is the wait queue to this driver.  Linux declaration. */
+DECLARE_WAIT_QUEUE_HEAD(Wait_queue);
+
+/* This is a global variable that is used to track how many times the device
+ * has been opened simultaneously. */
+#ifdef DIAG_DRV_IF
+static int Device_in_use = 0;
+#endif
+
+/* This is the system keystore object */
+fsl_shw_kso_t system_keystore;
+
+/*!
+ * OS-dependent handle used for registering user interface of a driver.
+ */
+static os_driver_reg_t reg_handle;
+
+#ifdef DIAG_DRV_IF
+/* This is for sprintf() to use when constructing output. */
+#define DIAG_MSG_SIZE   1024
+static char Diag_msg[DIAG_MSG_SIZE];
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
+/** Pointer to Sahara clock information.  Initialized during os_dev_init(). */
+static struct clk *sah_clk;
+#endif
+
+/*!
+*******************************************************************************
+* This function gets called when the module is inserted (insmod) into  the
+* running kernel.
+*
+* @brief     SAHARA device initialisation function.
+*
+* @return   0 on success
+* @return   -EBUSY if the device or proc file entry cannot be created.
+* @return   OS_ERROR_NO_MEMORY_S if kernel memory could not be allocated.
+* @return   OS_ERROR_FAIL_S if initialisation of proc entry failed
+*/
+OS_DEV_INIT(sah_init)
+{
+	/* Status variable */
+	int os_error_code = 0;
+	uint32_t sah_phys_base = SAHARA_BASE_ADDR;
+
+
+	interrupt_registered = 0;
+
+	/* Enable the SAHARA Clocks */
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG("SAHARA : Enabling the IPG and AHB clocks\n")
+#endif				/*DIAG_DRV_IF */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+	    mxc_clks_enable(SAHARA2_CLK);
+#else
+	{
+		sah_clk = clk_get(NULL, "sahara_clk");
+		if (sah_clk != ERR_PTR(ENOENT))
+			clk_enable(sah_clk);
+	}
+#endif
+
+	if (cpu_is_mx53())
+		sah_phys_base -= 0x20000000;
+
+	sah_virt_base = (void *)ioremap(sah_phys_base, SZ_16K);
+	if (sah_virt_base == NULL) {
+		os_printk(KERN_ERR
+			  "SAHARA: Register mapping failed\n");
+		os_error_code = OS_ERROR_FAIL_S;
+	}
+
+	if (os_error_code == OS_ERROR_OK_S) {
+		sah_hw_version = sah_HW_Read_Version();
+		os_printk("Sahara HW Version is 0x%08x\n", sah_hw_version);
+
+		/* verify code and hardware are version compatible */
+		if ((sah_hw_version != SAHARA_VERSION2)
+		    && (sah_hw_version != SAHARA_VERSION3)) {
+			if (((sah_hw_version >> 8) & 0xff) != SAHARA_VERSION4) {
+				os_printk
+				    ("Sahara HW Version was not expected value.\n");
+				os_error_code = OS_ERROR_FAIL_S;
+			}
+		}
+	}
+
+	if (os_error_code == OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("Calling sah_Init_Mem_Map to initialise "
+			  "memory subsystem.");
+#endif
+		/* Do any memory-routine initialization */
+		os_error_code = sah_Init_Mem_Map();
+	}
+
+	if (os_error_code == OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("Calling sah_HW_Reset() to Initialise the Hardware.");
+#endif
+		/* Initialise the hardware */
+		os_error_code = sah_HW_Reset();
+		if (os_error_code != OS_ERROR_OK_S) {
+			os_printk
+			    ("sah_HW_Reset() failed to Initialise the Hardware.\n");
+		}
+
+	}
+
+	if (os_error_code == OS_ERROR_OK_S) {
+#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+		/* Register the DEVFS entry */
+		Sahara_devfs_handle = devfs_register(NULL,
+						     SAHARA_DEVICE_SHORT,
+						     DEVFS_FL_AUTO_DEVNUM,
+						     0, 0,
+						     SAHARA_DEVICE_MODE,
+						     &Fops, NULL);
+		if (Sahara_devfs_handle == NULL) {
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG
+			    ("Registering the DEVFS character device failed.");
+#endif				/* DIAG_DRV_IF */
+			os_error_code = -EBUSY;
+		}
+#else				/* CONFIG_DEVFS_FS */
+		/* Create the PROCFS entry. This is used to report the assigned device
+		 * major number back to user-space. */
+#if 1
+		Sahara_procfs_handle = create_proc_entry(SAHARA_DEVICE_SHORT, 0700,	/* default mode */
+							 NULL);	/* parent dir */
+		if (Sahara_procfs_handle == NULL) {
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("Registering the PROCFS interface failed.");
+#endif				/* DIAG_DRV_IF */
+			os_error_code = OS_ERROR_FAIL_S;
+		} else {
+			Sahara_procfs_handle->nlink = 1;
+			Sahara_procfs_handle->data = 0;
+			Sahara_procfs_handle->read_proc = sah_read_procfs;
+			Sahara_procfs_handle->write_proc = sah_write_procfs;
+		}
+#endif				/* #if 1 */
+	}
+
+	if (os_error_code == OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG
+		    ("Calling sah_Queue_Manager_Init() to Initialise the Queue "
+		     "Manager.");
+#endif
+		/* Initialise the Queue Manager */
+		if (sah_Queue_Manager_Init() != FSL_RETURN_OK_S) {
+			os_error_code = -ENOMEM;
+		}
+	}
+#ifndef SAHARA_POLL_MODE
+	if (os_error_code == OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("Calling sah_Intr_Init() to Initialise the Interrupt "
+			  "Handler.");
+#endif
+		/* Initialise the Interrupt Handler */
+		os_error_code = sah_Intr_Init(&Wait_queue);
+		if (os_error_code == OS_ERROR_OK_S) {
+			interrupt_registered = 1;
+		}
+	}
+#endif				/* ifndef SAHARA_POLL_MODE */
+
+#ifdef SAHARA_POWER_MANAGEMENT
+	if (os_error_code == OS_ERROR_OK_S) {
+		/* set up dynamic power management (dmp) */
+		os_error_code = sah_dpm_init();
+	}
+#endif
+
+	if (os_error_code == OS_ERROR_OK_S) {
+		os_driver_init_registration(reg_handle);
+		os_driver_add_registration(reg_handle, OS_FN_OPEN,
+					   OS_DEV_OPEN_REF(sah_open));
+		os_driver_add_registration(reg_handle, OS_FN_IOCTL,
+					   OS_DEV_IOCTL_REF(sah_ioctl));
+		os_driver_add_registration(reg_handle, OS_FN_CLOSE,
+					   OS_DEV_CLOSE_REF(sah_release));
+		os_driver_add_registration(reg_handle, OS_FN_MMAP,
+					   OS_DEV_MMAP_REF(sah_mmap));
+
+		os_error_code =
+		    os_driver_complete_registration(reg_handle, Major,
+						    "sahara");
+
+		if (os_error_code < OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+			snprintf(Diag_msg, DIAG_MSG_SIZE,
+				 "Registering the regular "
+				 "character device failed with error code: %d\n",
+				 os_error_code);
+			LOG_KDIAG(Diag_msg);
+#endif
+		}
+	}
+#endif				/* CONFIG_DEVFS_FS */
+
+	if (os_error_code == OS_ERROR_OK_S) {
+		/* set up the system keystore, using the default keystore handler */
+		fsl_shw_init_keystore_default(&system_keystore);
+
+		if (fsl_shw_establish_keystore(NULL, &system_keystore)
+		    == FSL_RETURN_OK_S) {
+			os_error_code = OS_ERROR_OK_S;
+		} else {
+			os_error_code = OS_ERROR_FAIL_S;
+		}
+
+		if (os_error_code != OS_ERROR_OK_S) {
+#ifdef DIAG_DRV_IF
+			snprintf(Diag_msg, DIAG_MSG_SIZE,
+				 "Registering the system keystore "
+				 "failed with error code: %d\n", os_error_code);
+			LOG_KDIAG(Diag_msg);
+#endif
+		}
+	}
+
+	if (os_error_code != OS_ERROR_OK_S) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+		cleanup_module();
+#else
+		sah_cleanup();
+#endif
+	}
+#ifdef DIAG_DRV_IF
+	else {
+		LOG_KDIAG_ARGS("Sahara major node is %d\n", Major);
+	}
+#endif
+
+/* Disabling the Clock after the driver has been registered fine.
+    This is done to save power when Sahara is not in use.*/
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG("SAHARA : Disabling the clocks\n")
+#endif				/* DIAG_DRV_IF */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+		mxc_clks_disable(SAHARA2_CLK);
+#else
+	{
+		if (sah_clk != ERR_PTR(ENOENT))
+			clk_disable(sah_clk);
+	}
+#endif
+
+	os_dev_init_return(os_error_code);
+}
+
+/*!
+*******************************************************************************
+* This function gets called when the module is removed (rmmod) from the running
+* kernel.
+*
+* @brief     SAHARA device clean-up function.
+*
+* @return   void
+*/
+OS_DEV_SHUTDOWN(sah_cleanup)
+{
+	int ret_val = 0;
+
+	printk(KERN_ALERT "Sahara going into cleanup\n");
+
+	/* clear out the system keystore */
+	fsl_shw_release_keystore(NULL, &system_keystore);
+
+	/* Unregister the device */
+#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+	devfs_unregister(Sahara_devfs_handle);
+#else
+
+	if (Sahara_procfs_handle != NULL) {
+		remove_proc_entry(SAHARA_DEVICE_SHORT, NULL);
+	}
+
+	if (Major >= 0) {
+		ret_val = os_driver_remove_registration(reg_handle);
+	}
+#ifdef DIAG_DRV_IF
+	if (ret_val < 0) {
+		snprintf(Diag_msg, DIAG_MSG_SIZE, "Error while attempting to "
+			 "unregister the device: %d\n", ret_val);
+		LOG_KDIAG(Diag_msg);
+	}
+#endif
+
+#endif				/* CONFIG_DEVFS_FS */
+	sah_Queue_Manager_Close();
+
+#ifndef SAHARA_POLL_MODE
+	if (interrupt_registered) {
+		sah_Intr_Release();
+		interrupt_registered = 0;
+	}
+#endif
+	sah_Stop_Mem_Map();
+#ifdef SAHARA_POWER_MANAGEMENT
+	sah_dpm_close();
+#endif
+
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG("SAHARA : Disabling the clocks\n")
+#endif				/* DIAG_DRV_IF */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+	    mxc_clks_disable(SAHARA2_CLK);
+#else
+	{
+		if (sah_clk != ERR_PTR(ENOENT))
+			clk_disable(sah_clk);
+		clk_put(sah_clk);
+	}
+#endif
+
+	os_dev_shutdown_return(OS_ERROR_OK_S);
+}
+
+/*!
+*******************************************************************************
+* This function simply increments the module usage count.
+*
+* @brief     SAHARA device open function.
+*
+* @param    inode Part of the kernel prototype.
+* @param    file Part of the kernel prototype.
+*
+* @return   0 - Always returns 0 since any number of calls to this function are
+*               allowed.
+*
+*/
+OS_DEV_OPEN(sah_open)
+{
+
+#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
+	MOD_INC_USE_COUNT;
+#endif
+
+#ifdef DIAG_DRV_IF
+	Device_in_use++;
+	snprintf(Diag_msg, DIAG_MSG_SIZE,
+		 "Incrementing module use count to: %d ", Device_in_use);
+	LOG_KDIAG(Diag_msg);
+#endif
+
+	os_dev_set_user_private(NULL);
+
+	/* Return 0 to indicate success */
+	os_dev_open_return(0);
+}
+
+/*!
+*******************************************************************************
+* This function simply decrements the module usage count.
+*
+* @brief     SAHARA device release function.
+*
+* @param    inode   Part of the kernel prototype.
+* @param    file    Part of the kernel prototype.
+*
+* @return   0 - Always returns 0 since this function does not fail.
+*/
+OS_DEV_CLOSE(sah_release)
+{
+	fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
+	MOD_DEC_USE_COUNT;
+#endif
+
+#ifdef DIAG_DRV_IF
+	Device_in_use--;
+	snprintf(Diag_msg, DIAG_MSG_SIZE,
+		 "Decrementing module use count to: %d ", Device_in_use);
+	LOG_KDIAG(Diag_msg);
+#endif
+
+	if (user_ctx != NULL) {
+		sah_handle_deregistration(user_ctx);
+		os_free_memory(user_ctx);
+		os_dev_set_user_private(NULL);
+	}
+
+	/* Return 0 to indicate success */
+	os_dev_close_return(OS_ERROR_OK_S);
+}
+
+/*!
+*******************************************************************************
+* This function provides the IO Controls for the SAHARA driver. Three IO
+* Controls are supported:
+*
+*   SAHARA_HWRESET and
+*   SAHARA_SET_HA
+*   SAHARA_CHK_TEST_MODE
+*
+* @brief SAHARA device IO Control function.
+*
+* @param    inode   Part of the kernel prototype.
+* @param    filp    Part of the kernel prototype.
+* @param    cmd     Part of the kernel prototype.
+* @param    arg     Part of the kernel prototype.
+*
+* @return   0 on success
+* @return   -EBUSY if the HA bit could not be set due to busy hardware.
+* @return   -ENOTTY if an unsupported IOCTL was attempted on the device.
+* @return   -EFAULT if put_user() fails
+*/
+OS_DEV_IOCTL(sah_ioctl)
+{
+	int status = 0;
+	int test_mode;
+
+	switch (os_dev_get_ioctl_op()) {
+	case SAHARA_HWRESET:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_HWRESET IOCTL.");
+#endif
+		/* We need to reset the hardware. */
+		sah_HW_Reset();
+
+		/* Mark all the entries in the Queue Manager's queue with state
+		 * SAH_STATE_RESET.
+		 */
+		sah_Queue_Manager_Reset_Entries();
+
+		/* Wake up all sleeping write() calls. */
+		wake_up_interruptible(&Wait_queue);
+		break;
+#ifdef SAHARA_HA_ENABLED
+	case SAHARA_SET_HA:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SET_HA IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		if (sah_HW_Set_HA() == ERR_INTERNAL) {
+			status = -EBUSY;
+		}
+		break;
+#endif				/* SAHARA_HA_ENABLED */
+
+	case SAHARA_CHK_TEST_MODE:
+		/* load test_mode */
+		test_mode = TEST_MODE_OFF;
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_CHECK_TEST_MODE IOCTL.");
+		test_mode = TEST_MODE_ON;
+#endif				/* DIAG_DRV_IF */
+#if defined(KERNEL_TEST) || defined(PERF_TEST)
+		test_mode = TEST_MODE_ON;
+#endif				/* KERNEL_TEST || PERF_TEST */
+		/* copy test_mode back to user space.  put_user() is Linux fn */
+		/* compiler warning `register': no problem found so ignored */
+		status = put_user(test_mode, (int *)os_dev_get_ioctl_arg());
+		break;
+
+	case SAHARA_DAR:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_DAR IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			if (user_ctx != NULL) {
+				status =
+				    handle_sah_ioctl_dar(user_ctx,
+							 os_dev_get_ioctl_arg
+							 ());
+			} else {
+				status = OS_ERROR_FAIL_S;
+			}
+
+		}
+		break;
+
+	case SAHARA_GET_RESULTS:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_GET_RESULTS IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			if (user_ctx != NULL) {
+				status =
+				    sah_get_results_pointers(user_ctx,
+							     os_dev_get_ioctl_arg
+							     ());
+			} else {
+				status = OS_ERROR_FAIL_S;
+			}
+		}
+		break;
+
+	case SAHARA_REGISTER:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_REGISTER IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			if (user_ctx != NULL) {
+				status = OS_ERROR_FAIL_S;	/* already registered */
+			} else {
+				user_ctx =
+				    os_alloc_memory(sizeof(fsl_shw_uco_t),
+						    GFP_KERNEL);
+				if (user_ctx == NULL) {
+					status = OS_ERROR_NO_MEMORY_S;
+				} else {
+					/* Copy UCO from user, but only as big as the common UCO */
+					if (os_copy_from_user(user_ctx,
+							      (void *)
+							      os_dev_get_ioctl_arg
+							      (),
+							      offsetof
+							      (fsl_shw_uco_t,
+							       result_pool))) {
+						status = OS_ERROR_FAIL_S;
+					} else {
+						os_dev_set_user_private
+						    (user_ctx);
+						status =
+						    sah_handle_registration
+						    (user_ctx);
+					}
+				}
+			}
+		}
+		break;
+
+		/* This ioctl cmd should disappear in favor of a close() routine.  */
+	case SAHARA_DEREGISTER:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_DEREGISTER IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			if (user_ctx == NULL) {
+				status = OS_ERROR_FAIL_S;
+			} else {
+				status = sah_handle_deregistration(user_ctx);
+				os_free_memory(user_ctx);
+				os_dev_set_user_private(NULL);
+			}
+		}
+		break;
+	case SAHARA_SCC_DROP_PERMS:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SCC_DROP_PERMS IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			/* drop permissions on the specified partition */
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_scc_drop_perms(user_ctx,
+						      os_dev_get_ioctl_arg());
+		}
+		break;
+
+	case SAHARA_SCC_SFREE:
+		/* Unmap the specified partition from the users space, and then
+		 * free it for use by someone else.
+		 */
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SCC_SFREE IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_scc_sfree(user_ctx,
+						 os_dev_get_ioctl_arg());
+		}
+		break;
+
+	case SAHARA_SCC_SSTATUS:
+		/* Unmap the specified partition from the users space, and then
+		 * free it for use by someone else.
+		 */
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SCC_SSTATUS IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_scc_sstatus(user_ctx,
+						   os_dev_get_ioctl_arg());
+		}
+		break;
+
+	case SAHARA_SCC_ENCRYPT:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SCC_ENCRYPT IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_scc_encrypt(user_ctx,
+						   os_dev_get_ioctl_arg());
+		}
+		break;
+
+	case SAHARA_SCC_DECRYPT:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SCC_DECRYPT IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_scc_decrypt(user_ctx,
+						   os_dev_get_ioctl_arg());
+		}
+		break;
+
+	case SAHARA_SK_ALLOC:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SK_ALLOC IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = sah_handle_sk_slot_alloc(os_dev_get_ioctl_arg());
+		break;
+
+	case SAHARA_SK_DEALLOC:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SK_DEALLOC IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = sah_handle_sk_slot_dealloc(os_dev_get_ioctl_arg());
+		break;
+
+	case SAHARA_SK_LOAD:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SK_LOAD IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = sah_handle_sk_slot_load(os_dev_get_ioctl_arg());
+		break;
+	case SAHARA_SK_READ:
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG("SAHARA_SK_READ IOCTL.");
+#endif				/* DIAG_DRV_IF */
+				status = sah_handle_sk_slot_read(os_dev_get_ioctl_arg());
+				break;
+
+	case SAHARA_SK_SLOT_DEC:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SK_SLOT_DECRYPT IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = sah_handle_sk_slot_decrypt(os_dev_get_ioctl_arg());
+		break;
+
+	case SAHARA_SK_SLOT_ENC:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_SK_SLOT_ENCRYPT IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = sah_handle_sk_slot_encrypt(os_dev_get_ioctl_arg());
+		break;
+	case SAHARA_GET_CAPS:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA_GET_CAPS IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		{
+			fsl_shw_uco_t *user_ctx = os_dev_get_user_private();
+
+			status =
+			    sah_handle_get_capabilities(user_ctx,
+							os_dev_get_ioctl_arg());
+		}
+		break;
+
+	default:
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("Unknown SAHARA IOCTL.");
+#endif				/* DIAG_DRV_IF */
+		status = OS_ERROR_FAIL_S;
+	}
+
+	os_dev_ioctl_return(status);
+}
+
+/* Fill in the user's capabilities structure */
+static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t * user_ctx,
+						 uint32_t info)
+{
+	os_error_code status = OS_ERROR_FAIL_S;
+	fsl_shw_pco_t capabilities;
+
+	status = os_copy_from_user(&capabilities, (void *)info,
+				   sizeof(fsl_shw_pco_t));
+
+	if (status != OS_ERROR_OK_S) {
+		goto out;
+	}
+
+	if (get_capabilities(user_ctx, &capabilities) == FSL_RETURN_OK_S) {
+		status = os_copy_to_user((void *)info, &capabilities,
+					 sizeof(fsl_shw_pco_t));
+	}
+
+      out:
+	return status;
+}
+
+#ifdef FSL_HAVE_SCC2
+
+/* Find the kernel-mode address of the partition.
+ * This can then be passed to the SCC functions.
+ */
+void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base)
+{
+	/* search through the partition chain to find one that matches the user base
+	 * address.
+	 */
+	fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition;
+
+	while (curr != NULL) {
+		if (curr->user_base == user_base) {
+			return curr->kernel_base;
+		}
+		curr = (fsl_shw_spo_t *) curr->next;
+	}
+	return NULL;
+}
+
+/* user_base: userspace base address of the partition
+ * kernel_base: kernel mode base address of the partition
+ */
+static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx,
+						uint32_t user_base,
+						void *kernel_base)
+{
+	fsl_shw_spo_t *partition_info;
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	if (user_ctx == NULL) {
+		goto out;
+	}
+
+	partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL);
+
+	if (partition_info == NULL) {
+		goto out;
+	}
+
+	/* stuff the partition info, then put it at the front of the chain */
+	partition_info->user_base = user_base;
+	partition_info->kernel_base = kernel_base;
+	partition_info->next = user_ctx->partition;
+
+	user_ctx->partition = (struct fsl_shw_spo_t *)partition_info;
+
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG_ARGS
+	    ("partition with user_base=%p, kernel_base=%p registered.",
+	     (void *)user_base, kernel_base);
+#endif
+
+	ret = FSL_RETURN_OK_S;
+
+      out:
+
+	return ret;
+}
+
+/* if the partition is in the users list, remove it */
+static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx,
+						  uint32_t user_base)
+{
+	fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition;
+	fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition;
+
+	while (curr != NULL) {
+		if (curr->user_base == user_base) {
+
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG_ARGS
+			    ("deregister_user_partition: partition with "
+			     "user_base=%p, kernel_base=%p deregistered.\n",
+			     (void *)curr->user_base, curr->kernel_base);
+#endif
+
+			if (last == curr) {
+				user_ctx->partition = curr->next;
+				os_free_memory(curr);
+				return FSL_RETURN_OK_S;
+			} else {
+				last->next = curr->next;
+				os_free_memory(curr);
+				return FSL_RETURN_OK_S;
+			}
+		}
+		last = curr;
+		curr = (fsl_shw_spo_t *) curr->next;
+	}
+
+	return FSL_RETURN_ERROR_S;
+}
+
+#endif				/* FSL_HAVE_SCC2 */
+
+static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx,
+					       uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	scc_return_t scc_ret;
+	scc_partition_info_t partition_info;
+	void *kernel_base;
+
+	status =
+	    os_copy_from_user(&partition_info, (void *)info,
+			      sizeof(partition_info));
+
+	if (status != OS_ERROR_OK_S) {
+		goto out;
+	}
+
+	/* validate that the user owns this partition, and look up its handle */
+	kernel_base = lookup_user_partition(user_ctx, partition_info.user_base);
+
+	if (kernel_base == NULL) {
+		status = OS_ERROR_FAIL_S;
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("_scc_drop_perms(): failed to find partition\n");
+#endif
+		goto out;
+	}
+
+	/* call scc driver to perform the drop */
+	scc_ret = scc_diminish_permissions(kernel_base,
+					   partition_info.permissions);
+	if (scc_ret == SCC_RET_OK) {
+		status = OS_ERROR_OK_S;
+	} else {
+		status = OS_ERROR_FAIL_S;
+	}
+
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t * user_ctx,
+					  uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		scc_partition_info_t partition_info;
+		void *kernel_base;
+		int ret;
+
+		status =
+		    os_copy_from_user(&partition_info, (void *)info,
+				      sizeof(partition_info));
+
+		/* check that the copy was successful */
+		if (status != OS_ERROR_OK_S) {
+			goto out;
+		}
+
+		/* validate that the user owns this partition, and look up its handle */
+		kernel_base =
+		    lookup_user_partition(user_ctx, partition_info.user_base);
+
+		if (kernel_base == NULL) {
+			status = OS_ERROR_FAIL_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("failed to find partition\n");
+#endif				/*DIAG_DRV_IF */
+			goto out;
+		}
+
+		/* Unmap the memory region (see sys_munmap in mmap.c) */
+		ret = unmap_user_memory(partition_info.user_base, 8192);
+
+		/* If the memory was successfully released */
+		if (ret == OS_ERROR_OK_S) {
+
+			/* release the partition */
+			scc_release_partition(kernel_base);
+
+			/* and remove it from the users context */
+			deregister_user_partition(user_ctx,
+						  partition_info.user_base);
+
+			status = OS_ERROR_OK_S;
+		}
+	}
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		scc_partition_info_t partition_info;
+		void *kernel_base;
+
+		status =
+		    os_copy_from_user(&partition_info, (void *)info,
+				      sizeof(partition_info));
+
+		/* check that the copy was successful */
+		if (status != OS_ERROR_OK_S) {
+			goto out;
+		}
+
+		/* validate that the user owns this partition, and look up its handle */
+		kernel_base =
+		    lookup_user_partition(user_ctx, partition_info.user_base);
+
+		if (kernel_base == NULL) {
+			status = OS_ERROR_FAIL_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("failed to find partition\n");
+#endif				/*DIAG_DRV_IF */
+			goto out;
+		}
+
+		partition_info.status = scc_partition_status(kernel_base);
+
+		status =
+		    os_copy_to_user((void *)info, &partition_info,
+				    sizeof(partition_info));
+	}
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+	return status;
+}
+
+static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code os_err = OS_ERROR_FAIL_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		fsl_shw_return_t retval;
+		scc_region_t region_info;
+		void *page_ctx = NULL;
+		void *black_addr = NULL;
+		void *partition_base = NULL;
+		scc_config_t *scc_configuration;
+
+		os_err =
+		    os_copy_from_user(&region_info, (void *)info,
+				      sizeof(region_info));
+
+		if (os_err != OS_ERROR_OK_S) {
+			goto out;
+		}
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG_ARGS
+		    ("partition_base: %p, offset: %i, length: %i, black data: %p",
+		     (void *)region_info.partition_base, region_info.offset,
+		     region_info.length, (void *)region_info.black_data);
+#endif
+
+		/* validate that the user owns this partition, and look up its handle */
+		partition_base = lookup_user_partition(user_ctx,
+						       region_info.
+						       partition_base);
+
+		if (partition_base == NULL) {
+			retval = FSL_RETURN_ERROR_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("failed to find secure partition\n");
+#endif
+			goto out;
+		}
+
+		/* Check that the memory size requested is correct */
+		scc_configuration = scc_get_configuration();
+		if (region_info.offset + region_info.length >
+		    scc_configuration->partition_size_bytes) {
+			retval = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+
+		/* wire down black data */
+		black_addr = wire_user_memory(region_info.black_data,
+					      region_info.length, &page_ctx);
+
+		if (black_addr == NULL) {
+			retval = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+
+		retval =
+		    do_scc_encrypt_region(NULL, partition_base,
+					  region_info.offset,
+					  region_info.length, black_addr,
+					  region_info.IV,
+					  region_info.cypher_mode);
+
+		/* release black data */
+		unwire_user_memory(&page_ctx);
+
+	      out:
+		if (os_err == OS_ERROR_OK_S) {
+			/* Return error code */
+			region_info.code = retval;
+			os_err =
+			    os_copy_to_user((void *)info, &region_info,
+					    sizeof(region_info));
+		}
+	}
+
+#endif
+	return os_err;
+}
+
+static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t * user_ctx,
+					    uint32_t info)
+{
+	os_error_code os_err = OS_ERROR_FAIL_S;
+#ifdef FSL_HAVE_SCC2
+	{
+		fsl_shw_return_t retval;
+		scc_region_t region_info;
+		void *page_ctx = NULL;
+		void *black_addr;
+		void *partition_base;
+		scc_config_t *scc_configuration;
+
+		os_err =
+		    os_copy_from_user(&region_info, (void *)info,
+				      sizeof(region_info));
+
+		if (os_err != OS_ERROR_OK_S) {
+			goto out;
+		}
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG_ARGS
+		    ("partition_base: %p, offset: %i, length: %i, black data: %p",
+		     (void *)region_info.partition_base, region_info.offset,
+		     region_info.length, (void *)region_info.black_data);
+#endif
+
+		/* validate that the user owns this partition, and look up its handle */
+		partition_base = lookup_user_partition(user_ctx,
+						       region_info.
+						       partition_base);
+
+		if (partition_base == NULL) {
+			retval = FSL_RETURN_ERROR_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("failed to find partition\n");
+#endif
+			goto out;
+		}
+
+		/* Check that the memory size requested is correct */
+		scc_configuration = scc_get_configuration();
+		if (region_info.offset + region_info.length >
+		    scc_configuration->partition_size_bytes) {
+			retval = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+
+		/* wire down black data */
+		black_addr = wire_user_memory(region_info.black_data,
+					      region_info.length, &page_ctx);
+
+		if (black_addr == NULL) {
+			retval = FSL_RETURN_ERROR_S;
+			goto out;
+		}
+
+		retval =
+		    do_scc_decrypt_region(NULL, partition_base,
+					  region_info.offset,
+					  region_info.length, black_addr,
+					  region_info.IV,
+					  region_info.cypher_mode);
+
+		/* release black data */
+		unwire_user_memory(&page_ctx);
+
+	      out:
+		if (os_err == OS_ERROR_OK_S) {
+			/* Return error code */
+			region_info.code = retval;
+			os_err =
+			    os_copy_to_user((void *)info, &region_info,
+					    sizeof(region_info));
+		}
+	}
+
+#endif				/* FSL_HAVE_SCC2 */
+	return os_err;
+}
+
+/*****************************************************************************/
+/* fn get_user_smid()                                                        */
+/*****************************************************************************/
+uint32_t get_user_smid(void *proc)
+{
+	/*
+	 * A real implementation would have some way to handle signed applications
+	 * which wouild be assigned distinct SMIDs.  For the reference
+	 * implementation, we show where this would be determined (here), but
+	 * always provide a fixed answer, thus not separating users at all.
+	 */
+
+	return 0x42eaae42;
+}
+
+/*!
+*******************************************************************************
+* This function implements the smalloc() function for userspace programs, by
+* making a call to the SCC2 mmap() function that acquires a region of secure
+* memory on behalf of the user, and then maps it into the users memory space.
+* Currently, the only memory size supported is that of a single SCC2 partition.
+* Requests for other sized memory regions will fail.
+*/
+OS_DEV_MMAP(sah_mmap)
+{
+	os_error_code status = OS_ERROR_NO_MEMORY_S;
+
+#ifdef FSL_HAVE_SCC2
+	{
+		scc_return_t scc_ret;
+		fsl_shw_return_t fsl_ret;
+		uint32_t partition_registered = FALSE;
+
+		uint32_t user_base;
+		void *partition_base;
+		uint32_t smid;
+		scc_config_t *scc_configuration;
+
+		int part_no = -1;
+		uint32_t part_phys;
+
+		fsl_shw_uco_t *user_ctx =
+		    (fsl_shw_uco_t *) os_dev_get_user_private();
+
+		/* Make sure that the user context is valid */
+		if (user_ctx == NULL) {
+			user_ctx =
+			    os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL);
+
+			if (user_ctx == NULL) {
+				status = OS_ERROR_NO_MEMORY_S;
+				goto out;
+			}
+
+			sah_handle_registration(user_ctx);
+			os_dev_set_user_private(user_ctx);
+		}
+
+		/* Determine the size of a secure partition */
+		scc_configuration = scc_get_configuration();
+
+		/* Check that the memory size requested is equal to the partition
+		 * size, and that the requested destination is on a page boundary.
+		 */
+		if (((os_mmap_user_base() % PAGE_SIZE) != 0) ||
+		    (os_mmap_memory_size() !=
+		     scc_configuration->partition_size_bytes)) {
+			status = OS_ERROR_BAD_ARG_S;
+			goto out;
+		}
+
+		/* Retrieve the SMID associated with the user */
+		smid = get_user_smid(user_ctx->process);
+
+		/* Attempt to allocate a secure partition */
+		scc_ret =
+		    scc_allocate_partition(smid, &part_no, &partition_base,
+					   &part_phys);
+		if (scc_ret != SCC_RET_OK) {
+			pr_debug
+			    ("SCC mmap() request failed to allocate partition;"
+			     " error %d\n", status);
+			status = OS_ERROR_FAIL_S;
+			goto out;
+		}
+
+		pr_debug("scc_mmap() acquired partition %d at %08x\n",
+			 part_no, part_phys);
+
+		/* Record partition info in the user context */
+		user_base = os_mmap_user_base();
+		fsl_ret =
+		    register_user_partition(user_ctx, user_base,
+					    partition_base);
+
+		if (fsl_ret != FSL_RETURN_OK_S) {
+			pr_debug
+			    ("SCC mmap() request failed to register partition with user"
+			     " context, error: %d\n", fsl_ret);
+			status = OS_ERROR_FAIL_S;
+		}
+
+		partition_registered = TRUE;
+
+		status = map_user_memory(os_mmap_memory_ctx(), part_phys,
+					 os_mmap_memory_size());
+
+#ifdef SHW_DEBUG
+		if (status == OS_ERROR_OK_S) {
+			LOG_KDIAG_ARGS
+			    ("Partition allocated: user_base=%p, partition_base=%p.",
+			     (void *)user_base, partition_base);
+		}
+#endif
+
+	      out:
+		/* If there is an error it has to be handled here */
+		if (status != OS_ERROR_OK_S) {
+			/* if the partition was registered with the user, unregister it. */
+			if (partition_registered == TRUE) {
+				deregister_user_partition(user_ctx, user_base);
+			}
+
+			/* if the partition was allocated, deallocate it */
+			if (partition_base != NULL) {
+				scc_release_partition(partition_base);
+			}
+		}
+	}
+#endif				/* FSL_HAVE_SCC2 */
+
+	return status;
+}
+
+/* Find the physical address of a key stored in the system keystore */
+fsl_shw_return_t
+system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot,
+			      uint32_t * address, uint32_t * slot_size_bytes)
+{
+	fsl_shw_return_t retval;
+	void *kernel_address;
+
+	/* First verify that the key access is valid */
+	retval = system_keystore.slot_verify_access(system_keystore.user_data,
+						    owner_id, slot);
+
+	if (retval != FSL_RETURN_OK_S) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("verification failed");
+#endif
+		return retval;
+	}
+
+	if (address != NULL) {
+#ifdef FSL_HAVE_SCC2
+		kernel_address =
+		    system_keystore.slot_get_address(system_keystore.user_data,
+						     slot);
+		(*address) = scc_virt_to_phys(kernel_address);
+#else
+		kernel_address =
+		    system_keystore.slot_get_address((void *)&owner_id, slot);
+		(*address) = (uint32_t) kernel_address;
+#endif
+	}
+
+	if (slot_size_bytes != NULL) {
+#ifdef FSL_HAVE_SCC2
+		*slot_size_bytes =
+		    system_keystore.slot_get_slot_size(system_keystore.
+						       user_data, slot);
+#else
+		*slot_size_bytes =
+		    system_keystore.slot_get_slot_size((void *)&owner_id, slot);
+#endif
+	}
+
+	return retval;
+}
+
+static os_error_code sah_handle_sk_slot_alloc(uint32_t info)
+{
+	scc_slot_t slot_info;
+	os_error_code os_err;
+	scc_return_t scc_ret;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+	if (os_err == OS_ERROR_OK_S) {
+		scc_ret = keystore_slot_alloc(&system_keystore,
+					      slot_info.key_length,
+					      slot_info.ownerid,
+					      &slot_info.slot);
+		if (scc_ret == SCC_RET_OK) {
+			slot_info.code = FSL_RETURN_OK_S;
+		} else if (scc_ret == SCC_RET_INSUFFICIENT_SPACE) {
+			slot_info.code = FSL_RETURN_NO_RESOURCE_S;
+		} else {
+			slot_info.code = FSL_RETURN_ERROR_S;
+		}
+
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG_ARGS("key length: %i, handle: %i\n",
+			       slot_info.key_length, slot_info.slot);
+#endif
+
+		/* Return error code and slot info */
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+
+		if (os_err != OS_ERROR_OK_S) {
+			(void)keystore_slot_dealloc(&system_keystore,
+						    slot_info.ownerid,
+						    slot_info.slot);
+		}
+	}
+
+	return os_err;
+}
+
+static os_error_code sah_handle_sk_slot_dealloc(uint32_t info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+	scc_slot_t slot_info;
+	os_error_code os_err;
+	scc_return_t scc_ret;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+
+	if (os_err == OS_ERROR_OK_S) {
+		scc_ret = keystore_slot_dealloc(&system_keystore,
+						slot_info.ownerid,
+						slot_info.slot);
+
+		if (scc_ret == SCC_RET_OK) {
+			ret = FSL_RETURN_OK_S;
+		} else {
+			ret = FSL_RETURN_ERROR_S;
+		}
+		slot_info.code = ret;
+
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+	}
+
+	return os_err;
+}
+
+static os_error_code sah_handle_sk_slot_load(uint32_t info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+	scc_slot_t slot_info;
+	os_error_code os_err;
+	uint8_t *key = NULL;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+
+	if (os_err == OS_ERROR_OK_S) {
+		/* Allow slop in alloc in case we are rounding up to word multiple */
+		key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL);
+		if (key == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+			os_err = OS_ERROR_NO_MEMORY_S;
+		} else {
+			os_err = os_copy_from_user(key, slot_info.key,
+						   slot_info.key_length);
+		}
+	}
+
+	if (os_err == OS_ERROR_OK_S) {
+		unsigned key_length = slot_info.key_length;
+
+		/* Round up if necessary, as SCC call wants a multiple of 32-bit
+		 * values for the full object being loaded. */
+		if ((key_length & 3) != 0) {
+			key_length += 4 - (key_length & 3);
+		}
+		ret = keystore_slot_load(&system_keystore,
+					 slot_info.ownerid, slot_info.slot, key,
+					 key_length);
+
+		slot_info.code = ret;
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+	}
+
+	if (key != NULL) {
+		memset(key, 0, slot_info.key_length);
+		os_free_memory(key);
+	}
+
+	return os_err;
+}
+
+static os_error_code sah_handle_sk_slot_read(uint32_t info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+	scc_slot_t slot_info;
+	os_error_code os_err;
+	uint8_t *key = NULL;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+
+	if (os_err == OS_ERROR_OK_S) {
+
+		/* This operation is not allowed for user keys */
+		slot_info.code = FSL_RETURN_NO_RESOURCE_S;
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+
+		return os_err;
+	}
+
+	if (os_err == OS_ERROR_OK_S) {
+		/* Allow slop in alloc in case we are rounding up to word multiple */
+		key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL);
+		if (key == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+			os_err = OS_ERROR_NO_MEMORY_S;
+		}
+	}
+
+	if (os_err == OS_ERROR_OK_S) {
+		unsigned key_length = slot_info.key_length;
+
+		/* @bug Do some PERMISSIONS checking - make sure this is SW key */
+
+		/* Round up if necessary, as SCC call wants a multiple of 32-bit
+		 * values for the full object being loaded. */
+		if ((key_length & 3) != 0) {
+			key_length += 4 - (key_length & 3);
+		}
+		ret = keystore_slot_read(&system_keystore,
+					 slot_info.ownerid, slot_info.slot,
+					 key_length, key);
+
+		/* @bug do some error checking */
+
+		/* Send key back to user */
+		os_err = os_copy_to_user(slot_info.key, key,
+					 slot_info.key_length);
+
+		slot_info.code = ret;
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+	}
+
+	if (key != NULL) {
+		memset(key, 0, slot_info.key_length);
+		os_free_memory(key);
+	}
+
+	return os_err;
+}
+
+static os_error_code sah_handle_sk_slot_encrypt(uint32_t info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+	scc_slot_t slot_info;
+	os_error_code os_err;
+	scc_return_t scc_ret;
+	uint8_t *key = NULL;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+
+	if (os_err == OS_ERROR_OK_S) {
+		key = os_alloc_memory(slot_info.key_length, GFP_KERNEL);
+		if (key == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+		}
+	}
+
+	if (key != NULL) {
+
+		scc_ret = keystore_slot_encrypt(NULL, &system_keystore,
+						slot_info.ownerid,
+						slot_info.slot,
+						slot_info.key_length, key);
+
+		if (scc_ret != SCC_RET_OK) {
+			ret = FSL_RETURN_ERROR_S;
+		} else {
+			os_err =
+			    os_copy_to_user(slot_info.key, key,
+					    slot_info.key_length);
+			if (os_err != OS_ERROR_OK_S) {
+				ret = FSL_RETURN_INTERNAL_ERROR_S;
+			} else {
+				ret = FSL_RETURN_OK_S;
+			}
+		}
+
+		slot_info.code = ret;
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+
+		memset(key, 0, slot_info.key_length);
+		os_free_memory(key);
+	}
+
+	return os_err;
+}
+
+static os_error_code sah_handle_sk_slot_decrypt(uint32_t info)
+{
+	fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S;
+	scc_slot_t slot_info;	/*!< decrypt request fields */
+	os_error_code os_err;
+	scc_return_t scc_ret;
+	uint8_t *key = NULL;
+
+	os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info));
+
+	if (os_err == OS_ERROR_OK_S) {
+		key = os_alloc_memory(slot_info.key_length, GFP_KERNEL);
+		if (key == NULL) {
+			ret = FSL_RETURN_NO_RESOURCE_S;
+			os_err = OS_ERROR_OK_S;
+		} else {
+			os_err = os_copy_from_user(key, slot_info.key,
+						   slot_info.key_length);
+		}
+	}
+
+	if (os_err == OS_ERROR_OK_S) {
+		scc_ret = keystore_slot_decrypt(NULL, &system_keystore,
+						slot_info.ownerid,
+						slot_info.slot,
+						slot_info.key_length, key);
+		if (scc_ret == SCC_RET_OK) {
+			ret = FSL_RETURN_OK_S;
+		} else {
+			ret = FSL_RETURN_ERROR_S;
+		}
+
+		slot_info.code = ret;
+		os_err =
+		    os_copy_to_user((void *)info, &slot_info,
+				    sizeof(slot_info));
+	}
+
+	if (key != NULL) {
+		memset(key, 0, slot_info.key_length);
+		os_free_memory(key);
+	}
+
+	return os_err;
+}
+
+/*!
+ * Register a user
+ *
+ * @brief Register a user
+  *
+ * @param  user_ctx  information about this user
+ *
+ * @return   status code
+ */
+fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t * user_ctx)
+{
+	/* Initialize the user's result pool (like sah_Queue_Construct() */
+	user_ctx->result_pool.head = NULL;
+	user_ctx->result_pool.tail = NULL;
+	user_ctx->result_pool.count = 0;
+
+	/* initialize the user's partition chain */
+	user_ctx->partition = NULL;
+
+	return FSL_RETURN_OK_S;
+}
+
+/*!
+ * Deregister a user
+ *
+ * @brief Deregister a user
+ *
+ * @param  user_ctx  information about this user
+ *
+ * @return   status code
+ */
+fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t * user_ctx)
+{
+	/* NOTE:
+	 * This will release any secure partitions that are held by the user.
+	 * Encryption keys that were placed in the system keystore by the user
+	 * should not be removed here, because they might have been shared with
+	 * another process.  The user must be careful to release any that are no
+	 * longer in use.
+	 */
+	fsl_shw_return_t ret = FSL_RETURN_OK_S;
+
+#ifdef FSL_HAVE_SCC2
+	fsl_shw_spo_t *partition;
+	struct mm_struct *mm = current->mm;
+
+	while ((user_ctx->partition != NULL) && (ret == FSL_RETURN_OK_S)) {
+
+		partition = user_ctx->partition;
+
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG_ARGS
+		    ("Found an abandoned secure partition at %p, releasing",
+		     partition);
+#endif
+
+		/* It appears that current->mm is not valid if this is called from a
+		 * close routine (perhaps only if the program raised an exception that
+		 * caused it to close?)  If that is the case, then still free the
+		 * partition, but do not remove it from the memory space (dangerous?)
+		 */
+
+		if (mm == NULL) {
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG
+			    ("Warning: no mm structure found, not unmapping "
+			     "partition from user memory\n");
+#endif
+		} else {
+			/* Unmap the memory region (see sys_munmap in mmap.c) */
+			/* Note that this assumes a single memory partition */
+			unmap_user_memory(partition->user_base, 8192);
+		}
+
+		/* If the memory was successfully released */
+		if (ret == OS_ERROR_OK_S) {
+			/* release the partition */
+			scc_release_partition(partition->kernel_base);
+
+			/* and remove it from the users context */
+			deregister_user_partition(user_ctx,
+						  partition->user_base);
+
+			ret = FSL_RETURN_OK_S;
+		} else {
+			ret = FSL_RETURN_ERROR_S;
+
+			goto out;
+		}
+	}
+      out:
+#endif				/* FSL_HAVE_SCC2 */
+
+	return ret;
+}
+
+/*!
+ * Sets up memory to extract results from results pool
+ *
+ * @brief Sets up memory to extract results from results pool
+ *
+ * @param  user_ctx  information about this user
+ * @param[in,out]   arg contains input parameters and fields that the driver
+ *                   fills in
+ *
+ * @return   os error code or 0 on success
+ */
+int sah_get_results_pointers(fsl_shw_uco_t * user_ctx, uint32_t arg)
+{
+	sah_results results_arg;	/* kernel mode usable version of 'arg' */
+	fsl_shw_result_t *user_results;	/* user mode address of results */
+	unsigned *user_actual;	/* user mode address of actual number of results */
+	unsigned actual;	/* local memory of actual number of results */
+	int ret_val = OS_ERROR_FAIL_S;
+	sah_Head_Desc *finished_request;
+	unsigned int loop;
+
+	/* copy structure from user to kernel space */
+	if (!os_copy_from_user(&results_arg, (void *)arg, sizeof(sah_results))) {
+		/* save user space pointers */
+		user_actual = results_arg.actual;	/* where count goes */
+		user_results = results_arg.results;	/* where results goe */
+
+		/* Set pointer for actual value to temporary kernel memory location */
+		results_arg.actual = &actual;
+
+		/* Allocate kernel memory to hold temporary copy of the results */
+		results_arg.results =
+		    os_alloc_memory(sizeof(fsl_shw_result_t) *
+				    results_arg.requested, GFP_KERNEL);
+
+		/* if memory allocated, continue */
+		if (results_arg.results == NULL) {
+			ret_val = OS_ERROR_NO_MEMORY_S;
+		} else {
+			fsl_shw_return_t get_status;
+
+			/* get the results */
+			get_status =
+			    sah_get_results_from_pool(user_ctx, &results_arg);
+
+			/* free the copy of the user space descriptor chain */
+			for (loop = 0; loop < actual; ++loop) {
+				/* get sah_Head_Desc from results and put user address into
+				 * the return structure */
+				finished_request =
+				    results_arg.results[loop].user_desc;
+				results_arg.results[loop].user_desc =
+				    finished_request->user_desc;
+				/* return the descriptor chain memory to the block free pool */
+				sah_Free_Chained_Descriptors(finished_request);
+			}
+
+			/* if no errors, copy results and then the actual number of results
+			 * back to user space
+			 */
+			if (get_status == FSL_RETURN_OK_S) {
+				if (os_copy_to_user
+				    (user_results, results_arg.results,
+				     actual * sizeof(fsl_shw_result_t))
+				    || os_copy_to_user(user_actual, &actual,
+						       sizeof(user_actual))) {
+					ret_val = OS_ERROR_FAIL_S;
+				} else {
+					ret_val = 0;	/* no error */
+				}
+			}
+			/* free the allocated memory */
+			os_free_memory(results_arg.results);
+		}
+	}
+
+	return ret_val;
+}
+
+/*!
+ * Extracts results from results pool
+ *
+ * @brief Extract results from results pool
+ *
+ * @param           user_ctx  information about this user
+ * @param[in,out]   arg       contains input parameters and fields that the
+ *                            driver fills in
+ *
+ * @return   status code
+ */
+fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t * user_ctx,
+					   sah_results * arg)
+{
+	sah_Head_Desc *finished_request;
+	unsigned int loop = 0;
+	os_lock_context_t int_flags;
+
+	/* Get the number of results requested, up to total number of results
+	 * available
+	 */
+	do {
+		/* Protect state of user's result pool until we have retrieved and
+		 * remove the first entry, or determined that the pool is empty. */
+		os_lock_save_context(desc_queue_lock, int_flags);
+		finished_request = user_ctx->result_pool.head;
+
+		if (finished_request != NULL) {
+			sah_Queue_Remove_Entry((sah_Queue *) & user_ctx->
+					       result_pool);
+			os_unlock_restore_context(desc_queue_lock, int_flags);
+
+			/* Prepare to free. */
+			(void)sah_DePhysicalise_Descriptors(finished_request);
+
+			arg->results[loop].user_ref =
+			    finished_request->user_ref;
+			arg->results[loop].code = finished_request->result;
+			arg->results[loop].detail1 =
+			    finished_request->fault_address;
+			arg->results[loop].detail2 = 0;
+			arg->results[loop].user_desc = finished_request;
+
+			loop++;
+		} else {	/* finished_request is NULL */
+			/* pool is empty */
+			os_unlock_restore_context(desc_queue_lock, int_flags);
+		}
+
+	} while ((loop < arg->requested) && (finished_request != NULL));
+
+	/* record number of results actually obtained */
+	*arg->actual = loop;
+
+	return FSL_RETURN_OK_S;
+}
+
+/*!
+ * Converts descriptor chain to kernel space (from user space) and submits
+ * chain to Sahara for processing
+ *
+ * @brief Submits converted descriptor chain to sahara
+ *
+ * @param  user_ctx        Pointer to Kernel version of user's ctx
+ * @param  user_space_desc user space address of descriptor chain that is
+ *                         in user space
+ *
+ * @return   OS status code
+ */
+static int handle_sah_ioctl_dar(fsl_shw_uco_t * user_ctx,
+				uint32_t user_space_desc)
+{
+	int os_error_code = OS_ERROR_FAIL_S;
+	sah_Head_Desc *desc_chain_head;	/* chain in kernel - virtual address */
+
+	/* This will re-create the linked list so that the SAHARA hardware can
+	 * DMA on it.
+	 */
+	desc_chain_head = sah_Copy_Descriptors(user_ctx,
+					       (sah_Head_Desc *)
+					       user_space_desc);
+
+	if (desc_chain_head == NULL) {
+		/* We may have failed due to a -EFAULT as well, but we will return
+		 * OS_ERROR_NO_MEMORY_S since either way it is a memory related
+		 * failure.
+		 */
+		os_error_code = OS_ERROR_NO_MEMORY_S;
+	} else {
+		fsl_shw_return_t stat;
+
+		desc_chain_head->user_info = user_ctx;
+		desc_chain_head->user_desc = (sah_Head_Desc *) user_space_desc;
+
+		if (desc_chain_head->uco_flags & FSL_UCO_BLOCKING_MODE) {
+#ifdef SAHARA_POLL_MODE
+			sah_Handle_Poll(desc_chain_head);
+#else
+			sah_blocking_mode(desc_chain_head);
+#endif
+			stat = desc_chain_head->result;
+			/* return the descriptor chain memory to the block free pool */
+			sah_Free_Chained_Descriptors(desc_chain_head);
+			/* Tell user how the call turned out */
+
+			/* Copy 'result' back up to the result member.
+			 *
+			 * The dereference of the different member will cause correct the
+			 * arithmetic to occur on the user-space address because of the
+			 * missing dma/bus locations in the user mode version of the
+			 * sah_Desc structure. */
+			os_error_code =
+			    os_copy_to_user((void *)(user_space_desc
+						     + offsetof(sah_Head_Desc,
+								uco_flags)),
+					    &stat, sizeof(fsl_shw_return_t));
+
+		} else {	/* not blocking mode - queue and forget */
+
+			if (desc_chain_head->uco_flags & FSL_UCO_CALLBACK_MODE) {
+				user_ctx->process = os_get_process_handle();
+				user_ctx->callback = sah_user_callback;
+			}
+#ifdef SAHARA_POLL_MODE
+			/* will put results in result pool */
+			sah_Handle_Poll(desc_chain_head);
+#else
+			/* just put someting in the DAR */
+			sah_Queue_Manager_Append_Entry(desc_chain_head);
+#endif
+			/* assume all went well */
+			os_error_code = OS_ERROR_OK_S;
+		}
+	}
+
+	return os_error_code;
+}
+
+static void sah_user_callback(fsl_shw_uco_t * user_ctx)
+{
+	os_send_signal(user_ctx->process, SIGUSR2);
+}
+
+/*!
+ * This function is called when a thread attempts to read from the /proc/sahara
+ * file.  Upon read, statistics and information about the state of the driver
+ * are returned in nthe supplied buffer.
+ *
+ * @brief     SAHARA PROCFS read function.
+ *
+ * @param    buf     Anything written to this buffer will be returned to the
+ *                   user-space process that is reading from this proc entry.
+ * @param    start   Part of the kernel prototype.
+ * @param    offset  Part of the kernel prototype.
+ * @param    count   The size of the buf argument.
+ * @param    eof     An integer which is set to one to tell the user-space
+ *                   process that there is no more data to read.
+ * @param    data    Part of the kernel prototype.
+ *
+ * @return   The number of bytes written to the proc entry.
+ */
+#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
+static int sah_read_procfs(char *buf,
+			   char **start,
+			   off_t offset, int count, int *eof, void *data)
+{
+	int output_bytes = 0;
+	int in_queue_count = 0;
+	os_lock_context_t lock_context;
+
+	os_lock_save_context(desc_queue_lock, lock_context);
+	in_queue_count = sah_Queue_Manager_Count_Entries(TRUE, 0);
+	os_unlock_restore_context(desc_queue_lock, lock_context);
+	output_bytes += snprintf(buf, count - output_bytes, "queued: %d\n",
+				 in_queue_count);
+	output_bytes += snprintf(buf + output_bytes, count - output_bytes,
+				 "Descriptors: %d, "
+				 "Interrupts %d (%d Done1Done2, %d Done1Busy2, "
+				 " %d Done1)\n",
+				 dar_count, interrupt_count, done1done2_count,
+				 done1busy2_count, done1_count);
+	output_bytes += snprintf(buf + output_bytes, count - output_bytes,
+				 "Control: %08x\n", sah_HW_Read_Control());
+#if !defined(FSL_HAVE_SAHARA4) || defined(SAHARA4_NO_USE_SQUIB)
+	output_bytes += snprintf(buf + output_bytes, count - output_bytes,
+				 "IDAR: %08x; CDAR: %08x\n",
+				 sah_HW_Read_IDAR(), sah_HW_Read_CDAR());
+#endif
+#ifdef DIAG_DRV_STATUS
+	output_bytes += snprintf(buf + output_bytes, count - output_bytes,
+				 "Status: %08x; Error Status: %08x; Op Status: %08x\n",
+				 sah_HW_Read_Status(),
+				 sah_HW_Read_Error_Status(),
+				 sah_HW_Read_Op_Status());
+#endif
+#ifdef FSL_HAVE_SAHARA4
+	output_bytes += snprintf(buf + output_bytes, count - output_bytes,
+				 "MMStat: %08x; Config: %08x\n",
+				 sah_HW_Read_MM_Status(), sah_HW_Read_Config());
+#endif
+
+	/* Signal the end of the file */
+	*eof = 1;
+
+	/* To get rid of the unused parameter warnings */
+	(void)start;
+	(void)data;
+	(void)offset;
+
+	return output_bytes;
+}
+
+static int sah_write_procfs(struct file *file, const char __user * buffer,
+			    unsigned long count, void *data)
+{
+
+	/* Any write to this file will reset all counts. */
+	dar_count = interrupt_count = done1done2_count =
+	    done1busy2_count = done1_count = 0;
+
+	(void)file;
+	(void)buffer;
+	(void)data;
+
+	return count;
+}
+
+#endif
+
+#ifndef SAHARA_POLL_MODE
+/*!
+ * Block user call until processing is complete.
+ *
+ * @param entry    The user's request.
+ *
+ * @return   An OS error code, or 0 if no error
+ */
+int sah_blocking_mode(sah_Head_Desc * entry)
+{
+	int os_error_code = 0;
+	sah_Queue_Status status;
+
+	/* queue entry, put something in the DAR, if nothing is there currently */
+	sah_Queue_Manager_Append_Entry(entry);
+
+	/* get this descriptor chain's current status */
+	status = ((volatile sah_Head_Desc *)entry)->status;
+
+	while (!SAH_DESC_PROCESSED(status)) {
+		extern sah_Queue *main_queue;
+
+		DEFINE_WAIT(sahara_wait);	/* create a wait queue entry. Linux */
+
+		/* enter the wait queue entry into the queue */
+		prepare_to_wait(&Wait_queue, &sahara_wait, TASK_INTERRUPTIBLE);
+
+		/* check if this entry has been processed */
+		status = ((volatile sah_Head_Desc *)entry)->status;
+
+		if (!SAH_DESC_PROCESSED(status)) {
+			/* go to sleep - Linux */
+			schedule();
+		}
+
+		/* un-queue the 'prepare to wait' queue? - Linux */
+		finish_wait(&Wait_queue, &sahara_wait);
+
+		/* signal belongs to this thread? */
+		if (signal_pending(current)) {	/* Linux */
+			os_lock_context_t lock_flags;
+
+			/* don't allow access during this check and operation */
+			os_lock_save_context(desc_queue_lock, lock_flags);
+			status = ((volatile sah_Head_Desc *)entry)->status;
+			if (status == SAH_STATE_PENDING) {
+				sah_Queue_Remove_Any_Entry(main_queue, entry);
+				entry->result = FSL_RETURN_INTERNAL_ERROR_S;
+				((volatile sah_Head_Desc *)entry)->status =
+				    SAH_STATE_FAILED;
+			}
+			os_unlock_restore_context(desc_queue_lock, lock_flags);
+		}
+
+		status = ((volatile sah_Head_Desc *)entry)->status;
+	}			/* while ... */
+
+	/* Do this so that caller can free */
+	(void)sah_DePhysicalise_Descriptors(entry);
+
+	return os_error_code;
+}
+
+/*!
+ * If interrupt does not return in a reasonable time, time out, trigger
+ * interrupt, and continue with process
+ *
+ * @param    data   ignored
+ */
+void sahara_timeout_handler(unsigned long data)
+{
+	/* Sahara has not issuing an interrupt, so timed out */
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG("Sahara HW did not respond.  Resetting.\n");
+#endif
+	/* assume hardware needs resetting */
+	sah_Handle_Interrupt(SAH_EXEC_FAULT);
+	/* wake up sleeping thread to try again */
+	wake_up_interruptible(&Wait_queue);
+}
+
+#endif				/* ifndef SAHARA_POLL_MODE */
+
+/* End of sah_driver_interface.c */
diff --git a/drivers/mxc/security/sahara2/sah_hardware_interface.c b/drivers/mxc/security/sahara2/sah_hardware_interface.c
new file mode 100644
index 000000000000..ff3cb987dc7f
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_hardware_interface.c
@@ -0,0 +1,808 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sah_hardware_interface.c
+ *
+ * @brief Provides an interface to the SAHARA hardware registers.
+ *
+ */
+
+/* SAHARA Includes */
+#include <sah_driver_common.h>
+#include <sah_hardware_interface.h>
+#include <sah_memory_mapper.h>
+#include <sah_kernel.h>
+
+#if defined DIAG_DRV_IF || defined(DO_DBG)
+#include <diagnostic.h>
+#ifndef LOG_KDIAG
+#define LOG_KDIAG(x) os_printk("%s\n", x)
+#endif
+
+static void sah_Dump_Link(const char *prefix, const sah_Link * link,
+			  dma_addr_t addr);
+
+/* This is for sprintf() to use when constructing output. */
+#define DIAG_MSG_SIZE   1024
+/* was 200 */
+#define MAX_DUMP        200
+static char Diag_msg[DIAG_MSG_SIZE];
+
+#endif				/* DIAG_DRV_IF */
+
+/*!
+ * Number of descriptors sent to Sahara.  This value should only be updated
+ * with the main queue lock held.
+ */
+uint32_t dar_count;
+
+/* sahara virtual base address */
+void *sah_virt_base;
+
+/*! The "link-list optimize" bit in the Header of a Descriptor */
+#define SAH_HDR_LLO 0x01000000
+
+#define SAHARA_VERSION_REGISTER_OFFSET  0x000
+#define SAHARA_DAR_REGISTER_OFFSET      0x004
+#define SAHARA_CONTROL_REGISTER_OFFSET  0x008
+#define SAHARA_COMMAND_REGISTER_OFFSET  0x00C
+#define SAHARA_STATUS_REGISTER_OFFSET   0x010
+#define SAHARA_ESTATUS_REGISTER_OFFSET  0x014
+#define SAHARA_FLT_ADD_REGISTER_OFFSET  0x018
+#define SAHARA_CDAR_REGISTER_OFFSET     0x01C
+#define SAHARA_IDAR_REGISTER_OFFSET     0x020
+#define SAHARA_OSTATUS_REGISTER_OFFSET  0x028
+#define SAHARA_CONFIG_REGISTER_OFFSET   0x02C
+#define SAHARA_MM_STAT_REGISTER_OFFSET  0x030
+
+
+/* Local Functions */
+#if defined DIAG_DRV_IF || defined DO_DBG
+void sah_Dump_Region(const char *prefix, const unsigned char *data,
+		     dma_addr_t addr, unsigned length);
+
+#endif				/* DIAG_DRV_IF */
+
+/* time out value when polling SAHARA status register for completion */
+static uint32_t sah_poll_timeout = 0xFFFFFFFF;
+
+/*!
+ * Polls Sahara to determine when its current operation is complete
+ *
+ * @return   last value found in Sahara's status register
+ */
+sah_Execute_Status sah_Wait_On_Sahara()
+{
+	uint32_t count = 0;	/* ensure we don't get stuck in the loop forever */
+	sah_Execute_Status status;	/* Sahara's status register */
+	uint32_t stat_reg;
+
+	pr_debug("Entered sah_Wait_On_Sahara\n");
+
+	do {
+		/* get current status register from Sahara */
+		stat_reg = sah_HW_Read_Status();
+		status = stat_reg & SAH_EXEC_STATE_MASK;
+
+		/* timeout if SAHARA takes too long to complete */
+		if (++count == sah_poll_timeout) {
+			status = SAH_EXEC_FAULT;
+			printk("sah_Wait_On_Sahara timed out\n");
+		}
+
+		/* stay in loop as long as Sahara is still busy */
+	} while ((status == SAH_EXEC_BUSY) || (status == SAH_EXEC_DONE1_BUSY2));
+
+	if (status == SAH_EXEC_ERROR1) {
+		if (stat_reg & OP_STATUS) {
+			status = SAH_EXEC_OPSTAT1;
+		}
+	}
+
+	return status;
+}				/* sah_Wait_on_Sahara() */
+
+/*!
+ * This function resets the SAHARA hardware. The following operations are
+ * performed:
+ *   1. Resets SAHARA.
+ *   2. Requests BATCH mode.
+ *   3. Enables interrupts.
+ *   4. Requests Little Endian mode.
+ *
+ * @brief     SAHARA hardware reset function.
+ *
+ * @return   void
+ */
+int sah_HW_Reset(void)
+{
+	sah_Execute_Status sah_state;
+	int status;		/* this is the value to return to the calling routine */
+	uint32_t saha_control = 0;
+
+#ifndef USE_3WORD_BURST
+#ifdef FSL_HAVE_SAHARA2
+	saha_control |= (8 << 16);	/* Allow 8-word burst */
+#endif
+#else
+/***************** HARDWARE BUG WORK AROUND ******************/
+/* A burst size of > 4 can cause Sahara DMA to issue invalid AHB transactions
+ * when crossing 1KB boundaries.  By limiting the 'burst size' to 3, these
+ * invalid transactions will not be generated, but Sahara will still transfer
+ * data more efficiently than if the burst size were set to 1.
+ */
+	saha_control |= (3 << 16);	/* Limit DMA burst size. For versions 2/3 */
+#endif				/* USE_3WORD_BURST */
+
+#ifdef DIAG_DRV_IF
+	snprintf(Diag_msg, DIAG_MSG_SIZE,
+		 "Address of sah_virt_base = 0x%08x\n",
+		 sah_virt_base);
+	LOG_KDIAG(Diag_msg);
+	snprintf(Diag_msg, DIAG_MSG_SIZE,
+		 "Sahara Status register before reset: %08x",
+		 sah_HW_Read_Status());
+	LOG_KDIAG(Diag_msg);
+#endif
+
+	/* Write the Reset & BATCH mode command to the SAHARA Command register. */
+	sah_HW_Write_Command(CMD_BATCH | CMD_RESET);
+#ifdef SAHARA4_NO_USE_SQUIB
+	{
+		uint32_t cfg = sah_HW_Read_Config();
+		cfg &= ~0x10000;
+		sah_HW_Write_Config(cfg);
+	}
+#endif
+
+	sah_poll_timeout = 0x0FFFFFFF;
+	sah_state = sah_Wait_On_Sahara();
+#ifdef DIAG_DRV_IF
+	snprintf(Diag_msg, DIAG_MSG_SIZE,
+		 "Sahara Status register after reset: %08x",
+		 sah_HW_Read_Status());
+	LOG_KDIAG(Diag_msg);
+#endif
+	/* on reset completion, check that Sahara is in the idle state */
+	status = (sah_state == SAH_EXEC_IDLE) ? 0 : OS_ERROR_FAIL_S;
+
+	/* Set initial value out of reset */
+	sah_HW_Write_Control(saha_control);
+
+#ifndef NO_RESEED_WORKAROUND
+/***************** HARDWARE BUG WORK AROUND ******************/
+/* In order to set the 'auto reseed' bit, must first acquire a random value. */
+	/*
+	 * to solve a hardware bug, a random number must be generated before
+	 * the 'RNG Auto Reseed' bit can be set. So this generates a random
+	 * number that is thrown away.
+	 *
+	 * Note that the interrupt bit has not been set at this point so
+	 * the result can be polled.
+	 */
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG("Create and submit Random Number Descriptor");
+#endif
+
+	if (status == OS_ERROR_OK_S) {
+		/* place to put random number */
+		volatile uint32_t *random_data_ptr;
+		sah_Head_Desc *random_desc;
+		dma_addr_t desc_dma;
+		dma_addr_t rand_dma;
+		const int rnd_cnt = 3;	/* how many random 32-bit values to get */
+
+		/* Get space for data -- assume at least 32-bit aligned! */
+		random_data_ptr = os_alloc_memory(rnd_cnt * sizeof(uint32_t),
+						  GFP_ATOMIC);
+
+		random_desc = sah_Alloc_Head_Descriptor();
+
+		if ((random_data_ptr == NULL) || (random_desc == NULL)) {
+			status = OS_ERROR_FAIL_S;
+		} else {
+			int i;
+
+			/* Clear out values */
+			for (i = 0; i < rnd_cnt; i++) {
+				random_data_ptr[i] = 0;
+			}
+
+			rand_dma = os_pa(random_data_ptr);
+
+			random_desc->desc.header = 0xB18C0000;	/* LLO get random number */
+			random_desc->desc.len1 =
+			    rnd_cnt * sizeof(*random_data_ptr);
+			random_desc->desc.ptr1 = (void *)rand_dma;
+			random_desc->desc.original_ptr1 =
+			    (void *)random_data_ptr;
+
+			random_desc->desc.len2 = 0;	/* not used */
+			random_desc->desc.ptr2 = 0;	/* not used */
+
+			random_desc->desc.next = 0;	/* chain terminates here */
+			random_desc->desc.original_next = 0;	/* chain terminates here */
+
+			desc_dma = random_desc->desc.dma_addr;
+
+			/* Force in-cache data out to RAM */
+			os_cache_clean_range(random_data_ptr,
+					     rnd_cnt *
+					     sizeof(*random_data_ptr));
+
+			/* pass descriptor to Sahara */
+			sah_HW_Write_DAR(desc_dma);
+
+			/*
+			 * Wait for RNG to complete (interrupts are disabled at this point
+			 * due to sahara being reset previously) then check for error
+			 */
+			sah_state = sah_Wait_On_Sahara();
+			/* Force CPU to ignore in-cache and reload from RAM */
+			os_cache_inv_range(random_data_ptr,
+					   rnd_cnt * sizeof(*random_data_ptr));
+
+			/* if it didn't move to done state, an error occured */
+			if (
+#ifndef SUBMIT_MULTIPLE_DARS
+				   (sah_state != SAH_EXEC_IDLE) &&
+#endif
+				   (sah_state != SAH_EXEC_DONE1)
+			    ) {
+				status = OS_ERROR_FAIL_S;
+				os_printk
+				    ("(sahara) Failure: state is %08x; random_data is"
+				     " %08x\n", sah_state, *random_data_ptr);
+				os_printk
+				    ("(sahara) CDAR: %08x, IDAR: %08x, FADR: %08x,"
+				     " ESTAT: %08x\n", sah_HW_Read_CDAR(),
+				     sah_HW_Read_IDAR(),
+				     sah_HW_Read_Fault_Address(),
+				     sah_HW_Read_Error_Status());
+			} else {
+				int i;
+				int seen_rand = 0;
+
+				for (i = 0; i < rnd_cnt; i++) {
+					if (*random_data_ptr != 0) {
+						seen_rand = 1;
+						break;
+					}
+				}
+				if (!seen_rand) {
+					status = OS_ERROR_FAIL_S;
+					os_printk
+					    ("(sahara) Error:  Random number is zero!\n");
+				}
+			}
+		}
+
+		if (random_data_ptr) {
+			os_free_memory((void *)random_data_ptr);
+		}
+		if (random_desc) {
+			sah_Free_Head_Descriptor(random_desc);
+		}
+	}
+/***************** END HARDWARE BUG WORK AROUND ******************/
+#endif
+
+	if (status == 0) {
+#ifdef FSL_HAVE_SAHARA2
+		saha_control |= CTRL_RNG_RESEED;
+#endif
+
+#ifndef SAHARA_POLL_MODE
+		saha_control |= CTRL_INT_EN;	/* enable interrupts */
+#else
+		sah_poll_timeout = SAHARA_POLL_MODE_TIMEOUT;
+#endif
+
+#ifdef DIAG_DRV_IF
+		snprintf(Diag_msg, DIAG_MSG_SIZE,
+			 "Setting up Sahara's Control Register: %08x\n",
+			 saha_control);
+		LOG_KDIAG(Diag_msg);
+#endif
+
+		/* Rewrite the setup to the SAHARA Control register */
+		sah_HW_Write_Control(saha_control);
+#ifdef DIAG_DRV_IF
+		snprintf(Diag_msg, DIAG_MSG_SIZE,
+			 "Sahara Status register after control write: %08x",
+			 sah_HW_Read_Status());
+		LOG_KDIAG(Diag_msg);
+#endif
+
+#ifdef FSL_HAVE_SAHARA4
+		{
+			uint32_t cfg = sah_HW_Read_Config();
+			sah_HW_Write_Config(cfg | 0x100);	/* Add RNG auto-reseed */
+		}
+#endif
+	} else {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("Reset failed\n");
+#endif
+	}
+
+	return status;
+}				/* sah_HW_Reset() */
+
+/*!
+ * This function enables High Assurance mode.
+ *
+ * @brief     SAHARA hardware enable High Assurance mode.
+ *
+ * @return   FSL_RETURN_OK_S             - if HA was set successfully
+ * @return   FSL_RETURN_INTERNAL_ERROR_S - if HA was not set due to SAHARA
+ *                                         being busy.
+ */
+fsl_shw_return_t sah_HW_Set_HA(void)
+{
+	/* This is the value to write to the register */
+	uint32_t value;
+
+	/* Read from the control register. */
+	value = sah_HW_Read_Control();
+
+	/* Set the HA bit */
+	value |= CTRL_HA;
+
+	/* Write to the control register. */
+	sah_HW_Write_Control(value);
+
+	/* Read from the control register. */
+	value = sah_HW_Read_Control();
+
+	return (value & CTRL_HA) ? FSL_RETURN_OK_S :
+	    FSL_RETURN_INTERNAL_ERROR_S;
+}
+
+/*!
+ * This function reads the SAHARA hardware Version Register.
+ *
+ * @brief     Read SAHARA hardware Version Register.
+ *
+ * @return   uint32_t Register value.
+ */
+uint32_t sah_HW_Read_Version(void)
+{
+	return os_read32(sah_virt_base + SAHARA_VERSION_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Control Register.
+ *
+ * @brief     Read SAHARA hardware Control Register.
+ *
+ * @return   uint32_t Register value.
+ */
+uint32_t sah_HW_Read_Control(void)
+{
+	return os_read32(sah_virt_base + SAHARA_CONTROL_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Status Register.
+ *
+ * @brief     Read SAHARA hardware Status Register.
+ *
+ * @return   uint32_t Register value.
+ */
+uint32_t sah_HW_Read_Status(void)
+{
+	return os_read32(sah_virt_base + SAHARA_STATUS_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Error Status Register.
+ *
+ * @brief     Read SAHARA hardware Error Status Register.
+ *
+ * @return   uint32_t Error Status value.
+ */
+uint32_t sah_HW_Read_Error_Status(void)
+{
+	return os_read32(sah_virt_base + SAHARA_ESTATUS_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Op Status Register.
+ *
+ * @brief     Read SAHARA hardware Op Status Register.
+ *
+ * @return   uint32_t Op Status value.
+ */
+uint32_t sah_HW_Read_Op_Status(void)
+{
+	return os_read32(sah_virt_base + SAHARA_OSTATUS_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Descriptor Address Register.
+ *
+ * @brief     Read SAHARA hardware DAR Register.
+ *
+ * @return   uint32_t DAR value.
+ */
+uint32_t sah_HW_Read_DAR(void)
+{
+	return os_read32(sah_virt_base + SAHARA_DAR_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Current Descriptor Address Register.
+ *
+ * @brief     Read SAHARA hardware CDAR Register.
+ *
+ * @return   uint32_t CDAR value.
+ */
+uint32_t sah_HW_Read_CDAR(void)
+{
+	return os_read32(sah_virt_base + SAHARA_CDAR_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Initial Descriptor Address Register.
+ *
+ * @brief     Read SAHARA hardware IDAR Register.
+ *
+ * @return   uint32_t IDAR value.
+ */
+uint32_t sah_HW_Read_IDAR(void)
+{
+	return os_read32(sah_virt_base + SAHARA_IDAR_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Fault Address Register.
+ *
+ * @brief     Read SAHARA Fault Address Register.
+ *
+ * @return   uint32_t Fault Address value.
+ */
+uint32_t sah_HW_Read_Fault_Address(void)
+{
+	return os_read32(sah_virt_base + SAHARA_FLT_ADD_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Multiple Master Status Register.
+ *
+ * @brief     Read SAHARA hardware MM Stat Register.
+ *
+ * @return   uint32_t MM Stat value.
+ */
+uint32_t sah_HW_Read_MM_Status(void)
+{
+	return os_read32(sah_virt_base + SAHARA_MM_STAT_REGISTER_OFFSET);
+}
+
+/*!
+ * This function reads the SAHARA hardware Configuration Register.
+ *
+ * @brief     Read SAHARA Configuration Register.
+ *
+ * @return   uint32_t Configuration value.
+ */
+uint32_t sah_HW_Read_Config(void)
+{
+	return os_read32(sah_virt_base + SAHARA_CONFIG_REGISTER_OFFSET);
+}
+
+/*!
+ * This function writes a command to the SAHARA hardware Command Register.
+ *
+ * @brief     Write to SAHARA hardware Command Register.
+ *
+ * @param    command     An unsigned 32bit command value.
+ *
+ * @return   void
+ */
+void sah_HW_Write_Command(uint32_t command)
+{
+	os_write32(sah_virt_base + SAHARA_COMMAND_REGISTER_OFFSET, command);
+}
+
+/*!
+ * This function writes a control value to the SAHARA hardware Control
+ * Register.
+ *
+ * @brief     Write to SAHARA hardware Control Register.
+ *
+ * @param    control     An unsigned 32bit control value.
+ *
+ * @return   void
+ */
+void sah_HW_Write_Control(uint32_t control)
+{
+	os_write32(sah_virt_base + SAHARA_CONTROL_REGISTER_OFFSET, control);
+}
+
+/*!
+ * This function writes a configuration value to the SAHARA hardware Configuration
+ * Register.
+ *
+ * @brief     Write to SAHARA hardware Configuration Register.
+ *
+ * @param    configuration     An unsigned 32bit configuration value.
+ *
+ * @return   void
+ */
+void sah_HW_Write_Config(uint32_t configuration)
+{
+	os_write32(sah_virt_base + SAHARA_CONFIG_REGISTER_OFFSET,
+		configuration);
+}
+
+/*!
+ * This function writes a descriptor address to the SAHARA Descriptor Address
+ * Register.
+ *
+ * @brief     Write to SAHARA Descriptor Address Register.
+ *
+ * @param    pointer     An unsigned 32bit descriptor address value.
+ *
+ * @return   void
+ */
+void sah_HW_Write_DAR(uint32_t pointer)
+{
+	os_write32(sah_virt_base + SAHARA_DAR_REGISTER_OFFSET, pointer);
+	dar_count++;
+}
+
+#if defined DIAG_DRV_IF || defined DO_DBG
+
+static char *interpret_header(uint32_t header)
+{
+	unsigned desc_type = ((header >> 24) & 0x70) | ((header >> 16) & 0xF);
+
+	switch (desc_type) {
+	case 0x12:
+		return "5/SKHA_ST_CTX";
+	case 0x13:
+		return "35/SKHA_LD_MODE_KEY";
+	case 0x14:
+		return "38/SKHA_LD_MODE_IN_CPHR_ST_CTX";
+	case 0x15:
+		return "4/SKHA_IN_CPHR_OUT";
+	case 0x16:
+		return "34/SKHA_ST_SBOX";
+	case 0x18:
+		return "1/SKHA_LD_MODE_IV_KEY";
+	case 0x19:
+		return "33/SKHA_ST_SBOX";
+	case 0x1D:
+		return "2/SKHA_LD_MODE_IN_CPHR_OUT";
+	case 0x22:
+		return "11/MDHA_ST_MD";
+	case 0x25:
+		return "10/MDHA_HASH_ST_MD";
+	case 0x28:
+		return "6/MDHA_LD_MODE_MD_KEY";
+	case 0x2A:
+		return "39/MDHA_ICV";
+	case 0x2D:
+		return "8/MDHA_LD_MODE_HASH_ST_MD";
+	case 0x3C:
+		return "18/RNG_GEN";
+	case 0x40:
+		return "19/PKHA_LD_N_E";
+	case 0x41:
+		return "36/PKHA_LD_A3_B0";
+	case 0x42:
+		return "27/PKHA_ST_A_B";
+	case 0x43:
+		return "22/PKHA_LD_A_B";
+	case 0x44:
+		return "23/PKHA_LD_A0_A1";
+	case 0x45:
+		return "24/PKHA_LD_A2_A3";
+	case 0x46:
+		return "25/PKHA_LD_B0_B1";
+	case 0x47:
+		return "26/PKHA_LD_B2_B3";
+	case 0x48:
+		return "28/PKHA_ST_A0_A1";
+	case 0x49:
+		return "29/PKHA_ST_A2_A3";
+	case 0x4A:
+		return "30/PKHA_ST_B0_B1";
+	case 0x4B:
+		return "31/PKHA_ST_B2_B3";
+	case 0x4C:
+		return "32/PKHA_EX_ST_B1";
+	case 0x4D:
+		return "20/PKHA_LD_A_EX_ST_B";
+	case 0x4E:
+		return "21/PKHA_LD_N_EX_ST_B";
+	case 0x4F:
+		return "37/PKHA_ST_B1_B2";
+	default:
+		return "??/UNKNOWN";
+	}
+}				/* cvt_desc_name() */
+
+/*!
+ * Dump chain of descriptors to the log.
+ *
+ * @brief Dump descriptor chain
+ *
+ * @param    chain     Kernel virtual address of start of chain of descriptors
+ *
+ * @return   void
+ */
+void sah_Dump_Chain(const sah_Desc * chain, dma_addr_t addr)
+{
+	int desc_no = 1;
+
+	pr_debug("Chain for Sahara\n");
+
+	while (chain != NULL) {
+		char desc_name[50];
+
+		sprintf(desc_name, "Desc %02d (%s)\n" KERN_DEBUG "Desc  ",
+			desc_no++, interpret_header(chain->header));
+
+		sah_Dump_Words(desc_name, (unsigned *)chain, addr,
+			       6 /* #words in h/w link */ );
+		if (chain->original_ptr1) {
+			if (chain->header & SAH_HDR_LLO) {
+				sah_Dump_Region(" Data1",
+						(unsigned char *)chain->
+						original_ptr1,
+						(dma_addr_t) chain->ptr1,
+						chain->len1);
+			} else {
+				sah_Dump_Link(" Link1", chain->original_ptr1,
+					      (dma_addr_t) chain->ptr1);
+			}
+		}
+		if (chain->ptr2) {
+			if (chain->header & SAH_HDR_LLO) {
+				sah_Dump_Region(" Data2",
+						(unsigned char *)chain->
+						original_ptr2,
+						(dma_addr_t) chain->ptr2,
+						chain->len2);
+			} else {
+				sah_Dump_Link(" Link2", chain->original_ptr2,
+					      (dma_addr_t) chain->ptr2);
+			}
+		}
+
+		addr = (dma_addr_t) chain->next;
+		chain = (chain->next) ? (chain->original_next) : NULL;
+	}
+}
+
+/*!
+ * Dump chain of links to the log.
+ *
+ * @brief Dump chain of links
+ *
+ * @param    prefix    Text to put in front of dumped data
+ * @param    link      Kernel virtual address of start of chain of links
+ *
+ * @return   void
+ */
+static void sah_Dump_Link(const char *prefix, const sah_Link * link,
+			  dma_addr_t addr)
+{
+#ifdef DUMP_SCC_DATA
+	extern uint8_t *sahara_partition_base;
+	extern dma_addr_t sahara_partition_phys;
+#endif
+
+	while (link != NULL) {
+		sah_Dump_Words(prefix, (unsigned *)link, addr,
+			       3 /* # words in h/w link */ );
+		if (link->flags & SAH_STORED_KEY_INFO) {
+#ifdef SAH_DUMP_DATA
+#ifdef DUMP_SCC_DATA
+			sah_Dump_Region("  Data",
+					(uint8_t *) link->data -
+					(uint8_t *) sahara_partition_phys +
+					sahara_partition_base,
+					(dma_addr_t) link->data, link->len);
+#else
+			pr_debug("  Key Slot %d\n", link->slot);
+#endif
+#endif
+		} else {
+#ifdef SAH_DUMP_DATA
+			sah_Dump_Region("  Data", link->original_data,
+					(dma_addr_t) link->data, link->len);
+#endif
+		}
+		addr = (dma_addr_t) link->next;
+		link = link->original_next;
+	}
+}
+
+/*!
+ * Dump given region of data to the log.
+ *
+ * @brief Dump data
+ *
+ * @param    prefix    Text to put in front of dumped data
+ * @param    data      Kernel virtual address of start of region to dump
+ * @param    length    Amount of data to dump
+ *
+ * @return   void
+ */
+void sah_Dump_Region(const char *prefix, const unsigned char *data,
+		     dma_addr_t addr, unsigned length)
+{
+	unsigned count;
+	char *output;
+	unsigned data_len;
+
+	sprintf(Diag_msg, "%s (%08X,%u):", prefix, addr, length);
+
+	/* Restrict amount of data to dump */
+	if (length > MAX_DUMP) {
+		data_len = MAX_DUMP;
+	} else {
+		data_len = length;
+	}
+
+	/* We've already printed some text in output buffer, skip over it */
+	output = Diag_msg + strlen(Diag_msg);
+
+	for (count = 0; count < data_len; count++) {
+		if ((count % 4) == 0) {
+			*output++ = ' ';
+		}
+		sprintf(output, "%02X", *data++);
+		output += 2;
+	}
+
+	pr_debug("%s\n", Diag_msg);
+}
+
+/*!
+ * Dump given word of data to the log.
+ *
+ * @brief Dump data
+ *
+ * @param    prefix       Text to put in front of dumped data
+ * @param    data         Kernel virtual address of start of region to dump
+ * @param    word_count   Amount of data to dump
+ *
+ * @return   void
+ */
+void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr,
+		    unsigned word_count)
+{
+	char *output;
+
+	sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, addr, word_count);
+
+	/* We've already printed some text in output buffer, skip over it */
+	output = Diag_msg + strlen(Diag_msg);
+
+	while (word_count--) {
+		sprintf(output, "%08X ", *data++);
+		output += 9;
+	}
+
+	pr_debug("%s\n", Diag_msg);
+
+}
+
+#endif				/* DIAG_DRV_IF */
+
+/* End of sah_hardware_interface.c */
diff --git a/drivers/mxc/security/sahara2/sah_interrupt_handler.c b/drivers/mxc/security/sahara2/sah_interrupt_handler.c
new file mode 100644
index 000000000000..3d70fe8d2c64
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_interrupt_handler.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sah_interrupt_handler.c
+*
+* @brief Provides a hardware interrupt handling mechanism for device driver.
+*
+* This file needs to be ported for a non-Linux OS.
+*
+* It gets a call at #sah_Intr_Init() during initialization.
+*
+* #sah_Intr_Top_Half() is intended to be the Interrupt Service Routine.  It
+* calls a portable function in another file to process the Sahara status.
+*
+* #sah_Intr_Bottom_Half() is a 'background' task scheduled by the top half to
+* take care of the expensive tasks of the interrupt processing.
+*
+* The driver shutdown code calls #sah_Intr_Release().
+*
+*/
+
+#include <portable_os.h>
+
+/* SAHARA Includes */
+#include <sah_kernel.h>
+#include <sah_interrupt_handler.h>
+#include <sah_status_manager.h>
+#include <sah_hardware_interface.h>
+#include <sah_queue_manager.h>
+
+/*Enable this flag for debugging*/
+#if 0
+#define DIAG_DRV_INTERRUPT
+#endif
+
+#ifdef DIAG_DRV_INTERRUPT
+#include <diagnostic.h>
+#endif
+
+/*!
+ * Number of interrupts received.  This value should only be updated during
+ * interrupt processing.
+ */
+uint32_t interrupt_count;
+
+#ifndef SAHARA_POLL_MODE
+
+#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#define irqreturn_t void
+#define IRQ_HANDLED
+#define IRQ_RETVAL(x)
+#endif
+
+/* Internal Prototypes */
+static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id);
+
+#ifdef KERNEL_TEST
+extern void (*SAHARA_INT_PTR) (int, void *);
+#endif
+
+unsigned long reset_flag;
+static void sah_Intr_Bottom_Half(unsigned long reset_flag);
+
+/* This is the Bottom Half Task, (reset flag set to false) */
+DECLARE_TASKLET(BH_task, sah_Intr_Bottom_Half, (unsigned long)&reset_flag);
+
+/*! This is set by the Initialisation function */
+wait_queue_head_t *int_queue = NULL;
+
+/*!
+*******************************************************************************
+* This function registers the Top Half of the interrupt handler with the Kernel
+* and the SAHARA IRQ number.
+*
+* @brief     SAHARA Interrupt Handler Initialisation
+*
+* @param    wait_queue Pointer to the wait queue used by driver interface
+*
+* @return   int A return of Zero indicates successful initialisation.
+*/
+/******************************************************************************
+*
+* CAUTION: NONE
+*
+* MODIFICATION HISTORY:
+*
+* Date         Person     Change
+* 30/07/2003   MW         Initial Creation
+******************************************************************************/
+int sah_Intr_Init(wait_queue_head_t * wait_queue)
+{
+
+#ifdef DIAG_DRV_INTERRUPT
+	char err_string[200];
+#endif
+
+	int result;
+
+#ifdef KERNEL_TEST
+	SAHARA_INT_PTR = sah_Intr_Top_Half;
+#endif
+
+	/* Set queue used by the interrupt handler to match the driver interface */
+	int_queue = wait_queue;
+
+	/* Request use of the Interrupt line. */
+	result = request_irq(SAHARA_IRQ,
+			     sah_Intr_Top_Half, 0, SAHARA_NAME, NULL);
+
+#ifdef DIAG_DRV_INTERRUPT
+	if (result != 0) {
+		sprintf(err_string, "Cannot use SAHARA interrupt line %d. "
+			"request_irq() return code is %i.", SAHARA_IRQ, result);
+		LOG_KDIAG(err_string);
+	} else {
+		sprintf(err_string,
+			"SAHARA driver registered for interrupt %d. ",
+			SAHARA_IRQ);
+		LOG_KDIAG(err_string);
+	}
+#endif
+
+	return result;
+}
+
+/*!
+*******************************************************************************
+* This function releases the Top Half of the interrupt handler. The driver will
+* not receive any more interrupts after calling this functions.
+*
+* @brief     SAHARA Interrupt Handler Release
+*
+* @return   void
+*/
+/******************************************************************************
+*
+* CAUTION: NONE
+*
+* MODIFICATION HISTORY:
+*
+* Date         Person     Change
+* 30/07/2003   MW         Initial Creation
+******************************************************************************/
+void sah_Intr_Release(void)
+{
+	/* Release the Interrupt. */
+	free_irq(SAHARA_IRQ, NULL);
+}
+
+/*!
+*******************************************************************************
+* This function is the Top Half of the interrupt handler.  It updates the
+* status of any finished descriptor chains and then tries to add any pending
+* requests into the hardware.  It then queues the bottom half to complete
+* operations on the finished chains.
+*
+* @brief     SAHARA Interrupt Handler Top Half
+*
+* @param    irq     Part of the kernel prototype.
+* @param    dev_id  Part of the kernel prototype.
+*
+* @return   An IRQ_RETVAL() -- non-zero to that function means 'handled'
+*/
+static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id)
+{
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+	LOG_KDIAG("Top half of Sahara's interrupt handler called.");
+#endif
+
+	interrupt_count++;
+	reset_flag = sah_Handle_Interrupt(sah_HW_Read_Status());
+
+	/* Schedule the Bottom Half of the Interrupt. */
+	tasklet_schedule(&BH_task);
+
+	/* To get rid of the unused parameter warnings. */
+	irq = 0;
+	dev_id = NULL;
+	return IRQ_RETVAL(1);
+}
+
+/*!
+*******************************************************************************
+* This function is the Bottom Half of the interrupt handler.  It calls
+* #sah_postprocess_queue() to complete the processing of the Descriptor Chains
+* which were finished by the hardware.
+*
+* @brief     SAHARA Interrupt Handler Bottom Half
+*
+* @param    data   Part of the kernel prototype.
+*
+* @return   void
+*/
+static void sah_Intr_Bottom_Half(unsigned long reset_flag)
+{
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+	LOG_KDIAG("Bottom half of Sahara's interrupt handler called.");
+#endif
+	sah_postprocess_queue(*(unsigned long *)reset_flag);
+
+	return;
+}
+
+/* end of sah_interrupt_handler.c */
+#endif				/* ifndef SAHARA_POLL_MODE */
diff --git a/drivers/mxc/security/sahara2/sah_memory_mapper.c b/drivers/mxc/security/sahara2/sah_memory_mapper.c
new file mode 100644
index 000000000000..2e3b80b14873
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_memory_mapper.c
@@ -0,0 +1,2356 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sah_memory_mapper.c
+*
+* @brief Re-creates SAHARA data structures in Kernel memory such that they are
+*       suitable for DMA.  Provides support for kernel API.
+*
+* This file needs to be ported.
+*
+* The memory mapper gets a call at #sah_Init_Mem_Map() during driver
+* initialization.
+*
+* The routine #sah_Copy_Descriptors() is used to bring descriptor chains from
+* user memory down to kernel memory, relink using physical addresses, and make
+* sure that all user data will be accessible by the Sahara DMA.
+* #sah_Destroy_Descriptors() does the inverse.
+*
+* The #sah_Alloc_Block(), #sah_Free_Block(), and #sah_Block_Add_Page() routines
+* implement a cache of free blocks used when allocating descriptors and links
+* within the kernel.
+*
+* The memory mapper gets a call at #sah_Stop_Mem_Map() during driver shutdown.
+*
+*/
+
+#include <sah_driver_common.h>
+#include <sah_kernel.h>
+#include <sah_queue_manager.h>
+#include <sah_memory_mapper.h>
+#ifdef FSL_HAVE_SCC2
+#include <linux/mxc_scc2_driver.h>
+#else
+#include <linux/mxc_scc_driver.h>
+#endif
+
+#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DO_DBG)
+#include <diagnostic.h>
+#include <sah_hardware_interface.h>
+#endif
+
+#include <linux/mm.h>		/* get_user_pages() */
+#include <linux/pagemap.h>
+#include <linux/dmapool.h>
+
+#include <linux/slab.h>
+#include <linux/highmem.h>
+
+#if defined(DIAG_MEM) || defined(DIAG_DRV_IF)
+#define DIAG_MSG_SIZE   1024
+static char Diag_msg[DIAG_MSG_SIZE];
+#endif
+
+#ifdef LINUX_VERSION_CODE
+#define FLUSH_SPECIFIC_DATA_ONLY
+#else
+#define SELF_MANAGED_POOL
+#endif
+
+#if defined(LINUX_VERSION_CODE)
+EXPORT_SYMBOL(sah_Alloc_Link);
+EXPORT_SYMBOL(sah_Free_Link);
+EXPORT_SYMBOL(sah_Alloc_Descriptor);
+EXPORT_SYMBOL(sah_Free_Descriptor);
+EXPORT_SYMBOL(sah_Alloc_Head_Descriptor);
+EXPORT_SYMBOL(sah_Free_Head_Descriptor);
+EXPORT_SYMBOL(sah_Physicalise_Descriptors);
+EXPORT_SYMBOL(sah_DePhysicalise_Descriptors);
+#endif
+
+/* Determine if L2 cache support should be built in. */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21))
+#ifdef CONFIG_OUTER_CACHE
+#define HAS_L2_CACHE
+#endif
+#else
+#ifdef CONFIG_CPU_CACHE_L210
+#define HAS_L2_CACHE
+#endif
+#endif
+
+/* Number of bytes the hardware uses out of sah_Link and sah_*Desc structs */
+#define SAH_HW_LINK_LEN  1
+#define SAH_HW_DESC_LEN  24
+
+/* Macros for Descriptors */
+#define SAH_LLO_BIT 0x01000000
+#define sah_Desc_Get_LLO(desc)          (desc->header & SAH_LLO_BIT)
+#define sah_Desc_Set_Header(desc, h)    (desc->header = (h))
+
+#define sah_Desc_Get_Next(desc)     (desc->next)
+#define sah_Desc_Set_Next(desc, n)  (desc->next = (n))
+
+#define sah_Desc_Get_Ptr1(desc)     (desc->ptr1)
+#define sah_Desc_Get_Ptr2(desc)     (desc->ptr2)
+#define sah_Desc_Set_Ptr1(desc,p1)  (desc->ptr1 = (p1))
+#define sah_Desc_Set_Ptr2(desc,p2)  (desc->ptr2 = (p2))
+
+#define sah_Desc_Get_Len1(desc)     (desc->len1)
+#define sah_Desc_Get_Len2(desc)     (desc->len2)
+#define sah_Desc_Set_Len1(desc,l1)  (desc->len1 = (l1))
+#define sah_Desc_Set_Len2(desc,l2)  (desc->len2 = (l2))
+
+/* Macros for Links */
+#define sah_Link_Get_Next(link)     (link->next)
+#define sah_Link_Set_Next(link, n)  (link->next = (n))
+
+#define sah_Link_Get_Data(link)     (link->data)
+#define sah_Link_Set_Data(link,d)   (link->data = (d))
+
+#define sah_Link_Get_Len(link)      (link->len)
+#define sah_Link_Set_Len(link, l)   (link->len = (l))
+
+#define sah_Link_Get_Flags(link)    (link->flags)
+
+/* Memory block defines */
+/* Warning!  This assumes that kernel version of sah_Link
+ * is larger than kernel version of sah_Desc.
+ */
+#define MEM_BLOCK_SIZE sizeof(sah_Link)
+
+/*! Structure for  link/descriptor memory blocks in internal pool */
+typedef struct mem_block {
+	uint8_t data[MEM_BLOCK_SIZE];	/*!< the actual buffer area  */
+	struct mem_block *next;	/*!< next block when in free chain */
+	dma_addr_t dma_addr;	/*!< physical address of @a data  */
+} Mem_Block;
+
+#define MEM_BLOCK_ENTRIES  (PAGE_SIZE / sizeof(Mem_Block))
+
+#define MEM_BIG_BLOCK_SIZE     sizeof(sah_Head_Desc)
+
+/*! Structure for head descriptor memory blocks in internal pool */
+typedef struct mem_big_block {
+	uint8_t data[MEM_BIG_BLOCK_SIZE];	/*!< the actual buffer area  */
+	struct mem_big_block *next;	/*!< next block when in free chain */
+	uint32_t dma_addr;	/*!< physical address of @a data  */
+} Mem_Big_Block;
+
+#define MEM_BIG_BLOCK_ENTRIES  (PAGE_SIZE / sizeof(Mem_Big_Block))
+
+/* Shared variables */
+
+/*!
+ * Lock to protect the memory chain composed of #block_free_head and
+ * #block_free_tail.
+ */
+static os_lock_t mem_lock;
+
+#ifndef SELF_MANAGED_POOL
+static struct dma_pool *big_dma_pool = NULL;
+static struct dma_pool *small_dma_pool = NULL;
+#endif
+
+#ifdef SELF_MANAGED_POOL
+/*!
+ * Memory block free pool - pointer to first block.  Chain is protected by
+ * #mem_lock.
+ */
+static Mem_Block *block_free_head = NULL;
+/*!
+ * Memory block free pool - pointer to last block.  Chain is protected by
+ * #mem_lock.
+ */
+static Mem_Block *block_free_tail = NULL;
+/*!
+ * Memory block free pool - pointer to first block.  Chain is protected by
+ * #mem_lock.
+ */
+static Mem_Big_Block *big_block_free_head = NULL;
+/*!
+ * Memory block free pool - pointer to last block.  Chain is protected by
+ * #mem_lock.
+a */
+static Mem_Big_Block *big_block_free_tail = NULL;
+#endif				/* SELF_MANAGED_POOL */
+
+static Mem_Block *sah_Alloc_Block(void);
+static void sah_Free_Block(Mem_Block * block);
+static Mem_Big_Block *sah_Alloc_Big_Block(void);
+static void sah_Free_Big_Block(Mem_Big_Block * block);
+#ifdef SELF_MANAGED_POOL
+static void sah_Append_Block(Mem_Block * block);
+static void sah_Append_Big_Block(Mem_Big_Block * block);
+#endif				/* SELF_MANAGED_POOL */
+
+/* Page context structure.  Used by wire_user_memory and unwire_user_memory */
+typedef struct page_ctx_t {
+	uint32_t count;
+	struct page **local_pages;
+} page_ctx_t;
+
+/*!
+*******************************************************************************
+* Map and wire down a region of user memory.
+*
+*
+* @param    address     Userspace address of the memory to wire
+* @param    length      Length of the memory region to wire
+* @param    page_ctx    Page context, to be passed to unwire_user_memory
+*
+* @return   (if successful) Kernel virtual address of the wired pages
+*/
+void *wire_user_memory(void *address, uint32_t length, void **page_ctx)
+{
+	void *kernel_black_addr = NULL;
+	int result = -1;
+	int page_index = 0;
+	page_ctx_t *page_context;
+	int nr_pages = 0;
+	unsigned long start_page;
+	fsl_shw_return_t status;
+
+	/* Determine the number of pages being used for this link */
+	nr_pages = (((unsigned long)(address) & ~PAGE_MASK)
+		    + length + ~PAGE_MASK) >> PAGE_SHIFT;
+
+	start_page = (unsigned long)(address) & PAGE_MASK;
+
+	/* Allocate some memory to keep track of the wired user pages, so that
+	 * they can be deallocated later.  The block of memory will contain both
+	 * the structure and the array of pages.
+	 */
+	page_context = kmalloc(sizeof(page_ctx_t)
+			       + nr_pages * sizeof(struct page *), GFP_KERNEL);
+
+	if (page_context == NULL) {
+		status = FSL_RETURN_NO_RESOURCE_S;	/* no memory! */
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("kmalloc() failed.");
+#endif
+		return NULL;
+	}
+
+	/* Set the page pointer to point to the allocated region of memory */
+	page_context->local_pages = (void *)page_context + sizeof(page_ctx_t);
+
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p",
+		       (void *)page_context,
+		       (void *)(page_context->local_pages));
+#endif
+
+	/* Wire down the pages from user space */
+	down_read(&current->mm->mmap_sem);
+	result = get_user_pages(current, current->mm,
+				start_page, nr_pages, WRITE, 0 /* noforce */ ,
+				(page_context->local_pages), NULL);
+	up_read(&current->mm->mmap_sem);
+
+	if (result < nr_pages) {
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("get_user_pages() failed.");
+#endif
+		if (result > 0) {
+			for (page_index = 0; page_index < result; page_index++) {
+				page_cache_release((page_context->
+						    local_pages[page_index]));
+			}
+
+			kfree(page_context);
+		}
+		return NULL;
+	}
+
+	kernel_black_addr = page_address(page_context->local_pages[0]) +
+	    ((unsigned long)address & ~PAGE_MASK);
+
+	page_context->count = nr_pages;
+	*page_ctx = page_context;
+
+	return kernel_black_addr;
+}
+
+/*!
+*******************************************************************************
+* Release and unmap a region of user memory.
+*
+* @param    page_ctx    Page context from wire_user_memory
+*/
+void unwire_user_memory(void **page_ctx)
+{
+	int page_index = 0;
+	struct page_ctx_t *page_context = *page_ctx;
+
+#ifdef DIAG_DRV_IF
+	LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i",
+		       (void *)page_context,
+		       (void *)(page_context->local_pages),
+		       page_context->count);
+#endif
+
+	if ((page_context != NULL) && (page_context->local_pages != NULL)) {
+		for (page_index = 0; page_index < page_context->count;
+		     page_index++) {
+			page_cache_release(page_context->
+					   local_pages[page_index]);
+		}
+
+		kfree(page_context);
+		*page_ctx = NULL;
+	}
+}
+
+/*!
+*******************************************************************************
+* Map some physical memory into a users memory space
+*
+* @param    vma             Memory structure to map to
+* @param    physical_addr   Physical address of the memory to be mapped in
+* @param    size            Size of the memory to map (bytes)
+*
+* @return
+*/
+os_error_code
+map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr,
+		uint32_t size)
+{
+	os_error_code retval;
+
+	/* Map the acquired partition into the user's memory space */
+	vma->vm_end = vma->vm_start + size;
+
+	/* set cache policy to uncached so that each write of the UMID and
+	 * permissions get directly to the SCC2 in order to engage it
+	 * properly.  Once the permissions have been written, it may be
+	 * useful to provide a service for the user to request a different
+	 * cache policy
+	 */
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* Make sure that the user cannot fork() a child which will inherit
+	 * this mapping, as it creates a security hole.  Likewise, do not
+	 * allow the user to 'expand' his mapping beyond this partition.
+	 */
+	vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND;
+
+	retval = remap_pfn_range(vma,
+				 vma->vm_start,
+				 __phys_to_pfn(physical_addr),
+				 size, vma->vm_page_prot);
+
+	return retval;
+}
+
+/*!
+*******************************************************************************
+* Remove some memory from a user's memory space
+*
+* @param    user_addr       Userspace address of the memory to be unmapped
+* @param    size            Size of the memory to map (bytes)
+*
+* @return
+*/
+os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size)
+{
+	os_error_code retval;
+	struct mm_struct *mm = current->mm;
+
+	/* Unmap the memory region (see sys_munmap in mmap.c) */
+	down_write(&mm->mmap_sem);
+	retval = do_munmap(mm, (unsigned long)user_addr, size);
+	up_write(&mm->mmap_sem);
+
+	return retval;
+}
+
+/*!
+*******************************************************************************
+* Free descriptor back to free pool
+*
+* @brief Free descriptor
+*
+* @param    desc        A descriptor allocated with sah_Alloc_Descriptor().
+*
+* @return none
+*
+*/
+void sah_Free_Descriptor(sah_Desc * desc)
+{
+	memset(desc, 0x45, sizeof(*desc));
+	sah_Free_Block((Mem_Block *) desc);
+}
+
+/*!
+*******************************************************************************
+* Free Head descriptor back to free pool
+*
+* @brief Free Head descriptor
+*
+* @param    desc  A Head descriptor allocated with sah_Alloc_Head_Descriptor().
+*
+* @return none
+*
+*/
+void sah_Free_Head_Descriptor(sah_Head_Desc * desc)
+{
+	memset(desc, 0x43, sizeof(*desc));
+	sah_Free_Big_Block((Mem_Big_Block *) desc);
+}
+
+/*!
+*******************************************************************************
+* Free link back to free pool
+*
+* @brief Free link
+*
+* @param    link        A link allocated with sah_Alloc_Link().
+*
+* @return none
+*
+*/
+void sah_Free_Link(sah_Link * link)
+{
+	memset(link, 0x41, sizeof(*link));
+	sah_Free_Block((Mem_Block *) link);
+}
+
+/*!
+*******************************************************************************
+* This function runs through a descriptor chain pointed to by a user-space
+* address. It duplicates each descriptor in Kernel space memory and calls
+* sah_Copy_Links() to handle any links attached to the descriptors. This
+* function cleans-up everything that it created in the case of a failure.
+*
+* @brief Kernel Descriptor Chain Copier
+*
+* @param    fsl_shw_uco_t  The user context to act under
+* @param    user_head_desc A Head Descriptor pointer from user-space.
+*
+* @return   sah_Head_Desc *  - A virtual address of the first descriptor in the
+*                              chain.
+* @return   NULL        - If there was some error.
+*
+*/
+sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx,
+				sah_Head_Desc * user_head_desc)
+{
+	sah_Desc *curr_desc = NULL;
+	sah_Desc *prev_desc = NULL;
+	sah_Desc *next_desc = NULL;
+	sah_Head_Desc *head_desc = NULL;
+	sah_Desc *user_desc = NULL;
+	unsigned long result;
+
+	/* Internal status variable to be used in this function */
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+	sah_Head_Desc *ret_val = NULL;
+
+	/* This will be set to True when we have finished processing our
+	 * descriptor chain.
+	 */
+	int drv_if_done = FALSE;
+	int is_this_the_head = TRUE;
+
+	do {
+		/* Allocate memory for this descriptor */
+		if (is_this_the_head) {
+			head_desc =
+			    (sah_Head_Desc *) sah_Alloc_Head_Descriptor();
+
+#ifdef DIAG_MEM
+			sprintf(Diag_msg,
+				"Alloc_Head_Descriptor returned %p\n",
+				head_desc);
+			LOG_KDIAG(Diag_msg);
+#endif
+			if (head_desc == NULL) {
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG
+				    ("sah_Alloc_Head_Descriptor() failed.");
+#endif
+				drv_if_done = TRUE;
+				status = FSL_RETURN_NO_RESOURCE_S;
+			} else {
+				void *virt_addr = head_desc->desc.virt_addr;
+				dma_addr_t dma_addr = head_desc->desc.dma_addr;
+
+				/* Copy the head descriptor from user-space */
+				/* Instead of copying the whole structure,
+				 * unneeded bits at the end are left off.
+				 * The user space version is missing virt/dma addrs, which
+				 * means that the copy will be off for flags... */
+				result = copy_from_user(head_desc,
+							user_head_desc,
+							(sizeof(*head_desc) -
+							 sizeof(head_desc->desc.
+								dma_addr) -
+							 sizeof(head_desc->desc.
+								virt_addr) -
+							 sizeof(head_desc->desc.
+								original_ptr1) -
+/*                                sizeof(head_desc->desc.original_ptr2) -
+                                sizeof(head_desc->status) -
+                                sizeof(head_desc->error_status) -
+                                sizeof(head_desc->fault_address) -
+                                sizeof(head_desc->current_dar) -
+                                sizeof(head_desc->result) -
+                                sizeof(head_desc->next) -
+                                sizeof(head_desc->prev) -
+                                sizeof(head_desc->user_desc) -
+*/ sizeof(head_desc->out1_ptr) -
+							 sizeof(head_desc->
+								out2_ptr) -
+							 sizeof(head_desc->
+								out_len)));
+				/* there really isn't a 'next' descriptor at this point, so
+				 * set that pointer to NULL, but remember it for if/when there
+				 * is a next */
+				next_desc = head_desc->desc.next;
+				head_desc->desc.next = NULL;
+
+				if (result != 0) {
+#ifdef DIAG_DRV_IF
+					LOG_KDIAG("copy_from_user() failed.");
+#endif
+					drv_if_done = TRUE;
+					status = FSL_RETURN_INTERNAL_ERROR_S;
+					/* when destroying the descriptor, skip these links.
+					 * They've not been copied down, so don't exist */
+					head_desc->desc.ptr1 = NULL;
+					head_desc->desc.ptr2 = NULL;
+
+				} else {
+					/* The kernel DESC has five more words than user DESC, so
+					 * the missing values are in the middle of the HEAD DESC,
+					 * causing values after the missing ones to be at different
+					 * offsets in kernel and user space.
+					 *
+					 * Patch up the problem by moving field two spots.
+					 * This assumes sizeof(pointer) == sizeof(uint32_t).
+					 * Note that 'user_info' is not needed, so not copied.
+					 */
+					head_desc->user_ref =
+					    (uint32_t) head_desc->desc.dma_addr;
+					head_desc->uco_flags =
+					    (uint32_t) head_desc->desc.
+					    original_ptr1;
+#ifdef DIAG_DRV_IF
+					LOG_KDIAG_ARGS(
+						"User flags: %x; User Reference: %x",
+						head_desc->uco_flags,
+						head_desc->user_ref);
+#endif
+					/* These values were destroyed by the copy. */
+					head_desc->desc.virt_addr = virt_addr;
+					head_desc->desc.dma_addr = dma_addr;
+
+					/* ensure that the save descriptor chain bit is not set.
+					 * the copy of the user space descriptor chain should
+					 * always be deleted */
+					head_desc->uco_flags &=
+					    ~FSL_UCO_SAVE_DESC_CHAIN;
+
+					curr_desc = (sah_Desc *) head_desc;
+					is_this_the_head = FALSE;
+				}
+			}
+		} else {	/* not head */
+			curr_desc = sah_Alloc_Descriptor();
+#ifdef DIAG_MEM
+			LOG_KDIAG_ARGS("Alloc_Descriptor returned %p\n",
+				curr_desc);
+#endif
+			if (curr_desc == NULL) {
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG("sah_Alloc_Descriptor() failed.");
+#endif
+				drv_if_done = TRUE;
+				status = FSL_RETURN_NO_RESOURCE_S;
+			} else {
+				/* need to update the previous descriptors' next field to
+				 * pointer to the current descriptor. */
+				prev_desc->original_next = curr_desc;
+				prev_desc->next =
+				    (sah_Desc *) curr_desc->dma_addr;
+
+				/* Copy the current descriptor from user-space */
+				/* The virtual address and DMA address part of the sah_Desc
+				 * struct are not copied to user space */
+				result = copy_from_user(curr_desc, user_desc, (sizeof(sah_Desc) - sizeof(dma_addr_t) -	/* dma_addr */
+									       sizeof(uint32_t) -	/* virt_addr */
+									       sizeof(void *) -	/* original_ptr1 */
+									       sizeof(void *) -	/* original_ptr2 */
+									       sizeof(sah_Desc **)));	/* original_next */
+				/* there really isn't a 'next' descriptor at this point, so
+				 * set that pointer to NULL, but remember it for if/when there
+				 * is a next */
+				next_desc = curr_desc->next;
+				curr_desc->next = NULL;
+				curr_desc->original_next = NULL;
+
+				if (result != 0) {
+#ifdef DIAG_DRV_IF
+					LOG_KDIAG("copy_from_user() failed.");
+#endif
+					drv_if_done = TRUE;
+					status = FSL_RETURN_INTERNAL_ERROR_S;
+					/* when destroying the descriptor chain, skip these links.
+					 * They've not been copied down, so don't exist */
+					curr_desc->ptr1 = NULL;
+					curr_desc->ptr2 = NULL;
+				}
+			}
+		}		/* end if (is_this_the_head) */
+
+		if (status == FSL_RETURN_OK_S) {
+			if (!(curr_desc->header & SAH_LLO_BIT)) {
+				/* One or both pointer fields being NULL is a valid
+				 * configuration. */
+				if (curr_desc->ptr1 == NULL) {
+					curr_desc->original_ptr1 = NULL;
+				} else {
+					/* pointer fields point to sah_Link structures */
+					curr_desc->original_ptr1 =
+					    sah_Copy_Links(user_ctx, curr_desc->ptr1);
+					if (curr_desc->original_ptr1 == NULL) {
+						/* This descriptor and any links created successfully
+						 * are cleaned-up at the bottom of this function. */
+						drv_if_done = TRUE;
+						status =
+						    FSL_RETURN_INTERNAL_ERROR_S;
+						/* mark that link 2 doesn't exist */
+						curr_desc->ptr2 = NULL;
+#ifdef DIAG_DRV_IF
+						LOG_KDIAG
+						    ("sah_Copy_Links() failed.");
+#endif
+					} else {
+						curr_desc->ptr1 = (void *)
+						    ((sah_Link *) curr_desc->
+						     original_ptr1)->dma_addr;
+					}
+				}
+
+				if (status == FSL_RETURN_OK_S) {
+					if (curr_desc->ptr2 == NULL) {
+						curr_desc->original_ptr2 = NULL;
+					} else {
+						/* pointer fields point to sah_Link structures */
+						curr_desc->original_ptr2 =
+						    sah_Copy_Links(user_ctx, curr_desc->ptr2);
+						if (curr_desc->original_ptr2 ==
+						    NULL) {
+							/* This descriptor and any links created
+							 * successfully are cleaned-up at the bottom of
+							 * this function. */
+							drv_if_done = TRUE;
+							status =
+							    FSL_RETURN_INTERNAL_ERROR_S;
+#ifdef DIAG_DRV_IF
+							LOG_KDIAG
+							    ("sah_Copy_Links() failed.");
+#endif
+						} else {
+							curr_desc->ptr2 =
+							    (void
+							     *)(((sah_Link *)
+								 curr_desc->
+								 original_ptr2)
+								->dma_addr);
+						}
+					}
+				}
+			} else {
+				/* Pointer fields point directly to user buffers. We don't
+				 * support this mode.
+				 */
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG
+				    ("The LLO bit in the Descriptor Header field was "
+				     "set. This an invalid configuration.");
+#endif
+				drv_if_done = TRUE;
+				status = FSL_RETURN_INTERNAL_ERROR_S;
+			}
+		}
+
+		if (status == FSL_RETURN_OK_S) {
+			user_desc = next_desc;
+			prev_desc = curr_desc;
+			if (user_desc == NULL) {
+				/* We have reached the end our our descriptor chain */
+				drv_if_done = TRUE;
+			}
+		}
+
+	} while (drv_if_done == FALSE);
+
+	if (status != FSL_RETURN_OK_S) {
+		/* Clean-up if failed */
+		if (head_desc != NULL) {
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("Error!  Calling destroy descriptors!\n");
+#endif
+			sah_Destroy_Descriptors(head_desc);
+		}
+		ret_val = NULL;
+	} else {
+		/* Flush the caches */
+#ifndef FLUSH_SPECIFIC_DATA_ONLY
+		os_flush_cache_all();
+#endif
+
+		/* Success. Return the DMA'able head descriptor. */
+		ret_val = head_desc;
+
+	}
+
+	return ret_val;
+}				/* sah_Copy_Descriptors() */
+
+/*!
+*******************************************************************************
+* This function runs through a sah_Link chain pointed to by a kernel-space
+* address.  It computes the physical address for each pointer, and converts
+* the chain to use these physical addresses.
+*
+******
+*   This function needs to return some indication that the chain could not be
+*   converted.  It also needs to back out any conversion already taken place on
+*   this chain of links.
+*
+*   Then, of course, sah_Physicalise_Descriptors() will need to recognize that
+*   an error occured, and then be able to back out any physicalization of the
+*   chain which had taken place up to that point!
+******
+*
+* @brief Convert kernel Link chain
+*
+* @param    first_link   A sah_Link pointer from kernel space; must not be
+*                        NULL, so error case can be distinguished.
+*
+* @return   sah_Link *   A dma'able address of the first descriptor in the
+*                         chain.
+* @return   NULL         If Link chain could not be physicalised, i.e. ERROR
+*
+*/
+sah_Link *sah_Physicalise_Links(sah_Link * first_link)
+{
+	sah_Link *link = first_link;
+
+	while (link != NULL) {
+#ifdef DO_DBG
+		sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3);
+#endif
+		link->vm_info = NULL;
+
+		/* need to retrieve stored key? */
+		if (link->flags & SAH_STORED_KEY_INFO) {
+			uint32_t max_len = 0;	/* max slot length */
+			fsl_shw_return_t ret_status;
+
+			/* get length and physical address of stored key */
+			ret_status = system_keystore_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data,	/* RED key address */
+						       &max_len);
+			if ((ret_status != FSL_RETURN_OK_S) || (link->len > max_len)) {
+				/* trying to illegally/incorrectly access a key. Cause the
+				 * error status register to show a Link Length Error by
+				 * putting a zero in the links length. */
+				link->len = 0;	/* Cause error.  Somebody is up to no good. */
+			}
+		} else if (link->flags & SAH_IN_USER_KEYSTORE) {
+
+#ifdef FSL_HAVE_SCC2
+			/* The data field points to the virtual address of the key.  Convert
+			 * this to a physical address by modifying the address based
+			 * on where the secure memory was mapped to the kernel.  Note: In
+			 * kernel mode, no attempt is made to track or control who owns what
+			 * memory partition.
+			 */
+			link->data = (uint8_t *) scc_virt_to_phys(link->data);
+
+			/* Do bounds checking to ensure that the user is not overstepping
+			 * the bounds of their partition.  This is a simple implementation
+			 * that assumes the user only owns one partition.  It only checks
+			 * to see if the address of the last byte of data steps over a
+			 * page boundary.
+			 */
+
+#ifdef DO_DBG
+			LOG_KDIAG_ARGS("start page: %08x, end page: %08x"
+				       "first addr: %p, last addr: %p, len; %i",
+				       ((uint32_t) (link->data) >> PAGE_SHIFT),
+				       (((uint32_t) link->data +
+					 link->len) >> PAGE_SHIFT), link->data,
+				       link->data + link->len, link->len);
+#endif
+
+			if ((((uint32_t) link->data +
+			      link->len) >> PAGE_SHIFT) !=
+			    ((uint32_t) link->data >> PAGE_SHIFT)) {
+				link->len = 0;	/* Cause error.  Somebody is up to no good. */
+			}
+#else				/* FSL_HAVE_SCC2 */
+
+			/* User keystores are not valid on non-SCC2 platforms */
+			link->len = 0;	/* Cause error.  Somebody is up to no good. */
+
+#endif				/* FSL_HAVE_SCC2 */
+
+		} else {
+			if (!(link->flags & SAH_PREPHYS_DATA)) {
+				link->original_data = link->data;
+
+				/* All pointers are virtual right now */
+				link->data = (void *)os_pa(link->data);
+#ifdef DO_DBG
+				os_printk("%sput: %p (%d)\n",
+					  (link->
+					   flags & SAH_OUTPUT_LINK) ? "out" :
+					  "in", link->data, link->len);
+#endif
+
+				if (link->flags & SAH_OUTPUT_LINK) {
+					/* clean and invalidate */
+					os_cache_flush_range(link->
+							     original_data,
+							     link->len);
+				} else {
+					os_cache_clean_range(link->original_data,
+							     link->len);
+				}
+			}	/* not prephys */
+		}		/* else not key reference */
+
+#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING)
+		if (
+#ifdef NO_OUTPUT_1K_CROSSING
+			   /* Insert extra link if 1k boundary on output pointer
+			    * crossed not at an 8-word boundary */
+			   (link->flags & SAH_OUTPUT_LINK) &&
+			   (((uint32_t) link->data % 32) != 0) &&
+#endif
+			   ((((uint32_t) link->data & 1023) + link->len) >
+			    1024)) {
+			uint32_t full_length = link->len;
+			sah_Link *new_link = sah_Alloc_Link();
+			link->len = 1024 - ((uint32_t) link->data % 1024);
+			new_link->len = full_length - link->len;
+			new_link->data = link->data + link->len;
+			new_link->original_data =
+			    link->original_data + link->len;
+			new_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA);
+			new_link->flags |= SAH_LINK_INSERTED_LINK;
+			new_link->next = link->next;
+
+			link->next = (sah_Link *) new_link->dma_addr;
+			link->original_next = new_link;
+			link = new_link;
+		}
+#endif				/* ALLOW_OUTPUT_1K_CROSSING */
+
+		link->original_next = link->next;
+		if (link->next != NULL) {
+			link->next = (sah_Link *) link->next->dma_addr;
+		}
+#ifdef DO_DBG
+		sah_Dump_Words("Link", link, link->dma_addr, 3);
+#endif
+
+		link = link->original_next;
+	}
+
+	return (sah_Link *) first_link->dma_addr;
+}				/* sah_Physicalise_Links */
+
+/*!
+ * Run through descriptors and links created by KM-API and set the
+ * dma addresses and 'do not free' flags.
+ *
+ * @param first_desc  KERNEL VIRTUAL address of first descriptor in chain.
+ *
+ * Warning!  This ONLY works without LLO flags in headers!!!
+ *
+ * @return Virtual address of @a first_desc.
+ * @return NULL if Descriptor Chain could not be physicalised
+ */
+sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * first_desc)
+{
+	sah_Desc *desc = &first_desc->desc;
+
+	if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) {
+		while (desc != NULL) {
+			sah_Desc *next_desc;
+
+#ifdef DO_DBG
+
+			sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6);
+#endif
+
+			desc->original_ptr1 = desc->ptr1;
+			if (desc->ptr1 != NULL) {
+				if ((desc->ptr1 =
+				     sah_Physicalise_Links(desc->ptr1)) ==
+				    NULL) {
+					/* Clean up ... */
+					sah_DePhysicalise_Descriptors
+					    (first_desc);
+					first_desc = NULL;
+					break;
+				}
+			}
+			desc->original_ptr2 = desc->ptr2;
+			if (desc->ptr2 != NULL) {
+				if ((desc->ptr2 =
+				     sah_Physicalise_Links(desc->ptr2)) ==
+				    NULL) {
+					/* Clean up ... */
+					sah_DePhysicalise_Descriptors
+					    (first_desc);
+					first_desc = NULL;
+					break;
+				}
+			}
+
+			desc->original_next = desc->next;
+			next_desc = desc->next;	/* save for bottom of while loop */
+			if (desc->next != NULL) {
+				desc->next = (sah_Desc *) desc->next->dma_addr;
+			}
+
+			desc = next_desc;
+		}
+	}
+	/* not prephysicalized */
+#ifdef DO_DBG
+	os_printk("Physicalise finished\n");
+#endif
+
+	return first_desc;
+}				/* sah_Physicalise_Descriptors() */
+
+/*!
+*******************************************************************************
+* This function runs through a sah_Link chain pointed to by a physical address.
+* It computes the virtual address for each pointer
+*
+* @brief Convert physical Link chain
+*
+* @param    first_link   A kernel address of a sah_Link
+*
+* @return   sah_Link *  A kernal address for the link chain of @c first_link
+* @return   NULL        If there was some error.
+*
+* @post  All links will be chained together by original virtual addresses,
+*        data pointers will point to virtual addresses.  Appropriate cache
+*        lines will be flushed, memory unwired, etc.
+*/
+sah_Link *sah_DePhysicalise_Links(sah_Link * first_link)
+{
+	sah_Link *link = first_link;
+	sah_Link *prev_link = NULL;
+
+	/* Loop on virtual link pointer */
+	while (link != NULL) {
+
+#ifdef DO_DBG
+		sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3);
+#endif
+
+		/* if this references stored keys, don't want to dephysicalize them */
+		if (!(link->flags & SAH_STORED_KEY_INFO)
+		    && !(link->flags & SAH_PREPHYS_DATA)
+		    && !(link->flags & SAH_IN_USER_KEYSTORE)) {
+
+			/* */
+			if (link->flags & SAH_OUTPUT_LINK) {
+				os_cache_inv_range(link->original_data,
+						   link->len);
+			}
+
+			/* determine if there is a page in user space associated with this
+			 * link */
+			if (link->vm_info != NULL) {
+				/* check that this isn't reserved and contains output */
+				if (!PageReserved(link->vm_info) &&
+				    (link->flags & SAH_OUTPUT_LINK)) {
+
+					/* Mark to force page eventually to backing store */
+					SetPageDirty(link->vm_info);
+				}
+
+				/* Untie this page from physical memory */
+				page_cache_release(link->vm_info);
+			} else {
+				/* kernel-mode data */
+#ifdef DO_DBG
+				os_printk("%sput: %p (%d)\n",
+					  (link->
+					   flags & SAH_OUTPUT_LINK) ? "out" :
+					  "in", link->original_data, link->len);
+#endif
+			}
+			link->data = link->original_data;
+		}
+#ifndef ALLOW_OUTPUT_1K_CROSSING
+		if (link->flags & SAH_LINK_INSERTED_LINK) {
+			/* Reconsolidate data by merging this link with previous */
+			prev_link->len += link->len;
+			prev_link->next = link->next;
+			prev_link->original_next = link->original_next;
+			sah_Free_Link(link);
+			link = prev_link;
+
+		}
+#endif
+
+		if (link->next != NULL) {
+			link->next = link->original_next;
+		}
+		prev_link = link;
+		link = link->next;
+	}
+
+	return first_link;
+}				/* sah_DePhysicalise_Links() */
+
+/*!
+ * Run through descriptors and links that have been Physicalised
+ * (sah_Physicalise_Descriptors function) and set the dma addresses back
+ * to KM virtual addresses
+ *
+ * @param first_desc Kernel virtual address of first descriptor in chain.
+ *
+ * Warning!  This ONLY works without LLO flags in headers!!!
+ */
+sah_Head_Desc *sah_DePhysicalise_Descriptors(sah_Head_Desc * first_desc)
+{
+	sah_Desc *desc = &first_desc->desc;
+
+	if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) {
+		while (desc != NULL) {
+#ifdef DO_DBG
+			sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6);
+#endif
+
+			if (desc->ptr1 != NULL) {
+				desc->ptr1 =
+				    sah_DePhysicalise_Links(desc->
+							    original_ptr1);
+			}
+			if (desc->ptr2 != NULL) {
+				desc->ptr2 =
+				    sah_DePhysicalise_Links(desc->
+							    original_ptr2);
+			}
+			if (desc->next != NULL) {
+				desc->next = desc->original_next;
+			}
+			desc = desc->next;
+		}
+	}
+	/* not prephysicalized */
+	return first_desc;
+}				/* sah_DePhysicalise_Descriptors() */
+
+/*!
+*******************************************************************************
+* This walks through a SAHARA descriptor chain and free()'s everything
+* that is not NULL. Finally it also unmaps all of the physical memory and
+* frees the kiobuf_list Queue.
+*
+* @brief Kernel Descriptor Chain Destructor
+*
+* @param    head_desc   A Descriptor pointer from kernel-space.
+*
+* @return   void
+*
+*/
+void sah_Free_Chained_Descriptors(sah_Head_Desc * head_desc)
+{
+	sah_Desc *desc = NULL;
+	sah_Desc *next_desc = NULL;
+	int this_is_head = 1;
+
+	desc = &head_desc->desc;
+
+	while (desc != NULL) {
+
+		sah_Free_Chained_Links(desc->ptr1);
+		sah_Free_Chained_Links(desc->ptr2);
+
+		/* Get a bus pointer to the next Descriptor */
+		next_desc = desc->next;
+
+		/* Zero the header and Length fields for security reasons. */
+		desc->header = 0;
+		desc->len1 = 0;
+		desc->len2 = 0;
+
+		if (this_is_head) {
+			sah_Free_Head_Descriptor(head_desc);
+			this_is_head = 0;
+#ifdef DIAG_MEM
+			sprintf(Diag_msg, "Free_Head_Descriptor: %p\n",
+				head_desc);
+			LOG_KDIAG(Diag_msg);
+#endif
+		} else {
+			/* free this descriptor */
+			sah_Free_Descriptor(desc);
+#ifdef DIAG_MEM
+			sprintf(Diag_msg, "Free_Descriptor: %p\n", desc);
+			LOG_KDIAG(Diag_msg);
+#endif
+		}
+
+		/* Look at the next Descriptor */
+		desc = next_desc;
+	}
+}				/* sah_Free_Chained_Descriptors() */
+
+/*!
+*******************************************************************************
+* This walks through a SAHARA link chain and frees everything that is
+* not NULL, excluding user-space buffers.
+*
+* @brief Kernel Link Chain Destructor
+*
+* @param    link    A Link pointer from kernel-space. This is in bus address
+*                   space.
+*
+* @return   void
+*
+*/
+void sah_Free_Chained_Links(sah_Link * link)
+{
+	sah_Link *next_link = NULL;
+
+	while (link != NULL) {
+		/* Get a bus pointer to the next Link */
+		next_link = link->next;
+
+		/* Zero some fields for security reasons. */
+		link->data = NULL;
+		link->len = 0;
+		link->ownerid = 0;
+
+		/* Free this Link */
+#ifdef DIAG_MEM
+		sprintf(Diag_msg, "Free_Link: %p(->%p)\n", link, link->next);
+		LOG_KDIAG(Diag_msg);
+#endif
+		sah_Free_Link(link);
+
+		/* Move on to the next Link */
+		link = next_link;
+	}
+}
+
+/*!
+*******************************************************************************
+* This function runs through a link chain pointed to by a user-space
+* address. It makes a temporary kernel-space copy of each link in the
+* chain and calls sah_Make_Links() to create a set of kernel-side links
+* to replace it.
+*
+* @brief Kernel Link Chain Copier
+*
+* @param    ptr         A link pointer from user-space.
+*
+* @return   sah_Link *  - The virtual address of the first link in the
+*                         chain.
+* @return   NULL        - If there was some error.
+*/
+sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr)
+{
+	sah_Link *head_link = NULL;
+	sah_Link *new_head_link = NULL;
+	sah_Link *new_tail_link = NULL;
+	sah_Link *prev_tail_link = NULL;
+	sah_Link *user_link = ptr;
+	sah_Link link_copy;
+	int link_data_length = 0;
+
+	/* Internal status variable to be used in this function */
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+	sah_Link *ret_val = NULL;
+
+	/* This will be set to True when we have finished processing our
+	 * link chain. */
+	int drv_if_done = FALSE;
+	int is_this_the_head = TRUE;
+	int result;
+
+	/* transfer all links, on this link chain, from user space */
+	while (drv_if_done == FALSE) {
+		/* Copy the current link from user-space. The virtual address, DMA
+		 * address, and vm_info fields of the sah_Link struct are not part
+		 * of the user-space structure. They must be the last elements and
+		 * should not be copied. */
+		result = copy_from_user(&link_copy,
+					user_link, (sizeof(sah_Link) -
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+						    sizeof(struct page *) -	/* vm_info */
+#endif
+						    sizeof(dma_addr_t) -	/* dma_addr */
+						    sizeof(uint32_t) -	/* virt_addr */
+						    sizeof(uint8_t *) -	/* original_data */
+						    sizeof(sah_Link *)));	/* original_next */
+
+		if (result != 0) {
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("copy_from_user() failed.");
+#endif
+			drv_if_done = TRUE;
+			status = FSL_RETURN_INTERNAL_ERROR_S;
+		}
+
+		if (status == FSL_RETURN_OK_S) {
+			/* This will create new links which can be used to replace tmp_link
+			 * in the chain. This will return a new head and tail link. */
+			link_data_length = link_data_length + link_copy.len;
+			new_head_link =
+			    sah_Make_Links(user_ctx, &link_copy, &new_tail_link);
+
+			if (new_head_link == NULL) {
+				/* If we ran out of memory or a user pointer was invalid */
+				drv_if_done = TRUE;
+				status = FSL_RETURN_INTERNAL_ERROR_S;
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG("sah_Make_Links() failed.");
+#endif
+			} else {
+				if (is_this_the_head == TRUE) {
+					/* Keep a reference to the head link */
+					head_link = new_head_link;
+					is_this_the_head = FALSE;
+				} else {
+					/* Need to update the previous links' next field to point
+					 * to the current link. */
+					prev_tail_link->next =
+					    (void *)new_head_link->dma_addr;
+					prev_tail_link->original_next =
+					    new_head_link;
+				}
+			}
+		}
+
+		if (status == FSL_RETURN_OK_S) {
+			/* Get to the next link in the chain. */
+			user_link = link_copy.next;
+			prev_tail_link = new_tail_link;
+
+			/* Check if the end of the link chain was reached (TRUE) or if
+			 * there is another linked to this one (FALSE) */
+			drv_if_done = (user_link == NULL) ? TRUE : FALSE;
+		}
+	}			/* end while */
+
+	if (status != FSL_RETURN_OK_S) {
+		ret_val = NULL;
+		/* There could be clean-up to do here because we may have made some
+		 * successful iterations through the while loop and as a result, the
+		 * links created by sah_Make_Links() need to be destroyed.
+		 */
+		if (head_link != NULL) {
+			/* Failed somewhere in the while loop and need to clean-up. */
+			sah_Destroy_Links(head_link);
+		}
+	} else {
+		/* Success. Return the head link. */
+		ret_val = head_link;
+	}
+
+	return ret_val;
+}				/* sah_Copy_Links() */
+
+/*!
+*******************************************************************************
+* This function takes an input link pointed to by a user-space address
+* and returns a chain of links that span the physical pages pointed
+* to by the input link.
+*
+* @brief Kernel Link Chain Constructor
+*
+* @param    ptr         A link pointer from user-space.
+* @param    tail        The address of a link pointer. This is used to return
+*                       the tail link created by this function.
+*
+* @return   sah_Link *  - A virtual address of the first link in the
+*                         chain.
+* @return   NULL        - If there was some error.
+*
+*/
+sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx,
+							sah_Link * ptr, sah_Link ** tail)
+{
+	int result = -1;
+	int page_index = 0;
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+	int is_this_the_head = TRUE;
+	void *buffer_start = NULL;
+	sah_Link *link = NULL;
+	sah_Link *prev_link = NULL;
+	sah_Link *head_link = NULL;
+	sah_Link *ret_val = NULL;
+	int buffer_length = 0;
+	struct page **local_pages = NULL;
+	int nr_pages = 0;
+	int write = (sah_Link_Get_Flags(ptr) & SAH_OUTPUT_LINK) ? WRITE : READ;
+	dma_addr_t phys_addr;
+
+	/* need to retrieve stored key? */
+	if (ptr->flags & SAH_STORED_KEY_INFO) {
+		fsl_shw_return_t ret_status;
+
+		/* allocate space for this link */
+		link = sah_Alloc_Link();
+#ifdef DIAG_MEM
+		sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link,
+			(void *)link->dma_addr);
+		LOG_KDIAG(Diag_msg);
+#endif
+
+		if (link == NULL) {
+			status = FSL_RETURN_NO_RESOURCE_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("sah_Alloc_Link() failed!");
+#endif
+			return link;
+		} else {
+			uint32_t max_len = 0;	/* max slot length */
+
+			/* get length and physical address of stored key */
+			ret_status = system_keystore_get_slot_info(ptr->ownerid, ptr->slot, (uint32_t *) & link->data,	/* RED key address */
+						      &max_len);
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG_ARGS
+			("ret_status==SCC_RET_OK? %s.  slot: %i. data: %p"
+			 ". len: %i, key length: %i",
+			(ret_status == FSL_RETURN_OK_S ? "yes" : "no"),
+			 ptr->slot, link->data, max_len, ptr->len);
+#endif
+
+			if ((ret_status == FSL_RETURN_OK_S) && (ptr->len <= max_len)) {
+				/* finish populating the link */
+				link->len = ptr->len;
+				link->flags = ptr->flags & ~SAH_PREPHYS_DATA;
+				*tail = link;
+			} else {
+#ifdef DIAG_DRV_IF
+				if (ret_status == FSL_RETURN_OK_S) {
+					LOG_KDIAG
+					    ("SCC sah_Link key slot reference is too long");
+				} else {
+					LOG_KDIAG
+					    ("SCC sah_Link slot slot reference is invalid");
+				}
+#endif
+				sah_Free_Link(link);
+				status = FSL_RETURN_INTERNAL_ERROR_S;
+				return NULL;
+			}
+			return link;
+		}
+	}	else if (ptr->flags & SAH_IN_USER_KEYSTORE) {
+
+#ifdef FSL_HAVE_SCC2
+
+		void *kernel_base;
+
+		/* allocate space for this link */
+		link = sah_Alloc_Link();
+#ifdef DIAG_MEM
+		sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link,
+			(void *)link->dma_addr);
+		LOG_KDIAG(Diag_msg);
+#endif				/* DIAG_MEM */
+
+		if (link == NULL) {
+			status = FSL_RETURN_NO_RESOURCE_S;
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("sah_Alloc_Link() failed!");
+#endif
+			return link;
+		} else {
+			/* link->data points to the virtual address of the key data, however
+			 * this memory does not need to be locked down.
+			 */
+			kernel_base = lookup_user_partition(user_ctx,
+							    (uint32_t) ptr->
+							    data & PAGE_MASK);
+
+			link->data = (uint8_t *) scc_virt_to_phys(kernel_base +
+								  ((unsigned
+								    long)ptr->
+								   data &
+								   ~PAGE_MASK));
+
+			/* Do bounds checking to ensure that the user is not overstepping
+			 * the bounds of their partition.  This is a simple implementation
+			 * that assumes the user only owns one partition.  It only checks
+			 * to see if the address of the last byte of data steps over a
+			 * page boundary.
+			 */
+			if ((kernel_base != NULL) &&
+			    ((((uint32_t) link->data +
+			       link->len) >> PAGE_SHIFT) ==
+			     ((uint32_t) link->data >> PAGE_SHIFT))) {
+				/* finish populating the link */
+				link->len = ptr->len;
+				link->flags = ptr->flags & ~SAH_PREPHYS_DATA;
+				*tail = link;
+			} else {
+#ifdef DIAG_DRV_IF
+				if (kernel_base != NULL) {
+					LOG_KDIAG
+					    ("SCC sah_Link key slot reference is too long");
+				} else {
+					LOG_KDIAG
+					    ("SCC sah_Link slot slot reference is invalid");
+				}
+#endif
+				sah_Free_Link(link);
+				status = FSL_RETURN_INTERNAL_ERROR_S;
+				return NULL;
+			}
+			return link;
+		}
+
+#else				/* FSL_HAVE_SCC2 */
+
+		return NULL;
+
+#endif				/* FSL_HAVE_SCC2 */
+	}
+
+	if (ptr->data == NULL) {
+		/* The user buffer must not be NULL because map_user_kiobuf() cannot
+		 * handle NULL pointer input.
+		 */
+		status = FSL_RETURN_BAD_DATA_LENGTH_S;
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("sah_Link data pointer is NULL.");
+#endif
+	}
+
+	if (status == FSL_RETURN_OK_S) {
+		unsigned long start_page = (unsigned long)ptr->data & PAGE_MASK;
+
+		/* determine number of pages being used for this link */
+		nr_pages = (((unsigned long)(ptr->data) & ~PAGE_MASK)
+			    + ptr->len + ~PAGE_MASK) >> PAGE_SHIFT;
+
+		/* ptr contains all the 'user space' information, add the pages
+		 * to it also just so everything is in one place */
+		local_pages =
+		    kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
+
+		if (local_pages == NULL) {
+			status = FSL_RETURN_NO_RESOURCE_S;	/* no memory! */
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("kmalloc() failed.");
+#endif
+		} else {
+			/* get the actual pages being used in 'user space' */
+
+			down_read(&current->mm->mmap_sem);
+			result = get_user_pages(current, current->mm,
+						start_page, nr_pages,
+						write, 0 /* noforce */ ,
+						local_pages, NULL);
+			up_read(&current->mm->mmap_sem);
+
+			if (result < nr_pages) {
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG("get_user_pages() failed.");
+#endif
+				if (result > 0) {
+					for (page_index = 0;
+					     page_index < result;
+					     page_index++) {
+						page_cache_release(local_pages
+								   [page_index]);
+					}
+				}
+				status = FSL_RETURN_INTERNAL_ERROR_S;
+			}
+		}
+	}
+
+	/* Now we can walk through the list of pages in the buffer */
+	if (status == FSL_RETURN_OK_S) {
+
+#if defined(FLUSH_SPECIFIC_DATA_ONLY) && !defined(HAS_L2_CACHE)
+		/*
+		 * Now that pages are wired, clear user data from cache lines.  When
+		 * there is just an L1 cache, clean based on user virtual for ARM.
+		 */
+		if (write == WRITE) {
+			os_cache_flush_range(ptr->data, ptr->len);
+		} else {
+			os_cache_clean_range(ptr->data, ptr->len);
+		}
+#endif
+
+		for (page_index = 0; page_index < nr_pages; page_index++) {
+			/* Allocate a new link structure */
+			link = sah_Alloc_Link();
+#ifdef DIAG_MEM
+			sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link,
+				(void *)link->dma_addr);
+			LOG_KDIAG(Diag_msg);
+#endif
+			if (link == NULL) {
+#ifdef DIAG_DRV_IF
+				LOG_KDIAG("sah_Alloc_Link() failed.");
+#endif
+				status = FSL_RETURN_NO_RESOURCE_S;
+
+				/* need to free the rest of the pages. Destroy_Links will take
+				 * care of the ones already assigned to a link */
+				for (; page_index < nr_pages; page_index++) {
+					page_cache_release(local_pages
+							   [page_index]);
+				}
+				break;	/* exit 'for page_index' loop */
+			}
+
+			if (status == FSL_RETURN_OK_S) {
+				if (is_this_the_head == TRUE) {
+					/* keep a reference to the head link */
+					head_link = link;
+					/* remember that we have seen the head link */
+					is_this_the_head = FALSE;
+				} else {
+					/* If this is not the head link then set the previous
+					 * link's next pointer to point to this link */
+					prev_link->original_next = link;
+					prev_link->next =
+					    (sah_Link *) link->dma_addr;
+				}
+
+				buffer_start =
+				    page_address(local_pages[page_index]);
+
+				phys_addr =
+					page_to_phys(local_pages[page_index]);
+
+				if (page_index == 0) {
+					/* If this is the first page, there might be an
+					 * offset. We need to increment the address by this offset
+					 * so we don't just get the start of the page.
+					 */
+					buffer_start +=
+					    (unsigned long)
+					    sah_Link_Get_Data(ptr)
+					    & ~PAGE_MASK;
+					phys_addr +=
+					    (unsigned long)
+					    sah_Link_Get_Data(ptr)
+					    & ~PAGE_MASK;
+					buffer_length = PAGE_SIZE
+					    -
+					    ((unsigned long)
+					     sah_Link_Get_Data(ptr)
+					     & ~PAGE_MASK);
+				} else {
+					buffer_length = PAGE_SIZE;
+				}
+
+				if (page_index == nr_pages - 1) {
+					/* if this is the last page, we need to adjust
+					 * the buffer_length to account for the last page being
+					 * partially used.
+					 */
+					buffer_length -=
+					    nr_pages * PAGE_SIZE -
+					    sah_Link_Get_Len(ptr) -
+					    ((unsigned long)
+					     sah_Link_Get_Data(ptr) &
+					     ~PAGE_MASK);
+				}
+#if defined(FLUSH_SPECIFIC_DATA_ONLY) && defined(HAS_L2_CACHE)
+				/*
+				 * When there is an L2 cache, clean based on kernel
+				 * virtual..
+				 */
+				if (write == WRITE) {
+					os_cache_flush_range(buffer_start,
+							     buffer_length);
+				} else {
+					os_cache_clean_range(buffer_start,
+							     buffer_length);
+				}
+#endif
+
+				/* Fill in link information */
+				link->len = buffer_length;
+#if !defined(HAS_L2_CACHE)
+				/* use original virtual */
+				link->original_data = ptr->data;
+#else
+				/* use kernel virtual */
+				link->original_data = buffer_start;
+#endif
+				link->data = (void *)phys_addr;
+				link->flags = ptr->flags & ~SAH_PREPHYS_DATA;
+				link->vm_info = local_pages[page_index];
+				prev_link = link;
+
+#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING)
+				if (
+#ifdef NO_OUTPUT_1K_CROSSING
+					   /* Insert extra link if 1k boundary on output pointer
+					    * crossed not at an 8-word boundary */
+					   (link->flags & SAH_OUTPUT_LINK) &&
+					   (((uint32_t) buffer_start % 32) != 0)
+					   &&
+#endif
+					   ((((uint32_t) buffer_start & 1023) +
+					     buffer_length) > 1024)) {
+
+					/* Shorten current link to 1k boundary */
+					link->len =
+					    1024 -
+					    ((uint32_t) buffer_start % 1024);
+
+					/* Get new link to follow it */
+					link = sah_Alloc_Link();
+					prev_link->len =
+					    1024 -
+					    ((uint32_t) buffer_start % 1024);
+					prev_link->original_next = link;
+					prev_link->next =
+					    (sah_Link *) link->dma_addr;
+					buffer_length -= prev_link->len;
+					buffer_start += prev_link->len;
+
+#if !defined(HAS_L2_CACHE)
+					/* use original virtual */
+					link->original_data = ptr->data;
+#else
+					/* use kernel virtual */
+					link->original_data = buffer_start;
+#endif
+					link->data = (void *)phys_addr;
+					link->vm_info = prev_link->vm_info;
+					prev_link->vm_info = NULL;	/* delay release */
+					link->flags = ptr->flags;
+					link->len = buffer_length;
+					prev_link = link;
+				}	/* while link would cross 1K boundary */
+#endif				/* 1K_CROSSING */
+			}
+		}		/* for each page */
+	}
+
+	if (local_pages != NULL) {
+		kfree(local_pages);
+	}
+
+	if (status != FSL_RETURN_OK_S) {
+		/* De-allocated any links created, this routine first looks if
+		 * head_link is NULL */
+		sah_Destroy_Links(head_link);
+
+		/* Clean-up of the KIOBUF will occur in the * sah_Copy_Descriptors()
+		 * function.
+		 * Clean-up of the Queue entry must occur in the function called
+		 * sah_Copy_Descriptors().
+		 */
+	} else {
+
+		/* Success. Return the head link. */
+		ret_val = head_link;
+		link->original_next = NULL;
+		/* return the tail link as well */
+		*tail = link;
+	}
+
+	return ret_val;
+}				/* sah_Make_Links() */
+
+/*!
+*******************************************************************************
+* This walks through a SAHARA descriptor chain and frees everything
+* that is not NULL. Finally it also unmaps all of the physical memory and
+* frees the kiobuf_list Queue.
+*
+* @brief Kernel Descriptor Chain Destructor
+*
+* @param    desc        A Descriptor pointer from kernel-space. This should be
+*                       in bus address space.
+*
+* @return   void
+*
+*/
+void sah_Destroy_Descriptors(sah_Head_Desc * head_desc)
+{
+	sah_Desc *this_desc = (sah_Desc *) head_desc;
+	sah_Desc *next_desc = NULL;
+	int this_is_head = 1;
+
+	/*
+	 * Flush the D-cache. This flush is here because the hardware has finished
+	 * processing this descriptor and probably has changed the contents of
+	 * some linked user buffers as a result.  This flush will enable
+	 * user-space applications to see the correct data rather than the
+	 * out-of-date cached version.
+	 */
+#ifndef FLUSH_SPECIFIC_DATA_ONLY
+	os_flush_cache_all();
+#endif
+
+	head_desc = (sah_Head_Desc *) this_desc->virt_addr;
+
+	while (this_desc != NULL) {
+		if (this_desc->ptr1 != NULL) {
+			sah_Destroy_Links(this_desc->original_ptr1
+					  ? this_desc->
+					  original_ptr1 : this_desc->ptr1);
+		}
+		if (this_desc->ptr2 != NULL) {
+			sah_Destroy_Links(this_desc->original_ptr2
+					  ? this_desc->
+					  original_ptr2 : this_desc->ptr2);
+		}
+
+		/* Get a bus pointer to the next Descriptor */
+		next_desc = (this_desc->original_next
+			     ? this_desc->original_next : this_desc->next);
+
+		/* Zero the header and Length fields for security reasons. */
+		this_desc->header = 0;
+		this_desc->len1 = 0;
+		this_desc->len2 = 0;
+
+		if (this_is_head) {
+			sah_Free_Head_Descriptor(head_desc);
+#ifdef DIAG_MEM
+			sprintf(Diag_msg, "Free_Head_Descriptor: %p\n",
+				head_desc);
+			LOG_KDIAG(Diag_msg);
+#endif
+			this_is_head = 0;
+		} else {
+			/* free this descriptor */
+			sah_Free_Descriptor(this_desc);
+#ifdef DIAG_MEM
+			sprintf(Diag_msg, "Free_Descriptor: %p\n", this_desc);
+			LOG_KDIAG(Diag_msg);
+#endif
+		}
+
+		/* Set up for next round. */
+		this_desc = (sah_Desc *) next_desc;
+	}
+}
+
+/*!
+*******************************************************************************
+* This walks through a SAHARA link chain and frees everything that is
+* not NULL excluding user-space buffers.
+*
+* @brief Kernel Link Chain Destructor
+*
+* @param    link    A Link pointer from kernel-space.
+*
+* @return   void
+*
+*/
+void sah_Destroy_Links(sah_Link * link)
+{
+	sah_Link *this_link = link;
+	sah_Link *next_link = NULL;
+
+	while (this_link != NULL) {
+
+		/* if this link indicates an associated page, process it */
+		if (this_link->vm_info != NULL) {
+			/* since this function is only called from the routine that
+			 * creates a kernel copy of the user space descriptor chain,
+			 * there are no pages to dirty. All that is needed is to release
+			 * the page from cache */
+			page_cache_release(this_link->vm_info);
+		}
+
+		/* Get a bus pointer to the next Link */
+		next_link = (this_link->original_next
+			     ? this_link->original_next : this_link->next);
+
+		/* Zero the Pointer and Length fields for security reasons. */
+		this_link->data = NULL;
+		this_link->len = 0;
+
+		/* Free this Link */
+		sah_Free_Link(this_link);
+#ifdef DIAG_MEM
+		sprintf(Diag_msg, "Free_Link: %p\n", this_link);
+		LOG_KDIAG(Diag_msg);
+#endif
+
+		/* Look at the next Link */
+		this_link = next_link;
+	}
+}
+
+/*!
+*******************************************************************************
+* @brief Initialize memory manager/mapper.
+*
+* In 2.4, this function also allocates a kiovec to be used when mapping user
+* data to kernel space
+*
+* @return 0 for success, OS error code on failure
+*
+*/
+int sah_Init_Mem_Map(void)
+{
+	int ret = OS_ERROR_FAIL_S;
+
+	mem_lock = os_lock_alloc_init();
+
+	/*
+	 * If one of these fails, change the calculation in the #define earlier in
+	 * the file to be the other one.
+	 */
+	if (sizeof(sah_Link) > MEM_BLOCK_SIZE) {
+		os_printk("Sahara Driver: sah_Link structure is too large\n");
+	} else if (sizeof(sah_Desc) > MEM_BLOCK_SIZE) {
+		os_printk("Sahara Driver: sah_Desc structure is too large\n");
+	} else {
+		ret = OS_ERROR_OK_S;
+	}
+
+#ifndef SELF_MANAGED_POOL
+
+	big_dma_pool = dma_pool_create("sah_big_blocks", NULL,
+				       sizeof(Mem_Big_Block), sizeof(uint32_t),
+				       PAGE_SIZE);
+	small_dma_pool = dma_pool_create("sah_small_blocks", NULL,
+					 sizeof(Mem_Block), sizeof(uint32_t),
+					 PAGE_SIZE);
+#else
+
+#endif
+	return ret;
+}
+
+/*!
+*******************************************************************************
+* @brief Clean up memory manager/mapper.
+*
+* In 2.4, this function also frees the kiovec used when mapping user data to
+* kernel space.
+*
+* @return none
+*
+*/
+void sah_Stop_Mem_Map(void)
+{
+	os_lock_deallocate(mem_lock);
+
+#ifndef SELF_MANAGED_POOL
+	if (big_dma_pool != NULL) {
+		dma_pool_destroy(big_dma_pool);
+	}
+	if (small_dma_pool != NULL) {
+		dma_pool_destroy(small_dma_pool);
+	}
+#endif
+}
+
+/*!
+*******************************************************************************
+* Allocate Head descriptor from free pool.
+*
+* @brief Allocate Head descriptor
+*
+* @return sah_Head_Desc Free descriptor, NULL if no free descriptors available.
+*
+*/
+sah_Head_Desc *sah_Alloc_Head_Descriptor(void)
+{
+	Mem_Big_Block *block;
+	sah_Head_Desc *desc;
+
+	block = sah_Alloc_Big_Block();
+	if (block != NULL) {
+		/* initialize everything */
+		desc = (sah_Head_Desc *) block->data;
+
+		desc->desc.virt_addr = (sah_Desc *) desc;
+		desc->desc.dma_addr = block->dma_addr;
+		desc->desc.original_ptr1 = NULL;
+		desc->desc.original_ptr2 = NULL;
+		desc->desc.original_next = NULL;
+
+		desc->desc.ptr1 = NULL;
+		desc->desc.ptr2 = NULL;
+		desc->desc.next = NULL;
+	} else {
+		desc = NULL;
+	}
+
+	return desc;
+}
+
+/*!
+*******************************************************************************
+* Allocate descriptor from free pool.
+*
+* @brief Allocate descriptor
+*
+* @return sah_Desc Free descriptor, NULL if no free descriptors available.
+*
+*/
+sah_Desc *sah_Alloc_Descriptor(void)
+{
+	Mem_Block *block;
+	sah_Desc *desc;
+
+	block = sah_Alloc_Block();
+	if (block != NULL) {
+		/* initialize everything */
+		desc = (sah_Desc *) block->data;
+
+		desc->virt_addr = desc;
+		desc->dma_addr = block->dma_addr;
+		desc->original_ptr1 = NULL;
+		desc->original_ptr2 = NULL;
+		desc->original_next = NULL;
+
+		desc->ptr1 = NULL;
+		desc->ptr2 = NULL;
+		desc->next = NULL;
+	} else {
+		desc = NULL;
+	}
+
+	return (desc);
+}
+
+/*!
+*******************************************************************************
+* Allocate link from free pool.
+*
+* @brief Allocate link
+*
+* @return sah_Link Free link, NULL if no free links available.
+*
+*/
+sah_Link *sah_Alloc_Link(void)
+{
+	Mem_Block *block;
+	sah_Link *link;
+
+	block = sah_Alloc_Block();
+	if (block != NULL) {
+		/* initialize everything */
+		link = (sah_Link *) block->data;
+
+		link->virt_addr = link;
+		link->original_next = NULL;
+		link->original_data = NULL;
+		/* information found in allocated block */
+		link->dma_addr = block->dma_addr;
+
+		/* Sahara link fields */
+		link->len = 0;
+		link->data = NULL;
+		link->next = NULL;
+
+		/* driver required fields */
+		link->flags = 0;
+		link->vm_info = NULL;
+	} else {
+		link = NULL;
+	}
+
+	return link;
+}
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Add a new page to end of block free pool. This will allocate one page and
+* fill the pool with entries, appending to the end.
+*
+* @brief Add page of blocks to block free pool.
+*
+* @pre This function must be called with the #mem_lock held.
+*
+* @param   big    0        - make blocks big enough for sah_Desc
+*                 non-zero - make blocks big enough for sah_Head_Desc
+*
+* @return int TRUE if blocks added succeesfully, FALSE otherwise
+*
+*/
+int sah_Block_Add_Page(int big)
+{
+	void *page;
+	int success;
+	dma_addr_t dma_addr;
+	unsigned block_index;
+	uint32_t dma_offset;
+	unsigned block_entries =
+	    big ? MEM_BIG_BLOCK_ENTRIES : MEM_BLOCK_ENTRIES;
+	unsigned block_size = big ? sizeof(Mem_Big_Block) : sizeof(Mem_Block);
+	void *block;
+
+	/* Allocate page of memory */
+#ifndef USE_COHERENT_MEMORY
+	page = os_alloc_memory(PAGE_SIZE, GFP_ATOMIC | __GFP_DMA);
+	dma_addr = os_pa(page);
+#else
+	page = os_alloc_coherent(PAGE_SIZE, &dma_addr, GFP_ATOMIC);
+#endif
+	if (page != NULL) {
+		/*
+		 * Find the difference between the virtual address and the DMA
+		 * address of the page. This is used later to determine the DMA
+		 * address of each individual block.
+		 */
+		dma_offset = page - (void *)dma_addr;
+
+		/* Split page into blocks and add to free pool */
+		block = page;
+		for (block_index = 0; block_index < block_entries;
+		     block_index++) {
+			if (big) {
+				register Mem_Big_Block *blockp = block;
+				blockp->dma_addr =
+				    (uint32_t) (block - dma_offset);
+				sah_Append_Big_Block(blockp);
+			} else {
+				register Mem_Block *blockp = block;
+				blockp->dma_addr =
+				    (uint32_t) (block - dma_offset);
+				/* sah_Append_Block must be protected with spin locks. This is
+				 * done in sah_Alloc_Block(), which calls
+				 * sah_Block_Add_Page() */
+				sah_Append_Block(blockp);
+			}
+			block += block_size;
+		}
+		success = TRUE;
+#ifdef DIAG_MEM
+		LOG_KDIAG("Succeeded in allocating new page");
+#endif
+	} else {
+		success = FALSE;
+#ifdef DIAG_MEM
+		LOG_KDIAG("Failed in allocating new page");
+#endif
+	}
+
+	return success;
+}
+#endif				/* SELF_MANAGED_POOL */
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Allocate block from free pool. A block is large enough to fit either a link
+* or descriptor.
+*
+* @brief Allocate memory block
+*
+* @return Mem_Block Free block, NULL if no free blocks available.
+*
+*/
+static Mem_Big_Block *sah_Alloc_Big_Block(void)
+{
+	Mem_Big_Block *block;
+	os_lock_context_t lock_flags;
+
+	os_lock_save_context(mem_lock, lock_flags);
+
+	/* If the pool is empty, try to allocate more entries */
+	if (big_block_free_head == NULL) {
+		(void)sah_Block_Add_Page(1);
+	}
+
+	/* Check that the pool now has some free entries */
+	if (big_block_free_head != NULL) {
+		/* Return the head of the free pool */
+		block = big_block_free_head;
+
+		big_block_free_head = big_block_free_head->next;
+		if (big_block_free_head == NULL) {
+			/* Allocated last entry in pool */
+			big_block_free_tail = NULL;
+		}
+	} else {
+		block = NULL;
+	}
+	os_unlock_restore_context(mem_lock, lock_flags);
+
+	return block;
+}
+#else
+/*!
+*******************************************************************************
+* Allocate block from free pool. A block is large enough to fit either a link
+* or descriptor.
+*
+* @brief Allocate memory block
+*
+* @return Mem_Block Free block, NULL if no free blocks available.
+*
+*/
+static Mem_Big_Block *sah_Alloc_Big_Block(void)
+{
+	dma_addr_t dma_addr;
+	Mem_Big_Block *block =
+	    dma_pool_alloc(big_dma_pool, GFP_ATOMIC, &dma_addr);
+
+	if (block == NULL) {
+	} else {
+		block->dma_addr = dma_addr;
+	}
+
+	return block;
+}
+#endif
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Allocate block from free pool. A block is large enough to fit either a link
+* or descriptor.
+*
+* @brief Allocate memory block
+*
+* @return Mem_Block Free block, NULL if no free blocks available.
+*
+*/
+/******************************************************************************
+*
+* MODIFICATION HISTORY:
+*
+* Date         Person     Change
+* 31/10/2003   RWK        PR52734 - Implement functions to allocate
+*                                   descriptors and links. Replace
+*                                   consistent_alloc() calls. Initial creation.
+*
+******************************************************************************/
+static Mem_Block *sah_Alloc_Block(void)
+{
+	Mem_Block *block;
+	os_lock_context_t lock_flags;
+
+	os_lock_save_context(mem_lock, lock_flags);
+
+	/* If the pool is empty, try to allocate more entries */
+	if (block_free_head == NULL) {
+		(void)sah_Block_Add_Page(0);
+	}
+
+	/* Check that the pool now has some free entries */
+	if (block_free_head != NULL) {
+		/* Return the head of the free pool */
+		block = block_free_head;
+
+		block_free_head = block_free_head->next;
+		if (block_free_head == NULL) {
+			/* Allocated last entry in pool */
+			block_free_tail = NULL;
+		}
+	} else {
+		block = NULL;
+	}
+	os_unlock_restore_context(mem_lock, lock_flags);
+
+	return block;
+}
+#else
+/*!
+*******************************************************************************
+* Allocate block from free pool. A block is large enough to fit either a link
+* or descriptor.
+*
+* @brief Allocate memory block
+*
+* @return Mem_Block Free block, NULL if no free blocks available.
+*
+*/
+/******************************************************************************
+*
+* MODIFICATION HISTORY:
+*
+* Date         Person     Change
+* 31/10/2003   RWK        PR52734 - Implement functions to allocate
+*                                   descriptors and links. Replace
+*                                   consistent_alloc() calls. Initial creation.
+*
+******************************************************************************/
+static Mem_Block *sah_Alloc_Block(void)
+{
+
+	dma_addr_t dma_addr;
+	Mem_Block *block =
+	    dma_pool_alloc(small_dma_pool, GFP_ATOMIC, &dma_addr);
+
+	if (block == NULL) {
+	} else {
+		block->dma_addr = dma_addr;
+	}
+
+	return block;
+}
+#endif
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Free memory block back to free pool
+*
+* @brief Free memory block
+*
+* @param    block       A block allocated with sah_Alloc_Block().
+*
+* @return none
+*
+*/
+static void sah_Free_Block(Mem_Block * block)
+{
+	os_lock_context_t lock_flags;
+
+	os_lock_save_context(mem_lock, lock_flags);
+	sah_Append_Block(block);
+	os_unlock_restore_context(mem_lock, lock_flags);
+}
+#else
+/*!
+*******************************************************************************
+* Free memory block back to free pool
+*
+* @brief Free memory block
+*
+* @param    block       A block allocated with sah_Alloc_Block().
+*
+* @return none
+*
+*/
+static void sah_Free_Block(Mem_Block * block)
+{
+	dma_pool_free(small_dma_pool, block, block->dma_addr);
+}
+#endif
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Free memory block back to free pool
+*
+* @brief Free memory block
+*
+* @param    block       A block allocated with sah_Alloc_Block().
+*
+* @return none
+*
+*/
+static void sah_Free_Big_Block(Mem_Big_Block * block)
+{
+	os_lock_context_t lock_flags;
+
+	os_lock_save_context(mem_lock, lock_flags);
+	sah_Append_Big_Block(block);
+	os_unlock_restore_context(mem_lock, lock_flags);
+}
+#else
+/*!
+*******************************************************************************
+* Free memory block back to free pool
+*
+* @brief Free memory block
+*
+* @param    block       A block allocated with sah_Alloc_Block().
+*
+* @return none
+*
+*/
+static void sah_Free_Big_Block(Mem_Big_Block * block)
+{
+	dma_pool_free(big_dma_pool, block, block->dma_addr);
+}
+#endif
+
+#ifdef SELF_MANAGED_POOL
+/*!
+*******************************************************************************
+* Append memory block to end of free pool.
+*
+* @param    block       A block entry
+*
+* @return none
+*
+* @pre This function must be called with the #mem_lock held.
+*
+* @brief Append memory block to free pool
+*/
+static void sah_Append_Big_Block(Mem_Big_Block * block)
+{
+
+	/* Initialise block */
+	block->next = NULL;
+
+	/* Remember that block may be the first in the pool */
+	if (big_block_free_tail != NULL) {
+		big_block_free_tail->next = block;
+	} else {
+		/* Pool is empty */
+		big_block_free_head = block;
+	}
+
+	big_block_free_tail = block;
+}
+
+/*!
+*******************************************************************************
+* Append memory block to end of free pool.
+*
+* @brief Append memory block to free pool
+*
+* @param    block       A block entry
+*
+* @return none
+*
+* @pre #mem_lock must be held
+*
+*/
+static void sah_Append_Block(Mem_Block * block)
+{
+
+	/* Initialise block */
+	block->next = NULL;
+
+	/* Remember that block may be the first in the pool */
+	if (block_free_tail != NULL) {
+		block_free_tail->next = block;
+	} else {
+		/* Pool is empty */
+		block_free_head = block;
+	}
+
+	block_free_tail = block;
+}
+#endif				/* SELF_MANAGED_POOL */
+
+/* End of sah_memory_mapper.c */
diff --git a/drivers/mxc/security/sahara2/sah_queue.c b/drivers/mxc/security/sahara2/sah_queue.c
new file mode 100644
index 000000000000..0f3e56e4c254
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_queue.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sah_queue.c
+*
+* @brief This file provides a FIFO Queue implementation.
+*
+*/
+/******************************************************************************
+*
+* CAUTION:
+*******************************************************************
+*/
+
+/* SAHARA Includes */
+#include <sah_queue_manager.h>
+#ifdef DIAG_DRV_QUEUE
+#include <diagnostic.h>
+#endif
+
+/******************************************************************************
+* Queue Functions
+******************************************************************************/
+
+/*!
+*******************************************************************************
+* This function constructs a new sah_Queue.
+*
+* @brief     sah_Queue Constructor
+*
+* @return   A pointer to a newly allocated sah_Queue.
+* @return   NULL if allocation of memory failed.
+*/
+/******************************************************************************
+*
+* CAUTION:  This function may sleep in low-memory situations, as it uses
+*           kmalloc ( ..., GFP_KERNEL).
+******************************************************************************/
+sah_Queue *sah_Queue_Construct(void)
+{
+	sah_Queue *q = (sah_Queue *) os_alloc_memory(sizeof(sah_Queue),
+						     GFP_KERNEL);
+
+	if (q != NULL) {
+		/* Initialise the queue to an empty state. */
+		q->head = NULL;
+		q->tail = NULL;
+		q->count = 0;
+	}
+#ifdef DIAG_DRV_QUEUE
+	else {
+		LOG_KDIAG("kmalloc() failed.");
+	}
+#endif
+
+	return q;
+}
+
+/*!
+*******************************************************************************
+* This function destroys a sah_Queue.
+*
+* @brief     sah_Queue Destructor
+*
+* @param    q    A pointer to a sah_Queue.
+*
+* @return   void
+*/
+/******************************************************************************
+*
+* CAUTION:  This function does not free any queue entries.
+*
+******************************************************************************/
+void sah_Queue_Destroy(sah_Queue * q)
+{
+#ifdef DIAG_DRV_QUEUE
+	if (q == NULL) {
+		LOG_KDIAG("Trying to kfree() a NULL pointer.");
+	} else {
+		if (q->count != 0) {
+			LOG_KDIAG
+			    ("Trying to destroy a queue that is not empty.");
+		}
+	}
+#endif
+
+	if (q != NULL) {
+		os_free_memory(q);
+		q = NULL;
+	}
+}
+
+/*!
+*******************************************************************************
+* This function appends a sah_Head_Desc to the tail of a sah_Queue.
+*
+* @brief     Appends a sah_Head_Desc to a sah_Queue.
+*
+* @param    q       A pointer to a sah_Queue to append to.
+* @param    entry   A pointer to a sah_Head_Desc to append.
+*
+* @pre   The #desc_queue_lock must be held before calling this function.
+*
+* @return   void
+*/
+/******************************************************************************
+*
+* CAUTION: NONE
+******************************************************************************/
+void sah_Queue_Append_Entry(sah_Queue * q, sah_Head_Desc * entry)
+{
+	sah_Head_Desc *tail_entry = NULL;
+
+	if ((q == NULL) || (entry == NULL)) {
+#ifdef DIAG_DRV_QUEUE
+		LOG_KDIAG("Null pointer input.");
+#endif
+		return;
+	}
+
+	if (q->count == 0) {
+		/* The queue is empty */
+		q->head = entry;
+		q->tail = entry;
+		entry->next = NULL;
+		entry->prev = NULL;
+	} else {
+		/* The queue is not empty */
+		tail_entry = q->tail;
+		tail_entry->next = entry;
+		entry->next = NULL;
+		entry->prev = tail_entry;
+		q->tail = entry;
+	}
+	q->count++;
+}
+
+/*!
+*******************************************************************************
+* This function a removes a sah_Head_Desc from the head of a sah_Queue.
+*
+* @brief     Removes a sah_Head_Desc from a the head of a sah_Queue.
+*
+* @param    q    A pointer to a sah_Queue to remove from.
+*
+* @pre   The #desc_queue_lock must be held before calling this function.
+*
+* @return   void
+*/
+/******************************************************************************
+*
+* CAUTION:  This does not kfree() the entry.
+******************************************************************************/
+void sah_Queue_Remove_Entry(sah_Queue * q)
+{
+	sah_Queue_Remove_Any_Entry(q, q->head);
+}
+
+/*!
+*******************************************************************************
+* This function a removes a sah_Head_Desc from anywhere in a sah_Queue.
+*
+* @brief     Removes a sah_Head_Desc from anywhere in a sah_Queue.
+*
+* @param    qq      A pointer to a sah_Queue to remove from.
+* @param    entry   A pointer to a sah_Head_Desc to remove.
+*
+* @pre   The #desc_queue_lock must be held before calling this function.
+*
+* @return   void
+*/
+/******************************************************************************
+*
+* CAUTION:  This does not kfree() the entry. Does not check to see if the entry
+*           actually belongs to the queue.
+******************************************************************************/
+void sah_Queue_Remove_Any_Entry(sah_Queue * q, sah_Head_Desc * entry)
+{
+	sah_Head_Desc *prev_entry = NULL;
+	sah_Head_Desc *next_entry = NULL;
+
+	if ((q == NULL) || (entry == NULL)) {
+#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT
+		LOG_KDIAG("Null pointer input.");
+#endif
+		return;
+	}
+
+	if (q->count == 1) {
+		/* If q is the only entry in the queue. */
+		q->tail = NULL;
+		q->head = NULL;
+		q->count = 0;
+	} else if (q->count > 1) {
+		/* There are 2 or more entries in the queue. */
+
+#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT
+		if ((entry->next == NULL) && (entry->prev == NULL)) {
+			LOG_KDIAG
+			    ("Queue is not empty yet both next and prev pointers"
+			     " are NULL");
+		}
+#endif
+
+		if (entry->next == NULL) {
+			/* If this is the end of the queue */
+			prev_entry = entry->prev;
+			prev_entry->next = NULL;
+			q->tail = prev_entry;
+		} else if (entry->prev == NULL) {
+			/* If this is the head of the queue */
+			next_entry = entry->next;
+			next_entry->prev = NULL;
+			q->head = next_entry;
+		} else {
+			/* If this is somewhere in the middle of the queue */
+			prev_entry = entry->prev;
+			next_entry = entry->next;
+			prev_entry->next = next_entry;
+			next_entry->prev = prev_entry;
+		}
+		q->count--;
+	}
+	/*
+	 * Otherwise we are removing an entry from an empty queue.
+	 * Don't do anything in the product code
+	 */
+#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT
+	else {
+		LOG_KDIAG("Trying to remove an entry from an empty queue.");
+	}
+#endif
+
+	entry->next = NULL;
+	entry->prev = NULL;
+}
+
+/* End of sah_queue.c */
diff --git a/drivers/mxc/security/sahara2/sah_queue_manager.c b/drivers/mxc/security/sahara2/sah_queue_manager.c
new file mode 100644
index 000000000000..1602c7043a13
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_queue_manager.c
@@ -0,0 +1,1050 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sah_queue_manager.c
+ *
+ * @brief This file provides a Queue Manager implementation.
+ *
+ * The Queue Manager manages additions and removal from the queue and updates
+ * the status of queue entries. It also calls sah_HW_* functions to interract
+ * with the hardware.
+*/
+
+#include "portable_os.h"
+
+/* SAHARA Includes */
+#include <sah_driver_common.h>
+#include <sah_queue_manager.h>
+#include <sah_status_manager.h>
+#include <sah_hardware_interface.h>
+#if defined(DIAG_DRV_QUEUE) || defined(DIAG_DRV_STATUS)
+#include <diagnostic.h>
+#endif
+#include <sah_memory_mapper.h>
+
+#ifdef DIAG_DRV_STATUS
+
+#define FSL_INVALID_RETURN 13
+#define MAX_RETURN_STRING_LEN 22
+#endif
+
+/* Defines for parsing value from Error Status register */
+#define SAH_STATUS_MASK 0x07
+#define SAH_ERROR_MASK 0x0F
+#define SAH_CHA_ERR_SOURCE_MASK 0x07
+#define SAH_CHA_ERR_STATUS_MASK 0x0FFF
+#define SAH_DMA_ERR_STATUS_MASK 0x0F
+#define SAH_DMA_ERR_SIZE_MASK 0x03
+#define SAH_DMA_ERR_DIR_MASK 0x01
+
+#define SHA_ERROR_STATUS_CONTINUE 0xFFFFFFFF
+#define SHA_CHA_ERROR_STATUS_DONE 0xFFFFFFFF
+
+/* this maps the error status register's error source 4 bit field to the API
+ * return values. A 0xFFFFFFFF indicates additional fields must be checked to
+ * determine an appropriate return value */
+static sah_Execute_Error sah_Execute_Error_Array[] = {
+	FSL_RETURN_ERROR_S,	/* SAH_ERR_NONE */
+	FSL_RETURN_BAD_FLAG_S,	/* SAH_ERR_HEADER */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_ERR_DESC_LENGTH */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_ERR_DESC_POINTER */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_ERR_LINK_LENGTH */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_ERR_LINK_POINTER */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_ERR_INPUT_BUFFER */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_ERR_OUTPUT_BUFFER */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_ERR_OUTPUT_BUFFER_STARVATION */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_ERR_INTERNAL_STATE */
+	FSL_RETURN_ERROR_S,	/* SAH_ERR_GENERAL_DESCRIPTOR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_ERR_RESERVED_FIELDS */
+	FSL_RETURN_MEMORY_ERROR_S,	/* SAH_ERR_DESCRIPTOR_ADDRESS */
+	FSL_RETURN_MEMORY_ERROR_S,	/* SAH_ERR_LINK_ADDRESS */
+	SHA_ERROR_STATUS_CONTINUE,	/* SAH_ERR_CHA */
+	SHA_ERROR_STATUS_CONTINUE	/* SAH_ERR_DMA */
+};
+
+static sah_DMA_Error_Status sah_DMA_Error_Status_Array[] = {
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_NO_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_AHB_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_IP_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_PARITY_ERR */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_DMA_BOUNDRY_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_BUSY_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_DMA_RESERVED_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S	/* SAH_DMA_INT_ERR */
+};
+
+static sah_CHA_Error_Status sah_CHA_Error_Status_Array[] = {
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_CHA_NO_ERR */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_CHA_IP_BUF */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_CHA_ADD_ERR */
+	FSL_RETURN_BAD_MODE_S,	/* SAH_CHA_MODE_ERR */
+	FSL_RETURN_BAD_DATA_LENGTH_S,	/* SAH_CHA_DATA_SIZE_ERR */
+	FSL_RETURN_BAD_KEY_LENGTH_S,	/* SAH_CHA_KEY_SIZE_ERR */
+	FSL_RETURN_BAD_MODE_S,	/* SAH_CHA_PROC_ERR */
+	FSL_RETURN_ERROR_S,	/* SAH_CHA_CTX_READ_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_CHA_INTERNAL_HW_ERR */
+	FSL_RETURN_MEMORY_ERROR_S,	/* SAH_CHA_IP_BUFF_ERR */
+	FSL_RETURN_MEMORY_ERROR_S,	/* SAH_CHA_OP_BUFF_ERR */
+	FSL_RETURN_BAD_KEY_PARITY_S,	/* SAH_CHA_DES_KEY_ERR */
+	FSL_RETURN_INTERNAL_ERROR_S,	/* SAH_CHA_RES */
+};
+
+#ifdef DIAG_DRV_STATUS
+
+char sah_return_text[FSL_INVALID_RETURN][MAX_RETURN_STRING_LEN] = {
+	"No error",		/* FSL_RETURN_OK_S */
+	"Error",		/* FSL_RETURN_ERROR_S */
+	"No resource",		/* FSL_RETURN_NO_RESOURCE_S */
+	"Bad algorithm",	/* FSL_RETURN_BAD_ALGORITHM_S */
+	"Bad mode",		/* FSL_RETURN_BAD_MODE_S */
+	"Bad flag",		/* FSL_RETURN_BAD_FLAG_S */
+	"Bad key length",	/* FSL_RETURN_BAD_KEY_LENGTH_S */
+	"Bad key parity",	/* FSL_RETURN_BAD_KEY_PARITY_S */
+	"Bad data length",	/* FSL_RETURN_BAD_DATA_LENGTH_S */
+	"Authentication failed",	/* FSL_RETURN_AUTH_FAILED_S */
+	"Memory error",		/* FSL_RETURN_MEMORY_ERROR_S */
+	"Internal error",	/* FSL_RETURN_INTERNAL_ERROR_S */
+	"unknown value",	/* default */
+};
+
+#endif				/* DIAG_DRV_STATUS */
+
+/*!
+ * This lock must be held while performing any queuing or unqueuing functions,
+ * including reading the first pointer on the queue.  It also protects reading
+ * and writing the Sahara DAR register.  It must be held during a read-write
+ * operation on the DAR so that the 'test-and-set' is atomic.
+ */
+os_lock_t desc_queue_lock;
+
+/*! This is the main queue for the driver. This is shared between all threads
+ * and is not protected by mutexes since the kernel is non-preemptable. */
+sah_Queue *main_queue = NULL;
+
+/* Internal Prototypes */
+sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state);
+
+#ifdef DIAG_DRV_STATUS
+void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address);
+#endif
+
+extern wait_queue_head_t *int_queue;
+
+/*!
+ * This function initialises the Queue Manager
+ *
+ * @brief     Initialise the Queue Manager
+ *
+ * @return   FSL_RETURN_OK_S on success; FSL_RETURN_MEMORY_ERROR_S if not
+ */
+fsl_shw_return_t sah_Queue_Manager_Init(void)
+{
+	fsl_shw_return_t ret_val = FSL_RETURN_OK_S;
+
+	desc_queue_lock = os_lock_alloc_init();
+
+	if (main_queue == NULL) {
+		/* Construct the main queue. */
+		main_queue = sah_Queue_Construct();
+
+		if (main_queue == NULL) {
+			ret_val = FSL_RETURN_MEMORY_ERROR_S;
+		}
+	} else {
+#ifdef DIAG_DRV_QUEUE
+		LOG_KDIAG
+		    ("Trying to initialise the queue manager more than once.");
+#endif
+	}
+
+	return ret_val;
+}
+
+/*!
+ * This function closes the Queue Manager
+ *
+ * @brief     Close the Queue Manager
+ *
+ * @return   void
+ */
+void sah_Queue_Manager_Close(void)
+{
+#ifdef DIAG_DRV_QUEUE
+	if (main_queue && main_queue->count != 0) {
+		LOG_KDIAG
+		    ("Trying to close the main queue when it is not empty.");
+	}
+#endif
+
+	if (main_queue) {
+		/* There is no error checking here because there is no way to handle
+		   it. */
+		sah_Queue_Destroy(main_queue);
+		main_queue = NULL;
+	}
+}
+
+/*!
+ * Count the number of entries on the Queue Manager's queue
+ *
+ * @param ignore_state  If non-zero, the @a state parameter is ignored.
+ *                      If zero, only entries matching @a state are counted.
+ * @param state         State of entry to match for counting.
+ *
+ * @return        Number of entries which matched criteria
+ */
+int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state)
+{
+	int count = 0;
+	sah_Head_Desc *current_entry;
+
+	/* Start at the head */
+	current_entry = main_queue->head;
+	while (current_entry != NULL) {
+		if (ignore_state || (current_entry->status == state)) {
+			count++;
+		}
+		/* Jump to the next entry. */
+		current_entry = current_entry->next;
+	}
+
+	return count;
+}
+
+/*!
+ * This function removes an entry from the Queue Manager's queue. The entry to
+ * be removed can be anywhere in the queue.
+ *
+ * @brief     Remove an entry from the Queue Manager's queue.
+ *
+ * @param    entry   A pointer to a sah_Head_Desc to remove from the Queue
+ *                   Manager's queue.
+ *
+ * @pre   The #desc_queue_lock must be held before calling this function.
+ *
+ * @return   void
+ */
+void sah_Queue_Manager_Remove_Entry(sah_Head_Desc * entry)
+{
+	if (entry == NULL) {
+#ifdef DIAG_DRV_QUEUE
+		LOG_KDIAG("NULL pointer input.");
+#endif
+	} else {
+		sah_Queue_Remove_Any_Entry(main_queue, entry);
+	}
+}
+
+/*!
+ * This function appends an entry to the Queue Managers queue. It primes SAHARA
+ * if this entry is the first PENDING entry in the Queue Manager's Queue.
+ *
+ * @brief     Appends an entry to the Queue Manager's queue.
+ *
+ * @param    entry   A pointer to a sah_Head_Desc to append to the Queue
+ *                   Manager's queue.
+ *
+ * @pre   The #desc_queue_lock may not may be held when calling this function.
+ *
+ * @return   void
+ */
+void sah_Queue_Manager_Append_Entry(sah_Head_Desc * entry)
+{
+	sah_Head_Desc *current_entry;
+	os_lock_context_t int_flags;
+
+#ifdef DIAG_DRV_QUEUE
+	if (entry == NULL) {
+		LOG_KDIAG("NULL pointer input.");
+	}
+#endif
+	entry->status = SAH_STATE_PENDING;
+	os_lock_save_context(desc_queue_lock, int_flags);
+	sah_Queue_Append_Entry(main_queue, entry);
+
+	/* Prime SAHARA if the operation that was just appended is the only PENDING
+	 * operation in the queue.
+	 */
+	current_entry = sah_Find_With_State(SAH_STATE_PENDING);
+	if (current_entry != NULL) {
+		if (current_entry == entry) {
+			sah_Queue_Manager_Prime(entry);
+		}
+	}
+
+	os_unlock_restore_context(desc_queue_lock, int_flags);
+}
+
+/*!
+ * This function marks all entries in the Queue Manager's queue with state
+ * SAH_STATE_RESET.
+ *
+ * @brief     Mark all entries with state SAH_STATE_RESET
+ *
+ * @return   void
+ *
+ * @note This feature needs re-visiting
+ */
+void sah_Queue_Manager_Reset_Entries(void)
+{
+	sah_Head_Desc *current_entry = NULL;
+
+	/* Start at the head */
+	current_entry = main_queue->head;
+
+	while (current_entry != NULL) {
+		/* Set the state. */
+		current_entry->status = SAH_STATE_RESET;
+		/* Jump to the next entry. */
+		current_entry = current_entry->next;
+	}
+}
+
+/*!
+ * This function primes SAHARA for the first time or after the queue becomes
+ * empty. Queue lock must have been set by the caller of this routine.
+ *
+ * @brief    Prime SAHARA.
+ *
+ * @param    entry   A pointer to a sah_Head_Desc to Prime SAHARA with.
+ *
+ * @return   void
+ */
+void sah_Queue_Manager_Prime(sah_Head_Desc * entry)
+{
+#ifdef DIAG_DRV_QUEUE
+	LOG_KDIAG("Priming SAHARA");
+	if (entry == NULL) {
+		LOG_KDIAG("Trying to prime SAHARA with a NULL entry pointer.");
+	}
+#endif
+
+#ifndef SUBMIT_MULTIPLE_DARS
+	/* BUG FIX: state machine can transition from Done1 Busy2 directly
+	 * to Idle. To fix that problem, only one DAR is being allowed on
+	 * SAHARA at a time */
+	if (sah_Find_With_State(SAH_STATE_ON_SAHARA) != NULL) {
+		return;
+	}
+#endif
+
+#ifdef SAHARA_POWER_MANAGEMENT
+	/* check that dynamic power management is not asserted */
+    if (!sah_dpm_flag) {
+#endif
+
+	/* Enable the SAHARA Clocks */
+#ifdef DIAG_DRV_IF
+			LOG_KDIAG("SAHARA : Enabling the IPG and AHB clocks\n")
+#endif				/*DIAG_DRV_IF */
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+		mxc_clks_enable(SAHARA2_CLK);
+#else
+		{
+			struct clk *clk = clk_get(NULL, "sahara_clk");
+			if (clk != ERR_PTR(ENOENT))
+				clk_enable(clk);
+			clk_put(clk);
+		}
+#endif
+
+		/* Make sure nothing is in the DAR */
+		if (sah_HW_Read_DAR() == 0) {
+#if defined(DIAG_DRV_IF)
+			sah_Dump_Chain(&entry->desc, entry->desc.dma_addr);
+#endif				/* DIAG_DRV_IF */
+
+			sah_HW_Write_DAR((entry->desc.dma_addr));
+			entry->status = SAH_STATE_ON_SAHARA;
+		}
+#ifdef DIAG_DRV_QUEUE
+		else {
+			LOG_KDIAG("DAR should be empty when Priming SAHARA");
+		}
+#endif
+#ifdef SAHARA_POWER_MANAGEMENT
+	}
+#endif
+}
+
+#ifndef SAHARA_POLL_MODE
+
+/*!
+ * Reset SAHARA, then load the next descriptor on it, if one exists
+ */
+void sah_reset_sahara_request(void)
+{
+	sah_Head_Desc *desc;
+	os_lock_context_t lock_flags;
+
+#ifdef DIAG_DRV_STATUS
+	LOG_KDIAG("Sahara required reset from tasklet, replace chip");
+#endif
+	sah_HW_Reset();
+
+	/* Now stick in a waiting request */
+	os_lock_save_context(desc_queue_lock, lock_flags);
+	if ((desc = sah_Find_With_State(SAH_STATE_PENDING))) {
+		sah_Queue_Manager_Prime(desc);
+	}
+	os_unlock_restore_context(desc_queue_lock, lock_flags);
+}
+
+/*!
+ * Post-process a descriptor chain after the hardware has finished with it.
+ *
+ * The status of the descriptor could also be checked.  (for FATAL or IGNORED).
+ *
+ * @param     desc_head   The finished chain
+ * @param     error       A boolean to mark whether hardware reported error
+ *
+ * @pre   The #desc_queue_lock may not be held when calling this function.
+ */
+void sah_process_finished_request(sah_Head_Desc * desc_head, unsigned error)
+{
+	os_lock_context_t lock_flags;
+
+	if (!error) {
+		desc_head->result = FSL_RETURN_OK_S;
+	} else if (desc_head->error_status == -1) {
+		/* Disaster!  Sahara has faulted */
+		desc_head->result = FSL_RETURN_ERROR_S;
+	} else {
+		/* translate from SAHARA error status to fsl_shw return values */
+		desc_head->result =
+		    sah_convert_error_status(desc_head->error_status);
+#ifdef DIAG_DRV_STATUS
+		sah_Log_Error(desc_head->current_dar, desc_head->error_status,
+			      desc_head->fault_address);
+#endif
+	}
+
+	/* Show that the request has been processd */
+	desc_head->status = error ? SAH_STATE_FAILED : SAH_STATE_COMPLETE;
+
+	if (desc_head->uco_flags & FSL_UCO_BLOCKING_MODE) {
+
+		/* Wake up all processes on Sahara queue */
+		wake_up_interruptible(int_queue);
+
+	} else {
+		os_lock_save_context(desc_queue_lock, lock_flags);
+		sah_Queue_Append_Entry(&desc_head->user_info->result_pool,
+				       desc_head);
+		os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+		/* perform callback */
+		if (desc_head->uco_flags & FSL_UCO_CALLBACK_MODE) {
+			desc_head->user_info->callback(desc_head->user_info);
+		}
+	}
+}				/* sah_process_finished_request */
+
+/*! Called from bottom half.
+ *
+ * @pre   The #desc_queue_lock may not be held when calling this function.
+ */
+void sah_postprocess_queue(unsigned long reset_flag)
+{
+
+	/* if SAHARA needs to be reset, do it here. This starts a descriptor chain
+	 * if one is ready also */
+	if (reset_flag) {
+		sah_reset_sahara_request();
+	}
+
+	/* now handle the descriptor chain(s) that has/have completed */
+	do {
+		sah_Head_Desc *first_entry;
+		os_lock_context_t lock_flags;
+
+		os_lock_save_context(desc_queue_lock, lock_flags);
+
+		first_entry = main_queue->head;
+		if ((first_entry != NULL) &&
+		    (first_entry->status == SAH_STATE_OFF_SAHARA)) {
+			sah_Queue_Remove_Entry(main_queue);
+			os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+			sah_process_finished_request(first_entry,
+						     (first_entry->
+						      error_status != 0));
+		} else {
+			os_unlock_restore_context(desc_queue_lock, lock_flags);
+			break;
+		}
+	} while (1);
+
+	return;
+}
+
+#endif				/* ifndef SAHARA_POLL_MODE */
+
+/*!
+ * This is a helper function for Queue Manager. This function finds the first
+ * entry in the Queue Manager's queue whose state matches the given input
+ * state. This function starts at the head of the queue and works towards the
+ * tail. If a matching entry was found, the address of the entry is returned.
+ *
+ * @brief     Handle the IDLE state.
+ *
+ * @param    state   A sah_Queue_Status value.
+ *
+ * @pre   The #desc_queue_lock must be held before calling this function.
+ *
+ * @return   A pointer to a sah_Head_Desc that matches the given state.
+ * @return   NULL otherwise.
+ */
+sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state)
+{
+	sah_Head_Desc *current_entry = NULL;
+	sah_Head_Desc *ret_val = NULL;
+	int done_looping = FALSE;
+
+	/* Start at the head */
+	current_entry = main_queue->head;
+
+	while ((current_entry != NULL) && (done_looping == FALSE)) {
+		if (current_entry->status == state) {
+			done_looping = TRUE;
+			ret_val = current_entry;
+		}
+		/* Jump to the next entry. */
+		current_entry = current_entry->next;
+	}
+
+	return ret_val;
+}				/* sah_postprocess_queue */
+
+/*!
+ * Process the value from the Sahara error status register and convert it into
+ * an FSL SHW API error code.
+ *
+ * Warning, this routine must only be called if an error exists.
+ *
+ * @param error_status   The value from the error status register.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_convert_error_status(uint32_t error_status)
+{
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;	/* catchall */
+	uint8_t error_source;
+	uint8_t DMA_error_status;
+	uint8_t DMA_error_size;
+
+	/* get the error source from the error status register */
+	error_source = error_status & SAH_ERROR_MASK;
+
+	/* array size is maximum allowed by mask, so no boundary checking is
+	 * needed here */
+	ret = sah_Execute_Error_Array[error_source];
+
+	/* is this one that needs additional fields checked to determine the
+	 * error condition? */
+	if (ret == SHA_ERROR_STATUS_CONTINUE) {
+		/* check the DMA fields */
+		if (error_source == SAH_ERR_DMA) {
+			/* get the DMA transfer error size. If this indicates that no
+			 * error was detected, something is seriously wrong */
+			DMA_error_size =
+			    (error_status >> 9) & SAH_DMA_ERR_SIZE_MASK;
+			if (DMA_error_size == SAH_DMA_NO_ERR) {
+				ret = FSL_RETURN_INTERNAL_ERROR_S;
+			} else {
+				/* get DMA error status */
+				DMA_error_status = (error_status >> 12) &
+				    SAH_DMA_ERR_STATUS_MASK;
+
+				/* the DMA error bits cover all the even numbers. By dividing
+				 * by 2 it can be used as an index into the error array */
+				ret =
+				    sah_DMA_Error_Status_Array[DMA_error_status
+							       >> 1];
+			}
+		} else {	/* not SAH_ERR_DMA, so must be SAH_ERR_CHA */
+			uint16_t CHA_error_status;
+			uint8_t CHA_error_source;
+
+			/* get CHA Error Source. If this indicates that no error was
+			 * detected, something is seriously wrong */
+			CHA_error_source =
+			    (error_status >> 28) & SAH_CHA_ERR_SOURCE_MASK;
+			if (CHA_error_source == SAH_CHA_NO_ERROR) {
+				ret = FSL_RETURN_INTERNAL_ERROR_S;
+			} else {
+				uint32_t mask = 1;
+				uint32_t count = 0;
+
+				/* get CHA Error Status */
+				CHA_error_status = (error_status >> 16) &
+				    SAH_CHA_ERR_STATUS_MASK;
+
+				/* If more than one bit is set (which shouldn't happen), only
+				 * the first will be captured */
+				if (CHA_error_status != 0) {
+					count = 1;
+					while (CHA_error_status != mask) {
+						++count;
+						mask <<= 1;
+					}
+				}
+
+				ret = sah_CHA_Error_Status_Array[count];
+			}
+		}
+	}
+
+	return ret;
+}
+
+fsl_shw_return_t sah_convert_op_status(uint32_t op_status)
+{
+	unsigned op_source = (op_status >> 28) & 0x7;
+	unsigned op_detail = op_status & 0x3f;
+	fsl_shw_return_t ret = FSL_RETURN_ERROR_S;
+
+	switch (op_source) {
+	case 1:		/* SKHA */
+		/* Can't this have "ICV" error from CCM ?? */
+		break;
+	case 2:		/* MDHA */
+		if (op_detail == 1) {
+			ret = FSL_RETURN_AUTH_FAILED_S;
+		}
+		break;
+	case 3:		/* RNGA */
+		/* Self-test and Compare errors... what to do? */
+		break;
+	case 4:		/* PKHA */
+		switch (op_detail) {
+		case 0x01:
+			ret = FSL_RETURN_PRIME_S;
+			break;
+		case 0x02:
+			ret = FSL_RETURN_NOT_PRIME_S;
+			break;
+		case 0x04:
+			ret = FSL_RETURN_POINT_AT_INFINITY_S;
+			break;
+		case 0x08:
+			ret = FSL_RETURN_POINT_NOT_AT_INFINITY_S;
+			break;
+		case 0x10:
+			ret = FSL_RETURN_GCD_IS_ONE_S;
+			break;
+		case 0x20:
+			ret = FSL_RETURN_GCD_IS_NOT_ONE_S;
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+#ifdef DIAG_DRV_STATUS
+
+/*!
+ * This function logs the diagnostic information for the given error and
+ * descriptor address.  Only used for diagnostic purposes.
+ *
+ * @brief    (debug only) Log a description of hardware-detected error.
+ *
+ * @param    descriptor    The descriptor address that caused the error
+ * @param    error         The SAHARA error code
+ * @param    fault_address Value from the Fault address register
+ *
+ * @return   void
+ */
+void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address)
+{
+	char *source_text;	/* verbose error source from register */
+	char *address;		/* string buffer for descriptor address */
+	char *error_log;	/* the complete logging message */
+	char *cha_log = NULL;	/* string buffer for descriptor address */
+	char *dma_log = NULL;	/* string buffer for descriptor address */
+
+	uint16_t cha_error = 0;
+	uint16_t dma_error = 0;
+
+	uint8_t error_source;
+	sah_Execute_Error return_code;
+
+	/* log error code and descriptor address */
+	error_source = error & SAH_ERROR_MASK;
+	return_code = sah_Execute_Error_Array[error_source];
+
+	source_text = os_alloc_memory(64, GFP_KERNEL);
+
+	switch (error_source) {
+	case SAH_ERR_HEADER:
+		sprintf(source_text, "%s", "Header is not valid");
+		break;
+
+	case SAH_ERR_DESC_LENGTH:
+		sprintf(source_text, "%s",
+			"Descriptor length not equal to sum of link lengths");
+		break;
+
+	case SAH_ERR_DESC_POINTER:
+		sprintf(source_text, "%s", "Length or pointer "
+			"field is zero while the other is non-zero");
+		break;
+
+	case SAH_ERR_LINK_LENGTH:
+		/* note that the Sahara Block Guide 2.7 has an invalid explaination
+		 * of this. It only happens when a link length is zero */
+		sprintf(source_text, "%s", "A data length is a link is zero");
+		break;
+
+	case SAH_ERR_LINK_POINTER:
+		sprintf(source_text, "%s",
+			"The data pointer in a link is zero");
+		break;
+
+	case SAH_ERR_INPUT_BUFFER:
+		sprintf(source_text, "%s", "Input Buffer reported an overflow");
+		break;
+
+	case SAH_ERR_OUTPUT_BUFFER:
+		sprintf(source_text, "%s",
+			"Output Buffer reported an underflow");
+		break;
+
+	case SAH_ERR_OUTPUT_BUFFER_STARVATION:
+		sprintf(source_text, "%s", "Incorrect data in output "
+			"buffer after CHA has signalled 'done'");
+		break;
+
+	case SAH_ERR_INTERNAL_STATE:
+		sprintf(source_text, "%s", "Internal Hardware Failure");
+		break;
+
+	case SAH_ERR_GENERAL_DESCRIPTOR:
+		sprintf(source_text, "%s",
+			"Current Descriptor was not legal, but cause is unknown");
+		break;
+
+	case SAH_ERR_RESERVED_FIELDS:
+		sprintf(source_text, "%s",
+			"Reserved pointer field is non-zero");
+		break;
+
+	case SAH_ERR_DESCRIPTOR_ADDRESS:
+		sprintf(source_text, "%s",
+			"Descriptor address not word aligned");
+		break;
+
+	case SAH_ERR_LINK_ADDRESS:
+		sprintf(source_text, "%s", "Link address not word aligned");
+		break;
+
+	case SAH_ERR_CHA:
+		sprintf(source_text, "%s", "CHA Error");
+		{
+			char *cha_module = os_alloc_memory(5, GFP_KERNEL);
+			char *cha_text = os_alloc_memory(45, GFP_KERNEL);
+
+			cha_error = (error >> 28) & SAH_CHA_ERR_SOURCE_MASK;
+
+			switch (cha_error) {
+			case SAH_CHA_SKHA_ERROR:
+				sprintf(cha_module, "%s", "SKHA");
+				break;
+
+			case SAH_CHA_MDHA_ERROR:
+				sprintf(cha_module, "%s", "MDHA");
+				break;
+
+			case SAH_CHA_RNG_ERROR:
+				sprintf(cha_module, "%s", "RNG ");
+				break;
+
+			case SAH_CHA_PKHA_ERROR:
+				sprintf(cha_module, "%s", "PKHA");
+				break;
+
+			case SAH_CHA_NO_ERROR:
+				/* can't happen */
+				/* no break */
+			default:
+				sprintf(cha_module, "%s", "????");
+				break;
+			}
+
+			cha_error = (error >> 16) & SAH_CHA_ERR_STATUS_MASK;
+
+			/* Log CHA Error Status */
+			switch (cha_error) {
+			case SAH_CHA_IP_BUF:
+				sprintf(cha_text, "%s",
+					"Non-empty input buffer when done");
+				break;
+
+			case SAH_CHA_ADD_ERR:
+				sprintf(cha_text, "%s", "Illegal address");
+				break;
+
+			case SAH_CHA_MODE_ERR:
+				sprintf(cha_text, "%s", "Illegal mode");
+				break;
+
+			case SAH_CHA_DATA_SIZE_ERR:
+				sprintf(cha_text, "%s", "Illegal data size");
+				break;
+
+			case SAH_CHA_KEY_SIZE_ERR:
+				sprintf(cha_text, "%s", "Illegal key size");
+				break;
+
+			case SAH_CHA_PROC_ERR:
+				sprintf(cha_text, "%s",
+					"Mode/Context/Key written during processing");
+				break;
+
+			case SAH_CHA_CTX_READ_ERR:
+				sprintf(cha_text, "%s",
+					"Context read during processing");
+				break;
+
+			case SAH_CHA_INTERNAL_HW_ERR:
+				sprintf(cha_text, "%s", "Internal hardware");
+				break;
+
+			case SAH_CHA_IP_BUFF_ERR:
+				sprintf(cha_text, "%s",
+					"Input buffer not enabled or underflow");
+				break;
+
+			case SAH_CHA_OP_BUFF_ERR:
+				sprintf(cha_text, "%s",
+					"Output buffer not enabled or overflow");
+				break;
+
+			case SAH_CHA_DES_KEY_ERR:
+				sprintf(cha_text, "%s", "DES key parity error");
+				break;
+
+			case SAH_CHA_RES:
+				sprintf(cha_text, "%s", "Reserved");
+				break;
+
+			case SAH_CHA_NO_ERR:
+				/* can't happen */
+				/* no break */
+			default:
+				sprintf(cha_text, "%s", "Unknown error");
+				break;
+			}
+
+			cha_log = os_alloc_memory(90, GFP_KERNEL);
+			sprintf(cha_log,
+				"  Module %s encountered the error: %s.",
+				cha_module, cha_text);
+
+			os_free_memory(cha_module);
+			os_free_memory(cha_text);
+
+			{
+				uint32_t mask = 1;
+				uint32_t count = 0;
+
+				if (cha_error != 0) {
+					count = 1;
+					while (cha_error != mask) {
+						++count;
+						mask <<= 1;
+					}
+				}
+
+				return_code = sah_CHA_Error_Status_Array[count];
+			}
+			cha_error = 1;
+		}
+		break;
+
+	case SAH_ERR_DMA:
+		sprintf(source_text, "%s", "DMA Error");
+		{
+			char *dma_direction = os_alloc_memory(6, GFP_KERNEL);
+			char *dma_size = os_alloc_memory(14, GFP_KERNEL);
+			char *dma_text = os_alloc_memory(250, GFP_KERNEL);
+
+			if ((dma_direction == NULL) || (dma_size == NULL) ||
+			    (dma_text == NULL)) {
+				LOG_KDIAG
+				    ("No memory allocated for DMA debug messages\n");
+			}
+
+			/* log DMA error direction */
+			sprintf(dma_direction, "%s",
+				(((error >> 8) & SAH_DMA_ERR_DIR_MASK) == 1) ?
+				"read" : "write");
+
+			/* log the size of the DMA transfer error */
+			dma_error = (error >> 9) & SAH_DMA_ERR_SIZE_MASK;
+			switch (dma_error) {
+			case SAH_DMA_SIZE_BYTE:
+				sprintf(dma_size, "%s", "byte");
+				break;
+
+			case SAH_DMA_SIZE_HALF_WORD:
+				sprintf(dma_size, "%s", "half-word");
+				break;
+
+			case SAH_DMA_SIZE_WORD:
+				sprintf(dma_size, "%s", "word");
+				break;
+
+			case SAH_DMA_SIZE_RES:
+				sprintf(dma_size, "%s", "reserved size");
+				break;
+
+			default:
+				sprintf(dma_size, "%s", "unknown size");
+				break;
+			}
+
+			/* log DMA error status */
+			dma_error = (error >> 12) & SAH_DMA_ERR_STATUS_MASK;
+			switch (dma_error) {
+			case SAH_DMA_NO_ERR:
+				sprintf(dma_text, "%s", "No DMA Error Code");
+				break;
+
+			case SAH_DMA_AHB_ERR:
+				sprintf(dma_text, "%s",
+					"AHB terminated a bus cycle with an error");
+				break;
+
+			case SAH_DMA_IP_ERR:
+				sprintf(dma_text, "%s",
+					"Internal IP bus cycle was terminated with an "
+					"error termination. This would likely be "
+					"caused by a descriptor length being too "
+					"large, and thus accessing an illegal "
+					"internal address. Verify the length field "
+					"of the current descriptor");
+				break;
+
+			case SAH_DMA_PARITY_ERR:
+				sprintf(dma_text, "%s",
+					"Parity error detected on DMA command from "
+					"Descriptor Decoder. Cause is likely to be "
+					"internal hardware fault");
+				break;
+
+			case SAH_DMA_BOUNDRY_ERR:
+				sprintf(dma_text, "%s",
+					"DMA was requested to cross a 256 byte "
+					"internal address boundary. Cause is likely a "
+					"descriptor length being too large, thus "
+					"accessing two different internal hardware "
+					"blocks");
+				break;
+
+			case SAH_DMA_BUSY_ERR:
+				sprintf(dma_text, "%s",
+					"Descriptor Decoder has made a DMA request "
+					"while the DMA controller is busy. Cause is "
+					"likely due to hardware fault");
+				break;
+
+			case SAH_DMA_RESERVED_ERR:
+				sprintf(dma_text, "%s", "Reserved");
+				break;
+
+			case SAH_DMA_INT_ERR:
+				sprintf(dma_text, "%s",
+					"Internal DMA hardware error detected. The "
+					"DMA controller has detected an internal "
+					"condition which should never occur");
+				break;
+
+			default:
+				sprintf(dma_text, "%s",
+					"Unknown DMA Error Status Code");
+				break;
+			}
+
+			return_code =
+			    sah_DMA_Error_Status_Array[dma_error >> 1];
+			dma_error = 1;
+
+			dma_log = os_alloc_memory(320, GFP_KERNEL);
+			sprintf(dma_log,
+				"  Occurred during a %s operation of a %s transfer: %s.",
+				dma_direction, dma_size, dma_text);
+
+			os_free_memory(dma_direction);
+			os_free_memory(dma_size);
+			os_free_memory(dma_text);
+		}
+		break;
+
+	case SAH_ERR_NONE:
+	default:
+		sprintf(source_text, "%s", "Unknown Error Code");
+		break;
+	}
+
+	address = os_alloc_memory(35, GFP_KERNEL);
+
+	/* convert error & descriptor address to strings */
+	if (dma_error) {
+		sprintf(address, "Fault address is 0x%08x", fault_address);
+	} else {
+		sprintf(address, "Descriptor bus address is 0x%08x",
+			descriptor);
+	}
+
+	if (return_code > FSL_INVALID_RETURN) {
+		return_code = FSL_INVALID_RETURN;
+	}
+
+	error_log = os_alloc_memory(250, GFP_KERNEL);
+
+	/* construct final log message */
+	sprintf(error_log, "Error source = 0x%08x. Return = %s. %s. %s.",
+		error, sah_return_text[return_code], address, source_text);
+
+	os_free_memory(source_text);
+	os_free_memory(address);
+
+	/* log standard messages */
+	LOG_KDIAG(error_log);
+	os_free_memory(error_log);
+
+	/* add additional information if available */
+	if (cha_error) {
+		LOG_KDIAG(cha_log);
+		os_free_memory(cha_log);
+	}
+
+	if (dma_error) {
+		LOG_KDIAG(dma_log);
+		os_free_memory(dma_log);
+	}
+
+	return;
+}				/* sah_Log_Error */
+
+#endif				/* DIAG_DRV_STATUS */
+
+/* End of sah_queue_manager.c */
diff --git a/drivers/mxc/security/sahara2/sah_status_manager.c b/drivers/mxc/security/sahara2/sah_status_manager.c
new file mode 100644
index 000000000000..7791f5c45c93
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sah_status_manager.c
@@ -0,0 +1,734 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+* @file sah_status_manager.c
+*
+* @brief Status Manager Function
+*
+* This file contains the function which processes the Sahara status register
+* during an interrupt.
+*
+* This file does not need porting.
+*/
+
+#include "portable_os.h"
+
+#include <sah_status_manager.h>
+#include <sah_hardware_interface.h>
+#include <sah_queue_manager.h>
+#include <sah_memory_mapper.h>
+#include <sah_kernel.h>
+
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+#include <diagnostic.h>
+#endif
+
+/*! Compile-time flag to count various interrupt types. */
+#define DIAG_INT_COUNT
+
+/*!
+ * Number of interrupts processed with Done1Done2 status.  Updates to this
+ * value should only be done in interrupt processing.
+ */
+uint32_t done1_count;
+
+/*!
+ * Number of interrupts processed with Done1Busy2 status.  Updates to this
+ * value should only be done in interrupt processing.
+ */
+uint32_t done1busy2_count;
+
+/*!
+ * Number of interrupts processed with Done1Done2 status.  Updates to this
+ * value should only be done in interrupt processing.
+ */
+uint32_t done1done2_count;
+
+/*!
+ * the dynameic power management flag is false when power management is not
+ * asserted and true when dpm is.
+ */
+#ifdef SAHARA_POWER_MANAGEMENT
+bool sah_dpm_flag = FALSE;
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level);
+static int sah_dpm_resume(struct device *dev, uint32_t level);
+#else
+static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state);
+static int sah_dpm_resume(struct platform_device *dev);
+#endif
+#endif
+
+#ifndef SAHARA_POLL_MODE
+/*!
+*******************************************************************************
+* This functionx processes the status register of the Sahara, updates the state
+* of the finished queue entry, and then tries to find more work for Sahara to
+* do.
+*
+* @brief    The bulk of the interrupt handling code.
+*
+* @param   hw_status     The status register of Sahara at time of interrupt.
+*                        The Clear interrupt bit is already handled by this
+*                        register read prior to entry into this function.
+* @return   void
+*/
+unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status)
+{
+	unsigned long reset_flag = 0;	/* assume no SAHARA reset needed */
+	os_lock_context_t lock_flags;
+	sah_Head_Desc *current_entry;
+
+	/* HW status at time of interrupt */
+	sah_Execute_Status state = hw_status & SAH_EXEC_STATE_MASK;
+
+	do {
+		uint32_t dar;
+
+#ifdef DIAG_INT_COUNT
+		if (state == SAH_EXEC_DONE1) {
+			done1_count++;
+		} else if (state == SAH_EXEC_DONE1_BUSY2) {
+			done1busy2_count++;
+		} else if (state == SAH_EXEC_DONE1_DONE2) {
+			done1done2_count++;
+		}
+#endif
+
+		/* if the first entry on sahara has completed... */
+		if ((state & SAH_EXEC_DONE1_BIT) ||
+		    (state == SAH_EXEC_ERROR1)) {
+			/* lock queue while searching */
+			os_lock_save_context(desc_queue_lock, lock_flags);
+			current_entry =
+			    sah_Find_With_State(SAH_STATE_ON_SAHARA);
+			os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+			/* an active descriptor was not found */
+			if (current_entry == NULL) {
+				/* change state to avoid an infinite loop (possible if
+				 * state is SAH_EXEC_DONE1_BUSY2 first time into loop) */
+				hw_status = SAH_EXEC_IDLE;
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+				LOG_KDIAG
+				    ("Interrupt received with nothing on queue.");
+#endif
+			} else {
+				/* SAHARA has completed its work on this descriptor chain */
+				current_entry->status = SAH_STATE_OFF_SAHARA;
+
+				if (state == SAH_EXEC_ERROR1) {
+				   if (hw_status & STATUS_ERROR) {
+					  /* Gather extra diagnostic information */
+					  current_entry->fault_address =
+					    sah_HW_Read_Fault_Address();
+					  /* Read this last - it clears the error */
+					  current_entry->error_status =
+					    sah_HW_Read_Error_Status();
+					  current_entry->op_status = 0;
+#ifdef FSL_HAVE_SAHARA4
+				   } else {
+					  current_entry->op_status =
+							sah_HW_Read_Op_Status();
+					  current_entry->error_status = 0;
+#endif
+				   }
+
+				} else {
+					/* indicate that no errors were found with descriptor
+					 * chain 1 */
+					current_entry->error_status = 0;
+					current_entry->op_status = 0;
+
+					/* is there a second, successfully, completed descriptor
+					 * chain? (done1/error2 processing is handled later) */
+					if (state == SAH_EXEC_DONE1_DONE2) {
+						os_lock_save_context
+						    (desc_queue_lock,
+						     lock_flags);
+						current_entry =
+						    sah_Find_With_State
+						    (SAH_STATE_ON_SAHARA);
+						os_unlock_restore_context
+						    (desc_queue_lock,
+						     lock_flags);
+
+						if (current_entry == NULL) {
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+							LOG_KDIAG
+							    ("Done1_Done2 Interrupt received with "
+							     "one entry on queue.");
+#endif
+						} else {
+							/* indicate no errors in descriptor chain 2 */
+							current_entry->
+							    error_status = 0;
+							current_entry->status =
+							    SAH_STATE_OFF_SAHARA;
+						}
+					}
+				}
+			}
+
+#ifdef SAHARA_POWER_MANAGEMENT
+			/* check dynamic power management is not asserted */
+			if (!sah_dpm_flag) {
+#endif
+				do {
+					/* protect DAR and main_queue */
+					os_lock_save_context(desc_queue_lock,
+							     lock_flags);
+					dar = sah_HW_Read_DAR();
+					/* check if SAHARA has space for another descriptor. SAHARA
+					 * only accepts up to the DAR queue size number of DAR
+					 * entries, after that 'dar' will not be zero until the
+					 * pending interrupt is serviced */
+					if (dar == 0) {
+						current_entry =
+						    sah_Find_With_State
+						    (SAH_STATE_PENDING);
+						if (current_entry != NULL) {
+#ifndef SUBMIT_MULTIPLE_DARS
+							/* BUG FIX: state machine can transition from Done1
+							 * Busy2 directly to Idle. To fix that problem,
+							 * only one DAR is being allowed on SAHARA at a
+							 * time.  If a high level interrupt has happened,
+							 * there could * be an active descriptor chain */
+							if (sah_Find_With_State
+							    (SAH_STATE_ON_SAHARA)
+							    == NULL) {
+#endif
+#if defined(DIAG_DRV_IF) && defined(DIAG_DURING_INTERRUPT)
+								sah_Dump_Chain
+								    (&current_entry->
+								     desc,
+								     current_entry->
+								     desc.
+								     dma_addr);
+#endif				/* DIAG_DRV_IF */
+								sah_HW_Write_DAR
+								    (current_entry->
+								     desc.
+								     dma_addr);
+								current_entry->
+								    status =
+								    SAH_STATE_ON_SAHARA;
+#ifndef SUBMIT_MULTIPLE_DARS
+							}
+							current_entry = NULL;	/* exit loop */
+#endif
+						}
+					}
+					os_unlock_restore_context
+					    (desc_queue_lock, lock_flags);
+				} while ((dar == 0) && (current_entry != NULL));
+#ifdef SAHARA_POWER_MANAGEMENT
+			}	/* sah_device_power_manager */
+#endif
+		} else {
+			if (state == SAH_EXEC_FAULT) {
+				sah_Head_Desc *previous_entry;	/* point to chain 1 */
+				/* Address of request when fault occured */
+				uint32_t bad_dar = sah_HW_Read_IDAR();
+
+				reset_flag = 1;	/* SAHARA needs to be reset */
+
+				/* get first of possible two descriptor chain that was
+				 * on SAHARA */
+				os_lock_save_context(desc_queue_lock,
+						     lock_flags);
+				previous_entry =
+				    sah_Find_With_State(SAH_STATE_ON_SAHARA);
+				os_unlock_restore_context(desc_queue_lock,
+							  lock_flags);
+
+				/* if it exists, continue processing the fault */
+				if (previous_entry) {
+					/* assume this chain didn't complete correctly */
+					previous_entry->error_status = -1;
+					previous_entry->status =
+					    SAH_STATE_OFF_SAHARA;
+
+					/* get the second descriptor chain */
+					os_lock_save_context(desc_queue_lock,
+							     lock_flags);
+					current_entry =
+					    sah_Find_With_State
+					    (SAH_STATE_ON_SAHARA);
+					os_unlock_restore_context
+					    (desc_queue_lock, lock_flags);
+
+					/* if it exists, continue processing both chains */
+					if (current_entry) {
+						/* assume this chain didn't complete correctly */
+						current_entry->error_status =
+						    -1;
+						current_entry->status =
+						    SAH_STATE_OFF_SAHARA;
+
+						/* now see if either can be identified as the one
+						 * in progress when the fault occured */
+						if (current_entry->desc.
+						    dma_addr == bad_dar) {
+							/* the second descriptor chain was active when the
+							 * fault occured, so the first descriptor chain
+							 * was successfull */
+							previous_entry->
+							    error_status = 0;
+						} else {
+							if (previous_entry->
+							    desc.dma_addr ==
+							    bad_dar) {
+								/* if the first chain was in progress when the
+								 * fault occured, the second has not yet been
+								 * touched, so reset it to PENDING */
+								current_entry->
+								    status =
+								    SAH_STATE_PENDING;
+							}
+						}
+					}
+				}
+#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT)
+			} else {
+				/* shouldn't ever get here */
+				if (state == SAH_EXEC_BUSY) {
+					LOG_KDIAG
+					    ("Got Sahara interrupt in Busy state");
+				} else {
+					if (state == SAH_EXEC_IDLE) {
+						LOG_KDIAG
+						    ("Got Sahara interrupt in Idle state");
+					} else {
+						LOG_KDIAG
+						    ("Got Sahara interrupt in unknown state");
+					}
+				}
+#endif
+			}
+		}
+
+		/* haven't handled the done1/error2 (the error 2 part), so setup to
+		 * do that now. Otherwise, exit loop */
+		state = (state == SAH_EXEC_DONE1_ERROR2) ?
+		    SAH_EXEC_ERROR1 : SAH_EXEC_IDLE;
+
+		/* Keep going while further status is available. */
+	} while (state == SAH_EXEC_ERROR1);
+
+    /* Disabling Sahara Clock only if the hardware is in idle state and
+	    the DAR queue is empty.*/
+	os_lock_save_context(desc_queue_lock, lock_flags);
+	current_entry = sah_Find_With_State(SAH_STATE_ON_SAHARA);
+	os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+	if ((current_entry == NULL) && (state == SAH_EXEC_IDLE)) {
+
+#ifdef DIAG_DRV_IF
+		LOG_KDIAG("SAHARA : Disabling the clocks\n")
+#endif				/* DIAG_DRV_IF */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+		mxc_clks_disable(SAHARA2_CLK);
+#else
+		{
+			struct clk *clk = clk_get(NULL, "sahara_clk");
+			if (clk != ERR_PTR(ENOENT))
+				clk_disable(clk);
+			clk_put(clk);
+		}
+#endif
+
+	}
+
+	return reset_flag;
+}
+
+#endif				/* ifndef SAHARA_POLL_MODE */
+
+#ifdef SAHARA_POLL_MODE
+/*!
+*******************************************************************************
+* Submits descriptor chain to SAHARA, polls on SAHARA for completion, process
+* results, and dephysicalizes chain
+*
+* @brief     Handle poll mode.
+*
+* @param    entry   Virtual address of a physicalized chain
+*
+* @return   0      this function is always successful
+*/
+
+unsigned long sah_Handle_Poll(sah_Head_Desc * entry)
+{
+	sah_Execute_Status hw_status;	/* Sahara's status register */
+	os_lock_context_t lock_flags;
+
+	/* lock SARAHA */
+	os_lock_save_context(desc_queue_lock, lock_flags);
+
+#ifdef SAHARA_POWER_MANAGEMENT
+	/* check if the dynamic power management is asserted */
+	if (sah_dpm_flag) {
+		/* return that request failed to be processed */
+		entry->result = FSL_RETURN_ERROR_S;
+		entry->fault_address = 0xBAD;
+		entry->op_status= 0xBAD;
+		entry->error_status = 0xBAD;
+	} else {
+#endif				/* SAHARA_POWER_MANAGEMENT */
+
+#if defined(DIAG_DRV_IF)
+		sah_Dump_Chain(&entry->desc, entry->desc.dma_addr);
+#endif				/* DIAG_DRV_IF */
+		/* Nothing can be in the dar if we got the lock */
+		sah_HW_Write_DAR((uint32_t) (entry->desc.dma_addr));
+
+		/* Wait for SAHARA to finish with this entry */
+		hw_status = sah_Wait_On_Sahara();
+
+		/* if entry completed successfully, mark it as such */
+	/**** HARDWARE ERROR WORK AROUND (hw_status == SAH_EXEC_IDLE) *****/
+		if (
+#ifndef SUBMIT_MULTIPLE_DARS
+			   (hw_status == SAH_EXEC_IDLE) || (hw_status == SAH_EXEC_DONE1_BUSY2) ||	/* should not happen */
+#endif
+			   (hw_status == SAH_EXEC_DONE1)
+		    ) {
+			entry->error_status = 0;
+			entry->result = FSL_RETURN_OK_S;
+		} else {
+			/* SAHARA is reporting an error with entry */
+			if (hw_status == SAH_EXEC_ERROR1) {
+				/* Gather extra diagnostic information */
+				entry->fault_address =
+				    sah_HW_Read_Fault_Address();
+				/* Read this register last - it clears the error */
+				entry->error_status =
+				    sah_HW_Read_Error_Status();
+				entry->op_status = 0;
+				/* translate from SAHARA error status to fsl_shw return values */
+				entry->result =
+				    sah_convert_error_status(entry->
+							     error_status);
+#ifdef DIAG_DRV_STATUS
+				sah_Log_Error(entry->op_status,
+					      entry->error_status,
+					      entry->fault_address);
+#endif
+			} else if (hw_status == SAH_EXEC_OPSTAT1) {
+				entry->op_status = sah_HW_Read_Op_Status();
+				entry->error_status = 0;
+				entry->result =
+				    sah_convert_op_status(op_status);
+			} else {
+				/* SAHARA entered FAULT state (or something bazaar has
+				 * happened) */
+				pr_debug
+					("Sahara: hw_status = 0x%x; Stat: 0x%08x; IDAR: 0x%08x; "
+					 "CDAR: 0x%08x; FltAdr: 0x%08x; Estat: 0x%08x\n",
+					 hw_status, sah_HW_Read_Status(),
+					 sah_HW_Read_IDAR(), sah_HW_Read_CDAR(),
+					 sah_HW_Read_Fault_Address(),
+					 sah_HW_Read_Error_Status());
+#ifdef DIAG_DRV_IF
+				{
+					int old_level = console_loglevel;
+					console_loglevel = 8;
+					sah_Dump_Chain(&(entry->desc),
+							   entry->desc.dma_addr);
+					console_loglevel = old_level;
+				}
+#endif
+
+				entry->error_status = -1;
+				entry->result = FSL_RETURN_ERROR_S;
+				sah_HW_Reset();
+			}
+		}
+#ifdef SAHARA_POWER_MANAGEMENT
+	}
+#endif
+
+	if (!(entry->uco_flags & FSL_UCO_BLOCKING_MODE)) {
+		/* put it in results pool to allow get_results to work */
+		sah_Queue_Append_Entry(&entry->user_info->result_pool, entry);
+		if (entry->uco_flags & FSL_UCO_CALLBACK_MODE) {
+			/* invoke callback */
+			entry->user_info->callback(entry->user_info);
+		}
+	} else {
+		/* convert the descriptor link back to virtual memory, mark dirty pages
+		 * if they are from user mode, and release the page cache for user
+		 * pages
+		 */
+		entry = sah_DePhysicalise_Descriptors(entry);
+	}
+
+	os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+	return 0;
+}
+
+#endif				/* SAHARA_POLL_MODE */
+
+/******************************************************************************
+* The following is the implementation of the Dynamic Power Management
+* functionality.
+******************************************************************************/
+#ifdef SAHARA_POWER_MANAGEMENT
+
+static bool sah_dpm_init_flag;
+
+/* dynamic power management information for the sahara driver */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+static struct device_driver sah_dpm_driver = {
+	.name = "sahara_",
+	.bus = &platform_bus_type,
+#else
+static struct platform_driver sah_dpm_driver = {
+	.driver.name = "sahara_",
+	.driver.bus = &platform_bus_type,
+#endif
+	.suspend = sah_dpm_suspend,
+	.resume = sah_dpm_resume
+};
+
+/* dynamic power management information for the sahara HW device */
+static struct platform_device sah_dpm_device = {
+	.name = "sahara_",
+	.id = 1,
+};
+
+/*!
+*******************************************************************************
+* Initilaizes the dynamic power managment functionality
+*
+* @brief    Initialization of the Dynamic Power Management functionality
+*
+* @return   0 = success; failed otherwise
+*/
+int sah_dpm_init()
+{
+	int status;
+
+	/* dpm is not asserted */
+	sah_dpm_flag = FALSE;
+
+	/* register the driver to the kernel */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	status = os_register_to_driver(&sah_dpm_driver);
+#else
+	status = os_register_to_driver(&sah_dpm_driver.driver);
+#endif
+
+	if (status == 0) {
+		/* register a single sahara chip */
+		/*status = platform_device_register(&sah_dpm_device); */
+		status = os_register_a_device(&sah_dpm_device);
+
+		/* if something went awry, unregister the driver */
+		if (status != 0) {
+			/*driver_unregister(&sah_dpm_driver); */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+			os_unregister_from_driver(&sah_dpm_driver);
+#else
+			os_unregister_from_driver(&sah_dpm_driver.driver);
+#endif
+			sah_dpm_init_flag = FALSE;
+		} else {
+			/* if everything went okay, flag that life is good */
+			sah_dpm_init_flag = TRUE;
+		}
+	}
+
+	/* let the kernel know how it went */
+	return status;
+
+}
+
+/*!
+*******************************************************************************
+* Unregister the dynamic power managment functionality
+*
+* @brief    Unregister the Dynamic Power Management functionality
+*
+*/
+void sah_dpm_close()
+{
+	/* if dynamic power management was initilaized, kill it */
+	if (sah_dpm_init_flag == TRUE) {
+		/*driver_unregister(&sah_dpm_driver); */
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+		os_unregister_from_driver(&sah_dpm_driver);
+#else
+		os_unregister_from_driver(&sah_dpm_driver.driver);
+#endif
+		/*platform_device_register(&sah_dpm_device); */
+		os_unregister_a_device(&sah_dpm_device);
+	}
+}
+
+/*!
+*******************************************************************************
+* Callback routine defined by the Linux Device Model / Dynamic Power management
+* extension. It sets a global flag to disallow the driver to enter queued items
+* into Sahara's DAR.
+*
+* It allows the current active descriptor chains to complete before it returns
+*
+* @brief   Suspends the driver
+*
+* @param   dev   contains device information
+* @param   state contains state information
+* @param   level  level of shutdown
+*
+* @return   0 = success; failed otherwise
+*/
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level)
+#else
+static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state)
+#endif
+{
+	sah_Head_Desc *entry = NULL;
+	os_lock_context_t lock_flags;
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	switch (level) {
+	case SUSPEND_DISABLE:
+		/* Assert dynamic power management. This stops the driver from
+		 * entering queued requests to Sahara */
+		sah_dpm_flag = TRUE;
+		break;
+
+	case SUSPEND_SAVE_STATE:
+		break;
+
+	case SUSPEND_POWER_DOWN:
+		/* hopefully between the DISABLE call and this one, the outstanding
+		 * work Sahara was doing complete. this checks (and waits) for
+		 * those entries that were already active on Sahara to complete */
+		/* lock queue while searching */
+		os_lock_save_context(desc_queue_lock, lock_flags);
+		do {
+			entry = sah_Find_With_State(SAH_STATE_ON_SAHARA);
+		} while (entry != NULL);
+		os_unlock_restore_context(desc_queue_lock, lock_flags);
+
+		/* now we kill the clock so the control circuitry isn't sucking
+		 * any power */
+		mxc_clks_disable(SAHARA2_CLK);
+		break;
+	}
+#else
+	/* Assert dynamic power management. This stops the driver from
+	 * entering queued requests to Sahara */
+	sah_dpm_flag = TRUE;
+
+	/* Now wait for any outstanding work Sahara was doing to complete.
+	 * this checks (and waits) for
+	 * those entries that were already active on Sahara to complete */
+	do {
+		/* lock queue while searching */
+		os_lock_save_context(desc_queue_lock, lock_flags);
+		entry = sah_Find_With_State(SAH_STATE_ON_SAHARA);
+		os_unlock_restore_context(desc_queue_lock, lock_flags);
+	} while (entry != NULL);
+
+	/* now we kill the clock so the control circuitry isn't sucking
+	 * any power */
+	{
+		struct clk *clk = clk_get(NULL, "sahara_clk");
+		if (clk != ERR_PTR(ENOENT)) {
+			clk_disable(clk);
+		}
+	}
+#endif
+
+	return 0;
+}
+
+/*!
+*******************************************************************************
+* Callback routine defined by the Linux Device Model / Dynamic Power management
+* extension. It cleears a global flag to allow the driver to enter queued items
+* into Sahara's DAR.
+*
+* It primes the mechanism to start depleting the queue
+*
+* @brief   Resumes the driver
+*
+* @param   dev    contains device information
+* @param   level  level of resumption
+*
+* @return   0 = success; failed otherwise
+*/
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+static int sah_dpm_resume(struct device *dev, uint32_t level)
+#else
+static int sah_dpm_resume(struct platform_device *dev)
+#endif
+{
+	sah_Head_Desc *entry = NULL;
+	os_lock_context_t lock_flags;
+
+#if  LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+	switch (level) {
+	case RESUME_POWER_ON:
+		/* enable Sahara's clock */
+		mxc_clks_enable(SAHARA2_CLK);
+		break;
+
+	case RESUME_RESTORE_STATE:
+		break;
+
+	case RESUME_ENABLE:
+		/* Disable dynamic power managment. This allows the driver to put
+		 * entries into Sahara's DAR */
+		sah_dpm_flag = FALSE;
+
+		/* find a pending entry to prime the pump */
+		os_lock_save_context(desc_queue_lock, lock_flags);
+		entry = sah_Find_With_State(SAH_STATE_PENDING);
+		if (entry != NULL) {
+			sah_Queue_Manager_Prime(entry);
+		}
+		os_unlock_restore_context(desc_queue_lock, lock_flags);
+		break;
+	}
+#else
+	{
+		/* enable Sahara's clock */
+		struct clk *clk = clk_get(NULL, "sahara_clk");
+
+		if (clk != ERR_PTR(ENOENT)) {
+			clk_enable(clk);
+		}
+	}
+	sah_dpm_flag = FALSE;
+
+	/* find a pending entry to prime the pump */
+	os_lock_save_context(desc_queue_lock, lock_flags);
+	entry = sah_Find_With_State(SAH_STATE_PENDING);
+	if (entry != NULL) {
+		sah_Queue_Manager_Prime(entry);
+	}
+	os_unlock_restore_context(desc_queue_lock, lock_flags);
+#endif
+	return 0;
+}
+
+#endif				/* SAHARA_POWER_MANAGEMENT */
diff --git a/drivers/mxc/security/sahara2/sf_util.c b/drivers/mxc/security/sahara2/sf_util.c
new file mode 100644
index 000000000000..b1cc2597f183
--- /dev/null
+++ b/drivers/mxc/security/sahara2/sf_util.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/**
+* @file sf_util.c
+*
+* @brief Security Functions component API - Utility functions
+*
+* These are the 'Sahara api' functions which are used by the higher-level
+* FSL SHW API to build and then execute descriptor chains.
+*/
+
+
+#include "sf_util.h"
+#include <adaptor.h>
+
+#ifdef DIAG_SECURITY_FUNC
+#include <diagnostic.h>
+#endif /*DIAG_SECURITY_FUNC*/
+
+
+#ifdef __KERNEL__
+EXPORT_SYMBOL(sah_Append_Desc);
+EXPORT_SYMBOL(sah_Append_Link);
+EXPORT_SYMBOL(sah_Create_Link);
+EXPORT_SYMBOL(sah_Create_Key_Link);
+EXPORT_SYMBOL(sah_Destroy_Link);
+EXPORT_SYMBOL(sah_Descriptor_Chain_Execute);
+EXPORT_SYMBOL(sah_insert_mdha_algorithm);
+EXPORT_SYMBOL(sah_insert_skha_algorithm);
+EXPORT_SYMBOL(sah_insert_skha_mode);
+EXPORT_SYMBOL(sah_insert_skha_modulus);
+EXPORT_SYMBOL(sah_Descriptor_Chain_Destroy);
+EXPORT_SYMBOL(sah_add_two_in_desc);
+EXPORT_SYMBOL(sah_add_in_key_desc);
+EXPORT_SYMBOL(sah_add_two_out_desc);
+EXPORT_SYMBOL(sah_add_in_out_desc);
+EXPORT_SYMBOL(sah_add_key_out_desc);
+#endif
+
+#ifdef DEBUG_REWORK
+#ifndef __KERNEL__
+#include <stdio.h>
+#define os_printk printf
+#endif
+#endif
+
+/**
+ * Convert fsl_shw_hash_alg_t to mdha mode bits.
+ *
+ * Index must be maintained in order of fsl_shw_hash_alg_t enumeration!!!
+ */
+const uint32_t sah_insert_mdha_algorithm[] =
+{
+    [FSL_HASH_ALG_MD5] = sah_insert_mdha_algorithm_md5,
+    [FSL_HASH_ALG_SHA1] = sah_insert_mdha_algorithm_sha1,
+    [FSL_HASH_ALG_SHA224] = sah_insert_mdha_algorithm_sha224,
+    [FSL_HASH_ALG_SHA256] = sah_insert_mdha_algorithm_sha256,
+};
+
+/**
+ * Header bits for Algorithm field of SKHA header
+ *
+ * Index value must be kept in sync with fsl_shw_key_alg_t
+ */
+const uint32_t sah_insert_skha_algorithm[] =
+{
+    [FSL_KEY_ALG_HMAC] = 0x00000040,
+    [FSL_KEY_ALG_AES] = sah_insert_skha_algorithm_aes,
+    [FSL_KEY_ALG_DES] = sah_insert_skha_algorithm_des,
+    [FSL_KEY_ALG_TDES] = sah_insert_skha_algorithm_tdes,
+    [FSL_KEY_ALG_ARC4] = sah_insert_skha_algorithm_arc4,
+};
+
+
+/**
+ * Header bits for MODE field of SKHA header
+ *
+ * Index value must be kept in sync with fsl_shw_sym_mod_t
+ */
+const uint32_t sah_insert_skha_mode[] =
+{
+    [FSL_SYM_MODE_STREAM] = sah_insert_skha_mode_ecb,
+    [FSL_SYM_MODE_ECB] = sah_insert_skha_mode_ecb,
+    [FSL_SYM_MODE_CBC] = sah_insert_skha_mode_cbc,
+    [FSL_SYM_MODE_CTR] = sah_insert_skha_mode_ctr,
+};
+
+
+/**
+ * Header bits to set CTR modulus size.  These have parity
+ * included to allow XOR insertion of values.
+ *
+ * @note Must be kept in sync with fsl_shw_ctr_mod_t
+ */
+const uint32_t sah_insert_skha_modulus[] =
+{
+    [FSL_CTR_MOD_8] = 0x00000000, /**< 2**8 */
+    [FSL_CTR_MOD_16] = 0x80000200, /**< 2**16 */
+    [FSL_CTR_MOD_24] = 0x80000400, /**< 2**24 */
+    [FSL_CTR_MOD_32] = 0x00000600, /**< 2**32 */
+    [FSL_CTR_MOD_40] = 0x80000800, /**< 2**40 */
+    [FSL_CTR_MOD_48] = 0x00000a00, /**< 2**48 */
+    [FSL_CTR_MOD_56] = 0x00000c00, /**< 2**56 */
+    [FSL_CTR_MOD_64] = 0x80000e00, /**< 2**64 */
+    [FSL_CTR_MOD_72] = 0x80001000, /**< 2**72 */
+    [FSL_CTR_MOD_80] = 0x00001200, /**< 2**80 */
+    [FSL_CTR_MOD_88] = 0x00001400, /**< 2**88 */
+    [FSL_CTR_MOD_96] = 0x80001600, /**< 2**96 */
+    [FSL_CTR_MOD_104] = 0x00001800, /**< 2**104 */
+    [FSL_CTR_MOD_112] = 0x80001a00, /**< 2**112 */
+    [FSL_CTR_MOD_120] = 0x80001c00, /**< 2**120 */
+    [FSL_CTR_MOD_128] = 0x00001e00 /**< 2**128 */
+};
+
+
+/******************************************************************************
+* Internal function declarations
+******************************************************************************/
+static fsl_shw_return_t sah_Create_Desc(
+    const sah_Mem_Util *mu,
+    sah_Desc ** desc,
+    int head,
+    uint32_t header,
+    sah_Link * link1,
+    sah_Link * link2);
+
+
+/**
+ * Create a descriptor chain using the the header and links passed in as
+ * parameters. The newly created descriptor will be added to the end of
+ * the descriptor chain passed.
+ *
+ * If @a desc_head points to a NULL value, then a sah_Head_Desc will be created
+ * as the first descriptor.  Otherwise a sah_Desc will be created and appended.
+ *
+ * @pre
+ *
+ * - None
+ *
+ * @post
+ *
+ * - A descriptor has been created from the header, link1 and link2.
+ *
+ * - The newly created descriptor has been appended to the end of
+ *   desc_head, or its location stored into the location pointed to by
+ *   @a desc_head.
+ *
+ * - On allocation failure, @a link1 and @a link2 will be destroyed., and
+ *   @a desc_head will be untouched.
+ *
+ * @brief   Create and append descriptor chain, inserting header and links
+ *          pointing to link1 and link2
+ *
+ * @param  mu Memory functions
+ * @param  header Value of descriptor header to be added
+ * @param  desc_head Pointer to head of descriptor chain to append new desc
+ * @param  link1 Pointer to sah_Link 1 (or NULL)
+ * @param  link2 Pointer to sah_Link 2 (or NULL)
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_Append_Desc(
+    const sah_Mem_Util *mu,
+    sah_Head_Desc **desc_head,
+    const uint32_t header,
+    sah_Link *link1,
+    sah_Link *link2)
+{
+    fsl_shw_return_t status;
+    sah_Desc         *desc;
+    sah_Desc         *desc_ptr;
+
+
+    status = sah_Create_Desc(mu, (sah_Desc**)&desc, (*desc_head == NULL),
+                             header, link1, link2);
+    /* append newly created descriptor to end of current chain */
+    if (status == FSL_RETURN_OK_S) {
+        if (*desc_head == NULL) {
+            (*desc_head) = (sah_Head_Desc*)desc;
+            (*desc_head)->out1_ptr = NULL;
+            (*desc_head)->out2_ptr = NULL;
+
+        } else {
+            desc_ptr = (sah_Desc*)*desc_head;
+            while (desc_ptr->next != NULL) {
+                desc_ptr = desc_ptr->next;
+            }
+            desc_ptr->next = desc;
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Releases the memory allocated by the Security Function library for
+ * descriptors, links and any internally allocated memory referenced in the
+ * given chain. Note that memory allocated by user applications is not
+ * released.
+ *
+ * @post The @a desc_head pointer will be set to NULL to prevent further use.
+ *
+ * @brief   Destroy a descriptor chain and free memory of associated links
+ *
+ * @param  mu Memory functions
+ * @param  desc_head Pointer to head of descriptor chain to be freed
+ *
+ * @return none
+ */
+void sah_Descriptor_Chain_Destroy (
+    const sah_Mem_Util *mu,
+    sah_Head_Desc **desc_head)
+{
+    sah_Desc *desc_ptr = &(*desc_head)->desc;
+    sah_Head_Desc *desc_head_ptr = (sah_Head_Desc *)desc_ptr;
+
+    while (desc_ptr != NULL) {
+        register sah_Desc *next_desc_ptr;
+
+        if (desc_ptr->ptr1 != NULL) {
+            sah_Destroy_Link(mu, desc_ptr->ptr1);
+        }
+        if (desc_ptr->ptr2 != NULL) {
+            sah_Destroy_Link(mu, desc_ptr->ptr2);
+        }
+
+        next_desc_ptr = desc_ptr->next;
+
+        /* Be sure to free head descriptor as such */
+        if (desc_ptr == (sah_Desc*)desc_head_ptr) {
+            mu->mu_free_head_desc(mu->mu_ref, desc_head_ptr);
+        } else {
+            mu->mu_free_desc(mu->mu_ref, desc_ptr);
+        }
+
+        desc_ptr = next_desc_ptr;
+    }
+
+    *desc_head = NULL;
+}
+
+
+#ifndef NO_INPUT_WORKAROUND
+/**
+ * Reworks the link chain
+ *
+ * @brief   Reworks the link chain
+ *
+ * @param  mu    Memory functions
+ * @param  link  Pointer to head of link chain to be reworked
+ *
+ * @return none
+ */
+static fsl_shw_return_t sah_rework_link_chain(
+        const sah_Mem_Util *mu,
+        sah_Link* link)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    int found_potential_problem = 0;
+    uint32_t total_data = 0;
+#ifdef DEBUG_REWORK
+    sah_Link* first_link = link;
+#endif
+
+    if ((link->flags & SAH_OUTPUT_LINK)) {
+        return status;
+    }
+
+    while (link != NULL) {
+        total_data += link->len;
+
+    /* Only non-key Input Links are affected by the DMA flush-to-FIFO
+     * problem */
+
+        /* If have seen problem and at end of chain... */
+        if (found_potential_problem && (link->next == NULL) &&
+                                         (total_data > 16)) {
+            /* insert new 1-byte link */
+            sah_Link* new_tail_link = mu->mu_alloc_link(mu->mu_ref);
+            if (new_tail_link == NULL) {
+                status = FSL_RETURN_NO_RESOURCE_S;
+            } else {
+#ifdef DEBUG_REWORK
+                sah_Link* dump_link = first_link;
+                while (dump_link != NULL) {
+                    uint32_t i;
+                    unsigned bytes_to_dump = (dump_link->len > 32) ?
+                                              32 : dump_link->len;
+                    os_printk("(rework)Link %p: %p/%u/%p\n", dump_link,
+                              dump_link->data, dump_link->len,
+                              dump_link->next);
+                    if (!(dump_link->flags & SAH_STORED_KEY_INFO)) {
+                        os_printk("(rework)Data %p: ", dump_link->data);
+                        for (i = 0; i < bytes_to_dump; i++) {
+                            os_printk("%02X ", dump_link->data[i]);
+                        }
+                        os_printk("\n");
+                    }
+                    else {
+                        os_printk("rework)Data %p: Red key data\n", dump_link);
+                    }
+                    dump_link = dump_link->next;
+                }
+#endif
+                link->len--;
+                link->next = new_tail_link;
+                new_tail_link->len = 1;
+                new_tail_link->data = link->data+link->len;
+                new_tail_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA);
+                new_tail_link->next = NULL;
+                link = new_tail_link;
+#ifdef DEBUG_REWORK
+                os_printk("(rework)New link chain:\n");
+                dump_link = first_link;
+                while (dump_link != NULL) {
+                    uint32_t i;
+                    unsigned bytes_to_dump = (dump_link->len > 32) ?
+                                              32 : dump_link->len;
+
+                    os_printk("Link %p: %p/%u/%p\n", dump_link,
+                              dump_link->data, dump_link->len,
+                              dump_link->next);
+                    if (!(dump_link->flags & SAH_STORED_KEY_INFO)) {
+                        os_printk("Data %p: ", dump_link->data);
+                        for (i = 0; i < bytes_to_dump; i++) {
+                            os_printk("%02X ", dump_link->data[i]);
+                        }
+                        os_printk("\n");
+                    }
+                    else {
+                        os_printk("Data %p: Red key data\n", dump_link);
+                    }
+                    dump_link = dump_link->next;
+                }
+#endif
+            }
+        } else if ((link->len % 4) || ((uint32_t)link->data % 4)) {
+            found_potential_problem = 1;
+        }
+
+        link = link->next;
+    }
+
+    return status;
+}
+
+
+/**
+ * Rework links to avoid H/W bug
+ *
+ * @param head   Beginning of descriptor chain
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t sah_rework_links(
+        const sah_Mem_Util *mu,
+        sah_Head_Desc *head)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Desc* desc = &head->desc;
+
+    while ((status == FSL_RETURN_OK_S) && (desc != NULL)) {
+        if (desc->header & SAH_HDR_LLO) {
+            status = FSL_RETURN_ERROR_S;
+            break;
+        }
+        if (desc->ptr1 != NULL) {
+            status = sah_rework_link_chain(mu, desc->ptr1);
+        }
+        if ((status == FSL_RETURN_OK_S) && (desc->ptr2 != NULL)) {
+            status = sah_rework_link_chain(mu, desc->ptr2);
+        }
+        desc = desc->next;
+    }
+
+    return status;
+}
+#endif /* NO_INPUT_WORKAROUND */
+
+
+/**
+ * Send a descriptor chain to the SAHARA driver for processing.
+ *
+ * Note that SAHARA will read the input data from and write the output data
+ * directly to the locations indicated during construction of the chain.
+ *
+ * @pre
+ *
+ * - None
+ *
+ * @post
+ *
+ * - @a head will have been executed on SAHARA
+ * - @a head Will be freed unless a SAVE flag is set
+ *
+ * @brief   Execute a descriptor chain
+ *
+ * @param  head      Pointer to head of descriptor chain to be executed
+ * @param  user_ctx  The user context on which to execute the descriptor chain.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_Descriptor_Chain_Execute(
+    sah_Head_Desc *head,
+    fsl_shw_uco_t *user_ctx)
+{
+    fsl_shw_return_t status;
+
+	/* Check for null pointer or non-multiple-of-four value */
+    if ((head == NULL) || ((uint32_t)head & 0x3)) {
+        status = FSL_RETURN_ERROR_S;
+        goto out;
+    }
+
+#ifndef NO_INPUT_WORKAROUND
+    status = sah_rework_links(user_ctx->mem_util, head);
+    if (status != FSL_RETURN_OK_S) {
+        goto out;
+    }
+#endif
+
+    /* complete the information in the descriptor chain head node */
+    head->user_ref = user_ctx->user_ref;
+    head->uco_flags = user_ctx->flags;
+    head->next = NULL; /* driver will use this to link chain heads */
+
+    status = adaptor_Exec_Descriptor_Chain(head, user_ctx);
+
+#ifdef DIAG_SECURITY_FUNC
+	 if (status == FSL_RETURN_OK_S)
+		 LOG_DIAG("after exec desc chain: status is ok\n");
+	 else
+		 LOG_DIAG("after exec desc chain: status is not ok\n");
+#endif
+
+ out:
+    return status;
+}
+
+
+/**
+ * Create Link
+ *
+ * @brief   Allocate Memory for Link structure and populate using input
+ *          parameters
+ *
+ * @post    On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is
+ *          p set in @a flags.
+
+ * @param  mu Memory functions
+ * @param  link Pointer to link to be created
+ * @param  p Pointer to data to use in link
+ * @param  length Length of buffer 'p' in bytes
+ * @param  flags Indicates whether memory has been allocated by the calling
+ *         function or the security function
+ *
+ * @return FSL_RETURN_OK_S or FSL_RETURN_NO_RESOURCE_S
+ */
+fsl_shw_return_t sah_Create_Link(
+    const sah_Mem_Util *mu,
+    sah_Link **link,
+    uint8_t *p,
+    const size_t length,
+    const sah_Link_Flags flags)
+{
+
+#ifdef DIAG_SECURITY_FUNC
+
+    char diag[50];
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+    fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S;
+
+
+    *link = mu->mu_alloc_link(mu->mu_ref);
+
+    /* populate link if memory allocation successful */
+    if (*link != NULL) {
+        (*link)->len = length;
+        (*link)->data = p;
+        (*link)->next = NULL;
+        (*link)->flags = flags;
+        status = FSL_RETURN_OK_S;
+
+#ifdef DIAG_SECURITY_FUNC
+
+        LOG_DIAG("Created Link");
+        LOG_DIAG("------------");
+        sprintf(diag," address       = 0x%x", (int) *link);
+        LOG_DIAG(diag);
+        sprintf(diag," link->len     = %d",(*link)->len);
+        LOG_DIAG(diag);
+        sprintf(diag," link->data    = 0x%x",(int) (*link)->data);
+        LOG_DIAG(diag);
+        sprintf(diag," link->flags   = 0x%x",(*link)->flags);
+        LOG_DIAG(diag);
+        LOG_DIAG(" link->next    = NULL");
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+
+    } else {
+#ifdef DIAG_SECURITY_FUNC
+        LOG_DIAG("Allocation of memory for sah_Link failed!\n");
+#endif /*DIAG_SECURITY_FUNC*/
+
+        /* Free memory previously allocated by the security function layer for
+        link data. Note that the memory being pointed to will be zeroed before
+        being freed, for security reasons. */
+        if (flags & SAH_OWNS_LINK_DATA) {
+            mu->mu_memset(mu->mu_ref, p, 0x00, length);
+            mu->mu_free(mu->mu_ref, p);
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Create Key Link
+ *
+ * @brief   Allocate Memory for Link structure and populate using key info
+ *          object
+ *
+ * @param  mu Memory functions
+ * @param  link Pointer to store address of link to be created
+ * @param  key_info Pointer to Key Info object to be referenced
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_Create_Key_Link(
+    const sah_Mem_Util *mu,
+    sah_Link **link,
+    fsl_shw_sko_t *key_info)
+{
+#ifdef DIAG_SECURITY_FUNC_UGLY
+    char diag[50];
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+    fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S;
+    sah_Link_Flags flags = 0;
+
+
+    *link = mu->mu_alloc_link(mu->mu_ref);
+
+    /* populate link if memory allocation successful */
+    if (*link != NULL) {
+        (*link)->len = key_info->key_length;
+
+        if (key_info->flags & FSL_SKO_KEY_PRESENT) {
+            (*link)->data = key_info->key;
+            status = FSL_RETURN_OK_S;
+        } else {
+            if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+
+				if (key_info->keystore == NULL) {
+					/* System Keystore */
+			(*link)->slot = key_info->handle;
+			(*link)->ownerid = key_info->userid;
+			(*link)->data = 0;
+			flags |= SAH_STORED_KEY_INFO;
+			status = FSL_RETURN_OK_S;
+				} else {
+#ifdef FSL_HAVE_SCC2
+					/* User Keystore */
+					fsl_shw_kso_t *keystore = key_info->keystore;
+					/* Note: the key data is stored here, but the address has to
+					 * be converted to a partition and offset in the kernel.
+					 * This will be calculated in kernel space, based on the
+					 * list of partitions held by the users context.
+					 */
+					(*link)->data =
+						keystore->slot_get_address(keystore->user_data,
+												 key_info->handle);
+
+					flags |= SAH_IN_USER_KEYSTORE;
+					status = FSL_RETURN_OK_S;
+#else
+					/* User keystores only supported in SCC2 */
+					status = FSL_RETURN_BAD_FLAG_S;
+#endif				/* FSL_HAVE_SCC2 */
+
+				}
+            } else {
+                /* the flag is bad. Should never get here */
+                status = FSL_RETURN_BAD_FLAG_S;
+            }
+        }
+
+        (*link)->next = NULL;
+        (*link)->flags = flags;
+
+#ifdef DIAG_SECURITY_FUNC_UGLY
+        if (status == FSL_RETURN_OK_S) {
+            LOG_DIAG("Created Link");
+            LOG_DIAG("------------");
+            sprintf(diag," address       = 0x%x", (int) *link);
+            LOG_DIAG(diag);
+            sprintf(diag," link->len     = %d", (*link)->len);
+            LOG_DIAG(diag);
+            if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) {
+                sprintf(diag," link->slot    = 0x%x", (*link)->slot);
+                LOG_DIAG(diag);
+            } else {
+                sprintf(diag," link->data    = 0x%x", (int)(*link)->data);
+                LOG_DIAG(diag);
+            }
+            sprintf(diag," link->flags   = 0x%x", (*link)->flags);
+            LOG_DIAG(diag);
+            LOG_DIAG(" link->next    = NULL");
+        }
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+
+        if (status == FSL_RETURN_BAD_FLAG_S) {
+            mu->mu_free_link(mu->mu_ref, *link);
+            *link = NULL;
+#ifdef DIAG_SECURITY_FUNC
+            LOG_DIAG("Creation of sah_Key_Link failed due to bad key flag!\n");
+#endif /*DIAG_SECURITY_FUNC*/
+        }
+
+    } else {
+#ifdef DIAG_SECURITY_FUNC
+        LOG_DIAG("Allocation of memory for sah_Key_Link failed!\n");
+#endif /*DIAG_SECURITY_FUNC*/
+    }
+
+    return status;
+}
+
+
+/**
+ * Append Link
+ *
+ * @brief   Allocate Memory for Link structure and append it to the end of
+ *          the link chain.
+ *
+ * @post    On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is
+ *          p set in @a flags.
+ *
+ * @param  mu Memory functions
+ * @param  link_head Pointer to (head of) existing link chain
+ * @param  p Pointer to data to use in link
+ * @param  length Length of buffer 'p' in bytes
+ * @param  flags Indicates whether memory has been allocated by the calling
+ *         function or the security function
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_Append_Link(
+    const sah_Mem_Util *mu,
+    sah_Link *link_head,
+    uint8_t *p,
+    const size_t length,
+    const sah_Link_Flags flags)
+{
+    sah_Link* new_link;
+    fsl_shw_return_t status;
+
+
+    status = sah_Create_Link(mu, &new_link, p, length, flags);
+
+    if (status == FSL_RETURN_OK_S) {
+        /* chase for the tail */
+        while (link_head->next != NULL) {
+            link_head = link_head->next;
+        }
+
+        /* and add new tail */
+        link_head->next = new_link;
+    }
+
+    return status;
+}
+
+
+/**
+ * Create and populate a single descriptor
+ *
+ * The pointer and length fields will be be set based on the chains passed in
+ * as @a link1 and @a link2.
+ *
+ * @param  mu         Memory utility suite
+ * @param  desc       Location to store pointer of new descriptor
+ * @param  head_desc  Non-zero if this will be first in chain; zero otherwise
+ * @param  header     The Sahara header value to store in the descriptor
+ * @param  link1      A value (or NULL) for the first ptr
+ * @param  link2      A value (or NULL) for the second ptr
+ *
+ * @post  If allocation succeeded, the @a link1 and @link2 will be linked into
+ *        the descriptor.  If allocation failed, those link structues will be
+ *        freed, and the @a desc will be unchanged.
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+static fsl_shw_return_t sah_Create_Desc(
+    const sah_Mem_Util *mu,
+    sah_Desc ** desc,
+    int head_desc,
+    uint32_t header,
+    sah_Link * link1,
+    sah_Link * link2)
+{
+    fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S;
+#ifdef DIAG_SECURITY_FUNC_UGLY
+    char diag[50];
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+
+
+    if (head_desc != 0) {
+        *desc = (sah_Desc *)mu->mu_alloc_head_desc(mu->mu_ref);
+    } else {
+        *desc = mu->mu_alloc_desc(mu->mu_ref);
+    }
+
+    /* populate descriptor if memory allocation successful */
+    if ((*desc) != NULL) {
+        sah_Link* temp_link;
+
+        status = FSL_RETURN_OK_S;
+        (*desc)->header = header;
+
+        temp_link = (*desc)->ptr1 = link1;
+        (*desc)->len1 = 0;
+        while (temp_link != NULL) {
+            (*desc)->len1 += temp_link->len;
+            temp_link = temp_link->next;
+        }
+
+        temp_link = (*desc)->ptr2 = link2;
+        (*desc)->len2 = 0;
+        while (temp_link != NULL) {
+            (*desc)->len2 += temp_link->len;
+            temp_link = temp_link->next;
+        }
+
+        (*desc)->next = NULL;
+
+#ifdef DIAG_SECURITY_FUNC_UGLY
+        LOG_DIAG("Created Desc");
+        LOG_DIAG("------------");
+        sprintf(diag," address       = 0x%x",(int) *desc);
+        LOG_DIAG(diag);
+        sprintf(diag," desc->header  = 0x%x",(*desc)->header);
+        LOG_DIAG(diag);
+        sprintf(diag," desc->len1    = %d",(*desc)->len1);
+        LOG_DIAG(diag);
+        sprintf(diag," desc->ptr1    = 0x%x",(int) ((*desc)->ptr1));
+        LOG_DIAG(diag);
+        sprintf(diag," desc->len2    = %d",(*desc)->len2);
+        LOG_DIAG(diag);
+        sprintf(diag," desc->ptr2    = 0x%x",(int) ((*desc)->ptr2));
+        LOG_DIAG(diag);
+        sprintf(diag," desc->next    = 0x%x",(int) ((*desc)->next));
+        LOG_DIAG(diag);
+#endif /*DIAG_SECURITY_FUNC_UGLY*/
+    } else {
+#ifdef DIAG_SECURITY_FUNC
+        LOG_DIAG("Allocation of memory for sah_Desc failed!\n");
+#endif /*DIAG_SECURITY_FUNC*/
+
+        /* Destroy the links, otherwise the memory allocated by the Security
+        Function layer for the links (and possibly the data within the links)
+        will be lost */
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Destroy a link (chain) and free memory
+ *
+ * @param mu   memory utility suite
+ * @param link The Link to destroy
+ *
+ * @return none
+ */
+void sah_Destroy_Link(
+    const sah_Mem_Util *mu,
+    sah_Link * link)
+{
+
+    while (link != NULL) {
+        sah_Link * next_link = link->next;
+
+        if (link->flags & SAH_OWNS_LINK_DATA) {
+            /* zero data for security purposes */
+            mu->mu_memset(mu->mu_ref, link->data, 0x00, link->len);
+            mu->mu_free(mu->mu_ref, link->data);
+        }
+
+        link->data = NULL;
+        link->next = NULL;
+        mu->mu_free_link(mu->mu_ref, link);
+
+        link = next_link;
+    }
+}
+
+
+/**
+ * Add descriptor where both links are inputs.
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in1        The first input buffer (or NULL)
+ * @param         in1_length Size of @a in1
+ * @param[out]    in2        The second input buffer (or NULL)
+ * @param         in2_length Size of @a in2
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_two_in_desc(uint32_t header,
+                                 const uint8_t* in1,
+                                 uint32_t in1_length,
+                                 const uint8_t* in2,
+                                 uint32_t in2_length,
+                                 const sah_Mem_Util* mu,
+                                 sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link* link1 = NULL;
+    sah_Link* link2 = NULL;
+
+	if (in1 != NULL) {
+		status = sah_Create_Link(mu, &link1,
+			(sah_Oct_Str) in1, in1_length, SAH_USES_LINK_DATA);
+    }
+
+    if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) {
+        status = sah_Create_Link(mu, &link2,
+                                 (sah_Oct_Str) in2, in2_length,
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    } else {
+        status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+    }
+
+    return status;
+}
+
+/*!
+ * Add descriptor where neither link needs sync
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in1        The first input buffer (or NULL)
+ * @param         in1_length Size of @a in1
+ * @param[out]    in2        The second input buffer (or NULL)
+ * @param         in2_length Size of @a in2
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_two_d_desc(uint32_t header,
+				    const uint8_t * in1,
+				    uint32_t in1_length,
+				    const uint8_t * in2,
+				    uint32_t in2_length,
+				    const sah_Mem_Util * mu,
+				    sah_Head_Desc ** desc_chain)
+{
+	fsl_shw_return_t status = FSL_RETURN_OK_S;
+	sah_Link *link1 = NULL;
+	sah_Link *link2 = NULL;
+
+	printk("Entering sah_add_two_d_desc \n");
+
+	if (in1 != NULL) {
+		status = sah_Create_Link(mu, &link1,
+					 (sah_Oct_Str) in1, in1_length,
+					 SAH_USES_LINK_DATA);
+	}
+
+	if ((in2 != NULL) && (status == FSL_RETURN_OK_S)) {
+		status = sah_Create_Link(mu, &link2,
+					 (sah_Oct_Str) in2, in2_length,
+					 SAH_USES_LINK_DATA);
+	}
+
+	if (status != FSL_RETURN_OK_S) {
+		if (link1 != NULL) {
+			sah_Destroy_Link(mu, link1);
+		}
+		if (link2 != NULL) {
+			sah_Destroy_Link(mu, link2);
+		}
+	} else {
+		status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+	}
+
+	return status;
+}				/* sah_add_two_d_desc() */
+
+/**
+ * Add descriptor where both links are inputs, the second one being a key.
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in1        The first input buffer (or NULL)
+ * @param         in1_length Size of @a in1
+ * @param[out]    in2        The second input buffer (or NULL)
+ * @param         in2_length Size of @a in2
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_in_key_desc(uint32_t header,
+                                 const uint8_t* in1,
+                                 uint32_t in1_length,
+                                 fsl_shw_sko_t* key_info,
+                                 const sah_Mem_Util* mu,
+                                 sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+	if (in1 != NULL) {
+        status = sah_Create_Link(mu, &link1,
+                                 (sah_Oct_Str) in1, in1_length,
+                                 SAH_USES_LINK_DATA);
+    }
+
+	if (status != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+    status = sah_Create_Key_Link(mu, &link2, key_info);
+
+
+	if (status != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+	status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+
+out:
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Create two links using keys allocated in the scc
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in1        The first input buffer (or NULL)
+ * @param         in1_length Size of @a in1
+ * @param[out]    in2        The second input buffer (or NULL)
+ * @param         in2_length Size of @a in2
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_key_key_desc(uint32_t header,
+                                  fsl_shw_sko_t *key_info1,
+                                  fsl_shw_sko_t *key_info2,
+                                  const sah_Mem_Util *mu,
+                                  sah_Head_Desc **desc_chain)
+{
+    fsl_shw_return_t status;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+
+    status = sah_Create_Key_Link(mu, &link1, key_info1);
+
+    if (status == FSL_RETURN_OK_S) {
+        status = sah_Create_Key_Link(mu, &link2, key_info2);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    } else {
+        status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+    }
+
+    return status;
+}
+
+
+/**
+ * Add descriptor where first link is input, the second is a changing key
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in1        The first input buffer (or NULL)
+ * @param         in1_length Size of @a in1
+ * @param[out]    in2        The key for output
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header,
+                                 const uint8_t* in1,
+                                 uint32_t in1_length,
+                                 fsl_shw_sko_t* key_info,
+                                 const sah_Mem_Util* mu,
+                                 sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+	if (in1 != NULL) {
+        status = sah_Create_Link(mu, &link1,
+                                 (sah_Oct_Str) in1, in1_length,
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+		goto out;
+    }
+
+	status = sah_Create_Key_Link(mu, &link2, key_info);
+
+	if (status != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+link2->flags |= SAH_OUTPUT_LINK;	/* mark key for output */
+status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+
+out:
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    }
+
+    return status;
+}
+
+/**
+ * Add descriptor where both links are outputs.
+ *
+ * @param         header      The Sahara header value for the descriptor.
+ * @param         out1        The first output buffer (or NULL)
+ * @param         out1_length Size of @a out1
+ * @param[out]    out2        The second output buffer (or NULL)
+ * @param         out2_length Size of @a out2
+ * @param         mu          Memory functions
+ * @param[in,out] desc_chain  Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_two_out_desc(uint32_t header,
+                                      uint8_t* out1,
+                                      uint32_t out1_length,
+                                      uint8_t* out2,
+                                      uint32_t out2_length,
+                                      const sah_Mem_Util* mu,
+                                      sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+
+	if (out1 != NULL) {
+		status = sah_Create_Link(mu, &link1,
+			(sah_Oct_Str) out1, out1_length,
+			SAH_OUTPUT_LINK | SAH_USES_LINK_DATA);
+    }
+
+    if ( (out2 != NULL) && (status == FSL_RETURN_OK_S) ) {
+        status = sah_Create_Link(mu, &link2,
+                                 (sah_Oct_Str) out2, out2_length,
+                                 SAH_OUTPUT_LINK |
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    } else {
+        status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+    }
+
+    return status;
+}
+
+
+/**
+ * Add descriptor where first link is output, second is output
+ *
+ * @param         header      The Sahara header value for the descriptor.
+ * @param         out1        The first output buffer (or NULL)
+ * @param         out1_length Size of @a out1
+ * @param[out]    in2         The input buffer (or NULL)
+ * @param         in2_length  Size of @a in2
+ * @param         mu          Memory functions
+ * @param[in,out] desc_chain  Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_out_in_desc(uint32_t header,
+                                     uint8_t* out1,
+                                     uint32_t out1_length,
+                                     const uint8_t* in2,
+                                     uint32_t in2_length,
+                                     const sah_Mem_Util* mu,
+                                     sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+
+    if (out1 != NULL) {
+        status = sah_Create_Link(mu, &link1,
+                                 (sah_Oct_Str) out1, out1_length,
+                                 SAH_OUTPUT_LINK |
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) {
+        status = sah_Create_Link(mu, &link2,
+                                 (sah_Oct_Str) in2, in2_length,
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    } else {
+        status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+    }
+
+    return status;
+}
+
+
+/**
+ * Add descriptor where link1 is input buffer, link2 is output buffer.
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         in         The input buffer
+ * @param         in_length  Size of the input buffer
+ * @param[out]    out        The output buffer
+ * @param         out_length Size of the output buffer
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_in_out_desc(uint32_t header,
+                                 const uint8_t* in, uint32_t in_length,
+                                 uint8_t* out, uint32_t out_length,
+                                 const sah_Mem_Util* mu,
+                                 sah_Head_Desc** desc_chain)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+	if (in != NULL) {
+        status = sah_Create_Link(mu, &link1,
+                                 (sah_Oct_Str) in, in_length,
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if ((status == FSL_RETURN_OK_S) && (out != NULL))  {
+        status = sah_Create_Link(mu, &link2,
+                                 (sah_Oct_Str) out, out_length,
+                                 SAH_OUTPUT_LINK |
+                                 SAH_USES_LINK_DATA);
+    }
+
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    } else {
+        status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+    }
+
+    return status;
+}
+
+
+/**
+ * Add descriptor where link1 is a key, link2 is output buffer.
+ *
+ * @param         header     The Sahara header value for the descriptor.
+ * @param         key_info   Key information
+ * @param[out]    out        The output buffer
+ * @param         out_length Size of the output buffer
+ * @param         mu         Memory functions
+ * @param[in,out] desc_chain Chain to start or append to
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_add_key_out_desc(uint32_t header,
+								  const fsl_shw_sko_t *key_info,
+                                  uint8_t* out, uint32_t out_length,
+                                  const sah_Mem_Util *mu,
+                                  sah_Head_Desc **desc_chain)
+{
+    fsl_shw_return_t status;
+    sah_Link         *link1 = NULL;
+    sah_Link         *link2 = NULL;
+
+	status = sah_Create_Key_Link(mu, &link1, (fsl_shw_sko_t *) key_info);
+	if (status != FSL_RETURN_OK_S) {
+		goto out;
+	}
+
+
+    if (out != NULL)  {
+        status = sah_Create_Link(mu, &link2,
+                                 (sah_Oct_Str) out, out_length,
+                                 SAH_OUTPUT_LINK |
+                                 SAH_USES_LINK_DATA);
+		if (status != FSL_RETURN_OK_S) {
+			goto out;
+	   }
+    }
+status = sah_Append_Desc(mu, desc_chain, header, link1, link2);
+
+out:
+    if (status != FSL_RETURN_OK_S) {
+        if (link1 != NULL) {
+            sah_Destroy_Link(mu, link1);
+        }
+        if (link2 != NULL) {
+            sah_Destroy_Link(mu, link2);
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Sanity checks the user context object fields to ensure that they make some
+ * sense before passing the uco as a parameter
+ *
+ * @brief Verify the user context object
+ *
+ * @param  uco  user context object
+ *
+ * @return    A return code of type #fsl_shw_return_t.
+ */
+fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t *uco)
+{
+    fsl_shw_return_t status = FSL_RETURN_OK_S;
+
+
+    /* check if file is opened */
+    if (uco->sahara_openfd < 0) {
+        status = FSL_RETURN_NO_RESOURCE_S;
+    } else {
+        /* check flag combination: the only invalid setting of the
+         * blocking and callback flags is blocking with callback. So check
+         * for that
+         */
+        if ((uco->flags & (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) ==
+                         (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) {
+            status = FSL_RETURN_BAD_FLAG_S;
+        } else {
+            /* check that memory utilities have been attached */
+            if (uco->mem_util == NULL) {
+                status = FSL_RETURN_MEMORY_ERROR_S;
+            } else {
+                /* must have pool of at least 1, even for blocking mode */
+                if (uco->pool_size == 0) {
+                    status = FSL_RETURN_ERROR_S;
+                } else {
+                    /* if callback flag is set, it better have a callback
+                     * routine */
+                    if (uco->flags & FSL_UCO_CALLBACK_MODE) {
+                        if (uco->callback == NULL) {
+                            status = FSL_RETURN_INTERNAL_ERROR_S;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return status;
+}
+
+
+/**
+ * Perform any post-processing on non-blocking results.
+ *
+ * For instance, free descriptor chains, compare authentication codes, ...
+ *
+ * @param  user_ctx     User context object
+ * @param  result_info  A set of results
+ */
+void sah_Postprocess_Results(fsl_shw_uco_t* user_ctx, sah_results* result_info)
+{
+    unsigned i;
+
+    /* for each result returned */
+    for (i = 0; i < *result_info->actual; i++) {
+        sah_Head_Desc* desc = result_info->results[i].user_desc;
+        uint8_t* out1 = desc->out1_ptr;
+        uint8_t* out2 = desc->out2_ptr;
+        uint32_t len = desc->out_len;
+
+        /*
+         * For now, tne only post-processing besides freeing the
+         * chain is the need to check the auth code for fsl_shw_auth_decrypt().
+         *
+         * If other uses are required in the future, this code will probably
+         * need a flag in the sah_Head_Desc (or a function pointer!) to
+         * determine what needs to be done.
+         */
+        if ((out1 != NULL) && (out2 != NULL)) {
+            unsigned j;
+            for (j = 0; j < len; j++) {
+                if (out1[j] != out2[j]) {
+                    /* Problem detected.  Change result. */
+                    result_info->results[i].code = FSL_RETURN_AUTH_FAILED_S;
+                    break;
+                }
+            }
+            /* free allocated 'calced_auth' */
+            user_ctx->mem_util->
+                mu_free(user_ctx->mem_util->mu_ref, out1);
+        }
+
+        /* Free the API-created chain, unless tagged as not-from-API */
+        if (! (desc->uco_flags & FSL_UCO_SAVE_DESC_CHAIN)) {
+            sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc);
+        }
+    }
+}
+
+
+/* End of sf_util.c */
diff --git a/drivers/mxc/security/scc2_driver.c b/drivers/mxc/security/scc2_driver.c
new file mode 100644
index 000000000000..3249405c86a1
--- /dev/null
+++ b/drivers/mxc/security/scc2_driver.c
@@ -0,0 +1,2390 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*! @file scc2_driver.c
+ *
+ * This is the driver code for the Security Controller version 2 (SCC2).  It's
+ * interaction with the Linux kernel is from calls to #scc_init() when the
+ * driver is loaded, and #scc_cleanup() should the driver be unloaded.  The
+ * driver uses locking and (task-sleep/task-wakeup) functions from the kernel.
+ * It also registers itself to handle the interrupt line(s) from the SCC.  New
+ * to this version of the driver is an interface providing access to the secure
+ * partitions.  This is in turn exposed to the API user through the
+ * fsl_shw_smalloc() series of functions.  Other drivers in the kernel may use
+ * the remaining API functions to get at the services of the SCC.  The main
+ * service provided is the Secure Memory, which allows encoding and decoding of
+ * secrets with a per-chip secret key.
+ *
+ * The SCC is single-threaded, and so is this module.  When the scc_crypt()
+ * routine is called, it will lock out other accesses to the function.  If
+ * another task is already in the module, the subsequent caller will spin on a
+ * lock waiting for the other access to finish.
+ *
+ * Note that long crypto operations could cause a task to spin for a while,
+ * preventing other kernel work (other than interrupt processing) to get done.
+ *
+ * The external (kernel module) interface is through the following functions:
+ * @li scc_get_configuration() @li scc_crypt() @li scc_zeroize_memories() @li
+ * scc_monitor_security_failure() @li scc_stop_monitoring_security_failure()
+ * @li scc_set_sw_alarm() @li scc_read_register() @li scc_write_register() @li
+ * scc_allocate_partition() @li scc_initialize_partition @li
+ * scc_release_partition() @li scc_diminish_permissions @li
+ * scc_encrypt_region() @li scc_decrypt_region() @li scc_virt_to_phys
+ *
+ * All other functions are internal to the driver.
+ */
+
+#include "sahara2/include/portable_os.h"
+#include "scc2_internals.h"
+#include <linux/delay.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+
+#include <linux/device.h>
+#include <mach/clock.h>
+#include <linux/device.h>
+
+#else
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#endif
+
+#include <linux/dmapool.h>
+
+/**
+ * This is the set of errors which signal that access to the SCM RAM has
+ * failed or will fail.
+ */
+#define SCM_ACCESS_ERRORS                                                  \
+       (SCM_ERRSTAT_ILM | SCM_ERRSTAT_SUP | SCM_ERRSTAT_ERC_MASK)
+
+/******************************************************************************
+ *
+ *  Global / Static Variables
+ *
+ *****************************************************************************/
+
+#ifdef SCC_REGISTER_DEBUG
+
+#define REG_PRINT_BUFFER_SIZE 200
+
+static char reg_print_buffer[REG_PRINT_BUFFER_SIZE];
+
+typedef char *(*reg_print_routine_t) (uint32_t value, char *print_buffer,
+				      int buf_size);
+
+#endif
+
+/**
+ * This is type void* so that a) it cannot directly be dereferenced,
+ * and b) pointer arithmetic on it will function in a 'normal way' for
+ * the offsets in scc_defines.h
+ *
+ * scc_base is the location in the iomap where the SCC's registers
+ * (and memory) start.
+ *
+ * The referenced data is declared volatile so that the compiler will
+ * not make any assumptions about the value of registers in the SCC,
+ * and thus will always reload the register into CPU memory before
+ * using it (i.e. wherever it is referenced in the driver).
+ *
+ * This value should only be referenced by the #SCC_READ_REGISTER and
+ * #SCC_WRITE_REGISTER macros and their ilk.  All dereferences must be
+ * 32 bits wide.
+ */
+static volatile void *scc_base;
+uint32_t scc_phys_base;
+
+/** Array to hold function pointers registered by
+    #scc_monitor_security_failure() and processed by
+    #scc_perform_callbacks() */
+static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void);
+/*SCC need IRAM's base address but use only the partitions allocated for it.*/
+uint32_t scm_ram_phys_base;
+
+void *scm_ram_base = NULL;
+
+/** Calculated once for quick reference to size of the unreserved space in
+ *  RAM in SCM.
+ */
+uint32_t scm_memory_size_bytes;
+
+/** Structure returned by #scc_get_configuration() */
+static scc_config_t scc_configuration = {
+	.driver_major_version = SCC_DRIVER_MAJOR_VERSION,
+	.driver_minor_version = SCC_DRIVER_MINOR_VERSION_2,
+	.scm_version = -1,
+	.smn_version = -1,
+	.block_size_bytes = -1,
+	.partition_size_bytes = -1,
+	.partition_count = -1,
+};
+
+/** Internal flag to know whether SCC is in Failed state (and thus many
+ *  registers are unavailable).  Once it goes failed, it never leaves it. */
+static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL;
+
+/** Flag to say whether interrupt handler has been registered for
+ * SMN interrupt */
+static int smn_irq_set = 0;
+
+/** Flag to say whether interrupt handler has been registered for
+ * SCM interrupt */
+static int scm_irq_set = 0;
+
+/** This lock protects the #scc_callbacks list as well as the @c
+ * callbacks_performed flag in #scc_perform_callbacks.  Since the data this
+ * protects may be read or written from either interrupt or base level, all
+ * operations should use the irqsave/irqrestore or similar to make sure that
+ * interrupts are inhibited when locking from base level.
+ */
+static os_lock_t scc_callbacks_lock = NULL;
+
+/**
+ * Ownership of this lock prevents conflicts on the crypto operation in the
+ * SCC.
+ */
+static os_lock_t scc_crypto_lock = NULL;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18))
+/** Pointer to SCC's clock information.  Initialized during scc_init(). */
+static struct clk *scc_clk = NULL;
+#endif
+
+/** The lookup table for an 8-bit value.  Calculated once
+ * by #scc_init_ccitt_crc().
+ */
+static uint16_t scc_crc_lookup_table[256];
+
+/******************************************************************************
+ *
+ *  Function Implementations - Externally Accessible
+ *
+ *****************************************************************************/
+
+/**
+ * Allocate a partition of secure memory
+ *
+ * @param       smid_value  Value to use for the SMID register.  Must be 0 for
+ *                          kernel mode access.
+ * @param[out]  part_no     (If successful) Assigned partition number.
+ * @param[out]  part_base   Kernel virtual address of the partition.
+ * @param[out]  part_phys   Physical address of the partition.
+ *
+ * @return
+ */
+scc_return_t scc_allocate_partition(uint32_t smid_value,
+				    int *part_no,
+				    void **part_base, uint32_t *part_phys)
+{
+	uint32_t i;
+	os_lock_context_t irq_flags = 0;	/* for IRQ save/restore */
+	int local_part;
+	scc_return_t retval = SCC_RET_FAIL;
+	void *base_addr = NULL;
+	uint32_t reg_value;
+
+	local_part = -1;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+	if (scc_availability == SCC_STATUS_UNIMPLEMENTED) {
+		goto out;
+	}
+
+	/* ACQUIRE LOCK to prevent others from using crypto or acquiring a
+	 * partition.  Note that crypto operations could take a long time, so the
+	 * calling process could potentially spin for some time.
+	 */
+	os_lock_save_context(scc_crypto_lock, irq_flags);
+
+	do {
+		/* Find current state of partition ownership */
+		reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG);
+
+		/* Search for a free one */
+		for (i = 0; i < scc_configuration.partition_count; i++) {
+			if (((reg_value >> (SCM_POWN_SHIFT * i))
+			     & SCM_POWN_MASK) == SCM_POWN_PART_FREE) {
+				break;	/* found a free one */
+			}
+		}
+		if (i == local_part) {
+			/* found this one last time, and failed to allocated it */
+			pr_debug(KERN_ERR "Partition %d cannot be allocated\n",
+				 i);
+			goto out;
+		}
+		if (i >= scc_configuration.partition_count) {
+			retval = SCC_RET_INSUFFICIENT_SPACE;	/* all used up */
+			goto out;
+		}
+
+		pr_debug
+		    ("SCC2: Attempting to allocate partition %i, owners:%08x\n",
+		     i, SCC_READ_REGISTER(SCM_PART_OWNERS_REG));
+
+		local_part = i;
+		/* Store SMID to grab a partition */
+		SCC_WRITE_REGISTER(SCM_SMID0_REG +
+				   SCM_SMID_WIDTH * (local_part), smid_value);
+		mdelay(2);
+
+		/* Now make sure it is ours... ? */
+		reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG);
+
+		if (((reg_value >> (SCM_POWN_SHIFT * (local_part)))
+		     & SCM_POWN_MASK) != SCM_POWN_PART_OWNED) {
+			continue;	/* try for another */
+		}
+		base_addr = scm_ram_base +
+		    (local_part * scc_configuration.partition_size_bytes);
+		break;
+	} while (1);
+
+out:
+
+	/* Free the lock */
+	os_unlock_restore_context(scc_callbacks_lock, irq_flags);
+
+	/* If the base address was assigned, then a partition was successfully
+	 * acquired.
+	 */
+	if (base_addr != NULL) {
+		pr_debug("SCC2 Part owners: %08x, engaged: %08x\n",
+			 reg_value, SCC_READ_REGISTER(SCM_PART_ENGAGED_REG));
+		pr_debug("SCC2 MAP for part %d: %08x\n",
+			 local_part,
+			 SCC_READ_REGISTER(SCM_ACC0_REG + 8 * local_part));
+
+		/* Copy the partition information to the data structures passed by the
+		 * user.
+		 */
+		*part_no = local_part;
+		*part_base = base_addr;
+		*part_phys = (uint32_t) scm_ram_phys_base
+		    + (local_part * scc_configuration.partition_size_bytes);
+		retval = SCC_RET_OK;
+
+		pr_debug
+		    ("SCC2 partition engaged.  Kernel address: %p.  Physical "
+		     "address: %p, pfn: %08x\n", *part_base, (void *)*part_phys,
+		     __phys_to_pfn(*part_phys));
+	}
+
+	return retval;
+}				/* allocate_partition() */
+
+/**
+ * Release a partition of secure memory
+ *
+ * @param   part_base   Kernel virtual address of the partition to be released.
+ *
+ * @return  SCC_RET_OK if successful.
+ */
+scc_return_t scc_release_partition(void *part_base)
+{
+	uint32_t partition_no;
+
+	if (part_base == NULL) {
+		return SCC_RET_FAIL;
+	}
+
+	/* Ensure that this is a proper partition location */
+	partition_no = SCM_PART_NUMBER((uint32_t) part_base);
+
+	pr_debug("SCC2: Attempting to release partition %i, owners:%08x\n",
+		 partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG));
+
+	/* check that the partition is ours to de-establish */
+	if (!host_owns_partition(partition_no)) {
+		return SCC_RET_FAIL;
+	}
+
+	/* TODO: The state of the zeroize engine (SRS field in the Command Status
+	 * Register) should be examined before issuing the zeroize command here.
+	 * To make the driver thread-safe, a lock should be taken out before
+	 * issuing the check and released after the zeroize command has been
+	 * issued.
+	 */
+
+	/* Zero the partition to release it */
+	scc_write_register(SCM_ZCMD_REG,
+			   (partition_no << SCM_ZCMD_PART_SHIFT) |
+			   (ZCMD_DEALLOC_PART << SCM_ZCMD_CCMD_SHIFT));
+	mdelay(2);
+
+	pr_debug("SCC2: done releasing partition %i, owners:%08x\n",
+		 partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG));
+
+	/* Check that the de-assignment went correctly */
+	if (host_owns_partition(partition_no)) {
+		return SCC_RET_FAIL;
+	}
+
+	return SCC_RET_OK;
+}
+
+/**
+ * Diminish the permissions on a partition of secure memory
+ *
+ * @param   part_base     Kernel virtual address of the partition.
+ * @param   permissions   ORed values of the type SCM_PERM_* which will be used as
+ *                        initial partition permissions.  SHW API users should use
+ *                        the FSL_PERM_* definitions instead.
+ *
+ * @return  SCC_RET_OK if successful.
+ */
+scc_return_t scc_diminish_permissions(void *part_base, uint32_t permissions)
+{
+	uint32_t partition_no;
+	uint32_t permissions_requested;
+	permissions_requested = permissions;
+
+	/* ensure that this is a proper partition location */
+	partition_no = SCM_PART_NUMBER((uint32_t) part_base);
+
+	/* invert the permissions, masking out unused bits */
+	permissions = (~permissions) & SCM_PERM_MASK;
+
+	/* attempt to diminish the permissions */
+	scc_write_register(SCM_ACC0_REG + 8 * partition_no, permissions);
+	mdelay(2);
+
+	/* Reading it back puts it into the original form */
+	permissions = SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no);
+	if (permissions == permissions_requested) {
+		pr_debug("scc_partition_diminish_perms: successful\n");
+		pr_debug("scc_partition_diminish_perms: successful\n");
+		return SCC_RET_OK;
+	}
+	pr_debug("scc_partition_diminish_perms: not successful\n");
+
+	return SCC_RET_FAIL;
+}
+
+extern scc_partition_status_t scc_partition_status(void *part_base)
+{
+	uint32_t part_no;
+	uint32_t part_owner;
+
+	/* Determine the partition number from the address */
+	part_no = SCM_PART_NUMBER((uint32_t) part_base);
+
+	/* Check if the partition is implemented */
+	if (part_no >= scc_configuration.partition_count) {
+		return SCC_PART_S_UNUSABLE;
+	}
+
+	/* Determine the value of the partition owners register */
+	part_owner = (SCC_READ_REGISTER(SCM_PART_OWNERS_REG)
+		      >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK;
+
+	switch (part_owner) {
+	case SCM_POWN_PART_OTHER:
+		return SCC_PART_S_UNAVAILABLE;
+		break;
+	case SCM_POWN_PART_FREE:
+		return SCC_PART_S_AVAILABLE;
+		break;
+	case SCM_POWN_PART_OWNED:
+		/* could be allocated or engaged*/
+		if (partition_engaged(part_no)) {
+			return SCC_PART_S_ENGAGED;
+		} else {
+			return SCC_PART_S_ALLOCATED;
+		}
+		break;
+	case SCM_POWN_PART_UNUSABLE:
+	default:
+		return SCC_PART_S_UNUSABLE;
+		break;
+	}
+}
+
+/**
+ * Calculate the physical address from the kernel virtual address.
+ *
+ * @param   address Kernel virtual address of data in an Secure Partition.
+ * @return  Physical address of said data.
+ */
+uint32_t scc_virt_to_phys(void *address)
+{
+	return (uint32_t) address - (uint32_t) scm_ram_base
+	    + (uint32_t) scm_ram_phys_base;
+}
+
+/**
+ * Engage partition of secure memory
+ *
+ * @param part_base (kernel) Virtual
+ * @param UMID NULL, or 16-byte UMID for partition security
+ * @param permissions ORed values from fsl_shw_permission_t which
+ * will be used as initial partiition permissions.
+ *
+ * @return SCC_RET_OK if successful.
+ */
+
+scc_return_t
+scc_engage_partition(void *part_base,
+		     const uint8_t *UMID, uint32_t permissions)
+{
+	uint32_t partition_no;
+	uint8_t *UMID_base = part_base + 0x10;
+	uint32_t *MAP_base = part_base;
+	uint8_t i;
+
+	partition_no = SCM_PART_NUMBER((uint32_t) part_base);
+
+	if (!host_owns_partition(partition_no) ||
+	    partition_engaged(partition_no) ||
+	    !(SCC_READ_REGISTER(SCM_SMID0_REG + (partition_no * 8)) == 0)) {
+
+		return SCC_RET_FAIL;
+	}
+
+	if (UMID != NULL) {
+		for (i = 0; i < 16; i++) {
+			UMID_base[i] = UMID[i];
+		}
+	}
+
+	MAP_base[0] = permissions;
+
+	udelay(20);
+
+	/* Check that the partition was engaged correctly, and that it has the
+	 * proper permissions.
+	 */
+
+	if ((!partition_engaged(partition_no)) ||
+	    (permissions !=
+	     SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no))) {
+		return SCC_RET_FAIL;
+	}
+
+	return SCC_RET_OK;
+}
+
+/*****************************************************************************/
+/* fn scc_init()                                                             */
+/*****************************************************************************/
+/**
+ *  Initialize the driver at boot time or module load time.
+ *
+ *  Register with the kernel as the interrupt handler for the SCC interrupt
+ *  line(s).
+ *
+ *  Map the SCC's register space into the driver's memory space.
+ *
+ *  Query the SCC for its configuration and status.  Save the configuration in
+ *  #scc_configuration and save the status in #scc_availability.  Called by the
+ *  kernel.
+ *
+ *  Do any locking/wait queue initialization which may be necessary.
+ *
+ *  The availability fuse may be checked, depending on platform.
+ */
+static int scc_init(void)
+{
+	uint32_t smn_status;
+	int i;
+	int return_value = -EIO;	/* assume error */
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+
+		/* Set this until we get an initial reading */
+		scc_availability = SCC_STATUS_CHECKING;
+
+		/* Initialize the constant for the CRC function */
+		scc_init_ccitt_crc();
+
+		/* initialize the callback table */
+		for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+			scc_callbacks[i] = 0;
+		}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
+		mxc_clks_enable(SCC_CLK);
+#else
+		scc_clk = clk_get(NULL, "scc_clk");
+		if (scc_clk != ERR_PTR(ENOENT)) {
+			clk_enable(scc_clk);
+		}
+#endif
+
+		/* Set up the hardware access locks */
+		scc_callbacks_lock = os_lock_alloc_init();
+		scc_crypto_lock = os_lock_alloc_init();
+		if (scc_callbacks_lock == NULL || scc_crypto_lock == NULL) {
+			os_printk(KERN_ERR
+				  "SCC2: Failed to allocate context locks.  Exiting.\n");
+			goto out;
+		}
+
+		/* See whether there is an SCC available */
+		if (0 && !SCC_ENABLED()) {
+			os_printk(KERN_ERR
+				  "SCC2: Fuse for SCC is set to disabled.  Exiting.\n");
+			goto out;
+		}
+		/* Map the SCC (SCM and SMN) memory on the internal bus into
+		   kernel address space */
+		scc_base = (void *)ioremap(scc_phys_base, SZ_4K);
+		if (scc_base == NULL) {
+			os_printk(KERN_ERR
+				  "SCC2: Register mapping failed.  Exiting.\n");
+			goto out;
+		}
+
+		/* If that worked, we can try to use the SCC */
+		/* Get SCM into 'clean' condition w/interrupts cleared &
+		   disabled */
+		SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0);
+
+		/* Clear error status register */
+		(void)SCC_READ_REGISTER(SCM_ERR_STATUS_REG);
+
+		/*
+		 * There is an SCC.  Determine its current state.  Side effect
+		 * is to populate scc_config and scc_availability
+		 */
+		smn_status = scc_grab_config_values();
+
+		/* Try to set up interrupt handler(s) */
+		if (scc_availability != SCC_STATUS_OK) {
+			goto out;
+		}
+
+		if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
+			scm_ram_phys_base += 0x8000;
+
+		scm_ram_base = (void *)ioremap_nocache(scm_ram_phys_base,
+						       scc_configuration.
+						       partition_count *
+						       scc_configuration.
+						       partition_size_bytes);
+		if (scm_ram_base == NULL) {
+			os_printk(KERN_ERR
+				  "SCC2: RAM failed to remap: %p for %d bytes\n",
+				  (void *)scm_ram_phys_base,
+				  scc_configuration.partition_count *
+				  scc_configuration.partition_size_bytes);
+			goto out;
+		}
+		pr_debug("SCC2: RAM at Physical %p / Virtual %p\n",
+			 (void *)scm_ram_phys_base, scm_ram_base);
+
+		pr_debug("Secure Partition Table: Found %i partitions\n",
+			 scc_configuration.partition_count);
+
+		if (setup_interrupt_handling() != 0) {
+			unsigned err_cond;
+	    /**
+		* The error could be only that the SCM interrupt was
+		* not set up.  This interrupt is always masked, so
+		* that is not an issue.
+		* The SMN's interrupt may be shared on that line, it
+		* may be separate, or it may not be wired.  Do what
+		* is necessary to check its status.
+		* Although the driver is coded for possibility of not
+		* having SMN interrupt, the fact that there is one
+		* means it should be available and used.
+		*/
+#ifdef USE_SMN_INTERRUPT
+			err_cond = !smn_irq_set;	/* Separate. Check SMN binding */
+#elif !defined(NO_SMN_INTERRUPT)
+			err_cond = !scm_irq_set;	/* Shared. Check SCM binding */
+#else
+			err_cond = FALSE;	/*  SMN not wired at all.  Ignore. */
+#endif
+			if (err_cond) {
+				/* setup was not able to set up SMN interrupt */
+				scc_availability = SCC_STATUS_UNIMPLEMENTED;
+				goto out;
+			}
+		}
+
+		/* interrupt handling returned non-zero */
+		/* Get SMN into 'clean' condition w/interrupts cleared &
+		   enabled */
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_CLEAR_INTERRUPT
+				   | SMN_COMMAND_ENABLE_INTERRUPT);
+
+	      out:
+		/*
+		 * If status is SCC_STATUS_UNIMPLEMENTED or is still
+		 * SCC_STATUS_CHECKING, could be leaving here with the driver partially
+		 * initialized.  In either case, cleanup (which will mark the SCC as
+		 * UNIMPLEMENTED).
+		 */
+		if (scc_availability == SCC_STATUS_CHECKING ||
+		    scc_availability == SCC_STATUS_UNIMPLEMENTED) {
+			scc_cleanup();
+		} else {
+			return_value = 0;	/* All is well */
+		}
+	}
+	/* ! STATUS_INITIAL */
+	os_printk(KERN_ALERT "SCC2: Driver Status is %s\n",
+		  (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" :
+		  (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" :
+		  (scc_availability ==
+		   SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED"
+		  : (scc_availability ==
+		     SCC_STATUS_OK) ? "OK" : (scc_availability ==
+					      SCC_STATUS_FAILED) ? "FAILED" :
+		  "UNKNOWN");
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+			mxc_clks_disable(SCC_CLK);
+#else
+			if (scc_clk != ERR_PTR(ENOENT))
+				clk_disable(scc_clk);
+#endif
+
+	return return_value;
+}				/* scc_init */
+
+/*****************************************************************************/
+/* fn scc_cleanup()                                                          */
+/*****************************************************************************/
+/**
+ * Perform cleanup before driver/module is unloaded by setting the machine
+ * state close to what it was when the driver was loaded.  This function is
+ * called when the kernel is shutting down or when this driver is being
+ * unloaded.
+ *
+ * A driver like this should probably never be unloaded, especially if there
+ * are other module relying upon the callback feature for monitoring the SCC
+ * status.
+ *
+ * In any case, cleanup the callback table (by clearing out all of the
+ * pointers).  Deregister the interrupt handler(s).  Unmap SCC registers.
+ *
+ * Note that this will not release any partitions that have been allocated.
+ *
+ */
+static void scc_cleanup(void)
+{
+	int i;
+
+    /******************************************************/
+
+	/* Mark the driver / SCC as unusable. */
+	scc_availability = SCC_STATUS_UNIMPLEMENTED;
+
+	/* Clear out callback table */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		scc_callbacks[i] = 0;
+	}
+
+	/* If SCC has been mapped in, clean it up and unmap it */
+	if (scc_base) {
+		/* For the SCM, disable interrupts. */
+		SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0);
+
+		/* For the SMN, clear and disable interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_CLEAR_INTERRUPT);
+	}
+
+	/* Now that interrupts cannot occur, disassociate driver from the interrupt
+	 * lines.
+	 */
+
+	/* Deregister SCM interrupt handler */
+	if (scm_irq_set) {
+		os_deregister_interrupt(INT_SCC_SCM);
+	}
+
+	/* Deregister SMN interrupt handler */
+	if (smn_irq_set) {
+#ifdef USE_SMN_INTERRUPT
+		os_deregister_interrupt(INT_SCC_SMN);
+#endif
+	}
+
+	/* Finally, release the mapped memory */
+	iounmap(scm_ram_base);
+
+	if (scc_callbacks_lock != NULL)
+		os_lock_deallocate(scc_callbacks_lock);
+
+	if (scc_crypto_lock != NULL)
+		os_lock_deallocate(scc_crypto_lock);
+
+    /*Disabling SCC Clock*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+			mxc_clks_disable(SCC_CLK);
+#else
+			if (scc_clk != ERR_PTR(ENOENT))
+				clk_disable(scc_clk);
+			clk_put(scc_clk);
+#endif
+	pr_debug("SCC2 driver cleaned up.\n");
+
+}				/* scc_cleanup */
+
+/*****************************************************************************/
+/* fn scc_get_configuration()                                                */
+/*****************************************************************************/
+scc_config_t *scc_get_configuration(void)
+{
+	/*
+	 * If some other driver calls scc before the kernel does, make sure that
+	 * this driver's initialization is performed.
+	 */
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+    /**
+     * If there is no SCC, yet the driver exists, the value -1 will be in
+     * the #scc_config_t fields for other than the driver versions.
+     */
+	return &scc_configuration;
+}				/* scc_get_configuration */
+
+/*****************************************************************************/
+/* fn scc_zeroize_memories()                                                 */
+/*****************************************************************************/
+scc_return_t scc_zeroize_memories(void)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+
+	return return_status;
+}				/* scc_zeroize_memories */
+
+/*****************************************************************************/
+/* fn scc_set_sw_alarm()                                                     */
+/*****************************************************************************/
+void scc_set_sw_alarm(void)
+{
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Update scc_availability based on current SMN status.  This might
+	 * perform callbacks.
+	 */
+	(void)scc_update_state();
+
+	/* if everything is OK, make it fail */
+	if (scc_availability == SCC_STATUS_OK) {
+
+		/* sound the alarm (and disable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_SET_SOFTWARE_ALARM);
+
+		scc_availability = SCC_STATUS_FAILED;	/* Remember what we've done */
+
+		/* In case SMN interrupt is not available, tell the world */
+		scc_perform_callbacks();
+	}
+
+	return;
+}				/* scc_set_sw_alarm */
+
+/*****************************************************************************/
+/* fn scc_monitor_security_failure()                                         */
+/*****************************************************************************/
+scc_return_t scc_monitor_security_failure(void callback_func(void))
+{
+	int i;
+	os_lock_context_t irq_flags;	/* for IRQ save/restore */
+	scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS;
+	int function_stored = FALSE;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Acquire lock of callbacks table.  Could be spin_lock_irq() if this
+	 * routine were just called from base (not interrupt) level
+	 */
+	os_lock_save_context(scc_callbacks_lock, irq_flags);
+
+	/* Search through table looking for empty slot */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		if (scc_callbacks[i] == callback_func) {
+			if (function_stored) {
+				/* Saved duplicate earlier.  Clear this later one. */
+				scc_callbacks[i] = NULL;
+			}
+			/* Exactly one copy is now stored */
+			return_status = SCC_RET_OK;
+			break;
+		} else if (scc_callbacks[i] == NULL && !function_stored) {
+			/* Found open slot.  Save it and remember */
+			scc_callbacks[i] = callback_func;
+			return_status = SCC_RET_OK;
+			function_stored = TRUE;
+		}
+	}
+
+	/* Free the lock */
+	os_unlock_restore_context(scc_callbacks_lock, irq_flags);
+
+	return return_status;
+}				/* scc_monitor_security_failure */
+
+/*****************************************************************************/
+/* fn scc_stop_monitoring_security_failure()                                 */
+/*****************************************************************************/
+void scc_stop_monitoring_security_failure(void callback_func(void))
+{
+	os_lock_context_t irq_flags;	/* for IRQ save/restore */
+	int i;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* Acquire lock of callbacks table.  Could be spin_lock_irq() if this
+	 * routine were just called from base (not interrupt) level
+	 */
+	os_lock_save_context(scc_callbacks_lock, irq_flags);
+
+	/* Search every entry of the table for this function */
+	for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+		if (scc_callbacks[i] == callback_func) {
+			scc_callbacks[i] = NULL;	/* found instance - clear it out */
+			break;
+		}
+	}
+
+	/* Free the lock */
+	os_unlock_restore_context(scc_callbacks_lock, irq_flags);
+
+	return;
+}				/* scc_stop_monitoring_security_failure */
+
+/*****************************************************************************/
+/* fn scc_read_register()                                                    */
+/*****************************************************************************/
+scc_return_t scc_read_register(int register_offset, uint32_t * value)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+	uint32_t smn_status;
+	uint32_t scm_status;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* First layer of protection -- completely unaccessible SCC */
+	if (scc_availability != SCC_STATUS_UNIMPLEMENTED) {
+
+		/* Second layer -- that offset is valid */
+		if (register_offset != SMN_BB_DEC_REG &&	/* write only! */
+		    check_register_offset(register_offset) == SCC_RET_OK) {
+
+			/* Get current status / update local state */
+			smn_status = scc_update_state();
+			scm_status = SCC_READ_REGISTER(SCM_STATUS_REG);
+
+			/*
+			 * Third layer - verify that the register being requested is
+			 * available in the current state of the SCC.
+			 */
+			if ((return_status =
+			     check_register_accessible(register_offset,
+						       smn_status,
+						       scm_status)) ==
+			    SCC_RET_OK) {
+				*value = SCC_READ_REGISTER(register_offset);
+			}
+		}
+	}
+
+	return return_status;
+}				/* scc_read_register */
+
+/*****************************************************************************/
+/* fn scc_write_register()                                                   */
+/*****************************************************************************/
+scc_return_t scc_write_register(int register_offset, uint32_t value)
+{
+	scc_return_t return_status = SCC_RET_FAIL;
+	uint32_t smn_status;
+	uint32_t scm_status;
+
+	if (scc_availability == SCC_STATUS_INITIAL) {
+		scc_init();
+	}
+
+	/* First layer of protection -- completely unaccessible SCC */
+	if (scc_availability != SCC_STATUS_UNIMPLEMENTED) {
+
+		/* Second layer -- that offset is valid */
+		if (!((register_offset == SCM_STATUS_REG) ||	/* These registers are */
+		      (register_offset == SCM_VERSION_REG) ||	/*  Read Only */
+		      (register_offset == SMN_BB_CNT_REG) ||
+		      (register_offset == SMN_TIMER_REG)) &&
+		    check_register_offset(register_offset) == SCC_RET_OK) {
+
+			/* Get current status / update local state */
+			smn_status = scc_update_state();
+			scm_status = SCC_READ_REGISTER(SCM_STATUS_REG);
+
+			/*
+			 * Third layer - verify that the register being requested is
+			 * available in the current state of the SCC.
+			 */
+			if (check_register_accessible
+			    (register_offset, smn_status, scm_status) == 0) {
+				SCC_WRITE_REGISTER(register_offset, value);
+				return_status = SCC_RET_OK;
+			}
+		}
+	}
+
+	return return_status;
+}				/* scc_write_register() */
+
+/******************************************************************************
+ *
+ *  Function Implementations - Internal
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/* fn scc_irq()                                                              */
+/*****************************************************************************/
+/**
+ * This is the interrupt handler for the SCC.
+ *
+ * This function checks the SMN Status register to see whether it
+ * generated the interrupt, then it checks the SCM Status register to
+ * see whether it needs attention.
+ *
+ * If an SMN Interrupt is active, then the SCC state set to failure, and
+ * #scc_perform_callbacks() is invoked to notify any interested parties.
+ *
+ * The SCM Interrupt should be masked, as this driver uses polling to determine
+ * when the SCM has completed a crypto or zeroing operation.  Therefore, if the
+ * interrupt is active, the driver will just clear the interrupt and (re)mask.
+ */
+OS_DEV_ISR(scc_irq)
+{
+	uint32_t smn_status;
+	uint32_t scm_status;
+	int handled = 0;	/* assume interrupt isn't from SMN */
+#if defined(USE_SMN_INTERRUPT)
+	int smn_irq = INT_SCC_SMN;	/* SMN interrupt is on a line by itself */
+#elif defined (NO_SMN_INTERRUPT)
+	int smn_irq = -1;	/* not wired to CPU at all */
+#else
+	int smn_irq = INT_SCC_SCM;	/* SMN interrupt shares a line with SCM */
+#endif
+
+	/* Update current state... This will perform callbacks... */
+	smn_status = scc_update_state();
+
+	/* SMN is on its own interrupt line.  Verify the IRQ was triggered
+	 * before clearing the interrupt and marking it handled.  */
+	if ((os_dev_get_irq() == smn_irq) &&
+	    (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) {
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_CLEAR_INTERRUPT);
+		handled++;	/* tell kernel that interrupt was handled */
+	}
+
+	/* Check on the health of the SCM */
+	scm_status = SCC_READ_REGISTER(SCM_STATUS_REG);
+
+	/* The driver masks interrupts, so this should never happen. */
+	if (os_dev_get_irq() == INT_SCC_SCM) {
+		/* but if it does, try to prevent it in the future */
+		SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0);
+		handled++;
+	}
+
+	/* Any non-zero value of handled lets kernel know we got something */
+	os_dev_isr_return(handled);
+}
+
+/*****************************************************************************/
+/* fn scc_perform_callbacks()                                                */
+/*****************************************************************************/
+/** Perform callbacks registered by #scc_monitor_security_failure().
+ *
+ *  Make sure callbacks only happen once...  Since there may be some reason why
+ *  the interrupt isn't generated, this routine could be called from base(task)
+ *  level.
+ *
+ *  One at a time, go through #scc_callbacks[] and call any non-null pointers.
+ */
+static void scc_perform_callbacks(void)
+{
+	static int callbacks_performed = 0;
+	unsigned long irq_flags;	/* for IRQ save/restore */
+	int i;
+
+	/* Acquire lock of callbacks table and callbacks_performed flag */
+	os_lock_save_context(scc_callbacks_lock, irq_flags);
+
+	if (!callbacks_performed) {
+		callbacks_performed = 1;
+
+		/* Loop over all of the entries in the table */
+		for (i = 0; i < SCC_CALLBACK_SIZE; i++) {
+			/* If not null, ... */
+			if (scc_callbacks[i]) {
+				scc_callbacks[i] ();	/* invoke the callback routine */
+			}
+		}
+	}
+
+	os_unlock_restore_context(scc_callbacks_lock, irq_flags);
+
+	return;
+}
+
+/*****************************************************************************/
+/* fn scc_update_state()                                                     */
+/*****************************************************************************/
+/**
+ * Make certain SCC is still running.
+ *
+ * Side effect is to update #scc_availability and, if the state goes to failed,
+ * run #scc_perform_callbacks().
+ *
+ * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be
+ * in health check state)
+ *
+ * @return Current value of #SMN_STATUS_REG register.
+ */
+static uint32_t scc_update_state(void)
+{
+	uint32_t smn_status_register = SMN_STATE_FAIL;
+	int smn_state;
+
+	/* if FAIL or UNIMPLEMENTED, don't bother */
+	if (scc_availability == SCC_STATUS_CHECKING ||
+	    scc_availability == SCC_STATUS_OK) {
+
+		smn_status_register = SCC_READ_REGISTER(SMN_STATUS_REG);
+		smn_state = smn_status_register & SMN_STATUS_STATE_MASK;
+
+#ifdef SCC_BRINGUP
+		/* If in Health Check while booting, try to 'bringup' to Secure mode */
+		if (scc_availability == SCC_STATUS_CHECKING &&
+		    smn_state == SMN_STATE_HEALTH_CHECK) {
+			/* Code up a simple algorithm for the ASC */
+			SCC_WRITE_REGISTER(SMN_SEQ_START_REG, 0xaaaa);
+			SCC_WRITE_REGISTER(SMN_SEQ_END_REG, 0x5555);
+			SCC_WRITE_REGISTER(SMN_SEQ_CHECK_REG, 0x5555);
+			/* State should be SECURE now */
+			smn_status_register = SCC_READ_REGISTER(SMN_STATUS);
+			smn_state = smn_status_register & SMN_STATUS_STATE_MASK;
+		}
+#endif
+
+		/*
+		 * State should be SECURE or NON_SECURE for operation of the part.  If
+		 * FAIL, mark failed (i.e. limited access to registers).  Any other
+		 * state, mark unimplemented, as the SCC is unuseable.
+		 */
+		if (smn_state == SMN_STATE_SECURE
+		    || smn_state == SMN_STATE_NON_SECURE) {
+			/* Healthy */
+			scc_availability = SCC_STATUS_OK;
+		} else if (smn_state == SMN_STATE_FAIL) {
+			scc_availability = SCC_STATUS_FAILED;	/* uh oh - unhealthy */
+			scc_perform_callbacks();
+			os_printk(KERN_ERR "SCC2: SCC went into FAILED mode\n");
+		} else {
+			/* START, ZEROIZE RAM, HEALTH CHECK, or unknown */
+			scc_availability = SCC_STATUS_UNIMPLEMENTED;	/* unuseable */
+			os_printk(KERN_ERR
+				  "SCC2: SCC declared UNIMPLEMENTED\n");
+		}
+	}
+	/* if availability is initial or ok */
+	return smn_status_register;
+}
+
+/*****************************************************************************/
+/* fn scc_init_ccitt_crc()                                                   */
+/*****************************************************************************/
+/**
+ * Populate the partial CRC lookup table.
+ *
+ * @return   none
+ *
+ */
+static void scc_init_ccitt_crc(void)
+{
+	int dividend;		/* index for lookup table */
+	uint16_t remainder;	/* partial value for a given dividend */
+	int bit;		/* index into bits of a byte */
+
+	/*
+	 * Compute the remainder of each possible dividend.
+	 */
+	for (dividend = 0; dividend < 256; ++dividend) {
+		/*
+		 * Start with the dividend followed by zeros.
+		 */
+		remainder = dividend << (8);
+
+		/*
+		 * Perform modulo-2 division, a bit at a time.
+		 */
+		for (bit = 8; bit > 0; --bit) {
+			/*
+			 * Try to divide the current data bit.
+			 */
+			if (remainder & 0x8000) {
+				remainder = (remainder << 1) ^ CRC_POLYNOMIAL;
+			} else {
+				remainder = (remainder << 1);
+			}
+		}
+
+		/*
+		 * Store the result into the table.
+		 */
+		scc_crc_lookup_table[dividend] = remainder;
+	}
+
+}				/* scc_init_ccitt_crc() */
+
+/*****************************************************************************/
+/* fn grab_config_values()                                                   */
+/*****************************************************************************/
+/**
+ * grab_config_values() will read the SCM Configuration and SMN Status
+ * registers and store away version and size information for later use.
+ *
+ * @return The current value of the SMN Status register.
+ */
+static uint32_t scc_grab_config_values(void)
+{
+	uint32_t scm_version_register;
+	uint32_t smn_status_register = SMN_STATE_FAIL;
+
+	if (scc_availability != SCC_STATUS_CHECKING) {
+		goto out;
+	}
+	scm_version_register = SCC_READ_REGISTER(SCM_VERSION_REG);
+	pr_debug("SCC2 Driver: SCM version is 0x%08x\n", scm_version_register);
+
+	/* Get SMN status and update scc_availability */
+	smn_status_register = scc_update_state();
+	pr_debug("SCC2 Driver: SMN status is 0x%08x\n", smn_status_register);
+
+	/* save sizes and versions information for later use */
+	scc_configuration.block_size_bytes = 16;	/* BPCP ? */
+	scc_configuration.partition_count =
+	    1 + ((scm_version_register & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT);
+	scc_configuration.partition_size_bytes =
+	    1 << ((scm_version_register & SCM_VER_BPP_MASK) >>
+		  SCM_VER_BPP_SHIFT);
+	scc_configuration.scm_version =
+	    (scm_version_register & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT;
+	scc_configuration.smn_version =
+	    (smn_status_register & SMN_STATUS_VERSION_ID_MASK)
+	    >> SMN_STATUS_VERSION_ID_SHIFT;
+	if (scc_configuration.scm_version != SCM_MAJOR_VERSION_2) {
+		scc_availability = SCC_STATUS_UNIMPLEMENTED;	/* Unknown version */
+	}
+
+      out:
+	return smn_status_register;
+}				/* grab_config_values */
+
+/*****************************************************************************/
+/* fn setup_interrupt_handling()                                             */
+/*****************************************************************************/
+/**
+ * Register the SCM and SMN interrupt handlers.
+ *
+ * Called from #scc_init()
+ *
+ * @return 0 on success
+ */
+static int setup_interrupt_handling(void)
+{
+	int smn_error_code = -1;
+	int scm_error_code = -1;
+
+	/* Disnable SCM interrupts */
+	SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0);
+
+#ifdef USE_SMN_INTERRUPT
+	/* Install interrupt service routine for SMN. */
+	smn_error_code = os_register_interrupt(SCC_DRIVER_NAME,
+					       INT_SCC_SMN, scc_irq);
+	if (smn_error_code != 0) {
+		os_printk(KERN_ERR
+			  "SCC2 Driver: Error installing SMN Interrupt Handler: %d\n",
+			  smn_error_code);
+	} else {
+		smn_irq_set = 1;	/* remember this for cleanup */
+		/* Enable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_CLEAR_INTERRUPT |
+				   SMN_COMMAND_ENABLE_INTERRUPT);
+	}
+#else
+	smn_error_code = 0;	/* no problems... will handle later */
+#endif
+
+	/*
+	 * Install interrupt service routine for SCM (or both together).
+	 */
+	scm_error_code = os_register_interrupt(SCC_DRIVER_NAME,
+					       INT_SCC_SCM, scc_irq);
+	if (scm_error_code != 0) {
+#ifndef MXC
+		os_printk(KERN_ERR
+			  "SCC2 Driver: Error installing SCM Interrupt Handler: %d\n",
+			  scm_error_code);
+#else
+		os_printk(KERN_ERR
+			  "SCC2 Driver: Error installing SCC Interrupt Handler: %d\n",
+			  scm_error_code);
+#endif
+	} else {
+		scm_irq_set = 1;	/* remember this for cleanup */
+#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT)
+		/* Enable SMN interrupts */
+		SCC_WRITE_REGISTER(SMN_COMMAND_REG,
+				   SMN_COMMAND_CLEAR_INTERRUPT |
+				   SMN_COMMAND_ENABLE_INTERRUPT);
+#endif
+	}
+
+	/* Return an error if one was encountered */
+	return scm_error_code ? scm_error_code : smn_error_code;
+}				/* setup_interrupt_handling */
+
+/*****************************************************************************/
+/* fn scc_do_crypto()                                                        */
+/*****************************************************************************/
+/** Have the SCM perform the crypto function.
+ *
+ * Set up length register, and the store @c scm_control into control register
+ * to kick off the operation.  Wait for completion, gather status, clear
+ * interrupt / status.
+ *
+ * @param byte_count  number of bytes to perform in this operation
+ * @param scm_command Bit values to be set in @c SCM_CCMD_REG register
+ *
+ * @return 0 on success, value of #SCM_ERR_STATUS_REG on failure
+ */
+static uint32_t scc_do_crypto(int byte_count, uint32_t scm_command)
+{
+	int block_count = byte_count / SCC_BLOCK_SIZE_BYTES();
+	uint32_t crypto_status;
+	scc_return_t ret;
+
+	/* This seems to be necessary in order to allow subsequent cipher
+	 * operations to succeed when a partition is deallocated/reallocated!
+	 */
+	(void)SCC_READ_REGISTER(SCM_STATUS_REG);
+
+	/* In length register, 0 means 1, etc. */
+	scm_command |= (block_count - 1) << SCM_CCMD_LENGTH_SHIFT;
+
+	/* set modes and kick off the operation */
+	SCC_WRITE_REGISTER(SCM_CCMD_REG, scm_command);
+
+	ret = scc_wait_completion(&crypto_status);
+
+	/* Only done bit should be on */
+	if (crypto_status & SCM_STATUS_ERR) {
+		/* Replace with error status instead */
+		crypto_status = SCC_READ_REGISTER(SCM_ERR_STATUS_REG);
+		pr_debug("SCM Failure: 0x%x\n", crypto_status);
+		if (crypto_status == 0) {
+			/* That came up 0.  Turn on arbitrary bit to signal error. */
+			crypto_status = SCM_ERRSTAT_ILM;
+		}
+	} else {
+		crypto_status = 0;
+	}
+	pr_debug("SCC2: Done waiting.\n");
+
+	return crypto_status;
+}
+
+/**
+ * Encrypt a region of secure memory.
+ *
+ * @param   part_base    Kernel virtual address of the partition.
+ * @param   offset_bytes Offset from the start of the partition to the plaintext
+ *                       data.
+ * @param   byte_count   Length of the region (octets).
+ * @param   black_data   Physical location to store the encrypted data.
+ * @param   IV           Value to use for the IV.
+ * @param   cypher_mode  Cyphering mode to use, specified by type
+ *                       #scc_cypher_mode_t
+ *
+ * @return  SCC_RET_OK if successful.
+ */
+scc_return_t
+scc_encrypt_region(uint32_t part_base, uint32_t offset_bytes,
+		   uint32_t byte_count, uint8_t *black_data,
+		   uint32_t *IV, scc_cypher_mode_t cypher_mode)
+{
+	os_lock_context_t irq_flags;	/* for IRQ save/restore */
+	scc_return_t status = SCC_RET_OK;
+	uint32_t crypto_status;
+	uint32_t scm_command;
+	int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES();
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+				mxc_clks_enable(SCC_CLK);
+#else
+				if (scc_clk != ERR_PTR(ENOENT))
+					clk_enable(scc_clk);
+#endif
+
+	scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) |
+		       (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT));
+
+	switch (cypher_mode) {
+	case SCC_CYPHER_MODE_CBC:
+		scm_command |= SCM_CCMD_AES_ENC_CBC;
+		break;
+	case SCC_CYPHER_MODE_ECB:
+		scm_command |= SCM_CCMD_AES_ENC_ECB;
+		break;
+	default:
+		status = SCC_RET_FAIL;
+		break;
+	}
+
+	pr_debug("Received encrypt request.  SCM_C_BLACK_ST_REG: %p, "
+		 "scm_Command: %08x, length: %i (part_base: %08x, "
+		 "offset: %i)\n",
+		 black_data, scm_command, byte_count, part_base, offset_blocks);
+
+	if (status != SCC_RET_OK)
+		goto out;
+
+	/* ACQUIRE LOCK to prevent others from using crypto or releasing slot */
+	os_lock_save_context(scc_crypto_lock, irq_flags);
+
+	if (status == SCC_RET_OK) {
+		SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data);
+
+		/* Only write the IV if it will actually be used */
+		if (cypher_mode == SCC_CYPHER_MODE_CBC) {
+			/* Write the IV register */
+			SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV));
+			SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1));
+			SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2));
+			SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3));
+		}
+
+		/* Set modes and kick off the encryption */
+		crypto_status = scc_do_crypto(byte_count, scm_command);
+
+		if (crypto_status != 0) {
+			pr_debug("SCM encrypt red crypto failure: 0x%x\n",
+				 crypto_status);
+		} else {
+			status = SCC_RET_OK;
+			pr_debug("SCC2: Encrypted %d bytes\n", byte_count);
+		}
+	}
+
+	os_unlock_restore_context(scc_crypto_lock, irq_flags);
+
+out:
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+					mxc_clks_disable(SCC_CLK);
+#else
+					if (scc_clk != ERR_PTR(ENOENT))
+						clk_disable(scc_clk);
+#endif
+
+	return status;
+}
+
+/* Decrypt a region into secure memory
+ *
+ * @param   part_base    Kernel virtual address of the partition.
+ * @param   offset_bytes Offset from the start of the partition to store the
+ *                       plaintext data.
+ * @param   byte_counts  Length of the region (octets).
+ * @param   black_data   Physical location of the encrypted data.
+ * @param   IV           Value to use for the IV.
+ * @param   cypher_mode  Cyphering mode to use, specified by type
+ *                       #scc_cypher_mode_t
+ *
+ * @return  SCC_RET_OK if successful.
+ */
+scc_return_t
+scc_decrypt_region(uint32_t part_base, uint32_t offset_bytes,
+		   uint32_t byte_count, uint8_t *black_data,
+		   uint32_t *IV, scc_cypher_mode_t cypher_mode)
+{
+	os_lock_context_t irq_flags;	/* for IRQ save/restore */
+	scc_return_t status = SCC_RET_OK;
+	uint32_t crypto_status;
+	uint32_t scm_command;
+	int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES();
+
+    /*Enabling SCC clock.*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+			mxc_clks_enable(SCC_CLK);
+#else
+			if (scc_clk != ERR_PTR(ENOENT))
+				clk_enable(scc_clk);
+#endif
+	scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) |
+		       (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT));
+
+	switch (cypher_mode) {
+	case SCC_CYPHER_MODE_CBC:
+		scm_command |= SCM_CCMD_AES_DEC_CBC;
+		break;
+	case SCC_CYPHER_MODE_ECB:
+		scm_command |= SCM_CCMD_AES_DEC_ECB;
+		break;
+	default:
+		status = SCC_RET_FAIL;
+		break;
+	}
+
+	pr_debug("Received decrypt request.  SCM_C_BLACK_ST_REG: %p, "
+		 "scm_Command: %08x, length: %i (part_base: %08x, "
+		 "offset: %i)\n",
+		 black_data, scm_command, byte_count, part_base, offset_blocks);
+
+	if (status != SCC_RET_OK)
+		goto out;
+
+	/* ACQUIRE LOCK to prevent others from using crypto or releasing slot */
+	os_lock_save_context(scc_crypto_lock, irq_flags);
+
+	if (status == SCC_RET_OK) {
+		status = SCC_RET_FAIL;	/* reset expectations */
+		SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data);
+
+		/* Write the IV register */
+		SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV));
+		SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1));
+		SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2));
+		SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3));
+
+		/* Set modes and kick off the decryption */
+		crypto_status = scc_do_crypto(byte_count, scm_command);
+
+		if (crypto_status != 0) {
+			pr_debug("SCM decrypt black crypto failure: 0x%x\n",
+				 crypto_status);
+		} else {
+			status = SCC_RET_OK;
+			pr_debug("SCC2: Decrypted %d bytes\n", byte_count);
+		}
+	}
+
+	os_unlock_restore_context(scc_crypto_lock, irq_flags);
+out:
+    /*Disabling the Clock when the driver is not in use.*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+			mxc_clks_disable(SCC_CLK);
+#else
+			if (scc_clk != ERR_PTR(ENOENT))
+				clk_disable(scc_clk);
+#endif
+	return status;
+}
+
+/*****************************************************************************/
+/* fn host_owns_partition()                                                  */
+/*****************************************************************************/
+/**
+ * Determine if the host owns a given partition.
+ *
+ * @internal
+ *
+ * @param part_no       Partition number to query
+ *
+ * @return TRUE if the host owns the partition, FALSE otherwise.
+ */
+
+static uint32_t host_owns_partition(uint32_t part_no)
+{
+	uint32_t value;
+
+	if (part_no < scc_configuration.partition_count) {
+
+		/* Check the partition owners register */
+		value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG);
+		if (((value >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK)
+		    == SCM_POWN_PART_OWNED)
+			return TRUE;
+	}
+	return FALSE;
+}
+
+/*****************************************************************************/
+/* fn partition_engaged()                                                    */
+/*****************************************************************************/
+/**
+ * Determine if the given partition is engaged.
+ *
+ * @internal
+ *
+ * @param part_no       Partition number to query
+ *
+ * @return TRUE if the partition is engaged, FALSE otherwise.
+ */
+
+static uint32_t partition_engaged(uint32_t part_no)
+{
+	uint32_t value;
+
+	if (part_no < scc_configuration.partition_count) {
+
+		/* Check the partition engaged register */
+		value = SCC_READ_REGISTER(SCM_PART_ENGAGED_REG);
+		if (((value >> (part_no * SCM_PENG_SHIFT)) & 0x1)
+		    == SCM_PENG_ENGAGED)
+			return TRUE;
+	}
+	return FALSE;
+}
+
+/*****************************************************************************/
+/* fn scc_wait_completion()                                                  */
+/*****************************************************************************/
+/**
+ * Poll looking for end-of-cipher indication. Only used
+ * if @c SCC_SCM_SLEEP is not defined.
+ *
+ * @internal
+ *
+ * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all
+ * the way up to five sets of spins for 1024 bytes.  (8- and 16-byte functions
+ * are done when we first look.  Zeroizing takes one pass around.
+ *
+ * @param   scm_status      Address of the SCM_STATUS register
+ *
+ * @return  A return code of type #scc_return_t
+ */
+static scc_return_t scc_wait_completion(uint32_t * scm_status)
+{
+	scc_return_t ret;
+	int done;
+	int i = 0;
+
+	/* check for completion by polling */
+	do {
+		done = is_cipher_done(scm_status);
+		if (done)
+			break;
+		/* TODO: shorten this delay */
+		udelay(1000);
+	} while (i++ < SCC_CIPHER_MAX_POLL_COUNT);
+
+	pr_debug("SCC2: Polled DONE %d times\n", i);
+	if (!done) {
+		ret = SCC_RET_FAIL;
+	}
+
+	return ret;
+}				/* scc_wait_completion() */
+
+/*****************************************************************************/
+/* fn is_cipher_done()                                                       */
+/*****************************************************************************/
+/**
+ * This function returns non-zero if SCM Status register indicates
+ * that a cipher has terminated or some other interrupt-generating
+ * condition has occurred.
+ *
+ * @param scm_status    Address of the SCM STATUS register
+ *
+ * @return  0 if cipher operations are finished
+ */
+static int is_cipher_done(uint32_t * scm_status)
+{
+	register unsigned status;
+	register int cipher_done;
+
+	*scm_status = SCC_READ_REGISTER(SCM_STATUS_REG);
+	status = (*scm_status & SCM_STATUS_SRS_MASK) >> SCM_STATUS_SRS_SHIFT;
+
+	/*
+	 * Done when SCM is not in 'currently performing a function' states.
+	 */
+	cipher_done = ((status != SCM_STATUS_SRS_ZBUSY)
+		       && (status != SCM_STATUS_SRS_CBUSY)
+		       && (status != SCM_STATUS_SRS_ABUSY));
+
+	return cipher_done;
+}				/* is_cipher_done() */
+
+/*****************************************************************************/
+/* fn offset_within_smn()                                                    */
+/*****************************************************************************/
+/*!
+ *  Check that the offset is with the bounds of the SMN register set.
+ *
+ *  @param[in]  register_offset    register offset of SMN.
+ *
+ *  @return   1 if true, 0 if false (not within SMN)
+ */
+static inline int offset_within_smn(uint32_t register_offset)
+{
+	return ((register_offset >= SMN_STATUS_REG)
+		&& (register_offset <= SMN_HAC_REG));
+}
+
+/*****************************************************************************/
+/* fn offset_within_scm()                                                    */
+/*****************************************************************************/
+/*!
+ *  Check that the offset is with the bounds of the SCM register set.
+ *
+ *  @param[in]  register_offset    Register offset of SCM
+ *
+ *  @return   1 if true, 0 if false (not within SCM)
+ */
+static inline int offset_within_scm(uint32_t register_offset)
+{
+	return 1;		/* (register_offset >= SCM_RED_START)
+				   && (register_offset < scm_highest_memory_address); */
+/* Although this would cause trouble for zeroize testing, this change would
+ * close a security hole which currently allows any kernel program to access
+ * any location in RED RAM.  Perhaps enforce in non-SCC_DEBUG compiles?
+ && (register_offset <= SCM_INIT_VECTOR_1); */
+}
+
+/*****************************************************************************/
+/* fn check_register_accessible()                                            */
+/*****************************************************************************/
+/**
+ *  Given the current SCM and SMN status, verify that access to the requested
+ *  register should be OK.
+ *
+ *  @param[in]   register_offset  register offset within SCC
+ *  @param[in]   smn_status  recent value from #SMN_STATUS_REG
+ *  @param[in]   scm_status  recent value from #SCM_STATUS_REG
+ *
+ *  @return   #SCC_RET_OK if ok, #SCC_RET_FAIL if not
+ */
+static scc_return_t
+check_register_accessible(uint32_t register_offset, uint32_t smn_status,
+			  uint32_t scm_status)
+{
+	int error_code = SCC_RET_FAIL;
+
+	/* Verify that the register offset passed in is not among the verboten set
+	 * if the SMN is in Fail mode.
+	 */
+	if (offset_within_smn(register_offset)) {
+		if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) {
+			if (!((register_offset == SMN_STATUS_REG) ||
+			      (register_offset == SMN_COMMAND_REG) ||
+			      (register_offset == SMN_SEC_VIO_REG))) {
+				pr_debug
+				    ("SCC2 Driver: Note: Security State is in FAIL state.\n");
+			} /* register not a safe one */
+			else {
+				/* SMN is in  FAIL, but register is a safe one */
+				error_code = SCC_RET_OK;
+			}
+		} /* State is FAIL */
+		else {
+			/* State is not fail.  All registers accessible. */
+			error_code = SCC_RET_OK;
+		}
+	}
+	/* offset within SMN */
+	/*  Not SCM register.  Check for SCM busy. */
+	else if (offset_within_scm(register_offset)) {
+		/* This is the 'cannot access' condition in the SCM */
+		if (0		/* (scm_status & SCM_STATUS_BUSY) */
+		    /* these are always available  - rest fail on busy */
+		    && !((register_offset == SCM_STATUS_REG) ||
+			 (register_offset == SCM_ERR_STATUS_REG) ||
+			 (register_offset == SCM_INT_CTL_REG) ||
+			 (register_offset == SCM_VERSION_REG))) {
+			pr_debug
+			    ("SCC2 Driver: Note: Secure Memory is in BUSY state.\n");
+		} /* status is busy & register inaccessible */
+		else {
+			error_code = SCC_RET_OK;
+		}
+	}
+	/* offset within SCM */
+	return error_code;
+
+}				/* check_register_accessible() */
+
+/*****************************************************************************/
+/* fn check_register_offset()                                                */
+/*****************************************************************************/
+/**
+ *  Check that the offset is with the bounds of the SCC register set.
+ *
+ *  @param[in]  register_offset    register offset of SMN.
+ *
+ * #SCC_RET_OK if ok, #SCC_RET_FAIL if not
+ */
+static scc_return_t check_register_offset(uint32_t register_offset)
+{
+	int return_value = SCC_RET_FAIL;
+
+	/* Is it valid word offset ? */
+	if (SCC_BYTE_OFFSET(register_offset) == 0) {
+		/* Yes. Is register within SCM? */
+		if (offset_within_scm(register_offset)) {
+			return_value = SCC_RET_OK;	/* yes, all ok */
+		}
+		/* Not in SCM.  Now look within the SMN */
+		else if (offset_within_smn(register_offset)) {
+			return_value = SCC_RET_OK;	/* yes, all ok */
+		}
+	}
+
+	return return_value;
+}
+
+#ifdef SCC_REGISTER_DEBUG
+
+/**
+ * Names of the SCC Registers, indexed by register number
+ */
+static char *scc_regnames[] = {
+	"SCM_VERSION_REG",
+	"0x04",
+	"SCM_INT_CTL_REG",
+	"SCM_STATUS_REG",
+	"SCM_ERR_STATUS_REG",
+	"SCM_FAULT_ADR_REG",
+	"SCM_PART_OWNERS_REG",
+	"SCM_PART_ENGAGED_REG",
+	"SCM_UNIQUE_ID0_REG",
+	"SCM_UNIQUE_ID1_REG",
+	"SCM_UNIQUE_ID2_REG",
+	"SCM_UNIQUE_ID3_REG",
+	"0x30",
+	"0x34",
+	"0x38",
+	"0x3C",
+	"0x40",
+	"0x44",
+	"0x48",
+	"0x4C",
+	"SCM_ZCMD_REG",
+	"SCM_CCMD_REG",
+	"SCM_C_BLACK_ST_REG",
+	"SCM_DBG_STATUS_REG",
+	"SCM_AES_CBC_IV0_REG",
+	"SCM_AES_CBC_IV1_REG",
+	"SCM_AES_CBC_IV2_REG",
+	"SCM_AES_CBC_IV3_REG",
+	"0x70",
+	"0x74",
+	"0x78",
+	"0x7C",
+	"SCM_SMID0_REG",
+	"SCM_ACC0_REG",
+	"SCM_SMID1_REG",
+	"SCM_ACC1_REG",
+	"SCM_SMID2_REG",
+	"SCM_ACC2_REG",
+	"SCM_SMID3_REG",
+	"SCM_ACC3_REG",
+	"SCM_SMID4_REG",
+	"SCM_ACC4_REG",
+	"SCM_SMID5_REG",
+	"SCM_ACC5_REG",
+	"SCM_SMID6_REG",
+	"SCM_ACC6_REG",
+	"SCM_SMID7_REG",
+	"SCM_ACC7_REG",
+	"SCM_SMID8_REG",
+	"SCM_ACC8_REG",
+	"SCM_SMID9_REG",
+	"SCM_ACC9_REG",
+	"SCM_SMID10_REG",
+	"SCM_ACC10_REG",
+	"SCM_SMID11_REG",
+	"SCM_ACC11_REG",
+	"SCM_SMID12_REG",
+	"SCM_ACC12_REG",
+	"SCM_SMID13_REG",
+	"SCM_ACC13_REG",
+	"SCM_SMID14_REG",
+	"SCM_ACC14_REG",
+	"SCM_SMID15_REG",
+	"SCM_ACC15_REG",
+	"SMN_STATUS_REG",
+	"SMN_COMMAND_REG",
+	"SMN_SEQ_START_REG",
+	"SMN_SEQ_END_REG",
+	"SMN_SEQ_CHECK_REG",
+	"SMN_BB_CNT_REG",
+	"SMN_BB_INC_REG",
+	"SMN_BB_DEC_REG",
+	"SMN_COMPARE_REG",
+	"SMN_PT_CHK_REG",
+	"SMN_CT_CHK_REG",
+	"SMN_TIMER_IV_REG",
+	"SMN_TIMER_CTL_REG",
+	"SMN_SEC_VIO_REG",
+	"SMN_TIMER_REG",
+	"SMN_HAC_REG"
+};
+
+/**
+ * Names of the Secure RAM States
+ */
+static char *srs_names[] = {
+	"SRS_Reset",
+	"SRS_All_Ready",
+	"SRS_ZeroizeBusy",
+	"SRS_CipherBusy",
+	"SRS_AllBusy",
+	"SRS_ZeroizeDoneCipherReady",
+	"SRS_CipherDoneZeroizeReady",
+	"SRS_ZeroizeDoneCipherBusy",
+	"SRS_CipherDoneZeroizeBusy",
+	"SRS_UNKNOWN_STATE_9",
+	"SRS_TransitionalA",
+	"SRS_TransitionalB",
+	"SRS_TransitionalC",
+	"SRS_TransitionalD",
+	"SRS_AllDone",
+	"SRS_UNKNOWN_STATE_E",
+	"SRS_FAIL"
+};
+
+/**
+ * Create a text interpretation of the SCM Version Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_version_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	snprintf(print_buffer, buf_size,
+		 "Bpp: %u, Bpcb: %u, np: %u, maj: %u, min: %u",
+		 (value & SCM_VER_BPP_MASK) >> SCM_VER_BPP_SHIFT,
+		 ((value & SCM_VER_BPCB_MASK) >> SCM_VER_BPCB_SHIFT) + 1,
+		 ((value & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT) + 1,
+		 (value & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT,
+		 (value & SCM_VER_MIN_MASK) >> SCM_VER_MIN_SHIFT);
+
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of the SCM Status Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_status_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+
+	snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s",
+		 (value & SCM_STATUS_KST_DEFAULT_KEY) ? "KST_DefaultKey " : "",
+		 /* reserved */
+		 (value & SCM_STATUS_KST_WRONG_KEY) ? "KST_WrongKey " : "",
+		 (value & SCM_STATUS_KST_BAD_KEY) ? "KST_BadKey " : "",
+		 (value & SCM_STATUS_ERR) ? "Error " : "",
+		 (value & SCM_STATUS_MSS_FAIL) ? "MSS_FailState " : "",
+		 (value & SCM_STATUS_MSS_SEC) ? "MSS_SecureState " : "",
+		 (value & SCM_STATUS_RSS_FAIL) ? "RSS_FailState " : "",
+		 (value & SCM_STATUS_RSS_SEC) ? "RSS_SecureState " : "",
+		 (value & SCM_STATUS_RSS_INIT) ? "RSS_Initializing " : "",
+		 (value & SCM_STATUS_UNV) ? "UID_Invalid " : "",
+		 (value & SCM_STATUS_BIG) ? "BigEndian " : "",
+		 (value & SCM_STATUS_USK) ? "SecretKey " : "",
+		 srs_names[(value & SCM_STATUS_SRS_MASK) >>
+			   SCM_STATUS_SRS_SHIFT]);
+
+	return print_buffer;
+}
+
+/**
+ * Names of the SCM Error Codes
+ */
+static
+char *scm_err_code[] = {
+	"Unknown_0",
+	"UnknownAddress",
+	"UnknownCommand",
+	"ReadPermErr",
+	"WritePermErr",
+	"DMAErr",
+	"EncBlockLenOvfl",
+	"KeyNotEngaged",
+	"ZeroizeCmdQOvfl",
+	"CipherCmdQOvfl",
+	"ProcessIntr",
+	"WrongKey",
+	"DeviceBusy",
+	"DMAUnalignedAddr",
+	"Unknown_E",
+	"Unknown_F",
+};
+
+/**
+ * Names of the SMN States
+ */
+static char *smn_state_name[] = {
+	"Start",
+	"Invalid_01",
+	"Invalid_02",
+	"Invalid_03",
+	"Zeroizing_04",
+	"Zeroizing",
+	"HealthCheck",
+	"HealthCheck_07",
+	"Invalid_08",
+	"Fail",
+	"Secure",
+	"Invalid_0B",
+	"NonSecure",
+	"Invalid_0D",
+	"Invalid_0E",
+	"Invalid_0F",
+	"Invalid_10",
+	"Invalid_11",
+	"Invalid_12",
+	"Invalid_13",
+	"Invalid_14",
+	"Invalid_15",
+	"Invalid_16",
+	"Invalid_17",
+	"Invalid_18",
+	"FailHard",
+	"Invalid_1A",
+	"Invalid_1B",
+	"Invalid_1C",
+	"Invalid_1D",
+	"Invalid_1E",
+	"Invalid_1F"
+};
+
+/**
+ * Create a text interpretation of the SCM Error Status Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_err_status_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	snprintf(print_buffer, buf_size,
+		 "MID: 0x%x, %s%s ErrorCode: %s, SMSState: %s, SCMState: %s",
+		 (value & SCM_ERRSTAT_MID_MASK) >> SCM_ERRSTAT_MID_SHIFT,
+		 (value & SCM_ERRSTAT_ILM) ? "ILM, " : "",
+		 (value & SCM_ERRSTAT_SUP) ? "SUP, " : "",
+		 scm_err_code[(value & SCM_ERRSTAT_ERC_MASK) >>
+			      SCM_ERRSTAT_ERC_SHIFT],
+		 smn_state_name[(value & SCM_ERRSTAT_SMS_MASK) >>
+				SCM_ERRSTAT_SMS_SHIFT],
+		 srs_names[(value & SCM_ERRSTAT_SRS_MASK) >>
+			   SCM_ERRSTAT_SRS_SHIFT]);
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of the SCM Zeroize Command Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_zcmd_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	unsigned cmd = (value & SCM_ZCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT;
+
+	snprintf(print_buffer, buf_size, "%s %u",
+		 (cmd ==
+		  ZCMD_DEALLOC_PART) ? "DeallocPartition" :
+		 "(unknown function)",
+		 (value & SCM_ZCMD_PART_MASK) >> SCM_ZCMD_PART_SHIFT);
+
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of the SCM Cipher Command Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_ccmd_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	unsigned cmd = (value & SCM_CCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT;
+
+	snprintf(print_buffer, buf_size,
+		 "%s %u bytes, %s offset 0x%x, in partition %u",
+		 (cmd == SCM_CCMD_AES_DEC_ECB) ? "ECB Decrypt" : (cmd ==
+								  SCM_CCMD_AES_ENC_ECB)
+		 ? "ECB Encrypt" : (cmd ==
+				    SCM_CCMD_AES_DEC_CBC) ? "CBC Decrypt" : (cmd
+									     ==
+									     SCM_CCMD_AES_ENC_CBC)
+		 ? "CBC Encrypt" : "(unknown function)",
+		 16 +
+		 16 * ((value & SCM_CCMD_LENGTH_MASK) >> SCM_CCMD_LENGTH_SHIFT),
+		 ((cmd == SCM_CCMD_AES_ENC_CBC)
+		  || (cmd == SCM_CCMD_AES_ENC_ECB)) ? "at" : "to",
+		 16 * ((value & SCM_CCMD_OFFSET_MASK) >> SCM_CCMD_OFFSET_SHIFT),
+		 (value & SCM_CCMD_PART_MASK) >> SCM_CCMD_PART_SHIFT);
+
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of an SCM Access Permissions Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_acc_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s",
+		 (value & SCM_PERM_NO_ZEROIZE) ? "NO_ZERO " : "",
+		 (value & SCM_PERM_HD_SUP_DISABLE) ? "SUP_DIS " : "",
+		 (value & SCM_PERM_HD_READ) ? "HD_RD " : "",
+		 (value & SCM_PERM_HD_WRITE) ? "HD_WR " : "",
+		 (value & SCM_PERM_HD_EXECUTE) ? "HD_EX " : "",
+		 (value & SCM_PERM_TH_READ) ? "TH_RD " : "",
+		 (value & SCM_PERM_TH_WRITE) ? "TH_WR " : "",
+		 (value & SCM_PERM_OT_READ) ? "OT_RD " : "",
+		 (value & SCM_PERM_OT_WRITE) ? "OT_WR " : "",
+		 (value & SCM_PERM_OT_EXECUTE) ? "OT_EX" : "");
+
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of the SCM Partitions Engaged Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *scm_print_part_eng_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+		 (value & 0x8000) ? "15 " : "",
+		 (value & 0x4000) ? "14 " : "",
+		 (value & 0x2000) ? "13 " : "",
+		 (value & 0x1000) ? "12 " : "",
+		 (value & 0x0800) ? "11 " : "",
+		 (value & 0x0400) ? "10 " : "",
+		 (value & 0x0200) ? "9 " : "",
+		 (value & 0x0100) ? "8 " : "",
+		 (value & 0x0080) ? "7 " : "",
+		 (value & 0x0040) ? "6 " : "",
+		 (value & 0x0020) ? "5 " : "",
+		 (value & 0x0010) ? "4 " : "",
+		 (value & 0x0008) ? "3 " : "",
+		 (value & 0x0004) ? "2 " : "",
+		 (value & 0x0002) ? "1 " : "", (value & 0x0001) ? "0" : "");
+
+	return print_buffer;
+}
+
+/**
+ * Create a text interpretation of the SMN Status Register
+ *
+ * @param      value        The value of the register
+ * @param[out] print_buffer Place to store the interpretation
+ * @param      buf_size     Number of bytes available at print_buffer
+ *
+ * @return The print_buffer
+ */
+static
+char *smn_print_status_reg(uint32_t value, char *print_buffer, int buf_size)
+{
+	snprintf(print_buffer, buf_size,
+		 "Version %d %s%s%s%s%s%s%s%s%s%s%s%s%s",
+		 (value & SMN_STATUS_VERSION_ID_MASK) >>
+		 SMN_STATUS_VERSION_ID_SHIFT,
+		 (value & SMN_STATUS_ILLEGAL_MASTER) ? "IllMaster " : "",
+		 (value & SMN_STATUS_SCAN_EXIT) ? "ScanExit " : "",
+		 (value & SMN_STATUS_PERIP_INIT) ? "PeripInit " : "",
+		 (value & SMN_STATUS_SMN_ERROR) ? "SMNError " : "",
+		 (value & SMN_STATUS_SOFTWARE_ALARM) ? "SWAlarm " : "",
+		 (value & SMN_STATUS_TIMER_ERROR) ? "TimerErr " : "",
+		 (value & SMN_STATUS_PC_ERROR) ? "PTCTErr " : "",
+		 (value & SMN_STATUS_BITBANK_ERROR) ? "BitbankErr " : "",
+		 (value & SMN_STATUS_ASC_ERROR) ? "ASCErr " : "",
+		 (value & SMN_STATUS_SECURITY_POLICY_ERROR) ? "SecPlcyErr " :
+		 "",
+		 (value & SMN_STATUS_SEC_VIO_ACTIVE_ERROR) ? "SecVioAct " : "",
+		 (value & SMN_STATUS_INTERNAL_BOOT) ? "IntBoot " : "",
+		 smn_state_name[(value & SMN_STATUS_STATE_MASK) >>
+				SMN_STATUS_STATE_SHIFT]);
+
+	return print_buffer;
+}
+
+/**
+ * The array, indexed by register number (byte-offset / 4), of print routines
+ * for the SCC (SCM and SMN) registers.
+ */
+static reg_print_routine_t reg_printers[] = {
+	scm_print_version_reg,
+	NULL,			/* 0x04 */
+	NULL,			/* SCM_INT_CTL_REG */
+	scm_print_status_reg,
+	scm_print_err_status_reg,
+	NULL,			/* SCM_FAULT_ADR_REG */
+	NULL,			/* SCM_PART_OWNERS_REG */
+	scm_print_part_eng_reg,
+	NULL,			/* SCM_UNIQUE_ID0_REG */
+	NULL,			/* SCM_UNIQUE_ID1_REG */
+	NULL,			/* SCM_UNIQUE_ID2_REG */
+	NULL,			/* SCM_UNIQUE_ID3_REG */
+	NULL,			/* 0x30 */
+	NULL,			/* 0x34 */
+	NULL,			/* 0x38 */
+	NULL,			/* 0x3C */
+	NULL,			/* 0x40 */
+	NULL,			/* 0x44 */
+	NULL,			/* 0x48 */
+	NULL,			/* 0x4C */
+	scm_print_zcmd_reg,
+	scm_print_ccmd_reg,
+	NULL,			/* SCM_C_BLACK_ST_REG */
+	NULL,			/* SCM_DBG_STATUS_REG */
+	NULL,			/* SCM_AES_CBC_IV0_REG */
+	NULL,			/* SCM_AES_CBC_IV1_REG */
+	NULL,			/* SCM_AES_CBC_IV2_REG */
+	NULL,			/* SCM_AES_CBC_IV3_REG */
+	NULL,			/* 0x70 */
+	NULL,			/* 0x74 */
+	NULL,			/* 0x78 */
+	NULL,			/* 0x7C */
+	NULL,			/* SCM_SMID0_REG */
+	scm_print_acc_reg,	/* ACC0 */
+	NULL,			/* SCM_SMID1_REG */
+	scm_print_acc_reg,	/* ACC1 */
+	NULL,			/* SCM_SMID2_REG */
+	scm_print_acc_reg,	/* ACC2 */
+	NULL,			/* SCM_SMID3_REG */
+	scm_print_acc_reg,	/* ACC3 */
+	NULL,			/* SCM_SMID4_REG */
+	scm_print_acc_reg,	/* ACC4 */
+	NULL,			/* SCM_SMID5_REG */
+	scm_print_acc_reg,	/* ACC5 */
+	NULL,			/* SCM_SMID6_REG */
+	scm_print_acc_reg,	/* ACC6 */
+	NULL,			/* SCM_SMID7_REG */
+	scm_print_acc_reg,	/* ACC7 */
+	NULL,			/* SCM_SMID8_REG */
+	scm_print_acc_reg,	/* ACC8 */
+	NULL,			/* SCM_SMID9_REG */
+	scm_print_acc_reg,	/* ACC9 */
+	NULL,			/* SCM_SMID10_REG */
+	scm_print_acc_reg,	/* ACC10 */
+	NULL,			/* SCM_SMID11_REG */
+	scm_print_acc_reg,	/* ACC11 */
+	NULL,			/* SCM_SMID12_REG */
+	scm_print_acc_reg,	/* ACC12 */
+	NULL,			/* SCM_SMID13_REG */
+	scm_print_acc_reg,	/* ACC13 */
+	NULL,			/* SCM_SMID14_REG */
+	scm_print_acc_reg,	/* ACC14 */
+	NULL,			/* SCM_SMID15_REG */
+	scm_print_acc_reg,	/* ACC15 */
+	smn_print_status_reg,
+	NULL,			/* SMN_COMMAND_REG */
+	NULL,			/* SMN_SEQ_START_REG */
+	NULL,			/* SMN_SEQ_END_REG */
+	NULL,			/* SMN_SEQ_CHECK_REG */
+	NULL,			/* SMN_BB_CNT_REG */
+	NULL,			/* SMN_BB_INC_REG */
+	NULL,			/* SMN_BB_DEC_REG */
+	NULL,			/* SMN_COMPARE_REG */
+	NULL,			/* SMN_PT_CHK_REG */
+	NULL,			/* SMN_CT_CHK_REG */
+	NULL,			/* SMN_TIMER_IV_REG */
+	NULL,			/* SMN_TIMER_CTL_REG */
+	NULL,			/* SMN_SEC_VIO_REG */
+	NULL,			/* SMN_TIMER_REG */
+	NULL,			/* SMN_HAC_REG */
+};
+
+/*****************************************************************************/
+/* fn dbg_scc_read_register()                                                */
+/*****************************************************************************/
+/**
+ * Noisily read a 32-bit value to an SCC register.
+ * @param offset        The address of the register to read.
+ *
+ * @return  The register value
+ * */
+uint32_t dbg_scc_read_register(uint32_t offset)
+{
+	uint32_t value;
+	char *regname = scc_regnames[offset / 4];
+
+	value = __raw_readl(scc_base + offset);
+	pr_debug("SCC2 RD: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname,
+		 reg_printers[offset / 4]
+		 ? reg_printers[offset / 4] (value, reg_print_buffer,
+					     REG_PRINT_BUFFER_SIZE)
+		 : "");
+
+	return value;
+}
+
+/*****************************************************************************/
+/* fn dbg_scc_write_register()                                               */
+/*****************************************************************************/
+/*
+ * Noisily read a 32-bit value to an SCC register.
+ * @param offset        The address of the register to written.
+ *
+ * @param value         The new register value
+ */
+void dbg_scc_write_register(uint32_t offset, uint32_t value)
+{
+	char *regname = scc_regnames[offset / 4];
+
+	pr_debug("SCC2 WR: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname,
+		 reg_printers[offset / 4]
+		 ? reg_printers[offset / 4] (value, reg_print_buffer,
+					     REG_PRINT_BUFFER_SIZE)
+		 : "");
+	(void)__raw_writel(value, scc_base + offset);
+
+}
+
+#endif				/* SCC_REGISTER_DEBUG */
+
+static int scc_dev_probe(struct platform_device *pdev)
+{
+	struct resource *r;
+	int ret = 0;
+
+	/* get the scc registers base address */
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IORESOURCE_MEM (0)\n");
+		ret = -ENXIO;
+		goto exit;
+	}
+
+	scc_phys_base = r->start;
+
+
+	/* get the scc ram base address */
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!r) {
+		dev_err(&pdev->dev, "can't get IORESOURCE_MEM (1)\n");
+		ret = -ENXIO;
+		goto exit;
+	}
+
+	scm_ram_phys_base = r->start;
+
+	/* now initialize the SCC */
+	ret = scc_init();
+
+exit:
+	return ret;
+}
+
+static int scc_dev_remove(struct platform_device *pdev)
+{
+	scc_cleanup();
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int scc_suspend(struct platform_device *pdev,
+		pm_message_t state)
+{
+	return 0;
+}
+
+static int scc_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define scc_suspend	NULL
+#define	scc_resume	NULL
+#endif
+
+/*! Linux Driver definition
+ *
+ */
+static struct platform_driver mxcscc_driver = {
+	.driver = {
+		   .name = SCC_DRIVER_NAME,
+		   },
+	.probe = scc_dev_probe,
+	.remove = scc_dev_remove,
+	.suspend = scc_suspend,
+	.resume = scc_resume,
+};
+
+static int __init scc_driver_init(void)
+{
+	return platform_driver_register(&mxcscc_driver);
+}
+
+module_init(scc_driver_init);
+
+static void __exit scc_driver_exit(void)
+{
+	platform_driver_unregister(&mxcscc_driver);
+}
+
+module_exit(scc_driver_exit);
diff --git a/drivers/mxc/security/scc2_internals.h b/drivers/mxc/security/scc2_internals.h
new file mode 100644
index 000000000000..1c047de0082e
--- /dev/null
+++ b/drivers/mxc/security/scc2_internals.h
@@ -0,0 +1,519 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef SCC_INTERNALS_H
+#define SCC_INTERNALS_H
+
+/** @file scc2_internals.h
+ *
+ * @brief This is intended to be the file which contains most or all of the
+ * code or changes need to port the driver.  It also includes other definitions
+ * needed by the driver.
+ *
+ *  This header file should only ever be included by scc2_driver.c
+ *
+ *  Compile-time flags minimally needed:
+ *
+ *  @li Some sort of platform flag.  Currently TAHITI and MXC are understood.
+ *  @li Some start-of-SCC consideration, such as SCC_BASE_ADDR
+ *
+ *  Some changes which could be made when porting this driver:
+ *  #SCC_SPIN_COUNT
+ *
+ */
+
+#include <linux/version.h>          /* Current version Linux kernel */
+#include <linux/module.h>           /* Basic support for loadable modules,
+                                       printk */
+#include <linux/init.h>             /* module_init, module_exit */
+#include <linux/kernel.h>           /* General kernel system calls */
+#include <linux/sched.h>            /* for interrupt.h */
+#include <linux/spinlock.h>
+
+#include <linux/io.h>               /* ioremap() */
+#include <linux/interrupt.h>        /* IRQ / interrupt definitions */
+
+
+#include <linux/mxc_scc2_driver.h>
+
+#if defined(MXC)
+
+#include <mach/iim.h>
+#include <mach/mxc_scc.h>
+
+
+/**
+ * This macro is used to determine whether the SCC is enabled/available
+ * on the platform.  This macro may need to be ported.
+ */
+#define SCC_FUSE __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMHWV1))
+#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0)
+
+#else  /* neither TAHITI nor MXC */
+
+#error Do not understand target architecture
+
+#endif /* TAHITI */
+/**
+ * Define the number of Stored Keys which the SCC driver will make available.
+ * Value shall be from 0 to 20.  Default is zero (0).
+ */
+/*#define SCC_KEY_SLOTS   20*/
+
+
+/* Temporarily define compile-time flags to make Doxygen happy. */
+#ifdef DOXYGEN_HACK
+/** @addtogroup scccompileflags */
+/** @{ */
+
+
+/** @def NO_SMN_INTERRUPT
+ * The SMN interrupt is not wired to the CPU at all.
+ */
+#define NO_SMN_INTERRUPT
+
+
+/**
+ * Register an interrupt handler for the SMN as well as
+ * the SCM.  In some implementations, the SMN is not connected at all (see
+ * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the
+ * SCM.  When defining this flag, the SMN interrupt should be on a separate
+ * line from the SCM interrupt.
+ */
+
+#define USE_SMN_INTERRUPT
+
+
+/**
+ * Turn on generation of run-time operational, debug, and error messages
+ */
+#define SCC_DEBUG
+
+
+/**
+ * Turn on generation of run-time logging of access to the SCM and SMN
+ * registers.
+ */
+#define SCC_REGISTER_DEBUG
+
+
+/**
+ * Turn on generation of run-time logging of access to the SCM Red and
+ * Black memories.  Will only work if #SCC_REGISTER_DEBUG is also defined.
+ */
+#define SCC_RAM_DEBUG
+
+
+/**
+ *  If the driver finds the SCC in HEALTH_CHECK state, go ahead and
+ *  run a quick ASC to bring it to SECURE state.
+ */
+#define SCC_BRINGUP
+
+
+/**
+ * Expected to come from platform header files or compile command line.
+ * This symbol must be the address of the SCC
+ */
+#define SCC_BASE
+
+/**
+ *  This must be the interrupt line number of the SCM interrupt.
+ */
+#define INT_SCM
+
+/**
+ *  if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of
+ *  the SMN interrupt.
+ */
+#define INT_SMN
+
+/**
+ * Define the number of Stored Keys which the SCC driver will make available.
+ * Value shall be from 0 to 20.  Default is zero (0).
+ */
+#define SCC_KEY_SLOTS
+
+/**
+ * Make sure that this flag is defined if compiling for a Little-Endian
+ * platform.  Linux Kernel builds provide this flag.
+ */
+#define __LITTLE_ENDIAN
+
+/**
+ * Make sure that this flag is defined if compiling for a Big-Endian platform.
+ * Linux Kernel builds provide this flag.
+ */
+#define __BIG_ENDIAN
+
+/**
+ * Read a 32-bit register value from a 'peripheral'.  Standard Linux/Unix
+ * macro.
+ *
+ * @param offset   Bus address of register to be read
+ *
+ * @return The value of the register
+ */
+#define readl(offset)
+
+
+/**
+ * Write a 32-bit value to a register in a 'peripheral'.  Standard Linux/Unix
+ * macro.
+ *
+ * @param value    The 32-bit value to store
+ * @param offset   Bus address of register to be written
+ *
+ * return (none)
+ */
+#define writel(value,offset)
+
+
+/** @} */  /* end group scccompileflags */
+
+#endif  /* DOXYGEN_HACK */
+
+
+#ifndef SCC_KEY_SLOTS
+#define SCC_KEY_SLOTS 0
+
+#else
+
+#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20)
+#error Bad value for SCC_KEY_SLOTS
+#endif
+
+#endif
+
+
+/**
+ * Maximum length of key/secret value which can be stored in SCC.
+ */
+#define SCC_MAX_KEY_SIZE 256
+
+
+/**
+ * This is the size, in bytes, of each key slot, and therefore the maximum size
+ * of the wrapped key.
+ */
+#define SCC_KEY_SLOT_SIZE 32
+
+
+/* These come for free with Linux, but may need to be set in a port. */
+#ifndef __BIG_ENDIAN
+#ifndef __LITTLE_ENDIAN
+#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined
+#endif
+#else
+#ifdef __LITTLE_ENDIAN
+#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined
+#endif
+#endif
+
+
+#ifndef SCC_CALLBACK_SIZE
+/** The number of function pointers which can be stored in #scc_callbacks.
+ *  Defaults to 4, can be overridden with compile-line argument.
+ */
+#define SCC_CALLBACK_SIZE 4
+#endif
+
+
+/** Initial CRC value for CCITT-CRC calculation. */
+#define CRC_CCITT_START 0xFFFF
+
+
+#ifdef TAHITI
+
+/**
+ * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of
+ * registers are swapped in place.
+ */
+#define SCC_BASE       SMN_BASE_ADDR
+
+
+/** The interrupt number for the SCC (SCM only!) on Tahiti */
+#define INT_SCC_SCM       62
+
+
+/** Tahiti does not have the SMN interrupt wired to the CPU.  */
+#define NO_SMN_INTERRUPT
+
+
+#endif /* TAHITI */
+
+
+/** Number of times to spin between polling of SCC while waiting for cipher
+ *  or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */
+#define SCC_SPIN_COUNT 1000
+
+
+/** Number of times to polling SCC while waiting for cipher
+ *  or zeroizing function to complete.  See also #SCC_SPIN_COUNT.  */
+#define SCC_CIPHER_MAX_POLL_COUNT 100
+
+
+/**
+ * @def SCC_READ_REGISTER
+ * Read a 32-bit value from an SCC register.  Macro which depends upon
+ * #scc_base.  Linux readl()/writel() macros operate on 32-bit quantities, as
+ * do SCC register reads/writes.
+ *
+ * @param     offset  Register offset within SCC.
+ *
+ * @return    The value from the SCC's register.
+ */
+#ifndef SCC_REGISTER_DEBUG
+#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset))
+#else
+#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset)
+#endif
+
+
+/**
+ * Write a 32-bit value to an SCC register.  Macro depends upon #scc_base.
+ * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC
+ * register reads/writes.
+ *
+ * @param   offset  Register offset within SCC.
+ * @param   value   32-bit value to store into the register
+ *
+ * @return   (void)
+ */
+#ifndef SCC_REGISTER_DEBUG
+#define SCC_WRITE_REGISTER(offset,value) \
+	(void)__raw_writel(value, scc_base+(offset))
+#else
+#define SCC_WRITE_REGISTER(offset,value) \
+	dbg_scc_write_register(offset, value)
+#endif
+
+/**
+ * Calculate the kernel virtual address of a partition from the partition number.
+ */
+#define SCM_PART_ADDRESS(part)                                          \
+ (scm_ram_base + (part*scc_configuration.partition_size_bytes))
+
+/**
+ * Calculate the partition number from the kernel virtual address.
+ */
+#define SCM_PART_NUMBER(address)                                        \
+ ((address - (uint32_t)scm_ram_base)/scc_configuration.partition_size_bytes)
+
+/**
+ * Calculates the byte offset into a word
+ *  @param   bp  The byte (char*) pointer
+ *  @return      The offset (0, 1, 2, or 3)
+ */
+#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t))
+
+
+/**
+ * Converts (by rounding down) a byte pointer into a word pointer
+ *  @param  bp  The byte (char*) pointer
+ *  @return     The word (uint32_t) as though it were an aligned (uint32_t*)
+ */
+#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1))
+
+
+/**
+ * Determine number of bytes in an SCC block
+ *
+ * @return Bytes / block
+ */
+#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes
+
+
+/**
+ * Maximum number of additional bytes which may be added in CRC+padding mode.
+ */
+#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding))
+
+/**
+ *  Shorthand (clearer, anyway) for number of bytes in a CRC.
+ */
+#define CRC_SIZE_BYTES (sizeof(crc_t))
+
+/**
+ * The polynomial used in CCITT-CRC calculation
+ */
+#define CRC_POLYNOMIAL 0x1021
+
+/**
+ * Calculate CRC on one byte of data
+ *
+ * @param[in,out] running_crc  A value of type crc_t where CRC is kept. This
+ *                             must be an rvalue and an lvalue.
+ * @param[in]     byte_value   The byte (uint8_t, char) to be put in the CRC
+ *
+ * @return      none
+ */
+#define CALC_CRC(byte_value,running_crc)  {                                  \
+    uint8_t data;                                                            \
+    data = (0xff&(byte_value)) ^ (running_crc >> 8);                         \
+    running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8);           \
+}
+
+/** Value of 'beginning of padding' marker in driver-provided padding */
+#define SCC_DRIVER_PAD_CHAR  0x80
+
+
+/** Name of the driver.  Used (on Linux, anyway) when registering interrupts */
+#define SCC_DRIVER_NAME "mxc_scc"
+
+
+/* Port -- these symbols are defined in Linux 2.6 and later.  They are defined
+ * here for backwards compatibility because this started life as a 2.4
+ * driver, and as a guide to portation to other platforms.
+ */
+
+#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+
+#define irqreturn_t void        /* Return type of an interrupt handler */
+
+#define IRQ_HANDLED /* Would be '1' for handled -- as in return IRQ_HANDLED; */
+
+#define IRQ_NONE   /* would be '0' for not handled -- as in return IRQ_NONE; */
+
+#define IRQ_RETVAL(x) /* Return x==0 (not handled) or non-zero (handled) */
+
+#endif /* LINUX earlier than 2.5 */
+
+
+/* These are nice to have around */
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+
+/** Provide a typedef for the CRC which can be used in encrypt/decrypt */
+typedef uint16_t crc_t;
+
+
+/** Gives high-level view of state of the SCC */
+enum scc_status {
+    SCC_STATUS_INITIAL,         /**< State of driver before ever checking */
+    SCC_STATUS_CHECKING,        /**< Transient state while driver loading  */
+    SCC_STATUS_UNIMPLEMENTED,   /**< SCC is non-existent or unuseable  */
+    SCC_STATUS_OK,              /**< SCC is in Secure or Default state  */
+    SCC_STATUS_FAILED           /**< In Failed state */
+};
+
+/**
+ * Information about a key slot.
+ */
+struct scc_key_slot
+{
+    uint64_t   owner_id;        /**< Access control value. */
+    uint32_t   length;          /**< Length of value in slot. */
+    uint32_t   offset;          /**< Offset of value from start of RAM. */
+    uint32_t   status;          /**< 0 = unassigned, 1 = assigned. */
+    uint32_t   part_ctl;        /**< for the CCMD register  */
+};
+
+/* Forward-declare a number routines which are not part of user api */
+static int scc_init(void);
+static void scc_cleanup(void);
+static int __init scc_driver_init(void);
+static void __exit scc_driver_exit(void);
+
+/* Forward defines of internal functions */
+OS_DEV_ISR(scc_irq);
+/*static irqreturn_t scc_irq(int irq, void *dev_id);*/
+/** Perform callbacks registered by #scc_monitor_security_failure().
+ *
+ *  Make sure callbacks only happen once...  Since there may be some reason why
+ *  the interrupt isn't generated, this routine could be called from base(task)
+ *  level.
+ *
+ *  One at a time, go through #scc_callbacks[] and call any non-null pointers.
+ */
+static void scc_perform_callbacks(void);
+/*static uint32_t copy_to_scc(const uint8_t* from, uint32_t to, unsigned long count_bytes, uint16_t* crc);
+static uint32_t copy_from_scc(const uint32_t from, uint8_t* to,unsigned long count_bytes, uint16_t* crc);
+static scc_return_t scc_strip_padding(uint8_t* from,unsigned* count_bytes_stripped);*/
+static uint32_t scc_update_state(void);
+static void scc_init_ccitt_crc(void);
+static uint32_t scc_grab_config_values(void);
+static int setup_interrupt_handling(void);
+/**
+ * Perform an encryption on the input.  If @c verify_crc is true, a CRC must be
+ * calculated on the plaintext, and appended, with padding, before computing
+ * the ciphertext.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of plaintext
+ * @param[in]     data_in         Pointer to the plaintext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing ciphertext
+ * @param[in]     add_crc         Flag for computing CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+ */
+/*static scc_return_t scc_encrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out,int add_crc, unsigned long* count_out_bytes);*/
+/**
+ * Perform a decryption on the input.  If @c verify_crc is true, the last block
+ * (maybe the two last blocks) is special - it should contain a CRC and
+ * padding.  These must be stripped and verified.
+ *
+ * @param[in]     count_in_bytes  Count of bytes of ciphertext
+ * @param[in]     data_in         Pointer to the ciphertext
+ * @param[in]     scm_control     Bit values for the SCM_CONTROL register
+ * @param[in,out] data_out        Pointer for storing plaintext
+ * @param[in]     verify_crc      Flag for running CRC - 0 no, else yes
+ * @param[in,out] count_out_bytes Number of bytes available at @c data_out
+
+ */
+/*static scc_return_t scc_decrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out, int verify_crc, unsigned long* count_out_bytes);*/
+static uint32_t host_owns_partition(uint32_t part_no);
+static uint32_t partition_engaged(uint32_t part_no);
+
+static scc_return_t scc_wait_completion(uint32_t* scm_status);
+static int is_cipher_done(uint32_t* scm_status);
+static scc_return_t check_register_accessible (uint32_t offset,
+                                               uint32_t smn_status,
+                                               uint32_t scm_status);
+static scc_return_t check_register_offset(uint32_t offset);
+/*uint8_t make_vpu_partition(void);*/
+
+#ifdef SCC_REGISTER_DEBUG
+static uint32_t dbg_scc_read_register(uint32_t offset);
+static void dbg_scc_write_register(uint32_t offset, uint32_t value);
+#endif
+
+
+/* For Linux kernel, export the API functions to other kernel modules */
+EXPORT_SYMBOL(scc_get_configuration);
+EXPORT_SYMBOL(scc_zeroize_memories);
+/*EXPORT_SYMBOL(scc_crypt);*/
+EXPORT_SYMBOL(scc_set_sw_alarm);
+EXPORT_SYMBOL(scc_monitor_security_failure);
+EXPORT_SYMBOL(scc_stop_monitoring_security_failure);
+EXPORT_SYMBOL(scc_read_register);
+EXPORT_SYMBOL(scc_write_register);
+EXPORT_SYMBOL(scc_allocate_partition);
+EXPORT_SYMBOL(scc_engage_partition);
+EXPORT_SYMBOL(scc_release_partition);
+EXPORT_SYMBOL(scc_diminish_permissions);
+EXPORT_SYMBOL(scc_encrypt_region);
+EXPORT_SYMBOL(scc_decrypt_region);
+/*EXPORT_SYMBOL(make_vpu_partition);*/
+
+
+/* Tell Linux this is not GPL code */
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)");
+
+
+#endif /* SCC_INTERNALS_H */
diff --git a/drivers/mxc/ssi/Kconfig b/drivers/mxc/ssi/Kconfig
new file mode 100644
index 000000000000..4cb581c2f945
--- /dev/null
+++ b/drivers/mxc/ssi/Kconfig
@@ -0,0 +1,12 @@
+#
+# SPI device configuration
+#
+
+menu "MXC SSI support"
+
+config MXC_SSI
+	tristate "SSI support"
+	---help---
+	  Say Y to get the SSI services API available on MXC platform.
+
+endmenu
diff --git a/drivers/mxc/ssi/Makefile b/drivers/mxc/ssi/Makefile
new file mode 100644
index 000000000000..f9bb4419fc19
--- /dev/null
+++ b/drivers/mxc/ssi/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the kernel SSI device drivers.
+#
+
+obj-$(CONFIG_MXC_SSI) 		+= ssimod.o
+
+ssimod-objs := ssi.o
diff --git a/drivers/mxc/ssi/registers.h b/drivers/mxc/ssi/registers.h
new file mode 100644
index 000000000000..ba98d96c5274
--- /dev/null
+++ b/drivers/mxc/ssi/registers.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+ /*!
+  * @file ../ssi/registers.h
+  * @brief This header file contains SSI driver low level definition to access module registers.
+  *
+  * @ingroup SSI
+  */
+
+#ifndef __MXC_SSI_REGISTERS_H__
+#define __MXC_SSI_REGISTERS_H__
+
+/*!
+ * This include to define bool type, false and true definitions.
+ */
+#include <mach/hardware.h>
+
+#define SPBA_CPU_SSI            0x07
+
+#define    MXC_SSISTX0		0x00
+#define    MXC_SSISTX1		0x04
+#define    MXC_SSISRX0		0x08
+#define    MXC_SSISRX1   	0x0C
+#define    MXC_SSISCR           0x10
+#define    MXC_SSISISR          0x14
+#define    MXC_SSISIER   	0x18
+#define    MXC_SSISTCR   	0x1C
+#define    MXC_SSISRCR   	0x20
+#define    MXC_SSISTCCR  	0x24
+#define    MXC_SSISRCCR  	0x28
+#define    MXC_SSISFCSR  	0x2C
+#define    MXC_SSISTR           0x30
+#define    MXC_SSISOR           0x34
+#define    MXC_SSISACNT  	0x38
+#define    MXC_SSISACADD 	0x3C
+#define    MXC_SSISACDAT 	0x40
+#define    MXC_SSISATAG  	0x44
+#define    MXC_SSISTMSK  	0x48
+#define    MXC_SSISRMSK  	0x4C
+
+/* MXC 91221 only */
+#define    MXC_SSISACCST  	0x50
+#define    MXC_SSISACCEN  	0x54
+#define    MXC_SSISACCDIS  	0x58
+
+/*! SSI1 registers offset*/
+#define    MXC_SSI1STX0		0x00
+#define    MXC_SSI1STX1		0x04
+#define    MXC_SSI1SRX0		0x08
+#define    MXC_SSI1SRX1   	0x0C
+#define    MXC_SSI1SCR          0x10
+#define    MXC_SSI1SISR         0x14
+#define    MXC_SSI1SIER   	0x18
+#define    MXC_SSI1STCR   	0x1C
+#define    MXC_SSI1SRCR   	0x20
+#define    MXC_SSI1STCCR  	0x24
+#define    MXC_SSI1SRCCR  	0x28
+#define    MXC_SSI1SFCSR  	0x2C
+#define    MXC_SSI1STR          0x30
+#define    MXC_SSI1SOR          0x34
+#define    MXC_SSI1SACNT  	0x38
+#define    MXC_SSI1SACADD 	0x3C
+#define    MXC_SSI1SACDAT 	0x40
+#define    MXC_SSI1SATAG  	0x44
+#define    MXC_SSI1STMSK  	0x48
+#define    MXC_SSI1SRMSK  	0x4C
+
+/* MXC91221 only */
+
+#define    MXC_SSISACCST  	0x50
+#define    MXC_SSISACCEN  	0x54
+#define    MXC_SSISACCDIS  	0x58
+
+/* Not on MXC91221 */
+/*! SSI2 registers offset*/
+#define    MXC_SSI2STX0   	0x00
+#define    MXC_SSI2STX1         0x04
+#define    MXC_SSI2SRX0    	0x08
+#define    MXC_SSI2SRX1         0x0C
+#define    MXC_SSI2SCR          0x10
+#define    MXC_SSI2SISR         0x14
+#define    MXC_SSI2SIER         0x18
+#define    MXC_SSI2STCR         0x1C
+#define    MXC_SSI2SRCR         0x20
+#define    MXC_SSI2STCCR  	0x24
+#define    MXC_SSI2SRCCR   	0x28
+#define    MXC_SSI2SFCSR        0x2C
+#define    MXC_SSI2STR    	0x30
+#define    MXC_SSI2SOR    	0x34
+#define    MXC_SSI2SACNT  	0x38
+#define    MXC_SSI2SACADD 	0x3C
+#define    MXC_SSI2SACDAT 	0x40
+#define    MXC_SSI2SATAG  	0x44
+#define    MXC_SSI2STMSK  	0x48
+#define    MXC_SSI2SRMSK  	0x4C
+
+/*!
+ * SCR Register bit shift definitions
+ */
+#define SSI_ENABLE_SHIFT            0
+#define SSI_TRANSMIT_ENABLE_SHIFT   1
+#define SSI_RECEIVE_ENABLE_SHIFT    2
+#define SSI_NETWORK_MODE_SHIFT      3
+#define SSI_SYNCHRONOUS_MODE_SHIFT  4
+#define SSI_I2S_MODE_SHIFT          5
+#define SSI_SYSTEM_CLOCK_SHIFT      7
+#define SSI_TWO_CHANNEL_SHIFT       8
+#define SSI_CLOCK_IDLE_SHIFT        9
+
+/* MXC91221 only*/
+#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT        10
+#define SSI_RX_FRAME_CLOCK_DISABLE_SHIFT        11
+
+/*!
+ * STCR & SRCR Registers bit shift definitions
+ */
+#define SSI_EARLY_FRAME_SYNC_SHIFT    0
+#define SSI_FRAME_SYNC_LENGTH_SHIFT   1
+#define SSI_FRAME_SYNC_INVERT_SHIFT   2
+#define SSI_CLOCK_POLARITY_SHIFT      3
+#define SSI_SHIFT_DIRECTION_SHIFT     4
+#define SSI_CLOCK_DIRECTION_SHIFT     5
+#define SSI_FRAME_DIRECTION_SHIFT     6
+#define SSI_FIFO_ENABLE_0_SHIFT       7
+#define SSI_FIFO_ENABLE_1_SHIFT       8
+#define SSI_BIT_0_SHIFT               9
+
+/* MXC91221 only*/
+#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT        10
+#define SSI_RX_DATA_EXTENSION_SHIFT   10	/*SRCR only */
+/*!
+ * STCCR & SRCCR Registers bit shift definitions
+ */
+#define SSI_PRESCALER_MODULUS_SHIFT          0
+#define SSI_FRAME_RATE_DIVIDER_SHIFT         8
+#define SSI_WORD_LENGTH_SHIFT               13
+#define SSI_PRESCALER_RANGE_SHIFT           17
+#define SSI_DIVIDE_BY_TWO_SHIFT             18
+#define SSI_FRAME_DIVIDER_MASK              31
+#define SSI_MIN_FRAME_DIVIDER_RATIO          1
+#define SSI_MAX_FRAME_DIVIDER_RATIO         32
+#define SSI_PRESCALER_MODULUS_MASK         255
+#define SSI_MIN_PRESCALER_MODULUS_RATIO      1
+#define SSI_MAX_PRESCALER_MODULUS_RATIO    256
+#define SSI_WORD_LENGTH_MASK                15
+
+#define SSI_IRQ_STATUS_NUMBER        25
+
+/*!
+ * SFCSR Register bit shift definitions
+ */
+#define SSI_RX_FIFO_1_COUNT_SHIFT       28
+#define SSI_TX_FIFO_1_COUNT_SHIFT       24
+#define SSI_RX_FIFO_1_WATERMARK_SHIFT   20
+#define SSI_TX_FIFO_1_WATERMARK_SHIFT   16
+#define SSI_RX_FIFO_0_COUNT_SHIFT       12
+#define SSI_TX_FIFO_0_COUNT_SHIFT        8
+#define SSI_RX_FIFO_0_WATERMARK_SHIFT    4
+#define SSI_TX_FIFO_0_WATERMARK_SHIFT    0
+#define SSI_MIN_FIFO_WATERMARK           0
+#define SSI_MAX_FIFO_WATERMARK           8
+
+/*!
+ * SSI Option Register (SOR) bit shift definitions
+ */
+#define SSI_FRAME_SYN_RESET_SHIFT        0
+#define SSI_WAIT_SHIFT                   1
+#define SSI_INIT_SHIFT                   3
+#define SSI_TRANSMITTER_CLEAR_SHIFT      4
+#define SSI_RECEIVER_CLEAR_SHIFT         5
+#define SSI_CLOCK_OFF_SHIFT              6
+#define SSI_WAIT_STATE_MASK            0x3
+
+/*!
+ * SSI AC97 Control Register (SACNT) bit shift definitions
+ */
+#define AC97_MODE_ENABLE_SHIFT           0
+#define AC97_VARIABLE_OPERATION_SHIFT    1
+#define AC97_TAG_IN_FIFO_SHIFT           2
+#define AC97_READ_COMMAND_SHIFT          3
+#define AC97_WRITE_COMMAND_SHIFT         4
+#define AC97_FRAME_RATE_DIVIDER_SHIFT    5
+#define AC97_FRAME_RATE_MASK          0x3F
+
+/*!
+ * SSI Test Register (STR) bit shift definitions
+ */
+#define SSI_TEST_MODE_SHIFT               15
+#define SSI_RCK2TCK_SHIFT                 14
+#define SSI_RFS2TFS_SHIFT                 13
+#define SSI_RXSTATE_SHIFT                 8
+#define SSI_TXD2RXD_SHIFT                 7
+#define SSI_TCK2RCK_SHIFT                 6
+#define SSI_TFS2RFS_SHIFT                 5
+#define SSI_TXSTATE_SHIFT                 0
+
+#endif				/* __MXC_SSI_REGISTERS_H__ */
diff --git a/drivers/mxc/ssi/ssi.c b/drivers/mxc/ssi/ssi.c
new file mode 100644
index 000000000000..1b3a2729b174
--- /dev/null
+++ b/drivers/mxc/ssi/ssi.c
@@ -0,0 +1,1221 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ssi.c
+ * @brief This file contains the implementation of the SSI driver main services
+ *
+ *
+ * @ingroup SSI
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include <mach/clock.h>
+
+#include "registers.h"
+#include "ssi.h"
+
+static spinlock_t ssi_lock;
+struct mxc_audio_platform_data *ssi_platform_data;
+
+EXPORT_SYMBOL(ssi_ac97_frame_rate_divider);
+EXPORT_SYMBOL(ssi_ac97_get_command_address_register);
+EXPORT_SYMBOL(ssi_ac97_get_command_data_register);
+EXPORT_SYMBOL(ssi_ac97_get_tag_register);
+EXPORT_SYMBOL(ssi_ac97_mode_enable);
+EXPORT_SYMBOL(ssi_ac97_tag_in_fifo);
+EXPORT_SYMBOL(ssi_ac97_read_command);
+EXPORT_SYMBOL(ssi_ac97_set_command_address_register);
+EXPORT_SYMBOL(ssi_ac97_set_command_data_register);
+EXPORT_SYMBOL(ssi_ac97_set_tag_register);
+EXPORT_SYMBOL(ssi_ac97_variable_mode);
+EXPORT_SYMBOL(ssi_ac97_write_command);
+EXPORT_SYMBOL(ssi_clock_idle_state);
+EXPORT_SYMBOL(ssi_clock_off);
+EXPORT_SYMBOL(ssi_enable);
+EXPORT_SYMBOL(ssi_get_data);
+EXPORT_SYMBOL(ssi_get_status);
+EXPORT_SYMBOL(ssi_i2s_mode);
+EXPORT_SYMBOL(ssi_interrupt_disable);
+EXPORT_SYMBOL(ssi_interrupt_enable);
+EXPORT_SYMBOL(ssi_network_mode);
+EXPORT_SYMBOL(ssi_receive_enable);
+EXPORT_SYMBOL(ssi_rx_bit0);
+EXPORT_SYMBOL(ssi_rx_clock_direction);
+EXPORT_SYMBOL(ssi_rx_clock_divide_by_two);
+EXPORT_SYMBOL(ssi_rx_clock_polarity);
+EXPORT_SYMBOL(ssi_rx_clock_prescaler);
+EXPORT_SYMBOL(ssi_rx_early_frame_sync);
+EXPORT_SYMBOL(ssi_rx_fifo_counter);
+EXPORT_SYMBOL(ssi_rx_fifo_enable);
+EXPORT_SYMBOL(ssi_rx_fifo_full_watermark);
+EXPORT_SYMBOL(ssi_rx_flush_fifo);
+EXPORT_SYMBOL(ssi_rx_frame_direction);
+EXPORT_SYMBOL(ssi_rx_frame_rate);
+EXPORT_SYMBOL(ssi_rx_frame_sync_active);
+EXPORT_SYMBOL(ssi_rx_frame_sync_length);
+EXPORT_SYMBOL(ssi_rx_mask_time_slot);
+EXPORT_SYMBOL(ssi_rx_prescaler_modulus);
+EXPORT_SYMBOL(ssi_rx_shift_direction);
+EXPORT_SYMBOL(ssi_rx_word_length);
+EXPORT_SYMBOL(ssi_set_data);
+EXPORT_SYMBOL(ssi_set_wait_states);
+EXPORT_SYMBOL(ssi_synchronous_mode);
+EXPORT_SYMBOL(ssi_system_clock);
+EXPORT_SYMBOL(ssi_transmit_enable);
+EXPORT_SYMBOL(ssi_two_channel_mode);
+EXPORT_SYMBOL(ssi_tx_bit0);
+EXPORT_SYMBOL(ssi_tx_clock_direction);
+EXPORT_SYMBOL(ssi_tx_clock_divide_by_two);
+EXPORT_SYMBOL(ssi_tx_clock_polarity);
+EXPORT_SYMBOL(ssi_tx_clock_prescaler);
+EXPORT_SYMBOL(ssi_tx_early_frame_sync);
+EXPORT_SYMBOL(ssi_tx_fifo_counter);
+EXPORT_SYMBOL(ssi_tx_fifo_empty_watermark);
+EXPORT_SYMBOL(ssi_tx_fifo_enable);
+EXPORT_SYMBOL(ssi_tx_flush_fifo);
+EXPORT_SYMBOL(ssi_tx_frame_direction);
+EXPORT_SYMBOL(ssi_tx_frame_rate);
+EXPORT_SYMBOL(ssi_tx_frame_sync_active);
+EXPORT_SYMBOL(ssi_tx_frame_sync_length);
+EXPORT_SYMBOL(ssi_tx_mask_time_slot);
+EXPORT_SYMBOL(ssi_tx_prescaler_modulus);
+EXPORT_SYMBOL(ssi_tx_shift_direction);
+EXPORT_SYMBOL(ssi_tx_word_length);
+EXPORT_SYMBOL(get_ssi_fifo_addr);
+
+struct resource *res;
+unsigned long base_addr_1;
+unsigned long base_addr_2;
+
+unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction)
+{
+	unsigned int fifo_addr;
+	if (direction == 1) {
+		if (ssi_platform_data->ssi_num == 2) {
+			fifo_addr =
+			    (ssi ==
+			     SSI1) ? (int)(base_addr_1 +
+					   MXC_SSI1STX0) : (int)(base_addr_2 +
+								 MXC_SSI2STX0);
+		} else {
+			fifo_addr = (int)(base_addr_1 + MXC_SSI1STX0);
+		}
+	} else {
+		fifo_addr = (int)(base_addr_1 + MXC_SSI1SRX0);
+	}
+	return fifo_addr;
+}
+
+void * get_ssi_base_addr(unsigned int ssi)
+{
+	if (ssi_platform_data->ssi_num == 2) {
+		if (ssi == SSI1)
+			return IO_ADDRESS(base_addr_1);
+		else
+			return IO_ADDRESS(base_addr_2);
+	}
+	return IO_ADDRESS(base_addr_1);
+}
+
+void set_register_bits(unsigned int mask, unsigned int data,
+		       unsigned int offset, unsigned int ssi)
+{
+	volatile unsigned long reg = 0;
+	void *base_addr = get_ssi_base_addr(ssi);
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&ssi_lock, flags);
+	reg = __raw_readl(base_addr + offset);
+	reg = (reg & (~mask)) | data;
+	__raw_writel(reg, base_addr + offset);
+	spin_unlock_irqrestore(&ssi_lock, flags);
+}
+
+unsigned long getreg_value(unsigned int offset, unsigned int ssi)
+{
+	void *base_addr = get_ssi_base_addr(ssi);
+	return __raw_readl(base_addr + offset);
+}
+
+void set_register(unsigned int data, unsigned int offset, unsigned int ssi)
+{
+	void *base_addr = get_ssi_base_addr(ssi);
+	__raw_writel(data, base_addr + offset);
+}
+
+/*!
+ * This function controls the AC97 frame rate divider.
+ *
+ * @param        module               the module number
+ * @param        frame_rate_divider   the AC97 frame rate divider
+ */
+void ssi_ac97_frame_rate_divider(ssi_mod module,
+				 unsigned char frame_rate_divider)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	reg |= ((frame_rate_divider & AC97_FRAME_RATE_MASK)
+		<< AC97_FRAME_RATE_DIVIDER_SHIFT);
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function gets the AC97 command address register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the command address slot information.
+ */
+unsigned int ssi_ac97_get_command_address_register(ssi_mod module)
+{
+	return getreg_value(MXC_SSISACADD, module);
+}
+
+/*!
+ * This function gets the AC97 command data register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the command data slot information.
+ */
+unsigned int ssi_ac97_get_command_data_register(ssi_mod module)
+{
+	return getreg_value(MXC_SSISACDAT, module);
+}
+
+/*!
+ * This function gets the AC97 tag register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the tag information.
+ */
+unsigned int ssi_ac97_get_tag_register(ssi_mod module)
+{
+	return getreg_value(MXC_SSISATAG, module);
+}
+
+/*!
+ * This function controls the AC97 mode.
+ *
+ * @param        module        the module number
+ * @param        state         the AC97 mode state (enabled or disabled)
+ */
+void ssi_ac97_mode_enable(ssi_mod module, bool state)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	if (state == true) {
+		reg |= (1 << AC97_MODE_ENABLE_SHIFT);
+	} else {
+		reg &= ~(1 << AC97_MODE_ENABLE_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function controls the AC97 tag in FIFO behavior.
+ *
+ * @param        module        the module number
+ * @param        state         the tag in fifo behavior (Tag info stored in Rx FIFO 0 if true,
+ * Tag info stored in SATAG register otherwise)
+ */
+void ssi_ac97_tag_in_fifo(ssi_mod module, bool state)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	if (state == true) {
+		reg |= (1 << AC97_TAG_IN_FIFO_SHIFT);
+	} else {
+		reg &= ~(1 << AC97_TAG_IN_FIFO_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function controls the AC97 read command.
+ *
+ * @param        module        the module number
+ * @param        state         the next AC97 command is a read command or not
+ */
+void ssi_ac97_read_command(ssi_mod module, bool state)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	if (state == true) {
+		reg |= (1 << AC97_READ_COMMAND_SHIFT);
+	} else {
+		reg &= ~(1 << AC97_READ_COMMAND_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function sets the AC97 command address register.
+ *
+ * @param        module        the module number
+ * @param        address       the command address slot information
+ */
+void ssi_ac97_set_command_address_register(ssi_mod module, unsigned int address)
+{
+	set_register(address, MXC_SSISACADD, module);
+}
+
+/*!
+ * This function sets the AC97 command data register.
+ *
+ * @param        module        the module number
+ * @param        data          the command data slot information
+ */
+void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data)
+{
+	set_register(data, MXC_SSISACDAT, module);
+}
+
+/*!
+ * This function sets the AC97 tag register.
+ *
+ * @param        module        the module number
+ * @param        tag           the tag information
+ */
+void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag)
+{
+	set_register(tag, MXC_SSISATAG, module);
+}
+
+/*!
+ * This function controls the AC97 variable mode.
+ *
+ * @param        module        the module number
+ * @param        state         the AC97 variable mode state (enabled or disabled)
+ */ void ssi_ac97_variable_mode(ssi_mod module, bool state)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	if (state == true) {
+		reg |= (1 << AC97_VARIABLE_OPERATION_SHIFT);
+	} else {
+		reg &= ~(1 << AC97_VARIABLE_OPERATION_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function controls the AC97 write command.
+ *
+ * @param        module        the module number
+ * @param        state         the next AC97 command is a write command or not
+ */
+void ssi_ac97_write_command(ssi_mod module, bool state)
+{
+	unsigned int reg = 0;
+
+	reg = getreg_value(MXC_SSISACNT, module);
+	if (state == true) {
+		reg |= (1 << AC97_WRITE_COMMAND_SHIFT);
+	} else {
+		reg &= ~(1 << AC97_WRITE_COMMAND_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISACNT, module);
+}
+
+/*!
+ * This function controls the idle state of the transmit clock port during SSI internal gated mode.
+ *
+ * @param        module        the module number
+ * @param        state         the clock idle state
+ */
+void ssi_clock_idle_state(ssi_mod module, idle_state state)
+{
+	set_register_bits(1 << SSI_CLOCK_IDLE_SHIFT,
+			  state << SSI_CLOCK_IDLE_SHIFT, MXC_SSISCR, module);
+}
+
+/*!
+ * This function turns off/on the ccm_ssi_clk to reduce power consumption.
+ *
+ * @param        module        the module number
+ * @param        state         the state for ccm_ssi_clk (true: turn off, else:turn on)
+ */
+void ssi_clock_off(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_CLOCK_OFF_SHIFT,
+			  state << SSI_CLOCK_OFF_SHIFT, MXC_SSISOR, module);
+}
+
+/*!
+ * This function enables/disables the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the state for SSI module
+ */
+void ssi_enable(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_ENABLE_SHIFT, state << SSI_ENABLE_SHIFT,
+			  MXC_SSISCR, module);
+}
+
+/*!
+ * This function gets the data word in the Receive FIFO of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        fifo          the Receive FIFO to read
+ * @return       This function returns the read data.
+ */
+unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo)
+{
+	unsigned int result = 0;
+
+	if (ssi_fifo_0 == fifo) {
+		result = getreg_value(MXC_SSISRX0, module);
+	} else {
+		result = getreg_value(MXC_SSISRX1, module);
+	}
+
+	return result;
+}
+
+/*!
+ * This function returns the status of the SSI module (SISR register) as a combination of status.
+ *
+ * @param        module        the module number
+ * @return       This function returns the status of the SSI module
+ */
+ssi_status_enable_mask ssi_get_status(ssi_mod module)
+{
+	unsigned int result;
+
+	result = getreg_value(MXC_SSISISR, module);
+	result &= ((1 << SSI_IRQ_STATUS_NUMBER) - 1);
+
+	return (ssi_status_enable_mask) result;
+}
+
+/*!
+ * This function selects the I2S mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mode          the I2S mode
+ */
+void ssi_i2s_mode(ssi_mod module, mode_i2s mode)
+{
+	set_register_bits(3 << SSI_I2S_MODE_SHIFT, mode << SSI_I2S_MODE_SHIFT,
+			  MXC_SSISCR, module);
+}
+
+/*!
+ * This function disables the interrupts of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask of the interrupts to disable
+ */
+void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask)
+{
+	set_register_bits(mask, 0, MXC_SSISIER, module);
+}
+
+/*!
+ * This function enables the interrupts of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask of the interrupts to enable
+ */
+void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask)
+{
+	set_register_bits(0, mask, MXC_SSISIER, module);
+}
+
+/*!
+ * This function enables/disables the network mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the network mode state
+ */
+void ssi_network_mode(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_NETWORK_MODE_SHIFT,
+			  state << SSI_NETWORK_MODE_SHIFT, MXC_SSISCR, module);
+}
+
+/*!
+ * This function enables/disables the receive section of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the receive section state
+ */
+void ssi_receive_enable(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_RECEIVE_ENABLE_SHIFT,
+			  state << SSI_RECEIVE_ENABLE_SHIFT, MXC_SSISCR,
+			  module);
+}
+
+/*!
+ * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register.
+ *
+ * @param        module        the module number
+ * @param        state         the state to receive at bit 0
+ */
+void ssi_rx_bit0(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_BIT_0_SHIFT, state << SSI_BIT_0_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function controls the source of the clock signal used to clock the Receive shift register.
+ *
+ * @param        module        the module number
+ * @param        direction     the clock signal direction
+ */
+void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction)
+{
+	set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT,
+			  direction << SSI_CLOCK_DIRECTION_SHIFT, MXC_SSISRCR,
+			  module);
+}
+
+/*!
+ * This function configures the divide-by-two divider of the SSI module for the receive section.
+ *
+ * @param        module        the module number
+ * @param        state         the divider state
+ */
+void ssi_rx_clock_divide_by_two(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT,
+			  state << SSI_DIVIDE_BY_TWO_SHIFT, MXC_SSISRCCR,
+			  module);
+}
+
+/*!
+ * This function controls which bit clock edge is used to clock in data.
+ *
+ * @param        module        the module number
+ * @param        polarity      the clock polarity
+ */
+void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity)
+{
+	set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT,
+			  polarity << SSI_CLOCK_POLARITY_SHIFT, MXC_SSISRCR,
+			  module);
+}
+
+/*!
+ * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section.
+ *
+ * @param        module        the module number
+ * @param        state         the prescaler state
+ */
+void ssi_rx_clock_prescaler(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT,
+			  state << SSI_PRESCALER_RANGE_SHIFT,
+			  MXC_SSISRCCR, module);
+}
+
+/*!
+ * This function controls the early frame sync configuration.
+ *
+ * @param        module        the module number
+ * @param        early         the early frame sync configuration
+ */
+void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early)
+{
+	set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT,
+			  early << SSI_EARLY_FRAME_SYNC_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function gets the number of data words in the Receive FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo
+ * @return       This function returns the number of words in the Rx FIFO.
+ */
+unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo)
+{
+	unsigned char result;
+	result = 0;
+
+	if (ssi_fifo_0 == fifo) {
+		result = getreg_value(MXC_SSISFCSR, module);
+		result &= (0xF << SSI_RX_FIFO_0_COUNT_SHIFT);
+		result = result >> SSI_RX_FIFO_0_COUNT_SHIFT;
+	} else {
+		result = getreg_value(MXC_SSISFCSR, module);
+		result &= (0xF << SSI_RX_FIFO_1_COUNT_SHIFT);
+		result = result >> SSI_RX_FIFO_1_COUNT_SHIFT;
+	}
+
+	return result;
+}
+
+/*!
+ * This function enables the Receive FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        enable        the state of the fifo, enabled or disabled
+ */
+
+void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable)
+{
+	volatile unsigned int reg;
+
+	reg = getreg_value(MXC_SSISRCR, module);
+	if (enable == true) {
+		reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT);
+	} else {
+		reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISRCR, module);
+}
+
+/*!
+ * This function controls the threshold at which the RFFx flag will be set.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        watermark     the watermark
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_fifo_full_watermark(ssi_mod module,
+			       fifo_nb fifo, unsigned char watermark)
+{
+	int result = -1;
+	result = -1;
+
+	if ((watermark > SSI_MIN_FIFO_WATERMARK) &&
+	    (watermark <= SSI_MAX_FIFO_WATERMARK)) {
+		if (ssi_fifo_0 == fifo) {
+			set_register_bits(0xf << SSI_RX_FIFO_0_WATERMARK_SHIFT,
+					  watermark <<
+					  SSI_RX_FIFO_0_WATERMARK_SHIFT,
+					  MXC_SSISFCSR, module);
+		} else {
+			set_register_bits(0xf << SSI_RX_FIFO_1_WATERMARK_SHIFT,
+					  watermark <<
+					  SSI_RX_FIFO_1_WATERMARK_SHIFT,
+					  MXC_SSISFCSR, module);
+		}
+
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function flushes the Receive FIFOs.
+ *
+ * @param        module        the module number
+ */
+void ssi_rx_flush_fifo(ssi_mod module)
+{
+	set_register_bits(0, 1 << SSI_RECEIVER_CLEAR_SHIFT, MXC_SSISOR, module);
+}
+
+/*!
+ * This function controls the direction of the Frame Sync signal for the receive section.
+ *
+ * @param        module        the module number
+ * @param        direction     the Frame Sync signal direction
+ */
+void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction)
+{
+	set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT,
+			  direction << SSI_FRAME_DIRECTION_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function configures the Receive frame rate divider for the receive section.
+ *
+ * @param        module        the module number
+ * @param        ratio         the divide ratio from 1 to 32
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio)
+{
+	int result = -1;
+
+	if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) &&
+	    (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) {
+		set_register_bits(SSI_FRAME_DIVIDER_MASK <<
+				  SSI_FRAME_RATE_DIVIDER_SHIFT,
+				  (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT,
+				  MXC_SSISRCCR, module);
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function controls the Frame Sync active polarity for the receive section.
+ *
+ * @param        module        the module number
+ * @param        active        the Frame Sync active polarity
+ */
+void ssi_rx_frame_sync_active(ssi_mod module,
+			      ssi_tx_rx_frame_sync_active active)
+{
+	set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT,
+			  active << SSI_FRAME_SYNC_INVERT_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function controls the Frame Sync length (one word or one bit long) for the receive section.
+ *
+ * @param        module        the module number
+ * @param        length        the Frame Sync length
+ */
+void ssi_rx_frame_sync_length(ssi_mod module,
+			      ssi_tx_rx_frame_sync_length length)
+{
+	set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT,
+			  length << SSI_FRAME_SYNC_LENGTH_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function configures the time slot(s) to mask for the receive section.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask to indicate the time slot(s) masked
+ */
+void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask)
+{
+	set_register_bits(0xFFFFFFFF, mask, MXC_SSISRMSK, module);
+}
+
+/*!
+ * This function configures the Prescale divider for the receive section.
+ *
+ * @param        module        the module number
+ * @param        divider       the divide ratio from 1 to  256
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider)
+{
+	int result = -1;
+
+	if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) &&
+	    (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) {
+
+		set_register_bits(SSI_PRESCALER_MODULUS_MASK <<
+				  SSI_PRESCALER_MODULUS_SHIFT,
+				  (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT,
+				  MXC_SSISRCCR, module);
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function controls whether the MSB or LSB will be received first in a sample.
+ *
+ * @param        module        the module number
+ * @param        direction     the shift direction
+ */
+void ssi_rx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction)
+{
+	set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT,
+			  direction << SSI_SHIFT_DIRECTION_SHIFT,
+			  MXC_SSISRCR, module);
+}
+
+/*!
+ * This function configures the Receive word length.
+ *
+ * @param        module        the module number
+ * @param        length        the word length
+ */
+void ssi_rx_word_length(ssi_mod module, ssi_word_length length)
+{
+	set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT,
+			  length << SSI_WORD_LENGTH_SHIFT,
+			  MXC_SSISRCCR, module);
+}
+
+/*!
+ * This function sets the data word in the Transmit FIFO of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        fifo          the FIFO number
+ * @param        data          the data to load in the FIFO
+ */
+
+void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data)
+{
+	if (ssi_fifo_0 == fifo) {
+		set_register(data, MXC_SSISTX0, module);
+	} else {
+		set_register(data, MXC_SSISTX1, module);
+	}
+}
+
+/*!
+ * This function controls the number of wait states between the core and SSI.
+ *
+ * @param        module        the module number
+ * @param        wait          the number of wait state(s)
+ */
+void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait)
+{
+	set_register_bits(SSI_WAIT_STATE_MASK << SSI_WAIT_SHIFT,
+			  wait << SSI_WAIT_SHIFT, MXC_SSISOR, module);
+}
+
+/*!
+ * This function enables/disables the synchronous mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the synchronous mode state
+ */
+void ssi_synchronous_mode(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_SYNCHRONOUS_MODE_SHIFT,
+			  state << SSI_SYNCHRONOUS_MODE_SHIFT,
+			  MXC_SSISCR, module);
+}
+
+/*!
+ * This function allows the SSI module to output the SYS_CLK at the SRCK port.
+ *
+ * @param        module        the module number
+ * @param        state         the system clock state
+ */
+void ssi_system_clock(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_SYSTEM_CLOCK_SHIFT,
+			  state << SSI_SYSTEM_CLOCK_SHIFT, MXC_SSISCR, module);
+}
+
+/*!
+ * This function enables/disables the transmit section of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the transmit section state
+ */
+void ssi_transmit_enable(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_TRANSMIT_ENABLE_SHIFT,
+			  state << SSI_TRANSMIT_ENABLE_SHIFT,
+			  MXC_SSISCR, module);
+}
+
+/*!
+ * This function allows the SSI module to operate in the two channel mode.
+ *
+ * @param        module        the module number
+ * @param        state         the two channel mode state
+ */
+void ssi_two_channel_mode(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_TWO_CHANNEL_SHIFT,
+			  state << SSI_TWO_CHANNEL_SHIFT, MXC_SSISCR, module);
+}
+
+/*!
+ * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register.
+ *
+ * @param        module        the module number
+ * @param        state         the transmit from bit 0 state
+ */
+void ssi_tx_bit0(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_BIT_0_SHIFT,
+			  state << SSI_BIT_0_SHIFT, MXC_SSISTCR, module);
+}
+
+/*!
+ * This function controls the direction of the clock signal used to clock the Transmit shift register.
+ *
+ * @param        module        the module number
+ * @param        direction     the clock signal direction
+ */
+void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction)
+{
+	set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT,
+			  direction << SSI_CLOCK_DIRECTION_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function configures the divide-by-two divider of the SSI module for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        state         the divider state
+ */
+void ssi_tx_clock_divide_by_two(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT,
+			  state << SSI_DIVIDE_BY_TWO_SHIFT,
+			  MXC_SSISTCCR, module);
+}
+
+/*!
+ * This function controls which bit clock edge is used to clock out data.
+ *
+ * @param        module        the module number
+ * @param        polarity      the clock polarity
+ */
+void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity)
+{
+	set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT,
+			  polarity << SSI_CLOCK_POLARITY_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        state         the prescaler state
+ */
+void ssi_tx_clock_prescaler(ssi_mod module, bool state)
+{
+	set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT,
+			  state << SSI_PRESCALER_RANGE_SHIFT,
+			  MXC_SSISTCCR, module);
+}
+
+/*!
+ * This function controls the early frame sync configuration for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        early         the early frame sync configuration
+ */
+void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early)
+{
+	set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT,
+			  early << SSI_EARLY_FRAME_SYNC_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function gets the number of data words in the Transmit FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo
+ * @return       This function returns the number of words in the Tx FIFO.
+ */
+unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo)
+{
+	unsigned char result = 0;
+
+	if (ssi_fifo_0 == fifo) {
+		result = getreg_value(MXC_SSISFCSR, module);
+		result &= (0xF << SSI_TX_FIFO_0_COUNT_SHIFT);
+		result >>= SSI_TX_FIFO_0_COUNT_SHIFT;
+	} else {
+		result = getreg_value(MXC_SSISFCSR, module);
+		result &= (0xF << SSI_TX_FIFO_1_COUNT_SHIFT);
+		result >>= SSI_TX_FIFO_1_COUNT_SHIFT;
+	}
+
+	return result;
+}
+
+/*!
+ * This function controls the threshold at which the TFEx flag will be set.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        watermark     the watermark
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_fifo_empty_watermark(ssi_mod module,
+				fifo_nb fifo, unsigned char watermark)
+{
+	int result = -1;
+
+	if ((watermark > SSI_MIN_FIFO_WATERMARK) &&
+	    (watermark <= SSI_MAX_FIFO_WATERMARK)) {
+		if (ssi_fifo_0 == fifo) {
+			set_register_bits(0xf << SSI_TX_FIFO_0_WATERMARK_SHIFT,
+					  watermark <<
+					  SSI_TX_FIFO_0_WATERMARK_SHIFT,
+					  MXC_SSISFCSR, module);
+		} else {
+			set_register_bits(0xf << SSI_TX_FIFO_1_WATERMARK_SHIFT,
+					  watermark <<
+					  SSI_TX_FIFO_1_WATERMARK_SHIFT,
+					  MXC_SSISFCSR, module);
+		}
+
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function enables the Transmit FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        enable        the state of the fifo, enabled or disabled
+ */
+
+void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable)
+{
+	unsigned int reg;
+
+	reg = getreg_value(MXC_SSISTCR, module);
+	if (enable == true) {
+		reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT);
+	} else {
+		reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT);
+	}
+
+	set_register(reg, MXC_SSISTCR, module);
+}
+
+/*!
+ * This function flushes the Transmit FIFOs.
+ *
+ * @param        module        the module number
+ */
+void ssi_tx_flush_fifo(ssi_mod module)
+{
+	set_register_bits(0, 1 << SSI_TRANSMITTER_CLEAR_SHIFT,
+			  MXC_SSISOR, module);
+}
+
+/*!
+ * This function controls the direction of the Frame Sync signal for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        direction     the Frame Sync signal direction
+ */
+void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction)
+{
+	set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT,
+			  direction << SSI_FRAME_DIRECTION_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function configures the Transmit frame rate divider.
+ *
+ * @param        module        the module number
+ * @param        ratio         the divide ratio from 1 to 32
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio)
+{
+	int result = -1;
+
+	if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) &&
+	    (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) {
+
+		set_register_bits(SSI_FRAME_DIVIDER_MASK <<
+				  SSI_FRAME_RATE_DIVIDER_SHIFT,
+				  (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT,
+				  MXC_SSISTCCR, module);
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function controls the Frame Sync active polarity for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        active        the Frame Sync active polarity
+ */
+void ssi_tx_frame_sync_active(ssi_mod module,
+			      ssi_tx_rx_frame_sync_active active)
+{
+	set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT,
+			  active << SSI_FRAME_SYNC_INVERT_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function controls the Frame Sync length (one word or one bit long) for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        length        the Frame Sync length
+ */
+void ssi_tx_frame_sync_length(ssi_mod module,
+			      ssi_tx_rx_frame_sync_length length)
+{
+	set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT,
+			  length << SSI_FRAME_SYNC_LENGTH_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function configures the time slot(s) to mask for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask to indicate the time slot(s) masked
+ */
+void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask)
+{
+	set_register_bits(0xFFFFFFFF, mask, MXC_SSISTMSK, module);
+}
+
+/*!
+ * This function configures the Prescale divider for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        divider       the divide ratio from 1 to  256
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider)
+{
+	int result = -1;
+
+	if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) &&
+	    (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) {
+
+		set_register_bits(SSI_PRESCALER_MODULUS_MASK <<
+				  SSI_PRESCALER_MODULUS_SHIFT,
+				  (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT,
+				  MXC_SSISTCCR, module);
+		result = 0;
+	}
+
+	return result;
+}
+
+/*!
+ * This function controls whether the MSB or LSB will be transmitted first in a sample.
+ *
+ * @param        module        the module number
+ * @param        direction     the shift direction
+ */
+void ssi_tx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction)
+{
+	set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT,
+			  direction << SSI_SHIFT_DIRECTION_SHIFT,
+			  MXC_SSISTCR, module);
+}
+
+/*!
+ * This function configures the Transmit word length.
+ *
+ * @param        module        the module number
+ * @param        length        the word length
+ */
+void ssi_tx_word_length(ssi_mod module, ssi_word_length length)
+{
+	set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT,
+			  length << SSI_WORD_LENGTH_SHIFT,
+			  MXC_SSISTCCR, module);
+}
+
+/*!
+ * This function initializes the driver in terms of memory of the soundcard
+ * and some basic HW clock settings.
+ *
+ * @return              0 on success, -1 otherwise.
+ */
+static int __init ssi_probe(struct platform_device *pdev)
+{
+	int ret = -1;
+	ssi_platform_data =
+	    (struct mxc_audio_platform_data *)pdev->dev.platform_data;
+	if (!ssi_platform_data) {
+		dev_err(&pdev->dev, "can't get the platform data for SSI\n");
+		return -EINVAL;
+	}
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res) {
+		dev_err(&pdev->dev, "can't get platform resource -  SSI\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	if (pdev->id == 0) {
+		base_addr_1 = res->start;
+	} else if (pdev->id == 1) {
+		base_addr_2 = res->start;
+	}
+
+	printk(KERN_INFO "SSI %d module loaded successfully \n", pdev->id + 1);
+
+	return 0;
+      err:
+	return -1;
+
+}
+
+static int ssi_remove(struct platform_device *dev)
+{
+	return 0;
+}
+
+static struct platform_driver mxc_ssi_driver = {
+	.probe = ssi_probe,
+	.remove = ssi_remove,
+	.driver = {
+		   .name = "mxc_ssi",
+		   },
+};
+
+/*!
+ * This function implements the init function of the SSI device.
+ * This function is called when the module is loaded.
+ *
+ * @return       This function returns 0.
+ */
+static int __init ssi_init(void)
+{
+	spin_lock_init(&ssi_lock);
+	return platform_driver_register(&mxc_ssi_driver);
+
+}
+
+/*!
+ * This function implements the exit function of the SPI device.
+ * This function is called when the module is unloaded.
+ *
+ */
+static void __exit ssi_exit(void)
+{
+	platform_driver_unregister(&mxc_ssi_driver);
+	printk(KERN_INFO "SSI module unloaded successfully\n");
+}
+
+module_init(ssi_init);
+module_exit(ssi_exit);
+
+MODULE_DESCRIPTION("SSI char device driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/ssi/ssi.h b/drivers/mxc/ssi/ssi.h
new file mode 100644
index 000000000000..22032b6616fa
--- /dev/null
+++ b/drivers/mxc/ssi/ssi.h
@@ -0,0 +1,574 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+ /*!
+  * @defgroup SSI Synchronous Serial Interface (SSI) Driver
+  */
+
+ /*!
+  * @file ssi.h
+  * @brief This header file contains SSI driver functions prototypes.
+  *
+  * @ingroup SSI
+  */
+
+#ifndef __MXC_SSI_H__
+#define __MXC_SSI_H__
+
+#include "ssi_types.h"
+
+/*!
+ * This function gets the SSI fifo address.
+ *
+ * @param        ssi                 ssi number
+ * @param        direction           To indicate playback / recording
+ * @return       This function returns the SSI fifo address.
+ */
+unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction);
+
+/*!
+ * This function controls the AC97 frame rate divider.
+ *
+ * @param        module               the module number
+ * @param        frame_rate_divider   the AC97 frame rate divider
+ */
+void ssi_ac97_frame_rate_divider(ssi_mod module,
+				 unsigned char frame_rate_divider);
+
+/*!
+ * This function gets the AC97 command address register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the command address slot information.
+ */
+unsigned int ssi_ac97_get_command_address_register(ssi_mod module);
+
+/*!
+ * This function gets the AC97 command data register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the command data slot information.
+ */
+unsigned int ssi_ac97_get_command_data_register(ssi_mod module);
+
+/*!
+ * This function gets the AC97 tag register.
+ *
+ * @param        module        the module number
+ * @return       This function returns the tag information.
+ */
+unsigned int ssi_ac97_get_tag_register(ssi_mod module);
+
+/*!
+ * This function controls the AC97 mode.
+ *
+ * @param        module        the module number
+ * @param        state         the AC97 mode state (enabled or disabled)
+ */
+void ssi_ac97_mode_enable(ssi_mod module, bool state);
+
+/*!
+ * This function controls the AC97 tag in FIFO behavior.
+ *
+ * @param        module        the module number
+ * @param        state         the tag in fifo behavior (Tag info stored in Rx FIFO 0 if TRUE,
+ * Tag info stored in SATAG register otherwise)
+ */
+void ssi_ac97_tag_in_fifo(ssi_mod module, bool state);
+
+/*!
+ * This function controls the AC97 read command.
+ *
+ * @param        module        the module number
+ * @param        state         the next AC97 command is a read command or not
+ */
+void ssi_ac97_read_command(ssi_mod module, bool state);
+
+/*!
+ * This function sets the AC97 command address register.
+ *
+ * @param        module        the module number
+ * @param        address       the command address slot information
+ */
+void ssi_ac97_set_command_address_register(ssi_mod module,
+					   unsigned int address);
+
+/*!
+ * This function sets the AC97 command data register.
+ *
+ * @param        module        the module number
+ * @param        data          the command data slot information
+ */
+void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data);
+
+/*!
+ * This function sets the AC97 tag register.
+ *
+ * @param        module        the module number
+ * @param        tag           the tag information
+ */
+void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag);
+
+/*!
+ * This function controls the AC97 variable mode.
+ *
+ * @param        module        the module number
+ * @param        state         the AC97 variable mode state (enabled or disabled)
+ */
+void ssi_ac97_variable_mode(ssi_mod module, bool state);
+
+/*!
+ * This function controls the AC97 write command.
+ *
+ * @param        module        the module number
+ * @param        state         the next AC97 command is a write command or not
+ */
+void ssi_ac97_write_command(ssi_mod module, bool state);
+
+/*!
+ * This function controls the idle state of the transmit clock port during SSI internal gated mode.
+ *
+ * @param        module        the module number
+ * @param        state         the clock idle state
+ */
+void ssi_clock_idle_state(ssi_mod module, idle_state state);
+
+/*!
+ * This function turns off/on the ccm_ssi_clk to reduce power consumption.
+ *
+ * @param        module        the module number
+ * @param        state         the state for ccm_ssi_clk (true: turn off, else:turn on)
+ */
+void ssi_clock_off(ssi_mod module, bool state);
+
+/*!
+ * This function enables/disables the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the state for SSI module
+ */
+void ssi_enable(ssi_mod module, bool state);
+
+/*!
+ * This function gets the data word in the Receive FIFO of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        fifo          the Receive FIFO to read
+ * @return       This function returns the read data.
+ */
+unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo);
+
+/*!
+ * This function returns the status of the SSI module (SISR register) as a combination of status.
+ *
+ * @param        module        the module number
+ * @return       This function returns the status of the SSI module.
+ */
+ssi_status_enable_mask ssi_get_status(ssi_mod module);
+
+/*!
+ * This function selects the I2S mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mode          the I2S mode
+ */
+void ssi_i2s_mode(ssi_mod module, mode_i2s mode);
+
+/*!
+ * This function disables the interrupts of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask of the interrupts to disable
+ */
+void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask);
+
+/*!
+ * This function enables the interrupts of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask of the interrupts to enable
+ */
+void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask);
+
+/*!
+ * This function enables/disables the network mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the network mode state
+ */
+void ssi_network_mode(ssi_mod module, bool state);
+
+/*!
+ * This function enables/disables the receive section of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the receive section state
+ */
+void ssi_receive_enable(ssi_mod module, bool state);
+
+/*!
+ * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register.
+ *
+ * @param        module        the module number
+ * @param        state         the state to receive at bit 0
+ */
+void ssi_rx_bit0(ssi_mod module, bool state);
+
+/*!
+ * This function controls the source of the clock signal used to clock the Receive shift register.
+ *
+ * @param        module        the module number
+ * @param        direction     the clock signal direction
+ */
+void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction);
+
+/*!
+ * This function configures the divide-by-two divider of the SSI module for the receive section.
+ *
+ * @param        module        the module number
+ * @param        state         the divider state
+ */
+void ssi_rx_clock_divide_by_two(ssi_mod module, bool state);
+
+/*!
+ * This function controls which bit clock edge is used to clock in data.
+ *
+ * @param        module        the module number
+ * @param        polarity      the clock polarity
+ */
+void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity);
+
+/*!
+ * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section.
+ *
+ * @param        module        the module number
+ * @param        state         the prescaler state
+ */
+void ssi_rx_clock_prescaler(ssi_mod module, bool state);
+
+/*!
+ * This function controls the early frame sync configuration.
+ *
+ * @param        module        the module number
+ * @param        early         the early frame sync configuration
+ */
+void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early);
+
+/*!
+ * This function gets the number of data words in the Receive FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo
+ * @return       This function returns the number of words in the Rx FIFO.
+ */
+unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo);
+
+/*!
+ * This function enables the Receive FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        enabled       the state of the fifo, enabled or disabled
+ */
+void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enabled);
+
+/*!
+ * This function controls the threshold at which the RFFx flag will be set.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        watermark     the watermark
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_fifo_full_watermark(ssi_mod module,
+			       fifo_nb fifo, unsigned char watermark);
+
+/*!
+ * This function flushes the Receive FIFOs.
+ *
+ * @param        module        the module number
+ */
+void ssi_rx_flush_fifo(ssi_mod module);
+
+/*!
+ * This function controls the direction of the Frame Sync signal for the receive section.
+ *
+ * @param        module        the module number
+ * @param        direction     the Frame Sync signal direction
+ */
+void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction);
+
+/*!
+ * This function configures the Receive frame rate divider for the receive section.
+ *
+ * @param        module        the module number
+ * @param        ratio         the divide ratio from 1 to 32
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio);
+
+/*!
+ * This function controls the Frame Sync active polarity for the receive section.
+ *
+ * @param        module        the module number
+ * @param        active        the Frame Sync active polarity
+ */
+void ssi_rx_frame_sync_active(ssi_mod module,
+			      ssi_tx_rx_frame_sync_active active);
+
+/*!
+ * This function controls the Frame Sync length (one word or one bit long) for the receive section.
+ *
+ * @param        module        the module number
+ * @param        length        the Frame Sync length
+ */
+void ssi_rx_frame_sync_length(ssi_mod module,
+			      ssi_tx_rx_frame_sync_length length);
+
+/*!
+ * This function configures the time slot(s) to mask for the receive section.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask to indicate the time slot(s) masked
+ */
+void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask);
+
+/*!
+ * This function configures the Prescale divider for the receive section.
+ *
+ * @param        module        the module number
+ * @param        divider       the divide ratio from 1 to  256
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider);
+
+/*!
+ * This function controls whether the MSB or LSB will be received first in a sample.
+ *
+ * @param        module        the module number
+ * @param        direction     the shift direction
+ */
+void ssi_rx_shift_direction(ssi_mod module,
+			    ssi_tx_rx_shift_direction direction);
+
+/*!
+ * This function configures the Receive word length.
+ *
+ * @param        module        the module number
+ * @param        length        the word length
+ */
+void ssi_rx_word_length(ssi_mod module, ssi_word_length length);
+
+/*!
+ * This function sets the data word in the Transmit FIFO of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        fifo          the FIFO number
+ * @param        data          the data to load in the FIFO
+ */
+void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data);
+
+/*!
+ * This function controls the number of wait states between the core and SSI.
+ *
+ * @param        module        the module number
+ * @param        wait          the number of wait state(s)
+ */
+void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait);
+
+/*!
+ * This function enables/disables the synchronous mode of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the synchronous mode state
+ */
+void ssi_synchronous_mode(ssi_mod module, bool state);
+
+/*!
+ * This function allows the SSI module to output the SYS_CLK at the SRCK port.
+ *
+ * @param        module        the module number
+ * @param        state         the system clock state
+ */
+void ssi_system_clock(ssi_mod module, bool state);
+
+/*!
+ * This function enables/disables the transmit section of the SSI module.
+ *
+ * @param        module        the module number
+ * @param        state         the transmit section state
+ */
+void ssi_transmit_enable(ssi_mod module, bool state);
+
+/*!
+ * This function allows the SSI module to operate in the two channel mode.
+ *
+ * @param        module        the module number
+ * @param        state         the two channel mode state
+ */
+void ssi_two_channel_mode(ssi_mod module, bool state);
+
+/*!
+ * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register.
+ *
+ * @param        module        the module number
+ * @param        state         the transmit from bit 0 state
+ */
+void ssi_tx_bit0(ssi_mod module, bool state);
+
+/*!
+ * This function controls the direction of the clock signal used to clock the Transmit shift register.
+ *
+ * @param        module        the module number
+ * @param        direction     the clock signal direction
+ */
+void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction);
+
+/*!
+ * This function configures the divide-by-two divider of the SSI module for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        state         the divider state
+ */
+void ssi_tx_clock_divide_by_two(ssi_mod module, bool state);
+
+/*!
+ * This function controls which bit clock edge is used to clock out data.
+ *
+ * @param        module        the module number
+ * @param        polarity      the clock polarity
+ */
+void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity);
+
+/*!
+ * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        state         the prescaler state
+ */
+void ssi_tx_clock_prescaler(ssi_mod module, bool state);
+
+/*!
+ * This function controls the early frame sync configuration for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        early         the early frame sync configuration
+ */
+void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early);
+
+/*!
+ * This function gets the number of data words in the Transmit FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo
+ * @return       This function returns the number of words in the Tx FIFO.
+ */
+unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo);
+
+/*!
+ * This function controls the threshold at which the TFEx flag will be set.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        watermark     the watermark
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_fifo_empty_watermark(ssi_mod module, fifo_nb fifo,
+				unsigned char watermark);
+
+/*!
+ * This function enables the Transmit FIFO.
+ *
+ * @param        module        the module number
+ * @param        fifo          the fifo to enable
+ * @param        enable        the state of the FIFO, enabled or disabled
+ */
+void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable);
+
+/*!
+ * This function flushes the Transmit FIFOs.
+ *
+ * @param        module        the module number
+ */
+void ssi_tx_flush_fifo(ssi_mod module);
+
+/*!
+ * This function controls the direction of the Frame Sync signal for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        direction     the Frame Sync signal direction
+ */
+void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction);
+
+/*!
+ * This function configures the Transmit frame rate divider.
+ *
+ * @param        module        the module number
+ * @param        ratio         the divide ratio from 1 to 32
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio);
+
+/*!
+ * This function controls the Frame Sync active polarity for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        active        the Frame Sync active polarity
+ */
+void ssi_tx_frame_sync_active(ssi_mod module,
+			      ssi_tx_rx_frame_sync_active active);
+
+/*!
+ * This function controls the Frame Sync length (one word or one bit long) for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        length        the Frame Sync length
+ */
+void ssi_tx_frame_sync_length(ssi_mod module,
+			      ssi_tx_rx_frame_sync_length length);
+
+/*!
+ * This function configures the time slot(s) to mask for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        mask          the mask to indicate the time slot(s) masked
+ */
+void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask);
+
+/*!
+ * This function configures the Prescale divider for the transmit section.
+ *
+ * @param        module        the module number
+ * @param        divider       the divide ratio from 1 to  256
+ * @return       This function returns the result of the operation (0 if successful, -1 otherwise).
+ */
+int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider);
+
+/*!
+ * This function controls whether the MSB or LSB will be transmited first in a sample.
+ *
+ * @param        module        the module number
+ * @param        direction     the shift direction
+ */
+void ssi_tx_shift_direction(ssi_mod module,
+			    ssi_tx_rx_shift_direction direction);
+
+/*!
+ * This function configures the Transmit word length.
+ *
+ * @param        module        the module number
+ * @param        length        the word length
+ */
+void ssi_tx_word_length(ssi_mod module, ssi_word_length length);
+
+#endif				/* __MXC_SSI_H__ */
diff --git a/drivers/mxc/ssi/ssi_types.h b/drivers/mxc/ssi/ssi_types.h
new file mode 100644
index 000000000000..015e65a6d2d2
--- /dev/null
+++ b/drivers/mxc/ssi/ssi_types.h
@@ -0,0 +1,367 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+ /*!
+  * @file ssi_types.h
+  * @brief This header file contains SSI types.
+  *
+  * @ingroup SSI
+  */
+
+#ifndef __MXC_SSI_TYPES_H__
+#define __MXC_SSI_TYPES_H__
+
+/*!
+ * This enumeration describes the FIFO number.
+ */
+typedef enum {
+	/*!
+	 * FIFO 0
+	 */
+	ssi_fifo_0 = 0,
+	/*!
+	 * FIFO 1
+	 */
+	ssi_fifo_1 = 1
+} fifo_nb;
+
+/*!
+ * This enumeration describes the clock idle state.
+ */
+typedef enum {
+	/*!
+	 * Clock idle state is 1
+	 */
+	clock_idle_state_1 = 0,
+	/*!
+	 * Clock idle state is 0
+	 */
+	clock_idle_state_0 = 1
+} idle_state;
+
+/*!
+ * This enumeration describes I2S mode.
+ */
+typedef enum {
+	/*!
+	 * Normal mode
+	 */
+	i2s_normal = 0,
+	/*!
+	 * Master mode
+	 */
+	i2s_master = 1,
+	/*!
+	 * Slave mode
+	 */
+	i2s_slave = 2
+} mode_i2s;
+
+/*!
+ * This enumeration describes index for both SSI1 and SSI2 modules.
+ */
+typedef enum {
+	/*!
+	 * SSI1 index
+	 */
+	SSI1 = 0,
+	/*!
+	 * SSI2 index not present on MXC 91221 and MXC91311
+	 */
+	SSI2 = 1
+} ssi_mod;
+
+/*!
+ * This enumeration describes the status/enable bits for interrupt source of the SSI module.
+ */
+typedef enum {
+	/*!
+	 * SSI Transmit FIFO 0 empty bit
+	 */
+	ssi_tx_fifo_0_empty = 0x00000001,
+	/*!
+	 * SSI Transmit FIFO 1 empty bit
+	 */
+	ssi_tx_fifo_1_empty = 0x00000002,
+	/*!
+	 * SSI Receive FIFO 0 full bit
+	 */
+	ssi_rx_fifo_0_full = 0x00000004,
+	/*!
+	 * SSI Receive FIFO 1 full bit
+	 */
+	ssi_rx_fifo_1_full = 0x00000008,
+	/*!
+	 * SSI Receive Last Time Slot bit
+	 */
+	ssi_rls = 0x00000010,
+	/*!
+	 * SSI Transmit Last Time Slot bit
+	 */
+	ssi_tls = 0x00000020,
+	/*!
+	 * SSI Receive Frame Sync bit
+	 */
+	ssi_rfs = 0x00000040,
+	/*!
+	 * SSI Transmit Frame Sync bit
+	 */
+	ssi_tfs = 0x00000080,
+	/*!
+	 * SSI Transmitter underrun 0 bit
+	 */
+	ssi_transmitter_underrun_0 = 0x00000100,
+	/*!
+	 * SSI Transmitter underrun 1 bit
+	 */
+	ssi_transmitter_underrun_1 = 0x00000200,
+	/*!
+	 * SSI Receiver overrun 0 bit
+	 */
+	ssi_receiver_overrun_0 = 0x00000400,
+	/*!
+	 * SSI Receiver overrun 1 bit
+	 */
+	ssi_receiver_overrun_1 = 0x00000800,
+	/*!
+	 * SSI Transmit Data register empty 0 bit
+	 */
+	ssi_tx_data_reg_empty_0 = 0x00001000,
+	/*!
+	 * SSI Transmit Data register empty 1 bit
+	 */
+	ssi_tx_data_reg_empty_1 = 0x00002000,
+
+	/*!
+	 * SSI Receive Data Ready 0 bit
+	 */
+	ssi_rx_data_ready_0 = 0x00004000,
+	/*!
+	 * SSI Receive Data Ready 1 bit
+	 */
+	ssi_rx_data_ready_1 = 0x00008000,
+	/*!
+	 * SSI Receive tag updated bit
+	 */
+	ssi_rx_tag_updated = 0x00010000,
+	/*!
+	 * SSI Command data register updated bit
+	 */
+	ssi_cmd_data_reg_updated = 0x00020000,
+	/*!
+	 * SSI Command address register updated bit
+	 */
+	ssi_cmd_address_reg_updated = 0x00040000,
+	/*!
+	 * SSI Transmit interrupt enable bit
+	 */
+	ssi_tx_interrupt_enable = 0x00080000,
+	/*!
+	 * SSI Transmit DMA enable bit
+	 */
+	ssi_tx_dma_interrupt_enable = 0x00100000,
+	/*!
+	 * SSI Receive interrupt enable bit
+	 */
+	ssi_rx_interrupt_enable = 0x00200000,
+	/*!
+	 * SSI Receive DMA enable bit
+	 */
+	ssi_rx_dma_interrupt_enable = 0x00400000,
+	/*!
+	 * SSI Tx frame complete enable bit on MXC91221 & MXC91311 only
+	 */
+	ssi_tx_frame_complete = 0x00800000,
+	/*!
+	 * SSI Rx frame complete on MXC91221 & MXC91311 only
+	 */
+	ssi_rx_frame_complete = 0x001000000
+} ssi_status_enable_mask;
+
+/*!
+ * This enumeration describes the clock edge to clock in or clock out data.
+ */
+typedef enum {
+	/*!
+	 * Clock on rising edge
+	 */
+	ssi_clock_on_rising_edge = 0,
+	/*!
+	 * Clock on falling edge
+	 */
+	ssi_clock_on_falling_edge = 1
+} ssi_tx_rx_clock_polarity;
+
+/*!
+ * This enumeration describes the clock direction.
+ */
+typedef enum {
+	/*!
+	 * Clock is external
+	 */
+	ssi_tx_rx_externally = 0,
+	/*!
+	 * Clock is generated internally
+	 */
+	ssi_tx_rx_internally = 1
+} ssi_tx_rx_direction;
+
+/*!
+ * This enumeration describes the early frame sync behavior.
+ */
+typedef enum {
+	/*!
+	 * Frame Sync starts on the first data bit
+	 */
+	ssi_frame_sync_first_bit = 0,
+	/*!
+	 * Frame Sync starts one bit before the first data bit
+	 */
+	ssi_frame_sync_one_bit_before = 1
+} ssi_tx_rx_early_frame_sync;
+
+/*!
+ * This enumeration describes the Frame Sync active value.
+ */
+typedef enum {
+	/*!
+	 * Frame Sync is active when high
+	 */
+	ssi_frame_sync_active_high = 0,
+	/*!
+	 * Frame Sync is active when low
+	 */
+	ssi_frame_sync_active_low = 1
+} ssi_tx_rx_frame_sync_active;
+
+/*!
+ * This enumeration describes the Frame Sync active length.
+ */
+typedef enum {
+	/*!
+	 * Frame Sync is active when high
+	 */
+	ssi_frame_sync_one_word = 0,
+	/*!
+	 * Frame Sync is active when low
+	 */
+	ssi_frame_sync_one_bit = 1
+} ssi_tx_rx_frame_sync_length;
+
+/*!
+ * This enumeration describes the Tx/Rx frame shift direction.
+ */
+typedef enum {
+	/*!
+	 * MSB first
+	 */
+	ssi_msb_first = 0,
+	/*!
+	 * LSB first
+	 */
+	ssi_lsb_first = 1
+} ssi_tx_rx_shift_direction;
+
+/*!
+ * This enumeration describes the wait state number.
+ */
+typedef enum {
+	/*!
+	 * 0 wait state
+	 */
+	ssi_waitstates0 = 0x0,
+	/*!
+	 * 1 wait state
+	 */
+	ssi_waitstates1 = 0x1,
+	/*!
+	 * 2 wait states
+	 */
+	ssi_waitstates2 = 0x2,
+	/*!
+	 * 3 wait states
+	 */
+	ssi_waitstates3 = 0x3
+} ssi_wait_states;
+
+/*!
+ * This enumeration describes the word length.
+ */
+typedef enum {
+	/*!
+	 * 2 bits long
+	 */
+	ssi_2_bits = 0x0,
+	/*!
+	 * 4 bits long
+	 */
+	ssi_4_bits = 0x1,
+	/*!
+	 * 6 bits long
+	 */
+	ssi_6_bits = 0x2,
+	/*!
+	 * 8 bits long
+	 */
+	ssi_8_bits = 0x3,
+	/*!
+	 * 10 bits long
+	 */
+	ssi_10_bits = 0x4,
+	/*!
+	 * 12 bits long
+	 */
+	ssi_12_bits = 0x5,
+	/*!
+	 * 14 bits long
+	 */
+	ssi_14_bits = 0x6,
+	/*!
+	 * 16 bits long
+	 */
+	ssi_16_bits = 0x7,
+	/*!
+	 * 18 bits long
+	 */
+	ssi_18_bits = 0x8,
+	/*!
+	 * 20 bits long
+	 */
+	ssi_20_bits = 0x9,
+	/*!
+	 * 22 bits long
+	 */
+	ssi_22_bits = 0xA,
+	/*!
+	 * 24 bits long
+	 */
+	ssi_24_bits = 0xB,
+	/*!
+	 * 26 bits long
+	 */
+	ssi_26_bits = 0xC,
+	/*!
+	 * 28 bits long
+	 */
+	ssi_28_bits = 0xD,
+	/*!
+	 * 30 bits long
+	 */
+	ssi_30_bits = 0xE,
+	/*!
+	 * 32 bits long
+	 */
+	ssi_32_bits = 0xF
+} ssi_word_length;
+
+#endif				/* __MXC_SSI_TYPES_H__ */
diff --git a/drivers/mxc/vpu/Kconfig b/drivers/mxc/vpu/Kconfig
new file mode 100644
index 000000000000..37e55e03d2f2
--- /dev/null
+++ b/drivers/mxc/vpu/Kconfig
@@ -0,0 +1,30 @@
+#
+# Codec configuration
+#
+
+menu "MXC VPU(Video Processing Unit) support"
+
+config MXC_VPU
+	  tristate "Support for MXC VPU(Video Processing Unit)"
+	  depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX5)
+	  default y
+	---help---
+	  The VPU codec device provides codec function for H.264/MPEG4/H.263,
+	  as well as MPEG2/VC-1/DivX on some platforms.
+
+config MXC_VPU_IRAM
+	  tristate "Use IRAM as temporary buffer for VPU to enhance performace"
+	  depends on (ARCH_MX37 || ARCH_MX5)
+	  default y
+	---help---
+	  The VPU can use internal RAM as temporary buffer to save external
+	  memroy bandwith, thus to enhance video performance.
+
+config MXC_VPU_DEBUG
+	bool "MXC VPU debugging"
+	depends on MXC_VPU != n
+	help
+	  This is an option for the developers; most people should
+	  say N here.  This enables MXC VPU driver debugging.
+
+endmenu
diff --git a/drivers/mxc/vpu/Makefile b/drivers/mxc/vpu/Makefile
new file mode 100644
index 000000000000..88e8f2c084a0
--- /dev/null
+++ b/drivers/mxc/vpu/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the VPU drivers.
+#
+
+obj-$(CONFIG_MXC_VPU)                  += vpu.o
+vpu-objs	:= mxc_vpu.o mxc_vl2cc.o
+
+ifeq ($(CONFIG_MXC_VPU_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/mxc/vpu/mxc_vl2cc.c b/drivers/mxc/vpu/mxc_vl2cc.c
new file mode 100644
index 000000000000..acc40dd01689
--- /dev/null
+++ b/drivers/mxc/vpu/mxc_vl2cc.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_vl2cc.c
+ *
+ * @brief VL2CC initialization and flush operation implementation
+ *
+ * @ingroup VL2CC
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#define VL2CC_CTRL_OFFSET	(0x100)
+#define VL2CC_AUXCTRL_OFFSET	(0x104)
+#define VL2CC_INVWAY_OFFSET	(0x77C)
+#define VL2CC_CLEANWAY_OFFSET	(0x7BC)
+
+/*! VL2CC clock handle. */
+static struct clk *vl2cc_clk;
+static u32 *vl2cc_base;
+
+/*!
+ * Initialization function of VL2CC. Remap the VL2CC base address.
+ *
+ * @return status  0 success.
+ */
+int vl2cc_init(u32 vl2cc_hw_base)
+{
+	vl2cc_base = ioremap(vl2cc_hw_base, SZ_8K - 1);
+	if (vl2cc_base == NULL) {
+		printk(KERN_INFO "vl2cc: Unable to ioremap\n");
+		return -ENOMEM;
+	}
+
+	vl2cc_clk = clk_get(NULL, "vl2cc_clk");
+	if (IS_ERR(vl2cc_clk)) {
+		printk(KERN_INFO "vl2cc: Unable to get clock\n");
+		iounmap(vl2cc_base);
+		return -EIO;
+	}
+
+	printk(KERN_INFO "VL2CC initialized\n");
+	return 0;
+}
+
+/*!
+ * Enable VL2CC hardware
+ */
+void vl2cc_enable(void)
+{
+	volatile u32 reg;
+
+	clk_enable(vl2cc_clk);
+
+	/* Disable VL2CC */
+	reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET);
+	reg &= 0xFFFFFFFE;
+	__raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET);
+
+	/* Set the latency for data RAM reads, data RAM writes, tag RAM and
+	 * dirty RAM to 1 cycle - write 0x0 to AUX CTRL [11:0] and also
+	 * configure the number of ways to 8 - write 8 to AUX CTRL [16:13]
+	 */
+	reg = __raw_readl(vl2cc_base + VL2CC_AUXCTRL_OFFSET);
+	reg &= 0xFFFE1000;	/* Clear [16:13] too */
+	reg |= (0x8 << 13);	/* [16:13] = 8; */
+	__raw_writel(reg, vl2cc_base + VL2CC_AUXCTRL_OFFSET);
+
+	/* Invalidate the VL2CC ways - write 0xff to INV BY WAY and poll the
+	 * register until its value is 0x0
+	 */
+	__raw_writel(0xff, vl2cc_base + VL2CC_INVWAY_OFFSET);
+	while (__raw_readl(vl2cc_base + VL2CC_INVWAY_OFFSET) != 0x0) ;
+
+	/* Enable VL2CC */
+	reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET);
+	reg |= 0x1;
+	__raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET);
+}
+
+/*!
+ * Flush VL2CC
+ */
+void vl2cc_flush(void)
+{
+	__raw_writel(0xff, vl2cc_base + VL2CC_CLEANWAY_OFFSET);
+	while (__raw_readl(vl2cc_base + VL2CC_CLEANWAY_OFFSET) != 0x0) ;
+}
+
+/*!
+ * Disable VL2CC
+ */
+void vl2cc_disable(void)
+{
+	__raw_writel(0, vl2cc_base + VL2CC_CTRL_OFFSET);
+	clk_disable(vl2cc_clk);
+}
+
+/*!
+ * Cleanup VL2CC
+ */
+void vl2cc_cleanup(void)
+{
+	clk_put(vl2cc_clk);
+	iounmap(vl2cc_base);
+}
diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c
new file mode 100644
index 000000000000..f62e3d46a67c
--- /dev/null
+++ b/drivers/mxc/vpu/mxc_vpu.c
@@ -0,0 +1,858 @@
+/*
+ * Copyright 2006-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_vpu.c
+ *
+ * @brief VPU system initialization and file operation implementation
+ *
+ * @ingroup VPU
+ */
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/autoconf.h>
+#include <linux/ioport.h>
+#include <linux/stat.h>
+#include <linux/platform_device.h>
+#include <linux/kdev_t.h>
+#include <linux/dma-mapping.h>
+#include <linux/iram_alloc.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/dma-mapping.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+
+#include <mach/mxc_vpu.h>
+
+struct vpu_priv {
+	struct fasync_struct *async_queue;
+};
+
+/* To track the allocated memory buffer */
+typedef struct memalloc_record {
+	struct list_head list;
+	struct vpu_mem_desc mem;
+} memalloc_record;
+
+struct iram_setting {
+	u32 start;
+	u32 end;
+};
+
+static DEFINE_SPINLOCK(vpu_lock);
+static LIST_HEAD(head);
+
+static int vpu_major = 0;
+static int vpu_clk_usercount;
+static struct class *vpu_class;
+static struct vpu_priv vpu_data;
+static u8 open_count = 0;
+static struct clk *vpu_clk;
+static struct vpu_mem_desc bitwork_mem = { 0 };
+static struct vpu_mem_desc pic_para_mem = { 0 };
+static struct vpu_mem_desc user_data_mem = { 0 };
+static struct vpu_mem_desc share_mem = { 0 };
+
+static void __iomem *vpu_base;
+static u32 phy_vpu_base_addr;
+static struct mxc_vpu_platform_data *vpu_plat;
+
+/* IRAM setting */
+static struct iram_setting iram;
+
+/* implement the blocking ioctl */
+static int codec_done = 0;
+static wait_queue_head_t vpu_queue;
+
+static u32 workctrl_regsave[6];
+static u32 rd_ptr_regsave[4];
+static u32 wr_ptr_regsave[4];
+static u32 dis_flag_regsave[4];
+
+#define	READ_REG(x)		__raw_readl(vpu_base + x)
+#define	WRITE_REG(val, x)	__raw_writel(val, vpu_base + x)
+#define	SAVE_WORK_REGS	do {					\
+	int i;							\
+	for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++)	\
+		workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	RESTORE_WORK_REGS	do {				\
+	int i;							\
+	for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++)	\
+		WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	SAVE_CTRL_REGS	do {					\
+	int i;							\
+	for (i = ARRAY_SIZE(workctrl_regsave)/2;		\
+			i < ARRAY_SIZE(workctrl_regsave); i++)		\
+		workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	RESTORE_CTRL_REGS	do {				\
+	int i;							\
+	for (i = ARRAY_SIZE(workctrl_regsave)/2;		\
+			i < ARRAY_SIZE(workctrl_regsave); i++)		\
+		WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	SAVE_RDWR_PTR_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++)		\
+		rd_ptr_regsave[i] = READ_REG(BIT_RD_PTR_REG(i));	\
+	for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++)		\
+		wr_ptr_regsave[i] = READ_REG(BIT_WR_PTR_REG(i));	\
+} while (0)
+#define	RESTORE_RDWR_PTR_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++)		\
+		WRITE_REG(rd_ptr_regsave[i], BIT_RD_PTR_REG(i));	\
+	for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++)		\
+		WRITE_REG(wr_ptr_regsave[i], BIT_WR_PTR_REG(i));	\
+} while (0)
+#define	SAVE_DIS_FLAG_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++)		\
+		dis_flag_regsave[i] = READ_REG(BIT_FRM_DIS_FLG_REG(i));	\
+} while (0)
+#define	RESTORE_DIS_FLAG_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++)		\
+		WRITE_REG(dis_flag_regsave[i], BIT_FRM_DIS_FLG_REG(i));	\
+} while (0)
+
+/*!
+ * Private function to alloc dma buffer
+ * @return status  0 success.
+ */
+static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem)
+{
+	mem->cpu_addr = (unsigned long)
+	    dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
+			       (dma_addr_t *) (&mem->phy_addr),
+			       GFP_DMA | GFP_KERNEL);
+	pr_debug("[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr);
+	if ((void *)(mem->cpu_addr) == NULL) {
+		printk(KERN_ERR "Physical memory allocation error!\n");
+		return -1;
+	}
+	return 0;
+}
+
+/*!
+ * Private function to free dma buffer
+ */
+static void vpu_free_dma_buffer(struct vpu_mem_desc *mem)
+{
+	if (mem->cpu_addr != 0) {
+		dma_free_coherent(0, PAGE_ALIGN(mem->size),
+				  (void *)mem->cpu_addr, mem->phy_addr);
+	}
+}
+
+/*!
+ * Private function to free buffers
+ * @return status  0 success.
+ */
+static int vpu_free_buffers(void)
+{
+	struct memalloc_record *rec, *n;
+	struct vpu_mem_desc mem;
+
+	list_for_each_entry_safe(rec, n, &head, list) {
+		mem = rec->mem;
+		if (mem.cpu_addr != 0) {
+			vpu_free_dma_buffer(&mem);
+			pr_debug("[FREE] freed paddr=0x%08X\n", mem.phy_addr);
+			/* delete from list */
+			list_del(&rec->list);
+			kfree(rec);
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief vpu interrupt handler
+ */
+static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
+{
+	struct vpu_priv *dev = dev_id;
+
+	READ_REG(BIT_INT_STATUS);
+	WRITE_REG(0x1, BIT_INT_CLEAR);
+
+	if (dev->async_queue)
+		kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
+
+	/*
+	 * Clock is gated on when dec/enc started, gate it off when
+	 * interrupt is received.
+	 */
+	clk_disable(vpu_clk);
+
+	codec_done = 1;
+	wake_up_interruptible(&vpu_queue);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * @brief open function for vpu file operation
+ *
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_open(struct inode *inode, struct file *filp)
+{
+	spin_lock(&vpu_lock);
+	if ((open_count++ == 0) && cpu_is_mx32())
+		vl2cc_enable();
+	filp->private_data = (void *)(&vpu_data);
+	spin_unlock(&vpu_lock);
+	return 0;
+}
+
+/*!
+ * @brief IO ctrl function for vpu file operation
+ * @param cmd IO ctrl command
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd,
+		     u_long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case VPU_IOC_PHYMEM_ALLOC:
+		{
+			struct memalloc_record *rec;
+
+			rec = kzalloc(sizeof(*rec), GFP_KERNEL);
+			if (!rec)
+				return -ENOMEM;
+
+			ret = copy_from_user(&(rec->mem),
+					     (struct vpu_mem_desc *)arg,
+					     sizeof(struct vpu_mem_desc));
+			if (ret) {
+				kfree(rec);
+				return -EFAULT;
+			}
+
+			pr_debug("[ALLOC] mem alloc size = 0x%x\n",
+				 rec->mem.size);
+
+			ret = vpu_alloc_dma_buffer(&(rec->mem));
+			if (ret == -1) {
+				kfree(rec);
+				printk(KERN_ERR
+				       "Physical memory allocation error!\n");
+				break;
+			}
+			ret = copy_to_user((void __user *)arg, &(rec->mem),
+					   sizeof(struct vpu_mem_desc));
+			if (ret) {
+				kfree(rec);
+				ret = -EFAULT;
+				break;
+			}
+
+			spin_lock(&vpu_lock);
+			list_add(&rec->list, &head);
+			spin_unlock(&vpu_lock);
+
+			break;
+		}
+	case VPU_IOC_PHYMEM_FREE:
+		{
+			struct memalloc_record *rec, *n;
+			struct vpu_mem_desc vpu_mem;
+
+			ret = copy_from_user(&vpu_mem,
+					     (struct vpu_mem_desc *)arg,
+					     sizeof(struct vpu_mem_desc));
+			if (ret)
+				return -EACCES;
+
+			pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
+				 vpu_mem.cpu_addr);
+			if ((void *)vpu_mem.cpu_addr != NULL) {
+				vpu_free_dma_buffer(&vpu_mem);
+			}
+
+			spin_lock(&vpu_lock);
+			list_for_each_entry_safe(rec, n, &head, list) {
+				if (rec->mem.cpu_addr == vpu_mem.cpu_addr) {
+					/* delete from list */
+					list_del(&rec->list);
+					kfree(rec);
+					break;
+				}
+			}
+			spin_unlock(&vpu_lock);
+
+			break;
+		}
+	case VPU_IOC_WAIT4INT:
+		{
+			u_long timeout = (u_long) arg;
+			if (!wait_event_interruptible_timeout
+			    (vpu_queue, codec_done != 0,
+			     msecs_to_jiffies(timeout))) {
+				printk(KERN_WARNING "VPU blocking: timeout.\n");
+				ret = -ETIME;
+			} else if (signal_pending(current)) {
+				printk(KERN_WARNING
+				       "VPU interrupt received.\n");
+				ret = -ERESTARTSYS;
+			} else
+				codec_done = 0;
+			break;
+		}
+	case VPU_IOC_VL2CC_FLUSH:
+		if (cpu_is_mx32()) {
+			vl2cc_flush();
+		}
+		break;
+	case VPU_IOC_IRAM_SETTING:
+		{
+			ret = copy_to_user((void __user *)arg, &iram,
+					   sizeof(struct iram_setting));
+			if (ret)
+				ret = -EFAULT;
+
+			break;
+		}
+	case VPU_IOC_CLKGATE_SETTING:
+		{
+			u32 clkgate_en;
+
+			if (get_user(clkgate_en, (u32 __user *) arg))
+				return -EFAULT;
+
+			if (clkgate_en) {
+				clk_enable(vpu_clk);
+			} else {
+				clk_disable(vpu_clk);
+			}
+
+			break;
+		}
+	case VPU_IOC_GET_SHARE_MEM:
+		{
+			spin_lock(&vpu_lock);
+			if (share_mem.cpu_addr != 0) {
+				ret = copy_to_user((void __user *)arg,
+						   &share_mem,
+						   sizeof(struct vpu_mem_desc));
+				spin_unlock(&vpu_lock);
+				break;
+			} else {
+				if (copy_from_user(&share_mem,
+						   (struct vpu_mem_desc *)arg,
+						 sizeof(struct vpu_mem_desc))) {
+					spin_unlock(&vpu_lock);
+					return -EFAULT;
+				}
+				if (vpu_alloc_dma_buffer(&share_mem) == -1)
+					ret = -EFAULT;
+				else {
+					if (copy_to_user((void __user *)arg,
+							 &share_mem,
+							 sizeof(struct
+								vpu_mem_desc)))
+						ret = -EFAULT;
+				}
+			}
+			spin_unlock(&vpu_lock);
+			break;
+		}
+	case VPU_IOC_GET_WORK_ADDR:
+		{
+			if (bitwork_mem.cpu_addr != 0) {
+				ret =
+				    copy_to_user((void __user *)arg,
+						 &bitwork_mem,
+						 sizeof(struct vpu_mem_desc));
+				break;
+			} else {
+				if (copy_from_user(&bitwork_mem,
+						   (struct vpu_mem_desc *)arg,
+						   sizeof(struct vpu_mem_desc)))
+					return -EFAULT;
+
+				if (vpu_alloc_dma_buffer(&bitwork_mem) == -1)
+					ret = -EFAULT;
+				else if (copy_to_user((void __user *)arg,
+						      &bitwork_mem,
+						      sizeof(struct
+							     vpu_mem_desc)))
+					ret = -EFAULT;
+			}
+			break;
+		}
+	case VPU_IOC_GET_PIC_PARA_ADDR:
+		{
+			if (pic_para_mem.cpu_addr != 0) {
+				ret =
+				    copy_to_user((void __user *)arg,
+						 &pic_para_mem,
+						 sizeof(struct vpu_mem_desc));
+				break;
+			} else {
+				if (copy_from_user(&pic_para_mem,
+						   (struct vpu_mem_desc *)arg,
+						   sizeof(struct vpu_mem_desc)))
+					return -EFAULT;
+
+				if (vpu_alloc_dma_buffer(&pic_para_mem) == -1)
+					ret = -EFAULT;
+				else if (copy_to_user((void __user *)arg,
+						      &pic_para_mem,
+						      sizeof(struct
+							     vpu_mem_desc)))
+					ret = -EFAULT;
+			}
+			break;
+		}
+	case VPU_IOC_GET_USER_DATA_ADDR:
+		{
+			if (user_data_mem.cpu_addr != 0) {
+				ret =
+				    copy_to_user((void __user *)arg,
+						 &user_data_mem,
+						 sizeof(struct vpu_mem_desc));
+				break;
+			} else {
+				if (copy_from_user(&user_data_mem,
+						   (struct vpu_mem_desc *)arg,
+						   sizeof(struct vpu_mem_desc)))
+					return -EFAULT;
+
+				if (vpu_alloc_dma_buffer(&user_data_mem) == -1)
+					ret = -EFAULT;
+				else if (copy_to_user((void __user *)arg,
+						      &user_data_mem,
+						      sizeof(struct
+							     vpu_mem_desc)))
+					ret = -EFAULT;
+			}
+			break;
+		}
+	case VPU_IOC_SYS_SW_RESET:
+		{
+			if (vpu_plat->reset)
+				vpu_plat->reset();
+
+			break;
+		}
+	case VPU_IOC_REG_DUMP:
+		break;
+	case VPU_IOC_PHYMEM_DUMP:
+		break;
+	default:
+		{
+			printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd);
+			break;
+		}
+	}
+	return ret;
+}
+
+/*!
+ * @brief Release function for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_release(struct inode *inode, struct file *filp)
+{
+	spin_lock(&vpu_lock);
+	if (open_count > 0 && !(--open_count)) {
+		vpu_free_buffers();
+
+		if (cpu_is_mx32())
+			vl2cc_disable();
+
+		/* Free shared memory when vpu device is idle */
+		vpu_free_dma_buffer(&share_mem);
+		share_mem.cpu_addr = 0;
+	}
+	spin_unlock(&vpu_lock);
+
+	return 0;
+}
+
+/*!
+ * @brief fasync function for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_fasync(int fd, struct file *filp, int mode)
+{
+	struct vpu_priv *dev = (struct vpu_priv *)filp->private_data;
+	return fasync_helper(fd, filp, mode, &dev->async_queue);
+}
+
+/*!
+ * @brief memory map function of harware registers for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm)
+{
+	unsigned long pfn;
+
+	vm->vm_flags |= VM_IO | VM_RESERVED;
+	vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
+	pfn = phy_vpu_base_addr >> PAGE_SHIFT;
+	pr_debug("size=0x%x,  page no.=0x%x\n",
+		 (int)(vm->vm_end - vm->vm_start), (int)pfn);
+	return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
+			       vm->vm_page_prot) ? -EAGAIN : 0;
+}
+
+/*!
+ * @brief memory map function of memory for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_map_mem(struct file *fp, struct vm_area_struct *vm)
+{
+	int request_size;
+	request_size = vm->vm_end - vm->vm_start;
+
+	pr_debug(" start=0x%x, pgoff=0x%x, size=0x%x\n",
+		 (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff),
+		 request_size);
+
+	vm->vm_flags |= VM_IO | VM_RESERVED;
+	vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
+
+	return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff,
+			       request_size, vm->vm_page_prot) ? -EAGAIN : 0;
+
+}
+
+/*!
+ * @brief memory map interface for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
+{
+	if (vm->vm_pgoff)
+		return vpu_map_mem(fp, vm);
+	else
+		return vpu_map_hwregs(fp, vm);
+}
+
+struct file_operations vpu_fops = {
+	.owner = THIS_MODULE,
+	.open = vpu_open,
+	.ioctl = vpu_ioctl,
+	.release = vpu_release,
+	.fasync = vpu_fasync,
+	.mmap = vpu_mmap,
+};
+
+/*!
+ * This function is called by the driver framework to initialize the vpu device.
+ * @param   dev The device structure for the vpu passed in by the framework.
+ * @return   0 on success or negative error code on error
+ */
+static int vpu_dev_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct device *temp_class;
+	struct resource *res;
+	unsigned long addr = 0;
+
+	vpu_plat = pdev->dev.platform_data;
+
+	iram_alloc(VPU_IRAM_SIZE, &addr);
+	if (addr == 0)
+		iram.start = iram.end = 0;
+	else {
+		iram.start = addr;
+		iram.end = addr + VPU_IRAM_SIZE - 1;
+	}
+
+	if (cpu_is_mx32()) {
+		err = vl2cc_init(iram.start);
+		if (err != 0)
+			return err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "vpu: unable to get vpu base addr\n");
+		return -ENODEV;
+	}
+	phy_vpu_base_addr = res->start;
+	vpu_base = ioremap(res->start, res->end - res->start);
+
+	vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops);
+	if (vpu_major < 0) {
+		printk(KERN_ERR "vpu: unable to get a major for VPU\n");
+		err = -EBUSY;
+		goto error;
+	}
+
+	vpu_class = class_create(THIS_MODULE, "mxc_vpu");
+	if (IS_ERR(vpu_class)) {
+		err = PTR_ERR(vpu_class);
+		goto err_out_chrdev;
+	}
+
+	temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0),
+				   NULL, "mxc_vpu");
+	if (IS_ERR(temp_class)) {
+		err = PTR_ERR(temp_class);
+		goto err_out_class;
+	}
+
+	vpu_clk = clk_get(&pdev->dev, "vpu_clk");
+	if (IS_ERR(vpu_clk)) {
+		err = -ENOENT;
+		goto err_out_class;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		printk(KERN_ERR "vpu: unable to get vpu interrupt\n");
+		err = -ENXIO;
+		goto err_out_class;
+	}
+
+	err = request_irq(res->start, vpu_irq_handler, 0, "VPU_CODEC_IRQ",
+			  (void *)(&vpu_data));
+	if (err)
+		goto err_out_class;
+
+	printk(KERN_INFO "VPU initialized\n");
+	goto out;
+
+      err_out_class:
+	device_destroy(vpu_class, MKDEV(vpu_major, 0));
+	class_destroy(vpu_class);
+      err_out_chrdev:
+	unregister_chrdev(vpu_major, "mxc_vpu");
+      error:
+	iounmap(vpu_base);
+	if (cpu_is_mx32()) {
+		vl2cc_cleanup();
+	}
+      out:
+	return err;
+}
+
+static int vpu_dev_remove(struct platform_device *pdev)
+{
+	iounmap(vpu_base);
+	iram_free(iram.start, VPU_IRAM_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+	unsigned long timeout;
+
+	/* Wait for vpu go to idle state, suspect vpu cannot be changed
+	   to idle state after about 1 sec */
+	if (open_count > 0) {
+		timeout = jiffies + HZ;
+		clk_enable(vpu_clk);
+		while (READ_REG(BIT_BUSY_FLAG)) {
+			msleep(1);
+			if (time_after(jiffies, timeout))
+				goto out;
+		}
+		clk_disable(vpu_clk);
+	}
+
+	/* Make sure clock is disabled before suspend */
+	vpu_clk_usercount = clk_get_usecount(vpu_clk);
+	for (i = 0; i < vpu_clk_usercount; i++)
+		clk_disable(vpu_clk);
+
+	if (!cpu_is_mx53()) {
+		clk_enable(vpu_clk);
+		if (bitwork_mem.cpu_addr != 0) {
+			SAVE_WORK_REGS;
+			SAVE_CTRL_REGS;
+			SAVE_RDWR_PTR_REGS;
+			SAVE_DIS_FLAG_REGS;
+
+			WRITE_REG(0x1, BIT_BUSY_FLAG);
+			WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND);
+			while (READ_REG(BIT_BUSY_FLAG))
+				;
+		}
+		clk_disable(vpu_clk);
+	}
+
+	if (cpu_is_mx37() || cpu_is_mx51())
+		mxc_pg_enable(pdev);
+
+	return 0;
+
+out:
+	clk_disable(vpu_clk);
+	return -EAGAIN;
+
+}
+
+static int vpu_resume(struct platform_device *pdev)
+{
+	int i;
+
+	if (cpu_is_mx37() || cpu_is_mx51())
+		mxc_pg_disable(pdev);
+
+	if (cpu_is_mx53())
+		goto recover_clk;
+
+	clk_enable(vpu_clk);
+	if (bitwork_mem.cpu_addr != 0) {
+		u32 *p = (u32 *) bitwork_mem.cpu_addr;
+		u32 data;
+		u16 data_hi;
+		u16 data_lo;
+
+		RESTORE_WORK_REGS;
+
+		WRITE_REG(0x0, BIT_RESET_CTRL);
+		WRITE_REG(0x0, BIT_CODE_RUN);
+
+		/*
+		 * Re-load boot code, from the codebuffer in external RAM.
+		 * Thankfully, we only need 4096 bytes, same for all platforms.
+		 */
+		if (cpu_is_mx51()) {
+			for (i = 0; i < 2048; i += 4) {
+				data = p[(i / 2) + 1];
+				data_hi = (data >> 16) & 0xFFFF;
+				data_lo = data & 0xFFFF;
+				WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
+				WRITE_REG(((i + 1) << 16) | data_lo,
+					  BIT_CODE_DOWN);
+
+				data = p[i / 2];
+				data_hi = (data >> 16) & 0xFFFF;
+				data_lo = data & 0xFFFF;
+				WRITE_REG(((i + 2) << 16) | data_hi,
+					  BIT_CODE_DOWN);
+				WRITE_REG(((i + 3) << 16) | data_lo,
+					  BIT_CODE_DOWN);
+			}
+		} else {
+			for (i = 0; i < 2048; i += 2) {
+				if (cpu_is_mx37())
+					data = swab32(p[i / 2]);
+				else
+					data = p[i / 2];
+				data_hi = (data >> 16) & 0xFFFF;
+				data_lo = data & 0xFFFF;
+
+				WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
+				WRITE_REG(((i + 1) << 16) | data_lo,
+					  BIT_CODE_DOWN);
+			}
+		}
+
+		RESTORE_CTRL_REGS;
+
+		WRITE_REG(BITVAL_PIC_RUN, BIT_INT_ENABLE);
+
+		WRITE_REG(0x1, BIT_BUSY_FLAG);
+		WRITE_REG(0x1, BIT_CODE_RUN);
+		while (READ_REG(BIT_BUSY_FLAG)) ;
+
+		RESTORE_RDWR_PTR_REGS;
+		RESTORE_DIS_FLAG_REGS;
+
+		WRITE_REG(0x1, BIT_BUSY_FLAG);
+		WRITE_REG(VPU_WAKE_REG_VALUE, BIT_RUN_COMMAND);
+		while (READ_REG(BIT_BUSY_FLAG)) ;
+	}
+	clk_disable(vpu_clk);
+
+recover_clk:
+	/* Recover vpu clock */
+	for (i = 0; i < vpu_clk_usercount; i++)
+		clk_enable(vpu_clk);
+
+	return 0;
+}
+#else
+#define	vpu_suspend	NULL
+#define	vpu_resume	NULL
+#endif				/* !CONFIG_PM */
+
+/*! Driver definition
+ *
+ */
+static struct platform_driver mxcvpu_driver = {
+	.driver = {
+		   .name = "mxc_vpu",
+		   },
+	.probe = vpu_dev_probe,
+	.remove = vpu_dev_remove,
+	.suspend = vpu_suspend,
+	.resume = vpu_resume,
+};
+
+static int __init vpu_init(void)
+{
+	int ret = platform_driver_register(&mxcvpu_driver);
+
+	init_waitqueue_head(&vpu_queue);
+
+	return ret;
+}
+
+static void __exit vpu_exit(void)
+{
+	free_irq(MXC_INT_VPU, (void *)(&vpu_data));
+	if (vpu_major > 0) {
+		device_destroy(vpu_class, MKDEV(vpu_major, 0));
+		class_destroy(vpu_class);
+		unregister_chrdev(vpu_major, "mxc_vpu");
+		vpu_major = 0;
+	}
+
+	if (cpu_is_mx32()) {
+		vl2cc_cleanup();
+	}
+
+	vpu_free_dma_buffer(&bitwork_mem);
+	vpu_free_dma_buffer(&pic_para_mem);
+	vpu_free_dma_buffer(&user_data_mem);
+
+	clk_put(vpu_clk);
+
+	platform_driver_unregister(&mxcvpu_driver);
+	return;
+}
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC");
+MODULE_LICENSE("GPL");
+
+module_init(vpu_init);
+module_exit(vpu_exit);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5ce7cbabd7a7..28318f4236b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1439,7 +1439,7 @@ config FORCEDETH_NAPI
 config CS89x0
 	tristate "CS89x0 support"
 	depends on NET_ETHERNET && (ISA || EISA || MACH_IXDP2351 \
-		|| ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS)
+		|| ARCH_IXDP2X01 || ARCH_PNX010X || ARCH_MXC)
 	---help---
 	  Support for CS89x0 chipset based Ethernet cards. If you have a
 	  network (Ethernet) card of this type, say Y and read the
@@ -1453,7 +1453,7 @@ config CS89x0
 config CS89x0_NONISA_IRQ
 	def_bool y
 	depends on CS89x0 != n
-	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS
+	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || ARCH_MXC
 
 config TC35815
 	tristate "TOSHIBA TC35815 Ethernet support"
@@ -1875,11 +1875,23 @@ config 68360_ENET
 
 config FEC
 	bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
-	depends on M523x || M527x || M5272 || M528x || M520x || M532x || MACH_MX27 || ARCH_MX35
+	depends on M523x || M527x || M5272 || M528x || M520x || M532x || ARCH_MX25 || MACH_MX27 || ARCH_MX35 || ARCH_MX5 || ARCH_MX28
+	select PHYLIB
 	help
 	  Say Y here if you want to use the built-in 10/100 Fast ethernet
 	  controller on some Motorola ColdFire and Freescale i.MX processors.
 
+config FEC_1588
+	bool "Enable FEC 1588 timestamping"
+	depends on FEC
+
+config FEC_L2SWITCH
+	bool "L2 Switch Ethernet Controller (of ColdFire CPUs)"
+	depends on ARCH_MX28 && !FEC
+	help
+	  Say Y here if you want to use the built-in 10/100 Ethernet Switch
+	  Controller on some Motorola ColdFire processors.
+
 config FEC2
 	bool "Second FEC ethernet controller (on some ColdFire CPUs)"
 	depends on FEC
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ead8cab3cfe1..11bb1b5623bf 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -114,6 +114,8 @@ obj-$(CONFIG_PCMCIA_PCNET) += 8390.o
 obj-$(CONFIG_HP100) += hp100.o
 obj-$(CONFIG_SMC9194) += smc9194.o
 obj-$(CONFIG_FEC) += fec.o
+obj-$(CONFIG_FEC_1588) += fec_1588.o
+obj-$(CONFIG_FEC_L2SWITCH) += fec_switch.o
 obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o
 ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
 	obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 33821a81cbf8..481990fd3f2b 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -84,4 +84,13 @@ config CAN_DEBUG_DEVICES
 	  a problem with CAN support and want to see more of what is going
 	  on.
 
+config CAN_FLEXCAN
+        tristate "Freescale FlexCAN"
+        depends on CAN && (ARCH_MX25 || ARCH_MX35 || ARCH_MX28 || ARCH_MX53)
+        default y
+        ---help---
+          This select the support of Freescale CAN(FlexCAN).
+          This driver can also be built as a module.
+          If unsure, say N.
+
 endmenu
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 523a941b358b..22ea529fb46e 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_CAN_VCAN)		+= vcan.o
+obj-$(CONFIG_CAN_FLEXCAN)	+= flexcan/
 
 obj-$(CONFIG_CAN_DEV)		+= can-dev.o
 can-dev-y			:= dev.o
diff --git a/drivers/net/can/flexcan/Makefile b/drivers/net/can/flexcan/Makefile
new file mode 100644
index 000000000000..b2dbb4fb2793
--- /dev/null
+++ b/drivers/net/can/flexcan/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_CAN_FLEXCAN)	+= flexcan.o
+
+flexcan-y := dev.o drv.o mbm.o
diff --git a/drivers/net/can/flexcan/dev.c b/drivers/net/can/flexcan/dev.c
new file mode 100644
index 000000000000..404877c33eab
--- /dev/null
+++ b/drivers/net/can/flexcan/dev.c
@@ -0,0 +1,732 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dev.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+
+#include <linux/module.h>
+#include <mach/hardware.h>
+#ifdef CONFIG_ARCH_MXS
+#include <mach/device.h>
+#endif
+#include "flexcan.h"
+
+#define DEFAULT_BITRATE	    500000
+#define TIME_SEGMENT_MIN    8
+#define TIME_SEGMENT_MAX    25
+#define TIME_SEGMENT_MID    ((TIME_SEGMENT_MIN + TIME_SEGMENT_MAX)/2)
+
+struct time_segment {
+	char propseg;
+	char pseg1;
+	char pseg2;
+};
+
+struct time_segment time_segments[] = {
+    { /* total 8 timequanta */
+	1, 2, 1
+    },
+    { /* total 9 timequanta */
+	1, 2, 2
+    },
+    { /* total 10 timequanta */
+	2, 2, 2
+    },
+    { /* total 11 timequanta */
+	2, 2, 3
+    },
+    { /* total 12 timequanta */
+	2, 3, 3
+    },
+    { /* total 13 timequanta */
+	3, 3, 3
+    },
+    { /* total 14 timequanta */
+	3, 3, 4
+    },
+    { /* total 15 timequanta */
+	3, 4, 4
+    },
+    { /* total 16 timequanta */
+	4, 4, 4
+    },
+    { /* total 17 timequanta */
+	4, 4, 5
+    },
+    { /* total 18 timequanta */
+	4, 5, 5
+    },
+    { /* total 19 timequanta */
+	5, 5, 5
+    },
+    { /* total 20 timequanta */
+	5, 5, 6
+    },
+    { /* total 21 timequanta */
+	5, 6, 6
+    },
+    { /* total 22 timequanta */
+	6, 6, 6
+    },
+    { /* total 23 timequanta */
+	6, 6, 7
+    },
+    { /* total 24 timequanta */
+	6, 7, 7
+    },
+    { /* total 25 timequanta */
+	7, 7, 7
+    },
+};
+
+enum {
+	FLEXCAN_ATTR_STATE = 0,
+	FLEXCAN_ATTR_BITRATE,
+	FLEXCAN_ATTR_BR_PRESDIV,
+	FLEXCAN_ATTR_BR_RJW,
+	FLEXCAN_ATTR_BR_PROPSEG,
+	FLEXCAN_ATTR_BR_PSEG1,
+	FLEXCAN_ATTR_BR_PSEG2,
+	FLEXCAN_ATTR_BR_CLKSRC,
+	FLEXCAN_ATTR_MAXMB,
+	FLEXCAN_ATTR_XMIT_MAXMB,
+	FLEXCAN_ATTR_FIFO,
+	FLEXCAN_ATTR_WAKEUP,
+	FLEXCAN_ATTR_SRX_DIS,
+	FLEXCAN_ATTR_WAK_SRC,
+	FLEXCAN_ATTR_BCC,
+	FLEXCAN_ATTR_LOCAL_PRIORITY,
+	FLEXCAN_ATTR_ABORT,
+	FLEXCAN_ATTR_LOOPBACK,
+	FLEXCAN_ATTR_SMP,
+	FLEXCAN_ATTR_BOFF_REC,
+	FLEXCAN_ATTR_TSYN,
+	FLEXCAN_ATTR_LISTEN,
+	FLEXCAN_ATTR_EXTEND_MSG,
+	FLEXCAN_ATTR_STANDARD_MSG,
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	FLEXCAN_ATTR_DUMP_REG,
+	FLEXCAN_ATTR_DUMP_XMIT_MB,
+	FLEXCAN_ATTR_DUMP_RX_MB,
+#endif
+	FLEXCAN_ATTR_MAX
+};
+
+static ssize_t flexcan_show_attr(struct device *dev,
+				 struct device_attribute *attr, char *buf);
+static ssize_t flexcan_set_attr(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count);
+
+static struct device_attribute flexcan_dev_attr[FLEXCAN_ATTR_MAX] = {
+	[FLEXCAN_ATTR_STATE] = __ATTR(state, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_BITRATE] =
+	    __ATTR(bitrate, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PRESDIV] =
+	    __ATTR(br_presdiv, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_RJW] =
+	    __ATTR(br_rjw, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PROPSEG] =
+	    __ATTR(br_propseg, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PSEG1] =
+	    __ATTR(br_pseg1, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PSEG2] =
+	    __ATTR(br_pseg2, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_CLKSRC] =
+	    __ATTR(br_clksrc, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_MAXMB] =
+	    __ATTR(maxmb, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_XMIT_MAXMB] =
+	    __ATTR(xmit_maxmb, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_FIFO] =
+	    __ATTR(fifo, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_WAKEUP] =
+	    __ATTR(wakeup, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_SRX_DIS] =
+	    __ATTR(srx_dis, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_WAK_SRC] =
+	    __ATTR(wak_src, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BCC] =
+	    __ATTR(bcc, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LOCAL_PRIORITY] =
+	    __ATTR(local_priority, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_ABORT] =
+	    __ATTR(abort, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LOOPBACK] =
+	    __ATTR(loopback, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_SMP] =
+	    __ATTR(smp, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BOFF_REC] =
+	    __ATTR(boff_rec, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_TSYN] =
+	    __ATTR(tsyn, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LISTEN] =
+	    __ATTR(listen, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_EXTEND_MSG] =
+	    __ATTR(ext_msg, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_STANDARD_MSG] =
+	    __ATTR(std_msg, 0644, flexcan_show_attr, flexcan_set_attr),
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	[FLEXCAN_ATTR_DUMP_REG] =
+	    __ATTR(dump_reg, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_DUMP_XMIT_MB] =
+	    __ATTR(dump_xmit_mb, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_DUMP_RX_MB] =
+	    __ATTR(dump_rx_mb, 0444, flexcan_show_attr, NULL),
+#endif
+};
+
+static void flexcan_set_bitrate(struct flexcan_device *flexcan, int bitrate)
+{
+	/* TODO:: implement in future
+	 * based on the bitrate to get the timing of
+	 * presdiv, pseg1, pseg2, propseg
+	 */
+	int i, rate, div;
+	bool found = false;
+	struct time_segment *segment;
+	rate = clk_get_rate(flexcan->clk);
+
+	if (!bitrate)
+		bitrate = DEFAULT_BITRATE;
+
+	if (rate % bitrate == 0) {
+		div = rate / bitrate;
+		for (i = TIME_SEGMENT_MID; i <= TIME_SEGMENT_MAX; i++) {
+			if (div % i == 0) {
+				found = true;
+				break;
+			}
+		}
+		if (!found) {
+			for (i = TIME_SEGMENT_MID - 1;
+					    i >= TIME_SEGMENT_MIN; i--) {
+				if (div % i == 0) {
+					found = true;
+					break;
+				}
+			}
+
+		}
+	}
+
+	if (found) {
+		segment = &time_segments[i - TIME_SEGMENT_MIN];
+		flexcan->br_presdiv = div/i - 1;
+		flexcan->br_propseg = segment->propseg;
+		flexcan->br_pseg1 = segment->pseg1;
+		flexcan->br_pseg2 = segment->pseg2;
+		flexcan->bitrate = bitrate;
+	} else {
+		pr_info("The bitrate %d can't supported with clock \
+				    rate of %d \n", bitrate, rate);
+	}
+}
+
+static void flexcan_update_bitrate(struct flexcan_device *flexcan)
+{
+	int rate, div;
+
+	if (flexcan->br_clksrc)
+		rate = clk_get_rate(flexcan->clk);
+	else {
+		struct clk *clk;
+		clk = clk_get(NULL, "ckih");
+		if (!clk)
+			return;
+		rate = clk_get_rate(clk);
+		clk_put(clk);
+	}
+	if (!rate)
+		return;
+
+	div = (flexcan->br_presdiv + 1);
+	div *=
+	    (flexcan->br_propseg + flexcan->br_pseg1 + flexcan->br_pseg2 + 4);
+	flexcan->bitrate = (rate + div - 1) / div;
+}
+
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+static int flexcan_dump_reg(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0;
+	unsigned int reg;
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	ret += sprintf(buf + ret, "MCR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	ret += sprintf(buf + ret, "CTRL::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RXGMASK);
+	ret += sprintf(buf + ret, "RXGMASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX14MASK);
+	ret += sprintf(buf + ret, "RX14MASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX15MASK);
+	ret += sprintf(buf + ret, "RX15MASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+	ret += sprintf(buf + ret, "ECR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	ret += sprintf(buf + ret, "ESR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2);
+	ret += sprintf(buf + ret, "IMASK2::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+	ret += sprintf(buf + ret, "IMASK1::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2);
+	ret += sprintf(buf + ret, "IFLAG2::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1);
+	ret += sprintf(buf + ret, "IFLAG1::0x%x\n", reg);
+	return ret;
+}
+
+static int flexcan_dump_xmit_mb(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0, i;
+	i = flexcan->xmit_maxmb + 1;
+	for (; i <= flexcan->maxmb; i++)
+		ret +=
+		    sprintf(buf + ret,
+			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
+			    i, flexcan->hwmb[i].mb_cs,
+			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
+			    flexcan->hwmb[i].mb_data[2]);
+	return ret;
+}
+
+static int flexcan_dump_rx_mb(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0, i;
+	for (i = 0; i <= flexcan->xmit_maxmb; i++)
+		ret +=
+		    sprintf(buf + ret,
+			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
+			    i, flexcan->hwmb[i].mb_cs,
+			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
+			    flexcan->hwmb[i].mb_data[2]);
+	return ret;
+}
+#endif
+
+static ssize_t flexcan_show_state(struct net_device *net, char *buf)
+{
+	int ret, esr;
+	struct flexcan_device *flexcan = netdev_priv(net);
+	ret = sprintf(buf, "%s::", netif_running(net) ? "Start" : "Stop");
+	if (netif_carrier_ok(net)) {
+		esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+		switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) {
+		case 0:
+			ret += sprintf(buf + ret, "normal\n");
+			break;
+		case 1:
+			ret += sprintf(buf + ret, "error passive\n");
+			break;
+		default:
+			ret += sprintf(buf + ret, "bus off\n");
+		}
+	} else
+		ret += sprintf(buf + ret, "bus off\n");
+	return ret;
+}
+
+static ssize_t flexcan_show_attr(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	int attr_id;
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+
+	net = dev_get_drvdata(dev);
+	BUG_ON(!net);
+	flexcan = netdev_priv(net);
+	BUG_ON(!flexcan);
+
+	attr_id = attr - flexcan_dev_attr;
+	switch (attr_id) {
+	case FLEXCAN_ATTR_STATE:
+		return flexcan_show_state(net, buf);
+	case FLEXCAN_ATTR_BITRATE:
+		return sprintf(buf, "%d\n", flexcan->bitrate);
+	case FLEXCAN_ATTR_BR_PRESDIV:
+		return sprintf(buf, "%d\n", flexcan->br_presdiv + 1);
+	case FLEXCAN_ATTR_BR_RJW:
+		return sprintf(buf, "%d\n", flexcan->br_rjw);
+	case FLEXCAN_ATTR_BR_PROPSEG:
+		return sprintf(buf, "%d\n", flexcan->br_propseg + 1);
+	case FLEXCAN_ATTR_BR_PSEG1:
+		return sprintf(buf, "%d\n", flexcan->br_pseg1 + 1);
+	case FLEXCAN_ATTR_BR_PSEG2:
+		return sprintf(buf, "%d\n", flexcan->br_pseg2 + 1);
+	case FLEXCAN_ATTR_BR_CLKSRC:
+		return sprintf(buf, "%s\n", flexcan->br_clksrc ? "bus" : "osc");
+	case FLEXCAN_ATTR_MAXMB:
+		return sprintf(buf, "%d\n", flexcan->maxmb + 1);
+	case FLEXCAN_ATTR_XMIT_MAXMB:
+		return sprintf(buf, "%d\n", flexcan->xmit_maxmb + 1);
+	case FLEXCAN_ATTR_FIFO:
+		return sprintf(buf, "%d\n", flexcan->fifo);
+	case FLEXCAN_ATTR_WAKEUP:
+		return sprintf(buf, "%d\n", flexcan->wakeup);
+	case FLEXCAN_ATTR_SRX_DIS:
+		return sprintf(buf, "%d\n", flexcan->srx_dis);
+	case FLEXCAN_ATTR_WAK_SRC:
+		return sprintf(buf, "%d\n", flexcan->wak_src);
+	case FLEXCAN_ATTR_BCC:
+		return sprintf(buf, "%d\n", flexcan->bcc);
+	case FLEXCAN_ATTR_LOCAL_PRIORITY:
+		return sprintf(buf, "%d\n", flexcan->lprio);
+	case FLEXCAN_ATTR_ABORT:
+		return sprintf(buf, "%d\n", flexcan->abort);
+	case FLEXCAN_ATTR_LOOPBACK:
+		return sprintf(buf, "%d\n", flexcan->loopback);
+	case FLEXCAN_ATTR_SMP:
+		return sprintf(buf, "%d\n", flexcan->smp);
+	case FLEXCAN_ATTR_BOFF_REC:
+		return sprintf(buf, "%d\n", flexcan->boff_rec);
+	case FLEXCAN_ATTR_TSYN:
+		return sprintf(buf, "%d\n", flexcan->tsyn);
+	case FLEXCAN_ATTR_LISTEN:
+		return sprintf(buf, "%d\n", flexcan->listen);
+	case FLEXCAN_ATTR_EXTEND_MSG:
+		return sprintf(buf, "%d\n", flexcan->ext_msg);
+	case FLEXCAN_ATTR_STANDARD_MSG:
+		return sprintf(buf, "%d\n", flexcan->std_msg);
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	case FLEXCAN_ATTR_DUMP_REG:
+		return flexcan_dump_reg(flexcan, buf);
+	case FLEXCAN_ATTR_DUMP_XMIT_MB:
+		return flexcan_dump_xmit_mb(flexcan, buf);
+	case FLEXCAN_ATTR_DUMP_RX_MB:
+		return flexcan_dump_rx_mb(flexcan, buf);
+#endif
+	default:
+		return sprintf(buf, "%s:%p->%p\n", __func__, flexcan_dev_attr,
+			       attr);
+	}
+}
+
+static ssize_t flexcan_set_attr(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count)
+{
+	int attr_id, tmp;
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+
+	net = dev_get_drvdata(dev);
+	BUG_ON(!net);
+	flexcan = netdev_priv(net);
+	BUG_ON(!flexcan);
+
+	attr_id = attr - flexcan_dev_attr;
+
+	if (mutex_lock_interruptible(&flexcan->mutex))
+		return count;
+
+	if (netif_running(net))
+		goto set_finish;
+
+	if (attr_id == FLEXCAN_ATTR_BR_CLKSRC) {
+		if (!strncasecmp(buf, "bus", 3))
+			flexcan->br_clksrc = 1;
+		else if (!strncasecmp(buf, "osc", 3))
+			flexcan->br_clksrc = 0;
+		goto set_finish;
+	}
+
+	tmp = simple_strtoul(buf, NULL, 0);
+	switch (attr_id) {
+	case FLEXCAN_ATTR_BITRATE:
+		flexcan_set_bitrate(flexcan, tmp);
+		break;
+	case FLEXCAN_ATTR_BR_PRESDIV:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PRESDIV)) {
+			flexcan->br_presdiv = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_RJW:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_RJW))
+			flexcan->br_rjw = tmp - 1;
+		break;
+	case FLEXCAN_ATTR_BR_PROPSEG:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PROPSEG)) {
+			flexcan->br_propseg = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_PSEG1:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG1)) {
+			flexcan->br_pseg1 = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_PSEG2:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG2)) {
+			flexcan->br_pseg2 = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_MAXMB:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_MB)) {
+			if (flexcan->maxmb != (tmp - 1)) {
+				flexcan->maxmb = tmp - 1;
+				if (flexcan->xmit_maxmb < flexcan->maxmb)
+					flexcan->xmit_maxmb = flexcan->maxmb;
+			}
+		}
+		break;
+	case FLEXCAN_ATTR_XMIT_MAXMB:
+		if ((tmp > 0) && (tmp <= (flexcan->maxmb + 1))) {
+			if (flexcan->xmit_maxmb != (tmp - 1))
+				flexcan->xmit_maxmb = tmp - 1;
+		}
+		break;
+	case FLEXCAN_ATTR_FIFO:
+		flexcan->fifo = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_WAKEUP:
+		flexcan->wakeup = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_SRX_DIS:
+		flexcan->srx_dis = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_WAK_SRC:
+		flexcan->wak_src = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_BCC:
+		flexcan->bcc = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LOCAL_PRIORITY:
+		flexcan->lprio = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_ABORT:
+		flexcan->abort = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LOOPBACK:
+		flexcan->loopback = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_SMP:
+		flexcan->smp = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_BOFF_REC:
+		flexcan->boff_rec = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_TSYN:
+		flexcan->tsyn = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LISTEN:
+		flexcan->listen = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_EXTEND_MSG:
+		flexcan->ext_msg = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_STANDARD_MSG:
+		flexcan->std_msg = tmp ? 1 : 0;
+		break;
+	}
+      set_finish:
+	mutex_unlock(&flexcan->mutex);
+	return count;
+}
+
+static void flexcan_device_default(struct flexcan_device *dev)
+{
+	struct platform_device *pdev = dev->dev;
+	struct flexcan_platform_data *plat_data = (pdev->dev).platform_data;
+	dev->br_clksrc = plat_data->br_clksrc;
+	dev->br_rjw = plat_data->br_rjw;
+	dev->br_presdiv = plat_data->br_presdiv;
+	dev->br_propseg = plat_data->br_propseg;
+	dev->br_pseg1 = plat_data->br_pseg1;
+	dev->br_pseg2 = plat_data->br_pseg2;
+
+	dev->bcc = plat_data->bcc;
+	dev->srx_dis = plat_data->srx_dis;
+	dev->smp = plat_data->smp;
+	dev->boff_rec = plat_data->boff_rec;
+
+	dev->maxmb = FLEXCAN_MAX_MB - 1;
+	dev->xmit_maxmb = (FLEXCAN_MAX_MB >> 1) - 1;
+	dev->xmit_mb = dev->maxmb - dev->xmit_maxmb;
+
+	dev->ext_msg = plat_data->ext_msg;
+	dev->std_msg = plat_data->std_msg;
+}
+
+static int flexcan_device_attach(struct flexcan_device *flexcan)
+{
+	int ret;
+	struct resource *res;
+	struct platform_device *pdev = flexcan->dev;
+	struct flexcan_platform_data *plat_data = (pdev->dev).platform_data;
+
+	res = platform_get_resource(flexcan->dev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	flexcan->io_base = ioremap(res->start, res->end - res->start + 1);
+	if (!flexcan->io_base)
+		return -ENOMEM;
+
+	flexcan->irq = platform_get_irq(flexcan->dev, 0);
+	if (!flexcan->irq) {
+		ret = -ENODEV;
+		goto no_irq_err;
+	}
+
+	ret = -EINVAL;
+	if (plat_data) {
+		if (plat_data->core_reg) {
+			flexcan->core_reg = regulator_get(&pdev->dev,
+							  plat_data->core_reg);
+			if (!flexcan->core_reg)
+				goto plat_err;
+		}
+
+		if (plat_data->io_reg) {
+			flexcan->io_reg = regulator_get(&pdev->dev,
+							plat_data->io_reg);
+			if (!flexcan->io_reg)
+				goto plat_err;
+		}
+	}
+	flexcan->clk = clk_get(&(flexcan->dev)->dev, "can_clk");
+	flexcan->hwmb = (struct can_hw_mb *)(flexcan->io_base + CAN_MB_BASE);
+	flexcan->rx_mask = (unsigned int *)(flexcan->io_base + CAN_RXMASK_BASE);
+
+	return 0;
+      plat_err:
+	if (flexcan->core_reg) {
+		regulator_put(flexcan->core_reg);
+		flexcan->core_reg = NULL;
+	}
+      no_irq_err:
+	if (flexcan->io_base)
+		iounmap(flexcan->io_base);
+	return ret;
+}
+
+static void flexcan_device_detach(struct flexcan_device *flexcan)
+{
+	if (flexcan->clk) {
+		clk_put(flexcan->clk);
+		flexcan->clk = NULL;
+	}
+
+	if (flexcan->io_reg) {
+		regulator_put(flexcan->io_reg);
+		flexcan->io_reg = NULL;
+	}
+
+	if (flexcan->core_reg) {
+		regulator_put(flexcan->core_reg);
+		flexcan->core_reg = NULL;
+	}
+
+	if (flexcan->io_base)
+		iounmap(flexcan->io_base);
+}
+
+/*!
+ * @brief The function allocates can device.
+ *
+ * @param pdev	the pointer of platform device.
+ * @param setup	the initial function pointer of network device.
+ *
+ * @return none
+ */
+struct net_device *flexcan_device_alloc(struct platform_device *pdev,
+					void (*setup) (struct net_device *dev))
+{
+	struct flexcan_device *flexcan;
+	struct net_device *net;
+	int i, num;
+
+	net = alloc_netdev(sizeof(*flexcan), "can%d", setup);
+	if (net == NULL) {
+		printk(KERN_ERR "Allocate netdevice for FlexCAN fail!\n");
+		return NULL;
+	}
+	flexcan = netdev_priv(net);
+	memset(flexcan, 0, sizeof(*flexcan));
+
+	mutex_init(&flexcan->mutex);
+	init_timer(&flexcan->timer);
+
+	flexcan->dev = pdev;
+	if (flexcan_device_attach(flexcan)) {
+		printk(KERN_ERR "Attach FlexCAN fail!\n");
+		free_netdev(net);
+		return NULL;
+	}
+	flexcan_device_default(flexcan);
+	flexcan_set_bitrate(flexcan, flexcan->bitrate);
+	flexcan_update_bitrate(flexcan);
+
+	num = ARRAY_SIZE(flexcan_dev_attr);
+
+	for (i = 0; i < num; i++) {
+		if (device_create_file(&pdev->dev, flexcan_dev_attr + i)) {
+			printk(KERN_ERR "Create attribute file fail!\n");
+			break;
+		}
+	}
+
+	if (i != num) {
+		for (; i >= 0; i--)
+			device_remove_file(&pdev->dev, flexcan_dev_attr + i);
+		free_netdev(net);
+		return NULL;
+	}
+	dev_set_drvdata(&pdev->dev, net);
+	return net;
+}
+
+/*!
+ * @brief The function frees can device.
+ *
+ * @param pdev	the pointer of platform device.
+ *
+ * @return none
+ */
+void flexcan_device_free(struct platform_device *pdev)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	int i, num;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+
+	unregister_netdev(net);
+	flexcan = netdev_priv(net);
+	del_timer(&flexcan->timer);
+
+	num = ARRAY_SIZE(flexcan_dev_attr);
+
+	for (i = 0; i < num; i++)
+		device_remove_file(&pdev->dev, flexcan_dev_attr + i);
+
+	flexcan_device_detach(netdev_priv(net));
+	free_netdev(net);
+}
diff --git a/drivers/net/can/flexcan/drv.c b/drivers/net/can/flexcan/drv.c
new file mode 100644
index 000000000000..baa0f991c525
--- /dev/null
+++ b/drivers/net/can/flexcan/drv.c
@@ -0,0 +1,631 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drv.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#ifdef CONFIG_ARCH_MXS
+#include <mach/device.h>
+#endif
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include "flexcan.h"
+
+static void flexcan_hw_start(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	if ((flexcan->maxmb + 1) > 32) {
+		__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IMASK1);
+		reg = (1 << (flexcan->maxmb - 31)) - 1;
+		__raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK2);
+	} else {
+		reg = (1 << (flexcan->maxmb + 1)) - 1;
+		__raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK1);
+		__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	}
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_HALT);
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static void flexcan_hw_stop(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_HALT, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static int flexcan_hw_reset(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	int timeout = 100000;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_MDIS, flexcan->io_base + CAN_HW_REG_MCR);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	if (flexcan->br_clksrc)
+		reg |= __CTRL_CLK_SRC;
+	else
+		reg &= ~__CTRL_CLK_SRC;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_MDIS);
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+	reg |= __MCR_SOFT_RST;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	while (reg & __MCR_SOFT_RST) {
+		if (--timeout <= 0) {
+			printk(KERN_ERR "Flexcan software Reset Timeouted\n");
+			return -1;
+		}
+		udelay(10);
+		reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	}
+	return 0;
+}
+
+static inline void flexcan_mcr_setup(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	reg &= ~(__MCR_MAX_MB_MASK | __MCR_WAK_MSK | __MCR_MAX_IDAM_MASK);
+
+	if (flexcan->fifo)
+		reg |= __MCR_FEN;
+	else
+		reg &= ~__MCR_FEN;
+
+	if (flexcan->wakeup)
+		reg |= __MCR_SLF_WAK | __MCR_WAK_MSK;
+	else
+		reg &= ~(__MCR_SLF_WAK | __MCR_WAK_MSK);
+
+	if (flexcan->wak_src)
+		reg |= __MCR_WAK_SRC;
+	else
+		reg &= ~__MCR_WAK_SRC;
+
+	if (flexcan->srx_dis)
+		reg |= __MCR_SRX_DIS;
+	else
+		reg &= ~__MCR_SRX_DIS;
+
+	if (flexcan->bcc)
+		reg |= __MCR_BCC;
+	else
+		reg &= ~__MCR_BCC;
+
+	if (flexcan->lprio)
+		reg |= __MCR_LPRIO_EN;
+	else
+		reg &= ~__MCR_LPRIO_EN;
+
+	if (flexcan->abort)
+		reg |= __MCR_AEN;
+	else
+		reg &= ~__MCR_AEN;
+
+	reg |= (flexcan->maxmb << __MCR_MAX_MB_OFFSET);
+	reg |= __MCR_DOZE | __MCR_MAX_IDAM_C;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static inline void flexcan_ctrl_setup(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	reg &= ~(__CTRL_PRESDIV_MASK | __CTRL_RJW_MASK | __CTRL_PSEG1_MASK |
+		 __CTRL_PSEG2_MASK | __CTRL_PROPSEG_MASK);
+
+	if (flexcan->loopback)
+		reg |= __CTRL_LPB;
+	else
+		reg &= ~__CTRL_LPB;
+
+	if (flexcan->smp)
+		reg |= __CTRL_SMP;
+	else
+		reg &= ~__CTRL_SMP;
+
+	if (flexcan->boff_rec)
+		reg |= __CTRL_BOFF_REC;
+	else
+		reg &= ~__CTRL_BOFF_REC;
+
+	if (flexcan->tsyn)
+		reg |= __CTRL_TSYN;
+	else
+		reg &= ~__CTRL_TSYN;
+
+	if (flexcan->listen)
+		reg |= __CTRL_LOM;
+	else
+		reg &= ~__CTRL_LOM;
+
+	reg |= (flexcan->br_presdiv << __CTRL_PRESDIV_OFFSET) |
+	    (flexcan->br_rjw << __CTRL_RJW_OFFSET) |
+	    (flexcan->br_pseg1 << __CTRL_PSEG1_OFFSET) |
+	    (flexcan->br_pseg2 << __CTRL_PSEG2_OFFSET) |
+	    (flexcan->br_propseg << __CTRL_PROPSEG_OFFSET);
+
+	reg &= ~__CTRL_LBUF;
+
+	reg |= __CTRL_TWRN_MSK | __CTRL_RWRN_MSK | __CTRL_BOFF_MSK |
+	    __CTRL_ERR_MSK;
+
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL);
+}
+
+static int flexcan_hw_restart(struct net_device *dev)
+{
+	unsigned int reg;
+	struct flexcan_device *flexcan = netdev_priv(dev);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	if (reg & __MCR_SOFT_RST)
+		return 1;
+
+	flexcan_mcr_setup(flexcan);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1);
+
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2);
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR);
+
+	flexcan_mbm_init(flexcan);
+	netif_carrier_on(dev);
+	flexcan_hw_start(flexcan);
+
+	if (netif_queue_stopped(dev))
+		netif_start_queue(dev);
+
+	return 0;
+}
+
+static void flexcan_hw_watch(unsigned long data)
+{
+	unsigned int reg, ecr;
+	struct net_device *dev = (struct net_device *)data;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+
+	BUG_ON(!flexcan);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	if (reg & __MCR_MDIS) {
+		if (flexcan_hw_restart(dev))
+			mod_timer(&flexcan->timer, HZ / 20);
+		return;
+	}
+	ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+	if (flexcan->boff_rec) {
+		if (((reg & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) > 1) {
+			reg |= __MCR_SOFT_RST;
+			__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+			mod_timer(&flexcan->timer, HZ / 20);
+			return;
+		}
+		netif_carrier_on(dev);
+	}
+}
+
+static void flexcan_hw_busoff(struct net_device *dev)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	unsigned int reg;
+
+	netif_carrier_off(dev);
+
+	flexcan->timer.function = flexcan_hw_watch;
+	flexcan->timer.data = (unsigned long)dev;
+
+	if (flexcan->boff_rec) {
+		mod_timer(&flexcan->timer, HZ / 10);
+		return;
+	}
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_SOFT_RST, flexcan->io_base + CAN_HW_REG_MCR);
+	mod_timer(&flexcan->timer, HZ / 20);
+}
+
+static int flexcan_hw_open(struct flexcan_device *flexcan)
+{
+	if (flexcan_hw_reset(flexcan))
+		return -EFAULT;
+
+	flexcan_mcr_setup(flexcan);
+	flexcan_ctrl_setup(flexcan);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1);
+
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2);
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR);
+	return 0;
+}
+
+static void flexcan_err_handler(struct net_device *dev)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct sk_buff *skb;
+	struct can_frame *frame;
+	unsigned int esr, ecr;
+
+	esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	__raw_writel(esr & __ESR_INTERRUPTS, flexcan->io_base + CAN_HW_REG_ESR);
+
+	if (esr & __ESR_WAK_INT)
+		return;
+
+	skb = dev_alloc_skb(sizeof(struct can_frame));
+	if (!skb) {
+		printk(KERN_ERR "%s: allocates skb fail in\n", __func__);
+		return;
+	}
+	frame = (struct can_frame *)skb_put(skb, sizeof(*frame));
+	memset(frame, 0, sizeof(*frame));
+	frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL;
+	frame->can_dlc = CAN_ERR_DLC;
+
+	if (esr & __ESR_TWRN_INT)
+		frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+
+	if (esr & __ESR_RWRN_INT)
+		frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+
+	if (esr & __ESR_BOFF_INT)
+		frame->can_id |= CAN_ERR_BUSOFF;
+
+	if (esr & __ESR_ERR_INT) {
+		if (esr & __ESR_BIT1_ERR)
+			frame->data[2] |= CAN_ERR_PROT_BIT1;
+
+		if (esr & __ESR_BIT0_ERR)
+			frame->data[2] |= CAN_ERR_PROT_BIT0;
+
+		if (esr & __ESR_ACK_ERR)
+			frame->can_id |= CAN_ERR_ACK;
+
+		/*TODO:// if (esr & __ESR_CRC_ERR) */
+
+		if (esr & __ESR_FRM_ERR)
+			frame->data[2] |= CAN_ERR_PROT_FORM;
+
+		if (esr & __ESR_STF_ERR)
+			frame->data[2] |= CAN_ERR_PROT_STUFF;
+
+		ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+		switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) {
+		case 0:
+			if (__ECR_TX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+			if (__ECR_RX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+			break;
+		case 1:
+			if (__ECR_TX_ERR_COUNTER(ecr) >=
+			    __ECR_PASSIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+
+			if (__ECR_RX_ERR_COUNTER(ecr) >=
+			    __ECR_PASSIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+			break;
+		default:
+			frame->can_id |= CAN_ERR_BUSOFF;
+		}
+	}
+
+	if (frame->can_id & CAN_ERR_BUSOFF)
+		flexcan_hw_busoff(dev);
+
+	skb->dev = dev;
+	skb->ip_summed = CHECKSUM_UNNECESSARY;
+	netif_receive_skb(skb);
+}
+
+static irqreturn_t flexcan_irq_handler(int irq, void *data)
+{
+	struct net_device *dev = (struct net_device *)data;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+	unsigned int reg;
+
+	BUG_ON(!flexcan);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	if (reg & __ESR_INTERRUPTS) {
+		flexcan_err_handler(dev);
+		return IRQ_HANDLED;
+	}
+
+	flexcan_mbm_isr(dev);
+	return IRQ_HANDLED;
+}
+
+static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct can_frame *frame = (struct can_frame *)skb->data;
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct net_device_stats *stats = &dev->stats;
+
+	BUG_ON(!flexcan);
+
+	if (frame->can_dlc > 8)
+		return -EINVAL;
+
+	if (!flexcan_mbm_xmit(flexcan, frame)) {
+		dev_kfree_skb(skb);
+		stats->tx_bytes += frame->can_dlc;
+		stats->tx_packets++;
+		dev->trans_start = jiffies;
+		return NETDEV_TX_OK;
+	}
+	netif_stop_queue(dev);
+	return NETDEV_TX_BUSY;
+}
+
+static int flexcan_open(struct net_device *dev)
+{
+	struct flexcan_device *flexcan;
+	struct platform_device *pdev;
+	struct flexcan_platform_data *plat_data;
+
+	flexcan = netdev_priv(dev);
+	BUG_ON(!flexcan);
+
+	pdev = flexcan->dev;
+	plat_data = (pdev->dev).platform_data;
+	if (plat_data && plat_data->active)
+		plat_data->active(pdev->id);
+
+	if (flexcan->clk)
+		if (clk_enable(flexcan->clk))
+			goto clk_err;
+
+	if (flexcan->core_reg)
+		if (regulator_enable(flexcan->core_reg))
+			goto core_reg_err;
+
+	if (flexcan->io_reg)
+		if (regulator_enable(flexcan->io_reg))
+			goto io_reg_err;
+
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 1);
+
+	if (request_irq(flexcan->irq, flexcan_irq_handler, IRQF_SAMPLE_RANDOM,
+			dev->name, dev))
+		goto irq_err;
+
+	if (flexcan_hw_open(flexcan))
+		goto open_err;
+
+	flexcan_mbm_init(flexcan);
+	netif_carrier_on(dev);
+	flexcan_hw_start(flexcan);
+	return 0;
+      open_err:
+	free_irq(flexcan->irq, dev);
+      irq_err:
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 0);
+
+	if (flexcan->io_reg)
+		regulator_disable(flexcan->io_reg);
+      io_reg_err:
+	if (flexcan->core_reg)
+		regulator_disable(flexcan->core_reg);
+      core_reg_err:
+	if (flexcan->clk)
+		clk_disable(flexcan->clk);
+      clk_err:
+	if (plat_data && plat_data->inactive)
+		plat_data->inactive(pdev->id);
+	return -ENODEV;
+}
+
+static int flexcan_stop(struct net_device *dev)
+{
+	struct flexcan_device *flexcan;
+	struct platform_device *pdev;
+	struct flexcan_platform_data *plat_data;
+
+	flexcan = netdev_priv(dev);
+
+	BUG_ON(!flexcan);
+
+	pdev = flexcan->dev;
+	plat_data = (pdev->dev).platform_data;
+
+	flexcan_hw_stop(flexcan);
+
+	free_irq(flexcan->irq, dev);
+
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 0);
+
+	if (flexcan->io_reg)
+		regulator_disable(flexcan->io_reg);
+	if (flexcan->core_reg)
+		regulator_disable(flexcan->core_reg);
+	if (flexcan->clk)
+		clk_disable(flexcan->clk);
+	if (plat_data && plat_data->inactive)
+		plat_data->inactive(pdev->id);
+	return 0;
+}
+
+static struct net_device_ops flexcan_netdev_ops = {
+	.ndo_open = flexcan_open,
+	.ndo_stop = flexcan_stop,
+	.ndo_start_xmit = flexcan_start_xmit,
+};
+
+static void flexcan_setup(struct net_device *dev)
+{
+	dev->type = ARPHRD_CAN;
+	dev->mtu = sizeof(struct can_frame);
+	dev->hard_header_len = 0;
+	dev->addr_len = 0;
+	dev->tx_queue_len = FLEXCAN_MAX_MB;
+	dev->flags = IFF_NOARP;
+	dev->features = NETIF_F_NO_CSUM;
+
+	dev->netdev_ops = &flexcan_netdev_ops;
+}
+
+static int flexcan_probe(struct platform_device *pdev)
+{
+	struct net_device *net;
+	net = flexcan_device_alloc(pdev, flexcan_setup);
+	if (!net)
+		return -ENOMEM;
+
+	if (register_netdev(net)) {
+		flexcan_device_free(pdev);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int flexcan_remove(struct platform_device *pdev)
+{
+	flexcan_device_free(pdev);
+	return 0;
+}
+
+static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	struct flexcan_platform_data *plat_data;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+	flexcan = netdev_priv(net);
+
+	BUG_ON(!flexcan);
+
+	if (!(net->flags & IFF_UP))
+		return 0;
+	if (flexcan->wakeup)
+		set_irq_wake(flexcan->irq, 1);
+	else {
+		plat_data = (pdev->dev).platform_data;
+
+		if (plat_data && plat_data->xcvr_enable)
+			plat_data->xcvr_enable(pdev->id, 0);
+
+		if (flexcan->io_reg)
+			regulator_disable(flexcan->io_reg);
+		if (flexcan->core_reg)
+			regulator_disable(flexcan->core_reg);
+		if (flexcan->clk)
+			clk_disable(flexcan->clk);
+		if (plat_data && plat_data->inactive)
+			plat_data->inactive(pdev->id);
+	}
+	return 0;
+}
+
+static int flexcan_resume(struct platform_device *pdev)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	struct flexcan_platform_data *plat_data;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+	flexcan = netdev_priv(net);
+
+	BUG_ON(!flexcan);
+
+	if (!(net->flags & IFF_UP))
+		return 0;
+
+	if (flexcan->wakeup)
+		set_irq_wake(flexcan->irq, 0);
+	else {
+		plat_data = (pdev->dev).platform_data;
+		if (plat_data && plat_data->active)
+			plat_data->active(pdev->id);
+
+		if (flexcan->clk) {
+			if (clk_enable(flexcan->clk))
+				printk(KERN_ERR "%s:enable clock fail\n",
+				       __func__);
+		}
+
+		if (flexcan->core_reg) {
+			if (regulator_enable(flexcan->core_reg))
+				printk(KERN_ERR "%s:enable core voltage\n",
+				       __func__);
+		}
+		if (flexcan->io_reg) {
+			if (regulator_enable(flexcan->io_reg))
+				printk(KERN_ERR "%s:enable io voltage\n",
+				       __func__);
+		}
+
+		if (plat_data && plat_data->xcvr_enable)
+			plat_data->xcvr_enable(pdev->id, 1);
+	}
+	return 0;
+}
+
+static struct platform_driver flexcan_driver = {
+	.driver = {
+		   .name = FLEXCAN_DEVICE_NAME,
+		   },
+	.probe = flexcan_probe,
+	.remove = flexcan_remove,
+	.suspend = flexcan_suspend,
+	.resume = flexcan_resume,
+};
+
+static __init int flexcan_init(void)
+{
+	pr_info("Freescale FlexCAN Driver \n");
+	return platform_driver_register(&flexcan_driver);
+}
+
+static __exit void flexcan_exit(void)
+{
+	return platform_driver_unregister(&flexcan_driver);
+}
+
+module_init(flexcan_init);
+module_exit(flexcan_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/can/flexcan/flexcan.h b/drivers/net/can/flexcan/flexcan.h
new file mode 100644
index 000000000000..51a800bd8e55
--- /dev/null
+++ b/drivers/net/can/flexcan/flexcan.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file flexcan.h
+ *
+ * @brief FlexCan definitions.
+ *
+ * @ingroup can
+ */
+
+#ifndef __CAN_FLEXCAN_H__
+#define __CAN_FLEXCAN_H__
+
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/can.h>
+#include <linux/can/core.h>
+#include <linux/can/error.h>
+
+#define FLEXCAN_DEVICE_NAME	"FlexCAN"
+
+#define CAN_MB_RX_INACTIVE	0x0
+#define CAN_MB_RX_EMPTY		0x4
+#define CAN_MB_RX_FULL		0x2
+#define CAN_MB_RX_OVERRUN	0x6
+#define CAN_MB_RX_BUSY		0x1
+
+#define CAN_MB_TX_INACTIVE	0x8
+#define CAN_MB_TX_ABORT		0x9
+#define CAN_MB_TX_ONCE		0xC
+#define CAN_MB_TX_REMOTE	0xA
+
+struct can_hw_mb {
+	unsigned int mb_cs;
+	unsigned int mb_id;
+	unsigned char mb_data[8];
+};
+
+#define MB_CS_CODE_OFFSET	24
+#define MB_CS_CODE_MASK		(0xF << MB_CS_CODE_OFFSET)
+#define MB_CS_SRR_OFFSET	22
+#define MB_CS_SRR_MASK		(0x1 << MB_CS_SRR_OFFSET)
+#define MB_CS_IDE_OFFSET	21
+#define MB_CS_IDE_MASK		(0x1 << MB_CS_IDE_OFFSET)
+#define MB_CS_RTR_OFFSET	20
+#define MB_CS_RTR_MASK		(0x1 << MB_CS_RTR_OFFSET)
+#define MB_CS_LENGTH_OFFSET	16
+#define MB_CS_LENGTH_MASK	(0xF << MB_CS_LENGTH_OFFSET)
+#define MB_CS_TIMESTAMP_OFFSET	0
+#define MB_CS_TIMESTAMP_MASK	(0xFF << MB_CS_TIMESTAMP_OFFSET)
+
+#define CAN_HW_REG_MCR		0x00
+#define CAN_HW_REG_CTRL		0x04
+#define CAN_HW_REG_TIMER	0x08
+#define CAN_HW_REG_RXGMASK	0x10
+#define CAN_HW_REG_RX14MASK	0x14
+#define CAN_HW_REG_RX15MASK	0x18
+#define CAN_HW_REG_ECR		0x1C
+#define CAN_HW_REG_ESR		0x20
+#define CAN_HW_REG_IMASK2	0x24
+#define CAN_HW_REG_IMASK1	0x28
+#define CAN_HW_REG_IFLAG2	0x2C
+#define CAN_HW_REG_IFLAG1	0x30
+
+#define CAN_MB_BASE	0x0080
+#define CAN_RXMASK_BASE	0x0880
+#define CAN_FIFO_BASE	0xE0
+
+#define __MCR_MDIS		(1 << 31)
+#define __MCR_FRZ		(1 << 30)
+#define __MCR_FEN		(1 << 29)
+#define __MCR_HALT		(1 << 28)
+#define __MCR_NOTRDY		(1 << 27)
+#define __MCR_WAK_MSK		(1 << 26)
+#define __MCR_SOFT_RST		(1 << 25)
+#define __MCR_FRZ_ACK		(1 << 24)
+#define __MCR_SLF_WAK		(1 << 22)
+#define __MCR_WRN_EN		(1 << 21)
+#define __MCR_LPM_ACK		(1 << 20)
+#define __MCR_WAK_SRC		(1 << 19)
+#define __MCR_DOZE		(1 << 18)
+#define __MCR_SRX_DIS		(1 << 17)
+#define __MCR_BCC		(1 << 16)
+#define __MCR_LPRIO_EN		(1 << 13)
+#define __MCR_AEN		(1 << 12)
+#define __MCR_MAX_IDAM_OFFSET 	8
+#define __MCR_MAX_IDAM_MASK 	(0x3 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_A	(0x0 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_B	(0x1 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_C	(0x2 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_D	(0x3 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_MB_OFFSET 	0
+#define __MCR_MAX_MB_MASK 	(0x3F)
+
+#define __CTRL_PRESDIV_OFFSET	24
+#define __CTRL_PRESDIV_MASK	(0xFF << __CTRL_PRESDIV_OFFSET)
+#define __CTRL_RJW_OFFSET	22
+#define __CTRL_RJW_MASK		(0x3 << __CTRL_RJW_OFFSET)
+#define __CTRL_PSEG1_OFFSET	19
+#define __CTRL_PSEG1_MASK	(0x7 << __CTRL_PSEG1_OFFSET)
+#define __CTRL_PSEG2_OFFSET	16
+#define __CTRL_PSEG2_MASK	(0x7 << __CTRL_PSEG2_OFFSET)
+#define __CTRL_BOFF_MSK		(0x1 << 15)
+#define __CTRL_ERR_MSK		(0x1 << 14)
+#define __CTRL_CLK_SRC		(0x1 << 13)
+#define __CTRL_LPB		(0x1 << 12)
+#define __CTRL_TWRN_MSK		(0x1 << 11)
+#define __CTRL_RWRN_MSK		(0x1 << 10)
+#define __CTRL_SMP		(0x1 << 7)
+#define __CTRL_BOFF_REC		(0x1 << 6)
+#define __CTRL_TSYN		(0x1 << 5)
+#define __CTRL_LBUF		(0x1 << 4)
+#define __CTRL_LOM		(0x1 << 3)
+#define __CTRL_PROPSEG_OFFSET	0
+#define __CTRL_PROPSEG_MASK	(0x7)
+
+#define __ECR_TX_ERR_COUNTER(x) ((x) & 0xFF)
+#define __ECR_RX_ERR_COUNTER(x) (((x) >> 8) & 0xFF)
+#define __ECR_PASSIVE_THRESHOLD	128
+#define __ECR_ACTIVE_THRESHOLD	96
+
+#define __ESR_TWRN_INT		(0x1 << 17)
+#define __ESR_RWRN_INT		(0x1 << 16)
+#define __ESR_BIT1_ERR		(0x1 << 15)
+#define __ESR_BIT0_ERR		(0x1 << 14)
+#define __ESR_ACK_ERR		(0x1 << 13)
+#define __ESR_CRC_ERR		(0x1 << 12)
+#define __ESR_FRM_ERR		(0x1 << 11)
+#define __ESR_STF_ERR		(0x1 << 10)
+#define __ESR_TX_WRN		(0x1 << 9)
+#define __ESR_RX_WRN		(0x1 << 8)
+#define __ESR_IDLE		(0x1 << 7)
+#define __ESR_TXRX		(0x1 << 6)
+#define __ESR_FLT_CONF_OFF	4
+#define __ESR_FLT_CONF_MASK	(0x3 << __ESR_FLT_CONF_OFF)
+#define __ESR_BOFF_INT		(0x1 << 2)
+#define __ESR_ERR_INT		(0x1 << 1)
+#define __ESR_WAK_INT		(0x1)
+
+#define __ESR_INTERRUPTS	(__ESR_WAK_INT | __ESR_ERR_INT | \
+				__ESR_BOFF_INT | __ESR_TWRN_INT | \
+				__ESR_RWRN_INT)
+
+#define __FIFO_OV_INT		0x0080
+#define __FIFO_WARN_INT		0x0040
+#define __FIFO_RDY_INT		0x0020
+
+struct flexcan_device {
+	struct mutex mutex;
+	void *io_base;
+	struct can_hw_mb *hwmb;
+	unsigned int *rx_mask;
+	unsigned int xmit_mb;
+	unsigned int bitrate;
+	/* word 1 */
+	unsigned int br_presdiv:8;
+	unsigned int br_rjw:2;
+	unsigned int br_propseg:3;
+	unsigned int br_pseg1:3;
+	unsigned int br_pseg2:3;
+	unsigned int maxmb:6;
+	unsigned int xmit_maxmb:6;
+	unsigned int wd1_resv:1;
+
+	/* word 2 */
+	unsigned int fifo:1;
+	unsigned int wakeup:1;
+	unsigned int srx_dis:1;
+	unsigned int wak_src:1;
+	unsigned int bcc:1;
+	unsigned int lprio:1;
+	unsigned int abort:1;
+	unsigned int br_clksrc:1;
+	unsigned int loopback:1;
+	unsigned int smp:1;
+	unsigned int boff_rec:1;
+	unsigned int tsyn:1;
+	unsigned int listen:1;
+
+	unsigned int ext_msg:1;
+	unsigned int std_msg:1;
+
+	struct timer_list timer;
+	struct platform_device *dev;
+	struct regulator *core_reg;
+	struct regulator *io_reg;
+	struct clk *clk;
+	int irq;
+};
+
+#define FLEXCAN_MAX_FIFO_MB	8
+#define FLEXCAN_MAX_MB		64
+#define FLEXCAN_MAX_PRESDIV	256
+#define FLEXCAN_MAX_RJW		4
+#define FLEXCAN_MAX_PSEG1	8
+#define FLEXCAN_MAX_PSEG2	8
+#define FLEXCAN_MAX_PROPSEG	8
+#define FLEXCAN_MAX_BITRATE	1000000
+
+extern struct net_device *flexcan_device_alloc(struct platform_device *pdev,
+					       void (*setup) (struct net_device
+							      *dev));
+extern void flexcan_device_free(struct platform_device *pdev);
+
+extern void flexcan_mbm_init(struct flexcan_device *flexcan);
+extern void flexcan_mbm_isr(struct net_device *dev);
+extern int flexcan_mbm_xmit(struct flexcan_device *flexcan,
+			    struct can_frame *frame);
+#endif				/* __CAN_FLEXCAN_H__ */
diff --git a/drivers/net/can/flexcan/mbm.c b/drivers/net/can/flexcan/mbm.c
new file mode 100644
index 000000000000..c846d97daadb
--- /dev/null
+++ b/drivers/net/can/flexcan/mbm.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mbm.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include "flexcan.h"
+
+#define flexcan_swab32(x)	\
+	(((x) << 24) | ((x) >> 24) |\
+		(((x) & (__u32)0x0000ff00UL) << 8) |\
+		(((x) & (__u32)0x00ff0000UL) >> 8))
+
+static inline void flexcan_memcpy(void *dst, void *src, int len)
+{
+	int i;
+	unsigned int *d = (unsigned int *)dst, *s = (unsigned int *)src;
+	len = (len + 3) >> 2;
+	for (i = 0; i < len; i++, s++, d++)
+		*d = flexcan_swab32(*s);
+}
+
+static void flexcan_mb_bottom(struct net_device *dev, int index)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct net_device_stats *stats = &dev->stats;
+	struct can_hw_mb *hwmb;
+	struct can_frame *frame;
+	struct sk_buff *skb;
+	unsigned int tmp;
+
+	hwmb = flexcan->hwmb + index;
+	if (flexcan->fifo || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+		if ((hwmb->mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET ==
+							CAN_MB_TX_ABORT) {
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+		}
+
+		if (hwmb->mb_cs & (CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET)) {
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+			return;
+		}
+	}
+	skb = dev_alloc_skb(sizeof(struct can_frame));
+	if (skb) {
+		frame = (struct can_frame *)skb_put(skb, sizeof(*frame));
+		memset(frame, 0, sizeof(*frame));
+		if (hwmb->mb_cs & MB_CS_IDE_MASK)
+			frame->can_id =
+			    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+		else
+			frame->can_id = (hwmb->mb_id >> 18) & CAN_SFF_MASK;
+
+		if (hwmb->mb_cs & MB_CS_RTR_MASK)
+			frame->can_id |= CAN_RTR_FLAG;
+
+		frame->can_dlc =
+		(hwmb->mb_cs & MB_CS_LENGTH_MASK) >> MB_CS_LENGTH_OFFSET;
+
+		if (frame->can_dlc && frame->can_dlc)
+			flexcan_memcpy(frame->data, hwmb->mb_data,
+				       frame->can_dlc);
+
+		if (flexcan->fifo
+		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+		}
+
+		tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+
+		dev->last_rx = jiffies;
+		stats->rx_packets++;
+		stats->rx_bytes += frame->can_dlc;
+
+		skb->dev = dev;
+		skb->protocol = __constant_htons(ETH_P_CAN);
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+		netif_rx(skb);
+	} else {
+		tmp = hwmb->mb_cs;
+		tmp = hwmb->mb_id;
+		tmp = hwmb->mb_data[0];
+		if (flexcan->fifo
+		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+			hwmb->mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+		}
+		tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+		stats->rx_dropped++;
+	}
+}
+
+static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1)
+{
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+	struct net_device_stats *stats = &dev->stats;
+	struct sk_buff *skb;
+	struct can_hw_mb *hwmb = flexcan->hwmb;
+	struct can_frame *frame;
+	unsigned int tmp;
+
+	if (iflag1 & __FIFO_RDY_INT) {
+		skb = dev_alloc_skb(sizeof(struct can_frame));
+		if (skb) {
+			frame =
+			    (struct can_frame *)skb_put(skb, sizeof(*frame));
+			memset(frame, 0, sizeof(*frame));
+			if (hwmb->mb_cs & MB_CS_IDE_MASK)
+				frame->can_id =
+				    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+			else
+				frame->can_id =
+				    (hwmb->mb_id >> 18) & CAN_SFF_MASK;
+
+			if (hwmb->mb_cs & MB_CS_RTR_MASK)
+				frame->can_id |= CAN_RTR_FLAG;
+
+			frame->can_dlc =
+				(hwmb->mb_cs & MB_CS_LENGTH_MASK) >>
+						MB_CS_LENGTH_OFFSET;
+
+			if (frame->can_dlc && (frame->can_dlc <= 8))
+				flexcan_memcpy(frame->data, hwmb->mb_data,
+					       frame->can_dlc);
+			tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+
+			dev->last_rx = jiffies;
+
+			stats->rx_packets++;
+			stats->rx_bytes += frame->can_dlc;
+
+			skb->dev = dev;
+			skb->protocol = __constant_htons(ETH_P_CAN);
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			netif_rx(skb);
+		} else {
+			tmp = hwmb->mb_cs;
+			tmp = hwmb->mb_id;
+			tmp = hwmb->mb_data[0];
+			tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+		}
+	}
+
+	if (iflag1 & (__FIFO_OV_INT | __FIFO_WARN_INT)) {
+		skb = dev_alloc_skb(sizeof(struct can_frame));
+		if (skb) {
+			frame =
+			    (struct can_frame *)skb_put(skb, sizeof(*frame));
+			memset(frame, 0, sizeof(*frame));
+			frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL;
+			frame->can_dlc = CAN_ERR_DLC;
+			if (iflag1 & __FIFO_WARN_INT)
+				frame->data[1] |=
+				    CAN_ERR_CRTL_TX_WARNING |
+				    CAN_ERR_CRTL_RX_WARNING;
+			if (iflag1 & __FIFO_OV_INT)
+				frame->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
+
+			skb->dev = dev;
+			skb->protocol = __constant_htons(ETH_P_CAN);
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			netif_rx(skb);
+		}
+	}
+}
+
+/*!
+ * @brief The function call by CAN ISR to handle mb events.
+ *
+ * @param dev		the pointer of network device.
+ *
+ * @return none
+ */
+void flexcan_mbm_isr(struct net_device *dev)
+{
+	int i, iflag1, iflag2, maxmb;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+
+	if (flexcan->maxmb > 31) {
+		maxmb = flexcan->maxmb + 1 - 32;
+		iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+		iflag2 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2);
+		iflag2 &= (1 << maxmb) - 1;
+		maxmb = 32;
+	} else {
+		maxmb = flexcan->maxmb + 1;
+		iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+		iflag1 &= (1 << maxmb) - 1;
+		iflag2 = 0;
+	}
+
+	__raw_writel(iflag1, flexcan->io_base + CAN_HW_REG_IFLAG1);
+	__raw_writel(iflag2, flexcan->io_base + CAN_HW_REG_IFLAG2);
+
+	if (flexcan->fifo) {
+		flexcan_fifo_isr(dev, iflag1);
+		iflag1 &= 0xFFFFFF00;
+	}
+	for (i = 0; iflag1 && (i < maxmb); i++) {
+		if (iflag1 & (1 << i)) {
+			iflag1 &= ~(1 << i);
+			flexcan_mb_bottom(dev, i);
+		}
+	}
+
+	for (i = maxmb; iflag2 && (i <= flexcan->maxmb); i++) {
+		if (iflag2 & (1 << (i - 32))) {
+			iflag2 &= ~(1 << (i - 32));
+			flexcan_mb_bottom(dev, i);
+		}
+	}
+}
+
+/*!
+ * @brief function to xmit message buffer
+ *
+ * @param flexcan	the pointer of can hardware device.
+ * @param frame		the pointer of can message frame.
+ *
+ * @return	Returns 0 if xmit is success. otherwise returns non-zero.
+ */
+int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame)
+{
+	int i = flexcan->xmit_mb;
+	struct can_hw_mb *hwmb = flexcan->hwmb;
+
+	do {
+		if ((hwmb[i].mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET ==
+							    CAN_MB_TX_INACTIVE)
+			break;
+		if ((++i) > flexcan->maxmb) {
+			if (flexcan->fifo)
+				i = FLEXCAN_MAX_FIFO_MB;
+			else
+				i = flexcan->xmit_maxmb + 1;
+		}
+		if (i == flexcan->xmit_mb)
+			return -1;
+	} while (1);
+
+	flexcan->xmit_mb = i + 1;
+	if (flexcan->xmit_mb > flexcan->maxmb) {
+		if (flexcan->fifo)
+			flexcan->xmit_mb = FLEXCAN_MAX_FIFO_MB;
+		else
+			flexcan->xmit_mb = flexcan->xmit_maxmb + 1;
+	}
+
+	if (frame->can_id & CAN_RTR_FLAG)
+		hwmb[i].mb_cs |= 1 << MB_CS_RTR_OFFSET;
+	else
+		hwmb[i].mb_cs &= ~MB_CS_RTR_MASK;
+
+	if (frame->can_id & CAN_EFF_FLAG) {
+		hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET;
+		hwmb[i].mb_cs |= 1 << MB_CS_SRR_OFFSET;
+		hwmb[i].mb_id = frame->can_id & CAN_EFF_MASK;
+	} else {
+		hwmb[i].mb_cs &= ~MB_CS_IDE_MASK;
+		hwmb[i].mb_id = (frame->can_id & CAN_SFF_MASK) << 18;
+	}
+
+	hwmb[i].mb_cs &= ~MB_CS_LENGTH_MASK;
+	hwmb[i].mb_cs |= frame->can_dlc << MB_CS_LENGTH_OFFSET;
+	flexcan_memcpy(hwmb[i].mb_data, frame->data, frame->can_dlc);
+	hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+	hwmb[i].mb_cs |= CAN_MB_TX_ONCE << MB_CS_CODE_OFFSET;
+	return 0;
+}
+
+/*!
+ * @brief function to initial message buffer
+ *
+ * @param flexcan	the pointer of can hardware device.
+ *
+ * @return	none
+ */
+void flexcan_mbm_init(struct flexcan_device *flexcan)
+{
+	struct can_hw_mb *hwmb;
+	int rx_mb, i;
+
+	/* Set global mask to receive all messages */
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RXGMASK);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RX14MASK);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RX15MASK);
+
+	memset(flexcan->hwmb, 0, sizeof(*hwmb) * FLEXCAN_MAX_MB);
+	/* Set individual mask to receive all messages */
+	memset(flexcan->rx_mask, 0, sizeof(unsigned int) * FLEXCAN_MAX_MB);
+
+	if (flexcan->fifo)
+		rx_mb = FLEXCAN_MAX_FIFO_MB;
+	else
+		rx_mb = flexcan->maxmb - flexcan->xmit_maxmb;
+
+	hwmb = flexcan->hwmb;
+	if (flexcan->fifo) {
+		unsigned long *id_table = flexcan->io_base + CAN_FIFO_BASE;
+		for (i = 0; i < rx_mb; i++)
+			id_table[i] = 0;
+	} else {
+		for (i = 0; i < rx_mb; i++) {
+			hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+			hwmb[i].mb_cs |= CAN_MB_RX_EMPTY << MB_CS_CODE_OFFSET;
+			/*
+			 * IDE bit can not control by mask registers
+			 * So set message buffer to receive extend
+			 * or standard message.
+			 */
+			if (flexcan->ext_msg && flexcan->std_msg) {
+				hwmb[i].mb_cs &= ~MB_CS_IDE_MASK;
+				hwmb[i].mb_cs |= (i & 1) << MB_CS_IDE_OFFSET;
+			} else {
+				if (flexcan->ext_msg)
+					hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET;
+			}
+		}
+	}
+
+	for (; i <= flexcan->maxmb; i++) {
+		hwmb[i].mb_cs &= ~MB_CS_CODE_MASK;
+		hwmb[i].mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET;
+	}
+
+	flexcan->xmit_mb = rx_mb;
+}
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index 55445f980f9c..523cbf0cb07c 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -189,12 +189,17 @@ static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0};
 #define CIRRUS_DEFAULT_IRQ	VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */
 static unsigned int netcard_portlist[] __used __initdata = {CIRRUS_DEFAULT_BASE, 0};
 static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0};
-#elif defined(CONFIG_MACH_MX31ADS)
-#include <mach/board-mx31ads.h>
-static unsigned int netcard_portlist[] __used __initdata = {
-	PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300, 0
-};
-static unsigned cs8900_irq_map[] = {EXPIO_INT_ENET_INT, 0, 0, 0};
+#elif defined(CONFIG_ARCH_MXC)
+/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus
+ * Add 3 to reset the page window before probing (fixes eth probe when deployed
+ * using nand_boot)
+ */
+extern unsigned int netcard_portlist[2];
+/*!
+ * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt
+ * pin 0 is used for interrupt generation.
+ */
+extern unsigned int cs8900_irq_map[4];
 #else
 static unsigned int netcard_portlist[] __used __initdata =
    { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
@@ -1034,7 +1039,7 @@ skip_this_frame:
 
 static void __init reset_chip(struct net_device *dev)
 {
-#if !defined(CONFIG_MACH_MX31ADS)
+#if !defined(CONFIG_ARCH_MXC)
 #if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01)
 	struct net_local *lp = netdev_priv(dev);
 	int ioaddr = dev->base_addr;
@@ -1063,7 +1068,7 @@ static void __init reset_chip(struct net_device *dev)
 	reset_start_time = jiffies;
 	while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2)
 		;
-#endif /* !CONFIG_MACH_MX31ADS */
+#endif	/* !CONFIG_ARCH_MXC */
 }
 
 
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index fc6cc038c7b8..8a34f4679fa5 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -36,6 +36,7 @@
 #define DRV_VERSION	"1.01"
 
 #define SPI_OPLEN	1
+#define MAX_ENC_CARDS 	1
 
 #define ENC28J60_MSG_DEFAULT	\
 	(NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
@@ -49,6 +50,18 @@
 /* Max TX retries in case of collision as suggested by errata datasheet */
 #define MAX_TX_RETRYCOUNT	16
 
+#ifdef CONFIG_ARCH_STMP3XXX
+#include <mach/platform.h>
+#include <mach/stmp3xxx.h>
+#include <mach/regs-ocotp.h>
+#endif
+#ifdef CONFIG_ARCH_MXS
+#include <mach/system.h>
+#include <mach/hardware.h>
+#include <mach/regs-ocotp.h>
+#define REGS_OCOTP_BASE	IO_ADDRESS(OCOTP_PHYS_ADDR)
+#endif
+
 enum {
 	RXFILTER_NORMAL,
 	RXFILTER_MULTI,
@@ -81,6 +94,71 @@ static struct {
 	u32 msg_enable;
 } debug = { -1 };
 
+static int random_mac;	/* = 0 */
+static char *mac[MAX_ENC_CARDS];
+
+static int enc28j60_get_mac(unsigned char *dev_addr, int idx)
+{
+	int i, r;
+	char *p, *item;
+	unsigned long v;
+	unsigned char sv[10];
+
+	if (idx < 0)
+		idx = 0;
+	if (idx > MAX_ENC_CARDS)
+		return false;
+
+	if (!mac[idx]) {
+#if defined(CONFIG_ARCH_STMP3XXX) || defined(CONFIG_ARCH_MXS)
+		if (get_evk_board_version() >= 1) {
+			int mac1 , mac2 , retry = 0;
+
+			__raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN,
+					REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET);
+			while (__raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL) &
+					BM_OCOTP_CTRL_BUSY) {
+				msleep(10);
+				retry++;
+				if (retry > 10)
+					return false;
+			}
+
+			mac1 = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(0));
+			mac2 = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(1));
+			if (MAX_ADDR_LEN < 6)
+				return false;
+
+			dev_addr[0] = (mac1 >> 24) & 0xFF;
+			dev_addr[1] = (mac1 >> 16) & 0xFF;
+			dev_addr[2] = (mac1 >> 8) & 0xFF;
+			dev_addr[3] = (mac1 >> 0) & 0xFF;
+			dev_addr[4] = (mac2 >> 8) & 0xFF;
+			dev_addr[5] = (mac2 >> 0) & 0xFF;
+			return true;
+		}
+#endif
+		return false;
+	}
+
+	item = mac[idx];
+	for (i = 0; i < MAX_ADDR_LEN; i++) {
+		p = strchr(item, ':');
+		if (!p)
+			sprintf(sv, "0x%s", item);
+		else
+			sprintf(sv, "0x%*.*s", p - item, p-item, item);
+		r = strict_strtoul(sv, 0, &v);
+		dev_addr[i] = v;
+		if (p)
+			item = p + 1;
+		else
+			break;
+		if (r < 0)
+			return false;
+	}
+	return true;
+}
 /*
  * SPI read buffer
  * wait for the SPI transfer and copy received data to destination
@@ -90,10 +168,13 @@ spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
 {
 	u8 *rx_buf = priv->spi_transfer_buf + 4;
 	u8 *tx_buf = priv->spi_transfer_buf;
-	struct spi_transfer t = {
-		.tx_buf = tx_buf,
-		.rx_buf = rx_buf,
-		.len = SPI_OPLEN + len,
+	struct spi_transfer tt = {
+		.tx_buf	= tx_buf,
+		.len	= SPI_OPLEN,
+	};
+	struct spi_transfer tr = {
+		.rx_buf	= rx_buf,
+		.len	= len,
 	};
 	struct spi_message msg;
 	int ret;
@@ -102,10 +183,11 @@ spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
 	tx_buf[1] = tx_buf[2] = tx_buf[3] = 0;	/* don't care */
 
 	spi_message_init(&msg);
-	spi_message_add_tail(&t, &msg);
+	spi_message_add_tail(&tt, &msg);
+	spi_message_add_tail(&tr, &msg);
 	ret = spi_sync(priv->spi, &msg);
 	if (ret == 0) {
-		memcpy(data, &rx_buf[SPI_OPLEN], len);
+		memcpy(data, rx_buf, len);
 		ret = msg.status;
 	}
 	if (ret && netif_msg_drv(priv))
@@ -1108,8 +1190,24 @@ static int enc28j60_rx_interrupt(struct net_device *ndev)
 				priv->max_pk_counter);
 	}
 	ret = pk_counter;
-	while (pk_counter-- > 0)
+	while (pk_counter-- > 0) {
+		if (!priv->full_duplex) {
+			/*
+			 * This works only in HALF DUPLEX mode:
+			 * when more than 2 packets are available, start
+			 * transmission of 11111.. frame by setting
+			 * FCON0 (0x01) in EFLOCON
+			 *
+			 * This bit can be cleared either explicitly, or by
+			 * trasmitting the packet in enc28j60_hw_tx.
+			 */
+			if (pk_counter > 2)
+				locked_reg_bfset(priv, EFLOCON, 0x01);
+			if (pk_counter == 1)
+				locked_reg_bfclr(priv, EFLOCON, 0x01);
+		}
 		enc28j60_hw_rx(ndev);
+	}
 
 	return ret;
 }
@@ -1235,6 +1333,11 @@ static void enc28j60_irq_work_handler(struct work_struct *work)
  */
 static void enc28j60_hw_tx(struct enc28j60_net *priv)
 {
+	if (!priv->tx_skb) {
+		enc28j60_tx_clear(priv->netdev, false);
+		return;
+	}
+
 	if (netif_msg_tx_queued(priv))
 		printk(KERN_DEBUG DRV_NAME
 			": Tx Packet Len:%d\n", priv->tx_skb->len);
@@ -1547,6 +1650,7 @@ static int __devinit enc28j60_probe(struct spi_device *spi)
 	struct net_device *dev;
 	struct enc28j60_net *priv;
 	int ret = 0;
+	int set;
 
 	if (netif_msg_drv(&debug))
 		dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
@@ -1580,7 +1684,11 @@ static int __devinit enc28j60_probe(struct spi_device *spi)
 		ret = -EIO;
 		goto error_irq;
 	}
-	random_ether_addr(dev->dev_addr);
+
+	/* need a counter here, to count instances of enc28j60 devices */
+	set = enc28j60_get_mac(dev->dev_addr, -1);
+	if (!set || random_mac)
+		random_ether_addr(dev->dev_addr);
 	enc28j60_set_hw_macaddr(dev);
 
 	/* Board setup must set the relevant edge trigger type;
@@ -1635,6 +1743,40 @@ static int __devexit enc28j60_remove(struct spi_device *spi)
 	return 0;
 }
 
+#ifdef CONFIG_PM
+static int
+enc28j60_suspend(struct spi_device *spi, pm_message_t state)
+{
+	struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
+	struct net_device *net_dev = priv ? priv->netdev : NULL;
+
+	if (net_dev && netif_running(net_dev)) {
+		netif_stop_queue(net_dev);
+		netif_device_detach(net_dev);
+		disable_irq(spi->irq);
+	}
+	return 0;
+}
+
+static int
+enc28j60_resume(struct spi_device *spi)
+{
+	struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
+	struct net_device *net_dev = priv ? priv->netdev : NULL;
+
+	if (net_dev && netif_running(net_dev)) {
+		enable_irq(spi->irq);
+		netif_device_attach(net_dev);
+		netif_start_queue(net_dev);
+		schedule_work(&priv->restart_work);
+	}
+	return 0;
+}
+#else
+#define enc28j60_resume 	NULL
+#define enc28j60_suspend 	NULL
+#endif
+
 static struct spi_driver enc28j60_driver = {
 	.driver = {
 		   .name = DRV_NAME,
@@ -1642,6 +1784,8 @@ static struct spi_driver enc28j60_driver = {
 	 },
 	.probe = enc28j60_probe,
 	.remove = __devexit_p(enc28j60_remove),
+	.suspend = enc28j60_suspend,
+	.resume = enc28j60_resume,
 };
 
 static int __init enc28j60_init(void)
@@ -1664,4 +1808,6 @@ MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
 MODULE_LICENSE("GPL");
 module_param_named(debug, debug.msg_enable, int, 0);
+module_param(random_mac, int, 0444);
+module_param_array(mac, charp, NULL, 0);
 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index c9fd82d3a80d..ecd121f09516 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -17,6 +17,9 @@
  *
  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  * Copyright (c) 2004-2006 Macq Electronique SA.
+ *
+ * Support for FEC IEEE 1588.
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
 #include <linux/module.h>
@@ -40,33 +43,30 @@
 #include <linux/irq.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/swab.h>
+#include <linux/fec.h>
+#include <linux/phy.h>
 
 #include <asm/cacheflush.h>
 
 #ifndef CONFIG_ARCH_MXC
+#ifndef CONFIG_ARCH_MXS
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #endif
+#endif
 
 #include "fec.h"
+#include "fec_1588.h"
 
-#ifdef CONFIG_ARCH_MXC
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
 #include <mach/hardware.h>
 #define FEC_ALIGNMENT	0xf
 #else
 #define FEC_ALIGNMENT	0x3
 #endif
 
-/*
- * Define the fixed address of the FEC hardware.
- */
 #if defined(CONFIG_M5272)
-#define HAVE_mii_link_interrupt
-
-static unsigned char	fec_mac_default[] = {
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
 /*
  * Some hardware gets it MAC address out of local flash memory.
  * if this is non-zero then assume it is the address to get MAC from.
@@ -86,23 +86,6 @@ static unsigned char	fec_mac_default[] = {
 #endif
 #endif /* CONFIG_M5272 */
 
-/* Forward declarations of some structures to support different PHYs */
-
-typedef struct {
-	uint mii_data;
-	void (*funct)(uint mii_reg, struct net_device *dev);
-} phy_cmd_t;
-
-typedef struct {
-	uint id;
-	char *name;
-
-	const phy_cmd_t *config;
-	const phy_cmd_t *startup;
-	const phy_cmd_t *ack_int;
-	const phy_cmd_t *shutdown;
-} phy_info_t;
-
 /* The number of Tx and Rx buffers.  These are allocated from the page
  * pool.  The code may assume these are power of two, so it it best
  * to keep them that size.
@@ -133,6 +116,21 @@ typedef struct {
 #define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
 #define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
 #define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
+#define FEC_ENET_TS_AVAIL	((uint)0x00010000)
+#define FEC_ENET_TS_TIMER	((uint)0x00008000)
+
+/*
+ * RMII mode to be configured via a gasket
+ */
+#define FEC_MIIGSK_CFGR_FRCONT		(1 << 6)
+#define FEC_MIIGSK_CFGR_LBMODE		(1 << 4)
+#define FEC_MIIGSK_CFGR_EMODE		(1 << 3)
+#define FEC_MIIGSK_CFGR_IF_MODE_MASK	(3 << 0)
+#define FEC_MIIGSK_CFGR_IF_MODE_MII	(0 << 0)
+#define FEC_MIIGSK_CFGR_IF_MODE_RMII	(1 << 0)
+
+#define FEC_MIIGSK_ENR_READY		(1 << 2)
+#define FEC_MIIGSK_ENR_EN		(1 << 1)
 
 /* The FEC stores dest/src/type, data, and checksum for receive packets.
  */
@@ -147,7 +145,8 @@ typedef struct {
  * account when setting it.
  */
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
 #define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
 #else
 #define	OPT_FRAME_SIZE	0
@@ -182,36 +181,38 @@ struct fec_enet_private {
 	struct bufdesc	*rx_bd_base;
 	struct bufdesc	*tx_bd_base;
 	/* The next free ring entry */
-	struct bufdesc	*cur_rx, *cur_tx; 
+	struct bufdesc	*cur_rx, *cur_tx;
 	/* The ring entries to be free()ed */
 	struct bufdesc	*dirty_tx;
 
 	uint	tx_full;
 	/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
 	spinlock_t hw_lock;
-	/* hold while accessing the mii_list_t() elements */
-	spinlock_t mii_lock;
+	phy_interface_t phy_interface;
 
-	uint	phy_id;
-	uint	phy_id_done;
-	uint	phy_status;
-	uint	phy_speed;
-	phy_info_t const	*phy;
-	struct work_struct phy_task;
+	struct  platform_device *pdev;
 
-	uint	sequence_done;
-	uint	mii_phy_task_queued;
-
-	uint	phy_addr;
+	int	opened;
 
+	/* Phylib and MDIO interface */
+	struct  mii_bus *mii_bus;
+	struct  phy_device *phy_dev;
+	int     mii_timeout;
+	uint    phy_speed;
 	int	index;
-	int	opened;
 	int	link;
-	int	old_link;
 	int	full_duplex;
+
+	struct fec_ptp_private *ptp_priv;
+	uint	ptimer_present;
 };
 
-static void fec_enet_mii(struct net_device *dev);
+/*
+ * Define the fixed address of the FEC hardware.
+ */
+static unsigned char	fec_mac_default[ETH_ALEN];
+static struct mii_bus *fec_mii_bus;
+
 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
 static void fec_enet_tx(struct net_device *dev);
 static void fec_enet_rx(struct net_device *dev);
@@ -219,66 +220,32 @@ static int fec_enet_close(struct net_device *dev);
 static void fec_restart(struct net_device *dev, int duplex);
 static void fec_stop(struct net_device *dev);
 
+/* FEC MII MMFR bits definition */
+#define FEC_MMFR_ST		(1 << 30)
+#define FEC_MMFR_OP_READ	(2 << 28)
+#define FEC_MMFR_OP_WRITE	(1 << 28)
+#define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
+#define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
+#define FEC_MMFR_TA		(2 << 16)
+#define FEC_MMFR_DATA(v)	(v & 0xffff)
 
-/* MII processing.  We keep this as simple as possible.  Requests are
- * placed on the list (if there is room).  When the request is finished
- * by the MII, an optional function may be called.
- */
-typedef struct mii_list {
-	uint	mii_regval;
-	void	(*mii_func)(uint val, struct net_device *dev);
-	struct	mii_list *mii_next;
-} mii_list_t;
-
-#define		NMII	20
-static mii_list_t	mii_cmds[NMII];
-static mii_list_t	*mii_free;
-static mii_list_t	*mii_head;
-static mii_list_t	*mii_tail;
-
-static int	mii_queue(struct net_device *dev, int request,
-				void (*func)(uint, struct net_device *));
-
-/* Make MII read/write commands for the FEC */
-#define mk_mii_read(REG)	(0x60020000 | ((REG & 0x1f) << 18))
-#define mk_mii_write(REG, VAL)	(0x50020000 | ((REG & 0x1f) << 18) | \
-						(VAL & 0xffff))
-#define mk_mii_end	0
+#define FEC_MII_TIMEOUT		10
 
 /* Transmitter timeout */
 #define TX_TIMEOUT (2 * HZ)
 
-/* Register definitions for the PHY */
-
-#define MII_REG_CR          0  /* Control Register                         */
-#define MII_REG_SR          1  /* Status Register                          */
-#define MII_REG_PHYIR1      2  /* PHY Identification Register 1            */
-#define MII_REG_PHYIR2      3  /* PHY Identification Register 2            */
-#define MII_REG_ANAR        4  /* A-N Advertisement Register               */
-#define MII_REG_ANLPAR      5  /* A-N Link Partner Ability Register        */
-#define MII_REG_ANER        6  /* A-N Expansion Register                   */
-#define MII_REG_ANNPTR      7  /* A-N Next Page Transmit Register          */
-#define MII_REG_ANLPRNPR    8  /* A-N Link Partner Received Next Page Reg. */
-
-/* values for phy_status */
-
-#define PHY_CONF_ANE	0x0001  /* 1 auto-negotiation enabled */
-#define PHY_CONF_LOOP	0x0002  /* 1 loopback mode enabled */
-#define PHY_CONF_SPMASK	0x00f0  /* mask for speed */
-#define PHY_CONF_10HDX	0x0010  /* 10 Mbit half duplex supported */
-#define PHY_CONF_10FDX	0x0020  /* 10 Mbit full duplex supported */
-#define PHY_CONF_100HDX	0x0040  /* 100 Mbit half duplex supported */
-#define PHY_CONF_100FDX	0x0080  /* 100 Mbit full duplex supported */
-
-#define PHY_STAT_LINK	0x0100  /* 1 up - 0 down */
-#define PHY_STAT_FAULT	0x0200  /* 1 remote fault */
-#define PHY_STAT_ANC	0x0400  /* 1 auto-negotiation complete	*/
-#define PHY_STAT_SPMASK	0xf000  /* mask for speed */
-#define PHY_STAT_10HDX	0x1000  /* 10 Mbit half duplex selected	*/
-#define PHY_STAT_10FDX	0x2000  /* 10 Mbit full duplex selected	*/
-#define PHY_STAT_100HDX	0x4000  /* 100 Mbit half duplex selected */
-#define PHY_STAT_100FDX	0x8000  /* 100 Mbit full duplex selected */
+#ifdef CONFIG_ARCH_MXS
+static void *swap_buffer(void *bufaddr, int len)
+{
+	int i;
+	unsigned int *buf = bufaddr;
 
+	for (i = 0; i < (len + 3) / 4; i++, buf++)
+		*buf = __swab32(*buf);
+
+	return bufaddr;
+}
+#endif
 
 static int
 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
@@ -287,6 +254,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	struct bufdesc *bdp;
 	void *bufaddr;
 	unsigned short	status;
+	unsigned long	estatus;
 	unsigned long flags;
 
 	if (!fep->link) {
@@ -328,6 +296,20 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 		bufaddr = fep->tx_bounce[index];
 	}
 
+	if (fep->ptimer_present) {
+		if (fec_ptp_do_txstamp(skb))
+			estatus = BD_ENET_TX_TS;
+		else
+			estatus = 0;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = (estatus | BD_ENET_TX_INT);
+		bdp->cbd_bdu = 0;
+#endif
+	}
+
+#ifdef CONFIG_ARCH_MXS
+	swap_buffer(bufaddr, skb->len);
+#endif
 	/* Save skb pointer */
 	fep->tx_skbuff[fep->skb_cur] = skb;
 
@@ -386,6 +368,7 @@ fec_enet_interrupt(int irq, void * dev_id)
 {
 	struct	net_device *dev = dev_id;
 	struct fec_enet_private *fep = netdev_priv(dev);
+	struct fec_ptp_private *fpp = fep->ptp_priv;
 	uint	int_events;
 	irqreturn_t ret = IRQ_NONE;
 
@@ -406,12 +389,16 @@ fec_enet_interrupt(int irq, void * dev_id)
 			ret = IRQ_HANDLED;
 			fec_enet_tx(dev);
 		}
-
-		if (int_events & FEC_ENET_MII) {
+		if (int_events & FEC_ENET_TS_AVAIL) {
 			ret = IRQ_HANDLED;
-			fec_enet_mii(dev);
+			fec_ptp_store_txstamp(fep->ptp_priv);
 		}
 
+		if (int_events & FEC_ENET_TS_TIMER) {
+			ret = IRQ_HANDLED;
+			if (fep->ptimer_present)
+				fpp->prtc++;
+		}
 	} while (int_events);
 
 	return ret;
@@ -427,7 +414,7 @@ fec_enet_tx(struct net_device *dev)
 	struct	sk_buff	*skb;
 
 	fep = netdev_priv(dev);
-	spin_lock_irq(&fep->hw_lock);
+	spin_lock(&fep->hw_lock);
 	bdp = fep->dirty_tx;
 
 	while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
@@ -486,7 +473,7 @@ fec_enet_tx(struct net_device *dev)
 		}
 	}
 	fep->dirty_tx = bdp;
-	spin_unlock_irq(&fep->hw_lock);
+	spin_unlock(&fep->hw_lock);
 }
 
 
@@ -499,6 +486,7 @@ static void
 fec_enet_rx(struct net_device *dev)
 {
 	struct	fec_enet_private *fep = netdev_priv(dev);
+	struct	fec_ptp_private *fpp = fep->ptp_priv;
 	struct bufdesc *bdp;
 	unsigned short status;
 	struct	sk_buff	*skb;
@@ -509,7 +497,7 @@ fec_enet_rx(struct net_device *dev)
 	flush_cache_all();
 #endif
 
-	spin_lock_irq(&fep->hw_lock);
+	spin_lock(&fep->hw_lock);
 
 	/* First, grab all of the stats for the incoming packet.
 	 * These get messed up if we get called due to a busy condition.
@@ -561,7 +549,9 @@ fec_enet_rx(struct net_device *dev)
 
 	        dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
         			DMA_FROM_DEVICE);
-
+#ifdef CONFIG_ARCH_MXS
+		swap_buffer(data, pkt_len);
+#endif
 		/* This does 16 byte alignment, exactly what we need.
 		 * The packet length includes FCS, but we don't want to
 		 * include that when passing upstream as it messes up
@@ -578,6 +568,9 @@ fec_enet_rx(struct net_device *dev)
 			skb_put(skb, pkt_len - 4);	/* Make room */
 			skb_copy_to_linear_data(skb, data, pkt_len - 4);
 			skb->protocol = eth_type_trans(skb, dev);
+			/* 1588 messeage TS handle */
+			if (fep->ptimer_present)
+				fec_ptp_store_rxstamp(fpp, skb, bdp);
 			netif_rx(skb);
 		}
 
@@ -590,6 +583,11 @@ rx_processing_done:
 		/* Mark the buffer empty */
 		status |= BD_ENET_RX_EMPTY;
 		bdp->cbd_sc = status;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_RX_INT;
+		bdp->cbd_prot = 0;
+		bdp->cbd_bdu = 0;
+#endif
 
 		/* Update BD pointer to next entry */
 		if (status & BD_ENET_RX_WRAP)
@@ -604,809 +602,329 @@ rx_processing_done:
 	}
 	fep->cur_rx = bdp;
 
-	spin_unlock_irq(&fep->hw_lock);
+	spin_unlock(&fep->hw_lock);
 }
 
-/* called from interrupt context */
-static void
-fec_enet_mii(struct net_device *dev)
+/* ------------------------------------------------------------------------- */
+static void __inline__ fec_get_mac(struct net_device *dev)
 {
-	struct	fec_enet_private *fep;
-	mii_list_t	*mip;
-
-	fep = netdev_priv(dev);
-	spin_lock_irq(&fep->mii_lock);
+	struct fec_enet_private *fep = netdev_priv(dev);
+	unsigned char *iap, tmpaddr[ETH_ALEN];
+	static int index;
 
-	if ((mip = mii_head) == NULL) {
-		printk("MII and no head!\n");
-		goto unlock;
+#ifdef CONFIG_M5272
+	if (FEC_FLASHMAC) {
+		/*
+		 * Get MAC address from FLASH.
+		 * If it is all 1's or 0's, use the default.
+		 */
+		iap = (unsigned char *)FEC_FLASHMAC;
+		if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
+		    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
+			iap = fec_mac_default;
+		if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
+		    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
+			iap = fec_mac_default;
 	}
-
-	if (mip->mii_func != NULL)
-		(*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev);
-
-	mii_head = mip->mii_next;
-	mip->mii_next = mii_free;
-	mii_free = mip;
-
-	if ((mip = mii_head) != NULL)
-		writel(mip->mii_regval, fep->hwp + FEC_MII_DATA);
-
-unlock:
-	spin_unlock_irq(&fep->mii_lock);
-}
-
-static int
-mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
-{
-	struct fec_enet_private *fep;
-	unsigned long	flags;
-	mii_list_t	*mip;
-	int		retval;
-
-	/* Add PHY address to register command */
-	fep = netdev_priv(dev);
-	spin_lock_irqsave(&fep->mii_lock, flags);
-
-	regval |= fep->phy_addr << 23;
-	retval = 0;
-
-	if ((mip = mii_free) != NULL) {
-		mii_free = mip->mii_next;
-		mip->mii_regval = regval;
-		mip->mii_func = func;
-		mip->mii_next = NULL;
-		if (mii_head) {
-			mii_tail->mii_next = mip;
-			mii_tail = mip;
-		} else {
-			mii_head = mii_tail = mip;
-			writel(regval, fep->hwp + FEC_MII_DATA);
-		}
-	} else {
-		retval = 1;
+#else
+	if (is_valid_ether_addr(fec_mac_default)) {
+		iap = fec_mac_default;
+	}
+#endif
+	else {
+		*((unsigned long *) &tmpaddr[0]) = be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
+		*((unsigned short *) &tmpaddr[4]) = be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
+		iap = &tmpaddr[0];
 	}
 
-	spin_unlock_irqrestore(&fep->mii_lock, flags);
-	return retval;
-}
-
-static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
-{
-	if(!c)
-		return;
+	memcpy(dev->dev_addr, iap, ETH_ALEN);
 
-	for (; c->mii_data != mk_mii_end; c++)
-		mii_queue(dev, c->mii_data, c->funct);
+	/* Adjust MAC if using default MAC address */
+	if (iap == fec_mac_default) {
+		dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + index;
+		index++;
+	}
 }
 
-static void mii_parse_sr(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
-
-	status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
-
-	if (mii_reg & 0x0004)
-		status |= PHY_STAT_LINK;
-	if (mii_reg & 0x0010)
-		status |= PHY_STAT_FAULT;
-	if (mii_reg & 0x0020)
-		status |= PHY_STAT_ANC;
-	*s = status;
-}
+/* ------------------------------------------------------------------------- */
 
-static void mii_parse_cr(uint mii_reg, struct net_device *dev)
+/*
+ * Phy section
+ */
+static void fec_enet_adjust_link(struct net_device *dev)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
-
-	status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
-
-	if (mii_reg & 0x1000)
-		status |= PHY_CONF_ANE;
-	if (mii_reg & 0x4000)
-		status |= PHY_CONF_LOOP;
-	*s = status;
-}
+	struct phy_device *phy_dev = fep->phy_dev;
+	unsigned long flags;
 
-static void mii_parse_anar(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
-
-	status = *s & ~(PHY_CONF_SPMASK);
-
-	if (mii_reg & 0x0020)
-		status |= PHY_CONF_10HDX;
-	if (mii_reg & 0x0040)
-		status |= PHY_CONF_10FDX;
-	if (mii_reg & 0x0080)
-		status |= PHY_CONF_100HDX;
-	if (mii_reg & 0x00100)
-		status |= PHY_CONF_100FDX;
-	*s = status;
-}
+	int status_change = 0;
 
-/* ------------------------------------------------------------------------- */
-/* The Level one LXT970 is used by many boards				     */
+	spin_lock_irqsave(&fep->hw_lock, flags);
 
-#define MII_LXT970_MIRROR    16  /* Mirror register           */
-#define MII_LXT970_IER       17  /* Interrupt Enable Register */
-#define MII_LXT970_ISR       18  /* Interrupt Status Register */
-#define MII_LXT970_CONFIG    19  /* Configuration Register    */
-#define MII_LXT970_CSR       20  /* Chip Status Register      */
+	/* Prevent a state halted on mii error */
+	if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
+		phy_dev->state = PHY_RESUMING;
+		goto spin_unlock;
+	}
 
-static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
+	/* Duplex link change */
+	if (phy_dev->link) {
+		if (fep->full_duplex != phy_dev->duplex) {
+			fec_restart(dev, phy_dev->duplex);
+			status_change = 1;
+		}
+	}
 
-	status = *s & ~(PHY_STAT_SPMASK);
-	if (mii_reg & 0x0800) {
-		if (mii_reg & 0x1000)
-			status |= PHY_STAT_100FDX;
+	/* Link on or off change */
+	if (phy_dev->link != fep->link) {
+		fep->link = phy_dev->link;
+		if (phy_dev->link)
+			fec_restart(dev, phy_dev->duplex);
 		else
-			status |= PHY_STAT_100HDX;
-	} else {
-		if (mii_reg & 0x1000)
-			status |= PHY_STAT_10FDX;
-		else
-			status |= PHY_STAT_10HDX;
+			fec_stop(dev);
+		status_change = 1;
 	}
-	*s = status;
-}
 
-static phy_cmd_t const phy_cmd_lxt970_config[] = {
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
-		{ mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
-		/* read SR and ISR to acknowledge */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_read(MII_LXT970_ISR), NULL },
-
-		/* find out the current status */
-		{ mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
-		{ mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
-		{ mk_mii_end, }
-	};
-static phy_info_t const phy_info_lxt970 = {
-	.id = 0x07810000,
-	.name = "LXT970",
-	.config = phy_cmd_lxt970_config,
-	.startup = phy_cmd_lxt970_startup,
-	.ack_int = phy_cmd_lxt970_ack_int,
-	.shutdown = phy_cmd_lxt970_shutdown
-};
-
-/* ------------------------------------------------------------------------- */
-/* The Level one LXT971 is used on some of my custom boards                  */
-
-/* register definitions for the 971 */
+spin_unlock:
+	spin_unlock_irqrestore(&fep->hw_lock, flags);
 
-#define MII_LXT971_PCR       16  /* Port Control Register     */
-#define MII_LXT971_SR2       17  /* Status Register 2         */
-#define MII_LXT971_IER       18  /* Interrupt Enable Register */
-#define MII_LXT971_ISR       19  /* Interrupt Status Register */
-#define MII_LXT971_LCR       20  /* LED Control Register      */
-#define MII_LXT971_TCR       30  /* Transmit Control Register */
+	if (status_change)
+		phy_print_status(phy_dev);
+}
 
 /*
- * I had some nice ideas of running the MDIO faster...
- * The 971 should support 8MHz and I tried it, but things acted really
- * weird, so 2.5 MHz ought to be enough for anyone...
+ * NOTE: a MII transaction is during around 25 us, so polling it...
  */
+static int fec_enet_mdio_poll(struct fec_enet_private *fep)
+ {
+	int timeout = FEC_MII_TIMEOUT;
 
-static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
-
-	status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
+	fep->mii_timeout = 0;
 
-	if (mii_reg & 0x0400) {
-		fep->link = 1;
-		status |= PHY_STAT_LINK;
-	} else {
-		fep->link = 0;
-	}
-	if (mii_reg & 0x0080)
-		status |= PHY_STAT_ANC;
-	if (mii_reg & 0x4000) {
-		if (mii_reg & 0x0200)
-			status |= PHY_STAT_100FDX;
-		else
-			status |= PHY_STAT_100HDX;
-	} else {
-		if (mii_reg & 0x0200)
-			status |= PHY_STAT_10FDX;
-		else
-			status |= PHY_STAT_10HDX;
+	/* wait for end of transfer */
+	while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) {
+		msleep(1);
+		if (timeout-- < 0) {
+			fep->mii_timeout = 1;
+			break;
+		}
 	}
-	if (mii_reg & 0x0008)
-		status |= PHY_STAT_FAULT;
 
-	*s = status;
+	return 0;
 }
 
-static phy_cmd_t const phy_cmd_lxt971_config[] = {
-		/* limit to 10MBit because my prototype board
-		 * doesn't work with 100. */
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt971_startup[] = {  /* enable interrupts */
-		{ mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
-		/* Somehow does the 971 tell me that the link is down
-		 * the first read after power-up.
-		 * read here to get a valid value in ack_int */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
-		/* acknowledge the int before reading status ! */
-		{ mk_mii_read(MII_LXT971_ISR), NULL },
-		/* find out the current status */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
-		{ mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
-		{ mk_mii_end, }
-	};
-static phy_info_t const phy_info_lxt971 = {
-	.id = 0x0001378e,
-	.name = "LXT971",
-	.config = phy_cmd_lxt971_config,
-	.startup = phy_cmd_lxt971_startup,
-	.ack_int = phy_cmd_lxt971_ack_int,
-	.shutdown = phy_cmd_lxt971_shutdown
-};
-
-/* ------------------------------------------------------------------------- */
-/* The Quality Semiconductor QS6612 is used on the RPX CLLF                  */
-
-/* register definitions */
+static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct fec_enet_private *fep = bus->priv;
 
-#define MII_QS6612_MCR       17  /* Mode Control Register      */
-#define MII_QS6612_FTR       27  /* Factory Test Register      */
-#define MII_QS6612_MCO       28  /* Misc. Control Register     */
-#define MII_QS6612_ISR       29  /* Interrupt Source Register  */
-#define MII_QS6612_IMR       30  /* Interrupt Mask Register    */
-#define MII_QS6612_PCR       31  /* 100BaseTx PHY Control Reg. */
+	/* clear MII end of transfer bit*/
+	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
 
-static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
+	/* start a read op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
 
-	status = *s & ~(PHY_STAT_SPMASK);
+	fec_enet_mdio_poll(fep);
 
-	switch((mii_reg >> 2) & 7) {
-	case 1: status |= PHY_STAT_10HDX; break;
-	case 2: status |= PHY_STAT_100HDX; break;
-	case 5: status |= PHY_STAT_10FDX; break;
-	case 6: status |= PHY_STAT_100FDX; break;
+	/* return value */
+	return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
 }
 
-	*s = status;
-}
+static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			   u16 value)
+{
+	struct fec_enet_private *fep = bus->priv;
 
-static phy_cmd_t const phy_cmd_qs6612_config[] = {
-		/* The PHY powers up isolated on the RPX,
-		 * so send a command to allow operation.
-		 */
-		{ mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
-
-		/* parse cr and anar to get some info */
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_qs6612_startup[] = {  /* enable interrupts */
-		{ mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
-		/* we need to read ISR, SR and ANER to acknowledge */
-		{ mk_mii_read(MII_QS6612_ISR), NULL },
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_read(MII_REG_ANER), NULL },
-
-		/* read pcr to get info */
-		{ mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
-		{ mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
-		{ mk_mii_end, }
-	};
-static phy_info_t const phy_info_qs6612 = {
-	.id = 0x00181440,
-	.name = "QS6612",
-	.config = phy_cmd_qs6612_config,
-	.startup = phy_cmd_qs6612_startup,
-	.ack_int = phy_cmd_qs6612_ack_int,
-	.shutdown = phy_cmd_qs6612_shutdown
-};
+	/* clear MII end of transfer bit*/
+	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
 
-/* ------------------------------------------------------------------------- */
-/* AMD AM79C874 phy                                                          */
+	/* start a write op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA | FEC_MMFR_DATA(value),
+		fep->hwp + FEC_MII_DATA);
 
-/* register definitions for the 874 */
+	fec_enet_mdio_poll(fep);
 
-#define MII_AM79C874_MFR       16  /* Miscellaneous Feature Register */
-#define MII_AM79C874_ICSR      17  /* Interrupt/Status Register      */
-#define MII_AM79C874_DR        18  /* Diagnostic Register            */
-#define MII_AM79C874_PMLR      19  /* Power and Loopback Register    */
-#define MII_AM79C874_MCR       21  /* ModeControl Register           */
-#define MII_AM79C874_DC        23  /* Disconnect Counter             */
-#define MII_AM79C874_REC       24  /* Recieve Error Counter          */
+	return 0;
+}
 
-static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
+static int fec_enet_mdio_reset(struct mii_bus *bus)
 {
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-	uint status;
-
-	status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
-
-	if (mii_reg & 0x0080)
-		status |= PHY_STAT_ANC;
-	if (mii_reg & 0x0400)
-		status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
-	else
-		status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
-
-	*s = status;
+	return 0;
 }
 
-static phy_cmd_t const phy_cmd_am79c874_config[] = {
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_am79c874_startup[] = {  /* enable interrupts */
-		{ mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
-		/* find out the current status */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
-		/* we only need to read ISR to acknowledge */
-		{ mk_mii_read(MII_AM79C874_ICSR), NULL },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
-		{ mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
-		{ mk_mii_end, }
-	};
-static phy_info_t const phy_info_am79c874 = {
-	.id = 0x00022561,
-	.name = "AM79C874",
-	.config = phy_cmd_am79c874_config,
-	.startup = phy_cmd_am79c874_startup,
-	.ack_int = phy_cmd_am79c874_ack_int,
-	.shutdown = phy_cmd_am79c874_shutdown
-};
-
-
-/* ------------------------------------------------------------------------- */
-/* Kendin KS8721BL phy                                                       */
-
-/* register definitions for the 8721 */
-
-#define MII_KS8721BL_RXERCR	21
-#define MII_KS8721BL_ICSR	27
-#define	MII_KS8721BL_PHYCR	31
-
-static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_ks8721bl_startup[] = {  /* enable interrupts */
-		{ mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
-		/* find out the current status */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		/* we only need to read ISR to acknowledge */
-		{ mk_mii_read(MII_KS8721BL_ICSR), NULL },
-		{ mk_mii_end, }
-	};
-static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
-		{ mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
-		{ mk_mii_end, }
-	};
-static phy_info_t const phy_info_ks8721bl = {
-	.id = 0x00022161,
-	.name = "KS8721BL",
-	.config = phy_cmd_ks8721bl_config,
-	.startup = phy_cmd_ks8721bl_startup,
-	.ack_int = phy_cmd_ks8721bl_ack_int,
-	.shutdown = phy_cmd_ks8721bl_shutdown
-};
-
-/* ------------------------------------------------------------------------- */
-/* register definitions for the DP83848 */
-
-#define MII_DP8384X_PHYSTST    16  /* PHY Status Register */
-
-static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
+static int fec_enet_mii_probe(struct net_device *dev)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-
-	*s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
-
-	/* Link up */
-	if (mii_reg & 0x0001) {
-		fep->link = 1;
-		*s |= PHY_STAT_LINK;
-	} else
-		fep->link = 0;
-	/* Status of link */
-	if (mii_reg & 0x0010)   /* Autonegotioation complete */
-		*s |= PHY_STAT_ANC;
-	if (mii_reg & 0x0002) {   /* 10MBps? */
-		if (mii_reg & 0x0004)   /* Full Duplex? */
-			*s |= PHY_STAT_10FDX;
-		else
-			*s |= PHY_STAT_10HDX;
-	} else {                  /* 100 Mbps? */
-		if (mii_reg & 0x0004)   /* Full Duplex? */
-			*s |= PHY_STAT_100FDX;
-		else
-			*s |= PHY_STAT_100HDX;
+	struct phy_device *phy_dev = NULL;
+	int phy_addr;
+	int fec_index = fep->pdev->id > 0 ? fep->pdev->id : 0;
+
+	fep->phy_dev = NULL;
+
+	/* find the phy, assuming fec index corresponds to addr */
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (fep->mii_bus->phy_map[phy_addr]) {
+			if (fec_index--)
+				continue;
+			phy_dev = fep->mii_bus->phy_map[phy_addr];
+			break;
+		}
+	}
+	if (!phy_dev) {
+		printk(KERN_ERR "%s: no PHY found\n", dev->name);
+		return -ENODEV;
 	}
-	if (mii_reg & 0x0008)
-		*s |= PHY_STAT_FAULT;
-}
-
-static phy_info_t phy_info_dp83848= {
-	0x020005c9,
-	"DP83848",
-
-	(const phy_cmd_t []) {  /* config */
-		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
-		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
-		{ mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
-		{ mk_mii_end, }
-	},
-	(const phy_cmd_t []) {  /* startup - enable interrupts */
-		{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
-		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
-		{ mk_mii_end, }
-	},
-	(const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
-		{ mk_mii_end, }
-	},
-	(const phy_cmd_t []) {  /* shutdown */
-		{ mk_mii_end, }
-	},
-};
 
-/* ------------------------------------------------------------------------- */
+	/* attach the mac to the phy */
+	phy_dev = phy_connect(dev, dev_name(&phy_dev->dev),
+			     &fec_enet_adjust_link, 0,
+			     fep->phy_interface);
+	if (IS_ERR(phy_dev)) {
+		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+		return PTR_ERR(phy_dev);
+	}
 
-static phy_info_t const * const phy_info[] = {
-	&phy_info_lxt970,
-	&phy_info_lxt971,
-	&phy_info_qs6612,
-	&phy_info_am79c874,
-	&phy_info_ks8721bl,
-	&phy_info_dp83848,
-	NULL
-};
+	/* mask with MAC supported features */
+	phy_dev->supported &= PHY_BASIC_FEATURES;
+	phy_dev->advertising = phy_dev->supported;
 
-/* ------------------------------------------------------------------------- */
-#ifdef HAVE_mii_link_interrupt
-static irqreturn_t
-mii_link_interrupt(int irq, void * dev_id);
+	fep->phy_dev = phy_dev;
+	fep->link = 0;
+	fep->full_duplex = 0;
 
-/*
- *	This is specific to the MII interrupt setup of the M5272EVB.
- */
-static void __inline__ fec_request_mii_intr(struct net_device *dev)
-{
-	if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0)
-		printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
-}
+	printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
+               "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
+               fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
+               fep->phy_dev->irq);
 
-static void __inline__ fec_disable_phy_intr(void)
-{
-	volatile unsigned long *icrp;
-	icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
-	*icrp = 0x08000000;
-}
 
-static void __inline__ fec_phy_ack_intr(void)
-{
-	volatile unsigned long *icrp;
-	/* Acknowledge the interrupt */
-	icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
-	*icrp = 0x0d000000;
+	return 0;
 }
-#endif
 
-#ifdef CONFIG_M5272
-static void __inline__ fec_get_mac(struct net_device *dev)
+static struct mii_bus *fec_enet_mii_init(struct platform_device *pdev)
 {
+	struct net_device *dev = platform_get_drvdata(pdev);
 	struct fec_enet_private *fep = netdev_priv(dev);
-	unsigned char *iap, tmpaddr[ETH_ALEN];
-
-	if (FEC_FLASHMAC) {
-		/*
-		 * Get MAC address from FLASH.
-		 * If it is all 1's or 0's, use the default.
-		 */
-		iap = (unsigned char *)FEC_FLASHMAC;
-		if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
-		    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
-			iap = fec_mac_default;
-		if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
-		    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
-			iap = fec_mac_default;
-	} else {
-		*((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
-		*((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
-		iap = &tmpaddr[0];
-	}
+	struct fec_enet_platform_data *pdata;
+	int err = -ENXIO, i;
 
-	memcpy(dev->dev_addr, iap, ETH_ALEN);
+	fep->mii_timeout = 0;
 
-	/* Adjust MAC if using default MAC address */
-	if (iap == fec_mac_default)
-		 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
-}
+	/*
+	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
+	 */
+	fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/
+	fep->phy_speed <<= 2;
 #endif
+	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
-/* ------------------------------------------------------------------------- */
-
-static void mii_display_status(struct net_device *dev)
-{
-	struct fec_enet_private *fep = netdev_priv(dev);
-	volatile uint *s = &(fep->phy_status);
-
-	if (!fep->link && !fep->old_link) {
-		/* Link is still down - don't print anything */
-		return;
+	fep->mii_bus = mdiobus_alloc();
+	if (fep->mii_bus == NULL) {
+		err = -ENOMEM;
+		goto err_out;
 	}
 
-	printk("%s: status: ", dev->name);
-
-	if (!fep->link) {
-		printk("link down");
-	} else {
-		printk("link up");
-
-		switch(*s & PHY_STAT_SPMASK) {
-		case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
-		case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
-		case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
-		case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
-		default:
-			printk(", Unknown speed/duplex");
-		}
-
-		if (*s & PHY_STAT_ANC)
-			printk(", auto-negotiation complete");
+	fep->mii_bus->name = "fec_enet_mii_bus";
+	fep->mii_bus->read = fec_enet_mdio_read;
+	fep->mii_bus->write = fec_enet_mdio_write;
+	fep->mii_bus->reset = fec_enet_mdio_reset;
+	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
+	fep->mii_bus->priv = fep;
+	fep->mii_bus->parent = &pdev->dev;
+	pdata = pdev->dev.platform_data;
+
+	fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!fep->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_free_mdiobus;
 	}
 
-	if (*s & PHY_STAT_FAULT)
-		printk(", remote fault");
-
-	printk(".\n");
-}
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		fep->mii_bus->irq[i] = PHY_POLL;
 
-static void mii_display_config(struct work_struct *work)
-{
-	struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
-	struct net_device *dev = fep->netdev;
-	uint status = fep->phy_status;
-
-	/*
-	** When we get here, phy_task is already removed from
-	** the workqueue.  It is thus safe to allow to reuse it.
-	*/
-	fep->mii_phy_task_queued = 0;
-	printk("%s: config: auto-negotiation ", dev->name);
-
-	if (status & PHY_CONF_ANE)
-		printk("on");
-	else
-		printk("off");
+	platform_set_drvdata(dev, fep->mii_bus);
 
-	if (status & PHY_CONF_100FDX)
-		printk(", 100FDX");
-	if (status & PHY_CONF_100HDX)
-		printk(", 100HDX");
-	if (status & PHY_CONF_10FDX)
-		printk(", 10FDX");
-	if (status & PHY_CONF_10HDX)
-		printk(", 10HDX");
-	if (!(status & PHY_CONF_SPMASK))
-		printk(", No speed/duplex selected?");
+	if (mdiobus_register(fep->mii_bus))
+		goto err_out_free_mdio_irq;
 
-	if (status & PHY_CONF_LOOP)
-		printk(", loopback enabled");
+	return fep->mii_bus;
 
-	printk(".\n");
-
-	fep->sequence_done = 1;
+err_out_free_mdio_irq:
+	kfree(fep->mii_bus->irq);
+err_out_free_mdiobus:
+	mdiobus_free(fep->mii_bus);
+err_out:
+	return ERR_PTR(err);
 }
 
-static void mii_relink(struct work_struct *work)
+static void fec_enet_mii_remove(struct fec_enet_private *fep)
 {
-	struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
-	struct net_device *dev = fep->netdev;
-	int duplex;
-
-	/*
-	** When we get here, phy_task is already removed from
-	** the workqueue.  It is thus safe to allow to reuse it.
-	*/
-	fep->mii_phy_task_queued = 0;
-	fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
-	mii_display_status(dev);
-	fep->old_link = fep->link;
-
-	if (fep->link) {
-		duplex = 0;
-		if (fep->phy_status
-		    & (PHY_STAT_100FDX | PHY_STAT_10FDX))
-			duplex = 1;
-		fec_restart(dev, duplex);
-	} else
-		fec_stop(dev);
+	if (fep->phy_dev)
+		phy_disconnect(fep->phy_dev);
+	mdiobus_unregister(fep->mii_bus);
+	kfree(fep->mii_bus->irq);
+	mdiobus_free(fep->mii_bus);
 }
 
-/* mii_queue_relink is called in interrupt context from mii_link_interrupt */
-static void mii_queue_relink(uint mii_reg, struct net_device *dev)
+static int fec_enet_get_settings(struct net_device *dev,
+				  struct ethtool_cmd *cmd)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
 
-	/*
-	 * We cannot queue phy_task twice in the workqueue.  It
-	 * would cause an endless loop in the workqueue.
-	 * Fortunately, if the last mii_relink entry has not yet been
-	 * executed now, it will do the job for the current interrupt,
-	 * which is just what we want.
-	 */
-	if (fep->mii_phy_task_queued)
-		return;
+	if (!phydev)
+		return -ENODEV;
 
-	fep->mii_phy_task_queued = 1;
-	INIT_WORK(&fep->phy_task, mii_relink);
-	schedule_work(&fep->phy_task);
+	return phy_ethtool_gset(phydev, cmd);
 }
 
-/* mii_queue_config is called in interrupt context from fec_enet_mii */
-static void mii_queue_config(uint mii_reg, struct net_device *dev)
+static int fec_enet_set_settings(struct net_device *dev,
+				 struct ethtool_cmd *cmd)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
 
-	if (fep->mii_phy_task_queued)
-		return;
+	if (!phydev)
+		return -ENODEV;
 
-	fep->mii_phy_task_queued = 1;
-	INIT_WORK(&fep->phy_task, mii_display_config);
-	schedule_work(&fep->phy_task);
+	return phy_ethtool_sset(phydev, cmd);
 }
 
-phy_cmd_t const phy_cmd_relink[] = {
-	{ mk_mii_read(MII_REG_CR), mii_queue_relink },
-	{ mk_mii_end, }
-	};
-phy_cmd_t const phy_cmd_config[] = {
-	{ mk_mii_read(MII_REG_CR), mii_queue_config },
-	{ mk_mii_end, }
-	};
-
-/* Read remainder of PHY ID. */
-static void
-mii_discover_phy3(uint mii_reg, struct net_device *dev)
+static void fec_enet_get_drvinfo(struct net_device *dev,
+				 struct ethtool_drvinfo *info)
 {
-	struct fec_enet_private *fep;
-	int i;
-
-	fep = netdev_priv(dev);
-	fep->phy_id |= (mii_reg & 0xffff);
-	printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
-
-	for(i = 0; phy_info[i]; i++) {
-		if(phy_info[i]->id == (fep->phy_id >> 4))
-			break;
-	}
-
-	if (phy_info[i])
-		printk(" -- %s\n", phy_info[i]->name);
-	else
-		printk(" -- unknown PHY!\n");
+	struct fec_enet_private *fep = netdev_priv(dev);
 
-	fep->phy = phy_info[i];
-	fep->phy_id_done = 1;
+	strcpy(info->driver, fep->pdev->dev.driver->name);
+	strcpy(info->version, "Revision: 1.0");
+	strcpy(info->bus_info, dev_name(&dev->dev));
 }
 
-/* Scan all of the MII PHY addresses looking for someone to respond
- * with a valid ID.  This usually happens quickly.
- */
-static void
-mii_discover_phy(uint mii_reg, struct net_device *dev)
-{
-	struct fec_enet_private *fep;
-	uint phytype;
-
-	fep = netdev_priv(dev);
-
-	if (fep->phy_addr < 32) {
-		if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
-
-			/* Got first part of ID, now get remainder */
-			fep->phy_id = phytype << 16;
-			mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
-							mii_discover_phy3);
-		} else {
-			fep->phy_addr++;
-			mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
-							mii_discover_phy);
-		}
-	} else {
-		printk("FEC: No PHY device found.\n");
-		/* Disable external MII interface */
-		writel(0, fep->hwp + FEC_MII_SPEED);
-		fep->phy_speed = 0;
-#ifdef HAVE_mii_link_interrupt
-		fec_disable_phy_intr();
-#endif
-	}
-}
+static struct ethtool_ops fec_enet_ethtool_ops = {
+	.get_settings		= fec_enet_get_settings,
+	.set_settings		= fec_enet_set_settings,
+	.get_drvinfo		= fec_enet_get_drvinfo,
+	.get_link		= ethtool_op_get_link,
+};
 
-/* This interrupt occurs when the PHY detects a link change */
-#ifdef HAVE_mii_link_interrupt
-static irqreturn_t
-mii_link_interrupt(int irq, void * dev_id)
+static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
-	struct	net_device *dev = dev_id;
 	struct fec_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
 
-	fec_phy_ack_intr();
+	if (!netif_running(dev))
+		return -EINVAL;
 
-	mii_do_cmd(dev, fep->phy->ack_int);
-	mii_do_cmd(dev, phy_cmd_relink);  /* restart and display status */
+	if (!phydev)
+		return -ENODEV;
 
-	return IRQ_HANDLED;
+	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
 }
-#endif
 
 static void fec_enet_free_buffers(struct net_device *dev)
 {
@@ -1451,6 +969,9 @@ static int fec_enet_alloc_buffers(struct net_device *dev)
 		bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
 				FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
 		bdp->cbd_sc = BD_ENET_RX_EMPTY;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_RX_INT;
+#endif
 		bdp++;
 	}
 
@@ -1464,6 +985,9 @@ static int fec_enet_alloc_buffers(struct net_device *dev)
 
 		bdp->cbd_sc = 0;
 		bdp->cbd_bufaddr = 0;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_TX_INT;
+#endif
 		bdp++;
 	}
 
@@ -1483,40 +1007,19 @@ fec_enet_open(struct net_device *dev)
 	/* I should reset the ring buffers here, but I don't yet know
 	 * a simple way to do that.
 	 */
-
+	clk_enable(fep->clk);
 	ret = fec_enet_alloc_buffers(dev);
 	if (ret)
 		return ret;
 
-	fep->sequence_done = 0;
-	fep->link = 0;
-
-	fec_restart(dev, 1);
-
-	if (fep->phy) {
-		mii_do_cmd(dev, fep->phy->ack_int);
-		mii_do_cmd(dev, fep->phy->config);
-		mii_do_cmd(dev, phy_cmd_config);  /* display configuration */
-
-		/* Poll until the PHY tells us its configuration
-		 * (not link state).
-		 * Request is initiated by mii_do_cmd above, but answer
-		 * comes by interrupt.
-		 * This should take about 25 usec per register at 2.5 MHz,
-		 * and we read approximately 5 registers.
-		 */
-		while(!fep->sequence_done)
-			schedule();
-
-		mii_do_cmd(dev, fep->phy->startup);
+	/* Probe and connect to PHY when open the interface */
+	ret = fec_enet_mii_probe(dev);
+	if (ret) {
+	       fec_enet_free_buffers(dev);
+	       return ret;
 	}
-
-	/* Set the initial link state to true. A lot of hardware
-	 * based on this device does not implement a PHY interrupt,
-	 * so we are never notified of link change.
-	 */
-	fep->link = 1;
-
+	phy_start(fep->phy_dev);
+	fec_restart(dev, fep->phy_dev->duplex);
 	netif_start_queue(dev);
 	fep->opened = 1;
 	return 0;
@@ -1532,7 +1035,12 @@ fec_enet_close(struct net_device *dev)
 	netif_stop_queue(dev);
 	fec_stop(dev);
 
+	if (fep->phy_dev) {
+		phy_stop(fep->phy_dev);
+		phy_disconnect(fep->phy_dev);
+	}
         fec_enet_free_buffers(dev);
+	clk_disable(fep->clk);
 
 	return 0;
 }
@@ -1624,17 +1132,18 @@ fec_set_mac_address(struct net_device *dev, void *p)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
 	struct sockaddr *addr = p;
+	u32 temp_mac[2];
 
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 
 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 
-	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
-		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
-		fep->hwp + FEC_ADDR_LOW);
-	writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
-		fep + FEC_ADDR_HIGH);
+	memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+
+	writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+	writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+
 	return 0;
 }
 
@@ -1647,8 +1156,34 @@ static const struct net_device_ops fec_netdev_ops = {
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_tx_timeout		= fec_timeout,
 	.ndo_set_mac_address	= fec_set_mac_address,
+	.ndo_do_ioctl           = fec_enet_ioctl,
 };
 
+static int fec_mac_addr_setup(char *mac_addr)
+{
+	char *ptr, *p = mac_addr;
+	unsigned long tmp;
+	int i = 0, ret = 0;
+
+	while (p && (*p) && i < 6) {
+		ptr = strchr(p, ':');
+		if (ptr)
+			*ptr++ = '\0';
+
+		if (strlen(p)) {
+			ret = strict_strtoul(p, 16, &tmp);
+			if (ret < 0 || tmp > 0xff)
+				break;
+			fec_mac_default[i++] = tmp;
+		}
+		p = ptr;
+	}
+
+	return 0;
+}
+
+__setup("fec_mac=", fec_mac_addr_setup);
+
  /*
   * XXX:  We need to clean up on failure exits here.
   *
@@ -1658,6 +1193,7 @@ int __init fec_enet_init(struct net_device *dev, int index)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
 	struct bufdesc *cbd_base;
+	struct bufdesc *bdp;
 	int i;
 
 	/* Allocate memory for buffer descriptors. */
@@ -1669,55 +1205,51 @@ int __init fec_enet_init(struct net_device *dev, int index)
 	}
 
 	spin_lock_init(&fep->hw_lock);
-	spin_lock_init(&fep->mii_lock);
 
 	fep->index = index;
 	fep->hwp = (void __iomem *)dev->base_addr;
 	fep->netdev = dev;
 
 	/* Set the Ethernet address */
-#ifdef CONFIG_M5272
 	fec_get_mac(dev);
-#else
-	{
-		unsigned long l;
-		l = readl(fep->hwp + FEC_ADDR_LOW);
-		dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
-		dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
-		dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
-		dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
-		l = readl(fep->hwp + FEC_ADDR_HIGH);
-		dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
-		dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
-	}
-#endif
 
 	/* Set receive and transmit descriptor base. */
 	fep->rx_bd_base = cbd_base;
 	fep->tx_bd_base = cbd_base + RX_RING_SIZE;
 
-#ifdef HAVE_mii_link_interrupt
-	fec_request_mii_intr(dev);
-#endif
 	/* The FEC Ethernet specific entries in the device structure */
 	dev->watchdog_timeo = TX_TIMEOUT;
 	dev->netdev_ops = &fec_netdev_ops;
+	dev->ethtool_ops = &fec_enet_ethtool_ops;
 
-	for (i=0; i<NMII-1; i++)
-		mii_cmds[i].mii_next = &mii_cmds[i+1];
-	mii_free = mii_cmds;
+	/* Initialize the receive buffer descriptors. */
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
 
-	/* Set MII speed to 2.5 MHz */
-	fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999)
-					/ 2500000) / 2) & 0x3F) << 1;
-	fec_restart(dev, 0);
+		/* Initialize the BD for every fragment in the page. */
+		bdp->cbd_sc = 0;
+		bdp++;
+	}
 
-	/* Queue up command to detect the PHY and initialize the
-	 * remainder of the interface.
-	 */
-	fep->phy_id_done = 0;
-	fep->phy_addr = 0;
-	mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	/* ...and the same for transmit */
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+
+		/* Initialize the BD for every fragment in the page. */
+		bdp->cbd_sc = 0;
+		bdp->cbd_bufaddr = 0;
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	fec_restart(dev, 0);
 
 	return 0;
 }
@@ -1730,13 +1262,20 @@ static void
 fec_restart(struct net_device *dev, int duplex)
 {
 	struct fec_enet_private *fep = netdev_priv(dev);
-	struct bufdesc *bdp;
 	int i;
+	uint ret = 0;
+	u32 temp_mac[2];
+	unsigned long reg;
 
 	/* Whack a reset.  We should wait for this. */
 	writel(1, fep->hwp + FEC_ECNTRL);
 	udelay(10);
 
+	/* Reset fec will reset MAC to zero, reconfig it again */
+	memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+	writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+	writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+
 	/* Clear any outstanding interrupt. */
 	writel(0xffc00000, fep->hwp + FEC_IEVENT);
 
@@ -1748,6 +1287,30 @@ fec_restart(struct net_device *dev, int duplex)
 	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
 #endif
 
+#ifndef CONFIG_ARCH_MXS
+	if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
+		unsigned int val;
+		/*
+		 * Set up the MII gasket for RMII mode
+		 */
+
+		/* disable the gasket and wait */
+		__raw_writel(0, fep->hwp + FEC_MIIGSK_ENR);
+		while (__raw_readl(fep->hwp + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
+			udelay(1);
+
+		val = FEC_MIIGSK_CFGR_IF_MODE_RMII;
+		if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
+			val |= FEC_MIIGSK_CFGR_FRCONT;
+		__raw_writel(val, fep->hwp + FEC_MIIGSK_CFGR);
+
+		/* re-enable the gasket */
+		__raw_writel(FEC_MIIGSK_ENR_EN, fep->hwp + FEC_MIIGSK_ENR);
+		while (!(__raw_readl(fep->hwp + FEC_MIIGSK_ENR)
+			& FEC_MIIGSK_ENR_READY))
+			udelay(1);
+	}
+#endif
 	/* Set maximum receive buffer size. */
 	writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
 
@@ -1768,33 +1331,6 @@ fec_restart(struct net_device *dev, int duplex)
 		}
 	}
 
-	/* Initialize the receive buffer descriptors. */
-	bdp = fep->rx_bd_base;
-	for (i = 0; i < RX_RING_SIZE; i++) {
-
-		/* Initialize the BD for every fragment in the page. */
-		bdp->cbd_sc = BD_ENET_RX_EMPTY;
-		bdp++;
-	}
-
-	/* Set the last buffer to wrap */
-	bdp--;
-	bdp->cbd_sc |= BD_SC_WRAP;
-
-	/* ...and the same for transmit */
-	bdp = fep->tx_bd_base;
-	for (i = 0; i < TX_RING_SIZE; i++) {
-
-		/* Initialize the BD for every fragment in the page. */
-		bdp->cbd_sc = 0;
-		bdp->cbd_bufaddr = 0;
-		bdp++;
-	}
-
-	/* Set the last buffer to wrap */
-	bdp--;
-	bdp->cbd_sc |= BD_SC_WRAP;
-
 	/* Enable MII mode */
 	if (duplex) {
 		/* MII enable / FD enable */
@@ -1807,16 +1343,53 @@ fec_restart(struct net_device *dev, int duplex)
 	}
 	fep->full_duplex = duplex;
 
+#ifdef CONFIG_ARCH_MXS
+
+	reg = readl(fep->hwp + FEC_R_CNTRL);
+
+	/* Enable flow control and length check */
+	reg |= (0x40000000 | 0x00000020);
+
+	/* Check MII or RMII */
+	if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+		reg |= 0x00000100;
+	else
+		reg &= ~0x00000100;
+
+	/* Check 10M or 100M */
+	if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
+		reg &= ~0x00000200; /* 100M */
+	else
+		reg |= 0x00000200;  /* 10M */
+
+	writel(reg, fep->hwp + FEC_R_CNTRL);
+
+#endif
 	/* Set MII speed */
 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
+	if (fep->ptimer_present) {
+		/* Set Timer count */
+		ret = fec_ptp_start(fep->ptp_priv);
+		if (ret) {
+			fep->ptimer_present = 0;
+			reg = 0x0;
+		} else
+			reg = 0x00000010;
+	} else
+		reg = 0x0;
+
 	/* And last, enable the transmit and receive processing */
-	writel(2, fep->hwp + FEC_ECNTRL);
+	reg |= 0x00000002;
+	writel(reg, fep->hwp + FEC_ECNTRL);
 	writel(0, fep->hwp + FEC_R_DES_ACTIVE);
 
 	/* Enable interrupts we wish to service */
-	writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
-			fep->hwp + FEC_IMASK);
+	if (fep->ptimer_present)
+		writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_TS_AVAIL |
+				FEC_ENET_TS_TIMER, fep->hwp + FEC_IMASK);
+	else
+		writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->hwp + FEC_IMASK);
 }
 
 static void
@@ -1836,11 +1409,22 @@ fec_stop(struct net_device *dev)
 	writel(1, fep->hwp + FEC_ECNTRL);
 	udelay(10);
 
+#ifdef CONFIG_ARCH_MXS
+	/* Check MII or RMII */
+	if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+		writel(readl(fep->hwp + FEC_R_CNTRL) | 0x100,
+					fep->hwp + FEC_R_CNTRL);
+	else
+		writel(readl(fep->hwp + FEC_R_CNTRL) & ~0x100,
+					fep->hwp + FEC_R_CNTRL);
+#endif
 	/* Clear outstanding MII command interrupts. */
 	writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
 
-	writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+
+	if (fep->ptimer_present)
+		fec_ptp_stop(fep->ptp_priv);
 }
 
 static int __devinit
@@ -1850,6 +1434,7 @@ fec_probe(struct platform_device *pdev)
 	struct net_device *ndev;
 	int i, irq, ret = 0;
 	struct resource *r;
+	struct fec_platform_data *pdata = pdev->dev.platform_data;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!r)
@@ -1871,6 +1456,7 @@ fec_probe(struct platform_device *pdev)
 	memset(fep, 0, sizeof(*fep));
 
 	ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
+	fep->pdev = pdev;
 
 	if (!ndev->base_addr) {
 		ret = -ENOMEM;
@@ -1902,17 +1488,66 @@ fec_probe(struct platform_device *pdev)
 	}
 	clk_enable(fep->clk);
 
+	/* PHY reset should be done during clock on */
+	if (pdata) {
+		fep->phy_interface = pdata->phy;
+		if (pdata->init && pdata->init())
+			goto failed_platform_init;
+
+		/*
+		 * The priority for getting MAC address is:
+		 * (1) kernel command line fec_mac = xx:xx:xx...
+		 * (2) platform data mac field got from fuse etc
+		 * (3) bootloader set the FEC mac register
+		 */
+
+		if (!is_valid_ether_addr(fec_mac_default) &&
+			pdata->mac && is_valid_ether_addr(pdata->mac))
+			memcpy(fec_mac_default, pdata->mac,
+						sizeof(fec_mac_default));
+	} else
+		fep->phy_interface = PHY_INTERFACE_MODE_MII;
+
 	ret = fec_enet_init(ndev, 0);
 	if (ret)
 		goto failed_init;
 
+	if (pdev->id == 0) {
+		fec_mii_bus = fec_enet_mii_init(pdev);
+		if (IS_ERR(fec_mii_bus)) {
+			ret = -ENOMEM;
+			goto failed_mii_init;
+		}
+	} else {
+		fep->mii_bus = fec_mii_bus;
+	}
+
+	fep->ptp_priv = kzalloc(sizeof(struct fec_ptp_private), GFP_KERNEL);
+	if (fep->ptp_priv) {
+		fep->ptp_priv->hwp = fep->hwp;
+		ret = fec_ptp_init(fep->ptp_priv, pdev->id);
+		if (ret)
+			printk(KERN_WARNING
+					"IEEE1588: ptp-timer is unavailable\n");
+		else
+			fep->ptimer_present = 1;
+	} else
+		printk(KERN_ERR "IEEE1588: failed to malloc memory\n");
+
 	ret = register_netdev(ndev);
 	if (ret)
 		goto failed_register;
 
+	clk_disable(fep->clk);
+
 	return 0;
 
 failed_register:
+	fec_enet_mii_remove(fep);
+	if (fep->ptimer_present)
+		fec_ptp_cleanup(fep->ptp_priv);
+	kfree(fep->ptp_priv);
+failed_mii_init:
 failed_init:
 	clk_disable(fep->clk);
 	clk_put(fep->clk);
@@ -1925,6 +1560,7 @@ failed_clk:
 failed_irq:
 	iounmap((void __iomem *)ndev->base_addr);
 failed_ioremap:
+failed_platform_init:
 	free_netdev(ndev);
 
 	return ret;
@@ -1935,13 +1571,20 @@ fec_drv_remove(struct platform_device *pdev)
 {
 	struct net_device *ndev = platform_get_drvdata(pdev);
 	struct fec_enet_private *fep = netdev_priv(ndev);
+	struct fec_platform_data *pdata = pdev->dev.platform_data;
 
 	platform_set_drvdata(pdev, NULL);
 
 	fec_stop(ndev);
+	fec_enet_mii_remove(fep);
+	if (pdata && pdata->uninit)
+		pdata->uninit();
 	clk_disable(fep->clk);
 	clk_put(fep->clk);
 	iounmap((void __iomem *)ndev->base_addr);
+	if (fep->ptimer_present)
+		fec_ptp_cleanup(fep->ptp_priv);
+	kfree(fep->ptp_priv);
 	unregister_netdev(ndev);
 	free_netdev(ndev);
 	return 0;
@@ -1958,8 +1601,10 @@ fec_suspend(struct platform_device *dev, pm_message_t state)
 		if (netif_running(ndev)) {
 			netif_device_detach(ndev);
 			fec_stop(ndev);
+			clk_disable(fep->clk);
 		}
 	}
+
 	return 0;
 }
 
@@ -1967,10 +1612,13 @@ static int
 fec_resume(struct platform_device *dev)
 {
 	struct net_device *ndev = platform_get_drvdata(dev);
+	struct fec_enet_private *fep;
 
 	if (ndev) {
+		fep = netdev_priv(ndev);
 		if (netif_running(ndev)) {
-			fec_enet_init(ndev, 0);
+			clk_enable(fep->clk);
+			fec_restart(ndev, fep->full_duplex);
 			netif_device_attach(ndev);
 		}
 	}
diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index cc47f3f057c7..d20d71eff12c 100644
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -12,9 +12,12 @@
 #ifndef FEC_H
 #define	FEC_H
 /****************************************************************************/
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
 
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
 /*
  *	Just figures, Motorola would have to change the offsets for
  *	registers in the same peripheral device on different models
@@ -43,6 +46,17 @@
 #define FEC_R_DES_START		0x180 /* Receive descriptor ring */
 #define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
 #define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
+#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK config register */
+#define FEC_MIIGSK_ENR		0x308 /* MIIGSK enable register */
+
+/* Define the FEC 1588 registers offset */
+#define FEC_ATIME_CTRL		0x400
+#define FEC_ATIME		0x404
+#define FEC_ATIME_EVT_OFFSET    0x408
+#define FEC_ATIME_EVT_PERIOD	0x40c
+#define FEC_ATIME_CORR		0x410
+#define FEC_ATIME_INC		0x414
+#define FEC_TS_TIMESTAMP	0x418
 
 #else
 
@@ -69,19 +83,28 @@
 #define FEC_X_DES_START		0x3d4 /* Transmit descriptor ring */
 #define FEC_R_BUFF_SIZE		0x3d8 /* Maximum receive buff size */
 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
+#define FEC_MIIGSK_CFGR		0x000 /* MIIGSK config register */
+#define FEC_MIIGSK_ENR		0x000 /* MIIGSK enable register */
 
 #endif /* CONFIG_M5272 */
 
-
 /*
  *	Define the buffer descriptor structure.
  */
-#ifdef CONFIG_ARCH_MXC
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
 struct bufdesc {
 	unsigned short cbd_datlen;	/* Data length */
 	unsigned short cbd_sc;	/* Control and status info */
 	unsigned long cbd_bufaddr;	/* Buffer address */
+#ifdef CONFIG_FEC_1588
+	unsigned long cbd_esc;
+	unsigned long cbd_prot;
+	unsigned long cbd_bdu;
+	unsigned long ts;
+	unsigned short res0[4];
+#endif
 };
+
 #else
 struct bufdesc {
 	unsigned short	cbd_sc;			/* Control and status info */
@@ -123,6 +146,8 @@ struct bufdesc {
 #define BD_ENET_RX_CL           ((ushort)0x0001)
 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
 
+#define BD_ENET_RX_INT		0x00800000
+
 /* Buffer descriptor control/status used by Ethernet transmit.
 */
 #define BD_ENET_TX_READY        ((ushort)0x8000)
@@ -140,6 +165,7 @@ struct bufdesc {
 #define BD_ENET_TX_CSL          ((ushort)0x0001)
 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 
+#define BD_ENET_TX_INT		0x40000000
 
 /****************************************************************************/
 #endif /* FEC_H */
diff --git a/drivers/net/fec_1588.c b/drivers/net/fec_1588.c
new file mode 100644
index 000000000000..c4bf278c7f19
--- /dev/null
+++ b/drivers/net/fec_1588.c
@@ -0,0 +1,581 @@
+/*
+ * drivers/net/fec_1588.c
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009 IXXAT Automation, GmbH
+ *
+ * FEC Ethernet Driver -- IEEE 1588 interface functionality
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/ip.h>
+#include <linux/udp.h>
+#include "fec.h"
+#include "fec_1588.h"
+
+static DECLARE_WAIT_QUEUE_HEAD(ptp_rx_ts_wait);
+#define PTP_GET_RX_TIMEOUT      (HZ/10)
+
+static struct fec_ptp_private *ptp_private[2];
+
+/* Alloc the ring resource */
+static int fec_ptp_init_circ(struct circ_buf *ptp_buf)
+{
+	ptp_buf->buf = vmalloc(DEFAULT_PTP_RX_BUF_SZ *
+					sizeof(struct fec_ptp_data_t));
+
+	if (!ptp_buf->buf)
+		return 1;
+	ptp_buf->head = 0;
+	ptp_buf->tail = 0;
+
+	return 0;
+}
+
+static inline int fec_ptp_calc_index(int size, int curr_index, int offset)
+{
+	return (curr_index + offset) % size;
+}
+
+static int fec_ptp_is_empty(struct circ_buf *buf)
+{
+	return (buf->head == buf->tail);
+}
+
+static int fec_ptp_nelems(struct circ_buf *buf)
+{
+	const int front = buf->head;
+	const int end = buf->tail;
+	const int size = DEFAULT_PTP_RX_BUF_SZ;
+	int n_items;
+
+	if (end > front)
+		n_items = end - front;
+	else if (end < front)
+		n_items = size - (front - end);
+	else
+		n_items = 0;
+
+	return n_items;
+}
+
+static int fec_ptp_is_full(struct circ_buf *buf)
+{
+	if (fec_ptp_nelems(buf) ==
+				(DEFAULT_PTP_RX_BUF_SZ - 1))
+		return 1;
+	else
+		return 0;
+}
+
+static int fec_ptp_insert(struct circ_buf *ptp_buf,
+			  struct fec_ptp_data_t *data,
+			  struct fec_ptp_private *priv)
+{
+	struct fec_ptp_data_t *tmp;
+
+	if (fec_ptp_is_full(ptp_buf))
+		return 1;
+
+	spin_lock(&priv->ptp_lock);
+	tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + ptp_buf->tail;
+
+	tmp->key = data->key;
+	tmp->ts_time.sec = data->ts_time.sec;
+	tmp->ts_time.nsec = data->ts_time.nsec;
+
+	ptp_buf->tail = fec_ptp_calc_index(DEFAULT_PTP_RX_BUF_SZ,
+					ptp_buf->tail, 1);
+	spin_unlock(&priv->ptp_lock);
+
+	return 0;
+}
+
+static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf,
+				   int key,
+				   struct fec_ptp_data_t *data,
+				   struct fec_ptp_private *priv)
+{
+	int i;
+	int size = DEFAULT_PTP_RX_BUF_SZ;
+	int end = ptp_buf->tail;
+	unsigned long flags;
+	struct fec_ptp_data_t *tmp;
+
+	if (fec_ptp_is_empty(ptp_buf))
+		return 1;
+
+	i = ptp_buf->head;
+	while (i != end) {
+		tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + i;
+		if (tmp->key == key)
+			break;
+		i = fec_ptp_calc_index(size, i, 1);
+	}
+
+	spin_lock_irqsave(&priv->ptp_lock, flags);
+	if (i == end) {
+		ptp_buf->head = end;
+		spin_unlock_irqrestore(&priv->ptp_lock, flags);
+		return 1;
+	}
+
+	data->ts_time.sec = tmp->ts_time.sec;
+	data->ts_time.nsec = tmp->ts_time.nsec;
+
+	ptp_buf->head = fec_ptp_calc_index(size, i, 1);
+	spin_unlock_irqrestore(&priv->ptp_lock, flags);
+
+	return 0;
+}
+
+/* 1588 Module intialization */
+int fec_ptp_start(struct fec_ptp_private *priv)
+{
+	struct fec_ptp_private *fpp = priv;
+
+	/* Select 1588 Timer source and enable module for starting Tmr Clock */
+	writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL);
+	writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, fpp->hwp + FEC_ATIME_INC);
+	writel(FEC_T_PERIOD_ONE_SEC, fpp->hwp + FEC_ATIME_EVT_PERIOD);
+	/* start counter */
+	writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE,
+			fpp->hwp + FEC_ATIME_CTRL);
+
+	return 0;
+}
+
+/* Cleanup routine for 1588 module.
+ * When PTP is disabled this routing is called */
+void fec_ptp_stop(struct fec_ptp_private *priv)
+{
+	struct fec_ptp_private *fpp = priv;
+
+	writel(0, fpp->hwp + FEC_ATIME_CTRL);
+	writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL);
+
+}
+
+static void fec_get_curr_cnt(struct fec_ptp_private *priv,
+			struct ptp_rtc_time *curr_time)
+{
+	u32 tempval;
+
+	writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL);
+	writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL);
+	curr_time->rtc_time.nsec = readl(priv->hwp + FEC_ATIME);
+	curr_time->rtc_time.sec = priv->prtc;
+
+	writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL);
+	tempval = readl(priv->hwp + FEC_ATIME);
+	if (tempval < curr_time->rtc_time.nsec) {
+		curr_time->rtc_time.nsec = tempval;
+		curr_time->rtc_time.sec = priv->prtc;
+	}
+}
+
+/* Set the 1588 timer counter registers */
+static void fec_set_1588cnt(struct fec_ptp_private *priv,
+			struct ptp_rtc_time *fec_time)
+{
+	u32 tempval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->cnt_lock, flags);
+	priv->prtc = fec_time->rtc_time.sec;
+
+	tempval = fec_time->rtc_time.nsec;
+	writel(tempval, priv->hwp + FEC_ATIME);
+	spin_unlock_irqrestore(&priv->cnt_lock, flags);
+}
+
+/* Set the BD to ptp */
+int fec_ptp_do_txstamp(struct sk_buff *skb)
+{
+	struct iphdr *iph;
+	struct udphdr *udph;
+
+	if (skb->len > 44) {
+		/* Check if port is 319 for PTP Event, and check for UDP */
+		iph = ip_hdr(skb);
+		if (iph == NULL || iph->protocol != FEC_PACKET_TYPE_UDP)
+			return 0;
+
+		udph = udp_hdr(skb);
+		if (udph != NULL && ntohs(udph->source) == 319)
+			return 1;
+	}
+
+	return 0;
+}
+
+void fec_ptp_store_txstamp(struct fec_ptp_private *priv)
+{
+	struct fec_ptp_private *fpp = priv;
+	unsigned int reg;
+
+	reg = readl(fpp->hwp + FEC_TS_TIMESTAMP);
+	fpp->txstamp.nsec = reg;
+	fpp->txstamp.sec = fpp->prtc;
+}
+
+void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
+			   struct sk_buff *skb,
+			   struct bufdesc *bdp)
+{
+	int msg_type, seq_id, control;
+	struct fec_ptp_data_t tmp_rx_time;
+	struct fec_ptp_private *fpp = priv;
+	struct iphdr *iph;
+	struct udphdr *udph;
+
+	/* Check for UDP, and Check if port is 319 for PTP Event */
+	iph = (struct iphdr *)(skb->data + FEC_PTP_IP_OFFS);
+	if (iph->protocol != FEC_PACKET_TYPE_UDP)
+		return;
+
+	udph = (struct udphdr *)(skb->data + FEC_PTP_UDP_OFFS);
+	if (ntohs(udph->source) != 319)
+		return;
+
+	seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS));
+	control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS));
+
+	tmp_rx_time.key = ntohs(seq_id);
+	tmp_rx_time.ts_time.sec = fpp->prtc;
+	tmp_rx_time.ts_time.nsec = bdp->ts;
+
+	switch (control) {
+
+	case PTP_MSG_SYNC:
+		fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, priv);
+		break;
+
+	case PTP_MSG_DEL_REQ:
+		fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, priv);
+		break;
+
+	/* clear transportSpecific field*/
+	case PTP_MSG_ALL_OTHER:
+		msg_type = (*((u8 *)(skb->data +
+				FEC_PTP_MSG_TYPE_OFFS))) & 0x0F;
+		switch (msg_type) {
+		case PTP_MSG_P_DEL_REQ:
+			fec_ptp_insert(&(priv->rx_time_pdel_req),
+						&tmp_rx_time, priv);
+			break;
+		case PTP_MSG_P_DEL_RESP:
+			fec_ptp_insert(&(priv->rx_time_pdel_resp),
+					&tmp_rx_time, priv);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+	wake_up_interruptible(&ptp_rx_ts_wait);
+}
+
+static void fec_get_tx_timestamp(struct fec_ptp_private *priv,
+				 struct ptp_time *tx_time)
+{
+	tx_time->sec = priv->txstamp.sec;
+	tx_time->nsec = priv->txstamp.nsec;
+}
+
+static uint8_t fec_get_rx_time(struct fec_ptp_private *priv,
+			       struct ptp_ts_data *pts,
+			       struct ptp_time *rx_time)
+{
+	struct fec_ptp_data_t tmp;
+	int key, flag;
+	u8 mode;
+
+	key = pts->seq_id;
+	mode = pts->message_type;
+	switch (mode) {
+	case PTP_MSG_SYNC:
+		flag = fec_ptp_find_and_remove(&(priv->rx_time_sync),
+						key, &tmp, priv);
+		break;
+	case PTP_MSG_DEL_REQ:
+		flag = fec_ptp_find_and_remove(&(priv->rx_time_del_req),
+						key, &tmp, priv);
+		break;
+
+	case PTP_MSG_P_DEL_REQ:
+		flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_req),
+						key, &tmp, priv);
+		break;
+	case PTP_MSG_P_DEL_RESP:
+		flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_resp),
+						key, &tmp, priv);
+		break;
+
+	default:
+		flag = 1;
+		printk(KERN_ERR "ERROR\n");
+		break;
+	}
+
+	if (!flag) {
+		rx_time->sec = tmp.ts_time.sec;
+		rx_time->nsec = tmp.ts_time.nsec;
+		return 0;
+	} else {
+		wait_event_interruptible_timeout(ptp_rx_ts_wait, 0,
+					PTP_GET_RX_TIMEOUT);
+
+		switch (mode) {
+		case PTP_MSG_SYNC:
+			flag = fec_ptp_find_and_remove(&(priv->rx_time_sync),
+				key, &tmp, priv);
+			break;
+		case PTP_MSG_DEL_REQ:
+			flag = fec_ptp_find_and_remove(
+				&(priv->rx_time_del_req), key, &tmp, priv);
+			break;
+		case PTP_MSG_P_DEL_REQ:
+			flag = fec_ptp_find_and_remove(
+				&(priv->rx_time_pdel_req), key, &tmp, priv);
+			break;
+		case PTP_MSG_P_DEL_RESP:
+			flag = fec_ptp_find_and_remove(
+				&(priv->rx_time_pdel_resp), key, &tmp, priv);
+			break;
+		}
+
+		if (flag == 0) {
+			rx_time->sec = tmp.ts_time.sec;
+			rx_time->nsec = tmp.ts_time.nsec;
+			return 0;
+		}
+
+		return -1;
+	}
+}
+
+static void fec_handle_ptpdrift(struct ptp_set_comp *comp,
+				struct ptp_time_correct *ptc)
+{
+	u32 ndrift;
+	u32 i;
+	u32 tmp, tmp_ns, tmp_prid;
+	u32 min_ns, min_prid, miss_ns;
+
+	ndrift = comp->drift;
+	if (ndrift == 0) {
+		ptc->corr_inc = 0;
+		ptc->corr_period = 0;
+		return;
+	}
+
+	if (ndrift >= FEC_ATIME_40MHZ) {
+		ptc->corr_inc = (u32)(ndrift / FEC_ATIME_40MHZ);
+		ptc->corr_period = 1;
+		return;
+	}
+
+	min_ns = 1;
+	tmp = FEC_ATIME_40MHZ % ndrift;
+	tmp_prid = (u32)(FEC_ATIME_40MHZ / ndrift);
+	min_prid = tmp_prid;
+	miss_ns = tmp / tmp_prid;
+	for (i = 2; i <= FEC_T_INC_40MHZ; i++) {
+		tmp = (FEC_ATIME_40MHZ * i) % ndrift;
+		tmp_prid = (FEC_ATIME_40MHZ * i) / ndrift;
+		tmp_ns = tmp / tmp_prid;
+		if (tmp_ns <= 10) {
+			min_ns = i;
+			min_prid = tmp_prid;
+			break;
+		}
+		if (tmp_ns < miss_ns) {
+			min_ns = i;
+			min_prid = tmp_prid;
+			miss_ns = tmp_ns;
+		}
+	}
+
+	ptc->corr_inc = min_ns;
+	ptc->corr_period = min_prid;
+}
+
+static void fec_set_drift(struct fec_ptp_private *priv,
+			  struct ptp_set_comp *comp)
+{
+	struct ptp_time_correct	tc;
+	struct fec_ptp_private *fpp = priv;
+	u32 tmp, corr_ns;
+
+	fec_handle_ptpdrift(comp, &tc);
+	if (tc.corr_inc == 0)
+		return;
+
+	if (comp->o_ops == TRUE)
+		corr_ns = FEC_T_INC_40MHZ + tc.corr_inc;
+	else
+		corr_ns = FEC_T_INC_40MHZ - tc.corr_inc;
+
+	tmp = readl(fpp->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
+	tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
+	writel(tmp, fpp->hwp + FEC_ATIME_INC);
+
+	writel(tc.corr_period, fpp->hwp + FEC_ATIME_CORR);
+}
+
+static int ptp_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int ptp_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int ptp_ioctl(
+	struct inode *inode,
+	struct file *file,
+	unsigned int cmd,
+	unsigned long arg)
+{
+	struct ptp_rtc_time *cnt;
+	struct ptp_rtc_time curr_time;
+	struct ptp_time rx_time, tx_time;
+	struct ptp_ts_data *p_ts;
+	struct ptp_set_comp *p_comp;
+	struct fec_ptp_private *priv;
+	unsigned int minor = MINOR(inode->i_rdev);
+	int retval = 0;
+
+	priv = (struct fec_ptp_private *) ptp_private[minor];
+	switch (cmd) {
+	case PTP_GET_RX_TIMESTAMP:
+		p_ts = (struct ptp_ts_data *)arg;
+		retval = fec_get_rx_time(priv, p_ts, &rx_time);
+		if (retval == 0)
+			copy_to_user((void __user *)(&(p_ts->ts)), &rx_time,
+					sizeof(rx_time));
+		break;
+	case PTP_GET_TX_TIMESTAMP:
+		p_ts = (struct ptp_ts_data *)arg;
+		fec_get_tx_timestamp(priv, &tx_time);
+		copy_to_user((void __user *)(&(p_ts->ts)), &tx_time,
+				sizeof(tx_time));
+		break;
+	case PTP_GET_CURRENT_TIME:
+		fec_get_curr_cnt(priv, &curr_time);
+		copy_to_user((void __user *)arg, &curr_time, sizeof(curr_time));
+		break;
+	case PTP_SET_RTC_TIME:
+		cnt = (struct ptp_rtc_time *)arg;
+		fec_set_1588cnt(priv, cnt);
+		break;
+	case PTP_FLUSH_TIMESTAMP:
+		/* reset sync buffer */
+		priv->rx_time_sync.head = 0;
+		priv->rx_time_sync.tail = 0;
+		/* reset delay_req buffer */
+		priv->rx_time_del_req.head = 0;
+		priv->rx_time_del_req.tail = 0;
+		/* reset pdelay_req buffer */
+		priv->rx_time_pdel_req.head = 0;
+		priv->rx_time_pdel_req.tail = 0;
+		/* reset pdelay_resp buffer */
+		priv->rx_time_pdel_resp.head = 0;
+		priv->rx_time_pdel_resp.tail = 0;
+		break;
+	case PTP_SET_COMPENSATION:
+		p_comp = (struct ptp_set_comp *)arg;
+		fec_set_drift(priv, p_comp);
+		break;
+	case PTP_GET_ORIG_COMP:
+		((struct ptp_get_comp *)arg)->dw_origcomp = FEC_PTP_ORIG_COMP;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return retval;
+}
+
+static const struct file_operations ptp_fops = {
+	.owner	= THIS_MODULE,
+	.llseek	= NULL,
+	.read	= NULL,
+	.write	= NULL,
+	.ioctl	= ptp_ioctl,
+	.open	= ptp_open,
+	.release = ptp_release,
+};
+
+static int init_ptp(void)
+{
+	if (register_chrdev(PTP_MAJOR, "ptp", &ptp_fops))
+		printk(KERN_ERR "Unable to register PTP deivce as char\n");
+
+	return 0;
+}
+
+static void ptp_free(void)
+{
+	/*unregister the PTP device*/
+	unregister_chrdev(PTP_MAJOR, "ptp");
+}
+
+/*
+ * Resource required for accessing 1588 Timer Registers.
+ */
+int fec_ptp_init(struct fec_ptp_private *priv, int id)
+{
+	fec_ptp_init_circ(&(priv->rx_time_sync));
+	fec_ptp_init_circ(&(priv->rx_time_del_req));
+	fec_ptp_init_circ(&(priv->rx_time_pdel_req));
+	fec_ptp_init_circ(&(priv->rx_time_pdel_resp));
+
+	spin_lock_init(&priv->ptp_lock);
+	spin_lock_init(&priv->cnt_lock);
+	ptp_private[id] = priv;
+	if (id == 0)
+		init_ptp();
+	return 0;
+}
+EXPORT_SYMBOL(fec_ptp_init);
+
+void fec_ptp_cleanup(struct fec_ptp_private *priv)
+{
+
+	if (priv->rx_time_sync.buf)
+		vfree(priv->rx_time_sync.buf);
+	if (priv->rx_time_del_req.buf)
+		vfree(priv->rx_time_del_req.buf);
+	if (priv->rx_time_pdel_req.buf)
+		vfree(priv->rx_time_pdel_req.buf);
+	if (priv->rx_time_pdel_resp.buf)
+		vfree(priv->rx_time_pdel_resp.buf);
+
+	ptp_free();
+}
+EXPORT_SYMBOL(fec_ptp_cleanup);
diff --git a/drivers/net/fec_1588.h b/drivers/net/fec_1588.h
new file mode 100644
index 000000000000..800ff310668f
--- /dev/null
+++ b/drivers/net/fec_1588.h
@@ -0,0 +1,190 @@
+/*
+ * drivers/net/fec_1588.h
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef FEC_1588_H
+#define FEC_1588_H
+
+#include <linux/circ_buf.h>
+
+#define FALSE			0
+#define TRUE			1
+
+/* FEC 1588 register bits */
+#define FEC_T_CTRL_CAPTURE		0x00000800
+#define FEC_T_CTRL_RESTART		0x00000200
+#define FEC_T_CTRL_PERIOD_RST		0x00000030
+#define FEC_T_CTRL_ENABLE		0x00000001
+
+#define FEC_T_INC_MASK			0x0000007f
+#define FEC_T_INC_OFFSET		0
+#define FEC_T_INC_CORR_MASK		0x00007f00
+#define FEC_T_INC_CORR_OFFSET		8
+
+#define FEC_T_INC_40MHZ			25
+#define FEC_ATIME_40MHZ			40000000
+
+#define FEC_T_PERIOD_ONE_SEC		0x3B9ACA00
+
+/* IEEE 1588 definition */
+#define FEC_ECNTRL_TS_EN	0x10
+#define PTP_MAJOR		232	/*the temporary major number
+						 *used by PTP driver, the major
+						 *number 232~239 is unassigned*/
+
+#define DEFAULT_PTP_RX_BUF_SZ		2048
+#define PTP_MSG_SYNC			0x0
+#define PTP_MSG_DEL_REQ			0x1
+#define PTP_MSG_P_DEL_REQ		0x2
+#define PTP_MSG_P_DEL_RESP		0x3
+#define PTP_MSG_DEL_RESP		0x4
+#define PTP_MSG_ALL_OTHER		0x5
+
+#define PTP_GET_TX_TIMESTAMP		0x1
+#define PTP_GET_RX_TIMESTAMP		0x9
+#define PTP_SET_RTC_TIME		0x3
+#define PTP_SET_COMPENSATION		0x4
+#define PTP_GET_CURRENT_TIME		0x5
+#define PTP_FLUSH_TIMESTAMP		0x6
+#define PTP_ADJ_ADDEND			0x7
+#define PTP_GET_ORIG_COMP		0x8
+#define PTP_GET_ADDEND			0xB
+#define PTP_GET_RX_TIMESTAMP_PDELAY_REQ		0xC
+#define PTP_GET_RX_TIMESTAMP_PDELAY_RESP	0xD
+
+#define FEC_PTP_DOMAIN_DLFT		0xe0000181
+#define FEC_PTP_IP_OFFS			0x0
+#define FEC_PTP_UDP_OFFS		0x14
+#define FEC_PTP_MSG_TYPE_OFFS		0x1C
+#define FEC_PTP_SEQ_ID_OFFS		0x3A
+#define FEC_PTP_CTRL_OFFS		0x3C
+#define FEC_PACKET_TYPE_UDP		0x11
+
+#define FEC_PTP_ORIG_COMP		0x15555555
+
+/* PTP standard time representation structure */
+struct ptp_time{
+	u64 sec;	/* seconds */
+	u32 nsec;	/* nanoseconds */
+};
+
+/* Structure for PTP Time Stamp */
+struct fec_ptp_data_t {
+	int		key;
+	struct ptp_time	ts_time;
+};
+
+/* interface for PTP driver command GET_TX_TIME */
+struct ptp_ts_data {
+	/* PTP version */
+	u8 version;
+	/* PTP source port ID */
+	u8 spid[10];
+	/* PTP sequence ID */
+	u16 seq_id;
+	/* PTP message type */
+	u8 message_type;
+	/* PTP timestamp */
+	struct ptp_time ts;
+};
+
+/* interface for PTP driver command SET_RTC_TIME/GET_CURRENT_TIME */
+struct ptp_rtc_time {
+	struct ptp_time rtc_time;
+};
+
+/* interface for PTP driver command SET_COMPENSATION */
+struct ptp_set_comp {
+	u32 drift;
+	bool o_ops;
+};
+
+/* interface for PTP driver command GET_ORIG_COMP */
+struct ptp_get_comp {
+	/* the initial compensation value */
+	u32 dw_origcomp;
+	/* the minimum compensation value */
+	u32 dw_mincomp;
+	/*the max compensation value*/
+	u32 dw_maxcomp;
+	/*the min drift applying min compensation value in ppm*/
+	u32 dw_mindrift;
+	/*the max drift applying max compensation value in ppm*/
+	u32 dw_maxdrift;
+};
+
+struct ptp_time_correct {
+	u32 corr_period;
+	u32 corr_inc;
+};
+
+/* PTP message version */
+#define PTP_1588_MSG_VER_1	1
+#define PTP_1588_MSG_VER_2	2
+
+#define BD_ENET_TX_TS		0x20000000
+#define BD_ENET_TX_BDU		0x80000000
+
+struct fec_ptp_private {
+	void __iomem *hwp;
+
+	struct	circ_buf rx_time_sync;
+	struct	circ_buf rx_time_del_req;
+	struct	circ_buf rx_time_pdel_req;
+	struct	circ_buf rx_time_pdel_resp;
+	spinlock_t ptp_lock;
+	spinlock_t cnt_lock;
+
+	u64	prtc;
+	struct ptp_time	txstamp;
+};
+
+#ifdef CONFIG_FEC_1588
+extern int fec_ptp_init(struct fec_ptp_private *priv, int id);
+extern void fec_ptp_cleanup(struct fec_ptp_private *priv);
+extern int fec_ptp_start(struct fec_ptp_private *priv);
+extern void fec_ptp_stop(struct fec_ptp_private *priv);
+extern int fec_ptp_do_txstamp(struct sk_buff *skb);
+extern void fec_ptp_store_txstamp(struct fec_ptp_private *priv);
+extern void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
+				  struct sk_buff *skb,
+				  struct bufdesc *bdp);
+#else
+static inline int fec_ptp_init(struct fec_ptp_private *priv, int id)
+{
+	return 1;
+}
+static inline void fec_ptp_cleanup(struct fec_ptp_private *priv) { }
+static inline int fec_ptp_start(struct fec_ptp_private *priv)
+{
+	return 1;
+}
+static inline void fec_ptp_stop(struct fec_ptp_private *priv) {}
+static inline int fec_ptp_do_txstamp(struct sk_buff *skb)
+{
+	return 0;
+}
+static inline void fec_ptp_store_txstamp(struct fec_ptp_private *priv) {}
+static inline void fec_ptp_store_rxstamp(struct fec_ptp_private *priv,
+					 struct sk_buff *skb,
+					 struct bufdesc *bdp) {}
+#endif /* 1588 */
+
+#endif
diff --git a/drivers/net/fec_switch.c b/drivers/net/fec_switch.c
new file mode 100644
index 000000000000..0485349dcd76
--- /dev/null
+++ b/drivers/net/fec_switch.c
@@ -0,0 +1,4255 @@
+/*
+ *  L2 switch Controller (Etheren switch) driver for Mx28.
+ *
+ *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    Shrek Wu (B16972@freescale.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/fec.h>
+#include <linux/phy.h>
+
+#include <asm/irq.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <asm/pgtable.h>
+#include <asm/cacheflush.h>
+
+#include "fec_switch.h"
+
+#define	SWITCH_MAX_PORTS	1
+
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
+#include <mach/hardware.h>
+#define FEC_ALIGNMENT   0xf
+#else
+#define FEC_ALIGNMENT   0x3
+#endif
+
+/* The number of Tx and Rx buffers.  These are allocated from the page
+ * pool.  The code may assume these are power of two, so it it best
+ * to keep them that size.
+ * We don't need to allocate pages for the transmitter.  We just use
+ * the skbuffer directly.
+ */
+#define FEC_ENET_RX_PAGES       8
+#define FEC_ENET_RX_FRSIZE      2048
+#define FEC_ENET_RX_FRPPG       (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
+#define FEC_ENET_TX_FRSIZE      2048
+#define FEC_ENET_TX_FRPPG       (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
+#define TX_RING_SIZE            16      /* Must be power of two */
+#define TX_RING_MOD_MASK        15      /*   for this to work */
+
+#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
+#error "FEC: descriptor ring size constants too large"
+#endif
+
+/* Interrupt events/masks */
+#define FEC_ENET_HBERR	((uint)0x80000000)	/* Heartbeat error */
+#define FEC_ENET_BABR	((uint)0x40000000)	/* Babbling receiver */
+#define FEC_ENET_BABT	((uint)0x20000000)	/* Babbling transmitter */
+#define FEC_ENET_GRA	((uint)0x10000000)	/* Graceful stop complete */
+#define FEC_ENET_TXF	((uint)0x08000000)	/* Full frame transmitted */
+#define FEC_ENET_TXB	((uint)0x04000000)	/* A buffer was transmitted */
+#define FEC_ENET_RXF	((uint)0x02000000)	/* Full frame received */
+#define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
+#define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
+#define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
+
+/* FEC MII MMFR bits definition */
+#define FEC_MMFR_ST             (1 << 30)
+#define FEC_MMFR_OP_READ        (2 << 28)
+#define FEC_MMFR_OP_WRITE       (1 << 28)
+#define FEC_MMFR_PA(v)          ((v & 0x1f) << 23)
+#define FEC_MMFR_RA(v)          ((v & 0x1f) << 18)
+#define FEC_MMFR_TA             (2 << 16)
+#define FEC_MMFR_DATA(v)        (v & 0xffff)
+
+#ifdef FEC_PHY
+static struct phy_device *g_phy_dev;
+static struct mii_bus *fec_mii_bus;
+#endif
+
+static int switch_enet_open(struct net_device *dev);
+static int switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
+static irqreturn_t switch_enet_interrupt(int irq, void *dev_id);
+static void switch_enet_tx(struct net_device *dev);
+static void switch_enet_rx(struct net_device *dev);
+static int switch_enet_close(struct net_device *dev);
+static void set_multicast_list(struct net_device *dev);
+static void switch_restart(struct net_device *dev, int duplex);
+static void switch_stop(struct net_device *dev);
+
+#define		NMII	20
+
+/* Make MII read/write commands for the FEC */
+#define mk_mii_read(REG)	(0x60020000 | ((REG & 0x1f) << 18))
+#define mk_mii_write(REG, VAL)	(0x50020000 | ((REG & 0x1f) << 18) | \
+						(VAL & 0xffff))
+
+/* Transmitter timeout */
+#define TX_TIMEOUT (2*HZ)
+#define FEC_MII_TIMEOUT	10
+
+#ifdef CONFIG_ARCH_MXS
+static void *swap_buffer(void *bufaddr, int len)
+{
+	int i;
+	unsigned int *buf = bufaddr;
+
+	for (i = 0; i < (len + 3) / 4; i++, buf++)
+		*buf = __swab32(*buf);
+
+	return bufaddr;
+}
+#endif
+
+/*last read entry from learning interface*/
+struct eswPortInfo g_info;
+
+#ifdef USE_DEFAULT_SWITCH_PORT0_MAC
+static unsigned char    switch_mac_default[] = {
+	0x00, 0x08, 0x02, 0x6B, 0xA3, 0x1A,
+};
+#else
+static unsigned char    switch_mac_default[ETH_ALEN];
+#endif
+
+static void switch_request_intrs(struct net_device *dev,
+	irqreturn_t switch_net_irq_handler(int irq, void *private),
+	void *irq_privatedata)
+{
+	struct switch_enet_private *fep;
+
+	fep = netdev_priv(dev);
+
+	/* Setup interrupt handlers */
+	if (request_irq(dev->irq,
+		switch_net_irq_handler, IRQF_DISABLED,
+		"mxs-l2switch", irq_privatedata) != 0)
+		printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n",
+			dev->name, dev->irq);
+}
+
+static void switch_set_mii(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct switch_t *fecp;
+
+	fecp = (struct switch_t *)fep->hwp;
+
+	writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
+			MCF_FEC_RCR_MAX_FL(1522),
+			fep->enet_addr + MCF_FEC_RCR0);
+	writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE |
+			MCF_FEC_RCR_MAX_FL(1522),
+			fep->enet_addr + MCF_FEC_RCR1);
+	/* TCR */
+	writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR0);
+	writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR1);
+
+	/* ECR */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588,
+			fep->enet_addr + MCF_FEC_ECR1);
+#else /*legac buffer*/
+	writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR1);
+#endif
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0);
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1);
+
+	/*
+	* Set MII speed to 2.5 MHz
+	*/
+	writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1,
+			fep->enet_addr + MCF_FEC_MSCR0);
+	writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1,
+			fep->enet_addr + MCF_FEC_MSCR1);
+
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/
+	fep->phy_speed = readl(fep->enet_addr + MCF_FEC_MSCR0) << 2;
+	writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR0);
+	writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR1);
+#endif
+
+}
+
+static void switch_get_mac(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	unsigned char *iap, tmpaddr[ETH_ALEN];
+	static int index;
+#ifdef CONFIG_M5272
+	if (FEC_FLASHMAC) {
+		/*
+		 * Get MAC address from FLASH.
+		 * If it is all 1's or 0's, use the default.
+		 */
+		iap = (unsigned char *)FEC_FLASHMAC;
+		if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
+		    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
+			iap = switch_mac_default;
+		if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
+		    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
+			iap = switch_mac_default;
+	}
+#else
+	if (is_valid_ether_addr(switch_mac_default))
+		iap = switch_mac_default;
+#endif
+	else {
+		*((unsigned long *) &tmpaddr[0]) =
+			be32_to_cpu(readl(fep->enet_addr
+			+ FEC_ADDR_LOW / sizeof(unsigned long)));
+		*((unsigned short *) &tmpaddr[4]) =
+			be16_to_cpu(readl(fep->enet_addr
+			+ FEC_ADDR_HIGH / sizeof(unsigned long)) >> 16);
+		iap = &tmpaddr[0];
+	}
+
+	memcpy(dev->dev_addr, iap, ETH_ALEN);
+
+	/* Adjust MAC if using default MAC address */
+	if (iap == switch_mac_default) {
+		dev->dev_addr[ETH_ALEN-1] =
+			switch_mac_default[ETH_ALEN-1] + index;
+		index++;
+	}
+}
+
+static void switch_enable_phy_intr(void)
+{
+}
+
+static void switch_disable_phy_intr(void)
+{
+}
+
+static void switch_phy_ack_intr(void)
+{
+}
+
+static void switch_localhw_setup(void)
+{
+}
+
+static void switch_uncache(unsigned long addr)
+{
+}
+
+static void switch_platform_flush_cache(void)
+{
+}
+
+/*
+ * Calculate Galois Field Arithmetic CRC for Polynom x^8+x^2+x+1.
+ * It omits the final shift in of 8 zeroes a "normal" CRC would do
+ * (getting the remainder).
+ *
+ *  Examples (hexadecimal values):<br>
+ *   10-11-12-13-14-15  => CRC=0xc2
+ *   10-11-cc-dd-ee-00  => CRC=0xe6
+ *
+ *   param: pmacaddress
+ *          A 6-byte array with the MAC address.
+ *          The first byte is the first byte transmitted
+ *   return The 8-bit CRC in bits 7:0
+ */
+static int crc8_calc(unsigned char *pmacaddress)
+{
+	/* byte index */
+	int byt;
+	/* bit index */
+	int bit;
+	int inval;
+	int crc;
+	/* preset */
+	crc   = 0x12;
+	for (byt = 0; byt < 6; byt++) {
+		inval = (((int)pmacaddress[byt]) & 0xff);
+		/*
+		 * shift bit 0 to bit 8 so all our bits
+		 * travel through bit 8
+		 * (simplifies below calc)
+		 */
+		inval <<= 8;
+
+		for (bit = 0; bit < 8; bit++) {
+			/* next input bit comes into d7 after shift */
+			crc |= inval & 0x100;
+			if (crc & 0x01)
+				/* before shift  */
+				crc ^= 0x1c0;
+
+			crc >>= 1;
+			inval >>= 1;
+		}
+
+	}
+	/* upper bits are clean as we shifted in zeroes! */
+	return crc;
+}
+
+static void read_atable(struct switch_enet_private *fep,
+	int index,
+	unsigned long *read_lo, unsigned long *read_hi)
+{
+	unsigned long atable_base = (unsigned long)fep->hwentry;
+
+	*read_lo = readl(atable_base + (index<<3));
+	*read_hi = readl(atable_base + (index<<3) + 4);
+}
+
+static void write_atable(struct switch_enet_private *fep,
+	int index,
+	unsigned long write_lo, unsigned long write_hi)
+{
+	unsigned long atable_base = (unsigned long)fep->hwentry;
+
+	writel(write_lo, atable_base + (index<<3));
+	writel(write_hi, atable_base + (index<<3) + 4);
+}
+
+/* Read one element from the HW receive FIFO (Queue)
+ * if available and return it.
+ * return ms_HwPortInfo or null if no data is available
+ */
+static struct eswPortInfo *esw_portinfofifo_read(
+	struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp;
+
+	fecp = fep->hwp;
+	if (fecp->ESW_LSR == 0) {
+		printk(KERN_ERR "%s: ESW_LSR = %lx\n",
+			__func__, fecp->ESW_LSR);
+		return NULL;
+	}
+	/* read word from FIFO */
+	g_info.maclo = fecp->ESW_LREC0;
+	/* but verify that we actually did so
+	 * (0=no data available)
+	 */
+	if (g_info.maclo == 0) {
+		printk(KERN_ERR "%s: mac lo %x\n",
+			__func__, g_info.maclo);
+		return NULL;
+	}
+	/* read 2nd word from FIFO */
+	tmp = fecp->ESW_LREC1;
+	g_info.machi = tmp & 0xffff;
+	g_info.hash  = (tmp >> 16) & 0xff;
+	g_info.port  = (tmp >> 24) & 0xf;
+
+	return &g_info;
+}
+
+
+/*
+ * Clear complete MAC Look Up Table
+ */
+static void esw_clear_atable(struct switch_enet_private *fep)
+{
+	int index;
+	for (index = 0; index < 2048; index++)
+		write_atable(fep, index, 0, 0);
+}
+
+/*
+ * pdates MAC address lookup table with a static entry
+ * Searches if the MAC address is already there in the block and replaces
+ * the older entry with new one. If MAC address is not there then puts a
+ * new entry in the first empty slot available in the block
+ *
+ * mac_addr Pointer to the array containing MAC address to
+ *          be put as static entry
+ * port     Port bitmask numbers to be added in static entry,
+ *          valid values are 1-7
+ * priority Priority for the static entry in table
+ *
+ * return 0 for a successful update else -1  when no slot available
+ */
+static int esw_update_atable_static(unsigned char *mac_addr,
+	unsigned int port, unsigned int priority,
+	struct switch_enet_private *fep)
+{
+	unsigned long block_index, entry, index_end;
+
+	unsigned long read_lo, read_hi;
+	unsigned long write_lo, write_hi;
+
+	write_lo = (unsigned long)((mac_addr[3] << 24) |
+			(mac_addr[2] << 16) |
+			(mac_addr[1] << 8) |
+			mac_addr[0]);
+	write_hi = (unsigned long)(0 |
+			(port << AT_SENTRY_PORTMASK_shift) |
+			(priority << AT_SENTRY_PRIO_shift) |
+			(AT_ENTRY_TYPE_STATIC << AT_ENTRY_TYPE_shift) |
+			(AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift) |
+			(mac_addr[5] << 8) | (mac_addr[4]));
+
+	block_index = GET_BLOCK_PTR(crc8_calc(mac_addr));
+	index_end = block_index + ATABLE_ENTRY_PER_SLOT;
+	/* Now search all the entries in the selected block */
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		/*
+		 * MAC address matched, so update the
+		 * existing entry
+		 * even if its a dynamic one
+		 */
+		if ((read_lo == write_lo) &&
+			((read_hi & 0x0000ffff) ==
+			 (write_hi & 0x0000ffff))) {
+			write_atable(fep, entry, write_lo, write_hi);
+			return 0;
+		} else if (!(read_hi & (1 << 16))) {
+			/*
+			 * Fill this empty slot (valid bit zero),
+			 * assuming no holes in the block
+			 */
+			write_atable(fep, entry, write_lo, write_hi);
+			fep->atCurrEntries++;
+			return 0;
+		}
+	}
+
+	/* No space available for this static entry */
+	return -1;
+}
+
+static int esw_update_atable_dynamic1(unsigned long write_lo,
+	unsigned long write_hi, int block_index,
+	unsigned int port, unsigned int currTime,
+	struct switch_enet_private *fep)
+{
+	unsigned long entry, index_end;
+	unsigned long read_lo, read_hi;
+	unsigned long tmp;
+	int time, timeold, indexold;
+
+	/* prepare update port and timestamp */
+	tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift;
+	tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift;
+	tmp |= currTime << AT_DENTRY_TIME_shift;
+	tmp |= port << AT_DENTRY_PORT_shift;
+	tmp |= write_hi;
+
+	/*
+	* linear search through all slot
+	* entries and update if found
+	*/
+	index_end = block_index + ATABLE_ENTRY_PER_SLOT;
+	/* Now search all the entries in the selected block */
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		if ((read_lo == write_lo) &&
+			((read_hi & 0x0000ffff) ==
+			(write_hi & 0x0000ffff))) {
+			/* found correct address,
+			 * update timestamp.
+			 */
+			write_atable(fep, entry, write_lo, tmp);
+			return 0;
+		} else if (!(read_hi & (1 << 16))) {
+			/* slot is empty, then use it
+			 * for new entry
+			 * Note: There are no holes,
+			 * therefore cannot be any
+			 * more that need to be compared.
+			 */
+			write_atable(fep, entry, write_lo, tmp);
+			/* statistics (we do it between writing
+			 *  .hi an .lo due to
+			 * hardware limitation...
+			 */
+			fep->atCurrEntries++;
+			/* newly inserted */
+			return 1;
+		}
+	}
+
+	/*
+	 * no more entry available in block ...
+	 * overwrite oldest
+	 */
+	timeold = 0;
+	indexold = 0;
+	for (entry = block_index; entry < index_end; entry++) {
+		read_atable(fep, entry, &read_lo, &read_hi);
+		time = AT_EXTRACT_TIMESTAMP(read_hi);
+		printk(KERN_ERR "%s : time %x currtime %x\n",
+			__func__, time, currTime);
+		time = TIMEDELTA(currTime, time);
+		if (time > timeold) {
+			/* is it older ? */
+			timeold = time;
+			indexold = entry;
+		}
+	}
+
+	write_atable(fep, indexold, write_lo, tmp);
+	/*
+	 * Statistics (do it inbetween
+	 *writing to .lo and .hi
+	 */
+	fep->atBlockOverflows++;
+	printk(KERN_ERR "%s update time, atBlockOverflows %x\n",
+		__func__, fep->atBlockOverflows);
+	/* newly inserted */
+	return 1;
+}
+
+/* dynamicms MAC address table learn and migration */
+static int esw_atable_dynamicms_learn_migration(
+	struct switch_enet_private *fep,
+	int currTime)
+{
+	struct eswPortInfo *pESWPortInfo;
+	int index;
+	int inserted = 0;
+
+	pESWPortInfo = esw_portinfofifo_read(fep);
+	/* Anything to learn */
+	if (pESWPortInfo != 0) {
+		/* get block index from lookup table */
+		index = GET_BLOCK_PTR(pESWPortInfo->hash);
+		inserted = esw_update_atable_dynamic1(
+			pESWPortInfo->maclo,
+			pESWPortInfo->machi, index,
+			pESWPortInfo->port, currTime, fep);
+	} else {
+		printk(KERN_ERR "%s:hav invalidate learned data \n", __func__);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+/*
+ * esw_forced_forward
+ * The frame is forwared to the forced destination ports.
+ * It only replace the MAC lookup function,
+ * all other filtering(eg.VLAN verification) act as normal
+ */
+static int esw_forced_forward(struct switch_enet_private *fep,
+	int port1, int port2, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/* Enable Forced forwarding for port num */
+	if ((port1 == 1) && (port2 == 1))
+		tmp |= MCF_ESW_P0FFEN_FD(3);
+	else if (port1 == 1)
+		/* Enable Forced forwarding for port 1 only */
+		tmp |= MCF_ESW_P0FFEN_FD(1);
+	else if (port2 == 1)
+		/* Enable Forced forwarding for port 2 only */
+		tmp |= MCF_ESW_P0FFEN_FD(2);
+	else {
+		printk(KERN_ERR "%s:do not support "
+			"the forced forward mode"
+			"port1 %x port2 %x\n",
+			__func__, port1, port2);
+		return -1;
+	}
+
+	if (enable == 1)
+		tmp |= MCF_ESW_P0FFEN_FEN;
+	else if (enable == 0)
+		tmp &= ~MCF_ESW_P0FFEN_FEN;
+	else {
+		printk(KERN_ERR "%s: the enable %x is error\n",
+			__func__, enable);
+		return -2;
+	}
+
+	fecp->ESW_P0FFEN = tmp;
+	return 0;
+}
+
+static int esw_get_forced_forward(
+	struct switch_enet_private *fep,
+	unsigned long *ulForceForward)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulForceForward = fecp->ESW_P0FFEN;
+#ifdef DEBUG_FORCED_FORWARD
+	printk(KERN_INFO "%s  ESW_P0FFEN %#lx\n",
+		__func__, fecp->ESW_P0FFEN);
+#endif
+	return 0;
+}
+
+static void esw_get_port_enable(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortEnable)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortEnable = fecp->ESW_PER;
+#ifdef DEBUG_PORT_ENABLE
+	printk(KERN_INFO "%s  fecp->ESW_PER %#lx\n",
+		__func__, fecp->ESW_PER);
+#endif
+}
+/*
+ * enable or disable port n tx or rx
+ * tx_en 0 disable port n tx
+ * tx_en 1 enable  port n tx
+ * rx_en 0 disbale port n rx
+ * rx_en 1 enable  port n rx
+ */
+static int esw_port_enable_config(struct switch_enet_private *fep,
+	int port, int tx_en, int rx_en)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	tmp = fecp->ESW_PER;
+	if (tx_en == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_PER_TE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_PER_TE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_PER_TE2;
+		else {
+			printk(KERN_ERR "%s:do not support the"
+				" port %x tx enable %d\n",
+				__func__, port, tx_en);
+			return -1;
+		}
+	} else if (tx_en == 0) {
+		if (port == 0)
+			tmp &= (~MCF_ESW_PER_TE0);
+		else if (port == 1)
+			tmp &= (~MCF_ESW_PER_TE1);
+		else if (port == 2)
+			tmp &= (~MCF_ESW_PER_TE2);
+		else {
+			printk(KERN_ERR "%s:do not support "
+				"the port %x tx disable %d\n",
+				__func__, port, tx_en);
+			return -2;
+		}
+	} else {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" tx op value %x\n",
+			__func__, port, tx_en);
+		return -3;
+	}
+
+	if (rx_en == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_PER_RE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_PER_RE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_PER_RE2;
+		else {
+			printk(KERN_ERR "%s:do not support the "
+				"port %x rx enable %d\n",
+				__func__, port, tx_en);
+			return -4;
+		}
+	} else if (rx_en == 0) {
+		if (port == 0)
+			tmp &= (~MCF_ESW_PER_RE0);
+		else if (port == 1)
+			tmp &= (~MCF_ESW_PER_RE1);
+		else if (port == 2)
+			tmp &= (~MCF_ESW_PER_RE2);
+		else {
+			printk(KERN_ERR "%s:do not support the "
+				"port %x rx disable %d\n",
+				__func__, port, rx_en);
+			return -5;
+		}
+	} else {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" rx op value %x\n",
+			__func__, port, tx_en);
+		return -6;
+	}
+
+	fecp->ESW_PER = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_broadcast(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortBroadcast)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortBroadcast = fecp->ESW_DBCR;
+#ifdef DEBUG_PORT_BROADCAST
+	printk(KERN_INFO "%s  fecp->ESW_DBCR %#lx\n",
+		__func__, fecp->ESW_DBCR);
+#endif
+}
+
+static int esw_port_broadcast_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_DBCR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_DBCR_P0;
+		else if (port == 1)
+			tmp |= MCF_ESW_DBCR_P1;
+		else if (port == 2)
+			tmp |= MCF_ESW_DBCR_P2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_DBCR_P0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_DBCR_P1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_DBCR_P2;
+	}
+
+	fecp->ESW_DBCR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_multicast(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortMulticast)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortMulticast = fecp->ESW_DMCR;
+#ifdef DEBUG_PORT_MULTICAST
+	printk(KERN_INFO "%s  fecp->ESW_DMCR %#lx\n",
+		__func__, fecp->ESW_DMCR);
+#endif
+}
+
+static int esw_port_multicast_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_DMCR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_DMCR_P0;
+		else if (port == 1)
+			tmp |= MCF_ESW_DMCR_P1;
+		else if (port == 2)
+			tmp |= MCF_ESW_DMCR_P2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_DMCR_P0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_DMCR_P1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_DMCR_P2;
+	}
+
+	fecp->ESW_DMCR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_blocking(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortBlocking)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortBlocking = (fecp->ESW_BKLR & 0x00ff);
+#ifdef DEBUG_PORT_BLOCKING
+	printk(KERN_INFO "%s  fecp->ESW_BKLR %#lx\n",
+		__func__, fecp->ESW_BKLR);
+#endif
+}
+
+static int esw_port_blocking_config(
+	struct switch_enet_private *fep,
+	int port, int enable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_BKLR;
+	if (enable == 1) {
+		if (port == 0)
+			tmp |= MCF_ESW_BKLR_BE0;
+		else if (port == 1)
+			tmp |= MCF_ESW_BKLR_BE1;
+		else if (port == 2)
+			tmp |= MCF_ESW_BKLR_BE2;
+	} else if (enable == 0) {
+		if (port == 0)
+			tmp &= ~MCF_ESW_BKLR_BE0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_BKLR_BE1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_BKLR_BE2;
+	}
+
+	fecp->ESW_BKLR = tmp;
+	return 0;
+}
+
+
+static void esw_get_port_learning(
+	struct switch_enet_private *fep,
+	unsigned long *ulPortLearning)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulPortLearning = (fecp->ESW_BKLR & 0xff00) >> 16;
+#ifdef DEBUG_PORT_LEARNING
+	printk(KERN_INFO "%s  fecp->ESW_BKLR %#lx\n",
+		__func__, fecp->ESW_BKLR);
+#endif
+}
+
+static int esw_port_learning_config(
+	struct switch_enet_private *fep,
+	int port, int disable)
+{
+	unsigned long tmp = 0;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port > 2) || (port < 0)) {
+		printk(KERN_ERR "%s:do not support the port %x"
+			" default broadcast\n",
+			__func__, port);
+		return -1;
+	}
+
+	tmp = fecp->ESW_BKLR;
+	if (disable == 1) {
+		fep->learning_irqhandle_enable = 0;
+		if (port == 0)
+			tmp |= MCF_ESW_BKLR_LD0;
+		else if (port == 1)
+			tmp |= MCF_ESW_BKLR_LD1;
+		else if (port == 2)
+			tmp |= MCF_ESW_BKLR_LD2;
+	} else if (disable == 0) {
+		fep->learning_irqhandle_enable = 1;
+		fecp->switch_imask |= MCF_ESW_IMR_LRN;
+		if (port == 0)
+			tmp &= ~MCF_ESW_BKLR_LD0;
+		else if (port == 1)
+			tmp &= ~MCF_ESW_BKLR_LD1;
+		else if (port == 2)
+			tmp &= ~MCF_ESW_BKLR_LD2;
+	}
+
+	fecp->ESW_BKLR = tmp;
+#ifdef DEBUG_PORT_LEARNING
+	printk(KERN_INFO "%s  ESW_BKLR %#lx, switch_imask %#lx\n",
+		__func__, fecp->ESW_BKLR, fecp->switch_imask);
+#endif
+	return 0;
+}
+
+/*
+ * Checks IP Snoop options of handling the snooped frame.
+ * mode 0 : The snooped frame is forward only to management port
+ * mode 1 : The snooped frame is copy to management port and
+ *              normal forwarding is checked.
+ * mode 2 : The snooped frame is discarded.
+ * mode 3 : Disable the ip snoop function
+ * ip_header_protocol : the IP header protocol field
+ */
+static int esw_ip_snoop_config(struct switch_enet_private *fep,
+	int num, int mode, unsigned long ip_header_protocol)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0, protocol_type = 0;
+
+	fecp = fep->hwp;
+	/* Config IP Snooping */
+	if (mode == 0) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp |= MCF_ESW_IPSNP_MODE(0);/*For Forward*/
+	} else if (mode == 1) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		/*For Forward and copy_to_mangmnt_port*/
+		tmp |= MCF_ESW_IPSNP_MODE(1);
+	} else if (mode == 2) {
+		/* Enable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp |= MCF_ESW_IPSNP_MODE(2);/*discard*/
+	} else if (mode == 3) {
+		/* disable IP Snooping */
+		tmp = MCF_ESW_IPSNP_EN;
+		tmp &= ~MCF_ESW_IPSNP_EN;
+	} else {
+		printk(KERN_ERR "%s: the mode %x "
+			"we do not support\n", __func__, mode);
+		return -1;
+	}
+
+	protocol_type = ip_header_protocol;
+	fecp->ESW_IPSNP[num] =
+		tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type);
+	printk(KERN_INFO "%s : ESW_IPSNP[%d] %#lx\n",
+		__func__, num, fecp->ESW_IPSNP[num]);
+	return 0;
+}
+
+static void esw_get_ip_snoop_config(
+	struct switch_enet_private *fep,
+	unsigned long *ulpESW_IPSNP)
+{
+	int i;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 8; i++)
+		*(ulpESW_IPSNP + i) = fecp->ESW_IPSNP[i];
+#ifdef DEBUG_IP_SNOOP
+	printk(KERN_INFO "%s  ", __func__);
+	for (i = 0; i < 8; i++)
+		printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_IPSNP[i]);
+	printk(KERN_INFO "\n");
+#endif
+
+}
+/*
+ * Checks TCP/UDP Port Snoop options of handling the snooped frame.
+ * mode 0 : The snooped frame is forward only to management port
+ * mode 1 : The snooped frame is copy to management port and
+ *              normal forwarding is checked.
+ * mode 2 : The snooped frame is discarded.
+ * compare_port : port number in the TCP/UDP header
+ * compare_num 1: TCP/UDP source port number is compared
+ * compare_num 2: TCP/UDP destination port number is compared
+ * compare_num 3: TCP/UDP source and destination port number is compared
+ */
+static int esw_tcpudp_port_snoop_config(struct switch_enet_private *fep,
+	int num, int mode, int compare_port, int compare_num)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0;
+
+	fecp = fep->hwp;
+
+	/* Enable TCP/UDP port Snooping */
+	tmp = MCF_ESW_PSNP_EN;
+	if (mode == 0)
+		tmp |= MCF_ESW_PSNP_MODE(0);/* For Forward */
+	else if (mode == 1)/*For Forward and copy_to_mangmnt_port*/
+		tmp |= MCF_ESW_PSNP_MODE(1);
+	else if (mode == 2)
+		tmp |= MCF_ESW_PSNP_MODE(2);/* discard */
+	else if (mode == 3) /* disable the port function */
+		tmp &= (~MCF_ESW_PSNP_EN);
+	else {
+		printk(KERN_ERR "%s: the mode %x we do not support\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if (compare_num == 1)
+		tmp |= MCF_ESW_PSNP_CS;
+	else if (compare_num == 2)
+		tmp |= MCF_ESW_PSNP_CD;
+	else if (compare_num == 3)
+		tmp |= MCF_ESW_PSNP_CD | MCF_ESW_PSNP_CS;
+	else {
+		printk(KERN_ERR "%s: the compare port address %x"
+			" we do not support\n",
+			__func__, compare_num);
+		return -1;
+	}
+
+	fecp->ESW_PSNP[num] = tmp |
+		MCF_ESW_PSNP_PORT_COMPARE(compare_port);
+	printk(KERN_INFO "ESW_PSNP[%d] %#lx\n",
+			num, fecp->ESW_PSNP[num]);
+	return 0;
+}
+
+static void esw_get_tcpudp_port_snoop_config(
+	struct switch_enet_private *fep,
+	unsigned long *ulpESW_PSNP)
+{
+	int i;
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 8; i++)
+		*(ulpESW_PSNP + i) = fecp->ESW_PSNP[i];
+#ifdef DEBUG_TCPUDP_PORT_SNOOP
+	 printk(KERN_INFO "%s  ", __func__);
+	 for (i = 0; i < 8; i++)
+		printk(KERN_INFO " reg(%d) %#lx", fecp->ESW_PSNP[i]);
+	 printk(KERN_INFO "\n");
+#endif
+
+}
+
+static void esw_get_port_mirroring(
+	struct switch_enet_private *fep,
+	struct eswIoctlPortMirrorStatus *pPortMirrorStatus)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	pPortMirrorStatus->ESW_MCR    = fecp->ESW_MCR;
+	pPortMirrorStatus->ESW_EGMAP  = fecp->ESW_EGMAP;
+	pPortMirrorStatus->ESW_INGMAP = fecp->ESW_INGMAP;
+	pPortMirrorStatus->ESW_INGSAL = fecp->ESW_INGSAL;
+	pPortMirrorStatus->ESW_INGSAH = fecp->ESW_INGSAH;
+	pPortMirrorStatus->ESW_INGDAL = fecp->ESW_INGDAL;
+	pPortMirrorStatus->ESW_INGDAH = fecp->ESW_INGDAH;
+	pPortMirrorStatus->ESW_ENGSAL = fecp->ESW_ENGSAL;
+	pPortMirrorStatus->ESW_ENGSAH = fecp->ESW_ENGSAH;
+	pPortMirrorStatus->ESW_ENGDAL = fecp->ESW_ENGDAL;
+	pPortMirrorStatus->ESW_ENGDAH = fecp->ESW_ENGDAH;
+	pPortMirrorStatus->ESW_MCVAL  = fecp->ESW_MCVAL;
+#ifdef DEBUG_PORT_MIRROR
+	printk(KERN_INFO "%s : ESW_MCR %#lx, ESW_EGMAP %#lx\n"
+		"ESW_INGMAP %#lx, ESW_INGSAL %#lx, "
+		"ESW_INGSAH %#lx ESW_INGDAL %#lx, ESW_INGDAH %#lx\n"
+		"ESW_ENGSAL %#lx, ESW_ENGSAH%#lx, ESW_ENGDAL %#lx,"
+		"ESW_ENGDAH %#lx, ESW_MCVAL %#lx\n",
+		__func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP,
+		fecp->ESW_INGSAL, fecp->ESW_INGSAH, fecp->ESW_INGDAL,
+		fecp->ESW_INGDAH, fecp->ESW_ENGSAL, fecp->ESW_ENGSAH,
+		fecp->ESW_ENGDAL, fecp->ESW_ENGDAH, fecp->ESW_MCVAL);
+#endif
+}
+
+static int esw_port_mirroring_config(struct switch_enet_private *fep,
+	int mirror_port, int port, int mirror_enable,
+	unsigned char *src_mac, unsigned char *des_mac,
+	int egress_en, int ingress_en,
+	int egress_mac_src_en, int egress_mac_des_en,
+	int ingress_mac_src_en, int ingress_mac_des_en)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0;
+
+	fecp = fep->hwp;
+
+	/*mirroring config*/
+	tmp = 0;
+	if (egress_en == 1) {
+		tmp |= MCF_ESW_MCR_EGMAP;
+		if (port == 0)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0;
+		else if (port == 1)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1;
+		else if (port == 2)
+			fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2;
+		else {
+			printk(KERN_ERR "%s: the port %x we do not support\n",
+					__func__, port);
+			return -1;
+		}
+	} else if (egress_en == 0) {
+		tmp &= (~MCF_ESW_MCR_EGMAP);
+	} else {
+		printk(KERN_ERR "%s: egress_en %x we do not support\n",
+			__func__, egress_en);
+		return -1;
+	}
+
+	if (ingress_en == 1) {
+		tmp |= MCF_ESW_MCR_INGMAP;
+		if (port == 0)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0;
+		else if (port == 1)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1;
+		else if (port == 2)
+			fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2;
+		else {
+			printk(KERN_ERR "%s: the port %x we do not support\n",
+				__func__, port);
+			return -1;
+		}
+	} else if (ingress_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGMAP;
+	} else{
+		printk(KERN_ERR "%s: ingress_en %x we do not support\n",
+				__func__, ingress_en);
+		return -1;
+	}
+
+	if (egress_mac_src_en == 1) {
+		tmp |= MCF_ESW_MCR_EGSA;
+		fecp->ESW_ENGSAH = (src_mac[5] << 8) | (src_mac[4]);
+		fecp->ESW_ENGSAL = (unsigned long)((src_mac[3] << 24) |
+					(src_mac[2] << 16) |
+					(src_mac[1] << 8) |
+					src_mac[0]);
+	} else if (egress_mac_src_en == 0) {
+		tmp &= ~MCF_ESW_MCR_EGSA;
+	} else {
+		printk(KERN_ERR "%s: egress_mac_src_en  %x we do not support\n",
+			__func__, egress_mac_src_en);
+		return -1;
+	}
+
+	if (egress_mac_des_en == 1) {
+		tmp |= MCF_ESW_MCR_EGDA;
+		fecp->ESW_ENGDAH = (des_mac[5] << 8) | (des_mac[4]);
+		fecp->ESW_ENGDAL = (unsigned long)((des_mac[3] << 24) |
+					(des_mac[2] << 16) |
+					(des_mac[1] << 8) |
+					des_mac[0]);
+	} else if (egress_mac_des_en == 0) {
+		tmp &= ~MCF_ESW_MCR_EGDA;
+	} else {
+		printk(KERN_ERR "%s: egress_mac_des_en  %x we do not support\n",
+			__func__, egress_mac_des_en);
+		return -1;
+	}
+
+	if (ingress_mac_src_en == 1) {
+		tmp |= MCF_ESW_MCR_INGSA;
+		fecp->ESW_INGSAH = (src_mac[5] << 8) | (src_mac[4]);
+		fecp->ESW_INGSAL = (unsigned long)((src_mac[3] << 24) |
+					(src_mac[2] << 16) |
+					(src_mac[1] << 8) |
+					src_mac[0]);
+	} else if (ingress_mac_src_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGSA;
+	} else {
+		printk(KERN_ERR "%s: ingress_mac_src_en  %x we do not support\n",
+			__func__, ingress_mac_src_en);
+		return -1;
+	}
+
+	if (ingress_mac_des_en == 1) {
+		tmp |= MCF_ESW_MCR_INGDA;
+		fecp->ESW_INGDAH = (des_mac[5] << 8) | (des_mac[4]);
+		fecp->ESW_INGDAL = (unsigned long)((des_mac[3] << 24) |
+					(des_mac[2] << 16) |
+					(des_mac[1] << 8) |
+					des_mac[0]);
+	} else if (ingress_mac_des_en == 0) {
+		tmp &= ~MCF_ESW_MCR_INGDA;
+	} else {
+		printk(KERN_ERR "%s: ingress_mac_des_en  %x we do not support\n",
+			__func__, ingress_mac_des_en);
+		return -1;
+	}
+
+	/*------------------------------------------------------------------*/
+	if (mirror_enable == 1)
+		tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port);
+	else if (mirror_enable == 0)
+		tmp &= ~MCF_ESW_MCR_MEN;
+	else
+		printk(KERN_ERR "%s: the mirror enable %x is error\n",
+			__func__, mirror_enable);
+
+
+	fecp->ESW_MCR = tmp;
+	printk(KERN_INFO "%s : MCR %#lx, EGMAP %#lx, INGMAP %#lx;\n"
+		"ENGSAH %#lx, ENGSAL %#lx ;ENGDAH %#lx, ENGDAL %#lx;\n"
+		"INGSAH %#lx, INGSAL %#lx\n;INGDAH %#lx, INGDAL %#lx;\n",
+		__func__, fecp->ESW_MCR, fecp->ESW_EGMAP, fecp->ESW_INGMAP,
+		fecp->ESW_ENGSAH, fecp->ESW_ENGSAL,
+		fecp->ESW_ENGDAH, fecp->ESW_ENGDAL,
+		fecp->ESW_INGSAH, fecp->ESW_INGSAL,
+		fecp->ESW_INGDAH, fecp->ESW_INGDAL);
+	return 0;
+}
+
+static void esw_get_vlan_verification(
+	struct switch_enet_private *fep,
+	unsigned long *ulValue)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+	*ulValue = fecp->ESW_VLANV;
+
+#ifdef DEBUG_VLAN_VERIFICATION_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx\n",
+		__func__, fecp->ESW_VLANV);
+#endif
+}
+
+static int esw_set_vlan_verification(
+	struct switch_enet_private *fep, int port,
+	int vlan_domain_verify_en,
+	int vlan_discard_unknown_en)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	if ((port < 0) || (port > 2)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (vlan_domain_verify_en == 1) {
+		if (port == 0)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV0;
+		else if (port == 1)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV1;
+		else if (port == 2)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_VV2;
+	} else if (vlan_domain_verify_en == 0) {
+		if (port == 0)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV0;
+		else if (port == 1)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV1;
+		else if (port == 2)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV2;
+	} else {
+		printk(KERN_INFO "%s: donot support "
+			"vlan_domain_verify %x\n",
+			__func__, vlan_domain_verify_en);
+		return -2;
+	}
+
+	if (vlan_discard_unknown_en == 1) {
+		if (port == 0)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU0;
+		else if (port == 1)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU1;
+		else if (port == 2)
+			fecp->ESW_VLANV |= MCF_ESW_VLANV_DU2;
+	} else if (vlan_discard_unknown_en == 0) {
+		if (port == 0)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU0;
+		else if (port == 1)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU1;
+		else if (port == 2)
+			fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU2;
+	} else {
+		printk(KERN_INFO "%s: donot support "
+			"vlan_discard_unknown %x\n",
+			__func__, vlan_discard_unknown_en);
+		return -3;
+	}
+
+#ifdef DEBUG_VLAN_VERIFICATION_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx\n",
+		__func__, fecp->ESW_VLANV);
+#endif
+	return 0;
+}
+
+static void esw_get_vlan_resolution_table(
+	struct switch_enet_private *fep,
+	int vlan_domain_num,
+	unsigned long *ulValue)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	*ulValue = fecp->ESW_VRES[vlan_domain_num];
+
+#ifdef DEBUG_VLAN_DOMAIN_TABLE
+	printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n",
+		__func__, vlan_domain_num,
+		fecp->ESW_VRES[vlan_domain_num]);
+#endif
+}
+
+int esw_set_vlan_resolution_table(
+	struct switch_enet_private *fep,
+	unsigned short port_vlanid,
+	int vlan_domain_num,
+	int vlan_domain_port)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	if ((vlan_domain_num < 0)
+		|| (vlan_domain_num > 31)) {
+		printk(KERN_ERR "%s: do not support the "
+			"vlan_domain_num %d\n",
+		__func__, vlan_domain_num);
+		return -1;
+	}
+
+	if ((vlan_domain_port < 0)
+		|| (vlan_domain_port > 7)) {
+		printk(KERN_ERR "%s: do not support the "
+			"vlan_domain_port %d\n",
+			__func__, vlan_domain_port);
+		return -2;
+	}
+
+	fecp->ESW_VRES[vlan_domain_num] =
+		MCF_ESW_VRES_VLANID(port_vlanid)
+		| vlan_domain_port;
+
+#ifdef DEBUG_VLAN_DOMAIN_TABLE
+	printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n",
+		__func__, vlan_domain_num,
+		fecp->ESW_VRES[vlan_domain_num]);
+#endif
+	return 0;
+}
+
+static void esw_get_vlan_input_config(
+	struct switch_enet_private *fep,
+	struct eswIoctlVlanInputStatus *pVlanInputConfig)
+{
+	struct switch_t  *fecp;
+	int i;
+
+	fecp = fep->hwp;
+	for (i = 0; i < 3; i++)
+		pVlanInputConfig->ESW_PID[i] = fecp->ESW_PID[i];
+
+	pVlanInputConfig->ESW_VLANV  = fecp->ESW_VLANV;
+	pVlanInputConfig->ESW_VIMSEL = fecp->ESW_VIMSEL;
+	pVlanInputConfig->ESW_VIMEN  = fecp->ESW_VIMEN;
+
+	for (i = 0; i < 32; i++)
+		pVlanInputConfig->ESW_VRES[i] = fecp->ESW_VRES[i];
+#ifdef DEBUG_VLAN_INTPUT_CONFIG
+	printk(KERN_INFO "%s: ESW_VLANV %#lx, ESW_VIMSEL %#lx, "
+		"ESW_VIMEN %#lx, ESW_PID[0], ESW_PID[1] %#lx, "
+		"ESW_PID[2] %#lx", __func__,
+		fecp->ESW_VLANV, fecp->ESW_VIMSEL, fecp->ESW_VIMEN,
+		fecp->ESW_PID[0], fecp->ESW_PID[1], fecp->ESW_PID[2]);
+#endif
+}
+
+
+static int esw_vlan_input_process(struct switch_enet_private *fep,
+	int port, int mode, unsigned short port_vlanid,
+	int vlan_verify_en, int vlan_domain_num,
+	int vlan_domain_port)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/*we only support mode1 mode2 mode3 mode4*/
+	if ((mode < 0) || (mode > 3)) {
+		printk(KERN_ERR "%s: do not support the"
+			" VLAN input processing mode %d\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -2;
+	}
+
+	if ((vlan_verify_en == 1) && ((vlan_domain_num < 0)
+		|| (vlan_domain_num > 32))) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -3;
+	}
+
+	fecp->ESW_PID[port] = MCF_ESW_PID_VLANID(port_vlanid);
+	if (port == 0) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P0;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN0;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM0(mode);
+	} else if (port == 1) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P1;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN1;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM1(mode);
+	} else if (port == 2) {
+		if (vlan_verify_en == 1)
+			fecp->ESW_VRES[vlan_domain_num] =
+				MCF_ESW_VRES_VLANID(port_vlanid)
+				| MCF_ESW_VRES_P2;
+
+		fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN2;
+		fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM2(mode);
+	} else {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -2;
+	}
+
+	return 0;
+}
+
+static void esw_get_vlan_output_config(struct switch_enet_private *fep,
+	unsigned long *ulVlanOutputConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	*ulVlanOutputConfig = fecp->ESW_VOMSEL;
+#ifdef DEBUG_VLAN_OUTPUT_CONFIG
+	printk(KERN_INFO "%s: ESW_VOMSEL %#lx", __func__,
+			fecp->ESW_VOMSEL);
+#endif
+}
+
+static int esw_vlan_output_process(struct switch_enet_private *fep,
+	int port, int mode)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 2)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, mode);
+		return -1;
+	}
+
+	if (port == 0) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM0(mode);
+	} else if (port == 1) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM1(mode);
+	} else if (port == 2) {
+		fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM2(mode);
+	} else {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+	return 0;
+}
+
+/* frame calssify and priority resolution */
+/* vlan priority lookup */
+static int esw_framecalssify_vlan_priority_lookup(
+	struct switch_enet_private *fep,
+	int port, int func_enable,
+	int vlan_pri_table_num,
+	int vlan_pri_table_value)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (func_enable == 0) {
+		fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_VLAN;
+		printk(KERN_ERR "%s: disable port %d VLAN priority "
+			"lookup function\n", __func__, port);
+		return 0;
+	}
+
+	if ((vlan_pri_table_num < 0) || (vlan_pri_table_num > 7)) {
+		printk(KERN_ERR "%s: do not support the priority %d\n",
+			__func__, vlan_pri_table_num);
+		return -1;
+	}
+
+	fecp->ESW_PVRES[port] |= ((vlan_pri_table_value & 0x3)
+		<< (vlan_pri_table_num*3));
+	/* enable port  VLAN priority lookup function */
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_VLAN;
+
+	return 0;
+}
+
+static int esw_framecalssify_ip_priority_lookup(
+	struct switch_enet_private *fep,
+	int port, int func_enable, int ipv4_en,
+	int ip_priority_num,
+	int ip_priority_value)
+{
+	struct switch_t  *fecp;
+	unsigned long tmp = 0, tmp_prio = 0;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	if (func_enable == 0) {
+		fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_IP;
+		printk(KERN_ERR "%s: disable port %d ip priority "
+			"lookup function\n", __func__, port);
+		return 0;
+	}
+
+	/* IPV4 priority 64 entry table lookup */
+	/* IPv4 head 6 bit TOS field */
+	if (ipv4_en == 1) {
+		if ((ip_priority_num < 0) || (ip_priority_num > 63)) {
+			printk(KERN_ERR "%s: do not support the table entry %d\n",
+				__func__, ip_priority_num);
+			return -2;
+		}
+	} else { /* IPV6 priority 256 entry table lookup */
+		/* IPv6 head 8 bit COS field */
+		if ((ip_priority_num < 0) || (ip_priority_num > 255)) {
+			printk(KERN_ERR "%s: do not support the table entry %d\n",
+				__func__, ip_priority_num);
+			return -3;
+		}
+	}
+
+	/* IP priority  table lookup : address */
+	tmp = MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	/* IP priority  table lookup : ipv4sel */
+	if (ipv4_en == 1)
+		tmp = tmp | MCF_ESW_IPRES_IPV4SEL;
+	/* IP priority  table lookup : priority */
+	if (port == 0)
+		tmp |= MCF_ESW_IPRES_PRI0(ip_priority_value);
+	else if (port == 1)
+		tmp |= MCF_ESW_IPRES_PRI1(ip_priority_value);
+	else if (port == 2)
+		tmp |= MCF_ESW_IPRES_PRI2(ip_priority_value);
+
+	/* configure */
+	fecp->ESW_IPRES = MCF_ESW_IPRES_READ |
+		MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	tmp_prio = fecp->ESW_IPRES;
+
+	fecp->ESW_IPRES = tmp | tmp_prio;
+
+	fecp->ESW_IPRES = MCF_ESW_IPRES_READ |
+		MCF_ESW_IPRES_ADDRESS(ip_priority_num);
+	tmp_prio = fecp->ESW_IPRES;
+
+	/* enable port  IP priority lookup function */
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_IP;
+
+	return 0;
+}
+
+static int esw_framecalssify_mac_priority_lookup(
+	struct switch_enet_private *fep,
+	int port)
+{
+	struct switch_t  *fecp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	fecp = fep->hwp;
+	fecp->ESW_PRES[port] |= MCF_ESW_PRES_MAC;
+
+	return 0;
+}
+
+static int esw_frame_calssify_priority_init(
+	struct switch_enet_private *fep,
+	int port, unsigned char priority_value)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+	/* disable all priority lookup function */
+	fecp->ESW_PRES[port] = 0;
+	fecp->ESW_PRES[port] = MCF_ESW_PRES_DFLT_PRI(priority_value & 0x7);
+
+	return 0;
+}
+
+static int esw_get_statistics_status(
+	struct switch_enet_private *fep,
+	struct esw_statistics_status *pStatistics)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	pStatistics->ESW_DISCN   = fecp->ESW_DISCN;
+	pStatistics->ESW_DISCB   = fecp->ESW_DISCB;
+	pStatistics->ESW_NDISCN  = fecp->ESW_NDISCN;
+	pStatistics->ESW_NDISCB  = fecp->ESW_NDISCB;
+#ifdef DEBUG_STATISTICS
+	printk(KERN_ERR "%s:ESW_DISCN %#lx, ESW_DISCB %#lx,"
+		"ESW_NDISCN %#lx, ESW_NDISCB %#lx\n",
+		__func__, fecp->ESW_DISCN, fecp->ESW_DISCB,
+		fecp->ESW_NDISCN, fecp->ESW_NDISCB);
+#endif
+	return 0;
+}
+
+static int esw_get_port_statistics_status(
+	struct switch_enet_private *fep,
+	int port,
+	struct esw_port_statistics_status *pPortStatistics)
+{
+	struct switch_t  *fecp;
+
+	if ((port < 0) || (port > 3)) {
+		printk(KERN_ERR "%s: do not support the port %d\n",
+			__func__, port);
+		return -1;
+	}
+
+	fecp = fep->hwp;
+
+	pPortStatistics->MCF_ESW_POQC   =
+		fecp->port_statistics_status[port].MCF_ESW_POQC;
+	pPortStatistics->MCF_ESW_PMVID  =
+		fecp->port_statistics_status[port].MCF_ESW_PMVID;
+	pPortStatistics->MCF_ESW_PMVTAG =
+		fecp->port_statistics_status[port].MCF_ESW_PMVTAG;
+	pPortStatistics->MCF_ESW_PBL    =
+		fecp->port_statistics_status[port].MCF_ESW_PBL;
+#ifdef DEBUG_PORT_STATISTICS
+	printk(KERN_ERR "%s : port[%d].MCF_ESW_POQC %#lx, MCF_ESW_PMVID %#lx,"
+		" MCF_ESW_PMVTAG %#lx, MCF_ESW_PBL %#lx\n",
+		__func__, port,
+		fecp->port_statistics_status[port].MCF_ESW_POQC,
+		fecp->port_statistics_status[port].MCF_ESW_PMVID,
+		fecp->port_statistics_status[port].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[port].MCF_ESW_PBL);
+#endif
+	return 0;
+}
+
+static int esw_get_output_queue_status(
+	struct switch_enet_private *fep,
+	struct esw_output_queue_status *pOutputQueue)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	pOutputQueue->ESW_MMSR  = fecp->ESW_MMSR;
+	pOutputQueue->ESW_LMT   = fecp->ESW_LMT;
+	pOutputQueue->ESW_LFC   = fecp->ESW_LFC;
+	pOutputQueue->ESW_IOSR  = fecp->ESW_IOSR;
+	pOutputQueue->ESW_PCSR  = fecp->ESW_PCSR;
+	pOutputQueue->ESW_QWT   = fecp->ESW_QWT;
+	pOutputQueue->ESW_P0BCT = fecp->ESW_P0BCT;
+#ifdef DEBUG_OUTPUT_QUEUE
+	printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, "
+		"ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n",
+		__func__, fecp->ESW_MMSR,
+		fecp->ESW_LMT, fecp->ESW_LFC,
+		fecp->ESW_IOSR,  fecp->ESW_PCSR,
+		fecp->ESW_QWT, fecp->ESW_P0BCT);
+#endif
+	return 0;
+}
+
+/* set output queue memory status and configure*/
+static int esw_set_output_queue_memory(
+	struct switch_enet_private *fep,
+	int fun_num,
+	struct esw_output_queue_status *pOutputQueue)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	if (fun_num == 1) {
+		/* memory manager status*/
+		fecp->ESW_MMSR = pOutputQueue->ESW_MMSR;
+	} else if (fun_num == 2) {
+		/*low memory threshold*/
+		fecp->ESW_LMT = pOutputQueue->ESW_LMT;
+	} else if (fun_num == 3) {
+		/*lowest number of free cells*/
+		fecp->ESW_LFC = pOutputQueue->ESW_LFC;
+	} else if (fun_num == 4) {
+		/*queue weights*/
+		fecp->ESW_QWT = pOutputQueue->ESW_QWT;
+	} else if (fun_num == 5) {
+		/*port 0 backpressure congenstion thresled*/
+		fecp->ESW_P0BCT = pOutputQueue->ESW_P0BCT;
+	} else {
+		printk(KERN_INFO "%s: do not support the cmd %x\n",
+			__func__, fun_num);
+		return -1;
+	}
+#ifdef DEBUG_OUTPUT_QUEUE
+	printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, "
+		"ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n",
+		__func__, fecp->ESW_MMSR,
+		fecp->ESW_LMT, fecp->ESW_LFC,
+		fecp->ESW_IOSR,  fecp->ESW_PCSR,
+		fecp->ESW_QWT, fecp->ESW_P0BCT);
+#endif
+	return 0;
+}
+
+int esw_set_irq_mask(
+	struct switch_enet_private *fep,
+	unsigned long mask, int enable)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+#ifdef DEBUG_IRQ
+	printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx "
+		" mask %x, enable %x\n",
+		__func__, fecp->switch_ievent,
+		fecp->switch_imask, mask, enable);
+#endif
+	if (enable == 1)
+		fecp->switch_imask |= mask;
+	else if (enable == 1)
+		fecp->switch_imask &= (~mask);
+	else {
+		printk(KERN_INFO "%s: enable %x is error value\n",
+			__func__, enable);
+		return -1;
+	}
+#ifdef DEBUG_IRQ
+	printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx, "
+		"rx_des_start %#lx, tx_des_start %#lx, "
+		"rx_buff_size %#lx, rx_des_active %#lx, "
+		"tx_des_active %#lx\n",
+		__func__, fecp->switch_ievent, fecp->switch_imask,
+		fecp->fec_r_des_start, fecp->fec_x_des_start,
+		fecp->fec_r_buff_size, fecp->fec_r_des_active,
+		fecp->fec_x_des_active);
+#endif
+	return 0;
+}
+
+static void esw_get_switch_mode(
+	struct switch_enet_private *fep,
+	unsigned long *ulModeConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulModeConfig = fecp->ESW_MODE;
+#ifdef DEBUG_SWITCH_MODE
+	printk(KERN_INFO "%s: mode %#lx \n",
+		__func__, fecp->ESW_MODE);
+#endif
+}
+
+static void esw_switch_mode_configure(
+	struct switch_enet_private *fep,
+	unsigned long configure)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_MODE |= configure;
+#ifdef DEBUG_SWITCH_MODE
+	printk(KERN_INFO "%s: mode %#lx \n",
+		__func__, fecp->ESW_MODE);
+#endif
+}
+
+
+static void esw_get_bridge_port(
+	struct switch_enet_private *fep,
+	unsigned long *ulBMPConfig)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	*ulBMPConfig = fecp->ESW_BMPC;
+#ifdef DEBUG_BRIDGE_PORT
+	printk(KERN_INFO "%s: bridge management port %#lx \n",
+		__func__, fecp->ESW_BMPC);
+#endif
+}
+
+static void  esw_bridge_port_configure(
+	struct switch_enet_private *fep,
+	unsigned long configure)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_BMPC |= configure;
+#ifdef DEBUG_BRIDGE_PORT
+	printk(KERN_INFO "%s: bridge management port %#lx \n",
+		__func__, fecp->ESW_BMPC);
+#endif
+}
+
+/* The timer should create an interrupt every 4 seconds*/
+static void l2switch_aging_timer(unsigned long data)
+{
+	struct switch_enet_private *fep;
+
+	fep = (struct switch_enet_private *)data;
+
+	if (fep) {
+		TIMEINCREMENT(fep->currTime);
+		fep->timeChanged++;
+	}
+
+	mod_timer(&fep->timer_aging, jiffies + LEARNING_AGING_TIMER);
+}
+
+void esw_check_rxb_txb_interrupt(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+
+	/*Enable Forced forwarding for port 1*/
+	fecp->ESW_P0FFEN = MCF_ESW_P0FFEN_FEN |
+		MCF_ESW_P0FFEN_FD(1);
+	/*Disable learning for all ports*/
+
+	fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF;
+	printk(KERN_ERR "%s: fecp->ESW_DBCR %#lx, fecp->ESW_P0FFEN %#lx"
+		" fecp->ESW_BKLR %#lx\n", __func__, fecp->ESW_DBCR,
+		fecp->ESW_P0FFEN, fecp->ESW_BKLR);
+}
+
+static int esw_mac_addr_static(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+
+	fecp = fep->hwp;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1;
+
+	if (is_valid_ether_addr(fep->netdev->dev_addr))
+		esw_update_atable_static(fep->netdev->dev_addr, 7, 7, fep);
+	else{
+		printk(KERN_ERR "Can not add available mac address"
+				" for switch!!\n");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static void esw_main(struct switch_enet_private *fep)
+{
+	struct switch_t  *fecp;
+	fecp = fep->hwp;
+
+	esw_mac_addr_static(fep);
+	fecp->ESW_BKLR = 0;
+	fecp->switch_imask = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF;
+	fecp->ESW_PER = 0x70007;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2;
+}
+
+static int switch_enet_ioctl(
+	struct net_device *dev,
+	struct ifreq *ifr, int cmd)
+{
+	struct switch_enet_private *fep;
+	struct switch_t       *fecp;
+	int ret = 0;
+
+	printk(KERN_INFO "%s cmd %x\n", __func__, cmd);
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)dev->base_addr;
+
+	switch (cmd) {
+	case ESW_SET_PORTENABLE_CONF:
+	{
+		struct eswIoctlPortEnableConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPortEnableConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_enable_config(fep,
+			configData.port,
+			configData.tx_enable,
+			configData.rx_enable);
+	}
+		break;
+	case ESW_SET_BROADCAST_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_broadcast_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_MULTICAST_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_multicast_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_BLOCKING_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_port_blocking_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_LEARNING_CONF:
+	{
+		struct eswIoctlPortConfig configData;
+		printk(KERN_INFO "ESW_SET_LEARNING_CONF\n");
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_LEARNING_CONF: %x %x\n",
+				configData.port, configData.enable);
+		ret = esw_port_learning_config(fep,
+			configData.port, configData.enable);
+	}
+		break;
+
+	case ESW_SET_IP_SNOOP_CONF:
+	{
+		struct eswIoctlIpsnoopConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlIpsnoopConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_IP_SNOOP_CONF:: %x %x %x\n",
+				configData.num, configData.mode,
+				configData.ip_header_protocol);
+		ret = esw_ip_snoop_config(fep,
+			configData.num, configData.mode,
+			configData.ip_header_protocol);
+	}
+		break;
+
+	case ESW_SET_PORT_SNOOP_CONF:
+	{
+		struct eswIoctlPortsnoopConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortsnoopConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_PORT_SNOOP_CONF:: %x %x %x %x\n",
+			configData.num, configData.mode,
+			configData.compare_port, configData.compare_num);
+		ret = esw_tcpudp_port_snoop_config(fep,
+			configData.num, configData.mode,
+			configData.compare_port,
+			configData.compare_num);
+	}
+		break;
+
+	case ESW_SET_PORT_MIRROR_CONF:
+	{
+		struct eswIoctlPortMirrorConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPortMirrorConfig));
+		if (ret)
+			return -EFAULT;
+		printk(KERN_INFO "ESW_SET_PORT_MIRROR_CONF:: %x %x %x "
+			"%s %s\n %x %x %x %x %x %x\n",
+			configData.mirror_port, configData.port,
+			configData.mirror_enable,
+			configData.src_mac, configData.des_mac,
+			configData.egress_en, configData.ingress_en,
+			configData.egress_mac_src_en,
+			configData.egress_mac_des_en,
+			configData.ingress_mac_src_en,
+			configData.ingress_mac_des_en);
+		ret = esw_port_mirroring_config(fep,
+			configData.mirror_port, configData.port,
+			configData.mirror_enable,
+			configData.src_mac, configData.des_mac,
+			configData.egress_en, configData.ingress_en,
+			configData.egress_mac_src_en,
+			configData.egress_mac_des_en,
+			configData.ingress_mac_src_en,
+			configData.ingress_mac_des_en);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_VLAN:
+	{
+		struct eswIoctlPriorityVlanConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityVlanConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_vlan_priority_lookup(fep,
+			configData.port, configData.func_enable,
+			configData.vlan_pri_table_num,
+			configData.vlan_pri_table_value);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_IP:
+	{
+		struct eswIoctlPriorityIPConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlPriorityIPConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_ip_priority_lookup(fep,
+			configData.port, configData.func_enable,
+			configData.ipv4_en, configData.ip_priority_num,
+			configData.ip_priority_value);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_MAC:
+	{
+		struct eswIoctlPriorityMacConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityMacConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_framecalssify_mac_priority_lookup(fep,
+			configData.port);
+	}
+		break;
+
+	case ESW_SET_PIRORITY_DEFAULT:
+	{
+		struct eswIoctlPriorityDefaultConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlPriorityDefaultConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_frame_calssify_priority_init(fep,
+			configData.port, configData.priority_value);
+	}
+		break;
+
+	case ESW_SET_P0_FORCED_FORWARD:
+	{
+		struct eswIoctlP0ForcedForwardConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlP0ForcedForwardConfig));
+		if (ret)
+			return -EFAULT;
+
+		ret = esw_forced_forward(fep, configData.port1,
+			configData.port2, configData.enable);
+	}
+		break;
+
+	case ESW_SET_BRIDGE_CONFIG:
+	{
+		unsigned long configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+
+		esw_bridge_port_configure(fep, configData);
+	}
+		break;
+
+	case ESW_SET_SWITCH_MODE:
+	{
+		unsigned long configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+
+		esw_switch_mode_configure(fep, configData);
+	}
+		break;
+
+	case ESW_SET_OUTPUT_QUEUE_MEMORY:
+	{
+		struct eswIoctlOutputQueue configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlOutputQueue));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_OUTPUT_QUEUE_MEMORY:: %#x \n"
+			"%#lx %#lx %#lx %#lx\n"
+			"%#lx %#lx %#lx\n",
+			configData.fun_num,
+			configData.sOutputQueue.ESW_MMSR,
+			configData.sOutputQueue.ESW_LMT,
+			configData.sOutputQueue.ESW_LFC,
+			configData.sOutputQueue.ESW_PCSR,
+			configData.sOutputQueue.ESW_IOSR,
+			configData.sOutputQueue.ESW_QWT,
+			configData.sOutputQueue.ESW_P0BCT);
+		ret = esw_set_output_queue_memory(fep,
+			configData.fun_num, &configData.sOutputQueue);
+	}
+		break;
+
+	case ESW_SET_VLAN_OUTPUT_PROCESS:
+	{
+		struct eswIoctlVlanOutputConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data, sizeof(struct eswIoctlVlanOutputConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_OUTPUT_PROCESS: %x %x\n",
+			configData.port, configData.mode);
+		ret = esw_vlan_output_process(fep,
+			configData.port, configData.mode);
+	}
+		break;
+
+	case ESW_SET_VLAN_INPUT_PROCESS:
+	{
+		struct eswIoctlVlanInputConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanInputConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_INPUT_PROCESS: %x %x"
+				"%x %x %x %x\n",
+			configData.port, configData.mode,
+			configData.port_vlanid,
+			configData.vlan_verify_en,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+		ret = esw_vlan_input_process(fep, configData.port,
+				configData.mode, configData.port_vlanid,
+				configData.vlan_verify_en,
+				configData.vlan_domain_num,
+				configData.vlan_domain_port);
+	}
+		break;
+
+	case ESW_SET_VLAN_DOMAIN_VERIFICATION:
+	{
+		struct eswIoctlVlanVerificationConfig configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanVerificationConfig));
+		if (ret)
+			return -EFAULT;
+
+		printk("ESW_SET_VLAN_DOMAIN_VERIFICATION: "
+			"%x %x %x\n",
+			configData.port,
+			configData.vlan_domain_verify_en,
+			configData.vlan_discard_unknown_en);
+		ret = esw_set_vlan_verification(
+			fep, configData.port,
+			configData.vlan_domain_verify_en,
+			configData.vlan_discard_unknown_en);
+	}
+		break;
+
+	case ESW_SET_VLAN_RESOLUTION_TABLE:
+	{
+		struct eswIoctlVlanResoultionTable configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlVlanResoultionTable));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_SET_VLAN_RESOLUTION_TABLE: "
+			"%x %x %x\n",
+			configData.port_vlanid,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+
+		ret = esw_set_vlan_resolution_table(
+			fep, configData.port_vlanid,
+			configData.vlan_domain_num,
+			configData.vlan_domain_port);
+
+	}
+		break;
+	case ESW_UPDATE_STATIC_MACTABLE:
+	{
+		struct eswIoctlUpdateStaticMACtable configData;
+
+		ret = copy_from_user(&configData,
+			ifr->ifr_data,
+			sizeof(struct eswIoctlUpdateStaticMACtable));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "%s: ESW_UPDATE_STATIC_MACTABLE: mac %s, "
+			"port %x, priority %x\n", __func__,
+			configData.mac_addr,
+			configData.port,
+			configData.priority);
+		ret = esw_update_atable_static(configData.mac_addr,
+				configData.port, configData.priority, fep);
+	}
+		break;
+
+	case ESW_CLEAR_ALL_MACTABLE:
+	{
+		esw_clear_atable(fep);
+	}
+		break;
+
+	case ESW_GET_STATISTICS_STATUS:
+	{
+		struct esw_statistics_status Statistics;
+		ret = esw_get_statistics_status(fep, &Statistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &Statistics,
+			sizeof(struct esw_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT0_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			0, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT1_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			1, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT2_STATISTICS_STATUS:
+	{
+		struct esw_port_statistics_status PortStatistics;
+
+		ret = esw_get_port_statistics_status(fep,
+			2, &PortStatistics);
+		if (ret != 0) {
+			printk(KERN_ERR "%s: cmd %x fail\n",
+				__func__, cmd);
+			return -1;
+		}
+
+		ret = copy_to_user(ifr->ifr_data, &PortStatistics,
+			sizeof(struct esw_port_statistics_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_LEARNING_CONF:
+	{
+		unsigned long PortLearning;
+
+		esw_get_port_learning(fep, &PortLearning);
+		ret = copy_to_user(ifr->ifr_data, &PortLearning,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BLOCKING_CONF:
+	{
+		unsigned long PortBlocking;
+
+		esw_get_port_blocking(fep, &PortBlocking);
+		ret = copy_to_user(ifr->ifr_data, &PortBlocking,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_MULTICAST_CONF:
+	{
+		unsigned long PortMulticast;
+
+		esw_get_port_multicast(fep, &PortMulticast);
+		ret = copy_to_user(ifr->ifr_data, &PortMulticast,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BROADCAST_CONF:
+	{
+		unsigned long PortBroadcast;
+
+		esw_get_port_broadcast(fep, &PortBroadcast);
+		ret = copy_to_user(ifr->ifr_data, &PortBroadcast,
+		sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORTENABLE_CONF:
+	{
+		unsigned long PortEnable;
+
+		esw_get_port_enable(fep, &PortEnable);
+		ret = copy_to_user(ifr->ifr_data, &PortEnable,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_IP_SNOOP_CONF:
+	{
+		unsigned long ESW_IPSNP[8];
+
+		esw_get_ip_snoop_config(fep, (unsigned long *)ESW_IPSNP);
+		ret = copy_to_user(ifr->ifr_data, ESW_IPSNP,
+			(8 * sizeof(unsigned long)));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT_SNOOP_CONF:
+	{
+		unsigned long ESW_PSNP[8];
+
+		esw_get_tcpudp_port_snoop_config(fep,
+				(unsigned long *)ESW_PSNP);
+		ret = copy_to_user(ifr->ifr_data, ESW_PSNP,
+			(8 * sizeof(unsigned long)));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_PORT_MIRROR_CONF:
+	{
+		struct eswIoctlPortMirrorStatus PortMirrorStatus;
+
+		esw_get_port_mirroring(fep, &PortMirrorStatus);
+		ret = copy_to_user(ifr->ifr_data, &PortMirrorStatus,
+			sizeof(struct eswIoctlPortMirrorStatus));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_P0_FORCED_FORWARD:
+	{
+		unsigned long ForceForward;
+
+		esw_get_forced_forward(fep, &ForceForward);
+		ret = copy_to_user(ifr->ifr_data, &ForceForward,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_SWITCH_MODE:
+	{
+		unsigned long Config;
+
+		esw_get_switch_mode(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_BRIDGE_CONFIG:
+	{
+		unsigned long Config;
+
+		esw_get_bridge_port(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+	case ESW_GET_OUTPUT_QUEUE_STATUS:
+	{
+		struct esw_output_queue_status Config;
+		esw_get_output_queue_status(fep,
+			&Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(struct esw_output_queue_status));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_OUTPUT_PROCESS:
+	{
+		unsigned long Config;
+
+		esw_get_vlan_output_config(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_INPUT_PROCESS:
+	{
+		struct eswIoctlVlanInputStatus Config;
+
+		esw_get_vlan_input_config(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(struct eswIoctlVlanInputStatus));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_RESOLUTION_TABLE:
+	{
+		unsigned long Config;
+		unsigned char ConfigData;
+		ret = copy_from_user(&ConfigData,
+			ifr->ifr_data,
+			sizeof(unsigned char));
+		if (ret)
+			return -EFAULT;
+
+		printk(KERN_INFO "ESW_GET_VLAN_RESOLUTION_TABLE: %x \n",
+			ConfigData);
+
+		esw_get_vlan_resolution_table(fep, ConfigData, &Config);
+
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+
+	case ESW_GET_VLAN_DOMAIN_VERIFICATION:
+	{
+		unsigned long Config;
+
+		esw_get_vlan_verification(fep, &Config);
+		ret = copy_to_user(ifr->ifr_data, &Config,
+			sizeof(unsigned long));
+		if (ret)
+			return -EFAULT;
+	}
+		break;
+	/*------------------------------------------------------------------*/
+	default:
+		return -EOPNOTSUPP;
+	}
+
+
+	return ret;
+}
+
+static int
+switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct switch_enet_private *fep;
+	struct switch_t	*fecp;
+	struct cbd_t	*bdp;
+	void *bufaddr;
+	unsigned short	status;
+	unsigned long flags;
+
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)fep->hwp;
+
+	spin_lock_irqsave(&fep->hw_lock, flags);
+	/* Fill in a Tx ring entry */
+	bdp = fep->cur_tx;
+
+	status = bdp->cbd_sc;
+
+	if (status & BD_ENET_TX_READY) {
+		/*
+		 * Ooops.  All transmit buffers are full.  Bail out.
+		 * This should not happen, since dev->tbusy should be set.
+		 */
+		printk(KERN_ERR "%s: tx queue full!.\n", dev->name);
+		spin_unlock_irqrestore(&fep->hw_lock, flags);
+		return NETDEV_TX_BUSY;
+	}
+
+	/* Clear all of the status flags */
+	status &= ~BD_ENET_TX_STATS;
+
+	/* Set buffer length and buffer pointer	*/
+	bufaddr = skb->data;
+	bdp->cbd_datlen = skb->len;
+
+	/*
+	 * On some FEC implementations data must be aligned on
+	 * 4-byte boundaries. Use bounce buffers to copy data
+	 * and get it aligned. Ugh.
+	 */
+	if ((unsigned long) bufaddr & FEC_ALIGNMENT) {
+		unsigned int index;
+		index = bdp - fep->tx_bd_base;
+		memcpy(fep->tx_bounce[index],
+		       (void *)skb->data, skb->len);
+		bufaddr = fep->tx_bounce[index];
+	}
+
+#ifdef CONFIG_ARCH_MXS
+	swap_buffer(bufaddr, skb->len);
+#endif
+
+	/* Save skb pointer. */
+	fep->tx_skbuff[fep->skb_cur] = skb;
+
+	dev->stats.tx_bytes += skb->len;
+	fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
+
+	/*
+	 * Push the data cache so the CPM does not get stale memory
+	 * data.
+	 */
+	bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
+		FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+
+	/*
+	 * Send it on its way.  Tell FEC it's ready, interrupt when done,
+	 * it's the last BD of the frame, and to put the CRC on the end.
+	 */
+
+	status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
+			| BD_ENET_TX_LAST | BD_ENET_TX_TC);
+	bdp->cbd_sc = status;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	bdp->bdu = 0x00000000;
+	bdp->ebd_status = TX_BD_INT | TX_BD_TS;
+#endif
+	dev->trans_start = jiffies;
+
+	/* Trigger transmission start */
+	fecp->fec_x_des_active = MCF_ESW_TDAR_X_DES_ACTIVE;
+
+	/* If this was the last BD in the ring,
+	 * start at the beginning again.
+	 */
+	if (status & BD_ENET_TX_WRAP)
+		bdp = fep->tx_bd_base;
+	else
+		bdp++;
+
+	if (bdp == fep->dirty_tx) {
+		fep->tx_full = 1;
+		netif_stop_queue(dev);
+		printk(KERN_ERR "%s:  net stop\n", __func__);
+	}
+
+	fep->cur_tx = bdp;
+
+	spin_unlock_irqrestore(&fep->hw_lock, flags);
+
+	return 0;
+}
+
+static void
+switch_timeout(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	printk(KERN_INFO "%s: transmit timed out.\n", dev->name);
+	dev->stats.tx_errors++;
+	{
+	int	i;
+	struct cbd_t	*bdp;
+
+	printk(KERN_INFO "Ring data dump: cur_tx %lx%s,"
+		"dirty_tx %lx cur_rx: %lx\n",
+		(unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
+		(unsigned long)fep->dirty_tx,
+		(unsigned long)fep->cur_rx);
+
+	bdp = fep->tx_bd_base;
+	printk(KERN_INFO " tx: %u buffers\n",  TX_RING_SIZE);
+	for (i = 0 ; i < TX_RING_SIZE; i++) {
+		printk(KERN_INFO "  %08x: %04x %04x %08x\n",
+		       (uint) bdp,
+		       bdp->cbd_sc,
+		       bdp->cbd_datlen,
+		       (int) bdp->cbd_bufaddr);
+		bdp++;
+	}
+
+	bdp = fep->rx_bd_base;
+	printk(KERN_INFO " rx: %lu buffers\n",
+			(unsigned long) RX_RING_SIZE);
+	for (i = 0 ; i < RX_RING_SIZE; i++) {
+		printk(KERN_INFO "  %08x: %04x %04x %08x\n",
+		       (uint) bdp,
+		       bdp->cbd_sc,
+		       bdp->cbd_datlen,
+		       (int) bdp->cbd_bufaddr);
+		bdp++;
+	}
+	}
+	switch_restart(dev, fep->full_duplex);
+	netif_wake_queue(dev);
+}
+
+/*
+ * The interrupt handler.
+ * This is called from the MPC core interrupt.
+ */
+static irqreturn_t
+switch_enet_interrupt(int irq, void *dev_id)
+{
+	struct	net_device *dev = dev_id;
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct switch_t *fecp;
+	uint	int_events;
+	irqreturn_t ret = IRQ_NONE;
+
+	fecp = (struct switch_t *)dev->base_addr;
+
+	/* Get the interrupt events that caused us to be here */
+	do {
+		int_events = fecp->switch_ievent;
+		fecp->switch_ievent = int_events;
+		/* Handle receive event in its own function. */
+
+		/* Transmit OK, or non-fatal error. Update the buffer
+		 * descriptors. FEC handles all errors, we just discover
+		 *  them as part of the transmit process.
+		 */
+		if (int_events & MCF_ESW_ISR_LRN) {
+			if (fep->learning_irqhandle_enable)
+				esw_atable_dynamicms_learn_migration(
+					fep, fep->currTime);
+			ret = IRQ_HANDLED;
+		}
+
+		if (int_events & MCF_ESW_ISR_OD0)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_OD1)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_OD2)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_RXB)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_RXF) {
+			ret = IRQ_HANDLED;
+			switch_enet_rx(dev);
+		}
+
+		if (int_events & MCF_ESW_ISR_TXB)
+			ret = IRQ_HANDLED;
+
+		if (int_events & MCF_ESW_ISR_TXF) {
+			ret = IRQ_HANDLED;
+			switch_enet_tx(dev);
+		}
+
+	} while (int_events);
+
+	return ret;
+}
+
+
+static void
+switch_enet_tx(struct net_device *dev)
+{
+	struct	switch_enet_private *fep;
+	struct cbd_t	*bdp;
+	unsigned short status;
+	struct	sk_buff	*skb;
+
+	fep = netdev_priv(dev);
+	spin_lock(&fep->hw_lock);
+	bdp = fep->dirty_tx;
+
+	while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
+		if (bdp == fep->cur_tx && fep->tx_full == 0)
+			break;
+
+		dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
+				FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+		bdp->cbd_bufaddr = 0;
+		skb = fep->tx_skbuff[fep->skb_dirty];
+		/* Check for errors */
+		if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
+				   BD_ENET_TX_RL | BD_ENET_TX_UN |
+				   BD_ENET_TX_CSL)) {
+			dev->stats.tx_errors++;
+			if (status & BD_ENET_TX_HB)  /* No heartbeat */
+				dev->stats.tx_heartbeat_errors++;
+			if (status & BD_ENET_TX_LC)  /* Late collision */
+				dev->stats.tx_window_errors++;
+			if (status & BD_ENET_TX_RL)  /* Retrans limit */
+				dev->stats.tx_aborted_errors++;
+			if (status & BD_ENET_TX_UN)  /* Underrun */
+				dev->stats.tx_fifo_errors++;
+			if (status & BD_ENET_TX_CSL) /* Carrier lost */
+				dev->stats.tx_carrier_errors++;
+		} else {
+			dev->stats.tx_packets++;
+		}
+
+		if (status & BD_ENET_TX_READY)
+			printk(KERN_ERR "HEY! "
+				"Enet xmit interrupt and TX_READY.\n");
+		/*
+		 * Deferred means some collisions occurred during transmit,
+		 * but we eventually sent the packet OK.
+		 */
+		if (status & BD_ENET_TX_DEF)
+			dev->stats.collisions++;
+
+		/* Free the sk buffer associated with this last transmit */
+		dev_kfree_skb_any(skb);
+		fep->tx_skbuff[fep->skb_dirty] = NULL;
+		fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
+
+		/* Update pointer to next buffer descriptor to be transmitted */
+		if (status & BD_ENET_TX_WRAP)
+			bdp = fep->tx_bd_base;
+		else
+			bdp++;
+
+		/*
+		 * Since we have freed up a buffer, the ring is no longer
+		 * full.
+		 */
+		if (fep->tx_full) {
+			fep->tx_full = 0;
+			printk(KERN_ERR "%s: tx full is zero\n", __func__);
+			if (netif_queue_stopped(dev))
+				netif_wake_queue(dev);
+		}
+	}
+	fep->dirty_tx = bdp;
+	spin_unlock(&fep->hw_lock);
+}
+
+
+/*
+ * During a receive, the cur_rx points to the current incoming buffer.
+ * When we update through the ring, if the next incoming buffer has
+ * not been given to the system, we just set the empty indicator,
+ * effectively tossing the packet.
+ */
+static void
+switch_enet_rx(struct net_device *dev)
+{
+	struct	switch_enet_private *fep;
+	struct switch_t *fecp;
+	struct cbd_t *bdp;
+	unsigned short status;
+	struct	sk_buff	*skb;
+	ushort	pkt_len;
+	__u8 *data;
+
+#ifdef CONFIG_M532x
+	flush_cache_all();
+#endif
+
+	fep = netdev_priv(dev);
+	fecp = (struct switch_t *)fep->hwp;
+
+	spin_lock(&fep->hw_lock);
+	/*
+	 * First, grab all of the stats for the incoming packet.
+	 * These get messed up if we get called due to a busy condition.
+	 */
+	bdp = fep->cur_rx;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	printk(KERN_INFO "%s: cbd_sc %x cbd_datlen %x cbd_bufaddr %x "
+		"ebd_status %x bdu %x length_proto_type %x "
+		"payload_checksum %x\n",
+		__func__, bdp->cbd_sc, bdp->cbd_datlen,
+		bdp->cbd_bufaddr, bdp->ebd_status, bdp->bdu,
+		bdp->length_proto_type, bdp->payload_checksum);
+#endif
+
+while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
+	/*
+	 * Since we have allocated space to hold a complete frame,
+	 * the last indicator should be set.
+	 */
+	if ((status & BD_ENET_RX_LAST) == 0)
+		printk(KERN_INFO "SWITCH ENET: rcv is not +last\n");
+
+	if (!fep->opened)
+		goto rx_processing_done;
+
+	/* Check for errors. */
+	if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
+			   BD_ENET_RX_CR | BD_ENET_RX_OV)) {
+		dev->stats.rx_errors++;
+		if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
+			/* Frame too long or too short. */
+			dev->stats.rx_length_errors++;
+		}
+		if (status & BD_ENET_RX_NO)	/* Frame alignment */
+			dev->stats.rx_frame_errors++;
+		if (status & BD_ENET_RX_CR)	/* CRC Error */
+			dev->stats.rx_crc_errors++;
+		if (status & BD_ENET_RX_OV)	/* FIFO overrun */
+			dev->stats.rx_fifo_errors++;
+	}
+
+	/*
+	 * Report late collisions as a frame error.
+	 * On this error, the BD is closed, but we don't know what we
+	 * have in the buffer.  So, just drop this frame on the floor.
+	 */
+	if (status & BD_ENET_RX_CL) {
+		dev->stats.rx_errors++;
+		dev->stats.rx_frame_errors++;
+		goto rx_processing_done;
+	}
+
+	/* Process the incoming frame */
+	dev->stats.rx_packets++;
+	pkt_len = bdp->cbd_datlen;
+	dev->stats.rx_bytes += pkt_len;
+	data = (__u8 *)__va(bdp->cbd_bufaddr);
+
+	dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
+			DMA_FROM_DEVICE);
+#ifdef CONFIG_ARCH_MXS
+	swap_buffer(data, pkt_len);
+#endif
+	/*
+	 * This does 16 byte alignment, exactly what we need.
+	 * The packet length includes FCS, but we don't want to
+	 * include that when passing upstream as it messes up
+	 * bridging applications.
+	 */
+	skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
+	if (unlikely(!skb)) {
+		printk("%s: Memory squeeze, dropping packet.\n",
+			dev->name);
+		dev->stats.rx_dropped++;
+	} else {
+		skb_reserve(skb, NET_IP_ALIGN);
+		skb_put(skb, pkt_len - 4);      /* Make room */
+		skb_copy_to_linear_data(skb, data, pkt_len - 4);
+		skb->protocol = eth_type_trans(skb, dev);
+		netif_rx(skb);
+	}
+
+	bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
+		DMA_FROM_DEVICE);
+
+rx_processing_done:
+
+	/* Clear the status flags for this buffer */
+	status &= ~BD_ENET_RX_STATS;
+
+	/* Mark the buffer empty */
+	status |= BD_ENET_RX_EMPTY;
+	bdp->cbd_sc = status;
+
+	/* Update BD pointer to next entry */
+	if (status & BD_ENET_RX_WRAP)
+		bdp = fep->rx_bd_base;
+	else
+		bdp++;
+
+	/*
+	 * Doing this here will keep the FEC running while we process
+	 * incoming frames.  On a heavily loaded network, we should be
+	 * able to keep up at the expense of system resources.
+	 */
+	fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE;
+   } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
+	fep->cur_rx = bdp;
+
+	spin_unlock(&fep->hw_lock);
+}
+
+#ifdef FEC_PHY
+static int fec_mdio_transfer(struct mii_bus *bus, int phy_id,
+	int reg, int regval)
+{
+	struct net_device *dev = bus->priv;
+	unsigned long   flags;
+	struct switch_enet_private *fep;
+	int tries = 100;
+	int retval = 0;
+
+	fep = netdev_priv(dev);
+	spin_lock_irqsave(&fep->mii_lock, flags);
+
+	regval |= phy_id << 23;
+	writel(regval, fep->enet_addr + MCF_FEC_MMFR0);
+
+	/* wait for it to finish, this takes about 23 us on lite5200b */
+	while (!(readl(fep->enet_addr + MCF_FEC_EIR0) & FEC_ENET_MII)
+			&& --tries)
+		udelay(5);
+
+	if (!tries) {
+		printk(KERN_ERR "%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	writel(FEC_ENET_MII, fep->enet_addr + MCF_FEC_EIR0);
+	retval = readl(fep->enet_addr + MCF_FEC_MMFR0);
+	spin_unlock_irqrestore(&fep->mii_lock, flags);
+
+	return retval;
+}
+
+/*
+ * Phy section
+ */
+static void switch_adjust_link(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phy_dev = fep->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	phy_dev = g_phy_dev;
+	spin_lock_irqsave(&fep->hw_lock, flags);
+
+	/* Prevent a state halted on mii error */
+	if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
+		phy_dev->state = PHY_RESUMING;
+		goto spin_unlock;
+	}
+
+	/* Duplex link change */
+	if (phy_dev->link) {
+		if (fep->full_duplex != phy_dev->duplex) {
+			switch_restart(dev, phy_dev->duplex);
+			status_change = 1;
+		}
+	}
+
+	/* Link on or off change */
+	if (phy_dev->link != fep->link) {
+		fep->link = phy_dev->link;
+		if (phy_dev->link)
+			switch_restart(dev, phy_dev->duplex);
+		else
+			switch_stop(dev);
+		status_change = 1;
+	}
+
+spin_unlock:
+	spin_unlock_irqrestore(&fep->hw_lock, flags);
+
+	if (status_change)
+		phy_print_status(phy_dev);
+}
+
+/*
+ * NOTE: a MII transaction is during around 25 us, so polling it...
+ */
+static int fec_enet_mdio_poll(struct switch_enet_private *fep)
+ {
+	int timeout = FEC_MII_TIMEOUT;
+	unsigned int reg = 0;
+
+	fep->mii_timeout = 0;
+
+	/* wait for end of transfer */
+	reg = readl(fep->hwp + FEC_IEVENT);
+	while (!(reg & FEC_ENET_MII)) {
+		msleep(1);
+		if (timeout-- < 0) {
+			fep->mii_timeout = 1;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	struct switch_enet_private *fep = netdev_priv(bus->priv);
+
+
+	/* clear MII end of transfer bit */
+	writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT
+			/ sizeof(unsigned long));
+
+	/* start a read op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA, fep->enet_addr + FEC_MII_DATA
+		/ sizeof(unsigned long));
+
+	fec_enet_mdio_poll(fep);
+
+	/* return value */
+	return FEC_MMFR_DATA(readl(fep->enet_addr + FEC_MII_DATA
+				/ sizeof(unsigned long)));
+}
+
+static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+			   u16 value)
+{
+	struct switch_enet_private *fep = netdev_priv(bus->priv);
+
+	/* clear MII end of transfer bit */
+	writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT
+			/ sizeof(unsigned long));
+
+	/* start a read op */
+	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+		FEC_MMFR_TA | FEC_MMFR_DATA(value),
+		fep->enet_addr + FEC_MII_DATA / sizeof(unsigned long));
+
+	fec_enet_mdio_poll(fep);
+
+	return 0;
+}
+
+static int fec_enet_mdio_reset(struct mii_bus *bus)
+{
+	return 0;
+}
+
+static struct mii_bus *fec_enet_mii_init(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int err = -ENXIO, i;
+
+	fep->mii_timeout = 0;
+	/*
+	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
+	 */
+	fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */
+	fep->phy_speed <<= 2;
+#endif
+	writel(fep->phy_speed, fep->enet_addr + FEC_MII_SPEED
+			/ sizeof(unsigned long));
+
+	fep->mii_bus = mdiobus_alloc();
+	if (fep->mii_bus == NULL) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	fep->mii_bus->name = "fec_enet_mii_bus";
+	fep->mii_bus->read = fec_enet_mdio_read;
+	fep->mii_bus->write = fec_enet_mdio_write;
+	fep->mii_bus->reset = fec_enet_mdio_reset;
+	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", fep->pdev->id);
+	fep->mii_bus->priv = dev;
+
+	fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!fep->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_free_mdiobus;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		fep->mii_bus->irq[i] = PHY_POLL;
+
+	if (mdiobus_register(fep->mii_bus)) {
+		goto err_out_free_mdio_irq;
+	}
+
+	return fep->mii_bus;
+
+err_out_free_mdio_irq:
+	kfree(fep->mii_bus->irq);
+err_out_free_mdiobus:
+	mdiobus_free(fep->mii_bus);
+err_out:
+	return ERR_PTR(err);
+}
+#endif
+
+static int fec_enet_get_settings(struct net_device *dev,
+				  struct ethtool_cmd *cmd)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int fec_enet_set_settings(struct net_device *dev,
+				 struct ethtool_cmd *cmd)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct phy_device *phydev = fep->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static void fec_enet_get_drvinfo(struct net_device *dev,
+				 struct ethtool_drvinfo *info)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	strcpy(info->driver, fep->pdev->dev.driver->name);
+	strcpy(info->version, "Revision: 1.0");
+	strcpy(info->bus_info, dev_name(&dev->dev));
+}
+
+#ifdef FEC_PHY
+static int fec_switch_init_phy(struct net_device *dev)
+{
+	struct switch_enet_private *priv = netdev_priv(dev);
+	struct phy_device *phydev = NULL;
+	int i;
+
+	/* search for connect PHY device */
+	for (i = 0; i < PHY_MAX_ADDR; i++) {
+		struct phy_device *const tmp_phydev =
+			priv->mdio_bus->phy_map[i];
+
+		if (!tmp_phydev) {
+#ifdef FEC_DEBUG
+			printk(KERN_INFO "%s no PHY here at"
+				"mii_bus->phy_map[%d]\n",
+				__func__, i);
+#endif
+			continue; /* no PHY here... */
+		}
+
+#ifdef CONFIG_FEC_SHARED_PHY
+		if (priv->index == 0)
+			phydev = tmp_phydev;
+		else if (priv->index == 1) {
+			if (startnode == 1) {
+				phydev = tmp_phydev;
+				startnode = 0;
+			} else {
+				startnode++;
+				continue;
+			}
+		} else
+			printk(KERN_INFO "%s now we do not"
+				"support (%d) more than"
+				"2 phys shared "
+				"one mdio bus\n",
+				__func__, startnode);
+#else
+		phydev = tmp_phydev;
+#endif
+#ifdef FEC_DEBUG
+		printk(KERN_INFO "%s find PHY here at"
+			"mii_bus->phy_map[%d]\n",
+			__func__, i);
+#endif
+		break; /* found it */
+	}
+
+	/* now we are supposed to have a proper phydev, to attach to... */
+	if (!phydev) {
+		printk(KERN_INFO "%s: Don't found any phy device at all\n",
+			dev->name);
+		return -ENODEV;
+	}
+
+	priv->link = PHY_DOWN;
+	priv->old_link = PHY_DOWN;
+	priv->speed = 0;
+	priv->duplex = -1;
+
+	phydev = phy_connect(dev, dev_name(&phydev->dev),
+		&switch_adjust_link, 0, PHY_INTERFACE_MODE_MII);
+	if (IS_ERR(phydev)) {
+		printk(KERN_ERR " %s phy_connect failed\n", __func__);
+		return PTR_ERR(phydev);
+	}
+
+	printk(KERN_INFO "attached phy %i to driver %s\n",
+		phydev->addr, phydev->drv->name);
+
+	priv->phydev	= phydev;
+	g_phy_dev	= phydev;
+
+	return 0;
+}
+#endif
+
+static void fec_enet_free_buffers(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int i;
+	struct sk_buff *skb;
+	struct cbd_t	*bdp;
+
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		skb = fep->rx_skbuff[i];
+
+		if (bdp->cbd_bufaddr)
+			dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
+					FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+		if (skb)
+			dev_kfree_skb(skb);
+		bdp++;
+	}
+
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++)
+		kfree(fep->tx_bounce[i]);
+}
+
+static int fec_enet_alloc_buffers(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	int i;
+	struct sk_buff *skb;
+	struct cbd_t	*bdp;
+
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		skb = dev_alloc_skb(SWITCH_ENET_RX_FRSIZE);
+		if (!skb) {
+			fec_enet_free_buffers(dev);
+			return -ENOMEM;
+		}
+		fep->rx_skbuff[i] = skb;
+
+		bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
+				SWITCH_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+		bdp->cbd_sc = BD_ENET_RX_EMPTY;
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	bdp->bdu = 0x00000000;
+	bdp->ebd_status = RX_BD_INT;
+#endif
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_RX_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap. */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		fep->tx_bounce[i] = kmalloc(SWITCH_ENET_TX_FRSIZE, GFP_KERNEL);
+
+		bdp->cbd_sc = 0;
+		bdp->cbd_bufaddr = 0;
+#ifdef CONFIG_FEC_1588
+		bdp->cbd_esc = BD_ENET_TX_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap. */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	return 0;
+}
+
+static int
+switch_enet_open(struct net_device *dev)
+{
+	int ret;
+	struct switch_enet_private *fep = netdev_priv(dev);
+	/* I should reset the ring buffers here, but I don't yet know
+	 * a simple way to do that.
+	 */
+	clk_enable(fep->clk);
+	ret = fec_enet_alloc_buffers(dev);
+	if (ret)
+		return ret;
+
+	fep->link = 0;
+#ifdef FEC_PHY
+	clk_enable(fep->clk);
+	fec_switch_init_phy(dev);
+	phy_start(fep->phydev);
+#endif
+	fep->old_link = 0;
+	if (fep->phydev) {
+		/*
+		 * Set the initial link state to true. A lot of hardware
+		 * based on this device does not implement a PHY interrupt,
+		 * so we are never notified of link change.
+		 */
+		fep->link = 1;
+	} else {
+		fep->link = 1;
+		/* no phy,  go full duplex,  it's most likely a hub chip */
+		switch_restart(dev, 1);
+	}
+
+	/*
+	 * if the fec is the fist open, we need to do nothing
+	 * if the fec is not the fist open, we need to restart the FEC
+	 */
+	if (fep->sequence_done == 0)
+		switch_restart(dev, 1);
+	else
+		fep->sequence_done = 0;
+
+	fep->currTime = 0;
+	fep->learning_irqhandle_enable = 0;
+
+	esw_main(fep);
+
+	netif_start_queue(dev);
+	fep->opened = 1;
+
+	return 0;		/* Success */
+}
+
+static int
+switch_enet_close(struct net_device *dev)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	fep->opened = 0;
+	netif_stop_queue(dev);
+	switch_stop(dev);
+#ifdef FEC_PHY
+	phy_disconnect(fep->phydev);
+	phy_stop(fep->phydev);
+	phy_write(fep->phydev, MII_BMCR, BMCR_PDOWN);
+#endif
+	fec_enet_free_buffers(dev);
+	clk_disable(fep->clk);
+
+	return 0;
+}
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ * Skeleton taken from sunlance driver.
+ * The CPM Ethernet implementation allows Multicast as well as individual
+ * MAC address filtering.  Some of the drivers check to make sure it is
+ * a group multicast address, and discard those that are not.  I guess I
+ * will do the same for now, but just remove the test if you want
+ * individual filtering as well (do the upper net layers want or support
+ * this kind of feature?).
+ */
+
+/* bits in hash */
+#define HASH_BITS	6
+#define CRC32_POLY	0xEDB88320
+
+static void set_multicast_list(struct net_device *dev)
+{
+	struct switch_enet_private *fep;
+	struct switch_t *ep;
+	struct dev_mc_list *dmi;
+	unsigned int i, j, bit, data, crc;
+
+	fep = netdev_priv(dev);
+	ep = fep->hwp;
+
+	if (dev->flags & IFF_PROMISC) {
+		/* ep->fec_r_cntrl |= 0x0008; */
+		printk(KERN_INFO "%s IFF_PROMISC\n", __func__);
+	} else {
+
+		/* ep->fec_r_cntrl &= ~0x0008; */
+
+		if (dev->flags & IFF_ALLMULTI) {
+			/*
+			 * Catch all multicast addresses, so set the
+			 * filter to all 1's.
+			 */
+			printk(KERN_INFO "%s IFF_ALLMULTI\n", __func__);
+		} else {
+			/*
+			 * Clear filter and add the addresses
+			 * in hash register
+			 */
+			/*
+			 * ep->fec_grp_hash_table_high = 0;
+			 * ep->fec_grp_hash_table_low = 0;
+			 */
+
+			dmi = dev->mc_list;
+
+			for (j = 0; j < dev->mc_count;
+				j++, dmi = dmi->next) {
+				/* Only support group multicast for now */
+				if (!(dmi->dmi_addr[0] & 1))
+					continue;
+
+				/* calculate crc32 value of mac address	*/
+				crc = 0xffffffff;
+
+				for (i = 0; i < dmi->dmi_addrlen; i++) {
+					data = dmi->dmi_addr[i];
+					for (bit = 0; bit < 8; bit++,
+						data >>= 1) {
+						crc = (crc >> 1) ^
+						(((crc ^ data) & 1) ?
+						CRC32_POLY : 0);
+					}
+				}
+
+			}
+		}
+	}
+}
+
+/* Set a MAC change in hardware */
+static int
+switch_set_mac_address(struct net_device *dev, void *p)
+{
+	struct switch_enet_private *fep = netdev_priv(dev);
+	struct sockaddr *addr = p;
+	struct switch_t  *fecp;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+
+	fecp = fep->hwp;
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
+		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
+		fep->enet_addr + MCF_FEC_PAUR0);
+	writel((dev->dev_addr[5] << 16)
+		| ((dev->dev_addr[4]+(unsigned char)(0)) << 24),
+		fep->enet_addr + MCF_FEC_PAUR0);
+
+	writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
+		(dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
+		fep->enet_addr + MCF_FEC_PAUR1);
+	writel((dev->dev_addr[5] << 16)
+		| ((dev->dev_addr[4]+(unsigned char)(1)) << 24),
+		fep->enet_addr + MCF_FEC_PAUR1);
+
+	esw_update_atable_static(dev->dev_addr, 7, 7, fep);
+	fecp->ESW_DBCR = MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2;
+
+	return 0;
+}
+
+static struct ethtool_ops fec_enet_ethtool_ops = {
+	.get_settings           = fec_enet_get_settings,
+	.set_settings           = fec_enet_set_settings,
+	.get_drvinfo            = fec_enet_get_drvinfo,
+	.get_link               = ethtool_op_get_link,
+ };
+static const struct net_device_ops fec_netdev_ops = {
+       .ndo_open		= switch_enet_open,
+       .ndo_stop		= switch_enet_close,
+       .ndo_do_ioctl		= switch_enet_ioctl,
+       .ndo_start_xmit		= switch_enet_start_xmit,
+       .ndo_set_multicast_list	= set_multicast_list,
+       .ndo_tx_timeout		= switch_timeout,
+       .ndo_set_mac_address	= switch_set_mac_address,
+};
+
+static int switch_mac_addr_setup(char *mac_addr)
+{
+	char *ptr, *p = mac_addr;
+	unsigned long tmp;
+	int i = 0, ret = 0;
+
+	while (p && (*p) && i < 6) {
+		ptr = strchr(p, ':');
+		if (ptr)
+			*ptr++ = '\0';
+		if (strlen(p)) {
+			ret = strict_strtoul(p, 16, &tmp);
+			if (ret < 0 || tmp > 0xff)
+				break;
+			switch_mac_default[i++] = tmp;
+		}
+		p = ptr;
+	}
+
+	return 0;
+}
+
+__setup("fec_mac=", switch_mac_addr_setup);
+
+/* Initialize the FEC Ethernet */
+static int __init switch_enet_init(struct net_device *dev,
+	int slot, struct platform_device *pdev)
+{
+	struct switch_enet_private	*fep = netdev_priv(dev);
+	struct resource 	*r;
+	struct cbd_t		*bdp;
+	struct cbd_t		*cbd_base;
+	struct switch_t	*fecp;
+	int	i;
+	struct switch_platform_data *plat = pdev->dev.platform_data;
+
+	/* Only allow us to be probed once. */
+	if (slot >= SWITCH_MAX_PORTS)
+		return -ENXIO;
+
+	/* Allocate memory for buffer descriptors */
+	cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
+			 GFP_KERNEL);
+	if (!cbd_base) {
+		printk(KERN_ERR "FEC: allocate descriptor memory failed?\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&fep->hw_lock);
+	spin_lock_init(&fep->mii_lock);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r)
+		return -ENXIO;
+
+	r = request_mem_region(r->start, resource_size(r), pdev->name);
+	if (!r)
+		return -EBUSY;
+
+	fep->enet_addr = ioremap(r->start, resource_size(r));
+
+	dev->irq = platform_get_irq(pdev, 0);
+
+	/*
+	 * Create an Ethernet device instance.
+	 * The switch lookup address memory start 0x800FC000
+	 */
+	fecp = (struct switch_t *)(fep->enet_addr + ENET_SWI_PHYS_ADDR_OFFSET
+		/ sizeof(unsigned long));
+	plat->switch_hw[1] = (unsigned long)fecp + MCF_ESW_LOOKUP_MEM_OFFSET;
+
+	fep->index = slot;
+	fep->hwp = fecp;
+	fep->hwentry = (struct eswAddrTable_t *)plat->switch_hw[1];
+	fep->netdev = dev;
+#ifdef CONFIG_FEC_SHARED_PHY
+	fep->phy_hwp = (struct switch_t *) plat->switch_hw[slot & ~1];
+#else
+	fep->phy_hwp = fecp;
+#endif
+
+	fep->clk = clk_get(&pdev->dev, "fec_clk");
+	if (IS_ERR(fep->clk))
+		return PTR_ERR(fep->clk);
+	clk_enable(fep->clk);
+
+
+	/* PHY reset should be done during clock on */
+	if (plat) {
+		fep->phy_interface = plat->fec_enet->phy;
+		if (plat->fec_enet->init && plat->fec_enet->init())
+			return -EIO;
+
+		/*
+		 * The priority for getting MAC address is:
+		 * (1) kernel command line fec_mac = xx:xx:xx...
+		 * (2) platform data mac field got from fuse etc
+		 * (3) bootloader set the FEC mac register
+		 */
+
+		if (!is_valid_ether_addr(switch_mac_default) &&
+			plat->fec_enet->mac &&
+			is_valid_ether_addr(plat->fec_enet->mac))
+			memcpy(switch_mac_default, plat->fec_enet->mac,
+						sizeof(switch_mac_default));
+	} else
+		fep->phy_interface = PHY_INTERFACE_MODE_MII;
+
+	/*
+	 * SWITCH CONFIGURATION
+	 */
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_RST;
+	udelay(10);
+
+	/* enable switch*/
+	fecp->ESW_MODE = MCF_ESW_MODE_STATRST;
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_EN;
+
+	/* Enable transmit/receive on all ports */
+	fecp->ESW_PER = 0xffffffff;
+	/* Management port configuration,
+	 * make port 0 as management port
+	 */
+	fecp->ESW_BMPC = 0;
+
+	/* clear all switch irq */
+	fecp->switch_ievent = 0xffffffff;
+	fecp->switch_imask  = 0;
+	udelay(10);
+
+	plat->request_intrs = switch_request_intrs;
+	plat->set_mii = switch_set_mii;
+	plat->get_mac = switch_get_mac;
+	plat->enable_phy_intr = switch_enable_phy_intr;
+	plat->disable_phy_intr = switch_disable_phy_intr;
+	plat->phy_ack_intr = switch_phy_ack_intr;
+	plat->localhw_setup = switch_localhw_setup;
+	plat->uncache = switch_uncache;
+	plat->platform_flush_cache = switch_platform_flush_cache;
+
+	/*
+	 * Set the Ethernet address.  If using multiple Enets on the 8xx,
+	 * this needs some work to get unique addresses.
+	 *
+	 * This is our default MAC address unless the user changes
+	 * it via eth_mac_addr (our dev->set_mac_addr handler).
+	 */
+	if (plat && plat->get_mac)
+		plat->get_mac(dev);
+
+	/* Set receive and transmit descriptor base */
+	fep->rx_bd_base = cbd_base;
+	fep->tx_bd_base = cbd_base + RX_RING_SIZE;
+
+	/* Initialize the receive buffer descriptors */
+	bdp = fep->rx_bd_base;
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		bdp->cbd_sc = 0;
+
+#ifdef L2SWITCH_ENHANCED_BUFFER
+		bdp->bdu = 0x00000000;
+		bdp->ebd_status = RX_BD_INT;
+#endif
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	/* ...and the same for transmmit */
+	bdp = fep->tx_bd_base;
+	for (i = 0; i < TX_RING_SIZE; i++) {
+		/* Initialize the BD for every fragment in the page */
+		bdp->cbd_sc = 0;
+		bdp->cbd_bufaddr = 0;
+		bdp++;
+	}
+
+	/* Set the last buffer to wrap */
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+
+	/*
+	 * Install our interrupt handlers. This varies depending on
+	 * the architecture.
+	 */
+	if (plat && plat->request_intrs)
+		plat->request_intrs(dev, switch_enet_interrupt, dev);
+
+	dev->base_addr = (unsigned long)fecp;
+
+	/* The FEC Ethernet specific entries in the device structure. */
+	dev->netdev_ops = &fec_netdev_ops;
+	dev->ethtool_ops = &fec_enet_ethtool_ops;
+
+	/* setup MII interface */
+	if (plat && plat->set_mii)
+		plat->set_mii(dev);
+
+
+#ifndef CONFIG_FEC_SHARED_PHY
+	fep->phy_addr = 0;
+#else
+	fep->phy_addr = fep->index;
+#endif
+
+	fep->sequence_done = 1;
+	return 0;
+}
+
+static void enet_reset(struct net_device *dev, int duplex)
+{
+	struct switch_enet_private	*fep = netdev_priv(dev);
+
+	/* ECR */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	writel(MCF_FEC_ECR_ENA_1588
+			| MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_ENA_1588,
+			| MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR1);
+#else /*legac buffer*/
+	writel(MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(MCF_FEC_ECR_MAGIC_ENA,
+			fep->enet_addr + MCF_FEC_ECR1);
+#endif
+	/* EMRBR */
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0);
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1);
+
+	/*
+	 * set the receive and transmit BDs ring base to
+	 * hardware registers(ERDSR & ETDSR)
+	 */
+	writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR0);
+	writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR1);
+	writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE,
+			fep->enet_addr + MCF_FEC_ETDSR0);
+	writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE,
+			fep->enet_addr + MCF_FEC_ETDSR1);
+#ifdef CONFIG_ARCH_MXS
+	/* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */
+	writel(fep->phy_speed,
+			fep->enet_addr + MCF_FEC_MSCR0);
+	writel(fep->phy_speed,
+			fep->enet_addr + MCF_FEC_MSCR1);
+#endif
+	fep->full_duplex = duplex;
+
+	/* EIR */
+	writel(0, fep->enet_addr + MCF_FEC_EIR0);
+	writel(0, fep->enet_addr + MCF_FEC_EIR1);
+
+	/* IAUR */
+	writel(0, fep->enet_addr + MCF_FEC_IAUR0);
+	writel(0, fep->enet_addr + MCF_FEC_IAUR1);
+
+	/* IALR */
+	writel(0, fep->enet_addr + MCF_FEC_IALR0);
+	writel(0, fep->enet_addr + MCF_FEC_IALR1);
+
+	/* GAUR */
+	writel(0, fep->enet_addr + MCF_FEC_GAUR0);
+	writel(0, fep->enet_addr + MCF_FEC_GAUR1);
+
+	/* GALR */
+	writel(0, fep->enet_addr + MCF_FEC_GALR0);
+	writel(0, fep->enet_addr + MCF_FEC_GALR1);
+
+	/* EMRBR */
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0);
+	writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1);
+	msleep(10);
+
+	/* EIMR */
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR0);
+	writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->enet_addr + MCF_FEC_EIMR1);
+
+	/* PALR PAUR */
+	/* Set the station address for the ENET Adapter */
+	writel(dev->dev_addr[3] |
+		dev->dev_addr[2]<<8 |
+		dev->dev_addr[1]<<16 |
+		dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR0);
+	writel(dev->dev_addr[5]<<16 |
+		(dev->dev_addr[4]+(unsigned char)(0))<<24,
+		fep->enet_addr + MCF_FEC_PAUR0);
+	writel(dev->dev_addr[3] |
+		dev->dev_addr[2]<<8 |
+		dev->dev_addr[1]<<16 |
+		dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR1);
+	writel(dev->dev_addr[5]<<16 |
+		(dev->dev_addr[4]+(unsigned char)(1))<<24,
+		fep->enet_addr + MCF_FEC_PAUR1);
+
+	/* RCR */
+	writel(readl(fep->enet_addr + MCF_FEC_RCR0)
+		| MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM,
+		fep->enet_addr + MCF_FEC_RCR0);
+	writel(readl(fep->enet_addr + MCF_FEC_RCR1)
+		| MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM,
+		fep->enet_addr + MCF_FEC_RCR1);
+
+	/* TCR */
+	writel(0x1c, fep->enet_addr + MCF_FEC_TCR0);
+	writel(0x1c, fep->enet_addr + MCF_FEC_TCR1);
+
+	/* ECR */
+	writel(readl(fep->enet_addr + MCF_FEC_ECR0) | MCF_FEC_ECR_ETHER_EN,
+			fep->enet_addr + MCF_FEC_ECR0);
+	writel(readl(fep->enet_addr + MCF_FEC_ECR1) | MCF_FEC_ECR_ETHER_EN,
+			fep->enet_addr + MCF_FEC_ECR1);
+}
+
+/*
+ * This function is called to start or restart the FEC during a link
+ * change.  This only happens when switching between half and full
+ * duplex.
+ */
+static void
+switch_restart(struct net_device *dev, int duplex)
+{
+	struct switch_enet_private *fep;
+	struct switch_t *fecp;
+	int i;
+	struct switch_platform_data *plat;
+
+	fep = netdev_priv(dev);
+	fecp = fep->hwp;
+	plat = fep->pdev->dev.platform_data;
+	/*
+	 * Whack a reset.  We should wait for this.
+	 */
+	/* fecp->fec_ecntrl = 1; */
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_RST;
+	udelay(10);
+	fecp->ESW_MODE = MCF_ESW_MODE_STATRST;
+	fecp->ESW_MODE = MCF_ESW_MODE_SW_EN;
+
+	/* Enable transmit/receive on all ports */
+	fecp->ESW_PER = 0xffffffff;
+	/*
+	 * Management port configuration,
+	 * make port 0 as management port
+	 */
+	fecp->ESW_BMPC = 0;
+
+	/* Clear any outstanding interrupt */
+	fecp->switch_ievent = 0xffffffff;
+	/*if (plat && plat->enable_phy_intr)
+	 *	plat->enable_phy_intr();
+	 */
+
+	/* Reset all multicast */
+	/*
+	 * fecp->fec_grp_hash_table_high = 0;
+	 * fecp->fec_grp_hash_table_low = 0;
+	 */
+
+	/* Set maximum receive buffer size */
+	fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
+
+	if (plat && plat->localhw_setup)
+		plat->localhw_setup();
+
+	/* Set receive and transmit descriptor base */
+	fecp->fec_r_des_start = fep->bd_dma;
+	fecp->fec_x_des_start = (unsigned long)fep->bd_dma
+		+ sizeof(struct cbd_t) * RX_RING_SIZE;
+
+	fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
+	fep->cur_rx = fep->rx_bd_base;
+
+	/* Reset SKB transmit buffers */
+	fep->skb_cur = fep->skb_dirty = 0;
+	for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+		if (fep->tx_skbuff[i] != NULL) {
+			dev_kfree_skb_any(fep->tx_skbuff[i]);
+			fep->tx_skbuff[i] = NULL;
+		}
+	}
+
+	enet_reset(dev, duplex);
+	esw_clear_atable(fep);
+
+	/* And last, enable the transmit and receive processing */
+	fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE;
+
+	/* Enable interrupts we wish to service */
+	fecp->switch_ievent = 0xffffffff;
+	fecp->switch_imask  = MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF |
+		MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB;
+
+#ifdef SWITCH_DEBUG
+	printk(KERN_INFO "%s: switch hw init over."
+		"isr %x mask %x rx_addr %x %x tx_addr %x %x."
+		"fec_r_buff_size %x\n", __func__,
+		fecp->switch_ievent, fecp->switch_imask, fecp->fec_r_des_start,
+		&fecp->fec_r_des_start, fecp->fec_x_des_start,
+		&fecp->fec_x_des_start, fecp->fec_r_buff_size);
+	printk(KERN_INFO "%s: fecp->ESW_DBCR %x, fecp->ESW_P0FFEN %x fecp->ESW_BKLR %x\n",
+		__func__, fecp->ESW_DBCR, fecp->ESW_P0FFEN, fecp->ESW_BKLR);
+
+	printk(KERN_INFO "fecp->portstats[0].MCF_ESW_POQC %x,"
+		"fecp->portstats[0].MCF_ESW_PMVID %x,"
+		"fecp->portstats[0].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[0].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[0].MCF_ESW_POQC,
+		fecp->port_statistics_status[0].MCF_ESW_PMVID,
+		fecp->port_statistics_status[0].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[0].MCF_ESW_PBL);
+
+	printk(KERN_INFO "fecp->portstats[1].MCF_ESW_POQC %x,"
+		"fecp->portstats[1].MCF_ESW_PMVID %x,"
+		"fecp->portstats[1].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[1].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[1].MCF_ESW_POQC,
+		fecp->port_statistics_status[1].MCF_ESW_PMVID,
+		fecp->port_statistics_status[1].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[1].MCF_ESW_PBL);
+
+	printk(KERN_INFO "fecp->portstats[2].MCF_ESW_POQC %x,"
+		"fecp->portstats[2].MCF_ESW_PMVID %x,"
+		"fecp->portstats[2].MCF_ESW_PMVTAG %x,"
+		"fecp->portstats[2].MCF_ESW_PBL %x\n",
+		fecp->port_statistics_status[2].MCF_ESW_POQC,
+		fecp->port_statistics_status[2].MCF_ESW_PMVID,
+		fecp->port_statistics_status[2].MCF_ESW_PMVTAG,
+		fecp->port_statistics_status[2].MCF_ESW_PBL);
+#endif
+}
+
+static void
+switch_stop(struct net_device *dev)
+{
+	struct switch_t *fecp;
+	struct switch_enet_private *fep;
+	struct switch_platform_data *plat;
+
+#ifdef SWITCH_DEBUG
+	printk(KERN_ERR "%s\n", __func__);
+#endif
+	fep = netdev_priv(dev);
+	fecp = fep->hwp;
+	plat = fep->pdev->dev.platform_data;
+	/* We cannot expect a graceful transmit stop without link !!! */
+	if (fep->link)
+		udelay(10);
+
+	/* Whack a reset.  We should wait for this */
+	udelay(10);
+}
+
+#ifdef FEC_PHY
+static int fec_mdio_register(struct net_device *dev,
+	int slot)
+{
+	int err = 0;
+	struct switch_enet_private *fep = netdev_priv(dev);
+
+	fep->mdio_bus = mdiobus_alloc();
+	if (!fep->mdio_bus) {
+		printk(KERN_ERR "ethernet switch mdiobus_alloc fail\n");
+		return -ENOMEM;
+	}
+
+	if (slot == 0) {
+		fep->mdio_bus->name = "FEC switch MII 0 Bus";
+		strcpy(fep->mdio_bus->id, "0");
+	} else if (slot == 1) {
+		fep->mdio_bus->name = "FEC switch MII 1 Bus";
+		strcpy(fep->mdio_bus->id, "1");
+	} else {
+		printk(KERN_ERR "Now Fec switch can not"
+			"support more than 2 mii bus\n");
+	}
+
+	fep->mdio_bus->read = &fec_enet_mdio_read;
+	fep->mdio_bus->write = &fec_enet_mdio_write;
+	fep->mdio_bus->priv = dev;
+	err = mdiobus_register(fep->mdio_bus);
+	if (err) {
+		mdiobus_free(fep->mdio_bus);
+		printk(KERN_ERR "%s: ethernet mdiobus_register fail\n",
+			dev->name);
+		return -EIO;
+	}
+
+	printk(KERN_INFO "mdiobus_register %s ok\n",
+		fep->mdio_bus->name);
+	return err;
+}
+#endif
+
+static int __init eth_switch_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	int i, err;
+	struct switch_enet_private *fep;
+	struct switch_platform_private *chip;
+
+	printk(KERN_INFO "Ethernet Switch Version 1.0\n");
+	chip = kzalloc(sizeof(struct switch_platform_private) +
+		sizeof(struct switch_enet_private *) * SWITCH_MAX_PORTS,
+		GFP_KERNEL);
+	if (!chip) {
+		err = -ENOMEM;
+		printk(KERN_ERR "%s: kzalloc fail %x\n", __func__,
+			(unsigned int)chip);
+		return err;
+	}
+
+	chip->pdev = pdev;
+	chip->num_slots = SWITCH_MAX_PORTS;
+	platform_set_drvdata(pdev, chip);
+
+	for (i = 0; (i < chip->num_slots); i++) {
+		dev = alloc_etherdev(sizeof(struct switch_enet_private));
+		if (!dev) {
+			printk(KERN_ERR "%s: ethernet switch\
+				 alloc_etherdev fail\n",
+				dev->name);
+			return -ENOMEM;
+		}
+
+		fep = netdev_priv(dev);
+		fep->pdev = pdev;
+		printk(KERN_ERR "%s: ethernet switch port %d init\n",
+			__func__, i);
+		err = switch_enet_init(dev, i, pdev);
+		if (err) {
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			continue;
+		}
+
+		chip->fep_host[i] = fep;
+		/* disable mdio */
+#ifdef FEC_PHY
+#ifdef CONFIG_FEC_SHARED_PHY
+		if (i == 0)
+			err = fec_mdio_register(dev, 0);
+		else {
+			fep->mdio_bus = chip->fep_host[0]->mdio_bus;
+			printk(KERN_INFO "FEC%d SHARED the %s ok\n",
+				i, fep->mdio_bus->name);
+		}
+#else
+		err = fec_mdio_register(dev, i);
+#endif
+		if (err) {
+			printk(KERN_ERR "%s: ethernet switch fec_mdio_register\n",
+				dev->name);
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			return -ENOMEM;
+		}
+#endif
+		/* setup timer for Learning  Aging function */
+		/*
+		 * setup_timer(&fep->timer_aging,
+		 *	l2switch_aging_timer, (unsigned long)fep);
+		 */
+		init_timer(&fep->timer_aging);
+		fep->timer_aging.function = l2switch_aging_timer;
+		fep->timer_aging.data = (unsigned long) fep;
+		fep->timer_aging.expires = jiffies + LEARNING_AGING_TIMER;
+
+		/* register network device */
+		if (register_netdev(dev) != 0) {
+			free_netdev(dev);
+			platform_set_drvdata(pdev, NULL);
+			kfree(chip);
+			printk(KERN_ERR "%s: ethernet switch register_netdev fail\n",
+				dev->name);
+			return -EIO;
+		}
+		printk(KERN_INFO "%s: ethernet switch %pM\n",
+				dev->name, dev->dev_addr);
+	}
+
+	return 0;
+}
+
+static int eth_switch_remove(struct platform_device *pdev)
+{
+	int i;
+	struct net_device *dev;
+	struct switch_enet_private *fep;
+	struct switch_platform_private *chip;
+
+	chip = platform_get_drvdata(pdev);
+	if (chip) {
+		for (i = 0; i < chip->num_slots; i++) {
+			fep = chip->fep_host[i];
+			dev = fep->netdev;
+			fep->sequence_done = 1;
+			unregister_netdev(dev);
+			free_netdev(dev);
+
+			del_timer_sync(&fep->timer_aging);
+		}
+
+		platform_set_drvdata(pdev, NULL);
+		kfree(chip);
+
+	} else
+		printk(KERN_ERR "%s: can not get the "
+			"switch_platform_private %x\n", __func__,
+			(unsigned int)chip);
+
+	return 0;
+}
+
+static struct platform_driver eth_switch_driver = {
+	.probe          = eth_switch_probe,
+	.remove         = eth_switch_remove,
+	.driver         = {
+		.name   = "mxs-l2switch",
+		.owner  = THIS_MODULE,
+	},
+};
+
+static int __init fec_l2switch_init(void)
+{
+	return platform_driver_register(&eth_switch_driver);;
+}
+
+static void __exit fec_l2_switch_exit(void)
+{
+	platform_driver_unregister(&eth_switch_driver);
+}
+
+module_init(fec_l2switch_init);
+module_exit(fec_l2_switch_exit);
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/fec_switch.h b/drivers/net/fec_switch.h
new file mode 100644
index 000000000000..7b9f6a180f6a
--- /dev/null
+++ b/drivers/net/fec_switch.h
@@ -0,0 +1,1121 @@
+/****************************************************************************/
+
+/*
+ *	mcfswitch -- L2 Switch Controller for Modelo ColdFire SoC
+ *		   processors.
+ *
+ *      Copyright (C) 2010 Freescale Semiconductor,Inc.All rights reserved.
+ *
+ *     This program is free software; you can redistribute it and/or modify
+ *     it under the terms of the GNU General Public License as published by
+ *     the Free Software Foundation; either version 2 of the License, or (at
+ *     your option) any later version.
+ *
+ */
+
+/****************************************************************************/
+#ifndef SWITCH_H
+#define	SWITCH_H
+/****************************************************************************/
+/* The Switch stores dest/src/type, data, and checksum for receive packets.
+ */
+#define PKT_MAXBUF_SIZE         1518
+#define PKT_MINBUF_SIZE         64
+#define PKT_MAXBLR_SIZE         1520
+
+/*
+ * The 5441x RX control register also contains maximum frame
+ * size bits.
+ */
+#define OPT_FRAME_SIZE  (PKT_MAXBUF_SIZE << 16)
+
+/*
+ * Some hardware gets it MAC address out of local flash memory.
+ * if this is non-zero then assume it is the address to get MAC from.
+ */
+#define FEC_FLASHMAC    0
+
+/* The number of Tx and Rx buffers.  These are allocated from the page
+ * pool.  The code may assume these are power of two, so it it best
+ * to keep them that size.
+ * We don't need to allocate pages for the transmitter.  We just use
+ * the skbuffer directly.
+ */
+#ifdef CONFIG_SWITCH_DMA_USE_SRAM
+#define SWITCH_ENET_RX_PAGES       6
+#else
+#define SWITCH_ENET_RX_PAGES       8
+#endif
+
+#define SWITCH_ENET_RX_FRSIZE      2048
+#define SWITCH_ENET_RX_FRPPG       (PAGE_SIZE / SWITCH_ENET_RX_FRSIZE)
+#define RX_RING_SIZE            (SWITCH_ENET_RX_FRPPG * SWITCH_ENET_RX_PAGES)
+#define SWITCH_ENET_TX_FRSIZE      2048
+#define SWITCH_ENET_TX_FRPPG       (PAGE_SIZE / SWITCH_ENET_TX_FRSIZE)
+
+#ifdef CONFIG_SWITCH_DMA_USE_SRAM
+#define TX_RING_SIZE            8      /* Must be power of two */
+#define TX_RING_MOD_MASK        7      /*   for this to work */
+#else
+#define TX_RING_SIZE            16      /* Must be power of two */
+#define TX_RING_MOD_MASK        15      /*   for this to work */
+#endif
+
+#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
+#error "L2SWITCH: descriptor ring size constants too large"
+#endif
+/*-----------------------------------------------------------------------*/
+struct esw_output_queue_status {
+	unsigned long ESW_MMSR;
+	unsigned long ESW_LMT;
+	unsigned long ESW_LFC;
+	unsigned long ESW_PCSR;
+	unsigned long ESW_IOSR;
+	unsigned long ESW_QWT;
+	unsigned long esw_reserved;
+	unsigned long ESW_P0BCT;
+};
+struct esw_statistics_status {
+	/*
+	 * Total number of incoming frames processed
+	 * but discarded in switch
+	 */
+	unsigned long ESW_DISCN;
+	/*Sum of bytes of frames counted in ESW_DISCN*/
+	unsigned long ESW_DISCB;
+	/*
+	 * Total number of incoming frames processed
+	 * but not discarded in switch
+	 */
+	unsigned long ESW_NDISCN;
+	/*Sum of bytes of frames counted in ESW_NDISCN*/
+	unsigned long ESW_NDISCB;
+};
+
+struct esw_port_statistics_status {
+	/*outgoing frames discarded due to transmit queue congestion*/
+	unsigned long MCF_ESW_POQC;
+	/*incoming frames discarded due to VLAN domain mismatch*/
+	unsigned long MCF_ESW_PMVID;
+	/*incoming frames discarded due to untagged discard*/
+	unsigned long MCF_ESW_PMVTAG;
+	/*incoming frames discarded due port is in blocking state*/
+	unsigned long MCF_ESW_PBL;
+};
+
+struct switch_t {
+	unsigned long ESW_REVISION;
+	unsigned long ESW_SCRATCH;
+	unsigned long ESW_PER;
+	unsigned long reserved0[1];
+	unsigned long ESW_VLANV;
+	unsigned long ESW_DBCR;
+	unsigned long ESW_DMCR;
+	unsigned long ESW_BKLR;
+	unsigned long ESW_BMPC;
+	unsigned long ESW_MODE;
+	unsigned long ESW_VIMSEL;
+	unsigned long ESW_VOMSEL;
+	unsigned long ESW_VIMEN;
+	unsigned long ESW_VID;/*0x34*/
+	/*from 0x38 0x3C*/
+	unsigned long esw_reserved0[2];
+	unsigned long ESW_MCR;/*0x40*/
+	unsigned long ESW_EGMAP;
+	unsigned long ESW_INGMAP;
+	unsigned long ESW_INGSAL;
+	unsigned long ESW_INGSAH;
+	unsigned long ESW_INGDAL;
+	unsigned long ESW_INGDAH;
+	unsigned long ESW_ENGSAL;
+	unsigned long ESW_ENGSAH;
+	unsigned long ESW_ENGDAL;
+	unsigned long ESW_ENGDAH;
+	unsigned long ESW_MCVAL;/*0x6C*/
+	/*from 0x70--0x7C*/
+	unsigned long esw_reserved1[4];
+	unsigned long ESW_MMSR;/*0x80*/
+	unsigned long ESW_LMT;
+	unsigned long ESW_LFC;
+	unsigned long ESW_PCSR;
+	unsigned long ESW_IOSR;
+	unsigned long ESW_QWT;/*0x94*/
+	unsigned long esw_reserved2[1];/*0x98*/
+	unsigned long ESW_P0BCT;/*0x9C*/
+	/*from 0xA0-0xB8*/
+	unsigned long esw_reserved3[7];
+	unsigned long ESW_P0FFEN;/*0xBC*/
+	unsigned long ESW_PSNP[8];
+	unsigned long ESW_IPSNP[8];
+	unsigned long ESW_PVRES[3];
+	/*from 0x10C-0x13C*/
+	unsigned long esw_reserved4[13];
+	unsigned long ESW_IPRES;/*0x140*/
+	/*from 0x144-0x17C*/
+	unsigned long esw_reserved5[15];
+	unsigned long ESW_PRES[3];
+	/*from 0x18C-0x1FC*/
+	unsigned long esw_reserved6[29];
+	unsigned long ESW_PID[3];
+	/*from 0x20C-0x27C*/
+	unsigned long esw_reserved7[29];
+	unsigned long ESW_VRES[32];
+	unsigned long ESW_DISCN;/*0x300*/
+	unsigned long ESW_DISCB;
+	unsigned long ESW_NDISCN;
+	unsigned long ESW_NDISCB;/*0xFC0DC30C*/
+	struct esw_port_statistics_status port_statistics_status[3];
+	/*from 0x340-0x400*/
+	unsigned long esw_reserved8[48];
+
+	/*0xFC0DC400---0xFC0DC418*/
+	/*unsigned long MCF_ESW_ISR;*/
+	unsigned long   switch_ievent;             /* Interrupt event reg */
+	/*unsigned long MCF_ESW_IMR;*/
+	unsigned long   switch_imask;              /* Interrupt mask reg */
+	/*unsigned long MCF_ESW_RDSR;*/
+	unsigned long   fec_r_des_start;        /* Receive descriptor ring */
+	/*unsigned long MCF_ESW_TDSR;*/
+	unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
+	/*unsigned long MCF_ESW_MRBR;*/
+	unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
+	/*unsigned long MCF_ESW_RDAR;*/
+	unsigned long   fec_r_des_active;       /* Receive descriptor reg */
+	/*unsigned long MCF_ESW_TDAR;*/
+	unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
+	/*from 0x420-0x4FC*/
+	unsigned long esw_reserved9[57];
+
+	/*0xFC0DC500---0xFC0DC508*/
+	unsigned long ESW_LREC0;
+	unsigned long ESW_LREC1;
+	unsigned long ESW_LSR;
+};
+
+struct  AddrTable64bEntry {
+	unsigned int lo;  /* lower 32 bits */
+	unsigned int hi;  /* upper 32 bits */
+};
+
+struct  eswAddrTable_t {
+	struct AddrTable64bEntry  eswTable64bEntry[2048];
+};
+
+#define MCF_ESW_LOOKUP_MEM_OFFSET      0x4000
+#define ENET_SWI_PHYS_ADDR_OFFSET	0x8000
+#define MCF_ESW_PER	(0x08 / sizeof(unsigned long))
+#define MCF_ESW_DBCR	(0x14 / sizeof(unsigned long))
+#define MCF_ESW_IMR	(0x404 / sizeof(unsigned long))
+
+#define MCF_FEC_BASE_ADDR	(fep->enet_addr)
+#define MCF_FEC_EIR0		(0x04 / sizeof(unsigned long))
+#define MCF_FEC_EIR1		(0x4004 / sizeof(unsigned long))
+#define MCF_FEC_EIMR0		(0x08 / sizeof(unsigned long))
+#define MCF_FEC_EIMR1		(0x4008 / sizeof(unsigned long))
+#define MCF_FEC_MMFR0		(0x40 / sizeof(unsigned long))
+#define MCF_FEC_MMFR1		(0x4040 / sizeof(unsigned long))
+#define MCF_FEC_MSCR0		(0x44 / sizeof(unsigned long))
+#define MCF_FEC_MSCR1		(0x4044 / sizeof(unsigned long))
+
+#define MCF_FEC_RCR0		(0x84 / sizeof(unsigned long))
+#define MCF_FEC_RCR1		(0x4084 / sizeof(unsigned long))
+#define MCF_FEC_TCR0		(0xC4 / sizeof(unsigned long))
+#define MCF_FEC_TCR1		(0x40C4 / sizeof(unsigned long))
+#define MCF_FEC_ECR0		(0x24 / sizeof(unsigned long))
+#define MCF_FEC_ECR1		(0x4024 / sizeof(unsigned long))
+
+#define MCF_FEC_PALR0          (0xE4 / sizeof(unsigned long))
+#define MCF_FEC_PALR1          (0x40E4 / sizeof(unsigned long))
+#define MCF_FEC_PAUR0          (0xE8 / sizeof(unsigned long))
+#define MCF_FEC_PAUR1          (0x40E8 / sizeof(unsigned long))
+
+#define MCF_FEC_ERDSR0         (0x180 / sizeof(unsigned long))
+#define MCF_FEC_ERDSR1         (0x4180 / sizeof(unsigned long))
+#define MCF_FEC_ETDSR0         (0x184 / sizeof(unsigned long))
+#define MCF_FEC_ETDSR1         (0x4184 / sizeof(unsigned long))
+
+#define MCF_FEC_IAUR0          (0x118 / sizeof(unsigned long))
+#define MCF_FEC_IAUR1          (0x4118 / sizeof(unsigned long))
+#define MCF_FEC_IALR0          (0x11C / sizeof(unsigned long))
+#define MCF_FEC_IALR1          (0x411C / sizeof(unsigned long))
+
+#define MCF_FEC_GAUR0          (0x120 / sizeof(unsigned long))
+#define MCF_FEC_GAUR1          (0x4120 / sizeof(unsigned long))
+#define MCF_FEC_GALR0          (0x124 / sizeof(unsigned long))
+#define MCF_FEC_GALR1          (0x4124 / sizeof(unsigned long))
+
+#define MCF_FEC_EMRBR0         (0x188 / sizeof(unsigned long))
+#define MCF_FEC_EMRBR1         (0x4188 / sizeof(unsigned long))
+
+#define MCF_FEC_RCR_DRT	(0x00000002)
+#define MCF_FEC_RCR_PROM       (0x00000008)
+#define MCF_FEC_RCR_FCE	(0x00000020)
+#define MCF_FEC_RCR_RMII_MODE  (0x00000100)
+#define MCF_FEC_RCR_MAX_FL(x)  (((x)&0x00003FFF)<<16)
+#define MCF_FEC_RCR_CRC_FWD    (0x00004000)
+#define MCF_FEC_RCR_NO_LGTH_CHECK (0x40000000)
+#define MCF_FEC_TCR_FDEN       (0x00000004)
+
+#define MCF_FEC_ECR_RESET      (0x00000001)
+#define MCF_FEC_ECR_ETHER_EN   (0x00000002)
+#define MCF_FEC_ECR_MAGIC_ENA  (0x00000004)
+#define MCF_FEC_ECR_ENA_1588   (0x00000010)
+
+#define MCF_FEC_ERDSR(x)       ((x) << 2)
+
+/*-------------ioctl command ---------------------------------------*/
+#define ESW_SET_LEARNING_CONF               0x9101
+#define ESW_GET_LEARNING_CONF               0x9201
+#define ESW_SET_BLOCKING_CONF               0x9102
+#define ESW_GET_BLOCKING_CONF               0x9202
+#define ESW_SET_MULTICAST_CONF              0x9103
+#define ESW_GET_MULTICAST_CONF              0x9203
+#define ESW_SET_BROADCAST_CONF              0x9104
+#define ESW_GET_BROADCAST_CONF              0x9204
+#define ESW_SET_PORTENABLE_CONF             0x9105
+#define ESW_GET_PORTENABLE_CONF             0x9205
+#define ESW_SET_IP_SNOOP_CONF               0x9106
+#define ESW_GET_IP_SNOOP_CONF               0x9206
+#define ESW_SET_PORT_SNOOP_CONF             0x9107
+#define ESW_GET_PORT_SNOOP_CONF             0x9207
+#define ESW_SET_PORT_MIRROR_CONF            0x9108
+#define ESW_GET_PORT_MIRROR_CONF            0x9208
+#define ESW_SET_PIRORITY_VLAN               0x9109
+#define ESW_GET_PIRORITY_VLAN               0x9209
+#define ESW_SET_PIRORITY_IP                 0x910A
+#define ESW_GET_PIRORITY_IP                 0x920A
+#define ESW_SET_PIRORITY_MAC                0x910B
+#define ESW_GET_PIRORITY_MAC                0x920B
+#define ESW_SET_PIRORITY_DEFAULT            0x910C
+#define ESW_GET_PIRORITY_DEFAULT            0x920C
+#define ESW_SET_P0_FORCED_FORWARD           0x910D
+#define ESW_GET_P0_FORCED_FORWARD           0x920D
+#define ESW_SET_SWITCH_MODE                 0x910E
+#define ESW_GET_SWITCH_MODE                 0x920E
+#define ESW_SET_BRIDGE_CONFIG               0x910F
+#define ESW_GET_BRIDGE_CONFIG               0x920F
+#define ESW_SET_VLAN_OUTPUT_PROCESS         0x9110
+#define ESW_GET_VLAN_OUTPUT_PROCESS         0x9210
+#define ESW_SET_VLAN_INPUT_PROCESS          0x9111
+#define ESW_GET_VLAN_INPUT_PROCESS          0x9211
+#define ESW_SET_VLAN_DOMAIN_VERIFICATION    0x9112
+#define ESW_GET_VLAN_DOMAIN_VERIFICATION    0x9212
+#define ESW_SET_VLAN_RESOLUTION_TABLE       0x9113
+#define ESW_GET_VLAN_RESOLUTION_TABLE       0x9213
+
+
+#define ESW_GET_STATISTICS_STATUS           0x9221
+#define ESW_GET_PORT0_STATISTICS_STATUS     0x9222
+#define ESW_GET_PORT1_STATISTICS_STATUS     0x9223
+#define ESW_GET_PORT2_STATISTICS_STATUS     0x9224
+#define ESW_SET_OUTPUT_QUEUE_MEMORY         0x9125
+#define ESW_GET_OUTPUT_QUEUE_STATUS         0x9225
+#define ESW_UPDATE_STATIC_MACTABLE          0x9226
+#define ESW_CLEAR_ALL_MACTABLE              0x9227
+
+struct eswIoctlPortConfig {
+	int port;
+	int enable;
+};
+
+struct  eswIoctlPortEnableConfig {
+	int port;
+	int tx_enable;
+	int rx_enable;
+};
+
+struct  eswIoctlIpsnoopConfig {
+	int num;
+	int mode;
+	unsigned char ip_header_protocol;
+};
+
+struct eswIoctlP0ForcedForwardConfig {
+	int port1;
+	int port2;
+	int enable;
+};
+
+struct eswIoctlPortsnoopConfig {
+     int num;
+     int mode;
+     unsigned short compare_port;
+     int compare_num;
+};
+
+struct  eswIoctlPortMirrorConfig {
+	int mirror_port;
+	int port;
+	int egress_en;
+	int ingress_en;
+	int egress_mac_src_en;
+	int egress_mac_des_en;
+	int ingress_mac_src_en;
+	int ingress_mac_des_en;
+	unsigned char *src_mac;
+	unsigned char *des_mac;
+	int mirror_enable;
+};
+
+struct  eswIoctlPriorityVlanConfig {
+	int port;
+	int func_enable;
+	int vlan_pri_table_num;
+	int vlan_pri_table_value;
+};
+
+struct eswIoctlPriorityIPConfig {
+	int port;
+	int func_enable;
+	int ipv4_en;
+	int ip_priority_num;
+	int ip_priority_value;
+};
+
+struct  eswIoctlPriorityMacConfig {
+	int port;
+};
+
+struct  eswIoctlPriorityDefaultConfig{
+	int port;
+	unsigned char priority_value;
+};
+
+struct eswIoctlIrqStatus {
+	unsigned long isr;
+	unsigned long imr;
+	unsigned long rx_buf_pointer;
+	unsigned long tx_buf_pointer;
+	unsigned long rx_max_size;
+	unsigned long rx_buf_active;
+	unsigned long tx_buf_active;
+};
+
+struct eswIoctlPortMirrorStatus {
+	unsigned long ESW_MCR;
+	unsigned long ESW_EGMAP;
+	unsigned long ESW_INGMAP;
+	unsigned long ESW_INGSAL;
+	unsigned long ESW_INGSAH;
+	unsigned long ESW_INGDAL;
+	unsigned long ESW_INGDAH;
+	unsigned long ESW_ENGSAL;
+	unsigned long ESW_ENGSAH;
+	unsigned long ESW_ENGDAL;
+	unsigned long ESW_ENGDAH;
+	unsigned long ESW_MCVAL;
+};
+
+struct eswIoctlVlanOutputConfig {
+	int port;
+	int mode;
+};
+
+struct eswIoctlVlanInputConfig {
+	int port;
+	int mode;
+	unsigned short port_vlanid;
+	int vlan_verify_en;
+	int vlan_domain_num;
+	int vlan_domain_port;
+};
+
+struct eswIoctlVlanVerificationConfig {
+	int port;
+	int vlan_domain_verify_en;
+	int vlan_discard_unknown_en;
+};
+
+struct eswIoctlVlanResoultionTable {
+	unsigned short port_vlanid;
+	int vlan_domain_num;
+	int vlan_domain_port;
+};
+
+struct eswIoctlVlanInputStatus {
+	unsigned long ESW_VLANV;
+	unsigned long ESW_PID[3];
+	unsigned long ESW_VIMSEL;
+	unsigned long ESW_VIMEN;
+	unsigned long ESW_VRES[32];
+};
+
+struct eswIoctlUpdateStaticMACtable {
+	unsigned char *mac_addr;
+	int port;
+	int priority;
+};
+
+struct eswIoctlOutputQueue {
+	int fun_num;
+	struct esw_output_queue_status  sOutputQueue;
+};
+
+/*=============================================================*/
+#define LEARNING_AGING_TIMER (10 * HZ)
+/*
+ * Info received from Hardware Learning FIFO,
+ * holding MAC address and corresponding Hash Value and
+ * port number where the frame was received (disassembled).
+ */
+struct eswPortInfo {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int   maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int   machi;
+	/* the hash value for this MAC address. */
+	unsigned int   hash;
+	/* the port number this MAC address is associated with. */
+	unsigned int   port;
+};
+
+/*
+ * Hardware Look up Address Table 64-bit element.
+ */
+struct eswTable64bitEntry {
+	unsigned int lo;  /* lower 32 bits */
+	unsigned int hi;  /* upper 32 bits */
+};
+
+/*
+ * Disassembled element stored in Address Table.
+ */
+struct eswAddrTableDynamicEntry {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int machi;
+	/* timestamp of this entry */
+	unsigned int timestamp;
+	/* the port number this MAC address is associated with */
+	unsigned int port;
+};
+
+struct eswAddrTableStaticEntry {
+	/* MAC lower 32 bits (first byte is 7:0). */
+	unsigned int maclo;
+	/* MAC upper 16 bits (47:32). */
+	unsigned int machi;
+	/* priority of this entry */
+	unsigned int priority;
+	/* the port bitmask this MAC address is associated with */
+	unsigned int portbitmask;
+};
+/*
+ *	Define the buffer descriptor structure.
+ */
+struct cbd_t {
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS)
+	unsigned short	cbd_datlen;		/* Data length */
+	unsigned short	cbd_sc;			/* Control and status info */
+#else
+	unsigned short	cbd_sc;			/* Control and status info */
+	unsigned short	cbd_datlen;		/* Data length */
+#endif
+	unsigned long	cbd_bufaddr;		/* Buffer address */
+#ifdef L2SWITCH_ENHANCED_BUFFER
+	unsigned long   ebd_status;
+	unsigned short  length_proto_type;
+	unsigned short  payload_checksum;
+	unsigned long   bdu;
+	unsigned long   timestamp;
+	unsigned long   reserverd_word1;
+	unsigned long   reserverd_word2;
+#endif
+};
+
+/* Forward declarations of some structures to support different PHYs
+ */
+struct phy_cmd_t {
+	uint mii_data;
+	void (*funct)(uint mii_reg, struct net_device *dev);
+};
+
+struct  phy_info_t {
+	uint id;
+	char *name;
+
+	const struct phy_cmd_t *config;
+	const struct phy_cmd_t *startup;
+	const struct phy_cmd_t *ack_int;
+	const struct phy_cmd_t *shutdown;
+};
+
+/* The switch buffer descriptors track the ring buffers.  The rx_bd_base and
+ * tx_bd_base always point to the base of the buffer descriptors.  The
+ * cur_rx and cur_tx point to the currently available buffer.
+ * The dirty_tx tracks the current buffer that is being sent by the
+ * controller.  The cur_tx and dirty_tx are equal under both completely
+ * empty and completely full conditions.  The empty/ready indicator in
+ * the buffer descriptor determines the actual condition.
+ */
+struct switch_enet_private {
+	/* Hardware registers of the switch device */
+	struct switch_t  *hwp;
+	struct eswAddrTable_t  *hwentry;
+	unsigned long *enet_addr;
+
+	struct net_device *netdev;
+	struct platform_device *pdev;
+	struct clk *clk;
+	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
+	unsigned char *tx_bounce[TX_RING_SIZE];
+	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
+	struct  sk_buff *rx_skbuff[RX_RING_SIZE];
+	ushort  skb_cur;
+	ushort  skb_dirty;
+
+	/* CPM dual port RAM relative addresses */
+	dma_addr_t      bd_dma;
+	struct cbd_t   *rx_bd_base;	/* Address of Rx and Tx buffers. */
+	struct cbd_t   *tx_bd_base;
+	struct cbd_t   *cur_rx, *cur_tx;	/* The next free ring entry */
+	struct cbd_t   *dirty_tx;      /* The ring entries to be free()ed. */
+	uint    tx_full;
+	/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
+	spinlock_t hw_lock;
+
+	/* hold while accessing the mii_list_t() elements */
+	spinlock_t mii_lock;
+	struct mii_bus *mdio_bus;
+	struct phy_device *phydev;
+	phy_interface_t phy_interface;
+
+	uint    phy_id;
+	uint    phy_id_done;
+	uint    phy_status;
+	struct	phy_info_t const        *phy;
+	struct work_struct phy_task;
+	struct switch_t  *phy_hwp;
+
+	uint    sequence_done;
+	uint    mii_phy_task_queued;
+
+	uint    phy_addr;
+
+	int     opened;
+	int     old_link;
+	int     duplex;
+	int     speed;
+	int     msg_enable;
+
+	/* --------------Statistics--------------------------- */
+	/* when a new element deleted a element with in
+	 * a block due to lack of space */
+	int atBlockOverflows;
+	/* Peak number of valid entries in the address table */
+	int atMaxEntries;
+	/* current number of valid entries in the address table */
+	int atCurrEntries;
+	/* maximum entries within a block found
+	 * (updated within ageing)*/
+	int atMaxEntriesPerBlock;
+
+	/* -------------------ageing function------------------ */
+	/* maximum age allowed for an entry */
+	int ageMax;
+	/* last LUT entry to block that was
+	 * inspected by the Ageing task*/
+	int ageLutIdx;
+	/* last element within block inspected by the Ageing task */
+	int ageBlockElemIdx;
+	/* complete table has been processed by ageing process */
+	int ageCompleted;
+	/* delay setting */
+	int ageDelay;
+	/* current delay Counter */
+	int  ageDelayCnt;
+
+	/* ----------------timer related---------------------------- */
+	/* current time (for timestamping) */
+	int currTime;
+	/* flag set by timer when currTime changed
+	 * and cleared by serving function*/
+	int timeChanged;
+
+	/**/
+	/* Timer for Aging */
+	struct timer_list       timer_aging;
+	int learning_irqhandle_enable;
+	/* Phylib and MDIO interface */
+	struct  mii_bus *mii_bus;
+	struct  phy_device *phy_dev;
+	int     mii_timeout;
+	uint    phy_speed;
+	int     index;
+	int     link;
+	int     full_duplex;
+};
+
+struct switch_platform_private {
+	struct platform_device  *pdev;
+
+	unsigned long           quirks;
+	int                     num_slots;      /* Slots on controller */
+	struct switch_enet_private *fep_host[0];      /* Pointers to hosts */
+};
+
+/******************************************************************************/
+#define FEC_IEVENT		0x004 /* Interrupt event reg */
+#define FEC_IMASK		0x008 /* Interrupt mask reg */
+#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
+#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
+#define FEC_ECNTRL		0x024 /* Ethernet control reg */
+#define FEC_MII_DATA		0x040 /* MII manage frame reg */
+#define FEC_MII_SPEED		0x044 /* MII speed control reg */
+#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
+#define FEC_R_CNTRL		0x084 /* Receive control reg */
+#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
+#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
+#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
+#define FEC_OPD			0x0ec /* Opcode + Pause duration */
+#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
+#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
+#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
+#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
+#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
+#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
+#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
+#define FEC_R_DES_START		0x180 /* Receive descriptor ring */
+#define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
+#define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
+#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK config register */
+#define FEC_MIIGSK_ENR		0x308 /* MIIGSK enable register */
+
+/* Recieve is empty */
+#define BD_SC_EMPTY     ((unsigned short)0x8000)
+/* Transmit is ready */
+#define BD_SC_READY     ((unsigned short)0x8000)
+/* Last buffer descriptor */
+#define BD_SC_WRAP      ((unsigned short)0x2000)
+/* Interrupt on change */
+#define BD_SC_INTRPT    ((unsigned short)0x1000)
+/* Continous mode */
+#define BD_SC_CM        ((unsigned short)0x0200)
+/* Rec'd too many idles */
+#define BD_SC_ID        ((unsigned short)0x0100)
+/* xmt preamble */
+#define BD_SC_P         ((unsigned short)0x0100)
+/* Break received */
+#define BD_SC_BR        ((unsigned short)0x0020)
+/* Framing error */
+#define BD_SC_FR        ((unsigned short)0x0010)
+/* Parity error */
+#define BD_SC_PR        ((unsigned short)0x0008)
+/* Overrun */
+#define BD_SC_OV        ((unsigned short)0x0002)
+#define BD_SC_CD        ((unsigned short)0x0001)
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY        ((unsigned short)0x8000)
+#define BD_ENET_RX_WRAP         ((unsigned short)0x2000)
+#define BD_ENET_RX_INTR         ((unsigned short)0x1000)
+#define BD_ENET_RX_LAST         ((unsigned short)0x0800)
+#define BD_ENET_RX_FIRST        ((unsigned short)0x0400)
+#define BD_ENET_RX_MISS         ((unsigned short)0x0100)
+#define BD_ENET_RX_LG           ((unsigned short)0x0020)
+#define BD_ENET_RX_NO           ((unsigned short)0x0010)
+#define BD_ENET_RX_SH           ((unsigned short)0x0008)
+#define BD_ENET_RX_CR           ((unsigned short)0x0004)
+#define BD_ENET_RX_OV           ((unsigned short)0x0002)
+#define BD_ENET_RX_CL           ((unsigned short)0x0001)
+/* All status bits */
+#define BD_ENET_RX_STATS        ((unsigned short)0x013f)
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY        ((unsigned short)0x8000)
+#define BD_ENET_TX_PAD          ((unsigned short)0x4000)
+#define BD_ENET_TX_WRAP         ((unsigned short)0x2000)
+#define BD_ENET_TX_INTR         ((unsigned short)0x1000)
+#define BD_ENET_TX_LAST         ((unsigned short)0x0800)
+#define BD_ENET_TX_TC           ((unsigned short)0x0400)
+#define BD_ENET_TX_DEF          ((unsigned short)0x0200)
+#define BD_ENET_TX_HB           ((unsigned short)0x0100)
+#define BD_ENET_TX_LC           ((unsigned short)0x0080)
+#define BD_ENET_TX_RL           ((unsigned short)0x0040)
+#define BD_ENET_TX_RCMASK       ((unsigned short)0x003c)
+#define BD_ENET_TX_UN           ((unsigned short)0x0002)
+#define BD_ENET_TX_CSL          ((unsigned short)0x0001)
+/* All status bits */
+#define BD_ENET_TX_STATS        ((unsigned short)0x03ff)
+
+/*Copy from validation code */
+#define RX_BUFFER_SIZE 256
+#define TX_BUFFER_SIZE 256
+#define NUM_RXBDS 20
+#define NUM_TXBDS 20
+
+#define TX_BD_R                 0x8000
+#define TX_BD_TO1               0x4000
+#define TX_BD_W                 0x2000
+#define TX_BD_TO2               0x1000
+#define TX_BD_L                 0x0800
+#define TX_BD_TC                0x0400
+
+#define TX_BD_INT       0x40000000
+#define TX_BD_TS        0x20000000
+#define TX_BD_PINS      0x10000000
+#define TX_BD_IINS      0x08000000
+#define TX_BD_TXE       0x00008000
+#define TX_BD_UE        0x00002000
+#define TX_BD_EE        0x00001000
+#define TX_BD_FE        0x00000800
+#define TX_BD_LCE       0x00000400
+#define TX_BD_OE        0x00000200
+#define TX_BD_TSE       0x00000100
+#define TX_BD_BDU       0x80000000
+
+#define RX_BD_E                 0x8000
+#define RX_BD_R01               0x4000
+#define RX_BD_W                 0x2000
+#define RX_BD_R02               0x1000
+#define RX_BD_L                 0x0800
+#define RX_BD_M                 0x0100
+#define RX_BD_BC                0x0080
+#define RX_BD_MC                0x0040
+#define RX_BD_LG                0x0020
+#define RX_BD_NO                0x0010
+#define RX_BD_CR                0x0004
+#define RX_BD_OV                0x0002
+#define RX_BD_TR                0x0001
+
+#define RX_BD_ME               0x80000000
+#define RX_BD_PE               0x04000000
+#define RX_BD_CE               0x02000000
+#define RX_BD_UC               0x01000000
+#define RX_BD_INT              0x00800000
+#define RX_BD_ICE              0x00000020
+#define RX_BD_PCR              0x00000010
+#define RX_BD_VLAN             0x00000004
+#define RX_BD_IPV6             0x00000002
+#define RX_BD_FRAG             0x00000001
+#define RX_BD_BDU              0x80000000
+/****************************************************************************/
+
+/* Address Table size in bytes(2048 64bit entry ) */
+#define ESW_ATABLE_MEM_SIZE         (2048*8)
+/* How many 64-bit elements fit in the address table */
+#define ESW_ATABLE_MEM_NUM_ENTRIES  (2048)
+/* Address Table Maximum number of entries in each Slot */
+#define ATABLE_ENTRY_PER_SLOT 8
+/* log2(ATABLE_ENTRY_PER_SLOT)*/
+#define ATABLE_ENTRY_PER_SLOT_bits 3
+/* entry size in byte */
+#define ATABLE_ENTRY_SIZE     8
+/*  slot size in byte */
+#define ATABLE_SLOT_SIZE    (ATABLE_ENTRY_PER_SLOT * ATABLE_ENTRY_SIZE)
+/* width of timestamp variable (bits) within address table entry */
+#define AT_DENTRY_TIMESTAMP_WIDTH    10
+/* number of bits for port number storage */
+#define AT_DENTRY_PORT_WIDTH     4
+/* number of bits for port bitmask number storage */
+#define AT_SENTRY_PORT_WIDTH     11
+/* address table static entry port bitmask start address bit */
+#define AT_SENTRY_PORTMASK_shift     21
+/* address table static entry priority start address bit */
+#define AT_SENTRY_PRIO_shift     18
+/* address table dynamic entry port start address bit */
+#define AT_DENTRY_PORT_shift     28
+/* address table dynamic entry timestamp start address bit */
+#define AT_DENTRY_TIME_shift     18
+/* address table entry record type start address bit */
+#define AT_ENTRY_TYPE_shift     17
+/* address table entry record type bit: 1 static, 0 dynamic */
+#define AT_ENTRY_TYPE_STATIC      1
+#define AT_ENTRY_TYPE_DYNAMIC     0
+/* address table entry record valid start address bit */
+#define AT_ENTRY_VALID_shift     16
+#define AT_ENTRY_RECORD_VALID     1
+
+
+/* return block corresponding to the 8 bit hash value calculated */
+#define GET_BLOCK_PTR(hash)  (hash << 3)
+#define AT_EXTRACT_TIMESTAMP(x) \
+	((x >> AT_DENTRY_TIME_shift) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+#define AT_EXTRACT_PORT(x)   \
+	((x >> AT_DENTRY_PORT_shift) & ((1 << AT_DENTRY_PORT_WIDTH)-1))
+#define TIMEDELTA(newtime, oldtime) \
+	 ((newtime - oldtime) & \
+	  ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+/* increment time value respecting modulo. */
+#define TIMEINCREMENT(time) \
+	((time) = ((time)+1) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1))
+/* ------------------------------------------------------------------------- */
+/* Bit definitions and macros for MCF_ESW_REVISION */
+#define MCF_ESW_REVISION_CORE_REVISION(x)      (((x)&0x0000FFFF)<<0)
+#define MCF_ESW_REVISION_CUSTOMER_REVISION(x)  (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_PER */
+#define MCF_ESW_PER_TE0                        (0x00000001)
+#define MCF_ESW_PER_TE1                        (0x00000002)
+#define MCF_ESW_PER_TE2                        (0x00000004)
+#define MCF_ESW_PER_RE0                        (0x00010000)
+#define MCF_ESW_PER_RE1                        (0x00020000)
+#define MCF_ESW_PER_RE2                        (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_VLANV */
+#define MCF_ESW_VLANV_VV0                      (0x00000001)
+#define MCF_ESW_VLANV_VV1                      (0x00000002)
+#define MCF_ESW_VLANV_VV2                      (0x00000004)
+#define MCF_ESW_VLANV_DU0                      (0x00010000)
+#define MCF_ESW_VLANV_DU1                      (0x00020000)
+#define MCF_ESW_VLANV_DU2                      (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_DBCR */
+#define MCF_ESW_DBCR_P0                        (0x00000001)
+#define MCF_ESW_DBCR_P1                        (0x00000002)
+#define MCF_ESW_DBCR_P2                        (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_DMCR */
+#define MCF_ESW_DMCR_P0                        (0x00000001)
+#define MCF_ESW_DMCR_P1                        (0x00000002)
+#define MCF_ESW_DMCR_P2                        (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_BKLR */
+#define MCF_ESW_BKLR_BE0                       (0x00000001)
+#define MCF_ESW_BKLR_BE1                       (0x00000002)
+#define MCF_ESW_BKLR_BE2                       (0x00000004)
+#define MCF_ESW_BKLR_LD0                       (0x00010000)
+#define MCF_ESW_BKLR_LD1                       (0x00020000)
+#define MCF_ESW_BKLR_LD2                       (0x00040000)
+
+/* Bit definitions and macros for MCF_ESW_BMPC */
+#define MCF_ESW_BMPC_PORT(x)                   (((x)&0x0000000F)<<0)
+#define MCF_ESW_BMPC_MSG_TX                    (0x00000020)
+#define MCF_ESW_BMPC_EN                        (0x00000040)
+#define MCF_ESW_BMPC_DIS                       (0x00000080)
+#define MCF_ESW_BMPC_PRIORITY(x)               (((x)&0x00000007)<<13)
+#define MCF_ESW_BMPC_PORTMASK(x)               (((x)&0x00000007)<<16)
+
+/* Bit definitions and macros for MCF_ESW_MODE */
+#define MCF_ESW_MODE_SW_RST                    (0x00000001)
+#define MCF_ESW_MODE_SW_EN                     (0x00000002)
+#define MCF_ESW_MODE_STOP                      (0x00000080)
+#define MCF_ESW_MODE_CRC_TRAN                  (0x00000100)
+#define MCF_ESW_MODE_P0CT                      (0x00000200)
+#define MCF_ESW_MODE_STATRST                   (0x80000000)
+
+/* Bit definitions and macros for MCF_ESW_VIMSEL */
+#define MCF_ESW_VIMSEL_IM0(x)                  (((x)&0x00000003)<<0)
+#define MCF_ESW_VIMSEL_IM1(x)                  (((x)&0x00000003)<<2)
+#define MCF_ESW_VIMSEL_IM2(x)                  (((x)&0x00000003)<<4)
+
+/* Bit definitions and macros for MCF_ESW_VOMSEL */
+#define MCF_ESW_VOMSEL_OM0(x)                  (((x)&0x00000003)<<0)
+#define MCF_ESW_VOMSEL_OM1(x)                  (((x)&0x00000003)<<2)
+#define MCF_ESW_VOMSEL_OM2(x)                  (((x)&0x00000003)<<4)
+
+/* Bit definitions and macros for MCF_ESW_VIMEN */
+#define MCF_ESW_VIMEN_EN0                      (0x00000001)
+#define MCF_ESW_VIMEN_EN1                      (0x00000002)
+#define MCF_ESW_VIMEN_EN2                      (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_VID */
+#define MCF_ESW_VID_TAG(x)                     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MCR */
+#define MCF_ESW_MCR_PORT(x)                    (((x)&0x0000000F)<<0)
+#define MCF_ESW_MCR_MEN                        (0x00000010)
+#define MCF_ESW_MCR_INGMAP                     (0x00000020)
+#define MCF_ESW_MCR_EGMAP                      (0x00000040)
+#define MCF_ESW_MCR_INGSA                      (0x00000080)
+#define MCF_ESW_MCR_INGDA                      (0x00000100)
+#define MCF_ESW_MCR_EGSA                       (0x00000200)
+#define MCF_ESW_MCR_EGDA                       (0x00000400)
+
+/* Bit definitions and macros for MCF_ESW_EGMAP */
+#define MCF_ESW_EGMAP_EG0                      (0x00000001)
+#define MCF_ESW_EGMAP_EG1                      (0x00000002)
+#define MCF_ESW_EGMAP_EG2                      (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_INGMAP */
+#define MCF_ESW_INGMAP_ING0                    (0x00000001)
+#define MCF_ESW_INGMAP_ING1                    (0x00000002)
+#define MCF_ESW_INGMAP_ING2                    (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_INGSAL */
+#define MCF_ESW_INGSAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGSAH */
+#define MCF_ESW_INGSAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGDAL */
+#define MCF_ESW_INGDAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_INGDAH */
+#define MCF_ESW_INGDAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGSAL */
+#define MCF_ESW_ENGSAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGSAH */
+#define MCF_ESW_ENGSAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGDAL */
+#define MCF_ESW_ENGDAL_ADDLOW(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ENGDAH */
+#define MCF_ESW_ENGDAH_ADDHIGH(x)              (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MCVAL */
+#define MCF_ESW_MCVAL_COUNT(x)                 (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_MMSR */
+#define MCF_ESW_MMSR_BUSY                      (0x00000001)
+#define MCF_ESW_MMSR_NOCELL                    (0x00000002)
+#define MCF_ESW_MMSR_MEMFULL                   (0x00000004)
+#define MCF_ESW_MMSR_MFLATCH                   (0x00000008)
+#define MCF_ESW_MMSR_DQ_GRNT                   (0x00000040)
+#define MCF_ESW_MMSR_CELLS_AVAIL(x)            (((x)&0x000000FF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_LMT */
+#define MCF_ESW_LMT_THRESH(x)                  (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_LFC */
+#define MCF_ESW_LFC_COUNT(x)                   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PCSR */
+#define MCF_ESW_PCSR_PC0                       (0x00000001)
+#define MCF_ESW_PCSR_PC1                       (0x00000002)
+#define MCF_ESW_PCSR_PC2                       (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_IOSR */
+#define MCF_ESW_IOSR_OR0                       (0x00000001)
+#define MCF_ESW_IOSR_OR1                       (0x00000002)
+#define MCF_ESW_IOSR_OR2                       (0x00000004)
+
+/* Bit definitions and macros for MCF_ESW_QWT */
+#define MCF_ESW_QWT_Q0WT(x)                    (((x)&0x0000001F)<<0)
+#define MCF_ESW_QWT_Q1WT(x)                    (((x)&0x0000001F)<<8)
+#define MCF_ESW_QWT_Q2WT(x)                    (((x)&0x0000001F)<<16)
+#define MCF_ESW_QWT_Q3WT(x)                    (((x)&0x0000001F)<<24)
+
+/* Bit definitions and macros for MCF_ESW_P0BCT */
+#define MCF_ESW_P0BCT_THRESH(x)                (((x)&0x000000FF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_P0FFEN */
+#define MCF_ESW_P0FFEN_FEN                     (0x00000001)
+#define MCF_ESW_P0FFEN_FD(x)                   (((x)&0x00000003)<<2)
+
+/* Bit definitions and macros for MCF_ESW_PSNP */
+#define MCF_ESW_PSNP_EN                        (0x00000001)
+#define MCF_ESW_PSNP_MODE(x)                   (((x)&0x00000003)<<1)
+#define MCF_ESW_PSNP_CD                        (0x00000008)
+#define MCF_ESW_PSNP_CS                        (0x00000010)
+#define MCF_ESW_PSNP_PORT_COMPARE(x)           (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_ESW_IPSNP */
+#define MCF_ESW_IPSNP_EN                       (0x00000001)
+#define MCF_ESW_IPSNP_MODE(x)                  (((x)&0x00000003)<<1)
+#define MCF_ESW_IPSNP_PROTOCOL(x)              (((x)&0x000000FF)<<8)
+
+/* Bit definitions and macros for MCF_ESW_PVRES */
+#define MCF_ESW_PVRES_PRI0(x)                  (((x)&0x00000007)<<0)
+#define MCF_ESW_PVRES_PRI1(x)                  (((x)&0x00000007)<<3)
+#define MCF_ESW_PVRES_PRI2(x)                  (((x)&0x00000007)<<6)
+#define MCF_ESW_PVRES_PRI3(x)                  (((x)&0x00000007)<<9)
+#define MCF_ESW_PVRES_PRI4(x)                  (((x)&0x00000007)<<12)
+#define MCF_ESW_PVRES_PRI5(x)                  (((x)&0x00000007)<<15)
+#define MCF_ESW_PVRES_PRI6(x)                  (((x)&0x00000007)<<18)
+#define MCF_ESW_PVRES_PRI7(x)                  (((x)&0x00000007)<<21)
+
+/* Bit definitions and macros for MCF_ESW_IPRES */
+#define MCF_ESW_IPRES_ADDRESS(x)               (((x)&0x000000FF)<<0)
+#define MCF_ESW_IPRES_IPV4SEL                  (0x00000100)
+#define MCF_ESW_IPRES_PRI0(x)                  (((x)&0x00000003)<<9)
+#define MCF_ESW_IPRES_PRI1(x)                  (((x)&0x00000003)<<11)
+#define MCF_ESW_IPRES_PRI2(x)                   (((x)&0x00000003)<<13)
+#define MCF_ESW_IPRES_READ                     (0x80000000)
+
+/* Bit definitions and macros for MCF_ESW_PRES */
+#define MCF_ESW_PRES_VLAN                      (0x00000001)
+#define MCF_ESW_PRES_IP                        (0x00000002)
+#define MCF_ESW_PRES_MAC                       (0x00000004)
+#define MCF_ESW_PRES_DFLT_PRI(x)               (((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for MCF_ESW_PID */
+#define MCF_ESW_PID_VLANID(x)                  (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_VRES */
+#define MCF_ESW_VRES_P0                        (0x00000001)
+#define MCF_ESW_VRES_P1                        (0x00000002)
+#define MCF_ESW_VRES_P2                        (0x00000004)
+#define MCF_ESW_VRES_VLANID(x)                 (((x)&0x00000FFF)<<3)
+
+/* Bit definitions and macros for MCF_ESW_DISCN */
+#define MCF_ESW_DISCN_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_DISCB */
+#define MCF_ESW_DISCB_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_NDISCN */
+#define MCF_ESW_NDISCN_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_NDISCB */
+#define MCF_ESW_NDISCB_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_POQC */
+#define MCF_ESW_POQC_COUNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PMVID */
+#define MCF_ESW_PMVID_COUNT(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PMVTAG */
+#define MCF_ESW_PMVTAG_COUNT(x)                (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_PBL */
+#define MCF_ESW_PBL_COUNT(x)                   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_ISR */
+#define MCF_ESW_ISR_EBERR                      (0x00000001)
+#define MCF_ESW_ISR_RXB                        (0x00000002)
+#define MCF_ESW_ISR_RXF                        (0x00000004)
+#define MCF_ESW_ISR_TXB                        (0x00000008)
+#define MCF_ESW_ISR_TXF                        (0x00000010)
+#define MCF_ESW_ISR_QM                         (0x00000020)
+#define MCF_ESW_ISR_OD0                        (0x00000040)
+#define MCF_ESW_ISR_OD1                        (0x00000080)
+#define MCF_ESW_ISR_OD2                        (0x00000100)
+#define MCF_ESW_ISR_LRN                        (0x00000200)
+
+/* Bit definitions and macros for MCF_ESW_IMR */
+#define MCF_ESW_IMR_EBERR                      (0x00000001)
+#define MCF_ESW_IMR_RXB                        (0x00000002)
+#define MCF_ESW_IMR_RXF                        (0x00000004)
+#define MCF_ESW_IMR_TXB                        (0x00000008)
+#define MCF_ESW_IMR_TXF                        (0x00000010)
+#define MCF_ESW_IMR_QM                         (0x00000020)
+#define MCF_ESW_IMR_OD0                        (0x00000040)
+#define MCF_ESW_IMR_OD1                        (0x00000080)
+#define MCF_ESW_IMR_OD2                        (0x00000100)
+#define MCF_ESW_IMR_LRN                        (0x00000200)
+
+/* Bit definitions and macros for MCF_ESW_RDSR */
+#define MCF_ESW_RDSR_ADDRESS(x)                (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_ESW_TDSR */
+#define MCF_ESW_TDSR_ADDRESS(x)                (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_ESW_MRBR */
+#define MCF_ESW_MRBR_SIZE(x)                   (((x)&0x000003FF)<<4)
+
+/* Bit definitions and macros for MCF_ESW_RDAR */
+#define MCF_ESW_RDAR_R_DES_ACTIVE              (0x01000000)
+
+/* Bit definitions and macros for MCF_ESW_TDAR */
+#define MCF_ESW_TDAR_X_DES_ACTIVE              (0x01000000)
+
+/* Bit definitions and macros for MCF_ESW_LREC0 */
+#define MCF_ESW_LREC0_MACADDR0(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ESW_LREC1 */
+#define MCF_ESW_LREC1_MACADDR1(x)              (((x)&0x0000FFFF)<<0)
+#define MCF_ESW_LREC1_HASH(x)                  (((x)&0x000000FF)<<16)
+#define MCF_ESW_LREC1_SWPORT(x)                (((x)&0x00000003)<<24)
+
+/* Bit definitions and macros for MCF_ESW_LSR */
+#define MCF_ESW_LSR_DA                         (0x00000001)
+
+#endif /* SWITCH_H */
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index f76384221422..06151f87dacd 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -387,5 +387,9 @@ config MCS_FIR
 	  To compile it as a module, choose M here: the module will be called
 	  mcs7780.
 
+config MXC_FIR
+	tristate "Freescale MXC FIR driver"
+	depends on ARCH_MXC && IRDA
+
 endmenu
 
diff --git a/drivers/net/irda/Makefile b/drivers/net/irda/Makefile
index d82e1e3bd8c8..a54dcdeb3861 100644
--- a/drivers/net/irda/Makefile
+++ b/drivers/net/irda/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_VLSI_FIR)		+= vlsi_ir.o
 obj-$(CONFIG_VIA_FIR)		+= via-ircc.o
 obj-$(CONFIG_PXA_FICP)	        += pxaficp_ir.o
 obj-$(CONFIG_MCS_FIR)	        += mcs7780.o
+obj-$(CONFIG_MXC_FIR)	        += mxc_ir.o
 obj-$(CONFIG_AU1000_FIR)	+= au1k_ir.o
 # SIR drivers
 obj-$(CONFIG_IRTTY_SIR)		+= irtty-sir.o	sir-dev.o
diff --git a/drivers/net/irda/mxc_ir.c b/drivers/net/irda/mxc_ir.c
new file mode 100644
index 000000000000..fd5052f3a0ab
--- /dev/null
+++ b/drivers/net/irda/mxc_ir.c
@@ -0,0 +1,1781 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * Based on sa1100_ir.c - Copyright 2000-2001 Russell King
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_ir.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC FIRI.
+ *
+ * This driver is based on drivers/net/irda/sa1100_ir.c, by Russell King.
+ *
+ * @ingroup FIRI
+ */
+
+/*
+ * Include Files
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include <net/irda/irda.h>
+#include <net/irda/wrapper.h>
+#include <net/irda/irda_device.h>
+
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <mach/hardware.h>
+#include <mach/mxc_uart.h>
+#include "mxc_ir.h"
+
+#define IS_SIR(mi)		( (mi)->speed <= 115200 )
+#define IS_MIR(mi)		( (mi)->speed < 4000000 && (mi)->speed >= 576000 )
+#define IS_FIR(mi)		( (mi)->speed >= 4000000 )
+
+#define SDMA_START_DELAY()	{  \
+				volatile int j,k;\
+				int i;\
+				for(i=0;i<10000;i++)\
+				k=j;\
+				}
+
+#define IRDA_FRAME_SIZE_LIMIT   2047
+#define UART_BUFF_SIZE 		14384
+
+#define UART4_UFCR_TXTL  	16
+#define UART4_UFCR_RXTL 	1
+
+#define FIRI_SDMA_TX
+#define FIRI_SDMA_RX
+
+/*!
+ * This structure is a way for the low level driver to define their own
+ * \b mxc_irda structure. This structure includes SK buffers, DMA buffers.
+ * and has other elements that are specifically required by this driver.
+ */
+struct mxc_irda {
+	/*!
+	 * This keeps track of device is running or not
+	 */
+	unsigned char open;
+
+	/*!
+	 * This holds current FIRI communication speed
+	 */
+	int speed;
+
+	/*!
+	 * This holds FIRI communication speed for next packet
+	 */
+	int newspeed;
+
+	/*!
+	 * SK buffer for transmitter
+	 */
+	struct sk_buff *txskb;
+
+	/*!
+	 * SK buffer for receiver
+	 */
+	struct sk_buff *rxskb;
+
+#ifdef FIRI_SDMA_RX
+	/*!
+	 * SK buffer for tasklet
+	 */
+	struct sk_buff *tskb;
+#endif
+
+	/*!
+	 * DMA address for transmitter
+	 */
+	dma_addr_t dma_rx_buff_phy;
+
+	/*!
+	 * DMA address for receiver
+	 */
+	dma_addr_t dma_tx_buff_phy;
+
+	/*!
+	 * DMA Transmit buffer length
+	 */
+	unsigned int dma_tx_buff_len;
+
+	/*!
+	 * DMA channel for transmitter
+	 */
+	int txdma_ch;
+
+	/*!
+	 * DMA channel for receiver
+	 */
+	int rxdma_ch;
+
+	/*!
+	 * IrDA network device statistics
+	 */
+	struct net_device_stats stats;
+
+	/*!
+	 * The device structure used to get FIRI information
+	 */
+	struct device *dev;
+
+	/*!
+	 * Resource structure for UART, which will maintain base addresses and IRQs.
+	 */
+	struct resource *uart_res;
+
+	/*!
+	 * Base address of UART, used in readl and writel.
+	 */
+	void *uart_base;
+
+	/*!
+	 * Resource structure for FIRI, which will maintain base addresses and IRQs.
+	 */
+	struct resource *firi_res;
+
+	/*!
+	 * Base address of FIRI, used in readl and writel.
+	 */
+	void *firi_base;
+
+	/*!
+	 * UART IRQ number.
+	 */
+	int uart_irq;
+
+	/*!
+	 * Second UART IRQ number in case the interrupt lines are not muxed.
+	 */
+	int uart_irq1;
+
+	/*!
+	 * UART clock needed for baud rate calculations
+	 */
+	struct clk *uart_clk;
+
+	/*!
+	 * UART clock needed for baud rate calculations
+	 */
+	unsigned long uart_clk_rate;
+
+	/*!
+	 * FIRI clock needed for baud rate calculations
+	 */
+	struct clk *firi_clk;
+
+	/*!
+	 * FIRI IRQ number.
+	 */
+	int firi_irq;
+
+	/*!
+	 * IrLAP layer instance
+	 */
+	struct irlap_cb *irlap;
+
+	/*!
+	 * Driver supported baudrate capabilities
+	 */
+	struct qos_info qos;
+
+	/*!
+	 * Temporary transmit buffer used by the driver
+	 */
+	iobuff_t tx_buff;
+
+	/*!
+	 * Temporary receive buffer used by the driver
+	 */
+	iobuff_t rx_buff;
+
+	/*!
+	 * Pointer to platform specific data structure.
+	 */
+	struct mxc_ir_platform_data *mxc_ir_plat;
+
+	/*!
+	 * This holds the power management status of this module.
+	 */
+	int suspend;
+
+};
+
+extern void gpio_firi_active(void *, unsigned int);
+extern void gpio_firi_inactive(void);
+extern void gpio_firi_init(void);
+
+void mxc_irda_firi_init(struct mxc_irda *si);
+#ifdef FIRI_SDMA_RX
+static void mxc_irda_fir_dma_rx_irq(void *id, int error_status,
+				    unsigned int count);
+#endif
+#ifdef FIRI_SDMA_TX
+static void mxc_irda_fir_dma_tx_irq(void *id, int error_status,
+				    unsigned int count);
+#endif
+
+/*!
+ * This function allocates and maps the receive buffer,
+ * unless it is already allocated.
+ *
+ * @param   si   FIRI device specific structure.
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_rx_alloc(struct mxc_irda *si)
+{
+#ifdef FIRI_SDMA_RX
+	mxc_dma_requestbuf_t dma_request;
+#endif
+	if (si->rxskb) {
+		return 0;
+	}
+
+	si->rxskb = alloc_skb(IRDA_FRAME_SIZE_LIMIT + 1, GFP_ATOMIC);
+
+	if (!si->rxskb) {
+		dev_err(si->dev, "mxc_ir: out of memory for RX SKB\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Align any IP headers that may be contained
+	 * within the frame.
+	 */
+	skb_reserve(si->rxskb, 1);
+
+#ifdef FIRI_SDMA_RX
+	si->dma_rx_buff_phy =
+	    dma_map_single(si->dev, si->rxskb->data, IRDA_FRAME_SIZE_LIMIT,
+			   DMA_FROM_DEVICE);
+
+	dma_request.num_of_bytes = IRDA_FRAME_SIZE_LIMIT;
+	dma_request.dst_addr = si->dma_rx_buff_phy;
+	dma_request.src_addr = si->firi_res->start;
+
+	mxc_dma_config(si->rxdma_ch, &dma_request, 1, MXC_DMA_MODE_READ);
+#endif
+	return 0;
+}
+
+/*!
+ * This function is called to disable the FIRI dma
+ *
+ * @param   si  FIRI port specific structure.
+ */
+static void mxc_irda_disabledma(struct mxc_irda *si)
+{
+	/* Stop all DMA activity. */
+#ifdef FIRI_SDMA_TX
+	mxc_dma_disable(si->txdma_ch);
+#endif
+#ifdef FIRI_SDMA_RX
+	mxc_dma_disable(si->rxdma_ch);
+#endif
+}
+
+/*!
+ * This function is called to set the IrDA communications speed.
+ *
+ * @param   si     FIRI specific structure.
+ * @param   speed  new Speed to be configured for.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_set_speed(struct mxc_irda *si, int speed)
+{
+	unsigned long flags;
+	int ret = 0;
+	unsigned int num, denom, baud;
+	unsigned int cr;
+
+	dev_dbg(si->dev, "speed:%d\n", speed);
+	switch (speed) {
+	case 9600:
+	case 19200:
+	case 38400:
+	case 57600:
+	case 115200:
+		dev_dbg(si->dev, "starting SIR\n");
+		baud = speed;
+		if (IS_FIR(si)) {
+#ifdef FIRI_SDMA_RX
+			mxc_dma_disable(si->rxdma_ch);
+#endif
+			cr = readl(si->firi_base + FIRITCR);
+			cr &= ~FIRITCR_TE;
+			writel(cr, si->firi_base + FIRITCR);
+
+			cr = readl(si->firi_base + FIRIRCR);
+			cr &= ~FIRIRCR_RE;
+			writel(cr, si->firi_base + FIRIRCR);
+
+		}
+		local_irq_save(flags);
+
+		/* Disable Tx and Rx */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		gpio_firi_inactive();
+
+		num = baud / 100 - 1;
+		denom = si->uart_clk_rate / 1600 - 1;
+		if ((denom < 65536) && (si->uart_clk_rate > 1600)) {
+			writel(num, si->uart_base + MXC_UARTUBIR);
+			writel(denom, si->uart_base + MXC_UARTUBMR);
+		}
+
+		si->speed = speed;
+
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+
+		/* Enable Receive Overrun and Data Ready interrupts. */
+		cr = readl(si->uart_base + MXC_UARTUCR4);
+		cr |= (MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN);
+		writel(cr, si->uart_base + MXC_UARTUCR4);
+
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr |= (MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		local_irq_restore(flags);
+		break;
+	case 4000000:
+		local_irq_save(flags);
+
+		/* Disable Receive Overrun and Data Ready interrupts. */
+		cr = readl(si->uart_base + MXC_UARTUCR4);
+		cr &= ~(MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN);
+		writel(cr, si->uart_base + MXC_UARTUCR4);
+
+		/* Disable Tx and Rx */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		/*
+		 * FIR configuration
+		 */
+		mxc_irda_disabledma(si);
+
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+
+		gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP);
+
+		si->speed = speed;
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr |= FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		dev_dbg(si->dev, "Going for fast IRDA ...\n");
+		ret = mxc_irda_rx_alloc(si);
+
+		/* clear RX status register */
+		writel(0xFFFF, si->firi_base + FIRIRSR);
+#ifdef FIRI_SDMA_RX
+		if (si->rxskb) {
+			mxc_dma_enable(si->rxdma_ch);
+		}
+#endif
+		local_irq_restore(flags);
+
+		break;
+	default:
+		dev_err(si->dev, "speed not supported by FIRI\n");
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function is called to set the IrDA communications speed.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static inline int mxc_irda_fir_error(struct mxc_irda *si)
+{
+	struct sk_buff *skb = si->rxskb;
+	unsigned int dd_error, crc_error, overrun_error;
+	unsigned int sr;
+
+	if (!skb) {
+		dev_err(si->dev, "no skb!\n");
+		return -1;
+	}
+
+	sr = readl(si->firi_base + FIRIRSR);
+	dd_error = sr & FIRIRSR_DDE;
+	crc_error = sr & FIRIRSR_CRCE;
+	overrun_error = sr & FIRIRSR_RFO;
+
+	if (!(dd_error | crc_error | overrun_error)) {
+		return 0;
+	}
+	dev_err(si->dev, "dde,crce,rfo=%d,%d,%d.\n", dd_error, crc_error,
+		overrun_error);
+	si->stats.rx_errors++;
+	if (crc_error) {
+		si->stats.rx_crc_errors++;
+	}
+	if (dd_error) {
+		si->stats.rx_frame_errors++;
+	}
+	if (overrun_error) {
+		si->stats.rx_frame_errors++;
+	}
+	writel(sr, si->firi_base + FIRIRSR);
+
+	return -1;
+}
+
+#ifndef FIRI_SDMA_RX
+/*!
+ * FIR interrupt service routine to handle receive.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq_rx(struct net_device *dev)
+{
+	struct mxc_irda *si = dev->priv;
+	struct sk_buff *skb = si->rxskb;
+	unsigned int sr, len;
+	int i;
+	unsigned char *p = skb->data;
+
+	/*
+	 * Deal with any receive errors.
+	 */
+	if (mxc_irda_fir_error(si) != 0) {
+		return;
+	}
+
+	sr = readl(si->firi_base + FIRIRSR);
+
+	if (!(sr & FIRIRSR_RPE)) {
+		return;
+	}
+
+	/*
+	 * Coming here indicates that fir rx packet has been successfully recieved.
+	 * And No error happened so far.
+	 */
+	writel(sr | FIRIRSR_RPE, si->firi_base + FIRIRSR);
+
+	len = (sr & FIRIRSR_RFP) >> 8;
+
+	/* 4 bytes of CRC */
+	len -= 4;
+
+	skb_put(skb, len);
+
+	for (i = 0; i < len; i++) {
+		*p++ = readb(si->firi_base + FIRIRXFIFO);
+	}
+
+	/* Discard the four CRC bytes */
+	for (i = 0; i < 4; i++) {
+		readb(si->firi_base + FIRIRXFIFO);
+	}
+
+	/*
+	 * Deal with the case of packet complete.
+	 */
+	skb->dev = dev;
+	skb->mac.raw = skb->data;
+	skb->protocol = htons(ETH_P_IRDA);
+	si->stats.rx_packets++;
+	si->stats.rx_bytes += len;
+	netif_rx(skb);
+
+	si->rxskb = NULL;
+	mxc_irda_rx_alloc(si);
+
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+
+}
+#endif
+
+/*!
+ * FIR interrupt service routine to handle transmit.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq_tx(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	struct sk_buff *skb = si->txskb;
+	unsigned int cr, sr;
+
+	sr = readl(si->firi_base + FIRITSR);
+	writel(sr, si->firi_base + FIRITSR);
+
+	if (sr & FIRITSR_TC) {
+
+#ifdef FIRI_SDMA_TX
+		mxc_dma_disable(si->txdma_ch);
+#endif
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~(FIRITCR_TCIE | FIRITCR_TE);
+		writel(cr, si->firi_base + FIRITCR);
+
+		if (si->newspeed) {
+			mxc_irda_set_speed(si, si->newspeed);
+			si->newspeed = 0;
+		}
+		si->txskb = NULL;
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr |= FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		writel(0xFFFF, si->firi_base + FIRIRSR);
+		/*
+		 * Account and free the packet.
+		 */
+		if (skb) {
+#ifdef FIRI_SDMA_TX
+			dma_unmap_single(si->dev, si->dma_tx_buff_phy, skb->len,
+					 DMA_TO_DEVICE);
+#endif
+			si->stats.tx_packets++;
+			si->stats.tx_bytes += skb->len;
+			dev_kfree_skb_irq(skb);
+		}
+		/*
+		 * Make sure that the TX queue is available for sending
+		 * (for retries).  TX has priority over RX at all times.
+		 */
+		netif_wake_queue(dev);
+	}
+}
+
+/*!
+ * This is FIRI interrupt handler.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	unsigned int sr1, sr2;
+
+	sr1 = readl(si->firi_base + FIRIRSR);
+	sr2 = readl(si->firi_base + FIRITSR);
+
+	if (sr2 & FIRITSR_TC)
+		mxc_irda_fir_irq_tx(dev);
+#ifndef FIRI_SDMA_RX
+	if (sr1 & (FIRIRSR_RPE | FIRIRSR_RFO))
+		mxc_irda_fir_irq_rx(dev);
+#endif
+
+}
+
+/*!
+ * This is the SIR transmit routine.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @param   dev     pointer to the net_device structure
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_sir_txirq(struct mxc_irda *si, struct net_device *dev)
+{
+	unsigned int sr1, sr2, cr;
+	unsigned int status;
+
+	sr1 = readl(si->uart_base + MXC_UARTUSR1);
+	sr2 = readl(si->uart_base + MXC_UARTUSR2);
+	cr = readl(si->uart_base + MXC_UARTUCR2);
+
+	/*
+	 * Echo cancellation for IRDA Transmit chars
+	 * Disable the receiver and enable Transmit complete.
+	 */
+	cr &= ~MXC_UARTUCR2_RXEN;
+	writel(cr, si->uart_base + MXC_UARTUCR2);
+	cr = readl(si->uart_base + MXC_UARTUCR4);
+	cr |= MXC_UARTUCR4_TCEN;
+	writel(cr, si->uart_base + MXC_UARTUCR4);
+
+	while ((sr1 & MXC_UARTUSR1_TRDY) && si->tx_buff.len) {
+
+		writel(*si->tx_buff.data++, si->uart_base + MXC_UARTUTXD);
+		si->tx_buff.len -= 1;
+		sr1 = readl(si->uart_base + MXC_UARTUSR1);
+	}
+
+	if (si->tx_buff.len == 0) {
+		si->stats.tx_packets++;
+		si->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head;
+
+		/*Yoohoo...we are done...Lets stop Tx */
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr &= ~MXC_UARTUCR1_TRDYEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+
+		do {
+			status = readl(si->uart_base + MXC_UARTUSR2);
+		} while (!(status & MXC_UARTUSR2_TXDC));
+
+		if (si->newspeed) {
+			mxc_irda_set_speed(si, si->newspeed);
+			si->newspeed = 0;
+		}
+		/* I'm hungry! */
+		netif_wake_queue(dev);
+
+		/* Is the transmit complete to reenable the receiver? */
+		if (status & MXC_UARTUSR2_TXDC) {
+
+			cr = readl(si->uart_base + MXC_UARTUCR2);
+			cr |= MXC_UARTUCR2_RXEN;
+			writel(cr, si->uart_base + MXC_UARTUCR2);
+			/* Disable the Transmit complete interrupt bit */
+			cr = readl(si->uart_base + MXC_UARTUCR4);
+			cr &= ~MXC_UARTUCR4_TCEN;
+			writel(cr, si->uart_base + MXC_UARTUCR4);
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * This is the SIR receive routine.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @param   dev     pointer to the net_device structure
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_sir_rxirq(struct mxc_irda *si, struct net_device *dev)
+{
+	unsigned int data, status;
+	volatile unsigned int sr2;
+
+	sr2 = readl(si->uart_base + MXC_UARTUSR2);
+	while ((sr2 & MXC_UARTUSR2_RDR) == 1) {
+		data = readl(si->uart_base + MXC_UARTURXD);
+		status = data & 0xf400;
+		if (status & MXC_UARTURXD_ERR) {
+			dev_err(si->dev, "Receive an incorrect data =0x%x.\n",
+				data);
+			si->stats.rx_errors++;
+			if (status & MXC_UARTURXD_OVRRUN) {
+				si->stats.rx_fifo_errors++;
+				dev_err(si->dev, "Rx overrun.\n");
+			}
+			if (status & MXC_UARTURXD_FRMERR) {
+				si->stats.rx_frame_errors++;
+				dev_err(si->dev, "Rx frame error.\n");
+			}
+			if (status & MXC_UARTURXD_PRERR) {
+				dev_err(si->dev, "Rx parity error.\n");
+			}
+			/* Other: it is the Break char.
+			 * Do nothing for it. throw out the data.
+			 */
+			async_unwrap_char(dev, &si->stats, &si->rx_buff,
+					  (data & 0xFF));
+		} else {
+			/* It is correct data. */
+			data &= 0xFF;
+			async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
+
+			dev->last_rx = jiffies;
+		}
+		sr2 = readl(si->uart_base + MXC_UARTUSR2);
+
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+	}			/*while */
+	return 0;
+
+}
+
+static irqreturn_t mxc_irda_irq(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	if (IS_FIR(si)) {
+		mxc_irda_fir_irq(dev);
+		return IRQ_HANDLED;
+	}
+
+	if (readl(si->uart_base + MXC_UARTUCR2) & MXC_UARTUCR2_RXEN) {
+		mxc_irda_sir_rxirq(si, dev);
+	}
+	if ((readl(si->uart_base + MXC_UARTUCR1) & MXC_UARTUCR1_TRDYEN) &&
+	    (readl(si->uart_base + MXC_UARTUSR1) & MXC_UARTUSR1_TRDY)) {
+		mxc_irda_sir_txirq(si, dev);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxc_irda_tx_irq(int irq, void *dev_id)
+{
+
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	mxc_irda_sir_txirq(si, dev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxc_irda_rx_irq(int irq, void *dev_id)
+{
+
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	/* Clear the aging timer bit */
+	writel(MXC_UARTUSR1_AGTIM, si->uart_base + MXC_UARTUSR1);
+
+	mxc_irda_sir_rxirq(si, dev);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef FIRI_SDMA_RX
+struct tasklet_struct dma_rx_tasklet;
+
+static void mxc_irda_rx_task(unsigned long tparam)
+{
+	struct mxc_irda *si = (struct mxc_irda *)tparam;
+	struct sk_buff *lskb = si->tskb;
+
+	si->tskb = NULL;
+	if (lskb) {
+		lskb->mac_header = lskb->data;
+		lskb->protocol = htons(ETH_P_IRDA);
+		netif_rx(lskb);
+	}
+}
+
+/*!
+ * Receiver DMA callback routine.
+ *
+ * @param   id   pointer to network device structure
+ * @param   error_status   used to pass error status to this callback function
+ * @param   count   number of bytes received
+ */
+static void mxc_irda_fir_dma_rx_irq(void *id, int error_status,
+				    unsigned int count)
+{
+	struct net_device *dev = id;
+	struct mxc_irda *si = netdev_priv(dev);
+	struct sk_buff *skb = si->rxskb;
+	unsigned int cr;
+	unsigned int len;
+
+	cr = readl(si->firi_base + FIRIRCR);
+	cr &= ~FIRIRCR_RE;
+	writel(cr, si->firi_base + FIRIRCR);
+	cr = readl(si->firi_base + FIRIRCR);
+	cr |= FIRIRCR_RE;
+	writel(cr, si->firi_base + FIRIRCR);
+	len = count - 4;	/* remove 4 bytes for CRC */
+	skb_put(skb, len);
+	skb->dev = dev;
+	si->tskb = skb;
+	tasklet_schedule(&dma_rx_tasklet);
+
+	if (si->dma_rx_buff_phy != 0)
+		dma_unmap_single(si->dev, si->dma_rx_buff_phy,
+				 IRDA_FRAME_SIZE_LIMIT, DMA_FROM_DEVICE);
+
+	si->rxskb = NULL;
+	mxc_irda_rx_alloc(si);
+
+	SDMA_START_DELAY();
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+
+	if (si->rxskb) {
+		mxc_dma_enable(si->rxdma_ch);
+	}
+}
+#endif
+
+#ifdef FIRI_SDMA_TX
+/*!
+ * This function is called by SDMA Interrupt Service Routine to indicate
+ * requested DMA transfer is completed.
+ *
+ * @param   id   pointer to network device structure
+ * @param   error_status   used to pass error status to this callback function
+ * @param   count   number of bytes sent
+ */
+static void mxc_irda_fir_dma_tx_irq(void *id, int error_status,
+				    unsigned int count)
+{
+	struct net_device *dev = id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	mxc_dma_disable(si->txdma_ch);
+}
+#endif
+
+/*!
+ * This function is called by Linux IrDA network subsystem to
+ * transmit the Infrared data packet. The TX DMA channel is configured
+ * to transfer SK buffer data to FIRI TX FIFO along with DMA transfer
+ * completion routine.
+ *
+ * @param   skb   The packet that is queued to be sent
+ * @param   dev   net_device structure.
+ *
+ * @return  The function returns 0 on success and a negative value on
+ *          failure.
+ */
+static int mxc_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	int speed = irda_get_next_speed(skb);
+	unsigned int cr;
+
+	/*
+	 * Does this packet contain a request to change the interface
+	 * speed?  If so, remember it until we complete the transmission
+	 * of this frame.
+	 */
+	if (speed != si->speed && speed != -1) {
+		si->newspeed = speed;
+	}
+
+	/* If this is an empty frame, we can bypass a lot. */
+	if (skb->len == 0) {
+		if (si->newspeed) {
+			si->newspeed = 0;
+			mxc_irda_set_speed(si, speed);
+		}
+		dev_kfree_skb(skb);
+		return 0;
+	}
+
+	/* We must not be transmitting... */
+	netif_stop_queue(dev);
+	if (IS_SIR(si)) {
+
+		si->tx_buff.data = si->tx_buff.head;
+		si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data,
+						 si->tx_buff.truesize);
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr |= MXC_UARTUCR1_TRDYEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+		dev_kfree_skb(skb);
+	} else {
+		unsigned int mtt = irda_get_mtt(skb);
+		unsigned char *p = skb->data;
+		unsigned int skb_len = skb->len;
+#ifdef FIRI_SDMA_TX
+		mxc_dma_requestbuf_t dma_request;
+#else
+		unsigned int i, sr;
+#endif
+
+		skb_len = skb_len + ((4 - (skb_len % 4)) % 4);
+
+		if (si->txskb) {
+			BUG();
+		}
+		si->txskb = skb;
+
+		/*
+		 * If we have a mean turn-around time, impose the specified
+		 * specified delay.  We could shorten this by timing from
+		 * the point we received the packet.
+		 */
+		if (mtt) {
+			udelay(mtt);
+		}
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr &= ~FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		writel(skb->len - 1, si->firi_base + FIRITCTR);
+
+#ifdef FIRI_SDMA_TX
+		/*
+		 * Configure DMA Tx Channel for source and destination addresses,
+		 * Number of bytes in SK buffer to transfer and Transfer complete
+		 * callback function.
+		 */
+		si->dma_tx_buff_len = skb_len;
+		si->dma_tx_buff_phy =
+		    dma_map_single(si->dev, p, skb_len, DMA_TO_DEVICE);
+
+		dma_request.num_of_bytes = skb_len;
+		dma_request.dst_addr = si->firi_res->start + FIRITXFIFO;
+		dma_request.src_addr = si->dma_tx_buff_phy;
+
+		mxc_dma_config(si->txdma_ch, &dma_request, 1,
+			       MXC_DMA_MODE_WRITE);
+
+		mxc_dma_enable(si->txdma_ch);
+#endif
+		cr = readl(si->firi_base + FIRITCR);
+		cr |= FIRITCR_TCIE;
+		writel(cr, si->firi_base + FIRITCR);
+
+		cr |= FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+
+#ifndef FIRI_SDMA_TX
+		for (i = 0; i < skb->len;) {
+			sr = readl(si->firi_base + FIRITSR);
+			/* TFP = number of bytes in the TX FIFO for the
+			 * Transmitter
+			 * */
+			if ((sr >> 8) < 128) {
+				writeb(*p, si->firi_base + FIRITXFIFO);
+				p++;
+				i++;
+			}
+		}
+#endif
+	}
+
+	dev->trans_start = jiffies;
+	return 0;
+}
+
+/*!
+ * This function handles network interface ioctls passed to this driver..
+ *
+ * @param   dev   net device structure
+ * @param   ifreq user request data
+ * @param   cmd   command issued
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *           failure.
+ */
+static int mxc_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
+{
+	struct if_irda_req *rq = (struct if_irda_req *)ifreq;
+	struct mxc_irda *si = netdev_priv(dev);
+	int ret = -EOPNOTSUPP;
+
+	switch (cmd) {
+		/* This function will be used by IrLAP to change the speed */
+	case SIOCSBANDWIDTH:
+		dev_dbg(si->dev, "%s:with cmd SIOCSBANDWIDTH\n", __FUNCTION__);
+		if (capable(CAP_NET_ADMIN)) {
+			/*
+			 * We are unable to set the speed if the
+			 * device is not running.
+			 */
+			if (si->open) {
+				ret = mxc_irda_set_speed(si, rq->ifr_baudrate);
+			} else {
+				dev_err(si->dev, "mxc_ir_ioctl: SIOCSBANDWIDTH:\
+                                         !netif_running\n");
+				ret = 0;
+			}
+		}
+		break;
+	case SIOCSMEDIABUSY:
+		dev_dbg(si->dev, "%s:with cmd SIOCSMEDIABUSY\n", __FUNCTION__);
+		ret = -EPERM;
+		if (capable(CAP_NET_ADMIN)) {
+			irda_device_set_media_busy(dev, TRUE);
+			ret = 0;
+		}
+		break;
+	case SIOCGRECEIVING:
+		rq->ifr_receiving =
+		    IS_SIR(si) ? si->rx_buff.state != OUTSIDE_FRAME : 0;
+		ret = 0;
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+/*!
+ * Kernel interface routine to get current statistics of the device
+ * which includes the number bytes/packets transmitted/received,
+ * receive errors, CRC errors, framing errors etc.
+ *
+ * @param  dev  the net_device structure
+ *
+ * @return This function returns IrDA network statistics
+ */
+static struct net_device_stats *mxc_irda_stats(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	return &si->stats;
+}
+
+/*!
+ * FIRI init function
+ *
+ * @param si  FIRI device specific structure.
+ */
+void mxc_irda_firi_init(struct mxc_irda *si)
+{
+	unsigned int firi_baud, osf = 6;
+	unsigned int tcr, rcr, cr;
+
+	si->firi_clk = clk_get(si->dev, "firi_clk");
+	firi_baud = clk_round_rate(si->firi_clk, 48004500);
+	if ((firi_baud < 47995500) ||
+	    (clk_set_rate(si->firi_clk, firi_baud) < 0)) {
+		dev_err(si->dev, "Unable to set FIR clock to 48MHz.\n");
+		return;
+	}
+	clk_enable(si->firi_clk);
+
+	writel(0xFFFF, si->firi_base + FIRITSR);
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+	writel(0x00, si->firi_base + FIRITCR);
+	writel(0x00, si->firi_base + FIRIRCR);
+
+	/* set _BL & _OSF */
+	cr = (osf - 1) | (16 << 5);
+	writel(cr, si->firi_base + FIRICR);
+
+#ifdef FIRI_SDMA_TX
+	tcr =
+	    FIRITCR_TDT_FIR | FIRITCR_TM_FIR | FIRITCR_TCIE |
+	    FIRITCR_PCF | FIRITCR_PC;
+#else
+	tcr = FIRITCR_TM_FIR | FIRITCR_TCIE | FIRITCR_PCF | FIRITCR_PC;
+#endif
+
+#ifdef FIRI_SDMA_RX
+	rcr =
+	    FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR |
+	    FIRIRCR_RPA | FIRIRCR_RPP;
+#else
+	rcr =
+	    FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | FIRIRCR_RPEIE |
+	    FIRIRCR_RPA | FIRIRCR_PAIE | FIRIRCR_RFOIE | FIRIRCR_RPP;
+#endif
+
+	writel(tcr, si->firi_base + FIRITCR);
+	writel(rcr, si->firi_base + FIRIRCR);
+	cr = 0;
+	writel(cr, si->firi_base + FIRITCTR);
+}
+
+/*!
+ * This function initialises the UART.
+ *
+ * @param   si  FIRI port specific structure.
+ *
+ * @return  The function returns 0 on success.
+ */
+static int mxc_irda_uart_init(struct mxc_irda *si)
+{
+	unsigned int per_clk;
+	unsigned int num, denom, baud, ufcr = 0;
+	unsigned int cr;
+	int d = 1;
+	int uart_ir_mux = 0;
+
+	if (si->mxc_ir_plat)
+		uart_ir_mux = si->mxc_ir_plat->uart_ir_mux;
+	/*
+	 * Clear Status Registers 1 and 2
+	 **/
+	writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+	writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+
+	/* Configure the IOMUX for the UART */
+	gpio_firi_init();
+
+	per_clk = clk_get_rate(si->uart_clk);
+	baud = per_clk / 16;
+	if (baud > 1500000) {
+		baud = 1500000;
+		d = per_clk / ((baud * 16) + 1000);
+		if (d > 6) {
+			d = 6;
+		}
+	}
+	clk_enable(si->uart_clk);
+
+	si->uart_clk_rate = per_clk / d;
+	writel(si->uart_clk_rate / 1000, si->uart_base + MXC_UARTONEMS);
+
+	writel(si->mxc_ir_plat->ir_rx_invert | MXC_UARTUCR4_IRSC,
+	       si->uart_base + MXC_UARTUCR4);
+
+	if (uart_ir_mux) {
+		writel(MXC_UARTUCR3_RXDMUXSEL | si->mxc_ir_plat->ir_tx_invert |
+		       MXC_UARTUCR3_DSR, si->uart_base + MXC_UARTUCR3);
+	} else {
+		writel(si->mxc_ir_plat->ir_tx_invert | MXC_UARTUCR3_DSR,
+		       si->uart_base + MXC_UARTUCR3);
+	}
+
+	writel(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTS | MXC_UARTUCR2_WS |
+	       MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN,
+	       si->uart_base + MXC_UARTUCR2);
+	/* Wait till we are out of software reset */
+	do {
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+	} while (!(cr & MXC_UARTUCR2_SRST));
+
+	ufcr |= (UART4_UFCR_TXTL << MXC_UARTUFCR_TXTL_OFFSET) |
+	    ((6 - d) << MXC_UARTUFCR_RFDIV_OFFSET) | UART4_UFCR_RXTL;
+	writel(ufcr, si->uart_base + MXC_UARTUFCR);
+
+	writel(MXC_UARTUCR1_UARTEN | MXC_UARTUCR1_IREN,
+	       si->uart_base + MXC_UARTUCR1);
+
+	baud = 9600;
+	num = baud / 100 - 1;
+	denom = si->uart_clk_rate / 1600 - 1;
+
+	if ((denom < 65536) && (si->uart_clk_rate > 1600)) {
+		writel(num, si->uart_base + MXC_UARTUBIR);
+		writel(denom, si->uart_base + MXC_UARTUBMR);
+	}
+
+	writel(0x0000, si->uart_base + MXC_UARTUTS);
+	return 0;
+
+}
+
+/*!
+ * This function enables FIRI port.
+ *
+ * @param   si  FIRI port specific structure.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_startup(struct mxc_irda *si)
+{
+	int ret = 0;
+
+	mxc_irda_uart_init(si);
+	mxc_irda_firi_init(si);
+
+	/* configure FIRI device for speed */
+	ret = mxc_irda_set_speed(si, si->speed = 9600);
+
+	return ret;
+}
+
+/*!
+ * When an ifconfig is issued which changes the device flag to include
+ * IFF_UP this function is called. It is only called when the change
+ * occurs, not when the interface remains up. The function grabs the interrupt
+ * resources and registers FIRI interrupt service routines, requests for DMA
+ * channels, configures the DMA channel. It then initializes  the IOMUX
+ * registers to configure the pins for FIRI signals and finally initializes the
+ * various FIRI registers and enables the port for reception.
+ *
+ * @param   dev   net device structure that is being opened
+ *
+ * @return  The function returns 0 for a successful open and non-zero value
+ *          on failure.
+ */
+static int mxc_irda_start(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	int err;
+	int ints_muxed = 0;
+	mxc_dma_device_t dev_id = 0;
+
+	if (si->uart_irq == si->uart_irq1)
+		ints_muxed = 1;
+
+	si->speed = 9600;
+
+	if (si->uart_irq == si->firi_irq) {
+		err =
+		    request_irq(si->uart_irq, mxc_irda_irq, 0, dev->name, dev);
+		if (err) {
+			dev_err(si->dev, "%s:Failed to request the IRQ\n",
+				__FUNCTION__);
+			return err;
+		}
+		/*
+		 * The interrupt must remain disabled for now.
+		 */
+		disable_irq(si->uart_irq);
+	} else {
+		err =
+		    request_irq(si->firi_irq, mxc_irda_irq, 0, dev->name, dev);
+		if (err) {
+			dev_err(si->dev, "%s:Failed to request FIRI IRQ\n",
+				__FUNCTION__);
+			return err;
+		}
+		/*
+		 * The interrupt must remain disabled for now.
+		 */
+		disable_irq(si->firi_irq);
+		if (ints_muxed) {
+
+			err = request_irq(si->uart_irq, mxc_irda_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART IRQ\n",
+					__FUNCTION__);
+				goto err_irq1;
+			}
+			/*
+			 * The interrupt must remain disabled for now.
+			 */
+			disable_irq(si->uart_irq);
+		} else {
+			err = request_irq(si->uart_irq, mxc_irda_tx_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART IRQ\n",
+					__FUNCTION__);
+				goto err_irq1;
+			}
+			err = request_irq(si->uart_irq1, mxc_irda_rx_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART1 IRQ\n",
+					__FUNCTION__);
+				goto err_irq2;
+			}
+			/*
+			 * The interrupts must remain disabled for now.
+			 */
+			disable_irq(si->uart_irq);
+			disable_irq(si->uart_irq1);
+		}
+	}
+#ifdef FIRI_SDMA_RX
+	dev_id = MXC_DMA_FIR_RX;
+	si->rxdma_ch = mxc_dma_request(dev_id, "MXC FIRI RX");
+	if (si->rxdma_ch < 0) {
+		dev_err(si->dev, "Cannot allocate FIR DMA channel\n");
+		goto err_rx_dma;
+	}
+	mxc_dma_callback_set(si->rxdma_ch, mxc_irda_fir_dma_rx_irq,
+			     (void *)dev_get_drvdata(si->dev));
+#endif
+#ifdef FIRI_SDMA_TX
+
+	dev_id = MXC_DMA_FIR_TX;
+	si->txdma_ch = mxc_dma_request(dev_id, "MXC FIRI TX");
+	if (si->txdma_ch < 0) {
+		dev_err(si->dev, "Cannot allocate FIR DMA channel\n");
+		goto err_tx_dma;
+	}
+	mxc_dma_callback_set(si->txdma_ch, mxc_irda_fir_dma_tx_irq,
+			     (void *)dev_get_drvdata(si->dev));
+#endif
+	/* Setup the serial port port for the initial speed. */
+	err = mxc_irda_startup(si);
+	if (err) {
+		goto err_startup;
+	}
+
+	/* Open a new IrLAP layer instance. */
+	si->irlap = irlap_open(dev, &si->qos, "mxc");
+	err = -ENOMEM;
+	if (!si->irlap) {
+		goto err_irlap;
+	}
+
+	/* Now enable the interrupt and start the queue */
+	si->open = 1;
+	si->suspend = 0;
+
+	if (si->uart_irq == si->firi_irq) {
+		enable_irq(si->uart_irq);
+	} else {
+		enable_irq(si->firi_irq);
+		if (ints_muxed == 1) {
+			enable_irq(si->uart_irq);
+		} else {
+			enable_irq(si->uart_irq);
+			enable_irq(si->uart_irq1);
+		}
+	}
+
+	netif_start_queue(dev);
+	return 0;
+
+      err_irlap:
+	si->open = 0;
+	mxc_irda_disabledma(si);
+      err_startup:
+#ifdef FIRI_SDMA_TX
+	mxc_dma_free(si->txdma_ch);
+      err_tx_dma:
+#endif
+#ifdef FIRI_SDMA_RX
+	mxc_dma_free(si->rxdma_ch);
+      err_rx_dma:
+#endif
+	if (si->uart_irq1 && !ints_muxed)
+		free_irq(si->uart_irq1, dev);
+      err_irq2:
+	if (si->uart_irq != si->firi_irq)
+		free_irq(si->uart_irq, dev);
+      err_irq1:
+	if (si->firi_irq)
+		free_irq(si->firi_irq, dev);
+	return err;
+}
+
+/*!
+ * This function is called when IFF_UP flag has been cleared by the user via
+ * the ifconfig irda0 down command. This function stops any further
+ * transmissions being queued, and then disables the interrupts.
+ * Finally it resets the device.
+ * @param   dev   the net_device structure
+ *
+ * @return  int   the function always returns 0 indicating a success.
+ */
+static int mxc_irda_stop(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	unsigned long flags;
+
+	/* Stop IrLAP */
+	if (si->irlap) {
+		irlap_close(si->irlap);
+		si->irlap = NULL;
+	}
+
+	netif_stop_queue(dev);
+
+	/*Save flags and disable the FIRI interrupts.. */
+	if (si->open) {
+		local_irq_save(flags);
+		disable_irq(si->uart_irq);
+		free_irq(si->uart_irq, dev);
+		if (si->uart_irq != si->firi_irq) {
+			disable_irq(si->firi_irq);
+			free_irq(si->firi_irq, dev);
+			if (si->uart_irq1 != si->uart_irq) {
+				disable_irq(si->uart_irq1);
+				free_irq(si->uart_irq1, dev);
+			}
+		}
+		local_irq_restore(flags);
+		si->open = 0;
+	}
+#ifdef FIRI_SDMA_RX
+	if (si->rxdma_ch) {
+		mxc_dma_disable(si->rxdma_ch);
+		mxc_dma_free(si->rxdma_ch);
+		if (si->dma_rx_buff_phy) {
+			dma_unmap_single(si->dev, si->dma_rx_buff_phy,
+					 IRDA_FRAME_SIZE_LIMIT,
+					 DMA_FROM_DEVICE);
+			si->dma_rx_buff_phy = 0;
+		}
+		si->rxdma_ch = 0;
+	}
+	tasklet_kill(&dma_rx_tasklet);
+#endif
+#ifdef FIRI_SDMA_TX
+	if (si->txdma_ch) {
+		mxc_dma_disable(si->txdma_ch);
+		mxc_dma_free(si->txdma_ch);
+		if (si->dma_tx_buff_phy) {
+			dma_unmap_single(si->dev, si->dma_tx_buff_phy,
+					 si->dma_tx_buff_len, DMA_TO_DEVICE);
+			si->dma_tx_buff_phy = 0;
+		}
+		si->txdma_ch = 0;
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This function is called to put the FIRI in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(ndev);
+	unsigned int cr;
+	unsigned long flags;
+
+	if (!si) {
+		return 0;
+	}
+	if (si->suspend == 1) {
+		dev_err(si->dev,
+			" suspend - Device is already suspended ... \n");
+		return 0;
+	}
+	if (si->open) {
+
+		netif_device_detach(ndev);
+		mxc_irda_disabledma(si);
+
+		/*Save flags and disable the FIRI interrupts.. */
+		local_irq_save(flags);
+		disable_irq(si->uart_irq);
+		if (si->uart_irq != si->firi_irq) {
+			disable_irq(si->firi_irq);
+			if (si->uart_irq != si->uart_irq1) {
+				disable_irq(si->uart_irq1);
+			}
+		}
+		local_irq_restore(flags);
+
+		/* Disable Tx and Rx and then disable the UART clock */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr &= ~MXC_UARTUCR1_UARTEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+		clk_disable(si->uart_clk);
+
+		/*Disable Tx and Rx for FIRI and then disable the FIRI clock.. */
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+		cr = readl(si->firi_base + FIRIRCR);
+		cr &= ~FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+		clk_disable(si->firi_clk);
+
+		gpio_firi_inactive();
+
+		si->suspend = 1;
+		si->open = 0;
+	}
+	return 0;
+}
+
+/*!
+ * This function is called to bring the FIRI back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!si) {
+		return 0;
+	}
+
+	if (si->suspend == 1 && !si->open) {
+
+		/*Initialise the UART first */
+		clk_enable(si->uart_clk);
+
+		/*Now init FIRI */
+		gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP);
+		mxc_irda_startup(si);
+
+		/* Enable the UART and FIRI interrupts.. */
+		local_irq_save(flags);
+		enable_irq(si->uart_irq);
+		if (si->uart_irq != si->firi_irq) {
+			enable_irq(si->firi_irq);
+			if (si->uart_irq != si->uart_irq1) {
+				enable_irq(si->uart_irq1);
+			}
+		}
+		local_irq_restore(flags);
+
+		/* Let the kernel know that we are alive and kicking.. */
+		netif_device_attach(ndev);
+
+		si->suspend = 0;
+		si->open = 1;
+	}
+	return 0;
+}
+#else
+#define mxc_irda_suspend NULL
+#define mxc_irda_resume  NULL
+#endif
+
+static int mxc_irda_init_iobuf(iobuff_t * io, int size)
+{
+	io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
+	if (io->head != NULL) {
+		io->truesize = size;
+		io->in_frame = FALSE;
+		io->state = OUTSIDE_FRAME;
+		io->data = io->head;
+	}
+	return io->head ? 0 : -ENOMEM;
+
+}
+
+static struct net_device_ops mxc_irda_ops = {
+	.ndo_start_xmit = mxc_irda_hard_xmit,
+	.ndo_open = mxc_irda_start,
+	.ndo_stop = mxc_irda_stop,
+	.ndo_do_ioctl = mxc_irda_ioctl,
+	.ndo_get_stats = mxc_irda_stats,
+};
+
+/*!
+ * This function is called during the driver binding process.
+ * This function requests for memory, initializes net_device structure and
+ * registers with kernel.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure
+ */
+static int mxc_irda_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	struct mxc_irda *si;
+	struct resource *uart_res, *firi_res;
+	int uart_irq, firi_irq, uart_irq1;
+	unsigned int baudrate_mask = 0;
+	int err;
+
+	uart_res = &pdev->resource[0];
+	uart_irq = pdev->resource[1].start;
+
+	firi_res = &pdev->resource[2];
+	firi_irq = pdev->resource[3].start;
+
+	uart_irq1 = pdev->resource[4].start;
+
+	if (!uart_res || uart_irq == NO_IRQ || !firi_res || firi_irq == NO_IRQ) {
+		dev_err(&pdev->dev, "Unable to find resources\n");
+		return -ENXIO;
+	}
+
+	err =
+	    request_mem_region(uart_res->start, SZ_16K,
+			       "MXC_IRDA") ? 0 : -EBUSY;
+	if (err) {
+		dev_err(&pdev->dev, "Failed to request UART memory region\n");
+		return -ENOMEM;
+	}
+
+	err =
+	    request_mem_region(firi_res->start, SZ_16K,
+			       "MXC_IRDA") ? 0 : -EBUSY;
+	if (err) {
+		dev_err(&pdev->dev, "Failed to request FIRI  memory region\n");
+		goto err_mem_1;
+	}
+
+	dev = alloc_irdadev(sizeof(struct mxc_irda));
+	if (!dev) {
+		goto err_mem_2;
+	}
+
+	si = netdev_priv(dev);
+	si->dev = &pdev->dev;
+
+	si->mxc_ir_plat = pdev->dev.platform_data;
+	si->uart_clk = si->mxc_ir_plat->uart_clk;
+
+	si->uart_res = uart_res;
+	si->firi_res = firi_res;
+	si->uart_irq = uart_irq;
+	si->firi_irq = firi_irq;
+	si->uart_irq1 = uart_irq1;
+
+	si->uart_base = ioremap(uart_res->start, SZ_16K);
+	si->firi_base = ioremap(firi_res->start, SZ_16K);
+
+	if (!(si->uart_base || si->firi_base)) {
+		err = -ENOMEM;
+		goto err_mem_3;
+	}
+
+	/*
+	 * Initialise the SIR buffers
+	 */
+	err = mxc_irda_init_iobuf(&si->rx_buff, UART_BUFF_SIZE);
+	if (err) {
+		goto err_mem_4;
+	}
+
+	err = mxc_irda_init_iobuf(&si->tx_buff, UART_BUFF_SIZE);
+	if (err) {
+		goto err_mem_5;
+	}
+
+	dev->netdev_ops = &mxc_irda_ops;
+
+	irda_init_max_qos_capabilies(&si->qos);
+
+	/*
+	 * We support
+	 * SIR(9600, 19200,38400, 57600 and 115200 bps)
+	 * FIR(4 Mbps)
+	 * Min Turn Time set to 1ms or greater.
+	 */
+	baudrate_mask |= IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
+	baudrate_mask |= IR_4000000 << 8;
+
+	si->qos.baud_rate.bits &= baudrate_mask;
+	si->qos.min_turn_time.bits = 0x7;
+
+	irda_qos_bits_to_value(&si->qos);
+
+#ifdef FIRI_SDMA_RX
+	si->tskb = NULL;
+	tasklet_init(&dma_rx_tasklet, mxc_irda_rx_task, (unsigned long)si);
+#endif
+	err = register_netdev(dev);
+	if (err == 0) {
+		platform_set_drvdata(pdev, dev);
+	} else {
+		kfree(si->tx_buff.head);
+	      err_mem_5:
+		kfree(si->rx_buff.head);
+	      err_mem_4:
+		iounmap(si->uart_base);
+		iounmap(si->firi_base);
+	      err_mem_3:
+		free_netdev(dev);
+	      err_mem_2:
+		release_mem_region(firi_res->start, SZ_16K);
+	      err_mem_1:
+		release_mem_region(uart_res->start, SZ_16K);
+	}
+	return err;
+}
+
+/*!
+ * Dissociates the driver from the FIRI device. Removes the appropriate FIRI
+ * port structure from the kernel.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(dev);
+
+	if (si->uart_base)
+		iounmap(si->uart_base);
+	if (si->firi_base)
+		iounmap(si->firi_base);
+	if (si->firi_res->start)
+		release_mem_region(si->firi_res->start, SZ_16K);
+	if (si->uart_res->start)
+		release_mem_region(si->uart_res->start, SZ_16K);
+	if (si->tx_buff.head)
+		kfree(si->tx_buff.head);
+	if (si->rx_buff.head)
+		kfree(si->rx_buff.head);
+
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(dev);
+	free_netdev(dev);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcir_driver = {
+	.driver = {
+		   .name = "mxcir",
+		   },
+	.probe = mxc_irda_probe,
+	.remove = mxc_irda_remove,
+	.suspend = mxc_irda_suspend,
+	.resume = mxc_irda_resume,
+};
+
+/*!
+ * This function is used to initialize the FIRI driver module. The function
+ * registers the power management callback functions with the kernel and also
+ * registers the FIRI callback functions.
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxc_irda_init(void)
+{
+	return platform_driver_register(&mxcir_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxc_irda_exit(void)
+{
+	platform_driver_unregister(&mxcir_driver);
+}
+
+module_init(mxc_irda_init);
+module_exit(mxc_irda_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("MXC IrDA(SIR/FIR) driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/irda/mxc_ir.h b/drivers/net/irda/mxc_ir.h
new file mode 100644
index 000000000000..6b22ca129f27
--- /dev/null
+++ b/drivers/net/irda/mxc_ir.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXC_FIRI_REG_H__
+#define __MXC_FIRI_REG_H__
+
+#include <mach/hardware.h>
+
+/*!
+ * @defgroup FIRI Fast IR Driver
+ */
+
+/*!
+ * @file mxc_ir.h
+ *
+ * @brief  MXC FIRI header file
+ *
+ * This file defines base address and bits of FIRI registers
+ *
+ * @ingroup FIRI
+ */
+
+/*!
+ * FIRI maximum packet length
+ */
+#define FIR_MAX_RXLEN           2047
+
+/*
+ * FIRI Transmitter Control Register
+ */
+#define FIRITCR 0x00
+/*
+ * FIRI Transmitter Count Register
+ */
+#define FIRITCTR 0x04
+/*
+ * FIRI Receiver Control Register
+ */
+#define FIRIRCR 0x08
+/*
+ * FIRI Transmitter Status Register
+ */
+#define FIRITSR 0x0C
+/*
+ * FIRI Receiver Status Register
+ */
+#define FIRIRSR 0x10
+/*
+ * FIRI Transmitter FIFO
+ */
+#define FIRITXFIFO 0x14
+/*
+ * FIRI Receiver FIFO
+ */
+#define FIRIRXFIFO 0x18
+/*
+ * FIRI Control Register
+ */
+#define FIRICR 0x1C
+
+/*
+ * Bit definitions of Transmitter Controller Register
+ */
+#define FIRITCR_HAG     (1<<24)	/* H/W address generator */
+#define FIRITCR_SRF_FIR (0<<13)	/* Start field repeat factor */
+#define FIRITCR_SRF_MIR (1<<13)	/* Start field Repeat Factor */
+#define FIRITCR_TDT_MIR (2<<10)	/* TX trigger for MIR is set to 32 bytes) */
+#define FIRITCR_TDT_FIR (1<<10)	/* TX trigger for FIR is set to 16 bytes) */
+#define FIRITCR_TCIE    (1<<9)	/* TX Complete Interrupt Enable */
+#define FIRITCR_TPEIE   (1<<8)	/* TX Packet End Interrupt Enable */
+#define FIRITCR_TFUIE   (1<<7)	/* TX FIFO Under-run Interrupt Enable */
+#define FIRITCR_PCF     (1<<6)	/* Packet Complete by FIFO */
+#define FIRITCR_PC      (1<<5)	/* Packet Complete */
+#define FIRITCR_SIP     (1<<4)	/* TX Enable of SIP */
+#define FIRITCR_TPP     (1<<3)	/* TX Pulse Polarity bit */
+#define FIRITCR_TM_FIR  (0<<1)	/* TX Mode 4 Mbps */
+#define FIRITCR_TM_MIR1 (1<<1)	/* TX Mode 0.576 Mbps */
+#define FIRITCR_TM_MIR2 (1<<2)	/* TX Mode 1.152 Mbps */
+#define FIRITCR_TE      (1<<0)	/* TX Enable */
+
+/*
+ * Bit definitions of Transmitter Count Register
+ */
+#define FIRITCTR_TPL     511	/* TX Packet Length set to 512 bytes */
+
+/*
+ * Bit definitions of Receiver Control Register
+ */
+#define FIRIRCR_RAM     (1<<24)	/* RX Address Match */
+#define FIRIRCR_RPEDE   (1<<11)	/* Packet End DMA request Enable */
+#define FIRIRCR_RDT_MIR (2<<8)	/* DMA Trigger level(64 bytes in RXFIFO) */
+#define FIRIRCR_RDT_FIR (1<<8)	/* DMA Trigger level(16 bytes in RXFIFO) */
+#define FIRIRCR_RPA     (1<<7)	/* RX Packet Abort */
+#define FIRIRCR_RPEIE   (1<<6)	/* RX Packet End Interrupt Enable */
+#define FIRIRCR_PAIE    (1<<5)	/* Packet Abort Interrupt Enable */
+#define FIRIRCR_RFOIE   (1<<4)	/* RX FIFO Overrun Interrupt Enable */
+#define FIRIRCR_RPP     (1<<3)	/* RX Pulse Polarity bit */
+#define FIRIRCR_RM_FIR  (0<<1)	/* 4 Mbps */
+#define FIRIRCR_RM_MIR1 (1<<1)	/* 0.576 Mbps */
+#define FIRIRCR_RM_MIR2 (1<<2)	/* 1.152 Mbps */
+#define FIRIRCR_RE      (1<<0)	/* RX Enable */
+
+/* Transmitter Status Register */
+#define FIRITSR_TFP     0xFF00	/* Mask for available bytes in TX FIFO */
+#define FIRITSR_TC      (1<<3)	/* Transmit Complete bit */
+#define FIRITSR_SIPE    (1<<2)	/* SIP End bit */
+#define FIRITSR_TPE     (1<<1)	/* Transmit Packet End */
+#define FIRITSR_TFU     (1<<0)	/* TX FIFO Under-run */
+
+/* Receiver Status Register */
+#define FIRIRSR_RFP     0xFF00	/* mask for available bytes RX FIFO */
+#define FIRIRSR_PAS     (1<<5)	/* preamble search */
+#define FIRIRSR_RPE     (1<<4)	/* RX Packet End */
+#define FIRIRSR_RFO     (1<<3)	/* RX FIFO Overrun */
+#define FIRIRSR_BAM     (1<<2)	/* Broadcast Address Match */
+#define FIRIRSR_CRCE    (1<<1)	/* CRC error */
+#define FIRIRSR_DDE     (1<<0)	/* Address, control or data field error */
+
+/* FIRI Control Register */
+#define FIRICR_BL       (32<<5)	/* Burst Length is set to 32 */
+#define FIRICR_OSF      (0<<1)	/* Over Sampling Factor */
+
+#endif				/* __MXC_FIRI_REG_H__ */
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index bd4e8d72dc08..e17b70291bbc 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -264,6 +264,8 @@ static int mdio_bus_match(struct device *dev, struct device_driver *drv)
 		(phydev->phy_id & phydrv->phy_id_mask));
 }
 
+#ifdef CONFIG_PM
+
 static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 {
 	struct device_driver *drv = phydev->dev.driver;
@@ -295,34 +297,88 @@ static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 	return true;
 }
 
-/* Suspend and resume.  Copied from platform_suspend and
- * platform_resume
- */
-static int mdio_bus_suspend(struct device * dev, pm_message_t state)
+static int mdio_bus_suspend(struct device *dev)
 {
 	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
 
+	/*
+	 * We must stop the state machine manually, otherwise it stops out of
+	 * control, possibly with the phydev->lock held. Upon resume, netdev
+	 * may call phy routines that try to grab the same lock, and that may
+	 * lead to a deadlock.
+	 */
+	if (phydev->attached_dev)
+		phy_stop_machine(phydev);
+
 	if (!mdio_bus_phy_may_suspend(phydev))
 		return 0;
+
 	return phydrv->suspend(phydev);
 }
 
-static int mdio_bus_resume(struct device * dev)
+static int mdio_bus_resume(struct device *dev)
 {
 	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
+	int ret;
 
 	if (!mdio_bus_phy_may_suspend(phydev))
+		goto no_resume;
+
+	ret = phydrv->resume(phydev);
+	if (ret < 0)
+		return ret;
+
+no_resume:
+	if (phydev->attached_dev)
+		phy_start_machine(phydev, NULL);
+
+	return 0;
+}
+
+static int mdio_bus_restore(struct device *dev)
+{
+	struct phy_device *phydev = to_phy_device(dev);
+	struct net_device *netdev = phydev->attached_dev;
+	int ret;
+
+	if (!netdev)
 		return 0;
-	return phydrv->resume(phydev);
+
+	ret = phy_init_hw(phydev);
+	if (ret < 0)
+		return ret;
+
+	/* The PHY needs to renegotiate. */
+	phydev->link = 0;
+	phydev->state = PHY_UP;
+
+	phy_start_machine(phydev, NULL);
+
+	return 0;
 }
 
+static struct dev_pm_ops mdio_bus_pm_ops = {
+	.suspend = mdio_bus_suspend,
+	.resume = mdio_bus_resume,
+	.freeze = mdio_bus_suspend,
+	.thaw = mdio_bus_resume,
+	.restore = mdio_bus_restore,
+};
+
+#define MDIO_BUS_PM_OPS (&mdio_bus_pm_ops)
+
+#else
+
+#define MDIO_BUS_PM_OPS NULL
+
+#endif /* CONFIG_PM */
+
 struct bus_type mdio_bus_type = {
 	.name		= "mdio_bus",
 	.match		= mdio_bus_match,
-	.suspend	= mdio_bus_suspend,
-	.resume		= mdio_bus_resume,
+	.pm		= MDIO_BUS_PM_OPS,
 };
 EXPORT_SYMBOL(mdio_bus_type);
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index eda94fcd4065..d2df6382e123 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -413,7 +413,6 @@ EXPORT_SYMBOL(phy_start_aneg);
 
 
 static void phy_change(struct work_struct *work);
-static void phy_state_machine(struct work_struct *work);
 
 /**
  * phy_start_machine - start PHY state machine tracking
@@ -433,7 +432,6 @@ void phy_start_machine(struct phy_device *phydev,
 {
 	phydev->adjust_state = handler;
 
-	INIT_DELAYED_WORK(&phydev->state_queue, phy_state_machine);
 	schedule_delayed_work(&phydev->state_queue, HZ);
 }
 
@@ -764,7 +762,7 @@ EXPORT_SYMBOL(phy_start);
  * phy_state_machine - Handle the state machine
  * @work: work_struct that describes the work to be done
  */
-static void phy_state_machine(struct work_struct *work)
+void phy_state_machine(struct work_struct *work)
 {
 	struct delayed_work *dwork = to_delayed_work(work);
 	struct phy_device *phydev =
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index b10fedd82143..adbc0fded130 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -177,6 +177,7 @@ struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id)
 	dev->state = PHY_DOWN;
 
 	mutex_init(&dev->lock);
+	INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
 
 	return dev;
 }
@@ -378,6 +379,20 @@ void phy_disconnect(struct phy_device *phydev)
 }
 EXPORT_SYMBOL(phy_disconnect);
 
+int phy_init_hw(struct phy_device *phydev)
+{
+	int ret;
+
+	if (!phydev->drv || !phydev->drv->config_init)
+		return 0;
+
+	ret = phy_scan_fixups(phydev);
+	if (ret < 0)
+		return ret;
+
+	return phydev->drv->config_init(phydev);
+}
+
 /**
  * phy_attach_direct - attach a network device to a given PHY device pointer
  * @dev: network device to attach
@@ -425,21 +440,7 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
 	/* Do initial configuration here, now that
 	 * we have certain key parameters
 	 * (dev_flags and interface) */
-	if (phydev->drv->config_init) {
-		int err;
-
-		err = phy_scan_fixups(phydev);
-
-		if (err < 0)
-			return err;
-
-		err = phydev->drv->config_init(phydev);
-
-		if (err < 0)
-			return err;
-	}
-
-	return 0;
+	return phy_init_hw(phydev);
 }
 EXPORT_SYMBOL(phy_attach_direct);
 
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
index 94b6d2658ddc..04907ae11f51 100644
--- a/drivers/net/smsc911x.c
+++ b/drivers/net/smsc911x.c
@@ -128,6 +128,16 @@ static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
 	if (pdata->config.flags & SMSC911X_USE_32BIT)
 		return readl(pdata->ioaddr + reg);
 
+#ifdef CONFIG_ARCH_MXC
+	if (pdata->config.flags & 0x8000) {
+		u32 data;
+		unsigned long flags;
+		spin_lock_irqsave(&pdata->dev_lock, flags);
+		data = spi_cpld_read(reg);
+		spin_unlock_irqrestore(&pdata->dev_lock, flags);
+		return data;
+	} else
+#endif
 	if (pdata->config.flags & SMSC911X_USE_16BIT) {
 		u32 data;
 		unsigned long flags;
@@ -155,6 +165,15 @@ static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
 		return;
 	}
 
+#ifdef CONFIG_ARCH_MXC
+	if (pdata->config.flags & 0x8000) {
+		unsigned long flags;
+		spin_lock_irqsave(&pdata->dev_lock, flags);
+		spi_cpld_write(reg, val);
+		spin_unlock_irqrestore(&pdata->dev_lock, flags);
+		return;
+	} else
+#endif
 	if (pdata->config.flags & SMSC911X_USE_16BIT) {
 		unsigned long flags;
 
@@ -2118,6 +2137,9 @@ static int smsc911x_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct net_device *dev = platform_get_drvdata(pdev);
 	struct smsc911x_data *pdata = netdev_priv(dev);
+	struct phy_device *phy_dev = pdata->phy_dev;
+
+	smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_PDOWN);
 
 	/* enable wake on LAN, energy detection and the external PME
 	 * signal. */
@@ -2132,6 +2154,7 @@ static int smsc911x_resume(struct platform_device *pdev)
 {
 	struct net_device *dev = platform_get_drvdata(pdev);
 	struct smsc911x_data *pdata = netdev_priv(dev);
+	struct phy_device *phy_dev = pdata->phy_dev;
 	unsigned int to = 100;
 
 	/* Note 3.11 from the datasheet:
@@ -2146,6 +2169,8 @@ static int smsc911x_resume(struct platform_device *pdev)
 	while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
 		udelay(1000);
 
+	smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
+
 	return (to == 0) ? -EIO : 0;
 }
 
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 5bc00db21b24..32ec9aafa39d 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -503,5 +503,6 @@ source "drivers/net/wireless/rt2x00/Kconfig"
 source "drivers/net/wireless/orinoco/Kconfig"
 source "drivers/net/wireless/wl12xx/Kconfig"
 source "drivers/net/wireless/iwmc3200wifi/Kconfig"
+source "drivers/net/wireless/ath6kl/Kconfig"
 
 endmenu
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 7a4647e78fd3..a1a2df3973a5 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -62,3 +62,5 @@ obj-$(CONFIG_MAC80211_HWSIM)	+= mac80211_hwsim.o
 obj-$(CONFIG_WL12XX)	+= wl12xx/
 
 obj-$(CONFIG_IWM)	+= iwmc3200wifi/
+
+obj-$(CONFIG_ATH6K_LEGACY)	+= ath6kl/
diff --git a/drivers/net/wireless/ath6kl/Kconfig b/drivers/net/wireless/ath6kl/Kconfig
new file mode 100644
index 000000000000..cc0e5e3a5cad
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/Kconfig
@@ -0,0 +1,149 @@
+config ATH6K_LEGACY
+	tristate "Atheros AR600x support (non mac80211)"
+	depends on MMC
+	depends on WLAN_80211
+	help
+	This module adds support for wireless adapters based on Atheros AR600x chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl.
+
+choice
+	prompt "AR600x Board Data Configuration"
+	depends on ATH6K_LEGACY
+	default AR600x_SD31_XXX
+	help
+	Select the appropriate board data template from the list below that matches your AR600x based reference design.
+
+config AR600x_SD31_XXX
+	bool "SD31-xxx"
+	help
+        Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
+
+config AR600x_WB31_XXX
+	bool "WB31-xxx"
+	help
+        Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
+
+config AR600x_SD32_XXX
+	bool "SD32-xxx"
+	help
+        Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
+
+config AR600x_CUSTOM_XXX
+	bool "CUSTOM-xxx"
+	help
+        Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
+endchoice
+
+config ATH6KL_ENABLE_COEXISTENCE
+	bool "BT Coexistence support"
+	depends on ATH6K_LEGACY
+	help
+	Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
+
+choice
+	prompt "Front-End Antenna Configuration"
+	depends on ATH6KL_ENABLE_COEXISTENCE
+	default AR600x_DUAL_ANTENNA
+	help
+	Select the appropriate configuration from the list below that matches your AR600x based reference design.
+
+config AR600x_DUAL_ANTENNA
+	bool "Dual Antenna"
+	help
+        Dual Antenna Design
+
+config AR600x_SINGLE_ANTENNA
+	bool "Single Antenna"
+	help
+        Single Antenna Design
+endchoice
+
+choice
+	prompt "Collocated Bluetooth Type"
+	depends on ATH6KL_ENABLE_COEXISTENCE
+	default AR600x_BT_AR3001
+	help
+	Select the appropriate configuration from the list below that matches your AR600x based reference design.
+
+config AR600x_BT_QCOM
+	bool "Qualcomm BTS4020X"
+	help
+        Qualcomm BT (3 Wire PTA)
+
+config AR600x_BT_CSR
+	bool "CSR BC06"
+	help
+        CSR BT (3 Wire PTA)
+
+config AR600x_BT_AR3001
+	bool "Atheros AR3001"
+	help
+        Atheros BT (3 Wire PTA)
+endchoice
+
+config ATH6KL_HCI_BRIDGE
+	bool "HCI over SDIO support"
+	depends on ATH6K_LEGACY
+	help
+	Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
+
+config ATH6KL_CONFIG_GPIO_BT_RESET
+	bool "Configure BT Reset GPIO"
+	depends on ATH6KL_HCI_BRIDGE
+	help
+	Configure a WLAN GPIO for use with BT.
+
+config AR600x_BT_RESET_PIN
+	int "GPIO"
+	depends on ATH6KL_CONFIG_GPIO_BT_RESET
+	default 22
+	help
+	WLAN GPIO to be used for resetting BT
+
+config ATH6KL_CFG80211
+	bool "CFG80211 support"
+	depends on ATH6K_LEGACY
+	help
+	Enables support for CFG80211 APIs
+
+config ATH6KL_HTC_RAW_INTERFACE
+	bool "RAW HTC support"
+	depends on ATH6K_LEGACY
+	help
+	Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
+
+config ATH6KL_VIRTUAL_SCATTER_GATHER
+	bool "Virtual Scatter-Gather support"
+	depends on ATH6K_LEGACY
+	help
+	Enables virtual scatter gather support for the hardware that does not support it natively.
+
+config ATH6KL_DEBUG
+	bool "Debug support"
+	depends on ATH6K_LEGACY
+	help
+	Enables debug support
+
+config ATH6KL_ENABLE_HOST_DEBUG
+	bool "Host Debug support"
+	depends on ATH6KL_DEBUG
+	help
+	Enables debug support in the driver
+
+config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+	bool "Target Debug support - Enable UART prints"
+	depends on ATH6KL_DEBUG
+	help
+	Enables uart prints
+
+config AR600x_DEBUG_UART_TX_PIN
+	int "GPIO"
+	depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+	default 8
+	help
+	WLAN GPIO to be used for Debug UART (Tx)
+
+config ATH6KL_DISABLE_TARGET_DBGLOGS
+	bool "Target Debug support - Disable Debug logs"
+	depends on ATH6KL_DEBUG
+	help
+	Enables debug logs
diff --git a/drivers/net/wireless/ath6kl/Makefile b/drivers/net/wireless/ath6kl/Makefile
new file mode 100644
index 000000000000..b839dc5c54c5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/Makefile
@@ -0,0 +1,138 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2010 Atheros Corporation.  All rights reserved.
+#
+# $ATH_LICENSE_HOSTSDK0_C$
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+
+ccflags-y += -I$(obj)/include
+ccflags-y += -I$(obj)/wlan/include
+ccflags-y += -I$(obj)/os/linux/include
+ccflags-y += -I$(obj)/os
+ccflags-y += -I$(obj)/bmi/include
+ccflags-y += -I$(obj)/include/AR6002/hw4.0
+
+ifeq ($(CONFIG_AR600x_SD31_XXX),y)
+ccflags-y += -DAR600x_SD31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_WB31_XXX),y)
+ccflags-y += -DAR600x_WB31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_SD32_XXX),y)
+ccflags-y += -DAR600x_SD32_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
+ccflags-y += -DAR600x_CUSTOM_XXX
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
+ccflags-y += -DENABLE_COEXISTENCE
+endif
+
+ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
+ccflags-y += -DAR600x_DUAL_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
+ccflags-y += -DAR600x_SINGLE_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_BT_QCOM),y)
+ccflags-y += -DAR600x_BT_QCOM
+endif
+
+ifeq ($(CONFIG_AR600x_BT_CSR),y)
+ccflags-y += -DAR600x_BT_CSR
+endif
+
+ifeq ($(CONFIG_AR600x_BT_AR3001),y)
+ccflags-y += -DAR600x_BT_AR3001
+endif
+
+ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
+ccflags-y += -DATH_AR6K_ENABLE_GMBOX
+ccflags-y += -DHCI_TRANSPORT_SDIO
+ccflags-y += -DSETUPHCI_ENABLED
+ccflags-y += -DSETUPBTDEV_ENABLED
+ath6kl-y += htc2/AR6000/ar6k_gmbox.o
+ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
+ath6kl-y += miscdrv/ar3kconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
+ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
+endif
+
+ifeq ($(CONFIG_ATH6KL_CFG80211),y)
+ccflags-y += -DATH6K_CONFIG_CFG80211
+ath6kl-y += os/linux/cfg80211.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
+ccflags-y += -DHTC_RAW_INTERFACE
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
+ccflags-y += -DDEBUG
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
+ccflags-y += -DENABLEUARTPRINT_SET
+endif
+
+ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
+ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
+endif
+
+ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
+ccflags-y += -DATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+endif
+
+ccflags-y += -DLINUX -DKERNEL_2_6
+ccflags-y += -DTCMD
+ccflags-y += -DSEND_EVENT_TO_APP
+ccflags-y += -DUSER_KEYS
+ccflags-y += -DNO_SYNC_FLUSH
+ccflags-y += -DHTC_EP_STAT_PROFILING
+ccflags-y += -DATH_AR6K_11N_SUPPORT
+ccflags-y += -DWAPI_ENABLE
+ccflags-y += -DCHECKSUM_OFFLOAD
+ccflags-y += -DWLAN_HEADERS
+ccflags-y += -DINIT_MODE_DRV_ENABLED
+ccflags-y += -DBMIENABLE_SET
+
+obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
+ath6kl-y += htc2/AR6000/ar6k.o
+ath6kl-y += htc2/AR6000/ar6k_events.o
+ath6kl-y += htc2/htc_send.o
+ath6kl-y += htc2/htc_recv.o
+ath6kl-y += htc2/htc_services.o
+ath6kl-y += htc2/htc.o
+ath6kl-y += bmi/src/bmi.o
+ath6kl-y += os/linux/ar6000_drv.o
+ath6kl-y += os/linux/ar6000_raw_if.o
+ath6kl-y += os/linux/netbuf.o
+ath6kl-y += os/linux/wireless_ext.o
+ath6kl-y += os/linux/ioctl.o
+ath6kl-y += os/linux/hci_bridge.o
+ath6kl-y += miscdrv/common_drv.o
+ath6kl-y += miscdrv/credit_dist.o
+ath6kl-y += wmi/wmi.o
+ath6kl-y += reorder/rcv_aggr.o
+ath6kl-y += wlan/src/wlan_node.o
+ath6kl-y += wlan/src/wlan_recv_beacon.o
+ath6kl-y += wlan/src/wlan_utils.o
+
+# ATH_HIF_TYPE := sdio
+ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
+ccflags-y += -DSDIO
+ath6kl-y += hif/sdio/linux_sdio/src/hif.o
+ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o
diff --git a/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h
new file mode 100644
index 000000000000..729e3a6ac54d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h
@@ -0,0 +1,51 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi_internal.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef BMI_INTERNAL_H
+#define BMI_INTERNAL_H
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME bmi
+#include "a_debug.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "bmi_msg.h"
+
+#define ATH_DEBUG_BMI  ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+
+#define BMI_COMMUNICATION_TIMEOUT       100000
+
+/* ------ Global Variable Declarations ------- */
+A_BOOL bmiDone;
+
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+              A_UCHAR *buffer,
+              A_UINT32 length);
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+                 A_UCHAR *buffer,
+                 A_UINT32 length,
+                 A_BOOL want_timeout);
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/bmi/src/bmi.c b/drivers/net/wireless/ath6kl/bmi/src/bmi.c
new file mode 100644
index 000000000000..4fe280a06478
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/src/bmi.c
@@ -0,0 +1,984 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#include "hif.h"
+#include "bmi.h"
+#include "htc_api.h"
+#include "bmi_internal.h"
+
+#ifdef DEBUG
+static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+    { ATH_DEBUG_BMI , "BMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+                                 "bmi",
+                                 "Boot Manager Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+                                 bmi_debug_desc);
+                                 
+#endif
+
+/*
+Although we had envisioned BMI to run on top of HTC, this is not how the
+final implementation ended up. On the Target side, BMI is a part of the BSP
+and does not use the HTC protocol nor even DMA -- it is intentionally kept
+very simple.
+*/
+
+static A_BOOL pendingEventsFuncCheck = FALSE; 
+static A_UINT32 *pBMICmdCredits;
+static A_UCHAR *pBMICmdBuf;
+#define MAX_BMI_CMDBUF_SZ (BMI_DATASZ_MAX + \
+                       sizeof(A_UINT32) /* cmd */ + \
+                       sizeof(A_UINT32) /* addr */ + \
+                       sizeof(A_UINT32))/* length */
+#define BMI_COMMAND_FITS(sz) ((sz) <= MAX_BMI_CMDBUF_SZ)
+    
+/* APIs visible to the driver */
+void
+BMIInit(void)
+{
+    bmiDone = FALSE;
+    pendingEventsFuncCheck = FALSE;
+
+    /*
+     * On some platforms, it's not possible to DMA to a static variable
+     * in a device driver (e.g. Linux loadable driver module).
+     * So we need to A_MALLOC space for "command credits" and for commands.
+     *
+     * Note: implicitly relies on A_MALLOC to provide a buffer that is
+     * suitable for DMA (or PIO).  This buffer will be passed down the
+     * bus stack.
+     */
+    if (!pBMICmdCredits) {
+        pBMICmdCredits = (A_UINT32 *)A_MALLOC_NOWAIT(4);
+        A_ASSERT(pBMICmdCredits);
+    }
+
+    if (!pBMICmdBuf) {
+        pBMICmdBuf = (A_UCHAR *)A_MALLOC_NOWAIT(MAX_BMI_CMDBUF_SZ);
+        A_ASSERT(pBMICmdBuf);
+    }
+    
+    A_REGISTER_MODULE_DEBUG_INFO(bmi);
+}
+
+A_STATUS
+BMIDone(HIF_DEVICE *device)
+{
+    A_STATUS status;
+    A_UINT32 cid;
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
+        return A_OK;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
+    bmiDone = TRUE;
+    cid = BMI_DONE;
+
+    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    if (pBMICmdCredits) {
+        A_FREE(pBMICmdCredits);
+        pBMICmdCredits = NULL;
+    }
+
+    if (pBMICmdBuf) {
+        A_FREE(pBMICmdBuf);
+        pBMICmdBuf = NULL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
+{
+    A_STATUS status;
+    A_UINT32 cid;
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
+    cid = BMI_GET_TARGET_INFO;
+
+    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
+                                                sizeof(targ_info->target_ver), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
+        return A_ERROR;
+    }
+
+    if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
+        /* Determine how many bytes are in the Target's targ_info */
+        status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
+                                            sizeof(targ_info->target_info_byte_count), TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
+            return A_ERROR;
+        }
+
+        /*
+         * The Target's targ_info doesn't match the Host's targ_info.
+         * We need to do some backwards compatibility work to make this OK.
+         */
+        A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
+
+        /* Read the remainder of the targ_info */
+        status = bmiBufferReceive(device,
+                        ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
+                        sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
+                        					targ_info->target_info_byte_count));
+            return A_ERROR;
+        }
+    } else {
+        /*
+         * Target must be an AR6001 whose firmware does not
+         * support BMI_GET_TARGET_INFO.  Construct the data
+         * that it would have sent.
+         */
+        targ_info->target_info_byte_count=sizeof(*targ_info);
+        targ_info->target_type=TARGET_TYPE_AR6001;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
+        							targ_info->target_ver, targ_info->target_type));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+              A_UINT32 address,
+              A_UCHAR *buffer,
+              A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, rxlen;
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       			("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+        			device, address, length));
+
+    cid = BMI_READ_MEMORY;
+
+    remaining = length;
+
+    while (remaining)
+    {
+        rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+        offset += sizeof(address);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &rxlen, sizeof(rxlen));
+        offset += sizeof(length);
+
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        status = bmiBufferReceive(device, pBMICmdBuf, rxlen, TRUE);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+            return A_ERROR;
+        }
+        A_MEMCPY(&buffer[length - remaining], pBMICmdBuf, rxlen);
+        remaining -= rxlen; address += rxlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+               A_UINT32 address,
+               A_UCHAR *buffer,
+               A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, txlen;
+    const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
+    
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + header));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + header);
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+         device, address, length));
+
+    cid = BMI_WRITE_MEMORY;
+
+    remaining = length;
+    while (remaining)
+    {
+        txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+                                       remaining : (BMI_DATASZ_MAX - header);
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+        offset += sizeof(address);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+        offset += sizeof(txlen);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen);
+        offset += txlen;
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        remaining -= txlen; address += txlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+           A_UINT32 address,
+           A_UINT32 *param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+        device, address, *param));
+
+    cid = BMI_EXECUTE;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    A_MEMCPY(&(pBMICmdBuf[offset]), param, sizeof(*param));
+    offset += sizeof(*param);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), FALSE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+
+    A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
+    return A_OK;
+}
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+               A_UINT32 address)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
+        device, address));
+
+    cid = BMI_SET_APP_START;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+                   A_UINT32 address,
+                   A_UINT32 *param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+       ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
+       device, address));
+
+    cid = BMI_READ_SOC_REGISTER;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+    A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
+    return A_OK;
+}
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+                    A_UINT32 address,
+                    A_UINT32 param)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+     ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+     device, address, param));
+
+    cid = BMI_WRITE_SOC_REGISTER;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &param, sizeof(param));
+    offset += sizeof(param);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+                   A_UINT32 ROM_addr,
+                   A_UINT32 RAM_addr,
+                   A_UINT32 nbytes,
+                   A_UINT32 do_activate,
+                   A_UINT32 *rompatch_id)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+				sizeof(nbytes) + sizeof(do_activate)));
+    memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+			sizeof(nbytes) + sizeof(do_activate));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
+         device, ROM_addr, RAM_addr, nbytes, do_activate));
+
+    cid = BMI_ROMPATCH_INSTALL;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &ROM_addr, sizeof(ROM_addr));
+    offset += sizeof(ROM_addr);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &RAM_addr, sizeof(RAM_addr));
+    offset += sizeof(RAM_addr);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &nbytes, sizeof(nbytes));
+    offset += sizeof(nbytes);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &do_activate, sizeof(do_activate));
+    offset += sizeof(do_activate);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*rompatch_id), TRUE);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+        return A_ERROR;
+    }
+    A_MEMCPY(rompatch_id, pBMICmdBuf, sizeof(*rompatch_id));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+                     A_UINT32 rompatch_id)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(rompatch_id)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(rompatch_id));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
+         								 device, rompatch_id));
+
+    cid = BMI_ROMPATCH_UNINSTALL;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_id, sizeof(rompatch_id));
+    offset += sizeof(rompatch_id);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
+    return A_OK;
+}
+
+static A_STATUS
+_BMIrompatchChangeActivation(HIF_DEVICE *device,
+                             A_UINT32 rompatch_count,
+                             A_UINT32 *rompatch_list,
+                             A_UINT32 do_activate)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 length;
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)));
+    memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
+           device, rompatch_count));
+
+    cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
+
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_count, sizeof(rompatch_count));
+    offset += sizeof(rompatch_count);
+    length = rompatch_count * sizeof(*rompatch_list);
+    A_MEMCPY(&(pBMICmdBuf[offset]), rompatch_list, length);
+    offset += length;
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+                    A_UINT32 rompatch_count,
+                    A_UINT32 *rompatch_list)
+{
+    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
+}
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+                      A_UINT32 rompatch_count,
+                      A_UINT32 *rompatch_list)
+{
+    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
+}
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+          A_UCHAR *buffer,
+          A_UINT32 length)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+    A_UINT32 remaining, txlen;
+    const A_UINT32 header = sizeof(cid) + sizeof(length);
+
+    A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX+header));
+    memset (pBMICmdBuf, 0, BMI_DATASZ_MAX+header);
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n",
+         device, length));
+
+    cid = BMI_LZ_DATA;
+
+    remaining = length;
+    while (remaining)
+    {
+        txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+                                       remaining : (BMI_DATASZ_MAX - header);
+        offset = 0;
+        A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+        offset += sizeof(cid);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+        offset += sizeof(txlen);
+        A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen);
+        offset += txlen;
+        status = bmiBufferSend(device, pBMICmdBuf, offset);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+            return A_ERROR;
+        }
+        remaining -= txlen;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n"));
+
+    return A_OK;
+}
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+                 A_UINT32 address)
+{
+    A_UINT32 cid;
+    A_STATUS status;
+    A_UINT32 offset;
+
+    A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+    memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+    if (bmiDone) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+         ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n",
+         device, address));
+
+    cid = BMI_LZ_STREAM_START;
+    offset = 0;
+    A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+    offset += sizeof(cid);
+    A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+    offset += sizeof(address);
+    status = bmiBufferSend(device, pBMICmdBuf, offset);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n"));
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n"));
+
+    return A_OK;
+}
+
+/* BMI Access routines */
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+              A_UCHAR *buffer,
+              A_UINT32 length)
+{
+    A_STATUS status;
+    A_UINT32 timeout;
+    A_UINT32 address;
+    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+
+    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+                       &mboxAddress[0], sizeof(mboxAddress));
+
+    *pBMICmdCredits = 0;
+    timeout = BMI_COMMUNICATION_TIMEOUT;
+
+    while(timeout-- && !(*pBMICmdCredits)) {
+        /* Read the counter register to get the command credits */
+        address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
+        /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
+         * a decrement, while the remaining 3 bytes has no effect.  The rationale behind this is to
+         * make all HIF accesses 4-byte aligned */
+        status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, 4,
+            HIF_RD_SYNC_BYTE_INC, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
+            return A_ERROR;
+        }
+        /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
+        (*pBMICmdCredits) &= 0xFF;
+    }
+
+    if (*pBMICmdCredits) {
+        address = mboxAddress[ENDPOINT1];
+        status = HIFReadWrite(device, address, buffer, length,
+            HIF_WR_SYNC_BYTE_INC, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
+            return A_ERROR;
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n"));
+        return A_ERROR;
+    }
+
+    return status;
+}
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+                 A_UCHAR *buffer,
+                 A_UINT32 length,
+                 A_BOOL want_timeout)
+{
+    A_STATUS status;
+    A_UINT32 address;
+    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+    HIF_PENDING_EVENTS_INFO     hifPendingEvents;
+    static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL;
+    
+    if (!pendingEventsFuncCheck) {
+            /* see if the HIF layer implements an alternative function to get pending events
+             * do this only once! */
+        HIFConfigureDevice(device,
+                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+                           &getPendingEventsFunc,
+                           sizeof(getPendingEventsFunc));
+        pendingEventsFuncCheck = TRUE;
+    }
+                       
+    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+                       &mboxAddress[0], sizeof(mboxAddress));
+
+    /*
+     * During normal bootup, small reads may be required.
+     * Rather than issue an HIF Read and then wait as the Target
+     * adds successive bytes to the FIFO, we wait here until
+     * we know that response data is available.
+     *
+     * This allows us to cleanly timeout on an unexpected
+     * Target failure rather than risk problems at the HIF level.  In
+     * particular, this avoids SDIO timeouts and possibly garbage
+     * data on some host controllers.  And on an interconnect
+     * such as Compact Flash (as well as some SDIO masters) which
+     * does not provide any indication on data timeout, it avoids
+     * a potential hang or garbage response.
+     *
+     * Synchronization is more difficult for reads larger than the
+     * size of the MBOX FIFO (128B), because the Target is unable
+     * to push the 129th byte of data until AFTER the Host posts an
+     * HIF Read and removes some FIFO data.  So for large reads the
+     * Host proceeds to post an HIF Read BEFORE all the data is
+     * actually available to read.  Fortunately, large BMI reads do
+     * not occur in practice -- they're supported for debug/development.
+     *
+     * So Host/Target BMI synchronization is divided into these cases:
+     *  CASE 1: length < 4
+     *        Should not happen
+     *
+     *  CASE 2: 4 <= length <= 128
+     *        Wait for first 4 bytes to be in FIFO
+     *        If CONSERVATIVE_BMI_READ is enabled, also wait for
+     *        a BMI command credit, which indicates that the ENTIRE
+     *        response is available in the the FIFO
+     *
+     *  CASE 3: length > 128
+     *        Wait for the first 4 bytes to be in FIFO
+     *
+     * For most uses, a small timeout should be sufficient and we will
+     * usually see a response quickly; but there may be some unusual
+     * (debug) cases of BMI_EXECUTE where we want an larger timeout.
+     * For now, we use an unbounded busy loop while waiting for
+     * BMI_EXECUTE.
+     *
+     * If BMI_EXECUTE ever needs to support longer-latency execution,
+     * especially in production, this code needs to be enhanced to sleep
+     * and yield.  Also note that BMI_COMMUNICATION_TIMEOUT is currently
+     * a function of Host processor speed.
+     */
+    if (length >= 4) { /* NB: Currently, always true */
+        /*
+         * NB: word_available is declared static for esoteric reasons
+         * having to do with protection on some OSes.
+         */
+        static A_UINT32 word_available;
+        A_UINT32 timeout;
+
+        word_available = 0;
+        timeout = BMI_COMMUNICATION_TIMEOUT;
+        while((!want_timeout || timeout--) && !word_available) {
+            
+            if (getPendingEventsFunc != NULL) {
+                status = getPendingEventsFunc(device,
+                                              &hifPendingEvents,
+                                              NULL);
+                if (status != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n"));
+                    break;
+                }
+  
+                if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) {
+                    word_available = 1;    
+                }
+                continue;    
+            }
+            
+            status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available,
+                sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n"));
+                return A_ERROR;
+            }
+            /* We did a 4-byte read to the same register; all we really want is one bit */ 
+            word_available &= (1 << ENDPOINT1);
+        }
+
+        if (!word_available) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n"));
+            return A_ERROR;
+        }
+    }
+
+#define CONSERVATIVE_BMI_READ 0
+#if CONSERVATIVE_BMI_READ
+    /*
+     * This is an extra-conservative CREDIT check.  It guarantees
+     * that ALL data is available in the FIFO before we start to
+     * read from the interconnect.
+     *
+     * This credit check is useless when firmware chooses to
+     * allow multiple outstanding BMI Command Credits, since the next
+     * credit will already be present.  To restrict the Target to one
+     * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT.
+     *
+     * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set)
+     * we cannot wait for the next credit because the Target's FIFO
+     * will not hold the entire response.  So we need the Host to
+     * start to empty the FIFO sooner.  (And again, large reads are
+     * not used in practice; they are for debug/development only.)
+     *
+     * For a more conservative Host implementation (which would be
+     * safer for a Compact Flash interconnect):
+     *   Set CONSERVATIVE_BMI_READ (above) to 1
+     *   Set HI_OPTION_BMI_CRED_LIMIT and
+     *   reduce BMI_DATASZ_MAX to 32 or 64
+     */
+    if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */
+        A_UINT32 timeout;
+
+        *pBMICmdCredits = 0;
+        timeout = BMI_COMMUNICATION_TIMEOUT;
+        while((!want_timeout || timeout--) && !(*pBMICmdCredits) {
+            /* Read the counter register to get the command credits */
+            address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
+            /* read the counter using a 4-byte read.  Since the counter is NOT auto-decrementing,
+             * we can read this counter multiple times using a non-incrementing address mode.
+             * The rationale here is to make all HIF accesses a multiple of 4 bytes */
+            status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, sizeof(*pBMICmdCredits),
+                HIF_RD_SYNC_BYTE_FIX, NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
+                return A_ERROR;
+            }
+                /* we did a 4-byte read to the same count register so mask off upper bytes */
+            (*pBMICmdCredits) &= 0xFF;
+        }
+
+        if (!(*pBMICmdCredits)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout- bmiBufferReceive no credit\n"));
+            return A_ERROR;
+        }
+    }
+#endif
+
+    address = mboxAddress[ENDPOINT1];
+    status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device, A_UINT32 address, A_UCHAR *buffer, A_UINT32 length)
+{
+    A_STATUS status = A_ERROR;
+    A_UINT32  lastWord = 0;
+    A_UINT32  lastWordOffset = length & ~0x3;
+    A_UINT32  unalignedBytes = length & 0x3;
+
+    status = BMILZStreamStart (device, address);
+    if (A_FAILED(status)) {
+            return A_ERROR;
+    }
+
+    if (unalignedBytes) {
+            /* copy the last word into a zero padded buffer */
+        A_MEMCPY(&lastWord, &buffer[lastWordOffset], unalignedBytes);
+    }
+
+    status = BMILZData(device, buffer, lastWordOffset);
+
+    if (A_FAILED(status)) {
+        return A_ERROR;
+    }
+
+    if (unalignedBytes) {
+        status = BMILZData(device, (A_UINT8 *)&lastWord, 4);
+    }
+
+    if (A_SUCCESS(status)) {
+        //
+        // Close compressed stream and open a new (fake) one.  This serves mainly to flush Target caches.
+        //
+        status = BMILZStreamStart (device, 0x00);
+        if (A_FAILED(status)) {
+           return A_ERROR;
+        }
+    }
+	return status;
+}
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length)
+{
+    return bmiBufferSend(device, buffer, length);
+}
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length, A_BOOL want_timeout)
+{
+    return bmiBufferReceive(device, buffer, length, want_timeout);
+}
diff --git a/drivers/net/wireless/ath6kl/bmi/src/makefile b/drivers/net/wireless/ath6kl/bmi/src/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/src/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h
new file mode 100644
index 000000000000..78d29ca14dc2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h
@@ -0,0 +1,88 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_sdio_common.h" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// common header file for HIF modules designed for SDIO
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef HIF_SDIO_COMMON_H_
+#define HIF_SDIO_COMMON_H_
+
+    /* SDIO manufacturer ID and Codes */
+#define MANUFACTURER_ID_AR6001_BASE        0x100
+#define MANUFACTURER_ID_AR6002_BASE        0x200
+#define MANUFACTURER_ID_AR6003_BASE        0x300
+#define MANUFACTURER_ID_AR6K_BASE_MASK     0xFF00
+#define FUNCTION_CLASS                     0x0
+#define MANUFACTURER_CODE                  0x271    /* Atheros */
+
+    /* Mailbox address in SDIO address space */
+#define HIF_MBOX_BASE_ADDR                 0x800
+#define HIF_MBOX_WIDTH                     0x800
+#define HIF_MBOX_START_ADDR(mbox)               \
+   ( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
+
+#define HIF_MBOX_END_ADDR(mbox)                 \
+    (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
+
+    /* extended MBOX address for larger MBOX writes to MBOX 0*/
+#define HIF_MBOX0_EXTENDED_BASE_ADDR       0x2800
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6002    (6*1024)           
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003    (18*1024)   
+
+    /* version 1 of the chip has only a 12K extended mbox range */
+#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1  0x4000
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1      (12*1024)  
+
+    /* GMBOX addresses */
+#define HIF_GMBOX_BASE_ADDR                0x7000
+#define HIF_GMBOX_WIDTH                    0x4000
+
+    /* for SDIO we recommend a 128-byte block size */
+#define HIF_DEFAULT_IO_BLOCK_SIZE          128
+
+    /* set extended MBOX window information for SDIO interconnects */
+static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_INFO *pInfo)
+{
+    switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {                   
+        case MANUFACTURER_ID_AR6001_BASE :
+            /* no extended MBOX */
+            break;
+        case MANUFACTURER_ID_AR6002_BASE :
+                /* MBOX 0 has an extended range */
+            pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;             
+            pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
+            break;
+        case MANUFACTURER_ID_AR6003_BASE :
+                /* MBOX 0 has an extended range */
+            pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;             
+            pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
+            pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
+            pInfo->GMboxSize = HIF_GMBOX_WIDTH;
+            break;
+        default:
+            A_ASSERT(FALSE);
+            break;
+    }
+}
+             
+/* special CCCR (func 0) registers */
+
+#define CCCR_SDIO_IRQ_MODE_REG         0xF0        /* interrupt mode register */
+#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ   (1 << 0)    /* mode to enable special 4-bit interrupt assertion without clock*/ 
+                        
+#endif /*HIF_SDIO_COMMON_H_*/
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/Makefile b/drivers/net/wireless/ath6kl/hif/sdio/Makefile
new file mode 100644
index 000000000000..6f282bb8ad5f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/Makefile
@@ -0,0 +1,86 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2008 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+
+#
+#SDIO HIF makefile for atheros SDIO stack
+#  
+
+# Check for SDIO stack
+ifdef ATH_SDIO_STACK_BASE
+# Someone already set it on entry, the stack resides outside this tree, we will try to build it
+_SDIO_STACK = YES
+else
+# Check for SDIO stack within this tree
+_SDIO_STACK = $(shell if [ -f $(ATH_SRC_BASE)/sdiostack/src/Makefile ]; then echo "YES"; else echo "NO"; fi)
+
+ifeq ($(_SDIO_STACK), YES)
+    # SDIO stack is part of the kit and will need to be compiled
+ATH_SDIO_STACK_BASE := $(ATH_SRC_BASE)/sdiostack
+endif
+endif 
+
+
+ifeq ($(ATH_BUS_SUBTYPE),linux_sdio)
+_HIF_SUB_TYPE = linux_sdio
+_SDIO_STACK = NO
+else
+_HIF_SUB_TYPE = linux_athsdio
+endif
+
+
+ifeq ($(_SDIO_STACK), YES)
+    # Pass and translate build variables to the SDIO stack makefile
+_SDIO_STACK_MAKE_PARAMS := CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \
+                           CT_OS_TYPE=linux \
+                           CT_OS_SUB_TYPE=$(ATH_OS_SUB_TYPE) \
+                           CT_LINUXPATH=$(ATH_LINUXPATH) \
+                           CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \
+                           CT_CROSS_COMPILE_TYPE=$(ATH_CROSS_COMPILE_TYPE) \
+                           CT_ARCH_CPU_TYPE=$(ATH_ARCH_CPU_TYPE) \
+                           CT_HC_DRIVERS=$(ATH_HC_DRIVERS) \
+                           CT_MAKE_INCLUDE_OVERRIDE=$(_LOCALMAKE_INCLUDE)   \
+                           CT_BUILD_OUTPUT_OVERRIDE=$(COMPILED_IMAGE_OBJECTS_PATH) \
+                           BUS_BUILD=1
+endif
+EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/hif/sdio/$(_HIF_SUB_TYPE)/include
+EXTRA_CFLAGS += -DSDIO
+EXTRA_CFLAGS += -I$(ATH_SDIO_STACK_BASE)/src/include
+
+ifeq ($(ATH_OS_SUB_TYPE),linux_2_4)
+obj-y += ../../hif/sdio/linux_athsdio/src/hif.o
+obj-y += ../../hif/sdio/linux_athsdio/src/hif_scatter.o
+endif
+
+ifneq ($(ATH_OS_SUB_TYPE),linux_2_4)
+ar6000-objs := ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif.o \
+			   ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif_scatter.o
+
+
+endif
+
+all:
+ifeq ($(_SDIO_STACK),YES)
+	$(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C  $(ATH_SDIO_STACK_BASE)/src default
+	-cp -f $(ATH_SDIO_STACK_BASE)/src/Module.symvers $(COMPILED_IMAGE_OBJECTS_PATH)
+endif
+
+clean:
+ifeq ($(_SDIO_STACK),YES)
+	$(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C $(ATH_SDIO_STACK_BASE)/src clean
+endif
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
new file mode 100644
index 000000000000..e0155a58ec9a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
@@ -0,0 +1,128 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_internal.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// internal header file for hif layer
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_INTERNAL_H_
+#define _HIF_INTERNAL_H_
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "../../../common/hif_sdio_common.h"
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)   
+#include <linux/scatterlist.h>
+#define HIF_LINUX_MMC_SCATTER_SUPPORT
+#endif
+
+#define BUS_REQUEST_MAX_NUM                64
+
+#define SDIO_CLOCK_FREQUENCY_DEFAULT       25000000
+#define SDWLAN_ENABLE_DISABLE_TIMEOUT      20
+#define FLAGS_CARD_ENAB                    0x02
+#define FLAGS_CARD_IRQ_UNMSK               0x04
+
+#define HIF_MBOX_BLOCK_SIZE                HIF_DEFAULT_IO_BLOCK_SIZE
+#define HIF_MBOX0_BLOCK_SIZE               1
+#define HIF_MBOX1_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX2_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX3_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
+
+struct _HIF_SCATTER_REQ_PRIV;
+
+typedef struct bus_request {
+    struct bus_request *next;       /* link list of available requests */
+    struct bus_request *inusenext;  /* link list of in use requests */
+    struct semaphore sem_req;
+    A_UINT32 address;               /* request data */
+    A_UCHAR *buffer;
+    A_UINT32 length;
+    A_UINT32 request;
+    void *context;
+    A_STATUS status;
+    struct _HIF_SCATTER_REQ_PRIV *pScatterReq;      /* this request is a scatter request */
+} BUS_REQUEST;
+
+struct hif_device {
+    struct sdio_func *func;
+    spinlock_t asynclock;
+    struct task_struct* async_task;             /* task to handle async commands */
+    struct semaphore sem_async;                 /* wake up for async task */
+    int    async_shutdown;                      /* stop the async task */
+    struct completion async_completion;          /* thread completion */
+    BUS_REQUEST   *asyncreq;                    /* request for async tasklet */
+    BUS_REQUEST *taskreq;                       /*  async tasklet data */
+    spinlock_t lock;
+    BUS_REQUEST *s_busRequestFreeQueue;         /* free list */
+    BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
+    void     *claimedContext;
+    HTC_CALLBACKS htcCallbacks;
+    A_UINT8     *dma_buffer;
+    DL_LIST      ScatterReqHead;                /* scatter request list head */
+    A_BOOL       scatter_enabled;               /* scatter enabled flag */
+    A_BOOL   is_suspend;
+};
+
+#define HIF_DMA_BUFFER_SIZE (32 * 1024)
+#define CMD53_FIXED_ADDRESS 1
+#define CMD53_INCR_ADDRESS  2
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device);
+void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define MAX_SCATTER_REQUESTS             4
+#define MAX_SCATTER_ENTRIES_PER_REQ      16
+#define MAX_SCATTER_REQ_TRANSFER_SIZE    32*1024
+
+typedef struct _HIF_SCATTER_REQ_PRIV {
+    HIF_SCATTER_REQ     *pHifScatterReq;  /* HIF scatter request with allocated entries */   
+    HIF_DEVICE          *device;          /* this device */
+    BUS_REQUEST         *busrequest;      /* request associated with request */
+        /* scatter list for linux */    
+    struct scatterlist  sgentries[MAX_SCATTER_ENTRIES_PER_REQ];   
+} HIF_SCATTER_REQ_PRIV;
+
+#define ATH_DEBUG_SCATTER  ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo);
+void CleanupHIFScatterResources(HIF_DEVICE *device);
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#else  // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+static inline A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo) 
+{
+    return A_ENOTSUP;
+}
+
+static inline A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest) 
+{
+    return A_ENOTSUP;
+}
+
+#define CleanupHIFScatterResources(d) { }
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#endif // _HIF_INTERNAL_H_
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt
new file mode 100644
index 000000000000..0c98fd89a343
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt
@@ -0,0 +1,35 @@
+HIF support for native Linux MMC Stack.
+paull@atheros.com
+
+11/6/09
+Added patches for the MMC stacks Standard Host Controller for 2.6.30 and 2.6.32
+Patches enable ENE board support and speed up transfers for any Standard Host Controller
+linux2.6.30_mmc_std_host.patch
+linuxMMC_std_host_2.6.32-rc5sdio.patch
+
+
+2/18/2009
+Added patch for Freescale MX35 SD host driver. tested with SD25 AR6102 Olca 2.1.2
+
+12/18/2008
+Tested on Freescale MX27 and OMAP3530 Beageleboard Linux ver 2.6.28
+adds DMA bounce buffer support
+hif.c ver 5 and hif.h ver 4 are for the old HTC/HIF interface and shouold be useable with 2.1 drivers
+ver 6 and 5 are for the new HTC/HIF interface
+For older Linux MMC stack versions, comment out in hif.c hifDeviceInserted() the lines:
+    /* give us some time to enable, in ms */
+    func->enable_timeout = 100;
+it is only required on some platforms, eg Beagleboard.
+
+7/18/2008
+
+a. tested on Fedora Core 9 kernel 2.6.25.6, x86 with ENE standrad host controller,using the Olca 2.1.1RC.15
+b. requires applying the linux2.6.25.6mmc.patch to the kernel drivers/mmc directory
+c. through put is 20-22mbs up/down link
+d. new platform type is:
+	ATH_PLATFORM=LOCAL_i686_NATIVEMMC-SDIO
+	TARGET_TYPE=AR6002
+e. known issues: unloading the driver on Fedora Core 9 after conecting to an AP seems to not be complete.
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c
new file mode 100644
index 000000000000..75becd04cc49
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c
@@ -0,0 +1,1010 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF layer reference implementation for Linux Native MMC stack
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <linux/mmc/card.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/kthread.h>
+
+/* by default setup a bounce buffer for the data packets, if the underlying host controller driver
+   does not use DMA you may be able to skip this step and save the memory allocation and transfer time */
+#define HIF_USE_DMA_BOUNCE_BUFFER 1
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+
+
+#if HIF_USE_DMA_BOUNCE_BUFFER
+/* macro to check if DMA buffer is WORD-aligned and DMA-able.  Most host controllers assume the
+ * buffer is DMA'able and will bug-check otherwise (i.e. buffers on the stack).  
+ * virt_addr_valid check fails on stack memory.  
+ */
+#define BUFFER_NEEDS_BOUNCE(buffer)  (((A_UINT32)(buffer) & 0x3) || !virt_addr_valid((buffer)))
+#else
+#define BUFFER_NEEDS_BOUNCE(buffer)   (FALSE)
+#endif
+
+/* ATHENV */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+#define dev_to_sdio_func(d)	container_of(d, struct sdio_func, dev)
+#define to_sdio_driver(d)      container_of(d, struct sdio_driver, drv)
+static int hifDeviceSuspend(struct device *dev);
+static int hifDeviceResume(struct device *dev);
+#endif /* CONFIG_PM */
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
+static void hifDeviceRemoved(struct sdio_func *func);
+static HIF_DEVICE *addHifDevice(struct sdio_func *func);
+static HIF_DEVICE *getHifDevice(struct sdio_func *func);
+static void delHifDevice(HIF_DEVICE * device);
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte);
+
+int reset_sdio_on_unload = 0;
+module_param(reset_sdio_on_unload, int, 0644);
+
+extern A_UINT32 nohifscattersupport;
+
+
+/* ------ Static Variables ------ */
+static const struct sdio_device_id ar6k_id_table[] = {
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))  },
+    {  SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))  },
+    { /* null */                                         },
+};
+MODULE_DEVICE_TABLE(sdio, ar6k_id_table);
+
+static struct sdio_driver ar6k_driver = {
+	.name = "ar6k_wlan",
+	.id_table = ar6k_id_table,
+	.probe = hifDeviceInserted,
+	.remove = hifDeviceRemoved,
+};
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+/* New suspend/resume based on linux-2.6.32
+ * Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch
+ * Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host
+     */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+static struct dev_pm_ops ar6k_device_pm_ops = {
+#else
+static struct pm_ops ar6k_device_pm_ops = {
+#endif 
+	.suspend = hifDeviceSuspend,
+	.resume = hifDeviceResume,
+};
+#endif /* CONFIG_PM */
+
+/* make sure we only unregister when registered. */
+static int registered = 0;
+
+OSDRV_CALLBACKS osdrvCallbacks;
+extern A_UINT32 onebitmode;
+extern A_UINT32 busspeedlow;
+extern A_UINT32 debughif;
+
+static void ResetAllCards(void);
+
+#ifdef DEBUG
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif,
+                                 "hif",
+                                 "(Linux MMC) Host Interconnect Framework",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 0,
+                                 NULL);
+                                 
+#endif
+
+
+/* ------ Functions ------ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks)
+{
+    int status;
+    AR_DEBUG_ASSERT(callbacks != NULL);
+
+    A_REGISTER_MODULE_DEBUG_INFO(hif);
+
+    /* store the callback handlers */
+    osdrvCallbacks = *callbacks;
+
+    /* Register with bus driver core */
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n"));
+    registered = 1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+    if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) {
+        ar6k_driver.drv.pm = &ar6k_device_pm_ops;
+    }
+#endif /* CONFIG_PM */
+    status = sdio_register_driver(&ar6k_driver);
+    AR_DEBUG_ASSERT(status==0);
+
+    if (status != 0) {
+        return A_ERROR;
+    }
+
+    return A_OK;
+
+}
+
+static A_STATUS
+__HIFReadWrite(HIF_DEVICE *device,
+             A_UINT32 address,
+             A_UCHAR *buffer,
+             A_UINT32 length,
+             A_UINT32 request,
+             void *context)
+{
+    A_UINT8 opcode;
+    A_STATUS    status = A_OK;
+    int     ret;
+    A_UINT8 *tbuffer;
+    A_BOOL   bounced = FALSE;
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p (addr:0x%X)\n", 
+                    device, buffer, address));
+
+    do {
+        if (request & HIF_EXTENDED_IO) {
+            //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n"));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid command type: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (request & HIF_BLOCK_BASIS) {
+            /* round to whole block length size */
+            length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Block mode (BlockLen: %d)\n",
+                            length));
+        } else if (request & HIF_BYTE_BASIS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Byte mode (BlockLen: %d)\n",
+                            length));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid data mode: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+#if 0
+        /* useful for checking register accesses */
+        if (length & 0x3) {
+            A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
+                                request & HIF_WRITE ? "write":"read", address, length);
+        }
+#endif
+
+        if (request & HIF_WRITE) {
+            if ((address >= HIF_MBOX_START_ADDR(0)) &&
+                (address <= HIF_MBOX_END_ADDR(3)))
+            {
+    
+                AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH);
+    
+                /*
+                 * Mailbox write. Adjust the address so that the last byte
+                 * falls on the EOM address.
+                 */
+                address += (HIF_MBOX_WIDTH - length);
+            }
+        }
+
+        if (request & HIF_FIXED_ADDRESS) {
+            opcode = CMD53_FIXED_ADDRESS;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address));
+        } else if (request & HIF_INCREMENTAL_ADDRESS) {
+            opcode = CMD53_INCR_ADDRESS;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid address mode: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (request & HIF_WRITE) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (BUFFER_NEEDS_BOUNCE(buffer)) {
+                AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+                tbuffer = device->dma_buffer;
+                    /* copy the write data to the dma buffer */
+                AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+                memcpy(tbuffer, buffer, length);
+                bounced = TRUE;
+            } else {
+                tbuffer = buffer;    
+            }
+#else
+	        tbuffer = buffer;
+#endif
+            if (opcode == CMD53_FIXED_ADDRESS) {
+                ret = sdio_writesb(device->func, address, tbuffer, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            } else {
+                ret = sdio_memcpy_toio(device->func, address, tbuffer, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            }
+        } else if (request & HIF_READ) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (BUFFER_NEEDS_BOUNCE(buffer)) {
+                AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+                AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+                tbuffer = device->dma_buffer;
+                bounced = TRUE;
+            } else {
+                tbuffer = buffer;    
+            }
+#else
+            tbuffer = buffer;
+#endif
+            if (opcode == CMD53_FIXED_ADDRESS) {
+                ret = sdio_readsb(device->func, tbuffer, address, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            } else {
+                ret = sdio_memcpy_fromio(device->func, tbuffer, address, length);
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n",
+						  ret, address, length, *(int *)tbuffer));
+            }
+#if HIF_USE_DMA_BOUNCE_BUFFER
+            if (bounced) {
+    	           /* copy the read data from the dma buffer */
+                memcpy(buffer, tbuffer, length);
+            }
+#endif
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid direction: 0x%08x\n", request));
+            status = A_EINVAL;
+            break;
+        }
+
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: SDIO bus operation failed! MMC stack returned : %d \n", ret));
+            status = A_ERROR;
+        }
+    } while (FALSE);
+
+    return status;
+}
+
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    unsigned long flags;
+    BUS_REQUEST *async;
+    BUS_REQUEST *active;
+    
+    spin_lock_irqsave(&device->asynclock, flags);
+    active = device->asyncreq;
+    if (active == NULL) {
+        device->asyncreq = busrequest;
+        device->asyncreq->inusenext = NULL;
+    } else {
+        for (async = device->asyncreq;
+             async != NULL;
+             async = async->inusenext) {
+             active =  async;
+        }
+        active->inusenext = busrequest;
+        busrequest->inusenext = NULL;
+    }
+    spin_unlock_irqrestore(&device->asynclock, flags);
+}
+
+
+/* queue a read/write request */
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+             A_UINT32 address,
+             A_UCHAR *buffer,
+             A_UINT32 length,
+             A_UINT32 request,
+             void *context)
+{
+    A_STATUS    status = A_OK;
+    BUS_REQUEST *busrequest;
+
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p addr:0x%X\n", device,address));
+
+    do {            
+        if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){
+            /* serialize all requests through the async thread */
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", 
+                        (request & HIF_ASYNCHRONOUS)?"Async":"Synch"));
+            busrequest = hifAllocateBusRequest(device);
+            if (busrequest == NULL) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, 
+                    ("AR6000: no async bus requests available (%s, addr:0x%X, len:%d) \n", 
+                        request & HIF_READ ? "READ":"WRITE", address, length));
+                return A_ERROR;
+            }
+            busrequest->address = address;
+            busrequest->buffer = buffer;
+            busrequest->length = length;
+            busrequest->request = request;
+            busrequest->context = context;
+            
+            AddToAsyncList(device, busrequest);
+            
+            if (request & HIF_SYNCHRONOUS) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest));
+
+                /* wait for completion */
+                up(&device->sem_async);
+                if (down_interruptible(&busrequest->sem_req) != 0) {
+                    /* interrupted, exit */
+                    return A_ERROR;
+                } else {
+                    A_STATUS status = busrequest->status;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", 
+						      (unsigned int)busrequest, busrequest->status));
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request));
+                    hifFreeBusRequest(device, busrequest);
+                    return status;
+                }
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest));
+                up(&device->sem_async);
+                return A_PENDING;
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request));
+            status = A_EINVAL;
+            break;
+        }
+    } while(0);
+
+    return status;
+}
+/* thread to serialize all requests, both sync and async */
+static int async_task(void *param)
+ {
+    HIF_DEVICE *device;
+    BUS_REQUEST *request;
+    A_STATUS status;
+    unsigned long flags;
+
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n"));
+    set_current_state(TASK_INTERRUPTIBLE);
+    while(!device->async_shutdown) {
+        /* wait for work */
+        if (down_interruptible(&device->sem_async) != 0) {
+            /* interrupted, exit */
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n"));
+            break;
+        }
+        if (device->async_shutdown) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n"));
+            break;
+        }
+        /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */
+        sdio_claim_host(device->func);
+        spin_lock_irqsave(&device->asynclock, flags);
+        /* pull the request to work on */
+        while (device->asyncreq != NULL) {
+            request = device->asyncreq;
+            if (request->inusenext != NULL) {
+                device->asyncreq = request->inusenext;
+            } else {
+                device->asyncreq = NULL;
+            }
+            spin_unlock_irqrestore(&device->asynclock, flags);
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request));
+            
+            if (request->pScatterReq != NULL) {
+                A_ASSERT(device->scatter_enabled);
+                    /* this is a queued scatter request, pass the request to scatter routine which
+                     * executes it synchronously, note, no need to free the request since scatter requests
+                     * are maintained on a separate list */
+                status = DoHifReadWriteScatter(device,request);
+            } else {                
+                    /* call HIFReadWrite in sync mode to do the work */
+                status = __HIFReadWrite(device, request->address, request->buffer,
+                                      request->length, request->request & ~HIF_SYNCHRONOUS, NULL);
+                if (request->request & HIF_ASYNCHRONOUS) {
+                    void *context = request->context;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request));
+                    hifFreeBusRequest(device, request);
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request));
+                    device->htcCallbacks.rwCompletionHandler(context, status);
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request));
+                    request->status = status;
+                    up(&request->sem_req);
+                }
+            }
+            spin_lock_irqsave(&device->asynclock, flags);
+        }
+        spin_unlock_irqrestore(&device->asynclock, flags);
+        sdio_release_host(device->func);
+    }
+
+    complete_and_exit(&device->async_completion, 0);
+    return 0;
+ }
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+                   void *config, A_UINT32 configLen)
+{
+    A_UINT32 count;
+    A_STATUS status;
+    
+    switch(opcode) {
+        case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
+            ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
+            ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
+            ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
+            ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
+            break;
+
+        case HIF_DEVICE_GET_MBOX_ADDR:
+            for (count = 0; count < 4; count ++) {
+                ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
+            }
+            
+            if (configLen >= sizeof(HIF_DEVICE_MBOX_INFO)) {    
+                SetExtendedMboxWindowInfo((A_UINT16)device->func->device,
+                                          (HIF_DEVICE_MBOX_INFO *)config);
+            }
+                        
+            break;
+        case HIF_DEVICE_GET_IRQ_PROC_MODE:
+            *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY;
+            break;
+       case HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT:
+            if (!device->scatter_enabled) {
+                return A_ENOTSUP;    
+            }
+            status = SetupHIFScatterSupport(device, (HIF_DEVICE_SCATTER_SUPPORT_INFO *)config);
+            if (A_FAILED(status)) {
+                device->scatter_enabled = FALSE;           
+            }
+            return status;
+        case HIF_DEVICE_GET_OS_DEVICE:
+                /* pass back a pointer to the SDIO function's "dev" struct */
+            ((HIF_DEVICE_OS_DEVICE_INFO *)config)->pOSDevice = &device->func->dev;
+            break; 
+        default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                            ("AR6000: Unsupported configuration opcode: %d\n", opcode));
+            return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+void
+HIFShutDownDevice(HIF_DEVICE *device)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n"));
+    if (device != NULL) {
+        AR_DEBUG_ASSERT(device->func != NULL);
+    } else {
+            /* since we are unloading the driver anyways, reset all cards in case the SDIO card
+             * is externally powered and we are unloading the SDIO stack.  This avoids the problem when
+             * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
+             * enumerated */
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n"));
+        ResetAllCards();
+
+        /* Unregister with bus driver core */
+        if (registered) {
+            registered = 0;
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Unregistering with the bus driver\n"));
+            sdio_unregister_driver(&ar6k_driver);
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+                            ("AR6000: Unregistered\n"));
+        }
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n"));
+}
+
+static void
+hifIRQHandler(struct sdio_func *func)
+{
+    A_STATUS status;
+    HIF_DEVICE *device;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n"));
+
+    device = getHifDevice(func);
+    /* release the host during ints so we can pick it back up when we process cmds */
+    sdio_release_host(device->func);
+    status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context);
+    sdio_claim_host(device->func);
+    AR_DEBUG_ASSERT(status == A_OK || status == A_ECANCELED);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n"));
+}
+
+/* handle HTC startup via thread*/
+static int startup_task(void *param)
+{
+    HIF_DEVICE *device;
+
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n"));
+        /* start  up inform DRV layer */
+    if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+    }
+    return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+/* handle HTC startup via thread*/
+static int resume_task(void *param)
+{
+    HIF_DEVICE *device;
+    device = (HIF_DEVICE *)param;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from resume_task\n"));
+        /* start  up inform DRV layer */
+    if (device && device->claimedContext && osdrvCallbacks.deviceResumeHandler &&
+        osdrvCallbacks.deviceResumeHandler(device->claimedContext) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+    }
+    return 0;
+}
+#endif /* CONFIG_PM */
+
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
+{
+    int ret;
+    HIF_DEVICE * device;
+    int count;
+    struct task_struct* startup_task_struct;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+		    ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n",
+		     func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize));
+
+    addHifDevice(func);
+    device = getHifDevice(func);
+
+    spin_lock_init(&device->lock);
+
+    spin_lock_init(&device->asynclock);
+    
+    DL_LIST_INIT(&device->ScatterReqHead);
+    
+    if (!nohifscattersupport) {
+            /* try to allow scatter operation on all instances,
+             * unless globally overridden */
+        device->scatter_enabled = TRUE;
+    }
+    
+        /* enable the SDIO function */
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n"));
+    sdio_claim_host(func);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n"));
+
+    if ((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) >= MANUFACTURER_ID_AR6003_BASE) {
+        /* enable 4-bit ASYNC interrupt on AR6003 or later devices */    
+        ret = Func0_CMD52WriteByte(func->card, CCCR_SDIO_IRQ_MODE_REG, SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret));    
+            sdio_release_host(func);
+            return ret;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n"));   
+    }
+    
+    
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+    /* give us some time to enable, in ms */
+    func->enable_timeout = 100;
+#endif
+    ret = sdio_enable_func(func);
+    if (ret) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
+					  __FUNCTION__, ret)); 
+        sdio_release_host(func);
+        return ret;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE));
+    ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+    sdio_release_host(func);
+    if (ret) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x  AR6K: 0x%X\n",
+					  __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
+        return ret;
+    }
+    /* Initialize the bus requests to be used later */
+    A_MEMZERO(device->busRequest, sizeof(device->busRequest));
+    for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
+        sema_init(&device->busRequest[count].sem_req, 0);
+        hifFreeBusRequest(device, &device->busRequest[count]);
+    }
+
+    /* create async I/O thread */
+    device->async_shutdown = 0;
+    device->async_task = kthread_create(async_task,
+                                       (void *)device,
+                                       "AR6K Async");
+    if (IS_ERR(device->async_task)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
+        return A_ERROR;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
+    sema_init(&device->sem_async, 0);
+    wake_up_process(device->async_task );
+
+    /* create startup thread */
+    startup_task_struct = kthread_create(startup_task,
+                                  (void *)device,
+                                  "AR6K startup");
+    if (IS_ERR(startup_task_struct)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__));
+        return A_ERROR;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n"));
+    wake_up_process(startup_task_struct);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret));
+    return ret;
+}
+
+
+void
+HIFAckInterrupt(HIF_DEVICE *device)
+{
+    AR_DEBUG_ASSERT(device != NULL);
+
+    /* Acknowledge our function IRQ */
+}
+
+void
+HIFUnMaskInterrupt(HIF_DEVICE *device)
+{
+    int ret;;
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n"));
+
+    /* Register the IRQ Handler */
+    sdio_claim_host(device->func);
+    ret = sdio_claim_irq(device->func, hifIRQHandler);
+    sdio_release_host(device->func);
+    AR_DEBUG_ASSERT(ret == 0);
+}
+
+void HIFMaskInterrupt(HIF_DEVICE *device)
+{
+    int ret;;
+
+    AR_DEBUG_ASSERT(device != NULL);
+    AR_DEBUG_ASSERT(device->func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n"));
+
+    /* Mask our function IRQ */
+    sdio_claim_host(device->func);
+    ret = sdio_release_irq(device->func);
+    sdio_release_host(device->func);
+    AR_DEBUG_ASSERT(ret == 0);
+}
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device)
+{
+    BUS_REQUEST *busrequest;
+    unsigned long flag;
+
+    /* Acquire lock */
+    spin_lock_irqsave(&device->lock, flag);
+
+    /* Remove first in list */
+    if((busrequest = device->s_busRequestFreeQueue) != NULL)
+    {
+        device->s_busRequestFreeQueue = busrequest->next;
+    }
+
+    /* Release lock */
+    spin_unlock_irqrestore(&device->lock, flag);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest));
+    return busrequest;
+}
+
+void
+hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    unsigned long flag;
+
+    AR_DEBUG_ASSERT(busrequest != NULL);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest));
+    /* Acquire lock */
+    spin_lock_irqsave(&device->lock, flag);
+
+
+    /* Insert first in list */
+    busrequest->next = device->s_busRequestFreeQueue;
+    busrequest->inusenext = NULL;
+    device->s_busRequestFreeQueue = busrequest;
+
+    /* Release lock */
+    spin_unlock_irqrestore(&device->lock, flag);
+}
+
+static int hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func)
+{
+    int ret = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
+    device = getHifDevice(func);
+    if (!IS_ERR(device->async_task)) {
+        init_completion(&device->async_completion);
+        device->async_shutdown = 1;
+        up(&device->sem_async);
+        wait_for_completion(&device->async_completion);
+        device->async_task = NULL;
+    }
+    /* Disable the card */
+    sdio_claim_host(device->func);
+    ret = sdio_disable_func(device->func);
+
+    if (reset_sdio_on_unload) {
+        /* reset the SDIO interface.  This is useful in automated testing where the card
+         * does not need to be removed at the end of the test.  It is expected that the user will 
+         * also unload/reload the host controller driver to force the bus driver to re-enumerate the slot */
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6000: reseting SDIO card back to uninitialized state \n"));
+        
+        /* NOTE : sdio_f0_writeb() cannot be used here, that API only allows access
+         *        to undefined registers in the range of: 0xF0-0xFF */
+         
+        ret = Func0_CMD52WriteByte(device->func->card, SDIO_CCCR_ABORT, (1 << 3)); 
+        if (ret) {
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: reset failed : %d \n",ret));    
+        }
+    }
+
+    sdio_release_host(device->func);
+    return ret;
+}
+
+static void hifDeviceRemoved(struct sdio_func *func)
+{
+    A_STATUS status = A_OK;
+    HIF_DEVICE *device;
+    AR_DEBUG_ASSERT(func != NULL);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
+    device = getHifDevice(func);
+    if (device->claimedContext != NULL) {
+        status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device);
+    }
+
+    if (device->is_suspend) {
+        device->is_suspend = FALSE;
+    } else {
+        if (hifDisableFunc(device, func)!=0) {
+            status = A_ERROR;
+        }
+    }
+    CleanupHIFScatterResources(device);
+     
+    delHifDevice(device);
+    AR_DEBUG_ASSERT(status == A_OK);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n"));
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+static int hifDeviceSuspend(struct device *dev)
+{
+	struct sdio_func *func = dev_to_sdio_func(dev);
+    A_STATUS status = A_OK;
+    HIF_DEVICE *device;   
+    device = getHifDevice(func);
+    if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
+        status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext);
+    }
+    if (status == A_OK) {
+        hifDisableFunc(device, func);
+        device->is_suspend = TRUE;
+    } else if (status == A_EBUSY) {
+        status = A_OK; /* assume that sdio host controller will take care the power of wifi chip */
+    }
+    return A_SUCCESS(status) ? 0 : status;
+}
+
+static int hifDeviceResume(struct device *dev)
+{
+    struct task_struct* pTask;
+    const char *taskName;
+    int (*taskFunc)(void *);
+	struct sdio_func *func = dev_to_sdio_func(dev);
+    A_STATUS ret = A_OK;
+    HIF_DEVICE *device;   
+    device = getHifDevice(func);
+
+    if (device->is_suspend) {
+       /* enable the SDIO function */
+        sdio_claim_host(func);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+        /* give us some time to enable, in ms */
+        func->enable_timeout = 100;
+#endif
+        ret = sdio_enable_func(func);
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
+					  __FUNCTION__, ret));
+            sdio_release_host(func);
+            return ret;
+    }
+        ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+        sdio_release_host(func);
+        if (ret) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x  AR6K: 0x%X\n",
+					  __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
+            return ret;
+        }
+        device->is_suspend = FALSE;
+        /* create async I/O thread */
+        if (!device->async_task) {
+            device->async_shutdown = 0;
+            device->async_task = kthread_create(async_task,
+                                           (void *)device,
+                                           "AR6K Async");
+           if (IS_ERR(device->async_task)) {
+               AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
+                return A_ERROR;
+           }
+           AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
+           wake_up_process(device->async_task );    
+        }
+    }
+
+    if (!device->claimedContext) {
+        printk("WARNING!!! No claimedContext during resume wlan\n"); 
+        taskFunc = startup_task;
+        taskName = "AR6K startup";
+    } else {
+        taskFunc = resume_task;
+        taskName = "AR6K resume";
+    }
+    /* create resume thread */
+    pTask = kthread_create(taskFunc, (void *)device, taskName);
+    if (IS_ERR(pTask)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create resume task\n", __FUNCTION__));
+        return A_ERROR;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start resume task\n"));
+    wake_up_process(pTask);
+    return A_SUCCESS(ret) ? 0 : ret;
+}
+#endif /* CONFIG_PM */
+
+static HIF_DEVICE *
+addHifDevice(struct sdio_func *func)
+{
+    HIF_DEVICE *hifdevice;
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n"));
+    AR_DEBUG_ASSERT(func != NULL);
+    hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL);
+    AR_DEBUG_ASSERT(hifdevice != NULL);
+#if HIF_USE_DMA_BOUNCE_BUFFER
+    hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
+    AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL);
+#endif
+    hifdevice->func = func;
+    sdio_set_drvdata(func, hifdevice);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice));
+    return hifdevice;
+}
+
+static HIF_DEVICE *
+getHifDevice(struct sdio_func *func)
+{
+    AR_DEBUG_ASSERT(func != NULL);
+    return (HIF_DEVICE *)sdio_get_drvdata(func);
+}
+
+static void
+delHifDevice(HIF_DEVICE * device)
+{
+    AR_DEBUG_ASSERT(device!= NULL);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device));
+    if (device->dma_buffer != NULL) {
+        kfree(device->dma_buffer);
+    }
+    kfree(device);
+}
+
+static void ResetAllCards(void)
+{
+}
+
+void HIFClaimDevice(HIF_DEVICE  *device, void *context)
+{
+    device->claimedContext = context;
+}
+
+void HIFReleaseDevice(HIF_DEVICE  *device)
+{
+    device->claimedContext = NULL;
+}
+
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks)
+{
+    if (device->htcCallbacks.context != NULL) {
+            /* already in use! */
+        return A_ERROR;
+    }
+    device->htcCallbacks = *callbacks;
+    return A_OK;
+}
+
+void HIFDetachHTC(HIF_DEVICE *device)
+{
+    A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks));
+}
+
+#define SDIO_SET_CMD52_ARG(arg,rw,func,raw,address,writedata) \
+    (arg) = (((rw) & 1) << 31)           | \
+            (((func) & 0x7) << 28)       | \
+            (((raw) & 1) << 27)          | \
+            (1 << 26)                    | \
+            (((address) & 0x1FFFF) << 9) | \
+            (1 << 8)                     | \
+            ((writedata) & 0xFF)
+            
+#define SDIO_SET_CMD52_READ_ARG(arg,func,address) \
+    SDIO_SET_CMD52_ARG(arg,0,(func),0,address,0x00)
+#define SDIO_SET_CMD52_WRITE_ARG(arg,func,address,value) \
+    SDIO_SET_CMD52_ARG(arg,1,(func),0,address,value)
+    
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte)
+{
+    struct mmc_command ioCmd;
+    unsigned long      arg;
+    
+    memset(&ioCmd,0,sizeof(ioCmd));
+    SDIO_SET_CMD52_WRITE_ARG(arg,0,address,byte);
+    ioCmd.opcode = SD_IO_RW_DIRECT;
+    ioCmd.arg = arg;
+    ioCmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
+    
+    return mmc_wait_for_cmd(card->host, &ioCmd, 0);
+}
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
new file mode 100644
index 000000000000..de236d269f0d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
@@ -0,0 +1,390 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_scatter.c" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF scatter implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/kthread.h>
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define _CMD53_ARG_READ          0
+#define _CMD53_ARG_WRITE         1
+#define _CMD53_ARG_BLOCK_BASIS   1 
+#define _CMD53_ARG_FIXED_ADDRESS 0
+#define _CMD53_ARG_INCR_ADDRESS  1
+
+#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
+    (arg) = (((rw) & 1) << 31)                  | \
+            (((func) & 0x7) << 28)              | \
+            (((mode) & 1) << 27)                | \
+            (((opcode) & 1) << 26)              | \
+            (((address) & 0x1FFFF) << 9)        | \
+            ((bytes_blocks) & 0x1FF)
+            
+static void FreeScatterReq(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{   
+    unsigned long flag;
+
+    spin_lock_irqsave(&device->lock, flag);
+
+    DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
+    
+    spin_unlock_irqrestore(&device->lock, flag);
+        
+}
+
+static HIF_SCATTER_REQ *AllocScatterReq(HIF_DEVICE *device) 
+{
+    DL_LIST       *pItem; 
+    unsigned long flag;
+
+    spin_lock_irqsave(&device->lock, flag);
+    
+    pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
+    
+    spin_unlock_irqrestore(&device->lock, flag);
+    
+    if (pItem != NULL) {
+        return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+    }
+    
+    return NULL;   
+}
+
+    /* called by async task to perform the operation synchronously using direct MMC APIs  */
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+    int                     i;
+    A_UINT8                 rw;
+    A_UINT8                 opcode;
+    struct mmc_request      mmcreq;
+    struct mmc_command      cmd;
+    struct mmc_data         data;
+    HIF_SCATTER_REQ_PRIV   *pReqPriv;   
+    HIF_SCATTER_REQ        *pReq;       
+    A_STATUS                status = A_OK;
+    struct                  scatterlist *pSg;
+    
+    pReqPriv = busrequest->pScatterReq;
+    
+    A_ASSERT(pReqPriv != NULL);
+    
+    pReq = pReqPriv->pHifScatterReq;
+    
+    memset(&mmcreq, 0, sizeof(struct mmc_request));
+    memset(&cmd, 0, sizeof(struct mmc_command));
+    memset(&data, 0, sizeof(struct mmc_data));
+       
+    data.blksz = HIF_MBOX_BLOCK_SIZE;
+    data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
+                        
+    AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
+              (pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
+              pReq->TotalLength,pReq->ValidScatterEntries));
+         
+    if (pReq->Request  & HIF_WRITE) {
+        rw = _CMD53_ARG_WRITE;
+        data.flags = MMC_DATA_WRITE;
+    } else {
+        rw = _CMD53_ARG_READ;
+        data.flags = MMC_DATA_READ;
+    }
+
+    if (pReq->Request & HIF_FIXED_ADDRESS) {
+        opcode = _CMD53_ARG_FIXED_ADDRESS;
+    } else {
+        opcode = _CMD53_ARG_INCR_ADDRESS;
+    }
+    
+        /* fill SG entries */
+    pSg = pReqPriv->sgentries;   
+    sg_init_table(pSg, pReq->ValidScatterEntries); 
+          
+        /* assemble SG list */   
+    for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
+            /* setup each sg entry */
+        if ((A_UINT32)pReq->ScatterList[i].pBuffer & 0x3) {
+                /* note some scatter engines can handle unaligned buffers, print this
+                 * as informational only */
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
+                            ("HIF: (%s) Scatter Buffer is unaligned 0x%08x\n",
+                            pReq->Request & HIF_WRITE ? "WRITE":"READ",
+                            (A_UINT32)pReq->ScatterList[i].pBuffer)); 
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("  %d:  Addr:0x%X, Len:%d \n",
+            i,(A_UINT32)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
+            
+        sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
+    }
+        /* set scatter-gather table for request */
+    data.sg = pReqPriv->sgentries;
+    data.sg_len = pReq->ValidScatterEntries;
+        /* set command argument */    
+    SDIO_SET_CMD53_ARG(cmd.arg, 
+                       rw, 
+                       device->func->num, 
+                       _CMD53_ARG_BLOCK_BASIS, 
+                       opcode,  
+                       pReq->Address,
+                       data.blocks);  
+                       
+    cmd.opcode = SD_IO_RW_EXTENDED;
+    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+    
+    mmcreq.cmd = &cmd;
+    mmcreq.data = &data;
+    
+    mmc_set_data_timeout(&data, device->func->card);    
+        /* synchronous call to process request */
+    mmc_wait_for_req(device->func->card->host, &mmcreq);
+ 
+    if (cmd.error) {
+        status = A_ERROR;   
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
+    }
+               
+    if (data.error) {
+        status = A_ERROR;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));   
+    }
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
+              (pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));        
+    }
+    
+        /* set completion status, fail or success */
+    pReq->CompletionStatus = status;
+    
+    if (pReq->Request & HIF_ASYNCHRONOUS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%X (%d)\n",(unsigned int)busrequest, status));
+            /* complete the request */
+        A_ASSERT(pReq->CompletionRoutine != NULL);
+        pReq->CompletionRoutine(pReq);
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%X (%d)\n", (unsigned int)busrequest,status));
+            /* signal wait */
+        up(&busrequest->sem_req);
+    }
+                                                               
+    return status;   
+}
+
+    /* callback to issue a read-write scatter request */
+static A_STATUS HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{
+    A_STATUS             status = A_EINVAL;
+    A_UINT32             request = pReq->Request;
+    HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+    
+    do {
+        
+        A_ASSERT(pReqPriv != NULL);
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n", 
+                            pReq->TotalLength, pReq->ValidScatterEntries));
+        
+        if (!(request & HIF_EXTENDED_IO)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
+            break;
+        }
+        
+        if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
+            break;
+        }
+        
+        if (!(request & HIF_BLOCK_BASIS)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
+            break;   
+        }
+        
+        if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+                            ("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
+            break;          
+        }
+        
+        if (pReq->TotalLength == 0) {
+            A_ASSERT(FALSE);
+            break;    
+        }
+        
+            /* add bus request to the async list for the async I/O thread to process */
+        AddToAsyncList(device, pReqPriv->busrequest);
+
+        if (request & HIF_SYNCHRONOUS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%X\n", (unsigned int)pReqPriv->busrequest));
+            /* signal thread and wait */
+            up(&device->sem_async);
+            if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
+                /* interrupted, exit */
+                status = A_ERROR;
+                break;
+            } else {
+                status = pReq->CompletionStatus;
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%X\n", (unsigned int)pReqPriv->busrequest));
+                /* wake thread, it will process and then take care of the async callback */
+            up(&device->sem_async);
+            status = A_OK;
+        }           
+       
+    } while (FALSE);
+
+    if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+        pReq->CompletionStatus = status;
+        pReq->CompletionRoutine(pReq);
+        status = A_OK;
+    }
+        
+    return status;  
+}
+
+    /* setup of HIF scatter resources */
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
+{
+    A_STATUS              status = A_ERROR;   
+    int                   i;
+    HIF_SCATTER_REQ_PRIV *pReqPriv;
+    BUS_REQUEST          *busrequest;
+        
+    do {
+        
+            /* check if host supports scatter requests and it meets our requirements */
+        if (device->func->card->host->max_hw_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
+                    device->func->card->host->max_hw_segs, MAX_SCATTER_ENTRIES_PER_REQ));
+            status = A_ENOTSUP;
+            break;    
+        }
+                    
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
+                MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ)); 
+        
+        for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {    
+                /* allocate the private request blob */
+            pReqPriv = (HIF_SCATTER_REQ_PRIV *)A_MALLOC(sizeof(HIF_SCATTER_REQ_PRIV));
+            if (NULL == pReqPriv) {
+                break;    
+            }
+            A_MEMZERO(pReqPriv, sizeof(HIF_SCATTER_REQ_PRIV));
+                /* save the device instance*/
+            pReqPriv->device = device;      
+                /* allocate the scatter request */
+            pReqPriv->pHifScatterReq = (HIF_SCATTER_REQ *)A_MALLOC(sizeof(HIF_SCATTER_REQ) + 
+                                         (MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM))); 
+           
+            if (NULL == pReqPriv->pHifScatterReq) {
+                A_FREE(pReqPriv);
+                break;      
+            }           
+                /* just zero the main part of the scatter request */
+            A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(HIF_SCATTER_REQ));
+                /* back pointer to the private struct */
+            pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
+                /* allocate a bus request for this scatter request */
+            busrequest = hifAllocateBusRequest(device);
+            if (NULL == busrequest) {
+                A_FREE(pReqPriv->pHifScatterReq);
+                A_FREE(pReqPriv);
+                break;    
+            }
+                /* assign the scatter request to this bus request */
+            busrequest->pScatterReq = pReqPriv;
+                /* point back to the request */
+            pReqPriv->busrequest = busrequest;                           
+                /* add it to the scatter pool */
+            FreeScatterReq(device,pReqPriv->pHifScatterReq);
+        }
+        
+        if (i != MAX_SCATTER_REQUESTS) {
+            status = A_NO_MEMORY;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
+            break;    
+        }
+        
+            /* set scatter function pointers */
+        pInfo->pAllocateReqFunc = AllocScatterReq;
+        pInfo->pFreeReqFunc = FreeScatterReq;
+        pInfo->pReadWriteScatterFunc = HifReadWriteScatter;   
+        pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
+        pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
+     
+        status = A_OK;
+        
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        CleanupHIFScatterResources(device);   
+    }
+    
+    return status;
+}
+
+    /* clean up scatter support */
+void CleanupHIFScatterResources(HIF_DEVICE *device)
+{
+    HIF_SCATTER_REQ_PRIV    *pReqPriv;
+    HIF_SCATTER_REQ         *pReq;
+    
+        /* empty the free list */
+        
+    while (1) {
+        
+        pReq = AllocScatterReq(device);
+                
+        if (NULL == pReq) {
+            break;    
+        }   
+        
+        pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+        A_ASSERT(pReqPriv != NULL);
+        
+        if (pReqPriv->busrequest != NULL) {
+            pReqPriv->busrequest->pScatterReq = NULL;
+                /* free bus request */
+            hifFreeBusRequest(device, pReqPriv->busrequest);
+            pReqPriv->busrequest = NULL;
+        }
+        
+        if (pReqPriv->pHifScatterReq != NULL) {
+            A_FREE(pReqPriv->pHifScatterReq);   
+            pReqPriv->pHifScatterReq = NULL; 
+        }
+                
+        A_FREE(pReqPriv);       
+    }
+}
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c
new file mode 100644
index 000000000000..dfcc60b548e4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c
@@ -0,0 +1,1399 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+#define MAILBOX_FOR_BLOCK_SIZE          1
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev);
+
+void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
+{
+    LOCK_AR6K(pDev);
+    HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
+    UNLOCK_AR6K(pDev);
+}
+
+HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
+{
+    HTC_PACKET *pPacket;
+
+    LOCK_AR6K(pDev);
+    pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
+    UNLOCK_AR6K(pDev);
+
+    return pPacket;
+}
+
+void DevCleanup(AR6K_DEVICE *pDev)
+{
+    DevCleanupGMbox(pDev);
+    
+    if (pDev->HifAttached) {
+        HIFDetachHTC(pDev->HIFDevice);
+        pDev->HifAttached = FALSE;
+    }
+   
+    DevCleanupVirtualScatterSupport(pDev);
+    
+    if (A_IS_MUTEX_VALID(&pDev->Lock)) {
+        A_MUTEX_DELETE(&pDev->Lock);
+    }   
+}
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev)
+{
+    A_UINT32 blocksizes[AR6K_MAILBOXES];
+    A_STATUS status = A_OK;
+    int      i;
+    HTC_CALLBACKS htcCallbacks;
+    
+    do {
+        
+        DL_LIST_INIT(&pDev->ScatterReqHead);
+           /* initialize our free list of IO packets */
+        INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
+        A_MUTEX_INIT(&pDev->Lock);
+               
+        A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
+            /* the device layer handles these */
+        htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
+        htcCallbacks.dsrHandler = DevDsrHandler;
+        htcCallbacks.context = pDev;
+        
+        status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks);
+                
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pDev->HifAttached = TRUE;
+        
+            /* get the addresses for all 4 mailboxes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+                                    &pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* carve up register I/O packets (these are for ASYNC register I/O ) */
+        for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
+            HTC_PACKET *pIOPacket;
+            pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
+            SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
+                                          pDev,
+                                          pDev->RegIOBuffers[i].Buffer,
+                                          AR6K_REG_IO_BUFFER_SIZE,
+                                          0); /* don't care */
+            AR6KFreeIOPacket(pDev,pIOPacket);
+        }
+
+            /* get the block sizes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
+             * size on mailbox 0 is artificially set to 1.  So we use the block size that is set
+             * for the other 3 mailboxes */
+        pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
+            /* must be a power of 2 */
+        A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
+
+            /* assemble mask, used for padding to a block */
+        pDev->BlockMask = pDev->BlockSize - 1;
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
+                    pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]));
+
+        pDev->GetPendingEventsFunc = NULL;
+            /* see if the HIF layer implements the get pending events function  */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+                           &pDev->GetPendingEventsFunc,
+                           sizeof(pDev->GetPendingEventsFunc));
+
+            /* assume we can process HIF interrupt events asynchronously */
+        pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
+
+            /* see if the HIF layer overrides this assumption */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_IRQ_PROC_MODE,
+                           &pDev->HifIRQProcessingMode,
+                           sizeof(pDev->HifIRQProcessingMode));
+
+        switch (pDev->HifIRQProcessingMode) {
+            case HIF_DEVICE_IRQ_SYNC_ONLY:                
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n"));
+                    /* see if HIF layer wants HTC to yield */
+                HIFConfigureDevice(pDev->HIFDevice,
+                                   HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+                                   &pDev->HifIRQYieldParams,
+                                   sizeof(pDev->HifIRQYieldParams));
+                                   
+                if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                        ("HIF requests that DSR yield per %d RECV packets \n",
+                        pDev->HifIRQYieldParams.RecvPacketYieldCount));   
+                    pDev->DSRCanYield = TRUE;    
+                }                              
+                break;
+            case HIF_DEVICE_IRQ_ASYNC_SYNC:
+                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
+                break;
+            default:
+                A_ASSERT(FALSE);
+        }
+
+        pDev->HifMaskUmaskRecvEvent = NULL;
+
+            /* see if the HIF layer implements the mask/unmask recv events function  */
+        HIFConfigureDevice(pDev->HIFDevice,
+                           HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+                           &pDev->HifMaskUmaskRecvEvent,
+                           sizeof(pDev->HifMaskUmaskRecvEvent));
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n",
+                 (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent));
+
+        status = DevDisableInterrupts(pDev);
+
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        status = DevSetupGMbox(pDev);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (pDev->HifAttached) {
+            HIFDetachHTC(pDev->HIFDevice);
+            pDev->HifAttached = FALSE;
+        }
+    }
+
+    return status;
+
+}
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
+{
+    A_STATUS                  status;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+    LOCK_AR6K(pDev);
+
+        /* Enable all the interrupts except for the internal AR6000 CPU interrupt */
+    pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
+                                      INT_STATUS_ENABLE_CPU_SET(0x01) |
+                                      INT_STATUS_ENABLE_COUNTER_SET(0x01);
+
+    if (NULL == pDev->GetPendingEventsFunc) {
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    } else {
+        /* The HIF layer provided us with a pending events function which means that
+         * the detection of pending mbox messages is handled in the HIF layer.
+         * This is the case for the SPI2 interface.
+         * In the normal case we enable MBOX interrupts, for the case
+         * with HIFs that offer this mechanism, we keep these interrupts
+         * masked */
+        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    }
+
+
+    /* Set up the CPU Interrupt Status Register */
+    pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
+
+    /* Set up the Error Interrupt Status Register */
+    pDev->IrqEnableRegisters.error_status_enable =
+                                  ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
+                                  ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
+
+    /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
+    pDev->IrqEnableRegisters.counter_int_status_enable =
+        COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
+
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+        /* always synchronous */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          INT_STATUS_ENABLE_ADDRESS,
+                          &regs.int_status_enable,
+                          AR6K_IRQ_ENABLE_REGS_SIZE,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        /* Can't write it for some reason */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Failed to update interrupt control registers err: %d\n", status));
+
+    }
+
+    return status;
+}
+
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
+{
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+    LOCK_AR6K(pDev);
+        /* Disable all interrupts */
+    pDev->IrqEnableRegisters.int_status_enable = 0;
+    pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
+    pDev->IrqEnableRegisters.error_status_enable = 0;
+    pDev->IrqEnableRegisters.counter_int_status_enable = 0;
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+        /* always synchronous */
+    return HIFReadWrite(pDev->HIFDevice,
+                        INT_STATUS_ENABLE_ADDRESS,
+                        &regs.int_status_enable,
+                        AR6K_IRQ_ENABLE_REGS_SIZE,
+                        HIF_WR_SYNC_BYTE_INC,
+                        NULL);
+}
+
+/* enable device interrupts */
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
+{
+        /* for good measure, make sure interrupt are disabled before unmasking at the HIF
+         * layer.
+         * The rationale here is that between device insertion (where we clear the interrupts the first time)
+         * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets.
+         * The AR6K interrupt enables reset back to an "enabled" state when this happens.
+         *  */
+    DevDisableInterrupts(pDev);
+
+        /* Unmask the host controller interrupts */
+    HIFUnMaskInterrupt(pDev->HIFDevice);
+
+    return DevEnableInterrupts(pDev);
+}
+
+/* disable all device interrupts */
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
+{
+        /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
+         * we zero out our shadow registers in DevDisableInterrupts()*/
+    HIFMaskInterrupt(pDev->HIFDevice);
+
+    return DevDisableInterrupts(pDev);
+}
+
+/* callback when our fetch to enable/disable completes */
+static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" Failed to disable receiver, status:%d \n", pPacket->Status));
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "override" method when the HIF reports another methods to
+ * disable recv events */
+static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    HTC_PACKET                *pIOPacket = NULL;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
+            EnableRecv,AsyncMode));
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+            pIOPacket->pContext = pDev;
+
+                /* call the HIF layer override and do this asynchronously */
+            status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+                                                 EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+                                                 pIOPacket);
+            break;
+        }
+
+            /* if we get here we are doing it synchronously */
+        status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+                                             EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+                                             NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status) && (pIOPacket != NULL)) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "normal" method using the interrupt enable registers through
+ * the host I/F */
+static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    HTC_PACKET                *pIOPacket = NULL;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+
+        /* take the lock to protect interrupt enable shadows */
+    LOCK_AR6K(pDev);
+
+    if (EnableRecv) {
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    } else {
+        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+    }
+
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+            pIOPacket->pContext = pDev;
+
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         INT_STATUS_ENABLE_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_IRQ_ENABLE_REGS_SIZE,
+                         HIF_WR_ASYNC_BYTE_INC,
+                         pIOPacket);
+            break;
+        }
+
+        /* if we get here we are doing it synchronously */
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_STATUS_ENABLE_ADDRESS,
+                              &regs.int_status_enable,
+                              AR6K_IRQ_ENABLE_REGS_SIZE,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status) && (pIOPacket != NULL)) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+    if (NULL == pDev->HifMaskUmaskRecvEvent) {
+        return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
+    } else {
+        return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
+    }
+}
+
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+    if (NULL == pDev->HifMaskUmaskRecvEvent) {
+        return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
+    } else {
+        return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
+    }
+}
+
+void DevDumpRegisters(AR6K_DEVICE               *pDev,
+                      AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
+                      AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("\n<------- Register Table -------->\n"));
+
+    if (pIrqProcRegs != NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Host Int Status:           0x%x\n",pIrqProcRegs->host_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("CPU Int Status:            0x%x\n",pIrqProcRegs->cpu_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Error Int Status:          0x%x\n",pIrqProcRegs->error_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Counter Int Status:        0x%x\n",pIrqProcRegs->counter_int_status));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Mbox Frame:                0x%x\n",pIrqProcRegs->mbox_frame));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead Valid:        0x%x\n",pIrqProcRegs->rx_lookahead_valid));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead 0:            0x%x\n",pIrqProcRegs->rx_lookahead[0]));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Rx Lookahead 1:            0x%x\n",pIrqProcRegs->rx_lookahead[1]));
+            
+        if (pDev->MailBoxInfo.GMboxAddress != 0) {
+                /* if the target supports GMBOX hardware, dump some additional state */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX Host Int Status 2:   0x%x\n",pIrqProcRegs->host_int_status2));           
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX RX Avail:            0x%x\n",pIrqProcRegs->gmbox_rx_avail));
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX lookahead alias 0:   0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[0]));
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("GMBOX lookahead alias 1:   0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[1]));
+        }
+
+    }
+
+    if (pIrqEnableRegs != NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Int Status Enable:         0x%x\n",pIrqEnableRegs->int_status_enable));
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------->\n"));
+}
+
+
+#define DEV_GET_VIRT_DMA_INFO(p)  ((DEV_SCATTER_DMA_VIRTUAL_INFO *)((p)->HIFPrivate[0]))
+
+static HIF_SCATTER_REQ *DevAllocScatterReq(HIF_DEVICE *Context) 
+{
+    DL_LIST *pItem; 
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    LOCK_AR6K(pDev);
+    pItem = DL_ListRemoveItemFromHead(&pDev->ScatterReqHead);
+    UNLOCK_AR6K(pDev);
+    if (pItem != NULL) {
+        return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+    }
+    return NULL;   
+}
+
+static void DevFreeScatterReq(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    LOCK_AR6K(pDev);
+    DL_ListInsertTail(&pDev->ScatterReqHead, &pReq->ListLink);
+    UNLOCK_AR6K(pDev); 
+}
+
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA)
+{
+    A_UINT8         *pDMABuffer = NULL;
+    int             i, remaining;
+    A_UINT32        length;
+ 
+    pDMABuffer = pReq->pScatterBounceBuffer;
+       
+    if (pDMABuffer == NULL) {
+        A_ASSERT(FALSE);
+        return A_EINVAL;   
+    }
+    
+    remaining = (int)pReq->TotalLength;
+    
+    for (i = 0; i < pReq->ValidScatterEntries; i++) {
+        
+        length = min((int)pReq->ScatterList[i].Length, remaining);
+                       
+        if (length != (int)pReq->ScatterList[i].Length) {
+            A_ASSERT(FALSE);
+                /* there is a problem with the scatter list */
+            return A_EINVAL;    
+        }
+         
+        if (FromDMA) {
+                /* from DMA buffer */
+            A_MEMCPY(pReq->ScatterList[i].pBuffer, pDMABuffer , length);  
+        } else {
+                /* to DMA buffer */
+            A_MEMCPY(pDMABuffer, pReq->ScatterList[i].pBuffer, length);      
+        }
+        
+        pDMABuffer += length;
+        remaining -= length;
+    }
+    
+    return A_OK;
+}
+
+static void DevReadWriteScatterAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE     *pDev = (AR6K_DEVICE *)Context;
+    HIF_SCATTER_REQ *pReq = (HIF_SCATTER_REQ *)pPacket->pPktContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevReadWriteScatterAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+    
+    pReq->CompletionStatus = pPacket->Status;
+    
+    AR6KFreeIOPacket(pDev,pPacket);
+    
+    pReq->CompletionRoutine(pReq);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevReadWriteScatterAsyncHandler \n"));
+}
+
+static A_STATUS DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+    AR6K_DEVICE     *pDev = (AR6K_DEVICE *)Context;
+    A_STATUS        status = A_OK;
+    HTC_PACKET      *pIOPacket = NULL;
+    A_UINT32        request = pReq->Request; 
+    
+    do {    
+        
+        if (pReq->TotalLength > AR6K_MAX_TRANSFER_SIZE_PER_SCATTER) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("Invalid length: %d \n", pReq->TotalLength));
+            break;          
+        }
+        
+        if (pReq->TotalLength == 0) {
+            A_ASSERT(FALSE);
+            break;    
+        }
+                
+        if (request & HIF_ASYNCHRONOUS) {           
+                /* use an I/O packet to carry this request */
+            pIOPacket = AR6KAllocIOPacket(pDev);    
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                break;
+            }
+            
+                /* save the request */
+            pIOPacket->pPktContext = pReq;  
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevReadWriteScatterAsyncHandler;
+            pIOPacket->pContext = pDev;
+        }
+
+        if (request & HIF_WRITE) { 
+            /* in virtual DMA, we are issuing the requests through the legacy HIFReadWrite API
+             * this API will adjust the address automatically for the last byte to fall on the mailbox
+             * EOM. */
+             
+            /* if the address is an extended address, we can adjust the address here since the extended
+             * address will bypass the normal checks in legacy HIF layers */ 
+            if (pReq->Address == pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress) {
+                pReq->Address += pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize - pReq->TotalLength;         
+            }    
+        }
+        
+            /* use legacy readwrite */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              pReq->Address,
+                              DEV_GET_VIRT_DMA_INFO(pReq)->pVirtDmaBuffer,
+                              pReq->TotalLength,
+                              request,
+                              (request & HIF_ASYNCHRONOUS) ? pIOPacket : NULL);
+    
+    } while (FALSE);
+    
+    if ((status != A_PENDING) && A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+        if (pIOPacket != NULL) {
+            AR6KFreeIOPacket(pDev,pIOPacket);    
+        } 
+        pReq->CompletionStatus = status;
+        pReq->CompletionRoutine(pReq);
+        status = A_OK;
+    }
+    
+    return status;
+}
+
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+    HIF_SCATTER_REQ *pReq;
+    
+    while (1) {
+        pReq = DevAllocScatterReq((HIF_DEVICE *)pDev);
+        if (NULL == pReq) {
+            break;    
+        } 
+        A_FREE(pReq);   
+    }
+    
+}
+   
+    /* function to set up virtual scatter support if HIF layer has not implemented the interface */
+static A_STATUS DevSetupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+    A_STATUS                     status = A_OK;
+    int                          bufferSize, sgreqSize;
+    int                          i;
+    DEV_SCATTER_DMA_VIRTUAL_INFO *pVirtualInfo;
+    HIF_SCATTER_REQ              *pReq;
+    
+    bufferSize = sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO) + 
+                2 * (A_GET_CACHE_LINE_BYTES()) + AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
+    
+    sgreqSize = sizeof(HIF_SCATTER_REQ) + 
+                    (AR6K_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM));
+    
+    for (i = 0; i < AR6K_SCATTER_REQS; i++) {
+            /* allocate the scatter request, buffer info and the actual virtual buffer itself */            
+        pReq = (HIF_SCATTER_REQ *)A_MALLOC(sgreqSize + bufferSize);
+        
+        if (NULL == pReq) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        A_MEMZERO(pReq, sgreqSize);
+        
+            /* the virtual DMA starts after the scatter request struct */
+        pVirtualInfo = (DEV_SCATTER_DMA_VIRTUAL_INFO *)((A_UINT8 *)pReq + sgreqSize);
+        A_MEMZERO(pVirtualInfo, sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO));
+            
+        pVirtualInfo->pVirtDmaBuffer = &pVirtualInfo->DataArea[0];
+            /* align buffer to cache line in case host controller can actually DMA this */
+        pVirtualInfo->pVirtDmaBuffer = A_ALIGN_TO_CACHE_LINE(pVirtualInfo->pVirtDmaBuffer);
+            /* store the structure in the private area */ 
+        pReq->HIFPrivate[0] = pVirtualInfo;
+            /* we emulate a DMA bounce interface */
+        pReq->ScatterMethod = HIF_SCATTER_DMA_BOUNCE;
+        pReq->pScatterBounceBuffer = pVirtualInfo->pVirtDmaBuffer;
+            /* free request to the list */
+        DevFreeScatterReq((HIF_DEVICE *)pDev,pReq);
+    }
+    
+    if (A_FAILED(status)) {
+        DevCleanupVirtualScatterSupport(pDev);    
+    } else {   
+        pDev->HifScatterInfo.pAllocateReqFunc = DevAllocScatterReq;
+        pDev->HifScatterInfo.pFreeReqFunc = DevFreeScatterReq;
+        pDev->HifScatterInfo.pReadWriteScatterFunc = DevReadWriteScatter;   
+        pDev->HifScatterInfo.MaxScatterEntries = AR6K_SCATTER_ENTRIES_PER_REQ;
+        pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;   
+        pDev->ScatterIsVirtual = TRUE; 
+    }   
+    
+    return status;    
+}
+
+    
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer)
+{
+    A_STATUS status;    
+    
+    if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n"));     
+        return A_ENOTSUP;    
+    }
+    
+    status = HIFConfigureDevice(pDev->HIFDevice, 
+                                HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+                                &pDev->HifScatterInfo, 
+                                sizeof(pDev->HifScatterInfo));
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+            ("AR6K: ** HIF layer does not support scatter requests (%d) \n",status));
+        
+            /* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */
+        status = DevSetupVirtualScatterSupport(pDev);  
+        
+        if (A_SUCCESS(status)) {
+             AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                ("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n",
+                    DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));      
+        } 
+        
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n",
+                    DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));    
+    }
+    
+    if (A_SUCCESS(status)) {
+            /* for the recv path, the maximum number of bytes per recv bundle is just limited
+             * by the maximum transfer size at the HIF layer */
+        pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
+        
+            /* for the send path, the max transfer size is limited by the existence and size of
+             * the extended mailbox address range */
+        if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) {
+            pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize; 
+        } else {
+                /* legacy */
+            pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH;   
+        }
+        
+        if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) {
+                /* limit send bundle size to what the HIF can support for scatter requests */
+            pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;    
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+            ("AR6K: max recv: %d max send: %d \n",
+                    DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)));   
+                        
+    }  
+    return status;        
+}
+
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async)                            
+{   
+    A_STATUS status;
+                                                                                                                    
+    if (Read) {
+            /* read operation */
+        pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX;
+        pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];    
+        A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));                  
+    } else {
+        A_UINT32 mailboxWidth;
+        
+            /* write operation */
+        pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC;
+        A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));   
+        if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) {
+                /* for large writes use the extended address */
+            pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress;  
+            mailboxWidth = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize;
+        } else {
+            pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];    
+            mailboxWidth = AR6K_LEGACY_MAX_WRITE_LENGTH; 
+        }
+        
+        if (!pDev->ScatterIsVirtual) {
+            /* we are passing this scatter list down to the HIF layer' scatter request handler, fixup the address
+             * so that the last byte falls on the EOM, we do this for those HIFs that support the
+             * scatter API */
+            pScatterReq->Address += (mailboxWidth - pScatterReq->TotalLength);         
+        }
+                    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV | ATH_DEBUG_SEND,
+                ("DevSubmitScatterRequest, Entries: %d, Total Length: %d Mbox:0x%X (mode: %s : %s)\n",
+                pScatterReq->ValidScatterEntries,
+                pScatterReq->TotalLength,
+                pScatterReq->Address,
+                Async ? "ASYNC" : "SYNC",
+                (Read) ? "RD" : "WR"));
+    
+    status = DEV_PREPARE_SCATTER_OPERATION(pScatterReq);
+    
+    if (A_FAILED(status)) {
+        if (Async) {
+            pScatterReq->CompletionStatus = status;
+            pScatterReq->CompletionRoutine(pScatterReq);
+            return A_OK; 
+        }
+        return status;    
+    }
+                
+    status = pDev->HifScatterInfo.pReadWriteScatterFunc(pDev->ScatterIsVirtual ? pDev : pDev->HIFDevice,
+                                                        pScatterReq); 
+    if (!Async) {
+            /* in sync mode, we can touch the scatter request */
+        pScatterReq->CompletionStatus = status;
+        DEV_FINISH_SCATTER_OPERATION(pScatterReq);       
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;    
+        }    
+    }
+    
+    return status;
+}
+
+
+#ifdef MBOXHW_UNIT_TEST
+
+
+/* This is a mailbox hardware unit test that must be called in a schedulable context
+ * This test is very simple, it will send a list of buffers with a counting pattern
+ * and the target will invert the data and send the message back
+ *
+ * the unit test has the following constraints:
+ *
+ * The target has at least 8 buffers of 256 bytes each. The host will send
+ * the following pattern of buffers in rapid succession :
+ *
+ * 1 buffer - 128 bytes
+ * 1 buffer - 256 bytes
+ * 1 buffer - 512 bytes
+ * 1 buffer - 1024 bytes
+ *
+ * The host will send the buffers to one mailbox and wait for buffers to be reflected
+ * back from the same mailbox. The target sends the buffers FIFO order.
+ * Once the final buffer has been received for a mailbox, the next mailbox is tested.
+ *
+ *
+ * Note:  To simplifythe test , we assume that the chosen buffer sizes
+ *        will fall on a nice block pad
+ *
+ * It is expected that higher-order tests will be written to stress the mailboxes using
+ * a message-based protocol (with some performance timming) that can create more
+ * randomness in the packets sent over mailboxes.
+ *
+ * */
+
+#define A_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
+
+#define BUFFER_BLOCK_PAD 128
+
+#if 0
+#define BUFFER1 128
+#define BUFFER2 256
+#define BUFFER3 512
+#define BUFFER4 1024
+#endif
+
+#if 1
+#define BUFFER1 80
+#define BUFFER2 200
+#define BUFFER3 444
+#define BUFFER4 800
+#endif
+
+#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
+                     A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
+
+#define TEST_BYTES (BUFFER1 +  BUFFER2 + BUFFER3 + BUFFER4)
+
+#define TEST_CREDITS_RECV_TIMEOUT 100
+
+static A_UINT8  g_Buffer[TOTAL_BYTES];
+static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
+static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
+
+#define BUFFER_PROC_LIST_DEPTH 4
+
+typedef struct _BUFFER_PROC_LIST{
+    A_UINT8  *pBuffer;
+    A_UINT32 length;
+}BUFFER_PROC_LIST;
+
+
+#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
+{                                                   \
+    (pList)->pBuffer = (pCurrpos);                  \
+    (pList)->length = (len);                        \
+    (pCurrpos) += (len);                            \
+    (pList)++;                                      \
+}
+
+/* a simple and crude way to send different "message" sizes */
+static void AssembleBufferList(BUFFER_PROC_LIST *pList)
+{
+    A_UINT8 *pBuffer = g_Buffer;
+
+#if BUFFER_PROC_LIST_DEPTH < 4
+#error "Buffer processing list depth is not deep enough!!"
+#endif
+
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
+    PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
+
+}
+
+#define FILL_ZERO     TRUE
+#define FILL_COUNTING FALSE
+static void InitBuffers(A_BOOL Zero)
+{
+    A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
+    int      i;
+
+        /* fill buffer with 16 bit counting pattern or zeros */
+    for (i = 0; i <  (TOTAL_BYTES / 2) ; i++) {
+        if (!Zero) {
+            pBuffer16[i] = (A_UINT16)i;
+        } else {
+            pBuffer16[i] = 0;
+        }
+    }
+}
+
+
+static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
+{
+    int      i;
+    A_UINT16 startCount;
+    A_BOOL   success = TRUE;
+
+        /* get the starting count */
+    startCount = pBuffer16[0];
+        /* invert it, this is the expected value */
+    startCount = ~startCount;
+        /* scan the buffer and verify */
+    for (i = 0; i < (Length / 2) ; i++,startCount++) {
+            /* target will invert all the data */
+        if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
+            success = FALSE;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
+                        pBuffer16[i], ((A_UINT16)~startCount), i, Length));
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
+                        pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
+            break;
+        }
+    }
+
+    return success;
+}
+
+static A_BOOL CheckBuffers(void)
+{
+    int      i;
+    A_BOOL   success = TRUE;
+    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+        /* assemble the list */
+    AssembleBufferList(checkList);
+
+        /* scan the buffers and verify */
+    for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
+        success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
+        if (!success) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
+                        (A_UINT32)checkList[i].pBuffer, checkList[i].length));
+            break;
+        }
+    }
+
+    return success;
+}
+
+    /* find the end marker for the last buffer we will be sending */
+static A_UINT16 GetEndMarker(void)
+{
+    A_UINT8  *pBuffer;
+    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+        /* fill up buffers with the normal counting pattern */
+    InitBuffers(FILL_COUNTING);
+
+        /* assemble the list we will be sending down */
+    AssembleBufferList(checkList);
+        /* point to the last 2 bytes of the last buffer */
+    pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
+
+        /* the last count in the last buffer is the marker */
+    return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
+}
+
+#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
+
+/* send the ordered buffers to the target */
+static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS         status = A_OK;
+    A_UINT32         request = HIF_WR_SYNC_BLOCK_INC;
+    BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
+    int              i;
+    int              totalBytes = 0;
+    int              paddedLength;
+    int              totalwPadding = 0;
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
+
+        /* fill buffer with counting pattern */
+    InitBuffers(FILL_COUNTING);
+
+        /* assemble the order in which we send */
+    AssembleBufferList(sendList);
+
+    for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
+
+            /* we are doing block transfers, so we need to pad everything to a block size */
+        paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
+                       (~(g_BlockSizes[mbox] - 1));
+
+            /* send each buffer synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              g_MailboxAddrs[mbox],
+                              sendList[i].pBuffer,
+                              paddedLength,
+                              request,
+                              NULL);
+        if (status != A_OK) {
+            break;
+        }
+        totalBytes += sendList[i].length;
+        totalwPadding += paddedLength;
+    }
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
+
+    return status;
+}
+
+/* poll the mailbox credit counter until we get a credit or timeout */
+static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
+{
+    A_STATUS status = A_OK;
+    int      timeout = TEST_CREDITS_RECV_TIMEOUT;
+    A_UINT8  credits = 0;
+    A_UINT32 address;
+
+    while (TRUE) {
+
+            /* Read the counter register to get credits, this auto-decrements  */
+        address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
+        status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
+                              HIF_RD_SYNC_BYTE_FIX, NULL);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
+            status = A_ERROR;
+            break;
+        }
+
+        if (credits) {
+            break;
+        }
+
+        timeout--;
+
+        if (timeout <= 0) {
+              AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
+            status = A_ERROR;
+            break;
+        }
+
+         /* delay a little, target may not be ready */
+         A_MDELAY(1000);
+
+    }
+
+    if (status == A_OK) {
+        *pCredits = credits;
+    }
+
+    return status;
+}
+
+
+/* wait for the buffers to come back */
+static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS         status = A_OK;
+    A_UINT32         request = HIF_RD_SYNC_BLOCK_INC;
+    BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
+    int              curBuffer;
+    int              credits;
+    int              i;
+    int              totalBytes = 0;
+    int              paddedLength;
+    int              totalwPadding = 0;
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
+
+        /* zero the buffers */
+    InitBuffers(FILL_ZERO);
+
+        /* assemble the order in which we should receive */
+    AssembleBufferList(recvList);
+
+    curBuffer = 0;
+
+    while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
+
+            /* get number of buffers that have been completed, this blocks
+             * until we get at least 1 credit or it times out */
+        status = GetCredits(pDev, mbox, &credits);
+
+        if (status != A_OK) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
+
+            /* get all the buffers that are sitting on the queue */
+        for (i = 0; i < credits; i++) {
+            A_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
+                /* recv the current buffer synchronously, the buffers should come back in
+                 * order... with padding applied by the target */
+            paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
+                       (~(g_BlockSizes[mbox] - 1));
+
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  g_MailboxAddrs[mbox],
+                                  recvList[curBuffer].pBuffer,
+                                  paddedLength,
+                                  request,
+                                  NULL);
+            if (status != A_OK) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
+                        recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
+                break;
+            }
+
+            totalwPadding += paddedLength;
+            totalBytes += recvList[curBuffer].length;
+            curBuffer++;
+        }
+
+        if (status != A_OK) {
+            break;
+        }
+            /* go back and get some more */
+        credits = 0;
+    }
+
+    if (totalBytes != TEST_BYTES) {
+        A_ASSERT(FALSE);
+    }  else {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
+            mbox, totalBytes, totalwPadding));
+    }
+
+    return status;
+
+
+}
+
+static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
+{
+    A_STATUS status;
+
+    do {
+            /* send out buffers */
+        status = SendBuffers(pDev,mbox);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
+            break;
+        }
+
+            /* go get them, this will block */
+        status =  RecvBuffers(pDev, mbox);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
+            break;
+        }
+
+            /* check the returned data patterns */
+        if (!CheckBuffers()) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
+            status = A_ERROR;
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
+
+    }  while (FALSE);
+
+    return status;
+}
+
+/* here is where the test starts */
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
+{
+    int      i;
+    A_STATUS status;
+    int      credits = 0;
+    A_UINT8  params[4];
+    int      numBufs;
+    int      bufferSize;
+    A_UINT16 temp;
+
+
+    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START -  \n"));
+
+    do {
+            /* get the addresses for all 4 mailboxes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+                                    g_MailboxAddrs, sizeof(g_MailboxAddrs));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* get the block sizes */
+        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    g_BlockSizes, sizeof(g_BlockSizes));
+
+        if (status != A_OK) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* note, the HIF layer usually reports mbox 0 to have a block size of
+             * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
+             * the same. */
+        g_BlockSizes[0] = g_BlockSizes[1];
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
+
+        if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
+            AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
+                g_BlockSizes[1], BUFFER_BLOCK_PAD));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
+
+            /* the target lets us know it is ready by giving us 1 credit on
+             * mailbox 0 */
+        status = GetCredits(pDev, 0, &credits);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
+
+            /* read the first 4 scratch registers */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS,
+                              params,
+                              4,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
+            break;
+        }
+
+        numBufs = params[0];
+        bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
+            ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
+            numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
+
+        if ((numBufs * bufferSize) < TOTAL_BYTES) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
+                TOTAL_BYTES, (numBufs*bufferSize)));
+            status = A_ERROR;
+            break;
+        }
+
+        temp = GetEndMarker();
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS + 4,
+                              (A_UINT8 *)&temp,
+                              2,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
+
+        temp = (A_UINT16)g_BlockSizes[1];
+            /* convert to a mask */
+        temp = temp - 1;
+        status = HIFReadWrite(pDev->HIFDevice,
+                              SCRATCH_ADDRESS + 6,
+                              (A_UINT8 *)&temp,
+                              2,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);
+
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
+
+            /* execute the test on each mailbox */
+        for (i = 0; i < AR6K_MAILBOXES; i++) {
+            status = DoOneMboxHWTest(pDev, i);
+            if (status != A_OK) {
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+    if (status == A_OK) {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! -  \n"));
+    } else {
+        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! -  \n"));
+    }
+        /* don't let HTC_Start continue, the target is actually not running any HTC code */
+    return A_ERROR;
+}
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h
new file mode 100644
index 000000000000..b71ddb96cbde
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h
@@ -0,0 +1,383 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef AR6K_H_
+#define AR6K_H_
+
+#include "hci_transport_api.h"
+#include "../htc_debug.h"
+
+#define AR6K_MAILBOXES 4
+
+/* HTC runs over mailbox 0 */
+#define HTC_MAILBOX          0
+
+#define AR6K_TARGET_DEBUG_INTR_MASK     0x01
+
+#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK |   \
+                            INT_STATUS_ENABLE_CPU_MASK   |   \
+                            INT_STATUS_ENABLE_COUNTER_MASK)
+
+
+//#define MBOXHW_UNIT_TEST 1
+
+#include "athstartpack.h"
+typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
+    A_UINT8                      host_int_status;
+    A_UINT8                      cpu_int_status;
+    A_UINT8                      error_int_status;
+    A_UINT8                      counter_int_status;
+    A_UINT8                      mbox_frame;
+    A_UINT8                      rx_lookahead_valid;
+    A_UINT8                      host_int_status2;
+    A_UINT8                      gmbox_rx_avail;
+    A_UINT32                     rx_lookahead[2];
+    A_UINT32                     rx_gmbox_lookahead_alias[2];
+} POSTPACK AR6K_IRQ_PROC_REGISTERS;
+
+#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
+
+typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
+    A_UINT8                      int_status_enable;
+    A_UINT8                      cpu_int_status_enable;
+    A_UINT8                      error_status_enable;
+    A_UINT8                      counter_int_status_enable;
+} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
+
+typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS {
+    A_UINT8                      int_status_enable;
+} POSTPACK AR6K_GMBOX_CTRL_REGISTERS;
+
+#include "athendpack.h"
+
+#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
+
+#define AR6K_REG_IO_BUFFER_SIZE     32
+#define AR6K_MAX_REG_IO_BUFFERS     8
+#define FROM_DMA_BUFFER TRUE
+#define TO_DMA_BUFFER   FALSE
+#define AR6K_SCATTER_ENTRIES_PER_REQ            16
+#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER      16*1024
+#define AR6K_SCATTER_REQS                       4
+#define AR6K_LEGACY_MAX_WRITE_LENGTH            2048
+
+/* buffers for ASYNC I/O */
+typedef struct AR6K_ASYNC_REG_IO_BUFFER {
+    HTC_PACKET    HtcPacket;   /* we use an HTC packet as a wrapper for our async register-based I/O */
+    A_UINT8       Buffer[AR6K_REG_IO_BUFFER_SIZE];
+} AR6K_ASYNC_REG_IO_BUFFER;
+
+typedef struct _AR6K_GMBOX_INFO { 
+    void        *pProtocolContext;
+    A_STATUS    (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes);
+    A_STATUS    (*pCreditsPendingCallback)(void *pContext, int NumCredits,  A_BOOL CreditIRQEnabled);
+    void        (*pTargetFailureCallback)(void *pContext, A_STATUS Status);
+    void        (*pStateDumpCallback)(void *pContext);
+    A_BOOL      CreditCountIRQEnabled;    
+} AR6K_GMBOX_INFO; 
+
+typedef struct _AR6K_DEVICE {
+    A_MUTEX_T                   Lock;
+    AR6K_IRQ_PROC_REGISTERS     IrqProcRegisters;
+    AR6K_IRQ_ENABLE_REGISTERS   IrqEnableRegisters;
+    void                        *HIFDevice;
+    A_UINT32                    BlockSize;
+    A_UINT32                    BlockMask;
+    HIF_DEVICE_MBOX_INFO        MailBoxInfo;
+    HIF_PENDING_EVENTS_FUNC     GetPendingEventsFunc;
+    void                        *HTCContext;
+    HTC_PACKET_QUEUE            RegisterIOList;
+    AR6K_ASYNC_REG_IO_BUFFER    RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
+    void                        (*TargetFailureCallback)(void *Context);
+    A_STATUS                    (*MessagePendingCallback)(void *Context, 
+                                                          A_UINT32 LookAheads[], 
+                                                          int NumLookAheads, 
+                                                          A_BOOL *pAsyncProc,
+                                                          int *pNumPktsFetched);
+    HIF_DEVICE_IRQ_PROCESSING_MODE  HifIRQProcessingMode;
+    HIF_MASK_UNMASK_RECV_EVENT      HifMaskUmaskRecvEvent;
+    A_BOOL                          HifAttached;
+    HIF_DEVICE_IRQ_YIELD_PARAMS     HifIRQYieldParams;
+    A_BOOL                          DSRCanYield;
+    int                             CurrentDSRRecvCount;
+    HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo;
+    DL_LIST                         ScatterReqHead; 
+    A_BOOL                          ScatterIsVirtual;    
+    int                             MaxRecvBundleSize;
+    int                             MaxSendBundleSize;
+    AR6K_GMBOX_INFO                 GMboxInfo;
+    A_BOOL                          GMboxEnabled; 
+    AR6K_GMBOX_CTRL_REGISTERS       GMboxControlRegisters;
+    int                             RecheckIRQStatusCnt;
+} AR6K_DEVICE;
+
+#define LOCK_AR6K(p)      A_MUTEX_LOCK(&(p)->Lock);
+#define UNLOCK_AR6K(p)    A_MUTEX_UNLOCK(&(p)->Lock);
+#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1  /* note: no need to lock this, it only gets set */
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev);
+void     DevCleanup(AR6K_DEVICE *pDev);
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+                            A_UINT32    *pLookAhead,
+                            int          TimeoutMS);
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
+A_STATUS DevDsrHandler(void *context);
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
+void     DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev);
+void     DevDumpRegisters(AR6K_DEVICE               *pDev,
+                          AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
+                          AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
+
+#define DEV_STOP_RECV_ASYNC TRUE
+#define DEV_STOP_RECV_SYNC  FALSE
+#define DEV_ENABLE_RECV_ASYNC TRUE
+#define DEV_ENABLE_RECV_SYNC  FALSE
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+
+#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
+#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
+#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
+
+static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
+    A_UINT32 paddedLength;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+    A_STATUS status;
+
+       /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
+
+#if 0                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+#endif
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                paddedLength,
+                pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                          pPacket->pBuffer,
+                          paddedLength,     /* the padded length */
+                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;    
+        }    
+    }
+
+    return status;
+}
+                    
+static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
+    A_UINT32 paddedLength;
+    A_STATUS status;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+        /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
+                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+                    paddedLength,RecvLength,pPacket->BufferLength));
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("DevRecvPacket (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+                paddedLength,
+                pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+                          pPacket->pBuffer,
+                          paddedLength,
+                          sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    }
+
+    return status;
+}
+
+#define DEV_CHECK_RECV_YIELD(pDev) \
+            ((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
+            
+#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
+#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
+
+/**************************************************/
+/****** Scatter Function and Definitions
+ * 
+ *  
+ */
+  
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA);
+    
+    /* copy any READ data back into scatter list */        
+#define DEV_FINISH_SCATTER_OPERATION(pR)                      \
+    if (A_SUCCESS((pR)->CompletionStatus) &&                  \
+        !((pR)->Request & HIF_WRITE) &&                       \
+         ((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {   \
+         (pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \
+    }
+    
+    /* copy any WRITE data to bounce buffer */
+static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq)  { 
+    if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
+        return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);    
+    } else {
+        return A_OK;    
+    }
+}
+        
+    
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer);
+                                  
+#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev)        (pDev)->HifScatterInfo.MaxScatterEntries
+#define DEV_GET_MAX_BUNDLE_LENGTH(pDev)         (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
+#define DEV_ALLOC_SCATTER_REQ(pDev)             \
+    (pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
+    
+#define DEV_FREE_SCATTER_REQ(pDev,pR)           \
+    (pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
+
+#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev)   (pDev)->MaxRecvBundleSize
+#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)   (pDev)->MaxSendBundleSize
+
+#define DEV_SCATTER_READ  TRUE
+#define DEV_SCATTER_WRITE FALSE
+#define DEV_SCATTER_ASYNC TRUE
+#define DEV_SCATTER_SYNC  FALSE
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async);
+
+#ifdef MBOXHW_UNIT_TEST
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
+#endif
+
+    /* completely virtual */
+typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO {
+    A_UINT8            *pVirtDmaBuffer;      /* dma-able buffer - CPU accessible address */
+    A_UINT8            DataArea[1];      /* start of data area */
+} DEV_SCATTER_DMA_VIRTUAL_INFO;
+
+
+
+void     DumpAR6KDevState(AR6K_DEVICE *pDev);
+
+/**************************************************/
+/****** GMBOX functions and definitions
+ * 
+ *  
+ */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+void     DevCleanupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev);
+void     DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev);
+
+#else
+
+    /* compiled out */
+#define DevCleanupGMbox(p)
+#define DevCheckGMboxInterrupts(p) A_OK
+#define DevNotifyGMboxTargetFailure(p)
+
+static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) {
+    pDev->GMboxEnabled = FALSE;
+    return A_OK;    
+}
+
+#endif
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+    /* GMBOX protocol modules must expose each of these internal APIs */
+HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+A_STATUS             GMboxProtocolInstall(AR6K_DEVICE *pDev);
+void                 GMboxProtocolUninstall(AR6K_DEVICE *pDev);
+
+    /* API used by GMBOX protocol modules */
+AR6K_DEVICE  *HTCGetAR6KDevice(void *HTCHandle);
+#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
+{                                                                  \
+    (pDev)->GMboxInfo.pProtocolContext = (context);                \
+    (pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback);   \
+    (pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
+    (pDev)->GMboxInfo.pTargetFailureCallback = (failure);          \
+    (pDev)->GMboxInfo.pStateDumpCallback = (statedump);            \
+}
+
+#define DEV_GMBOX_GET_PROTOCOL(pDev)  (pDev)->GMboxInfo.pProtocolContext
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
+
+#define PROC_IO_ASYNC TRUE
+#define PROC_IO_SYNC  FALSE
+typedef enum GMBOX_IRQ_ACTION_TYPE {
+    GMBOX_ACTION_NONE = 0,
+    GMBOX_DISABLE_ALL,
+    GMBOX_ERRORS_IRQ_ENABLE,
+    GMBOX_RECV_IRQ_ENABLE,
+    GMBOX_RECV_IRQ_DISABLE,
+    GMBOX_CREDIT_IRQ_ENABLE,
+    GMBOX_CREDIT_IRQ_DISABLE,
+} GMBOX_IRQ_ACTION_TYPE;
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode);
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits);
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS);
+
+#endif
+
+#endif /*AR6K_H_*/
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c
new file mode 100644
index 000000000000..178cbb3e2962
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c
@@ -0,0 +1,762 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_events.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K Driver layer event handling (i.e. interrupts, message polling)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
+
+#define DELAY_PER_INTERVAL_MS 10  /* 10 MS delay per polling interval */
+
+/* completion routine for ALL HIF layer async I/O */
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
+{
+    HTC_PACKET *pPacket = (HTC_PACKET *)context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("+DevRWCompletionHandler (Pkt:0x%X) , Status: %d \n",
+                (A_UINT32)pPacket,
+                status));
+                
+    COMPLETE_HTC_PACKET(pPacket,status);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("-DevRWCompletionHandler\n"));
+                
+    return A_OK;
+}
+
+/* mailbox recv message polling */
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+                            A_UINT32    *pLookAhead,
+                            int          TimeoutMS)
+{
+    A_STATUS status = A_OK;
+    int      timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
+
+    A_ASSERT(timeout > 0);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
+
+    while (TRUE) {
+
+        if (pDev->GetPendingEventsFunc != NULL) {
+
+            HIF_PENDING_EVENTS_INFO events;
+
+            /* the HIF layer uses a special mechanism to get events, do this
+             * synchronously */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                            &events,
+                                            NULL);
+            if (A_FAILED(status))
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
+                break;
+            }
+
+            if (events.Events & HIF_RECV_MSG_AVAIL)
+            {
+                    /*  there is a message available, the lookahead should be valid now */
+                *pLookAhead = events.LookAhead;
+
+                break;
+            }
+        } else {
+
+                /* this is the standard HIF way.... */
+                /* load the register table */
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  HOST_INT_STATUS_ADDRESS,
+                                  (A_UINT8 *)&pDev->IrqProcRegisters,
+                                  AR6K_IRQ_PROC_REGS_SIZE,
+                                  HIF_RD_SYNC_BYTE_INC,
+                                  NULL);
+
+            if (A_FAILED(status)){
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
+                break;
+            }
+
+                /* check for MBOX data and valid lookahead */
+            if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
+                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
+                {
+                    /* mailbox has a message and the look ahead is valid */
+                    *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+                    break;
+                }
+            }
+
+        }
+
+        timeout--;
+
+        if (timeout <= 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
+            status = A_ERROR;
+
+                /* check if the target asserted */
+            if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+                    /* target signaled an assert, process this pending interrupt
+                     * this will call the target failure handler */
+                DevServiceDebugInterrupt(pDev);
+            }
+
+            break;
+        }
+
+            /* delay a little  */
+        A_MDELAY(DELAY_PER_INTERVAL_MS);
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("  Retry Mbox Poll : %d \n",timeout));
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
+
+    return status;
+}
+
+static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
+{
+    A_STATUS status;
+    A_UINT8  cpu_int_status;
+    A_UINT8  regBuffer[4];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
+    cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
+                     pDev->IrqEnableRegisters.cpu_int_status_enable;
+    A_ASSERT(cpu_int_status);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
+                    cpu_int_status));
+
+        /* Clear the interrupt */
+    pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
+
+        /* set up the register transfer buffer to hit the register 4 times , this is done
+         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+         * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+        /* set W1C value to clear the interrupt, this hits the register first */
+    regBuffer[0] = cpu_int_status;
+        /* the remaining 4 values are set to zero which have no-effect  */
+    regBuffer[1] = 0;
+    regBuffer[2] = 0;
+    regBuffer[3] = 0;
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          CPU_INT_STATUS_ADDRESS,
+                          regBuffer,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+
+static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
+{
+    A_STATUS status;
+    A_UINT8  error_int_status;
+    A_UINT8  regBuffer[4];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
+    error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
+    A_ASSERT(error_int_status);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
+                    error_int_status));
+
+    if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
+        /* Wakeup */
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
+    }
+
+    if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
+        /* Rx Underflow */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
+    }
+
+    if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
+        /* Tx Overflow */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
+    }
+
+        /* Clear the interrupt */
+    pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
+
+        /* set up the register transfer buffer to hit the register 4 times , this is done
+         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+         * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+        /* set W1C value to clear the interrupt, this hits the register first */
+    regBuffer[0] = error_int_status;
+        /* the remaining 4 values are set to zero which have no-effect  */
+    regBuffer[1] = 0;
+    regBuffer[2] = 0;
+    regBuffer[3] = 0;
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          ERROR_INT_STATUS_ADDRESS,
+                          regBuffer,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
+{
+    A_UINT32 dummy;
+    A_STATUS status;
+
+    /* Send a target failure event to the application */
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
+
+    if (pDev->TargetFailureCallback != NULL) {
+        pDev->TargetFailureCallback(pDev->HTCContext);
+    }
+    
+    if (pDev->GMboxEnabled) {
+        DevNotifyGMboxTargetFailure(pDev);
+    }
+
+    /* clear the interrupt , the debug error interrupt is
+     * counter 0 */
+        /* read counter to clear interrupt */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          COUNT_DEC_ADDRESS,
+                          (A_UINT8 *)&dummy,
+                          4,
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+
+    A_ASSERT(status == A_OK);
+    return status;
+}
+
+static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
+{
+    A_UINT8 counter_int_status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
+
+    counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+                         pDev->IrqEnableRegisters.counter_int_status_enable;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
+                    counter_int_status));
+
+        /* Check if the debug interrupt is pending
+         * NOTE: other modules like GMBOX may use the counter interrupt for
+         * credit flow control on other counters, we only need to check for the debug assertion 
+         * counter interrupt */
+    if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+        return DevServiceDebugInterrupt(pDev);
+    }
+
+    return A_OK;
+}
+
+/* callback when our fetch to get interrupt status registers completes */
+static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+    A_UINT32    lookAhead = 0;
+    A_BOOL      otherInts = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+    do {
+
+        if (A_FAILED(pPacket->Status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
+            /* bail out, don't unmask HIF interrupt */
+            break;
+        }
+
+        if (pDev->GetPendingEventsFunc != NULL) {
+                /* the HIF layer collected the information for us */
+            HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
+            if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
+                lookAhead = pEvents->LookAhead;
+                if (0 == lookAhead) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
+                }
+            }
+            if (pEvents->Events & HIF_OTHER_EVENTS) {
+                otherInts = TRUE;
+            }
+        } else {
+                /* standard interrupt table handling.... */
+            AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
+            A_UINT8                 host_int_status;
+
+            host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
+
+            if (host_int_status & (1 << HTC_MAILBOX)) {
+                host_int_status &= ~(1 << HTC_MAILBOX);
+                if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+                        /* mailbox has a message and the look ahead is valid */
+                    lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
+                    if (0 == lookAhead) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
+                    }
+                }
+            }
+
+            if (host_int_status) {
+                    /* there are other interrupts to handle */
+                otherInts = TRUE;
+            }
+        }
+
+        if (otherInts || (lookAhead == 0)) {
+            /* if there are other interrupts to process, we cannot do this in the async handler so
+             * ack the interrupt which will cause our sync handler to run again
+             * if however there are no more messages, we can now ack the interrupt  */
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
+                otherInts, lookAhead));
+            HIFAckInterrupt(pDev->HIFDevice);
+        } else {
+            int      fetched = 0;
+            A_STATUS status;
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
+                    lookAhead));
+                /* lookahead is non-zero and there are no other interrupts to service,
+                 * go get the next message */
+            status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
+            
+            if (A_SUCCESS(status) && !fetched) {
+                    /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */    
+                AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
+                DevAsyncIrqProcessComplete(pDev); 
+            }
+        }
+
+    } while (FALSE);
+
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
+}
+
+/* called by the HTC layer when it wants us to check if the device has any more pending
+ * recv messages, this starts off a series of async requests to read interrupt registers  */
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
+{
+    AR6K_DEVICE  *pDev = (AR6K_DEVICE *)context;
+    A_STATUS      status = A_OK;
+    HTC_PACKET   *pIOPacket;
+
+    /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
+     * cause us to switch contexts */
+
+   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+   do {
+
+        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+                /* break the async processing chain right here, no need to continue.
+                 * The DevDsrHandler() will handle things in a loop when things are driven
+                 * synchronously  */
+            break;
+        }
+        
+            /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+             * the target, if upper layers determine that we are in a low-throughput mode, we can
+             * rely on taking another interrupt rather than re-checking the status registers which can
+             * re-wake the target */
+        if (pDev->RecheckIRQStatusCnt == 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
+                /* ack interrupt */
+            HIFAckInterrupt(pDev->HIFDevice);
+            break;   
+        }
+    
+            /* first allocate one of our HTC packets we created for async I/O
+             * we reuse HTC packet definitions so that we can use the completion mechanism
+             * in DevRWCompletionHandler() */
+        pIOPacket = AR6KAllocIOPacket(pDev);
+
+        if (NULL == pIOPacket) {
+                /* there should be only 1 asynchronous request out at a time to read these registers
+                 * so this should actually never happen */
+            status = A_NO_MEMORY;
+            A_ASSERT(FALSE);
+            break;
+        }
+
+            /* stick in our completion routine when the I/O operation completes */
+        pIOPacket->Completion = DevGetEventAsyncHandler;
+        pIOPacket->pContext = pDev;
+
+        if (pDev->GetPendingEventsFunc) {
+                /* HIF layer has it's own mechanism, pass the IO to it.. */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                                (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
+                                                pIOPacket);
+
+        } else {
+                /* standard way, read the interrupt register table asynchronously again */
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  HOST_INT_STATUS_ADDRESS,
+                                  pIOPacket->pBuffer,
+                                  AR6K_IRQ_PROC_REGS_SIZE,
+                                  HIF_RD_ASYNC_BYTE_INC,
+                                  pIOPacket);
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
+   } while (FALSE);
+
+   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
+
+   return status;
+}
+
+void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev)
+{  
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
+    HIFAckInterrupt(pDev->HIFDevice);
+}
+
+/* process pending interrupts synchronously */
+static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     host_int_status = 0;
+    A_UINT32    lookAhead = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+    /*** NOTE: the HIF implementation guarantees that the context of this call allows
+     *         us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
+     *         can block or switch thread/task ontexts.
+     *         This is a fully schedulable context.
+     * */
+    do {
+
+        if (pDev->IrqEnableRegisters.int_status_enable == 0) {
+            /* interrupt enables have been cleared, do not try to process any pending interrupts that
+             * may result in more bus transactions.  The target may be unresponsive at this
+             * point. */
+             break;    
+        }
+        
+        if (pDev->GetPendingEventsFunc != NULL) {
+            HIF_PENDING_EVENTS_INFO events;
+
+                /* the HIF layer uses a special mechanism to get events
+                 * get this synchronously  */
+            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+                                                &events,
+                                                NULL);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+            if (events.Events & HIF_RECV_MSG_AVAIL) {
+                lookAhead = events.LookAhead;
+                if (0 == lookAhead) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
+                }
+            }
+
+            if (!(events.Events & HIF_OTHER_EVENTS) ||
+                !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
+                    /* no need to read the register table, no other interesting interrupts.
+                     * Some interfaces (like SPI) can shadow interrupt sources without
+                     * requiring the host to do a full table read */
+                break;
+            }
+
+            /* otherwise fall through and read the register table */
+        }
+
+        /*
+         * Read the first 28 bytes of the HTC register table. This will yield us
+         * the value of different int status registers and the lookahead
+         * registers.
+         *    length = sizeof(int_status) + sizeof(cpu_int_status) +
+         *             sizeof(error_int_status) + sizeof(counter_int_status) +
+         *             sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
+         *             sizeof(hole) +  sizeof(rx_lookahead) +
+         *             sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
+         *             sizeof(error_status_enable) +
+         *             sizeof(counter_int_status_enable);
+         *
+        */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              HOST_INT_STATUS_ADDRESS,
+                              (A_UINT8 *)&pDev->IrqProcRegisters,
+                              AR6K_IRQ_PROC_REGS_SIZE,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
+            DevDumpRegisters(pDev,
+                             &pDev->IrqProcRegisters,
+                             &pDev->IrqEnableRegisters);
+        }
+
+            /* Update only those registers that are enabled */
+        host_int_status = pDev->IrqProcRegisters.host_int_status &
+                          pDev->IrqEnableRegisters.int_status_enable;
+
+        if (NULL == pDev->GetPendingEventsFunc) {
+                /* only look at mailbox status if the HIF layer did not provide this function,
+                 * on some HIF interfaces reading the RX lookahead is not valid to do */
+            if (host_int_status & (1 << HTC_MAILBOX)) {
+                    /* mask out pending mailbox value, we use "lookAhead" as the real flag for
+                     * mailbox processing below */
+                host_int_status &= ~(1 << HTC_MAILBOX);
+                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+                        /* mailbox has a message and the look ahead is valid */
+                    lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+                    if (0 == lookAhead) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
+                    }
+                }
+            }
+        } else {
+                /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
+            host_int_status &= ~(1 << HTC_MAILBOX);
+        }
+
+        if (pDev->GMboxEnabled) {
+                /*call GMBOX layer to process any interrupts of interest */
+            status = DevCheckGMboxInterrupts(pDev);  
+        } 
+
+    } while (FALSE);
+
+
+    do {
+
+            /* did the interrupt status fetches succeed? */
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if ((0 == host_int_status) && (0 == lookAhead)) {
+                /* nothing to process, the caller can use this to break out of a loop */
+            *pDone = TRUE;
+            break;
+        }
+
+        if (lookAhead != 0) {
+            int fetched = 0;
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
+                /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
+                 * mailbox...
+                 * When emptying the recv mailbox we use the async handler above called from the
+                 * completion routine of the callers read request. This can improve performance
+                 * by reducing context switching when we rapidly pull packets */
+            status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
+            if (A_FAILED(status)) {
+                break;
+            }
+            
+            if (!fetched) {
+                    /* HTC could not pull any messages out due to lack of resources */
+                    /* force DSR handler to ack the interrupt */
+                *pASyncProcessing = FALSE; 
+                pDev->RecheckIRQStatusCnt = 0;  
+            }
+        }
+
+            /* now handle the rest of them */
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                            (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
+                            host_int_status));
+
+        if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
+                /* CPU Interrupt */
+            status = DevServiceCPUInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+        if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
+                /* Error Interrupt */
+            status = DevServiceErrorInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+        if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
+                /* Counter Interrupt */
+            status = DevServiceCounterInterrupt(pDev);
+            if (A_FAILED(status)){
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+        /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+         * the target, if upper layers determine that we are in a low-throughput mode, we can
+         * rely on taking another interrupt rather than re-checking the status registers which can
+         * re-wake the target.
+         * 
+         * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
+         * be used due to possible side-effects.  For example, SPI requires the host to drain all
+         * messages from the mailbox before exiting the ISR routine. */
+    if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
+        *pDone = TRUE;
+    }
+ 
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
+                *pDone, *pASyncProcessing, status));
+
+    return status;
+}
+
+
+/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
+A_STATUS DevDsrHandler(void *context)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+    A_STATUS    status = A_OK;
+    A_BOOL      done = FALSE;
+    A_BOOL      asyncProc = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+        /* reset the recv counter that tracks when we need to yield from the DSR */
+    pDev->CurrentDSRRecvCount = 0;
+        /* reset counter used to flag a re-scan of IRQ status registers on the target */
+    pDev->RecheckIRQStatusCnt = 0;
+    
+    while (!done) {
+        status = ProcessPendingIRQs(pDev, &done, &asyncProc);
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+            /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
+            asyncProc = FALSE;
+            /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
+             * this has a nice side effect of blocking us until all async read requests are completed.
+             * This behavior is required on some HIF implementations that do not allow ASYNC
+             * processing in interrupt handlers (like Windows CE) */
+            
+            if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
+                /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
+                 * checking for more messages and return */
+                break;    
+            }
+        }
+
+        if (asyncProc) {
+                /* the function performed some async I/O for performance, we
+                   need to exit the ISR immediately, the check below will prevent the interrupt from being
+                   Ack'd while we handle it asynchronously */
+            break;
+        }
+
+    }
+
+    if (A_SUCCESS(status) && !asyncProc) {
+            /* Ack the interrupt only if :
+             *  1. we did not get any errors in processing interrupts
+             *  2. there are no outstanding async processing requests */
+        if (pDev->DSRCanYield) {           
+                /* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
+                 * The HIF layer must ACK the interrupt on behalf of HTC */ 
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
+            HIFAckInterrupt(pDev->HIFDevice);            
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
+    return status;
+}
+
+void DumpAR6KDevState(AR6K_DEVICE *pDev)
+{
+    A_STATUS                    status;
+    AR6K_IRQ_ENABLE_REGISTERS   regs;
+    AR6K_IRQ_PROC_REGISTERS     procRegs;
+
+    LOCK_AR6K(pDev);
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+    UNLOCK_AR6K(pDev);
+    
+        /* load the register table from the device */
+    status = HIFReadWrite(pDev->HIFDevice,
+                          HOST_INT_STATUS_ADDRESS,
+                          (A_UINT8 *)&procRegs,
+                          AR6K_IRQ_PROC_REGS_SIZE,
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+            ("DumpAR6KDevState : Failed to read register table (%d) \n",status));
+        return;
+    }
+            
+    DevDumpRegisters(pDev,&procRegs,&regs);
+    
+    if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
+        pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);        
+    }
+    
+        /* dump any bus state at the HIF layer */
+    HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
+            
+}
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c
new file mode 100644
index 000000000000..f1408082a809
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c
@@ -0,0 +1,752 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_gmbox.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Generic MBOX API implementation
+// 
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hw/mbox_host_reg.h"
+#include "gmboxif.h"
+
+/* 
+ * This file provides management functions and a toolbox for GMBOX protocol modules.  
+ * Only one protocol module can be installed at a time. The determination of which protocol
+ * module is installed is determined at compile time.  
+ * 
+ */
+#ifdef ATH_AR6K_ENABLE_GMBOX
+     /* GMBOX definitions */
+#define GMBOX_INT_STATUS_ENABLE_REG     0x488
+#define GMBOX_INT_STATUS_RX_DATA        (1 << 0)
+#define GMBOX_INT_STATUS_TX_OVERFLOW    (1 << 1)
+#define GMBOX_INT_STATUS_RX_OVERFLOW    (1 << 2)
+
+#define GMBOX_LOOKAHEAD_MUX_REG         0x498
+#define GMBOX_LA_MUX_OVERRIDE_2_3       (1 << 0)
+
+#define AR6K_GMBOX_CREDIT_DEC_ADDRESS   (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER)
+#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS  (COUNT_ADDRESS     + AR6K_GMBOX_CREDIT_SIZE_COUNTER)
+
+
+    /* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */ 
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxIRQActionAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status));
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n"));
+}
+
+static A_STATUS DevGMboxCounterEnableDisable(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+    A_STATUS                  status = A_OK;
+    AR6K_IRQ_ENABLE_REGISTERS regs;
+    HTC_PACKET                *pIOPacket = NULL;  
+    
+    LOCK_AR6K(pDev);
+    
+    if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+        pDev->GMboxInfo.CreditCountIRQEnabled = TRUE;
+        pDev->IrqEnableRegisters.counter_int_status_enable |=
+            COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER);
+        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01);
+    } else {
+        pDev->GMboxInfo.CreditCountIRQEnabled = FALSE;
+        pDev->IrqEnableRegisters.counter_int_status_enable &=
+            ~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER));    
+    }
+        /* copy into our temp area */
+    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+            pIOPacket->pContext = pDev;
+            pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         INT_STATUS_ENABLE_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_IRQ_ENABLE_REGS_SIZE,
+                         HIF_WR_ASYNC_BYTE_INC,
+                         pIOPacket);
+                         
+            pIOPacket = NULL; 
+            break;
+        } 
+
+            /* if we get here we are doing it synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_STATUS_ENABLE_ADDRESS,
+                              &regs.int_status_enable,
+                              AR6K_IRQ_ENABLE_REGS_SIZE,
+                              HIF_WR_SYNC_BYTE_INC,
+                              NULL);    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));    
+    } else {
+        if (!AsyncMode) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" IRQAction Operation (%d) success \n", IrqAction)); 
+        }       
+    }
+    
+    if (pIOPacket != NULL) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+        
+    return status;
+}
+
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+    A_STATUS      status = A_OK;
+    HTC_PACKET    *pIOPacket = NULL;   
+    A_UINT8       GMboxIntControl[4];
+
+    if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+        return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode);
+    } else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) {
+        return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
+    }
+    
+    if (GMBOX_DISABLE_ALL == IrqAction) {
+            /* disable credit IRQ, those are on a different set of registers */
+        DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);    
+    }
+            
+        /* take the lock to protect interrupt enable shadows */
+    LOCK_AR6K(pDev);
+
+    switch (IrqAction) {
+        
+        case GMBOX_DISABLE_ALL:
+            pDev->GMboxControlRegisters.int_status_enable = 0;
+            break;
+        case GMBOX_ERRORS_IRQ_ENABLE:
+            pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW |
+                                                             GMBOX_INT_STATUS_RX_OVERFLOW;
+            break;
+        case GMBOX_RECV_IRQ_ENABLE:
+            pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA;
+            break;
+        case GMBOX_RECV_IRQ_DISABLE:
+            pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA;
+            break;
+        case GMBOX_ACTION_NONE:
+        default:
+            A_ASSERT(FALSE);    
+            break;
+    }
+    
+    GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable;
+    GMboxIntControl[1] = GMboxIntControl[0];
+    GMboxIntControl[2] = GMboxIntControl[0];
+    GMboxIntControl[3] = GMboxIntControl[0];
+    
+    UNLOCK_AR6K(pDev);
+
+    do {
+
+        if (AsyncMode) {
+
+            pIOPacket = AR6KAllocIOPacket(pDev);
+
+            if (NULL == pIOPacket) {
+                status = A_NO_MEMORY;
+                A_ASSERT(FALSE);
+                break;
+            }
+
+                /* copy values to write to our async I/O buffer */
+            A_MEMCPY(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl));
+
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+            pIOPacket->pContext = pDev;
+            pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+                /* write it out asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         GMBOX_INT_STATUS_ENABLE_REG,
+                         pIOPacket->pBuffer,
+                         sizeof(GMboxIntControl),
+                         HIF_WR_ASYNC_BYTE_FIX,
+                         pIOPacket);
+            pIOPacket = NULL;
+            break;
+        }
+
+        /* if we get here we are doing it synchronously */
+
+        status = HIFReadWrite(pDev->HIFDevice,
+                              GMBOX_INT_STATUS_ENABLE_REG,
+                              GMboxIntControl,
+                              sizeof(GMboxIntControl),
+                              HIF_WR_SYNC_BYTE_FIX,
+                              NULL);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));    
+    } else {
+        if (!AsyncMode) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+                    (" IRQAction Operation (%d) success \n", IrqAction)); 
+        }      
+    }
+    
+    if (pIOPacket != NULL) {
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+
+    return status;
+}
+
+void DevCleanupGMbox(AR6K_DEVICE *pDev)
+{
+    if (pDev->GMboxEnabled) {
+        pDev->GMboxEnabled = FALSE;
+        GMboxProtocolUninstall(pDev);        
+    }
+}
+
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     muxControl[4];
+    
+    do {
+        
+        if (0 == pDev->MailBoxInfo.GMboxAddress) {
+            break;    
+        }
+    
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n",
+                    pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize));
+                    
+        status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+       
+            /* write to mailbox look ahead mux control register, we want the
+             * GMBOX lookaheads to appear on lookaheads 2 and 3 
+             * the register is 1-byte wide so we need to hit it 4 times to align the operation 
+             * to 4-bytes */            
+        muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3;
+        muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3;
+                
+        status = HIFReadWrite(pDev->HIFDevice,
+                              GMBOX_LOOKAHEAD_MUX_REG,
+                              muxControl,
+                              sizeof(muxControl),
+                              HIF_WR_SYNC_BYTE_FIX,  /* hit this register 4 times */
+                              NULL);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        status = GMboxProtocolInstall(pDev);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pDev->GMboxEnabled = TRUE;
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev)
+{
+    A_STATUS status = A_OK;
+    A_UINT8  counter_int_status;
+    int      credits;
+    A_UINT8  host_int_status2;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n"));
+     
+    /* the caller guarantees that this is a context that allows for blocking I/O */
+    
+    do {
+        
+        host_int_status2 = pDev->IrqProcRegisters.host_int_status2 &
+                           pDev->GMboxControlRegisters.int_status_enable; 
+                
+        if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n"));  
+            status = A_ECOMM;   
+        }
+        
+        if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n"));  
+            status = A_ECOMM;    
+        }
+        
+        if (A_FAILED(status)) {
+            if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+                pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status);        
+            }
+            break;
+        }
+    
+        if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) {
+            if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) {
+                A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL);
+                status = pDev->GMboxInfo.pMessagePendingCallBack(
+                                pDev->GMboxInfo.pProtocolContext,
+                                (A_UINT8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0],
+                                pDev->IrqProcRegisters.gmbox_rx_avail);
+            }
+        } 
+        
+        if (A_FAILED(status)) {
+           break;                
+        }
+        
+        counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+                             pDev->IrqEnableRegisters.counter_int_status_enable;
+    
+            /* check if credit interrupt is pending */
+        if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) {
+            
+                /* do synchronous read */
+            status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits);
+            
+            if (A_FAILED(status)) {
+                break;    
+            }
+            
+            A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL);
+            status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+                                                             credits,
+                                                             pDev->GMboxInfo.CreditCountIRQEnabled);
+        }
+        
+    } while (FALSE);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status));
+    
+    return status;
+}
+
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength) 
+{
+    A_UINT32 paddedLength;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+    A_STATUS status;
+    A_UINT32 address;
+    
+       /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                ("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                WriteLength,
+                pDev->MailBoxInfo.GMboxAddress,
+                sync ? "SYNC" : "ASYNC"));
+                
+        /* last byte of packet has to hit the EOM marker */
+    address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength;
+    
+    status = HIFReadWrite(pDev->HIFDevice,
+                          address,
+                          pPacket->pBuffer,
+                          paddedLength,     /* the padded length */
+                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    } else {
+        if (status == A_PENDING) {
+            status = A_OK;    
+        }    
+    }
+
+    return status;
+}
+
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength) 
+{
+    
+    A_UINT32 paddedLength;
+    A_STATUS status;
+    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+        /* adjust the length to be a multiple of block size if appropriate */
+    paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength);
+                    
+    if (paddedLength > pPacket->BufferLength) {
+        A_ASSERT(FALSE);
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+                    paddedLength,ReadLength,pPacket->BufferLength));
+        if (pPacket->Completion != NULL) {
+            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+            return A_OK;
+        }
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("DevGMboxRead (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+                (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+                paddedLength,
+                pDev->MailBoxInfo.GMboxAddress,
+                sync ? "SYNC" : "ASYNC"));
+
+    status = HIFReadWrite(pDev->HIFDevice,
+                          pDev->MailBoxInfo.GMboxAddress,
+                          pPacket->pBuffer,
+                          paddedLength,
+                          sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
+
+    if (sync) {
+        pPacket->Status = status;
+    }
+
+    return status;
+}
+
+
+static int ProcessCreditCounterReadBuffer(A_UINT8 *pBuffer, int Length)
+{
+    int     credits = 0;
+    
+    /* theory of how this works:
+     * We read the credit decrement register multiple times on a byte-wide basis. 
+     * The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a 
+     * reasonable chance to acquire "all" pending credits in a single I/O operation. 
+     * 
+     * Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions.
+     * Each non-zero byte represents a single credit decrement (which is a credit given back to the host)
+     * For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following
+     * pattern "could" appear:
+     * 
+     *    0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros
+     *    <--------->                     <----------------------------->
+     *         \_ credits aleady there              \_ target adding 4 more credits
+     * 
+     *    The total available credits would be 7, since there are 7 non-zero bytes in the buffer.
+     * 
+     * */
+    
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer");
+    } 
+        
+    while (Length) {
+        if (*pBuffer != 0) {
+            credits++;    
+        }
+        Length--;
+        pBuffer++;   
+    }  
+    
+    return credits;
+}
+   
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxReadCreditsAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("Read Credit Operation failed! status:%d \n", pPacket->Status));
+    } else {
+        int credits = 0;
+        credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
+        pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+                                                credits,
+                                                pDev->GMboxInfo.CreditCountIRQEnabled);
+        
+        
+    }
+        /* free this IO packet */
+    AR6KFreeIOPacket(pDev,pPacket);
+    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n"));
+}
+
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits)
+{
+    A_STATUS    status = A_OK;
+    HTC_PACKET  *pIOPacket = NULL;  
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC"));
+                                            
+    do {
+        
+        pIOPacket = AR6KAllocIOPacket(pDev);
+
+        if (NULL == pIOPacket) {
+            status = A_NO_MEMORY;
+            A_ASSERT(FALSE);
+            break;
+        }
+        
+        A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE);
+      
+        if (AsyncMode) {   
+                /* stick in our completion routine when the I/O operation completes */
+            pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler;
+            pIOPacket->pContext = pDev;
+                /* read registers asynchronously */
+            HIFReadWrite(pDev->HIFDevice,
+                         AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+                         pIOPacket->pBuffer,
+                         AR6K_REG_IO_BUFFER_SIZE,  /* hit the register multiple times */
+                         HIF_RD_ASYNC_BYTE_FIX,
+                         pIOPacket);
+            pIOPacket = NULL;
+            break;
+        } 
+
+        pIOPacket->Completion = NULL;
+            /* if we get here we are doing it synchronously */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+                              pIOPacket->pBuffer,
+                              AR6K_REG_IO_BUFFER_SIZE,
+                              HIF_RD_SYNC_BYTE_FIX,
+                              NULL);    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" DevGMboxReadCreditCounter failed! status:%d \n", status));          
+    }
+    
+    if (pIOPacket != NULL) {
+        if (A_SUCCESS(status)) {
+                /* sync mode processing */
+            *pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);     
+        }
+        AR6KFreeIOPacket(pDev,pIOPacket);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n", 
+            AsyncMode ? "ASYNC" : "SYNC", status));
+    
+    return status;
+}
+
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize)
+{
+    A_STATUS    status;
+    A_UINT8     buffer[4];
+       
+    status = HIFReadWrite(pDev->HIFDevice,
+                          AR6K_GMBOX_CREDIT_SIZE_ADDRESS,
+                          buffer,
+                          sizeof(buffer),
+                          HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+                          NULL);    
+    
+    if (A_SUCCESS(status)) {
+        if (buffer[0] == 0) {
+            *pCreditSize = 256;    
+        } else {   
+            *pCreditSize = buffer[0];
+        } 
+           
+    } 
+    
+    return status;
+}
+
+void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev)
+{
+        /* Target ASSERTED!!! */
+    if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+        pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE);        
+    }
+}
+
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes)
+{
+
+    A_STATUS                    status = A_OK;
+    AR6K_IRQ_PROC_REGISTERS     procRegs;
+    int                         maxCopy;
+  
+    do {
+            /* on entry the caller provides the length of the lookahead buffer */
+        if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) {
+            A_ASSERT(FALSE);
+            status = A_EINVAL;
+            break;    
+        }
+        
+        maxCopy = *pLookAheadBytes;
+        *pLookAheadBytes = 0;
+            /* load the register table from the device */
+        status = HIFReadWrite(pDev->HIFDevice,
+                              HOST_INT_STATUS_ADDRESS,
+                              (A_UINT8 *)&procRegs,
+                              AR6K_IRQ_PROC_REGS_SIZE,
+                              HIF_RD_SYNC_BYTE_INC,
+                              NULL);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status));
+            break;
+        }
+        
+        if (procRegs.gmbox_rx_avail > 0) {
+            int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail;
+            A_MEMCPY(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes);
+            *pLookAheadBytes = bytes;
+        }
+        
+    } while (FALSE);
+       
+    return status; 
+}
+
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int Signal, int AckTimeoutMS)
+{
+    A_STATUS status = A_OK;
+    int      i;
+    A_UINT8  buffer[4];
+    
+    A_MEMZERO(buffer, sizeof(buffer));
+    
+    do {
+        
+        if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* set the last buffer to do the actual signal trigger */
+        buffer[3] = (1 << Signal);
+        
+        status = HIFReadWrite(pDev->HIFDevice,
+                              INT_WLAN_ADDRESS,
+                              buffer,
+                              sizeof(buffer),
+                              HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+                              NULL);    
+                          
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+    } while (FALSE);
+    
+    
+    if (A_SUCCESS(status)) {        
+            /* now read back the register to see if the bit cleared */
+        while (AckTimeoutMS) {        
+            status = HIFReadWrite(pDev->HIFDevice,
+                                  INT_WLAN_ADDRESS,
+                                  buffer,
+                                  sizeof(buffer),
+                                  HIF_RD_SYNC_BYTE_FIX,
+                                  NULL);    
+                          
+            if (A_FAILED(status)) {
+                break;    
+            }
+                            
+            for (i = 0; i < sizeof(buffer); i++) {
+                if (buffer[i] & (1 << Signal)) {
+                    /* bit is still set */
+                    break;    
+                }   
+            }
+            
+            if (i >= sizeof(buffer)) {
+                /* done */
+                break;    
+            }
+            
+            AckTimeoutMS--;
+            A_MDELAY(1);  
+        }
+        
+        if (0 == AckTimeoutMS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal));
+            status = A_ERROR;    
+        }        
+    }
+    
+    return status;
+    
+}
+
+#endif  //ATH_AR6K_ENABLE_GMBOX
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
new file mode 100644
index 000000000000..ec5c1dc18ed2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
@@ -0,0 +1,1255 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_prot_hciUart.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Protocol module for use in bridging HCI-UART packets over the GMBOX interface
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hci_transport_api.h"
+#include "gmboxif.h"
+#include "ar6000_diag.h"
+#include "hw/apb_map.h"
+#include "hw/mbox_reg.h"
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT     0x02
+#define HCI_UART_SCO_PKT     0x03
+#define HCI_UART_EVENT_PKT   0x04
+
+#define HCI_RECV_WAIT_BUFFERS (1 << 0)
+
+#define HCI_SEND_WAIT_CREDITS (1 << 0)
+
+#define HCI_UART_BRIDGE_CREDIT_SIZE     128
+
+#define CREDIT_POLL_COUNT       256
+
+#define HCI_DELAY_PER_INTERVAL_MS 10 
+#define BTON_TIMEOUT_MS           500
+#define BTOFF_TIMEOUT_MS          500
+#define BAUD_TIMEOUT_MS           1
+
+typedef struct {
+    HCI_TRANSPORT_CONFIG_INFO   HCIConfig;
+    A_BOOL                      HCIAttached;
+    A_BOOL                      HCIStopped;
+    A_UINT32                    RecvStateFlags;
+    A_UINT32                    SendStateFlags;
+    HCI_TRANSPORT_PACKET_TYPE   WaitBufferType;
+    HTC_PACKET_QUEUE            SendQueue;         /* write queue holding HCI Command and ACL packets */
+    HTC_PACKET_QUEUE            HCIACLRecvBuffers;  /* recv queue holding buffers for incomming ACL packets */
+    HTC_PACKET_QUEUE            HCIEventBuffers;    /* recv queue holding buffers for incomming event packets */
+    AR6K_DEVICE                 *pDev;
+    A_MUTEX_T                   HCIRxLock;
+    A_MUTEX_T                   HCITxLock;
+    int                         CreditsMax;
+    int                         CreditsConsumed;
+    int                         CreditsAvailable;
+    int                         CreditSize;
+    int                         CreditsCurrentSeek;
+    int                         SendProcessCount;
+} GMBOX_PROTO_HCI_UART;
+
+#define LOCK_HCI_RX(t)   A_MUTEX_LOCK(&(t)->HCIRxLock);
+#define UNLOCK_HCI_RX(t) A_MUTEX_UNLOCK(&(t)->HCIRxLock);
+#define LOCK_HCI_TX(t)   A_MUTEX_LOCK(&(t)->HCITxLock);
+#define UNLOCK_HCI_TX(t) A_MUTEX_UNLOCK(&(t)->HCITxLock);
+
+#define DO_HCI_RECV_INDICATION(p,pt) \
+{   AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI: Indicate Recv on packet:0x%X status:%d len:%d type:%d \n",  \
+      (A_UINT32)(pt),(pt)->Status, A_SUCCESS((pt)->Status) ? (pt)->ActualLength : 0, HCI_GET_PACKET_TYPE(pt))); \
+    (p)->HCIConfig.pHCIPktRecv((p)->HCIConfig.pContext, (pt));                                 \
+}
+
+#define DO_HCI_SEND_INDICATION(p,pt) \
+{   AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Indicate Send on packet:0x%X status:%d type:%d \n",  \
+            (A_UINT32)(pt),(pt)->Status,HCI_GET_PACKET_TYPE(pt)));                             \
+    (p)->HCIConfig.pHCISendComplete((p)->HCIConfig.pContext, (pt));                            \
+}
+    
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+static void HCIUartCleanup(GMBOX_PROTO_HCI_UART *pProtocol)
+{
+    A_ASSERT(pProtocol != NULL);
+    
+    A_MUTEX_DELETE(&pProtocol->HCIRxLock);
+    A_MUTEX_DELETE(&pProtocol->HCITxLock);
+        
+    A_FREE(pProtocol);    
+}
+
+static A_STATUS InitTxCreditState(GMBOX_PROTO_HCI_UART *pProt)
+{
+    A_STATUS    status;
+    int         credits;
+    int         creditPollCount = CREDIT_POLL_COUNT;
+    A_BOOL      gotCredits = FALSE;
+
+    pProt->CreditsConsumed = 0;
+    
+    do {    
+        
+        if (pProt->CreditsMax != 0) {
+            /* we can only call this only once per target reset */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI: InitTxCreditState - already called!  \n"));
+            A_ASSERT(FALSE);
+            status = A_EINVAL;
+            break; 
+        }
+        
+        /* read the credit counter. At startup the target will set the credit counter
+         * to the max available, we read this in a loop because it may take
+         * multiple credit counter reads to get all credits  */
+                 
+        while (creditPollCount) {
+            
+            credits = 0;
+
+            status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);
+    
+            if (A_FAILED(status)) {
+                break;    
+            }
+            
+            if (!gotCredits && (0 == credits)) {
+                creditPollCount--;
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: credit is 0, retrying (%d)  \n",creditPollCount));
+                A_MDELAY(HCI_DELAY_PER_INTERVAL_MS);
+                continue;  
+            } else {
+                gotCredits = TRUE;    
+            }
+            
+            if (0 == credits) {
+                break;    
+            }
+            
+            pProt->CreditsMax += credits;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (0 == creditPollCount) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("** HCI : Failed to get credits! GMBOX Target was not available \n"));        
+            status = A_ERROR;
+            break;
+        }
+        
+            /* now get the size */
+        status = DevGMboxReadCreditSize(pProt->pDev, &pProt->CreditSize);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+               
+    } while (FALSE);
+    
+    if (A_SUCCESS(status)) {
+        pProt->CreditsAvailable = pProt->CreditsMax;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI : InitTxCreditState - credits avail: %d, size: %d \n",
+            pProt->CreditsAvailable, pProt->CreditSize));    
+    }    
+    
+    return status;
+}
+
+static A_STATUS CreditsAvailableCallback(void *pContext, int Credits, A_BOOL CreditIRQEnabled)
+{
+    GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;    
+    A_BOOL               enableCreditIrq = FALSE;   
+    A_BOOL               disableCreditIrq = FALSE;
+    A_BOOL               doPendingSends = FALSE;
+    A_STATUS             status = A_OK;
+    
+    /** this callback is called under 2 conditions:
+     *   1. The credit IRQ interrupt was enabled and signaled.
+     *   2. A credit counter read completed.
+     * 
+     *   The function must not assume that the calling context can block !
+     */
+     
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback (Credits:%d, IRQ:%s) \n",
+                Credits, CreditIRQEnabled ? "ON" : "OFF"));
+    
+    LOCK_HCI_RX(pProt);
+    
+    do {
+        
+        if (0 == Credits) {
+            if (!CreditIRQEnabled) {
+                    /* enable credit IRQ */
+                enableCreditIrq = TRUE;    
+            }
+            break;
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: current credit state, consumed:%d available:%d max:%d seek:%d\n",
+                         pProt->CreditsConsumed, 
+                         pProt->CreditsAvailable,  
+                         pProt->CreditsMax,
+                         pProt->CreditsCurrentSeek));
+                         
+        pProt->CreditsAvailable += Credits;
+        A_ASSERT(pProt->CreditsAvailable <= pProt->CreditsMax);
+        pProt->CreditsConsumed  -= Credits;
+        A_ASSERT(pProt->CreditsConsumed >= 0);
+            
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state, consumed:%d available:%d max:%d seek:%d\n",
+                         pProt->CreditsConsumed, 
+                         pProt->CreditsAvailable,  
+                         pProt->CreditsMax,
+                         pProt->CreditsCurrentSeek));
+        
+        if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+                /* we have enough credits to fullfill at least 1 packet waiting in the queue */
+            pProt->CreditsCurrentSeek = 0;
+            pProt->SendStateFlags &= ~HCI_SEND_WAIT_CREDITS;  
+            doPendingSends = TRUE;  
+            if (CreditIRQEnabled) {
+                    /* credit IRQ was enabled, we shouldn't need it anymore */
+                disableCreditIrq = TRUE;    
+            }      
+        } else {
+                /* not enough credits yet, enable credit IRQ if we haven't already */
+            if (!CreditIRQEnabled) {               
+                enableCreditIrq = TRUE;    
+            }    
+        }
+                      
+    } while (FALSE);
+    
+    UNLOCK_HCI_RX(pProt);
+
+    if (enableCreditIrq) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Enabling credit count IRQ...\n"));
+            /* must use async only */
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_ENABLE, PROC_IO_ASYNC);    
+    } else if (disableCreditIrq) {
+            /* must use async only */
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Disabling credit count IRQ...\n"));
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_DISABLE, PROC_IO_ASYNC); 
+    }
+       
+    if (doPendingSends) {
+        HCITrySend(pProt, NULL, FALSE);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback \n"));
+    return status;
+}
+
+static INLINE void NotifyTransportFailure(GMBOX_PROTO_HCI_UART  *pProt, A_STATUS status)
+{
+    if (pProt->HCIConfig.TransportFailure != NULL) {
+        pProt->HCIConfig.TransportFailure(pProt->HCIConfig.pContext, status);
+    }
+}
+
+static void FailureCallback(void *pContext, A_STATUS Status)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)pContext; 
+    
+        /* target assertion occured */           
+    NotifyTransportFailure(pProt, Status);  
+}
+
+static void StateDumpCallback(void *pContext)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("============ HCIUart State ======================\n"));    
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("RecvStateFlags   :  0x%X \n",pProt->RecvStateFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendStateFlags   :  0x%X \n",pProt->SendStateFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("WaitBufferType   :  %d   \n",pProt->WaitBufferType));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendQueue Depth  :  %d   \n",HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsMax       :  %d   \n",pProt->CreditsMax));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsConsumed  :  %d   \n",pProt->CreditsConsumed));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsAvailable :  %d   \n",pProt->CreditsAvailable));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("==================================================\n"));
+}
+
+static A_STATUS HCIUartMessagePending(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes)
+{
+    GMBOX_PROTO_HCI_UART        *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+    A_STATUS                    status = A_OK;
+    int                         totalRecvLength = 0;
+    HCI_TRANSPORT_PACKET_TYPE   pktType = HCI_PACKET_INVALID;
+    A_BOOL                      recvRefillCalled = FALSE;
+    A_BOOL                      blockRecv = FALSE;
+    HTC_PACKET                  *pPacket = NULL;
+    
+    /** caller guarantees that this is a fully block-able context (synch I/O is allowed) */
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCIUartMessagePending Lookahead Bytes:%d \n",ValidBytes));
+    
+    LOCK_HCI_RX(pProt);
+        
+    do {
+    
+        if (ValidBytes < 3) {
+                /* not enough for ACL or event header */
+            break;    
+        }    
+        
+        if ((LookAheadBytes[0] == HCI_UART_ACL_PKT) && (ValidBytes < 5)) {
+                /* not enough for ACL data header */
+            break;    
+        }
+                
+        switch (LookAheadBytes[0]) {       
+            case HCI_UART_EVENT_PKT:
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+                        LookAheadBytes[1], LookAheadBytes[2]));
+                totalRecvLength = LookAheadBytes[2];
+                totalRecvLength += 3; /* add type + event code + length field */
+                pktType = HCI_EVENT_TYPE;      
+                break;
+            case HCI_UART_ACL_PKT:                
+                totalRecvLength = (LookAheadBytes[4] << 8) | LookAheadBytes[3];                
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI ACL: conn:0x%X length: %d \n",
+                        ((LookAheadBytes[2] & 0xF0) << 8) | LookAheadBytes[1], totalRecvLength));
+                totalRecvLength += 5; /* add type + connection handle + length field */
+                pktType = HCI_ACL_TYPE;           
+                break;        
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",LookAheadBytes[0]));
+                status = A_EPROTO;
+                break;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+                
+        if (pProt->HCIConfig.pHCIPktRecvAlloc != NULL) {
+            UNLOCK_HCI_RX(pProt);
+                /* user is using a per-packet allocation callback */
+            pPacket = pProt->HCIConfig.pHCIPktRecvAlloc(pProt->HCIConfig.pContext,
+                                                        pktType,
+                                                        totalRecvLength);
+            LOCK_HCI_RX(pProt);
+    
+        } else {
+            HTC_PACKET_QUEUE *pQueue;
+                /* user is using a refill handler that can refill multiple HTC buffers */
+            
+                /* select buffer queue */
+            if (pktType == HCI_ACL_TYPE) {
+                pQueue = &pProt->HCIACLRecvBuffers;    
+            } else {
+                pQueue = &pProt->HCIEventBuffers;              
+            }    
+            
+            if (HTC_QUEUE_EMPTY(pQueue)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d has no buffers available calling allocation handler \n", 
+                    pktType));
+                    /* check for refill handler */
+                if (pProt->HCIConfig.pHCIPktRecvRefill != NULL) {
+                    recvRefillCalled = TRUE;
+                    UNLOCK_HCI_RX(pProt);
+                        /* call the re-fill handler */
+                    pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+                                                       pktType,
+                                                       0);
+                    LOCK_HCI_RX(pProt);
+                        /* check if we have more buffers */
+                    pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                        /* fall through */
+                }
+            } else {
+                pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("HCI pkt type: %d now has %d recv buffers left \n", 
+                            pktType, HTC_PACKET_QUEUE_DEPTH(pQueue)));    
+            }
+        }
+     
+        if (NULL == pPacket) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d has no buffers available stopping recv...\n", pktType));
+                /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+            pProt->RecvStateFlags |= HCI_RECV_WAIT_BUFFERS;
+            pProt->WaitBufferType = pktType;
+            blockRecv = TRUE;
+            break;
+        }
+        
+        if (totalRecvLength > (int)pPacket->BufferLength) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI-UART pkt: %d requires %d bytes (%d buffer bytes avail) ! \n",
+                LookAheadBytes[0], totalRecvLength, pPacket->BufferLength));
+            status = A_EINVAL;
+            break;
+        }
+        
+    } while (FALSE);
+    
+    UNLOCK_HCI_RX(pProt);
+    
+        /* locks are released, we can go fetch the packet */
+        
+    do {
+        
+        if (A_FAILED(status) || (NULL == pPacket)) {
+            break;    
+        } 
+        
+            /* do this synchronously, we don't need to be fast here */
+        pPacket->Completion = NULL;
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI : getting recv packet len:%d hci-uart-type: %s \n",
+                totalRecvLength, (LookAheadBytes[0] == HCI_UART_EVENT_PKT) ? "EVENT" : "ACL"));
+                
+        status = DevGMboxRead(pProt->pDev, pPacket, totalRecvLength);     
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (pPacket->pBuffer[0] != LookAheadBytes[0]) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not contain expected packet type: %d ! \n",
+                        pPacket->pBuffer[0]));
+            status = A_EPROTO;
+            break;   
+        }
+        
+        if (pPacket->pBuffer[0] == HCI_UART_EVENT_PKT) {
+                /* validate event header fields */
+            if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+                (pPacket->pBuffer[2] != LookAheadBytes[2])) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+                DebugDumpBytes(LookAheadBytes, 3, "Expected HCI-UART Header");  
+                DebugDumpBytes(pPacket->pBuffer, 3, "** Bad HCI-UART Header");  
+                status = A_EPROTO;
+                break;       
+            }   
+        } else if (pPacket->pBuffer[0] == HCI_UART_ACL_PKT) {
+                /* validate acl header fields */
+            if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+                (pPacket->pBuffer[2] != LookAheadBytes[2]) ||
+                (pPacket->pBuffer[3] != LookAheadBytes[3]) ||
+                (pPacket->pBuffer[4] != LookAheadBytes[4])) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+                DebugDumpBytes(LookAheadBytes, 5, "Expected HCI-UART Header");  
+                DebugDumpBytes(pPacket->pBuffer, 5, "** Bad HCI-UART Header");  
+                status = A_EPROTO;
+                break;       
+            }   
+        }
+        
+            /* adjust buffer to move past packet ID */
+        pPacket->pBuffer++;
+        pPacket->ActualLength = totalRecvLength - 1;
+        pPacket->Status = A_OK;
+            /* indicate packet */
+        DO_HCI_RECV_INDICATION(pProt,pPacket);
+        pPacket = NULL;
+        
+            /* check if we need to refill recv buffers */        
+        if ((pProt->HCIConfig.pHCIPktRecvRefill != NULL) && !recvRefillCalled) {           
+            HTC_PACKET_QUEUE *pQueue;
+            int              watermark;
+
+            if (pktType == HCI_ACL_TYPE) {
+                watermark = pProt->HCIConfig.ACLRecvBufferWaterMark;
+                pQueue = &pProt->HCIACLRecvBuffers;    
+            } else {
+                watermark = pProt->HCIConfig.EventRecvBufferWaterMark;     
+                pQueue = &pProt->HCIEventBuffers;        
+            }    
+            
+            if (HTC_PACKET_QUEUE_DEPTH(pQueue) < watermark) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("** HCI pkt type: %d watermark hit (%d) current:%d \n", 
+                    pktType, watermark, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+                    /* call the re-fill handler */
+                pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+                                                   pktType,
+                                                   HTC_PACKET_QUEUE_DEPTH(pQueue));
+            }
+        }   
+        
+    } while (FALSE);
+        
+        /* check if we need to disable the reciever */
+    if (A_FAILED(status) || blockRecv) {
+        DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_DISABLE, PROC_IO_SYNC); 
+    }
+    
+        /* see if we need to recycle the recv buffer */    
+    if (A_FAILED(status) && (pPacket != NULL)) {
+        HTC_PACKET_QUEUE queue;
+        
+        if (A_EPROTO == status) {
+            DebugDumpBytes(pPacket->pBuffer, totalRecvLength, "Bad HCI-UART Recv packet");    
+        }
+            /* recycle packet */
+        HTC_PACKET_RESET_RX(pPacket);
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket);
+        HCI_TransportAddReceivePkts(pProt,&queue);
+        NotifyTransportFailure(pProt,status);    
+    }
+    
+ 
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCIUartMessagePending \n"));
+    
+    return status;
+}
+
+static void HCISendPacketCompletion(void *Context, HTC_PACKET *pPacket)
+{
+    GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)Context;
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion (pPacket:0x%X) \n",(A_UINT32)pPacket));
+    
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Send Packet (0x%X) failed: %d , len:%d \n",
+            (A_UINT32)pPacket, pPacket->Status, pPacket->ActualLength));        
+    }
+    
+    DO_HCI_SEND_INDICATION(pProt,pPacket);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion \n"));
+}
+
+static A_STATUS SeekCreditsSynch(GMBOX_PROTO_HCI_UART *pProt)
+{
+    A_STATUS status = A_OK;
+    int      credits;
+    int      retry = 100;
+    
+    while (TRUE) {                
+        credits = 0;
+        status =  DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);   
+        if (A_FAILED(status)) {
+            break;    
+        }
+        LOCK_HCI_TX(pProt);
+        pProt->CreditsAvailable += credits;        
+        pProt->CreditsConsumed -= credits;        
+        if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+            pProt->CreditsCurrentSeek = 0;
+            UNLOCK_HCI_TX(pProt);
+            break;    
+        }
+        UNLOCK_HCI_TX(pProt);
+        retry--;
+        if (0 == retry) {
+            status = A_EBUSY;
+            break;    
+        }
+        A_MDELAY(20);
+    }   
+    
+    return status;
+}
+
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{   
+    A_STATUS    status = A_OK;
+    int         transferLength;
+    int         creditsRequired, remainder;
+    A_UINT8     hciUartType;
+    A_BOOL      synchSendComplete = FALSE;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCITrySend (pPacket:0x%X) %s \n",(A_UINT32)pPacket,
+            Synchronous ? "SYNC" :"ASYNC"));
+    
+    LOCK_HCI_TX(pProt);
+     
+        /* increment write processing count on entry */    
+    pProt->SendProcessCount++;
+        
+    do {
+                                             
+        if (pProt->HCIStopped) {
+            status = A_ECANCELED;
+            break;     
+        }   
+         
+        if (pPacket != NULL) {  
+                /* packet was supplied */     
+            if (Synchronous) {
+                    /* in synchronous mode, the send queue can only hold 1 packet */
+                if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+                    status = A_EBUSY;
+                    A_ASSERT(FALSE);
+                    break;    
+                }             
+                
+                if (pProt->SendProcessCount > 1) {
+                        /* another thread or task is draining the TX queues  */
+                    status = A_EBUSY;
+                    A_ASSERT(FALSE);
+                    break;
+                } 
+                  
+                HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+                
+            } else {
+                    /* see if adding this packet hits the max depth (asynchronous mode only) */
+                if ((pProt->HCIConfig.MaxSendQueueDepth > 0) && 
+                    ((HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue) + 1) >= pProt->HCIConfig.MaxSendQueueDepth)) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("HCI Send queue is full, Depth:%d, Max:%d \n",
+                            HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue), 
+                            pProt->HCIConfig.MaxSendQueueDepth));
+                        /* queue will be full, invoke any callbacks to determine what action to take */
+                    if (pProt->HCIConfig.pHCISendFull != NULL) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, 
+                                    ("HCI : Calling driver's send full callback.... \n"));
+                        if (pProt->HCIConfig.pHCISendFull(pProt->HCIConfig.pContext,
+                                                          pPacket) == HCI_SEND_FULL_DROP) {
+                                /* drop it */
+                            status = A_NO_RESOURCE;      
+                            break;
+                        }
+                    }               
+                }
+          
+                HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+            }
+
+        }
+               
+        if (pProt->SendStateFlags & HCI_SEND_WAIT_CREDITS) {
+            break;   
+        }
+
+        if (pProt->SendProcessCount > 1) {
+                /* another thread or task is draining the TX queues  */
+            break;
+        }
+    
+        /***** beyond this point only 1 thread may enter ******/
+           
+        /* now drain the send queue for transmission as long as we have enough
+         * credits */
+        while (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+            
+            pPacket = HTC_PACKET_DEQUEUE(&pProt->SendQueue);
+
+            switch (HCI_GET_PACKET_TYPE(pPacket)) {            
+                case HCI_COMMAND_TYPE:
+                    hciUartType = HCI_UART_COMMAND_PKT;
+                    break;
+                case HCI_ACL_TYPE:
+                    hciUartType = HCI_UART_ACL_PKT;
+                    break;
+                default:
+                    status = A_EINVAL;
+                    A_ASSERT(FALSE);
+                    break;
+            }
+                       
+            if (A_FAILED(status)) {
+                break;   
+            }
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Got head packet:0x%X , Type:%d  Length: %d Remaining Queue Depth: %d\n",
+                (A_UINT32)pPacket, HCI_GET_PACKET_TYPE(pPacket), pPacket->ActualLength, 
+                HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+        
+            transferLength = 1;  /* UART type header is 1 byte */
+            transferLength += pPacket->ActualLength;
+            transferLength = DEV_CALC_SEND_PADDED_LEN(pProt->pDev, transferLength);
+                   
+                /* figure out how many credits this message requires */
+            creditsRequired = transferLength / pProt->CreditSize;
+            remainder = transferLength % pProt->CreditSize;
+
+            if (remainder) {
+                creditsRequired++;
+            }
+
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Creds Required:%d   Got:%d\n",
+                            creditsRequired, pProt->CreditsAvailable));
+            
+            if (creditsRequired > pProt->CreditsAvailable) {
+                if (Synchronous) {
+                        /* in synchronous mode we need to seek credits in synchronously */
+                    pProt->CreditsCurrentSeek = creditsRequired;
+                    UNLOCK_HCI_TX(pProt);
+                    status = SeekCreditsSynch(pProt);
+                    LOCK_HCI_TX(pProt);
+                    if (A_FAILED(status)) {
+                        break;    
+                    }                    
+                    /* fall through and continue processing this send op */                    
+                } else {
+                        /* not enough credits, queue back to the head */
+                    HTC_PACKET_ENQUEUE_TO_HEAD(&pProt->SendQueue,pPacket);
+                        /* waiting for credits */
+                    pProt->SendStateFlags |= HCI_SEND_WAIT_CREDITS;
+                        /* provide a hint to reduce attempts to re-send if credits are dribbling back
+                         * this hint is the short fall of credits */
+                    pProt->CreditsCurrentSeek = creditsRequired;
+                    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: packet:0x%X placed back in queue. head packet needs: %d credits \n",
+                                        (A_UINT32)pPacket, pProt->CreditsCurrentSeek));
+                    pPacket = NULL;
+                    UNLOCK_HCI_TX(pProt);
+                    
+                        /* schedule a credit counter read, our CreditsAvailableCallback callback will be called
+                         * with the result */   
+                    DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_ASYNC, NULL);
+                             
+                    LOCK_HCI_TX(pProt);
+                    break;              
+                }          
+            }
+        
+                /* caller guarantees some head room */
+            pPacket->pBuffer--;
+            pPacket->pBuffer[0] = hciUartType;
+            
+            pProt->CreditsAvailable -= creditsRequired;
+            pProt->CreditsConsumed  += creditsRequired;
+            A_ASSERT(pProt->CreditsConsumed <= pProt->CreditsMax);
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state: consumed:%d   available:%d max:%d\n",
+                             pProt->CreditsConsumed, pProt->CreditsAvailable,  pProt->CreditsMax));
+            
+            UNLOCK_HCI_TX(pProt);   
+            
+                /* write it out */   
+            if (Synchronous) {                            
+                pPacket->Completion = NULL;
+                pPacket->pContext = NULL;         
+            } else {                       
+                pPacket->Completion = HCISendPacketCompletion;
+                pPacket->pContext = pProt;    
+            }
+            
+            status = DevGMboxWrite(pProt->pDev,pPacket,transferLength);            
+            if (Synchronous) {            
+                synchSendComplete = TRUE;
+            } else {
+                pPacket = NULL;    
+            }
+            
+            LOCK_HCI_TX(pProt);
+              
+        }
+        
+    } while (FALSE);
+        
+    pProt->SendProcessCount--;
+    A_ASSERT(pProt->SendProcessCount >= 0);
+    UNLOCK_HCI_TX(pProt);
+    
+    if (Synchronous) {
+        A_ASSERT(pPacket != NULL);
+        if (A_SUCCESS(status) && (!synchSendComplete)) {
+            status = A_EBUSY;
+            A_ASSERT(FALSE);
+            LOCK_HCI_TX(pProt);
+            if (pPacket->ListLink.pNext != NULL) {
+                    /* remove from the queue */
+                HTC_PACKET_REMOVE(&pProt->SendQueue,pPacket);
+            }
+            UNLOCK_HCI_TX(pProt);
+        }
+    } else {   
+        if (A_FAILED(status) && (pPacket != NULL)) {
+            pPacket->Status = status;
+            DO_HCI_SEND_INDICATION(pProt,pPacket); 
+        }
+    }
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HCITrySend:  \n"));
+    return status;    
+}
+
+static void FlushSendQueue(GMBOX_PROTO_HCI_UART *pProt)
+{
+    HTC_PACKET          *pPacket;
+    HTC_PACKET_QUEUE    discardQueue;
+    
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+    
+    LOCK_HCI_TX(pProt);
+    
+    if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->SendQueue);    
+    }
+    
+    UNLOCK_HCI_TX(pProt);
+    
+        /* discard packets */
+    while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);   
+        pPacket->Status = A_ECANCELED;
+        DO_HCI_SEND_INDICATION(pProt,pPacket);
+    }
+    
+}
+
+static void FlushRecvBuffers(GMBOX_PROTO_HCI_UART *pProt)
+{
+    HTC_PACKET_QUEUE discardQueue;
+    HTC_PACKET *pPacket;
+    
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+    
+    LOCK_HCI_RX(pProt);
+        /*transfer list items from ACL and event buffer queues to the discard queue */       
+    if (!HTC_QUEUE_EMPTY(&pProt->HCIACLRecvBuffers)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIACLRecvBuffers);    
+    }
+    if (!HTC_QUEUE_EMPTY(&pProt->HCIEventBuffers)) {
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIEventBuffers);    
+    }
+    UNLOCK_HCI_RX(pProt);
+    
+        /* now empty the discard queue */
+    while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);      
+        pPacket->Status = A_ECANCELED;
+        DO_HCI_RECV_INDICATION(pProt,pPacket);
+    }
+    
+}
+
+/*** protocol module install entry point ***/
+
+A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev)
+{
+    A_STATUS                status = A_OK;
+    GMBOX_PROTO_HCI_UART    *pProtocol = NULL;
+        
+    do {
+        
+        pProtocol = A_MALLOC(sizeof(GMBOX_PROTO_HCI_UART));
+        
+        if (NULL == pProtocol) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        A_MEMZERO(pProtocol, sizeof(*pProtocol));
+        pProtocol->pDev = pDev;
+        INIT_HTC_PACKET_QUEUE(&pProtocol->SendQueue);
+        INIT_HTC_PACKET_QUEUE(&pProtocol->HCIACLRecvBuffers);
+        INIT_HTC_PACKET_QUEUE(&pProtocol->HCIEventBuffers);
+        A_MUTEX_INIT(&pProtocol->HCIRxLock);
+        A_MUTEX_INIT(&pProtocol->HCITxLock);
+     
+    } while (FALSE);
+    
+    if (A_SUCCESS(status)) {
+        LOCK_AR6K(pDev);
+        DEV_GMBOX_SET_PROTOCOL(pDev,
+                               HCIUartMessagePending,
+                               CreditsAvailableCallback,
+                               FailureCallback,
+                               StateDumpCallback,
+                               pProtocol);
+        UNLOCK_AR6K(pDev);
+    } else {
+        if (pProtocol != NULL) {
+            HCIUartCleanup(pProtocol);    
+        }    
+    }
+    
+    return status;    
+}
+
+/*** protocol module uninstall entry point ***/
+void GMboxProtocolUninstall(AR6K_DEVICE *pDev)
+{
+    GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+    
+    if (pProtocol != NULL) {
+        
+            /* notify anyone attached */    
+        if (pProtocol->HCIAttached) {
+            A_ASSERT(pProtocol->HCIConfig.TransportRemoved != NULL);
+            pProtocol->HCIConfig.TransportRemoved(pProtocol->HCIConfig.pContext);
+            pProtocol->HCIAttached = FALSE;    
+        }
+        
+        HCIUartCleanup(pProtocol);
+        DEV_GMBOX_SET_PROTOCOL(pDev,NULL,NULL,NULL,NULL,NULL);       
+    }
+    
+}
+
+static A_STATUS NotifyTransportReady(GMBOX_PROTO_HCI_UART  *pProt)
+{
+    HCI_TRANSPORT_PROPERTIES props;
+    A_STATUS                 status = A_OK;
+    
+    do {
+        
+        A_MEMZERO(&props,sizeof(props));
+        
+            /* HCI UART only needs one extra byte at the head to indicate the packet TYPE */
+        props.HeadRoom = 1;
+        props.TailRoom = 0;
+        props.IOBlockPad = pProt->pDev->BlockSize;
+        if (pProt->HCIAttached) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI: notifying attached client to transport... \n"));    
+            A_ASSERT(pProt->HCIConfig.TransportReady != NULL);
+            status = pProt->HCIConfig.TransportReady(pProt,
+                                                    &props,
+                                                    pProt->HCIConfig.pContext);
+        }
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+/***********  HCI UART protocol implementation ************************************************/
+
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo)
+{
+    GMBOX_PROTO_HCI_UART  *pProtocol = NULL; 
+    AR6K_DEVICE           *pDev;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportAttach \n"));
+    
+    pDev = HTCGetAR6KDevice(HTCHandle);
+    
+    LOCK_AR6K(pDev);
+    
+    do {
+        
+        pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+        
+        if (NULL == pProtocol) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not installed! \n"));
+            break;
+        }
+        
+        if (pProtocol->HCIAttached) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol already attached! \n"));
+            break;    
+        }
+        
+        A_MEMCPY(&pProtocol->HCIConfig, pInfo, sizeof(HCI_TRANSPORT_CONFIG_INFO));
+        
+        A_ASSERT(pProtocol->HCIConfig.pHCIPktRecv != NULL);
+        A_ASSERT(pProtocol->HCIConfig.pHCISendComplete != NULL);
+        
+        pProtocol->HCIAttached = TRUE;
+        
+    } while (FALSE);
+    
+    UNLOCK_AR6K(pDev);
+    
+    if (pProtocol != NULL) {
+            /* TODO ... should we use a worker? */
+        NotifyTransportReady(pProtocol);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach (0x%X) \n",(A_UINT32)pProtocol));
+    return (HCI_TRANSPORT_HANDLE)pProtocol;
+}
+
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    GMBOX_PROTO_HCI_UART  *pProtocol = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    AR6K_DEVICE           *pDev = pProtocol->pDev;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportDetach \n"));
+    
+    LOCK_AR6K(pDev);
+    if (!pProtocol->HCIAttached) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not attached! \n"));
+        UNLOCK_AR6K(pDev);
+        return;
+    }
+    pProtocol->HCIAttached = FALSE;
+    UNLOCK_AR6K(pDev);
+    
+    HCI_TransportStop(HciTrans);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach \n"));
+}
+
+A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    A_STATUS              status = A_OK;
+    A_BOOL                unblockRecv = FALSE;
+    HTC_PACKET            *pPacket;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCI_TransportAddReceivePkt \n"));
+    
+    LOCK_HCI_RX(pProt);
+   
+    do {
+         
+        if (pProt->HCIStopped) {
+            status = A_ECANCELED;
+            break;    
+        }
+        
+        pPacket = HTC_GET_PKT_AT_HEAD(pQueue);
+        
+        if (NULL == pPacket) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv packet added, type :%d, len:%d num:%d \n",
+                        HCI_GET_PACKET_TYPE(pPacket), pPacket->BufferLength, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+                        
+        if (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) {
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIEventBuffers, pQueue);
+        } else if (HCI_GET_PACKET_TYPE(pPacket) == HCI_ACL_TYPE) {
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIACLRecvBuffers, pQueue);    
+        } else {
+            status = A_EINVAL;
+            break;    
+        }
+        
+        if (pProt->RecvStateFlags & HCI_RECV_WAIT_BUFFERS) {
+            if (pProt->WaitBufferType == HCI_GET_PACKET_TYPE(pPacket)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv was blocked on packet type :%d, unblocking.. \n",
+                        pProt->WaitBufferType));
+                pProt->RecvStateFlags &= ~HCI_RECV_WAIT_BUFFERS;
+                pProt->WaitBufferType = HCI_PACKET_INVALID;
+                unblockRecv = TRUE;
+            }
+        }
+        
+    } while (FALSE);
+    
+    UNLOCK_HCI_RX(pProt);
+    
+    if (A_FAILED(status)) {
+        while (!HTC_QUEUE_EMPTY(pQueue)) {
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);      
+            pPacket->Status = A_ECANCELED;
+            DO_HCI_RECV_INDICATION(pProt,pPacket);
+        }   
+    }
+    
+    if (unblockRecv) {
+        DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_ASYNC);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCI_TransportAddReceivePkt \n"));
+    
+    return A_OK;    
+}
+
+A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;  
+    
+    return HCITrySend(pProt,pPacket,Synchronous);
+}
+
+void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; 
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStop \n"));
+     
+    LOCK_AR6K(pProt->pDev);
+    if (pProt->HCIStopped) {
+        UNLOCK_AR6K(pProt->pDev);
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+        return;    
+    }
+    pProt->HCIStopped = TRUE;
+    UNLOCK_AR6K(pProt->pDev);
+     
+        /* disable interrupts */
+    DevGMboxIRQAction(pProt->pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+    FlushSendQueue(pProt);
+    FlushRecvBuffers(pProt);
+    
+        /* signal bridge side to power down BT */
+    DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_OFF, BTOFF_TIMEOUT_MS);
+           
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+}
+
+A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans)
+{
+    A_STATUS              status;
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStart \n"));
+    
+        /* set stopped in case we have a problem in starting */
+    pProt->HCIStopped = TRUE;
+    
+    do {
+        
+        status = InitTxCreditState(pProt);   
+        
+        if (A_FAILED(status)) {
+            break;    
+        }     
+        
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_ERRORS_IRQ_ENABLE, PROC_IO_SYNC);   
+        
+        if (A_FAILED(status)) {
+            break;   
+        } 
+            /* enable recv */   
+        status = DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_SYNC);
+        
+        if (A_FAILED(status)) {
+            break;   
+        } 
+            /* signal bridge side to power up BT */
+        status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_ON, BTON_TIMEOUT_MS);
+        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI_TransportStart : Failed to trigger BT ON \n"));
+            break;   
+        } 
+        
+            /* we made it */
+        pProt->HCIStopped = FALSE;
+        
+    } while (FALSE);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStart \n"));
+    
+    return status;
+}
+
+A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    return DevGMboxIRQAction(pProt->pDev, 
+                             Enable ? GMBOX_RECV_IRQ_ENABLE : GMBOX_RECV_IRQ_DISABLE, 
+                             PROC_IO_SYNC);
+                             
+}
+
+A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
+                                       HTC_PACKET           *pPacket,
+                                       int                  MaxPollMS)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    A_STATUS              status = A_OK;
+    A_UINT8               lookAhead[8];
+    int                   bytes;
+    int                   totalRecvLength;
+    
+    MaxPollMS = MaxPollMS / 16;
+    
+    if (MaxPollMS < 2) {
+        MaxPollMS = 2;    
+    }
+    
+    while (MaxPollMS) {
+        
+        bytes = sizeof(lookAhead);
+        status = DevGMboxRecvLookAheadPeek(pProt->pDev,lookAhead,&bytes);
+        if (A_FAILED(status)) {
+            break;    
+        }        
+                
+        if (bytes < 3) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI recv poll got bytes: %d, retry : %d \n",
+                        bytes, MaxPollMS));
+            A_MDELAY(16);
+            MaxPollMS--;        
+            continue;
+        }
+        
+        totalRecvLength = 0;
+        switch (lookAhead[0]) {       
+            case HCI_UART_EVENT_PKT:
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+                        lookAhead[1], lookAhead[2]));
+                totalRecvLength = lookAhead[2];
+                totalRecvLength += 3; /* add type + event code + length field */
+                break;
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",lookAhead[0]));
+                status = A_EPROTO;
+                break;
+        }
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pPacket->Completion = NULL;
+        status = DevGMboxRead(pProt->pDev,pPacket,totalRecvLength); 
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        pPacket->pBuffer++;
+        pPacket->ActualLength = totalRecvLength - 1;
+        pPacket->Status = A_OK;        
+        break; 
+    }
+    
+    if (MaxPollMS == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI recv poll timeout! \n"));
+        status = A_ERROR;    
+    }
+    
+    return status;
+}
+
+#define LSB_SCRATCH_IDX     4
+#define MSB_SCRATCH_IDX     5
+A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud)
+{
+    GMBOX_PROTO_HCI_UART  *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+    HIF_DEVICE *pHIFDevice = (HIF_DEVICE *)(pProt->pDev->HIFDevice);
+    A_UINT32 scaledBaud, scratchAddr;
+    A_STATUS status = A_OK;
+
+    /* Divide the desired baud rate by 100
+     * Store the LSB in the local scratch register 4 and the MSB in the local
+     * scratch register 5 for the target to read
+     */
+    scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * LSB_SCRATCH_IDX);
+    scaledBaud = (Baud / 100) & LOCAL_SCRATCH_VALUE_MASK;
+    status = ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);                     
+    scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * MSB_SCRATCH_IDX);
+    scaledBaud = ((Baud / 100) >> (LOCAL_SCRATCH_VALUE_MSB+1)) & LOCAL_SCRATCH_VALUE_MASK;
+    status |= ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);                     
+    if (A_OK != status) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to set up baud rate in scratch register!"));            
+        return status;
+    }
+
+    /* Now interrupt the target to tell it about the baud rate */
+    status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BAUD_SET, BAUD_TIMEOUT_MS);
+    if (A_OK != status) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to tell target to change baud rate!"));            
+    }
+    
+    return status;
+}
+
+#endif  //ATH_AR6K_ENABLE_GMBOX
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/makefile b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc.c b/drivers/net/wireless/ath6kl/htc2/htc.c
new file mode 100644
index 000000000000..0068685972a9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc.c
@@ -0,0 +1,558 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#ifdef DEBUG
+static ATH_DEBUG_MASK_DESCRIPTION g_HTCDebugDescription[] = {
+    { ATH_DEBUG_SEND , "Send"},
+    { ATH_DEBUG_RECV , "Recv"},
+    { ATH_DEBUG_SYNC , "Sync"},
+    { ATH_DEBUG_DUMP , "Dump Data (RX or TX)"},
+    { ATH_DEBUG_IRQ  , "Interrupt Processing"}
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
+                                 "htc",
+                                 "Host Target Communications",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription),
+                                 g_HTCDebugDescription);
+                                 
+#endif
+
+static void HTCReportFailure(void *Context);
+static void ResetEndpointStates(HTC_TARGET *target);
+
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
+{
+    LOCK_HTC(target);
+    HTC_PACKET_ENQUEUE(pList,pPacket);
+    UNLOCK_HTC(target);
+}
+
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target,  HTC_PACKET_QUEUE *pList)
+{
+    HTC_PACKET *pPacket;
+
+    LOCK_HTC(target);
+    pPacket = HTC_PACKET_DEQUEUE(pList);
+    UNLOCK_HTC(target);
+
+    return pPacket;
+}
+
+/* cleanup the HTC instance */
+static void HTCCleanup(HTC_TARGET *target)
+{
+    A_INT32 i;
+
+    DevCleanup(&target->Device);
+    
+    for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+        if (target->HTCControlBuffers[i].Buffer) {
+            A_FREE(target->HTCControlBuffers[i].Buffer);
+        }
+    }
+    
+    if (A_IS_MUTEX_VALID(&target->HTCLock)) {
+        A_MUTEX_DELETE(&target->HTCLock);
+    }
+
+    if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
+        A_MUTEX_DELETE(&target->HTCRxLock);
+    }
+
+    if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
+        A_MUTEX_DELETE(&target->HTCTxLock);
+    }
+        /* free our instance */
+    A_FREE(target);
+}
+
+/* registered target arrival callback from the HIF layer */
+HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
+{
+    HTC_TARGET              *target = NULL;
+    A_STATUS                 status = A_OK;
+    int                      i;
+    A_UINT32                 ctrl_bufsz;
+    A_UINT32                 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
+
+    A_REGISTER_MODULE_DEBUG_INFO(htc);
+    
+    do {
+
+            /* allocate target memory */
+        if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+            status = A_ERROR;
+            break;
+        }
+
+        A_MEMZERO(target, sizeof(HTC_TARGET));
+        A_MUTEX_INIT(&target->HTCLock);
+        A_MUTEX_INIT(&target->HTCRxLock);
+        A_MUTEX_INIT(&target->HTCTxLock);
+        INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
+        INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
+        
+            /* give device layer the hif device handle */
+        target->Device.HIFDevice = hif_handle;
+            /* give the device layer our context (for event processing)
+             * the device layer will register it's own context with HIF
+             * so we need to set this so we can fetch it in the target remove handler */
+        target->Device.HTCContext = target;
+            /* set device layer target failure callback */
+        target->Device.TargetFailureCallback = HTCReportFailure;
+            /* set device layer recv message pending callback */
+        target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
+        target->EpWaitingForBuffers = ENDPOINT_MAX;
+
+        A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO));
+        
+        ResetEndpointStates(target);
+          
+            /* setup device layer */
+        status = DevSetup(&target->Device);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+
+        /* get the block sizes */
+        status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
+            break;
+        }
+
+        /* Set the control buffer size based on the block size */
+        if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) {
+            ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
+        } else {
+            ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
+        }
+        for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+            target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
+            if (target->HTCControlBuffers[i].Buffer == NULL) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+                status = A_ERROR;
+                break;
+            }
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* carve up buffers/packets for control messages */
+        for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
+            HTC_PACKET *pControlPacket;
+            pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+            SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
+                                          target,
+                                          target->HTCControlBuffers[i].Buffer,
+                                          ctrl_bufsz,
+                                          ENDPOINT_0);
+            HTC_FREE_CONTROL_RX(target,pControlPacket);
+        }
+
+        for (;i < NUM_CONTROL_BUFFERS;i++) {
+             HTC_PACKET *pControlPacket;
+             pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+             INIT_HTC_PACKET_INFO(pControlPacket,
+                                  target->HTCControlBuffers[i].Buffer,
+                                  ctrl_bufsz);
+             HTC_FREE_CONTROL_TX(target,pControlPacket);
+        }
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (target != NULL) {
+            HTCCleanup(target);
+            target = NULL;
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
+
+    return target;
+}
+
+void  HTCDestroy(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy ..  Destroying :0x%X \n",(A_UINT32)target));
+    HTCCleanup(target);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n"));
+}
+
+/* get the low level HIF device for the caller , the caller may wish to do low level
+ * HIF requests */
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    return target->Device.HIFDevice;
+}
+
+/* wait for the target to arrive (sends HTC Ready message)
+ * this operation is fully synchronous and the message is polled for */
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET              *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_STATUS                 status;
+    HTC_PACKET              *pPacket = NULL;
+    HTC_READY_EX_MSG        *pRdyMsg;
+    HTC_SERVICE_CONNECT_REQ  connect;
+    HTC_SERVICE_CONNECT_RESP resp;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target));
+
+    do {
+
+#ifdef MBOXHW_UNIT_TEST
+
+        status = DoMboxHWTest(&target->Device);
+
+        if (status != A_OK) {
+            break;
+        }
+
+#endif
+
+            /* we should be getting 1 control message that the target is ready */
+        status = HTCWaitforControlMessage(target, &pPacket);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
+            break;
+        }
+
+            /* we controlled the buffer creation so it has to be properly aligned */
+        pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer;
+
+        if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) ||
+            (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
+                /* this message is not valid */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        
+        if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) {
+              /* this message is not valid */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount;
+        target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize;
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n",
+                target->TargetCredits, target->TargetCreditSize));
+        
+            /* check if this is an extended ready message */        
+        if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) {
+                /* this is an extended message */    
+            target->HTCTargetVersion = pRdyMsg->HTCVersion;   
+            target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle;     
+        } else {
+                /* legacy */
+            target->HTCTargetVersion = HTC_VERSION_2P0;
+            target->MaxMsgPerBundle = 0;    
+        }
+        
+#ifdef HTC_FORCE_LEGACY_2P0   
+            /* for testing and comparison...*/     
+        target->HTCTargetVersion = HTC_VERSION_2P0;
+        target->MaxMsgPerBundle = 0;
+#endif
+           
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, 
+                    ("Using HTC Protocol Version : %s (%d)\n ", 
+                    (target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1",
+                    target->HTCTargetVersion));
+                    
+        if (target->MaxMsgPerBundle > 0) {
+                /* limit what HTC can handle */
+            target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle);          
+                /* target supports message bundling, setup device layer */
+            if (A_FAILED(DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle))) {
+                    /* device layer can't handle bundling */
+                target->MaxMsgPerBundle = 0;        
+            } else {
+                    /* limit bundle what the device layer can handle */
+                target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device),
+                                              target->MaxMsgPerBundle);     
+            }
+        }
+        
+        if (target->MaxMsgPerBundle > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_TRC, 
+                    (" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle));       
+            target->SendBundlingEnabled = TRUE;
+            target->RecvBundlingEnabled = TRUE;                    
+            if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n",
+                        target->TargetCreditSize));    
+                    /* disallow send bundling since the credit size is not aligned to a block size
+                     * the I/O block padding will spill into the next credit buffer which is fatal */
+                target->SendBundlingEnabled = FALSE;
+            }
+        }
+           
+            /* setup our pseudo HTC control endpoint connection */
+        A_MEMZERO(&connect,sizeof(connect));
+        A_MEMZERO(&resp,sizeof(resp));
+        connect.EpCallbacks.pContext = target;
+        connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
+        connect.EpCallbacks.EpRecv = HTCControlRecv;
+        connect.EpCallbacks.EpRecvRefill = NULL;  /* not needed */
+        connect.EpCallbacks.EpSendFull = NULL;    /* not nedded */
+        connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
+        connect.ServiceID = HTC_CTRL_RSVD_SVC;
+
+            /* connect fake service */
+        status = HTCConnectService((HTC_HANDLE)target,
+                                   &connect,
+                                   &resp);
+
+        if (!A_FAILED(status)) {
+            break;
+        }
+
+    } while (FALSE);
+
+    if (pPacket != NULL) {
+        HTC_FREE_CONTROL_RX(target,pPacket);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
+
+    return status;
+}
+
+
+
+/* Start HTC, enable interrupts and let the target know host has finished setup */
+A_STATUS HTCStart(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_PACKET *pPacket;
+    A_STATUS   status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
+
+        /* make sure interrupts are disabled at the chip level,
+         * this function can be called again from a reboot of the target without shutting down HTC */
+    DevDisableInterrupts(&target->Device);
+        /* make sure state is cleared again */
+    target->OpStateFlags = 0;
+    target->RecvStateFlags = 0;
+      
+        /* now that we are starting, push control receive buffers into the
+         * HTC control endpoint */
+
+    while (1) {
+        pPacket = HTC_ALLOC_CONTROL_RX(target);
+        if (NULL == pPacket) {
+            break;
+        }
+        HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
+    }
+
+    do {
+
+        AR_DEBUG_ASSERT(target->InitCredits != NULL);
+        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
+        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
+
+            /* call init credits callback to do the distribution ,
+             * NOTE: the first entry in the distribution list is ENDPOINT_0, so
+             * we pass the start of the list after this one. */
+        target->InitCredits(target->pCredDistContext,
+                            target->EpCreditDistributionListHead->pNext,
+                            target->TargetCredits);
+
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+            DumpCreditDistStates(target);
+        }
+
+            /* the caller is done connecting to services, so we can indicate to the
+            * target that the setup phase is complete */
+        status = HTCSendSetupComplete(target);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* unmask interrupts */
+        status = DevUnmaskInterrupts(&target->Device);
+
+        if (A_FAILED(status)) {
+            HTCStop(target);
+        }
+
+    } while (FALSE);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
+    return status;
+}
+
+static void ResetEndpointStates(HTC_TARGET *target)
+{
+    HTC_ENDPOINT        *pEndpoint;
+    int                  i;
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        
+        A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist));
+        pEndpoint->ServiceID = 0;
+        pEndpoint->MaxMsgLength = 0;
+        pEndpoint->MaxTxQueueDepth = 0;
+#ifdef HTC_EP_STAT_PROFILING
+        A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
+#endif
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
+        INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
+        pEndpoint->target = target;
+    }
+        /* reset distribution list */
+    target->EpCreditDistributionListHead = NULL;
+}
+
+/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
+void HTCStop(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
+
+    LOCK_HTC(target);
+        /* mark that we are shutting down .. */
+    target->OpStateFlags |= HTC_OP_STATE_STOPPING;
+    UNLOCK_HTC(target);
+    
+        /* Masking interrupts is a synchronous operation, when this function returns
+         * all pending HIF I/O has completed, we can safely flush the queues */
+    DevMaskInterrupts(&target->Device);
+
+        /* flush all send packets */
+    HTCFlushSendPkts(target);
+        /* flush all recv buffers */
+    HTCFlushRecvBuffers(target);
+
+    ResetEndpointStates(target);
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
+}
+
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    LOCK_HTC_TX(target);
+
+    DumpCreditDistStates(target);
+
+    UNLOCK_HTC_TX(target);
+    
+    DumpAR6KDevState(&target->Device);
+}
+
+/* report a target failure from the device, this is a callback from the device layer
+ * which uses a mechanism to report errors from the target (i.e. special interrupts) */
+static void HTCReportFailure(void *Context)
+{
+    HTC_TARGET *target = (HTC_TARGET *)Context;
+
+    target->TargetFailure = TRUE;
+
+    if (target->HTCInitInfo.TargetFailure != NULL) {
+            /* let upper layer know, it needs to call HTCStop() */
+        target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR);
+    }
+}
+
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
+                                HTC_ENDPOINT_ID          Endpoint,
+                                HTC_ENDPOINT_STAT_ACTION Action,
+                                HTC_ENDPOINT_STATS       *pStats)
+{
+
+#ifdef HTC_EP_STAT_PROFILING
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_BOOL     clearStats = FALSE;
+    A_BOOL     sample = FALSE;
+
+    switch (Action) {
+        case HTC_EP_STAT_SAMPLE :
+            sample = TRUE;
+            break;
+        case HTC_EP_STAT_SAMPLE_AND_CLEAR :
+            sample = TRUE;
+            clearStats = TRUE;
+            break;
+        case HTC_EP_STAT_CLEAR :
+            clearStats = TRUE;
+            break;
+        default:
+            break;
+    }
+
+    A_ASSERT(Endpoint < ENDPOINT_MAX);
+
+        /* lock out TX and RX while we sample and/or clear */
+    LOCK_HTC_TX(target);
+    LOCK_HTC_RX(target);
+
+    if (sample) {
+        A_ASSERT(pStats != NULL);
+            /* return the stats to the caller */
+        A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+    }
+
+    if (clearStats) {
+            /* reset stats */
+        A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+    }
+
+    UNLOCK_HTC_RX(target);
+    UNLOCK_HTC_TX(target);
+
+    return TRUE;
+#else
+    return FALSE;
+#endif
+}
+
+AR6K_DEVICE  *HTCGetAR6KDevice(void *HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    return &target->Device;
+}
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_debug.h b/drivers/net/wireless/ath6kl/htc2/htc_debug.h
new file mode 100644
index 000000000000..0ceecf0dd36c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_debug.h
@@ -0,0 +1,34 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_debug.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_DEBUG_H_
+#define HTC_DEBUG_H_
+
+#define ATH_MODULE_NAME htc
+#include "a_debug.h"
+
+/* ------- Debug related stuff ------- */
+
+#define  ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_IRQ  ATH_DEBUG_MAKE_MODULE_MASK(4)
+
+
+#endif /*HTC_DEBUG_H_*/
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_internal.h b/drivers/net/wireless/ath6kl/htc2/htc_internal.h
new file mode 100644
index 000000000000..fbff23f598f1
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_internal.h
@@ -0,0 +1,213 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_internal.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_INTERNAL_H_
+#define _HTC_INTERNAL_H_
+
+/* for debugging, uncomment this to capture the last frame header, on frame header
+ * processing errors, the last frame header is dump for comparison */
+//#define HTC_CAPTURE_LAST_FRAME
+
+//#define HTC_EP_STAT_PROFILING
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_debug.h"
+#include "htc.h"
+#include "htc_api.h"
+#include "bmi_msg.h"
+#include "hif.h"
+#include "AR6000/ar6k.h"
+
+/* HTC operational parameters */
+#define HTC_TARGET_RESPONSE_TIMEOUT        2000 /* in ms */
+#define HTC_TARGET_DEBUG_INTR_MASK         0x01
+#define HTC_TARGET_CREDIT_INTR_MASK        0xF0
+
+#define HTC_HOST_MAX_MSG_PER_BUNDLE        8
+#define HTC_MIN_HTC_MSGS_TO_BUNDLE         2
+
+/* packet flags */
+
+#define HTC_RX_PKT_IGNORE_LOOKAHEAD      (1 << 0)
+#define HTC_RX_PKT_REFRESH_HDR           (1 << 1)
+#define HTC_RX_PKT_PART_OF_BUNDLE        (1 << 2)
+#define HTC_RX_PKT_NO_RECYCLE            (1 << 3)
+
+/* scatter request flags */
+
+#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE  (1 << 0)
+
+typedef struct _HTC_ENDPOINT {
+    HTC_ENDPOINT_ID             Id;
+    HTC_SERVICE_ID              ServiceID;      /* service ID this endpoint is bound to
+                                                   non-zero value means this endpoint is in use */
+    HTC_PACKET_QUEUE            TxQueue;        /* HTC frame buffer TX queue */
+    HTC_PACKET_QUEUE            RxBuffers;      /* HTC frame buffer RX list */
+    HTC_ENDPOINT_CREDIT_DIST    CreditDist;     /* credit distribution structure (exposed to driver layer) */
+    HTC_EP_CALLBACKS            EpCallBacks;    /* callbacks associated with this endpoint */
+    int                         MaxTxQueueDepth;   /* max depth of the TX queue before we need to
+                                                      call driver's full handler */
+    int                         MaxMsgLength;        /* max length of endpoint message */
+    int                         TxProcessCount;  /* reference count to continue tx processing */
+    HTC_PACKET_QUEUE            RecvIndicationQueue;    /* recv packets ready to be indicated */
+    int                         RxProcessCount;         /* reference count to allow single processing context */
+    struct  _HTC_TARGET         *target;                /* back pointer to target */
+    A_UINT8                     SeqNo;                  /* TX seq no (helpful) for debugging */
+    A_UINT32                    LocalConnectionFlags;   /* local connection flags */
+#ifdef HTC_EP_STAT_PROFILING
+    HTC_ENDPOINT_STATS          EndPointStats;          /* endpoint statistics */
+#endif
+} HTC_ENDPOINT;
+
+#ifdef HTC_EP_STAT_PROFILING
+#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
+#else
+#define INC_HTC_EP_STAT(p,stat,count)
+#endif
+
+#define HTC_SERVICE_TX_PACKET_TAG  HTC_TX_PACKET_TAG_INTERNAL
+
+#define NUM_CONTROL_BUFFERS     8
+#define NUM_CONTROL_TX_BUFFERS  2
+#define NUM_CONTROL_RX_BUFFERS  (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
+
+typedef struct HTC_CONTROL_BUFFER {
+    HTC_PACKET    HtcPacket;
+    A_UINT8       *Buffer;
+} HTC_CONTROL_BUFFER;
+
+#define HTC_RECV_WAIT_BUFFERS        (1 << 0)
+#define HTC_OP_STATE_STOPPING        (1 << 0)
+
+/* our HTC target state */
+typedef struct _HTC_TARGET {
+    HTC_ENDPOINT                EndPoint[ENDPOINT_MAX];
+    HTC_CONTROL_BUFFER          HTCControlBuffers[NUM_CONTROL_BUFFERS];
+    HTC_ENDPOINT_CREDIT_DIST   *EpCreditDistributionListHead;
+    HTC_PACKET_QUEUE            ControlBufferTXFreeList;
+    HTC_PACKET_QUEUE            ControlBufferRXFreeList;
+    HTC_CREDIT_DIST_CALLBACK    DistributeCredits;
+    HTC_CREDIT_INIT_CALLBACK    InitCredits;
+    void                       *pCredDistContext;
+    int                         TargetCredits;
+    unsigned int                TargetCreditSize;
+    A_MUTEX_T                   HTCLock;
+    A_MUTEX_T                   HTCRxLock;
+    A_MUTEX_T                   HTCTxLock;
+    AR6K_DEVICE                 Device;         /* AR6K - specific state */
+    A_UINT32                    OpStateFlags;
+    A_UINT32                    RecvStateFlags;
+    HTC_ENDPOINT_ID             EpWaitingForBuffers;
+    A_BOOL                      TargetFailure;
+#ifdef HTC_CAPTURE_LAST_FRAME
+    HTC_FRAME_HDR               LastFrameHdr;  /* useful for debugging */
+    A_UINT8                     LastTrailer[256];
+    A_UINT8                     LastTrailerLength;
+#endif
+    HTC_INIT_INFO               HTCInitInfo;
+    A_UINT8                     HTCTargetVersion;
+    int                         MaxMsgPerBundle;       /* max messages per bundle for HTC */
+    A_BOOL                      SendBundlingEnabled;   /* run time enable for send bundling (dynamic) */
+    int                         RecvBundlingEnabled;   /* run time enable for recv bundling (dynamic) */
+} HTC_TARGET;
+
+#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING)
+#define LOCK_HTC(t)      A_MUTEX_LOCK(&(t)->HTCLock);
+#define UNLOCK_HTC(t)    A_MUTEX_UNLOCK(&(t)->HTCLock);
+#define LOCK_HTC_RX(t)   A_MUTEX_LOCK(&(t)->HTCRxLock);
+#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
+#define LOCK_HTC_TX(t)   A_MUTEX_LOCK(&(t)->HTCTxLock);
+#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
+
+#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
+#define HTC_RECYCLE_RX_PKT(target,p,e)                           \
+{                                                                \
+    if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) {  \
+         HTC_PACKET_RESET_RX(pPacket);                           \
+         pPacket->Status = A_ECANCELED;                          \
+         (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext,      \
+                                 (p));                           \
+    } else {                                                     \
+        HTC_PACKET_RESET_RX(pPacket);                            \
+        HTCAddReceivePkt((HTC_HANDLE)(target),(p));              \
+    }                                                            \
+}
+
+/* internal HTC functions */
+void        HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
+void        HTCControlRecv(void *Context, HTC_PACKET *pPacket);
+A_STATUS    HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
+void        HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
+A_STATUS    HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket);
+void        HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
+A_STATUS    HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched);
+void        HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
+A_STATUS    HTCSendSetupComplete(HTC_TARGET *target);
+void        HTCFlushRecvBuffers(HTC_TARGET *target);
+void        HTCFlushSendPkts(HTC_TARGET *target);
+void        DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
+void        DumpCreditDistStates(HTC_TARGET *target);
+void 		DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
+    HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
+    if (pPacket != NULL) {
+            /* set payload pointer area with some headroom */
+        pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
+    }
+    return pPacket;
+}
+
+#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
+#define HTC_ALLOC_CONTROL_RX(t)  HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
+#define HTC_FREE_CONTROL_RX(t,p) \
+{                                                                \
+    HTC_PACKET_RESET_RX(p);                                      \
+    HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
+}
+
+#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1)       \
+{                                                   \
+    A_UINT8 *pHdrBuf;                               \
+    (pP)->pBuffer -= HTC_HDR_LENGTH;                \
+    pHdrBuf = (pP)->pBuffer;                        \
+    A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)(pP)->ActualLength);  \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,(sendflags));                         \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)(pP)->Endpoint); \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[0], (A_UINT8)(ctrl0));   \
+    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[1], (A_UINT8)(ctrl1));   \
+}
+
+#define HTC_UNPREPARE_SEND_PKT(pP)     \
+    (pP)->pBuffer += HTC_HDR_LENGTH;   \
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_INTERNAL_H_ */
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_recv.c b/drivers/net/wireless/ath6kl/htc2/htc_recv.c
new file mode 100644
index 000000000000..2b4c130b9467
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_recv.c
@@ -0,0 +1,1545 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_recv.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#define HTCIssueRecv(t, p) \
+    DevRecvPacket(&(t)->Device,  \
+                  (p),          \
+                  (p)->ActualLength)
+
+#define DO_RCV_COMPLETION(e,q)  DoRecvCompletion(e,q)
+
+#define DUMP_RECV_PKT_INFO(pP) \
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC RECV packet 0x%X (%d bytes) (hdr:0x%X) on ep : %d \n", \
+                        (A_UINT32)(pP),                        \
+                        (pP)->ActualLength,                    \
+                        (pP)->PktInfo.AsRx.ExpectedHdr,        \
+                        (pP)->Endpoint))                         
+                        
+#ifdef HTC_EP_STAT_PROFILING
+#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads)        \
+{                                                      \
+    INC_HTC_EP_STAT((ep), RxReceived, 1);              \
+    if ((numLookAheads) == 1) {                        \
+        INC_HTC_EP_STAT((ep), RxLookAheads, 1);        \
+    } else if ((numLookAheads) > 1) {                  \
+        INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1);  \
+    }                                                  \
+}
+#else
+#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
+#endif
+
+static void DoRecvCompletion(HTC_ENDPOINT     *pEndpoint,
+                             HTC_PACKET_QUEUE *pQueueToIndicate)
+{           
+    
+    do {
+        
+        if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+                /* nothing to indicate */
+            break;    
+        }
+ 
+        if (pEndpoint->EpCallBacks.EpRecvPktMultiple != NULL) {    
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d, recv multiple callback (%d pkts) \n",
+                     pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+                /* a recv multiple handler is being used, pass the queue to the handler */                             
+            pEndpoint->EpCallBacks.EpRecvPktMultiple(pEndpoint->EpCallBacks.pContext,
+                                                     pQueueToIndicate);
+            INIT_HTC_PACKET_QUEUE(pQueueToIndicate);        
+        } else {
+            HTC_PACKET *pPacket;  
+            /* using legacy EpRecv */         
+            do {
+                pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d recv callback on packet 0x%X \n", \
+                        pEndpoint->Id, (A_UINT32)(pPacket)));
+                pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket);                                              
+            } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));                                              
+        }
+        
+    } while (FALSE);
+
+}
+
+static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
+                                         A_UINT8    *pBuffer,
+                                         int         Length,
+                                         A_UINT32   *pNextLookAheads,
+                                         int        *pNumLookAheads,
+                                         HTC_ENDPOINT_ID FromEndpoint)
+{
+    HTC_RECORD_HDR          *pRecord;
+    A_UINT8                 *pRecordBuf;
+    HTC_LOOKAHEAD_REPORT    *pLookAhead;
+    A_UINT8                 *pOrigBuffer;
+    int                     origLength;
+    A_STATUS                status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
+    }
+
+    pOrigBuffer = pBuffer;
+    origLength = Length;
+    status = A_OK;
+    
+    while (Length > 0) {
+
+        if (Length < sizeof(HTC_RECORD_HDR)) {
+            status = A_EPROTO;
+            break;
+        }
+            /* these are byte aligned structs */
+        pRecord = (HTC_RECORD_HDR *)pBuffer;
+        Length -= sizeof(HTC_RECORD_HDR);
+        pBuffer += sizeof(HTC_RECORD_HDR);
+
+        if (pRecord->Length > Length) {
+                /* no room left in buffer for record */
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
+                        pRecord->Length, pRecord->RecordID, Length));
+            status = A_EPROTO;
+            break;
+        }
+            /* start of record follows the header */
+        pRecordBuf = pBuffer;
+
+        switch (pRecord->RecordID) {
+            case HTC_RECORD_CREDITS:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
+                HTCProcessCreditRpt(target,
+                                    (HTC_CREDIT_REPORT *)pRecordBuf,
+                                    pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
+                                    FromEndpoint);
+                break;
+            case HTC_RECORD_LOOKAHEAD:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
+                pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
+                if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
+                    (pNextLookAheads != NULL)) {
+
+                    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                                (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
+                                pLookAhead->PreValid,
+                                pLookAhead->PostValid));
+
+                        /* look ahead bytes are valid, copy them over */
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[0] = pLookAhead->LookAhead[0];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[1] = pLookAhead->LookAhead[1];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[2] = pLookAhead->LookAhead[2];
+                    ((A_UINT8 *)(&pNextLookAheads[0]))[3] = pLookAhead->LookAhead[3];
+
+                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+                        DebugDumpBytes((A_UINT8 *)pNextLookAheads,4,"Next Look Ahead");
+                    }
+                        /* just one normal lookahead */
+                    *pNumLookAheads = 1;
+                }
+                break;
+            case HTC_RECORD_LOOKAHEAD_BUNDLE:
+                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT));
+                if (pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT) &&
+                    (pNextLookAheads != NULL)) {                   
+                    HTC_BUNDLED_LOOKAHEAD_REPORT    *pBundledLookAheadRpt;
+                    int                             i;
+                    
+                    pBundledLookAheadRpt = (HTC_BUNDLED_LOOKAHEAD_REPORT *)pRecordBuf;
+                    
+                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+                        DebugDumpBytes(pRecordBuf,pRecord->Length,"Bundle LookAhead");
+                    }
+                    
+                    if ((pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))) >
+                            HTC_HOST_MAX_MSG_PER_BUNDLE) {
+                            /* this should never happen, the target restricts the number
+                             * of messages per bundle configured by the host */        
+                        A_ASSERT(FALSE);
+                        status = A_EPROTO;
+                        break;        
+                    }
+                                         
+                    for (i = 0; i < (int)(pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))); i++) {
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[0] = pBundledLookAheadRpt->LookAhead[0];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[1] = pBundledLookAheadRpt->LookAhead[1];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[2] = pBundledLookAheadRpt->LookAhead[2];
+                        ((A_UINT8 *)(&pNextLookAheads[i]))[3] = pBundledLookAheadRpt->LookAhead[3];
+                        pBundledLookAheadRpt++;
+                    }
+                    
+                    *pNumLookAheads = i;
+                }               
+                break;
+            default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
+                        pRecord->RecordID, pRecord->Length));
+                break;
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* advance buffer past this record for next time around */
+        pBuffer += pRecord->Length;
+        Length -= pRecord->Length;
+    }
+
+    if (A_FAILED(status)) {
+        DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
+    return status;
+
+}
+
+/* process a received message (i.e. strip off header, process any trailer data)
+ * note : locks must be released when this function is called */
+static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, 
+                                     HTC_PACKET *pPacket, 
+                                     A_UINT32   *pNextLookAheads, 
+                                     int        *pNumLookAheads)
+{
+    A_UINT8   temp;
+    A_UINT8   *pBuf;
+    A_STATUS  status = A_OK;
+    A_UINT16  payloadLen;
+    A_UINT32  lookAhead;
+
+    pBuf = pPacket->pBuffer;
+    
+    if (pNumLookAheads != NULL) {
+        *pNumLookAheads = 0;
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+        AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
+    }
+
+    do {
+        /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
+         * retrieve 16 bit fields */
+        payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
+        
+        ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
+        ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
+        ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
+        ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
+
+        if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_REFRESH_HDR) {
+                /* refresh expected hdr, since this was unknown at the time we grabbed the packets
+                 * as part of a bundle */
+            pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+                /* refresh actual length since we now have the real header */
+            pPacket->ActualLength = payloadLen + HTC_HDR_LENGTH;
+            
+                /* validate the actual header that was refreshed  */ 
+            if (pPacket->ActualLength > pPacket->BufferLength) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("Refreshed HDR payload length (%d) in bundled RECV is invalid (hdr: 0x%X) \n", 
+                    payloadLen, lookAhead));
+                    /* limit this to max buffer just to print out some of the buffer */    
+                pPacket->ActualLength = min(pPacket->ActualLength, pPacket->BufferLength);
+                status = A_EPROTO;
+                break;    
+            }
+            
+            if (pPacket->Endpoint != A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("Refreshed HDR endpoint (%d) does not match expected endpoint (%d) \n", 
+                    A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID), pPacket->Endpoint));
+                status = A_EPROTO;
+                break;      
+            }   
+        }
+                
+        if (lookAhead != pPacket->PktInfo.AsRx.ExpectedHdr) {
+            /* somehow the lookahead that gave us the full read length did not
+             * reflect the actual header in the pending message */
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCProcessRecvHeader, lookahead mismatch! (pPkt:0x%X flags:0x%X) \n", 
+                        (A_UINT32)pPacket, pPacket->PktInfo.AsRx.HTCRxFlags));
+             DebugDumpBytes((A_UINT8 *)&pPacket->PktInfo.AsRx.ExpectedHdr,4,"Expected Message LookAhead");
+             DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
+#ifdef HTC_CAPTURE_LAST_FRAME
+            DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
+            if (target->LastTrailerLength != 0) {
+                DebugDumpBytes(target->LastTrailer,
+                               target->LastTrailerLength,
+                               "Last trailer");
+            }
+#endif
+            status = A_EPROTO;
+            break;
+        }
+
+            /* get flags */
+        temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
+
+        if (temp & HTC_FLAGS_RECV_TRAILER) {
+            /* this packet has a trailer */
+
+                /* extract the trailer length in control byte 0 */
+            temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
+
+            if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
+                        payloadLen, temp));
+                status = A_EPROTO;
+                break;
+            }
+
+            if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+                    /* this packet was fetched as part of an HTC bundle, the embedded lookahead is
+                     * not valid since the next packet may have already been fetched as part of the
+                     * bundle */
+                pNextLookAheads = NULL;   
+                pNumLookAheads = NULL;     
+            }
+            
+                /* process trailer data that follows HDR + application payload */
+            status = HTCProcessTrailer(target,
+                                       (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
+                                       temp,
+                                       pNextLookAheads,
+                                       pNumLookAheads,
+                                       pPacket->Endpoint);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+#ifdef HTC_CAPTURE_LAST_FRAME
+            A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
+            target->LastTrailerLength = temp;
+#endif
+                /* trim length by trailer bytes */
+            pPacket->ActualLength -= temp;
+        }
+#ifdef HTC_CAPTURE_LAST_FRAME
+         else {
+            target->LastTrailerLength = 0;
+        }
+#endif
+
+            /* if we get to this point, the packet is good */
+            /* remove header and adjust length */
+        pPacket->pBuffer += HTC_HDR_LENGTH;
+        pPacket->ActualLength -= HTC_HDR_LENGTH;
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+            /* dump the whole packet */
+        DebugDumpBytes(pBuf,pPacket->ActualLength < 256 ? pPacket->ActualLength : 256 ,"BAD HTC Recv PKT");
+    } else {
+#ifdef HTC_CAPTURE_LAST_FRAME
+        A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
+#endif
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+            if (pPacket->ActualLength > 0) {
+                AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
+            }
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
+    return status;
+}
+
+static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET  *target, 
+                                                A_UINT32    NextLookAheads[], 
+                                                int         NumLookAheads,
+                                                A_BOOL      CheckMoreMsgs)
+{
+        /* was there a lookahead for the next packet? */
+    if (NumLookAheads > 0) {
+        A_STATUS nextStatus;
+        int      fetched = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                        ("HTCAsyncRecvCheckMorePackets - num lookaheads were non-zero : %d \n",
+                         NumLookAheads));
+            /* force status re-check */                    
+        REF_IRQ_STATUS_RECHECK(&target->Device);
+            /* we have more packets, get the next packet fetch started */
+        nextStatus = HTCRecvMessagePendingHandler(target, NextLookAheads, NumLookAheads, NULL, &fetched);
+        if (A_EPROTO == nextStatus) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Next look ahead from recv header was INVALID\n"));
+            DebugDumpBytes((A_UINT8 *)NextLookAheads,
+                            NumLookAheads * (sizeof(A_UINT32)),
+                            "BAD lookaheads from lookahead report");
+        }
+        if (A_SUCCESS(nextStatus) && !fetched) {
+                /* we could not fetch any more packets due to resources */
+            DevAsyncIrqProcessComplete(&target->Device);        
+        }
+    } else {
+        if (CheckMoreMsgs) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTCAsyncRecvCheckMorePackets - rechecking for more messages...\n"));
+            /* if we did not get anything on the look-ahead,
+             * call device layer to asynchronously re-check for messages. If we can keep the async
+             * processing going we get better performance.  If there is a pending message we will keep processing
+             * messages asynchronously which should pipeline things nicely */
+            DevCheckPendingRecvMsgsAsync(&target->Device);
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("HTCAsyncRecvCheckMorePackets - no check \n"));    
+        }
+    }
+    
+     
+}      
+
+    /* unload the recv completion queue */
+static INLINE void DrainRecvIndicationQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+    HTC_PACKET_QUEUE     recvCompletions;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+DrainRecvIndicationQueue \n"));
+                
+    INIT_HTC_PACKET_QUEUE(&recvCompletions);
+    
+    LOCK_HTC_RX(target);
+    
+            /* increment rx processing count on entry */    
+    pEndpoint->RxProcessCount++;
+    if (pEndpoint->RxProcessCount > 1) {
+         pEndpoint->RxProcessCount--;
+            /* another thread or task is draining the RX completion queue on this endpoint
+             * that thread will reset the rx processing count when the queue is drained */
+         UNLOCK_HTC_RX(target);
+         return;
+    }
+    
+    /******* at this point only 1 thread may enter ******/
+     
+    while (TRUE) { 
+                
+            /* transfer items from main recv queue to the local one so we can release the lock */ 
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&recvCompletions, &pEndpoint->RecvIndicationQueue);
+            
+        if (HTC_QUEUE_EMPTY(&recvCompletions)) {
+                /* all drained */
+            break;    
+        }
+        
+            /* release lock while we do the recv completions 
+             * other threads can now queue more recv completions */
+        UNLOCK_HTC_RX(target);
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, 
+                ("DrainRecvIndicationQueue : completing %d RECV packets \n",
+                                        HTC_PACKET_QUEUE_DEPTH(&recvCompletions)));
+            /* do completion */
+        DO_RCV_COMPLETION(pEndpoint,&recvCompletions);     
+              
+            /* re-acquire lock to grab some more completions */
+        LOCK_HTC_RX(target);    
+    }
+    
+        /* reset count */
+    pEndpoint->RxProcessCount = 0;       
+    UNLOCK_HTC_RX(target);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-DrainRecvIndicationQueue \n"));
+  
+}
+
+    /* optimization for recv packets, we can indicate a "hint" that there are more
+     * single-packets to fetch on this endpoint */
+#define SET_MORE_RX_PACKET_INDICATION_FLAG(L,N,E,P) \
+    if ((N) > 0) { SetRxPacketIndicationFlags((L)[0],(E),(P)); }
+
+    /* for bundled frames, we can force the flag to indicate there are more packets */
+#define FORCE_MORE_RX_PACKET_INDICATION_FLAG(P) \
+    (P)->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; 
+   
+   /* note: this function can be called with the RX lock held */     
+static INLINE void SetRxPacketIndicationFlags(A_UINT32      LookAhead, 
+                                              HTC_ENDPOINT  *pEndpoint, 
+                                              HTC_PACKET    *pPacket)
+{
+    HTC_FRAME_HDR *pHdr = (HTC_FRAME_HDR *)&LookAhead;
+        /* check to see if the "next" packet is from the same endpoint of the
+           completing packet */
+    if (pHdr->EndpointID == pPacket->Endpoint) {
+            /* check that there is a buffer available to actually fetch it */
+        if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) {                        
+                /* provide a hint that there are more RX packets to fetch */
+            FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);        
+        }             
+    }                  
+}
+
+     
+/* asynchronous completion handler for recv packet fetching, when the device layer
+ * completes a read request, it will call this completion handler */
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    HTC_ENDPOINT    *pEndpoint;
+    A_UINT32        nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int             numLookAheads = 0;
+    A_STATUS        status;
+    A_BOOL          checkMorePkts = TRUE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (pkt:0x%X, status:%d, ep:%d) \n",
+                (A_UINT32)pPacket, pPacket->Status, pPacket->Endpoint));
+
+    A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    pPacket->Completion = NULL;
+
+        /* get completion status */
+    status = pPacket->Status;
+
+    do {
+        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
+                pPacket->Status, pPacket->Endpoint));
+            break;
+        }
+            /* process the header for any trailer data */
+        status = HTCProcessRecvHeader(target,pPacket,nextLookAheads,&numLookAheads);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+        
+        if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+                /* this packet was part of a bundle that had to be broken up. 
+                 * It was fetched one message at a time.  There may be other asynchronous reads queued behind this one.
+                 * Do no issue another check for more packets since the last one in the series of requests
+                 * will handle it */
+            checkMorePkts = FALSE;    
+        }
+          
+        DUMP_RECV_PKT_INFO(pPacket);    
+        LOCK_HTC_RX(target);
+        SET_MORE_RX_PACKET_INDICATION_FLAG(nextLookAheads,numLookAheads,pEndpoint,pPacket);
+            /* we have a good packet, queue it to the completion queue */
+        HTC_PACKET_ENQUEUE(&pEndpoint->RecvIndicationQueue,pPacket);
+        HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+        UNLOCK_HTC_RX(target);     
+       
+            /* check for more recv packets before indicating */
+        HTCAsyncRecvCheckMorePackets(target,nextLookAheads,numLookAheads,checkMorePkts);
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                         ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
+                         status));
+            /* recycle this packet */
+        HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+    } else {
+            /* a good packet was queued, drain the queue */
+        DrainRecvIndicationQueue(target,pEndpoint);     
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
+}
+
+/* synchronously wait for a control message from the target,
+ * This function is used at initialization time ONLY.  At init messages
+ * on ENDPOINT 0 are expected. */
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
+{
+    A_STATUS        status;
+    A_UINT32        lookAhead;
+    HTC_PACKET      *pPacket = NULL;
+    HTC_FRAME_HDR   *pHdr;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
+
+    do  {
+
+        *ppControlPacket = NULL;
+
+            /* call the polling function to see if we have a message */
+        status = DevPollMboxMsgRecv(&target->Device,
+                                    &lookAhead,
+                                    HTC_TARGET_RESPONSE_TIMEOUT);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
+
+            /* check the lookahead */
+        pHdr = (HTC_FRAME_HDR *)&lookAhead;
+
+        if (pHdr->EndpointID != ENDPOINT_0) {
+                /* unexpected endpoint number, should be zero */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        if (A_FAILED(status)) {
+                /* bad message */
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+        pPacket = HTC_ALLOC_CONTROL_RX(target);
+
+        if (pPacket == NULL) {
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_NO_MEMORY;
+            break;
+        }
+        
+        pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+        pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+
+        if (pPacket->ActualLength > pPacket->BufferLength) {
+            AR_DEBUG_ASSERT(FALSE);
+            status = A_EPROTO;
+            break;
+        }
+
+            /* we want synchronous operation */
+        pPacket->Completion = NULL;
+
+            /* get the message from the device, this will block */
+        status = HTCIssueRecv(target, pPacket);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* process receive header */
+        status = HTCProcessRecvHeader(target,pPacket,NULL,NULL);
+
+        pPacket->Status = status;
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
+                     status));
+            break;
+        }
+
+            /* give the caller this control message packet, they are responsible to free */
+        *ppControlPacket = pPacket;
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        if (pPacket != NULL) {
+                /* cleanup buffer on error */
+            HTC_FREE_CONTROL_RX(target,pPacket);
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
+
+    return status;
+}
+
+static A_STATUS AllocAndPrepareRxPackets(HTC_TARGET       *target, 
+                                         A_UINT32         LookAheads[], 
+                                         int              Messages,                                        
+                                         HTC_ENDPOINT     *pEndpoint, 
+                                         HTC_PACKET_QUEUE *pQueue)
+{
+    A_STATUS         status = A_OK;
+    HTC_PACKET      *pPacket;
+    HTC_FRAME_HDR   *pHdr;
+    int              i,j;
+    int              numMessages;
+    int              fullLength;
+    A_BOOL           noRecycle;
+            
+        /* lock RX while we assemble the packet buffers */
+    LOCK_HTC_RX(target);
+                        
+    for (i = 0; i < Messages; i++) {   
+         
+        pHdr = (HTC_FRAME_HDR *)&LookAheads[i];
+
+        if (pHdr->EndpointID >= ENDPOINT_MAX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
+                /* invalid endpoint */
+            status = A_EPROTO;
+            break;
+        }
+
+        if (pHdr->EndpointID != pEndpoint->Id) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d should be : %d (index:%d)\n",
+                pHdr->EndpointID, pEndpoint->Id, i));
+                /* invalid endpoint */
+            status = A_EPROTO;
+            break;    
+        }    
+       
+        if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
+                    pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH));
+            status = A_EPROTO;
+            break;
+        }
+
+        if (0 == pEndpoint->ServiceID) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
+                /* endpoint isn't even connected */
+            status = A_EPROTO;
+            break;
+        }
+
+        if ((pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) == 0) {
+                /* HTC header only indicates 1 message to fetch */
+            numMessages = 1;
+        } else {
+                /* HTC header indicates that every packet to follow has the same padded length so that it can
+                 * be optimally fetched as a full bundle */
+            numMessages = (pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT;
+                /* the count doesn't include the starter frame, just a count of frames to follow */
+            numMessages++;
+            A_ASSERT(numMessages <= target->MaxMsgPerBundle);          
+            INC_HTC_EP_STAT(pEndpoint, RxBundleIndFromHdr, 1);
+            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                ("HTC header indicates :%d messages can be fetched as a bundle \n",numMessages));           
+        }
+     
+        fullLength = DEV_CALC_RECV_PADDED_LEN(&target->Device,pHdr->PayloadLen + sizeof(HTC_FRAME_HDR));
+            
+            /* get packet buffers for each message, if there was a bundle detected in the header,
+             * use pHdr as a template to fetch all packets in the bundle */        
+        for (j = 0; j < numMessages; j++) {  
+            
+                /* reset flag, any packets allocated using the RecvAlloc() API cannot be recycled on cleanup,
+                 * they must be explicitly returned */
+            noRecycle = FALSE;
+                                                                                   
+            if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) {
+                UNLOCK_HTC_RX(target);
+                noRecycle = TRUE;
+                    /* user is using a per-packet allocation callback */
+                pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext,
+                                                             pEndpoint->Id,
+                                                             fullLength);
+                LOCK_HTC_RX(target);
+    
+            } else if ((pEndpoint->EpCallBacks.EpRecvAllocThresh != NULL) &&
+                       (fullLength > pEndpoint->EpCallBacks.RecvAllocThreshold)) { 
+                INC_HTC_EP_STAT(pEndpoint,RxAllocThreshHit,1);
+                INC_HTC_EP_STAT(pEndpoint,RxAllocThreshBytes,pHdr->PayloadLen);                
+                    /* threshold was hit, call the special recv allocation callback */        
+                UNLOCK_HTC_RX(target);
+                noRecycle = TRUE;
+                    /* user wants to allocate packets above a certain threshold */
+                pPacket = pEndpoint->EpCallBacks.EpRecvAllocThresh(pEndpoint->EpCallBacks.pContext,
+                                                                   pEndpoint->Id,
+                                                                   fullLength);
+                LOCK_HTC_RX(target);        
+                        
+            } else {
+                    /* user is using a refill handler that can refill multiple HTC buffers */
+                    
+                    /* get a packet from the endpoint recv queue */
+                pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+    
+                if (NULL == pPacket) {
+                        /* check for refill handler */
+                    if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
+                        UNLOCK_HTC_RX(target);
+                            /* call the re-fill handler */
+                        pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+                                                            pEndpoint->Id);
+                        LOCK_HTC_RX(target);
+                            /* check if we have more buffers */
+                        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+                            /* fall through */
+                    }
+                }
+            }
+    
+            if (NULL == pPacket) {
+                    /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+                target->RecvStateFlags |= HTC_RECV_WAIT_BUFFERS;
+                target->EpWaitingForBuffers = pEndpoint->Id;
+                status = A_NO_RESOURCE;
+                break;
+            }
+                             
+            AR_DEBUG_ASSERT(pPacket->Endpoint == pEndpoint->Id);
+                /* clear flags */
+            pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+            pPacket->PktInfo.AsRx.IndicationFlags = 0;
+            pPacket->Status = A_OK;
+            
+            if (noRecycle) {
+                    /* flag that these packets cannot be recycled, they have to be returned to the 
+                     * user */
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_NO_RECYCLE; 
+            }
+                /* add packet to queue (also incase we need to cleanup down below)  */
+            HTC_PACKET_ENQUEUE(pQueue,pPacket);
+            
+            if (HTC_STOPPING(target)) {
+                status = A_ECANCELED;
+                break;
+            }
+    
+                /* make sure this message can fit in the endpoint buffer */
+            if ((A_UINT32)fullLength > pPacket->BufferLength) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Payload Length Error : header reports payload of: %d (%d) endpoint buffer size: %d \n",
+                        pHdr->PayloadLen, fullLength, pPacket->BufferLength));
+                status = A_EPROTO;
+                break;
+            }
+            
+            if (j > 0) {
+                    /* for messages fetched in a bundle the expected lookahead is unknown since we
+                     * are only using the lookahead of the first packet as a template of what to
+                     * expect for lengths */
+                    /* flag that once we get the real HTC header we need to refesh the information */     
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_REFRESH_HDR;
+                    /* set it to something invalid */
+                pPacket->PktInfo.AsRx.ExpectedHdr = 0xFFFFFFFF;    
+            } else {
+            
+                pPacket->PktInfo.AsRx.ExpectedHdr = LookAheads[i]; /* set expected look ahead */
+            }
+                /* set the amount of data to fetch */
+            pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+        }
+        
+        if (A_FAILED(status)) {
+            if (A_NO_RESOURCE == status) {
+                    /* this is actually okay */
+                status = A_OK;    
+            }
+            break;    
+        }
+                
+    }
+    
+    UNLOCK_HTC_RX(target);
+    
+    if (A_FAILED(status)) {
+        while (!HTC_QUEUE_EMPTY(pQueue)) {
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);
+                /* recycle all allocated packets */
+            HTC_RECYCLE_RX_PKT(target,pPacket,&target->EndPoint[pPacket->Endpoint]);
+        }        
+    }
+        
+    return status; 
+}
+
+static void HTCAsyncRecvScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+    int                 i;    
+    HTC_PACKET          *pPacket;
+    HTC_ENDPOINT        *pEndpoint;
+    A_UINT32            lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int                 numLookAheads = 0;
+    HTC_TARGET          *target = (HTC_TARGET *)pScatterReq->Context;
+    A_STATUS            status;
+    A_BOOL              partialBundle = FALSE;
+    HTC_PACKET_QUEUE    localRecvQueue;
+    A_BOOL              procError = FALSE;
+           
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCAsyncRecvScatterCompletion  TotLen: %d  Entries: %d\n",
+        pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+    
+    A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+           
+    if (A_FAILED(pScatterReq->CompletionStatus)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Recv Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));            
+    }
+    
+    if (pScatterReq->CallerFlags & HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE) {
+        partialBundle = TRUE;    
+    }
+    
+    DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+    
+    INIT_HTC_PACKET_QUEUE(&localRecvQueue);
+        
+    pPacket = (HTC_PACKET *)pScatterReq->ScatterList[0].pCallerContexts[0];
+        /* note: all packets in a scatter req are for the same endpoint ! */
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+         
+        /* walk through the scatter list and process */
+        /* **** NOTE: DO NOT HOLD ANY LOCKS here, HTCProcessRecvHeader can take the TX lock
+         * as it processes credit reports */
+    for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+        pPacket = (HTC_PACKET *)pScatterReq->ScatterList[i].pCallerContexts[0];
+        A_ASSERT(pPacket != NULL);       
+            /* reset count, we are only interested in the look ahead in the last packet when we
+             * break out of this loop */
+        numLookAheads = 0;
+        
+        if (A_SUCCESS(pScatterReq->CompletionStatus)) {      
+                /* process header for each of the recv packets */            
+            status = HTCProcessRecvHeader(target,pPacket,lookAheads,&numLookAheads);
+        } else {
+            status = A_ERROR;    
+        }
+        
+        if (A_SUCCESS(status)) {    
+#ifdef HTC_EP_STAT_PROFILING
+            LOCK_HTC_RX(target);              
+            HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+            INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+            UNLOCK_HTC_RX(target);
+#endif      
+            if (i == (pScatterReq->ValidScatterEntries - 1)) {
+                    /* last packet's more packets flag is set based on the lookahead */
+                SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket);
+            } else {
+                    /* packets in a bundle automatically have this flag set */
+                FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+            }
+             
+            DUMP_RECV_PKT_INFO(pPacket);            
+                /* since we can't hold a lock in this loop, we insert into our local recv queue for
+                 * storage until we can transfer them to the recv completion queue */
+            HTC_PACKET_ENQUEUE(&localRecvQueue,pPacket);
+            
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Recv packet scatter entry %d failed (out of %d) \n",
+                    i, pScatterReq->ValidScatterEntries));
+                /* recycle failed recv */
+            HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+                /* set flag and continue processing the remaining scatter entries */
+            procError = TRUE;
+        }   
+    
+    }
+  
+        /* free scatter request */
+    DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+   
+    LOCK_HTC_RX(target);   
+        /* transfer the packets in the local recv queue to the recv completion queue */
+    HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RecvIndicationQueue, &localRecvQueue);  
+    
+    UNLOCK_HTC_RX(target);
+    
+    if (!procError) {  
+            /* pipeline the next check (asynchronously) for more packets */           
+        HTCAsyncRecvCheckMorePackets(target,
+                                     lookAheads,
+                                     numLookAheads,
+                                     partialBundle ? FALSE : TRUE);
+    }
+    
+        /* now drain the indication queue */
+    DrainRecvIndicationQueue(target,pEndpoint);
+          
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCAsyncRecvScatterCompletion \n"));
+}
+
+static A_STATUS HTCIssueRecvPacketBundle(HTC_TARGET        *target,
+                                         HTC_PACKET_QUEUE  *pRecvPktQueue, 
+                                         HTC_PACKET_QUEUE  *pSyncCompletionQueue,
+                                         int               *pNumPacketsFetched,
+                                         A_BOOL             PartialBundle)
+{
+    A_STATUS        status = A_OK;
+    HIF_SCATTER_REQ *pScatterReq;
+    int             i, totalLength;
+    int             pktsToScatter;
+    HTC_PACKET      *pPacket;
+    A_BOOL          asyncMode = (pSyncCompletionQueue == NULL) ? TRUE : FALSE;
+    int             scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device);
+        
+    pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue);
+    pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+        
+    if ((HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue) - pktsToScatter) > 0) {
+            /* we were forced to split this bundle receive operation
+             * all packets in this partial bundle must have their lookaheads ignored */
+        PartialBundle = TRUE;
+            /* this would only happen if the target ignored our max bundle limit */
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                         ("HTCIssueRecvPacketBundle : partial bundle detected num:%d , %d \n",
+                         HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));       
+    }
+    
+    totalLength = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCIssueRecvPacketBundle (Numpackets: %d , actual : %d) \n", 
+        HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));
+    
+    do {
+        
+        pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); 
+        
+        if (pScatterReq == NULL) {
+                /* no scatter resources left, just let caller handle it the legacy way */
+            break;    
+        }        
+    
+        pScatterReq->CallerFlags = 0;
+             
+        if (PartialBundle) {
+                /* mark that this is a partial bundle, this has special ramifications to the
+                 * scatter completion routine */
+            pScatterReq->CallerFlags |= HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE;
+        }
+                   
+            /* convert HTC packets to scatter list */                   
+        for (i = 0; i < pktsToScatter; i++) {
+            int paddedLength;
+            
+            pPacket = HTC_PACKET_DEQUEUE(pRecvPktQueue);
+            A_ASSERT(pPacket != NULL);
+            
+            paddedLength = DEV_CALC_RECV_PADDED_LEN(&target->Device, pPacket->ActualLength);
+     
+            if ((scatterSpaceRemaining - paddedLength) < 0) {
+                    /* exceeds what we can transfer, put the packet back */  
+                HTC_PACKET_ENQUEUE_TO_HEAD(pRecvPktQueue,pPacket);
+                break;    
+            }
+                        
+            scatterSpaceRemaining -= paddedLength;
+                       
+            if (PartialBundle || (i < (pktsToScatter - 1))) {
+                    /* packet 0..n-1 cannot be checked for look-aheads since we are fetching a bundle
+                     * the last packet however can have it's lookahead used */
+                pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+            }
+            
+            /* note: 1 HTC packet per scatter entry */           
+                /* setup packet into */   
+            pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+            pScatterReq->ScatterList[i].Length = paddedLength;
+            
+            pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_PART_OF_BUNDLE;
+            
+            if (asyncMode) {
+                    /* save HTC packet for async completion routine */
+                pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;
+            } else {
+                    /* queue to caller's sync completion queue, caller will unload this when we return */
+                HTC_PACKET_ENQUEUE(pSyncCompletionQueue,pPacket);    
+            }             
+                   
+            A_ASSERT(pScatterReq->ScatterList[i].Length);
+            totalLength += pScatterReq->ScatterList[i].Length;
+        }            
+        
+        pScatterReq->TotalLength = totalLength;
+        pScatterReq->ValidScatterEntries = i;
+        
+        if (asyncMode) {
+            pScatterReq->CompletionRoutine = HTCAsyncRecvScatterCompletion;
+            pScatterReq->Context = target;
+        }
+        
+        status = DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_READ, asyncMode);
+        
+        if (A_SUCCESS(status)) {
+            *pNumPacketsFetched = i;    
+        }
+        
+        if (!asyncMode) {
+                /* free scatter request */
+            DEV_FREE_SCATTER_REQ(&target->Device, pScatterReq);   
+        }
+        
+    } while (FALSE);
+   
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCIssueRecvPacketBundle (status:%d) (fetched:%d) \n",
+            status,*pNumPacketsFetched));
+        
+    return status;
+}
+
+static INLINE void CheckRecvWaterMark(HTC_ENDPOINT    *pEndpoint)
+{  
+        /* see if endpoint is using a refill watermark 
+         * ** no need to use a lock here, since we are only inspecting...
+         * caller may must not hold locks when calling this function */
+    if (pEndpoint->EpCallBacks.RecvRefillWaterMark > 0) {
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->RxBuffers) < pEndpoint->EpCallBacks.RecvRefillWaterMark) {
+                /* call the re-fill handler before we continue */
+            pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+                                                pEndpoint->Id);
+        }
+    }  
+}
+
+/* callback when device layer or lookahead report parsing detects a pending message */
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    A_STATUS         status = A_OK;
+    HTC_PACKET      *pPacket;
+    HTC_ENDPOINT    *pEndpoint;
+    A_BOOL          asyncProc = FALSE;
+    A_UINT32        lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+    int             pktsFetched;
+    HTC_PACKET_QUEUE recvPktQueue, syncCompletedPktsQueue;
+    A_BOOL          partialBundle;
+    HTC_ENDPOINT_ID id;
+    int             totalFetched = 0;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler NumLookAheads: %d \n",NumLookAheads));
+    
+    if (pNumPktsFetched != NULL) {
+        *pNumPktsFetched = 0;    
+    }
+    
+    if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
+            /* We use async mode to get the packets if the device layer supports it.
+             * The device layer interfaces with HIF in which HIF may have restrictions on
+             * how interrupts are processed */
+        asyncProc = TRUE;
+    }
+
+    if (pAsyncProc != NULL) {
+            /* indicate to caller how we decided to process this */
+        *pAsyncProc = asyncProc;
+    }
+    
+    if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+        A_ASSERT(FALSE);
+        return A_EPROTO; 
+    }
+        
+        /* on first entry copy the lookaheads into our temp array for processing */
+    A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(A_UINT32)) * NumLookAheads);  
+            
+    while (TRUE) {
+        
+            /* reset packets queues */
+        INIT_HTC_PACKET_QUEUE(&recvPktQueue);
+        INIT_HTC_PACKET_QUEUE(&syncCompletedPktsQueue);
+        
+        if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+            status = A_EPROTO;
+            A_ASSERT(FALSE);
+            break;    
+        }
+   
+            /* first lookahead sets the expected endpoint IDs for all packets in a bundle */
+        id = ((HTC_FRAME_HDR *)&lookAheads[0])->EndpointID;
+        pEndpoint = &target->EndPoint[id];
+        
+        if (id >= ENDPOINT_MAX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MsgPend, Invalid Endpoint in look-ahead: %d \n",id));
+            status = A_EPROTO;
+            break;
+        }
+        
+            /* try to allocate as many HTC RX packets indicated by the lookaheads
+             * these packets are stored in the recvPkt queue */
+        status = AllocAndPrepareRxPackets(target, 
+                                          lookAheads, 
+                                          NumLookAheads,
+                                          pEndpoint, 
+                                          &recvPktQueue);        
+        if (A_FAILED(status)) {
+            break;    
+        }
+ 
+        if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) >= 2) {
+                /* a recv bundle was detected, force IRQ status re-check again */
+            REF_IRQ_STATUS_RECHECK(&target->Device);
+        }
+        
+        totalFetched += HTC_PACKET_QUEUE_DEPTH(&recvPktQueue);
+               
+            /* we've got packet buffers for all we can currently fetch, 
+             * this count is not valid anymore  */
+        NumLookAheads = 0;
+        partialBundle = FALSE;
+       
+            /* now go fetch the list of HTC packets */
+        while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {   
+            
+            pktsFetched = 0;
+                       
+            if (target->RecvBundlingEnabled && (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 1)) {             
+                    /* there are enough packets to attempt a bundle transfer and recv bundling is allowed  */
+                status = HTCIssueRecvPacketBundle(target,
+                                                  &recvPktQueue,
+                                                  asyncProc ? NULL : &syncCompletedPktsQueue,
+                                                  &pktsFetched,
+                                                  partialBundle);                                                   
+                if (A_FAILED(status)) {
+                    break;
+                }
+                
+                if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) != 0) {
+                        /* we couldn't fetch all packets at one time, this creates a broken
+                         * bundle  */
+                    partialBundle = TRUE;    
+                }                                                                     
+            }
+            
+                /* see if the previous operation fetched any packets using bundling */
+            if (0 == pktsFetched) {  
+                    /* dequeue one packet */
+                pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+                A_ASSERT(pPacket != NULL);                 
+                                     
+                if (asyncProc) {
+                        /* we use async mode to get the packet if the device layer supports it
+                         * set our callback and context */
+                    pPacket->Completion = HTCRecvCompleteHandler;
+                    pPacket->pContext = target;
+                } else {
+                        /* fully synchronous */
+                    pPacket->Completion = NULL;
+                }
+                
+                if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 0) {
+                        /* lookaheads in all packets except the last one in the bundle must be ignored */
+                    pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+                }
+                                    
+                    /* go fetch the packet */
+                status = HTCIssueRecv(target, pPacket);              
+                if (A_FAILED(status)) {
+                    break;
+                }  
+                               
+                if (!asyncProc) {               
+                        /* sent synchronously, queue this packet for synchronous completion */
+                    HTC_PACKET_ENQUEUE(&syncCompletedPktsQueue,pPacket);
+                } 
+                               
+            }
+            
+        }
+
+        if (A_SUCCESS(status)) {  
+            CheckRecvWaterMark(pEndpoint);
+        }
+            
+        if (asyncProc) {
+                /* we did this asynchronously so we can get out of the loop, the asynch processing
+                 * creates a chain of requests to continue processing pending messages in the
+                 * context of callbacks  */
+            break;
+        }
+
+            /* synchronous handling */
+        if (target->Device.DSRCanYield) {
+                /* for the SYNC case, increment count that tracks when the DSR should yield */
+            target->Device.CurrentDSRRecvCount++;    
+        }
+            
+            /* in the sync case, all packet buffers are now filled, 
+             * we can process each packet, check lookaheads and then repeat */ 
+             
+             /* unload sync completion queue */      
+        while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+            HTC_PACKET_QUEUE    container;
+           
+            pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+            A_ASSERT(pPacket != NULL);
+            
+            pEndpoint = &target->EndPoint[pPacket->Endpoint];           
+                /* reset count on each iteration, we are only interested in the last packet's lookahead
+                 * information when we break out of this loop */
+            NumLookAheads = 0;
+                /* process header for each of the recv packets
+                 * note: the lookahead of the last packet is useful for us to continue in this loop */            
+            status = HTCProcessRecvHeader(target,pPacket,lookAheads,&NumLookAheads);
+            if (A_FAILED(status)) {
+                break;
+            }
+            
+            if (HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+                    /* last packet's more packets flag is set based on the lookahead */
+                SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,NumLookAheads,pEndpoint,pPacket);
+            } else {
+                    /* packets in a bundle automatically have this flag set */
+                FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+            }
+                /* good packet, indicate it */
+            HTC_RX_STAT_PROFILE(target,pEndpoint,NumLookAheads);
+            
+            if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_PART_OF_BUNDLE) {
+                INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+            }
+            
+            INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+            DO_RCV_COMPLETION(pEndpoint,&container);
+        }
+
+        if (A_FAILED(status)) {
+            break;
+        }
+            
+        if (NumLookAheads == 0) {
+                /* no more look aheads */
+            break;    
+        }
+
+            /* when we process recv synchronously we need to check if we should yield and stop
+             * fetching more packets indicated by the embedded lookaheads */
+        if (target->Device.DSRCanYield) {
+            if (DEV_CHECK_RECV_YIELD(&target->Device)) {
+                    /* break out, don't fetch any more packets */
+                break;  
+            }  
+        }
+            
+
+        /* check whether other OS contexts have queued any WMI command/data for WLAN. 
+         * This check is needed only if WLAN Tx and Rx happens in same thread context */
+        A_CHECK_DRV_TX();
+        
+            /* for SYNCH processing, if we get here, we are running through the loop again due to a detected lookahead.
+             * Set flag that we should re-check IRQ status registers again before leaving IRQ processing,
+             * this can net better performance in high throughput situations */
+        REF_IRQ_STATUS_RECHECK(&target->Device);
+    }
+    
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("Failed to get pending recv messages (%d) \n",status));
+            /* cleanup any packets we allocated but didn't use to actually fetch any packets */                        
+        while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {   
+            pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+                /* clean up packets */
+            HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+        }
+            /* cleanup any packets in sync completion queue */
+        while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {   
+            pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+                /* clean up packets */
+            HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+        }
+    }
+    
+        /* before leaving, check to see if host ran out of buffers and needs to stop the
+         * receiver */
+    if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+                (" Host has no RX buffers, blocking receiver to prevent overrun.. \n"));
+            /* try to stop receive at the device layer */
+        DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
+    }
+    
+    if (pNumPktsFetched != NULL) {
+        *pNumPktsFetched = totalFetched;    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
+
+    return status;
+}
+
+A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint;
+    A_BOOL          unblockRecv = FALSE;
+    A_STATUS        status = A_OK;
+    HTC_PACKET      *pFirstPacket;
+
+    pFirstPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+    
+    if (NULL == pFirstPacket) {
+        A_ASSERT(FALSE);
+        return A_EINVAL;    
+    }
+    
+    AR_DEBUG_ASSERT(pFirstPacket->Endpoint < ENDPOINT_MAX);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+                    ("+- HTCAddReceivePktMultiple : endPointId: %d, cnt:%d, length: %d\n",
+                    pFirstPacket->Endpoint,
+                    HTC_PACKET_QUEUE_DEPTH(pPktQueue), 
+                    pFirstPacket->BufferLength));
+
+    do {
+
+        pEndpoint = &target->EndPoint[pFirstPacket->Endpoint];
+
+        LOCK_HTC_RX(target);
+
+        if (HTC_STOPPING(target)) {
+            HTC_PACKET *pPacket;
+            
+            UNLOCK_HTC_RX(target);
+            
+                /* walk through queue and mark each one canceled */
+            HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+                pPacket->Status = A_ECANCELED;    
+            } HTC_PACKET_QUEUE_ITERATE_END;
+            
+            DO_RCV_COMPLETION(pEndpoint,pPktQueue);
+            break;
+        }
+
+            /* store receive packets */
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RxBuffers, pPktQueue);
+
+            /* check if we are blocked waiting for a new buffer */
+        if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+            if (target->EpWaitingForBuffers == pFirstPacket->Endpoint) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
+                    target->EpWaitingForBuffers));
+                target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+                target->EpWaitingForBuffers = ENDPOINT_MAX;
+                unblockRecv = TRUE;
+            }
+        }
+
+        UNLOCK_HTC_RX(target);
+
+        if (unblockRecv && !HTC_STOPPING(target)) {
+                /* TODO : implement a buffer threshold count? */
+            DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+/* Makes a buffer available to the HTC module */
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+    HTC_PACKET_QUEUE queue;
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); 
+    return HTCAddReceivePktMultiple(HTCHandle, &queue);       
+}
+
+void HTCUnblockRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_BOOL      unblockRecv = FALSE;
+
+    LOCK_HTC_RX(target);
+
+        /* check if we are blocked waiting for a new buffer */
+    if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n",
+            target->EpWaitingForBuffers));
+        target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+        target->EpWaitingForBuffers = ENDPOINT_MAX;
+        unblockRecv = TRUE;
+    }
+
+    UNLOCK_HTC_RX(target);
+
+    if (unblockRecv && !HTC_STOPPING(target)) {
+            /* re-enable */
+        DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC);
+    }
+}
+
+static void HTCFlushRxQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET_QUEUE *pQueue)
+{
+    HTC_PACKET  *pPacket;
+    HTC_PACKET_QUEUE container;
+    
+    LOCK_HTC_RX(target);
+
+    while (1) {
+        pPacket = HTC_PACKET_DEQUEUE(pQueue);
+        if (NULL == pPacket) {
+            break;
+        }
+        UNLOCK_HTC_RX(target);
+        pPacket->Status = A_ECANCELED;
+        pPacket->ActualLength = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("  Flushing RX packet:0x%X, length:%d, ep:%d \n",
+                (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint));
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+            /* give the packet back */
+        DO_RCV_COMPLETION(pEndpoint,&container);
+        LOCK_HTC_RX(target);
+    }
+    
+    UNLOCK_HTC_RX(target);
+}
+
+static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+        /* flush any recv indications not already made */
+    HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RecvIndicationQueue);
+        /* flush any rx buffers */
+    HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RxBuffers);
+}
+
+void HTCFlushRecvBuffers(HTC_TARGET *target)
+{
+    HTC_ENDPOINT    *pEndpoint;
+    int             i;
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        if (pEndpoint->ServiceID == 0) {
+                /* not in use.. */
+            continue;
+        }
+        HTCFlushEndpointRX(target,pEndpoint);
+    }
+}
+
+
+void HTCEnableRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    if (!HTC_STOPPING(target)) {
+            /* re-enable */
+        DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+    }
+}
+
+void HTCDisableRecv(HTC_HANDLE HTCHandle)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+    if (!HTC_STOPPING(target)) {
+            /* disable */
+        DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+    }
+}
+
+int HTCGetNumRecvBuffers(HTC_HANDLE      HTCHandle,
+                         HTC_ENDPOINT_ID Endpoint)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);    
+    return HTC_PACKET_QUEUE_DEPTH(&(target->EndPoint[Endpoint].RxBuffers));
+}
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_send.c b/drivers/net/wireless/ath6kl/htc2/htc_send.c
new file mode 100644
index 000000000000..13eef67aaeaf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_send.c
@@ -0,0 +1,1019 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_send.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+typedef enum _HTC_SEND_QUEUE_RESULT {
+    HTC_SEND_QUEUE_OK = 0,    /* packet was queued */
+    HTC_SEND_QUEUE_DROP = 1,  /* this packet should be dropped */
+} HTC_SEND_QUEUE_RESULT;
+
+#define DO_EP_TX_COMPLETION(ep,q)  DoSendCompletion(ep,q)
+
+/* call the distribute credits callback with the distribution */
+#define DO_DISTRIBUTION(t,reason,description,pList) \
+{                                             \
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,           \
+        ("  calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \
+                (description),                                           \
+                (A_UINT32)(t)->DistributeCredits,                        \
+                (A_UINT32)(t)->pCredDistContext,                         \
+                (A_UINT32)pList));                                       \
+    (t)->DistributeCredits((t)->pCredDistContext,                        \
+                           (pList),                                      \
+                           (reason));                                    \
+}
+
+static void DoSendCompletion(HTC_ENDPOINT       *pEndpoint,
+                             HTC_PACKET_QUEUE   *pQueueToIndicate)
+{           
+    do {
+                
+        if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+                /* nothing to indicate */
+            break;    
+        }
+ 
+        if (pEndpoint->EpCallBacks.EpTxCompleteMultiple != NULL) {    
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d, send complete multiple callback (%d pkts) \n",
+                     pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+                /* a multiple send complete handler is being used, pass the queue to the handler */                             
+            pEndpoint->EpCallBacks.EpTxCompleteMultiple(pEndpoint->EpCallBacks.pContext,
+                                                        pQueueToIndicate);
+                /* all packets are now owned by the callback, reset queue to be safe */
+            INIT_HTC_PACKET_QUEUE(pQueueToIndicate);                                                      
+        } else {
+            HTC_PACKET *pPacket;  
+            /* using legacy EpTxComplete */         
+            do {
+                pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d send complete callback on packet 0x%X \n", \
+                        pEndpoint->Id, (A_UINT32)(pPacket)));
+                pEndpoint->EpCallBacks.EpTxComplete(pEndpoint->EpCallBacks.pContext, pPacket);                                              
+            } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));                                              
+        }
+        
+    } while (FALSE);
+
+}
+
+/* do final completion on sent packet */
+static INLINE void CompleteSentPacket(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET *pPacket)
+{
+    pPacket->Completion = NULL;  
+    
+    if (A_FAILED(pPacket->Status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+            ("CompleteSentPacket: request failed (status:%d, ep:%d, length:%d creds:%d) \n",
+                pPacket->Status, pPacket->Endpoint, pPacket->ActualLength, pPacket->PktInfo.AsTx.CreditsUsed));                
+            /* on failure to submit, reclaim credits for this packet */        
+        LOCK_HTC_TX(target);        
+        pEndpoint->CreditDist.TxCreditsToDist += pPacket->PktInfo.AsTx.CreditsUsed;
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_SEND_COMPLETE,
+                        "Send Complete",
+                        target->EpCreditDistributionListHead->pNext);
+        UNLOCK_HTC_TX(target);            
+    }
+        /* first, fixup the head room we allocated */
+    pPacket->pBuffer += HTC_HDR_LENGTH; 
+}
+
+/* our internal send packet completion handler when packets are submited to the AR6K device
+ * layer */
+static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
+{
+    HTC_TARGET      *target = (HTC_TARGET *)Context;
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    HTC_PACKET_QUEUE container;
+    
+    CompleteSentPacket(target,pEndpoint,pPacket);
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+        /* do completion */
+    DO_EP_TX_COMPLETION(pEndpoint,&container);
+}
+
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket)
+{
+    A_STATUS status;
+    A_BOOL   sync = FALSE;
+
+    if (pPacket->Completion == NULL) {
+            /* mark that this request was synchronously issued */
+        sync = TRUE;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    ("+-HTCIssueSend: transmit length : %d (%s) \n",
+                    pPacket->ActualLength + HTC_HDR_LENGTH,
+                    sync ? "SYNC" : "ASYNC" ));
+
+        /* send message to device */
+    status = DevSendPacket(&target->Device,
+                           pPacket,
+                           pPacket->ActualLength + HTC_HDR_LENGTH);
+
+    if (sync) {
+            /* use local sync variable.  If this was issued asynchronously, pPacket is no longer
+             * safe to access. */
+        pPacket->pBuffer += HTC_HDR_LENGTH;
+    }
+    
+    /* if this request was asynchronous, the packet completion routine will be invoked by
+     * the device layer when the HIF layer completes the request */
+
+    return status;
+}
+
+    /* get HTC send packets from the TX queue on an endpoint */
+static INLINE void GetHTCSendPackets(HTC_TARGET        *target, 
+                                     HTC_ENDPOINT      *pEndpoint, 
+                                     HTC_PACKET_QUEUE  *pQueue)
+{
+    int          creditsRequired;
+    int          remainder;
+    A_UINT8      sendFlags;
+    HTC_PACKET   *pPacket;
+    unsigned int transferLength;
+
+    /****** NOTE : the TX lock is held when this function is called *****************/
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+GetHTCSendPackets \n"));
+     
+        /* loop until we can grab as many packets out of the queue as we can */       
+    while (TRUE) {    
+        
+        sendFlags = 0;   
+            /* get packet at head, but don't remove it */
+        pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);       
+        if (pPacket == NULL) {
+            break;    
+        }
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n",
+                (A_UINT32)pPacket, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+        
+        transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, pPacket->ActualLength + HTC_HDR_LENGTH);       
+       
+        if (transferLength <= target->TargetCreditSize) {
+            creditsRequired = 1;    
+        } else {
+                /* figure out how many credits this message requires */
+            creditsRequired = transferLength / target->TargetCreditSize;
+            remainder = transferLength % target->TargetCreditSize;
+            
+            if (remainder) {
+                creditsRequired++;
+            }
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d   Got:%d\n",
+                            creditsRequired, pEndpoint->CreditDist.TxCredits));
+
+        if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+
+                /* not enough credits */
+            if (pPacket->Endpoint == ENDPOINT_0) {
+                    /* leave it in the queue */
+                break;
+            }
+                /* invoke the registered distribution function only if this is not
+                 * endpoint 0, we let the driver layer provide more credits if it can.
+                 * We pass the credit distribution list starting at the endpoint in question
+                 * */
+
+                /* set how many credits we need  */
+            pEndpoint->CreditDist.TxCreditsSeek =
+                                    creditsRequired - pEndpoint->CreditDist.TxCredits;
+            DO_DISTRIBUTION(target,
+                            HTC_CREDIT_DIST_SEEK_CREDITS,
+                            "Seek Credits",
+                            &pEndpoint->CreditDist);
+            pEndpoint->CreditDist.TxCreditsSeek = 0;
+
+            if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+                    /* still not enough credits to send, leave packet in the queue */
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    (" Not enough credits for ep %d leaving packet in queue..\n",
+                    pPacket->Endpoint));
+                break;
+            }
+
+        }
+
+        pEndpoint->CreditDist.TxCredits -= creditsRequired;
+        INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
+
+            /* check if we need credits back from the target */
+        if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+                /* we are getting low on credits, see if we can ask for more from the distribution function */
+            pEndpoint->CreditDist.TxCreditsSeek =
+                        pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits;
+
+            DO_DISTRIBUTION(target,
+                            HTC_CREDIT_DIST_SEEK_CREDITS,
+                            "Seek Credits",
+                            &pEndpoint->CreditDist);
+
+            pEndpoint->CreditDist.TxCreditsSeek = 0;
+                /* see if we were successful in getting more */
+            if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+                    /* tell the target we need credits ASAP! */
+                sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
+                INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits  \n"));
+            }
+        }
+                        
+            /* now we can fully dequeue */
+        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); 
+            /* save the number of credits this packet consumed */
+        pPacket->PktInfo.AsTx.CreditsUsed = creditsRequired;
+            /* all TX packets are handled asynchronously */
+        pPacket->Completion = HTCSendPktCompletionHandler;
+        pPacket->pContext = target;
+        INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
+            /* save send flags */
+        pPacket->PktInfo.AsTx.SendFlags = sendFlags;
+        pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;         
+        pEndpoint->SeqNo++;
+            /* queue this packet into the caller's queue */
+        HTC_PACKET_ENQUEUE(pQueue,pPacket);
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-GetHTCSendPackets \n"));
+     
+}
+
+static void HTCAsyncSendScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+    int                 i;    
+    HTC_PACKET          *pPacket;
+    HTC_ENDPOINT        *pEndpoint = (HTC_ENDPOINT *)pScatterReq->Context;
+    HTC_TARGET          *target = (HTC_TARGET *)pEndpoint->target;
+    A_STATUS            status = A_OK;
+    HTC_PACKET_QUEUE    sendCompletes;
+    
+    INIT_HTC_PACKET_QUEUE(&sendCompletes);
+          
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCAsyncSendScatterCompletion  TotLen: %d  Entries: %d\n",
+        pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+    
+    DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+           
+    if (A_FAILED(pScatterReq->CompletionStatus)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Send Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));            
+        status = A_ERROR;
+    }
+    
+        /* walk through the scatter list and process */
+    for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+        pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+        A_ASSERT(pPacket != NULL);
+        pPacket->Status = status;
+        CompleteSentPacket(target,pEndpoint,pPacket);
+            /* add it to the completion queue */
+        HTC_PACKET_ENQUEUE(&sendCompletes, pPacket);      
+    }
+    
+        /* free scatter request */
+    DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+        /* complete all packets */
+    DO_EP_TX_COMPLETION(pEndpoint,&sendCompletes);
+               
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCAsyncSendScatterCompletion \n"));
+}
+
+    /* drain a queue and send as bundles 
+     * this function may return without fully draining the queue under the following conditions :
+     *    - scatter resources are exhausted
+     *    - a message that will consume a partial credit will stop the bundling process early 
+     *    - we drop below the minimum number of messages for a bundle 
+     * */
+static void HTCIssueSendBundle(HTC_ENDPOINT      *pEndpoint, 
+                               HTC_PACKET_QUEUE  *pQueue, 
+                               int               *pBundlesSent, 
+                               int               *pTotalBundlesPkts)
+{
+    int                 pktsToScatter;
+    unsigned int        scatterSpaceRemaining;
+    HIF_SCATTER_REQ     *pScatterReq = NULL;
+    int                 i, packetsInScatterReq;
+    unsigned int        transferLength;
+    HTC_PACKET          *pPacket;
+    A_BOOL              done = FALSE;
+    int                 bundlesSent = 0;
+    int                 totalPktsInBundle = 0;
+    HTC_TARGET          *target = pEndpoint->target;
+    int                 creditRemainder = 0;
+    int                 creditPad;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCIssueSendBundle \n"));
+    
+    while (!done) {
+          
+        pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pQueue);
+        pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+        
+        if (pktsToScatter < HTC_MIN_HTC_MSGS_TO_BUNDLE) {
+                /* not enough to bundle */
+            break;    
+        }
+        
+        pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); 
+        
+        if (pScatterReq == NULL) {
+                /* no scatter resources  */
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("   No more scatter resources \n"));
+            break;    
+        }       
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("   pkts to scatter: %d \n", pktsToScatter));
+        
+        pScatterReq->TotalLength = 0;
+        pScatterReq->ValidScatterEntries = 0;  
+        
+        packetsInScatterReq = 0;
+        scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device);
+        
+        for (i = 0; i < pktsToScatter; i++) {
+            
+            pScatterReq->ScatterList[i].pCallerContexts[0] = NULL;
+            
+            pPacket = HTC_GET_PKT_AT_HEAD(pQueue);        
+            if (pPacket == NULL) {
+                A_ASSERT(FALSE);
+                break;    
+            }
+            
+            creditPad = 0;
+            transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, 
+                                                      pPacket->ActualLength + HTC_HDR_LENGTH);               
+                /* see if the padded transfer length falls on a credit boundary */         
+            creditRemainder = transferLength % target->TargetCreditSize;
+                                
+            if (creditRemainder != 0) {
+                    /* the transfer consumes a "partial" credit, this packet cannot be bundled unless
+                     * we add additional "dummy" padding (max 255 bytes) to consume the entire credit 
+                     *** NOTE: only allow the send padding if the endpoint is allowed to */
+                if (pEndpoint->LocalConnectionFlags & HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING) {
+                    if (transferLength < target->TargetCreditSize) {
+                            /* special case where the transfer is less than a credit */
+                        creditPad = target->TargetCreditSize - transferLength;                    
+                    } else {
+                        creditPad = creditRemainder;    
+                    }
+                                    
+                        /* now check to see if we can indicate padding in the HTC header */
+                    if ((creditPad > 0) && (creditPad <= 255)) {
+                            /* adjust the transferlength of this packet with the new credit padding */
+                        transferLength += creditPad;            
+                    } else {
+                            /* the amount to pad is too large, bail on this packet, we have to 
+                             * send it using the non-bundled method */
+                        pPacket = NULL;
+                    }
+                } else {
+                        /* bail on this packet, user does not want padding applied */
+                    pPacket = NULL;    
+                }
+            }                       
+                       
+            if (NULL == pPacket) {
+                    /* can't bundle */
+                done = TRUE;
+                break;    
+            }         
+               
+            if (scatterSpaceRemaining < transferLength) {
+                    /* exceeds what we can transfer */
+                break;    
+            }
+            
+            scatterSpaceRemaining -= transferLength;
+                /* now remove it from the queue */ 
+            pPacket = HTC_PACKET_DEQUEUE(pQueue);           
+                /* save it in the scatter list */
+            pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;            
+                /* prepare packet and flag message as part of a send bundle */               
+            HTC_PREPARE_SEND_PKT(pPacket,
+                                 pPacket->PktInfo.AsTx.SendFlags | HTC_FLAGS_SEND_BUNDLE, 
+                                 creditPad,                                 
+                                 pPacket->PktInfo.AsTx.SeqNo); 
+            pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+            pScatterReq->ScatterList[i].Length = transferLength;
+            A_ASSERT(transferLength);
+            pScatterReq->TotalLength += transferLength;
+            pScatterReq->ValidScatterEntries++;
+            packetsInScatterReq++;             
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("  %d, Adding packet : 0x%X, len:%d (remaining space:%d) \n", 
+                    i, (A_UINT32)pPacket,transferLength,scatterSpaceRemaining));                                                      
+        }
+                    
+        if (packetsInScatterReq >= HTC_MIN_HTC_MSGS_TO_BUNDLE) {          
+                /* send path is always asynchronous */
+            pScatterReq->CompletionRoutine = HTCAsyncSendScatterCompletion;
+            pScatterReq->Context = pEndpoint;
+            bundlesSent++;
+            totalPktsInBundle += packetsInScatterReq;
+            packetsInScatterReq = 0;
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Send Scatter total bytes: %d , entries: %d\n",
+                                pScatterReq->TotalLength,pScatterReq->ValidScatterEntries));
+            DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_WRITE, DEV_SCATTER_ASYNC);
+                /* we don't own this anymore */
+            pScatterReq = NULL;
+                /* try to send some more */
+            continue;               
+        } 
+        
+            /* not enough packets to use the scatter request, cleanup */
+        if (pScatterReq != NULL) {
+            if (packetsInScatterReq > 0) {
+                    /* work backwards to requeue requests */
+                for (i = (packetsInScatterReq - 1); i >= 0; i--) {
+                    pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+                    if (pPacket != NULL) {
+                            /* undo any prep */
+                        HTC_UNPREPARE_SEND_PKT(pPacket);
+                            /* queue back to the head */
+                        HTC_PACKET_ENQUEUE_TO_HEAD(pQueue,pPacket);   
+                    }  
+                }  
+            }               
+            DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);    
+        }  
+        
+        /* if we get here, we sent all that we could, get out */
+        break;  
+        
+    }
+    
+    *pBundlesSent = bundlesSent;
+    *pTotalBundlesPkts = totalPktsInBundle;
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCIssueSendBundle (sent:%d) \n",bundlesSent));  
+     
+    return; 
+}
+
+/*
+ * if there are no credits, the packet(s) remains in the queue.
+ * this function returns the result of the attempt to send a queue of HTC packets */
+static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET       *target,
+                                        HTC_ENDPOINT     *pEndpoint,
+                                        HTC_PACKET_QUEUE *pCallersSendQueue)
+{
+    HTC_PACKET_QUEUE      sendQueue; /* temp queue to hold packets at various stages */
+    HTC_PACKET            *pPacket;
+    int                   bundlesSent;
+    int                   pktsInBundles;
+    int                   overflow;
+    HTC_SEND_QUEUE_RESULT result = HTC_SEND_QUEUE_OK;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (Queue:0x%X Depth:%d)\n",
+            (A_UINT32)pCallersSendQueue, 
+            (pCallersSendQueue == NULL) ? 0 : HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue)));
+
+        /* init the local send queue */
+    INIT_HTC_PACKET_QUEUE(&sendQueue);
+    
+    do {
+        
+        if (NULL == pCallersSendQueue) {
+                /* caller didn't provide a queue, just wants us to check queues and send */
+            break;    
+        }
+        
+        if (HTC_QUEUE_EMPTY(pCallersSendQueue)) {
+                /* empty queue */
+            result = HTC_SEND_QUEUE_DROP;
+            break;    
+        }
+  
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) >= pEndpoint->MaxTxQueueDepth) {
+                    /* we've already overflowed */
+            overflow = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);    
+        } else {
+                /* figure out how much we will overflow by */
+            overflow = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+            overflow += HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue); 
+                /* figure out how much we will overflow the TX queue by */
+            overflow -= pEndpoint->MaxTxQueueDepth;     
+        }
+                     
+            /* if overflow is negative or zero, we are okay */    
+        if (overflow > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, 
+                (" Endpoint %d, TX queue will overflow :%d , Tx Depth:%d, Max:%d \n",
+                pEndpoint->Id, overflow, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue), pEndpoint->MaxTxQueueDepth));      
+        }   
+        if ((overflow <= 0) || (pEndpoint->EpCallBacks.EpSendFull == NULL)) {
+                /* all packets will fit or caller did not provide send full indication handler
+                 * --  just move all of them to the local sendQueue object */
+            HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&sendQueue, pCallersSendQueue);           
+        } else {
+            int               i;
+            int               goodPkts = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue) - overflow;
+                        
+            A_ASSERT(goodPkts >= 0);
+                /* we have overflowed, and a callback is provided */        
+                /* dequeue all non-overflow packets into the sendqueue */
+            for (i = 0; i < goodPkts; i++) {
+                    /* pop off caller's queue*/
+                pPacket = HTC_PACKET_DEQUEUE(pCallersSendQueue);
+                A_ASSERT(pPacket != NULL);
+                    /* insert into local queue */
+                HTC_PACKET_ENQUEUE(&sendQueue,pPacket);
+            }
+            
+                /* the caller's queue has all the packets that won't fit*/                
+                /* walk through the caller's queue and indicate each one to the send full handler */            
+            ITERATE_OVER_LIST_ALLOW_REMOVE(&pCallersSendQueue->QueueHead, pPacket, HTC_PACKET, ListLink) {            
+                
+                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Indicating overflowed TX packet: 0x%X \n", 
+                                            (A_UINT32)pPacket));    
+                if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
+                                                      pPacket) == HTC_SEND_FULL_DROP) {
+                        /* callback wants the packet dropped */
+                    INC_HTC_EP_STAT(pEndpoint, TxDropped, 1);
+                        /* leave this one in the caller's queue for cleanup */
+                } else {
+                        /* callback wants to keep this packet, remove from caller's queue */
+                    HTC_PACKET_REMOVE(pCallersSendQueue, pPacket);
+                        /* put it in the send queue */
+                    HTC_PACKET_ENQUEUE(&sendQueue,pPacket);                                      
+                }
+                
+            } ITERATE_END;
+            
+            if (HTC_QUEUE_EMPTY(&sendQueue)) {
+                    /* no packets made it in, caller will cleanup */
+                result = HTC_SEND_QUEUE_DROP;
+                break;   
+            } 
+        }
+        
+    } while (FALSE);
+    
+    if (result != HTC_SEND_QUEUE_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
+        return result;
+    }
+
+    LOCK_HTC_TX(target);
+    
+    if (!HTC_QUEUE_EMPTY(&sendQueue)) {
+            /* transfer packets */
+        HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->TxQueue,&sendQueue);
+        A_ASSERT(HTC_QUEUE_EMPTY(&sendQueue));
+        INIT_HTC_PACKET_QUEUE(&sendQueue); 
+    }
+    
+        /* increment tx processing count on entry */    
+    pEndpoint->TxProcessCount++;
+    if (pEndpoint->TxProcessCount > 1) {
+            /* another thread or task is draining the TX queues on this endpoint
+             * that thread will reset the tx processing count when the queue is drained */
+        pEndpoint->TxProcessCount--;
+        UNLOCK_HTC_TX(target);
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend (busy) \n"));
+        return HTC_SEND_QUEUE_OK; 
+    }
+    
+    /***** beyond this point only 1 thread may enter ******/
+            
+        /* now drain the endpoint TX queue for transmission as long as we have enough
+         * credits */
+    while (TRUE) {
+          
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) == 0) {
+            break;
+        }
+                
+            /* get all the packets for this endpoint that we can for this pass */
+        GetHTCSendPackets(target, pEndpoint, &sendQueue);        
+     
+        if (HTC_PACKET_QUEUE_DEPTH(&sendQueue) == 0) {
+                /* didn't get any packets due to a lack of credits */
+            break;    
+        }
+        
+        UNLOCK_HTC_TX(target);
+        
+            /* any packets to send are now in our local send queue */    
+         
+        bundlesSent = 0;
+        pktsInBundles = 0;
+     
+        while (TRUE) {
+            
+                /* try to send a bundle on each pass */            
+            if ((target->SendBundlingEnabled) &&
+                    (HTC_PACKET_QUEUE_DEPTH(&sendQueue) >= HTC_MIN_HTC_MSGS_TO_BUNDLE)) {
+                 int temp1,temp2;       
+                    /* bundling is enabled and there is at least a minimum number of packets in the send queue
+                     * send what we can in this pass */                       
+                 HTCIssueSendBundle(pEndpoint, &sendQueue, &temp1, &temp2);
+                 bundlesSent += temp1;
+                 pktsInBundles += temp2;
+            }
+        
+                /* if not bundling or there was a packet that could not be placed in a bundle, pull it out
+                 * and send it the normal way */
+            pPacket = HTC_PACKET_DEQUEUE(&sendQueue);
+            if (NULL == pPacket) {
+                    /* local queue is fully drained */
+                break;    
+            }
+            HTC_PREPARE_SEND_PKT(pPacket,
+                                 pPacket->PktInfo.AsTx.SendFlags,
+                                 0,
+                                 pPacket->PktInfo.AsTx.SeqNo);  
+            HTCIssueSend(target, pPacket);
+            
+                /* go back and see if we can bundle some more */
+        }
+        
+        LOCK_HTC_TX(target);
+        
+        INC_HTC_EP_STAT(pEndpoint, TxBundles, bundlesSent);
+        INC_HTC_EP_STAT(pEndpoint, TxPacketsBundled, pktsInBundles);
+        
+    }
+        
+        /* done with this endpoint, we can clear the count */
+    pEndpoint->TxProcessCount = 0;
+    UNLOCK_HTC_TX(target);
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
+
+    return HTC_SEND_QUEUE_OK;
+}
+
+A_STATUS  HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint;
+    HTC_PACKET      *pPacket;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCSendPktsMultiple: Queue: 0x%X, Pkts %d \n",
+                    (A_UINT32)pPktQueue, HTC_PACKET_QUEUE_DEPTH(pPktQueue)));
+    
+        /* get packet at head to figure out which endpoint these packets will go into */
+    pPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+    if (NULL == pPacket) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+        return A_EINVAL;   
+    }
+    
+    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+    pEndpoint = &target->EndPoint[pPacket->Endpoint];
+    
+    HTCTrySend(target, pEndpoint, pPktQueue);
+
+        /* do completion on any packets that couldn't get in */
+    if (!HTC_QUEUE_EMPTY(pPktQueue)) {        
+        
+        HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+            if (HTC_STOPPING(target)) {
+                pPacket->Status = A_ECANCELED;
+            } else {
+                pPacket->Status = A_NO_RESOURCE;
+            } 
+        } HTC_PACKET_QUEUE_ITERATE_END;
+                   
+        DO_EP_TX_COMPLETION(pEndpoint,pPktQueue);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+
+    return A_OK;   
+}
+
+/* HTC API - HTCSendPkt */
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+    HTC_PACKET_QUEUE queue;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+                    ("+-HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n",
+                    pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength));                   
+    INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); 
+    return HTCSendPktsMultiple(HTCHandle, &queue);
+}
+
+/* check TX queues to drain because of credit distribution update */
+static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
+{
+    HTC_ENDPOINT                *pEndpoint;
+    HTC_ENDPOINT_CREDIT_DIST    *pDistItem;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
+    pDistItem = target->EpCreditDistributionListHead;
+
+        /* run through the credit distribution list to see
+         * if there are packets queued
+         * NOTE: no locks need to be taken since the distribution list
+         * is not dynamic (cannot be re-ordered) and we are not modifying any state */
+    while (pDistItem != NULL) {
+        pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
+
+        if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) > 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
+                    pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+                /* try to start the stalled queue, this list is ordered by priority.
+                 * Highest priority queue get's processed first, if there are credits available the
+                 * highest priority queue will get a chance to reclaim credits from lower priority
+                 * ones */
+            HTCTrySend(target, pEndpoint, NULL);
+        }
+
+        pDistItem = pDistItem->pNext;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
+}
+
+/* process credit reports and call distribution function */
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
+{
+    int             i;
+    HTC_ENDPOINT    *pEndpoint;
+    int             totalCredits = 0;
+    A_BOOL          doDist = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
+
+        /* lock out TX while we update credits */
+    LOCK_HTC_TX(target);
+
+    for (i = 0; i < NumEntries; i++, pRpt++) {
+        if (pRpt->EndpointID >= ENDPOINT_MAX) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        pEndpoint = &target->EndPoint[pRpt->EndpointID];
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Endpoint %d got %d credits \n",
+                pRpt->EndpointID, pRpt->Credits));
+
+
+#ifdef HTC_EP_STAT_PROFILING
+
+        INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
+        INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
+
+        if (FromEndpoint == pRpt->EndpointID) {
+                /* this credit report arrived on the same endpoint indicating it arrived in an RX
+                 * packet */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
+        } else if (FromEndpoint == ENDPOINT_0) {
+                /* this credit arrived on endpoint 0 as a NULL message */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
+        } else {
+                /* arrived on another endpoint */
+            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
+            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
+        }
+
+#endif
+
+        if (ENDPOINT_0 == pRpt->EndpointID) {
+                /* always give endpoint 0 credits back */
+            pEndpoint->CreditDist.TxCredits += pRpt->Credits;
+        } else {
+                /* for all other endpoints, update credits to distribute, the distribution function
+                 * will handle giving out credits back to the endpoints */
+            pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
+                /* flag that we have to do the distribution */
+            doDist = TRUE;
+        }
+        
+            /* refresh tx depth for distribution function that will recover these credits
+             * NOTE: this is only valid when there are credits to recover! */
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        
+        totalCredits += pRpt->Credits;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Report indicated %d credits to distribute \n", totalCredits));
+
+    if (doDist) {
+            /* this was a credit return based on a completed send operations
+             * note, this is done with the lock held */
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_SEND_COMPLETE,
+                        "Send Complete",
+                        target->EpCreditDistributionListHead->pNext);
+    }
+
+    UNLOCK_HTC_TX(target);
+
+    if (totalCredits) {
+        HTCCheckEndpointTxQueues(target);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
+}
+
+/* flush endpoint TX queue */
+static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
+{
+    HTC_PACKET          *pPacket;
+    HTC_PACKET_QUEUE    discardQueue;
+    HTC_PACKET_QUEUE    container;
+
+        /* initialize the discard queue */
+    INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+    LOCK_HTC_TX(target);
+
+        /* interate from the front of the TX queue and flush out packets */
+    ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue.QueueHead, pPacket, HTC_PACKET, ListLink) {
+
+            /* check for removal */
+        if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
+                /* remove from queue */
+            HTC_PACKET_REMOVE(&pEndpoint->TxQueue, pPacket);
+                /* add it to the discard pile */
+            HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
+        }
+
+    } ITERATE_END;
+
+    UNLOCK_HTC_TX(target);
+
+        /* empty the discard queue */
+    while (1) {
+        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+        if (NULL == pPacket) {
+            break;
+        }
+        pPacket->Status = A_ECANCELED;
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("  Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n",
+                (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
+        INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+        DO_EP_TX_COMPLETION(pEndpoint,&container);
+    }
+
+}
+
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d  ServiceID: 0x%X    --------------\n",
+                        pEPDist->Endpoint, pEPDist->ServiceID));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n",
+                (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags          : 0x%X \n", pEPDist->DistFlags));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm      : %d \n", pEPDist->TxCreditsNorm));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin       : %d \n", pEPDist->TxCreditsMin));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits          : %d \n", pEPDist->TxCredits));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned  : %d \n", pEPDist->TxCreditsAssigned));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek      : %d \n", pEPDist->TxCreditsSeek));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize       : %d \n", pEPDist->TxCreditSize));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist    : %d \n", pEPDist->TxCreditsToDist));
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth       : %d \n", 
+                    HTC_PACKET_QUEUE_DEPTH(&((HTC_ENDPOINT *)pEPDist->pHTCReserved)->TxQueue)));                                      
+    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
+}
+
+void DumpCreditDistStates(HTC_TARGET *target)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
+
+    while (pEPList != NULL) {
+        DumpCreditDist(pEPList);
+        pEPList = pEPList->pNext;
+    }
+
+    if (target->DistributeCredits != NULL) {
+        DO_DISTRIBUTION(target,
+                        HTC_DUMP_CREDIT_STATE,
+                        "Dump State",
+                        NULL);
+    }
+}
+
+/* flush all send packets from all endpoint queues */
+void HTCFlushSendPkts(HTC_TARGET *target)
+{
+    HTC_ENDPOINT    *pEndpoint;
+    int             i;
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+        DumpCreditDistStates(target);
+    }
+
+    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+        pEndpoint = &target->EndPoint[i];
+        if (pEndpoint->ServiceID == 0) {
+                /* not in use.. */
+            continue;
+        }
+        HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
+    }
+
+
+}
+
+/* HTC API to flush an endpoint's TX queue*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+
+    if (pEndpoint->ServiceID == 0) {
+        AR_DEBUG_ASSERT(FALSE);
+        /* not in use.. */
+        return;
+    }
+
+    HTCFlushEndpointTX(target, pEndpoint, Tag);
+}
+
+/* HTC API to indicate activity to the credit distribution function */
+void HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
+                               HTC_ENDPOINT_ID Endpoint,
+                               A_BOOL          Active)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+    A_BOOL          doDist = FALSE;
+
+    if (pEndpoint->ServiceID == 0) {
+        AR_DEBUG_ASSERT(FALSE);
+        /* not in use.. */
+        return;
+    }
+
+    LOCK_HTC_TX(target);
+
+    if (Active) {
+        if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
+                /* mark active now */
+            pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
+            doDist = TRUE;
+        }
+    } else {
+        if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+                /* mark inactive now */
+            pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
+            doDist = TRUE;
+        }
+    }
+
+    if (doDist) {
+            /* indicate current Tx Queue depth to the credit distribution function */
+        pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+        /* do distribution again based on activity change
+         * note, this is done with the lock held */
+        DO_DISTRIBUTION(target,
+                        HTC_CREDIT_DIST_ACTIVITY_CHANGE,
+                        "Activity Change",
+                        target->EpCreditDistributionListHead->pNext);
+    }
+
+    UNLOCK_HTC_TX(target);
+
+    if (doDist && !Active) {
+        /* if a stream went inactive and this resulted in a credit distribution change,
+         * some credits may now be available for HTC packets that are stuck in
+         * HTC queues */
+        HTCCheckEndpointTxQueues(target);
+    }
+}
+
+A_BOOL HTCIsEndpointActive(HTC_HANDLE      HTCHandle,
+                           HTC_ENDPOINT_ID Endpoint)
+{
+    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
+
+    if (pEndpoint->ServiceID == 0) {
+        return FALSE;
+    }
+    
+    if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+        return TRUE;
+    }
+    
+    return FALSE;
+}
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_services.c b/drivers/net/wireless/ath6kl/htc2/htc_services.c
new file mode 100644
index 000000000000..acef96e238c3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_services.c
@@ -0,0 +1,444 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.c" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
+{
+        /* not implemented
+         * we do not send control TX frames during normal runtime, only during setup  */
+    AR_DEBUG_ASSERT(FALSE);
+}
+
+    /* callback when a control message arrives on this endpoint */
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
+{
+    AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /* this is a flush operation, return the control packet back to the pool */
+        HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket);    
+        return;
+    }  
+    
+        /* the only control messages we are expecting are NULL messages (credit resports) */   
+    if (pPacket->ActualLength > 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("HTCControlRecv, got message with length:%d \n",
+                        pPacket->ActualLength + HTC_HDR_LENGTH));
+    
+            /* dump header and message */
+        DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
+                       pPacket->ActualLength + HTC_HDR_LENGTH,
+                       "Unexpected ENDPOINT 0 Message");
+    }
+
+    HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]);
+}
+
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
+{
+    HTC_PACKET             *pSendPacket = NULL;
+    A_STATUS                status;
+
+    do {
+           /* allocate a packet to send to the target */
+        pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+        if (NULL == pSendPacket) {
+            status = A_NO_MEMORY;
+            break;
+        }
+
+        if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
+            HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
+            A_UINT32                  setupFlags = 0;
+                   
+            pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
+            A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
+            pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID;   
+            if (target->MaxMsgPerBundle > 0) {
+                    /* host can do HTC bundling, indicate this to the target */
+                setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV; 
+                pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle;
+            }    
+            A_MEMCPY(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags));            
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pSetupCompleteEx,
+                                   sizeof(HTC_SETUP_COMPLETE_EX_MSG),
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+      
+        }  else {            
+            HTC_SETUP_COMPLETE_MSG *pSetupComplete;
+                /* assemble setup complete message */
+            pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
+            A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG));
+            pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;   
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pSetupComplete,
+                                   sizeof(HTC_SETUP_COMPLETE_MSG),
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+        }
+
+            /* we want synchronous operation */
+        pSendPacket->Completion = NULL;
+        HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+            /* send the message */
+        status = HTCIssueSend(target,pSendPacket);
+
+    } while (FALSE);
+
+    if (pSendPacket != NULL) {
+        HTC_FREE_CONTROL_TX(target,pSendPacket);
+    }
+
+    return status;
+}
+
+
+A_STATUS HTCConnectService(HTC_HANDLE               HTCHandle,
+                           HTC_SERVICE_CONNECT_REQ  *pConnectReq,
+                           HTC_SERVICE_CONNECT_RESP *pConnectResp)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    A_STATUS                            status = A_OK;
+    HTC_PACKET                          *pRecvPacket = NULL;
+    HTC_PACKET                          *pSendPacket = NULL;
+    HTC_CONNECT_SERVICE_RESPONSE_MSG    *pResponseMsg;
+    HTC_CONNECT_SERVICE_MSG             *pConnectMsg;
+    HTC_ENDPOINT_ID                     assignedEndpoint = ENDPOINT_MAX;
+    HTC_ENDPOINT                        *pEndpoint;
+    unsigned int                        maxMsgSize = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n",
+               (A_UINT32)target, pConnectReq->ServiceID));
+
+    do {
+
+        AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
+
+        if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
+                /* special case for pseudo control service */
+            assignedEndpoint = ENDPOINT_0;
+            maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
+        } else {
+                /* allocate a packet to send to the target */
+            pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+            if (NULL == pSendPacket) {
+                AR_DEBUG_ASSERT(FALSE);
+                status = A_NO_MEMORY;
+                break;
+            }
+                /* assemble connect service message */
+            pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
+            AR_DEBUG_ASSERT(pConnectMsg != NULL);
+            A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
+            pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
+            pConnectMsg->ServiceID = pConnectReq->ServiceID;
+            pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
+                /* check caller if it wants to transfer meta data */
+            if ((pConnectReq->pMetaData != NULL) &&
+                (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+                    /* copy meta data into message buffer (after header ) */
+                A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
+                         pConnectReq->pMetaData,
+                         pConnectReq->MetaDataLength);
+                pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
+            }
+
+            SET_HTC_PACKET_INFO_TX(pSendPacket,
+                                   NULL,
+                                   (A_UINT8 *)pConnectMsg,
+                                   sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
+                                   ENDPOINT_0,
+                                   HTC_SERVICE_TX_PACKET_TAG);
+
+                /* we want synchronous operation */
+            pSendPacket->Completion = NULL;
+            HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+            status = HTCIssueSend(target,pSendPacket);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+
+                /* wait for response */
+            status = HTCWaitforControlMessage(target, &pRecvPacket);
+
+            if (A_FAILED(status)) {
+                break;
+            }
+                /* we controlled the buffer creation so it has to be properly aligned */
+            pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
+
+            if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
+                (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
+                    /* this message is not valid */
+                AR_DEBUG_ASSERT(FALSE);
+                status = A_EPROTO;
+                break;
+            }
+
+            pConnectResp->ConnectRespCode = pResponseMsg->Status;
+                /* check response status */
+            if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    (" Target failed service 0x%X connect request (status:%d)\n",
+                                pResponseMsg->ServiceID, pResponseMsg->Status));
+                status = A_EPROTO;
+                break;
+            }
+
+            assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID;
+            maxMsgSize = pResponseMsg->MaxMsgSize;
+
+            if ((pConnectResp->pMetaData != NULL) &&
+                (pResponseMsg->ServiceMetaLength > 0) &&
+                (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+                    /* caller supplied a buffer and the target responded with data */
+                int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
+                    /* copy the meta data */
+                A_MEMCPY(pConnectResp->pMetaData,
+                         ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
+                         copyLength);
+                pConnectResp->ActualLength = copyLength;
+            }
+
+        }
+
+            /* the rest of these are parameter checks so set the error status */
+        status = A_EPROTO;
+
+        if (assignedEndpoint >= ENDPOINT_MAX) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        if (0 == maxMsgSize) {
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+        pEndpoint = &target->EndPoint[assignedEndpoint];
+        pEndpoint->Id = assignedEndpoint;
+        if (pEndpoint->ServiceID != 0) {
+            /* endpoint already in use! */
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+
+            /* return assigned endpoint to caller */
+        pConnectResp->Endpoint = assignedEndpoint;
+        pConnectResp->MaxMsgLength = maxMsgSize;
+
+            /* setup the endpoint */
+        pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
+        pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
+        pEndpoint->MaxMsgLength = maxMsgSize;
+            /* copy all the callbacks */
+        pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
+            /* set the credit distribution info for this endpoint, this information is
+             * passed back to the credit distribution callback function */
+        pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
+        pEndpoint->CreditDist.pHTCReserved = pEndpoint;
+        pEndpoint->CreditDist.Endpoint = assignedEndpoint;
+        pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
+        
+        if (pConnectReq->MaxSendMsgSize != 0) {
+                /* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications
+                 * since the host will actually issue smaller messages in the Send path */
+            if (pConnectReq->MaxSendMsgSize > maxMsgSize) {
+                    /* can't be larger than the maximum the target can support */
+                AR_DEBUG_ASSERT(FALSE);
+                break;       
+            }
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize;
+        } else {
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
+        }
+        
+        if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+            pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
+        }
+        
+            /* save local connection flags */
+        pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags;
+        
+        status = A_OK;
+
+    } while (FALSE);
+
+    if (pSendPacket != NULL) {
+        HTC_FREE_CONTROL_TX(target,pSendPacket);
+    }
+
+    if (pRecvPacket != NULL) {
+        HTC_FREE_CONTROL_RX(target,pRecvPacket);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
+
+    return status;
+}
+
+static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
+
+    if (NULL == target->EpCreditDistributionListHead) {
+        target->EpCreditDistributionListHead = pEpDist;
+        pEpDist->pNext = NULL;
+        pEpDist->pPrev = NULL;
+        return;
+    }
+
+        /* queue to the end of the list, this does not have to be very
+         * fast since this list is built at startup time */
+    pCurEntry = target->EpCreditDistributionListHead;
+
+    while (pCurEntry) {
+        pLastEntry = pCurEntry;
+        pCurEntry = pCurEntry->pNext;
+    }
+
+    pLastEntry->pNext = pEpDist;
+    pEpDist->pPrev = pLastEntry;
+    pEpDist->pNext = NULL;
+}
+
+
+
+/* default credit init callback */
+static void HTCDefaultCreditInit(void                     *Context,
+                                 HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                 int                      TotalCredits)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      totalEps = 0;
+    int                      creditsPerEndpoint;
+
+    pCurEpDist = pEPList;
+        /* first run through the list and figure out how many endpoints we are dealing with */
+    while (pCurEpDist != NULL) {
+        pCurEpDist = pCurEpDist->pNext;
+        totalEps++;
+    }
+
+        /* even distribution */
+    creditsPerEndpoint = TotalCredits/totalEps;
+
+    pCurEpDist = pEPList;
+        /* run through the list and set minimum and normal credits and
+         * provide the endpoint with some credits to start */
+    while (pCurEpDist != NULL) {
+
+        if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
+                /* too many endpoints and not enough credits */
+            AR_DEBUG_ASSERT(FALSE);
+            break;
+        }
+            /* our minimum is set for at least 1 max message */
+        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+            /* this value is ignored by our credit alg, since we do
+             * not dynamically adjust credits, this is the policy of
+             * the "default" credit distribution, something simple and easy */
+        pCurEpDist->TxCreditsNorm = 0xFFFF;
+            /* give the endpoint minimum credits */
+        pCurEpDist->TxCredits = creditsPerEndpoint;
+        pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+/* default credit distribution callback, NOTE, this callback holds the TX lock */
+void HTCDefaultCreditDist(void                     *Context,
+                          HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+                          HTC_CREDIT_DIST_REASON   Reason)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+
+    if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
+        pCurEpDist = pEPDistList;
+            /* simple distribution */
+        while (pCurEpDist != NULL) {
+            if (pCurEpDist->TxCreditsToDist > 0) {
+                    /* just give the endpoint back the credits */
+                pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+                pCurEpDist->TxCreditsToDist = 0;
+            }
+            pCurEpDist = pCurEpDist->pNext;
+        }
+    }
+
+    /* note we do not need to handle the other reason codes as this is a very
+     * simple distribution scheme, no need to seek for more credits or handle inactivity */
+}
+
+void HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
+                              void                     *pCreditDistContext,
+                              HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+                              HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+                              HTC_SERVICE_ID           ServicePriorityOrder[],
+                              int                      ListLength)
+{
+    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+    int i;
+    int ep;
+
+    if (CreditInitFunc != NULL) {
+            /* caller has supplied their own distribution functions */
+        target->InitCredits = CreditInitFunc;
+        AR_DEBUG_ASSERT(CreditDistFunc != NULL);
+        target->DistributeCredits = CreditDistFunc;
+        target->pCredDistContext = pCreditDistContext;
+    } else {
+        /* caller wants HTC to do distribution */
+        /* if caller wants service to handle distributions then
+         * it must set both of these to NULL! */
+        AR_DEBUG_ASSERT(CreditDistFunc == NULL);
+        target->InitCredits = HTCDefaultCreditInit;
+        target->DistributeCredits = HTCDefaultCreditDist;
+        target->pCredDistContext = target;
+    }
+
+        /* always add HTC control endpoint first, we only expose the list after the
+         * first one, this is added for TX queue checking */
+    AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
+
+        /* build the list of credit distribution structures in priority order
+         * supplied by the caller, these will follow endpoint 0 */
+    for (i = 0; i < ListLength; i++) {
+            /* match services with endpoints and add the endpoints to the distribution list
+             * in FIFO order */
+        for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
+            if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
+                    /* queue this one to the list */
+                AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
+                break;
+            }
+        }
+        AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
+    }
+
+}
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h
new file mode 100644
index 000000000000..9e071548ed92
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h
@@ -0,0 +1,57 @@
+//------------------------------------------------------------------------------
+// <copyright file="AR6002_regdump.h" company="Atheros">
+//    Copyright (c) 2006 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __AR6002_REGDUMP_H__
+#define __AR6002_REGDUMP_H__
+
+#if !defined(__ASSEMBLER__)
+/*
+ * XTensa CPU state
+ * This must match the state saved by the target exception handler.
+ */
+struct XTensa_exception_frame_s {
+    A_UINT32 xt_pc;
+    A_UINT32 xt_ps;
+    A_UINT32 xt_sar;
+    A_UINT32 xt_vpri;
+    A_UINT32 xt_a2;
+    A_UINT32 xt_a3;
+    A_UINT32 xt_a4;
+    A_UINT32 xt_a5;
+    A_UINT32 xt_exccause;
+    A_UINT32 xt_lcount;
+    A_UINT32 xt_lbeg;
+    A_UINT32 xt_lend;
+
+    A_UINT32 epc1, epc2, epc3, epc4;
+
+    /* Extra info to simplify post-mortem stack walkback */
+#define AR6002_REGDUMP_FRAMES 10
+    struct {
+        A_UINT32 a0;  /* pc */
+        A_UINT32 a1;  /* sp */
+        A_UINT32 a2;
+        A_UINT32 a3;
+    } wb[AR6002_REGDUMP_FRAMES];
+};
+typedef struct XTensa_exception_frame_s CPU_exception_frame_t; 
+#define RD_SIZE sizeof(CPU_exception_frame_t)
+
+#endif
+#endif /* __AR6002_REGDUMP_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h
new file mode 100644
index 000000000000..ca45848c3caa
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h
@@ -0,0 +1,47 @@
+//------------------------------------------------------------------------------
+// <copyright file="AR6K_version.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#define __VER_MAJOR_ 3
+#define __VER_MINOR_ 0 
+#define __VER_PATCH_ 0
+
+/* The makear6ksdk script (used for release builds) modifies the following line. */
+#define __BUILD_NUMBER_ 1057
+
+
+/* Format of the version number. */
+#define VER_MAJOR_BIT_OFFSET        28
+#define VER_MINOR_BIT_OFFSET        24
+#define VER_PATCH_BIT_OFFSET        16
+#define VER_BUILD_NUM_BIT_OFFSET    0
+
+
+/*
+ * The version has the following format:
+ * Bits 28-31: Major version
+ * Bits 24-27: Minor version
+ * Bits 16-23: Patch version
+ * Bits 0-15:  Build number (automatically generated during build process )
+ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
+ *
+ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
+ */
+#define AR6K_SW_VERSION     ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/addrs.h b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h
new file mode 100644
index 000000000000..bbb647fb942a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h
@@ -0,0 +1,86 @@
+//------------------------------------------------------------------------------
+// <copyright file="addrs.h" company="Atheros">
+//    Copyright (c) 2004-2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __ADDRS_H__
+#define __ADDRS_H__
+
+/*
+ * Special AR6002 Addresses that may be needed by special
+ * applications (e.g. ART) on the Host as well as Target.
+ */
+
+#if defined(AR6002_REV2)
+#define AR6K_RAM_START 0x00500000
+#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
+#define TARG_RAM_SZ (184*1024)
+#define TARG_ROM_SZ (80*1024)
+#endif
+#if defined(AR6002_REV4) || defined(AR6003)
+#define AR6K_RAM_START 0x00540000
+#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
+#define TARG_RAM_SZ (256*1024)
+#define TARG_ROM_SZ (256*1024)
+#endif
+
+#define AR6002_BOARD_DATA_SZ 768
+#define AR6003_BOARD_DATA_SZ 1024
+
+#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
+#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
+
+#define AR6K_ROM_START 0x004e0000
+#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
+#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
+#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
+
+/*
+ * At this ROM address is a pointer to the start of the ROM DataSet Index.
+ * If there are no ROM DataSets, there's a 0 at this address.
+ */
+#define ROM_DATASET_INDEX_ADDR          (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
+#define ROM_MBIST_CKSUM_ADDR            (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
+
+/*
+ * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
+ * board data.
+ */
+
+/* Size of Board Data, in bytes */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ
+#else
+#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
+#endif
+
+
+/*
+ * Constants used by ASM code to access fields of host_interest_s,
+ * which is at a fixed location in RAM.
+ */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR  (AR6K_RAM_START + 0x60c)
+#else
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR  (AR6K_RAM_START + 0x40c)
+#endif
+#define FLASH_IS_PRESENT_TARGADDR       HOST_INTEREST_FLASH_IS_PRESENT_ADDR
+
+#endif /* __ADDRS_H__ */
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..28b972afc8d7
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h
@@ -0,0 +1,83 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_INTF_REG_REG_H_
+#define _ANALOG_INTF_REG_REG_H_
+
+#define SW_OVERRIDE_ADDRESS                      0x00000080
+#define SW_OVERRIDE_OFFSET                       0x00000080
+#define SW_OVERRIDE_SUPDATE_DELAY_MSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_LSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_MASK           0x00000002
+#define SW_OVERRIDE_SUPDATE_DELAY_GET(x)         (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
+#define SW_OVERRIDE_SUPDATE_DELAY_SET(x)         (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
+#define SW_OVERRIDE_ENABLE_MSB                   0
+#define SW_OVERRIDE_ENABLE_LSB                   0
+#define SW_OVERRIDE_ENABLE_MASK                  0x00000001
+#define SW_OVERRIDE_ENABLE_GET(x)                (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
+#define SW_OVERRIDE_ENABLE_SET(x)                (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
+
+#define SIN_VAL_ADDRESS                          0x00000084
+#define SIN_VAL_OFFSET                           0x00000084
+#define SIN_VAL_SIN_MSB                          0
+#define SIN_VAL_SIN_LSB                          0
+#define SIN_VAL_SIN_MASK                         0x00000001
+#define SIN_VAL_SIN_GET(x)                       (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
+#define SIN_VAL_SIN_SET(x)                       (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
+
+#define SW_SCLK_ADDRESS                          0x00000088
+#define SW_SCLK_OFFSET                           0x00000088
+#define SW_SCLK_SW_SCLK_MSB                      0
+#define SW_SCLK_SW_SCLK_LSB                      0
+#define SW_SCLK_SW_SCLK_MASK                     0x00000001
+#define SW_SCLK_SW_SCLK_GET(x)                   (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
+#define SW_SCLK_SW_SCLK_SET(x)                   (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
+
+#define SW_CNTL_ADDRESS                          0x0000008c
+#define SW_CNTL_OFFSET                           0x0000008c
+#define SW_CNTL_SW_SCAPTURE_MSB                  2
+#define SW_CNTL_SW_SCAPTURE_LSB                  2
+#define SW_CNTL_SW_SCAPTURE_MASK                 0x00000004
+#define SW_CNTL_SW_SCAPTURE_GET(x)               (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
+#define SW_CNTL_SW_SCAPTURE_SET(x)               (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
+#define SW_CNTL_SW_SUPDATE_MSB                   1
+#define SW_CNTL_SW_SUPDATE_LSB                   1
+#define SW_CNTL_SW_SUPDATE_MASK                  0x00000002
+#define SW_CNTL_SW_SUPDATE_GET(x)                (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
+#define SW_CNTL_SW_SUPDATE_SET(x)                (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
+#define SW_CNTL_SW_SOUT_MSB                      0
+#define SW_CNTL_SW_SOUT_LSB                      0
+#define SW_CNTL_SW_SOUT_MASK                     0x00000001
+#define SW_CNTL_SW_SOUT_GET(x)                   (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
+#define SW_CNTL_SW_SOUT_SET(x)                   (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_reg_reg_s {
+  unsigned char pad0[128]; /* pad to 0x80 */
+  volatile unsigned int sw_override;
+  volatile unsigned int sin_val;
+  volatile unsigned int sw_sclk;
+  volatile unsigned int sw_cntl;
+} analog_intf_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h
new file mode 100644
index 000000000000..c485ac725c2f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h
@@ -0,0 +1,1951 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_REG_REG_H_
+#define _ANALOG_REG_REG_H_
+
+#define SYNTH_SYNTH1_ADDRESS                     0x00000000
+#define SYNTH_SYNTH1_OFFSET                      0x00000000
+#define SYNTH_SYNTH1_PWD_BIAS_MSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_LSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_MASK               0x80000000
+#define SYNTH_SYNTH1_PWD_BIAS_GET(x)             (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
+#define SYNTH_SYNTH1_PWD_BIAS_SET(x)             (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
+#define SYNTH_SYNTH1_PWD_CP_MSB                  30
+#define SYNTH_SYNTH1_PWD_CP_LSB                  30
+#define SYNTH_SYNTH1_PWD_CP_MASK                 0x40000000
+#define SYNTH_SYNTH1_PWD_CP_GET(x)               (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
+#define SYNTH_SYNTH1_PWD_CP_SET(x)               (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
+#define SYNTH_SYNTH1_PWD_VCMON_MSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_LSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_MASK              0x20000000
+#define SYNTH_SYNTH1_PWD_VCMON_GET(x)            (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
+#define SYNTH_SYNTH1_PWD_VCMON_SET(x)            (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
+#define SYNTH_SYNTH1_PWD_VCO_MSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_LSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_MASK                0x10000000
+#define SYNTH_SYNTH1_PWD_VCO_GET(x)              (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
+#define SYNTH_SYNTH1_PWD_VCO_SET(x)              (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
+#define SYNTH_SYNTH1_PWD_PRESC_MSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_LSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_MASK              0x08000000
+#define SYNTH_SYNTH1_PWD_PRESC_GET(x)            (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
+#define SYNTH_SYNTH1_PWD_PRESC_SET(x)            (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
+#define SYNTH_SYNTH1_PWD_LODIV_MSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_LSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_MASK              0x04000000
+#define SYNTH_SYNTH1_PWD_LODIV_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
+#define SYNTH_SYNTH1_PWD_LODIV_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
+#define SYNTH_SYNTH1_PWD_LOMIX_MSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_LSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_MASK              0x02000000
+#define SYNTH_SYNTH1_PWD_LOMIX_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
+#define SYNTH_SYNTH1_PWD_LOMIX_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
+#define SYNTH_SYNTH1_FORCE_LO_ON_MSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_LSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_MASK            0x01000000
+#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x)          (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
+#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x)          (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK            0x00800000
+#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x)          (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x)          (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
+#define SYNTH_SYNTH1_VCOREGBYPASS_MSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_LSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_MASK           0x00400000
+#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x)         (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
+#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x)         (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
+#define SYNTH_SYNTH1_VCOREGLEVEL_MSB             21
+#define SYNTH_SYNTH1_VCOREGLEVEL_LSB             20
+#define SYNTH_SYNTH1_VCOREGLEVEL_MASK            0x00300000
+#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x)          (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
+#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x)          (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
+#define SYNTH_SYNTH1_VCOREGBIAS_MSB              19
+#define SYNTH_SYNTH1_VCOREGBIAS_LSB              18
+#define SYNTH_SYNTH1_VCOREGBIAS_MASK             0x000c0000
+#define SYNTH_SYNTH1_VCOREGBIAS_GET(x)           (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
+#define SYNTH_SYNTH1_VCOREGBIAS_SET(x)           (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
+#define SYNTH_SYNTH1_SLIDINGIF_MSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_LSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_MASK              0x00020000
+#define SYNTH_SYNTH1_SLIDINGIF_GET(x)            (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
+#define SYNTH_SYNTH1_SLIDINGIF_SET(x)            (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
+#define SYNTH_SYNTH1_SPARE_PWD_MSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_LSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_MASK              0x00010000
+#define SYNTH_SYNTH1_SPARE_PWD_GET(x)            (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
+#define SYNTH_SYNTH1_SPARE_PWD_SET(x)            (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK          0x00008000
+#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x)        (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x)        (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOREG_MSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_LSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_MASK            0x00004000
+#define SYNTH_SYNTH1_CON_IVCOREG_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_IVCOREG_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOBUF_MSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_LSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_MASK            0x00002000
+#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
+#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB           12
+#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB           10
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK          0x00001c00
+#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x)        (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x)        (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK         0x00000200
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x)       (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x)       (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK          0x00000100
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK          0x00000080
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK        0x00000040
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x)      (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x)      (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_MSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_LSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_MASK             0x00000020
+#define SYNTH_SYNTH1_MONITOR_FB_GET(x)           (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_SET(x)           (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
+#define SYNTH_SYNTH1_MONITOR_REF_MSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_LSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_MASK            0x00000010
+#define SYNTH_SYNTH1_MONITOR_REF_GET(x)          (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
+#define SYNTH_SYNTH1_MONITOR_REF_SET(x)          (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK        0x00000008
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK        0x00000004
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK         0x00000002
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x)       (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x)       (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK  0x00000001
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
+
+#define SYNTH_SYNTH2_ADDRESS                     0x00000004
+#define SYNTH_SYNTH2_OFFSET                      0x00000004
+#define SYNTH_SYNTH2_VC_CAL_REF_MSB              31
+#define SYNTH_SYNTH2_VC_CAL_REF_LSB              29
+#define SYNTH_SYNTH2_VC_CAL_REF_MASK             0xe0000000
+#define SYNTH_SYNTH2_VC_CAL_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
+#define SYNTH_SYNTH2_VC_CAL_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
+#define SYNTH_SYNTH2_VC_HI_REF_MSB               28
+#define SYNTH_SYNTH2_VC_HI_REF_LSB               26
+#define SYNTH_SYNTH2_VC_HI_REF_MASK              0x1c000000
+#define SYNTH_SYNTH2_VC_HI_REF_GET(x)            (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
+#define SYNTH_SYNTH2_VC_HI_REF_SET(x)            (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
+#define SYNTH_SYNTH2_VC_MID_REF_MSB              25
+#define SYNTH_SYNTH2_VC_MID_REF_LSB              23
+#define SYNTH_SYNTH2_VC_MID_REF_MASK             0x03800000
+#define SYNTH_SYNTH2_VC_MID_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
+#define SYNTH_SYNTH2_VC_MID_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
+#define SYNTH_SYNTH2_VC_LOW_REF_MSB              22
+#define SYNTH_SYNTH2_VC_LOW_REF_LSB              20
+#define SYNTH_SYNTH2_VC_LOW_REF_MASK             0x00700000
+#define SYNTH_SYNTH2_VC_LOW_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
+#define SYNTH_SYNTH2_VC_LOW_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB        19
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB        15
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK       0x000f8000
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x)     (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x)     (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
+#define SYNTH_SYNTH2_LOOP_CP_MSB                 14
+#define SYNTH_SYNTH2_LOOP_CP_LSB                 10
+#define SYNTH_SYNTH2_LOOP_CP_MASK                0x00007c00
+#define SYNTH_SYNTH2_LOOP_CP_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
+#define SYNTH_SYNTH2_LOOP_CP_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
+#define SYNTH_SYNTH2_LOOP_RS_MSB                 9
+#define SYNTH_SYNTH2_LOOP_RS_LSB                 5
+#define SYNTH_SYNTH2_LOOP_RS_MASK                0x000003e0
+#define SYNTH_SYNTH2_LOOP_RS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
+#define SYNTH_SYNTH2_LOOP_RS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
+#define SYNTH_SYNTH2_LOOP_CS_MSB                 4
+#define SYNTH_SYNTH2_LOOP_CS_LSB                 3
+#define SYNTH_SYNTH2_LOOP_CS_MASK                0x00000018
+#define SYNTH_SYNTH2_LOOP_CS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
+#define SYNTH_SYNTH2_LOOP_CS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
+#define SYNTH_SYNTH2_SPARE_BITS_MSB              2
+#define SYNTH_SYNTH2_SPARE_BITS_LSB              0
+#define SYNTH_SYNTH2_SPARE_BITS_MASK             0x00000007
+#define SYNTH_SYNTH2_SPARE_BITS_GET(x)           (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
+#define SYNTH_SYNTH2_SPARE_BITS_SET(x)           (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
+
+#define SYNTH_SYNTH3_ADDRESS                     0x00000008
+#define SYNTH_SYNTH3_OFFSET                      0x00000008
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK           0x80000000
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x)         (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x)         (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK           0x40000000
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x)         (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x)         (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB       29
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB       24
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK      0x3f000000
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)    (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)    (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_PWRUP_MSB              23
+#define SYNTH_SYNTH3_WAIT_PWRUP_LSB              18
+#define SYNTH_SYNTH3_WAIT_PWRUP_MASK             0x00fc0000
+#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x)           (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x)           (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB            17
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB            12
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK           0x0003f000
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB            11
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB            6
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK           0x00000fc0
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB           5
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB           0
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK          0x0000003f
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x)        (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x)        (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
+
+#define SYNTH_SYNTH4_ADDRESS                     0x0000000c
+#define SYNTH_SYNTH4_OFFSET                      0x0000000c
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK      0x80000000
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)    (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)    (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
+#define SYNTH_SYNTH4_DIS_LOSTVC_MSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_LSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_MASK             0x40000000
+#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x)           (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
+#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x)           (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK          0x20000000
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x)        (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x)        (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK    0x10000000
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)  (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)  (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
+#define SYNTH_SYNTH4_FORCE_PINVC_MSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_LSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_MASK            0x08000000
+#define SYNTH_SYNTH4_FORCE_PINVC_GET(x)          (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
+#define SYNTH_SYNTH4_FORCE_PINVC_SET(x)          (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK           0x04000000
+#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x)         (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x)         (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
+#define SYNTH_SYNTH4_VCOCAP_OVR_MSB              25
+#define SYNTH_SYNTH4_VCOCAP_OVR_LSB              18
+#define SYNTH_SYNTH4_VCOCAP_OVR_MASK             0x03fc0000
+#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x)           (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
+#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x)           (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK           0x00020000
+#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x)         (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x)         (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
+#define SYNTH_SYNTH4_REFDIVSEL_MSB               16
+#define SYNTH_SYNTH4_REFDIVSEL_LSB               15
+#define SYNTH_SYNTH4_REFDIVSEL_MASK              0x00018000
+#define SYNTH_SYNTH4_REFDIVSEL_GET(x)            (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
+#define SYNTH_SYNTH4_REFDIVSEL_SET(x)            (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
+#define SYNTH_SYNTH4_PFDDELAY_MSB                14
+#define SYNTH_SYNTH4_PFDDELAY_LSB                14
+#define SYNTH_SYNTH4_PFDDELAY_MASK               0x00004000
+#define SYNTH_SYNTH4_PFDDELAY_GET(x)             (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
+#define SYNTH_SYNTH4_PFDDELAY_SET(x)             (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
+#define SYNTH_SYNTH4_PFD_DISABLE_MSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_LSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_MASK            0x00002000
+#define SYNTH_SYNTH4_PFD_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
+#define SYNTH_SYNTH4_PFD_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
+#define SYNTH_SYNTH4_PRESCSEL_MSB                12
+#define SYNTH_SYNTH4_PRESCSEL_LSB                11
+#define SYNTH_SYNTH4_PRESCSEL_MASK               0x00001800
+#define SYNTH_SYNTH4_PRESCSEL_GET(x)             (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
+#define SYNTH_SYNTH4_PRESCSEL_SET(x)             (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
+#define SYNTH_SYNTH4_RESET_PRESC_MSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_LSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_MASK            0x00000400
+#define SYNTH_SYNTH4_RESET_PRESC_GET(x)          (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
+#define SYNTH_SYNTH4_RESET_PRESC_SET(x)          (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
+#define SYNTH_SYNTH4_SDM_DISABLE_MSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_LSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_MASK            0x00000200
+#define SYNTH_SYNTH4_SDM_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
+#define SYNTH_SYNTH4_SDM_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
+#define SYNTH_SYNTH4_SDM_MODE_MSB                8
+#define SYNTH_SYNTH4_SDM_MODE_LSB                8
+#define SYNTH_SYNTH4_SDM_MODE_MASK               0x00000100
+#define SYNTH_SYNTH4_SDM_MODE_GET(x)             (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
+#define SYNTH_SYNTH4_SDM_MODE_SET(x)             (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
+#define SYNTH_SYNTH4_SDM_DITHER_MSB              7
+#define SYNTH_SYNTH4_SDM_DITHER_LSB              6
+#define SYNTH_SYNTH4_SDM_DITHER_MASK             0x000000c0
+#define SYNTH_SYNTH4_SDM_DITHER_GET(x)           (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
+#define SYNTH_SYNTH4_SDM_DITHER_SET(x)           (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK          0x00000020
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x)        (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x)        (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK       0x00000010
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x)     (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x)     (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
+#define SYNTH_SYNTH4_SPARE_MISC_MSB              3
+#define SYNTH_SYNTH4_SPARE_MISC_LSB              2
+#define SYNTH_SYNTH4_SPARE_MISC_MASK             0x0000000c
+#define SYNTH_SYNTH4_SPARE_MISC_GET(x)           (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
+#define SYNTH_SYNTH4_SPARE_MISC_SET(x)           (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK           0x00000002
+#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x)         (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x)         (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK         0x00000001
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x)       (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x)       (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
+
+#define SYNTH_SYNTH5_ADDRESS                     0x00000010
+#define SYNTH_SYNTH5_OFFSET                      0x00000010
+#define SYNTH_SYNTH5_LOOP_IP0_MSB                31
+#define SYNTH_SYNTH5_LOOP_IP0_LSB                28
+#define SYNTH_SYNTH5_LOOP_IP0_MASK               0xf0000000
+#define SYNTH_SYNTH5_LOOP_IP0_GET(x)             (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
+#define SYNTH_SYNTH5_LOOP_IP0_SET(x)             (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
+#define SYNTH_SYNTH5_SLOPE_IP_MSB                27
+#define SYNTH_SYNTH5_SLOPE_IP_LSB                25
+#define SYNTH_SYNTH5_SLOPE_IP_MASK               0x0e000000
+#define SYNTH_SYNTH5_SLOPE_IP_GET(x)             (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
+#define SYNTH_SYNTH5_SLOPE_IP_SET(x)             (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
+#define SYNTH_SYNTH5_CPBIAS_MSB                  24
+#define SYNTH_SYNTH5_CPBIAS_LSB                  23
+#define SYNTH_SYNTH5_CPBIAS_MASK                 0x01800000
+#define SYNTH_SYNTH5_CPBIAS_GET(x)               (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
+#define SYNTH_SYNTH5_CPBIAS_SET(x)               (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
+#define SYNTH_SYNTH5_CPSTEERING_EN_MSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_LSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_MASK          0x00400000
+#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x)        (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
+#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x)        (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
+#define SYNTH_SYNTH5_CPLOWLK_MSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_LSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_MASK                0x00200000
+#define SYNTH_SYNTH5_CPLOWLK_GET(x)              (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
+#define SYNTH_SYNTH5_CPLOWLK_SET(x)              (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB             20
+#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB             17
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK            0x001e0000
+#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x)          (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x)          (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
+#define SYNTH_SYNTH5_CAPRANGE1_MSB               16
+#define SYNTH_SYNTH5_CAPRANGE1_LSB               13
+#define SYNTH_SYNTH5_CAPRANGE1_MASK              0x0001e000
+#define SYNTH_SYNTH5_CAPRANGE1_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
+#define SYNTH_SYNTH5_CAPRANGE1_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
+#define SYNTH_SYNTH5_CAPRANGE2_MSB               12
+#define SYNTH_SYNTH5_CAPRANGE2_LSB               9
+#define SYNTH_SYNTH5_CAPRANGE2_MASK              0x00001e00
+#define SYNTH_SYNTH5_CAPRANGE2_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
+#define SYNTH_SYNTH5_CAPRANGE2_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
+#define SYNTH_SYNTH5_CAPRANGE3_MSB               8
+#define SYNTH_SYNTH5_CAPRANGE3_LSB               5
+#define SYNTH_SYNTH5_CAPRANGE3_MASK              0x000001e0
+#define SYNTH_SYNTH5_CAPRANGE3_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
+#define SYNTH_SYNTH5_CAPRANGE3_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK      0x00000010
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x)    (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x)    (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB         3
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB         2
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK        0x0000000c
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x)      (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x)      (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
+#define SYNTH_SYNTH5_SPARE_MSB                   1
+#define SYNTH_SYNTH5_SPARE_LSB                   0
+#define SYNTH_SYNTH5_SPARE_MASK                  0x00000003
+#define SYNTH_SYNTH5_SPARE_GET(x)                (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
+#define SYNTH_SYNTH5_SPARE_SET(x)                (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
+
+#define SYNTH_SYNTH6_ADDRESS                     0x00000014
+#define SYNTH_SYNTH6_OFFSET                      0x00000014
+#define SYNTH_SYNTH6_IRCP_MSB                    31
+#define SYNTH_SYNTH6_IRCP_LSB                    29
+#define SYNTH_SYNTH6_IRCP_MASK                   0xe0000000
+#define SYNTH_SYNTH6_IRCP_GET(x)                 (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
+#define SYNTH_SYNTH6_IRCP_SET(x)                 (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
+#define SYNTH_SYNTH6_IRVCMON_MSB                 28
+#define SYNTH_SYNTH6_IRVCMON_LSB                 26
+#define SYNTH_SYNTH6_IRVCMON_MASK                0x1c000000
+#define SYNTH_SYNTH6_IRVCMON_GET(x)              (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
+#define SYNTH_SYNTH6_IRVCMON_SET(x)              (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
+#define SYNTH_SYNTH6_IRSPARE_MSB                 25
+#define SYNTH_SYNTH6_IRSPARE_LSB                 23
+#define SYNTH_SYNTH6_IRSPARE_MASK                0x03800000
+#define SYNTH_SYNTH6_IRSPARE_GET(x)              (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
+#define SYNTH_SYNTH6_IRSPARE_SET(x)              (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
+#define SYNTH_SYNTH6_ICPRESC_MSB                 22
+#define SYNTH_SYNTH6_ICPRESC_LSB                 20
+#define SYNTH_SYNTH6_ICPRESC_MASK                0x00700000
+#define SYNTH_SYNTH6_ICPRESC_GET(x)              (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
+#define SYNTH_SYNTH6_ICPRESC_SET(x)              (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
+#define SYNTH_SYNTH6_ICLODIV_MSB                 19
+#define SYNTH_SYNTH6_ICLODIV_LSB                 17
+#define SYNTH_SYNTH6_ICLODIV_MASK                0x000e0000
+#define SYNTH_SYNTH6_ICLODIV_GET(x)              (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
+#define SYNTH_SYNTH6_ICLODIV_SET(x)              (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
+#define SYNTH_SYNTH6_ICLOMIX_MSB                 16
+#define SYNTH_SYNTH6_ICLOMIX_LSB                 14
+#define SYNTH_SYNTH6_ICLOMIX_MASK                0x0001c000
+#define SYNTH_SYNTH6_ICLOMIX_GET(x)              (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
+#define SYNTH_SYNTH6_ICLOMIX_SET(x)              (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
+#define SYNTH_SYNTH6_ICSPAREA_MSB                13
+#define SYNTH_SYNTH6_ICSPAREA_LSB                11
+#define SYNTH_SYNTH6_ICSPAREA_MASK               0x00003800
+#define SYNTH_SYNTH6_ICSPAREA_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
+#define SYNTH_SYNTH6_ICSPAREA_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
+#define SYNTH_SYNTH6_ICSPAREB_MSB                10
+#define SYNTH_SYNTH6_ICSPAREB_LSB                8
+#define SYNTH_SYNTH6_ICSPAREB_MASK               0x00000700
+#define SYNTH_SYNTH6_ICSPAREB_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
+#define SYNTH_SYNTH6_ICSPAREB_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
+#define SYNTH_SYNTH6_ICVCO_MSB                   7
+#define SYNTH_SYNTH6_ICVCO_LSB                   5
+#define SYNTH_SYNTH6_ICVCO_MASK                  0x000000e0
+#define SYNTH_SYNTH6_ICVCO_GET(x)                (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
+#define SYNTH_SYNTH6_ICVCO_SET(x)                (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
+#define SYNTH_SYNTH6_VCOBUFBIAS_MSB              4
+#define SYNTH_SYNTH6_VCOBUFBIAS_LSB              3
+#define SYNTH_SYNTH6_VCOBUFBIAS_MASK             0x00000018
+#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x)           (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
+#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x)           (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
+#define SYNTH_SYNTH6_SPARE_BIAS_MSB              2
+#define SYNTH_SYNTH6_SPARE_BIAS_LSB              0
+#define SYNTH_SYNTH6_SPARE_BIAS_MASK             0x00000007
+#define SYNTH_SYNTH6_SPARE_BIAS_GET(x)           (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
+#define SYNTH_SYNTH6_SPARE_BIAS_SET(x)           (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
+
+#define SYNTH_SYNTH7_ADDRESS                     0x00000018
+#define SYNTH_SYNTH7_OFFSET                      0x00000018
+#define SYNTH_SYNTH7_SYNTH_ON_MSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_LSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_MASK               0x80000000
+#define SYNTH_SYNTH7_SYNTH_ON_GET(x)             (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
+#define SYNTH_SYNTH7_SYNTH_ON_SET(x)             (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB          30
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB          27
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK         0x78000000
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x)       (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x)       (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
+#define SYNTH_SYNTH7_CAP_SEARCH_MSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_LSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_MASK             0x04000000
+#define SYNTH_SYNTH7_CAP_SEARCH_GET(x)           (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
+#define SYNTH_SYNTH7_CAP_SEARCH_SET(x)           (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK       0x02000000
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x)     (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x)     (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
+#define SYNTH_SYNTH7_PIN_VC_MSB                  24
+#define SYNTH_SYNTH7_PIN_VC_LSB                  24
+#define SYNTH_SYNTH7_PIN_VC_MASK                 0x01000000
+#define SYNTH_SYNTH7_PIN_VC_GET(x)               (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
+#define SYNTH_SYNTH7_PIN_VC_SET(x)               (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
+#define SYNTH_SYNTH7_VCO_CAP_ST_MSB              23
+#define SYNTH_SYNTH7_VCO_CAP_ST_LSB              16
+#define SYNTH_SYNTH7_VCO_CAP_ST_MASK             0x00ff0000
+#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x)           (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
+#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x)           (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
+#define SYNTH_SYNTH7_SHORT_R_MSB                 15
+#define SYNTH_SYNTH7_SHORT_R_LSB                 15
+#define SYNTH_SYNTH7_SHORT_R_MASK                0x00008000
+#define SYNTH_SYNTH7_SHORT_R_GET(x)              (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
+#define SYNTH_SYNTH7_SHORT_R_SET(x)              (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
+#define SYNTH_SYNTH7_RESET_RFD_MSB               14
+#define SYNTH_SYNTH7_RESET_RFD_LSB               14
+#define SYNTH_SYNTH7_RESET_RFD_MASK              0x00004000
+#define SYNTH_SYNTH7_RESET_RFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
+#define SYNTH_SYNTH7_RESET_RFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
+#define SYNTH_SYNTH7_RESET_PFD_MSB               13
+#define SYNTH_SYNTH7_RESET_PFD_LSB               13
+#define SYNTH_SYNTH7_RESET_PFD_MASK              0x00002000
+#define SYNTH_SYNTH7_RESET_PFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
+#define SYNTH_SYNTH7_RESET_PFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK       0x00001000
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x)     (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x)     (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
+#define SYNTH_SYNTH7_RESET_SDM_B_MSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_LSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_MASK            0x00000800
+#define SYNTH_SYNTH7_RESET_SDM_B_GET(x)          (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
+#define SYNTH_SYNTH7_RESET_SDM_B_SET(x)          (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
+#define SYNTH_SYNTH7_VC2HIGH_MSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_LSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_MASK                0x00000400
+#define SYNTH_SYNTH7_VC2HIGH_GET(x)              (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
+#define SYNTH_SYNTH7_VC2HIGH_SET(x)              (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
+#define SYNTH_SYNTH7_VC2LOW_MSB                  9
+#define SYNTH_SYNTH7_VC2LOW_LSB                  9
+#define SYNTH_SYNTH7_VC2LOW_MASK                 0x00000200
+#define SYNTH_SYNTH7_VC2LOW_GET(x)               (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
+#define SYNTH_SYNTH7_VC2LOW_SET(x)               (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
+#define SYNTH_SYNTH7_LOOP_IP_MSB                 8
+#define SYNTH_SYNTH7_LOOP_IP_LSB                 5
+#define SYNTH_SYNTH7_LOOP_IP_MASK                0x000001e0
+#define SYNTH_SYNTH7_LOOP_IP_GET(x)              (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
+#define SYNTH_SYNTH7_LOOP_IP_SET(x)              (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB             4
+#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB             3
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK            0x00000018
+#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x)          (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x)          (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH7_SPARE_READ_MSB              2
+#define SYNTH_SYNTH7_SPARE_READ_LSB              0
+#define SYNTH_SYNTH7_SPARE_READ_MASK             0x00000007
+#define SYNTH_SYNTH7_SPARE_READ_GET(x)           (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
+#define SYNTH_SYNTH7_SPARE_READ_SET(x)           (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
+
+#define SYNTH_SYNTH8_ADDRESS                     0x0000001c
+#define SYNTH_SYNTH8_OFFSET                      0x0000001c
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK       0x80000000
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x)     (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x)     (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
+#define SYNTH_SYNTH8_FRACMODE_MSB                30
+#define SYNTH_SYNTH8_FRACMODE_LSB                30
+#define SYNTH_SYNTH8_FRACMODE_MASK               0x40000000
+#define SYNTH_SYNTH8_FRACMODE_GET(x)             (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
+#define SYNTH_SYNTH8_FRACMODE_SET(x)             (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
+#define SYNTH_SYNTH8_AMODEREFSEL_MSB             29
+#define SYNTH_SYNTH8_AMODEREFSEL_LSB             28
+#define SYNTH_SYNTH8_AMODEREFSEL_MASK            0x30000000
+#define SYNTH_SYNTH8_AMODEREFSEL_GET(x)          (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
+#define SYNTH_SYNTH8_AMODEREFSEL_SET(x)          (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
+#define SYNTH_SYNTH8_SPARE_MSB                   27
+#define SYNTH_SYNTH8_SPARE_LSB                   27
+#define SYNTH_SYNTH8_SPARE_MASK                  0x08000000
+#define SYNTH_SYNTH8_SPARE_GET(x)                (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
+#define SYNTH_SYNTH8_SPARE_SET(x)                (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
+#define SYNTH_SYNTH8_CHANSEL_MSB                 26
+#define SYNTH_SYNTH8_CHANSEL_LSB                 18
+#define SYNTH_SYNTH8_CHANSEL_MASK                0x07fc0000
+#define SYNTH_SYNTH8_CHANSEL_GET(x)              (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
+#define SYNTH_SYNTH8_CHANSEL_SET(x)              (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
+#define SYNTH_SYNTH8_CHANFRAC_MSB                17
+#define SYNTH_SYNTH8_CHANFRAC_LSB                1
+#define SYNTH_SYNTH8_CHANFRAC_MASK               0x0003fffe
+#define SYNTH_SYNTH8_CHANFRAC_GET(x)             (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
+#define SYNTH_SYNTH8_CHANFRAC_SET(x)             (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK          0x00000001
+#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x)        (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x)        (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
+
+#define RF5G_RF5G1_ADDRESS                       0x00000020
+#define RF5G_RF5G1_OFFSET                        0x00000020
+#define RF5G_RF5G1_PDTXLO5_MSB                   31
+#define RF5G_RF5G1_PDTXLO5_LSB                   31
+#define RF5G_RF5G1_PDTXLO5_MASK                  0x80000000
+#define RF5G_RF5G1_PDTXLO5_GET(x)                (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
+#define RF5G_RF5G1_PDTXLO5_SET(x)                (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
+#define RF5G_RF5G1_PDTXMIX5_MSB                  30
+#define RF5G_RF5G1_PDTXMIX5_LSB                  30
+#define RF5G_RF5G1_PDTXMIX5_MASK                 0x40000000
+#define RF5G_RF5G1_PDTXMIX5_GET(x)               (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
+#define RF5G_RF5G1_PDTXMIX5_SET(x)               (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
+#define RF5G_RF5G1_PDTXBUF5_MSB                  29
+#define RF5G_RF5G1_PDTXBUF5_LSB                  29
+#define RF5G_RF5G1_PDTXBUF5_MASK                 0x20000000
+#define RF5G_RF5G1_PDTXBUF5_GET(x)               (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
+#define RF5G_RF5G1_PDTXBUF5_SET(x)               (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
+#define RF5G_RF5G1_PDPADRV5_MSB                  28
+#define RF5G_RF5G1_PDPADRV5_LSB                  28
+#define RF5G_RF5G1_PDPADRV5_MASK                 0x10000000
+#define RF5G_RF5G1_PDPADRV5_GET(x)               (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
+#define RF5G_RF5G1_PDPADRV5_SET(x)               (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
+#define RF5G_RF5G1_PDPAOUT5_MSB                  27
+#define RF5G_RF5G1_PDPAOUT5_LSB                  27
+#define RF5G_RF5G1_PDPAOUT5_MASK                 0x08000000
+#define RF5G_RF5G1_PDPAOUT5_GET(x)               (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
+#define RF5G_RF5G1_PDPAOUT5_SET(x)               (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
+#define RF5G_RF5G1_TUNE_PADRV5_MSB               26
+#define RF5G_RF5G1_TUNE_PADRV5_LSB               24
+#define RF5G_RF5G1_TUNE_PADRV5_MASK              0x07000000
+#define RF5G_RF5G1_TUNE_PADRV5_GET(x)            (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
+#define RF5G_RF5G1_TUNE_PADRV5_SET(x)            (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
+#define RF5G_RF5G1_PWDTXPKD_MSB                  23
+#define RF5G_RF5G1_PWDTXPKD_LSB                  21
+#define RF5G_RF5G1_PWDTXPKD_MASK                 0x00e00000
+#define RF5G_RF5G1_PWDTXPKD_GET(x)               (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
+#define RF5G_RF5G1_PWDTXPKD_SET(x)               (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
+#define RF5G_RF5G1_DB5_MSB                       20
+#define RF5G_RF5G1_DB5_LSB                       18
+#define RF5G_RF5G1_DB5_MASK                      0x001c0000
+#define RF5G_RF5G1_DB5_GET(x)                    (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
+#define RF5G_RF5G1_DB5_SET(x)                    (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
+#define RF5G_RF5G1_OB5_MSB                       17
+#define RF5G_RF5G1_OB5_LSB                       15
+#define RF5G_RF5G1_OB5_MASK                      0x00038000
+#define RF5G_RF5G1_OB5_GET(x)                    (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
+#define RF5G_RF5G1_OB5_SET(x)                    (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
+#define RF5G_RF5G1_TX5_ATB_SEL_MSB               14
+#define RF5G_RF5G1_TX5_ATB_SEL_LSB               12
+#define RF5G_RF5G1_TX5_ATB_SEL_MASK              0x00007000
+#define RF5G_RF5G1_TX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
+#define RF5G_RF5G1_TX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
+#define RF5G_RF5G1_PDLO5DIV_MSB                  11
+#define RF5G_RF5G1_PDLO5DIV_LSB                  11
+#define RF5G_RF5G1_PDLO5DIV_MASK                 0x00000800
+#define RF5G_RF5G1_PDLO5DIV_GET(x)               (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
+#define RF5G_RF5G1_PDLO5DIV_SET(x)               (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
+#define RF5G_RF5G1_PDLO5MIX_MSB                  10
+#define RF5G_RF5G1_PDLO5MIX_LSB                  10
+#define RF5G_RF5G1_PDLO5MIX_MASK                 0x00000400
+#define RF5G_RF5G1_PDLO5MIX_GET(x)               (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
+#define RF5G_RF5G1_PDLO5MIX_SET(x)               (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
+#define RF5G_RF5G1_PDQBUF5_MSB                   9
+#define RF5G_RF5G1_PDQBUF5_LSB                   9
+#define RF5G_RF5G1_PDQBUF5_MASK                  0x00000200
+#define RF5G_RF5G1_PDQBUF5_GET(x)                (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
+#define RF5G_RF5G1_PDQBUF5_SET(x)                (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
+#define RF5G_RF5G1_PDLO5AGC_MSB                  8
+#define RF5G_RF5G1_PDLO5AGC_LSB                  8
+#define RF5G_RF5G1_PDLO5AGC_MASK                 0x00000100
+#define RF5G_RF5G1_PDLO5AGC_GET(x)               (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
+#define RF5G_RF5G1_PDLO5AGC_SET(x)               (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
+#define RF5G_RF5G1_PDREGLO5_MSB                  7
+#define RF5G_RF5G1_PDREGLO5_LSB                  7
+#define RF5G_RF5G1_PDREGLO5_MASK                 0x00000080
+#define RF5G_RF5G1_PDREGLO5_GET(x)               (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
+#define RF5G_RF5G1_PDREGLO5_SET(x)               (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
+#define RF5G_RF5G1_LO5_ATB_SEL_MSB               6
+#define RF5G_RF5G1_LO5_ATB_SEL_LSB               4
+#define RF5G_RF5G1_LO5_ATB_SEL_MASK              0x00000070
+#define RF5G_RF5G1_LO5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
+#define RF5G_RF5G1_LO5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
+#define RF5G_RF5G1_LO5CONTROL_MSB                3
+#define RF5G_RF5G1_LO5CONTROL_LSB                3
+#define RF5G_RF5G1_LO5CONTROL_MASK               0x00000008
+#define RF5G_RF5G1_LO5CONTROL_GET(x)             (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
+#define RF5G_RF5G1_LO5CONTROL_SET(x)             (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
+#define RF5G_RF5G1_REGLO_BYPASS5_MSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_LSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_MASK            0x00000004
+#define RF5G_RF5G1_REGLO_BYPASS5_GET(x)          (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
+#define RF5G_RF5G1_REGLO_BYPASS5_SET(x)          (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
+#define RF5G_RF5G1_SPARE_MSB                     1
+#define RF5G_RF5G1_SPARE_LSB                     0
+#define RF5G_RF5G1_SPARE_MASK                    0x00000003
+#define RF5G_RF5G1_SPARE_GET(x)                  (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
+#define RF5G_RF5G1_SPARE_SET(x)                  (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
+
+#define RF5G_RF5G2_ADDRESS                       0x00000024
+#define RF5G_RF5G2_OFFSET                        0x00000024
+#define RF5G_RF5G2_AGCLO_B_MSB                   31
+#define RF5G_RF5G2_AGCLO_B_LSB                   29
+#define RF5G_RF5G2_AGCLO_B_MASK                  0xe0000000
+#define RF5G_RF5G2_AGCLO_B_GET(x)                (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
+#define RF5G_RF5G2_AGCLO_B_SET(x)                (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
+#define RF5G_RF5G2_RX5_ATB_SEL_MSB               28
+#define RF5G_RF5G2_RX5_ATB_SEL_LSB               26
+#define RF5G_RF5G2_RX5_ATB_SEL_MASK              0x1c000000
+#define RF5G_RF5G2_RX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
+#define RF5G_RF5G2_RX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
+#define RF5G_RF5G2_PDCMOSLO5_MSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_LSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_MASK                0x02000000
+#define RF5G_RF5G2_PDCMOSLO5_GET(x)              (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
+#define RF5G_RF5G2_PDCMOSLO5_SET(x)              (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
+#define RF5G_RF5G2_PDVGM5_MSB                    24
+#define RF5G_RF5G2_PDVGM5_LSB                    24
+#define RF5G_RF5G2_PDVGM5_MASK                   0x01000000
+#define RF5G_RF5G2_PDVGM5_GET(x)                 (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
+#define RF5G_RF5G2_PDVGM5_SET(x)                 (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
+#define RF5G_RF5G2_PDCSLNA5_MSB                  23
+#define RF5G_RF5G2_PDCSLNA5_LSB                  23
+#define RF5G_RF5G2_PDCSLNA5_MASK                 0x00800000
+#define RF5G_RF5G2_PDCSLNA5_GET(x)               (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
+#define RF5G_RF5G2_PDCSLNA5_SET(x)               (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
+#define RF5G_RF5G2_PDRFVGA5_MSB                  22
+#define RF5G_RF5G2_PDRFVGA5_LSB                  22
+#define RF5G_RF5G2_PDRFVGA5_MASK                 0x00400000
+#define RF5G_RF5G2_PDRFVGA5_GET(x)               (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
+#define RF5G_RF5G2_PDRFVGA5_SET(x)               (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
+#define RF5G_RF5G2_PDREGFE5_MSB                  21
+#define RF5G_RF5G2_PDREGFE5_LSB                  21
+#define RF5G_RF5G2_PDREGFE5_MASK                 0x00200000
+#define RF5G_RF5G2_PDREGFE5_GET(x)               (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
+#define RF5G_RF5G2_PDREGFE5_SET(x)               (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
+#define RF5G_RF5G2_TUNE_RFVGA5_MSB               20
+#define RF5G_RF5G2_TUNE_RFVGA5_LSB               18
+#define RF5G_RF5G2_TUNE_RFVGA5_MASK              0x001c0000
+#define RF5G_RF5G2_TUNE_RFVGA5_GET(x)            (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
+#define RF5G_RF5G2_TUNE_RFVGA5_SET(x)            (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
+#define RF5G_RF5G2_BRFVGA5_MSB                   17
+#define RF5G_RF5G2_BRFVGA5_LSB                   15
+#define RF5G_RF5G2_BRFVGA5_MASK                  0x00038000
+#define RF5G_RF5G2_BRFVGA5_GET(x)                (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
+#define RF5G_RF5G2_BRFVGA5_SET(x)                (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
+#define RF5G_RF5G2_BCSLNA5_MSB                   14
+#define RF5G_RF5G2_BCSLNA5_LSB                   12
+#define RF5G_RF5G2_BCSLNA5_MASK                  0x00007000
+#define RF5G_RF5G2_BCSLNA5_GET(x)                (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
+#define RF5G_RF5G2_BCSLNA5_SET(x)                (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
+#define RF5G_RF5G2_BVGM5_MSB                     11
+#define RF5G_RF5G2_BVGM5_LSB                     9
+#define RF5G_RF5G2_BVGM5_MASK                    0x00000e00
+#define RF5G_RF5G2_BVGM5_GET(x)                  (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
+#define RF5G_RF5G2_BVGM5_SET(x)                  (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
+#define RF5G_RF5G2_REGFE_BYPASS5_MSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_LSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_MASK            0x00000100
+#define RF5G_RF5G2_REGFE_BYPASS5_GET(x)          (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
+#define RF5G_RF5G2_REGFE_BYPASS5_SET(x)          (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
+#define RF5G_RF5G2_LNA5_ATTENMODE_MSB            7
+#define RF5G_RF5G2_LNA5_ATTENMODE_LSB            6
+#define RF5G_RF5G2_LNA5_ATTENMODE_MASK           0x000000c0
+#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x)         (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
+#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x)         (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
+#define RF5G_RF5G2_ENABLE_PCA_MSB                5
+#define RF5G_RF5G2_ENABLE_PCA_LSB                5
+#define RF5G_RF5G2_ENABLE_PCA_MASK               0x00000020
+#define RF5G_RF5G2_ENABLE_PCA_GET(x)             (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
+#define RF5G_RF5G2_ENABLE_PCA_SET(x)             (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
+#define RF5G_RF5G2_TUNE_LO_MSB                   4
+#define RF5G_RF5G2_TUNE_LO_LSB                   2
+#define RF5G_RF5G2_TUNE_LO_MASK                  0x0000001c
+#define RF5G_RF5G2_TUNE_LO_GET(x)                (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
+#define RF5G_RF5G2_TUNE_LO_SET(x)                (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
+#define RF5G_RF5G2_SPARE_MSB                     1
+#define RF5G_RF5G2_SPARE_LSB                     0
+#define RF5G_RF5G2_SPARE_MASK                    0x00000003
+#define RF5G_RF5G2_SPARE_GET(x)                  (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
+#define RF5G_RF5G2_SPARE_SET(x)                  (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
+
+#define RF2G_RF2G1_ADDRESS                       0x00000028
+#define RF2G_RF2G1_OFFSET                        0x00000028
+#define RF2G_RF2G1_BLNA1_MSB                     31
+#define RF2G_RF2G1_BLNA1_LSB                     29
+#define RF2G_RF2G1_BLNA1_MASK                    0xe0000000
+#define RF2G_RF2G1_BLNA1_GET(x)                  (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
+#define RF2G_RF2G1_BLNA1_SET(x)                  (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
+#define RF2G_RF2G1_BLNA1F_MSB                    28
+#define RF2G_RF2G1_BLNA1F_LSB                    26
+#define RF2G_RF2G1_BLNA1F_MASK                   0x1c000000
+#define RF2G_RF2G1_BLNA1F_GET(x)                 (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
+#define RF2G_RF2G1_BLNA1F_SET(x)                 (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
+#define RF2G_RF2G1_BLNA1BUF_MSB                  25
+#define RF2G_RF2G1_BLNA1BUF_LSB                  23
+#define RF2G_RF2G1_BLNA1BUF_MASK                 0x03800000
+#define RF2G_RF2G1_BLNA1BUF_GET(x)               (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
+#define RF2G_RF2G1_BLNA1BUF_SET(x)               (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
+#define RF2G_RF2G1_BLNA2_MSB                     22
+#define RF2G_RF2G1_BLNA2_LSB                     20
+#define RF2G_RF2G1_BLNA2_MASK                    0x00700000
+#define RF2G_RF2G1_BLNA2_GET(x)                  (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
+#define RF2G_RF2G1_BLNA2_SET(x)                  (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
+#define RF2G_RF2G1_DB_MSB                        19
+#define RF2G_RF2G1_DB_LSB                        17
+#define RF2G_RF2G1_DB_MASK                       0x000e0000
+#define RF2G_RF2G1_DB_GET(x)                     (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
+#define RF2G_RF2G1_DB_SET(x)                     (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
+#define RF2G_RF2G1_OB_MSB                        16
+#define RF2G_RF2G1_OB_LSB                        14
+#define RF2G_RF2G1_OB_MASK                       0x0001c000
+#define RF2G_RF2G1_OB_GET(x)                     (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
+#define RF2G_RF2G1_OB_SET(x)                     (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
+#define RF2G_RF2G1_FE_ATB_SEL_MSB                13
+#define RF2G_RF2G1_FE_ATB_SEL_LSB                11
+#define RF2G_RF2G1_FE_ATB_SEL_MASK               0x00003800
+#define RF2G_RF2G1_FE_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
+#define RF2G_RF2G1_FE_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
+#define RF2G_RF2G1_RF_ATB_SEL_MSB                10
+#define RF2G_RF2G1_RF_ATB_SEL_LSB                8
+#define RF2G_RF2G1_RF_ATB_SEL_MASK               0x00000700
+#define RF2G_RF2G1_RF_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
+#define RF2G_RF2G1_RF_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
+#define RF2G_RF2G1_SELLNA_MSB                    7
+#define RF2G_RF2G1_SELLNA_LSB                    7
+#define RF2G_RF2G1_SELLNA_MASK                   0x00000080
+#define RF2G_RF2G1_SELLNA_GET(x)                 (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
+#define RF2G_RF2G1_SELLNA_SET(x)                 (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
+#define RF2G_RF2G1_LOCONTROL_MSB                 6
+#define RF2G_RF2G1_LOCONTROL_LSB                 6
+#define RF2G_RF2G1_LOCONTROL_MASK                0x00000040
+#define RF2G_RF2G1_LOCONTROL_GET(x)              (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
+#define RF2G_RF2G1_LOCONTROL_SET(x)              (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
+#define RF2G_RF2G1_SHORTLNA2_MSB                 5
+#define RF2G_RF2G1_SHORTLNA2_LSB                 5
+#define RF2G_RF2G1_SHORTLNA2_MASK                0x00000020
+#define RF2G_RF2G1_SHORTLNA2_GET(x)              (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
+#define RF2G_RF2G1_SHORTLNA2_SET(x)              (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
+#define RF2G_RF2G1_SPARE_MSB                     4
+#define RF2G_RF2G1_SPARE_LSB                     0
+#define RF2G_RF2G1_SPARE_MASK                    0x0000001f
+#define RF2G_RF2G1_SPARE_GET(x)                  (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
+#define RF2G_RF2G1_SPARE_SET(x)                  (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
+
+#define RF2G_RF2G2_ADDRESS                       0x0000002c
+#define RF2G_RF2G2_OFFSET                        0x0000002c
+#define RF2G_RF2G2_PDCGLNA_MSB                   31
+#define RF2G_RF2G2_PDCGLNA_LSB                   31
+#define RF2G_RF2G2_PDCGLNA_MASK                  0x80000000
+#define RF2G_RF2G2_PDCGLNA_GET(x)                (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
+#define RF2G_RF2G2_PDCGLNA_SET(x)                (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
+#define RF2G_RF2G2_PDCGLNABUF_MSB                30
+#define RF2G_RF2G2_PDCGLNABUF_LSB                30
+#define RF2G_RF2G2_PDCGLNABUF_MASK               0x40000000
+#define RF2G_RF2G2_PDCGLNABUF_GET(x)             (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
+#define RF2G_RF2G2_PDCGLNABUF_SET(x)             (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
+#define RF2G_RF2G2_PDCSLNA_MSB                   29
+#define RF2G_RF2G2_PDCSLNA_LSB                   29
+#define RF2G_RF2G2_PDCSLNA_MASK                  0x20000000
+#define RF2G_RF2G2_PDCSLNA_GET(x)                (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
+#define RF2G_RF2G2_PDCSLNA_SET(x)                (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
+#define RF2G_RF2G2_PDDIV_MSB                     28
+#define RF2G_RF2G2_PDDIV_LSB                     28
+#define RF2G_RF2G2_PDDIV_MASK                    0x10000000
+#define RF2G_RF2G2_PDDIV_GET(x)                  (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
+#define RF2G_RF2G2_PDDIV_SET(x)                  (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
+#define RF2G_RF2G2_PDPADRV_MSB                   27
+#define RF2G_RF2G2_PDPADRV_LSB                   27
+#define RF2G_RF2G2_PDPADRV_MASK                  0x08000000
+#define RF2G_RF2G2_PDPADRV_GET(x)                (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
+#define RF2G_RF2G2_PDPADRV_SET(x)                (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
+#define RF2G_RF2G2_PDPAOUT_MSB                   26
+#define RF2G_RF2G2_PDPAOUT_LSB                   26
+#define RF2G_RF2G2_PDPAOUT_MASK                  0x04000000
+#define RF2G_RF2G2_PDPAOUT_GET(x)                (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
+#define RF2G_RF2G2_PDPAOUT_SET(x)                (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
+#define RF2G_RF2G2_PDREGLNA_MSB                  25
+#define RF2G_RF2G2_PDREGLNA_LSB                  25
+#define RF2G_RF2G2_PDREGLNA_MASK                 0x02000000
+#define RF2G_RF2G2_PDREGLNA_GET(x)               (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
+#define RF2G_RF2G2_PDREGLNA_SET(x)               (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
+#define RF2G_RF2G2_PDREGLO_MSB                   24
+#define RF2G_RF2G2_PDREGLO_LSB                   24
+#define RF2G_RF2G2_PDREGLO_MASK                  0x01000000
+#define RF2G_RF2G2_PDREGLO_GET(x)                (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
+#define RF2G_RF2G2_PDREGLO_SET(x)                (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
+#define RF2G_RF2G2_PDRFGM_MSB                    23
+#define RF2G_RF2G2_PDRFGM_LSB                    23
+#define RF2G_RF2G2_PDRFGM_MASK                   0x00800000
+#define RF2G_RF2G2_PDRFGM_GET(x)                 (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
+#define RF2G_RF2G2_PDRFGM_SET(x)                 (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
+#define RF2G_RF2G2_PDRXLO_MSB                    22
+#define RF2G_RF2G2_PDRXLO_LSB                    22
+#define RF2G_RF2G2_PDRXLO_MASK                   0x00400000
+#define RF2G_RF2G2_PDRXLO_GET(x)                 (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
+#define RF2G_RF2G2_PDRXLO_SET(x)                 (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
+#define RF2G_RF2G2_PDTXLO_MSB                    21
+#define RF2G_RF2G2_PDTXLO_LSB                    21
+#define RF2G_RF2G2_PDTXLO_MASK                   0x00200000
+#define RF2G_RF2G2_PDTXLO_GET(x)                 (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
+#define RF2G_RF2G2_PDTXLO_SET(x)                 (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
+#define RF2G_RF2G2_PDTXMIX_MSB                   20
+#define RF2G_RF2G2_PDTXMIX_LSB                   20
+#define RF2G_RF2G2_PDTXMIX_MASK                  0x00100000
+#define RF2G_RF2G2_PDTXMIX_GET(x)                (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
+#define RF2G_RF2G2_PDTXMIX_SET(x)                (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
+#define RF2G_RF2G2_REGLNA_BYPASS_MSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_LSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_MASK            0x00080000
+#define RF2G_RF2G2_REGLNA_BYPASS_GET(x)          (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
+#define RF2G_RF2G2_REGLNA_BYPASS_SET(x)          (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
+#define RF2G_RF2G2_REGLO_BYPASS_MSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_LSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_MASK             0x00040000
+#define RF2G_RF2G2_REGLO_BYPASS_GET(x)           (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
+#define RF2G_RF2G2_REGLO_BYPASS_SET(x)           (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
+#define RF2G_RF2G2_ENABLE_PCB_MSB                17
+#define RF2G_RF2G2_ENABLE_PCB_LSB                17
+#define RF2G_RF2G2_ENABLE_PCB_MASK               0x00020000
+#define RF2G_RF2G2_ENABLE_PCB_GET(x)             (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
+#define RF2G_RF2G2_ENABLE_PCB_SET(x)             (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
+#define RF2G_RF2G2_SPARE_MSB                     16
+#define RF2G_RF2G2_SPARE_LSB                     0
+#define RF2G_RF2G2_SPARE_MASK                    0x0001ffff
+#define RF2G_RF2G2_SPARE_GET(x)                  (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
+#define RF2G_RF2G2_SPARE_SET(x)                  (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
+
+#define TOP_GAIN_ADDRESS                         0x00000030
+#define TOP_GAIN_OFFSET                          0x00000030
+#define TOP_GAIN_TX6DBLOQGAIN_MSB                31
+#define TOP_GAIN_TX6DBLOQGAIN_LSB                30
+#define TOP_GAIN_TX6DBLOQGAIN_MASK               0xc0000000
+#define TOP_GAIN_TX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
+#define TOP_GAIN_TX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
+#define TOP_GAIN_TX1DBLOQGAIN_MSB                29
+#define TOP_GAIN_TX1DBLOQGAIN_LSB                27
+#define TOP_GAIN_TX1DBLOQGAIN_MASK               0x38000000
+#define TOP_GAIN_TX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
+#define TOP_GAIN_TX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
+#define TOP_GAIN_TXV2IGAIN_MSB                   26
+#define TOP_GAIN_TXV2IGAIN_LSB                   25
+#define TOP_GAIN_TXV2IGAIN_MASK                  0x06000000
+#define TOP_GAIN_TXV2IGAIN_GET(x)                (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
+#define TOP_GAIN_TXV2IGAIN_SET(x)                (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
+#define TOP_GAIN_PABUF5GN_MSB                    24
+#define TOP_GAIN_PABUF5GN_LSB                    24
+#define TOP_GAIN_PABUF5GN_MASK                   0x01000000
+#define TOP_GAIN_PABUF5GN_GET(x)                 (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
+#define TOP_GAIN_PABUF5GN_SET(x)                 (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
+#define TOP_GAIN_PADRVGN_MSB                     23
+#define TOP_GAIN_PADRVGN_LSB                     21
+#define TOP_GAIN_PADRVGN_MASK                    0x00e00000
+#define TOP_GAIN_PADRVGN_GET(x)                  (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
+#define TOP_GAIN_PADRVGN_SET(x)                  (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
+#define TOP_GAIN_PAOUT2GN_MSB                    20
+#define TOP_GAIN_PAOUT2GN_LSB                    18
+#define TOP_GAIN_PAOUT2GN_MASK                   0x001c0000
+#define TOP_GAIN_PAOUT2GN_GET(x)                 (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
+#define TOP_GAIN_PAOUT2GN_SET(x)                 (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
+#define TOP_GAIN_LNAON_MSB                       17
+#define TOP_GAIN_LNAON_LSB                       17
+#define TOP_GAIN_LNAON_MASK                      0x00020000
+#define TOP_GAIN_LNAON_GET(x)                    (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
+#define TOP_GAIN_LNAON_SET(x)                    (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
+#define TOP_GAIN_LNAGAIN_MSB                     16
+#define TOP_GAIN_LNAGAIN_LSB                     13
+#define TOP_GAIN_LNAGAIN_MASK                    0x0001e000
+#define TOP_GAIN_LNAGAIN_GET(x)                  (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
+#define TOP_GAIN_LNAGAIN_SET(x)                  (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
+#define TOP_GAIN_RFVGA5GAIN_MSB                  12
+#define TOP_GAIN_RFVGA5GAIN_LSB                  11
+#define TOP_GAIN_RFVGA5GAIN_MASK                 0x00001800
+#define TOP_GAIN_RFVGA5GAIN_GET(x)               (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
+#define TOP_GAIN_RFVGA5GAIN_SET(x)               (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
+#define TOP_GAIN_RFGMGN_MSB                      10
+#define TOP_GAIN_RFGMGN_LSB                      8
+#define TOP_GAIN_RFGMGN_MASK                     0x00000700
+#define TOP_GAIN_RFGMGN_GET(x)                   (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
+#define TOP_GAIN_RFGMGN_SET(x)                   (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
+#define TOP_GAIN_RX6DBLOQGAIN_MSB                7
+#define TOP_GAIN_RX6DBLOQGAIN_LSB                6
+#define TOP_GAIN_RX6DBLOQGAIN_MASK               0x000000c0
+#define TOP_GAIN_RX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
+#define TOP_GAIN_RX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
+#define TOP_GAIN_RX1DBLOQGAIN_MSB                5
+#define TOP_GAIN_RX1DBLOQGAIN_LSB                3
+#define TOP_GAIN_RX1DBLOQGAIN_MASK               0x00000038
+#define TOP_GAIN_RX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
+#define TOP_GAIN_RX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
+#define TOP_GAIN_RX6DBHIQGAIN_MSB                2
+#define TOP_GAIN_RX6DBHIQGAIN_LSB                1
+#define TOP_GAIN_RX6DBHIQGAIN_MASK               0x00000006
+#define TOP_GAIN_RX6DBHIQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
+#define TOP_GAIN_RX6DBHIQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
+#define TOP_GAIN_SPARE_MSB                       0
+#define TOP_GAIN_SPARE_LSB                       0
+#define TOP_GAIN_SPARE_MASK                      0x00000001
+#define TOP_GAIN_SPARE_GET(x)                    (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
+#define TOP_GAIN_SPARE_SET(x)                    (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
+
+#define TOP_TOP_ADDRESS                          0x00000034
+#define TOP_TOP_OFFSET                           0x00000034
+#define TOP_TOP_LOCALTXGAIN_MSB                  31
+#define TOP_TOP_LOCALTXGAIN_LSB                  31
+#define TOP_TOP_LOCALTXGAIN_MASK                 0x80000000
+#define TOP_TOP_LOCALTXGAIN_GET(x)               (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
+#define TOP_TOP_LOCALTXGAIN_SET(x)               (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
+#define TOP_TOP_LOCALRXGAIN_MSB                  30
+#define TOP_TOP_LOCALRXGAIN_LSB                  30
+#define TOP_TOP_LOCALRXGAIN_MASK                 0x40000000
+#define TOP_TOP_LOCALRXGAIN_GET(x)               (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
+#define TOP_TOP_LOCALRXGAIN_SET(x)               (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
+#define TOP_TOP_LOCALMODE_MSB                    29
+#define TOP_TOP_LOCALMODE_LSB                    29
+#define TOP_TOP_LOCALMODE_MASK                   0x20000000
+#define TOP_TOP_LOCALMODE_GET(x)                 (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
+#define TOP_TOP_LOCALMODE_SET(x)                 (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
+#define TOP_TOP_CALFC_MSB                        28
+#define TOP_TOP_CALFC_LSB                        28
+#define TOP_TOP_CALFC_MASK                       0x10000000
+#define TOP_TOP_CALFC_GET(x)                     (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
+#define TOP_TOP_CALFC_SET(x)                     (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
+#define TOP_TOP_CALDC_MSB                        27
+#define TOP_TOP_CALDC_LSB                        27
+#define TOP_TOP_CALDC_MASK                       0x08000000
+#define TOP_TOP_CALDC_GET(x)                     (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
+#define TOP_TOP_CALDC_SET(x)                     (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
+#define TOP_TOP_CAL_RESIDUE_MSB                  26
+#define TOP_TOP_CAL_RESIDUE_LSB                  26
+#define TOP_TOP_CAL_RESIDUE_MASK                 0x04000000
+#define TOP_TOP_CAL_RESIDUE_GET(x)               (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
+#define TOP_TOP_CAL_RESIDUE_SET(x)               (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
+#define TOP_TOP_BMODE_MSB                        25
+#define TOP_TOP_BMODE_LSB                        25
+#define TOP_TOP_BMODE_MASK                       0x02000000
+#define TOP_TOP_BMODE_GET(x)                     (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
+#define TOP_TOP_BMODE_SET(x)                     (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
+#define TOP_TOP_SYNTHON_MSB                      24
+#define TOP_TOP_SYNTHON_LSB                      24
+#define TOP_TOP_SYNTHON_MASK                     0x01000000
+#define TOP_TOP_SYNTHON_GET(x)                   (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
+#define TOP_TOP_SYNTHON_SET(x)                   (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
+#define TOP_TOP_RXON_MSB                         23
+#define TOP_TOP_RXON_LSB                         23
+#define TOP_TOP_RXON_MASK                        0x00800000
+#define TOP_TOP_RXON_GET(x)                      (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
+#define TOP_TOP_RXON_SET(x)                      (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
+#define TOP_TOP_TXON_MSB                         22
+#define TOP_TOP_TXON_LSB                         22
+#define TOP_TOP_TXON_MASK                        0x00400000
+#define TOP_TOP_TXON_GET(x)                      (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
+#define TOP_TOP_TXON_SET(x)                      (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
+#define TOP_TOP_PAON_MSB                         21
+#define TOP_TOP_PAON_LSB                         21
+#define TOP_TOP_PAON_MASK                        0x00200000
+#define TOP_TOP_PAON_GET(x)                      (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
+#define TOP_TOP_PAON_SET(x)                      (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
+#define TOP_TOP_CALTX_MSB                        20
+#define TOP_TOP_CALTX_LSB                        20
+#define TOP_TOP_CALTX_MASK                       0x00100000
+#define TOP_TOP_CALTX_GET(x)                     (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
+#define TOP_TOP_CALTX_SET(x)                     (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
+#define TOP_TOP_LOCALADDAC_MSB                   19
+#define TOP_TOP_LOCALADDAC_LSB                   19
+#define TOP_TOP_LOCALADDAC_MASK                  0x00080000
+#define TOP_TOP_LOCALADDAC_GET(x)                (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
+#define TOP_TOP_LOCALADDAC_SET(x)                (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
+#define TOP_TOP_PWDPLL_MSB                       18
+#define TOP_TOP_PWDPLL_LSB                       18
+#define TOP_TOP_PWDPLL_MASK                      0x00040000
+#define TOP_TOP_PWDPLL_GET(x)                    (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
+#define TOP_TOP_PWDPLL_SET(x)                    (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
+#define TOP_TOP_PWDADC_MSB                       17
+#define TOP_TOP_PWDADC_LSB                       17
+#define TOP_TOP_PWDADC_MASK                      0x00020000
+#define TOP_TOP_PWDADC_GET(x)                    (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
+#define TOP_TOP_PWDADC_SET(x)                    (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
+#define TOP_TOP_PWDDAC_MSB                       16
+#define TOP_TOP_PWDDAC_LSB                       16
+#define TOP_TOP_PWDDAC_MASK                      0x00010000
+#define TOP_TOP_PWDDAC_GET(x)                    (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
+#define TOP_TOP_PWDDAC_SET(x)                    (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
+#define TOP_TOP_LOCALXTAL_MSB                    15
+#define TOP_TOP_LOCALXTAL_LSB                    15
+#define TOP_TOP_LOCALXTAL_MASK                   0x00008000
+#define TOP_TOP_LOCALXTAL_GET(x)                 (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
+#define TOP_TOP_LOCALXTAL_SET(x)                 (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
+#define TOP_TOP_PWDCLKIN_MSB                     14
+#define TOP_TOP_PWDCLKIN_LSB                     14
+#define TOP_TOP_PWDCLKIN_MASK                    0x00004000
+#define TOP_TOP_PWDCLKIN_GET(x)                  (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
+#define TOP_TOP_PWDCLKIN_SET(x)                  (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
+#define TOP_TOP_OSCON_MSB                        13
+#define TOP_TOP_OSCON_LSB                        13
+#define TOP_TOP_OSCON_MASK                       0x00002000
+#define TOP_TOP_OSCON_GET(x)                     (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
+#define TOP_TOP_OSCON_SET(x)                     (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
+#define TOP_TOP_SCLKEN_FORCE_MSB                 12
+#define TOP_TOP_SCLKEN_FORCE_LSB                 12
+#define TOP_TOP_SCLKEN_FORCE_MASK                0x00001000
+#define TOP_TOP_SCLKEN_FORCE_GET(x)              (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
+#define TOP_TOP_SCLKEN_FORCE_SET(x)              (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
+#define TOP_TOP_SYNTHON_FORCE_MSB                11
+#define TOP_TOP_SYNTHON_FORCE_LSB                11
+#define TOP_TOP_SYNTHON_FORCE_MASK               0x00000800
+#define TOP_TOP_SYNTHON_FORCE_GET(x)             (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
+#define TOP_TOP_SYNTHON_FORCE_SET(x)             (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
+#define TOP_TOP_PDBIAS_MSB                       10
+#define TOP_TOP_PDBIAS_LSB                       10
+#define TOP_TOP_PDBIAS_MASK                      0x00000400
+#define TOP_TOP_PDBIAS_GET(x)                    (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
+#define TOP_TOP_PDBIAS_SET(x)                    (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
+#define TOP_TOP_DATAOUTSEL_MSB                   9
+#define TOP_TOP_DATAOUTSEL_LSB                   8
+#define TOP_TOP_DATAOUTSEL_MASK                  0x00000300
+#define TOP_TOP_DATAOUTSEL_GET(x)                (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
+#define TOP_TOP_DATAOUTSEL_SET(x)                (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
+#define TOP_TOP_REVID_MSB                        7
+#define TOP_TOP_REVID_LSB                        5
+#define TOP_TOP_REVID_MASK                       0x000000e0
+#define TOP_TOP_REVID_GET(x)                     (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
+#define TOP_TOP_REVID_SET(x)                     (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
+#define TOP_TOP_INT2PAD_MSB                      4
+#define TOP_TOP_INT2PAD_LSB                      4
+#define TOP_TOP_INT2PAD_MASK                     0x00000010
+#define TOP_TOP_INT2PAD_GET(x)                   (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
+#define TOP_TOP_INT2PAD_SET(x)                   (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
+#define TOP_TOP_INTH2PAD_MSB                     3
+#define TOP_TOP_INTH2PAD_LSB                     3
+#define TOP_TOP_INTH2PAD_MASK                    0x00000008
+#define TOP_TOP_INTH2PAD_GET(x)                  (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
+#define TOP_TOP_INTH2PAD_SET(x)                  (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
+#define TOP_TOP_PAD2GND_MSB                      2
+#define TOP_TOP_PAD2GND_LSB                      2
+#define TOP_TOP_PAD2GND_MASK                     0x00000004
+#define TOP_TOP_PAD2GND_GET(x)                   (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
+#define TOP_TOP_PAD2GND_SET(x)                   (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
+#define TOP_TOP_INT2GND_MSB                      1
+#define TOP_TOP_INT2GND_LSB                      1
+#define TOP_TOP_INT2GND_MASK                     0x00000002
+#define TOP_TOP_INT2GND_GET(x)                   (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
+#define TOP_TOP_INT2GND_SET(x)                   (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
+#define TOP_TOP_FORCE_XPAON_MSB                  0
+#define TOP_TOP_FORCE_XPAON_LSB                  0
+#define TOP_TOP_FORCE_XPAON_MASK                 0x00000001
+#define TOP_TOP_FORCE_XPAON_GET(x)               (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
+#define TOP_TOP_FORCE_XPAON_SET(x)               (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
+
+#define BIAS_BIAS_SEL_ADDRESS                    0x00000038
+#define BIAS_BIAS_SEL_OFFSET                     0x00000038
+#define BIAS_BIAS_SEL_PADON_MSB                  31
+#define BIAS_BIAS_SEL_PADON_LSB                  31
+#define BIAS_BIAS_SEL_PADON_MASK                 0x80000000
+#define BIAS_BIAS_SEL_PADON_GET(x)               (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
+#define BIAS_BIAS_SEL_PADON_SET(x)               (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
+#define BIAS_BIAS_SEL_SEL_BIAS_MSB               30
+#define BIAS_BIAS_SEL_SEL_BIAS_LSB               25
+#define BIAS_BIAS_SEL_SEL_BIAS_MASK              0x7e000000
+#define BIAS_BIAS_SEL_SEL_BIAS_GET(x)            (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
+#define BIAS_BIAS_SEL_SEL_BIAS_SET(x)            (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
+#define BIAS_BIAS_SEL_SEL_SPARE_MSB              24
+#define BIAS_BIAS_SEL_SEL_SPARE_LSB              21
+#define BIAS_BIAS_SEL_SEL_SPARE_MASK             0x01e00000
+#define BIAS_BIAS_SEL_SEL_SPARE_GET(x)           (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SEL_SPARE_SET(x)           (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_SPARE_MSB                  20
+#define BIAS_BIAS_SEL_SPARE_LSB                  20
+#define BIAS_BIAS_SEL_SPARE_MASK                 0x00100000
+#define BIAS_BIAS_SEL_SPARE_GET(x)               (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SPARE_SET(x)               (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB   19
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB   17
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK  0x000e0000
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK   0x00010000
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK  0x00004000
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK          0x00002000
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB       12
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB       10
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK      0x00001c00
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x)    (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x)    (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB           9
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB           7
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK          0x00000380
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB          6
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB          4
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK         0x00000070
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x)       (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x)       (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB           3
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB           1
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK          0x0000000e
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK           0x00000001
+#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x)         (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x)         (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
+
+#define BIAS_BIAS1_ADDRESS                       0x0000003c
+#define BIAS_BIAS1_OFFSET                        0x0000003c
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB            31
+#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB            29
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK           0xe0000000
+#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x)         (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
+#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x)         (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
+#define BIAS_BIAS1_PWD_IC2GVGM25_MSB             28
+#define BIAS_BIAS1_PWD_IC2GVGM25_LSB             26
+#define BIAS_BIAS1_PWD_IC2GVGM25_MASK            0x1c000000
+#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x)          (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
+#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x)          (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB            25
+#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB            23
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK           0x03800000
+#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB           22
+#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB           20
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK          0x00700000
+#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB          19
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB          17
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK         0x000e0000
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x)       (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x)       (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK        0x00010000
+#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK        0x00008000
+#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK           0x00004000
+#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB            13
+#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB            11
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK           0x00003800
+#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB           10
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB           8
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK          0x00000700
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GQB25_MSB              7
+#define BIAS_BIAS1_PWD_IC5GQB25_LSB              5
+#define BIAS_BIAS1_PWD_IC5GQB25_MASK             0x000000e0
+#define BIAS_BIAS1_PWD_IC5GQB25_GET(x)           (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
+#define BIAS_BIAS1_PWD_IC5GQB25_SET(x)           (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB            4
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB            2
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK           0x0000001c
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
+#define BIAS_BIAS1_SPARE_MSB                     1
+#define BIAS_BIAS1_SPARE_LSB                     0
+#define BIAS_BIAS1_SPARE_MASK                    0x00000003
+#define BIAS_BIAS1_SPARE_GET(x)                  (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
+#define BIAS_BIAS1_SPARE_SET(x)                  (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
+
+#define BIAS_BIAS2_ADDRESS                       0x00000040
+#define BIAS_BIAS2_OFFSET                        0x00000040
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB            31
+#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB            29
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK           0xe0000000
+#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x)         (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
+#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x)         (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
+#define BIAS_BIAS2_PWD_IC5GDIV25_MSB             28
+#define BIAS_BIAS2_PWD_IC5GDIV25_LSB             26
+#define BIAS_BIAS2_PWD_IC5GDIV25_MASK            0x1c000000
+#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x)          (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
+#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x)          (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB           25
+#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB           23
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK          0x03800000
+#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IRPLL25_MSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_LSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_MASK              0x00400000
+#define BIAS_BIAS2_PWD_IRPLL25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
+#define BIAS_BIAS2_PWD_IRPLL25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
+#define BIAS_BIAS2_PWD_IRXTAL25_MSB              21
+#define BIAS_BIAS2_PWD_IRXTAL25_LSB              19
+#define BIAS_BIAS2_PWD_IRXTAL25_MASK             0x00380000
+#define BIAS_BIAS2_PWD_IRXTAL25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
+#define BIAS_BIAS2_PWD_IRXTAL25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
+#define BIAS_BIAS2_PWD_IRTSENS25_MSB             18
+#define BIAS_BIAS2_PWD_IRTSENS25_LSB             16
+#define BIAS_BIAS2_PWD_IRTSENS25_MASK            0x00070000
+#define BIAS_BIAS2_PWD_IRTSENS25_GET(x)          (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
+#define BIAS_BIAS2_PWD_IRTSENS25_SET(x)          (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
+#define BIAS_BIAS2_PWD_IRTXPC25_MSB              15
+#define BIAS_BIAS2_PWD_IRTXPC25_LSB              13
+#define BIAS_BIAS2_PWD_IRTXPC25_MASK             0x0000e000
+#define BIAS_BIAS2_PWD_IRTXPC25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
+#define BIAS_BIAS2_PWD_IRTXPC25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
+#define BIAS_BIAS2_PWD_IRLDO25_MSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_LSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_MASK              0x00001000
+#define BIAS_BIAS2_PWD_IRLDO25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
+#define BIAS_BIAS2_PWD_IRLDO25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB           11
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB           9
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK          0x00000e00
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB           8
+#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB           6
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK          0x000001c0
+#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB          5
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB          3
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK         0x00000038
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x)       (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x)       (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB        2
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB        0
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK       0x00000007
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x)     (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x)     (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
+
+#define BIAS_BIAS3_ADDRESS                       0x00000044
+#define BIAS_BIAS3_OFFSET                        0x00000044
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB           31
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB           29
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK          0xe0000000
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x)        (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x)        (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
+#define BIAS_BIAS3_PWD_IR5GAGC25_MSB             28
+#define BIAS_BIAS3_PWD_IR5GAGC25_LSB             26
+#define BIAS_BIAS3_PWD_IR5GAGC25_MASK            0x1c000000
+#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x)          (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
+#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x)          (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
+#define BIAS_BIAS3_PWD_ICDAC50_MSB               25
+#define BIAS_BIAS3_PWD_ICDAC50_LSB               23
+#define BIAS_BIAS3_PWD_ICDAC50_MASK              0x03800000
+#define BIAS_BIAS3_PWD_ICDAC50_GET(x)            (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
+#define BIAS_BIAS3_PWD_ICDAC50_SET(x)            (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
+#define BIAS_BIAS3_PWD_ICSYNTH50_MSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_LSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_MASK            0x00400000
+#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_ICBB50_MSB                21
+#define BIAS_BIAS3_PWD_ICBB50_LSB                21
+#define BIAS_BIAS3_PWD_ICBB50_MASK               0x00200000
+#define BIAS_BIAS3_PWD_ICBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
+#define BIAS_BIAS3_PWD_ICBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
+#define BIAS_BIAS3_PWD_IC2GDIV50_MSB             20
+#define BIAS_BIAS3_PWD_IC2GDIV50_LSB             18
+#define BIAS_BIAS3_PWD_IC2GDIV50_MASK            0x001c0000
+#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x)          (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
+#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x)          (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
+#define BIAS_BIAS3_PWD_IRSYNTH50_MSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_LSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_MASK            0x00020000
+#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_IRBB50_MSB                16
+#define BIAS_BIAS3_PWD_IRBB50_LSB                16
+#define BIAS_BIAS3_PWD_IRBB50_MASK               0x00010000
+#define BIAS_BIAS3_PWD_IRBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
+#define BIAS_BIAS3_PWD_IRBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE1_MSB            15
+#define BIAS_BIAS3_PWD_IC25SPARE1_LSB            13
+#define BIAS_BIAS3_PWD_IC25SPARE1_MASK           0x0000e000
+#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE2_MSB            12
+#define BIAS_BIAS3_PWD_IC25SPARE2_LSB            10
+#define BIAS_BIAS3_PWD_IC25SPARE2_MASK           0x00001c00
+#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE1_MSB            9
+#define BIAS_BIAS3_PWD_IR25SPARE1_LSB            7
+#define BIAS_BIAS3_PWD_IR25SPARE1_MASK           0x00000380
+#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE2_MSB            6
+#define BIAS_BIAS3_PWD_IR25SPARE2_LSB            4
+#define BIAS_BIAS3_PWD_IR25SPARE2_MASK           0x00000070
+#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB          3
+#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB          1
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK         0x0000000e
+#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x)       (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x)       (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
+#define BIAS_BIAS3_SPARE_MSB                     0
+#define BIAS_BIAS3_SPARE_LSB                     0
+#define BIAS_BIAS3_SPARE_MASK                    0x00000001
+#define BIAS_BIAS3_SPARE_GET(x)                  (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
+#define BIAS_BIAS3_SPARE_SET(x)                  (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
+
+#define TXPC_TXPC_ADDRESS                        0x00000048
+#define TXPC_TXPC_OFFSET                         0x00000048
+#define TXPC_TXPC_SELINTPD_MSB                   31
+#define TXPC_TXPC_SELINTPD_LSB                   31
+#define TXPC_TXPC_SELINTPD_MASK                  0x80000000
+#define TXPC_TXPC_SELINTPD_GET(x)                (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
+#define TXPC_TXPC_SELINTPD_SET(x)                (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
+#define TXPC_TXPC_TEST_MSB                       30
+#define TXPC_TXPC_TEST_LSB                       30
+#define TXPC_TXPC_TEST_MASK                      0x40000000
+#define TXPC_TXPC_TEST_GET(x)                    (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
+#define TXPC_TXPC_TEST_SET(x)                    (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
+#define TXPC_TXPC_TESTGAIN_MSB                   29
+#define TXPC_TXPC_TESTGAIN_LSB                   28
+#define TXPC_TXPC_TESTGAIN_MASK                  0x30000000
+#define TXPC_TXPC_TESTGAIN_GET(x)                (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
+#define TXPC_TXPC_TESTGAIN_SET(x)                (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
+#define TXPC_TXPC_TESTDAC_MSB                    27
+#define TXPC_TXPC_TESTDAC_LSB                    22
+#define TXPC_TXPC_TESTDAC_MASK                   0x0fc00000
+#define TXPC_TXPC_TESTDAC_GET(x)                 (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
+#define TXPC_TXPC_TESTDAC_SET(x)                 (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
+#define TXPC_TXPC_TESTPWDPC_MSB                  21
+#define TXPC_TXPC_TESTPWDPC_LSB                  21
+#define TXPC_TXPC_TESTPWDPC_MASK                 0x00200000
+#define TXPC_TXPC_TESTPWDPC_GET(x)               (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
+#define TXPC_TXPC_TESTPWDPC_SET(x)               (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
+#define TXPC_TXPC_CURHALF_MSB                    20
+#define TXPC_TXPC_CURHALF_LSB                    20
+#define TXPC_TXPC_CURHALF_MASK                   0x00100000
+#define TXPC_TXPC_CURHALF_GET(x)                 (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
+#define TXPC_TXPC_CURHALF_SET(x)                 (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
+#define TXPC_TXPC_NEGOUT_MSB                     19
+#define TXPC_TXPC_NEGOUT_LSB                     19
+#define TXPC_TXPC_NEGOUT_MASK                    0x00080000
+#define TXPC_TXPC_NEGOUT_GET(x)                  (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
+#define TXPC_TXPC_NEGOUT_SET(x)                  (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
+#define TXPC_TXPC_CLKDELAY_MSB                   18
+#define TXPC_TXPC_CLKDELAY_LSB                   18
+#define TXPC_TXPC_CLKDELAY_MASK                  0x00040000
+#define TXPC_TXPC_CLKDELAY_GET(x)                (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
+#define TXPC_TXPC_CLKDELAY_SET(x)                (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
+#define TXPC_TXPC_SELMODREF_MSB                  17
+#define TXPC_TXPC_SELMODREF_LSB                  17
+#define TXPC_TXPC_SELMODREF_MASK                 0x00020000
+#define TXPC_TXPC_SELMODREF_GET(x)               (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
+#define TXPC_TXPC_SELMODREF_SET(x)               (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
+#define TXPC_TXPC_SELCMOUT_MSB                   16
+#define TXPC_TXPC_SELCMOUT_LSB                   16
+#define TXPC_TXPC_SELCMOUT_MASK                  0x00010000
+#define TXPC_TXPC_SELCMOUT_GET(x)                (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
+#define TXPC_TXPC_SELCMOUT_SET(x)                (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
+#define TXPC_TXPC_TSMODE_MSB                     15
+#define TXPC_TXPC_TSMODE_LSB                     14
+#define TXPC_TXPC_TSMODE_MASK                    0x0000c000
+#define TXPC_TXPC_TSMODE_GET(x)                  (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
+#define TXPC_TXPC_TSMODE_SET(x)                  (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
+#define TXPC_TXPC_N_MSB                          13
+#define TXPC_TXPC_N_LSB                          6
+#define TXPC_TXPC_N_MASK                         0x00003fc0
+#define TXPC_TXPC_N_GET(x)                       (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
+#define TXPC_TXPC_N_SET(x)                       (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
+#define TXPC_TXPC_ON1STSYNTHON_MSB               5
+#define TXPC_TXPC_ON1STSYNTHON_LSB               5
+#define TXPC_TXPC_ON1STSYNTHON_MASK              0x00000020
+#define TXPC_TXPC_ON1STSYNTHON_GET(x)            (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
+#define TXPC_TXPC_ON1STSYNTHON_SET(x)            (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
+#define TXPC_TXPC_SELINIT_MSB                    4
+#define TXPC_TXPC_SELINIT_LSB                    3
+#define TXPC_TXPC_SELINIT_MASK                   0x00000018
+#define TXPC_TXPC_SELINIT_GET(x)                 (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
+#define TXPC_TXPC_SELINIT_SET(x)                 (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
+#define TXPC_TXPC_SELCOUNT_MSB                   2
+#define TXPC_TXPC_SELCOUNT_LSB                   2
+#define TXPC_TXPC_SELCOUNT_MASK                  0x00000004
+#define TXPC_TXPC_SELCOUNT_GET(x)                (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
+#define TXPC_TXPC_SELCOUNT_SET(x)                (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
+#define TXPC_TXPC_ATBSEL_MSB                     1
+#define TXPC_TXPC_ATBSEL_LSB                     0
+#define TXPC_TXPC_ATBSEL_MASK                    0x00000003
+#define TXPC_TXPC_ATBSEL_GET(x)                  (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
+#define TXPC_TXPC_ATBSEL_SET(x)                  (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
+
+#define TXPC_MISC_ADDRESS                        0x0000004c
+#define TXPC_MISC_OFFSET                         0x0000004c
+#define TXPC_MISC_FLIPBMODE_MSB                  31
+#define TXPC_MISC_FLIPBMODE_LSB                  31
+#define TXPC_MISC_FLIPBMODE_MASK                 0x80000000
+#define TXPC_MISC_FLIPBMODE_GET(x)               (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
+#define TXPC_MISC_FLIPBMODE_SET(x)               (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
+#define TXPC_MISC_LEVEL_MSB                      30
+#define TXPC_MISC_LEVEL_LSB                      29
+#define TXPC_MISC_LEVEL_MASK                     0x60000000
+#define TXPC_MISC_LEVEL_GET(x)                   (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
+#define TXPC_MISC_LEVEL_SET(x)                   (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
+#define TXPC_MISC_LDO_TEST_MODE_MSB              28
+#define TXPC_MISC_LDO_TEST_MODE_LSB              28
+#define TXPC_MISC_LDO_TEST_MODE_MASK             0x10000000
+#define TXPC_MISC_LDO_TEST_MODE_GET(x)           (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
+#define TXPC_MISC_LDO_TEST_MODE_SET(x)           (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
+#define TXPC_MISC_NOTCXODET_MSB                  27
+#define TXPC_MISC_NOTCXODET_LSB                  27
+#define TXPC_MISC_NOTCXODET_MASK                 0x08000000
+#define TXPC_MISC_NOTCXODET_GET(x)               (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
+#define TXPC_MISC_NOTCXODET_SET(x)               (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
+#define TXPC_MISC_PWDCLKIND_MSB                  26
+#define TXPC_MISC_PWDCLKIND_LSB                  26
+#define TXPC_MISC_PWDCLKIND_MASK                 0x04000000
+#define TXPC_MISC_PWDCLKIND_GET(x)               (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
+#define TXPC_MISC_PWDCLKIND_SET(x)               (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
+#define TXPC_MISC_PWDXINPAD_MSB                  25
+#define TXPC_MISC_PWDXINPAD_LSB                  25
+#define TXPC_MISC_PWDXINPAD_MASK                 0x02000000
+#define TXPC_MISC_PWDXINPAD_GET(x)               (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
+#define TXPC_MISC_PWDXINPAD_SET(x)               (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
+#define TXPC_MISC_LOCALBIAS_MSB                  24
+#define TXPC_MISC_LOCALBIAS_LSB                  24
+#define TXPC_MISC_LOCALBIAS_MASK                 0x01000000
+#define TXPC_MISC_LOCALBIAS_GET(x)               (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
+#define TXPC_MISC_LOCALBIAS_SET(x)               (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
+#define TXPC_MISC_LOCALBIAS2X_MSB                23
+#define TXPC_MISC_LOCALBIAS2X_LSB                23
+#define TXPC_MISC_LOCALBIAS2X_MASK               0x00800000
+#define TXPC_MISC_LOCALBIAS2X_GET(x)             (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
+#define TXPC_MISC_LOCALBIAS2X_SET(x)             (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
+#define TXPC_MISC_SELTSP_MSB                     22
+#define TXPC_MISC_SELTSP_LSB                     22
+#define TXPC_MISC_SELTSP_MASK                    0x00400000
+#define TXPC_MISC_SELTSP_GET(x)                  (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
+#define TXPC_MISC_SELTSP_SET(x)                  (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
+#define TXPC_MISC_SELTSN_MSB                     21
+#define TXPC_MISC_SELTSN_LSB                     21
+#define TXPC_MISC_SELTSN_MASK                    0x00200000
+#define TXPC_MISC_SELTSN_GET(x)                  (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
+#define TXPC_MISC_SELTSN_SET(x)                  (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
+#define TXPC_MISC_SPARE_A_MSB                    20
+#define TXPC_MISC_SPARE_A_LSB                    18
+#define TXPC_MISC_SPARE_A_MASK                   0x001c0000
+#define TXPC_MISC_SPARE_A_GET(x)                 (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
+#define TXPC_MISC_SPARE_A_SET(x)                 (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
+#define TXPC_MISC_DECOUT_MSB                     17
+#define TXPC_MISC_DECOUT_LSB                     8
+#define TXPC_MISC_DECOUT_MASK                    0x0003ff00
+#define TXPC_MISC_DECOUT_GET(x)                  (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
+#define TXPC_MISC_DECOUT_SET(x)                  (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
+#define TXPC_MISC_XTALDIV_MSB                    7
+#define TXPC_MISC_XTALDIV_LSB                    6
+#define TXPC_MISC_XTALDIV_MASK                   0x000000c0
+#define TXPC_MISC_XTALDIV_GET(x)                 (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
+#define TXPC_MISC_XTALDIV_SET(x)                 (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
+#define TXPC_MISC_SPARE_MSB                      5
+#define TXPC_MISC_SPARE_LSB                      0
+#define TXPC_MISC_SPARE_MASK                     0x0000003f
+#define TXPC_MISC_SPARE_GET(x)                   (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
+#define TXPC_MISC_SPARE_SET(x)                   (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
+
+#define RXTXBB_RXTXBB1_ADDRESS                   0x00000050
+#define RXTXBB_RXTXBB1_OFFSET                    0x00000050
+#define RXTXBB_RXTXBB1_SPARE_MSB                 31
+#define RXTXBB_RXTXBB1_SPARE_LSB                 19
+#define RXTXBB_RXTXBB1_SPARE_MASK                0xfff80000
+#define RXTXBB_RXTXBB1_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
+#define RXTXBB_RXTXBB1_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
+#define RXTXBB_RXTXBB1_FNOTCH_MSB                18
+#define RXTXBB_RXTXBB1_FNOTCH_LSB                17
+#define RXTXBB_RXTXBB1_FNOTCH_MASK               0x00060000
+#define RXTXBB_RXTXBB1_FNOTCH_GET(x)             (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
+#define RXTXBB_RXTXBB1_FNOTCH_SET(x)             (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
+#define RXTXBB_RXTXBB1_SEL_ATB_MSB               16
+#define RXTXBB_RXTXBB1_SEL_ATB_LSB               9
+#define RXTXBB_RXTXBB1_SEL_ATB_MASK              0x0001fe00
+#define RXTXBB_RXTXBB1_SEL_ATB_GET(x)            (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
+#define RXTXBB_RXTXBB1_SEL_ATB_SET(x)            (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK       0x00000100
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x)     (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x)     (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
+#define RXTXBB_RXTXBB1_PDV2I_MSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_LSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_MASK                0x00000080
+#define RXTXBB_RXTXBB1_PDV2I_GET(x)              (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
+#define RXTXBB_RXTXBB1_PDV2I_SET(x)              (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
+#define RXTXBB_RXTXBB1_PDI2V_MSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_LSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_MASK                0x00000040
+#define RXTXBB_RXTXBB1_PDI2V_GET(x)              (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
+#define RXTXBB_RXTXBB1_PDI2V_SET(x)              (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
+#define RXTXBB_RXTXBB1_PDRXTXBB_MSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_LSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_MASK             0x00000020
+#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x)           (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
+#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x)           (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK          0x00000010
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK          0x00000008
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK          0x00000004
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
+#define RXTXBB_RXTXBB1_PDLOQ_MSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_LSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_MASK                0x00000002
+#define RXTXBB_RXTXBB1_PDLOQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDLOQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDHIQ_MSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_LSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_MASK                0x00000001
+#define RXTXBB_RXTXBB1_PDHIQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDHIQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
+
+#define RXTXBB_RXTXBB2_ADDRESS                   0x00000054
+#define RXTXBB_RXTXBB2_OFFSET                    0x00000054
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB    31
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB    29
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK   0xe0000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB    28
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB    26
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK   0x1c000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB   25
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB   23
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK  0x03800000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
+#define RXTXBB_RXTXBB2_SPARE_MSB                 22
+#define RXTXBB_RXTXBB2_SPARE_LSB                 21
+#define RXTXBB_RXTXBB2_SPARE_MASK                0x00600000
+#define RXTXBB_RXTXBB2_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
+#define RXTXBB_RXTXBB2_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK          0x00100000
+#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x)        (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x)        (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SELBUFFER_MSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_LSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_MASK            0x00080000
+#define RXTXBB_RXTXBB2_SELBUFFER_GET(x)          (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SELBUFFER_SET(x)          (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK         0x00040000
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK         0x00020000
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK         0x00010000
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK         0x00008000
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
+#define RXTXBB_RXTXBB2_CMSEL_MSB                 14
+#define RXTXBB_RXTXBB2_CMSEL_LSB                 13
+#define RXTXBB_RXTXBB2_CMSEL_MASK                0x00006000
+#define RXTXBB_RXTXBB2_CMSEL_GET(x)              (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
+#define RXTXBB_RXTXBB2_CMSEL_SET(x)              (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
+#define RXTXBB_RXTXBB2_FILTERFC_MSB              12
+#define RXTXBB_RXTXBB2_FILTERFC_LSB              8
+#define RXTXBB_RXTXBB2_FILTERFC_MASK             0x00001f00
+#define RXTXBB_RXTXBB2_FILTERFC_GET(x)           (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
+#define RXTXBB_RXTXBB2_FILTERFC_SET(x)           (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK    0x00000080
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x)  (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x)  (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK       0x00000040
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x)     (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x)     (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK          0x00000020
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK          0x00000010
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK          0x00000008
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK          0x00000004
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK          0x00000002
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK        0x00000001
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x)      (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x)      (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
+
+#define RXTXBB_RXTXBB3_ADDRESS                   0x00000058
+#define RXTXBB_RXTXBB3_OFFSET                    0x00000058
+#define RXTXBB_RXTXBB3_SPARE_MSB                 31
+#define RXTXBB_RXTXBB3_SPARE_LSB                 27
+#define RXTXBB_RXTXBB3_SPARE_MASK                0xf8000000
+#define RXTXBB_RXTXBB3_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
+#define RXTXBB_RXTXBB3_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB    23
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB    21
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK   0x00e00000
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB      20
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB      18
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK     0x001c0000
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB      17
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB      15
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK     0x00038000
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB      14
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB      12
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK     0x00007000
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB      11
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB      9
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK     0x00000e00
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB      8
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB      6
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK     0x000001c0
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB     5
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB     3
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK    0x00000038
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x)  (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x)  (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB    2
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB    0
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK   0x00000007
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
+
+#define RXTXBB_RXTXBB4_ADDRESS                   0x0000005c
+#define RXTXBB_RXTXBB4_OFFSET                    0x0000005c
+#define RXTXBB_RXTXBB4_SPARE_MSB                 31
+#define RXTXBB_RXTXBB4_SPARE_LSB                 31
+#define RXTXBB_RXTXBB4_SPARE_MASK                0x80000000
+#define RXTXBB_RXTXBB4_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
+#define RXTXBB_RXTXBB4_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK          0x40000000
+#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x)        (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x)        (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB           29
+#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB           25
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK          0x3e000000
+#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB           24
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB           20
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK          0x01f00000
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB           19
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB           15
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK          0x000f8000
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB           14
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB           10
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK          0x00007c00
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB          9
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB          5
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK         0x000003e0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB          4
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB          0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK         0x0000001f
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
+
+#define ADDAC_ADDAC1_ADDRESS                     0x00000060
+#define ADDAC_ADDAC1_OFFSET                      0x00000060
+#define ADDAC_ADDAC1_PLL_SVREG_MSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_LSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_MASK              0x80000000
+#define ADDAC_ADDAC1_PLL_SVREG_GET(x)            (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
+#define ADDAC_ADDAC1_PLL_SVREG_SET(x)            (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
+#define ADDAC_ADDAC1_PLL_SCLAMP_MSB              30
+#define ADDAC_ADDAC1_PLL_SCLAMP_LSB              28
+#define ADDAC_ADDAC1_PLL_SCLAMP_MASK             0x70000000
+#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x)           (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
+#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x)           (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
+#define ADDAC_ADDAC1_PLL_ATB_MSB                 27
+#define ADDAC_ADDAC1_PLL_ATB_LSB                 26
+#define ADDAC_ADDAC1_PLL_ATB_MASK                0x0c000000
+#define ADDAC_ADDAC1_PLL_ATB_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
+#define ADDAC_ADDAC1_PLL_ATB_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
+#define ADDAC_ADDAC1_PLL_ICP_MSB                 25
+#define ADDAC_ADDAC1_PLL_ICP_LSB                 23
+#define ADDAC_ADDAC1_PLL_ICP_MASK                0x03800000
+#define ADDAC_ADDAC1_PLL_ICP_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
+#define ADDAC_ADDAC1_PLL_ICP_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
+#define ADDAC_ADDAC1_PLL_FILTER_MSB              22
+#define ADDAC_ADDAC1_PLL_FILTER_LSB              15
+#define ADDAC_ADDAC1_PLL_FILTER_MASK             0x007f8000
+#define ADDAC_ADDAC1_PLL_FILTER_GET(x)           (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
+#define ADDAC_ADDAC1_PLL_FILTER_SET(x)           (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
+#define ADDAC_ADDAC1_PWDPLL_MSB                  14
+#define ADDAC_ADDAC1_PWDPLL_LSB                  14
+#define ADDAC_ADDAC1_PWDPLL_MASK                 0x00004000
+#define ADDAC_ADDAC1_PWDPLL_GET(x)               (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
+#define ADDAC_ADDAC1_PWDPLL_SET(x)               (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
+#define ADDAC_ADDAC1_PWDADC_MSB                  13
+#define ADDAC_ADDAC1_PWDADC_LSB                  13
+#define ADDAC_ADDAC1_PWDADC_MASK                 0x00002000
+#define ADDAC_ADDAC1_PWDADC_GET(x)               (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
+#define ADDAC_ADDAC1_PWDADC_SET(x)               (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
+#define ADDAC_ADDAC1_PWDDAC_MSB                  12
+#define ADDAC_ADDAC1_PWDDAC_LSB                  12
+#define ADDAC_ADDAC1_PWDDAC_MASK                 0x00001000
+#define ADDAC_ADDAC1_PWDDAC_GET(x)               (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
+#define ADDAC_ADDAC1_PWDDAC_SET(x)               (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
+#define ADDAC_ADDAC1_FORCEMSBLOW_MSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_LSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_MASK            0x00000800
+#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x)          (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
+#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x)          (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
+#define ADDAC_ADDAC1_SELMANPWDS_MSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_LSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_MASK             0x00000400
+#define ADDAC_ADDAC1_SELMANPWDS_GET(x)           (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
+#define ADDAC_ADDAC1_SELMANPWDS_SET(x)           (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK         0x00000200
+#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x)       (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x)       (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
+#define ADDAC_ADDAC1_CM_SEL_MSB                  8
+#define ADDAC_ADDAC1_CM_SEL_LSB                  7
+#define ADDAC_ADDAC1_CM_SEL_MASK                 0x00000180
+#define ADDAC_ADDAC1_CM_SEL_GET(x)               (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
+#define ADDAC_ADDAC1_CM_SEL_SET(x)               (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK        0x00000040
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x)      (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x)      (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
+#define ADDAC_ADDAC1_SPARE_MSB                   5
+#define ADDAC_ADDAC1_SPARE_LSB                   0
+#define ADDAC_ADDAC1_SPARE_MASK                  0x0000003f
+#define ADDAC_ADDAC1_SPARE_GET(x)                (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
+#define ADDAC_ADDAC1_SPARE_SET(x)                (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_reg_reg_s {
+  volatile unsigned int synth_synth1;
+  volatile unsigned int synth_synth2;
+  volatile unsigned int synth_synth3;
+  volatile unsigned int synth_synth4;
+  volatile unsigned int synth_synth5;
+  volatile unsigned int synth_synth6;
+  volatile unsigned int synth_synth7;
+  volatile unsigned int synth_synth8;
+  volatile unsigned int rf5g_rf5g1;
+  volatile unsigned int rf5g_rf5g2;
+  volatile unsigned int rf2g_rf2g1;
+  volatile unsigned int rf2g_rf2g2;
+  volatile unsigned int top_gain;
+  volatile unsigned int top_top;
+  volatile unsigned int bias_bias_sel;
+  volatile unsigned int bias_bias1;
+  volatile unsigned int bias_bias2;
+  volatile unsigned int bias_bias3;
+  volatile unsigned int txpc_txpc;
+  volatile unsigned int txpc_misc;
+  volatile unsigned int rxtxbb_rxtxbb1;
+  volatile unsigned int rxtxbb_rxtxbb2;
+  volatile unsigned int rxtxbb_rxtxbb3;
+  volatile unsigned int rxtxbb_rxtxbb4;
+  volatile unsigned int addac_addac1;
+} analog_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h
new file mode 100644
index 000000000000..bba885ed1f08
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h
@@ -0,0 +1,32 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_MAP_H_
+#define _APB_MAP_H_
+
+#define RTC_BASE_ADDRESS                         0x00004000
+#define VMC_BASE_ADDRESS                         0x00008000
+#define UART_BASE_ADDRESS                        0x0000c000
+#define SI_BASE_ADDRESS                          0x00010000
+#define GPIO_BASE_ADDRESS                        0x00014000
+#define MBOX_BASE_ADDRESS                        0x00018000
+#define ANALOG_INTF_BASE_ADDRESS                 0x0001c000
+#define MAC_BASE_ADDRESS                         0x00020000
+
+#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h
new file mode 100644
index 000000000000..de88e8cc91bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h
@@ -0,0 +1,996 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_OUT_ADDRESS                         0x00000000
+#define GPIO_OUT_OFFSET                          0x00000000
+#define GPIO_OUT_DATA_MSB                        17
+#define GPIO_OUT_DATA_LSB                        0
+#define GPIO_OUT_DATA_MASK                       0x0003ffff
+#define GPIO_OUT_DATA_GET(x)                     (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
+#define GPIO_OUT_DATA_SET(x)                     (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
+
+#define GPIO_OUT_W1TS_ADDRESS                    0x00000004
+#define GPIO_OUT_W1TS_OFFSET                     0x00000004
+#define GPIO_OUT_W1TS_DATA_MSB                   17
+#define GPIO_OUT_W1TS_DATA_LSB                   0
+#define GPIO_OUT_W1TS_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TS_DATA_GET(x)                (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
+#define GPIO_OUT_W1TS_DATA_SET(x)                (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
+
+#define GPIO_OUT_W1TC_ADDRESS                    0x00000008
+#define GPIO_OUT_W1TC_OFFSET                     0x00000008
+#define GPIO_OUT_W1TC_DATA_MSB                   17
+#define GPIO_OUT_W1TC_DATA_LSB                   0
+#define GPIO_OUT_W1TC_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TC_DATA_GET(x)                (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
+#define GPIO_OUT_W1TC_DATA_SET(x)                (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
+
+#define GPIO_ENABLE_ADDRESS                      0x0000000c
+#define GPIO_ENABLE_OFFSET                       0x0000000c
+#define GPIO_ENABLE_DATA_MSB                     17
+#define GPIO_ENABLE_DATA_LSB                     0
+#define GPIO_ENABLE_DATA_MASK                    0x0003ffff
+#define GPIO_ENABLE_DATA_GET(x)                  (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
+#define GPIO_ENABLE_DATA_SET(x)                  (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
+
+#define GPIO_ENABLE_W1TS_ADDRESS                 0x00000010
+#define GPIO_ENABLE_W1TS_OFFSET                  0x00000010
+#define GPIO_ENABLE_W1TS_DATA_MSB                17
+#define GPIO_ENABLE_W1TS_DATA_LSB                0
+#define GPIO_ENABLE_W1TS_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TS_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
+#define GPIO_ENABLE_W1TS_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define GPIO_ENABLE_W1TC_ADDRESS                 0x00000014
+#define GPIO_ENABLE_W1TC_OFFSET                  0x00000014
+#define GPIO_ENABLE_W1TC_DATA_MSB                17
+#define GPIO_ENABLE_W1TC_DATA_LSB                0
+#define GPIO_ENABLE_W1TC_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TC_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
+#define GPIO_ENABLE_W1TC_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define GPIO_IN_ADDRESS                          0x00000018
+#define GPIO_IN_OFFSET                           0x00000018
+#define GPIO_IN_DATA_MSB                         17
+#define GPIO_IN_DATA_LSB                         0
+#define GPIO_IN_DATA_MASK                        0x0003ffff
+#define GPIO_IN_DATA_GET(x)                      (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
+#define GPIO_IN_DATA_SET(x)                      (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
+
+#define GPIO_STATUS_ADDRESS                      0x0000001c
+#define GPIO_STATUS_OFFSET                       0x0000001c
+#define GPIO_STATUS_INTERRUPT_MSB                17
+#define GPIO_STATUS_INTERRUPT_LSB                0
+#define GPIO_STATUS_INTERRUPT_MASK               0x0003ffff
+#define GPIO_STATUS_INTERRUPT_GET(x)             (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
+#define GPIO_STATUS_INTERRUPT_SET(x)             (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TS_ADDRESS                 0x00000020
+#define GPIO_STATUS_W1TS_OFFSET                  0x00000020
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TC_ADDRESS                 0x00000024
+#define GPIO_STATUS_W1TC_OFFSET                  0x00000024
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define GPIO_PIN0_ADDRESS                        0x00000028
+#define GPIO_PIN0_OFFSET                         0x00000028
+#define GPIO_PIN0_CONFIG_MSB                     12
+#define GPIO_PIN0_CONFIG_LSB                     11
+#define GPIO_PIN0_CONFIG_MASK                    0x00001800
+#define GPIO_PIN0_CONFIG_GET(x)                  (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_CONFIG_SET(x)                  (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN0_INT_TYPE_MSB                   9
+#define GPIO_PIN0_INT_TYPE_LSB                   7
+#define GPIO_PIN0_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN0_INT_TYPE_GET(x)                (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
+#define GPIO_PIN0_INT_TYPE_SET(x)                (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
+#define GPIO_PIN0_PAD_DRIVER_MSB                 2
+#define GPIO_PIN0_PAD_DRIVER_LSB                 2
+#define GPIO_PIN0_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN0_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
+#define GPIO_PIN0_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
+#define GPIO_PIN0_SOURCE_MSB                     0
+#define GPIO_PIN0_SOURCE_LSB                     0
+#define GPIO_PIN0_SOURCE_MASK                    0x00000001
+#define GPIO_PIN0_SOURCE_GET(x)                  (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
+#define GPIO_PIN0_SOURCE_SET(x)                  (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
+
+#define GPIO_PIN1_ADDRESS                        0x0000002c
+#define GPIO_PIN1_OFFSET                         0x0000002c
+#define GPIO_PIN1_CONFIG_MSB                     12
+#define GPIO_PIN1_CONFIG_LSB                     11
+#define GPIO_PIN1_CONFIG_MASK                    0x00001800
+#define GPIO_PIN1_CONFIG_GET(x)                  (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
+#define GPIO_PIN1_CONFIG_SET(x)                  (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN1_INT_TYPE_MSB                   9
+#define GPIO_PIN1_INT_TYPE_LSB                   7
+#define GPIO_PIN1_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN1_INT_TYPE_GET(x)                (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
+#define GPIO_PIN1_INT_TYPE_SET(x)                (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
+#define GPIO_PIN1_PAD_DRIVER_MSB                 2
+#define GPIO_PIN1_PAD_DRIVER_LSB                 2
+#define GPIO_PIN1_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN1_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
+#define GPIO_PIN1_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
+#define GPIO_PIN1_SOURCE_MSB                     0
+#define GPIO_PIN1_SOURCE_LSB                     0
+#define GPIO_PIN1_SOURCE_MASK                    0x00000001
+#define GPIO_PIN1_SOURCE_GET(x)                  (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
+#define GPIO_PIN1_SOURCE_SET(x)                  (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
+
+#define GPIO_PIN2_ADDRESS                        0x00000030
+#define GPIO_PIN2_OFFSET                         0x00000030
+#define GPIO_PIN2_CONFIG_MSB                     12
+#define GPIO_PIN2_CONFIG_LSB                     11
+#define GPIO_PIN2_CONFIG_MASK                    0x00001800
+#define GPIO_PIN2_CONFIG_GET(x)                  (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
+#define GPIO_PIN2_CONFIG_SET(x)                  (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN2_INT_TYPE_MSB                   9
+#define GPIO_PIN2_INT_TYPE_LSB                   7
+#define GPIO_PIN2_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN2_INT_TYPE_GET(x)                (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
+#define GPIO_PIN2_INT_TYPE_SET(x)                (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
+#define GPIO_PIN2_PAD_DRIVER_MSB                 2
+#define GPIO_PIN2_PAD_DRIVER_LSB                 2
+#define GPIO_PIN2_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN2_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
+#define GPIO_PIN2_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
+#define GPIO_PIN2_SOURCE_MSB                     0
+#define GPIO_PIN2_SOURCE_LSB                     0
+#define GPIO_PIN2_SOURCE_MASK                    0x00000001
+#define GPIO_PIN2_SOURCE_GET(x)                  (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
+#define GPIO_PIN2_SOURCE_SET(x)                  (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
+
+#define GPIO_PIN3_ADDRESS                        0x00000034
+#define GPIO_PIN3_OFFSET                         0x00000034
+#define GPIO_PIN3_CONFIG_MSB                     12
+#define GPIO_PIN3_CONFIG_LSB                     11
+#define GPIO_PIN3_CONFIG_MASK                    0x00001800
+#define GPIO_PIN3_CONFIG_GET(x)                  (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
+#define GPIO_PIN3_CONFIG_SET(x)                  (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN3_INT_TYPE_MSB                   9
+#define GPIO_PIN3_INT_TYPE_LSB                   7
+#define GPIO_PIN3_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN3_INT_TYPE_GET(x)                (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
+#define GPIO_PIN3_INT_TYPE_SET(x)                (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
+#define GPIO_PIN3_PAD_DRIVER_MSB                 2
+#define GPIO_PIN3_PAD_DRIVER_LSB                 2
+#define GPIO_PIN3_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN3_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
+#define GPIO_PIN3_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
+#define GPIO_PIN3_SOURCE_MSB                     0
+#define GPIO_PIN3_SOURCE_LSB                     0
+#define GPIO_PIN3_SOURCE_MASK                    0x00000001
+#define GPIO_PIN3_SOURCE_GET(x)                  (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
+#define GPIO_PIN3_SOURCE_SET(x)                  (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
+
+#define GPIO_PIN4_ADDRESS                        0x00000038
+#define GPIO_PIN4_OFFSET                         0x00000038
+#define GPIO_PIN4_CONFIG_MSB                     12
+#define GPIO_PIN4_CONFIG_LSB                     11
+#define GPIO_PIN4_CONFIG_MASK                    0x00001800
+#define GPIO_PIN4_CONFIG_GET(x)                  (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
+#define GPIO_PIN4_CONFIG_SET(x)                  (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN4_INT_TYPE_MSB                   9
+#define GPIO_PIN4_INT_TYPE_LSB                   7
+#define GPIO_PIN4_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN4_INT_TYPE_GET(x)                (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
+#define GPIO_PIN4_INT_TYPE_SET(x)                (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
+#define GPIO_PIN4_PAD_DRIVER_MSB                 2
+#define GPIO_PIN4_PAD_DRIVER_LSB                 2
+#define GPIO_PIN4_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN4_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
+#define GPIO_PIN4_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
+#define GPIO_PIN4_SOURCE_MSB                     0
+#define GPIO_PIN4_SOURCE_LSB                     0
+#define GPIO_PIN4_SOURCE_MASK                    0x00000001
+#define GPIO_PIN4_SOURCE_GET(x)                  (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
+#define GPIO_PIN4_SOURCE_SET(x)                  (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
+
+#define GPIO_PIN5_ADDRESS                        0x0000003c
+#define GPIO_PIN5_OFFSET                         0x0000003c
+#define GPIO_PIN5_CONFIG_MSB                     12
+#define GPIO_PIN5_CONFIG_LSB                     11
+#define GPIO_PIN5_CONFIG_MASK                    0x00001800
+#define GPIO_PIN5_CONFIG_GET(x)                  (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
+#define GPIO_PIN5_CONFIG_SET(x)                  (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN5_INT_TYPE_MSB                   9
+#define GPIO_PIN5_INT_TYPE_LSB                   7
+#define GPIO_PIN5_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN5_INT_TYPE_GET(x)                (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
+#define GPIO_PIN5_INT_TYPE_SET(x)                (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
+#define GPIO_PIN5_PAD_DRIVER_MSB                 2
+#define GPIO_PIN5_PAD_DRIVER_LSB                 2
+#define GPIO_PIN5_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN5_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
+#define GPIO_PIN5_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
+#define GPIO_PIN5_SOURCE_MSB                     0
+#define GPIO_PIN5_SOURCE_LSB                     0
+#define GPIO_PIN5_SOURCE_MASK                    0x00000001
+#define GPIO_PIN5_SOURCE_GET(x)                  (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
+#define GPIO_PIN5_SOURCE_SET(x)                  (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
+
+#define GPIO_PIN6_ADDRESS                        0x00000040
+#define GPIO_PIN6_OFFSET                         0x00000040
+#define GPIO_PIN6_CONFIG_MSB                     12
+#define GPIO_PIN6_CONFIG_LSB                     11
+#define GPIO_PIN6_CONFIG_MASK                    0x00001800
+#define GPIO_PIN6_CONFIG_GET(x)                  (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
+#define GPIO_PIN6_CONFIG_SET(x)                  (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN6_INT_TYPE_MSB                   9
+#define GPIO_PIN6_INT_TYPE_LSB                   7
+#define GPIO_PIN6_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN6_INT_TYPE_GET(x)                (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
+#define GPIO_PIN6_INT_TYPE_SET(x)                (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
+#define GPIO_PIN6_PAD_DRIVER_MSB                 2
+#define GPIO_PIN6_PAD_DRIVER_LSB                 2
+#define GPIO_PIN6_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN6_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
+#define GPIO_PIN6_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
+#define GPIO_PIN6_SOURCE_MSB                     0
+#define GPIO_PIN6_SOURCE_LSB                     0
+#define GPIO_PIN6_SOURCE_MASK                    0x00000001
+#define GPIO_PIN6_SOURCE_GET(x)                  (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
+#define GPIO_PIN6_SOURCE_SET(x)                  (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
+
+#define GPIO_PIN7_ADDRESS                        0x00000044
+#define GPIO_PIN7_OFFSET                         0x00000044
+#define GPIO_PIN7_CONFIG_MSB                     12
+#define GPIO_PIN7_CONFIG_LSB                     11
+#define GPIO_PIN7_CONFIG_MASK                    0x00001800
+#define GPIO_PIN7_CONFIG_GET(x)                  (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
+#define GPIO_PIN7_CONFIG_SET(x)                  (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN7_INT_TYPE_MSB                   9
+#define GPIO_PIN7_INT_TYPE_LSB                   7
+#define GPIO_PIN7_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN7_INT_TYPE_GET(x)                (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
+#define GPIO_PIN7_INT_TYPE_SET(x)                (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
+#define GPIO_PIN7_PAD_DRIVER_MSB                 2
+#define GPIO_PIN7_PAD_DRIVER_LSB                 2
+#define GPIO_PIN7_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN7_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
+#define GPIO_PIN7_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
+#define GPIO_PIN7_SOURCE_MSB                     0
+#define GPIO_PIN7_SOURCE_LSB                     0
+#define GPIO_PIN7_SOURCE_MASK                    0x00000001
+#define GPIO_PIN7_SOURCE_GET(x)                  (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
+#define GPIO_PIN7_SOURCE_SET(x)                  (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
+
+#define GPIO_PIN8_ADDRESS                        0x00000048
+#define GPIO_PIN8_OFFSET                         0x00000048
+#define GPIO_PIN8_CONFIG_MSB                     12
+#define GPIO_PIN8_CONFIG_LSB                     11
+#define GPIO_PIN8_CONFIG_MASK                    0x00001800
+#define GPIO_PIN8_CONFIG_GET(x)                  (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
+#define GPIO_PIN8_CONFIG_SET(x)                  (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN8_INT_TYPE_MSB                   9
+#define GPIO_PIN8_INT_TYPE_LSB                   7
+#define GPIO_PIN8_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN8_INT_TYPE_GET(x)                (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
+#define GPIO_PIN8_INT_TYPE_SET(x)                (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
+#define GPIO_PIN8_PAD_DRIVER_MSB                 2
+#define GPIO_PIN8_PAD_DRIVER_LSB                 2
+#define GPIO_PIN8_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN8_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
+#define GPIO_PIN8_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
+#define GPIO_PIN8_SOURCE_MSB                     0
+#define GPIO_PIN8_SOURCE_LSB                     0
+#define GPIO_PIN8_SOURCE_MASK                    0x00000001
+#define GPIO_PIN8_SOURCE_GET(x)                  (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
+#define GPIO_PIN8_SOURCE_SET(x)                  (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
+
+#define GPIO_PIN9_ADDRESS                        0x0000004c
+#define GPIO_PIN9_OFFSET                         0x0000004c
+#define GPIO_PIN9_CONFIG_MSB                     12
+#define GPIO_PIN9_CONFIG_LSB                     11
+#define GPIO_PIN9_CONFIG_MASK                    0x00001800
+#define GPIO_PIN9_CONFIG_GET(x)                  (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
+#define GPIO_PIN9_CONFIG_SET(x)                  (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN9_INT_TYPE_MSB                   9
+#define GPIO_PIN9_INT_TYPE_LSB                   7
+#define GPIO_PIN9_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN9_INT_TYPE_GET(x)                (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
+#define GPIO_PIN9_INT_TYPE_SET(x)                (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
+#define GPIO_PIN9_PAD_DRIVER_MSB                 2
+#define GPIO_PIN9_PAD_DRIVER_LSB                 2
+#define GPIO_PIN9_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN9_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
+#define GPIO_PIN9_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
+#define GPIO_PIN9_SOURCE_MSB                     0
+#define GPIO_PIN9_SOURCE_LSB                     0
+#define GPIO_PIN9_SOURCE_MASK                    0x00000001
+#define GPIO_PIN9_SOURCE_GET(x)                  (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
+#define GPIO_PIN9_SOURCE_SET(x)                  (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
+
+#define GPIO_PIN10_ADDRESS                       0x00000050
+#define GPIO_PIN10_OFFSET                        0x00000050
+#define GPIO_PIN10_CONFIG_MSB                    12
+#define GPIO_PIN10_CONFIG_LSB                    11
+#define GPIO_PIN10_CONFIG_MASK                   0x00001800
+#define GPIO_PIN10_CONFIG_GET(x)                 (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
+#define GPIO_PIN10_CONFIG_SET(x)                 (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN10_INT_TYPE_MSB                  9
+#define GPIO_PIN10_INT_TYPE_LSB                  7
+#define GPIO_PIN10_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN10_INT_TYPE_GET(x)               (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
+#define GPIO_PIN10_INT_TYPE_SET(x)               (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
+#define GPIO_PIN10_PAD_DRIVER_MSB                2
+#define GPIO_PIN10_PAD_DRIVER_LSB                2
+#define GPIO_PIN10_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN10_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
+#define GPIO_PIN10_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
+#define GPIO_PIN10_SOURCE_MSB                    0
+#define GPIO_PIN10_SOURCE_LSB                    0
+#define GPIO_PIN10_SOURCE_MASK                   0x00000001
+#define GPIO_PIN10_SOURCE_GET(x)                 (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
+#define GPIO_PIN10_SOURCE_SET(x)                 (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
+
+#define GPIO_PIN11_ADDRESS                       0x00000054
+#define GPIO_PIN11_OFFSET                        0x00000054
+#define GPIO_PIN11_CONFIG_MSB                    12
+#define GPIO_PIN11_CONFIG_LSB                    11
+#define GPIO_PIN11_CONFIG_MASK                   0x00001800
+#define GPIO_PIN11_CONFIG_GET(x)                 (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
+#define GPIO_PIN11_CONFIG_SET(x)                 (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN11_INT_TYPE_MSB                  9
+#define GPIO_PIN11_INT_TYPE_LSB                  7
+#define GPIO_PIN11_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN11_INT_TYPE_GET(x)               (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
+#define GPIO_PIN11_INT_TYPE_SET(x)               (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
+#define GPIO_PIN11_PAD_DRIVER_MSB                2
+#define GPIO_PIN11_PAD_DRIVER_LSB                2
+#define GPIO_PIN11_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN11_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
+#define GPIO_PIN11_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
+#define GPIO_PIN11_SOURCE_MSB                    0
+#define GPIO_PIN11_SOURCE_LSB                    0
+#define GPIO_PIN11_SOURCE_MASK                   0x00000001
+#define GPIO_PIN11_SOURCE_GET(x)                 (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
+#define GPIO_PIN11_SOURCE_SET(x)                 (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
+
+#define GPIO_PIN12_ADDRESS                       0x00000058
+#define GPIO_PIN12_OFFSET                        0x00000058
+#define GPIO_PIN12_CONFIG_MSB                    12
+#define GPIO_PIN12_CONFIG_LSB                    11
+#define GPIO_PIN12_CONFIG_MASK                   0x00001800
+#define GPIO_PIN12_CONFIG_GET(x)                 (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
+#define GPIO_PIN12_CONFIG_SET(x)                 (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN12_INT_TYPE_MSB                  9
+#define GPIO_PIN12_INT_TYPE_LSB                  7
+#define GPIO_PIN12_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN12_INT_TYPE_GET(x)               (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
+#define GPIO_PIN12_INT_TYPE_SET(x)               (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
+#define GPIO_PIN12_PAD_DRIVER_MSB                2
+#define GPIO_PIN12_PAD_DRIVER_LSB                2
+#define GPIO_PIN12_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN12_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
+#define GPIO_PIN12_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
+#define GPIO_PIN12_SOURCE_MSB                    0
+#define GPIO_PIN12_SOURCE_LSB                    0
+#define GPIO_PIN12_SOURCE_MASK                   0x00000001
+#define GPIO_PIN12_SOURCE_GET(x)                 (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
+#define GPIO_PIN12_SOURCE_SET(x)                 (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
+
+#define GPIO_PIN13_ADDRESS                       0x0000005c
+#define GPIO_PIN13_OFFSET                        0x0000005c
+#define GPIO_PIN13_CONFIG_MSB                    12
+#define GPIO_PIN13_CONFIG_LSB                    11
+#define GPIO_PIN13_CONFIG_MASK                   0x00001800
+#define GPIO_PIN13_CONFIG_GET(x)                 (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
+#define GPIO_PIN13_CONFIG_SET(x)                 (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN13_INT_TYPE_MSB                  9
+#define GPIO_PIN13_INT_TYPE_LSB                  7
+#define GPIO_PIN13_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN13_INT_TYPE_GET(x)               (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
+#define GPIO_PIN13_INT_TYPE_SET(x)               (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
+#define GPIO_PIN13_PAD_DRIVER_MSB                2
+#define GPIO_PIN13_PAD_DRIVER_LSB                2
+#define GPIO_PIN13_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN13_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
+#define GPIO_PIN13_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
+#define GPIO_PIN13_SOURCE_MSB                    0
+#define GPIO_PIN13_SOURCE_LSB                    0
+#define GPIO_PIN13_SOURCE_MASK                   0x00000001
+#define GPIO_PIN13_SOURCE_GET(x)                 (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
+#define GPIO_PIN13_SOURCE_SET(x)                 (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
+
+#define GPIO_PIN14_ADDRESS                       0x00000060
+#define GPIO_PIN14_OFFSET                        0x00000060
+#define GPIO_PIN14_CONFIG_MSB                    12
+#define GPIO_PIN14_CONFIG_LSB                    11
+#define GPIO_PIN14_CONFIG_MASK                   0x00001800
+#define GPIO_PIN14_CONFIG_GET(x)                 (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
+#define GPIO_PIN14_CONFIG_SET(x)                 (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN14_INT_TYPE_MSB                  9
+#define GPIO_PIN14_INT_TYPE_LSB                  7
+#define GPIO_PIN14_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN14_INT_TYPE_GET(x)               (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
+#define GPIO_PIN14_INT_TYPE_SET(x)               (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
+#define GPIO_PIN14_PAD_DRIVER_MSB                2
+#define GPIO_PIN14_PAD_DRIVER_LSB                2
+#define GPIO_PIN14_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN14_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
+#define GPIO_PIN14_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
+#define GPIO_PIN14_SOURCE_MSB                    0
+#define GPIO_PIN14_SOURCE_LSB                    0
+#define GPIO_PIN14_SOURCE_MASK                   0x00000001
+#define GPIO_PIN14_SOURCE_GET(x)                 (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
+#define GPIO_PIN14_SOURCE_SET(x)                 (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
+
+#define GPIO_PIN15_ADDRESS                       0x00000064
+#define GPIO_PIN15_OFFSET                        0x00000064
+#define GPIO_PIN15_CONFIG_MSB                    12
+#define GPIO_PIN15_CONFIG_LSB                    11
+#define GPIO_PIN15_CONFIG_MASK                   0x00001800
+#define GPIO_PIN15_CONFIG_GET(x)                 (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
+#define GPIO_PIN15_CONFIG_SET(x)                 (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN15_INT_TYPE_MSB                  9
+#define GPIO_PIN15_INT_TYPE_LSB                  7
+#define GPIO_PIN15_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN15_INT_TYPE_GET(x)               (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
+#define GPIO_PIN15_INT_TYPE_SET(x)               (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
+#define GPIO_PIN15_PAD_DRIVER_MSB                2
+#define GPIO_PIN15_PAD_DRIVER_LSB                2
+#define GPIO_PIN15_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN15_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
+#define GPIO_PIN15_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
+#define GPIO_PIN15_SOURCE_MSB                    0
+#define GPIO_PIN15_SOURCE_LSB                    0
+#define GPIO_PIN15_SOURCE_MASK                   0x00000001
+#define GPIO_PIN15_SOURCE_GET(x)                 (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
+#define GPIO_PIN15_SOURCE_SET(x)                 (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
+
+#define GPIO_PIN16_ADDRESS                       0x00000068
+#define GPIO_PIN16_OFFSET                        0x00000068
+#define GPIO_PIN16_CONFIG_MSB                    12
+#define GPIO_PIN16_CONFIG_LSB                    11
+#define GPIO_PIN16_CONFIG_MASK                   0x00001800
+#define GPIO_PIN16_CONFIG_GET(x)                 (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
+#define GPIO_PIN16_CONFIG_SET(x)                 (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN16_INT_TYPE_MSB                  9
+#define GPIO_PIN16_INT_TYPE_LSB                  7
+#define GPIO_PIN16_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN16_INT_TYPE_GET(x)               (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
+#define GPIO_PIN16_INT_TYPE_SET(x)               (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
+#define GPIO_PIN16_PAD_DRIVER_MSB                2
+#define GPIO_PIN16_PAD_DRIVER_LSB                2
+#define GPIO_PIN16_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN16_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
+#define GPIO_PIN16_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
+#define GPIO_PIN16_SOURCE_MSB                    0
+#define GPIO_PIN16_SOURCE_LSB                    0
+#define GPIO_PIN16_SOURCE_MASK                   0x00000001
+#define GPIO_PIN16_SOURCE_GET(x)                 (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
+#define GPIO_PIN16_SOURCE_SET(x)                 (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
+
+#define GPIO_PIN17_ADDRESS                       0x0000006c
+#define GPIO_PIN17_OFFSET                        0x0000006c
+#define GPIO_PIN17_CONFIG_MSB                    12
+#define GPIO_PIN17_CONFIG_LSB                    11
+#define GPIO_PIN17_CONFIG_MASK                   0x00001800
+#define GPIO_PIN17_CONFIG_GET(x)                 (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
+#define GPIO_PIN17_CONFIG_SET(x)                 (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN17_INT_TYPE_MSB                  9
+#define GPIO_PIN17_INT_TYPE_LSB                  7
+#define GPIO_PIN17_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN17_INT_TYPE_GET(x)               (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
+#define GPIO_PIN17_INT_TYPE_SET(x)               (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
+#define GPIO_PIN17_PAD_DRIVER_MSB                2
+#define GPIO_PIN17_PAD_DRIVER_LSB                2
+#define GPIO_PIN17_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN17_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
+#define GPIO_PIN17_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
+#define GPIO_PIN17_SOURCE_MSB                    0
+#define GPIO_PIN17_SOURCE_LSB                    0
+#define GPIO_PIN17_SOURCE_MASK                   0x00000001
+#define GPIO_PIN17_SOURCE_GET(x)                 (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
+#define GPIO_PIN17_SOURCE_SET(x)                 (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
+
+#define SDIO_PIN_ADDRESS                         0x00000070
+#define SDIO_PIN_OFFSET                          0x00000070
+#define SDIO_PIN_PAD_PULL_MSB                    3
+#define SDIO_PIN_PAD_PULL_LSB                    2
+#define SDIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define SDIO_PIN_PAD_PULL_GET(x)                 (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
+#define SDIO_PIN_PAD_PULL_SET(x)                 (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
+#define SDIO_PIN_PAD_STRENGTH_MSB                1
+#define SDIO_PIN_PAD_STRENGTH_LSB                0
+#define SDIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define SDIO_PIN_PAD_STRENGTH_GET(x)             (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
+#define SDIO_PIN_PAD_STRENGTH_SET(x)             (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
+
+#define CLK_REQ_PIN_ADDRESS                      0x00000074
+#define CLK_REQ_PIN_OFFSET                       0x00000074
+#define CLK_REQ_PIN_ATE_OE_L_MSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_LSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_MASK                0x00000010
+#define CLK_REQ_PIN_ATE_OE_L_GET(x)              (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
+#define CLK_REQ_PIN_ATE_OE_L_SET(x)              (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
+#define CLK_REQ_PIN_PAD_PULL_MSB                 3
+#define CLK_REQ_PIN_PAD_PULL_LSB                 2
+#define CLK_REQ_PIN_PAD_PULL_MASK                0x0000000c
+#define CLK_REQ_PIN_PAD_PULL_GET(x)              (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
+#define CLK_REQ_PIN_PAD_PULL_SET(x)              (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
+#define CLK_REQ_PIN_PAD_STRENGTH_MSB             1
+#define CLK_REQ_PIN_PAD_STRENGTH_LSB             0
+#define CLK_REQ_PIN_PAD_STRENGTH_MASK            0x00000003
+#define CLK_REQ_PIN_PAD_STRENGTH_GET(x)          (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
+#define CLK_REQ_PIN_PAD_STRENGTH_SET(x)          (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
+
+#define SIGMA_DELTA_ADDRESS                      0x00000078
+#define SIGMA_DELTA_OFFSET                       0x00000078
+#define SIGMA_DELTA_ENABLE_MSB                   16
+#define SIGMA_DELTA_ENABLE_LSB                   16
+#define SIGMA_DELTA_ENABLE_MASK                  0x00010000
+#define SIGMA_DELTA_ENABLE_GET(x)                (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
+#define SIGMA_DELTA_ENABLE_SET(x)                (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
+#define SIGMA_DELTA_PRESCALAR_MSB                15
+#define SIGMA_DELTA_PRESCALAR_LSB                8
+#define SIGMA_DELTA_PRESCALAR_MASK               0x0000ff00
+#define SIGMA_DELTA_PRESCALAR_GET(x)             (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
+#define SIGMA_DELTA_PRESCALAR_SET(x)             (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
+#define SIGMA_DELTA_TARGET_MSB                   7
+#define SIGMA_DELTA_TARGET_LSB                   0
+#define SIGMA_DELTA_TARGET_MASK                  0x000000ff
+#define SIGMA_DELTA_TARGET_GET(x)                (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
+#define SIGMA_DELTA_TARGET_SET(x)                (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
+
+#define DEBUG_CONTROL_ADDRESS                    0x0000007c
+#define DEBUG_CONTROL_OFFSET                     0x0000007c
+#define DEBUG_CONTROL_OBS_OE_L_MSB               1
+#define DEBUG_CONTROL_OBS_OE_L_LSB               1
+#define DEBUG_CONTROL_OBS_OE_L_MASK              0x00000002
+#define DEBUG_CONTROL_OBS_OE_L_GET(x)            (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
+#define DEBUG_CONTROL_OBS_OE_L_SET(x)            (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
+#define DEBUG_CONTROL_ENABLE_MSB                 0
+#define DEBUG_CONTROL_ENABLE_LSB                 0
+#define DEBUG_CONTROL_ENABLE_MASK                0x00000001
+#define DEBUG_CONTROL_ENABLE_GET(x)              (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
+#define DEBUG_CONTROL_ENABLE_SET(x)              (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
+
+#define DEBUG_INPUT_SEL_ADDRESS                  0x00000080
+#define DEBUG_INPUT_SEL_OFFSET                   0x00000080
+#define DEBUG_INPUT_SEL_SRC_MSB                  3
+#define DEBUG_INPUT_SEL_SRC_LSB                  0
+#define DEBUG_INPUT_SEL_SRC_MASK                 0x0000000f
+#define DEBUG_INPUT_SEL_SRC_GET(x)               (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
+#define DEBUG_INPUT_SEL_SRC_SET(x)               (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
+
+#define DEBUG_OUT_ADDRESS                        0x00000084
+#define DEBUG_OUT_OFFSET                         0x00000084
+#define DEBUG_OUT_DATA_MSB                       17
+#define DEBUG_OUT_DATA_LSB                       0
+#define DEBUG_OUT_DATA_MASK                      0x0003ffff
+#define DEBUG_OUT_DATA_GET(x)                    (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
+#define DEBUG_OUT_DATA_SET(x)                    (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
+
+#define LA_CONTROL_ADDRESS                       0x00000088
+#define LA_CONTROL_OFFSET                        0x00000088
+#define LA_CONTROL_RUN_MSB                       1
+#define LA_CONTROL_RUN_LSB                       1
+#define LA_CONTROL_RUN_MASK                      0x00000002
+#define LA_CONTROL_RUN_GET(x)                    (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
+#define LA_CONTROL_RUN_SET(x)                    (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
+#define LA_CONTROL_TRIGGERED_MSB                 0
+#define LA_CONTROL_TRIGGERED_LSB                 0
+#define LA_CONTROL_TRIGGERED_MASK                0x00000001
+#define LA_CONTROL_TRIGGERED_GET(x)              (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
+#define LA_CONTROL_TRIGGERED_SET(x)              (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
+
+#define LA_CLOCK_ADDRESS                         0x0000008c
+#define LA_CLOCK_OFFSET                          0x0000008c
+#define LA_CLOCK_DIV_MSB                         7
+#define LA_CLOCK_DIV_LSB                         0
+#define LA_CLOCK_DIV_MASK                        0x000000ff
+#define LA_CLOCK_DIV_GET(x)                      (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
+#define LA_CLOCK_DIV_SET(x)                      (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
+
+#define LA_STATUS_ADDRESS                        0x00000090
+#define LA_STATUS_OFFSET                         0x00000090
+#define LA_STATUS_INTERRUPT_MSB                  0
+#define LA_STATUS_INTERRUPT_LSB                  0
+#define LA_STATUS_INTERRUPT_MASK                 0x00000001
+#define LA_STATUS_INTERRUPT_GET(x)               (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
+#define LA_STATUS_INTERRUPT_SET(x)               (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
+
+#define LA_TRIGGER_SAMPLE_ADDRESS                0x00000094
+#define LA_TRIGGER_SAMPLE_OFFSET                 0x00000094
+#define LA_TRIGGER_SAMPLE_COUNT_MSB              15
+#define LA_TRIGGER_SAMPLE_COUNT_LSB              0
+#define LA_TRIGGER_SAMPLE_COUNT_MASK             0x0000ffff
+#define LA_TRIGGER_SAMPLE_COUNT_GET(x)           (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
+#define LA_TRIGGER_SAMPLE_COUNT_SET(x)           (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
+
+#define LA_TRIGGER_POSITION_ADDRESS              0x00000098
+#define LA_TRIGGER_POSITION_OFFSET               0x00000098
+#define LA_TRIGGER_POSITION_VALUE_MSB            15
+#define LA_TRIGGER_POSITION_VALUE_LSB            0
+#define LA_TRIGGER_POSITION_VALUE_MASK           0x0000ffff
+#define LA_TRIGGER_POSITION_VALUE_GET(x)         (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
+#define LA_TRIGGER_POSITION_VALUE_SET(x)         (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
+
+#define LA_PRE_TRIGGER_ADDRESS                   0x0000009c
+#define LA_PRE_TRIGGER_OFFSET                    0x0000009c
+#define LA_PRE_TRIGGER_COUNT_MSB                 15
+#define LA_PRE_TRIGGER_COUNT_LSB                 0
+#define LA_PRE_TRIGGER_COUNT_MASK                0x0000ffff
+#define LA_PRE_TRIGGER_COUNT_GET(x)              (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
+#define LA_PRE_TRIGGER_COUNT_SET(x)              (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
+
+#define LA_POST_TRIGGER_ADDRESS                  0x000000a0
+#define LA_POST_TRIGGER_OFFSET                   0x000000a0
+#define LA_POST_TRIGGER_COUNT_MSB                15
+#define LA_POST_TRIGGER_COUNT_LSB                0
+#define LA_POST_TRIGGER_COUNT_MASK               0x0000ffff
+#define LA_POST_TRIGGER_COUNT_GET(x)             (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
+#define LA_POST_TRIGGER_COUNT_SET(x)             (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
+
+#define LA_FILTER_CONTROL_ADDRESS                0x000000a4
+#define LA_FILTER_CONTROL_OFFSET                 0x000000a4
+#define LA_FILTER_CONTROL_DELTA_MSB              0
+#define LA_FILTER_CONTROL_DELTA_LSB              0
+#define LA_FILTER_CONTROL_DELTA_MASK             0x00000001
+#define LA_FILTER_CONTROL_DELTA_GET(x)           (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
+#define LA_FILTER_CONTROL_DELTA_SET(x)           (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
+
+#define LA_FILTER_DATA_ADDRESS                   0x000000a8
+#define LA_FILTER_DATA_OFFSET                    0x000000a8
+#define LA_FILTER_DATA_MATCH_MSB                 17
+#define LA_FILTER_DATA_MATCH_LSB                 0
+#define LA_FILTER_DATA_MATCH_MASK                0x0003ffff
+#define LA_FILTER_DATA_MATCH_GET(x)              (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
+#define LA_FILTER_DATA_MATCH_SET(x)              (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
+
+#define LA_FILTER_WILDCARD_ADDRESS               0x000000ac
+#define LA_FILTER_WILDCARD_OFFSET                0x000000ac
+#define LA_FILTER_WILDCARD_MATCH_MSB             17
+#define LA_FILTER_WILDCARD_MATCH_LSB             0
+#define LA_FILTER_WILDCARD_MATCH_MASK            0x0003ffff
+#define LA_FILTER_WILDCARD_MATCH_GET(x)          (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
+#define LA_FILTER_WILDCARD_MATCH_SET(x)          (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERA_DATA_ADDRESS                 0x000000b0
+#define LA_TRIGGERA_DATA_OFFSET                  0x000000b0
+#define LA_TRIGGERA_DATA_MATCH_MSB               17
+#define LA_TRIGGERA_DATA_MATCH_LSB               0
+#define LA_TRIGGERA_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERA_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
+#define LA_TRIGGERA_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
+
+#define LA_TRIGGERA_WILDCARD_ADDRESS             0x000000b4
+#define LA_TRIGGERA_WILDCARD_OFFSET              0x000000b4
+#define LA_TRIGGERA_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERA_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERA_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERA_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERA_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERB_DATA_ADDRESS                 0x000000b8
+#define LA_TRIGGERB_DATA_OFFSET                  0x000000b8
+#define LA_TRIGGERB_DATA_MATCH_MSB               17
+#define LA_TRIGGERB_DATA_MATCH_LSB               0
+#define LA_TRIGGERB_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERB_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
+#define LA_TRIGGERB_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
+
+#define LA_TRIGGERB_WILDCARD_ADDRESS             0x000000bc
+#define LA_TRIGGERB_WILDCARD_OFFSET              0x000000bc
+#define LA_TRIGGERB_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERB_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERB_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERB_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERB_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGER_ADDRESS                       0x000000c0
+#define LA_TRIGGER_OFFSET                        0x000000c0
+#define LA_TRIGGER_EVENT_MSB                     2
+#define LA_TRIGGER_EVENT_LSB                     0
+#define LA_TRIGGER_EVENT_MASK                    0x00000007
+#define LA_TRIGGER_EVENT_GET(x)                  (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
+#define LA_TRIGGER_EVENT_SET(x)                  (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
+
+#define LA_FIFO_ADDRESS                          0x000000c4
+#define LA_FIFO_OFFSET                           0x000000c4
+#define LA_FIFO_FULL_MSB                         1
+#define LA_FIFO_FULL_LSB                         1
+#define LA_FIFO_FULL_MASK                        0x00000002
+#define LA_FIFO_FULL_GET(x)                      (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
+#define LA_FIFO_FULL_SET(x)                      (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
+#define LA_FIFO_EMPTY_MSB                        0
+#define LA_FIFO_EMPTY_LSB                        0
+#define LA_FIFO_EMPTY_MASK                       0x00000001
+#define LA_FIFO_EMPTY_GET(x)                     (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
+#define LA_FIFO_EMPTY_SET(x)                     (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
+
+#define LA_ADDRESS                               0x000000c8
+#define LA_OFFSET                                0x000000c8
+#define LA_DATA_MSB                              17
+#define LA_DATA_LSB                              0
+#define LA_DATA_MASK                             0x0003ffff
+#define LA_DATA_GET(x)                           (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
+#define LA_DATA_SET(x)                           (((x) << LA_DATA_LSB) & LA_DATA_MASK)
+
+#define ANT_PIN_ADDRESS                          0x000000d0
+#define ANT_PIN_OFFSET                           0x000000d0
+#define ANT_PIN_PAD_PULL_MSB                     3
+#define ANT_PIN_PAD_PULL_LSB                     2
+#define ANT_PIN_PAD_PULL_MASK                    0x0000000c
+#define ANT_PIN_PAD_PULL_GET(x)                  (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
+#define ANT_PIN_PAD_PULL_SET(x)                  (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
+#define ANT_PIN_PAD_STRENGTH_MSB                 1
+#define ANT_PIN_PAD_STRENGTH_LSB                 0
+#define ANT_PIN_PAD_STRENGTH_MASK                0x00000003
+#define ANT_PIN_PAD_STRENGTH_GET(x)              (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
+#define ANT_PIN_PAD_STRENGTH_SET(x)              (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
+
+#define ANTD_PIN_ADDRESS                         0x000000d4
+#define ANTD_PIN_OFFSET                          0x000000d4
+#define ANTD_PIN_PAD_PULL_MSB                    1
+#define ANTD_PIN_PAD_PULL_LSB                    0
+#define ANTD_PIN_PAD_PULL_MASK                   0x00000003
+#define ANTD_PIN_PAD_PULL_GET(x)                 (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
+#define ANTD_PIN_PAD_PULL_SET(x)                 (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
+
+#define GPIO_PIN_ADDRESS                         0x000000d8
+#define GPIO_PIN_OFFSET                          0x000000d8
+#define GPIO_PIN_PAD_PULL_MSB                    3
+#define GPIO_PIN_PAD_PULL_LSB                    2
+#define GPIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define GPIO_PIN_PAD_PULL_GET(x)                 (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
+#define GPIO_PIN_PAD_PULL_SET(x)                 (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
+#define GPIO_PIN_PAD_STRENGTH_MSB                1
+#define GPIO_PIN_PAD_STRENGTH_LSB                0
+#define GPIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define GPIO_PIN_PAD_STRENGTH_GET(x)             (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
+#define GPIO_PIN_PAD_STRENGTH_SET(x)             (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
+
+#define GPIO_H_PIN_ADDRESS                       0x000000dc
+#define GPIO_H_PIN_OFFSET                        0x000000dc
+#define GPIO_H_PIN_PAD_PULL_MSB                  1
+#define GPIO_H_PIN_PAD_PULL_LSB                  0
+#define GPIO_H_PIN_PAD_PULL_MASK                 0x00000003
+#define GPIO_H_PIN_PAD_PULL_GET(x)               (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
+#define GPIO_H_PIN_PAD_PULL_SET(x)               (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
+
+#define BT_PIN_ADDRESS                           0x000000e0
+#define BT_PIN_OFFSET                            0x000000e0
+#define BT_PIN_PAD_PULL_MSB                      3
+#define BT_PIN_PAD_PULL_LSB                      2
+#define BT_PIN_PAD_PULL_MASK                     0x0000000c
+#define BT_PIN_PAD_PULL_GET(x)                   (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
+#define BT_PIN_PAD_PULL_SET(x)                   (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
+#define BT_PIN_PAD_STRENGTH_MSB                  1
+#define BT_PIN_PAD_STRENGTH_LSB                  0
+#define BT_PIN_PAD_STRENGTH_MASK                 0x00000003
+#define BT_PIN_PAD_STRENGTH_GET(x)               (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
+#define BT_PIN_PAD_STRENGTH_SET(x)               (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
+
+#define BT_WLAN_PIN_ADDRESS                      0x000000e4
+#define BT_WLAN_PIN_OFFSET                       0x000000e4
+#define BT_WLAN_PIN_PAD_PULL_MSB                 1
+#define BT_WLAN_PIN_PAD_PULL_LSB                 0
+#define BT_WLAN_PIN_PAD_PULL_MASK                0x00000003
+#define BT_WLAN_PIN_PAD_PULL_GET(x)              (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
+#define BT_WLAN_PIN_PAD_PULL_SET(x)              (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
+
+#define SI_UART_PIN_ADDRESS                      0x000000e8
+#define SI_UART_PIN_OFFSET                       0x000000e8
+#define SI_UART_PIN_PAD_PULL_MSB                 3
+#define SI_UART_PIN_PAD_PULL_LSB                 2
+#define SI_UART_PIN_PAD_PULL_MASK                0x0000000c
+#define SI_UART_PIN_PAD_PULL_GET(x)              (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
+#define SI_UART_PIN_PAD_PULL_SET(x)              (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
+#define SI_UART_PIN_PAD_STRENGTH_MSB             1
+#define SI_UART_PIN_PAD_STRENGTH_LSB             0
+#define SI_UART_PIN_PAD_STRENGTH_MASK            0x00000003
+#define SI_UART_PIN_PAD_STRENGTH_GET(x)          (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
+#define SI_UART_PIN_PAD_STRENGTH_SET(x)          (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
+
+#define CLK32K_PIN_ADDRESS                       0x000000ec
+#define CLK32K_PIN_OFFSET                        0x000000ec
+#define CLK32K_PIN_PAD_PULL_MSB                  1
+#define CLK32K_PIN_PAD_PULL_LSB                  0
+#define CLK32K_PIN_PAD_PULL_MASK                 0x00000003
+#define CLK32K_PIN_PAD_PULL_GET(x)               (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
+#define CLK32K_PIN_PAD_PULL_SET(x)               (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
+
+#define RESET_TUPLE_STATUS_ADDRESS               0x000000f0
+#define RESET_TUPLE_STATUS_OFFSET                0x000000f0
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB  11
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB  8
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB   7
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB   0
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK  0x000000ff
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_reg_reg_s {
+  volatile unsigned int gpio_out;
+  volatile unsigned int gpio_out_w1ts;
+  volatile unsigned int gpio_out_w1tc;
+  volatile unsigned int gpio_enable;
+  volatile unsigned int gpio_enable_w1ts;
+  volatile unsigned int gpio_enable_w1tc;
+  volatile unsigned int gpio_in;
+  volatile unsigned int gpio_status;
+  volatile unsigned int gpio_status_w1ts;
+  volatile unsigned int gpio_status_w1tc;
+  volatile unsigned int gpio_pin0;
+  volatile unsigned int gpio_pin1;
+  volatile unsigned int gpio_pin2;
+  volatile unsigned int gpio_pin3;
+  volatile unsigned int gpio_pin4;
+  volatile unsigned int gpio_pin5;
+  volatile unsigned int gpio_pin6;
+  volatile unsigned int gpio_pin7;
+  volatile unsigned int gpio_pin8;
+  volatile unsigned int gpio_pin9;
+  volatile unsigned int gpio_pin10;
+  volatile unsigned int gpio_pin11;
+  volatile unsigned int gpio_pin12;
+  volatile unsigned int gpio_pin13;
+  volatile unsigned int gpio_pin14;
+  volatile unsigned int gpio_pin15;
+  volatile unsigned int gpio_pin16;
+  volatile unsigned int gpio_pin17;
+  volatile unsigned int sdio_pin;
+  volatile unsigned int clk_req_pin;
+  volatile unsigned int sigma_delta;
+  volatile unsigned int debug_control;
+  volatile unsigned int debug_input_sel;
+  volatile unsigned int debug_out;
+  volatile unsigned int la_control;
+  volatile unsigned int la_clock;
+  volatile unsigned int la_status;
+  volatile unsigned int la_trigger_sample;
+  volatile unsigned int la_trigger_position;
+  volatile unsigned int la_pre_trigger;
+  volatile unsigned int la_post_trigger;
+  volatile unsigned int la_filter_control;
+  volatile unsigned int la_filter_data;
+  volatile unsigned int la_filter_wildcard;
+  volatile unsigned int la_triggera_data;
+  volatile unsigned int la_triggera_wildcard;
+  volatile unsigned int la_triggerb_data;
+  volatile unsigned int la_triggerb_wildcard;
+  volatile unsigned int la_trigger;
+  volatile unsigned int la_fifo;
+  volatile unsigned int la[2];
+  volatile unsigned int ant_pin;
+  volatile unsigned int antd_pin;
+  volatile unsigned int gpio_pin;
+  volatile unsigned int gpio_h_pin;
+  volatile unsigned int bt_pin;
+  volatile unsigned int bt_wlan_pin;
+  volatile unsigned int si_uart_pin;
+  volatile unsigned int clk32k_pin;
+  volatile unsigned int reset_tuple_status;
+} gpio_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..20ac2b5c8920
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h
@@ -0,0 +1,405 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_HOST_REG_REG_H_
+#define _MBOX_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS                  0x00000400
+#define HOST_INT_STATUS_OFFSET                   0x00000400
+#define HOST_INT_STATUS_ERROR_MSB                7
+#define HOST_INT_STATUS_ERROR_LSB                7
+#define HOST_INT_STATUS_ERROR_MASK               0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB                  6
+#define HOST_INT_STATUS_CPU_LSB                  6
+#define HOST_INT_STATUS_CPU_MASK                 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_DRAGON_INT_MSB           5
+#define HOST_INT_STATUS_DRAGON_INT_LSB           5
+#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
+#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
+#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB              4
+#define HOST_INT_STATUS_COUNTER_LSB              4
+#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB            3
+#define HOST_INT_STATUS_MBOX_DATA_LSB            0
+#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS                   0x00000401
+#define CPU_INT_STATUS_OFFSET                    0x00000401
+#define CPU_INT_STATUS_BIT_MSB                   7
+#define CPU_INT_STATUS_BIT_LSB                   0
+#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS                 0x00000402
+#define ERROR_INT_STATUS_OFFSET                  0x00000402
+#define ERROR_INT_STATUS_SPI_MSB                 3
+#define ERROR_INT_STATUS_SPI_LSB                 3
+#define ERROR_INT_STATUS_SPI_MASK                0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB              2
+#define ERROR_INT_STATUS_WAKEUP_LSB              2
+#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS               0x00000403
+#define COUNTER_INT_STATUS_OFFSET                0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB           7
+#define COUNTER_INT_STATUS_COUNTER_LSB           0
+#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS                       0x00000404
+#define MBOX_FRAME_OFFSET                        0x00000404
+#define MBOX_FRAME_RX_EOM_MSB                    7
+#define MBOX_FRAME_RX_EOM_LSB                    4
+#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB                    3
+#define MBOX_FRAME_RX_SOM_LSB                    0
+#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
+#define RX_LOOKAHEAD0_OFFSET                     0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB                   7
+#define RX_LOOKAHEAD0_DATA_LSB                   0
+#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
+#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB                   7
+#define RX_LOOKAHEAD1_DATA_LSB                   0
+#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
+#define RX_LOOKAHEAD2_OFFSET                     0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB                   7
+#define RX_LOOKAHEAD2_DATA_LSB                   0
+#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
+#define RX_LOOKAHEAD3_OFFSET                     0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB                   7
+#define RX_LOOKAHEAD3_DATA_LSB                   0
+#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS                0x00000418
+#define INT_STATUS_ENABLE_OFFSET                 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB              7
+#define INT_STATUS_ENABLE_ERROR_LSB              7
+#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB                6
+#define INT_STATUS_ENABLE_CPU_LSB                6
+#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
+#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
+#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB            4
+#define INT_STATUS_ENABLE_COUNTER_LSB            4
+#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS                            0x00000420
+#define COUNT_OFFSET                             0x00000420
+#define COUNT_VALUE_MSB                          7
+#define COUNT_VALUE_LSB                          0
+#define COUNT_VALUE_MASK                         0x000000ff
+#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS                        0x00000440
+#define COUNT_DEC_OFFSET                         0x00000440
+#define COUNT_DEC_VALUE_MSB                      7
+#define COUNT_DEC_VALUE_LSB                      0
+#define COUNT_DEC_VALUE_MASK                     0x000000ff
+#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS                          0x00000460
+#define SCRATCH_OFFSET                           0x00000460
+#define SCRATCH_VALUE_MSB                        7
+#define SCRATCH_VALUE_LSB                        0
+#define SCRATCH_VALUE_MASK                       0x000000ff
+#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS                     0x00000468
+#define FIFO_TIMEOUT_OFFSET                      0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB                   7
+#define FIFO_TIMEOUT_VALUE_LSB                   0
+#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS                    0x0000046a
+#define DISABLE_SLEEP_OFFSET                     0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB                1
+#define DISABLE_SLEEP_FOR_INT_LSB                1
+#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB                     0
+#define DISABLE_SLEEP_ON_LSB                     0
+#define DISABLE_SLEEP_ON_MASK                    0x00000001
+#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS                        0x00000470
+#define LOCAL_BUS_OFFSET                         0x00000470
+#define LOCAL_BUS_STATE_MSB                      1
+#define LOCAL_BUS_STATE_LSB                      0
+#define LOCAL_BUS_STATE_MASK                     0x00000003
+#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS                         0x00000472
+#define INT_WLAN_OFFSET                          0x00000472
+#define INT_WLAN_VECTOR_MSB                      7
+#define INT_WLAN_VECTOR_LSB                      0
+#define INT_WLAN_VECTOR_MASK                     0x000000ff
+#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS                      0x00000474
+#define WINDOW_DATA_OFFSET                       0x00000474
+#define WINDOW_DATA_DATA_MSB                     7
+#define WINDOW_DATA_DATA_LSB                     0
+#define WINDOW_DATA_DATA_MASK                    0x000000ff
+#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB               7
+#define WINDOW_WRITE_ADDR_ADDR_LSB               0
+#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB                7
+#define WINDOW_READ_ADDR_ADDR_LSB                0
+#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define SPI_CONFIG_ADDRESS                       0x00000480
+#define SPI_CONFIG_OFFSET                        0x00000480
+#define SPI_CONFIG_SPI_RESET_MSB                 4
+#define SPI_CONFIG_SPI_RESET_LSB                 4
+#define SPI_CONFIG_SPI_RESET_MASK                0x00000010
+#define SPI_CONFIG_SPI_RESET_GET(x)              (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
+#define SPI_CONFIG_SPI_RESET_SET(x)              (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
+#define SPI_CONFIG_INTERRUPT_ENABLE_MSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_LSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_MASK         0x00000008
+#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x)       (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x)       (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define SPI_CONFIG_TEST_MODE_MSB                 2
+#define SPI_CONFIG_TEST_MODE_LSB                 2
+#define SPI_CONFIG_TEST_MODE_MASK                0x00000004
+#define SPI_CONFIG_TEST_MODE_GET(x)              (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
+#define SPI_CONFIG_TEST_MODE_SET(x)              (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
+#define SPI_CONFIG_DATA_SIZE_MSB                 1
+#define SPI_CONFIG_DATA_SIZE_LSB                 0
+#define SPI_CONFIG_DATA_SIZE_MASK                0x00000003
+#define SPI_CONFIG_DATA_SIZE_GET(x)              (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
+#define SPI_CONFIG_DATA_SIZE_SET(x)              (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
+
+#define SPI_STATUS_ADDRESS                       0x00000481
+#define SPI_STATUS_OFFSET                        0x00000481
+#define SPI_STATUS_ADDR_ERR_MSB                  3
+#define SPI_STATUS_ADDR_ERR_LSB                  3
+#define SPI_STATUS_ADDR_ERR_MASK                 0x00000008
+#define SPI_STATUS_ADDR_ERR_GET(x)               (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
+#define SPI_STATUS_ADDR_ERR_SET(x)               (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
+#define SPI_STATUS_RD_ERR_MSB                    2
+#define SPI_STATUS_RD_ERR_LSB                    2
+#define SPI_STATUS_RD_ERR_MASK                   0x00000004
+#define SPI_STATUS_RD_ERR_GET(x)                 (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
+#define SPI_STATUS_RD_ERR_SET(x)                 (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
+#define SPI_STATUS_WR_ERR_MSB                    1
+#define SPI_STATUS_WR_ERR_LSB                    1
+#define SPI_STATUS_WR_ERR_MASK                   0x00000002
+#define SPI_STATUS_WR_ERR_GET(x)                 (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
+#define SPI_STATUS_WR_ERR_SET(x)                 (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
+#define SPI_STATUS_READY_MSB                     0
+#define SPI_STATUS_READY_LSB                     0
+#define SPI_STATUS_READY_MASK                    0x00000001
+#define SPI_STATUS_READY_GET(x)                  (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
+#define SPI_STATUS_READY_SET(x)                  (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS               0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET                0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK              0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x)            (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x)            (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CIS_WINDOW_ADDRESS                       0x00000600
+#define CIS_WINDOW_OFFSET                        0x00000600
+#define CIS_WINDOW_DATA_MSB                      7
+#define CIS_WINDOW_DATA_LSB                      0
+#define CIS_WINDOW_DATA_MASK                     0x000000ff
+#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_host_reg_reg_s {
+  unsigned char pad0[1024]; /* pad to 0x400 */
+  volatile unsigned char host_int_status;
+  volatile unsigned char cpu_int_status;
+  volatile unsigned char error_int_status;
+  volatile unsigned char counter_int_status;
+  volatile unsigned char mbox_frame;
+  volatile unsigned char rx_lookahead_valid;
+  unsigned char pad1[2]; /* pad to 0x408 */
+  volatile unsigned char rx_lookahead0[4];
+  volatile unsigned char rx_lookahead1[4];
+  volatile unsigned char rx_lookahead2[4];
+  volatile unsigned char rx_lookahead3[4];
+  volatile unsigned char int_status_enable;
+  volatile unsigned char cpu_int_status_enable;
+  volatile unsigned char error_status_enable;
+  volatile unsigned char counter_int_status_enable;
+  unsigned char pad2[4]; /* pad to 0x420 */
+  volatile unsigned char count[8];
+  unsigned char pad3[24]; /* pad to 0x440 */
+  volatile unsigned char count_dec[32];
+  volatile unsigned char scratch[8];
+  volatile unsigned char fifo_timeout;
+  volatile unsigned char fifo_timeout_enable;
+  volatile unsigned char disable_sleep;
+  unsigned char pad4[5]; /* pad to 0x470 */
+  volatile unsigned char local_bus;
+  unsigned char pad5[1]; /* pad to 0x472 */
+  volatile unsigned char int_wlan;
+  unsigned char pad6[1]; /* pad to 0x474 */
+  volatile unsigned char window_data[4];
+  volatile unsigned char window_write_addr[4];
+  volatile unsigned char window_read_addr[4];
+  volatile unsigned char spi_config;
+  volatile unsigned char spi_status;
+  volatile unsigned char non_assoc_sleep_en;
+  unsigned char pad7[381]; /* pad to 0x600 */
+  volatile unsigned char cis_window[512];
+} mbox_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h
new file mode 100644
index 000000000000..d232764d5af6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h
@@ -0,0 +1,500 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_REG_REG_H_
+#define _MBOX_REG_REG_H_
+
+#define MBOX_FIFO_ADDRESS                        0x00000000
+#define MBOX_FIFO_OFFSET                         0x00000000
+#define MBOX_FIFO_DATA_MSB                       19
+#define MBOX_FIFO_DATA_LSB                       0
+#define MBOX_FIFO_DATA_MASK                      0x000fffff
+#define MBOX_FIFO_DATA_GET(x)                    (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
+#define MBOX_FIFO_DATA_SET(x)                    (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
+
+#define MBOX_FIFO_STATUS_ADDRESS                 0x00000010
+#define MBOX_FIFO_STATUS_OFFSET                  0x00000010
+#define MBOX_FIFO_STATUS_EMPTY_MSB               19
+#define MBOX_FIFO_STATUS_EMPTY_LSB               16
+#define MBOX_FIFO_STATUS_EMPTY_MASK              0x000f0000
+#define MBOX_FIFO_STATUS_EMPTY_GET(x)            (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x)            (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
+#define MBOX_FIFO_STATUS_FULL_MSB                15
+#define MBOX_FIFO_STATUS_FULL_LSB                12
+#define MBOX_FIFO_STATUS_FULL_MASK               0x0000f000
+#define MBOX_FIFO_STATUS_FULL_GET(x)             (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
+#define MBOX_FIFO_STATUS_FULL_SET(x)             (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
+
+#define MBOX_DMA_POLICY_ADDRESS                  0x00000014
+#define MBOX_DMA_POLICY_OFFSET                   0x00000014
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK          0x00000008
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_LSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_MASK            0x00000004
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK          0x00000002
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_LSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_MASK            0x00000001
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_RX_CONTROL_ADDRESS             0x0000001c
+#define MBOX0_DMA_RX_CONTROL_OFFSET              0x0000001c
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_RX_CONTROL_START_MSB           1
+#define MBOX0_DMA_RX_CONTROL_START_LSB           1
+#define MBOX0_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_TX_CONTROL_ADDRESS             0x00000024
+#define MBOX0_DMA_TX_CONTROL_OFFSET              0x00000024
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_TX_CONTROL_START_MSB           1
+#define MBOX0_DMA_TX_CONTROL_START_LSB           1
+#define MBOX0_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_RX_CONTROL_ADDRESS             0x0000002c
+#define MBOX1_DMA_RX_CONTROL_OFFSET              0x0000002c
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_RX_CONTROL_START_MSB           1
+#define MBOX1_DMA_RX_CONTROL_START_LSB           1
+#define MBOX1_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_TX_CONTROL_ADDRESS             0x00000034
+#define MBOX1_DMA_TX_CONTROL_OFFSET              0x00000034
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_TX_CONTROL_START_MSB           1
+#define MBOX1_DMA_TX_CONTROL_START_LSB           1
+#define MBOX1_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_RX_CONTROL_ADDRESS             0x0000003c
+#define MBOX2_DMA_RX_CONTROL_OFFSET              0x0000003c
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_RX_CONTROL_START_MSB           1
+#define MBOX2_DMA_RX_CONTROL_START_LSB           1
+#define MBOX2_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_TX_CONTROL_ADDRESS             0x00000044
+#define MBOX2_DMA_TX_CONTROL_OFFSET              0x00000044
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_TX_CONTROL_START_MSB           1
+#define MBOX2_DMA_TX_CONTROL_START_LSB           1
+#define MBOX2_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_RX_CONTROL_ADDRESS             0x0000004c
+#define MBOX3_DMA_RX_CONTROL_OFFSET              0x0000004c
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_RX_CONTROL_START_MSB           1
+#define MBOX3_DMA_RX_CONTROL_START_LSB           1
+#define MBOX3_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_TX_CONTROL_ADDRESS             0x00000054
+#define MBOX3_DMA_TX_CONTROL_OFFSET              0x00000054
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_TX_CONTROL_START_MSB           1
+#define MBOX3_DMA_TX_CONTROL_START_LSB           1
+#define MBOX3_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX_INT_STATUS_ADDRESS                  0x00000058
+#define MBOX_INT_STATUS_OFFSET                   0x00000058
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB          11
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB          8
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define MBOX_INT_STATUS_HOST_MSB                 7
+#define MBOX_INT_STATUS_HOST_LSB                 0
+#define MBOX_INT_STATUS_HOST_MASK                0x000000ff
+#define MBOX_INT_STATUS_HOST_GET(x)              (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
+#define MBOX_INT_STATUS_HOST_SET(x)              (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
+
+#define MBOX_INT_ENABLE_ADDRESS                  0x0000005c
+#define MBOX_INT_ENABLE_OFFSET                   0x0000005c
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB          11
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB          8
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define MBOX_INT_ENABLE_HOST_MSB                 7
+#define MBOX_INT_ENABLE_HOST_LSB                 0
+#define MBOX_INT_ENABLE_HOST_MASK                0x000000ff
+#define MBOX_INT_ENABLE_HOST_GET(x)              (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
+#define MBOX_INT_ENABLE_HOST_SET(x)              (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
+
+#define INT_HOST_ADDRESS                         0x00000060
+#define INT_HOST_OFFSET                          0x00000060
+#define INT_HOST_VECTOR_MSB                      7
+#define INT_HOST_VECTOR_LSB                      0
+#define INT_HOST_VECTOR_MASK                     0x000000ff
+#define INT_HOST_VECTOR_GET(x)                   (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
+#define INT_HOST_VECTOR_SET(x)                   (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
+
+#define LOCAL_COUNT_ADDRESS                      0x00000080
+#define LOCAL_COUNT_OFFSET                       0x00000080
+#define LOCAL_COUNT_VALUE_MSB                    7
+#define LOCAL_COUNT_VALUE_LSB                    0
+#define LOCAL_COUNT_VALUE_MASK                   0x000000ff
+#define LOCAL_COUNT_VALUE_GET(x)                 (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
+#define LOCAL_COUNT_VALUE_SET(x)                 (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
+
+#define COUNT_INC_ADDRESS                        0x000000a0
+#define COUNT_INC_OFFSET                         0x000000a0
+#define COUNT_INC_VALUE_MSB                      7
+#define COUNT_INC_VALUE_LSB                      0
+#define COUNT_INC_VALUE_MASK                     0x000000ff
+#define COUNT_INC_VALUE_GET(x)                   (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
+#define COUNT_INC_VALUE_SET(x)                   (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
+
+#define LOCAL_SCRATCH_ADDRESS                    0x000000c0
+#define LOCAL_SCRATCH_OFFSET                     0x000000c0
+#define LOCAL_SCRATCH_VALUE_MSB                  7
+#define LOCAL_SCRATCH_VALUE_LSB                  0
+#define LOCAL_SCRATCH_VALUE_MASK                 0x000000ff
+#define LOCAL_SCRATCH_VALUE_GET(x)               (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
+#define LOCAL_SCRATCH_VALUE_SET(x)               (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
+
+#define USE_LOCAL_BUS_ADDRESS                    0x000000e0
+#define USE_LOCAL_BUS_OFFSET                     0x000000e0
+#define USE_LOCAL_BUS_PIN_INIT_MSB               0
+#define USE_LOCAL_BUS_PIN_INIT_LSB               0
+#define USE_LOCAL_BUS_PIN_INIT_MASK              0x00000001
+#define USE_LOCAL_BUS_PIN_INIT_GET(x)            (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x)            (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define SDIO_CONFIG_ADDRESS                      0x000000e4
+#define SDIO_CONFIG_OFFSET                       0x000000e4
+#define SDIO_CONFIG_CCCR_IOR1_MSB                0
+#define SDIO_CONFIG_CCCR_IOR1_LSB                0
+#define SDIO_CONFIG_CCCR_IOR1_MASK               0x00000001
+#define SDIO_CONFIG_CCCR_IOR1_GET(x)             (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x)             (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define MBOX_DEBUG_ADDRESS                       0x000000e8
+#define MBOX_DEBUG_OFFSET                        0x000000e8
+#define MBOX_DEBUG_SEL_MSB                       2
+#define MBOX_DEBUG_SEL_LSB                       0
+#define MBOX_DEBUG_SEL_MASK                      0x00000007
+#define MBOX_DEBUG_SEL_GET(x)                    (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
+#define MBOX_DEBUG_SEL_SET(x)                    (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
+
+#define MBOX_FIFO_RESET_ADDRESS                  0x000000ec
+#define MBOX_FIFO_RESET_OFFSET                   0x000000ec
+#define MBOX_FIFO_RESET_INIT_MSB                 0
+#define MBOX_FIFO_RESET_INIT_LSB                 0
+#define MBOX_FIFO_RESET_INIT_MASK                0x00000001
+#define MBOX_FIFO_RESET_INIT_GET(x)              (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
+#define MBOX_FIFO_RESET_INIT_SET(x)              (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
+
+#define MBOX_TXFIFO_POP_ADDRESS                  0x000000f0
+#define MBOX_TXFIFO_POP_OFFSET                   0x000000f0
+#define MBOX_TXFIFO_POP_DATA_MSB                 0
+#define MBOX_TXFIFO_POP_DATA_LSB                 0
+#define MBOX_TXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_TXFIFO_POP_DATA_GET(x)              (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
+#define MBOX_TXFIFO_POP_DATA_SET(x)              (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
+
+#define MBOX_RXFIFO_POP_ADDRESS                  0x00000100
+#define MBOX_RXFIFO_POP_OFFSET                   0x00000100
+#define MBOX_RXFIFO_POP_DATA_MSB                 0
+#define MBOX_RXFIFO_POP_DATA_LSB                 0
+#define MBOX_RXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_RXFIFO_POP_DATA_GET(x)              (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
+#define MBOX_RXFIFO_POP_DATA_SET(x)              (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
+
+#define SDIO_DEBUG_ADDRESS                       0x00000110
+#define SDIO_DEBUG_OFFSET                        0x00000110
+#define SDIO_DEBUG_SEL_MSB                       3
+#define SDIO_DEBUG_SEL_LSB                       0
+#define SDIO_DEBUG_SEL_MASK                      0x0000000f
+#define SDIO_DEBUG_SEL_GET(x)                    (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
+#define SDIO_DEBUG_SEL_SET(x)                    (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
+
+#define HOST_IF_WINDOW_ADDRESS                   0x00002000
+#define HOST_IF_WINDOW_OFFSET                    0x00002000
+#define HOST_IF_WINDOW_DATA_MSB                  7
+#define HOST_IF_WINDOW_DATA_LSB                  0
+#define HOST_IF_WINDOW_DATA_MASK                 0x000000ff
+#define HOST_IF_WINDOW_DATA_GET(x)               (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
+#define HOST_IF_WINDOW_DATA_SET(x)               (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_reg_reg_s {
+  volatile unsigned int mbox_fifo[4];
+  volatile unsigned int mbox_fifo_status;
+  volatile unsigned int mbox_dma_policy;
+  volatile unsigned int mbox0_dma_rx_descriptor_base;
+  volatile unsigned int mbox0_dma_rx_control;
+  volatile unsigned int mbox0_dma_tx_descriptor_base;
+  volatile unsigned int mbox0_dma_tx_control;
+  volatile unsigned int mbox1_dma_rx_descriptor_base;
+  volatile unsigned int mbox1_dma_rx_control;
+  volatile unsigned int mbox1_dma_tx_descriptor_base;
+  volatile unsigned int mbox1_dma_tx_control;
+  volatile unsigned int mbox2_dma_rx_descriptor_base;
+  volatile unsigned int mbox2_dma_rx_control;
+  volatile unsigned int mbox2_dma_tx_descriptor_base;
+  volatile unsigned int mbox2_dma_tx_control;
+  volatile unsigned int mbox3_dma_rx_descriptor_base;
+  volatile unsigned int mbox3_dma_rx_control;
+  volatile unsigned int mbox3_dma_tx_descriptor_base;
+  volatile unsigned int mbox3_dma_tx_control;
+  volatile unsigned int mbox_int_status;
+  volatile unsigned int mbox_int_enable;
+  volatile unsigned int int_host;
+  unsigned char pad0[28]; /* pad to 0x80 */
+  volatile unsigned int local_count[8];
+  volatile unsigned int count_inc[8];
+  volatile unsigned int local_scratch[8];
+  volatile unsigned int use_local_bus;
+  volatile unsigned int sdio_config;
+  volatile unsigned int mbox_debug;
+  volatile unsigned int mbox_fifo_reset;
+  volatile unsigned int mbox_txfifo_pop[4];
+  volatile unsigned int mbox_rxfifo_pop[4];
+  volatile unsigned int sdio_debug;
+  unsigned char pad1[7916]; /* pad to 0x2000 */
+  volatile unsigned int host_if_window[2048];
+} mbox_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h
new file mode 100644
index 000000000000..cc2cb7350a78
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h
@@ -0,0 +1,1182 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_REG_REG_H_
+#define _RTC_REG_REG_H_
+
+#define RESET_CONTROL_ADDRESS                    0x00000000
+#define RESET_CONTROL_OFFSET                     0x00000000
+#define RESET_CONTROL_CPU_INIT_RESET_MSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_LSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_MASK        0x00000800
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x)      (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x)      (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK       0x00000400
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x)     (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x)     (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define RESET_CONTROL_RST_OUT_MSB                9
+#define RESET_CONTROL_RST_OUT_LSB                9
+#define RESET_CONTROL_RST_OUT_MASK               0x00000200
+#define RESET_CONTROL_RST_OUT_GET(x)             (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
+#define RESET_CONTROL_RST_OUT_SET(x)             (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
+#define RESET_CONTROL_COLD_RST_MSB               8
+#define RESET_CONTROL_COLD_RST_LSB               8
+#define RESET_CONTROL_COLD_RST_MASK              0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+#define RESET_CONTROL_WARM_RST_MSB               7
+#define RESET_CONTROL_WARM_RST_LSB               7
+#define RESET_CONTROL_WARM_RST_MASK              0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+#define RESET_CONTROL_CPU_WARM_RST_MSB           6
+#define RESET_CONTROL_CPU_WARM_RST_LSB           6
+#define RESET_CONTROL_CPU_WARM_RST_MASK          0x00000040
+#define RESET_CONTROL_CPU_WARM_RST_GET(x)        (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x)        (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
+#define RESET_CONTROL_MAC_COLD_RST_MSB           5
+#define RESET_CONTROL_MAC_COLD_RST_LSB           5
+#define RESET_CONTROL_MAC_COLD_RST_MASK          0x00000020
+#define RESET_CONTROL_MAC_COLD_RST_GET(x)        (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x)        (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
+#define RESET_CONTROL_MAC_WARM_RST_MSB           4
+#define RESET_CONTROL_MAC_WARM_RST_LSB           4
+#define RESET_CONTROL_MAC_WARM_RST_MASK          0x00000010
+#define RESET_CONTROL_MAC_WARM_RST_GET(x)        (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x)        (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
+#define RESET_CONTROL_MBOX_RST_MSB               2
+#define RESET_CONTROL_MBOX_RST_LSB               2
+#define RESET_CONTROL_MBOX_RST_MASK              0x00000004
+#define RESET_CONTROL_MBOX_RST_GET(x)            (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
+#define RESET_CONTROL_MBOX_RST_SET(x)            (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_UART_RST_MSB               1
+#define RESET_CONTROL_UART_RST_LSB               1
+#define RESET_CONTROL_UART_RST_MASK              0x00000002
+#define RESET_CONTROL_UART_RST_GET(x)            (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
+#define RESET_CONTROL_UART_RST_SET(x)            (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MSB                0
+#define RESET_CONTROL_SI0_RST_LSB                0
+#define RESET_CONTROL_SI0_RST_MASK               0x00000001
+#define RESET_CONTROL_SI0_RST_GET(x)             (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
+#define RESET_CONTROL_SI0_RST_SET(x)             (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
+
+#define XTAL_CONTROL_ADDRESS                     0x00000004
+#define XTAL_CONTROL_OFFSET                      0x00000004
+#define XTAL_CONTROL_TCXO_MSB                    0
+#define XTAL_CONTROL_TCXO_LSB                    0
+#define XTAL_CONTROL_TCXO_MASK                   0x00000001
+#define XTAL_CONTROL_TCXO_GET(x)                 (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
+#define XTAL_CONTROL_TCXO_SET(x)                 (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
+
+#define TCXO_DETECT_ADDRESS                      0x00000008
+#define TCXO_DETECT_OFFSET                       0x00000008
+#define TCXO_DETECT_PRESENT_MSB                  0
+#define TCXO_DETECT_PRESENT_LSB                  0
+#define TCXO_DETECT_PRESENT_MASK                 0x00000001
+#define TCXO_DETECT_PRESENT_GET(x)               (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
+#define TCXO_DETECT_PRESENT_SET(x)               (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
+
+#define XTAL_TEST_ADDRESS                        0x0000000c
+#define XTAL_TEST_OFFSET                         0x0000000c
+#define XTAL_TEST_NOTCXODET_MSB                  0
+#define XTAL_TEST_NOTCXODET_LSB                  0
+#define XTAL_TEST_NOTCXODET_MASK                 0x00000001
+#define XTAL_TEST_NOTCXODET_GET(x)               (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
+#define XTAL_TEST_NOTCXODET_SET(x)               (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
+
+#define QUADRATURE_ADDRESS                       0x00000010
+#define QUADRATURE_OFFSET                        0x00000010
+#define QUADRATURE_ADC_MSB                       5
+#define QUADRATURE_ADC_LSB                       4
+#define QUADRATURE_ADC_MASK                      0x00000030
+#define QUADRATURE_ADC_GET(x)                    (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
+#define QUADRATURE_ADC_SET(x)                    (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
+#define QUADRATURE_SEL_MSB                       2
+#define QUADRATURE_SEL_LSB                       2
+#define QUADRATURE_SEL_MASK                      0x00000004
+#define QUADRATURE_SEL_GET(x)                    (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
+#define QUADRATURE_SEL_SET(x)                    (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
+#define QUADRATURE_DAC_MSB                       1
+#define QUADRATURE_DAC_LSB                       0
+#define QUADRATURE_DAC_MASK                      0x00000003
+#define QUADRATURE_DAC_GET(x)                    (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
+#define QUADRATURE_DAC_SET(x)                    (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
+
+#define PLL_CONTROL_ADDRESS                      0x00000014
+#define PLL_CONTROL_OFFSET                       0x00000014
+#define PLL_CONTROL_DIG_TEST_CLK_MSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_LSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_MASK            0x00100000
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x)          (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x)          (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_LSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_MASK            0x00080000
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x)          (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x)          (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define PLL_CONTROL_NOPWD_MSB                    18
+#define PLL_CONTROL_NOPWD_LSB                    18
+#define PLL_CONTROL_NOPWD_MASK                   0x00040000
+#define PLL_CONTROL_NOPWD_GET(x)                 (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
+#define PLL_CONTROL_NOPWD_SET(x)                 (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
+#define PLL_CONTROL_UPDATING_MSB                 17
+#define PLL_CONTROL_UPDATING_LSB                 17
+#define PLL_CONTROL_UPDATING_MASK                0x00020000
+#define PLL_CONTROL_UPDATING_GET(x)              (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
+#define PLL_CONTROL_UPDATING_SET(x)              (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
+#define PLL_CONTROL_BYPASS_MSB                   16
+#define PLL_CONTROL_BYPASS_LSB                   16
+#define PLL_CONTROL_BYPASS_MASK                  0x00010000
+#define PLL_CONTROL_BYPASS_GET(x)                (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
+#define PLL_CONTROL_BYPASS_SET(x)                (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
+#define PLL_CONTROL_REFDIV_MSB                   15
+#define PLL_CONTROL_REFDIV_LSB                   12
+#define PLL_CONTROL_REFDIV_MASK                  0x0000f000
+#define PLL_CONTROL_REFDIV_GET(x)                (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
+#define PLL_CONTROL_REFDIV_SET(x)                (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
+#define PLL_CONTROL_DIV_MSB                      9
+#define PLL_CONTROL_DIV_LSB                      0
+#define PLL_CONTROL_DIV_MASK                     0x000003ff
+#define PLL_CONTROL_DIV_GET(x)                   (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
+#define PLL_CONTROL_DIV_SET(x)                   (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
+
+#define PLL_SETTLE_ADDRESS                       0x00000018
+#define PLL_SETTLE_OFFSET                        0x00000018
+#define PLL_SETTLE_TIME_MSB                      11
+#define PLL_SETTLE_TIME_LSB                      0
+#define PLL_SETTLE_TIME_MASK                     0x00000fff
+#define PLL_SETTLE_TIME_GET(x)                   (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
+#define PLL_SETTLE_TIME_SET(x)                   (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
+
+#define XTAL_SETTLE_ADDRESS                      0x0000001c
+#define XTAL_SETTLE_OFFSET                       0x0000001c
+#define XTAL_SETTLE_TIME_MSB                     7
+#define XTAL_SETTLE_TIME_LSB                     0
+#define XTAL_SETTLE_TIME_MASK                    0x000000ff
+#define XTAL_SETTLE_TIME_GET(x)                  (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
+#define XTAL_SETTLE_TIME_SET(x)                  (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
+
+#define CPU_CLOCK_ADDRESS                        0x00000020
+#define CPU_CLOCK_OFFSET                         0x00000020
+#define CPU_CLOCK_STANDARD_MSB                   1
+#define CPU_CLOCK_STANDARD_LSB                   0
+#define CPU_CLOCK_STANDARD_MASK                  0x00000003
+#define CPU_CLOCK_STANDARD_GET(x)                (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_SET(x)                (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+
+#define CLOCK_OUT_ADDRESS                        0x00000024
+#define CLOCK_OUT_OFFSET                         0x00000024
+#define CLOCK_OUT_SELECT_MSB                     3
+#define CLOCK_OUT_SELECT_LSB                     0
+#define CLOCK_OUT_SELECT_MASK                    0x0000000f
+#define CLOCK_OUT_SELECT_GET(x)                  (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
+#define CLOCK_OUT_SELECT_SET(x)                  (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
+
+#define CLOCK_CONTROL_ADDRESS                    0x00000028
+#define CLOCK_CONTROL_OFFSET                     0x00000028
+#define CLOCK_CONTROL_LF_CLK32_MSB               2
+#define CLOCK_CONTROL_LF_CLK32_LSB               2
+#define CLOCK_CONTROL_LF_CLK32_MASK              0x00000004
+#define CLOCK_CONTROL_LF_CLK32_GET(x)            (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
+#define CLOCK_CONTROL_LF_CLK32_SET(x)            (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
+#define CLOCK_CONTROL_UART_CLK_MSB               1
+#define CLOCK_CONTROL_UART_CLK_LSB               1
+#define CLOCK_CONTROL_UART_CLK_MASK              0x00000002
+#define CLOCK_CONTROL_UART_CLK_GET(x)            (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
+#define CLOCK_CONTROL_UART_CLK_SET(x)            (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
+#define CLOCK_CONTROL_SI0_CLK_MSB                0
+#define CLOCK_CONTROL_SI0_CLK_LSB                0
+#define CLOCK_CONTROL_SI0_CLK_MASK               0x00000001
+#define CLOCK_CONTROL_SI0_CLK_GET(x)             (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
+#define CLOCK_CONTROL_SI0_CLK_SET(x)             (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define BIAS_OVERRIDE_ADDRESS                    0x0000002c
+#define BIAS_OVERRIDE_OFFSET                     0x0000002c
+#define BIAS_OVERRIDE_ON_MSB                     0
+#define BIAS_OVERRIDE_ON_LSB                     0
+#define BIAS_OVERRIDE_ON_MASK                    0x00000001
+#define BIAS_OVERRIDE_ON_GET(x)                  (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
+#define BIAS_OVERRIDE_ON_SET(x)                  (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
+
+#define WDT_CONTROL_ADDRESS                      0x00000030
+#define WDT_CONTROL_OFFSET                       0x00000030
+#define WDT_CONTROL_ACTION_MSB                   2
+#define WDT_CONTROL_ACTION_LSB                   0
+#define WDT_CONTROL_ACTION_MASK                  0x00000007
+#define WDT_CONTROL_ACTION_GET(x)                (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
+#define WDT_CONTROL_ACTION_SET(x)                (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
+
+#define WDT_STATUS_ADDRESS                       0x00000034
+#define WDT_STATUS_OFFSET                        0x00000034
+#define WDT_STATUS_INTERRUPT_MSB                 0
+#define WDT_STATUS_INTERRUPT_LSB                 0
+#define WDT_STATUS_INTERRUPT_MASK                0x00000001
+#define WDT_STATUS_INTERRUPT_GET(x)              (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
+#define WDT_STATUS_INTERRUPT_SET(x)              (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
+
+#define WDT_ADDRESS                              0x00000038
+#define WDT_OFFSET                               0x00000038
+#define WDT_TARGET_MSB                           21
+#define WDT_TARGET_LSB                           0
+#define WDT_TARGET_MASK                          0x003fffff
+#define WDT_TARGET_GET(x)                        (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
+#define WDT_TARGET_SET(x)                        (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
+
+#define WDT_COUNT_ADDRESS                        0x0000003c
+#define WDT_COUNT_OFFSET                         0x0000003c
+#define WDT_COUNT_VALUE_MSB                      21
+#define WDT_COUNT_VALUE_LSB                      0
+#define WDT_COUNT_VALUE_MASK                     0x003fffff
+#define WDT_COUNT_VALUE_GET(x)                   (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
+#define WDT_COUNT_VALUE_SET(x)                   (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
+
+#define WDT_RESET_ADDRESS                        0x00000040
+#define WDT_RESET_OFFSET                         0x00000040
+#define WDT_RESET_VALUE_MSB                      0
+#define WDT_RESET_VALUE_LSB                      0
+#define WDT_RESET_VALUE_MASK                     0x00000001
+#define WDT_RESET_VALUE_GET(x)                   (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
+#define WDT_RESET_VALUE_SET(x)                   (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
+
+#define INT_STATUS_ADDRESS                       0x00000044
+#define INT_STATUS_OFFSET                        0x00000044
+#define INT_STATUS_RTC_POWER_MSB                 14
+#define INT_STATUS_RTC_POWER_LSB                 14
+#define INT_STATUS_RTC_POWER_MASK                0x00004000
+#define INT_STATUS_RTC_POWER_GET(x)              (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
+#define INT_STATUS_RTC_POWER_SET(x)              (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
+#define INT_STATUS_MAC_MSB                       13
+#define INT_STATUS_MAC_LSB                       13
+#define INT_STATUS_MAC_MASK                      0x00002000
+#define INT_STATUS_MAC_GET(x)                    (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
+#define INT_STATUS_MAC_SET(x)                    (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
+#define INT_STATUS_MAILBOX_MSB                   12
+#define INT_STATUS_MAILBOX_LSB                   12
+#define INT_STATUS_MAILBOX_MASK                  0x00001000
+#define INT_STATUS_MAILBOX_GET(x)                (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
+#define INT_STATUS_MAILBOX_SET(x)                (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
+#define INT_STATUS_RTC_ALARM_MSB                 11
+#define INT_STATUS_RTC_ALARM_LSB                 11
+#define INT_STATUS_RTC_ALARM_MASK                0x00000800
+#define INT_STATUS_RTC_ALARM_GET(x)              (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
+#define INT_STATUS_RTC_ALARM_SET(x)              (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
+#define INT_STATUS_HF_TIMER_MSB                  10
+#define INT_STATUS_HF_TIMER_LSB                  10
+#define INT_STATUS_HF_TIMER_MASK                 0x00000400
+#define INT_STATUS_HF_TIMER_GET(x)               (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
+#define INT_STATUS_HF_TIMER_SET(x)               (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
+#define INT_STATUS_LF_TIMER3_MSB                 9
+#define INT_STATUS_LF_TIMER3_LSB                 9
+#define INT_STATUS_LF_TIMER3_MASK                0x00000200
+#define INT_STATUS_LF_TIMER3_GET(x)              (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
+#define INT_STATUS_LF_TIMER3_SET(x)              (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
+#define INT_STATUS_LF_TIMER2_MSB                 8
+#define INT_STATUS_LF_TIMER2_LSB                 8
+#define INT_STATUS_LF_TIMER2_MASK                0x00000100
+#define INT_STATUS_LF_TIMER2_GET(x)              (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
+#define INT_STATUS_LF_TIMER2_SET(x)              (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
+#define INT_STATUS_LF_TIMER1_MSB                 7
+#define INT_STATUS_LF_TIMER1_LSB                 7
+#define INT_STATUS_LF_TIMER1_MASK                0x00000080
+#define INT_STATUS_LF_TIMER1_GET(x)              (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
+#define INT_STATUS_LF_TIMER1_SET(x)              (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
+#define INT_STATUS_LF_TIMER0_MSB                 6
+#define INT_STATUS_LF_TIMER0_LSB                 6
+#define INT_STATUS_LF_TIMER0_MASK                0x00000040
+#define INT_STATUS_LF_TIMER0_GET(x)              (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
+#define INT_STATUS_LF_TIMER0_SET(x)              (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
+#define INT_STATUS_KEYPAD_MSB                    5
+#define INT_STATUS_KEYPAD_LSB                    5
+#define INT_STATUS_KEYPAD_MASK                   0x00000020
+#define INT_STATUS_KEYPAD_GET(x)                 (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
+#define INT_STATUS_KEYPAD_SET(x)                 (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
+#define INT_STATUS_SI_MSB                        4
+#define INT_STATUS_SI_LSB                        4
+#define INT_STATUS_SI_MASK                       0x00000010
+#define INT_STATUS_SI_GET(x)                     (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
+#define INT_STATUS_SI_SET(x)                     (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
+#define INT_STATUS_GPIO_MSB                      3
+#define INT_STATUS_GPIO_LSB                      3
+#define INT_STATUS_GPIO_MASK                     0x00000008
+#define INT_STATUS_GPIO_GET(x)                   (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
+#define INT_STATUS_GPIO_SET(x)                   (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
+#define INT_STATUS_UART_MSB                      2
+#define INT_STATUS_UART_LSB                      2
+#define INT_STATUS_UART_MASK                     0x00000004
+#define INT_STATUS_UART_GET(x)                   (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
+#define INT_STATUS_UART_SET(x)                   (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
+#define INT_STATUS_ERROR_MSB                     1
+#define INT_STATUS_ERROR_LSB                     1
+#define INT_STATUS_ERROR_MASK                    0x00000002
+#define INT_STATUS_ERROR_GET(x)                  (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
+#define INT_STATUS_ERROR_SET(x)                  (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
+#define INT_STATUS_WDT_INT_MSB                   0
+#define INT_STATUS_WDT_INT_LSB                   0
+#define INT_STATUS_WDT_INT_MASK                  0x00000001
+#define INT_STATUS_WDT_INT_GET(x)                (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
+#define INT_STATUS_WDT_INT_SET(x)                (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
+
+#define LF_TIMER0_ADDRESS                        0x00000048
+#define LF_TIMER0_OFFSET                         0x00000048
+#define LF_TIMER0_TARGET_MSB                     31
+#define LF_TIMER0_TARGET_LSB                     0
+#define LF_TIMER0_TARGET_MASK                    0xffffffff
+#define LF_TIMER0_TARGET_GET(x)                  (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
+#define LF_TIMER0_TARGET_SET(x)                  (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
+
+#define LF_TIMER_COUNT0_ADDRESS                  0x0000004c
+#define LF_TIMER_COUNT0_OFFSET                   0x0000004c
+#define LF_TIMER_COUNT0_VALUE_MSB                31
+#define LF_TIMER_COUNT0_VALUE_LSB                0
+#define LF_TIMER_COUNT0_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT0_VALUE_GET(x)             (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
+#define LF_TIMER_COUNT0_VALUE_SET(x)             (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
+
+#define LF_TIMER_CONTROL0_ADDRESS                0x00000050
+#define LF_TIMER_CONTROL0_OFFSET                 0x00000050
+#define LF_TIMER_CONTROL0_ENABLE_MSB             2
+#define LF_TIMER_CONTROL0_ENABLE_LSB             2
+#define LF_TIMER_CONTROL0_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL0_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL0_RESET_MSB              0
+#define LF_TIMER_CONTROL0_RESET_LSB              0
+#define LF_TIMER_CONTROL0_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL0_RESET_GET(x)           (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
+#define LF_TIMER_CONTROL0_RESET_SET(x)           (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
+
+#define LF_TIMER_STATUS0_ADDRESS                 0x00000054
+#define LF_TIMER_STATUS0_OFFSET                  0x00000054
+#define LF_TIMER_STATUS0_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define LF_TIMER1_ADDRESS                        0x00000058
+#define LF_TIMER1_OFFSET                         0x00000058
+#define LF_TIMER1_TARGET_MSB                     31
+#define LF_TIMER1_TARGET_LSB                     0
+#define LF_TIMER1_TARGET_MASK                    0xffffffff
+#define LF_TIMER1_TARGET_GET(x)                  (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
+#define LF_TIMER1_TARGET_SET(x)                  (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
+
+#define LF_TIMER_COUNT1_ADDRESS                  0x0000005c
+#define LF_TIMER_COUNT1_OFFSET                   0x0000005c
+#define LF_TIMER_COUNT1_VALUE_MSB                31
+#define LF_TIMER_COUNT1_VALUE_LSB                0
+#define LF_TIMER_COUNT1_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT1_VALUE_GET(x)             (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
+#define LF_TIMER_COUNT1_VALUE_SET(x)             (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
+
+#define LF_TIMER_CONTROL1_ADDRESS                0x00000060
+#define LF_TIMER_CONTROL1_OFFSET                 0x00000060
+#define LF_TIMER_CONTROL1_ENABLE_MSB             2
+#define LF_TIMER_CONTROL1_ENABLE_LSB             2
+#define LF_TIMER_CONTROL1_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL1_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL1_RESET_MSB              0
+#define LF_TIMER_CONTROL1_RESET_LSB              0
+#define LF_TIMER_CONTROL1_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL1_RESET_GET(x)           (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
+#define LF_TIMER_CONTROL1_RESET_SET(x)           (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
+
+#define LF_TIMER_STATUS1_ADDRESS                 0x00000064
+#define LF_TIMER_STATUS1_OFFSET                  0x00000064
+#define LF_TIMER_STATUS1_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define LF_TIMER2_ADDRESS                        0x00000068
+#define LF_TIMER2_OFFSET                         0x00000068
+#define LF_TIMER2_TARGET_MSB                     31
+#define LF_TIMER2_TARGET_LSB                     0
+#define LF_TIMER2_TARGET_MASK                    0xffffffff
+#define LF_TIMER2_TARGET_GET(x)                  (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
+#define LF_TIMER2_TARGET_SET(x)                  (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
+
+#define LF_TIMER_COUNT2_ADDRESS                  0x0000006c
+#define LF_TIMER_COUNT2_OFFSET                   0x0000006c
+#define LF_TIMER_COUNT2_VALUE_MSB                31
+#define LF_TIMER_COUNT2_VALUE_LSB                0
+#define LF_TIMER_COUNT2_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT2_VALUE_GET(x)             (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
+#define LF_TIMER_COUNT2_VALUE_SET(x)             (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
+
+#define LF_TIMER_CONTROL2_ADDRESS                0x00000070
+#define LF_TIMER_CONTROL2_OFFSET                 0x00000070
+#define LF_TIMER_CONTROL2_ENABLE_MSB             2
+#define LF_TIMER_CONTROL2_ENABLE_LSB             2
+#define LF_TIMER_CONTROL2_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL2_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL2_RESET_MSB              0
+#define LF_TIMER_CONTROL2_RESET_LSB              0
+#define LF_TIMER_CONTROL2_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL2_RESET_GET(x)           (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
+#define LF_TIMER_CONTROL2_RESET_SET(x)           (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
+
+#define LF_TIMER_STATUS2_ADDRESS                 0x00000074
+#define LF_TIMER_STATUS2_OFFSET                  0x00000074
+#define LF_TIMER_STATUS2_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define LF_TIMER3_ADDRESS                        0x00000078
+#define LF_TIMER3_OFFSET                         0x00000078
+#define LF_TIMER3_TARGET_MSB                     31
+#define LF_TIMER3_TARGET_LSB                     0
+#define LF_TIMER3_TARGET_MASK                    0xffffffff
+#define LF_TIMER3_TARGET_GET(x)                  (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
+#define LF_TIMER3_TARGET_SET(x)                  (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
+
+#define LF_TIMER_COUNT3_ADDRESS                  0x0000007c
+#define LF_TIMER_COUNT3_OFFSET                   0x0000007c
+#define LF_TIMER_COUNT3_VALUE_MSB                31
+#define LF_TIMER_COUNT3_VALUE_LSB                0
+#define LF_TIMER_COUNT3_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT3_VALUE_GET(x)             (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
+#define LF_TIMER_COUNT3_VALUE_SET(x)             (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
+
+#define LF_TIMER_CONTROL3_ADDRESS                0x00000080
+#define LF_TIMER_CONTROL3_OFFSET                 0x00000080
+#define LF_TIMER_CONTROL3_ENABLE_MSB             2
+#define LF_TIMER_CONTROL3_ENABLE_LSB             2
+#define LF_TIMER_CONTROL3_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL3_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL3_RESET_MSB              0
+#define LF_TIMER_CONTROL3_RESET_LSB              0
+#define LF_TIMER_CONTROL3_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL3_RESET_GET(x)           (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
+#define LF_TIMER_CONTROL3_RESET_SET(x)           (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
+
+#define LF_TIMER_STATUS3_ADDRESS                 0x00000084
+#define LF_TIMER_STATUS3_OFFSET                  0x00000084
+#define LF_TIMER_STATUS3_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define HF_TIMER_ADDRESS                         0x00000088
+#define HF_TIMER_OFFSET                          0x00000088
+#define HF_TIMER_TARGET_MSB                      31
+#define HF_TIMER_TARGET_LSB                      12
+#define HF_TIMER_TARGET_MASK                     0xfffff000
+#define HF_TIMER_TARGET_GET(x)                   (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
+#define HF_TIMER_TARGET_SET(x)                   (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
+
+#define HF_TIMER_COUNT_ADDRESS                   0x0000008c
+#define HF_TIMER_COUNT_OFFSET                    0x0000008c
+#define HF_TIMER_COUNT_VALUE_MSB                 31
+#define HF_TIMER_COUNT_VALUE_LSB                 12
+#define HF_TIMER_COUNT_VALUE_MASK                0xfffff000
+#define HF_TIMER_COUNT_VALUE_GET(x)              (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
+#define HF_TIMER_COUNT_VALUE_SET(x)              (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
+
+#define HF_LF_COUNT_ADDRESS                      0x00000090
+#define HF_LF_COUNT_OFFSET                       0x00000090
+#define HF_LF_COUNT_VALUE_MSB                    31
+#define HF_LF_COUNT_VALUE_LSB                    0
+#define HF_LF_COUNT_VALUE_MASK                   0xffffffff
+#define HF_LF_COUNT_VALUE_GET(x)                 (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
+#define HF_LF_COUNT_VALUE_SET(x)                 (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
+
+#define HF_TIMER_CONTROL_ADDRESS                 0x00000094
+#define HF_TIMER_CONTROL_OFFSET                  0x00000094
+#define HF_TIMER_CONTROL_ENABLE_MSB              3
+#define HF_TIMER_CONTROL_ENABLE_LSB              3
+#define HF_TIMER_CONTROL_ENABLE_MASK             0x00000008
+#define HF_TIMER_CONTROL_ENABLE_GET(x)           (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
+#define HF_TIMER_CONTROL_ENABLE_SET(x)           (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
+#define HF_TIMER_CONTROL_ON_MSB                  2
+#define HF_TIMER_CONTROL_ON_LSB                  2
+#define HF_TIMER_CONTROL_ON_MASK                 0x00000004
+#define HF_TIMER_CONTROL_ON_GET(x)               (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
+#define HF_TIMER_CONTROL_ON_SET(x)               (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK       0x00000002
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x)     (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x)     (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define HF_TIMER_CONTROL_RESET_MSB               0
+#define HF_TIMER_CONTROL_RESET_LSB               0
+#define HF_TIMER_CONTROL_RESET_MASK              0x00000001
+#define HF_TIMER_CONTROL_RESET_GET(x)            (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
+#define HF_TIMER_CONTROL_RESET_SET(x)            (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
+
+#define HF_TIMER_STATUS_ADDRESS                  0x00000098
+#define HF_TIMER_STATUS_OFFSET                   0x00000098
+#define HF_TIMER_STATUS_INTERRUPT_MSB            0
+#define HF_TIMER_STATUS_INTERRUPT_LSB            0
+#define HF_TIMER_STATUS_INTERRUPT_MASK           0x00000001
+#define HF_TIMER_STATUS_INTERRUPT_GET(x)         (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x)         (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define RTC_CONTROL_ADDRESS                      0x0000009c
+#define RTC_CONTROL_OFFSET                       0x0000009c
+#define RTC_CONTROL_ENABLE_MSB                   2
+#define RTC_CONTROL_ENABLE_LSB                   2
+#define RTC_CONTROL_ENABLE_MASK                  0x00000004
+#define RTC_CONTROL_ENABLE_GET(x)                (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
+#define RTC_CONTROL_ENABLE_SET(x)                (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
+#define RTC_CONTROL_LOAD_RTC_MSB                 1
+#define RTC_CONTROL_LOAD_RTC_LSB                 1
+#define RTC_CONTROL_LOAD_RTC_MASK                0x00000002
+#define RTC_CONTROL_LOAD_RTC_GET(x)              (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
+#define RTC_CONTROL_LOAD_RTC_SET(x)              (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
+#define RTC_CONTROL_LOAD_ALARM_MSB               0
+#define RTC_CONTROL_LOAD_ALARM_LSB               0
+#define RTC_CONTROL_LOAD_ALARM_MASK              0x00000001
+#define RTC_CONTROL_LOAD_ALARM_GET(x)            (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
+#define RTC_CONTROL_LOAD_ALARM_SET(x)            (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define RTC_TIME_ADDRESS                         0x000000a0
+#define RTC_TIME_OFFSET                          0x000000a0
+#define RTC_TIME_WEEK_DAY_MSB                    26
+#define RTC_TIME_WEEK_DAY_LSB                    24
+#define RTC_TIME_WEEK_DAY_MASK                   0x07000000
+#define RTC_TIME_WEEK_DAY_GET(x)                 (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
+#define RTC_TIME_WEEK_DAY_SET(x)                 (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
+#define RTC_TIME_HOUR_MSB                        21
+#define RTC_TIME_HOUR_LSB                        16
+#define RTC_TIME_HOUR_MASK                       0x003f0000
+#define RTC_TIME_HOUR_GET(x)                     (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
+#define RTC_TIME_HOUR_SET(x)                     (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
+#define RTC_TIME_MINUTE_MSB                      14
+#define RTC_TIME_MINUTE_LSB                      8
+#define RTC_TIME_MINUTE_MASK                     0x00007f00
+#define RTC_TIME_MINUTE_GET(x)                   (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
+#define RTC_TIME_MINUTE_SET(x)                   (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
+#define RTC_TIME_SECOND_MSB                      6
+#define RTC_TIME_SECOND_LSB                      0
+#define RTC_TIME_SECOND_MASK                     0x0000007f
+#define RTC_TIME_SECOND_GET(x)                   (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
+#define RTC_TIME_SECOND_SET(x)                   (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
+
+#define RTC_DATE_ADDRESS                         0x000000a4
+#define RTC_DATE_OFFSET                          0x000000a4
+#define RTC_DATE_YEAR_MSB                        23
+#define RTC_DATE_YEAR_LSB                        16
+#define RTC_DATE_YEAR_MASK                       0x00ff0000
+#define RTC_DATE_YEAR_GET(x)                     (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
+#define RTC_DATE_YEAR_SET(x)                     (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
+#define RTC_DATE_MONTH_MSB                       12
+#define RTC_DATE_MONTH_LSB                       8
+#define RTC_DATE_MONTH_MASK                      0x00001f00
+#define RTC_DATE_MONTH_GET(x)                    (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
+#define RTC_DATE_MONTH_SET(x)                    (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
+#define RTC_DATE_MONTH_DAY_MSB                   5
+#define RTC_DATE_MONTH_DAY_LSB                   0
+#define RTC_DATE_MONTH_DAY_MASK                  0x0000003f
+#define RTC_DATE_MONTH_DAY_GET(x)                (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
+#define RTC_DATE_MONTH_DAY_SET(x)                (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_TIME_ADDRESS                     0x000000a8
+#define RTC_SET_TIME_OFFSET                      0x000000a8
+#define RTC_SET_TIME_WEEK_DAY_MSB                26
+#define RTC_SET_TIME_WEEK_DAY_LSB                24
+#define RTC_SET_TIME_WEEK_DAY_MASK               0x07000000
+#define RTC_SET_TIME_WEEK_DAY_GET(x)             (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
+#define RTC_SET_TIME_WEEK_DAY_SET(x)             (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
+#define RTC_SET_TIME_HOUR_MSB                    21
+#define RTC_SET_TIME_HOUR_LSB                    16
+#define RTC_SET_TIME_HOUR_MASK                   0x003f0000
+#define RTC_SET_TIME_HOUR_GET(x)                 (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
+#define RTC_SET_TIME_HOUR_SET(x)                 (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
+#define RTC_SET_TIME_MINUTE_MSB                  14
+#define RTC_SET_TIME_MINUTE_LSB                  8
+#define RTC_SET_TIME_MINUTE_MASK                 0x00007f00
+#define RTC_SET_TIME_MINUTE_GET(x)               (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
+#define RTC_SET_TIME_MINUTE_SET(x)               (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
+#define RTC_SET_TIME_SECOND_MSB                  6
+#define RTC_SET_TIME_SECOND_LSB                  0
+#define RTC_SET_TIME_SECOND_MASK                 0x0000007f
+#define RTC_SET_TIME_SECOND_GET(x)               (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
+#define RTC_SET_TIME_SECOND_SET(x)               (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
+
+#define RTC_SET_DATE_ADDRESS                     0x000000ac
+#define RTC_SET_DATE_OFFSET                      0x000000ac
+#define RTC_SET_DATE_YEAR_MSB                    23
+#define RTC_SET_DATE_YEAR_LSB                    16
+#define RTC_SET_DATE_YEAR_MASK                   0x00ff0000
+#define RTC_SET_DATE_YEAR_GET(x)                 (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
+#define RTC_SET_DATE_YEAR_SET(x)                 (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
+#define RTC_SET_DATE_MONTH_MSB                   12
+#define RTC_SET_DATE_MONTH_LSB                   8
+#define RTC_SET_DATE_MONTH_MASK                  0x00001f00
+#define RTC_SET_DATE_MONTH_GET(x)                (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
+#define RTC_SET_DATE_MONTH_SET(x)                (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
+#define RTC_SET_DATE_MONTH_DAY_MSB               5
+#define RTC_SET_DATE_MONTH_DAY_LSB               0
+#define RTC_SET_DATE_MONTH_DAY_MASK              0x0000003f
+#define RTC_SET_DATE_MONTH_DAY_GET(x)            (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
+#define RTC_SET_DATE_MONTH_DAY_SET(x)            (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_ALARM_ADDRESS                    0x000000b0
+#define RTC_SET_ALARM_OFFSET                     0x000000b0
+#define RTC_SET_ALARM_HOUR_MSB                   21
+#define RTC_SET_ALARM_HOUR_LSB                   16
+#define RTC_SET_ALARM_HOUR_MASK                  0x003f0000
+#define RTC_SET_ALARM_HOUR_GET(x)                (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
+#define RTC_SET_ALARM_HOUR_SET(x)                (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
+#define RTC_SET_ALARM_MINUTE_MSB                 14
+#define RTC_SET_ALARM_MINUTE_LSB                 8
+#define RTC_SET_ALARM_MINUTE_MASK                0x00007f00
+#define RTC_SET_ALARM_MINUTE_GET(x)              (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
+#define RTC_SET_ALARM_MINUTE_SET(x)              (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
+#define RTC_SET_ALARM_SECOND_MSB                 6
+#define RTC_SET_ALARM_SECOND_LSB                 0
+#define RTC_SET_ALARM_SECOND_MASK                0x0000007f
+#define RTC_SET_ALARM_SECOND_GET(x)              (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
+#define RTC_SET_ALARM_SECOND_SET(x)              (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
+
+#define RTC_CONFIG_ADDRESS                       0x000000b4
+#define RTC_CONFIG_OFFSET                        0x000000b4
+#define RTC_CONFIG_BCD_MSB                       2
+#define RTC_CONFIG_BCD_LSB                       2
+#define RTC_CONFIG_BCD_MASK                      0x00000004
+#define RTC_CONFIG_BCD_GET(x)                    (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
+#define RTC_CONFIG_BCD_SET(x)                    (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
+#define RTC_CONFIG_TWELVE_HOUR_MSB               1
+#define RTC_CONFIG_TWELVE_HOUR_LSB               1
+#define RTC_CONFIG_TWELVE_HOUR_MASK              0x00000002
+#define RTC_CONFIG_TWELVE_HOUR_GET(x)            (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x)            (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
+#define RTC_CONFIG_DSE_MSB                       0
+#define RTC_CONFIG_DSE_LSB                       0
+#define RTC_CONFIG_DSE_MASK                      0x00000001
+#define RTC_CONFIG_DSE_GET(x)                    (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
+#define RTC_CONFIG_DSE_SET(x)                    (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
+
+#define RTC_ALARM_STATUS_ADDRESS                 0x000000b8
+#define RTC_ALARM_STATUS_OFFSET                  0x000000b8
+#define RTC_ALARM_STATUS_ENABLE_MSB              1
+#define RTC_ALARM_STATUS_ENABLE_LSB              1
+#define RTC_ALARM_STATUS_ENABLE_MASK             0x00000002
+#define RTC_ALARM_STATUS_ENABLE_GET(x)           (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
+#define RTC_ALARM_STATUS_ENABLE_SET(x)           (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_LSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_MASK          0x00000001
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x)        (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x)        (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define UART_WAKEUP_ADDRESS                      0x000000bc
+#define UART_WAKEUP_OFFSET                       0x000000bc
+#define UART_WAKEUP_ENABLE_MSB                   0
+#define UART_WAKEUP_ENABLE_LSB                   0
+#define UART_WAKEUP_ENABLE_MASK                  0x00000001
+#define UART_WAKEUP_ENABLE_GET(x)                (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
+#define UART_WAKEUP_ENABLE_SET(x)                (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
+
+#define RESET_CAUSE_ADDRESS                      0x000000c0
+#define RESET_CAUSE_OFFSET                       0x000000c0
+#define RESET_CAUSE_LAST_MSB                     2
+#define RESET_CAUSE_LAST_LSB                     0
+#define RESET_CAUSE_LAST_MASK                    0x00000007
+#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#define SYSTEM_SLEEP_ADDRESS                     0x000000c4
+#define SYSTEM_SLEEP_OFFSET                      0x000000c4
+#define SYSTEM_SLEEP_HOST_IF_MSB                 4
+#define SYSTEM_SLEEP_HOST_IF_LSB                 4
+#define SYSTEM_SLEEP_HOST_IF_MASK                0x00000010
+#define SYSTEM_SLEEP_HOST_IF_GET(x)              (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
+#define SYSTEM_SLEEP_HOST_IF_SET(x)              (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
+#define SYSTEM_SLEEP_MBOX_MSB                    3
+#define SYSTEM_SLEEP_MBOX_LSB                    3
+#define SYSTEM_SLEEP_MBOX_MASK                   0x00000008
+#define SYSTEM_SLEEP_MBOX_GET(x)                 (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
+#define SYSTEM_SLEEP_MBOX_SET(x)                 (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
+#define SYSTEM_SLEEP_MAC_IF_MSB                  2
+#define SYSTEM_SLEEP_MAC_IF_LSB                  2
+#define SYSTEM_SLEEP_MAC_IF_MASK                 0x00000004
+#define SYSTEM_SLEEP_MAC_IF_GET(x)               (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
+#define SYSTEM_SLEEP_MAC_IF_SET(x)               (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
+#define SYSTEM_SLEEP_LIGHT_MSB                   1
+#define SYSTEM_SLEEP_LIGHT_LSB                   1
+#define SYSTEM_SLEEP_LIGHT_MASK                  0x00000002
+#define SYSTEM_SLEEP_LIGHT_GET(x)                (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
+#define SYSTEM_SLEEP_LIGHT_SET(x)                (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
+#define SYSTEM_SLEEP_DISABLE_MSB                 0
+#define SYSTEM_SLEEP_DISABLE_LSB                 0
+#define SYSTEM_SLEEP_DISABLE_MASK                0x00000001
+#define SYSTEM_SLEEP_DISABLE_GET(x)              (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SDIO_WRAPPER_ADDRESS                     0x000000c8
+#define SDIO_WRAPPER_OFFSET                      0x000000c8
+#define SDIO_WRAPPER_SLEEP_MSB                   3
+#define SDIO_WRAPPER_SLEEP_LSB                   3
+#define SDIO_WRAPPER_SLEEP_MASK                  0x00000008
+#define SDIO_WRAPPER_SLEEP_GET(x)                (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
+#define SDIO_WRAPPER_SLEEP_SET(x)                (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
+#define SDIO_WRAPPER_WAKEUP_MSB                  2
+#define SDIO_WRAPPER_WAKEUP_LSB                  2
+#define SDIO_WRAPPER_WAKEUP_MASK                 0x00000004
+#define SDIO_WRAPPER_WAKEUP_GET(x)               (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
+#define SDIO_WRAPPER_WAKEUP_SET(x)               (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
+#define SDIO_WRAPPER_SOC_ON_MSB                  1
+#define SDIO_WRAPPER_SOC_ON_LSB                  1
+#define SDIO_WRAPPER_SOC_ON_MASK                 0x00000002
+#define SDIO_WRAPPER_SOC_ON_GET(x)               (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
+#define SDIO_WRAPPER_SOC_ON_SET(x)               (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
+#define SDIO_WRAPPER_ON_MSB                      0
+#define SDIO_WRAPPER_ON_LSB                      0
+#define SDIO_WRAPPER_ON_MASK                     0x00000001
+#define SDIO_WRAPPER_ON_GET(x)                   (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
+#define SDIO_WRAPPER_ON_SET(x)                   (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
+
+#define MAC_SLEEP_CONTROL_ADDRESS                0x000000cc
+#define MAC_SLEEP_CONTROL_OFFSET                 0x000000cc
+#define MAC_SLEEP_CONTROL_ENABLE_MSB             1
+#define MAC_SLEEP_CONTROL_ENABLE_LSB             0
+#define MAC_SLEEP_CONTROL_ENABLE_MASK            0x00000003
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x)          (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x)          (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define KEEP_AWAKE_ADDRESS                       0x000000d0
+#define KEEP_AWAKE_OFFSET                        0x000000d0
+#define KEEP_AWAKE_COUNT_MSB                     7
+#define KEEP_AWAKE_COUNT_LSB                     0
+#define KEEP_AWAKE_COUNT_MASK                    0x000000ff
+#define KEEP_AWAKE_COUNT_GET(x)                  (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
+#define KEEP_AWAKE_COUNT_SET(x)                  (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
+
+#define LPO_CAL_TIME_ADDRESS                     0x000000d4
+#define LPO_CAL_TIME_OFFSET                      0x000000d4
+#define LPO_CAL_TIME_LENGTH_MSB                  13
+#define LPO_CAL_TIME_LENGTH_LSB                  0
+#define LPO_CAL_TIME_LENGTH_MASK                 0x00003fff
+#define LPO_CAL_TIME_LENGTH_GET(x)               (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
+#define LPO_CAL_TIME_LENGTH_SET(x)               (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
+
+#define LPO_INIT_DIVIDEND_INT_ADDRESS            0x000000d8
+#define LPO_INIT_DIVIDEND_INT_OFFSET             0x000000d8
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB          23
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB          0
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK         0x00ffffff
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x)       (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x)       (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS       0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET        0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB     10
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB     0
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK    0x000007ff
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)  (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)  (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define LPO_CAL_ADDRESS                          0x000000e0
+#define LPO_CAL_OFFSET                           0x000000e0
+#define LPO_CAL_ENABLE_MSB                       20
+#define LPO_CAL_ENABLE_LSB                       20
+#define LPO_CAL_ENABLE_MASK                      0x00100000
+#define LPO_CAL_ENABLE_GET(x)                    (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_SET(x)                    (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define LPO_CAL_COUNT_MSB                        19
+#define LPO_CAL_COUNT_LSB                        0
+#define LPO_CAL_COUNT_MASK                       0x000fffff
+#define LPO_CAL_COUNT_GET(x)                     (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
+#define LPO_CAL_COUNT_SET(x)                     (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
+
+#define LPO_CAL_TEST_CONTROL_ADDRESS             0x000000e4
+#define LPO_CAL_TEST_CONTROL_OFFSET              0x000000e4
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK         0x00000020
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x)       (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x)       (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB      4
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB      0
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK     0x0000001f
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)   (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)   (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define LPO_CAL_TEST_STATUS_ADDRESS              0x000000e8
+#define LPO_CAL_TEST_STATUS_OFFSET               0x000000e8
+#define LPO_CAL_TEST_STATUS_READY_MSB            16
+#define LPO_CAL_TEST_STATUS_READY_LSB            16
+#define LPO_CAL_TEST_STATUS_READY_MASK           0x00010000
+#define LPO_CAL_TEST_STATUS_READY_GET(x)         (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
+#define LPO_CAL_TEST_STATUS_READY_SET(x)         (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB            15
+#define LPO_CAL_TEST_STATUS_COUNT_LSB            0
+#define LPO_CAL_TEST_STATUS_COUNT_MASK           0x0000ffff
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x)         (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x)         (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define CHIP_ID_ADDRESS                          0x000000ec
+#define CHIP_ID_OFFSET                           0x000000ec
+#define CHIP_ID_DEVICE_ID_MSB                    31
+#define CHIP_ID_DEVICE_ID_LSB                    16
+#define CHIP_ID_DEVICE_ID_MASK                   0xffff0000
+#define CHIP_ID_DEVICE_ID_GET(x)                 (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
+#define CHIP_ID_DEVICE_ID_SET(x)                 (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
+#define CHIP_ID_CONFIG_ID_MSB                    15
+#define CHIP_ID_CONFIG_ID_LSB                    4
+#define CHIP_ID_CONFIG_ID_MASK                   0x0000fff0
+#define CHIP_ID_CONFIG_ID_GET(x)                 (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
+#define CHIP_ID_CONFIG_ID_SET(x)                 (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
+#define CHIP_ID_VERSION_ID_MSB                   3
+#define CHIP_ID_VERSION_ID_LSB                   0
+#define CHIP_ID_VERSION_ID_MASK                  0x0000000f
+#define CHIP_ID_VERSION_ID_GET(x)                (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
+#define CHIP_ID_VERSION_ID_SET(x)                (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
+
+#define DERIVED_RTC_CLK_ADDRESS                  0x000000f0
+#define DERIVED_RTC_CLK_OFFSET                   0x000000f0
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK  0x00100000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK     0x00040000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)   (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)   (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define DERIVED_RTC_CLK_FORCE_MSB                17
+#define DERIVED_RTC_CLK_FORCE_LSB                16
+#define DERIVED_RTC_CLK_FORCE_MASK               0x00030000
+#define DERIVED_RTC_CLK_FORCE_GET(x)             (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
+#define DERIVED_RTC_CLK_FORCE_SET(x)             (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
+#define DERIVED_RTC_CLK_PERIOD_MSB               15
+#define DERIVED_RTC_CLK_PERIOD_LSB               1
+#define DERIVED_RTC_CLK_PERIOD_MASK              0x0000fffe
+#define DERIVED_RTC_CLK_PERIOD_GET(x)            (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
+#define DERIVED_RTC_CLK_PERIOD_SET(x)            (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS               0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET                0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB  19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB  0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS               0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET                0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB          15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB          0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK         0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x)       (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x)       (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS                0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET                 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB            19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB            0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK           0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x)         (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x)         (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS                 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET                  0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB           31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB           0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS                 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET                  0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB           31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB           0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS                 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET                  0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK            0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x)          (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x)          (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK            0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x)          (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x)          (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define MAC_PCU_SLP_BEACON_ADDRESS               0x0000010c
+#define MAC_PCU_SLP_BEACON_OFFSET                0x0000010c
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB     23
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB     0
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK    0x00ffffff
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x)  (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x)  (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
+
+#define POWER_REG_ADDRESS                        0x00000110
+#define POWER_REG_OFFSET                         0x00000110
+#define POWER_REG_VLVL_MSB                       11
+#define POWER_REG_VLVL_LSB                       8
+#define POWER_REG_VLVL_MASK                      0x00000f00
+#define POWER_REG_VLVL_GET(x)                    (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
+#define POWER_REG_VLVL_SET(x)                    (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
+#define POWER_REG_CPU_INT_ENABLE_MSB             7
+#define POWER_REG_CPU_INT_ENABLE_LSB             7
+#define POWER_REG_CPU_INT_ENABLE_MASK            0x00000080
+#define POWER_REG_CPU_INT_ENABLE_GET(x)          (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
+#define POWER_REG_CPU_INT_ENABLE_SET(x)          (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
+#define POWER_REG_WLAN_ISO_DIS_MSB               6
+#define POWER_REG_WLAN_ISO_DIS_LSB               6
+#define POWER_REG_WLAN_ISO_DIS_MASK              0x00000040
+#define POWER_REG_WLAN_ISO_DIS_GET(x)            (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
+#define POWER_REG_WLAN_ISO_DIS_SET(x)            (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
+#define POWER_REG_WLAN_ISO_CNTL_MSB              5
+#define POWER_REG_WLAN_ISO_CNTL_LSB              5
+#define POWER_REG_WLAN_ISO_CNTL_MASK             0x00000020
+#define POWER_REG_WLAN_ISO_CNTL_GET(x)           (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x)           (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
+#define POWER_REG_RADIO_PWD_EN_MSB               4
+#define POWER_REG_RADIO_PWD_EN_LSB               4
+#define POWER_REG_RADIO_PWD_EN_MASK              0x00000010
+#define POWER_REG_RADIO_PWD_EN_GET(x)            (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
+#define POWER_REG_RADIO_PWD_EN_SET(x)            (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
+#define POWER_REG_SOC_SCALE_EN_MSB               3
+#define POWER_REG_SOC_SCALE_EN_LSB               3
+#define POWER_REG_SOC_SCALE_EN_MASK              0x00000008
+#define POWER_REG_SOC_SCALE_EN_GET(x)            (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
+#define POWER_REG_SOC_SCALE_EN_SET(x)            (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
+#define POWER_REG_WLAN_SCALE_EN_MSB              2
+#define POWER_REG_WLAN_SCALE_EN_LSB              2
+#define POWER_REG_WLAN_SCALE_EN_MASK             0x00000004
+#define POWER_REG_WLAN_SCALE_EN_GET(x)           (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
+#define POWER_REG_WLAN_SCALE_EN_SET(x)           (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
+#define POWER_REG_WLAN_PWD_EN_MSB                1
+#define POWER_REG_WLAN_PWD_EN_LSB                1
+#define POWER_REG_WLAN_PWD_EN_MASK               0x00000002
+#define POWER_REG_WLAN_PWD_EN_GET(x)             (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
+#define POWER_REG_WLAN_PWD_EN_SET(x)             (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
+#define POWER_REG_POWER_EN_MSB                   0
+#define POWER_REG_POWER_EN_LSB                   0
+#define POWER_REG_POWER_EN_MASK                  0x00000001
+#define POWER_REG_POWER_EN_GET(x)                (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
+#define POWER_REG_POWER_EN_SET(x)                (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
+
+#define CORE_CLK_CTRL_ADDRESS                    0x00000114
+#define CORE_CLK_CTRL_OFFSET                     0x00000114
+#define CORE_CLK_CTRL_DIV_MSB                    2
+#define CORE_CLK_CTRL_DIV_LSB                    0
+#define CORE_CLK_CTRL_DIV_MASK                   0x00000007
+#define CORE_CLK_CTRL_DIV_GET(x)                 (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
+#define CORE_CLK_CTRL_DIV_SET(x)                 (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
+
+#define SDIO_SETUP_CIRCUIT_ADDRESS               0x00000120
+#define SDIO_SETUP_CIRCUIT_OFFSET                0x00000120
+#define SDIO_SETUP_CIRCUIT_VECTOR_MSB            7
+#define SDIO_SETUP_CIRCUIT_VECTOR_LSB            0
+#define SDIO_SETUP_CIRCUIT_VECTOR_MASK           0x000000ff
+#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x)         (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
+#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x)         (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define SDIO_SETUP_CONFIG_ADDRESS                0x00000140
+#define SDIO_SETUP_CONFIG_OFFSET                 0x00000140
+#define SDIO_SETUP_CONFIG_ENABLE_MSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_LSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_MASK            0x00000002
+#define SDIO_SETUP_CONFIG_ENABLE_GET(x)          (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
+#define SDIO_SETUP_CONFIG_ENABLE_SET(x)          (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
+#define SDIO_SETUP_CONFIG_CLEAR_MSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_LSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_MASK             0x00000001
+#define SDIO_SETUP_CONFIG_CLEAR_GET(x)           (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
+#define SDIO_SETUP_CONFIG_CLEAR_SET(x)           (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CONFIG_ADDRESS                 0x00000144
+#define CPU_SETUP_CONFIG_OFFSET                  0x00000144
+#define CPU_SETUP_CONFIG_ENABLE_MSB              1
+#define CPU_SETUP_CONFIG_ENABLE_LSB              1
+#define CPU_SETUP_CONFIG_ENABLE_MASK             0x00000002
+#define CPU_SETUP_CONFIG_ENABLE_GET(x)           (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
+#define CPU_SETUP_CONFIG_ENABLE_SET(x)           (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
+#define CPU_SETUP_CONFIG_CLEAR_MSB               0
+#define CPU_SETUP_CONFIG_CLEAR_LSB               0
+#define CPU_SETUP_CONFIG_CLEAR_MASK              0x00000001
+#define CPU_SETUP_CONFIG_CLEAR_GET(x)            (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
+#define CPU_SETUP_CONFIG_CLEAR_SET(x)            (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CIRCUIT_ADDRESS                0x00000160
+#define CPU_SETUP_CIRCUIT_OFFSET                 0x00000160
+#define CPU_SETUP_CIRCUIT_VECTOR_MSB             7
+#define CPU_SETUP_CIRCUIT_VECTOR_LSB             0
+#define CPU_SETUP_CIRCUIT_VECTOR_MASK            0x000000ff
+#define CPU_SETUP_CIRCUIT_VECTOR_GET(x)          (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
+#define CPU_SETUP_CIRCUIT_VECTOR_SET(x)          (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define BB_SETUP_CONFIG_ADDRESS                  0x00000180
+#define BB_SETUP_CONFIG_OFFSET                   0x00000180
+#define BB_SETUP_CONFIG_ENABLE_MSB               1
+#define BB_SETUP_CONFIG_ENABLE_LSB               1
+#define BB_SETUP_CONFIG_ENABLE_MASK              0x00000002
+#define BB_SETUP_CONFIG_ENABLE_GET(x)            (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
+#define BB_SETUP_CONFIG_ENABLE_SET(x)            (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
+#define BB_SETUP_CONFIG_CLEAR_MSB                0
+#define BB_SETUP_CONFIG_CLEAR_LSB                0
+#define BB_SETUP_CONFIG_CLEAR_MASK               0x00000001
+#define BB_SETUP_CONFIG_CLEAR_GET(x)             (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
+#define BB_SETUP_CONFIG_CLEAR_SET(x)             (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
+
+#define BB_SETUP_CIRCUIT_ADDRESS                 0x000001a0
+#define BB_SETUP_CIRCUIT_OFFSET                  0x000001a0
+#define BB_SETUP_CIRCUIT_VECTOR_MSB              7
+#define BB_SETUP_CIRCUIT_VECTOR_LSB              0
+#define BB_SETUP_CIRCUIT_VECTOR_MASK             0x000000ff
+#define BB_SETUP_CIRCUIT_VECTOR_GET(x)           (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
+#define BB_SETUP_CIRCUIT_VECTOR_SET(x)           (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define GPIO_WAKEUP_CONTROL_ADDRESS              0x000001c0
+#define GPIO_WAKEUP_CONTROL_OFFSET               0x000001c0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK          0x00000001
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x)        (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x)        (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_reg_reg_s {
+  volatile unsigned int reset_control;
+  volatile unsigned int xtal_control;
+  volatile unsigned int tcxo_detect;
+  volatile unsigned int xtal_test;
+  volatile unsigned int quadrature;
+  volatile unsigned int pll_control;
+  volatile unsigned int pll_settle;
+  volatile unsigned int xtal_settle;
+  volatile unsigned int cpu_clock;
+  volatile unsigned int clock_out;
+  volatile unsigned int clock_control;
+  volatile unsigned int bias_override;
+  volatile unsigned int wdt_control;
+  volatile unsigned int wdt_status;
+  volatile unsigned int wdt;
+  volatile unsigned int wdt_count;
+  volatile unsigned int wdt_reset;
+  volatile unsigned int int_status;
+  volatile unsigned int lf_timer0;
+  volatile unsigned int lf_timer_count0;
+  volatile unsigned int lf_timer_control0;
+  volatile unsigned int lf_timer_status0;
+  volatile unsigned int lf_timer1;
+  volatile unsigned int lf_timer_count1;
+  volatile unsigned int lf_timer_control1;
+  volatile unsigned int lf_timer_status1;
+  volatile unsigned int lf_timer2;
+  volatile unsigned int lf_timer_count2;
+  volatile unsigned int lf_timer_control2;
+  volatile unsigned int lf_timer_status2;
+  volatile unsigned int lf_timer3;
+  volatile unsigned int lf_timer_count3;
+  volatile unsigned int lf_timer_control3;
+  volatile unsigned int lf_timer_status3;
+  volatile unsigned int hf_timer;
+  volatile unsigned int hf_timer_count;
+  volatile unsigned int hf_lf_count;
+  volatile unsigned int hf_timer_control;
+  volatile unsigned int hf_timer_status;
+  volatile unsigned int rtc_control;
+  volatile unsigned int rtc_time;
+  volatile unsigned int rtc_date;
+  volatile unsigned int rtc_set_time;
+  volatile unsigned int rtc_set_date;
+  volatile unsigned int rtc_set_alarm;
+  volatile unsigned int rtc_config;
+  volatile unsigned int rtc_alarm_status;
+  volatile unsigned int uart_wakeup;
+  volatile unsigned int reset_cause;
+  volatile unsigned int system_sleep;
+  volatile unsigned int sdio_wrapper;
+  volatile unsigned int mac_sleep_control;
+  volatile unsigned int keep_awake;
+  volatile unsigned int lpo_cal_time;
+  volatile unsigned int lpo_init_dividend_int;
+  volatile unsigned int lpo_init_dividend_fraction;
+  volatile unsigned int lpo_cal;
+  volatile unsigned int lpo_cal_test_control;
+  volatile unsigned int lpo_cal_test_status;
+  volatile unsigned int chip_id;
+  volatile unsigned int derived_rtc_clk;
+  volatile unsigned int mac_pcu_slp32_mode;
+  volatile unsigned int mac_pcu_slp32_wake;
+  volatile unsigned int mac_pcu_slp32_inc;
+  volatile unsigned int mac_pcu_slp_mib1;
+  volatile unsigned int mac_pcu_slp_mib2;
+  volatile unsigned int mac_pcu_slp_mib3;
+  volatile unsigned int mac_pcu_slp_beacon;
+  volatile unsigned int power_reg;
+  volatile unsigned int core_clk_ctrl;
+  unsigned char pad0[8]; /* pad to 0x120 */
+  volatile unsigned int sdio_setup_circuit[8];
+  volatile unsigned int sdio_setup_config;
+  volatile unsigned int cpu_setup_config;
+  unsigned char pad1[24]; /* pad to 0x160 */
+  volatile unsigned int cpu_setup_circuit[8];
+  volatile unsigned int bb_setup_config;
+  unsigned char pad2[28]; /* pad to 0x1a0 */
+  volatile unsigned int bb_setup_circuit[8];
+  volatile unsigned int gpio_wakeup_control;
+} rtc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS                        0x00000000
+#define SI_CONFIG_OFFSET                         0x00000000
+#define SI_CONFIG_ERR_INT_MSB                    19
+#define SI_CONFIG_ERR_INT_LSB                    19
+#define SI_CONFIG_ERR_INT_MASK                   0x00080000
+#define SI_CONFIG_ERR_INT_GET(x)                 (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x)                 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x)           (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x)           (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB                        16
+#define SI_CONFIG_I2C_LSB                        16
+#define SI_CONFIG_I2C_MASK                       0x00010000
+#define SI_CONFIG_I2C_GET(x)                     (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x)                     (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB                 7
+#define SI_CONFIG_POS_SAMPLE_LSB                 7
+#define SI_CONFIG_POS_SAMPLE_MASK                0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x)              (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x)              (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB                  6
+#define SI_CONFIG_POS_DRIVE_LSB                  6
+#define SI_CONFIG_POS_DRIVE_MASK                 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x)               (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x)               (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB              5
+#define SI_CONFIG_INACTIVE_DATA_LSB              5
+#define SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x)           (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x)           (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB               4
+#define SI_CONFIG_INACTIVE_CLK_LSB               4
+#define SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x)            (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x)            (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB                    3
+#define SI_CONFIG_DIVIDER_LSB                    0
+#define SI_CONFIG_DIVIDER_MASK                   0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x)                 (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x)                 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS                            0x00000004
+#define SI_CS_OFFSET                             0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB           13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB           11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK          0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x)        (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x)        (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB                       10
+#define SI_CS_DONE_ERR_LSB                       10
+#define SI_CS_DONE_ERR_MASK                      0x00000400
+#define SI_CS_DONE_ERR_GET(x)                    (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x)                    (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB                       9
+#define SI_CS_DONE_INT_LSB                       9
+#define SI_CS_DONE_INT_MASK                      0x00000200
+#define SI_CS_DONE_INT_GET(x)                    (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x)                    (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB                          8
+#define SI_CS_START_LSB                          8
+#define SI_CS_START_MASK                         0x00000100
+#define SI_CS_START_GET(x)                       (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x)                       (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB                         7
+#define SI_CS_RX_CNT_LSB                         4
+#define SI_CS_RX_CNT_MASK                        0x000000f0
+#define SI_CS_RX_CNT_GET(x)                      (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x)                      (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB                         3
+#define SI_CS_TX_CNT_LSB                         0
+#define SI_CS_TX_CNT_MASK                        0x0000000f
+#define SI_CS_TX_CNT_GET(x)                      (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x)                      (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS                      0x00000008
+#define SI_TX_DATA0_OFFSET                       0x00000008
+#define SI_TX_DATA0_DATA3_MSB                    31
+#define SI_TX_DATA0_DATA3_LSB                    24
+#define SI_TX_DATA0_DATA3_MASK                   0xff000000
+#define SI_TX_DATA0_DATA3_GET(x)                 (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x)                 (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB                    23
+#define SI_TX_DATA0_DATA2_LSB                    16
+#define SI_TX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x)                 (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x)                 (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB                    15
+#define SI_TX_DATA0_DATA1_LSB                    8
+#define SI_TX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x)                 (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x)                 (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB                    7
+#define SI_TX_DATA0_DATA0_LSB                    0
+#define SI_TX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x)                 (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x)                 (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS                      0x0000000c
+#define SI_TX_DATA1_OFFSET                       0x0000000c
+#define SI_TX_DATA1_DATA7_MSB                    31
+#define SI_TX_DATA1_DATA7_LSB                    24
+#define SI_TX_DATA1_DATA7_MASK                   0xff000000
+#define SI_TX_DATA1_DATA7_GET(x)                 (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x)                 (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB                    23
+#define SI_TX_DATA1_DATA6_LSB                    16
+#define SI_TX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x)                 (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x)                 (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB                    15
+#define SI_TX_DATA1_DATA5_LSB                    8
+#define SI_TX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x)                 (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x)                 (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB                    7
+#define SI_TX_DATA1_DATA4_LSB                    0
+#define SI_TX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x)                 (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x)                 (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS                      0x00000010
+#define SI_RX_DATA0_OFFSET                       0x00000010
+#define SI_RX_DATA0_DATA3_MSB                    31
+#define SI_RX_DATA0_DATA3_LSB                    24
+#define SI_RX_DATA0_DATA3_MASK                   0xff000000
+#define SI_RX_DATA0_DATA3_GET(x)                 (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x)                 (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB                    23
+#define SI_RX_DATA0_DATA2_LSB                    16
+#define SI_RX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x)                 (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x)                 (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB                    15
+#define SI_RX_DATA0_DATA1_LSB                    8
+#define SI_RX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x)                 (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x)                 (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB                    7
+#define SI_RX_DATA0_DATA0_LSB                    0
+#define SI_RX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x)                 (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x)                 (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS                      0x00000014
+#define SI_RX_DATA1_OFFSET                       0x00000014
+#define SI_RX_DATA1_DATA7_MSB                    31
+#define SI_RX_DATA1_DATA7_LSB                    24
+#define SI_RX_DATA1_DATA7_MASK                   0xff000000
+#define SI_RX_DATA1_DATA7_GET(x)                 (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x)                 (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB                    23
+#define SI_RX_DATA1_DATA6_LSB                    16
+#define SI_RX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x)                 (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x)                 (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB                    15
+#define SI_RX_DATA1_DATA5_LSB                    8
+#define SI_RX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x)                 (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x)                 (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB                    7
+#define SI_RX_DATA1_DATA4_LSB                    0
+#define SI_RX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x)                 (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x)                 (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+  volatile unsigned int si_config;
+  volatile unsigned int si_cs;
+  volatile unsigned int si_tx_data0;
+  volatile unsigned int si_tx_data1;
+  volatile unsigned int si_rx_data0;
+  volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h
new file mode 100644
index 000000000000..db573106dcd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h
@@ -0,0 +1,346 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define RBR_ADDRESS                              0x00000000
+#define RBR_OFFSET                               0x00000000
+#define RBR_RBR_MSB                              7
+#define RBR_RBR_LSB                              0
+#define RBR_RBR_MASK                             0x000000ff
+#define RBR_RBR_GET(x)                           (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
+#define RBR_RBR_SET(x)                           (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
+
+#define THR_ADDRESS                              0x00000000
+#define THR_OFFSET                               0x00000000
+#define THR_THR_MSB                              7
+#define THR_THR_LSB                              0
+#define THR_THR_MASK                             0x000000ff
+#define THR_THR_GET(x)                           (((x) & THR_THR_MASK) >> THR_THR_LSB)
+#define THR_THR_SET(x)                           (((x) << THR_THR_LSB) & THR_THR_MASK)
+
+#define DLL_ADDRESS                              0x00000000
+#define DLL_OFFSET                               0x00000000
+#define DLL_DLL_MSB                              7
+#define DLL_DLL_LSB                              0
+#define DLL_DLL_MASK                             0x000000ff
+#define DLL_DLL_GET(x)                           (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
+#define DLL_DLL_SET(x)                           (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
+
+#define DLH_ADDRESS                              0x00000004
+#define DLH_OFFSET                               0x00000004
+#define DLH_DLH_MSB                              7
+#define DLH_DLH_LSB                              0
+#define DLH_DLH_MASK                             0x000000ff
+#define DLH_DLH_GET(x)                           (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
+#define DLH_DLH_SET(x)                           (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
+
+#define IER_ADDRESS                              0x00000004
+#define IER_OFFSET                               0x00000004
+#define IER_EDDSI_MSB                            3
+#define IER_EDDSI_LSB                            3
+#define IER_EDDSI_MASK                           0x00000008
+#define IER_EDDSI_GET(x)                         (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
+#define IER_EDDSI_SET(x)                         (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
+#define IER_ELSI_MSB                             2
+#define IER_ELSI_LSB                             2
+#define IER_ELSI_MASK                            0x00000004
+#define IER_ELSI_GET(x)                          (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
+#define IER_ELSI_SET(x)                          (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
+#define IER_ETBEI_MSB                            1
+#define IER_ETBEI_LSB                            1
+#define IER_ETBEI_MASK                           0x00000002
+#define IER_ETBEI_GET(x)                         (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
+#define IER_ETBEI_SET(x)                         (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
+#define IER_ERBFI_MSB                            0
+#define IER_ERBFI_LSB                            0
+#define IER_ERBFI_MASK                           0x00000001
+#define IER_ERBFI_GET(x)                         (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
+#define IER_ERBFI_SET(x)                         (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
+
+#define IIR_ADDRESS                              0x00000008
+#define IIR_OFFSET                               0x00000008
+#define IIR_FIFO_STATUS_MSB                      7
+#define IIR_FIFO_STATUS_LSB                      6
+#define IIR_FIFO_STATUS_MASK                     0x000000c0
+#define IIR_FIFO_STATUS_GET(x)                   (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
+#define IIR_FIFO_STATUS_SET(x)                   (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
+#define IIR_IID_MSB                              3
+#define IIR_IID_LSB                              0
+#define IIR_IID_MASK                             0x0000000f
+#define IIR_IID_GET(x)                           (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
+#define IIR_IID_SET(x)                           (((x) << IIR_IID_LSB) & IIR_IID_MASK)
+
+#define FCR_ADDRESS                              0x00000008
+#define FCR_OFFSET                               0x00000008
+#define FCR_RCVR_TRIG_MSB                        7
+#define FCR_RCVR_TRIG_LSB                        6
+#define FCR_RCVR_TRIG_MASK                       0x000000c0
+#define FCR_RCVR_TRIG_GET(x)                     (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
+#define FCR_RCVR_TRIG_SET(x)                     (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
+#define FCR_DMA_MODE_MSB                         3
+#define FCR_DMA_MODE_LSB                         3
+#define FCR_DMA_MODE_MASK                        0x00000008
+#define FCR_DMA_MODE_GET(x)                      (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
+#define FCR_DMA_MODE_SET(x)                      (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
+#define FCR_XMIT_FIFO_RST_MSB                    2
+#define FCR_XMIT_FIFO_RST_LSB                    2
+#define FCR_XMIT_FIFO_RST_MASK                   0x00000004
+#define FCR_XMIT_FIFO_RST_GET(x)                 (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
+#define FCR_XMIT_FIFO_RST_SET(x)                 (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
+#define FCR_RCVR_FIFO_RST_MSB                    1
+#define FCR_RCVR_FIFO_RST_LSB                    1
+#define FCR_RCVR_FIFO_RST_MASK                   0x00000002
+#define FCR_RCVR_FIFO_RST_GET(x)                 (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
+#define FCR_RCVR_FIFO_RST_SET(x)                 (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
+#define FCR_FIFO_EN_MSB                          0
+#define FCR_FIFO_EN_LSB                          0
+#define FCR_FIFO_EN_MASK                         0x00000001
+#define FCR_FIFO_EN_GET(x)                       (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
+#define FCR_FIFO_EN_SET(x)                       (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
+
+#define LCR_ADDRESS                              0x0000000c
+#define LCR_OFFSET                               0x0000000c
+#define LCR_DLAB_MSB                             7
+#define LCR_DLAB_LSB                             7
+#define LCR_DLAB_MASK                            0x00000080
+#define LCR_DLAB_GET(x)                          (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
+#define LCR_DLAB_SET(x)                          (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
+#define LCR_BREAK_MSB                            6
+#define LCR_BREAK_LSB                            6
+#define LCR_BREAK_MASK                           0x00000040
+#define LCR_BREAK_GET(x)                         (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
+#define LCR_BREAK_SET(x)                         (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
+#define LCR_EPS_MSB                              4
+#define LCR_EPS_LSB                              4
+#define LCR_EPS_MASK                             0x00000010
+#define LCR_EPS_GET(x)                           (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
+#define LCR_EPS_SET(x)                           (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
+#define LCR_PEN_MSB                              3
+#define LCR_PEN_LSB                              3
+#define LCR_PEN_MASK                             0x00000008
+#define LCR_PEN_GET(x)                           (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
+#define LCR_PEN_SET(x)                           (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
+#define LCR_STOP_MSB                             2
+#define LCR_STOP_LSB                             2
+#define LCR_STOP_MASK                            0x00000004
+#define LCR_STOP_GET(x)                          (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
+#define LCR_STOP_SET(x)                          (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
+#define LCR_CLS_MSB                              1
+#define LCR_CLS_LSB                              0
+#define LCR_CLS_MASK                             0x00000003
+#define LCR_CLS_GET(x)                           (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
+#define LCR_CLS_SET(x)                           (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
+
+#define MCR_ADDRESS                              0x00000010
+#define MCR_OFFSET                               0x00000010
+#define MCR_LOOPBACK_MSB                         5
+#define MCR_LOOPBACK_LSB                         5
+#define MCR_LOOPBACK_MASK                        0x00000020
+#define MCR_LOOPBACK_GET(x)                      (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
+#define MCR_LOOPBACK_SET(x)                      (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
+#define MCR_OUT2_MSB                             3
+#define MCR_OUT2_LSB                             3
+#define MCR_OUT2_MASK                            0x00000008
+#define MCR_OUT2_GET(x)                          (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
+#define MCR_OUT2_SET(x)                          (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
+#define MCR_OUT1_MSB                             2
+#define MCR_OUT1_LSB                             2
+#define MCR_OUT1_MASK                            0x00000004
+#define MCR_OUT1_GET(x)                          (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
+#define MCR_OUT1_SET(x)                          (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
+#define MCR_RTS_MSB                              1
+#define MCR_RTS_LSB                              1
+#define MCR_RTS_MASK                             0x00000002
+#define MCR_RTS_GET(x)                           (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
+#define MCR_RTS_SET(x)                           (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
+#define MCR_DTR_MSB                              0
+#define MCR_DTR_LSB                              0
+#define MCR_DTR_MASK                             0x00000001
+#define MCR_DTR_GET(x)                           (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
+#define MCR_DTR_SET(x)                           (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
+
+#define LSR_ADDRESS                              0x00000014
+#define LSR_OFFSET                               0x00000014
+#define LSR_FERR_MSB                             7
+#define LSR_FERR_LSB                             7
+#define LSR_FERR_MASK                            0x00000080
+#define LSR_FERR_GET(x)                          (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
+#define LSR_FERR_SET(x)                          (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
+#define LSR_TEMT_MSB                             6
+#define LSR_TEMT_LSB                             6
+#define LSR_TEMT_MASK                            0x00000040
+#define LSR_TEMT_GET(x)                          (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
+#define LSR_TEMT_SET(x)                          (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
+#define LSR_THRE_MSB                             5
+#define LSR_THRE_LSB                             5
+#define LSR_THRE_MASK                            0x00000020
+#define LSR_THRE_GET(x)                          (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
+#define LSR_THRE_SET(x)                          (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
+#define LSR_BI_MSB                               4
+#define LSR_BI_LSB                               4
+#define LSR_BI_MASK                              0x00000010
+#define LSR_BI_GET(x)                            (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
+#define LSR_BI_SET(x)                            (((x) << LSR_BI_LSB) & LSR_BI_MASK)
+#define LSR_FE_MSB                               3
+#define LSR_FE_LSB                               3
+#define LSR_FE_MASK                              0x00000008
+#define LSR_FE_GET(x)                            (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
+#define LSR_FE_SET(x)                            (((x) << LSR_FE_LSB) & LSR_FE_MASK)
+#define LSR_PE_MSB                               2
+#define LSR_PE_LSB                               2
+#define LSR_PE_MASK                              0x00000004
+#define LSR_PE_GET(x)                            (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
+#define LSR_PE_SET(x)                            (((x) << LSR_PE_LSB) & LSR_PE_MASK)
+#define LSR_OE_MSB                               1
+#define LSR_OE_LSB                               1
+#define LSR_OE_MASK                              0x00000002
+#define LSR_OE_GET(x)                            (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
+#define LSR_OE_SET(x)                            (((x) << LSR_OE_LSB) & LSR_OE_MASK)
+#define LSR_DR_MSB                               0
+#define LSR_DR_LSB                               0
+#define LSR_DR_MASK                              0x00000001
+#define LSR_DR_GET(x)                            (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
+#define LSR_DR_SET(x)                            (((x) << LSR_DR_LSB) & LSR_DR_MASK)
+
+#define MSR_ADDRESS                              0x00000018
+#define MSR_OFFSET                               0x00000018
+#define MSR_DCD_MSB                              7
+#define MSR_DCD_LSB                              7
+#define MSR_DCD_MASK                             0x00000080
+#define MSR_DCD_GET(x)                           (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
+#define MSR_DCD_SET(x)                           (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
+#define MSR_RI_MSB                               6
+#define MSR_RI_LSB                               6
+#define MSR_RI_MASK                              0x00000040
+#define MSR_RI_GET(x)                            (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
+#define MSR_RI_SET(x)                            (((x) << MSR_RI_LSB) & MSR_RI_MASK)
+#define MSR_DSR_MSB                              5
+#define MSR_DSR_LSB                              5
+#define MSR_DSR_MASK                             0x00000020
+#define MSR_DSR_GET(x)                           (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
+#define MSR_DSR_SET(x)                           (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
+#define MSR_CTS_MSB                              4
+#define MSR_CTS_LSB                              4
+#define MSR_CTS_MASK                             0x00000010
+#define MSR_CTS_GET(x)                           (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
+#define MSR_CTS_SET(x)                           (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
+#define MSR_DDCD_MSB                             3
+#define MSR_DDCD_LSB                             3
+#define MSR_DDCD_MASK                            0x00000008
+#define MSR_DDCD_GET(x)                          (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
+#define MSR_DDCD_SET(x)                          (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
+#define MSR_TERI_MSB                             2
+#define MSR_TERI_LSB                             2
+#define MSR_TERI_MASK                            0x00000004
+#define MSR_TERI_GET(x)                          (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
+#define MSR_TERI_SET(x)                          (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
+#define MSR_DDSR_MSB                             1
+#define MSR_DDSR_LSB                             1
+#define MSR_DDSR_MASK                            0x00000002
+#define MSR_DDSR_GET(x)                          (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
+#define MSR_DDSR_SET(x)                          (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
+#define MSR_DCTS_MSB                             0
+#define MSR_DCTS_LSB                             0
+#define MSR_DCTS_MASK                            0x00000001
+#define MSR_DCTS_GET(x)                          (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
+#define MSR_DCTS_SET(x)                          (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
+
+#define SCR_ADDRESS                              0x0000001c
+#define SCR_OFFSET                               0x0000001c
+#define SCR_SCR_MSB                              7
+#define SCR_SCR_LSB                              0
+#define SCR_SCR_MASK                             0x000000ff
+#define SCR_SCR_GET(x)                           (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
+#define SCR_SCR_SET(x)                           (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
+
+#define SRBR_ADDRESS                             0x00000020
+#define SRBR_OFFSET                              0x00000020
+#define SRBR_SRBR_MSB                            7
+#define SRBR_SRBR_LSB                            0
+#define SRBR_SRBR_MASK                           0x000000ff
+#define SRBR_SRBR_GET(x)                         (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
+#define SRBR_SRBR_SET(x)                         (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
+
+#define SIIR_ADDRESS                             0x00000028
+#define SIIR_OFFSET                              0x00000028
+#define SIIR_SIIR_MSB                            7
+#define SIIR_SIIR_LSB                            0
+#define SIIR_SIIR_MASK                           0x000000ff
+#define SIIR_SIIR_GET(x)                         (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
+#define SIIR_SIIR_SET(x)                         (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
+
+#define MWR_ADDRESS                              0x0000002c
+#define MWR_OFFSET                               0x0000002c
+#define MWR_MWR_MSB                              31
+#define MWR_MWR_LSB                              0
+#define MWR_MWR_MASK                             0xffffffff
+#define MWR_MWR_GET(x)                           (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
+#define MWR_MWR_SET(x)                           (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
+
+#define SLSR_ADDRESS                             0x00000034
+#define SLSR_OFFSET                              0x00000034
+#define SLSR_SLSR_MSB                            7
+#define SLSR_SLSR_LSB                            0
+#define SLSR_SLSR_MASK                           0x000000ff
+#define SLSR_SLSR_GET(x)                         (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
+#define SLSR_SLSR_SET(x)                         (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
+
+#define SMSR_ADDRESS                             0x00000038
+#define SMSR_OFFSET                              0x00000038
+#define SMSR_SMSR_MSB                            7
+#define SMSR_SMSR_LSB                            0
+#define SMSR_SMSR_MASK                           0x000000ff
+#define SMSR_SMSR_GET(x)                         (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
+#define SMSR_SMSR_SET(x)                         (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
+
+#define MRR_ADDRESS                              0x0000003c
+#define MRR_OFFSET                               0x0000003c
+#define MRR_MRR_MSB                              31
+#define MRR_MRR_LSB                              0
+#define MRR_MRR_MASK                             0xffffffff
+#define MRR_MRR_GET(x)                           (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
+#define MRR_MRR_SET(x)                           (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+  volatile unsigned int rbr;
+  volatile unsigned int dlh;
+  volatile unsigned int iir;
+  volatile unsigned int lcr;
+  volatile unsigned int mcr;
+  volatile unsigned int lsr;
+  volatile unsigned int msr;
+  volatile unsigned int scr;
+  volatile unsigned int srbr;
+  unsigned char pad0[4]; /* pad to 0x28 */
+  volatile unsigned int siir;
+  volatile unsigned int mwr;
+  unsigned char pad1[4]; /* pad to 0x34 */
+  volatile unsigned int slsr;
+  volatile unsigned int smsr;
+  volatile unsigned int mrr;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h
new file mode 100644
index 000000000000..0c15ebfaeaa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h
@@ -0,0 +1,95 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_REG_REG_H_
+#define _VMC_REG_REG_H_
+
+#define MC_TCAM_VALID_ADDRESS                    0x00000000
+#define MC_TCAM_VALID_OFFSET                     0x00000000
+#define MC_TCAM_VALID_BIT_MSB                    0
+#define MC_TCAM_VALID_BIT_LSB                    0
+#define MC_TCAM_VALID_BIT_MASK                   0x00000001
+#define MC_TCAM_VALID_BIT_GET(x)                 (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
+#define MC_TCAM_VALID_BIT_SET(x)                 (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
+
+#define MC_TCAM_MASK_ADDRESS                     0x00000080
+#define MC_TCAM_MASK_OFFSET                      0x00000080
+#define MC_TCAM_MASK_SIZE_MSB                    2
+#define MC_TCAM_MASK_SIZE_LSB                    0
+#define MC_TCAM_MASK_SIZE_MASK                   0x00000007
+#define MC_TCAM_MASK_SIZE_GET(x)                 (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
+#define MC_TCAM_MASK_SIZE_SET(x)                 (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
+
+#define MC_TCAM_COMPARE_ADDRESS                  0x00000100
+#define MC_TCAM_COMPARE_OFFSET                   0x00000100
+#define MC_TCAM_COMPARE_KEY_MSB                  21
+#define MC_TCAM_COMPARE_KEY_LSB                  5
+#define MC_TCAM_COMPARE_KEY_MASK                 0x003fffe0
+#define MC_TCAM_COMPARE_KEY_GET(x)               (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
+#define MC_TCAM_COMPARE_KEY_SET(x)               (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
+
+#define MC_TCAM_TARGET_ADDRESS                   0x00000180
+#define MC_TCAM_TARGET_OFFSET                    0x00000180
+#define MC_TCAM_TARGET_ADDR_MSB                  21
+#define MC_TCAM_TARGET_ADDR_LSB                  5
+#define MC_TCAM_TARGET_ADDR_MASK                 0x003fffe0
+#define MC_TCAM_TARGET_ADDR_GET(x)               (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
+#define MC_TCAM_TARGET_ADDR_SET(x)               (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
+
+#define ADDR_ERROR_CONTROL_ADDRESS               0x00000200
+#define ADDR_ERROR_CONTROL_OFFSET                0x00000200
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK      0x00000002
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)    (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)    (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define ADDR_ERROR_CONTROL_ENABLE_MSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_LSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_MASK           0x00000001
+#define ADDR_ERROR_CONTROL_ENABLE_GET(x)         (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_ENABLE_SET(x)         (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define ADDR_ERROR_STATUS_ADDRESS                0x00000204
+#define ADDR_ERROR_STATUS_OFFSET                 0x00000204
+#define ADDR_ERROR_STATUS_WRITE_MSB              25
+#define ADDR_ERROR_STATUS_WRITE_LSB              25
+#define ADDR_ERROR_STATUS_WRITE_MASK             0x02000000
+#define ADDR_ERROR_STATUS_WRITE_GET(x)           (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
+#define ADDR_ERROR_STATUS_WRITE_SET(x)           (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
+#define ADDR_ERROR_STATUS_ADDRESS_MSB            24
+#define ADDR_ERROR_STATUS_ADDRESS_LSB            0
+#define ADDR_ERROR_STATUS_ADDRESS_MASK           0x01ffffff
+#define ADDR_ERROR_STATUS_ADDRESS_GET(x)         (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define ADDR_ERROR_STATUS_ADDRESS_SET(x)         (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_reg_reg_s {
+  volatile unsigned int mc_tcam_valid[32];
+  volatile unsigned int mc_tcam_mask[32];
+  volatile unsigned int mc_tcam_compare[32];
+  volatile unsigned int mc_tcam_target[32];
+  volatile unsigned int addr_error_control;
+  volatile unsigned int addr_error_status;
+} vmc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..28b972afc8d7
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h
@@ -0,0 +1,83 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_INTF_REG_REG_H_
+#define _ANALOG_INTF_REG_REG_H_
+
+#define SW_OVERRIDE_ADDRESS                      0x00000080
+#define SW_OVERRIDE_OFFSET                       0x00000080
+#define SW_OVERRIDE_SUPDATE_DELAY_MSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_LSB            1
+#define SW_OVERRIDE_SUPDATE_DELAY_MASK           0x00000002
+#define SW_OVERRIDE_SUPDATE_DELAY_GET(x)         (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
+#define SW_OVERRIDE_SUPDATE_DELAY_SET(x)         (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
+#define SW_OVERRIDE_ENABLE_MSB                   0
+#define SW_OVERRIDE_ENABLE_LSB                   0
+#define SW_OVERRIDE_ENABLE_MASK                  0x00000001
+#define SW_OVERRIDE_ENABLE_GET(x)                (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
+#define SW_OVERRIDE_ENABLE_SET(x)                (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
+
+#define SIN_VAL_ADDRESS                          0x00000084
+#define SIN_VAL_OFFSET                           0x00000084
+#define SIN_VAL_SIN_MSB                          0
+#define SIN_VAL_SIN_LSB                          0
+#define SIN_VAL_SIN_MASK                         0x00000001
+#define SIN_VAL_SIN_GET(x)                       (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
+#define SIN_VAL_SIN_SET(x)                       (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
+
+#define SW_SCLK_ADDRESS                          0x00000088
+#define SW_SCLK_OFFSET                           0x00000088
+#define SW_SCLK_SW_SCLK_MSB                      0
+#define SW_SCLK_SW_SCLK_LSB                      0
+#define SW_SCLK_SW_SCLK_MASK                     0x00000001
+#define SW_SCLK_SW_SCLK_GET(x)                   (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
+#define SW_SCLK_SW_SCLK_SET(x)                   (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
+
+#define SW_CNTL_ADDRESS                          0x0000008c
+#define SW_CNTL_OFFSET                           0x0000008c
+#define SW_CNTL_SW_SCAPTURE_MSB                  2
+#define SW_CNTL_SW_SCAPTURE_LSB                  2
+#define SW_CNTL_SW_SCAPTURE_MASK                 0x00000004
+#define SW_CNTL_SW_SCAPTURE_GET(x)               (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
+#define SW_CNTL_SW_SCAPTURE_SET(x)               (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
+#define SW_CNTL_SW_SUPDATE_MSB                   1
+#define SW_CNTL_SW_SUPDATE_LSB                   1
+#define SW_CNTL_SW_SUPDATE_MASK                  0x00000002
+#define SW_CNTL_SW_SUPDATE_GET(x)                (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
+#define SW_CNTL_SW_SUPDATE_SET(x)                (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
+#define SW_CNTL_SW_SOUT_MSB                      0
+#define SW_CNTL_SW_SOUT_LSB                      0
+#define SW_CNTL_SW_SOUT_MASK                     0x00000001
+#define SW_CNTL_SW_SOUT_GET(x)                   (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
+#define SW_CNTL_SW_SOUT_SET(x)                   (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_reg_reg_s {
+  unsigned char pad0[128]; /* pad to 0x80 */
+  volatile unsigned int sw_override;
+  volatile unsigned int sin_val;
+  volatile unsigned int sw_sclk;
+  volatile unsigned int sw_cntl;
+} analog_intf_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h
new file mode 100644
index 000000000000..c485ac725c2f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h
@@ -0,0 +1,1951 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_REG_REG_H_
+#define _ANALOG_REG_REG_H_
+
+#define SYNTH_SYNTH1_ADDRESS                     0x00000000
+#define SYNTH_SYNTH1_OFFSET                      0x00000000
+#define SYNTH_SYNTH1_PWD_BIAS_MSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_LSB                31
+#define SYNTH_SYNTH1_PWD_BIAS_MASK               0x80000000
+#define SYNTH_SYNTH1_PWD_BIAS_GET(x)             (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
+#define SYNTH_SYNTH1_PWD_BIAS_SET(x)             (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
+#define SYNTH_SYNTH1_PWD_CP_MSB                  30
+#define SYNTH_SYNTH1_PWD_CP_LSB                  30
+#define SYNTH_SYNTH1_PWD_CP_MASK                 0x40000000
+#define SYNTH_SYNTH1_PWD_CP_GET(x)               (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
+#define SYNTH_SYNTH1_PWD_CP_SET(x)               (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
+#define SYNTH_SYNTH1_PWD_VCMON_MSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_LSB               29
+#define SYNTH_SYNTH1_PWD_VCMON_MASK              0x20000000
+#define SYNTH_SYNTH1_PWD_VCMON_GET(x)            (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
+#define SYNTH_SYNTH1_PWD_VCMON_SET(x)            (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
+#define SYNTH_SYNTH1_PWD_VCO_MSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_LSB                 28
+#define SYNTH_SYNTH1_PWD_VCO_MASK                0x10000000
+#define SYNTH_SYNTH1_PWD_VCO_GET(x)              (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
+#define SYNTH_SYNTH1_PWD_VCO_SET(x)              (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
+#define SYNTH_SYNTH1_PWD_PRESC_MSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_LSB               27
+#define SYNTH_SYNTH1_PWD_PRESC_MASK              0x08000000
+#define SYNTH_SYNTH1_PWD_PRESC_GET(x)            (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
+#define SYNTH_SYNTH1_PWD_PRESC_SET(x)            (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
+#define SYNTH_SYNTH1_PWD_LODIV_MSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_LSB               26
+#define SYNTH_SYNTH1_PWD_LODIV_MASK              0x04000000
+#define SYNTH_SYNTH1_PWD_LODIV_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
+#define SYNTH_SYNTH1_PWD_LODIV_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
+#define SYNTH_SYNTH1_PWD_LOMIX_MSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_LSB               25
+#define SYNTH_SYNTH1_PWD_LOMIX_MASK              0x02000000
+#define SYNTH_SYNTH1_PWD_LOMIX_GET(x)            (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
+#define SYNTH_SYNTH1_PWD_LOMIX_SET(x)            (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
+#define SYNTH_SYNTH1_FORCE_LO_ON_MSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_LSB             24
+#define SYNTH_SYNTH1_FORCE_LO_ON_MASK            0x01000000
+#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x)          (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
+#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x)          (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB             23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK            0x00800000
+#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x)          (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x)          (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
+#define SYNTH_SYNTH1_VCOREGBYPASS_MSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_LSB            22
+#define SYNTH_SYNTH1_VCOREGBYPASS_MASK           0x00400000
+#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x)         (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
+#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x)         (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
+#define SYNTH_SYNTH1_VCOREGLEVEL_MSB             21
+#define SYNTH_SYNTH1_VCOREGLEVEL_LSB             20
+#define SYNTH_SYNTH1_VCOREGLEVEL_MASK            0x00300000
+#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x)          (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
+#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x)          (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
+#define SYNTH_SYNTH1_VCOREGBIAS_MSB              19
+#define SYNTH_SYNTH1_VCOREGBIAS_LSB              18
+#define SYNTH_SYNTH1_VCOREGBIAS_MASK             0x000c0000
+#define SYNTH_SYNTH1_VCOREGBIAS_GET(x)           (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
+#define SYNTH_SYNTH1_VCOREGBIAS_SET(x)           (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
+#define SYNTH_SYNTH1_SLIDINGIF_MSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_LSB               17
+#define SYNTH_SYNTH1_SLIDINGIF_MASK              0x00020000
+#define SYNTH_SYNTH1_SLIDINGIF_GET(x)            (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
+#define SYNTH_SYNTH1_SLIDINGIF_SET(x)            (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
+#define SYNTH_SYNTH1_SPARE_PWD_MSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_LSB               16
+#define SYNTH_SYNTH1_SPARE_PWD_MASK              0x00010000
+#define SYNTH_SYNTH1_SPARE_PWD_GET(x)            (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
+#define SYNTH_SYNTH1_SPARE_PWD_SET(x)            (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB           15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK          0x00008000
+#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x)        (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x)        (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOREG_MSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_LSB             14
+#define SYNTH_SYNTH1_CON_IVCOREG_MASK            0x00004000
+#define SYNTH_SYNTH1_CON_IVCOREG_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_IVCOREG_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOBUF_MSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_LSB             13
+#define SYNTH_SYNTH1_CON_IVCOBUF_MASK            0x00002000
+#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x)          (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
+#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x)          (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB           12
+#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB           10
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK          0x00001c00
+#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x)        (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x)        (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB          9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK         0x00000200
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x)       (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x)       (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB           8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK          0x00000100
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB           7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK          0x00000080
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x)        (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x)        (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB         6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK        0x00000040
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x)      (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x)      (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_MSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_LSB              5
+#define SYNTH_SYNTH1_MONITOR_FB_MASK             0x00000020
+#define SYNTH_SYNTH1_MONITOR_FB_GET(x)           (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_SET(x)           (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
+#define SYNTH_SYNTH1_MONITOR_REF_MSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_LSB             4
+#define SYNTH_SYNTH1_MONITOR_REF_MASK            0x00000010
+#define SYNTH_SYNTH1_MONITOR_REF_GET(x)          (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
+#define SYNTH_SYNTH1_MONITOR_REF_SET(x)          (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB         3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK        0x00000008
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB         2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK        0x00000004
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x)      (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x)      (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB          1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK         0x00000002
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x)       (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x)       (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB   0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK  0x00000001
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
+
+#define SYNTH_SYNTH2_ADDRESS                     0x00000004
+#define SYNTH_SYNTH2_OFFSET                      0x00000004
+#define SYNTH_SYNTH2_VC_CAL_REF_MSB              31
+#define SYNTH_SYNTH2_VC_CAL_REF_LSB              29
+#define SYNTH_SYNTH2_VC_CAL_REF_MASK             0xe0000000
+#define SYNTH_SYNTH2_VC_CAL_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
+#define SYNTH_SYNTH2_VC_CAL_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
+#define SYNTH_SYNTH2_VC_HI_REF_MSB               28
+#define SYNTH_SYNTH2_VC_HI_REF_LSB               26
+#define SYNTH_SYNTH2_VC_HI_REF_MASK              0x1c000000
+#define SYNTH_SYNTH2_VC_HI_REF_GET(x)            (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
+#define SYNTH_SYNTH2_VC_HI_REF_SET(x)            (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
+#define SYNTH_SYNTH2_VC_MID_REF_MSB              25
+#define SYNTH_SYNTH2_VC_MID_REF_LSB              23
+#define SYNTH_SYNTH2_VC_MID_REF_MASK             0x03800000
+#define SYNTH_SYNTH2_VC_MID_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
+#define SYNTH_SYNTH2_VC_MID_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
+#define SYNTH_SYNTH2_VC_LOW_REF_MSB              22
+#define SYNTH_SYNTH2_VC_LOW_REF_LSB              20
+#define SYNTH_SYNTH2_VC_LOW_REF_MASK             0x00700000
+#define SYNTH_SYNTH2_VC_LOW_REF_GET(x)           (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
+#define SYNTH_SYNTH2_VC_LOW_REF_SET(x)           (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB        19
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB        15
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK       0x000f8000
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x)     (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x)     (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
+#define SYNTH_SYNTH2_LOOP_CP_MSB                 14
+#define SYNTH_SYNTH2_LOOP_CP_LSB                 10
+#define SYNTH_SYNTH2_LOOP_CP_MASK                0x00007c00
+#define SYNTH_SYNTH2_LOOP_CP_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
+#define SYNTH_SYNTH2_LOOP_CP_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
+#define SYNTH_SYNTH2_LOOP_RS_MSB                 9
+#define SYNTH_SYNTH2_LOOP_RS_LSB                 5
+#define SYNTH_SYNTH2_LOOP_RS_MASK                0x000003e0
+#define SYNTH_SYNTH2_LOOP_RS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
+#define SYNTH_SYNTH2_LOOP_RS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
+#define SYNTH_SYNTH2_LOOP_CS_MSB                 4
+#define SYNTH_SYNTH2_LOOP_CS_LSB                 3
+#define SYNTH_SYNTH2_LOOP_CS_MASK                0x00000018
+#define SYNTH_SYNTH2_LOOP_CS_GET(x)              (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
+#define SYNTH_SYNTH2_LOOP_CS_SET(x)              (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
+#define SYNTH_SYNTH2_SPARE_BITS_MSB              2
+#define SYNTH_SYNTH2_SPARE_BITS_LSB              0
+#define SYNTH_SYNTH2_SPARE_BITS_MASK             0x00000007
+#define SYNTH_SYNTH2_SPARE_BITS_GET(x)           (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
+#define SYNTH_SYNTH2_SPARE_BITS_SET(x)           (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
+
+#define SYNTH_SYNTH3_ADDRESS                     0x00000008
+#define SYNTH_SYNTH3_OFFSET                      0x00000008
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB            31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK           0x80000000
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x)         (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x)         (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB            30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK           0x40000000
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x)         (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x)         (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB       29
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB       24
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK      0x3f000000
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)    (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)    (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_PWRUP_MSB              23
+#define SYNTH_SYNTH3_WAIT_PWRUP_LSB              18
+#define SYNTH_SYNTH3_WAIT_PWRUP_MASK             0x00fc0000
+#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x)           (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x)           (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB            17
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB            12
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK           0x0003f000
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB            11
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB            6
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK           0x00000fc0
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x)         (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x)         (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB           5
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB           0
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK          0x0000003f
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x)        (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x)        (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
+
+#define SYNTH_SYNTH4_ADDRESS                     0x0000000c
+#define SYNTH_SYNTH4_OFFSET                      0x0000000c
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB       31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK      0x80000000
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)    (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)    (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
+#define SYNTH_SYNTH4_DIS_LOSTVC_MSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_LSB              30
+#define SYNTH_SYNTH4_DIS_LOSTVC_MASK             0x40000000
+#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x)           (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
+#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x)           (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB           29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK          0x20000000
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x)        (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x)        (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB     28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK    0x10000000
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)  (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)  (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
+#define SYNTH_SYNTH4_FORCE_PINVC_MSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_LSB             27
+#define SYNTH_SYNTH4_FORCE_PINVC_MASK            0x08000000
+#define SYNTH_SYNTH4_FORCE_PINVC_GET(x)          (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
+#define SYNTH_SYNTH4_FORCE_PINVC_SET(x)          (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB            26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK           0x04000000
+#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x)         (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x)         (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
+#define SYNTH_SYNTH4_VCOCAP_OVR_MSB              25
+#define SYNTH_SYNTH4_VCOCAP_OVR_LSB              18
+#define SYNTH_SYNTH4_VCOCAP_OVR_MASK             0x03fc0000
+#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x)           (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
+#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x)           (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB            17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK           0x00020000
+#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x)         (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x)         (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
+#define SYNTH_SYNTH4_REFDIVSEL_MSB               16
+#define SYNTH_SYNTH4_REFDIVSEL_LSB               15
+#define SYNTH_SYNTH4_REFDIVSEL_MASK              0x00018000
+#define SYNTH_SYNTH4_REFDIVSEL_GET(x)            (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
+#define SYNTH_SYNTH4_REFDIVSEL_SET(x)            (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
+#define SYNTH_SYNTH4_PFDDELAY_MSB                14
+#define SYNTH_SYNTH4_PFDDELAY_LSB                14
+#define SYNTH_SYNTH4_PFDDELAY_MASK               0x00004000
+#define SYNTH_SYNTH4_PFDDELAY_GET(x)             (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
+#define SYNTH_SYNTH4_PFDDELAY_SET(x)             (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
+#define SYNTH_SYNTH4_PFD_DISABLE_MSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_LSB             13
+#define SYNTH_SYNTH4_PFD_DISABLE_MASK            0x00002000
+#define SYNTH_SYNTH4_PFD_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
+#define SYNTH_SYNTH4_PFD_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
+#define SYNTH_SYNTH4_PRESCSEL_MSB                12
+#define SYNTH_SYNTH4_PRESCSEL_LSB                11
+#define SYNTH_SYNTH4_PRESCSEL_MASK               0x00001800
+#define SYNTH_SYNTH4_PRESCSEL_GET(x)             (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
+#define SYNTH_SYNTH4_PRESCSEL_SET(x)             (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
+#define SYNTH_SYNTH4_RESET_PRESC_MSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_LSB             10
+#define SYNTH_SYNTH4_RESET_PRESC_MASK            0x00000400
+#define SYNTH_SYNTH4_RESET_PRESC_GET(x)          (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
+#define SYNTH_SYNTH4_RESET_PRESC_SET(x)          (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
+#define SYNTH_SYNTH4_SDM_DISABLE_MSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_LSB             9
+#define SYNTH_SYNTH4_SDM_DISABLE_MASK            0x00000200
+#define SYNTH_SYNTH4_SDM_DISABLE_GET(x)          (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
+#define SYNTH_SYNTH4_SDM_DISABLE_SET(x)          (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
+#define SYNTH_SYNTH4_SDM_MODE_MSB                8
+#define SYNTH_SYNTH4_SDM_MODE_LSB                8
+#define SYNTH_SYNTH4_SDM_MODE_MASK               0x00000100
+#define SYNTH_SYNTH4_SDM_MODE_GET(x)             (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
+#define SYNTH_SYNTH4_SDM_MODE_SET(x)             (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
+#define SYNTH_SYNTH4_SDM_DITHER_MSB              7
+#define SYNTH_SYNTH4_SDM_DITHER_LSB              6
+#define SYNTH_SYNTH4_SDM_DITHER_MASK             0x000000c0
+#define SYNTH_SYNTH4_SDM_DITHER_GET(x)           (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
+#define SYNTH_SYNTH4_SDM_DITHER_SET(x)           (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB           5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK          0x00000020
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x)        (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x)        (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB        4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK       0x00000010
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x)     (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x)     (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
+#define SYNTH_SYNTH4_SPARE_MISC_MSB              3
+#define SYNTH_SYNTH4_SPARE_MISC_LSB              2
+#define SYNTH_SYNTH4_SPARE_MISC_MASK             0x0000000c
+#define SYNTH_SYNTH4_SPARE_MISC_GET(x)           (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
+#define SYNTH_SYNTH4_SPARE_MISC_SET(x)           (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB            1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK           0x00000002
+#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x)         (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x)         (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB          0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK         0x00000001
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x)       (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x)       (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
+
+#define SYNTH_SYNTH5_ADDRESS                     0x00000010
+#define SYNTH_SYNTH5_OFFSET                      0x00000010
+#define SYNTH_SYNTH5_LOOP_IP0_MSB                31
+#define SYNTH_SYNTH5_LOOP_IP0_LSB                28
+#define SYNTH_SYNTH5_LOOP_IP0_MASK               0xf0000000
+#define SYNTH_SYNTH5_LOOP_IP0_GET(x)             (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
+#define SYNTH_SYNTH5_LOOP_IP0_SET(x)             (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
+#define SYNTH_SYNTH5_SLOPE_IP_MSB                27
+#define SYNTH_SYNTH5_SLOPE_IP_LSB                25
+#define SYNTH_SYNTH5_SLOPE_IP_MASK               0x0e000000
+#define SYNTH_SYNTH5_SLOPE_IP_GET(x)             (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
+#define SYNTH_SYNTH5_SLOPE_IP_SET(x)             (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
+#define SYNTH_SYNTH5_CPBIAS_MSB                  24
+#define SYNTH_SYNTH5_CPBIAS_LSB                  23
+#define SYNTH_SYNTH5_CPBIAS_MASK                 0x01800000
+#define SYNTH_SYNTH5_CPBIAS_GET(x)               (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
+#define SYNTH_SYNTH5_CPBIAS_SET(x)               (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
+#define SYNTH_SYNTH5_CPSTEERING_EN_MSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_LSB           22
+#define SYNTH_SYNTH5_CPSTEERING_EN_MASK          0x00400000
+#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x)        (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
+#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x)        (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
+#define SYNTH_SYNTH5_CPLOWLK_MSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_LSB                 21
+#define SYNTH_SYNTH5_CPLOWLK_MASK                0x00200000
+#define SYNTH_SYNTH5_CPLOWLK_GET(x)              (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
+#define SYNTH_SYNTH5_CPLOWLK_SET(x)              (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB             20
+#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB             17
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK            0x001e0000
+#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x)          (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x)          (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
+#define SYNTH_SYNTH5_CAPRANGE1_MSB               16
+#define SYNTH_SYNTH5_CAPRANGE1_LSB               13
+#define SYNTH_SYNTH5_CAPRANGE1_MASK              0x0001e000
+#define SYNTH_SYNTH5_CAPRANGE1_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
+#define SYNTH_SYNTH5_CAPRANGE1_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
+#define SYNTH_SYNTH5_CAPRANGE2_MSB               12
+#define SYNTH_SYNTH5_CAPRANGE2_LSB               9
+#define SYNTH_SYNTH5_CAPRANGE2_MASK              0x00001e00
+#define SYNTH_SYNTH5_CAPRANGE2_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
+#define SYNTH_SYNTH5_CAPRANGE2_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
+#define SYNTH_SYNTH5_CAPRANGE3_MSB               8
+#define SYNTH_SYNTH5_CAPRANGE3_LSB               5
+#define SYNTH_SYNTH5_CAPRANGE3_MASK              0x000001e0
+#define SYNTH_SYNTH5_CAPRANGE3_GET(x)            (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
+#define SYNTH_SYNTH5_CAPRANGE3_SET(x)            (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB       4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK      0x00000010
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x)    (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x)    (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB         3
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB         2
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK        0x0000000c
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x)      (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x)      (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
+#define SYNTH_SYNTH5_SPARE_MSB                   1
+#define SYNTH_SYNTH5_SPARE_LSB                   0
+#define SYNTH_SYNTH5_SPARE_MASK                  0x00000003
+#define SYNTH_SYNTH5_SPARE_GET(x)                (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
+#define SYNTH_SYNTH5_SPARE_SET(x)                (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
+
+#define SYNTH_SYNTH6_ADDRESS                     0x00000014
+#define SYNTH_SYNTH6_OFFSET                      0x00000014
+#define SYNTH_SYNTH6_IRCP_MSB                    31
+#define SYNTH_SYNTH6_IRCP_LSB                    29
+#define SYNTH_SYNTH6_IRCP_MASK                   0xe0000000
+#define SYNTH_SYNTH6_IRCP_GET(x)                 (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
+#define SYNTH_SYNTH6_IRCP_SET(x)                 (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
+#define SYNTH_SYNTH6_IRVCMON_MSB                 28
+#define SYNTH_SYNTH6_IRVCMON_LSB                 26
+#define SYNTH_SYNTH6_IRVCMON_MASK                0x1c000000
+#define SYNTH_SYNTH6_IRVCMON_GET(x)              (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
+#define SYNTH_SYNTH6_IRVCMON_SET(x)              (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
+#define SYNTH_SYNTH6_IRSPARE_MSB                 25
+#define SYNTH_SYNTH6_IRSPARE_LSB                 23
+#define SYNTH_SYNTH6_IRSPARE_MASK                0x03800000
+#define SYNTH_SYNTH6_IRSPARE_GET(x)              (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
+#define SYNTH_SYNTH6_IRSPARE_SET(x)              (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
+#define SYNTH_SYNTH6_ICPRESC_MSB                 22
+#define SYNTH_SYNTH6_ICPRESC_LSB                 20
+#define SYNTH_SYNTH6_ICPRESC_MASK                0x00700000
+#define SYNTH_SYNTH6_ICPRESC_GET(x)              (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
+#define SYNTH_SYNTH6_ICPRESC_SET(x)              (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
+#define SYNTH_SYNTH6_ICLODIV_MSB                 19
+#define SYNTH_SYNTH6_ICLODIV_LSB                 17
+#define SYNTH_SYNTH6_ICLODIV_MASK                0x000e0000
+#define SYNTH_SYNTH6_ICLODIV_GET(x)              (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
+#define SYNTH_SYNTH6_ICLODIV_SET(x)              (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
+#define SYNTH_SYNTH6_ICLOMIX_MSB                 16
+#define SYNTH_SYNTH6_ICLOMIX_LSB                 14
+#define SYNTH_SYNTH6_ICLOMIX_MASK                0x0001c000
+#define SYNTH_SYNTH6_ICLOMIX_GET(x)              (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
+#define SYNTH_SYNTH6_ICLOMIX_SET(x)              (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
+#define SYNTH_SYNTH6_ICSPAREA_MSB                13
+#define SYNTH_SYNTH6_ICSPAREA_LSB                11
+#define SYNTH_SYNTH6_ICSPAREA_MASK               0x00003800
+#define SYNTH_SYNTH6_ICSPAREA_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
+#define SYNTH_SYNTH6_ICSPAREA_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
+#define SYNTH_SYNTH6_ICSPAREB_MSB                10
+#define SYNTH_SYNTH6_ICSPAREB_LSB                8
+#define SYNTH_SYNTH6_ICSPAREB_MASK               0x00000700
+#define SYNTH_SYNTH6_ICSPAREB_GET(x)             (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
+#define SYNTH_SYNTH6_ICSPAREB_SET(x)             (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
+#define SYNTH_SYNTH6_ICVCO_MSB                   7
+#define SYNTH_SYNTH6_ICVCO_LSB                   5
+#define SYNTH_SYNTH6_ICVCO_MASK                  0x000000e0
+#define SYNTH_SYNTH6_ICVCO_GET(x)                (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
+#define SYNTH_SYNTH6_ICVCO_SET(x)                (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
+#define SYNTH_SYNTH6_VCOBUFBIAS_MSB              4
+#define SYNTH_SYNTH6_VCOBUFBIAS_LSB              3
+#define SYNTH_SYNTH6_VCOBUFBIAS_MASK             0x00000018
+#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x)           (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
+#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x)           (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
+#define SYNTH_SYNTH6_SPARE_BIAS_MSB              2
+#define SYNTH_SYNTH6_SPARE_BIAS_LSB              0
+#define SYNTH_SYNTH6_SPARE_BIAS_MASK             0x00000007
+#define SYNTH_SYNTH6_SPARE_BIAS_GET(x)           (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
+#define SYNTH_SYNTH6_SPARE_BIAS_SET(x)           (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
+
+#define SYNTH_SYNTH7_ADDRESS                     0x00000018
+#define SYNTH_SYNTH7_OFFSET                      0x00000018
+#define SYNTH_SYNTH7_SYNTH_ON_MSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_LSB                31
+#define SYNTH_SYNTH7_SYNTH_ON_MASK               0x80000000
+#define SYNTH_SYNTH7_SYNTH_ON_GET(x)             (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
+#define SYNTH_SYNTH7_SYNTH_ON_SET(x)             (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB          30
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB          27
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK         0x78000000
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x)       (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x)       (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
+#define SYNTH_SYNTH7_CAP_SEARCH_MSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_LSB              26
+#define SYNTH_SYNTH7_CAP_SEARCH_MASK             0x04000000
+#define SYNTH_SYNTH7_CAP_SEARCH_GET(x)           (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
+#define SYNTH_SYNTH7_CAP_SEARCH_SET(x)           (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB        25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK       0x02000000
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x)     (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x)     (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
+#define SYNTH_SYNTH7_PIN_VC_MSB                  24
+#define SYNTH_SYNTH7_PIN_VC_LSB                  24
+#define SYNTH_SYNTH7_PIN_VC_MASK                 0x01000000
+#define SYNTH_SYNTH7_PIN_VC_GET(x)               (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
+#define SYNTH_SYNTH7_PIN_VC_SET(x)               (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
+#define SYNTH_SYNTH7_VCO_CAP_ST_MSB              23
+#define SYNTH_SYNTH7_VCO_CAP_ST_LSB              16
+#define SYNTH_SYNTH7_VCO_CAP_ST_MASK             0x00ff0000
+#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x)           (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
+#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x)           (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
+#define SYNTH_SYNTH7_SHORT_R_MSB                 15
+#define SYNTH_SYNTH7_SHORT_R_LSB                 15
+#define SYNTH_SYNTH7_SHORT_R_MASK                0x00008000
+#define SYNTH_SYNTH7_SHORT_R_GET(x)              (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
+#define SYNTH_SYNTH7_SHORT_R_SET(x)              (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
+#define SYNTH_SYNTH7_RESET_RFD_MSB               14
+#define SYNTH_SYNTH7_RESET_RFD_LSB               14
+#define SYNTH_SYNTH7_RESET_RFD_MASK              0x00004000
+#define SYNTH_SYNTH7_RESET_RFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
+#define SYNTH_SYNTH7_RESET_RFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
+#define SYNTH_SYNTH7_RESET_PFD_MSB               13
+#define SYNTH_SYNTH7_RESET_PFD_LSB               13
+#define SYNTH_SYNTH7_RESET_PFD_MASK              0x00002000
+#define SYNTH_SYNTH7_RESET_PFD_GET(x)            (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
+#define SYNTH_SYNTH7_RESET_PFD_SET(x)            (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB        12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK       0x00001000
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x)     (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x)     (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
+#define SYNTH_SYNTH7_RESET_SDM_B_MSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_LSB             11
+#define SYNTH_SYNTH7_RESET_SDM_B_MASK            0x00000800
+#define SYNTH_SYNTH7_RESET_SDM_B_GET(x)          (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
+#define SYNTH_SYNTH7_RESET_SDM_B_SET(x)          (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
+#define SYNTH_SYNTH7_VC2HIGH_MSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_LSB                 10
+#define SYNTH_SYNTH7_VC2HIGH_MASK                0x00000400
+#define SYNTH_SYNTH7_VC2HIGH_GET(x)              (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
+#define SYNTH_SYNTH7_VC2HIGH_SET(x)              (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
+#define SYNTH_SYNTH7_VC2LOW_MSB                  9
+#define SYNTH_SYNTH7_VC2LOW_LSB                  9
+#define SYNTH_SYNTH7_VC2LOW_MASK                 0x00000200
+#define SYNTH_SYNTH7_VC2LOW_GET(x)               (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
+#define SYNTH_SYNTH7_VC2LOW_SET(x)               (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
+#define SYNTH_SYNTH7_LOOP_IP_MSB                 8
+#define SYNTH_SYNTH7_LOOP_IP_LSB                 5
+#define SYNTH_SYNTH7_LOOP_IP_MASK                0x000001e0
+#define SYNTH_SYNTH7_LOOP_IP_GET(x)              (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
+#define SYNTH_SYNTH7_LOOP_IP_SET(x)              (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB             4
+#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB             3
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK            0x00000018
+#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x)          (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x)          (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH7_SPARE_READ_MSB              2
+#define SYNTH_SYNTH7_SPARE_READ_LSB              0
+#define SYNTH_SYNTH7_SPARE_READ_MASK             0x00000007
+#define SYNTH_SYNTH7_SPARE_READ_GET(x)           (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
+#define SYNTH_SYNTH7_SPARE_READ_SET(x)           (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
+
+#define SYNTH_SYNTH8_ADDRESS                     0x0000001c
+#define SYNTH_SYNTH8_OFFSET                      0x0000001c
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB        31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK       0x80000000
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x)     (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x)     (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
+#define SYNTH_SYNTH8_FRACMODE_MSB                30
+#define SYNTH_SYNTH8_FRACMODE_LSB                30
+#define SYNTH_SYNTH8_FRACMODE_MASK               0x40000000
+#define SYNTH_SYNTH8_FRACMODE_GET(x)             (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
+#define SYNTH_SYNTH8_FRACMODE_SET(x)             (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
+#define SYNTH_SYNTH8_AMODEREFSEL_MSB             29
+#define SYNTH_SYNTH8_AMODEREFSEL_LSB             28
+#define SYNTH_SYNTH8_AMODEREFSEL_MASK            0x30000000
+#define SYNTH_SYNTH8_AMODEREFSEL_GET(x)          (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
+#define SYNTH_SYNTH8_AMODEREFSEL_SET(x)          (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
+#define SYNTH_SYNTH8_SPARE_MSB                   27
+#define SYNTH_SYNTH8_SPARE_LSB                   27
+#define SYNTH_SYNTH8_SPARE_MASK                  0x08000000
+#define SYNTH_SYNTH8_SPARE_GET(x)                (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
+#define SYNTH_SYNTH8_SPARE_SET(x)                (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
+#define SYNTH_SYNTH8_CHANSEL_MSB                 26
+#define SYNTH_SYNTH8_CHANSEL_LSB                 18
+#define SYNTH_SYNTH8_CHANSEL_MASK                0x07fc0000
+#define SYNTH_SYNTH8_CHANSEL_GET(x)              (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
+#define SYNTH_SYNTH8_CHANSEL_SET(x)              (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
+#define SYNTH_SYNTH8_CHANFRAC_MSB                17
+#define SYNTH_SYNTH8_CHANFRAC_LSB                1
+#define SYNTH_SYNTH8_CHANFRAC_MASK               0x0003fffe
+#define SYNTH_SYNTH8_CHANFRAC_GET(x)             (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
+#define SYNTH_SYNTH8_CHANFRAC_SET(x)             (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB           0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK          0x00000001
+#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x)        (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x)        (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
+
+#define RF5G_RF5G1_ADDRESS                       0x00000020
+#define RF5G_RF5G1_OFFSET                        0x00000020
+#define RF5G_RF5G1_PDTXLO5_MSB                   31
+#define RF5G_RF5G1_PDTXLO5_LSB                   31
+#define RF5G_RF5G1_PDTXLO5_MASK                  0x80000000
+#define RF5G_RF5G1_PDTXLO5_GET(x)                (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
+#define RF5G_RF5G1_PDTXLO5_SET(x)                (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
+#define RF5G_RF5G1_PDTXMIX5_MSB                  30
+#define RF5G_RF5G1_PDTXMIX5_LSB                  30
+#define RF5G_RF5G1_PDTXMIX5_MASK                 0x40000000
+#define RF5G_RF5G1_PDTXMIX5_GET(x)               (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
+#define RF5G_RF5G1_PDTXMIX5_SET(x)               (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
+#define RF5G_RF5G1_PDTXBUF5_MSB                  29
+#define RF5G_RF5G1_PDTXBUF5_LSB                  29
+#define RF5G_RF5G1_PDTXBUF5_MASK                 0x20000000
+#define RF5G_RF5G1_PDTXBUF5_GET(x)               (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
+#define RF5G_RF5G1_PDTXBUF5_SET(x)               (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
+#define RF5G_RF5G1_PDPADRV5_MSB                  28
+#define RF5G_RF5G1_PDPADRV5_LSB                  28
+#define RF5G_RF5G1_PDPADRV5_MASK                 0x10000000
+#define RF5G_RF5G1_PDPADRV5_GET(x)               (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
+#define RF5G_RF5G1_PDPADRV5_SET(x)               (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
+#define RF5G_RF5G1_PDPAOUT5_MSB                  27
+#define RF5G_RF5G1_PDPAOUT5_LSB                  27
+#define RF5G_RF5G1_PDPAOUT5_MASK                 0x08000000
+#define RF5G_RF5G1_PDPAOUT5_GET(x)               (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
+#define RF5G_RF5G1_PDPAOUT5_SET(x)               (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
+#define RF5G_RF5G1_TUNE_PADRV5_MSB               26
+#define RF5G_RF5G1_TUNE_PADRV5_LSB               24
+#define RF5G_RF5G1_TUNE_PADRV5_MASK              0x07000000
+#define RF5G_RF5G1_TUNE_PADRV5_GET(x)            (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
+#define RF5G_RF5G1_TUNE_PADRV5_SET(x)            (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
+#define RF5G_RF5G1_PWDTXPKD_MSB                  23
+#define RF5G_RF5G1_PWDTXPKD_LSB                  21
+#define RF5G_RF5G1_PWDTXPKD_MASK                 0x00e00000
+#define RF5G_RF5G1_PWDTXPKD_GET(x)               (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
+#define RF5G_RF5G1_PWDTXPKD_SET(x)               (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
+#define RF5G_RF5G1_DB5_MSB                       20
+#define RF5G_RF5G1_DB5_LSB                       18
+#define RF5G_RF5G1_DB5_MASK                      0x001c0000
+#define RF5G_RF5G1_DB5_GET(x)                    (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
+#define RF5G_RF5G1_DB5_SET(x)                    (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
+#define RF5G_RF5G1_OB5_MSB                       17
+#define RF5G_RF5G1_OB5_LSB                       15
+#define RF5G_RF5G1_OB5_MASK                      0x00038000
+#define RF5G_RF5G1_OB5_GET(x)                    (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
+#define RF5G_RF5G1_OB5_SET(x)                    (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
+#define RF5G_RF5G1_TX5_ATB_SEL_MSB               14
+#define RF5G_RF5G1_TX5_ATB_SEL_LSB               12
+#define RF5G_RF5G1_TX5_ATB_SEL_MASK              0x00007000
+#define RF5G_RF5G1_TX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
+#define RF5G_RF5G1_TX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
+#define RF5G_RF5G1_PDLO5DIV_MSB                  11
+#define RF5G_RF5G1_PDLO5DIV_LSB                  11
+#define RF5G_RF5G1_PDLO5DIV_MASK                 0x00000800
+#define RF5G_RF5G1_PDLO5DIV_GET(x)               (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
+#define RF5G_RF5G1_PDLO5DIV_SET(x)               (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
+#define RF5G_RF5G1_PDLO5MIX_MSB                  10
+#define RF5G_RF5G1_PDLO5MIX_LSB                  10
+#define RF5G_RF5G1_PDLO5MIX_MASK                 0x00000400
+#define RF5G_RF5G1_PDLO5MIX_GET(x)               (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
+#define RF5G_RF5G1_PDLO5MIX_SET(x)               (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
+#define RF5G_RF5G1_PDQBUF5_MSB                   9
+#define RF5G_RF5G1_PDQBUF5_LSB                   9
+#define RF5G_RF5G1_PDQBUF5_MASK                  0x00000200
+#define RF5G_RF5G1_PDQBUF5_GET(x)                (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
+#define RF5G_RF5G1_PDQBUF5_SET(x)                (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
+#define RF5G_RF5G1_PDLO5AGC_MSB                  8
+#define RF5G_RF5G1_PDLO5AGC_LSB                  8
+#define RF5G_RF5G1_PDLO5AGC_MASK                 0x00000100
+#define RF5G_RF5G1_PDLO5AGC_GET(x)               (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
+#define RF5G_RF5G1_PDLO5AGC_SET(x)               (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
+#define RF5G_RF5G1_PDREGLO5_MSB                  7
+#define RF5G_RF5G1_PDREGLO5_LSB                  7
+#define RF5G_RF5G1_PDREGLO5_MASK                 0x00000080
+#define RF5G_RF5G1_PDREGLO5_GET(x)               (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
+#define RF5G_RF5G1_PDREGLO5_SET(x)               (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
+#define RF5G_RF5G1_LO5_ATB_SEL_MSB               6
+#define RF5G_RF5G1_LO5_ATB_SEL_LSB               4
+#define RF5G_RF5G1_LO5_ATB_SEL_MASK              0x00000070
+#define RF5G_RF5G1_LO5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
+#define RF5G_RF5G1_LO5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
+#define RF5G_RF5G1_LO5CONTROL_MSB                3
+#define RF5G_RF5G1_LO5CONTROL_LSB                3
+#define RF5G_RF5G1_LO5CONTROL_MASK               0x00000008
+#define RF5G_RF5G1_LO5CONTROL_GET(x)             (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
+#define RF5G_RF5G1_LO5CONTROL_SET(x)             (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
+#define RF5G_RF5G1_REGLO_BYPASS5_MSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_LSB             2
+#define RF5G_RF5G1_REGLO_BYPASS5_MASK            0x00000004
+#define RF5G_RF5G1_REGLO_BYPASS5_GET(x)          (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
+#define RF5G_RF5G1_REGLO_BYPASS5_SET(x)          (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
+#define RF5G_RF5G1_SPARE_MSB                     1
+#define RF5G_RF5G1_SPARE_LSB                     0
+#define RF5G_RF5G1_SPARE_MASK                    0x00000003
+#define RF5G_RF5G1_SPARE_GET(x)                  (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
+#define RF5G_RF5G1_SPARE_SET(x)                  (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
+
+#define RF5G_RF5G2_ADDRESS                       0x00000024
+#define RF5G_RF5G2_OFFSET                        0x00000024
+#define RF5G_RF5G2_AGCLO_B_MSB                   31
+#define RF5G_RF5G2_AGCLO_B_LSB                   29
+#define RF5G_RF5G2_AGCLO_B_MASK                  0xe0000000
+#define RF5G_RF5G2_AGCLO_B_GET(x)                (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
+#define RF5G_RF5G2_AGCLO_B_SET(x)                (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
+#define RF5G_RF5G2_RX5_ATB_SEL_MSB               28
+#define RF5G_RF5G2_RX5_ATB_SEL_LSB               26
+#define RF5G_RF5G2_RX5_ATB_SEL_MASK              0x1c000000
+#define RF5G_RF5G2_RX5_ATB_SEL_GET(x)            (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
+#define RF5G_RF5G2_RX5_ATB_SEL_SET(x)            (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
+#define RF5G_RF5G2_PDCMOSLO5_MSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_LSB                 25
+#define RF5G_RF5G2_PDCMOSLO5_MASK                0x02000000
+#define RF5G_RF5G2_PDCMOSLO5_GET(x)              (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
+#define RF5G_RF5G2_PDCMOSLO5_SET(x)              (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
+#define RF5G_RF5G2_PDVGM5_MSB                    24
+#define RF5G_RF5G2_PDVGM5_LSB                    24
+#define RF5G_RF5G2_PDVGM5_MASK                   0x01000000
+#define RF5G_RF5G2_PDVGM5_GET(x)                 (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
+#define RF5G_RF5G2_PDVGM5_SET(x)                 (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
+#define RF5G_RF5G2_PDCSLNA5_MSB                  23
+#define RF5G_RF5G2_PDCSLNA5_LSB                  23
+#define RF5G_RF5G2_PDCSLNA5_MASK                 0x00800000
+#define RF5G_RF5G2_PDCSLNA5_GET(x)               (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
+#define RF5G_RF5G2_PDCSLNA5_SET(x)               (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
+#define RF5G_RF5G2_PDRFVGA5_MSB                  22
+#define RF5G_RF5G2_PDRFVGA5_LSB                  22
+#define RF5G_RF5G2_PDRFVGA5_MASK                 0x00400000
+#define RF5G_RF5G2_PDRFVGA5_GET(x)               (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
+#define RF5G_RF5G2_PDRFVGA5_SET(x)               (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
+#define RF5G_RF5G2_PDREGFE5_MSB                  21
+#define RF5G_RF5G2_PDREGFE5_LSB                  21
+#define RF5G_RF5G2_PDREGFE5_MASK                 0x00200000
+#define RF5G_RF5G2_PDREGFE5_GET(x)               (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
+#define RF5G_RF5G2_PDREGFE5_SET(x)               (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
+#define RF5G_RF5G2_TUNE_RFVGA5_MSB               20
+#define RF5G_RF5G2_TUNE_RFVGA5_LSB               18
+#define RF5G_RF5G2_TUNE_RFVGA5_MASK              0x001c0000
+#define RF5G_RF5G2_TUNE_RFVGA5_GET(x)            (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
+#define RF5G_RF5G2_TUNE_RFVGA5_SET(x)            (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
+#define RF5G_RF5G2_BRFVGA5_MSB                   17
+#define RF5G_RF5G2_BRFVGA5_LSB                   15
+#define RF5G_RF5G2_BRFVGA5_MASK                  0x00038000
+#define RF5G_RF5G2_BRFVGA5_GET(x)                (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
+#define RF5G_RF5G2_BRFVGA5_SET(x)                (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
+#define RF5G_RF5G2_BCSLNA5_MSB                   14
+#define RF5G_RF5G2_BCSLNA5_LSB                   12
+#define RF5G_RF5G2_BCSLNA5_MASK                  0x00007000
+#define RF5G_RF5G2_BCSLNA5_GET(x)                (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
+#define RF5G_RF5G2_BCSLNA5_SET(x)                (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
+#define RF5G_RF5G2_BVGM5_MSB                     11
+#define RF5G_RF5G2_BVGM5_LSB                     9
+#define RF5G_RF5G2_BVGM5_MASK                    0x00000e00
+#define RF5G_RF5G2_BVGM5_GET(x)                  (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
+#define RF5G_RF5G2_BVGM5_SET(x)                  (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
+#define RF5G_RF5G2_REGFE_BYPASS5_MSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_LSB             8
+#define RF5G_RF5G2_REGFE_BYPASS5_MASK            0x00000100
+#define RF5G_RF5G2_REGFE_BYPASS5_GET(x)          (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
+#define RF5G_RF5G2_REGFE_BYPASS5_SET(x)          (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
+#define RF5G_RF5G2_LNA5_ATTENMODE_MSB            7
+#define RF5G_RF5G2_LNA5_ATTENMODE_LSB            6
+#define RF5G_RF5G2_LNA5_ATTENMODE_MASK           0x000000c0
+#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x)         (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
+#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x)         (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
+#define RF5G_RF5G2_ENABLE_PCA_MSB                5
+#define RF5G_RF5G2_ENABLE_PCA_LSB                5
+#define RF5G_RF5G2_ENABLE_PCA_MASK               0x00000020
+#define RF5G_RF5G2_ENABLE_PCA_GET(x)             (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
+#define RF5G_RF5G2_ENABLE_PCA_SET(x)             (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
+#define RF5G_RF5G2_TUNE_LO_MSB                   4
+#define RF5G_RF5G2_TUNE_LO_LSB                   2
+#define RF5G_RF5G2_TUNE_LO_MASK                  0x0000001c
+#define RF5G_RF5G2_TUNE_LO_GET(x)                (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
+#define RF5G_RF5G2_TUNE_LO_SET(x)                (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
+#define RF5G_RF5G2_SPARE_MSB                     1
+#define RF5G_RF5G2_SPARE_LSB                     0
+#define RF5G_RF5G2_SPARE_MASK                    0x00000003
+#define RF5G_RF5G2_SPARE_GET(x)                  (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
+#define RF5G_RF5G2_SPARE_SET(x)                  (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
+
+#define RF2G_RF2G1_ADDRESS                       0x00000028
+#define RF2G_RF2G1_OFFSET                        0x00000028
+#define RF2G_RF2G1_BLNA1_MSB                     31
+#define RF2G_RF2G1_BLNA1_LSB                     29
+#define RF2G_RF2G1_BLNA1_MASK                    0xe0000000
+#define RF2G_RF2G1_BLNA1_GET(x)                  (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
+#define RF2G_RF2G1_BLNA1_SET(x)                  (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
+#define RF2G_RF2G1_BLNA1F_MSB                    28
+#define RF2G_RF2G1_BLNA1F_LSB                    26
+#define RF2G_RF2G1_BLNA1F_MASK                   0x1c000000
+#define RF2G_RF2G1_BLNA1F_GET(x)                 (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
+#define RF2G_RF2G1_BLNA1F_SET(x)                 (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
+#define RF2G_RF2G1_BLNA1BUF_MSB                  25
+#define RF2G_RF2G1_BLNA1BUF_LSB                  23
+#define RF2G_RF2G1_BLNA1BUF_MASK                 0x03800000
+#define RF2G_RF2G1_BLNA1BUF_GET(x)               (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
+#define RF2G_RF2G1_BLNA1BUF_SET(x)               (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
+#define RF2G_RF2G1_BLNA2_MSB                     22
+#define RF2G_RF2G1_BLNA2_LSB                     20
+#define RF2G_RF2G1_BLNA2_MASK                    0x00700000
+#define RF2G_RF2G1_BLNA2_GET(x)                  (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
+#define RF2G_RF2G1_BLNA2_SET(x)                  (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
+#define RF2G_RF2G1_DB_MSB                        19
+#define RF2G_RF2G1_DB_LSB                        17
+#define RF2G_RF2G1_DB_MASK                       0x000e0000
+#define RF2G_RF2G1_DB_GET(x)                     (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
+#define RF2G_RF2G1_DB_SET(x)                     (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
+#define RF2G_RF2G1_OB_MSB                        16
+#define RF2G_RF2G1_OB_LSB                        14
+#define RF2G_RF2G1_OB_MASK                       0x0001c000
+#define RF2G_RF2G1_OB_GET(x)                     (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
+#define RF2G_RF2G1_OB_SET(x)                     (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
+#define RF2G_RF2G1_FE_ATB_SEL_MSB                13
+#define RF2G_RF2G1_FE_ATB_SEL_LSB                11
+#define RF2G_RF2G1_FE_ATB_SEL_MASK               0x00003800
+#define RF2G_RF2G1_FE_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
+#define RF2G_RF2G1_FE_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
+#define RF2G_RF2G1_RF_ATB_SEL_MSB                10
+#define RF2G_RF2G1_RF_ATB_SEL_LSB                8
+#define RF2G_RF2G1_RF_ATB_SEL_MASK               0x00000700
+#define RF2G_RF2G1_RF_ATB_SEL_GET(x)             (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
+#define RF2G_RF2G1_RF_ATB_SEL_SET(x)             (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
+#define RF2G_RF2G1_SELLNA_MSB                    7
+#define RF2G_RF2G1_SELLNA_LSB                    7
+#define RF2G_RF2G1_SELLNA_MASK                   0x00000080
+#define RF2G_RF2G1_SELLNA_GET(x)                 (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
+#define RF2G_RF2G1_SELLNA_SET(x)                 (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
+#define RF2G_RF2G1_LOCONTROL_MSB                 6
+#define RF2G_RF2G1_LOCONTROL_LSB                 6
+#define RF2G_RF2G1_LOCONTROL_MASK                0x00000040
+#define RF2G_RF2G1_LOCONTROL_GET(x)              (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
+#define RF2G_RF2G1_LOCONTROL_SET(x)              (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
+#define RF2G_RF2G1_SHORTLNA2_MSB                 5
+#define RF2G_RF2G1_SHORTLNA2_LSB                 5
+#define RF2G_RF2G1_SHORTLNA2_MASK                0x00000020
+#define RF2G_RF2G1_SHORTLNA2_GET(x)              (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
+#define RF2G_RF2G1_SHORTLNA2_SET(x)              (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
+#define RF2G_RF2G1_SPARE_MSB                     4
+#define RF2G_RF2G1_SPARE_LSB                     0
+#define RF2G_RF2G1_SPARE_MASK                    0x0000001f
+#define RF2G_RF2G1_SPARE_GET(x)                  (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
+#define RF2G_RF2G1_SPARE_SET(x)                  (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
+
+#define RF2G_RF2G2_ADDRESS                       0x0000002c
+#define RF2G_RF2G2_OFFSET                        0x0000002c
+#define RF2G_RF2G2_PDCGLNA_MSB                   31
+#define RF2G_RF2G2_PDCGLNA_LSB                   31
+#define RF2G_RF2G2_PDCGLNA_MASK                  0x80000000
+#define RF2G_RF2G2_PDCGLNA_GET(x)                (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
+#define RF2G_RF2G2_PDCGLNA_SET(x)                (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
+#define RF2G_RF2G2_PDCGLNABUF_MSB                30
+#define RF2G_RF2G2_PDCGLNABUF_LSB                30
+#define RF2G_RF2G2_PDCGLNABUF_MASK               0x40000000
+#define RF2G_RF2G2_PDCGLNABUF_GET(x)             (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
+#define RF2G_RF2G2_PDCGLNABUF_SET(x)             (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
+#define RF2G_RF2G2_PDCSLNA_MSB                   29
+#define RF2G_RF2G2_PDCSLNA_LSB                   29
+#define RF2G_RF2G2_PDCSLNA_MASK                  0x20000000
+#define RF2G_RF2G2_PDCSLNA_GET(x)                (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
+#define RF2G_RF2G2_PDCSLNA_SET(x)                (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
+#define RF2G_RF2G2_PDDIV_MSB                     28
+#define RF2G_RF2G2_PDDIV_LSB                     28
+#define RF2G_RF2G2_PDDIV_MASK                    0x10000000
+#define RF2G_RF2G2_PDDIV_GET(x)                  (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
+#define RF2G_RF2G2_PDDIV_SET(x)                  (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
+#define RF2G_RF2G2_PDPADRV_MSB                   27
+#define RF2G_RF2G2_PDPADRV_LSB                   27
+#define RF2G_RF2G2_PDPADRV_MASK                  0x08000000
+#define RF2G_RF2G2_PDPADRV_GET(x)                (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
+#define RF2G_RF2G2_PDPADRV_SET(x)                (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
+#define RF2G_RF2G2_PDPAOUT_MSB                   26
+#define RF2G_RF2G2_PDPAOUT_LSB                   26
+#define RF2G_RF2G2_PDPAOUT_MASK                  0x04000000
+#define RF2G_RF2G2_PDPAOUT_GET(x)                (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
+#define RF2G_RF2G2_PDPAOUT_SET(x)                (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
+#define RF2G_RF2G2_PDREGLNA_MSB                  25
+#define RF2G_RF2G2_PDREGLNA_LSB                  25
+#define RF2G_RF2G2_PDREGLNA_MASK                 0x02000000
+#define RF2G_RF2G2_PDREGLNA_GET(x)               (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
+#define RF2G_RF2G2_PDREGLNA_SET(x)               (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
+#define RF2G_RF2G2_PDREGLO_MSB                   24
+#define RF2G_RF2G2_PDREGLO_LSB                   24
+#define RF2G_RF2G2_PDREGLO_MASK                  0x01000000
+#define RF2G_RF2G2_PDREGLO_GET(x)                (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
+#define RF2G_RF2G2_PDREGLO_SET(x)                (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
+#define RF2G_RF2G2_PDRFGM_MSB                    23
+#define RF2G_RF2G2_PDRFGM_LSB                    23
+#define RF2G_RF2G2_PDRFGM_MASK                   0x00800000
+#define RF2G_RF2G2_PDRFGM_GET(x)                 (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
+#define RF2G_RF2G2_PDRFGM_SET(x)                 (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
+#define RF2G_RF2G2_PDRXLO_MSB                    22
+#define RF2G_RF2G2_PDRXLO_LSB                    22
+#define RF2G_RF2G2_PDRXLO_MASK                   0x00400000
+#define RF2G_RF2G2_PDRXLO_GET(x)                 (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
+#define RF2G_RF2G2_PDRXLO_SET(x)                 (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
+#define RF2G_RF2G2_PDTXLO_MSB                    21
+#define RF2G_RF2G2_PDTXLO_LSB                    21
+#define RF2G_RF2G2_PDTXLO_MASK                   0x00200000
+#define RF2G_RF2G2_PDTXLO_GET(x)                 (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
+#define RF2G_RF2G2_PDTXLO_SET(x)                 (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
+#define RF2G_RF2G2_PDTXMIX_MSB                   20
+#define RF2G_RF2G2_PDTXMIX_LSB                   20
+#define RF2G_RF2G2_PDTXMIX_MASK                  0x00100000
+#define RF2G_RF2G2_PDTXMIX_GET(x)                (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
+#define RF2G_RF2G2_PDTXMIX_SET(x)                (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
+#define RF2G_RF2G2_REGLNA_BYPASS_MSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_LSB             19
+#define RF2G_RF2G2_REGLNA_BYPASS_MASK            0x00080000
+#define RF2G_RF2G2_REGLNA_BYPASS_GET(x)          (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
+#define RF2G_RF2G2_REGLNA_BYPASS_SET(x)          (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
+#define RF2G_RF2G2_REGLO_BYPASS_MSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_LSB              18
+#define RF2G_RF2G2_REGLO_BYPASS_MASK             0x00040000
+#define RF2G_RF2G2_REGLO_BYPASS_GET(x)           (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
+#define RF2G_RF2G2_REGLO_BYPASS_SET(x)           (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
+#define RF2G_RF2G2_ENABLE_PCB_MSB                17
+#define RF2G_RF2G2_ENABLE_PCB_LSB                17
+#define RF2G_RF2G2_ENABLE_PCB_MASK               0x00020000
+#define RF2G_RF2G2_ENABLE_PCB_GET(x)             (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
+#define RF2G_RF2G2_ENABLE_PCB_SET(x)             (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
+#define RF2G_RF2G2_SPARE_MSB                     16
+#define RF2G_RF2G2_SPARE_LSB                     0
+#define RF2G_RF2G2_SPARE_MASK                    0x0001ffff
+#define RF2G_RF2G2_SPARE_GET(x)                  (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
+#define RF2G_RF2G2_SPARE_SET(x)                  (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
+
+#define TOP_GAIN_ADDRESS                         0x00000030
+#define TOP_GAIN_OFFSET                          0x00000030
+#define TOP_GAIN_TX6DBLOQGAIN_MSB                31
+#define TOP_GAIN_TX6DBLOQGAIN_LSB                30
+#define TOP_GAIN_TX6DBLOQGAIN_MASK               0xc0000000
+#define TOP_GAIN_TX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
+#define TOP_GAIN_TX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
+#define TOP_GAIN_TX1DBLOQGAIN_MSB                29
+#define TOP_GAIN_TX1DBLOQGAIN_LSB                27
+#define TOP_GAIN_TX1DBLOQGAIN_MASK               0x38000000
+#define TOP_GAIN_TX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
+#define TOP_GAIN_TX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
+#define TOP_GAIN_TXV2IGAIN_MSB                   26
+#define TOP_GAIN_TXV2IGAIN_LSB                   25
+#define TOP_GAIN_TXV2IGAIN_MASK                  0x06000000
+#define TOP_GAIN_TXV2IGAIN_GET(x)                (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
+#define TOP_GAIN_TXV2IGAIN_SET(x)                (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
+#define TOP_GAIN_PABUF5GN_MSB                    24
+#define TOP_GAIN_PABUF5GN_LSB                    24
+#define TOP_GAIN_PABUF5GN_MASK                   0x01000000
+#define TOP_GAIN_PABUF5GN_GET(x)                 (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
+#define TOP_GAIN_PABUF5GN_SET(x)                 (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
+#define TOP_GAIN_PADRVGN_MSB                     23
+#define TOP_GAIN_PADRVGN_LSB                     21
+#define TOP_GAIN_PADRVGN_MASK                    0x00e00000
+#define TOP_GAIN_PADRVGN_GET(x)                  (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
+#define TOP_GAIN_PADRVGN_SET(x)                  (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
+#define TOP_GAIN_PAOUT2GN_MSB                    20
+#define TOP_GAIN_PAOUT2GN_LSB                    18
+#define TOP_GAIN_PAOUT2GN_MASK                   0x001c0000
+#define TOP_GAIN_PAOUT2GN_GET(x)                 (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
+#define TOP_GAIN_PAOUT2GN_SET(x)                 (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
+#define TOP_GAIN_LNAON_MSB                       17
+#define TOP_GAIN_LNAON_LSB                       17
+#define TOP_GAIN_LNAON_MASK                      0x00020000
+#define TOP_GAIN_LNAON_GET(x)                    (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
+#define TOP_GAIN_LNAON_SET(x)                    (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
+#define TOP_GAIN_LNAGAIN_MSB                     16
+#define TOP_GAIN_LNAGAIN_LSB                     13
+#define TOP_GAIN_LNAGAIN_MASK                    0x0001e000
+#define TOP_GAIN_LNAGAIN_GET(x)                  (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
+#define TOP_GAIN_LNAGAIN_SET(x)                  (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
+#define TOP_GAIN_RFVGA5GAIN_MSB                  12
+#define TOP_GAIN_RFVGA5GAIN_LSB                  11
+#define TOP_GAIN_RFVGA5GAIN_MASK                 0x00001800
+#define TOP_GAIN_RFVGA5GAIN_GET(x)               (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
+#define TOP_GAIN_RFVGA5GAIN_SET(x)               (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
+#define TOP_GAIN_RFGMGN_MSB                      10
+#define TOP_GAIN_RFGMGN_LSB                      8
+#define TOP_GAIN_RFGMGN_MASK                     0x00000700
+#define TOP_GAIN_RFGMGN_GET(x)                   (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
+#define TOP_GAIN_RFGMGN_SET(x)                   (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
+#define TOP_GAIN_RX6DBLOQGAIN_MSB                7
+#define TOP_GAIN_RX6DBLOQGAIN_LSB                6
+#define TOP_GAIN_RX6DBLOQGAIN_MASK               0x000000c0
+#define TOP_GAIN_RX6DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
+#define TOP_GAIN_RX6DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
+#define TOP_GAIN_RX1DBLOQGAIN_MSB                5
+#define TOP_GAIN_RX1DBLOQGAIN_LSB                3
+#define TOP_GAIN_RX1DBLOQGAIN_MASK               0x00000038
+#define TOP_GAIN_RX1DBLOQGAIN_GET(x)             (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
+#define TOP_GAIN_RX1DBLOQGAIN_SET(x)             (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
+#define TOP_GAIN_RX6DBHIQGAIN_MSB                2
+#define TOP_GAIN_RX6DBHIQGAIN_LSB                1
+#define TOP_GAIN_RX6DBHIQGAIN_MASK               0x00000006
+#define TOP_GAIN_RX6DBHIQGAIN_GET(x)             (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
+#define TOP_GAIN_RX6DBHIQGAIN_SET(x)             (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
+#define TOP_GAIN_SPARE_MSB                       0
+#define TOP_GAIN_SPARE_LSB                       0
+#define TOP_GAIN_SPARE_MASK                      0x00000001
+#define TOP_GAIN_SPARE_GET(x)                    (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
+#define TOP_GAIN_SPARE_SET(x)                    (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
+
+#define TOP_TOP_ADDRESS                          0x00000034
+#define TOP_TOP_OFFSET                           0x00000034
+#define TOP_TOP_LOCALTXGAIN_MSB                  31
+#define TOP_TOP_LOCALTXGAIN_LSB                  31
+#define TOP_TOP_LOCALTXGAIN_MASK                 0x80000000
+#define TOP_TOP_LOCALTXGAIN_GET(x)               (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
+#define TOP_TOP_LOCALTXGAIN_SET(x)               (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
+#define TOP_TOP_LOCALRXGAIN_MSB                  30
+#define TOP_TOP_LOCALRXGAIN_LSB                  30
+#define TOP_TOP_LOCALRXGAIN_MASK                 0x40000000
+#define TOP_TOP_LOCALRXGAIN_GET(x)               (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
+#define TOP_TOP_LOCALRXGAIN_SET(x)               (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
+#define TOP_TOP_LOCALMODE_MSB                    29
+#define TOP_TOP_LOCALMODE_LSB                    29
+#define TOP_TOP_LOCALMODE_MASK                   0x20000000
+#define TOP_TOP_LOCALMODE_GET(x)                 (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
+#define TOP_TOP_LOCALMODE_SET(x)                 (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
+#define TOP_TOP_CALFC_MSB                        28
+#define TOP_TOP_CALFC_LSB                        28
+#define TOP_TOP_CALFC_MASK                       0x10000000
+#define TOP_TOP_CALFC_GET(x)                     (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
+#define TOP_TOP_CALFC_SET(x)                     (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
+#define TOP_TOP_CALDC_MSB                        27
+#define TOP_TOP_CALDC_LSB                        27
+#define TOP_TOP_CALDC_MASK                       0x08000000
+#define TOP_TOP_CALDC_GET(x)                     (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
+#define TOP_TOP_CALDC_SET(x)                     (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
+#define TOP_TOP_CAL_RESIDUE_MSB                  26
+#define TOP_TOP_CAL_RESIDUE_LSB                  26
+#define TOP_TOP_CAL_RESIDUE_MASK                 0x04000000
+#define TOP_TOP_CAL_RESIDUE_GET(x)               (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
+#define TOP_TOP_CAL_RESIDUE_SET(x)               (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
+#define TOP_TOP_BMODE_MSB                        25
+#define TOP_TOP_BMODE_LSB                        25
+#define TOP_TOP_BMODE_MASK                       0x02000000
+#define TOP_TOP_BMODE_GET(x)                     (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
+#define TOP_TOP_BMODE_SET(x)                     (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
+#define TOP_TOP_SYNTHON_MSB                      24
+#define TOP_TOP_SYNTHON_LSB                      24
+#define TOP_TOP_SYNTHON_MASK                     0x01000000
+#define TOP_TOP_SYNTHON_GET(x)                   (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
+#define TOP_TOP_SYNTHON_SET(x)                   (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
+#define TOP_TOP_RXON_MSB                         23
+#define TOP_TOP_RXON_LSB                         23
+#define TOP_TOP_RXON_MASK                        0x00800000
+#define TOP_TOP_RXON_GET(x)                      (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
+#define TOP_TOP_RXON_SET(x)                      (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
+#define TOP_TOP_TXON_MSB                         22
+#define TOP_TOP_TXON_LSB                         22
+#define TOP_TOP_TXON_MASK                        0x00400000
+#define TOP_TOP_TXON_GET(x)                      (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
+#define TOP_TOP_TXON_SET(x)                      (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
+#define TOP_TOP_PAON_MSB                         21
+#define TOP_TOP_PAON_LSB                         21
+#define TOP_TOP_PAON_MASK                        0x00200000
+#define TOP_TOP_PAON_GET(x)                      (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
+#define TOP_TOP_PAON_SET(x)                      (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
+#define TOP_TOP_CALTX_MSB                        20
+#define TOP_TOP_CALTX_LSB                        20
+#define TOP_TOP_CALTX_MASK                       0x00100000
+#define TOP_TOP_CALTX_GET(x)                     (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
+#define TOP_TOP_CALTX_SET(x)                     (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
+#define TOP_TOP_LOCALADDAC_MSB                   19
+#define TOP_TOP_LOCALADDAC_LSB                   19
+#define TOP_TOP_LOCALADDAC_MASK                  0x00080000
+#define TOP_TOP_LOCALADDAC_GET(x)                (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
+#define TOP_TOP_LOCALADDAC_SET(x)                (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
+#define TOP_TOP_PWDPLL_MSB                       18
+#define TOP_TOP_PWDPLL_LSB                       18
+#define TOP_TOP_PWDPLL_MASK                      0x00040000
+#define TOP_TOP_PWDPLL_GET(x)                    (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
+#define TOP_TOP_PWDPLL_SET(x)                    (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
+#define TOP_TOP_PWDADC_MSB                       17
+#define TOP_TOP_PWDADC_LSB                       17
+#define TOP_TOP_PWDADC_MASK                      0x00020000
+#define TOP_TOP_PWDADC_GET(x)                    (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
+#define TOP_TOP_PWDADC_SET(x)                    (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
+#define TOP_TOP_PWDDAC_MSB                       16
+#define TOP_TOP_PWDDAC_LSB                       16
+#define TOP_TOP_PWDDAC_MASK                      0x00010000
+#define TOP_TOP_PWDDAC_GET(x)                    (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
+#define TOP_TOP_PWDDAC_SET(x)                    (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
+#define TOP_TOP_LOCALXTAL_MSB                    15
+#define TOP_TOP_LOCALXTAL_LSB                    15
+#define TOP_TOP_LOCALXTAL_MASK                   0x00008000
+#define TOP_TOP_LOCALXTAL_GET(x)                 (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
+#define TOP_TOP_LOCALXTAL_SET(x)                 (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
+#define TOP_TOP_PWDCLKIN_MSB                     14
+#define TOP_TOP_PWDCLKIN_LSB                     14
+#define TOP_TOP_PWDCLKIN_MASK                    0x00004000
+#define TOP_TOP_PWDCLKIN_GET(x)                  (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
+#define TOP_TOP_PWDCLKIN_SET(x)                  (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
+#define TOP_TOP_OSCON_MSB                        13
+#define TOP_TOP_OSCON_LSB                        13
+#define TOP_TOP_OSCON_MASK                       0x00002000
+#define TOP_TOP_OSCON_GET(x)                     (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
+#define TOP_TOP_OSCON_SET(x)                     (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
+#define TOP_TOP_SCLKEN_FORCE_MSB                 12
+#define TOP_TOP_SCLKEN_FORCE_LSB                 12
+#define TOP_TOP_SCLKEN_FORCE_MASK                0x00001000
+#define TOP_TOP_SCLKEN_FORCE_GET(x)              (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
+#define TOP_TOP_SCLKEN_FORCE_SET(x)              (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
+#define TOP_TOP_SYNTHON_FORCE_MSB                11
+#define TOP_TOP_SYNTHON_FORCE_LSB                11
+#define TOP_TOP_SYNTHON_FORCE_MASK               0x00000800
+#define TOP_TOP_SYNTHON_FORCE_GET(x)             (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
+#define TOP_TOP_SYNTHON_FORCE_SET(x)             (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
+#define TOP_TOP_PDBIAS_MSB                       10
+#define TOP_TOP_PDBIAS_LSB                       10
+#define TOP_TOP_PDBIAS_MASK                      0x00000400
+#define TOP_TOP_PDBIAS_GET(x)                    (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
+#define TOP_TOP_PDBIAS_SET(x)                    (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
+#define TOP_TOP_DATAOUTSEL_MSB                   9
+#define TOP_TOP_DATAOUTSEL_LSB                   8
+#define TOP_TOP_DATAOUTSEL_MASK                  0x00000300
+#define TOP_TOP_DATAOUTSEL_GET(x)                (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
+#define TOP_TOP_DATAOUTSEL_SET(x)                (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
+#define TOP_TOP_REVID_MSB                        7
+#define TOP_TOP_REVID_LSB                        5
+#define TOP_TOP_REVID_MASK                       0x000000e0
+#define TOP_TOP_REVID_GET(x)                     (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
+#define TOP_TOP_REVID_SET(x)                     (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
+#define TOP_TOP_INT2PAD_MSB                      4
+#define TOP_TOP_INT2PAD_LSB                      4
+#define TOP_TOP_INT2PAD_MASK                     0x00000010
+#define TOP_TOP_INT2PAD_GET(x)                   (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
+#define TOP_TOP_INT2PAD_SET(x)                   (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
+#define TOP_TOP_INTH2PAD_MSB                     3
+#define TOP_TOP_INTH2PAD_LSB                     3
+#define TOP_TOP_INTH2PAD_MASK                    0x00000008
+#define TOP_TOP_INTH2PAD_GET(x)                  (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
+#define TOP_TOP_INTH2PAD_SET(x)                  (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
+#define TOP_TOP_PAD2GND_MSB                      2
+#define TOP_TOP_PAD2GND_LSB                      2
+#define TOP_TOP_PAD2GND_MASK                     0x00000004
+#define TOP_TOP_PAD2GND_GET(x)                   (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
+#define TOP_TOP_PAD2GND_SET(x)                   (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
+#define TOP_TOP_INT2GND_MSB                      1
+#define TOP_TOP_INT2GND_LSB                      1
+#define TOP_TOP_INT2GND_MASK                     0x00000002
+#define TOP_TOP_INT2GND_GET(x)                   (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
+#define TOP_TOP_INT2GND_SET(x)                   (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
+#define TOP_TOP_FORCE_XPAON_MSB                  0
+#define TOP_TOP_FORCE_XPAON_LSB                  0
+#define TOP_TOP_FORCE_XPAON_MASK                 0x00000001
+#define TOP_TOP_FORCE_XPAON_GET(x)               (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
+#define TOP_TOP_FORCE_XPAON_SET(x)               (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
+
+#define BIAS_BIAS_SEL_ADDRESS                    0x00000038
+#define BIAS_BIAS_SEL_OFFSET                     0x00000038
+#define BIAS_BIAS_SEL_PADON_MSB                  31
+#define BIAS_BIAS_SEL_PADON_LSB                  31
+#define BIAS_BIAS_SEL_PADON_MASK                 0x80000000
+#define BIAS_BIAS_SEL_PADON_GET(x)               (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
+#define BIAS_BIAS_SEL_PADON_SET(x)               (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
+#define BIAS_BIAS_SEL_SEL_BIAS_MSB               30
+#define BIAS_BIAS_SEL_SEL_BIAS_LSB               25
+#define BIAS_BIAS_SEL_SEL_BIAS_MASK              0x7e000000
+#define BIAS_BIAS_SEL_SEL_BIAS_GET(x)            (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
+#define BIAS_BIAS_SEL_SEL_BIAS_SET(x)            (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
+#define BIAS_BIAS_SEL_SEL_SPARE_MSB              24
+#define BIAS_BIAS_SEL_SEL_SPARE_LSB              21
+#define BIAS_BIAS_SEL_SEL_SPARE_MASK             0x01e00000
+#define BIAS_BIAS_SEL_SEL_SPARE_GET(x)           (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SEL_SPARE_SET(x)           (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_SPARE_MSB                  20
+#define BIAS_BIAS_SEL_SPARE_LSB                  20
+#define BIAS_BIAS_SEL_SPARE_MASK                 0x00100000
+#define BIAS_BIAS_SEL_SPARE_GET(x)               (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SPARE_SET(x)               (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB   19
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB   17
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK  0x000e0000
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB    16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK   0x00010000
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB   14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK  0x00004000
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB           13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK          0x00002000
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB       12
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB       10
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK      0x00001c00
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x)    (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x)    (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB           9
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB           7
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK          0x00000380
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB          6
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB          4
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK         0x00000070
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x)       (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x)       (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB           3
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB           1
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK          0x0000000e
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x)        (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x)        (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB            0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK           0x00000001
+#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x)         (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x)         (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
+
+#define BIAS_BIAS1_ADDRESS                       0x0000003c
+#define BIAS_BIAS1_OFFSET                        0x0000003c
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB            31
+#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB            29
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK           0xe0000000
+#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x)         (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
+#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x)         (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
+#define BIAS_BIAS1_PWD_IC2GVGM25_MSB             28
+#define BIAS_BIAS1_PWD_IC2GVGM25_LSB             26
+#define BIAS_BIAS1_PWD_IC2GVGM25_MASK            0x1c000000
+#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x)          (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
+#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x)          (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB            25
+#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB            23
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK           0x03800000
+#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB           22
+#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB           20
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK          0x00700000
+#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB          19
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB          17
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK         0x000e0000
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x)       (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x)       (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB         16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK        0x00010000
+#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB         15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK        0x00008000
+#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x)      (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x)      (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB            14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK           0x00004000
+#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB            13
+#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB            11
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK           0x00003800
+#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB           10
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB           8
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK          0x00000700
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x)        (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x)        (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GQB25_MSB              7
+#define BIAS_BIAS1_PWD_IC5GQB25_LSB              5
+#define BIAS_BIAS1_PWD_IC5GQB25_MASK             0x000000e0
+#define BIAS_BIAS1_PWD_IC5GQB25_GET(x)           (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
+#define BIAS_BIAS1_PWD_IC5GQB25_SET(x)           (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB            4
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB            2
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK           0x0000001c
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x)         (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x)         (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
+#define BIAS_BIAS1_SPARE_MSB                     1
+#define BIAS_BIAS1_SPARE_LSB                     0
+#define BIAS_BIAS1_SPARE_MASK                    0x00000003
+#define BIAS_BIAS1_SPARE_GET(x)                  (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
+#define BIAS_BIAS1_SPARE_SET(x)                  (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
+
+#define BIAS_BIAS2_ADDRESS                       0x00000040
+#define BIAS_BIAS2_OFFSET                        0x00000040
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB            31
+#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB            29
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK           0xe0000000
+#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x)         (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
+#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x)         (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
+#define BIAS_BIAS2_PWD_IC5GDIV25_MSB             28
+#define BIAS_BIAS2_PWD_IC5GDIV25_LSB             26
+#define BIAS_BIAS2_PWD_IC5GDIV25_MASK            0x1c000000
+#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x)          (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
+#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x)          (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB           25
+#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB           23
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK          0x03800000
+#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IRPLL25_MSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_LSB               22
+#define BIAS_BIAS2_PWD_IRPLL25_MASK              0x00400000
+#define BIAS_BIAS2_PWD_IRPLL25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
+#define BIAS_BIAS2_PWD_IRPLL25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
+#define BIAS_BIAS2_PWD_IRXTAL25_MSB              21
+#define BIAS_BIAS2_PWD_IRXTAL25_LSB              19
+#define BIAS_BIAS2_PWD_IRXTAL25_MASK             0x00380000
+#define BIAS_BIAS2_PWD_IRXTAL25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
+#define BIAS_BIAS2_PWD_IRXTAL25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
+#define BIAS_BIAS2_PWD_IRTSENS25_MSB             18
+#define BIAS_BIAS2_PWD_IRTSENS25_LSB             16
+#define BIAS_BIAS2_PWD_IRTSENS25_MASK            0x00070000
+#define BIAS_BIAS2_PWD_IRTSENS25_GET(x)          (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
+#define BIAS_BIAS2_PWD_IRTSENS25_SET(x)          (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
+#define BIAS_BIAS2_PWD_IRTXPC25_MSB              15
+#define BIAS_BIAS2_PWD_IRTXPC25_LSB              13
+#define BIAS_BIAS2_PWD_IRTXPC25_MASK             0x0000e000
+#define BIAS_BIAS2_PWD_IRTXPC25_GET(x)           (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
+#define BIAS_BIAS2_PWD_IRTXPC25_SET(x)           (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
+#define BIAS_BIAS2_PWD_IRLDO25_MSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_LSB               12
+#define BIAS_BIAS2_PWD_IRLDO25_MASK              0x00001000
+#define BIAS_BIAS2_PWD_IRLDO25_GET(x)            (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
+#define BIAS_BIAS2_PWD_IRLDO25_SET(x)            (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB           11
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB           9
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK          0x00000e00
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB           8
+#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB           6
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK          0x000001c0
+#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x)        (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x)        (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB          5
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB          3
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK         0x00000038
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x)       (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x)       (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB        2
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB        0
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK       0x00000007
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x)     (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x)     (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
+
+#define BIAS_BIAS3_ADDRESS                       0x00000044
+#define BIAS_BIAS3_OFFSET                        0x00000044
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB           31
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB           29
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK          0xe0000000
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x)        (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x)        (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
+#define BIAS_BIAS3_PWD_IR5GAGC25_MSB             28
+#define BIAS_BIAS3_PWD_IR5GAGC25_LSB             26
+#define BIAS_BIAS3_PWD_IR5GAGC25_MASK            0x1c000000
+#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x)          (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
+#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x)          (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
+#define BIAS_BIAS3_PWD_ICDAC50_MSB               25
+#define BIAS_BIAS3_PWD_ICDAC50_LSB               23
+#define BIAS_BIAS3_PWD_ICDAC50_MASK              0x03800000
+#define BIAS_BIAS3_PWD_ICDAC50_GET(x)            (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
+#define BIAS_BIAS3_PWD_ICDAC50_SET(x)            (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
+#define BIAS_BIAS3_PWD_ICSYNTH50_MSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_LSB             22
+#define BIAS_BIAS3_PWD_ICSYNTH50_MASK            0x00400000
+#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_ICBB50_MSB                21
+#define BIAS_BIAS3_PWD_ICBB50_LSB                21
+#define BIAS_BIAS3_PWD_ICBB50_MASK               0x00200000
+#define BIAS_BIAS3_PWD_ICBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
+#define BIAS_BIAS3_PWD_ICBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
+#define BIAS_BIAS3_PWD_IC2GDIV50_MSB             20
+#define BIAS_BIAS3_PWD_IC2GDIV50_LSB             18
+#define BIAS_BIAS3_PWD_IC2GDIV50_MASK            0x001c0000
+#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x)          (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
+#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x)          (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
+#define BIAS_BIAS3_PWD_IRSYNTH50_MSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_LSB             17
+#define BIAS_BIAS3_PWD_IRSYNTH50_MASK            0x00020000
+#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x)          (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x)          (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_IRBB50_MSB                16
+#define BIAS_BIAS3_PWD_IRBB50_LSB                16
+#define BIAS_BIAS3_PWD_IRBB50_MASK               0x00010000
+#define BIAS_BIAS3_PWD_IRBB50_GET(x)             (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
+#define BIAS_BIAS3_PWD_IRBB50_SET(x)             (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE1_MSB            15
+#define BIAS_BIAS3_PWD_IC25SPARE1_LSB            13
+#define BIAS_BIAS3_PWD_IC25SPARE1_MASK           0x0000e000
+#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE2_MSB            12
+#define BIAS_BIAS3_PWD_IC25SPARE2_LSB            10
+#define BIAS_BIAS3_PWD_IC25SPARE2_MASK           0x00001c00
+#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE1_MSB            9
+#define BIAS_BIAS3_PWD_IR25SPARE1_LSB            7
+#define BIAS_BIAS3_PWD_IR25SPARE1_MASK           0x00000380
+#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE2_MSB            6
+#define BIAS_BIAS3_PWD_IR25SPARE2_LSB            4
+#define BIAS_BIAS3_PWD_IR25SPARE2_MASK           0x00000070
+#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x)         (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x)         (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB          3
+#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB          1
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK         0x0000000e
+#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x)       (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x)       (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
+#define BIAS_BIAS3_SPARE_MSB                     0
+#define BIAS_BIAS3_SPARE_LSB                     0
+#define BIAS_BIAS3_SPARE_MASK                    0x00000001
+#define BIAS_BIAS3_SPARE_GET(x)                  (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
+#define BIAS_BIAS3_SPARE_SET(x)                  (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
+
+#define TXPC_TXPC_ADDRESS                        0x00000048
+#define TXPC_TXPC_OFFSET                         0x00000048
+#define TXPC_TXPC_SELINTPD_MSB                   31
+#define TXPC_TXPC_SELINTPD_LSB                   31
+#define TXPC_TXPC_SELINTPD_MASK                  0x80000000
+#define TXPC_TXPC_SELINTPD_GET(x)                (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
+#define TXPC_TXPC_SELINTPD_SET(x)                (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
+#define TXPC_TXPC_TEST_MSB                       30
+#define TXPC_TXPC_TEST_LSB                       30
+#define TXPC_TXPC_TEST_MASK                      0x40000000
+#define TXPC_TXPC_TEST_GET(x)                    (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
+#define TXPC_TXPC_TEST_SET(x)                    (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
+#define TXPC_TXPC_TESTGAIN_MSB                   29
+#define TXPC_TXPC_TESTGAIN_LSB                   28
+#define TXPC_TXPC_TESTGAIN_MASK                  0x30000000
+#define TXPC_TXPC_TESTGAIN_GET(x)                (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
+#define TXPC_TXPC_TESTGAIN_SET(x)                (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
+#define TXPC_TXPC_TESTDAC_MSB                    27
+#define TXPC_TXPC_TESTDAC_LSB                    22
+#define TXPC_TXPC_TESTDAC_MASK                   0x0fc00000
+#define TXPC_TXPC_TESTDAC_GET(x)                 (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
+#define TXPC_TXPC_TESTDAC_SET(x)                 (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
+#define TXPC_TXPC_TESTPWDPC_MSB                  21
+#define TXPC_TXPC_TESTPWDPC_LSB                  21
+#define TXPC_TXPC_TESTPWDPC_MASK                 0x00200000
+#define TXPC_TXPC_TESTPWDPC_GET(x)               (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
+#define TXPC_TXPC_TESTPWDPC_SET(x)               (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
+#define TXPC_TXPC_CURHALF_MSB                    20
+#define TXPC_TXPC_CURHALF_LSB                    20
+#define TXPC_TXPC_CURHALF_MASK                   0x00100000
+#define TXPC_TXPC_CURHALF_GET(x)                 (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
+#define TXPC_TXPC_CURHALF_SET(x)                 (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
+#define TXPC_TXPC_NEGOUT_MSB                     19
+#define TXPC_TXPC_NEGOUT_LSB                     19
+#define TXPC_TXPC_NEGOUT_MASK                    0x00080000
+#define TXPC_TXPC_NEGOUT_GET(x)                  (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
+#define TXPC_TXPC_NEGOUT_SET(x)                  (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
+#define TXPC_TXPC_CLKDELAY_MSB                   18
+#define TXPC_TXPC_CLKDELAY_LSB                   18
+#define TXPC_TXPC_CLKDELAY_MASK                  0x00040000
+#define TXPC_TXPC_CLKDELAY_GET(x)                (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
+#define TXPC_TXPC_CLKDELAY_SET(x)                (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
+#define TXPC_TXPC_SELMODREF_MSB                  17
+#define TXPC_TXPC_SELMODREF_LSB                  17
+#define TXPC_TXPC_SELMODREF_MASK                 0x00020000
+#define TXPC_TXPC_SELMODREF_GET(x)               (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
+#define TXPC_TXPC_SELMODREF_SET(x)               (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
+#define TXPC_TXPC_SELCMOUT_MSB                   16
+#define TXPC_TXPC_SELCMOUT_LSB                   16
+#define TXPC_TXPC_SELCMOUT_MASK                  0x00010000
+#define TXPC_TXPC_SELCMOUT_GET(x)                (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
+#define TXPC_TXPC_SELCMOUT_SET(x)                (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
+#define TXPC_TXPC_TSMODE_MSB                     15
+#define TXPC_TXPC_TSMODE_LSB                     14
+#define TXPC_TXPC_TSMODE_MASK                    0x0000c000
+#define TXPC_TXPC_TSMODE_GET(x)                  (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
+#define TXPC_TXPC_TSMODE_SET(x)                  (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
+#define TXPC_TXPC_N_MSB                          13
+#define TXPC_TXPC_N_LSB                          6
+#define TXPC_TXPC_N_MASK                         0x00003fc0
+#define TXPC_TXPC_N_GET(x)                       (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
+#define TXPC_TXPC_N_SET(x)                       (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
+#define TXPC_TXPC_ON1STSYNTHON_MSB               5
+#define TXPC_TXPC_ON1STSYNTHON_LSB               5
+#define TXPC_TXPC_ON1STSYNTHON_MASK              0x00000020
+#define TXPC_TXPC_ON1STSYNTHON_GET(x)            (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
+#define TXPC_TXPC_ON1STSYNTHON_SET(x)            (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
+#define TXPC_TXPC_SELINIT_MSB                    4
+#define TXPC_TXPC_SELINIT_LSB                    3
+#define TXPC_TXPC_SELINIT_MASK                   0x00000018
+#define TXPC_TXPC_SELINIT_GET(x)                 (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
+#define TXPC_TXPC_SELINIT_SET(x)                 (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
+#define TXPC_TXPC_SELCOUNT_MSB                   2
+#define TXPC_TXPC_SELCOUNT_LSB                   2
+#define TXPC_TXPC_SELCOUNT_MASK                  0x00000004
+#define TXPC_TXPC_SELCOUNT_GET(x)                (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
+#define TXPC_TXPC_SELCOUNT_SET(x)                (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
+#define TXPC_TXPC_ATBSEL_MSB                     1
+#define TXPC_TXPC_ATBSEL_LSB                     0
+#define TXPC_TXPC_ATBSEL_MASK                    0x00000003
+#define TXPC_TXPC_ATBSEL_GET(x)                  (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
+#define TXPC_TXPC_ATBSEL_SET(x)                  (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
+
+#define TXPC_MISC_ADDRESS                        0x0000004c
+#define TXPC_MISC_OFFSET                         0x0000004c
+#define TXPC_MISC_FLIPBMODE_MSB                  31
+#define TXPC_MISC_FLIPBMODE_LSB                  31
+#define TXPC_MISC_FLIPBMODE_MASK                 0x80000000
+#define TXPC_MISC_FLIPBMODE_GET(x)               (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
+#define TXPC_MISC_FLIPBMODE_SET(x)               (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
+#define TXPC_MISC_LEVEL_MSB                      30
+#define TXPC_MISC_LEVEL_LSB                      29
+#define TXPC_MISC_LEVEL_MASK                     0x60000000
+#define TXPC_MISC_LEVEL_GET(x)                   (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
+#define TXPC_MISC_LEVEL_SET(x)                   (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
+#define TXPC_MISC_LDO_TEST_MODE_MSB              28
+#define TXPC_MISC_LDO_TEST_MODE_LSB              28
+#define TXPC_MISC_LDO_TEST_MODE_MASK             0x10000000
+#define TXPC_MISC_LDO_TEST_MODE_GET(x)           (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
+#define TXPC_MISC_LDO_TEST_MODE_SET(x)           (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
+#define TXPC_MISC_NOTCXODET_MSB                  27
+#define TXPC_MISC_NOTCXODET_LSB                  27
+#define TXPC_MISC_NOTCXODET_MASK                 0x08000000
+#define TXPC_MISC_NOTCXODET_GET(x)               (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
+#define TXPC_MISC_NOTCXODET_SET(x)               (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
+#define TXPC_MISC_PWDCLKIND_MSB                  26
+#define TXPC_MISC_PWDCLKIND_LSB                  26
+#define TXPC_MISC_PWDCLKIND_MASK                 0x04000000
+#define TXPC_MISC_PWDCLKIND_GET(x)               (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
+#define TXPC_MISC_PWDCLKIND_SET(x)               (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
+#define TXPC_MISC_PWDXINPAD_MSB                  25
+#define TXPC_MISC_PWDXINPAD_LSB                  25
+#define TXPC_MISC_PWDXINPAD_MASK                 0x02000000
+#define TXPC_MISC_PWDXINPAD_GET(x)               (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
+#define TXPC_MISC_PWDXINPAD_SET(x)               (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
+#define TXPC_MISC_LOCALBIAS_MSB                  24
+#define TXPC_MISC_LOCALBIAS_LSB                  24
+#define TXPC_MISC_LOCALBIAS_MASK                 0x01000000
+#define TXPC_MISC_LOCALBIAS_GET(x)               (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
+#define TXPC_MISC_LOCALBIAS_SET(x)               (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
+#define TXPC_MISC_LOCALBIAS2X_MSB                23
+#define TXPC_MISC_LOCALBIAS2X_LSB                23
+#define TXPC_MISC_LOCALBIAS2X_MASK               0x00800000
+#define TXPC_MISC_LOCALBIAS2X_GET(x)             (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
+#define TXPC_MISC_LOCALBIAS2X_SET(x)             (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
+#define TXPC_MISC_SELTSP_MSB                     22
+#define TXPC_MISC_SELTSP_LSB                     22
+#define TXPC_MISC_SELTSP_MASK                    0x00400000
+#define TXPC_MISC_SELTSP_GET(x)                  (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
+#define TXPC_MISC_SELTSP_SET(x)                  (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
+#define TXPC_MISC_SELTSN_MSB                     21
+#define TXPC_MISC_SELTSN_LSB                     21
+#define TXPC_MISC_SELTSN_MASK                    0x00200000
+#define TXPC_MISC_SELTSN_GET(x)                  (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
+#define TXPC_MISC_SELTSN_SET(x)                  (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
+#define TXPC_MISC_SPARE_A_MSB                    20
+#define TXPC_MISC_SPARE_A_LSB                    18
+#define TXPC_MISC_SPARE_A_MASK                   0x001c0000
+#define TXPC_MISC_SPARE_A_GET(x)                 (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
+#define TXPC_MISC_SPARE_A_SET(x)                 (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
+#define TXPC_MISC_DECOUT_MSB                     17
+#define TXPC_MISC_DECOUT_LSB                     8
+#define TXPC_MISC_DECOUT_MASK                    0x0003ff00
+#define TXPC_MISC_DECOUT_GET(x)                  (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
+#define TXPC_MISC_DECOUT_SET(x)                  (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
+#define TXPC_MISC_XTALDIV_MSB                    7
+#define TXPC_MISC_XTALDIV_LSB                    6
+#define TXPC_MISC_XTALDIV_MASK                   0x000000c0
+#define TXPC_MISC_XTALDIV_GET(x)                 (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
+#define TXPC_MISC_XTALDIV_SET(x)                 (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
+#define TXPC_MISC_SPARE_MSB                      5
+#define TXPC_MISC_SPARE_LSB                      0
+#define TXPC_MISC_SPARE_MASK                     0x0000003f
+#define TXPC_MISC_SPARE_GET(x)                   (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
+#define TXPC_MISC_SPARE_SET(x)                   (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
+
+#define RXTXBB_RXTXBB1_ADDRESS                   0x00000050
+#define RXTXBB_RXTXBB1_OFFSET                    0x00000050
+#define RXTXBB_RXTXBB1_SPARE_MSB                 31
+#define RXTXBB_RXTXBB1_SPARE_LSB                 19
+#define RXTXBB_RXTXBB1_SPARE_MASK                0xfff80000
+#define RXTXBB_RXTXBB1_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
+#define RXTXBB_RXTXBB1_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
+#define RXTXBB_RXTXBB1_FNOTCH_MSB                18
+#define RXTXBB_RXTXBB1_FNOTCH_LSB                17
+#define RXTXBB_RXTXBB1_FNOTCH_MASK               0x00060000
+#define RXTXBB_RXTXBB1_FNOTCH_GET(x)             (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
+#define RXTXBB_RXTXBB1_FNOTCH_SET(x)             (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
+#define RXTXBB_RXTXBB1_SEL_ATB_MSB               16
+#define RXTXBB_RXTXBB1_SEL_ATB_LSB               9
+#define RXTXBB_RXTXBB1_SEL_ATB_MASK              0x0001fe00
+#define RXTXBB_RXTXBB1_SEL_ATB_GET(x)            (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
+#define RXTXBB_RXTXBB1_SEL_ATB_SET(x)            (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB        8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK       0x00000100
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x)     (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x)     (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
+#define RXTXBB_RXTXBB1_PDV2I_MSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_LSB                 7
+#define RXTXBB_RXTXBB1_PDV2I_MASK                0x00000080
+#define RXTXBB_RXTXBB1_PDV2I_GET(x)              (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
+#define RXTXBB_RXTXBB1_PDV2I_SET(x)              (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
+#define RXTXBB_RXTXBB1_PDI2V_MSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_LSB                 6
+#define RXTXBB_RXTXBB1_PDI2V_MASK                0x00000040
+#define RXTXBB_RXTXBB1_PDI2V_GET(x)              (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
+#define RXTXBB_RXTXBB1_PDI2V_SET(x)              (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
+#define RXTXBB_RXTXBB1_PDRXTXBB_MSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_LSB              5
+#define RXTXBB_RXTXBB1_PDRXTXBB_MASK             0x00000020
+#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x)           (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
+#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x)           (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB           4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK          0x00000010
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB           3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK          0x00000008
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB           2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK          0x00000004
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x)        (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x)        (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
+#define RXTXBB_RXTXBB1_PDLOQ_MSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_LSB                 1
+#define RXTXBB_RXTXBB1_PDLOQ_MASK                0x00000002
+#define RXTXBB_RXTXBB1_PDLOQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDLOQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDHIQ_MSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_LSB                 0
+#define RXTXBB_RXTXBB1_PDHIQ_MASK                0x00000001
+#define RXTXBB_RXTXBB1_PDHIQ_GET(x)              (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDHIQ_SET(x)              (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
+
+#define RXTXBB_RXTXBB2_ADDRESS                   0x00000054
+#define RXTXBB_RXTXBB2_OFFSET                    0x00000054
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB    31
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB    29
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK   0xe0000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB    28
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB    26
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK   0x1c000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB   25
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB   23
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK  0x03800000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
+#define RXTXBB_RXTXBB2_SPARE_MSB                 22
+#define RXTXBB_RXTXBB2_SPARE_LSB                 21
+#define RXTXBB_RXTXBB2_SPARE_MASK                0x00600000
+#define RXTXBB_RXTXBB2_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
+#define RXTXBB_RXTXBB2_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB           20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK          0x00100000
+#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x)        (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x)        (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SELBUFFER_MSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_LSB             19
+#define RXTXBB_RXTXBB2_SELBUFFER_MASK            0x00080000
+#define RXTXBB_RXTXBB2_SELBUFFER_GET(x)          (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SELBUFFER_SET(x)          (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB          18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK         0x00040000
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB          17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK         0x00020000
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB          16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK         0x00010000
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB          15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK         0x00008000
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x)       (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x)       (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
+#define RXTXBB_RXTXBB2_CMSEL_MSB                 14
+#define RXTXBB_RXTXBB2_CMSEL_LSB                 13
+#define RXTXBB_RXTXBB2_CMSEL_MASK                0x00006000
+#define RXTXBB_RXTXBB2_CMSEL_GET(x)              (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
+#define RXTXBB_RXTXBB2_CMSEL_SET(x)              (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
+#define RXTXBB_RXTXBB2_FILTERFC_MSB              12
+#define RXTXBB_RXTXBB2_FILTERFC_LSB              8
+#define RXTXBB_RXTXBB2_FILTERFC_MASK             0x00001f00
+#define RXTXBB_RXTXBB2_FILTERFC_GET(x)           (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
+#define RXTXBB_RXTXBB2_FILTERFC_SET(x)           (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB     7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK    0x00000080
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x)  (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x)  (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB        6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK       0x00000040
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x)     (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x)     (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB           5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK          0x00000020
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB           4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK          0x00000010
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB           3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK          0x00000008
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB           2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK          0x00000004
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB           1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK          0x00000002
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x)        (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x)        (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB         0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK        0x00000001
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x)      (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x)      (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
+
+#define RXTXBB_RXTXBB3_ADDRESS                   0x00000058
+#define RXTXBB_RXTXBB3_OFFSET                    0x00000058
+#define RXTXBB_RXTXBB3_SPARE_MSB                 31
+#define RXTXBB_RXTXBB3_SPARE_LSB                 27
+#define RXTXBB_RXTXBB3_SPARE_MASK                0xf8000000
+#define RXTXBB_RXTXBB3_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
+#define RXTXBB_RXTXBB3_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB    23
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB    21
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK   0x00e00000
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB      20
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB      18
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK     0x001c0000
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB      17
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB      15
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK     0x00038000
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB      14
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB      12
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK     0x00007000
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB      11
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB      9
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK     0x00000e00
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB      8
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB      6
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK     0x000001c0
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x)   (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x)   (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB     5
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB     3
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK    0x00000038
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x)  (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x)  (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB    2
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB    0
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK   0x00000007
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
+
+#define RXTXBB_RXTXBB4_ADDRESS                   0x0000005c
+#define RXTXBB_RXTXBB4_OFFSET                    0x0000005c
+#define RXTXBB_RXTXBB4_SPARE_MSB                 31
+#define RXTXBB_RXTXBB4_SPARE_LSB                 31
+#define RXTXBB_RXTXBB4_SPARE_MASK                0x80000000
+#define RXTXBB_RXTXBB4_SPARE_GET(x)              (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
+#define RXTXBB_RXTXBB4_SPARE_SET(x)              (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB           30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK          0x40000000
+#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x)        (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x)        (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB           29
+#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB           25
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK          0x3e000000
+#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB           24
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB           20
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK          0x01f00000
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB           19
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB           15
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK          0x000f8000
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB           14
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB           10
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK          0x00007c00
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x)        (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x)        (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB          9
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB          5
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK         0x000003e0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB          4
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB          0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK         0x0000001f
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x)       (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x)       (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
+
+#define ADDAC_ADDAC1_ADDRESS                     0x00000060
+#define ADDAC_ADDAC1_OFFSET                      0x00000060
+#define ADDAC_ADDAC1_PLL_SVREG_MSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_LSB               31
+#define ADDAC_ADDAC1_PLL_SVREG_MASK              0x80000000
+#define ADDAC_ADDAC1_PLL_SVREG_GET(x)            (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
+#define ADDAC_ADDAC1_PLL_SVREG_SET(x)            (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
+#define ADDAC_ADDAC1_PLL_SCLAMP_MSB              30
+#define ADDAC_ADDAC1_PLL_SCLAMP_LSB              28
+#define ADDAC_ADDAC1_PLL_SCLAMP_MASK             0x70000000
+#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x)           (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
+#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x)           (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
+#define ADDAC_ADDAC1_PLL_ATB_MSB                 27
+#define ADDAC_ADDAC1_PLL_ATB_LSB                 26
+#define ADDAC_ADDAC1_PLL_ATB_MASK                0x0c000000
+#define ADDAC_ADDAC1_PLL_ATB_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
+#define ADDAC_ADDAC1_PLL_ATB_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
+#define ADDAC_ADDAC1_PLL_ICP_MSB                 25
+#define ADDAC_ADDAC1_PLL_ICP_LSB                 23
+#define ADDAC_ADDAC1_PLL_ICP_MASK                0x03800000
+#define ADDAC_ADDAC1_PLL_ICP_GET(x)              (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
+#define ADDAC_ADDAC1_PLL_ICP_SET(x)              (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
+#define ADDAC_ADDAC1_PLL_FILTER_MSB              22
+#define ADDAC_ADDAC1_PLL_FILTER_LSB              15
+#define ADDAC_ADDAC1_PLL_FILTER_MASK             0x007f8000
+#define ADDAC_ADDAC1_PLL_FILTER_GET(x)           (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
+#define ADDAC_ADDAC1_PLL_FILTER_SET(x)           (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
+#define ADDAC_ADDAC1_PWDPLL_MSB                  14
+#define ADDAC_ADDAC1_PWDPLL_LSB                  14
+#define ADDAC_ADDAC1_PWDPLL_MASK                 0x00004000
+#define ADDAC_ADDAC1_PWDPLL_GET(x)               (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
+#define ADDAC_ADDAC1_PWDPLL_SET(x)               (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
+#define ADDAC_ADDAC1_PWDADC_MSB                  13
+#define ADDAC_ADDAC1_PWDADC_LSB                  13
+#define ADDAC_ADDAC1_PWDADC_MASK                 0x00002000
+#define ADDAC_ADDAC1_PWDADC_GET(x)               (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
+#define ADDAC_ADDAC1_PWDADC_SET(x)               (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
+#define ADDAC_ADDAC1_PWDDAC_MSB                  12
+#define ADDAC_ADDAC1_PWDDAC_LSB                  12
+#define ADDAC_ADDAC1_PWDDAC_MASK                 0x00001000
+#define ADDAC_ADDAC1_PWDDAC_GET(x)               (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
+#define ADDAC_ADDAC1_PWDDAC_SET(x)               (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
+#define ADDAC_ADDAC1_FORCEMSBLOW_MSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_LSB             11
+#define ADDAC_ADDAC1_FORCEMSBLOW_MASK            0x00000800
+#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x)          (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
+#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x)          (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
+#define ADDAC_ADDAC1_SELMANPWDS_MSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_LSB              10
+#define ADDAC_ADDAC1_SELMANPWDS_MASK             0x00000400
+#define ADDAC_ADDAC1_SELMANPWDS_GET(x)           (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
+#define ADDAC_ADDAC1_SELMANPWDS_SET(x)           (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB          9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK         0x00000200
+#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x)       (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x)       (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
+#define ADDAC_ADDAC1_CM_SEL_MSB                  8
+#define ADDAC_ADDAC1_CM_SEL_LSB                  7
+#define ADDAC_ADDAC1_CM_SEL_MASK                 0x00000180
+#define ADDAC_ADDAC1_CM_SEL_GET(x)               (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
+#define ADDAC_ADDAC1_CM_SEL_SET(x)               (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB         6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK        0x00000040
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x)      (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x)      (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
+#define ADDAC_ADDAC1_SPARE_MSB                   5
+#define ADDAC_ADDAC1_SPARE_LSB                   0
+#define ADDAC_ADDAC1_SPARE_MASK                  0x0000003f
+#define ADDAC_ADDAC1_SPARE_GET(x)                (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
+#define ADDAC_ADDAC1_SPARE_SET(x)                (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_reg_reg_s {
+  volatile unsigned int synth_synth1;
+  volatile unsigned int synth_synth2;
+  volatile unsigned int synth_synth3;
+  volatile unsigned int synth_synth4;
+  volatile unsigned int synth_synth5;
+  volatile unsigned int synth_synth6;
+  volatile unsigned int synth_synth7;
+  volatile unsigned int synth_synth8;
+  volatile unsigned int rf5g_rf5g1;
+  volatile unsigned int rf5g_rf5g2;
+  volatile unsigned int rf2g_rf2g1;
+  volatile unsigned int rf2g_rf2g2;
+  volatile unsigned int top_gain;
+  volatile unsigned int top_top;
+  volatile unsigned int bias_bias_sel;
+  volatile unsigned int bias_bias1;
+  volatile unsigned int bias_bias2;
+  volatile unsigned int bias_bias3;
+  volatile unsigned int txpc_txpc;
+  volatile unsigned int txpc_misc;
+  volatile unsigned int rxtxbb_rxtxbb1;
+  volatile unsigned int rxtxbb_rxtxbb2;
+  volatile unsigned int rxtxbb_rxtxbb3;
+  volatile unsigned int rxtxbb_rxtxbb4;
+  volatile unsigned int addac_addac1;
+} analog_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h
new file mode 100644
index 000000000000..bba885ed1f08
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h
@@ -0,0 +1,32 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_MAP_H_
+#define _APB_MAP_H_
+
+#define RTC_BASE_ADDRESS                         0x00004000
+#define VMC_BASE_ADDRESS                         0x00008000
+#define UART_BASE_ADDRESS                        0x0000c000
+#define SI_BASE_ADDRESS                          0x00010000
+#define GPIO_BASE_ADDRESS                        0x00014000
+#define MBOX_BASE_ADDRESS                        0x00018000
+#define ANALOG_INTF_BASE_ADDRESS                 0x0001c000
+#define MAC_BASE_ADDRESS                         0x00020000
+
+#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h
new file mode 100644
index 000000000000..de88e8cc91bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h
@@ -0,0 +1,996 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_OUT_ADDRESS                         0x00000000
+#define GPIO_OUT_OFFSET                          0x00000000
+#define GPIO_OUT_DATA_MSB                        17
+#define GPIO_OUT_DATA_LSB                        0
+#define GPIO_OUT_DATA_MASK                       0x0003ffff
+#define GPIO_OUT_DATA_GET(x)                     (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
+#define GPIO_OUT_DATA_SET(x)                     (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
+
+#define GPIO_OUT_W1TS_ADDRESS                    0x00000004
+#define GPIO_OUT_W1TS_OFFSET                     0x00000004
+#define GPIO_OUT_W1TS_DATA_MSB                   17
+#define GPIO_OUT_W1TS_DATA_LSB                   0
+#define GPIO_OUT_W1TS_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TS_DATA_GET(x)                (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
+#define GPIO_OUT_W1TS_DATA_SET(x)                (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
+
+#define GPIO_OUT_W1TC_ADDRESS                    0x00000008
+#define GPIO_OUT_W1TC_OFFSET                     0x00000008
+#define GPIO_OUT_W1TC_DATA_MSB                   17
+#define GPIO_OUT_W1TC_DATA_LSB                   0
+#define GPIO_OUT_W1TC_DATA_MASK                  0x0003ffff
+#define GPIO_OUT_W1TC_DATA_GET(x)                (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
+#define GPIO_OUT_W1TC_DATA_SET(x)                (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
+
+#define GPIO_ENABLE_ADDRESS                      0x0000000c
+#define GPIO_ENABLE_OFFSET                       0x0000000c
+#define GPIO_ENABLE_DATA_MSB                     17
+#define GPIO_ENABLE_DATA_LSB                     0
+#define GPIO_ENABLE_DATA_MASK                    0x0003ffff
+#define GPIO_ENABLE_DATA_GET(x)                  (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
+#define GPIO_ENABLE_DATA_SET(x)                  (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
+
+#define GPIO_ENABLE_W1TS_ADDRESS                 0x00000010
+#define GPIO_ENABLE_W1TS_OFFSET                  0x00000010
+#define GPIO_ENABLE_W1TS_DATA_MSB                17
+#define GPIO_ENABLE_W1TS_DATA_LSB                0
+#define GPIO_ENABLE_W1TS_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TS_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
+#define GPIO_ENABLE_W1TS_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define GPIO_ENABLE_W1TC_ADDRESS                 0x00000014
+#define GPIO_ENABLE_W1TC_OFFSET                  0x00000014
+#define GPIO_ENABLE_W1TC_DATA_MSB                17
+#define GPIO_ENABLE_W1TC_DATA_LSB                0
+#define GPIO_ENABLE_W1TC_DATA_MASK               0x0003ffff
+#define GPIO_ENABLE_W1TC_DATA_GET(x)             (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
+#define GPIO_ENABLE_W1TC_DATA_SET(x)             (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define GPIO_IN_ADDRESS                          0x00000018
+#define GPIO_IN_OFFSET                           0x00000018
+#define GPIO_IN_DATA_MSB                         17
+#define GPIO_IN_DATA_LSB                         0
+#define GPIO_IN_DATA_MASK                        0x0003ffff
+#define GPIO_IN_DATA_GET(x)                      (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
+#define GPIO_IN_DATA_SET(x)                      (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
+
+#define GPIO_STATUS_ADDRESS                      0x0000001c
+#define GPIO_STATUS_OFFSET                       0x0000001c
+#define GPIO_STATUS_INTERRUPT_MSB                17
+#define GPIO_STATUS_INTERRUPT_LSB                0
+#define GPIO_STATUS_INTERRUPT_MASK               0x0003ffff
+#define GPIO_STATUS_INTERRUPT_GET(x)             (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
+#define GPIO_STATUS_INTERRUPT_SET(x)             (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TS_ADDRESS                 0x00000020
+#define GPIO_STATUS_W1TS_OFFSET                  0x00000020
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TC_ADDRESS                 0x00000024
+#define GPIO_STATUS_W1TC_OFFSET                  0x00000024
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB           17
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB           0
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK          0x0003ffff
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x)        (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x)        (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define GPIO_PIN0_ADDRESS                        0x00000028
+#define GPIO_PIN0_OFFSET                         0x00000028
+#define GPIO_PIN0_CONFIG_MSB                     12
+#define GPIO_PIN0_CONFIG_LSB                     11
+#define GPIO_PIN0_CONFIG_MASK                    0x00001800
+#define GPIO_PIN0_CONFIG_GET(x)                  (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_CONFIG_SET(x)                  (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN0_INT_TYPE_MSB                   9
+#define GPIO_PIN0_INT_TYPE_LSB                   7
+#define GPIO_PIN0_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN0_INT_TYPE_GET(x)                (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
+#define GPIO_PIN0_INT_TYPE_SET(x)                (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
+#define GPIO_PIN0_PAD_DRIVER_MSB                 2
+#define GPIO_PIN0_PAD_DRIVER_LSB                 2
+#define GPIO_PIN0_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN0_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
+#define GPIO_PIN0_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
+#define GPIO_PIN0_SOURCE_MSB                     0
+#define GPIO_PIN0_SOURCE_LSB                     0
+#define GPIO_PIN0_SOURCE_MASK                    0x00000001
+#define GPIO_PIN0_SOURCE_GET(x)                  (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
+#define GPIO_PIN0_SOURCE_SET(x)                  (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
+
+#define GPIO_PIN1_ADDRESS                        0x0000002c
+#define GPIO_PIN1_OFFSET                         0x0000002c
+#define GPIO_PIN1_CONFIG_MSB                     12
+#define GPIO_PIN1_CONFIG_LSB                     11
+#define GPIO_PIN1_CONFIG_MASK                    0x00001800
+#define GPIO_PIN1_CONFIG_GET(x)                  (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
+#define GPIO_PIN1_CONFIG_SET(x)                  (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN1_INT_TYPE_MSB                   9
+#define GPIO_PIN1_INT_TYPE_LSB                   7
+#define GPIO_PIN1_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN1_INT_TYPE_GET(x)                (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
+#define GPIO_PIN1_INT_TYPE_SET(x)                (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
+#define GPIO_PIN1_PAD_DRIVER_MSB                 2
+#define GPIO_PIN1_PAD_DRIVER_LSB                 2
+#define GPIO_PIN1_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN1_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
+#define GPIO_PIN1_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
+#define GPIO_PIN1_SOURCE_MSB                     0
+#define GPIO_PIN1_SOURCE_LSB                     0
+#define GPIO_PIN1_SOURCE_MASK                    0x00000001
+#define GPIO_PIN1_SOURCE_GET(x)                  (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
+#define GPIO_PIN1_SOURCE_SET(x)                  (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
+
+#define GPIO_PIN2_ADDRESS                        0x00000030
+#define GPIO_PIN2_OFFSET                         0x00000030
+#define GPIO_PIN2_CONFIG_MSB                     12
+#define GPIO_PIN2_CONFIG_LSB                     11
+#define GPIO_PIN2_CONFIG_MASK                    0x00001800
+#define GPIO_PIN2_CONFIG_GET(x)                  (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
+#define GPIO_PIN2_CONFIG_SET(x)                  (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN2_INT_TYPE_MSB                   9
+#define GPIO_PIN2_INT_TYPE_LSB                   7
+#define GPIO_PIN2_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN2_INT_TYPE_GET(x)                (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
+#define GPIO_PIN2_INT_TYPE_SET(x)                (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
+#define GPIO_PIN2_PAD_DRIVER_MSB                 2
+#define GPIO_PIN2_PAD_DRIVER_LSB                 2
+#define GPIO_PIN2_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN2_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
+#define GPIO_PIN2_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
+#define GPIO_PIN2_SOURCE_MSB                     0
+#define GPIO_PIN2_SOURCE_LSB                     0
+#define GPIO_PIN2_SOURCE_MASK                    0x00000001
+#define GPIO_PIN2_SOURCE_GET(x)                  (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
+#define GPIO_PIN2_SOURCE_SET(x)                  (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
+
+#define GPIO_PIN3_ADDRESS                        0x00000034
+#define GPIO_PIN3_OFFSET                         0x00000034
+#define GPIO_PIN3_CONFIG_MSB                     12
+#define GPIO_PIN3_CONFIG_LSB                     11
+#define GPIO_PIN3_CONFIG_MASK                    0x00001800
+#define GPIO_PIN3_CONFIG_GET(x)                  (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
+#define GPIO_PIN3_CONFIG_SET(x)                  (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN3_INT_TYPE_MSB                   9
+#define GPIO_PIN3_INT_TYPE_LSB                   7
+#define GPIO_PIN3_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN3_INT_TYPE_GET(x)                (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
+#define GPIO_PIN3_INT_TYPE_SET(x)                (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
+#define GPIO_PIN3_PAD_DRIVER_MSB                 2
+#define GPIO_PIN3_PAD_DRIVER_LSB                 2
+#define GPIO_PIN3_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN3_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
+#define GPIO_PIN3_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
+#define GPIO_PIN3_SOURCE_MSB                     0
+#define GPIO_PIN3_SOURCE_LSB                     0
+#define GPIO_PIN3_SOURCE_MASK                    0x00000001
+#define GPIO_PIN3_SOURCE_GET(x)                  (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
+#define GPIO_PIN3_SOURCE_SET(x)                  (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
+
+#define GPIO_PIN4_ADDRESS                        0x00000038
+#define GPIO_PIN4_OFFSET                         0x00000038
+#define GPIO_PIN4_CONFIG_MSB                     12
+#define GPIO_PIN4_CONFIG_LSB                     11
+#define GPIO_PIN4_CONFIG_MASK                    0x00001800
+#define GPIO_PIN4_CONFIG_GET(x)                  (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
+#define GPIO_PIN4_CONFIG_SET(x)                  (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN4_INT_TYPE_MSB                   9
+#define GPIO_PIN4_INT_TYPE_LSB                   7
+#define GPIO_PIN4_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN4_INT_TYPE_GET(x)                (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
+#define GPIO_PIN4_INT_TYPE_SET(x)                (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
+#define GPIO_PIN4_PAD_DRIVER_MSB                 2
+#define GPIO_PIN4_PAD_DRIVER_LSB                 2
+#define GPIO_PIN4_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN4_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
+#define GPIO_PIN4_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
+#define GPIO_PIN4_SOURCE_MSB                     0
+#define GPIO_PIN4_SOURCE_LSB                     0
+#define GPIO_PIN4_SOURCE_MASK                    0x00000001
+#define GPIO_PIN4_SOURCE_GET(x)                  (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
+#define GPIO_PIN4_SOURCE_SET(x)                  (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
+
+#define GPIO_PIN5_ADDRESS                        0x0000003c
+#define GPIO_PIN5_OFFSET                         0x0000003c
+#define GPIO_PIN5_CONFIG_MSB                     12
+#define GPIO_PIN5_CONFIG_LSB                     11
+#define GPIO_PIN5_CONFIG_MASK                    0x00001800
+#define GPIO_PIN5_CONFIG_GET(x)                  (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
+#define GPIO_PIN5_CONFIG_SET(x)                  (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN5_INT_TYPE_MSB                   9
+#define GPIO_PIN5_INT_TYPE_LSB                   7
+#define GPIO_PIN5_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN5_INT_TYPE_GET(x)                (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
+#define GPIO_PIN5_INT_TYPE_SET(x)                (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
+#define GPIO_PIN5_PAD_DRIVER_MSB                 2
+#define GPIO_PIN5_PAD_DRIVER_LSB                 2
+#define GPIO_PIN5_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN5_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
+#define GPIO_PIN5_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
+#define GPIO_PIN5_SOURCE_MSB                     0
+#define GPIO_PIN5_SOURCE_LSB                     0
+#define GPIO_PIN5_SOURCE_MASK                    0x00000001
+#define GPIO_PIN5_SOURCE_GET(x)                  (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
+#define GPIO_PIN5_SOURCE_SET(x)                  (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
+
+#define GPIO_PIN6_ADDRESS                        0x00000040
+#define GPIO_PIN6_OFFSET                         0x00000040
+#define GPIO_PIN6_CONFIG_MSB                     12
+#define GPIO_PIN6_CONFIG_LSB                     11
+#define GPIO_PIN6_CONFIG_MASK                    0x00001800
+#define GPIO_PIN6_CONFIG_GET(x)                  (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
+#define GPIO_PIN6_CONFIG_SET(x)                  (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN6_INT_TYPE_MSB                   9
+#define GPIO_PIN6_INT_TYPE_LSB                   7
+#define GPIO_PIN6_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN6_INT_TYPE_GET(x)                (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
+#define GPIO_PIN6_INT_TYPE_SET(x)                (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
+#define GPIO_PIN6_PAD_DRIVER_MSB                 2
+#define GPIO_PIN6_PAD_DRIVER_LSB                 2
+#define GPIO_PIN6_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN6_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
+#define GPIO_PIN6_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
+#define GPIO_PIN6_SOURCE_MSB                     0
+#define GPIO_PIN6_SOURCE_LSB                     0
+#define GPIO_PIN6_SOURCE_MASK                    0x00000001
+#define GPIO_PIN6_SOURCE_GET(x)                  (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
+#define GPIO_PIN6_SOURCE_SET(x)                  (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
+
+#define GPIO_PIN7_ADDRESS                        0x00000044
+#define GPIO_PIN7_OFFSET                         0x00000044
+#define GPIO_PIN7_CONFIG_MSB                     12
+#define GPIO_PIN7_CONFIG_LSB                     11
+#define GPIO_PIN7_CONFIG_MASK                    0x00001800
+#define GPIO_PIN7_CONFIG_GET(x)                  (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
+#define GPIO_PIN7_CONFIG_SET(x)                  (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN7_INT_TYPE_MSB                   9
+#define GPIO_PIN7_INT_TYPE_LSB                   7
+#define GPIO_PIN7_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN7_INT_TYPE_GET(x)                (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
+#define GPIO_PIN7_INT_TYPE_SET(x)                (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
+#define GPIO_PIN7_PAD_DRIVER_MSB                 2
+#define GPIO_PIN7_PAD_DRIVER_LSB                 2
+#define GPIO_PIN7_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN7_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
+#define GPIO_PIN7_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
+#define GPIO_PIN7_SOURCE_MSB                     0
+#define GPIO_PIN7_SOURCE_LSB                     0
+#define GPIO_PIN7_SOURCE_MASK                    0x00000001
+#define GPIO_PIN7_SOURCE_GET(x)                  (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
+#define GPIO_PIN7_SOURCE_SET(x)                  (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
+
+#define GPIO_PIN8_ADDRESS                        0x00000048
+#define GPIO_PIN8_OFFSET                         0x00000048
+#define GPIO_PIN8_CONFIG_MSB                     12
+#define GPIO_PIN8_CONFIG_LSB                     11
+#define GPIO_PIN8_CONFIG_MASK                    0x00001800
+#define GPIO_PIN8_CONFIG_GET(x)                  (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
+#define GPIO_PIN8_CONFIG_SET(x)                  (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN8_INT_TYPE_MSB                   9
+#define GPIO_PIN8_INT_TYPE_LSB                   7
+#define GPIO_PIN8_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN8_INT_TYPE_GET(x)                (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
+#define GPIO_PIN8_INT_TYPE_SET(x)                (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
+#define GPIO_PIN8_PAD_DRIVER_MSB                 2
+#define GPIO_PIN8_PAD_DRIVER_LSB                 2
+#define GPIO_PIN8_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN8_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
+#define GPIO_PIN8_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
+#define GPIO_PIN8_SOURCE_MSB                     0
+#define GPIO_PIN8_SOURCE_LSB                     0
+#define GPIO_PIN8_SOURCE_MASK                    0x00000001
+#define GPIO_PIN8_SOURCE_GET(x)                  (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
+#define GPIO_PIN8_SOURCE_SET(x)                  (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
+
+#define GPIO_PIN9_ADDRESS                        0x0000004c
+#define GPIO_PIN9_OFFSET                         0x0000004c
+#define GPIO_PIN9_CONFIG_MSB                     12
+#define GPIO_PIN9_CONFIG_LSB                     11
+#define GPIO_PIN9_CONFIG_MASK                    0x00001800
+#define GPIO_PIN9_CONFIG_GET(x)                  (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
+#define GPIO_PIN9_CONFIG_SET(x)                  (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK             0x00000400
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x)           (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN9_INT_TYPE_MSB                   9
+#define GPIO_PIN9_INT_TYPE_LSB                   7
+#define GPIO_PIN9_INT_TYPE_MASK                  0x00000380
+#define GPIO_PIN9_INT_TYPE_GET(x)                (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
+#define GPIO_PIN9_INT_TYPE_SET(x)                (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
+#define GPIO_PIN9_PAD_DRIVER_MSB                 2
+#define GPIO_PIN9_PAD_DRIVER_LSB                 2
+#define GPIO_PIN9_PAD_DRIVER_MASK                0x00000004
+#define GPIO_PIN9_PAD_DRIVER_GET(x)              (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
+#define GPIO_PIN9_PAD_DRIVER_SET(x)              (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
+#define GPIO_PIN9_SOURCE_MSB                     0
+#define GPIO_PIN9_SOURCE_LSB                     0
+#define GPIO_PIN9_SOURCE_MASK                    0x00000001
+#define GPIO_PIN9_SOURCE_GET(x)                  (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
+#define GPIO_PIN9_SOURCE_SET(x)                  (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
+
+#define GPIO_PIN10_ADDRESS                       0x00000050
+#define GPIO_PIN10_OFFSET                        0x00000050
+#define GPIO_PIN10_CONFIG_MSB                    12
+#define GPIO_PIN10_CONFIG_LSB                    11
+#define GPIO_PIN10_CONFIG_MASK                   0x00001800
+#define GPIO_PIN10_CONFIG_GET(x)                 (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
+#define GPIO_PIN10_CONFIG_SET(x)                 (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN10_INT_TYPE_MSB                  9
+#define GPIO_PIN10_INT_TYPE_LSB                  7
+#define GPIO_PIN10_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN10_INT_TYPE_GET(x)               (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
+#define GPIO_PIN10_INT_TYPE_SET(x)               (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
+#define GPIO_PIN10_PAD_DRIVER_MSB                2
+#define GPIO_PIN10_PAD_DRIVER_LSB                2
+#define GPIO_PIN10_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN10_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
+#define GPIO_PIN10_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
+#define GPIO_PIN10_SOURCE_MSB                    0
+#define GPIO_PIN10_SOURCE_LSB                    0
+#define GPIO_PIN10_SOURCE_MASK                   0x00000001
+#define GPIO_PIN10_SOURCE_GET(x)                 (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
+#define GPIO_PIN10_SOURCE_SET(x)                 (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
+
+#define GPIO_PIN11_ADDRESS                       0x00000054
+#define GPIO_PIN11_OFFSET                        0x00000054
+#define GPIO_PIN11_CONFIG_MSB                    12
+#define GPIO_PIN11_CONFIG_LSB                    11
+#define GPIO_PIN11_CONFIG_MASK                   0x00001800
+#define GPIO_PIN11_CONFIG_GET(x)                 (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
+#define GPIO_PIN11_CONFIG_SET(x)                 (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN11_INT_TYPE_MSB                  9
+#define GPIO_PIN11_INT_TYPE_LSB                  7
+#define GPIO_PIN11_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN11_INT_TYPE_GET(x)               (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
+#define GPIO_PIN11_INT_TYPE_SET(x)               (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
+#define GPIO_PIN11_PAD_DRIVER_MSB                2
+#define GPIO_PIN11_PAD_DRIVER_LSB                2
+#define GPIO_PIN11_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN11_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
+#define GPIO_PIN11_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
+#define GPIO_PIN11_SOURCE_MSB                    0
+#define GPIO_PIN11_SOURCE_LSB                    0
+#define GPIO_PIN11_SOURCE_MASK                   0x00000001
+#define GPIO_PIN11_SOURCE_GET(x)                 (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
+#define GPIO_PIN11_SOURCE_SET(x)                 (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
+
+#define GPIO_PIN12_ADDRESS                       0x00000058
+#define GPIO_PIN12_OFFSET                        0x00000058
+#define GPIO_PIN12_CONFIG_MSB                    12
+#define GPIO_PIN12_CONFIG_LSB                    11
+#define GPIO_PIN12_CONFIG_MASK                   0x00001800
+#define GPIO_PIN12_CONFIG_GET(x)                 (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
+#define GPIO_PIN12_CONFIG_SET(x)                 (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN12_INT_TYPE_MSB                  9
+#define GPIO_PIN12_INT_TYPE_LSB                  7
+#define GPIO_PIN12_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN12_INT_TYPE_GET(x)               (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
+#define GPIO_PIN12_INT_TYPE_SET(x)               (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
+#define GPIO_PIN12_PAD_DRIVER_MSB                2
+#define GPIO_PIN12_PAD_DRIVER_LSB                2
+#define GPIO_PIN12_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN12_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
+#define GPIO_PIN12_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
+#define GPIO_PIN12_SOURCE_MSB                    0
+#define GPIO_PIN12_SOURCE_LSB                    0
+#define GPIO_PIN12_SOURCE_MASK                   0x00000001
+#define GPIO_PIN12_SOURCE_GET(x)                 (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
+#define GPIO_PIN12_SOURCE_SET(x)                 (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
+
+#define GPIO_PIN13_ADDRESS                       0x0000005c
+#define GPIO_PIN13_OFFSET                        0x0000005c
+#define GPIO_PIN13_CONFIG_MSB                    12
+#define GPIO_PIN13_CONFIG_LSB                    11
+#define GPIO_PIN13_CONFIG_MASK                   0x00001800
+#define GPIO_PIN13_CONFIG_GET(x)                 (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
+#define GPIO_PIN13_CONFIG_SET(x)                 (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN13_INT_TYPE_MSB                  9
+#define GPIO_PIN13_INT_TYPE_LSB                  7
+#define GPIO_PIN13_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN13_INT_TYPE_GET(x)               (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
+#define GPIO_PIN13_INT_TYPE_SET(x)               (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
+#define GPIO_PIN13_PAD_DRIVER_MSB                2
+#define GPIO_PIN13_PAD_DRIVER_LSB                2
+#define GPIO_PIN13_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN13_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
+#define GPIO_PIN13_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
+#define GPIO_PIN13_SOURCE_MSB                    0
+#define GPIO_PIN13_SOURCE_LSB                    0
+#define GPIO_PIN13_SOURCE_MASK                   0x00000001
+#define GPIO_PIN13_SOURCE_GET(x)                 (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
+#define GPIO_PIN13_SOURCE_SET(x)                 (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
+
+#define GPIO_PIN14_ADDRESS                       0x00000060
+#define GPIO_PIN14_OFFSET                        0x00000060
+#define GPIO_PIN14_CONFIG_MSB                    12
+#define GPIO_PIN14_CONFIG_LSB                    11
+#define GPIO_PIN14_CONFIG_MASK                   0x00001800
+#define GPIO_PIN14_CONFIG_GET(x)                 (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
+#define GPIO_PIN14_CONFIG_SET(x)                 (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN14_INT_TYPE_MSB                  9
+#define GPIO_PIN14_INT_TYPE_LSB                  7
+#define GPIO_PIN14_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN14_INT_TYPE_GET(x)               (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
+#define GPIO_PIN14_INT_TYPE_SET(x)               (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
+#define GPIO_PIN14_PAD_DRIVER_MSB                2
+#define GPIO_PIN14_PAD_DRIVER_LSB                2
+#define GPIO_PIN14_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN14_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
+#define GPIO_PIN14_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
+#define GPIO_PIN14_SOURCE_MSB                    0
+#define GPIO_PIN14_SOURCE_LSB                    0
+#define GPIO_PIN14_SOURCE_MASK                   0x00000001
+#define GPIO_PIN14_SOURCE_GET(x)                 (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
+#define GPIO_PIN14_SOURCE_SET(x)                 (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
+
+#define GPIO_PIN15_ADDRESS                       0x00000064
+#define GPIO_PIN15_OFFSET                        0x00000064
+#define GPIO_PIN15_CONFIG_MSB                    12
+#define GPIO_PIN15_CONFIG_LSB                    11
+#define GPIO_PIN15_CONFIG_MASK                   0x00001800
+#define GPIO_PIN15_CONFIG_GET(x)                 (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
+#define GPIO_PIN15_CONFIG_SET(x)                 (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN15_INT_TYPE_MSB                  9
+#define GPIO_PIN15_INT_TYPE_LSB                  7
+#define GPIO_PIN15_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN15_INT_TYPE_GET(x)               (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
+#define GPIO_PIN15_INT_TYPE_SET(x)               (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
+#define GPIO_PIN15_PAD_DRIVER_MSB                2
+#define GPIO_PIN15_PAD_DRIVER_LSB                2
+#define GPIO_PIN15_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN15_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
+#define GPIO_PIN15_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
+#define GPIO_PIN15_SOURCE_MSB                    0
+#define GPIO_PIN15_SOURCE_LSB                    0
+#define GPIO_PIN15_SOURCE_MASK                   0x00000001
+#define GPIO_PIN15_SOURCE_GET(x)                 (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
+#define GPIO_PIN15_SOURCE_SET(x)                 (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
+
+#define GPIO_PIN16_ADDRESS                       0x00000068
+#define GPIO_PIN16_OFFSET                        0x00000068
+#define GPIO_PIN16_CONFIG_MSB                    12
+#define GPIO_PIN16_CONFIG_LSB                    11
+#define GPIO_PIN16_CONFIG_MASK                   0x00001800
+#define GPIO_PIN16_CONFIG_GET(x)                 (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
+#define GPIO_PIN16_CONFIG_SET(x)                 (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN16_INT_TYPE_MSB                  9
+#define GPIO_PIN16_INT_TYPE_LSB                  7
+#define GPIO_PIN16_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN16_INT_TYPE_GET(x)               (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
+#define GPIO_PIN16_INT_TYPE_SET(x)               (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
+#define GPIO_PIN16_PAD_DRIVER_MSB                2
+#define GPIO_PIN16_PAD_DRIVER_LSB                2
+#define GPIO_PIN16_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN16_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
+#define GPIO_PIN16_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
+#define GPIO_PIN16_SOURCE_MSB                    0
+#define GPIO_PIN16_SOURCE_LSB                    0
+#define GPIO_PIN16_SOURCE_MASK                   0x00000001
+#define GPIO_PIN16_SOURCE_GET(x)                 (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
+#define GPIO_PIN16_SOURCE_SET(x)                 (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
+
+#define GPIO_PIN17_ADDRESS                       0x0000006c
+#define GPIO_PIN17_OFFSET                        0x0000006c
+#define GPIO_PIN17_CONFIG_MSB                    12
+#define GPIO_PIN17_CONFIG_LSB                    11
+#define GPIO_PIN17_CONFIG_MASK                   0x00001800
+#define GPIO_PIN17_CONFIG_GET(x)                 (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
+#define GPIO_PIN17_CONFIG_SET(x)                 (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB             10
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x)          (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN17_INT_TYPE_MSB                  9
+#define GPIO_PIN17_INT_TYPE_LSB                  7
+#define GPIO_PIN17_INT_TYPE_MASK                 0x00000380
+#define GPIO_PIN17_INT_TYPE_GET(x)               (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
+#define GPIO_PIN17_INT_TYPE_SET(x)               (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
+#define GPIO_PIN17_PAD_DRIVER_MSB                2
+#define GPIO_PIN17_PAD_DRIVER_LSB                2
+#define GPIO_PIN17_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN17_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
+#define GPIO_PIN17_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
+#define GPIO_PIN17_SOURCE_MSB                    0
+#define GPIO_PIN17_SOURCE_LSB                    0
+#define GPIO_PIN17_SOURCE_MASK                   0x00000001
+#define GPIO_PIN17_SOURCE_GET(x)                 (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
+#define GPIO_PIN17_SOURCE_SET(x)                 (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
+
+#define SDIO_PIN_ADDRESS                         0x00000070
+#define SDIO_PIN_OFFSET                          0x00000070
+#define SDIO_PIN_PAD_PULL_MSB                    3
+#define SDIO_PIN_PAD_PULL_LSB                    2
+#define SDIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define SDIO_PIN_PAD_PULL_GET(x)                 (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
+#define SDIO_PIN_PAD_PULL_SET(x)                 (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
+#define SDIO_PIN_PAD_STRENGTH_MSB                1
+#define SDIO_PIN_PAD_STRENGTH_LSB                0
+#define SDIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define SDIO_PIN_PAD_STRENGTH_GET(x)             (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
+#define SDIO_PIN_PAD_STRENGTH_SET(x)             (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
+
+#define CLK_REQ_PIN_ADDRESS                      0x00000074
+#define CLK_REQ_PIN_OFFSET                       0x00000074
+#define CLK_REQ_PIN_ATE_OE_L_MSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_LSB                 4
+#define CLK_REQ_PIN_ATE_OE_L_MASK                0x00000010
+#define CLK_REQ_PIN_ATE_OE_L_GET(x)              (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
+#define CLK_REQ_PIN_ATE_OE_L_SET(x)              (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
+#define CLK_REQ_PIN_PAD_PULL_MSB                 3
+#define CLK_REQ_PIN_PAD_PULL_LSB                 2
+#define CLK_REQ_PIN_PAD_PULL_MASK                0x0000000c
+#define CLK_REQ_PIN_PAD_PULL_GET(x)              (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
+#define CLK_REQ_PIN_PAD_PULL_SET(x)              (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
+#define CLK_REQ_PIN_PAD_STRENGTH_MSB             1
+#define CLK_REQ_PIN_PAD_STRENGTH_LSB             0
+#define CLK_REQ_PIN_PAD_STRENGTH_MASK            0x00000003
+#define CLK_REQ_PIN_PAD_STRENGTH_GET(x)          (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
+#define CLK_REQ_PIN_PAD_STRENGTH_SET(x)          (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
+
+#define SIGMA_DELTA_ADDRESS                      0x00000078
+#define SIGMA_DELTA_OFFSET                       0x00000078
+#define SIGMA_DELTA_ENABLE_MSB                   16
+#define SIGMA_DELTA_ENABLE_LSB                   16
+#define SIGMA_DELTA_ENABLE_MASK                  0x00010000
+#define SIGMA_DELTA_ENABLE_GET(x)                (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
+#define SIGMA_DELTA_ENABLE_SET(x)                (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
+#define SIGMA_DELTA_PRESCALAR_MSB                15
+#define SIGMA_DELTA_PRESCALAR_LSB                8
+#define SIGMA_DELTA_PRESCALAR_MASK               0x0000ff00
+#define SIGMA_DELTA_PRESCALAR_GET(x)             (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
+#define SIGMA_DELTA_PRESCALAR_SET(x)             (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
+#define SIGMA_DELTA_TARGET_MSB                   7
+#define SIGMA_DELTA_TARGET_LSB                   0
+#define SIGMA_DELTA_TARGET_MASK                  0x000000ff
+#define SIGMA_DELTA_TARGET_GET(x)                (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
+#define SIGMA_DELTA_TARGET_SET(x)                (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
+
+#define DEBUG_CONTROL_ADDRESS                    0x0000007c
+#define DEBUG_CONTROL_OFFSET                     0x0000007c
+#define DEBUG_CONTROL_OBS_OE_L_MSB               1
+#define DEBUG_CONTROL_OBS_OE_L_LSB               1
+#define DEBUG_CONTROL_OBS_OE_L_MASK              0x00000002
+#define DEBUG_CONTROL_OBS_OE_L_GET(x)            (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
+#define DEBUG_CONTROL_OBS_OE_L_SET(x)            (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
+#define DEBUG_CONTROL_ENABLE_MSB                 0
+#define DEBUG_CONTROL_ENABLE_LSB                 0
+#define DEBUG_CONTROL_ENABLE_MASK                0x00000001
+#define DEBUG_CONTROL_ENABLE_GET(x)              (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
+#define DEBUG_CONTROL_ENABLE_SET(x)              (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
+
+#define DEBUG_INPUT_SEL_ADDRESS                  0x00000080
+#define DEBUG_INPUT_SEL_OFFSET                   0x00000080
+#define DEBUG_INPUT_SEL_SRC_MSB                  3
+#define DEBUG_INPUT_SEL_SRC_LSB                  0
+#define DEBUG_INPUT_SEL_SRC_MASK                 0x0000000f
+#define DEBUG_INPUT_SEL_SRC_GET(x)               (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
+#define DEBUG_INPUT_SEL_SRC_SET(x)               (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
+
+#define DEBUG_OUT_ADDRESS                        0x00000084
+#define DEBUG_OUT_OFFSET                         0x00000084
+#define DEBUG_OUT_DATA_MSB                       17
+#define DEBUG_OUT_DATA_LSB                       0
+#define DEBUG_OUT_DATA_MASK                      0x0003ffff
+#define DEBUG_OUT_DATA_GET(x)                    (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
+#define DEBUG_OUT_DATA_SET(x)                    (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
+
+#define LA_CONTROL_ADDRESS                       0x00000088
+#define LA_CONTROL_OFFSET                        0x00000088
+#define LA_CONTROL_RUN_MSB                       1
+#define LA_CONTROL_RUN_LSB                       1
+#define LA_CONTROL_RUN_MASK                      0x00000002
+#define LA_CONTROL_RUN_GET(x)                    (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
+#define LA_CONTROL_RUN_SET(x)                    (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
+#define LA_CONTROL_TRIGGERED_MSB                 0
+#define LA_CONTROL_TRIGGERED_LSB                 0
+#define LA_CONTROL_TRIGGERED_MASK                0x00000001
+#define LA_CONTROL_TRIGGERED_GET(x)              (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
+#define LA_CONTROL_TRIGGERED_SET(x)              (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
+
+#define LA_CLOCK_ADDRESS                         0x0000008c
+#define LA_CLOCK_OFFSET                          0x0000008c
+#define LA_CLOCK_DIV_MSB                         7
+#define LA_CLOCK_DIV_LSB                         0
+#define LA_CLOCK_DIV_MASK                        0x000000ff
+#define LA_CLOCK_DIV_GET(x)                      (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
+#define LA_CLOCK_DIV_SET(x)                      (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
+
+#define LA_STATUS_ADDRESS                        0x00000090
+#define LA_STATUS_OFFSET                         0x00000090
+#define LA_STATUS_INTERRUPT_MSB                  0
+#define LA_STATUS_INTERRUPT_LSB                  0
+#define LA_STATUS_INTERRUPT_MASK                 0x00000001
+#define LA_STATUS_INTERRUPT_GET(x)               (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
+#define LA_STATUS_INTERRUPT_SET(x)               (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
+
+#define LA_TRIGGER_SAMPLE_ADDRESS                0x00000094
+#define LA_TRIGGER_SAMPLE_OFFSET                 0x00000094
+#define LA_TRIGGER_SAMPLE_COUNT_MSB              15
+#define LA_TRIGGER_SAMPLE_COUNT_LSB              0
+#define LA_TRIGGER_SAMPLE_COUNT_MASK             0x0000ffff
+#define LA_TRIGGER_SAMPLE_COUNT_GET(x)           (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
+#define LA_TRIGGER_SAMPLE_COUNT_SET(x)           (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
+
+#define LA_TRIGGER_POSITION_ADDRESS              0x00000098
+#define LA_TRIGGER_POSITION_OFFSET               0x00000098
+#define LA_TRIGGER_POSITION_VALUE_MSB            15
+#define LA_TRIGGER_POSITION_VALUE_LSB            0
+#define LA_TRIGGER_POSITION_VALUE_MASK           0x0000ffff
+#define LA_TRIGGER_POSITION_VALUE_GET(x)         (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
+#define LA_TRIGGER_POSITION_VALUE_SET(x)         (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
+
+#define LA_PRE_TRIGGER_ADDRESS                   0x0000009c
+#define LA_PRE_TRIGGER_OFFSET                    0x0000009c
+#define LA_PRE_TRIGGER_COUNT_MSB                 15
+#define LA_PRE_TRIGGER_COUNT_LSB                 0
+#define LA_PRE_TRIGGER_COUNT_MASK                0x0000ffff
+#define LA_PRE_TRIGGER_COUNT_GET(x)              (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
+#define LA_PRE_TRIGGER_COUNT_SET(x)              (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
+
+#define LA_POST_TRIGGER_ADDRESS                  0x000000a0
+#define LA_POST_TRIGGER_OFFSET                   0x000000a0
+#define LA_POST_TRIGGER_COUNT_MSB                15
+#define LA_POST_TRIGGER_COUNT_LSB                0
+#define LA_POST_TRIGGER_COUNT_MASK               0x0000ffff
+#define LA_POST_TRIGGER_COUNT_GET(x)             (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
+#define LA_POST_TRIGGER_COUNT_SET(x)             (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
+
+#define LA_FILTER_CONTROL_ADDRESS                0x000000a4
+#define LA_FILTER_CONTROL_OFFSET                 0x000000a4
+#define LA_FILTER_CONTROL_DELTA_MSB              0
+#define LA_FILTER_CONTROL_DELTA_LSB              0
+#define LA_FILTER_CONTROL_DELTA_MASK             0x00000001
+#define LA_FILTER_CONTROL_DELTA_GET(x)           (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
+#define LA_FILTER_CONTROL_DELTA_SET(x)           (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
+
+#define LA_FILTER_DATA_ADDRESS                   0x000000a8
+#define LA_FILTER_DATA_OFFSET                    0x000000a8
+#define LA_FILTER_DATA_MATCH_MSB                 17
+#define LA_FILTER_DATA_MATCH_LSB                 0
+#define LA_FILTER_DATA_MATCH_MASK                0x0003ffff
+#define LA_FILTER_DATA_MATCH_GET(x)              (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
+#define LA_FILTER_DATA_MATCH_SET(x)              (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
+
+#define LA_FILTER_WILDCARD_ADDRESS               0x000000ac
+#define LA_FILTER_WILDCARD_OFFSET                0x000000ac
+#define LA_FILTER_WILDCARD_MATCH_MSB             17
+#define LA_FILTER_WILDCARD_MATCH_LSB             0
+#define LA_FILTER_WILDCARD_MATCH_MASK            0x0003ffff
+#define LA_FILTER_WILDCARD_MATCH_GET(x)          (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
+#define LA_FILTER_WILDCARD_MATCH_SET(x)          (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERA_DATA_ADDRESS                 0x000000b0
+#define LA_TRIGGERA_DATA_OFFSET                  0x000000b0
+#define LA_TRIGGERA_DATA_MATCH_MSB               17
+#define LA_TRIGGERA_DATA_MATCH_LSB               0
+#define LA_TRIGGERA_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERA_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
+#define LA_TRIGGERA_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
+
+#define LA_TRIGGERA_WILDCARD_ADDRESS             0x000000b4
+#define LA_TRIGGERA_WILDCARD_OFFSET              0x000000b4
+#define LA_TRIGGERA_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERA_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERA_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERA_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERA_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERB_DATA_ADDRESS                 0x000000b8
+#define LA_TRIGGERB_DATA_OFFSET                  0x000000b8
+#define LA_TRIGGERB_DATA_MATCH_MSB               17
+#define LA_TRIGGERB_DATA_MATCH_LSB               0
+#define LA_TRIGGERB_DATA_MATCH_MASK              0x0003ffff
+#define LA_TRIGGERB_DATA_MATCH_GET(x)            (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
+#define LA_TRIGGERB_DATA_MATCH_SET(x)            (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
+
+#define LA_TRIGGERB_WILDCARD_ADDRESS             0x000000bc
+#define LA_TRIGGERB_WILDCARD_OFFSET              0x000000bc
+#define LA_TRIGGERB_WILDCARD_MATCH_MSB           17
+#define LA_TRIGGERB_WILDCARD_MATCH_LSB           0
+#define LA_TRIGGERB_WILDCARD_MATCH_MASK          0x0003ffff
+#define LA_TRIGGERB_WILDCARD_MATCH_GET(x)        (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERB_WILDCARD_MATCH_SET(x)        (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGER_ADDRESS                       0x000000c0
+#define LA_TRIGGER_OFFSET                        0x000000c0
+#define LA_TRIGGER_EVENT_MSB                     2
+#define LA_TRIGGER_EVENT_LSB                     0
+#define LA_TRIGGER_EVENT_MASK                    0x00000007
+#define LA_TRIGGER_EVENT_GET(x)                  (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
+#define LA_TRIGGER_EVENT_SET(x)                  (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
+
+#define LA_FIFO_ADDRESS                          0x000000c4
+#define LA_FIFO_OFFSET                           0x000000c4
+#define LA_FIFO_FULL_MSB                         1
+#define LA_FIFO_FULL_LSB                         1
+#define LA_FIFO_FULL_MASK                        0x00000002
+#define LA_FIFO_FULL_GET(x)                      (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
+#define LA_FIFO_FULL_SET(x)                      (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
+#define LA_FIFO_EMPTY_MSB                        0
+#define LA_FIFO_EMPTY_LSB                        0
+#define LA_FIFO_EMPTY_MASK                       0x00000001
+#define LA_FIFO_EMPTY_GET(x)                     (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
+#define LA_FIFO_EMPTY_SET(x)                     (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
+
+#define LA_ADDRESS                               0x000000c8
+#define LA_OFFSET                                0x000000c8
+#define LA_DATA_MSB                              17
+#define LA_DATA_LSB                              0
+#define LA_DATA_MASK                             0x0003ffff
+#define LA_DATA_GET(x)                           (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
+#define LA_DATA_SET(x)                           (((x) << LA_DATA_LSB) & LA_DATA_MASK)
+
+#define ANT_PIN_ADDRESS                          0x000000d0
+#define ANT_PIN_OFFSET                           0x000000d0
+#define ANT_PIN_PAD_PULL_MSB                     3
+#define ANT_PIN_PAD_PULL_LSB                     2
+#define ANT_PIN_PAD_PULL_MASK                    0x0000000c
+#define ANT_PIN_PAD_PULL_GET(x)                  (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
+#define ANT_PIN_PAD_PULL_SET(x)                  (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
+#define ANT_PIN_PAD_STRENGTH_MSB                 1
+#define ANT_PIN_PAD_STRENGTH_LSB                 0
+#define ANT_PIN_PAD_STRENGTH_MASK                0x00000003
+#define ANT_PIN_PAD_STRENGTH_GET(x)              (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
+#define ANT_PIN_PAD_STRENGTH_SET(x)              (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
+
+#define ANTD_PIN_ADDRESS                         0x000000d4
+#define ANTD_PIN_OFFSET                          0x000000d4
+#define ANTD_PIN_PAD_PULL_MSB                    1
+#define ANTD_PIN_PAD_PULL_LSB                    0
+#define ANTD_PIN_PAD_PULL_MASK                   0x00000003
+#define ANTD_PIN_PAD_PULL_GET(x)                 (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
+#define ANTD_PIN_PAD_PULL_SET(x)                 (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
+
+#define GPIO_PIN_ADDRESS                         0x000000d8
+#define GPIO_PIN_OFFSET                          0x000000d8
+#define GPIO_PIN_PAD_PULL_MSB                    3
+#define GPIO_PIN_PAD_PULL_LSB                    2
+#define GPIO_PIN_PAD_PULL_MASK                   0x0000000c
+#define GPIO_PIN_PAD_PULL_GET(x)                 (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
+#define GPIO_PIN_PAD_PULL_SET(x)                 (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
+#define GPIO_PIN_PAD_STRENGTH_MSB                1
+#define GPIO_PIN_PAD_STRENGTH_LSB                0
+#define GPIO_PIN_PAD_STRENGTH_MASK               0x00000003
+#define GPIO_PIN_PAD_STRENGTH_GET(x)             (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
+#define GPIO_PIN_PAD_STRENGTH_SET(x)             (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
+
+#define GPIO_H_PIN_ADDRESS                       0x000000dc
+#define GPIO_H_PIN_OFFSET                        0x000000dc
+#define GPIO_H_PIN_PAD_PULL_MSB                  1
+#define GPIO_H_PIN_PAD_PULL_LSB                  0
+#define GPIO_H_PIN_PAD_PULL_MASK                 0x00000003
+#define GPIO_H_PIN_PAD_PULL_GET(x)               (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
+#define GPIO_H_PIN_PAD_PULL_SET(x)               (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
+
+#define BT_PIN_ADDRESS                           0x000000e0
+#define BT_PIN_OFFSET                            0x000000e0
+#define BT_PIN_PAD_PULL_MSB                      3
+#define BT_PIN_PAD_PULL_LSB                      2
+#define BT_PIN_PAD_PULL_MASK                     0x0000000c
+#define BT_PIN_PAD_PULL_GET(x)                   (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
+#define BT_PIN_PAD_PULL_SET(x)                   (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
+#define BT_PIN_PAD_STRENGTH_MSB                  1
+#define BT_PIN_PAD_STRENGTH_LSB                  0
+#define BT_PIN_PAD_STRENGTH_MASK                 0x00000003
+#define BT_PIN_PAD_STRENGTH_GET(x)               (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
+#define BT_PIN_PAD_STRENGTH_SET(x)               (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
+
+#define BT_WLAN_PIN_ADDRESS                      0x000000e4
+#define BT_WLAN_PIN_OFFSET                       0x000000e4
+#define BT_WLAN_PIN_PAD_PULL_MSB                 1
+#define BT_WLAN_PIN_PAD_PULL_LSB                 0
+#define BT_WLAN_PIN_PAD_PULL_MASK                0x00000003
+#define BT_WLAN_PIN_PAD_PULL_GET(x)              (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
+#define BT_WLAN_PIN_PAD_PULL_SET(x)              (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
+
+#define SI_UART_PIN_ADDRESS                      0x000000e8
+#define SI_UART_PIN_OFFSET                       0x000000e8
+#define SI_UART_PIN_PAD_PULL_MSB                 3
+#define SI_UART_PIN_PAD_PULL_LSB                 2
+#define SI_UART_PIN_PAD_PULL_MASK                0x0000000c
+#define SI_UART_PIN_PAD_PULL_GET(x)              (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
+#define SI_UART_PIN_PAD_PULL_SET(x)              (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
+#define SI_UART_PIN_PAD_STRENGTH_MSB             1
+#define SI_UART_PIN_PAD_STRENGTH_LSB             0
+#define SI_UART_PIN_PAD_STRENGTH_MASK            0x00000003
+#define SI_UART_PIN_PAD_STRENGTH_GET(x)          (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
+#define SI_UART_PIN_PAD_STRENGTH_SET(x)          (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
+
+#define CLK32K_PIN_ADDRESS                       0x000000ec
+#define CLK32K_PIN_OFFSET                        0x000000ec
+#define CLK32K_PIN_PAD_PULL_MSB                  1
+#define CLK32K_PIN_PAD_PULL_LSB                  0
+#define CLK32K_PIN_PAD_PULL_MASK                 0x00000003
+#define CLK32K_PIN_PAD_PULL_GET(x)               (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
+#define CLK32K_PIN_PAD_PULL_SET(x)               (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
+
+#define RESET_TUPLE_STATUS_ADDRESS               0x000000f0
+#define RESET_TUPLE_STATUS_OFFSET                0x000000f0
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB  11
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB  8
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB   7
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB   0
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK  0x000000ff
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_reg_reg_s {
+  volatile unsigned int gpio_out;
+  volatile unsigned int gpio_out_w1ts;
+  volatile unsigned int gpio_out_w1tc;
+  volatile unsigned int gpio_enable;
+  volatile unsigned int gpio_enable_w1ts;
+  volatile unsigned int gpio_enable_w1tc;
+  volatile unsigned int gpio_in;
+  volatile unsigned int gpio_status;
+  volatile unsigned int gpio_status_w1ts;
+  volatile unsigned int gpio_status_w1tc;
+  volatile unsigned int gpio_pin0;
+  volatile unsigned int gpio_pin1;
+  volatile unsigned int gpio_pin2;
+  volatile unsigned int gpio_pin3;
+  volatile unsigned int gpio_pin4;
+  volatile unsigned int gpio_pin5;
+  volatile unsigned int gpio_pin6;
+  volatile unsigned int gpio_pin7;
+  volatile unsigned int gpio_pin8;
+  volatile unsigned int gpio_pin9;
+  volatile unsigned int gpio_pin10;
+  volatile unsigned int gpio_pin11;
+  volatile unsigned int gpio_pin12;
+  volatile unsigned int gpio_pin13;
+  volatile unsigned int gpio_pin14;
+  volatile unsigned int gpio_pin15;
+  volatile unsigned int gpio_pin16;
+  volatile unsigned int gpio_pin17;
+  volatile unsigned int sdio_pin;
+  volatile unsigned int clk_req_pin;
+  volatile unsigned int sigma_delta;
+  volatile unsigned int debug_control;
+  volatile unsigned int debug_input_sel;
+  volatile unsigned int debug_out;
+  volatile unsigned int la_control;
+  volatile unsigned int la_clock;
+  volatile unsigned int la_status;
+  volatile unsigned int la_trigger_sample;
+  volatile unsigned int la_trigger_position;
+  volatile unsigned int la_pre_trigger;
+  volatile unsigned int la_post_trigger;
+  volatile unsigned int la_filter_control;
+  volatile unsigned int la_filter_data;
+  volatile unsigned int la_filter_wildcard;
+  volatile unsigned int la_triggera_data;
+  volatile unsigned int la_triggera_wildcard;
+  volatile unsigned int la_triggerb_data;
+  volatile unsigned int la_triggerb_wildcard;
+  volatile unsigned int la_trigger;
+  volatile unsigned int la_fifo;
+  volatile unsigned int la[2];
+  volatile unsigned int ant_pin;
+  volatile unsigned int antd_pin;
+  volatile unsigned int gpio_pin;
+  volatile unsigned int gpio_h_pin;
+  volatile unsigned int bt_pin;
+  volatile unsigned int bt_wlan_pin;
+  volatile unsigned int si_uart_pin;
+  volatile unsigned int clk32k_pin;
+  volatile unsigned int reset_tuple_status;
+} gpio_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..20ac2b5c8920
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h
@@ -0,0 +1,405 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_HOST_REG_REG_H_
+#define _MBOX_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS                  0x00000400
+#define HOST_INT_STATUS_OFFSET                   0x00000400
+#define HOST_INT_STATUS_ERROR_MSB                7
+#define HOST_INT_STATUS_ERROR_LSB                7
+#define HOST_INT_STATUS_ERROR_MASK               0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB                  6
+#define HOST_INT_STATUS_CPU_LSB                  6
+#define HOST_INT_STATUS_CPU_MASK                 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_DRAGON_INT_MSB           5
+#define HOST_INT_STATUS_DRAGON_INT_LSB           5
+#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
+#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
+#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB              4
+#define HOST_INT_STATUS_COUNTER_LSB              4
+#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB            3
+#define HOST_INT_STATUS_MBOX_DATA_LSB            0
+#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS                   0x00000401
+#define CPU_INT_STATUS_OFFSET                    0x00000401
+#define CPU_INT_STATUS_BIT_MSB                   7
+#define CPU_INT_STATUS_BIT_LSB                   0
+#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS                 0x00000402
+#define ERROR_INT_STATUS_OFFSET                  0x00000402
+#define ERROR_INT_STATUS_SPI_MSB                 3
+#define ERROR_INT_STATUS_SPI_LSB                 3
+#define ERROR_INT_STATUS_SPI_MASK                0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB              2
+#define ERROR_INT_STATUS_WAKEUP_LSB              2
+#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS               0x00000403
+#define COUNTER_INT_STATUS_OFFSET                0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB           7
+#define COUNTER_INT_STATUS_COUNTER_LSB           0
+#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS                       0x00000404
+#define MBOX_FRAME_OFFSET                        0x00000404
+#define MBOX_FRAME_RX_EOM_MSB                    7
+#define MBOX_FRAME_RX_EOM_LSB                    4
+#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB                    3
+#define MBOX_FRAME_RX_SOM_LSB                    0
+#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
+#define RX_LOOKAHEAD0_OFFSET                     0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB                   7
+#define RX_LOOKAHEAD0_DATA_LSB                   0
+#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
+#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB                   7
+#define RX_LOOKAHEAD1_DATA_LSB                   0
+#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
+#define RX_LOOKAHEAD2_OFFSET                     0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB                   7
+#define RX_LOOKAHEAD2_DATA_LSB                   0
+#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
+#define RX_LOOKAHEAD3_OFFSET                     0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB                   7
+#define RX_LOOKAHEAD3_DATA_LSB                   0
+#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS                0x00000418
+#define INT_STATUS_ENABLE_OFFSET                 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB              7
+#define INT_STATUS_ENABLE_ERROR_LSB              7
+#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB                6
+#define INT_STATUS_ENABLE_CPU_LSB                6
+#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
+#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
+#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
+#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB            4
+#define INT_STATUS_ENABLE_COUNTER_LSB            4
+#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS                            0x00000420
+#define COUNT_OFFSET                             0x00000420
+#define COUNT_VALUE_MSB                          7
+#define COUNT_VALUE_LSB                          0
+#define COUNT_VALUE_MASK                         0x000000ff
+#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS                        0x00000440
+#define COUNT_DEC_OFFSET                         0x00000440
+#define COUNT_DEC_VALUE_MSB                      7
+#define COUNT_DEC_VALUE_LSB                      0
+#define COUNT_DEC_VALUE_MASK                     0x000000ff
+#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS                          0x00000460
+#define SCRATCH_OFFSET                           0x00000460
+#define SCRATCH_VALUE_MSB                        7
+#define SCRATCH_VALUE_LSB                        0
+#define SCRATCH_VALUE_MASK                       0x000000ff
+#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS                     0x00000468
+#define FIFO_TIMEOUT_OFFSET                      0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB                   7
+#define FIFO_TIMEOUT_VALUE_LSB                   0
+#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS                    0x0000046a
+#define DISABLE_SLEEP_OFFSET                     0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB                1
+#define DISABLE_SLEEP_FOR_INT_LSB                1
+#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB                     0
+#define DISABLE_SLEEP_ON_LSB                     0
+#define DISABLE_SLEEP_ON_MASK                    0x00000001
+#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS                        0x00000470
+#define LOCAL_BUS_OFFSET                         0x00000470
+#define LOCAL_BUS_STATE_MSB                      1
+#define LOCAL_BUS_STATE_LSB                      0
+#define LOCAL_BUS_STATE_MASK                     0x00000003
+#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS                         0x00000472
+#define INT_WLAN_OFFSET                          0x00000472
+#define INT_WLAN_VECTOR_MSB                      7
+#define INT_WLAN_VECTOR_LSB                      0
+#define INT_WLAN_VECTOR_MASK                     0x000000ff
+#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS                      0x00000474
+#define WINDOW_DATA_OFFSET                       0x00000474
+#define WINDOW_DATA_DATA_MSB                     7
+#define WINDOW_DATA_DATA_LSB                     0
+#define WINDOW_DATA_DATA_MASK                    0x000000ff
+#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB               7
+#define WINDOW_WRITE_ADDR_ADDR_LSB               0
+#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB                7
+#define WINDOW_READ_ADDR_ADDR_LSB                0
+#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define SPI_CONFIG_ADDRESS                       0x00000480
+#define SPI_CONFIG_OFFSET                        0x00000480
+#define SPI_CONFIG_SPI_RESET_MSB                 4
+#define SPI_CONFIG_SPI_RESET_LSB                 4
+#define SPI_CONFIG_SPI_RESET_MASK                0x00000010
+#define SPI_CONFIG_SPI_RESET_GET(x)              (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
+#define SPI_CONFIG_SPI_RESET_SET(x)              (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
+#define SPI_CONFIG_INTERRUPT_ENABLE_MSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_LSB          3
+#define SPI_CONFIG_INTERRUPT_ENABLE_MASK         0x00000008
+#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x)       (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x)       (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define SPI_CONFIG_TEST_MODE_MSB                 2
+#define SPI_CONFIG_TEST_MODE_LSB                 2
+#define SPI_CONFIG_TEST_MODE_MASK                0x00000004
+#define SPI_CONFIG_TEST_MODE_GET(x)              (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
+#define SPI_CONFIG_TEST_MODE_SET(x)              (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
+#define SPI_CONFIG_DATA_SIZE_MSB                 1
+#define SPI_CONFIG_DATA_SIZE_LSB                 0
+#define SPI_CONFIG_DATA_SIZE_MASK                0x00000003
+#define SPI_CONFIG_DATA_SIZE_GET(x)              (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
+#define SPI_CONFIG_DATA_SIZE_SET(x)              (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
+
+#define SPI_STATUS_ADDRESS                       0x00000481
+#define SPI_STATUS_OFFSET                        0x00000481
+#define SPI_STATUS_ADDR_ERR_MSB                  3
+#define SPI_STATUS_ADDR_ERR_LSB                  3
+#define SPI_STATUS_ADDR_ERR_MASK                 0x00000008
+#define SPI_STATUS_ADDR_ERR_GET(x)               (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
+#define SPI_STATUS_ADDR_ERR_SET(x)               (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
+#define SPI_STATUS_RD_ERR_MSB                    2
+#define SPI_STATUS_RD_ERR_LSB                    2
+#define SPI_STATUS_RD_ERR_MASK                   0x00000004
+#define SPI_STATUS_RD_ERR_GET(x)                 (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
+#define SPI_STATUS_RD_ERR_SET(x)                 (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
+#define SPI_STATUS_WR_ERR_MSB                    1
+#define SPI_STATUS_WR_ERR_LSB                    1
+#define SPI_STATUS_WR_ERR_MASK                   0x00000002
+#define SPI_STATUS_WR_ERR_GET(x)                 (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
+#define SPI_STATUS_WR_ERR_SET(x)                 (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
+#define SPI_STATUS_READY_MSB                     0
+#define SPI_STATUS_READY_LSB                     0
+#define SPI_STATUS_READY_MASK                    0x00000001
+#define SPI_STATUS_READY_GET(x)                  (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
+#define SPI_STATUS_READY_SET(x)                  (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS               0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET                0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK              0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x)            (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x)            (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CIS_WINDOW_ADDRESS                       0x00000600
+#define CIS_WINDOW_OFFSET                        0x00000600
+#define CIS_WINDOW_DATA_MSB                      7
+#define CIS_WINDOW_DATA_LSB                      0
+#define CIS_WINDOW_DATA_MASK                     0x000000ff
+#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_host_reg_reg_s {
+  unsigned char pad0[1024]; /* pad to 0x400 */
+  volatile unsigned char host_int_status;
+  volatile unsigned char cpu_int_status;
+  volatile unsigned char error_int_status;
+  volatile unsigned char counter_int_status;
+  volatile unsigned char mbox_frame;
+  volatile unsigned char rx_lookahead_valid;
+  unsigned char pad1[2]; /* pad to 0x408 */
+  volatile unsigned char rx_lookahead0[4];
+  volatile unsigned char rx_lookahead1[4];
+  volatile unsigned char rx_lookahead2[4];
+  volatile unsigned char rx_lookahead3[4];
+  volatile unsigned char int_status_enable;
+  volatile unsigned char cpu_int_status_enable;
+  volatile unsigned char error_status_enable;
+  volatile unsigned char counter_int_status_enable;
+  unsigned char pad2[4]; /* pad to 0x420 */
+  volatile unsigned char count[8];
+  unsigned char pad3[24]; /* pad to 0x440 */
+  volatile unsigned char count_dec[32];
+  volatile unsigned char scratch[8];
+  volatile unsigned char fifo_timeout;
+  volatile unsigned char fifo_timeout_enable;
+  volatile unsigned char disable_sleep;
+  unsigned char pad4[5]; /* pad to 0x470 */
+  volatile unsigned char local_bus;
+  unsigned char pad5[1]; /* pad to 0x472 */
+  volatile unsigned char int_wlan;
+  unsigned char pad6[1]; /* pad to 0x474 */
+  volatile unsigned char window_data[4];
+  volatile unsigned char window_write_addr[4];
+  volatile unsigned char window_read_addr[4];
+  volatile unsigned char spi_config;
+  volatile unsigned char spi_status;
+  volatile unsigned char non_assoc_sleep_en;
+  unsigned char pad7[381]; /* pad to 0x600 */
+  volatile unsigned char cis_window[512];
+} mbox_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h
new file mode 100644
index 000000000000..d232764d5af6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h
@@ -0,0 +1,500 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_REG_REG_H_
+#define _MBOX_REG_REG_H_
+
+#define MBOX_FIFO_ADDRESS                        0x00000000
+#define MBOX_FIFO_OFFSET                         0x00000000
+#define MBOX_FIFO_DATA_MSB                       19
+#define MBOX_FIFO_DATA_LSB                       0
+#define MBOX_FIFO_DATA_MASK                      0x000fffff
+#define MBOX_FIFO_DATA_GET(x)                    (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
+#define MBOX_FIFO_DATA_SET(x)                    (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
+
+#define MBOX_FIFO_STATUS_ADDRESS                 0x00000010
+#define MBOX_FIFO_STATUS_OFFSET                  0x00000010
+#define MBOX_FIFO_STATUS_EMPTY_MSB               19
+#define MBOX_FIFO_STATUS_EMPTY_LSB               16
+#define MBOX_FIFO_STATUS_EMPTY_MASK              0x000f0000
+#define MBOX_FIFO_STATUS_EMPTY_GET(x)            (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x)            (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
+#define MBOX_FIFO_STATUS_FULL_MSB                15
+#define MBOX_FIFO_STATUS_FULL_LSB                12
+#define MBOX_FIFO_STATUS_FULL_MASK               0x0000f000
+#define MBOX_FIFO_STATUS_FULL_GET(x)             (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
+#define MBOX_FIFO_STATUS_FULL_SET(x)             (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
+
+#define MBOX_DMA_POLICY_ADDRESS                  0x00000014
+#define MBOX_DMA_POLICY_OFFSET                   0x00000014
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB           3
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK          0x00000008
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_LSB             2
+#define MBOX_DMA_POLICY_TX_ORDER_MASK            0x00000004
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB           1
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK          0x00000002
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_LSB             0
+#define MBOX_DMA_POLICY_RX_ORDER_MASK            0x00000001
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_RX_CONTROL_ADDRESS             0x0000001c
+#define MBOX0_DMA_RX_CONTROL_OFFSET              0x0000001c
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_RX_CONTROL_START_MSB           1
+#define MBOX0_DMA_RX_CONTROL_START_LSB           1
+#define MBOX0_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_TX_CONTROL_ADDRESS             0x00000024
+#define MBOX0_DMA_TX_CONTROL_OFFSET              0x00000024
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_TX_CONTROL_START_MSB           1
+#define MBOX0_DMA_TX_CONTROL_START_LSB           1
+#define MBOX0_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX0_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_RX_CONTROL_ADDRESS             0x0000002c
+#define MBOX1_DMA_RX_CONTROL_OFFSET              0x0000002c
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_RX_CONTROL_START_MSB           1
+#define MBOX1_DMA_RX_CONTROL_START_LSB           1
+#define MBOX1_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_TX_CONTROL_ADDRESS             0x00000034
+#define MBOX1_DMA_TX_CONTROL_OFFSET              0x00000034
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_TX_CONTROL_START_MSB           1
+#define MBOX1_DMA_TX_CONTROL_START_LSB           1
+#define MBOX1_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX1_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_RX_CONTROL_ADDRESS             0x0000003c
+#define MBOX2_DMA_RX_CONTROL_OFFSET              0x0000003c
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_RX_CONTROL_START_MSB           1
+#define MBOX2_DMA_RX_CONTROL_START_LSB           1
+#define MBOX2_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_TX_CONTROL_ADDRESS             0x00000044
+#define MBOX2_DMA_TX_CONTROL_OFFSET              0x00000044
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_TX_CONTROL_START_MSB           1
+#define MBOX2_DMA_TX_CONTROL_START_LSB           1
+#define MBOX2_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX2_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_RX_CONTROL_ADDRESS             0x0000004c
+#define MBOX3_DMA_RX_CONTROL_OFFSET              0x0000004c
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_RX_CONTROL_START_MSB           1
+#define MBOX3_DMA_RX_CONTROL_START_LSB           1
+#define MBOX3_DMA_RX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_TX_CONTROL_ADDRESS             0x00000054
+#define MBOX3_DMA_TX_CONTROL_OFFSET              0x00000054
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB          2
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK         0x00000004
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_TX_CONTROL_START_MSB           1
+#define MBOX3_DMA_TX_CONTROL_START_LSB           1
+#define MBOX3_DMA_TX_CONTROL_START_MASK          0x00000002
+#define MBOX3_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB            0
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK           0x00000001
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX_INT_STATUS_ADDRESS                  0x00000058
+#define MBOX_INT_STATUS_OFFSET                   0x00000058
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB          17
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB          11
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB          8
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define MBOX_INT_STATUS_HOST_MSB                 7
+#define MBOX_INT_STATUS_HOST_LSB                 0
+#define MBOX_INT_STATUS_HOST_MASK                0x000000ff
+#define MBOX_INT_STATUS_HOST_GET(x)              (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
+#define MBOX_INT_STATUS_HOST_SET(x)              (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
+
+#define MBOX_INT_ENABLE_ADDRESS                  0x0000005c
+#define MBOX_INT_ENABLE_OFFSET                   0x0000005c
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB      31
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB      28
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK     0xf0000000
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB  27
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB  24
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB      23
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB      20
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK     0x00f00000
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB          17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK         0x00020000
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB         16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK        0x00010000
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB         15
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB         12
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK        0x0000f000
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB          11
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB          8
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK         0x00000f00
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define MBOX_INT_ENABLE_HOST_MSB                 7
+#define MBOX_INT_ENABLE_HOST_LSB                 0
+#define MBOX_INT_ENABLE_HOST_MASK                0x000000ff
+#define MBOX_INT_ENABLE_HOST_GET(x)              (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
+#define MBOX_INT_ENABLE_HOST_SET(x)              (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
+
+#define INT_HOST_ADDRESS                         0x00000060
+#define INT_HOST_OFFSET                          0x00000060
+#define INT_HOST_VECTOR_MSB                      7
+#define INT_HOST_VECTOR_LSB                      0
+#define INT_HOST_VECTOR_MASK                     0x000000ff
+#define INT_HOST_VECTOR_GET(x)                   (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
+#define INT_HOST_VECTOR_SET(x)                   (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
+
+#define LOCAL_COUNT_ADDRESS                      0x00000080
+#define LOCAL_COUNT_OFFSET                       0x00000080
+#define LOCAL_COUNT_VALUE_MSB                    7
+#define LOCAL_COUNT_VALUE_LSB                    0
+#define LOCAL_COUNT_VALUE_MASK                   0x000000ff
+#define LOCAL_COUNT_VALUE_GET(x)                 (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
+#define LOCAL_COUNT_VALUE_SET(x)                 (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
+
+#define COUNT_INC_ADDRESS                        0x000000a0
+#define COUNT_INC_OFFSET                         0x000000a0
+#define COUNT_INC_VALUE_MSB                      7
+#define COUNT_INC_VALUE_LSB                      0
+#define COUNT_INC_VALUE_MASK                     0x000000ff
+#define COUNT_INC_VALUE_GET(x)                   (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
+#define COUNT_INC_VALUE_SET(x)                   (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
+
+#define LOCAL_SCRATCH_ADDRESS                    0x000000c0
+#define LOCAL_SCRATCH_OFFSET                     0x000000c0
+#define LOCAL_SCRATCH_VALUE_MSB                  7
+#define LOCAL_SCRATCH_VALUE_LSB                  0
+#define LOCAL_SCRATCH_VALUE_MASK                 0x000000ff
+#define LOCAL_SCRATCH_VALUE_GET(x)               (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
+#define LOCAL_SCRATCH_VALUE_SET(x)               (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
+
+#define USE_LOCAL_BUS_ADDRESS                    0x000000e0
+#define USE_LOCAL_BUS_OFFSET                     0x000000e0
+#define USE_LOCAL_BUS_PIN_INIT_MSB               0
+#define USE_LOCAL_BUS_PIN_INIT_LSB               0
+#define USE_LOCAL_BUS_PIN_INIT_MASK              0x00000001
+#define USE_LOCAL_BUS_PIN_INIT_GET(x)            (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x)            (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define SDIO_CONFIG_ADDRESS                      0x000000e4
+#define SDIO_CONFIG_OFFSET                       0x000000e4
+#define SDIO_CONFIG_CCCR_IOR1_MSB                0
+#define SDIO_CONFIG_CCCR_IOR1_LSB                0
+#define SDIO_CONFIG_CCCR_IOR1_MASK               0x00000001
+#define SDIO_CONFIG_CCCR_IOR1_GET(x)             (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x)             (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define MBOX_DEBUG_ADDRESS                       0x000000e8
+#define MBOX_DEBUG_OFFSET                        0x000000e8
+#define MBOX_DEBUG_SEL_MSB                       2
+#define MBOX_DEBUG_SEL_LSB                       0
+#define MBOX_DEBUG_SEL_MASK                      0x00000007
+#define MBOX_DEBUG_SEL_GET(x)                    (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
+#define MBOX_DEBUG_SEL_SET(x)                    (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
+
+#define MBOX_FIFO_RESET_ADDRESS                  0x000000ec
+#define MBOX_FIFO_RESET_OFFSET                   0x000000ec
+#define MBOX_FIFO_RESET_INIT_MSB                 0
+#define MBOX_FIFO_RESET_INIT_LSB                 0
+#define MBOX_FIFO_RESET_INIT_MASK                0x00000001
+#define MBOX_FIFO_RESET_INIT_GET(x)              (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
+#define MBOX_FIFO_RESET_INIT_SET(x)              (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
+
+#define MBOX_TXFIFO_POP_ADDRESS                  0x000000f0
+#define MBOX_TXFIFO_POP_OFFSET                   0x000000f0
+#define MBOX_TXFIFO_POP_DATA_MSB                 0
+#define MBOX_TXFIFO_POP_DATA_LSB                 0
+#define MBOX_TXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_TXFIFO_POP_DATA_GET(x)              (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
+#define MBOX_TXFIFO_POP_DATA_SET(x)              (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
+
+#define MBOX_RXFIFO_POP_ADDRESS                  0x00000100
+#define MBOX_RXFIFO_POP_OFFSET                   0x00000100
+#define MBOX_RXFIFO_POP_DATA_MSB                 0
+#define MBOX_RXFIFO_POP_DATA_LSB                 0
+#define MBOX_RXFIFO_POP_DATA_MASK                0x00000001
+#define MBOX_RXFIFO_POP_DATA_GET(x)              (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
+#define MBOX_RXFIFO_POP_DATA_SET(x)              (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
+
+#define SDIO_DEBUG_ADDRESS                       0x00000110
+#define SDIO_DEBUG_OFFSET                        0x00000110
+#define SDIO_DEBUG_SEL_MSB                       3
+#define SDIO_DEBUG_SEL_LSB                       0
+#define SDIO_DEBUG_SEL_MASK                      0x0000000f
+#define SDIO_DEBUG_SEL_GET(x)                    (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
+#define SDIO_DEBUG_SEL_SET(x)                    (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
+
+#define HOST_IF_WINDOW_ADDRESS                   0x00002000
+#define HOST_IF_WINDOW_OFFSET                    0x00002000
+#define HOST_IF_WINDOW_DATA_MSB                  7
+#define HOST_IF_WINDOW_DATA_LSB                  0
+#define HOST_IF_WINDOW_DATA_MASK                 0x000000ff
+#define HOST_IF_WINDOW_DATA_GET(x)               (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
+#define HOST_IF_WINDOW_DATA_SET(x)               (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_reg_reg_s {
+  volatile unsigned int mbox_fifo[4];
+  volatile unsigned int mbox_fifo_status;
+  volatile unsigned int mbox_dma_policy;
+  volatile unsigned int mbox0_dma_rx_descriptor_base;
+  volatile unsigned int mbox0_dma_rx_control;
+  volatile unsigned int mbox0_dma_tx_descriptor_base;
+  volatile unsigned int mbox0_dma_tx_control;
+  volatile unsigned int mbox1_dma_rx_descriptor_base;
+  volatile unsigned int mbox1_dma_rx_control;
+  volatile unsigned int mbox1_dma_tx_descriptor_base;
+  volatile unsigned int mbox1_dma_tx_control;
+  volatile unsigned int mbox2_dma_rx_descriptor_base;
+  volatile unsigned int mbox2_dma_rx_control;
+  volatile unsigned int mbox2_dma_tx_descriptor_base;
+  volatile unsigned int mbox2_dma_tx_control;
+  volatile unsigned int mbox3_dma_rx_descriptor_base;
+  volatile unsigned int mbox3_dma_rx_control;
+  volatile unsigned int mbox3_dma_tx_descriptor_base;
+  volatile unsigned int mbox3_dma_tx_control;
+  volatile unsigned int mbox_int_status;
+  volatile unsigned int mbox_int_enable;
+  volatile unsigned int int_host;
+  unsigned char pad0[28]; /* pad to 0x80 */
+  volatile unsigned int local_count[8];
+  volatile unsigned int count_inc[8];
+  volatile unsigned int local_scratch[8];
+  volatile unsigned int use_local_bus;
+  volatile unsigned int sdio_config;
+  volatile unsigned int mbox_debug;
+  volatile unsigned int mbox_fifo_reset;
+  volatile unsigned int mbox_txfifo_pop[4];
+  volatile unsigned int mbox_rxfifo_pop[4];
+  volatile unsigned int sdio_debug;
+  unsigned char pad1[7916]; /* pad to 0x2000 */
+  volatile unsigned int host_if_window[2048];
+} mbox_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h
new file mode 100644
index 000000000000..cc2cb7350a78
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h
@@ -0,0 +1,1182 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_REG_REG_H_
+#define _RTC_REG_REG_H_
+
+#define RESET_CONTROL_ADDRESS                    0x00000000
+#define RESET_CONTROL_OFFSET                     0x00000000
+#define RESET_CONTROL_CPU_INIT_RESET_MSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_LSB         11
+#define RESET_CONTROL_CPU_INIT_RESET_MASK        0x00000800
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x)      (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x)      (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB        10
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK       0x00000400
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x)     (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x)     (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define RESET_CONTROL_RST_OUT_MSB                9
+#define RESET_CONTROL_RST_OUT_LSB                9
+#define RESET_CONTROL_RST_OUT_MASK               0x00000200
+#define RESET_CONTROL_RST_OUT_GET(x)             (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
+#define RESET_CONTROL_RST_OUT_SET(x)             (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
+#define RESET_CONTROL_COLD_RST_MSB               8
+#define RESET_CONTROL_COLD_RST_LSB               8
+#define RESET_CONTROL_COLD_RST_MASK              0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+#define RESET_CONTROL_WARM_RST_MSB               7
+#define RESET_CONTROL_WARM_RST_LSB               7
+#define RESET_CONTROL_WARM_RST_MASK              0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+#define RESET_CONTROL_CPU_WARM_RST_MSB           6
+#define RESET_CONTROL_CPU_WARM_RST_LSB           6
+#define RESET_CONTROL_CPU_WARM_RST_MASK          0x00000040
+#define RESET_CONTROL_CPU_WARM_RST_GET(x)        (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x)        (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
+#define RESET_CONTROL_MAC_COLD_RST_MSB           5
+#define RESET_CONTROL_MAC_COLD_RST_LSB           5
+#define RESET_CONTROL_MAC_COLD_RST_MASK          0x00000020
+#define RESET_CONTROL_MAC_COLD_RST_GET(x)        (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x)        (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
+#define RESET_CONTROL_MAC_WARM_RST_MSB           4
+#define RESET_CONTROL_MAC_WARM_RST_LSB           4
+#define RESET_CONTROL_MAC_WARM_RST_MASK          0x00000010
+#define RESET_CONTROL_MAC_WARM_RST_GET(x)        (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x)        (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
+#define RESET_CONTROL_MBOX_RST_MSB               2
+#define RESET_CONTROL_MBOX_RST_LSB               2
+#define RESET_CONTROL_MBOX_RST_MASK              0x00000004
+#define RESET_CONTROL_MBOX_RST_GET(x)            (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
+#define RESET_CONTROL_MBOX_RST_SET(x)            (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_UART_RST_MSB               1
+#define RESET_CONTROL_UART_RST_LSB               1
+#define RESET_CONTROL_UART_RST_MASK              0x00000002
+#define RESET_CONTROL_UART_RST_GET(x)            (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
+#define RESET_CONTROL_UART_RST_SET(x)            (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MSB                0
+#define RESET_CONTROL_SI0_RST_LSB                0
+#define RESET_CONTROL_SI0_RST_MASK               0x00000001
+#define RESET_CONTROL_SI0_RST_GET(x)             (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
+#define RESET_CONTROL_SI0_RST_SET(x)             (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
+
+#define XTAL_CONTROL_ADDRESS                     0x00000004
+#define XTAL_CONTROL_OFFSET                      0x00000004
+#define XTAL_CONTROL_TCXO_MSB                    0
+#define XTAL_CONTROL_TCXO_LSB                    0
+#define XTAL_CONTROL_TCXO_MASK                   0x00000001
+#define XTAL_CONTROL_TCXO_GET(x)                 (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
+#define XTAL_CONTROL_TCXO_SET(x)                 (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
+
+#define TCXO_DETECT_ADDRESS                      0x00000008
+#define TCXO_DETECT_OFFSET                       0x00000008
+#define TCXO_DETECT_PRESENT_MSB                  0
+#define TCXO_DETECT_PRESENT_LSB                  0
+#define TCXO_DETECT_PRESENT_MASK                 0x00000001
+#define TCXO_DETECT_PRESENT_GET(x)               (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
+#define TCXO_DETECT_PRESENT_SET(x)               (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
+
+#define XTAL_TEST_ADDRESS                        0x0000000c
+#define XTAL_TEST_OFFSET                         0x0000000c
+#define XTAL_TEST_NOTCXODET_MSB                  0
+#define XTAL_TEST_NOTCXODET_LSB                  0
+#define XTAL_TEST_NOTCXODET_MASK                 0x00000001
+#define XTAL_TEST_NOTCXODET_GET(x)               (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
+#define XTAL_TEST_NOTCXODET_SET(x)               (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
+
+#define QUADRATURE_ADDRESS                       0x00000010
+#define QUADRATURE_OFFSET                        0x00000010
+#define QUADRATURE_ADC_MSB                       5
+#define QUADRATURE_ADC_LSB                       4
+#define QUADRATURE_ADC_MASK                      0x00000030
+#define QUADRATURE_ADC_GET(x)                    (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
+#define QUADRATURE_ADC_SET(x)                    (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
+#define QUADRATURE_SEL_MSB                       2
+#define QUADRATURE_SEL_LSB                       2
+#define QUADRATURE_SEL_MASK                      0x00000004
+#define QUADRATURE_SEL_GET(x)                    (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
+#define QUADRATURE_SEL_SET(x)                    (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
+#define QUADRATURE_DAC_MSB                       1
+#define QUADRATURE_DAC_LSB                       0
+#define QUADRATURE_DAC_MASK                      0x00000003
+#define QUADRATURE_DAC_GET(x)                    (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
+#define QUADRATURE_DAC_SET(x)                    (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
+
+#define PLL_CONTROL_ADDRESS                      0x00000014
+#define PLL_CONTROL_OFFSET                       0x00000014
+#define PLL_CONTROL_DIG_TEST_CLK_MSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_LSB             20
+#define PLL_CONTROL_DIG_TEST_CLK_MASK            0x00100000
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x)          (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x)          (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_LSB             19
+#define PLL_CONTROL_MAC_OVERRIDE_MASK            0x00080000
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x)          (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x)          (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define PLL_CONTROL_NOPWD_MSB                    18
+#define PLL_CONTROL_NOPWD_LSB                    18
+#define PLL_CONTROL_NOPWD_MASK                   0x00040000
+#define PLL_CONTROL_NOPWD_GET(x)                 (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
+#define PLL_CONTROL_NOPWD_SET(x)                 (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
+#define PLL_CONTROL_UPDATING_MSB                 17
+#define PLL_CONTROL_UPDATING_LSB                 17
+#define PLL_CONTROL_UPDATING_MASK                0x00020000
+#define PLL_CONTROL_UPDATING_GET(x)              (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
+#define PLL_CONTROL_UPDATING_SET(x)              (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
+#define PLL_CONTROL_BYPASS_MSB                   16
+#define PLL_CONTROL_BYPASS_LSB                   16
+#define PLL_CONTROL_BYPASS_MASK                  0x00010000
+#define PLL_CONTROL_BYPASS_GET(x)                (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
+#define PLL_CONTROL_BYPASS_SET(x)                (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
+#define PLL_CONTROL_REFDIV_MSB                   15
+#define PLL_CONTROL_REFDIV_LSB                   12
+#define PLL_CONTROL_REFDIV_MASK                  0x0000f000
+#define PLL_CONTROL_REFDIV_GET(x)                (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
+#define PLL_CONTROL_REFDIV_SET(x)                (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
+#define PLL_CONTROL_DIV_MSB                      9
+#define PLL_CONTROL_DIV_LSB                      0
+#define PLL_CONTROL_DIV_MASK                     0x000003ff
+#define PLL_CONTROL_DIV_GET(x)                   (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
+#define PLL_CONTROL_DIV_SET(x)                   (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
+
+#define PLL_SETTLE_ADDRESS                       0x00000018
+#define PLL_SETTLE_OFFSET                        0x00000018
+#define PLL_SETTLE_TIME_MSB                      11
+#define PLL_SETTLE_TIME_LSB                      0
+#define PLL_SETTLE_TIME_MASK                     0x00000fff
+#define PLL_SETTLE_TIME_GET(x)                   (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
+#define PLL_SETTLE_TIME_SET(x)                   (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
+
+#define XTAL_SETTLE_ADDRESS                      0x0000001c
+#define XTAL_SETTLE_OFFSET                       0x0000001c
+#define XTAL_SETTLE_TIME_MSB                     7
+#define XTAL_SETTLE_TIME_LSB                     0
+#define XTAL_SETTLE_TIME_MASK                    0x000000ff
+#define XTAL_SETTLE_TIME_GET(x)                  (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
+#define XTAL_SETTLE_TIME_SET(x)                  (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
+
+#define CPU_CLOCK_ADDRESS                        0x00000020
+#define CPU_CLOCK_OFFSET                         0x00000020
+#define CPU_CLOCK_STANDARD_MSB                   1
+#define CPU_CLOCK_STANDARD_LSB                   0
+#define CPU_CLOCK_STANDARD_MASK                  0x00000003
+#define CPU_CLOCK_STANDARD_GET(x)                (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_SET(x)                (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+
+#define CLOCK_OUT_ADDRESS                        0x00000024
+#define CLOCK_OUT_OFFSET                         0x00000024
+#define CLOCK_OUT_SELECT_MSB                     3
+#define CLOCK_OUT_SELECT_LSB                     0
+#define CLOCK_OUT_SELECT_MASK                    0x0000000f
+#define CLOCK_OUT_SELECT_GET(x)                  (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
+#define CLOCK_OUT_SELECT_SET(x)                  (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
+
+#define CLOCK_CONTROL_ADDRESS                    0x00000028
+#define CLOCK_CONTROL_OFFSET                     0x00000028
+#define CLOCK_CONTROL_LF_CLK32_MSB               2
+#define CLOCK_CONTROL_LF_CLK32_LSB               2
+#define CLOCK_CONTROL_LF_CLK32_MASK              0x00000004
+#define CLOCK_CONTROL_LF_CLK32_GET(x)            (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
+#define CLOCK_CONTROL_LF_CLK32_SET(x)            (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
+#define CLOCK_CONTROL_UART_CLK_MSB               1
+#define CLOCK_CONTROL_UART_CLK_LSB               1
+#define CLOCK_CONTROL_UART_CLK_MASK              0x00000002
+#define CLOCK_CONTROL_UART_CLK_GET(x)            (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
+#define CLOCK_CONTROL_UART_CLK_SET(x)            (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
+#define CLOCK_CONTROL_SI0_CLK_MSB                0
+#define CLOCK_CONTROL_SI0_CLK_LSB                0
+#define CLOCK_CONTROL_SI0_CLK_MASK               0x00000001
+#define CLOCK_CONTROL_SI0_CLK_GET(x)             (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
+#define CLOCK_CONTROL_SI0_CLK_SET(x)             (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define BIAS_OVERRIDE_ADDRESS                    0x0000002c
+#define BIAS_OVERRIDE_OFFSET                     0x0000002c
+#define BIAS_OVERRIDE_ON_MSB                     0
+#define BIAS_OVERRIDE_ON_LSB                     0
+#define BIAS_OVERRIDE_ON_MASK                    0x00000001
+#define BIAS_OVERRIDE_ON_GET(x)                  (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
+#define BIAS_OVERRIDE_ON_SET(x)                  (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
+
+#define WDT_CONTROL_ADDRESS                      0x00000030
+#define WDT_CONTROL_OFFSET                       0x00000030
+#define WDT_CONTROL_ACTION_MSB                   2
+#define WDT_CONTROL_ACTION_LSB                   0
+#define WDT_CONTROL_ACTION_MASK                  0x00000007
+#define WDT_CONTROL_ACTION_GET(x)                (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
+#define WDT_CONTROL_ACTION_SET(x)                (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
+
+#define WDT_STATUS_ADDRESS                       0x00000034
+#define WDT_STATUS_OFFSET                        0x00000034
+#define WDT_STATUS_INTERRUPT_MSB                 0
+#define WDT_STATUS_INTERRUPT_LSB                 0
+#define WDT_STATUS_INTERRUPT_MASK                0x00000001
+#define WDT_STATUS_INTERRUPT_GET(x)              (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
+#define WDT_STATUS_INTERRUPT_SET(x)              (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
+
+#define WDT_ADDRESS                              0x00000038
+#define WDT_OFFSET                               0x00000038
+#define WDT_TARGET_MSB                           21
+#define WDT_TARGET_LSB                           0
+#define WDT_TARGET_MASK                          0x003fffff
+#define WDT_TARGET_GET(x)                        (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
+#define WDT_TARGET_SET(x)                        (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
+
+#define WDT_COUNT_ADDRESS                        0x0000003c
+#define WDT_COUNT_OFFSET                         0x0000003c
+#define WDT_COUNT_VALUE_MSB                      21
+#define WDT_COUNT_VALUE_LSB                      0
+#define WDT_COUNT_VALUE_MASK                     0x003fffff
+#define WDT_COUNT_VALUE_GET(x)                   (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
+#define WDT_COUNT_VALUE_SET(x)                   (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
+
+#define WDT_RESET_ADDRESS                        0x00000040
+#define WDT_RESET_OFFSET                         0x00000040
+#define WDT_RESET_VALUE_MSB                      0
+#define WDT_RESET_VALUE_LSB                      0
+#define WDT_RESET_VALUE_MASK                     0x00000001
+#define WDT_RESET_VALUE_GET(x)                   (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
+#define WDT_RESET_VALUE_SET(x)                   (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
+
+#define INT_STATUS_ADDRESS                       0x00000044
+#define INT_STATUS_OFFSET                        0x00000044
+#define INT_STATUS_RTC_POWER_MSB                 14
+#define INT_STATUS_RTC_POWER_LSB                 14
+#define INT_STATUS_RTC_POWER_MASK                0x00004000
+#define INT_STATUS_RTC_POWER_GET(x)              (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
+#define INT_STATUS_RTC_POWER_SET(x)              (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
+#define INT_STATUS_MAC_MSB                       13
+#define INT_STATUS_MAC_LSB                       13
+#define INT_STATUS_MAC_MASK                      0x00002000
+#define INT_STATUS_MAC_GET(x)                    (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
+#define INT_STATUS_MAC_SET(x)                    (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
+#define INT_STATUS_MAILBOX_MSB                   12
+#define INT_STATUS_MAILBOX_LSB                   12
+#define INT_STATUS_MAILBOX_MASK                  0x00001000
+#define INT_STATUS_MAILBOX_GET(x)                (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
+#define INT_STATUS_MAILBOX_SET(x)                (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
+#define INT_STATUS_RTC_ALARM_MSB                 11
+#define INT_STATUS_RTC_ALARM_LSB                 11
+#define INT_STATUS_RTC_ALARM_MASK                0x00000800
+#define INT_STATUS_RTC_ALARM_GET(x)              (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
+#define INT_STATUS_RTC_ALARM_SET(x)              (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
+#define INT_STATUS_HF_TIMER_MSB                  10
+#define INT_STATUS_HF_TIMER_LSB                  10
+#define INT_STATUS_HF_TIMER_MASK                 0x00000400
+#define INT_STATUS_HF_TIMER_GET(x)               (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
+#define INT_STATUS_HF_TIMER_SET(x)               (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
+#define INT_STATUS_LF_TIMER3_MSB                 9
+#define INT_STATUS_LF_TIMER3_LSB                 9
+#define INT_STATUS_LF_TIMER3_MASK                0x00000200
+#define INT_STATUS_LF_TIMER3_GET(x)              (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
+#define INT_STATUS_LF_TIMER3_SET(x)              (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
+#define INT_STATUS_LF_TIMER2_MSB                 8
+#define INT_STATUS_LF_TIMER2_LSB                 8
+#define INT_STATUS_LF_TIMER2_MASK                0x00000100
+#define INT_STATUS_LF_TIMER2_GET(x)              (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
+#define INT_STATUS_LF_TIMER2_SET(x)              (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
+#define INT_STATUS_LF_TIMER1_MSB                 7
+#define INT_STATUS_LF_TIMER1_LSB                 7
+#define INT_STATUS_LF_TIMER1_MASK                0x00000080
+#define INT_STATUS_LF_TIMER1_GET(x)              (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
+#define INT_STATUS_LF_TIMER1_SET(x)              (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
+#define INT_STATUS_LF_TIMER0_MSB                 6
+#define INT_STATUS_LF_TIMER0_LSB                 6
+#define INT_STATUS_LF_TIMER0_MASK                0x00000040
+#define INT_STATUS_LF_TIMER0_GET(x)              (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
+#define INT_STATUS_LF_TIMER0_SET(x)              (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
+#define INT_STATUS_KEYPAD_MSB                    5
+#define INT_STATUS_KEYPAD_LSB                    5
+#define INT_STATUS_KEYPAD_MASK                   0x00000020
+#define INT_STATUS_KEYPAD_GET(x)                 (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
+#define INT_STATUS_KEYPAD_SET(x)                 (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
+#define INT_STATUS_SI_MSB                        4
+#define INT_STATUS_SI_LSB                        4
+#define INT_STATUS_SI_MASK                       0x00000010
+#define INT_STATUS_SI_GET(x)                     (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
+#define INT_STATUS_SI_SET(x)                     (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
+#define INT_STATUS_GPIO_MSB                      3
+#define INT_STATUS_GPIO_LSB                      3
+#define INT_STATUS_GPIO_MASK                     0x00000008
+#define INT_STATUS_GPIO_GET(x)                   (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
+#define INT_STATUS_GPIO_SET(x)                   (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
+#define INT_STATUS_UART_MSB                      2
+#define INT_STATUS_UART_LSB                      2
+#define INT_STATUS_UART_MASK                     0x00000004
+#define INT_STATUS_UART_GET(x)                   (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
+#define INT_STATUS_UART_SET(x)                   (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
+#define INT_STATUS_ERROR_MSB                     1
+#define INT_STATUS_ERROR_LSB                     1
+#define INT_STATUS_ERROR_MASK                    0x00000002
+#define INT_STATUS_ERROR_GET(x)                  (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
+#define INT_STATUS_ERROR_SET(x)                  (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
+#define INT_STATUS_WDT_INT_MSB                   0
+#define INT_STATUS_WDT_INT_LSB                   0
+#define INT_STATUS_WDT_INT_MASK                  0x00000001
+#define INT_STATUS_WDT_INT_GET(x)                (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
+#define INT_STATUS_WDT_INT_SET(x)                (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
+
+#define LF_TIMER0_ADDRESS                        0x00000048
+#define LF_TIMER0_OFFSET                         0x00000048
+#define LF_TIMER0_TARGET_MSB                     31
+#define LF_TIMER0_TARGET_LSB                     0
+#define LF_TIMER0_TARGET_MASK                    0xffffffff
+#define LF_TIMER0_TARGET_GET(x)                  (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
+#define LF_TIMER0_TARGET_SET(x)                  (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
+
+#define LF_TIMER_COUNT0_ADDRESS                  0x0000004c
+#define LF_TIMER_COUNT0_OFFSET                   0x0000004c
+#define LF_TIMER_COUNT0_VALUE_MSB                31
+#define LF_TIMER_COUNT0_VALUE_LSB                0
+#define LF_TIMER_COUNT0_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT0_VALUE_GET(x)             (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
+#define LF_TIMER_COUNT0_VALUE_SET(x)             (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
+
+#define LF_TIMER_CONTROL0_ADDRESS                0x00000050
+#define LF_TIMER_CONTROL0_OFFSET                 0x00000050
+#define LF_TIMER_CONTROL0_ENABLE_MSB             2
+#define LF_TIMER_CONTROL0_ENABLE_LSB             2
+#define LF_TIMER_CONTROL0_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL0_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL0_RESET_MSB              0
+#define LF_TIMER_CONTROL0_RESET_LSB              0
+#define LF_TIMER_CONTROL0_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL0_RESET_GET(x)           (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
+#define LF_TIMER_CONTROL0_RESET_SET(x)           (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
+
+#define LF_TIMER_STATUS0_ADDRESS                 0x00000054
+#define LF_TIMER_STATUS0_OFFSET                  0x00000054
+#define LF_TIMER_STATUS0_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS0_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define LF_TIMER1_ADDRESS                        0x00000058
+#define LF_TIMER1_OFFSET                         0x00000058
+#define LF_TIMER1_TARGET_MSB                     31
+#define LF_TIMER1_TARGET_LSB                     0
+#define LF_TIMER1_TARGET_MASK                    0xffffffff
+#define LF_TIMER1_TARGET_GET(x)                  (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
+#define LF_TIMER1_TARGET_SET(x)                  (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
+
+#define LF_TIMER_COUNT1_ADDRESS                  0x0000005c
+#define LF_TIMER_COUNT1_OFFSET                   0x0000005c
+#define LF_TIMER_COUNT1_VALUE_MSB                31
+#define LF_TIMER_COUNT1_VALUE_LSB                0
+#define LF_TIMER_COUNT1_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT1_VALUE_GET(x)             (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
+#define LF_TIMER_COUNT1_VALUE_SET(x)             (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
+
+#define LF_TIMER_CONTROL1_ADDRESS                0x00000060
+#define LF_TIMER_CONTROL1_OFFSET                 0x00000060
+#define LF_TIMER_CONTROL1_ENABLE_MSB             2
+#define LF_TIMER_CONTROL1_ENABLE_LSB             2
+#define LF_TIMER_CONTROL1_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL1_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL1_RESET_MSB              0
+#define LF_TIMER_CONTROL1_RESET_LSB              0
+#define LF_TIMER_CONTROL1_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL1_RESET_GET(x)           (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
+#define LF_TIMER_CONTROL1_RESET_SET(x)           (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
+
+#define LF_TIMER_STATUS1_ADDRESS                 0x00000064
+#define LF_TIMER_STATUS1_OFFSET                  0x00000064
+#define LF_TIMER_STATUS1_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS1_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define LF_TIMER2_ADDRESS                        0x00000068
+#define LF_TIMER2_OFFSET                         0x00000068
+#define LF_TIMER2_TARGET_MSB                     31
+#define LF_TIMER2_TARGET_LSB                     0
+#define LF_TIMER2_TARGET_MASK                    0xffffffff
+#define LF_TIMER2_TARGET_GET(x)                  (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
+#define LF_TIMER2_TARGET_SET(x)                  (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
+
+#define LF_TIMER_COUNT2_ADDRESS                  0x0000006c
+#define LF_TIMER_COUNT2_OFFSET                   0x0000006c
+#define LF_TIMER_COUNT2_VALUE_MSB                31
+#define LF_TIMER_COUNT2_VALUE_LSB                0
+#define LF_TIMER_COUNT2_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT2_VALUE_GET(x)             (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
+#define LF_TIMER_COUNT2_VALUE_SET(x)             (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
+
+#define LF_TIMER_CONTROL2_ADDRESS                0x00000070
+#define LF_TIMER_CONTROL2_OFFSET                 0x00000070
+#define LF_TIMER_CONTROL2_ENABLE_MSB             2
+#define LF_TIMER_CONTROL2_ENABLE_LSB             2
+#define LF_TIMER_CONTROL2_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL2_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL2_RESET_MSB              0
+#define LF_TIMER_CONTROL2_RESET_LSB              0
+#define LF_TIMER_CONTROL2_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL2_RESET_GET(x)           (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
+#define LF_TIMER_CONTROL2_RESET_SET(x)           (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
+
+#define LF_TIMER_STATUS2_ADDRESS                 0x00000074
+#define LF_TIMER_STATUS2_OFFSET                  0x00000074
+#define LF_TIMER_STATUS2_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS2_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define LF_TIMER3_ADDRESS                        0x00000078
+#define LF_TIMER3_OFFSET                         0x00000078
+#define LF_TIMER3_TARGET_MSB                     31
+#define LF_TIMER3_TARGET_LSB                     0
+#define LF_TIMER3_TARGET_MASK                    0xffffffff
+#define LF_TIMER3_TARGET_GET(x)                  (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
+#define LF_TIMER3_TARGET_SET(x)                  (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
+
+#define LF_TIMER_COUNT3_ADDRESS                  0x0000007c
+#define LF_TIMER_COUNT3_OFFSET                   0x0000007c
+#define LF_TIMER_COUNT3_VALUE_MSB                31
+#define LF_TIMER_COUNT3_VALUE_LSB                0
+#define LF_TIMER_COUNT3_VALUE_MASK               0xffffffff
+#define LF_TIMER_COUNT3_VALUE_GET(x)             (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
+#define LF_TIMER_COUNT3_VALUE_SET(x)             (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
+
+#define LF_TIMER_CONTROL3_ADDRESS                0x00000080
+#define LF_TIMER_CONTROL3_OFFSET                 0x00000080
+#define LF_TIMER_CONTROL3_ENABLE_MSB             2
+#define LF_TIMER_CONTROL3_ENABLE_LSB             2
+#define LF_TIMER_CONTROL3_ENABLE_MASK            0x00000004
+#define LF_TIMER_CONTROL3_ENABLE_GET(x)          (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x)          (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB       1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK      0x00000002
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)    (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)    (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL3_RESET_MSB              0
+#define LF_TIMER_CONTROL3_RESET_LSB              0
+#define LF_TIMER_CONTROL3_RESET_MASK             0x00000001
+#define LF_TIMER_CONTROL3_RESET_GET(x)           (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
+#define LF_TIMER_CONTROL3_RESET_SET(x)           (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
+
+#define LF_TIMER_STATUS3_ADDRESS                 0x00000084
+#define LF_TIMER_STATUS3_OFFSET                  0x00000084
+#define LF_TIMER_STATUS3_INTERRUPT_MSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_LSB           0
+#define LF_TIMER_STATUS3_INTERRUPT_MASK          0x00000001
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x)        (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x)        (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define HF_TIMER_ADDRESS                         0x00000088
+#define HF_TIMER_OFFSET                          0x00000088
+#define HF_TIMER_TARGET_MSB                      31
+#define HF_TIMER_TARGET_LSB                      12
+#define HF_TIMER_TARGET_MASK                     0xfffff000
+#define HF_TIMER_TARGET_GET(x)                   (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
+#define HF_TIMER_TARGET_SET(x)                   (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
+
+#define HF_TIMER_COUNT_ADDRESS                   0x0000008c
+#define HF_TIMER_COUNT_OFFSET                    0x0000008c
+#define HF_TIMER_COUNT_VALUE_MSB                 31
+#define HF_TIMER_COUNT_VALUE_LSB                 12
+#define HF_TIMER_COUNT_VALUE_MASK                0xfffff000
+#define HF_TIMER_COUNT_VALUE_GET(x)              (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
+#define HF_TIMER_COUNT_VALUE_SET(x)              (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
+
+#define HF_LF_COUNT_ADDRESS                      0x00000090
+#define HF_LF_COUNT_OFFSET                       0x00000090
+#define HF_LF_COUNT_VALUE_MSB                    31
+#define HF_LF_COUNT_VALUE_LSB                    0
+#define HF_LF_COUNT_VALUE_MASK                   0xffffffff
+#define HF_LF_COUNT_VALUE_GET(x)                 (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
+#define HF_LF_COUNT_VALUE_SET(x)                 (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
+
+#define HF_TIMER_CONTROL_ADDRESS                 0x00000094
+#define HF_TIMER_CONTROL_OFFSET                  0x00000094
+#define HF_TIMER_CONTROL_ENABLE_MSB              3
+#define HF_TIMER_CONTROL_ENABLE_LSB              3
+#define HF_TIMER_CONTROL_ENABLE_MASK             0x00000008
+#define HF_TIMER_CONTROL_ENABLE_GET(x)           (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
+#define HF_TIMER_CONTROL_ENABLE_SET(x)           (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
+#define HF_TIMER_CONTROL_ON_MSB                  2
+#define HF_TIMER_CONTROL_ON_LSB                  2
+#define HF_TIMER_CONTROL_ON_MASK                 0x00000004
+#define HF_TIMER_CONTROL_ON_GET(x)               (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
+#define HF_TIMER_CONTROL_ON_SET(x)               (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB        1
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK       0x00000002
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x)     (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x)     (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define HF_TIMER_CONTROL_RESET_MSB               0
+#define HF_TIMER_CONTROL_RESET_LSB               0
+#define HF_TIMER_CONTROL_RESET_MASK              0x00000001
+#define HF_TIMER_CONTROL_RESET_GET(x)            (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
+#define HF_TIMER_CONTROL_RESET_SET(x)            (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
+
+#define HF_TIMER_STATUS_ADDRESS                  0x00000098
+#define HF_TIMER_STATUS_OFFSET                   0x00000098
+#define HF_TIMER_STATUS_INTERRUPT_MSB            0
+#define HF_TIMER_STATUS_INTERRUPT_LSB            0
+#define HF_TIMER_STATUS_INTERRUPT_MASK           0x00000001
+#define HF_TIMER_STATUS_INTERRUPT_GET(x)         (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x)         (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define RTC_CONTROL_ADDRESS                      0x0000009c
+#define RTC_CONTROL_OFFSET                       0x0000009c
+#define RTC_CONTROL_ENABLE_MSB                   2
+#define RTC_CONTROL_ENABLE_LSB                   2
+#define RTC_CONTROL_ENABLE_MASK                  0x00000004
+#define RTC_CONTROL_ENABLE_GET(x)                (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
+#define RTC_CONTROL_ENABLE_SET(x)                (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
+#define RTC_CONTROL_LOAD_RTC_MSB                 1
+#define RTC_CONTROL_LOAD_RTC_LSB                 1
+#define RTC_CONTROL_LOAD_RTC_MASK                0x00000002
+#define RTC_CONTROL_LOAD_RTC_GET(x)              (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
+#define RTC_CONTROL_LOAD_RTC_SET(x)              (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
+#define RTC_CONTROL_LOAD_ALARM_MSB               0
+#define RTC_CONTROL_LOAD_ALARM_LSB               0
+#define RTC_CONTROL_LOAD_ALARM_MASK              0x00000001
+#define RTC_CONTROL_LOAD_ALARM_GET(x)            (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
+#define RTC_CONTROL_LOAD_ALARM_SET(x)            (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define RTC_TIME_ADDRESS                         0x000000a0
+#define RTC_TIME_OFFSET                          0x000000a0
+#define RTC_TIME_WEEK_DAY_MSB                    26
+#define RTC_TIME_WEEK_DAY_LSB                    24
+#define RTC_TIME_WEEK_DAY_MASK                   0x07000000
+#define RTC_TIME_WEEK_DAY_GET(x)                 (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
+#define RTC_TIME_WEEK_DAY_SET(x)                 (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
+#define RTC_TIME_HOUR_MSB                        21
+#define RTC_TIME_HOUR_LSB                        16
+#define RTC_TIME_HOUR_MASK                       0x003f0000
+#define RTC_TIME_HOUR_GET(x)                     (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
+#define RTC_TIME_HOUR_SET(x)                     (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
+#define RTC_TIME_MINUTE_MSB                      14
+#define RTC_TIME_MINUTE_LSB                      8
+#define RTC_TIME_MINUTE_MASK                     0x00007f00
+#define RTC_TIME_MINUTE_GET(x)                   (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
+#define RTC_TIME_MINUTE_SET(x)                   (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
+#define RTC_TIME_SECOND_MSB                      6
+#define RTC_TIME_SECOND_LSB                      0
+#define RTC_TIME_SECOND_MASK                     0x0000007f
+#define RTC_TIME_SECOND_GET(x)                   (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
+#define RTC_TIME_SECOND_SET(x)                   (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
+
+#define RTC_DATE_ADDRESS                         0x000000a4
+#define RTC_DATE_OFFSET                          0x000000a4
+#define RTC_DATE_YEAR_MSB                        23
+#define RTC_DATE_YEAR_LSB                        16
+#define RTC_DATE_YEAR_MASK                       0x00ff0000
+#define RTC_DATE_YEAR_GET(x)                     (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
+#define RTC_DATE_YEAR_SET(x)                     (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
+#define RTC_DATE_MONTH_MSB                       12
+#define RTC_DATE_MONTH_LSB                       8
+#define RTC_DATE_MONTH_MASK                      0x00001f00
+#define RTC_DATE_MONTH_GET(x)                    (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
+#define RTC_DATE_MONTH_SET(x)                    (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
+#define RTC_DATE_MONTH_DAY_MSB                   5
+#define RTC_DATE_MONTH_DAY_LSB                   0
+#define RTC_DATE_MONTH_DAY_MASK                  0x0000003f
+#define RTC_DATE_MONTH_DAY_GET(x)                (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
+#define RTC_DATE_MONTH_DAY_SET(x)                (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_TIME_ADDRESS                     0x000000a8
+#define RTC_SET_TIME_OFFSET                      0x000000a8
+#define RTC_SET_TIME_WEEK_DAY_MSB                26
+#define RTC_SET_TIME_WEEK_DAY_LSB                24
+#define RTC_SET_TIME_WEEK_DAY_MASK               0x07000000
+#define RTC_SET_TIME_WEEK_DAY_GET(x)             (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
+#define RTC_SET_TIME_WEEK_DAY_SET(x)             (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
+#define RTC_SET_TIME_HOUR_MSB                    21
+#define RTC_SET_TIME_HOUR_LSB                    16
+#define RTC_SET_TIME_HOUR_MASK                   0x003f0000
+#define RTC_SET_TIME_HOUR_GET(x)                 (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
+#define RTC_SET_TIME_HOUR_SET(x)                 (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
+#define RTC_SET_TIME_MINUTE_MSB                  14
+#define RTC_SET_TIME_MINUTE_LSB                  8
+#define RTC_SET_TIME_MINUTE_MASK                 0x00007f00
+#define RTC_SET_TIME_MINUTE_GET(x)               (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
+#define RTC_SET_TIME_MINUTE_SET(x)               (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
+#define RTC_SET_TIME_SECOND_MSB                  6
+#define RTC_SET_TIME_SECOND_LSB                  0
+#define RTC_SET_TIME_SECOND_MASK                 0x0000007f
+#define RTC_SET_TIME_SECOND_GET(x)               (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
+#define RTC_SET_TIME_SECOND_SET(x)               (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
+
+#define RTC_SET_DATE_ADDRESS                     0x000000ac
+#define RTC_SET_DATE_OFFSET                      0x000000ac
+#define RTC_SET_DATE_YEAR_MSB                    23
+#define RTC_SET_DATE_YEAR_LSB                    16
+#define RTC_SET_DATE_YEAR_MASK                   0x00ff0000
+#define RTC_SET_DATE_YEAR_GET(x)                 (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
+#define RTC_SET_DATE_YEAR_SET(x)                 (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
+#define RTC_SET_DATE_MONTH_MSB                   12
+#define RTC_SET_DATE_MONTH_LSB                   8
+#define RTC_SET_DATE_MONTH_MASK                  0x00001f00
+#define RTC_SET_DATE_MONTH_GET(x)                (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
+#define RTC_SET_DATE_MONTH_SET(x)                (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
+#define RTC_SET_DATE_MONTH_DAY_MSB               5
+#define RTC_SET_DATE_MONTH_DAY_LSB               0
+#define RTC_SET_DATE_MONTH_DAY_MASK              0x0000003f
+#define RTC_SET_DATE_MONTH_DAY_GET(x)            (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
+#define RTC_SET_DATE_MONTH_DAY_SET(x)            (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_ALARM_ADDRESS                    0x000000b0
+#define RTC_SET_ALARM_OFFSET                     0x000000b0
+#define RTC_SET_ALARM_HOUR_MSB                   21
+#define RTC_SET_ALARM_HOUR_LSB                   16
+#define RTC_SET_ALARM_HOUR_MASK                  0x003f0000
+#define RTC_SET_ALARM_HOUR_GET(x)                (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
+#define RTC_SET_ALARM_HOUR_SET(x)                (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
+#define RTC_SET_ALARM_MINUTE_MSB                 14
+#define RTC_SET_ALARM_MINUTE_LSB                 8
+#define RTC_SET_ALARM_MINUTE_MASK                0x00007f00
+#define RTC_SET_ALARM_MINUTE_GET(x)              (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
+#define RTC_SET_ALARM_MINUTE_SET(x)              (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
+#define RTC_SET_ALARM_SECOND_MSB                 6
+#define RTC_SET_ALARM_SECOND_LSB                 0
+#define RTC_SET_ALARM_SECOND_MASK                0x0000007f
+#define RTC_SET_ALARM_SECOND_GET(x)              (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
+#define RTC_SET_ALARM_SECOND_SET(x)              (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
+
+#define RTC_CONFIG_ADDRESS                       0x000000b4
+#define RTC_CONFIG_OFFSET                        0x000000b4
+#define RTC_CONFIG_BCD_MSB                       2
+#define RTC_CONFIG_BCD_LSB                       2
+#define RTC_CONFIG_BCD_MASK                      0x00000004
+#define RTC_CONFIG_BCD_GET(x)                    (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
+#define RTC_CONFIG_BCD_SET(x)                    (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
+#define RTC_CONFIG_TWELVE_HOUR_MSB               1
+#define RTC_CONFIG_TWELVE_HOUR_LSB               1
+#define RTC_CONFIG_TWELVE_HOUR_MASK              0x00000002
+#define RTC_CONFIG_TWELVE_HOUR_GET(x)            (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x)            (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
+#define RTC_CONFIG_DSE_MSB                       0
+#define RTC_CONFIG_DSE_LSB                       0
+#define RTC_CONFIG_DSE_MASK                      0x00000001
+#define RTC_CONFIG_DSE_GET(x)                    (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
+#define RTC_CONFIG_DSE_SET(x)                    (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
+
+#define RTC_ALARM_STATUS_ADDRESS                 0x000000b8
+#define RTC_ALARM_STATUS_OFFSET                  0x000000b8
+#define RTC_ALARM_STATUS_ENABLE_MSB              1
+#define RTC_ALARM_STATUS_ENABLE_LSB              1
+#define RTC_ALARM_STATUS_ENABLE_MASK             0x00000002
+#define RTC_ALARM_STATUS_ENABLE_GET(x)           (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
+#define RTC_ALARM_STATUS_ENABLE_SET(x)           (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_LSB           0
+#define RTC_ALARM_STATUS_INTERRUPT_MASK          0x00000001
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x)        (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x)        (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define UART_WAKEUP_ADDRESS                      0x000000bc
+#define UART_WAKEUP_OFFSET                       0x000000bc
+#define UART_WAKEUP_ENABLE_MSB                   0
+#define UART_WAKEUP_ENABLE_LSB                   0
+#define UART_WAKEUP_ENABLE_MASK                  0x00000001
+#define UART_WAKEUP_ENABLE_GET(x)                (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
+#define UART_WAKEUP_ENABLE_SET(x)                (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
+
+#define RESET_CAUSE_ADDRESS                      0x000000c0
+#define RESET_CAUSE_OFFSET                       0x000000c0
+#define RESET_CAUSE_LAST_MSB                     2
+#define RESET_CAUSE_LAST_LSB                     0
+#define RESET_CAUSE_LAST_MASK                    0x00000007
+#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#define SYSTEM_SLEEP_ADDRESS                     0x000000c4
+#define SYSTEM_SLEEP_OFFSET                      0x000000c4
+#define SYSTEM_SLEEP_HOST_IF_MSB                 4
+#define SYSTEM_SLEEP_HOST_IF_LSB                 4
+#define SYSTEM_SLEEP_HOST_IF_MASK                0x00000010
+#define SYSTEM_SLEEP_HOST_IF_GET(x)              (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
+#define SYSTEM_SLEEP_HOST_IF_SET(x)              (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
+#define SYSTEM_SLEEP_MBOX_MSB                    3
+#define SYSTEM_SLEEP_MBOX_LSB                    3
+#define SYSTEM_SLEEP_MBOX_MASK                   0x00000008
+#define SYSTEM_SLEEP_MBOX_GET(x)                 (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
+#define SYSTEM_SLEEP_MBOX_SET(x)                 (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
+#define SYSTEM_SLEEP_MAC_IF_MSB                  2
+#define SYSTEM_SLEEP_MAC_IF_LSB                  2
+#define SYSTEM_SLEEP_MAC_IF_MASK                 0x00000004
+#define SYSTEM_SLEEP_MAC_IF_GET(x)               (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
+#define SYSTEM_SLEEP_MAC_IF_SET(x)               (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
+#define SYSTEM_SLEEP_LIGHT_MSB                   1
+#define SYSTEM_SLEEP_LIGHT_LSB                   1
+#define SYSTEM_SLEEP_LIGHT_MASK                  0x00000002
+#define SYSTEM_SLEEP_LIGHT_GET(x)                (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
+#define SYSTEM_SLEEP_LIGHT_SET(x)                (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
+#define SYSTEM_SLEEP_DISABLE_MSB                 0
+#define SYSTEM_SLEEP_DISABLE_LSB                 0
+#define SYSTEM_SLEEP_DISABLE_MASK                0x00000001
+#define SYSTEM_SLEEP_DISABLE_GET(x)              (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SDIO_WRAPPER_ADDRESS                     0x000000c8
+#define SDIO_WRAPPER_OFFSET                      0x000000c8
+#define SDIO_WRAPPER_SLEEP_MSB                   3
+#define SDIO_WRAPPER_SLEEP_LSB                   3
+#define SDIO_WRAPPER_SLEEP_MASK                  0x00000008
+#define SDIO_WRAPPER_SLEEP_GET(x)                (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
+#define SDIO_WRAPPER_SLEEP_SET(x)                (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
+#define SDIO_WRAPPER_WAKEUP_MSB                  2
+#define SDIO_WRAPPER_WAKEUP_LSB                  2
+#define SDIO_WRAPPER_WAKEUP_MASK                 0x00000004
+#define SDIO_WRAPPER_WAKEUP_GET(x)               (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
+#define SDIO_WRAPPER_WAKEUP_SET(x)               (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
+#define SDIO_WRAPPER_SOC_ON_MSB                  1
+#define SDIO_WRAPPER_SOC_ON_LSB                  1
+#define SDIO_WRAPPER_SOC_ON_MASK                 0x00000002
+#define SDIO_WRAPPER_SOC_ON_GET(x)               (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
+#define SDIO_WRAPPER_SOC_ON_SET(x)               (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
+#define SDIO_WRAPPER_ON_MSB                      0
+#define SDIO_WRAPPER_ON_LSB                      0
+#define SDIO_WRAPPER_ON_MASK                     0x00000001
+#define SDIO_WRAPPER_ON_GET(x)                   (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
+#define SDIO_WRAPPER_ON_SET(x)                   (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
+
+#define MAC_SLEEP_CONTROL_ADDRESS                0x000000cc
+#define MAC_SLEEP_CONTROL_OFFSET                 0x000000cc
+#define MAC_SLEEP_CONTROL_ENABLE_MSB             1
+#define MAC_SLEEP_CONTROL_ENABLE_LSB             0
+#define MAC_SLEEP_CONTROL_ENABLE_MASK            0x00000003
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x)          (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x)          (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define KEEP_AWAKE_ADDRESS                       0x000000d0
+#define KEEP_AWAKE_OFFSET                        0x000000d0
+#define KEEP_AWAKE_COUNT_MSB                     7
+#define KEEP_AWAKE_COUNT_LSB                     0
+#define KEEP_AWAKE_COUNT_MASK                    0x000000ff
+#define KEEP_AWAKE_COUNT_GET(x)                  (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
+#define KEEP_AWAKE_COUNT_SET(x)                  (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
+
+#define LPO_CAL_TIME_ADDRESS                     0x000000d4
+#define LPO_CAL_TIME_OFFSET                      0x000000d4
+#define LPO_CAL_TIME_LENGTH_MSB                  13
+#define LPO_CAL_TIME_LENGTH_LSB                  0
+#define LPO_CAL_TIME_LENGTH_MASK                 0x00003fff
+#define LPO_CAL_TIME_LENGTH_GET(x)               (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
+#define LPO_CAL_TIME_LENGTH_SET(x)               (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
+
+#define LPO_INIT_DIVIDEND_INT_ADDRESS            0x000000d8
+#define LPO_INIT_DIVIDEND_INT_OFFSET             0x000000d8
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB          23
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB          0
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK         0x00ffffff
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x)       (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x)       (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS       0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET        0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB     10
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB     0
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK    0x000007ff
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)  (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)  (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define LPO_CAL_ADDRESS                          0x000000e0
+#define LPO_CAL_OFFSET                           0x000000e0
+#define LPO_CAL_ENABLE_MSB                       20
+#define LPO_CAL_ENABLE_LSB                       20
+#define LPO_CAL_ENABLE_MASK                      0x00100000
+#define LPO_CAL_ENABLE_GET(x)                    (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_SET(x)                    (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define LPO_CAL_COUNT_MSB                        19
+#define LPO_CAL_COUNT_LSB                        0
+#define LPO_CAL_COUNT_MASK                       0x000fffff
+#define LPO_CAL_COUNT_GET(x)                     (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
+#define LPO_CAL_COUNT_SET(x)                     (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
+
+#define LPO_CAL_TEST_CONTROL_ADDRESS             0x000000e4
+#define LPO_CAL_TEST_CONTROL_OFFSET              0x000000e4
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB          5
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK         0x00000020
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x)       (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x)       (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB      4
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB      0
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK     0x0000001f
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)   (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)   (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define LPO_CAL_TEST_STATUS_ADDRESS              0x000000e8
+#define LPO_CAL_TEST_STATUS_OFFSET               0x000000e8
+#define LPO_CAL_TEST_STATUS_READY_MSB            16
+#define LPO_CAL_TEST_STATUS_READY_LSB            16
+#define LPO_CAL_TEST_STATUS_READY_MASK           0x00010000
+#define LPO_CAL_TEST_STATUS_READY_GET(x)         (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
+#define LPO_CAL_TEST_STATUS_READY_SET(x)         (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB            15
+#define LPO_CAL_TEST_STATUS_COUNT_LSB            0
+#define LPO_CAL_TEST_STATUS_COUNT_MASK           0x0000ffff
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x)         (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x)         (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define CHIP_ID_ADDRESS                          0x000000ec
+#define CHIP_ID_OFFSET                           0x000000ec
+#define CHIP_ID_DEVICE_ID_MSB                    31
+#define CHIP_ID_DEVICE_ID_LSB                    16
+#define CHIP_ID_DEVICE_ID_MASK                   0xffff0000
+#define CHIP_ID_DEVICE_ID_GET(x)                 (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
+#define CHIP_ID_DEVICE_ID_SET(x)                 (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
+#define CHIP_ID_CONFIG_ID_MSB                    15
+#define CHIP_ID_CONFIG_ID_LSB                    4
+#define CHIP_ID_CONFIG_ID_MASK                   0x0000fff0
+#define CHIP_ID_CONFIG_ID_GET(x)                 (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
+#define CHIP_ID_CONFIG_ID_SET(x)                 (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
+#define CHIP_ID_VERSION_ID_MSB                   3
+#define CHIP_ID_VERSION_ID_LSB                   0
+#define CHIP_ID_VERSION_ID_MASK                  0x0000000f
+#define CHIP_ID_VERSION_ID_GET(x)                (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
+#define CHIP_ID_VERSION_ID_SET(x)                (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
+
+#define DERIVED_RTC_CLK_ADDRESS                  0x000000f0
+#define DERIVED_RTC_CLK_OFFSET                   0x000000f0
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB   20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK  0x00100000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB      18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK     0x00040000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)   (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)   (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define DERIVED_RTC_CLK_FORCE_MSB                17
+#define DERIVED_RTC_CLK_FORCE_LSB                16
+#define DERIVED_RTC_CLK_FORCE_MASK               0x00030000
+#define DERIVED_RTC_CLK_FORCE_GET(x)             (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
+#define DERIVED_RTC_CLK_FORCE_SET(x)             (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
+#define DERIVED_RTC_CLK_PERIOD_MSB               15
+#define DERIVED_RTC_CLK_PERIOD_LSB               1
+#define DERIVED_RTC_CLK_PERIOD_MASK              0x0000fffe
+#define DERIVED_RTC_CLK_PERIOD_GET(x)            (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
+#define DERIVED_RTC_CLK_PERIOD_SET(x)            (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS               0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET                0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB  19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB  0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS               0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET                0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB          15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB          0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK         0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x)       (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x)       (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS                0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET                 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB            19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB            0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK           0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x)         (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x)         (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS                 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET                  0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB           31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB           0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS                 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET                  0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB           31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB           0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS                 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET                  0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK            0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x)          (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x)          (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK            0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x)          (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x)          (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define MAC_PCU_SLP_BEACON_ADDRESS               0x0000010c
+#define MAC_PCU_SLP_BEACON_OFFSET                0x0000010c
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB     23
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB     0
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK    0x00ffffff
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x)  (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x)  (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
+
+#define POWER_REG_ADDRESS                        0x00000110
+#define POWER_REG_OFFSET                         0x00000110
+#define POWER_REG_VLVL_MSB                       11
+#define POWER_REG_VLVL_LSB                       8
+#define POWER_REG_VLVL_MASK                      0x00000f00
+#define POWER_REG_VLVL_GET(x)                    (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
+#define POWER_REG_VLVL_SET(x)                    (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
+#define POWER_REG_CPU_INT_ENABLE_MSB             7
+#define POWER_REG_CPU_INT_ENABLE_LSB             7
+#define POWER_REG_CPU_INT_ENABLE_MASK            0x00000080
+#define POWER_REG_CPU_INT_ENABLE_GET(x)          (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
+#define POWER_REG_CPU_INT_ENABLE_SET(x)          (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
+#define POWER_REG_WLAN_ISO_DIS_MSB               6
+#define POWER_REG_WLAN_ISO_DIS_LSB               6
+#define POWER_REG_WLAN_ISO_DIS_MASK              0x00000040
+#define POWER_REG_WLAN_ISO_DIS_GET(x)            (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
+#define POWER_REG_WLAN_ISO_DIS_SET(x)            (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
+#define POWER_REG_WLAN_ISO_CNTL_MSB              5
+#define POWER_REG_WLAN_ISO_CNTL_LSB              5
+#define POWER_REG_WLAN_ISO_CNTL_MASK             0x00000020
+#define POWER_REG_WLAN_ISO_CNTL_GET(x)           (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x)           (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
+#define POWER_REG_RADIO_PWD_EN_MSB               4
+#define POWER_REG_RADIO_PWD_EN_LSB               4
+#define POWER_REG_RADIO_PWD_EN_MASK              0x00000010
+#define POWER_REG_RADIO_PWD_EN_GET(x)            (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
+#define POWER_REG_RADIO_PWD_EN_SET(x)            (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
+#define POWER_REG_SOC_SCALE_EN_MSB               3
+#define POWER_REG_SOC_SCALE_EN_LSB               3
+#define POWER_REG_SOC_SCALE_EN_MASK              0x00000008
+#define POWER_REG_SOC_SCALE_EN_GET(x)            (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
+#define POWER_REG_SOC_SCALE_EN_SET(x)            (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
+#define POWER_REG_WLAN_SCALE_EN_MSB              2
+#define POWER_REG_WLAN_SCALE_EN_LSB              2
+#define POWER_REG_WLAN_SCALE_EN_MASK             0x00000004
+#define POWER_REG_WLAN_SCALE_EN_GET(x)           (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
+#define POWER_REG_WLAN_SCALE_EN_SET(x)           (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
+#define POWER_REG_WLAN_PWD_EN_MSB                1
+#define POWER_REG_WLAN_PWD_EN_LSB                1
+#define POWER_REG_WLAN_PWD_EN_MASK               0x00000002
+#define POWER_REG_WLAN_PWD_EN_GET(x)             (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
+#define POWER_REG_WLAN_PWD_EN_SET(x)             (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
+#define POWER_REG_POWER_EN_MSB                   0
+#define POWER_REG_POWER_EN_LSB                   0
+#define POWER_REG_POWER_EN_MASK                  0x00000001
+#define POWER_REG_POWER_EN_GET(x)                (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
+#define POWER_REG_POWER_EN_SET(x)                (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
+
+#define CORE_CLK_CTRL_ADDRESS                    0x00000114
+#define CORE_CLK_CTRL_OFFSET                     0x00000114
+#define CORE_CLK_CTRL_DIV_MSB                    2
+#define CORE_CLK_CTRL_DIV_LSB                    0
+#define CORE_CLK_CTRL_DIV_MASK                   0x00000007
+#define CORE_CLK_CTRL_DIV_GET(x)                 (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
+#define CORE_CLK_CTRL_DIV_SET(x)                 (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
+
+#define SDIO_SETUP_CIRCUIT_ADDRESS               0x00000120
+#define SDIO_SETUP_CIRCUIT_OFFSET                0x00000120
+#define SDIO_SETUP_CIRCUIT_VECTOR_MSB            7
+#define SDIO_SETUP_CIRCUIT_VECTOR_LSB            0
+#define SDIO_SETUP_CIRCUIT_VECTOR_MASK           0x000000ff
+#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x)         (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
+#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x)         (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define SDIO_SETUP_CONFIG_ADDRESS                0x00000140
+#define SDIO_SETUP_CONFIG_OFFSET                 0x00000140
+#define SDIO_SETUP_CONFIG_ENABLE_MSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_LSB             1
+#define SDIO_SETUP_CONFIG_ENABLE_MASK            0x00000002
+#define SDIO_SETUP_CONFIG_ENABLE_GET(x)          (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
+#define SDIO_SETUP_CONFIG_ENABLE_SET(x)          (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
+#define SDIO_SETUP_CONFIG_CLEAR_MSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_LSB              0
+#define SDIO_SETUP_CONFIG_CLEAR_MASK             0x00000001
+#define SDIO_SETUP_CONFIG_CLEAR_GET(x)           (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
+#define SDIO_SETUP_CONFIG_CLEAR_SET(x)           (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CONFIG_ADDRESS                 0x00000144
+#define CPU_SETUP_CONFIG_OFFSET                  0x00000144
+#define CPU_SETUP_CONFIG_ENABLE_MSB              1
+#define CPU_SETUP_CONFIG_ENABLE_LSB              1
+#define CPU_SETUP_CONFIG_ENABLE_MASK             0x00000002
+#define CPU_SETUP_CONFIG_ENABLE_GET(x)           (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
+#define CPU_SETUP_CONFIG_ENABLE_SET(x)           (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
+#define CPU_SETUP_CONFIG_CLEAR_MSB               0
+#define CPU_SETUP_CONFIG_CLEAR_LSB               0
+#define CPU_SETUP_CONFIG_CLEAR_MASK              0x00000001
+#define CPU_SETUP_CONFIG_CLEAR_GET(x)            (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
+#define CPU_SETUP_CONFIG_CLEAR_SET(x)            (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CIRCUIT_ADDRESS                0x00000160
+#define CPU_SETUP_CIRCUIT_OFFSET                 0x00000160
+#define CPU_SETUP_CIRCUIT_VECTOR_MSB             7
+#define CPU_SETUP_CIRCUIT_VECTOR_LSB             0
+#define CPU_SETUP_CIRCUIT_VECTOR_MASK            0x000000ff
+#define CPU_SETUP_CIRCUIT_VECTOR_GET(x)          (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
+#define CPU_SETUP_CIRCUIT_VECTOR_SET(x)          (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define BB_SETUP_CONFIG_ADDRESS                  0x00000180
+#define BB_SETUP_CONFIG_OFFSET                   0x00000180
+#define BB_SETUP_CONFIG_ENABLE_MSB               1
+#define BB_SETUP_CONFIG_ENABLE_LSB               1
+#define BB_SETUP_CONFIG_ENABLE_MASK              0x00000002
+#define BB_SETUP_CONFIG_ENABLE_GET(x)            (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
+#define BB_SETUP_CONFIG_ENABLE_SET(x)            (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
+#define BB_SETUP_CONFIG_CLEAR_MSB                0
+#define BB_SETUP_CONFIG_CLEAR_LSB                0
+#define BB_SETUP_CONFIG_CLEAR_MASK               0x00000001
+#define BB_SETUP_CONFIG_CLEAR_GET(x)             (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
+#define BB_SETUP_CONFIG_CLEAR_SET(x)             (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
+
+#define BB_SETUP_CIRCUIT_ADDRESS                 0x000001a0
+#define BB_SETUP_CIRCUIT_OFFSET                  0x000001a0
+#define BB_SETUP_CIRCUIT_VECTOR_MSB              7
+#define BB_SETUP_CIRCUIT_VECTOR_LSB              0
+#define BB_SETUP_CIRCUIT_VECTOR_MASK             0x000000ff
+#define BB_SETUP_CIRCUIT_VECTOR_GET(x)           (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
+#define BB_SETUP_CIRCUIT_VECTOR_SET(x)           (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define GPIO_WAKEUP_CONTROL_ADDRESS              0x000001c0
+#define GPIO_WAKEUP_CONTROL_OFFSET               0x000001c0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB           0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK          0x00000001
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x)        (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x)        (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_reg_reg_s {
+  volatile unsigned int reset_control;
+  volatile unsigned int xtal_control;
+  volatile unsigned int tcxo_detect;
+  volatile unsigned int xtal_test;
+  volatile unsigned int quadrature;
+  volatile unsigned int pll_control;
+  volatile unsigned int pll_settle;
+  volatile unsigned int xtal_settle;
+  volatile unsigned int cpu_clock;
+  volatile unsigned int clock_out;
+  volatile unsigned int clock_control;
+  volatile unsigned int bias_override;
+  volatile unsigned int wdt_control;
+  volatile unsigned int wdt_status;
+  volatile unsigned int wdt;
+  volatile unsigned int wdt_count;
+  volatile unsigned int wdt_reset;
+  volatile unsigned int int_status;
+  volatile unsigned int lf_timer0;
+  volatile unsigned int lf_timer_count0;
+  volatile unsigned int lf_timer_control0;
+  volatile unsigned int lf_timer_status0;
+  volatile unsigned int lf_timer1;
+  volatile unsigned int lf_timer_count1;
+  volatile unsigned int lf_timer_control1;
+  volatile unsigned int lf_timer_status1;
+  volatile unsigned int lf_timer2;
+  volatile unsigned int lf_timer_count2;
+  volatile unsigned int lf_timer_control2;
+  volatile unsigned int lf_timer_status2;
+  volatile unsigned int lf_timer3;
+  volatile unsigned int lf_timer_count3;
+  volatile unsigned int lf_timer_control3;
+  volatile unsigned int lf_timer_status3;
+  volatile unsigned int hf_timer;
+  volatile unsigned int hf_timer_count;
+  volatile unsigned int hf_lf_count;
+  volatile unsigned int hf_timer_control;
+  volatile unsigned int hf_timer_status;
+  volatile unsigned int rtc_control;
+  volatile unsigned int rtc_time;
+  volatile unsigned int rtc_date;
+  volatile unsigned int rtc_set_time;
+  volatile unsigned int rtc_set_date;
+  volatile unsigned int rtc_set_alarm;
+  volatile unsigned int rtc_config;
+  volatile unsigned int rtc_alarm_status;
+  volatile unsigned int uart_wakeup;
+  volatile unsigned int reset_cause;
+  volatile unsigned int system_sleep;
+  volatile unsigned int sdio_wrapper;
+  volatile unsigned int mac_sleep_control;
+  volatile unsigned int keep_awake;
+  volatile unsigned int lpo_cal_time;
+  volatile unsigned int lpo_init_dividend_int;
+  volatile unsigned int lpo_init_dividend_fraction;
+  volatile unsigned int lpo_cal;
+  volatile unsigned int lpo_cal_test_control;
+  volatile unsigned int lpo_cal_test_status;
+  volatile unsigned int chip_id;
+  volatile unsigned int derived_rtc_clk;
+  volatile unsigned int mac_pcu_slp32_mode;
+  volatile unsigned int mac_pcu_slp32_wake;
+  volatile unsigned int mac_pcu_slp32_inc;
+  volatile unsigned int mac_pcu_slp_mib1;
+  volatile unsigned int mac_pcu_slp_mib2;
+  volatile unsigned int mac_pcu_slp_mib3;
+  volatile unsigned int mac_pcu_slp_beacon;
+  volatile unsigned int power_reg;
+  volatile unsigned int core_clk_ctrl;
+  unsigned char pad0[8]; /* pad to 0x120 */
+  volatile unsigned int sdio_setup_circuit[8];
+  volatile unsigned int sdio_setup_config;
+  volatile unsigned int cpu_setup_config;
+  unsigned char pad1[24]; /* pad to 0x160 */
+  volatile unsigned int cpu_setup_circuit[8];
+  volatile unsigned int bb_setup_config;
+  unsigned char pad2[28]; /* pad to 0x1a0 */
+  volatile unsigned int bb_setup_circuit[8];
+  volatile unsigned int gpio_wakeup_control;
+} rtc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS                        0x00000000
+#define SI_CONFIG_OFFSET                         0x00000000
+#define SI_CONFIG_ERR_INT_MSB                    19
+#define SI_CONFIG_ERR_INT_LSB                    19
+#define SI_CONFIG_ERR_INT_MASK                   0x00080000
+#define SI_CONFIG_ERR_INT_GET(x)                 (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x)                 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x)           (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x)           (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB                        16
+#define SI_CONFIG_I2C_LSB                        16
+#define SI_CONFIG_I2C_MASK                       0x00010000
+#define SI_CONFIG_I2C_GET(x)                     (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x)                     (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB                 7
+#define SI_CONFIG_POS_SAMPLE_LSB                 7
+#define SI_CONFIG_POS_SAMPLE_MASK                0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x)              (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x)              (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB                  6
+#define SI_CONFIG_POS_DRIVE_LSB                  6
+#define SI_CONFIG_POS_DRIVE_MASK                 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x)               (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x)               (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB              5
+#define SI_CONFIG_INACTIVE_DATA_LSB              5
+#define SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x)           (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x)           (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB               4
+#define SI_CONFIG_INACTIVE_CLK_LSB               4
+#define SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x)            (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x)            (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB                    3
+#define SI_CONFIG_DIVIDER_LSB                    0
+#define SI_CONFIG_DIVIDER_MASK                   0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x)                 (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x)                 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS                            0x00000004
+#define SI_CS_OFFSET                             0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB           13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB           11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK          0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x)        (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x)        (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB                       10
+#define SI_CS_DONE_ERR_LSB                       10
+#define SI_CS_DONE_ERR_MASK                      0x00000400
+#define SI_CS_DONE_ERR_GET(x)                    (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x)                    (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB                       9
+#define SI_CS_DONE_INT_LSB                       9
+#define SI_CS_DONE_INT_MASK                      0x00000200
+#define SI_CS_DONE_INT_GET(x)                    (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x)                    (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB                          8
+#define SI_CS_START_LSB                          8
+#define SI_CS_START_MASK                         0x00000100
+#define SI_CS_START_GET(x)                       (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x)                       (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB                         7
+#define SI_CS_RX_CNT_LSB                         4
+#define SI_CS_RX_CNT_MASK                        0x000000f0
+#define SI_CS_RX_CNT_GET(x)                      (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x)                      (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB                         3
+#define SI_CS_TX_CNT_LSB                         0
+#define SI_CS_TX_CNT_MASK                        0x0000000f
+#define SI_CS_TX_CNT_GET(x)                      (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x)                      (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS                      0x00000008
+#define SI_TX_DATA0_OFFSET                       0x00000008
+#define SI_TX_DATA0_DATA3_MSB                    31
+#define SI_TX_DATA0_DATA3_LSB                    24
+#define SI_TX_DATA0_DATA3_MASK                   0xff000000
+#define SI_TX_DATA0_DATA3_GET(x)                 (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x)                 (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB                    23
+#define SI_TX_DATA0_DATA2_LSB                    16
+#define SI_TX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x)                 (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x)                 (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB                    15
+#define SI_TX_DATA0_DATA1_LSB                    8
+#define SI_TX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x)                 (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x)                 (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB                    7
+#define SI_TX_DATA0_DATA0_LSB                    0
+#define SI_TX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x)                 (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x)                 (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS                      0x0000000c
+#define SI_TX_DATA1_OFFSET                       0x0000000c
+#define SI_TX_DATA1_DATA7_MSB                    31
+#define SI_TX_DATA1_DATA7_LSB                    24
+#define SI_TX_DATA1_DATA7_MASK                   0xff000000
+#define SI_TX_DATA1_DATA7_GET(x)                 (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x)                 (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB                    23
+#define SI_TX_DATA1_DATA6_LSB                    16
+#define SI_TX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x)                 (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x)                 (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB                    15
+#define SI_TX_DATA1_DATA5_LSB                    8
+#define SI_TX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x)                 (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x)                 (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB                    7
+#define SI_TX_DATA1_DATA4_LSB                    0
+#define SI_TX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x)                 (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x)                 (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS                      0x00000010
+#define SI_RX_DATA0_OFFSET                       0x00000010
+#define SI_RX_DATA0_DATA3_MSB                    31
+#define SI_RX_DATA0_DATA3_LSB                    24
+#define SI_RX_DATA0_DATA3_MASK                   0xff000000
+#define SI_RX_DATA0_DATA3_GET(x)                 (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x)                 (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB                    23
+#define SI_RX_DATA0_DATA2_LSB                    16
+#define SI_RX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x)                 (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x)                 (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB                    15
+#define SI_RX_DATA0_DATA1_LSB                    8
+#define SI_RX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x)                 (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x)                 (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB                    7
+#define SI_RX_DATA0_DATA0_LSB                    0
+#define SI_RX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x)                 (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x)                 (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS                      0x00000014
+#define SI_RX_DATA1_OFFSET                       0x00000014
+#define SI_RX_DATA1_DATA7_MSB                    31
+#define SI_RX_DATA1_DATA7_LSB                    24
+#define SI_RX_DATA1_DATA7_MASK                   0xff000000
+#define SI_RX_DATA1_DATA7_GET(x)                 (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x)                 (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB                    23
+#define SI_RX_DATA1_DATA6_LSB                    16
+#define SI_RX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x)                 (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x)                 (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB                    15
+#define SI_RX_DATA1_DATA5_LSB                    8
+#define SI_RX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x)                 (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x)                 (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB                    7
+#define SI_RX_DATA1_DATA4_LSB                    0
+#define SI_RX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x)                 (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x)                 (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+  volatile unsigned int si_config;
+  volatile unsigned int si_cs;
+  volatile unsigned int si_tx_data0;
+  volatile unsigned int si_tx_data1;
+  volatile unsigned int si_rx_data0;
+  volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h
new file mode 100644
index 000000000000..db573106dcd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h
@@ -0,0 +1,346 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define RBR_ADDRESS                              0x00000000
+#define RBR_OFFSET                               0x00000000
+#define RBR_RBR_MSB                              7
+#define RBR_RBR_LSB                              0
+#define RBR_RBR_MASK                             0x000000ff
+#define RBR_RBR_GET(x)                           (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
+#define RBR_RBR_SET(x)                           (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
+
+#define THR_ADDRESS                              0x00000000
+#define THR_OFFSET                               0x00000000
+#define THR_THR_MSB                              7
+#define THR_THR_LSB                              0
+#define THR_THR_MASK                             0x000000ff
+#define THR_THR_GET(x)                           (((x) & THR_THR_MASK) >> THR_THR_LSB)
+#define THR_THR_SET(x)                           (((x) << THR_THR_LSB) & THR_THR_MASK)
+
+#define DLL_ADDRESS                              0x00000000
+#define DLL_OFFSET                               0x00000000
+#define DLL_DLL_MSB                              7
+#define DLL_DLL_LSB                              0
+#define DLL_DLL_MASK                             0x000000ff
+#define DLL_DLL_GET(x)                           (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
+#define DLL_DLL_SET(x)                           (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
+
+#define DLH_ADDRESS                              0x00000004
+#define DLH_OFFSET                               0x00000004
+#define DLH_DLH_MSB                              7
+#define DLH_DLH_LSB                              0
+#define DLH_DLH_MASK                             0x000000ff
+#define DLH_DLH_GET(x)                           (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
+#define DLH_DLH_SET(x)                           (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
+
+#define IER_ADDRESS                              0x00000004
+#define IER_OFFSET                               0x00000004
+#define IER_EDDSI_MSB                            3
+#define IER_EDDSI_LSB                            3
+#define IER_EDDSI_MASK                           0x00000008
+#define IER_EDDSI_GET(x)                         (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
+#define IER_EDDSI_SET(x)                         (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
+#define IER_ELSI_MSB                             2
+#define IER_ELSI_LSB                             2
+#define IER_ELSI_MASK                            0x00000004
+#define IER_ELSI_GET(x)                          (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
+#define IER_ELSI_SET(x)                          (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
+#define IER_ETBEI_MSB                            1
+#define IER_ETBEI_LSB                            1
+#define IER_ETBEI_MASK                           0x00000002
+#define IER_ETBEI_GET(x)                         (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
+#define IER_ETBEI_SET(x)                         (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
+#define IER_ERBFI_MSB                            0
+#define IER_ERBFI_LSB                            0
+#define IER_ERBFI_MASK                           0x00000001
+#define IER_ERBFI_GET(x)                         (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
+#define IER_ERBFI_SET(x)                         (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
+
+#define IIR_ADDRESS                              0x00000008
+#define IIR_OFFSET                               0x00000008
+#define IIR_FIFO_STATUS_MSB                      7
+#define IIR_FIFO_STATUS_LSB                      6
+#define IIR_FIFO_STATUS_MASK                     0x000000c0
+#define IIR_FIFO_STATUS_GET(x)                   (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
+#define IIR_FIFO_STATUS_SET(x)                   (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
+#define IIR_IID_MSB                              3
+#define IIR_IID_LSB                              0
+#define IIR_IID_MASK                             0x0000000f
+#define IIR_IID_GET(x)                           (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
+#define IIR_IID_SET(x)                           (((x) << IIR_IID_LSB) & IIR_IID_MASK)
+
+#define FCR_ADDRESS                              0x00000008
+#define FCR_OFFSET                               0x00000008
+#define FCR_RCVR_TRIG_MSB                        7
+#define FCR_RCVR_TRIG_LSB                        6
+#define FCR_RCVR_TRIG_MASK                       0x000000c0
+#define FCR_RCVR_TRIG_GET(x)                     (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
+#define FCR_RCVR_TRIG_SET(x)                     (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
+#define FCR_DMA_MODE_MSB                         3
+#define FCR_DMA_MODE_LSB                         3
+#define FCR_DMA_MODE_MASK                        0x00000008
+#define FCR_DMA_MODE_GET(x)                      (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
+#define FCR_DMA_MODE_SET(x)                      (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
+#define FCR_XMIT_FIFO_RST_MSB                    2
+#define FCR_XMIT_FIFO_RST_LSB                    2
+#define FCR_XMIT_FIFO_RST_MASK                   0x00000004
+#define FCR_XMIT_FIFO_RST_GET(x)                 (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
+#define FCR_XMIT_FIFO_RST_SET(x)                 (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
+#define FCR_RCVR_FIFO_RST_MSB                    1
+#define FCR_RCVR_FIFO_RST_LSB                    1
+#define FCR_RCVR_FIFO_RST_MASK                   0x00000002
+#define FCR_RCVR_FIFO_RST_GET(x)                 (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
+#define FCR_RCVR_FIFO_RST_SET(x)                 (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
+#define FCR_FIFO_EN_MSB                          0
+#define FCR_FIFO_EN_LSB                          0
+#define FCR_FIFO_EN_MASK                         0x00000001
+#define FCR_FIFO_EN_GET(x)                       (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
+#define FCR_FIFO_EN_SET(x)                       (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
+
+#define LCR_ADDRESS                              0x0000000c
+#define LCR_OFFSET                               0x0000000c
+#define LCR_DLAB_MSB                             7
+#define LCR_DLAB_LSB                             7
+#define LCR_DLAB_MASK                            0x00000080
+#define LCR_DLAB_GET(x)                          (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
+#define LCR_DLAB_SET(x)                          (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
+#define LCR_BREAK_MSB                            6
+#define LCR_BREAK_LSB                            6
+#define LCR_BREAK_MASK                           0x00000040
+#define LCR_BREAK_GET(x)                         (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
+#define LCR_BREAK_SET(x)                         (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
+#define LCR_EPS_MSB                              4
+#define LCR_EPS_LSB                              4
+#define LCR_EPS_MASK                             0x00000010
+#define LCR_EPS_GET(x)                           (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
+#define LCR_EPS_SET(x)                           (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
+#define LCR_PEN_MSB                              3
+#define LCR_PEN_LSB                              3
+#define LCR_PEN_MASK                             0x00000008
+#define LCR_PEN_GET(x)                           (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
+#define LCR_PEN_SET(x)                           (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
+#define LCR_STOP_MSB                             2
+#define LCR_STOP_LSB                             2
+#define LCR_STOP_MASK                            0x00000004
+#define LCR_STOP_GET(x)                          (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
+#define LCR_STOP_SET(x)                          (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
+#define LCR_CLS_MSB                              1
+#define LCR_CLS_LSB                              0
+#define LCR_CLS_MASK                             0x00000003
+#define LCR_CLS_GET(x)                           (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
+#define LCR_CLS_SET(x)                           (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
+
+#define MCR_ADDRESS                              0x00000010
+#define MCR_OFFSET                               0x00000010
+#define MCR_LOOPBACK_MSB                         5
+#define MCR_LOOPBACK_LSB                         5
+#define MCR_LOOPBACK_MASK                        0x00000020
+#define MCR_LOOPBACK_GET(x)                      (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
+#define MCR_LOOPBACK_SET(x)                      (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
+#define MCR_OUT2_MSB                             3
+#define MCR_OUT2_LSB                             3
+#define MCR_OUT2_MASK                            0x00000008
+#define MCR_OUT2_GET(x)                          (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
+#define MCR_OUT2_SET(x)                          (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
+#define MCR_OUT1_MSB                             2
+#define MCR_OUT1_LSB                             2
+#define MCR_OUT1_MASK                            0x00000004
+#define MCR_OUT1_GET(x)                          (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
+#define MCR_OUT1_SET(x)                          (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
+#define MCR_RTS_MSB                              1
+#define MCR_RTS_LSB                              1
+#define MCR_RTS_MASK                             0x00000002
+#define MCR_RTS_GET(x)                           (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
+#define MCR_RTS_SET(x)                           (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
+#define MCR_DTR_MSB                              0
+#define MCR_DTR_LSB                              0
+#define MCR_DTR_MASK                             0x00000001
+#define MCR_DTR_GET(x)                           (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
+#define MCR_DTR_SET(x)                           (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
+
+#define LSR_ADDRESS                              0x00000014
+#define LSR_OFFSET                               0x00000014
+#define LSR_FERR_MSB                             7
+#define LSR_FERR_LSB                             7
+#define LSR_FERR_MASK                            0x00000080
+#define LSR_FERR_GET(x)                          (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
+#define LSR_FERR_SET(x)                          (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
+#define LSR_TEMT_MSB                             6
+#define LSR_TEMT_LSB                             6
+#define LSR_TEMT_MASK                            0x00000040
+#define LSR_TEMT_GET(x)                          (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
+#define LSR_TEMT_SET(x)                          (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
+#define LSR_THRE_MSB                             5
+#define LSR_THRE_LSB                             5
+#define LSR_THRE_MASK                            0x00000020
+#define LSR_THRE_GET(x)                          (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
+#define LSR_THRE_SET(x)                          (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
+#define LSR_BI_MSB                               4
+#define LSR_BI_LSB                               4
+#define LSR_BI_MASK                              0x00000010
+#define LSR_BI_GET(x)                            (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
+#define LSR_BI_SET(x)                            (((x) << LSR_BI_LSB) & LSR_BI_MASK)
+#define LSR_FE_MSB                               3
+#define LSR_FE_LSB                               3
+#define LSR_FE_MASK                              0x00000008
+#define LSR_FE_GET(x)                            (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
+#define LSR_FE_SET(x)                            (((x) << LSR_FE_LSB) & LSR_FE_MASK)
+#define LSR_PE_MSB                               2
+#define LSR_PE_LSB                               2
+#define LSR_PE_MASK                              0x00000004
+#define LSR_PE_GET(x)                            (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
+#define LSR_PE_SET(x)                            (((x) << LSR_PE_LSB) & LSR_PE_MASK)
+#define LSR_OE_MSB                               1
+#define LSR_OE_LSB                               1
+#define LSR_OE_MASK                              0x00000002
+#define LSR_OE_GET(x)                            (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
+#define LSR_OE_SET(x)                            (((x) << LSR_OE_LSB) & LSR_OE_MASK)
+#define LSR_DR_MSB                               0
+#define LSR_DR_LSB                               0
+#define LSR_DR_MASK                              0x00000001
+#define LSR_DR_GET(x)                            (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
+#define LSR_DR_SET(x)                            (((x) << LSR_DR_LSB) & LSR_DR_MASK)
+
+#define MSR_ADDRESS                              0x00000018
+#define MSR_OFFSET                               0x00000018
+#define MSR_DCD_MSB                              7
+#define MSR_DCD_LSB                              7
+#define MSR_DCD_MASK                             0x00000080
+#define MSR_DCD_GET(x)                           (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
+#define MSR_DCD_SET(x)                           (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
+#define MSR_RI_MSB                               6
+#define MSR_RI_LSB                               6
+#define MSR_RI_MASK                              0x00000040
+#define MSR_RI_GET(x)                            (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
+#define MSR_RI_SET(x)                            (((x) << MSR_RI_LSB) & MSR_RI_MASK)
+#define MSR_DSR_MSB                              5
+#define MSR_DSR_LSB                              5
+#define MSR_DSR_MASK                             0x00000020
+#define MSR_DSR_GET(x)                           (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
+#define MSR_DSR_SET(x)                           (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
+#define MSR_CTS_MSB                              4
+#define MSR_CTS_LSB                              4
+#define MSR_CTS_MASK                             0x00000010
+#define MSR_CTS_GET(x)                           (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
+#define MSR_CTS_SET(x)                           (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
+#define MSR_DDCD_MSB                             3
+#define MSR_DDCD_LSB                             3
+#define MSR_DDCD_MASK                            0x00000008
+#define MSR_DDCD_GET(x)                          (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
+#define MSR_DDCD_SET(x)                          (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
+#define MSR_TERI_MSB                             2
+#define MSR_TERI_LSB                             2
+#define MSR_TERI_MASK                            0x00000004
+#define MSR_TERI_GET(x)                          (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
+#define MSR_TERI_SET(x)                          (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
+#define MSR_DDSR_MSB                             1
+#define MSR_DDSR_LSB                             1
+#define MSR_DDSR_MASK                            0x00000002
+#define MSR_DDSR_GET(x)                          (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
+#define MSR_DDSR_SET(x)                          (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
+#define MSR_DCTS_MSB                             0
+#define MSR_DCTS_LSB                             0
+#define MSR_DCTS_MASK                            0x00000001
+#define MSR_DCTS_GET(x)                          (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
+#define MSR_DCTS_SET(x)                          (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
+
+#define SCR_ADDRESS                              0x0000001c
+#define SCR_OFFSET                               0x0000001c
+#define SCR_SCR_MSB                              7
+#define SCR_SCR_LSB                              0
+#define SCR_SCR_MASK                             0x000000ff
+#define SCR_SCR_GET(x)                           (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
+#define SCR_SCR_SET(x)                           (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
+
+#define SRBR_ADDRESS                             0x00000020
+#define SRBR_OFFSET                              0x00000020
+#define SRBR_SRBR_MSB                            7
+#define SRBR_SRBR_LSB                            0
+#define SRBR_SRBR_MASK                           0x000000ff
+#define SRBR_SRBR_GET(x)                         (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
+#define SRBR_SRBR_SET(x)                         (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
+
+#define SIIR_ADDRESS                             0x00000028
+#define SIIR_OFFSET                              0x00000028
+#define SIIR_SIIR_MSB                            7
+#define SIIR_SIIR_LSB                            0
+#define SIIR_SIIR_MASK                           0x000000ff
+#define SIIR_SIIR_GET(x)                         (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
+#define SIIR_SIIR_SET(x)                         (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
+
+#define MWR_ADDRESS                              0x0000002c
+#define MWR_OFFSET                               0x0000002c
+#define MWR_MWR_MSB                              31
+#define MWR_MWR_LSB                              0
+#define MWR_MWR_MASK                             0xffffffff
+#define MWR_MWR_GET(x)                           (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
+#define MWR_MWR_SET(x)                           (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
+
+#define SLSR_ADDRESS                             0x00000034
+#define SLSR_OFFSET                              0x00000034
+#define SLSR_SLSR_MSB                            7
+#define SLSR_SLSR_LSB                            0
+#define SLSR_SLSR_MASK                           0x000000ff
+#define SLSR_SLSR_GET(x)                         (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
+#define SLSR_SLSR_SET(x)                         (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
+
+#define SMSR_ADDRESS                             0x00000038
+#define SMSR_OFFSET                              0x00000038
+#define SMSR_SMSR_MSB                            7
+#define SMSR_SMSR_LSB                            0
+#define SMSR_SMSR_MASK                           0x000000ff
+#define SMSR_SMSR_GET(x)                         (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
+#define SMSR_SMSR_SET(x)                         (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
+
+#define MRR_ADDRESS                              0x0000003c
+#define MRR_OFFSET                               0x0000003c
+#define MRR_MRR_MSB                              31
+#define MRR_MRR_LSB                              0
+#define MRR_MRR_MASK                             0xffffffff
+#define MRR_MRR_GET(x)                           (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
+#define MRR_MRR_SET(x)                           (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+  volatile unsigned int rbr;
+  volatile unsigned int dlh;
+  volatile unsigned int iir;
+  volatile unsigned int lcr;
+  volatile unsigned int mcr;
+  volatile unsigned int lsr;
+  volatile unsigned int msr;
+  volatile unsigned int scr;
+  volatile unsigned int srbr;
+  unsigned char pad0[4]; /* pad to 0x28 */
+  volatile unsigned int siir;
+  volatile unsigned int mwr;
+  unsigned char pad1[4]; /* pad to 0x34 */
+  volatile unsigned int slsr;
+  volatile unsigned int smsr;
+  volatile unsigned int mrr;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h
new file mode 100644
index 000000000000..0c15ebfaeaa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h
@@ -0,0 +1,95 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_REG_REG_H_
+#define _VMC_REG_REG_H_
+
+#define MC_TCAM_VALID_ADDRESS                    0x00000000
+#define MC_TCAM_VALID_OFFSET                     0x00000000
+#define MC_TCAM_VALID_BIT_MSB                    0
+#define MC_TCAM_VALID_BIT_LSB                    0
+#define MC_TCAM_VALID_BIT_MASK                   0x00000001
+#define MC_TCAM_VALID_BIT_GET(x)                 (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
+#define MC_TCAM_VALID_BIT_SET(x)                 (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
+
+#define MC_TCAM_MASK_ADDRESS                     0x00000080
+#define MC_TCAM_MASK_OFFSET                      0x00000080
+#define MC_TCAM_MASK_SIZE_MSB                    2
+#define MC_TCAM_MASK_SIZE_LSB                    0
+#define MC_TCAM_MASK_SIZE_MASK                   0x00000007
+#define MC_TCAM_MASK_SIZE_GET(x)                 (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
+#define MC_TCAM_MASK_SIZE_SET(x)                 (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
+
+#define MC_TCAM_COMPARE_ADDRESS                  0x00000100
+#define MC_TCAM_COMPARE_OFFSET                   0x00000100
+#define MC_TCAM_COMPARE_KEY_MSB                  21
+#define MC_TCAM_COMPARE_KEY_LSB                  5
+#define MC_TCAM_COMPARE_KEY_MASK                 0x003fffe0
+#define MC_TCAM_COMPARE_KEY_GET(x)               (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
+#define MC_TCAM_COMPARE_KEY_SET(x)               (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
+
+#define MC_TCAM_TARGET_ADDRESS                   0x00000180
+#define MC_TCAM_TARGET_OFFSET                    0x00000180
+#define MC_TCAM_TARGET_ADDR_MSB                  21
+#define MC_TCAM_TARGET_ADDR_LSB                  5
+#define MC_TCAM_TARGET_ADDR_MASK                 0x003fffe0
+#define MC_TCAM_TARGET_ADDR_GET(x)               (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
+#define MC_TCAM_TARGET_ADDR_SET(x)               (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
+
+#define ADDR_ERROR_CONTROL_ADDRESS               0x00000200
+#define ADDR_ERROR_CONTROL_OFFSET                0x00000200
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB       1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK      0x00000002
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)    (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)    (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define ADDR_ERROR_CONTROL_ENABLE_MSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_LSB            0
+#define ADDR_ERROR_CONTROL_ENABLE_MASK           0x00000001
+#define ADDR_ERROR_CONTROL_ENABLE_GET(x)         (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_ENABLE_SET(x)         (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define ADDR_ERROR_STATUS_ADDRESS                0x00000204
+#define ADDR_ERROR_STATUS_OFFSET                 0x00000204
+#define ADDR_ERROR_STATUS_WRITE_MSB              25
+#define ADDR_ERROR_STATUS_WRITE_LSB              25
+#define ADDR_ERROR_STATUS_WRITE_MASK             0x02000000
+#define ADDR_ERROR_STATUS_WRITE_GET(x)           (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
+#define ADDR_ERROR_STATUS_WRITE_SET(x)           (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
+#define ADDR_ERROR_STATUS_ADDRESS_MSB            24
+#define ADDR_ERROR_STATUS_ADDRESS_LSB            0
+#define ADDR_ERROR_STATUS_ADDRESS_MASK           0x01ffffff
+#define ADDR_ERROR_STATUS_ADDRESS_GET(x)         (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define ADDR_ERROR_STATUS_ADDRESS_SET(x)         (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_reg_reg_s {
+  volatile unsigned int mc_tcam_valid[32];
+  volatile unsigned int mc_tcam_mask[32];
+  volatile unsigned int mc_tcam_compare[32];
+  volatile unsigned int mc_tcam_target[32];
+  volatile unsigned int addr_error_control;
+  volatile unsigned int addr_error_status;
+} vmc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h
new file mode 100644
index 000000000000..20194688df1d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h
@@ -0,0 +1,3287 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _ANALOG_INTF_ARES_REG_REG_H_
+#define _ANALOG_INTF_ARES_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS                                                                0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET                                                                 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB                                                               3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB                                                               1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK                                                     0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB                                                                6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB                                                                4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK                                                      0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x)                                     (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x)                                     (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB                                                                9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB                                                                7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK                                                      0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x)                                     (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x)                                     (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB                                                           12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB                                                           10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK                                                  0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x)                                (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x)                                (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB                                                             15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB                                                             13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK                                                    0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x)                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x)                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB                                                              18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK                                                     0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x)                                   (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x)                                   (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB                                                              21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB                                                              19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK                                                     0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x)                                   (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x)                                   (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB                                                               24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB                                                               22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK                                                      0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x)                                    (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x)                                    (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB                                                             27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB                                                             25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK                                                    0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x)                                  (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x)                                  (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB                                                              30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB                                                              28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK                                                     0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x)                                   (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x)                                   (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK                                                          0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS                                                                0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET                                                                 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB                                                                        3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB                                                                        1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK                                                              0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x)                                             (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x)                                             (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB                                                                    6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB                                                                    4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK                                                          0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x)                                         (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x)                                         (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK                                                        0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB                                                             10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB                                                              8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK                                                    0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x)                                   (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x)                                   (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB                                                              13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB                                                              11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK                                                     0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB                                                              14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK                                                     0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x)                                   (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x)                                   (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB                                                             19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB                                                             17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK                                                    0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x)                                  (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x)                                  (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB                                                              22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB                                                              20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK                                                     0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x)                                   (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x)                                   (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB                                                              25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB                                                              23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK                                                     0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x)                                   (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x)                                   (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB                                                             28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB                                                             26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK                                                    0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x)                                  (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x)                                  (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB                                                                31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB                                                                29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK                                                       0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS                                                           0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET                                                            0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK                                                        0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK                                                  0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x)                                 (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x)                                 (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB                                                              3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB                                                              2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK                                                    0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x)                                   (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x)                                   (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB                                                              5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB                                                              4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK                                                    0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x)                                   (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x)                                   (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK                                               0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK                                                     0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x)                                    (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x)                                    (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK                                                    0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x)                                   (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x)                                   (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK                                                    0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x)                                   (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x)                                   (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK                                                    0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB                                                             12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB                                                             11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK                                                    0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x)                                  (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x)                                  (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK                                               0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x)                             (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x)                             (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK                                                     0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x)                                   (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x)                                   (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK                                                     0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x)                                   (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x)                                   (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK                                                    0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x)                                  (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x)                                  (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK                                                    0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB                                                        19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB                                                        18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK                                               0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x)                             (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x)                             (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB                                                        22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB                                                        20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK                                               0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x)                             (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x)                             (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB                                                        25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB                                                        23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK                                               0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x)                             (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x)                             (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB                                                        27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB                                                        26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK                                               0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB                                                        30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB                                                        28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK                                               0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x)                             (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x)                             (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK                                                  0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x)                                (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x)                                (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS                                                                  0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET                                                                   0x0000000c
+#define PHY_ANALOG_RXRF_AGC_SPARE_MSB                                                                         5
+#define PHY_ANALOG_RXRF_AGC_SPARE_LSB                                                                         0
+#define PHY_ANALOG_RXRF_AGC_SPARE_MASK                                                               0x0000003f
+#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x)                                              (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x)                                              (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB                                                                 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB                                                                 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK                                                       0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x)                                      (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x)                                      (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB                                                             14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB                                                              9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK                                                    0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x)                                   (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x)                                   (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB                                                              18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB                                                              15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK                                                     0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x)                                   (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x)                                   (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB                                                             24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB                                                             19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK                                                    0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x)                                  (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x)                                  (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB                                                              28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB                                                              25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK                                                     0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x)                                   (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x)                                   (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK                                                         0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK                                                          0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK                                                        0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x)                                      (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x)                                      (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS                                                                     0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET                                                                      0x00000040
+#define PHY_ANALOG_TXRF1_DCAS2G_MSB                                                                           2
+#define PHY_ANALOG_TXRF1_DCAS2G_LSB                                                                           0
+#define PHY_ANALOG_TXRF1_DCAS2G_MASK                                                                 0x00000007
+#define PHY_ANALOG_TXRF1_DCAS2G_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF1_DCAS2G_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB                                                                      5
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB                                                                      3
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK                                                            0x00000038
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x)                                           (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x)                                           (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB                                                                         8
+#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB                                                                         6
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK                                                               0x000001c0
+#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x)                                              (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x)                                              (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB                                                                        11
+#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB                                                                         9
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK                                                               0x00000e00
+#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x)                                              (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x)                                              (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB                                                                        14
+#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB                                                                        12
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK                                                               0x00007000
+#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x)                                             (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x)                                             (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF1_DB2G_MSB                                                                            17
+#define PHY_ANALOG_TXRF1_DB2G_LSB                                                                            15
+#define PHY_ANALOG_TXRF1_DB2G_MASK                                                                   0x00038000
+#define PHY_ANALOG_TXRF1_DB2G_GET(x)                                                 (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF1_DB2G_SET(x)                                                 (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB                                                                         18
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB                                                                         18
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK                                                                0x00040000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x)                                              (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x)                                              (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB                                                                          19
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB                                                                          19
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK                                                                 0x00080000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x)                                               (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x)                                               (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB                                                                         20
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB                                                                         20
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK                                                                0x00100000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x)                                              (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x)                                              (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLO2G_MSB                                                                          21
+#define PHY_ANALOG_TXRF1_PDLO2G_LSB                                                                          21
+#define PHY_ANALOG_TXRF1_PDLO2G_MASK                                                                 0x00200000
+#define PHY_ANALOG_TXRF1_PDLO2G_GET(x)                                               (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLO2G_SET(x)                                               (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK                                                          0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x)                                        (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x)                                        (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK                                                          0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x)                                        (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x)                                        (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB                                                                       30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB                                                                       24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK                                                              0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x)                                            (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x)                                            (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS                                                                     0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET                                                                      0x00000044
+#define PHY_ANALOG_TXRF2_SPARE2_MSB                                                                           0
+#define PHY_ANALOG_TXRF2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_TXRF2_SPARE2_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF2_SPARE2_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF2_SPARE2_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF2_D3B5G_MSB                                                                            3
+#define PHY_ANALOG_TXRF2_D3B5G_LSB                                                                            1
+#define PHY_ANALOG_TXRF2_D3B5G_MASK                                                                  0x0000000e
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x)                                                 (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x)                                                 (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB                                                                            6
+#define PHY_ANALOG_TXRF2_D4B5G_LSB                                                                            4
+#define PHY_ANALOG_TXRF2_D4B5G_MASK                                                                  0x00000070
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x)                                                 (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x)                                                 (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB                                                                         10
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB                                                                          7
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK                                                                0x00000780
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x)                                               (((x) & 0x00000780) >> 7)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x)                                               (((x) << 7) & 0x00000780)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB                                                                         11
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB                                                                         11
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK                                                                0x00000800
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x)                                              (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x)                                              (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB                                                                       12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB                                                                       12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK                                                              0x00001000
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x)                                            (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x)                                            (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB                                                                       13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB                                                                       13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK                                                              0x00002000
+#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x)                                            (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x)                                            (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB                                                                   14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB                                                                   14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK                                                          0x00004000
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB                                                                   15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB                                                                   15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK                                                          0x00008000
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x)                                        (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x)                                        (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB                                                                      19
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB                                                                      16
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK                                                             0x000f0000
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x)                                           (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x)                                           (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB                                                                      23
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB                                                                      20
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK                                                             0x00f00000
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x)                                           (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x)                                           (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB                                                                      27
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB                                                                      24
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK                                                             0x0f000000
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x)                                           (((x) & 0x0f000000) >> 24)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x)                                           (((x) << 24) & 0x0f000000)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB                                                                   28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB                                                                   28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK                                                          0x10000000
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x)                                        (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x)                                        (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB                                                                          31
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB                                                                          29
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK                                                                 0xe0000000
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x)                                               (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x)                                               (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS                                                                     0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET                                                                      0x00000048
+#define PHY_ANALOG_TXRF3_SPARE3_MSB                                                                          22
+#define PHY_ANALOG_TXRF3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_TXRF3_SPARE3_MASK                                                                 0x007fffff
+#define PHY_ANALOG_TXRF3_SPARE3_GET(x)                                                (((x) & 0x007fffff) >> 0)
+#define PHY_ANALOG_TXRF3_SPARE3_SET(x)                                                (((x) << 0) & 0x007fffff)
+#define PHY_ANALOG_TXRF3_CAS5G_MSB                                                                           25
+#define PHY_ANALOG_TXRF3_CAS5G_LSB                                                                           23
+#define PHY_ANALOG_TXRF3_CAS5G_MASK                                                                  0x03800000
+#define PHY_ANALOG_TXRF3_CAS5G_GET(x)                                                (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_CAS5G_SET(x)                                                (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB                                                                            28
+#define PHY_ANALOG_TXRF3_OB5G_LSB                                                                            26
+#define PHY_ANALOG_TXRF3_OB5G_MASK                                                                   0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x)                                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x)                                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB                                                                           31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB                                                                           29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK                                                                  0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x)                                                (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x)                                                (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS                                                                     0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET                                                                      0x0000004c
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB                                                                       2
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB                                                                       0
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK                                                             0x00000007
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x)                                            (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x)                                            (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB                                                                       5
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB                                                                       3
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK                                                             0x00000038
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x)                                            (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x)                                            (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB                                                                      8
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB                                                                      6
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK                                                            0x000001c0
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x)                                           (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x)                                           (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB                                                                     11
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB                                                                      9
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK                                                            0x00000e00
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x)                                           (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x)                                           (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB                                                                     14
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB                                                                     12
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK                                                            0x00007000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x)                                          (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x)                                          (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB                                                                       17
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB                                                                       15
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK                                                              0x00038000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x)                                            (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x)                                            (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF4_FILTR2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF4_FILTR2G_LSB                                                                         18
+#define PHY_ANALOG_TXRF4_FILTR2G_MASK                                                                0x000c0000
+#define PHY_ANALOG_TXRF4_FILTR2G_GET(x)                                              (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF4_FILTR2G_SET(x)                                              (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB                                                                       20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK                                                              0x00100000
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB                                                                       21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB                                                                       21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK                                                              0x00200000
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF4_PDFB2G_MSB                                                                          22
+#define PHY_ANALOG_TXRF4_PDFB2G_LSB                                                                          22
+#define PHY_ANALOG_TXRF4_PDFB2G_MASK                                                                 0x00400000
+#define PHY_ANALOG_TXRF4_PDFB2G_GET(x)                                               (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF4_PDFB2G_SET(x)                                               (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF4_RDIV5G_MSB                                                                          24
+#define PHY_ANALOG_TXRF4_RDIV5G_LSB                                                                          23
+#define PHY_ANALOG_TXRF4_RDIV5G_MASK                                                                 0x01800000
+#define PHY_ANALOG_TXRF4_RDIV5G_GET(x)                                               (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_TXRF4_RDIV5G_SET(x)                                               (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB                                                                        27
+#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB                                                                        25
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK                                                               0x0e000000
+#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB                                                                     28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB                                                                     28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK                                                            0x10000000
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x)                                          (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x)                                          (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF4_RDIV2G_MSB                                                                          30
+#define PHY_ANALOG_TXRF4_RDIV2G_LSB                                                                          29
+#define PHY_ANALOG_TXRF4_RDIV2G_MASK                                                                 0x60000000
+#define PHY_ANALOG_TXRF4_RDIV2G_GET(x)                                               (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_TXRF4_RDIV2G_SET(x)                                               (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB                                                                     31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB                                                                     31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK                                                            0x80000000
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS                                                                     0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET                                                                      0x00000050
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB                                                                           0
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB                                                                           0
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB                                                                           1
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB                                                                           1
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK                                                                 0x00000002
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x)                                                (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB                                                                          4
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB                                                                          2
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK                                                                0x0000001c
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x)                                               (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x)                                               (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB                                                                          7
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB                                                                          5
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK                                                                0x000000e0
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x)                                               (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x)                                               (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB                                                                       9
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB                                                                       8
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK                                                             0x00000300
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x)                                            (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x)                                            (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB                                                                      11
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB                                                                      10
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK                                                             0x00000c00
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x)                                           (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x)                                           (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB                                                                      13
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB                                                                      12
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK                                                             0x00003000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x)                                           (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x)                                           (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB                                                                      15
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB                                                                      14
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK                                                             0x0000c000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB                                                                      17
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB                                                                      16
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK                                                             0x00030000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x)                                           (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x)                                           (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB                                                                      19
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB                                                                      18
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK                                                             0x000c0000
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x)                                           (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x)                                           (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB                                                                      22
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB                                                                      20
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK                                                             0x00700000
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x)                                           (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x)                                           (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB                                                                      25
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB                                                                      23
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK                                                             0x03800000
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x)                                           (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x)                                           (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB                                                                      28
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB                                                                      26
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK                                                             0x1c000000
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB                                                                      31
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB                                                                      29
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK                                                             0xe0000000
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x)                                           (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x)                                           (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS                                                                     0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET                                                                      0x00000054
+#define PHY_ANALOG_TXRF6_SPARE6_MSB                                                                           0
+#define PHY_ANALOG_TXRF6_SPARE6_LSB                                                                           0
+#define PHY_ANALOG_TXRF6_SPARE6_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF6_SPARE6_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_SPARE6_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB                                                                       1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB                                                                       1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK                                                             0x00000002
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x)                                            (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB                                                                  7
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB                                                                  2
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK                                                        0x000000fc
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x)                                       (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB                                                                      10
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB                                                                       8
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK                                                             0x00000700
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x)                                            (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x)                                            (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB                                                                11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB                                                                11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK                                                       0x00000800
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x)                                     (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x)                                     (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB                                                               15
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB                                                               12
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK                                                      0x0000f000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x)                                    (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x)                                    (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB                                                                    18
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB                                                                    16
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK                                                           0x00070000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x)                                         (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x)                                         (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB                                                                        21
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB                                                                        19
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK                                                               0x00380000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x)                                             (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x)                                             (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB                                                                     22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB                                                                     22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK                                                            0x00400000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB                                                                       23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB                                                                       23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK                                                              0x00800000
+#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF6_OFFSET2G_MSB                                                                        30
+#define PHY_ANALOG_TXRF6_OFFSET2G_LSB                                                                        24
+#define PHY_ANALOG_TXRF6_OFFSET2G_MASK                                                               0x7f000000
+#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x)                                             (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x)                                             (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS                                                                     0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET                                                                      0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB                                                                           1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB                                                                           0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB                                                                     7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB                                                                     2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB                                                                    13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB                                                                     8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB                                                                    19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB                                                                    14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB                                                                    25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB                                                                    20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB                                                                    31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB                                                                    26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS                                                                     0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET                                                                      0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB                                                                           1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB                                                                           0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB                                                                     7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB                                                                     2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB                                                                    13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB                                                                     8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB                                                                    19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB                                                                    14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB                                                                    25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB                                                                    20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB                                                                    31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB                                                                    26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS                                                                     0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET                                                                      0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB                                                                           1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB                                                                           0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB                                                                    7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB                                                                    2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK                                                          0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x)                                         (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x)                                         (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB                                                                   13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB                                                                    8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK                                                          0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x)                                         (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x)                                         (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB                                                                   19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB                                                                   14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK                                                          0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x)                                        (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x)                                        (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB                                                                   25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB                                                                   20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK                                                          0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x)                                        (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x)                                        (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB                                                                   31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB                                                                   26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK                                                          0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x)                                        (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x)                                        (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS                                                                    0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET                                                                     0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB                                                                        12
+#define PHY_ANALOG_TXRF10_SPARE10_LSB                                                                         0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK                                                               0x00001fff
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x)                                              (((x) & 0x00001fff) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x)                                              (((x) << 0) & 0x00001fff)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB                                                                 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB                                                                 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK                                                        0x00002000
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x)                                      (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x)                                      (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB                                                                     16
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB                                                                     14
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK                                                            0x0001c000
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x)                                          (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x)                                          (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB                                                                     19
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB                                                                     17
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK                                                            0x000e0000
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x)                                          (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x)                                          (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB                                                                 26
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB                                                                 20
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK                                                        0x07f00000
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x)                                      (((x) & 0x07f00000) >> 20)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x)                                      (((x) << 20) & 0x07f00000)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB                                                                      29
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB                                                                      27
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK                                                             0x38000000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x)                                           (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x)                                           (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB                                                                     30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB                                                                     30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK                                                            0x40000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB                                                                  31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB                                                                  31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK                                                         0x80000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x)                                       (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x)                                       (((x) << 31) & 0x80000000)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS                                                                    0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET                                                                     0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB                                                                         1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB                                                                         0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK                                                               0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB                                                               4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB                                                               2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK                                                     0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x)                                    (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x)                                    (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB                                                                7
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB                                                                5
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK                                                      0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB                                                                   10
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB                                                                    8
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK                                                          0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB                                                              13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB                                                              11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK                                                     0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB                                                               16
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB                                                               14
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK                                                      0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x)                                    (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x)                                    (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB                                                                    19
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB                                                                    17
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK                                                           0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x)                                         (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x)                                         (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB                                                                  22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB                                                                  20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK                                                         0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB                                                                  25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB                                                                  23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB                                                               28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB                                                               26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK                                                      0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x)                                    (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x)                                    (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB                                                                   29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK                                                          0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS                                                                    0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET                                                                     0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB                                                                       7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB                                                                       0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK                                                             0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x)                                            (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB                                                                      15
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB                                                                       8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK                                                             0x0000ff00
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x)                                            (((x) & 0x0000ff00) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x)                                            (((x) << 8) & 0x0000ff00)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB                                                                       19
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB                                                                       16
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK                                                              0x000f0000
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x)                                            (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x)                                            (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB                                                                       22
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK                                                              0x00700000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x)                                            (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x)                                            (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB                                                                    25
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB                                                                    23
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK                                                           0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x)                                         (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x)                                         (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB                                                                  28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB                                                                  26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK                                                         0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB                                                                  31
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB                                                                  29
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK                                                         0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS                                                                    0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET                                                                     0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB                                                                   2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB                                                                   0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK                                                         0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x)                                        (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x)                                        (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB                                                                     5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB                                                                     3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK                                                           0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x)                                          (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x)                                          (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK                                                 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x)                                (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x)                                (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK                                                        0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK                                                       0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x)                                      (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x)                                      (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK                                                       0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x)                                      (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x)                                      (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK                                                            0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB                                                                        15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB                                                                        13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK                                                               0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x)                                             (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x)                                             (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK                                                            0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x)                                          (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x)                                          (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB                                                                     18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB                                                                     17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK                                                            0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x)                                          (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x)                                          (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB                                                                    20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB                                                                    19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK                                                           0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x)                                         (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x)                                         (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK                                                          0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x)                                        (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x)                                        (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK                                                            0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK                                                             0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x)                                           (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x)                                           (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK                                                             0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x)                                           (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x)                                           (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK                                                           0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x)                                         (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x)                                         (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK                                                           0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK                                                             0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK                                                               0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x)                                             (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x)                                             (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK                                                             0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x)                                           (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x)                                           (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK                                                                0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS                                                                    0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET                                                                     0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB                                                                       3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB                                                                       0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK                                                             0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x)                                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x)                                            (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB                                                                       7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB                                                                       4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK                                                             0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB                                                                      11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB                                                                       8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB                                                                    15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB                                                                    12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK                                                           0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x)                                         (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x)                                         (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB                                                                        16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB                                                                        16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK                                                               0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x)                                             (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x)                                             (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK                                                    0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_MSB                                                                         19
+#define PHY_ANALOG_SYNTH2_CPBIAS_LSB                                                                         18
+#define PHY_ANALOG_SYNTH2_CPBIAS_MASK                                                                0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x)                                              (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x)                                              (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB                                                                     20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK                                                            0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB                                                                     25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB                                                                     23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK                                                            0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB                                                                      28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB                                                                      26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK                                                             0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB                                                                     31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB                                                                     29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK                                                            0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS                                                                    0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET                                                                     0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB                                                                   5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB                                                                   0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK                                                         0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x)                                        (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x)                                        (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB                                                                   11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB                                                                    6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK                                                          0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x)                                         (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x)                                         (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB                                                                   17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB                                                                   12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK                                                          0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x)                                        (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x)                                        (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB                                                                     23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB                                                                     18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK                                                            0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x)                                          (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x)                                          (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB                                                              29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB                                                              24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK                                                     0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)                                   (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)                                   (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK                                                          0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK                                                          0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS                                                                    0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET                                                                     0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK                                                       0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x)                                      (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x)                                      (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK                                                          0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x)                                         (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x)                                         (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB                                                                 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB                                                                 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK                                                       0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x)                                      (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x)                                      (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK                                                     0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x)                                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x)                                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK                                                         0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x)                                        (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x)                                        (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB                                                                      7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB                                                                      6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK                                                            0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x)                                           (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x)                                           (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK                                                              0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK                                                           0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB                                                                       12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB                                                                       11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK                                                              0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x)                                            (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x)                                            (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK                                                           0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x)                                         (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x)                                         (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK                                                           0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK                                                      0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x)                                    (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x)                                    (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK                                                          0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x)                                        (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x)                                        (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB                                                                     25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB                                                                     18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK                                                            0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x)                                          (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x)                                          (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK                                                          0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x)                                        (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x)                                        (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK                                                           0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x)                                         (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x)                                         (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK                                                   0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)                                 (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)                                 (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK                                                         0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK                                                            0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK                                                     0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)                                   (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)                                   (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS                                                                    0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET                                                                     0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB                                                                         1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB                                                                         0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK                                                               0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB                                                                4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB                                                                2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB                                                                7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB                                                                5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK                                                      0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB                                                                   10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB                                                                    8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK                                                          0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB                                                                13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB                                                                11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK                                                       0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x)                                     (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x)                                     (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK                                                       0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x)                                     (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x)                                     (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB                                                                   17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB                                                                   15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK                                                          0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x)                                        (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x)                                        (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB                                                                 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB                                                                 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK                                                        0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x)                                      (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x)                                      (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB                                                                 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB                                                                 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK                                                        0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x)                                      (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x)                                      (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB                                                                 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB                                                                 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK                                                        0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x)                                      (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x)                                      (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB                                                                   29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB                                                                   27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK                                                          0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x)                                        (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x)                                        (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SPARE5A_MSB                                                                        31
+#define PHY_ANALOG_SYNTH5_SPARE5A_LSB                                                                        30
+#define PHY_ANALOG_SYNTH5_SPARE5A_MASK                                                               0xc0000000
+#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x)                                             (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x)                                             (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS                                                                    0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET                                                                     0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB                                                                     1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB                                                                     0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK                                                           0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x)                                          (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB                                                                         8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB                                                                         2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK                                                               0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x)                                              (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK                                                                0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x)                                               (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK                                                               0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK                                                           0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK                                                      0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK                                                             0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x)                                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK                                                             0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x)                                           (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK                                                               0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x)                                             (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB                                                                     23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB                                                                     16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK                                                            0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x)                                          (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK                                                                0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x)                                              (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK                                                      0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK                                                            0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x)                                          (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB                                                                 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB                                                                 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK                                                        0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x)                                      (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x)                                            (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS                                                                    0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET                                                                     0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK                                                        0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK                                                         0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x)                                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x)                                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB                                                                       18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB                                                                        2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK                                                              0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x)                                             (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x)                                             (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB                                                                        27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB                                                                        19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK                                                               0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x)                                             (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x)                                             (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB                                                                    29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB                                                                    28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK                                                           0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x)                                         (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x)                                         (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK                                                              0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x)                                            (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x)                                            (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK                                                      0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x)                                    (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x)                                    (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS                                                                    0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET                                                                     0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK                                                   0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB                                                                       7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB                                                                       1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK                                                             0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x)                                            (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x)                                            (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB                                                                       11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB                                                                        8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK                                                              0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x)                                             (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x)                                             (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB                                                                       16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB                                                                       12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK                                                              0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x)                                            (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x)                                            (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB                                                                       21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB                                                                       17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK                                                              0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x)                                            (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x)                                            (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB                                                              26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB                                                              22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB                                                                        31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB                                                                        27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS                                                                    0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET                                                                     0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK                                                         0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB                                                                     3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB                                                                     1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK                                                           0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x)                                          (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x)                                          (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB                                                                      7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB                                                                      4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK                                                            0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x)                                           (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x)                                           (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB                                                                      11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB                                                                       8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB                                                                      16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB                                                                      12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK                                                             0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x)                                           (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x)                                           (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB                                                                      21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB                                                                      17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK                                                             0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x)                                           (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x)                                           (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB                                                              26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB                                                              22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB                                                                        31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB                                                                        27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS                                                                   0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET                                                                    0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK                                                             0x00000001
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB                                                                3
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB                                                                1
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK                                                      0x0000000e
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x)                                     (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x)                                     (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB                                                                 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB                                                                 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK                                                       0x00000010
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x)                                      (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x)                                      (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB                                                                 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB                                                                 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK                                                       0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x)                                      (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x)                                      (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB                                                                10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB                                                                 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK                                                       0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x)                                      (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x)                                      (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB                                                                   13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB                                                                   11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB                                                                    17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB                                                                    14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB                                                                     21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB                                                                     18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB                                                                     26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB                                                                     22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB                                                                     31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB                                                                     27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS                                                                   0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET                                                                    0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB                                                                       4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK                                                             0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x)                                            (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x)                                            (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK                                                     0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x)                                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x)                                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB                                                                       7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB                                                                       6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK                                                             0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x)                                            (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x)                                            (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB                                                                    9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB                                                                    8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK                                                          0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x)                                         (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x)                                         (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK                                                      0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x)                                    (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x)                                    (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB                                                                   13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB                                                                   11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB                                                                    17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB                                                                    14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB                                                                     21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB                                                                     18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB                                                                     26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB                                                                     22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB                                                                     31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB                                                                     27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS                                                                   0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET                                                                    0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB                                                                      17
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK                                                             0x0003ffff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x)                                            (((x) & 0x0003ffff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x)                                            (((x) << 0) & 0x0003ffff)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK                                                              0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB                                                                      22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB                                                                      19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK                                                             0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB                                                                      26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB                                                                      23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK                                                             0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB                                                                      30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB                                                                      27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK                                                             0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x)                                           (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x)                                           (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK                                                       0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x)                                     (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x)                                     (((x) << 31) & 0x80000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS                                                                     0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET                                                                      0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB                                                                           6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB                                                                           0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK                                                                 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x)                                                (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x)                                                (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB                                                                     9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB                                                                     7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK                                                           0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x)                                          (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x)                                          (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB                                                                    12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB                                                                    10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK                                                           0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x)                                         (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x)                                         (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB                                                                      15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB                                                                      13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK                                                             0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x)                                           (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x)                                           (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB                                                                     18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB                                                                     16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK                                                            0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x)                                          (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x)                                          (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB                                                                     21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB                                                                     19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK                                                            0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x)                                          (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x)                                          (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB                                                                     24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB                                                                     22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK                                                            0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x)                                          (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x)                                          (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB                                                                        31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB                                                                        25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK                                                               0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x)                                             (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x)                                             (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS                                                                     0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET                                                                      0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB                                                                           4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK                                                                 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x)                                                (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x)                                                (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB                                                                  7
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB                                                                  5
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK                                                        0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x)                                       (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x)                                       (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB                                                                    10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB                                                                     8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB                                                                    13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB                                                                    11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK                                                           0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x)                                         (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x)                                         (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB                                                                    16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB                                                                    14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK                                                           0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB                                                                   19
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB                                                                   17
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK                                                          0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x)                                        (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x)                                        (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB                                                                  22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB                                                                  20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB                                                                  25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB                                                                  23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB                                                                   28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB                                                                   26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK                                                          0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x)                                        (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x)                                        (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB                                                                   31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB                                                                   29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK                                                          0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS                                                                     0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET                                                                      0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB                                                                           1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK                                                                 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB                                                                  4
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB                                                                  2
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK                                                        0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x)                                       (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x)                                       (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB                                                                     7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB                                                                     5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK                                                           0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x)                                          (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x)                                          (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB                                                                    10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB                                                                     8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB                                                                   13
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB                                                                   11
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK                                                          0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB                                                                  16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB                                                                  14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB                                                                      19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB                                                                      17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK                                                             0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB                                                                     22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB                                                                     20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB                                                                     25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB                                                                     23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK                                                            0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB                                                                     28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB                                                                     26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK                                                            0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB                                                                     31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB                                                                     29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK                                                            0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS                                                                     0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET                                                                      0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB                                                                          13
+#define PHY_ANALOG_BIAS4_SPARE4_LSB                                                                           0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK                                                                 0x00003fff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x)                                                (((x) & 0x00003fff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x)                                                (((x) << 0) & 0x00003fff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB                                                                  16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB                                                                  14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB                                                                  19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB                                                                  17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK                                                         0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x)                                       (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x)                                       (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB                                                                  22
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB                                                                  20
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB                                                                  25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB                                                                  23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB                                                                  28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB                                                                  26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK                                                         0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB                                                                  31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB                                                                  29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK                                                         0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS                                                                     0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET                                                                      0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK                                                             0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB                                                                        5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB                                                                        2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK                                                              0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x)                                             (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x)                                             (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK                                                          0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK                                                             0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK                                                         0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x)                                        (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x)                                        (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB                                                                    11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB                                                                     9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK                                                           0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x)                                          (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x)                                          (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB                                                                    13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB                                                                    12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK                                                           0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x)                                         (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x)                                         (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK                                                          0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB                                                                        18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB                                                                        15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK                                                               0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x)                                             (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x)                                             (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB                                                                      22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB                                                                      19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK                                                             0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB                                                                      26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB                                                                      23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK                                                             0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB                                                                         30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB                                                                         27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK                                                                0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK                                                              0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS                                                                     0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET                                                                      0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_LSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_MASK                                                                  0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x)                                                 (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x)                                                 (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK                                                                0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK                                                            0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x)                                           (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x)                                           (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB                                                                            5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB                                                                            4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK                                                                  0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x)                                                 (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x)                                                 (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK                                                              0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x)                                             (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x)                                             (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_LSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_MASK                                                                   0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x)                                                  (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x)                                                  (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK                                                               0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x)                                              (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x)                                              (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_LSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_MASK                                                                   0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x)                                                  (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x)                                                  (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK                                                               0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x)                                             (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_LSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_MASK                                                                   0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x)                                                 (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x)                                                 (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK                                                               0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_LSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_MASK                                                                  0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x)                                                (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x)                                                (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK                                                              0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB                                                                           17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB                                                                           15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK                                                                  0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x)                                                (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x)                                                (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK                                                              0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB                                                                    21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB                                                                    19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK                                                           0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB                                                                    23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB                                                                    22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK                                                           0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x)                                         (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x)                                         (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB                                                                         25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB                                                                         24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK                                                                0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x)                                              (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x)                                              (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB                                                                         28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB                                                                         26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK                                                                0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x)                                              (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x)                                              (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB                                                                         31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB                                                                         29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK                                                                0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x)                                              (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x)                                              (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS                                                                     0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET                                                                      0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB                                                                           2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK                                                                 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB                                                                     3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB                                                                     3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK                                                           0x00000008
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x)                                          (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x)                                          (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_DACRSTB_MSB                                                                          4
+#define PHY_ANALOG_RXTX3_DACRSTB_LSB                                                                          4
+#define PHY_ANALOG_RXTX3_DACRSTB_MASK                                                                0x00000010
+#define PHY_ANALOG_RXTX3_DACRSTB_GET(x)                                               (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_DACRSTB_SET(x)                                               (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB                                                                    5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB                                                                    5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK                                                          0x00000020
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x)                                         (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x)                                         (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK                                                               0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x)                                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x)                                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK                                                                 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x)                                                (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x)                                                (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK                                                             0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x)                                            (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x)                                            (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK                                                                 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x)                                                (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x)                                                (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK                                                             0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x)                                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x)                                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB                                                                      16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB                                                                      11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK                                                             0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x)                                           (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x)                                           (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK                                                                0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK                                                            0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x)                                          (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x)                                          (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK                                                             0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK                                                             0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x)                                           (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x)                                           (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK                                                         0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_LSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_MASK                                                                  0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x)                                                (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x)                                                (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK                                                              0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_LSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_MASK                                                                  0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK                                                              0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x)                                            (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x)                                            (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK                                                             0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x)                                           (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x)                                           (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK                                                         0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x)                                       (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x)                                       (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_LSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_MASK                                                                  0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x)                                                (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x)                                                (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK                                                              0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_SPURON_MSB                                                                          30
+#define PHY_ANALOG_RXTX3_SPURON_LSB                                                                          30
+#define PHY_ANALOG_RXTX3_SPURON_MASK                                                                 0x40000000
+#define PHY_ANALOG_RXTX3_SPURON_GET(x)                                               (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x)                                               (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB                                                                      31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB                                                                      31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK                                                             0x80000000
+#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x)                                           (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x)                                           (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS                                                                       0x00000140
+#define PHY_ANALOG_BB1_OFFSET                                                                        0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK                                                               0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x)                                              (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x)                                              (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK                                                               0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK                                                                0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK                                                             0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x)                                            (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x)                                            (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK                                                              0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x)                                             (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x)                                             (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK                                                            0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x)                                           (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x)                                           (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK                                                             0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x)                                            (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x)                                            (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK                                                             0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK                                                              0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK                                                               0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x)                                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x)                                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK                                                                0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x)                                              (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x)                                              (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK                                                               0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x)                                             (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x)                                             (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK                                                                0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x)                                              (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x)                                              (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB                                                                             15
+#define PHY_ANALOG_BB1_CMSEL_LSB                                                                             13
+#define PHY_ANALOG_BB1_CMSEL_MASK                                                                    0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x)                                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x)                                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB                                                                            17
+#define PHY_ANALOG_BB1_ATBSEL_LSB                                                                            16
+#define PHY_ANALOG_BB1_ATBSEL_MASK                                                                   0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x)                                                 (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x)                                                 (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK                                                     0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x)                                   (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x)                                   (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB                                                                      23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB                                                                      19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK                                                             0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x)                                           (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB                                                                      28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB                                                                      24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK                                                             0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x)                                           (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x)                                           (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK                                                              0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB                                                                       31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB                                                                       30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK                                                              0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x)                                            (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x)                                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS                                                                       0x00000144
+#define PHY_ANALOG_BB2_OFFSET                                                                        0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB                                                                              6
+#define PHY_ANALOG_BB2_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB2_SPARE_MASK                                                                    0x0000007f
+#define PHY_ANALOG_BB2_SPARE_GET(x)                                                   (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x)                                                   (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB                                                                           9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB                                                                           7
+#define PHY_ANALOG_BB2_SEL_TEST_MASK                                                                 0x00000380
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x)                                                (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x)                                                (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BB2_SCFIR_CAP_MSB                                                                         14
+#define PHY_ANALOG_BB2_SCFIR_CAP_LSB                                                                         10
+#define PHY_ANALOG_BB2_SCFIR_CAP_MASK                                                                0x00007c00
+#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x)                                              (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x)                                              (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB                                                                15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB                                                                15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK                                                       0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x)                                     (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x)                                     (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB                                                                            19
+#define PHY_ANALOG_BB2_FNOTCH_LSB                                                                            16
+#define PHY_ANALOG_BB2_FNOTCH_MASK                                                                   0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x)                                                 (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x)                                                 (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK                                                          0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB                                                                          25
+#define PHY_ANALOG_BB2_FILTERFC_LSB                                                                          21
+#define PHY_ANALOG_BB2_FILTERFC_MASK                                                                 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x)                                               (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x)                                               (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK                                                        0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x)                                      (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x)                                      (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK                                                             0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK                                                              0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK                                                              0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK                                                               0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK                                                          0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TOP1 */
+#define PHY_ANALOG_TOP1_ADDRESS                                                                      0x00000280
+#define PHY_ANALOG_TOP1_OFFSET                                                                       0x00000280
+#define PHY_ANALOG_TOP1_SEL_KVCO_MSB                                                                          1
+#define PHY_ANALOG_TOP1_SEL_KVCO_LSB                                                                          0
+#define PHY_ANALOG_TOP1_SEL_KVCO_MASK                                                                0x00000003
+#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x)                                               (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x)                                               (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TOP1_PLLATB_MSB                                                                            3
+#define PHY_ANALOG_TOP1_PLLATB_LSB                                                                            2
+#define PHY_ANALOG_TOP1_PLLATB_MASK                                                                  0x0000000c
+#define PHY_ANALOG_TOP1_PLLATB_GET(x)                                                 (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_TOP1_PLLATB_SET(x)                                                 (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_TOP1_PLL_SVREG_MSB                                                                         4
+#define PHY_ANALOG_TOP1_PLL_SVREG_LSB                                                                         4
+#define PHY_ANALOG_TOP1_PLL_SVREG_MASK                                                               0x00000010
+#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x)                                              (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x)                                              (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB                                                                        5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB                                                                        5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK                                                              0x00000020
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x)                                             (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x)                                             (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP1_PWDPLL_MSB                                                                            6
+#define PHY_ANALOG_TOP1_PWDPLL_LSB                                                                            6
+#define PHY_ANALOG_TOP1_PWDPLL_MASK                                                                  0x00000040
+#define PHY_ANALOG_TOP1_PWDPLL_GET(x)                                                 (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP1_PWDPLL_SET(x)                                                 (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB                                                                      7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB                                                                      7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK                                                            0x00000080
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x)                                           (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x)                                           (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB                                                                      9
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB                                                                      8
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK                                                            0x00000300
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x)                                           (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x)                                           (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB                                                                     11
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB                                                                     10
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK                                                            0x00000c00
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x)                                          (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x)                                          (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB                                                                      13
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB                                                                      12
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK                                                             0x00003000
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x)                                           (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x)                                           (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB                                                                      15
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB                                                                      14
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK                                                             0x0000c000
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP1_REFDIV_MSB                                                                           19
+#define PHY_ANALOG_TOP1_REFDIV_LSB                                                                           16
+#define PHY_ANALOG_TOP1_REFDIV_MASK                                                                  0x000f0000
+#define PHY_ANALOG_TOP1_REFDIV_GET(x)                                                (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TOP1_REFDIV_SET(x)                                                (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TOP1_DIV_MSB                                                                              29
+#define PHY_ANALOG_TOP1_DIV_LSB                                                                              20
+#define PHY_ANALOG_TOP1_DIV_MASK                                                                     0x3ff00000
+#define PHY_ANALOG_TOP1_DIV_GET(x)                                                   (((x) & 0x3ff00000) >> 20)
+#define PHY_ANALOG_TOP1_DIV_SET(x)                                                   (((x) << 20) & 0x3ff00000)
+#define PHY_ANALOG_TOP1_PLLBYPASS_MSB                                                                        30
+#define PHY_ANALOG_TOP1_PLLBYPASS_LSB                                                                        30
+#define PHY_ANALOG_TOP1_PLLBYPASS_MASK                                                               0x40000000
+#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB                                                                      31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB                                                                      31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK                                                             0x80000000
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x)                                           (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x)                                           (((x) << 31) & 0x80000000)
+
+/* macros for TOP2 */
+#define PHY_ANALOG_TOP2_ADDRESS                                                                      0x00000284
+#define PHY_ANALOG_TOP2_OFFSET                                                                       0x00000284
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB                                                                       0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB                                                                       0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK                                                             0x00000001
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP2_PLL_LEAK_MSB                                                                          4
+#define PHY_ANALOG_TOP2_PLL_LEAK_LSB                                                                          1
+#define PHY_ANALOG_TOP2_PLL_LEAK_MASK                                                                0x0000001e
+#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x)                                               (((x) & 0x0000001e) >> 1)
+#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x)                                               (((x) << 1) & 0x0000001e)
+#define PHY_ANALOG_TOP2_PLLFRAC_MSB                                                                          19
+#define PHY_ANALOG_TOP2_PLLFRAC_LSB                                                                           5
+#define PHY_ANALOG_TOP2_PLLFRAC_MASK                                                                 0x000fffe0
+#define PHY_ANALOG_TOP2_PLLFRAC_GET(x)                                                (((x) & 0x000fffe0) >> 5)
+#define PHY_ANALOG_TOP2_PLLFRAC_SET(x)                                                (((x) << 5) & 0x000fffe0)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB                                                                       20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB                                                                       20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK                                                              0x00100000
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP2_PLLICP_MSB                                                                           23
+#define PHY_ANALOG_TOP2_PLLICP_LSB                                                                           21
+#define PHY_ANALOG_TOP2_PLLICP_MASK                                                                  0x00e00000
+#define PHY_ANALOG_TOP2_PLLICP_GET(x)                                                (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TOP2_PLLICP_SET(x)                                                (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TOP2_PLLFILTER_MSB                                                                        31
+#define PHY_ANALOG_TOP2_PLLFILTER_LSB                                                                        24
+#define PHY_ANALOG_TOP2_PLLFILTER_MASK                                                               0xff000000
+#define PHY_ANALOG_TOP2_PLLFILTER_GET(x)                                             (((x) & 0xff000000) >> 24)
+#define PHY_ANALOG_TOP2_PLLFILTER_SET(x)                                             (((x) << 24) & 0xff000000)
+
+/* macros for TOP3 */
+#define PHY_ANALOG_TOP3_ADDRESS                                                                      0x00000288
+#define PHY_ANALOG_TOP3_OFFSET                                                                       0x00000288
+#define PHY_ANALOG_TOP3_INT2GND_MSB                                                                           0
+#define PHY_ANALOG_TOP3_INT2GND_LSB                                                                           0
+#define PHY_ANALOG_TOP3_INT2GND_MASK                                                                 0x00000001
+#define PHY_ANALOG_TOP3_INT2GND_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP3_INT2GND_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP3_PWDPALCLK_MSB                                                                         1
+#define PHY_ANALOG_TOP3_PWDPALCLK_LSB                                                                         1
+#define PHY_ANALOG_TOP3_PWDPALCLK_MASK                                                               0x00000002
+#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB                                                                         2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB                                                                         2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK                                                               0x00000004
+#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x)                                              (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x)                                              (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TOP3_PWDV2I_MSB                                                                            3
+#define PHY_ANALOG_TOP3_PWDV2I_LSB                                                                            3
+#define PHY_ANALOG_TOP3_PWDV2I_MASK                                                                  0x00000008
+#define PHY_ANALOG_TOP3_PWDV2I_GET(x)                                                 (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP3_PWDV2I_SET(x)                                                 (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP3_PWDBIAS_MSB                                                                           4
+#define PHY_ANALOG_TOP3_PWDBIAS_LSB                                                                           4
+#define PHY_ANALOG_TOP3_PWDBIAS_MASK                                                                 0x00000010
+#define PHY_ANALOG_TOP3_PWDBIAS_GET(x)                                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP3_PWDBIAS_SET(x)                                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP3_PWDBG_MSB                                                                             5
+#define PHY_ANALOG_TOP3_PWDBG_LSB                                                                             5
+#define PHY_ANALOG_TOP3_PWDBG_MASK                                                                   0x00000020
+#define PHY_ANALOG_TOP3_PWDBG_GET(x)                                                  (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP3_PWDBG_SET(x)                                                  (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB                                                                      6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB                                                                      6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK                                                            0x00000040
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x)                                           (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x)                                           (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB                                                                       7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB                                                                       7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK                                                             0x00000080
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB                                                                     8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB                                                                     8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK                                                           0x00000100
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x)                                          (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x)                                          (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB                                                                      9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB                                                                      9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK                                                            0x00000200
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x)                                           (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x)                                           (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB                                                                       10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB                                                                       10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK                                                              0x00000400
+#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x)                                            (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x)                                            (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB                                                                   11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB                                                                   11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK                                                          0x00000800
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x)                                        (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x)                                        (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB                                                                   12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB                                                                   12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK                                                          0x00001000
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x)                                        (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x)                                        (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB                                                                       13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB                                                                       13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK                                                              0x00002000
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x)                                            (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x)                                            (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB                                                                      15
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB                                                                      14
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK                                                             0x0000c000
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB                                                                    22
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB                                                                    16
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK                                                           0x007f0000
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x)                                         (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x)                                         (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB                                                                    29
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB                                                                    23
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK                                                           0x3f800000
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x)                                         (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x)                                         (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB                                                                      30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB                                                                      30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK                                                             0x40000000
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x)                                           (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x)                                           (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP3_TCXODET_MSB                                                                          31
+#define PHY_ANALOG_TOP3_TCXODET_LSB                                                                          31
+#define PHY_ANALOG_TOP3_TCXODET_MASK                                                                 0x80000000
+#define PHY_ANALOG_TOP3_TCXODET_GET(x)                                               (((x) & 0x80000000) >> 31)
+
+/* macros for TOP4 */
+#define PHY_ANALOG_TOP4_ADDRESS                                                                      0x0000028c
+#define PHY_ANALOG_TOP4_OFFSET                                                                       0x0000028c
+#define PHY_ANALOG_TOP4_SPARE4_MSB                                                                           19
+#define PHY_ANALOG_TOP4_SPARE4_LSB                                                                            0
+#define PHY_ANALOG_TOP4_SPARE4_MASK                                                                  0x000fffff
+#define PHY_ANALOG_TOP4_SPARE4_GET(x)                                                 (((x) & 0x000fffff) >> 0)
+#define PHY_ANALOG_TOP4_SPARE4_SET(x)                                                 (((x) << 0) & 0x000fffff)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB                                                                   20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB                                                                   20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK                                                          0x00100000
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB                                                                       21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB                                                                       21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK                                                              0x00200000
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB                                                                       22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB                                                                       22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK                                                              0x00400000
+#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x)                                            (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x)                                            (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB                                                                       23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB                                                                       23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK                                                              0x00800000
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB                                                                     24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB                                                                     24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK                                                            0x01000000
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x)                                          (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x)                                          (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB                                                                     25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB                                                                     25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK                                                            0x02000000
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x)                                          (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x)                                          (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB                                                                    26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB                                                                    26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK                                                           0x04000000
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP4_ENBTCLK_MSB                                                                          27
+#define PHY_ANALOG_TOP4_ENBTCLK_LSB                                                                          27
+#define PHY_ANALOG_TOP4_ENBTCLK_MASK                                                                 0x08000000
+#define PHY_ANALOG_TOP4_ENBTCLK_GET(x)                                               (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP4_ENBTCLK_SET(x)                                               (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP4_PAD2GND_MSB                                                                          28
+#define PHY_ANALOG_TOP4_PAD2GND_LSB                                                                          28
+#define PHY_ANALOG_TOP4_PAD2GND_MASK                                                                 0x10000000
+#define PHY_ANALOG_TOP4_PAD2GND_GET(x)                                               (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP4_PAD2GND_SET(x)                                               (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP4_INTH2PAD_MSB                                                                         29
+#define PHY_ANALOG_TOP4_INTH2PAD_LSB                                                                         29
+#define PHY_ANALOG_TOP4_INTH2PAD_MASK                                                                0x20000000
+#define PHY_ANALOG_TOP4_INTH2PAD_GET(x)                                              (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP4_INTH2PAD_SET(x)                                              (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP4_INTH2GND_MSB                                                                         30
+#define PHY_ANALOG_TOP4_INTH2GND_LSB                                                                         30
+#define PHY_ANALOG_TOP4_INTH2GND_MASK                                                                0x40000000
+#define PHY_ANALOG_TOP4_INTH2GND_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP4_INTH2GND_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP4_INT2PAD_MSB                                                                          31
+#define PHY_ANALOG_TOP4_INT2PAD_LSB                                                                          31
+#define PHY_ANALOG_TOP4_INT2PAD_MASK                                                                 0x80000000
+#define PHY_ANALOG_TOP4_INT2PAD_GET(x)                                               (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP4_INT2PAD_SET(x)                                               (((x) << 31) & 0x80000000)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS                                                               0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET                                                                0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK                                            0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK                                         0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x)                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK                                         0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x)                        (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x)                        (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK                                       0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x)                      (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x)                      (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK                                     0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x)                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x)                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK                                     0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x)                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x)                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK                                        0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x)                       (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x)                       (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK                                        0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK                                      0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x)                     (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x)                     (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK                                               0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x)                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x)                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK                                             0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK                                            0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x)                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK                                               0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x)                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x)                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK                                             0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x)                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x)                           (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK                                        0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x)                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x)                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK                                              0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x)                            (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x)                            (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK                                                 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x)                               (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x)                               (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK                                               0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x)                             (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x)                             (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS                                                              0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET                                                               0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB                                                         10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB                                                          0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK                                                0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x)                               (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x)                               (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB                                                         26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB                                                         16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK                                                0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x)                              (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS                                                               0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET                                                                0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS                                                               0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET                                                                0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS                                                             0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET                                                              0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                    6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                    0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                          0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                         (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                         (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                  11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                   8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                         0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                        (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                        (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                  23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                  16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                         0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                  30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                  24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                         0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                       (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                       (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS                                                          0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET                                                           0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS                                                          0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET                                                           0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS                                                               0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET                                                                0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB                                               9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB                                               0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK                                     0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x)                    (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB                                              25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB                                              16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK                                     0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x)                   (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x)                   (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS                                                            0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET                                                             0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS                                                            0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET                                                             0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS                                                            0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET                                                             0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB                                                    9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB                                                    0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK                                          0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x)                         (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x)                         (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB                                                   25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB                                                   16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK                                          0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x)                        (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x)                        (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS                                                            0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET                                                             0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB                                                      3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB                                                      0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK                                            0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x)                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x)                           (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS                                                                 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET                                                                  0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB                                                         4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK                                               0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB                                                          13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB                                                           8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK                                                 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x)                                (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS                                                                0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET                                                                 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB                                                       3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB                                                       0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK                                             0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x)                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x)                            (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS                                                           0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET                                                            0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB                                                     3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB                                                     0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK                                           0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x)                          (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x)                          (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS                                                                 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET                                                                  0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB                                                         3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK                                               0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x)                              (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x)                              (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS                                                            0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET                                                             0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB                                               3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB                                               0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK                                     0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB                                                 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB                                                 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK                                       0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x)                      (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x)                      (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS                                                                0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET                                                                 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB                                                               1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB                                                               0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK                                                     0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x)                                    (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x)                                    (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK                                                 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x)                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x)                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB                                                         13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB                                                          8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK                                                0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB                                                 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB                                                 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK                                        0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x)                      (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x)                      (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS                                                                0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET                                                                 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB                                                              4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB                                                              0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK                                                    0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x)                                   (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x)                                   (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB                                                             12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB                                                              8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK                                                    0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x)                                   (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x)                                   (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB                                                            20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB                                                            16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK                                                   0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x)                                 (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x)                                 (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB                                                            28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB                                                            24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK                                                   0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x)                                 (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x)                                 (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS                                                          0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET                                                           0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB                                                    4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB                                                    0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK                                          0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x)                         (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x)                         (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB                                                   12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB                                                    8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK                                          0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x)                         (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x)                         (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS                                                            0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET                                                             0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS                                                            0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET                                                             0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS                                                                      0x00000740
+#define PHY_ANALOG_PMU1_OFFSET                                                                       0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB                                                                            10
+#define PHY_ANALOG_PMU1_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU1_SPARE_MASK                                                                   0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x)                                                  (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x)                                                  (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK                                                             0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x)                                           (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x)                                           (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK                                                              0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK                                                           0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK                                                             0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB                                                                    18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB                                                                    17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK                                                           0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x)                                         (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x)                                         (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB                                                                    21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB                                                                    19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK                                                           0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB                                                                     23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB                                                                     22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK                                                            0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x)                                          (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x)                                          (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB                                                                      25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB                                                                      24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK                                                             0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB                                                                      27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB                                                                      26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK                                                             0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB                                                                     31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB                                                                     29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK                                                            0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS                                                                      0x00000744
+#define PHY_ANALOG_PMU2_OFFSET                                                                       0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB                                                                             7
+#define PHY_ANALOG_PMU2_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU2_SPARE_MASK                                                                   0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x)                                                  (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x)                                                  (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK                                                          0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x)                                         (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x)                                         (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK                                                          0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x)                                         (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x)                                         (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK                                                          0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x)                                        (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x)                                        (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK                                                         0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x)                                       (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x)                                       (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK                                                            0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x)                                          (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x)                                          (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK                                                            0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x)                                          (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x)                                          (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK                                                     0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB                                                                  18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB                                                                  17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK                                                         0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x)                                       (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x)                                       (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK                                                           0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x)                                         (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x)                                         (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB                                                                 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB                                                                 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK                                                        0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x)                                      (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x)                                      (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK                                                           0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x)                                         (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x)                                         (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB                                                                 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB                                                                 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK                                                        0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x)                                      (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x)                                      (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB                                                                        27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB                                                                        25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK                                                               0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB                                                                    30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB                                                                    29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK                                                           0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x)                                         (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x)                                         (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK                                                   0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x)                                 (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x)                                 (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_ares_reg_reg_s {
+  volatile unsigned int RXRF_BIAS1;                                    /*        0x0 - 0x4        */
+  volatile unsigned int RXRF_BIAS2;                                    /*        0x4 - 0x8        */
+  volatile unsigned int RXRF_GAINSTAGES;                               /*        0x8 - 0xc        */
+  volatile unsigned int RXRF_AGC;                                      /*        0xc - 0x10       */
+  volatile char pad__0[0x30];                                          /*       0x10 - 0x40       */
+  volatile unsigned int TXRF1;                                         /*       0x40 - 0x44       */
+  volatile unsigned int TXRF2;                                         /*       0x44 - 0x48       */
+  volatile unsigned int TXRF3;                                         /*       0x48 - 0x4c       */
+  volatile unsigned int TXRF4;                                         /*       0x4c - 0x50       */
+  volatile unsigned int TXRF5;                                         /*       0x50 - 0x54       */
+  volatile unsigned int TXRF6;                                         /*       0x54 - 0x58       */
+  volatile unsigned int TXRF7;                                         /*       0x58 - 0x5c       */
+  volatile unsigned int TXRF8;                                         /*       0x5c - 0x60       */
+  volatile unsigned int TXRF9;                                         /*       0x60 - 0x64       */
+  volatile unsigned int TXRF10;                                        /*       0x64 - 0x68       */
+  volatile unsigned int TXRF11;                                        /*       0x68 - 0x6c       */
+  volatile unsigned int TXRF12;                                        /*       0x6c - 0x70       */
+  volatile char pad__1[0x10];                                          /*       0x70 - 0x80       */
+  volatile unsigned int SYNTH1;                                        /*       0x80 - 0x84       */
+  volatile unsigned int SYNTH2;                                        /*       0x84 - 0x88       */
+  volatile unsigned int SYNTH3;                                        /*       0x88 - 0x8c       */
+  volatile unsigned int SYNTH4;                                        /*       0x8c - 0x90       */
+  volatile unsigned int SYNTH5;                                        /*       0x90 - 0x94       */
+  volatile unsigned int SYNTH6;                                        /*       0x94 - 0x98       */
+  volatile unsigned int SYNTH7;                                        /*       0x98 - 0x9c       */
+  volatile unsigned int SYNTH8;                                        /*       0x9c - 0xa0       */
+  volatile unsigned int SYNTH9;                                        /*       0xa0 - 0xa4       */
+  volatile unsigned int SYNTH10;                                       /*       0xa4 - 0xa8       */
+  volatile unsigned int SYNTH11;                                       /*       0xa8 - 0xac       */
+  volatile unsigned int SYNTH12;                                       /*       0xac - 0xb0       */
+  volatile char pad__2[0x10];                                          /*       0xb0 - 0xc0       */
+  volatile unsigned int BIAS1;                                         /*       0xc0 - 0xc4       */
+  volatile unsigned int BIAS2;                                         /*       0xc4 - 0xc8       */
+  volatile unsigned int BIAS3;                                         /*       0xc8 - 0xcc       */
+  volatile unsigned int BIAS4;                                         /*       0xcc - 0xd0       */
+  volatile char pad__3[0x30];                                          /*       0xd0 - 0x100      */
+  volatile unsigned int RXTX1;                                         /*      0x100 - 0x104      */
+  volatile unsigned int RXTX2;                                         /*      0x104 - 0x108      */
+  volatile unsigned int RXTX3;                                         /*      0x108 - 0x10c      */
+  volatile char pad__4[0x34];                                          /*      0x10c - 0x140      */
+  volatile unsigned int BB1;                                           /*      0x140 - 0x144      */
+  volatile unsigned int BB2;                                           /*      0x144 - 0x148      */
+  volatile char pad__5[0x138];                                         /*      0x148 - 0x280      */
+  volatile unsigned int TOP1;                                          /*      0x280 - 0x284      */
+  volatile unsigned int TOP2;                                          /*      0x284 - 0x288      */
+  volatile unsigned int TOP3;                                          /*      0x288 - 0x28c      */
+  volatile unsigned int TOP4;                                          /*      0x28c - 0x290      */
+  volatile char pad__6[0xf0];                                          /*      0x290 - 0x380      */
+  volatile unsigned int rbist_cntrl;                                   /*      0x380 - 0x384      */
+  volatile unsigned int tx_dc_offset;                                  /*      0x384 - 0x388      */
+  volatile unsigned int tx_tonegen0;                                   /*      0x388 - 0x38c      */
+  volatile unsigned int tx_tonegen1;                                   /*      0x38c - 0x390      */
+  volatile unsigned int tx_lftonegen0;                                 /*      0x390 - 0x394      */
+  volatile unsigned int tx_linear_ramp_i;                              /*      0x394 - 0x398      */
+  volatile unsigned int tx_linear_ramp_q;                              /*      0x398 - 0x39c      */
+  volatile unsigned int tx_prbs_mag;                                   /*      0x39c - 0x3a0      */
+  volatile unsigned int tx_prbs_seed_i;                                /*      0x3a0 - 0x3a4      */
+  volatile unsigned int tx_prbs_seed_q;                                /*      0x3a4 - 0x3a8      */
+  volatile unsigned int cmac_dc_cancel;                                /*      0x3a8 - 0x3ac      */
+  volatile unsigned int cmac_dc_offset;                                /*      0x3ac - 0x3b0      */
+  volatile unsigned int cmac_corr;                                     /*      0x3b0 - 0x3b4      */
+  volatile unsigned int cmac_power;                                    /*      0x3b4 - 0x3b8      */
+  volatile unsigned int cmac_cross_corr;                               /*      0x3b8 - 0x3bc      */
+  volatile unsigned int cmac_i2q2;                                     /*      0x3bc - 0x3c0      */
+  volatile unsigned int cmac_power_hpf;                                /*      0x3c0 - 0x3c4      */
+  volatile unsigned int rxdac_set1;                                    /*      0x3c4 - 0x3c8      */
+  volatile unsigned int rxdac_set2;                                    /*      0x3c8 - 0x3cc      */
+  volatile unsigned int rxdac_long_shift;                              /*      0x3cc - 0x3d0      */
+  volatile unsigned int cmac_results_i;                                /*      0x3d0 - 0x3d4      */
+  volatile unsigned int cmac_results_q;                                /*      0x3d4 - 0x3d8      */
+  volatile char pad__7[0x368];                                         /*      0x3d8 - 0x740      */
+  volatile unsigned int PMU1;                                          /*      0x740 - 0x744      */
+  volatile unsigned int PMU2;                                          /*      0x744 - 0x748      */
+} analog_intf_ares_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
new file mode 100644
index 000000000000..55ed918fa6ec
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
@@ -0,0 +1,3670 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS                                                                0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET                                                                 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB                                                               3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB                                                               1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK                                                     0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB                                                                6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB                                                                4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK                                                      0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x)                                     (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x)                                     (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB                                                                9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB                                                                7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK                                                      0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x)                                     (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x)                                     (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB                                                           12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB                                                           10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK                                                  0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x)                                (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x)                                (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB                                                             15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB                                                             13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK                                                    0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x)                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x)                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB                                                              18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB                                                              16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK                                                     0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x)                                   (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x)                                   (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB                                                              21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB                                                              19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK                                                     0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x)                                   (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x)                                   (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB                                                               24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB                                                               22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK                                                      0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x)                                    (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x)                                    (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB                                                             27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB                                                             25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK                                                    0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x)                                  (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x)                                  (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB                                                              30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB                                                              28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK                                                     0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x)                                   (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x)                                   (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB                                                                   31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK                                                          0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS                                                                0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET                                                                 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB                                                                       0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK                                                             0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB                                                                        3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB                                                                        1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK                                                              0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x)                                             (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x)                                             (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB                                                                    6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB                                                                    4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK                                                          0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x)                                         (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x)                                         (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB                                                                  7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK                                                        0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB                                                             10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB                                                              8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK                                                    0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x)                                   (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x)                                   (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB                                                              13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB                                                              11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK                                                     0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x)                                   (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x)                                   (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB                                                             16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB                                                             14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK                                                    0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x)                                  (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x)                                  (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB                                                               19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB                                                               17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK                                                      0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x)                                    (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x)                                    (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB                                                                22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB                                                                20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK                                                       0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x)                                     (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x)                                     (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB                                                                25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB                                                                23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK                                                       0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x)                                     (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x)                                     (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB                                                             28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB                                                             26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK                                                    0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x)                                  (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x)                                  (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB                                                                31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB                                                                29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK                                                       0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS                                                           0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET                                                            0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB                                                                  0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK                                                        0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB                                                            1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK                                                  0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x)                                 (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x)                                 (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB                                                              3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB                                                              2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK                                                    0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x)                                   (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x)                                   (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB                                                              5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB                                                              4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK                                                    0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x)                                   (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x)                                   (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB                                                         6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK                                               0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB                                                               7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK                                                     0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x)                                    (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x)                                    (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB                                                              8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK                                                    0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x)                                   (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x)                                   (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB                                                              9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK                                                    0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x)                                   (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x)                                   (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB                                                             10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK                                                    0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB                                                             12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB                                                             11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK                                                    0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x)                                  (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x)                                  (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB                                                        13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK                                               0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x)                             (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x)                             (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB                                                              14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK                                                     0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x)                                   (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x)                                   (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB                                                              15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK                                                     0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x)                                   (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x)                                   (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB                                                             16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK                                                    0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x)                                  (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x)                                  (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB                                                             17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK                                                    0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB                                                        19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB                                                        18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK                                               0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x)                             (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x)                             (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB                                                        22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB                                                        20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK                                               0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x)                             (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x)                             (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB                                                        25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB                                                        23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK                                               0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x)                             (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x)                             (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB                                                        27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB                                                        26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK                                               0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB                                                        30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB                                                        28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK                                               0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x)                             (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x)                             (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB                                                           31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK                                                  0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x)                                (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x)                                (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS                                                                  0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET                                                                   0x0000000c
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB                                                          0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB                                                          0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK                                                0x00000001
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x)                               (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x)                               (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB                                                          1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB                                                          1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK                                                0x00000002
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x)                               (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x)                               (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB                                                                       2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB                                                                       2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK                                                             0x00000004
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x)                                            (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB                                                                  3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB                                                                  3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK                                                        0x00000008
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x)                                       (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x)                                       (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB                                                                4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB                                                                4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK                                                      0x00000010
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x)                                     (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x)                                     (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB                                                                    5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB                                                                    5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK                                                          0x00000020
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x)                                         (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x)                                         (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB                                                                 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB                                                                 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK                                                       0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x)                                      (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x)                                      (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB                                                             14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB                                                              9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK                                                    0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x)                                   (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x)                                   (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB                                                              18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB                                                              15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK                                                     0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x)                                   (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x)                                   (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB                                                             24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB                                                             19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK                                                    0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x)                                  (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x)                                  (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB                                                              28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB                                                              25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK                                                     0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x)                                   (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x)                                   (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB                                                                  29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK                                                         0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB                                                                   30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK                                                          0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB                                                                 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK                                                        0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x)                                      (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x)                                      (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS                                                                     0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET                                                                      0x00000040
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB                                                                        0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB                                                                        0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK                                                              0x00000001
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x)                                             (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x)                                             (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB                                                                        1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB                                                                        1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK                                                              0x00000002
+#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB                                                                    2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB                                                                    2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK                                                          0x00000004
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x)                                         (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x)                                         (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB                                                                    3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB                                                                    3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK                                                          0x00000008
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x)                                         (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x)                                         (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB                                                                       7
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB                                                                       4
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK                                                             0x000000f0
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB                                                                      11
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB                                                                       8
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK                                                             0x00000f00
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB                                                                      15
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB                                                                      12
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK                                                             0x0000f000
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x)                                           (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x)                                           (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB                                                                   16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB                                                                   16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK                                                          0x00010000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x)                                        (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x)                                        (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB                                                                         17
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB                                                                         17
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK                                                                0x00020000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB                                                                          18
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB                                                                          18
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK                                                                 0x00040000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x)                                               (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x)                                               (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB                                                                         19
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK                                                                0x00080000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x)                                              (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x)                                              (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB                                                                       20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB                                                                       20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK                                                              0x00100000
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x)                                            (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x)                                            (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB                                                                       21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB                                                                       21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK                                                              0x00200000
+#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x)                                            (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x)                                            (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB                                                                   22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK                                                          0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x)                                        (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x)                                        (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB                                                                   23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK                                                          0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x)                                        (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x)                                        (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB                                                                       30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB                                                                       24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK                                                              0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x)                                            (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x)                                            (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB                                                                   31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK                                                          0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS                                                                     0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET                                                                      0x00000044
+#define PHY_ANALOG_TXRF2_D3B5G_MSB                                                                            2
+#define PHY_ANALOG_TXRF2_D3B5G_LSB                                                                            0
+#define PHY_ANALOG_TXRF2_D3B5G_MASK                                                                  0x00000007
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x)                                                 (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x)                                                 (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB                                                                            5
+#define PHY_ANALOG_TXRF2_D4B5G_LSB                                                                            3
+#define PHY_ANALOG_TXRF2_D4B5G_MASK                                                                  0x00000038
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x)                                                 (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x)                                                 (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB                                                                           8
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB                                                                           6
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK                                                                 0x000001c0
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x)                                                (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x)                                                (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF2_DCAS2G_MSB                                                                          11
+#define PHY_ANALOG_TXRF2_DCAS2G_LSB                                                                           9
+#define PHY_ANALOG_TXRF2_DCAS2G_MASK                                                                 0x00000e00
+#define PHY_ANALOG_TXRF2_DCAS2G_GET(x)                                                (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF2_DCAS2G_SET(x)                                                (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB                                                                     14
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB                                                                     12
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK                                                            0x00007000
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x)                                          (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x)                                          (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB                                                                        17
+#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB                                                                        15
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK                                                               0x00038000
+#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x)                                             (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x)                                             (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB                                                                        20
+#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB                                                                        18
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK                                                               0x001c0000
+#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x)                                             (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x)                                             (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB                                                                        23
+#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB                                                                        21
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK                                                               0x00e00000
+#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x)                                             (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x)                                             (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TXRF2_DB2G_MSB                                                                            26
+#define PHY_ANALOG_TXRF2_DB2G_LSB                                                                            24
+#define PHY_ANALOG_TXRF2_DB2G_MASK                                                                   0x07000000
+#define PHY_ANALOG_TXRF2_DB2G_GET(x)                                                 (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF2_DB2G_SET(x)                                                 (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB                                                                         30
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB                                                                         27
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK                                                                0x78000000
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB                                                                         31
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB                                                                         31
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK                                                                0x80000000
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x)                                              (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x)                                              (((x) << 31) & 0x80000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS                                                                     0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET                                                                      0x00000048
+#define PHY_ANALOG_TXRF3_FILTR2G_MSB                                                                          1
+#define PHY_ANALOG_TXRF3_FILTR2G_LSB                                                                          0
+#define PHY_ANALOG_TXRF3_FILTR2G_MASK                                                                0x00000003
+#define PHY_ANALOG_TXRF3_FILTR2G_GET(x)                                               (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF3_FILTR2G_SET(x)                                               (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB                                                                        2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB                                                                        2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK                                                              0x00000004
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x)                                             (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x)                                             (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB                                                                        3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB                                                                        3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK                                                              0x00000008
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x)                                             (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x)                                             (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF3_PDFB2G_MSB                                                                           4
+#define PHY_ANALOG_TXRF3_PDFB2G_LSB                                                                           4
+#define PHY_ANALOG_TXRF3_PDFB2G_MASK                                                                 0x00000010
+#define PHY_ANALOG_TXRF3_PDFB2G_GET(x)                                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF3_PDFB2G_SET(x)                                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF3_RDIV5G_MSB                                                                           6
+#define PHY_ANALOG_TXRF3_RDIV5G_LSB                                                                           5
+#define PHY_ANALOG_TXRF3_RDIV5G_MASK                                                                 0x00000060
+#define PHY_ANALOG_TXRF3_RDIV5G_GET(x)                                                (((x) & 0x00000060) >> 5)
+#define PHY_ANALOG_TXRF3_RDIV5G_SET(x)                                                (((x) << 5) & 0x00000060)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB                                                                         9
+#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB                                                                         7
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK                                                               0x00000380
+#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x)                                              (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x)                                              (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB                                                                     10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB                                                                     10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK                                                            0x00000400
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x)                                          (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x)                                          (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TXRF3_RDIV2G_MSB                                                                          12
+#define PHY_ANALOG_TXRF3_RDIV2G_LSB                                                                          11
+#define PHY_ANALOG_TXRF3_RDIV2G_MASK                                                                 0x00001800
+#define PHY_ANALOG_TXRF3_RDIV2G_GET(x)                                               (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_TXRF3_RDIV2G_SET(x)                                               (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB                                                                     13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB                                                                     13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK                                                            0x00002000
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF3_OCAS5G_MSB                                                                          16
+#define PHY_ANALOG_TXRF3_OCAS5G_LSB                                                                          14
+#define PHY_ANALOG_TXRF3_OCAS5G_MASK                                                                 0x0001c000
+#define PHY_ANALOG_TXRF3_OCAS5G_GET(x)                                               (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF3_OCAS5G_SET(x)                                               (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF3_D2CAS5G_MSB                                                                         19
+#define PHY_ANALOG_TXRF3_D2CAS5G_LSB                                                                         17
+#define PHY_ANALOG_TXRF3_D2CAS5G_MASK                                                                0x000e0000
+#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x)                                              (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x)                                              (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF3_D3CAS5G_MSB                                                                         22
+#define PHY_ANALOG_TXRF3_D3CAS5G_LSB                                                                         20
+#define PHY_ANALOG_TXRF3_D3CAS5G_MASK                                                                0x00700000
+#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x)                                              (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x)                                              (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF3_D4CAS5G_MSB                                                                         25
+#define PHY_ANALOG_TXRF3_D4CAS5G_LSB                                                                         23
+#define PHY_ANALOG_TXRF3_D4CAS5G_MASK                                                                0x03800000
+#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x)                                              (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x)                                              (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB                                                                            28
+#define PHY_ANALOG_TXRF3_OB5G_LSB                                                                            26
+#define PHY_ANALOG_TXRF3_OB5G_MASK                                                                   0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x)                                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x)                                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB                                                                           31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB                                                                           29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK                                                                  0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x)                                                (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x)                                                (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS                                                                     0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET                                                                      0x0000004c
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB                                                                       1
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB                                                                       0
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK                                                             0x00000003
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB                                                                       4
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB                                                                       2
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK                                                             0x0000001c
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x)                                            (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x)                                            (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB                                                                       7
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB                                                                       5
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK                                                             0x000000e0
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x)                                            (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x)                                            (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB                                                                      10
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB                                                                       8
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK                                                             0x00000700
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x)                                            (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x)                                            (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB                                                                      13
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB                                                                      11
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK                                                             0x00003800
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x)                                           (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x)                                           (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB                                                                      16
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB                                                                      14
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK                                                             0x0001c000
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x)                                           (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x)                                           (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB                                                                      19
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB                                                                      17
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK                                                             0x000e0000
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB                                                                     22
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB                                                                     20
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK                                                            0x00700000
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB                                                                     25
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB                                                                     23
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK                                                            0x03800000
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB                                                                     28
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB                                                                     26
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK                                                            0x1c000000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB                                                                       31
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB                                                                       29
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK                                                              0xe0000000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x)                                            (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x)                                            (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS                                                                     0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET                                                                      0x00000050
+#define PHY_ANALOG_TXRF5_SPARE5_MSB                                                                           0
+#define PHY_ANALOG_TXRF5_SPARE5_LSB                                                                           0
+#define PHY_ANALOG_TXRF5_SPARE5_MASK                                                                 0x00000001
+#define PHY_ANALOG_TXRF5_SPARE5_GET(x)                                                (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_SPARE5_SET(x)                                                (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB                                                                       1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB                                                                       1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK                                                             0x00000002
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x)                                            (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB                                                                           2
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB                                                                           2
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK                                                                 0x00000004
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x)                                                (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB                                                                           3
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB                                                                           3
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK                                                                 0x00000008
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x)                                                (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB                                                                      4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB                                                                      4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK                                                            0x00000010
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x)                                           (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x)                                           (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB                                                                        5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB                                                                        5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK                                                              0x00000020
+#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x)                                             (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x)                                             (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TXRF5_OFFSET2G_MSB                                                                        12
+#define PHY_ANALOG_TXRF5_OFFSET2G_LSB                                                                         6
+#define PHY_ANALOG_TXRF5_OFFSET2G_MASK                                                               0x00001fc0
+#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x)                                              (((x) & 0x00001fc0) >> 6)
+#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x)                                              (((x) << 6) & 0x00001fc0)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB                                                                   13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB                                                                   13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK                                                          0x00002000
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x)                                        (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x)                                        (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB                                                                         16
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB                                                                         14
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK                                                                0x0001c000
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x)                                              (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x)                                              (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB                                                                         19
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB                                                                         17
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK                                                                0x000e0000
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x)                                              (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x)                                              (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB                                                                      21
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB                                                                      20
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK                                                             0x00300000
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x)                                           (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x)                                           (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB                                                                      23
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB                                                                      22
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK                                                             0x00c00000
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x)                                           (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x)                                           (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB                                                                      25
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB                                                                      24
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK                                                             0x03000000
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB                                                                      27
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB                                                                      26
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK                                                             0x0c000000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB                                                                      29
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB                                                                      28
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK                                                             0x30000000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x)                                           (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x)                                           (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB                                                                      31
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB                                                                      30
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK                                                             0xc0000000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x)                                           (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x)                                           (((x) << 30) & 0xc0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS                                                                     0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET                                                                      0x00000054
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB                                                                     0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB                                                                     0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK                                                           0x00000001
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x)                                          (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x)                                          (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB                                                                  8
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB                                                                  1
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK                                                        0x000001fe
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x)                                       (((x) & 0x000001fe) >> 1)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x)                                       (((x) << 1) & 0x000001fe)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB                                                                  10
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB                                                                   9
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK                                                         0x00000600
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x)                                        (((x) & 0x00000600) >> 9)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x)                                        (((x) << 9) & 0x00000600)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB                                                                    11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB                                                                    11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK                                                           0x00000800
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x)                                         (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB                                                                      14
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB                                                                      12
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK                                                             0x00007000
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x)                                           (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x)                                           (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB                                                                15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB                                                                15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK                                                       0x00008000
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x)                                     (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x)                                     (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB                                                                      19
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB                                                                      16
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK                                                             0x000f0000
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x)                                           (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x)                                           (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB                                                               23
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB                                                               20
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK                                                      0x00f00000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x)                                    (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x)                                    (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB                                                                    26
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB                                                                    24
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK                                                           0x07000000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x)                                         (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x)                                         (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB                                                                        30
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB                                                                        27
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK                                                               0x78000000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x)                                             (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x)                                             (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB                                                                     31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB                                                                     31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK                                                            0x80000000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS                                                                     0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET                                                                      0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB                                                                           1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB                                                                           0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB                                                                     7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB                                                                     2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB                                                                    13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB                                                                     8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB                                                                    19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB                                                                    14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB                                                                    25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB                                                                    20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB                                                                    31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB                                                                    26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS                                                                     0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET                                                                      0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB                                                                           1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB                                                                           0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB                                                                     7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB                                                                     2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK                                                           0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x)                                          (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x)                                          (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB                                                                    13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB                                                                     8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK                                                           0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x)                                          (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x)                                          (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB                                                                    19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB                                                                    14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK                                                           0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x)                                         (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x)                                         (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB                                                                    25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB                                                                    20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK                                                           0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x)                                         (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x)                                         (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB                                                                    31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB                                                                    26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK                                                           0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x)                                         (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x)                                         (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS                                                                     0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET                                                                      0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB                                                                           1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB                                                                           0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK                                                                 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB                                                                    7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB                                                                    2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK                                                          0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x)                                         (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x)                                         (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB                                                                   13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB                                                                    8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK                                                          0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x)                                         (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x)                                         (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB                                                                   19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB                                                                   14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK                                                          0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x)                                        (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x)                                        (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB                                                                   25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB                                                                   20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK                                                          0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x)                                        (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x)                                        (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB                                                                   31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB                                                                   26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK                                                          0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x)                                        (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x)                                        (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS                                                                    0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET                                                                     0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB                                                                         2
+#define PHY_ANALOG_TXRF10_SPARE10_LSB                                                                         0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK                                                               0x00000007
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x)                                              (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x)                                              (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB                                                                  3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB                                                                  3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK                                                        0x00000008
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x)                                       (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x)                                       (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB                                                                      6
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB                                                                      4
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK                                                            0x00000070
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x)                                           (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x)                                           (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB                                                                      9
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB                                                                      7
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK                                                            0x00000380
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x)                                           (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x)                                           (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB                                                                 16
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB                                                                 10
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK                                                        0x0001fc00
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x)                                      (((x) & 0x0001fc00) >> 10)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x)                                      (((x) << 10) & 0x0001fc00)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB                                                                      19
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB                                                                      17
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK                                                             0x000e0000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB                                                                     20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB                                                                     20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK                                                            0x00100000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x)                                          (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x)                                          (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB                                                                  21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB                                                                  21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK                                                         0x00200000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB                                                                27
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB                                                                22
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK                                                       0x0fc00000
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x)                                     (((x) & 0x0fc00000) >> 22)
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB                                                          31
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB                                                          28
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK                                                 0xf0000000
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x)                               (((x) & 0xf0000000) >> 28)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS                                                                    0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET                                                                     0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB                                                                         1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB                                                                         0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK                                                               0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB                                                                4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB                                                                2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK                                                      0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB                                                                    7
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB                                                                    5
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK                                                          0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x)                                         (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x)                                         (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB                                                              10
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB                                                               8
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK                                                     0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x)                                    (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x)                                    (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB                                                               13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB                                                               11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK                                                      0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x)                                    (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x)                                    (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB                                                                    16
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB                                                                    14
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK                                                           0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB                                                                19
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB                                                                17
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK                                                       0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x)                                     (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x)                                     (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB                                                                  22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB                                                                  20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK                                                         0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB                                                                  25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB                                                                  23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB                                                               28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB                                                               26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK                                                      0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x)                                    (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x)                                    (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB                                                                   31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB                                                                   29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK                                                          0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS                                                                    0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET                                                                     0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB                                                                       7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB                                                                       0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK                                                             0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x)                                            (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB                                                                       9
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB                                                                       8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK                                                             0x00000300
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x)                                            (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x)                                            (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB                                                                       13
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB                                                                       10
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK                                                              0x00003c00
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x)                                            (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x)                                            (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB                                                                       16
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB                                                                       14
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK                                                              0x0001c000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x)                                            (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x)                                            (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB                                                                    19
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB                                                                    17
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK                                                           0x000e0000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x)                                         (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x)                                         (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB                                                                22
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB                                                                20
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK                                                       0x00700000
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x)                                     (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x)                                     (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB                                                                  25
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB                                                                  23
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK                                                         0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB                                                                  28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB                                                                  26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK                                                         0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB                                                              31
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB                                                              29
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK                                                     0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x)                                   (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x)                                   (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS                                                                    0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET                                                                     0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB                                                                   2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB                                                                   0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK                                                         0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x)                                        (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x)                                        (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB                                                                     5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB                                                                     3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK                                                           0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x)                                          (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x)                                          (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB                                                           6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK                                                 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x)                                (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x)                                (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB                                                                  7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK                                                        0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x)                                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x)                                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB                                                                 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK                                                       0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x)                                      (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x)                                      (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB                                                                 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK                                                       0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x)                                      (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x)                                      (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB                                                                    10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB                                                                     11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK                                                            0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB                                                                 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB                                                                        15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB                                                                        13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK                                                               0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x)                                             (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x)                                             (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB                                                                     16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK                                                            0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x)                                          (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x)                                          (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB                                                                     18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB                                                                     17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK                                                            0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x)                                          (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x)                                          (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB                                                                    20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB                                                                    19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK                                                           0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x)                                         (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x)                                         (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB                                                                   21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK                                                          0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x)                                        (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x)                                        (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB                                                                     22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK                                                            0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x)                                          (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x)                                          (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB                                                                      23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK                                                             0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x)                                           (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x)                                           (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB                                                                      24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK                                                             0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x)                                           (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x)                                           (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB                                                                    25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK                                                           0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x)                                         (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x)                                         (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB                                                                    26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK                                                           0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB                                                                      27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK                                                             0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB                                                                        28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK                                                               0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x)                                             (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x)                                             (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB                                                                      29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK                                                             0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x)                                           (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x)                                           (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB                                                                         30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK                                                                0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB                                                                       31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS                                                                    0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET                                                                     0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB                                                                       3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB                                                                       0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK                                                             0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x)                                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x)                                            (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB                                                                       7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB                                                                       4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK                                                             0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x)                                            (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x)                                            (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB                                                                      11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB                                                                       8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB                                                               15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB                                                               12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK                                                      0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x)                                    (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x)                                    (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB                                                                   16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB                                                                   16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK                                                          0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x)                                        (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x)                                        (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB                                                             17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK                                                    0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x)                                  (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x)                                  (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB                                                                    19
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB                                                                    18
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK                                                           0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x)                                         (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x)                                         (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB                                                                     22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB                                                                     20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK                                                            0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB                                                                     25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB                                                                     23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK                                                            0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB                                                                      28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB                                                                      26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK                                                             0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x)                                           (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x)                                           (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB                                                                     31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB                                                                     29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK                                                            0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS                                                                    0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET                                                                     0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB                                                                   5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB                                                                   0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK                                                         0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x)                                        (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x)                                        (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB                                                                   11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB                                                                    6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK                                                          0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x)                                         (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x)                                         (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB                                                                   17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB                                                                   12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK                                                          0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x)                                        (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x)                                        (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB                                                                     23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB                                                                     18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK                                                            0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x)                                          (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x)                                          (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB                                                              29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB                                                              24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK                                                     0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x)                                   (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x)                                   (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB                                                                   30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK                                                          0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x)                                        (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x)                                        (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB                                                                   31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK                                                          0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS                                                                    0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET                                                                     0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB                                                                 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK                                                       0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x)                                      (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x)                                      (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB                                                                    1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK                                                          0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x)                                         (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x)                                         (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB                                                                 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB                                                                 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK                                                       0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x)                                      (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x)                                      (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB                                                               4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK                                                     0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x)                                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x)                                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB                                                                   5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK                                                         0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x)                                        (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x)                                        (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB                                                                     7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB                                                                     6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK                                                           0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x)                                          (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x)                                          (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB                                                                        8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK                                                              0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB                                                                     9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK                                                           0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB                                                                    10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK                                                           0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x)                                         (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x)                                         (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB                                                                       12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB                                                                       11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK                                                              0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x)                                            (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x)                                            (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB                                                                    13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK                                                           0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x)                                         (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x)                                         (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB                                                                    15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK                                                           0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB                                                               16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK                                                      0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x)                                    (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x)                                    (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB                                                                   17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK                                                          0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x)                                        (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x)                                        (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB                                                                     25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB                                                                     18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK                                                            0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x)                                          (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x)                                          (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB                                                                   26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK                                                          0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x)                                        (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x)                                        (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB                                                                    27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK                                                           0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x)                                         (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x)                                         (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB                                                            28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK                                                   0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x)                                 (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x)                                 (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB                                                                  29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK                                                         0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB                                                                     30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK                                                            0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x)                                          (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x)                                          (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB                                                              31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK                                                     0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x)                                   (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x)                                   (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS                                                                    0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET                                                                     0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB                                                                         1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB                                                                         0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK                                                               0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x)                                              (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x)                                              (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB                                                                4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB                                                                2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB                                                                7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB                                                                5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK                                                      0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x)                                     (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x)                                     (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB                                                                   10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB                                                                    8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK                                                          0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x)                                         (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x)                                         (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB                                                                13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB                                                                11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK                                                       0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x)                                     (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x)                                     (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB                                                                14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK                                                       0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x)                                     (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x)                                     (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB                                                                   17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB                                                                   15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK                                                          0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x)                                        (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x)                                        (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB                                                                 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB                                                                 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK                                                        0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x)                                      (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x)                                      (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB                                                                 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB                                                                 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK                                                        0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x)                                      (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x)                                      (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB                                                                 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB                                                                 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK                                                        0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x)                                      (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x)                                      (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB                                                                   29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB                                                                   27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK                                                          0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x)                                        (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x)                                        (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB                                                                    31
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB                                                                    30
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK                                                           0xc0000000
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x)                                         (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x)                                         (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS                                                                    0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET                                                                     0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB                                                                     1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB                                                                     0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK                                                           0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x)                                          (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB                                                                         8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB                                                                         2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK                                                               0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x)                                              (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB                                                                          9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK                                                                0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x)                                               (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB                                                                        10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK                                                               0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB                                                                    11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK                                                           0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x)                                         (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB                                                               12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK                                                      0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB                                                                      13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK                                                             0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x)                                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB                                                                      14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK                                                             0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x)                                           (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB                                                                        15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK                                                               0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x)                                             (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB                                                                     23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB                                                                     16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK                                                            0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x)                                          (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB                                                                         24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK                                                                0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x)                                              (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB                                                               25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK                                                      0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB                                                                     26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK                                                            0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x)                                          (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB                                                                 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB                                                                 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK                                                        0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x)                                      (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB                                                                       31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK                                                              0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x)                                            (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS                                                                    0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET                                                                     0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB                                                                  0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK                                                        0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB                                                                   1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK                                                         0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x)                                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x)                                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB                                                                       18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB                                                                        2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK                                                              0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x)                                             (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x)                                             (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB                                                                        27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB                                                                        19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK                                                               0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x)                                             (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x)                                             (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB                                                                    29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB                                                                    28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK                                                           0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x)                                         (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x)                                         (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB                                                                       30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK                                                              0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x)                                            (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x)                                            (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB                                                               31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK                                                      0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x)                                    (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x)                                    (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS                                                                    0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET                                                                     0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB                                                             0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK                                                   0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB                                                                       7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB                                                                       1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK                                                             0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x)                                            (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x)                                            (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB                                                                       11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB                                                                        8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK                                                              0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x)                                             (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x)                                             (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB                                                                       16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB                                                                       12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK                                                              0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x)                                            (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x)                                            (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB                                                                       21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB                                                                       17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK                                                              0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x)                                            (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x)                                            (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB                                                              26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB                                                              22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB                                                                        31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB                                                                        27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS                                                                    0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET                                                                     0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB                                                                   0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK                                                         0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB                                                                     3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB                                                                     1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK                                                           0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x)                                          (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x)                                          (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB                                                                      7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB                                                                      4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK                                                            0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x)                                           (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x)                                           (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB                                                                      11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB                                                                       8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK                                                             0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x)                                            (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x)                                            (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB                                                                      16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB                                                                      12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK                                                             0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x)                                           (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x)                                           (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB                                                                      21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB                                                                      17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK                                                             0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x)                                           (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x)                                           (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB                                                              26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB                                                              22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK                                                     0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x)                                   (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x)                                   (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB                                                                        31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB                                                                        27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK                                                               0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x)                                             (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x)                                             (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS                                                                   0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET                                                                    0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB                                                                       1
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK                                                             0x00000003
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB                                                                4
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB                                                                2
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK                                                      0x0000001c
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x)                                     (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x)                                     (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB                                                                 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB                                                                 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK                                                       0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x)                                      (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x)                                      (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB                                                                10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB                                                                 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK                                                       0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x)                                      (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x)                                      (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB                                                                   13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB                                                                   11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB                                                                    17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB                                                                    14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB                                                                     21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB                                                                     18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB                                                                     26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB                                                                     22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB                                                                     31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB                                                                     27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS                                                                   0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET                                                                    0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB                                                                       4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK                                                             0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x)                                            (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x)                                            (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB                                                               5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK                                                     0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x)                                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x)                                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB                                                                       7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB                                                                       6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK                                                             0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x)                                            (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x)                                            (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB                                                                    9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB                                                                    8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK                                                          0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x)                                         (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x)                                         (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB                                                               10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK                                                      0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x)                                    (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x)                                    (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB                                                                   13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB                                                                   11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK                                                          0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB                                                                    17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB                                                                    14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK                                                           0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x)                                         (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x)                                         (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB                                                                     21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB                                                                     18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK                                                            0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x)                                          (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x)                                          (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB                                                                     26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB                                                                     22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK                                                            0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x)                                          (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x)                                          (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB                                                                     31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB                                                                     27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK                                                            0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x)                                          (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x)                                          (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS                                                                   0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET                                                                    0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB                                                                       9
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK                                                             0x000003ff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x)                                            (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x)                                            (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB                                                             13
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB                                                             10
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK                                                    0x00003c00
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x)                                  (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x)                                  (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB                                                                 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB                                                                 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK                                                        0x00004000
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB                                                                  16
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB                                                                  15
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK                                                         0x00018000
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x)                                       (((x) & 0x00018000) >> 15)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x)                                       (((x) << 15) & 0x00018000)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB                                                                 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB                                                                 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK                                                        0x00020000
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x)                                      (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x)                                      (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB                                                                       18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK                                                              0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB                                                                      22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB                                                                      19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK                                                             0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB                                                                      26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB                                                                      23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK                                                             0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB                                                                      30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB                                                                      27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK                                                             0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x)                                           (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x)                                           (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB                                                                31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK                                                       0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x)                                     (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x)                                     (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH13 */
+#define PHY_ANALOG_SYNTH13_ADDRESS                                                                   0x000000b0
+#define PHY_ANALOG_SYNTH13_OFFSET                                                                    0x000000b0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MSB                                                                       0
+#define PHY_ANALOG_SYNTH13_SPARE13A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MASK                                                             0x00000001
+#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB                                                               3
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB                                                               1
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK                                                     0x0000000e
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x)                                    (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x)                                    (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB                                                                7
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB                                                                4
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK                                                      0x000000f0
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x)                                     (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x)                                     (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB                                                                11
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB                                                                 8
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK                                                       0x00000f00
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x)                                      (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x)                                      (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB                                                                16
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB                                                                12
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK                                                       0x0001f000
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x)                                     (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x)                                     (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB                                                                21
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB                                                                17
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK                                                       0x003e0000
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x)                                     (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x)                                     (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB                                                       26
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB                                                       22
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK                                              0x07c00000
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x)                            (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x)                            (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB                                                                 31
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB                                                                 27
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK                                                        0xf8000000
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x)                                      (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x)                                      (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH14 */
+#define PHY_ANALOG_SYNTH14_ADDRESS                                                                   0x000000b4
+#define PHY_ANALOG_SYNTH14_OFFSET                                                                    0x000000b4
+#define PHY_ANALOG_SYNTH14_SPARE14A_MSB                                                                       1
+#define PHY_ANALOG_SYNTH14_SPARE14A_LSB                                                                       0
+#define PHY_ANALOG_SYNTH14_SPARE14A_MASK                                                             0x00000003
+#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x)                                            (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x)                                            (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB                                                                  3
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB                                                                  2
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK                                                        0x0000000c
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x)                                       (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x)                                       (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB                                                                  5
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB                                                                  4
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK                                                        0x00000030
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x)                                       (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x)                                       (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB                                                                  7
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB                                                                  6
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK                                                        0x000000c0
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x)                                       (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x)                                       (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB                                                                  9
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB                                                                  8
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK                                                        0x00000300
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x)                                       (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x)                                       (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB                                                                 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB                                                                 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK                                                        0x00000400
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x)                                      (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x)                                      (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB                                                                 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB                                                                 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK                                                        0x00000800
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x)                                      (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x)                                      (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB                                                                 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB                                                                 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK                                                        0x00001000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x)                                      (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x)                                      (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB                                                                 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB                                                                 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK                                                        0x00002000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x)                                      (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x)                                      (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB                                                                   16
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB                                                                   14
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK                                                          0x0001c000
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x)                                        (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x)                                        (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB                                                            19
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB                                                            17
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK                                                   0x000e0000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x)                                 (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x)                                 (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB                                                            22
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB                                                            20
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK                                                   0x00700000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x)                                 (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x)                                 (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB                                                            25
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB                                                            23
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK                                                   0x03800000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x)                                 (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x)                                 (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB                                                            28
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB                                                            26
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK                                                   0x1c000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x)                                 (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x)                                 (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB                                                                31
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB                                                                29
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK                                                       0xe0000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x)                                     (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x)                                     (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS                                                                     0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET                                                                      0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB                                                                           6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB                                                                           0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK                                                                 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x)                                                (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x)                                                (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB                                                                     9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB                                                                     7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK                                                           0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x)                                          (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x)                                          (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB                                                                    12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB                                                                    10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK                                                           0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x)                                         (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x)                                         (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB                                                                      15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB                                                                      13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK                                                             0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x)                                           (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x)                                           (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB                                                                     18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB                                                                     16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK                                                            0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x)                                          (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x)                                          (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB                                                                     21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB                                                                     19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK                                                            0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x)                                          (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x)                                          (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB                                                                     24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB                                                                     22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK                                                            0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x)                                          (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x)                                          (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB                                                                        31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB                                                                        25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK                                                               0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x)                                             (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x)                                             (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS                                                                     0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET                                                                      0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB                                                                           4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB                                                                           0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK                                                                 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x)                                                (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x)                                                (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB                                                                      7
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB                                                                      5
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK                                                            0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x)                                           (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x)                                           (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB                                                                    10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB                                                                     8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB                                                                    13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB                                                                    11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK                                                           0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x)                                         (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x)                                         (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB                                                                    16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB                                                                    14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK                                                           0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x)                                         (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x)                                         (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB                                                                   19
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB                                                                   17
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK                                                          0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x)                                        (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x)                                        (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB                                                                  22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB                                                                  20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK                                                         0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x)                                       (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x)                                       (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB                                                                  25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB                                                                  23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB                                                                   28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB                                                                   26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK                                                          0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x)                                        (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x)                                        (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB                                                                   31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB                                                                   29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK                                                          0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x)                                        (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x)                                        (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS                                                                     0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET                                                                      0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB                                                                           1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK                                                                 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x)                                                (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB                                                                      4
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB                                                                      2
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK                                                            0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x)                                           (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x)                                           (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB                                                                     7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB                                                                     5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK                                                           0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x)                                          (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x)                                          (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB                                                                    10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB                                                                     8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK                                                           0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x)                                          (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x)                                          (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB                                                                   13
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB                                                                   11
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK                                                          0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x)                                        (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x)                                        (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB                                                                  16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB                                                                  14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB                                                                      19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB                                                                      17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK                                                             0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x)                                           (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x)                                           (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB                                                                     22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB                                                                     20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB                                                                     25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB                                                                     23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK                                                            0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x)                                          (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x)                                          (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB                                                                     28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB                                                                     26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK                                                            0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x)                                          (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x)                                          (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB                                                                     31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB                                                                     29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK                                                            0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS                                                                     0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET                                                                      0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB                                                                          10
+#define PHY_ANALOG_BIAS4_SPARE4_LSB                                                                           0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK                                                                 0x000007ff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x)                                                (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x)                                                (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB                                                                  13
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB                                                                  11
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK                                                         0x00003800
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x)                                       (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x)                                       (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB                                                                  16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB                                                                  14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK                                                         0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x)                                       (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x)                                       (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB                                                                  19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB                                                                  17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK                                                         0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x)                                       (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x)                                       (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB                                                                     22
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB                                                                     20
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK                                                            0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x)                                          (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x)                                          (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB                                                                  25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB                                                                  23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK                                                         0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x)                                       (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x)                                       (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB                                                                  28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB                                                                  26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK                                                         0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x)                                       (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x)                                       (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB                                                                  31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB                                                                  29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK                                                         0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x)                                       (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x)                                       (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS                                                                     0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET                                                                      0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB                                                                       0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK                                                             0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x)                                            (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x)                                            (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB                                                                        1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB                                                                        5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB                                                                        2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK                                                              0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x)                                             (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x)                                             (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB                                                                    6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK                                                          0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB                                                                       7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK                                                             0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB                                                                   8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK                                                         0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x)                                        (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x)                                        (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB                                                                    11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB                                                                     9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK                                                           0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x)                                          (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x)                                          (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB                                                                    13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB                                                                    12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK                                                           0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x)                                         (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x)                                         (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB                                                                   14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK                                                          0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x)                                        (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x)                                        (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB                                                                        18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB                                                                        15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK                                                               0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x)                                             (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x)                                             (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB                                                                      22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB                                                                      19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK                                                             0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x)                                           (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x)                                           (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB                                                                      26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB                                                                      23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK                                                             0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x)                                           (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x)                                           (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB                                                                         30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB                                                                         27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK                                                                0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x)                                              (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x)                                              (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB                                                                       31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK                                                              0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x)                                            (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x)                                            (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS                                                                     0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET                                                                      0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_LSB                                                                            0
+#define PHY_ANALOG_RXTX2_BMODE_MASK                                                                  0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x)                                                 (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x)                                                 (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB                                                                        1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK                                                              0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x)                                             (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x)                                             (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB                                                                          2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK                                                                0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB                                                                      3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK                                                            0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x)                                           (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x)                                           (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB                                                                            5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB                                                                            4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK                                                                  0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x)                                                 (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x)                                                 (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB                                                                        6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK                                                              0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x)                                             (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x)                                             (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_LSB                                                                             7
+#define PHY_ANALOG_RXTX2_TXON_MASK                                                                   0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x)                                                  (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x)                                                  (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB                                                                         8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK                                                               0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x)                                              (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x)                                              (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_LSB                                                                             9
+#define PHY_ANALOG_RXTX2_PAON_MASK                                                                   0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x)                                                  (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x)                                                  (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB                                                                        10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK                                                               0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x)                                             (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x)                                             (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_LSB                                                                            11
+#define PHY_ANALOG_RXTX2_RXON_MASK                                                                   0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x)                                                 (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x)                                                 (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB                                                                        12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK                                                               0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_LSB                                                                           13
+#define PHY_ANALOG_RXTX2_AGCON_MASK                                                                  0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x)                                                (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x)                                                (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB                                                                       14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK                                                              0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB                                                                           17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB                                                                           15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK                                                                  0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x)                                                (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x)                                                (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB                                                                       18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK                                                              0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB                                                                    21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB                                                                    19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK                                                           0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB                                                                    23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB                                                                    22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK                                                           0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x)                                         (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x)                                         (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB                                                                         25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB                                                                         24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK                                                                0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x)                                              (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x)                                              (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB                                                                         28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB                                                                         26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK                                                                0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x)                                              (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x)                                              (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB                                                                         31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB                                                                         29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK                                                                0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x)                                              (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x)                                              (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS                                                                     0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET                                                                      0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB                                                                           2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB                                                                           0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK                                                                 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x)                                                (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x)                                                (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_SPURON_MSB                                                                           3
+#define PHY_ANALOG_RXTX3_SPURON_LSB                                                                           3
+#define PHY_ANALOG_RXTX3_SPURON_MASK                                                                 0x00000008
+#define PHY_ANALOG_RXTX3_SPURON_GET(x)                                                (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x)                                                (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB                                                                     4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB                                                                     4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK                                                           0x00000010
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x)                                          (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x)                                          (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB                                                                     5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB                                                                     5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK                                                           0x00000020
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x)                                          (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x)                                          (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB                                                                         6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK                                                               0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x)                                              (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x)                                              (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB                                                                           7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK                                                                 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x)                                                (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x)                                                (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB                                                                       8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK                                                             0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x)                                            (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x)                                            (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB                                                                           9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK                                                                 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x)                                                (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x)                                                (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB                                                                      10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK                                                             0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x)                                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x)                                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB                                                                      16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB                                                                      11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK                                                             0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x)                                           (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x)                                           (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB                                                                         17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK                                                                0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x)                                              (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x)                                              (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB                                                                     18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK                                                            0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x)                                          (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x)                                          (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB                                                                      19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK                                                             0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB                                                                      20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK                                                             0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x)                                           (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x)                                           (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB                                                                  21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK                                                         0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x)                                       (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x)                                       (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_LSB                                                                           22
+#define PHY_ANALOG_RXTX3_CALFC_MASK                                                                  0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x)                                                (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x)                                                (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB                                                                       23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK                                                              0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x)                                            (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x)                                            (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_LSB                                                                           24
+#define PHY_ANALOG_RXTX3_CALTX_MASK                                                                  0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB                                                                       25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK                                                              0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x)                                            (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x)                                            (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB                                                                      26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK                                                             0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x)                                           (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x)                                           (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB                                                                  27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK                                                         0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x)                                       (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x)                                       (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_LSB                                                                           28
+#define PHY_ANALOG_RXTX3_CALPA_MASK                                                                  0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x)                                                (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x)                                                (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB                                                                       29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK                                                              0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_MSB                                                                        30
+#define PHY_ANALOG_RXTX3_TURBOADC_LSB                                                                        30
+#define PHY_ANALOG_RXTX3_TURBOADC_MASK                                                               0x40000000
+#define PHY_ANALOG_RXTX3_TURBOADC_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_TURBOADC_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB                                                                    31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB                                                                    31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK                                                           0x80000000
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x)                                         (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x)                                         (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS                                                                       0x00000140
+#define PHY_ANALOG_BB1_OFFSET                                                                        0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB                                                                         0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK                                                               0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x)                                              (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x)                                              (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB                                                                         1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK                                                               0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x)                                              (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x)                                              (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB                                                                          2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK                                                                0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x)                                               (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x)                                               (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB                                                                       3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK                                                             0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x)                                            (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x)                                            (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB                                                                        4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK                                                              0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x)                                             (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x)                                             (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB                                                                      5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK                                                            0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x)                                           (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x)                                           (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB                                                                       6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK                                                             0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x)                                            (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x)                                            (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB                                                                       7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK                                                             0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB                                                                        8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK                                                              0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB                                                                         9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK                                                               0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x)                                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x)                                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB                                                                         10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK                                                                0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x)                                              (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x)                                              (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB                                                                        11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK                                                               0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x)                                             (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x)                                             (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB                                                                         12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK                                                                0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x)                                              (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x)                                              (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB                                                                             15
+#define PHY_ANALOG_BB1_CMSEL_LSB                                                                             13
+#define PHY_ANALOG_BB1_CMSEL_MASK                                                                    0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x)                                                  (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x)                                                  (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB                                                                            17
+#define PHY_ANALOG_BB1_ATBSEL_LSB                                                                            16
+#define PHY_ANALOG_BB1_ATBSEL_MASK                                                                   0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x)                                                 (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x)                                                 (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB                                                              18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK                                                     0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x)                                   (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x)                                   (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB                                                                      23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB                                                                      19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK                                                             0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x)                                           (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB                                                                      28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB                                                                      24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK                                                             0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x)                                           (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x)                                           (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB                                                                       29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK                                                              0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB                                                                       31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB                                                                       30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK                                                              0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x)                                            (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x)                                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS                                                                       0x00000144
+#define PHY_ANALOG_BB2_OFFSET                                                                        0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB                                                                              3
+#define PHY_ANALOG_BB2_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB2_SPARE_MASK                                                                    0x0000000f
+#define PHY_ANALOG_BB2_SPARE_GET(x)                                                   (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x)                                                   (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB                                                                   7
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB                                                                   4
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK                                                         0x000000f0
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x)                                        (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x)                                        (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB                                                                           9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB                                                                           8
+#define PHY_ANALOG_BB2_SEL_TEST_MASK                                                                 0x00000300
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x)                                                (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x)                                                (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB                                                                      14
+#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB                                                                      10
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK                                                             0x00007c00
+#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x)                                           (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x)                                           (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB                                                             15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB                                                             15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK                                                    0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x)                                  (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x)                                  (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB                                                                            19
+#define PHY_ANALOG_BB2_FNOTCH_LSB                                                                            16
+#define PHY_ANALOG_BB2_FNOTCH_MASK                                                                   0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x)                                                 (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x)                                                 (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB                                                                   20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK                                                          0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x)                                        (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x)                                        (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB                                                                          25
+#define PHY_ANALOG_BB2_FILTERFC_LSB                                                                          21
+#define PHY_ANALOG_BB2_FILTERFC_MASK                                                                 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x)                                               (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x)                                               (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB                                                                 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK                                                        0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x)                                      (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x)                                      (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB                                                                      27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK                                                             0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x)                                           (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x)                                           (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB                                                                       28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK                                                              0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB                                                                       29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK                                                              0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x)                                            (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x)                                            (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB                                                                        30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK                                                               0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x)                                             (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x)                                             (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB                                                                   31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK                                                          0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for BB3 */
+#define PHY_ANALOG_BB3_ADDRESS                                                                       0x00000148
+#define PHY_ANALOG_BB3_OFFSET                                                                        0x00000148
+#define PHY_ANALOG_BB3_SPARE_MSB                                                                             15
+#define PHY_ANALOG_BB3_SPARE_LSB                                                                              0
+#define PHY_ANALOG_BB3_SPARE_MASK                                                                    0x0000ffff
+#define PHY_ANALOG_BB3_SPARE_GET(x)                                                   (((x) & 0x0000ffff) >> 0)
+#define PHY_ANALOG_BB3_SPARE_SET(x)                                                   (((x) << 0) & 0x0000ffff)
+#define PHY_ANALOG_BB3_FILTERFC_MSB                                                                          20
+#define PHY_ANALOG_BB3_FILTERFC_LSB                                                                          16
+#define PHY_ANALOG_BB3_FILTERFC_MASK                                                                 0x001f0000
+#define PHY_ANALOG_BB3_FILTERFC_GET(x)                                               (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB                                                                      25
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB                                                                      21
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK                                                             0x03e00000
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x)                                           (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB                                                                      30
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB                                                                      26
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK                                                             0x7c000000
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x)                                           (((x) & 0x7c000000) >> 26)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB                                                                   31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB                                                                   31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK                                                          0x80000000
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x)                                        (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x)                                        (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA */
+#define PHY_ANALOG_PLLCLKMODA_ADDRESS                                                                0x00000280
+#define PHY_ANALOG_PLLCLKMODA_OFFSET                                                                 0x00000280
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB                                                                  0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB                                                                  0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK                                                        0x00000001
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB                                                                      1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB                                                                      1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK                                                            0x00000002
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x)                                           (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x)                                           (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB                                                                    16
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB                                                                     2
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK                                                           0x0001fffc
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x)                                          (((x) & 0x0001fffc) >> 2)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x)                                          (((x) << 2) & 0x0001fffc)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB                                                                     20
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB                                                                     17
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK                                                            0x001e0000
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x)                                          (((x) & 0x001e0000) >> 17)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x)                                          (((x) << 17) & 0x001e0000)
+#define PHY_ANALOG_PLLCLKMODA_DIV_MSB                                                                        30
+#define PHY_ANALOG_PLLCLKMODA_DIV_LSB                                                                        21
+#define PHY_ANALOG_PLLCLKMODA_DIV_MASK                                                               0x7fe00000
+#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x)                                             (((x) & 0x7fe00000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x)                                             (((x) << 21) & 0x7fe00000)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB                                                                  31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB                                                                  31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK                                                         0x80000000
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x)                                       (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x)                                       (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA2 */
+#define PHY_ANALOG_PLLCLKMODA2_ADDRESS                                                               0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_OFFSET                                                                0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB                                                                      3
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB                                                                      0
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK                                                            0x0000000f
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x)                                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x)                                           (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB                                                                     4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB                                                                     4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK                                                           0x00000010
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x)                                          (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x)                                          (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB                                                                     5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB                                                                     5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK                                                           0x00000020
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x)                                          (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x)                                          (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB                                                                6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB                                                                6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK                                                      0x00000040
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x)                                     (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x)                                     (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB                                                                8
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB                                                                7
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK                                                      0x00000180
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x)                                     (((x) & 0x00000180) >> 7)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x)                                     (((x) << 7) & 0x00000180)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB                                                               12
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB                                                                9
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK                                                      0x00001e00
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x)                                     (((x) & 0x00001e00) >> 9)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x)                                     (((x) << 9) & 0x00001e00)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB                                                             13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB                                                             13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK                                                    0x00002000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x)                                  (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x)                                  (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB                                                                 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB                                                                 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK                                                        0x00004000
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x)                                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x)                                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB                                                           15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB                                                           15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK                                                  0x00008000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB                                                                    17
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB                                                                    16
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK                                                           0x00030000
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x)                                         (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x)                                         (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB                                                                 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB                                                                 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK                                                        0x00040000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x)                                      (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x)                                      (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB                                                                19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB                                                                19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK                                                       0x00080000
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x)                                     (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x)                                     (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB                                                            20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB                                                            20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK                                                   0x00100000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x)                                 (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x)                                 (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB                                                              21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB                                                              21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK                                                     0x00200000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x)                                   (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x)                                   (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB                                                                  23
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB                                                                  22
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK                                                         0x00c00000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x)                                       (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x)                                       (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB                                                                    26
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB                                                                    24
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK                                                           0x07000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x)                                         (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x)                                         (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB                                                                 31
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB                                                                 27
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK                                                        0xf8000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x)                                      (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x)                                      (((x) << 27) & 0xf8000000)
+
+/* macros for TOP */
+#define PHY_ANALOG_TOP_ADDRESS                                                                       0x00000288
+#define PHY_ANALOG_TOP_OFFSET                                                                        0x00000288
+#define PHY_ANALOG_TOP_SPARE_MSB                                                                              2
+#define PHY_ANALOG_TOP_SPARE_LSB                                                                              0
+#define PHY_ANALOG_TOP_SPARE_MASK                                                                    0x00000007
+#define PHY_ANALOG_TOP_SPARE_GET(x)                                                   (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TOP_SPARE_SET(x)                                                   (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TOP_PWDBIAS_MSB                                                                            3
+#define PHY_ANALOG_TOP_PWDBIAS_LSB                                                                            3
+#define PHY_ANALOG_TOP_PWDBIAS_MASK                                                                  0x00000008
+#define PHY_ANALOG_TOP_PWDBIAS_GET(x)                                                 (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP_PWDBIAS_SET(x)                                                 (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB                                                                       4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB                                                                       4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK                                                             0x00000010
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x)                                            (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x)                                            (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP_XPAON2_MSB                                                                             5
+#define PHY_ANALOG_TOP_XPAON2_LSB                                                                             5
+#define PHY_ANALOG_TOP_XPAON2_MASK                                                                   0x00000020
+#define PHY_ANALOG_TOP_XPAON2_GET(x)                                                  (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP_XPAON2_SET(x)                                                  (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP_XPAON5_MSB                                                                             6
+#define PHY_ANALOG_TOP_XPAON5_LSB                                                                             6
+#define PHY_ANALOG_TOP_XPAON5_MASK                                                                   0x00000040
+#define PHY_ANALOG_TOP_XPAON5_GET(x)                                                  (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP_XPAON5_SET(x)                                                  (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP_XPASHORT2GND_MSB                                                                       7
+#define PHY_ANALOG_TOP_XPASHORT2GND_LSB                                                                       7
+#define PHY_ANALOG_TOP_XPASHORT2GND_MASK                                                             0x00000080
+#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP_XPABIASLVL_MSB                                                                        11
+#define PHY_ANALOG_TOP_XPABIASLVL_LSB                                                                         8
+#define PHY_ANALOG_TOP_XPABIASLVL_MASK                                                               0x00000f00
+#define PHY_ANALOG_TOP_XPABIASLVL_GET(x)                                              (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TOP_XPABIASLVL_SET(x)                                              (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TOP_XPABIAS_EN_MSB                                                                        12
+#define PHY_ANALOG_TOP_XPABIAS_EN_LSB                                                                        12
+#define PHY_ANALOG_TOP_XPABIAS_EN_MASK                                                               0x00001000
+#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x)                                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x)                                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP_ATBSELECT_MSB                                                                         13
+#define PHY_ANALOG_TOP_ATBSELECT_LSB                                                                         13
+#define PHY_ANALOG_TOP_ATBSELECT_MASK                                                                0x00002000
+#define PHY_ANALOG_TOP_ATBSELECT_GET(x)                                              (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP_ATBSELECT_SET(x)                                              (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP_LOCAL_XPA_MSB                                                                         14
+#define PHY_ANALOG_TOP_LOCAL_XPA_LSB                                                                         14
+#define PHY_ANALOG_TOP_LOCAL_XPA_MASK                                                                0x00004000
+#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x)                                              (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x)                                              (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB                                                                    15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB                                                                    15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK                                                           0x00008000
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB                                                                      16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB                                                                      16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK                                                             0x00010000
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB                                                                      17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB                                                                      17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK                                                             0x00020000
+#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x)                                           (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x)                                           (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB                                                                       18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB                                                                       18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK                                                              0x00040000
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x)                                            (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x)                                            (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB                                                                      19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB                                                                      19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK                                                             0x00080000
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x)                                           (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x)                                           (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TOP_PAD2GND_MSB                                                                           20
+#define PHY_ANALOG_TOP_PAD2GND_LSB                                                                           20
+#define PHY_ANALOG_TOP_PAD2GND_MASK                                                                  0x00100000
+#define PHY_ANALOG_TOP_PAD2GND_GET(x)                                                (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP_PAD2GND_SET(x)                                                (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP_INTH2PAD_MSB                                                                          21
+#define PHY_ANALOG_TOP_INTH2PAD_LSB                                                                          21
+#define PHY_ANALOG_TOP_INTH2PAD_MASK                                                                 0x00200000
+#define PHY_ANALOG_TOP_INTH2PAD_GET(x)                                               (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP_INTH2PAD_SET(x)                                               (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP_INTH2GND_MSB                                                                          22
+#define PHY_ANALOG_TOP_INTH2GND_LSB                                                                          22
+#define PHY_ANALOG_TOP_INTH2GND_MASK                                                                 0x00400000
+#define PHY_ANALOG_TOP_INTH2GND_GET(x)                                               (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP_INTH2GND_SET(x)                                               (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP_INT2PAD_MSB                                                                           23
+#define PHY_ANALOG_TOP_INT2PAD_LSB                                                                           23
+#define PHY_ANALOG_TOP_INT2PAD_MASK                                                                  0x00800000
+#define PHY_ANALOG_TOP_INT2PAD_GET(x)                                                (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP_INT2PAD_SET(x)                                                (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP_INT2GND_MSB                                                                           24
+#define PHY_ANALOG_TOP_INT2GND_LSB                                                                           24
+#define PHY_ANALOG_TOP_INT2GND_MASK                                                                  0x01000000
+#define PHY_ANALOG_TOP_INT2GND_GET(x)                                                (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP_INT2GND_SET(x)                                                (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP_PWDPALCLK_MSB                                                                         25
+#define PHY_ANALOG_TOP_PWDPALCLK_LSB                                                                         25
+#define PHY_ANALOG_TOP_PWDPALCLK_MASK                                                                0x02000000
+#define PHY_ANALOG_TOP_PWDPALCLK_GET(x)                                              (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP_PWDPALCLK_SET(x)                                              (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB                                                                    26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB                                                                    26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK                                                           0x04000000
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x)                                         (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x)                                         (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB                                                                     27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB                                                                     27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK                                                            0x08000000
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x)                                          (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x)                                          (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB                                                                    28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB                                                                    28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK                                                           0x10000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x)                                         (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x)                                         (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB                                                                    29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB                                                                    29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK                                                           0x20000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x)                                         (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x)                                         (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP_CLK_SEL_MSB                                                                           31
+#define PHY_ANALOG_TOP_CLK_SEL_LSB                                                                           30
+#define PHY_ANALOG_TOP_CLK_SEL_MASK                                                                  0xc0000000
+#define PHY_ANALOG_TOP_CLK_SEL_GET(x)                                                (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TOP_CLK_SEL_SET(x)                                                (((x) << 30) & 0xc0000000)
+
+/* macros for THERM */
+#define PHY_ANALOG_THERM_ADDRESS                                                                     0x0000028c
+#define PHY_ANALOG_THERM_OFFSET                                                                      0x0000028c
+#define PHY_ANALOG_THERM_LOREG_LVL_MSB                                                                        2
+#define PHY_ANALOG_THERM_LOREG_LVL_LSB                                                                        0
+#define PHY_ANALOG_THERM_LOREG_LVL_MASK                                                              0x00000007
+#define PHY_ANALOG_THERM_LOREG_LVL_GET(x)                                             (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_THERM_LOREG_LVL_SET(x)                                             (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_THERM_RFREG_LVL_MSB                                                                        5
+#define PHY_ANALOG_THERM_RFREG_LVL_LSB                                                                        3
+#define PHY_ANALOG_THERM_RFREG_LVL_MASK                                                              0x00000038
+#define PHY_ANALOG_THERM_RFREG_LVL_GET(x)                                             (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_THERM_RFREG_LVL_SET(x)                                             (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB                                                                     6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB                                                                     6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK                                                           0x00000040
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x)                                          (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB                                                                     14
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB                                                                      7
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK                                                            0x00007f80
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x)                                           (((x) & 0x00007f80) >> 7)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB                                                                22
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB                                                                15
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK                                                       0x007f8000
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x)                                     (((x) & 0x007f8000) >> 15)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x)                                     (((x) << 15) & 0x007f8000)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB                                                                  23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB                                                                  23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK                                                         0x00800000
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x)                                       (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x)                                       (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB                                                                   24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB                                                                   24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK                                                          0x01000000
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x)                                        (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x)                                        (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_THERM_THERMSEL_MSB                                                                        26
+#define PHY_ANALOG_THERM_THERMSEL_LSB                                                                        25
+#define PHY_ANALOG_THERM_THERMSEL_MASK                                                               0x06000000
+#define PHY_ANALOG_THERM_THERMSEL_GET(x)                                             (((x) & 0x06000000) >> 25)
+#define PHY_ANALOG_THERM_THERMSEL_SET(x)                                             (((x) << 25) & 0x06000000)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB                                                                     27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB                                                                     27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK                                                            0x08000000
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x)                                          (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x)                                          (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_THERM_THERMSTART_MSB                                                                      28
+#define PHY_ANALOG_THERM_THERMSTART_LSB                                                                      28
+#define PHY_ANALOG_THERM_THERMSTART_MASK                                                             0x10000000
+#define PHY_ANALOG_THERM_THERMSTART_GET(x)                                           (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_THERM_THERMSTART_SET(x)                                           (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB                                                                  29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB                                                                  29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK                                                         0x20000000
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x)                                       (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x)                                       (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_THERM_THERMON_MSB                                                                         30
+#define PHY_ANALOG_THERM_THERMON_LSB                                                                         30
+#define PHY_ANALOG_THERM_THERMON_MASK                                                                0x40000000
+#define PHY_ANALOG_THERM_THERMON_GET(x)                                              (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_THERM_THERMON_SET(x)                                              (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_THERM_LOCAL_THERM_MSB                                                                     31
+#define PHY_ANALOG_THERM_LOCAL_THERM_LSB                                                                     31
+#define PHY_ANALOG_THERM_LOCAL_THERM_MASK                                                            0x80000000
+#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x)                                          (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x)                                          (((x) << 31) & 0x80000000)
+
+/* macros for XTAL */
+#define PHY_ANALOG_XTAL_ADDRESS                                                                      0x00000290
+#define PHY_ANALOG_XTAL_OFFSET                                                                       0x00000290
+#define PHY_ANALOG_XTAL_SPARE_MSB                                                                             5
+#define PHY_ANALOG_XTAL_SPARE_LSB                                                                             0
+#define PHY_ANALOG_XTAL_SPARE_MASK                                                                   0x0000003f
+#define PHY_ANALOG_XTAL_SPARE_GET(x)                                                  (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_XTAL_SPARE_SET(x)                                                  (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB                                                                    6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB                                                                    6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK                                                          0x00000040
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x)                                         (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x)                                         (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB                                                                       7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB                                                                       7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK                                                             0x00000080
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x)                                            (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x)                                            (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB                                                                        8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB                                                                        8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK                                                              0x00000100
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x)                                             (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x)                                             (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB                                                                     9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB                                                                     9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK                                                           0x00000200
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x)                                          (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x)                                          (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB                                                                       10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB                                                                       10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK                                                              0x00000400
+#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x)                                            (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x)                                            (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB                                                                     11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB                                                                     11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK                                                            0x00000800
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x)                                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x)                                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB                                                                   12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB                                                                   12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK                                                          0x00001000
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x)                                        (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x)                                        (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB                                                                     13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB                                                                     13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK                                                            0x00002000
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB                                                                      15
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB                                                                      14
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK                                                             0x0000c000
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x)                                           (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x)                                           (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB                                                                   22
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB                                                                   16
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK                                                          0x007f0000
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x)                                        (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x)                                        (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB                                                                    29
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB                                                                    23
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK                                                           0x3f800000
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x)                                         (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x)                                         (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB                                                                      30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB                                                                      30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK                                                             0x40000000
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x)                                           (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x)                                           (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_XTAL_TCXODET_MSB                                                                          31
+#define PHY_ANALOG_XTAL_TCXODET_LSB                                                                          31
+#define PHY_ANALOG_XTAL_TCXODET_MASK                                                                 0x80000000
+#define PHY_ANALOG_XTAL_TCXODET_GET(x)                                               (((x) & 0x80000000) >> 31)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS                                                               0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET                                                                0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB                                                      0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK                                            0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB                                                   1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK                                         0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x)                        (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB                                                   2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK                                         0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x)                        (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x)                        (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB                                                 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK                                       0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x)                      (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x)                      (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB                                               4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK                                     0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x)                    (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x)                    (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB                                               5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK                                     0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x)                    (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x)                    (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB                                                  6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK                                        0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x)                       (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x)                       (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB                                                  7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK                                        0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB                                                8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK                                      0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x)                     (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x)                     (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB                                                         9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK                                               0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x)                              (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x)                              (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB                                                      10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK                                             0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB                                                     11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK                                            0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x)                          (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB                                                        12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK                                               0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x)                             (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x)                             (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB                                                      13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK                                             0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x)                           (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x)                           (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB                                                 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK                                        0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x)                      (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x)                      (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB                                                       15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK                                              0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x)                            (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x)                            (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB                                                          16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK                                                 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x)                               (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x)                               (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB                                                        17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK                                               0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x)                             (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x)                             (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS                                                              0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET                                                               0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB                                                         10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB                                                          0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK                                                0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x)                               (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x)                               (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB                                                         26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB                                                         16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK                                                0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x)                              (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS                                                               0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET                                                                0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS                                                               0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET                                                                0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB                                                      6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB                                                      0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK                                            0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x)                           (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x)                           (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB                                                    11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB                                                     8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK                                           0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x)                          (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x)                          (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB                                                    23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB                                                    16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK                                           0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB                                                    30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB                                                    24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK                                           0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x)                         (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x)                         (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS                                                             0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET                                                              0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB                                                    6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB                                                    0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK                                          0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x)                         (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x)                         (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB                                                  11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB                                                   8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK                                         0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x)                        (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x)                        (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB                                                  23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB                                                  16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK                                         0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB                                                  30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB                                                  24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK                                         0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x)                       (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x)                       (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS                                                          0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET                                                           0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS                                                          0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET                                                           0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB                                             10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB                                              0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK                                    0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x)                   (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x)                   (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB                                            21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB                                            12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK                                   0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x)                 (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x)                 (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB                                             29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB                                             24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK                                    0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x)                  (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x)                  (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS                                                               0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET                                                                0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB                                               9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB                                               0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK                                     0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x)                    (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB                                              25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB                                              16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK                                     0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x)                   (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x)                   (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS                                                            0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET                                                             0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS                                                            0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET                                                             0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB                                                  30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB                                                   0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK                                         0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x)                        (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x)                        (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS                                                            0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET                                                             0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB                                                    9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB                                                    0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK                                          0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x)                         (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x)                         (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB                                                   25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB                                                   16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK                                          0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x)                        (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x)                        (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS                                                            0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET                                                             0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB                                                      3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB                                                      0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK                                            0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x)                           (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x)                           (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS                                                                 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET                                                                  0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB                                                         4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK                                               0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB                                                          13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB                                                           8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK                                                 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x)                                (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS                                                                0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET                                                                 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB                                                       3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB                                                       0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK                                             0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x)                            (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x)                            (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS                                                           0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET                                                            0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB                                                     3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB                                                     0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK                                           0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x)                          (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x)                          (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS                                                                 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET                                                                  0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB                                                         3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB                                                         0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK                                               0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x)                              (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x)                              (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS                                                            0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET                                                             0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB                                               3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB                                               0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK                                     0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB                                                 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB                                                 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK                                       0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x)                      (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x)                      (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS                                                                0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET                                                                 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB                                                               1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB                                                               0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK                                                     0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x)                                    (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x)                                    (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB                                                           4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK                                                 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x)                                (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x)                                (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB                                                         13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB                                                          8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK                                                0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB                                                 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB                                                 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK                                        0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x)                      (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x)                      (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS                                                                0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET                                                                 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB                                                              4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB                                                              0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK                                                    0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x)                                   (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x)                                   (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB                                                             12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB                                                              8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK                                                    0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x)                                   (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x)                                   (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB                                                            20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB                                                            16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK                                                   0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x)                                 (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x)                                 (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB                                                            28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB                                                            24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK                                                   0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x)                                 (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x)                                 (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS                                                          0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET                                                           0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB                                                    4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB                                                    0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK                                          0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x)                         (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x)                         (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB                                                   12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB                                                    8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK                                          0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x)                         (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x)                         (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS                                                            0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET                                                             0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS                                                            0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET                                                             0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB                                                       31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB                                                        0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK                                              0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x)                             (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x)                             (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS                                                                      0x00000740
+#define PHY_ANALOG_PMU1_OFFSET                                                                       0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB                                                                            10
+#define PHY_ANALOG_PMU1_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU1_SPARE_MASK                                                                   0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x)                                                  (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x)                                                  (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB                                                                      11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK                                                             0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x)                                           (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x)                                           (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB                                                                     13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB                                                                       14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK                                                              0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x)                                            (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x)                                            (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB                                                                    15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK                                                           0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x)                                         (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x)                                         (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB                                                                      16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK                                                             0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x)                                           (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x)                                           (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB                                                                    18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB                                                                    17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK                                                           0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x)                                         (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x)                                         (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB                                                                    21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB                                                                    19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK                                                           0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x)                                         (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x)                                         (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB                                                                     23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB                                                                     22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK                                                            0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x)                                          (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x)                                          (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB                                                                      25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB                                                                      24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK                                                             0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x)                                           (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x)                                           (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB                                                                      27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB                                                                      26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK                                                             0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x)                                           (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x)                                           (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB                                                                       28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB                                                                     31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB                                                                     29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK                                                            0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x)                                          (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x)                                          (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS                                                                      0x00000744
+#define PHY_ANALOG_PMU2_OFFSET                                                                       0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB                                                                             7
+#define PHY_ANALOG_PMU2_SPARE_LSB                                                                             0
+#define PHY_ANALOG_PMU2_SPARE_MASK                                                                   0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x)                                                  (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x)                                                  (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB                                                                    8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK                                                          0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x)                                         (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x)                                         (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB                                                                    9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK                                                          0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x)                                         (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x)                                         (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB                                                                   10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK                                                          0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x)                                        (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x)                                        (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB                                                                  11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK                                                         0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x)                                       (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x)                                       (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB                                                                      12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK                                                             0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x)                                           (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x)                                           (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB                                                                     13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK                                                            0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x)                                          (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x)                                          (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB                                                                     14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK                                                            0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x)                                          (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x)                                          (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB                                                                     15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK                                                            0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x)                                          (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x)                                          (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB                                                              16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK                                                     0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB                                                                  18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB                                                                  17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK                                                         0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x)                                       (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x)                                       (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB                                                                    19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK                                                           0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x)                                         (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x)                                         (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB                                                                 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB                                                                 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK                                                        0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x)                                      (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x)                                      (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB                                                                    22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK                                                           0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x)                                         (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x)                                         (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB                                                                 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB                                                                 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK                                                        0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x)                                      (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x)                                      (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB                                                                        27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB                                                                        25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK                                                               0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x)                                             (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x)                                             (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB                                                                       28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK                                                              0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x)                                            (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x)                                            (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB                                                                    30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB                                                                    29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK                                                           0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x)                                         (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x)                                         (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB                                                            31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK                                                   0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x)                                 (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x)                                 (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_athr_wlan_reg_reg_s {
+  volatile unsigned int RXRF_BIAS1;                                    /*        0x0 - 0x4        */
+  volatile unsigned int RXRF_BIAS2;                                    /*        0x4 - 0x8        */
+  volatile unsigned int RXRF_GAINSTAGES;                               /*        0x8 - 0xc        */
+  volatile unsigned int RXRF_AGC;                                      /*        0xc - 0x10       */
+  volatile char pad__0[0x30];                                          /*       0x10 - 0x40       */
+  volatile unsigned int TXRF1;                                         /*       0x40 - 0x44       */
+  volatile unsigned int TXRF2;                                         /*       0x44 - 0x48       */
+  volatile unsigned int TXRF3;                                         /*       0x48 - 0x4c       */
+  volatile unsigned int TXRF4;                                         /*       0x4c - 0x50       */
+  volatile unsigned int TXRF5;                                         /*       0x50 - 0x54       */
+  volatile unsigned int TXRF6;                                         /*       0x54 - 0x58       */
+  volatile unsigned int TXRF7;                                         /*       0x58 - 0x5c       */
+  volatile unsigned int TXRF8;                                         /*       0x5c - 0x60       */
+  volatile unsigned int TXRF9;                                         /*       0x60 - 0x64       */
+  volatile unsigned int TXRF10;                                        /*       0x64 - 0x68       */
+  volatile unsigned int TXRF11;                                        /*       0x68 - 0x6c       */
+  volatile unsigned int TXRF12;                                        /*       0x6c - 0x70       */
+  volatile char pad__1[0x10];                                          /*       0x70 - 0x80       */
+  volatile unsigned int SYNTH1;                                        /*       0x80 - 0x84       */
+  volatile unsigned int SYNTH2;                                        /*       0x84 - 0x88       */
+  volatile unsigned int SYNTH3;                                        /*       0x88 - 0x8c       */
+  volatile unsigned int SYNTH4;                                        /*       0x8c - 0x90       */
+  volatile unsigned int SYNTH5;                                        /*       0x90 - 0x94       */
+  volatile unsigned int SYNTH6;                                        /*       0x94 - 0x98       */
+  volatile unsigned int SYNTH7;                                        /*       0x98 - 0x9c       */
+  volatile unsigned int SYNTH8;                                        /*       0x9c - 0xa0       */
+  volatile unsigned int SYNTH9;                                        /*       0xa0 - 0xa4       */
+  volatile unsigned int SYNTH10;                                       /*       0xa4 - 0xa8       */
+  volatile unsigned int SYNTH11;                                       /*       0xa8 - 0xac       */
+  volatile unsigned int SYNTH12;                                       /*       0xac - 0xb0       */
+  volatile unsigned int SYNTH13;                                       /*       0xb0 - 0xb4       */
+  volatile unsigned int SYNTH14;                                       /*       0xb4 - 0xb8       */
+  volatile char pad__2[0x8];                                           /*       0xb8 - 0xc0       */
+  volatile unsigned int BIAS1;                                         /*       0xc0 - 0xc4       */
+  volatile unsigned int BIAS2;                                         /*       0xc4 - 0xc8       */
+  volatile unsigned int BIAS3;                                         /*       0xc8 - 0xcc       */
+  volatile unsigned int BIAS4;                                         /*       0xcc - 0xd0       */
+  volatile char pad__3[0x30];                                          /*       0xd0 - 0x100      */
+  volatile unsigned int RXTX1;                                         /*      0x100 - 0x104      */
+  volatile unsigned int RXTX2;                                         /*      0x104 - 0x108      */
+  volatile unsigned int RXTX3;                                         /*      0x108 - 0x10c      */
+  volatile char pad__4[0x34];                                          /*      0x10c - 0x140      */
+  volatile unsigned int BB1;                                           /*      0x140 - 0x144      */
+  volatile unsigned int BB2;                                           /*      0x144 - 0x148      */
+  volatile unsigned int BB3;                                           /*      0x148 - 0x14c      */
+  volatile char pad__5[0x134];                                         /*      0x14c - 0x280      */
+  volatile unsigned int PLLCLKMODA;                                    /*      0x280 - 0x284      */
+  volatile unsigned int PLLCLKMODA2;                                   /*      0x284 - 0x288      */
+  volatile unsigned int TOP;                                           /*      0x288 - 0x28c      */
+  volatile unsigned int THERM;                                         /*      0x28c - 0x290      */
+  volatile unsigned int XTAL;                                          /*      0x290 - 0x294      */
+  volatile char pad__6[0xec];                                          /*      0x294 - 0x380      */
+  volatile unsigned int rbist_cntrl;                                   /*      0x380 - 0x384      */
+  volatile unsigned int tx_dc_offset;                                  /*      0x384 - 0x388      */
+  volatile unsigned int tx_tonegen0;                                   /*      0x388 - 0x38c      */
+  volatile unsigned int tx_tonegen1;                                   /*      0x38c - 0x390      */
+  volatile unsigned int tx_lftonegen0;                                 /*      0x390 - 0x394      */
+  volatile unsigned int tx_linear_ramp_i;                              /*      0x394 - 0x398      */
+  volatile unsigned int tx_linear_ramp_q;                              /*      0x398 - 0x39c      */
+  volatile unsigned int tx_prbs_mag;                                   /*      0x39c - 0x3a0      */
+  volatile unsigned int tx_prbs_seed_i;                                /*      0x3a0 - 0x3a4      */
+  volatile unsigned int tx_prbs_seed_q;                                /*      0x3a4 - 0x3a8      */
+  volatile unsigned int cmac_dc_cancel;                                /*      0x3a8 - 0x3ac      */
+  volatile unsigned int cmac_dc_offset;                                /*      0x3ac - 0x3b0      */
+  volatile unsigned int cmac_corr;                                     /*      0x3b0 - 0x3b4      */
+  volatile unsigned int cmac_power;                                    /*      0x3b4 - 0x3b8      */
+  volatile unsigned int cmac_cross_corr;                               /*      0x3b8 - 0x3bc      */
+  volatile unsigned int cmac_i2q2;                                     /*      0x3bc - 0x3c0      */
+  volatile unsigned int cmac_power_hpf;                                /*      0x3c0 - 0x3c4      */
+  volatile unsigned int rxdac_set1;                                    /*      0x3c4 - 0x3c8      */
+  volatile unsigned int rxdac_set2;                                    /*      0x3c8 - 0x3cc      */
+  volatile unsigned int rxdac_long_shift;                              /*      0x3cc - 0x3d0      */
+  volatile unsigned int cmac_results_i;                                /*      0x3d0 - 0x3d4      */
+  volatile unsigned int cmac_results_q;                                /*      0x3d4 - 0x3d8      */
+  volatile char pad__7[0x368];                                         /*      0x3d8 - 0x740      */
+  volatile unsigned int PMU1;                                          /*      0x740 - 0x744      */
+  volatile unsigned int PMU2;                                          /*      0x744 - 0x748      */
+} analog_intf_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..7e6320d28ac6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "analog_intf_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h
new file mode 100644
index 000000000000..143460719bbf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h
@@ -0,0 +1,36 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_ATHR_WLAN_MAP_H_
+#define _APB_ATHR_WLAN_MAP_H_
+
+#define WLAN_RTC_BASE_ADDRESS                    0x00004000
+#define WLAN_VMC_BASE_ADDRESS                    0x00008000
+#define WLAN_UART_BASE_ADDRESS                   0x0000c000
+#define WLAN_DBG_UART_BASE_ADDRESS               0x0000d000
+#define WLAN_UMBOX_BASE_ADDRESS                  0x0000e000
+#define WLAN_SI_BASE_ADDRESS                     0x00010000
+#define WLAN_GPIO_BASE_ADDRESS                   0x00014000
+#define WLAN_MBOX_BASE_ADDRESS                   0x00018000
+#define WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
+#define WLAN_MAC_BASE_ADDRESS                    0x00020000
+#define WLAN_RDMA_BASE_ADDRESS                   0x00030100
+#define EFUSE_BASE_ADDRESS                       0x00031000
+
+#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h
new file mode 100644
index 000000000000..6c85e2643d24
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h
@@ -0,0 +1,44 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "apb_athr_wlan_map.h"
+
+
+#ifndef BT_HEADERS
+
+#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
+#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
+#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
+#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
+#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
+#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
+#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
+#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
+#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
+#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
+#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h
new file mode 100644
index 000000000000..61827bc79cba
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h
@@ -0,0 +1,7072 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc.  All rights reserved              */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
+
+
+#ifndef _BB_LC_REG_REG_H_
+#define _BB_LC_REG_REG_H_
+
+
+/* macros for BB_test_controls */
+#define PHY_BB_TEST_CONTROLS_ADDRESS                                                          0x00009800
+#define PHY_BB_TEST_CONTROLS_OFFSET                                                           0x00009800
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB                                                        3
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB                                                        0
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK                                              0x0000000f
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x)                             (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x)                             (((x) << 0) & 0x0000000f)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB                                                            4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB                                                            4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK                                                  0x00000010
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x)                                 (((x) & 0x00000010) >> 4)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x)                                 (((x) << 4) & 0x00000010)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB                                                        6
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB                                                        5
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK                                              0x00000060
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x)                             (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x)                             (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB                                                          9
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB                                                          8
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK                                                0x00000300
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x)                               (((x) & 0x00000300) >> 8)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x)                               (((x) << 8) & 0x00000300)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB                                                      10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB                                                      10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK                                             0x00000400
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x)                           (((x) & 0x00000400) >> 10)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x)                           (((x) << 10) & 0x00000400)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB                                                   13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB                                                   13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK                                          0x00002000
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x)                        (((x) & 0x00002000) >> 13)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x)                        (((x) << 13) & 0x00002000)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB                                                      15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB                                                      15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK                                             0x00008000
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB                                                          17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB                                                          17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK                                                 0x00020000
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x)                               (((x) & 0x00020000) >> 17)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x)                               (((x) << 17) & 0x00020000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB                                                        18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB                                                        18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK                                               0x00040000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x)                             (((x) & 0x00040000) >> 18)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x)                             (((x) << 18) & 0x00040000)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB                                                       22
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB                                                       19
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK                                              0x00780000
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x)                            (((x) & 0x00780000) >> 19)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x)                            (((x) << 19) & 0x00780000)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB                                                   23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB                                                   23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK                                          0x00800000
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x)                        (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x)                        (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB                                                        24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB                                                        24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK                                               0x01000000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x)                             (((x) & 0x01000000) >> 24)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x)                             (((x) << 24) & 0x01000000)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB                                                      28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB                                                      28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK                                             0x10000000
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x)                           (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x)                           (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB                                                       31
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB                                                       30
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK                                              0xc0000000
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x)                            (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x)                            (((x) << 30) & 0xc0000000)
+
+/* macros for BB_gen_controls */
+#define PHY_BB_GEN_CONTROLS_ADDRESS                                                           0x00009804
+#define PHY_BB_GEN_CONTROLS_OFFSET                                                            0x00009804
+#define PHY_BB_GEN_CONTROLS_TURBO_MSB                                                                  0
+#define PHY_BB_GEN_CONTROLS_TURBO_LSB                                                                  0
+#define PHY_BB_GEN_CONTROLS_TURBO_MASK                                                        0x00000001
+#define PHY_BB_GEN_CONTROLS_TURBO_GET(x)                                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_GEN_CONTROLS_TURBO_SET(x)                                       (((x) << 0) & 0x00000001)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB                                                             1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB                                                             1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK                                                   0x00000002
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x)                                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x)                                  (((x) << 1) & 0x00000002)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB                                                              2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB                                                              2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK                                                    0x00000004
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x)                                   (((x) & 0x00000004) >> 2)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x)                                   (((x) << 2) & 0x00000004)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB                                                     3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB                                                     3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK                                           0x00000008
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x)                          (((x) & 0x00000008) >> 3)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x)                          (((x) << 3) & 0x00000008)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB                                                      4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB                                                      4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK                                            0x00000010
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x)                           (((x) & 0x00000010) >> 4)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x)                           (((x) << 4) & 0x00000010)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB                                                      5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB                                                      5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK                                            0x00000020
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x)                           (((x) & 0x00000020) >> 5)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x)                           (((x) << 5) & 0x00000020)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB                                                              6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB                                                              6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK                                                    0x00000040
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x)                                   (((x) & 0x00000040) >> 6)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x)                                   (((x) << 6) & 0x00000040)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB                                                         7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB                                                         7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK                                               0x00000080
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x)                              (((x) & 0x00000080) >> 7)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x)                              (((x) << 7) & 0x00000080)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB                                                  8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB                                                  8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK                                        0x00000100
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x)                       (((x) & 0x00000100) >> 8)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x)                       (((x) << 8) & 0x00000100)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB                                                      9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB                                                      9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK                                            0x00000200
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x)                           (((x) & 0x00000200) >> 9)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x)                           (((x) << 9) & 0x00000200)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB                                                             10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB                                                             10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK                                                    0x00000400
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x)                                  (((x) & 0x00000400) >> 10)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x)                                  (((x) << 10) & 0x00000400)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB                                                     11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB                                                     11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK                                            0x00000800
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x)                          (((x) & 0x00000800) >> 11)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x)                          (((x) << 11) & 0x00000800)
+
+/* macros for BB_test_controls_status */
+#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS                                                   0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET                                                    0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB                                                   0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB                                                   0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK                                         0x00000001
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x)                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x)                        (((x) << 0) & 0x00000001)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB                                            1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB                                            1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK                                  0x00000002
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x)                 (((x) & 0x00000002) >> 1)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x)                 (((x) << 1) & 0x00000002)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB                                                  4
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB                                                  2
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK                                        0x0000001c
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x)                       (((x) & 0x0000001c) >> 2)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x)                       (((x) << 2) & 0x0000001c)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB                                              6
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB                                              5
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK                                    0x00000060
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x)                   (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x)                   (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB                                            7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB                                            7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK                                  0x00000080
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x)                 (((x) & 0x00000080) >> 7)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x)                 (((x) << 7) & 0x00000080)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB                                                   8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB                                                   8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK                                         0x00000100
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x)                        (((x) & 0x00000100) >> 8)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x)                        (((x) << 8) & 0x00000100)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB                                            9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB                                            9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK                                  0x00000200
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x)                 (((x) & 0x00000200) >> 9)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x)                 (((x) << 9) & 0x00000200)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB                                                    13
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB                                                    10
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK                                           0x00003c00
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x)                         (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x)                         (((x) << 10) & 0x00003c00)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB                                         14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB                                         14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK                                0x00004000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x)              (((x) & 0x00004000) >> 14)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x)              (((x) << 14) & 0x00004000)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB                                                      15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB                                                      15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK                                             0x00008000
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB                                                   18
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB                                                   16
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK                                          0x00070000
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x)                        (((x) & 0x00070000) >> 16)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x)                        (((x) << 16) & 0x00070000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB                                            19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB                                            19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK                                   0x00080000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x)                 (((x) & 0x00080000) >> 19)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x)                 (((x) << 19) & 0x00080000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB                                               23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB                                               23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK                                      0x00800000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x)                    (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x)                    (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB                                             27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB                                             27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK                                    0x08000000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x)                  (((x) & 0x08000000) >> 27)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x)                  (((x) << 27) & 0x08000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB                                               28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB                                               28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK                                      0x10000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x)                    (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x)                    (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB                                              30
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB                                              29
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK                                     0x60000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x)                   (((x) & 0x60000000) >> 29)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x)                   (((x) << 29) & 0x60000000)
+
+/* macros for BB_timing_controls_1 */
+#define PHY_BB_TIMING_CONTROLS_1_ADDRESS                                                      0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_OFFSET                                                       0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB                                                           6
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB                                                           0
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK                                                 0x0000007f
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x)                                (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x)                                (((x) << 0) & 0x0000007f)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB                                                     12
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB                                                      7
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK                                            0x00001f80
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x)                           (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x)                           (((x) << 7) & 0x00001f80)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB                                                   16
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB                                                   13
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK                                          0x0001e000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x)                        (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x)                        (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB                                               17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB                                               17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK                                      0x00020000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x)                    (((x) & 0x00020000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x)                    (((x) << 17) & 0x00020000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB                                               19
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB                                               18
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK                                      0x000c0000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x)                    (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x)                    (((x) << 18) & 0x000c0000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB                                                  21
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB                                                  20
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK                                         0x00300000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x)                       (((x) & 0x00300000) >> 20)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x)                       (((x) << 20) & 0x00300000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB                                              22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB                                              22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK                                     0x00400000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x)                   (((x) & 0x00400000) >> 22)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x)                   (((x) << 22) & 0x00400000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB                                                   23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB                                                   23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK                                          0x00800000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x)                        (((x) & 0x00800000) >> 23)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x)                        (((x) << 23) & 0x00800000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB                                            24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB                                            24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK                                   0x01000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x)                 (((x) & 0x01000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x)                 (((x) << 24) & 0x01000000)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB                                                      26
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB                                                      25
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK                                             0x06000000
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x)                           (((x) & 0x06000000) >> 25)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x)                           (((x) << 25) & 0x06000000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB                                              27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB                                              27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK                                     0x08000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x)                   (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x)                   (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB                                               28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB                                               28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK                                      0x10000000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x)                    (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x)                    (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB                                                30
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB                                                29
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK                                       0x60000000
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x)                     (((x) & 0x60000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x)                     (((x) << 29) & 0x60000000)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB                                                      31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB                                                      31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK                                             0x80000000
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_2 */
+#define PHY_BB_TIMING_CONTROLS_2_ADDRESS                                                      0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_OFFSET                                                       0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB                                          11
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB                                           0
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK                                 0x00000fff
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x)                (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x)                (((x) << 0) & 0x00000fff)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB                                           12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB                                           12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK                                  0x00001000
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x)                (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x)                (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB                                           13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB                                           13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK                                  0x00002000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x)                (((x) & 0x00002000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x)                (((x) << 13) & 0x00002000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB                                              14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB                                              14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK                                     0x00004000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x)                   (((x) & 0x00004000) >> 14)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x)                   (((x) << 14) & 0x00004000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB                                             15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB                                             15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK                                    0x00008000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x)                  (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x)                  (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB                                              22
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB                                              16
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK                                     0x007f0000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x)                   (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x)                   (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB                                                 26
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB                                                 24
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK                                        0x07000000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x)                      (((x) & 0x07000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x)                      (((x) << 24) & 0x07000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB                                                 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB                                                 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK                                        0x08000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x)                      (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x)                      (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB                                           28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB                                           28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK                                  0x10000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x)                (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x)                (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB                                                 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB                                                 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK                                        0x20000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x)                      (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x)                      (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB                                                     30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB                                                     30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK                                            0x40000000
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x)                          (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x)                          (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB                                            31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB                                            31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK                                   0x80000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x)                 (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x)                 (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_3 */
+#define PHY_BB_TIMING_CONTROLS_3_ADDRESS                                                      0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_OFFSET                                                       0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB                                               7
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB                                               0
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK                                     0x000000ff
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x)                    (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x)                    (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB                                                 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB                                                 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK                                       0x00000100
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x)                      (((x) & 0x00000100) >> 8)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x)                      (((x) << 8) & 0x00000100)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB                                                   9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB                                                   9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK                                         0x00000200
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x)                        (((x) & 0x00000200) >> 9)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x)                        (((x) << 9) & 0x00000200)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB                                               10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB                                               10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK                                      0x00000400
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x)                    (((x) & 0x00000400) >> 10)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x)                    (((x) << 10) & 0x00000400)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB                                            11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB                                            11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK                                   0x00000800
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x)                 (((x) & 0x00000800) >> 11)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x)                 (((x) << 11) & 0x00000800)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB                                                12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB                                                12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK                                       0x00001000
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x)                     (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x)                     (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB                                             16
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB                                             13
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK                                    0x0001e000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x)                  (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x)                  (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB                                             31
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB                                             17
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK                                    0xfffe0000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x)                  (((x) & 0xfffe0000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x)                  (((x) << 17) & 0xfffe0000)
+
+/* macros for BB_D2_chip_id */
+#define PHY_BB_D2_CHIP_ID_ADDRESS                                                             0x00009818
+#define PHY_BB_D2_CHIP_ID_OFFSET                                                              0x00009818
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB                                                                   7
+#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB                                                                   0
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK                                                         0x000000ff
+#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x)                                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_D2_CHIP_ID_ID_MSB                                                                      31
+#define PHY_BB_D2_CHIP_ID_ID_LSB                                                                       8
+#define PHY_BB_D2_CHIP_ID_ID_MASK                                                             0xffffff00
+#define PHY_BB_D2_CHIP_ID_ID_GET(x)                                            (((x) & 0xffffff00) >> 8)
+
+/* macros for BB_active */
+#define PHY_BB_ACTIVE_ADDRESS                                                                 0x0000981c
+#define PHY_BB_ACTIVE_OFFSET                                                                  0x0000981c
+#define PHY_BB_ACTIVE_CF_ACTIVE_MSB                                                                    0
+#define PHY_BB_ACTIVE_CF_ACTIVE_LSB                                                                    0
+#define PHY_BB_ACTIVE_CF_ACTIVE_MASK                                                          0x00000001
+#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x)                                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x)                                         (((x) << 0) & 0x00000001)
+
+/* macros for BB_tx_timing_1 */
+#define PHY_BB_TX_TIMING_1_ADDRESS                                                            0x00009820
+#define PHY_BB_TX_TIMING_1_OFFSET                                                             0x00009820
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB                                                     7
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB                                                     0
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK                                           0x000000ff
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB                                                  15
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB                                                   8
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK                                         0x0000ff00
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB                                                     23
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB                                                     16
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK                                            0x00ff0000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x)                          (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x)                          (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB                                                   31
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB                                                   24
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK                                          0xff000000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x)                        (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x)                        (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_2 */
+#define PHY_BB_TX_TIMING_2_ADDRESS                                                            0x00009824
+#define PHY_BB_TX_TIMING_2_OFFSET                                                             0x00009824
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB                                                  7
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB                                                  0
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK                                        0x000000ff
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB                                                      15
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB                                                       8
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK                                             0x0000ff00
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB                                                       23
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB                                                       16
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK                                              0x00ff0000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x)                            (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB                                                    31
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB                                                    24
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK                                           0xff000000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x)                         (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x)                         (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_3 */
+#define PHY_BB_TX_TIMING_3_ADDRESS                                                            0x00009828
+#define PHY_BB_TX_TIMING_3_OFFSET                                                             0x00009828
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB                                                       7
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB                                                       0
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK                                             0x000000ff
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x)                            (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x)                            (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB                                             15
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB                                              8
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK                                    0x0000ff00
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB                                                     23
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB                                                     16
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK                                            0x00ff0000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x)                          (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x)                          (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB                                                       31
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB                                                       24
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK                                              0xff000000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x)                            (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x)                            (((x) << 24) & 0xff000000)
+
+/* macros for BB_addac_parallel_control */
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS                                                 0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET                                                  0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB                                               12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB                                               12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK                                      0x00001000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x)                    (((x) & 0x00001000) >> 12)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x)                    (((x) << 12) & 0x00001000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB                                                  13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB                                                  13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK                                         0x00002000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x)                       (((x) & 0x00002000) >> 13)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x)                       (((x) << 13) & 0x00002000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB                                                  15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB                                                  15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK                                         0x00008000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x)                       (((x) & 0x00008000) >> 15)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x)                       (((x) << 15) & 0x00008000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB                                                28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB                                                28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK                                       0x10000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x)                     (((x) & 0x10000000) >> 28)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x)                     (((x) << 28) & 0x10000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB                                                   29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB                                                   29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK                                          0x20000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x)                        (((x) & 0x20000000) >> 29)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x)                        (((x) << 29) & 0x20000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB                                                   31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB                                                   31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK                                          0x80000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x)                        (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x)                        (((x) << 31) & 0x80000000)
+
+/* macros for BB_xpa_timing_control */
+#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS                                                     0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_OFFSET                                                      0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB                                              7
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB                                              0
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK                                    0x000000ff
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x)                   (((x) & 0x000000ff) >> 0)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x)                   (((x) << 0) & 0x000000ff)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB                                             15
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB                                              8
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK                                    0x0000ff00
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB                                              23
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB                                              16
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK                                     0x00ff0000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x)                   (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x)                   (((x) << 16) & 0x00ff0000)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB                                              31
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB                                              24
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK                                     0xff000000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x)                   (((x) & 0xff000000) >> 24)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x)                   (((x) << 24) & 0xff000000)
+
+/* macros for BB_misc_pa_control */
+#define PHY_BB_MISC_PA_CONTROL_ADDRESS                                                        0x00009838
+#define PHY_BB_MISC_PA_CONTROL_OFFSET                                                         0x00009838
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB                                                    0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB                                                    0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK                                          0x00000001
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x)                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x)                         (((x) << 0) & 0x00000001)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB                                                    1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB                                                    1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK                                          0x00000002
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB                                                         2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB                                                         2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK                                               0x00000004
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x)                              (((x) & 0x00000004) >> 2)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x)                              (((x) << 2) & 0x00000004)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB                                                         3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB                                                         3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK                                               0x00000008
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x)                              (((x) & 0x00000008) >> 3)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x)                              (((x) << 3) & 0x00000008)
+
+/* macros for BB_tstdac_constant */
+#define PHY_BB_TSTDAC_CONSTANT_ADDRESS                                                        0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_OFFSET                                                         0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB                                               10
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB                                                0
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK                                      0x000007ff
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x)                     (((x) & 0x000007ff) >> 0)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x)                     (((x) << 0) & 0x000007ff)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB                                               21
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB                                               11
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK                                      0x003ff800
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x)                    (((x) & 0x003ff800) >> 11)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x)                    (((x) << 11) & 0x003ff800)
+
+/* macros for BB_find_signal_low */
+#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS                                                        0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_OFFSET                                                         0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB                                                         5
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB                                                         0
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK                                               0x0000003f
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB                                                        11
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB                                                         6
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK                                               0x00000fc0
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB                                                         19
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB                                                         12
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK                                                0x000ff000
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x)                              (((x) & 0x000ff000) >> 12)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x)                              (((x) << 12) & 0x000ff000)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB                                                       23
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB                                                       20
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK                                              0x00f00000
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x)                            (((x) & 0x00f00000) >> 20)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x)                            (((x) << 20) & 0x00f00000)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB                                                     30
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB                                                     24
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK                                            0x7f000000
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x)                          (((x) & 0x7f000000) >> 24)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x)                          (((x) << 24) & 0x7f000000)
+
+/* macros for BB_settling_time */
+#define PHY_BB_SETTLING_TIME_ADDRESS                                                          0x00009844
+#define PHY_BB_SETTLING_TIME_OFFSET                                                           0x00009844
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB                                                          6
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB                                                          0
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK                                                0x0000007f
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x)                               (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x)                               (((x) << 0) & 0x0000007f)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB                                                      13
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB                                                       7
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK                                             0x00003f80
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x)                            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x)                            (((x) << 7) & 0x00003f80)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB                                                          19
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB                                                          14
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK                                                 0x000fc000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x)                               (((x) & 0x000fc000) >> 14)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x)                               (((x) << 14) & 0x000fc000)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB                                                          25
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB                                                          20
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK                                                 0x03f00000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x)                               (((x) & 0x03f00000) >> 20)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x)                               (((x) << 20) & 0x03f00000)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB                                                      29
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB                                                      26
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK                                             0x3c000000
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x)                           (((x) & 0x3c000000) >> 26)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x)                           (((x) << 26) & 0x3c000000)
+
+/* macros for BB_gain_force_max_gains_b0 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS                                                0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET                                                 0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB                                      13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB                                       7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK                             0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x)            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x)            (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB                                      20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB                                      14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK                             0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x)           (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x)           (((x) << 14) & 0x001fc000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB                                                 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB                                                 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK                                        0x00200000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x)                      (((x) & 0x00200000) >> 21)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x)                      (((x) << 21) & 0x00200000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB                                           31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB                                           31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK                                  0x80000000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x)                (((x) & 0x80000000) >> 31)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x)                (((x) << 31) & 0x80000000)
+
+/* macros for BB_gains_min_offsets_b0 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS                                                   0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET                                                    0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB                                                       6
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB                                                       0
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK                                             0x0000007f
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x)                            (((x) & 0x0000007f) >> 0)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x)                            (((x) << 0) & 0x0000007f)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB                                                      11
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB                                                       7
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK                                             0x00000f80
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x)                            (((x) & 0x00000f80) >> 7)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x)                            (((x) << 7) & 0x00000f80)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB                                                      16
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB                                                      12
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK                                             0x0001f000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x)                           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x)                           (((x) << 12) & 0x0001f000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB                                                   24
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB                                                   17
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK                                          0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x)                        (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x)                        (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK                                       0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x)                     (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x)                     (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK                                       0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x)                     (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x)                     (((x) << 26) & 0x04000000)
+
+/* macros for BB_desired_sigsize */
+#define PHY_BB_DESIRED_SIGSIZE_ADDRESS                                                        0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_OFFSET                                                         0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB                                                    7
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB                                                    0
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK                                          0x000000ff
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x)                         (((x) & 0x000000ff) >> 0)
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x)                         (((x) << 0) & 0x000000ff)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB                                                      27
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB                                                      20
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK                                             0x0ff00000
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x)                           (((x) & 0x0ff00000) >> 20)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x)                           (((x) << 20) & 0x0ff00000)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB                                                  29
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB                                                  28
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK                                         0x30000000
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x)                       (((x) & 0x30000000) >> 28)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x)                       (((x) << 28) & 0x30000000)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB                                               30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB                                               30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK                                      0x40000000
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x)                    (((x) << 30) & 0x40000000)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB                                                      31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB                                                      31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK                                             0x80000000
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_3a */
+#define PHY_BB_TIMING_CONTROL_3A_ADDRESS                                                      0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_OFFSET                                                       0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB                                                   6
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB                                                   0
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK                                         0x0000007f
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x)                        (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x)                        (((x) << 0) & 0x0000007f)
+
+/* macros for BB_find_signal */
+#define PHY_BB_FIND_SIGNAL_ADDRESS                                                            0x00009858
+#define PHY_BB_FIND_SIGNAL_OFFSET                                                             0x00009858
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB                                                                 5
+#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB                                                                 0
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK                                                       0x0000003f
+#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x)                                      (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x)                                      (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_RELPWR_MSB                                                                 11
+#define PHY_BB_FIND_SIGNAL_RELPWR_LSB                                                                  6
+#define PHY_BB_FIND_SIGNAL_RELPWR_MASK                                                        0x00000fc0
+#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x)                                       (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x)                                       (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB                                                                17
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB                                                                12
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK                                                       0x0003f000
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x)                                     (((x) & 0x0003f000) >> 12)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x)                                     (((x) << 12) & 0x0003f000)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB                                                                 25
+#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB                                                                 18
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK                                                        0x03fc0000
+#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x)                                      (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x)                                      (((x) << 18) & 0x03fc0000)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB                                                            31
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB                                                            26
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK                                                   0xfc000000
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x)                                 (((x) & 0xfc000000) >> 26)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x)                                 (((x) << 26) & 0xfc000000)
+
+/* macros for BB_agc */
+#define PHY_BB_AGC_ADDRESS                                                                    0x0000985c
+#define PHY_BB_AGC_OFFSET                                                                     0x0000985c
+#define PHY_BB_AGC_COARSEPWR_CONST_MSB                                                                 6
+#define PHY_BB_AGC_COARSEPWR_CONST_LSB                                                                 0
+#define PHY_BB_AGC_COARSEPWR_CONST_MASK                                                       0x0000007f
+#define PHY_BB_AGC_COARSEPWR_CONST_GET(x)                                      (((x) & 0x0000007f) >> 0)
+#define PHY_BB_AGC_COARSEPWR_CONST_SET(x)                                      (((x) << 0) & 0x0000007f)
+#define PHY_BB_AGC_COARSE_LOW_MSB                                                                     14
+#define PHY_BB_AGC_COARSE_LOW_LSB                                                                      7
+#define PHY_BB_AGC_COARSE_LOW_MASK                                                            0x00007f80
+#define PHY_BB_AGC_COARSE_LOW_GET(x)                                           (((x) & 0x00007f80) >> 7)
+#define PHY_BB_AGC_COARSE_LOW_SET(x)                                           (((x) << 7) & 0x00007f80)
+#define PHY_BB_AGC_COARSE_HIGH_MSB                                                                    21
+#define PHY_BB_AGC_COARSE_HIGH_LSB                                                                    15
+#define PHY_BB_AGC_COARSE_HIGH_MASK                                                           0x003f8000
+#define PHY_BB_AGC_COARSE_HIGH_GET(x)                                         (((x) & 0x003f8000) >> 15)
+#define PHY_BB_AGC_COARSE_HIGH_SET(x)                                         (((x) << 15) & 0x003f8000)
+#define PHY_BB_AGC_QUICK_DROP_MSB                                                                     29
+#define PHY_BB_AGC_QUICK_DROP_LSB                                                                     22
+#define PHY_BB_AGC_QUICK_DROP_MASK                                                            0x3fc00000
+#define PHY_BB_AGC_QUICK_DROP_GET(x)                                          (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_AGC_QUICK_DROP_SET(x)                                          (((x) << 22) & 0x3fc00000)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB                                                                31
+#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB                                                                30
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK                                                       0xc0000000
+#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x)                                     (((x) & 0xc0000000) >> 30)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x)                                     (((x) << 30) & 0xc0000000)
+
+/* macros for BB_agc_control */
+#define PHY_BB_AGC_CONTROL_ADDRESS                                                            0x00009860
+#define PHY_BB_AGC_CONTROL_OFFSET                                                             0x00009860
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB                                                            0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB                                                            0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK                                                  0x00000001
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB                                                           1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB                                                           1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK                                                 0x00000002
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x)                                (((x) & 0x00000002) >> 1)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x)                                (((x) << 1) & 0x00000002)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB                                                     5
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB                                                     3
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK                                           0x00000038
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x)                          (((x) & 0x00000038) >> 3)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x)                          (((x) << 3) & 0x00000038)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB                                                                9
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB                                                                6
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK                                                      0x000003c0
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x)                                     (((x) & 0x000003c0) >> 6)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x)                                     (((x) << 6) & 0x000003c0)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB                                                    10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB                                                    10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK                                           0x00000400
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x)                         (((x) & 0x00000400) >> 10)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x)                         (((x) << 10) & 0x00000400)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB                                                             11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB                                                             11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK                                                    0x00000800
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x)                                  (((x) & 0x00000800) >> 11)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x)                                  (((x) << 11) & 0x00000800)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB                                                         12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB                                                         12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK                                                0x00001000
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x)                              (((x) & 0x00001000) >> 12)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x)                              (((x) << 12) & 0x00001000)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB                                                  13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB                                                  13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK                                         0x00002000
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x)                       (((x) & 0x00002000) >> 13)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x)                       (((x) << 13) & 0x00002000)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB                                                      15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB                                                      15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK                                             0x00008000
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x)                           (((x) & 0x00008000) >> 15)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x)                           (((x) << 15) & 0x00008000)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB                                                        16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB                                                        16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK                                               0x00010000
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x)                             (((x) & 0x00010000) >> 16)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x)                             (((x) << 16) & 0x00010000)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB                                                   17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB                                                   17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK                                          0x00020000
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x)                        (((x) & 0x00020000) >> 17)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x)                        (((x) << 17) & 0x00020000)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB                                                     18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB                                                     18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK                                            0x00040000
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x)                          (((x) & 0x00040000) >> 18)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x)                          (((x) << 18) & 0x00040000)
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB                                                            19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB                                                            19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK                                                   0x00080000
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x)                                 (((x) & 0x00080000) >> 19)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB                                                       20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB                                                       20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK                                              0x00100000
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x)                            (((x) & 0x00100000) >> 20)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x)                            (((x) << 20) & 0x00100000)
+
+/* macros for BB_cca_b0 */
+#define PHY_BB_CCA_B0_ADDRESS                                                                 0x00009864
+#define PHY_BB_CCA_B0_OFFSET                                                                  0x00009864
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB                                                               8
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB                                                               0
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK                                                     0x000001ff
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x)                                    (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x)                                    (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB                                                           11
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB                                                            9
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK                                                  0x00000e00
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x)                                 (((x) & 0x00000e00) >> 9)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x)                                 (((x) << 9) & 0x00000e00)
+#define PHY_BB_CCA_B0_CF_THRESH62_MSB                                                                 19
+#define PHY_BB_CCA_B0_CF_THRESH62_LSB                                                                 12
+#define PHY_BB_CCA_B0_CF_THRESH62_MASK                                                        0x000ff000
+#define PHY_BB_CCA_B0_CF_THRESH62_GET(x)                                      (((x) & 0x000ff000) >> 12)
+#define PHY_BB_CCA_B0_CF_THRESH62_SET(x)                                      (((x) << 12) & 0x000ff000)
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB                                                                 28
+#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB                                                                 20
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK                                                        0x1ff00000
+#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x)                                      (((x) & 0x1ff00000) >> 20)
+
+/* macros for BB_sfcorr */
+#define PHY_BB_SFCORR_ADDRESS                                                                 0x00009868
+#define PHY_BB_SFCORR_OFFSET                                                                  0x00009868
+#define PHY_BB_SFCORR_M2COUNT_THR_MSB                                                                  4
+#define PHY_BB_SFCORR_M2COUNT_THR_LSB                                                                  0
+#define PHY_BB_SFCORR_M2COUNT_THR_MASK                                                        0x0000001f
+#define PHY_BB_SFCORR_M2COUNT_THR_GET(x)                                       (((x) & 0x0000001f) >> 0)
+#define PHY_BB_SFCORR_M2COUNT_THR_SET(x)                                       (((x) << 0) & 0x0000001f)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB                                                               10
+#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB                                                                5
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK                                                      0x000007e0
+#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x)                                     (((x) & 0x000007e0) >> 5)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x)                                     (((x) << 5) & 0x000007e0)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB                                                               16
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB                                                               11
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK                                                      0x0001f800
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x)                                    (((x) & 0x0001f800) >> 11)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x)                                    (((x) << 11) & 0x0001f800)
+#define PHY_BB_SFCORR_M1_THRES_MSB                                                                    23
+#define PHY_BB_SFCORR_M1_THRES_LSB                                                                    17
+#define PHY_BB_SFCORR_M1_THRES_MASK                                                           0x00fe0000
+#define PHY_BB_SFCORR_M1_THRES_GET(x)                                         (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_SFCORR_M1_THRES_SET(x)                                         (((x) << 17) & 0x00fe0000)
+#define PHY_BB_SFCORR_M2_THRES_MSB                                                                    30
+#define PHY_BB_SFCORR_M2_THRES_LSB                                                                    24
+#define PHY_BB_SFCORR_M2_THRES_MASK                                                           0x7f000000
+#define PHY_BB_SFCORR_M2_THRES_GET(x)                                         (((x) & 0x7f000000) >> 24)
+#define PHY_BB_SFCORR_M2_THRES_SET(x)                                         (((x) << 24) & 0x7f000000)
+
+/* macros for BB_self_corr_low */
+#define PHY_BB_SELF_CORR_LOW_ADDRESS                                                          0x0000986c
+#define PHY_BB_SELF_CORR_LOW_OFFSET                                                           0x0000986c
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB                                                     0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB                                                     0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK                                           0x00000001
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB                                                       7
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB                                                       1
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK                                             0x000000fe
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x)                            (((x) & 0x000000fe) >> 1)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x)                            (((x) << 1) & 0x000000fe)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB                                                      13
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB                                                       8
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK                                             0x00003f00
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x)                            (((x) & 0x00003f00) >> 8)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x)                            (((x) << 8) & 0x00003f00)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB                                                        20
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB                                                        14
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK                                               0x001fc000
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x)                             (((x) & 0x001fc000) >> 14)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x)                             (((x) << 14) & 0x001fc000)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB                                                        27
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB                                                        21
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK                                               0x0fe00000
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x)                             (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x)                             (((x) << 21) & 0x0fe00000)
+
+/* macros for BB_synth_control */
+#define PHY_BB_SYNTH_CONTROL_ADDRESS                                                          0x00009874
+#define PHY_BB_SYNTH_CONTROL_OFFSET                                                           0x00009874
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB                                                           16
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB                                                            0
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK                                                  0x0001ffff
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x)                                 (((x) & 0x0001ffff) >> 0)
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x)                                 (((x) << 0) & 0x0001ffff)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB                                                            25
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB                                                            17
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK                                                   0x03fe0000
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x)                                 (((x) & 0x03fe0000) >> 17)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x)                                 (((x) << 17) & 0x03fe0000)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB                                                        27
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB                                                        26
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK                                               0x0c000000
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x)                             (((x) & 0x0c000000) >> 26)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x)                             (((x) << 26) & 0x0c000000)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB                                                           28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB                                                           28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK                                                  0x10000000
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x)                                (((x) & 0x10000000) >> 28)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x)                                (((x) << 28) & 0x10000000)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB                                                              29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB                                                              29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK                                                     0x20000000
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x)                                   (((x) & 0x20000000) >> 29)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x)                                   (((x) << 29) & 0x20000000)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB                                                  30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB                                                  30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK                                         0x40000000
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x)                       (((x) & 0x40000000) >> 30)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x)                       (((x) << 30) & 0x40000000)
+
+/* macros for BB_addac_clk_select */
+#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS                                                       0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_OFFSET                                                        0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB                                                  3
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB                                                  2
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK                                        0x0000000c
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x)                       (((x) & 0x0000000c) >> 2)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x)                       (((x) << 2) & 0x0000000c)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB                                                  5
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB                                                  4
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK                                        0x00000030
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x)                       (((x) & 0x00000030) >> 4)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x)                       (((x) << 4) & 0x00000030)
+
+/* macros for BB_pll_cntl */
+#define PHY_BB_PLL_CNTL_ADDRESS                                                               0x0000987c
+#define PHY_BB_PLL_CNTL_OFFSET                                                                0x0000987c
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB                                                                 9
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB                                                                 0
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK                                                       0x000003ff
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB                                                             13
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB                                                             10
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK                                                    0x00003c00
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x)                                  (((x) & 0x00003c00) >> 10)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x)                                  (((x) << 10) & 0x00003c00)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB                                                            15
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB                                                            14
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK                                                   0x0000c000
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x)                                 (((x) & 0x0000c000) >> 14)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x)                                 (((x) << 14) & 0x0000c000)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB                                                              16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB                                                              16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK                                                     0x00010000
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x)                                   (((x) << 16) & 0x00010000)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB                                                        27
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB                                                        17
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK                                               0x0ffe0000
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x)                             (((x) & 0x0ffe0000) >> 17)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x)                             (((x) << 17) & 0x0ffe0000)
+
+/* macros for BB_vit_spur_mask_A */
+#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS                                                        0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_OFFSET                                                         0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB                                                      9
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB                                                      0
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK                                            0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB                                                 16
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB                                                 10
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK                                        0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x)                      (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x)                      (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_vit_spur_mask_B */
+#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS                                                        0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_OFFSET                                                         0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB                                                      9
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB                                                      0
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK                                            0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB                                                 16
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB                                                 10
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK                                        0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x)                      (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x)                      (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_pilot_spur_mask */
+#define PHY_BB_PILOT_SPUR_MASK_ADDRESS                                                        0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_OFFSET                                                         0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB                                                     4
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB                                                     0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK                                           0x0000001f
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x)                          (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x)                          (((x) << 0) & 0x0000001f)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB                                                11
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB                                                 5
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK                                       0x00000fe0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x)                      (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x)                      (((x) << 5) & 0x00000fe0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB                                                    16
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB                                                    12
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK                                           0x0001f000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x)                         (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x)                         (((x) << 12) & 0x0001f000)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB                                                23
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB                                                17
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK                                       0x00fe0000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x)                     (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x)                     (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_chan_spur_mask */
+#define PHY_BB_CHAN_SPUR_MASK_ADDRESS                                                         0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_OFFSET                                                          0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB                                                       4
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB                                                       0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK                                             0x0000001f
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x)                            (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x)                            (((x) << 0) & 0x0000001f)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB                                                  11
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB                                                   5
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK                                         0x00000fe0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x)                        (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x)                        (((x) << 5) & 0x00000fe0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB                                                      16
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB                                                      12
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK                                             0x0001f000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x)                           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x)                           (((x) << 12) & 0x0001f000)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB                                                  23
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB                                                  17
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK                                         0x00fe0000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x)                       (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x)                       (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_spectral_scan */
+#define PHY_BB_SPECTRAL_SCAN_ADDRESS                                                          0x00009910
+#define PHY_BB_SPECTRAL_SCAN_OFFSET                                                           0x00009910
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB                                                     0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB                                                     0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK                                           0x00000001
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB                                                  1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB                                                  1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK                                        0x00000002
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x)                       (((x) & 0x00000002) >> 1)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x)                       (((x) << 1) & 0x00000002)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB                                                2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB                                                2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK                                      0x00000004
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x)                     (((x) & 0x00000004) >> 2)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x)                     (((x) << 2) & 0x00000004)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB                                              3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB                                              3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK                                    0x00000008
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x)                   (((x) & 0x00000008) >> 3)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x)                   (((x) << 3) & 0x00000008)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB                                              7
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB                                              4
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK                                    0x000000f0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x)                   (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x)                   (((x) << 4) & 0x000000f0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB                                                 15
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB                                                  8
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK                                        0x0000ff00
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x)                       (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x)                       (((x) << 8) & 0x0000ff00)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB                                                  27
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB                                                  16
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK                                         0x0fff0000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x)                       (((x) & 0x0fff0000) >> 16)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x)                       (((x) << 16) & 0x0fff0000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB                                              28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB                                              28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK                                     0x10000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x)                   (((x) & 0x10000000) >> 28)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x)                   (((x) << 28) & 0x10000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB                                               29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB                                               29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK                                      0x20000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x)                    (((x) & 0x20000000) >> 29)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x)                    (((x) << 29) & 0x20000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB                                               30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB                                               30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK                                      0x40000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x)                    (((x) << 30) & 0x40000000)
+
+/* macros for BB_analog_power_on_time */
+#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS                                                   0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET                                                    0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB                                             13
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB                                              0
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK                                    0x00003fff
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x)                   (((x) & 0x00003fff) >> 0)
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x)                   (((x) << 0) & 0x00003fff)
+
+/* macros for BB_search_start_delay */
+#define PHY_BB_SEARCH_START_DELAY_ADDRESS                                                     0x00009918
+#define PHY_BB_SEARCH_START_DELAY_OFFSET                                                      0x00009918
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB                                              11
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB                                               0
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK                                     0x00000fff
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x)                    (((x) & 0x00000fff) >> 0)
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x)                    (((x) << 0) & 0x00000fff)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB                                                  12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB                                                  12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK                                         0x00001000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x)                       (((x) & 0x00001000) >> 12)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x)                       (((x) << 12) & 0x00001000)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB                                                13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB                                                13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK                                       0x00002000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x)                     (((x) & 0x00002000) >> 13)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x)                     (((x) << 13) & 0x00002000)
+
+/* macros for BB_max_rx_length */
+#define PHY_BB_MAX_RX_LENGTH_ADDRESS                                                          0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_OFFSET                                                           0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB                                                        11
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB                                                         0
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK                                               0x00000fff
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x)                              (((x) & 0x00000fff) >> 0)
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x)                              (((x) << 0) & 0x00000fff)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB                                                        29
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB                                                        12
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK                                               0x3ffff000
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x)                             (((x) & 0x3ffff000) >> 12)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x)                             (((x) << 12) & 0x3ffff000)
+
+/* macros for BB_timing_control_4 */
+#define PHY_BB_TIMING_CONTROL_4_ADDRESS                                                       0x00009920
+#define PHY_BB_TIMING_CONTROL_4_OFFSET                                                        0x00009920
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB                                                  15
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB                                                  12
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK                                         0x0000f000
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x)                       (((x) & 0x0000f000) >> 12)
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x)                       (((x) << 12) & 0x0000f000)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB                                                 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB                                                 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK                                        0x00010000
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x)                      (((x) & 0x00010000) >> 16)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x)                      (((x) << 16) & 0x00010000)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB                                                20
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB                                                17
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK                                       0x001e0000
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x)                     (((x) & 0x001e0000) >> 17)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x)                     (((x) << 17) & 0x001e0000)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB                                                 27
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB                                                 21
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK                                        0x0fe00000
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x)                      (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x)                      (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB                                                 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB                                                 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK                                        0x10000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x)                      (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x)                      (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB                                                  29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB                                                  29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK                                         0x20000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x)                       (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x)                       (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB                                                30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB                                                30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK                                       0x40000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x)                     (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x)                     (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB                                                  31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB                                                  31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK                                         0x80000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x)                       (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x)                       (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_5 */
+#define PHY_BB_TIMING_CONTROL_5_ADDRESS                                                       0x00009924
+#define PHY_BB_TIMING_CONTROL_5_OFFSET                                                        0x00009924
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB                                                 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB                                                 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK                                       0x00000001
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x)                      (((x) & 0x00000001) >> 0)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x)                      (((x) << 0) & 0x00000001)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB                                                        7
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB                                                        1
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK                                              0x000000fe
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x)                             (((x) & 0x000000fe) >> 1)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x)                             (((x) << 1) & 0x000000fe)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB                                                 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB                                                 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK                                        0x00008000
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x)                      (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x)                      (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB                                                        22
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB                                                        16
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK                                               0x007f0000
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x)                             (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x)                             (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB                                            29
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB                                            23
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK                                   0x3f800000
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x)                 (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x)                 (((x) << 23) & 0x3f800000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB                                                30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB                                                30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK                                       0x40000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x)                     (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x)                     (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB                                             31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB                                             31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK                                    0x80000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_phyonly_warm_reset */
+#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS                                                     0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_OFFSET                                                      0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB                                               0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB                                               0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK                                     0x00000001
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x)                    (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x)                    (((x) << 0) & 0x00000001)
+
+/* macros for BB_phyonly_control */
+#define PHY_BB_PHYONLY_CONTROL_ADDRESS                                                        0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_OFFSET                                                         0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB                                                       0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB                                                       0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK                                             0x00000001
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB                                               1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB                                               1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK                                     0x00000002
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x)                    (((x) & 0x00000002) >> 1)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x)                    (((x) << 1) & 0x00000002)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB                                                  2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB                                                  2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK                                        0x00000004
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x)                       (((x) & 0x00000004) >> 2)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x)                       (((x) << 2) & 0x00000004)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB                                                   3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB                                                   3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK                                         0x00000008
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x)                        (((x) & 0x00000008) >> 3)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x)                        (((x) << 3) & 0x00000008)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB                                                   4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB                                                   4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK                                         0x00000010
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x)                        (((x) & 0x00000010) >> 4)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x)                        (((x) << 4) & 0x00000010)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB                                                   5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB                                                   5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK                                         0x00000020
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x)                        (((x) & 0x00000020) >> 5)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x)                        (((x) << 5) & 0x00000020)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB                                                   6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB                                                   6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK                                         0x00000040
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x)                        (((x) & 0x00000040) >> 6)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x)                        (((x) << 6) & 0x00000040)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB                                                   7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB                                                   7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK                                         0x00000080
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x)                        (((x) & 0x00000080) >> 7)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x)                        (((x) << 7) & 0x00000080)
+
+/* macros for BB_powertx_rate1 */
+#define PHY_BB_POWERTX_RATE1_ADDRESS                                                          0x00009934
+#define PHY_BB_POWERTX_RATE1_OFFSET                                                           0x00009934
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB                                                             5
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB                                                             0
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK                                                   0x0000003f
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB                                                            13
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB                                                             8
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK                                                   0x00003f00
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x)                                  (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x)                                  (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB                                                            21
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB                                                            16
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK                                                   0x003f0000
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x)                                 (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x)                                 (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB                                                            29
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB                                                            24
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK                                                   0x3f000000
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x)                                 (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x)                                 (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate2 */
+#define PHY_BB_POWERTX_RATE2_ADDRESS                                                          0x00009938
+#define PHY_BB_POWERTX_RATE2_OFFSET                                                           0x00009938
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB                                                             5
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB                                                             0
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK                                                   0x0000003f
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB                                                            13
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB                                                             8
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK                                                   0x00003f00
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x)                                  (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x)                                  (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB                                                            21
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB                                                            16
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK                                                   0x003f0000
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x)                                 (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x)                                 (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB                                                            29
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB                                                            24
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK                                                   0x3f000000
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x)                                 (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x)                                 (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_max */
+#define PHY_BB_POWERTX_MAX_ADDRESS                                                            0x0000993c
+#define PHY_BB_POWERTX_MAX_OFFSET                                                             0x0000993c
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB                                              6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB                                              6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK                                    0x00000040
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x)                   (((x) & 0x00000040) >> 6)
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x)                   (((x) << 6) & 0x00000040)
+
+/* macros for BB_extension_radar */
+#define PHY_BB_EXTENSION_RADAR_ADDRESS                                                        0x00009940
+#define PHY_BB_EXTENSION_RADAR_OFFSET                                                         0x00009940
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB                                                13
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB                                                 8
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK                                       0x00003f00
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x)                      (((x) & 0x00003f00) >> 8)
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x)                      (((x) << 8) & 0x00003f00)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB                                                   14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB                                                   14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK                                          0x00004000
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x)                        (((x) & 0x00004000) >> 14)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x)                        (((x) << 14) & 0x00004000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB                                                22
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB                                                15
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK                                       0x007f8000
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x)                     (((x) & 0x007f8000) >> 15)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x)                     (((x) << 15) & 0x007f8000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB                                                    30
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB                                                    23
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK                                           0x7f800000
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x)                         (((x) & 0x7f800000) >> 23)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x)                         (((x) << 23) & 0x7f800000)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB                                                31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB                                                31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK                                       0x80000000
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x)                     (((x) & 0x80000000) >> 31)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x)                     (((x) << 31) & 0x80000000)
+
+/* macros for BB_frame_control */
+#define PHY_BB_FRAME_CONTROL_ADDRESS                                                          0x00009944
+#define PHY_BB_FRAME_CONTROL_OFFSET                                                           0x00009944
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB                                                     1
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB                                                     0
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK                                           0x00000003
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x)                          (((x) & 0x00000003) >> 0)
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x)                          (((x) << 0) & 0x00000003)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB                                                        2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB                                                        2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK                                              0x00000004
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x)                             (((x) & 0x00000004) >> 2)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x)                             (((x) << 2) & 0x00000004)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB                                                            5
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB                                                            3
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK                                                  0x00000038
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x)                                 (((x) & 0x00000038) >> 3)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x)                                 (((x) << 3) & 0x00000038)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB                                                  7
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB                                                  6
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK                                        0x000000c0
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x)                       (((x) & 0x000000c0) >> 6)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x)                       (((x) << 6) & 0x000000c0)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB                                                        15
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB                                                         8
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK                                               0x0000ff00
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x)                              (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x)                              (((x) << 8) & 0x0000ff00)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB                                                    16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB                                                    16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK                                           0x00010000
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x)                         (((x) & 0x00010000) >> 16)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x)                         (((x) << 16) & 0x00010000)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB                                                  17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB                                                  17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK                                         0x00020000
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x)                       (((x) & 0x00020000) >> 17)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x)                       (((x) << 17) & 0x00020000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB                                                   18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB                                                   18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK                                          0x00040000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x)                        (((x) & 0x00040000) >> 18)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x)                        (((x) << 18) & 0x00040000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB                                                19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB                                                19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK                                       0x00080000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x)                     (((x) & 0x00080000) >> 19)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x)                     (((x) << 19) & 0x00080000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB                                                    20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB                                                    20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK                                           0x00100000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x)                         (((x) & 0x00100000) >> 20)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x)                         (((x) << 20) & 0x00100000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB                                                   21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB                                                   21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK                                          0x00200000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x)                        (((x) & 0x00200000) >> 21)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x)                        (((x) << 21) & 0x00200000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB                                                     22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB                                                     22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK                                            0x00400000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x)                          (((x) & 0x00400000) >> 22)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x)                          (((x) << 22) & 0x00400000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB                                                23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB                                                23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK                                       0x00800000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x)                     (((x) & 0x00800000) >> 23)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x)                     (((x) << 23) & 0x00800000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB                                                   24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB                                                   24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK                                          0x01000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x)                        (((x) & 0x01000000) >> 24)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x)                        (((x) << 24) & 0x01000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB                                                 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB                                                 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK                                        0x02000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x)                      (((x) & 0x02000000) >> 25)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x)                      (((x) << 25) & 0x02000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB                                                  26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB                                                  26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK                                         0x04000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x)                       (((x) & 0x04000000) >> 26)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x)                       (((x) << 26) & 0x04000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB                                                27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB                                                27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK                                       0x08000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x)                     (((x) & 0x08000000) >> 27)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x)                     (((x) << 27) & 0x08000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB                                                    28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB                                                    28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK                                           0x10000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x)                         (((x) & 0x10000000) >> 28)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x)                         (((x) << 28) & 0x10000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB                                                       29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB                                                       29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK                                              0x20000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x)                            (((x) & 0x20000000) >> 29)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x)                            (((x) << 29) & 0x20000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB                                                   30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB                                                   30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK                                          0x40000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x)                        (((x) & 0x40000000) >> 30)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x)                        (((x) << 30) & 0x40000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB                                                      31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB                                                      31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK                                             0x80000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_6 */
+#define PHY_BB_TIMING_CONTROL_6_ADDRESS                                                       0x00009948
+#define PHY_BB_TIMING_CONTROL_6_OFFSET                                                        0x00009948
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB                                                     7
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB                                                     0
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK                                           0x000000ff
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB                                         14
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB                                          8
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK                                0x00007f00
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x)               (((x) & 0x00007f00) >> 8)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x)               (((x) << 8) & 0x00007f00)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB                                                 20
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB                                                 15
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK                                        0x001f8000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x)                      (((x) & 0x001f8000) >> 15)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x)                      (((x) << 15) & 0x001f8000)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB                                         27
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB                                         21
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK                                0x0fe00000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x)              (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x)              (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB                                             31
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB                                             28
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK                                    0xf0000000
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x)                  (((x) & 0xf0000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x)                  (((x) << 28) & 0xf0000000)
+
+/* macros for BB_spur_mask_controls */
+#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS                                                     0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET                                                      0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB                                                 7
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB                                                 0
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK                                       0x000000ff
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x)                      (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x)                      (((x) << 0) & 0x000000ff)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB                                                 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB                                                 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK                                       0x00000100
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x)                      (((x) & 0x00000100) >> 8)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x)                      (((x) << 8) & 0x00000100)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB                                                 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB                                                 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK                                        0x00020000
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x)                      (((x) & 0x00020000) >> 17)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x)                      (((x) << 17) & 0x00020000)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB                                                  25
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB                                                  18
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK                                         0x03fc0000
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x)                       (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x)                       (((x) << 18) & 0x03fc0000)
+
+/* macros for BB_rx_iq_corr_b0 */
+#define PHY_BB_RX_IQ_CORR_B0_ADDRESS                                                          0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_OFFSET                                                           0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB                                                  6
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB                                                  0
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK                                        0x0000007f
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x)                       (((x) & 0x0000007f) >> 0)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x)                       (((x) << 0) & 0x0000007f)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB                                                 13
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB                                                  7
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK                                        0x00003f80
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x)                       (((x) & 0x00003f80) >> 7)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x)                       (((x) << 7) & 0x00003f80)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB                                                     14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB                                                     14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK                                            0x00004000
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x)                          (((x) & 0x00004000) >> 14)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x)                          (((x) << 14) & 0x00004000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB                                           21
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB                                           15
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK                                  0x003f8000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x)                (((x) & 0x003f8000) >> 15)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x)                (((x) << 15) & 0x003f8000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB                                           28
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB                                           22
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK                                  0x1fc00000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x)                (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x)                (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB                                               29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB                                               29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK                                      0x20000000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x)                    (((x) & 0x20000000) >> 29)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x)                    (((x) << 29) & 0x20000000)
+
+/* macros for BB_radar_detection */
+#define PHY_BB_RADAR_DETECTION_ADDRESS                                                        0x00009954
+#define PHY_BB_RADAR_DETECTION_OFFSET                                                         0x00009954
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB                                                 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB                                                 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK                                       0x00000001
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x)                      (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x)                      (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB                                                5
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB                                                1
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK                                      0x0000003e
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x)                     (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x)                     (((x) << 1) & 0x0000003e)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB                                                  11
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB                                                   6
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK                                         0x00000fc0
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x)                        (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x)                        (((x) << 6) & 0x00000fc0)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB                                                17
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB                                                12
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK                                       0x0003f000
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x)                     (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x)                     (((x) << 12) & 0x0003f000)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB                                                  23
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB                                                  18
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK                                         0x00fc0000
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x)                       (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x)                       (((x) << 18) & 0x00fc0000)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB                                                30
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB                                                24
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK                                       0x7f000000
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x)                     (((x) & 0x7f000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x)                     (((x) << 24) & 0x7f000000)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB                                                   31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB                                                   31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK                                          0x80000000
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x)                        (((x) & 0x80000000) >> 31)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x)                        (((x) << 31) & 0x80000000)
+
+/* macros for BB_radar_detection_2 */
+#define PHY_BB_RADAR_DETECTION_2_ADDRESS                                                      0x00009958
+#define PHY_BB_RADAR_DETECTION_2_OFFSET                                                       0x00009958
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB                                                  7
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB                                                  0
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK                                        0x000000ff
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB                                             12
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB                                              8
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK                                    0x00001f00
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x)                   (((x) & 0x00001f00) >> 8)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x)                   (((x) << 8) & 0x00001f00)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB                                       13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB                                       13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK                              0x00002000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x)            (((x) & 0x00002000) >> 13)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x)            (((x) << 13) & 0x00002000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB                                            14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB                                            14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK                                   0x00004000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x)                 (((x) & 0x00004000) >> 14)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x)                 (((x) << 14) & 0x00004000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB                                         15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB                                         15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK                                0x00008000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x)              (((x) & 0x00008000) >> 15)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x)              (((x) << 15) & 0x00008000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB                                              21
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB                                              16
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK                                     0x003f0000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x)                   (((x) & 0x003f0000) >> 16)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x)                   (((x) << 16) & 0x003f0000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB                                             22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB                                             22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK                                    0x00400000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x)                  (((x) & 0x00400000) >> 22)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x)                  (((x) << 22) & 0x00400000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB                                        23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB                                        23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK                               0x00800000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x)             (((x) & 0x00800000) >> 23)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x)             (((x) << 23) & 0x00800000)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB                                          26
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB                                          24
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK                                 0x07000000
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x)               (((x) & 0x07000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x)               (((x) << 24) & 0x07000000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB                                      27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB                                      27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK                             0x08000000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x)           (((x) & 0x08000000) >> 27)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x)           (((x) << 27) & 0x08000000)
+
+/* macros for BB_tx_phase_ramp_b0 */
+#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS                                                       0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET                                                        0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB                                             0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB                                             0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK                                   0x00000001
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x)                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x)                  (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB                                               6
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB                                               1
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK                                     0x0000007e
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x)                    (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x)                    (((x) << 1) & 0x0000007e)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB                                              16
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB                                               7
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK                                     0x0001ff80
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x)                    (((x) & 0x0001ff80) >> 7)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x)                    (((x) << 7) & 0x0001ff80)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB                                             24
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB                                             17
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK                                    0x01fe0000
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x)                  (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x)                  (((x) << 17) & 0x01fe0000)
+
+/* macros for BB_switch_table_chn_b0 */
+#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS                                                    0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET                                                     0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB                                             1
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB                                             0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK                                   0x00000003
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x)                  (((x) & 0x00000003) >> 0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x)                  (((x) << 0) & 0x00000003)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB                                                3
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB                                                2
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK                                      0x0000000c
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x)                     (((x) & 0x0000000c) >> 2)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x)                     (((x) << 2) & 0x0000000c)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB                                                5
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB                                                4
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK                                      0x00000030
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x)                     (((x) & 0x00000030) >> 4)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x)                     (((x) << 4) & 0x00000030)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB                                              7
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB                                              6
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK                                    0x000000c0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x)                   (((x) & 0x000000c0) >> 6)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x)                   (((x) << 6) & 0x000000c0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB                                             9
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB                                             8
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK                                   0x00000300
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x)                  (((x) & 0x00000300) >> 8)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x)                  (((x) << 8) & 0x00000300)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB                                               11
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB                                               10
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK                                      0x00000c00
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x)                    (((x) & 0x00000c00) >> 10)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x)                    (((x) << 10) & 0x00000c00)
+
+/* macros for BB_switch_table_com1 */
+#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS                                                      0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_OFFSET                                                       0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB                                             3
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB                                             0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK                                   0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x)                  (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x)                  (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB                                               7
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB                                               4
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK                                     0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x)                    (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x)                    (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB                                              11
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB                                               8
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK                                     0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x)                    (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x)                    (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB                                               15
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB                                               12
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK                                      0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x)                    (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x)                    (((x) << 12) & 0x0000f000)
+
+/* macros for BB_cca_ctrl_2_b0 */
+#define PHY_BB_CCA_CTRL_2_B0_ADDRESS                                                          0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_OFFSET                                                           0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB                                                       8
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB                                                       0
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK                                             0x000001ff
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x)                            (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x)                            (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB                                                  9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB                                                  9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK                                        0x00000200
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x)                       (((x) & 0x00000200) >> 9)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x)                       (((x) << 9) & 0x00000200)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB                                                       17
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB                                                       10
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK                                              0x0003fc00
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x)                            (((x) & 0x0003fc00) >> 10)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x)                            (((x) << 10) & 0x0003fc00)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB                                                        18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB                                                        18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK                                               0x00040000
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x)                             (((x) & 0x00040000) >> 18)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x)                             (((x) << 18) & 0x00040000)
+
+/* macros for BB_switch_table_com2 */
+#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS                                                      0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_OFFSET                                                       0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB                                         3
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB                                         0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK                               0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x)              (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x)              (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB                                         7
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB                                         4
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK                               0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x)              (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x)              (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB                                         11
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB                                          8
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK                                0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x)               (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x)               (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB                                         15
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB                                         12
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK                                0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x)              (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x)              (((x) << 12) & 0x0000f000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB                                        19
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB                                        16
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK                               0x000f0000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x)             (((x) & 0x000f0000) >> 16)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x)             (((x) << 16) & 0x000f0000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB                                        23
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB                                        20
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK                               0x00f00000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x)             (((x) & 0x00f00000) >> 20)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x)             (((x) << 20) & 0x00f00000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB                                         27
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB                                         24
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK                                0x0f000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x)              (((x) & 0x0f000000) >> 24)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x)              (((x) << 24) & 0x0f000000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB                                         31
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB                                         28
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK                                0xf0000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x)              (((x) & 0xf0000000) >> 28)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x)              (((x) << 28) & 0xf0000000)
+
+/* macros for BB_restart */
+#define PHY_BB_RESTART_ADDRESS                                                                0x00009970
+#define PHY_BB_RESTART_OFFSET                                                                 0x00009970
+#define PHY_BB_RESTART_ENABLE_RESTART_MSB                                                              0
+#define PHY_BB_RESTART_ENABLE_RESTART_LSB                                                              0
+#define PHY_BB_RESTART_ENABLE_RESTART_MASK                                                    0x00000001
+#define PHY_BB_RESTART_ENABLE_RESTART_GET(x)                                   (((x) & 0x00000001) >> 0)
+#define PHY_BB_RESTART_ENABLE_RESTART_SET(x)                                   (((x) << 0) & 0x00000001)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB                                                      5
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB                                                      1
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK                                            0x0000003e
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x)                           (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x)                           (((x) << 1) & 0x0000003e)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB                                                         6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB                                                         6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK                                               0x00000040
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x)                              (((x) & 0x00000040) >> 6)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x)                              (((x) << 6) & 0x00000040)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB                                                     11
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB                                                      7
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK                                            0x00000f80
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x)                           (((x) & 0x00000f80) >> 7)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x)                           (((x) << 7) & 0x00000f80)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB                                                         17
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB                                                         12
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK                                                0x0003f000
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x)                              (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x)                              (((x) << 12) & 0x0003f000)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB                                                      20
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB                                                      18
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK                                             0x001c0000
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x)                           (((x) & 0x001c0000) >> 18)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x)                           (((x) << 18) & 0x001c0000)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB                                                 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB                                                 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK                                        0x00200000
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x)                      (((x) & 0x00200000) >> 21)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x)                      (((x) << 21) & 0x00200000)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB                                                         28
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB                                                         22
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK                                                0x1fc00000
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x)                              (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x)                              (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB                                                    29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB                                                    29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK                                           0x20000000
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x)                         (((x) & 0x20000000) >> 29)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x)                         (((x) << 29) & 0x20000000)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB                                                         30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB                                                         30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK                                                0x40000000
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x)                              (((x) & 0x40000000) >> 30)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x)                              (((x) << 30) & 0x40000000)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB                                                          31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB                                                          31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK                                                 0x80000000
+#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_scrambler_seed */
+#define PHY_BB_SCRAMBLER_SEED_ADDRESS                                                         0x00009978
+#define PHY_BB_SCRAMBLER_SEED_OFFSET                                                          0x00009978
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB                                                 6
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB                                                 0
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK                                       0x0000007f
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x)                      (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x)                      (((x) << 0) & 0x0000007f)
+
+/* macros for BB_rfbus_request */
+#define PHY_BB_RFBUS_REQUEST_ADDRESS                                                          0x0000997c
+#define PHY_BB_RFBUS_REQUEST_OFFSET                                                           0x0000997c
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB                                                         0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB                                                         0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK                                               0x00000001
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x)                              (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x)                              (((x) << 0) & 0x00000001)
+
+/* macros for BB_timing_control_11 */
+#define PHY_BB_TIMING_CONTROL_11_ADDRESS                                                      0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_OFFSET                                                       0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB                                                 19
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB                                                  0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK                                        0x000fffff
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x)                       (((x) & 0x000fffff) >> 0)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x)                       (((x) << 0) & 0x000fffff)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB                                                     29
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB                                                     20
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK                                            0x3ff00000
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x)                          (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x)                          (((x) << 20) & 0x3ff00000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB                                           30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB                                           30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK                                  0x40000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x)                (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB                                       31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB                                       31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK                              0x80000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x)            (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x)            (((x) << 31) & 0x80000000)
+
+/* macros for BB_multichain_enable */
+#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS                                                      0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_OFFSET                                                       0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB                                                     2
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB                                                     0
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK                                           0x00000007
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x)                          (((x) & 0x00000007) >> 0)
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x)                          (((x) << 0) & 0x00000007)
+
+/* macros for BB_multichain_control */
+#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS                                                     0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_OFFSET                                                      0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB                                           0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB                                           0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK                                 0x00000001
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB                                              7
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB                                              1
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK                                    0x000000fe
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x)                   (((x) & 0x000000fe) >> 1)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x)                   (((x) << 1) & 0x000000fe)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB                                                     8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB                                                     8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK                                           0x00000100
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x)                          (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x)                          (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB                                               9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB                                               9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK                                     0x00000200
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x)                    (((x) & 0x00000200) >> 9)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x)                    (((x) << 9) & 0x00000200)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB                                                    20
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB                                                    10
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK                                           0x001ffc00
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x)                         (((x) & 0x001ffc00) >> 10)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x)                         (((x) << 10) & 0x001ffc00)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB                                             28
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB                                             22
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK                                    0x1fc00000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x)                  (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x)                  (((x) << 22) & 0x1fc00000)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB                                                29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB                                                29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK                                       0x20000000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x)                     (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x)                     (((x) << 29) & 0x20000000)
+
+/* macros for BB_multichain_gain_ctrl */
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS                                                   0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET                                                    0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB                                                  7
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB                                                  0
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK                                        0x000000ff
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB                                        8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB                                        8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK                              0x00000100
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x)             (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x)             (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB                                             14
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB                                              9
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK                                    0x00007e00
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x)                   (((x) & 0x00007e00) >> 9)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x)                   (((x) << 9) & 0x00007e00)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB                                            20
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB                                            15
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK                                   0x001f8000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x)                 (((x) & 0x001f8000) >> 15)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x)                 (((x) << 15) & 0x001f8000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB                                            21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB                                            21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK                                   0x00200000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x)                 (((x) & 0x00200000) >> 21)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x)                 (((x) << 21) & 0x00200000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB                                           22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB                                           22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK                                  0x00400000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x)                (((x) & 0x00400000) >> 22)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x)                (((x) << 22) & 0x00400000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB                                         23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB                                         23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK                                0x00800000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x)              (((x) & 0x00800000) >> 23)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x)              (((x) << 23) & 0x00800000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB                                         24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB                                         24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK                                0x01000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x)              (((x) & 0x01000000) >> 24)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x)              (((x) << 24) & 0x01000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB                                           26
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB                                           25
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK                                  0x06000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x)                (((x) & 0x06000000) >> 25)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x)                (((x) << 25) & 0x06000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB                                          28
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB                                          27
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK                                 0x18000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x)               (((x) & 0x18000000) >> 27)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x)               (((x) << 27) & 0x18000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB                                            29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB                                            29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK                                   0x20000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x)                 (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x)                 (((x) << 29) & 0x20000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB                                           30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB                                           30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK                                  0x40000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x)                (((x) << 30) & 0x40000000)
+
+/* macros for BB_adc_gain_dc_corr_b0 */
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS                                                    0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET                                                     0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB                                         5
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB                                         0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK                               0x0000003f
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x)              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x)              (((x) << 0) & 0x0000003f)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB                                        11
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB                                         6
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK                               0x00000fc0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x)              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x)              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB                                          20
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB                                          12
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK                                 0x001ff000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x)               (((x) & 0x001ff000) >> 12)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x)               (((x) << 12) & 0x001ff000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB                                          29
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB                                          21
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK                                 0x3fe00000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x)               (((x) & 0x3fe00000) >> 21)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x)               (((x) << 21) & 0x3fe00000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB                                           30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB                                           30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK                                  0x40000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x)                (((x) & 0x40000000) >> 30)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x)                (((x) << 30) & 0x40000000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB                                             31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB                                             31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK                                    0x80000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_chan_pwr_thr_1 */
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS                                                     0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET                                                      0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB                                                     7
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB                                                     0
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK                                           0x000000ff
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB                                      15
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB                                       8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK                             0x0000ff00
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x)            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x)            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB                                    20
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB                                    16
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK                           0x001f0000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x)         (((x) & 0x001f0000) >> 16)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x)         (((x) << 16) & 0x001f0000)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB                                         26
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB                                         21
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK                                0x07e00000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x)              (((x) & 0x07e00000) >> 21)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x)              (((x) << 21) & 0x07e00000)
+
+/* macros for BB_ext_chan_pwr_thr_2_b0 */
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS                                                  0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET                                                   0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB                                            8
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB                                            0
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK                                  0x000001ff
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x)                 (((x) << 0) & 0x000001ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB                                              15
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB                                               9
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK                                     0x0000fe00
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x)                    (((x) & 0x0000fe00) >> 9)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x)                    (((x) << 9) & 0x0000fe00)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB                                              24
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB                                              16
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK                                     0x01ff0000
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x)                   (((x) & 0x01ff0000) >> 16)
+
+/* macros for BB_ext_chan_scorr_thr */
+#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS                                                     0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET                                                      0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB                                                     6
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB                                                     0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK                                           0x0000007f
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x)                          (((x) & 0x0000007f) >> 0)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x)                          (((x) << 0) & 0x0000007f)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB                                                    13
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB                                                     7
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK                                           0x00003f80
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x)                          (((x) & 0x00003f80) >> 7)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x)                          (((x) << 7) & 0x00003f80)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB                                                20
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB                                                14
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK                                       0x001fc000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x)                     (((x) & 0x001fc000) >> 14)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x)                     (((x) << 14) & 0x001fc000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB                                                27
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB                                                21
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK                                       0x0fe00000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x)                     (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x)                     (((x) << 21) & 0x0fe00000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB                                              28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB                                              28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK                                     0x10000000
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x)                   (((x) & 0x10000000) >> 28)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x)                   (((x) << 28) & 0x10000000)
+
+/* macros for BB_ext_chan_detect_win */
+#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS                                                    0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET                                                     0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB                                               3
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB                                               0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK                                     0x0000000f
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x)                    (((x) & 0x0000000f) >> 0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x)                    (((x) << 0) & 0x0000000f)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB                                           7
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB                                           4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK                                 0x000000f0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x)                (((x) & 0x000000f0) >> 4)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x)                (((x) << 4) & 0x000000f0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB                                          12
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB                                           8
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK                                 0x00001f00
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x)                (((x) & 0x00001f00) >> 8)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x)                (((x) << 8) & 0x00001f00)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB                                                  15
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB                                                  13
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK                                         0x0000e000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x)                       (((x) & 0x0000e000) >> 13)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x)                       (((x) << 13) & 0x0000e000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB                                              18
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB                                              16
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK                                     0x00070000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x)                   (((x) & 0x00070000) >> 16)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x)                   (((x) << 16) & 0x00070000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB                                           24
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB                                           19
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK                                  0x01f80000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x)                (((x) & 0x01f80000) >> 19)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x)                (((x) << 19) & 0x01f80000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB                                            28
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB                                            25
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK                                   0x1e000000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x)                 (((x) & 0x1e000000) >> 25)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x)                 (((x) << 25) & 0x1e000000)
+
+/* macros for BB_pwr_thr_20_40_det */
+#define PHY_BB_PWR_THR_20_40_DET_ADDRESS                                                      0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_OFFSET                                                       0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB                                                  4
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB                                                  0
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK                                        0x0000001f
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x)                       (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x)                       (((x) << 0) & 0x0000001f)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB                                                    10
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB                                                     5
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK                                           0x000007e0
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x)                          (((x) & 0x000007e0) >> 5)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x)                          (((x) << 5) & 0x000007e0)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB                                                15
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB                                                11
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK                                       0x0000f800
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x)                     (((x) & 0x0000f800) >> 11)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x)                     (((x) << 11) & 0x0000f800)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB                                                    23
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB                                                    16
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK                                           0x00ff0000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB                                                   28
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB                                                   24
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK                                          0x1f000000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x)                        (((x) & 0x1f000000) >> 24)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x)                        (((x) << 24) & 0x1f000000)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB                                                    29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB                                                    29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK                                           0x20000000
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x)                         (((x) & 0x20000000) >> 29)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x)                         (((x) << 29) & 0x20000000)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB                                                     30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB                                                     30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK                                            0x40000000
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x)                          (((x) & 0x40000000) >> 30)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x)                          (((x) << 30) & 0x40000000)
+
+/* macros for BB_short_gi_delta_slope */
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS                                                   0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET                                                    0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB                                  3
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB                                  0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK                        0x0000000f
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x)       (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x)       (((x) << 0) & 0x0000000f)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB                                 18
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB                                  4
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK                        0x0007fff0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x)       (((x) & 0x0007fff0) >> 4)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x)       (((x) << 4) & 0x0007fff0)
+
+/* macros for BB_chaninfo_ctrl */
+#define PHY_BB_CHANINFO_CTRL_ADDRESS                                                          0x000099dc
+#define PHY_BB_CHANINFO_CTRL_OFFSET                                                           0x000099dc
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB                                                     0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB                                                     0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK                                           0x00000001
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB                                                   1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB                                                   1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK                                         0x00000002
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x)                        (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x)                        (((x) << 1) & 0x00000002)
+
+/* macros for BB_heavy_clip_ctrl */
+#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS                                                        0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET                                                         0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB                                                8
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB                                                0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK                                      0x000001ff
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x)                     (((x) & 0x000001ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x)                     (((x) << 0) & 0x000001ff)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB                                                 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB                                                 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK                                       0x00000200
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x)                      (((x) & 0x00000200) >> 9)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x)                      (((x) << 9) & 0x00000200)
+
+/* macros for BB_heavy_clip_20 */
+#define PHY_BB_HEAVY_CLIP_20_ADDRESS                                                          0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_OFFSET                                                           0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB                                                   7
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB                                                   0
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK                                         0x000000ff
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x)                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x)                        (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB                                                  15
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB                                                   8
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK                                         0x0000ff00
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB                                                  23
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB                                                  16
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK                                         0x00ff0000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB                                                  31
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB                                                  24
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK                                         0xff000000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x)                       (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x)                       (((x) << 24) & 0xff000000)
+
+/* macros for BB_heavy_clip_40 */
+#define PHY_BB_HEAVY_CLIP_40_ADDRESS                                                          0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_OFFSET                                                           0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB                                                   7
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB                                                   0
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK                                         0x000000ff
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x)                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x)                        (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB                                                  15
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB                                                   8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK                                         0x0000ff00
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB                                                  23
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB                                                  16
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK                                         0x00ff0000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x)                       (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x)                       (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB                                                  31
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB                                                  24
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK                                         0xff000000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x)                       (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x)                       (((x) << 24) & 0xff000000)
+
+/* macros for BB_rifs_srch */
+#define PHY_BB_RIFS_SRCH_ADDRESS                                                              0x000099ec
+#define PHY_BB_RIFS_SRCH_OFFSET                                                               0x000099ec
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB                                                      7
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB                                                      0
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK                                            0x000000ff
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x)                           (((x) << 0) & 0x000000ff)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB                                                      15
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB                                                       8
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK                                             0x0000ff00
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB                                                          25
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB                                                          16
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK                                                 0x03ff0000
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x)                               (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x)                               (((x) << 16) & 0x03ff0000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB                                                   26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB                                                   26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK                                          0x04000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x)                        (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x)                        (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB                                                     27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB                                                     27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK                                            0x08000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x)                          (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x)                          (((x) << 27) & 0x08000000)
+
+/* macros for BB_iq_adc_cal_mode */
+#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS                                                        0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET                                                         0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB                                                 1
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB                                                 0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK                                       0x00000003
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x)                      (((x) & 0x00000003) >> 0)
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x)                      (((x) << 0) & 0x00000003)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB                                                      2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB                                                      2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK                                            0x00000004
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x)                           (((x) & 0x00000004) >> 2)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x)                           (((x) << 2) & 0x00000004)
+
+/* macros for BB_per_chain_csd */
+#define PHY_BB_PER_CHAIN_CSD_ADDRESS                                                          0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_OFFSET                                                           0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB                                                      4
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB                                                      0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK                                            0x0000001f
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x)                           (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x)                           (((x) << 0) & 0x0000001f)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB                                                      9
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB                                                      5
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK                                            0x000003e0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x)                           (((x) & 0x000003e0) >> 5)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x)                           (((x) << 5) & 0x000003e0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB                                                     14
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB                                                     10
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK                                            0x00007c00
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x)                          (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x)                          (((x) << 10) & 0x00007c00)
+
+/* macros for BB_rx_ocgain */
+#define PHY_BB_RX_OCGAIN_ADDRESS                                                              0x00009a00
+#define PHY_BB_RX_OCGAIN_OFFSET                                                               0x00009a00
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB                                                               31
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB                                                                0
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK                                                      0xffffffff
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_crc */
+#define PHY_BB_TX_CRC_ADDRESS                                                                 0x00009c00
+#define PHY_BB_TX_CRC_OFFSET                                                                  0x00009c00
+#define PHY_BB_TX_CRC_TX_CRC_MSB                                                                      15
+#define PHY_BB_TX_CRC_TX_CRC_LSB                                                                       0
+#define PHY_BB_TX_CRC_TX_CRC_MASK                                                             0x0000ffff
+#define PHY_BB_TX_CRC_TX_CRC_GET(x)                                            (((x) & 0x0000ffff) >> 0)
+
+/* macros for BB_iq_adc_meas_0_b0 */
+#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS                                                       0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET                                                        0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_1_b0 */
+#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS                                                       0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET                                                        0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_2_b0 */
+#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS                                                       0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET                                                        0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_3_b0 */
+#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS                                                       0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET                                                        0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB                                           31
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB                                            0
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK                                  0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x)                 (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_rfbus_grant */
+#define PHY_BB_RFBUS_GRANT_ADDRESS                                                            0x00009c20
+#define PHY_BB_RFBUS_GRANT_OFFSET                                                             0x00009c20
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB                                                             0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB                                                             0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK                                                   0x00000001
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB                                                                  1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB                                                                  1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK                                                        0x00000002
+#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x)                                       (((x) & 0x00000002) >> 1)
+
+/* macros for BB_tstadc */
+#define PHY_BB_TSTADC_ADDRESS                                                                 0x00009c24
+#define PHY_BB_TSTADC_OFFSET                                                                  0x00009c24
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB                                                                 9
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB                                                                 0
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK                                                       0x000003ff
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB                                                                19
+#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB                                                                10
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK                                                       0x000ffc00
+#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_tstdac */
+#define PHY_BB_TSTDAC_ADDRESS                                                                 0x00009c28
+#define PHY_BB_TSTDAC_OFFSET                                                                  0x00009c28
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB                                                                 9
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB                                                                 0
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK                                                       0x000003ff
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB                                                                19
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB                                                                10
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK                                                       0x000ffc00
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_illegal_tx_rate */
+#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS                                                        0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_OFFSET                                                         0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB                                                     0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB                                                     0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK                                           0x00000001
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x)                          (((x) & 0x00000001) >> 0)
+
+/* macros for BB_spur_report_b0 */
+#define PHY_BB_SPUR_REPORT_B0_ADDRESS                                                         0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_OFFSET                                                          0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB                                                         7
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB                                                         0
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK                                               0x000000ff
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x)                              (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB                                                        15
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB                                                         8
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK                                               0x0000ff00
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x)                              (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB                                           31
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB                                           16
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK                                  0xffff0000
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x)                (((x) & 0xffff0000) >> 16)
+
+/* macros for BB_channel_status */
+#define PHY_BB_CHANNEL_STATUS_ADDRESS                                                         0x00009c38
+#define PHY_BB_CHANNEL_STATUS_OFFSET                                                          0x00009c38
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB                                                            0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB                                                            0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK                                                  0x00000001
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB                                                         1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB                                                         1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK                                               0x00000002
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x)                              (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB                                                         2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB                                                         2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK                                               0x00000004
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x)                              (((x) & 0x00000004) >> 2)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB                                                         3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB                                                         3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK                                               0x00000008
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x)                              (((x) & 0x00000008) >> 3)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB                                                          5
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB                                                          4
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK                                                0x00000030
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x)                               (((x) & 0x00000030) >> 4)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB                                                          7
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB                                                          6
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK                                                0x000000c0
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x)                               (((x) & 0x000000c0) >> 6)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB                                                          9
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB                                                          8
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK                                                0x00000300
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x)                               (((x) & 0x00000300) >> 8)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB                                                       13
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB                                                       10
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK                                              0x00003c00
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x)                            (((x) & 0x00003c00) >> 10)
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB                                                    16
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB                                                    14
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK                                           0x0001c000
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x)                         (((x) & 0x0001c000) >> 14)
+
+/* macros for BB_rssi_b0 */
+#define PHY_BB_RSSI_B0_ADDRESS                                                                0x00009c3c
+#define PHY_BB_RSSI_B0_OFFSET                                                                 0x00009c3c
+#define PHY_BB_RSSI_B0_RSSI_0_MSB                                                                      7
+#define PHY_BB_RSSI_B0_RSSI_0_LSB                                                                      0
+#define PHY_BB_RSSI_B0_RSSI_0_MASK                                                            0x000000ff
+#define PHY_BB_RSSI_B0_RSSI_0_GET(x)                                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB                                                                 15
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB                                                                  8
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK                                                        0x0000ff00
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x)                                       (((x) & 0x0000ff00) >> 8)
+
+/* macros for BB_spur_est_cck_report_b0 */
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS                                                 0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET                                                  0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB                                          7
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB                                          0
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK                                0x000000ff
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x)               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB                                         15
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB                                          8
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK                                0x0000ff00
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x)               (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB                                            23
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB                                            16
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK                                   0x00ff0000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x)                 (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB                                            31
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB                                            24
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK                                   0xff000000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x)                 (((x) & 0xff000000) >> 24)
+
+/* macros for BB_chan_info_noise_pwr */
+#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS                                                    0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET                                                     0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB                                                    11
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB                                                     0
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK                                           0x00000fff
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x)                          (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_gain_diff */
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS                                                    0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET                                                     0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB                                                       11
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB                                                        0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK                                              0x00000fff
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x)                             (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_fine_timing */
+#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS                                                  0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET                                                   0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB                                                   11
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB                                                    0
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK                                          0x00000fff
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x)                         (((x) & 0x00000fff) >> 0)
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB                                                  21
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB                                                  12
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK                                         0x003ff000
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x)                       (((x) & 0x003ff000) >> 12)
+
+/* macros for BB_chan_info_gain_b0 */
+#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS                                                      0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET                                                       0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB                                                  7
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB                                                  0
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK                                        0x000000ff
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB                                              15
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB                                               8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK                                     0x0000ff00
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x)                    (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB                                           16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB                                           16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK                                  0x00010000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x)                (((x) & 0x00010000) >> 16)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB                                           17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB                                           17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK                                  0x00020000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x)                (((x) & 0x00020000) >> 17)
+
+/* macros for BB_chan_info_chan_tab_b0 */
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS                                                  0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET                                                   0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB                                                       5
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB                                                       0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK                                             0x0000003f
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB                                                      11
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB                                                       6
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK                                             0x00000fc0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x)                            (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB                                                        15
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB                                                        12
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK                                               0x0000f000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x)                             (((x) & 0x0000f000) >> 12)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB                                                      21
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB                                                      16
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK                                             0x003f0000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB                                                      27
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB                                                      22
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK                                             0x0fc00000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x)                           (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB                                                        31
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB                                                        28
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK                                               0xf0000000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x)                             (((x) & 0xf0000000) >> 28)
+
+/* macros for BB_paprd_am2am_mask */
+#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS                                                       0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET                                                        0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB                                                  24
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB                                                   0
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK                                         0x01ffffff
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x)                        (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x)                        (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_am2pm_mask */
+#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS                                                       0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET                                                        0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB                                                  24
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB                                                   0
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK                                         0x01ffffff
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x)                        (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x)                        (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ht40_mask */
+#define PHY_BB_PAPRD_HT40_MASK_ADDRESS                                                        0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_OFFSET                                                         0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB                                                    24
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB                                                     0
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK                                           0x01ffffff
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x)                          (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x)                          (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ctrl0 */
+#define PHY_BB_PAPRD_CTRL0_ADDRESS                                                            0x00009df0
+#define PHY_BB_PAPRD_CTRL0_OFFSET                                                             0x00009df0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB                                                            0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB                                                            0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK                                                  0x00000001
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB                                         1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB                                         1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK                               0x00000002
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x)              (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x)              (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB                                                       26
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB                                                        2
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK                                              0x07fffffc
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x)                             (((x) & 0x07fffffc) >> 2)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x)                             (((x) << 2) & 0x07fffffc)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB                                                        31
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB                                                        27
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK                                               0xf8000000
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x)                             (((x) & 0xf8000000) >> 27)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x)                             (((x) << 27) & 0xf8000000)
+
+/* macros for BB_paprd_ctrl1 */
+#define PHY_BB_PAPRD_CTRL1_ADDRESS                                                            0x00009df4
+#define PHY_BB_PAPRD_CTRL1_OFFSET                                                             0x00009df4
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB                                           0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB                                           0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK                                 0x00000001
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB                                             1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB                                             1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK                                   0x00000002
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x)                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x)                  (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB                                             2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB                                             2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK                                   0x00000004
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x)                  (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x)                  (((x) << 2) & 0x00000004)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB                                                8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB                                                3
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK                                      0x000001f8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x)                     (((x) & 0x000001f8) >> 3)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x)                     (((x) << 3) & 0x000001f8)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB                                                   16
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB                                                    9
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK                                          0x0001fe00
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x)                         (((x) & 0x0001fe00) >> 9)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x)                         (((x) << 9) & 0x0001fe00)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB                                                 26
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB                                                 17
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK                                        0x07fe0000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x)                      (((x) & 0x07fe0000) >> 17)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x)                      (((x) << 17) & 0x07fe0000)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB                                                27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB                                                27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK                                       0x08000000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x)                     (((x) & 0x08000000) >> 27)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x)                     (((x) << 27) & 0x08000000)
+
+/* macros for BB_pa_gain123 */
+#define PHY_BB_PA_GAIN123_ADDRESS                                                             0x00009df8
+#define PHY_BB_PA_GAIN123_OFFSET                                                              0x00009df8
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB                                                                 9
+#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB                                                                 0
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK                                                       0x000003ff
+#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB                                                                19
+#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB                                                                10
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK                                                       0x000ffc00
+#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x)                                     (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB                                                                29
+#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB                                                                20
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK                                                       0x3ff00000
+#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x)                                     (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x)                                     (((x) << 20) & 0x3ff00000)
+
+/* macros for BB_pa_gain45 */
+#define PHY_BB_PA_GAIN45_ADDRESS                                                              0x00009dfc
+#define PHY_BB_PA_GAIN45_OFFSET                                                               0x00009dfc
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB                                                                  9
+#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB                                                                  0
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK                                                        0x000003ff
+#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x)                                       (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x)                                       (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB                                                                 19
+#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB                                                                 10
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK                                                        0x000ffc00
+#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x)                                      (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x)                                      (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB                                               24
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB                                               20
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK                                      0x01f00000
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x)                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x)                    (((x) << 20) & 0x01f00000)
+
+/* macros for BB_paprd_pre_post_scale_0 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS                                                 0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET                                                  0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_1 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS                                                 0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET                                                  0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_2 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS                                                 0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET                                                  0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_3 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS                                                 0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET                                                  0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_4 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS                                                 0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET                                                  0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_5 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS                                                 0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET                                                  0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_6 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS                                                 0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET                                                  0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_7 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS                                                 0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET                                                  0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB                                    17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB                                     0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK                           0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x)          (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x)          (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_mem_tab */
+#define PHY_BB_PAPRD_MEM_TAB_ADDRESS                                                          0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_OFFSET                                                           0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB                                                            21
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB                                                             0
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK                                                   0x003fffff
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x)                                  (((x) & 0x003fffff) >> 0)
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x)                                  (((x) << 0) & 0x003fffff)
+
+/* macros for BB_peak_det_ctrl_1 */
+#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS                                                        0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_OFFSET                                                         0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB                                                   0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB                                                   0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK                                         0x00000001
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x)                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x)                        (((x) << 0) & 0x00000001)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB                                                        1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB                                                        1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK                                              0x00000002
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x)                             (((x) & 0x00000002) >> 1)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x)                             (((x) << 1) & 0x00000002)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB                                                    7
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB                                                    2
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK                                          0x000000fc
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x)                         (((x) & 0x000000fc) >> 2)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x)                         (((x) << 2) & 0x000000fc)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB                                             12
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB                                              8
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK                                    0x00001f00
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x)                   (((x) & 0x00001f00) >> 8)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x)                   (((x) << 8) & 0x00001f00)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB                                             17
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB                                             13
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK                                    0x0003e000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x)                  (((x) & 0x0003e000) >> 13)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x)                  (((x) << 13) & 0x0003e000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB                                            22
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB                                            18
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK                                   0x007c0000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x)                 (((x) & 0x007c0000) >> 18)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x)                 (((x) << 18) & 0x007c0000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB                                                  29
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB                                                  23
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK                                         0x3f800000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x)                       (((x) & 0x3f800000) >> 23)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x)                       (((x) << 23) & 0x3f800000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB                                               30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB                                               30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK                                      0x40000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x)                    (((x) & 0x40000000) >> 30)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x)                    (((x) << 30) & 0x40000000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB                                                31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB                                                31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK                                       0x80000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x)                     (((x) & 0x80000000) >> 31)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x)                     (((x) << 31) & 0x80000000)
+
+/* macros for BB_peak_det_ctrl_2 */
+#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS                                                        0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_OFFSET                                                         0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB                                              9
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB                                              0
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK                                    0x000003ff
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x)                   (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x)                   (((x) << 0) & 0x000003ff)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB                                                14
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB                                                10
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK                                       0x00007c00
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x)                     (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x)                     (((x) << 10) & 0x00007c00)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB                                                19
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB                                                15
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK                                       0x000f8000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x)                     (((x) & 0x000f8000) >> 15)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x)                     (((x) << 15) & 0x000f8000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB                                               24
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB                                               20
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK                                      0x01f00000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x)                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x)                    (((x) << 20) & 0x01f00000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB                                                29
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB                                                25
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK                                       0x3e000000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x)                     (((x) & 0x3e000000) >> 25)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x)                     (((x) << 25) & 0x3e000000)
+
+/* macros for BB_rx_gain_bounds_1 */
+#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS                                                       0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET                                                        0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB                                                     7
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB                                                     0
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK                                           0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB                                                15
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB                                                 8
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK                                       0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x)                      (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x)                      (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB                                                    23
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB                                                    16
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK                                           0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x)                         (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x)                         (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB                                                  24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB                                                  24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK                                         0x01000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x)                       (((x) & 0x01000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x)                       (((x) << 24) & 0x01000000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB                                                  25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB                                                  25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK                                         0x02000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x)                       (((x) & 0x02000000) >> 25)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x)                       (((x) << 25) & 0x02000000)
+
+/* macros for BB_rx_gain_bounds_2 */
+#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS                                                       0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET                                                        0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB                                                     7
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB                                                     0
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK                                           0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x)                          (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x)                          (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB                                             15
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB                                              8
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK                                    0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x)                   (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x)                   (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB                                                 23
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB                                                 16
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK                                        0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x)                      (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x)                      (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB                                             31
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB                                             24
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK                                    0xff000000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x)                  (((x) & 0xff000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x)                  (((x) << 24) & 0xff000000)
+
+/* macros for BB_peak_det_cal_ctrl */
+#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS                                                      0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET                                                       0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB                                                 5
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB                                                 0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK                                       0x0000003f
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x)                      (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x)                      (((x) << 0) & 0x0000003f)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB                                                   11
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB                                                    6
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK                                          0x00000fc0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x)                         (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x)                         (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB                                          13
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB                                          12
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK                                 0x00003000
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x)               (((x) & 0x00003000) >> 12)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x)               (((x) << 12) & 0x00003000)
+
+/* macros for BB_agc_dig_dc_ctrl */
+#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS                                                        0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET                                                         0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB                                                          0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB                                                          0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK                                                0x00000001
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x)                               (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x)                               (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB                                                   3
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB                                                   1
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK                                         0x0000000e
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x)                        (((x) & 0x0000000e) >> 1)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x)                        (((x) << 1) & 0x0000000e)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB                                                  9
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB                                                  4
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK                                        0x000003f0
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x)                       (((x) & 0x000003f0) >> 4)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x)                       (((x) << 4) & 0x000003f0)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB                                              31
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB                                              16
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK                                     0xffff0000
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x)                   (((x) & 0xffff0000) >> 16)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x)                   (((x) << 16) & 0xffff0000)
+
+/* macros for BB_agc_dig_dc_status_i_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS                                                 0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET                                                  0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB                                            8
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB                                            0
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK                                  0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB                                           17
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB                                            9
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK                                  0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x)                 (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB                                           26
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB                                           18
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK                                  0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x)                (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_agc_dig_dc_status_q_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS                                                 0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET                                                  0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB                                            8
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB                                            0
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK                                  0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x)                 (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB                                           17
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB                                            9
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK                                  0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x)                 (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB                                           26
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB                                           18
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK                                  0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x)                (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_bbb_txfir_0 */
+#define PHY_BB_BBB_TXFIR_0_ADDRESS                                                            0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_OFFSET                                                             0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB                                                          3
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK                                                0x0000000f
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x)                               (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x)                               (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB                                                         11
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK                                                0x00000f00
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x)                               (((x) & 0x00000f00) >> 8)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x)                               (((x) << 8) & 0x00000f00)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB                                                         20
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB                                                         16
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK                                                0x001f0000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x)                              (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x)                              (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB                                                         28
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB                                                         24
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK                                                0x1f000000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x)                              (((x) & 0x1f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x)                              (((x) << 24) & 0x1f000000)
+
+/* macros for BB_bbb_txfir_1 */
+#define PHY_BB_BBB_TXFIR_1_ADDRESS                                                            0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_OFFSET                                                             0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB                                                          5
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK                                                0x0000003f
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x)                               (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x)                               (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB                                                         13
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK                                                0x00003f00
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x)                               (((x) & 0x00003f00) >> 8)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x)                               (((x) << 8) & 0x00003f00)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB                                                         22
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB                                                         16
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK                                                0x007f0000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x)                              (((x) & 0x007f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x)                              (((x) << 16) & 0x007f0000)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB                                                         30
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB                                                         24
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK                                                0x7f000000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x)                              (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x)                              (((x) << 24) & 0x7f000000)
+
+/* macros for BB_bbb_txfir_2 */
+#define PHY_BB_BBB_TXFIR_2_ADDRESS                                                            0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_OFFSET                                                             0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB                                                          7
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB                                                          0
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK                                                0x000000ff
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x)                               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x)                               (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB                                                         15
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB                                                          8
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK                                                0x0000ff00
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x)                               (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x)                               (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB                                                        23
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB                                                        16
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK                                               0x00ff0000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x)                             (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x)                             (((x) << 16) & 0x00ff0000)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB                                                        31
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB                                                        24
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK                                               0xff000000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x)                             (((x) & 0xff000000) >> 24)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x)                             (((x) << 24) & 0xff000000)
+
+/* macros for BB_modes_select */
+#define PHY_BB_MODES_SELECT_ADDRESS                                                           0x0000a200
+#define PHY_BB_MODES_SELECT_OFFSET                                                            0x0000a200
+#define PHY_BB_MODES_SELECT_CCK_MODE_MSB                                                               0
+#define PHY_BB_MODES_SELECT_CCK_MODE_LSB                                                               0
+#define PHY_BB_MODES_SELECT_CCK_MODE_MASK                                                     0x00000001
+#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x)                                    (((x) & 0x00000001) >> 0)
+#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x)                                    (((x) << 0) & 0x00000001)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB                                                      2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB                                                      2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK                                            0x00000004
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x)                           (((x) & 0x00000004) >> 2)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x)                           (((x) << 2) & 0x00000004)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB                                                         5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB                                                         5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK                                               0x00000020
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x)                              (((x) & 0x00000020) >> 5)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x)                              (((x) << 5) & 0x00000020)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB                                                      6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB                                                      6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK                                            0x00000040
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x)                           (((x) & 0x00000040) >> 6)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x)                           (((x) << 6) & 0x00000040)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB                                                           7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB                                                           7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK                                                 0x00000080
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x)                                (((x) & 0x00000080) >> 7)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x)                                (((x) << 7) & 0x00000080)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB                                                    8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB                                                    8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK                                          0x00000100
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x)                         (((x) & 0x00000100) >> 8)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x)                         (((x) << 8) & 0x00000100)
+
+/* macros for BB_bbb_tx_ctrl */
+#define PHY_BB_BBB_TX_CTRL_ADDRESS                                                            0x0000a204
+#define PHY_BB_BBB_TX_CTRL_OFFSET                                                             0x0000a204
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB                                                       0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB                                                       0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK                                             0x00000001
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB                                                      1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB                                                      1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK                                            0x00000002
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x)                           (((x) & 0x00000002) >> 1)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x)                           (((x) << 1) & 0x00000002)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB                                                        3
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB                                                        2
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK                                              0x0000000c
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x)                             (((x) & 0x0000000c) >> 2)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x)                             (((x) << 2) & 0x0000000c)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB                                                         4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB                                                         4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK                                               0x00000010
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x)                              (((x) & 0x00000010) >> 4)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x)                              (((x) << 4) & 0x00000010)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB                                                       5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB                                                       5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK                                             0x00000020
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x)                            (((x) & 0x00000020) >> 5)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x)                            (((x) << 5) & 0x00000020)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB                                                          8
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB                                                          6
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK                                                0x000001c0
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x)                               (((x) & 0x000001c0) >> 6)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x)                               (((x) << 6) & 0x000001c0)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB                                                         11
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB                                                          9
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK                                                0x00000e00
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x)                               (((x) & 0x00000e00) >> 9)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x)                               (((x) << 9) & 0x00000e00)
+
+/* macros for BB_bbb_sig_detect */
+#define PHY_BB_BBB_SIG_DETECT_ADDRESS                                                         0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_OFFSET                                                          0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB                                                     5
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB                                                     0
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK                                           0x0000003f
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x)                          (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x)                          (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB                                                     12
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB                                                      6
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK                                            0x00001fc0
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x)                           (((x) & 0x00001fc0) >> 6)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x)                           (((x) << 6) & 0x00001fc0)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB                                                 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB                                                 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK                                        0x00002000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x)                      (((x) & 0x00002000) >> 13)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x)                      (((x) << 13) & 0x00002000)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB                                                    14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB                                                    14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK                                           0x00004000
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x)                         (((x) & 0x00004000) >> 14)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x)                         (((x) << 14) & 0x00004000)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB                                                    15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB                                                    15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK                                           0x00008000
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x)                         (((x) & 0x00008000) >> 15)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x)                         (((x) << 15) & 0x00008000)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB                                             16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB                                             16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK                                    0x00010000
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x)                  (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x)                  (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB                                             17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB                                             17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK                                    0x00020000
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x)                  (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x)                  (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB                                                18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB                                                18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK                                       0x00040000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x)                     (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x)                     (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB                                              19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB                                              19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK                                     0x00080000
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x)                   (((x) & 0x00080000) >> 19)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x)                   (((x) << 19) & 0x00080000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB                                                  20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB                                                  20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK                                         0x00100000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x)                       (((x) & 0x00100000) >> 20)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x)                       (((x) << 20) & 0x00100000)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB                                                21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB                                                21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK                                       0x00200000
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x)                     (((x) & 0x00200000) >> 21)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x)                     (((x) << 21) & 0x00200000)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB                                              22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB                                              22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK                                     0x00400000
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x)                   (((x) & 0x00400000) >> 22)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x)                   (((x) << 22) & 0x00400000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB                                             31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB                                             31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK                                    0x80000000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x)                  (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x)                  (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_atten_switch_ctl_b0 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS                                                0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET                                                 0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB                                                5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB                                                0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK                                      0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x)                     (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x)                     (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB                                               11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB                                                6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK                                      0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x)                     (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x)                     (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB                                           16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB                                           12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK                                  0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x)                (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x)                (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB                                           21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB                                           17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK                                  0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x)                (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x)                (((x) << 17) & 0x003e0000)
+
+/* macros for BB_bbb_rx_ctrl_1 */
+#define PHY_BB_BBB_RX_CTRL_1_ADDRESS                                                          0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_OFFSET                                                           0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB                                                2
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB                                                0
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK                                      0x00000007
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x)                     (((x) & 0x00000007) >> 0)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x)                     (((x) << 0) & 0x00000007)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB                                                  7
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB                                                  3
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK                                        0x000000f8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x)                       (((x) & 0x000000f8) >> 3)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x)                       (((x) << 3) & 0x000000f8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB                                                    10
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB                                                     8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK                                           0x00000700
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x)                          (((x) & 0x00000700) >> 8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x)                          (((x) << 8) & 0x00000700)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB                                                         15
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB                                                         11
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK                                                0x0000f800
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x)                              (((x) & 0x0000f800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x)                              (((x) << 11) & 0x0000f800)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB                                                        20
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB                                                        16
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK                                               0x001f0000
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x)                             (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x)                             (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB                                                       23
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB                                                       21
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK                                              0x00e00000
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x)                            (((x) & 0x00e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x)                            (((x) << 21) & 0x00e00000)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB                                                         30
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB                                                         24
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK                                                0x7f000000
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x)                              (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x)                              (((x) << 24) & 0x7f000000)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB                                                      31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB                                                      31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK                                             0x80000000
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x)                           (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x)                           (((x) << 31) & 0x80000000)
+
+/* macros for BB_bbb_rx_ctrl_2 */
+#define PHY_BB_BBB_RX_CTRL_2_ADDRESS                                                          0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_OFFSET                                                           0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB                                                   5
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB                                                   0
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK                                         0x0000003f
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x)                        (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x)                        (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB                                                        11
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB                                                         6
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK                                               0x00000fc0
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB                                               16
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB                                               12
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK                                      0x0001f000
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x)                    (((x) & 0x0001f000) >> 12)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x)                    (((x) << 12) & 0x0001f000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB                                             21
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB                                             17
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK                                    0x003e0000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x)                  (((x) & 0x003e0000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x)                  (((x) << 17) & 0x003e0000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB                                              25
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB                                              22
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK                                     0x03c00000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x)                   (((x) & 0x03c00000) >> 22)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x)                   (((x) << 22) & 0x03c00000)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB                                               31
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB                                               26
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK                                      0xfc000000
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x)                    (((x) & 0xfc000000) >> 26)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x)                    (((x) << 26) & 0xfc000000)
+
+/* macros for BB_bbb_rx_ctrl_3 */
+#define PHY_BB_BBB_RX_CTRL_3_ADDRESS                                                          0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_OFFSET                                                           0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB                                                  7
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB                                                  0
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK                                        0x000000ff
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x)                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x)                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB                                                  15
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB                                                   8
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK                                         0x0000ff00
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x)                        (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x)                        (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB                                                          23
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB                                                          16
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK                                                 0x00ff0000
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x)                               (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x)                               (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_bbb_rx_ctrl_4 */
+#define PHY_BB_BBB_RX_CTRL_4_ADDRESS                                                          0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_OFFSET                                                           0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB                                                          3
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB                                                          0
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK                                                0x0000000f
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x)                               (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x)                               (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB                                                 15
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB                                                  4
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK                                        0x0000fff0
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x)                       (((x) & 0x0000fff0) >> 4)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x)                       (((x) << 4) & 0x0000fff0)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB                                                16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB                                                16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK                                       0x00010000
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x)                     (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x)                     (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB                                                    17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB                                                    17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK                                           0x00020000
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x)                         (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x)                         (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB                                                       18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB                                                       18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK                                              0x00040000
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x)                            (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x)                            (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB                                                 24
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB                                                 19
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK                                        0x01f80000
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x)                      (((x) & 0x01f80000) >> 19)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x)                      (((x) << 19) & 0x01f80000)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB                                                       30
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB                                                       25
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK                                              0x7e000000
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x)                            (((x) & 0x7e000000) >> 25)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x)                            (((x) << 25) & 0x7e000000)
+
+/* macros for BB_bbb_rx_ctrl_5 */
+#define PHY_BB_BBB_RX_CTRL_5_ADDRESS                                                          0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_OFFSET                                                           0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB                                                4
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB                                                0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK                                      0x0000001f
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x)                     (((x) & 0x0000001f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x)                     (((x) << 0) & 0x0000001f)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB                                                9
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB                                                5
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK                                      0x000003e0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x)                     (((x) & 0x000003e0) >> 5)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x)                     (((x) << 5) & 0x000003e0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB                                               15
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB                                               10
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK                                      0x0000fc00
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x)                    (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x)                    (((x) << 10) & 0x0000fc00)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB                                                     20
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB                                                     16
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK                                            0x001f0000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x)                          (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x)                          (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB                                                     26
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB                                                     21
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK                                            0x07e00000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x)                          (((x) & 0x07e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x)                          (((x) << 21) & 0x07e00000)
+
+/* macros for BB_bbb_rx_ctrl_6 */
+#define PHY_BB_BBB_RX_CTRL_6_ADDRESS                                                          0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_OFFSET                                                           0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB                                                      9
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB                                                      0
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK                                            0x000003ff
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x)                           (((x) & 0x000003ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x)                           (((x) << 0) & 0x000003ff)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB                                                         10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB                                                         10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK                                                0x00000400
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x)                              (((x) & 0x00000400) >> 10)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x)                              (((x) << 10) & 0x00000400)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB                                                      20
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB                                                      11
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK                                             0x001ff800
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x)                           (((x) & 0x001ff800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x)                           (((x) << 11) & 0x001ff800)
+
+/* macros for BB_bbb_dagc_ctrl */
+#define PHY_BB_BBB_DAGC_CTRL_ADDRESS                                                          0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_OFFSET                                                           0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB                                                       0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB                                                       0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK                                             0x00000001
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB                                                   8
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB                                                   1
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK                                         0x000001fe
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x)                        (((x) & 0x000001fe) >> 1)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x)                        (((x) << 1) & 0x000001fe)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB                                                9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB                                                9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK                                      0x00000200
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x)                     (((x) & 0x00000200) >> 9)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x)                     (((x) << 9) & 0x00000200)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB                                                      16
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB                                                      10
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK                                             0x0001fc00
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x)                           (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x)                           (((x) << 10) & 0x0001fc00)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB                                                   17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB                                                   17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK                                          0x00020000
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x)                        (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x)                        (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB                                                            23
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB                                                            18
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK                                                   0x00fc0000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x)                                 (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x)                                 (((x) << 18) & 0x00fc0000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB                                                  27
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB                                                  24
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK                                         0x0f000000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x)                       (((x) & 0x0f000000) >> 24)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x)                       (((x) << 24) & 0x0f000000)
+
+/* macros for BB_force_clken_cck */
+#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS                                                        0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_OFFSET                                                         0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB                                                    0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB                                                    0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK                                          0x00000001
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x)                         (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x)                         (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB                                                    1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB                                                    1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK                                          0x00000002
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB                                                    2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB                                                    2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK                                          0x00000004
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x)                         (((x) & 0x00000004) >> 2)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x)                         (((x) << 2) & 0x00000004)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB                                                    3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB                                                    3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK                                          0x00000008
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x)                         (((x) & 0x00000008) >> 3)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x)                         (((x) << 3) & 0x00000008)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB                                                     4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB                                                     4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK                                           0x00000010
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x)                          (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x)                          (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB                                                    5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB                                                    5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK                                          0x00000020
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x)                         (((x) & 0x00000020) >> 5)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x)                         (((x) << 5) & 0x00000020)
+
+/* macros for BB_rx_clear_delay */
+#define PHY_BB_RX_CLEAR_DELAY_ADDRESS                                                         0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFFSET                                                          0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB                                               9
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB                                               0
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK                                     0x000003ff
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x)                    (((x) & 0x000003ff) >> 0)
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x)                    (((x) << 0) & 0x000003ff)
+
+/* macros for BB_powertx_rate3 */
+#define PHY_BB_POWERTX_RATE3_ADDRESS                                                          0x0000a234
+#define PHY_BB_POWERTX_RATE3_OFFSET                                                           0x0000a234
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB                                                            5
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB                                                            0
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK                                                  0x0000003f
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x)                                 (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x)                                 (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB                                                           21
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB                                                           16
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK                                                  0x003f0000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x)                                (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x)                                (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB                                                           29
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB                                                           24
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK                                                  0x3f000000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x)                                (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x)                                (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate4 */
+#define PHY_BB_POWERTX_RATE4_ADDRESS                                                          0x0000a238
+#define PHY_BB_POWERTX_RATE4_OFFSET                                                           0x0000a238
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB                                                           5
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB                                                           0
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK                                                 0x0000003f
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x)                                (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x)                                (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB                                                          13
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB                                                           8
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK                                                 0x00003f00
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x)                                (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB                                                          21
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB                                                          16
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK                                                 0x003f0000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x)                               (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x)                               (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB                                                          29
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB                                                          24
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK                                                 0x3f000000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x)                               (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x)                               (((x) << 24) & 0x3f000000)
+
+/* macros for BB_cck_spur_mit */
+#define PHY_BB_CCK_SPUR_MIT_ADDRESS                                                           0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_OFFSET                                                            0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB                                                       0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB                                                       0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK                                             0x00000001
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x)                            (((x) & 0x00000001) >> 0)
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x)                            (((x) << 0) & 0x00000001)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB                                                          8
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB                                                          1
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK                                                0x000001fe
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x)                               (((x) & 0x000001fe) >> 1)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x)                               (((x) << 1) & 0x000001fe)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB                                                         28
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB                                                          9
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK                                                0x1ffffe00
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x)                               (((x) & 0x1ffffe00) >> 9)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x)                               (((x) << 9) & 0x1ffffe00)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB                                                      30
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB                                                      29
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK                                             0x60000000
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x)                           (((x) & 0x60000000) >> 29)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x)                           (((x) << 29) & 0x60000000)
+
+/* macros for BB_panic_watchdog_status */
+#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS                                                  0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET                                                   0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB                                       2
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB                                       0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK                             0x00000007
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x)            (((x) & 0x00000007) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x)            (((x) << 0) & 0x00000007)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB                                       3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB                                       3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK                             0x00000008
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x)            (((x) & 0x00000008) >> 3)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x)            (((x) << 3) & 0x00000008)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB                                       7
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB                                       4
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK                             0x000000f0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x)            (((x) & 0x000000f0) >> 4)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x)            (((x) << 4) & 0x000000f0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB                                      11
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB                                       8
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK                             0x00000f00
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x)            (((x) & 0x00000f00) >> 8)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x)            (((x) << 8) & 0x00000f00)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB                                      15
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB                                      12
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK                             0x0000f000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x)           (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x)           (((x) << 12) & 0x0000f000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB                                      19
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB                                      16
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK                             0x000f0000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x)           (((x) & 0x000f0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x)           (((x) << 16) & 0x000f0000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB                                      23
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB                                      20
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK                             0x00f00000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x)           (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x)           (((x) << 20) & 0x00f00000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB                                      27
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB                                      24
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK                             0x0f000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x)           (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x)           (((x) << 24) & 0x0f000000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB                                      31
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB                                      28
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK                             0xf0000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x)           (((x) & 0xf0000000) >> 28)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x)           (((x) << 28) & 0xf0000000)
+
+/* macros for BB_panic_watchdog_ctrl_1 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS                                                  0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET                                                   0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB                                0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB                                0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK                      0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x)     (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x)     (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB                                    1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB                                    1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK                          0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x)         (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x)         (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB                                15
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB                                 2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK                       0x0000fffc
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x)      (((x) & 0x0000fffc) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x)      (((x) << 2) & 0x0000fffc)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB                                    31
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB                                    16
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK                           0xffff0000
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x)         (((x) & 0xffff0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x)         (((x) << 16) & 0xffff0000)
+
+/* macros for BB_panic_watchdog_ctrl_2 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS                                                  0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET                                                   0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB                                            0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB                                            0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK                                  0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x)                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x)                 (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB                                      1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB                                      1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK                            0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x)           (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x)           (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB                                        2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB                                        2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK                              0x00000004
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x)             (((x) & 0x00000004) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x)             (((x) << 2) & 0x00000004)
+
+/* macros for BB_iqcorr_ctrl_cck */
+#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS                                                        0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_OFFSET                                                         0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB                                                 4
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB                                                 0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK                                       0x0000001f
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x)                      (((x) & 0x0000001f) >> 0)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x)                      (((x) << 0) & 0x0000001f)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB                                                10
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB                                                 5
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK                                       0x000007e0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x)                      (((x) & 0x000007e0) >> 5)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x)                      (((x) << 5) & 0x000007e0)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB                                                  11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB                                                  11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK                                         0x00000800
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x)                       (((x) & 0x00000800) >> 11)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x)                       (((x) << 11) & 0x00000800)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB                                                13
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB                                                12
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK                                       0x00003000
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x)                     (((x) & 0x00003000) >> 12)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x)                     (((x) << 12) & 0x00003000)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB                                                15
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB                                                14
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK                                       0x0000c000
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x)                     (((x) & 0x0000c000) >> 14)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x)                     (((x) << 14) & 0x0000c000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB                                                 20
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB                                                 16
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK                                        0x001f0000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x)                      (((x) & 0x001f0000) >> 16)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x)                      (((x) << 16) & 0x001f0000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB                                                    21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB                                                    21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK                                           0x00200000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x)                         (((x) & 0x00200000) >> 21)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x)                         (((x) << 21) & 0x00200000)
+
+/* macros for BB_bluetooth_cntl */
+#define PHY_BB_BLUETOOTH_CNTL_ADDRESS                                                         0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_OFFSET                                                          0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB                                                      0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB                                                      0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK                                            0x00000001
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB                                                     1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB                                                     1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK                                           0x00000002
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x)                          (((x) & 0x00000002) >> 1)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x)                          (((x) << 1) & 0x00000002)
+
+/* macros for BB_tpc_1 */
+#define PHY_BB_TPC_1_ADDRESS                                                                  0x0000a258
+#define PHY_BB_TPC_1_OFFSET                                                                   0x0000a258
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB                                                                0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB                                                                0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK                                                      0x00000001
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x)                                     (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x)                                     (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB                                                               5
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB                                                               1
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK                                                     0x0000003e
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x)                                    (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x)                                    (((x) << 1) & 0x0000003e)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB                                                          13
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB                                                           6
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK                                                 0x00003fc0
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x)                                (((x) & 0x00003fc0) >> 6)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x)                                (((x) << 6) & 0x00003fc0)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB                                                                  15
+#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB                                                                  14
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK                                                         0x0000c000
+#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x)                                       (((x) & 0x0000c000) >> 14)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x)                                       (((x) << 14) & 0x0000c000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB                                                             17
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB                                                             16
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK                                                    0x00030000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x)                                  (((x) & 0x00030000) >> 16)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x)                                  (((x) << 16) & 0x00030000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB                                                             19
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB                                                             18
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK                                                    0x000c0000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x)                                  (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x)                                  (((x) << 18) & 0x000c0000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB                                                             21
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB                                                             20
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK                                                    0x00300000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x)                                  (((x) & 0x00300000) >> 20)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x)                                  (((x) << 20) & 0x00300000)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB                                                          22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB                                                          22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK                                                 0x00400000
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x)                               (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x)                               (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB                                                            28
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB                                                            23
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK                                                   0x1f800000
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x)                                 (((x) & 0x1f800000) >> 23)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x)                                 (((x) << 23) & 0x1f800000)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB                                                             29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB                                                             29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK                                                    0x20000000
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x)                                  (((x) & 0x20000000) >> 29)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x)                                  (((x) << 29) & 0x20000000)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB                                                            31
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB                                                            30
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK                                                   0xc0000000
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x)                                 (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x)                                 (((x) << 30) & 0xc0000000)
+
+/* macros for BB_tpc_2 */
+#define PHY_BB_TPC_2_ADDRESS                                                                  0x0000a25c
+#define PHY_BB_TPC_2_OFFSET                                                                   0x0000a25c
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB                                                          7
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB                                                          0
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK                                                0x000000ff
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x)                               (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x)                               (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB                                                      15
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB                                                       8
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK                                             0x0000ff00
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB                                                       23
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB                                                       16
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK                                              0x00ff0000
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x)                            (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_tpc_3 */
+#define PHY_BB_TPC_3_ADDRESS                                                                  0x0000a260
+#define PHY_BB_TPC_3_OFFSET                                                                   0x0000a260
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB                                                            7
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB                                                            0
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK                                                  0x000000ff
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x)                                 (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x)                                 (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB                                                          15
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB                                                           8
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK                                                 0x0000ff00
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x)                                (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x)                                (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB                                                         18
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB                                                         16
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK                                                0x00070000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x)                              (((x) & 0x00070000) >> 16)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x)                              (((x) << 16) & 0x00070000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB                                                            21
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB                                                            19
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK                                                   0x00380000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x)                                 (((x) & 0x00380000) >> 19)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x)                                 (((x) << 19) & 0x00380000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB                                                           24
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB                                                           22
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK                                                  0x01c00000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x)                                (((x) & 0x01c00000) >> 22)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x)                                (((x) << 22) & 0x01c00000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB                                                            27
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB                                                            25
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK                                                   0x0e000000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x)                                 (((x) & 0x0e000000) >> 25)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x)                                 (((x) << 25) & 0x0e000000)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB                                                          31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB                                                          31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK                                                 0x80000000
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_tpc_4_b0 */
+#define PHY_BB_TPC_4_B0_ADDRESS                                                               0x0000a264
+#define PHY_BB_TPC_4_B0_OFFSET                                                                0x0000a264
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB                                                             0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB                                                             0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK                                                   0x00000001
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB                                                               8
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB                                                               1
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK                                                     0x000001fe
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x)                                    (((x) & 0x000001fe) >> 1)
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB                                                                13
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB                                                                 9
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK                                                       0x00003e00
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x)                                      (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB                                                         19
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB                                                         14
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK                                                0x000fc000
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x)                              (((x) & 0x000fc000) >> 14)
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB                                                               24
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB                                                               20
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK                                                      0x01f00000
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x)                                    (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB                                             30
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB                                             25
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK                                    0x7e000000
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x)                  (((x) & 0x7e000000) >> 25)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x)                  (((x) << 25) & 0x7e000000)
+
+/* macros for BB_analog_swap */
+#define PHY_BB_ANALOG_SWAP_ADDRESS                                                            0x0000a268
+#define PHY_BB_ANALOG_SWAP_OFFSET                                                             0x0000a268
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB                                                     2
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB                                                     0
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK                                           0x00000007
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x)                          (((x) & 0x00000007) >> 0)
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x)                          (((x) << 0) & 0x00000007)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB                                                     5
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB                                                     3
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK                                           0x00000038
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x)                          (((x) & 0x00000038) >> 3)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x)                          (((x) << 3) & 0x00000038)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB                                                            6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB                                                            6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK                                                  0x00000040
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x)                                 (((x) & 0x00000040) >> 6)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x)                                 (((x) << 6) & 0x00000040)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB                                                  7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB                                                  7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK                                        0x00000080
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x)                       (((x) & 0x00000080) >> 7)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x)                       (((x) << 7) & 0x00000080)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB                                               8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB                                               8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK                                     0x00000100
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x)                    (((x) & 0x00000100) >> 8)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x)                    (((x) << 8) & 0x00000100)
+
+/* macros for BB_tpc_5_b0 */
+#define PHY_BB_TPC_5_B0_ADDRESS                                                               0x0000a26c
+#define PHY_BB_TPC_5_B0_OFFSET                                                                0x0000a26c
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB                                                            3
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB                                                            0
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK                                                  0x0000000f
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x)                                 (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x)                                 (((x) << 0) & 0x0000000f)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB                                                       9
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB                                                       4
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK                                             0x000003f0
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x)                            (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x)                            (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB                                                      15
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB                                                      10
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK                                             0x0000fc00
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x)                           (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x)                           (((x) << 10) & 0x0000fc00)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB                                                      21
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB                                                      16
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK                                             0x003f0000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB                                                      27
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB                                                      22
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK                                             0x0fc00000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x)                           (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x)                           (((x) << 22) & 0x0fc00000)
+
+/* macros for BB_tpc_6_b0 */
+#define PHY_BB_TPC_6_B0_ADDRESS                                                               0x0000a270
+#define PHY_BB_TPC_6_B0_OFFSET                                                                0x0000a270
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB                                                         5
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB                                                         0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK                                               0x0000003f
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB                                                        11
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB                                                         6
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK                                               0x00000fc0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x)                              (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x)                              (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB                                                        17
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB                                                        12
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK                                               0x0003f000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x)                             (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x)                             (((x) << 12) & 0x0003f000)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB                                                        23
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB                                                        18
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK                                               0x00fc0000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x)                             (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x)                             (((x) << 18) & 0x00fc0000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB                                                            25
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB                                                            24
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK                                                   0x03000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x)                                 (((x) & 0x03000000) >> 24)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x)                                 (((x) << 24) & 0x03000000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB                                                    28
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB                                                    26
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK                                           0x1c000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x)                         (((x) & 0x1c000000) >> 26)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x)                         (((x) << 26) & 0x1c000000)
+
+/* macros for BB_tpc_7 */
+#define PHY_BB_TPC_7_ADDRESS                                                                  0x0000a274
+#define PHY_BB_TPC_7_OFFSET                                                                   0x0000a274
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB                                                             5
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB                                                             0
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK                                                   0x0000003f
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x)                                  (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x)                                  (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB                                                         11
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB                                                          6
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK                                                0x00000fc0
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x)                               (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x)                               (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB                                                               12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB                                                               12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK                                                      0x00001000
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x)                                    (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x)                                    (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB                                                             13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB                                                             13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK                                                    0x00002000
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x)                                  (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x)                                  (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB                                                      14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB                                                      14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK                                             0x00004000
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x)                           (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x)                           (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB                                    15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB                                    15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK                           0x00008000
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x)         (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x)         (((x) << 15) & 0x00008000)
+
+/* macros for BB_tpc_8 */
+#define PHY_BB_TPC_8_ADDRESS                                                                  0x0000a278
+#define PHY_BB_TPC_8_OFFSET                                                                   0x0000a278
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB                                                               4
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB                                                               0
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK                                                     0x0000001f
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB                                                               9
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB                                                               5
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK                                                     0x000003e0
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x)                                    (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x)                                    (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB                                                              14
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB                                                              10
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK                                                     0x00007c00
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x)                                   (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x)                                   (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB                                                              19
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB                                                              15
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK                                                     0x000f8000
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x)                                   (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x)                                   (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB                                                              24
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB                                                              20
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK                                                     0x01f00000
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x)                                   (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x)                                   (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB                                                              29
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB                                                              25
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK                                                     0x3e000000
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x)                                   (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x)                                   (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_9 */
+#define PHY_BB_TPC_9_ADDRESS                                                                  0x0000a27c
+#define PHY_BB_TPC_9_OFFSET                                                                   0x0000a27c
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB                                                               4
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB                                                               0
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK                                                     0x0000001f
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB                                                               9
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB                                                               5
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK                                                     0x000003e0
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x)                                    (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x)                                    (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB                                                            14
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB                                                            10
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK                                                   0x00007c00
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x)                                 (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x)                                 (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB                                                          20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB                                                          20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK                                                 0x00100000
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x)                               (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x)                               (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB                                                             26
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB                                                             21
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK                                                    0x07e00000
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x)                                  (((x) & 0x07e00000) >> 21)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x)                                  (((x) << 21) & 0x07e00000)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB                                                            30
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB                                                            27
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK                                                   0x78000000
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x)                                 (((x) & 0x78000000) >> 27)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x)                                 (((x) << 27) & 0x78000000)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB                                            31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB                                            31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK                                   0x80000000
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x)                 (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x)                 (((x) << 31) & 0x80000000)
+
+/* macros for BB_pdadc_tab_b0 */
+#define PHY_BB_PDADC_TAB_B0_ADDRESS                                                           0x0000a280
+#define PHY_BB_PDADC_TAB_B0_OFFSET                                                            0x0000a280
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB                                                             31
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB                                                              0
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK                                                    0xffffffff
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x)                                   (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_tab_b0 */
+#define PHY_BB_CL_TAB_B0_ADDRESS                                                              0x0000a300
+#define PHY_BB_CL_TAB_B0_OFFSET                                                               0x0000a300
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB                                                               4
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB                                                               0
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK                                                     0x0000001f
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x)                                    (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x)                                    (((x) << 0) & 0x0000001f)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB                                                         15
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB                                                          5
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK                                                0x0000ffe0
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x)                               (((x) & 0x0000ffe0) >> 5)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x)                               (((x) << 5) & 0x0000ffe0)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB                                                         26
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB                                                         16
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK                                                0x07ff0000
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x)                              (((x) & 0x07ff0000) >> 16)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x)                              (((x) << 16) & 0x07ff0000)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB                                                                  30
+#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB                                                                  27
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK                                                         0x78000000
+#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x)                                       (((x) & 0x78000000) >> 27)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x)                                       (((x) << 27) & 0x78000000)
+
+/* macros for BB_cl_map_0_b0 */
+#define PHY_BB_CL_MAP_0_B0_ADDRESS                                                            0x0000a340
+#define PHY_BB_CL_MAP_0_B0_OFFSET                                                             0x0000a340
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB                                                               31
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB                                                                0
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_1_b0 */
+#define PHY_BB_CL_MAP_1_B0_ADDRESS                                                            0x0000a344
+#define PHY_BB_CL_MAP_1_B0_OFFSET                                                             0x0000a344
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB                                                               31
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB                                                                0
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_2_b0 */
+#define PHY_BB_CL_MAP_2_B0_ADDRESS                                                            0x0000a348
+#define PHY_BB_CL_MAP_2_B0_OFFSET                                                             0x0000a348
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB                                                               31
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB                                                                0
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_3_b0 */
+#define PHY_BB_CL_MAP_3_B0_ADDRESS                                                            0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_OFFSET                                                             0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB                                                               31
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB                                                                0
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK                                                      0xffffffff
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x)                                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x)                                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_cal_ctrl */
+#define PHY_BB_CL_CAL_CTRL_ADDRESS                                                            0x0000a358
+#define PHY_BB_CL_CAL_CTRL_OFFSET                                                             0x0000a358
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB                                                     0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB                                                     0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK                                           0x00000001
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x)                          (((x) & 0x00000001) >> 0)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x)                          (((x) << 0) & 0x00000001)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB                                                     1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB                                                     1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK                                           0x00000002
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x)                          (((x) & 0x00000002) >> 1)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x)                          (((x) << 1) & 0x00000002)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB                                                       3
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB                                                       2
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK                                             0x0000000c
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x)                            (((x) & 0x0000000c) >> 2)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x)                            (((x) << 2) & 0x0000000c)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB                                                    7
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB                                                    4
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK                                          0x000000f0
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x)                         (((x) & 0x000000f0) >> 4)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x)                         (((x) << 4) & 0x000000f0)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB                                                   15
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB                                                    8
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK                                          0x0000ff00
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x)                         (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x)                         (((x) << 8) & 0x0000ff00)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB                                                     21
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB                                                     16
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK                                            0x003f0000
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x)                          (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x)                          (((x) << 16) & 0x003f0000)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB                                                           29
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB                                                           22
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK                                                  0x3fc00000
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x)                                (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x)                                (((x) << 22) & 0x3fc00000)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB                                                  30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB                                                  30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK                                         0x40000000
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x)                       (((x) & 0x40000000) >> 30)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x)                       (((x) << 30) & 0x40000000)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB                                                          31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB                                                          31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK                                                 0x80000000
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x)                               (((x) & 0x80000000) >> 31)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x)                               (((x) << 31) & 0x80000000)
+
+/* macros for BB_cl_map_pal_0_b0 */
+#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS                                                        0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET                                                         0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_1_b0 */
+#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS                                                        0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET                                                         0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_2_b0 */
+#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS                                                        0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET                                                         0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_3_b0 */
+#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS                                                        0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET                                                         0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB                                                           31
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB                                                            0
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK                                                  0xffffffff
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x)                                 (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x)                                 (((x) << 0) & 0xffffffff)
+
+/* macros for BB_rifs */
+#define PHY_BB_RIFS_ADDRESS                                                                   0x0000a388
+#define PHY_BB_RIFS_OFFSET                                                                    0x0000a388
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB                                                               25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB                                                               25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK                                                      0x02000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x)                                    (((x) & 0x02000000) >> 25)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x)                                    (((x) << 25) & 0x02000000)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB                                                          26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB                                                          26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK                                                 0x04000000
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x)                               (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x)                               (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB                                                              27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB                                                              27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK                                                     0x08000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x)                                   (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x)                                   (((x) << 27) & 0x08000000)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB                                                          28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB                                                          28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK                                                 0x10000000
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x)                               (((x) & 0x10000000) >> 28)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x)                               (((x) << 28) & 0x10000000)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB                                                       29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB                                                       29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK                                              0x20000000
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x)                            (((x) & 0x20000000) >> 29)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x)                            (((x) << 29) & 0x20000000)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB                                                       30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB                                                       30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK                                              0x40000000
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x)                            (((x) & 0x40000000) >> 30)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x)                            (((x) << 30) & 0x40000000)
+
+/* macros for BB_powertx_rate5 */
+#define PHY_BB_POWERTX_RATE5_ADDRESS                                                          0x0000a38c
+#define PHY_BB_POWERTX_RATE5_OFFSET                                                           0x0000a38c
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB                                                         5
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB                                                         0
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB                                                        13
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB                                                         8
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB                                                        21
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB                                                        16
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB                                                        29
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB                                                        24
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate6 */
+#define PHY_BB_POWERTX_RATE6_ADDRESS                                                          0x0000a390
+#define PHY_BB_POWERTX_RATE6_OFFSET                                                           0x0000a390
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB                                                         5
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB                                                         0
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB                                                        13
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB                                                         8
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB                                                        21
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB                                                        16
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB                                                        29
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB                                                        24
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_10 */
+#define PHY_BB_TPC_10_ADDRESS                                                                 0x0000a394
+#define PHY_BB_TPC_10_OFFSET                                                                  0x0000a394
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB                                                         4
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB                                                         0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK                                               0x0000001f
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB                                                         9
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB                                                         5
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK                                               0x000003e0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB                                                        14
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB                                                        10
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK                                               0x00007c00
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x)                             (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x)                             (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB                                                        19
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB                                                        15
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK                                               0x000f8000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x)                             (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x)                             (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB                                                        24
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB                                                        20
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK                                               0x01f00000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x)                             (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x)                             (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB                                                        29
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB                                                        25
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK                                               0x3e000000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x)                             (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x)                             (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_11_b0 */
+#define PHY_BB_TPC_11_B0_ADDRESS                                                              0x0000a398
+#define PHY_BB_TPC_11_B0_OFFSET                                                               0x0000a398
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB                                                      4
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB                                                      0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK                                            0x0000001f
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x)                           (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x)                           (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB                                                      9
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB                                                      5
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK                                            0x000003e0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x)                           (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x)                           (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB                                                        23
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB                                                        16
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK                                               0x00ff0000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x)                             (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x)                             (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB                                                 31
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB                                                 24
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK                                        0xff000000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x)                      (((x) & 0xff000000) >> 24)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x)                      (((x) << 24) & 0xff000000)
+
+/* macros for BB_cal_chain_mask */
+#define PHY_BB_CAL_CHAIN_MASK_ADDRESS                                                         0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_OFFSET                                                          0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB                                                       2
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB                                                       0
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK                                             0x00000007
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x)                            (((x) & 0x00000007) >> 0)
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x)                            (((x) << 0) & 0x00000007)
+
+/* macros for BB_powertx_sub */
+#define PHY_BB_POWERTX_SUB_ADDRESS                                                            0x0000a3bc
+#define PHY_BB_POWERTX_SUB_OFFSET                                                             0x0000a3bc
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB                                                  5
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB                                                  0
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK                                        0x0000003f
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x)                       (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x)                       (((x) << 0) & 0x0000003f)
+
+/* macros for BB_powertx_rate7 */
+#define PHY_BB_POWERTX_RATE7_ADDRESS                                                          0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_OFFSET                                                           0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB                                                         5
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB                                                         0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB                                                        13
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB                                                         8
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB                                                        21
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB                                                        16
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB                                                        29
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB                                                        24
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate8 */
+#define PHY_BB_POWERTX_RATE8_ADDRESS                                                          0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_OFFSET                                                           0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB                                                         5
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB                                                         0
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK                                               0x0000003f
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x)                              (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x)                              (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB                                                        13
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB                                                         8
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK                                               0x00003f00
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x)                              (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x)                              (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB                                                        21
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB                                                        16
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK                                               0x003f0000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x)                             (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x)                             (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB                                                        29
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB                                                        24
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK                                               0x3f000000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x)                             (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x)                             (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate9 */
+#define PHY_BB_POWERTX_RATE9_ADDRESS                                                          0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_OFFSET                                                           0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB                                                     5
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB                                                     0
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK                                           0x0000003f
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x)                          (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x)                          (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB                                                   13
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB                                                    8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK                                          0x00003f00
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x)                         (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x)                         (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB                                                    21
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB                                                    16
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK                                           0x003f0000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x)                         (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x)                         (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB                                                   29
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB                                                   24
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK                                          0x3f000000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x)                        (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x)                        (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate10 */
+#define PHY_BB_POWERTX_RATE10_ADDRESS                                                         0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_OFFSET                                                          0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB                                                        5
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB                                                        0
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK                                              0x0000003f
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x)                             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x)                             (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB                                                       13
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB                                                        8
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK                                              0x00003f00
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x)                             (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x)                             (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB                                                      21
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB                                                      16
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB                                                      29
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB                                                      24
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate11 */
+#define PHY_BB_POWERTX_RATE11_ADDRESS                                                         0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_OFFSET                                                          0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB                                                       5
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB                                                       0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK                                             0x0000003f
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x)                            (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB                                                      13
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB                                                       8
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK                                             0x00003f00
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x)                            (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x)                            (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB                                                      21
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB                                                      16
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB                                                      29
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB                                                      24
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate12 */
+#define PHY_BB_POWERTX_RATE12_ADDRESS                                                         0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_OFFSET                                                          0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB                                                        5
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB                                                        0
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK                                              0x0000003f
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x)                             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x)                             (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB                                                       13
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB                                                        8
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK                                              0x00003f00
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x)                             (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x)                             (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB                                                      21
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB                                                      16
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK                                             0x003f0000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x)                           (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x)                           (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB                                                      29
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB                                                      24
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK                                             0x3f000000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x)                           (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x)                           (((x) << 24) & 0x3f000000)
+
+/* macros for BB_force_analog */
+#define PHY_BB_FORCE_ANALOG_ADDRESS                                                           0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_OFFSET                                                            0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB                                                            0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB                                                            0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK                                                  0x00000001
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x)                                 (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x)                                 (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB                                                           3
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB                                                           1
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK                                                 0x0000000e
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x)                                (((x) & 0x0000000e) >> 1)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x)                                (((x) << 1) & 0x0000000e)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB                                                        4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB                                                        4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK                                              0x00000010
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x)                             (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x)                             (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB                                                       7
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB                                                       5
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK                                             0x000000e0
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x)                            (((x) & 0x000000e0) >> 5)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x)                            (((x) << 5) & 0x000000e0)
+
+/* macros for BB_tpc_12 */
+#define PHY_BB_TPC_12_ADDRESS                                                                 0x0000a3dc
+#define PHY_BB_TPC_12_OFFSET                                                                  0x0000a3dc
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB                                                         4
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB                                                         0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK                                               0x0000001f
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB                                                         9
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB                                                         5
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK                                               0x000003e0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB                                                        14
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB                                                        10
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK                                               0x00007c00
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x)                             (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x)                             (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB                                                        19
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB                                                        15
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK                                               0x000f8000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x)                             (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x)                             (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB                                                        24
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB                                                        20
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK                                               0x01f00000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x)                             (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x)                             (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB                                                        29
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB                                                        25
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK                                               0x3e000000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x)                             (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x)                             (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_13 */
+#define PHY_BB_TPC_13_ADDRESS                                                                 0x0000a3e0
+#define PHY_BB_TPC_13_OFFSET                                                                  0x0000a3e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB                                                         4
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB                                                         0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK                                               0x0000001f
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB                                                         9
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB                                                         5
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK                                               0x000003e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x)                              (((x) << 5) & 0x000003e0)
+
+/* macros for BB_tpc_14 */
+#define PHY_BB_TPC_14_ADDRESS                                                                 0x0000a3e4
+#define PHY_BB_TPC_14_OFFSET                                                                  0x0000a3e4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB                                                         4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB                                                         0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK                                               0x0000001f
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB                                                         9
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB                                                         5
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK                                               0x000003e0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB                                                       14
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB                                                       10
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK                                              0x00007c00
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x)                            (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x)                            (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB                                                       19
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB                                                       15
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK                                              0x000f8000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x)                            (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x)                            (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB                                                       24
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB                                                       20
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK                                              0x01f00000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x)                            (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x)                            (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB                                                       29
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB                                                       25
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK                                              0x3e000000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x)                            (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x)                            (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_15 */
+#define PHY_BB_TPC_15_ADDRESS                                                                 0x0000a3e8
+#define PHY_BB_TPC_15_OFFSET                                                                  0x0000a3e8
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB                                                         4
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB                                                         0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK                                               0x0000001f
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x)                              (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x)                              (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB                                                         9
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB                                                         5
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK                                               0x000003e0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x)                              (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x)                              (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB                                                       14
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB                                                       10
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK                                              0x00007c00
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x)                            (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x)                            (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB                                                       19
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB                                                       15
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK                                              0x000f8000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x)                            (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x)                            (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB                                                       24
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB                                                       20
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK                                              0x01f00000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x)                            (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x)                            (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB                                                       29
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB                                                       25
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK                                              0x3e000000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x)                            (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x)                            (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_16 */
+#define PHY_BB_TPC_16_ADDRESS                                                                 0x0000a3ec
+#define PHY_BB_TPC_16_OFFSET                                                                  0x0000a3ec
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB                                                          13
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB                                                           8
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK                                                 0x00003f00
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x)                                (((x) & 0x00003f00) >> 8)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x)                                (((x) << 8) & 0x00003f00)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB                                                         21
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB                                                         16
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK                                                0x003f0000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x)                              (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x)                              (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB                                                         29
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB                                                         24
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK                                                0x3f000000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x)                              (((x) & 0x3f000000) >> 24)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x)                              (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_17 */
+#define PHY_BB_TPC_17_ADDRESS                                                                 0x0000a3f0
+#define PHY_BB_TPC_17_OFFSET                                                                  0x0000a3f0
+#define PHY_BB_TPC_17_ENABLE_PAL_MSB                                                                   0
+#define PHY_BB_TPC_17_ENABLE_PAL_LSB                                                                   0
+#define PHY_BB_TPC_17_ENABLE_PAL_MASK                                                         0x00000001
+#define PHY_BB_TPC_17_ENABLE_PAL_GET(x)                                        (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_17_ENABLE_PAL_SET(x)                                        (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB                                                               1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB                                                               1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK                                                     0x00000002
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x)                                    (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x)                                    (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB                                                           2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB                                                           2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK                                                 0x00000004
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x)                                (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x)                                (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB                                                           3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB                                                           3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK                                                 0x00000008
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x)                                (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x)                                (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB                                                          9
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB                                                          4
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK                                                0x000003f0
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x)                               (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x)                               (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB                                                            10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB                                                            10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK                                                   0x00000400
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x)                                 (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x)                                 (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB                                                 16
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB                                                 11
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK                                        0x0001f800
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x)                      (((x) & 0x0001f800) >> 11)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x)                      (((x) << 11) & 0x0001f800)
+
+/* macros for BB_tpc_18 */
+#define PHY_BB_TPC_18_ADDRESS                                                                 0x0000a3f4
+#define PHY_BB_TPC_18_OFFSET                                                                  0x0000a3f4
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB                                                              7
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB                                                              0
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK                                                    0x000000ff
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x)                                   (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x)                                   (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB                                                              15
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB                                                               8
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK                                                     0x0000ff00
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x)                                    (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x)                                    (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB                                                              16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB                                                              16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK                                                     0x00010000
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x)                                   (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x)                                   (((x) << 16) & 0x00010000)
+
+/* macros for BB_tpc_19 */
+#define PHY_BB_TPC_19_ADDRESS                                                                 0x0000a3f8
+#define PHY_BB_TPC_19_OFFSET                                                                  0x0000a3f8
+#define PHY_BB_TPC_19_ALPHA_THERM_MSB                                                                  7
+#define PHY_BB_TPC_19_ALPHA_THERM_LSB                                                                  0
+#define PHY_BB_TPC_19_ALPHA_THERM_MASK                                                        0x000000ff
+#define PHY_BB_TPC_19_ALPHA_THERM_GET(x)                                       (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_19_ALPHA_THERM_SET(x)                                       (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB                                                          15
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB                                                           8
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK                                                 0x0000ff00
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x)                                (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x)                                (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_19_ALPHA_VOLT_MSB                                                                  20
+#define PHY_BB_TPC_19_ALPHA_VOLT_LSB                                                                  16
+#define PHY_BB_TPC_19_ALPHA_VOLT_MASK                                                         0x001f0000
+#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x)                                       (((x) & 0x001f0000) >> 16)
+#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x)                                       (((x) << 16) & 0x001f0000)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB                                                           25
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB                                                           21
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK                                                  0x03e00000
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x)                                (((x) & 0x03e00000) >> 21)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x)                                (((x) << 21) & 0x03e00000)
+
+/* macros for BB_tpc_20 */
+#define PHY_BB_TPC_20_ADDRESS                                                                 0x0000a3fc
+#define PHY_BB_TPC_20_OFFSET                                                                  0x0000a3fc
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB                                                             0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB                                                             0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK                                                   0x00000001
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x)                                  (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x)                                  (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB                                                             1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB                                                             1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK                                                   0x00000002
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x)                                  (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x)                                  (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB                                                             2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB                                                             2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK                                                   0x00000004
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x)                                  (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x)                                  (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB                                                             3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB                                                             3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK                                                   0x00000008
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x)                                  (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x)                                  (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB                                                             4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB                                                             4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK                                                   0x00000010
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x)                                  (((x) & 0x00000010) >> 4)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x)                                  (((x) << 4) & 0x00000010)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB                                                             5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB                                                             5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK                                                   0x00000020
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x)                                  (((x) & 0x00000020) >> 5)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x)                                  (((x) << 5) & 0x00000020)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB                                                             6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB                                                             6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK                                                   0x00000040
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x)                                  (((x) & 0x00000040) >> 6)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x)                                  (((x) << 6) & 0x00000040)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB                                                             7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB                                                             7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK                                                   0x00000080
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x)                                  (((x) & 0x00000080) >> 7)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x)                                  (((x) << 7) & 0x00000080)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB                                                             8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB                                                             8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK                                                   0x00000100
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x)                                  (((x) & 0x00000100) >> 8)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x)                                  (((x) << 8) & 0x00000100)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB                                                             9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB                                                             9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK                                                   0x00000200
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x)                                  (((x) & 0x00000200) >> 9)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x)                                  (((x) << 9) & 0x00000200)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB                                                           10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB                                                           10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK                                                  0x00000400
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x)                                (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x)                                (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB                                                           11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB                                                           11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK                                                  0x00000800
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x)                                (((x) & 0x00000800) >> 11)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x)                                (((x) << 11) & 0x00000800)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB                                                           12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB                                                           12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK                                                  0x00001000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x)                                (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x)                                (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB                                                           13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB                                                           13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK                                                  0x00002000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x)                                (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x)                                (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB                                                           14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB                                                           14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK                                                  0x00004000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x)                                (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x)                                (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB                                                           15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB                                                           15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK                                                  0x00008000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB                                                           16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB                                                           16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK                                                  0x00010000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x)                                (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x)                                (((x) << 16) & 0x00010000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB                                                           17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB                                                           17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK                                                  0x00020000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x)                                (((x) & 0x00020000) >> 17)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x)                                (((x) << 17) & 0x00020000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB                                                           18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB                                                           18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK                                                  0x00040000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x)                                (((x) & 0x00040000) >> 18)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x)                                (((x) << 18) & 0x00040000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB                                                           19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB                                                           19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK                                                  0x00080000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x)                                (((x) & 0x00080000) >> 19)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x)                                (((x) << 19) & 0x00080000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB                                                           20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB                                                           20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK                                                  0x00100000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x)                                (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x)                                (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB                                                           21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB                                                           21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK                                                  0x00200000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x)                                (((x) & 0x00200000) >> 21)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x)                                (((x) << 21) & 0x00200000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB                                                           22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB                                                           22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK                                                  0x00400000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x)                                (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x)                                (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB                                                           23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB                                                           23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK                                                  0x00800000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x)                                (((x) & 0x00800000) >> 23)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x)                                (((x) << 23) & 0x00800000)
+
+/* macros for BB_tx_gain_tab_1 */
+#define PHY_BB_TX_GAIN_TAB_1_ADDRESS                                                          0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_OFFSET                                                           0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_2 */
+#define PHY_BB_TX_GAIN_TAB_2_ADDRESS                                                          0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_OFFSET                                                           0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_3 */
+#define PHY_BB_TX_GAIN_TAB_3_ADDRESS                                                          0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_OFFSET                                                           0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_4 */
+#define PHY_BB_TX_GAIN_TAB_4_ADDRESS                                                          0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_OFFSET                                                           0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_5 */
+#define PHY_BB_TX_GAIN_TAB_5_ADDRESS                                                          0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_OFFSET                                                           0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_6 */
+#define PHY_BB_TX_GAIN_TAB_6_ADDRESS                                                          0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_OFFSET                                                           0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_7 */
+#define PHY_BB_TX_GAIN_TAB_7_ADDRESS                                                          0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_OFFSET                                                           0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_8 */
+#define PHY_BB_TX_GAIN_TAB_8_ADDRESS                                                          0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_OFFSET                                                           0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_9 */
+#define PHY_BB_TX_GAIN_TAB_9_ADDRESS                                                          0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_OFFSET                                                           0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB                                                            31
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB                                                             0
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK                                                   0xffffffff
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x)                                  (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x)                                  (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_10 */
+#define PHY_BB_TX_GAIN_TAB_10_ADDRESS                                                         0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_OFFSET                                                          0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_11 */
+#define PHY_BB_TX_GAIN_TAB_11_ADDRESS                                                         0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_OFFSET                                                          0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_12 */
+#define PHY_BB_TX_GAIN_TAB_12_ADDRESS                                                         0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_OFFSET                                                          0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_13 */
+#define PHY_BB_TX_GAIN_TAB_13_ADDRESS                                                         0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_OFFSET                                                          0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_14 */
+#define PHY_BB_TX_GAIN_TAB_14_ADDRESS                                                         0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_OFFSET                                                          0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_15 */
+#define PHY_BB_TX_GAIN_TAB_15_ADDRESS                                                         0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_OFFSET                                                          0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_16 */
+#define PHY_BB_TX_GAIN_TAB_16_ADDRESS                                                         0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_OFFSET                                                          0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_17 */
+#define PHY_BB_TX_GAIN_TAB_17_ADDRESS                                                         0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_OFFSET                                                          0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_18 */
+#define PHY_BB_TX_GAIN_TAB_18_ADDRESS                                                         0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_OFFSET                                                          0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_19 */
+#define PHY_BB_TX_GAIN_TAB_19_ADDRESS                                                         0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_OFFSET                                                          0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_20 */
+#define PHY_BB_TX_GAIN_TAB_20_ADDRESS                                                         0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_OFFSET                                                          0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_21 */
+#define PHY_BB_TX_GAIN_TAB_21_ADDRESS                                                         0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_OFFSET                                                          0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_22 */
+#define PHY_BB_TX_GAIN_TAB_22_ADDRESS                                                         0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_OFFSET                                                          0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_23 */
+#define PHY_BB_TX_GAIN_TAB_23_ADDRESS                                                         0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_OFFSET                                                          0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_24 */
+#define PHY_BB_TX_GAIN_TAB_24_ADDRESS                                                         0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_OFFSET                                                          0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_25 */
+#define PHY_BB_TX_GAIN_TAB_25_ADDRESS                                                         0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_OFFSET                                                          0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_26 */
+#define PHY_BB_TX_GAIN_TAB_26_ADDRESS                                                         0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_OFFSET                                                          0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_27 */
+#define PHY_BB_TX_GAIN_TAB_27_ADDRESS                                                         0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_OFFSET                                                          0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_28 */
+#define PHY_BB_TX_GAIN_TAB_28_ADDRESS                                                         0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_OFFSET                                                          0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_29 */
+#define PHY_BB_TX_GAIN_TAB_29_ADDRESS                                                         0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_OFFSET                                                          0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_30 */
+#define PHY_BB_TX_GAIN_TAB_30_ADDRESS                                                         0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_OFFSET                                                          0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_31 */
+#define PHY_BB_TX_GAIN_TAB_31_ADDRESS                                                         0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_OFFSET                                                          0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_32 */
+#define PHY_BB_TX_GAIN_TAB_32_ADDRESS                                                         0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_OFFSET                                                          0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB                                                          31
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB                                                           0
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK                                                 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x)                                (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x)                                (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_1 */
+#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS                                                      0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET                                                       0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_2 */
+#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS                                                      0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET                                                       0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_3 */
+#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS                                                      0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET                                                       0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_4 */
+#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS                                                      0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET                                                       0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_5 */
+#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS                                                      0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET                                                       0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_6 */
+#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS                                                      0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET                                                       0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_7 */
+#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS                                                      0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET                                                       0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_8 */
+#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS                                                      0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET                                                       0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_9 */
+#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS                                                      0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET                                                       0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB                                                 31
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB                                                  0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK                                        0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x)                       (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x)                       (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_10 */
+#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS                                                     0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET                                                      0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_11 */
+#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS                                                     0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET                                                      0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_12 */
+#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS                                                     0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET                                                      0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_13 */
+#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS                                                     0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET                                                      0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_14 */
+#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS                                                     0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET                                                      0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_15 */
+#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS                                                     0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET                                                      0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_16 */
+#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS                                                     0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET                                                      0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_17 */
+#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS                                                     0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET                                                      0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_18 */
+#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS                                                     0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET                                                      0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_19 */
+#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS                                                     0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET                                                      0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_20 */
+#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS                                                     0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET                                                      0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_21 */
+#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS                                                     0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET                                                      0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_22 */
+#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS                                                     0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET                                                      0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_23 */
+#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS                                                     0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET                                                      0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_24 */
+#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS                                                     0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET                                                      0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_25 */
+#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS                                                     0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET                                                      0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_26 */
+#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS                                                     0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET                                                      0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_27 */
+#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS                                                     0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET                                                      0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_28 */
+#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS                                                     0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET                                                      0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_29 */
+#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS                                                     0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET                                                      0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_30 */
+#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS                                                     0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET                                                      0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_31 */
+#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS                                                     0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET                                                      0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_32 */
+#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS                                                     0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET                                                      0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB                                               31
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB                                                0
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK                                      0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x)                     (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x)                     (((x) << 0) & 0xffffffff)
+
+/* macros for BB_caltx_gain_set_0 */
+#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS                                                       0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_OFFSET                                                        0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_2 */
+#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS                                                       0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_OFFSET                                                        0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_4 */
+#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS                                                       0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_OFFSET                                                        0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_6 */
+#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS                                                       0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_OFFSET                                                        0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_8 */
+#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS                                                       0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_OFFSET                                                        0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB                                                  13
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB                                                   0
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK                                         0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x)                        (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x)                        (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB                                                  27
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB                                                  14
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK                                         0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x)                       (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x)                       (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_10 */
+#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS                                                      0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_OFFSET                                                       0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_12 */
+#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS                                                      0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_OFFSET                                                       0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_14 */
+#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS                                                      0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_OFFSET                                                       0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_16 */
+#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS                                                      0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_OFFSET                                                       0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_18 */
+#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS                                                      0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_OFFSET                                                       0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_20 */
+#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS                                                      0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_OFFSET                                                       0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_22 */
+#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS                                                      0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_OFFSET                                                       0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_24 */
+#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS                                                      0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_OFFSET                                                       0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_26 */
+#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS                                                      0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_OFFSET                                                       0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_28 */
+#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS                                                      0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_OFFSET                                                       0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_30 */
+#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS                                                      0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_OFFSET                                                       0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB                                                13
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB                                                 0
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK                                       0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x)                      (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x)                      (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB                                                27
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB                                                14
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK                                       0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x)                     (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x)                     (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiqcal_meas_b0 */
+#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS                                                        0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET                                                         0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB                                                 11
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB                                                  0
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK                                        0x00000fff
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x)                       (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB                                                 23
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB                                                 12
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK                                        0x00fff000
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x)                      (((x) & 0x00fff000) >> 12)
+
+/* macros for BB_txiqcal_start */
+#define PHY_BB_TXIQCAL_START_ADDRESS                                                          0x0000a6d8
+#define PHY_BB_TXIQCAL_START_OFFSET                                                           0x0000a6d8
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB                                                           0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB                                                           0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK                                                 0x00000001
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x)                                (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x)                                (((x) << 0) & 0x00000001)
+
+/* macros for BB_txiqcal_control_0 */
+#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS                                                      0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET                                                       0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB                                                  0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB                                                  0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK                                        0x00000001
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x)                       (((x) << 0) & 0x00000001)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB                                                   6
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB                                                   1
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK                                         0x0000007e
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x)                        (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x)                        (((x) << 1) & 0x0000007e)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB                                                 12
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB                                                  7
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK                                        0x00001f80
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x)                       (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x)                       (((x) << 7) & 0x00001f80)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB                                                 18
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB                                                 13
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK                                        0x0007e000
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x)                      (((x) & 0x0007e000) >> 13)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x)                      (((x) << 13) & 0x0007e000)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB                                                 22
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB                                                 19
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK                                        0x00780000
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x)                      (((x) & 0x00780000) >> 19)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x)                      (((x) << 19) & 0x00780000)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB                                                   29
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB                                                   23
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK                                          0x3f800000
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x)                        (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x)                        (((x) << 23) & 0x3f800000)
+
+/* macros for BB_txiqcal_control_1 */
+#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS                                                      0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET                                                       0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB                                                   5
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB                                                   0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK                                         0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x)                        (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x)                        (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB                                                   11
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB                                                    6
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK                                          0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x)                         (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x)                         (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB                                                   17
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB                                                   12
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK                                          0x0003f000
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x)                        (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x)                        (((x) << 12) & 0x0003f000)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB                                            24
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB                                            18
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK                                   0x01fc0000
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x)                 (((x) & 0x01fc0000) >> 18)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x)                 (((x) << 18) & 0x01fc0000)
+
+/* macros for BB_txiqcal_control_2 */
+#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS                                                      0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET                                                       0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB                                                 3
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB                                                 0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK                                       0x0000000f
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x)                      (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x)                      (((x) << 0) & 0x0000000f)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB                                                 8
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB                                                 4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK                                       0x000001f0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x)                      (((x) & 0x000001f0) >> 4)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x)                      (((x) << 4) & 0x000001f0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB                                                13
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB                                                 9
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK                                       0x00003e00
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x)                      (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x)                      (((x) << 9) & 0x00003e00)
+
+/* macros for BB_txiqcal_control_3 */
+#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS                                                      0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET                                                       0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB                                                       5
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB                                                       0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK                                             0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x)                            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x)                            (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB                                                       11
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB                                                        6
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK                                              0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x)                             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x)                             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB                                              21
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB                                              12
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK                                     0x003ff000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x)                   (((x) & 0x003ff000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x)                   (((x) << 12) & 0x003ff000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB                                                       23
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB                                                       22
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK                                              0x00c00000
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x)                            (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x)                            (((x) << 22) & 0x00c00000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB                                                      24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB                                                      24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK                                             0x01000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x)                           (((x) & 0x01000000) >> 24)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x)                           (((x) << 24) & 0x01000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB                                                      26
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB                                                      25
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK                                             0x06000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x)                           (((x) & 0x06000000) >> 25)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x)                           (((x) << 25) & 0x06000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB                                                   28
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB                                                   27
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK                                          0x18000000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x)                        (((x) & 0x18000000) >> 27)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x)                        (((x) << 27) & 0x18000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB                                                  30
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB                                                  29
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK                                         0x60000000
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x)                       (((x) & 0x60000000) >> 29)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x)                       (((x) << 29) & 0x60000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB                                                     31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB                                                     31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK                                            0x80000000
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x)                          (((x) & 0x80000000) >> 31)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x)                          (((x) << 31) & 0x80000000)
+
+/* macros for BB_txiq_corr_coeff_01_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS                                                  0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET                                                   0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_23_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS                                                  0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET                                                   0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_45_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS                                                  0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET                                                   0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_67_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS                                                  0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET                                                   0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_89_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS                                                  0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET                                                   0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ab_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS                                                  0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET                                                   0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_cd_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS                                                  0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET                                                   0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ef_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS                                                  0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET                                                   0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB                                          13
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB                                           0
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK                                 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x)                (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x)                (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB                                          27
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB                                          14
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK                                 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x)               (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x)               (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_cal_rxbb_gain_tbl_0 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS                                                    0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET                                                     0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB                                       17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB                                       12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK                              0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x)            (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x)            (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB                                       23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB                                       18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK                              0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x)            (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x)            (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_4 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS                                                    0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET                                                     0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB                                       17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB                                       12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK                              0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x)            (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x)            (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB                                       23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB                                       18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK                              0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x)            (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x)            (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_8 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS                                                    0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET                                                     0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB                                        5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB                                        0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK                              0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x)             (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x)             (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB                                       11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB                                        6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK                              0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x)             (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x)             (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB                                      17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB                                      12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK                             0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x)           (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x)           (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB                                      23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB                                      18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK                             0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x)           (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x)           (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_12 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS                                                   0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET                                                    0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_16 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS                                                   0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET                                                    0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_20 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS                                                   0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET                                                    0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x)           (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB                                     11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB                                      6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK                            0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x)           (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x)           (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB                                     17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB                                     12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK                            0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x)          (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x)          (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB                                     23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB                                     18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK                            0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x)          (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x)          (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_24 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS                                                   0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET                                                    0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB                                      5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB                                      0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK                            0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x)           (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x)           (((x) << 0) & 0x0000003f)
+
+/* macros for BB_txiqcal_status_b0 */
+#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS                                                      0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET                                                       0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB                                                  0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB                                                  0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK                                        0x00000001
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB                                                5
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB                                                1
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK                                      0x0000003e
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x)                     (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB                                                 11
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB                                                  6
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK                                        0x00000fc0
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x)                       (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB                                                   17
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB                                                   12
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK                                          0x0003f000
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x)                        (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB                                                 24
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB                                                 18
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK                                        0x01fc0000
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x)                      (((x) & 0x01fc0000) >> 18)
+
+/* macros for BB_paprd_trainer_cntl1 */
+#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS                                                    0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET                                                     0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB                                           0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB                                           0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK                                 0x00000001
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x)                (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x)                (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB                                          7
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB                                          1
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK                                0x000000fe
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x)               (((x) & 0x000000fe) >> 1)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x)               (((x) << 1) & 0x000000fe)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB                                          8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB                                          8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK                                0x00000100
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x)               (((x) & 0x00000100) >> 8)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x)               (((x) << 8) & 0x00000100)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB                                       9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB                                       9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK                             0x00000200
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x)            (((x) & 0x00000200) >> 9)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x)            (((x) << 9) & 0x00000200)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB                                         10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB                                         10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK                                0x00000400
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x)              (((x) & 0x00000400) >> 10)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x)              (((x) << 10) & 0x00000400)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB                                             11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB                                             11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK                                    0x00000800
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x)                  (((x) & 0x00000800) >> 11)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x)                  (((x) << 11) & 0x00000800)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB                                               18
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB                                               12
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK                                      0x0007f000
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x)                    (((x) & 0x0007f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x)                    (((x) << 12) & 0x0007f000)
+
+/* macros for BB_paprd_trainer_cntl2 */
+#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS                                                    0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET                                                     0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB                                       31
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB                                        0
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK                              0xffffffff
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x)             (((x) & 0xffffffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x)             (((x) << 0) & 0xffffffff)
+
+/* macros for BB_paprd_trainer_cntl3 */
+#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS                                                    0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET                                                     0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB                                       5
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB                                       0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK                             0x0000003f
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x)            (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x)            (((x) << 0) & 0x0000003f)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB                                            11
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB                                             6
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK                                   0x00000fc0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x)                  (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x)                  (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB                                      16
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB                                      12
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK                             0x0001f000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x)           (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x)           (((x) << 12) & 0x0001f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB                                       19
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB                                       17
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK                              0x000e0000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x)            (((x) & 0x000e0000) >> 17)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x)            (((x) << 17) & 0x000e0000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB                                       23
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB                                       20
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK                              0x00f00000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x)            (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x)            (((x) << 20) & 0x00f00000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB                                         27
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB                                         24
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK                                0x0f000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x)              (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x)              (((x) << 24) & 0x0f000000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB                                       28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB                                       28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK                              0x10000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x)            (((x) & 0x10000000) >> 28)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x)            (((x) << 28) & 0x10000000)
+
+/* macros for BB_paprd_trainer_cntl4 */
+#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS                                                    0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET                                                     0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB                                              11
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB                                               0
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK                                     0x00000fff
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x)                    (((x) & 0x00000fff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x)                    (((x) << 0) & 0x00000fff)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB                                          15
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB                                          12
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK                                 0x0000f000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x)               (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x)               (((x) << 12) & 0x0000f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB                                     25
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB                                     16
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK                            0x03ff0000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x)          (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x)          (((x) << 16) & 0x03ff0000)
+
+/* macros for BB_paprd_trainer_stat1 */
+#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS                                                    0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET                                                     0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB                                                0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB                                                0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK                                      0x00000001
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x)                     (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x)                     (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB                                          1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB                                          1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK                                0x00000002
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x)               (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB                                                  2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB                                                  2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK                                        0x00000004
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x)                       (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB                                              3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB                                              3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK                                    0x00000008
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x)                   (((x) & 0x00000008) >> 3)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB                                               8
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB                                               4
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK                                     0x000001f0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x)                    (((x) & 0x000001f0) >> 4)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB                                                 16
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB                                                  9
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK                                        0x0001fe00
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x)                       (((x) & 0x0001fe00) >> 9)
+
+/* macros for BB_paprd_trainer_stat2 */
+#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS                                                    0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET                                                     0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB                                                 15
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB                                                  0
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK                                        0x0000ffff
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x)                       (((x) & 0x0000ffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB                                               20
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB                                               16
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK                                      0x001f0000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x)                    (((x) & 0x001f0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB                                                 22
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB                                                 21
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK                                        0x00600000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x)                      (((x) & 0x00600000) >> 21)
+
+/* macros for BB_paprd_trainer_stat3 */
+#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS                                                    0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET                                                     0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB                                        19
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB                                         0
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK                               0x000fffff
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x)              (((x) & 0x000fffff) >> 0)
+
+/* macros for BB_fcal_1 */
+#define PHY_BB_FCAL_1_ADDRESS                                                                 0x0000a7d8
+#define PHY_BB_FCAL_1_OFFSET                                                                  0x0000a7d8
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB                                                                 9
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB                                                                 0
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK                                                       0x000003ff
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x)                                      (((x) & 0x000003ff) >> 0)
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x)                                      (((x) << 0) & 0x000003ff)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB                                                                19
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB                                                                10
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK                                                       0x000ffc00
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x)                                     (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x)                                     (((x) << 10) & 0x000ffc00)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB                                                                24
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB                                                                20
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK                                                       0x01f00000
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x)                                     (((x) & 0x01f00000) >> 20)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x)                                     (((x) << 20) & 0x01f00000)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB                                                                29
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB                                                                25
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK                                                       0x3e000000
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x)                                     (((x) & 0x3e000000) >> 25)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x)                                     (((x) << 25) & 0x3e000000)
+
+/* macros for BB_fcal_2_b0 */
+#define PHY_BB_FCAL_2_B0_ADDRESS                                                              0x0000a7dc
+#define PHY_BB_FCAL_2_B0_OFFSET                                                               0x0000a7dc
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB                                                            2
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB                                                            0
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK                                                  0x00000007
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x)                                 (((x) & 0x00000007) >> 0)
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x)                                 (((x) << 0) & 0x00000007)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB                                                          7
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB                                                          3
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK                                                0x000000f8
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x)                               (((x) & 0x000000f8) >> 3)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x)                               (((x) << 3) & 0x000000f8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB                                                            9
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB                                                            8
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK                                                  0x00000300
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x)                                 (((x) & 0x00000300) >> 8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x)                                 (((x) << 8) & 0x00000300)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB                                                            12
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB                                                            10
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK                                                   0x00001c00
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x)                                 (((x) & 0x00001c00) >> 10)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x)                                 (((x) << 10) & 0x00001c00)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB                                                            14
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB                                                            13
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK                                                   0x00006000
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x)                                 (((x) & 0x00006000) >> 13)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x)                                 (((x) << 13) & 0x00006000)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB                                                           15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB                                                           15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK                                                  0x00008000
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x)                                (((x) & 0x00008000) >> 15)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x)                                (((x) << 15) & 0x00008000)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB                                                             18
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB                                                             16
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK                                                    0x00070000
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x)                                  (((x) & 0x00070000) >> 16)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x)                                  (((x) << 16) & 0x00070000)
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB                                                     24
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB                                                     20
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK                                            0x01f00000
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x)                          (((x) & 0x01f00000) >> 20)
+
+/* macros for BB_radar_bw_filter */
+#define PHY_BB_RADAR_BW_FILTER_ADDRESS                                                        0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_OFFSET                                                         0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB                                                  0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB                                                  0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK                                        0x00000001
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x)                       (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x)                       (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB                                                    1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB                                                    1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK                                          0x00000002
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x)                         (((x) & 0x00000002) >> 1)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x)                         (((x) << 1) & 0x00000002)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB                                                    3
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB                                                    2
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK                                          0x0000000c
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x)                         (((x) & 0x0000000c) >> 2)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x)                         (((x) << 2) & 0x0000000c)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB                                               5
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB                                               4
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK                                     0x00000030
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x)                    (((x) & 0x00000030) >> 4)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x)                    (((x) << 4) & 0x00000030)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB                                             14
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB                                              8
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK                                    0x00007f00
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x)                   (((x) & 0x00007f00) >> 8)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x)                   (((x) << 8) & 0x00007f00)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB                                                  20
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB                                                  15
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK                                         0x001f8000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x)                       (((x) & 0x001f8000) >> 15)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x)                       (((x) << 15) & 0x001f8000)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB                                                   26
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB                                                   21
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK                                          0x07e00000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x)                        (((x) & 0x07e00000) >> 21)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x)                        (((x) << 21) & 0x07e00000)
+
+/* macros for BB_dft_tone_ctrl_b0 */
+#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS                                                       0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET                                                        0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB                                                      0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB                                                      0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK                                            0x00000001
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x)                           (((x) & 0x00000001) >> 0)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x)                           (((x) << 0) & 0x00000001)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB                                                 3
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB                                                 2
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK                                       0x0000000c
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x)                      (((x) & 0x0000000c) >> 2)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x)                      (((x) << 2) & 0x0000000c)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB                                               12
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB                                                4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK                                      0x00001ff0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x)                     (((x) & 0x00001ff0) >> 4)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x)                     (((x) << 4) & 0x00001ff0)
+
+/* macros for BB_therm_adc_1 */
+#define PHY_BB_THERM_ADC_1_ADDRESS                                                            0x0000a7e8
+#define PHY_BB_THERM_ADC_1_OFFSET                                                             0x0000a7e8
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB                                                      7
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB                                                      0
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK                                            0x000000ff
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x)                           (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB                                                      15
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB                                                       8
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK                                             0x0000ff00
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x)                            (((x) << 8) & 0x0000ff00)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB                                                       23
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB                                                       16
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK                                              0x00ff0000
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x)                            (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x)                            (((x) << 16) & 0x00ff0000)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB                                                     25
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB                                                     24
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK                                            0x03000000
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x)                          (((x) & 0x03000000) >> 24)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x)                          (((x) << 24) & 0x03000000)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB                               26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB                               26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK                      0x04000000
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x)    (((x) & 0x04000000) >> 26)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x)    (((x) << 26) & 0x04000000)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB                                  27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB                                  27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK                         0x08000000
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x)       (((x) & 0x08000000) >> 27)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x)       (((x) << 27) & 0x08000000)
+
+/* macros for BB_therm_adc_2 */
+#define PHY_BB_THERM_ADC_2_ADDRESS                                                            0x0000a7ec
+#define PHY_BB_THERM_ADC_2_OFFSET                                                             0x0000a7ec
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB                                                     11
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB                                                      0
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK                                            0x00000fff
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x)                           (((x) & 0x00000fff) >> 0)
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x)                           (((x) << 0) & 0x00000fff)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB                                                      21
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB                                                      12
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK                                             0x003ff000
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x)                           (((x) & 0x003ff000) >> 12)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x)                           (((x) << 12) & 0x003ff000)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB                                                       31
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB                                                       22
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK                                              0xffc00000
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x)                            (((x) & 0xffc00000) >> 22)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x)                            (((x) << 22) & 0xffc00000)
+
+/* macros for BB_therm_adc_3 */
+#define PHY_BB_THERM_ADC_3_ADDRESS                                                            0x0000a7f0
+#define PHY_BB_THERM_ADC_3_OFFSET                                                             0x0000a7f0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB                                                        7
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB                                                        0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK                                              0x000000ff
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x)                             (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x)                             (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB                                                  16
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB                                                   8
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK                                         0x0001ff00
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x)                        (((x) & 0x0001ff00) >> 8)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x)                        (((x) << 8) & 0x0001ff00)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB                                                           29
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB                                                           17
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK                                                  0x3ffe0000
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x)                                (((x) & 0x3ffe0000) >> 17)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x)                                (((x) << 17) & 0x3ffe0000)
+
+/* macros for BB_therm_adc_4 */
+#define PHY_BB_THERM_ADC_4_ADDRESS                                                            0x0000a7f4
+#define PHY_BB_THERM_ADC_4_OFFSET                                                             0x0000a7f4
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB                                                      7
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB                                                      0
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK                                            0x000000ff
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x)                           (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB                                                      15
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB                                                       8
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK                                             0x0000ff00
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x)                            (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB                                                       23
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB                                                       16
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK                                              0x00ff0000
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x)                            (((x) & 0x00ff0000) >> 16)
+
+/* macros for BB_tx_forced_gain */
+#define PHY_BB_TX_FORCED_GAIN_ADDRESS                                                         0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_OFFSET                                                          0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB                                                        0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB                                                        0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK                                              0x00000001
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x)                             (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x)                             (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB                                                   3
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB                                                   1
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK                                         0x0000000e
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x)                        (((x) & 0x0000000e) >> 1)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x)                        (((x) << 1) & 0x0000000e)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB                                                   5
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB                                                   4
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK                                         0x00000030
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x)                        (((x) & 0x00000030) >> 4)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x)                        (((x) << 4) & 0x00000030)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB                                                     9
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB                                                     6
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK                                           0x000003c0
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x)                          (((x) & 0x000003c0) >> 6)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x)                          (((x) << 6) & 0x000003c0)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB                                                     13
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB                                                     10
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK                                            0x00003c00
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x)                          (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x)                          (((x) << 10) & 0x00003c00)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB                                                     17
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB                                                     14
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK                                            0x0003c000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x)                          (((x) & 0x0003c000) >> 14)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x)                          (((x) << 14) & 0x0003c000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB                                                     21
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB                                                     18
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK                                            0x003c0000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x)                          (((x) & 0x003c0000) >> 18)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x)                          (((x) << 18) & 0x003c0000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB                                                     23
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB                                                     22
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK                                            0x00c00000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x)                          (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x)                          (((x) << 22) & 0x00c00000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB                                                   24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB                                                   24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK                                          0x01000000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x)                        (((x) & 0x01000000) >> 24)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x)                        (((x) << 24) & 0x01000000)
+
+/* macros for BB_eco_ctrl */
+#define PHY_BB_ECO_CTRL_ADDRESS                                                               0x0000a7fc
+#define PHY_BB_ECO_CTRL_OFFSET                                                                0x0000a7fc
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB                                                                   7
+#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB                                                                   0
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK                                                         0x000000ff
+#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x)                                        (((x) & 0x000000ff) >> 0)
+#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x)                                        (((x) << 0) & 0x000000ff)
+
+/* macros for BB_gain_force_max_gains_b1 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS                                                0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET                                                 0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB                                      13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB                                       7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK                             0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x)            (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x)            (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB                                      20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB                                      14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK                             0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x)           (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x)           (((x) << 14) & 0x001fc000)
+
+/* macros for BB_gains_min_offsets_b1 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS                                                   0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET                                                    0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB                                                   24
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB                                                   17
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK                                          0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x)                        (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x)                        (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB                                                25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK                                       0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x)                     (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x)                     (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB                                                26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK                                       0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x)                     (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x)                     (((x) << 26) & 0x04000000)
+
+/* macros for BB_rx_ocgain2 */
+#define PHY_BB_RX_OCGAIN2_ADDRESS                                                             0x0000aa00
+#define PHY_BB_RX_OCGAIN2_OFFSET                                                              0x0000aa00
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB                                                             31
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB                                                              0
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK                                                    0xffffffff
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x)                                   (((x) << 0) & 0xffffffff)
+
+/* macros for BB_ext_atten_switch_ctl_b1 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS                                                0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET                                                 0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB                                                5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB                                                0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK                                      0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x)                     (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x)                     (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB                                               11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB                                                6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK                                      0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x)                     (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x)                     (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB                                           16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB                                           12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK                                  0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x)                (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x)                (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB                                           21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB                                           17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK                                  0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x)                (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x)                (((x) << 17) & 0x003e0000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct bb_lc_reg_reg_s {
+  volatile char pad__0[0x9800];                                        /*        0x0 - 0x9800     */
+  volatile unsigned int BB_test_controls;                              /*     0x9800 - 0x9804     */
+  volatile unsigned int BB_gen_controls;                               /*     0x9804 - 0x9808     */
+  volatile unsigned int BB_test_controls_status;                       /*     0x9808 - 0x980c     */
+  volatile unsigned int BB_timing_controls_1;                          /*     0x980c - 0x9810     */
+  volatile unsigned int BB_timing_controls_2;                          /*     0x9810 - 0x9814     */
+  volatile unsigned int BB_timing_controls_3;                          /*     0x9814 - 0x9818     */
+  volatile unsigned int BB_D2_chip_id;                                 /*     0x9818 - 0x981c     */
+  volatile unsigned int BB_active;                                     /*     0x981c - 0x9820     */
+  volatile unsigned int BB_tx_timing_1;                                /*     0x9820 - 0x9824     */
+  volatile unsigned int BB_tx_timing_2;                                /*     0x9824 - 0x9828     */
+  volatile unsigned int BB_tx_timing_3;                                /*     0x9828 - 0x982c     */
+  volatile unsigned int BB_addac_parallel_control;                     /*     0x982c - 0x9830     */
+  volatile char pad__1[0x4];                                           /*     0x9830 - 0x9834     */
+  volatile unsigned int BB_xpa_timing_control;                         /*     0x9834 - 0x9838     */
+  volatile unsigned int BB_misc_pa_control;                            /*     0x9838 - 0x983c     */
+  volatile unsigned int BB_tstdac_constant;                            /*     0x983c - 0x9840     */
+  volatile unsigned int BB_find_signal_low;                            /*     0x9840 - 0x9844     */
+  volatile unsigned int BB_settling_time;                              /*     0x9844 - 0x9848     */
+  volatile unsigned int BB_gain_force_max_gains_b0;                    /*     0x9848 - 0x984c     */
+  volatile unsigned int BB_gains_min_offsets_b0;                       /*     0x984c - 0x9850     */
+  volatile unsigned int BB_desired_sigsize;                            /*     0x9850 - 0x9854     */
+  volatile unsigned int BB_timing_control_3a;                          /*     0x9854 - 0x9858     */
+  volatile unsigned int BB_find_signal;                                /*     0x9858 - 0x985c     */
+  volatile unsigned int BB_agc;                                        /*     0x985c - 0x9860     */
+  volatile unsigned int BB_agc_control;                                /*     0x9860 - 0x9864     */
+  volatile unsigned int BB_cca_b0;                                     /*     0x9864 - 0x9868     */
+  volatile unsigned int BB_sfcorr;                                     /*     0x9868 - 0x986c     */
+  volatile unsigned int BB_self_corr_low;                              /*     0x986c - 0x9870     */
+  volatile char pad__2[0x4];                                           /*     0x9870 - 0x9874     */
+  volatile unsigned int BB_synth_control;                              /*     0x9874 - 0x9878     */
+  volatile unsigned int BB_addac_clk_select;                           /*     0x9878 - 0x987c     */
+  volatile unsigned int BB_pll_cntl;                                   /*     0x987c - 0x9880     */
+  volatile char pad__3[0x80];                                          /*     0x9880 - 0x9900     */
+  volatile unsigned int BB_vit_spur_mask_A;                            /*     0x9900 - 0x9904     */
+  volatile unsigned int BB_vit_spur_mask_B;                            /*     0x9904 - 0x9908     */
+  volatile unsigned int BB_pilot_spur_mask;                            /*     0x9908 - 0x990c     */
+  volatile unsigned int BB_chan_spur_mask;                             /*     0x990c - 0x9910     */
+  volatile unsigned int BB_spectral_scan;                              /*     0x9910 - 0x9914     */
+  volatile unsigned int BB_analog_power_on_time;                       /*     0x9914 - 0x9918     */
+  volatile unsigned int BB_search_start_delay;                         /*     0x9918 - 0x991c     */
+  volatile unsigned int BB_max_rx_length;                              /*     0x991c - 0x9920     */
+  volatile unsigned int BB_timing_control_4;                           /*     0x9920 - 0x9924     */
+  volatile unsigned int BB_timing_control_5;                           /*     0x9924 - 0x9928     */
+  volatile unsigned int BB_phyonly_warm_reset;                         /*     0x9928 - 0x992c     */
+  volatile unsigned int BB_phyonly_control;                            /*     0x992c - 0x9930     */
+  volatile char pad__4[0x4];                                           /*     0x9930 - 0x9934     */
+  volatile unsigned int BB_powertx_rate1;                              /*     0x9934 - 0x9938     */
+  volatile unsigned int BB_powertx_rate2;                              /*     0x9938 - 0x993c     */
+  volatile unsigned int BB_powertx_max;                                /*     0x993c - 0x9940     */
+  volatile unsigned int BB_extension_radar;                            /*     0x9940 - 0x9944     */
+  volatile unsigned int BB_frame_control;                              /*     0x9944 - 0x9948     */
+  volatile unsigned int BB_timing_control_6;                           /*     0x9948 - 0x994c     */
+  volatile unsigned int BB_spur_mask_controls;                         /*     0x994c - 0x9950     */
+  volatile unsigned int BB_rx_iq_corr_b0;                              /*     0x9950 - 0x9954     */
+  volatile unsigned int BB_radar_detection;                            /*     0x9954 - 0x9958     */
+  volatile unsigned int BB_radar_detection_2;                          /*     0x9958 - 0x995c     */
+  volatile unsigned int BB_tx_phase_ramp_b0;                           /*     0x995c - 0x9960     */
+  volatile unsigned int BB_switch_table_chn_b0;                        /*     0x9960 - 0x9964     */
+  volatile unsigned int BB_switch_table_com1;                          /*     0x9964 - 0x9968     */
+  volatile unsigned int BB_cca_ctrl_2_b0;                              /*     0x9968 - 0x996c     */
+  volatile unsigned int BB_switch_table_com2;                          /*     0x996c - 0x9970     */
+  volatile unsigned int BB_restart;                                    /*     0x9970 - 0x9974     */
+  volatile char pad__5[0x4];                                           /*     0x9974 - 0x9978     */
+  volatile unsigned int BB_scrambler_seed;                             /*     0x9978 - 0x997c     */
+  volatile unsigned int BB_rfbus_request;                              /*     0x997c - 0x9980     */
+  volatile char pad__6[0x20];                                          /*     0x9980 - 0x99a0     */
+  volatile unsigned int BB_timing_control_11;                          /*     0x99a0 - 0x99a4     */
+  volatile unsigned int BB_multichain_enable;                          /*     0x99a4 - 0x99a8     */
+  volatile unsigned int BB_multichain_control;                         /*     0x99a8 - 0x99ac     */
+  volatile unsigned int BB_multichain_gain_ctrl;                       /*     0x99ac - 0x99b0     */
+  volatile char pad__7[0x4];                                           /*     0x99b0 - 0x99b4     */
+  volatile unsigned int BB_adc_gain_dc_corr_b0;                        /*     0x99b4 - 0x99b8     */
+  volatile unsigned int BB_ext_chan_pwr_thr_1;                         /*     0x99b8 - 0x99bc     */
+  volatile unsigned int BB_ext_chan_pwr_thr_2_b0;                      /*     0x99bc - 0x99c0     */
+  volatile unsigned int BB_ext_chan_scorr_thr;                         /*     0x99c0 - 0x99c4     */
+  volatile unsigned int BB_ext_chan_detect_win;                        /*     0x99c4 - 0x99c8     */
+  volatile unsigned int BB_pwr_thr_20_40_det;                          /*     0x99c8 - 0x99cc     */
+  volatile char pad__8[0x4];                                           /*     0x99cc - 0x99d0     */
+  volatile unsigned int BB_short_gi_delta_slope;                       /*     0x99d0 - 0x99d4     */
+  volatile char pad__9[0x8];                                           /*     0x99d4 - 0x99dc     */
+  volatile unsigned int BB_chaninfo_ctrl;                              /*     0x99dc - 0x99e0     */
+  volatile unsigned int BB_heavy_clip_ctrl;                            /*     0x99e0 - 0x99e4     */
+  volatile unsigned int BB_heavy_clip_20;                              /*     0x99e4 - 0x99e8     */
+  volatile unsigned int BB_heavy_clip_40;                              /*     0x99e8 - 0x99ec     */
+  volatile unsigned int BB_rifs_srch;                                  /*     0x99ec - 0x99f0     */
+  volatile unsigned int BB_iq_adc_cal_mode;                            /*     0x99f0 - 0x99f4     */
+  volatile char pad__10[0x8];                                          /*     0x99f4 - 0x99fc     */
+  volatile unsigned int BB_per_chain_csd;                              /*     0x99fc - 0x9a00     */
+  volatile unsigned int BB_rx_ocgain[128];                             /*     0x9a00 - 0x9c00     */
+  volatile unsigned int BB_tx_crc;                                     /*     0x9c00 - 0x9c04     */
+  volatile char pad__11[0xc];                                          /*     0x9c04 - 0x9c10     */
+  volatile unsigned int BB_iq_adc_meas_0_b0;                           /*     0x9c10 - 0x9c14     */
+  volatile unsigned int BB_iq_adc_meas_1_b0;                           /*     0x9c14 - 0x9c18     */
+  volatile unsigned int BB_iq_adc_meas_2_b0;                           /*     0x9c18 - 0x9c1c     */
+  volatile unsigned int BB_iq_adc_meas_3_b0;                           /*     0x9c1c - 0x9c20     */
+  volatile unsigned int BB_rfbus_grant;                                /*     0x9c20 - 0x9c24     */
+  volatile unsigned int BB_tstadc;                                     /*     0x9c24 - 0x9c28     */
+  volatile unsigned int BB_tstdac;                                     /*     0x9c28 - 0x9c2c     */
+  volatile char pad__12[0x4];                                          /*     0x9c2c - 0x9c30     */
+  volatile unsigned int BB_illegal_tx_rate;                            /*     0x9c30 - 0x9c34     */
+  volatile unsigned int BB_spur_report_b0;                             /*     0x9c34 - 0x9c38     */
+  volatile unsigned int BB_channel_status;                             /*     0x9c38 - 0x9c3c     */
+  volatile unsigned int BB_rssi_b0;                                    /*     0x9c3c - 0x9c40     */
+  volatile unsigned int BB_spur_est_cck_report_b0;                     /*     0x9c40 - 0x9c44     */
+  volatile char pad__13[0x68];                                         /*     0x9c44 - 0x9cac     */
+  volatile unsigned int BB_chan_info_noise_pwr;                        /*     0x9cac - 0x9cb0     */
+  volatile unsigned int BB_chan_info_gain_diff;                        /*     0x9cb0 - 0x9cb4     */
+  volatile unsigned int BB_chan_info_fine_timing;                      /*     0x9cb4 - 0x9cb8     */
+  volatile unsigned int BB_chan_info_gain_b0;                          /*     0x9cb8 - 0x9cbc     */
+  volatile unsigned int BB_chan_info_chan_tab_b0[60];                  /*     0x9cbc - 0x9dac     */
+  volatile char pad__14[0x38];                                         /*     0x9dac - 0x9de4     */
+  volatile unsigned int BB_paprd_am2am_mask;                           /*     0x9de4 - 0x9de8     */
+  volatile unsigned int BB_paprd_am2pm_mask;                           /*     0x9de8 - 0x9dec     */
+  volatile unsigned int BB_paprd_ht40_mask;                            /*     0x9dec - 0x9df0     */
+  volatile unsigned int BB_paprd_ctrl0;                                /*     0x9df0 - 0x9df4     */
+  volatile unsigned int BB_paprd_ctrl1;                                /*     0x9df4 - 0x9df8     */
+  volatile unsigned int BB_pa_gain123;                                 /*     0x9df8 - 0x9dfc     */
+  volatile unsigned int BB_pa_gain45;                                  /*     0x9dfc - 0x9e00     */
+  volatile unsigned int BB_paprd_pre_post_scale_0;                     /*     0x9e00 - 0x9e04     */
+  volatile unsigned int BB_paprd_pre_post_scale_1;                     /*     0x9e04 - 0x9e08     */
+  volatile unsigned int BB_paprd_pre_post_scale_2;                     /*     0x9e08 - 0x9e0c     */
+  volatile unsigned int BB_paprd_pre_post_scale_3;                     /*     0x9e0c - 0x9e10     */
+  volatile unsigned int BB_paprd_pre_post_scale_4;                     /*     0x9e10 - 0x9e14     */
+  volatile unsigned int BB_paprd_pre_post_scale_5;                     /*     0x9e14 - 0x9e18     */
+  volatile unsigned int BB_paprd_pre_post_scale_6;                     /*     0x9e18 - 0x9e1c     */
+  volatile unsigned int BB_paprd_pre_post_scale_7;                     /*     0x9e1c - 0x9e20     */
+  volatile unsigned int BB_paprd_mem_tab[120];                         /*     0x9e20 - 0xa000     */
+  volatile unsigned int BB_peak_det_ctrl_1;                            /*     0xa000 - 0xa004     */
+  volatile unsigned int BB_peak_det_ctrl_2;                            /*     0xa004 - 0xa008     */
+  volatile unsigned int BB_rx_gain_bounds_1;                           /*     0xa008 - 0xa00c     */
+  volatile unsigned int BB_rx_gain_bounds_2;                           /*     0xa00c - 0xa010     */
+  volatile unsigned int BB_peak_det_cal_ctrl;                          /*     0xa010 - 0xa014     */
+  volatile unsigned int BB_agc_dig_dc_ctrl;                            /*     0xa014 - 0xa018     */
+  volatile unsigned int BB_agc_dig_dc_status_i_b0;                     /*     0xa018 - 0xa01c     */
+  volatile unsigned int BB_agc_dig_dc_status_q_b0;                     /*     0xa01c - 0xa020     */
+  volatile char pad__15[0x1d4];                                        /*     0xa020 - 0xa1f4     */
+  volatile unsigned int BB_bbb_txfir_0;                                /*     0xa1f4 - 0xa1f8     */
+  volatile unsigned int BB_bbb_txfir_1;                                /*     0xa1f8 - 0xa1fc     */
+  volatile unsigned int BB_bbb_txfir_2;                                /*     0xa1fc - 0xa200     */
+  volatile unsigned int BB_modes_select;                               /*     0xa200 - 0xa204     */
+  volatile unsigned int BB_bbb_tx_ctrl;                                /*     0xa204 - 0xa208     */
+  volatile unsigned int BB_bbb_sig_detect;                             /*     0xa208 - 0xa20c     */
+  volatile unsigned int BB_ext_atten_switch_ctl_b0;                    /*     0xa20c - 0xa210     */
+  volatile unsigned int BB_bbb_rx_ctrl_1;                              /*     0xa210 - 0xa214     */
+  volatile unsigned int BB_bbb_rx_ctrl_2;                              /*     0xa214 - 0xa218     */
+  volatile unsigned int BB_bbb_rx_ctrl_3;                              /*     0xa218 - 0xa21c     */
+  volatile unsigned int BB_bbb_rx_ctrl_4;                              /*     0xa21c - 0xa220     */
+  volatile unsigned int BB_bbb_rx_ctrl_5;                              /*     0xa220 - 0xa224     */
+  volatile unsigned int BB_bbb_rx_ctrl_6;                              /*     0xa224 - 0xa228     */
+  volatile unsigned int BB_bbb_dagc_ctrl;                              /*     0xa228 - 0xa22c     */
+  volatile unsigned int BB_force_clken_cck;                            /*     0xa22c - 0xa230     */
+  volatile unsigned int BB_rx_clear_delay;                             /*     0xa230 - 0xa234     */
+  volatile unsigned int BB_powertx_rate3;                              /*     0xa234 - 0xa238     */
+  volatile unsigned int BB_powertx_rate4;                              /*     0xa238 - 0xa23c     */
+  volatile char pad__16[0x4];                                          /*     0xa23c - 0xa240     */
+  volatile unsigned int BB_cck_spur_mit;                               /*     0xa240 - 0xa244     */
+  volatile unsigned int BB_panic_watchdog_status;                      /*     0xa244 - 0xa248     */
+  volatile unsigned int BB_panic_watchdog_ctrl_1;                      /*     0xa248 - 0xa24c     */
+  volatile unsigned int BB_panic_watchdog_ctrl_2;                      /*     0xa24c - 0xa250     */
+  volatile unsigned int BB_iqcorr_ctrl_cck;                            /*     0xa250 - 0xa254     */
+  volatile unsigned int BB_bluetooth_cntl;                             /*     0xa254 - 0xa258     */
+  volatile unsigned int BB_tpc_1;                                      /*     0xa258 - 0xa25c     */
+  volatile unsigned int BB_tpc_2;                                      /*     0xa25c - 0xa260     */
+  volatile unsigned int BB_tpc_3;                                      /*     0xa260 - 0xa264     */
+  volatile unsigned int BB_tpc_4_b0;                                   /*     0xa264 - 0xa268     */
+  volatile unsigned int BB_analog_swap;                                /*     0xa268 - 0xa26c     */
+  volatile unsigned int BB_tpc_5_b0;                                   /*     0xa26c - 0xa270     */
+  volatile unsigned int BB_tpc_6_b0;                                   /*     0xa270 - 0xa274     */
+  volatile unsigned int BB_tpc_7;                                      /*     0xa274 - 0xa278     */
+  volatile unsigned int BB_tpc_8;                                      /*     0xa278 - 0xa27c     */
+  volatile unsigned int BB_tpc_9;                                      /*     0xa27c - 0xa280     */
+  volatile unsigned int BB_pdadc_tab_b0[32];                           /*     0xa280 - 0xa300     */
+  volatile unsigned int BB_cl_tab_b0[16];                              /*     0xa300 - 0xa340     */
+  volatile unsigned int BB_cl_map_0_b0;                                /*     0xa340 - 0xa344     */
+  volatile unsigned int BB_cl_map_1_b0;                                /*     0xa344 - 0xa348     */
+  volatile unsigned int BB_cl_map_2_b0;                                /*     0xa348 - 0xa34c     */
+  volatile unsigned int BB_cl_map_3_b0;                                /*     0xa34c - 0xa350     */
+  volatile char pad__17[0x8];                                          /*     0xa350 - 0xa358     */
+  volatile unsigned int BB_cl_cal_ctrl;                                /*     0xa358 - 0xa35c     */
+  volatile unsigned int BB_cl_map_pal_0_b0;                            /*     0xa35c - 0xa360     */
+  volatile unsigned int BB_cl_map_pal_1_b0;                            /*     0xa360 - 0xa364     */
+  volatile unsigned int BB_cl_map_pal_2_b0;                            /*     0xa364 - 0xa368     */
+  volatile unsigned int BB_cl_map_pal_3_b0;                            /*     0xa368 - 0xa36c     */
+  volatile char pad__18[0x1c];                                         /*     0xa36c - 0xa388     */
+  volatile unsigned int BB_rifs;                                       /*     0xa388 - 0xa38c     */
+  volatile unsigned int BB_powertx_rate5;                              /*     0xa38c - 0xa390     */
+  volatile unsigned int BB_powertx_rate6;                              /*     0xa390 - 0xa394     */
+  volatile unsigned int BB_tpc_10;                                     /*     0xa394 - 0xa398     */
+  volatile unsigned int BB_tpc_11_b0;                                  /*     0xa398 - 0xa39c     */
+  volatile unsigned int BB_cal_chain_mask;                             /*     0xa39c - 0xa3a0     */
+  volatile char pad__19[0x1c];                                         /*     0xa3a0 - 0xa3bc     */
+  volatile unsigned int BB_powertx_sub;                                /*     0xa3bc - 0xa3c0     */
+  volatile unsigned int BB_powertx_rate7;                              /*     0xa3c0 - 0xa3c4     */
+  volatile unsigned int BB_powertx_rate8;                              /*     0xa3c4 - 0xa3c8     */
+  volatile unsigned int BB_powertx_rate9;                              /*     0xa3c8 - 0xa3cc     */
+  volatile unsigned int BB_powertx_rate10;                             /*     0xa3cc - 0xa3d0     */
+  volatile unsigned int BB_powertx_rate11;                             /*     0xa3d0 - 0xa3d4     */
+  volatile unsigned int BB_powertx_rate12;                             /*     0xa3d4 - 0xa3d8     */
+  volatile unsigned int BB_force_analog;                               /*     0xa3d8 - 0xa3dc     */
+  volatile unsigned int BB_tpc_12;                                     /*     0xa3dc - 0xa3e0     */
+  volatile unsigned int BB_tpc_13;                                     /*     0xa3e0 - 0xa3e4     */
+  volatile unsigned int BB_tpc_14;                                     /*     0xa3e4 - 0xa3e8     */
+  volatile unsigned int BB_tpc_15;                                     /*     0xa3e8 - 0xa3ec     */
+  volatile unsigned int BB_tpc_16;                                     /*     0xa3ec - 0xa3f0     */
+  volatile unsigned int BB_tpc_17;                                     /*     0xa3f0 - 0xa3f4     */
+  volatile unsigned int BB_tpc_18;                                     /*     0xa3f4 - 0xa3f8     */
+  volatile unsigned int BB_tpc_19;                                     /*     0xa3f8 - 0xa3fc     */
+  volatile unsigned int BB_tpc_20;                                     /*     0xa3fc - 0xa400     */
+  volatile unsigned int BB_tx_gain_tab_1;                              /*     0xa400 - 0xa404     */
+  volatile unsigned int BB_tx_gain_tab_2;                              /*     0xa404 - 0xa408     */
+  volatile unsigned int BB_tx_gain_tab_3;                              /*     0xa408 - 0xa40c     */
+  volatile unsigned int BB_tx_gain_tab_4;                              /*     0xa40c - 0xa410     */
+  volatile unsigned int BB_tx_gain_tab_5;                              /*     0xa410 - 0xa414     */
+  volatile unsigned int BB_tx_gain_tab_6;                              /*     0xa414 - 0xa418     */
+  volatile unsigned int BB_tx_gain_tab_7;                              /*     0xa418 - 0xa41c     */
+  volatile unsigned int BB_tx_gain_tab_8;                              /*     0xa41c - 0xa420     */
+  volatile unsigned int BB_tx_gain_tab_9;                              /*     0xa420 - 0xa424     */
+  volatile unsigned int BB_tx_gain_tab_10;                             /*     0xa424 - 0xa428     */
+  volatile unsigned int BB_tx_gain_tab_11;                             /*     0xa428 - 0xa42c     */
+  volatile unsigned int BB_tx_gain_tab_12;                             /*     0xa42c - 0xa430     */
+  volatile unsigned int BB_tx_gain_tab_13;                             /*     0xa430 - 0xa434     */
+  volatile unsigned int BB_tx_gain_tab_14;                             /*     0xa434 - 0xa438     */
+  volatile unsigned int BB_tx_gain_tab_15;                             /*     0xa438 - 0xa43c     */
+  volatile unsigned int BB_tx_gain_tab_16;                             /*     0xa43c - 0xa440     */
+  volatile unsigned int BB_tx_gain_tab_17;                             /*     0xa440 - 0xa444     */
+  volatile unsigned int BB_tx_gain_tab_18;                             /*     0xa444 - 0xa448     */
+  volatile unsigned int BB_tx_gain_tab_19;                             /*     0xa448 - 0xa44c     */
+  volatile unsigned int BB_tx_gain_tab_20;                             /*     0xa44c - 0xa450     */
+  volatile unsigned int BB_tx_gain_tab_21;                             /*     0xa450 - 0xa454     */
+  volatile unsigned int BB_tx_gain_tab_22;                             /*     0xa454 - 0xa458     */
+  volatile unsigned int BB_tx_gain_tab_23;                             /*     0xa458 - 0xa45c     */
+  volatile unsigned int BB_tx_gain_tab_24;                             /*     0xa45c - 0xa460     */
+  volatile unsigned int BB_tx_gain_tab_25;                             /*     0xa460 - 0xa464     */
+  volatile unsigned int BB_tx_gain_tab_26;                             /*     0xa464 - 0xa468     */
+  volatile unsigned int BB_tx_gain_tab_27;                             /*     0xa468 - 0xa46c     */
+  volatile unsigned int BB_tx_gain_tab_28;                             /*     0xa46c - 0xa470     */
+  volatile unsigned int BB_tx_gain_tab_29;                             /*     0xa470 - 0xa474     */
+  volatile unsigned int BB_tx_gain_tab_30;                             /*     0xa474 - 0xa478     */
+  volatile unsigned int BB_tx_gain_tab_31;                             /*     0xa478 - 0xa47c     */
+  volatile unsigned int BB_tx_gain_tab_32;                             /*     0xa47c - 0xa480     */
+  volatile unsigned int BB_tx_gain_tab_pal_1;                          /*     0xa480 - 0xa484     */
+  volatile unsigned int BB_tx_gain_tab_pal_2;                          /*     0xa484 - 0xa488     */
+  volatile unsigned int BB_tx_gain_tab_pal_3;                          /*     0xa488 - 0xa48c     */
+  volatile unsigned int BB_tx_gain_tab_pal_4;                          /*     0xa48c - 0xa490     */
+  volatile unsigned int BB_tx_gain_tab_pal_5;                          /*     0xa490 - 0xa494     */
+  volatile unsigned int BB_tx_gain_tab_pal_6;                          /*     0xa494 - 0xa498     */
+  volatile unsigned int BB_tx_gain_tab_pal_7;                          /*     0xa498 - 0xa49c     */
+  volatile unsigned int BB_tx_gain_tab_pal_8;                          /*     0xa49c - 0xa4a0     */
+  volatile unsigned int BB_tx_gain_tab_pal_9;                          /*     0xa4a0 - 0xa4a4     */
+  volatile unsigned int BB_tx_gain_tab_pal_10;                         /*     0xa4a4 - 0xa4a8     */
+  volatile unsigned int BB_tx_gain_tab_pal_11;                         /*     0xa4a8 - 0xa4ac     */
+  volatile unsigned int BB_tx_gain_tab_pal_12;                         /*     0xa4ac - 0xa4b0     */
+  volatile unsigned int BB_tx_gain_tab_pal_13;                         /*     0xa4b0 - 0xa4b4     */
+  volatile unsigned int BB_tx_gain_tab_pal_14;                         /*     0xa4b4 - 0xa4b8     */
+  volatile unsigned int BB_tx_gain_tab_pal_15;                         /*     0xa4b8 - 0xa4bc     */
+  volatile unsigned int BB_tx_gain_tab_pal_16;                         /*     0xa4bc - 0xa4c0     */
+  volatile unsigned int BB_tx_gain_tab_pal_17;                         /*     0xa4c0 - 0xa4c4     */
+  volatile unsigned int BB_tx_gain_tab_pal_18;                         /*     0xa4c4 - 0xa4c8     */
+  volatile unsigned int BB_tx_gain_tab_pal_19;                         /*     0xa4c8 - 0xa4cc     */
+  volatile unsigned int BB_tx_gain_tab_pal_20;                         /*     0xa4cc - 0xa4d0     */
+  volatile unsigned int BB_tx_gain_tab_pal_21;                         /*     0xa4d0 - 0xa4d4     */
+  volatile unsigned int BB_tx_gain_tab_pal_22;                         /*     0xa4d4 - 0xa4d8     */
+  volatile unsigned int BB_tx_gain_tab_pal_23;                         /*     0xa4d8 - 0xa4dc     */
+  volatile unsigned int BB_tx_gain_tab_pal_24;                         /*     0xa4dc - 0xa4e0     */
+  volatile unsigned int BB_tx_gain_tab_pal_25;                         /*     0xa4e0 - 0xa4e4     */
+  volatile unsigned int BB_tx_gain_tab_pal_26;                         /*     0xa4e4 - 0xa4e8     */
+  volatile unsigned int BB_tx_gain_tab_pal_27;                         /*     0xa4e8 - 0xa4ec     */
+  volatile unsigned int BB_tx_gain_tab_pal_28;                         /*     0xa4ec - 0xa4f0     */
+  volatile unsigned int BB_tx_gain_tab_pal_29;                         /*     0xa4f0 - 0xa4f4     */
+  volatile unsigned int BB_tx_gain_tab_pal_30;                         /*     0xa4f4 - 0xa4f8     */
+  volatile unsigned int BB_tx_gain_tab_pal_31;                         /*     0xa4f8 - 0xa4fc     */
+  volatile unsigned int BB_tx_gain_tab_pal_32;                         /*     0xa4fc - 0xa500     */
+  volatile char pad__20[0x18];                                         /*     0xa500 - 0xa518     */
+  volatile unsigned int BB_caltx_gain_set_0;                           /*     0xa518 - 0xa51c     */
+  volatile unsigned int BB_caltx_gain_set_2;                           /*     0xa51c - 0xa520     */
+  volatile unsigned int BB_caltx_gain_set_4;                           /*     0xa520 - 0xa524     */
+  volatile unsigned int BB_caltx_gain_set_6;                           /*     0xa524 - 0xa528     */
+  volatile unsigned int BB_caltx_gain_set_8;                           /*     0xa528 - 0xa52c     */
+  volatile unsigned int BB_caltx_gain_set_10;                          /*     0xa52c - 0xa530     */
+  volatile unsigned int BB_caltx_gain_set_12;                          /*     0xa530 - 0xa534     */
+  volatile unsigned int BB_caltx_gain_set_14;                          /*     0xa534 - 0xa538     */
+  volatile unsigned int BB_caltx_gain_set_16;                          /*     0xa538 - 0xa53c     */
+  volatile unsigned int BB_caltx_gain_set_18;                          /*     0xa53c - 0xa540     */
+  volatile unsigned int BB_caltx_gain_set_20;                          /*     0xa540 - 0xa544     */
+  volatile unsigned int BB_caltx_gain_set_22;                          /*     0xa544 - 0xa548     */
+  volatile unsigned int BB_caltx_gain_set_24;                          /*     0xa548 - 0xa54c     */
+  volatile unsigned int BB_caltx_gain_set_26;                          /*     0xa54c - 0xa550     */
+  volatile unsigned int BB_caltx_gain_set_28;                          /*     0xa550 - 0xa554     */
+  volatile unsigned int BB_caltx_gain_set_30;                          /*     0xa554 - 0xa558     */
+  volatile unsigned int BB_txiqcal_meas_b0[96];                        /*     0xa558 - 0xa6d8     */
+  volatile unsigned int BB_txiqcal_start;                              /*     0xa6d8 - 0xa6dc     */
+  volatile unsigned int BB_txiqcal_control_0;                          /*     0xa6dc - 0xa6e0     */
+  volatile unsigned int BB_txiqcal_control_1;                          /*     0xa6e0 - 0xa6e4     */
+  volatile unsigned int BB_txiqcal_control_2;                          /*     0xa6e4 - 0xa6e8     */
+  volatile unsigned int BB_txiqcal_control_3;                          /*     0xa6e8 - 0xa6ec     */
+  volatile unsigned int BB_txiq_corr_coeff_01_b0;                      /*     0xa6ec - 0xa6f0     */
+  volatile unsigned int BB_txiq_corr_coeff_23_b0;                      /*     0xa6f0 - 0xa6f4     */
+  volatile unsigned int BB_txiq_corr_coeff_45_b0;                      /*     0xa6f4 - 0xa6f8     */
+  volatile unsigned int BB_txiq_corr_coeff_67_b0;                      /*     0xa6f8 - 0xa6fc     */
+  volatile unsigned int BB_txiq_corr_coeff_89_b0;                      /*     0xa6fc - 0xa700     */
+  volatile unsigned int BB_txiq_corr_coeff_ab_b0;                      /*     0xa700 - 0xa704     */
+  volatile unsigned int BB_txiq_corr_coeff_cd_b0;                      /*     0xa704 - 0xa708     */
+  volatile unsigned int BB_txiq_corr_coeff_ef_b0;                      /*     0xa708 - 0xa70c     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_0;                        /*     0xa70c - 0xa710     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_4;                        /*     0xa710 - 0xa714     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_8;                        /*     0xa714 - 0xa718     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_12;                       /*     0xa718 - 0xa71c     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_16;                       /*     0xa71c - 0xa720     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_20;                       /*     0xa720 - 0xa724     */
+  volatile unsigned int BB_cal_rxbb_gain_tbl_24;                       /*     0xa724 - 0xa728     */
+  volatile unsigned int BB_txiqcal_status_b0;                          /*     0xa728 - 0xa72c     */
+  volatile unsigned int BB_paprd_trainer_cntl1;                        /*     0xa72c - 0xa730     */
+  volatile unsigned int BB_paprd_trainer_cntl2;                        /*     0xa730 - 0xa734     */
+  volatile unsigned int BB_paprd_trainer_cntl3;                        /*     0xa734 - 0xa738     */
+  volatile unsigned int BB_paprd_trainer_cntl4;                        /*     0xa738 - 0xa73c     */
+  volatile unsigned int BB_paprd_trainer_stat1;                        /*     0xa73c - 0xa740     */
+  volatile unsigned int BB_paprd_trainer_stat2;                        /*     0xa740 - 0xa744     */
+  volatile unsigned int BB_paprd_trainer_stat3;                        /*     0xa744 - 0xa748     */
+  volatile char pad__21[0x90];                                         /*     0xa748 - 0xa7d8     */
+  volatile unsigned int BB_fcal_1;                                     /*     0xa7d8 - 0xa7dc     */
+  volatile unsigned int BB_fcal_2_b0;                                  /*     0xa7dc - 0xa7e0     */
+  volatile unsigned int BB_radar_bw_filter;                            /*     0xa7e0 - 0xa7e4     */
+  volatile unsigned int BB_dft_tone_ctrl_b0;                           /*     0xa7e4 - 0xa7e8     */
+  volatile unsigned int BB_therm_adc_1;                                /*     0xa7e8 - 0xa7ec     */
+  volatile unsigned int BB_therm_adc_2;                                /*     0xa7ec - 0xa7f0     */
+  volatile unsigned int BB_therm_adc_3;                                /*     0xa7f0 - 0xa7f4     */
+  volatile unsigned int BB_therm_adc_4;                                /*     0xa7f4 - 0xa7f8     */
+  volatile unsigned int BB_tx_forced_gain;                             /*     0xa7f8 - 0xa7fc     */
+  volatile unsigned int BB_eco_ctrl;                                   /*     0xa7fc - 0xa800     */
+  volatile char pad__22[0x48];                                         /*     0xa800 - 0xa848     */
+  volatile unsigned int BB_gain_force_max_gains_b1;                    /*     0xa848 - 0xa84c     */
+  volatile unsigned int BB_gains_min_offsets_b1;                       /*     0xa84c - 0xa850     */
+  volatile char pad__23[0x1b0];                                        /*     0xa850 - 0xaa00     */
+  volatile unsigned int BB_rx_ocgain2[128];                            /*     0xaa00 - 0xac00     */
+  volatile char pad__24[0x60c];                                        /*     0xac00 - 0xb20c     */
+  volatile unsigned int BB_ext_atten_switch_ctl_b1;                    /*     0xb20c - 0xb210     */
+} bb_lc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _BB_LC_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h
new file mode 100644
index 000000000000..4905152f0c0a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h
@@ -0,0 +1,104 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _EFUSE_REG_REG_H_
+#define _EFUSE_REG_REG_H_
+
+#define EFUSE_WR_ENABLE_REG_ADDRESS              0x00000000
+#define EFUSE_WR_ENABLE_REG_OFFSET               0x00000000
+#define EFUSE_WR_ENABLE_REG_V_MSB                0
+#define EFUSE_WR_ENABLE_REG_V_LSB                0
+#define EFUSE_WR_ENABLE_REG_V_MASK               0x00000001
+#define EFUSE_WR_ENABLE_REG_V_GET(x)             (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
+#define EFUSE_WR_ENABLE_REG_V_SET(x)             (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_ENABLE_REG_ADDRESS             0x00000004
+#define EFUSE_INT_ENABLE_REG_OFFSET              0x00000004
+#define EFUSE_INT_ENABLE_REG_V_MSB               0
+#define EFUSE_INT_ENABLE_REG_V_LSB               0
+#define EFUSE_INT_ENABLE_REG_V_MASK              0x00000001
+#define EFUSE_INT_ENABLE_REG_V_GET(x)            (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
+#define EFUSE_INT_ENABLE_REG_V_SET(x)            (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_STATUS_REG_ADDRESS             0x00000008
+#define EFUSE_INT_STATUS_REG_OFFSET              0x00000008
+#define EFUSE_INT_STATUS_REG_V_MSB               0
+#define EFUSE_INT_STATUS_REG_V_LSB               0
+#define EFUSE_INT_STATUS_REG_V_MASK              0x00000001
+#define EFUSE_INT_STATUS_REG_V_GET(x)            (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
+#define EFUSE_INT_STATUS_REG_V_SET(x)            (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
+
+#define BITMASK_WR_REG_ADDRESS                   0x0000000c
+#define BITMASK_WR_REG_OFFSET                    0x0000000c
+#define BITMASK_WR_REG_V_MSB                     31
+#define BITMASK_WR_REG_V_LSB                     0
+#define BITMASK_WR_REG_V_MASK                    0xffffffff
+#define BITMASK_WR_REG_V_GET(x)                  (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
+#define BITMASK_WR_REG_V_SET(x)                  (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
+
+#define VDDQ_SETTLE_TIME_REG_ADDRESS             0x00000010
+#define VDDQ_SETTLE_TIME_REG_OFFSET              0x00000010
+#define VDDQ_SETTLE_TIME_REG_V_MSB               31
+#define VDDQ_SETTLE_TIME_REG_V_LSB               0
+#define VDDQ_SETTLE_TIME_REG_V_MASK              0xffffffff
+#define VDDQ_SETTLE_TIME_REG_V_GET(x)            (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
+#define VDDQ_SETTLE_TIME_REG_V_SET(x)            (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
+
+#define RD_STROBE_PW_REG_ADDRESS                 0x00000014
+#define RD_STROBE_PW_REG_OFFSET                  0x00000014
+#define RD_STROBE_PW_REG_V_MSB                   31
+#define RD_STROBE_PW_REG_V_LSB                   0
+#define RD_STROBE_PW_REG_V_MASK                  0xffffffff
+#define RD_STROBE_PW_REG_V_GET(x)                (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
+#define RD_STROBE_PW_REG_V_SET(x)                (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
+
+#define PG_STROBE_PW_REG_ADDRESS                 0x00000018
+#define PG_STROBE_PW_REG_OFFSET                  0x00000018
+#define PG_STROBE_PW_REG_V_MSB                   31
+#define PG_STROBE_PW_REG_V_LSB                   0
+#define PG_STROBE_PW_REG_V_MASK                  0xffffffff
+#define PG_STROBE_PW_REG_V_GET(x)                (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
+#define PG_STROBE_PW_REG_V_SET(x)                (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
+
+#define EFUSE_INTF_ADDRESS                       0x00000800
+#define EFUSE_INTF_OFFSET                        0x00000800
+#define EFUSE_INTF_R_MSB                         31
+#define EFUSE_INTF_R_LSB                         0
+#define EFUSE_INTF_R_MASK                        0xffffffff
+#define EFUSE_INTF_R_GET(x)                      (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
+#define EFUSE_INTF_R_SET(x)                      (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct efuse_reg_reg_s {
+  volatile unsigned int efuse_wr_enable_reg;
+  volatile unsigned int efuse_int_enable_reg;
+  volatile unsigned int efuse_int_status_reg;
+  volatile unsigned int bitmask_wr_reg;
+  volatile unsigned int vddq_settle_time_reg;
+  volatile unsigned int rd_strobe_pw_reg;
+  volatile unsigned int pg_strobe_pw_reg;
+  unsigned char pad0[2020]; /* pad to 0x800 */
+  volatile unsigned int efuse_intf[512];
+} efuse_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _EFUSE_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
new file mode 100644
index 000000000000..60ea43b7806e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
@@ -0,0 +1,1249 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_ATHR_WLAN_REG_REG_H_
+#define _GPIO_ATHR_WLAN_REG_REG_H_
+
+#define WLAN_GPIO_OUT_ADDRESS                    0x00000000
+#define WLAN_GPIO_OUT_OFFSET                     0x00000000
+#define WLAN_GPIO_OUT_DATA_MSB                   25
+#define WLAN_GPIO_OUT_DATA_LSB                   0
+#define WLAN_GPIO_OUT_DATA_MASK                  0x03ffffff
+#define WLAN_GPIO_OUT_DATA_GET(x)                (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB)
+#define WLAN_GPIO_OUT_DATA_SET(x)                (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TS_ADDRESS               0x00000004
+#define WLAN_GPIO_OUT_W1TS_OFFSET                0x00000004
+#define WLAN_GPIO_OUT_W1TS_DATA_MSB              25
+#define WLAN_GPIO_OUT_W1TS_DATA_LSB              0
+#define WLAN_GPIO_OUT_W1TS_DATA_MASK             0x03ffffff
+#define WLAN_GPIO_OUT_W1TS_DATA_GET(x)           (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TS_DATA_SET(x)           (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TC_ADDRESS               0x00000008
+#define WLAN_GPIO_OUT_W1TC_OFFSET                0x00000008
+#define WLAN_GPIO_OUT_W1TC_DATA_MSB              25
+#define WLAN_GPIO_OUT_W1TC_DATA_LSB              0
+#define WLAN_GPIO_OUT_W1TC_DATA_MASK             0x03ffffff
+#define WLAN_GPIO_OUT_W1TC_DATA_GET(x)           (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TC_DATA_SET(x)           (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_ADDRESS                 0x0000000c
+#define WLAN_GPIO_ENABLE_OFFSET                  0x0000000c
+#define WLAN_GPIO_ENABLE_DATA_MSB                25
+#define WLAN_GPIO_ENABLE_DATA_LSB                0
+#define WLAN_GPIO_ENABLE_DATA_MASK               0x03ffffff
+#define WLAN_GPIO_ENABLE_DATA_GET(x)             (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB)
+#define WLAN_GPIO_ENABLE_DATA_SET(x)             (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TS_ADDRESS            0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_OFFSET             0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB           25
+#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB           0
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK          0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)        (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)        (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TC_ADDRESS            0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_OFFSET             0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB           25
+#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB           0
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK          0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)        (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)        (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_IN_ADDRESS                     0x00000018
+#define WLAN_GPIO_IN_OFFSET                      0x00000018
+#define WLAN_GPIO_IN_DATA_MSB                    25
+#define WLAN_GPIO_IN_DATA_LSB                    0
+#define WLAN_GPIO_IN_DATA_MASK                   0x03ffffff
+#define WLAN_GPIO_IN_DATA_GET(x)                 (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB)
+#define WLAN_GPIO_IN_DATA_SET(x)                 (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK)
+
+#define WLAN_GPIO_STATUS_ADDRESS                 0x0000001c
+#define WLAN_GPIO_STATUS_OFFSET                  0x0000001c
+#define WLAN_GPIO_STATUS_INTERRUPT_MSB           25
+#define WLAN_GPIO_STATUS_INTERRUPT_LSB           0
+#define WLAN_GPIO_STATUS_INTERRUPT_MASK          0x03ffffff
+#define WLAN_GPIO_STATUS_INTERRUPT_GET(x)        (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_INTERRUPT_SET(x)        (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TS_ADDRESS            0x00000020
+#define WLAN_GPIO_STATUS_W1TS_OFFSET             0x00000020
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB      25
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB      0
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK     0x03ffffff
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)   (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)   (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TC_ADDRESS            0x00000024
+#define WLAN_GPIO_STATUS_W1TC_OFFSET             0x00000024
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB      25
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB      0
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK     0x03ffffff
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)   (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)   (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define WLAN_GPIO_PIN0_ADDRESS                   0x00000028
+#define WLAN_GPIO_PIN0_OFFSET                    0x00000028
+#define WLAN_GPIO_PIN0_CONFIG_MSB                13
+#define WLAN_GPIO_PIN0_CONFIG_LSB                11
+#define WLAN_GPIO_PIN0_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN0_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB)
+#define WLAN_GPIO_PIN0_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN0_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN0_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN0_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN0_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN0_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN0_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN0_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN0_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN0_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN0_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN0_SOURCE_MSB                0
+#define WLAN_GPIO_PIN0_SOURCE_LSB                0
+#define WLAN_GPIO_PIN0_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN0_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB)
+#define WLAN_GPIO_PIN0_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN1_ADDRESS                   0x0000002c
+#define WLAN_GPIO_PIN1_OFFSET                    0x0000002c
+#define WLAN_GPIO_PIN1_CONFIG_MSB                13
+#define WLAN_GPIO_PIN1_CONFIG_LSB                11
+#define WLAN_GPIO_PIN1_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN1_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB)
+#define WLAN_GPIO_PIN1_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN1_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN1_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN1_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN1_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN1_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN1_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN1_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN1_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN1_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN1_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN1_SOURCE_MSB                0
+#define WLAN_GPIO_PIN1_SOURCE_LSB                0
+#define WLAN_GPIO_PIN1_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN1_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB)
+#define WLAN_GPIO_PIN1_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN2_ADDRESS                   0x00000030
+#define WLAN_GPIO_PIN2_OFFSET                    0x00000030
+#define WLAN_GPIO_PIN2_CONFIG_MSB                13
+#define WLAN_GPIO_PIN2_CONFIG_LSB                11
+#define WLAN_GPIO_PIN2_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN2_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB)
+#define WLAN_GPIO_PIN2_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN2_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN2_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN2_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN2_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN2_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN2_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN2_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN2_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN2_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN2_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN2_SOURCE_MSB                0
+#define WLAN_GPIO_PIN2_SOURCE_LSB                0
+#define WLAN_GPIO_PIN2_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN2_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB)
+#define WLAN_GPIO_PIN2_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN3_ADDRESS                   0x00000034
+#define WLAN_GPIO_PIN3_OFFSET                    0x00000034
+#define WLAN_GPIO_PIN3_CONFIG_MSB                13
+#define WLAN_GPIO_PIN3_CONFIG_LSB                11
+#define WLAN_GPIO_PIN3_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN3_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB)
+#define WLAN_GPIO_PIN3_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN3_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN3_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN3_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN3_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN3_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN3_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN3_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN3_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN3_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN3_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN3_SOURCE_MSB                0
+#define WLAN_GPIO_PIN3_SOURCE_LSB                0
+#define WLAN_GPIO_PIN3_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN3_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB)
+#define WLAN_GPIO_PIN3_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN4_ADDRESS                   0x00000038
+#define WLAN_GPIO_PIN4_OFFSET                    0x00000038
+#define WLAN_GPIO_PIN4_CONFIG_MSB                13
+#define WLAN_GPIO_PIN4_CONFIG_LSB                11
+#define WLAN_GPIO_PIN4_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN4_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB)
+#define WLAN_GPIO_PIN4_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN4_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN4_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN4_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN4_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN4_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN4_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN4_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN4_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN4_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN4_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN4_SOURCE_MSB                0
+#define WLAN_GPIO_PIN4_SOURCE_LSB                0
+#define WLAN_GPIO_PIN4_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN4_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB)
+#define WLAN_GPIO_PIN4_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN5_ADDRESS                   0x0000003c
+#define WLAN_GPIO_PIN5_OFFSET                    0x0000003c
+#define WLAN_GPIO_PIN5_CONFIG_MSB                13
+#define WLAN_GPIO_PIN5_CONFIG_LSB                11
+#define WLAN_GPIO_PIN5_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN5_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB)
+#define WLAN_GPIO_PIN5_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN5_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN5_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN5_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN5_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN5_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN5_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN5_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN5_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN5_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN5_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN5_SOURCE_MSB                0
+#define WLAN_GPIO_PIN5_SOURCE_LSB                0
+#define WLAN_GPIO_PIN5_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN5_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB)
+#define WLAN_GPIO_PIN5_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN6_ADDRESS                   0x00000040
+#define WLAN_GPIO_PIN6_OFFSET                    0x00000040
+#define WLAN_GPIO_PIN6_CONFIG_MSB                13
+#define WLAN_GPIO_PIN6_CONFIG_LSB                11
+#define WLAN_GPIO_PIN6_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN6_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB)
+#define WLAN_GPIO_PIN6_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN6_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN6_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN6_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN6_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN6_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN6_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN6_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN6_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN6_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN6_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN6_SOURCE_MSB                0
+#define WLAN_GPIO_PIN6_SOURCE_LSB                0
+#define WLAN_GPIO_PIN6_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN6_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB)
+#define WLAN_GPIO_PIN6_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN7_ADDRESS                   0x00000044
+#define WLAN_GPIO_PIN7_OFFSET                    0x00000044
+#define WLAN_GPIO_PIN7_CONFIG_MSB                13
+#define WLAN_GPIO_PIN7_CONFIG_LSB                11
+#define WLAN_GPIO_PIN7_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN7_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB)
+#define WLAN_GPIO_PIN7_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN7_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN7_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN7_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN7_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN7_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN7_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN7_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN7_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN7_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN7_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN7_SOURCE_MSB                0
+#define WLAN_GPIO_PIN7_SOURCE_LSB                0
+#define WLAN_GPIO_PIN7_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN7_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB)
+#define WLAN_GPIO_PIN7_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN8_ADDRESS                   0x00000048
+#define WLAN_GPIO_PIN8_OFFSET                    0x00000048
+#define WLAN_GPIO_PIN8_CONFIG_MSB                13
+#define WLAN_GPIO_PIN8_CONFIG_LSB                11
+#define WLAN_GPIO_PIN8_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN8_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB)
+#define WLAN_GPIO_PIN8_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN8_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN8_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN8_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN8_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN8_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN8_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN8_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN8_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN8_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN8_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN8_SOURCE_MSB                0
+#define WLAN_GPIO_PIN8_SOURCE_LSB                0
+#define WLAN_GPIO_PIN8_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN8_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB)
+#define WLAN_GPIO_PIN8_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN9_ADDRESS                   0x0000004c
+#define WLAN_GPIO_PIN9_OFFSET                    0x0000004c
+#define WLAN_GPIO_PIN9_CONFIG_MSB                13
+#define WLAN_GPIO_PIN9_CONFIG_LSB                11
+#define WLAN_GPIO_PIN9_CONFIG_MASK               0x00003800
+#define WLAN_GPIO_PIN9_CONFIG_GET(x)             (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB)
+#define WLAN_GPIO_PIN9_CONFIG_SET(x)             (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB         10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB         10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK        0x00000400
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)      (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)      (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN9_INT_TYPE_MSB              9
+#define WLAN_GPIO_PIN9_INT_TYPE_LSB              7
+#define WLAN_GPIO_PIN9_INT_TYPE_MASK             0x00000380
+#define WLAN_GPIO_PIN9_INT_TYPE_GET(x)           (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN9_INT_TYPE_SET(x)           (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN9_PAD_PULL_MSB              6
+#define WLAN_GPIO_PIN9_PAD_PULL_LSB              5
+#define WLAN_GPIO_PIN9_PAD_PULL_MASK             0x00000060
+#define WLAN_GPIO_PIN9_PAD_PULL_GET(x)           (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN9_PAD_PULL_SET(x)           (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB          4
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB          3
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK         0x00000018
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)       (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)       (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB            2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB            2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK           0x00000004
+#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)         (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)         (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN9_SOURCE_MSB                0
+#define WLAN_GPIO_PIN9_SOURCE_LSB                0
+#define WLAN_GPIO_PIN9_SOURCE_MASK               0x00000001
+#define WLAN_GPIO_PIN9_SOURCE_GET(x)             (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB)
+#define WLAN_GPIO_PIN9_SOURCE_SET(x)             (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN10_ADDRESS                  0x00000050
+#define WLAN_GPIO_PIN10_OFFSET                   0x00000050
+#define WLAN_GPIO_PIN10_CONFIG_MSB               13
+#define WLAN_GPIO_PIN10_CONFIG_LSB               11
+#define WLAN_GPIO_PIN10_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN10_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB)
+#define WLAN_GPIO_PIN10_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN10_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN10_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN10_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN10_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN10_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN10_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN10_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN10_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN10_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN10_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN10_SOURCE_MSB               0
+#define WLAN_GPIO_PIN10_SOURCE_LSB               0
+#define WLAN_GPIO_PIN10_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN10_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB)
+#define WLAN_GPIO_PIN10_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN11_ADDRESS                  0x00000054
+#define WLAN_GPIO_PIN11_OFFSET                   0x00000054
+#define WLAN_GPIO_PIN11_CONFIG_MSB               13
+#define WLAN_GPIO_PIN11_CONFIG_LSB               11
+#define WLAN_GPIO_PIN11_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN11_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB)
+#define WLAN_GPIO_PIN11_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN11_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN11_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN11_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN11_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN11_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN11_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN11_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN11_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN11_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN11_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN11_SOURCE_MSB               0
+#define WLAN_GPIO_PIN11_SOURCE_LSB               0
+#define WLAN_GPIO_PIN11_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN11_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB)
+#define WLAN_GPIO_PIN11_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN12_ADDRESS                  0x00000058
+#define WLAN_GPIO_PIN12_OFFSET                   0x00000058
+#define WLAN_GPIO_PIN12_CONFIG_MSB               13
+#define WLAN_GPIO_PIN12_CONFIG_LSB               11
+#define WLAN_GPIO_PIN12_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN12_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB)
+#define WLAN_GPIO_PIN12_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN12_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN12_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN12_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN12_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN12_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN12_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN12_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN12_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN12_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN12_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN12_SOURCE_MSB               0
+#define WLAN_GPIO_PIN12_SOURCE_LSB               0
+#define WLAN_GPIO_PIN12_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN12_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB)
+#define WLAN_GPIO_PIN12_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN13_ADDRESS                  0x0000005c
+#define WLAN_GPIO_PIN13_OFFSET                   0x0000005c
+#define WLAN_GPIO_PIN13_CONFIG_MSB               13
+#define WLAN_GPIO_PIN13_CONFIG_LSB               11
+#define WLAN_GPIO_PIN13_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN13_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB)
+#define WLAN_GPIO_PIN13_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN13_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN13_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN13_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN13_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN13_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN13_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN13_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN13_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN13_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN13_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN13_SOURCE_MSB               0
+#define WLAN_GPIO_PIN13_SOURCE_LSB               0
+#define WLAN_GPIO_PIN13_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN13_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB)
+#define WLAN_GPIO_PIN13_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN14_ADDRESS                  0x00000060
+#define WLAN_GPIO_PIN14_OFFSET                   0x00000060
+#define WLAN_GPIO_PIN14_CONFIG_MSB               13
+#define WLAN_GPIO_PIN14_CONFIG_LSB               11
+#define WLAN_GPIO_PIN14_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN14_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB)
+#define WLAN_GPIO_PIN14_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN14_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN14_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN14_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN14_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN14_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN14_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN14_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN14_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN14_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN14_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN14_SOURCE_MSB               0
+#define WLAN_GPIO_PIN14_SOURCE_LSB               0
+#define WLAN_GPIO_PIN14_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN14_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB)
+#define WLAN_GPIO_PIN14_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN15_ADDRESS                  0x00000064
+#define WLAN_GPIO_PIN15_OFFSET                   0x00000064
+#define WLAN_GPIO_PIN15_CONFIG_MSB               13
+#define WLAN_GPIO_PIN15_CONFIG_LSB               11
+#define WLAN_GPIO_PIN15_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN15_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB)
+#define WLAN_GPIO_PIN15_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN15_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN15_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN15_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN15_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN15_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN15_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN15_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN15_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN15_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN15_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN15_SOURCE_MSB               0
+#define WLAN_GPIO_PIN15_SOURCE_LSB               0
+#define WLAN_GPIO_PIN15_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN15_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB)
+#define WLAN_GPIO_PIN15_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN16_ADDRESS                  0x00000068
+#define WLAN_GPIO_PIN16_OFFSET                   0x00000068
+#define WLAN_GPIO_PIN16_CONFIG_MSB               13
+#define WLAN_GPIO_PIN16_CONFIG_LSB               11
+#define WLAN_GPIO_PIN16_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN16_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB)
+#define WLAN_GPIO_PIN16_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN16_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN16_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN16_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN16_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN16_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN16_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN16_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN16_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN16_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN16_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN16_SOURCE_MSB               0
+#define WLAN_GPIO_PIN16_SOURCE_LSB               0
+#define WLAN_GPIO_PIN16_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN16_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB)
+#define WLAN_GPIO_PIN16_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN17_ADDRESS                  0x0000006c
+#define WLAN_GPIO_PIN17_OFFSET                   0x0000006c
+#define WLAN_GPIO_PIN17_CONFIG_MSB               13
+#define WLAN_GPIO_PIN17_CONFIG_LSB               11
+#define WLAN_GPIO_PIN17_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN17_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB)
+#define WLAN_GPIO_PIN17_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN17_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN17_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN17_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN17_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN17_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN17_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN17_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN17_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN17_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN17_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN17_SOURCE_MSB               0
+#define WLAN_GPIO_PIN17_SOURCE_LSB               0
+#define WLAN_GPIO_PIN17_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN17_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB)
+#define WLAN_GPIO_PIN17_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN18_ADDRESS                  0x00000070
+#define WLAN_GPIO_PIN18_OFFSET                   0x00000070
+#define WLAN_GPIO_PIN18_CONFIG_MSB               13
+#define WLAN_GPIO_PIN18_CONFIG_LSB               11
+#define WLAN_GPIO_PIN18_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN18_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB)
+#define WLAN_GPIO_PIN18_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN18_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN18_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN18_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN18_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN18_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN18_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN18_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN18_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN18_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN18_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN18_SOURCE_MSB               0
+#define WLAN_GPIO_PIN18_SOURCE_LSB               0
+#define WLAN_GPIO_PIN18_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN18_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB)
+#define WLAN_GPIO_PIN18_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN19_ADDRESS                  0x00000074
+#define WLAN_GPIO_PIN19_OFFSET                   0x00000074
+#define WLAN_GPIO_PIN19_CONFIG_MSB               13
+#define WLAN_GPIO_PIN19_CONFIG_LSB               11
+#define WLAN_GPIO_PIN19_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN19_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB)
+#define WLAN_GPIO_PIN19_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN19_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN19_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN19_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN19_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN19_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN19_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN19_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN19_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN19_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN19_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN19_SOURCE_MSB               0
+#define WLAN_GPIO_PIN19_SOURCE_LSB               0
+#define WLAN_GPIO_PIN19_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN19_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB)
+#define WLAN_GPIO_PIN19_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN20_ADDRESS                  0x00000078
+#define WLAN_GPIO_PIN20_OFFSET                   0x00000078
+#define WLAN_GPIO_PIN20_CONFIG_MSB               13
+#define WLAN_GPIO_PIN20_CONFIG_LSB               11
+#define WLAN_GPIO_PIN20_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN20_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB)
+#define WLAN_GPIO_PIN20_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN20_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN20_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN20_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN20_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN20_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN20_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN20_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN20_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN20_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN20_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN20_SOURCE_MSB               0
+#define WLAN_GPIO_PIN20_SOURCE_LSB               0
+#define WLAN_GPIO_PIN20_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN20_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB)
+#define WLAN_GPIO_PIN20_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN21_ADDRESS                  0x0000007c
+#define WLAN_GPIO_PIN21_OFFSET                   0x0000007c
+#define WLAN_GPIO_PIN21_CONFIG_MSB               13
+#define WLAN_GPIO_PIN21_CONFIG_LSB               11
+#define WLAN_GPIO_PIN21_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN21_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB)
+#define WLAN_GPIO_PIN21_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN21_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN21_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN21_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN21_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN21_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN21_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN21_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN21_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN21_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN21_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN21_SOURCE_MSB               0
+#define WLAN_GPIO_PIN21_SOURCE_LSB               0
+#define WLAN_GPIO_PIN21_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN21_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB)
+#define WLAN_GPIO_PIN21_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN22_ADDRESS                  0x00000080
+#define WLAN_GPIO_PIN22_OFFSET                   0x00000080
+#define WLAN_GPIO_PIN22_CONFIG_MSB               13
+#define WLAN_GPIO_PIN22_CONFIG_LSB               11
+#define WLAN_GPIO_PIN22_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN22_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB)
+#define WLAN_GPIO_PIN22_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN22_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN22_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN22_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN22_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN22_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN22_PAD_PULL_MSB             6
+#define WLAN_GPIO_PIN22_PAD_PULL_LSB             5
+#define WLAN_GPIO_PIN22_PAD_PULL_MASK            0x00000060
+#define WLAN_GPIO_PIN22_PAD_PULL_GET(x)          (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN22_PAD_PULL_SET(x)          (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB         4
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB         3
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK        0x00000018
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)      (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)      (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN22_SOURCE_MSB               0
+#define WLAN_GPIO_PIN22_SOURCE_LSB               0
+#define WLAN_GPIO_PIN22_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN22_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB)
+#define WLAN_GPIO_PIN22_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN23_ADDRESS                  0x00000084
+#define WLAN_GPIO_PIN23_OFFSET                   0x00000084
+#define WLAN_GPIO_PIN23_CONFIG_MSB               13
+#define WLAN_GPIO_PIN23_CONFIG_LSB               11
+#define WLAN_GPIO_PIN23_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN23_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB)
+#define WLAN_GPIO_PIN23_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN23_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN23_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN23_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN23_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN23_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN23_SOURCE_MSB               0
+#define WLAN_GPIO_PIN23_SOURCE_LSB               0
+#define WLAN_GPIO_PIN23_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN23_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB)
+#define WLAN_GPIO_PIN23_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN24_ADDRESS                  0x00000088
+#define WLAN_GPIO_PIN24_OFFSET                   0x00000088
+#define WLAN_GPIO_PIN24_CONFIG_MSB               13
+#define WLAN_GPIO_PIN24_CONFIG_LSB               11
+#define WLAN_GPIO_PIN24_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN24_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB)
+#define WLAN_GPIO_PIN24_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN24_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN24_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN24_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN24_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN24_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN24_SOURCE_MSB               0
+#define WLAN_GPIO_PIN24_SOURCE_LSB               0
+#define WLAN_GPIO_PIN24_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN24_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB)
+#define WLAN_GPIO_PIN24_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN25_ADDRESS                  0x0000008c
+#define WLAN_GPIO_PIN25_OFFSET                   0x0000008c
+#define WLAN_GPIO_PIN25_CONFIG_MSB               13
+#define WLAN_GPIO_PIN25_CONFIG_LSB               11
+#define WLAN_GPIO_PIN25_CONFIG_MASK              0x00003800
+#define WLAN_GPIO_PIN25_CONFIG_GET(x)            (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB)
+#define WLAN_GPIO_PIN25_CONFIG_SET(x)            (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB        10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB        10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK       0x00000400
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)     (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)     (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN25_INT_TYPE_MSB             9
+#define WLAN_GPIO_PIN25_INT_TYPE_LSB             7
+#define WLAN_GPIO_PIN25_INT_TYPE_MASK            0x00000380
+#define WLAN_GPIO_PIN25_INT_TYPE_GET(x)          (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN25_INT_TYPE_SET(x)          (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB           2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB           2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK          0x00000004
+#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)        (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)        (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN25_SOURCE_MSB               0
+#define WLAN_GPIO_PIN25_SOURCE_LSB               0
+#define WLAN_GPIO_PIN25_SOURCE_MASK              0x00000001
+#define WLAN_GPIO_PIN25_SOURCE_GET(x)            (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB)
+#define WLAN_GPIO_PIN25_SOURCE_SET(x)            (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK)
+
+#define SDIO_ADDRESS                             0x00000090
+#define SDIO_OFFSET                              0x00000090
+#define SDIO_PINS_EN_MSB                         0
+#define SDIO_PINS_EN_LSB                         0
+#define SDIO_PINS_EN_MASK                        0x00000001
+#define SDIO_PINS_EN_GET(x)                      (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB)
+#define SDIO_PINS_EN_SET(x)                      (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK)
+
+#define FUNC_BUS_ADDRESS                         0x00000094
+#define FUNC_BUS_OFFSET                          0x00000094
+#define FUNC_BUS_GPIO_MODE_MSB                   22
+#define FUNC_BUS_GPIO_MODE_LSB                   22
+#define FUNC_BUS_GPIO_MODE_MASK                  0x00400000
+#define FUNC_BUS_GPIO_MODE_GET(x)                (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB)
+#define FUNC_BUS_GPIO_MODE_SET(x)                (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK)
+#define FUNC_BUS_OE_L_MSB                        21
+#define FUNC_BUS_OE_L_LSB                        0
+#define FUNC_BUS_OE_L_MASK                       0x003fffff
+#define FUNC_BUS_OE_L_GET(x)                     (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB)
+#define FUNC_BUS_OE_L_SET(x)                     (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK)
+
+#define WL_SOC_APB_ADDRESS                       0x00000098
+#define WL_SOC_APB_OFFSET                        0x00000098
+#define WL_SOC_APB_TOGGLE_MSB                    0
+#define WL_SOC_APB_TOGGLE_LSB                    0
+#define WL_SOC_APB_TOGGLE_MASK                   0x00000001
+#define WL_SOC_APB_TOGGLE_GET(x)                 (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB)
+#define WL_SOC_APB_TOGGLE_SET(x)                 (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK)
+
+#define WLAN_SIGMA_DELTA_ADDRESS                 0x0000009c
+#define WLAN_SIGMA_DELTA_OFFSET                  0x0000009c
+#define WLAN_SIGMA_DELTA_ENABLE_MSB              16
+#define WLAN_SIGMA_DELTA_ENABLE_LSB              16
+#define WLAN_SIGMA_DELTA_ENABLE_MASK             0x00010000
+#define WLAN_SIGMA_DELTA_ENABLE_GET(x)           (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB)
+#define WLAN_SIGMA_DELTA_ENABLE_SET(x)           (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK)
+#define WLAN_SIGMA_DELTA_PRESCALAR_MSB           15
+#define WLAN_SIGMA_DELTA_PRESCALAR_LSB           8
+#define WLAN_SIGMA_DELTA_PRESCALAR_MASK          0x0000ff00
+#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x)        (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB)
+#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x)        (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK)
+#define WLAN_SIGMA_DELTA_TARGET_MSB              7
+#define WLAN_SIGMA_DELTA_TARGET_LSB              0
+#define WLAN_SIGMA_DELTA_TARGET_MASK             0x000000ff
+#define WLAN_SIGMA_DELTA_TARGET_GET(x)           (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB)
+#define WLAN_SIGMA_DELTA_TARGET_SET(x)           (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK)
+
+#define WL_BOOTSTRAP_ADDRESS                     0x000000a0
+#define WL_BOOTSTRAP_OFFSET                      0x000000a0
+#define WL_BOOTSTRAP_STATUS_MSB                  22
+#define WL_BOOTSTRAP_STATUS_LSB                  0
+#define WL_BOOTSTRAP_STATUS_MASK                 0x007fffff
+#define WL_BOOTSTRAP_STATUS_GET(x)               (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB)
+#define WL_BOOTSTRAP_STATUS_SET(x)               (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK)
+
+#define CLOCK_GPIO_ADDRESS                       0x000000a4
+#define CLOCK_GPIO_OFFSET                        0x000000a4
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB            2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB            2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK           0x00000004
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x)         (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB)
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x)         (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB             1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB             1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK            0x00000002
+#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x)          (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x)          (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB             0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0x00000001
+#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x)          (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x)          (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
+
+#define WLAN_DEBUG_CONTROL_ADDRESS               0x000000a8
+#define WLAN_DEBUG_CONTROL_OFFSET                0x000000a8
+#define WLAN_DEBUG_CONTROL_ENABLE_MSB            0
+#define WLAN_DEBUG_CONTROL_ENABLE_LSB            0
+#define WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
+#define WLAN_DEBUG_CONTROL_ENABLE_GET(x)         (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_SET(x)         (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK)
+
+#define WLAN_DEBUG_INPUT_SEL_ADDRESS             0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_OFFSET              0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB           5
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB           4
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK          0x00000030
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)        (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)        (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK)
+#define WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
+#define WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
+#define WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
+#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x)          (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x)          (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK)
+
+#define WLAN_DEBUG_OUT_ADDRESS                   0x000000b0
+#define WLAN_DEBUG_OUT_OFFSET                    0x000000b0
+#define WLAN_DEBUG_OUT_DATA_MSB                  17
+#define WLAN_DEBUG_OUT_DATA_LSB                  0
+#define WLAN_DEBUG_OUT_DATA_MASK                 0x0003ffff
+#define WLAN_DEBUG_OUT_DATA_GET(x)               (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
+#define WLAN_DEBUG_OUT_DATA_SET(x)               (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
+
+#define WLAN_RESET_TUPLE_STATUS_ADDRESS          0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_OFFSET           0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+#define ANTENNA_SLEEP_CONTROL_ADDRESS            0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OFFSET             0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB       14
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB       10
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK      0x00007c00
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x)    (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB)
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x)    (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK)
+#define ANTENNA_SLEEP_CONTROL_VALUE_MSB          9
+#define ANTENNA_SLEEP_CONTROL_VALUE_LSB          5
+#define ANTENNA_SLEEP_CONTROL_VALUE_MASK         0x000003e0
+#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x)       (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB)
+#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x)       (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB         4
+#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB         0
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK        0x0000001f
+#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x)      (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x)      (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_athr_wlan_reg_reg_s {
+  volatile unsigned int wlan_gpio_out;
+  volatile unsigned int wlan_gpio_out_w1ts;
+  volatile unsigned int wlan_gpio_out_w1tc;
+  volatile unsigned int wlan_gpio_enable;
+  volatile unsigned int wlan_gpio_enable_w1ts;
+  volatile unsigned int wlan_gpio_enable_w1tc;
+  volatile unsigned int wlan_gpio_in;
+  volatile unsigned int wlan_gpio_status;
+  volatile unsigned int wlan_gpio_status_w1ts;
+  volatile unsigned int wlan_gpio_status_w1tc;
+  volatile unsigned int wlan_gpio_pin0;
+  volatile unsigned int wlan_gpio_pin1;
+  volatile unsigned int wlan_gpio_pin2;
+  volatile unsigned int wlan_gpio_pin3;
+  volatile unsigned int wlan_gpio_pin4;
+  volatile unsigned int wlan_gpio_pin5;
+  volatile unsigned int wlan_gpio_pin6;
+  volatile unsigned int wlan_gpio_pin7;
+  volatile unsigned int wlan_gpio_pin8;
+  volatile unsigned int wlan_gpio_pin9;
+  volatile unsigned int wlan_gpio_pin10;
+  volatile unsigned int wlan_gpio_pin11;
+  volatile unsigned int wlan_gpio_pin12;
+  volatile unsigned int wlan_gpio_pin13;
+  volatile unsigned int wlan_gpio_pin14;
+  volatile unsigned int wlan_gpio_pin15;
+  volatile unsigned int wlan_gpio_pin16;
+  volatile unsigned int wlan_gpio_pin17;
+  volatile unsigned int wlan_gpio_pin18;
+  volatile unsigned int wlan_gpio_pin19;
+  volatile unsigned int wlan_gpio_pin20;
+  volatile unsigned int wlan_gpio_pin21;
+  volatile unsigned int wlan_gpio_pin22;
+  volatile unsigned int wlan_gpio_pin23;
+  volatile unsigned int wlan_gpio_pin24;
+  volatile unsigned int wlan_gpio_pin25;
+  volatile unsigned int sdio;
+  volatile unsigned int func_bus;
+  volatile unsigned int wl_soc_apb;
+  volatile unsigned int wlan_sigma_delta;
+  volatile unsigned int wl_bootstrap;
+  volatile unsigned int clock_gpio;
+  volatile unsigned int wlan_debug_control;
+  volatile unsigned int wlan_debug_input_sel;
+  volatile unsigned int wlan_debug_out;
+  volatile unsigned int wlan_reset_tuple_status;
+  volatile unsigned int antenna_sleep_control;
+} gpio_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_ATHR_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h
new file mode 100644
index 000000000000..2d5c1cd22aa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h
@@ -0,0 +1,1090 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "gpio_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS
+#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET
+#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB
+#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB
+#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK
+#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x)
+#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x)
+#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS
+#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET
+#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB
+#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB
+#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK
+#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x)
+#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x)
+#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS
+#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET
+#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB
+#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB
+#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK
+#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x)
+#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x)
+#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS
+#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET
+#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB
+#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB
+#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK
+#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x)
+#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x)
+#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS
+#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET
+#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB
+#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB
+#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK
+#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)
+#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)
+#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS
+#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET
+#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB
+#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB
+#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK
+#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)
+#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)
+#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS
+#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET
+#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB
+#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB
+#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK
+#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x)
+#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x)
+#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS
+#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET
+#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB
+#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB
+#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK
+#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x)
+#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS
+#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS
+#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)
+#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS
+#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET
+#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB
+#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
+#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
+#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x)
+#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB
+#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB
+#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK
+#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x)
+#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x)
+#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB
+#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
+#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
+#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x)
+#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x)
+#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB
+#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB
+#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK
+#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)
+#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)
+#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB
+#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB
+#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK
+#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)
+#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)
+#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB
+#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB
+#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK
+#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x)
+#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x)
+#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS
+#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET
+#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB
+#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB
+#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
+#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x)
+#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB
+#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB
+#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK
+#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x)
+#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x)
+#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB
+#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB
+#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK
+#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x)
+#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x)
+#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB
+#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB
+#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK
+#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)
+#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)
+#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB
+#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB
+#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK
+#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)
+#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)
+#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB
+#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB
+#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK
+#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x)
+#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x)
+#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS
+#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET
+#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB
+#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB
+#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK
+#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x)
+#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB
+#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB
+#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK
+#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x)
+#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x)
+#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB
+#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB
+#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK
+#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x)
+#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x)
+#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB
+#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB
+#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK
+#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)
+#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)
+#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB
+#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB
+#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK
+#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)
+#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)
+#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB
+#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB
+#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK
+#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x)
+#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x)
+#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS
+#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET
+#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB
+#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB
+#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK
+#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x)
+#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB
+#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB
+#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK
+#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x)
+#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x)
+#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB
+#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB
+#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK
+#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x)
+#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x)
+#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB
+#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB
+#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK
+#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)
+#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)
+#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB
+#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB
+#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK
+#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)
+#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)
+#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB
+#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB
+#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK
+#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x)
+#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x)
+#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS
+#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET
+#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB
+#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB
+#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK
+#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x)
+#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB
+#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB
+#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK
+#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x)
+#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x)
+#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB
+#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB
+#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK
+#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x)
+#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x)
+#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB
+#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB
+#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK
+#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)
+#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)
+#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB
+#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB
+#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK
+#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)
+#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)
+#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB
+#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB
+#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK
+#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x)
+#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x)
+#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS
+#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET
+#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB
+#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB
+#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK
+#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x)
+#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB
+#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB
+#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK
+#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x)
+#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x)
+#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB
+#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB
+#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK
+#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x)
+#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x)
+#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB
+#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB
+#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK
+#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)
+#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)
+#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB
+#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB
+#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK
+#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)
+#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)
+#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB
+#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB
+#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK
+#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x)
+#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x)
+#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS
+#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET
+#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB
+#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB
+#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK
+#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x)
+#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB
+#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB
+#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK
+#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x)
+#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x)
+#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB
+#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB
+#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK
+#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x)
+#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x)
+#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB
+#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB
+#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK
+#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)
+#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)
+#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB
+#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB
+#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK
+#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)
+#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)
+#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB
+#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB
+#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK
+#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x)
+#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x)
+#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS
+#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET
+#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB
+#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB
+#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK
+#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x)
+#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB
+#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB
+#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK
+#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x)
+#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x)
+#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB
+#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB
+#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK
+#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x)
+#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x)
+#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB
+#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB
+#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK
+#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)
+#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)
+#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB
+#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB
+#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK
+#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)
+#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)
+#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB
+#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB
+#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK
+#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x)
+#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x)
+#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS
+#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET
+#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB
+#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB
+#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK
+#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x)
+#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB
+#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB
+#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK
+#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x)
+#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x)
+#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB
+#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB
+#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK
+#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x)
+#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x)
+#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB
+#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB
+#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK
+#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)
+#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)
+#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB
+#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB
+#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK
+#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)
+#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)
+#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB
+#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB
+#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK
+#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x)
+#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x)
+#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS
+#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET
+#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB
+#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB
+#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK
+#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x)
+#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB
+#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB
+#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK
+#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x)
+#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x)
+#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB
+#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB
+#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK
+#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x)
+#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x)
+#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB
+#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB
+#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK
+#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)
+#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)
+#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB
+#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB
+#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK
+#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)
+#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)
+#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB
+#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB
+#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK
+#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x)
+#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x)
+#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS
+#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET
+#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB
+#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB
+#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK
+#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x)
+#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB
+#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB
+#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK
+#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x)
+#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x)
+#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB
+#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB
+#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK
+#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x)
+#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x)
+#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB
+#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB
+#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK
+#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)
+#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)
+#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB
+#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB
+#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK
+#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)
+#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)
+#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB
+#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB
+#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK
+#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x)
+#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x)
+#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS
+#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET
+#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB
+#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB
+#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK
+#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x)
+#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB
+#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB
+#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK
+#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x)
+#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x)
+#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB
+#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB
+#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK
+#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x)
+#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x)
+#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB
+#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB
+#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK
+#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)
+#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)
+#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB
+#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB
+#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK
+#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)
+#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)
+#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB
+#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB
+#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK
+#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x)
+#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x)
+#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS
+#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET
+#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB
+#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB
+#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK
+#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x)
+#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB
+#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB
+#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK
+#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x)
+#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x)
+#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB
+#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB
+#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK
+#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x)
+#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x)
+#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB
+#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB
+#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK
+#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)
+#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)
+#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB
+#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB
+#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK
+#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)
+#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)
+#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB
+#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB
+#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK
+#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x)
+#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x)
+#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS
+#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET
+#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB
+#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB
+#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK
+#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x)
+#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB
+#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB
+#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK
+#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x)
+#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x)
+#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB
+#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB
+#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK
+#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x)
+#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x)
+#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB
+#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB
+#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK
+#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)
+#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)
+#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB
+#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB
+#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK
+#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)
+#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)
+#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB
+#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB
+#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK
+#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x)
+#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x)
+#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS
+#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET
+#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB
+#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB
+#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK
+#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x)
+#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB
+#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB
+#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK
+#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x)
+#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x)
+#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB
+#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB
+#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK
+#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x)
+#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x)
+#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB
+#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB
+#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK
+#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)
+#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)
+#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB
+#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB
+#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK
+#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)
+#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)
+#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB
+#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB
+#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK
+#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x)
+#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x)
+#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS
+#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET
+#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB
+#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB
+#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK
+#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x)
+#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB
+#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB
+#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK
+#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x)
+#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x)
+#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB
+#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB
+#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK
+#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x)
+#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x)
+#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB
+#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB
+#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK
+#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)
+#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)
+#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB
+#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB
+#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK
+#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)
+#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)
+#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB
+#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB
+#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK
+#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x)
+#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x)
+#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS
+#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET
+#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB
+#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB
+#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK
+#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x)
+#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB
+#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB
+#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK
+#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x)
+#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x)
+#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB
+#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB
+#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK
+#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x)
+#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x)
+#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB
+#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB
+#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK
+#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)
+#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)
+#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB
+#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB
+#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK
+#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)
+#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)
+#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB
+#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB
+#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK
+#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x)
+#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x)
+#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS
+#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET
+#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB
+#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB
+#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK
+#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x)
+#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB
+#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB
+#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK
+#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x)
+#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x)
+#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB
+#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB
+#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK
+#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x)
+#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x)
+#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB
+#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB
+#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK
+#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)
+#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)
+#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB
+#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB
+#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK
+#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)
+#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)
+#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB
+#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB
+#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK
+#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x)
+#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x)
+#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS
+#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET
+#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB
+#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB
+#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK
+#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x)
+#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB
+#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB
+#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK
+#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB
+#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB
+#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK
+#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x)
+#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x)
+#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB
+#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB
+#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK
+#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x)
+#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x)
+#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB
+#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB
+#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK
+#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)
+#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)
+#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB
+#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB
+#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK
+#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)
+#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)
+#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB
+#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB
+#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK
+#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x)
+#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x)
+#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS
+#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET
+#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB
+#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB
+#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK
+#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x)
+#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB
+#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB
+#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK
+#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB
+#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB
+#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK
+#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x)
+#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x)
+#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB
+#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB
+#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK
+#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x)
+#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x)
+#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB
+#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB
+#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK
+#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)
+#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)
+#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB
+#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB
+#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK
+#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)
+#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)
+#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB
+#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB
+#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK
+#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x)
+#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x)
+#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS
+#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET
+#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB
+#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB
+#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK
+#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x)
+#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB
+#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB
+#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK
+#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB
+#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB
+#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK
+#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x)
+#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x)
+#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB
+#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB
+#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK
+#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x)
+#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x)
+#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB
+#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB
+#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK
+#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)
+#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)
+#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB
+#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB
+#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK
+#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)
+#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)
+#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB
+#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB
+#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK
+#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x)
+#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x)
+#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS
+#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET
+#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB
+#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB
+#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK
+#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x)
+#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB
+#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB
+#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK
+#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB
+#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB
+#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK
+#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x)
+#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x)
+#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB
+#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB
+#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK
+#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x)
+#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x)
+#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB
+#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB
+#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK
+#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)
+#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)
+#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB
+#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB
+#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK
+#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)
+#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)
+#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB
+#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB
+#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK
+#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x)
+#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x)
+#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS
+#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET
+#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB
+#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB
+#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK
+#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x)
+#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB
+#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB
+#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK
+#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB
+#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB
+#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK
+#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x)
+#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x)
+#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB
+#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB
+#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK
+#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x)
+#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x)
+#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB
+#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB
+#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK
+#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)
+#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)
+#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB
+#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB
+#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK
+#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)
+#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)
+#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB
+#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB
+#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK
+#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x)
+#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x)
+#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS
+#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET
+#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB
+#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB
+#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK
+#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x)
+#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB
+#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB
+#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK
+#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB
+#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB
+#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK
+#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x)
+#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x)
+#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB
+#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB
+#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK
+#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)
+#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)
+#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB
+#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB
+#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK
+#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x)
+#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x)
+#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS
+#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET
+#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB
+#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB
+#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK
+#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x)
+#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB
+#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB
+#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK
+#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB
+#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB
+#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK
+#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x)
+#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x)
+#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB
+#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB
+#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK
+#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)
+#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)
+#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB
+#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB
+#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK
+#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x)
+#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x)
+#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS
+#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET
+#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB
+#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB
+#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK
+#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x)
+#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB
+#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB
+#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK
+#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB
+#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB
+#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK
+#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x)
+#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x)
+#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB
+#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB
+#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK
+#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)
+#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)
+#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB
+#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB
+#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK
+#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x)
+#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x)
+#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS
+#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET
+#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB
+#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB
+#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK
+#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x)
+#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x)
+#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB
+#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB
+#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK
+#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x)
+#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x)
+#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB
+#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB
+#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK
+#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x)
+#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x)
+#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS
+#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET
+#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB
+#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB
+#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK
+#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x)
+#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x)
+#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS
+#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET
+#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB
+#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB
+#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK
+#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)
+#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)
+#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB
+#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB
+#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK
+#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x)
+#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x)
+#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS
+#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET
+#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB
+#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB
+#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK
+#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x)
+#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x)
+#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS
+#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h
new file mode 100644
index 000000000000..f700d41851c6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h
@@ -0,0 +1,587 @@
+//
+// Copyright (c) 2002-2009 Atheros Communications Inc.
+// All rights reserved.
+// $ATH_LICENSE_TMAC_DMAGET_C$
+//
+
+/*****************************************************************************/
+/* AR6003 WLAN MAC DMA register definitions                                  */
+/*****************************************************************************/
+
+#ifndef _AR6000_DMAREG_H_
+#define _AR6000_DMAREG_H_
+
+/*
+ * Definitions for the Atheros AR6003 chipset.
+ */
+
+/* DMA Control and Interrupt Registers */
+#define MAC_DMA_CR_ADDRESS                       0x00000008 /* MAC control register */
+#define MAC_DMA_CR_RXE_MASK                      0x00000004 /* Receive enable */
+#define MAC_DMA_CR_RXD_MASK                      0x00000020 /* Receive disable */
+#define MAC_DMA_CR_SWI_MASK                      0x00000040 /* One-shot software interrupt */
+
+#define MAC_DMA_RXDP_ADDRESS                     0x0000000C /* MAC receive queue descriptor pointer */
+
+#define MAC_DMA_CFG_ADDRESS                      0x00000014 /* MAC configuration and status register */
+#define MAC_DMA_CFG_SWTD_MASK                    0x00000001 /* byteswap tx descriptor words */
+#define MAC_DMA_CFG_SWTB_MASK                    0x00000002 /* byteswap tx data buffer words */
+#define MAC_DMA_CFG_SWRD_MASK                    0x00000004 /* byteswap rx descriptor words */
+#define MAC_DMA_CFG_SWRB_MASK                    0x00000008 /* byteswap rx data buffer words */
+#define MAC_DMA_CFG_SWRG_MASK                    0x00000010 /* byteswap register access data words */
+#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK     0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
+#define MAC_DMA_CFG_PHOK_MASK                    0x00000100 /* PHY OK status */
+#define MAC_DMA_CFG_CLK_GATE_DIS_MASK            0x00000400 /* Clock gating disable  */
+
+#define MAC_DMA_MIRT_ADDRESS                     0x00000020 /* Maximum rate threshold register */
+#define MAC_DMA_MIRT_THRESH_MASK                 0x0000FFFF 
+
+#define MAC_DMA_IER_ADDRESS                      0x00000024  /* MAC Interrupt enable register */
+#define MAC_DMA_IER_ENABLE_MASK                  0x00000001 /* Global interrupt enable */
+#define MAC_DMA_IER_DISABLE_MASK                 0x00000000 /* Global interrupt disable */
+
+#define MAC_DMA_TIMT_ADDRESS                     0x00000028 /* Transmit Interrupt Mitigation Threshold */
+#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK     0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK    0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_RIMT_ADDRESS                     0x0000002C /* Receive Interrupt Mitigation Threshold */
+#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK     0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK    0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_TXCFG_ADDRESS                    0x00000030  /* MAC tx DMA size config register */
+#define MAC_DMA_FTRIG_MASK                       0x000003F0 /* Mask for Frame trigger level */
+#define MAC_DMA_FTRIG_LSB                        4          /* Shift for Frame trigger level */
+#define MAC_DMA_FTRIG_IMMED                      0x00000000 /* bytes in PCU TX FIFO before air */
+#define MAC_DMA_FTRIG_64B                        0x00000010 /* default */
+#define MAC_DMA_FTRIG_128B                       0x00000020
+#define MAC_DMA_FTRIG_192B                       0x00000030
+#define MAC_DMA_FTRIG_256B                       0x00000040 /* 5 bits total */
+#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
+
+#define MAC_DMA_RXCFG_ADDRESS                     0x00000034  /* MAC rx DMA size config register */
+#define MAC_DMA_RXCFG_ZLFDMA_MASK                 0x00000010 /* Enable DMA of zero-length frame */
+#define MAC_DMA_RXCFG_DMASIZE_4B                  0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
+#define MAC_DMA_RXCFG_DMASIZE_8B                  0x00000001 /* DMA size 8 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_16B                 0x00000002 /* DMA size 16 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_32B                 0x00000003 /* DMA size 32 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_64B                 0x00000004 /* DMA size 64 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_128B                0x00000005 /* DMA size 128 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_256B                0x00000006 /* DMA size 256 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_512B                0x00000007 /* DMA size 512 bytes */
+
+#define MAC_DMA_MIBC_ADDRESS                      0x00000040  /* MAC MIB control register */
+#define MAC_DMA_MIBC_COW_MASK                     0x00000001 /* counter overflow warning */
+#define MAC_DMA_MIBC_FMC_MASK                     0x00000002 /* freeze MIB counters */
+#define MAC_DMA_MIBC_CMC_MASK                     0x00000004 /* clear MIB counters */
+#define MAC_DMA_MIBC_MCS_MASK                     0x00000008 /* MIB counter strobe, increment all */
+
+#define MAC_DMA_TOPS_ADDRESS                      0x00000044  /* MAC timeout prescale count */
+#define MAC_DMA_TOPS_MASK                         0x0000FFFF /* Mask for timeout prescale */
+
+#define MAC_DMA_RXNPTO_ADDRESS                    0x00000048  /* MAC no frame received timeout */
+#define MAC_DMA_RXNPTO_MASK                       0x000003FF /* Mask for no frame received timeout */
+
+#define MAC_DMA_TXNPTO_ADDRESS                    0x0000004C  /* MAC no frame trasmitted timeout */
+#define MAC_DMA_TXNPTO_MASK                       0x000003FF /* Mask for no frame transmitted timeout */
+#define MAC_DMA_TXNPTO_QCU_MASK                   0x000FFC00 /* Mask indicating the set of QCUs */
+                                                       /* for which frame completions will cause */
+                                                       /* a reset of the no frame xmit'd timeout */
+
+#define MAC_DMA_RPGTO_ADDRESS                     0x00000050  /* MAC receive frame gap timeout */
+#define MAC_DMA_RPGTO_MASK                        0x000003FF /* Mask for receive frame gap timeout */
+
+#define MAC_DMA_RPCNT_ADDRESS                     0x00000054  /* MAC receive frame count limit */
+#define MAC_DMA_RPCNT_MASK                        0x0000001F /* Mask for receive frame count limit */
+
+#define MAC_DMA_MACMISC_ADDRESS                   0x00000058  /* MAC miscellaneous control/status register */
+#define MAC_DMA_MACMISC_DMA_OBS_MASK              0x000001E0 /* Mask for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_DMA_OBS_LSB               5          /* Shift for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS                  0x00000E00 /* Mask for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS_LSB              9          /* Shift for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB           0x00007000 /* Mask for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB       12         /* Shift for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB           0x00038000 /* Mask for MAC observation bus mux select (msb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB       15         /* Shift for MAC observation bus mux select (msb) */
+
+
+#define MAC_DMA_ISR_ADDRESS                        0x00000080  /* MAC Primary interrupt status register */
+/*
+ * Interrupt Status Registers
+ *
+ * Only the bits in the ISR_P register and the IMR_P registers
+ * control whether the MAC's INTA# output is asserted.  The bits in
+ * the secondary interrupt status/mask registers control what bits
+ * are set in the primary interrupt status register; however the
+ * IMR_S* registers DO NOT determine whether INTA# is asserted.
+ * That is INTA# is asserted only when the logical AND of ISR_P
+ * and IMR_P is non-zero.  The secondary interrupt mask/status
+ * registers affect what bits are set in ISR_P but they do not
+ * directly affect whether INTA# is asserted.
+ */
+#define MAC_DMA_ISR_RXOK_MASK                    0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_ISR_RXDESC_MASK                  0x00000002 /* Receive interrupt request */
+#define MAC_DMA_ISR_RXERR_MASK                   0x00000004 /* Receive error interrupt */
+#define MAC_DMA_ISR_RXNOPKT_MASK                 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_ISR_RXEOL_MASK                   0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_ISR_RXORN_MASK                   0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_ISR_TXOK_MASK                    0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_ISR_TXDESC_MASK                  0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_ISR_TXERR_MASK                   0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_ISR_TXNOPKT_MASK                 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_ISR_TXEOL_MASK                   0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_ISR_TXURN_MASK                   0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_ISR_MIB_MASK                     0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_ISR_SWI_MASK                     0x00002000 /* Software interrupt */
+#define MAC_DMA_ISR_RXPHY_MASK                   0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_ISR_RXKCM_MASK                   0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_ISR_BRSSI_HI_MASK                0x00010000 /* Beacon rssi high threshold interrupt */
+#define MAC_DMA_ISR_BRSSI_LO_MASK                0x00020000 /* Beacon threshold interrupt */
+#define MAC_DMA_ISR_BMISS_MASK                   0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_ISR_TXMINTR_MASK                 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_ISR_BNR_MASK                     0x00100000 /* Beacon not ready interrupt */
+#define MAC_DMA_ISR_HIUERR_MASK                  0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_ISR_BCNMISC_MASK                 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
+#define MAC_DMA_ISR_RXMINTR_MASK                 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_ISR_QCBROVF_MASK                 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_ISR_QCBRURN_MASK                 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_ISR_QTRIG_MASK                   0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_ISR_TIMER_MASK                   0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_ISR_HCFTO_MASK                   0x20000000 /* HCFTO interrupt   */
+#define MAC_DMA_ISR_TXINTM_MASK                  0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_ISR_RXINTM_MASK                  0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_ISR_S0_ADDRESS                   0x00000084  /* MAC Secondary interrupt status register 0 */
+#define MAC_DMA_ISR_S0_QCU_TXOK_MASK             0x000003FF /* Mask for TXOK (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXOK_LSB              0
+#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK           0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB            16
+
+#define MAC_DMA_ISR_S1_ADDRESS                   0x00000088  /* MAC Secondary interrupt status register 1 */
+#define MAC_DMA_ISR_S1_QCU_TXERR_MASK            0x000003FF /* Mask for TXERR (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXERR_LSB             0
+#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK            0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB             16
+
+#define MAC_DMA_ISR_S2_ADDRESS                      0x0000008c  /* MAC Secondary interrupt status register 2 */
+#define MAC_DMA_ISR_S2_QCU_TXURN_MASK               0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_QCU_TXURN_LSB                0 /* Shift for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_RX_INT_MASK			        0x00000800
+#define MAC_DMA_ISR_S2_WL_STOMPED_MASK		        0x00001000
+#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK		        0x00002000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK  0x00004000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK	0x00008000
+#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK            0x00010000
+#define MAC_DMA_ISR_S2_BT_STOMPED_MASK		        0x00020000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK	    0x00040000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK	    0x00080000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK	    0x00100000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK	    0x00200000
+#define MAC_DMA_ISR_S2_CST_MASK			            0x00400000
+#define MAC_DMA_ISR_S2_GTT_MASK			            0x00800000
+#define MAC_DMA_ISR_S2_TIM_MASK                     0x01000000 /* TIM */
+#define MAC_DMA_ISR_S2_CABEND_MASK                  0x02000000 /* CABEND */
+#define MAC_DMA_ISR_S2_DTIMSYNC_MASK                0x04000000 /* DTIMSYNC */
+#define MAC_DMA_ISR_S2_BCNTO_MASK                   0x08000000 /* BCNTO */
+#define MAC_DMA_ISR_S2_CABTO_MASK                   0x10000000 /* CABTO */
+#define MAC_DMA_ISR_S2_DTIM_MASK                    0x20000000 /* DTIM */
+#define MAC_DMA_ISR_S2_TSFOOR_MASK                  0x40000000 /* TSFOOR */
+
+#define MAC_DMA_ISR_S3_ADDRESS                   0x00000090  /* MAC Secondary interrupt status register 3 */
+#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK          0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK          0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+
+#define MAC_DMA_ISR_S4_ADDRESS                   0x00000094  /* MAC Secondary interrupt status register 4 */
+#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK            0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_ISR_S5_ADDRESS                   0x00000098  /* MAC Secondary interrupt status register 5 */
+#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK   0x00000001
+#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK    0x00000002
+#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK    0x00000004
+#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK    0x00000008
+#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK    0x00000010
+#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK   0x00000020
+#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK  0x00000040
+#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK    0x00000080
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
+#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK       0x00010000
+#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK  0x00020000
+#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK  0x00040000
+#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK  0x00080000
+#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK  0x00100000
+#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK  0x00200000
+#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
+#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK   0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB  24 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_IMR_ADDRESS                      0x000000A0  /* MAC Primary interrupt mask register */
+/*
+ * Interrupt Mask Registers
+ *
+ * Only the bits in the IMR control whether the MAC's INTA#
+ * output will be asserted.  The bits in the secondary interrupt
+ * mask registers control what bits get set in the primary
+ * interrupt status register; however the IMR_S* registers
+ * DO NOT determine whether INTA# is asserted.
+ */
+#define MAC_DMA_IMR_RXOK_MASK                    0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_IMR_RXDESC_MASK                  0x00000002 /* Receive interrupt request */
+#define MAC_DMA_IMR_RXERR_MASK                   0x00000004 /* Receive error interrupt */
+#define MAC_DMA_IMR_RXNOPKT_MASK                 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_IMR_RXEOL_MASK                   0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_IMR_RXORN_MASK                   0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_IMR_TXOK_MASK                    0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_IMR_TXDESC_MASK                  0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_IMR_TXERR_MASK                   0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_IMR_TXNOPKT_MASK                 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_IMR_TXEOL_MASK                   0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_IMR_TXURN_MASK                   0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_IMR_MIB_MASK                     0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_IMR_SWI_MASK                     0x00002000 /* Software interrupt */
+#define MAC_DMA_IMR_RXPHY_MASK                   0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_IMR_RXKCM_MASK                   0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_IMR_BRSSI_HI_MASK                0x00010000 /* Beacon rssi hi threshold interrupt */
+#define MAC_DMA_IMR_BRSSI_LO_MASK                0x00020000 /* Beacon rssi lo threshold interrupt */
+#define MAC_DMA_IMR_BMISS_MASK                   0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_IMR_TXMINTR_MASK                 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_IMR_BNR_MASK                     0x00100000 /* BNR interrupt */
+#define MAC_DMA_IMR_HIUERR_MASK                  0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_IMR_BCNMISC_MASK                 0x00800000 /* Beacon Misc */
+#define MAC_DMA_IMR_RXMINTR_MASK                 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_IMR_QCBROVF_MASK                 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_IMR_QCBRURN_MASK                 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_IMR_QTRIG_MASK                   0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_IMR_TIMER_MASK                   0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_IMR_HCFTO_MASK                   0x20000000 /* HCFTO interrupt*/
+#define MAC_DMA_IMR_TXINTM_MASK                  0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_IMR_RXINTM_MASK                  0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_IMR_S0_ADDRESS                   0x000000A4  /* MAC Secondary interrupt mask register 0 */
+#define MAC_DMA_IMR_S0_QCU_TXOK_MASK             0x000003FF /* TXOK (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXOK_LSB              0
+#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK           0x03FF0000 /* TXDESC (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB            16
+
+#define MAC_DMA_IMR_S1_ADDRESS                   0x000000A8  /* MAC Secondary interrupt mask register 1 */
+#define MAC_DMA_IMR_S1_QCU_TXERR_MASK            0x000003FF /* TXERR (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXERR_LSB             0
+#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK            0x03FF0000 /* TXEOL (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB             16
+
+#define MAC_DMA_IMR_S2_ADDRESS                      0x000000AC  /* MAC Secondary interrupt mask register 2 */
+#define MAC_DMA_IMR_S2_QCU_TXURN_MASK               0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_IMR_S2_QCU_TXURN_LSB                0
+#define MAC_DMA_IMR_S2_RX_INT_MASK			        0x00000800
+#define MAC_DMA_IMR_S2_WL_STOMPED_MASK		        0x00001000
+#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK		        0x00002000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK  0x00004000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK	0x00008000
+#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK            0x00010000
+#define MAC_DMA_IMR_S2_BT_STOMPED_MASK		        0x00020000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK	    0x00040000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK	    0x00080000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK	    0x00100000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK	    0x00200000
+#define MAC_DMA_IMR_S2_CST_MASK			            0x00400000
+#define MAC_DMA_IMR_S2_GTT_MASK			            0x00800000
+#define MAC_DMA_IMR_S2_TIM_MASK                     0x01000000 /* TIM */
+#define MAC_DMA_IMR_S2_CABEND_MASK                  0x02000000 /* CABEND */
+#define MAC_DMA_IMR_S2_DTIMSYNC_MASK                0x04000000 /* DTIMSYNC */
+#define MAC_DMA_IMR_S2_BCNTO_MASK                   0x08000000 /* BCNTO */
+#define MAC_DMA_IMR_S2_CABTO_MASK                   0x10000000 /* CABTO */
+#define MAC_DMA_IMR_S2_DTIM_MASK                    0x20000000 /* DTIM */
+#define MAC_DMA_IMR_S2_TSFOOR_MASK                  0x40000000 /* TSFOOR */
+
+#define MAC_DMA_IMR_S3_ADDRESS                   0x000000B0  /* MAC Secondary interrupt mask register 3 */
+#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK          0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK          0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB           16 
+
+#define MAC_DMA_IMR_S4_ADDRESS                   0x000000B4  /* MAC Secondary interrupt mask register 4 */
+#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK            0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_IMR_S5_ADDRESS                   0x000000B8  /* MAC Secondary interrupt mask register 5 */
+#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK   0x00000001
+#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK    0x00000002
+#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK    0x00000004
+#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK    0x00000008
+#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK    0x00000010
+#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK   0x00000020
+#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK  0x00000040
+#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK    0x00000080
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i)    (0x100 << (_i))
+#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK       0x00010000
+#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK  0x00020000
+#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK  0x00040000
+#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK  0x00080000
+#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK  0x00100000
+#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
+#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
+#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK  0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB  24 
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_ISR_RAC_ADDRESS                  0x000000C0  /* ISR read-and-clear access */
+
+/* Shadow copies with read-and-clear access */
+#define MAC_DMA_ISR_S0_S_ADDRESS                 0x000000C4  /* ISR_S0 shadow copy */
+#define MAC_DMA_ISR_S1_S_ADDRESS                 0x000000C8  /* ISR_S1 shadow copy */
+#define MAC_DMA_ISR_S2_S_ADDRESS                 0x000000Cc  /* ISR_S2 shadow copy */
+#define MAC_DMA_ISR_S3_S_ADDRESS                 0x000000D0  /* ISR_S3 shadow copy */
+#define MAC_DMA_ISR_S4_S_ADDRESS                 0x000000D4  /* ISR_S4 shadow copy */
+#define MAC_DMA_ISR_S5_S_ADDRESS                 0x000000D8  /* ISR_S5 shadow copy */
+
+#define MAC_DMA_Q0_TXDP_ADDRESS                  0x00000800  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q1_TXDP_ADDRESS                  0x00000804  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q2_TXDP_ADDRESS                  0x00000808  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q3_TXDP_ADDRESS                  0x0000080C  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q4_TXDP_ADDRESS                  0x00000810  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q5_TXDP_ADDRESS                  0x00000814  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q6_TXDP_ADDRESS                  0x00000818  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q7_TXDP_ADDRESS                  0x0000081C  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q8_TXDP_ADDRESS                  0x00000820  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q9_TXDP_ADDRESS                  0x00000824  /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_QTXDP_ADDRESS(_i)                (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_TXE_ADDRESS                    0x00000840  /* MAC Transmit Queue enable */
+#define MAC_DMA_Q_TXD_ADDRESS                    0x00000880  /* MAC Transmit Queue disable */
+/* QCU registers */
+
+#define MAC_DMA_Q0_CBRCFG_ADDRESS                0x000008C0  /* MAC CBR configuration */
+#define MAC_DMA_Q1_CBRCFG_ADDRESS                0x000008C4  /* MAC CBR configuration */
+#define MAC_DMA_Q2_CBRCFG_ADDRESS                0x000008C8  /* MAC CBR configuration */
+#define MAC_DMA_Q3_CBRCFG_ADDRESS                0x000008CC  /* MAC CBR configuration */
+#define MAC_DMA_Q4_CBRCFG_ADDRESS                0x000008D0  /* MAC CBR configuration */
+#define MAC_DMA_Q5_CBRCFG_ADDRESS                0x000008D4  /* MAC CBR configuration */
+#define MAC_DMA_Q6_CBRCFG_ADDRESS                0x000008D8  /* MAC CBR configuration */
+#define MAC_DMA_Q7_CBRCFG_ADDRESS                0x000008DC  /* MAC CBR configuration */
+#define MAC_DMA_Q8_CBRCFG_ADDRESS                0x000008E0  /* MAC CBR configuration */
+#define MAC_DMA_Q9_CBRCFG_ADDRESS                0x000008E4  /* MAC CBR configuration */
+#define MAC_DMA_QCBRCFG_ADDRESS(_i)             (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK        0x00FFFFFF /* Mask for CBR interval (us) */
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB         0   /* Shift for CBR interval */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK      0xFF000000 /* Mask for CBR overflow threshold */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB       24  /* Shift for CBR overflow thresh */
+
+
+#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS             0x00000900  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS             0x00000904  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS             0x00000908  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS             0x0000090C  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS             0x00000910  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS             0x00000914  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS             0x00000918  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS             0x0000091C  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS             0x00000920  /* MAC ReadyTime configuration */
+#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS             0x00000924  /* MAC ReadyTime configuration */
+#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i)           (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_RDYTIMECFG_INT_MASK             0x00FFFFFF /* CBR interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_INT_LSB              0  /* Shift for ReadyTime Interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK             0x01000000 /* CBR enable */
+
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS      0x00000940  /* MAC OneShotArm set control */
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS      0x00000980  /* MAC OneShotArm clear control */
+
+#define MAC_DMA_Q0_MISC_ADDRESS                   0x000009C0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q1_MISC_ADDRESS                   0x000009C4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q2_MISC_ADDRESS                   0x000009C8  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q3_MISC_ADDRESS                   0x000009CC  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q4_MISC_ADDRESS                   0x000009D0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q5_MISC_ADDRESS                   0x000009D4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q6_MISC_ADDRESS                   0x000009D8  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q7_MISC_ADDRESS                   0x000009DC  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q8_MISC_ADDRESS                   0x000009E0  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q9_MISC_ADDRESS                   0x000009E4  /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_QMISC_ADDRESS(_i)                 (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_MISC_FSP_MASK                   0x0000000F /* Frame Scheduling Policy mask */
+#define MAC_DMA_Q_MISC_FSP_ASAP                   0   /* ASAP */
+#define MAC_DMA_Q_MISC_FSP_CBR                    1   /* CBR */
+#define MAC_DMA_Q_MISC_FSP_DBA_GATED              2   /* DMA Beacon Alert gated */
+#define MAC_DMA_Q_MISC_FSP_TIM_GATED              3   /* TIM gated */
+#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED      4   /* Beacon-sent-gated */
+#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK           0x00000010 /* OneShot enable */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK         0x00000020 /* Disable CBR expired counter incr
+                                                        (empty q) */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK         0x00000040 /* Disable CBR expired counter incr
+                                                        (empty beacon q) */
+#define MAC_DMA_Q_MISC_BEACON_USE_MASK            0x00000080 /* Beacon use indication */
+#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK    0x00000100 /* CBR expired counter limit enable */
+#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK    0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
+#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK     0x00000400 /* Reset CBR expired counter */
+#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK    0x00000800 /* DCU frame early termination request control */
+
+#define MAC_DMA_Q0_STS_ADDRESS                   0x00000A00  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q1_STS_ADDRESS                   0x00000A04  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q2_STS_ADDRESS                   0x00000A08  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q3_STS_ADDRESS                   0x00000A0C  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q4_STS_ADDRESS                   0x00000A10  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q5_STS_ADDRESS                   0x00000A14  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q6_STS_ADDRESS                   0x00000A18  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q7_STS_ADDRESS                   0x00000A1C  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q8_STS_ADDRESS                   0x00000A20  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q9_STS_ADDRESS                   0x00000A24  /* MAC Miscellaneous QCU status */
+#define MAC_DMA_QSTS_ADDRESS(_i)                 (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK           0x00000003 /* Mask for Pending Frame Count */
+#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK           0x0000FF00 /* Mask for CBR expired counter */
+
+#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS            0x00000A40  /* MAC ReadyTimeShutdown status */
+
+/* DCU registers */
+
+#define MAC_DMA_D0_QCUMASK_ADDRESS               0x00001000  /* MAC QCU Mask */
+#define MAC_DMA_D1_QCUMASK_ADDRESS               0x00001004  /* MAC QCU Mask */
+#define MAC_DMA_D2_QCUMASK_ADDRESS               0x00001008  /* MAC QCU Mask */
+#define MAC_DMA_D3_QCUMASK_ADDRESS               0x0000100C  /* MAC QCU Mask */
+#define MAC_DMA_D4_QCUMASK_ADDRESS               0x00001010  /* MAC QCU Mask */
+#define MAC_DMA_D5_QCUMASK_ADDRESS               0x00001014  /* MAC QCU Mask */
+#define MAC_DMA_D6_QCUMASK_ADDRESS               0x00001018  /* MAC QCU Mask */
+#define MAC_DMA_D7_QCUMASK_ADDRESS               0x0000101C  /* MAC QCU Mask */
+#define MAC_DMA_D8_QCUMASK_ADDRESS               0x00001020  /* MAC QCU Mask */
+#define MAC_DMA_D9_QCUMASK_ADDRESS               0x00001024  /* MAC QCU Mask */
+#define MAC_DMA_DQCUMASK_ADDRESS(_i)             (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_QCUMASK_MASK                   0x000003FF /* Mask for QCU Mask (QCU 0-9) */
+
+#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS           0x00001030  /* DCU global SIFS settings */
+
+
+#define MAC_DMA_D0_LCL_IFS_ADDRESS               0x00001040  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D1_LCL_IFS_ADDRESS               0x00001044  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D2_LCL_IFS_ADDRESS               0x00001048  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D3_LCL_IFS_ADDRESS               0x0000104C  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D4_LCL_IFS_ADDRESS               0x00001050  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D5_LCL_IFS_ADDRESS               0x00001054  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D6_LCL_IFS_ADDRESS               0x00001058  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D7_LCL_IFS_ADDRESS               0x0000105C  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D8_LCL_IFS_ADDRESS               0x00001060  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D9_LCL_IFS_ADDRESS               0x00001064  /* MAC DCU-specific IFS settings */
+#define MAC_DMA_DLCL_IFS_ADDRESS(_i)             (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
+#define MAC_DMA_D_LCL_IFS_CWMIN_MASK             0x000003FF /* Mask for CW_MIN */
+#define MAC_DMA_D_LCL_IFS_CWMIN_LSB              0
+#define MAC_DMA_D_LCL_IFS_CWMAX_MASK             0x000FFC00 /* Mask for CW_MAX */
+#define MAC_DMA_D_LCL_IFS_CWMAX_LSB              10
+#define MAC_DMA_D_LCL_IFS_AIFS_MASK              0x0FF00000 /* Mask for AIFS */
+#define MAC_DMA_D_LCL_IFS_AIFS_LSB               20
+/*
+ *  Note:  even though this field is 8 bits wide the
+ *  maximum supported AIFS value is 0xFc.  Setting the AIFS value
+ *  to 0xFd 0xFe, or 0xFf will not work correctly and will cause
+ *  the DCU to hang.
+ */
+#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS           0x00001070  /* DC global slot interval */
+
+#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS           0x00001080  /* MAC Retry limits */
+#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS           0x00001084  /* MAC Retry limits */
+#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS           0x00001088  /* MAC Retry limits */
+#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS           0x0000108C  /* MAC Retry limits */
+#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS           0x00001090  /* MAC Retry limits */
+#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS           0x00001094  /* MAC Retry limits */
+#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS           0x00001098  /* MAC Retry limits */
+#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS           0x0000109C  /* MAC Retry limits */
+#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS           0x000010A0  /* MAC Retry limits */
+#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS           0x000010A4  /* MAC Retry limits */
+#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i)         (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK        0x0000000F /* frame RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB         0
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK       0x00003F00 /* station RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB        8
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK      0x000FC000 /* station short retry limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB       14
+
+#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS           0x000010B0  /* DCU global EIFS setting */
+
+#define MAC_DMA_D0_CHNTIME_ADDRESS               0x000010C0  /* MAC ChannelTime settings */
+#define MAC_DMA_D1_CHNTIME_ADDRESS               0x000010C4  /* MAC ChannelTime settings */
+#define MAC_DMA_D2_CHNTIME_ADDRESS               0x000010C8  /* MAC ChannelTime settings */
+#define MAC_DMA_D3_CHNTIME_ADDRESS               0x000010CC  /* MAC ChannelTime settings */
+#define MAC_DMA_D4_CHNTIME_ADDRESS               0x000010D0  /* MAC ChannelTime settings */
+#define MAC_DMA_D5_CHNTIME_ADDRESS               0x000010D4  /* MAC ChannelTime settings */
+#define MAC_DMA_D6_CHNTIME_ADDRESS               0x000010D8  /* MAC ChannelTime settings */
+#define MAC_DMA_D7_CHNTIME_ADDRESS               0x000010DC  /* MAC ChannelTime settings */
+#define MAC_DMA_D8_CHNTIME_ADDRESS               0x000010E0  /* MAC ChannelTime settings */
+#define MAC_DMA_D9_CHNTIME_ADDRESS               0x000010E4  /* MAC ChannelTime settings */
+#define MAC_DMA_DCHNTIME_ADDRESS(_i)             (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_CHNTIME_DUR_MASK               0x000FFFFF /* ChannelTime duration (us) */
+#define MAC_DMA_D_CHNTIME_DUR_LSB                0 /* Shift for ChannelTime duration */
+#define MAC_DMA_D_CHNTIME_EN_MASK                0x00100000 /* ChannelTime enable */
+
+#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS           0x000010f0  /* DCU global misc. IFS settings */
+#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
+#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK     0x00000008 /* Turbo mode indication */
+#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
+#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK      0x10000000
+
+#define MAC_DMA_D0_MISC_ADDRESS                  0x00001100  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D1_MISC_ADDRESS                  0x00001104  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D2_MISC_ADDRESS                  0x00001108  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D3_MISC_ADDRESS                  0x0000110C  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D4_MISC_ADDRESS                  0x00001110  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D5_MISC_ADDRESS                  0x00001114  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D6_MISC_ADDRESS                  0x00001118  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D7_MISC_ADDRESS                  0x0000111C  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D8_MISC_ADDRESS                  0x00001120  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D9_MISC_ADDRESS                  0x00001124  /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_DMISC_ADDRESS(_i)                (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D0_EOL_ADDRESS                  0x00001180
+#define MAC_DMA_D1_EOL_ADDRESS                  0x00001184
+#define MAC_DMA_D2_EOL_ADDRESS                  0x00001188
+#define MAC_DMA_D3_EOL_ADDRESS                  0x0000118C
+#define MAC_DMA_D4_EOL_ADDRESS                  0x00001190
+#define MAC_DMA_D5_EOL_ADDRESS                  0x00001194
+#define MAC_DMA_D6_EOL_ADDRESS                  0x00001198
+#define MAC_DMA_D7_EOL_ADDRESS                  0x0000119C
+#define MAC_DMA_D8_EOL_ADDRESS                  0x00001200
+#define MAC_DMA_D9_EOL_ADDRESS                  0x00001204
+#define MAC_DMA_DEOL_ADDRESS(_i)                (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK         0x0000003F /* Backoff threshold */
+#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB       0
+#define MAC_DMA_D_MISC_ETS_RTS_MASK              0x00000040 /* End of transmission series
+                                                          station RTS/data failure
+                                                          count reset policy */
+#define MAC_DMA_D_MISC_ETS_CW_MASK               0x00000080 /* End of transmission series
+                                                          CW reset policy */
+#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK         0x00000100  /* Fragment Starvation Policy */
+
+#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK        0x00000200 /* Backoff during a frag burst */
+#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK          0x00000800 /* HFC poll enable */
+#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK    0x00001000 /* Backoff persistence factor
+                                                          setting */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK     0x0000C000 /* Mask for Virtual collision
+                                                          handling policy */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB      14
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT  0   /* Normal */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE   1   /* Ignore */
+#define MAC_DMA_D_MISC_BEACON_USE_MASK           0x00010000 /*  Beacon use indication */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /*  Mask for DCU arbiter lockout control */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB  17
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE     0        /*  No lockout*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1        /*  Intra-frame*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2        /*  Global */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /*  DCU arbiter lockout ignore control */
+#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK    0x00100000 /* Sequence number increment disable */
+#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK   0x00200000 /* Post-frame backoff disable */
+#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK    0x00400000 /* Virtual coll. handling policy */
+#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK    0x00800000 /* Blown IFS handling policy */
+
+#define MAC_DMA_D_SEQNUM_ADDRESS                0x00001140  /* MAC Frame sequence number */
+
+
+
+#define MAC_DMA_D_FPCTL_ADDRESS                  0x00001230      /* DCU frame prefetch settings */
+#define MAC_DMA_D_TXPSE_ADDRESS                  0x00001270      /* DCU transmit pause control/status */
+
+#endif /* _AR6000_DMMAEG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h
new file mode 100644
index 000000000000..9825b7b984fa
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h
@@ -0,0 +1,3061 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MAC_PCU_REG_H_
+#define _MAC_PCU_REG_H_
+
+#define MAC_PCU_STA_ADDR_L32_ADDRESS             0x00008000
+#define MAC_PCU_STA_ADDR_L32_OFFSET              0x00000000
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB       31
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB       0
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK      0xffffffff
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x)    (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB)
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x)    (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK)
+
+#define MAC_PCU_STA_ADDR_U16_ADDRESS             0x00008004
+#define MAC_PCU_STA_ADDR_U16_OFFSET              0x00000004
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB    30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB    30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK   0x40000000
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB      28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB      28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK     0x10000000
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB   25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB   25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK  0x02000000
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB      24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB      24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK     0x01000000
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB     23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB     23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK    0x00800000
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x)  (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x)  (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB   22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB   22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK  0x00400000
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB      21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB      21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK     0x00200000
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK)
+#define MAC_PCU_STA_ADDR_U16_PCF_MSB             20
+#define MAC_PCU_STA_ADDR_U16_PCF_LSB             20
+#define MAC_PCU_STA_ADDR_U16_PCF_MASK            0x00100000
+#define MAC_PCU_STA_ADDR_U16_PCF_GET(x)          (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB)
+#define MAC_PCU_STA_ADDR_U16_PCF_SET(x)          (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB     19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB     19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK    0x00080000
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x)  (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x)  (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB         18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB         18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK        0x00040000
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x)      (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x)      (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB           17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB           17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK          0x00020000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x)        (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x)        (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB          16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB          16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK         0x00010000
+#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x)       (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x)       (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB      15
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB      0
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK     0x0000ffff
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x)   (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x)   (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK)
+
+#define MAC_PCU_BSSID_L32_ADDRESS                0x00008008
+#define MAC_PCU_BSSID_L32_OFFSET                 0x00000008
+#define MAC_PCU_BSSID_L32_ADDR_MSB               31
+#define MAC_PCU_BSSID_L32_ADDR_LSB               0
+#define MAC_PCU_BSSID_L32_ADDR_MASK              0xffffffff
+#define MAC_PCU_BSSID_L32_ADDR_GET(x)            (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB)
+#define MAC_PCU_BSSID_L32_ADDR_SET(x)            (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID_U16_ADDRESS                0x0000800c
+#define MAC_PCU_BSSID_U16_OFFSET                 0x0000000c
+#define MAC_PCU_BSSID_U16_AID_MSB                26
+#define MAC_PCU_BSSID_U16_AID_LSB                16
+#define MAC_PCU_BSSID_U16_AID_MASK               0x07ff0000
+#define MAC_PCU_BSSID_U16_AID_GET(x)             (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB)
+#define MAC_PCU_BSSID_U16_AID_SET(x)             (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK)
+#define MAC_PCU_BSSID_U16_ADDR_MSB               15
+#define MAC_PCU_BSSID_U16_ADDR_LSB               0
+#define MAC_PCU_BSSID_U16_ADDR_MASK              0x0000ffff
+#define MAC_PCU_BSSID_U16_ADDR_GET(x)            (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB)
+#define MAC_PCU_BSSID_U16_ADDR_SET(x)            (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK)
+
+#define MAC_PCU_BCN_RSSI_AVE_ADDRESS             0x00008010
+#define MAC_PCU_BCN_RSSI_AVE_OFFSET              0x00000010
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB           11
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB           0
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK          0x00000fff
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x)        (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB)
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x)        (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK)
+
+#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS          0x00008014
+#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET           0x00000014
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB  29
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB  16
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB  13
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB  0
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK)
+
+#define MAC_PCU_BCN_RSSI_CTL_ADDRESS             0x00008018
+#define MAC_PCU_BCN_RSSI_CTL_OFFSET              0x00000018
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB           29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB           29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK          0x20000000
+#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x)        (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x)        (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB          28
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB          24
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK         0x1f000000
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x)       (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x)       (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB     15
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB     8
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK    0x0000ff00
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x)  (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x)  (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK)
+
+#define MAC_PCU_USEC_LATENCY_ADDRESS             0x0000801c
+#define MAC_PCU_USEC_LATENCY_OFFSET              0x0000001c
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB      28
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB      23
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK     0x1f800000
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x)   (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x)   (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB      22
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB      14
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK     0x007fc000
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x)   (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x)   (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_USEC_MSB            7
+#define MAC_PCU_USEC_LATENCY_USEC_LSB            0
+#define MAC_PCU_USEC_LATENCY_USEC_MASK           0x000000ff
+#define MAC_PCU_USEC_LATENCY_USEC_GET(x)         (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB)
+#define MAC_PCU_USEC_LATENCY_USEC_SET(x)         (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK)
+
+#define PCU_MAX_CFP_DUR_ADDRESS                  0x00008020
+#define PCU_MAX_CFP_DUR_OFFSET                   0x00000020
+#define PCU_MAX_CFP_DUR_VALUE_MSB                15
+#define PCU_MAX_CFP_DUR_VALUE_LSB                0
+#define PCU_MAX_CFP_DUR_VALUE_MASK               0x0000ffff
+#define PCU_MAX_CFP_DUR_VALUE_GET(x)             (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB)
+#define PCU_MAX_CFP_DUR_VALUE_SET(x)             (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK)
+
+#define MAC_PCU_RX_FILTER_ADDRESS                0x00008024
+#define MAC_PCU_RX_FILTER_OFFSET                 0x00000024
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB     25
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB     24
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK    0x03000000
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x)  (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x)  (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB      23
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB      18
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK     0x00fc0000
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x)   (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x)   (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB         17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB         17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK        0x00020000
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x)      (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x)      (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB    15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB    15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK   0x00008000
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK)
+#define MAC_PCU_RX_FILTER_PS_POLL_MSB            14
+#define MAC_PCU_RX_FILTER_PS_POLL_LSB            14
+#define MAC_PCU_RX_FILTER_PS_POLL_MASK           0x00004000
+#define MAC_PCU_RX_FILTER_PS_POLL_GET(x)         (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB)
+#define MAC_PCU_RX_FILTER_PS_POLL_SET(x)         (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB       13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB       13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK      0x00002000
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x)    (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x)    (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB      11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB      11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK     0x00000800
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x)   (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x)   (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB     10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB     10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK    0x00000400
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x)  (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x)  (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK)
+#define MAC_PCU_RX_FILTER_MY_BEACON_MSB          9
+#define MAC_PCU_RX_FILTER_MY_BEACON_LSB          9
+#define MAC_PCU_RX_FILTER_MY_BEACON_MASK         0x00000200
+#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x)       (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x)       (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB         8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB         8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK        0x00000100
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x)      (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x)      (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB          7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB          7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK         0x00000080
+#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x)       (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x)       (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK)
+#define MAC_PCU_RX_FILTER_XR_POLL_MSB            6
+#define MAC_PCU_RX_FILTER_XR_POLL_LSB            6
+#define MAC_PCU_RX_FILTER_XR_POLL_MASK           0x00000040
+#define MAC_PCU_RX_FILTER_XR_POLL_GET(x)         (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB)
+#define MAC_PCU_RX_FILTER_XR_POLL_SET(x)         (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB        5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB        5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK       0x00000020
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x)     (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x)     (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK)
+#define MAC_PCU_RX_FILTER_BEACON_MSB             4
+#define MAC_PCU_RX_FILTER_BEACON_LSB             4
+#define MAC_PCU_RX_FILTER_BEACON_MASK            0x00000010
+#define MAC_PCU_RX_FILTER_BEACON_GET(x)          (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_BEACON_SET(x)          (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_CONTROL_MSB            3
+#define MAC_PCU_RX_FILTER_CONTROL_LSB            3
+#define MAC_PCU_RX_FILTER_CONTROL_MASK           0x00000008
+#define MAC_PCU_RX_FILTER_CONTROL_GET(x)         (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB)
+#define MAC_PCU_RX_FILTER_CONTROL_SET(x)         (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK)
+#define MAC_PCU_RX_FILTER_BROADCAST_MSB          2
+#define MAC_PCU_RX_FILTER_BROADCAST_LSB          2
+#define MAC_PCU_RX_FILTER_BROADCAST_MASK         0x00000004
+#define MAC_PCU_RX_FILTER_BROADCAST_GET(x)       (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB)
+#define MAC_PCU_RX_FILTER_BROADCAST_SET(x)       (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK)
+#define MAC_PCU_RX_FILTER_MULTICAST_MSB          1
+#define MAC_PCU_RX_FILTER_MULTICAST_LSB          1
+#define MAC_PCU_RX_FILTER_MULTICAST_MASK         0x00000002
+#define MAC_PCU_RX_FILTER_MULTICAST_GET(x)       (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB)
+#define MAC_PCU_RX_FILTER_MULTICAST_SET(x)       (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK)
+#define MAC_PCU_RX_FILTER_UNICAST_MSB            0
+#define MAC_PCU_RX_FILTER_UNICAST_LSB            0
+#define MAC_PCU_RX_FILTER_UNICAST_MASK           0x00000001
+#define MAC_PCU_RX_FILTER_UNICAST_GET(x)         (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB)
+#define MAC_PCU_RX_FILTER_UNICAST_SET(x)         (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK)
+
+#define MAC_PCU_MCAST_FILTER_L32_ADDRESS         0x00008028
+#define MAC_PCU_MCAST_FILTER_L32_OFFSET          0x00000028
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB       31
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB       0
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK      0xffffffff
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x)    (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x)    (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK)
+
+#define MAC_PCU_MCAST_FILTER_U32_ADDRESS         0x0000802c
+#define MAC_PCU_MCAST_FILTER_U32_OFFSET          0x0000002c
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB       31
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB       0
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK      0xffffffff
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x)    (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x)    (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK)
+
+#define MAC_PCU_DIAG_SW_ADDRESS                  0x00008030
+#define MAC_PCU_DIAG_SW_OFFSET                   0x00000030
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB           31
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB           30
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK          0xc0000000
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x)        (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB)
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x)        (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB     29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB     29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK    0x20000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x)  (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x)  (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB     28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB     28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK    0x10000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x)  (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x)  (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB            27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB            27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK           0x08000000
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x)         (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x)         (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB   26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB   26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK  0x04000000
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB       25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB       25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK      0x02000000
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x)    (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x)    (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB       22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB       22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK      0x00400000
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x)    (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x)    (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB           21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB           21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK          0x00200000
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x)        (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x)        (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB        20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB        20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK       0x00100000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x)     (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x)     (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB          19
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB          18
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK         0x000c0000
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x)       (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x)       (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB        17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB        17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK       0x00020000
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x)     (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x)     (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB       8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB       8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK      0x00000100
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x)    (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x)    (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB          7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB          7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK         0x00000080
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x)       (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x)       (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB            6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB            6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK           0x00000040
+#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x)         (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x)         (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK)
+#define MAC_PCU_DIAG_SW_HALT_RX_MSB              5
+#define MAC_PCU_DIAG_SW_HALT_RX_LSB              5
+#define MAC_PCU_DIAG_SW_HALT_RX_MASK             0x00000020
+#define MAC_PCU_DIAG_SW_HALT_RX_GET(x)           (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB)
+#define MAC_PCU_DIAG_SW_HALT_RX_SET(x)           (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB           4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB           4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK          0x00000010
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x)        (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x)        (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB           3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB           3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK          0x00000008
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x)        (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x)        (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_CTS_MSB               2
+#define MAC_PCU_DIAG_SW_NO_CTS_LSB               2
+#define MAC_PCU_DIAG_SW_NO_CTS_MASK              0x00000004
+#define MAC_PCU_DIAG_SW_NO_CTS_GET(x)            (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB)
+#define MAC_PCU_DIAG_SW_NO_CTS_SET(x)            (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK)
+#define MAC_PCU_DIAG_SW_NO_ACK_MSB               1
+#define MAC_PCU_DIAG_SW_NO_ACK_LSB               1
+#define MAC_PCU_DIAG_SW_NO_ACK_MASK              0x00000002
+#define MAC_PCU_DIAG_SW_NO_ACK_GET(x)            (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_NO_ACK_SET(x)            (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB   0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB   0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK  0x00000001
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK)
+
+#define MAC_PCU_TST_ADDAC_ADDRESS                0x00008034
+#define MAC_PCU_TST_ADDAC_OFFSET                 0x00000034
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB           20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB           20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK          0x00100000
+#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB       19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB       19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK      0x00080000
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x)    (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x)    (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB          18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB          18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK         0x00040000
+#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x)       (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x)       (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB      17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB      17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK     0x00020000
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x)   (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x)   (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB           16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB           16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK          0x00010000
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB           14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB           14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK          0x00004000
+#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x)        (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x)        (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB           13
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB           3
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK          0x00003ff8
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x)        (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x)        (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_MSB               2
+#define MAC_PCU_TST_ADDAC_LOOP_LSB               2
+#define MAC_PCU_TST_ADDAC_LOOP_MASK              0x00000004
+#define MAC_PCU_TST_ADDAC_LOOP_GET(x)            (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_SET(x)            (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK)
+#define MAC_PCU_TST_ADDAC_TESTMODE_MSB           1
+#define MAC_PCU_TST_ADDAC_TESTMODE_LSB           1
+#define MAC_PCU_TST_ADDAC_TESTMODE_MASK          0x00000002
+#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x)        (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB)
+#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x)        (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TX_MSB            0
+#define MAC_PCU_TST_ADDAC_CONT_TX_LSB            0
+#define MAC_PCU_TST_ADDAC_CONT_TX_MASK           0x00000001
+#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x)         (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x)         (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK)
+
+#define MAC_PCU_DEF_ANTENNA_ADDRESS              0x00008038
+#define MAC_PCU_DEF_ANTENNA_OFFSET               0x00000038
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB   24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB   24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK  0x01000000
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_VALUE_MSB            23
+#define MAC_PCU_DEF_ANTENNA_VALUE_LSB            0
+#define MAC_PCU_DEF_ANTENNA_VALUE_MASK           0x00ffffff
+#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x)         (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB)
+#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x)         (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS          0x0000803c
+#define MAC_PCU_AES_MUTE_MASK_0_OFFSET           0x0000003c
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB          31
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB          16
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK         0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x)       (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x)       (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB           15
+#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB           0
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK          0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x)        (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x)        (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS          0x00008040
+#define MAC_PCU_AES_MUTE_MASK_1_OFFSET           0x00000040
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB      31
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB      16
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK     0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x)   (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x)   (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB          15
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB          0
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK         0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x)       (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x)       (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK)
+
+#define MAC_PCU_GATED_CLKS_ADDRESS               0x00008044
+#define MAC_PCU_GATED_CLKS_OFFSET                0x00000044
+#define MAC_PCU_GATED_CLKS_GATED_REG_MSB         3
+#define MAC_PCU_GATED_CLKS_GATED_REG_LSB         3
+#define MAC_PCU_GATED_CLKS_GATED_REG_MASK        0x00000008
+#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x)      (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x)      (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_RX_MSB          2
+#define MAC_PCU_GATED_CLKS_GATED_RX_LSB          2
+#define MAC_PCU_GATED_CLKS_GATED_RX_MASK         0x00000004
+#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x)       (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x)       (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_TX_MSB          1
+#define MAC_PCU_GATED_CLKS_GATED_TX_LSB          1
+#define MAC_PCU_GATED_CLKS_GATED_TX_MASK         0x00000002
+#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x)       (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x)       (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK)
+
+#define MAC_PCU_OBS_BUS_2_ADDRESS                0x00008048
+#define MAC_PCU_OBS_BUS_2_OFFSET                 0x00000048
+#define MAC_PCU_OBS_BUS_2_VALUE_MSB              17
+#define MAC_PCU_OBS_BUS_2_VALUE_LSB              0
+#define MAC_PCU_OBS_BUS_2_VALUE_MASK             0x0003ffff
+#define MAC_PCU_OBS_BUS_2_VALUE_GET(x)           (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB)
+#define MAC_PCU_OBS_BUS_2_VALUE_SET(x)           (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK)
+
+#define MAC_PCU_OBS_BUS_1_ADDRESS                0x0000804c
+#define MAC_PCU_OBS_BUS_1_OFFSET                 0x0000004c
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB           30
+#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB           25
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK          0x7e000000
+#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB           24
+#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB           20
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK          0x01f00000
+#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB          17
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB          12
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK         0x0003f000
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x)       (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x)       (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB           11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB           11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK          0x00000800
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB           10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB           10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK          0x00000400
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB           9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB           9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK          0x00000200
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x)        (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x)        (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB            8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB            8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK           0x00000100
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x)         (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x)         (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB   7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB   7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK  0x00000080
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB      6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB      6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK     0x00000040
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x)   (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x)   (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB             5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB             5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK            0x00000020
+#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x)          (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x)          (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB        4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB        4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK       0x00000010
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x)     (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x)     (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB       3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB       3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK      0x00000008
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x)    (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x)    (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB             2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB             2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK            0x00000004
+#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x)          (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x)          (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB         1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB         1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK        0x00000002
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x)      (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x)      (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB       0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB       0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK      0x00000001
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x)    (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x)    (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK)
+
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS        0x00008050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET         0x00000050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK)
+
+#define MAC_PCU_LAST_BEACON_TSF_ADDRESS          0x00008054
+#define MAC_PCU_LAST_BEACON_TSF_OFFSET           0x00000054
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB        31
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB        0
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK       0xffffffff
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x)     (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB)
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x)     (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK)
+
+#define MAC_PCU_NAV_ADDRESS                      0x00008058
+#define MAC_PCU_NAV_OFFSET                       0x00000058
+#define MAC_PCU_NAV_VALUE_MSB                    25
+#define MAC_PCU_NAV_VALUE_LSB                    0
+#define MAC_PCU_NAV_VALUE_MASK                   0x03ffffff
+#define MAC_PCU_NAV_VALUE_GET(x)                 (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB)
+#define MAC_PCU_NAV_VALUE_SET(x)                 (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK)
+
+#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS          0x0000805c
+#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET           0x0000005c
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB        15
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB        0
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK       0x0000ffff
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x)     (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x)     (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK)
+
+#define MAC_PCU_RTS_FAIL_CNT_ADDRESS             0x00008060
+#define MAC_PCU_RTS_FAIL_CNT_OFFSET              0x00000060
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_ACK_FAIL_CNT_ADDRESS             0x00008064
+#define MAC_PCU_ACK_FAIL_CNT_OFFSET              0x00000064
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_FCS_FAIL_CNT_ADDRESS             0x00008068
+#define MAC_PCU_FCS_FAIL_CNT_OFFSET              0x00000068
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB           15
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB           0
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK          0x0000ffff
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x)        (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x)        (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_BEACON_CNT_ADDRESS               0x0000806c
+#define MAC_PCU_BEACON_CNT_OFFSET                0x0000006c
+#define MAC_PCU_BEACON_CNT_VALUE_MSB             15
+#define MAC_PCU_BEACON_CNT_VALUE_LSB             0
+#define MAC_PCU_BEACON_CNT_VALUE_MASK            0x0000ffff
+#define MAC_PCU_BEACON_CNT_VALUE_GET(x)          (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB)
+#define MAC_PCU_BEACON_CNT_VALUE_SET(x)          (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK)
+
+#define MAC_PCU_XRMODE_ADDRESS                   0x00008070
+#define MAC_PCU_XRMODE_OFFSET                    0x00000070
+#define MAC_PCU_XRMODE_FRAME_HOLD_MSB            31
+#define MAC_PCU_XRMODE_FRAME_HOLD_LSB            20
+#define MAC_PCU_XRMODE_FRAME_HOLD_MASK           0xfff00000
+#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x)         (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB)
+#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x)         (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB         7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB         7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK        0x00000080
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x)      (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x)      (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK)
+#define MAC_PCU_XRMODE_POLL_TYPE_MSB             5
+#define MAC_PCU_XRMODE_POLL_TYPE_LSB             0
+#define MAC_PCU_XRMODE_POLL_TYPE_MASK            0x0000003f
+#define MAC_PCU_XRMODE_POLL_TYPE_GET(x)          (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB)
+#define MAC_PCU_XRMODE_POLL_TYPE_SET(x)          (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK)
+
+#define MAC_PCU_XRDEL_ADDRESS                    0x00008074
+#define MAC_PCU_XRDEL_OFFSET                     0x00000074
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB       31
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB       16
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK      0xffff0000
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x)    (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB)
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x)    (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK)
+#define MAC_PCU_XRDEL_SLOT_DELAY_MSB             15
+#define MAC_PCU_XRDEL_SLOT_DELAY_LSB             0
+#define MAC_PCU_XRDEL_SLOT_DELAY_MASK            0x0000ffff
+#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x)          (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB)
+#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x)          (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK)
+
+#define MAC_PCU_XRTO_ADDRESS                     0x00008078
+#define MAC_PCU_XRTO_OFFSET                      0x00000078
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB            31
+#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB            16
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK           0xffff0000
+#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x)         (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x)         (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB           15
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB           0
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK          0x0000ffff
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x)        (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x)        (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK)
+
+#define MAC_PCU_XRCRP_ADDRESS                    0x0000807c
+#define MAC_PCU_XRCRP_OFFSET                     0x0000007c
+#define MAC_PCU_XRCRP_CHIRP_GAP_MSB              31
+#define MAC_PCU_XRCRP_CHIRP_GAP_LSB              16
+#define MAC_PCU_XRCRP_CHIRP_GAP_MASK             0xffff0000
+#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x)           (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB)
+#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x)           (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK)
+#define MAC_PCU_XRCRP_SEND_CHIRP_MSB             0
+#define MAC_PCU_XRCRP_SEND_CHIRP_LSB             0
+#define MAC_PCU_XRCRP_SEND_CHIRP_MASK            0x00000001
+#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x)          (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB)
+#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x)          (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK)
+
+#define MAC_PCU_XRSTMP_ADDRESS                   0x00008080
+#define MAC_PCU_XRSTMP_OFFSET                    0x00000080
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB  23
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB  16
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB  15
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB  8
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB         5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB         5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK        0x00000020
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x)      (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x)      (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB         4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB         4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK        0x00000010
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x)      (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x)      (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB        3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB        3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK       0x00000008
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x)     (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x)     (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB         2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB         2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK        0x00000004
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x)      (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x)      (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB        1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB        1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK       0x00000002
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x)     (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x)     (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB         0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB         0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK        0x00000001
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x)      (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x)      (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK)
+
+#define MAC_PCU_ADDR1_MASK_L32_ADDRESS           0x00008084
+#define MAC_PCU_ADDR1_MASK_L32_OFFSET            0x00000084
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB         31
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB         0
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK        0xffffffff
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x)      (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x)      (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK)
+
+#define MAC_PCU_ADDR1_MASK_U16_ADDRESS           0x00008088
+#define MAC_PCU_ADDR1_MASK_U16_OFFSET            0x00000088
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB         15
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB         0
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK        0x0000ffff
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x)      (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x)      (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK)
+
+#define MAC_PCU_TPC_ADDRESS                      0x0000808c
+#define MAC_PCU_TPC_OFFSET                       0x0000008c
+#define MAC_PCU_TPC_CHIRP_PWR_MSB                21
+#define MAC_PCU_TPC_CHIRP_PWR_LSB                16
+#define MAC_PCU_TPC_CHIRP_PWR_MASK               0x003f0000
+#define MAC_PCU_TPC_CHIRP_PWR_GET(x)             (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB)
+#define MAC_PCU_TPC_CHIRP_PWR_SET(x)             (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK)
+#define MAC_PCU_TPC_CTS_PWR_MSB                  13
+#define MAC_PCU_TPC_CTS_PWR_LSB                  8
+#define MAC_PCU_TPC_CTS_PWR_MASK                 0x00003f00
+#define MAC_PCU_TPC_CTS_PWR_GET(x)               (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB)
+#define MAC_PCU_TPC_CTS_PWR_SET(x)               (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK)
+#define MAC_PCU_TPC_ACK_PWR_MSB                  5
+#define MAC_PCU_TPC_ACK_PWR_LSB                  0
+#define MAC_PCU_TPC_ACK_PWR_MASK                 0x0000003f
+#define MAC_PCU_TPC_ACK_PWR_GET(x)               (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB)
+#define MAC_PCU_TPC_ACK_PWR_SET(x)               (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK)
+
+#define MAC_PCU_TX_FRAME_CNT_ADDRESS             0x00008090
+#define MAC_PCU_TX_FRAME_CNT_OFFSET              0x00000090
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB           31
+#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB           0
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x)        (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x)        (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_FRAME_CNT_ADDRESS             0x00008094
+#define MAC_PCU_RX_FRAME_CNT_OFFSET              0x00000094
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB           31
+#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB           0
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_CLEAR_CNT_ADDRESS             0x00008098
+#define MAC_PCU_RX_CLEAR_CNT_OFFSET              0x00000098
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB           31
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB           0
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK          0xffffffff
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x)        (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x)        (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK)
+
+#define MAC_PCU_CYCLE_CNT_ADDRESS                0x0000809c
+#define MAC_PCU_CYCLE_CNT_OFFSET                 0x0000009c
+#define MAC_PCU_CYCLE_CNT_VALUE_MSB              31
+#define MAC_PCU_CYCLE_CNT_VALUE_LSB              0
+#define MAC_PCU_CYCLE_CNT_VALUE_MASK             0xffffffff
+#define MAC_PCU_CYCLE_CNT_VALUE_GET(x)           (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB)
+#define MAC_PCU_CYCLE_CNT_VALUE_SET(x)           (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK)
+
+#define MAC_PCU_QUIET_TIME_1_ADDRESS             0x000080a0
+#define MAC_PCU_QUIET_TIME_1_OFFSET              0x000000a0
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB  17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB  17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB)
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK)
+
+#define MAC_PCU_QUIET_TIME_2_ADDRESS             0x000080a4
+#define MAC_PCU_QUIET_TIME_2_OFFSET              0x000000a4
+#define MAC_PCU_QUIET_TIME_2_DURATION_MSB        31
+#define MAC_PCU_QUIET_TIME_2_DURATION_LSB        16
+#define MAC_PCU_QUIET_TIME_2_DURATION_MASK       0xffff0000
+#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x)     (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB)
+#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x)     (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK)
+
+#define MAC_PCU_QOS_NO_ACK_ADDRESS               0x000080a8
+#define MAC_PCU_QOS_NO_ACK_OFFSET                0x000000a8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB       8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB       7
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK      0x00000180
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x)    (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x)    (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB        6
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB        4
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK       0x00000070
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x)     (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x)     (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB    3
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB    0
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK   0x0000000f
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_ADDRESS           0x000080ac
+#define MAC_PCU_PHY_ERROR_MASK_OFFSET            0x000000ac
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB         31
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB         0
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK        0xffffffff
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x)      (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x)      (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK)
+
+#define MAC_PCU_XRLAT_ADDRESS                    0x000080b0
+#define MAC_PCU_XRLAT_OFFSET                     0x000000b0
+#define MAC_PCU_XRLAT_VALUE_MSB                  11
+#define MAC_PCU_XRLAT_VALUE_LSB                  0
+#define MAC_PCU_XRLAT_VALUE_MASK                 0x00000fff
+#define MAC_PCU_XRLAT_VALUE_GET(x)               (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB)
+#define MAC_PCU_XRLAT_VALUE_SET(x)               (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK)
+
+#define MAC_PCU_RXBUF_ADDRESS                    0x000080b4
+#define MAC_PCU_RXBUF_OFFSET                     0x000000b4
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB          11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB          11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK         0x00000800
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x)       (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB)
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x)       (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB   10
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB   0
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK  0x000007ff
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK)
+
+#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS          0x000080b8
+#define MAC_PCU_MIC_QOS_CONTROL_OFFSET           0x000000b8
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB       16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB       16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK      0x00010000
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x)    (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x)    (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB      15
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB      14
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK     0x0000c000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB      13
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB      12
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK     0x00003000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB      11
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB      10
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK     0x00000c00
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB      9
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB      8
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK     0x00000300
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB      7
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB      6
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK     0x000000c0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB      5
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB      4
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK     0x00000030
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB      3
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB      2
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK     0x0000000c
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB      1
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB      0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK     0x00000003
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x)   (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x)   (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK)
+
+#define MAC_PCU_MIC_QOS_SELECT_ADDRESS           0x000080bc
+#define MAC_PCU_MIC_QOS_SELECT_OFFSET            0x000000bc
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB       31
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB       28
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK      0xf0000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB       27
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB       24
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK      0x0f000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB       23
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB       20
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK      0x00f00000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB       19
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB       16
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK      0x000f0000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB       15
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB       12
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK      0x0000f000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB       11
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB       8
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK      0x00000f00
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB       7
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB       4
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK      0x000000f0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB       3
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB       0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK      0x0000000f
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x)    (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x)    (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK)
+
+#define MAC_PCU_MISC_MODE_ADDRESS                0x000080c0
+#define MAC_PCU_MISC_MODE_OFFSET                 0x000000c0
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB         31
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB         30
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK        0xc0000000
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x)      (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x)      (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK)
+#define MAC_PCU_MISC_MODE_SEL_EVM_MSB            27
+#define MAC_PCU_MISC_MODE_SEL_EVM_LSB            27
+#define MAC_PCU_MISC_MODE_SEL_EVM_MASK           0x08000000
+#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x)         (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB)
+#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x)         (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB     26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB     26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK    0x04000000
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x)  (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x)  (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB    25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB    25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK   0x02000000
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB          24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB          24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK         0x01000000
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x)       (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x)       (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB       21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB       21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK      0x00200000
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x)    (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x)    (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB   11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB   11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK  0x00000800
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB    10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB    10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK   0x00000400
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB      4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB      4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK     0x00000010
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x)   (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x)   (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB         3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB         3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK        0x00000008
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x)      (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x)      (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB      1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB      1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK     0x00000002
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x)   (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x)   (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB  0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB  0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK)
+
+#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS          0x000080c4
+#define MAC_PCU_FILTER_OFDM_CNT_OFFSET           0x000000c4
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB        23
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB        0
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK       0x00ffffff
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x)     (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x)     (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK)
+
+#define MAC_PCU_FILTER_CCK_CNT_ADDRESS           0x000080c8
+#define MAC_PCU_FILTER_CCK_CNT_OFFSET            0x000000c8
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB         23
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB         0
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK        0x00ffffff
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x)      (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x)      (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS            0x000080cc
+#define MAC_PCU_PHY_ERR_CNT_1_OFFSET             0x000000cc
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS       0x000080d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET        0x000000d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS            0x000080d4
+#define MAC_PCU_PHY_ERR_CNT_2_OFFSET             0x000000d4
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS       0x000080d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET        0x000000d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK)
+
+#define MAC_PCU_TSF_THRESHOLD_ADDRESS            0x000080dc
+#define MAC_PCU_TSF_THRESHOLD_OFFSET             0x000000dc
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB          15
+#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB          0
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK         0x0000ffff
+#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x)       (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB)
+#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x)       (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS      0x000080e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET       0x000000e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB    31
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB    0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK   0xffffffff
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS            0x000080e4
+#define MAC_PCU_PHY_ERR_CNT_3_OFFSET             0x000000e4
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB          23
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB          0
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK         0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x)       (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x)       (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS       0x000080e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET        0x000000e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB     31
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB     0
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK    0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x)  (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x)  (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE_ADDRESS           0x000080ec
+#define MAC_PCU_BLUETOOTH_MODE_OFFSET            0x000000ec
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB    16
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB    13
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK   0x0001e000
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB         12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB         12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK        0x00001000
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x)      (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x)      (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB          11
+#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB          10
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK         0x00000c00
+#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x)       (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x)       (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB   7
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB   0
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK  0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS        0x000080f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET         0x000000f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB  31
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB  16
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB  15
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB  0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS          0x000080f4
+#define MAC_PCU_BLUETOOTH_MODE2_OFFSET           0x000000f4
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK)
+
+#define MAC_PCU_TXSIFS_ADDRESS                   0x000080f8
+#define MAC_PCU_TXSIFS_OFFSET                    0x000000f8
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB             14
+#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB             12
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK            0x00007000
+#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x)          (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB)
+#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x)          (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK)
+#define MAC_PCU_TXSIFS_TX_LATENCY_MSB            11
+#define MAC_PCU_TXSIFS_TX_LATENCY_LSB            8
+#define MAC_PCU_TXSIFS_TX_LATENCY_MASK           0x00000f00
+#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x)         (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB)
+#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x)         (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK)
+#define MAC_PCU_TXSIFS_SIFS_TIME_MSB             7
+#define MAC_PCU_TXSIFS_SIFS_TIME_LSB             0
+#define MAC_PCU_TXSIFS_SIFS_TIME_MASK            0x000000ff
+#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x)          (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB)
+#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x)          (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK)
+
+#define MAC_PCU_TXOP_X_ADDRESS                   0x000080fc
+#define MAC_PCU_TXOP_X_OFFSET                    0x000000fc
+#define MAC_PCU_TXOP_X_VALUE_MSB                 7
+#define MAC_PCU_TXOP_X_VALUE_LSB                 0
+#define MAC_PCU_TXOP_X_VALUE_MASK                0x000000ff
+#define MAC_PCU_TXOP_X_VALUE_GET(x)              (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB)
+#define MAC_PCU_TXOP_X_VALUE_SET(x)              (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK)
+
+#define MAC_PCU_TXOP_0_3_ADDRESS                 0x00008100
+#define MAC_PCU_TXOP_0_3_OFFSET                  0x00000100
+#define MAC_PCU_TXOP_0_3_VALUE_3_MSB             31
+#define MAC_PCU_TXOP_0_3_VALUE_3_LSB             24
+#define MAC_PCU_TXOP_0_3_VALUE_3_MASK            0xff000000
+#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_2_MSB             23
+#define MAC_PCU_TXOP_0_3_VALUE_2_LSB             16
+#define MAC_PCU_TXOP_0_3_VALUE_2_MASK            0x00ff0000
+#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_1_MSB             15
+#define MAC_PCU_TXOP_0_3_VALUE_1_LSB             8
+#define MAC_PCU_TXOP_0_3_VALUE_1_MASK            0x0000ff00
+#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_0_MSB             7
+#define MAC_PCU_TXOP_0_3_VALUE_0_LSB             0
+#define MAC_PCU_TXOP_0_3_VALUE_0_MASK            0x000000ff
+#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x)          (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x)          (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK)
+
+#define MAC_PCU_TXOP_4_7_ADDRESS                 0x00008104
+#define MAC_PCU_TXOP_4_7_OFFSET                  0x00000104
+#define MAC_PCU_TXOP_4_7_VALUE_7_MSB             31
+#define MAC_PCU_TXOP_4_7_VALUE_7_LSB             24
+#define MAC_PCU_TXOP_4_7_VALUE_7_MASK            0xff000000
+#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_6_MSB             23
+#define MAC_PCU_TXOP_4_7_VALUE_6_LSB             16
+#define MAC_PCU_TXOP_4_7_VALUE_6_MASK            0x00ff0000
+#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_5_MSB             15
+#define MAC_PCU_TXOP_4_7_VALUE_5_LSB             8
+#define MAC_PCU_TXOP_4_7_VALUE_5_MASK            0x0000ff00
+#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_4_MSB             7
+#define MAC_PCU_TXOP_4_7_VALUE_4_LSB             0
+#define MAC_PCU_TXOP_4_7_VALUE_4_MASK            0x000000ff
+#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x)          (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x)          (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK)
+
+#define MAC_PCU_TXOP_8_11_ADDRESS                0x00008108
+#define MAC_PCU_TXOP_8_11_OFFSET                 0x00000108
+#define MAC_PCU_TXOP_8_11_VALUE_11_MSB           31
+#define MAC_PCU_TXOP_8_11_VALUE_11_LSB           24
+#define MAC_PCU_TXOP_8_11_VALUE_11_MASK          0xff000000
+#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x)        (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x)        (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_10_MSB           23
+#define MAC_PCU_TXOP_8_11_VALUE_10_LSB           16
+#define MAC_PCU_TXOP_8_11_VALUE_10_MASK          0x00ff0000
+#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x)        (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x)        (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_9_MSB            15
+#define MAC_PCU_TXOP_8_11_VALUE_9_LSB            8
+#define MAC_PCU_TXOP_8_11_VALUE_9_MASK           0x0000ff00
+#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x)         (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x)         (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_8_MSB            7
+#define MAC_PCU_TXOP_8_11_VALUE_8_LSB            0
+#define MAC_PCU_TXOP_8_11_VALUE_8_MASK           0x000000ff
+#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x)         (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x)         (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK)
+
+#define MAC_PCU_TXOP_12_15_ADDRESS               0x0000810c
+#define MAC_PCU_TXOP_12_15_OFFSET                0x0000010c
+#define MAC_PCU_TXOP_12_15_VALUE_15_MSB          31
+#define MAC_PCU_TXOP_12_15_VALUE_15_LSB          24
+#define MAC_PCU_TXOP_12_15_VALUE_15_MASK         0xff000000
+#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_14_MSB          23
+#define MAC_PCU_TXOP_12_15_VALUE_14_LSB          16
+#define MAC_PCU_TXOP_12_15_VALUE_14_MASK         0x00ff0000
+#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_13_MSB          15
+#define MAC_PCU_TXOP_12_15_VALUE_13_LSB          8
+#define MAC_PCU_TXOP_12_15_VALUE_13_MASK         0x0000ff00
+#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_12_MSB          7
+#define MAC_PCU_TXOP_12_15_VALUE_12_LSB          0
+#define MAC_PCU_TXOP_12_15_VALUE_12_MASK         0x000000ff
+#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x)       (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x)       (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_ADDRESS           0x00008110
+#define MAC_PCU_LOGIC_ANALYZER_OFFSET            0x00000110
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB     31
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB     18
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK    0xfffc0000
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x)  (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x)  (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB      17
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB      8
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK     0x0003ff00
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB       7
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB       4
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK      0x000000f0
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x)    (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x)    (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB        3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB        3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK       0x00000008
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x)     (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x)     (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB         2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB         2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK        0x00000004
+#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x)      (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x)      (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB         1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB         1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK        0x00000002
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x)      (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x)      (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB          0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB          0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK         0x00000001
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x)       (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x)       (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS       0x00008114
+#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET        0x00000114
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB      31
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB      0
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK     0xffffffff
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS       0x00008118
+#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET        0x00000118
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB      15
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB      0
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK     0x0000ffff
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x)   (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x)   (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS    0x0000811c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET     0x0000011c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB  23
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB  16
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB  15
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB  8
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB  7
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB  0
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK)
+
+#define MAC_PCU_AZIMUTH_MODE_ADDRESS             0x00008120
+#define MAC_PCU_AZIMUTH_MODE_OFFSET              0x00000120
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB     7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB     7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK    0x00000080
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x)  (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x)  (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB      5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB      5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK     0x00000020
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x)   (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x)   (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB          4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB          4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK         0x00000010
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x)       (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x)       (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB  1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB  1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK)
+
+#define MAC_PCU_20_40_MODE_ADDRESS               0x00008124
+#define MAC_PCU_20_40_MODE_OFFSET                0x00000124
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB       15
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB       4
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK      0x0000fff0
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x)    (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB)
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x)    (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB   1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB   1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK  0x00000002
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB   0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB   0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK  0x00000001
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK)
+
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS        0x00008128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET         0x00000128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB      31
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB      0
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK     0xffffffff
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x)   (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x)   (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK)
+
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS    0x0000812c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET     0x0000012c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB  2
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB  0
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB)
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK)
+
+#define MAC_PCU_BA_BAR_CONTROL_ADDRESS           0x00008130
+#define MAC_PCU_BA_BAR_CONTROL_OFFSET            0x00000130
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK)
+
+#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS        0x00008134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET         0x00000134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS      0x00008138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET       0x00000138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK)
+
+#define MAC_PCU_TX_TIMER_ADDRESS                 0x0000813c
+#define MAC_PCU_TX_TIMER_OFFSET                  0x0000013c
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB  25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB  25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB         24
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB         20
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK        0x01f00000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x)      (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x)      (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB          19
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB          16
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK         0x000f0000
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x)       (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x)       (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB     15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB     15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK    0x00008000
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x)  (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x)  (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_MSB            14
+#define MAC_PCU_TX_TIMER_TX_TIMER_LSB            0
+#define MAC_PCU_TX_TIMER_TX_TIMER_MASK           0x00007fff
+#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x)         (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x)         (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK)
+
+#define MAC_PCU_TXBUF_CTRL_ADDRESS               0x00008140
+#define MAC_PCU_TXBUF_CTRL_OFFSET                0x00000140
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB)
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB    11
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB    0
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK   0x00000fff
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK)
+
+#define MAC_PCU_MISC_MODE2_ADDRESS               0x00008144
+#define MAC_PCU_MISC_MODE2_OFFSET                0x00000144
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB        31
+#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB        28
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK       0xf0000000
+#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB  24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB  24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB   21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB   21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK  0x00200000
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_28676_MSB         20
+#define MAC_PCU_MISC_MODE2_BUG_28676_LSB         20
+#define MAC_PCU_MISC_MODE2_BUG_28676_MASK        0x00100000
+#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x)      (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x)      (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB   18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB   18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK  0x00040000
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB           17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB           17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK          0x00020000
+#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x)        (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x)        (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB          15
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB          8
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK         0x0000ff00
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x)       (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x)       (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB        7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB        7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK       0x00000080
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x)     (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x)     (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB        5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB        5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK       0x00000020
+#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB        3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB        3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK       0x00000008
+#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x)     (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x)     (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK)
+
+#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS        0x00008148
+#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET         0x00000148
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB        31
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB        16
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK       0xffff0000
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x)     (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB)
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x)     (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK)
+
+#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS       0x0000814c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET        0x0000014c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB     31
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB     0
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK    0xffffffff
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x)  (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB)
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x)  (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK)
+
+#define MAC_PCU_MAX_CFP_DUR_ADDRESS              0x00008150
+#define MAC_PCU_MAX_CFP_DUR_OFFSET               0x00000150
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK)
+
+#define MAC_PCU_HCF_TIMEOUT_ADDRESS              0x00008154
+#define MAC_PCU_HCF_TIMEOUT_OFFSET               0x00000154
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB            15
+#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB            0
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK           0x0000ffff
+#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x)         (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x)         (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS       0x00008158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET        0x00000158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS  0x0000815c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET   0x0000015c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS          0x00008164
+#define MAC_PCU_BLUETOOTH_MODE3_OFFSET           0x00000164
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB  27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB  27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB    26
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB    25
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK   0x06000000
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB    20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB    20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK   0x00100000
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB   15
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB   8
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK  0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS          0x00008168
+#define MAC_PCU_BLUETOOTH_MODE4_OFFSET           0x00000168
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK)
+
+#define MAC_PCU_BT_BT_ADDRESS                    0x00008200
+#define MAC_PCU_BT_BT_OFFSET                     0x00000200
+#define MAC_PCU_BT_BT_WEIGHT_MSB                 31
+#define MAC_PCU_BT_BT_WEIGHT_LSB                 0
+#define MAC_PCU_BT_BT_WEIGHT_MASK                0xffffffff
+#define MAC_PCU_BT_BT_WEIGHT_GET(x)              (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_WEIGHT_SET(x)              (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BT_BT_ASYNC_ADDRESS              0x00008300
+#define MAC_PCU_BT_BT_ASYNC_OFFSET               0x00000300
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB      15
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB      12
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK     0x0000f000
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB      11
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB      8
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK     0x00000f00
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB      7
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB      4
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK     0x000000f0
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB      3
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB      0
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK     0x0000000f
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x)   (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x)   (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_1_ADDRESS                  0x00008304
+#define MAC_PCU_BT_WL_1_OFFSET                   0x00000304
+#define MAC_PCU_BT_WL_1_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_1_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_1_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_1_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_1_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_2_ADDRESS                  0x00008308
+#define MAC_PCU_BT_WL_2_OFFSET                   0x00000308
+#define MAC_PCU_BT_WL_2_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_2_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_2_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_2_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_2_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_3_ADDRESS                  0x0000830c
+#define MAC_PCU_BT_WL_3_OFFSET                   0x0000030c
+#define MAC_PCU_BT_WL_3_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_3_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_3_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_3_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_3_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_4_ADDRESS                  0x00008310
+#define MAC_PCU_BT_WL_4_OFFSET                   0x00000310
+#define MAC_PCU_BT_WL_4_WEIGHT_MSB               31
+#define MAC_PCU_BT_WL_4_WEIGHT_LSB               0
+#define MAC_PCU_BT_WL_4_WEIGHT_MASK              0xffffffff
+#define MAC_PCU_BT_WL_4_WEIGHT_GET(x)            (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_4_WEIGHT_SET(x)            (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK)
+
+#define MAC_PCU_COEX_EPTA_ADDRESS                0x00008314
+#define MAC_PCU_COEX_EPTA_OFFSET                 0x00000314
+#define MAC_PCU_COEX_EPTA_WT_IDX_MSB             12
+#define MAC_PCU_COEX_EPTA_WT_IDX_LSB             6
+#define MAC_PCU_COEX_EPTA_WT_IDX_MASK            0x00001fc0
+#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x)          (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB)
+#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x)          (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK)
+#define MAC_PCU_COEX_EPTA_LINKID_MSB             5
+#define MAC_PCU_COEX_EPTA_LINKID_LSB             0
+#define MAC_PCU_COEX_EPTA_LINKID_MASK            0x0000003f
+#define MAC_PCU_COEX_EPTA_LINKID_GET(x)          (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB)
+#define MAC_PCU_COEX_EPTA_LINKID_SET(x)          (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS         0x00008318
+#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET          0x00000318
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS         0x0000831c
+#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET          0x0000031c
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS         0x00008320
+#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET          0x00000320
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS         0x00008324
+#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET          0x00000324
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB    31
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB    24
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK   0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB    23
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB    16
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK   0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB    15
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB    8
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK   0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB    7
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB    0
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK   0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET0_ADDRESS          0x00008328
+#define MAC_PCU_BASIC_RATE_SET0_OFFSET           0x00000328
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET1_ADDRESS          0x0000832c
+#define MAC_PCU_BASIC_RATE_SET1_OFFSET           0x0000032c
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET2_ADDRESS          0x00008330
+#define MAC_PCU_BASIC_RATE_SET2_OFFSET           0x00000330
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB        29
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK       0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET3_ADDRESS          0x00008334
+#define MAC_PCU_BASIC_RATE_SET3_OFFSET           0x00000334
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB        24
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB        0
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK       0x01ffffff
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x)     (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x)     (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS0_ADDRESS           0x00008338
+#define MAC_PCU_RX_INT_STATUS0_OFFSET            0x00000338
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB    31
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB    24
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK   0xff000000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB    23
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB    16
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK   0x00ff0000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK)
+
+#define MAC_PCU_RX_INT_STATUS1_ADDRESS           0x0000833c
+#define MAC_PCU_RX_INT_STATUS1_OFFSET            0x0000033c
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB         17
+#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK        0x0003ffff
+#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS2_ADDRESS           0x00008340
+#define MAC_PCU_RX_INT_STATUS2_OFFSET            0x00000340
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB         26
+#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK        0x07ffffff
+#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS3_ADDRESS           0x00008344
+#define MAC_PCU_RX_INT_STATUS3_OFFSET            0x00000344
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB         23
+#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB         0
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK        0x00ffffff
+#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x)      (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x)      (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK)
+
+#define HT_HALF_GI_RATE1_ADDRESS                 0x00008348
+#define HT_HALF_GI_RATE1_OFFSET                  0x00000348
+#define HT_HALF_GI_RATE1_MCS3_MSB                31
+#define HT_HALF_GI_RATE1_MCS3_LSB                24
+#define HT_HALF_GI_RATE1_MCS3_MASK               0xff000000
+#define HT_HALF_GI_RATE1_MCS3_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB)
+#define HT_HALF_GI_RATE1_MCS3_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK)
+#define HT_HALF_GI_RATE1_MCS2_MSB                23
+#define HT_HALF_GI_RATE1_MCS2_LSB                16
+#define HT_HALF_GI_RATE1_MCS2_MASK               0x00ff0000
+#define HT_HALF_GI_RATE1_MCS2_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB)
+#define HT_HALF_GI_RATE1_MCS2_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK)
+#define HT_HALF_GI_RATE1_MCS1_MSB                15
+#define HT_HALF_GI_RATE1_MCS1_LSB                8
+#define HT_HALF_GI_RATE1_MCS1_MASK               0x0000ff00
+#define HT_HALF_GI_RATE1_MCS1_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB)
+#define HT_HALF_GI_RATE1_MCS1_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK)
+#define HT_HALF_GI_RATE1_MCS0_MSB                7
+#define HT_HALF_GI_RATE1_MCS0_LSB                0
+#define HT_HALF_GI_RATE1_MCS0_MASK               0x000000ff
+#define HT_HALF_GI_RATE1_MCS0_GET(x)             (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB)
+#define HT_HALF_GI_RATE1_MCS0_SET(x)             (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK)
+
+#define HT_HALF_GI_RATE2_ADDRESS                 0x0000834c
+#define HT_HALF_GI_RATE2_OFFSET                  0x0000034c
+#define HT_HALF_GI_RATE2_MCS7_MSB                31
+#define HT_HALF_GI_RATE2_MCS7_LSB                24
+#define HT_HALF_GI_RATE2_MCS7_MASK               0xff000000
+#define HT_HALF_GI_RATE2_MCS7_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB)
+#define HT_HALF_GI_RATE2_MCS7_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK)
+#define HT_HALF_GI_RATE2_MCS6_MSB                23
+#define HT_HALF_GI_RATE2_MCS6_LSB                16
+#define HT_HALF_GI_RATE2_MCS6_MASK               0x00ff0000
+#define HT_HALF_GI_RATE2_MCS6_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB)
+#define HT_HALF_GI_RATE2_MCS6_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK)
+#define HT_HALF_GI_RATE2_MCS5_MSB                15
+#define HT_HALF_GI_RATE2_MCS5_LSB                8
+#define HT_HALF_GI_RATE2_MCS5_MASK               0x0000ff00
+#define HT_HALF_GI_RATE2_MCS5_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB)
+#define HT_HALF_GI_RATE2_MCS5_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK)
+#define HT_HALF_GI_RATE2_MCS4_MSB                7
+#define HT_HALF_GI_RATE2_MCS4_LSB                0
+#define HT_HALF_GI_RATE2_MCS4_MASK               0x000000ff
+#define HT_HALF_GI_RATE2_MCS4_GET(x)             (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB)
+#define HT_HALF_GI_RATE2_MCS4_SET(x)             (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK)
+
+#define HT_FULL_GI_RATE1_ADDRESS                 0x00008350
+#define HT_FULL_GI_RATE1_OFFSET                  0x00000350
+#define HT_FULL_GI_RATE1_MCS3_MSB                31
+#define HT_FULL_GI_RATE1_MCS3_LSB                24
+#define HT_FULL_GI_RATE1_MCS3_MASK               0xff000000
+#define HT_FULL_GI_RATE1_MCS3_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB)
+#define HT_FULL_GI_RATE1_MCS3_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK)
+#define HT_FULL_GI_RATE1_MCS2_MSB                23
+#define HT_FULL_GI_RATE1_MCS2_LSB                16
+#define HT_FULL_GI_RATE1_MCS2_MASK               0x00ff0000
+#define HT_FULL_GI_RATE1_MCS2_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB)
+#define HT_FULL_GI_RATE1_MCS2_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK)
+#define HT_FULL_GI_RATE1_MCS1_MSB                15
+#define HT_FULL_GI_RATE1_MCS1_LSB                8
+#define HT_FULL_GI_RATE1_MCS1_MASK               0x0000ff00
+#define HT_FULL_GI_RATE1_MCS1_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB)
+#define HT_FULL_GI_RATE1_MCS1_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK)
+#define HT_FULL_GI_RATE1_MCS0_MSB                7
+#define HT_FULL_GI_RATE1_MCS0_LSB                0
+#define HT_FULL_GI_RATE1_MCS0_MASK               0x000000ff
+#define HT_FULL_GI_RATE1_MCS0_GET(x)             (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB)
+#define HT_FULL_GI_RATE1_MCS0_SET(x)             (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK)
+
+#define HT_FULL_GI_RATE2_ADDRESS                 0x00008354
+#define HT_FULL_GI_RATE2_OFFSET                  0x00000354
+#define HT_FULL_GI_RATE2_MCS7_MSB                31
+#define HT_FULL_GI_RATE2_MCS7_LSB                24
+#define HT_FULL_GI_RATE2_MCS7_MASK               0xff000000
+#define HT_FULL_GI_RATE2_MCS7_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB)
+#define HT_FULL_GI_RATE2_MCS7_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK)
+#define HT_FULL_GI_RATE2_MCS6_MSB                23
+#define HT_FULL_GI_RATE2_MCS6_LSB                16
+#define HT_FULL_GI_RATE2_MCS6_MASK               0x00ff0000
+#define HT_FULL_GI_RATE2_MCS6_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB)
+#define HT_FULL_GI_RATE2_MCS6_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK)
+#define HT_FULL_GI_RATE2_MCS5_MSB                15
+#define HT_FULL_GI_RATE2_MCS5_LSB                8
+#define HT_FULL_GI_RATE2_MCS5_MASK               0x0000ff00
+#define HT_FULL_GI_RATE2_MCS5_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB)
+#define HT_FULL_GI_RATE2_MCS5_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK)
+#define HT_FULL_GI_RATE2_MCS4_MSB                7
+#define HT_FULL_GI_RATE2_MCS4_LSB                0
+#define HT_FULL_GI_RATE2_MCS4_MASK               0x000000ff
+#define HT_FULL_GI_RATE2_MCS4_GET(x)             (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB)
+#define HT_FULL_GI_RATE2_MCS4_SET(x)             (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK)
+
+#define LEGACY_RATE1_ADDRESS                     0x00008358
+#define LEGACY_RATE1_OFFSET                      0x00000358
+#define LEGACY_RATE1_RATE12_MSB                  29
+#define LEGACY_RATE1_RATE12_LSB                  24
+#define LEGACY_RATE1_RATE12_MASK                 0x3f000000
+#define LEGACY_RATE1_RATE12_GET(x)               (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB)
+#define LEGACY_RATE1_RATE12_SET(x)               (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK)
+#define LEGACY_RATE1_RATE11_MSB                  23
+#define LEGACY_RATE1_RATE11_LSB                  18
+#define LEGACY_RATE1_RATE11_MASK                 0x00fc0000
+#define LEGACY_RATE1_RATE11_GET(x)               (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB)
+#define LEGACY_RATE1_RATE11_SET(x)               (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK)
+#define LEGACY_RATE1_RATE10_MSB                  17
+#define LEGACY_RATE1_RATE10_LSB                  12
+#define LEGACY_RATE1_RATE10_MASK                 0x0003f000
+#define LEGACY_RATE1_RATE10_GET(x)               (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB)
+#define LEGACY_RATE1_RATE10_SET(x)               (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK)
+#define LEGACY_RATE1_RATE9_MSB                   11
+#define LEGACY_RATE1_RATE9_LSB                   6
+#define LEGACY_RATE1_RATE9_MASK                  0x00000fc0
+#define LEGACY_RATE1_RATE9_GET(x)                (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB)
+#define LEGACY_RATE1_RATE9_SET(x)                (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK)
+#define LEGACY_RATE1_RATE8_MSB                   5
+#define LEGACY_RATE1_RATE8_LSB                   0
+#define LEGACY_RATE1_RATE8_MASK                  0x0000003f
+#define LEGACY_RATE1_RATE8_GET(x)                (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB)
+#define LEGACY_RATE1_RATE8_SET(x)                (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK)
+
+#define LEGACY_RATE2_ADDRESS                     0x0000835c
+#define LEGACY_RATE2_OFFSET                      0x0000035c
+#define LEGACY_RATE2_RATE25_MSB                  29
+#define LEGACY_RATE2_RATE25_LSB                  24
+#define LEGACY_RATE2_RATE25_MASK                 0x3f000000
+#define LEGACY_RATE2_RATE25_GET(x)               (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB)
+#define LEGACY_RATE2_RATE25_SET(x)               (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK)
+#define LEGACY_RATE2_RATE24_MSB                  23
+#define LEGACY_RATE2_RATE24_LSB                  18
+#define LEGACY_RATE2_RATE24_MASK                 0x00fc0000
+#define LEGACY_RATE2_RATE24_GET(x)               (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB)
+#define LEGACY_RATE2_RATE24_SET(x)               (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK)
+#define LEGACY_RATE2_RATE15_MSB                  17
+#define LEGACY_RATE2_RATE15_LSB                  12
+#define LEGACY_RATE2_RATE15_MASK                 0x0003f000
+#define LEGACY_RATE2_RATE15_GET(x)               (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB)
+#define LEGACY_RATE2_RATE15_SET(x)               (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK)
+#define LEGACY_RATE2_RATE14_MSB                  11
+#define LEGACY_RATE2_RATE14_LSB                  6
+#define LEGACY_RATE2_RATE14_MASK                 0x00000fc0
+#define LEGACY_RATE2_RATE14_GET(x)               (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB)
+#define LEGACY_RATE2_RATE14_SET(x)               (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK)
+#define LEGACY_RATE2_RATE13_MSB                  5
+#define LEGACY_RATE2_RATE13_LSB                  0
+#define LEGACY_RATE2_RATE13_MASK                 0x0000003f
+#define LEGACY_RATE2_RATE13_GET(x)               (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB)
+#define LEGACY_RATE2_RATE13_SET(x)               (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK)
+
+#define LEGACY_RATE3_ADDRESS                     0x00008360
+#define LEGACY_RATE3_OFFSET                      0x00000360
+#define LEGACY_RATE3_RATE30_MSB                  29
+#define LEGACY_RATE3_RATE30_LSB                  24
+#define LEGACY_RATE3_RATE30_MASK                 0x3f000000
+#define LEGACY_RATE3_RATE30_GET(x)               (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB)
+#define LEGACY_RATE3_RATE30_SET(x)               (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK)
+#define LEGACY_RATE3_RATE29_MSB                  23
+#define LEGACY_RATE3_RATE29_LSB                  18
+#define LEGACY_RATE3_RATE29_MASK                 0x00fc0000
+#define LEGACY_RATE3_RATE29_GET(x)               (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB)
+#define LEGACY_RATE3_RATE29_SET(x)               (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK)
+#define LEGACY_RATE3_RATE28_MSB                  17
+#define LEGACY_RATE3_RATE28_LSB                  12
+#define LEGACY_RATE3_RATE28_MASK                 0x0003f000
+#define LEGACY_RATE3_RATE28_GET(x)               (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB)
+#define LEGACY_RATE3_RATE28_SET(x)               (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK)
+#define LEGACY_RATE3_RATE27_MSB                  11
+#define LEGACY_RATE3_RATE27_LSB                  6
+#define LEGACY_RATE3_RATE27_MASK                 0x00000fc0
+#define LEGACY_RATE3_RATE27_GET(x)               (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB)
+#define LEGACY_RATE3_RATE27_SET(x)               (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK)
+#define LEGACY_RATE3_RATE26_MSB                  5
+#define LEGACY_RATE3_RATE26_LSB                  0
+#define LEGACY_RATE3_RATE26_MASK                 0x0000003f
+#define LEGACY_RATE3_RATE26_GET(x)               (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB)
+#define LEGACY_RATE3_RATE26_SET(x)               (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK)
+
+#define RX_INT_FILTER_ADDRESS                    0x00008364
+#define RX_INT_FILTER_OFFSET                     0x00000364
+#define RX_INT_FILTER_BEACON_MSB                 17
+#define RX_INT_FILTER_BEACON_LSB                 17
+#define RX_INT_FILTER_BEACON_MASK                0x00020000
+#define RX_INT_FILTER_BEACON_GET(x)              (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB)
+#define RX_INT_FILTER_BEACON_SET(x)              (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK)
+#define RX_INT_FILTER_AMPDU_MSB                  16
+#define RX_INT_FILTER_AMPDU_LSB                  16
+#define RX_INT_FILTER_AMPDU_MASK                 0x00010000
+#define RX_INT_FILTER_AMPDU_GET(x)               (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB)
+#define RX_INT_FILTER_AMPDU_SET(x)               (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK)
+#define RX_INT_FILTER_EOSP_MSB                   15
+#define RX_INT_FILTER_EOSP_LSB                   15
+#define RX_INT_FILTER_EOSP_MASK                  0x00008000
+#define RX_INT_FILTER_EOSP_GET(x)                (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB)
+#define RX_INT_FILTER_EOSP_SET(x)                (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK)
+#define RX_INT_FILTER_LENGTH_LOW_MSB             14
+#define RX_INT_FILTER_LENGTH_LOW_LSB             14
+#define RX_INT_FILTER_LENGTH_LOW_MASK            0x00004000
+#define RX_INT_FILTER_LENGTH_LOW_GET(x)          (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB)
+#define RX_INT_FILTER_LENGTH_LOW_SET(x)          (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK)
+#define RX_INT_FILTER_LENGTH_HIGH_MSB            13
+#define RX_INT_FILTER_LENGTH_HIGH_LSB            13
+#define RX_INT_FILTER_LENGTH_HIGH_MASK           0x00002000
+#define RX_INT_FILTER_LENGTH_HIGH_GET(x)         (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB)
+#define RX_INT_FILTER_LENGTH_HIGH_SET(x)         (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK)
+#define RX_INT_FILTER_RSSI_MSB                   12
+#define RX_INT_FILTER_RSSI_LSB                   12
+#define RX_INT_FILTER_RSSI_MASK                  0x00001000
+#define RX_INT_FILTER_RSSI_GET(x)                (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB)
+#define RX_INT_FILTER_RSSI_SET(x)                (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK)
+#define RX_INT_FILTER_RATE_LOW_MSB               11
+#define RX_INT_FILTER_RATE_LOW_LSB               11
+#define RX_INT_FILTER_RATE_LOW_MASK              0x00000800
+#define RX_INT_FILTER_RATE_LOW_GET(x)            (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB)
+#define RX_INT_FILTER_RATE_LOW_SET(x)            (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK)
+#define RX_INT_FILTER_RATE_HIGH_MSB              10
+#define RX_INT_FILTER_RATE_HIGH_LSB              10
+#define RX_INT_FILTER_RATE_HIGH_MASK             0x00000400
+#define RX_INT_FILTER_RATE_HIGH_GET(x)           (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB)
+#define RX_INT_FILTER_RATE_HIGH_SET(x)           (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK)
+#define RX_INT_FILTER_MORE_FRAG_MSB              9
+#define RX_INT_FILTER_MORE_FRAG_LSB              9
+#define RX_INT_FILTER_MORE_FRAG_MASK             0x00000200
+#define RX_INT_FILTER_MORE_FRAG_GET(x)           (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB)
+#define RX_INT_FILTER_MORE_FRAG_SET(x)           (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK)
+#define RX_INT_FILTER_MORE_DATA_MSB              8
+#define RX_INT_FILTER_MORE_DATA_LSB              8
+#define RX_INT_FILTER_MORE_DATA_MASK             0x00000100
+#define RX_INT_FILTER_MORE_DATA_GET(x)           (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB)
+#define RX_INT_FILTER_MORE_DATA_SET(x)           (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK)
+#define RX_INT_FILTER_RETRY_MSB                  7
+#define RX_INT_FILTER_RETRY_LSB                  7
+#define RX_INT_FILTER_RETRY_MASK                 0x00000080
+#define RX_INT_FILTER_RETRY_GET(x)               (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB)
+#define RX_INT_FILTER_RETRY_SET(x)               (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK)
+#define RX_INT_FILTER_CTS_MSB                    6
+#define RX_INT_FILTER_CTS_LSB                    6
+#define RX_INT_FILTER_CTS_MASK                   0x00000040
+#define RX_INT_FILTER_CTS_GET(x)                 (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB)
+#define RX_INT_FILTER_CTS_SET(x)                 (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK)
+#define RX_INT_FILTER_ACK_MSB                    5
+#define RX_INT_FILTER_ACK_LSB                    5
+#define RX_INT_FILTER_ACK_MASK                   0x00000020
+#define RX_INT_FILTER_ACK_GET(x)                 (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB)
+#define RX_INT_FILTER_ACK_SET(x)                 (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK)
+#define RX_INT_FILTER_RTS_MSB                    4
+#define RX_INT_FILTER_RTS_LSB                    4
+#define RX_INT_FILTER_RTS_MASK                   0x00000010
+#define RX_INT_FILTER_RTS_GET(x)                 (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB)
+#define RX_INT_FILTER_RTS_SET(x)                 (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK)
+#define RX_INT_FILTER_MCAST_MSB                  3
+#define RX_INT_FILTER_MCAST_LSB                  3
+#define RX_INT_FILTER_MCAST_MASK                 0x00000008
+#define RX_INT_FILTER_MCAST_GET(x)               (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB)
+#define RX_INT_FILTER_MCAST_SET(x)               (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK)
+#define RX_INT_FILTER_BCAST_MSB                  2
+#define RX_INT_FILTER_BCAST_LSB                  2
+#define RX_INT_FILTER_BCAST_MASK                 0x00000004
+#define RX_INT_FILTER_BCAST_GET(x)               (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB)
+#define RX_INT_FILTER_BCAST_SET(x)               (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK)
+#define RX_INT_FILTER_DIRECTED_MSB               1
+#define RX_INT_FILTER_DIRECTED_LSB               1
+#define RX_INT_FILTER_DIRECTED_MASK              0x00000002
+#define RX_INT_FILTER_DIRECTED_GET(x)            (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB)
+#define RX_INT_FILTER_DIRECTED_SET(x)            (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK)
+#define RX_INT_FILTER_ENABLE_MSB                 0
+#define RX_INT_FILTER_ENABLE_LSB                 0
+#define RX_INT_FILTER_ENABLE_MASK                0x00000001
+#define RX_INT_FILTER_ENABLE_GET(x)              (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB)
+#define RX_INT_FILTER_ENABLE_SET(x)              (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK)
+
+#define RX_INT_OVERFLOW_ADDRESS                  0x00008368
+#define RX_INT_OVERFLOW_OFFSET                   0x00000368
+#define RX_INT_OVERFLOW_STATUS_MSB               0
+#define RX_INT_OVERFLOW_STATUS_LSB               0
+#define RX_INT_OVERFLOW_STATUS_MASK              0x00000001
+#define RX_INT_OVERFLOW_STATUS_GET(x)            (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB)
+#define RX_INT_OVERFLOW_STATUS_SET(x)            (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK)
+
+#define RX_FILTER_THRESH_ADDRESS                 0x0000836c
+#define RX_FILTER_THRESH_OFFSET                  0x0000036c
+#define RX_FILTER_THRESH_RSSI_LOW_MSB            23
+#define RX_FILTER_THRESH_RSSI_LOW_LSB            16
+#define RX_FILTER_THRESH_RSSI_LOW_MASK           0x00ff0000
+#define RX_FILTER_THRESH_RSSI_LOW_GET(x)         (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB)
+#define RX_FILTER_THRESH_RSSI_LOW_SET(x)         (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_LOW_MSB            15
+#define RX_FILTER_THRESH_RATE_LOW_LSB            8
+#define RX_FILTER_THRESH_RATE_LOW_MASK           0x0000ff00
+#define RX_FILTER_THRESH_RATE_LOW_GET(x)         (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB)
+#define RX_FILTER_THRESH_RATE_LOW_SET(x)         (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_HIGH_MSB           7
+#define RX_FILTER_THRESH_RATE_HIGH_LSB           0
+#define RX_FILTER_THRESH_RATE_HIGH_MASK          0x000000ff
+#define RX_FILTER_THRESH_RATE_HIGH_GET(x)        (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB)
+#define RX_FILTER_THRESH_RATE_HIGH_SET(x)        (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK)
+
+#define RX_FILTER_THRESH1_ADDRESS                0x00008370
+#define RX_FILTER_THRESH1_OFFSET                 0x00000370
+#define RX_FILTER_THRESH1_LENGTH_LOW_MSB         23
+#define RX_FILTER_THRESH1_LENGTH_LOW_LSB         12
+#define RX_FILTER_THRESH1_LENGTH_LOW_MASK        0x00fff000
+#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x)      (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB)
+#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x)      (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB        11
+#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB        0
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK       0x00000fff
+#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x)     (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x)     (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH0_ADDRESS              0x00008374
+#define RX_PRIORITY_THRESH0_OFFSET               0x00000374
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB         31
+#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB         24
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK        0xff000000
+#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x)      (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x)      (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB        23
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB        16
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK       0x00ff0000
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x)     (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x)     (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH0_RATE_LOW_MSB         15
+#define RX_PRIORITY_THRESH0_RATE_LOW_LSB         8
+#define RX_PRIORITY_THRESH0_RATE_LOW_MASK        0x0000ff00
+#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x)      (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x)      (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB        7
+#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB        0
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK       0x000000ff
+#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x)     (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x)     (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH1_ADDRESS              0x00008378
+#define RX_PRIORITY_THRESH1_OFFSET               0x00000378
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB  31
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB  24
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB       23
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB       12
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK      0x00fff000
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x)    (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x)    (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB      11
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB      0
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK     0x00000fff
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x)   (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x)   (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH2_ADDRESS              0x0000837c
+#define RX_PRIORITY_THRESH2_OFFSET               0x0000037c
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB   31
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB   24
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK  0xff000000
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB   15
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB   8
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK  0x0000ff00
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB  7
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB  0
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH3_ADDRESS              0x00008380
+#define RX_PRIORITY_THRESH3_OFFSET               0x00000380
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB   7
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB   0
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK  0x000000ff
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET0_ADDRESS              0x00008384
+#define RX_PRIORITY_OFFSET0_OFFSET               0x00000384
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB  29
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB  24
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB         23
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB         18
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK        0x00fc0000
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x)      (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x)      (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB        17
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB        12
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK       0x0003f000
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x)     (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x)     (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB     11
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB     6
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK    0x00000fc0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x)  (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x)  (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB    5
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB    0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK   0x0000003f
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET1_ADDRESS              0x00008388
+#define RX_PRIORITY_OFFSET1_OFFSET               0x00000388
+#define RX_PRIORITY_OFFSET1_RTS_MSB              29
+#define RX_PRIORITY_OFFSET1_RTS_LSB              24
+#define RX_PRIORITY_OFFSET1_RTS_MASK             0x3f000000
+#define RX_PRIORITY_OFFSET1_RTS_GET(x)           (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB)
+#define RX_PRIORITY_OFFSET1_RTS_SET(x)           (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK)
+#define RX_PRIORITY_OFFSET1_RETX_MSB             23
+#define RX_PRIORITY_OFFSET1_RETX_LSB             18
+#define RX_PRIORITY_OFFSET1_RETX_MASK            0x00fc0000
+#define RX_PRIORITY_OFFSET1_RETX_GET(x)          (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB)
+#define RX_PRIORITY_OFFSET1_RETX_SET(x)          (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB  17
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB  12
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB       11
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB       6
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK      0x00000fc0
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x)    (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x)    (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB      5
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB      0
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK     0x0000003f
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x)   (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x)   (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET2_ADDRESS              0x0000838c
+#define RX_PRIORITY_OFFSET2_OFFSET               0x0000038c
+#define RX_PRIORITY_OFFSET2_BEACON_MSB           29
+#define RX_PRIORITY_OFFSET2_BEACON_LSB           24
+#define RX_PRIORITY_OFFSET2_BEACON_MASK          0x3f000000
+#define RX_PRIORITY_OFFSET2_BEACON_GET(x)        (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB)
+#define RX_PRIORITY_OFFSET2_BEACON_SET(x)        (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK)
+#define RX_PRIORITY_OFFSET2_MGMT_MSB             23
+#define RX_PRIORITY_OFFSET2_MGMT_LSB             18
+#define RX_PRIORITY_OFFSET2_MGMT_MASK            0x00fc0000
+#define RX_PRIORITY_OFFSET2_MGMT_GET(x)          (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB)
+#define RX_PRIORITY_OFFSET2_MGMT_SET(x)          (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK)
+#define RX_PRIORITY_OFFSET2_ATIM_MSB             17
+#define RX_PRIORITY_OFFSET2_ATIM_LSB             12
+#define RX_PRIORITY_OFFSET2_ATIM_MASK            0x0003f000
+#define RX_PRIORITY_OFFSET2_ATIM_GET(x)          (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB)
+#define RX_PRIORITY_OFFSET2_ATIM_SET(x)          (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK)
+#define RX_PRIORITY_OFFSET2_PRESP_MSB            11
+#define RX_PRIORITY_OFFSET2_PRESP_LSB            6
+#define RX_PRIORITY_OFFSET2_PRESP_MASK           0x00000fc0
+#define RX_PRIORITY_OFFSET2_PRESP_GET(x)         (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB)
+#define RX_PRIORITY_OFFSET2_PRESP_SET(x)         (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK)
+#define RX_PRIORITY_OFFSET2_XCAST_MSB            5
+#define RX_PRIORITY_OFFSET2_XCAST_LSB            0
+#define RX_PRIORITY_OFFSET2_XCAST_MASK           0x0000003f
+#define RX_PRIORITY_OFFSET2_XCAST_GET(x)         (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB)
+#define RX_PRIORITY_OFFSET2_XCAST_SET(x)         (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK)
+
+#define RX_PRIORITY_OFFSET3_ADDRESS              0x00008390
+#define RX_PRIORITY_OFFSET3_OFFSET               0x00000390
+#define RX_PRIORITY_OFFSET3_PS_POLL_MSB          29
+#define RX_PRIORITY_OFFSET3_PS_POLL_LSB          24
+#define RX_PRIORITY_OFFSET3_PS_POLL_MASK         0x3f000000
+#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x)       (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB)
+#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x)       (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK)
+#define RX_PRIORITY_OFFSET3_AMSDU_MSB            23
+#define RX_PRIORITY_OFFSET3_AMSDU_LSB            18
+#define RX_PRIORITY_OFFSET3_AMSDU_MASK           0x00fc0000
+#define RX_PRIORITY_OFFSET3_AMSDU_GET(x)         (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMSDU_SET(x)         (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK)
+#define RX_PRIORITY_OFFSET3_AMPDU_MSB            17
+#define RX_PRIORITY_OFFSET3_AMPDU_LSB            12
+#define RX_PRIORITY_OFFSET3_AMPDU_MASK           0x0003f000
+#define RX_PRIORITY_OFFSET3_AMPDU_GET(x)         (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMPDU_SET(x)         (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK)
+#define RX_PRIORITY_OFFSET3_EOSP_MSB             11
+#define RX_PRIORITY_OFFSET3_EOSP_LSB             6
+#define RX_PRIORITY_OFFSET3_EOSP_MASK            0x00000fc0
+#define RX_PRIORITY_OFFSET3_EOSP_GET(x)          (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB)
+#define RX_PRIORITY_OFFSET3_EOSP_SET(x)          (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK)
+#define RX_PRIORITY_OFFSET3_MORE_MSB             5
+#define RX_PRIORITY_OFFSET3_MORE_LSB             0
+#define RX_PRIORITY_OFFSET3_MORE_MASK            0x0000003f
+#define RX_PRIORITY_OFFSET3_MORE_GET(x)          (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB)
+#define RX_PRIORITY_OFFSET3_MORE_SET(x)          (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK)
+
+#define RX_PRIORITY_OFFSET4_ADDRESS              0x00008394
+#define RX_PRIORITY_OFFSET4_OFFSET               0x00000394
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB   23
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB   18
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK  0x00fc0000
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB      17
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB      12
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK     0x0003f000
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x)   (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x)   (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK)
+#define RX_PRIORITY_OFFSET4_NULL_MSB             11
+#define RX_PRIORITY_OFFSET4_NULL_LSB             6
+#define RX_PRIORITY_OFFSET4_NULL_MASK            0x00000fc0
+#define RX_PRIORITY_OFFSET4_NULL_GET(x)          (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB)
+#define RX_PRIORITY_OFFSET4_NULL_SET(x)          (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK)
+#define RX_PRIORITY_OFFSET4_PREQ_MSB             5
+#define RX_PRIORITY_OFFSET4_PREQ_LSB             0
+#define RX_PRIORITY_OFFSET4_PREQ_MASK            0x0000003f
+#define RX_PRIORITY_OFFSET4_PREQ_GET(x)          (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB)
+#define RX_PRIORITY_OFFSET4_PREQ_SET(x)          (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK)
+
+#define RX_PRIORITY_OFFSET5_ADDRESS              0x00008398
+#define RX_PRIORITY_OFFSET5_OFFSET               0x00000398
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB   11
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB   6
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK  0x00000fc0
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB   5
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB   0
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK  0x0000003f
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK)
+
+#define MAC_PCU_BSSID2_L32_ADDRESS               0x0000839c
+#define MAC_PCU_BSSID2_L32_OFFSET                0x0000039c
+#define MAC_PCU_BSSID2_L32_ADDR_MSB              31
+#define MAC_PCU_BSSID2_L32_ADDR_LSB              0
+#define MAC_PCU_BSSID2_L32_ADDR_MASK             0xffffffff
+#define MAC_PCU_BSSID2_L32_ADDR_GET(x)           (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB)
+#define MAC_PCU_BSSID2_L32_ADDR_SET(x)           (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID2_U16_ADDRESS               0x000083a0
+#define MAC_PCU_BSSID2_U16_OFFSET                0x000003a0
+#define MAC_PCU_BSSID2_U16_ENABLE_MSB            16
+#define MAC_PCU_BSSID2_U16_ENABLE_LSB            16
+#define MAC_PCU_BSSID2_U16_ENABLE_MASK           0x00010000
+#define MAC_PCU_BSSID2_U16_ENABLE_GET(x)         (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB)
+#define MAC_PCU_BSSID2_U16_ENABLE_SET(x)         (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK)
+#define MAC_PCU_BSSID2_U16_ADDR_MSB              15
+#define MAC_PCU_BSSID2_U16_ADDR_LSB              0
+#define MAC_PCU_BSSID2_U16_ADDR_MASK             0x0000ffff
+#define MAC_PCU_BSSID2_U16_ADDR_GET(x)           (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB)
+#define MAC_PCU_BSSID2_U16_ADDR_SET(x)           (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK)
+
+#define MAC_PCU_TSF1_STATUS_L32_ADDRESS          0x000083a4
+#define MAC_PCU_TSF1_STATUS_L32_OFFSET           0x000003a4
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB        31
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB        0
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x)     (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x)     (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF1_STATUS_U32_ADDRESS          0x000083a8
+#define MAC_PCU_TSF1_STATUS_U32_OFFSET           0x000003a8
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB        31
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB        0
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x)     (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x)     (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_L32_ADDRESS          0x000083ac
+#define MAC_PCU_TSF2_STATUS_L32_OFFSET           0x000003ac
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB        31
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB        0
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x)     (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x)     (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_U32_ADDRESS          0x000083b0
+#define MAC_PCU_TSF2_STATUS_U32_OFFSET           0x000003b0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB        31
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB        0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK       0xffffffff
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x)     (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x)     (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TXBUF_BA_ADDRESS                 0x00008400
+#define MAC_PCU_TXBUF_BA_OFFSET                  0x00000400
+#define MAC_PCU_TXBUF_BA_DATA_MSB                31
+#define MAC_PCU_TXBUF_BA_DATA_LSB                0
+#define MAC_PCU_TXBUF_BA_DATA_MASK               0xffffffff
+#define MAC_PCU_TXBUF_BA_DATA_GET(x)             (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB)
+#define MAC_PCU_TXBUF_BA_DATA_SET(x)             (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK)
+
+#define MAC_PCU_KEY_CACHE_1_ADDRESS              0x00008800
+#define MAC_PCU_KEY_CACHE_1_OFFSET               0x00000800
+#define MAC_PCU_KEY_CACHE_1_DATA_MSB             31
+#define MAC_PCU_KEY_CACHE_1_DATA_LSB             0
+#define MAC_PCU_KEY_CACHE_1_DATA_MASK            0xffffffff
+#define MAC_PCU_KEY_CACHE_1_DATA_GET(x)          (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB)
+#define MAC_PCU_KEY_CACHE_1_DATA_SET(x)          (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_0_ADDRESS               0x00009800
+#define MAC_PCU_BASEBAND_0_OFFSET                0x00001800
+#define MAC_PCU_BASEBAND_0_DATA_MSB              31
+#define MAC_PCU_BASEBAND_0_DATA_LSB              0
+#define MAC_PCU_BASEBAND_0_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_0_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB)
+#define MAC_PCU_BASEBAND_0_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_1_ADDRESS               0x0000a000
+#define MAC_PCU_BASEBAND_1_OFFSET                0x00002000
+#define MAC_PCU_BASEBAND_1_DATA_MSB              31
+#define MAC_PCU_BASEBAND_1_DATA_LSB              0
+#define MAC_PCU_BASEBAND_1_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_1_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB)
+#define MAC_PCU_BASEBAND_1_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_2_ADDRESS               0x0000c000
+#define MAC_PCU_BASEBAND_2_OFFSET                0x00004000
+#define MAC_PCU_BASEBAND_2_DATA_MSB              31
+#define MAC_PCU_BASEBAND_2_DATA_LSB              0
+#define MAC_PCU_BASEBAND_2_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_2_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB)
+#define MAC_PCU_BASEBAND_2_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_3_ADDRESS               0x0000d000
+#define MAC_PCU_BASEBAND_3_OFFSET                0x00005000
+#define MAC_PCU_BASEBAND_3_DATA_MSB              31
+#define MAC_PCU_BASEBAND_3_DATA_LSB              0
+#define MAC_PCU_BASEBAND_3_DATA_MASK             0xffffffff
+#define MAC_PCU_BASEBAND_3_DATA_GET(x)           (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB)
+#define MAC_PCU_BASEBAND_3_DATA_SET(x)           (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK)
+
+#define MAC_PCU_BUF_ADDRESS                      0x0000e000
+#define MAC_PCU_BUF_OFFSET                       0x00006000
+#define MAC_PCU_BUF_DATA_MSB                     31
+#define MAC_PCU_BUF_DATA_LSB                     0
+#define MAC_PCU_BUF_DATA_MASK                    0xffffffff
+#define MAC_PCU_BUF_DATA_GET(x)                  (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB)
+#define MAC_PCU_BUF_DATA_SET(x)                  (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mac_pcu_reg_s {
+  volatile unsigned int mac_pcu_sta_addr_l32;
+  volatile unsigned int mac_pcu_sta_addr_u16;
+  volatile unsigned int mac_pcu_bssid_l32;
+  volatile unsigned int mac_pcu_bssid_u16;
+  volatile unsigned int mac_pcu_bcn_rssi_ave;
+  volatile unsigned int mac_pcu_ack_cts_timeout;
+  volatile unsigned int mac_pcu_bcn_rssi_ctl;
+  volatile unsigned int mac_pcu_usec_latency;
+  volatile unsigned int pcu_max_cfp_dur;
+  volatile unsigned int mac_pcu_rx_filter;
+  volatile unsigned int mac_pcu_mcast_filter_l32;
+  volatile unsigned int mac_pcu_mcast_filter_u32;
+  volatile unsigned int mac_pcu_diag_sw;
+  volatile unsigned int mac_pcu_tst_addac;
+  volatile unsigned int mac_pcu_def_antenna;
+  volatile unsigned int mac_pcu_aes_mute_mask_0;
+  volatile unsigned int mac_pcu_aes_mute_mask_1;
+  volatile unsigned int mac_pcu_gated_clks;
+  volatile unsigned int mac_pcu_obs_bus_2;
+  volatile unsigned int mac_pcu_obs_bus_1;
+  volatile unsigned int mac_pcu_dym_mimo_pwr_save;
+  volatile unsigned int mac_pcu_last_beacon_tsf;
+  volatile unsigned int mac_pcu_nav;
+  volatile unsigned int mac_pcu_rts_success_cnt;
+  volatile unsigned int mac_pcu_rts_fail_cnt;
+  volatile unsigned int mac_pcu_ack_fail_cnt;
+  volatile unsigned int mac_pcu_fcs_fail_cnt;
+  volatile unsigned int mac_pcu_beacon_cnt;
+  volatile unsigned int mac_pcu_xrmode;
+  volatile unsigned int mac_pcu_xrdel;
+  volatile unsigned int mac_pcu_xrto;
+  volatile unsigned int mac_pcu_xrcrp;
+  volatile unsigned int mac_pcu_xrstmp;
+  volatile unsigned int mac_pcu_addr1_mask_l32;
+  volatile unsigned int mac_pcu_addr1_mask_u16;
+  volatile unsigned int mac_pcu_tpc;
+  volatile unsigned int mac_pcu_tx_frame_cnt;
+  volatile unsigned int mac_pcu_rx_frame_cnt;
+  volatile unsigned int mac_pcu_rx_clear_cnt;
+  volatile unsigned int mac_pcu_cycle_cnt;
+  volatile unsigned int mac_pcu_quiet_time_1;
+  volatile unsigned int mac_pcu_quiet_time_2;
+  volatile unsigned int mac_pcu_qos_no_ack;
+  volatile unsigned int mac_pcu_phy_error_mask;
+  volatile unsigned int mac_pcu_xrlat;
+  volatile unsigned int mac_pcu_rxbuf;
+  volatile unsigned int mac_pcu_mic_qos_control;
+  volatile unsigned int mac_pcu_mic_qos_select;
+  volatile unsigned int mac_pcu_misc_mode;
+  volatile unsigned int mac_pcu_filter_ofdm_cnt;
+  volatile unsigned int mac_pcu_filter_cck_cnt;
+  volatile unsigned int mac_pcu_phy_err_cnt_1;
+  volatile unsigned int mac_pcu_phy_err_cnt_1_mask;
+  volatile unsigned int mac_pcu_phy_err_cnt_2;
+  volatile unsigned int mac_pcu_phy_err_cnt_2_mask;
+  volatile unsigned int mac_pcu_tsf_threshold;
+  volatile unsigned int mac_pcu_phy_error_eifs_mask;
+  volatile unsigned int mac_pcu_phy_err_cnt_3;
+  volatile unsigned int mac_pcu_phy_err_cnt_3_mask;
+  volatile unsigned int mac_pcu_bluetooth_mode;
+  volatile unsigned int mac_pcu_bluetooth_weights;
+  volatile unsigned int mac_pcu_bluetooth_mode2;
+  volatile unsigned int mac_pcu_txsifs;
+  volatile unsigned int mac_pcu_txop_x;
+  volatile unsigned int mac_pcu_txop_0_3;
+  volatile unsigned int mac_pcu_txop_4_7;
+  volatile unsigned int mac_pcu_txop_8_11;
+  volatile unsigned int mac_pcu_txop_12_15;
+  volatile unsigned int mac_pcu_logic_analyzer;
+  volatile unsigned int mac_pcu_logic_analyzer_32l;
+  volatile unsigned int mac_pcu_logic_analyzer_16u;
+  volatile unsigned int mac_pcu_phy_err_cnt_mask_cont;
+  volatile unsigned int mac_pcu_azimuth_mode;
+  volatile unsigned int mac_pcu_20_40_mode;
+  volatile unsigned int mac_pcu_rx_clear_diff_cnt;
+  volatile unsigned int mac_pcu_self_gen_antenna_mask;
+  volatile unsigned int mac_pcu_ba_bar_control;
+  volatile unsigned int mac_pcu_legacy_plcp_spoof;
+  volatile unsigned int mac_pcu_phy_error_mask_cont;
+  volatile unsigned int mac_pcu_tx_timer;
+  volatile unsigned int mac_pcu_txbuf_ctrl;
+  volatile unsigned int mac_pcu_misc_mode2;
+  volatile unsigned int mac_pcu_alt_aes_mute_mask;
+  volatile unsigned int mac_pcu_azimuth_time_stamp;
+  volatile unsigned int mac_pcu_max_cfp_dur;
+  volatile unsigned int mac_pcu_hcf_timeout;
+  volatile unsigned int mac_pcu_bluetooth_weights2;
+  volatile unsigned int mac_pcu_bluetooth_tsf_bt_active;
+  volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority;
+  volatile unsigned int mac_pcu_bluetooth_mode3;
+  volatile unsigned int mac_pcu_bluetooth_mode4;
+  unsigned char pad0[148]; /* pad to 0x200 */
+  volatile unsigned int mac_pcu_bt_bt[64];
+  volatile unsigned int mac_pcu_bt_bt_async;
+  volatile unsigned int mac_pcu_bt_wl_1;
+  volatile unsigned int mac_pcu_bt_wl_2;
+  volatile unsigned int mac_pcu_bt_wl_3;
+  volatile unsigned int mac_pcu_bt_wl_4;
+  volatile unsigned int mac_pcu_coex_epta;
+  volatile unsigned int mac_pcu_coex_lnamaxgain1;
+  volatile unsigned int mac_pcu_coex_lnamaxgain2;
+  volatile unsigned int mac_pcu_coex_lnamaxgain3;
+  volatile unsigned int mac_pcu_coex_lnamaxgain4;
+  volatile unsigned int mac_pcu_basic_rate_set0;
+  volatile unsigned int mac_pcu_basic_rate_set1;
+  volatile unsigned int mac_pcu_basic_rate_set2;
+  volatile unsigned int mac_pcu_basic_rate_set3;
+  volatile unsigned int mac_pcu_rx_int_status0;
+  volatile unsigned int mac_pcu_rx_int_status1;
+  volatile unsigned int mac_pcu_rx_int_status2;
+  volatile unsigned int mac_pcu_rx_int_status3;
+  volatile unsigned int ht_half_gi_rate1;
+  volatile unsigned int ht_half_gi_rate2;
+  volatile unsigned int ht_full_gi_rate1;
+  volatile unsigned int ht_full_gi_rate2;
+  volatile unsigned int legacy_rate1;
+  volatile unsigned int legacy_rate2;
+  volatile unsigned int legacy_rate3;
+  volatile unsigned int rx_int_filter;
+  volatile unsigned int rx_int_overflow;
+  volatile unsigned int rx_filter_thresh;
+  volatile unsigned int rx_filter_thresh1;
+  volatile unsigned int rx_priority_thresh0;
+  volatile unsigned int rx_priority_thresh1;
+  volatile unsigned int rx_priority_thresh2;
+  volatile unsigned int rx_priority_thresh3;
+  volatile unsigned int rx_priority_offset0;
+  volatile unsigned int rx_priority_offset1;
+  volatile unsigned int rx_priority_offset2;
+  volatile unsigned int rx_priority_offset3;
+  volatile unsigned int rx_priority_offset4;
+  volatile unsigned int rx_priority_offset5;
+  volatile unsigned int mac_pcu_bssid2_l32;
+  volatile unsigned int mac_pcu_bssid2_u16;
+  volatile unsigned int mac_pcu_tsf1_status_l32;
+  volatile unsigned int mac_pcu_tsf1_status_u32;
+  volatile unsigned int mac_pcu_tsf2_status_l32;
+  volatile unsigned int mac_pcu_tsf2_status_u32;
+  unsigned char pad1[76]; /* pad to 0x400 */
+  volatile unsigned int mac_pcu_txbuf_ba[64];
+  unsigned char pad2[768]; /* pad to 0x800 */
+  volatile unsigned int mac_pcu_key_cache_1[256];
+  unsigned char pad3[3072]; /* pad to 0x1800 */
+  volatile unsigned int mac_pcu_baseband_0[512];
+  volatile unsigned int mac_pcu_baseband_1[2048];
+  volatile unsigned int mac_pcu_baseband_2[1024];
+  volatile unsigned int mac_pcu_baseband_3[1024];
+  volatile unsigned int mac_pcu_buf[512];
+} mac_pcu_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MAC_PCU_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..e84e2e011ca2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_host_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h
new file mode 100644
index 000000000000..2ac8528987d4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h
@@ -0,0 +1,556 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
+#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
+#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
+#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
+#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
+#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
+#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
+#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
+#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
+#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
+#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
+#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
+#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
+#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
+#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
+#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
+#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
+#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
+#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
+#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
+#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
+#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
+#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
+#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
+#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
+#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
+#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
+#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
+#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
+#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
+#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
+#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
+#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
+#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
+#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
+#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
+#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
+#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
+#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
+#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
+#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
+#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
+#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
+#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
+#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
+#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
+#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
+#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
+#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
+#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
+#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
+#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
+#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
+#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
+#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
+#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
+#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
+#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
+#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
+#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
+#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
+#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
+#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
+#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
+#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
+#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
+#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
+#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
+#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
+#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
+#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
+#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
+#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
+#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
+#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
+#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
+#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
+#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
+#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
+#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
+#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
+#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
+#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
+#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
+#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
+#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
+#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
+#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
+#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
+#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
+#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
+#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
+#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
+#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
+#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
+#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
+#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
+#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
+#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
+#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
+#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
+#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
+#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
+#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
+#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
+#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
+#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
+#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
+#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
+#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
+#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
+#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
+#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
+#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
+#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
+#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
+#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
+#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
+#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
+#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
+#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
+#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
+#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
+#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
+#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
+#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
+#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
+#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
+#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
+#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
+#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
+#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
+#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
+#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
+#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
+#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
+#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
+#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
+#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
+#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
+#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
+#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
+#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
+#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
+#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
+#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
+#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
+#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
+#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
+#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
+#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
+#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
+#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
+#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
+#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
+#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
+#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
+#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
new file mode 100644
index 000000000000..dbad49ea0a01
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
@@ -0,0 +1,518 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_HOST_REG_REG_H_
+#define _MBOX_WLAN_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS                  0x00000400
+#define HOST_INT_STATUS_OFFSET                   0x00000400
+#define HOST_INT_STATUS_ERROR_MSB                7
+#define HOST_INT_STATUS_ERROR_LSB                7
+#define HOST_INT_STATUS_ERROR_MASK               0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB                  6
+#define HOST_INT_STATUS_CPU_LSB                  6
+#define HOST_INT_STATUS_CPU_MASK                 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_INT_MSB                  5
+#define HOST_INT_STATUS_INT_LSB                  5
+#define HOST_INT_STATUS_INT_MASK                 0x00000020
+#define HOST_INT_STATUS_INT_GET(x)               (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
+#define HOST_INT_STATUS_INT_SET(x)               (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB              4
+#define HOST_INT_STATUS_COUNTER_LSB              4
+#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB            3
+#define HOST_INT_STATUS_MBOX_DATA_LSB            0
+#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS                   0x00000401
+#define CPU_INT_STATUS_OFFSET                    0x00000401
+#define CPU_INT_STATUS_BIT_MSB                   7
+#define CPU_INT_STATUS_BIT_LSB                   0
+#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS                 0x00000402
+#define ERROR_INT_STATUS_OFFSET                  0x00000402
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_SPI_MSB                 3
+#define ERROR_INT_STATUS_SPI_LSB                 3
+#define ERROR_INT_STATUS_SPI_MASK                0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB              2
+#define ERROR_INT_STATUS_WAKEUP_LSB              2
+#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS               0x00000403
+#define COUNTER_INT_STATUS_OFFSET                0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB           7
+#define COUNTER_INT_STATUS_COUNTER_LSB           0
+#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS                       0x00000404
+#define MBOX_FRAME_OFFSET                        0x00000404
+#define MBOX_FRAME_RX_EOM_MSB                    7
+#define MBOX_FRAME_RX_EOM_LSB                    4
+#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB                    3
+#define MBOX_FRAME_RX_SOM_LSB                    0
+#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define HOST_INT_STATUS2_ADDRESS                 0x00000406
+#define HOST_INT_STATUS2_OFFSET                  0x00000406
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB  2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB  2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB   1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB   1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK  0x00000002
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_DATA_MSB          0
+#define HOST_INT_STATUS2_GMBOX_DATA_LSB          0
+#define HOST_INT_STATUS2_GMBOX_DATA_MASK         0x00000001
+#define HOST_INT_STATUS2_GMBOX_DATA_GET(x)       (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
+#define HOST_INT_STATUS2_GMBOX_DATA_SET(x)       (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_AVAIL_ADDRESS                   0x00000407
+#define GMBOX_RX_AVAIL_OFFSET                    0x00000407
+#define GMBOX_RX_AVAIL_BYTE_MSB                  6
+#define GMBOX_RX_AVAIL_BYTE_LSB                  0
+#define GMBOX_RX_AVAIL_BYTE_MASK                 0x0000007f
+#define GMBOX_RX_AVAIL_BYTE_GET(x)               (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
+#define GMBOX_RX_AVAIL_BYTE_SET(x)               (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
+#define RX_LOOKAHEAD0_OFFSET                     0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB                   7
+#define RX_LOOKAHEAD0_DATA_LSB                   0
+#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
+#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB                   7
+#define RX_LOOKAHEAD1_DATA_LSB                   0
+#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
+#define RX_LOOKAHEAD2_OFFSET                     0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB                   7
+#define RX_LOOKAHEAD2_DATA_LSB                   0
+#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
+#define RX_LOOKAHEAD3_OFFSET                     0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB                   7
+#define RX_LOOKAHEAD3_DATA_LSB                   0
+#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS                0x00000418
+#define INT_STATUS_ENABLE_OFFSET                 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB              7
+#define INT_STATUS_ENABLE_ERROR_LSB              7
+#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB                6
+#define INT_STATUS_ENABLE_CPU_LSB                6
+#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_INT_MSB                5
+#define INT_STATUS_ENABLE_INT_LSB                5
+#define INT_STATUS_ENABLE_INT_MASK               0x00000020
+#define INT_STATUS_ENABLE_INT_GET(x)             (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
+#define INT_STATUS_ENABLE_INT_SET(x)             (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB            4
+#define INT_STATUS_ENABLE_COUNTER_LSB            4
+#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS                            0x00000420
+#define COUNT_OFFSET                             0x00000420
+#define COUNT_VALUE_MSB                          7
+#define COUNT_VALUE_LSB                          0
+#define COUNT_VALUE_MASK                         0x000000ff
+#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS                        0x00000440
+#define COUNT_DEC_OFFSET                         0x00000440
+#define COUNT_DEC_VALUE_MSB                      7
+#define COUNT_DEC_VALUE_LSB                      0
+#define COUNT_DEC_VALUE_MASK                     0x000000ff
+#define COUNT_DEC_VALUE_GET(x)                   (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x)                   (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS                          0x00000460
+#define SCRATCH_OFFSET                           0x00000460
+#define SCRATCH_VALUE_MSB                        7
+#define SCRATCH_VALUE_LSB                        0
+#define SCRATCH_VALUE_MASK                       0x000000ff
+#define SCRATCH_VALUE_GET(x)                     (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x)                     (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS                     0x00000468
+#define FIFO_TIMEOUT_OFFSET                      0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB                   7
+#define FIFO_TIMEOUT_VALUE_LSB                   0
+#define FIFO_TIMEOUT_VALUE_MASK                  0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x)                (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x)                (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS              0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET               0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB              0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK             0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x)           (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x)           (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS                    0x0000046a
+#define DISABLE_SLEEP_OFFSET                     0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB                1
+#define DISABLE_SLEEP_FOR_INT_LSB                1
+#define DISABLE_SLEEP_FOR_INT_MASK               0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x)             (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x)             (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB                     0
+#define DISABLE_SLEEP_ON_LSB                     0
+#define DISABLE_SLEEP_ON_MASK                    0x00000001
+#define DISABLE_SLEEP_ON_GET(x)                  (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x)                  (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS                        0x00000470
+#define LOCAL_BUS_OFFSET                         0x00000470
+#define LOCAL_BUS_STATE_MSB                      1
+#define LOCAL_BUS_STATE_LSB                      0
+#define LOCAL_BUS_STATE_MASK                     0x00000003
+#define LOCAL_BUS_STATE_GET(x)                   (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x)                   (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS                         0x00000472
+#define INT_WLAN_OFFSET                          0x00000472
+#define INT_WLAN_VECTOR_MSB                      7
+#define INT_WLAN_VECTOR_LSB                      0
+#define INT_WLAN_VECTOR_MASK                     0x000000ff
+#define INT_WLAN_VECTOR_GET(x)                   (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x)                   (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS                      0x00000474
+#define WINDOW_DATA_OFFSET                       0x00000474
+#define WINDOW_DATA_DATA_MSB                     7
+#define WINDOW_DATA_DATA_LSB                     0
+#define WINDOW_DATA_DATA_MASK                    0x000000ff
+#define WINDOW_DATA_DATA_GET(x)                  (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x)                  (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET                 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB               7
+#define WINDOW_WRITE_ADDR_ADDR_LSB               0
+#define WINDOW_WRITE_ADDR_ADDR_MASK              0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x)            (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x)            (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET                  0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB                7
+#define WINDOW_READ_ADDR_ADDR_LSB                0
+#define WINDOW_READ_ADDR_ADDR_MASK               0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x)             (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x)             (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define HOST_CTRL_SPI_CONFIG_ADDRESS             0x00000480
+#define HOST_CTRL_SPI_CONFIG_OFFSET              0x00000480
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB       4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB       4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK      0x00000010
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB       2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB       2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK      0x00000004
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB       1
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB       0
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK      0x00000003
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x)    (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x)    (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
+
+#define HOST_CTRL_SPI_STATUS_ADDRESS             0x00000481
+#define HOST_CTRL_SPI_STATUS_OFFSET              0x00000481
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB        3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB        3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK       0x00000008
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x)     (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x)     (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB          2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB          2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK         0x00000004
+#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x)       (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x)       (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB          1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB          1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK         0x00000002
+#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x)       (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x)       (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_READY_MSB           0
+#define HOST_CTRL_SPI_STATUS_READY_LSB           0
+#define HOST_CTRL_SPI_STATUS_READY_MASK          0x00000001
+#define HOST_CTRL_SPI_STATUS_READY_GET(x)        (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
+#define HOST_CTRL_SPI_STATUS_READY_SET(x)        (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS               0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET                0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB               0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK              0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x)            (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x)            (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CPU_DBG_SEL_ADDRESS                      0x00000483
+#define CPU_DBG_SEL_OFFSET                       0x00000483
+#define CPU_DBG_SEL_BIT_MSB                      5
+#define CPU_DBG_SEL_BIT_LSB                      0
+#define CPU_DBG_SEL_BIT_MASK                     0x0000003f
+#define CPU_DBG_SEL_BIT_GET(x)                   (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
+#define CPU_DBG_SEL_BIT_SET(x)                   (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
+
+#define CPU_DBG_ADDRESS                          0x00000484
+#define CPU_DBG_OFFSET                           0x00000484
+#define CPU_DBG_DATA_MSB                         7
+#define CPU_DBG_DATA_LSB                         0
+#define CPU_DBG_DATA_MASK                        0x000000ff
+#define CPU_DBG_DATA_GET(x)                      (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
+#define CPU_DBG_DATA_SET(x)                      (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
+
+#define INT_STATUS2_ENABLE_ADDRESS               0x00000488
+#define INT_STATUS2_ENABLE_OFFSET                0x00000488
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB        0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB        0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK       0x00000001
+#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x)     (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x)     (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_ADDRESS               0x00000490
+#define GMBOX_RX_LOOKAHEAD_OFFSET                0x00000490
+#define GMBOX_RX_LOOKAHEAD_DATA_MSB              7
+#define GMBOX_RX_LOOKAHEAD_DATA_LSB              0
+#define GMBOX_RX_LOOKAHEAD_DATA_MASK             0x000000ff
+#define GMBOX_RX_LOOKAHEAD_DATA_GET(x)           (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
+#define GMBOX_RX_LOOKAHEAD_DATA_SET(x)           (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS           0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET            0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB           0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB           0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK          0x00000001
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x)        (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x)        (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
+
+#define CIS_WINDOW_ADDRESS                       0x00000600
+#define CIS_WINDOW_OFFSET                        0x00000600
+#define CIS_WINDOW_DATA_MSB                      7
+#define CIS_WINDOW_DATA_LSB                      0
+#define CIS_WINDOW_DATA_MASK                     0x000000ff
+#define CIS_WINDOW_DATA_GET(x)                   (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x)                   (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_host_reg_reg_s {
+  unsigned char pad0[1024]; /* pad to 0x400 */
+  volatile unsigned char host_int_status;
+  volatile unsigned char cpu_int_status;
+  volatile unsigned char error_int_status;
+  volatile unsigned char counter_int_status;
+  volatile unsigned char mbox_frame;
+  volatile unsigned char rx_lookahead_valid;
+  volatile unsigned char host_int_status2;
+  volatile unsigned char gmbox_rx_avail;
+  volatile unsigned char rx_lookahead0[4];
+  volatile unsigned char rx_lookahead1[4];
+  volatile unsigned char rx_lookahead2[4];
+  volatile unsigned char rx_lookahead3[4];
+  volatile unsigned char int_status_enable;
+  volatile unsigned char cpu_int_status_enable;
+  volatile unsigned char error_status_enable;
+  volatile unsigned char counter_int_status_enable;
+  unsigned char pad1[4]; /* pad to 0x420 */
+  volatile unsigned char count[8];
+  unsigned char pad2[24]; /* pad to 0x440 */
+  volatile unsigned char count_dec[32];
+  volatile unsigned char scratch[8];
+  volatile unsigned char fifo_timeout;
+  volatile unsigned char fifo_timeout_enable;
+  volatile unsigned char disable_sleep;
+  unsigned char pad3[5]; /* pad to 0x470 */
+  volatile unsigned char local_bus;
+  unsigned char pad4[1]; /* pad to 0x472 */
+  volatile unsigned char int_wlan;
+  unsigned char pad5[1]; /* pad to 0x474 */
+  volatile unsigned char window_data[4];
+  volatile unsigned char window_write_addr[4];
+  volatile unsigned char window_read_addr[4];
+  volatile unsigned char host_ctrl_spi_config;
+  volatile unsigned char host_ctrl_spi_status;
+  volatile unsigned char non_assoc_sleep_en;
+  volatile unsigned char cpu_dbg_sel;
+  volatile unsigned char cpu_dbg[4];
+  volatile unsigned char int_status2_enable;
+  unsigned char pad6[7]; /* pad to 0x490 */
+  volatile unsigned char gmbox_rx_lookahead[8];
+  volatile unsigned char gmbox_rx_lookahead_mux;
+  unsigned char pad7[359]; /* pad to 0x600 */
+  volatile unsigned char cis_window[512];
+} mbox_wlan_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h
new file mode 100644
index 000000000000..55d20216ec11
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h
@@ -0,0 +1,634 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_REG_REG_H_
+#define _MBOX_WLAN_REG_REG_H_
+
+#define WLAN_MBOX_FIFO_ADDRESS                   0x00000000
+#define WLAN_MBOX_FIFO_OFFSET                    0x00000000
+#define WLAN_MBOX_FIFO_DATA_MSB                  19
+#define WLAN_MBOX_FIFO_DATA_LSB                  0
+#define WLAN_MBOX_FIFO_DATA_MASK                 0x000fffff
+#define WLAN_MBOX_FIFO_DATA_GET(x)               (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
+#define WLAN_MBOX_FIFO_DATA_SET(x)               (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
+
+#define WLAN_MBOX_FIFO_STATUS_ADDRESS            0x00000010
+#define WLAN_MBOX_FIFO_STATUS_OFFSET             0x00000010
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB          19
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB          16
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK         0x000f0000
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)       (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)       (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
+#define WLAN_MBOX_FIFO_STATUS_FULL_MSB           15
+#define WLAN_MBOX_FIFO_STATUS_FULL_LSB           12
+#define WLAN_MBOX_FIFO_STATUS_FULL_MASK          0x0000f000
+#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x)        (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
+#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x)        (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
+
+#define WLAN_MBOX_DMA_POLICY_ADDRESS             0x00000014
+#define WLAN_MBOX_DMA_POLICY_OFFSET              0x00000014
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB      3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB      3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK     0x00000008
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)   (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)   (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB        2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB        2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK       0x00000004
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)     (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)     (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB      1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB      1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK     0x00000002
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)   (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)   (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB        0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB        0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK       0x00000001
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)     (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)     (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS        0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET         0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS        0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET         0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS        0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET         0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS        0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET         0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS        0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET         0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS        0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET         0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS        0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET         0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB      1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB      1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS        0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET         0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB     2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB     2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK    0x00000004
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)  (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)  (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB      1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB      1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK     0x00000002
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)   (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)   (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB       0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB       0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK      0x00000001
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)    (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)    (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX_INT_STATUS_ADDRESS             0x00000058
+#define WLAN_MBOX_INT_STATUS_OFFSET              0x00000058
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB     17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB     17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK    0x00020000
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)  (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)  (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB    16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB    16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK   0x00010000
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB    15
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB    12
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK   0x0000f000
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB     11
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB     8
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK    0x00000f00
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)  (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)  (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_STATUS_HOST_MSB            7
+#define WLAN_MBOX_INT_STATUS_HOST_LSB            0
+#define WLAN_MBOX_INT_STATUS_HOST_MASK           0x000000ff
+#define WLAN_MBOX_INT_STATUS_HOST_GET(x)         (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
+#define WLAN_MBOX_INT_STATUS_HOST_SET(x)         (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
+
+#define WLAN_MBOX_INT_ENABLE_ADDRESS             0x0000005c
+#define WLAN_MBOX_INT_ENABLE_OFFSET              0x0000005c
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB     17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB     17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK    0x00020000
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)  (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)  (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB    16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB    16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK   0x00010000
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB    15
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB    12
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK   0x0000f000
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB     11
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB     8
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK    0x00000f00
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)  (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)  (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_ENABLE_HOST_MSB            7
+#define WLAN_MBOX_INT_ENABLE_HOST_LSB            0
+#define WLAN_MBOX_INT_ENABLE_HOST_MASK           0x000000ff
+#define WLAN_MBOX_INT_ENABLE_HOST_GET(x)         (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
+#define WLAN_MBOX_INT_ENABLE_HOST_SET(x)         (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
+
+#define WLAN_INT_HOST_ADDRESS                    0x00000060
+#define WLAN_INT_HOST_OFFSET                     0x00000060
+#define WLAN_INT_HOST_VECTOR_MSB                 7
+#define WLAN_INT_HOST_VECTOR_LSB                 0
+#define WLAN_INT_HOST_VECTOR_MASK                0x000000ff
+#define WLAN_INT_HOST_VECTOR_GET(x)              (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
+#define WLAN_INT_HOST_VECTOR_SET(x)              (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
+
+#define WLAN_LOCAL_COUNT_ADDRESS                 0x00000080
+#define WLAN_LOCAL_COUNT_OFFSET                  0x00000080
+#define WLAN_LOCAL_COUNT_VALUE_MSB               7
+#define WLAN_LOCAL_COUNT_VALUE_LSB               0
+#define WLAN_LOCAL_COUNT_VALUE_MASK              0x000000ff
+#define WLAN_LOCAL_COUNT_VALUE_GET(x)            (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
+#define WLAN_LOCAL_COUNT_VALUE_SET(x)            (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
+
+#define WLAN_COUNT_INC_ADDRESS                   0x000000a0
+#define WLAN_COUNT_INC_OFFSET                    0x000000a0
+#define WLAN_COUNT_INC_VALUE_MSB                 7
+#define WLAN_COUNT_INC_VALUE_LSB                 0
+#define WLAN_COUNT_INC_VALUE_MASK                0x000000ff
+#define WLAN_COUNT_INC_VALUE_GET(x)              (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
+#define WLAN_COUNT_INC_VALUE_SET(x)              (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
+
+#define WLAN_LOCAL_SCRATCH_ADDRESS               0x000000c0
+#define WLAN_LOCAL_SCRATCH_OFFSET                0x000000c0
+#define WLAN_LOCAL_SCRATCH_VALUE_MSB             7
+#define WLAN_LOCAL_SCRATCH_VALUE_LSB             0
+#define WLAN_LOCAL_SCRATCH_VALUE_MASK            0x000000ff
+#define WLAN_LOCAL_SCRATCH_VALUE_GET(x)          (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
+#define WLAN_LOCAL_SCRATCH_VALUE_SET(x)          (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
+
+#define WLAN_USE_LOCAL_BUS_ADDRESS               0x000000e0
+#define WLAN_USE_LOCAL_BUS_OFFSET                0x000000e0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB          0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB          0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK         0x00000001
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)       (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)       (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define WLAN_SDIO_CONFIG_ADDRESS                 0x000000e4
+#define WLAN_SDIO_CONFIG_OFFSET                  0x000000e4
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB           0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB           0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK          0x00000001
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)        (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)        (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define WLAN_MBOX_DEBUG_ADDRESS                  0x000000e8
+#define WLAN_MBOX_DEBUG_OFFSET                   0x000000e8
+#define WLAN_MBOX_DEBUG_SEL_MSB                  2
+#define WLAN_MBOX_DEBUG_SEL_LSB                  0
+#define WLAN_MBOX_DEBUG_SEL_MASK                 0x00000007
+#define WLAN_MBOX_DEBUG_SEL_GET(x)               (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
+#define WLAN_MBOX_DEBUG_SEL_SET(x)               (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
+
+#define WLAN_MBOX_FIFO_RESET_ADDRESS             0x000000ec
+#define WLAN_MBOX_FIFO_RESET_OFFSET              0x000000ec
+#define WLAN_MBOX_FIFO_RESET_INIT_MSB            0
+#define WLAN_MBOX_FIFO_RESET_INIT_LSB            0
+#define WLAN_MBOX_FIFO_RESET_INIT_MASK           0x00000001
+#define WLAN_MBOX_FIFO_RESET_INIT_GET(x)         (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
+#define WLAN_MBOX_FIFO_RESET_INIT_SET(x)         (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
+
+#define WLAN_MBOX_TXFIFO_POP_ADDRESS             0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_OFFSET              0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MSB            0
+#define WLAN_MBOX_TXFIFO_POP_DATA_LSB            0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MASK           0x00000001
+#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x)         (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x)         (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
+
+#define WLAN_MBOX_RXFIFO_POP_ADDRESS             0x00000100
+#define WLAN_MBOX_RXFIFO_POP_OFFSET              0x00000100
+#define WLAN_MBOX_RXFIFO_POP_DATA_MSB            0
+#define WLAN_MBOX_RXFIFO_POP_DATA_LSB            0
+#define WLAN_MBOX_RXFIFO_POP_DATA_MASK           0x00000001
+#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x)         (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x)         (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
+
+#define WLAN_SDIO_DEBUG_ADDRESS                  0x00000110
+#define WLAN_SDIO_DEBUG_OFFSET                   0x00000110
+#define WLAN_SDIO_DEBUG_SEL_MSB                  3
+#define WLAN_SDIO_DEBUG_SEL_LSB                  0
+#define WLAN_SDIO_DEBUG_SEL_MASK                 0x0000000f
+#define WLAN_SDIO_DEBUG_SEL_GET(x)               (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
+#define WLAN_SDIO_DEBUG_SEL_SET(x)               (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS       0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET        0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB    2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB    2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK   0x00000004
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB     1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB     1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK    0x00000002
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)  (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)  (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB      0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB      0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK     0x00000001
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)   (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)   (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS       0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET        0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB    2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB    2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK   0x00000004
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB     1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB     1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK    0x00000002
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)  (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)  (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB      0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB      0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK     0x00000001
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)   (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)   (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX_INT_STATUS_ADDRESS            0x00000124
+#define WLAN_GMBOX_INT_STATUS_OFFSET             0x00000124
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB    6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB    6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK   0x00000040
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB   5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB   5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK  0x00000020
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB   1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB   1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK  0x00000002
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB    0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB    0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK   0x00000001
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define WLAN_GMBOX_INT_ENABLE_ADDRESS            0x00000128
+#define WLAN_GMBOX_INT_ENABLE_OFFSET             0x00000128
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB    6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB    6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK   0x00000040
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB   5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB   5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK  0x00000020
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB   1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB   1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK  0x00000002
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB    0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB    0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK   0x00000001
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define WLAN_HOST_IF_WINDOW_ADDRESS              0x00002000
+#define WLAN_HOST_IF_WINDOW_OFFSET               0x00002000
+#define WLAN_HOST_IF_WINDOW_DATA_MSB             7
+#define WLAN_HOST_IF_WINDOW_DATA_LSB             0
+#define WLAN_HOST_IF_WINDOW_DATA_MASK            0x000000ff
+#define WLAN_HOST_IF_WINDOW_DATA_GET(x)          (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
+#define WLAN_HOST_IF_WINDOW_DATA_SET(x)          (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_reg_reg_s {
+  volatile unsigned int wlan_mbox_fifo[4];
+  volatile unsigned int wlan_mbox_fifo_status;
+  volatile unsigned int wlan_mbox_dma_policy;
+  volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox0_dma_rx_control;
+  volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox0_dma_tx_control;
+  volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox1_dma_rx_control;
+  volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox1_dma_tx_control;
+  volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox2_dma_rx_control;
+  volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox2_dma_tx_control;
+  volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
+  volatile unsigned int wlan_mbox3_dma_rx_control;
+  volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
+  volatile unsigned int wlan_mbox3_dma_tx_control;
+  volatile unsigned int wlan_mbox_int_status;
+  volatile unsigned int wlan_mbox_int_enable;
+  volatile unsigned int wlan_int_host;
+  unsigned char pad0[28]; /* pad to 0x80 */
+  volatile unsigned int wlan_local_count[8];
+  volatile unsigned int wlan_count_inc[8];
+  volatile unsigned int wlan_local_scratch[8];
+  volatile unsigned int wlan_use_local_bus;
+  volatile unsigned int wlan_sdio_config;
+  volatile unsigned int wlan_mbox_debug;
+  volatile unsigned int wlan_mbox_fifo_reset;
+  volatile unsigned int wlan_mbox_txfifo_pop[4];
+  volatile unsigned int wlan_mbox_rxfifo_pop[4];
+  volatile unsigned int wlan_sdio_debug;
+  volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
+  volatile unsigned int wlan_gmbox0_dma_rx_control;
+  volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
+  volatile unsigned int wlan_gmbox0_dma_tx_control;
+  volatile unsigned int wlan_gmbox_int_status;
+  volatile unsigned int wlan_gmbox_int_enable;
+  unsigned char pad1[7892]; /* pad to 0x2000 */
+  volatile unsigned int wlan_host_if_window[2048];
+} mbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h
new file mode 100644
index 000000000000..cbf4acfa7925
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h
@@ -0,0 +1,560 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RDMA_REG_REG_H_
+#define _RDMA_REG_REG_H_
+
+#define DMA_CONFIG_ADDRESS                       0x00000000
+#define DMA_CONFIG_OFFSET                        0x00000000
+#define DMA_CONFIG_WLBB_PWD_EN_MSB               4
+#define DMA_CONFIG_WLBB_PWD_EN_LSB               4
+#define DMA_CONFIG_WLBB_PWD_EN_MASK              0x00000010
+#define DMA_CONFIG_WLBB_PWD_EN_GET(x)            (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
+#define DMA_CONFIG_WLBB_PWD_EN_SET(x)            (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
+#define DMA_CONFIG_WLMAC_PWD_EN_MSB              3
+#define DMA_CONFIG_WLMAC_PWD_EN_LSB              3
+#define DMA_CONFIG_WLMAC_PWD_EN_MASK             0x00000008
+#define DMA_CONFIG_WLMAC_PWD_EN_GET(x)           (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
+#define DMA_CONFIG_WLMAC_PWD_EN_SET(x)           (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
+#define DMA_CONFIG_ENABLE_RETENTION_MSB          2
+#define DMA_CONFIG_ENABLE_RETENTION_LSB          2
+#define DMA_CONFIG_ENABLE_RETENTION_MASK         0x00000004
+#define DMA_CONFIG_ENABLE_RETENTION_GET(x)       (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
+#define DMA_CONFIG_ENABLE_RETENTION_SET(x)       (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
+#define DMA_CONFIG_RTC_PRIORITY_MSB              1
+#define DMA_CONFIG_RTC_PRIORITY_LSB              1
+#define DMA_CONFIG_RTC_PRIORITY_MASK             0x00000002
+#define DMA_CONFIG_RTC_PRIORITY_GET(x)           (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
+#define DMA_CONFIG_RTC_PRIORITY_SET(x)           (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
+#define DMA_CONFIG_DMA_TYPE_MSB                  0
+#define DMA_CONFIG_DMA_TYPE_LSB                  0
+#define DMA_CONFIG_DMA_TYPE_MASK                 0x00000001
+#define DMA_CONFIG_DMA_TYPE_GET(x)               (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
+#define DMA_CONFIG_DMA_TYPE_SET(x)               (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
+
+#define DMA_CONTROL_ADDRESS                      0x00000004
+#define DMA_CONTROL_OFFSET                       0x00000004
+#define DMA_CONTROL_START_MSB                    1
+#define DMA_CONTROL_START_LSB                    1
+#define DMA_CONTROL_START_MASK                   0x00000002
+#define DMA_CONTROL_START_GET(x)                 (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
+#define DMA_CONTROL_START_SET(x)                 (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
+#define DMA_CONTROL_STOP_MSB                     0
+#define DMA_CONTROL_STOP_LSB                     0
+#define DMA_CONTROL_STOP_MASK                    0x00000001
+#define DMA_CONTROL_STOP_GET(x)                  (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
+#define DMA_CONTROL_STOP_SET(x)                  (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
+
+#define DMA_SRC_ADDRESS                          0x00000008
+#define DMA_SRC_OFFSET                           0x00000008
+#define DMA_SRC_ADDR_MSB                         31
+#define DMA_SRC_ADDR_LSB                         2
+#define DMA_SRC_ADDR_MASK                        0xfffffffc
+#define DMA_SRC_ADDR_GET(x)                      (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
+#define DMA_SRC_ADDR_SET(x)                      (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
+
+#define DMA_DEST_ADDRESS                         0x0000000c
+#define DMA_DEST_OFFSET                          0x0000000c
+#define DMA_DEST_ADDR_MSB                        31
+#define DMA_DEST_ADDR_LSB                        2
+#define DMA_DEST_ADDR_MASK                       0xfffffffc
+#define DMA_DEST_ADDR_GET(x)                     (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
+#define DMA_DEST_ADDR_SET(x)                     (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
+
+#define DMA_LENGTH_ADDRESS                       0x00000010
+#define DMA_LENGTH_OFFSET                        0x00000010
+#define DMA_LENGTH_WORDS_MSB                     11
+#define DMA_LENGTH_WORDS_LSB                     0
+#define DMA_LENGTH_WORDS_MASK                    0x00000fff
+#define DMA_LENGTH_WORDS_GET(x)                  (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
+#define DMA_LENGTH_WORDS_SET(x)                  (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
+
+#define VMC_BASE_ADDRESS                         0x00000014
+#define VMC_BASE_OFFSET                          0x00000014
+#define VMC_BASE_ADDR_MSB                        31
+#define VMC_BASE_ADDR_LSB                        2
+#define VMC_BASE_ADDR_MASK                       0xfffffffc
+#define VMC_BASE_ADDR_GET(x)                     (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
+#define VMC_BASE_ADDR_SET(x)                     (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
+
+#define INDIRECT_REG_ADDRESS                     0x00000018
+#define INDIRECT_REG_OFFSET                      0x00000018
+#define INDIRECT_REG_ID_MSB                      31
+#define INDIRECT_REG_ID_LSB                      2
+#define INDIRECT_REG_ID_MASK                     0xfffffffc
+#define INDIRECT_REG_ID_GET(x)                   (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
+#define INDIRECT_REG_ID_SET(x)                   (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
+
+#define INDIRECT_RETURN_ADDRESS                  0x0000001c
+#define INDIRECT_RETURN_OFFSET                   0x0000001c
+#define INDIRECT_RETURN_ADDR_MSB                 31
+#define INDIRECT_RETURN_ADDR_LSB                 2
+#define INDIRECT_RETURN_ADDR_MASK                0xfffffffc
+#define INDIRECT_RETURN_ADDR_GET(x)              (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
+#define INDIRECT_RETURN_ADDR_SET(x)              (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
+
+#define RDMA_REGION_0__ADDRESS                   0x00000020
+#define RDMA_REGION_0__OFFSET                    0x00000020
+#define RDMA_REGION_0__ADDR_MSB                  31
+#define RDMA_REGION_0__ADDR_LSB                  13
+#define RDMA_REGION_0__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_0__ADDR_GET(x)               (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
+#define RDMA_REGION_0__ADDR_SET(x)               (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
+#define RDMA_REGION_0__LENGTH_MSB                12
+#define RDMA_REGION_0__LENGTH_LSB                2
+#define RDMA_REGION_0__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_0__LENGTH_GET(x)             (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
+#define RDMA_REGION_0__LENGTH_SET(x)             (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
+#define RDMA_REGION_0__INDI_MSB                  1
+#define RDMA_REGION_0__INDI_LSB                  1
+#define RDMA_REGION_0__INDI_MASK                 0x00000002
+#define RDMA_REGION_0__INDI_GET(x)               (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
+#define RDMA_REGION_0__INDI_SET(x)               (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
+#define RDMA_REGION_0__NEXT_MSB                  0
+#define RDMA_REGION_0__NEXT_LSB                  0
+#define RDMA_REGION_0__NEXT_MASK                 0x00000001
+#define RDMA_REGION_0__NEXT_GET(x)               (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
+#define RDMA_REGION_0__NEXT_SET(x)               (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
+
+#define RDMA_REGION_1__ADDRESS                   0x00000024
+#define RDMA_REGION_1__OFFSET                    0x00000024
+#define RDMA_REGION_1__ADDR_MSB                  31
+#define RDMA_REGION_1__ADDR_LSB                  13
+#define RDMA_REGION_1__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_1__ADDR_GET(x)               (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
+#define RDMA_REGION_1__ADDR_SET(x)               (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
+#define RDMA_REGION_1__LENGTH_MSB                12
+#define RDMA_REGION_1__LENGTH_LSB                2
+#define RDMA_REGION_1__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_1__LENGTH_GET(x)             (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
+#define RDMA_REGION_1__LENGTH_SET(x)             (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
+#define RDMA_REGION_1__INDI_MSB                  1
+#define RDMA_REGION_1__INDI_LSB                  1
+#define RDMA_REGION_1__INDI_MASK                 0x00000002
+#define RDMA_REGION_1__INDI_GET(x)               (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
+#define RDMA_REGION_1__INDI_SET(x)               (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
+#define RDMA_REGION_1__NEXT_MSB                  0
+#define RDMA_REGION_1__NEXT_LSB                  0
+#define RDMA_REGION_1__NEXT_MASK                 0x00000001
+#define RDMA_REGION_1__NEXT_GET(x)               (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
+#define RDMA_REGION_1__NEXT_SET(x)               (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
+
+#define RDMA_REGION_2__ADDRESS                   0x00000028
+#define RDMA_REGION_2__OFFSET                    0x00000028
+#define RDMA_REGION_2__ADDR_MSB                  31
+#define RDMA_REGION_2__ADDR_LSB                  13
+#define RDMA_REGION_2__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_2__ADDR_GET(x)               (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
+#define RDMA_REGION_2__ADDR_SET(x)               (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
+#define RDMA_REGION_2__LENGTH_MSB                12
+#define RDMA_REGION_2__LENGTH_LSB                2
+#define RDMA_REGION_2__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_2__LENGTH_GET(x)             (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
+#define RDMA_REGION_2__LENGTH_SET(x)             (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
+#define RDMA_REGION_2__INDI_MSB                  1
+#define RDMA_REGION_2__INDI_LSB                  1
+#define RDMA_REGION_2__INDI_MASK                 0x00000002
+#define RDMA_REGION_2__INDI_GET(x)               (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
+#define RDMA_REGION_2__INDI_SET(x)               (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
+#define RDMA_REGION_2__NEXT_MSB                  0
+#define RDMA_REGION_2__NEXT_LSB                  0
+#define RDMA_REGION_2__NEXT_MASK                 0x00000001
+#define RDMA_REGION_2__NEXT_GET(x)               (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
+#define RDMA_REGION_2__NEXT_SET(x)               (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
+
+#define RDMA_REGION_3__ADDRESS                   0x0000002c
+#define RDMA_REGION_3__OFFSET                    0x0000002c
+#define RDMA_REGION_3__ADDR_MSB                  31
+#define RDMA_REGION_3__ADDR_LSB                  13
+#define RDMA_REGION_3__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_3__ADDR_GET(x)               (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
+#define RDMA_REGION_3__ADDR_SET(x)               (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
+#define RDMA_REGION_3__LENGTH_MSB                12
+#define RDMA_REGION_3__LENGTH_LSB                2
+#define RDMA_REGION_3__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_3__LENGTH_GET(x)             (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
+#define RDMA_REGION_3__LENGTH_SET(x)             (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
+#define RDMA_REGION_3__INDI_MSB                  1
+#define RDMA_REGION_3__INDI_LSB                  1
+#define RDMA_REGION_3__INDI_MASK                 0x00000002
+#define RDMA_REGION_3__INDI_GET(x)               (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
+#define RDMA_REGION_3__INDI_SET(x)               (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
+#define RDMA_REGION_3__NEXT_MSB                  0
+#define RDMA_REGION_3__NEXT_LSB                  0
+#define RDMA_REGION_3__NEXT_MASK                 0x00000001
+#define RDMA_REGION_3__NEXT_GET(x)               (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
+#define RDMA_REGION_3__NEXT_SET(x)               (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
+
+#define RDMA_REGION_4__ADDRESS                   0x00000030
+#define RDMA_REGION_4__OFFSET                    0x00000030
+#define RDMA_REGION_4__ADDR_MSB                  31
+#define RDMA_REGION_4__ADDR_LSB                  13
+#define RDMA_REGION_4__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_4__ADDR_GET(x)               (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
+#define RDMA_REGION_4__ADDR_SET(x)               (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
+#define RDMA_REGION_4__LENGTH_MSB                12
+#define RDMA_REGION_4__LENGTH_LSB                2
+#define RDMA_REGION_4__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_4__LENGTH_GET(x)             (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
+#define RDMA_REGION_4__LENGTH_SET(x)             (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
+#define RDMA_REGION_4__INDI_MSB                  1
+#define RDMA_REGION_4__INDI_LSB                  1
+#define RDMA_REGION_4__INDI_MASK                 0x00000002
+#define RDMA_REGION_4__INDI_GET(x)               (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
+#define RDMA_REGION_4__INDI_SET(x)               (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
+#define RDMA_REGION_4__NEXT_MSB                  0
+#define RDMA_REGION_4__NEXT_LSB                  0
+#define RDMA_REGION_4__NEXT_MASK                 0x00000001
+#define RDMA_REGION_4__NEXT_GET(x)               (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
+#define RDMA_REGION_4__NEXT_SET(x)               (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
+
+#define RDMA_REGION_5__ADDRESS                   0x00000034
+#define RDMA_REGION_5__OFFSET                    0x00000034
+#define RDMA_REGION_5__ADDR_MSB                  31
+#define RDMA_REGION_5__ADDR_LSB                  13
+#define RDMA_REGION_5__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_5__ADDR_GET(x)               (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
+#define RDMA_REGION_5__ADDR_SET(x)               (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
+#define RDMA_REGION_5__LENGTH_MSB                12
+#define RDMA_REGION_5__LENGTH_LSB                2
+#define RDMA_REGION_5__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_5__LENGTH_GET(x)             (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
+#define RDMA_REGION_5__LENGTH_SET(x)             (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
+#define RDMA_REGION_5__INDI_MSB                  1
+#define RDMA_REGION_5__INDI_LSB                  1
+#define RDMA_REGION_5__INDI_MASK                 0x00000002
+#define RDMA_REGION_5__INDI_GET(x)               (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
+#define RDMA_REGION_5__INDI_SET(x)               (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
+#define RDMA_REGION_5__NEXT_MSB                  0
+#define RDMA_REGION_5__NEXT_LSB                  0
+#define RDMA_REGION_5__NEXT_MASK                 0x00000001
+#define RDMA_REGION_5__NEXT_GET(x)               (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
+#define RDMA_REGION_5__NEXT_SET(x)               (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
+
+#define RDMA_REGION_6__ADDRESS                   0x00000038
+#define RDMA_REGION_6__OFFSET                    0x00000038
+#define RDMA_REGION_6__ADDR_MSB                  31
+#define RDMA_REGION_6__ADDR_LSB                  13
+#define RDMA_REGION_6__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_6__ADDR_GET(x)               (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
+#define RDMA_REGION_6__ADDR_SET(x)               (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
+#define RDMA_REGION_6__LENGTH_MSB                12
+#define RDMA_REGION_6__LENGTH_LSB                2
+#define RDMA_REGION_6__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_6__LENGTH_GET(x)             (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
+#define RDMA_REGION_6__LENGTH_SET(x)             (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
+#define RDMA_REGION_6__INDI_MSB                  1
+#define RDMA_REGION_6__INDI_LSB                  1
+#define RDMA_REGION_6__INDI_MASK                 0x00000002
+#define RDMA_REGION_6__INDI_GET(x)               (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
+#define RDMA_REGION_6__INDI_SET(x)               (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
+#define RDMA_REGION_6__NEXT_MSB                  0
+#define RDMA_REGION_6__NEXT_LSB                  0
+#define RDMA_REGION_6__NEXT_MASK                 0x00000001
+#define RDMA_REGION_6__NEXT_GET(x)               (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
+#define RDMA_REGION_6__NEXT_SET(x)               (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
+
+#define RDMA_REGION_7__ADDRESS                   0x0000003c
+#define RDMA_REGION_7__OFFSET                    0x0000003c
+#define RDMA_REGION_7__ADDR_MSB                  31
+#define RDMA_REGION_7__ADDR_LSB                  13
+#define RDMA_REGION_7__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_7__ADDR_GET(x)               (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
+#define RDMA_REGION_7__ADDR_SET(x)               (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
+#define RDMA_REGION_7__LENGTH_MSB                12
+#define RDMA_REGION_7__LENGTH_LSB                2
+#define RDMA_REGION_7__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_7__LENGTH_GET(x)             (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
+#define RDMA_REGION_7__LENGTH_SET(x)             (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
+#define RDMA_REGION_7__INDI_MSB                  1
+#define RDMA_REGION_7__INDI_LSB                  1
+#define RDMA_REGION_7__INDI_MASK                 0x00000002
+#define RDMA_REGION_7__INDI_GET(x)               (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
+#define RDMA_REGION_7__INDI_SET(x)               (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
+#define RDMA_REGION_7__NEXT_MSB                  0
+#define RDMA_REGION_7__NEXT_LSB                  0
+#define RDMA_REGION_7__NEXT_MASK                 0x00000001
+#define RDMA_REGION_7__NEXT_GET(x)               (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
+#define RDMA_REGION_7__NEXT_SET(x)               (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
+
+#define RDMA_REGION_8__ADDRESS                   0x00000040
+#define RDMA_REGION_8__OFFSET                    0x00000040
+#define RDMA_REGION_8__ADDR_MSB                  31
+#define RDMA_REGION_8__ADDR_LSB                  13
+#define RDMA_REGION_8__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_8__ADDR_GET(x)               (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
+#define RDMA_REGION_8__ADDR_SET(x)               (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
+#define RDMA_REGION_8__LENGTH_MSB                12
+#define RDMA_REGION_8__LENGTH_LSB                2
+#define RDMA_REGION_8__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_8__LENGTH_GET(x)             (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
+#define RDMA_REGION_8__LENGTH_SET(x)             (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
+#define RDMA_REGION_8__INDI_MSB                  1
+#define RDMA_REGION_8__INDI_LSB                  1
+#define RDMA_REGION_8__INDI_MASK                 0x00000002
+#define RDMA_REGION_8__INDI_GET(x)               (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
+#define RDMA_REGION_8__INDI_SET(x)               (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
+#define RDMA_REGION_8__NEXT_MSB                  0
+#define RDMA_REGION_8__NEXT_LSB                  0
+#define RDMA_REGION_8__NEXT_MASK                 0x00000001
+#define RDMA_REGION_8__NEXT_GET(x)               (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
+#define RDMA_REGION_8__NEXT_SET(x)               (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
+
+#define RDMA_REGION_9__ADDRESS                   0x00000044
+#define RDMA_REGION_9__OFFSET                    0x00000044
+#define RDMA_REGION_9__ADDR_MSB                  31
+#define RDMA_REGION_9__ADDR_LSB                  13
+#define RDMA_REGION_9__ADDR_MASK                 0xffffe000
+#define RDMA_REGION_9__ADDR_GET(x)               (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
+#define RDMA_REGION_9__ADDR_SET(x)               (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
+#define RDMA_REGION_9__LENGTH_MSB                12
+#define RDMA_REGION_9__LENGTH_LSB                2
+#define RDMA_REGION_9__LENGTH_MASK               0x00001ffc
+#define RDMA_REGION_9__LENGTH_GET(x)             (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
+#define RDMA_REGION_9__LENGTH_SET(x)             (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
+#define RDMA_REGION_9__INDI_MSB                  1
+#define RDMA_REGION_9__INDI_LSB                  1
+#define RDMA_REGION_9__INDI_MASK                 0x00000002
+#define RDMA_REGION_9__INDI_GET(x)               (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
+#define RDMA_REGION_9__INDI_SET(x)               (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
+#define RDMA_REGION_9__NEXT_MSB                  0
+#define RDMA_REGION_9__NEXT_LSB                  0
+#define RDMA_REGION_9__NEXT_MASK                 0x00000001
+#define RDMA_REGION_9__NEXT_GET(x)               (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
+#define RDMA_REGION_9__NEXT_SET(x)               (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
+
+#define RDMA_REGION_10__ADDRESS                  0x00000048
+#define RDMA_REGION_10__OFFSET                   0x00000048
+#define RDMA_REGION_10__ADDR_MSB                 31
+#define RDMA_REGION_10__ADDR_LSB                 13
+#define RDMA_REGION_10__ADDR_MASK                0xffffe000
+#define RDMA_REGION_10__ADDR_GET(x)              (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
+#define RDMA_REGION_10__ADDR_SET(x)              (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
+#define RDMA_REGION_10__LENGTH_MSB               12
+#define RDMA_REGION_10__LENGTH_LSB               2
+#define RDMA_REGION_10__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_10__LENGTH_GET(x)            (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
+#define RDMA_REGION_10__LENGTH_SET(x)            (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
+#define RDMA_REGION_10__INDI_MSB                 1
+#define RDMA_REGION_10__INDI_LSB                 1
+#define RDMA_REGION_10__INDI_MASK                0x00000002
+#define RDMA_REGION_10__INDI_GET(x)              (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
+#define RDMA_REGION_10__INDI_SET(x)              (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
+#define RDMA_REGION_10__NEXT_MSB                 0
+#define RDMA_REGION_10__NEXT_LSB                 0
+#define RDMA_REGION_10__NEXT_MASK                0x00000001
+#define RDMA_REGION_10__NEXT_GET(x)              (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
+#define RDMA_REGION_10__NEXT_SET(x)              (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
+
+#define RDMA_REGION_11__ADDRESS                  0x0000004c
+#define RDMA_REGION_11__OFFSET                   0x0000004c
+#define RDMA_REGION_11__ADDR_MSB                 31
+#define RDMA_REGION_11__ADDR_LSB                 13
+#define RDMA_REGION_11__ADDR_MASK                0xffffe000
+#define RDMA_REGION_11__ADDR_GET(x)              (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
+#define RDMA_REGION_11__ADDR_SET(x)              (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
+#define RDMA_REGION_11__LENGTH_MSB               12
+#define RDMA_REGION_11__LENGTH_LSB               2
+#define RDMA_REGION_11__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_11__LENGTH_GET(x)            (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
+#define RDMA_REGION_11__LENGTH_SET(x)            (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
+#define RDMA_REGION_11__INDI_MSB                 1
+#define RDMA_REGION_11__INDI_LSB                 1
+#define RDMA_REGION_11__INDI_MASK                0x00000002
+#define RDMA_REGION_11__INDI_GET(x)              (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
+#define RDMA_REGION_11__INDI_SET(x)              (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
+#define RDMA_REGION_11__NEXT_MSB                 0
+#define RDMA_REGION_11__NEXT_LSB                 0
+#define RDMA_REGION_11__NEXT_MASK                0x00000001
+#define RDMA_REGION_11__NEXT_GET(x)              (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
+#define RDMA_REGION_11__NEXT_SET(x)              (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
+
+#define RDMA_REGION_12__ADDRESS                  0x00000050
+#define RDMA_REGION_12__OFFSET                   0x00000050
+#define RDMA_REGION_12__ADDR_MSB                 31
+#define RDMA_REGION_12__ADDR_LSB                 13
+#define RDMA_REGION_12__ADDR_MASK                0xffffe000
+#define RDMA_REGION_12__ADDR_GET(x)              (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
+#define RDMA_REGION_12__ADDR_SET(x)              (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
+#define RDMA_REGION_12__LENGTH_MSB               12
+#define RDMA_REGION_12__LENGTH_LSB               2
+#define RDMA_REGION_12__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_12__LENGTH_GET(x)            (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
+#define RDMA_REGION_12__LENGTH_SET(x)            (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
+#define RDMA_REGION_12__INDI_MSB                 1
+#define RDMA_REGION_12__INDI_LSB                 1
+#define RDMA_REGION_12__INDI_MASK                0x00000002
+#define RDMA_REGION_12__INDI_GET(x)              (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
+#define RDMA_REGION_12__INDI_SET(x)              (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
+#define RDMA_REGION_12__NEXT_MSB                 0
+#define RDMA_REGION_12__NEXT_LSB                 0
+#define RDMA_REGION_12__NEXT_MASK                0x00000001
+#define RDMA_REGION_12__NEXT_GET(x)              (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
+#define RDMA_REGION_12__NEXT_SET(x)              (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
+
+#define RDMA_REGION_13__ADDRESS                  0x00000054
+#define RDMA_REGION_13__OFFSET                   0x00000054
+#define RDMA_REGION_13__ADDR_MSB                 31
+#define RDMA_REGION_13__ADDR_LSB                 13
+#define RDMA_REGION_13__ADDR_MASK                0xffffe000
+#define RDMA_REGION_13__ADDR_GET(x)              (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
+#define RDMA_REGION_13__ADDR_SET(x)              (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
+#define RDMA_REGION_13__LENGTH_MSB               12
+#define RDMA_REGION_13__LENGTH_LSB               2
+#define RDMA_REGION_13__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_13__LENGTH_GET(x)            (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
+#define RDMA_REGION_13__LENGTH_SET(x)            (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
+#define RDMA_REGION_13__INDI_MSB                 1
+#define RDMA_REGION_13__INDI_LSB                 1
+#define RDMA_REGION_13__INDI_MASK                0x00000002
+#define RDMA_REGION_13__INDI_GET(x)              (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
+#define RDMA_REGION_13__INDI_SET(x)              (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
+#define RDMA_REGION_13__NEXT_MSB                 0
+#define RDMA_REGION_13__NEXT_LSB                 0
+#define RDMA_REGION_13__NEXT_MASK                0x00000001
+#define RDMA_REGION_13__NEXT_GET(x)              (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
+#define RDMA_REGION_13__NEXT_SET(x)              (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
+
+#define RDMA_REGION_14__ADDRESS                  0x00000058
+#define RDMA_REGION_14__OFFSET                   0x00000058
+#define RDMA_REGION_14__ADDR_MSB                 31
+#define RDMA_REGION_14__ADDR_LSB                 13
+#define RDMA_REGION_14__ADDR_MASK                0xffffe000
+#define RDMA_REGION_14__ADDR_GET(x)              (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
+#define RDMA_REGION_14__ADDR_SET(x)              (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
+#define RDMA_REGION_14__LENGTH_MSB               12
+#define RDMA_REGION_14__LENGTH_LSB               2
+#define RDMA_REGION_14__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_14__LENGTH_GET(x)            (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
+#define RDMA_REGION_14__LENGTH_SET(x)            (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
+#define RDMA_REGION_14__INDI_MSB                 1
+#define RDMA_REGION_14__INDI_LSB                 1
+#define RDMA_REGION_14__INDI_MASK                0x00000002
+#define RDMA_REGION_14__INDI_GET(x)              (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
+#define RDMA_REGION_14__INDI_SET(x)              (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
+#define RDMA_REGION_14__NEXT_MSB                 0
+#define RDMA_REGION_14__NEXT_LSB                 0
+#define RDMA_REGION_14__NEXT_MASK                0x00000001
+#define RDMA_REGION_14__NEXT_GET(x)              (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
+#define RDMA_REGION_14__NEXT_SET(x)              (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
+
+#define RDMA_REGION_15__ADDRESS                  0x0000005c
+#define RDMA_REGION_15__OFFSET                   0x0000005c
+#define RDMA_REGION_15__ADDR_MSB                 31
+#define RDMA_REGION_15__ADDR_LSB                 13
+#define RDMA_REGION_15__ADDR_MASK                0xffffe000
+#define RDMA_REGION_15__ADDR_GET(x)              (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
+#define RDMA_REGION_15__ADDR_SET(x)              (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
+#define RDMA_REGION_15__LENGTH_MSB               12
+#define RDMA_REGION_15__LENGTH_LSB               2
+#define RDMA_REGION_15__LENGTH_MASK              0x00001ffc
+#define RDMA_REGION_15__LENGTH_GET(x)            (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
+#define RDMA_REGION_15__LENGTH_SET(x)            (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
+#define RDMA_REGION_15__INDI_MSB                 1
+#define RDMA_REGION_15__INDI_LSB                 1
+#define RDMA_REGION_15__INDI_MASK                0x00000002
+#define RDMA_REGION_15__INDI_GET(x)              (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
+#define RDMA_REGION_15__INDI_SET(x)              (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
+#define RDMA_REGION_15__NEXT_MSB                 0
+#define RDMA_REGION_15__NEXT_LSB                 0
+#define RDMA_REGION_15__NEXT_MASK                0x00000001
+#define RDMA_REGION_15__NEXT_GET(x)              (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
+#define RDMA_REGION_15__NEXT_SET(x)              (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
+
+#define DMA_STATUS_ADDRESS                       0x00000060
+#define DMA_STATUS_OFFSET                        0x00000060
+#define DMA_STATUS_ERROR_CODE_MSB                14
+#define DMA_STATUS_ERROR_CODE_LSB                4
+#define DMA_STATUS_ERROR_CODE_MASK               0x00007ff0
+#define DMA_STATUS_ERROR_CODE_GET(x)             (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
+#define DMA_STATUS_ERROR_CODE_SET(x)             (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
+#define DMA_STATUS_ERROR_MSB                     3
+#define DMA_STATUS_ERROR_LSB                     3
+#define DMA_STATUS_ERROR_MASK                    0x00000008
+#define DMA_STATUS_ERROR_GET(x)                  (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
+#define DMA_STATUS_ERROR_SET(x)                  (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
+#define DMA_STATUS_DONE_MSB                      2
+#define DMA_STATUS_DONE_LSB                      2
+#define DMA_STATUS_DONE_MASK                     0x00000004
+#define DMA_STATUS_DONE_GET(x)                   (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
+#define DMA_STATUS_DONE_SET(x)                   (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
+#define DMA_STATUS_STOPPED_MSB                   1
+#define DMA_STATUS_STOPPED_LSB                   1
+#define DMA_STATUS_STOPPED_MASK                  0x00000002
+#define DMA_STATUS_STOPPED_GET(x)                (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
+#define DMA_STATUS_STOPPED_SET(x)                (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
+#define DMA_STATUS_RUNNING_MSB                   0
+#define DMA_STATUS_RUNNING_LSB                   0
+#define DMA_STATUS_RUNNING_MASK                  0x00000001
+#define DMA_STATUS_RUNNING_GET(x)                (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
+#define DMA_STATUS_RUNNING_SET(x)                (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
+
+#define DMA_INT_EN_ADDRESS                       0x00000064
+#define DMA_INT_EN_OFFSET                        0x00000064
+#define DMA_INT_EN_ERROR_ENA_MSB                 3
+#define DMA_INT_EN_ERROR_ENA_LSB                 3
+#define DMA_INT_EN_ERROR_ENA_MASK                0x00000008
+#define DMA_INT_EN_ERROR_ENA_GET(x)              (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
+#define DMA_INT_EN_ERROR_ENA_SET(x)              (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
+#define DMA_INT_EN_DONE_ENA_MSB                  2
+#define DMA_INT_EN_DONE_ENA_LSB                  2
+#define DMA_INT_EN_DONE_ENA_MASK                 0x00000004
+#define DMA_INT_EN_DONE_ENA_GET(x)               (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
+#define DMA_INT_EN_DONE_ENA_SET(x)               (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
+#define DMA_INT_EN_STOPPED_ENA_MSB               1
+#define DMA_INT_EN_STOPPED_ENA_LSB               1
+#define DMA_INT_EN_STOPPED_ENA_MASK              0x00000002
+#define DMA_INT_EN_STOPPED_ENA_GET(x)            (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
+#define DMA_INT_EN_STOPPED_ENA_SET(x)            (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rdma_reg_reg_s {
+  volatile unsigned int dma_config;
+  volatile unsigned int dma_control;
+  volatile unsigned int dma_src;
+  volatile unsigned int dma_dest;
+  volatile unsigned int dma_length;
+  volatile unsigned int vmc_base;
+  volatile unsigned int indirect_reg;
+  volatile unsigned int indirect_return;
+  volatile unsigned int rdma_region_0_;
+  volatile unsigned int rdma_region_1_;
+  volatile unsigned int rdma_region_2_;
+  volatile unsigned int rdma_region_3_;
+  volatile unsigned int rdma_region_4_;
+  volatile unsigned int rdma_region_5_;
+  volatile unsigned int rdma_region_6_;
+  volatile unsigned int rdma_region_7_;
+  volatile unsigned int rdma_region_8_;
+  volatile unsigned int rdma_region_9_;
+  volatile unsigned int rdma_region_10_;
+  volatile unsigned int rdma_region_11_;
+  volatile unsigned int rdma_region_12_;
+  volatile unsigned int rdma_region_13_;
+  volatile unsigned int rdma_region_14_;
+  volatile unsigned int rdma_region_15_;
+  volatile unsigned int dma_status;
+  volatile unsigned int dma_int_en;
+} rdma_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RDMA_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h
new file mode 100644
index 000000000000..312af9284b7c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h
@@ -0,0 +1,971 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "rtc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
+#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
+#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
+#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
+#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
+#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
+#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
+#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
+#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
+#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
+#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
+#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
+#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
+#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
+#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
+#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
+#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
+#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
+#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
+#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
+#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
+#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
+#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
+#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
+#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
+#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
+#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
+#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
+#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
+#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
+#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
+#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
+#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
+#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
+#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
+#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
+#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
+#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
+#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
+#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
+#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
+#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
+#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
+#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
+#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
+#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
+#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
+#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
+#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
+#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
+#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
+#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
+#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
+#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
+#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
+#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
+#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
+#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
+#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
+#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
+#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
+#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
+#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
+#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
+#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
+#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
+#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
+#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
+#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
+#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
+#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
+#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
+#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
+#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
+#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
+#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
+#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
+#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
+#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
+#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
+#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
+#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
+#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
+#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
+#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
+#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
+#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
+#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
+#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
+#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
+#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
+#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
+#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
+#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
+#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
+#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
+#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
+#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
+#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
+#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
+#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
+#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
+#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
+#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
+#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
+#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
+#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
+#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
+#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
+#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
+#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
+#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
+#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
+#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
+#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
+#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
+#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
+#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
+#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
+#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
+#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
+#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
+#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
+#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
+#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
+#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
+#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
+#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
+#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
+#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
+#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
+#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
+#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
+#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
+#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
+#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
+#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
+#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
+#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
+#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
+#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
+#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
+#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
+#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
+#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
+#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
+#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
+#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
+#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
+#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
+#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
+#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
+#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
+#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
+#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
+#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
+#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
+#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
+#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
+#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
+#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
+#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
+#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
+#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
+#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
+#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
+#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
+#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
+#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
+#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
+#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
+#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
+#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
+#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
+#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
+#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
+#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
+#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
+#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
+#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
+#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
+#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
+#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
+#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
+#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
+#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
+#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
+#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
+#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
+#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
+#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
+#define WDT_ADDRESS WLAN_WDT_ADDRESS
+#define WDT_OFFSET WLAN_WDT_OFFSET
+#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
+#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
+#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
+#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
+#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
+#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
+#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
+#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
+#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
+#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
+#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
+#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
+#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
+#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
+#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
+#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
+#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
+#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
+#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
+#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
+#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
+#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
+#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
+#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
+#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
+#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
+#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
+#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
+#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
+#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
+#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
+#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
+#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
+#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
+#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
+#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
+#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
+#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
+#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
+#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
+#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
+#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
+#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
+#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
+#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
+#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
+#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
+#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
+#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
+#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
+#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
+#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
+#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
+#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
+#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
+#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
+#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
+#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
+#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
+#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
+#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
+#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
+#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
+#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
+#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
+#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
+#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
+#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
+#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
+#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
+#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
+#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
+#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
+#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
+#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
+#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
+#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
+#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
+#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
+#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
+#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
+#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
+#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
+#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
+#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
+#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
+#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
+#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
+#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
+#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
+#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
+#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
+#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
+#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
+#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
+#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
+#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
+#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
+#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
+#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
+#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
+#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
+#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
+#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
+#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
+#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
+#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
+#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
+#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
+#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
+#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
+#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
+#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
+#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
+#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
+#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
+#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
+#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
+#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
+#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
+#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
+#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
+#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
+#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
+#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
+#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
+#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
+#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
+#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
+#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
+#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
+#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
+#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
+#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
+#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
+#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
+#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
+#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
+#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
+#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
+#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
+#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
+#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
+#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
+#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
+#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
+#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
+#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
+#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
+#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
+#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
+#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
+#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
+#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
+#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
+#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
+#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
+#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
+#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
+#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
+#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
+#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
+#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
+#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
+#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
+#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
+#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
+#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
+#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
+#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
+#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
+#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
+#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
+#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
+#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
+#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
+#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
+#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
+#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
+#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
+#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
+#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
+#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
+#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
+#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
+#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
+#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
+#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
+#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
+#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
+#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
+#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
+#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
+#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
+#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
+#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
+#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
+#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
+#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
+#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
+#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
+#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
+#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
+#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
+#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
+#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
+#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
+#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
+#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
+#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
+#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
+#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
+#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
+#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
+#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
+#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
+#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
+#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
+#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
+#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
+#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
+#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
+#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
+#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
+#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
+#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
+#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
+#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
+#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
+#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
+#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
+#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
+#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
+#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
+#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
+#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
+#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
+#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
+#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
+#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
+#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
+#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
+#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
+#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
+#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
+#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
+#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
+#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
+#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
+#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
+#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
+#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
+#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
+#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
+#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
+#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
+#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
+#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
+#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
+#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
+#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
+#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
+#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
+#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
+#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
+#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
+#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
+#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
+#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
+#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
+#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
+#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
+#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
+#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
+#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
+#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
+#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
+#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
+#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
+#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
+#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
+#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
+#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
+#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
+#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
+#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
+#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
+#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
+#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
+#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
+#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
+#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
+#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
+#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
+#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
+#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
+#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
+#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
+#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
+#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
+#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
+#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
+#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
+#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
+#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
+#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
+#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
+#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
+#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
+#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
+#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
+#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
+#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
+#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
+#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
+#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
+#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
+#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
+#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
+#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
+#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
+#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
+#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
+#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
+#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
+#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
+#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
+#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
+#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
+#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
+#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
+#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
+#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
+#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
+#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
+#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
+#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
+#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
+#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
+#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
+#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
+#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
+#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
+#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
+#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
+#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
+#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
+#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
+#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
+#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
+#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
+#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
+#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
+#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
+#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
+#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
+#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
+#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
+#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
+#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
+#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
+#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
+#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
+#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
+#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
+#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
+#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
+#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
+#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
+#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
+#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
+#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
+#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
+#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
+#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
+#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
+#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
+#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
+#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
+#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
+#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
+#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
+#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
+#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
+#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
+#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
+#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
+#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
+#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
+#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
+#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
+#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
+#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
+#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
+#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
+#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
+#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
+#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
+#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
+#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
+#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
+#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
+#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
+#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
+#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
+#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
+#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
+#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
+#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
+#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
+#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
+#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
+#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
+#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
+#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
+#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
+#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
+#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
+#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
+#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
+#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
+#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
+#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
+#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
+#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
+#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
+#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
+#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
+#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
+#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
+#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
+#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
+#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
+#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
+#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
+#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
+#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
+#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
+#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
+#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
+#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
+#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
+#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
+#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
+#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
+#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
+#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
+#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
+#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
+#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
+#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
+#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
+#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
+#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
+#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
+#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
+#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
+#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
+#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
+#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
+#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
+#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
+#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
+#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
+#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
+#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
+#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
+#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
+#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
+#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
+#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
+#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
+#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
+#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
+#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
+#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
+#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
+#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
+#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
+#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
+#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
+#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
+#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
+#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
+#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
+#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
+#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
+#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
+#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
+#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
+#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
+#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
+#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
+#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
+#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
+#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
+#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
+#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
+#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
+#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
+#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
+#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
+#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
+#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
+#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
+#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
+#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
+#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
+#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
+#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
+#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
+#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
+#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
+#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
+#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
+#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
+#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
+#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
+#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
+#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
+#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
+#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
+#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
+#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
+#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
+#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
+#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
+#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
+#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
+#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
+#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
+#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
+#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
+#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
+#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
+#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
+#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
+#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
+#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
+#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
+#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
+#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
+#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
+#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
+#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
+#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
+#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
+#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
+#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
+#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
+#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
+#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
+#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
+#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
+#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
+#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
+#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
+#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
+#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
+#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
+#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
+#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
+#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
+#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
+#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
+#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
+#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
+#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
+#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
+#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
+#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
+#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
+#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
+#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
+#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
+#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
+#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
+#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
+#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
+#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
+#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
+#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
+#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
+#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
+#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
+#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
+#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
+#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
+#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
+#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
+#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
+#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
+#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
+#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
+#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
+#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
+#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
+#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
+#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
+#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
+#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
+#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
+#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
+#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
+#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
+#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
+#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
+#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
+#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
+#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
+#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
+#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
+#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
+#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
+#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
+#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
+#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
+#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
+#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
+#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
+#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
+#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
+#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
+#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
+#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
+#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h
new file mode 100644
index 000000000000..c215f2e78809
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h
@@ -0,0 +1,2061 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_WLAN_REG_REG_H_
+#define _RTC_WLAN_REG_REG_H_
+
+#define WLAN_RESET_CONTROL_ADDRESS               0x00000000
+#define WLAN_RESET_CONTROL_OFFSET                0x00000000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB    14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB    14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK   0x00004000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB       13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB       13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK      0x00002000
+#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)    (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)    (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB       12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB       12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK      0x00001000
+#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)    (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)    (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB    11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB    11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK   0x00000800
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB   10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB   10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK  0x00000400
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define WLAN_RESET_CONTROL_RST_OUT_MSB           9
+#define WLAN_RESET_CONTROL_RST_OUT_LSB           9
+#define WLAN_RESET_CONTROL_RST_OUT_MASK          0x00000200
+#define WLAN_RESET_CONTROL_RST_OUT_GET(x)        (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB)
+#define WLAN_RESET_CONTROL_RST_OUT_SET(x)        (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK)
+#define WLAN_RESET_CONTROL_COLD_RST_MSB          8
+#define WLAN_RESET_CONTROL_COLD_RST_LSB          8
+#define WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000100
+#define WLAN_RESET_CONTROL_COLD_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_COLD_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_WARM_RST_MSB          7
+#define WLAN_RESET_CONTROL_WARM_RST_LSB          7
+#define WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000080
+#define WLAN_RESET_CONTROL_WARM_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_WARM_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB      6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB      6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK     0x00000040
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB      5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB      5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK     0x00000020
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB      4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB      4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK     0x00000010
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)   (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)   (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MBOX_RST_MSB          2
+#define WLAN_RESET_CONTROL_MBOX_RST_LSB          2
+#define WLAN_RESET_CONTROL_MBOX_RST_MASK         0x00000004
+#define WLAN_RESET_CONTROL_MBOX_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB)
+#define WLAN_RESET_CONTROL_MBOX_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK)
+#define WLAN_RESET_CONTROL_UART_RST_MSB          1
+#define WLAN_RESET_CONTROL_UART_RST_LSB          1
+#define WLAN_RESET_CONTROL_UART_RST_MASK         0x00000002
+#define WLAN_RESET_CONTROL_UART_RST_GET(x)       (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_UART_RST_SET(x)       (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_SI0_RST_MSB           0
+#define WLAN_RESET_CONTROL_SI0_RST_LSB           0
+#define WLAN_RESET_CONTROL_SI0_RST_MASK          0x00000001
+#define WLAN_RESET_CONTROL_SI0_RST_GET(x)        (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB)
+#define WLAN_RESET_CONTROL_SI0_RST_SET(x)        (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK)
+
+#define WLAN_XTAL_CONTROL_ADDRESS                0x00000004
+#define WLAN_XTAL_CONTROL_OFFSET                 0x00000004
+#define WLAN_XTAL_CONTROL_TCXO_MSB               0
+#define WLAN_XTAL_CONTROL_TCXO_LSB               0
+#define WLAN_XTAL_CONTROL_TCXO_MASK              0x00000001
+#define WLAN_XTAL_CONTROL_TCXO_GET(x)            (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB)
+#define WLAN_XTAL_CONTROL_TCXO_SET(x)            (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK)
+
+#define WLAN_TCXO_DETECT_ADDRESS                 0x00000008
+#define WLAN_TCXO_DETECT_OFFSET                  0x00000008
+#define WLAN_TCXO_DETECT_PRESENT_MSB             0
+#define WLAN_TCXO_DETECT_PRESENT_LSB             0
+#define WLAN_TCXO_DETECT_PRESENT_MASK            0x00000001
+#define WLAN_TCXO_DETECT_PRESENT_GET(x)          (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB)
+#define WLAN_TCXO_DETECT_PRESENT_SET(x)          (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK)
+
+#define WLAN_XTAL_TEST_ADDRESS                   0x0000000c
+#define WLAN_XTAL_TEST_OFFSET                    0x0000000c
+#define WLAN_XTAL_TEST_NOTCXODET_MSB             0
+#define WLAN_XTAL_TEST_NOTCXODET_LSB             0
+#define WLAN_XTAL_TEST_NOTCXODET_MASK            0x00000001
+#define WLAN_XTAL_TEST_NOTCXODET_GET(x)          (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB)
+#define WLAN_XTAL_TEST_NOTCXODET_SET(x)          (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK)
+
+#define WLAN_QUADRATURE_ADDRESS                  0x00000010
+#define WLAN_QUADRATURE_OFFSET                   0x00000010
+#define WLAN_QUADRATURE_ADC_MSB                  7
+#define WLAN_QUADRATURE_ADC_LSB                  4
+#define WLAN_QUADRATURE_ADC_MASK                 0x000000f0
+#define WLAN_QUADRATURE_ADC_GET(x)               (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB)
+#define WLAN_QUADRATURE_ADC_SET(x)               (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK)
+#define WLAN_QUADRATURE_SEL_MSB                  2
+#define WLAN_QUADRATURE_SEL_LSB                  2
+#define WLAN_QUADRATURE_SEL_MASK                 0x00000004
+#define WLAN_QUADRATURE_SEL_GET(x)               (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB)
+#define WLAN_QUADRATURE_SEL_SET(x)               (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK)
+#define WLAN_QUADRATURE_DAC_MSB                  1
+#define WLAN_QUADRATURE_DAC_LSB                  0
+#define WLAN_QUADRATURE_DAC_MASK                 0x00000003
+#define WLAN_QUADRATURE_DAC_GET(x)               (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB)
+#define WLAN_QUADRATURE_DAC_SET(x)               (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK)
+
+#define WLAN_PLL_CONTROL_ADDRESS                 0x00000014
+#define WLAN_PLL_CONTROL_OFFSET                  0x00000014
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB        20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB        20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK       0x00100000
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)     (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)     (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB        19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB        19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK       0x00080000
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)     (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)     (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define WLAN_PLL_CONTROL_NOPWD_MSB               18
+#define WLAN_PLL_CONTROL_NOPWD_LSB               18
+#define WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
+#define WLAN_PLL_CONTROL_NOPWD_GET(x)            (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
+#define WLAN_PLL_CONTROL_NOPWD_SET(x)            (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
+#define WLAN_PLL_CONTROL_UPDATING_MSB            17
+#define WLAN_PLL_CONTROL_UPDATING_LSB            17
+#define WLAN_PLL_CONTROL_UPDATING_MASK           0x00020000
+#define WLAN_PLL_CONTROL_UPDATING_GET(x)         (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB)
+#define WLAN_PLL_CONTROL_UPDATING_SET(x)         (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_MSB              16
+#define WLAN_PLL_CONTROL_BYPASS_LSB              16
+#define WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
+#define WLAN_PLL_CONTROL_BYPASS_GET(x)           (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
+#define WLAN_PLL_CONTROL_BYPASS_SET(x)           (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
+#define WLAN_PLL_CONTROL_REFDIV_MSB              15
+#define WLAN_PLL_CONTROL_REFDIV_LSB              12
+#define WLAN_PLL_CONTROL_REFDIV_MASK             0x0000f000
+#define WLAN_PLL_CONTROL_REFDIV_GET(x)           (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
+#define WLAN_PLL_CONTROL_REFDIV_SET(x)           (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
+#define WLAN_PLL_CONTROL_DIV_MSB                 9
+#define WLAN_PLL_CONTROL_DIV_LSB                 0
+#define WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
+#define WLAN_PLL_CONTROL_DIV_GET(x)              (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
+#define WLAN_PLL_CONTROL_DIV_SET(x)              (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
+
+#define WLAN_PLL_SETTLE_ADDRESS                  0x00000018
+#define WLAN_PLL_SETTLE_OFFSET                   0x00000018
+#define WLAN_PLL_SETTLE_TIME_MSB                 11
+#define WLAN_PLL_SETTLE_TIME_LSB                 0
+#define WLAN_PLL_SETTLE_TIME_MASK                0x00000fff
+#define WLAN_PLL_SETTLE_TIME_GET(x)              (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
+#define WLAN_PLL_SETTLE_TIME_SET(x)              (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
+
+#define WLAN_XTAL_SETTLE_ADDRESS                 0x0000001c
+#define WLAN_XTAL_SETTLE_OFFSET                  0x0000001c
+#define WLAN_XTAL_SETTLE_TIME_MSB                7
+#define WLAN_XTAL_SETTLE_TIME_LSB                0
+#define WLAN_XTAL_SETTLE_TIME_MASK               0x000000ff
+#define WLAN_XTAL_SETTLE_TIME_GET(x)             (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB)
+#define WLAN_XTAL_SETTLE_TIME_SET(x)             (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK)
+
+#define WLAN_CPU_CLOCK_ADDRESS                   0x00000020
+#define WLAN_CPU_CLOCK_OFFSET                    0x00000020
+#define WLAN_CPU_CLOCK_STANDARD_MSB              1
+#define WLAN_CPU_CLOCK_STANDARD_LSB              0
+#define WLAN_CPU_CLOCK_STANDARD_MASK             0x00000003
+#define WLAN_CPU_CLOCK_STANDARD_GET(x)           (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB)
+#define WLAN_CPU_CLOCK_STANDARD_SET(x)           (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK)
+
+#define WLAN_CLOCK_OUT_ADDRESS                   0x00000024
+#define WLAN_CLOCK_OUT_OFFSET                    0x00000024
+#define WLAN_CLOCK_OUT_SELECT_MSB                3
+#define WLAN_CLOCK_OUT_SELECT_LSB                0
+#define WLAN_CLOCK_OUT_SELECT_MASK               0x0000000f
+#define WLAN_CLOCK_OUT_SELECT_GET(x)             (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB)
+#define WLAN_CLOCK_OUT_SELECT_SET(x)             (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK)
+
+#define WLAN_CLOCK_CONTROL_ADDRESS               0x00000028
+#define WLAN_CLOCK_CONTROL_OFFSET                0x00000028
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB          2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB          2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK         0x00000004
+#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)       (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB)
+#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)       (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB           0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB           0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK          0x00000001
+#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)        (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)        (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define WLAN_BIAS_OVERRIDE_ADDRESS               0x0000002c
+#define WLAN_BIAS_OVERRIDE_OFFSET                0x0000002c
+#define WLAN_BIAS_OVERRIDE_ON_MSB                0
+#define WLAN_BIAS_OVERRIDE_ON_LSB                0
+#define WLAN_BIAS_OVERRIDE_ON_MASK               0x00000001
+#define WLAN_BIAS_OVERRIDE_ON_GET(x)             (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB)
+#define WLAN_BIAS_OVERRIDE_ON_SET(x)             (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK)
+
+#define WLAN_WDT_CONTROL_ADDRESS                 0x00000030
+#define WLAN_WDT_CONTROL_OFFSET                  0x00000030
+#define WLAN_WDT_CONTROL_ACTION_MSB              2
+#define WLAN_WDT_CONTROL_ACTION_LSB              0
+#define WLAN_WDT_CONTROL_ACTION_MASK             0x00000007
+#define WLAN_WDT_CONTROL_ACTION_GET(x)           (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB)
+#define WLAN_WDT_CONTROL_ACTION_SET(x)           (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK)
+
+#define WLAN_WDT_STATUS_ADDRESS                  0x00000034
+#define WLAN_WDT_STATUS_OFFSET                   0x00000034
+#define WLAN_WDT_STATUS_INTERRUPT_MSB            0
+#define WLAN_WDT_STATUS_INTERRUPT_LSB            0
+#define WLAN_WDT_STATUS_INTERRUPT_MASK           0x00000001
+#define WLAN_WDT_STATUS_INTERRUPT_GET(x)         (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB)
+#define WLAN_WDT_STATUS_INTERRUPT_SET(x)         (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK)
+
+#define WLAN_WDT_ADDRESS                         0x00000038
+#define WLAN_WDT_OFFSET                          0x00000038
+#define WLAN_WDT_TARGET_MSB                      21
+#define WLAN_WDT_TARGET_LSB                      0
+#define WLAN_WDT_TARGET_MASK                     0x003fffff
+#define WLAN_WDT_TARGET_GET(x)                   (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB)
+#define WLAN_WDT_TARGET_SET(x)                   (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK)
+
+#define WLAN_WDT_COUNT_ADDRESS                   0x0000003c
+#define WLAN_WDT_COUNT_OFFSET                    0x0000003c
+#define WLAN_WDT_COUNT_VALUE_MSB                 21
+#define WLAN_WDT_COUNT_VALUE_LSB                 0
+#define WLAN_WDT_COUNT_VALUE_MASK                0x003fffff
+#define WLAN_WDT_COUNT_VALUE_GET(x)              (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB)
+#define WLAN_WDT_COUNT_VALUE_SET(x)              (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK)
+
+#define WLAN_WDT_RESET_ADDRESS                   0x00000040
+#define WLAN_WDT_RESET_OFFSET                    0x00000040
+#define WLAN_WDT_RESET_VALUE_MSB                 0
+#define WLAN_WDT_RESET_VALUE_LSB                 0
+#define WLAN_WDT_RESET_VALUE_MASK                0x00000001
+#define WLAN_WDT_RESET_VALUE_GET(x)              (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB)
+#define WLAN_WDT_RESET_VALUE_SET(x)              (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK)
+
+#define WLAN_INT_STATUS_ADDRESS                  0x00000044
+#define WLAN_INT_STATUS_OFFSET                   0x00000044
+#define WLAN_INT_STATUS_HCI_UART_MSB             21
+#define WLAN_INT_STATUS_HCI_UART_LSB             21
+#define WLAN_INT_STATUS_HCI_UART_MASK            0x00200000
+#define WLAN_INT_STATUS_HCI_UART_GET(x)          (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB)
+#define WLAN_INT_STATUS_HCI_UART_SET(x)          (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK)
+#define WLAN_INT_STATUS_THERM_MSB                20
+#define WLAN_INT_STATUS_THERM_LSB                20
+#define WLAN_INT_STATUS_THERM_MASK               0x00100000
+#define WLAN_INT_STATUS_THERM_GET(x)             (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB)
+#define WLAN_INT_STATUS_THERM_SET(x)             (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB      19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB      19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK     0x00080000
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)   (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)   (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK)
+#define WLAN_INT_STATUS_UART_MBOX_MSB            18
+#define WLAN_INT_STATUS_UART_MBOX_LSB            18
+#define WLAN_INT_STATUS_UART_MBOX_MASK           0x00040000
+#define WLAN_INT_STATUS_UART_MBOX_GET(x)         (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB)
+#define WLAN_INT_STATUS_UART_MBOX_SET(x)         (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK)
+#define WLAN_INT_STATUS_GENERIC_MBOX_MSB         17
+#define WLAN_INT_STATUS_GENERIC_MBOX_LSB         17
+#define WLAN_INT_STATUS_GENERIC_MBOX_MASK        0x00020000
+#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x)      (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB)
+#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x)      (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK)
+#define WLAN_INT_STATUS_RDMA_MSB                 16
+#define WLAN_INT_STATUS_RDMA_LSB                 16
+#define WLAN_INT_STATUS_RDMA_MASK                0x00010000
+#define WLAN_INT_STATUS_RDMA_GET(x)              (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB)
+#define WLAN_INT_STATUS_RDMA_SET(x)              (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK)
+#define WLAN_INT_STATUS_BTCOEX_MSB               15
+#define WLAN_INT_STATUS_BTCOEX_LSB               15
+#define WLAN_INT_STATUS_BTCOEX_MASK              0x00008000
+#define WLAN_INT_STATUS_BTCOEX_GET(x)            (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB)
+#define WLAN_INT_STATUS_BTCOEX_SET(x)            (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK)
+#define WLAN_INT_STATUS_RTC_POWER_MSB            14
+#define WLAN_INT_STATUS_RTC_POWER_LSB            14
+#define WLAN_INT_STATUS_RTC_POWER_MASK           0x00004000
+#define WLAN_INT_STATUS_RTC_POWER_GET(x)         (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB)
+#define WLAN_INT_STATUS_RTC_POWER_SET(x)         (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK)
+#define WLAN_INT_STATUS_MAC_MSB                  13
+#define WLAN_INT_STATUS_MAC_LSB                  13
+#define WLAN_INT_STATUS_MAC_MASK                 0x00002000
+#define WLAN_INT_STATUS_MAC_GET(x)               (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB)
+#define WLAN_INT_STATUS_MAC_SET(x)               (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK)
+#define WLAN_INT_STATUS_MAILBOX_MSB              12
+#define WLAN_INT_STATUS_MAILBOX_LSB              12
+#define WLAN_INT_STATUS_MAILBOX_MASK             0x00001000
+#define WLAN_INT_STATUS_MAILBOX_GET(x)           (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB)
+#define WLAN_INT_STATUS_MAILBOX_SET(x)           (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK)
+#define WLAN_INT_STATUS_RTC_ALARM_MSB            11
+#define WLAN_INT_STATUS_RTC_ALARM_LSB            11
+#define WLAN_INT_STATUS_RTC_ALARM_MASK           0x00000800
+#define WLAN_INT_STATUS_RTC_ALARM_GET(x)         (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB)
+#define WLAN_INT_STATUS_RTC_ALARM_SET(x)         (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK)
+#define WLAN_INT_STATUS_HF_TIMER_MSB             10
+#define WLAN_INT_STATUS_HF_TIMER_LSB             10
+#define WLAN_INT_STATUS_HF_TIMER_MASK            0x00000400
+#define WLAN_INT_STATUS_HF_TIMER_GET(x)          (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB)
+#define WLAN_INT_STATUS_HF_TIMER_SET(x)          (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK)
+#define WLAN_INT_STATUS_LF_TIMER3_MSB            9
+#define WLAN_INT_STATUS_LF_TIMER3_LSB            9
+#define WLAN_INT_STATUS_LF_TIMER3_MASK           0x00000200
+#define WLAN_INT_STATUS_LF_TIMER3_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB)
+#define WLAN_INT_STATUS_LF_TIMER3_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK)
+#define WLAN_INT_STATUS_LF_TIMER2_MSB            8
+#define WLAN_INT_STATUS_LF_TIMER2_LSB            8
+#define WLAN_INT_STATUS_LF_TIMER2_MASK           0x00000100
+#define WLAN_INT_STATUS_LF_TIMER2_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB)
+#define WLAN_INT_STATUS_LF_TIMER2_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK)
+#define WLAN_INT_STATUS_LF_TIMER1_MSB            7
+#define WLAN_INT_STATUS_LF_TIMER1_LSB            7
+#define WLAN_INT_STATUS_LF_TIMER1_MASK           0x00000080
+#define WLAN_INT_STATUS_LF_TIMER1_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB)
+#define WLAN_INT_STATUS_LF_TIMER1_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK)
+#define WLAN_INT_STATUS_LF_TIMER0_MSB            6
+#define WLAN_INT_STATUS_LF_TIMER0_LSB            6
+#define WLAN_INT_STATUS_LF_TIMER0_MASK           0x00000040
+#define WLAN_INT_STATUS_LF_TIMER0_GET(x)         (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB)
+#define WLAN_INT_STATUS_LF_TIMER0_SET(x)         (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK)
+#define WLAN_INT_STATUS_KEYPAD_MSB               5
+#define WLAN_INT_STATUS_KEYPAD_LSB               5
+#define WLAN_INT_STATUS_KEYPAD_MASK              0x00000020
+#define WLAN_INT_STATUS_KEYPAD_GET(x)            (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB)
+#define WLAN_INT_STATUS_KEYPAD_SET(x)            (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK)
+#define WLAN_INT_STATUS_SI_MSB                   4
+#define WLAN_INT_STATUS_SI_LSB                   4
+#define WLAN_INT_STATUS_SI_MASK                  0x00000010
+#define WLAN_INT_STATUS_SI_GET(x)                (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB)
+#define WLAN_INT_STATUS_SI_SET(x)                (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK)
+#define WLAN_INT_STATUS_GPIO_MSB                 3
+#define WLAN_INT_STATUS_GPIO_LSB                 3
+#define WLAN_INT_STATUS_GPIO_MASK                0x00000008
+#define WLAN_INT_STATUS_GPIO_GET(x)              (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB)
+#define WLAN_INT_STATUS_GPIO_SET(x)              (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK)
+#define WLAN_INT_STATUS_UART_MSB                 2
+#define WLAN_INT_STATUS_UART_LSB                 2
+#define WLAN_INT_STATUS_UART_MASK                0x00000004
+#define WLAN_INT_STATUS_UART_GET(x)              (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB)
+#define WLAN_INT_STATUS_UART_SET(x)              (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK)
+#define WLAN_INT_STATUS_ERROR_MSB                1
+#define WLAN_INT_STATUS_ERROR_LSB                1
+#define WLAN_INT_STATUS_ERROR_MASK               0x00000002
+#define WLAN_INT_STATUS_ERROR_GET(x)             (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB)
+#define WLAN_INT_STATUS_ERROR_SET(x)             (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK)
+#define WLAN_INT_STATUS_WDT_INT_MSB              0
+#define WLAN_INT_STATUS_WDT_INT_LSB              0
+#define WLAN_INT_STATUS_WDT_INT_MASK             0x00000001
+#define WLAN_INT_STATUS_WDT_INT_GET(x)           (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB)
+#define WLAN_INT_STATUS_WDT_INT_SET(x)           (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK)
+
+#define WLAN_LF_TIMER0_ADDRESS                   0x00000048
+#define WLAN_LF_TIMER0_OFFSET                    0x00000048
+#define WLAN_LF_TIMER0_TARGET_MSB                31
+#define WLAN_LF_TIMER0_TARGET_LSB                0
+#define WLAN_LF_TIMER0_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER0_TARGET_GET(x)             (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB)
+#define WLAN_LF_TIMER0_TARGET_SET(x)             (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT0_ADDRESS             0x0000004c
+#define WLAN_LF_TIMER_COUNT0_OFFSET              0x0000004c
+#define WLAN_LF_TIMER_COUNT0_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT0_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT0_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL0_ADDRESS           0x00000050
+#define WLAN_LF_TIMER_CONTROL0_OFFSET            0x00000050
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL0_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL0_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL0_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS0_ADDRESS            0x00000054
+#define WLAN_LF_TIMER_STATUS0_OFFSET             0x00000054
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER1_ADDRESS                   0x00000058
+#define WLAN_LF_TIMER1_OFFSET                    0x00000058
+#define WLAN_LF_TIMER1_TARGET_MSB                31
+#define WLAN_LF_TIMER1_TARGET_LSB                0
+#define WLAN_LF_TIMER1_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER1_TARGET_GET(x)             (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB)
+#define WLAN_LF_TIMER1_TARGET_SET(x)             (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT1_ADDRESS             0x0000005c
+#define WLAN_LF_TIMER_COUNT1_OFFSET              0x0000005c
+#define WLAN_LF_TIMER_COUNT1_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT1_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT1_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL1_ADDRESS           0x00000060
+#define WLAN_LF_TIMER_CONTROL1_OFFSET            0x00000060
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL1_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL1_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL1_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS1_ADDRESS            0x00000064
+#define WLAN_LF_TIMER_STATUS1_OFFSET             0x00000064
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER2_ADDRESS                   0x00000068
+#define WLAN_LF_TIMER2_OFFSET                    0x00000068
+#define WLAN_LF_TIMER2_TARGET_MSB                31
+#define WLAN_LF_TIMER2_TARGET_LSB                0
+#define WLAN_LF_TIMER2_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER2_TARGET_GET(x)             (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB)
+#define WLAN_LF_TIMER2_TARGET_SET(x)             (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT2_ADDRESS             0x0000006c
+#define WLAN_LF_TIMER_COUNT2_OFFSET              0x0000006c
+#define WLAN_LF_TIMER_COUNT2_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT2_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT2_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL2_ADDRESS           0x00000070
+#define WLAN_LF_TIMER_CONTROL2_OFFSET            0x00000070
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL2_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL2_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL2_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS2_ADDRESS            0x00000074
+#define WLAN_LF_TIMER_STATUS2_OFFSET             0x00000074
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER3_ADDRESS                   0x00000078
+#define WLAN_LF_TIMER3_OFFSET                    0x00000078
+#define WLAN_LF_TIMER3_TARGET_MSB                31
+#define WLAN_LF_TIMER3_TARGET_LSB                0
+#define WLAN_LF_TIMER3_TARGET_MASK               0xffffffff
+#define WLAN_LF_TIMER3_TARGET_GET(x)             (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB)
+#define WLAN_LF_TIMER3_TARGET_SET(x)             (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT3_ADDRESS             0x0000007c
+#define WLAN_LF_TIMER_COUNT3_OFFSET              0x0000007c
+#define WLAN_LF_TIMER_COUNT3_VALUE_MSB           31
+#define WLAN_LF_TIMER_COUNT3_VALUE_LSB           0
+#define WLAN_LF_TIMER_COUNT3_VALUE_MASK          0xffffffff
+#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x)        (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x)        (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL3_ADDRESS           0x00000080
+#define WLAN_LF_TIMER_CONTROL3_OFFSET            0x00000080
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB        2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB        2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK       0x00000004
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)     (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)     (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB  1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB  1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL3_RESET_MSB         0
+#define WLAN_LF_TIMER_CONTROL3_RESET_LSB         0
+#define WLAN_LF_TIMER_CONTROL3_RESET_MASK        0x00000001
+#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x)      (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x)      (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS3_ADDRESS            0x00000084
+#define WLAN_LF_TIMER_STATUS3_OFFSET             0x00000084
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB      0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB      0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK     0x00000001
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)   (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)   (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define WLAN_HF_TIMER_ADDRESS                    0x00000088
+#define WLAN_HF_TIMER_OFFSET                     0x00000088
+#define WLAN_HF_TIMER_TARGET_MSB                 31
+#define WLAN_HF_TIMER_TARGET_LSB                 12
+#define WLAN_HF_TIMER_TARGET_MASK                0xfffff000
+#define WLAN_HF_TIMER_TARGET_GET(x)              (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB)
+#define WLAN_HF_TIMER_TARGET_SET(x)              (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK)
+
+#define WLAN_HF_TIMER_COUNT_ADDRESS              0x0000008c
+#define WLAN_HF_TIMER_COUNT_OFFSET               0x0000008c
+#define WLAN_HF_TIMER_COUNT_VALUE_MSB            31
+#define WLAN_HF_TIMER_COUNT_VALUE_LSB            12
+#define WLAN_HF_TIMER_COUNT_VALUE_MASK           0xfffff000
+#define WLAN_HF_TIMER_COUNT_VALUE_GET(x)         (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB)
+#define WLAN_HF_TIMER_COUNT_VALUE_SET(x)         (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK)
+
+#define WLAN_HF_LF_COUNT_ADDRESS                 0x00000090
+#define WLAN_HF_LF_COUNT_OFFSET                  0x00000090
+#define WLAN_HF_LF_COUNT_VALUE_MSB               31
+#define WLAN_HF_LF_COUNT_VALUE_LSB               0
+#define WLAN_HF_LF_COUNT_VALUE_MASK              0xffffffff
+#define WLAN_HF_LF_COUNT_VALUE_GET(x)            (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB)
+#define WLAN_HF_LF_COUNT_VALUE_SET(x)            (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK)
+
+#define WLAN_HF_TIMER_CONTROL_ADDRESS            0x00000094
+#define WLAN_HF_TIMER_CONTROL_OFFSET             0x00000094
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB         3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB         3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK        0x00000008
+#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)      (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB)
+#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)      (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK)
+#define WLAN_HF_TIMER_CONTROL_ON_MSB             2
+#define WLAN_HF_TIMER_CONTROL_ON_LSB             2
+#define WLAN_HF_TIMER_CONTROL_ON_MASK            0x00000004
+#define WLAN_HF_TIMER_CONTROL_ON_GET(x)          (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB)
+#define WLAN_HF_TIMER_CONTROL_ON_SET(x)          (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB   1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB   1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK  0x00000002
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define WLAN_HF_TIMER_CONTROL_RESET_MSB          0
+#define WLAN_HF_TIMER_CONTROL_RESET_LSB          0
+#define WLAN_HF_TIMER_CONTROL_RESET_MASK         0x00000001
+#define WLAN_HF_TIMER_CONTROL_RESET_GET(x)       (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB)
+#define WLAN_HF_TIMER_CONTROL_RESET_SET(x)       (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK)
+
+#define WLAN_HF_TIMER_STATUS_ADDRESS             0x00000098
+#define WLAN_HF_TIMER_STATUS_OFFSET              0x00000098
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB       0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB       0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK      0x00000001
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)    (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB)
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)    (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define WLAN_RTC_CONTROL_ADDRESS                 0x0000009c
+#define WLAN_RTC_CONTROL_OFFSET                  0x0000009c
+#define WLAN_RTC_CONTROL_ENABLE_MSB              2
+#define WLAN_RTC_CONTROL_ENABLE_LSB              2
+#define WLAN_RTC_CONTROL_ENABLE_MASK             0x00000004
+#define WLAN_RTC_CONTROL_ENABLE_GET(x)           (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB)
+#define WLAN_RTC_CONTROL_ENABLE_SET(x)           (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK)
+#define WLAN_RTC_CONTROL_LOAD_RTC_MSB            1
+#define WLAN_RTC_CONTROL_LOAD_RTC_LSB            1
+#define WLAN_RTC_CONTROL_LOAD_RTC_MASK           0x00000002
+#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x)         (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB)
+#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x)         (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB          0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB          0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK         0x00000001
+#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)       (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)       (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define WLAN_RTC_TIME_ADDRESS                    0x000000a0
+#define WLAN_RTC_TIME_OFFSET                     0x000000a0
+#define WLAN_RTC_TIME_WEEK_DAY_MSB               26
+#define WLAN_RTC_TIME_WEEK_DAY_LSB               24
+#define WLAN_RTC_TIME_WEEK_DAY_MASK              0x07000000
+#define WLAN_RTC_TIME_WEEK_DAY_GET(x)            (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_TIME_WEEK_DAY_SET(x)            (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_TIME_HOUR_MSB                   21
+#define WLAN_RTC_TIME_HOUR_LSB                   16
+#define WLAN_RTC_TIME_HOUR_MASK                  0x003f0000
+#define WLAN_RTC_TIME_HOUR_GET(x)                (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB)
+#define WLAN_RTC_TIME_HOUR_SET(x)                (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK)
+#define WLAN_RTC_TIME_MINUTE_MSB                 14
+#define WLAN_RTC_TIME_MINUTE_LSB                 8
+#define WLAN_RTC_TIME_MINUTE_MASK                0x00007f00
+#define WLAN_RTC_TIME_MINUTE_GET(x)              (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB)
+#define WLAN_RTC_TIME_MINUTE_SET(x)              (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK)
+#define WLAN_RTC_TIME_SECOND_MSB                 6
+#define WLAN_RTC_TIME_SECOND_LSB                 0
+#define WLAN_RTC_TIME_SECOND_MASK                0x0000007f
+#define WLAN_RTC_TIME_SECOND_GET(x)              (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB)
+#define WLAN_RTC_TIME_SECOND_SET(x)              (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK)
+
+#define WLAN_RTC_DATE_ADDRESS                    0x000000a4
+#define WLAN_RTC_DATE_OFFSET                     0x000000a4
+#define WLAN_RTC_DATE_YEAR_MSB                   23
+#define WLAN_RTC_DATE_YEAR_LSB                   16
+#define WLAN_RTC_DATE_YEAR_MASK                  0x00ff0000
+#define WLAN_RTC_DATE_YEAR_GET(x)                (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB)
+#define WLAN_RTC_DATE_YEAR_SET(x)                (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK)
+#define WLAN_RTC_DATE_MONTH_MSB                  12
+#define WLAN_RTC_DATE_MONTH_LSB                  8
+#define WLAN_RTC_DATE_MONTH_MASK                 0x00001f00
+#define WLAN_RTC_DATE_MONTH_GET(x)               (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB)
+#define WLAN_RTC_DATE_MONTH_SET(x)               (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK)
+#define WLAN_RTC_DATE_MONTH_DAY_MSB              5
+#define WLAN_RTC_DATE_MONTH_DAY_LSB              0
+#define WLAN_RTC_DATE_MONTH_DAY_MASK             0x0000003f
+#define WLAN_RTC_DATE_MONTH_DAY_GET(x)           (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_DATE_MONTH_DAY_SET(x)           (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_TIME_ADDRESS                0x000000a8
+#define WLAN_RTC_SET_TIME_OFFSET                 0x000000a8
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB           26
+#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB           24
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK          0x07000000
+#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)        (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)        (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_SET_TIME_HOUR_MSB               21
+#define WLAN_RTC_SET_TIME_HOUR_LSB               16
+#define WLAN_RTC_SET_TIME_HOUR_MASK              0x003f0000
+#define WLAN_RTC_SET_TIME_HOUR_GET(x)            (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB)
+#define WLAN_RTC_SET_TIME_HOUR_SET(x)            (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK)
+#define WLAN_RTC_SET_TIME_MINUTE_MSB             14
+#define WLAN_RTC_SET_TIME_MINUTE_LSB             8
+#define WLAN_RTC_SET_TIME_MINUTE_MASK            0x00007f00
+#define WLAN_RTC_SET_TIME_MINUTE_GET(x)          (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB)
+#define WLAN_RTC_SET_TIME_MINUTE_SET(x)          (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK)
+#define WLAN_RTC_SET_TIME_SECOND_MSB             6
+#define WLAN_RTC_SET_TIME_SECOND_LSB             0
+#define WLAN_RTC_SET_TIME_SECOND_MASK            0x0000007f
+#define WLAN_RTC_SET_TIME_SECOND_GET(x)          (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB)
+#define WLAN_RTC_SET_TIME_SECOND_SET(x)          (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK)
+
+#define WLAN_RTC_SET_DATE_ADDRESS                0x000000ac
+#define WLAN_RTC_SET_DATE_OFFSET                 0x000000ac
+#define WLAN_RTC_SET_DATE_YEAR_MSB               23
+#define WLAN_RTC_SET_DATE_YEAR_LSB               16
+#define WLAN_RTC_SET_DATE_YEAR_MASK              0x00ff0000
+#define WLAN_RTC_SET_DATE_YEAR_GET(x)            (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB)
+#define WLAN_RTC_SET_DATE_YEAR_SET(x)            (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_MSB              12
+#define WLAN_RTC_SET_DATE_MONTH_LSB              8
+#define WLAN_RTC_SET_DATE_MONTH_MASK             0x00001f00
+#define WLAN_RTC_SET_DATE_MONTH_GET(x)           (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_SET(x)           (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB          5
+#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB          0
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK         0x0000003f
+#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)       (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)       (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_ALARM_ADDRESS               0x000000b0
+#define WLAN_RTC_SET_ALARM_OFFSET                0x000000b0
+#define WLAN_RTC_SET_ALARM_HOUR_MSB              21
+#define WLAN_RTC_SET_ALARM_HOUR_LSB              16
+#define WLAN_RTC_SET_ALARM_HOUR_MASK             0x003f0000
+#define WLAN_RTC_SET_ALARM_HOUR_GET(x)           (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB)
+#define WLAN_RTC_SET_ALARM_HOUR_SET(x)           (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK)
+#define WLAN_RTC_SET_ALARM_MINUTE_MSB            14
+#define WLAN_RTC_SET_ALARM_MINUTE_LSB            8
+#define WLAN_RTC_SET_ALARM_MINUTE_MASK           0x00007f00
+#define WLAN_RTC_SET_ALARM_MINUTE_GET(x)         (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB)
+#define WLAN_RTC_SET_ALARM_MINUTE_SET(x)         (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK)
+#define WLAN_RTC_SET_ALARM_SECOND_MSB            6
+#define WLAN_RTC_SET_ALARM_SECOND_LSB            0
+#define WLAN_RTC_SET_ALARM_SECOND_MASK           0x0000007f
+#define WLAN_RTC_SET_ALARM_SECOND_GET(x)         (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB)
+#define WLAN_RTC_SET_ALARM_SECOND_SET(x)         (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK)
+
+#define WLAN_RTC_CONFIG_ADDRESS                  0x000000b4
+#define WLAN_RTC_CONFIG_OFFSET                   0x000000b4
+#define WLAN_RTC_CONFIG_BCD_MSB                  2
+#define WLAN_RTC_CONFIG_BCD_LSB                  2
+#define WLAN_RTC_CONFIG_BCD_MASK                 0x00000004
+#define WLAN_RTC_CONFIG_BCD_GET(x)               (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB)
+#define WLAN_RTC_CONFIG_BCD_SET(x)               (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB          1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB          1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK         0x00000002
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)       (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)       (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK)
+#define WLAN_RTC_CONFIG_DSE_MSB                  0
+#define WLAN_RTC_CONFIG_DSE_LSB                  0
+#define WLAN_RTC_CONFIG_DSE_MASK                 0x00000001
+#define WLAN_RTC_CONFIG_DSE_GET(x)               (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB)
+#define WLAN_RTC_CONFIG_DSE_SET(x)               (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK)
+
+#define WLAN_RTC_ALARM_STATUS_ADDRESS            0x000000b8
+#define WLAN_RTC_ALARM_STATUS_OFFSET             0x000000b8
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB         1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB         1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK        0x00000002
+#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)      (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB)
+#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)      (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB      0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB      0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK     0x00000001
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)   (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)   (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define WLAN_UART_WAKEUP_ADDRESS                 0x000000bc
+#define WLAN_UART_WAKEUP_OFFSET                  0x000000bc
+#define WLAN_UART_WAKEUP_ENABLE_MSB              0
+#define WLAN_UART_WAKEUP_ENABLE_LSB              0
+#define WLAN_UART_WAKEUP_ENABLE_MASK             0x00000001
+#define WLAN_UART_WAKEUP_ENABLE_GET(x)           (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB)
+#define WLAN_UART_WAKEUP_ENABLE_SET(x)           (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK)
+
+#define WLAN_RESET_CAUSE_ADDRESS                 0x000000c0
+#define WLAN_RESET_CAUSE_OFFSET                  0x000000c0
+#define WLAN_RESET_CAUSE_LAST_MSB                2
+#define WLAN_RESET_CAUSE_LAST_LSB                0
+#define WLAN_RESET_CAUSE_LAST_MASK               0x00000007
+#define WLAN_RESET_CAUSE_LAST_GET(x)             (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB)
+#define WLAN_RESET_CAUSE_LAST_SET(x)             (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK)
+
+#define WLAN_SYSTEM_SLEEP_ADDRESS                0x000000c4
+#define WLAN_SYSTEM_SLEEP_OFFSET                 0x000000c4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB            4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB            4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK           0x00000010
+#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)         (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)         (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_MBOX_MSB               3
+#define WLAN_SYSTEM_SLEEP_MBOX_LSB               3
+#define WLAN_SYSTEM_SLEEP_MBOX_MASK              0x00000008
+#define WLAN_SYSTEM_SLEEP_MBOX_GET(x)            (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB)
+#define WLAN_SYSTEM_SLEEP_MBOX_SET(x)            (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB             2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB             2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK            0x00000004
+#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)          (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)          (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_LIGHT_MSB              1
+#define WLAN_SYSTEM_SLEEP_LIGHT_LSB              1
+#define WLAN_SYSTEM_SLEEP_LIGHT_MASK             0x00000002
+#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x)           (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB)
+#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x)           (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK)
+#define WLAN_SYSTEM_SLEEP_DISABLE_MSB            0
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
+#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x)         (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB)
+#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x)         (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
+
+#define WLAN_SDIO_WRAPPER_ADDRESS                0x000000c8
+#define WLAN_SDIO_WRAPPER_OFFSET                 0x000000c8
+#define WLAN_SDIO_WRAPPER_SLEEP_MSB              3
+#define WLAN_SDIO_WRAPPER_SLEEP_LSB              3
+#define WLAN_SDIO_WRAPPER_SLEEP_MASK             0x00000008
+#define WLAN_SDIO_WRAPPER_SLEEP_GET(x)           (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB)
+#define WLAN_SDIO_WRAPPER_SLEEP_SET(x)           (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK)
+#define WLAN_SDIO_WRAPPER_WAKEUP_MSB             2
+#define WLAN_SDIO_WRAPPER_WAKEUP_LSB             2
+#define WLAN_SDIO_WRAPPER_WAKEUP_MASK            0x00000004
+#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x)          (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB)
+#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x)          (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK)
+#define WLAN_SDIO_WRAPPER_SOC_ON_MSB             1
+#define WLAN_SDIO_WRAPPER_SOC_ON_LSB             1
+#define WLAN_SDIO_WRAPPER_SOC_ON_MASK            0x00000002
+#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x)          (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB)
+#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x)          (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK)
+#define WLAN_SDIO_WRAPPER_ON_MSB                 0
+#define WLAN_SDIO_WRAPPER_ON_LSB                 0
+#define WLAN_SDIO_WRAPPER_ON_MASK                0x00000001
+#define WLAN_SDIO_WRAPPER_ON_GET(x)              (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB)
+#define WLAN_SDIO_WRAPPER_ON_SET(x)              (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK)
+
+#define WLAN_MAC_SLEEP_CONTROL_ADDRESS           0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_OFFSET            0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB        1
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB        0
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK       0x00000003
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)     (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)     (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define WLAN_KEEP_AWAKE_ADDRESS                  0x000000d0
+#define WLAN_KEEP_AWAKE_OFFSET                   0x000000d0
+#define WLAN_KEEP_AWAKE_COUNT_MSB                7
+#define WLAN_KEEP_AWAKE_COUNT_LSB                0
+#define WLAN_KEEP_AWAKE_COUNT_MASK               0x000000ff
+#define WLAN_KEEP_AWAKE_COUNT_GET(x)             (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB)
+#define WLAN_KEEP_AWAKE_COUNT_SET(x)             (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TIME_ADDRESS                0x000000d4
+#define WLAN_LPO_CAL_TIME_OFFSET                 0x000000d4
+#define WLAN_LPO_CAL_TIME_LENGTH_MSB             13
+#define WLAN_LPO_CAL_TIME_LENGTH_LSB             0
+#define WLAN_LPO_CAL_TIME_LENGTH_MASK            0x00003fff
+#define WLAN_LPO_CAL_TIME_LENGTH_GET(x)          (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB)
+#define WLAN_LPO_CAL_TIME_LENGTH_SET(x)          (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS       0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET        0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB     23
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB     0
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK    0x00ffffff
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)  (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)  (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS  0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET   0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define WLAN_LPO_CAL_ADDRESS                     0x000000e0
+#define WLAN_LPO_CAL_OFFSET                      0x000000e0
+#define WLAN_LPO_CAL_ENABLE_MSB                  20
+#define WLAN_LPO_CAL_ENABLE_LSB                  20
+#define WLAN_LPO_CAL_ENABLE_MASK                 0x00100000
+#define WLAN_LPO_CAL_ENABLE_GET(x)               (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB)
+#define WLAN_LPO_CAL_ENABLE_SET(x)               (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK)
+#define WLAN_LPO_CAL_COUNT_MSB                   19
+#define WLAN_LPO_CAL_COUNT_LSB                   0
+#define WLAN_LPO_CAL_COUNT_MASK                  0x000fffff
+#define WLAN_LPO_CAL_COUNT_GET(x)                (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB)
+#define WLAN_LPO_CAL_COUNT_SET(x)                (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS        0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET         0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB     5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB     5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK    0x00000020
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)  (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)  (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS         0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_OFFSET          0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB       16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB       16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK      0x00010000
+#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)    (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)    (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB       15
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB       0
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK      0x0000ffff
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)    (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)    (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define WLAN_CHIP_ID_ADDRESS                     0x000000ec
+#define WLAN_CHIP_ID_OFFSET                      0x000000ec
+#define WLAN_CHIP_ID_DEVICE_ID_MSB               31
+#define WLAN_CHIP_ID_DEVICE_ID_LSB               16
+#define WLAN_CHIP_ID_DEVICE_ID_MASK              0xffff0000
+#define WLAN_CHIP_ID_DEVICE_ID_GET(x)            (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB)
+#define WLAN_CHIP_ID_DEVICE_ID_SET(x)            (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK)
+#define WLAN_CHIP_ID_CONFIG_ID_MSB               15
+#define WLAN_CHIP_ID_CONFIG_ID_LSB               4
+#define WLAN_CHIP_ID_CONFIG_ID_MASK              0x0000fff0
+#define WLAN_CHIP_ID_CONFIG_ID_GET(x)            (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB)
+#define WLAN_CHIP_ID_CONFIG_ID_SET(x)            (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK)
+#define WLAN_CHIP_ID_VERSION_ID_MSB              3
+#define WLAN_CHIP_ID_VERSION_ID_LSB              0
+#define WLAN_CHIP_ID_VERSION_ID_MASK             0x0000000f
+#define WLAN_CHIP_ID_VERSION_ID_GET(x)           (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB)
+#define WLAN_CHIP_ID_VERSION_ID_SET(x)           (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK)
+
+#define WLAN_DERIVED_RTC_CLK_ADDRESS             0x000000f0
+#define WLAN_DERIVED_RTC_CLK_OFFSET              0x000000f0
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define WLAN_DERIVED_RTC_CLK_FORCE_MSB           17
+#define WLAN_DERIVED_RTC_CLK_FORCE_LSB           16
+#define WLAN_DERIVED_RTC_CLK_FORCE_MASK          0x00030000
+#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x)        (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB)
+#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x)        (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB          15
+#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB          1
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK         0x0000fffe
+#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)       (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)       (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS               0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET                0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB     22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB     22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK    0x00400000
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x)  (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x)  (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB  21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB  21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_ENABLE_MSB            20
+#define MAC_PCU_SLP32_MODE_ENABLE_LSB            20
+#define MAC_PCU_SLP32_MODE_ENABLE_MASK           0x00100000
+#define MAC_PCU_SLP32_MODE_ENABLE_GET(x)         (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB)
+#define MAC_PCU_SLP32_MODE_ENABLE_SET(x)         (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB  19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB  0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS               0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET                0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB          15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB          0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK         0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x)       (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x)       (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS                0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET                 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB            19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB            0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK           0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x)         (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x)         (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS                 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET                  0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB           31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB           0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS                 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET                  0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB           31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB           0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK          0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x)        (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x)        (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS                 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET                  0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB             1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK            0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x)          (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x)          (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB             0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK            0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x)          (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x)          (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define WLAN_POWER_REG_ADDRESS                   0x0000010c
+#define WLAN_POWER_REG_OFFSET                    0x0000010c
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB)
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK)
+#define WLAN_POWER_REG_DEBUG_EN_MSB              14
+#define WLAN_POWER_REG_DEBUG_EN_LSB              14
+#define WLAN_POWER_REG_DEBUG_EN_MASK             0x00004000
+#define WLAN_POWER_REG_DEBUG_EN_GET(x)           (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB)
+#define WLAN_POWER_REG_DEBUG_EN_SET(x)           (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB        13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB        13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK       0x00002000
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)     (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)     (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB       12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB       12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK      0x00001000
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)    (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)    (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK)
+#define WLAN_POWER_REG_VLVL_MSB                  11
+#define WLAN_POWER_REG_VLVL_LSB                  8
+#define WLAN_POWER_REG_VLVL_MASK                 0x00000f00
+#define WLAN_POWER_REG_VLVL_GET(x)               (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB)
+#define WLAN_POWER_REG_VLVL_SET(x)               (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB        7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB        7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK       0x00000080
+#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)     (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)     (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB          6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB          6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK         0x00000040
+#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)       (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)       (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB         5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB         5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK        0x00000020
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)      (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)      (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK)
+#define WLAN_POWER_REG_RADIO_PWD_EN_MSB          4
+#define WLAN_POWER_REG_RADIO_PWD_EN_LSB          4
+#define WLAN_POWER_REG_RADIO_PWD_EN_MASK         0x00000010
+#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x)       (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB)
+#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x)       (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK)
+#define WLAN_POWER_REG_SOC_ISO_EN_MSB            3
+#define WLAN_POWER_REG_SOC_ISO_EN_LSB            3
+#define WLAN_POWER_REG_SOC_ISO_EN_MASK           0x00000008
+#define WLAN_POWER_REG_SOC_ISO_EN_GET(x)         (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB)
+#define WLAN_POWER_REG_SOC_ISO_EN_SET(x)         (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_EN_MSB           2
+#define WLAN_POWER_REG_WLAN_ISO_EN_LSB           2
+#define WLAN_POWER_REG_WLAN_ISO_EN_MASK          0x00000004
+#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x)        (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x)        (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_PWD_EN_MSB           1
+#define WLAN_POWER_REG_WLAN_PWD_EN_LSB           1
+#define WLAN_POWER_REG_WLAN_PWD_EN_MASK          0x00000002
+#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x)        (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x)        (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK)
+#define WLAN_POWER_REG_POWER_EN_MSB              0
+#define WLAN_POWER_REG_POWER_EN_LSB              0
+#define WLAN_POWER_REG_POWER_EN_MASK             0x00000001
+#define WLAN_POWER_REG_POWER_EN_GET(x)           (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB)
+#define WLAN_POWER_REG_POWER_EN_SET(x)           (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK)
+
+#define WLAN_CORE_CLK_CTRL_ADDRESS               0x00000110
+#define WLAN_CORE_CLK_CTRL_OFFSET                0x00000110
+#define WLAN_CORE_CLK_CTRL_DIV_MSB               2
+#define WLAN_CORE_CLK_CTRL_DIV_LSB               0
+#define WLAN_CORE_CLK_CTRL_DIV_MASK              0x00000007
+#define WLAN_CORE_CLK_CTRL_DIV_GET(x)            (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB)
+#define WLAN_CORE_CLK_CTRL_DIV_SET(x)            (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK)
+
+#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS         0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET          0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB      0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB      0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK     0x00000001
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)   (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)   (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+#define HT_ADDRESS                               0x00000118
+#define HT_OFFSET                                0x00000118
+#define HT_MODE_MSB                              0
+#define HT_MODE_LSB                              0
+#define HT_MODE_MASK                             0x00000001
+#define HT_MODE_GET(x)                           (((x) & HT_MODE_MASK) >> HT_MODE_LSB)
+#define HT_MODE_SET(x)                           (((x) << HT_MODE_LSB) & HT_MODE_MASK)
+
+#define MAC_PCU_TSF_L32_ADDRESS                  0x0000011c
+#define MAC_PCU_TSF_L32_OFFSET                   0x0000011c
+#define MAC_PCU_TSF_L32_VALUE_MSB                31
+#define MAC_PCU_TSF_L32_VALUE_LSB                0
+#define MAC_PCU_TSF_L32_VALUE_MASK               0xffffffff
+#define MAC_PCU_TSF_L32_VALUE_GET(x)             (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB)
+#define MAC_PCU_TSF_L32_VALUE_SET(x)             (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF_U32_ADDRESS                  0x00000120
+#define MAC_PCU_TSF_U32_OFFSET                   0x00000120
+#define MAC_PCU_TSF_U32_VALUE_MSB                31
+#define MAC_PCU_TSF_U32_VALUE_LSB                0
+#define MAC_PCU_TSF_U32_VALUE_MASK               0xffffffff
+#define MAC_PCU_TSF_U32_VALUE_GET(x)             (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB)
+#define MAC_PCU_TSF_U32_VALUE_SET(x)             (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK)
+
+#define MAC_PCU_WBTIMER_ADDRESS                  0x00000124
+#define MAC_PCU_WBTIMER_OFFSET                   0x00000124
+#define MAC_PCU_WBTIMER_VALUE_MSB                31
+#define MAC_PCU_WBTIMER_VALUE_LSB                0
+#define MAC_PCU_WBTIMER_VALUE_MASK               0xffffffff
+#define MAC_PCU_WBTIMER_VALUE_GET(x)             (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB)
+#define MAC_PCU_WBTIMER_VALUE_SET(x)             (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_ADDRESS           0x00000140
+#define MAC_PCU_GENERIC_TIMERS_OFFSET            0x00000140
+#define MAC_PCU_GENERIC_TIMERS_DATA_MSB          31
+#define MAC_PCU_GENERIC_TIMERS_DATA_LSB          0
+#define MAC_PCU_GENERIC_TIMERS_DATA_MASK         0xffffffff
+#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x)       (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x)       (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS      0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET       0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB   15
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB   0
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK  0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS2_ADDRESS          0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_OFFSET           0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB         31
+#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB         0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK        0xffffffff
+#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x)      (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x)      (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS     0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET      0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB  15
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB  0
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK)
+
+#define MAC_PCU_SLP1_ADDRESS                     0x00000204
+#define MAC_PCU_SLP1_OFFSET                      0x00000204
+#define MAC_PCU_SLP1_ASSUME_DTIM_MSB             19
+#define MAC_PCU_SLP1_ASSUME_DTIM_LSB             19
+#define MAC_PCU_SLP1_ASSUME_DTIM_MASK            0x00080000
+#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x)          (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB)
+#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x)          (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB             15
+#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB             0
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK            0x0000ffff
+#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x)          (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x)          (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK)
+
+#define MAC_PCU_SLP2_ADDRESS                     0x00000208
+#define MAC_PCU_SLP2_OFFSET                      0x00000208
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB          15
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB          0
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK         0x0000ffff
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x)       (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB)
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x)       (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK)
+
+#define MAC_PCU_RESET_TSF_ADDRESS                0x0000020c
+#define MAC_PCU_RESET_TSF_OFFSET                 0x0000020c
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB          25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB          25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK         0x02000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x)       (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x)       (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB           24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB           24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK          0x01000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x)        (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x)        (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK)
+
+#define MAC_PCU_TSF_ADD_PLL_ADDRESS              0x00000210
+#define MAC_PCU_TSF_ADD_PLL_OFFSET               0x00000210
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB            7
+#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB            0
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK           0x000000ff
+#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x)         (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB)
+#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x)         (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK)
+
+#define SLEEP_RETENTION_ADDRESS                  0x00000214
+#define SLEEP_RETENTION_OFFSET                   0x00000214
+#define SLEEP_RETENTION_TIME_MSB                 9
+#define SLEEP_RETENTION_TIME_LSB                 2
+#define SLEEP_RETENTION_TIME_MASK                0x000003fc
+#define SLEEP_RETENTION_TIME_GET(x)              (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
+#define SLEEP_RETENTION_TIME_SET(x)              (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
+#define SLEEP_RETENTION_MODE_MSB                 1
+#define SLEEP_RETENTION_MODE_LSB                 1
+#define SLEEP_RETENTION_MODE_MASK                0x00000002
+#define SLEEP_RETENTION_MODE_GET(x)              (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
+#define SLEEP_RETENTION_MODE_SET(x)              (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
+#define SLEEP_RETENTION_ENABLE_MSB               0
+#define SLEEP_RETENTION_ENABLE_LSB               0
+#define SLEEP_RETENTION_ENABLE_MASK              0x00000001
+#define SLEEP_RETENTION_ENABLE_GET(x)            (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
+#define SLEEP_RETENTION_ENABLE_SET(x)            (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
+
+#define BTCOEXCTRL_ADDRESS                       0x00000218
+#define BTCOEXCTRL_OFFSET                        0x00000218
+#define BTCOEXCTRL_WBTIMER_ENABLE_MSB            26
+#define BTCOEXCTRL_WBTIMER_ENABLE_LSB            26
+#define BTCOEXCTRL_WBTIMER_ENABLE_MASK           0x04000000
+#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x)         (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB)
+#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x)         (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB          25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB          25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK         0x02000000
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x)       (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x)       (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK)
+#define BTCOEXCTRL_PTA_MODE_MSB                  24
+#define BTCOEXCTRL_PTA_MODE_LSB                  23
+#define BTCOEXCTRL_PTA_MODE_MASK                 0x01800000
+#define BTCOEXCTRL_PTA_MODE_GET(x)               (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB)
+#define BTCOEXCTRL_PTA_MODE_SET(x)               (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK)
+#define BTCOEXCTRL_FREQ_TIME_MSB                 22
+#define BTCOEXCTRL_FREQ_TIME_LSB                 18
+#define BTCOEXCTRL_FREQ_TIME_MASK                0x007c0000
+#define BTCOEXCTRL_FREQ_TIME_GET(x)              (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB)
+#define BTCOEXCTRL_FREQ_TIME_SET(x)              (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK)
+#define BTCOEXCTRL_PRIORITY_TIME_MSB             17
+#define BTCOEXCTRL_PRIORITY_TIME_LSB             12
+#define BTCOEXCTRL_PRIORITY_TIME_MASK            0x0003f000
+#define BTCOEXCTRL_PRIORITY_TIME_GET(x)          (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB)
+#define BTCOEXCTRL_PRIORITY_TIME_SET(x)          (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK)
+#define BTCOEXCTRL_SYNC_DET_EN_MSB               11
+#define BTCOEXCTRL_SYNC_DET_EN_LSB               11
+#define BTCOEXCTRL_SYNC_DET_EN_MASK              0x00000800
+#define BTCOEXCTRL_SYNC_DET_EN_GET(x)            (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB)
+#define BTCOEXCTRL_SYNC_DET_EN_SET(x)            (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK)
+#define BTCOEXCTRL_IDLE_CNT_EN_MSB               10
+#define BTCOEXCTRL_IDLE_CNT_EN_LSB               10
+#define BTCOEXCTRL_IDLE_CNT_EN_MASK              0x00000400
+#define BTCOEXCTRL_IDLE_CNT_EN_GET(x)            (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB)
+#define BTCOEXCTRL_IDLE_CNT_EN_SET(x)            (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK)
+#define BTCOEXCTRL_FRAME_CNT_EN_MSB              9
+#define BTCOEXCTRL_FRAME_CNT_EN_LSB              9
+#define BTCOEXCTRL_FRAME_CNT_EN_MASK             0x00000200
+#define BTCOEXCTRL_FRAME_CNT_EN_GET(x)           (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB)
+#define BTCOEXCTRL_FRAME_CNT_EN_SET(x)           (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK)
+#define BTCOEXCTRL_CLK_CNT_EN_MSB                8
+#define BTCOEXCTRL_CLK_CNT_EN_LSB                8
+#define BTCOEXCTRL_CLK_CNT_EN_MASK               0x00000100
+#define BTCOEXCTRL_CLK_CNT_EN_GET(x)             (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB)
+#define BTCOEXCTRL_CLK_CNT_EN_SET(x)             (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK)
+#define BTCOEXCTRL_GAP_MSB                       7
+#define BTCOEXCTRL_GAP_LSB                       0
+#define BTCOEXCTRL_GAP_MASK                      0x000000ff
+#define BTCOEXCTRL_GAP_GET(x)                    (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB)
+#define BTCOEXCTRL_GAP_SET(x)                    (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK)
+
+#define WBSYNC_PRIORITY1_ADDRESS                 0x0000021c
+#define WBSYNC_PRIORITY1_OFFSET                  0x0000021c
+#define WBSYNC_PRIORITY1_BITMAP_MSB              31
+#define WBSYNC_PRIORITY1_BITMAP_LSB              0
+#define WBSYNC_PRIORITY1_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY1_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB)
+#define WBSYNC_PRIORITY1_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY2_ADDRESS                 0x00000220
+#define WBSYNC_PRIORITY2_OFFSET                  0x00000220
+#define WBSYNC_PRIORITY2_BITMAP_MSB              31
+#define WBSYNC_PRIORITY2_BITMAP_LSB              0
+#define WBSYNC_PRIORITY2_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY2_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB)
+#define WBSYNC_PRIORITY2_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY3_ADDRESS                 0x00000224
+#define WBSYNC_PRIORITY3_OFFSET                  0x00000224
+#define WBSYNC_PRIORITY3_BITMAP_MSB              31
+#define WBSYNC_PRIORITY3_BITMAP_LSB              0
+#define WBSYNC_PRIORITY3_BITMAP_MASK             0xffffffff
+#define WBSYNC_PRIORITY3_BITMAP_GET(x)           (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB)
+#define WBSYNC_PRIORITY3_BITMAP_SET(x)           (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK)
+
+#define BTCOEX0_ADDRESS                          0x00000228
+#define BTCOEX0_OFFSET                           0x00000228
+#define BTCOEX0_SYNC_DUR_MSB                     7
+#define BTCOEX0_SYNC_DUR_LSB                     0
+#define BTCOEX0_SYNC_DUR_MASK                    0x000000ff
+#define BTCOEX0_SYNC_DUR_GET(x)                  (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB)
+#define BTCOEX0_SYNC_DUR_SET(x)                  (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK)
+
+#define BTCOEX1_ADDRESS                          0x0000022c
+#define BTCOEX1_OFFSET                           0x0000022c
+#define BTCOEX1_CLK_THRES_MSB                    20
+#define BTCOEX1_CLK_THRES_LSB                    0
+#define BTCOEX1_CLK_THRES_MASK                   0x001fffff
+#define BTCOEX1_CLK_THRES_GET(x)                 (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB)
+#define BTCOEX1_CLK_THRES_SET(x)                 (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK)
+
+#define BTCOEX2_ADDRESS                          0x00000230
+#define BTCOEX2_OFFSET                           0x00000230
+#define BTCOEX2_FRAME_THRES_MSB                  7
+#define BTCOEX2_FRAME_THRES_LSB                  0
+#define BTCOEX2_FRAME_THRES_MASK                 0x000000ff
+#define BTCOEX2_FRAME_THRES_GET(x)               (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB)
+#define BTCOEX2_FRAME_THRES_SET(x)               (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK)
+
+#define BTCOEX3_ADDRESS                          0x00000234
+#define BTCOEX3_OFFSET                           0x00000234
+#define BTCOEX3_CLK_CNT_MSB                      20
+#define BTCOEX3_CLK_CNT_LSB                      0
+#define BTCOEX3_CLK_CNT_MASK                     0x001fffff
+#define BTCOEX3_CLK_CNT_GET(x)                   (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB)
+#define BTCOEX3_CLK_CNT_SET(x)                   (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK)
+
+#define BTCOEX4_ADDRESS                          0x00000238
+#define BTCOEX4_OFFSET                           0x00000238
+#define BTCOEX4_FRAME_CNT_MSB                    7
+#define BTCOEX4_FRAME_CNT_LSB                    0
+#define BTCOEX4_FRAME_CNT_MASK                   0x000000ff
+#define BTCOEX4_FRAME_CNT_GET(x)                 (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB)
+#define BTCOEX4_FRAME_CNT_SET(x)                 (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK)
+
+#define BTCOEX5_ADDRESS                          0x0000023c
+#define BTCOEX5_OFFSET                           0x0000023c
+#define BTCOEX5_IDLE_CNT_MSB                     15
+#define BTCOEX5_IDLE_CNT_LSB                     0
+#define BTCOEX5_IDLE_CNT_MASK                    0x0000ffff
+#define BTCOEX5_IDLE_CNT_GET(x)                  (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB)
+#define BTCOEX5_IDLE_CNT_SET(x)                  (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK)
+
+#define BTCOEX6_ADDRESS                          0x00000240
+#define BTCOEX6_OFFSET                           0x00000240
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB        31
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB        0
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK       0xffffffff
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x)     (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB)
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x)     (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK)
+
+#define LOCK_ADDRESS                             0x00000244
+#define LOCK_OFFSET                              0x00000244
+#define LOCK_TLOCK_SLAVE_MSB                     31
+#define LOCK_TLOCK_SLAVE_LSB                     24
+#define LOCK_TLOCK_SLAVE_MASK                    0xff000000
+#define LOCK_TLOCK_SLAVE_GET(x)                  (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB)
+#define LOCK_TLOCK_SLAVE_SET(x)                  (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK)
+#define LOCK_TUNLOCK_SLAVE_MSB                   23
+#define LOCK_TUNLOCK_SLAVE_LSB                   16
+#define LOCK_TUNLOCK_SLAVE_MASK                  0x00ff0000
+#define LOCK_TUNLOCK_SLAVE_GET(x)                (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB)
+#define LOCK_TUNLOCK_SLAVE_SET(x)                (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK)
+#define LOCK_TLOCK_MASTER_MSB                    15
+#define LOCK_TLOCK_MASTER_LSB                    8
+#define LOCK_TLOCK_MASTER_MASK                   0x0000ff00
+#define LOCK_TLOCK_MASTER_GET(x)                 (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB)
+#define LOCK_TLOCK_MASTER_SET(x)                 (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK)
+#define LOCK_TUNLOCK_MASTER_MSB                  7
+#define LOCK_TUNLOCK_MASTER_LSB                  0
+#define LOCK_TUNLOCK_MASTER_MASK                 0x000000ff
+#define LOCK_TUNLOCK_MASTER_GET(x)               (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB)
+#define LOCK_TUNLOCK_MASTER_SET(x)               (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK)
+
+#define NOLOCK_PRIORITY_ADDRESS                  0x00000248
+#define NOLOCK_PRIORITY_OFFSET                   0x00000248
+#define NOLOCK_PRIORITY_BITMAP_MSB               31
+#define NOLOCK_PRIORITY_BITMAP_LSB               0
+#define NOLOCK_PRIORITY_BITMAP_MASK              0xffffffff
+#define NOLOCK_PRIORITY_BITMAP_GET(x)            (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB)
+#define NOLOCK_PRIORITY_BITMAP_SET(x)            (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK)
+
+#define WBSYNC_ADDRESS                           0x0000024c
+#define WBSYNC_OFFSET                            0x0000024c
+#define WBSYNC_BTCLOCK_MSB                       31
+#define WBSYNC_BTCLOCK_LSB                       0
+#define WBSYNC_BTCLOCK_MASK                      0xffffffff
+#define WBSYNC_BTCLOCK_GET(x)                    (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB)
+#define WBSYNC_BTCLOCK_SET(x)                    (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK)
+
+#define WBSYNC1_ADDRESS                          0x00000250
+#define WBSYNC1_OFFSET                           0x00000250
+#define WBSYNC1_BTCLOCK_MSB                      31
+#define WBSYNC1_BTCLOCK_LSB                      0
+#define WBSYNC1_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC1_BTCLOCK_GET(x)                   (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB)
+#define WBSYNC1_BTCLOCK_SET(x)                   (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK)
+
+#define WBSYNC2_ADDRESS                          0x00000254
+#define WBSYNC2_OFFSET                           0x00000254
+#define WBSYNC2_BTCLOCK_MSB                      31
+#define WBSYNC2_BTCLOCK_LSB                      0
+#define WBSYNC2_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC2_BTCLOCK_GET(x)                   (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB)
+#define WBSYNC2_BTCLOCK_SET(x)                   (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK)
+
+#define WBSYNC3_ADDRESS                          0x00000258
+#define WBSYNC3_OFFSET                           0x00000258
+#define WBSYNC3_BTCLOCK_MSB                      31
+#define WBSYNC3_BTCLOCK_LSB                      0
+#define WBSYNC3_BTCLOCK_MASK                     0xffffffff
+#define WBSYNC3_BTCLOCK_GET(x)                   (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB)
+#define WBSYNC3_BTCLOCK_SET(x)                   (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK)
+
+#define WB_TIMER_TARGET_ADDRESS                  0x0000025c
+#define WB_TIMER_TARGET_OFFSET                   0x0000025c
+#define WB_TIMER_TARGET_VALUE_MSB                31
+#define WB_TIMER_TARGET_VALUE_LSB                0
+#define WB_TIMER_TARGET_VALUE_MASK               0xffffffff
+#define WB_TIMER_TARGET_VALUE_GET(x)             (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB)
+#define WB_TIMER_TARGET_VALUE_SET(x)             (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK)
+
+#define WB_TIMER_SLOP_ADDRESS                    0x00000260
+#define WB_TIMER_SLOP_OFFSET                     0x00000260
+#define WB_TIMER_SLOP_VALUE_MSB                  9
+#define WB_TIMER_SLOP_VALUE_LSB                  0
+#define WB_TIMER_SLOP_VALUE_MASK                 0x000003ff
+#define WB_TIMER_SLOP_VALUE_GET(x)               (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB)
+#define WB_TIMER_SLOP_VALUE_SET(x)               (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK)
+
+#define BTCOEX_INT_EN_ADDRESS                    0x00000264
+#define BTCOEX_INT_EN_OFFSET                     0x00000264
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB      11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB      11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK     0x00000800
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x)   (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x)   (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB          10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB          10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK         0x00000400
+#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x)       (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x)       (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB          9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB          9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK         0x00000200
+#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x)       (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x)       (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_EN_ST_MESG_RECV_MSB           8
+#define BTCOEX_INT_EN_ST_MESG_RECV_LSB           8
+#define BTCOEX_INT_EN_ST_MESG_RECV_MASK          0x00000100
+#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x)        (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB)
+#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x)        (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK)
+#define BTCOEX_INT_EN_WB_TIMER_MSB               7
+#define BTCOEX_INT_EN_WB_TIMER_LSB               7
+#define BTCOEX_INT_EN_WB_TIMER_MASK              0x00000080
+#define BTCOEX_INT_EN_WB_TIMER_GET(x)            (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB)
+#define BTCOEX_INT_EN_WB_TIMER_SET(x)            (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK)
+#define BTCOEX_INT_EN_NOSYNC_MSB                 4
+#define BTCOEX_INT_EN_NOSYNC_LSB                 4
+#define BTCOEX_INT_EN_NOSYNC_MASK                0x00000010
+#define BTCOEX_INT_EN_NOSYNC_GET(x)              (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB)
+#define BTCOEX_INT_EN_NOSYNC_SET(x)              (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK)
+#define BTCOEX_INT_EN_SYNC_MSB                   3
+#define BTCOEX_INT_EN_SYNC_LSB                   3
+#define BTCOEX_INT_EN_SYNC_MASK                  0x00000008
+#define BTCOEX_INT_EN_SYNC_GET(x)                (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB)
+#define BTCOEX_INT_EN_SYNC_SET(x)                (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK)
+#define BTCOEX_INT_EN_END_MSB                    2
+#define BTCOEX_INT_EN_END_LSB                    2
+#define BTCOEX_INT_EN_END_MASK                   0x00000004
+#define BTCOEX_INT_EN_END_GET(x)                 (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB)
+#define BTCOEX_INT_EN_END_SET(x)                 (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK)
+#define BTCOEX_INT_EN_FRAME_CNT_MSB              1
+#define BTCOEX_INT_EN_FRAME_CNT_LSB              1
+#define BTCOEX_INT_EN_FRAME_CNT_MASK             0x00000002
+#define BTCOEX_INT_EN_FRAME_CNT_GET(x)           (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB)
+#define BTCOEX_INT_EN_FRAME_CNT_SET(x)           (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK)
+#define BTCOEX_INT_EN_CLK_CNT_MSB                0
+#define BTCOEX_INT_EN_CLK_CNT_LSB                0
+#define BTCOEX_INT_EN_CLK_CNT_MASK               0x00000001
+#define BTCOEX_INT_EN_CLK_CNT_GET(x)             (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB)
+#define BTCOEX_INT_EN_CLK_CNT_SET(x)             (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK)
+
+#define BTCOEX_INT_STAT_ADDRESS                  0x00000268
+#define BTCOEX_INT_STAT_OFFSET                   0x00000268
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB    11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB    11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK   0x00000800
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB        10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB        10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK       0x00000400
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB        9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB        9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK       0x00000200
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB        8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB        8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK       0x00000100
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x)     (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x)     (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK)
+#define BTCOEX_INT_STAT_WB_TIMER_MSB             7
+#define BTCOEX_INT_STAT_WB_TIMER_LSB             7
+#define BTCOEX_INT_STAT_WB_TIMER_MASK            0x00000080
+#define BTCOEX_INT_STAT_WB_TIMER_GET(x)          (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB)
+#define BTCOEX_INT_STAT_WB_TIMER_SET(x)          (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB     6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB     6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK    0x00000040
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x)  (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x)  (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_MSB           5
+#define BTCOEX_INT_STAT_BTPRIORITY_LSB           5
+#define BTCOEX_INT_STAT_BTPRIORITY_MASK          0x00000020
+#define BTCOEX_INT_STAT_BTPRIORITY_GET(x)        (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_SET(x)        (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK)
+#define BTCOEX_INT_STAT_NOSYNC_MSB               4
+#define BTCOEX_INT_STAT_NOSYNC_LSB               4
+#define BTCOEX_INT_STAT_NOSYNC_MASK              0x00000010
+#define BTCOEX_INT_STAT_NOSYNC_GET(x)            (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB)
+#define BTCOEX_INT_STAT_NOSYNC_SET(x)            (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK)
+#define BTCOEX_INT_STAT_SYNC_MSB                 3
+#define BTCOEX_INT_STAT_SYNC_LSB                 3
+#define BTCOEX_INT_STAT_SYNC_MASK                0x00000008
+#define BTCOEX_INT_STAT_SYNC_GET(x)              (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB)
+#define BTCOEX_INT_STAT_SYNC_SET(x)              (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK)
+#define BTCOEX_INT_STAT_END_MSB                  2
+#define BTCOEX_INT_STAT_END_LSB                  2
+#define BTCOEX_INT_STAT_END_MASK                 0x00000004
+#define BTCOEX_INT_STAT_END_GET(x)               (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB)
+#define BTCOEX_INT_STAT_END_SET(x)               (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK)
+#define BTCOEX_INT_STAT_FRAME_CNT_MSB            1
+#define BTCOEX_INT_STAT_FRAME_CNT_LSB            1
+#define BTCOEX_INT_STAT_FRAME_CNT_MASK           0x00000002
+#define BTCOEX_INT_STAT_FRAME_CNT_GET(x)         (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB)
+#define BTCOEX_INT_STAT_FRAME_CNT_SET(x)         (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK)
+#define BTCOEX_INT_STAT_CLK_CNT_MSB              0
+#define BTCOEX_INT_STAT_CLK_CNT_LSB              0
+#define BTCOEX_INT_STAT_CLK_CNT_MASK             0x00000001
+#define BTCOEX_INT_STAT_CLK_CNT_GET(x)           (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB)
+#define BTCOEX_INT_STAT_CLK_CNT_SET(x)           (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK)
+
+#define BTPRIORITY_INT_EN_ADDRESS                0x0000026c
+#define BTPRIORITY_INT_EN_OFFSET                 0x0000026c
+#define BTPRIORITY_INT_EN_BITMAP_MSB             31
+#define BTPRIORITY_INT_EN_BITMAP_LSB             0
+#define BTPRIORITY_INT_EN_BITMAP_MASK            0xffffffff
+#define BTPRIORITY_INT_EN_BITMAP_GET(x)          (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_INT_EN_BITMAP_SET(x)          (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_INT_STAT_ADDRESS              0x00000270
+#define BTPRIORITY_INT_STAT_OFFSET               0x00000270
+#define BTPRIORITY_INT_STAT_BITMAP_MSB           31
+#define BTPRIORITY_INT_STAT_BITMAP_LSB           0
+#define BTPRIORITY_INT_STAT_BITMAP_MASK          0xffffffff
+#define BTPRIORITY_INT_STAT_BITMAP_GET(x)        (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_INT_STAT_BITMAP_SET(x)        (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_EN_ADDRESS          0x00000274
+#define BTPRIORITY_STOMP_INT_EN_OFFSET           0x00000274
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB       31
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB       0
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK      0xffffffff
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x)    (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x)    (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_STAT_ADDRESS        0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_OFFSET         0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB     31
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB     0
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK    0xffffffff
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x)  (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x)  (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK)
+
+#define MAC_PCU_BMISS_TIMEOUT_ADDRESS            0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_OFFSET             0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB         24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB         24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK        0x01000000
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x)      (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x)      (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB          23
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB          0
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK         0x00ffffff
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x)       (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x)       (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_CAB_AWAKE_ADDRESS                0x00000280
+#define MAC_PCU_CAB_AWAKE_OFFSET                 0x00000280
+#define MAC_PCU_CAB_AWAKE_ENABLE_MSB             16
+#define MAC_PCU_CAB_AWAKE_ENABLE_LSB             16
+#define MAC_PCU_CAB_AWAKE_ENABLE_MASK            0x00010000
+#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x)          (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB)
+#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x)          (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK)
+#define MAC_PCU_CAB_AWAKE_DURATION_MSB           15
+#define MAC_PCU_CAB_AWAKE_DURATION_LSB           0
+#define MAC_PCU_CAB_AWAKE_DURATION_MASK          0x0000ffff
+#define MAC_PCU_CAB_AWAKE_DURATION_GET(x)        (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB)
+#define MAC_PCU_CAB_AWAKE_DURATION_SET(x)        (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK)
+
+#define LP_PERF_COUNTER_ADDRESS                  0x00000284
+#define LP_PERF_COUNTER_OFFSET                   0x00000284
+#define LP_PERF_COUNTER_EN_MSB                   0
+#define LP_PERF_COUNTER_EN_LSB                   0
+#define LP_PERF_COUNTER_EN_MASK                  0x00000001
+#define LP_PERF_COUNTER_EN_GET(x)                (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
+#define LP_PERF_COUNTER_EN_SET(x)                (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
+
+#define LP_PERF_LIGHT_SLEEP_ADDRESS              0x00000288
+#define LP_PERF_LIGHT_SLEEP_OFFSET               0x00000288
+#define LP_PERF_LIGHT_SLEEP_CNT_MSB              31
+#define LP_PERF_LIGHT_SLEEP_CNT_LSB              0
+#define LP_PERF_LIGHT_SLEEP_CNT_MASK             0xffffffff
+#define LP_PERF_LIGHT_SLEEP_CNT_GET(x)           (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
+#define LP_PERF_LIGHT_SLEEP_CNT_SET(x)           (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
+
+#define LP_PERF_DEEP_SLEEP_ADDRESS               0x0000028c
+#define LP_PERF_DEEP_SLEEP_OFFSET                0x0000028c
+#define LP_PERF_DEEP_SLEEP_CNT_MSB               31
+#define LP_PERF_DEEP_SLEEP_CNT_LSB               0
+#define LP_PERF_DEEP_SLEEP_CNT_MASK              0xffffffff
+#define LP_PERF_DEEP_SLEEP_CNT_GET(x)            (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
+#define LP_PERF_DEEP_SLEEP_CNT_SET(x)            (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
+
+#define LP_PERF_ON_ADDRESS                       0x00000290
+#define LP_PERF_ON_OFFSET                        0x00000290
+#define LP_PERF_ON_CNT_MSB                       31
+#define LP_PERF_ON_CNT_LSB                       0
+#define LP_PERF_ON_CNT_MASK                      0xffffffff
+#define LP_PERF_ON_CNT_GET(x)                    (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
+#define LP_PERF_ON_CNT_SET(x)                    (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
+
+#define ST_64_BIT_ADDRESS                        0x00000294
+#define ST_64_BIT_OFFSET                         0x00000294
+#define ST_64_BIT_TIMEOUT_MSB                    26
+#define ST_64_BIT_TIMEOUT_LSB                    9
+#define ST_64_BIT_TIMEOUT_MASK                   0x07fffe00
+#define ST_64_BIT_TIMEOUT_GET(x)                 (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB)
+#define ST_64_BIT_TIMEOUT_SET(x)                 (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB    8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB    8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK   0x00000100
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK)
+#define ST_64_BIT_DRIVE_MODE_MSB                 7
+#define ST_64_BIT_DRIVE_MODE_LSB                 7
+#define ST_64_BIT_DRIVE_MODE_MASK                0x00000080
+#define ST_64_BIT_DRIVE_MODE_GET(x)              (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB)
+#define ST_64_BIT_DRIVE_MODE_SET(x)              (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK)
+#define ST_64_BIT_CLOCK_GATE_MSB                 6
+#define ST_64_BIT_CLOCK_GATE_LSB                 6
+#define ST_64_BIT_CLOCK_GATE_MASK                0x00000040
+#define ST_64_BIT_CLOCK_GATE_GET(x)              (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB)
+#define ST_64_BIT_CLOCK_GATE_SET(x)              (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB       5
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB       1
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK      0x0000003e
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x)    (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x)    (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK)
+#define ST_64_BIT_MODE_MSB                       0
+#define ST_64_BIT_MODE_LSB                       0
+#define ST_64_BIT_MODE_MASK                      0x00000001
+#define ST_64_BIT_MODE_GET(x)                    (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB)
+#define ST_64_BIT_MODE_SET(x)                    (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK)
+
+#define MESSAGE_WR_ADDRESS                       0x00000298
+#define MESSAGE_WR_OFFSET                        0x00000298
+#define MESSAGE_WR_TYPE_MSB                      31
+#define MESSAGE_WR_TYPE_LSB                      0
+#define MESSAGE_WR_TYPE_MASK                     0xffffffff
+#define MESSAGE_WR_TYPE_GET(x)                   (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB)
+#define MESSAGE_WR_TYPE_SET(x)                   (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK)
+
+#define MESSAGE_WR_P_ADDRESS                     0x0000029c
+#define MESSAGE_WR_P_OFFSET                      0x0000029c
+#define MESSAGE_WR_P_PARAMETER_MSB               31
+#define MESSAGE_WR_P_PARAMETER_LSB               0
+#define MESSAGE_WR_P_PARAMETER_MASK              0xffffffff
+#define MESSAGE_WR_P_PARAMETER_GET(x)            (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB)
+#define MESSAGE_WR_P_PARAMETER_SET(x)            (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK)
+
+#define MESSAGE_RD_ADDRESS                       0x000002a0
+#define MESSAGE_RD_OFFSET                        0x000002a0
+#define MESSAGE_RD_TYPE_MSB                      31
+#define MESSAGE_RD_TYPE_LSB                      0
+#define MESSAGE_RD_TYPE_MASK                     0xffffffff
+#define MESSAGE_RD_TYPE_GET(x)                   (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB)
+#define MESSAGE_RD_TYPE_SET(x)                   (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK)
+
+#define MESSAGE_RD_P_ADDRESS                     0x000002a4
+#define MESSAGE_RD_P_OFFSET                      0x000002a4
+#define MESSAGE_RD_P_PARAMETER_MSB               31
+#define MESSAGE_RD_P_PARAMETER_LSB               0
+#define MESSAGE_RD_P_PARAMETER_MASK              0xffffffff
+#define MESSAGE_RD_P_PARAMETER_GET(x)            (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB)
+#define MESSAGE_RD_P_PARAMETER_SET(x)            (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK)
+
+#define CHIP_MODE_ADDRESS                        0x000002a8
+#define CHIP_MODE_OFFSET                         0x000002a8
+#define CHIP_MODE_BIT_MSB                        1
+#define CHIP_MODE_BIT_LSB                        0
+#define CHIP_MODE_BIT_MASK                       0x00000003
+#define CHIP_MODE_BIT_GET(x)                     (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
+#define CHIP_MODE_BIT_SET(x)                     (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
+
+#define CLK_REQ_FALL_EDGE_ADDRESS                0x000002ac
+#define CLK_REQ_FALL_EDGE_OFFSET                 0x000002ac
+#define CLK_REQ_FALL_EDGE_EN_MSB                 31
+#define CLK_REQ_FALL_EDGE_EN_LSB                 31
+#define CLK_REQ_FALL_EDGE_EN_MASK                0x80000000
+#define CLK_REQ_FALL_EDGE_EN_GET(x)              (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
+#define CLK_REQ_FALL_EDGE_EN_SET(x)              (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
+#define CLK_REQ_FALL_EDGE_DELAY_MSB              7
+#define CLK_REQ_FALL_EDGE_DELAY_LSB              0
+#define CLK_REQ_FALL_EDGE_DELAY_MASK             0x000000ff
+#define CLK_REQ_FALL_EDGE_DELAY_GET(x)           (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
+#define CLK_REQ_FALL_EDGE_DELAY_SET(x)           (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
+
+#define OTP_ADDRESS                              0x000002b0
+#define OTP_OFFSET                               0x000002b0
+#define OTP_LDO25_EN_MSB                         1
+#define OTP_LDO25_EN_LSB                         1
+#define OTP_LDO25_EN_MASK                        0x00000002
+#define OTP_LDO25_EN_GET(x)                      (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
+#define OTP_LDO25_EN_SET(x)                      (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
+#define OTP_VDD12_EN_MSB                         0
+#define OTP_VDD12_EN_LSB                         0
+#define OTP_VDD12_EN_MASK                        0x00000001
+#define OTP_VDD12_EN_GET(x)                      (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
+#define OTP_VDD12_EN_SET(x)                      (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
+
+#define OTP_STATUS_ADDRESS                       0x000002b4
+#define OTP_STATUS_OFFSET                        0x000002b4
+#define OTP_STATUS_LDO25_EN_READY_MSB            1
+#define OTP_STATUS_LDO25_EN_READY_LSB            1
+#define OTP_STATUS_LDO25_EN_READY_MASK           0x00000002
+#define OTP_STATUS_LDO25_EN_READY_GET(x)         (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
+#define OTP_STATUS_LDO25_EN_READY_SET(x)         (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
+#define OTP_STATUS_VDD12_EN_READY_MSB            0
+#define OTP_STATUS_VDD12_EN_READY_LSB            0
+#define OTP_STATUS_VDD12_EN_READY_MASK           0x00000001
+#define OTP_STATUS_VDD12_EN_READY_GET(x)         (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
+#define OTP_STATUS_VDD12_EN_READY_SET(x)         (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
+
+#define PMU_ADDRESS                              0x000002b8
+#define PMU_OFFSET                               0x000002b8
+#define PMU_REG_WAKEUP_TIME_SEL_MSB              1
+#define PMU_REG_WAKEUP_TIME_SEL_LSB              0
+#define PMU_REG_WAKEUP_TIME_SEL_MASK             0x00000003
+#define PMU_REG_WAKEUP_TIME_SEL_GET(x)           (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
+#define PMU_REG_WAKEUP_TIME_SEL_SET(x)           (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
+
+#define PMU_CONFIG_ADDRESS                       0x000002c0
+#define PMU_CONFIG_OFFSET                        0x000002c0
+#define PMU_CONFIG_VALUE_MSB                     15
+#define PMU_CONFIG_VALUE_LSB                     0
+#define PMU_CONFIG_VALUE_MASK                    0x0000ffff
+#define PMU_CONFIG_VALUE_GET(x)                  (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
+#define PMU_CONFIG_VALUE_SET(x)                  (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
+
+#define PMU_BYPASS_ADDRESS                       0x000002c8
+#define PMU_BYPASS_OFFSET                        0x000002c8
+#define PMU_BYPASS_SWREG_MSB                     2
+#define PMU_BYPASS_SWREG_LSB                     2
+#define PMU_BYPASS_SWREG_MASK                    0x00000004
+#define PMU_BYPASS_SWREG_GET(x)                  (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
+#define PMU_BYPASS_SWREG_SET(x)                  (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
+#define PMU_BYPASS_DREG_MSB                      1
+#define PMU_BYPASS_DREG_LSB                      1
+#define PMU_BYPASS_DREG_MASK                     0x00000002
+#define PMU_BYPASS_DREG_GET(x)                   (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
+#define PMU_BYPASS_DREG_SET(x)                   (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
+#define PMU_BYPASS_PAREG_MSB                     0
+#define PMU_BYPASS_PAREG_LSB                     0
+#define PMU_BYPASS_PAREG_MASK                    0x00000001
+#define PMU_BYPASS_PAREG_GET(x)                  (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
+#define PMU_BYPASS_PAREG_SET(x)                  (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
+
+#define MAC_PCU_TSF2_L32_ADDRESS                 0x000002cc
+#define MAC_PCU_TSF2_L32_OFFSET                  0x000002cc
+#define MAC_PCU_TSF2_L32_VALUE_MSB               31
+#define MAC_PCU_TSF2_L32_VALUE_LSB               0
+#define MAC_PCU_TSF2_L32_VALUE_MASK              0xffffffff
+#define MAC_PCU_TSF2_L32_VALUE_GET(x)            (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_L32_VALUE_SET(x)            (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_U32_ADDRESS                 0x000002d0
+#define MAC_PCU_TSF2_U32_OFFSET                  0x000002d0
+#define MAC_PCU_TSF2_U32_VALUE_MSB               31
+#define MAC_PCU_TSF2_U32_VALUE_LSB               0
+#define MAC_PCU_TSF2_U32_VALUE_MASK              0xffffffff
+#define MAC_PCU_TSF2_U32_VALUE_GET(x)            (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_U32_VALUE_SET(x)            (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS     0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET      0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB  19
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB  0
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK)
+
+#define MAC_PCU_DIRECT_CONNECT_ADDRESS           0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_OFFSET            0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK)
+
+#define THERM_CTRL1_ADDRESS                      0x000002dc
+#define THERM_CTRL1_OFFSET                       0x000002dc
+#define THERM_CTRL1_BYPASS_MSB                   16
+#define THERM_CTRL1_BYPASS_LSB                   16
+#define THERM_CTRL1_BYPASS_MASK                  0x00010000
+#define THERM_CTRL1_BYPASS_GET(x)                (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
+#define THERM_CTRL1_BYPASS_SET(x)                (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
+#define THERM_CTRL1_WIDTH_ARBITOR_MSB            15
+#define THERM_CTRL1_WIDTH_ARBITOR_LSB            12
+#define THERM_CTRL1_WIDTH_ARBITOR_MASK           0x0000f000
+#define THERM_CTRL1_WIDTH_ARBITOR_GET(x)         (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
+#define THERM_CTRL1_WIDTH_ARBITOR_SET(x)         (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
+#define THERM_CTRL1_WIDTH_MSB                    11
+#define THERM_CTRL1_WIDTH_LSB                    5
+#define THERM_CTRL1_WIDTH_MASK                   0x00000fe0
+#define THERM_CTRL1_WIDTH_GET(x)                 (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
+#define THERM_CTRL1_WIDTH_SET(x)                 (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
+#define THERM_CTRL1_TYPE_MSB                     4
+#define THERM_CTRL1_TYPE_LSB                     3
+#define THERM_CTRL1_TYPE_MASK                    0x00000018
+#define THERM_CTRL1_TYPE_GET(x)                  (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
+#define THERM_CTRL1_TYPE_SET(x)                  (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
+#define THERM_CTRL1_MEASURE_MSB                  2
+#define THERM_CTRL1_MEASURE_LSB                  2
+#define THERM_CTRL1_MEASURE_MASK                 0x00000004
+#define THERM_CTRL1_MEASURE_GET(x)               (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
+#define THERM_CTRL1_MEASURE_SET(x)               (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
+#define THERM_CTRL1_INT_EN_MSB                   1
+#define THERM_CTRL1_INT_EN_LSB                   1
+#define THERM_CTRL1_INT_EN_MASK                  0x00000002
+#define THERM_CTRL1_INT_EN_GET(x)                (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
+#define THERM_CTRL1_INT_EN_SET(x)                (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
+#define THERM_CTRL1_INT_STATUS_MSB               0
+#define THERM_CTRL1_INT_STATUS_LSB               0
+#define THERM_CTRL1_INT_STATUS_MASK              0x00000001
+#define THERM_CTRL1_INT_STATUS_GET(x)            (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
+#define THERM_CTRL1_INT_STATUS_SET(x)            (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
+
+#define THERM_CTRL2_ADDRESS                      0x000002e0
+#define THERM_CTRL2_OFFSET                       0x000002e0
+#define THERM_CTRL2_ADC_OFF_MSB                  25
+#define THERM_CTRL2_ADC_OFF_LSB                  25
+#define THERM_CTRL2_ADC_OFF_MASK                 0x02000000
+#define THERM_CTRL2_ADC_OFF_GET(x)               (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
+#define THERM_CTRL2_ADC_OFF_SET(x)               (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
+#define THERM_CTRL2_ADC_ON_MSB                   24
+#define THERM_CTRL2_ADC_ON_LSB                   24
+#define THERM_CTRL2_ADC_ON_MASK                  0x01000000
+#define THERM_CTRL2_ADC_ON_GET(x)                (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
+#define THERM_CTRL2_ADC_ON_SET(x)                (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
+#define THERM_CTRL2_SAMPLE_MSB                   23
+#define THERM_CTRL2_SAMPLE_LSB                   16
+#define THERM_CTRL2_SAMPLE_MASK                  0x00ff0000
+#define THERM_CTRL2_SAMPLE_GET(x)                (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
+#define THERM_CTRL2_SAMPLE_SET(x)                (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
+#define THERM_CTRL2_HIGH_MSB                     15
+#define THERM_CTRL2_HIGH_LSB                     8
+#define THERM_CTRL2_HIGH_MASK                    0x0000ff00
+#define THERM_CTRL2_HIGH_GET(x)                  (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
+#define THERM_CTRL2_HIGH_SET(x)                  (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
+#define THERM_CTRL2_LOW_MSB                      7
+#define THERM_CTRL2_LOW_LSB                      0
+#define THERM_CTRL2_LOW_MASK                     0x000000ff
+#define THERM_CTRL2_LOW_GET(x)                   (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
+#define THERM_CTRL2_LOW_SET(x)                   (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
+
+#define THERM_CTRL3_ADDRESS                      0x000002e4
+#define THERM_CTRL3_OFFSET                       0x000002e4
+#define THERM_CTRL3_ADC_GAIN_MSB                 16
+#define THERM_CTRL3_ADC_GAIN_LSB                 8
+#define THERM_CTRL3_ADC_GAIN_MASK                0x0001ff00
+#define THERM_CTRL3_ADC_GAIN_GET(x)              (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
+#define THERM_CTRL3_ADC_GAIN_SET(x)              (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
+#define THERM_CTRL3_ADC_OFFSET_MSB               7
+#define THERM_CTRL3_ADC_OFFSET_LSB               0
+#define THERM_CTRL3_ADC_OFFSET_MASK              0x000000ff
+#define THERM_CTRL3_ADC_OFFSET_GET(x)            (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
+#define THERM_CTRL3_ADC_OFFSET_SET(x)            (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_wlan_reg_reg_s {
+  volatile unsigned int wlan_reset_control;
+  volatile unsigned int wlan_xtal_control;
+  volatile unsigned int wlan_tcxo_detect;
+  volatile unsigned int wlan_xtal_test;
+  volatile unsigned int wlan_quadrature;
+  volatile unsigned int wlan_pll_control;
+  volatile unsigned int wlan_pll_settle;
+  volatile unsigned int wlan_xtal_settle;
+  volatile unsigned int wlan_cpu_clock;
+  volatile unsigned int wlan_clock_out;
+  volatile unsigned int wlan_clock_control;
+  volatile unsigned int wlan_bias_override;
+  volatile unsigned int wlan_wdt_control;
+  volatile unsigned int wlan_wdt_status;
+  volatile unsigned int wlan_wdt;
+  volatile unsigned int wlan_wdt_count;
+  volatile unsigned int wlan_wdt_reset;
+  volatile unsigned int wlan_int_status;
+  volatile unsigned int wlan_lf_timer0;
+  volatile unsigned int wlan_lf_timer_count0;
+  volatile unsigned int wlan_lf_timer_control0;
+  volatile unsigned int wlan_lf_timer_status0;
+  volatile unsigned int wlan_lf_timer1;
+  volatile unsigned int wlan_lf_timer_count1;
+  volatile unsigned int wlan_lf_timer_control1;
+  volatile unsigned int wlan_lf_timer_status1;
+  volatile unsigned int wlan_lf_timer2;
+  volatile unsigned int wlan_lf_timer_count2;
+  volatile unsigned int wlan_lf_timer_control2;
+  volatile unsigned int wlan_lf_timer_status2;
+  volatile unsigned int wlan_lf_timer3;
+  volatile unsigned int wlan_lf_timer_count3;
+  volatile unsigned int wlan_lf_timer_control3;
+  volatile unsigned int wlan_lf_timer_status3;
+  volatile unsigned int wlan_hf_timer;
+  volatile unsigned int wlan_hf_timer_count;
+  volatile unsigned int wlan_hf_lf_count;
+  volatile unsigned int wlan_hf_timer_control;
+  volatile unsigned int wlan_hf_timer_status;
+  volatile unsigned int wlan_rtc_control;
+  volatile unsigned int wlan_rtc_time;
+  volatile unsigned int wlan_rtc_date;
+  volatile unsigned int wlan_rtc_set_time;
+  volatile unsigned int wlan_rtc_set_date;
+  volatile unsigned int wlan_rtc_set_alarm;
+  volatile unsigned int wlan_rtc_config;
+  volatile unsigned int wlan_rtc_alarm_status;
+  volatile unsigned int wlan_uart_wakeup;
+  volatile unsigned int wlan_reset_cause;
+  volatile unsigned int wlan_system_sleep;
+  volatile unsigned int wlan_sdio_wrapper;
+  volatile unsigned int wlan_mac_sleep_control;
+  volatile unsigned int wlan_keep_awake;
+  volatile unsigned int wlan_lpo_cal_time;
+  volatile unsigned int wlan_lpo_init_dividend_int;
+  volatile unsigned int wlan_lpo_init_dividend_fraction;
+  volatile unsigned int wlan_lpo_cal;
+  volatile unsigned int wlan_lpo_cal_test_control;
+  volatile unsigned int wlan_lpo_cal_test_status;
+  volatile unsigned int wlan_chip_id;
+  volatile unsigned int wlan_derived_rtc_clk;
+  volatile unsigned int mac_pcu_slp32_mode;
+  volatile unsigned int mac_pcu_slp32_wake;
+  volatile unsigned int mac_pcu_slp32_inc;
+  volatile unsigned int mac_pcu_slp_mib1;
+  volatile unsigned int mac_pcu_slp_mib2;
+  volatile unsigned int mac_pcu_slp_mib3;
+  volatile unsigned int wlan_power_reg;
+  volatile unsigned int wlan_core_clk_ctrl;
+  volatile unsigned int wlan_gpio_wakeup_control;
+  volatile unsigned int ht;
+  volatile unsigned int mac_pcu_tsf_l32;
+  volatile unsigned int mac_pcu_tsf_u32;
+  volatile unsigned int mac_pcu_wbtimer;
+  unsigned char pad0[24]; /* pad to 0x140 */
+  volatile unsigned int mac_pcu_generic_timers[16];
+  volatile unsigned int mac_pcu_generic_timers_mode;
+  unsigned char pad1[60]; /* pad to 0x1c0 */
+  volatile unsigned int mac_pcu_generic_timers2[16];
+  volatile unsigned int mac_pcu_generic_timers_mode2;
+  volatile unsigned int mac_pcu_slp1;
+  volatile unsigned int mac_pcu_slp2;
+  volatile unsigned int mac_pcu_reset_tsf;
+  volatile unsigned int mac_pcu_tsf_add_pll;
+  volatile unsigned int sleep_retention;
+  volatile unsigned int btcoexctrl;
+  volatile unsigned int wbsync_priority1;
+  volatile unsigned int wbsync_priority2;
+  volatile unsigned int wbsync_priority3;
+  volatile unsigned int btcoex0;
+  volatile unsigned int btcoex1;
+  volatile unsigned int btcoex2;
+  volatile unsigned int btcoex3;
+  volatile unsigned int btcoex4;
+  volatile unsigned int btcoex5;
+  volatile unsigned int btcoex6;
+  volatile unsigned int lock;
+  volatile unsigned int nolock_priority;
+  volatile unsigned int wbsync;
+  volatile unsigned int wbsync1;
+  volatile unsigned int wbsync2;
+  volatile unsigned int wbsync3;
+  volatile unsigned int wb_timer_target;
+  volatile unsigned int wb_timer_slop;
+  volatile unsigned int btcoex_int_en;
+  volatile unsigned int btcoex_int_stat;
+  volatile unsigned int btpriority_int_en;
+  volatile unsigned int btpriority_int_stat;
+  volatile unsigned int btpriority_stomp_int_en;
+  volatile unsigned int btpriority_stomp_int_stat;
+  volatile unsigned int mac_pcu_bmiss_timeout;
+  volatile unsigned int mac_pcu_cab_awake;
+  volatile unsigned int lp_perf_counter;
+  volatile unsigned int lp_perf_light_sleep;
+  volatile unsigned int lp_perf_deep_sleep;
+  volatile unsigned int lp_perf_on;
+  volatile unsigned int st_64_bit;
+  volatile unsigned int message_wr;
+  volatile unsigned int message_wr_p;
+  volatile unsigned int message_rd;
+  volatile unsigned int message_rd_p;
+  volatile unsigned int chip_mode;
+  volatile unsigned int clk_req_fall_edge;
+  volatile unsigned int otp;
+  volatile unsigned int otp_status;
+  volatile unsigned int pmu;
+  unsigned char pad2[4]; /* pad to 0x2c0 */
+  volatile unsigned int pmu_config[2];
+  volatile unsigned int pmu_bypass;
+  volatile unsigned int mac_pcu_tsf2_l32;
+  volatile unsigned int mac_pcu_tsf2_u32;
+  volatile unsigned int mac_pcu_generic_timers_mode3;
+  volatile unsigned int mac_pcu_direct_connect;
+  volatile unsigned int therm_ctrl1;
+  volatile unsigned int therm_ctrl2;
+  volatile unsigned int therm_ctrl3;
+} rtc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS                        0x00000000
+#define SI_CONFIG_OFFSET                         0x00000000
+#define SI_CONFIG_ERR_INT_MSB                    19
+#define SI_CONFIG_ERR_INT_LSB                    19
+#define SI_CONFIG_ERR_INT_MASK                   0x00080000
+#define SI_CONFIG_ERR_INT_GET(x)                 (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x)                 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB              18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x)           (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x)           (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB                        16
+#define SI_CONFIG_I2C_LSB                        16
+#define SI_CONFIG_I2C_MASK                       0x00010000
+#define SI_CONFIG_I2C_GET(x)                     (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x)                     (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB                 7
+#define SI_CONFIG_POS_SAMPLE_LSB                 7
+#define SI_CONFIG_POS_SAMPLE_MASK                0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x)              (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x)              (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB                  6
+#define SI_CONFIG_POS_DRIVE_LSB                  6
+#define SI_CONFIG_POS_DRIVE_MASK                 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x)               (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x)               (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB              5
+#define SI_CONFIG_INACTIVE_DATA_LSB              5
+#define SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x)           (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x)           (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB               4
+#define SI_CONFIG_INACTIVE_CLK_LSB               4
+#define SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x)            (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x)            (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB                    3
+#define SI_CONFIG_DIVIDER_LSB                    0
+#define SI_CONFIG_DIVIDER_MASK                   0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x)                 (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x)                 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS                            0x00000004
+#define SI_CS_OFFSET                             0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB           13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB           11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK          0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x)        (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x)        (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB                       10
+#define SI_CS_DONE_ERR_LSB                       10
+#define SI_CS_DONE_ERR_MASK                      0x00000400
+#define SI_CS_DONE_ERR_GET(x)                    (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x)                    (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB                       9
+#define SI_CS_DONE_INT_LSB                       9
+#define SI_CS_DONE_INT_MASK                      0x00000200
+#define SI_CS_DONE_INT_GET(x)                    (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x)                    (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB                          8
+#define SI_CS_START_LSB                          8
+#define SI_CS_START_MASK                         0x00000100
+#define SI_CS_START_GET(x)                       (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x)                       (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB                         7
+#define SI_CS_RX_CNT_LSB                         4
+#define SI_CS_RX_CNT_MASK                        0x000000f0
+#define SI_CS_RX_CNT_GET(x)                      (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x)                      (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB                         3
+#define SI_CS_TX_CNT_LSB                         0
+#define SI_CS_TX_CNT_MASK                        0x0000000f
+#define SI_CS_TX_CNT_GET(x)                      (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x)                      (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS                      0x00000008
+#define SI_TX_DATA0_OFFSET                       0x00000008
+#define SI_TX_DATA0_DATA3_MSB                    31
+#define SI_TX_DATA0_DATA3_LSB                    24
+#define SI_TX_DATA0_DATA3_MASK                   0xff000000
+#define SI_TX_DATA0_DATA3_GET(x)                 (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x)                 (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB                    23
+#define SI_TX_DATA0_DATA2_LSB                    16
+#define SI_TX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x)                 (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x)                 (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB                    15
+#define SI_TX_DATA0_DATA1_LSB                    8
+#define SI_TX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x)                 (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x)                 (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB                    7
+#define SI_TX_DATA0_DATA0_LSB                    0
+#define SI_TX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x)                 (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x)                 (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS                      0x0000000c
+#define SI_TX_DATA1_OFFSET                       0x0000000c
+#define SI_TX_DATA1_DATA7_MSB                    31
+#define SI_TX_DATA1_DATA7_LSB                    24
+#define SI_TX_DATA1_DATA7_MASK                   0xff000000
+#define SI_TX_DATA1_DATA7_GET(x)                 (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x)                 (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB                    23
+#define SI_TX_DATA1_DATA6_LSB                    16
+#define SI_TX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x)                 (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x)                 (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB                    15
+#define SI_TX_DATA1_DATA5_LSB                    8
+#define SI_TX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x)                 (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x)                 (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB                    7
+#define SI_TX_DATA1_DATA4_LSB                    0
+#define SI_TX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x)                 (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x)                 (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS                      0x00000010
+#define SI_RX_DATA0_OFFSET                       0x00000010
+#define SI_RX_DATA0_DATA3_MSB                    31
+#define SI_RX_DATA0_DATA3_LSB                    24
+#define SI_RX_DATA0_DATA3_MASK                   0xff000000
+#define SI_RX_DATA0_DATA3_GET(x)                 (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x)                 (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB                    23
+#define SI_RX_DATA0_DATA2_LSB                    16
+#define SI_RX_DATA0_DATA2_MASK                   0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x)                 (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x)                 (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB                    15
+#define SI_RX_DATA0_DATA1_LSB                    8
+#define SI_RX_DATA0_DATA1_MASK                   0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x)                 (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x)                 (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB                    7
+#define SI_RX_DATA0_DATA0_LSB                    0
+#define SI_RX_DATA0_DATA0_MASK                   0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x)                 (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x)                 (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS                      0x00000014
+#define SI_RX_DATA1_OFFSET                       0x00000014
+#define SI_RX_DATA1_DATA7_MSB                    31
+#define SI_RX_DATA1_DATA7_LSB                    24
+#define SI_RX_DATA1_DATA7_MASK                   0xff000000
+#define SI_RX_DATA1_DATA7_GET(x)                 (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x)                 (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB                    23
+#define SI_RX_DATA1_DATA6_LSB                    16
+#define SI_RX_DATA1_DATA6_MASK                   0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x)                 (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x)                 (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB                    15
+#define SI_RX_DATA1_DATA5_LSB                    8
+#define SI_RX_DATA1_DATA5_MASK                   0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x)                 (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x)                 (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB                    7
+#define SI_RX_DATA1_DATA4_LSB                    0
+#define SI_RX_DATA1_DATA4_MASK                   0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x)                 (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x)                 (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+  volatile unsigned int si_config;
+  volatile unsigned int si_cs;
+  volatile unsigned int si_tx_data0;
+  volatile unsigned int si_tx_data1;
+  volatile unsigned int si_rx_data0;
+  volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h
new file mode 100644
index 000000000000..9e01b6a0875a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h
@@ -0,0 +1,256 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define UART_DATA_ADDRESS                        0x00000000
+#define UART_DATA_OFFSET                         0x00000000
+#define UART_DATA_TX_CSR_MSB                     9
+#define UART_DATA_TX_CSR_LSB                     9
+#define UART_DATA_TX_CSR_MASK                    0x00000200
+#define UART_DATA_TX_CSR_GET(x)                  (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
+#define UART_DATA_TX_CSR_SET(x)                  (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
+#define UART_DATA_RX_CSR_MSB                     8
+#define UART_DATA_RX_CSR_LSB                     8
+#define UART_DATA_RX_CSR_MASK                    0x00000100
+#define UART_DATA_RX_CSR_GET(x)                  (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
+#define UART_DATA_RX_CSR_SET(x)                  (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
+#define UART_DATA_TXRX_DATA_MSB                  7
+#define UART_DATA_TXRX_DATA_LSB                  0
+#define UART_DATA_TXRX_DATA_MASK                 0x000000ff
+#define UART_DATA_TXRX_DATA_GET(x)               (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
+#define UART_DATA_TXRX_DATA_SET(x)               (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
+
+#define UART_CONTROL_ADDRESS                     0x00000004
+#define UART_CONTROL_OFFSET                      0x00000004
+#define UART_CONTROL_RX_BUSY_MSB                 15
+#define UART_CONTROL_RX_BUSY_LSB                 15
+#define UART_CONTROL_RX_BUSY_MASK                0x00008000
+#define UART_CONTROL_RX_BUSY_GET(x)              (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
+#define UART_CONTROL_RX_BUSY_SET(x)              (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
+#define UART_CONTROL_TX_BUSY_MSB                 14
+#define UART_CONTROL_TX_BUSY_LSB                 14
+#define UART_CONTROL_TX_BUSY_MASK                0x00004000
+#define UART_CONTROL_TX_BUSY_GET(x)              (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
+#define UART_CONTROL_TX_BUSY_SET(x)              (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
+#define UART_CONTROL_HOST_INT_ENABLE_MSB         13
+#define UART_CONTROL_HOST_INT_ENABLE_LSB         13
+#define UART_CONTROL_HOST_INT_ENABLE_MASK        0x00002000
+#define UART_CONTROL_HOST_INT_ENABLE_GET(x)      (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
+#define UART_CONTROL_HOST_INT_ENABLE_SET(x)      (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
+#define UART_CONTROL_HOST_INT_MSB                12
+#define UART_CONTROL_HOST_INT_LSB                12
+#define UART_CONTROL_HOST_INT_MASK               0x00001000
+#define UART_CONTROL_HOST_INT_GET(x)             (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
+#define UART_CONTROL_HOST_INT_SET(x)             (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
+#define UART_CONTROL_TX_BREAK_MSB                11
+#define UART_CONTROL_TX_BREAK_LSB                11
+#define UART_CONTROL_TX_BREAK_MASK               0x00000800
+#define UART_CONTROL_TX_BREAK_GET(x)             (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
+#define UART_CONTROL_TX_BREAK_SET(x)             (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
+#define UART_CONTROL_RX_BREAK_MSB                10
+#define UART_CONTROL_RX_BREAK_LSB                10
+#define UART_CONTROL_RX_BREAK_MASK               0x00000400
+#define UART_CONTROL_RX_BREAK_GET(x)             (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
+#define UART_CONTROL_RX_BREAK_SET(x)             (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
+#define UART_CONTROL_SERIAL_TX_READY_MSB         9
+#define UART_CONTROL_SERIAL_TX_READY_LSB         9
+#define UART_CONTROL_SERIAL_TX_READY_MASK        0x00000200
+#define UART_CONTROL_SERIAL_TX_READY_GET(x)      (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
+#define UART_CONTROL_SERIAL_TX_READY_SET(x)      (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
+#define UART_CONTROL_TX_READY_ORIDE_MSB          8
+#define UART_CONTROL_TX_READY_ORIDE_LSB          8
+#define UART_CONTROL_TX_READY_ORIDE_MASK         0x00000100
+#define UART_CONTROL_TX_READY_ORIDE_GET(x)       (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
+#define UART_CONTROL_TX_READY_ORIDE_SET(x)       (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
+#define UART_CONTROL_RX_READY_ORIDE_MSB          7
+#define UART_CONTROL_RX_READY_ORIDE_LSB          7
+#define UART_CONTROL_RX_READY_ORIDE_MASK         0x00000080
+#define UART_CONTROL_RX_READY_ORIDE_GET(x)       (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
+#define UART_CONTROL_RX_READY_ORIDE_SET(x)       (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
+#define UART_CONTROL_DMA_ENABLE_MSB              6
+#define UART_CONTROL_DMA_ENABLE_LSB              6
+#define UART_CONTROL_DMA_ENABLE_MASK             0x00000040
+#define UART_CONTROL_DMA_ENABLE_GET(x)           (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
+#define UART_CONTROL_DMA_ENABLE_SET(x)           (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
+#define UART_CONTROL_FLOW_ENABLE_MSB             5
+#define UART_CONTROL_FLOW_ENABLE_LSB             5
+#define UART_CONTROL_FLOW_ENABLE_MASK            0x00000020
+#define UART_CONTROL_FLOW_ENABLE_GET(x)          (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
+#define UART_CONTROL_FLOW_ENABLE_SET(x)          (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
+#define UART_CONTROL_FLOW_INVERT_MSB             4
+#define UART_CONTROL_FLOW_INVERT_LSB             4
+#define UART_CONTROL_FLOW_INVERT_MASK            0x00000010
+#define UART_CONTROL_FLOW_INVERT_GET(x)          (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
+#define UART_CONTROL_FLOW_INVERT_SET(x)          (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
+#define UART_CONTROL_IFC_ENABLE_MSB              3
+#define UART_CONTROL_IFC_ENABLE_LSB              3
+#define UART_CONTROL_IFC_ENABLE_MASK             0x00000008
+#define UART_CONTROL_IFC_ENABLE_GET(x)           (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
+#define UART_CONTROL_IFC_ENABLE_SET(x)           (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
+#define UART_CONTROL_IFC_DCE_MSB                 2
+#define UART_CONTROL_IFC_DCE_LSB                 2
+#define UART_CONTROL_IFC_DCE_MASK                0x00000004
+#define UART_CONTROL_IFC_DCE_GET(x)              (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
+#define UART_CONTROL_IFC_DCE_SET(x)              (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
+#define UART_CONTROL_PARITY_ENABLE_MSB           1
+#define UART_CONTROL_PARITY_ENABLE_LSB           1
+#define UART_CONTROL_PARITY_ENABLE_MASK          0x00000002
+#define UART_CONTROL_PARITY_ENABLE_GET(x)        (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
+#define UART_CONTROL_PARITY_ENABLE_SET(x)        (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
+#define UART_CONTROL_PARITY_EVEN_MSB             0
+#define UART_CONTROL_PARITY_EVEN_LSB             0
+#define UART_CONTROL_PARITY_EVEN_MASK            0x00000001
+#define UART_CONTROL_PARITY_EVEN_GET(x)          (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
+#define UART_CONTROL_PARITY_EVEN_SET(x)          (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
+
+#define UART_CLKDIV_ADDRESS                      0x00000008
+#define UART_CLKDIV_OFFSET                       0x00000008
+#define UART_CLKDIV_CLK_SCALE_MSB                23
+#define UART_CLKDIV_CLK_SCALE_LSB                16
+#define UART_CLKDIV_CLK_SCALE_MASK               0x00ff0000
+#define UART_CLKDIV_CLK_SCALE_GET(x)             (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
+#define UART_CLKDIV_CLK_SCALE_SET(x)             (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
+#define UART_CLKDIV_CLK_STEP_MSB                 15
+#define UART_CLKDIV_CLK_STEP_LSB                 0
+#define UART_CLKDIV_CLK_STEP_MASK                0x0000ffff
+#define UART_CLKDIV_CLK_STEP_GET(x)              (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
+#define UART_CLKDIV_CLK_STEP_SET(x)              (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
+
+#define UART_INT_ADDRESS                         0x0000000c
+#define UART_INT_OFFSET                          0x0000000c
+#define UART_INT_TX_EMPTY_INT_MSB                9
+#define UART_INT_TX_EMPTY_INT_LSB                9
+#define UART_INT_TX_EMPTY_INT_MASK               0x00000200
+#define UART_INT_TX_EMPTY_INT_GET(x)             (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
+#define UART_INT_TX_EMPTY_INT_SET(x)             (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
+#define UART_INT_RX_FULL_INT_MSB                 8
+#define UART_INT_RX_FULL_INT_LSB                 8
+#define UART_INT_RX_FULL_INT_MASK                0x00000100
+#define UART_INT_RX_FULL_INT_GET(x)              (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
+#define UART_INT_RX_FULL_INT_SET(x)              (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
+#define UART_INT_RX_BREAK_OFF_INT_MSB            7
+#define UART_INT_RX_BREAK_OFF_INT_LSB            7
+#define UART_INT_RX_BREAK_OFF_INT_MASK           0x00000080
+#define UART_INT_RX_BREAK_OFF_INT_GET(x)         (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
+#define UART_INT_RX_BREAK_OFF_INT_SET(x)         (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
+#define UART_INT_RX_BREAK_ON_INT_MSB             6
+#define UART_INT_RX_BREAK_ON_INT_LSB             6
+#define UART_INT_RX_BREAK_ON_INT_MASK            0x00000040
+#define UART_INT_RX_BREAK_ON_INT_GET(x)          (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
+#define UART_INT_RX_BREAK_ON_INT_SET(x)          (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
+#define UART_INT_RX_PARITY_ERR_INT_MSB           5
+#define UART_INT_RX_PARITY_ERR_INT_LSB           5
+#define UART_INT_RX_PARITY_ERR_INT_MASK          0x00000020
+#define UART_INT_RX_PARITY_ERR_INT_GET(x)        (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
+#define UART_INT_RX_PARITY_ERR_INT_SET(x)        (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
+#define UART_INT_TX_OFLOW_ERR_INT_MSB            4
+#define UART_INT_TX_OFLOW_ERR_INT_LSB            4
+#define UART_INT_TX_OFLOW_ERR_INT_MASK           0x00000010
+#define UART_INT_TX_OFLOW_ERR_INT_GET(x)         (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
+#define UART_INT_TX_OFLOW_ERR_INT_SET(x)         (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_OFLOW_ERR_INT_MSB            3
+#define UART_INT_RX_OFLOW_ERR_INT_LSB            3
+#define UART_INT_RX_OFLOW_ERR_INT_MASK           0x00000008
+#define UART_INT_RX_OFLOW_ERR_INT_GET(x)         (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
+#define UART_INT_RX_OFLOW_ERR_INT_SET(x)         (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_FRAMING_ERR_INT_MSB          2
+#define UART_INT_RX_FRAMING_ERR_INT_LSB          2
+#define UART_INT_RX_FRAMING_ERR_INT_MASK         0x00000004
+#define UART_INT_RX_FRAMING_ERR_INT_GET(x)       (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
+#define UART_INT_RX_FRAMING_ERR_INT_SET(x)       (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
+#define UART_INT_TX_READY_INT_MSB                1
+#define UART_INT_TX_READY_INT_LSB                1
+#define UART_INT_TX_READY_INT_MASK               0x00000002
+#define UART_INT_TX_READY_INT_GET(x)             (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
+#define UART_INT_TX_READY_INT_SET(x)             (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
+#define UART_INT_RX_VALID_INT_MSB                0
+#define UART_INT_RX_VALID_INT_LSB                0
+#define UART_INT_RX_VALID_INT_MASK               0x00000001
+#define UART_INT_RX_VALID_INT_GET(x)             (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
+#define UART_INT_RX_VALID_INT_SET(x)             (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
+
+#define UART_INT_EN_ADDRESS                      0x00000010
+#define UART_INT_EN_OFFSET                       0x00000010
+#define UART_INT_EN_TX_EMPTY_INT_EN_MSB          9
+#define UART_INT_EN_TX_EMPTY_INT_EN_LSB          9
+#define UART_INT_EN_TX_EMPTY_INT_EN_MASK         0x00000200
+#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x)       (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
+#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x)       (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
+#define UART_INT_EN_RX_FULL_INT_EN_MSB           8
+#define UART_INT_EN_RX_FULL_INT_EN_LSB           8
+#define UART_INT_EN_RX_FULL_INT_EN_MASK          0x00000100
+#define UART_INT_EN_RX_FULL_INT_EN_GET(x)        (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
+#define UART_INT_EN_RX_FULL_INT_EN_SET(x)        (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB      7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB      7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK     0x00000080
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x)   (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x)   (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB       6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB       6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK      0x00000040
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x)    (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x)    (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB     5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB     5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK    0x00000020
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x)  (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x)  (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB      4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB      4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK     0x00000010
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x)   (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x)   (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB      3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB      3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK     0x00000008
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x)   (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x)   (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB    2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB    2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK   0x00000004
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_READY_INT_EN_MSB          1
+#define UART_INT_EN_TX_READY_INT_EN_LSB          1
+#define UART_INT_EN_TX_READY_INT_EN_MASK         0x00000002
+#define UART_INT_EN_TX_READY_INT_EN_GET(x)       (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
+#define UART_INT_EN_TX_READY_INT_EN_SET(x)       (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
+#define UART_INT_EN_RX_VALID_INT_EN_MSB          0
+#define UART_INT_EN_RX_VALID_INT_EN_LSB          0
+#define UART_INT_EN_RX_VALID_INT_EN_MASK         0x00000001
+#define UART_INT_EN_RX_VALID_INT_EN_GET(x)       (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
+#define UART_INT_EN_RX_VALID_INT_EN_SET(x)       (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+  volatile unsigned int uart_data;
+  volatile unsigned int uart_control;
+  volatile unsigned int uart_clkdiv;
+  volatile unsigned int uart_int;
+  volatile unsigned int uart_int_en;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h
new file mode 100644
index 000000000000..d8a07b30043b
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "umbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h
new file mode 100644
index 000000000000..9b63f5f40757
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h
@@ -0,0 +1,318 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UMBOX_WLAN_REG_REG_H_
+#define _UMBOX_WLAN_REG_REG_H_
+
+#define UMBOX_FIFO_ADDRESS                       0x00000000
+#define UMBOX_FIFO_OFFSET                        0x00000000
+#define UMBOX_FIFO_DATA_MSB                      8
+#define UMBOX_FIFO_DATA_LSB                      0
+#define UMBOX_FIFO_DATA_MASK                     0x000001ff
+#define UMBOX_FIFO_DATA_GET(x)                   (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
+#define UMBOX_FIFO_DATA_SET(x)                   (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
+
+#define UMBOX_FIFO_STATUS_ADDRESS                0x00000008
+#define UMBOX_FIFO_STATUS_OFFSET                 0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB           3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB           3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK          0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x)        (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x)        (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_TX_FULL_MSB            2
+#define UMBOX_FIFO_STATUS_TX_FULL_LSB            2
+#define UMBOX_FIFO_STATUS_TX_FULL_MASK           0x00000004
+#define UMBOX_FIFO_STATUS_TX_FULL_GET(x)         (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_TX_FULL_SET(x)         (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB           1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB           1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK          0x00000002
+#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x)        (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x)        (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_RX_FULL_MSB            0
+#define UMBOX_FIFO_STATUS_RX_FULL_LSB            0
+#define UMBOX_FIFO_STATUS_RX_FULL_MASK           0x00000001
+#define UMBOX_FIFO_STATUS_RX_FULL_GET(x)         (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_RX_FULL_SET(x)         (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
+
+#define UMBOX_DMA_POLICY_ADDRESS                 0x0000000c
+#define UMBOX_DMA_POLICY_OFFSET                  0x0000000c
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB          3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB          3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK         0x00000008
+#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x)       (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x)       (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_TX_ORDER_MSB            2
+#define UMBOX_DMA_POLICY_TX_ORDER_LSB            2
+#define UMBOX_DMA_POLICY_TX_ORDER_MASK           0x00000004
+#define UMBOX_DMA_POLICY_TX_ORDER_GET(x)         (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_TX_ORDER_SET(x)         (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB          1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB          1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK         0x00000002
+#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x)       (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x)       (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_RX_ORDER_MSB            0
+#define UMBOX_DMA_POLICY_RX_ORDER_LSB            0
+#define UMBOX_DMA_POLICY_RX_ORDER_MASK           0x00000001
+#define UMBOX_DMA_POLICY_RX_ORDER_GET(x)         (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_RX_ORDER_SET(x)         (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS    0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET     0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_RX_CONTROL_ADDRESS            0x00000014
+#define UMBOX0_DMA_RX_CONTROL_OFFSET             0x00000014
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB         2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB         2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK        0x00000004
+#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x)      (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x)      (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_RX_CONTROL_START_MSB          1
+#define UMBOX0_DMA_RX_CONTROL_START_LSB          1
+#define UMBOX0_DMA_RX_CONTROL_START_MASK         0x00000002
+#define UMBOX0_DMA_RX_CONTROL_START_GET(x)       (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
+#define UMBOX0_DMA_RX_CONTROL_START_SET(x)       (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
+#define UMBOX0_DMA_RX_CONTROL_STOP_MSB           0
+#define UMBOX0_DMA_RX_CONTROL_STOP_LSB           0
+#define UMBOX0_DMA_RX_CONTROL_STOP_MASK          0x00000001
+#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x)        (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x)        (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS    0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET     0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_TX_CONTROL_ADDRESS            0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_OFFSET             0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB         2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB         2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK        0x00000004
+#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x)      (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x)      (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_TX_CONTROL_START_MSB          1
+#define UMBOX0_DMA_TX_CONTROL_START_LSB          1
+#define UMBOX0_DMA_TX_CONTROL_START_MASK         0x00000002
+#define UMBOX0_DMA_TX_CONTROL_START_GET(x)       (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
+#define UMBOX0_DMA_TX_CONTROL_START_SET(x)       (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
+#define UMBOX0_DMA_TX_CONTROL_STOP_MSB           0
+#define UMBOX0_DMA_TX_CONTROL_STOP_LSB           0
+#define UMBOX0_DMA_TX_CONTROL_STOP_MASK          0x00000001
+#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x)        (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x)        (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define UMBOX_FIFO_TIMEOUT_ADDRESS               0x00000020
+#define UMBOX_FIFO_TIMEOUT_OFFSET                0x00000020
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB        8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB        8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK       0x00000100
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x)     (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x)     (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
+#define UMBOX_FIFO_TIMEOUT_VALUE_MSB             7
+#define UMBOX_FIFO_TIMEOUT_VALUE_LSB             0
+#define UMBOX_FIFO_TIMEOUT_VALUE_MASK            0x000000ff
+#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x)          (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
+#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x)          (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
+
+#define UMBOX_INT_STATUS_ADDRESS                 0x00000024
+#define UMBOX_INT_STATUS_OFFSET                  0x00000024
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB     7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB     7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK    0x00000080
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB     5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB     5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK    0x00000020
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB      4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB      4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK     0x00000010
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x)   (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x)   (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB         3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB         3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK        0x00000008
+#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB        2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB        2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK       0x00000004
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB        1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB        1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK       0x00000002
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)     (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)     (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB         0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB         0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK        0x00000001
+#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x)      (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x)      (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define UMBOX_INT_ENABLE_ADDRESS                 0x00000028
+#define UMBOX_INT_ENABLE_OFFSET                  0x00000028
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB     7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB     7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK    0x00000080
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB     5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB     5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK    0x00000020
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)  (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)  (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB      4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB      4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK     0x00000010
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x)   (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x)   (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB         3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB         3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK        0x00000008
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)      (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)      (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB        2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB        2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK       0x00000004
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)     (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)     (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB        1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB        1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK       0x00000002
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)     (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)     (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB         0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB         0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK        0x00000001
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)      (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)      (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define UMBOX_DEBUG_ADDRESS                      0x0000002c
+#define UMBOX_DEBUG_OFFSET                       0x0000002c
+#define UMBOX_DEBUG_SEL_MSB                      2
+#define UMBOX_DEBUG_SEL_LSB                      0
+#define UMBOX_DEBUG_SEL_MASK                     0x00000007
+#define UMBOX_DEBUG_SEL_GET(x)                   (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
+#define UMBOX_DEBUG_SEL_SET(x)                   (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
+
+#define UMBOX_FIFO_RESET_ADDRESS                 0x00000030
+#define UMBOX_FIFO_RESET_OFFSET                  0x00000030
+#define UMBOX_FIFO_RESET_INIT_MSB                0
+#define UMBOX_FIFO_RESET_INIT_LSB                0
+#define UMBOX_FIFO_RESET_INIT_MASK               0x00000001
+#define UMBOX_FIFO_RESET_INIT_GET(x)             (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
+#define UMBOX_FIFO_RESET_INIT_SET(x)             (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
+
+#define UMBOX_HCI_FRAMER_ADDRESS                 0x00000034
+#define UMBOX_HCI_FRAMER_OFFSET                  0x00000034
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB        6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB        6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK       0x00000040
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x)     (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x)     (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
+#define UMBOX_HCI_FRAMER_ENABLE_MSB              5
+#define UMBOX_HCI_FRAMER_ENABLE_LSB              5
+#define UMBOX_HCI_FRAMER_ENABLE_MASK             0x00000020
+#define UMBOX_HCI_FRAMER_ENABLE_GET(x)           (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
+#define UMBOX_HCI_FRAMER_ENABLE_SET(x)           (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB          4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB          4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK         0x00000010
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x)       (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x)       (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB           3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB           3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK          0x00000008
+#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x)        (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x)        (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_OVERFLOW_MSB            2
+#define UMBOX_HCI_FRAMER_OVERFLOW_LSB            2
+#define UMBOX_HCI_FRAMER_OVERFLOW_MASK           0x00000004
+#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x)         (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x)         (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB         1
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB         0
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK        0x00000003
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x)      (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x)      (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct umbox_wlan_reg_reg_s {
+  volatile unsigned int umbox_fifo[2];
+  volatile unsigned int umbox_fifo_status;
+  volatile unsigned int umbox_dma_policy;
+  volatile unsigned int umbox0_dma_rx_descriptor_base;
+  volatile unsigned int umbox0_dma_rx_control;
+  volatile unsigned int umbox0_dma_tx_descriptor_base;
+  volatile unsigned int umbox0_dma_tx_control;
+  volatile unsigned int umbox_fifo_timeout;
+  volatile unsigned int umbox_int_status;
+  volatile unsigned int umbox_int_enable;
+  volatile unsigned int umbox_debug;
+  volatile unsigned int umbox_fifo_reset;
+  volatile unsigned int umbox_hci_framer;
+} umbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UMBOX_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h
new file mode 100644
index 000000000000..2d7b6aa06911
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h
@@ -0,0 +1,163 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "vmc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
+#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
+#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
+#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
+#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
+#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
+#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
+#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
+#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
+#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
+#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
+#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
+#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
+#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
+#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
+#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
+#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
+#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
+#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
+#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
+#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
+#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
+#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
+#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
+#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
+#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
+#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
+#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
+#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
+#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
+#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
+#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
+#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
+#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
+#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
+#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
+#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
+#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
+#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
+#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
+#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
+#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
+#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
+#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
+#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
+#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
+#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
+#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
+#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
+#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
+#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
+#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
+#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
+#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
+#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
+#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
+#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
+#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
+#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
+#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
+#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
+#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
+#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
+#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
+#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
+#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
+#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
+#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
+#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
+#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
+#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
+#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
+#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
+#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
+#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
+#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
+#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
+#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
+#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
+#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
+#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
+#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
+#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
+#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
+#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h
new file mode 100644
index 000000000000..ff6d14545cd0
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h
@@ -0,0 +1,191 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_WLAN_REG_REG_H_
+#define _VMC_WLAN_REG_REG_H_
+
+#define WLAN_MC_BCAM_VALID_ADDRESS               0x00000000
+#define WLAN_MC_BCAM_VALID_OFFSET                0x00000000
+#define WLAN_MC_BCAM_VALID_BIT_MSB               0
+#define WLAN_MC_BCAM_VALID_BIT_LSB               0
+#define WLAN_MC_BCAM_VALID_BIT_MASK              0x00000001
+#define WLAN_MC_BCAM_VALID_BIT_GET(x)            (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
+#define WLAN_MC_BCAM_VALID_BIT_SET(x)            (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
+
+#define WLAN_MC_BCAM_COMPARE_ADDRESS             0x00000200
+#define WLAN_MC_BCAM_COMPARE_OFFSET              0x00000200
+#define WLAN_MC_BCAM_COMPARE_KEY_MSB             19
+#define WLAN_MC_BCAM_COMPARE_KEY_LSB             2
+#define WLAN_MC_BCAM_COMPARE_KEY_MASK            0x000ffffc
+#define WLAN_MC_BCAM_COMPARE_KEY_GET(x)          (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
+#define WLAN_MC_BCAM_COMPARE_KEY_SET(x)          (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
+
+#define WLAN_MC_BCAM_TARGET_ADDRESS              0x00000400
+#define WLAN_MC_BCAM_TARGET_OFFSET               0x00000400
+#define WLAN_MC_BCAM_TARGET_INST_MSB             31
+#define WLAN_MC_BCAM_TARGET_INST_LSB             0
+#define WLAN_MC_BCAM_TARGET_INST_MASK            0xffffffff
+#define WLAN_MC_BCAM_TARGET_INST_GET(x)          (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
+#define WLAN_MC_BCAM_TARGET_INST_SET(x)          (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
+
+#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS      0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET       0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB   0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB   0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK  0x00000001
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS       0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET        0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB     25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB     25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK    0x02000000
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)  (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)  (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB   24
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB   0
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK  0x01ffffff
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS      0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET       0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB   0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB   0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK  0x00000001
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS       0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET        0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB       31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB       31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK      0x80000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)    (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)    (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB      30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB      30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK     0x40000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)   (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)   (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB   23
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB   0
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK  0x00ffffff
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS         0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_OFFSET          0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB  1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB  1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB  0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB  0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
+
+#define WLAN_CPU_PERF_CNT_ADDRESS                0x00000614
+#define WLAN_CPU_PERF_CNT_OFFSET                 0x00000614
+#define WLAN_CPU_PERF_CNT_EN_MSB                 0
+#define WLAN_CPU_PERF_CNT_EN_LSB                 0
+#define WLAN_CPU_PERF_CNT_EN_MASK                0x00000001
+#define WLAN_CPU_PERF_CNT_EN_GET(x)              (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
+#define WLAN_CPU_PERF_CNT_EN_SET(x)              (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
+
+#define WLAN_CPU_INST_FETCH_ADDRESS              0x00000618
+#define WLAN_CPU_INST_FETCH_OFFSET               0x00000618
+#define WLAN_CPU_INST_FETCH_CNT_MSB              31
+#define WLAN_CPU_INST_FETCH_CNT_LSB              0
+#define WLAN_CPU_INST_FETCH_CNT_MASK             0xffffffff
+#define WLAN_CPU_INST_FETCH_CNT_GET(x)           (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
+#define WLAN_CPU_INST_FETCH_CNT_SET(x)           (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
+
+#define WLAN_CPU_DATA_FETCH_ADDRESS              0x0000061c
+#define WLAN_CPU_DATA_FETCH_OFFSET               0x0000061c
+#define WLAN_CPU_DATA_FETCH_CNT_MSB              31
+#define WLAN_CPU_DATA_FETCH_CNT_LSB              0
+#define WLAN_CPU_DATA_FETCH_CNT_MASK             0xffffffff
+#define WLAN_CPU_DATA_FETCH_CNT_GET(x)           (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
+#define WLAN_CPU_DATA_FETCH_CNT_SET(x)           (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
+
+#define WLAN_CPU_RAM1_CONFLICT_ADDRESS           0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_OFFSET            0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM2_CONFLICT_ADDRESS           0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_OFFSET            0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM3_CONFLICT_ADDRESS           0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_OFFSET            0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM4_CONFLICT_ADDRESS           0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_OFFSET            0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB           11
+#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB           0
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK          0x00000fff
+#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)        (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)        (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_wlan_reg_reg_s {
+  volatile unsigned int wlan_mc_bcam_valid[128];
+  volatile unsigned int wlan_mc_bcam_compare[128];
+  volatile unsigned int wlan_mc_bcam_target[128];
+  volatile unsigned int wlan_apb_addr_error_control;
+  volatile unsigned int wlan_apb_addr_error_status;
+  volatile unsigned int wlan_ahb_addr_error_control;
+  volatile unsigned int wlan_ahb_addr_error_status;
+  volatile unsigned int wlan_bcam_conflict_error;
+  volatile unsigned int wlan_cpu_perf_cnt;
+  volatile unsigned int wlan_cpu_inst_fetch;
+  volatile unsigned int wlan_cpu_data_fetch;
+  volatile unsigned int wlan_cpu_ram1_conflict;
+  volatile unsigned int wlan_cpu_ram2_conflict;
+  volatile unsigned int wlan_cpu_ram3_conflict;
+  volatile unsigned int wlan_cpu_ram4_conflict;
+} vmc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_config.h b/drivers/net/wireless/ath6kl/include/a_config.h
new file mode 100644
index 000000000000..8f9ccf7d1a29
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_config.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_config.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains software configuration options that enables
+// specific software "features"
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_CONFIG_H_
+#define _A_CONFIG_H_
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/config.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/config.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/config_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/config_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/win/config_win.h"
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_debug.h b/drivers/net/wireless/ath6kl/include/a_debug.h
new file mode 100644
index 000000000000..f8f7a2cdf5d3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_debug.h
@@ -0,0 +1,215 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_debug.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DEBUG_H_
+#define _A_DEBUG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <a_types.h>
+#include <a_osapi.h>
+
+    /* standard debug print masks bits 0..7 */
+#define ATH_DEBUG_ERR   (1 << 0)   /* errors */
+#define ATH_DEBUG_WARN  (1 << 1)   /* warnings */
+#define ATH_DEBUG_INFO  (1 << 2)   /* informational (module startup info) */
+#define ATH_DEBUG_TRC   (1 << 3)   /* generic function call tracing */
+#define ATH_DEBUG_RSVD1 (1 << 4)
+#define ATH_DEBUG_RSVD2 (1 << 5)
+#define ATH_DEBUG_RSVD3 (1 << 6)
+#define ATH_DEBUG_RSVD4 (1 << 7)
+
+#define ATH_DEBUG_MASK_DEFAULTS  (ATH_DEBUG_ERR | ATH_DEBUG_WARN)
+#define ATH_DEBUG_ANY  0xFFFF
+
+    /* other aliases used throughout */
+#define ATH_DEBUG_ERROR   ATH_DEBUG_ERR
+#define ATH_LOG_ERR       ATH_DEBUG_ERR
+#define ATH_LOG_INF       ATH_DEBUG_INFO
+#define ATH_LOG_TRC       ATH_DEBUG_TRC
+#define ATH_DEBUG_TRACE   ATH_DEBUG_TRC
+#define ATH_DEBUG_INIT    ATH_DEBUG_INFO
+
+    /* bits 8..31 are module-specific masks */
+#define ATH_DEBUG_MODULE_MASK_SHIFT   8
+
+    /* macro to make a module-specific masks */
+#define ATH_DEBUG_MAKE_MODULE_MASK(index)  (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+/* Debug support on a per-module basis
+ *
+ * Usage:
+ *
+ *   Each module can utilize it's own debug mask variable.  A set of commonly used
+ *   masks are provided (ERRORS, WARNINGS, TRACE etc..).  It is up to each module
+ *   to define module-specific masks using the macros above.
+ *
+ *   Each module defines a single debug mask variable debug_XXX where the "name" of the module is
+ *   common to all C-files within that module.  This requires every C-file that includes a_debug.h
+ *   to define the module name in that file.
+ *
+ *   Example:
+ *
+ *   #define ATH_MODULE_NAME htc
+ *   #include "a_debug.h"
+ *
+ *   This will define a debug mask structure called debug_htc and all debug macros will reference this
+ *   variable.
+ *
+ *   A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro:
+ *
+ *      #define ATH_DEBUG_MY_MASK1  ATH_DEBUG_MAKE_MODULE_MASK(0)
+ *      #define ATH_DEBUG_MY_MASK2  ATH_DEBUG_MAKE_MODULE_MASK(1)
+ *
+ *   The instantiation of the debug structure should be made by the module.  When a module is
+ *   instantiated, the module can set a description string, a default mask and an array of description
+ *   entries containing information on each module-defined debug mask.
+ *   NOTE: The instantiation is statically allocated, only one instance can exist per module.
+ *
+ *   Example:
+ *
+ *
+ *   #define ATH_DEBUG_BMI  ATH_DEBUG_MAKE_MODULE_MASK(0)
+ *
+ *   #ifdef DEBUG
+ *   static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+ *       { ATH_DEBUG_BMI , "BMI Tracing"},   <== description of the module specific mask
+ *   };
+ *
+ *   ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+ *                                    "bmi"  <== module name
+ *                                    "Boot Manager Interface",  <== description of module
+ *                                    ATH_DEBUG_MASK_DEFAULTS,          <== defaults
+ *                                    ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+ *                                    bmi_debug_desc);
+ *
+ *   #endif
+ *
+ *  A module can optionally register it's debug module information in order for other tools to change the
+ *  bit mask at runtime.  A module can call  A_REGISTER_MODULE_DEBUG_INFO() in it's module
+ *  init code.  This macro can be called multiple times without consequence.  The debug info maintains
+ *  state to indicate whether the information was previously registered.
+ *
+ * */
+
+#define ATH_DEBUG_MAX_MASK_DESC_LENGTH   32
+#define ATH_DEBUG_MAX_MOD_DESC_LENGTH    64
+
+typedef struct {
+    A_UINT32 Mask;
+    A_CHAR   Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
+} ATH_DEBUG_MASK_DESCRIPTION;
+
+#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0)
+
+typedef struct  _ATH_DEBUG_MODULE_DBG_INFO{
+    struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
+    A_CHAR                      ModuleName[16];
+    A_CHAR                      ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
+    A_UINT32                    Flags;
+    A_UINT32                    CurrentMask;
+    int                         MaxDescriptions;
+    ATH_DEBUG_MASK_DESCRIPTION  *pMaskDescriptions; /* pointer to array of descriptions */
+} ATH_DEBUG_MODULE_DBG_INFO;
+
+#define ATH_DEBUG_DESCRIPTION_COUNT(d)  (int)((sizeof((d))) / (sizeof(ATH_DEBUG_MASK_DESCRIPTION)))
+
+#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s)
+#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask
+#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s
+
+#ifdef DEBUG
+
+    /* for source files that will instantiate the debug variables */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \
+ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \
+            {NULL,(name),(moddesc),0,(initmask),count,(descriptions)}
+
+#ifdef ATH_MODULE_NAME
+extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME);
+#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl))
+#endif /* ATH_MODULE_NAME */
+
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl)
+
+#define ATH_DEBUG_DECLARE_EXTERN(s) \
+    extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s)
+
+#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc)
+
+
+#define AR_DEBUG_ASSERT A_ASSERT
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+
+#else /* !DEBUG */
+    /* NON DEBUG */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions)
+#define AR_DEBUG_LVL_CHECK(lvl) 0
+#define AR_DEBUG_PRINTBUF(buffer, length, desc)
+#define AR_DEBUG_ASSERT(test)
+#define ATH_DEBUG_DECLARE_EXTERN(s)
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl)
+#define A_DUMP_MODULE_DEBUG_INFO(s)
+#define A_REGISTER_MODULE_DEBUG_INFO(s)
+
+#endif
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask);
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask);
+void a_dump_module_debug_info_by_name(A_CHAR *module_name);
+void a_module_debug_support_init(void);
+void a_module_debug_support_cleanup(void);
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/debug.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/debug.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/debug_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/debug_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/debug_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <debug_win.h>
+#endif 
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_drv.h b/drivers/net/wireless/ath6kl/include/a_drv.h
new file mode 100644
index 000000000000..f7a6afe91993
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_drv.h
@@ -0,0 +1,46 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_H_
+#define _A_DRV_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athdrv_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athdrv_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#endif /* _ADRV_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_drv_api.h b/drivers/net/wireless/ath6kl/include/a_drv_api.h
new file mode 100644
index 000000000000..b3dd4f5635b4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_drv_api.h
@@ -0,0 +1,228 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_API_H_
+#define _A_DRV_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/****************************************************************************/
+/**                                                                        **/
+/** WMI related hooks                                                      **/
+/**                                                                        **/
+/****************************************************************************/
+/****************************************************************************/
+
+#include <ar6000_api.h>
+
+#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList)   \
+    ar6000_channelList_rx((devt), (numChan), (chanList))
+
+#define A_WMI_SET_NUMDATAENDPTS(devt, num)  \
+    ar6000_set_numdataendpts((devt), (num))
+
+#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
+    ar6000_control_tx((devt), (osbuf), (streamID))
+
+#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len)  \
+    ar6000_targetStats_event((devt), (pStats), (len))
+
+#define A_WMI_SCANCOMPLETE_EVENT(devt, status)  \
+    ar6000_scanComplete_event((devt), (status))
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+
+#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg)   \
+    ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_DSET_CLOSE(devt, access_cookie)   \
+    ar6000_dset_close((devt), (access_cookie))
+
+#endif
+
+#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
+    ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
+    ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
+
+#define A_WMI_PSPOLL_EVENT(devt, aid)\
+    ar6000_pspoll_event((devt),(aid))
+
+#define A_WMI_DTIMEXPIRY_EVENT(devt)\
+    ar6000_dtimexpiry_event((devt))
+
+#ifdef WAPI_ENABLE
+#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\
+    ap_wapi_rekey_event((devt),(type),(mac))
+#endif
+
+#define A_WMI_REGDOMAIN_EVENT(devt, regCode)    \
+    ar6000_regDomain_event((devt), (regCode))
+
+#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info)  \
+    ar6000_neighborReport_event((devt), (numAps), (info))
+
+#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus)  \
+    ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
+
+#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast)   \
+    ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
+
+#define A_WMI_BITRATE_RX(devt, rateKbps)    \
+    ar6000_bitrate_rx((devt), (rateKbps))
+
+#define A_WMI_TXPWR_RX(devt, txPwr) \
+    ar6000_txPwr_rx((devt), (txPwr))
+
+#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \
+    ar6000_ready_event((devt), (datap), (phyCap), (ver))
+
+#define A_WMI_DBGLOG_INIT_DONE(ar) \
+    ar6000_dbglog_init_done(ar);
+
+#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi)    \
+    ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
+
+#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal)    \
+    ar6000_reportError_event((devt), (errorVal))
+
+#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
+    ar6000_roam_tbl_event((devt), (pTbl))
+
+#define A_WMI_ROAM_DATA_EVENT(devt, p) \
+    ar6000_roam_data_event((devt), (p))
+
+#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters)    \
+    ar6000_wow_list_event((devt), (num_filters), (wow_filters))
+
+#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion)  \
+    ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
+
+#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel)  \
+    ar6000_channel_change_event((devt), (oldChannel), (newChannel))
+
+#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \
+    ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list))
+
+#define A_WMI_PEER_EVENT(devt, eventCode, bssid)    \
+    ar6000_peer_event ((devt), (eventCode), (bssid))
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+
+#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
+    ar6000_gpio_intr_rx((intr_mask), (input_values))
+
+#define A_WMI_GPIO_DATA_RX(reg_id, value) \
+    ar6000_gpio_data_rx((reg_id), (value))
+
+#define A_WMI_GPIO_ACK_RX() \
+    ar6000_gpio_ack_rx()
+
+#endif
+
+#ifdef SEND_EVENT_TO_APP
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
+    ar6000_send_event_to_app((ar), (eventId), (datap), (len))
+
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
+    ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
+
+#else
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
+
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
+    ar6000_tcmd_rx_report_event((devt), (results), (len))
+#endif
+
+#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source)    \
+    ar6000_hbChallengeResp_event((devt), (cookie), (source))
+
+#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
+    ar6000_tx_retry_err_event((devt))
+
+#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
+    ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
+
+#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
+    ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
+
+#define A_WMI_RATEMASK_RX(devt, ratemask) \
+    ar6000_ratemask_rx((devt), (ratemask))
+
+#define A_WMI_KEEPALIVE_RX(devt, configured)    \
+    ar6000_keepalive_rx((devt), (configured))
+
+#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len)   \
+    ar6000_bssInfo_event_rx((ar), (datap), (len))
+
+#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
+    ar6000_dbglog_event((ar), (dropped), (buffer), (length));
+
+#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
+    ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
+
+#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
+    ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
+#define A_WMI_Ac2EndpointID(devht, ac)\
+    ar6000_ac2_endpoint_id((devht), (ac))
+
+#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\
+    ar6000_aggr_rcv_addba_req_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\
+    ar6000_aggr_rcv_addba_resp_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\
+    ar6000_aggr_rcv_delba_req_evt((devt), (cmd))
+#define A_WMI_HCI_EVENT_EVT(devt, cmd)\
+    ar6000_hci_event_rcv_evt((devt), (cmd))
+
+#define A_WMI_Endpoint2Ac(devt, ep) \
+    ar6000_endpoint_id2_ac((devt), (ep))
+
+#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\
+	ar6000_btcoex_config_event((devt), (evt), (len))
+
+#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\
+	ar6000_btcoex_stats_event((devt), (datap), (len))
+
+/****************************************************************************/
+/****************************************************************************/
+/**                                                                        **/
+/** HTC related hooks                                                      **/
+/**                                                                        **/
+/****************************************************************************/
+/****************************************************************************/
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count))
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_hci.h b/drivers/net/wireless/ath6kl/include/a_hci.h
new file mode 100644
index 000000000000..b1a66308d828
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_hci.h
@@ -0,0 +1,668 @@
+//-
+// Copyright (c) 2009 Atheros Communications Inc.
+// All rights reserved.
+// $ATH_LICENSE_TARGET_C$
+//
+//
+
+
+#ifndef __A_HCI_H__
+#define __A_HCI_H__
+
+#define HCI_CMD_OGF_MASK            0x3F
+#define HCI_CMD_OGF_SHIFT           10
+#define HCI_CMD_GET_OGF(opcode)     ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
+
+#define HCI_CMD_OCF_MASK            0x3FF
+#define HCI_CMD_OCF_SHIFT           0 
+#define HCI_CMD_GET_OCF(opcode)     (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
+
+#define HCI_FORM_OPCODE(ocf, ogf)    ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
+                                          (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
+
+
+/*======== HCI Opcode groups ===============*/
+#define OGF_NOP                         0x00
+#define OGF_LINK_CONTROL                0x01
+#define OGF_LINK_POLICY                 0x03
+#define OGF_INFO_PARAMS                 0x04
+#define OGF_STATUS                      0x05
+#define OGF_TESTING                     0x06
+#define OGF_BLUETOOTH                   0x3E
+#define OGF_VENDOR_DEBUG                0x3F
+
+
+
+#define OCF_NOP                         0x00
+
+
+/*===== Link Control Commands Opcode===================*/
+#define OCF_HCI_Create_Physical_Link                0x35
+#define OCF_HCI_Accept_Physical_Link_Req            0x36
+#define OCF_HCI_Disconnect_Physical_Link            0x37
+#define OCF_HCI_Create_Logical_Link                 0x38
+#define OCF_HCI_Accept_Logical_Link                 0x39
+#define OCF_HCI_Disconnect_Logical_Link             0x3A
+#define OCF_HCI_Logical_Link_Cancel                 0x3B
+#define OCF_HCI_Flow_Spec_Modify                    0x3C
+
+
+
+/*===== Link Policy Commands Opcode====================*/
+#define OCF_HCI_Set_Event_Mask                      0x01
+#define OCF_HCI_Reset                               0x03
+#define OCF_HCI_Read_Conn_Accept_Timeout            0x15
+#define OCF_HCI_Write_Conn_Accept_Timeout           0x16
+#define OCF_HCI_Read_Link_Supervision_Timeout       0x36
+#define OCF_HCI_Write_Link_Supervision_Timeout      0x37
+#define OCF_HCI_Enhanced_Flush                      0x5F
+#define OCF_HCI_Read_Logical_Link_Accept_Timeout    0x61
+#define OCF_HCI_Write_Logical_Link_Accept_Timeout   0x62
+#define OCF_HCI_Set_Event_Mask_Page_2               0x63
+#define OCF_HCI_Read_Location_Data                  0x64
+#define OCF_HCI_Write_Location_Data                 0x65
+#define OCF_HCI_Read_Flow_Control_Mode              0x66
+#define OCF_HCI_Write_Flow_Control_Mode             0x67
+#define OCF_HCI_Read_BE_Flush_Timeout               0x69
+#define OCF_HCI_Write_BE_Flush_Timeout              0x6A
+#define OCF_HCI_Short_Range_Mode                    0x6B
+
+
+/*======== Info Commands Opcode========================*/
+#define OCF_HCI_Read_Local_Ver_Info                 0x01
+#define OCF_HCI_Read_Local_Supported_Cmds           0x02
+#define OCF_HCI_Read_Data_Block_Size                0x0A
+/*======== Status Commands Opcode======================*/
+#define OCF_HCI_Read_Failed_Contact_Counter         0x01
+#define OCF_HCI_Reset_Failed_Contact_Counter        0x02
+#define OCF_HCI_Read_Link_Quality                   0x03
+#define OCF_HCI_Read_RSSI                           0x05
+#define OCF_HCI_Read_Local_AMP_Info                 0x09    
+#define OCF_HCI_Read_Local_AMP_ASSOC                0x0A
+#define OCF_HCI_Write_Remote_AMP_ASSOC              0x0B
+
+
+/*======= AMP_ASSOC Specific TLV tags =================*/
+#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE             0x1
+#define AMP_ASSOC_PREF_CHAN_LIST                    0x2
+#define AMP_ASSOC_CONNECTED_CHAN                    0x3
+#define AMP_ASSOC_PAL_CAPABILITIES                  0x4
+#define AMP_ASSOC_PAL_VERSION                       0x5
+
+
+/*========= PAL Events =================================*/
+#define PAL_COMMAND_COMPLETE_EVENT                  0x0E
+#define PAL_COMMAND_STATUS_EVENT                    0x0F
+#define PAL_HARDWARE_ERROR_EVENT                    0x10
+#define PAL_FLUSH_OCCURRED_EVENT                    0x11
+#define PAL_LOOPBACK_EVENT                          0x19
+#define PAL_BUFFER_OVERFLOW_EVENT                   0x1A
+#define PAL_QOS_VIOLATION_EVENT                     0x1E
+#define PAL_ENHANCED_FLUSH_COMPLT_EVENT             0x39
+#define PAL_PHYSICAL_LINK_COMPL_EVENT               0x40
+#define PAL_CHANNEL_SELECT_EVENT                    0x41
+#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT          0x42
+#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT       0x43
+#define PAL_PHY_LINK_RECOVERY_EVENT                 0x44
+#define PAL_LOGICAL_LINK_COMPL_EVENT                0x45
+#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT     0x46
+#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT            0x47
+#define PAL_NUM_COMPL_DATA_BLOCK_EVENT              0x48
+#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT     0x4C
+#define PAL_AMP_STATUS_CHANGE_EVENT                 0x4D
+/*======== End of PAL events definiton =================*/
+
+
+/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
+#define Timer_Conn_Accept_TO                        0x01
+#define Timer_Link_Supervision_TO                   0x02
+
+#define NUM_HCI_COMMAND_PKTS                0x1
+
+
+/*====== NOP Cmd ============================*/
+#define HCI_CMD_NOP                     HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
+
+
+/*===== Link Control Commands================*/
+#define HCI_Create_Physical_Link        HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Physical_Link_Req    HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Physical_Link    HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Create_Logical_Link         HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Logical_Link         HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Logical_Link     HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Logical_Link_Cancel         HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
+#define HCI_Flow_Spec_Modify            HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
+
+
+/*===== Link Policy Commands ================*/
+#define HCI_Set_Event_Mask              HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
+#define HCI_Reset                       HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
+#define HCI_Enhanced_Flush              HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
+#define HCI_Read_Conn_Accept_Timeout    HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Conn_Accept_Timeout   HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Logical_Link_Accept_Timeout    HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Logical_Link_Accept_Timeout   HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Link_Supervision_Timeout       HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Link_Supervision_Timeout      HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Location_Data          HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
+#define HCI_Write_Location_Data         HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
+#define HCI_Set_Event_Mask_Page_2       HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
+#define HCI_Read_Flow_Control_Mode      HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_Flow_Control_Mode     HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_BE_Flush_Timeout      HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_BE_Flush_Timeout       HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Short_Range_Mode            HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)            
+
+
+/*===== Info Commands =====================*/
+#define HCI_Read_Local_Ver_Info         HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info,  OGF_INFO_PARAMS)
+#define HCI_Read_Local_Supported_Cmds   HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
+#define HCI_Read_Data_Block_Size        HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
+
+/*===== Status Commands =====================*/
+#define HCI_Read_Link_Quality           HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
+#define HCI_Read_RSSI                   HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
+#define HCI_Read_Local_AMP_Info         HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
+#define HCI_Read_Local_AMP_ASSOC        HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
+#define HCI_Write_Remote_AMP_ASSOC      HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
+
+/*====== End of cmd definitions =============*/
+
+
+
+/*===== Timeouts(private - can't come from HCI)=================*/
+#define Conn_Accept_TO                  HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
+#define Link_Supervision_TO             HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
+
+/*----- PAL Constants (Sec 6 of Doc)------------------------*/
+#define Max80211_PAL_PDU_Size      1492
+#define Max80211_AMP_ASSOC_Len      672
+#define MinGUserPrio                4
+#define MaxGUserPrio                7
+#define BEUserPrio0                 0
+#define BEUserPrio1                 3
+#define Max80211BeaconPeriod        2000    /* in millisec */
+#define ShortRangeModePowerMax      4       /* dBm */
+
+/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
+typedef enum {
+    ACL_DATA = 0x01,
+    ACTIVITY_REPORT,
+    SECURED_FRAMES,
+    LINK_SUPERVISION_REQ,
+    LINK_SUPERVISION_RESP,
+}PAL_PROTOCOL_IDENTIFIERS;
+
+#define HCI_CMD_HDR_SZ          3
+#define HCI_EVENT_HDR_SIZE      2
+#define MAX_EVT_PKT_SZ          255
+#define AMP_ASSOC_MAX_FRAG_SZ   248
+#define AMP_MAX_GUARANTEED_BW   20000
+
+#define DEFAULT_CONN_ACCPT_TO   5000
+#define DEFAULT_LL_ACCPT_TO     5000
+#define DEFAULT_LSTO            10000
+
+#define PACKET_BASED_FLOW_CONTROL_MODE      0x00
+#define DATA_BLK_BASED_FLOW_CONTROL_MODE    0x01
+
+#define SERVICE_TYPE_BEST_EFFORT    0x01
+#define SERVICE_TYPE_GUARANTEED     0x02
+
+#define MAC_ADDR_LEN            6
+#define LINK_KEY_LEN            32
+
+typedef enum  {
+    ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
+    ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
+    ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
+    ACL_DATA_PB_COMPLETE_PDU = 0x03,
+} ACL_DATA_PB_FLAGS;
+#define ACL_DATA_PB_FLAGS_SHIFT     12
+
+typedef enum {
+    ACL_DATA_BC_POINT_TO_POINT = 0x00,
+} ACL_DATA_BC_FLAGS;
+#define ACL_DATA_BC_FLAGS_SHIFT     14
+
+/* Command pkt */
+typedef struct  hci_cmd_pkt_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     params[255];
+} POSTPACK HCI_CMD_PKT;
+
+#define ACL_DATA_HDR_SIZE   4   /* hdl_and flags + data_len */
+/* Data pkt */
+typedef struct  hci_acl_data_pkt_t {
+    A_UINT16    hdl_and_flags;
+    A_UINT16    data_len;
+    A_UINT8     data[Max80211_PAL_PDU_Size];
+} POSTPACK HCI_ACL_DATA_PKT;
+
+/* Event pkt */
+typedef struct  hci_event_pkt_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     params[256];
+} POSTPACK HCI_EVENT_PKT;
+
+
+/*============== HCI Command definitions ======================= */
+typedef struct hci_cmd_phy_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     link_key_len;
+    A_UINT8     link_key_type;
+    A_UINT8     link_key[LINK_KEY_LEN];
+} POSTPACK HCI_CMD_PHY_LINK;
+
+typedef struct  hci_cmd_write_rem_amp_assoc_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT16    len_so_far;
+    A_UINT16    amp_assoc_remaining_len;
+    A_UINT8     amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
+
+
+typedef struct  hci_cmd_opcode_hdl_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+} POSTPACK HCI_CMD_READ_LINK_QUAL,
+           HCI_CMD_FLUSH,
+           HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct  hci_cmd_read_local_amp_assoc_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT16    len_so_far;
+    A_UINT16    max_rem_amp_assoc_len;
+} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
+
+
+typedef struct hci_cmd_set_event_mask_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT64    mask;
+}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
+
+
+typedef struct  hci_cmd_enhanced_flush_t{
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    A_UINT8     type;
+} POSTPACK HCI_CMD_ENHANCED_FLUSH;
+
+
+typedef struct  hci_cmd_write_timeout_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    timeout;
+} POSTPACK  HCI_CMD_WRITE_TIMEOUT;
+
+typedef struct  hci_cmd_write_link_supervision_timeout_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    A_UINT16    timeout;
+} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct  hci_cmd_write_flow_control_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     mode;
+} POSTPACK  HCI_CMD_WRITE_FLOW_CONTROL;
+
+typedef struct  location_data_cfg_t {
+    A_UINT8     reg_domain_aware;
+    A_UINT8     reg_domain[3];
+    A_UINT8     reg_options;
+} POSTPACK LOCATION_DATA_CFG;
+
+typedef struct  hci_cmd_write_location_data_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    LOCATION_DATA_CFG   cfg;
+} POSTPACK  HCI_CMD_WRITE_LOCATION_DATA;
+
+
+typedef struct  flow_spec_t {
+    A_UINT8     id;
+    A_UINT8     service_type;
+    A_UINT16    max_sdu;
+    A_UINT32    sdu_inter_arrival_time;
+    A_UINT32    access_latency;
+    A_UINT32    flush_timeout;
+} POSTPACK FLOW_SPEC;
+
+
+typedef struct  hci_cmd_create_logical_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    FLOW_SPEC   tx_flow_spec;
+    FLOW_SPEC   rx_flow_spec;
+} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
+
+typedef struct  hci_cmd_flow_spec_modify_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    hdl;
+    FLOW_SPEC   tx_flow_spec;
+    FLOW_SPEC   rx_flow_spec;
+} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
+
+typedef struct hci_cmd_logical_link_cancel_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     tx_flow_spec_id;
+} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
+
+typedef struct  hci_cmd_disconnect_logical_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT16    logical_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
+
+typedef struct  hci_cmd_disconnect_phy_link_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
+
+typedef struct  hci_cmd_srm_t {
+    A_UINT16    opcode;
+    A_UINT8     param_length;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     mode;
+} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
+/*============== HCI Command definitions end ======================= */
+
+
+
+/*============== HCI Event definitions ============================= */
+
+/* Command complete event */
+typedef struct  hci_event_cmd_complete_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     num_hci_cmd_pkts;
+    A_UINT16    opcode;
+    A_UINT8     params[255];
+} POSTPACK HCI_EVENT_CMD_COMPLETE;
+
+
+/* Command status event */
+typedef struct  hci_event_cmd_status_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     num_hci_cmd_pkts;
+    A_UINT16    opcode;
+} POSTPACK HCI_EVENT_CMD_STATUS;
+
+/* Hardware Error event */
+typedef struct  hci_event_hw_err_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     hw_err_code;
+} POSTPACK HCI_EVENT_HW_ERR;
+
+/* Flush occured event */
+/* Qos Violation event */
+typedef struct  hci_event_handle_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    handle;
+} POSTPACK HCI_EVENT_FLUSH_OCCRD,
+           HCI_EVENT_QOS_VIOLATION;
+
+/* Loopback command event */
+typedef struct hci_loopback_cmd_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     params[252];
+} POSTPACK HCI_EVENT_LOOPBACK_CMD;
+
+/* Data buffer overflow event */
+typedef struct  hci_data_buf_overflow_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     link_type;
+} POSTPACK  HCI_EVENT_DATA_BUF_OVERFLOW;
+
+/* Enhanced Flush complete event */
+typedef struct hci_enhanced_flush_complt_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    hdl;
+} POSTPACK  HCI_EVENT_ENHANCED_FLUSH_COMPLT;
+
+/* Channel select event */
+typedef struct  hci_event_chan_select_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_EVENT_CHAN_SELECT;
+
+/* Physical Link Complete event */
+typedef struct  hci_event_phy_link_complete_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
+
+/* Logical Link complete event */
+typedef struct hci_event_logical_link_complete_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    logical_link_hdl;
+    A_UINT8     phy_hdl;
+    A_UINT8     tx_flow_id;
+} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
+
+/* Disconnect Logical Link complete event */
+typedef struct hci_event_disconnect_logical_link_event_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    logical_link_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
+
+/* Disconnect Physical Link complete event */
+typedef struct hci_event_disconnect_phy_link_complete_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
+
+typedef struct hci_event_physical_link_loss_early_warning_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_hdl;
+    A_UINT8     reason;
+} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
+
+typedef struct hci_event_physical_link_recovery_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     phy_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
+
+
+/* Flow spec modify complete event */
+/* Flush event */
+typedef struct hci_event_status_handle_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT16    handle;
+} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
+           HCI_EVENT_FLUSH;
+
+
+/* Num of completed data blocks event */
+typedef struct hci_event_num_of_compl_data_blks_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT16    num_data_blks;
+    A_UINT8     num_handles;
+    A_UINT8     params[255];
+} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
+
+/* Short range mode change complete event */
+typedef struct  hci_srm_cmpl_t {
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     phy_link;
+    A_UINT8     state;
+} POSTPACK HCI_EVENT_SRM_COMPL;
+
+typedef struct hci_event_amp_status_change_t{
+    A_UINT8     event_code;
+    A_UINT8     param_len;
+    A_UINT8     status;
+    A_UINT8     amp_status;
+} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
+
+/*============== Event definitions end =========================== */
+
+
+typedef struct  local_amp_info_resp_t {
+    A_UINT8     status;
+    A_UINT8     amp_status;
+    A_UINT32    total_bw;           /* kbps */
+    A_UINT32    max_guranteed_bw;   /* kbps */
+    A_UINT32    min_latency;
+    A_UINT32    max_pdu_size;
+    A_UINT8     amp_type;
+    A_UINT16    pal_capabilities;
+    A_UINT16    amp_assoc_len;
+    A_UINT32    max_flush_timeout;  /* in ms */
+    A_UINT32    be_flush_timeout;   /* in ms */
+} POSTPACK  LOCAL_AMP_INFO;
+
+typedef struct  amp_assoc_cmd_resp_t{
+    A_UINT8     status;
+    A_UINT8     phy_hdl;
+    A_UINT16    amp_assoc_len;
+    A_UINT8     amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+}POSTPACK AMP_ASSOC_CMD_RESP;
+
+
+enum PAL_HCI_CMD_STATUS {
+    PAL_HCI_CMD_PROCESSED,
+    PAL_HCI_CMD_IGNORED
+}; 
+
+
+/*============= HCI Error Codes =======================*/
+#define HCI_SUCCESS                             0x00
+#define HCI_ERR_UNKNOW_CMD                      0x01
+#define HCI_ERR_UNKNOWN_CONN_ID                 0x02
+#define HCI_ERR_HW_FAILURE                      0x03
+#define HCI_ERR_PAGE_TIMEOUT                    0x04
+#define HCI_ERR_AUTH_FAILURE                    0x05
+#define HCI_ERR_KEY_MISSING                     0x06
+#define HCI_ERR_MEM_CAP_EXECED                  0x07
+#define HCI_ERR_CON_TIMEOUT                     0x08
+#define HCI_ERR_CON_LIMIT_EXECED                0x09
+#define	HCI_ERR_ACL_CONN_ALRDY_EXISTS	        0x0B
+#define	HCI_ERR_COMMAND_DISALLOWED		        0x0C
+#define HCI_ERR_CONN_REJ_BY_LIMIT_RES           0x0D
+#define HCI_ERR_CONN_REJ_BY_SEC                 0x0E
+#define HCI_ERR_CONN_REJ_BY_BAD_ADDR            0x0F
+#define HCI_ERR_CONN_ACCPT_TIMEOUT              0x10
+#define HCI_ERR_UNSUPPORT_FEATURE               0x11
+#define HCI_ERR_INVALID_HCI_CMD_PARAMS          0x12
+#define HCI_ERR_REMOTE_USER_TERMINATE_CONN      0x13
+#define HCI_ERR_CON_TERM_BY_HOST                0x16
+#define HCI_ERR_UNSPECIFIED_ERROR               0x1F
+#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT     0x25
+#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT       0x27
+#define HCI_ERR_QOS_UNACCEPTABLE_PARM           0x2C
+#define HCI_ERR_QOS_REJECTED                    0x2D
+#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN       0x39
+
+/*============= HCI Error Codes End =======================*/
+
+
+/* Following are event return parameters.. part of HCI events 
+ */
+typedef struct  timeout_read_t {
+    A_UINT8     status;
+    A_UINT16    timeout;
+}POSTPACK TIMEOUT_INFO;
+
+typedef struct  link_supervision_timeout_read_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+    A_UINT16    timeout;
+}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
+
+typedef struct  status_hdl_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+}POSTPACK INFO_STATUS_HDL;
+
+typedef struct write_remote_amp_assoc_t{
+    A_UINT8     status;
+    A_UINT8     hdl;
+}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
+
+typedef struct  read_loc_info_t {
+    A_UINT8             status;
+    LOCATION_DATA_CFG   loc;
+}POSTPACK READ_LOC_INFO;
+
+typedef struct  read_flow_ctrl_mode_t {
+    A_UINT8     status;
+    A_UINT8     mode;
+}POSTPACK READ_FLWCTRL_INFO;
+
+typedef struct  read_data_blk_size_t {
+    A_UINT8     status;
+    A_UINT16    max_acl_data_pkt_len;
+    A_UINT16    data_block_len;
+    A_UINT16    total_num_data_blks;
+}POSTPACK READ_DATA_BLK_SIZE_INFO;
+
+/* Read Link quality info */
+typedef struct link_qual_t {
+    A_UINT8     status;
+    A_UINT16    hdl;
+    A_UINT8     link_qual;
+} POSTPACK READ_LINK_QUAL_INFO,
+            READ_RSSI_INFO;
+
+typedef struct ll_cancel_resp_t {
+    A_UINT8 status;
+    A_UINT8 phy_link_hdl;
+    A_UINT8 tx_flow_spec_id;
+} POSTPACK LL_CANCEL_RESP;
+
+typedef struct read_local_ver_info_t {
+    A_UINT8     status;
+    A_UINT8     hci_version;
+    A_UINT16    hci_revision;
+    A_UINT8     pal_version;
+    A_UINT16    manf_name;
+    A_UINT16    pal_sub_ver;
+} POSTPACK READ_LOCAL_VER_INFO;
+
+
+#endif  /* __A_HCI_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/a_osapi.h b/drivers/net/wireless/ath6kl/include/a_osapi.h
new file mode 100644
index 000000000000..17138cec2f77
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_osapi.h
@@ -0,0 +1,53 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_osapi.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_OSAPI_H_
+#define _A_OSAPI_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/osapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/osapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/osapi_win.h"
+#include "../os/win_art/include/netbuf.h"
+#endif
+
+#ifdef WIN_NWF
+#include <osapi_win.h>
+#endif
+
+#endif /* _OSAPI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_types.h b/drivers/net/wireless/ath6kl/include/a_types.h
new file mode 100644
index 000000000000..bf4f1a485b45
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_types.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_types.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_TYPES_H_
+#define _A_TYPES_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athtypes_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athtypes_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/athtypes_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <athtypes_win.h>
+#endif
+
+#endif /* _ATHTYPES_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/aggr_recv_api.h b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h
new file mode 100644
index 000000000000..185354eddcde
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h
@@ -0,0 +1,136 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RECV_API_H__
+#define __AGGR_RECV_API_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (* RX_CALLBACK)(void * dev, void *osbuf);
+
+typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+
+/*
+ * aggr_init:
+ * Initialises the data structures, allocates data queues and 
+ * os buffers. Netbuf allocator is the input param, used by the
+ * aggr module for allocation of NETBUFs from driver context.
+ * These NETBUFs are used for AMSDU processing.
+ * Returns the context for the aggr module.
+ */
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator);
+
+
+/*
+ * aggr_register_rx_dispatcher:
+ * Registers OS call back function to deliver the
+ * frames to OS. This is generally the topmost layer of
+ * the driver context, after which the frames go to
+ * IP stack via the call back function.
+ * This dispatcher is active only when aggregation is ON.
+ */
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev,  RX_CALLBACK fn);
+
+
+/*
+ * aggr_process_bar:
+ * When target receives BAR, it communicates to host driver
+ * for modifying window parameters. Target indicates this via the 
+ * event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames
+ * up to the indicated sequence number.
+ */
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no);
+
+
+/*
+ * aggr_recv_addba_req_evt:
+ * This event is to initiate/modify the receive side window.
+ * Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup 
+ * recv re-ordering queues. Target will negotiate ADDBA with peer, 
+ * and indicate via this event after succesfully completing the 
+ * negotiation. This happens in two situations:
+ *  1. Initial setup of aggregation
+ *  2. Renegotiation of current recv window.
+ * Window size for re-ordering is limited by target buffer
+ * space, which is reflected in win_sz.
+ * (Re)Start the periodic timer to deliver long standing frames,
+ * in hold_q to OS.
+ */
+void
+aggr_recv_addba_req_evt(void * cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz);
+
+
+/*
+ * aggr_recv_delba_req_evt:
+ * Target indicates deletion of a BA window for a tid via the
+ * WMI_DELBA_EVENTID. Host would deliver all the frames in the 
+ * hold_q, reset tid config and disable the periodic timer, if 
+ * aggr is not enabled on any tid.
+ */
+void
+aggr_recv_delba_req_evt(void * cntxt, A_UINT8 tid);
+
+
+
+/*
+ * aggr_process_recv_frm:
+ * Called only for data frames. When aggr is ON for a tid, the buffer 
+ * is always consumed, and osbuf would be NULL. For a non-aggr case,
+ * osbuf is not modified.
+ * AMSDU frames are consumed and are later freed. They are sliced and 
+ * diced to individual frames and dispatched to stack.
+ * After consuming a osbuf(when aggr is ON), a previously registered
+ * callback may be called to deliver frames in order.
+ */
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf);
+
+
+/*
+ * aggr_module_destroy:
+ * Frees up all the queues and frames in them. Releases the cntxt to OS.
+ */
+void
+aggr_module_destroy(void *cntxt);
+
+/*
+ * Dumps the aggregation stats 
+ */
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf);
+
+/* 
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ *  hold Q state.  Examples include when a Connect event or disconnect event is 
+ *  received. 
+ */
+void
+aggr_reset_state(void *cntxt);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AGGR_RECV_API_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/ar3kconfig.h b/drivers/net/wireless/ath6kl/include/ar3kconfig.h
new file mode 100644
index 000000000000..8d7bf2a6ec75
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar3kconfig.h
@@ -0,0 +1,58 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar3Kconfig.h" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/* AR3K module configuration APIs for HCI-bridge operation */
+
+#ifndef AR3KCONFIG_H_
+#define AR3KCONFIG_H_
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT         (1 << 0)
+#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD              (1 << 1)
+#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY     (1 << 2)
+#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP        (1 << 3)
+
+
+typedef struct {
+    A_UINT32                 Flags;           /* config flags */
+    void                     *pHCIDev;        /* HCI bridge device     */
+    HCI_TRANSPORT_PROPERTIES *pHCIProps;      /* HCI bridge props      */
+    HIF_DEVICE               *pHIFDevice;     /* HIF layer device      */
+    
+    A_UINT32                 AR3KBaudRate;    /* AR3K operational baud rate */
+    A_UINT16                 AR6KScale;       /* AR6K UART scale value */    
+    A_UINT16                 AR6KStep;        /* AR6K UART step value  */
+    struct hci_dev           *pBtStackHCIDev; /* BT Stack HCI dev */
+} AR3K_CONFIG_INFO;
+                                                                                        
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfigInfo);
+
+A_STATUS AR3KConfigureExit(void *config);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*AR3KCONFIG_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ar6000_api.h b/drivers/net/wireless/ath6kl/include/ar6000_api.h
new file mode 100644
index 000000000000..431520fb0b1c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6000_api.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API to access the OS dependent atheros host driver
+// by the WMI or WLAN generic modules.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _AR6000_API_H_
+#define _AR6000_API_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/ar6xapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/ar6xapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/ar6xapi_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#endif /* _AR6000_API_H */
+
diff --git a/drivers/net/wireless/ath6kl/include/ar6000_diag.h b/drivers/net/wireless/ath6kl/include/ar6000_diag.h
new file mode 100644
index 000000000000..ae87e2b23b6e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6000_diag.h
@@ -0,0 +1,44 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_diag.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef AR6000_DIAG_H_
+#define AR6000_DIAG_H_
+
+
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                     A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval);
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs);
+
+#endif /*AR6000_DIAG_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ar6kap_common.h b/drivers/net/wireless/ath6kl/include/ar6kap_common.h
new file mode 100644
index 000000000000..87b183c45bf5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6kap_common.h
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+
+// <copyright file="ar6kap_common.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+
+//==============================================================================
+
+// This file contains the definitions of common AP mode data structures.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _AR6KAP_COMMON_H_
+#define _AR6KAP_COMMON_H_
+/*
+ * Used with AR6000_XIOCTL_AP_GET_STA_LIST
+ */
+typedef struct {
+    A_UINT8     mac[ATH_MAC_LEN];
+    A_UINT8     aid;
+    A_UINT8     keymgmt;
+    A_UINT8     ucipher;
+    A_UINT8     auth;
+} station_t;
+typedef struct {
+    station_t sta[AP_MAX_NUM_STA];
+} ap_get_sta_t;
+#endif /* _AR6KAP_COMMON_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/athbtfilter.h b/drivers/net/wireless/ath6kl/include/athbtfilter.h
new file mode 100644
index 000000000000..4ea3fa5b2f5d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athbtfilter.h
@@ -0,0 +1,129 @@
+//------------------------------------------------------------------------------
+// <copyright file="athbtfilter.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Public Bluetooth filter APIs
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef ATHBTFILTER_H_
+#define ATHBTFILTER_H_
+
+
+typedef enum _ATHBT_HCI_CTRL_TYPE {
+    ATHBT_HCI_COMMAND     = 0,
+    ATHBT_HCI_EVENT       = 1,
+} ATHBT_HCI_CTRL_TYPE;
+
+typedef enum _ATHBT_STATE_INDICATION {
+    ATH_BT_NOOP        = 0,
+    ATH_BT_INQUIRY     = 1,
+    ATH_BT_CONNECT     = 2,
+    ATH_BT_SCO         = 3,
+    ATH_BT_ACL         = 4,
+    ATH_BT_A2DP        = 5,
+    ATH_BT_ESCO        = 6,
+    /* new states go here.. */
+
+    ATH_BT_MAX_STATE_INDICATION
+} ATHBT_STATE_INDICATION;
+
+    /* filter function for OUTGOING commands and INCOMMING events */
+typedef void   (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length);
+
+    /* filter function for OUTGOING data HCI packets */
+typedef void   (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length);
+
+typedef enum _ATHBT_STATE {
+    STATE_OFF  = 0,
+    STATE_ON   = 1,
+    STATE_MAX
+} ATHBT_STATE;
+
+    /* BT state indication (when filter functions are not used) */
+
+typedef void   (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion);
+
+typedef struct _ATHBT_FILTER_INSTANCE {
+#ifdef UNDER_CE
+    WCHAR                       *pWlanAdapterName;  /* filled in by user */
+#else
+    A_CHAR                      *pWlanAdapterName;  /* filled in by user */
+#endif /* UNDER_CE */
+    int                         FilterEnabled;      /* filtering is enabled */
+    int                         Attached;           /* filter library is attached */
+    void                        *pContext;          /* private context for filter library */
+    ATHBT_FILTER_CMD_EVENTS_FN  pFilterCmdEvents;   /* function ptr to filter a command or event */
+    ATHBT_FILTER_DATA_FN        pFilterAclDataOut;  /* function ptr to filter ACL data out (to radio) */
+    ATHBT_FILTER_DATA_FN        pFilterAclDataIn;   /* function ptr to filter ACL data in (from radio) */
+    ATHBT_INDICATE_STATE_FN     pIndicateState;     /* function ptr to indicate a state */
+} ATH_BT_FILTER_INSTANCE;
+
+
+/* API MACROS */
+
+#define AthBtFilterHciCommand(instance,packet,length)          \
+    if ((instance)->FilterEnabled) {                           \
+        (instance)->pFilterCmdEvents((instance)->pContext,     \
+                                   ATHBT_HCI_COMMAND,          \
+                                   (unsigned char *)(packet),  \
+                                   (length));                  \
+    }
+
+#define AthBtFilterHciEvent(instance,packet,length)            \
+    if ((instance)->FilterEnabled) {                           \
+        (instance)->pFilterCmdEvents((instance)->pContext,     \
+                                   ATHBT_HCI_EVENT,            \
+                                   (unsigned char *)(packet),  \
+                                   (length));                  \
+    }
+
+#define AthBtFilterHciAclDataOut(instance,packet,length)     \
+    if ((instance)->FilterEnabled) {                         \
+        (instance)->pFilterAclDataOut((instance)->pContext,  \
+                                 (unsigned char *)(packet),  \
+                                 (length));                  \
+    }
+
+#define AthBtFilterHciAclDataIn(instance,packet,length)      \
+    if ((instance)->FilterEnabled) {                         \
+        (instance)->pFilterAclDataIn((instance)->pContext,   \
+                                 (unsigned char *)(packet),  \
+                                 (length));                  \
+    }
+        
+/* if filtering is not desired, the application can indicate the state directly using this
+ * macro:
+ */
+#define AthBtIndicateState(instance,indication,state)           \
+    if ((instance)->FilterEnabled) {                            \
+        (instance)->pIndicateState((instance)->pContext,        \
+                                   (indication),                \
+                                   (state),                     \
+                                   0);                          \
+    }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API prototypes */
+int     AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, A_UINT32 flags);
+void    AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*ATHBTFILTER_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/athdefs.h b/drivers/net/wireless/ath6kl/include/athdefs.h
new file mode 100644
index 000000000000..cc8bb3cc81be
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athdefs.h
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------
+// <copyright file="athdefs.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __ATHDEFS_H__
+#define __ATHDEFS_H__
+
+/*
+ * This file contains definitions that may be used across both
+ * Host and Target software.  Nothing here is module-dependent
+ * or platform-dependent.
+ */
+
+/*
+ * Generic error codes that can be used by hw, sta, ap, sim, dk
+ * and any other environments. Since these are enums, feel free to
+ * add any more codes that you need.
+ */
+
+typedef enum {
+    A_ERROR = -1,               /* Generic error return */
+    A_OK = 0,                   /* success */
+                                /* Following values start at 1 */
+    A_DEVICE_NOT_FOUND,         /* not able to find PCI device */
+    A_NO_MEMORY,                /* not able to allocate memory, not available */
+    A_MEMORY_NOT_AVAIL,         /* memory region is not free for mapping */
+    A_NO_FREE_DESC,             /* no free descriptors available */
+    A_BAD_ADDRESS,              /* address does not match descriptor */
+    A_WIN_DRIVER_ERROR,         /* used in NT_HW version, if problem at init */
+    A_REGS_NOT_MAPPED,          /* registers not correctly mapped */
+    A_EPERM,                    /* Not superuser */
+    A_EACCES,                   /* Access denied */
+    A_ENOENT,                   /* No such entry, search failed, etc. */
+    A_EEXIST,                   /* The object already exists (can't create) */
+    A_EFAULT,                   /* Bad address fault */
+    A_EBUSY,                    /* Object is busy */
+    A_EINVAL,                   /* Invalid parameter */
+    A_EMSGSIZE,                 /* Inappropriate message buffer length */
+    A_ECANCELED,                /* Operation canceled */
+    A_ENOTSUP,                  /* Operation not supported */
+    A_ECOMM,                    /* Communication error on send */
+    A_EPROTO,                   /* Protocol error */
+    A_ENODEV,                   /* No such device */
+    A_EDEVNOTUP,                /* device is not UP */
+    A_NO_RESOURCE,              /* No resources for requested operation */
+    A_HARDWARE,                 /* Hardware failure */
+    A_PENDING,                  /* Asynchronous routine; will send up results la
+ter (typically in callback) */
+    A_EBADCHANNEL,              /* The channel cannot be used */
+    A_DECRYPT_ERROR,            /* Decryption error */
+    A_PHY_ERROR,                /* RX PHY error */
+    A_CONSUMED                  /* Object was consumed */
+} A_STATUS;
+
+#define A_SUCCESS(x)        (x == A_OK)
+#define A_FAILED(x)         (!A_SUCCESS(x))
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* __ATHDEFS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/athendpack.h b/drivers/net/wireless/ath6kl/include/athendpack.h
new file mode 100644
index 000000000000..b0c7e1425f74
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athendpack.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="athendpack.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// end compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athendpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athendpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athendpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athendpack_win.h>
+#endif 
diff --git a/drivers/net/wireless/ath6kl/include/athstartpack.h b/drivers/net/wireless/ath6kl/include/athstartpack.h
new file mode 100644
index 000000000000..04b3cc240b35
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athstartpack.h
@@ -0,0 +1,47 @@
+//------------------------------------------------------------------------------
+// <copyright file="athstartpack.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// start compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athstartpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athstartpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athstartpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athstartpack_win.h>
+#endif 
diff --git a/drivers/net/wireless/ath6kl/include/bmi.h b/drivers/net/wireless/ath6kl/include/bmi.h
new file mode 100644
index 000000000000..64e817ed6929
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/bmi.h
@@ -0,0 +1,128 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// BMI declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _BMI_H_
+#define _BMI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "hif.h"
+#include "a_osapi.h"
+#include "bmi_msg.h"
+
+void
+BMIInit(void);
+
+A_STATUS
+BMIDone(HIF_DEVICE *device);
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+              A_UINT32 address,
+              A_UCHAR *buffer,
+              A_UINT32 length);
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+               A_UINT32 address,
+               A_UCHAR *buffer,
+               A_UINT32 length);
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+           A_UINT32 address,
+           A_UINT32 *param);
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+               A_UINT32 address);
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+                   A_UINT32 address,
+                   A_UINT32 *param);
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+                    A_UINT32 address,
+                    A_UINT32 param);
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+                   A_UINT32 ROM_addr,
+                   A_UINT32 RAM_addr,
+                   A_UINT32 nbytes,
+                   A_UINT32 do_activate,
+                   A_UINT32 *patch_id);
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+                     A_UINT32 rompatch_id);
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+                    A_UINT32 rompatch_count,
+                    A_UINT32 *rompatch_list);
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+                      A_UINT32 rompatch_count,
+                      A_UINT32 *rompatch_list);
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+                 A_UINT32 address);
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+          A_UCHAR *buffer,
+          A_UINT32 length);
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device,
+                A_UINT32 address,
+                A_UCHAR *buffer,
+                A_UINT32 length);
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device,
+            A_UCHAR *buffer,
+            A_UINT32 length);
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device, 
+           A_UCHAR *buffer, 
+           A_UINT32 length, 
+           A_BOOL want_timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BMI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/bmi_msg.h b/drivers/net/wireless/ath6kl/include/bmi_msg.h
new file mode 100644
index 000000000000..1f48389f9664
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/bmi_msg.h
@@ -0,0 +1,231 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi_msg.h" company="Atheros">
+//    Copyright (c) 2004-2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __BMI_MSG_H__
+#define __BMI_MSG_H__
+
+/*
+ * Bootloader Messaging Interface (BMI)
+ *
+ * BMI is a very simple messaging interface used during initialization
+ * to read memory, write memory, execute code, and to define an
+ * application entry PC.
+ *
+ * It is used to download an application to AR6K, to provide
+ * patches to code that is already resident on AR6K, and generally
+ * to examine and modify state.  The Host has an opportunity to use
+ * BMI only once during bootup.  Once the Host issues a BMI_DONE
+ * command, this opportunity ends.
+ *
+ * The Host writes BMI requests to mailbox0, and reads BMI responses
+ * from mailbox0.   BMI requests all begin with a command
+ * (see below for specific commands), and are followed by
+ * command-specific data.
+ *
+ * Flow control:
+ * The Host can only issue a command once the Target gives it a
+ * "BMI Command Credit", using AR6K Counter #4.  As soon as the
+ * Target has completed a command, it issues another BMI Command
+ * Credit (so the Host can issue the next command).
+ *
+ * BMI handles all required Target-side cache flushing.
+ */
+
+
+/* Maximum data size used for BMI transfers */
+#define BMI_DATASZ_MAX                      256
+
+/* BMI Commands */
+
+#define BMI_NO_COMMAND                      0
+
+#define BMI_DONE                            1
+        /*
+         * Semantics: Host is done using BMI
+         * Request format:
+         *    A_UINT32      command (BMI_DONE)
+         * Response format: none
+         */
+
+#define BMI_READ_MEMORY                     2
+        /*
+         * Semantics: Host reads AR6K memory
+         * Request format:
+         *    A_UINT32      command (BMI_READ_MEMORY)
+         *    A_UINT32      address
+         *    A_UINT32      length, at most BMI_DATASZ_MAX
+         * Response format:
+         *    A_UINT8       data[length]
+         */
+
+#define BMI_WRITE_MEMORY                    3
+        /*
+         * Semantics: Host writes AR6K memory
+         * Request format:
+         *    A_UINT32       command (BMI_WRITE_MEMORY)
+         *    A_UINT32      address
+         *    A_UINT32      length, at most BMI_DATASZ_MAX
+         *    A_UINT8       data[length]
+         * Response format: none
+         */
+
+#define BMI_EXECUTE                         4
+        /*
+         * Semantics: Causes AR6K to execute code
+         * Request format:
+         *    A_UINT32      command (BMI_EXECUTE)
+         *    A_UINT32      address
+         *    A_UINT32      parameter
+         * Response format:
+         *    A_UINT32      return value
+         */
+
+#define BMI_SET_APP_START                   5
+        /*
+         * Semantics: Set Target application starting address
+         * Request format:
+         *    A_UINT32      command (BMI_SET_APP_START)
+         *    A_UINT32      address
+         * Response format: none
+         */
+
+#define BMI_READ_SOC_REGISTER               6
+        /*
+         * Semantics: Read a 32-bit Target SOC register.
+         * Request format:
+         *    A_UINT32      command (BMI_READ_REGISTER)
+         *    A_UINT32      address
+         * Response format: 
+         *    A_UINT32      value
+         */
+
+#define BMI_WRITE_SOC_REGISTER              7
+        /*
+         * Semantics: Write a 32-bit Target SOC register.
+         * Request format:
+         *    A_UINT32      command (BMI_WRITE_REGISTER)
+         *    A_UINT32      address
+         *    A_UINT32      value
+         *
+         * Response format: none
+         */
+
+#define BMI_GET_TARGET_ID                  8
+#define BMI_GET_TARGET_INFO                8
+        /*
+         * Semantics: Fetch the 4-byte Target information
+         * Request format:
+         *    A_UINT32      command (BMI_GET_TARGET_ID/INFO)
+         * Response format1 (old firmware):
+         *    A_UINT32      TargetVersionID
+         * Response format2 (newer firmware):
+         *    A_UINT32      TARGET_VERSION_SENTINAL
+         *    struct bmi_target_info;
+         */
+
+struct bmi_target_info {
+    A_UINT32 target_info_byte_count; /* size of this structure */
+    A_UINT32 target_ver;             /* Target Version ID */
+    A_UINT32 target_type;            /* Target type */
+};
+#define TARGET_VERSION_SENTINAL 0xffffffff
+#define TARGET_TYPE_AR6001 1
+#define TARGET_TYPE_AR6002 2
+#define TARGET_TYPE_AR6003 3
+
+
+#define BMI_ROMPATCH_INSTALL               9
+        /*
+         * Semantics: Install a ROM Patch.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_INSTALL)
+         *    A_UINT32      Target ROM Address
+         *    A_UINT32      Target RAM Address or Value (depending on Target Type)
+         *    A_UINT32      Size, in bytes
+         *    A_UINT32      Activate? 1-->activate;
+         *                            0-->install but do not activate
+         * Response format:
+         *    A_UINT32      PatchID
+         */
+
+#define BMI_ROMPATCH_UNINSTALL             10
+        /*
+         * Semantics: Uninstall a previously-installed ROM Patch,
+         * automatically deactivating, if necessary.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_UNINSTALL)
+         *    A_UINT32      PatchID
+         *
+         * Response format: none
+         */
+
+#define BMI_ROMPATCH_ACTIVATE              11
+        /*
+         * Semantics: Activate a list of previously-installed ROM Patches.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_ACTIVATE)
+         *    A_UINT32      rompatch_count
+         *    A_UINT32      PatchID[rompatch_count]
+         *
+         * Response format: none
+         */
+
+#define BMI_ROMPATCH_DEACTIVATE            12
+        /*
+         * Semantics: Deactivate a list of active ROM Patches.
+         * Request format:
+         *    A_UINT32      command (BMI_ROMPATCH_DEACTIVATE)
+         *    A_UINT32      rompatch_count
+         *    A_UINT32      PatchID[rompatch_count]
+         *
+         * Response format: none
+         */
+
+
+#define BMI_LZ_STREAM_START                13
+        /*
+         * Semantics: Begin an LZ-compressed stream of input
+         * which is to be uncompressed by the Target to an
+         * output buffer at address.  The output buffer must
+         * be sufficiently large to hold the uncompressed
+         * output from the compressed input stream.  This BMI
+         * command should be followed by a series of 1 or more
+         * BMI_LZ_DATA commands.
+         *    A_UINT32      command (BMI_LZ_STREAM_START)
+         *    A_UINT32      address
+         * Note: Not supported on all versions of ROM firmware.
+         */
+
+#define BMI_LZ_DATA                        14
+        /*
+         * Semantics: Host writes AR6K memory with LZ-compressed
+         * data which is uncompressed by the Target.  This command
+         * must be preceded by a BMI_LZ_STREAM_START command. A series
+         * of BMI_LZ_DATA commands are considered part of a single
+         * input stream until another BMI_LZ_STREAM_START is issued.
+         * Request format:
+         *    A_UINT32      command (BMI_LZ_DATA)
+         *    A_UINT32      length (of compressed data),
+         *                  at most BMI_DATASZ_MAX
+         *    A_UINT8       CompressedData[length]
+         * Response format: none
+         * Note: Not supported on all versions of ROM firmware.
+         */
+
+#endif /* __BMI_MSG_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/btcoexGpio.h b/drivers/net/wireless/ath6kl/include/btcoexGpio.h
new file mode 100644
index 000000000000..8ed52a34fb1e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/btcoexGpio.h
@@ -0,0 +1,68 @@
+#ifndef BTCOEX_GPIO_H_
+#define BTCOEX_GPIO_H_
+
+
+
+#ifdef FPGA
+#define GPIO_A      (15)
+#define GPIO_B      (16)
+#define GPIO_C      (17)
+#define GPIO_D      (18)
+#define GPIO_E      (19)
+#define GPIO_F      (21)
+#define GPIO_G      (21)
+#else
+#define GPIO_A      (0)
+#define GPIO_B      (5)
+#define GPIO_C      (6)
+#define GPIO_D      (7)
+#define GPIO_E      (7)
+#define GPIO_F      (7)
+#define GPIO_G      (7)
+#endif
+
+
+
+
+
+#define GPIO_DEBUG_WORD_1                                 (1<<GPIO_A)
+#define GPIO_DEBUG_WORD_2                   (1<<GPIO_B)
+#define GPIO_DEBUG_WORD_3                  ((1<<GPIO_B) | (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_4     (1<<GPIO_C)
+#define GPIO_DEBUG_WORD_5    ((1<<GPIO_C) |               (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_6    ((1<<GPIO_C) | (1<<GPIO_B))
+#define GPIO_DEBUG_WORD_7    ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
+
+#define GPIO_DEBUG_WORD_8     (1<<GPIO_D)
+#define GPIO_DEBUG_WORD_9    ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_10   ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_11   ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_12   ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_13   ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_14   ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_15   ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
+
+#define GPIO_DEBUG_WORD_16   (1<<GPIO_E)
+#define GPIO_DEBUG_WORD_17    ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_18   ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_19   ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_20   ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_21   ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_22   ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_23   ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
+
+
+
+extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask);
+extern void btcoexDbgPulse(A_UINT32 pin);
+
+#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)  (btcoexDbgPulseWord(gpioPinMask))
+#define BTCOEX_DBG_PULSE(pin)               (btcoexDbgPulse(pin))
+#else
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
+#define BTCOEX_DBG_PULSE(pin)
+
+#endif
+#endif
+
diff --git a/drivers/net/wireless/ath6kl/include/cnxmgmt.h b/drivers/net/wireless/ath6kl/include/cnxmgmt.h
new file mode 100644
index 000000000000..0c956fb6b9d5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/cnxmgmt.h
@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------
+// <copyright file="cnxmgmt.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _CNXMGMT_H_
+#define _CNXMGMT_H_
+
+typedef enum {
+    CM_CONNECT_WITHOUT_SCAN             = 0x0001,
+    CM_CONNECT_ASSOC_POLICY_USER        = 0x0002,
+    CM_CONNECT_SEND_REASSOC             = 0x0004,
+    CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
+    CM_CONNECT_DO_WPA_OFFLOAD           = 0x0010,
+    CM_CONNECT_DO_NOT_DEAUTH            = 0x0020,
+} CM_CONNECT_TYPE;
+
+#endif  /* _CNXMGMT_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/common_drv.h b/drivers/net/wireless/ath6kl/include/common_drv.h
new file mode 100644
index 000000000000..286490188605
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/common_drv.h
@@ -0,0 +1,90 @@
+//------------------------------------------------------------------------------
+// <copyright file="common_drv.h" company="Atheros">
+//    Copyright (c) 2010 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef COMMON_DRV_H_
+#define COMMON_DRV_H_
+
+#include "hif.h"
+#include "htc_packet.h"
+#include "htc_api.h"
+
+/* structure that is the state information for the default credit distribution callback
+ * drivers should instantiate (zero-init as well) this structure in their driver instance
+ * and pass it as a context to the HTC credit distribution functions */
+typedef struct _COMMON_CREDIT_STATE_INFO {
+    int TotalAvailableCredits;      /* total credits in the system at startup */
+    int CurrentFreeCredits;         /* credits available in the pool that have not been
+                                       given out to endpoints */
+    HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist;  /* pointer to the lowest priority endpoint dist struct */
+} COMMON_CREDIT_STATE_INFO;
+
+typedef struct {
+    A_INT32 (*setupTransport)(void *ar);
+    void (*cleanupTransport)(void *ar);
+} HCI_TRANSPORT_CALLBACKS;
+
+typedef struct {
+   void *netDevice;
+   void *hifDevice;
+   void *htcHandle;
+} HCI_TRANSPORT_MISC_HANDLES;
+
+/* HTC TX packet tagging definitions */
+#define AR6K_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
+#define AR6K_DATA_PKT_TAG       (AR6K_CONTROL_PKT_TAG + 1)
+
+#define AR6002_VERSION_REV1     0x20000086
+#define AR6002_VERSION_REV2     0x20000188
+#define AR6003_VERSION_REV1     0x300002ba
+#define AR6003_VERSION_REV2     0x30000384
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* OS-independent APIs */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,  A_UCHAR *data, A_UINT32 length);
+
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset);
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    MboxIsrYieldValue,
+                               A_UINT8     HtcControlBuffers);
+
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    TargetVersion);
+
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+                                     A_UINT32    TargetType,
+                                     A_UINT32    Flags);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*COMMON_DRV_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/dbglog.h b/drivers/net/wireless/ath6kl/include/dbglog.h
new file mode 100644
index 000000000000..ae05eb66c21a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_H_
+#define _DBGLOG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DBGLOG_TIMESTAMP_OFFSET          0
+#define DBGLOG_TIMESTAMP_MASK            0x0000FFFF /* Bit 0-15. Contains bit
+                                                       8-23 of the LF0 timer */
+#define DBGLOG_DBGID_OFFSET              16
+#define DBGLOG_DBGID_MASK                0x03FF0000 /* Bit 16-25 */
+#define DBGLOG_DBGID_NUM_MAX             256 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULEID_OFFSET           26
+#define DBGLOG_MODULEID_MASK             0x3C000000 /* Bit 26-29 */
+#define DBGLOG_MODULEID_NUM_MAX          16 /* Upper limit is width of mask */
+
+/*
+ * Please ensure that the definition of any new module intrduced is captured
+ * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The 
+ * structure is required for the parser to correctly pick up the values for
+ * different modules.
+ */
+#define DBGLOG_MODULEID_START
+#define DBGLOG_MODULEID_INF                   0
+#define DBGLOG_MODULEID_WMI                   1
+#define DBGLOG_MODULEID_MISC                  2
+#define DBGLOG_MODULEID_PM                    3
+#define DBGLOG_MODULEID_TXRX_MGMTBUF          4
+#define DBGLOG_MODULEID_TXRX_TXBUF            5
+#define DBGLOG_MODULEID_TXRX_RXBUF            6
+#define DBGLOG_MODULEID_WOW                   7
+#define DBGLOG_MODULEID_WHAL                  8
+#define DBGLOG_MODULEID_DC                    9
+#define DBGLOG_MODULEID_CO                    10
+#define DBGLOG_MODULEID_RO                    11
+#define DBGLOG_MODULEID_CM                    12
+#define DBGLOG_MODULEID_MGMT                  13
+#define DBGLOG_MODULEID_TMR                   14
+#define DBGLOG_MODULEID_BTCOEX                15
+#define DBGLOG_MODULEID_END
+
+#define DBGLOG_NUM_ARGS_OFFSET             30
+#define DBGLOG_NUM_ARGS_MASK               0xC0000000 /* Bit 30-31 */
+#define DBGLOG_NUM_ARGS_MAX                2 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULE_LOG_ENABLE_OFFSET    0
+#define DBGLOG_MODULE_LOG_ENABLE_MASK      0x0000FFFF
+
+#define DBGLOG_REPORTING_ENABLED_OFFSET    16
+#define DBGLOG_REPORTING_ENABLED_MASK      0x00010000
+
+#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
+#define DBGLOG_TIMESTAMP_RESOLUTION_MASK   0x000E0000
+
+#define DBGLOG_REPORT_SIZE_OFFSET          20
+#define DBGLOG_REPORT_SIZE_MASK            0x3FF00000
+
+#define DBGLOG_LOG_BUFFER_SIZE             1500
+#define DBGLOG_DBGID_DEFINITION_LEN_MAX    90
+
+struct dbglog_buf_s {
+    struct dbglog_buf_s *next;
+    A_UINT8             *buffer;
+    A_UINT32             bufsize;
+    A_UINT32             length;
+    A_UINT32             count;
+    A_UINT32             free;
+};
+
+struct dbglog_hdr_s {
+    struct dbglog_buf_s *dbuf;
+    A_UINT32             dropped;
+};
+
+struct dbglog_config_s {
+    A_UINT32                    cfgvalid; /* Mask with valid config bits */
+    union {
+        /* TODO: Take care of endianness */
+        struct {
+            A_UINT32            mmask:16; /* Mask of modules with logging on */
+            A_UINT32            rep:1; /* Reporting enabled or not */
+            A_UINT32            tsr:3; /* Time stamp resolution. Def: 1 ms */
+            A_UINT32            size:10; /* Report size in number of messages */
+            A_UINT32            reserved:2;
+        } dbglog_config;
+
+        A_UINT32                value;
+    } u;
+};
+
+#define cfgmmask                   u.dbglog_config.mmask
+#define cfgrep                     u.dbglog_config.rep
+#define cfgtsr                     u.dbglog_config.tsr
+#define cfgsize                    u.dbglog_config.size
+#define cfgvalue                   u.value
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dbglog_api.h b/drivers/net/wireless/ath6kl/include/dbglog_api.h
new file mode 100644
index 000000000000..4710b4c140fc
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog_api.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains host side debug primitives.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DBGLOG_API_H_
+#define _DBGLOG_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dbglog.h"
+
+#define DBGLOG_HOST_LOG_BUFFER_SIZE            DBGLOG_LOG_BUFFER_SIZE
+
+#define DBGLOG_GET_DBGID(arg) \
+    ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
+
+#define DBGLOG_GET_MODULEID(arg) \
+    ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
+
+#define DBGLOG_GET_NUMARGS(arg) \
+    ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
+
+#define DBGLOG_GET_TIMESTAMP(arg) \
+    ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dbglog_id.h b/drivers/net/wireless/ath6kl/include/dbglog_id.h
new file mode 100644
index 000000000000..b5cd521a260f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog_id.h
@@ -0,0 +1,530 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_id.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_ID_H_
+#define _DBGLOG_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 
+ * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
+ * Please ensure that the definition of any new debugid introduced is captured
+ * between the <MODULE>_DBGID_DEFINITION_START and 
+ * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the 
+ * parser to correctly pick up the values for different debug identifiers.
+ */
+
+/* INF debug identifier definitions */
+#define INF_DBGID_DEFINITION_START
+#define INF_ASSERTION_FAILED                          1
+#define INF_TARGET_ID                                 2
+#define INF_DBGID_DEFINITION_END
+
+/* WMI debug identifier definitions */
+#define WMI_DBGID_DEFINITION_START
+#define WMI_CMD_RX_XTND_PKT_TOO_SHORT                 1
+#define WMI_EXTENDED_CMD_NOT_HANDLED                  2
+#define WMI_CMD_RX_PKT_TOO_SHORT                      3
+#define WMI_CALLING_WMI_EXTENSION_FN                  4
+#define WMI_CMD_NOT_HANDLED                           5
+#define WMI_IN_SYNC                                   6
+#define WMI_TARGET_WMI_SYNC_CMD                       7
+#define WMI_SET_SNR_THRESHOLD_PARAMS                  8
+#define WMI_SET_RSSI_THRESHOLD_PARAMS                 9
+#define WMI_SET_LQ_TRESHOLD_PARAMS                   10
+#define WMI_TARGET_CREATE_PSTREAM_CMD                11
+#define WMI_WI_DTM_INUSE                             12
+#define WMI_TARGET_DELETE_PSTREAM_CMD                13
+#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD       14
+#define WMI_TARGET_GET_BIT_RATE_CMD                  15
+#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS       16
+#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD        17
+#define WMI_TARGET_GET_TX_PWR_CMD                    18
+#define WMI_FREE_EVBUF_WMIBUF                        19
+#define WMI_FREE_EVBUF_DATABUF                       20
+#define WMI_FREE_EVBUF_BADFLAG                       21
+#define WMI_HTC_RX_ERROR_DATA_PACKET                 22
+#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX             23
+#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT      24
+#define WMI_SENDING_READY_EVENT                      25
+#define WMI_SETPOWER_MDOE_TO_MAXPERF                 26
+#define WMI_SETPOWER_MDOE_TO_REC                     27
+#define WMI_BSSINFO_EVENT_FROM                       28
+#define WMI_TARGET_GET_STATS_CMD                     29
+#define WMI_SENDING_SCAN_COMPLETE_EVENT              30
+#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT        31
+#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT       32
+#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT     33
+#define WMI_SENDING_ERROR_REPORT_EVENT               34
+#define WMI_SENDING_CAC_EVENT                        35
+#define WMI_TARGET_GET_ROAM_TABLE_CMD                36
+#define WMI_TARGET_GET_ROAM_DATA_CMD                 37
+#define WMI_SENDING_GPIO_INTR_EVENT                  38
+#define WMI_SENDING_GPIO_ACK_EVENT                   39
+#define WMI_SENDING_GPIO_DATA_EVENT                  40
+#define WMI_CMD_RX                                   41
+#define WMI_CMD_RX_XTND                              42
+#define WMI_EVENT_SEND                               43
+#define WMI_EVENT_SEND_XTND                          44
+#define WMI_CMD_PARAMS_DUMP_START                    45
+#define WMI_CMD_PARAMS_DUMP_END                      46
+#define WMI_CMD_PARAMS                               47
+#define WMI_DBGID_DEFINITION_END
+
+/* MISC debug identifier definitions */
+#define MISC_DBGID_DEFINITION_START
+#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR     1
+#define MISC_DBGID_DEFINITION_END
+    
+/* TXRX debug identifier definitions */
+#define TXRX_TXBUF_DBGID_DEFINITION_START
+#define TXRX_TXBUF_ALLOCATE_BUF                      1
+#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX                 2
+#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ                  3
+#define TXRX_TXBUF_TXQ_DEPTH                         4   
+#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ                 5
+#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ         6
+#define TXRX_TXBUF_INITIALIZE_TIMER                  7
+#define TXRX_TXBUF_ARM_TIMER                         8
+#define TXRX_TXBUF_DISARM_TIMER                      9
+#define TXRX_TXBUF_UNINITIALIZE_TIMER                10
+#define TXRX_TXBUF_DBGID_DEFINITION_END
+ 
+#define TXRX_RXBUF_DBGID_DEFINITION_START    
+#define TXRX_RXBUF_ALLOCATE_BUF                      1
+#define TXRX_RXBUF_QUEUE_TO_HOST                     2
+#define TXRX_RXBUF_QUEUE_TO_WLAN                     3
+#define TXRX_RXBUF_ZERO_LEN_BUF                      4
+#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN  5
+#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF        6
+#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN         7
+#define TXRX_RXBUF_SEND_TO_RECV_MGMT                 8
+#define TXRX_RXBUF_SEND_TO_IEEE_LAYER                9
+#define TXRX_RXBUF_REQUEUE_ERROR                     10
+#define TXRX_RXBUF_DBGID_DEFINITION_END
+
+#define TXRX_MGMTBUF_DBGID_DEFINITION_START 
+#define TXRX_MGMTBUF_ALLOCATE_BUF                    1
+#define TXRX_MGMTBUF_ALLOCATE_SM_BUF                 2    
+#define TXRX_MGMTBUF_ALLOCATE_RMBUF                  3
+#define TXRX_MGMTBUF_GET_BUF                         4
+#define TXRX_MGMTBUF_GET_SM_BUF                      5
+#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ                6
+#define TXRX_MGMTBUF_REAPED_BUF                      7
+#define TXRX_MGMTBUF_REAPED_SM_BUF                   8
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN              9
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN          10
+#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ           11
+#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ           12
+#define TXRX_MGMTBUF_PAUSE_DATA_TXQ                  13
+#define TXRX_MGMTBUF_RESUME_DATA_TXQ                 14
+#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT       15
+#define TXRX_MGMTBUF_DRAINQ                          16
+#define TXRX_MGMTBUF_INDICATE_Q_DRAINED              17
+#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ             18
+#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ             19
+#define TXRX_MGMTBUF_PAUSE_HW_TXQ                    20
+#define TXRX_MGMTBUF_RESUME_HW_TXQ                   21
+#define TXRX_MGMTBUF_TEAR_DOWN_BA					 22
+#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ				 23
+#define TXRX_MGMTBUF_PROCESS_DELBA					 24
+#define TXRX_MGMTBUF_PERFORM_BA                      25
+#define TXRX_MGMTBUF_DBGID_DEFINITION_END
+
+/* PM (Power Module) debug identifier definitions */
+#define PM_DBGID_DEFINITION_START
+#define PM_INIT                                      1
+#define PM_ENABLE                                    2
+#define PM_SET_STATE                                 3
+#define PM_SET_POWERMODE                             4
+#define PM_CONN_NOTIFY                               5
+#define PM_REF_COUNT_NEGATIVE                        6
+#define PM_INFRA_STA_APSD_ENABLE                     7
+#define PM_INFRA_STA_UPDATE_APSD_STATE               8
+#define PM_CHAN_OP_REQ                               9
+#define PM_SET_MY_BEACON_POLICY                      10
+#define PM_SET_ALL_BEACON_POLICY                     11
+#define PM_INFRA_STA_SET_PM_PARAMS1                  12
+#define PM_INFRA_STA_SET_PM_PARAMS2                  13
+#define PM_ADHOC_SET_PM_CAPS_FAIL                    14
+#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID              15
+#define PM_ADHOC_SET_PM_PARAMS                       16
+#define PM_ADHOC_STATE1                              18
+#define PM_ADHOC_STATE2                              19
+#define PM_ADHOC_CONN_MAP                            20 
+#define PM_FAKE_SLEEP                                21
+#define PM_AP_STATE1                                 22
+#define PM_AP_SET_PM_PARAMS                          23
+#define PM_DBGID_DEFINITION_END
+
+/* Wake on Wireless debug identifier definitions */
+#define WOW_DBGID_DEFINITION_START
+#define WOW_INIT                                        1
+#define WOW_GET_CONFIG_DSET                             2   
+#define WOW_NO_CONFIG_DSET                              3
+#define WOW_INVALID_CONFIG_DSET                         4
+#define WOW_USE_DEFAULT_CONFIG                          5
+#define WOW_SETUP_GPIO                                  6
+#define WOW_INIT_DONE                                   7
+#define WOW_SET_GPIO_PIN                                8
+#define WOW_CLEAR_GPIO_PIN                              9
+#define WOW_SET_WOW_MODE_CMD                            10
+#define WOW_SET_HOST_MODE_CMD                           11  
+#define WOW_ADD_WOW_PATTERN_CMD                         12    
+#define WOW_NEW_WOW_PATTERN_AT_INDEX                    13    
+#define WOW_DEL_WOW_PATTERN_CMD                         14    
+#define WOW_LIST_CONTAINS_PATTERNS                      15    
+#define WOW_GET_WOW_LIST_CMD                            16 
+#define WOW_INVALID_FILTER_ID                           17
+#define WOW_INVALID_FILTER_LISTID                       18
+#define WOW_NO_VALID_FILTER_AT_ID                       19
+#define WOW_NO_VALID_LIST_AT_ID                         20
+#define WOW_NUM_PATTERNS_EXCEEDED                       21
+#define WOW_NUM_LISTS_EXCEEDED                          22
+#define WOW_GET_WOW_STATS                               23
+#define WOW_CLEAR_WOW_STATS                             24
+#define WOW_WAKEUP_HOST                                 25
+#define WOW_EVENT_WAKEUP_HOST                           26
+#define WOW_EVENT_DISCARD                               27
+#define WOW_PATTERN_MATCH                               28
+#define WOW_PATTERN_NOT_MATCH                           29
+#define WOW_PATTERN_NOT_MATCH_OFFSET                    30
+#define WOW_DISABLED_HOST_ASLEEP                        31
+#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS             32
+#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND          33
+#define WOW_DBGID_DEFINITION_END
+
+/* WHAL debug identifier definitions */
+#define WHAL_DBGID_DEFINITION_START
+#define WHAL_ERROR_ANI_CONTROL                      1
+#define WHAL_ERROR_CHIP_TEST1                       2
+#define WHAL_ERROR_CHIP_TEST2                       3
+#define WHAL_ERROR_EEPROM_CHECKSUM                  4
+#define WHAL_ERROR_EEPROM_MACADDR                   5
+#define WHAL_ERROR_INTERRUPT_HIU                    6
+#define WHAL_ERROR_KEYCACHE_RESET                   7
+#define WHAL_ERROR_KEYCACHE_SET                     8 
+#define WHAL_ERROR_KEYCACHE_TYPE                    9
+#define WHAL_ERROR_KEYCACHE_TKIPENTRY              10
+#define WHAL_ERROR_KEYCACHE_WEPLENGTH              11
+#define WHAL_ERROR_PHY_INVALID_CHANNEL             12
+#define WHAL_ERROR_POWER_AWAKE                     13
+#define WHAL_ERROR_POWER_SET                       14
+#define WHAL_ERROR_RECV_STOPDMA                    15
+#define WHAL_ERROR_RECV_STOPPCU                    16
+#define WHAL_ERROR_RESET_CHANNF1                   17
+#define WHAL_ERROR_RESET_CHANNF2                   18
+#define WHAL_ERROR_RESET_PM                        19
+#define WHAL_ERROR_RESET_OFFSETCAL                 20
+#define WHAL_ERROR_RESET_RFGRANT                   21
+#define WHAL_ERROR_RESET_RXFRAME                   22
+#define WHAL_ERROR_RESET_STOPDMA                   23
+#define WHAL_ERROR_RESET_RECOVER                   24
+#define WHAL_ERROR_XMIT_COMPUTE                    25
+#define WHAL_ERROR_XMIT_NOQUEUE                    26
+#define WHAL_ERROR_XMIT_ACTIVEQUEUE                27
+#define WHAL_ERROR_XMIT_BADTYPE                    28
+#define WHAL_ERROR_XMIT_STOPDMA                    29
+#define WHAL_ERROR_INTERRUPT_BB_PANIC              30 
+#define WHAL_ERROR_RESET_TXIQCAL                   31 
+#define WHAL_DBGID_DEFINITION_END
+
+/* DC debug identifier definitions */
+#define DC_DBGID_DEFINITION_START
+#define DC_SCAN_CHAN_START                          1
+#define DC_SCAN_CHAN_FINISH                         2
+#define DC_BEACON_RECEIVE7                          3
+#define DC_SSID_PROBE_CB                            4
+#define DC_SEND_NEXT_SSID_PROBE                     5
+#define DC_START_SEARCH                             6
+#define DC_CANCEL_SEARCH_CB                         7
+#define DC_STOP_SEARCH                              8
+#define DC_END_SEARCH                               9
+#define DC_MIN_CHDWELL_TIMEOUT                     10
+#define DC_START_SEARCH_CANCELED                   11
+#define DC_SET_POWER_MODE                          12
+#define DC_INIT                                    13
+#define DC_SEARCH_OPPORTUNITY                      14
+#define DC_RECEIVED_ANY_BEACON                     15
+#define DC_RECEIVED_MY_BEACON                      16
+#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA       17
+#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT        18
+#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED           19
+#define DC_SET_BEACON_UPDATE                       20
+#define DC_BEACON_UPDATE_COMPLETE                  21
+#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB        22
+#define DC_BSSINFO_EVENT_DROPPED                   23
+#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT          24 
+#define DC_DBGID_DEFINITION_END
+
+/* CO debug identifier definitions */
+#define CO_DBGID_DEFINITION_START
+#define CO_INIT                                     1
+#define CO_ACQUIRE_LOCK                             2
+#define CO_START_OP1                                3
+#define CO_START_OP2                                4
+#define CO_DRAIN_TX_COMPLETE_CB                     5
+#define CO_CHANGE_CHANNEL_CB                        6
+#define CO_RETURN_TO_HOME_CHANNEL                   7
+#define CO_FINISH_OP_TIMEOUT                        8
+#define CO_OP_END                                   9
+#define CO_CANCEL_OP                               10
+#define CO_CHANGE_CHANNEL                          11
+#define CO_RELEASE_LOCK                            12
+#define CO_CHANGE_STATE                            13
+#define CO_DBGID_DEFINITION_END
+
+/* RO debug identifier definitions */
+#define RO_DBGID_DEFINITION_START
+#define RO_REFRESH_ROAM_TABLE                       1
+#define RO_UPDATE_ROAM_CANDIDATE                    2
+#define RO_UPDATE_ROAM_CANDIDATE_CB                 3
+#define RO_UPDATE_ROAM_CANDIDATE_FINISH             4
+#define RO_REFRESH_ROAM_TABLE_DONE                  5
+#define RO_PERIODIC_SEARCH_CB                       6
+#define RO_PERIODIC_SEARCH_TIMEOUT                  7
+#define RO_INIT                                     8
+#define RO_BMISS_STATE1                             9
+#define RO_BMISS_STATE2                            10
+#define RO_SET_PERIODIC_SEARCH_ENABLE              11
+#define RO_SET_PERIODIC_SEARCH_DISABLE             12
+#define RO_ENABLE_SQ_THRESHOLD                     13
+#define RO_DISABLE_SQ_THRESHOLD                    14
+#define RO_ADD_BSS_TO_ROAM_TABLE                   15
+#define RO_SET_PERIODIC_SEARCH_MODE                16
+#define RO_CONFIGURE_SQ_THRESHOLD1                 17
+#define RO_CONFIGURE_SQ_THRESHOLD2                 18
+#define RO_CONFIGURE_SQ_PARAMS                     19
+#define RO_LOW_SIGNAL_QUALITY_EVENT                20
+#define RO_HIGH_SIGNAL_QUALITY_EVENT               21
+#define RO_REMOVE_BSS_FROM_ROAM_TABLE              22
+#define RO_UPDATE_CONNECTION_STATE_METRIC          23
+#define RO_DBGID_DEFINITION_END
+
+/* CM debug identifier definitions */
+#define CM_DBGID_DEFINITION_START
+#define CM_INITIATE_HANDOFF                         1
+#define CM_INITIATE_HANDOFF_CB                      2
+#define CM_CONNECT_EVENT                            3
+#define CM_DISCONNECT_EVENT                         4
+#define CM_INIT                                     5
+#define CM_HANDOFF_SOURCE                           6
+#define CM_SET_HANDOFF_TRIGGERS                     7
+#define CM_CONNECT_REQUEST                          8
+#define CM_CONNECT_REQUEST_CB                       9
+#define CM_CONTINUE_SCAN_CB                         10 
+#define CM_DBGID_DEFINITION_END
+
+
+/* mgmt debug identifier definitions */
+#define MGMT_DBGID_DEFINITION_START
+#define KEYMGMT_CONNECTION_INIT                     1
+#define KEYMGMT_CONNECTION_COMPLETE                 2
+#define KEYMGMT_CONNECTION_CLOSE                    3
+#define KEYMGMT_ADD_KEY                             4
+#define MLME_NEW_STATE                              5
+#define MLME_CONN_INIT                              6
+#define MLME_CONN_COMPLETE                          7
+#define MLME_CONN_CLOSE                             8 
+#define MGMT_DBGID_DEFINITION_END
+
+/* TMR debug identifier definitions */
+#define TMR_DBGID_DEFINITION_START
+#define TMR_HANG_DETECTED                           1
+#define TMR_WDT_TRIGGERED                           2
+#define TMR_WDT_RESET                               3
+#define TMR_HANDLER_ENTRY                           4
+#define TMR_HANDLER_EXIT                            5
+#define TMR_SAVED_START                             6
+#define TMR_SAVED_END                               7
+#define TMR_DBGID_DEFINITION_END
+
+/* BTCOEX debug identifier definitions */
+#define BTCOEX_DBGID_DEFINITION_START
+#define BTCOEX_STATUS_CMD                           1
+#define BTCOEX_PARAMS_CMD                           2
+#define BTCOEX_ANT_CONFIG                           3
+#define BTCOEX_COLOCATED_BT_DEVICE                  4
+#define BTCOEX_CLOSE_RANGE_SCO_ON                   5
+#define BTCOEX_CLOSE_RANGE_SCO_OFF                  6
+#define BTCOEX_CLOSE_RANGE_A2DP_ON                  7
+#define BTCOEX_CLOSE_RANGE_A2DP_OFF                 8
+#define BTCOEX_A2DP_PROTECT_ON                      9
+#define BTCOEX_A2DP_PROTECT_OFF                     10
+#define BTCOEX_SCO_PROTECT_ON                       11
+#define BTCOEX_SCO_PROTECT_OFF                      12
+#define BTCOEX_CLOSE_RANGE_DETECTOR_START           13
+#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP            14
+#define BTCOEX_CLOSE_RANGE_TOGGLE                   15
+#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT        16
+#define BTCOEX_CLOSE_RANGE_RSSI_THRESH              17
+#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH          18
+#define BTCOEX_PTA_PRI_INTR_HANDLER  		        19
+#define BTCOEX_PSPOLL_QUEUED						20
+#define BTCOEX_PSPOLL_COMPLETE						21
+#define BTCOEX_DBG_PM_AWAKE							22
+#define BTCOEX_DBG_PM_SLEEP							23
+#define BTCOEX_DBG_SCO_COEX_ON						24
+#define BTCOEX_SCO_DATARECEIVE						25
+#define BTCOEX_INTR_INIT							26
+#define BTCOEX_PTA_PRI_DIFF							27
+#define BTCOEX_TIM_NOTIFICATION						28
+#define BTCOEX_SCO_WAKEUP_ON_DATA					29
+#define BTCOEX_SCO_SLEEP							30
+#define BTCOEX_SET_WEIGHTS							31
+#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL			32
+#define BTCOEX_SCO_MEASURE_TIME_DIFF				33
+#define BTCOEX_SET_EOL_VAL							34
+#define BTCOEX_OPT_DETECT_HANDLER					35
+#define BTCOEX_SCO_TOGGLE_STATE						36
+#define BTCOEX_SCO_STOMP							37
+#define BTCOEX_NULL_COMP_CALLBACK					38
+#define BTCOEX_RX_INCOMING							39
+#define BTCOEX_RX_INCOMING_CTL						40
+#define BTCOEX_RX_INCOMING_MGMT						41
+#define BTCOEX_RX_INCOMING_DATA						42
+#define BTCOEX_RTS_RECEPTION						43
+#define BTCOEX_FRAME_PRI_LOW_RATE_THRES				44
+#define BTCOEX_PM_FAKE_SLEEP						45
+#define BTCOEX_ACL_COEX_STATUS						46
+#define BTCOEX_ACL_COEX_DETECTECTION				47
+#define BTCOEX_A2DP_COEX_STATUS						48
+#define BTCOEX_SCO_STATUS							49
+#define BTCOEX_WAKEUP_ON_DATA						50
+#define BTCOEX_DATARECEIVE							51
+#define BTCOEX_GET_MAX_AGGR_SIZE					53
+#define BTCOEX_MAX_AGGR_AVAIL_TIME					54
+#define BTCOEX_DBG_WBTIMER_INTR						55
+#define BTCOEX_DBG_SCO_SYNC                         57
+#define BTCOEX_UPLINK_QUEUED_RATE  					59
+#define BTCOEX_DBG_UPLINK_ENABLE_EOL				60
+#define BTCOEX_UPLINK_FRAME_DURATION				61
+#define BTCOEX_UPLINK_SET_EOL						62
+#define BTCOEX_DBG_EOL_EXPIRED						63
+#define BTCOEX_DBG_DATA_COMPLETE					64
+#define BTCOEX_UPLINK_QUEUED_TIMESTAMP				65
+#define BTCOEX_DBG_DATA_COMPLETE_TIME				66
+#define BTCOEX_DBG_TX_COMP_TXQ						67
+#define BTCOEX_DBG_SCO_FL_EDGE						68
+#define BTCOEX_DBG_UPLINK_SEQ_NUM					69
+#define BTCOEX_UPLINK_AGGR_SEQ						70
+#define BTCOEX_DBG_TX_COMP_SEQ_NO					71
+#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE				72
+#define BTCOEX_DBG_ACL_TRAFFIC                      73
+#define BTCOEX_CURR_AGGR_PROP						74
+#define BTCOEX_CREAT_AGGR							75
+#define BTCOEX_PSPOLL_PROCESS						76
+#define BTCOEX_RETURN_FROM_MAC						77
+#define BTCOEX_FREED_REQUEUED_CNT					78
+#define BTCOEX_DBG_TOGGLE_LOW_RATES					79
+#define BTCOEX_MAC_GOES_TO_SLEEP    				80
+#define BTCOEX_DBG_A2DP_NO_SYNC                     81
+#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO			82
+#define BTCOEX_RETURN_FROM_MAC_AC					83
+#define BTCOEX_CREAT_AGGR_AC						84
+#define BTCOEX_IS_PRE_UPDATE						86
+#define BTCOEX_ENQUEUED_BIT_MAP						87
+#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS			88
+#define BTCOEX_UPLINK_DESC							89
+#define BTCOEX_DBG_TXQ_DETAILS						90
+#define BTCOEX_DBG_RECV_ACK							94
+#define BTCOEX_DBG_ADDBA_INDICATION                 95
+#define BTCOEX_TX_COMPLETE_EOL_FAILED				96
+#define BTCOEX_DBG_A2DP_USAGE_COMPLETE  			97
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER		98
+#define BTCOEX_DBG_A2DP_SYNC_INTR                   99
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION	   100
+#define BTCOEX_FORM_AGGR_CURR_AGGR				   101
+#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT           102
+#define BTCOEX_DBG_BT_TRAFFIC   				   103
+#define BTCOEX_DBG_STOMP_BT_TRAFFIC 			   104
+#define BTCOEX_RECV_NULL                           105
+#define BTCOEX_DBG_A2DP_MASTER_BT_END			   106
+#define BTCOEX_DBG_A2DP_BT_START				   107
+#define BTCOEX_DBG_A2DP_SLAVE_BT_END			   108
+#define BTCOEX_DBG_A2DP_STOMP_BT				   109
+#define BTCOEX_DBG_GO_TO_SLEEP					   110
+#define BTCOEX_DBG_A2DP_PKT						   111
+#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV		   112
+#define BTCOEX_DBG_A2DP_NULL					   113
+#define BTCOEX_DBG_UPLINK_DATA					   114
+#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL		   115
+#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT			   116
+#define BTCOEX_DBG_TXQ_STATE					   117
+#define BTCOEX_DBG_ALLOW_SCAN					   118
+#define BTCOEX_DBG_SCAN_REQUEST					   119
+#define BTCOEX_A2DP_SLEEP						   127
+#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT			   128
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE		   129
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 	   130
+#define BTCOEX_DATARECEIVE_AGGR					   131
+#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING	   132
+#define BTCOEX_DBG_DATARESP_TIMEOUT				   133
+#define BTCOEX_BDG_BMISS						   134
+#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM			   135
+#define BTCOEX_DBG_SECOND_BMISS					   136
+#define BTCOEX_DBG_SET_WLAN_STATE				   138
+#define BTCOEX_BDG_FIRST_BMISS					   139
+#define BTCOEX_DBG_A2DP_CHAN_OP					   140
+#define BTCOEX_DBG_A2DP_INTR					   141
+#define BTCOEX_DBG_BT_INQUIRY					   142
+#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH		   143
+#define BTCOEX_DBG_POST_INQUIRY_FINISH			   144
+#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER	   145
+#define BTCOEX_DBG_NULL_FRAME_SLEEP				   146
+#define BTCOEX_DBG_NULL_FRAME_AWAKE				   147
+#define BTCOEX_DBG_SET_AGGR_SIZE				   152
+#define BTCOEX_DBG_TEAR_BA_TIMEOUT				   153
+#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO			   154
+#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI			   155
+#define BTCOEX_DBG_COLOCATED_BT_DEV				   156
+#define BTCOEX_DBG_FE_ANT_TYPE				       157
+#define BTCOEX_DBG_BT_INQUIRY_CMD				   158
+#define BTCOEX_DBG_SCO_CONFIG					   159
+#define BTCOEX_DBG_SCO_PSPOLL_CONFIG			   160
+#define BTCOEX_DBG_SCO_OPTMODE_CONFIG		       161
+#define BTCOEX_DBG_A2DP_CONFIG				       162
+#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG		       163
+#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG		       164
+#define BTCOEX_DBG_ACLCOEX_CONFIG			       165
+#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG		   166
+#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG	       167
+#define BTCOEX_DBG_DEBUG_CMD					   168
+#define BTCOEX_DBG_SET_BT_OPERATING_STATUS		   169
+#define BTCOEX_DBG_GET_CONFIG					   170
+#define BTCOEX_DBG_GET_STATS					   171
+#define BTCOEX_DBG_BT_OPERATING_STATUS			   172
+#define BTCOEX_DBG_PERFORM_RECONNECT               173
+#define BTCOEX_DBG_ACL_WLAN_MED                    175
+#define BTCOEX_DBG_ACL_BT_MED                      176
+#define BTCOEX_DBG_WLAN_CONNECT                    177
+#define BTCOEX_DBG_A2DP_DUAL_START                 178
+#define BTCOEX_DBG_PMAWAKE_NOTIFY                  179
+#define BTCOEX_DBG_BEACON_SCAN_ENABLE              180
+#define BTCOEX_DBG_BEACON_SCAN_DISABLE             181
+#define BTCOEX_DBG_RX_NOTIFY                       182
+#define BTCOEX_DBGID_DEFINITION_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_ID_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/discovery.h b/drivers/net/wireless/ath6kl/include/discovery.h
new file mode 100644
index 000000000000..53791df70ab9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/discovery.h
@@ -0,0 +1,71 @@
+//------------------------------------------------------------------------------
+// <copyright file="discovery.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DISCOVERY_H_
+#define _DISCOVERY_H_
+
+/*
+ * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
+ */
+typedef enum {
+    DEFAULT_SCPRI = 0x01,
+    POPULAR_SCPRI = 0x02,
+    SSIDS_SCPRI   = 0x04,
+    PROF_SCPRI    = 0x08,
+} DC_SCAN_PRIORITY;
+
+/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
+typedef enum {
+    SCAN_RESET                     = 0,
+    SCAN_ALL                       = (DEFAULT_SCPRI | POPULAR_SCPRI |  \
+                                      SSIDS_SCPRI | PROF_SCPRI),
+
+    SCAN_POPULAR                   = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
+    SCAN_SSIDS                     = (SSIDS_SCPRI | PROF_SCPRI),
+    SCAN_PROF_MASK                 = (PROF_SCPRI),
+    SCAN_MULTI_CHANNEL             = 0x000100,
+    SCAN_DETERMINISTIC             = 0x000200,
+    SCAN_PROFILE_MATCH_TERMINATED  = 0x000400,
+    SCAN_HOME_CHANNEL_SKIP         = 0x000800,
+    SCAN_CHANNEL_LIST_CONTINUE     = 0x001000,
+    SCAN_CURRENT_SSID_SKIP         = 0x002000,
+    SCAN_ACTIVE_PROBE_DISABLE      = 0x004000,
+    SCAN_CHANNEL_HINT_ONLY         = 0x008000,
+    SCAN_ACTIVE_CHANNELS_ONLY      = 0x010000,
+    SCAN_UNUSED1                   = 0x020000, /* unused */
+    SCAN_PERIODIC                  = 0x040000,
+    SCAN_FIXED_DURATION            = 0x080000,
+    SCAN_AP_ASSISTED               = 0x100000,
+} DC_SCAN_TYPE;
+
+typedef enum {
+    BSS_REPORTING_DEFAULT = 0x0,
+    EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
+} DC_BSS_REPORTING_POLICY;
+
+typedef enum {
+    DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
+    DC_PROFILE_MATCH_DONE = 0x02,
+    DC_IGNORE_AAC_BEACON = 0x04, 
+    DC_CSA_FOLLOW_BSS = 0x08,
+} DC_PROFILE_FILTER;
+
+#define DEFAULT_DC_PROFILE_FILTER   (DC_CSA_FOLLOW_BSS)
+
+#endif  /* _DISCOVERY_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dl_list.h b/drivers/net/wireless/ath6kl/include/dl_list.h
new file mode 100644
index 000000000000..f07b41d7638a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dl_list.h
@@ -0,0 +1,149 @@
+//------------------------------------------------------------------------------
+// <copyright file="dl_list.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Double-link list definitions (adapted from Atheros SDIO stack)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __DL_LIST_H___
+#define __DL_LIST_H___
+
+#include "a_osapi.h"
+
+#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
+            ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name)))
+
+/* list functions */
+/* pointers for the list */
+typedef struct _DL_LIST {
+    struct _DL_LIST *pPrev;
+    struct _DL_LIST *pNext;
+}DL_LIST, *PDL_LIST;
+/*
+ * DL_LIST_INIT , initialize doubly linked list
+*/
+#define DL_LIST_INIT(pList)\
+    {(pList)->pPrev = pList; (pList)->pNext = pList;}
+
+/* faster macro to init list and add a single item */    
+#define DL_LIST_INIT_AND_ADD(pList,pItem) \
+{   (pList)->pPrev = (pItem); \
+    (pList)->pNext = (pItem); \
+    (pItem)->pNext = (pList); \
+    (pItem)->pPrev = (pList); \
+}
+    
+#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
+#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
+#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
+/*
+ * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
+ * NOT: do not use this function if the items in the list are deleted inside the
+ * iteration loop
+*/
+#define ITERATE_OVER_LIST(pStart, pTemp) \
+    for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
+
+
+/* safe iterate macro that allows the item to be removed from the list
+ * the iteration continues to the next item in the list
+ */
+#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset)  \
+{                                                       \
+    PDL_LIST  pTemp;                                     \
+    pTemp = (pStart)->pNext;                            \
+    while (pTemp != (pStart)) {                         \
+        (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset);   \
+         pTemp = pTemp->pNext;                          \
+
+#define ITERATE_END }}
+
+/*
+ * DL_ListInsertTail - insert pAdd to the end of the list
+*/
+static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
+        /* insert at tail */
+    pAdd->pPrev = pList->pPrev;
+    pAdd->pNext = pList;
+    pList->pPrev->pNext = pAdd;
+    pList->pPrev = pAdd;
+    return pAdd;
+}
+
+/*
+ * DL_ListInsertHead - insert pAdd into the head of the list
+*/
+static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
+        /* insert at head */
+    pAdd->pPrev = pList;
+    pAdd->pNext = pList->pNext;
+    pList->pNext->pPrev = pAdd;
+    pList->pNext = pAdd;
+    return pAdd;
+}
+
+#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
+/*
+ * DL_ListRemove - remove pDel from list
+*/
+static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
+    pDel->pNext->pPrev = pDel->pPrev;
+    pDel->pPrev->pNext = pDel->pNext;
+        /* point back to itself just to be safe, incase remove is called again */
+    pDel->pNext = pDel;
+    pDel->pPrev = pDel;
+    return pDel;
+}
+
+/*
+ * DL_ListRemoveItemFromHead - get a list item from the head
+*/
+static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
+    PDL_LIST pItem = NULL;
+    if (pList->pNext != pList) {
+        pItem = pList->pNext;
+            /* remove the first item from head */
+        DL_ListRemove(pItem);
+    }
+    return pItem;
+}
+
+static INLINE PDL_LIST DL_ListRemoveItemFromTail(PDL_LIST pList) {
+    PDL_LIST pItem = NULL;
+    if (pList->pPrev != pList) {
+        pItem = pList->pPrev;
+            /* remove the item from tail */
+        DL_ListRemove(pItem);
+    }
+    return pItem;
+}
+
+/* transfer src list items to the tail of the destination list */
+static INLINE void DL_ListTransferItemsToTail(PDL_LIST pDest, PDL_LIST pSrc) {
+        /* only concatenate if src is not empty */
+    if (!DL_LIST_IS_EMPTY(pSrc)) {
+            /* cut out circular list in src and re-attach to end of dest */
+        pSrc->pPrev->pNext = pDest;
+        pSrc->pNext->pPrev = pDest->pPrev;
+        pDest->pPrev->pNext = pSrc->pNext; 
+        pDest->pPrev = pSrc->pPrev;
+            /* terminate src list, it is now empty */      
+        pSrc->pPrev = pSrc;
+        pSrc->pNext = pSrc;
+    }
+}
+
+#endif /* __DL_LIST_H___ */
diff --git a/drivers/net/wireless/ath6kl/include/dset_api.h b/drivers/net/wireless/ath6kl/include/dset_api.h
new file mode 100644
index 000000000000..9456df988073
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dset_api.h
@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side DataSet API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DSET_API_H_
+#define _DSET_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Host-side DataSet support is optional, and is not
+ * currently required for correct operation.  To disable
+ * Host-side DataSet support, set this to 0.
+ */
+#ifndef CONFIG_HOST_DSET_SUPPORT
+#define CONFIG_HOST_DSET_SUPPORT 1
+#endif
+
+/* Called to send a DataSet Open Reply back to the Target. */
+A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
+                             A_UINT32 status,
+                             A_UINT32 access_cookie,
+                             A_UINT32 size,
+                             A_UINT32 version,
+                             A_UINT32 targ_handle,
+                             A_UINT32 targ_reply_fn,
+                             A_UINT32 targ_reply_arg);
+
+/* Called to send a DataSet Data Reply back to the Target. */
+A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
+                             A_UINT32 status,
+                             A_UINT8 *host_buf,
+                             A_UINT32 length,
+                             A_UINT32 targ_buf,
+                             A_UINT32 targ_reply_fn,
+                             A_UINT32 targ_reply_arg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _DSET_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dset_internal.h b/drivers/net/wireless/ath6kl/include/dset_internal.h
new file mode 100644
index 000000000000..474f3c273574
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dset_internal.h
@@ -0,0 +1,51 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_internal.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSET_INTERNAL_H__
+#define __DSET_INTERNAL_H__
+
+/*
+ * Internal dset definitions, common for DataSet layer.
+ */
+
+#define DSET_TYPE_STANDARD      0
+#define DSET_TYPE_BPATCHED      1
+#define DSET_TYPE_COMPRESSED    2
+
+/* Dataset descriptor */
+
+typedef struct dset_descriptor_s {
+  struct dset_descriptor_s  *next;         /* List link. NULL only at the last
+                                              descriptor */
+  A_UINT16                   id;           /* Dset ID */
+  A_UINT16                   size;         /* Dset size. */
+  void                      *DataPtr;      /* Pointer to raw data for standard
+                                              DataSet or pointer to original
+                                              dset_descriptor for patched
+                                              DataSet */
+  A_UINT32                   data_type;    /* DSET_TYPE_*, above */
+
+  void                      *AuxPtr;       /* Additional data that might
+                                              needed for data_type. For
+                                              example, pointer to patch
+                                              Dataset descriptor for BPatch. */
+} dset_descriptor_t;
+
+#endif /* __DSET_INTERNAL_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/dsetid.h b/drivers/net/wireless/ath6kl/include/dsetid.h
new file mode 100644
index 000000000000..fc42fd20ba83
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dsetid.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="dsetid.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSETID_H__
+#define __DSETID_H__
+
+/* Well-known DataSet IDs */
+#define DSETID_UNUSED                     0x00000000
+#define DSETID_BOARD_DATA                 0x00000001 /* Cal and board data */
+#define DSETID_REGDB                      0x00000002 /* Regulatory Database */
+#define DSETID_POWER_CONTROL              0x00000003 /* TX Pwr Lim & Ant Gain */
+#define DSETID_USER_CONFIG                0x00000004 /* User Configuration */
+
+#define DSETID_ANALOG_CONTROL_DATA_START  0x00000005
+#define DSETID_ANALOG_CONTROL_DATA_END    0x00000025
+/*
+ * Get DSETID for various reference clock speeds.
+ * For each speed there are three DataSets that correspond
+ * to the three columns of bank6 data (addr, 11a, 11b/g).
+ * This macro returns the dsetid of the first of those
+ * three DataSets.
+ */
+#define ANALOG_CONTROL_DATA_DSETID(refclk) \
+        (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
+
+/*
+ * There are TWO STARTUP_PATCH DataSets.
+ * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
+ * earlier systems.  On AR6002, it is applied after BMI, just like
+ * DSETID_STARTUP_PATCH2.
+ */
+#define DSETID_STARTUP_PATCH              0x00000026
+#define DSETID_GPIO_CONFIG_PATCH          0x00000027
+#define DSETID_WLANREGS                   0x00000028 /* override wlan regs */
+#define DSETID_STARTUP_PATCH2             0x00000029
+
+#define DSETID_WOW_CONFIG                 0x00000090 /* WoW Configuration */
+
+/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
+#define DSETID_INI_DATA                   0x00000100
+/* Reserved for WHAL INI Tables: 0x100..0x11f */
+#define DSETID_INI_DATA_END               0x0000011f
+
+#define DSETID_VENDOR_START               0x00010000 /* Vendor-defined DataSets */
+
+#define DSETID_INDEX_END                  0xfffffffe /* Reserved to indicate the
+                                                        end of a memory-based
+                                                        DataSet Index */
+#define DSETID_INDEX_FREE                 0xffffffff /* An unused index entry */
+
+/* 
+ * PATCH DataSet format:
+ * A list of patches, terminated by a patch with
+ * address=PATCH_END.
+ *
+ * This allows for patches to be stored in flash.
+ */
+struct patch_s {
+    A_UINT32 *address;
+    A_UINT32  data;
+};
+
+/*
+ * Skip some patches.  Can be used to erase a single patch in a
+ * patch DataSet without having to re-write the DataSet.  May
+ * also be used to embed information for use by subsequent
+ * patch code.  The "data" in a PATCH_SKIP tells how many
+ * bytes of length "patch_s" to skip.
+ */
+#define PATCH_SKIP      ((A_UINT32 *)0x00000000)
+
+/*
+ * Execute code at the address specified by "data".
+ * The address of the patch structure is passed as
+ * the one parameter.
+ */
+#define PATCH_CODE_ABS  ((A_UINT32 *)0x00000001)
+
+/*
+ * Same as PATCH_CODE_ABS, but treat "data" as an
+ * offset from the start of the patch word.
+ */
+#define PATCH_CODE_REL  ((A_UINT32 *)0x00000002)
+
+/* Mark the end of this patch DataSet. */
+#define PATCH_END       ((A_UINT32 *)0xffffffff)
+
+/*
+ * A DataSet which contains a Binary Patch to some other DataSet
+ * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
+ * Such a BPatch DataSet consists of BPatch metadata followed by
+ * the bdiff bytes.  BPatch metadata consists of a single 32-bit
+ * word that contains the size of the BPatched final image.
+ *
+ * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
+ * to create "diffs":
+ *  bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
+ * Then add BPatch metadata to the start of "diffs".
+ *
+ * NB: There are some implementation-induced restrictions
+ * on which DataSets can be BPatched.
+ */
+#define DSETID_BPATCH_FLAG                0x80000000
+
+#endif /* __DSETID_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/epping_test.h b/drivers/net/wireless/ath6kl/include/epping_test.h
new file mode 100644
index 000000000000..e76b6420758d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/epping_test.h
@@ -0,0 +1,115 @@
+//------------------------------------------------------------------------------
+// <copyright file="epping_test.h" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//
+
+/* This file contains shared definitions for the host/target endpoint ping test */
+
+#ifndef EPPING_TEST_H_
+#define EPPING_TEST_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+    /* alignment to 4-bytes */
+#define EPPING_ALIGNMENT_PAD  (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
+
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+
+#define EPPING_RSVD_FILL                  0xCC
+
+#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET  7 
+  
+typedef PREPACK struct {    
+    A_UINT8     _HCIRsvd[8];           /* reserved for HCI packet header (GMBOX) testing */
+    A_UINT8     StreamEcho_h;          /* stream no. to echo this packet on (filled by host) */
+    A_UINT8     StreamEchoSent_t;      /* stream no. packet was echoed to (filled by target)
+                                          When echoed: StreamEchoSent_t == StreamEcho_h */
+    A_UINT8     StreamRecv_t;          /* stream no. that target received this packet on (filled by target) */
+    A_UINT8     StreamNo_h;            /* stream number to send on (filled by host) */   
+    A_UINT8     Magic_h[4];            /* magic number to filter for this packet on the host*/
+    A_UINT8     _rsvd[6];              /* reserved fields that must be set to a "reserved" value
+                                          since this packet maps to a 14-byte ethernet frame we want 
+                                          to make sure ethertype field is set to something unknown */
+                                          
+    A_UINT8     _pad[2];               /* padding for alignment */                      
+    A_UINT8     TimeStamp[8];          /* timestamp of packet (host or target) */
+    A_UINT32    HostContext_h;         /* 4 byte host context, target echos this back */
+    A_UINT32    SeqNo;                 /* sequence number (set by host or target) */   
+    A_UINT16    Cmd_h;                 /* ping command (filled by host) */  
+    A_UINT16    CmdFlags_h;            /* optional flags */
+    A_UINT8     CmdBuffer_h[8];        /* buffer for command (host -> target) */
+    A_UINT8     CmdBuffer_t[8];        /* buffer for command (target -> host) */  
+    A_UINT16    DataLength;            /* length of data */
+    A_UINT16    DataCRC;               /* 16 bit CRC of data */
+    A_UINT16    HeaderCRC;             /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */                       
+} POSTPACK EPPING_HEADER;
+
+#define EPPING_PING_MAGIC_0               0xAA
+#define EPPING_PING_MAGIC_1               0x55
+#define EPPING_PING_MAGIC_2               0xCE
+#define EPPING_PING_MAGIC_3               0xEC
+
+
+
+#define IS_EPPING_PACKET(pPkt)   (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
+                                  ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
+                                  ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
+                                  ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
+
+#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
+                                        (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
+                                        (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
+                                        (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
+                                                                            
+#define CMD_FLAGS_DATA_CRC            (1 << 0)  /* DataCRC field is valid */
+#define CMD_FLAGS_DELAY_ECHO          (1 << 1)  /* delay the echo of the packet */
+#define CMD_FLAGS_NO_DROP             (1 << 2)  /* do not drop at HTC layer no matter what the stream is */
+
+#define IS_EPING_PACKET_NO_DROP(pPkt)  ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
+
+#define EPPING_CMD_ECHO_PACKET          1   /* echo packet test */
+#define EPPING_CMD_RESET_RECV_CNT       2   /* reset recv count */
+#define EPPING_CMD_CAPTURE_RECV_CNT     3   /* fetch recv count, 4-byte count returned in CmdBuffer_t */
+#define EPPING_CMD_NO_ECHO              4   /* non-echo packet test (tx-only) */
+#define EPPING_CMD_CONT_RX_START        5   /* continous RX packets, parameters are in CmdBuffer_h */
+#define EPPING_CMD_CONT_RX_STOP         6   /* stop continuous RX packet transmission */
+
+    /* test command parameters may be no more than 8 bytes */
+typedef PREPACK struct {    
+    A_UINT16  BurstCnt;       /* number of packets to burst together (for HTC 2.1 testing) */
+    A_UINT16  PacketLength;   /* length of packet to generate including header */      
+    A_UINT16  Flags;          /* flags */
+
+#define EPPING_CONT_RX_DATA_CRC     (1 << 0)  /* Add CRC to all data */
+#define EPPING_CONT_RX_RANDOM_DATA  (1 << 1)  /* randomize the data pattern */
+#define EPPING_CONT_RX_RANDOM_LEN   (1 << 2)  /* randomize the packet lengths */          
+} POSTPACK EPPING_CONT_RX_PARAMS;
+
+#define EPPING_HDR_CRC_OFFSET    A_OFFSETOF(EPPING_HEADER,StreamNo_h)
+#define EPPING_HDR_BYTES_CRC     (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
+
+#define HCI_TRANSPORT_STREAM_NUM  16  /* this number is higher than the define WMM AC classes so we
+                                         can use this to distinguish packets */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+    
+    
+#endif /*EPPING_TEST_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/gmboxif.h b/drivers/net/wireless/ath6kl/include/gmboxif.h
new file mode 100644
index 000000000000..0d4120e34978
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gmboxif.h
@@ -0,0 +1,73 @@
+//------------------------------------------------------------------------------
+// <copyright file="gmboxif.h" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __GMBOXIF_H__
+#define __GMBOXIF_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* GMBOX interface definitions */
+    
+#define AR6K_GMBOX_CREDIT_COUNTER       1   /* we use credit counter 1 to track credits */
+#define AR6K_GMBOX_CREDIT_SIZE_COUNTER  2   /* credit counter 2 is used to pass the size of each credit */
+
+
+    /* HCI UART transport definitions when used over GMBOX interface */
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT     0x02
+#define HCI_UART_SCO_PKT     0x03
+#define HCI_UART_EVENT_PKT   0x04
+
+    /* definitions for BT HCI packets */
+typedef PREPACK struct {
+    A_UINT16 Flags_ConnHandle;
+    A_UINT16 Length;
+} POSTPACK BT_HCI_ACL_HEADER;
+
+typedef PREPACK struct {
+    A_UINT16 Flags_ConnHandle;
+    A_UINT8  Length;
+} POSTPACK BT_HCI_SCO_HEADER;
+
+typedef PREPACK struct {
+    A_UINT16 OpCode;
+    A_UINT8  ParamLength;
+} POSTPACK BT_HCI_COMMAND_HEADER;
+
+typedef PREPACK struct {
+    A_UINT8  EventCode;
+    A_UINT8  ParamLength;
+} POSTPACK BT_HCI_EVENT_HEADER;
+
+/* MBOX host interrupt signal assignments */
+
+#define MBOX_SIG_HCI_BRIDGE_MAX      8
+#define MBOX_SIG_HCI_BRIDGE_BT_ON    0
+#define MBOX_SIG_HCI_BRIDGE_BT_OFF   1
+#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
+
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __GMBOXIF_H__ */
+
diff --git a/drivers/net/wireless/ath6kl/include/gpio.h b/drivers/net/wireless/ath6kl/include/gpio.h
new file mode 100644
index 000000000000..9865af05ebd9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gpio.h
@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------
+// <copyright file="gpio.h" company="Atheros">
+//    Copyright (c) 2005 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#define AR6001_GPIO_PIN_COUNT 18
+#define AR6002_GPIO_PIN_COUNT 18
+#define AR6003_GPIO_PIN_COUNT 28
+
+/*
+ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
+ * NB: These match hardware order, so that addresses can
+ * easily be computed.
+ */
+#define GPIO_ID_OUT             0x00000000
+#define GPIO_ID_OUT_W1TS        0x00000001
+#define GPIO_ID_OUT_W1TC        0x00000002
+#define GPIO_ID_ENABLE          0x00000003
+#define GPIO_ID_ENABLE_W1TS     0x00000004
+#define GPIO_ID_ENABLE_W1TC     0x00000005
+#define GPIO_ID_IN              0x00000006
+#define GPIO_ID_STATUS          0x00000007
+#define GPIO_ID_STATUS_W1TS     0x00000008
+#define GPIO_ID_STATUS_W1TC     0x00000009
+#define GPIO_ID_PIN0            0x0000000a
+#define GPIO_ID_PIN(n)          (GPIO_ID_PIN0+(n))
+
+#define GPIO_LAST_REGISTER_ID   GPIO_ID_PIN(17)
+#define GPIO_ID_NONE            0xffffffff
diff --git a/drivers/net/wireless/ath6kl/include/gpio_api.h b/drivers/net/wireless/ath6kl/include/gpio_api.h
new file mode 100644
index 000000000000..82edcdd418bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gpio_api.h
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+// <copyright file="gpio_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side General Purpose I/O API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _GPIO_API_H_
+#define _GPIO_API_H_
+
+/*
+ * Send a command to the Target in order to change output on GPIO pins.
+ */
+A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
+                             A_UINT32 set_mask,
+                             A_UINT32 clear_mask,
+                             A_UINT32 enable_mask,
+                             A_UINT32 disable_mask);
+
+/*
+ * Send a command to the Target requesting input state of GPIO pins.
+ */
+A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
+
+/*
+ * Send a command to the Target to change the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
+                               A_UINT32 gpioreg_id,
+                               A_UINT32 value);
+
+/*
+ * Send a command to the Target to fetch the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
+
+/*
+ * Send a command to the Target, acknowledging some GPIO interrupts.
+ */
+A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
+
+#endif /* _GPIO_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/hci_transport_api.h b/drivers/net/wireless/ath6kl/include/hci_transport_api.h
new file mode 100644
index 000000000000..a6cc16fc325a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/hci_transport_api.h
@@ -0,0 +1,243 @@
+//------------------------------------------------------------------------------
+// <copyright file="HCI_TRANSPORT_api.h" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HCI_TRANSPORT_API_H_
+#define _HCI_TRANSPORT_API_H_
+
+    /* Bluetooth HCI packets are stored in HTC packet containers */
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void *HCI_TRANSPORT_HANDLE;
+
+typedef HTC_ENDPOINT_ID HCI_TRANSPORT_PACKET_TYPE; 
+
+    /* we map each HCI packet class to a static Endpoint ID */
+#define HCI_COMMAND_TYPE   ENDPOINT_1
+#define HCI_EVENT_TYPE     ENDPOINT_2
+#define HCI_ACL_TYPE       ENDPOINT_3
+#define HCI_PACKET_INVALID ENDPOINT_MAX
+
+#define HCI_GET_PACKET_TYPE(pP)    (pP)->Endpoint
+#define HCI_SET_PACKET_TYPE(pP,s)  (pP)->Endpoint = (s)
+
+/* callback when an HCI packet was completely sent */
+typedef void   (*HCI_TRANSPORT_SEND_PKT_COMPLETE)(void *, HTC_PACKET *);
+/* callback when an HCI packet is received */
+typedef void   (*HCI_TRANSPORT_RECV_PKT)(void *, HTC_PACKET *);
+/* Optional receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ * A refill callback is used for the reception of ACL and EVENT packets.  The caller must
+ * set the watermark trigger point to cause a refill.
+ */
+typedef void   (*HCI_TRANSPORT_RECV_REFILL)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable);
+/* Optional receive packet refill
+ * On some systems packet buffers are an extremely limited resource.  Rather than
+ * queue largest-possible-sized buffers to the HCI bridge, some systems would rather
+ * allocate a specific size as the packet is received.  The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into the bridge.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * full transport header, HCI header, plus the length of payload.  The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * NOTE*** This callback is mutually exclusive with the the refill callback above.
+ *
+ * */
+typedef HTC_PACKET *(*HCI_TRANSPORT_RECV_ALLOC)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int Length);
+
+typedef enum _HCI_SEND_FULL_ACTION {
+    HCI_SEND_FULL_KEEP = 0,  /* packet that overflowed should be kept in the queue */
+    HCI_SEND_FULL_DROP = 1,  /* packet that overflowed should be dropped */
+} HCI_SEND_FULL_ACTION;
+
+/* callback when an HCI send queue exceeds the caller's MaxSendQueueDepth threshold,
+ * the callback must return the send full action to take (either DROP or KEEP) */
+typedef HCI_SEND_FULL_ACTION  (*HCI_TRANSPORT_SEND_FULL)(void *, HTC_PACKET *);
+
+typedef struct {
+    int    HeadRoom;      /* number of bytes in front of HCI packet for header space */
+    int    TailRoom;      /* number of bytes at the end of the HCI packet for tail space */
+    int    IOBlockPad;    /* I/O block padding required (always a power of 2) */
+} HCI_TRANSPORT_PROPERTIES;
+
+typedef struct _HCI_TRANSPORT_CONFIG_INFO {
+    int      ACLRecvBufferWaterMark;     /* low watermark to trigger recv refill */
+    int      EventRecvBufferWaterMark;   /* low watermark to trigger recv refill */  
+    int      MaxSendQueueDepth;          /* max number of packets in the single send queue */
+    void     *pContext;                  /* context for all callbacks */
+    void     (*TransportFailure)(void *pContext, A_STATUS Status); /* transport failure callback */
+    A_STATUS (*TransportReady)(HCI_TRANSPORT_HANDLE, HCI_TRANSPORT_PROPERTIES *,void *pContext); /* transport is ready */
+    void     (*TransportRemoved)(void *pContext);                  /* transport was removed */
+        /* packet processing callbacks */
+    HCI_TRANSPORT_SEND_PKT_COMPLETE    pHCISendComplete;
+    HCI_TRANSPORT_RECV_PKT             pHCIPktRecv;
+    HCI_TRANSPORT_RECV_REFILL          pHCIPktRecvRefill;
+    HCI_TRANSPORT_RECV_ALLOC           pHCIPktRecvAlloc;
+    HCI_TRANSPORT_SEND_FULL            pHCISendFull;
+} HCI_TRANSPORT_CONFIG_INFO;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Attach to the HCI transport module
+  @function name: HCI_TransportAttach
+  @input:  HTCHandle - HTC handle (see HTC apis)
+           pInfo - initialization information
+  @output:
+  @return: HCI_TRANSPORT_HANDLE on success, NULL on failure
+  @notes:    The HTC module provides HCI transport services.
+  @example:
+  @see also: HCI_TransportDetach
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Detach from the HCI transport module
+  @function name: HCI_TransportDetach
+  @input:  HciTrans - HCI transport handle
+           pInfo - initialization information
+  @output:
+  @return: 
+  @notes:  
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add receive packets to the HCI transport
+  @function name: HCI_TransportAddReceivePkts
+  @input:  HciTrans - HCI transport handle
+           pQueue - a queue holding one or more packets
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HCI packets.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro. Each packet in the queue must be of the same type and length 
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Send an HCI packet packet
+  @function name: HCI_TransportSendPkt
+  @input:  HciTrans - HCI transport handle
+           pPacket - packet to send
+           Synchronous - send the packet synchronously (blocking)
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() and
+           HCI_SET_PACKET_TYPE() macros to prepare the packet. 
+           If Synchronous is set to FALSE the call is fully asynchronous.  On error or completion, 
+           the registered send complete callback will be called.
+           If Synchronous is set to TRUE, the call will block until the packet is sent, if the
+           interface cannot send the packet within a 2 second timeout, the function will return 
+           the failure code : A_EBUSY.
+           
+           Synchronous Mode should only be used at start-up to initialize the HCI device using 
+           custom HCI commands.  It should NOT be mixed with Asynchronous operations.  Mixed synchronous
+           and asynchronous operation behavior is undefined.
+           
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Stop HCI transport
+  @function name: HCI_TransportStop
+  @input:  HciTrans - hci transport handle 
+  @output:
+  @return:
+  @notes: HCI transport communication will be halted.  All receive and pending TX packets will
+          be flushed.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Start the HCI transport
+  @function name: HCI_TransportStart
+  @input:  HciTrans - hci transport handle 
+  @output:
+  @return: A_OK on success
+  @notes: HCI transport communication will begin, the caller can expect the arrival
+          of HCI recv packets as soon as this call returns.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Enable or Disable Asynchronous Recv
+  @function name: HCI_TransportEnableDisableAsyncRecv
+  @input:  HciTrans - hci transport handle 
+           Enable - enable or disable asynchronous recv
+  @output:
+  @return: A_OK on success
+  @notes: This API must be called when HCI recv is handled synchronously
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Receive an event packet from the HCI transport synchronously using polling
+  @function name: HCI_TransportRecvHCIEventSync
+  @input:  HciTrans - hci transport handle 
+           pPacket - HTC packet to hold the recv data
+           MaxPollMS - maximum polling duration in Milliseconds;
+  @output: 
+  @return: A_OK on success
+  @notes: This API should be used only during HCI device initialization, the caller must call
+          HCI_TransportEnableDisableAsyncRecv with Enable=FALSE prior to using this API. 
+          This API will only capture HCI Event packets.
+  @example:
+  @see also: HCI_TransportEnableDisableAsyncRecv
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Set the desired baud rate for the underlying transport layer
+  @function name: HCI_TransportSetBaudRate
+  @input:  HciTrans - hci transport handle 
+           Baud - baud rate in bps
+  @output: 
+  @return: A_OK on success
+  @notes: This API should be used only after HCI device initialization
+  @example:
+  @see also: 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HCI_TRANSPORT_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/hif.h b/drivers/net/wireless/ath6kl/include/hif.h
new file mode 100644
index 000000000000..bc6e6a5b3448
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/hif.h
@@ -0,0 +1,421 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF specific declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_H_
+#define _HIF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "dl_list.h"
+
+
+typedef struct htc_callbacks HTC_CALLBACKS;
+typedef struct hif_device HIF_DEVICE;
+
+/*
+ * direction - Direction of transfer (HIF_READ/HIF_WRITE).
+ */
+#define HIF_READ                    0x00000001
+#define HIF_WRITE                   0x00000002
+#define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
+
+/*
+ *     type - An interface may support different kind of read/write commands.
+ *            For example: SDIO supports CMD52/CMD53s. In case of MSIO it
+ *            translates to using different kinds of TPCs. The command type
+ *            is thus divided into a basic and an extended command and can
+ *            be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
+ */
+#define HIF_BASIC_IO                0x00000004
+#define HIF_EXTENDED_IO             0x00000008
+#define HIF_TYPE_MASK               (HIF_BASIC_IO | HIF_EXTENDED_IO)
+
+/*
+ *     emode - This indicates the whether the command is to be executed in a
+ *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
+ *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
+ *             implemented using the asynchronous mode allowing the the bus
+ *             driver to indicate the completion of operation through the
+ *             registered callback routine. The requirement primarily comes
+ *             from the contexts these operations get called from (a driver's
+ *             transmit context or the ISR context in case of receive).
+ *             Support for both of these modes is essential.
+ */
+#define HIF_SYNCHRONOUS             0x00000010
+#define HIF_ASYNCHRONOUS            0x00000020
+#define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
+
+/*
+ *     dmode - An interface may support different kinds of commands based on
+ *             the tradeoff between the amount of data it can carry and the
+ *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
+ *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
+ *             to the nearest block size by padding. The size of the block is
+ *             configurable at compile time using the HIF_BLOCK_SIZE and is
+ *             negotiated with the target during initialization after the
+ *             AR6000 interrupts are enabled.
+ */
+#define HIF_BYTE_BASIS              0x00000040
+#define HIF_BLOCK_BASIS             0x00000080
+#define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
+
+/*
+ *     amode - This indicates if the address has to be incremented on AR6000 
+ *             after every read/write operation (HIF?FIXED_ADDRESS/
+ *             HIF_INCREMENTAL_ADDRESS).
+ */
+#define HIF_FIXED_ADDRESS           0x00000100
+#define HIF_INCREMENTAL_ADDRESS     0x00000200
+#define HIF_AMODE_MASK              (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
+
+#define HIF_WR_ASYNC_BYTE_FIX   \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_ASYNC_BYTE_INC   \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_INC  \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BYTE_FIX    \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BYTE_INC    \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_INC  \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_FIX \
+    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_FIX  \
+    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_SYNC_BYTE_INC    \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BYTE_FIX    \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_FIX   \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_FIX  \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_INC   \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_INC  \
+    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_INC  \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_FIX  \
+    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+    
+typedef enum {
+    HIF_DEVICE_POWER_STATE = 0,
+    HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+    HIF_DEVICE_GET_MBOX_ADDR,
+    HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+    HIF_DEVICE_GET_IRQ_PROC_MODE,
+    HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+    HIF_DEVICE_POWER_STATE_CHANGE,
+    HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+    HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+    HIF_DEVICE_GET_OS_DEVICE,
+    HIF_DEVICE_DEBUG_BUS_STATE,
+} HIF_DEVICE_CONFIG_OPCODE;
+
+/*
+ * HIF CONFIGURE definitions:
+ *
+ *   HIF_DEVICE_GET_MBOX_BLOCK_SIZE
+ *   input : none
+ *   output : array of 4 A_UINT32s
+ *   notes: block size is returned for each mailbox (4)
+ *
+ *   HIF_DEVICE_GET_MBOX_ADDR
+ *   input : none
+ *   output : HIF_DEVICE_MBOX_INFO
+ *   notes: 
+ *
+ *   HIF_DEVICE_GET_PENDING_EVENTS_FUNC
+ *   input : none
+ *   output: HIF_PENDING_EVENTS_FUNC function pointer
+ *   notes: this is optional for the HIF layer, if the request is
+ *          not handled then it indicates that the upper layer can use
+ *          the standard device methods to get pending events (IRQs, mailbox messages etc..)
+ *          otherwise it can call the function pointer to check pending events.
+ *
+ *   HIF_DEVICE_GET_IRQ_PROC_MODE
+ *   input : none
+ *   output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
+ *   note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
+ *         layer can report whether IRQ processing is requires synchronous behavior or
+ *         can be processed using asynchronous bus requests (typically faster).
+ *
+ *   HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
+ *   input :
+ *   output : HIF_MASK_UNMASK_RECV_EVENT function pointer
+ *   notes: this is optional for the HIF layer.  The HIF layer may require a special mechanism
+ *          to mask receive message events.  The upper layer can call this pointer when it needs
+ *          to mask/unmask receive events (in case it runs out of buffers).
+ *
+ *   HIF_DEVICE_POWER_STATE_CHANGE
+ *
+ *   input : HIF_DEVICE_POWER_CHANGE_TYPE
+ *   output : none
+ *   note: this is optional for the HIF layer.  The HIF layer can handle power on/off state change
+ *         requests in an interconnect specific way.  This is highly OS and bus driver dependent.
+ *         The caller must guarantee that no HIF read/write requests will be made after the device
+ *         is powered down.
+ *
+ *   HIF_DEVICE_GET_IRQ_YIELD_PARAMS
+ * 
+ *   input : none
+ *   output : HIF_DEVICE_IRQ_YIELD_PARAMS
+ *   note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler.
+ *   The DSR callback handler will exit after a fixed number of RX packets or events are processed.  
+ *   This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY. 
+ *   The HIF implementation can ignore this command if it does not desire the DSR callback to yield.
+ *   The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the
+ *   DSR handler callback must yield and return control back to the HIF layer.  When a yield limit is 
+ *   used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning.  
+ *   The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared
+ *   to process interrupts again.
+ *   
+ *   HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT
+ *   input : none
+ *   output : HIF_DEVICE_SCATTER_SUPPORT_INFO
+ *   note:  This query checks if the HIF layer implements the SCATTER request interface.  Scatter requests
+ *   allows upper layers to submit mailbox I/O operations using a list of buffers.  This is useful for
+ *   multi-message transfers that can better utilize the bus interconnect.
+ * 
+ * 
+ *   HIF_DEVICE_GET_OS_DEVICE
+ *   intput : none
+ *   output : HIF_DEVICE_OS_DEVICE_INFO;
+ *   note: On some operating systems, the HIF layer has a parent device object for the bus.  This object
+ *         may be required to register certain types of logical devices.
+ * 
+ *   HIF_DEVICE_DEBUG_BUS_STATE
+ *   input : none
+ *   output : none
+ *   note: This configure option triggers the HIF interface to dump as much bus interface state.  This 
+ *   configuration request is optional (No-OP on some HIF implementations)
+ * 
+ */
+
+typedef struct {
+    A_UINT32    ExtendedAddress;  /* extended address for larger writes */  
+    A_UINT32    ExtendedSize;
+} HIF_MBOX_PROPERTIES;
+
+#define HIF_MBOX_FLAG_NO_BUNDLING   (1 << 0)   /* do not allow bundling over the mailbox */
+
+typedef struct {
+    A_UINT32 MboxAddresses[4];  /* must be first element for legacy HIFs that return the address in  
+                                   and ARRAY of 32-bit words */
+    
+        /* the following describe extended mailbox properties */
+    HIF_MBOX_PROPERTIES MboxProp[4];
+        /* if the HIF supports the GMbox extended address region it can report it
+         * here, some interfaces cannot support the GMBOX address range and not set this */
+    A_UINT32 GMboxAddress;  
+    A_UINT32 GMboxSize;
+    A_UINT32 Flags;             /* flags to describe mbox behavior or usage */
+} HIF_DEVICE_MBOX_INFO;
+
+typedef enum {
+    HIF_DEVICE_IRQ_SYNC_ONLY,   /* for HIF implementations that require the DSR to process all
+                                   interrupts before returning */
+    HIF_DEVICE_IRQ_ASYNC_SYNC,  /* for HIF implementations that allow DSR to process interrupts
+                                   using ASYNC I/O (that is HIFAckInterrupt can be called at a
+                                   later time */
+} HIF_DEVICE_IRQ_PROCESSING_MODE;
+
+typedef enum {
+    HIF_DEVICE_POWER_UP,    /* HIF layer should power up interface and/or module */
+    HIF_DEVICE_POWER_DOWN,  /* HIF layer should initiate bus-specific measures to minimize power */
+    HIF_DEVICE_POWER_CUT    /* HIF layer should initiate bus-specific AND/OR platform-specific measures
+                               to completely power-off the module and associated hardware (i.e. cut power supplies)
+                            */
+} HIF_DEVICE_POWER_CHANGE_TYPE;
+
+typedef struct {
+    int     RecvPacketYieldCount; /* max number of packets to force DSR to return */
+} HIF_DEVICE_IRQ_YIELD_PARAMS;
+
+
+typedef struct _HIF_SCATTER_ITEM {
+    A_UINT8     *pBuffer;             /* CPU accessible address of buffer */
+    int          Length;              /* length of transfer to/from this buffer */
+    void        *pCallerContexts[2];  /* space for caller to insert a context associated with this item */
+} HIF_SCATTER_ITEM;
+
+struct _HIF_SCATTER_REQ;
+
+typedef void ( *HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *);
+
+typedef enum _HIF_SCATTER_METHOD {
+    HIF_SCATTER_NONE = 0,
+    HIF_SCATTER_DMA_REAL,              /* Real SG support no restrictions */
+    HIF_SCATTER_DMA_BOUNCE,            /* Uses SG DMA but HIF layer uses an internal bounce buffer */    
+} HIF_SCATTER_METHOD;
+
+typedef struct _HIF_SCATTER_REQ {
+    DL_LIST             ListLink;           /* link management */
+    A_UINT32            Address;            /* address for the read/write operation */
+    A_UINT32            Request;            /* request flags */
+    A_UINT32            TotalLength;        /* total length of entire transfer */
+    A_UINT32            CallerFlags;        /* caller specific flags can be stored here */
+    HIF_SCATTER_COMP_CB CompletionRoutine;  /* completion routine set by caller */
+    A_STATUS            CompletionStatus;   /* status of completion */
+    void                *Context;           /* caller context for this request */
+    int                 ValidScatterEntries;  /* number of valid entries set by caller */
+    HIF_SCATTER_METHOD  ScatterMethod;        /* scatter method handled by HIF */  
+    void                *HIFPrivate[4];     /* HIF private area */
+    A_UINT8             *pScatterBounceBuffer;  /* bounce buffer for upper layers to copy to/from */
+    HIF_SCATTER_ITEM    ScatterList[1];     /* start of scatter list */
+} HIF_SCATTER_REQ;
+
+typedef HIF_SCATTER_REQ * ( *HIF_ALLOCATE_SCATTER_REQUEST)(HIF_DEVICE *device);
+typedef void ( *HIF_FREE_SCATTER_REQUEST)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+typedef A_STATUS ( *HIF_READWRITE_SCATTER)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+
+typedef struct _HIF_DEVICE_SCATTER_SUPPORT_INFO {
+        /* information returned from HIF layer */
+    HIF_ALLOCATE_SCATTER_REQUEST    pAllocateReqFunc;
+    HIF_FREE_SCATTER_REQUEST        pFreeReqFunc;
+    HIF_READWRITE_SCATTER           pReadWriteScatterFunc;    
+    int                             MaxScatterEntries;
+    int                             MaxTransferSizePerScatterReq;
+} HIF_DEVICE_SCATTER_SUPPORT_INFO;
+                      
+typedef struct {
+    void    *pOSDevice;
+} HIF_DEVICE_OS_DEVICE_INFO;
+                      
+#define HIF_MAX_DEVICES                 1
+
+struct htc_callbacks {
+    void      *context;     /* context to pass to the dsrhandler
+                               note : rwCompletionHandler is provided the context passed to HIFReadWrite  */
+    A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status);
+    A_STATUS (* dsrHandler)(void *context);
+};
+
+typedef struct osdrv_callbacks {
+    void      *context;     /* context to pass for all callbacks except deviceRemovedHandler 
+                               the deviceRemovedHandler is only called if the device is claimed */
+    A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle);
+    A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle);
+    A_STATUS (* deviceSuspendHandler)(void *context);
+    A_STATUS (* deviceResumeHandler)(void *context);
+    A_STATUS (* deviceWakeupHandler)(void *context);  
+} OSDRV_CALLBACKS;
+
+#define HIF_OTHER_EVENTS     (1 << 0)   /* other interrupts (non-Recv) are pending, host
+                                           needs to read the register table to figure out what */
+#define HIF_RECV_MSG_AVAIL   (1 << 1)   /* pending recv packet */
+
+typedef struct _HIF_PENDING_EVENTS_INFO {
+    A_UINT32 Events;
+    A_UINT32 LookAhead;
+    A_UINT32 AvailableRecvBytes;
+} HIF_PENDING_EVENTS_INFO;
+
+    /* function to get pending events , some HIF modules use special mechanisms
+     * to detect packet available and other interrupts */
+typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE              *device,
+                                             HIF_PENDING_EVENTS_INFO *pEvents,
+                                             void                    *AsyncContext);
+
+#define HIF_MASK_RECV    TRUE
+#define HIF_UNMASK_RECV  FALSE
+    /* function to mask recv events */
+typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE  *device,
+                                                A_BOOL      Mask,
+                                                void        *AsyncContext);
+
+
+/*
+ * This API is used to perform any global initialization of the HIF layer
+ * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
+ * 
+ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks);
+
+/* This API claims the HIF device and provides a context for handling removal.
+ * The device removal callback is only called when the OSDRV layer claims
+ * a device.  The claimed context must be non-NULL */
+void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext);
+/* release the claimed device */
+void HIFReleaseDevice(HIF_DEVICE *device);
+
+/* This API allows the HTC layer to attach to the HIF device */
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks);
+/* This API detaches the HTC layer from the HIF device */
+void     HIFDetachHTC(HIF_DEVICE *device);
+
+/*
+ * This API is used to provide the read/write interface over the specific bus
+ * interface.
+ * address - Starting address in the AR6000's address space. For mailbox
+ *           writes, it refers to the start of the mbox boundary. It should
+ *           be ensured that the last byte falls on the mailbox's EOM. For
+ *           mailbox reads, it refers to the end of the mbox boundary.
+ * buffer - Pointer to the buffer containg the data to be transmitted or
+ *          received.
+ * length - Amount of data to be transmitted or received.
+ * request - Characterizes the attributes of the command.
+ */
+A_STATUS
+HIFReadWrite(HIF_DEVICE    *device,
+             A_UINT32       address,
+             A_UCHAR       *buffer,
+             A_UINT32       length,
+             A_UINT32       request,
+             void          *context);
+
+/*
+ * This can be initiated from the unload driver context when the OSDRV layer has no more use for
+ * the device.
+ */
+void HIFShutDownDevice(HIF_DEVICE *device);
+
+/*
+ * This should translate to an acknowledgment to the bus driver indicating that
+ * the previous interrupt request has been serviced and the all the relevant
+ * sources have been cleared. HTC is ready to process more interrupts.
+ * This should prevent the bus driver from raising an interrupt unless the
+ * previous one has been serviced and acknowledged using the previous API.
+ */
+void HIFAckInterrupt(HIF_DEVICE *device);
+
+void HIFMaskInterrupt(HIF_DEVICE *device);
+
+void HIFUnMaskInterrupt(HIF_DEVICE *device);
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+                   void *config, A_UINT32 configLen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HIF_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/host_version.h b/drivers/net/wireless/ath6kl/include/host_version.h
new file mode 100644
index 000000000000..8e464997ecf5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/host_version.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="host_version.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains version information for the sample host driver for the
+// AR6000 chip
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_VERSION_H_
+#define _HOST_VERSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <AR6002/AR6K_version.h>
+
+/*
+ * The version number is made up of major, minor, patch and build
+ * numbers. These are 16 bit numbers.  The build and release script will
+ * set the build number using a Perforce counter.  Here the build number is
+ * set to 9999 so that builds done without the build-release script are easily
+ * identifiable.
+ */
+
+#define ATH_SW_VER_MAJOR      __VER_MAJOR_
+#define ATH_SW_VER_MINOR      __VER_MINOR_
+#define ATH_SW_VER_PATCH      __VER_PATCH_
+#define ATH_SW_VER_BUILD      __BUILD_NUMBER_ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_VERSION_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/htc.h b/drivers/net/wireless/ath6kl/include/htc.h
new file mode 100644
index 000000000000..515c8ec62bdf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc.h
@@ -0,0 +1,232 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_H__
+#define __HTC_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+
+#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
+        (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
+        
+/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a 
+ * structure using only the type and field name.
+ * Use these macros if there is the potential for unaligned buffer accesses. */
+#define A_GET_UINT16_FIELD(p,type,field) \
+    ASSEMBLE_UNALIGNED_UINT16(p,\
+                              A_OFFSETOF(type,field) + 1, \
+                              A_OFFSETOF(type,field))
+
+#define A_SET_UINT16_FIELD(p,type,field,value) \
+{                                              \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value);        \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
+}
+  
+#define A_GET_UINT8_FIELD(p,type,field) \
+            ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
+            
+#define A_SET_UINT8_FIELD(p,type,field,value) \
+    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
+
+/****** DANGER DANGER ***************
+ * 
+ *   The frame header length and message formats defined herein were
+ *   selected to accommodate optimal alignment for target processing.  This reduces code
+ *   size and improves performance.
+ * 
+ *   Any changes to the header length may alter the alignment and cause exceptions
+ *   on the target. When adding to the message structures insure that fields are
+ *   properly aligned.
+ * 
+ */
+
+/* HTC frame header */
+typedef PREPACK struct _HTC_FRAME_HDR{
+        /* do not remove or re-arrange these fields, these are minimally required
+         * to take advantage of 4-byte lookaheads in some hardware implementations */
+    A_UINT8   EndpointID;
+    A_UINT8   Flags;
+    A_UINT16  PayloadLen;       /* length of data (including trailer) that follows the header */
+    
+    /***** end of 4-byte lookahead ****/
+    
+    A_UINT8   ControlBytes[2];
+    
+    /* message payload starts after the header */
+    
+} POSTPACK HTC_FRAME_HDR;
+
+/* frame header flags */
+
+    /* send direction */
+#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
+#define HTC_FLAGS_SEND_BUNDLE        (1 << 1)  /* start or part of bundle */
+    /* receive direction */
+#define HTC_FLAGS_RECV_UNUSED_0      (1 << 0)  /* bit 0 unused */    
+#define HTC_FLAGS_RECV_TRAILER       (1 << 1)  /* bit 1 trailer data present */
+#define HTC_FLAGS_RECV_UNUSED_2      (1 << 0)  /* bit 2 unused */
+#define HTC_FLAGS_RECV_UNUSED_3      (1 << 0)  /* bit 3 unused */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0)  /* bits 7..4  */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
+
+#define HTC_HDR_LENGTH  (sizeof(HTC_FRAME_HDR))
+#define HTC_MAX_TRAILER_LENGTH   255
+#define HTC_MAX_PAYLOAD_LENGTH   (4096 - sizeof(HTC_FRAME_HDR))
+
+/* HTC control message IDs */
+
+#define HTC_MSG_READY_ID                    1
+#define HTC_MSG_CONNECT_SERVICE_ID          2
+#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3   
+#define HTC_MSG_SETUP_COMPLETE_ID           4
+#define HTC_MSG_SETUP_COMPLETE_EX_ID        5
+
+#define HTC_MAX_CONTROL_MESSAGE_LENGTH  256
+         
+/* base message ID header */
+typedef PREPACK struct {
+    A_UINT16 MessageID;    
+} POSTPACK HTC_UNKNOWN_MSG;
+                                                     
+/* HTC ready message
+ * direction : target-to-host  */
+typedef PREPACK struct {
+    A_UINT16  MessageID;    /* ID */
+    A_UINT16  CreditCount;  /* number of credits the target can offer */       
+    A_UINT16  CreditSize;   /* size of each credit */
+    A_UINT8   MaxEndpoints; /* maximum number of endpoints the target has resources for */
+    A_UINT8   _Pad1;
+} POSTPACK HTC_READY_MSG;
+
+    /* extended HTC ready message */
+typedef PREPACK struct {
+    HTC_READY_MSG   Version2_0_Info;   /* legacy version 2.0 information at the front... */
+    /* extended information */
+    A_UINT8         HTCVersion;
+    A_UINT8         MaxMsgsPerHTCBundle;
+} POSTPACK HTC_READY_EX_MSG;
+
+#define HTC_VERSION_2P0  0x00  
+#define HTC_VERSION_2P1  0x01  /* HTC 2.1 */
+
+#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
+
+/* connect service
+ * direction : host-to-target */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT16  ServiceID;           /* service ID of the service to connect to */       
+    A_UINT16  ConnectionFlags;     /* connection flags */
+
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)  /* reduce credit dribbling when 
+                                                             the host needs credits */  
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK             (0x3)  
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH        0x0
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF          0x1
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS     0x2
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY             0x3
+                                                             
+    A_UINT8   ServiceMetaLength;   /* length of meta data that follows */
+    A_UINT8   _Pad1;
+    
+    /* service-specific meta data starts after the header */
+    
+} POSTPACK HTC_CONNECT_SERVICE_MSG;
+
+/* connect response
+ * direction : target-to-host */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT16  ServiceID;            /* service ID that the connection request was made */
+    A_UINT8   Status;               /* service connection status */ 
+    A_UINT8   EndpointID;           /* assigned endpoint ID */
+    A_UINT16  MaxMsgSize;           /* maximum expected message size on this endpoint */
+    A_UINT8   ServiceMetaLength;    /* length of meta data that follows */
+    A_UINT8   _Pad1;               
+    
+    /* service-specific meta data starts after the header */
+    
+} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
+
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    /* currently, no other fields */
+} POSTPACK HTC_SETUP_COMPLETE_MSG;
+
+    /* extended setup completion message */
+typedef PREPACK struct {
+    A_UINT16  MessageID;
+    A_UINT32  SetupFlags;
+    A_UINT8   MaxMsgsPerBundledRecv;
+    A_UINT8   Rsvd[3];
+} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
+
+#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV     (1 << 0)
+
+/* connect response status codes */
+#define HTC_SERVICE_SUCCESS      0  /* success */
+#define HTC_SERVICE_NOT_FOUND    1  /* service could not be found */
+#define HTC_SERVICE_FAILED       2  /* specific service failed the connect */
+#define HTC_SERVICE_NO_RESOURCES 3  /* no resources (i.e. no more endpoints) */  
+#define HTC_SERVICE_NO_MORE_EP   4  /* specific service is not allowing any more 
+                                       endpoints */
+
+/* report record IDs */
+
+#define HTC_RECORD_NULL             0
+#define HTC_RECORD_CREDITS          1
+#define HTC_RECORD_LOOKAHEAD        2
+#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
+
+typedef PREPACK struct {
+    A_UINT8 RecordID;     /* Record ID */
+    A_UINT8 Length;       /* Length of record */
+} POSTPACK HTC_RECORD_HDR;
+
+typedef PREPACK struct {
+    A_UINT8 EndpointID;     /* Endpoint that owns these credits */
+    A_UINT8 Credits;        /* credits to report since last report */
+} POSTPACK HTC_CREDIT_REPORT;
+
+typedef PREPACK struct {    
+    A_UINT8 PreValid;         /* pre valid guard */
+    A_UINT8 LookAhead[4];     /* 4 byte lookahead */
+    A_UINT8 PostValid;        /* post valid guard */
+    
+   /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
+    * The PreValid bytes must equal the inverse of the PostValid byte */
+    
+} POSTPACK HTC_LOOKAHEAD_REPORT;
+
+typedef PREPACK struct {    
+    A_UINT8 LookAhead[4];     /* 4 byte lookahead */    
+} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+
+#endif /* __HTC_H__ */
+
diff --git a/drivers/net/wireless/ath6kl/include/htc_api.h b/drivers/net/wireless/ath6kl/include/htc_api.h
new file mode 100644
index 000000000000..12f81f53ee90
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_api.h
@@ -0,0 +1,568 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_api.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_API_H_
+#define _HTC_API_H_
+
+#include <htc.h>
+#include <htc_services.h>
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* TODO.. for BMI */
+#define ENDPOINT1 0
+// TODO -remove me, but we have to fix BMI first
+#define HTC_MAILBOX_NUM_MAX    4
+
+/* this is the amount of header room required by users of HTC */
+#define HTC_HEADER_LEN         HTC_HDR_LENGTH
+
+typedef void *HTC_HANDLE;
+
+typedef A_UINT16 HTC_SERVICE_ID;
+
+typedef struct _HTC_INIT_INFO {
+    void   *pContext;           /* context for target failure notification */
+    void   (*TargetFailure)(void *Instance, A_STATUS Status);
+} HTC_INIT_INFO;
+
+/* per service connection send completion */
+typedef void   (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets have been sent
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of completed send packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ *   HTC_PACKET_ENQUEUE() */
+typedef void   (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+/* per service connection pkt received */
+typedef void   (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets are received
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of recv packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ *   HTC_PACKET_ENQUEUE() */
+typedef void   (*HTC_EP_RECV_PKT_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+
+/* Optional per service connection receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ *
+ * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
+ * the driver can re-queue these buffers into HTC. In this regard a refill callback is
+ * unnecessary */
+typedef void   (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
+
+/* Optional per service connection receive buffer allocation callback.
+ * On some systems packet buffers are an extremely limited resource.  Rather than
+ * queue largest-possible-sized buffers to HTC, some systems would rather
+ * allocate a specific size as the packet is received.  The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into HTC.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * HTC header length plus the length of payload.  The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * Alternatively a variant of this handler can be used to allocate large receive packets as needed.  
+ * For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to 
+ * handle the case where a large packet buffer is required.  This can significantly reduce the
+ * amount of "committed" memory used to receive packets.
+ *  
+ * */
+typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length);
+
+typedef enum _HTC_SEND_FULL_ACTION {
+    HTC_SEND_FULL_KEEP = 0,  /* packet that overflowed should be kept in the queue */
+    HTC_SEND_FULL_DROP = 1,  /* packet that overflowed should be dropped */
+} HTC_SEND_FULL_ACTION;
+
+/* Optional per service connection callback when a send queue is full. This can occur if the
+ * host continues queueing up TX packets faster than credits can arrive
+ * To prevent the host (on some Oses like Linux) from continuously queueing packets
+ * and consuming resources, this callback is provided so that that the host
+ * can disable TX in the subsystem (i.e. network stack).
+ * This callback is invoked for each packet that "overflows" the HTC queue. The callback can
+ * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or
+ * dropped (HTC_SEND_FULL_DROP).  If a packet is dropped, the EpTxComplete handler will be called
+ * and the packet's status field will be set to A_NO_RESOURCE.
+ * Other OSes require a "per-packet" indication for each completed TX packet, this
+ * closed loop mechanism will prevent the network stack from overunning the NIC
+ * The packet to keep or drop is passed for inspection to the registered handler the handler
+ * must ONLY inspect the packet, it may not free or reclaim the packet. */
+typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket);
+
+typedef struct _HTC_EP_CALLBACKS {
+    void                     *pContext;     /* context for each callback */
+    HTC_EP_SEND_PKT_COMPLETE EpTxComplete;  /* tx completion callback for connected endpoint */
+    HTC_EP_RECV_PKT          EpRecv;        /* receive callback for connected endpoint */
+    HTC_EP_RECV_REFILL       EpRecvRefill;  /* OPTIONAL receive re-fill callback for connected endpoint */
+    HTC_EP_SEND_QUEUE_FULL   EpSendFull;    /* OPTIONAL send full callback */
+    HTC_EP_RECV_ALLOC        EpRecvAlloc;   /* OPTIONAL recv allocation callback */
+    HTC_EP_RECV_ALLOC        EpRecvAllocThresh;  /* OPTIONAL recv allocation callback based on a threshold */
+    HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple; /* OPTIONAL completion handler for multiple complete
+                                                             indications (EpTxComplete must be NULL) */
+    HTC_EP_RECV_PKT_MULTIPLE      EpRecvPktMultiple;      /* OPTIONAL completion handler for multiple
+                                                             recv packet indications (EpRecv must be NULL) */           
+    int                      RecvAllocThreshold;    /* if EpRecvAllocThresh is non-NULL, HTC will compare the 
+                                                       threshold value to the current recv packet length and invoke
+                                                       the EpRecvAllocThresh callback to acquire a packet buffer */
+    int                      RecvRefillWaterMark;   /* if a EpRecvRefill handler is provided, this value
+                                                       can be used to set a trigger refill callback 
+                                                       when the recv queue drops below this value 
+                                                       if set to 0, the refill is only called when packets 
+                                                       are empty */
+} HTC_EP_CALLBACKS;
+
+/* service connection information */
+typedef struct _HTC_SERVICE_CONNECT_REQ {
+    HTC_SERVICE_ID   ServiceID;                 /* service ID to connect to */
+    A_UINT16         ConnectionFlags;           /* connection flags, see htc protocol definition */
+    A_UINT8         *pMetaData;                 /* ptr to optional service-specific meta-data */
+    A_UINT8          MetaDataLength;            /* optional meta data length */
+    HTC_EP_CALLBACKS EpCallbacks;               /* endpoint callbacks */
+    int              MaxSendQueueDepth;         /* maximum depth of any send queue */
+    A_UINT32         LocalConnectionFlags;      /* HTC flags for the host-side (local) connection */
+    unsigned int     MaxSendMsgSize;            /* override max message size in send direction */
+} HTC_SERVICE_CONNECT_REQ;
+
+#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0)  /* enable send bundle padding for this endpoint */
+
+/* service connection response information */
+typedef struct _HTC_SERVICE_CONNECT_RESP {
+    A_UINT8         *pMetaData;         /* caller supplied buffer to optional meta-data */
+    A_UINT8         BufferLength;       /* length of caller supplied buffer */
+    A_UINT8         ActualLength;       /* actual length of meta data */
+    HTC_ENDPOINT_ID Endpoint;           /* endpoint to communicate over */
+    unsigned int    MaxMsgLength;       /* max length of all messages over this endpoint */
+    A_UINT8         ConnectRespCode;    /* connect response code from target */
+} HTC_SERVICE_CONNECT_RESP;
+
+/* endpoint distribution structure */
+typedef struct _HTC_ENDPOINT_CREDIT_DIST {
+    struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
+    struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
+    HTC_SERVICE_ID      ServiceID;          /* Service ID (set by HTC) */
+    HTC_ENDPOINT_ID     Endpoint;           /* endpoint for this distribution struct (set by HTC) */
+    A_UINT32            DistFlags;          /* distribution flags, distribution function can
+                                               set default activity using SET_EP_ACTIVE() macro */
+    int                 TxCreditsNorm;      /* credits for normal operation, anything above this
+                                               indicates the endpoint is over-subscribed, this field
+                                               is only relevant to the credit distribution function */
+    int                 TxCreditsMin;       /* floor for credit distribution, this field is
+                                               only relevant to the credit distribution function */
+    int                 TxCreditsAssigned;  /* number of credits assigned to this EP, this field
+                                               is only relevant to the credit dist function */
+    int                 TxCredits;          /* current credits available, this field is used by
+                                               HTC to determine whether a message can be sent or
+                                               must be queued */
+    int                 TxCreditsToDist;    /* pending credits to distribute on this endpoint, this
+                                               is set by HTC when credit reports arrive.
+                                               The credit distribution functions sets this to zero
+                                               when it distributes the credits */
+    int                 TxCreditsSeek;      /* this is the number of credits that the current pending TX
+                                               packet needs to transmit.  This is set by HTC when
+                                               and endpoint needs credits in order to transmit */
+    int                 TxCreditSize;       /* size in bytes of each credit (set by HTC) */
+    int                 TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
+    void                *pHTCReserved;      /* reserved for HTC use */    
+    int                 TxQueueDepth;       /* current depth of TX queue , i.e. messages waiting for credits
+                                               This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE
+                                               or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint
+                                               that has non-zero credits to recover
+                                              */
+} HTC_ENDPOINT_CREDIT_DIST;
+
+#define HTC_EP_ACTIVE                            ((A_UINT32) (1u << 31))
+
+/* macro to check if an endpoint has gone active, useful for credit
+ * distributions */
+#define IS_EP_ACTIVE(epDist)  ((epDist)->DistFlags & HTC_EP_ACTIVE)
+#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
+
+    /* credit distibution code that is passed into the distrbution function,
+     * there are mandatory and optional codes that must be handled */
+typedef enum _HTC_CREDIT_DIST_REASON {
+    HTC_CREDIT_DIST_SEND_COMPLETE = 0,     /* credits available as a result of completed
+                                              send operations (MANDATORY) resulting in credit reports */
+    HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1,   /* a change in endpoint activity occured (OPTIONAL) */
+    HTC_CREDIT_DIST_SEEK_CREDITS,          /* an endpoint needs to "seek" credits (OPTIONAL) */
+    HTC_DUMP_CREDIT_STATE                  /* for debugging, dump any state information that is kept by
+                                              the distribution function */
+} HTC_CREDIT_DIST_REASON;
+
+typedef void (*HTC_CREDIT_DIST_CALLBACK)(void                     *Context,
+                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                         HTC_CREDIT_DIST_REASON   Reason);
+
+typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
+                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                                         int                      TotalCredits);
+
+    /* endpoint statistics action */
+typedef enum _HTC_ENDPOINT_STAT_ACTION {
+    HTC_EP_STAT_SAMPLE = 0,                /* only read statistics */
+    HTC_EP_STAT_SAMPLE_AND_CLEAR = 1,      /* sample and immediately clear statistics */
+    HTC_EP_STAT_CLEAR                      /* clear only */
+} HTC_ENDPOINT_STAT_ACTION;
+
+    /* endpoint statistics */
+typedef struct _HTC_ENDPOINT_STATS {
+    A_UINT32  TxCreditLowIndications;  /* number of times the host set the credit-low flag in a send message on
+                                        this endpoint */
+    A_UINT32  TxIssued;               /* running count of total TX packets issued */
+    A_UINT32  TxPacketsBundled;       /* running count of TX packets that were issued in bundles */
+    A_UINT32  TxBundles;              /* running count of TX bundles that were issued */
+    A_UINT32  TxDropped;              /* tx packets that were dropped */
+    A_UINT32  TxCreditRpts;           /* running count of total credit reports received for this endpoint */
+    A_UINT32  TxCreditRptsFromRx;     /* credit reports received from this endpoint's RX packets */
+    A_UINT32  TxCreditRptsFromOther;  /* credit reports received from RX packets of other endpoints */
+    A_UINT32  TxCreditRptsFromEp0;    /* credit reports received from endpoint 0 RX packets */
+    A_UINT32  TxCreditsFromRx;        /* count of credits received via Rx packets on this endpoint */
+    A_UINT32  TxCreditsFromOther;     /* count of credits received via another endpoint */
+    A_UINT32  TxCreditsFromEp0;       /* count of credits received via another endpoint */
+    A_UINT32  TxCreditsConsummed;     /* count of consummed credits */
+    A_UINT32  TxCreditsReturned;      /* count of credits returned */
+    A_UINT32  RxReceived;             /* count of RX packets received */
+    A_UINT32  RxLookAheads;           /* count of lookahead records
+                                         found in messages received on this endpoint */
+    A_UINT32  RxPacketsBundled;       /* count of recv packets received in a bundle */                                     
+    A_UINT32  RxBundleLookAheads;     /* count of number of bundled lookaheads */
+    A_UINT32  RxBundleIndFromHdr;     /* count of the number of bundle indications from the HTC header */
+    A_UINT32  RxAllocThreshHit;       /* count of the number of times the recv allocation threshhold was hit */
+    A_UINT32  RxAllocThreshBytes;     /* total number of bytes */
+} HTC_ENDPOINT_STATS;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Create an instance of HTC over the underlying HIF device
+  @function name: HTCCreate
+  @input:  HifDevice - hif device handle,
+           pInfo - initialization information
+  @output:
+  @return: HTC_HANDLE on success, NULL on failure
+  @notes: 
+  @example:
+  @see also: HTCDestroy
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get the underlying HIF device handle
+  @function name: HTCGetHifDevice
+  @input:  HTCHandle - handle passed into the AddInstance callback
+  @output:
+  @return: opaque HIF device handle usable in HIF API calls.
+  @notes:
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void       *HTCGetHifDevice(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Set credit distribution parameters
+  @function name: HTCSetCreditDistribution
+  @input:  HTCHandle - HTC handle
+           pCreditDistCont - caller supplied context to pass into distribution functions
+           CreditDistFunc - Distribution function callback
+           CreditDistInit - Credit Distribution initialization callback
+           ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
+                                  priority
+           ListLength - number of elements in ServicePriorityOrder
+  @output:
+  @return:
+  @notes:  The user can set a custom credit distribution function to handle special requirements
+           for each endpoint.  A default credit distribution routine can be used by setting
+           CreditInitFunc to NULL.  The default credit distribution is only provided for simple
+           "fair" credit distribution without regard to any prioritization.
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
+                                     void                     *pCreditDistContext,
+                                     HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+                                     HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+                                     HTC_SERVICE_ID           ServicePriorityOrder[],
+                                     int                      ListLength);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Wait for the target to indicate the HTC layer is ready
+  @function name: HTCWaitTarget
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:  This API blocks until the target responds with an HTC ready message.
+           The caller should not connect services until the target has indicated it is
+           ready.
+  @example:
+  @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCWaitTarget(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Start target service communications
+  @function name: HTCStart
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes: This API indicates to the target that the service connection phase is complete
+          and the target can freely start all connected services.  This API should only be
+          called AFTER all service connections have been made.  TCStart will issue a
+          SETUP_COMPLETE message to the target to indicate that all service connections
+          have been made and the target can start communicating over the endpoints.
+  @example:
+  @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCStart(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add receive packet to HTC
+  @function name: HTCAddReceivePkt
+  @input:  HTCHandle - HTC handle
+           pPacket - HTC receive packet to add
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Connect to an HTC service
+  @function name: HTCConnectService
+  @input:  HTCHandle - HTC handle
+           pReq - connection details
+  @output: pResp - connection response
+  @return:
+  @notes:  Service connections must be performed before HTCStart.  User provides callback handlers
+           for various endpoint events.
+  @example:
+  @see also: HTCStart
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCConnectService(HTC_HANDLE HTCHandle,
+                              HTC_SERVICE_CONNECT_REQ  *pReq,
+                              HTC_SERVICE_CONNECT_RESP *pResp);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Send an HTC packet
+  @function name: HTCSendPkt
+  @input:  HTCHandle - HTC handle
+           pPacket - packet to send
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
+           This interface is fully asynchronous.  On error, HTC SendPkt will
+           call the registered Endpoint callback to cleanup the packet.
+  @example:
+  @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Stop HTC service communications
+  @function name: HTCStop
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes: HTC communications is halted.  All receive and pending TX packets will
+          be flushed.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCStop(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Destory HTC service
+  @function name: HTCDestroy
+  @input: HTCHandle 
+  @output:
+  @return:
+  @notes:  This cleans up all resources allocated by HTCCreate().
+  @example:
+  @see also: HTCCreate
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCDestroy(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Flush pending TX packets
+  @function name: HTCFlushEndpoint
+  @input:  HTCHandle - HTC handle
+           Endpoint - Endpoint to flush
+           Tag - flush tag
+  @output:
+  @return:
+  @notes:  The Tag parameter is used to selectively flush packets with matching tags.
+           The value of 0 forces all packets to be flush regardless of tag.
+  @example:
+  @see also: HTCSendPkt
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Dump credit distribution state
+  @function name: HTCDumpCreditStates
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:  This dumps all credit distribution information to the debugger
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCDumpCreditStates(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Indicate a traffic activity change on an endpoint
+  @function name: HTCIndicateActivityChange
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint in which activity has changed
+           Active - TRUE if active, FALSE if it has become inactive
+  @output:
+  @return:
+  @notes:  This triggers the registered credit distribution function to
+           re-adjust credits for active/inactive endpoints.
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void        HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
+                                      HTC_ENDPOINT_ID Endpoint,
+                                      A_BOOL          Active);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get endpoint statistics
+  @function name: HTCGetEndpointStatistics
+  @input:  HTCHandle - HTC handle
+           Endpoint - Endpoint identifier
+           Action - action to take with statistics
+  @output:
+           pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
+
+  @return: TRUE if statistics profiling is enabled, otherwise FALSE.
+
+  @notes:  Statistics is a compile-time option and this function may return FALSE
+           if HTC is not compiled with profiling.
+
+           The caller can specify the statistic "action" to take when sampling
+           the statistics.  This includes:
+
+           HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
+           HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
+                             are cleared.
+           HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
+                   pStats
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL       HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
+                                      HTC_ENDPOINT_ID          Endpoint,
+                                      HTC_ENDPOINT_STAT_ACTION Action,
+                                      HTC_ENDPOINT_STATS       *pStats);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Unblock HTC message reception
+  @function name: HTCUnblockRecv
+  @input:  HTCHandle - HTC handle
+  @output:
+  @return:
+  @notes:
+           HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet.
+           The caller can use this API to indicate to HTC when resources (buffers) are available
+           such that the  receiver can be unblocked and HTC may re-attempt fetching the pending message.
+
+           This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket()
+           API to recycle or provide receive packets to HTC.
+
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCUnblockRecv(HTC_HANDLE HTCHandle);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: send a series of HTC packets  
+  @function name: HTCSendPktsMultiple
+  @input:  HTCHandle - HTC handle
+           pPktQueue - local queue holding packets to send
+  @output:
+  @return: A_OK
+  @notes:  Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro.
+           The queue must only contain packets directed at the same endpoint.
+           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the TX packets in FIFO order.
+           This API will remove the packets from the pkt queue and place them into the HTC Tx Queue
+           and bundle messages where possible.
+           The caller may allocate the pkt queue on the stack to hold the packets.           
+           This interface is fully asynchronous.  On error, HTCSendPkts will
+           call the registered Endpoint callback to cleanup the packet.
+  @example:
+  @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Add multiple receive packets to HTC
+  @function name: HTCAddReceivePktMultiple
+  @input:  HTCHandle - HTC handle
+           pPktQueue - HTC receive packet queue holding packets to add
+  @output:
+  @return: A_OK on success
+  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
+           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+           macro. The queue must only contain recv packets for the same endpoint.
+           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the recv packet.
+           This API will remove the packets from the pkt queue and place them into internal
+           recv packet list.
+           The caller may allocate the pkt queue on the stack to hold the packets.           
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS    HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Check if an endpoint is marked active
+  @function name: HTCIsEndpointActive
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint to check for active state
+  @output:
+  @return: returns TRUE if Endpoint is Active
+  @notes:  
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL      HTCIsEndpointActive(HTC_HANDLE      HTCHandle,
+                                HTC_ENDPOINT_ID Endpoint);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  @desc: Get the number of recv buffers currently queued into an HTC endpoint
+  @function name: HTCGetNumRecvBuffers
+  @input:  HTCHandle - HTC handle
+           Endpoint - endpoint to check
+  @output:
+  @return: returns number of buffers in queue
+  @notes:  
+  @example:
+  @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+int         HTCGetNumRecvBuffers(HTC_HANDLE      HTCHandle,
+                                 HTC_ENDPOINT_ID Endpoint);
+                                                                      
+/* internally used functions for testing... */
+void HTCEnableRecv(HTC_HANDLE HTCHandle);
+void HTCDisableRecv(HTC_HANDLE HTCHandle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/htc_packet.h b/drivers/net/wireless/ath6kl/include/htc_packet.h
new file mode 100644
index 000000000000..26b20f2183f3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_packet.h
@@ -0,0 +1,223 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_packet.h" company="Atheros">
+//    Copyright (c) 2007-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_PACKET_H_
+#define HTC_PACKET_H_
+
+
+#include "dl_list.h"
+
+/* ------ Endpoint IDS ------ */
+typedef enum
+{
+    ENDPOINT_UNUSED = -1,
+    ENDPOINT_0 = 0,
+    ENDPOINT_1 = 1,
+    ENDPOINT_2 = 2,
+    ENDPOINT_3,
+    ENDPOINT_4,
+    ENDPOINT_5,
+    ENDPOINT_6,
+    ENDPOINT_7,
+    ENDPOINT_8,
+    ENDPOINT_MAX,
+} HTC_ENDPOINT_ID;
+
+struct _HTC_PACKET;
+
+typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
+
+typedef A_UINT16 HTC_TX_TAG;
+
+typedef struct _HTC_TX_PACKET_INFO {
+    HTC_TX_TAG    Tag;            /* tag used to selective flush packets */
+    int           CreditsUsed;    /* number of credits used for this TX packet (HTC internal) */
+    A_UINT8       SendFlags;      /* send flags (HTC internal) */
+    int           SeqNo;          /* internal seq no for debugging (HTC internal) */
+} HTC_TX_PACKET_INFO;
+
+#define HTC_TX_PACKET_TAG_ALL          0    /* a tag of zero is reserved and used to flush ALL packets */
+#define HTC_TX_PACKET_TAG_INTERNAL     1                                /* internal tags start here */
+#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
+
+typedef struct _HTC_RX_PACKET_INFO {
+    A_UINT32    ExpectedHdr;        /* HTC internal use */
+    A_UINT32    HTCRxFlags;         /* HTC internal use */
+    A_UINT32    IndicationFlags;    /* indication flags set on each RX packet indication */
+} HTC_RX_PACKET_INFO;
+
+#define HTC_RX_FLAGS_INDICATE_MORE_PKTS  (1 << 0)   /* more packets on this endpoint are being fetched */
+
+/* wrapper around endpoint-specific packets */
+typedef struct _HTC_PACKET {
+    DL_LIST         ListLink;       /* double link */
+    void            *pPktContext;   /* caller's per packet specific context */
+
+    A_UINT8         *pBufferStart;  /* the true buffer start , the caller can
+                                       store the real buffer start here.  In
+                                       receive callbacks, the HTC layer sets pBuffer
+                                       to the start of the payload past the header. This
+                                       field allows the caller to reset pBuffer when it
+                                       recycles receive packets back to HTC */
+    /*
+     * Pointer to the start of the buffer. In the transmit
+     * direction this points to the start of the payload. In the
+     * receive direction, however, the buffer when queued up
+     * points to the start of the HTC header but when returned
+     * to the caller points to the start of the payload
+     */
+    A_UINT8         *pBuffer;       /* payload start (RX/TX) */
+    A_UINT32        BufferLength;   /* length of buffer */
+    A_UINT32        ActualLength;   /* actual length of payload */
+    HTC_ENDPOINT_ID Endpoint;       /* endpoint that this packet was sent/recv'd from */
+    A_STATUS        Status;         /* completion status */
+    union {
+        HTC_TX_PACKET_INFO  AsTx;   /* Tx Packet specific info */
+        HTC_RX_PACKET_INFO  AsRx;   /* Rx Packet specific info */
+    } PktInfo;
+
+    /* the following fields are for internal HTC use */
+    HTC_PACKET_COMPLETION Completion;   /* completion */
+    void                  *pContext;    /* HTC private completion context */
+} HTC_PACKET;
+
+
+
+#define COMPLETE_HTC_PACKET(p,status)        \
+{                                            \
+    (p)->Status = (status);                  \
+    (p)->Completion((p)->pContext,(p));      \
+}
+
+#define INIT_HTC_PACKET_INFO(p,b,len)             \
+{                                                 \
+    (p)->pBufferStart = (b);                      \
+    (p)->BufferLength = (len);                    \
+}
+
+/* macro to set an initial RX packet for refilling HTC */
+#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
+{                                                 \
+    (p)->pPktContext = (c);                       \
+    (p)->pBuffer = (b);                           \
+    (p)->pBufferStart = (b);                      \
+    (p)->BufferLength = (len);                    \
+    (p)->Endpoint = (ep);                         \
+}
+
+/* fast macro to recycle an RX packet that will be re-queued to HTC */
+#define HTC_PACKET_RESET_RX(p)              \
+    { (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; }  
+
+/* macro to set packet parameters for TX */
+#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag)  \
+{                                                 \
+    (p)->pPktContext = (c);                       \
+    (p)->pBuffer = (b);                           \
+    (p)->ActualLength = (len);                    \
+    (p)->Endpoint = (ep);                         \
+    (p)->PktInfo.AsTx.Tag = (tag);                \
+}
+
+/* HTC Packet Queueing Macros */
+typedef struct _HTC_PACKET_QUEUE {
+    DL_LIST     QueueHead;
+    int         Depth;    
+} HTC_PACKET_QUEUE;
+ 
+/* initialize queue */
+#define INIT_HTC_PACKET_QUEUE(pQ)   \
+{                                   \
+    DL_LIST_INIT(&(pQ)->QueueHead); \
+    (pQ)->Depth = 0;                \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE(pQ,p)                        \
+{   DL_ListInsertTail(&(pQ)->QueueHead,&(p)->ListLink); \
+    (pQ)->Depth++;                                      \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p)                \
+{   DL_ListInsertHead(&(pQ)->QueueHead,&(p)->ListLink); \
+    (pQ)->Depth++;                                      \
+}
+/* test if a queue is empty */
+#define HTC_QUEUE_EMPTY(pQ)       ((pQ)->Depth == 0)
+/* get packet at head without removing it */
+static INLINE HTC_PACKET *HTC_GET_PKT_AT_HEAD(HTC_PACKET_QUEUE *queue)   {
+    if (queue->Depth == 0) {
+        return NULL; 
+    }  
+    return A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),HTC_PACKET,ListLink);
+}
+/* remove a packet from a queue, where-ever it is in the queue */
+#define HTC_PACKET_REMOVE(pQ,p)     \
+{                                   \
+    DL_ListRemove(&(p)->ListLink);  \
+    (pQ)->Depth--;                  \
+}
+
+/* dequeue an HTC packet from the head of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
+    DL_LIST    *pItem = DL_ListRemoveItemFromHead(&queue->QueueHead);
+    if (pItem != NULL) {
+        queue->Depth--;
+        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+    }
+    return NULL;
+}
+
+/* dequeue an HTC packet from the tail of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE_TAIL(HTC_PACKET_QUEUE *queue) {
+    DL_LIST    *pItem = DL_ListRemoveItemFromTail(&queue->QueueHead);
+    if (pItem != NULL) {
+        queue->Depth--;
+        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+    }
+    return NULL;
+}
+
+#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth
+
+
+#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint
+#define HTC_GET_TAG_FROM_PKT(p)      (p)->PktInfo.AsTx.Tag
+
+    /* transfer the packets from one queue to the tail of another queue */
+#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc) \
+{                                                                           \
+    DL_ListTransferItemsToTail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead);   \
+    (pQDest)->Depth += (pQSrc)->Depth;                                      \
+    (pQSrc)->Depth = 0;                                                     \
+}
+
+    /* fast version to init and add a single packet to a queue */
+#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \
+{                                            \
+    DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink)  \
+    (pQ)->Depth = 1;                                        \
+}
+    
+#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \
+    ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), HTC_PACKET, ListLink) 
+
+#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END
+        
+#endif /*HTC_PACKET_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/htc_services.h b/drivers/net/wireless/ath6kl/include/htc_services.h
new file mode 100644
index 000000000000..4457d6634f26
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_services.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.h" company="Atheros">
+//    Copyright (c) 2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_SERVICES_H__
+#define __HTC_SERVICES_H__
+
+/* Current service IDs */
+
+typedef enum {
+    RSVD_SERVICE_GROUP  = 0,
+    WMI_SERVICE_GROUP   = 1, 
+    
+    HTC_TEST_GROUP = 254,
+    HTC_SERVICE_GROUP_LAST = 255
+}HTC_SERVICE_GROUP_IDS;
+
+#define MAKE_SERVICE_ID(group,index) \
+            (int)(((int)group << 8) | (int)(index))
+
+/* NOTE: service ID of 0x0000 is reserved and should never be used */
+#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
+#define WMI_CONTROL_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
+#define WMI_DATA_BE_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_DATA_BK_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_DATA_VI_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
+#define WMI_DATA_VO_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
+#define WMI_MAX_SERVICES  5
+
+/* raw stream service (i.e. flash, tcmd, calibration apps) */
+#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
+
+#endif /*HTC_SERVICES_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ini_dset.h b/drivers/net/wireless/ath6kl/include/ini_dset.h
new file mode 100644
index 000000000000..fcd5a68fdac3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ini_dset.h
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------
+// <copyright file="ini_dset.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _INI_DSET_H_
+#define _INI_DSET_H_
+
+/*
+ * Each of these represents a WHAL INI table, which consists
+ * of an "address column" followed by 1 or more "value columns".
+ *
+ * Software uses the base WHAL_INI_DATA_ID+column to access a
+ * DataSet that holds a particular column of data.
+ */
+typedef enum {
+#if defined(AR6002_REV4) || defined(AR6003)
+/* Add these definitions for compatability  */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
+    WHAL_INI_DATA_ID_NULL               =0,
+    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3,4,5 */
+    WHAL_INI_DATA_ID_COMMON             =6,  /* 7 */
+    WHAL_INI_DATA_ID_BB_RFGAIN          =8,  /* 9,10 */
+#ifdef FPGA
+    WHAL_INI_DATA_ID_ANALOG_BANK0       =11, /* 12 */
+    WHAL_INI_DATA_ID_ANALOG_BANK1       =13, /* 14 */
+    WHAL_INI_DATA_ID_ANALOG_BANK2       =15, /* 16 */
+    WHAL_INI_DATA_ID_ANALOG_BANK3       =17, /* 18, 19 */
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =20, /* 21,22 */
+    WHAL_INI_DATA_ID_ANALOG_BANK7       =23, /* 24 */
+    WHAL_INI_DATA_ID_ADDAC              =25, /* 26 */
+#else
+    WHAL_INI_DATA_ID_ANALOG_COMMON      =11, /* 12 */ 
+    WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ 
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17,18 */
+    WHAL_INI_DATA_ID_MODE_OVERRIDES     =19, /* 20,21,22,23 */
+    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
+    WHAL_INI_DATA_ID_ANALOG_OVERRIDES   =26, /* 27,28 */
+#endif /* FPGA */
+#else
+    WHAL_INI_DATA_ID_NULL               =0,
+    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3 */
+    WHAL_INI_DATA_ID_COMMON             =4,  /* 5 */
+    WHAL_INI_DATA_ID_BB_RFGAIN          =6,  /* 7,8 */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+    WHAL_INI_DATA_ID_ANALOG_BANK1       =9,  /* 10 */
+    WHAL_INI_DATA_ID_ANALOG_BANK2       =11, /* 12 */
+    WHAL_INI_DATA_ID_ANALOG_BANK3       =13, /* 14, 15 */
+    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17, 18 */
+    WHAL_INI_DATA_ID_ANALOG_BANK7       =19, /* 20 */
+    WHAL_INI_DATA_ID_MODE_OVERRIDES     =21, /* 22,23 */
+    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
+    WHAL_INI_DATA_ID_ANALOG_OVERRIDES   =26, /* 27,28 */
+    WHAL_INI_DATA_ID_BB_RFGAIN_LNA2     =29, /* 30,31 */
+#endif
+    WHAL_INI_DATA_ID_MAX                =31
+} WHAL_INI_DATA_ID;
+
+typedef PREPACK struct {
+    A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
+    A_UINT16 offset;
+    A_UINT32 newValue;
+} POSTPACK INI_DSET_REG_OVERRIDE;
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/pkt_log.h b/drivers/net/wireless/ath6kl/include/pkt_log.h
new file mode 100644
index 000000000000..1fcc1cb2750a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/pkt_log.h
@@ -0,0 +1,41 @@
+//------------------------------------------------------------------------------
+//    Copyright (c) 2005 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __PKT_LOG_H__
+#define __PKT_LOG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Pkt log info */
+typedef PREPACK struct pkt_log_t {
+    struct info_t {
+        A_UINT16    st;
+        A_UINT16    end;
+        A_UINT16    cur;
+    }info[4096];
+    A_UINT16    last_idx;
+}POSTPACK PACKET_LOG;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif  /* __PKT_LOG_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/regdump.h b/drivers/net/wireless/ath6kl/include/regdump.h
new file mode 100644
index 000000000000..09755cd2874d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/regdump.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// <copyright file="regdump.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __REGDUMP_H__
+#define __REGDUMP_H__
+#if defined(AR6001)
+#include "AR6001/AR6001_regdump.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/AR6002_regdump.h"
+#endif
+
+#if !defined(__ASSEMBLER__)
+/*
+ * Target CPU state at the time of failure is reflected
+ * in a register dump, which the Host can fetch through
+ * the diagnostic window.
+ */
+struct register_dump_s {
+    A_UINT32 target_id;               /* Target ID */
+    A_UINT32 assline;                 /* Line number (if assertion failure) */
+    A_UINT32 pc;                      /* Program Counter at time of exception */
+    A_UINT32 badvaddr;                /* Virtual address causing exception */
+    CPU_exception_frame_t exc_frame;  /* CPU-specific exception info */
+
+    /* Could copy top of stack here, too.... */
+};
+#endif /* __ASSEMBLER__ */
+#endif /* __REGDUMP_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/roaming.h b/drivers/net/wireless/ath6kl/include/roaming.h
new file mode 100644
index 000000000000..88c1bd278490
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/roaming.h
@@ -0,0 +1,37 @@
+//------------------------------------------------------------------------------
+// <copyright file="roaming.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _ROAMING_H_
+#define _ROAMING_H_
+
+/* 
+ * The signal quality could be in terms of either snr or rssi. We should 
+ * have an enum for both of them. For the time being, we are going to move 
+ * it to wmi.h that is shared by both host and the target, since we are 
+ * repartitioning the code to the host 
+ */
+#define SIGNAL_QUALITY_NOISE_FLOOR        -96
+#define SIGNAL_QUALITY_METRICS_NUM_MAX    2
+typedef enum {
+    SIGNAL_QUALITY_METRICS_SNR = 0,
+    SIGNAL_QUALITY_METRICS_RSSI,
+    SIGNAL_QUALITY_METRICS_ALL,
+} SIGNAL_QUALITY_METRICS_TYPE;
+
+#endif  /* _ROAMING_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/targaddrs.h b/drivers/net/wireless/ath6kl/include/targaddrs.h
new file mode 100644
index 000000000000..7b27ca2a78fe
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/targaddrs.h
@@ -0,0 +1,232 @@
+//------------------------------------------------------------------------------
+// <copyright file="targaddrs.h" company="Atheros">
+//    Copyright (c) 2010 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __TARGADDRS_H__
+#define __TARGADDRS_H__
+#if defined(AR6001)
+#include "AR6001/addrs.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/addrs.h"
+#endif
+
+/*
+ * AR6K option bits, to enable/disable various features.
+ * By default, all option bits are 0.
+ * These bits can be set in LOCAL_SCRATCH register 0.
+ */
+#define AR6K_OPTION_BMI_DISABLE      0x01 /* Disable BMI comm with Host */
+#define AR6K_OPTION_SERIAL_ENABLE    0x02 /* Enable serial port msgs */
+#define AR6K_OPTION_WDT_DISABLE      0x04 /* WatchDog Timer override */
+#define AR6K_OPTION_SLEEP_DISABLE    0x08 /* Disable system sleep */
+#define AR6K_OPTION_STOP_BOOT        0x10 /* Stop boot processes (for ATE) */
+#define AR6K_OPTION_ENABLE_NOANI     0x20 /* Operate without ANI */
+#define AR6K_OPTION_DSET_DISABLE     0x40 /* Ignore DataSets */
+#define AR6K_OPTION_IGNORE_FLASH     0x80 /* Ignore flash during bootup */
+
+/*
+ * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
+ * host_interest structure.  It must match the address of the _host_interest
+ * symbol (see linker script).
+ *
+ * Host Interest is shared between Host and Target in order to coordinate
+ * between the two, and is intended to remain constant (with additions only
+ * at the end) across software releases.
+ *
+ * All addresses are available here so that it's possible to
+ * write a single binary that works with all Target Types.
+ * May be used in assembler code as well as C.
+ */
+#define AR6001_HOST_INTEREST_ADDRESS    0x80000600
+#define AR6002_HOST_INTEREST_ADDRESS    0x00500400
+#define AR6003_HOST_INTEREST_ADDRESS    0x00540600
+
+
+#define HOST_INTEREST_MAX_SIZE          0x100
+
+#if !defined(__ASSEMBLER__)
+struct register_dump_s;
+struct dbglog_hdr_s;
+
+/*
+ * These are items that the Host may need to access
+ * via BMI or via the Diagnostic Window. The position
+ * of items in this structure must remain constant
+ * across firmware revisions!
+ *
+ * Types for each item must be fixed size across
+ * target and host platforms.
+ *
+ * More items may be added at the end.
+ */
+struct host_interest_s {
+    /*
+     * Pointer to application-defined area, if any.
+     * Set by Target application during startup.
+     */
+    A_UINT32               hi_app_host_interest;                      /* 0x00 */
+
+    /* Pointer to register dump area, valid after Target crash. */
+    A_UINT32               hi_failure_state;                          /* 0x04 */
+
+    /* Pointer to debug logging header */
+    A_UINT32               hi_dbglog_hdr;                             /* 0x08 */
+
+    /* Indicates whether or not flash is present on Target.
+     * NB: flash_is_present indicator is here not just
+     * because it might be of interest to the Host; but
+     * also because it's set early on by Target's startup
+     * asm code and we need it to have a special RAM address
+     * so that it doesn't get reinitialized with the rest
+     * of data.
+     */
+    A_UINT32               hi_flash_is_present;                       /* 0x0c */
+
+    /*
+     * General-purpose flag bits, similar to AR6000_OPTION_* flags.
+     * Can be used by application rather than by OS.
+     */
+    A_UINT32               hi_option_flag;                            /* 0x10 */
+
+    /*
+     * Boolean that determines whether or not to
+     * display messages on the serial port.
+     */
+    A_UINT32               hi_serial_enable;                          /* 0x14 */
+
+    /* Start address of Flash DataSet index, if any */
+    A_UINT32               hi_dset_list_head;                         /* 0x18 */
+
+    /* Override Target application start address */
+    A_UINT32               hi_app_start;                              /* 0x1c */
+
+    /* Clock and voltage tuning */
+    A_UINT32               hi_skip_clock_init;                        /* 0x20 */
+    A_UINT32               hi_core_clock_setting;                     /* 0x24 */
+    A_UINT32               hi_cpu_clock_setting;                      /* 0x28 */
+    A_UINT32               hi_system_sleep_setting;                   /* 0x2c */
+    A_UINT32               hi_xtal_control_setting;                   /* 0x30 */
+    A_UINT32               hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
+    A_UINT32               hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
+    A_UINT32               hi_ref_voltage_trim_setting;               /* 0x3c */
+    A_UINT32               hi_clock_info;                             /* 0x40 */
+
+    /*
+     * Flash configuration overrides, used only
+     * when firmware is not executing from flash.
+     * (When using flash, modify the global variables
+     * with equivalent names.)
+     */
+    A_UINT32               hi_bank0_addr_value;                       /* 0x44 */
+    A_UINT32               hi_bank0_read_value;                       /* 0x48 */
+    A_UINT32               hi_bank0_write_value;                      /* 0x4c */
+    A_UINT32               hi_bank0_config_value;                     /* 0x50 */
+
+    /* Pointer to Board Data  */
+    A_UINT32               hi_board_data;                             /* 0x54 */
+    A_UINT32               hi_board_data_initialized;                 /* 0x58 */
+
+    A_UINT32               hi_dset_RAM_index_table;                   /* 0x5c */
+
+    A_UINT32               hi_desired_baud_rate;                      /* 0x60 */
+    A_UINT32               hi_dbglog_config;                          /* 0x64 */
+    A_UINT32               hi_end_RAM_reserve_sz;                     /* 0x68 */
+    A_UINT32               hi_mbox_io_block_sz;                       /* 0x6c */
+
+    A_UINT32               hi_num_bpatch_streams;                     /* 0x70 -- unused */
+    A_UINT32               hi_mbox_isr_yield_limit;                   /* 0x74 */
+
+    A_UINT32               hi_refclk_hz;                              /* 0x78 */
+    A_UINT32               hi_ext_clk_detected;                       /* 0x7c */
+    A_UINT32               hi_dbg_uart_txpin;                         /* 0x80 */
+    A_UINT32               hi_dbg_uart_rxpin;                         /* 0x84 */
+    A_UINT32               hi_hci_uart_baud;                          /* 0x88 */
+    A_UINT32               hi_hci_uart_pin_assignments;               /* 0x8C */
+        /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
+    A_UINT32               hi_hci_uart_baud_scale_val;                /* 0x90 */
+    A_UINT32               hi_hci_uart_baud_step_val;                 /* 0x94 */
+
+    A_UINT32               hi_allocram_start;                         /* 0x98 */
+    A_UINT32               hi_allocram_sz;                            /* 0x9c */
+    A_UINT32               hi_hci_bridge_flags;                       /* 0xa0 */
+    A_UINT32               hi_hci_uart_support_pins;                  /* 0xa4 */
+        /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
+};
+
+/* Bits defined in hi_option_flag */
+#define HI_OPTION_TIMER_WAR       0x01 /* Enable timer workaround */
+#define HI_OPTION_BMI_CRED_LIMIT  0x02 /* Limit BMI command credits */
+#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
+#define HI_OPTION_FW_MODE_LSB     0x08 /* low bit of MODE (see below) */
+#define HI_OPTION_FW_MODE_MSB     0x10 /* high bit of MODE (see below) */
+#define HI_OPTION_ENABLE_PROFILE  0x20 /* Enable CPU profiling */
+#define HI_OPTION_DISABLE_DBGLOG  0x40 /* Disable debug logging */
+#define HI_OPTION_SKIP_ERA_TRACKING  0x80 /* Skip Era Tracking */
+
+/* 2 bits of hi_option_flag are used to represent 3 modes */
+#define HI_OPTION_FW_MODE_IBSS    0x0 /* IBSS Mode */
+#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
+#define HI_OPTION_FW_MODE_AP      0x2 /* AP Mode */
+
+/* Fw Mode Mask */
+#define HI_OPTION_FW_MODE_MASK    0x3
+#define HI_OPTION_FW_MODE_SHIFT   0x3
+
+/*
+ * Intended for use by Host software, this macro returns the Target RAM
+ * address of any item in the host_interest structure.
+ * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
+ */
+#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \
+    ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
+    ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
+    ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
+
+#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
+        (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
+
+#define HOST_INTEREST_PROFILE_IS_ENABLED() \
+        (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
+
+/* Convert a Target virtual address into a Target physical address */
+#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff)
+#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define TARG_VTOP(TargetType, vaddr) \
+        (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \
+        (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr)))
+
+/* override REV2 ROM's app start address */
+#define AR6002_REV2_APP_START_OVERRIDE    0x911A00
+#define AR6003_REV1_APP_START_OVERRIDE    0x944c00
+#define AR6003_REV1_OTP_DATA_ADDRESS      0x542800
+#define AR6003_REV2_APP_START_OVERRIDE    0x945000
+#define AR6003_REV2_OTP_DATA_ADDRESS      0x543800
+
+
+/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
+#define AR6003_FETCH_TARG_REGS_COUNT 64
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __TARGADDRS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/target_reg_table.h b/drivers/net/wireless/ath6kl/include/target_reg_table.h
new file mode 100644
index 000000000000..4105b9c418cf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/target_reg_table.h
@@ -0,0 +1,236 @@
+//------------------------------------------------------------------------------
+// <copyright file="target_reg_table.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Target register table macros and structure definitions
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef TARGET_REG_TABLE_H_
+#define TARGET_REG_TABLE_H_
+
+#include "targaddrs.h"
+
+/*** WARNING : Add to the end of the TABLE! do not change the order ****/
+typedef struct targetdef_s {
+    A_UINT32 d_RTC_BASE_ADDRESS;
+    A_UINT32 d_SYSTEM_SLEEP_OFFSET;
+    A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB;
+    A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK;
+    A_UINT32 d_CLOCK_CONTROL_OFFSET;
+    A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
+    A_UINT32 d_RESET_CONTROL_OFFSET;
+    A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
+    A_UINT32 d_GPIO_BASE_ADDRESS;
+    A_UINT32 d_GPIO_PIN0_OFFSET;
+    A_UINT32 d_GPIO_PIN1_OFFSET;
+    A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
+    A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
+    A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
+    A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
+    A_UINT32 d_SI_CONFIG_I2C_LSB;
+    A_UINT32 d_SI_CONFIG_I2C_MASK;
+    A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
+    A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
+    A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
+    A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
+    A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
+    A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
+    A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
+    A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
+    A_UINT32 d_SI_BASE_ADDRESS;
+    A_UINT32 d_SI_CONFIG_OFFSET;
+    A_UINT32 d_SI_TX_DATA0_OFFSET;
+    A_UINT32 d_SI_TX_DATA1_OFFSET;
+    A_UINT32 d_SI_RX_DATA0_OFFSET;
+    A_UINT32 d_SI_RX_DATA1_OFFSET;
+    A_UINT32 d_SI_CS_OFFSET;
+    A_UINT32 d_SI_CS_DONE_ERR_MASK;
+    A_UINT32 d_SI_CS_DONE_INT_MASK;
+    A_UINT32 d_SI_CS_START_LSB;
+    A_UINT32 d_SI_CS_START_MASK;
+    A_UINT32 d_SI_CS_RX_CNT_LSB;
+    A_UINT32 d_SI_CS_RX_CNT_MASK;
+    A_UINT32 d_SI_CS_TX_CNT_LSB;
+    A_UINT32 d_SI_CS_TX_CNT_MASK;
+    A_UINT32 d_BOARD_DATA_SZ;
+} TARGET_REGISTER_TABLE;
+
+#define BOARD_DATA_SZ_MAX 2048
+
+#if defined(MY_TARGET_DEF) /* { */
+
+#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
+
+static struct targetdef_s my_target_def = {
+    RTC_BASE_ADDRESS,
+    SYSTEM_SLEEP_OFFSET,
+    SYSTEM_SLEEP_DISABLE_LSB,
+    SYSTEM_SLEEP_DISABLE_MASK,
+    CLOCK_CONTROL_OFFSET,
+    CLOCK_CONTROL_SI0_CLK_MASK,
+    RESET_CONTROL_OFFSET,
+    RESET_CONTROL_SI0_RST_MASK,
+    GPIO_BASE_ADDRESS,
+    GPIO_PIN0_OFFSET,
+    GPIO_PIN0_CONFIG_MASK,
+    GPIO_PIN1_OFFSET,
+    GPIO_PIN1_CONFIG_MASK,
+    SI_CONFIG_BIDIR_OD_DATA_LSB,
+    SI_CONFIG_BIDIR_OD_DATA_MASK,
+    SI_CONFIG_I2C_LSB,
+    SI_CONFIG_I2C_MASK,
+    SI_CONFIG_POS_SAMPLE_LSB,
+    SI_CONFIG_POS_SAMPLE_MASK,
+    SI_CONFIG_INACTIVE_CLK_LSB,
+    SI_CONFIG_INACTIVE_CLK_MASK,
+    SI_CONFIG_INACTIVE_DATA_LSB,
+    SI_CONFIG_INACTIVE_DATA_MASK,
+    SI_CONFIG_DIVIDER_LSB,
+    SI_CONFIG_DIVIDER_MASK,
+    SI_BASE_ADDRESS,
+    SI_CONFIG_OFFSET,
+    SI_TX_DATA0_OFFSET,
+    SI_TX_DATA1_OFFSET,
+    SI_RX_DATA0_OFFSET,
+    SI_RX_DATA1_OFFSET,
+    SI_CS_OFFSET,
+    SI_CS_DONE_ERR_MASK,
+    SI_CS_DONE_INT_MASK,
+    SI_CS_START_LSB,
+    SI_CS_START_MASK,
+    SI_CS_RX_CNT_LSB,
+    SI_CS_RX_CNT_MASK,
+    SI_CS_TX_CNT_LSB,
+    SI_CS_TX_CNT_MASK,
+    MY_TARGET_BOARD_DATA_SZ,
+};
+
+#else
+
+static struct targetdef_s my_target_def = {
+    .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
+    .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
+    .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
+    .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
+    .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
+    .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
+    .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
+    .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
+    .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
+    .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
+    .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
+    .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
+    .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
+    .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
+    .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
+    .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
+    .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
+    .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
+    .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
+    .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
+    .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
+    .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
+    .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
+    .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
+    .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
+    .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
+    .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
+    .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
+    .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
+    .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
+    .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
+    .d_SI_CS_OFFSET = SI_CS_OFFSET,
+    .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
+    .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
+    .d_SI_CS_START_LSB = SI_CS_START_LSB,
+    .d_SI_CS_START_MASK = SI_CS_START_MASK,
+    .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
+    .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
+    .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
+    .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
+    .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
+};
+
+#endif
+
+#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
+#error "BOARD_DATA_SZ_MAX is too small"
+#endif
+
+struct targetdef_s *MY_TARGET_DEF = &my_target_def;
+
+#else /* } { */
+
+#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
+#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
+#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
+#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
+#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
+#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
+#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
+#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
+#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
+#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
+#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
+#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
+#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
+#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
+#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
+#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
+#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
+#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
+#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
+#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
+#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
+#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
+#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
+
+/* SET macros */
+#define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#endif /* } */
+
+#endif /*TARGET_REG_TABLE_H_*/
+
+
diff --git a/drivers/net/wireless/ath6kl/include/testcmd.h b/drivers/net/wireless/ath6kl/include/testcmd.h
new file mode 100644
index 000000000000..49f2cf380296
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/testcmd.h
@@ -0,0 +1,179 @@
+//------------------------------------------------------------------------------
+// <copyright file="testcmd.h" company="Atheros">
+//    Copyright (c) 2004-2005 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef  TESTCMD_H_
+#define  TESTCMD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AR6002_REV2
+#define TCMD_MAX_RATES 12
+#else
+#define TCMD_MAX_RATES 28
+#endif
+
+typedef enum {
+    ZEROES_PATTERN = 0,
+    ONES_PATTERN,
+    REPEATING_10,
+    PN7_PATTERN,
+    PN9_PATTERN,
+    PN15_PATTERN
+}TX_DATA_PATTERN;
+
+/* Continous tx
+   mode : TCMD_CONT_TX_OFF - Disabling continous tx
+          TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
+          TCMD_CONT_TX_FRAME- Enable continuous modulated tx
+   freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
+dataRate: 0 - 1 Mbps
+          1 - 2 Mbps
+          2 - 5.5 Mbps
+          3 - 11 Mbps
+          4 - 6 Mbps
+          5 - 9 Mbps
+          6 - 12 Mbps
+          7 - 18 Mbps
+          8 - 24 Mbps
+          9 - 36 Mbps
+         10 - 28 Mbps
+         11 - 54 Mbps
+  txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
+antenna:  1 - one antenna
+          2 - two antenna
+Note : Enable/disable continuous tx test cmd works only when target is awake.
+*/
+
+typedef enum {
+    TCMD_CONT_TX_OFF = 0,
+    TCMD_CONT_TX_SINE,
+    TCMD_CONT_TX_FRAME,
+    TCMD_CONT_TX_TX99,
+    TCMD_CONT_TX_TX100
+} TCMD_CONT_TX_MODE;
+
+typedef enum {
+    TCMD_WLAN_MODE_HT20 = 0,
+    TCMD_WLAN_MODE_HT40PLUS = 1,
+    TCMD_WLAN_MODE_HT40MINUS = 2,
+} TCMD_WLAN_MODE;
+
+typedef PREPACK struct {
+    A_UINT32                testCmdId;
+    A_UINT32                mode;
+    A_UINT32                freq;
+    A_UINT32                dataRate;
+    A_INT32                 txPwr;
+    A_UINT32                antenna;
+    A_UINT32                enANI;
+    A_UINT32                scramblerOff;
+    A_UINT32                aifsn;
+    A_UINT16                pktSz;
+    A_UINT16                txPattern;
+    A_UINT32                shortGuard;
+    A_UINT32                numPackets;
+    A_UINT32                wlanMode;
+} POSTPACK TCMD_CONT_TX;
+
+#define TCMD_TXPATTERN_ZERONE                 0x1
+#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE    0x2
+
+/* Continuous Rx
+ act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
+      TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
+                                             address equal specified
+                                             mac address (set via act =3)
+      TCMD_CONT_RX_REPORT  off mode  (disable cont rx mode and get the
+                                          report from the last cont
+                                          Rx test)
+
+     TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
+                                                 target. This Overrides
+                                                 the default MAC address.)
+
+*/
+typedef enum {
+    TCMD_CONT_RX_PROMIS =0,
+    TCMD_CONT_RX_FILTER,
+    TCMD_CONT_RX_REPORT,
+    TCMD_CONT_RX_SETMAC,
+    TCMD_CONT_RX_SET_ANT_SWITCH_TABLE
+} TCMD_CONT_RX_ACT;
+
+typedef PREPACK struct {
+    A_UINT32         testCmdId;
+    A_UINT32        act;
+    A_UINT32        enANI;
+    PREPACK union {
+        struct PREPACK TCMD_CONT_RX_PARA {
+            A_UINT32    freq;
+            A_UINT32    antenna;
+            A_UINT32    wlanMode;
+        } POSTPACK para;
+        struct PREPACK TCMD_CONT_RX_REPORT {
+            A_UINT32    totalPkt;
+            A_INT32     rssiInDBm;
+            A_UINT32    crcErrPkt;
+            A_UINT32    secErrPkt;
+            A_UINT16    rateCnt[TCMD_MAX_RATES];
+            A_UINT16    rateCntShortGuard[TCMD_MAX_RATES];
+        } POSTPACK report;
+        struct PREPACK TCMD_CONT_RX_MAC {
+            A_UCHAR    addr[ATH_MAC_LEN];
+        } POSTPACK mac;
+        struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
+            A_UINT32                antswitch1;
+            A_UINT32                antswitch2;
+        }POSTPACK antswitchtable;
+    } POSTPACK u;
+} POSTPACK TCMD_CONT_RX;
+
+/* Force sleep/wake  test cmd
+ mode: TCMD_PM_WAKEUP - Wakeup the target
+       TCMD_PM_SLEEP - Force the target to sleep.
+ */
+typedef enum {
+    TCMD_PM_WAKEUP = 1, /* be consistent with target */
+    TCMD_PM_SLEEP
+} TCMD_PM_MODE;
+
+typedef PREPACK struct {
+    A_UINT32  testCmdId;
+    A_UINT32  mode;
+} POSTPACK TCMD_PM;
+
+typedef enum {
+    TCMD_CONT_TX_ID,
+    TCMD_CONT_RX_ID,
+    TCMD_PM_ID
+} TCMD_ID;
+
+typedef PREPACK union {
+          TCMD_CONT_TX contTx;
+          TCMD_CONT_RX contRx;
+          TCMD_PM pm;
+} POSTPACK TEST_CMD;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TESTCMD_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_api.h b/drivers/net/wireless/ath6kl/include/wlan_api.h
new file mode 100644
index 000000000000..aa17b3e1de12
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_api.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_api.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API for the host wlan module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_API_H_
+#define _HOST_WLAN_API_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <a_osapi.h>
+
+struct ieee80211_node_table;
+struct ieee80211_frame;
+
+struct ieee80211_common_ie {
+    A_UINT16    ie_chan;
+    A_UINT8     *ie_tstamp;
+    A_UINT8     *ie_ssid;
+    A_UINT8     *ie_rates;
+    A_UINT8     *ie_xrates;
+    A_UINT8     *ie_country;
+    A_UINT8     *ie_wpa;
+    A_UINT8     *ie_rsn;
+    A_UINT8     *ie_wmm;
+    A_UINT8     *ie_ath;
+    A_UINT16    ie_capInfo;
+    A_UINT16    ie_beaconInt;
+    A_UINT8     *ie_tim;
+    A_UINT8     *ie_chswitch;
+    A_UINT8     ie_erp;
+    A_UINT8     *ie_wsc;
+    A_UINT8     *ie_htcap;
+    A_UINT8     *ie_htop;
+#ifdef WAPI_ENABLE
+    A_UINT8     *ie_wapi;
+#endif
+};
+
+typedef struct bss {
+    A_UINT8                      ni_macaddr[6];
+    A_UINT8                      ni_snr;
+    A_INT16                      ni_rssi;
+    struct bss                   *ni_list_next;
+    struct bss                   *ni_list_prev;
+    struct bss                   *ni_hash_next;
+    struct bss                   *ni_hash_prev;
+    struct ieee80211_common_ie   ni_cie;
+    A_UINT8                     *ni_buf;
+    A_UINT16                     ni_framelen;
+    struct ieee80211_node_table *ni_table;
+    A_UINT32                     ni_refcnt;
+    int                          ni_scangen;
+
+    A_UINT32                     ni_tstamp;
+#ifdef OS_ROAM_MANAGEMENT
+    A_UINT32                     ni_si_gen;
+#endif
+} bss_t;
+
+typedef void wlan_node_iter_func(void *arg, bss_t *);
+
+bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
+void wlan_node_free(bss_t *ni);
+void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+                const A_UINT8 *macaddr);
+bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
+void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
+void wlan_free_allnodes(struct ieee80211_node_table *nt);
+void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+                        void *arg);
+
+void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
+void wlan_node_table_reset(struct ieee80211_node_table *nt);
+void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
+
+A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
+                           struct ieee80211_common_ie *cie);
+
+A_UINT16 wlan_ieee2freq(int chan);
+A_UINT32 wlan_freq2ieee(A_UINT16 freq);
+
+void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge);
+
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
+
+bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid);
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_WLAN_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_defs.h b/drivers/net/wireless/ath6kl/include/wlan_defs.h
new file mode 100644
index 000000000000..1fe4b113a427
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_defs.h
@@ -0,0 +1,75 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_defs.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __WLAN_DEFS_H__
+#define __WLAN_DEFS_H__
+
+/*
+ * This file contains WLAN definitions that may be used across both
+ * Host and Target software.  
+ */
+
+typedef enum {
+    MODE_11A        = 0,   /* 11a Mode */
+    MODE_11G        = 1,   /* 11b/g Mode */
+    MODE_11B        = 2,   /* 11b Mode */
+    MODE_11GONLY    = 3,   /* 11g only Mode */
+#ifdef SUPPORT_11N
+    MODE_11NA_HT20   = 4,  /* 11a HT20 mode */
+    MODE_11NG_HT20   = 5,  /* 11g HT20 mode */
+    MODE_11NA_HT40   = 6,  /* 11a HT40 mode */
+    MODE_11NG_HT40   = 7,  /* 11g HT40 mode */
+    MODE_UNKNOWN    = 8,
+    MODE_MAX        = 8
+#else
+    MODE_UNKNOWN    = 4,
+    MODE_MAX        = 4
+#endif
+} WLAN_PHY_MODE;
+
+typedef enum {
+    WLAN_11A_CAPABILITY   = 1,
+    WLAN_11G_CAPABILITY   = 2,
+    WLAN_11AG_CAPABILITY  = 3,
+}WLAN_CAPABILITY;
+
+#ifdef SUPPORT_11N
+typedef unsigned long A_RATEMASK;
+#else
+typedef unsigned short A_RATEMASK;
+#endif
+
+#ifdef SUPPORT_11N
+#define IS_MODE_11A(mode)       (((mode) == MODE_11A) || \
+                                 ((mode) == MODE_11NA_HT20) || \
+                                 ((mode) == MODE_11NA_HT40))
+#define IS_MODE_11B(mode)       ((mode) == MODE_11B)
+#define IS_MODE_11G(mode)       (((mode) == MODE_11G) || \
+                                 ((mode) == MODE_11GONLY) || \
+                                 ((mode) == MODE_11NG_HT20) || \
+                                 ((mode) == MODE_11NG_HT40))
+#define IS_MODE_11GONLY(mode)   ((mode) == MODE_11GONLY)
+#else
+#define IS_MODE_11A(mode)       ((mode) == MODE_11A)
+#define IS_MODE_11B(mode)       ((mode) == MODE_11B)
+#define IS_MODE_11G(mode)       (((mode) == MODE_11G) || \
+                                 ((mode) == MODE_11GONLY))
+#define IS_MODE_11GONLY(mode)   ((mode) == MODE_11GONLY)
+#endif /* SUPPORT_11N */
+
+#endif /* __WLANDEFS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_dset.h b/drivers/net/wireless/ath6kl/include/wlan_dset.h
new file mode 100644
index 000000000000..e5f9b2480c15
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_dset.h
@@ -0,0 +1,30 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_dset.h" company="Atheros">
+//    Copyright (c) 2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __WLAN_DSET_H__
+#define __WLAN_DSET_H__
+
+typedef PREPACK struct wow_config_dset {
+
+    A_UINT8 valid_dset;
+    A_UINT8 gpio_enable;
+    A_UINT16 gpio_pin;
+} POSTPACK WOW_CONFIG_DSET;
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/wmi.h b/drivers/net/wireless/ath6kl/include/wmi.h
new file mode 100644
index 000000000000..7b140d8118b4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi.h
@@ -0,0 +1,3053 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to commands
+ * belongs to the host driver and the WMI is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_H_
+#define _WMI_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "wmix.h"
+#include "wlan_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HTC_PROTOCOL_VERSION    0x0002
+#define HTC_PROTOCOL_REVISION   0x0000
+
+#define WMI_PROTOCOL_VERSION    0x0002
+#define WMI_PROTOCOL_REVISION   0x0000
+
+#define ATH_MAC_LEN             6               /* length of mac in bytes */
+#define WMI_CMD_MAX_LEN         100
+#define WMI_CONTROL_MSG_MAX_LEN     256
+#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
+#define IS_ETHERTYPE(_typeOrLen)        ((_typeOrLen) >= 0x0600)
+#define RFC1042OUI      {0x00, 0x00, 0x00}
+
+#define IP_ETHERTYPE 0x0800
+
+#define WMI_IMPLICIT_PSTREAM 0xFF
+#define WMI_MAX_THINSTREAM 15
+
+#ifdef AR6002_REV2
+#define IBSS_MAX_NUM_STA          4
+#else
+#define IBSS_MAX_NUM_STA          8
+#endif
+
+struct host_app_area_s {
+    A_UINT32 wmi_protocol_ver;
+};
+
+/*
+ * Data Path
+ */
+typedef PREPACK struct {
+    A_UINT8     dstMac[ATH_MAC_LEN];
+    A_UINT8     srcMac[ATH_MAC_LEN];
+    A_UINT16    typeOrLen;
+} POSTPACK ATH_MAC_HDR;
+
+typedef PREPACK struct {
+    A_UINT8     dsap;
+    A_UINT8     ssap;
+    A_UINT8     cntl;
+    A_UINT8     orgCode[3];
+    A_UINT16    etherType;
+} POSTPACK ATH_LLC_SNAP_HDR;
+
+typedef enum {
+    DATA_MSGTYPE = 0x0,
+    CNTL_MSGTYPE,
+    SYNC_MSGTYPE,
+    OPT_MSGTYPE,
+} WMI_MSG_TYPE;
+
+
+/*
+ * Macros for operating on WMI_DATA_HDR (info) field
+ */
+
+#define WMI_DATA_HDR_MSG_TYPE_MASK  0x03
+#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
+#define WMI_DATA_HDR_UP_MASK        0x07
+#define WMI_DATA_HDR_UP_SHIFT       2
+/* In AP mode, the same bit (b5) is used to indicate Power save state in
+ * the Rx dir and More data bit state in the tx direction.
+ */
+#define WMI_DATA_HDR_PS_MASK        0x1
+#define WMI_DATA_HDR_PS_SHIFT       5
+
+#define WMI_DATA_HDR_MORE_MASK      0x1
+#define WMI_DATA_HDR_MORE_SHIFT     5
+
+typedef enum {
+    WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
+    WMI_DATA_HDR_DATA_TYPE_802_11,
+    WMI_DATA_HDR_DATA_TYPE_ACL,
+} WMI_DATA_HDR_DATA_TYPE;
+
+#define WMI_DATA_HDR_DATA_TYPE_MASK     0x3
+#define WMI_DATA_HDR_DATA_TYPE_SHIFT    6
+
+#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT))
+
+#define WMI_DATA_HDR_IS_MSG_TYPE(h, t)  (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
+#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
+#define WMI_DATA_HDR_GET_UP(h)    (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK)
+#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
+
+#define WMI_DATA_HDR_GET_DATA_TYPE(h)   (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK)
+#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT))
+
+#define WMI_DATA_HDR_GET_DOT11(h)   (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11)
+#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p))
+
+/* Macros for operating on WMI_DATA_HDR (info2) field */
+#define WMI_DATA_HDR_SEQNO_MASK     0xFFF
+#define WMI_DATA_HDR_SEQNO_SHIFT    0
+
+#define WMI_DATA_HDR_AMSDU_MASK     0x1
+#define WMI_DATA_HDR_AMSDU_SHIFT    12
+
+#define WMI_DATA_HDR_META_MASK      0x7
+#define WMI_DATA_HDR_META_SHIFT     13
+
+#define GET_SEQ_NO(_v)                  ((_v) & WMI_DATA_HDR_SEQNO_MASK)
+#define GET_ISMSDU(_v)                  ((_v) & WMI_DATA_HDR_AMSDU_MASK)
+
+#define WMI_DATA_HDR_GET_SEQNO(h)        GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT)
+#define WMI_DATA_HDR_SET_SEQNO(h, _v)   ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT))
+
+#define WMI_DATA_HDR_IS_AMSDU(h)        GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT)
+#define WMI_DATA_HDR_SET_AMSDU(h, _v)   ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT))
+
+#define WMI_DATA_HDR_GET_META(h)        (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK)
+#define WMI_DATA_HDR_SET_META(h, _v)    ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT))
+
+typedef PREPACK struct {
+    A_INT8      rssi;
+    A_UINT8     info;               /* usage of 'info' field(8-bit):
+                                     *  b1:b0       - WMI_MSG_TYPE
+                                     *  b4:b3:b2    - UP(tid)
+                                     *  b5          - Used in AP mode. More-data in tx dir, PS in rx.
+                                     *  b7:b6       -  Dot3 header(0),
+                                     *                 Dot11 Header(1),
+                                     *                 ACL data(2)
+                                     */
+
+    A_UINT16    info2;              /* usage of 'info2' field(16-bit):
+                                     * b11:b0       - seq_no
+                                     * b12          - A-MSDU?
+                                     * b15:b13      - META_DATA_VERSION 0 - 7
+                                     */
+    A_UINT16    reserved;
+} POSTPACK WMI_DATA_HDR;
+
+/*
+ *  TX META VERSION DEFINITIONS
+ */
+#define WMI_MAX_TX_META_SZ  (12)
+#define WMI_MAX_TX_META_VERSION (7)
+#define WMI_META_VERSION_1 (0x01)
+#define WMI_META_VERSION_2 (0X02)
+
+#define WMI_ACL_TO_DOT11_HEADROOM   36
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_TX_META_V0;
+#endif
+
+typedef PREPACK struct {
+    A_UINT8     pktID;           /* The packet ID to identify the tx request */
+    A_UINT8     ratePolicyID;    /* The rate policy to be used for the tx of this frame */
+} POSTPACK WMI_TX_META_V1;
+
+
+#define WMI_CSUM_DIR_TX (0x1)
+#define TX_CSUM_CALC_FILL (0x1)
+typedef PREPACK struct {
+    A_UINT8    csumStart;       /*Offset from start of the WMI header for csum calculation to begin */
+    A_UINT8    csumDest;        /*Offset from start of WMI header where final csum goes*/
+    A_UINT8     csumFlags;    /*number of bytes over which csum is calculated*/
+} POSTPACK WMI_TX_META_V2;
+
+
+/*
+ *  RX META VERSION DEFINITIONS
+ */
+/* if RX meta data is present at all then the meta data field
+ *  will consume WMI_MAX_RX_META_SZ bytes of space between the
+ *  WMI_DATA_HDR and the payload. How much of the available
+ *  Meta data is actually used depends on which meta data
+ *  version is active. */
+#define WMI_MAX_RX_META_SZ  (12)
+#define WMI_MAX_RX_META_VERSION (7)
+
+#define WMI_RX_STATUS_OK            0 /* success */
+#define WMI_RX_STATUS_DECRYPT_ERR   1 /* decrypt error */
+#define WMI_RX_STATUS_MIC_ERR       2 /* tkip MIC error */
+#define WMI_RX_STATUS_ERR           3 /* undefined error */
+
+#define WMI_RX_FLAGS_AGGR           0x0001 /* part of AGGR */
+#define WMI_RX_FlAGS_STBC           0x0002 /* used STBC */
+#define WMI_RX_FLAGS_SGI            0x0004 /* used SGI */
+#define WMI_RX_FLAGS_HT             0x0008 /* is HT packet */
+/* the flags field is also used to store the CRYPTO_TYPE of the frame
+ * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */
+#define WMI_RX_FLAGS_CRYPTO_SHIFT   4
+#define WMI_RX_FLAGS_CRYPTO_MASK    0x1f
+#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK)
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_RX_META_VERSION_0;
+#endif
+
+typedef PREPACK struct {
+    A_UINT8     status; /* one of WMI_RX_STATUS_... */
+    A_UINT8     rix;    /* rate index mapped to rate at which this packet was received. */
+    A_UINT8     rssi;   /* rssi of packet */
+    A_UINT8     channel;/* rf channel during packet reception */
+    A_UINT16    flags;  /* a combination of WMI_RX_FLAGS_... */
+} POSTPACK WMI_RX_META_V1;
+
+#define RX_CSUM_VALID_FLAG (0x1)
+typedef PREPACK struct {
+    A_UINT16    csum;
+    A_UINT8     csumFlags;/* bit 0 set -partial csum valid
+                             bit 1 set -test mode */
+} POSTPACK WMI_RX_META_V2;
+
+
+
+#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF)
+
+/*
+ * Control Path
+ */
+typedef PREPACK struct {
+    A_UINT16    commandId;
+/*
+ * info1 - 16 bits
+ * b03:b00 - id
+ * b15:b04 - unused
+ */
+    A_UINT16    info1;
+
+    A_UINT16    reserved;      /* For alignment */
+} POSTPACK WMI_CMD_HDR;        /* used for commands and events */
+
+/*
+ * List of Commnands
+ */
+typedef enum {
+    WMI_CONNECT_CMDID           = 0x0001,
+    WMI_RECONNECT_CMDID,
+    WMI_DISCONNECT_CMDID,
+    WMI_SYNCHRONIZE_CMDID,
+    WMI_CREATE_PSTREAM_CMDID,
+    WMI_DELETE_PSTREAM_CMDID,
+    WMI_START_SCAN_CMDID,
+    WMI_SET_SCAN_PARAMS_CMDID,
+    WMI_SET_BSS_FILTER_CMDID,
+    WMI_SET_PROBED_SSID_CMDID,               /* 10 */
+    WMI_SET_LISTEN_INT_CMDID,
+    WMI_SET_BMISS_TIME_CMDID,
+    WMI_SET_DISC_TIMEOUT_CMDID,
+    WMI_GET_CHANNEL_LIST_CMDID,
+    WMI_SET_BEACON_INT_CMDID,
+    WMI_GET_STATISTICS_CMDID,
+    WMI_SET_CHANNEL_PARAMS_CMDID,
+    WMI_SET_POWER_MODE_CMDID,
+    WMI_SET_IBSS_PM_CAPS_CMDID,
+    WMI_SET_POWER_PARAMS_CMDID,              /* 20 */
+    WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+    WMI_ADD_CIPHER_KEY_CMDID,
+    WMI_DELETE_CIPHER_KEY_CMDID,
+    WMI_ADD_KRK_CMDID,
+    WMI_DELETE_KRK_CMDID,
+    WMI_SET_PMKID_CMDID,
+    WMI_SET_TX_PWR_CMDID,
+    WMI_GET_TX_PWR_CMDID,
+    WMI_SET_ASSOC_INFO_CMDID,
+    WMI_ADD_BAD_AP_CMDID,                    /* 30 */
+    WMI_DELETE_BAD_AP_CMDID,
+    WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+    WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+    WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+    WMI_SET_ACCESS_PARAMS_CMDID,
+    WMI_SET_RETRY_LIMITS_CMDID,
+    WMI_SET_OPT_MODE_CMDID,
+    WMI_OPT_TX_FRAME_CMDID,
+    WMI_SET_VOICE_PKT_SIZE_CMDID,
+    WMI_SET_MAX_SP_LEN_CMDID,                /* 40 */
+    WMI_SET_ROAM_CTRL_CMDID,
+    WMI_GET_ROAM_TBL_CMDID,
+    WMI_GET_ROAM_DATA_CMDID,
+    WMI_ENABLE_RM_CMDID,
+    WMI_SET_MAX_OFFHOME_DURATION_CMDID,
+    WMI_EXTENSION_CMDID,                        /* Non-wireless extensions */
+    WMI_SNR_THRESHOLD_PARAMS_CMDID,
+    WMI_LQ_THRESHOLD_PARAMS_CMDID,
+    WMI_SET_LPREAMBLE_CMDID,
+    WMI_SET_RTS_CMDID,                       /* 50 */
+    WMI_CLR_RSSI_SNR_CMDID,
+    WMI_SET_FIXRATES_CMDID,
+    WMI_GET_FIXRATES_CMDID,
+    WMI_SET_AUTH_MODE_CMDID,
+    WMI_SET_REASSOC_MODE_CMDID,
+    WMI_SET_WMM_CMDID,
+    WMI_SET_WMM_TXOP_CMDID,
+    WMI_TEST_CMDID,
+    /* COEX AR6002 only*/
+    WMI_SET_BT_STATUS_CMDID,                
+    WMI_SET_BT_PARAMS_CMDID,                /* 60 */
+
+    WMI_SET_KEEPALIVE_CMDID,
+    WMI_GET_KEEPALIVE_CMDID,
+    WMI_SET_APPIE_CMDID,
+    WMI_GET_APPIE_CMDID,
+    WMI_SET_WSC_STATUS_CMDID,
+
+    /* Wake on Wireless */
+    WMI_SET_HOST_SLEEP_MODE_CMDID,
+    WMI_SET_WOW_MODE_CMDID,
+    WMI_GET_WOW_LIST_CMDID,
+    WMI_ADD_WOW_PATTERN_CMDID,
+    WMI_DEL_WOW_PATTERN_CMDID,               /* 70 */
+
+    WMI_SET_FRAMERATES_CMDID,
+    WMI_SET_AP_PS_CMDID,
+    WMI_SET_QOS_SUPP_CMDID,
+    /* WMI_THIN_RESERVED_... mark the start and end
+     * values for WMI_THIN_RESERVED command IDs. These
+     * command IDs can be found in wmi_thin.h */
+    WMI_THIN_RESERVED_START = 0x8000,
+    WMI_THIN_RESERVED_END = 0x8fff,
+    /*
+     * Developer commands starts at 0xF000
+     */
+    WMI_SET_BITRATE_CMDID = 0xF000,
+    WMI_GET_BITRATE_CMDID,
+    WMI_SET_WHALPARAM_CMDID,
+
+
+    /*Should add the new command to the tail for compatible with
+     * etna.
+     */
+    WMI_SET_MAC_ADDRESS_CMDID,
+    WMI_SET_AKMP_PARAMS_CMDID,
+    WMI_SET_PMKID_LIST_CMDID,
+    WMI_GET_PMKID_LIST_CMDID,
+    WMI_ABORT_SCAN_CMDID,
+    WMI_SET_TARGET_EVENT_REPORT_CMDID,
+
+    // Unused
+    WMI_UNUSED1,
+    WMI_UNUSED2,
+
+    /*
+     * AP mode commands
+     */
+    WMI_AP_HIDDEN_SSID_CMDID,
+    WMI_AP_SET_NUM_STA_CMDID,
+    WMI_AP_ACL_POLICY_CMDID,
+    WMI_AP_ACL_MAC_LIST_CMDID,
+    WMI_AP_CONFIG_COMMIT_CMDID,
+    WMI_AP_SET_MLME_CMDID,
+    WMI_AP_SET_PVB_CMDID,
+    WMI_AP_CONN_INACT_CMDID,
+    WMI_AP_PROT_SCAN_TIME_CMDID,
+    WMI_AP_SET_COUNTRY_CMDID,
+    WMI_AP_SET_DTIM_CMDID,
+    WMI_AP_MODE_STAT_CMDID,
+
+    WMI_SET_IP_CMDID,
+    WMI_SET_PARAMS_CMDID,
+    WMI_SET_MCAST_FILTER_CMDID,
+    WMI_DEL_MCAST_FILTER_CMDID,
+
+    WMI_ALLOW_AGGR_CMDID,
+    WMI_ADDBA_REQ_CMDID,
+    WMI_DELBA_REQ_CMDID,
+    WMI_SET_HT_CAP_CMDID,
+    WMI_SET_HT_OP_CMDID,
+    WMI_SET_TX_SELECT_RATES_CMDID,
+    WMI_SET_TX_SGI_PARAM_CMDID,
+    WMI_SET_RATE_POLICY_CMDID,
+
+    WMI_HCI_CMD_CMDID,
+    WMI_RX_FRAME_FORMAT_CMDID,
+    WMI_SET_THIN_MODE_CMDID,
+    WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+
+    WMI_AP_SET_11BG_RATESET_CMDID,
+    WMI_SET_PMK_CMDID,
+    WMI_MCAST_FILTER_CMDID,
+	/* COEX CMDID AR6003*/
+	WMI_SET_BTCOEX_FE_ANT_CMDID,
+	WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+	WMI_SET_BTCOEX_SCO_CONFIG_CMDID,
+	WMI_SET_BTCOEX_A2DP_CONFIG_CMDID,
+	WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID,
+	WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+	WMI_SET_BTCOEX_DEBUG_CMDID,
+	WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID,
+	WMI_GET_BTCOEX_STATS_CMDID,
+	WMI_GET_BTCOEX_CONFIG_CMDID
+} WMI_COMMAND_ID;
+
+/*
+ * Frame Types
+ */
+typedef enum {
+    WMI_FRAME_BEACON        =   0,
+    WMI_FRAME_PROBE_REQ,
+    WMI_FRAME_PROBE_RESP,
+    WMI_FRAME_ASSOC_REQ,
+    WMI_FRAME_ASSOC_RESP,
+    WMI_NUM_MGMT_FRAME
+} WMI_MGMT_FRAME_TYPE;
+
+/*
+ * Connect Command
+ */
+typedef enum {
+    INFRA_NETWORK       = 0x01,
+    ADHOC_NETWORK       = 0x02,
+    ADHOC_CREATOR       = 0x04,
+    AP_NETWORK          = 0x10,
+} NETWORK_TYPE;
+
+typedef enum {
+    OPEN_AUTH           = 0x01,
+    SHARED_AUTH         = 0x02,
+    LEAP_AUTH           = 0x04,  /* different from IEEE_AUTH_MODE definitions */
+} DOT11_AUTH_MODE;
+
+typedef enum {
+    NONE_AUTH           = 0x01,
+    WPA_AUTH            = 0x02,
+    WPA2_AUTH           = 0x04,
+    WPA_PSK_AUTH        = 0x08,
+    WPA2_PSK_AUTH       = 0x10,
+    WPA_AUTH_CCKM       = 0x20,
+    WPA2_AUTH_CCKM      = 0x40,
+} AUTH_MODE;
+
+typedef enum {
+    NONE_CRYPT          = 0x01,
+    WEP_CRYPT           = 0x02,
+    TKIP_CRYPT          = 0x04,
+    AES_CRYPT           = 0x08,
+#ifdef WAPI_ENABLE
+    WAPI_CRYPT          = 0x10,
+#endif /*WAPI_ENABLE*/
+} CRYPTO_TYPE;
+
+#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
+#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_CRYPTO_TYPE
+#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1)
+#endif /* WAPI_ENABLE */
+
+#ifdef WAPI_ENABLE
+#define IW_ENCODE_ALG_SM4       0x20
+#define IW_AUTH_WAPI_ENABLED    0x20
+#endif
+
+#define WMI_MIN_KEY_INDEX   0
+#define WMI_MAX_KEY_INDEX   3
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_KEY_INDEX
+#define WMI_MAX_KEY_INDEX   7 /* wapi grpKey 0-3, prwKey 4-7 */
+#endif /* WAPI_ENABLE */
+
+#define WMI_MAX_KEY_LEN     32
+
+#define WMI_MAX_SSID_LEN    32
+
+typedef enum {
+    CONNECT_ASSOC_POLICY_USER           = 0x0001,
+    CONNECT_SEND_REASSOC                = 0x0002,
+    CONNECT_IGNORE_WPAx_GROUP_CIPHER    = 0x0004,
+    CONNECT_PROFILE_MATCH_DONE          = 0x0008,
+    CONNECT_IGNORE_AAC_BEACON           = 0x0010,
+    CONNECT_CSA_FOLLOW_BSS              = 0x0020,
+    CONNECT_DO_WPA_OFFLOAD              = 0x0040,
+    CONNECT_DO_NOT_DEAUTH               = 0x0080,
+} WMI_CONNECT_CTRL_FLAGS_BITS;
+
+#define DEFAULT_CONNECT_CTRL_FLAGS    (CONNECT_CSA_FOLLOW_BSS)
+
+typedef PREPACK struct {
+    A_UINT8     networkType;
+    A_UINT8     dot11AuthMode;
+    A_UINT8     authMode;
+    A_UINT8     pairwiseCryptoType;
+    A_UINT8     pairwiseCryptoLen;
+    A_UINT8     groupCryptoType;
+    A_UINT8     groupCryptoLen;
+    A_UINT8     ssidLength;
+    A_UCHAR     ssid[WMI_MAX_SSID_LEN];
+    A_UINT16    channel;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT32    ctrl_flags;
+} POSTPACK WMI_CONNECT_CMD;
+
+/*
+ * WMI_RECONNECT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;                    /* hint */
+    A_UINT8     bssid[ATH_MAC_LEN];         /* mandatory if set */
+} POSTPACK WMI_RECONNECT_CMD;
+
+#define WMI_PMK_LEN     32
+typedef PREPACK struct {
+    A_UINT8 pmk[WMI_PMK_LEN];
+} POSTPACK WMI_SET_PMK_CMD;
+
+/*
+ * WMI_ADD_CIPHER_KEY_CMDID
+ */
+typedef enum {
+    PAIRWISE_USAGE      = 0x00,
+    GROUP_USAGE         = 0x01,
+    TX_USAGE            = 0x02,     /* default Tx Key - Static WEP only */
+} KEY_USAGE;
+
+/*
+ * Bit Flag
+ * Bit 0 - Initialise TSC - default is Initialize
+ */
+#define KEY_OP_INIT_TSC       0x01
+#define KEY_OP_INIT_RSC       0x02
+#ifdef WAPI_ENABLE
+#define KEY_OP_INIT_WAPIPN    0x10
+#endif /* WAPI_ENABLE */
+
+#define KEY_OP_INIT_VAL     0x03     /* Default Initialise the TSC & RSC */
+#define KEY_OP_VALID_MASK   0x03
+
+typedef PREPACK struct {
+    A_UINT8     keyIndex;
+    A_UINT8     keyType;
+    A_UINT8     keyUsage;           /* KEY_USAGE */
+    A_UINT8     keyLength;
+    A_UINT8     keyRSC[8];          /* key replay sequence counter */
+    A_UINT8     key[WMI_MAX_KEY_LEN];
+    A_UINT8     key_op_ctrl;       /* Additional Key Control information */
+    A_UINT8    key_macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
+
+/*
+ * WMI_DELETE_CIPHER_KEY_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     keyIndex;
+} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
+
+#define WMI_KRK_LEN     16
+/*
+ * WMI_ADD_KRK_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     krk[WMI_KRK_LEN];
+} POSTPACK WMI_ADD_KRK_CMD;
+
+/*
+ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
+ */
+typedef enum {
+    WMI_TKIP_CM_DISABLE = 0x0,
+    WMI_TKIP_CM_ENABLE  = 0x1,
+} WMI_TKIP_CM_CONTROL;
+
+typedef PREPACK struct {
+    A_UINT8  cm_en;                     /* WMI_TKIP_CM_CONTROL */
+} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
+
+/*
+ * WMI_SET_PMKID_CMDID
+ */
+
+#define WMI_PMKID_LEN 16
+
+typedef enum {
+   PMKID_DISABLE = 0,
+   PMKID_ENABLE  = 1,
+} PMKID_ENABLE_FLG;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     enable;                 /* PMKID_ENABLE_FLG */
+    A_UINT8     pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_SET_PMKID_CMD;
+
+/*
+ * WMI_START_SCAN_CMD
+ */
+typedef enum {
+    WMI_LONG_SCAN  = 0,
+    WMI_SHORT_SCAN = 1,
+} WMI_SCAN_TYPE;
+
+typedef PREPACK struct {
+    A_BOOL   forceFgScan;
+    A_BOOL   isLegacy;        /* For Legacy Cisco AP compatibility */
+    A_UINT32 homeDwellTime;   /* Maximum duration in the home channel(milliseconds) */
+    A_UINT32 forceScanInterval;    /* Time interval between scans (milliseconds)*/
+    A_UINT8  scanType;           /* WMI_SCAN_TYPE */
+    A_UINT8  numChannels;            /* how many channels follow */
+    A_UINT16 channelList[1];         /* channels in Mhz */
+} POSTPACK WMI_START_SCAN_CMD;
+
+/*
+ * WMI_SET_SCAN_PARAMS_CMDID
+ */
+#define WMI_SHORTSCANRATIO_DEFAULT      3
+/* 
+ *  Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD 
+ *  Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS
+ */
+typedef enum {
+    CONNECT_SCAN_CTRL_FLAGS = 0x01,    /* set if can scan in the Connect cmd */
+    SCAN_CONNECTED_CTRL_FLAGS = 0x02,  /* set if scan for the SSID it is */
+                                       /* already connected to */
+    ACTIVE_SCAN_CTRL_FLAGS = 0x04,     /* set if enable active scan */
+    ROAM_SCAN_CTRL_FLAGS = 0x08,       /* set if enable roam scan when bmiss and lowrssi */
+    REPORT_BSSINFO_CTRL_FLAGS = 0x10,   /* set if follows customer BSSINFO reporting rule */
+    ENABLE_AUTO_CTRL_FLAGS = 0x20,      /* if disabled, target doesn't
+                                          scan after a disconnect event  */
+    ENABLE_SCAN_ABORT_EVENT = 0x40      /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
+} WMI_SCAN_CTRL_FLAGS_BITS;
+
+#define CAN_SCAN_IN_CONNECT(flags)      (flags & CONNECT_SCAN_CTRL_FLAGS)
+#define CAN_SCAN_CONNECTED(flags)       (flags & SCAN_CONNECTED_CTRL_FLAGS)
+#define ENABLE_ACTIVE_SCAN(flags)       (flags & ACTIVE_SCAN_CTRL_FLAGS)
+#define ENABLE_ROAM_SCAN(flags)         (flags & ROAM_SCAN_CTRL_FLAGS)
+#define CONFIG_REPORT_BSSINFO(flags)     (flags & REPORT_BSSINFO_CTRL_FLAGS)
+#define IS_AUTO_SCAN_ENABLED(flags)      (flags & ENABLE_AUTO_CTRL_FLAGS)
+#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
+
+#define DEFAULT_SCAN_CTRL_FLAGS         (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
+
+
+typedef PREPACK struct {
+    A_UINT16    fg_start_period;        /* seconds */
+    A_UINT16    fg_end_period;          /* seconds */
+    A_UINT16    bg_period;              /* seconds */
+    A_UINT16    maxact_chdwell_time;    /* msec */
+    A_UINT16    pas_chdwell_time;       /* msec */
+    A_UINT8     shortScanRatio;         /* how many shorts scan for one long */
+    A_UINT8     scanCtrlFlags;
+    A_UINT16    minact_chdwell_time;    /* msec */
+    A_UINT16    maxact_scan_per_ssid;   /* max active scans per ssid */
+    A_UINT32    max_dfsch_act_time;  /* msecs */
+} POSTPACK WMI_SCAN_PARAMS_CMD;
+
+/*
+ * WMI_SET_BSS_FILTER_CMDID
+ */
+typedef enum {
+    NONE_BSS_FILTER = 0x0,              /* no beacons forwarded */
+    ALL_BSS_FILTER,                     /* all beacons forwarded */
+    PROFILE_FILTER,                     /* only beacons matching profile */
+    ALL_BUT_PROFILE_FILTER,             /* all but beacons matching profile */
+    CURRENT_BSS_FILTER,                 /* only beacons matching current BSS */
+    ALL_BUT_BSS_FILTER,                 /* all but beacons matching BSS */
+    PROBED_SSID_FILTER,                 /* beacons matching probed ssid */
+    LAST_BSS_FILTER,                    /* marker only */
+} WMI_BSS_FILTER;
+
+typedef PREPACK struct {
+    A_UINT8    bssFilter;                      /* see WMI_BSS_FILTER */
+    A_UINT8    reserved1;                      /* For alignment */
+    A_UINT16   reserved2;                      /* For alignment */
+    A_UINT32   ieMask;
+} POSTPACK WMI_BSS_FILTER_CMD;
+
+/*
+ * WMI_SET_PROBED_SSID_CMDID
+ */
+#define MAX_PROBED_SSID_INDEX   9
+
+typedef enum {
+    DISABLE_SSID_FLAG  = 0,                  /* disables entry */
+    SPECIFIC_SSID_FLAG = 0x01,               /* probes specified ssid */
+    ANY_SSID_FLAG      = 0x02,               /* probes for any ssid */
+} WMI_SSID_FLAG;
+
+typedef PREPACK struct {
+    A_UINT8     entryIndex;                     /* 0 to MAX_PROBED_SSID_INDEX */
+    A_UINT8     flag;                           /* WMI_SSID_FLG */
+    A_UINT8     ssidLength;
+    A_UINT8     ssid[32];
+} POSTPACK WMI_PROBED_SSID_CMD;
+
+/*
+ * WMI_SET_LISTEN_INT_CMDID
+ * The Listen interval is between 15 and 3000 TUs
+ */
+#define MIN_LISTEN_INTERVAL 15
+#define MAX_LISTEN_INTERVAL 5000
+#define MIN_LISTEN_BEACONS 1
+#define MAX_LISTEN_BEACONS 50
+
+typedef PREPACK struct {
+    A_UINT16     listenInterval;
+    A_UINT16     numBeacons;
+} POSTPACK WMI_LISTEN_INT_CMD;
+
+/*
+ * WMI_SET_BEACON_INT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16     beaconInterval;
+} POSTPACK WMI_BEACON_INT_CMD;
+
+/*
+ * WMI_SET_BMISS_TIME_CMDID
+ * valid values are between 1000 and 5000 TUs
+ */
+
+#define MIN_BMISS_TIME     1000
+#define MAX_BMISS_TIME     5000
+#define MIN_BMISS_BEACONS  1
+#define MAX_BMISS_BEACONS  50
+
+typedef PREPACK struct {
+    A_UINT16     bmissTime;
+    A_UINT16     numBeacons;
+} POSTPACK WMI_BMISS_TIME_CMD;
+
+/*
+ * WMI_SET_POWER_MODE_CMDID
+ */
+typedef enum {
+    REC_POWER = 0x01,
+    MAX_PERF_POWER,
+} WMI_POWER_MODE;
+
+typedef PREPACK struct {
+    A_UINT8     powerMode;      /* WMI_POWER_MODE */
+} POSTPACK WMI_POWER_MODE_CMD;
+
+typedef PREPACK struct {
+    A_INT8 status;      /* WMI_SET_PARAMS_REPLY */
+} POSTPACK WMI_SET_PARAMS_REPLY;
+
+typedef PREPACK struct {
+    A_UINT32 opcode;
+    A_UINT32 length;
+    A_CHAR buffer[1];      /* WMI_SET_PARAMS */
+} POSTPACK WMI_SET_PARAMS_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 multicast_mac[ATH_MAC_LEN];      /* WMI_SET_MCAST_FILTER */
+} POSTPACK WMI_SET_MCAST_FILTER_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 enable;      /* WMI_MCAST_FILTER */
+} POSTPACK WMI_MCAST_FILTER_CMD;
+
+/*
+ * WMI_SET_POWER_PARAMS_CMDID
+ */
+typedef enum {
+    IGNORE_DTIM = 0x01,
+    NORMAL_DTIM = 0x02,
+    STICK_DTIM  = 0x03,
+    AUTO_DTIM   = 0x04,
+} WMI_DTIM_POLICY;
+
+/* Policy to determnine whether TX should wakeup WLAN if sleeping */
+typedef enum {
+    TX_WAKEUP_UPON_SLEEP = 1,
+    TX_DONT_WAKEUP_UPON_SLEEP = 2
+} WMI_TX_WAKEUP_POLICY_UPON_SLEEP;
+
+/*
+ * Policy to determnine whether power save failure event should be sent to
+ * host during scanning
+ */
+typedef enum {
+    SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1,
+    IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2,
+} POWER_SAVE_FAIL_EVENT_POLICY;
+
+typedef PREPACK struct {
+    A_UINT16    idle_period;             /* msec */
+    A_UINT16    pspoll_number;
+    A_UINT16    dtim_policy;
+    A_UINT16    tx_wakeup_policy;
+    A_UINT16    num_tx_to_wakeup;
+    A_UINT16    ps_fail_event_policy;
+} POSTPACK WMI_POWER_PARAMS_CMD;
+
+/* Adhoc power save types */
+typedef enum {
+    ADHOC_PS_DISABLE=1,
+    ADHOC_PS_ATH=2,
+    ADHOC_PS_IEEE=3,
+    ADHOC_PS_OTHER=4,
+} WMI_ADHOC_PS_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8    power_saving;
+    A_UINT8    ttl; /* number of beacon periods */
+    A_UINT16   atim_windows;          /* msec */
+    A_UINT16   timeout_value;         /* msec */
+} POSTPACK WMI_IBSS_PM_CAPS_CMD;
+
+/* AP power save types */
+typedef enum {
+    AP_PS_DISABLE=1,
+    AP_PS_ATH=2,
+} WMI_AP_PS_TYPE;
+
+typedef PREPACK struct {
+    A_UINT32   idle_time;   /* in msec */
+    A_UINT32   ps_period;   /* in usec */
+    A_UINT8    sleep_period; /* in ps periods */
+    A_UINT8    psType;
+} POSTPACK WMI_AP_PS_CMD;
+
+/*
+ * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
+ */
+typedef enum {
+    IGNORE_TIM_ALL_QUEUES_APSD = 0,
+    PROCESS_TIM_ALL_QUEUES_APSD = 1,
+    IGNORE_TIM_SIMULATED_APSD = 2,
+    PROCESS_TIM_SIMULATED_APSD = 3,
+} APSD_TIM_POLICY;
+
+typedef PREPACK struct {
+    A_UINT16    psPollTimeout;          /* msec */
+    A_UINT16    triggerTimeout;         /* msec */
+    A_UINT32    apsdTimPolicy;      /* TIM behavior with  ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
+    A_UINT32    simulatedAPSDTimPolicy;      /* TIM behavior with  simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
+} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
+
+/*
+ * WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT16    voicePktSize;
+} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
+
+/*
+ * WMI_SET_MAX_SP_LEN_CMDID
+ */
+typedef enum {
+    DELIVER_ALL_PKT = 0x0,
+    DELIVER_2_PKT = 0x1,
+    DELIVER_4_PKT = 0x2,
+    DELIVER_6_PKT = 0x3,
+} APSD_SP_LEN_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8    maxSPLen;
+} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
+
+/*
+ * WMI_SET_DISC_TIMEOUT_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     disconnectTimeout;          /* seconds */
+} POSTPACK WMI_DISC_TIMEOUT_CMD;
+
+typedef enum {
+    UPLINK_TRAFFIC = 0,
+    DNLINK_TRAFFIC = 1,
+    BIDIR_TRAFFIC = 2,
+} DIR_TYPE;
+
+typedef enum {
+    DISABLE_FOR_THIS_AC = 0,
+    ENABLE_FOR_THIS_AC  = 1,
+    ENABLE_FOR_ALL_AC   = 2,
+} VOICEPS_CAP_TYPE;
+
+typedef enum {
+    TRAFFIC_TYPE_APERIODIC = 0,
+    TRAFFIC_TYPE_PERIODIC = 1,
+}TRAFFIC_TYPE;
+
+/*
+ * WMI_SYNCHRONIZE_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8 dataSyncMap;
+} POSTPACK WMI_SYNC_CMD;
+
+/*
+ * WMI_CREATE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT32        minServiceInt;           /* in milli-sec */
+    A_UINT32        maxServiceInt;           /* in milli-sec */
+    A_UINT32        inactivityInt;           /* in milli-sec */
+    A_UINT32        suspensionInt;           /* in milli-sec */
+    A_UINT32        serviceStartTime;
+    A_UINT32        minDataRate;             /* in bps */
+    A_UINT32        meanDataRate;            /* in bps */
+    A_UINT32        peakDataRate;            /* in bps */
+    A_UINT32        maxBurstSize;
+    A_UINT32        delayBound;
+    A_UINT32        minPhyRate;              /* in bps */
+    A_UINT32        sba;
+    A_UINT32        mediumTime;
+    A_UINT16        nominalMSDU;             /* in octects */
+    A_UINT16        maxMSDU;                 /* in octects */
+    A_UINT8         trafficClass;
+    A_UINT8         trafficDirection;        /* DIR_TYPE */
+    A_UINT8         rxQueueNum;
+    A_UINT8         trafficType;             /* TRAFFIC_TYPE */
+    A_UINT8         voicePSCapability;       /* VOICEPS_CAP_TYPE */
+    A_UINT8         tsid;
+    A_UINT8         userPriority;            /* 802.1D user priority */
+    A_UINT8         nominalPHY;              /* nominal phy rate */
+} POSTPACK WMI_CREATE_PSTREAM_CMD;
+
+/*
+ * WMI_DELETE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;
+    A_UINT8     trafficClass;
+    A_UINT8     tsid;
+} POSTPACK WMI_DELETE_PSTREAM_CMD;
+
+/*
+ * WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+typedef enum {
+    WMI_11A_MODE  = 0x1,
+    WMI_11G_MODE  = 0x2,
+    WMI_11AG_MODE = 0x3,
+    WMI_11B_MODE  = 0x4,
+    WMI_11GONLY_MODE = 0x5,    
+} WMI_PHY_MODE;
+
+#define WMI_MAX_CHANNELS        32
+
+typedef PREPACK struct {
+    A_UINT8     reserved1;
+    A_UINT8     scanParam;              /* set if enable scan */
+    A_UINT8     phyMode;                /* see WMI_PHY_MODE */
+    A_UINT8     numChannels;            /* how many channels follow */
+    A_UINT16    channelList[1];         /* channels in Mhz */
+} POSTPACK WMI_CHANNEL_PARAMS_CMD;
+
+
+/*
+ *  WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ *  Setting the polltime to 0 would disable polling.
+ *  Threshold values are in the ascending order, and should agree to:
+ *  (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
+ *      < highThreshold_upperVal)
+ */
+
+typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
+    A_UINT32    pollTime;               /* Polling time as a factor of LI */
+    A_INT16     thresholdAbove1_Val;          /* lowest of upper */
+    A_INT16     thresholdAbove2_Val;
+    A_INT16     thresholdAbove3_Val;
+    A_INT16     thresholdAbove4_Val;
+    A_INT16     thresholdAbove5_Val;
+    A_INT16     thresholdAbove6_Val;          /* highest of upper */
+    A_INT16     thresholdBelow1_Val;         /* lowest of bellow */
+    A_INT16     thresholdBelow2_Val;
+    A_INT16     thresholdBelow3_Val;
+    A_INT16     thresholdBelow4_Val;
+    A_INT16     thresholdBelow5_Val;
+    A_INT16     thresholdBelow6_Val;         /* highest of bellow */
+    A_UINT8     weight;                  /* "alpha" */
+    A_UINT8     reserved[3];
+} POSTPACK  WMI_RSSI_THRESHOLD_PARAMS_CMD;
+
+/*
+ *  WMI_SNR_THRESHOLD_PARAMS_CMDID
+ *  Setting the polltime to 0 would disable polling.
+ */
+
+typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
+    A_UINT32    pollTime;               /* Polling time as a factor of LI */
+    A_UINT8     weight;                  /* "alpha" */
+    A_UINT8     thresholdAbove1_Val;      /* lowest of uppper*/
+    A_UINT8     thresholdAbove2_Val;
+    A_UINT8     thresholdAbove3_Val;
+    A_UINT8     thresholdAbove4_Val;      /* highest of upper */
+    A_UINT8     thresholdBelow1_Val;     /* lowest of bellow */
+    A_UINT8     thresholdBelow2_Val;
+    A_UINT8     thresholdBelow3_Val;
+    A_UINT8     thresholdBelow4_Val;     /* highest of bellow */
+    A_UINT8     reserved[3];
+} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
+
+/*
+ *  WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
+    A_UINT8     enable;
+    A_UINT8     thresholdAbove1_Val;
+    A_UINT8     thresholdAbove2_Val;
+    A_UINT8     thresholdAbove3_Val;
+    A_UINT8     thresholdAbove4_Val;
+    A_UINT8     thresholdBelow1_Val;
+    A_UINT8     thresholdBelow2_Val;
+    A_UINT8     thresholdBelow3_Val;
+    A_UINT8     thresholdBelow4_Val;
+    A_UINT8     reserved[3];
+} POSTPACK  WMI_LQ_THRESHOLD_PARAMS_CMD;
+
+typedef enum {
+    WMI_LPREAMBLE_DISABLED = 0,
+    WMI_LPREAMBLE_ENABLED
+} WMI_LPREAMBLE_STATUS;
+
+typedef enum {
+    WMI_IGNORE_BARKER_IN_ERP = 0,
+    WMI_DONOT_IGNORE_BARKER_IN_ERP
+} WMI_PREAMBLE_POLICY;
+
+typedef PREPACK struct {
+    A_UINT8     status;
+    A_UINT8     preamblePolicy;
+}POSTPACK WMI_SET_LPREAMBLE_CMD;
+
+typedef PREPACK struct {
+    A_UINT16    threshold;
+}POSTPACK WMI_SET_RTS_CMD;
+
+/*
+ *  WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ *  Sets the error reporting event bitmask in target. Target clears it
+ *  upon an error. Subsequent errors are counted, but not reported
+ *  via event, unless the bitmask is set again.
+ */
+typedef PREPACK struct {
+    A_UINT32    bitmask;
+} POSTPACK  WMI_TARGET_ERROR_REPORT_BITMASK;
+
+/*
+ * WMI_SET_TX_PWR_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     dbM;                  /* in dbM units */
+} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
+
+/*
+ * WMI_SET_ASSOC_INFO_CMDID
+ *
+ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
+ * A 3rd one, the CCX version IE can also be set from the host.
+ */
+#define WMI_MAX_ASSOC_INFO_TYPE    2
+#define WMI_CCX_VER_IE             2 /* ieType to set CCX Version IE */
+
+#define WMI_MAX_ASSOC_INFO_LEN     240
+
+typedef PREPACK struct {
+    A_UINT8     ieType;
+    A_UINT8     bufferSize;
+    A_UINT8     assocInfo[1];       /* up to WMI_MAX_ASSOC_INFO_LEN */
+} POSTPACK WMI_SET_ASSOC_INFO_CMD;
+
+
+/*
+ * WMI_GET_TX_PWR_CMDID does not take any parameters
+ */
+
+/*
+ * WMI_ADD_BAD_AP_CMDID
+ */
+#define WMI_MAX_BAD_AP_INDEX      1
+
+typedef PREPACK struct {
+    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_BAD_AP_CMD;
+
+/*
+ * WMI_DELETE_BAD_AP_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
+} POSTPACK WMI_DELETE_BAD_AP_CMD;
+
+/*
+ * WMI_SET_ACCESS_PARAMS_CMDID
+ */
+#define WMI_DEFAULT_TXOP_ACPARAM    0       /* implies one MSDU */
+#define WMI_DEFAULT_ECWMIN_ACPARAM  4       /* corresponds to CWmin of 15 */
+#define WMI_DEFAULT_ECWMAX_ACPARAM  10      /* corresponds to CWmax of 1023 */
+#define WMI_MAX_CW_ACPARAM          15      /* maximum eCWmin or eCWmax */
+#define WMI_DEFAULT_AIFSN_ACPARAM   2
+#define WMI_MAX_AIFSN_ACPARAM       15
+typedef PREPACK struct {
+    A_UINT16 txop;                      /* in units of 32 usec */
+    A_UINT8  eCWmin;
+    A_UINT8  eCWmax;
+    A_UINT8  aifsn;
+    A_UINT8  ac;
+} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
+
+
+/*
+ * WMI_SET_RETRY_LIMITS_CMDID
+ *
+ * This command is used to customize the number of retries the
+ * wlan device will perform on a given frame.
+ */
+#define WMI_MIN_RETRIES 2
+#define WMI_MAX_RETRIES 13
+typedef enum {
+    MGMT_FRAMETYPE    = 0,
+    CONTROL_FRAMETYPE = 1,
+    DATA_FRAMETYPE    = 2
+} WMI_FRAMETYPE;
+
+typedef PREPACK struct {
+    A_UINT8 frameType;                      /* WMI_FRAMETYPE */
+    A_UINT8 trafficClass;                   /* applies only to DATA_FRAMETYPE */
+    A_UINT8 maxRetries;
+    A_UINT8 enableNotify;
+} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
+
+/*
+ * WMI_SET_ROAM_CTRL_CMDID
+ *
+ * This command is used to influence the Roaming behaviour
+ * Set the host biases of the BSSs before setting the roam mode as bias
+ * based.
+ */
+
+/*
+ * Different types of Roam Control
+ */
+
+typedef enum {
+        WMI_FORCE_ROAM          = 1,      /* Roam to the specified BSSID */
+        WMI_SET_ROAM_MODE       = 2,      /* default ,progd bias, no roam */
+        WMI_SET_HOST_BIAS       = 3,     /* Set the Host Bias */
+        WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
+} WMI_ROAM_CTRL_TYPE;
+
+#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
+#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
+
+/*
+ * ROAM MODES
+ */
+
+typedef enum {
+        WMI_DEFAULT_ROAM_MODE   = 1,  /* RSSI based ROAM */
+        WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
+        WMI_LOCK_BSS_MODE  = 3  /* Lock to the Current BSS - no Roam */
+} WMI_ROAM_MODE;
+
+/*
+ * BSS HOST BIAS INFO
+ */
+
+typedef PREPACK struct {
+        A_UINT8 bssid[ATH_MAC_LEN];
+        A_INT8  bias;
+} POSTPACK WMI_BSS_BIAS;
+
+typedef PREPACK struct {
+        A_UINT8 numBss;
+        WMI_BSS_BIAS bssBias[1];
+} POSTPACK WMI_BSS_BIAS_INFO;
+
+typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
+        A_UINT16 lowrssi_scan_period;
+        A_INT16  lowrssi_scan_threshold;
+        A_INT16  lowrssi_roam_threshold;
+        A_UINT8  roam_rssi_floor;
+        A_UINT8  reserved[1];              /* For alignment */
+} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
+
+typedef PREPACK struct {
+    PREPACK union {
+        A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
+        A_UINT8 roamMode;           /* WMI_SET_ROAM_MODE  */
+        WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
+        WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
+    } POSTPACK info;
+    A_UINT8   roamCtrlType ;
+} POSTPACK WMI_SET_ROAM_CTRL_CMD;
+
+/*
+ * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID
+ */
+typedef enum {
+    BT_WLAN_CONN_PRECDENCE_WLAN=0,  /* Default */
+    BT_WLAN_CONN_PRECDENCE_PAL,
+} BT_WLAN_CONN_PRECEDENCE;
+
+typedef PREPACK struct {
+    A_UINT8 precedence;
+} POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE;
+
+/*
+ * WMI_ENABLE_RM_CMDID
+ */
+typedef PREPACK struct {
+        A_BOOL enable_radio_measurements;
+} POSTPACK WMI_ENABLE_RM_CMD;
+
+/*
+ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
+ */
+typedef PREPACK struct {
+        A_UINT8 max_offhome_duration;
+} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 frequency;
+    A_UINT8  threshold;
+} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
+/*---------------------- BTCOEX RELATED -------------------------------------*/
+/*----------------------COMMON to AR6002 and AR6003 -------------------------*/
+typedef enum {
+    BT_STREAM_UNDEF = 0,
+    BT_STREAM_SCO,             /* SCO stream */
+    BT_STREAM_A2DP,            /* A2DP stream */
+    BT_STREAM_SCAN,            /* BT Discovery or Page */
+    BT_STREAM_ESCO,
+    BT_STREAM_MAX
+} BT_STREAM_TYPE;
+
+typedef enum {
+    BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1,
+    BT_PARAM_SCO_PSPOLL_LATENCY_HALF,
+    BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH,
+} BT_PARAMS_SCO_PSPOLL_LATENCY;
+
+typedef enum {
+    BT_PARAMS_SCO_STOMP_SCO_NEVER =1,
+    BT_PARAMS_SCO_STOMP_SCO_ALWAYS,
+    BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI,
+} BT_PARAMS_SCO_STOMP_RULES;
+
+typedef enum {
+    BT_STATUS_UNDEF = 0,
+    BT_STATUS_ON,
+    BT_STATUS_OFF,
+    BT_STATUS_MAX
+} BT_STREAM_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8 streamType;
+    A_UINT8 status;
+} POSTPACK WMI_SET_BT_STATUS_CMD;
+
+typedef enum {
+    BT_ANT_TYPE_UNDEF=0,
+    BT_ANT_TYPE_DUAL,
+    BT_ANT_TYPE_SPLITTER,
+    BT_ANT_TYPE_SWITCH,
+    BT_ANT_TYPE_HIGH_ISO_DUAL
+} BT_ANT_FRONTEND_CONFIG;
+
+typedef enum {
+    BT_COLOCATED_DEV_BTS4020=0,
+    BT_COLCATED_DEV_CSR ,
+    BT_COLOCATED_DEV_VALKYRIE
+} BT_COLOCATED_DEV_TYPE;
+
+/*********************** Applicable to AR6002 ONLY ******************************/
+
+typedef enum {
+    BT_PARAM_SCO = 1,         /* SCO stream parameters */
+    BT_PARAM_A2DP ,
+    BT_PARAM_ANTENNA_CONFIG,
+    BT_PARAM_COLOCATED_BT_DEVICE,
+    BT_PARAM_ACLCOEX,
+    BT_PARAM_11A_SEPARATE_ANT,
+    BT_PARAM_MAX
+} BT_PARAM_TYPE;
+
+
+#define BT_SCO_ALLOW_CLOSE_RANGE_OPT    (1 << 0)
+#define BT_SCO_FORCE_AWAKE_OPT          (1 << 1)
+#define BT_SCO_SET_RSSI_OVERRIDE(flags)        ((flags) |= (1 << 2))
+#define BT_SCO_GET_RSSI_OVERRIDE(flags)        (((flags) >> 2) & 0x1)
+#define BT_SCO_SET_RTS_OVERRIDE(flags)   ((flags) |= (1 << 3))
+#define BT_SCO_GET_RTS_OVERRIDE(flags)   (((flags) >> 3) & 0x1)
+#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags)     (((flags) >> 8) & 0xFF)
+#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags)     (((flags) >> 16) & 0xFF)
+#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+    A_UINT32 numScoCyclesForceTrigger;  /* Number SCO cycles after which
+                                           force a pspoll. default = 10 */
+    A_UINT32 dataResponseTimeout;       /* Timeout Waiting for Downlink pkt
+                                           in response for ps-poll,
+                                           default = 10 msecs */
+    A_UINT32  stompScoRules;
+    A_UINT32 scoOptFlags;               /* SCO Options Flags :
+                                            bits:     meaning:
+                                             0        Allow Close Range Optimization
+                                             1        Force awake during close range
+                                             2        If set use host supplied RSSI for OPT
+                                             3        If set use host supplied RTS COUNT for OPT
+                                             4..7     Unused
+                                             8..15    Low Data Rate Min Cnt
+                                             16..23   Low Data Rate Max Cnt
+                                        */
+
+    A_UINT8 stompDutyCyleVal;           /* Sco cycles to limit ps-poll queuing
+                                           if stomped */
+    A_UINT8 stompDutyCyleMaxVal;        /*firm ware increases stomp duty cycle
+                                          gradually uptill this value on need basis*/
+    A_UINT8 psPollLatencyFraction;      /* Fraction of idle
+                                           period, within which
+                                           additional ps-polls
+                                           can be queued */
+    A_UINT8 noSCOSlots;                 /* Number of SCO Tx/Rx slots.
+                                           HVx, EV3, 2EV3 = 2 */
+    A_UINT8 noIdleSlots;                /* Number of Bluetooth idle slots between
+                                           consecutive SCO Tx/Rx slots
+                                           HVx, EV3 = 4
+                                           2EV3 = 10 */
+    A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/
+    A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/
+    A_UINT8 scoOptRtsCount;
+} POSTPACK BT_PARAMS_SCO;
+
+#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT  (1 << 0)
+#define BT_A2DP_FORCE_AWAKE_OPT        (1 << 1)
+#define BT_A2DP_SET_RSSI_OVERRIDE(flags)        ((flags) |= (1 << 2))
+#define BT_A2DP_GET_RSSI_OVERRIDE(flags)        (((flags) >> 2) & 0x1)
+#define BT_A2DP_SET_RTS_OVERRIDE(flags)   ((flags) |= (1 << 3))
+#define BT_A2DP_GET_RTS_OVERRIDE(flags)   (((flags) >> 3) & 0x1)
+#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags)     (((flags) >> 8) & 0xFF)
+#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags)     (((flags) >> 16) & 0xFF)
+#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+    A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for
+                                    wlan, after it identifies the idle time
+                                    default (30 msecs) */
+    A_UINT32 a2dpBurstCntMin;   /* Minimum number of bluetooth data frames
+                                   to replenish Wlan Usage  limit (default 3) */
+    A_UINT32 a2dpDataRespTimeout;
+    A_UINT32 a2dpOptFlags;      /* A2DP Option flags:
+                                       bits:    meaning:
+                                        0       Allow Close Range Optimization
+                                        1       Force awake during close range
+                                        2        If set use host supplied RSSI for OPT
+                                        3        If set use host supplied RTS COUNT for OPT
+                                        4..7    Unused
+                                        8..15   Low Data Rate Min Cnt
+                                        16..23  Low Data Rate Max Cnt
+                                 */
+    A_UINT8 isCoLocatedBtRoleMaster;
+    A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/
+    A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/
+    A_UINT8 a2dpOptRtsCount;
+}POSTPACK BT_PARAMS_A2DP;
+
+/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth
+   (non a2dp).*/
+typedef PREPACK struct {
+    A_UINT32 aclWlanMediumUsageTime;  /* Wlan usage time during Acl (non-a2dp)
+                                       coexistence (default 30 msecs) */
+    A_UINT32 aclBtMediumUsageTime;   /* Bt usage time during acl coexistence
+                                       (default 30 msecs)*/
+    A_UINT32 aclDataRespTimeout;
+    A_UINT32 aclDetectTimeout;      /* ACL coexistence enabled if we get
+                                       10 Pkts in X msec(default 100 msecs) */
+    A_UINT32 aclmaxPktCnt;          /* No of ACL pkts to receive before
+                                         enabling ACL coex */
+
+}POSTPACK BT_PARAMS_ACLCOEX;
+
+typedef PREPACK struct {
+    PREPACK union {
+        BT_PARAMS_SCO scoParams;
+        BT_PARAMS_A2DP a2dpParams;
+        BT_PARAMS_ACLCOEX  aclCoexParams;
+        A_UINT8 antType;         /* 0 -Disabled (default)
+                                     1 - BT_ANT_TYPE_DUAL
+                                     2 - BT_ANT_TYPE_SPLITTER
+                                     3 - BT_ANT_TYPE_SWITCH */
+        A_UINT8 coLocatedBtDev;  /* 0 - BT_COLOCATED_DEV_BTS4020 (default)
+                                     1 - BT_COLCATED_DEV_CSR
+                                     2 - BT_COLOCATED_DEV_VALKYRIe
+                                   */
+    } POSTPACK info;
+    A_UINT8 paramType ;
+} POSTPACK WMI_SET_BT_PARAMS_CMD;
+
+/************************ END AR6002 BTCOEX *******************************/
+/*-----------------------AR6003 BTCOEX -----------------------------------*/
+
+/*  ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/
+/* Indicates front end antenna configuration. This command needs to be issued
+ * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID.
+ * AR6003 enables coexistence and antenna switching based on the configuration.
+ */
+typedef enum {
+    WMI_BTCOEX_NOT_ENABLED = 0,
+    WMI_BTCOEX_FE_ANT_SINGLE =1,
+    WMI_BTCOEX_FE_ANT_DUAL=2,
+    WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3,
+    WMI_BTCOEX_FE_ANT_TYPE_MAX
+}WMI_BTCOEX_FE_ANT_TYPE;
+
+typedef PREPACK struct {
+	A_UINT8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end
+                                2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end
+                                    (for isolations less 35dB, for higher isolation there
+                                    is not need to pass this command).
+                                    (not implemented)
+                              */
+}POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD;
+
+/* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/
+/* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based
+ * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used.
+ */
+typedef PREPACK struct {
+	A_UINT8	btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA)
+                                    2 - CSR BT  (3 wire PTA)
+                                    3 - Atheros 3001 BT (3 wire PTA)
+                                    4 - STE bluetooth (4-wire ePTA)
+                                    5 - Atheros 3002 BT (4-wire MCI)
+                                    defaults= 3 (Atheros 3001 BT )
+                                    */
+}POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD;
+
+/* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/
+/* Configuration parameters during bluetooth inquiry and page. Page configuration
+ * is applicable only on interfaces which can distinguish page (applicable only for ePTA -
+ * STE bluetooth).
+ * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID.
+ * During this the station will be  power-save mode.
+ */
+typedef PREPACK struct {
+	A_UINT32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data
+                                            (via pspoll) is configured by this parameter.
+                                            "default = 10 ms" */
+
+	A_UINT32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state
+                                             for configured duration, after inquiry completion
+                                             . This is to ensure other bluetooth transactions
+                                             (RDP, SDP profiles, link key exchange ...etc)
+                                             goes through smoothly without wifi stomping.
+                                             default = 10 secs*/
+
+	A_UINT32 maxpageStomp;                 /*Applicable only for STE-BT interface. Currently not
+                                             used */
+	A_UINT32 btInquiryPageFlag;           /* Not used */
+}POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD;
+
+/*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/
+/* Configure  SCO parameters. These parameters would be used whenever firmware is indicated
+ * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps.
+ * Opt Mode - station is in awake state and access point can send data to station any time.
+ * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode.
+ */
+typedef PREPACK struct {
+	A_UINT32 scoSlots;					/* Number of SCO Tx/Rx slots.
+										   HVx, EV3, 2EV3 = 2 */
+	A_UINT32 scoIdleSlots;				/* Number of Bluetooth idle slots between
+										   consecutive SCO Tx/Rx slots
+										   HVx, EV3 = 4
+										   2EV3 = 10
+                                         */
+ 	A_UINT32 scoFlags;				   /* SCO Options Flags :
+										  bits:	   meaning:
+ 										  0   Allow Close Range Optimization
+ 										  1   Is EDR capable or Not
+ 										  2       IS Co-located Bt role Master
+							  			 */
+
+    A_UINT32 linkId;                      /* applicable to STE-BT - not used */
+}POSTPACK BTCOEX_SCO_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32  scoCyclesForceTrigger;	/* Number SCO cycles after which
+											force a pspoll. default = 10 */
+    A_UINT32 scoDataResponseTimeout;	 /* Timeout Waiting for Downlink pkt
+											in response for ps-poll,
+											default = 20 msecs */
+
+	A_UINT32 scoStompDutyCyleVal;		 /* not implemented */
+
+	A_UINT32 scoStompDutyCyleMaxVal;     /*Not implemented */
+
+	A_UINT32 scoPsPollLatencyFraction; 	 /* Fraction of idle
+											period, within which
+											additional ps-polls can be queued
+                                            1 - 1/4 of idle duration
+                                            2 - 1/2 of idle duration
+                                            3 - 3/4 of idle duration
+                                            default =2 (1/2)
+                                           */
+}POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in
+                                   opt mode. If exceeds the configured value,
+                                   switch to ps-poll mode
+                                  default = 3 */
+
+	A_UINT32 scoContStompMax;   /* max number of continous stomp allowed in opt mode.
+                                   if excedded switch to pspoll mode
+                                    default = 3 */
+
+	A_UINT32 scoMinlowRateMbps; /* Low rate threshold */
+
+	A_UINT32 scoLowRateCnt;     /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms.
+                                   If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+                                   default = 36
+                                 */
+
+	A_UINT32 scoHighPktRatio;   /*(Total Rx pkts in 100 ms + 1)/
+                                  ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+                                  if exceeded switch/stay in opt mode and if lower switch/stay in  pspoll mode.
+                                  default = 5 (80% of high rates)
+                                 */
+
+	A_UINT32 scoMaxAggrSize;    /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+                                   max number of aggregates if it was negogiated to higher value
+                                   default = 1
+                                   Recommended value Basic rate headsets = 1, EDR (2-EV3)  =4.
+                                 */
+}POSTPACK BTCOEX_OPTMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_SCO_CONFIG scoConfig;
+	BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig;
+	BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig;
+}POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD;
+
+/* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/
+/* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated
+ * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts.
+ * Opt Mode - station is in power save during a2dp bursts and awake in the gaps.
+ * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode.
+ */
+
+typedef PREPACK struct {
+    A_UINT32 a2dpFlags;      /* A2DP Option flags:
+		                        bits:    meaning:
+               		            0       Allow Close Range Optimization
+       	                     	1       IS EDR capable
+       	                     	2       IS Co-located Bt role Master
+                                3       a2dp traffic is high priority
+                             */
+	A_UINT32 linkId;         /* Applicable only to STE-BT - not used */
+
+}POSTPACK BTCOEX_A2DP_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for
+                      			wlan, after it identifies the idle time
+                                default (30 msecs) */
+
+    A_UINT32 a2dpMinBurstCnt;   /* Minimum number of bluetooth data frames
+                  				to replenish Wlan Usage  limit (default 3) */
+
+    A_UINT32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink
+                                     by stomping on  bluetooth
+                                     after ps-poll is acknowledged.
+                                     default = 20 ms
+                                   */
+}POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+	A_UINT32 a2dpMinlowRateMbps;  /* Low rate threshold */
+
+	A_UINT32 a2dpLowRateCnt;    /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms.
+                                   If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+                                   default = 36
+                                 */
+
+	A_UINT32 a2dpHighPktRatio;   /*(Total Rx pkts in 100 ms + 1)/
+                                  ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+                                  if exceeded switch/stay in opt mode and if lower switch/stay in  pspoll mode.
+                                  default = 5 (80% of high rates)
+                                 */
+
+	A_UINT32 a2dpMaxAggrSize;    /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+                                   max number of aggregates if it was negogiated to higher value
+                                   default = 1
+                                  Recommended value Basic rate headsets = 1, EDR (2-EV3)  =8.
+                                 */
+	A_UINT32 a2dpPktStompCnt;    /*number of a2dp pkts that can be stomped per burst.
+                                   default = 6*/
+
+}POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_A2DP_CONFIG a2dpConfig;
+	BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig;
+	BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig;
+}POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD;
+
+/*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/
+/* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be
+ * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection
+ *  which is configured via "aclCoexFlags".
+ * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium.
+ * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration.
+ *             (Not implemented yet)
+ *
+ * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode.
+ */
+
+typedef PREPACK struct {
+    A_UINT32 aclWlanMediumDur; 	    /* Wlan usage time during Acl (non-a2dp)
+                     					coexistence (default 30 msecs)
+                                    */
+
+    A_UINT32 aclBtMediumDur; 	   /* Bt usage time during acl coexistence
+					                     (default 30 msecs)
+                                   */
+
+	A_UINT32 aclDetectTimeout;	   /* ACL coexistence enabled if we get
+    								   10 Pkts in X msec(default 100 msecs)
+                                    */
+
+	 A_UINT32 aclmaxPktCnt;		   /* No of ACL pkts to receive before
+								      enabling ACL coex
+                                      default = 9
+                                   */
+
+	A_UINT32 aclCoexFlags;			/* A2DP Option flags:
+		  	                          bits:    meaning:
+       		                          0       Allow Close Range Optimization
+                    		          1       disable Firmware detection
+                                      (Currently supported configuration is aclCoexFlags =0)
+                      			 	*/
+	A_UINT32 linkId;                /* Applicable only for STE-BT - not used */
+
+}POSTPACK BTCOEX_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 aclDataRespTimeout;   /* Max duration firmware waits for downlink
+                                      by stomping on  bluetooth
+                                      after ps-poll is acknowledged.
+                                     default = 20 ms */
+
+}POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG;
+
+
+/* Not implemented yet*/
+typedef PREPACK struct {
+	A_UINT32 aclCoexMinlowRateMbps;
+	A_UINT32 aclCoexLowRateCnt;
+	A_UINT32 aclCoexHighPktRatio;
+	A_UINT32 aclCoexMaxAggrSize;
+	A_UINT32 aclPktStompCnt;
+}POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+	BTCOEX_ACLCOEX_CONFIG aclCoexConfig;
+	BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig;
+	BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig;
+}POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD;
+
+/* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/
+typedef enum {
+	WMI_BTCOEX_BT_PROFILE_SCO =1,
+	WMI_BTCOEX_BT_PROFILE_A2DP,
+	WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE,
+	WMI_BTCOEX_BT_PROFILE_ACLCOEX,
+}WMI_BTCOEX_BT_PROFILE;
+
+typedef PREPACK struct {
+	A_UINT32 btProfileType;
+	A_UINT32 btOperatingStatus;
+	A_UINT32 btLinkId;
+}WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD;
+
+/*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/
+/* Used for firmware development and debugging */
+typedef PREPACK struct {
+	A_UINT32 btcoexDbgParam1;
+	A_UINT32 btcoexDbgParam2;
+	A_UINT32 btcoexDbgParam3;
+	A_UINT32 btcoexDbgParam4;
+	A_UINT32 btcoexDbgParam5;
+}WMI_SET_BTCOEX_DEBUG_CMD;
+
+/*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */
+/* Command to firmware to get configuration parameters of the bt profile
+ * reported via WMI_BTCOEX_CONFIG_EVENTID */
+typedef PREPACK struct {
+	A_UINT32 btProfileType; /* 1 - SCO
+                               2 - A2DP
+                               3 - INQUIRY_PAGE
+                               4 - ACLCOEX
+                            */
+	A_UINT32 linkId;    /* not used */
+}WMI_GET_BTCOEX_CONFIG_CMD;
+
+/*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */
+/* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID
+ * */
+typedef PREPACK struct {
+	A_UINT32 btProfileType;
+	A_UINT32 linkId; /* not used */
+	PREPACK union {
+		WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd;
+		WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd;
+		WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig;
+        WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd;
+    } POSTPACK info;
+} POSTPACK WMI_BTCOEX_CONFIG_EVENT;
+
+/*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/
+/* Used for firmware development and debugging*/
+typedef PREPACK struct {
+	A_UINT32 highRatePktCnt;
+	A_UINT32 firstBmissCnt;
+	A_UINT32 psPollFailureCnt;
+	A_UINT32 nullFrameFailureCnt;
+	A_UINT32 optModeTransitionCnt;
+}BTCOEX_GENERAL_STATS;
+
+typedef PREPACK struct {
+	A_UINT32	scoStompCntAvg;
+	A_UINT32	scoStompIn100ms;
+	A_UINT32 	scoMaxContStomp;
+	A_UINT32	scoAvgNoRetries;
+	A_UINT32	scoMaxNoRetriesIn100ms;
+}BTCOEX_SCO_STATS;
+
+typedef PREPACK struct {
+	A_UINT32  	a2dpBurstCnt;
+	A_UINT32	a2dpMaxBurstCnt;
+	A_UINT32	a2dpAvgIdletimeIn100ms;
+	A_UINT32	a2dpAvgStompCnt;
+}BTCOEX_A2DP_STATS;
+
+typedef PREPACK struct {
+	A_UINT32	aclPktCntInBtTime;
+	A_UINT32	aclStompCntInWlanTime;
+	A_UINT32	aclPktCntIn100ms;
+}BTCOEX_ACLCOEX_STATS;
+
+typedef PREPACK struct {
+	BTCOEX_GENERAL_STATS coexStats;
+	BTCOEX_SCO_STATS scoStats;
+	BTCOEX_A2DP_STATS a2dpStats;
+	BTCOEX_ACLCOEX_STATS aclCoexStats;
+}WMI_BTCOEX_STATS_EVENT;
+
+
+
+/*--------------------------END OF BTCOEX -------------------------------------*/
+typedef enum {
+    DISCONN_EVT_IN_RECONN = 0,  /* default */
+    NO_DISCONN_EVT_IN_RECONN
+} TARGET_EVENT_REPORT_CONFIG;
+
+typedef PREPACK struct {
+    A_UINT32 evtConfig;
+} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD;
+
+
+typedef PREPACK struct {
+    A_UINT16    cmd_buf_sz;     /* HCI cmd buffer size */
+    A_UINT8     buf[1];         /* Absolute HCI cmd */
+} POSTPACK WMI_HCI_CMD;
+
+/*
+ * Command Replies
+ */
+
+/*
+ * WMI_GET_CHANNEL_LIST_CMDID reply
+ */
+typedef PREPACK struct {
+    A_UINT8     reserved1;
+    A_UINT8     numChannels;            /* number of channels in reply */
+    A_UINT16    channelList[1];         /* channel in Mhz */
+} POSTPACK WMI_CHANNEL_LIST_REPLY;
+
+typedef enum {
+    A_SUCCEEDED = A_OK,
+    A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
+    A_SUCCEEDED_MODIFY_STREAM=251,
+    A_FAILED_INVALID_STREAM = 252,
+    A_FAILED_MAX_THINSTREAMS = 253,
+    A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
+} PSTREAM_REPLY_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8     status;                 /* PSTREAM_REPLY_STATUS */
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficClass;
+    A_UINT8     trafficDirection;       /* DIR_TYPE */
+} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8     status;                 /* PSTREAM_REPLY_STATUS */
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;       /* DIR_TYPE */
+    A_UINT8     trafficClass;
+} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY;
+
+/*
+ * List of Events (target to host)
+ */
+typedef enum {
+    WMI_READY_EVENTID           = 0x1001,
+    WMI_CONNECT_EVENTID,
+    WMI_DISCONNECT_EVENTID,
+    WMI_BSSINFO_EVENTID,
+    WMI_CMDERROR_EVENTID,
+    WMI_REGDOMAIN_EVENTID,
+    WMI_PSTREAM_TIMEOUT_EVENTID,
+    WMI_NEIGHBOR_REPORT_EVENTID,
+    WMI_TKIP_MICERR_EVENTID,
+    WMI_SCAN_COMPLETE_EVENTID,           /* 0x100a */
+    WMI_REPORT_STATISTICS_EVENTID,
+    WMI_RSSI_THRESHOLD_EVENTID,
+    WMI_ERROR_REPORT_EVENTID,
+    WMI_OPT_RX_FRAME_EVENTID,
+    WMI_REPORT_ROAM_TBL_EVENTID,
+    WMI_EXTENSION_EVENTID,
+    WMI_CAC_EVENTID,
+    WMI_SNR_THRESHOLD_EVENTID,
+    WMI_LQ_THRESHOLD_EVENTID,
+    WMI_TX_RETRY_ERR_EVENTID,            /* 0x1014 */
+    WMI_REPORT_ROAM_DATA_EVENTID,
+    WMI_TEST_EVENTID,
+    WMI_APLIST_EVENTID,
+    WMI_GET_WOW_LIST_EVENTID,
+    WMI_GET_PMKID_LIST_EVENTID,
+    WMI_CHANNEL_CHANGE_EVENTID,
+    WMI_PEER_NODE_EVENTID,
+    WMI_PSPOLL_EVENTID,
+    WMI_DTIMEXPIRY_EVENTID,
+    WMI_WLAN_VERSION_EVENTID,
+    WMI_SET_PARAMS_REPLY_EVENTID,
+    WMI_ADDBA_REQ_EVENTID,              /*0x1020 */
+    WMI_ADDBA_RESP_EVENTID,
+    WMI_DELBA_REQ_EVENTID,
+    WMI_TX_COMPLETE_EVENTID,
+    WMI_HCI_EVENT_EVENTID,
+    WMI_ACL_DATA_EVENTID,
+#ifdef WAPI_ENABLE
+    WMI_WAPI_REKEY_EVENTID,
+#endif
+	WMI_REPORT_BTCOEX_STATS_EVENTID,
+	WMI_REPORT_BTCOEX_CONFIG_EVENTID,
+	
+	WMI_THIN_RESERVED_START_EVENTID = 0x8000,
+	/* Events in this range are reserved for thinmode 
+	 * See wmi_thin.h for actual definitions */
+    WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
+
+} WMI_EVENT_ID;
+
+
+typedef enum {
+    WMI_11A_CAPABILITY   = 1,
+    WMI_11G_CAPABILITY   = 2,
+    WMI_11AG_CAPABILITY  = 3,
+    WMI_11NA_CAPABILITY  = 4,
+    WMI_11NG_CAPABILITY  = 5,
+    WMI_11NAG_CAPABILITY = 6,
+    // END CAPABILITY
+    WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
+} WMI_PHY_CAPABILITY;
+
+typedef PREPACK struct {
+    A_UINT8     macaddr[ATH_MAC_LEN];
+    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_1;
+
+typedef PREPACK struct {
+    A_UINT32    version;
+    A_UINT8     macaddr[ATH_MAC_LEN];
+    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_2;
+
+#if defined(ATH_TARGET)
+#ifdef AR6002_REV2
+#define WMI_READY_EVENT WMI_READY_EVENT_1  /* AR6002_REV2 target code */
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2  /* AR6002_REV4 and AR6001 */
+#endif
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */
+#endif
+
+
+/*
+ * Connect Event
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    listenInterval;
+    A_UINT16    beaconInterval;
+    A_UINT32    networkType;
+    A_UINT8     beaconIeLen;
+    A_UINT8     assocReqLen;
+    A_UINT8     assocRespLen;
+    A_UINT8     assocInfo[1];
+} POSTPACK WMI_CONNECT_EVENT;
+
+/*
+ * Disconnect Event
+ */
+typedef enum {
+    NO_NETWORK_AVAIL   = 0x01,
+    LOST_LINK          = 0x02,     /* bmiss */
+    DISCONNECT_CMD     = 0x03,
+    BSS_DISCONNECTED   = 0x04,
+    AUTH_FAILED        = 0x05,
+    ASSOC_FAILED       = 0x06,
+    NO_RESOURCES_AVAIL = 0x07,
+    CSERV_DISCONNECT   = 0x08,
+    INVALID_PROFILE    = 0x0a,
+    DOT11H_CHANNEL_SWITCH = 0x0b,
+    PROFILE_MISMATCH   = 0x0c,
+    CONNECTION_EVICTED = 0x0d,
+} WMI_DISCONNECT_REASON;
+
+typedef PREPACK struct {
+    A_UINT16    protocolReasonStatus;  /* reason code, see 802.11 spec. */
+    A_UINT8     bssid[ATH_MAC_LEN];    /* set if known */
+    A_UINT8     disconnectReason ;      /* see WMI_DISCONNECT_REASON */
+    A_UINT8     assocRespLen;
+    A_UINT8     assocInfo[1];
+} POSTPACK WMI_DISCONNECT_EVENT;
+
+/*
+ * BSS Info Event.
+ * Mechanism used to inform host of the presence and characteristic of
+ * wireless networks present.  Consists of bss info header followed by
+ * the beacon or probe-response frame body.  The 802.11 header is not included.
+ */
+typedef enum {
+    BEACON_FTYPE = 0x1,
+    PROBERESP_FTYPE,
+    ACTION_MGMT_FTYPE,
+    PROBEREQ_FTYPE,
+} WMI_BI_FTYPE;
+
+enum {
+    BSS_ELEMID_CHANSWITCH = 0x01,
+    BSS_ELEMID_ATHEROS = 0x02,
+};
+
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
+    A_UINT8     snr;
+    A_INT16     rssi;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT32    ieMask;
+} POSTPACK WMI_BSS_INFO_HDR;
+
+/*
+ * BSS INFO HDR version 2.0
+ * With 6 bytes HTC header and 6 bytes of WMI header
+ * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management
+ * header space.
+ * - Reduce the ieMask to 2 bytes as only two bit flags are used
+ * - Remove rssi and compute it on the host. rssi = snr - 95
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
+    A_UINT8     snr;
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    ieMask;
+} POSTPACK WMI_BSS_INFO_HDR2;
+
+/*
+ * Command Error Event
+ */
+typedef enum {
+    INVALID_PARAM  = 0x01,
+    ILLEGAL_STATE  = 0x02,
+    INTERNAL_ERROR = 0x03,
+} WMI_ERROR_CODE;
+
+typedef PREPACK struct {
+    A_UINT16    commandId;
+    A_UINT8     errorCode;
+} POSTPACK WMI_CMD_ERROR_EVENT;
+
+/*
+ * New Regulatory Domain Event
+ */
+typedef PREPACK struct {
+    A_UINT32    regDomain;
+} POSTPACK WMI_REG_DOMAIN_EVENT;
+
+typedef PREPACK struct {
+    A_UINT8     txQueueNumber;
+    A_UINT8     rxQueueNumber;
+    A_UINT8     trafficDirection;
+    A_UINT8     trafficClass;
+} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
+
+/*
+ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
+ * the host of BSS's it has found that matches the current profile.
+ * It can be used by the host to cache PMKs and/to initiate pre-authentication
+ * if the BSS supports it.  The first bssid is always the current associated
+ * BSS.
+ * The bssid and bssFlags information repeats according to the number
+ * or APs reported.
+ */
+typedef enum {
+    WMI_DEFAULT_BSS_FLAGS   = 0x00,
+    WMI_PREAUTH_CAPABLE_BSS = 0x01,
+    WMI_PMKID_VALID_BSS     = 0x02,
+} WMI_BSS_FLAGS;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     bssFlags;            /* see WMI_BSS_FLAGS */
+} POSTPACK WMI_NEIGHBOR_INFO;
+
+typedef PREPACK struct {
+    A_INT8      numberOfAps;
+    WMI_NEIGHBOR_INFO neighbor[1];
+} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
+
+/*
+ * TKIP MIC Error Event
+ */
+typedef PREPACK struct {
+    A_UINT8 keyid;
+    A_UINT8 ismcast;
+} POSTPACK WMI_TKIP_MICERR_EVENT;
+
+/*
+ * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
+ */
+typedef PREPACK struct {
+    A_INT32 status;
+} POSTPACK WMI_SCAN_COMPLETE_EVENT;
+
+#define MAX_OPT_DATA_LEN 1400
+
+/*
+ * WMI_SET_ADHOC_BSSID_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
+
+/*
+ * WMI_SET_OPT_MODE_CMDID
+ */
+typedef enum {
+    SPECIAL_OFF,
+    SPECIAL_ON,
+} OPT_MODE_TYPE;
+
+typedef PREPACK struct {
+    A_UINT8     optMode;
+} POSTPACK WMI_SET_OPT_MODE_CMD;
+
+/*
+ * WMI_TX_OPT_FRAME_CMDID
+ */
+typedef enum {
+    OPT_PROBE_REQ   = 0x01,
+    OPT_PROBE_RESP  = 0x02,
+    OPT_CPPP_START  = 0x03,
+    OPT_CPPP_STOP   = 0x04,
+} WMI_OPT_FTYPE;
+
+typedef PREPACK struct {
+    A_UINT16    optIEDataLen;
+    A_UINT8     frmType;
+    A_UINT8     dstAddr[ATH_MAC_LEN];
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT8     reserved;               /* For alignment */
+    A_UINT8     optIEData[1];
+} POSTPACK WMI_OPT_TX_FRAME_CMD;
+
+/*
+ * Special frame receive Event.
+ * Mechanism used to inform host of the receiption of the special frames.
+ * Consists of special frame info header followed by special frame body.
+ * The 802.11 header is not included.
+ */
+typedef PREPACK struct {
+    A_UINT16    channel;
+    A_UINT8     frameType;          /* see WMI_OPT_FTYPE */
+    A_INT8      snr;
+    A_UINT8     srcAddr[ATH_MAC_LEN];
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_OPT_RX_INFO_HDR;
+
+/*
+ * Reporting statistics.
+ */
+typedef PREPACK struct {
+    A_UINT32   tx_packets;
+    A_UINT32   tx_bytes;
+    A_UINT32   tx_unicast_pkts;
+    A_UINT32   tx_unicast_bytes;
+    A_UINT32   tx_multicast_pkts;
+    A_UINT32   tx_multicast_bytes;
+    A_UINT32   tx_broadcast_pkts;
+    A_UINT32   tx_broadcast_bytes;
+    A_UINT32   tx_rts_success_cnt;
+    A_UINT32   tx_packet_per_ac[4];
+    A_UINT32   tx_errors_per_ac[4];
+
+    A_UINT32   tx_errors;
+    A_UINT32   tx_failed_cnt;
+    A_UINT32   tx_retry_cnt;
+    A_UINT32   tx_mult_retry_cnt;
+    A_UINT32   tx_rts_fail_cnt;
+    A_INT32    tx_unicast_rate;
+}POSTPACK tx_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   rx_packets;
+    A_UINT32   rx_bytes;
+    A_UINT32   rx_unicast_pkts;
+    A_UINT32   rx_unicast_bytes;
+    A_UINT32   rx_multicast_pkts;
+    A_UINT32   rx_multicast_bytes;
+    A_UINT32   rx_broadcast_pkts;
+    A_UINT32   rx_broadcast_bytes;
+    A_UINT32   rx_fragment_pkt;
+
+    A_UINT32   rx_errors;
+    A_UINT32   rx_crcerr;
+    A_UINT32   rx_key_cache_miss;
+    A_UINT32   rx_decrypt_err;
+    A_UINT32   rx_duplicate_frames;
+    A_INT32    rx_unicast_rate;
+}POSTPACK rx_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   tkip_local_mic_failure;
+    A_UINT32   tkip_counter_measures_invoked;
+    A_UINT32   tkip_replays;
+    A_UINT32   tkip_format_errors;
+    A_UINT32   ccmp_format_errors;
+    A_UINT32   ccmp_replays;
+}POSTPACK tkip_ccmp_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32   power_save_failure_cnt;
+    A_UINT16   stop_tx_failure_cnt;
+    A_UINT16   atim_tx_failure_cnt;
+    A_UINT16   atim_rx_failure_cnt;
+    A_UINT16   bcn_rx_failure_cnt;
+}POSTPACK pm_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    cs_bmiss_cnt;
+    A_UINT32    cs_lowRssi_cnt;
+    A_UINT16    cs_connect_cnt;
+    A_UINT16    cs_disconnect_cnt;
+    A_INT16     cs_aveBeacon_rssi;
+    A_UINT16    cs_roam_count;
+    A_INT16     cs_rssi;
+    A_UINT8     cs_snr;
+    A_UINT8     cs_aveBeacon_snr;
+    A_UINT8     cs_lastRoam_msec;
+} POSTPACK cserv_stats_t;
+
+typedef PREPACK struct {
+    tx_stats_t          tx_stats;
+    rx_stats_t          rx_stats;
+    tkip_ccmp_stats_t   tkipCcmpStats;
+}POSTPACK wlan_net_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    arp_received;
+    A_UINT32    arp_matched;
+    A_UINT32    arp_replied;
+} POSTPACK arp_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32    wow_num_pkts_dropped;
+    A_UINT16    wow_num_events_discarded;
+    A_UINT8     wow_num_host_pkt_wakeups;
+    A_UINT8     wow_num_host_event_wakeups;
+} POSTPACK wlan_wow_stats_t;
+
+typedef PREPACK struct {
+    A_UINT32            lqVal;
+    A_INT32             noise_floor_calibation;
+    pm_stats_t          pmStats;
+    wlan_net_stats_t    txrxStats;
+    wlan_wow_stats_t    wowStats;
+    arp_stats_t         arpStats;
+    cserv_stats_t       cservStats;
+} POSTPACK WMI_TARGET_STATS;
+
+/*
+ * WMI_RSSI_THRESHOLD_EVENTID.
+ * Indicate the RSSI events to host. Events are indicated when we breach a
+ * thresold value.
+ */
+typedef enum{
+    WMI_RSSI_THRESHOLD1_ABOVE = 0,
+    WMI_RSSI_THRESHOLD2_ABOVE,
+    WMI_RSSI_THRESHOLD3_ABOVE,
+    WMI_RSSI_THRESHOLD4_ABOVE,
+    WMI_RSSI_THRESHOLD5_ABOVE,
+    WMI_RSSI_THRESHOLD6_ABOVE,
+    WMI_RSSI_THRESHOLD1_BELOW,
+    WMI_RSSI_THRESHOLD2_BELOW,
+    WMI_RSSI_THRESHOLD3_BELOW,
+    WMI_RSSI_THRESHOLD4_BELOW,
+    WMI_RSSI_THRESHOLD5_BELOW,
+    WMI_RSSI_THRESHOLD6_BELOW
+}WMI_RSSI_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_INT16 rssi;
+    A_UINT8 range;
+}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
+
+/*
+ *  WMI_ERROR_REPORT_EVENTID
+ */
+typedef enum{
+    WMI_TARGET_PM_ERR_FAIL      = 0x00000001,
+    WMI_TARGET_KEY_NOT_FOUND    = 0x00000002,
+    WMI_TARGET_DECRYPTION_ERR   = 0x00000004,
+    WMI_TARGET_BMISS            = 0x00000008,
+    WMI_PSDISABLE_NODE_JOIN     = 0x00000010,
+    WMI_TARGET_COM_ERR          = 0x00000020,
+    WMI_TARGET_FATAL_ERR        = 0x00000040
+} WMI_TARGET_ERROR_VAL;
+
+typedef PREPACK struct {
+    A_UINT32 errorVal;
+}POSTPACK  WMI_TARGET_ERROR_REPORT_EVENT;
+
+typedef PREPACK struct {
+    A_UINT8 retrys;
+}POSTPACK  WMI_TX_RETRY_ERR_EVENT;
+
+typedef enum{
+    WMI_SNR_THRESHOLD1_ABOVE = 1,
+    WMI_SNR_THRESHOLD1_BELOW,
+    WMI_SNR_THRESHOLD2_ABOVE,
+    WMI_SNR_THRESHOLD2_BELOW,
+    WMI_SNR_THRESHOLD3_ABOVE,
+    WMI_SNR_THRESHOLD3_BELOW,
+    WMI_SNR_THRESHOLD4_ABOVE,
+    WMI_SNR_THRESHOLD4_BELOW
+} WMI_SNR_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_UINT8 range;  /* WMI_SNR_THRESHOLD_VAL */
+    A_UINT8 snr;
+}POSTPACK  WMI_SNR_THRESHOLD_EVENT;
+
+typedef enum{
+    WMI_LQ_THRESHOLD1_ABOVE = 1,
+    WMI_LQ_THRESHOLD1_BELOW,
+    WMI_LQ_THRESHOLD2_ABOVE,
+    WMI_LQ_THRESHOLD2_BELOW,
+    WMI_LQ_THRESHOLD3_ABOVE,
+    WMI_LQ_THRESHOLD3_BELOW,
+    WMI_LQ_THRESHOLD4_ABOVE,
+    WMI_LQ_THRESHOLD4_BELOW
+} WMI_LQ_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+    A_INT32 lq;
+    A_UINT8 range;  /* WMI_LQ_THRESHOLD_VAL */
+}POSTPACK  WMI_LQ_THRESHOLD_EVENT;
+/*
+ * WMI_REPORT_ROAM_TBL_EVENTID
+ */
+#define MAX_ROAM_TBL_CAND   5
+
+typedef PREPACK struct {
+    A_INT32 roam_util;
+    A_UINT8 bssid[ATH_MAC_LEN];
+    A_INT8  rssi;
+    A_INT8  rssidt;
+    A_INT8  last_rssi;
+    A_INT8  util;
+    A_INT8  bias;
+    A_UINT8 reserved; /* For alignment */
+} POSTPACK WMI_BSS_ROAM_INFO;
+
+
+typedef PREPACK struct {
+    A_UINT16  roamMode;
+    A_UINT16  numEntries;
+    WMI_BSS_ROAM_INFO bssRoamInfo[1];
+} POSTPACK WMI_TARGET_ROAM_TBL;
+
+/*
+ * WMI_HCI_EVENT_EVENTID
+ */
+typedef PREPACK struct {
+    A_UINT16    evt_buf_sz;     /* HCI event buffer size */
+    A_UINT8     buf[1];         /* HCI  event */
+} POSTPACK WMI_HCI_EVENT;
+
+/*
+ *  WMI_CAC_EVENTID
+ */
+typedef enum {
+    CAC_INDICATION_ADMISSION = 0x00,
+    CAC_INDICATION_ADMISSION_RESP = 0x01,
+    CAC_INDICATION_DELETE = 0x02,
+    CAC_INDICATION_NO_RESP = 0x03,
+}CAC_INDICATION;
+
+#define WMM_TSPEC_IE_LEN   63
+
+typedef PREPACK struct {
+    A_UINT8 ac;
+    A_UINT8 cac_indication;
+    A_UINT8 statusCode;
+    A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
+}POSTPACK  WMI_CAC_EVENT;
+
+/*
+ * WMI_APLIST_EVENTID
+ */
+
+typedef enum {
+    APLIST_VER1 = 1,
+} APLIST_VER;
+
+typedef PREPACK struct {
+    A_UINT8     bssid[ATH_MAC_LEN];
+    A_UINT16    channel;
+} POSTPACK  WMI_AP_INFO_V1;
+
+typedef PREPACK union {
+    WMI_AP_INFO_V1  apInfoV1;
+} POSTPACK WMI_AP_INFO;
+
+typedef PREPACK struct {
+    A_UINT8     apListVer;
+    A_UINT8     numAP;
+    WMI_AP_INFO apList[1];
+} POSTPACK WMI_APLIST_EVENT;
+
+/*
+ * developer commands
+ */
+
+/*
+ * WMI_SET_BITRATE_CMDID
+ *
+ * Get bit rate cmd uses same definition as set bit rate cmd
+ */
+typedef enum {
+    RATE_AUTO   = -1,
+    RATE_1Mb    = 0,
+    RATE_2Mb    = 1,
+    RATE_5_5Mb  = 2,
+    RATE_11Mb   = 3,
+    RATE_6Mb    = 4,
+    RATE_9Mb    = 5,
+    RATE_12Mb   = 6,
+    RATE_18Mb   = 7,
+    RATE_24Mb   = 8,
+    RATE_36Mb   = 9,
+    RATE_48Mb   = 10,
+    RATE_54Mb   = 11,
+    RATE_MCS_0_20 = 12,
+    RATE_MCS_1_20 = 13,
+    RATE_MCS_2_20 = 14,
+    RATE_MCS_3_20 = 15,
+    RATE_MCS_4_20 = 16,
+    RATE_MCS_5_20 = 17,
+    RATE_MCS_6_20 = 18,
+    RATE_MCS_7_20 = 19,
+    RATE_MCS_0_40 = 20,
+    RATE_MCS_1_40 = 21,
+    RATE_MCS_2_40 = 22,
+    RATE_MCS_3_40 = 23,
+    RATE_MCS_4_40 = 24,
+    RATE_MCS_5_40 = 25,
+    RATE_MCS_6_40 = 26,
+    RATE_MCS_7_40 = 27,
+} WMI_BIT_RATE;
+
+typedef PREPACK struct {
+    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
+    A_INT8      mgmtRateIndex;
+    A_INT8      ctlRateIndex;
+} POSTPACK WMI_BIT_RATE_CMD;
+
+
+typedef PREPACK struct {
+    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
+} POSTPACK  WMI_BIT_RATE_REPLY;
+
+
+/*
+ * WMI_SET_FIXRATES_CMDID
+ *
+ * Get fix rates cmd uses same definition as set fix rates cmd
+ */
+#define FIX_RATE_1Mb            ((A_UINT32)0x1)
+#define FIX_RATE_2Mb            ((A_UINT32)0x2)
+#define FIX_RATE_5_5Mb          ((A_UINT32)0x4)
+#define FIX_RATE_11Mb           ((A_UINT32)0x8)
+#define FIX_RATE_6Mb            ((A_UINT32)0x10)
+#define FIX_RATE_9Mb            ((A_UINT32)0x20)
+#define FIX_RATE_12Mb           ((A_UINT32)0x40)
+#define FIX_RATE_18Mb           ((A_UINT32)0x80)
+#define FIX_RATE_24Mb           ((A_UINT32)0x100)
+#define FIX_RATE_36Mb           ((A_UINT32)0x200)
+#define FIX_RATE_48Mb           ((A_UINT32)0x400)
+#define FIX_RATE_54Mb           ((A_UINT32)0x800)
+#define FIX_RATE_MCS_0_20       ((A_UINT32)0x1000)
+#define FIX_RATE_MCS_1_20       ((A_UINT32)0x2000)
+#define FIX_RATE_MCS_2_20       ((A_UINT32)0x4000)
+#define FIX_RATE_MCS_3_20       ((A_UINT32)0x8000)
+#define FIX_RATE_MCS_4_20       ((A_UINT32)0x10000)
+#define FIX_RATE_MCS_5_20       ((A_UINT32)0x20000)
+#define FIX_RATE_MCS_6_20       ((A_UINT32)0x40000)
+#define FIX_RATE_MCS_7_20       ((A_UINT32)0x80000)
+#define FIX_RATE_MCS_0_40       ((A_UINT32)0x100000)
+#define FIX_RATE_MCS_1_40       ((A_UINT32)0x200000)
+#define FIX_RATE_MCS_2_40       ((A_UINT32)0x400000)
+#define FIX_RATE_MCS_3_40       ((A_UINT32)0x800000)
+#define FIX_RATE_MCS_4_40       ((A_UINT32)0x1000000)
+#define FIX_RATE_MCS_5_40       ((A_UINT32)0x2000000)
+#define FIX_RATE_MCS_6_40       ((A_UINT32)0x4000000)
+#define FIX_RATE_MCS_7_40       ((A_UINT32)0x8000000)
+
+typedef PREPACK struct {
+    A_UINT32      fixRateMask;          /* see WMI_BIT_RATE */
+} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8        bEnableMask;
+    A_UINT8        frameType;               /*type and subtype*/
+    A_UINT32     frameRateMask;          /* see WMI_BIT_RATE */
+} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY;
+
+/*
+ * WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+    RECONN_DO_AUTH = 0x00,
+    RECONN_NOT_AUTH = 0x01
+} WMI_AUTH_MODE;
+
+typedef PREPACK struct {
+    A_UINT8 mode;
+} POSTPACK WMI_SET_AUTH_MODE_CMD;
+
+/*
+ * WMI_SET_REASSOC_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+    REASSOC_DO_DISASSOC = 0x00,
+    REASSOC_DONOT_DISASSOC = 0x01
+} WMI_REASSOC_MODE;
+
+typedef PREPACK struct {
+    A_UINT8 mode;
+}POSTPACK WMI_SET_REASSOC_MODE_CMD;
+
+typedef enum {
+    ROAM_DATA_TIME = 1,            /* Get The Roam Time Data */
+} ROAM_DATA_TYPE;
+
+typedef PREPACK struct {
+    A_UINT32        disassoc_time;
+    A_UINT32        no_txrx_time;
+    A_UINT32        assoc_time;
+    A_UINT32        allow_txrx_time;
+    A_UINT8         disassoc_bssid[ATH_MAC_LEN];
+    A_INT8          disassoc_bss_rssi;
+    A_UINT8         assoc_bssid[ATH_MAC_LEN];
+    A_INT8          assoc_bss_rssi;
+} POSTPACK WMI_TARGET_ROAM_TIME;
+
+typedef PREPACK struct {
+    PREPACK union {
+        WMI_TARGET_ROAM_TIME roamTime;
+    } POSTPACK u;
+    A_UINT8 roamDataType ;
+} POSTPACK WMI_TARGET_ROAM_DATA;
+
+typedef enum {
+    WMI_WMM_DISABLED = 0,
+    WMI_WMM_ENABLED
+} WMI_WMM_STATUS;
+
+typedef PREPACK struct {
+    A_UINT8    status;
+}POSTPACK WMI_SET_WMM_CMD;
+
+typedef PREPACK struct {
+    A_UINT8    status;
+}POSTPACK WMI_SET_QOS_SUPP_CMD;
+
+typedef enum {
+    WMI_TXOP_DISABLED = 0,
+    WMI_TXOP_ENABLED
+} WMI_TXOP_CFG;
+
+typedef PREPACK struct {
+    A_UINT8    txopEnable;
+}POSTPACK WMI_SET_WMM_TXOP_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 keepaliveInterval;
+} POSTPACK WMI_SET_KEEPALIVE_CMD;
+
+typedef PREPACK struct {
+    A_BOOL configured;
+    A_UINT8 keepaliveInterval;
+} POSTPACK WMI_GET_KEEPALIVE_CMD;
+
+/*
+ * Add Application specified IE to a management frame
+ */
+#define WMI_MAX_IE_LEN  255
+
+typedef PREPACK struct {
+    A_UINT8 mgmtFrmType;  /* one of WMI_MGMT_FRAME_TYPE */
+    A_UINT8 ieLen;    /* Length  of the IE that should be added to the MGMT frame */
+    A_UINT8 ieInfo[1];
+} POSTPACK WMI_SET_APPIE_CMD;
+
+/*
+ * Notify the WSC registration status to the target
+ */
+#define WSC_REG_ACTIVE     1
+#define WSC_REG_INACTIVE   0
+/* Generic Hal Interface for setting hal paramters. */
+/* Add new Set HAL Param cmdIds here for newer params */
+typedef enum {
+   WHAL_SETCABTO_CMDID = 1,
+}WHAL_CMDID;
+
+typedef PREPACK struct {
+    A_UINT8 cabTimeOut;
+} POSTPACK WHAL_SETCABTO_PARAM;
+
+typedef PREPACK struct {
+    A_UINT8  whalCmdId;
+    A_UINT8 data[1];
+} POSTPACK WHAL_PARAMCMD;
+
+
+#define WOW_MAX_FILTER_LISTS 1 /*4*/
+#define WOW_MAX_FILTERS_PER_LIST 4
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+#define MAC_MAX_FILTERS_PER_LIST 4
+
+typedef PREPACK struct {
+    A_UINT8 wow_valid_filter;
+    A_UINT8 wow_filter_id;
+    A_UINT8 wow_filter_size;
+    A_UINT8 wow_filter_offset;
+    A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
+    A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
+} POSTPACK WOW_FILTER;
+
+
+typedef PREPACK struct {
+    A_UINT8 wow_valid_list;
+    A_UINT8 wow_list_id;
+    A_UINT8 wow_num_filters;
+    A_UINT8 wow_total_list_size;
+    WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
+} POSTPACK WOW_FILTER_LIST;
+
+typedef PREPACK struct {
+    A_UINT8 valid_filter;
+    A_UINT8 mac_addr[ATH_MAC_LEN];
+} POSTPACK MAC_FILTER;
+
+
+typedef PREPACK struct {
+    A_UINT8 total_list_size;
+    A_UINT8 enable;
+    MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST];
+} POSTPACK MAC_FILTER_LIST;
+
+#define MAX_IP_ADDRS  2
+typedef PREPACK struct {
+    A_UINT32 ips[MAX_IP_ADDRS];  /* IP in Network Byte Order */
+} POSTPACK WMI_SET_IP_CMD;
+
+typedef PREPACK struct {
+    A_BOOL awake;
+    A_BOOL asleep;
+} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
+
+typedef enum {
+    WOW_FILTER_SSID = 0x1
+} WMI_WOW_FILTER;
+
+typedef PREPACK struct {
+    A_BOOL enable_wow;
+    WMI_WOW_FILTER filter;
+} POSTPACK WMI_SET_WOW_MODE_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 filter_list_id;
+} POSTPACK WMI_GET_WOW_LIST_CMD;
+
+/*
+ * WMI_GET_WOW_LIST_CMD reply
+ */
+typedef PREPACK struct {
+    A_UINT8     num_filters;     /* number of patterns in reply */
+    A_UINT8     this_filter_num; /*  this is filter # x of total num_filters */
+    A_UINT8     wow_mode;
+    A_UINT8     host_mode;
+    WOW_FILTER  wow_filters[1];
+} POSTPACK WMI_GET_WOW_LIST_REPLY;
+
+typedef PREPACK struct {
+    A_UINT8 filter_list_id;
+    A_UINT8 filter_size;
+    A_UINT8 filter_offset;
+    A_UINT8 filter[1];
+} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+    A_UINT16 filter_list_id;
+    A_UINT16 filter_id;
+} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
+
+/*
+ * WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define WMI_AKMP_MULTI_PMKID_EN   0x000001
+
+typedef PREPACK struct {
+    A_UINT32    akmpInfo;
+} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_PMKID;
+
+/*
+ * WMI_SET_PMKID_LIST_CMD
+ */
+#define WMI_MAX_PMKID_CACHE   8
+
+typedef PREPACK struct {
+    A_UINT32    numPMKID;
+    WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
+} POSTPACK WMI_SET_PMKID_LIST_CMD;
+
+/*
+ * WMI_GET_PMKID_LIST_CMD  Reply
+ * Following the Number of PMKIDs is the list of PMKIDs
+ */
+typedef PREPACK struct {
+    A_UINT32    numPMKID;
+    A_UINT8     bssidList[ATH_MAC_LEN][1];
+    WMI_PMKID   pmkidList[1];
+} POSTPACK WMI_PMKID_LIST_REPLY;
+
+typedef PREPACK struct {
+    A_UINT16 oldChannel;
+    A_UINT32 newChannel;
+} POSTPACK WMI_CHANNEL_CHANGE_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32 version;
+} POSTPACK WMI_WLAN_VERSION_EVENT;
+
+
+/* WMI_ADDBA_REQ_EVENTID */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     win_sz;
+    A_UINT16    st_seq_no;
+    A_UINT8     status;         /* f/w response for ADDBA Req; OK(0) or failure(!=0) */
+} POSTPACK WMI_ADDBA_REQ_EVENT;
+
+/* WMI_ADDBA_RESP_EVENTID */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     status;         /* OK(0), failure (!=0) */
+    A_UINT16    amsdu_sz;       /* Three values: Not supported(0), 3839, 8k */
+} POSTPACK WMI_ADDBA_RESP_EVENT;
+
+/* WMI_DELBA_EVENTID
+ * f/w received a DELBA for peer and processed it.
+ * Host is notified of this
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     is_peer_initiator;
+    A_UINT16    reason_code;
+} POSTPACK WMI_DELBA_EVENT;
+
+
+#ifdef WAPI_ENABLE
+#define WAPI_REKEY_UCAST    1
+#define WAPI_REKEY_MCAST    2
+typedef PREPACK struct {
+    A_UINT8     type;
+    A_UINT8     macAddr[ATH_MAC_LEN];
+} POSTPACK WMI_WAPIREKEY_EVENT;
+#endif
+
+
+/* WMI_ALLOW_AGGR_CMDID
+ * Configures tid's to allow ADDBA negotiations
+ * on each tid, in each direction
+ */
+typedef PREPACK struct {
+    A_UINT16    tx_allow_aggr;  /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/
+    A_UINT16    rx_allow_aggr;  /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/
+} POSTPACK WMI_ALLOW_AGGR_CMD;
+
+/* WMI_ADDBA_REQ_CMDID
+ * f/w starts performing ADDBA negotiations with peer
+ * on the given tid
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+} POSTPACK WMI_ADDBA_REQ_CMD;
+
+/* WMI_DELBA_REQ_CMDID
+ * f/w would teardown BA with peer.
+ * is_send_initiator indicates if it's or tx or rx side
+ */
+typedef PREPACK struct {
+    A_UINT8     tid;
+    A_UINT8     is_sender_initiator;
+
+} POSTPACK WMI_DELBA_REQ_CMD;
+
+#define PEER_NODE_JOIN_EVENT 0x00
+#define PEER_NODE_LEAVE_EVENT 0x01
+#define PEER_FIRST_NODE_JOIN_EVENT 0x10
+#define PEER_LAST_NODE_LEAVE_EVENT 0x11
+typedef PREPACK struct {
+    A_UINT8 eventCode;
+    A_UINT8 peerMacAddr[ATH_MAC_LEN];
+} POSTPACK WMI_PEER_NODE_EVENT;
+
+#define IEEE80211_FRAME_TYPE_MGT          0x00
+#define IEEE80211_FRAME_TYPE_CTL          0x04
+
+/*
+ * Transmit complete event data structure(s)
+ */
+
+
+typedef PREPACK struct {
+#define TX_COMPLETE_STATUS_SUCCESS 0
+#define TX_COMPLETE_STATUS_RETRIES 1
+#define TX_COMPLETE_STATUS_NOLINK  2
+#define TX_COMPLETE_STATUS_TIMEOUT 3
+#define TX_COMPLETE_STATUS_OTHER   4
+
+    A_UINT8 status; /* one of TX_COMPLETE_STATUS_... */
+    A_UINT8 pktID; /* packet ID to identify parent packet */
+    A_UINT8 rateIdx; /* rate index on successful transmission */
+    A_UINT8 ackFailures; /* number of ACK failures in tx attempt */
+#if 0 /* optional params currently ommitted. */
+    A_UINT32 queueDelay; // usec delay measured Tx Start time - host delivery time
+    A_UINT32 mediaDelay; // usec delay measured ACK rx time - host delivery time
+#endif
+} POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */
+
+typedef PREPACK struct {
+    A_UINT8 numMessages; /* number of tx comp msgs following this struct */
+    A_UINT8 msgLen; /* length in bytes for each individual msg following this struct */
+    A_UINT8 msgType; /* version of tx complete msg data following this struct */
+    A_UINT8 reserved; /* individual messages follow this header */
+} POSTPACK WMI_TX_COMPLETE_EVENT;
+
+#define WMI_TXCOMPLETE_VERSION_1 (0x01)
+
+
+/*
+ * ------- AP Mode definitions --------------
+ */
+
+/*
+ * !!! Warning !!!
+ * -Changing the following values needs compilation of both driver and firmware
+ */
+#ifdef AR6002_REV2
+#define AP_MAX_NUM_STA          4
+#else
+#define AP_MAX_NUM_STA          8
+#endif
+#define AP_ACL_SIZE             10
+#define IEEE80211_MAX_IE        256
+#define MCAST_AID               0xFF /* Spl. AID used to set DTIM flag in the beacons */
+#define DEF_AP_COUNTRY_CODE     "US "
+#define DEF_AP_WMODE_G          WMI_11G_MODE
+#define DEF_AP_WMODE_AG         WMI_11AG_MODE
+#define DEF_AP_DTIM             5
+#define DEF_BEACON_INTERVAL     100
+
+/* AP mode disconnect reasons */
+#define AP_DISCONNECT_STA_LEFT      101
+#define AP_DISCONNECT_FROM_HOST     102
+#define AP_DISCONNECT_COMM_TIMEOUT  103
+
+/*
+ * Used with WMI_AP_HIDDEN_SSID_CMDID
+ */
+#define HIDDEN_SSID_FALSE   0
+#define HIDDEN_SSID_TRUE    1
+typedef PREPACK struct {
+    A_UINT8     hidden_ssid;
+} POSTPACK WMI_AP_HIDDEN_SSID_CMD;
+
+/*
+ * Used with WMI_AP_ACL_POLICY_CMDID
+ */
+#define AP_ACL_DISABLE          0x00
+#define AP_ACL_ALLOW_MAC        0x01
+#define AP_ACL_DENY_MAC         0x02
+#define AP_ACL_RETAIN_LIST_MASK 0x80
+typedef PREPACK struct {
+    A_UINT8     policy;
+} POSTPACK WMI_AP_ACL_POLICY_CMD;
+
+/*
+ * Used with WMI_AP_ACL_MAC_LIST_CMDID
+ */
+#define ADD_MAC_ADDR    1
+#define DEL_MAC_ADDR    2
+typedef PREPACK struct {
+    A_UINT8     action;
+    A_UINT8     index;
+    A_UINT8     mac[ATH_MAC_LEN];
+    A_UINT8     wildcard;
+} POSTPACK WMI_AP_ACL_MAC_CMD;
+
+typedef PREPACK struct {
+    A_UINT16    index;
+    A_UINT8     acl_mac[AP_ACL_SIZE][ATH_MAC_LEN];
+    A_UINT8     wildcard[AP_ACL_SIZE];
+    A_UINT8     policy;
+} POSTPACK WMI_AP_ACL;
+
+/*
+ * Used with WMI_AP_SET_NUM_STA_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8     num_sta;
+} POSTPACK WMI_AP_SET_NUM_STA_CMD;
+
+/*
+ * Used with WMI_AP_SET_MLME_CMDID
+ */
+typedef PREPACK struct {
+    A_UINT8    mac[ATH_MAC_LEN];
+    A_UINT16   reason;              /* 802.11 reason code */
+    A_UINT8    cmd;                 /* operation to perform */
+#define WMI_AP_MLME_ASSOC       1   /* associate station */
+#define WMI_AP_DISASSOC         2   /* disassociate station */
+#define WMI_AP_DEAUTH           3   /* deauthenticate station */
+#define WMI_AP_MLME_AUTHORIZE   4   /* authorize station */
+#define WMI_AP_MLME_UNAUTHORIZE 5   /* unauthorize station */
+} POSTPACK WMI_AP_SET_MLME_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 period;
+} POSTPACK WMI_AP_CONN_INACT_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 period_min;
+    A_UINT32 dwell_ms;
+} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD;
+
+typedef PREPACK struct {
+    A_BOOL flag;
+    A_UINT16 aid;
+} POSTPACK WMI_AP_SET_PVB_CMD;
+
+#define WMI_DISABLE_REGULATORY_CODE "FF"
+
+typedef PREPACK struct {
+    A_UCHAR countryCode[3];
+} POSTPACK WMI_AP_SET_COUNTRY_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 dtim;
+} POSTPACK WMI_AP_SET_DTIM_CMD;
+
+typedef PREPACK struct {
+    A_UINT8  band; /* specifies which band to apply these values */
+    A_UINT8  enable; /* allows 11n to be disabled on a per band basis */    
+    A_UINT8  chan_width_40M_supported;
+    A_UINT8  short_GI_20MHz;
+    A_UINT8  short_GI_40MHz;
+    A_UINT8  intolerance_40MHz;
+    A_UINT8  max_ampdu_len_exp;
+} POSTPACK WMI_SET_HT_CAP_CMD;
+
+typedef PREPACK struct {
+    A_UINT8   sta_chan_width;
+} POSTPACK WMI_SET_HT_OP_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 rateMasks[8];
+} POSTPACK WMI_SET_TX_SELECT_RATES_CMD;
+
+typedef PREPACK struct {
+    A_UINT32    sgiMask;
+    A_UINT8     sgiPERThreshold;
+} POSTPACK WMI_SET_TX_SGI_PARAM_CMD;
+
+
+typedef PREPACK struct {
+    A_UINT32 rateField; /* 1 bit per rate corresponding to index */
+    A_UINT8 id;
+    A_UINT8 shortTrys;
+    A_UINT8 longTrys;
+    A_UINT8 reserved; /* padding */
+} POSTPACK WMI_SET_RATE_POLICY_CMD;
+
+typedef PREPACK struct {
+    A_UINT8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */
+    A_UINT8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 <default> */
+    A_UINT8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target <default> */
+    A_UINT8 reserved[1]; /* alignment */
+} POSTPACK WMI_RX_FRAME_FORMAT_CMD;
+
+
+typedef PREPACK struct {
+    A_UINT8 enable;     // 1 == device operates in thin mode , 0 == normal mode <default> */
+    A_UINT8 reserved[3];
+} POSTPACK WMI_SET_THIN_MODE_CMD;
+
+/* AP mode events */
+/* WMI_PS_POLL_EVENT */
+typedef PREPACK struct {
+    A_UINT16 aid;
+} POSTPACK WMI_PSPOLL_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32 tx_bytes;
+    A_UINT32 tx_pkts;
+    A_UINT32 tx_error;
+    A_UINT32 tx_discard;
+    A_UINT32 rx_bytes;
+    A_UINT32 rx_pkts;
+    A_UINT32 rx_error;
+    A_UINT32 rx_discard;
+    A_UINT32 aid;
+} POSTPACK WMI_PER_STA_STAT;
+
+#define AP_GET_STATS    0
+#define AP_CLEAR_STATS  1
+
+typedef PREPACK struct {
+    A_UINT32            action;
+    WMI_PER_STA_STAT    sta[AP_MAX_NUM_STA+1];
+} POSTPACK WMI_AP_MODE_STAT;
+#define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(A_UINT32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT)))
+
+#define AP_11BG_RATESET1        1
+#define AP_11BG_RATESET2        2
+#define DEF_AP_11BG_RATESET     AP_11BG_RATESET1
+typedef PREPACK struct {
+    A_UINT8 rateset;
+} POSTPACK WMI_AP_SET_11BG_RATESET_CMD;
+/*
+ * End of AP mode definitions
+ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmi_api.h b/drivers/net/wireless/ath6kl/include/wmi_api.h
new file mode 100644
index 000000000000..446c56eab0ed
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi_api.h
@@ -0,0 +1,435 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_api.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions for the Wireless Module Interface (WMI).
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_API_H_
+#define _WMI_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    /* WMI converts a dix frame with an ethernet payload (up to 1500 bytes) 
+     * to an 802.3 frame (adds SNAP header) and adds on a WMI data header */
+#define WMI_MAX_TX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+    /* A normal WMI data frame */
+#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+    
+    /* An AMSDU frame */
+#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH  (4096 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+/*
+ * IP QoS Field definitions according to 802.1p
+ */
+#define BEST_EFFORT_PRI         0
+#define BACKGROUND_PRI          1
+#define EXCELLENT_EFFORT_PRI    3
+#define CONTROLLED_LOAD_PRI     4
+#define VIDEO_PRI               5
+#define VOICE_PRI               6
+#define NETWORK_CONTROL_PRI     7
+#define MAX_NUM_PRI             8
+
+#define UNDEFINED_PRI           (0xff)
+
+#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
+
+#define A_ROUND_UP(x, y)  ((((x) + ((y) - 1)) / (y)) * (y))
+
+typedef enum {
+    ATHEROS_COMPLIANCE = 0x1,
+}TSPEC_PARAM_COMPLIANCE;
+
+struct wmi_t;
+
+void *wmi_init(void *devt);
+
+void wmi_qos_state_init(struct wmi_t *wmip);
+void wmi_shutdown(struct wmi_t *wmip);
+HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip);
+void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid);
+A_UINT16  wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
+A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData, WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS);
+A_STATUS wmi_dot3_2_dix(void *osbuf);
+
+A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode);
+
+A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_syncpoint(struct wmi_t *wmip);
+A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled);
+
+A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri);
+
+A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
+void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
+void wmi_free_allnodes(struct wmi_t *wmip);
+bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+
+
+typedef enum {
+    NO_SYNC_WMIFLAG = 0,
+    SYNC_BEFORE_WMIFLAG,            /* transmit all queued data before cmd */
+    SYNC_AFTER_WMIFLAG,             /* any new data waits until cmd execs */
+    SYNC_BOTH_WMIFLAG,
+    END_WMIFLAG                     /* end marker */
+} WMI_SYNC_FLAG;
+
+A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+                      WMI_SYNC_FLAG flag);
+
+A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
+                         NETWORK_TYPE netType,
+                         DOT11_AUTH_MODE dot11AuthMode,
+                         AUTH_MODE authMode,
+                         CRYPTO_TYPE pairwiseCrypto,
+                         A_UINT8 pairwiseCryptoLen,
+                         CRYPTO_TYPE groupCrypto,
+                         A_UINT8 groupCryptoLen,
+                         int ssidLength,
+                         A_UCHAR *ssid,
+                         A_UINT8 *bssid,
+                         A_UINT16 channel,
+                         A_UINT32 ctrl_flags);
+
+A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
+                           A_UINT8 *bssid,
+                           A_UINT16 channel);
+A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
+A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
+A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+                           A_BOOL forceFgScan, A_BOOL isLegacy,
+                           A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+                           A_INT8 numChan, A_UINT16 *channelList);
+A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+                            A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+                            A_UINT16 minact_chdw_msec,
+                            A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
+                            A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+                            A_UINT32 max_dfsch_act_time,
+                            A_UINT16 maxact_scan_per_ssid);
+A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
+A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+                            A_UINT8 ssidLength, A_UCHAR *ssid);
+A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
+A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
+A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+                           A_UINT8 ieLen, A_UINT8 *ieInfo);
+A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
+A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+                            A_UINT16 atim_windows, A_UINT16 timeout_value);
+A_STATUS wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+                   A_UINT32 ps_period, A_UINT8 sleep_period);
+A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+                           A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+                           A_UINT16 wakup_tx_policy, A_UINT16 num_tx_to_wakeup,
+                           A_UINT16 ps_fail_event_policy);
+A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
+A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
+A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
+A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
+A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask);
+A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate);
+A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
+A_INT8   wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
+A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+                                   WMI_PHY_MODE mode, A_INT8 numChan,
+                                   A_UINT16 *channelList);
+
+A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
+                                       WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+                                        WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
+A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
+                                      WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
+A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
+A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy);
+
+A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
+
+A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
+                                    A_UINT32 source);
+
+A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+                                     A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+                                     A_UINT32 valid);
+
+A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
+                        CRYPTO_TYPE keyType, A_UINT8 keyUsage,
+                        A_UINT8 keyLength,A_UINT8 *keyRSC,
+                        A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac,
+                        WMI_SYNC_FLAG sync_flag);
+A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
+A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
+A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
+A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+                                 WMI_SET_AKMP_PARAMS_CMD *akmpParams);
+A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+                                WMI_SET_PMKID_LIST_CMD *pmkInfo);
+A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
+A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
+A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
+A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
+A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
+A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+                          A_BOOL set);
+A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop,
+                                   A_UINT8 eCWmin, A_UINT8 eCWmax,
+                                   A_UINT8 aifsn);
+A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+                                  A_UINT8 trafficClass, A_UINT8 maxRetries,
+                                  A_UINT8 enableNotify);
+
+void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
+
+A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
+A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+                               A_UINT8 size);
+A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+                            A_UINT8 size);
+
+A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
+A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+                              A_UINT8 frmType,
+                              A_UINT8 *dstMacAddr,
+                              A_UINT8 *bssid,
+                              A_UINT16 optIEDataLen,
+                              A_UINT8 *optIEData);
+
+A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
+A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
+A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
+A_UINT8  convert_userPriority_to_trafficClass(A_UINT8 userPriority);
+A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
+A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len);
+#endif
+
+A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
+A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+		                                WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+                               			WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *cmd);
+
+A_STATUS wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+                   		              WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+		                                 WMI_SET_BTCOEX_A2DP_CONFIG_CMD* cmd);
+
+
+A_STATUS wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+							WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_stats_cmd(struct wmi_t * wmip);
+
+/*
+ *  This function is used to configure the fix rates mask to the target.
+ */
+A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask);
+A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_qos_supp_cmd(struct wmi_t *wmip,A_UINT8 status);
+A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
+A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
+A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode);
+
+A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
+A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
+
+A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
+                           A_UINT8 ieLen,A_UINT8 *ieInfo);
+
+A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
+
+A_INT32 wmi_get_rate(A_INT8 rateindex);
+
+A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd);
+
+/*Wake on Wireless WMI commands*/
+A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
+A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
+A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
+A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_DEL_WOW_PATTERN_CMD *cmd);
+A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer);
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable);
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss);
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge);
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins);
+A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr);
+A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+#ifdef OS_ROAM_MANAGEMENT
+void wmi_scan_indication (struct wmi_t *wmip);
+#endif
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd);
+
+bss_t   *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id);
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss);
+
+
+/*
+ * AP mode
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p);
+
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid);
+
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta);
+
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy);
+
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a);
+
+A_UINT8
+acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl);
+
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason);
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag);
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period);
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell);
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim);
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset);
+
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd);
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width);
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz);
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray);
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid);
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink);
+
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask);
+
+A_STATUS 
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion, A_BOOL rxDot11Hdr, A_BOOL defragOnHost);
+
+A_STATUS 
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode);
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence);
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk);
+
+A_UINT16
+wmi_ieee2freq (int chan);
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq);
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength,
+                   A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmi_thin.h b/drivers/net/wireless/ath6kl/include/wmi_thin.h
new file mode 100644
index 000000000000..1e300d1c6563
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi_thin.h
@@ -0,0 +1,343 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_thin.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to WMI commands
+ * belongs to the host driver and the WM is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_THIN_H_
+#define _WMI_THIN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    WMI_THIN_CONFIG_CMDID =  0x8000, // WMI_THIN_RESERVED_START 
+    WMI_THIN_SET_MIB_CMDID,
+    WMI_THIN_GET_MIB_CMDID,
+    WMI_THIN_JOIN_CMDID,
+    /* add new CMDID's here */
+    WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
+} WMI_THIN_COMMAND_ID;
+
+typedef enum{
+    TEMPLATE_FRM_FIRST = 0,
+    TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
+    TEMPLATE_FRM_BEACON,
+    TEMPLATE_FRM_PROBE_RESP,
+    TEMPLATE_FRM_NULL,
+    TEMPLATE_FRM_QOS_NULL,
+    TEMPLATE_FRM_PSPOLL,
+    TEMPLATE_FRM_MAX
+}WMI_TEMPLATE_FRM_TYPE;
+
+/* TEMPLATE_FRM_LEN... represent the maximum allowable
+ * data lengths (bytes) for each frame type */
+#define TEMPLATE_FRM_LEN_PROBE_REQ  (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
+#define TEMPLATE_FRM_LEN_BEACON     (256)
+#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
+#define TEMPLATE_FRM_LEN_NULL       (32)
+#define TEMPLATE_FRM_LEN_QOS_NULL   (32)
+#define TEMPLATE_FRM_LEN_PSPOLL     (32)
+#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
+            TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
+
+
+/* MAC Header Build Rules */
+/*  These values allow the host to configure the 
+ *  target code that is responsible for constructing
+ *  the MAC header.  In cases where the MAC header
+ *  is provided by the host framework, the target
+ *  has a diminished responsibility over what fields
+ *  it must write. This will vary from framework to framework.
+ *  Symbian requires different behavior from MAC80211 which
+ *  requires different behavior from MS Native Wifi. */
+#define WMI_WRT_VER_TYPE    0x00000001
+#define WMI_WRT_DURATION    0x00000002
+#define WMI_WRT_DIRECTION   0x00000004
+#define WMI_WRT_POWER       0x00000008
+#define WMI_WRT_WEP         0x00000010
+#define WMI_WRT_MORE        0x00000020
+#define WMI_WRT_BSSID       0x00000040
+#define WMI_WRT_QOS         0x00000080
+#define WMI_WRT_SEQNO       0x00000100
+#define WMI_GUARD_TX        0x00000200 /* prevents TX ops that are not allowed for a current state */
+#define WMI_WRT_DEFAULT_CONFIG  (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
+                                 WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
+                                 WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
+
+/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for 
+ *  TX Complete messages the will come from the Target.  these messages are 
+ *  disabled by default but can be enabled using this structure and the 
+ *  WMI_THIN_CONFIG_CMDID. */
+typedef PREPACK struct {
+    A_UINT8     version; /* the versioned type of messages to use or 0 to disable */
+    A_UINT8     countThreshold; /* msg count threshold triggering a tx complete message */
+    A_UINT16    timeThreshold; /* timeout interval in MSEC triggering a tx complete message */       
+} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
+
+/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames 
+ *  that have decryption errors.  The default behavior is to discard the frame
+ *  without notification. Alternately, the MAC Header is forwarded to the host 
+ *  with the failed status. */
+typedef PREPACK struct {
+    A_UINT8     enable; /* 1 == send decrypt errors to the host, 0 == don't */
+    A_UINT8     reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
+
+/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
+ *  frames that require partial MAC header construction. These rules 
+ *  are used by the target to indicate which fields need to be written. */
+typedef PREPACK struct {
+    A_UINT32    rules; /* combination of WMI_WRT_... values */     
+} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
+
+/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
+ *  frames as to which frames should get forwarded to the host and which
+ *  should get processed internally. */
+typedef PREPACK struct {
+    A_UINT32    rules; /* combination of WMI_FILT_... values */     
+} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
+
+/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
+ *  WMI_THIN_CONFIG_... structures. The actual combination is indicated 
+ *  by the value of cfgField. Each bit in this field corresponds to 
+ *  one of the above structures. */
+typedef PREPACK struct {
+#define WMI_THIN_CFG_TXCOMP         0x00000001
+#define WMI_THIN_CFG_DECRYPT        0x00000002
+#define WMI_THIN_CFG_MAC_RULES      0x00000004
+#define WMI_THIN_CFG_FILTER_RULES   0x00000008
+    A_UINT32    cfgField;   /* combination of WMI_THIN_CFG_... describes contents of config command */
+    A_UINT16    length;     /* length in bytes of appended sub-commands */        
+    A_UINT8     reserved[2];   /* align padding */
+} POSTPACK WMI_THIN_CONFIG_CMD;
+
+/* MIB Access Identifiers tailored for Symbian. */
+enum {
+    MIB_ID_STA_MAC = 1,             // [READONLY]
+    MIB_ID_RX_LIFE_TIME,            // [NOT IMPLEMENTED]
+    MIB_ID_SLOT_TIME,               // [READ/WRITE]
+    MIB_ID_RTS_THRESHOLD,           // [READ/WRITE]
+    MIB_ID_CTS_TO_SELF,             // [READ/WRITE]
+    MIB_ID_TEMPLATE_FRAME,          // [WRITE ONLY]
+    MIB_ID_RXFRAME_FILTER,          // [READ/WRITE]
+    MIB_ID_BEACON_FILTER_TABLE,     // [WRITE ONLY]
+    MIB_ID_BEACON_FILTER,           // [READ/WRITE]
+    MIB_ID_BEACON_LOST_COUNT,       // [WRITE ONLY]
+    MIB_ID_RSSI_THRESHOLD,          // [WRITE ONLY]
+    MIB_ID_HT_CAP,                  // [NOT IMPLEMENTED]
+    MIB_ID_HT_OP,                   // [NOT IMPLEMENTED]
+    MIB_ID_HT_2ND_BEACON,           // [NOT IMPLEMENTED]
+    MIB_ID_HT_BLOCK_ACK,            // [NOT IMPLEMENTED]
+    MIB_ID_PREAMBLE,                // [READ/WRITE]
+    /*MIB_ID_GROUP_ADDR_TABLE,*/
+    /*MIB_ID_WEP_DEFAULT_KEY_ID */
+    /*MIB_ID_TX_POWER */
+    /*MIB_ID_ARP_IP_TABLE */
+    /*MIB_ID_SLEEP_MODE */
+    /*MIB_ID_WAKE_INTERVAL*/
+    /*MIB_ID_STAT_TABLE*/
+    /*MIB_ID_IBSS_PWR_SAVE*/
+    /*MIB_ID_COUNTERS_TABLE*/
+    /*MIB_ID_ETHERTYPE_FILTER*/
+    /*MIB_ID_BC_UDP_FILTER*/
+       
+};
+
+typedef PREPACK struct {
+    A_UINT8 addr[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_MIB_STA_MAC;
+
+typedef PREPACK struct {
+    A_UINT32 time; // units == msec
+} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
+
+typedef PREPACK struct {
+    A_UINT8 enable; //1 = on, 0 = off
+} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
+
+typedef PREPACK struct {
+    A_UINT32 time; // units == usec
+} POSTPACK WMI_THIN_MIB_SLOT_TIME;
+
+typedef PREPACK struct {
+    A_UINT16 length; //units == bytes
+} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
+
+typedef PREPACK struct {
+    A_UINT8 type; // type of frame
+    A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE)
+    A_UINT16 length; // num bytes following this structure as the template data
+} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
+
+typedef PREPACK struct {
+#define FRAME_FILTER_PROMISCUOUS 0x00000001
+#define FRAME_FILTER_BSSID       0x00000002
+    A_UINT32 filterMask; 
+} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
+
+
+#define IE_FILTER_TREATMENT_CHANGE 1
+#define IE_FILTER_TREATMENT_APPEAR 2
+
+typedef PREPACK struct {
+    A_UINT8 ie;
+    A_UINT8 treatment;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
+
+typedef PREPACK struct {
+    A_UINT8 ie;
+    A_UINT8 treatment;
+    A_UINT8 oui[3];
+    A_UINT8 type;
+    A_UINT16 version;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
+
+typedef PREPACK struct {
+    A_UINT16 numElements;
+    A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
+    A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER; 
+
+typedef PREPACK struct {
+    A_UINT32 count; /* num beacons between deliveries */
+    A_UINT8 enable;
+    A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
+
+typedef PREPACK struct {
+    A_UINT32 count; /* num consec lost beacons after which send event */
+} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
+
+typedef PREPACK struct {
+    A_UINT8 rssi; /* the low threshold which can trigger an event warning */
+    A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
+    A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */
+    A_UINT8 reserved[1]; /* padding */
+} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
+
+
+typedef PREPACK struct {
+    A_UINT32 cap;
+    A_UINT32 rxRateField;
+    A_UINT32 beamForming;
+    A_UINT8 addr[ATH_MAC_LEN];
+    A_UINT8 enable;        
+    A_UINT8 stbc;
+    A_UINT8 maxAMPDU;    
+    A_UINT8 msduSpacing;
+    A_UINT8 mcsFeedback;   
+    A_UINT8 antennaSelCap;    
+} POSTPACK WMI_THIN_MIB_HT_CAP;
+
+typedef PREPACK struct {
+    A_UINT32 infoField;
+    A_UINT32 basicRateField;
+    A_UINT8 protection;
+    A_UINT8 secondChanneloffset;
+    A_UINT8 channelWidth;
+    A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_HT_OP;
+
+typedef PREPACK struct {
+#define SECOND_BEACON_PRIMARY   1
+#define SECOND_BEACON_EITHER    2
+#define SECOND_BEACON_SECONDARY 3
+    A_UINT8 cfg;
+    A_UINT8 reserved[3]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
+
+typedef PREPACK struct {
+    A_UINT8 txTIDField;
+    A_UINT8 rxTIDField;
+    A_UINT8 reserved[2]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
+
+typedef PREPACK struct {
+    A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble
+    A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_PREAMBLE;
+
+typedef PREPACK struct {    
+    A_UINT16    length;     /* the length in bytes of the appended MIB data */
+    A_UINT8     mibID;      /* the ID of the MIB element being set */
+    A_UINT8     reserved; /* align padding */
+} POSTPACK WMI_THIN_SET_MIB_CMD;
+
+typedef PREPACK struct {    
+    A_UINT8     mibID;      /* the ID of the MIB element being set */
+    A_UINT8     reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_GET_MIB_CMD;
+
+typedef PREPACK struct {
+    A_UINT32    basicRateMask; /* bit mask of basic rates */
+    A_UINT32    beaconIntval; /* TUs */
+    A_UINT16    atimWindow; /* TUs */
+    A_UINT16    channel; /* frequency in Mhz */
+    A_UINT8     networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
+    A_UINT8     ssidLength; /* 0 - 32 */
+    A_UINT8     probe;      /* != 0 : issue probe req at start */
+    A_UINT8     reserved;   /* alignment */    
+    A_UCHAR     ssid[WMI_MAX_SSID_LEN];    
+    A_UINT8     bssid[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_JOIN_CMD;
+
+typedef PREPACK struct {
+    A_UINT16 dtim; /* dtim interval in num beacons */
+    A_UINT16 aid; /* 80211 AID from Assoc resp */   
+} POSTPACK WMI_THIN_POST_ASSOC_CMD;
+
+typedef enum {
+    WMI_THIN_EVENTID_RESERVED_START           = 0x8000,
+    WMI_THIN_GET_MIB_EVENTID,
+    WMI_THIN_JOIN_EVENTID,
+    
+    /* Add new THIN EVENTID's here */
+    WMI_THIN_EVENTID_RESERVED_END           = 0x8fff    
+} WMI_THIN_EVENT_ID;
+
+/* Possible values for WMI_THIN_JOIN_EVENT.result */
+typedef enum {
+    WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
+    WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
+    WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
+    WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
+}WMI_THIN_JOIN_RESULT;
+
+typedef PREPACK struct {
+    A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
+    A_UINT8 reserved[3]; /* alignment */
+} POSTPACK WMI_THIN_JOIN_EVENT;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_THIN_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmix.h b/drivers/net/wireless/ath6kl/include/wmix.h
new file mode 100644
index 000000000000..7db5560f41f0
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmix.h
@@ -0,0 +1,275 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmix.h" company="Atheros">
+//    Copyright (c) 2004-2007 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains extensions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI).  It includes definitions of all
+ * extended commands and events.  Extensions include useful commands
+ * that are not directly related to wireless activities.  They may
+ * be hardware-specific, and they might not be supported on all
+ * implementations.
+ *
+ * Extended WMIX commands are encapsulated in a WMI message with
+ * cmd=WMI_EXTENSION_CMD.
+ */
+
+#ifndef _WMIX_H_
+#define _WMIX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "dbglog.h"
+
+/*
+ * Extended WMI commands are those that are needed during wireless
+ * operation, but which are not really wireless commands.  This allows,
+ * for instance, platform-specific commands.  Extended WMI commands are
+ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
+ * Extended WMI events are similarly embedded in a WMI event message with
+ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
+ */
+typedef PREPACK struct {
+    A_UINT32    commandId;
+} POSTPACK WMIX_CMD_HDR;
+
+typedef enum {
+    WMIX_DSETOPEN_REPLY_CMDID           = 0x2001,
+    WMIX_DSETDATA_REPLY_CMDID,
+    WMIX_GPIO_OUTPUT_SET_CMDID,
+    WMIX_GPIO_INPUT_GET_CMDID,
+    WMIX_GPIO_REGISTER_SET_CMDID,
+    WMIX_GPIO_REGISTER_GET_CMDID,
+    WMIX_GPIO_INTR_ACK_CMDID,
+    WMIX_HB_CHALLENGE_RESP_CMDID,
+    WMIX_DBGLOG_CFG_MODULE_CMDID,
+    WMIX_PROF_CFG_CMDID,                 /* 0x200a */
+    WMIX_PROF_ADDR_SET_CMDID,
+    WMIX_PROF_START_CMDID,
+    WMIX_PROF_STOP_CMDID,
+    WMIX_PROF_COUNT_GET_CMDID,
+} WMIX_COMMAND_ID;
+
+typedef enum {
+    WMIX_DSETOPENREQ_EVENTID            = 0x3001,
+    WMIX_DSETCLOSE_EVENTID,
+    WMIX_DSETDATAREQ_EVENTID,
+    WMIX_GPIO_INTR_EVENTID,
+    WMIX_GPIO_DATA_EVENTID,
+    WMIX_GPIO_ACK_EVENTID,
+    WMIX_HB_CHALLENGE_RESP_EVENTID,
+    WMIX_DBGLOG_EVENTID,
+    WMIX_PROF_COUNT_EVENTID,
+} WMIX_EVENT_ID;
+
+/*
+ * =============DataSet support=================
+ */
+
+/*
+ * WMIX_DSETOPENREQ_EVENTID
+ * DataSet Open Request Event
+ */
+typedef PREPACK struct {
+    A_UINT32 dset_id;
+    A_UINT32 targ_dset_handle;  /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_fn;     /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_arg;    /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETOPENREQ_EVENT;
+
+/*
+ * WMIX_DSETCLOSE_EVENTID
+ * DataSet Close Event
+ */
+typedef PREPACK struct {
+    A_UINT32 access_cookie;
+} POSTPACK WMIX_DSETCLOSE_EVENT;
+
+/*
+ * WMIX_DSETDATAREQ_EVENTID
+ * DataSet Data Request Event
+ */
+typedef PREPACK struct {
+    A_UINT32 access_cookie;
+    A_UINT32 offset;
+    A_UINT32 length;
+    A_UINT32 targ_buf;         /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_fn;    /* echo'ed, not used by Host, */
+    A_UINT32 targ_reply_arg;   /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETDATAREQ_EVENT;
+
+typedef PREPACK struct {
+    A_UINT32              status;
+    A_UINT32              targ_dset_handle;
+    A_UINT32              targ_reply_fn;
+    A_UINT32              targ_reply_arg;
+    A_UINT32              access_cookie;
+    A_UINT32              size;
+    A_UINT32              version;
+} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
+
+typedef PREPACK struct {
+    A_UINT32              status;
+    A_UINT32              targ_buf;
+    A_UINT32              targ_reply_fn;
+    A_UINT32              targ_reply_arg;
+    A_UINT32              length;
+    A_UINT8               buf[1];
+} POSTPACK WMIX_DSETDATA_REPLY_CMD;
+
+
+/* 
+ * =============GPIO support=================
+ * All masks are 18-bit masks with bit N operating on GPIO pin N.
+ */
+
+#include "gpio.h"
+
+/*
+ * Set GPIO pin output state.
+ * In order for output to be driven, a pin must be enabled for output.
+ * This can be done during initialization through the GPIO Configuration
+ * DataSet, or during operation with the enable_mask.
+ *
+ * If a request is made to simultaneously set/clear or set/disable or
+ * clear/disable or disable/enable, results are undefined.
+ */
+typedef PREPACK struct {
+    A_UINT32              set_mask;             /* pins to set */
+    A_UINT32              clear_mask;           /* pins to clear */
+    A_UINT32              enable_mask;          /* pins to enable for output */
+    A_UINT32              disable_mask;         /* pins to disable/tristate */
+} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
+
+/* 
+ * Set a GPIO register.  For debug/exceptional cases.
+ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
+ * platform-dependent header.
+ */
+typedef PREPACK struct {
+    A_UINT32              gpioreg_id;           /* GPIO register ID */
+    A_UINT32              value;                /* value to write */
+} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
+
+/* Get a GPIO register.  For debug/exceptional cases. */
+typedef PREPACK struct {
+    A_UINT32              gpioreg_id;           /* GPIO register to read */
+} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
+
+/*
+ * Host acknowledges and re-arms GPIO interrupts.  A single
+ * message should be used to acknowledge all interrupts that
+ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
+ */
+typedef PREPACK struct {
+    A_UINT32              ack_mask;             /* interrupts to acknowledge */
+} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
+
+/*
+ * Target informs Host of GPIO interrupts that have ocurred since the
+ * last WMIX_GIPO_INTR_ACK_CMD was received.  Additional information --
+ * the current GPIO input values is provided -- in order to support
+ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
+ */
+typedef PREPACK struct {
+    A_UINT32              intr_mask;            /* pending GPIO interrupts */
+    A_UINT32              input_values;         /* recent GPIO input values */
+} POSTPACK WMIX_GPIO_INTR_EVENT;
+
+/*
+ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ *   value set to the mask of GPIO pin inputs and
+ *   reg_id set to GPIO_ID_NONE
+ * 
+ *
+ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ *   value set to the value of the requested register and
+ *   reg_id identifying the register (reflects the original request)
+ * NB: reg_id supports the future possibility of unsolicited
+ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
+ * simplify Host GPIO support.
+ */
+typedef PREPACK struct {
+    A_UINT32              value;
+    A_UINT32              reg_id;
+} POSTPACK WMIX_GPIO_DATA_EVENT;
+
+/*
+ * =============Error Detection support=================
+ */
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_CMDID
+ * Heartbeat Challenge Response command
+ */
+typedef PREPACK struct {
+    A_UINT32              cookie;
+    A_UINT32              source;
+} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_EVENTID
+ * Heartbeat Challenge Response Event
+ */
+#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
+
+typedef PREPACK struct {
+    struct dbglog_config_s config;
+} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
+
+/*
+ * =============Target Profiling support=================
+ */
+
+typedef PREPACK struct {
+    A_UINT32 period; /* Time (in 30.5us ticks) between samples */
+    A_UINT32 nbins;
+} POSTPACK WMIX_PROF_CFG_CMD;
+
+typedef PREPACK struct {
+    A_UINT32 addr;
+} POSTPACK WMIX_PROF_ADDR_SET_CMD;
+
+/*
+ * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
+ * using a WMIX_PROF_COUNT_EVENT with
+ *   addr set to the next address
+ *   count set to the corresponding count
+ */
+typedef PREPACK struct {
+    A_UINT32              addr;
+    A_UINT32              count;
+} POSTPACK WMIX_PROF_COUNT_EVENT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMIX_H_ */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c
new file mode 100644
index 000000000000..44ae924ef134
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c
@@ -0,0 +1,432 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar3kconfig.c" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR3K configuration implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "ar3kconfig.h"
+
+#define BAUD_CHANGE_COMMAND_STATUS_OFFSET   5
+#define HCI_EVENT_RESP_TIMEOUTMS            3000
+#define HCI_CMD_OPCODE_BYTE_LOW_OFFSET      0
+#define HCI_CMD_OPCODE_BYTE_HI_OFFSET       1
+#define HCI_EVENT_OPCODE_BYTE_LOW           3
+#define HCI_EVENT_OPCODE_BYTE_HI            4
+#define HCI_CMD_COMPLETE_EVENT_CODE         0xE
+#define HCI_MAX_EVT_RECV_LENGTH             257
+#define EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET  5
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+
+static A_STATUS SendHCICommand(AR3K_CONFIG_INFO *pConfig,
+                               A_UINT8          *pBuffer,
+                               int              Length)
+{
+    HTC_PACKET  *pPacket = NULL;
+    A_STATUS    status = A_OK;
+       
+    do {   
+        
+        pPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));     
+        if (NULL == pPacket) {
+            status = A_NO_MEMORY;
+            break;    
+        }       
+        
+        A_MEMZERO(pPacket,sizeof(HTC_PACKET));      
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               NULL,
+                               pBuffer, 
+                               Length,
+                               HCI_COMMAND_TYPE, 
+                               AR6K_CONTROL_PKT_TAG);
+        
+            /* issue synchronously */                                      
+        status = HCI_TransportSendPkt(pConfig->pHCIDev,pPacket,TRUE);   
+        
+    } while (FALSE);
+   
+    if (pPacket != NULL) {
+        A_FREE(pPacket);
+    }
+        
+    return status;
+}
+
+static A_STATUS RecvHCIEvent(AR3K_CONFIG_INFO *pConfig,
+                             A_UINT8          *pBuffer,
+                             int              *pLength)
+{
+    A_STATUS    status = A_OK; 
+    HTC_PACKET  *pRecvPacket = NULL;
+    
+    do {
+                 
+        pRecvPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));
+        if (NULL == pRecvPacket) {
+            status = A_NO_MEMORY;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+            break;    
+        }     
+        
+        A_MEMZERO(pRecvPacket,sizeof(HTC_PACKET)); 
+         
+        SET_HTC_PACKET_INFO_RX_REFILL(pRecvPacket,NULL,pBuffer,*pLength,HCI_EVENT_TYPE);
+        
+        status = HCI_TransportRecvHCIEventSync(pConfig->pHCIDev,
+                                               pRecvPacket,
+                                               HCI_EVENT_RESP_TIMEOUTMS);
+        if (A_FAILED(status)) {
+            break;    
+        }
+
+        *pLength = pRecvPacket->ActualLength;
+        
+    } while (FALSE);
+       
+    if (pRecvPacket != NULL) {
+        A_FREE(pRecvPacket);    
+    }
+    
+    return status;
+} 
+    
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree)
+{
+    A_STATUS    status = A_OK;   
+    A_UINT8     *pBuffer = NULL;
+    A_UINT8     *pTemp;
+    int         length;
+    A_BOOL      commandComplete = FALSE;
+    A_UINT8     opCodeBytes[2];
+                               
+    do {
+        
+        length = max(HCI_MAX_EVT_RECV_LENGTH,CmdLength);
+        length += pConfig->pHCIProps->HeadRoom + pConfig->pHCIProps->TailRoom;
+        length += pConfig->pHCIProps->IOBlockPad;
+                                     
+        pBuffer = (A_UINT8 *)A_MALLOC(length);        
+        if (NULL == pBuffer) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to allocate bt buffer \n"));
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+            /* get the opcodes to check the command complete event */
+        opCodeBytes[0] = pHCICommand[HCI_CMD_OPCODE_BYTE_LOW_OFFSET];
+        opCodeBytes[1] = pHCICommand[HCI_CMD_OPCODE_BYTE_HI_OFFSET];
+        
+            /* copy HCI command */
+        A_MEMCPY(pBuffer + pConfig->pHCIProps->HeadRoom,pHCICommand,CmdLength);         
+            /* send command */
+        status = SendHCICommand(pConfig,
+                                pBuffer + pConfig->pHCIProps->HeadRoom,
+                                CmdLength);
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to send HCI Command (%d) \n", status));
+            AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+            break;    
+        }   
+        
+            /* reuse buffer to capture command complete event */
+        A_MEMZERO(pBuffer,length);
+        status = RecvHCIEvent(pConfig,pBuffer,&length);        
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI event recv failed \n"));
+            AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+            break;    
+        }
+        
+        pTemp = pBuffer + pConfig->pHCIProps->HeadRoom;        
+        if (pTemp[0] == HCI_CMD_COMPLETE_EVENT_CODE) {
+            if ((pTemp[HCI_EVENT_OPCODE_BYTE_LOW] == opCodeBytes[0]) &&
+                (pTemp[HCI_EVENT_OPCODE_BYTE_HI] == opCodeBytes[1])) {
+                commandComplete = TRUE;    
+            }
+        }
+        
+        if (!commandComplete) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Unexpected HCI event : %d \n",pTemp[0]));
+            AR_DEBUG_PRINTBUF(pTemp,pTemp[1],"Unexpected HCI event");
+            status = A_ECOMM;
+            break;    
+        }       
+        
+        if (ppEventBuffer != NULL) {
+                /* caller wants to look at the event */
+            *ppEventBuffer = pTemp;
+            if (ppBufferToFree == NULL) {
+                status = A_EINVAL;
+                break;        
+            }
+                /* caller must free the buffer */
+            *ppBufferToFree = pBuffer;
+            pBuffer = NULL;            
+        }
+        
+    } while (FALSE);
+
+    if (pBuffer != NULL) {
+        A_FREE(pBuffer);    
+    }
+    
+    return status;    
+}
+
+static A_STATUS AR3KConfigureHCIBaud(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS    status = A_OK;
+    A_UINT8     hciBaudChangeCommand[] =  {0x0c,0xfc,0x2,0,0};
+    A_UINT16    baudVal; 
+    A_UINT8     *pEvent = NULL;
+    A_UINT8     *pBufferToFree = NULL;
+    
+    do {
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR3K_BAUD) {
+            baudVal = (A_UINT16)(pConfig->AR3KBaudRate / 100);
+            hciBaudChangeCommand[3] = (A_UINT8)baudVal;
+            hciBaudChangeCommand[4] = (A_UINT8)(baudVal >> 8);
+            
+            status = SendHCICommandWaitCommandComplete(pConfig,
+                                                       hciBaudChangeCommand,
+                                                       sizeof(hciBaudChangeCommand),
+                                                       &pEvent,
+                                                       &pBufferToFree);          
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Baud rate change failed! \n"));  
+                break;    
+            }
+            
+            if (pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET] != 0) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("AR3K Config: Baud change command event status failed: %d \n", 
+                                pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET]));
+                status = A_ECOMM; 
+                break;           
+            } 
+            
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                    ("AR3K Config: Baud Changed to %d \n",pConfig->AR3KBaudRate));  
+        }
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY) {
+                /* some versions of AR3K do not switch baud immediately, up to 300MS */
+            A_MDELAY(325);
+        }
+        
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP) {
+            /* Tell target to change UART baud rate for AR6K */
+            status = HCI_TransportSetBaudRate(pConfig->pHCIDev, pConfig->AR3KBaudRate);
+
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                    ("AR3K Config: failed to set scale and step values: %d \n", status));
+                break;    
+            }
+    
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+                    ("AR3K Config: Baud changed to %d for AR6K\n", pConfig->AR3KBaudRate));            
+        }
+                
+    } while (FALSE);
+                        
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+        
+    return status;
+}
+
+static A_STATUS AR3KExitMinBoot(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS  status;
+    A_CHAR    exitMinBootCmd[] = {0x25,0xFC,0x0c,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
+                                  0x00,0x00,0x00,0x00,0x00};
+    A_UINT8   *pEvent = NULL;
+    A_UINT8   *pBufferToFree = NULL;
+    
+    status = SendHCICommandWaitCommandComplete(pConfig,
+                                               exitMinBootCmd,
+                                               sizeof(exitMinBootCmd),
+                                               &pEvent,
+                                               &pBufferToFree);
+    
+    if (A_SUCCESS(status)) {
+        if (pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET] != 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                ("AR3K Config: MinBoot exit command event status failed: %d \n", 
+                            pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET]));
+            status = A_ECOMM;            
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, 
+                                ("AR3K Config: MinBoot Exit Command Complete (Success) \n"));
+            A_MDELAY(1);
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: MinBoot Exit Failed! \n"));    
+    }
+    
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);    
+    }
+    
+    return status;                                              
+}
+                                 
+static A_STATUS AR3KConfigureSendHCIReset(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS status = A_OK;
+    A_UINT8 hciResetCommand[] = {0x03,0x0c,0x0};
+    A_UINT8 *pEvent = NULL;
+    A_UINT8 *pBufferToFree = NULL;
+
+    status = SendHCICommandWaitCommandComplete( pConfig,
+                                                hciResetCommand,
+                                                sizeof(hciResetCommand),
+                                                &pEvent,
+                                                &pBufferToFree );
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI reset failed! \n"));
+    }
+
+    if (pBufferToFree != NULL) {
+        A_FREE(pBufferToFree);
+    }
+
+    return status;
+}
+
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfig)
+{
+    A_STATUS        status = A_OK; 
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuring AR3K ...\n"));
+                                
+    do {
+        
+        if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* disable asynchronous recv while we issue commands and receive events synchronously */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+        if (A_FAILED(status)) {
+            break;    
+        }
+      
+        if (pConfig->Flags & AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT) {
+            status =  AR3KExitMinBoot(pConfig);   
+            if (A_FAILED(status)) {
+                break;    
+            }    
+        }
+        
+        if (pConfig->Flags & 
+                (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+            status = AR3KConfigureHCIBaud(pConfig);      
+            if (A_FAILED(status)) {
+                break;    
+            }
+        }
+
+        /* Load patching and PST file if available*/
+        if (A_OK != AthPSInitialize(pConfig)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch Download Failed!\n"));
+        }
+
+        /* Send HCI reset to make PS tags take effect*/
+        AR3KConfigureSendHCIReset(pConfig);
+               
+           /* re-enable asynchronous recv */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+        if (A_FAILED(status)) {
+            break;    
+        }     
+    
+    
+    } while (FALSE);   
+    
+  
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuration Complete (status = %d) \n",status));
+    
+    return status;
+}
+
+A_STATUS AR3KConfigureExit(void *config)
+{
+    A_STATUS        status = A_OK; 
+    AR3K_CONFIG_INFO *pConfig = (AR3K_CONFIG_INFO *)config;
+        
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleaning up AR3K ...\n"));
+                                
+    do {
+        
+        if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+            status = A_EINVAL;
+            break;    
+        }
+        
+            /* disable asynchronous recv while we issue commands and receive events synchronously */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+        if (A_FAILED(status)) {
+            break;    
+        }
+      
+        if (pConfig->Flags & 
+                (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+            status = AR3KConfigureHCIBaud(pConfig);      
+            if (A_FAILED(status)) {
+                break;    
+            }
+        }
+
+           /* re-enable asynchronous recv */
+        status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+        if (A_FAILED(status)) {
+            break;    
+        }     
+    
+    
+    } while (FALSE);   
+    
+  
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleanup Complete (status = %d) \n",status));
+    
+    return status;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
new file mode 100644
index 000000000000..d4048c8efd0c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch downloaded for HCI UART Transport driver.
+ * This file can be used for HCI SDIO transport implementation for AR6002 with HCI_TRANSPORT_SDIO
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#include "ar3kpsconfig.h"
+#ifndef HCI_TRANSPORT_SDIO
+#include "hci_ath.h"
+#include "hci_uart.h"
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+/*
+ *  Structure used to send HCI packet, hci packet length and device info 
+ *  together as parameter to PSThread.
+ */
+typedef struct {
+
+    PSCmdPacket *HciCmdList;
+    A_UINT32  num_packets;
+    AR3K_CONFIG_INFO *dev;
+}HciCommandListParam;
+
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree);
+
+A_UINT32  Rom_Version;
+A_UINT32  Build_Version;
+
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code);
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig);
+#ifndef HCI_TRANSPORT_SDIO
+
+DECLARE_WAIT_QUEUE_HEAD(PsCompleteEvent);
+DECLARE_WAIT_QUEUE_HEAD(HciEvent);
+A_UCHAR *HciEventpacket;
+rwlock_t syncLock;
+wait_queue_t Eventwait;
+
+int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, A_UINT32 len);
+extern char *bdaddr;
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr);
+
+int PSSendOps(void *arg);
+
+#ifdef BT_PS_DEBUG
+void Hci_log(A_UCHAR * log_string,A_UCHAR *data,A_UINT32 len)
+{
+    int i;
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string));
+    for (i = 0; i < len; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("0x%02x ", data[i]));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n...................................\n"));
+}
+#else
+#define Hci_log(string,data,len)
+#endif /* BT_PS_DEBUG */
+
+
+
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev)
+{
+    A_STATUS status = A_OK;
+    if(hdev == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Device handle received\n"));
+        return A_ERROR;
+    }
+
+#ifndef HCI_TRANSPORT_SDIO
+    DECLARE_WAITQUEUE(wait, current);
+#endif /* HCI_TRANSPORT_SDIO */
+    
+
+#ifdef HCI_TRANSPORT_SDIO
+    status = PSSendOps((void*)hdev);
+#else
+    if(InitPSState(hdev) == -1) {
+        return A_ERROR;
+    }
+    allow_signal(SIGKILL);
+    add_wait_queue(&PsCompleteEvent,&wait);
+    set_current_state(TASK_INTERRUPTIBLE);
+    if(!kernel_thread(PSSendOps,(void*)hdev,CLONE_FS|CLONE_FILES|CLONE_SIGHAND|SIGCHLD)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Kthread Failed\n"));
+        remove_wait_queue(&PsCompleteEvent,&wait);
+        return A_ERROR;
+    }
+    wait_event_interruptible(PsCompleteEvent,(PSTagMode == FALSE));
+    set_current_state(TASK_RUNNING);
+    remove_wait_queue(&PsCompleteEvent,&wait);
+
+#endif /* HCI_TRANSPORT_SDIO */
+
+
+    return status;
+    
+}
+
+int PSSendOps(void *arg) 
+{
+    int i;
+    int status = 0;
+    PSCmdPacket *HciCmdList; /* List storing the commands */
+    const struct firmware* firmware;
+    A_UINT32 numCmds;
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree;
+    struct hci_dev *device;
+    A_UCHAR *buffer;
+    A_UINT32 len;
+    A_UINT32 DevType;
+    A_UCHAR *PsFileName;
+    A_UCHAR *patchFileName;
+    AR3K_CONFIG_INFO *hdev = (AR3K_CONFIG_INFO*)arg;
+    struct device *firmwareDev = NULL;
+    status = 0;
+    HciCmdList = NULL;
+#ifdef HCI_TRANSPORT_SDIO
+    device = hdev->pBtStackHCIDev; 
+    firmwareDev = device->parent;
+#else 
+    device = hdev;
+    firmwareDev = &device->dev;
+    AthEnableSyncCommandOp(TRUE);    
+#endif /* HCI_TRANSPORT_SDIO */
+    /* First verify if the controller is an FPGA or ASIC, so depending on the device type the PS file to be written will be different.
+     */ 
+    if(A_ERROR == getDeviceType(hdev,&DevType)) {
+        status = 1;
+        goto complete;
+    }
+    if(A_ERROR == ReadVersionInfo(hdev)) {
+        status = 1;
+        goto complete;
+    }
+    patchFileName = PATCH_FILE;
+    if(DevType){
+        if(DevType == 0xdeadc0de){
+	        PsFileName =  PS_ASIC_FILE;
+	    } else{
+    		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" FPGA Test Image : %x %x  \n",Rom_Version,Build_Version));
+                if((Rom_Version == 0x99999999) && (Build_Version == 1)){
+                        
+    			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("FPGA Test Image : Skipping Patch File load\n"));
+    			patchFileName = NULL;
+		}
+	        PsFileName =  PS_FPGA_FILE;
+	    }
+    }
+    else{
+	    PsFileName =  PS_ASIC_FILE;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%x: FPGA/ASIC PS File Name %s\n", DevType,PsFileName));
+    /* Read the PS file to a dynamically allocated buffer */
+    if(request_firmware(&firmware,PsFileName,firmwareDev) < 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        status = 1;
+        goto complete;
+
+    }
+    if(NULL == firmware || firmware->size == 0) {
+        status = 1;
+        goto complete;
+    }
+    buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+    if(buffer != NULL) {
+    /* Copy the read file to a local Dynamic buffer */
+        memcpy(buffer,firmware->data,firmware->size);
+        len = firmware->size;
+        release_firmware(firmware);
+        /* Parse the PS buffer to a global variable */
+        status = AthDoParsePS(buffer,len);
+        A_FREE(buffer);
+    } else {
+        release_firmware(firmware);
+    }
+
+
+    /* Read the patch file to a dynamically allocated buffer */
+    if((patchFileName == NULL) || (request_firmware(&firmware,patchFileName,firmwareDev) < 0)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        /* 
+         *  It is not necessary that Patch file be available, continue with PS Operations if.
+         *  failed.
+         */
+        status = 0;
+
+    } else {
+        if(NULL == firmware || firmware->size == 0) {
+            status = 0;
+        } else {
+            buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+            if(buffer != NULL) {
+                /* Copy the read file to a local Dynamic buffer */
+                memcpy(buffer,firmware->data,firmware->size);
+                len = firmware->size;
+                release_firmware(firmware);
+                /* parse and store the Patch file contents to a global variables */
+                status = AthDoParsePatch(buffer,len);
+                A_FREE(buffer);
+            } else {
+                release_firmware(firmware);
+            }
+        }
+    }
+
+    /* Create an HCI command list from the parsed PS and patch information */
+    AthCreateCommandList(&HciCmdList,&numCmds);
+
+    /* Form the parameter for PSSendOps() API */
+ 
+
+    /*
+     * First Send the CRC packet, 
+     * We have to continue with the PS operations only if the CRC packet has been replied with 
+     * a Command complete event with status Error.
+     */
+
+    if(SendHCICommandWaitCommandComplete
+    (hdev,
+    HciCmdList[0].Hcipacket,
+    HciCmdList[0].packetLen,
+    &event,
+    &bufferToFree) == A_OK) {
+        if(ReadPSEvent(event) == A_OK) { /* Exit if the status is success */
+            if(bufferToFree != NULL) {
+                A_FREE(bufferToFree);
+                }
+#ifndef HCI_TRANSPORT_SDIO
+				if(bdaddr[0] !='\0') {
+					write_bdaddr(hdev,bdaddr);
+				}
+#endif 
+               status = 1;
+               goto complete;
+        }
+        if(bufferToFree != NULL) {
+               A_FREE(bufferToFree);
+        }
+    } else {
+        status = 0;
+        goto complete;
+    }
+ 
+    for(i = 1; i <numCmds; i++) {
+    
+        if(SendHCICommandWaitCommandComplete
+        (hdev,
+        HciCmdList[i].Hcipacket,
+        HciCmdList[i].packetLen,
+        &event,
+        &bufferToFree) == A_OK) {
+            if(ReadPSEvent(event) != A_OK) { /* Exit if the status is success */
+                if(bufferToFree != NULL) {
+                    A_FREE(bufferToFree);
+                    }
+                   status = 1;
+                    goto complete;
+            }
+            if(bufferToFree != NULL) {
+                   A_FREE(bufferToFree);
+            }
+        } else {
+            status = 0;
+            goto complete;
+        }
+    }
+#ifndef HCI_TRANSPORT_SDIO
+	if(bdaddr[0] != '\0') {
+		write_bdaddr(hdev,bdaddr);
+	} else
+#endif /* HCI_TRANSPORT_SDIO */
+	{
+		 /* Read Contents of BDADDR file if user has not provided any option */
+    	if(request_firmware(&firmware,BDADDR_FILE,firmwareDev) < 0) {
+        	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+        	status = 1;
+        	goto complete;
+    	}
+    	if(NULL == firmware || firmware->size == 0) {
+        	status = 1;
+        	goto complete;
+    	}
+		write_bdaddr(hdev,(A_UCHAR *)firmware->data);
+       	release_firmware(firmware);
+	}
+complete:
+#ifndef HCI_TRANSPORT_SDIO
+    AthEnableSyncCommandOp(FALSE);    
+    PSTagMode = FALSE;
+    wake_up_interruptible(&PsCompleteEvent);
+#endif /* HCI_TRANSPORT_SDIO */
+    if(NULL != HciCmdList) {
+        AthFreeCommandList(&HciCmdList,numCmds);
+    }
+    return status;
+}
+#ifndef HCI_TRANSPORT_SDIO
+/*
+ *  This API is used to send the HCI command to controller and return
+ *  with a HCI Command Complete event.
+ *  For HCI SDIO transport, this will be internally defined. 
+ */
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+                                           A_UINT8          *pHCICommand,
+                                           int              CmdLength,
+                                           A_UINT8          **ppEventBuffer,
+                                           A_UINT8          **ppBufferToFree)
+{
+    if(CmdLength == 0) {
+        return A_ERROR;
+    }
+    Hci_log("COM Write -->",pHCICommand,CmdLength);
+    PSAcked = FALSE;
+    if(PSHciWritepacket(pConfig,pHCICommand,CmdLength) == 0) {
+        /* If the controller is not available, return Error */
+        return A_ERROR;
+    }
+    //add_timer(&psCmdTimer);
+    wait_event_interruptible(HciEvent,(PSAcked == TRUE));
+    if(NULL != HciEventpacket) {
+        *ppEventBuffer = HciEventpacket;
+        *ppBufferToFree = HciEventpacket;
+    } else {
+        /* Did not get an event from controller. return error */
+        *ppBufferToFree = NULL;
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS ReadPSEvent(A_UCHAR* Data){
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" PS Event %x %x %x\n",Data[4],Data[5],Data[3]));
+                                
+    if(Data[4] == 0xFC && Data[5] == 0x00)
+    {
+         switch(Data[3]){
+             case 0x0B:
+                     return A_OK;
+                 break;
+                 case 0x0C:
+                    /* Change Baudrate */
+                        return A_OK;    
+                 break;  
+                 case 0x04:
+                     return A_OK;
+                 break;  
+		case 0x1E:
+			Rom_Version = Data[9];
+			Rom_Version = ((Rom_Version << 8) |Data[8]);
+			Rom_Version = ((Rom_Version << 8) |Data[7]);
+			Rom_Version = ((Rom_Version << 8) |Data[6]);
+
+			Build_Version = Data[13];
+			Build_Version = ((Build_Version << 8) |Data[12]);
+			Build_Version = ((Build_Version << 8) |Data[11]);
+			Build_Version = ((Build_Version << 8) |Data[10]);
+			return A_OK;
+		break;
+
+        
+                }
+    }                       
+        
+    return A_ERROR;           
+}
+int str2ba(unsigned char *str_bdaddr,unsigned char *bdaddr)
+{
+	unsigned char bdbyte[3];
+	unsigned char *str_byte = str_bdaddr;
+	int i,j;
+	unsigned char colon_present = 0;
+
+	if(NULL != strstr(str_bdaddr,":")) {
+		colon_present = 1;
+	}
+
+
+	bdbyte[2] = '\0';
+
+	for( i = 0,j = 5; i < 6; i++, j--) {
+		bdbyte[0] = str_byte[0];
+		bdbyte[1] = str_byte[1];
+		bdaddr[j] = A_STRTOL(bdbyte,NULL,16);
+		if(colon_present == 1) {
+			str_byte+=3;
+		} else {
+			str_byte+=2;
+		}
+	}
+	return 0; 
+}
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr)
+{
+	A_UCHAR bdaddr_cmd[] = { 0x0B, 0xFC, 0x0A, 0x01, 0x01, 
+							0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_STATUS result = A_ERROR;
+	
+	str2ba(bdaddr,&bdaddr_cmd[7]);
+
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,bdaddr_cmd,
+												sizeof(bdaddr_cmd),
+												&event,&bufferToFree)) {
+
+        if(event[4] == 0xFC && event[5] == 0x00){
+               if(event[3] == 0x0B){
+                result = A_OK;
+            }
+        }
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+
+}
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig)
+{
+    A_UINT8   hciCommand[] =  {0x1E,0xfc,0x00};
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_STATUS result = A_ERROR;
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+	result = ReadPSEvent(event);
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+}
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code)
+{
+    A_UINT8   hciCommand[] =  {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04};
+    A_UINT8 *event;
+    A_UINT8 *bufferToFree = NULL;
+    A_UINT32 reg;
+    A_STATUS result = A_ERROR;
+    *code = 0;
+    hciCommand[3] = (A_UINT8)(FPGA_REGISTER & 0xFF);
+    hciCommand[4] = (A_UINT8)((FPGA_REGISTER >> 8) & 0xFF);
+    hciCommand[5] = (A_UINT8)((FPGA_REGISTER >> 16) & 0xFF);
+    hciCommand[6] = (A_UINT8)((FPGA_REGISTER >> 24) & 0xFF); 
+    if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+
+        if(event[4] == 0xFC && event[5] == 0x00){
+               switch(event[3]){
+                case 0x05:
+                reg = event[9];
+                reg = ((reg << 8) |event[8]);
+                reg = ((reg << 8) |event[7]);
+                reg = ((reg << 8) |event[6]);
+                *code = reg;
+                result = A_OK;
+
+                break;
+                case 0x06:
+                    //Sleep(500);
+                break;
+            }
+        }
+
+    }
+    if(bufferToFree != NULL) {
+        A_FREE(bufferToFree);
+   }
+    return result;
+}
+
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
new file mode 100644
index 000000000000..2dd664e47798
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file defines the symbols exported by Atheros PS and patch download module.
+ * define the constant HCI_TRANSPORT_SDIO if the module is being used for HCI SDIO transport.
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.h
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#ifndef __AR3KPSCONFIG_H
+#define __AR3KPSCONFIG_H
+
+/* 
+ * Define the flag HCI_TRANSPORT_SDIO and undefine HCI_TRANSPORT_UART if the transport being used is SDIO.
+ */
+#undef HCI_TRANSPORT_UART
+
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/signal.h>
+#include <linux/timer.h>
+
+
+#include <linux/ioctl.h>
+#include <linux/skbuff.h>
+#include <linux/firmware.h>
+#include <linux/wait.h>
+
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include "ar3kpsparser.h"
+
+#define FPGA_REGISTER	0x4FFC
+
+
+#define PS_ASIC_FILE      "PS_ASIC.pst"
+#define PS_FPGA_FILE      "PS_FPGA.pst"
+
+#define PATCH_FILE      "RamPatch.txt"
+#define BDADDR_FILE "ar3kbdaddr.pst"
+
+
+#ifndef HCI_TRANSPORT_SDIO
+#define AR3K_CONFIG_INFO        struct hci_dev
+extern wait_queue_head_t HciEvent;
+extern wait_queue_t Eventwait;
+extern A_UCHAR *HciEventpacket;
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+A_STATUS ReadPSEvent(A_UCHAR* Data);
+#endif /* __AR3KPSCONFIG_H */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
new file mode 100644
index 000000000000..8392777512ec
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ * ar3kpsparser.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+#include "ar3kpsparser.h"
+
+#define BD_ADDR_SIZE            6
+#define WRITE_PATCH             8
+#define ENABLE_PATCH            11
+#define PS_RESET                2
+#define PS_WRITE                1
+#define PS_VERIFY_CRC           9
+#define CHANGE_BDADDR           15
+
+#define HCI_COMMAND_HEADER      7
+
+#define HCI_EVENT_SIZE          7
+
+#define WRITE_PATCH_COMMAND_STATUS_OFFSET 5
+
+#define RAM_PS_REGION           (1<<0)
+#define RAM_PATCH_REGION        (1<<1)
+#define RAMPS_MAX_PS_DATA_PER_TAG         20000
+#define MAX_RADIO_CFG_TABLE_SIZE  244
+#define RAMPS_MAX_PS_TAGS_PER_FILE        50
+
+#define PS_MAX_LEN                        500 
+#define LINE_SIZE_MAX                     (PS_MAX_LEN *2) 
+
+/* Constant values used by parser */
+#define BYTES_OF_PS_DATA_PER_LINE         16
+#define RAMPS_MAX_PS_DATA_PER_TAG         20000
+
+
+/* Number pf PS/Patch entries in an HCI packet */
+#define MAX_BYTE_LENGTH                   244
+
+#define SKIP_BLANKS(str) while (*str == ' ') str++
+#define MIN(x, y) (((x) <= (y))? (x):(y))
+#define MAX(x, y) (((x) >= (y))? (x):(y))
+
+#define UNUSED(x) (x=x)
+
+#define IS_BETWEEN(x, lower, upper) (((lower) <= (x)) && ((x) <= (upper)))
+#define IS_DIGIT(c) (IS_BETWEEN((c), '0', '9'))
+#define IS_HEX(c)   (IS_BETWEEN((c), '0', '9') || IS_BETWEEN((c), 'a', 'f') || IS_BETWEEN((c), 'A', 'F'))
+#define TO_LOWER(c) (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 'a') : (c))
+#define IS_BLANK(c) ((c) == ' ')
+#define CONV_DEC_DIGIT_TO_VALUE(c) ((c) - '0')
+#define CONV_HEX_DIGIT_TO_VALUE(c) (IS_DIGIT(c) ? ((c) - '0') : (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 10) : ((c) - 'a' + 10))) 
+#define CONV_VALUE_TO_HEX(v) ((A_UINT8)( ((v & 0x0F) <= 9) ? ((v & 0x0F) + '0') : ((v & 0x0F) - 10 + 'A') ) )
+
+
+enum MinBootFileFormatE
+{
+   MB_FILEFORMAT_RADIOTBL,
+   MB_FILEFORMAT_PATCH,
+   MB_FILEFORMAT_COEXCONFIG
+};
+
+enum RamPsSection
+{
+   RAM_PS_SECTION,
+   RAM_PATCH_SECTION,
+   RAM_DYN_MEM_SECTION
+};
+
+enum eType {
+   eHex,
+   edecimal
+};
+
+
+typedef struct tPsTagEntry
+{
+   A_UINT32   TagId;
+   A_UINT32   TagLen;
+   A_UINT8    *TagData;
+} tPsTagEntry, *tpPsTagEntry;
+
+typedef struct tRamPatch
+{
+   A_UINT16   Len;
+   A_UINT8    * Data;
+} tRamPatch, *ptRamPatch;
+
+
+
+typedef struct ST_PS_DATA_FORMAT {
+   enum eType   eDataType;
+   A_BOOL    bIsArray;
+}ST_PS_DATA_FORMAT;
+
+typedef struct ST_READ_STATUS {
+    unsigned uTagID;
+    unsigned uSection;
+    unsigned uLineCount;
+    unsigned uCharCount;
+    unsigned uByteCount;
+}ST_READ_STATUS;
+
+
+/* Stores the number of PS Tags */
+static A_UINT32 Tag_Count = 0;
+
+/* Stores the number of patch commands */
+static A_UINT32 Patch_Count = 0;
+static A_UINT32 Total_tag_lenght = 0;
+static A_BOOL BDADDR = FALSE;
+A_UINT32      StartTagId;
+
+tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE];
+tRamPatch   RamPatch[MAX_NUM_PATCH_ENTRY];
+
+
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat);
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos);
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos);
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index);
+
+/* Function to reads the next character from the input buffer */
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos) 
+{
+    char Ch;
+    if(buffer == NULL || *pos >=len )
+    {
+        return '\0';
+    } else {
+        Ch = buffer[*pos];
+        (*pos)++;
+        return Ch;
+    }
+}
+/* PS parser helper function */
+unsigned int uGetInputDataFormat(char* pCharLine, ST_PS_DATA_FORMAT *pstFormat) 
+{
+    if(pCharLine[0] != '[') {
+        pstFormat->eDataType = eHex;
+        pstFormat->bIsArray = true;
+        return 0;
+    }
+    switch(pCharLine[1]) {
+        case 'H':
+        case 'h':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'a') || (pCharLine[3]== 'A')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+                    return 1;
+                }
+            }
+            if((pCharLine[3]== 'S') || (pCharLine[3]== 's')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = false;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+                    return 1;
+                }
+            }
+            else if(pCharLine[3] == ']') {         //[H:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[H:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+            return 1;            
+        }
+        break;
+
+        case 'A':
+        case 'a':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 1\n")); //[A:H
+                    return 1;
+                }
+             }
+            else if(pCharLine[3]== ']') {         //[A:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[A:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 2\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 3\n"));
+            return 1;            
+        }
+        break;
+
+        case 'S':
+        case 's':
+        if(pCharLine[2]==':') {
+            if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+                if(pCharLine[4] == ']') {
+                    pstFormat->eDataType = eHex;
+                    pstFormat->bIsArray = true;
+                    pCharLine += 5;
+                    return 0;
+                }
+                else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 5\n")); //[A:H
+                    return 1;
+                }
+             }
+            else if(pCharLine[3]== ']') {         //[A:]
+                pstFormat->eDataType = eHex;
+                pstFormat->bIsArray = true;
+                pCharLine += 4;
+                return 0;
+            }
+            else {                            //[A:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 6\n"));
+                return 1;                    
+            }
+        }
+        else if(pCharLine[2]==']') {    //[H]
+            pstFormat->eDataType = eHex;
+            pstFormat->bIsArray = true;
+            pCharLine += 3;
+            return 0;
+        }
+        else {                      //[H
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 7\n"));
+            return 1;            
+        }
+        break;
+    
+        default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 8\n"));
+        return 1;
+    }
+}
+
+unsigned int uReadDataInSection(char *pCharLine, ST_PS_DATA_FORMAT stPS_DataFormat)
+{
+    char *pTokenPtr = pCharLine;
+
+    if(pTokenPtr[0] == '[') {
+        while(pTokenPtr[0] != ']' && pTokenPtr[0] != '\0') {
+            pTokenPtr++;
+        }
+        if(pTokenPtr[0] == '\0') {
+            return (0x0FFF);
+        }
+        pTokenPtr++;
+            
+
+    }
+    if(stPS_DataFormat.eDataType == eHex) {
+        if(stPS_DataFormat.bIsArray == true) {
+            //Not implemented
+            return (0x0FFF);
+        }
+        else {
+            return (A_STRTOL(pTokenPtr, NULL, 16));
+        }
+    }
+    else {
+        //Not implemented
+        return (0x0FFF);
+    }
+}
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat)
+{
+   char     *Buffer;
+   char     *pCharLine;
+   A_UINT8    TagCount;
+   A_UINT16   ByteCount;
+   A_UINT8    ParseSection=RAM_PS_SECTION;
+   A_UINT32 pos;
+
+
+
+   int uReadCount;
+   ST_PS_DATA_FORMAT stPS_DataFormat;
+   ST_READ_STATUS   stReadStatus = {0, 0, 0,0};
+   pos = 0;
+   Buffer = NULL;
+
+   if (srcbuffer == NULL || srclen == 0)
+   {
+      AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Could not open .\n"));
+      return A_ERROR;
+   }
+   TagCount = 0;
+   ByteCount = 0;
+   Buffer = A_MALLOC(LINE_SIZE_MAX + 1);
+   if(NULL == Buffer) {
+       return A_ERROR;
+   }
+   if (FileFormat == MB_FILEFORMAT_PATCH)
+   {
+      int LineRead = 0;
+      while((pCharLine = AthGetLine(Buffer, LINE_SIZE_MAX, srcbuffer,srclen,&pos)) != NULL)
+      {
+
+         SKIP_BLANKS(pCharLine);
+
+         // Comment line or empty line
+         if ((pCharLine[0] == '/') && (pCharLine[1] == '/'))
+         {
+            continue;
+         }
+         
+         if ((pCharLine[0] == '#')) { 
+             if (stReadStatus.uSection != 0)
+             {
+                 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
+                 if(Buffer != NULL) {
+                     A_FREE(Buffer);
+                 }
+                 return A_ERROR;
+             }
+             else {
+                 stReadStatus.uSection = 1;
+                 continue;
+             }
+         }
+         if ((pCharLine[0] == '/') && (pCharLine[1] == '*'))
+         {
+            pCharLine+=2;
+            SKIP_BLANKS(pCharLine);
+
+            if(!strncmp(pCharLine,"PA",2)||!strncmp(pCharLine,"Pa",2)||!strncmp(pCharLine,"pa",2))
+                ParseSection=RAM_PATCH_SECTION;
+
+            if(!strncmp(pCharLine,"DY",2)||!strncmp(pCharLine,"Dy",2)||!strncmp(pCharLine,"dy",2))
+                ParseSection=RAM_DYN_MEM_SECTION;
+
+            if(!strncmp(pCharLine,"PS",2)||!strncmp(pCharLine,"Ps",2)||!strncmp(pCharLine,"ps",2))
+                ParseSection=RAM_PS_SECTION;
+
+            LineRead = 0;
+            stReadStatus.uSection = 0;
+
+            continue;
+    }
+         
+         switch(ParseSection)
+         {
+             case RAM_PS_SECTION:
+             {
+                 if (stReadStatus.uSection == 1)  //TagID
+                 {
+                    SKIP_BLANKS(pCharLine);
+                    if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                        return A_ERROR;
+                    }    
+                    //pCharLine +=5;
+                    PsTagEntry[TagCount].TagId = uReadDataInSection(pCharLine, stPS_DataFormat);                            
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG ID %d \n",PsTagEntry[TagCount].TagId));
+
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag # %x\n", PsTagEntry[TagCount].TagId);
+                    if (TagCount == 0)
+                    {
+                       StartTagId = PsTagEntry[TagCount].TagId;
+                    }
+                    stReadStatus.uSection = 2;
+                 }
+                 else if (stReadStatus.uSection == 2) //TagLength
+                 {
+            
+                    if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                        return A_ERROR;
+                    }
+                    //pCharLine +=5;
+                    ByteCount = uReadDataInSection(pCharLine, stPS_DataFormat);
+
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag length %x\n", ByteCount));
+                    if (ByteCount > LINE_SIZE_MAX/2)
+                    {
+                     if(Buffer != NULL) {
+                             A_FREE(Buffer);
+                     }
+                       return A_ERROR;
+                    }
+                    PsTagEntry[TagCount].TagLen = ByteCount;
+                    PsTagEntry[TagCount].TagData = (A_UINT8*)A_MALLOC(ByteCount);
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG Length %d  Tag Index %d \n",PsTagEntry[TagCount].TagLen,TagCount));
+                    stReadStatus.uSection = 3;
+                    stReadStatus.uLineCount = 0;
+                 }
+                 else if( stReadStatus.uSection == 3) {  //Data
+
+                    if(stReadStatus.uLineCount == 0) {
+                        if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
+                            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
+                            if(Buffer != NULL) {
+                                 A_FREE(Buffer);
+                         }
+                            return A_ERROR;
+                        }
+                        //pCharLine +=5;
+                    }
+           SKIP_BLANKS(pCharLine);
+                    stReadStatus.uCharCount = 0;
+            if(pCharLine[stReadStatus.uCharCount] == '[') {
+            while(pCharLine[stReadStatus.uCharCount] != ']' && pCharLine[stReadStatus.uCharCount] != '\0' ) {
+                            stReadStatus.uCharCount++;
+            }
+            if(pCharLine[stReadStatus.uCharCount] == ']' ) {
+                            stReadStatus.uCharCount++;
+            } else {
+                            stReadStatus.uCharCount = 0;
+            }
+            }
+                    uReadCount = (ByteCount > BYTES_OF_PS_DATA_PER_LINE)? BYTES_OF_PS_DATA_PER_LINE: ByteCount;
+                    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" "));
+                    if((stPS_DataFormat.eDataType == eHex) && stPS_DataFormat.bIsArray == true) {
+                       while(uReadCount > 0) {
+                           PsTagEntry[TagCount].TagData[stReadStatus.uByteCount] =
+                                                     (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount]) << 4)
+                                                     | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 1]));
+
+                           PsTagEntry[TagCount].TagData[stReadStatus.uByteCount+1] =
+                                                     (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 3]) << 4)
+                                                     | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 4]));
+
+                           stReadStatus.uCharCount += 6; // read two bytes, plus a space;
+                           stReadStatus.uByteCount += 2;
+                           uReadCount -= 2;
+                       }
+                       if(ByteCount > BYTES_OF_PS_DATA_PER_LINE) {
+                              ByteCount -= BYTES_OF_PS_DATA_PER_LINE;
+                       }
+                       else {
+                          ByteCount = 0;
+                       }
+                    }
+                    else {
+                        //to be implemented
+                    }
+
+                    stReadStatus.uLineCount++;
+                    
+                    if(ByteCount == 0) {
+                        stReadStatus.uSection = 0;
+                        stReadStatus.uCharCount = 0;
+                        stReadStatus.uLineCount = 0;
+                        stReadStatus.uByteCount = 0;
+                    }
+                    else { 
+                        stReadStatus.uCharCount = 0;
+                    }
+
+                    if((stReadStatus.uSection == 0)&&(++TagCount == RAMPS_MAX_PS_TAGS_PER_FILE))
+                    {
+                       AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
+                       if(Buffer != NULL) {
+                           A_FREE(Buffer);
+                       }
+                       return A_ERROR;
+                       //Sleep (3000);
+                       //exit(1);
+                    }
+        
+                 }
+             }
+
+             break;
+             default:
+             {
+                   if(Buffer != NULL) {
+                       A_FREE(Buffer);
+                   }
+                   return A_ERROR;
+             }
+             break;
+         }
+         LineRead++;
+      }
+      Tag_Count = TagCount;
+      AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Number of Tags %d\n", Tag_Count));
+   }
+
+
+   if (TagCount > RAMPS_MAX_PS_TAGS_PER_FILE)
+   {
+
+      if(Buffer != NULL) {
+           A_FREE(Buffer);
+      }
+      return A_ERROR;
+   }
+
+   if(Buffer != NULL) {
+        A_FREE(Buffer);
+   }
+   return A_OK;
+
+}
+
+
+
+/********************/
+
+
+A_STATUS GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char * buffer)
+{
+    unsigned char ch;
+
+    ch = AthReadChar(srcbuffer,len,pos);
+    if(ch != '\0' && IS_HEX(ch)) {
+        buffer[0] =  ch;
+    } else 
+    {
+        return A_ERROR;
+    }
+    ch = AthReadChar(srcbuffer,len,pos);
+    if(ch != '\0' && IS_HEX(ch)) {
+        buffer[1] =  ch;
+    } else 
+    {
+        return A_ERROR;
+    }
+    return A_OK;
+}
+
+A_STATUS AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
+{
+
+    char  Byte[3];
+    char   Line[MAX_BYTE_LENGTH + 1];
+    int    ByteCount,ByteCount_Org;
+    int count;
+    int i,j,k;
+    int data;
+    A_UINT32 filepos;
+    Byte[2] = '\0';
+    j = 0;
+    filepos = 0;
+
+    while(NULL != AthGetLine(Line,MAX_BYTE_LENGTH,patchbuffer,patchlen,&filepos)) {
+        if(strlen(Line) <= 1 || !IS_HEX(Line[0])) {
+            continue;
+        } else {
+            break;
+        }
+    }
+    ByteCount = A_STRTOL(Line, NULL, 16);
+    ByteCount_Org = ByteCount;
+
+    while(ByteCount > MAX_BYTE_LENGTH){
+
+        /* Handle case when the number of patch buffer is more than the 20K */
+        if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
+            for(i = 0; i < Patch_Count; i++) {
+                A_FREE(RamPatch[i].Data);
+            }
+            return A_ERROR;
+        }
+        RamPatch[Patch_Count].Len= MAX_BYTE_LENGTH;
+        RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(MAX_BYTE_LENGTH);
+        Patch_Count ++;
+
+
+        ByteCount= ByteCount - MAX_BYTE_LENGTH;
+    }
+
+    RamPatch[Patch_Count].Len= (ByteCount & 0xFF);
+    if(ByteCount != 0) {
+        RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(ByteCount);
+        Patch_Count ++;
+    }
+    count = 0;
+    while(ByteCount_Org > MAX_BYTE_LENGTH){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+        for (i = 0,k=0; i < MAX_BYTE_LENGTH*2; i += 2,k++,count +=2) {
+            if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+                return A_ERROR;
+            }
+            data = A_STRTOUL(&Byte[0], NULL, 16);
+            RamPatch[j].Data[k] = (data & 0xFF);
+
+
+        }
+        j++;
+        ByteCount_Org = ByteCount_Org - MAX_BYTE_LENGTH;
+    }
+    if(j == 0){
+        j++;
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+    for (k=0; k < ByteCount_Org; i += 2,k++,count+=2) {
+        if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+            return A_ERROR;
+        }
+        data = A_STRTOUL(Byte, NULL, 16);
+        RamPatch[j].Data[k] = (data & 0xFF);
+
+
+    }
+    return A_OK;
+}
+
+
+/********************/
+A_STATUS AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen)
+{
+    A_STATUS status;
+    int i;
+    A_BOOL BDADDR_Present = A_ERROR;
+
+
+
+    status = A_ERROR;
+
+    if(NULL != srcbuffer && srclen != 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("File Open Operation Successful\n"));
+
+        status = AthParseFilesUnified(srcbuffer,srclen,MB_FILEFORMAT_PATCH); 
+    }
+    
+
+
+        if(Tag_Count == 0){
+                Total_tag_lenght = 10;
+
+        }
+        else{
+                for(i=0; i<Tag_Count; i++){
+                        if(PsTagEntry[i].TagId == 1){
+                                BDADDR_Present = A_OK;
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is present in Patch File \r\n"));
+
+                        }
+                        if(PsTagEntry[i].TagLen % 2 == 1){
+                                Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen + 1;
+                        }
+                        else{
+                                Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen;
+                        }
+
+                }
+        }
+
+        if(Tag_Count > 0 && !BDADDR_Present){
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is not present adding 10 extra bytes \r\n"));
+                Total_tag_lenght=Total_tag_lenght + 10;
+        }
+        Total_tag_lenght = Total_tag_lenght+ 10 + (Tag_Count*4);
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Total Length %d\n",Total_tag_lenght));
+
+
+    return status;
+}
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos)
+{
+
+    int count;
+    static short flag;
+    char CharRead;
+    count = 0;
+    flag = A_ERROR;
+
+    do
+    {
+        CharRead = AthReadChar(srcbuffer,len,pos);
+        if( CharRead == '\0' ) {
+            buffer[count+1] = '\0';
+            if(count == 0) {
+                return NULL;
+            }
+            else {
+                return buffer;
+            }
+        }
+
+        if(CharRead == 13) {
+        } else if(CharRead == 10) {
+            buffer[count] ='\0';  
+            flag = A_ERROR;
+            return buffer;
+        }else {
+            buffer[count++] = CharRead;
+        }
+
+    }
+    while(count < maxlen-1 && CharRead != '\0');
+    buffer[count] = '\0';
+
+    return buffer;
+}
+
+static void LoadHeader(A_UCHAR *HCI_PS_Command,A_UCHAR opcode,int length,int index){
+
+        HCI_PS_Command[0]= 0x0B;
+        HCI_PS_Command[1]= 0xFC;
+        HCI_PS_Command[2]= length + 4;
+        HCI_PS_Command[3]= opcode;
+        HCI_PS_Command[4]= (index & 0xFF);
+        HCI_PS_Command[5]= ((index>>8) & 0xFF);
+        HCI_PS_Command[6]= length;
+}
+
+/////////////////////////
+//
+int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
+{
+
+    A_UINT8 count;
+    A_UINT32 NumcmdEntry = 0; 
+
+    A_UINT32 Crc = 0;
+    *numPackets = 0;
+
+
+    if(Patch_Count > 0)
+            Crc |= RAM_PATCH_REGION;
+    if(Tag_Count > 0)
+            Crc |= RAM_PS_REGION;
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("PS Thread Started CRC %x Patch Count %d  Tag Count %d \n",Crc,Patch_Count,Tag_Count));
+    
+    if(Patch_Count || Tag_Count ){
+    NumcmdEntry+=(2 + Patch_Count + Tag_Count); /* CRC Packet + PS Reset Packet  + Patch List + PS List*/
+        if(Patch_Count > 0) {
+            NumcmdEntry++; /* Patch Enable Command */
+        }
+           AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size  %d  \r\n",NumcmdEntry,sizeof(PSCmdPacket) * NumcmdEntry));
+        (*HciPacketList) = A_MALLOC(sizeof(PSCmdPacket) * NumcmdEntry);
+    if(NULL == *HciPacketList) {
+               AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed  \r\n"));
+        }
+        AthPSCreateHCICommand(PS_VERIFY_CRC,Crc,*HciPacketList,numPackets);
+        if(Patch_Count > 0){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Write Patch**** \r\n"));
+                AthPSCreateHCICommand(WRITE_PATCH,Patch_Count,*HciPacketList,numPackets);
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Enable Patch**** \r\n"));
+                AthPSCreateHCICommand(ENABLE_PATCH,0,*HciPacketList,numPackets);
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Reset**** \r\n"));
+        AthPSCreateHCICommand(PS_RESET,Total_tag_lenght,*HciPacketList,numPackets);
+        if(Tag_Count > 0){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Write**** \r\n"));
+                AthPSCreateHCICommand(PS_WRITE,Tag_Count,*HciPacketList,numPackets);
+        }    
+    }
+    if(!BDADDR){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR not present \r\n"));
+    
+    }
+    for(count = 0; count < Patch_Count; count++) {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
+        A_FREE(RamPatch[Patch_Count].Data);
+    }
+
+    for(count = 0; count < Tag_Count; count++) {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
+        A_FREE(PsTagEntry[count].TagData);
+    }
+
+/* 
+ *  SDIO Transport uses synchronous mode of data transfer 
+ *  So, AthPSOperations() call returns only after receiving the 
+ *  command complete event.
+ */
+    return *numPackets;
+}
+
+
+////////////////////////
+
+/////////////
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index)
+{
+    A_UCHAR *HCI_PS_Command;
+    A_UINT32 Length;
+    int i,j;
+    
+    switch(Opcode)
+    {
+    case WRITE_PATCH:
+
+
+         for(i=0;i< Param1;i++){
+
+             HCI_PS_Command = (A_UCHAR *) A_MALLOC(RamPatch[i].Len+HCI_COMMAND_HEADER);
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Allocated Buffer Size %d\n",RamPatch[i].Len+HCI_COMMAND_HEADER));
+                 if(HCI_PS_Command == NULL){
+                     AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                         return A_ERROR;
+                 }
+                 memset (HCI_PS_Command, 0, RamPatch[i].Len+HCI_COMMAND_HEADER);
+                 LoadHeader(HCI_PS_Command,Opcode,RamPatch[i].Len,i);
+                 for(j=0;j<RamPatch[i].Len;j++){
+                        HCI_PS_Command[HCI_COMMAND_HEADER+j]=RamPatch[i].Data[j];
+                 }
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = RamPatch[i].Len+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+          
+         }
+
+    break;
+
+    case ENABLE_PATCH:
+
+
+         Length = 0;
+         i= 0;
+         HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+         if(HCI_PS_Command == NULL){
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+            return A_ERROR;
+         }
+
+         memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+         LoadHeader(HCI_PS_Command,Opcode,Length,i);
+         PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+         PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+         (*index)++;
+
+    break;
+
+    case PS_RESET:
+                        Length = 0x06;
+                        i=0;
+                        HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+                        if(HCI_PS_Command == NULL){
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                return A_ERROR;
+                        }
+                        memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+                        LoadHeader(HCI_PS_Command,Opcode,Length,i);
+                        HCI_PS_Command[7]= 0x00;
+                        HCI_PS_Command[Length+HCI_COMMAND_HEADER -2]= (Param1 & 0xFF);
+                        HCI_PS_Command[Length+HCI_COMMAND_HEADER -1]= ((Param1 >>  8) & 0xFF);
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+    break;
+
+    case PS_WRITE:
+                       for(i=0;i< Param1;i++){
+                                if(PsTagEntry[i].TagId ==1)
+                                        BDADDR = TRUE;
+
+                                HCI_PS_Command = (A_UCHAR *) A_MALLOC(PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+                                if(HCI_PS_Command == NULL){
+                                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                        return A_ERROR;
+                                }
+
+                                memset (HCI_PS_Command, 0, PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+                                LoadHeader(HCI_PS_Command,Opcode,PsTagEntry[i].TagLen,PsTagEntry[i].TagId);
+
+                                for(j=0;j<PsTagEntry[i].TagLen;j++){
+                                        HCI_PS_Command[HCI_COMMAND_HEADER+j]=PsTagEntry[i].TagData[j];
+                                }
+
+                     PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                     PSPatchPacket[*index].packetLen = PsTagEntry[i].TagLen+HCI_COMMAND_HEADER;
+                     (*index)++;
+
+                        }
+
+    break;
+
+
+    case PS_VERIFY_CRC:
+                        Length = 0x0;
+
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("VALUE of CRC:%d At index %d\r\n",Param1,*index));
+
+                        HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+                        if(HCI_PS_Command == NULL){
+                                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+                                return A_ERROR;
+                        }
+                        memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+                        LoadHeader(HCI_PS_Command,Opcode,Length,Param1);
+
+                 PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+                 PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+                 (*index)++;
+
+    break;
+
+    case CHANGE_BDADDR:
+    break;
+    }
+    return A_OK;
+}
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets)
+{
+    int i;
+    if(*HciPacketList == NULL) {
+        return A_ERROR;
+    }
+    for(i = 0; i < numPackets;i++) {
+        A_FREE((*HciPacketList)[i].Hcipacket);
+    }  
+    A_FREE(*HciPacketList);
+    return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
new file mode 100644
index 000000000000..2aaadbb50469
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file is the include file for Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ * ar3kpsparser.h
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices..  Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+/*------------------------------------------------------------------------------
+ *
+ * <copyright file="File name" company="Atheros">
+ * Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * This file is the include file for Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ *
+ *
+ */
+#ifndef __AR3KPSPARSER_H
+#define __AR3KPSPARSER_H
+
+
+
+
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include "athdefs.h"
+#ifdef HCI_TRANSPORT_SDIO
+#include "a_config.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#include "hci_transport_api.h"
+#include "ar3kconfig.h"
+#else
+#ifndef A_PRINTF
+#define A_PRINTF(args...)     printk(KERN_ALERT args)
+#endif /* A_PRINTF */
+#include "debug_linux.h"
+
+/* Helper data type declaration */
+
+#ifndef A_UINT32
+#define A_UCHAR                 unsigned char
+#define A_UINT32                unsigned long
+#define A_UINT16                unsigned short
+#define A_UINT8                 unsigned char
+#define A_BOOL                  unsigned char
+#endif /* A_UINT32 */
+
+#define ATH_DEBUG_ERR          (1 << 0)
+#define ATH_DEBUG_WARN         (1 << 1)
+#define ATH_DEBUG_INFO         (1 << 2)
+
+
+
+#define FALSE   0
+#define TRUE    1
+
+#ifndef A_MALLOC
+#define A_MALLOC(size)  kmalloc((size),GFP_KERNEL)
+#endif /* A_MALLOC */
+
+
+#ifndef A_FREE
+#define A_FREE(addr)  kfree((addr))
+#endif /* A_MALLOC */
+#endif /* HCI_TRANSPORT_UART */
+
+/* String manipulation APIs */
+#ifndef A_STRTOUL
+#define A_STRTOUL               simple_strtoul
+#endif  /* A_STRTOL */
+
+#ifndef A_STRTOL 
+#define A_STRTOL                simple_strtol
+#endif /* A_STRTOL */
+
+
+/* The maximum number of bytes possible in a patch entry */
+#define MAX_PATCH_SIZE                    20000
+
+/* Maximum HCI packets that will be formed from the Patch file */
+#define MAX_NUM_PATCH_ENTRY               (MAX_PATCH_SIZE/MAX_BYTE_LENGTH) + 1
+
+
+
+
+
+
+
+typedef struct PSCmdPacket
+{
+    A_UCHAR *Hcipacket;
+    int packetLen;
+} PSCmdPacket;
+
+/* Parses a Patch information buffer and store it in global structure */
+A_STATUS AthDoParsePatch(A_UCHAR *, A_UINT32);
+
+/* parses a PS information buffer and stores it in a global structure */
+A_STATUS AthDoParsePS(A_UCHAR *, A_UINT32);
+
+/* 
+ *  Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with
+ *  all the PS and patch commands.
+ *  The list will have the below mentioned commands in order.
+ *  CRC command packet
+ *  Download patch command(s)
+ *  Enable patch Command
+ *  PS Reset Command
+ *  PS Tag Command(s)
+ *
+ */  
+int AthCreateCommandList(PSCmdPacket **, A_UINT32 *);
+
+/* Cleanup the dynamically allicated HCI command list */
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets);
+#endif /* __AR3KPSPARSER_H */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/common_drv.c b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c
new file mode 100644
index 000000000000..0a318c3c8de4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c
@@ -0,0 +1,973 @@
+//------------------------------------------------------------------------------
+// <copyright file="common_drv.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+
+#include "AR6002/hw/mbox_host_reg.h"
+#include "AR6002/hw/apb_map.h"
+#include "AR6002/hw/si_reg.h"
+#include "AR6002/hw/gpio_reg.h"
+#include "AR6002/hw/rtc_reg.h"
+#include "AR6002/hw/vmc_reg.h"
+#include "AR6002/hw/mbox_reg.h"
+
+#include "targaddrs.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "bmi.h"
+#include "bmi_msg.h"
+#include "common_drv.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "ar6000_diag.h"
+
+static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
+static A_MUTEX_T                 g_ModuleListLock;
+static A_BOOL                    g_ModuleDebugInit = FALSE;
+
+#ifdef DEBUG
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
+                                 "misc",
+                                 "Common and misc APIs",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 0,
+                                 NULL);
+
+#endif
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
+        (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
+
+
+#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
+#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
+#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
+#define CPU_DBG_SEL_ADDRESS                      0x00000483
+#define CPU_DBG_ADDRESS                          0x00000484
+
+/* Compile the 4BYTE version of the window register setup routine,
+ * This mitigates host interconnect issues with non-4byte aligned bus requests, some
+ * interconnects use bus adapters that impose strict limitations.
+ * Since diag window access is not intended for performance critical operations, the 4byte mode should
+ * be satisfactory even though it generates 4X the bus activity. */
+
+#ifdef USE_4BYTE_REGISTER_ACCESS
+
+    /* set the window address register (using 4-byte register access ). */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+    A_STATUS status;
+    A_UINT8 addrValue[4];
+    A_INT32 i;
+
+        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+         * last to initiate the access cycle */
+
+    for (i = 1; i <= 3; i++) {
+            /* fill the buffer with the address byte value we want to hit 4 times*/
+        addrValue[0] = ((A_UINT8 *)&Address)[i];
+        addrValue[1] = addrValue[0];
+        addrValue[2] = addrValue[0];
+        addrValue[3] = addrValue[0];
+
+            /* hit each byte of the register address with a 4-byte write operation to the same address,
+             * this is a harmless operation */
+        status = HIFReadWrite(hifDevice,
+                              RegisterAddr+i,
+                              addrValue,
+                              4,
+                              HIF_WR_SYNC_BYTE_FIX,
+                              NULL);
+        if (status != A_OK) {
+            break;
+        }
+    }
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+            Address, RegisterAddr));
+        return status;
+    }
+
+        /* write the address register again, this time write the whole 4-byte value.
+         * The effect here is that the LSB write causes the cycle to start, the extra
+         * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr,
+                          (A_UCHAR *)(&Address),
+                          4,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+            Address, RegisterAddr));
+        return status;
+    }
+
+    return A_OK;
+
+
+
+}
+
+
+#else
+
+    /* set the window address register */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+    A_STATUS status;
+
+        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+         * last to initiate the access cycle */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr+1,  /* write upper 3 bytes */
+                          ((A_UCHAR *)(&Address))+1,
+                          sizeof(A_UINT32)-1,
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+             RegisterAddr, Address));
+        return status;
+    }
+
+        /* write the LSB of the register, this initiates the operation */
+    status = HIFReadWrite(hifDevice,
+                          RegisterAddr,
+                          (A_UCHAR *)(&Address),
+                          sizeof(A_UINT8),
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+            RegisterAddr, Address));
+        return status;
+    }
+
+    return A_OK;
+}
+
+#endif
+
+/*
+ * Read from the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+    A_STATUS status;
+
+        /* set window register to start read cycle */
+    status = ar6000_SetAddressWindowRegister(hifDevice,
+                                             WINDOW_READ_ADDR_ADDRESS,
+                                             *address);
+
+    if (status != A_OK) {
+        return status;
+    }
+
+        /* read the data */
+    status = HIFReadWrite(hifDevice,
+                          WINDOW_DATA_ADDRESS,
+                          (A_UCHAR *)data,
+                          sizeof(A_UINT32),
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
+        return status;
+    }
+
+    return status;
+}
+
+
+/*
+ * Write to the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+    A_STATUS status;
+
+        /* set write data */
+    status = HIFReadWrite(hifDevice,
+                          WINDOW_DATA_ADDRESS,
+                          (A_UCHAR *)data,
+                          sizeof(A_UINT32),
+                          HIF_WR_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
+        return status;
+    }
+
+        /* set window register, which starts the write cycle */
+    return ar6000_SetAddressWindowRegister(hifDevice,
+                                           WINDOW_WRITE_ADDR_ADDRESS,
+                                           *address);
+    }
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length)
+{
+    A_UINT32 count;
+    A_STATUS status = A_OK;
+
+    for (count = 0; count < length; count += 4, address += 4) {
+        if ((status = ar6000_ReadRegDiag(hifDevice, &address,
+                                         (A_UINT32 *)&data[count])) != A_OK)
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+                    A_UCHAR *data, A_UINT32 length)
+{
+    A_UINT32 count;
+    A_STATUS status = A_OK;
+
+    for (count = 0; count < length; count += 4, address += 4) {
+        if ((status = ar6000_WriteRegDiag(hifDevice, &address,
+                                         (A_UINT32 *)&data[count])) != A_OK)
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval)
+{
+    A_STATUS status;
+    A_UCHAR vals[4];
+    A_UCHAR register_selection[4];
+
+    register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
+    status = HIFReadWrite(hifDevice,
+                          CPU_DBG_SEL_ADDRESS,
+                          register_selection,
+                          4,
+                          HIF_WR_SYNC_BYTE_FIX,
+                          NULL);
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
+        return status;
+    }
+
+    status = HIFReadWrite(hifDevice,
+                          CPU_DBG_ADDRESS,
+                          (A_UCHAR *)vals,
+                          sizeof(vals),
+                          HIF_RD_SYNC_BYTE_INC,
+                          NULL);
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
+        return status;
+    }
+
+    *regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
+
+    return status;
+}
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs)
+{
+    int i;
+    A_UINT32 val;
+
+    for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
+        val=0xffffffff;
+        (void)ar6k_ReadTargetRegister(hifDevice, i, &val);
+        targregs[i] = val;
+    }
+}
+
+#if 0
+static A_STATUS
+_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value)
+{
+    A_STATUS status;
+
+    status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
+    if (status != A_OK)
+    {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
+    }
+
+    return status;
+}
+#endif
+
+
+/*
+ * Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
+ * which is a good sign that it's alive and well.  This is used after
+ * explicitly forcing the Target to reset.
+ *
+ * The wait_msecs time should be sufficiently long to cover any reasonable
+ * boot-time delay.  For instance, AR6001 firmware allow one second for a
+ * low frequency crystal to settle before it calibrates the refclk frequency.
+ *
+ * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
+ */
+#if 0
+static A_STATUS
+_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType)
+{
+    A_INT32 actual_wait;
+    A_INT32 i;
+    A_UINT32 address;
+
+    actual_wait = 0;
+
+    /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
+    if (TargetType == TARGET_TYPE_AR6001) {
+        address = AR6001_LOCAL_COUNT_ADDRESS;
+    } else if (TargetType == TARGET_TYPE_AR6002) {
+       address = AR6002_LOCAL_COUNT_ADDRESS;
+    } else if (TargetType == TARGET_TYPE_AR6003) {
+       address = AR6003_LOCAL_COUNT_ADDRESS;
+    } else {
+       A_ASSERT(0);
+    }
+    address += 0x10;
+    for (i=0; actual_wait < wait_msecs; i++) {
+        A_UINT32 data;
+
+        A_MDELAY(100);
+        actual_wait += 100;
+
+        data = 0;
+        if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) {
+            return A_ERROR;
+        }
+
+        if (data != 0) {
+            /* No need to wait longer -- we have a BMI credit */
+            return A_OK;
+        }
+    }
+    return A_ERROR; /* timed out */
+}
+#endif
+
+#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
+#define AR6002_RESET_CONTROL_ADDRESS 0x00004000
+#define AR6003_RESET_CONTROL_ADDRESS 0x00004000
+/* reset device */
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset)
+{
+    A_STATUS status = A_OK;
+    A_UINT32 address;
+    A_UINT32 data;
+
+    do {
+// Workaround BEGIN
+        // address = RESET_CONTROL_ADDRESS;
+    	
+    	if (coldReset) {
+            data = RESET_CONTROL_COLD_RST_MASK;
+    	}
+    	else {
+            data = RESET_CONTROL_MBOX_RST_MASK;
+    	}
+
+          /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
+        if (TargetType == TARGET_TYPE_AR6001) {
+            address = AR6001_RESET_CONTROL_ADDRESS;
+        } else if (TargetType == TARGET_TYPE_AR6002) {
+            address = AR6002_RESET_CONTROL_ADDRESS;
+        } else if (TargetType == TARGET_TYPE_AR6003) {
+            address = AR6003_RESET_CONTROL_ADDRESS;
+        } else {
+            A_ASSERT(0);
+        }
+
+
+        status = ar6000_WriteRegDiag(hifDevice, &address, &data);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        if (!waitForCompletion) {
+            break;
+        }
+
+#if 0
+        /* Up to 2 second delay to allow things to settle down */
+        (void)_delay_until_target_alive(hifDevice, 2000, TargetType);
+
+        /*
+         * Read back the RESET CAUSE register to ensure that the cold reset
+         * went through.
+         */
+
+        // address = RESET_CAUSE_ADDRESS;
+        /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
+        if (TargetType == TARGET_TYPE_AR6001) {
+            address = 0x0C0000CC;
+        } else if (TargetType == TARGET_TYPE_AR6002) {
+            address = 0x000040C0;
+        } else if (TargetType == TARGET_TYPE_AR6003) {
+            address = 0x000040C0;
+        } else {
+            A_ASSERT(0);
+        }
+
+        data = 0;
+        status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
+        data &= RESET_CAUSE_LAST_MASK;
+        if (data != 2) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
+        }
+#endif
+// Workaroud END
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
+    }
+
+    return A_OK;
+}
+
+#define REG_DUMP_COUNT_AR6001   38  /* WORDs, derived from AR600x_regdump.h */
+#define REG_DUMP_COUNT_AR6002   60
+#define REG_DUMP_COUNT_AR6003   60
+#define REGISTER_DUMP_LEN_MAX   60
+#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6001 too large"
+#endif
+#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6002 too large"
+#endif
+#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6003 too large"
+#endif
+
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+    A_UINT32 address;
+    A_UINT32 regDumpArea = 0;
+    A_STATUS status;
+    A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
+    A_UINT32 regDumpCount = 0;
+    A_UINT32 i;
+
+    do {
+
+            /* the reg dump pointer is copied to the host interest area */
+        address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
+        address = TARG_VTOP(TargetType, address);
+
+        if (TargetType == TARGET_TYPE_AR6001) {
+                /* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
+                 * this may be fixed in later firmware versions */
+            address = 0x18a0;
+            regDumpCount = REG_DUMP_COUNT_AR6001;
+        } else  if (TargetType == TARGET_TYPE_AR6002) {
+            regDumpCount = REG_DUMP_COUNT_AR6002;
+        } else  if (TargetType == TARGET_TYPE_AR6003) {
+            regDumpCount = REG_DUMP_COUNT_AR6003;
+        } else {
+            A_ASSERT(0);
+        }
+
+            /* read RAM location through diagnostic window */
+        status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
+
+        if (regDumpArea == 0) {
+                /* no reg dump */
+            break;
+        }
+
+        regDumpArea = TARG_VTOP(TargetType, regDumpArea);
+
+            /* fetch register dump data */
+        status = ar6000_ReadDataDiag(hifDevice,
+                                     regDumpArea,
+                                     (A_UCHAR *)&regDumpValues[0],
+                                     regDumpCount * (sizeof(A_UINT32)));
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
+            break;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
+
+        for (i = 0; i < regDumpCount; i++) {
+            //ATHR_DISPLAY_MSG (_T(" %d :  0x%8.8X \n"), i, regDumpValues[i]);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d :  0x%8.8X \n",i, regDumpValues[i]));
+
+#ifdef UNDER_CE
+        /*
+         * For Every logPrintf() Open the File so that in case of Crashes
+         * We will have until the Last Message Flushed on to the File
+         * So use logPrintf Sparingly..!!
+         */
+        tgtassertPrintf (ATH_DEBUG_TRC," %d:  0x%8.8X \n",i, regDumpValues[i]);
+#endif
+        }
+
+    } while (FALSE);
+
+}
+
+/* set HTC/Mbox operational parameters, this can only be called when the target is in the
+ * BMI phase */
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    MboxIsrYieldValue,
+                               A_UINT8     HtcControlBuffers)
+{
+    A_STATUS status;
+    A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+    do {
+            /* get the block sizes */
+        status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+                                    blocksizes, sizeof(blocksizes));
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
+            break;
+        }
+            /* note: we actually get the block size for mailbox 1, for SDIO the block
+             * size on mailbox 0 is artificially set to 1 */
+            /* must be a power of 2 */
+        A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
+
+        if (HtcControlBuffers != 0) {
+                /* set override for number of control buffers to use */
+            blocksizes[1] |=  ((A_UINT32)HtcControlBuffers) << 16;
+        }
+
+            /* set the host interest area for the block size */
+        status = BMIWriteMemory(hifDevice,
+                                HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
+                                (A_UCHAR *)&blocksizes[1],
+                                4);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
+            break;
+        }
+
+        AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
+                blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
+
+        if (MboxIsrYieldValue != 0) {
+                /* set the host interest area for the mbox ISR yield limit */
+            status = BMIWriteMemory(hifDevice,
+                                    HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
+                                    (A_UCHAR *)&MboxIsrYieldValue,
+                                    4);
+
+            if (A_FAILED(status)) {
+                AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
+                break;
+            }
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+
+static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+    A_STATUS status = A_OK;
+
+    /* placeholder */
+
+    return status;
+}
+
+static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+    A_STATUS status = A_OK;
+
+    /* placeholder */
+
+    return status;
+}
+
+/* this function assumes the caller has already initialized the BMI APIs */
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+                               A_UINT32    TargetType,
+                               A_UINT32    TargetVersion)
+{
+    if (TargetType == TARGET_TYPE_AR6002) {
+            /* do any preparations for AR6002 devices */
+        return prepare_ar6002(hifDevice,TargetVersion);
+    } else if (TargetType == TARGET_TYPE_AR6003) {
+        return prepare_ar6003(hifDevice,TargetVersion);
+    }
+
+    return A_OK;
+}
+
+#if defined(CONFIG_AR6002_REV1_FORCE_HOST)
+/*
+ * Call this function just before the call to BMIInit
+ * in order to force* AR6002 rev 1.x firmware to detect a Host.
+ * THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
+ * TBDXXX: Remove this function when REV 1.x is desupported.
+ */
+A_STATUS
+ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice)
+{
+    A_INT32 i;
+    struct forceROM_s {
+        A_UINT32 addr;
+        A_UINT32 data;
+    };
+    struct forceROM_s *ForceROM;
+    A_INT32 szForceROM;
+    A_STATUS status = A_OK;
+    A_UINT32 address;
+    A_UINT32 data;
+
+    /* Force AR6002 REV1.x to recognize Host presence.
+     *
+     * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
+     * so that this workaround functions with AR6002.war1.sh.  We
+     * could fold that entire workaround into this one, but it's not
+     * worth the effort at this point.  This workaround cannot be
+     * merged into the other workaround because this must be done
+     * before BMI.
+     */
+
+    static struct forceROM_s ForceROM_NEW[] = {
+        {0x52df80, 0x20f31c07},
+        {0x52df84, 0x92374420},
+        {0x52df88, 0x1d120c03},
+        {0x52df8c, 0xff8216f0},
+        {0x52df90, 0xf01d120c},
+        {0x52df94, 0x81004136},
+        {0x52df98, 0xbc9100bd},
+        {0x52df9c, 0x00bba100},
+
+        {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
+        {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
+        {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
+        {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
+
+        {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
+
+        {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
+    };
+
+    address = 0x004ed4b0; /* REV1 target software ID is stored here */
+    status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+    if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) {
+        return A_ERROR; /* Not AR6002 REV1 */
+    }
+
+    ForceROM = ForceROM_NEW;
+    szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
+
+    ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
+    for (i = 0; i < szForceROM; i++)
+    {
+        if (ar6000_WriteRegDiag(hifDevice,
+                                &ForceROM[i].addr,
+                                &ForceROM[i].data) != A_OK)
+        {
+            ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
+            return A_ERROR;
+        }
+    }
+
+    A_MDELAY(1000);
+
+    return A_OK;
+}
+
+#endif /* CONFIG_AR6002_REV1_FORCE_HOST */
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
+{
+    A_CHAR stream[60];
+    A_CHAR byteOffsetStr[10];
+    A_UINT32 i;
+    A_UINT16 offset, count, byteOffset;
+
+    A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
+
+    count = 0;
+    offset = 0;
+    byteOffset = 0;
+    for(i = 0; i < length; i++) {
+        A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
+        count ++;
+        offset += 3;
+
+        if(count == 16) {
+            count = 0;
+            offset = 0;
+            A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+            A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+            A_MEMZERO(stream, 60);
+            byteOffset += 16;
+        }
+    }
+
+    if(offset != 0) {
+        A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+        A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+    }
+
+    A_PRINTF("<------------------------------------------------->\n");
+}
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+    int                         i;
+    ATH_DEBUG_MASK_DESCRIPTION *pDesc;
+
+    if (pInfo == NULL) {
+        return;
+    }
+
+    pDesc = pInfo->pMaskDescriptions;
+
+    A_PRINTF("========================================================\n\n");
+    A_PRINTF("Module Debug Info => Name   : %s    \n", pInfo->ModuleName);
+    A_PRINTF("                  => Descr. : %s \n", pInfo->ModuleDescription);
+    A_PRINTF("\n  Current mask    => 0x%8.8X \n", pInfo->CurrentMask);
+    A_PRINTF("\n  Avail. Debug Masks :\n\n");
+
+    for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
+        A_PRINTF("                  => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
+    }
+
+    if (0 == i) {
+        A_PRINTF("                  => * none defined * \n");
+    }
+
+    A_PRINTF("\n  Standard Debug Masks :\n\n");
+        /* print standard masks */
+    A_PRINTF("                  => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
+    A_PRINTF("                  => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
+    A_PRINTF("                  => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
+    A_PRINTF("                  => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
+    A_PRINTF("\n========================================================\n");
+
+}
+
+
+static ATH_DEBUG_MODULE_DBG_INFO *FindModule(A_CHAR *module_name)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+    if (!g_ModuleDebugInit) {
+        return NULL;
+    }
+
+    while (pInfo != NULL) {
+            /* TODO: need to use something other than strlen */
+        if (A_MEMCMP(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
+            break;
+        }
+        pInfo = pInfo->pNext;
+    }
+
+    return pInfo;
+}
+
+
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    A_MUTEX_LOCK(&g_ModuleListLock);
+
+    if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
+        if (g_pModuleInfoHead == NULL) {
+            g_pModuleInfoHead = pInfo;
+        } else {
+           pInfo->pNext = g_pModuleInfoHead;
+           g_pModuleInfoHead = pInfo;
+        }
+        pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
+    }
+
+    A_MUTEX_UNLOCK(&g_ModuleListLock);
+}
+
+void a_dump_module_debug_info_by_name(A_CHAR *module_name)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    if (A_MEMCMP(module_name,"all",3) == 0) {
+            /* dump all */
+        while (pInfo != NULL) {
+            a_dump_module_debug_info(pInfo);
+            pInfo = pInfo->pNext;
+        }
+        return;
+    }
+
+    pInfo = FindModule(module_name);
+
+    if (pInfo != NULL) {
+         a_dump_module_debug_info(pInfo);
+    }
+
+}
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+    if (NULL == pInfo) {
+        return A_ERROR;
+    }
+
+    *pMask = pInfo->CurrentMask;
+    return A_OK;
+}
+
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+    if (NULL == pInfo) {
+        return A_ERROR;
+    }
+
+    pInfo->CurrentMask = Mask;
+    A_PRINTF("Module %s,  new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
+    return A_OK;
+}
+
+
+void a_module_debug_support_init(void)
+{
+    if (g_ModuleDebugInit) {
+        return;
+    }
+    A_MUTEX_INIT(&g_ModuleListLock);
+    g_pModuleInfoHead = NULL;
+    g_ModuleDebugInit = TRUE;
+    A_REGISTER_MODULE_DEBUG_INFO(misc);
+}
+
+void a_module_debug_support_cleanup(void)
+{
+    ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+    ATH_DEBUG_MODULE_DBG_INFO *pCur;
+
+    if (!g_ModuleDebugInit) {
+        return;
+    }
+
+    g_ModuleDebugInit = FALSE;
+
+    A_MUTEX_LOCK(&g_ModuleListLock);
+
+    while (pInfo != NULL) {
+        pCur = pInfo;
+        pInfo = pInfo->pNext;
+        pCur->pNext = NULL;
+            /* clear registered flag */
+        pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
+    }
+
+    A_MUTEX_UNLOCK(&g_ModuleListLock);
+
+    A_MUTEX_DELETE(&g_ModuleListLock);
+    g_pModuleInfoHead = NULL;
+}
+
+    /* can only be called during bmi init stage */
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+                                     A_UINT32    TargetType,
+                                     A_UINT32    Flags)
+{
+    A_STATUS status = A_OK;
+
+    do {
+
+        if (TargetType != TARGET_TYPE_AR6003) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
+                TargetType));
+            break;
+        }
+
+            /* set hci bridge flags */
+        status = BMIWriteMemory(hifDevice,
+                                HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),
+                                (A_UCHAR *)&Flags,
+                                4);
+
+
+    } while (FALSE);
+
+    return status;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c
new file mode 100644
index 000000000000..74426b8f710a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c
@@ -0,0 +1,375 @@
+//------------------------------------------------------------------------------
+// <copyright file="credit_dist.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "htc_api.h"
+#include "common_drv.h"
+
+/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
+
+#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
+
+#ifdef NO_VO_SERVICE
+#define DATA_SVCS_USED 3
+#else
+#define DATA_SVCS_USED 4
+#endif
+
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                        HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+/* reduce an ep's credits back to a set limit */
+static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST  *pEpDist,
+                                int                       Limit)
+{
+    int credits;
+
+        /* set the new limit */
+    pEpDist->TxCreditsAssigned = Limit;
+
+    if (pEpDist->TxCredits <= Limit) {
+        return;
+    }
+
+        /* figure out how much to take away */
+    credits = pEpDist->TxCredits - Limit;
+        /* take them away */
+    pEpDist->TxCredits -= credits;
+    pCredInfo->CurrentFreeCredits += credits;
+}
+
+/* give an endpoint some credits from the free credit pool */
+#define GiveCredits(pCredInfo,pEpDist,credits)      \
+{                                                   \
+    (pEpDist)->TxCredits += (credits);              \
+    (pEpDist)->TxCreditsAssigned += (credits);      \
+    (pCredInfo)->CurrentFreeCredits -= (credits);   \
+}
+
+
+/* default credit init callback.
+ * This function is called in the context of HTCStart() to setup initial (application-specific)
+ * credit distributions */
+static void ar6000_credit_init(void                     *Context,
+                               HTC_ENDPOINT_CREDIT_DIST *pEPList,
+                               int                      TotalCredits)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      count;
+    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+    pCredInfo->CurrentFreeCredits = TotalCredits;
+    pCredInfo->TotalAvailableCredits = TotalCredits;
+
+    pCurEpDist = pEPList;
+
+        /* run through the list and initialize */
+    while (pCurEpDist != NULL) {
+
+            /* set minimums for each endpoint */
+        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+
+        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+                /* give control service some credits */
+            GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
+                /* control service is always marked active, it never goes inactive EVER */
+            SET_EP_ACTIVE(pCurEpDist);
+        } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
+                /* this is the lowest priority data endpoint, save this off for easy access */
+            pCredInfo->pLowestPriEpDist = pCurEpDist;
+        }
+
+        /* Streams have to be created (explicit | implicit)for all kinds
+         * of traffic. BE endpoints are also inactive in the beginning.
+         * When BE traffic starts it creates implicit streams that
+         * redistributes credits.
+         */
+
+        /* note, all other endpoints have minimums set but are initially given NO credits.
+         * Credits will be distributed as traffic activity demands */
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+    if (pCredInfo->CurrentFreeCredits <= 0) {
+        AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
+        A_ASSERT(FALSE);
+        return;
+    }
+
+        /* reset list */
+    pCurEpDist = pEPList;
+        /* now run through the list and set max operating credit limits for everyone */
+    while (pCurEpDist != NULL) {
+        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+                /* control service max is just 1 max message */
+            pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
+        } else {
+                /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
+                 * the same.
+                 * We use a simple calculation here, we take the remaining credits and
+                 * determine how many max messages this can cover and then set each endpoint's
+                 * normal value equal to 3/4 this amount.
+                 * */
+            count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
+            count = (count * 3) >> 2;
+            count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
+                /* set normal */
+            pCurEpDist->TxCreditsNorm = count;
+
+        }
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+
+/* default credit distribution callback
+ * This callback is invoked whenever endpoints require credit distributions.
+ * A lock is held while this function is invoked, this function shall NOT block.
+ * The pEPDistList is a list of distribution structures in prioritized order as
+ * defined by the call to the HTCSetCreditDistribution() api.
+ *
+ */
+static void ar6000_credit_distribute(void                     *Context,
+                                     HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+                                     HTC_CREDIT_DIST_REASON   Reason)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+    switch (Reason) {
+        case HTC_CREDIT_DIST_SEND_COMPLETE :
+            pCurEpDist = pEPDistList;
+                /* we are given the start of the endpoint distribution list.
+                 * There may be one or more endpoints to service.
+                 * Run through the list and distribute credits */
+            while (pCurEpDist != NULL) {
+
+                if (pCurEpDist->TxCreditsToDist > 0) {
+                        /* return the credits back to the endpoint */
+                    pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+                        /* always zero out when we are done */
+                    pCurEpDist->TxCreditsToDist = 0;
+
+                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
+                            /* reduce to the assigned limit, previous credit reductions
+                             * could have caused the limit to change */
+                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
+                    }
+
+                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
+                            /* oversubscribed endpoints need to reduce back to normal */
+                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
+                    }
+                
+                    if (!IS_EP_ACTIVE(pCurEpDist)) {
+                            /* endpoint is inactive, now check for messages waiting for credits */
+                        if (pCurEpDist->TxQueueDepth == 0) {
+                                /* EP is inactive and there are no pending messages, 
+                                 * reduce credits back to zero to recover credits */
+                            ReduceCredits(pCredInfo, pCurEpDist, 0);
+                        }
+                    }
+                }
+
+                pCurEpDist = pCurEpDist->pNext;
+            }
+
+            break;
+
+        case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
+            RedistributeCredits(pCredInfo,pEPDistList);
+            break;
+        case HTC_CREDIT_DIST_SEEK_CREDITS :
+            SeekCredits(pCredInfo,pEPDistList);
+            break;
+        case HTC_DUMP_CREDIT_STATE :
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n",
+            								pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
+            break;
+        default:
+            break;
+
+    }
+
+        /* sanity checks done after each distribution action */
+    A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
+    A_ASSERT(pCredInfo->CurrentFreeCredits >= 0);
+
+}
+
+/* redistribute credits based on activity change */
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
+
+        /* walk through the list and remove credits from inactive endpoints */
+    while (pCurEpDist != NULL) {
+
+        if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
+            if (!IS_EP_ACTIVE(pCurEpDist)) {
+                if (pCurEpDist->TxQueueDepth == 0) {
+                        /* EP is inactive and there are no pending messages, reduce credits back to zero */
+                    ReduceCredits(pCredInfo, pCurEpDist, 0);
+                } else {
+                        /* we cannot zero the credits assigned to this EP, but to keep
+                         * the credits available for these leftover packets, reduce to
+                         * a minimum */
+                    ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin);
+                }
+            }
+        }
+
+        /* NOTE in the active case, we do not need to do anything further,
+         * when an EP goes active and needs credits, HTC will call into
+         * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS  */
+
+        pCurEpDist = pCurEpDist->pNext;
+    }
+
+}
+
+/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+                        HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+    int                      credits = 0;
+    int                      need;
+
+    do {
+
+        if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
+                /* we never oversubscribe on the control service, this is not
+                 * a high performance path and the target never holds onto control
+                 * credits for too long */
+            break;
+        }
+
+        if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+                (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+                 /* limit VI service from oversubscribing */
+                 /* at least one free credit will not be used by VI */
+                 break;
+            }
+        }
+ 
+        if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
+            if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+                (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+                 /* limit VO service from oversubscribing */
+                 /* at least one free credit will not be used by VO */
+                break;
+            }
+        }
+
+        /* for all other services, we follow a simple algorithm of
+         * 1. checking the free pool for credits
+         * 2. checking lower priority endpoints for credits to take */
+
+            /* give what we can */
+        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+        if (credits >= pEPDist->TxCreditsSeek) {
+                /* we found some to fullfill the seek request */
+            break;
+        }
+
+        /* we don't have enough in the free pool, try taking away from lower priority services
+         *
+         * The rule for taking away credits:
+         *   1. Only take from lower priority endpoints
+         *   2. Only take what is allocated above the minimum (never starve an endpoint completely)
+         *   3. Only take what you need.
+         *
+         * */
+
+            /* starting at the lowest priority */
+        pCurEpDist = pCredInfo->pLowestPriEpDist;
+
+            /* work backwards until we hit the endpoint again */
+        while (pCurEpDist != pEPDist) {
+                /* calculate how many we need so far */
+            need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
+
+            if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) {
+                    /* the current one has been allocated more than it's minimum and it
+                     * has enough credits assigned above it's minimum to fullfill our need
+                     * try to take away just enough to fullfill our need */
+                ReduceCredits(pCredInfo,
+                              pCurEpDist,
+                              pCurEpDist->TxCreditsAssigned - need);
+
+                if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
+                        /* we have enough */
+                    break;
+                }
+            }
+
+            pCurEpDist = pCurEpDist->pPrev;
+        }
+
+            /* return what we can get */
+        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+    } while (FALSE);
+
+        /* did we find some credits? */
+    if (credits) {
+            /* give what we can */
+        GiveCredits(pCredInfo, pEPDist, credits);
+    }
+
+}
+
+/* initialize and setup credit distribution */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
+{
+    HTC_SERVICE_ID servicepriority[5];
+
+    A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
+
+    servicepriority[0] = WMI_CONTROL_SVC;  /* highest */
+    servicepriority[1] = WMI_DATA_VO_SVC;
+    servicepriority[2] = WMI_DATA_VI_SVC;
+    servicepriority[3] = WMI_DATA_BE_SVC;
+    servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
+
+        /* set callbacks and priority list */
+    HTCSetCreditDistribution(HTCHandle,
+                             pCredInfo,
+                             ar6000_credit_distribute,
+                             ar6000_credit_init,
+                             servicepriority,
+                             5);
+
+    return A_OK;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/makefile b/drivers/net/wireless/ath6kl/miscdrv/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h
new file mode 100644
index 000000000000..c72f116dbe04
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+// <copyright file="miscdrv.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _MISCDRV_H
+#define _MISCDRV_H
+
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item)    \
+(((target) == TARGET_TYPE_AR6001) ?     \
+   AR6001_HOST_INTEREST_ITEM_ADDRESS(item) :    \
+   AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+A_UINT32 ar6kRev2Array[][128]   = {
+                                    {0xFFFF, 0xFFFF},      // No Patches
+                               };
+
+#define CFG_REV2_ITEMS                0     // no patches so far
+#define AR6K_RESET_ADDR               0x4000
+#define AR6K_RESET_VAL                0x100
+
+#define EEPROM_SZ                     768
+#define EEPROM_WAIT_LIMIT             4
+
+#endif
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
new file mode 100644
index 000000000000..9d0c3773d4d7
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
@@ -0,0 +1,621 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/vmalloc.h>
+
+#include <linux/fs.h>
+#ifdef CONFIG_PM
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+#include <linux/wakelock.h>
+#endif 
+enum {
+    WLAN_PWR_CTRL_UP = 0,
+    WLAN_PWR_CTRL_CUT_PWR,
+    WLAN_PWR_CTRL_DEEP_SLEEP,
+    WLAN_PWR_CTRL_WOW
+};
+#include <linux/platform_device.h>
+#include <linux/inetdevice.h>
+
+#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0)
+#define MAX_BUF (8*1024)
+
+#ifdef DEBUG
+
+#define  ATH_DEBUG_DBG_LOG       ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+static ATH_DEBUG_MASK_DESCRIPTION android_debug_desc[] = {
+    { ATH_DEBUG_DBG_LOG      , "Android Debug Logs"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(android,
+                                 "android",
+                                 "Android Driver Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_DBG_LOG,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(android_debug_desc),
+                                 android_debug_desc);
+                                 
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+char fwpath[256] = "/lib/firmware/ath6k/AR6102";
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+int buspm = WLAN_PWR_CTRL_CUT_PWR;
+int wow2mode = WLAN_PWR_CTRL_CUT_PWR;
+#define HAVE_WLAN_PWR_IMPL 0 
+#if HAVE_WLAN_PWR_IMPL
+/**   @brief Disable SDIO clock source and mask all interrupt  */
+extern void plat_disable_wlan_slot(void);
+/**   @brief Enable SDIO clock source and unmask all interrupt */
+extern void plat_enable_wlan_slot(void);
+#else
+#define plat_disable_wlan_slot()
+#define plat_enable_wlan_slot()
+#endif 
+
+#endif /* CONFIG_PM */
+extern int bmienable;
+extern int wlaninitmode;
+extern unsigned int wmitimeout;
+extern wait_queue_head_t arEvent;
+extern struct net_device *ar6000_devices[];
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+extern unsigned int testmode;
+#endif
+extern char ifname[];
+
+const char def_ifname[] = "wlan0";
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
+module_param(buspm, int, 0644);
+#else
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(buspm,"i");
+#endif 
+
+struct wake_lock ar6k_init_wake_lock;
+struct wake_lock ar6k_wow_wake_lock;
+static A_STATUS (*ar6000_avail_ev_p)(void *, void *);
+
+extern int ar6000_init(struct net_device *dev);
+extern A_STATUS ar6000_configure_target(AR_SOFTC_T *ar);
+extern void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile);
+extern A_STATUS ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode);
+extern void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+
+static void ar6000_enable_mmchost_detect_change(int enable);
+static void ar6000_restart_endpoint(struct net_device *dev);
+
+#if defined(CONFIG_PM)
+static A_STATUS ar6000_suspend_ev(void *context);
+
+static A_STATUS ar6000_resume_ev(void *context);
+#endif
+
+int android_request_firmware(const struct firmware **firmware_p, const char *name,
+                     struct device *device)
+{
+    struct file *filp = (struct file *)-ENOENT;
+    int ret = 0;
+    mm_segment_t    oldfs;
+    struct firmware *firmware;
+	char filename[2048];
+#if 0 
+    const char *raw_filename = strrchr(name, '/');
+#else
+    const char *raw_filename = NULL;
+#endif 
+	*firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
+    if (!firmware) 
+		return -ENOMEM;
+    if (raw_filename) 
+        ++raw_filename;
+    else
+        raw_filename = name;
+	sprintf(filename, "%s/%s", fwpath, raw_filename);
+    // Open file
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+    do {
+        size_t length, bufsize, bmisize;
+        struct inode    *inode;
+        filp = filp_open(filename, O_RDONLY, S_IRUSR);
+        if (IS_ERR(filp) || !filp->f_op) {
+            printk("%s: file %s filp_open error\n", __FUNCTION__, filename);
+            ret = -1;
+            break;
+        }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+        inode = filp->f_path.dentry->d_inode;
+#else
+        inode = filp->f_dentry->d_inode;
+#endif
+		if (!inode) {
+            printk("%s: Get inode from filp failed\n", __FUNCTION__);
+            ret = -1;
+            break;
+        }
+        length = i_size_read(inode->i_mapping->host);
+	    bufsize = ALIGN(length, PAGE_SIZE);
+        bmisize = A_ROUND_UP(length, 4);
+        bufsize = max(bmisize, bufsize);
+	    firmware->data = vmalloc(bufsize);
+        firmware->size = bmisize;
+        if (!firmware->data) {
+            printk("Cannot allocate buffer for firmware\n");
+            ret = -ENOMEM;
+            break;
+        }
+        if (filp->f_op->read(filp, (char*)firmware->data, length, &filp->f_pos) != length) {
+            printk("%s: file read error, remaining=%d\n", __FUNCTION__, length);
+            ret = -1;
+            break;
+        }        
+    } while (0);
+
+    if (!IS_ERR(filp)) {
+        filp_close(filp, NULL);
+    }
+    set_fs(oldfs);
+
+    if (ret!=0) {
+		if (firmware) {
+            if (firmware->data)
+                vfree(firmware->data);
+            kfree(firmware);
+        }
+        *firmware_p = NULL;
+    }
+    return ret;    
+}
+
+void android_release_firmware(const struct firmware *firmware)
+{
+	if (firmware) {
+        if (firmware->data)
+            vfree(firmware->data);
+        kfree(firmware);
+    }
+}
+
+#if defined(CONFIG_PM)
+static void ar6k_send_asleep_event_to_app(AR_SOFTC_T *ar, A_BOOL asleep)
+{
+    char buf[128];
+    union iwreq_data wrqu;
+
+    snprintf(buf, sizeof(buf), "HOST_ASLEEP=%s", asleep ? "asleep" : "awake");
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = strlen(buf);
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+static void ar6000_wow_resume(AR_SOFTC_T *ar)
+{
+    if (ar->arWowState) {
+        WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {TRUE, FALSE};
+        ar->arWowState = 0;
+        wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode);
+        wmi_scanparams_cmd(ar->arWmi, 0,0,60,0,0,0,0,0,0,0);
+        //wmi_set_keepalive_cmd(ar->arWmi, 0);
+
+#if 1 /* we don't do it if the power consumption is already good enough. */
+        if (wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0) == A_OK) {
+        }
+#endif
+        ar6k_send_asleep_event_to_app(ar, FALSE);
+        if (ar->arTxPending[ar->arControlEp]) {
+            long timeleft = wait_event_interruptible_timeout(arEvent,
+            ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+            if (!timeleft || signal_pending(current)) {
+                printk("Failed to Resume Wow!!!!!!!!!!!!!!!!!!!!\n");
+            } else {
+                printk("Resume WoW successfully\n");
+            }
+        }
+    } else {
+        printk("WoW does not invoked. skip resume");
+    }
+}
+
+static void ar6000_wow_suspend(AR_SOFTC_T *ar)
+{
+#define ANDROID_WOW_LIST_ID 1
+    if (ar->arNetworkType != AP_NETWORK) {
+        /* Setup WoW for unicast & Aarp request for our own IP
+        disable background scan. Set listen interval into 1000 TUs
+        Enable keepliave for 110 seconds
+        */
+        struct in_ifaddr **ifap = NULL;
+        struct in_ifaddr *ifa = NULL;
+        struct in_device *in_dev;
+        A_UINT8 macMask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+        A_STATUS status;
+        WMI_ADD_WOW_PATTERN_CMD addWowCmd = { .filter = { 0 } };
+        WMI_DEL_WOW_PATTERN_CMD delWowCmd;
+        WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {FALSE, TRUE};
+        WMI_SET_WOW_MODE_CMD wowMode = { .enable_wow = TRUE };
+
+        ar6000_TxDataCleanup(ar); /* IMPORTANT, otherwise there will be 11mA after listen interval as 1000*/
+
+#if 1 /* we don't do it if the power consumption is already good enough. */
+        if (wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0) == A_OK) {
+        }
+#endif
+
+//        wmi_set_keepalive_cmd(ar->arWmi, 110); /* keepalive otherwise, we will be disconnected*/
+        status = wmi_scanparams_cmd(ar->arWmi, 0,0,0xffff,0,0,0,0,0,0,0);
+        wmi_set_wow_mode_cmd(ar->arWmi, &wowMode);
+
+        /* clear up our WoW pattern first */
+        delWowCmd.filter_list_id = ANDROID_WOW_LIST_ID;
+        delWowCmd.filter_id = 0;
+        wmi_del_wow_pattern_cmd(ar->arWmi, &delWowCmd);
+
+        /* setup unicast packet pattern for WoW */
+        if (ar->arNetDev->dev_addr[1]) {
+            addWowCmd.filter_list_id = ANDROID_WOW_LIST_ID;
+            addWowCmd.filter_size = 6; /* MAC address */
+            addWowCmd.filter_offset = 2;
+            status = wmi_add_wow_pattern_cmd(ar->arWmi, &addWowCmd, ar->arNetDev->dev_addr, macMask, addWowCmd.filter_size);
+        }
+            /* setup ARP request for our own IP */
+        if ((in_dev = __in_dev_get_rtnl(ar->arNetDev)) != NULL) {
+            for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; ifap = &ifa->ifa_next) {
+                if (!strcmp(ar->arNetDev->name, ifa->ifa_label)) {
+                    break; /* found */
+                }
+            }
+        }
+        if (ifa && ifa->ifa_local) {
+            WMI_SET_IP_CMD ipCmd;
+            memset(&ipCmd, 0, sizeof(ipCmd));
+            ipCmd.ips[0] = ifa->ifa_local;
+            status = wmi_set_ip_cmd(ar->arWmi, &ipCmd);
+        }
+        ar6k_send_asleep_event_to_app(ar, TRUE);
+        wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode);
+        if (ar->arTxPending[ar->arControlEp]) {
+            long timeleft = wait_event_interruptible_timeout(arEvent,
+            ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+            if (!timeleft || signal_pending(current)) {
+               /* what can I do? wow resume at once */
+                printk("Fail to setup WoW\n");
+            } else {
+                ar->arWowState = 1;
+                printk("Setup WoW successfully\n");
+            }
+        }
+        mdelay(10);
+    } else {
+        printk("Not allowed to go to WOW at this moment.\n");
+    }
+}
+
+static void ar6000_pwr_on(AR_SOFTC_T *ar)
+{
+    if (ar == NULL) {
+        /* turn on for all cards */
+    }
+    printk("%s --enter\n", __func__);
+
+}
+
+static void ar6000_pwr_down(AR_SOFTC_T *ar)
+{
+    if (ar == NULL) {
+        /* shutdown for all cards */
+    }
+    printk("%s --enter\n", __func__);
+
+}
+
+static A_STATUS ar6000_suspend_ev(void *context)
+{
+    int pmmode = buspm;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+    printk("%s: enter ar %p devices %p\n", __func__, ar, ar6000_devices[0]? netdev_priv(ar6000_devices[0]) : NULL);
+
+wow_not_connected:
+
+    switch (pmmode) {
+    case WLAN_PWR_CTRL_DEEP_SLEEP:
+        ar6000_set_wlan_state(ar, WLAN_DISABLED);
+        ar->arOsPowerCtrl = WLAN_PWR_CTRL_DEEP_SLEEP;
+        return A_EBUSY;
+    case WLAN_PWR_CTRL_WOW:
+        if (ar->arWmiReady && ar->arWlanState==WLAN_ENABLED && ar->arConnected) {
+            ar->arOsPowerCtrl = WLAN_PWR_CTRL_WOW;
+            /* leave for pm_device to setup wow */
+            return A_EBUSY;
+        } else {
+            pmmode = wow2mode;
+            goto wow_not_connected;
+        }
+        break;
+    case WLAN_PWR_CTRL_CUT_PWR:
+        /* fall through */
+    default:
+        ar->arOsPowerCtrl = WLAN_PWR_CTRL_CUT_PWR;
+        ar6000_stop_endpoint(ar->arNetDev, TRUE);
+        ar->arWlanState = WLAN_DISABLED;
+        break;
+    }
+    return A_OK;
+}
+
+static A_STATUS ar6000_resume_ev(void *context)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+    A_UINT16 powerCtrl = ar->arOsPowerCtrl;
+    wake_lock(&ar6k_init_wake_lock);
+    printk("%s: enter\n", __func__);
+    ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP;
+    switch (powerCtrl) {
+    case WLAN_PWR_CTRL_WOW:
+        printk("Warning! resume but osPowerCtl is not clear\n");
+        break;
+    case WLAN_PWR_CTRL_CUT_PWR:
+        ar6000_restart_endpoint(ar->arNetDev);
+        break;
+    case WLAN_PWR_CTRL_DEEP_SLEEP:
+        ar6000_set_wlan_state(ar, WLAN_ENABLED);
+        break;
+    default:
+        printk("Strange SDIO bus power mode!!\n");
+        break; 
+    }
+    wake_unlock(&ar6k_init_wake_lock);
+    return A_OK;
+}
+
+static A_STATUS ar6000_android_avail_ev(void *context, void *hif_handle)
+{
+	A_STATUS ret;    
+    wake_lock(&ar6k_init_wake_lock);
+	ret = ar6000_avail_ev_p(context, hif_handle);
+    wake_unlock(&ar6k_init_wake_lock);
+    return ret;
+}
+
+
+static int ar6000_pm_suspend(struct platform_device *dev, pm_message_t state)
+{
+    int i;
+    for (i = 0; i < MAX_AR6000; i++) {
+        AR_SOFTC_T *ar;
+
+        if (ar6000_devices[i] == NULL)
+            continue;
+        ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]);
+        printk("%s: enter\n", __func__);
+        switch (ar->arOsPowerCtrl) {
+        case WLAN_PWR_CTRL_CUT_PWR:
+            ar6000_pwr_down(ar);
+            break;
+        case WLAN_PWR_CTRL_WOW:
+            ar6000_wow_suspend(ar);
+            plat_disable_wlan_slot();
+            break;
+        case WLAN_PWR_CTRL_DEEP_SLEEP:
+            /* nothing to do. keep the power on */
+            break;
+        default:
+            printk("Something is strange for ar6000_pm_suspend %d\n", ar->arOsPowerCtrl);
+            break;
+       }
+    }
+    return 0;
+}
+
+static int ar6000_pm_resume(struct platform_device *dev)
+{
+    int i;
+    for (i = 0; i < MAX_AR6000; i++) {
+        AR_SOFTC_T *ar;
+
+        if (ar6000_devices[i] == NULL)
+            continue;
+        printk("%s: enter\n", __func__);
+        ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]);
+        switch (ar->arOsPowerCtrl) {
+        case WLAN_PWR_CTRL_CUT_PWR:
+            ar6000_pwr_on(ar);
+            break;
+        case WLAN_PWR_CTRL_WOW:
+            wake_lock_timeout(&ar6k_wow_wake_lock, 3*HZ);
+            plat_enable_wlan_slot();
+            ar6000_wow_resume(ar);
+            ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP;
+            break;
+        case WLAN_PWR_CTRL_DEEP_SLEEP:
+            /* nothing to do. keep the power on */
+            break;
+        default:
+            printk("Something is strange for ar6000_pm_resume %d\n", ar->arOsPowerCtrl);
+            break;
+       }
+    }
+    return 0;
+}
+
+static int ar6000_pm_probe(struct platform_device *pdev)
+{
+	ar6000_pwr_on(NULL);
+	return 0;
+}
+
+static int ar6000_pm_remove(struct platform_device *pdev)
+{
+	ar6000_pwr_down(NULL);
+	return 0;
+}
+
+static struct platform_driver ar6000_pm_device = {
+	.probe		= ar6000_pm_probe,
+	.remove		= ar6000_pm_remove,
+	.suspend	= ar6000_pm_suspend,
+	.resume		= ar6000_pm_resume,
+	.driver		= {
+			.name = "wlan_ar6000_pm_dev",
+	},
+};
+#endif /* CONFIG_PM */
+
+/* Useful for qualcom platform to detect our wlan card for mmc stack */
+static void ar6000_enable_mmchost_detect_change(int enable)
+{
+#ifdef CONFIG_MMC_MSM 
+    mm_segment_t        oldfs;
+    struct file     *filp = (struct file*)-ENOENT;
+    int         length;
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+    do {
+        char buf[3];
+        filp = filp_open("/sys/devices/platform/msm_sdcc.2/detect_change", O_RDWR, S_IRUSR);
+        if (IS_ERR(filp) || !filp->f_op)
+            break;
+        length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0);
+        if (filp->f_op->write(filp, buf, length, &filp->f_pos) != length) {
+            break;
+        }
+    } while (0);
+    if (!IS_ERR(filp)) {
+        filp_close(filp, NULL);
+    }
+    set_fs(oldfs);
+#endif
+}
+
+static void
+ar6000_restart_endpoint(struct net_device *dev)
+{
+    A_STATUS status = A_OK;
+    AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev);
+    if (down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s(): down_interruptible failed \n", __func__));
+        return ;
+    }
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return;
+    }
+    BMIInit();
+    do {        
+        A_BOOL rtnl_lock_held_on_entry; 
+        if ( (status=ar6000_configure_target(ar))!=A_OK)
+            break;
+		if ( (status=ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+		{
+			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+			break;
+		}     
+        rtnl_lock_held_on_entry = rtnl_trylock();
+        status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+        if (rtnl_lock_held_on_entry) {
+            rtnl_unlock();
+        }
+        if (status!=A_OK) {
+            break;
+        }   
+        ar->arWlanState = WLAN_ENABLED;
+        if (ar->arSsidLen) {
+            ar6000_connect_to_ap(ar);
+        }
+    } while (0);
+
+    up(&ar->arSem);    
+    if (status==A_OK) {
+        return;
+    }
+
+    ar6000_devices[ar->arDeviceIndex] = NULL;
+    ar6000_destroy(ar->arNetDev, 1);
+}
+
+void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks)
+{
+    ar6000_enable_mmchost_detect_change(1);
+    bmienable = 1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+    if (ifname[0] == '\0')
+        strcpy(ifname, def_ifname);
+#endif 
+    if (wow2mode!=WLAN_PWR_CTRL_CUT_PWR && wow2mode!=WLAN_PWR_CTRL_DEEP_SLEEP) {
+        wow2mode=WLAN_PWR_CTRL_CUT_PWR;
+    }
+
+    wake_lock_init(&ar6k_init_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_init");
+    wake_lock_init(&ar6k_wow_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_wow");
+
+#if defined(CONFIG_PM)
+    osdrvCallbacks->deviceSuspendHandler = ar6000_suspend_ev;
+    osdrvCallbacks->deviceResumeHandler = ar6000_resume_ev;
+#endif
+    ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler;
+    osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev;
+
+#if defined(CONFIG_PM)
+    /* Register ar6000_pm_device into system.
+     * We should also add platform_device into the first item of array devices[] in
+     * file arch/xxx/mach-xxx/board-xxxx.c
+     * Otherwise, WoW may not work properly since we may trigger WoW GPIO before system suspend
+     */
+    if (platform_driver_register(&ar6000_pm_device))
+        printk("ar6000: fail to register the power control driver.\n");
+#endif
+}
+
+void android_module_exit(void)
+{
+    wake_lock_destroy(&ar6k_wow_wake_lock);
+    wake_lock_destroy(&ar6k_init_wake_lock);
+
+#ifdef CONFIG_PM
+    platform_driver_unregister(&ar6000_pm_device);
+#endif
+    ar6000_enable_mmchost_detect_change(1);
+}
+
+A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar)
+{
+#ifdef CONFIG_PM
+    return ar->arOsPowerCtrl == WLAN_PWR_CTRL_CUT_PWR;
+#else
+    return FALSE;
+#endif 
+}
+
+void android_ar6k_check_wow_status(AR_SOFTC_T *ar)
+{
+#ifdef CONFIG_PM
+	if (ar->arWowState) {
+		ar6000_wow_resume(ar);
+	}
+#endif /* CONFIG_PM */
+}
+
+A_STATUS android_ar6k_start(AR_SOFTC_T *ar)
+{
+    return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c
new file mode 100644
index 000000000000..33e13064c43f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c
@@ -0,0 +1,6311 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+/*
+ * This driver is a pseudo ethernet driver to access the Atheros AR6000
+ * WLAN Device
+ */
+
+#include "ar6000_drv.h"
+#ifdef ATH6K_CONFIG_CFG80211
+#include "cfg80211.h"
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include "htc.h"
+#include "wmi_filter_linux.h"
+#include "epping_test.h"
+#include "wlan_config.h"
+#include "ar3kconfig.h"
+
+
+/* LINUX_HACK_FUDGE_FACTOR -- this is used to provide a workaround for linux behavior.  When
+ *  the meta data was added to the header it was found that linux did not correctly provide
+ *  enough headroom.  However when more headroom was requested beyond what was truly needed
+ *  Linux gave the requested headroom. Therefore to get the necessary headroom from Linux
+ *  the driver requests more than is needed by the amount = LINUX_HACK_FUDGE_FACTOR */
+#define LINUX_HACK_FUDGE_FACTOR 16
+
+A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+
+#ifdef DEBUG
+
+#define  ATH_DEBUG_DBG_LOG       ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_WLAN_CONNECT  ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_WLAN_SCAN     ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_WLAN_TX       ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_WLAN_RX       ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define  ATH_DEBUG_HTC_RAW       ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+
+static ATH_DEBUG_MASK_DESCRIPTION driver_debug_desc[] = {
+    { ATH_DEBUG_DBG_LOG      , "Target Debug Logs"},
+    { ATH_DEBUG_WLAN_CONNECT , "WLAN connect"},
+    { ATH_DEBUG_WLAN_SCAN    , "WLAN scan"},
+    { ATH_DEBUG_WLAN_TX      , "WLAN Tx"},
+    { ATH_DEBUG_WLAN_RX      , "WLAN Rx"},
+    { ATH_DEBUG_HTC_RAW      , "HTC Raw IF tracing"},
+    { ATH_DEBUG_HCI_BRIDGE   , "HCI Bridge Setup"},
+    { ATH_DEBUG_HCI_RECV     , "HCI Recv tracing"},
+    { ATH_DEBUG_HCI_SEND     , "HCI Send tracing"},
+    { ATH_DEBUG_HCI_DUMP     , "HCI Packet dumps"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(driver,
+                                 "driver",
+                                 "Linux Driver Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_WLAN_SCAN |
+                                 ATH_DEBUG_HCI_BRIDGE,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(driver_debug_desc),
+                                 driver_debug_desc);
+
+#endif
+
+
+#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0)
+#define IS_MAC_BCAST(mac) (*mac==0xff)
+
+MODULE_LICENSE("GPL and additional rights");
+
+#ifndef REORG_APTC_HEURISTICS
+#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#endif /* REORG_APTC_HEURISTICS */
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#define APTC_TRAFFIC_SAMPLING_INTERVAL     100  /* msec */
+#define APTC_UPPER_THROUGHPUT_THRESHOLD    3000 /* Kbps */
+#define APTC_LOWER_THROUGHPUT_THRESHOLD    2000 /* Kbps */
+
+typedef struct aptc_traffic_record {
+    A_BOOL timerScheduled;
+    struct timeval samplingTS;
+    unsigned long bytesReceived;
+    unsigned long bytesTransmitted;
+} APTC_TRAFFIC_RECORD;
+
+A_TIMER aptcTimer;
+APTC_TRAFFIC_RECORD aptcTR;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+// callbacks registered by HCI transport driver
+HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks = { NULL };
+#endif
+
+unsigned int processDot11Hdr = 0;
+int bmienable = BMIENABLE_DEFAULT;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+char ifname[IFNAMSIZ] = "wlan%d";
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+
+int wlaninitmode = WLAN_INIT_MODE_DEFAULT;
+unsigned int bypasswmi = 0;
+unsigned int debuglevel = 0;
+int tspecCompliance = ATHEROS_COMPLIANCE;
+unsigned int busspeedlow = 0;
+unsigned int onebitmode = 0;
+unsigned int skipflash = 0;
+unsigned int wmitimeout = 2;
+unsigned int wlanNodeCaching = 1;
+unsigned int enableuartprint = ENABLEUARTPRINT_DEFAULT;
+unsigned int logWmiRawMsgs = 0;
+unsigned int enabletimerwar = 0;
+unsigned int fwmode = 1;
+unsigned int mbox_yield_limit = 99;
+unsigned int enablerssicompensation = 0;
+int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
+int allow_trace_signal = 0;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+unsigned int testmode =0;
+#endif
+
+unsigned int irqprocmode = HIF_DEVICE_IRQ_SYNC_ONLY;//HIF_DEVICE_IRQ_ASYNC_SYNC;
+unsigned int panic_on_assert = 1;
+unsigned int nohifscattersupport = NOHIFSCATTERSUPPORT_DEFAULT;
+
+unsigned int setuphci = SETUPHCI_DEFAULT;
+unsigned int loghci = 0;
+unsigned int setupbtdev = SETUPBTDEV_DEFAULT;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = AR3KHCIBAUD_DEFAULT;
+unsigned int hciuartscale = HCIUARTSCALE_DEFAULT;
+unsigned int hciuartstep = HCIUARTSTEP_DEFAULT;
+#endif
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+unsigned int csumOffload=0;
+unsigned int csumOffloadTest=0;
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_string(ifname, ifname, sizeof(ifname), 0644);
+module_param(wlaninitmode, int, 0644);
+module_param(bmienable, int, 0644);
+module_param(bypasswmi, uint, 0644);
+module_param(debuglevel, uint, 0644);
+module_param(tspecCompliance, int, 0644);
+module_param(onebitmode, uint, 0644);
+module_param(busspeedlow, uint, 0644);
+module_param(skipflash, uint, 0644);
+module_param(wmitimeout, uint, 0644);
+module_param(wlanNodeCaching, uint, 0644);
+module_param(logWmiRawMsgs, uint, 0644);
+module_param(enableuartprint, uint, 0644);
+module_param(enabletimerwar, uint, 0644);
+module_param(fwmode, uint, 0644);
+module_param(mbox_yield_limit, uint, 0644);
+module_param(reduce_credit_dribble, int, 0644);
+module_param(allow_trace_signal, int, 0644);
+module_param(enablerssicompensation, uint, 0644);
+module_param(processDot11Hdr, uint, 0644);
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+module_param(csumOffload, uint, 0644);
+#endif
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+module_param(testmode, uint, 0644);
+#endif
+module_param(irqprocmode, uint, 0644);
+module_param(nohifscattersupport, uint, 0644);
+module_param(panic_on_assert, uint, 0644);
+module_param(setuphci, uint, 0644);
+module_param(loghci, uint, 0644);
+module_param(setupbtdev, uint, 0644);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+module_param(ar3khcibaud, uint, 0644);
+module_param(hciuartscale, uint, 0644);
+module_param(hciuartstep, uint, 0644);
+#endif
+#else
+
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(bmienable,"i");
+MODULE_PARM(wlaninitmode,"i");
+MODULE_PARM(bypasswmi,"i");
+MODULE_PARM(debuglevel, "i");
+MODULE_PARM(onebitmode,"i");
+MODULE_PARM(busspeedlow, "i");
+MODULE_PARM(skipflash, "i");
+MODULE_PARM(wmitimeout, "i");
+MODULE_PARM(wlanNodeCaching, "i");
+MODULE_PARM(enableuartprint,"i");
+MODULE_PARM(logWmiRawMsgs, "i");
+MODULE_PARM(enabletimerwar,"i");
+MODULE_PARM(fwmode,"i");
+MODULE_PARM(mbox_yield_limit,"i");
+MODULE_PARM(reduce_credit_dribble,"i");
+MODULE_PARM(allow_trace_signal,"i");
+MODULE_PARM(enablerssicompensation,"i");
+MODULE_PARM(processDot11Hdr,"i");
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+MODULE_PARM(csumOffload,"i");
+#endif
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+MODULE_PARM(testmode, "i");
+#endif
+MODULE_PARM(irqprocmode, "i");
+MODULE_PARM(nohifscattersupport, "i");
+MODULE_PARM(panic_on_assert, "i");
+MODULE_PARM(setuphci, "i");
+MODULE_PARM(loghci, "i");
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
+/* in 2.6.10 and later this is now a pointer to a uint */
+unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
+#define mboxnum &_mboxnum
+#else
+unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
+#endif
+
+#ifdef DEBUG
+A_UINT32 g_dbg_flags = DBG_DEFAULTS;
+unsigned int debugflags = 0;
+int debugdriver = 0;
+unsigned int debughtc = 0;
+unsigned int debugbmi = 0;
+unsigned int debughif = 0;
+unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(debugflags, uint, 0644);
+module_param(debugdriver, int, 0644);
+module_param(debughtc, uint, 0644);
+module_param(debugbmi, uint, 0644);
+module_param(debughif, uint, 0644);
+module_param_array(txcreditsavailable, uint, mboxnum, 0644);
+module_param_array(txcreditsconsumed, uint, mboxnum, 0644);
+module_param_array(txcreditintrenable, uint, mboxnum, 0644);
+module_param_array(txcreditintrenableaggregate, uint, mboxnum, 0644);
+#else
+/* linux 2.4 and lower */
+MODULE_PARM(debugflags,"i");
+MODULE_PARM(debugdriver, "i");
+MODULE_PARM(debughtc, "i");
+MODULE_PARM(debugbmi, "i");
+MODULE_PARM(debughif, "i");
+MODULE_PARM(txcreditsavailable, "0-3i");
+MODULE_PARM(txcreditsconsumed, "0-3i");
+MODULE_PARM(txcreditintrenable, "0-3i");
+MODULE_PARM(txcreditintrenableaggregate, "0-3i");
+#endif
+
+#endif /* DEBUG */
+
+unsigned int resetok = 1;
+unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int hifBusRequestNumMax = 40;
+unsigned int war23838_disabled = 0;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+unsigned int enableAPTCHeuristics = 1;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_array(tx_attempt, uint, mboxnum, 0644);
+module_param_array(tx_post, uint, mboxnum, 0644);
+module_param_array(tx_complete, uint, mboxnum, 0644);
+module_param(hifBusRequestNumMax, uint, 0644);
+module_param(war23838_disabled, uint, 0644);
+module_param(resetok, uint, 0644);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+module_param(enableAPTCHeuristics, uint, 0644);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#else
+MODULE_PARM(tx_attempt, "0-3i");
+MODULE_PARM(tx_post, "0-3i");
+MODULE_PARM(tx_complete, "0-3i");
+MODULE_PARM(hifBusRequestNumMax, "i");
+MODULE_PARM(war23838_disabled, "i");
+MODULE_PARM(resetok, "i");
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+MODULE_PARM(enableAPTCHeuristics, "i");
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#endif
+
+#ifdef BLOCK_TX_PATH_FLAG
+int blocktx = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(blocktx, int, 0644);
+#else
+MODULE_PARM(blocktx, "i");
+#endif
+#endif /* BLOCK_TX_PATH_FLAG */
+
+typedef struct user_rssi_compensation_t {
+    A_UINT16         a_enable;
+    A_INT16           a_param_a;
+    A_INT16           a_param_b;
+    A_UINT16         bg_enable;
+    A_INT16           bg_param_a;
+    A_INT16           bg_param_b;
+} USER_RSSI_CPENSATION;
+
+static USER_RSSI_CPENSATION rssi_compensation_param;
+
+static A_INT16 rssi_compensation_table[96];
+
+int reconnect_flag = 0;
+
+/* Function declarations */
+static int ar6000_init_module(void);
+static void ar6000_cleanup_module(void);
+
+int ar6000_init(struct net_device *dev);
+static int ar6000_open(struct net_device *dev);
+static int ar6000_close(struct net_device *dev);
+static void ar6000_init_control_info(AR_SOFTC_T *ar);
+static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+static void ar6000_detect_error(unsigned long ptr);
+static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
+static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
+
+static void disconnect_timer_handler(unsigned long ptr);
+
+void read_rssi_compensation_param(AR_SOFTC_T *ar);
+
+    /* for android builds we call external APIs that handle firmware download and configuration */
+#ifdef ANDROID_ENV
+/* !!!! Interim android support to make it easier to patch the default driver for
+ * android use. You must define an external source file ar6000_android.c that handles the following
+ * APIs */
+extern A_STATUS android_ar6k_start(AR_SOFTC_T *ar);
+extern void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks);
+extern void android_module_exit(void);
+extern A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar);
+extern void android_ar6k_check_wow_status(AR_SOFTC_T *ar);
+#endif
+/*
+ * HTC service connection handlers
+ */
+static A_STATUS ar6000_avail_ev(void *context, void *hif_handle);
+
+static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle);
+
+A_STATUS ar6000_configure_target(AR_SOFTC_T *ar);
+
+void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile);
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status);
+
+static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
+
+static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
+
+static void ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPackets);
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket);
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+#endif
+static void ar6000_deliver_frames_to_nw_stack(void * dev, void *osbuf);
+//static void ar6000_deliver_frames_to_bt_stack(void * dev, void *osbuf);
+
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length);
+
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count);
+
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar);
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr,
+                      char *buf, loff_t pos, size_t count);
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr,
+                       char *buf, loff_t pos, size_t count);
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar);
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar);
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode);
+
+/*
+ * Static variables
+ */
+
+struct net_device *ar6000_devices[MAX_AR6000];
+extern struct iw_handler_def ath_iw_handler_def;
+DECLARE_WAIT_QUEUE_HEAD(arEvent);
+static void ar6000_cookie_init(AR_SOFTC_T *ar);
+static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
+static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
+static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
+
+#ifdef USER_KEYS
+static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
+#endif
+
+
+static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
+
+#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \
+        (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+        (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+static struct net_device_ops ar6000_netdev_ops = {
+    .ndo_init               = NULL,
+    .ndo_open               = ar6000_open,
+    .ndo_stop               = ar6000_close,
+    .ndo_get_stats          = ar6000_get_stats,
+    .ndo_do_ioctl           = ar6000_ioctl,
+    .ndo_start_xmit         = ar6000_data_tx,
+};
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) */
+
+/* Debug log support */
+
+/*
+ * Flag to govern whether the debug logs should be parsed in the kernel
+ * or reported to the application.
+ */
+#define REPORT_DEBUG_LOGS_TO_APP
+
+A_STATUS
+ar6000_set_host_app_area(AR_SOFTC_T *ar)
+{
+    A_UINT32 address, data;
+    struct host_app_area_s host_app_area;
+
+    /* Fetch the address of the host_app_area_s instance in the host interest area */
+    address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest));
+    if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
+        return A_ERROR;
+    }
+    address = TARG_VTOP(ar->arTargetType, data);
+    host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
+    if (ar6000_WriteDataDiag(ar->arHifDevice, address,
+                             (A_UCHAR *)&host_app_area,
+                             sizeof(struct host_app_area_s)) != A_OK)
+    {
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+A_UINT32
+dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
+{
+    A_UINT32 param;
+    A_UINT32 address;
+    A_STATUS status;
+
+    address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr));
+    if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                      (A_UCHAR *)&param, 4)) != A_OK)
+    {
+        param = 0;
+    }
+
+    return param;
+}
+
+/*
+ * The dbglog module has been initialized. Its ok to access the relevant
+ * data stuctures over the diagnostic window.
+ */
+void
+ar6000_dbglog_init_done(AR_SOFTC_T *ar)
+{
+    ar->dbglog_init_done = TRUE;
+}
+
+A_UINT32
+dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
+{
+    A_INT32 *buffer;
+    A_UINT32 count;
+    A_UINT32 numargs;
+    A_UINT32 length;
+    A_UINT32 fraglen;
+
+    count = fraglen = 0;
+    buffer = (A_INT32 *)datap;
+    length = (limit >> 2);
+
+    if (len <= limit) {
+        fraglen = len;
+    } else {
+        while (count < length) {
+            numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+            fraglen = (count << 2);
+            count += numargs + 1;
+        }
+    }
+
+    return fraglen;
+}
+
+void
+dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
+{
+    A_INT32 *buffer;
+    A_UINT32 count;
+    A_UINT32 timestamp;
+    A_UINT32 debugid;
+    A_UINT32 moduleid;
+    A_UINT32 numargs;
+    A_UINT32 length;
+
+    count = 0;
+    buffer = (A_INT32 *)datap;
+    length = (len >> 2);
+    while (count < length) {
+        debugid = DBGLOG_GET_DBGID(buffer[count]);
+        moduleid = DBGLOG_GET_MODULEID(buffer[count]);
+        numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+        timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
+        switch (numargs) {
+            case 0:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d)\n", moduleid, debugid, timestamp));
+            break;
+
+            case 1:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x\n", moduleid, debugid,
+                            timestamp, buffer[count+1]));
+            break;
+
+            case 2:
+            AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
+                            timestamp, buffer[count+1], buffer[count+2]));
+            break;
+
+            default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid args: %d\n", numargs));
+        }
+        count += numargs + 1;
+    }
+}
+
+int
+ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
+{
+    struct dbglog_hdr_s debug_hdr;
+    struct dbglog_buf_s debug_buf;
+    A_UINT32 address;
+    A_UINT32 length;
+    A_UINT32 dropped;
+    A_UINT32 firstbuf;
+    A_UINT32 debug_hdr_ptr;
+
+    if (!ar->dbglog_init_done) return A_ERROR;
+
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (ar->dbgLogFetchInProgress) {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        return A_EBUSY;
+    }
+
+        /* block out others */
+    ar->dbgLogFetchInProgress = TRUE;
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
+    printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
+
+    /* Get the contents of the ring buffer */
+    if (debug_hdr_ptr) {
+        address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr);
+        length = sizeof(struct dbglog_hdr_s);
+        ar6000_ReadDataDiag(ar->arHifDevice, address,
+                            (A_UCHAR *)&debug_hdr, length);
+        address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf);
+        firstbuf = address;
+        dropped = debug_hdr.dropped;
+        length = sizeof(struct dbglog_buf_s);
+        ar6000_ReadDataDiag(ar->arHifDevice, address,
+                            (A_UCHAR *)&debug_buf, length);
+
+        do {
+            address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer);
+            length = debug_buf.length;
+            if ((length) && (debug_buf.length <= debug_buf.bufsize)) {
+                /* Rewind the index if it is about to overrun the buffer */
+                if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
+                    ar->log_cnt = 0;
+                }
+                if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                    (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
+                {
+                    break;
+                }
+                ar6000_dbglog_event(ar, dropped, (A_INT8*)&ar->log_buffer[ar->log_cnt], length);
+                ar->log_cnt += length;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("Length: %d (Total size: %d)\n",
+                                debug_buf.length, debug_buf.bufsize));
+            }
+
+            address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next);
+            length = sizeof(struct dbglog_buf_s);
+            if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+                                (A_UCHAR *)&debug_buf, length))
+            {
+                break;
+            }
+
+        } while (address != firstbuf);
+    }
+
+    ar->dbgLogFetchInProgress = FALSE;
+
+    return A_OK;
+}
+
+void
+ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
+                    A_INT8 *buffer, A_UINT32 length)
+{
+#ifdef REPORT_DEBUG_LOGS_TO_APP
+    #define MAX_WIRELESS_EVENT_SIZE 252
+    /*
+     * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
+     * There seems to be a limitation on the length of message that could be
+     * transmitted to the user app via this mechanism.
+     */
+    A_UINT32 send, sent;
+
+    sent = 0;
+    send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+                                     MAX_WIRELESS_EVENT_SIZE);
+    while (send) {
+        ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, (A_UINT8*)&buffer[sent], send);
+        sent += send;
+        send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+                                         MAX_WIRELESS_EVENT_SIZE);
+    }
+#else
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Dropped logs: 0x%x\nDebug info length: %d\n",
+                    dropped, length));
+
+    /* Interpret the debug logs */
+    dbglog_parse_debug_logs((A_INT8*)buffer, length);
+#endif /* REPORT_DEBUG_LOGS_TO_APP */
+}
+
+
+static int __init
+ar6000_init_module(void)
+{
+    static int probed = 0;
+    A_STATUS status;
+    OSDRV_CALLBACKS osdrvCallbacks;
+
+    a_module_debug_support_init();
+
+#ifdef DEBUG
+        /* check for debug mask overrides */
+    if (debughtc != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(htc,debughtc);
+    }
+    if (debugbmi != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(bmi,debugbmi);
+    }
+    if (debughif != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(hif,debughif);
+    }
+    if (debugdriver != 0) {
+        ATH_DEBUG_SET_DEBUG_MASK(driver,debugdriver);
+    }
+
+#endif
+
+    A_REGISTER_MODULE_DEBUG_INFO(driver);
+
+    A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks));
+    osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev;
+    osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev;
+
+#ifdef ANDROID_ENV
+    android_module_init(&osdrvCallbacks);
+#endif
+
+#ifdef DEBUG
+    /* Set the debug flags if specified at load time */
+    if(debugflags != 0)
+    {
+        g_dbg_flags = debugflags;
+    }
+#endif
+
+    if (probed) {
+        return -ENODEV;
+    }
+    probed++;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+    ar6000_gpio_init();
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+    status = HIFInit(&osdrvCallbacks);
+    if(status != A_OK)
+        return -ENODEV;
+
+    return 0;
+}
+
+static void __exit
+ar6000_cleanup_module(void)
+{
+    int i = 0;
+    struct net_device *ar6000_netdev;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    /* Delete the Adaptive Power Control timer */
+    if (timer_pending(&aptcTimer)) {
+        del_timer_sync(&aptcTimer);
+    }
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+    for (i=0; i < MAX_AR6000; i++) {
+        if (ar6000_devices[i] != NULL) {
+            ar6000_netdev = ar6000_devices[i];
+            ar6000_devices[i] = NULL;
+            ar6000_destroy(ar6000_netdev, 1);
+        }
+    }
+
+    HIFShutDownDevice(NULL);
+
+    a_module_debug_support_cleanup();
+
+#ifdef ANDROID_ENV    
+    android_module_exit();
+#endif
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_cleanup: success\n"));
+}
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+void
+aptcTimerHandler(unsigned long arg)
+{
+    A_UINT32 numbytes;
+    A_UINT32 throughput;
+    AR_SOFTC_T *ar;
+    A_STATUS status;
+
+    ar = (AR_SOFTC_T *)arg;
+    A_ASSERT(ar != NULL);
+    A_ASSERT(!timer_pending(&aptcTimer));
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    /* Get the number of bytes transferred */
+    numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+    aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+
+    /* Calculate and decide based on throughput thresholds */
+    throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
+    if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
+        /* Enable Sleep and delete the timer */
+        A_ASSERT(ar->arWmiReady == TRUE);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        A_ASSERT(status == A_OK);
+        aptcTR.timerScheduled = FALSE;
+    } else {
+        A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void
+ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num)
+{
+    void * osbuf;
+
+    while(num) {
+        if((osbuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE))) {
+            A_NETBUF_ENQUEUE(q, osbuf);
+        } else {
+            break;
+        }
+        num--;
+    }
+
+    if(num) {
+        A_PRINTF("%s(), allocation of netbuf failed", __func__);
+    }
+}
+#endif
+
+static struct bin_attribute bmi_attr = {
+    .attr = {.name = "bmi", .mode = 0600},
+    .read = ar6000_sysfs_bmi_read,
+    .write = ar6000_sysfs_bmi_write,
+};
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr,
+                      char *buf, loff_t pos, size_t count)
+{
+    int index;
+    AR_SOFTC_T *ar;
+    HIF_DEVICE_OS_DEVICE_INFO   *osDevInfo;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Read %d bytes\n", count));
+    for (index=0; index < MAX_AR6000; index++) {
+        ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+        osDevInfo = &ar->osDevInfo;
+        if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+            break;
+        }
+    }
+
+    if (index == MAX_AR6000) return 0;
+
+    if ((BMIRawRead(ar->arHifDevice, (A_UCHAR*)buf, count, TRUE)) != A_OK) {
+        return 0;
+    }
+
+    return count;
+}
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr,
+                       char *buf, loff_t pos, size_t count)
+{
+    int index;
+    AR_SOFTC_T *ar;
+    HIF_DEVICE_OS_DEVICE_INFO   *osDevInfo;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Write %d bytes\n", count));
+    for (index=0; index < MAX_AR6000; index++) {
+        ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+        osDevInfo = &ar->osDevInfo;
+        if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+            break;
+        }
+    }
+
+    if (index == MAX_AR6000) return 0;
+
+    if ((BMIRawWrite(ar->arHifDevice, (A_UCHAR*)buf, count)) != A_OK) {
+        return 0;
+    }
+
+    return count;
+}
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar)
+{
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Creating sysfs entry\n"));
+    A_MEMZERO(&ar->osDevInfo, sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+    /* Get the underlying OS device */
+    status = HIFConfigureDevice(ar->arHifDevice,
+                                HIF_DEVICE_GET_OS_DEVICE,
+                                &ar->osDevInfo,
+                                sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failed to get OS device info from HIF\n"));
+        return A_ERROR;
+    }
+
+    /* Create a bmi entry in the sysfs filesystem */
+    if ((sysfs_create_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr)) < 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to create entry for bmi in sysfs filesystem\n"));
+        return A_ERROR;
+    }
+
+    return A_OK;
+}
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Deleting sysfs entry\n"));
+
+    sysfs_remove_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr);
+}
+
+#define bmifn(fn) do { \
+    if ((fn) < A_OK) { \
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__)); \
+        return A_ERROR; \
+    } \
+} while(0)
+
+#ifdef INIT_MODE_DRV_ENABLED
+
+#ifdef SOFTMAC_FILE_USED
+#define AR6001_MAC_ADDRESS_OFFSET     0x06
+#define AR6002_MAC_ADDRESS_OFFSET     0x0A
+#define AR6003_MAC_ADDRESS_OFFSET     0x16
+static
+void calculate_crc(A_UINT32 TargetType, A_UCHAR *eeprom_data)
+{
+    A_UINT16        *ptr_crc;
+    A_UINT16        *ptr16_eeprom;
+    A_UINT16        checksum;
+    A_UINT32        i;
+    A_UINT32        eeprom_size;
+
+    if (TargetType == TARGET_TYPE_AR6001)
+    {
+        eeprom_size = 512;
+        ptr_crc = (A_UINT16 *)eeprom_data;
+    }
+    else if (TargetType == TARGET_TYPE_AR6003)
+    {
+        eeprom_size = 1024;
+        ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+    }
+    else
+    {
+        eeprom_size = 768;
+        ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+    }
+
+
+    // Clear the crc
+    *ptr_crc = 0;
+
+    // Recalculate new CRC
+    checksum = 0;
+    ptr16_eeprom = (A_UINT16 *)eeprom_data;
+    for (i = 0;i < eeprom_size; i += 2)
+    {
+        checksum = checksum ^ (*ptr16_eeprom);
+        ptr16_eeprom++;
+    }
+    checksum = 0xFFFF ^ checksum;
+    *ptr_crc = checksum;
+}
+
+static void 
+ar6000_softmac_update(AR_SOFTC_T *ar, A_UCHAR *eeprom_data, size_t size)
+{
+    const char *source = "random generated";
+    const struct firmware *softmac_entry;
+    A_UCHAR *ptr_mac;
+    switch (ar->arTargetType) {
+    case TARGET_TYPE_AR6001:
+        ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6001_MAC_ADDRESS_OFFSET);
+        break;
+    case TARGET_TYPE_AR6002:
+        ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6002_MAC_ADDRESS_OFFSET);
+        break;
+    case TARGET_TYPE_AR6003:
+        ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6003_MAC_ADDRESS_OFFSET);
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Target Type \n"));
+        return;
+    }
+    printk("MAC from EEPROM %02X:%02X:%02X:%02X:%02X:%02X\n", 
+            ptr_mac[0], ptr_mac[1], ptr_mac[2], 
+            ptr_mac[3], ptr_mac[4], ptr_mac[5]); 
+
+    /* create a random MAC in case we cannot read file from system */
+    ptr_mac[0] = 0;
+    ptr_mac[1] = 0x03;
+    ptr_mac[2] = 0x7F;
+    ptr_mac[3] = random32() & 0xff; 
+    ptr_mac[4] = random32() & 0xff; 
+    ptr_mac[5] = random32() & 0xff; 
+    if ((A_REQUEST_FIRMWARE(&softmac_entry, "softmac", ((struct device *)ar->osDevInfo.pOSDevice))) == 0)
+    {
+        A_CHAR *macbuf = A_MALLOC_NOWAIT(softmac_entry->size+1);
+        if (macbuf) {            
+            unsigned int softmac[6];
+            memcpy(macbuf, softmac_entry->data, softmac_entry->size);
+            macbuf[softmac_entry->size] = '\0';
+            if (sscanf(macbuf, "%02x:%02x:%02x:%02x:%02x:%02x", 
+                        &softmac[0], &softmac[1], &softmac[2],
+                        &softmac[3], &softmac[4], &softmac[5])==6) {
+                int i;
+                for (i=0; i<6; ++i) {
+                    ptr_mac[i] = softmac[i] & 0xff;
+                }
+                source = "softmac file";
+            }
+            A_FREE(macbuf);
+        }
+        A_RELEASE_FIRMWARE(softmac_entry);
+    }
+    printk("MAC from %s %02X:%02X:%02X:%02X:%02X:%02X\n", source,
+            ptr_mac[0], ptr_mac[1], ptr_mac[2], 
+            ptr_mac[3], ptr_mac[4], ptr_mac[5]); 
+   calculate_crc(ar->arTargetType, eeprom_data);
+}
+#endif /* SOFTMAC_FILE_USED */
+
+static A_STATUS
+ar6000_transfer_bin_file(AR_SOFTC_T *ar, AR6K_BIN_FILE file, A_UINT32 address, A_BOOL compressed)
+{
+    A_STATUS status;
+    const char *filename;
+    const struct firmware *fw_entry;
+
+    switch (file) {
+        case AR6K_OTP_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_OTP_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_OTP_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        case AR6K_FIRMWARE_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_FIRMWARE_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_FIRMWARE_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+            if(testmode) {
+                if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                    filename = AR6003_REV1_TCMD_FIRMWARE_FILE;
+                } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                    filename = AR6003_REV2_TCMD_FIRMWARE_FILE;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                    return A_ERROR;
+                }
+                compressed = 0;
+            }
+#endif 
+#ifdef HTC_RAW_INTERFACE
+            if (bypasswmi) {
+                if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                    filename = AR6003_REV1_ART_FIRMWARE_FILE;
+                } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                    filename = AR6003_REV2_ART_FIRMWARE_FILE;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                    return A_ERROR;
+                }
+                compressed = 0;                
+            }
+#endif 
+            break;
+
+        case AR6K_PATCH_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_PATCH_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_PATCH_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        case AR6K_BOARD_DATA_FILE:
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                filename = AR6003_REV1_BOARD_DATA_FILE;
+            } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+                filename = AR6003_REV2_BOARD_DATA_FILE;
+            } else {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+                return A_ERROR;
+            }
+            break;
+
+        default:
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown file type: %d\n", file));
+            return A_ERROR;
+    }
+    if ((A_REQUEST_FIRMWARE(&fw_entry, filename, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to get %s\n", filename));
+        return A_ENOENT;
+    }
+
+#ifdef SOFTMAC_FILE_USED
+    if (file==AR6K_BOARD_DATA_FILE && fw_entry->data) {
+        ar6000_softmac_update(ar, (A_UCHAR *)fw_entry->data, fw_entry->size);
+    }
+#endif 
+
+    if (compressed) {
+        status = BMIFastDownload(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size);
+    } else {
+        status = BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size);
+    }
+
+    if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__));
+        A_RELEASE_FIRMWARE(fw_entry);
+        return A_ERROR;
+    }
+    A_RELEASE_FIRMWARE(fw_entry);
+    return A_OK;
+}
+#endif /* INIT_MODE_DRV_ENABLED */
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Requesting device specific configuration\n"));
+
+    if (mode == WLAN_INIT_MODE_UDEV) {
+        A_CHAR version[16];
+        const struct firmware *fw_entry;
+
+        /* Get config using udev through a script in user space */
+        sprintf(version, "%2.2x", ar->arVersion.target_ver);
+        if ((A_REQUEST_FIRMWARE(&fw_entry, version, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failure to get configuration for target version: %s\n", version));
+            return A_ERROR;
+        }
+
+        A_RELEASE_FIRMWARE(fw_entry);
+#ifdef INIT_MODE_DRV_ENABLED
+    } else {
+        /* The config is contained within the driver itself */
+        A_STATUS status;
+        A_UINT32 param, options, sleep, address;
+
+        /* Temporarily disable system sleep */
+        address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+        bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+        options = param;
+        param |= AR6K_OPTION_SLEEP_DISABLE;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+        bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+        sleep = param;
+        param |= WLAN_SYSTEM_SLEEP_DISABLE_SET(1);
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("old options: %d, old sleep: %d\n", options, sleep));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Run at 80/88MHz by default */
+            param = CPU_CLOCK_STANDARD_SET(1);
+        } else {
+            /* Run at 40/44MHz by default */
+            param = CPU_CLOCK_STANDARD_SET(0);
+        }
+        address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        param = 0;
+        if (ar->arTargetType == TARGET_TYPE_AR6002) {
+            bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+        }
+
+        /* LPO_CAL.ENABLE = 1 if no external clk is detected */
+        if (param != 1) {
+            address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
+            param = LPO_CAL_ENABLE_SET(1);
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+
+        /* Venus2.0: Lower SDIO pad drive strength,
+         * temporary WAR to avoid SDIO CRC error */
+        if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6K: Temporary WAR to avoid SDIO CRC error\n"));
+            param = 0x20;
+            address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+            address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+
+#ifdef FORCE_INTERNAL_CLOCK
+        /* Ignore external clock, if any, and force use of internal clock */
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* hi_ext_clk_detected = 0 */
+            param = 0;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+
+            /* CLOCK_CONTROL &= ~LF_CLK32 */
+            address = RTC_BASE_ADDRESS + CLOCK_CONTROL_ADDRESS;
+            bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+            param &= (~CLOCK_CONTROL_LF_CLK32_SET(1));
+            bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+        }
+#endif /* FORCE_INTERNAL_CLOCK */
+
+        /* Transfer Board Data from Target EEPROM to Target RAM */
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Determine where in Target RAM to write Board Data */
+            bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), (A_UCHAR *)&address, 4));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Board Data download address: 0x%x\n", address));
+
+            /* Write EEPROM data to Target RAM */
+            if ((ar6000_transfer_bin_file(ar, AR6K_BOARD_DATA_FILE, address, FALSE)) != A_OK) {
+                return A_ERROR;
+            }
+
+            /* Record the fact that Board Data IS initialized */
+            param = 1;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), (A_UCHAR *)&param, 4));
+
+            /* Transfer One time Programmable data */
+            AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+            status = ar6000_transfer_bin_file(ar, AR6K_OTP_FILE, address, TRUE);
+            if (status == A_OK) {
+                /* Execute the OTP code */
+                param = 0;
+                AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+                bmifn(BMIExecute(ar->arHifDevice, address, &param));
+            } else if (status != A_ENOENT) {
+                return A_ERROR;
+            } 
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Programming of board data for chip %d not supported\n", ar->arTargetType));
+            return A_ERROR;
+        }
+
+        /* Download Target firmware */
+        AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+        if ((ar6000_transfer_bin_file(ar, AR6K_FIRMWARE_FILE, address, TRUE)) != A_OK) {
+            return A_ERROR;
+        }
+
+        /* Set starting address for firmware */
+        AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+        bmifn(BMISetAppStart(ar->arHifDevice, address));
+
+        /* Apply the patches */
+        AR6K_PATCH_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+        if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE, address, FALSE)) != A_OK) {
+            return A_ERROR;
+        }
+
+        param = address;
+        bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head), (A_UCHAR *)&param, 4));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+                /* Reserve 5.5K of RAM */
+                param = 5632;
+            } else { /* AR6003_REV2_VERSION */
+                /* Reserve 6K of RAM */
+                param = 6144;
+            }
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), (A_UCHAR *)&param, 4));
+        }
+
+        /* Restore system sleep */
+        address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, sleep));
+
+        address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+        param = options | 0x20;
+        bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+        if (ar->arTargetType == TARGET_TYPE_AR6003) {
+            /* Configure GPIO AR6003 UART */
+#ifndef CONFIG_AR600x_DEBUG_UART_TX_PIN
+#define CONFIG_AR600x_DEBUG_UART_TX_PIN 8
+#endif
+            param = CONFIG_AR600x_DEBUG_UART_TX_PIN;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbg_uart_txpin), (A_UCHAR *)&param, 4));
+
+#if (CONFIG_AR600x_DEBUG_UART_TX_PIN == 23)
+            {
+                address = GPIO_BASE_ADDRESS + CLOCK_GPIO_ADDRESS;
+                bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+                param |= CLOCK_GPIO_BT_CLK_OUT_EN_SET(1);
+                bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+            }
+#endif
+
+            /* Configure GPIO for BT Reset */
+#ifdef ATH6KL_CONFIG_GPIO_BT_RESET
+            param = CONFIG_AR600x_BT_RESET_PIN;
+            bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_hci_uart_support_pins), (A_UCHAR *)&param, 4));
+#endif /* ATH6KL_CONFIG_GPIO_BT_RESET */
+        }
+#ifdef HTC_RAW_INTERFACE
+        if (bypasswmi) {
+            /* Don't run BMIDone for ART mode and force resetok=0 */
+            resetok = 0;
+            msleep(1000);
+            return A_OK;
+        }
+#endif /* HTC_RAW_INTERFACE */
+        /* Tell Target to execute loaded firmware */
+        bmifn(BMIDone(ar->arHifDevice));
+#endif /* INIT_MODE_DRV_ENABLED */
+    }
+
+    return A_OK;
+}
+
+A_STATUS
+ar6000_configure_target(AR_SOFTC_T *ar)
+{
+    A_UINT32 param;
+    if (enableuartprint) {
+        param = 1;
+        if (BMIWriteMemory(ar->arHifDevice,
+                           HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
+                           (A_UCHAR *)&param,
+                           4)!= A_OK)
+        {
+             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enableuartprint failed \n"));
+             return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Serial console prints enabled\n"));
+    }
+
+    /* Tell target which HTC version it is used*/
+    param = HTC_PROTOCOL_VERSION;
+    if (BMIWriteMemory(ar->arHifDevice,
+                       HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest),
+                       (A_UCHAR *)&param,
+                       4)!= A_OK)
+    {
+         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for htc version failed \n"));
+         return A_ERROR;
+    }
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    if(testmode) {
+        ar->arTargetMode = AR6000_TCMD_MODE;
+    }else {
+        ar->arTargetMode = AR6000_WLAN_MODE;
+    }
+#endif
+    if (enabletimerwar) {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for enabletimerwar failed \n"));
+            return A_ERROR;
+        }
+
+        param |= HI_OPTION_TIMER_WAR;
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enabletimerwar failed \n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Timer WAR enabled\n"));
+    }
+
+    /* set the firmware mode to STA/IBSS/AP */
+    {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for setting fwmode failed \n"));
+            return A_ERROR;
+        }
+
+        param |= (fwmode << HI_OPTION_FW_MODE_SHIFT);
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for setting fwmode failed \n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+    }
+#if 0 /* HOST_INTEREST is no longer used to configure dot11 processing rule */
+    if (processDot11Hdr) {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for processDot11Hdr failed \n"));
+            return A_ERROR;
+        }
+
+        param |= HI_OPTION_RELAY_DOT11_HDR;
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for processDot11Hdr failed \n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("processDot11Hdr enabled\n"));
+    }
+#endif
+
+#ifdef ATH6KL_DISABLE_TARGET_DBGLOGS
+    {
+        A_UINT32 param;
+
+        if (BMIReadMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4)!= A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for disabling debug logs failed\n"));
+            return A_ERROR;
+        }
+
+        param |= HI_OPTION_DISABLE_DBGLOG;
+
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for HI_OPTION_DISABLE_DBGLOG\n"));
+            return A_ERROR;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+    }
+#endif /* ATH6KL_DISABLE_TARGET_DBGLOGS */
+
+    // No need to reserve RAM space for patch as AR6001 is flash based
+    if (ar->arTargetType == TARGET_TYPE_AR6001) {
+        param = 0;
+        if (BMIWriteMemory(ar->arHifDevice,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz),
+            (A_UCHAR *)&param,
+            4) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"));
+            return A_ERROR;
+        }
+    }
+
+
+        /* since BMIInit is called in the driver layer, we have to set the block
+         * size here for the target */
+
+    if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice,
+                                       ar->arTargetType,
+                                       mbox_yield_limit,
+                                       0 /* use default number of control buffers */
+                                       ))) {
+        return A_ERROR;
+    }
+
+    if (setupbtdev != 0) {
+        if (A_FAILED(ar6000_set_hci_bridge_flags(ar->arHifDevice,
+                                                 ar->arTargetType,
+                                                 setupbtdev))) {
+            return A_ERROR;
+        }
+    }
+    return A_OK;
+}
+
+/*
+ * HTC Event handlers
+ */
+static A_STATUS
+ar6000_avail_ev(void *context, void *hif_handle)
+{
+    int i;
+    struct net_device *dev;
+    void *ar_netif;
+    AR_SOFTC_T *ar;
+    int device_index = 0;
+    HTC_INIT_INFO  htcInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+    struct wireless_dev *wdev;
+#endif /* ATH6K_CONFIG_CFG80211 */
+    A_STATUS init_status = A_OK;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_available\n"));
+
+    for (i=0; i < MAX_AR6000; i++) {
+        if (ar6000_devices[i] == NULL) {
+            break;
+        }
+    }
+
+    if (i == MAX_AR6000) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: max devices reached\n"));
+        return A_ERROR;
+    }
+
+    /* Save this. It gives a bit better readability especially since */
+    /* we use another local "i" variable below.                      */
+    device_index = i;
+
+#ifdef ATH6K_CONFIG_CFG80211
+    wdev = ar6k_cfg80211_init(NULL);
+    if (IS_ERR(wdev)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ar6k_cfg80211_init failed\n", __func__));
+        return A_ERROR;
+    }
+    ar_netif = wdev_priv(wdev);
+#else
+    dev = alloc_etherdev(sizeof(AR_SOFTC_T));
+    if (dev == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: can't alloc etherdev\n"));
+        return A_ERROR;
+    }
+    ether_setup(dev);
+    ar_netif = ar6k_priv(dev);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if (ar_netif == NULL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Can't allocate ar6k priv memory\n", __func__));
+        return A_ERROR;
+    }
+
+    A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T));
+    ar = (AR_SOFTC_T *)ar_netif;
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar->wdev = wdev;
+    wdev->iftype = NL80211_IFTYPE_STATION;
+
+    dev = alloc_netdev_mq(0, "wlan%d", ether_setup, 1);
+    if (!dev) {
+        printk(KERN_CRIT "AR6K: no memory for network device instance\n");
+        ar6k_cfg80211_deinit(ar);
+        return A_ERROR;
+    }
+
+    dev->ieee80211_ptr = wdev;
+    SET_NETDEV_DEV(dev, wiphy_dev(wdev->wiphy));
+    wdev->netdev = dev;
+    ar->arNetworkType = INFRA_NETWORK;
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+    if (ifname[0])
+    {
+        strcpy(dev->name, ifname);
+    }
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+
+#ifdef SET_MODULE_OWNER
+    SET_MODULE_OWNER(dev);
+#endif
+
+#ifdef SET_NETDEV_DEV
+    if (ar_netif) { 
+        HIF_DEVICE_OS_DEVICE_INFO osDevInfo;
+        A_MEMZERO(&osDevInfo, sizeof(osDevInfo));
+        if ( A_SUCCESS( HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_OS_DEVICE,
+                        &osDevInfo, sizeof(osDevInfo))) ) {
+            SET_NETDEV_DEV(dev, osDevInfo.pOSDevice);
+        }
+    }
+#endif 
+
+    ar->arNetDev             = dev;
+    ar->arHifDevice          = hif_handle;
+    ar->arWlanState          = WLAN_ENABLED;
+    ar->arDeviceIndex        = device_index;
+
+    A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
+    ar->arHBChallengeResp.seqNum = 0;
+    ar->arHBChallengeResp.outstanding = FALSE;
+    ar->arHBChallengeResp.missCnt = 0;
+    ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
+    ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
+
+    ar6000_init_control_info(ar);
+    init_waitqueue_head(&arEvent);
+    sema_init(&ar->arSem, 1);
+    ar->bIsDestroyProgress = FALSE;
+
+    INIT_HTC_PACKET_QUEUE(&ar->amsdu_rx_buffer_queue);
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+    A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+    A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev);
+
+    /*
+     * If requested, perform some magic which requires no cooperation from
+     * the Target.  It causes the Target to ignore flash and execute to the
+     * OS from ROM.
+     *
+     * This is intended to support recovery from a corrupted flash on Targets
+     * that support flash.
+     */
+    if (skipflash)
+    {
+        //ar6000_reset_device_skipflash(ar->arHifDevice);
+    }
+
+    BMIInit();
+
+    if (bmienable) {
+        ar6000_sysfs_bmi_init(ar);
+    }
+
+    {
+        struct bmi_target_info targ_info;
+
+        if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+        }
+
+        ar->arVersion.target_ver = targ_info.target_ver;
+        ar->arTargetType = targ_info.target_type;
+
+            /* do any target-specific preparation that can be done through BMI */
+        if (ar6000_prepare_target(ar->arHifDevice,
+                                  targ_info.target_type,
+                                  targ_info.target_ver) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+        }
+
+    }
+
+    if (ar6000_configure_target(ar) != A_OK) {
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+    }
+
+    A_MEMZERO(&htcInfo,sizeof(htcInfo));
+    htcInfo.pContext = ar;
+    htcInfo.TargetFailure = ar6000_target_failure;
+
+    ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo);
+
+    if (ar->arHtcTarget == NULL) {
+        init_status = A_ERROR;
+        goto avail_ev_failed;
+    }
+
+    spin_lock_init(&ar->arLock);
+
+#ifdef WAPI_ENABLE
+    ar->arWapiEnable = 0;
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+    dev->open = &ar6000_open;
+    dev->stop = &ar6000_close;
+    dev->hard_start_xmit = &ar6000_data_tx;
+    dev->get_stats = &ar6000_get_stats;
+
+    /* dev->tx_timeout = ar6000_tx_timeout; */
+    dev->do_ioctl = &ar6000_ioctl;
+#else
+    dev->netdev_ops = &ar6000_netdev_ops;
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */
+    dev->watchdog_timeo = AR6000_TX_TIMEOUT;
+    dev->wireless_handlers = &ath_iw_handler_def;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+    dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+#else
+    ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+#endif
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+    if(csumOffload){
+
+        dev->features |= NETIF_F_IP_CSUM;/*advertise kernel capability
+                                             to do TCP/UDP CSUM offload for IPV4*/
+        ar->rxMetaVersion=WMI_META_VERSION_2;/*if external frame work is also needed, change and use an extended rxMetaVerion*/
+    }
+#endif
+    if (processDot11Hdr) {
+        dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+    } else {
+        /*
+         * We need the OS to provide us with more headroom in order to
+         * perform dix to 802.3, WMI header encap, and the HTC header
+         */
+        dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
+            sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+    }
+
+#ifdef ATH_AR6K_11N_SUPPORT
+    if((ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs)) == NULL) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize aggr.\n", __func__));
+            init_status = A_ERROR;
+            goto avail_ev_failed;
+    }
+
+    aggr_register_rx_dispatcher(ar->aggr_cntxt, (void *)dev, ar6000_deliver_frames_to_nw_stack);
+#endif
+
+    HIFClaimDevice(ar->arHifDevice, ar);
+
+    /* We only register the device in the global list if we succeed. */
+    /* If the device is in the global list, it will be destroyed     */
+    /* when the module is unloaded.                                  */
+    ar6000_devices[device_index] = dev;
+
+    /* Don't install the init function if BMI is requested */
+    if (!bmienable) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+        dev->init = ar6000_init;
+#else
+        ar6000_netdev_ops.ndo_init = ar6000_init;
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode));
+        if ((wlaninitmode == WLAN_INIT_MODE_UDEV) ||
+            (wlaninitmode == WLAN_INIT_MODE_DRV))
+        {
+            A_STATUS status = A_OK;
+            do {
+                A_BOOL rtnl_lock_grabbed;
+                if ((status = ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+                {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+                    break;
+                }
+#ifdef HTC_RAW_INTERFACE
+                if (bypasswmi) {
+                    A_UINT32 param = 1;
+                    status = BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), 
+                                           (A_UCHAR *)&param, 4);
+                    break;
+                }
+#endif 
+                rtnl_lock_grabbed = rtnl_trylock();
+                status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+                if (rtnl_lock_grabbed) {
+                    rtnl_unlock(); /* we locked it above, so unlock it here */
+                }
+                if (status != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n"));
+                }
+            } while (FALSE);
+
+            if (status != A_OK) {
+                init_status = status;
+                goto avail_ev_failed;
+            }
+        }
+    }
+
+    /* This runs the init function if registered */
+    if (register_netdev(dev)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: register_netdev failed\n"));
+        ar6000_destroy(dev, 0);
+        return A_ERROR;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n",
+                    dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index,
+                    (A_UINT32)ar));
+
+avail_ev_failed :
+    if (A_FAILED(init_status)) {
+        if (bmienable) { 
+            ar6000_sysfs_bmi_deinit(ar);  
+        }
+    }
+
+    return init_status;
+}
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
+    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+    static A_BOOL sip = FALSE;
+
+    if (Status != A_OK) {
+
+        printk(KERN_ERR "ar6000_target_failure: target asserted \n");
+
+        if (timer_pending(&ar->arHBChallengeResp.timer)) {
+            A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+        }
+
+        /* try dumping target assertion information (if any) */
+        ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
+
+        /*
+         * Fetch the logs from the target via the diagnostic
+         * window.
+         */
+        ar6000_dbglog_get_debug_logs(ar);
+
+        /* Report the error only once */
+        if (!sip) {
+            sip = TRUE;
+            errEvent.errorVal = WMI_TARGET_COM_ERR |
+                                WMI_TARGET_FATAL_ERR;
+            ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+                                     (A_UINT8 *)&errEvent,
+                                     sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+        }
+    }
+}
+
+static A_STATUS
+ar6000_unavail_ev(void *context, void *hif_handle)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+        /* NULL out it's entry in the global list */
+    ar6000_devices[ar->arDeviceIndex] = NULL;
+    ar6000_destroy(ar->arNetDev, 1);
+
+    return A_OK;
+}
+
+void
+ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev);
+    /* Stop the transmit queues */
+    netif_stop_queue(dev);
+
+    /* Disable the target and the interrupts associated with it */
+    if (ar->arWmiReady == TRUE)
+    {
+        if (!bypasswmi)
+        {
+            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Disconnect\n", __func__));
+#ifdef ANDROID_ENV
+                if (keepprofile) {
+                    wmi_disconnect_cmd(ar->arWmi);
+                } else 
+#endif /* ANDROID_ENV */
+                {                    
+                    AR6000_SPIN_LOCK(&ar->arLock, 0);
+                    ar6000_init_profile_info(ar);
+                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                    wmi_disconnect_cmd(ar->arWmi);
+                }
+            }
+            A_UNTIMEOUT(&ar->disconnect_timer);
+            ar->arWmiReady  = FALSE;
+            ar->arConnected = FALSE;
+            ar->arConnectPending = FALSE;
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+            ar->arWlanState = WLAN_ENABLED;
+#ifdef USER_KEYS
+            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+            ar->user_key_ctrl      = 0;
+#endif
+        }
+
+         AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI stopped\n", __func__));
+    }
+    else
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI not ready 0x%08x 0x%08x\n",
+            __func__, (unsigned int) ar, (unsigned int) ar->arWmi));
+
+        /* Shut down WMI if we have started it */
+        if(ar->arWmiEnabled == TRUE)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Shut down WMI\n", __func__));
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+        }
+    }
+
+    if (ar->arHtcTarget != NULL) {
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        if (NULL != ar6kHciTransCallbacks.cleanupTransport) {
+            ar6kHciTransCallbacks.cleanupTransport(NULL);
+        }
+#else
+        // FIXME: workaround to reset BT's UART baud rate to default
+        if (NULL != ar->exitCallback) {
+            AR3K_CONFIG_INFO ar3kconfig;
+            A_STATUS status;
+
+            A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+            ar6000_set_default_ar3kconfig(ar, (void *)&ar3kconfig);
+            status = ar->exitCallback(&ar3kconfig);
+            if (A_OK != status) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to reset AR3K baud rate! \n"));
+            }
+        }
+        // END workaround
+        ar6000_cleanup_hci(ar);
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Shutting down HTC .... \n"));
+        /* stop HTC */
+        HTCStop(ar->arHtcTarget);
+    }
+
+    if (resetok) {
+        /* try to reset the device if we can
+         * The driver may have been configure NOT to reset the target during
+         * a debug session */
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Attempting to reset target on instance destroy.... \n"));
+        if (ar->arHifDevice != NULL) {
+            /* WAR for AR6003 cannot do without cold reset */
+            A_BOOL coldReset = (ar->arTargetType==TARGET_TYPE_AR6003) ? TRUE : FALSE;
+            ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, coldReset);
+        }
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Host does not want target reset. \n"));
+    }
+       /* Done with cookies */
+    ar6000_cookie_cleanup(ar);
+}
+/*
+ * We need to differentiate between the surprise and planned removal of the
+ * device because of the following consideration:
+ * - In case of surprise removal, the hcd already frees up the pending
+ *   for the device and hence there is no need to unregister the function
+ *   driver inorder to get these requests. For planned removal, the function
+ *   driver has to explictly unregister itself to have the hcd return all the
+ *   pending requests before the data structures for the devices are freed up.
+ *   Note that as per the current implementation, the function driver will
+ *   end up releasing all the devices since there is no API to selectively
+ *   release a particular device.
+ * - Certain commands issued to the target can be skipped for surprise
+ *   removal since they will anyway not go through.
+ */
+void
+ar6000_destroy(struct net_device *dev, unsigned int unregister)
+{
+    AR_SOFTC_T *ar;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("+ar6000_destroy \n"));
+
+    if((dev == NULL) || ((ar = ar6k_priv(dev)) == NULL))
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): Failed to get device structure.\n", __func__));
+        return;
+    }
+
+    ar->bIsDestroyProgress = TRUE;
+
+    if (down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): down_interruptible failed \n", __func__));
+        return;
+    }
+    if (ar->arWmiReady && !bypasswmi) {
+            ar6000_dbglog_get_debug_logs(ar); 
+    }
+#ifdef ANDROID_ENV
+    if (!android_ar6k_endpoint_is_stop(ar)) {
+#else
+    if (1) {
+#endif 
+        /* only stop endpoint if we are not stop it in suspend_ev */
+        ar6000_stop_endpoint(dev, FALSE);
+    }
+    if (ar->arHtcTarget != NULL) {
+        /* destroy HTC */
+        HTCDestroy(ar->arHtcTarget);
+    }
+    if (ar->arHifDevice != NULL) {
+        /*release the device so we do not get called back on remove incase we
+         * we're explicity destroyed by module unload */
+        HIFReleaseDevice(ar->arHifDevice);
+        HIFShutDownDevice(ar->arHifDevice);
+    }
+#ifdef ATH_AR6K_11N_SUPPORT
+    aggr_module_destroy(ar->aggr_cntxt);
+#endif
+
+       /* Done with cookies */
+    ar6000_cookie_cleanup(ar);
+
+        /* cleanup any allocated AMSDU buffers */
+    ar6000_cleanup_amsdu_rxbufs(ar);
+
+    if (bmienable) {
+        ar6000_sysfs_bmi_deinit(ar);
+    }
+
+    /* Cleanup BMI */
+    BMIInit();
+
+    /* Clear the tx counters */
+    memset(tx_attempt, 0, sizeof(tx_attempt));
+    memset(tx_post, 0, sizeof(tx_post));
+    memset(tx_complete, 0, sizeof(tx_complete));
+
+#ifdef HTC_RAW_INTERFACE
+    if (ar->arRawHtc) {
+        A_FREE(ar->arRawHtc);
+        ar->arRawHtc = NULL;
+    }
+#endif 
+    /* Free up the device data structure */
+    if( unregister )
+        unregister_netdev(dev);
+#ifndef free_netdev
+    kfree(dev);
+#else
+    free_netdev(dev);
+#endif
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_deinit(ar);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("-ar6000_destroy \n"));
+}
+
+static void disconnect_timer_handler(unsigned long ptr)
+{
+    struct net_device *dev = (struct net_device *)ptr;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    A_UNTIMEOUT(&ar->disconnect_timer);
+
+    ar6000_init_profile_info(ar);
+    wmi_disconnect_cmd(ar->arWmi);
+}
+
+static void ar6000_detect_error(unsigned long ptr)
+{
+    struct net_device *dev = (struct net_device *)ptr;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (ar->arHBChallengeResp.outstanding) {
+        ar->arHBChallengeResp.missCnt++;
+    } else {
+        ar->arHBChallengeResp.missCnt = 0;
+    }
+
+    if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
+        /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
+        ar->arHBChallengeResp.missCnt = 0;
+        ar->arHBChallengeResp.seqNum = 0;
+        errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+                                 (A_UINT8 *)&errEvent,
+                                 sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+        return;
+    }
+
+    /* Generate the sequence number for the next challenge */
+    ar->arHBChallengeResp.seqNum++;
+    ar->arHBChallengeResp.outstanding = TRUE;
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    /* Send the challenge on the control channel */
+    if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to send heart beat challenge\n"));
+    }
+
+
+    /* Reschedule the timer for the next challenge */
+    A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+}
+
+void ar6000_init_profile_info(AR_SOFTC_T *ar)
+{
+    ar->arSsidLen            = 0;
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+
+    switch(fwmode) {
+        case HI_OPTION_FW_MODE_IBSS:
+            ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK;
+            break;
+        case HI_OPTION_FW_MODE_BSS_STA:
+            ar->arNetworkType = ar->arNextMode = INFRA_NETWORK;
+            break;
+        case HI_OPTION_FW_MODE_AP:
+            ar->arNetworkType = ar->arNextMode = AP_NETWORK;
+            break;
+    }
+
+    ar->arDot11AuthMode      = OPEN_AUTH;
+    ar->arAuthMode           = NONE_AUTH;
+    ar->arPairwiseCrypto     = NONE_CRYPT;
+    ar->arPairwiseCryptoLen  = 0;
+    ar->arGroupCrypto        = NONE_CRYPT;
+    ar->arGroupCryptoLen     = 0;
+    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+    ar->arBssChannel = 0;
+    ar->arConnected = FALSE;
+}
+
+static void
+ar6000_init_control_info(AR_SOFTC_T *ar)
+{
+    ar->arWmiEnabled         = FALSE;
+    ar6000_init_profile_info(ar);
+    ar->arDefTxKeyIndex      = 0;
+    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+    ar->arChannelHint        = 0;
+    ar->arListenInterval     = A_DEFAULT_LISTEN_INTERVAL;
+    ar->arVersion.host_ver   = AR6K_SW_VERSION;
+    ar->arRssi               = 0;
+    ar->arTxPwr              = 0;
+    ar->arTxPwrSet           = FALSE;
+    ar->arSkipScan           = 0;
+    ar->arBeaconInterval     = 0;
+    ar->arBitRate            = 0;
+    ar->arMaxRetries         = 0;
+    ar->arWmmEnabled         = TRUE;
+    ar->intra_bss            = 1;
+    ar->scan_complete        = 1;
+    A_MEMZERO(&ar->scParams, sizeof(ar->scParams));
+    ar->scParams.shortScanRatio = WMI_SHORTSCANRATIO_DEFAULT;
+    ar->scParams.scanCtrlFlags = DEFAULT_SCAN_CTRL_FLAGS;
+
+    /* Initialize the AP mode state info */
+    {
+        A_UINT8 ctr;
+        A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t));
+
+        /* init the Mutexes */
+        A_MUTEX_INIT(&ar->mcastpsqLock);
+
+        /* Init the PS queues */
+        for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) {
+            A_MUTEX_INIT(&ar->sta_list[ctr].psqLock);
+            A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq);
+        }
+
+        ar->ap_profile_flag = 0;
+        A_NETBUF_QUEUE_INIT(&ar->mcastpsq);
+
+        A_MEMCPY(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3);
+        ar->ap_wmode = DEF_AP_WMODE_G;
+        ar->ap_dtim_period = DEF_AP_DTIM;
+        ar->ap_beacon_interval = DEF_BEACON_INTERVAL;
+    }
+}
+
+static int
+ar6000_open(struct net_device *dev)
+{
+    unsigned long  flags;
+    AR_SOFTC_T    *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    spin_lock_irqsave(&ar->arLock, flags);
+
+#ifndef ANDROID_ENV
+    if(ar->arWlanState == WLAN_DISABLED) {
+        ar->arWlanState = WLAN_ENABLED;
+    }
+#endif 
+
+    if( ar->arConnected || bypasswmi) {
+        netif_carrier_on(dev);
+        /* Wake up the queues */
+        netif_wake_queue(dev);
+    }
+    else
+        netif_carrier_off(dev);
+
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    return 0;
+}
+
+static int
+ar6000_close(struct net_device *dev)
+{
+    AR_SOFTC_T    *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    netif_stop_queue(dev);
+
+#ifdef ANDROID_ENV
+    (void)ar; /* do nothing. Android SDK will handle it */
+#else
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+    if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        wmi_disconnect_cmd(ar->arWmi);
+    } else {
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+    }
+
+    if(ar->arWmiReady == TRUE) {
+        if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0,
+                               0, 0, 0, 0, 0, 0, 0, 0) != A_OK) {
+            return -EIO;
+        }
+        ar->arWlanState = WLAN_DISABLED;
+    }
+#endif
+    return 0;
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connectservice(AR_SOFTC_T               *ar,
+                                      HTC_SERVICE_CONNECT_REQ  *pConnect,
+                                      char                     *pDesc)
+{
+    A_STATUS                 status;
+    HTC_SERVICE_CONNECT_RESP response;
+
+    do {
+
+        A_MEMZERO(&response,sizeof(response));
+
+        status = HTCConnectService(ar->arHtcTarget,
+                                   pConnect,
+                                   &response);
+
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Failed to connect to %s service status:%d \n",
+                              pDesc, status));
+            break;
+        }
+        switch (pConnect->ServiceID) {
+            case WMI_CONTROL_SVC :
+                if (ar->arWmiEnabled) {
+                        /* set control endpoint for WMI use */
+                    wmi_set_control_ep(ar->arWmi, response.Endpoint);
+                }
+                    /* save EP for fast lookup */
+                ar->arControlEp = response.Endpoint;
+                break;
+            case WMI_DATA_BE_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint);
+                break;
+            case WMI_DATA_BK_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint);
+                break;
+            case WMI_DATA_VI_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint);
+                 break;
+           case WMI_DATA_VO_SVC :
+                arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint);
+                break;
+           default:
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ServiceID not mapped %d\n", pConnect->ServiceID));
+                status = A_EINVAL;
+            break;
+        }
+
+    } while (FALSE);
+
+    return status;
+}
+
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
+{
+        /* flush all the data (non-control) streams
+         * we only flush packets that are tagged as data, we leave any control packets that
+         * were in the TX queues alone */
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_BE),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_BK),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_VI),
+                     AR6K_DATA_PKT_TAG);
+    HTCFlushEndpoint(ar->arHtcTarget,
+                     arAc2EndpointID(ar, WMM_AC_VO),
+                     AR6K_DATA_PKT_TAG);
+}
+
+HTC_ENDPOINT_ID
+ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+    return(arAc2EndpointID(ar, ac));
+}
+
+A_UINT8
+ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep )
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+    return(arEndpoint2Ac(ar, ep ));
+}
+
+/* This function does one time initialization for the lifetime of the device */
+int ar6000_init(struct net_device *dev)
+{
+    AR_SOFTC_T *ar;
+    A_STATUS    status;
+    A_INT32     timeleft;
+    A_INT16     i;
+    int         ret = 0;
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+    WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd;
+    WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd;
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+
+    dev_hold(dev);
+    rtnl_unlock();
+
+    if((ar = ar6k_priv(dev)) == NULL)
+    {
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    if (enablerssicompensation) {
+       read_rssi_compensation_param(ar);
+       for (i=-95; i<=0; i++) {
+           rssi_compensation_table[0-i] = rssi_compensation_calc(ar,i);
+       }
+    }
+
+    /* Do we need to finish the BMI phase */
+    if ((wlaninitmode == WLAN_INIT_MODE_USR) && (BMIDone(ar->arHifDevice) != A_OK))
+    {
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    if (!bypasswmi)
+    {
+#if 0 /* TBDXXX */
+        if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
+            A_PRINTF("WARNING: Host version 0x%x does not match Target "
+                    " version 0x%x!\n",
+                    ar->arVersion.host_ver, ar->arVersion.target_ver);
+        }
+#endif
+
+        /* Indicate that WMI is enabled (although not ready yet) */
+        ar->arWmiEnabled = TRUE;
+        if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize WMI.\n", __func__));
+            ret = -EIO;
+            goto ar6000_init_done;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Got WMI @ 0x%08x.\n", __func__,
+            (unsigned int) ar->arWmi));
+    }
+
+    do {
+        HTC_SERVICE_CONNECT_REQ connect;
+
+            /* the reason we have to wait for the target here is that the driver layer
+             * has to init BMI in order to set the host block size,
+             */
+        status = HTCWaitTarget(ar->arHtcTarget);
+
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        A_MEMZERO(&connect,sizeof(connect));
+            /* meta data is unused for now */
+        connect.pMetaData = NULL;
+        connect.MetaDataLength = 0;
+            /* these fields are the same for all service endpoints */
+        connect.EpCallbacks.pContext = ar;
+        connect.EpCallbacks.EpTxCompleteMultiple = ar6000_tx_complete;
+        connect.EpCallbacks.EpRecv = ar6000_rx;
+        connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
+        connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
+            /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
+             * Linux has the peculiarity of not providing flow control between the
+             * NIC and the network stack. There is no API to indicate that a TX packet
+             * was sent which could provide some back pressure to the network stack.
+             * Under linux you would have to wait till the network stack consumed all sk_buffs
+             * before any back-flow kicked in. Which isn't very friendly.
+             * So we have to manage this ourselves */
+        connect.MaxSendQueueDepth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
+        connect.EpCallbacks.RecvRefillWaterMark = AR6000_MAX_RX_BUFFERS / 4; /* set to 25 % */
+        if (0 == connect.EpCallbacks.RecvRefillWaterMark) {
+            connect.EpCallbacks.RecvRefillWaterMark++;
+        }
+            /* connect to control service */
+        connect.ServiceID = WMI_CONTROL_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI CONTROL");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        connect.LocalConnectionFlags |= HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING;
+            /* limit the HTC message size on the send path, although we can receive A-MSDU frames of
+             * 4K, we will only send ethernet-sized (802.3) frames on the send path. */
+        connect.MaxSendMsgSize = WMI_MAX_TX_DATA_FRAME_LENGTH;
+
+            /* to reduce the amount of committed memory for larger A_MSDU frames, use the recv-alloc threshold
+             * mechanism for larger packets */
+        connect.EpCallbacks.RecvAllocThreshold = AR6000_BUFFER_SIZE;
+        connect.EpCallbacks.EpRecvAllocThresh = ar6000_alloc_amsdu_rxbuf;
+
+            /* for the remaining data services set the connection flag to reduce dribbling,
+             * if configured to do so */
+        if (reduce_credit_dribble) {
+            connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
+            /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
+             * of 0-3 */
+            connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+            connect.ConnectionFlags |=
+                        ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+        }
+            /* connect to best-effort service */
+        connect.ServiceID = WMI_DATA_BE_SVC;
+
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA BE");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to back-ground
+             * map this to WMI LOW_PRI */
+        connect.ServiceID = WMI_DATA_BK_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA BK");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to Video service, map this to
+             * to HI PRI */
+        connect.ServiceID = WMI_DATA_VI_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA VI");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+            /* connect to VO service, this is currently not
+             * mapped to a WMI priority stream due to historical reasons.
+             * WMI originally defined 3 priorities over 3 mailboxes
+             * We can change this when WMI is reworked so that priorities are not
+             * dependent on mailboxes */
+        connect.ServiceID = WMI_DATA_VO_SVC;
+        status = ar6000_connectservice(ar,
+                                       &connect,
+                                       "WMI DATA VO");
+        if (A_FAILED(status)) {
+            break;
+        }
+
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0);
+        A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0);
+
+            /* setup access class priority mappings */
+        ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest  */
+        ar->arAcStreamPriMap[WMM_AC_BE] = 1; /*         */
+        ar->arAcStreamPriMap[WMM_AC_VI] = 2; /*         */
+        ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        if (setuphci && (NULL != ar6kHciTransCallbacks.setupTransport)) {
+            HCI_TRANSPORT_MISC_HANDLES hciHandles;
+
+            hciHandles.netDevice = ar->arNetDev;
+            hciHandles.hifDevice = ar->arHifDevice;
+            hciHandles.htcHandle = ar->arHtcTarget;
+            status = (A_STATUS)(ar6kHciTransCallbacks.setupTransport(&hciHandles));
+        }
+#else
+        if (setuphci) {
+                /* setup HCI */
+            status = ar6000_setup_hci(ar);
+        }
+#endif
+
+    } while (FALSE);
+
+    if (A_FAILED(status)) {
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    /*
+     * give our connected endpoints some buffers
+     */
+
+    ar6000_rx_refill(ar, ar->arControlEp);
+    ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE));
+
+    /*
+     * We will post the receive buffers only for SPE or endpoint ping testing so we are
+     * making it conditional on the 'bypasswmi' flag.
+     */
+    if (bypasswmi) {
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK));
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI));
+        ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO));
+    }
+
+    /* allocate some buffers that handle larger AMSDU frames */
+    ar6000_refill_amsdu_rxbufs(ar,AR6000_MAX_AMSDU_RX_BUFFERS);
+
+        /* setup credit distribution */
+    ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
+
+    /* Since cookies are used for HTC transports, they should be */
+    /* initialized prior to enabling HTC.                        */
+    ar6000_cookie_init(ar);
+
+    /* start HTC */
+    status = HTCStart(ar->arHtcTarget);
+
+    if (status != A_OK) {
+        if (ar->arWmiEnabled == TRUE) {
+            wmi_shutdown(ar->arWmi);
+            ar->arWmiEnabled = FALSE;
+            ar->arWmi = NULL;
+        }
+        ar6000_cookie_cleanup(ar);
+        ret = -EIO;
+        goto ar6000_init_done;
+    }
+
+    if (!bypasswmi) {
+        /* Wait for Wmi event to be ready */
+        timeleft = wait_event_interruptible_timeout(arEvent,
+            (ar->arWmiReady == TRUE), wmitimeout * HZ);
+
+        if(!timeleft || signal_pending(current))
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI is not ready or wait was interrupted\n"));
+            ret = -EIO;
+            goto ar6000_init_done;
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() WMI is ready\n", __func__));
+
+        /* Communicate the wmi protocol verision to the target */
+        if ((ar6000_set_host_app_area(ar)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the host app area\n"));
+        }
+
+        /* configure the device for rx dot11 header rules 0,0 are the default values
+         * therefore this command can be skipped if the inputs are 0,FALSE,FALSE.Required
+         if checksum offload is needed. Set RxMetaVersion to 2*/
+        if ((wmi_set_rx_frame_format_cmd(ar->arWmi,ar->rxMetaVersion, processDot11Hdr, processDot11Hdr)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the rx frame format.\n"));
+        }
+
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+        /* Configure the type of BT collocated with WLAN */
+        A_MEMZERO(&sbcb_cmd, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+#ifdef CONFIG_AR600x_BT_QCOM
+        sbcb_cmd.btcoexCoLocatedBTdev = 1;
+#elif defined(CONFIG_AR600x_BT_CSR)
+        sbcb_cmd.btcoexCoLocatedBTdev = 2;
+#elif defined(CONFIG_AR600x_BT_AR3001)
+        sbcb_cmd.btcoexCoLocatedBTdev = 3;
+#else
+#error Unsupported Bluetooth Type
+#endif /* Collocated Bluetooth Type */
+
+        if ((wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd)) != A_OK)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set collocated BT type\n"));
+        }
+
+        /* Configure the type of BT collocated with WLAN */
+        A_MEMZERO(&sbfa_cmd, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+#ifdef CONFIG_AR600x_DUAL_ANTENNA
+        sbfa_cmd.btcoexFeAntType = 2;
+#elif defined(CONFIG_AR600x_SINGLE_ANTENNA)
+        sbfa_cmd.btcoexFeAntType = 1;
+#else
+#error Unsupported Front-End Antenna Configuration
+#endif /* AR600x Front-End Antenna Configuration */
+
+        if ((wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd)) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set fornt end antenna configuration\n"));
+        }
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+    }
+
+    ar->arNumDataEndPts = 1;
+
+    if (bypasswmi) {
+            /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise
+             * the data path through a raw socket is disabled */
+        dev->dev_addr[0] = 0x00;
+        dev->dev_addr[1] = 0x01;
+        dev->dev_addr[2] = 0x02;
+        dev->dev_addr[3] = 0xAA;
+        dev->dev_addr[4] = 0xBB;
+        dev->dev_addr[5] = 0xCC;
+    }
+
+#ifdef ANDROID_ENV
+    android_ar6k_start(ar);
+#endif 
+
+ar6000_init_done:
+    rtnl_lock();
+    dev_put(dev);
+
+    return ret;
+}
+
+
+void
+ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arBitRate = rateKbps;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_ratemask_rx(void *devt, A_UINT32 ratemask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arRateMask = ratemask;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arTxPwr = txPwr;
+    wake_up(&arEvent);
+}
+
+
+void
+ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
+    ar->arNumChannels = numChan;
+
+    wake_up(&arEvent);
+}
+
+A_UINT8
+ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
+{
+    AR_SOFTC_T      *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8         *datap;
+    ATH_MAC_HDR     *macHdr;
+    A_UINT32         i, eptMap;
+
+    (*mapNo) = 0;
+    datap = A_NETBUF_DATA(skb);
+    macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
+    if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
+        return ENDPOINT_2;
+    }
+
+    eptMap = -1;
+    for (i = 0; i < ar->arNodeNum; i ++) {
+        if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
+            (*mapNo) = i + 1;
+            ar->arNodeMap[i].txPending ++;
+            return ar->arNodeMap[i].epId;
+        }
+
+        if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
+            eptMap = i;
+        }
+    }
+
+    if (eptMap == -1) {
+        eptMap = ar->arNodeNum;
+        ar->arNodeNum ++;
+        A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
+    }
+
+    A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
+
+    for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
+        if (!ar->arTxPending[i]) {
+            ar->arNodeMap[eptMap].epId = i;
+            break;
+        }
+        // No free endpoint is available, start redistribution on the inuse endpoints.
+        if (i == ENDPOINT_5) {
+            ar->arNodeMap[eptMap].epId = ar->arNexEpId;
+            ar->arNexEpId ++;
+            if (ar->arNexEpId > ENDPOINT_5) {
+                ar->arNexEpId = ENDPOINT_2;
+            }
+        }
+    }
+
+    (*mapNo) = eptMap + 1;
+    ar->arNodeMap[eptMap].txPending ++;
+
+    return ar->arNodeMap[eptMap].epId;
+}
+
+#ifdef DEBUG
+static void ar6000_dump_skb(struct sk_buff *skb)
+{
+   u_char *ch;
+   for (ch = A_NETBUF_DATA(skb);
+        (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) +
+        A_NETBUF_LEN(skb)); ch++)
+    {
+         AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("%2.2x ", *ch));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("\n"));
+}
+#endif
+
+#ifdef HTC_TEST_SEND_PKTS
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *skb);
+#endif
+
+static int
+ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+#define AC_NOT_MAPPED   99
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8            ac = AC_NOT_MAPPED;
+    HTC_ENDPOINT_ID    eid = ENDPOINT_UNUSED;
+    A_UINT32          mapNo = 0;
+    int               len;
+    struct ar_cookie *cookie;
+    A_BOOL            checkAdHocPsMapping = FALSE,bMoreData = FALSE;
+    HTC_TX_TAG        htc_tag = AR6K_DATA_PKT_TAG;
+    A_UINT8           dot11Hdr = processDot11Hdr;
+#ifdef CONFIG_PM
+    if (ar->arWowState) {
+        A_NETBUF_FREE(skb);
+        return 0;
+    }
+#endif /* CONFIG_PM */
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)
+    skb->list = NULL;
+#endif
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
+                     (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb),
+                     A_NETBUF_LEN(skb)));
+
+    /* If target is not associated */
+    if( (!ar->arConnected && !bypasswmi)
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+     /* TCMD doesnt support any data, free the buf and return */
+    || (ar->arTargetMode == AR6000_TCMD_MODE)
+#endif
+                                            ) {
+        A_NETBUF_FREE(skb);
+        return 0;
+    }
+
+    do {
+
+        if (ar->arWmiReady == FALSE && bypasswmi == 0) {
+            break;
+        }
+
+#ifdef BLOCK_TX_PATH_FLAG
+        if (blocktx) {
+            break;
+        }
+#endif /* BLOCK_TX_PATH_FLAG */
+
+        /* AP mode Power save processing */
+        /* If the dst STA is in sleep state, queue the pkt in its PS queue */
+
+        if (ar->arNetworkType == AP_NETWORK) {
+            ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+            sta_t *conn = NULL;
+
+            /* If the dstMac is a Multicast address & atleast one of the
+             * associated STA is in PS mode, then queue the pkt to the
+             * mcastq
+             */
+            if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+                A_UINT8 ctr=0;
+                A_BOOL qMcast=FALSE;
+
+
+                for (ctr=0; ctr<AP_MAX_NUM_STA; ctr++) {
+                    if (STA_IS_PWR_SLEEP((&ar->sta_list[ctr]))) {
+                        qMcast = TRUE;
+                    }
+                }
+                if(qMcast) {
+
+                    /* If this transmit is not because of a Dtim Expiry q it */
+                    if (ar->DTIMExpired == FALSE) {
+                        A_BOOL isMcastqEmpty = FALSE;
+
+                        A_MUTEX_LOCK(&ar->mcastpsqLock);
+                        isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+                        A_NETBUF_ENQUEUE(&ar->mcastpsq, skb);
+                        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+                        /* If this is the first Mcast pkt getting queued
+                         * indicate to the target to set the BitmapControl LSB
+                         * of the TIM IE.
+                         */
+                        if (isMcastqEmpty) {
+                             wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1);
+                        }
+                        return 0;
+                    } else {
+                     /* This transmit is because of Dtim expiry. Determine if
+                      * MoreData bit has to be set.
+                      */
+                         A_MUTEX_LOCK(&ar->mcastpsqLock);
+                         if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+                             bMoreData = TRUE;
+                         }
+                         A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+                    }
+                }
+            } else {
+                conn = ieee80211_find_conn(ar, datap->dstMac);
+                if (conn) {
+                    if (STA_IS_PWR_SLEEP(conn)) {
+                        /* If this transmit is not because of a PsPoll q it*/
+                        if (!STA_IS_PS_POLLED(conn)) {
+                            A_BOOL isPsqEmpty = FALSE;
+                            /* Queue the frames if the STA is sleeping */
+                            A_MUTEX_LOCK(&conn->psqLock);
+                            isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+                            A_NETBUF_ENQUEUE(&conn->psq, skb);
+                            A_MUTEX_UNLOCK(&conn->psqLock);
+
+                            /* If this is the first pkt getting queued
+                             * for this STA, update the PVB for this STA
+                             */
+                            if (isPsqEmpty) {
+                                wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1);
+                            }
+
+                            return 0;
+                         } else {
+                         /* This tx is because of a PsPoll. Determine if
+                          * MoreData bit has to be set
+                          */
+                             A_MUTEX_LOCK(&conn->psqLock);
+                             if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+                                 bMoreData = TRUE;
+                             }
+                             A_MUTEX_UNLOCK(&conn->psqLock);
+                         }
+                    }
+                } else {
+
+                    /* non existent STA. drop the frame */
+                    A_NETBUF_FREE(skb);
+                    return 0;
+                }
+            }
+        }
+
+        if (ar->arWmiEnabled) {
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+        A_UINT8 csumStart=0;
+        A_UINT8 csumDest=0;
+        A_UINT8 csum=skb->ip_summed;
+        if(csumOffload && (csum==CHECKSUM_PARTIAL)){
+            csumStart=skb->csum_start-(skb->network_header-skb->head)+sizeof(ATH_LLC_SNAP_HDR);
+            csumDest=skb->csum_offset+csumStart;
+        }
+#endif
+            if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len - LINUX_HACK_FUDGE_FACTOR) {
+                struct sk_buff  *newbuf;
+
+                /*
+                 * We really should have gotten enough headroom but sometimes
+                 * we still get packets with not enough headroom.  Copy the packet.
+                 */
+                len = A_NETBUF_LEN(skb);
+                newbuf = A_NETBUF_ALLOC(len);
+                if (newbuf == NULL) {
+                    break;
+                }
+                A_NETBUF_PUT(newbuf, len);
+                A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
+                A_NETBUF_FREE(skb);
+                skb = newbuf;
+                /* fall through and assemble header */
+            }
+
+            if (dot11Hdr) {
+                if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx-wmi_dot11_hdr_add failed\n"));
+                    break;
+                }
+            } else {
+                if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_dix_2_dot3 failed\n"));
+                    break;
+                }
+            }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+            if(csumOffload && (csum ==CHECKSUM_PARTIAL)){
+                WMI_TX_META_V2  metaV2;
+                metaV2.csumStart =csumStart;
+                metaV2.csumDest = csumDest;
+                metaV2.csumFlags = 0x1;/*instruct target to calculate checksum*/
+                if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,
+                                        WMI_META_VERSION_2,&metaV2) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+                    break;
+                }
+
+            }
+            else
+#endif
+            {
+                if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,0,NULL) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+                    break;
+                }
+            }
+
+
+            if ((ar->arNetworkType == ADHOC_NETWORK) &&
+                ar->arIbssPsEnable && ar->arConnected) {
+                    /* flag to check adhoc mapping once we take the lock below: */
+                checkAdHocPsMapping = TRUE;
+
+            } else {
+                    /* get the stream mapping */
+                ac  =  wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled);
+            }
+
+        } else {
+            EPPING_HEADER    *eppingHdr;
+
+            eppingHdr = A_NETBUF_DATA(skb);
+
+            if (IS_EPPING_PACKET(eppingHdr)) {
+                    /* the stream ID is mapped to an access class */
+                ac = eppingHdr->StreamNo_h;
+                    /* some EPPING packets cannot be dropped no matter what access class it was
+                     * sent on.  We can change the packet tag to guarantee it will not get dropped */
+                if (IS_EPING_PACKET_NO_DROP(eppingHdr)) {
+                    htc_tag = AR6K_CONTROL_PKT_TAG;
+                }
+
+                if (ac == HCI_TRANSPORT_STREAM_NUM) {
+                        /* pass this to HCI */
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+                    if (A_SUCCESS(hci_test_send(ar,skb))) {
+                        return 0;
+                    }
+#endif
+                        /* set AC to discard this skb */
+                    ac = AC_NOT_MAPPED;
+                } else {
+                    /* a quirk of linux, the payload of the frame is 32-bit aligned and thus the addition
+                     * of the HTC header will mis-align the start of the HTC frame, so we add some
+                     * padding which will be stripped off in the target */
+                    if (EPPING_ALIGNMENT_PAD > 0) {
+                        A_NETBUF_PUSH(skb, EPPING_ALIGNMENT_PAD);
+                    }
+                }
+
+            } else {
+                    /* not a ping packet, drop it */
+                ac = AC_NOT_MAPPED;
+            }
+        }
+
+    } while (FALSE);
+
+        /* did we succeed ? */
+    if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) {
+            /* cleanup and exit */
+        A_NETBUF_FREE(skb);
+        AR6000_STAT_INC(ar, tx_dropped);
+        AR6000_STAT_INC(ar, tx_aborted_errors);
+        return 0;
+    }
+
+    cookie = NULL;
+
+        /* take the lock to protect driver data */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    do {
+
+        if (checkAdHocPsMapping) {
+            eid = ar6000_ibss_map_epid(skb, dev, &mapNo);
+        }else {
+            eid = arAc2EndpointID (ar, ac);
+        }
+            /* validate that the endpoint is connected */
+        if (eid == 0 || eid == ENDPOINT_UNUSED ) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" eid %d is NOT mapped!\n", eid));
+            break;
+        }
+            /* allocate resource for this packet */
+        cookie = ar6000_alloc_cookie(ar);
+
+        if (cookie != NULL) {
+                /* update counts while the lock is held */
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+    } while (FALSE);
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    if (cookie != NULL) {
+        cookie->arc_bp[0] = (A_UINT32)skb;
+        cookie->arc_bp[1] = mapNo;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(skb),
+                               A_NETBUF_LEN(skb),
+                               eid,
+                               htc_tag);
+
+#ifdef DEBUG
+        if (debugdriver >= 3) {
+            ar6000_dump_skb(skb);
+        }
+#endif
+#ifdef HTC_TEST_SEND_PKTS
+        DoHTCSendPktsTest(ar,mapNo,eid,skb);
+#endif
+            /* HTC interface is asynchronous, if this fails, cleanup will happen in
+             * the ar6000_tx_complete callback */
+        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+    } else {
+            /* no packet to send, cleanup */
+        A_NETBUF_FREE(skb);
+        AR6000_STAT_INC(ar, tx_dropped);
+        AR6000_STAT_INC(ar, tx_aborted_errors);
+    }
+
+    return 0;
+}
+
+int
+ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar_cookie *cookie;
+    HTC_ENDPOINT_ID    eid = ENDPOINT_UNUSED;
+
+    cookie = NULL;
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        /* For now we send ACL on BE endpoint: We can also have a dedicated EP */
+        eid = arAc2EndpointID (ar, 0);
+        /* allocate resource for this packet */
+        cookie = ar6000_alloc_cookie(ar);
+
+        if (cookie != NULL) {
+            /* update counts while the lock is held */
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (cookie != NULL) {
+            cookie->arc_bp[0] = (A_UINT32)skb;
+            cookie->arc_bp[1] = 0;
+            SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                            cookie,
+                            A_NETBUF_DATA(skb),
+                            A_NETBUF_LEN(skb),
+                            eid,
+                            AR6K_DATA_PKT_TAG);
+
+            /* HTC interface is asynchronous, if this fails, cleanup will happen in
+             * the ar6000_tx_complete callback */
+            HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+        } else {
+            /* no packet to send, cleanup */
+            A_NETBUF_FREE(skb);
+            AR6000_STAT_INC(ar, tx_dropped);
+            AR6000_STAT_INC(ar, tx_aborted_errors);
+        }
+    return 0;
+}
+
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+static void
+tvsub(register struct timeval *out, register struct timeval *in)
+{
+    if((out->tv_usec -= in->tv_usec) < 0) {
+        out->tv_sec--;
+        out->tv_usec += 1000000;
+    }
+    out->tv_sec -= in->tv_sec;
+}
+
+void
+applyAPTCHeuristics(AR_SOFTC_T *ar)
+{
+    A_UINT32 duration;
+    A_UINT32 numbytes;
+    A_UINT32 throughput;
+    struct timeval ts;
+    A_STATUS status;
+
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
+        do_gettimeofday(&ts);
+        tvsub(&ts, &aptcTR.samplingTS);
+        duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
+        numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+
+        if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
+            /* Initialize the time stamp and byte count */
+            aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+            do_gettimeofday(&aptcTR.samplingTS);
+
+            /* Calculate and decide based on throughput thresholds */
+            throughput = ((numbytes * 8) / duration);
+            if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
+                /* Disable Sleep and schedule a timer */
+                A_ASSERT(ar->arWmiReady == TRUE);
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+                aptcTR.timerScheduled = TRUE;
+            }
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
+    HTC_SEND_FULL_ACTION    action = HTC_SEND_FULL_KEEP;
+    A_BOOL                  stopNet = FALSE;
+    HTC_ENDPOINT_ID         Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket);
+
+    do {
+
+        if (bypasswmi) {
+            int accessClass;
+
+            if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+                    /* don't drop special control packets */
+                break;
+            }
+
+            accessClass = arEndpoint2Ac(ar,Endpoint);
+                /* for endpoint ping testing drop Best Effort and Background */
+            if ((accessClass == WMM_AC_BE) || (accessClass == WMM_AC_BK)) {
+                action = HTC_SEND_FULL_DROP;
+                stopNet = FALSE;
+            } else {
+                    /* keep but stop the netqueues */
+                stopNet = TRUE;
+            }
+            break;
+        }
+
+        if (Endpoint == ar->arControlEp) {
+                /* under normal WMI if this is getting full, then something is running rampant
+                 * the host should not be exhausting the WMI queue with too many commands
+                 * the only exception to this is during testing using endpointping */
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+                /* set flag to handle subsequent messages */
+            ar->arWMIControlEpFull = TRUE;
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI Control Endpoint is FULL!!! \n"));
+                /* no need to stop the network */
+            stopNet = FALSE;
+            break;
+        }
+
+        /* if we get here, we are dealing with data endpoints getting full */
+
+        if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+            /* don't drop control packets issued on ANY data endpoint */
+            break;
+        }
+
+        if (ar->arNetworkType == ADHOC_NETWORK) {
+            /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to
+             * continue, however we should stop the network */
+            stopNet = TRUE;
+            break;
+        }
+        /* the last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for the highest
+         * active stream */
+        if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri &&
+            ar->arCookieCount <= MAX_HI_COOKIE_NUM) {
+                /* this stream's priority is less than the highest active priority, we
+                 * give preference to the highest priority stream by directing
+                 * HTC to drop the packet that overflowed */
+            action = HTC_SEND_FULL_DROP;
+                /* since we are dropping packets, no need to stop the network */
+            stopNet = FALSE;
+            break;
+        }
+
+    } while (FALSE);
+
+    if (stopNet) {
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        ar->arNetQueueStopped = TRUE;
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        /* one of the data endpoints queues is getting full..need to stop network stack
+         * the queue will resume in ar6000_tx_complete() */
+        netif_stop_queue(ar->arNetDev);
+    }
+
+    return action;
+}
+
+
+static void
+ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPacketQueue)
+{
+    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
+    A_UINT32        mapNo = 0;
+    A_STATUS        status;
+    struct ar_cookie * ar_cookie;
+    HTC_ENDPOINT_ID   eid;
+    A_BOOL          wakeEvent = FALSE;
+    struct sk_buff_head  skb_queue;
+    HTC_PACKET      *pPacket;
+    struct sk_buff  *pktSkb;
+    A_BOOL          flushing = FALSE;
+
+    skb_queue_head_init(&skb_queue);
+
+        /* lock the driver as we update internal state */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        /* reap completed packets */
+    while (!HTC_QUEUE_EMPTY(pPacketQueue)) {
+
+        pPacket = HTC_PACKET_DEQUEUE(pPacketQueue);
+
+        ar_cookie = (struct ar_cookie *)pPacket->pPktContext;
+        A_ASSERT(ar_cookie);
+
+        status = pPacket->Status;
+        pktSkb = (struct sk_buff *)ar_cookie->arc_bp[0];
+        eid = pPacket->Endpoint;
+        mapNo = ar_cookie->arc_bp[1];
+
+        A_ASSERT(pktSkb);
+        A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(pktSkb));
+
+            /* add this to the list, use faster non-lock API */
+        __skb_queue_tail(&skb_queue,pktSkb);
+
+        if (A_SUCCESS(status)) {
+            A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(pktSkb));
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ",
+                         (A_UINT32)pktSkb, (A_UINT32)pPacket->pBuffer,
+                         pPacket->ActualLength,
+                         eid));
+
+        ar->arTxPending[eid]--;
+
+        if ((eid  != ar->arControlEp) || bypasswmi) {
+            ar->arTotalTxDataPending--;
+        }
+
+        if (eid == ar->arControlEp)
+        {
+            if (ar->arWMIControlEpFull) {
+                    /* since this packet completed, the WMI EP is no longer full */
+                ar->arWMIControlEpFull = FALSE;
+            }
+
+            if (ar->arTxPending[eid] == 0) {
+                wakeEvent = TRUE;
+            }
+        }
+
+        if (A_FAILED(status)) {
+            if (status == A_ECANCELED) {
+                    /* a packet was flushed  */
+                flushing = TRUE;
+            }
+            AR6000_STAT_INC(ar, tx_errors);
+            if (status != A_NO_RESOURCE) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() -TX ERROR, status: 0x%x\n", __func__,
+                            status));
+            }
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("OK\n"));
+            flushing = FALSE;
+            AR6000_STAT_INC(ar, tx_packets);
+            ar->arNetStats.tx_bytes += A_NETBUF_LEN(pktSkb);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+            aptcTR.bytesTransmitted += a_netbuf_to_len(pktSkb);
+            applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+        }
+
+        // TODO this needs to be looked at
+        if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
+            && (eid != ar->arControlEp) && mapNo)
+        {
+            mapNo --;
+            ar->arNodeMap[mapNo].txPending --;
+
+            if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
+                A_UINT32 i;
+                for (i = ar->arNodeNum; i > 0; i --) {
+                    if (!ar->arNodeMap[i - 1].txPending) {
+                        A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
+                        ar->arNodeNum --;
+                    } else {
+                        break;
+                    }
+                }
+            }
+        }
+
+        ar6000_free_cookie(ar, ar_cookie);
+
+        if (ar->arNetQueueStopped) {
+            ar->arNetQueueStopped = FALSE;
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    /* lock is released, we can freely call other kernel APIs */
+
+        /* free all skbs in our local list */
+    while (!skb_queue_empty(&skb_queue)) {
+            /* use non-lock version */
+        pktSkb = __skb_dequeue(&skb_queue);
+        A_NETBUF_FREE(pktSkb);
+    }
+
+    if ((ar->arConnected == TRUE) || (bypasswmi)) {
+        if (!flushing) {
+                /* don't wake the queue if we are flushing, other wise it will just
+                 * keep queueing packets, which will keep failing */
+            netif_wake_queue(ar->arNetDev);
+        }
+    }
+
+    if (wakeEvent) {
+        wake_up(&arEvent);
+    }
+
+}
+
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr)
+{
+    sta_t *conn = NULL;
+    A_UINT8 i, max_conn;
+
+    switch(ar->arNetworkType) {
+        case AP_NETWORK:
+            max_conn = AP_MAX_NUM_STA;
+            break;
+        default:
+            max_conn=0;
+            break;
+    }
+
+    for (i = 0; i < max_conn; i++) {
+        if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) {
+            conn = &ar->sta_list[i];
+            break;
+        }
+    }
+
+    return conn;
+}
+
+sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid)
+{
+    sta_t *conn = NULL;
+    A_UINT8 ctr;
+
+    for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
+        if (ar->sta_list[ctr].aid == aid) {
+            conn = &ar->sta_list[ctr];
+            break;
+        }
+    }
+    return conn;
+}
+
+/*
+ * Receive event handler.  This is called by HTC when a packet is received
+ */
+int pktcount;
+static void
+ar6000_rx(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+    struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
+    int minHdrLen;
+    A_UINT8 containsDot11Hdr = 0;
+    A_STATUS        status = pPacket->Status;
+    HTC_ENDPOINT_ID   ept = pPacket->Endpoint;
+
+    A_ASSERT((status != A_OK) ||
+             (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x status:%d",
+                    (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
+                    pPacket->ActualLength, status));
+    if (status != A_OK) {
+        if (status != A_ECANCELED) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("RX ERR (%d) \n",status));
+        }
+    }
+
+        /* take lock to protect buffer counts
+         * and adaptive power throughput state */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    if (A_SUCCESS(status)) {
+        AR6000_STAT_INC(ar, rx_packets);
+        ar->arNetStats.rx_bytes += pPacket->ActualLength;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+        aptcTR.bytesReceived += a_netbuf_to_len(skb);
+        applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+        A_NETBUF_PUT(skb, pPacket->ActualLength +  HTC_HEADER_LEN);
+        A_NETBUF_PULL(skb, HTC_HEADER_LEN);
+
+#ifdef DEBUG
+        if (debugdriver >= 2) {
+            ar6000_dump_skb(skb);
+        }
+#endif /* DEBUG */
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    skb->dev = ar->arNetDev;
+    if (status != A_OK) {
+        AR6000_STAT_INC(ar, rx_errors);
+        A_NETBUF_FREE(skb);
+    } else if (ar->arWmiEnabled == TRUE) {
+        if (ept == ar->arControlEp) {
+           /*
+            * this is a wmi control msg
+            */
+#ifdef ANDROID_ENV
+            android_ar6k_check_wow_status(ar);
+#endif /* ANDROID_ENV */
+            wmi_control_rx(ar->arWmi, skb);
+        } else {
+                WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
+                A_UINT8 is_amsdu, tid, is_acl_data_frame;
+                is_acl_data_frame = WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL;
+
+                /*
+                 * this is a wmi data packet
+                 */
+                 // NWF
+
+                if (processDot11Hdr) {
+                    minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR);
+                } else {
+                    minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
+                          sizeof(ATH_LLC_SNAP_HDR);
+                }
+
+                /* In the case of AP mode we may receive NULL data frames
+                 * that do not have LLC hdr. They are 16 bytes in size.
+                 * Allow these frames in the AP mode.
+                 * ACL data frames don't follow ethernet frame bounds for
+                 * min length
+                 */
+                if (ar->arNetworkType != AP_NETWORK &&  !is_acl_data_frame &&
+                    ((pPacket->ActualLength < minHdrLen) ||
+                    (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)))
+                {
+                    /*
+                     * packet is too short or too long
+                     */
+                    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("TOO SHORT or TOO LONG\n"));
+                    AR6000_STAT_INC(ar, rx_errors);
+                    AR6000_STAT_INC(ar, rx_length_errors);
+                    A_NETBUF_FREE(skb);
+                } else {
+                    A_UINT16 seq_no;
+                    A_UINT8 meta_type;
+
+#if 0
+                    /* Access RSSI values here */
+                    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("RSSI %d\n",
+                        ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi));
+#endif
+                    /* Get the Power save state of the STA */
+                    if (ar->arNetworkType == AP_NETWORK) {
+                        sta_t *conn = NULL;
+                        A_UINT8 psState=0,prevPsState;
+                        ATH_MAC_HDR *datap=NULL;
+                        A_UINT16 offset;
+
+                        meta_type = WMI_DATA_HDR_GET_META(dhdr);
+
+                        psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info
+                                     >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK;
+
+                        offset = sizeof(WMI_DATA_HDR);
+
+                        switch (meta_type) {
+                            case 0:
+                                break;
+                            case WMI_META_VERSION_1:
+                                offset += sizeof(WMI_RX_META_V1);
+                                break;
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+                            case WMI_META_VERSION_2:
+                                offset += sizeof(WMI_RX_META_V2);
+                                break;
+#endif
+                            default:
+                                break;
+                        }
+
+                        datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+offset);
+                        conn = ieee80211_find_conn(ar, datap->srcMac);
+
+                        if (conn) {
+                            /* if there is a change in PS state of the STA,
+                             * take appropriate steps.
+                             * 1. If Sleep-->Awake, flush the psq for the STA
+                             *    Clear the PVB for the STA.
+                             * 2. If Awake-->Sleep, Starting queueing frames
+                             * the STA.
+                             */
+                            prevPsState = STA_IS_PWR_SLEEP(conn);
+                            if (psState) {
+                                STA_SET_PWR_SLEEP(conn);
+                            } else {
+                                STA_CLR_PWR_SLEEP(conn);
+                            }
+
+                            if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) {
+
+                                if (!STA_IS_PWR_SLEEP(conn)) {
+
+                                    A_MUTEX_LOCK(&conn->psqLock);
+                                    while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+                                        struct sk_buff *skb=NULL;
+
+                                        skb = A_NETBUF_DEQUEUE(&conn->psq);
+                                        A_MUTEX_UNLOCK(&conn->psqLock);
+                                        ar6000_data_tx(skb,ar->arNetDev);
+                                        A_MUTEX_LOCK(&conn->psqLock);
+                                    }
+                                    A_MUTEX_UNLOCK(&conn->psqLock);
+                                    /* Clear the PVB for this STA */
+                                    wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+                                }
+                            }
+                        } else {
+                            /* This frame is from a STA that is not associated*/
+                            A_ASSERT(FALSE);
+                        }
+
+                        /* Drop NULL data frames here */
+                        if((pPacket->ActualLength < minHdrLen) ||
+                                (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)) {
+                            A_NETBUF_FREE(skb);
+                            goto rx_done;
+                        }
+                    }
+
+                    is_amsdu = WMI_DATA_HDR_IS_AMSDU(dhdr);
+                    tid = WMI_DATA_HDR_GET_UP(dhdr);
+                    seq_no = WMI_DATA_HDR_GET_SEQNO(dhdr);
+                    meta_type = WMI_DATA_HDR_GET_META(dhdr);
+                    containsDot11Hdr = WMI_DATA_HDR_GET_DOT11(dhdr);
+
+                    wmi_data_hdr_remove(ar->arWmi, skb);
+
+                    switch (meta_type) {
+                        case WMI_META_VERSION_1:
+                            {
+                                WMI_RX_META_V1 *pMeta = (WMI_RX_META_V1 *)A_NETBUF_DATA(skb);
+                                A_PRINTF("META %d %d %d %d %x\n", pMeta->status, pMeta->rix, pMeta->rssi, pMeta->channel, pMeta->flags);
+                                A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V1));
+                                break;
+                            }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+                        case WMI_META_VERSION_2:
+                            {
+                                WMI_RX_META_V2 *pMeta = (WMI_RX_META_V2 *)A_NETBUF_DATA(skb);
+                                if(pMeta->csumFlags & 0x1){
+                                    skb->ip_summed=CHECKSUM_COMPLETE;
+                                    skb->csum=(pMeta->csum);
+                                }
+                                A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V2));
+                                break;
+                            }
+#endif
+                        default:
+                            break;
+                    }
+
+                    A_ASSERT(status == A_OK);
+
+                    /* NWF: print the 802.11 hdr bytes */
+                    if(containsDot11Hdr) {
+                        status = wmi_dot11_hdr_remove(ar->arWmi,skb);
+                    } else if(!is_amsdu && !is_acl_data_frame) {
+                        status = wmi_dot3_2_dix(skb);
+                    }
+
+                    if (status != A_OK) {
+                        /* Drop frames that could not be processed (lack of memory, etc.) */
+                        A_NETBUF_FREE(skb);
+                        goto rx_done;
+                    }
+
+                    if (is_acl_data_frame) {
+                        A_NETBUF_PUSH(skb, sizeof(int));
+                        *((short *)A_NETBUF_DATA(skb)) = WMI_ACL_DATA_EVENTID;
+                    }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+                    /*
+                     * extra push and memcpy, for eth_type_trans() of 2.4 kernel
+                     * will pull out hard_header_len bytes of the skb.
+                     */
+                    A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
+                    A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) +
+                             sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
+#endif
+                    if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+                        if (ar->arNetworkType == AP_NETWORK) {
+                            struct sk_buff *skb1 = NULL;
+                            ATH_MAC_HDR *datap;
+
+                            datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+                            if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+                                /* Bcast/Mcast frames should be sent to the OS
+                                 * stack as well as on the air.
+                                 */
+                                skb1 = skb_copy(skb,GFP_ATOMIC);
+                            } else {
+                                /* Search for a connected STA with dstMac as
+                                 * the Mac address. If found send the frame to
+                                 * it on the air else send the frame up the
+                                 * stack
+                                 */
+                                sta_t *conn = NULL;
+                                conn = ieee80211_find_conn(ar, datap->dstMac);
+
+                                if (conn && ar->intra_bss) {
+                                    skb1 = skb;
+                                    skb = NULL;
+                                } else if(conn && !ar->intra_bss) {
+                                    A_NETBUF_FREE(skb);
+                                    skb = NULL;
+                                }
+                            }
+                            if (skb1) {
+                                ar6000_data_tx(skb1, ar->arNetDev);
+                            }
+                        }
+                    }
+#ifdef ATH_AR6K_11N_SUPPORT
+                    aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, is_amsdu, (void **)&skb);
+#endif
+                    ar6000_deliver_frames_to_nw_stack((void *) ar->arNetDev, (void *)skb);
+                }
+            }
+    } else {
+        if (EPPING_ALIGNMENT_PAD > 0) {
+            A_NETBUF_PULL(skb, EPPING_ALIGNMENT_PAD);
+        }
+        ar6000_deliver_frames_to_nw_stack((void *)ar->arNetDev, (void *)skb);
+    }
+
+rx_done:
+
+    return;
+}
+
+static void
+ar6000_deliver_frames_to_nw_stack(void *dev, void *osbuf)
+{
+    struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+    if(skb) {
+        skb->dev = dev;
+        if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = eth_type_trans(skb, skb->dev);
+        /*
+         * If this routine is called on a ISR (Hard IRQ) or DSR (Soft IRQ)
+         * or tasklet use the netif_rx to deliver the packet to the stack
+         * netif_rx will queue the packet onto the receive queue and mark
+         * the softirq thread has a pending action to complete. Kernel will 
+         * schedule the softIrq kernel thread after processing the DSR.
+         *
+         * If this routine is called on a process context, use netif_rx_ni
+         * which will schedle the softIrq kernel thread after queuing the packet.
+         */
+            if (in_interrupt()) {
+                netif_rx(skb);
+            } else {
+                netif_rx_ni(skb);
+            }
+        } else {
+            A_NETBUF_FREE(skb);
+        }
+    }
+}
+
+#if 0
+static void
+ar6000_deliver_frames_to_bt_stack(void *dev, void *osbuf)
+{
+    struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+    if(skb) {
+        skb->dev = dev;
+        if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = htons(ETH_P_CONTROL);
+            netif_rx(skb);
+        } else {
+            A_NETBUF_FREE(skb);
+        }
+    }
+}
+#endif
+
+static void
+ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
+{
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
+    void        *osBuf;
+    int         RxBuffers;
+    int         buffersToRefill;
+    HTC_PACKET  *pPacket;
+    HTC_PACKET_QUEUE queue;
+
+    buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
+                                    HTCGetNumRecvBuffers(ar->arHtcTarget, Endpoint);
+
+    if (buffersToRefill <= 0) {
+            /* fast return, nothing to fill */
+        return;
+    }
+
+    INIT_HTC_PACKET_QUEUE(&queue);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
+                    buffersToRefill, Endpoint));
+
+    for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
+        osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
+        if (NULL == osBuf) {
+            break;
+        }
+            /* the HTC packet wrapper is at the head of the reserved area
+             * in the skb */
+        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+            /* set re-fill info */
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
+            /* add to queue */
+        HTC_PACKET_ENQUEUE(&queue,pPacket);
+    }
+
+    if (!HTC_QUEUE_EMPTY(&queue)) {
+            /* add packets */
+        HTCAddReceivePktMultiple(ar->arHtcTarget, &queue);
+    }
+
+}
+
+  /* clean up our amsdu buffer list */
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar)
+{
+    HTC_PACKET  *pPacket;
+    void        *osBuf;
+
+        /* empty AMSDU buffer queue and free OS bufs */
+    while (TRUE) {
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == pPacket) {
+            break;
+        }
+
+        osBuf = pPacket->pPktContext;
+        if (NULL == osBuf) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        A_NETBUF_FREE(osBuf);
+    }
+
+}
+
+
+    /* refill the amsdu buffer list */
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count)
+{
+    HTC_PACKET  *pPacket;
+    void        *osBuf;
+
+    while (Count > 0) {
+        osBuf = A_NETBUF_ALLOC(AR6000_AMSDU_BUFFER_SIZE);
+        if (NULL == osBuf) {
+            break;
+        }
+            /* the HTC packet wrapper is at the head of the reserved area
+             * in the skb */
+        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+            /* set re-fill info */
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_AMSDU_BUFFER_SIZE,0);
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+            /* put it in the list */
+        HTC_PACKET_ENQUEUE(&ar->amsdu_rx_buffer_queue,pPacket);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        Count--;
+    }
+
+}
+
+    /* callback to allocate a large receive buffer for a pending packet.  This function is called when
+     * an HTC packet arrives whose length exceeds a threshold value
+     *
+     * We use a pre-allocated list of buffers of maximum AMSDU size (4K).  Under linux it is more optimal to
+     * keep the allocation size the same to optimize cached-slab allocations.
+     *
+     * */
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length)
+{
+    HTC_PACKET  *pPacket = NULL;
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
+    int         refillCount = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_alloc_amsdu_rxbuf: eid=%d, Length:%d\n",Endpoint,Length));
+
+    do {
+
+        if (Length <= AR6000_BUFFER_SIZE) {
+                /* shouldn't be getting called on normal sized packets */
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        if (Length > AR6000_AMSDU_BUFFER_SIZE) {
+            A_ASSERT(FALSE);
+            break;
+        }
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+            /* allocate a packet from the list */
+        pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+            /* see if we need to refill again */
+        refillCount = AR6000_MAX_AMSDU_RX_BUFFERS - HTC_PACKET_QUEUE_DEPTH(&ar->amsdu_rx_buffer_queue);
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == pPacket) {
+            break;
+        }
+            /* set actual endpoint ID */
+        pPacket->Endpoint = Endpoint;
+
+    } while (FALSE);
+
+    if (refillCount >= AR6000_AMSDU_REFILL_THRESHOLD) {
+        ar6000_refill_amsdu_rxbufs(ar,refillCount);
+    }
+
+    return pPacket;
+}
+
+
+static struct net_device_stats *
+ar6000_get_stats(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    return &ar->arNetStats;
+}
+
+static struct iw_statistics *
+ar6000_get_iwstats(struct net_device * dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    struct iw_statistics * pIwStats = &ar->arIwStats;
+    int rtnllocked;
+
+    if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE)
+    {
+        pIwStats->status = 0;
+        pIwStats->qual.qual = 0;
+        pIwStats->qual.level =0;
+        pIwStats->qual.noise = 0;
+        pIwStats->discard.code =0;
+        pIwStats->discard.retries=0;
+        pIwStats->miss.beacon =0;
+        return pIwStats;
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+    /*
+     * The in_atomic function is used to determine if the scheduling is
+     * allowed in the current context or not. This was introduced in 2.6
+     * From what I have read on the differences between 2.4 and 2.6, the
+     * 2.4 kernel did not support preemption and so this check might not
+     * be required for 2.4 kernels.
+     */
+    if (in_atomic())
+    {
+        wmi_get_stats_cmd(ar->arWmi);
+
+        pIwStats->status = 1 ;
+        pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+        pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
+        pIwStats->qual.noise = pStats->noise_floor_calibation;
+        pIwStats->discard.code = pStats->rx_decrypt_err;
+        pIwStats->discard.retries = pStats->tx_retry_cnt;
+        pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+        return pIwStats;
+    }
+#endif /* LINUX_VERSION_CODE */
+
+    if (down_interruptible(&ar->arSem)) {
+        pIwStats->status = 0;
+        return pIwStats;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        pIwStats->status = 0;
+        return pIwStats;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        pIwStats->status = 0;
+        return pIwStats;
+    }
+
+    dev_hold(dev);   
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+    rtnllocked = rtnl_is_locked();
+#else
+    rtnllocked = TRUE;
+#endif
+    if (rtnllocked) {
+        rtnl_unlock();
+    }
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+    if (rtnllocked) {
+        rtnl_lock();
+    }
+    dev_put(dev);
+
+    if (signal_pending(current)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : WMI get stats timeout \n"));
+        up(&ar->arSem);
+        pIwStats->status = 0;
+        return pIwStats;
+    }
+    pIwStats->status = 1 ;
+    pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+    pIwStats->qual.level =pStats->cs_aveBeacon_rssi;  /* noise is -95 dBm */
+    pIwStats->qual.noise = pStats->noise_floor_calibation;
+    pIwStats->discard.code = pStats->rx_decrypt_err;
+    pIwStats->discard.retries = pStats->tx_retry_cnt;
+    pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+    up(&ar->arSem);
+    return pIwStats;
+}
+
+void
+ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+    struct net_device *dev = ar->arNetDev;
+
+    ar->arWmiReady = TRUE;
+    wake_up(&arEvent);
+    A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+        dev->dev_addr[0], dev->dev_addr[1],
+        dev->dev_addr[2], dev->dev_addr[3],
+        dev->dev_addr[4], dev->dev_addr[5]));
+
+    ar->arPhyCapability = phyCap;
+    ar->arVersion.wlan_ver = vers;
+
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+    wmi_pmparams_cmd(ar->arWmi, 0, 1, 0, 0, 1, IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN);
+#endif
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP
+    wmi_set_lpreamble_cmd(ar->arWmi, 0, WMI_DONOT_IGNORE_BARKER_IN_ERP);
+#endif
+    wmi_set_keepalive_cmd(ar->arWmi, WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
+}
+
+A_UINT8
+add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie,
+            A_UINT8 ielen, A_UINT8 keymgmt, A_UINT8 ucipher, A_UINT8 auth)
+{
+    A_INT8    free_slot=-1, i;
+
+    for(i=0; i < AP_MAX_NUM_STA; i++) {
+        if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) {
+            /* it is already available */
+            return 0;
+        }
+
+        if(!((1 << i) & ar->sta_list_index)) {
+            free_slot = i;
+            break;
+        }
+    }
+
+    if(free_slot >= 0) {
+        A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN);
+        A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen);
+        ar->sta_list[free_slot].aid = aid;
+        ar->sta_list[free_slot].keymgmt = keymgmt;
+        ar->sta_list[free_slot].ucipher = ucipher;
+        ar->sta_list[free_slot].auth = auth;
+        ar->sta_list_index = ar->sta_list_index | (1 << free_slot);
+        ar->arAPStats.sta[aid-1].aid = aid;
+        return 1;
+    }
+    return 0; /* not added */
+}
+
+void
+ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
+                     A_UINT16 listenInterval, A_UINT16 beaconInterval,
+                     NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
+                     A_UINT8 assocReqLen, A_UINT8 assocRespLen,
+                     A_UINT8 *assocInfo)
+{
+    union iwreq_data wrqu;
+    int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
+    static const char *tag1 = "ASSOCINFO(ReqIEs=";
+    static const char *tag2 = "ASSOCRESPIE=";
+    static const char *beaconIetag = "BEACONIE=";
+    char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1];
+    char *pos;
+    A_UINT8 key_op_ctrl;
+    unsigned long flags;
+    struct ieee80211req_key *ik;
+    CRYPTO_TYPE keyType = NONE_CRYPT;
+
+    if(ar->arNetworkType & AP_NETWORK) {
+        struct net_device *dev = ar->arNetDev;
+        if(A_MEMCMP(dev->dev_addr, bssid, ATH_MAC_LEN)==0) {
+            ar->arACS = channel;
+            ik = &ar->ap_mode_bkey;
+
+            switch(ar->arAuthMode) {
+            case NONE_AUTH:
+                if(ar->arPairwiseCrypto == WEP_CRYPT) {
+                    ar6000_install_static_wep_keys(ar);
+                }
+#ifdef WAPI_ENABLE
+                else if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                    ap_set_wapi_key(ar, ik);
+                }
+#endif
+                break;
+            case WPA_PSK_AUTH:
+            case WPA2_PSK_AUTH:
+            case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+                switch (ik->ik_type) {
+                    case IEEE80211_CIPHER_TKIP:
+                        keyType = TKIP_CRYPT;
+                        break;
+                    case IEEE80211_CIPHER_AES_CCM:
+                        keyType = AES_CRYPT;
+                        break;
+                    default:
+                       goto skip_key;
+                }
+                wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE,
+                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                                ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                                SYNC_BOTH_WMIFLAG);
+
+                break;
+            }
+skip_key:
+            ar->arConnected  = TRUE;
+            return;
+        }
+
+        A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n "
+            " AID=%d \n", bssid[0], bssid[1], bssid[2],
+             bssid[3], bssid[4], bssid[5], channel);
+        switch ((listenInterval>>8)&0xFF) {
+            case OPEN_AUTH:
+                A_PRINTF("AUTH: OPEN\n");
+                break;
+            case SHARED_AUTH:
+                A_PRINTF("AUTH: SHARED\n");
+                break;
+            default:
+                A_PRINTF("AUTH: Unknown\n");
+                break;
+        };
+        switch (listenInterval&0xFF) {
+            case WPA_PSK_AUTH:
+                A_PRINTF("KeyMgmt: WPA-PSK\n");
+                break;
+            case WPA2_PSK_AUTH:
+                A_PRINTF("KeyMgmt: WPA2-PSK\n");
+                break;
+            default:
+                A_PRINTF("KeyMgmt: NONE\n");
+                break;
+        };
+        switch (beaconInterval) {
+            case AES_CRYPT:
+                A_PRINTF("Cipher: AES\n");
+                break;
+            case TKIP_CRYPT:
+                A_PRINTF("Cipher: TKIP\n");
+                break;
+            case WEP_CRYPT:
+                A_PRINTF("Cipher: WEP\n");
+                break;
+#ifdef WAPI_ENABLE
+            case WAPI_CRYPT:
+                A_PRINTF("Cipher: WAPI\n");
+                break;
+#endif
+            default:
+                A_PRINTF("Cipher: NONE\n");
+                break;
+        };
+
+        add_new_sta(ar, bssid, channel /*aid*/,
+            assocInfo /* WPA IE */, assocRespLen /* IE len */,
+            listenInterval&0xFF /* Keymgmt */, beaconInterval /* cipher */,
+            (listenInterval>>8)&0xFF /* auth alg */);
+
+        /* Send event to application */
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+        wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL);
+        /* In case the queue is stopped when we switch modes, this will
+         * wake it up
+         */
+        netif_wake_queue(ar->arNetDev);
+        return;
+    }
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_connect_event(ar, channel, bssid,
+                                listenInterval, beaconInterval,
+                                networkType, beaconIeLen,
+                                assocReqLen, assocRespLen,
+                                assocInfo);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
+    ar->arBssChannel = channel;
+
+    A_PRINTF("AR6000 connected event on freq %d ", channel);
+    A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+            " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
+            " assocRespLen =%d\n",
+             bssid[0], bssid[1], bssid[2],
+             bssid[3], bssid[4], bssid[5],
+             listenInterval, beaconInterval,
+             beaconIeLen, assocReqLen, assocRespLen);
+    if (networkType & ADHOC_NETWORK) {
+        if (networkType & ADHOC_CREATOR) {
+            A_PRINTF("Network: Adhoc (Creator)\n");
+        } else {
+            A_PRINTF("Network: Adhoc (Joiner)\n");
+        }
+    } else {
+        A_PRINTF("Network: Infrastructure\n");
+    }
+
+    if ((ar->arNetworkType == INFRA_NETWORK)) {
+        wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0);
+    }
+
+    if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nBeaconIEs= "));
+
+        beacon_ie_pos = 0;
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", beaconIetag);
+        pos = buf + 9;
+        for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+    if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
+    {
+        assoc_resp_ie_pos = beaconIeLen + assocReqLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16)  +  /* status Code */
+                            sizeof(A_UINT16)  ;  /* associd */
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", tag2);
+        pos = buf + 12;
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocRespIEs= "));
+        /*
+         * The Association Response Frame w.o. the WLAN header is delivered to
+         * the host, so skip over to the IEs
+         */
+        for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+    if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
+        /*
+         * assoc Request includes capability and listen interval. Skip these.
+         */
+        assoc_req_ie_pos =  beaconIeLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16);    /* listen interval */
+
+        A_MEMZERO(buf, sizeof(buf));
+        sprintf(buf, "%s", tag1);
+        pos = buf + 17;
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AssocReqIEs= "));
+        for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+            sprintf(pos, "%2.2x", assocInfo[i]);
+            pos += 2;;
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+    }
+
+#ifdef USER_KEYS
+    if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
+        ar->user_saved_keys.keyOk == TRUE)
+    {
+        key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
+
+        if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
+            key_op_ctrl &= ~KEY_OP_INIT_RSC;
+        } else {
+            key_op_ctrl |= KEY_OP_INIT_RSC;
+        }
+        ar6000_reinstall_keys(ar, key_op_ctrl);
+    }
+#endif /* USER_KEYS */
+
+    netif_wake_queue(ar->arNetDev);
+
+    if ((networkType & ADHOC_NETWORK)      &&
+        (OPEN_AUTH == ar->arDot11AuthMode) &&
+        (NONE_AUTH == ar->arAuthMode)      &&
+        (WEP_CRYPT == ar->arPairwiseCrypto))
+    {
+        if (!ar->arConnected) {
+            wmi_addKey_cmd(ar->arWmi,
+                           ar->arDefTxKeyIndex,
+                           WEP_CRYPT,
+                           GROUP_USAGE | TX_USAGE,
+                           ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen,
+                           NULL,
+                           ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL,
+                           NO_SYNC_WMIFLAG);
+        }
+    }
+
+    /* Update connect & link status atomically */
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected  = TRUE;
+    ar->arConnectPending = FALSE;
+    netif_carrier_on(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    /* reset the rx aggr state */
+    aggr_reset_state(ar->aggr_cntxt);
+    reconnect_flag = 0;
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
+    wrqu.addr.sa_family = ARPHRD_ETHER;
+    wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
+        A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
+        ar->arNodeNum = 0;
+        ar->arNexEpId = ENDPOINT_2;
+    }
+   if (!ar->arUserBssFilter) {
+        wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+   }
+
+}
+
+void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
+{
+    A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
+    ar->arNumDataEndPts = num;
+}
+
+void
+sta_cleanup(AR_SOFTC_T *ar, A_UINT8 i)
+{
+    struct sk_buff *skb;
+
+    /* empty the queued pkts in the PS queue if any */
+    A_MUTEX_LOCK(&ar->sta_list[i].psqLock);
+    while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) {
+        skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq);
+        A_NETBUF_FREE(skb);
+    }
+    A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock);
+
+    /* Zero out the state fields */
+    A_MEMZERO(&ar->arAPStats.sta[ar->sta_list[i].aid-1], sizeof(WMI_PER_STA_STAT));
+    A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN);
+    A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE);
+    ar->sta_list[i].aid = 0;
+    ar->sta_list[i].flags = 0;
+
+    ar->sta_list_index = ar->sta_list_index & ~(1 << i);
+
+}
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason)
+{
+    A_UINT8 i, removed=0;
+
+    if(IS_MAC_NULL(mac)) {
+        return removed;
+    }
+
+    if(IS_MAC_BCAST(mac)) {
+        A_PRINTF("DEL ALL STA\n");
+        for(i=0; i < AP_MAX_NUM_STA; i++) {
+            if(!IS_MAC_NULL(ar->sta_list[i].mac)) {
+                sta_cleanup(ar, i);
+                removed = 1;
+            }
+        }
+    } else {
+        for(i=0; i < AP_MAX_NUM_STA; i++) {
+            if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) {
+                A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+                " aid=%d REASON=%d\n", mac[0], mac[1], mac[2],
+                 mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason);
+
+                sta_cleanup(ar, i);
+                removed = 1;
+                break;
+            }
+        }
+    }
+    return removed;
+}
+
+void
+ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
+                        A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+    A_UINT8 i;
+    unsigned long flags;
+
+    if(ar->arNetworkType & AP_NETWORK) {
+        union iwreq_data wrqu;
+        struct sk_buff *skb;
+
+        if(!remove_sta(ar, bssid, protocolReasonStatus)) {
+            return;
+        }
+
+        /* If there are no more associated STAs, empty the mcast PS q */
+        if (ar->sta_list_index == 0) {
+            A_MUTEX_LOCK(&ar->mcastpsqLock);
+            while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+                skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+                A_NETBUF_FREE(skb);
+            }
+            A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+            /* Clear the LSB of the BitMapCtl field of the TIM IE */
+            wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+        }
+
+        if(!IS_MAC_BCAST(bssid)) {
+            /* Send event to application */
+            A_MEMZERO(&wrqu, sizeof(wrqu));
+            A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+            wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL);
+        }
+        return;
+    }
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_disconnect_event(ar, reason, bssid,
+                                   assocRespLen, assocInfo,
+                                   protocolReasonStatus);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if (NO_NETWORK_AVAIL != reason)
+    {
+        union iwreq_data wrqu;
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+        wrqu.addr.sa_family = ARPHRD_ETHER;
+
+        /* Send disconnect event to supplicant */
+        wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+    }
+    /* it is necessary to clear the host-side rx aggregation state */
+
+    aggr_reset_state(ar->aggr_cntxt);
+
+    A_UNTIMEOUT(&ar->disconnect_timer);
+
+    A_PRINTF("AR6000 disconnected");
+    if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
+        A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+                 bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nDisconnect Reason is %d", reason));
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nProtocol Reason/Status Code is %d", protocolReasonStatus));
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocResp Frame = %s",
+                    assocRespLen ? " " : "NULL"));
+    for (i = 0; i < assocRespLen; i++) {
+        if (!(i % 0x10)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+    }
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+    /*
+     * If the event is due to disconnect cmd from the host, only they the target
+     * would stop trying to connect. Under any other condition, target would
+     * keep trying to connect.
+     *
+     */
+    if( reason == DISCONNECT_CMD)
+    {
+        ar->arConnectPending = FALSE;
+        if (!ar->arUserBssFilter) {
+            wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+        }
+    } else {
+        ar->arConnectPending = TRUE;
+        if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
+            ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
+            ar->arConnected = TRUE;
+            return;
+        }
+    }
+
+    if (reason == NO_NETWORK_AVAIL)
+    {
+        bss_t *pWmiSsidnode = NULL;
+
+        /* remove the current associated bssid node */
+        wmi_free_node (ar->arWmi, bssid);
+
+        /*
+         * In case any other same SSID nodes are present
+         * remove it, since those nodes also not available now
+         */
+        do
+        {
+            /*
+             * Find the nodes based on SSID and remove it
+             * NOTE :: This case will not work out for Hidden-SSID
+             */
+            pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE);
+
+            if (pWmiSsidnode)
+            {
+                wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr);
+            }
+
+        }while (pWmiSsidnode);
+
+#if 0
+        /*
+         * Issuing a disconnect cmd prevent the firmware from
+         * continuing the scan and connect to the AP, if the AP
+         * cannot be found in 10 seconds. The user has to issue
+         * the iwconfig command again to connect to the AP.
+         * This change came in CL#575412 (EV# 59469) has to
+         * be fixed in a different way
+         */
+        ar6000_init_profile_info(ar);
+        wmi_disconnect_cmd(ar->arWmi);
+#endif
+    }
+
+    /* Update connect & link status atomically */
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected = FALSE;
+    netif_carrier_off(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+
+    if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
+        reconnect_flag = 0;
+    }
+
+#ifdef USER_KEYS
+    if (reason != CSERV_DISCONNECT)
+    {
+        ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+        ar->user_key_ctrl      = 0;
+    }
+#endif /* USER_KEYS */
+
+    netif_stop_queue(ar->arNetDev);
+    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+    ar->arBssChannel = 0;
+    ar->arBeaconInterval = 0;
+
+    ar6000_TxDataCleanup(ar);
+}
+
+void
+ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
+{
+    A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
+    ar->arRegCode = regCode;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+void
+ar6000_aggr_rcv_addba_req_evt(AR_SOFTC_T *ar, WMI_ADDBA_REQ_EVENT *evt)
+{
+    if(evt->status == 0) {
+        aggr_recv_addba_req_evt(ar->aggr_cntxt, evt->tid, evt->st_seq_no, evt->win_sz);
+    }
+}
+
+void
+ar6000_aggr_rcv_addba_resp_evt(AR_SOFTC_T *ar, WMI_ADDBA_RESP_EVENT *evt)
+{
+    A_PRINTF("ADDBA RESP. tid %d status %d, sz %d\n", evt->tid, evt->status, evt->amsdu_sz);
+    if(evt->status == 0) {
+    }
+}
+
+void
+ar6000_aggr_rcv_delba_req_evt(AR_SOFTC_T *ar, WMI_DELBA_EVENT *evt)
+{
+    aggr_recv_delba_req_evt(ar->aggr_cntxt, evt->tid);
+}
+#endif
+
+void
+ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd)
+{
+    void *osbuf = NULL;
+    A_INT8 i;
+    A_UINT8 size, *buf;
+    A_STATUS ret = A_OK;
+
+    size = cmd->evt_buf_sz + 4;
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+       ret = A_NO_MEMORY;
+       A_PRINTF("Error in allocating netbuf \n");
+       return;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+    buf = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+    /* First 2-bytes carry HCI event/ACL data type
+     * the next 2 are free
+     */
+    *((short *)buf) = WMI_HCI_EVENT_EVENTID;
+    buf += sizeof(int);
+    A_MEMCPY(buf, cmd->buf, cmd->evt_buf_sz);
+
+    ar6000_deliver_frames_to_nw_stack(ar->arNetDev, osbuf);
+    if(loghci) {
+        A_PRINTF_LOG("HCI Event From PAL <-- \n");
+        for(i = 0; i < cmd->evt_buf_sz; i++) {
+           A_PRINTF_LOG("0x%02x ", cmd->buf[i]);
+           if((i % 10) == 0) {
+               A_PRINTF_LOG("\n");
+           }
+        }
+        A_PRINTF_LOG("\n");
+        A_PRINTF_LOG("==================================\n");
+    }
+}
+
+void
+ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
+{
+#if WIRELESS_EXT >= 18
+    struct iw_pmkid_cand *pmkcand;
+#else /* WIRELESS_EXT >= 18 */
+    static const char *tag = "PRE-AUTH";
+    char buf[128];
+#endif /* WIRELESS_EXT >= 18 */
+
+    union iwreq_data wrqu;
+    int i;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("AR6000 Neighbor Report Event\n"));
+    for (i=0; i < numAps; info++, i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+            info->bssid[0], info->bssid[1], info->bssid[2],
+            info->bssid[3], info->bssid[4], info->bssid[5]));
+        if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("preauth-cap"));
+        }
+        if (info->bssFlags & WMI_PMKID_VALID_BSS) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,(" pmkid-valid\n"));
+            continue;           /* we skip bss if the pmkid is already valid */
+        }
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("\n"));
+        A_MEMZERO(&wrqu, sizeof(wrqu));
+#if WIRELESS_EXT >= 18
+        pmkcand = A_MALLOC_NOWAIT(sizeof(struct iw_pmkid_cand));
+        A_MEMZERO(pmkcand, sizeof(struct iw_pmkid_cand));
+        pmkcand->index = i;
+        pmkcand->flags = info->bssFlags;
+        A_MEMCPY(pmkcand->bssid.sa_data, info->bssid, ATH_MAC_LEN);
+        wrqu.data.length = sizeof(struct iw_pmkid_cand);
+        wireless_send_event(ar->arNetDev, IWEVPMKIDCAND, &wrqu, (char *)pmkcand);
+        A_FREE(pmkcand);
+#else /* WIRELESS_EXT >= 18 */
+        snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
+                 tag,
+                 info->bssid[0], info->bssid[1], info->bssid[2],
+                 info->bssid[3], info->bssid[4], info->bssid[5],
+                 i, info->bssFlags);
+        wrqu.data.length = strlen(buf);
+        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+#endif /* WIRELESS_EXT >= 18 */
+    }
+}
+
+void
+ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+    static const char *tag = "MLME-MICHAELMICFAILURE.indication";
+    char buf[128];
+    union iwreq_data wrqu;
+
+    /*
+     * For AP case, keyid will have aid of STA which sent pkt with
+     * MIC error. Use this aid to get MAC & send it to hostapd.
+     */
+    if (ar->arNetworkType == AP_NETWORK) {
+        sta_t *s = ieee80211_find_conn_for_aid(ar, (keyid >> 2));
+        if(!s){
+            A_PRINTF("AP TKIP MIC error received from Invalid aid / STA not found =%d\n", keyid);
+            return;
+        }
+        A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid);
+        snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
+            tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]);
+    } else {
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_tkip_micerr_event(ar, keyid, ismcast);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+        A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
+             keyid & 0x3, ismcast ? "multi": "uni");
+        snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid & 0x3,
+             ismcast ? "mult" : "un");
+    }
+
+    memset(&wrqu, 0, sizeof(wrqu));
+    wrqu.data.length = strlen(buf);
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+void
+ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+#ifdef ATH6K_CONFIG_CFG80211
+    ar6k_cfg80211_scanComplete_event(ar, status);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+    if (!ar->arUserBssFilter) {
+        wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+    }
+    if (!ar->scan_complete) {
+        if (status==A_OK) {
+            union iwreq_data wrqu;
+            A_MEMZERO(&wrqu, sizeof(wrqu));
+            wireless_send_event(ar->arNetDev, SIOCGIWSCAN, &wrqu, NULL);
+            ar->scan_complete = 1;
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,( "AR6000 scan complete: %d\n", status));
+}
+
+void
+ar6000_targetStats_event(AR_SOFTC_T *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+    A_UINT8 ac;
+
+    if(ar->arNetworkType == AP_NETWORK) {
+        WMI_AP_MODE_STAT *p = (WMI_AP_MODE_STAT *)ptr;
+        WMI_AP_MODE_STAT *ap = &ar->arAPStats;
+
+        if (len < sizeof(*p)) {
+            return;
+        }
+
+        for(ac=0;ac<AP_MAX_NUM_STA;ac++) {
+            ap->sta[ac].tx_bytes   += p->sta[ac].tx_bytes;
+            ap->sta[ac].tx_pkts    += p->sta[ac].tx_pkts;
+            ap->sta[ac].tx_error   += p->sta[ac].tx_error;
+            ap->sta[ac].tx_discard += p->sta[ac].tx_discard;
+            ap->sta[ac].rx_bytes   += p->sta[ac].rx_bytes;
+            ap->sta[ac].rx_pkts    += p->sta[ac].rx_pkts;
+            ap->sta[ac].rx_error   += p->sta[ac].rx_error;
+            ap->sta[ac].rx_discard += p->sta[ac].rx_discard;
+        }
+
+    } else {
+        WMI_TARGET_STATS *pTarget = (WMI_TARGET_STATS *)ptr;
+         TARGET_STATS *pStats = &ar->arTargetStats;
+
+        if (len < sizeof(*pTarget)) {
+            return;
+        }
+
+        // Update the RSSI of the connected bss.
+        if (ar->arConnected) {
+            bss_t *pConnBss = NULL;
+
+            pConnBss = wmi_find_node(ar->arWmi,ar->arBssid);
+            if (pConnBss)
+            {
+                pConnBss->ni_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
+                pConnBss->ni_snr = pTarget->cservStats.cs_aveBeacon_snr;
+                wmi_node_return(ar->arWmi, pConnBss);
+            }
+        }
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 updating target stats\n"));
+        pStats->tx_packets          += pTarget->txrxStats.tx_stats.tx_packets;
+        pStats->tx_bytes            += pTarget->txrxStats.tx_stats.tx_bytes;
+        pStats->tx_unicast_pkts     += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
+        pStats->tx_unicast_bytes    += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
+        pStats->tx_multicast_pkts   += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
+        pStats->tx_multicast_bytes  += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
+        pStats->tx_broadcast_pkts   += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
+        pStats->tx_broadcast_bytes  += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
+        pStats->tx_rts_success_cnt  += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
+        for(ac = 0; ac < WMM_NUM_AC; ac++)
+            pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
+        pStats->tx_errors           += pTarget->txrxStats.tx_stats.tx_errors;
+        pStats->tx_failed_cnt       += pTarget->txrxStats.tx_stats.tx_failed_cnt;
+        pStats->tx_retry_cnt        += pTarget->txrxStats.tx_stats.tx_retry_cnt;
+        pStats->tx_mult_retry_cnt   += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt;
+        pStats->tx_rts_fail_cnt     += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
+        pStats->tx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
+
+        pStats->rx_packets          += pTarget->txrxStats.rx_stats.rx_packets;
+        pStats->rx_bytes            += pTarget->txrxStats.rx_stats.rx_bytes;
+        pStats->rx_unicast_pkts     += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
+        pStats->rx_unicast_bytes    += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
+        pStats->rx_multicast_pkts   += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
+        pStats->rx_multicast_bytes  += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
+        pStats->rx_broadcast_pkts   += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
+        pStats->rx_broadcast_bytes  += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
+        pStats->rx_fragment_pkt     += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
+        pStats->rx_errors           += pTarget->txrxStats.rx_stats.rx_errors;
+        pStats->rx_crcerr           += pTarget->txrxStats.rx_stats.rx_crcerr;
+        pStats->rx_key_cache_miss   += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
+        pStats->rx_decrypt_err      += pTarget->txrxStats.rx_stats.rx_decrypt_err;
+        pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
+        pStats->rx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
+
+
+        pStats->tkip_local_mic_failure
+                                += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
+        pStats->tkip_counter_measures_invoked
+                                += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
+        pStats->tkip_replays        += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
+        pStats->tkip_format_errors  += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
+        pStats->ccmp_format_errors  += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
+        pStats->ccmp_replays        += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
+
+        pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
+        pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
+
+        pStats->cs_bmiss_cnt        += pTarget->cservStats.cs_bmiss_cnt;
+        pStats->cs_lowRssi_cnt      += pTarget->cservStats.cs_lowRssi_cnt;
+        pStats->cs_connect_cnt      += pTarget->cservStats.cs_connect_cnt;
+        pStats->cs_disconnect_cnt   += pTarget->cservStats.cs_disconnect_cnt;
+        pStats->cs_aveBeacon_snr    = pTarget->cservStats.cs_aveBeacon_snr;
+        pStats->cs_aveBeacon_rssi   = pTarget->cservStats.cs_aveBeacon_rssi;
+
+        if (enablerssicompensation) {
+            pStats->cs_aveBeacon_rssi =
+                    rssi_compensation_calc(ar, pStats->cs_aveBeacon_rssi);
+        }
+        pStats->cs_lastRoam_msec    = pTarget->cservStats.cs_lastRoam_msec;
+        pStats->cs_snr              = pTarget->cservStats.cs_snr;
+        pStats->cs_rssi             = pTarget->cservStats.cs_rssi;
+
+        pStats->lq_val              = pTarget->lqVal;
+
+        pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
+        pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
+        pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
+        pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
+        pStats->arp_received += pTarget->arpStats.arp_received;
+        pStats->arp_matched  += pTarget->arpStats.arp_matched;
+        pStats->arp_replied  += pTarget->arpStats.arp_replied;
+
+        if (ar->statsUpdatePending) {
+            ar->statsUpdatePending = FALSE;
+            wake_up(&arEvent);
+        }
+    }
+}
+
+void
+ar6000_rssiThreshold_event(AR_SOFTC_T *ar,  WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
+{
+    USER_RSSI_THOLD userRssiThold;
+
+    rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR;
+
+    if (enablerssicompensation) {
+        rssi = rssi_compensation_calc(ar, rssi);
+    }
+
+    /* Send an event to the app */
+    userRssiThold.tag = ar->rssi_map[newThreshold].tag;
+    userRssiThold.rssi = rssi;
+    A_PRINTF("rssi Threshold range = %d tag = %d  rssi = %d\n", newThreshold,
+             userRssiThold.tag, userRssiThold.rssi);
+
+    ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
+}
+
+
+void
+ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
+{
+    if (source == APP_HB_CHALLENGE) {
+        /* Report it to the app in case it wants a positive acknowledgement */
+        ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
+                                 (A_UINT8 *)&cookie, sizeof(cookie));
+    } else {
+        /* This would ignore the replys that come in after their due time */
+        if (cookie == ar->arHBChallengeResp.seqNum) {
+            ar->arHBChallengeResp.outstanding = FALSE;
+        }
+    }
+}
+
+
+void
+ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
+{
+    char    *errString[] = {
+                [WMI_TARGET_PM_ERR_FAIL]    "WMI_TARGET_PM_ERR_FAIL",
+                [WMI_TARGET_KEY_NOT_FOUND]  "WMI_TARGET_KEY_NOT_FOUND",
+                [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
+                [WMI_TARGET_BMISS]          "WMI_TARGET_BMISS",
+                [WMI_PSDISABLE_NODE_JOIN]   "WMI_PSDISABLE_NODE_JOIN"
+                };
+
+    A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
+
+    /* One error is reported at a time, and errorval is a bitmask */
+    if(errorVal & (errorVal - 1))
+       return;
+
+    A_PRINTF("AR6000 Error type = ");
+    switch(errorVal)
+    {
+        case WMI_TARGET_PM_ERR_FAIL:
+        case WMI_TARGET_KEY_NOT_FOUND:
+        case WMI_TARGET_DECRYPTION_ERR:
+        case WMI_TARGET_BMISS:
+        case WMI_PSDISABLE_NODE_JOIN:
+            A_PRINTF("%s\n", errString[errorVal]);
+            break;
+        default:
+            A_PRINTF("INVALID\n");
+            break;
+    }
+
+}
+
+
+void
+ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
+                 A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
+{
+    WMM_TSPEC_IE    *tspecIe;
+
+    /*
+     * This is the TSPEC IE suggestion from AP.
+     * Suggestion provided by AP under some error
+     * cases, could be helpful for the host app.
+     * Check documentation.
+     */
+    tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
+
+    /*
+     * What do we do, if we get TSPEC rejection? One thought
+     * that comes to mind is implictly delete the pstream...
+     */
+    A_PRINTF("AR6000 CAC notification. "
+                "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
+                 ac, cacIndication, statusCode);
+}
+
+void
+ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel,
+                            A_UINT16 newChannel)
+{
+    A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n",
+             oldChannel, newChannel);
+}
+
+#define AR6000_PRINT_BSSID(_pBss)  do {     \
+        A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
+                 (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
+                 (_pBss)[4],(_pBss)[5]);  \
+} while(0)
+
+void
+ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
+{
+    A_UINT8 i;
+
+    A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
+              pTbl->numEntries, pTbl->roamMode);
+    for (i= 0; i < pTbl->numEntries; i++) {
+        A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
+            pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
+            pTbl->bssRoamInfo[i].bssid[2],
+            pTbl->bssRoamInfo[i].bssid[3],
+            pTbl->bssRoamInfo[i].bssid[4],
+            pTbl->bssRoamInfo[i].bssid[5]);
+        A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
+                 " BIAS %d\n",
+            pTbl->bssRoamInfo[i].rssi,
+            pTbl->bssRoamInfo[i].rssidt,
+            pTbl->bssRoamInfo[i].last_rssi,
+            pTbl->bssRoamInfo[i].util,
+            pTbl->bssRoamInfo[i].roam_util,
+            pTbl->bssRoamInfo[i].bias);
+    }
+}
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
+{
+    A_UINT8 i,j;
+
+    /*Each event now contains exactly one filter, see bug 26613*/
+    A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num,                 wow_reply->num_filters);
+    A_PRINTF("wow mode = %s host mode = %s\n",
+            (wow_reply->wow_mode == 0? "disabled":"enabled"),
+            (wow_reply->host_mode == 1 ? "awake":"asleep"));
+
+
+    /*If there are no patterns, the reply will only contain generic
+      WoW information. Pattern information will exist only if there are
+      patterns present. Bug 26716*/
+
+   /* If this event contains pattern information, display it*/
+    if (wow_reply->this_filter_num) {
+        i=0;
+        A_PRINTF("id=%d size=%d offset=%d\n",
+                    wow_reply->wow_filters[i].wow_filter_id,
+                    wow_reply->wow_filters[i].wow_filter_size,
+                    wow_reply->wow_filters[i].wow_filter_offset);
+       A_PRINTF("wow pattern = ");
+       for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+             A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
+        }
+
+        A_PRINTF("\nwow mask = ");
+        for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+            A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
+        }
+        A_PRINTF("\n");
+    }
+}
+
+/*
+ * Report the Roaming related data collected on the target
+ */
+void
+ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
+{
+    A_PRINTF("Disconnect Data : BSSID: ");
+    AR6000_PRINT_BSSID(p->disassoc_bssid);
+    A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
+             p->disassoc_bss_rssi,p->disassoc_time,
+             p->no_txrx_time);
+    A_PRINTF("Connect Data: BSSID: ");
+    AR6000_PRINT_BSSID(p->assoc_bssid);
+    A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
+             p->assoc_bss_rssi,p->assoc_time,
+             p->allow_txrx_time);
+}
+
+void
+ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
+{
+    switch (p->roamDataType) {
+        case ROAM_DATA_TIME:
+            ar6000_display_roam_time(&p->u.roamTime);
+            break;
+        default:
+            break;
+    }
+}
+
+void
+ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
+{
+    struct sk_buff *skb;
+    WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
+
+
+    if (!ar->arMgmtFilter) {
+        return;
+    }
+    if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
+        (bih->frameType != BEACON_FTYPE))  ||
+        ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
+        (bih->frameType != PROBERESP_FTYPE)))
+    {
+        return;
+    }
+
+    if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
+
+        A_NETBUF_PUT(skb, len);
+        A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
+        skb->dev = ar->arNetDev;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+        A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6);
+#else
+        skb->mac.raw = A_NETBUF_DATA(skb);
+#endif
+        skb->ip_summed = CHECKSUM_NONE;
+        skb->pkt_type = PACKET_OTHERHOST;
+        skb->protocol = __constant_htons(0x0019);
+        netif_rx(skb);
+    }
+}
+
+A_UINT32 wmiSendCmdNum;
+
+A_STATUS
+ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+    AR_SOFTC_T       *ar = (AR_SOFTC_T *)devt;
+    A_STATUS         status = A_OK;
+    struct ar_cookie *cookie = NULL;
+    int i;
+#ifdef CONFIG_PM
+    if (ar->arWowState) {
+        A_NETBUF_FREE(osbuf);
+        return A_EACCES;
+    }
+#endif /* CONFIG_PM */
+        /* take lock to protect ar6000_alloc_cookie() */
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+    do {
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n",
+                         (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid));
+
+        if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) {
+                /* control endpoint is full, don't allocate resources, we
+                 * are just going to drop this packet */
+            cookie = NULL;
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" WMI Control EP full, dropping packet : 0x%X, len:%d \n",
+                    (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)));
+        } else {
+            cookie = ar6000_alloc_cookie(ar);
+        }
+
+        if (cookie == NULL) {
+            status = A_NO_MEMORY;
+            break;
+        }
+
+        if(logWmiRawMsgs) {
+            A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
+            for(i = 0; i < a_netbuf_to_len(osbuf); i++)
+                A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
+            A_PRINTF("\n");
+        }
+
+        wmiSendCmdNum++;
+
+    } while (FALSE);
+
+    if (cookie != NULL) {
+            /* got a structure to send it out on */
+        ar->arTxPending[eid]++;
+
+        if (eid != ar->arControlEp) {
+            ar->arTotalTxDataPending++;
+        }
+    }
+
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    if (cookie != NULL) {
+        cookie->arc_bp[0] = (A_UINT32)osbuf;
+        cookie->arc_bp[1] = 0;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(osbuf),
+                               A_NETBUF_LEN(osbuf),
+                               eid,
+                               AR6K_CONTROL_PKT_TAG);
+            /* this interface is asynchronous, if there is an error, cleanup will happen in the
+             * TX completion callback */
+        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+        status = A_OK;
+    }
+
+    if (status != A_OK) {
+        A_NETBUF_FREE(osbuf);
+    }
+    return status;
+}
+
+/* indicate tx activity or inactivity on a WMI stream */
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
+{
+    AR_SOFTC_T  *ar = (AR_SOFTC_T *)devt;
+    HTC_ENDPOINT_ID eid ;
+    int i;
+
+    if (ar->arWmiEnabled) {
+        eid = arAc2EndpointID(ar, TrafficClass);
+
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+        ar->arAcStreamActive[TrafficClass] = Active;
+
+        if (Active) {
+            /* when a stream goes active, keep track of the active stream with the highest priority */
+
+            if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) {
+                    /* set the new highest active priority */
+                ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass];
+            }
+
+        } else {
+            /* when a stream goes inactive, we may have to search for the next active stream
+             * that is the highest priority */
+
+            if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) {
+
+                /* the highest priority stream just went inactive */
+
+                    /* reset and search for the "next" highest "active" priority stream */
+                ar->arHiAcStreamActivePri = 0;
+                for (i = 0; i < WMM_NUM_AC; i++) {
+                    if (ar->arAcStreamActive[i]) {
+                        if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) {
+                            /* set the new highest active priority */
+                            ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i];
+                        }
+                    }
+                }
+            }
+        }
+
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+    } else {
+            /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
+             * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */
+        eid = (HTC_ENDPOINT_ID)TrafficClass;
+    }
+
+        /* notify HTC, this may cause credit distribution changes */
+
+    HTCIndicateActivityChange(ar->arHtcTarget,
+                              eid,
+                              Active);
+
+}
+
+void
+ar6000_btcoex_config_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+
+    WMI_BTCOEX_CONFIG_EVENT *pBtcoexConfig = (WMI_BTCOEX_CONFIG_EVENT *)ptr;
+    WMI_BTCOEX_CONFIG_EVENT *pArbtcoexConfig =&ar->arBtcoexConfig;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+    A_PRINTF("received config event\n");
+    pArbtcoexConfig->btProfileType = pBtcoexConfig->btProfileType;
+    pArbtcoexConfig->linkId = pBtcoexConfig->linkId;
+
+    switch (pBtcoexConfig->btProfileType) {
+        case WMI_BTCOEX_BT_PROFILE_SCO:
+            A_MEMCPY(&pArbtcoexConfig->info.scoConfigCmd, &pBtcoexConfig->info.scoConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_A2DP:
+            A_MEMCPY(&pArbtcoexConfig->info.a2dpConfigCmd, &pBtcoexConfig->info.a2dpConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_ACLCOEX:
+            A_MEMCPY(&pArbtcoexConfig->info.aclcoexConfig, &pBtcoexConfig->info.aclcoexConfig,
+                                        sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+            break;
+        case WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE:
+           A_MEMCPY(&pArbtcoexConfig->info.btinquiryPageConfigCmd, &pBtcoexConfig->info.btinquiryPageConfigCmd,
+                                        sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+            break;
+    }
+    if (ar->statsUpdatePending) {
+         ar->statsUpdatePending = FALSE;
+          wake_up(&arEvent);
+    }
+}
+
+void
+ar6000_btcoex_stats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len)
+{
+    WMI_BTCOEX_STATS_EVENT *pBtcoexStats = (WMI_BTCOEX_STATS_EVENT *)ptr;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+    A_MEMCPY(&ar->arBtcoexStats, pBtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT));
+
+    if (ar->statsUpdatePending) {
+         ar->statsUpdatePending = FALSE;
+        wake_up(&arEvent);
+    }
+
+}
+module_init(ar6000_init_module);
+module_exit(ar6000_cleanup_module);
+
+/* Init cookie queue */
+static void
+ar6000_cookie_init(AR_SOFTC_T *ar)
+{
+    A_UINT32    i;
+
+    ar->arCookieList = NULL;
+    ar->arCookieCount = 0;
+
+    A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
+
+    for (i = 0; i < MAX_COOKIE_NUM; i++) {
+        ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
+    }
+}
+
+/* cleanup cookie queue */
+static void
+ar6000_cookie_cleanup(AR_SOFTC_T *ar)
+{
+    /* It is gone .... */
+    ar->arCookieList = NULL;
+    ar->arCookieCount = 0;
+}
+
+/* Init cookie queue */
+static void
+ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
+{
+    /* Insert first */
+    A_ASSERT(ar != NULL);
+    A_ASSERT(cookie != NULL);
+
+    cookie->arc_list_next = ar->arCookieList;
+    ar->arCookieList = cookie;
+    ar->arCookieCount++;
+}
+
+/* cleanup cookie queue */
+static struct ar_cookie *
+ar6000_alloc_cookie(AR_SOFTC_T  *ar)
+{
+    struct ar_cookie   *cookie;
+
+    cookie = ar->arCookieList;
+    if(cookie != NULL)
+    {
+        ar->arCookieList = cookie->arc_list_next;
+        ar->arCookieCount--;
+    }
+
+    return cookie;
+}
+
+#ifdef SEND_EVENT_TO_APP
+/*
+ * This function is used to send event which come from taget to
+ * the application. The buf which send to application is include
+ * the event ID and event content.
+ */
+#define EVENT_ID_LEN   2
+void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+                              A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 15)
+
+/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
+
+    char *buf;
+    A_UINT16 size;
+    union iwreq_data wrqu;
+
+    size = len + EVENT_ID_LEN;
+
+    if (size > IW_CUSTOM_MAX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
+                eventId, size, IW_CUSTOM_MAX));
+        return;
+    }
+
+    buf = A_MALLOC_NOWAIT(size);
+    if (NULL == buf){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+        return;
+    }
+
+    A_MEMZERO(buf, size);
+    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+    //AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("event ID = %d,len = %d\n",*(A_UINT16*)buf, size));
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = size;
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+    A_FREE(buf);
+#endif
+
+
+}
+
+/*
+ * This function is used to send events larger than 256 bytes
+ * to the application. The buf which is sent to application
+ * includes the event ID and event content.
+ */
+void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+                                      A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 18)
+
+/* IWEVGENIE exists in wireless extensions version 18 onwards */
+
+    char *buf;
+    A_UINT16 size;
+    union iwreq_data wrqu;
+
+    size = len + EVENT_ID_LEN;
+
+    if (size > IW_GENERIC_IE_MAX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n",
+                        eventId, size, IW_GENERIC_IE_MAX));
+        return;
+    }
+
+    buf = A_MALLOC_NOWAIT(size);
+    if (NULL == buf){
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+        return;
+    }
+
+    A_MEMZERO(buf, size);
+    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = size;
+    wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf);
+
+    A_FREE(buf);
+
+#endif /* (WIRELESS_EXT >= 18) */
+
+}
+#endif /* SEND_EVENT_TO_APP */
+
+
+void
+ar6000_tx_retry_err_event(void *devt)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Tx retries reach maximum!\n"));
+}
+
+void
+ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
+{
+    WMI_SNR_THRESHOLD_EVENT event;
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    event.range = newThreshold;
+    event.snr = snr;
+
+    ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event,
+                             sizeof(WMI_SNR_THRESHOLD_EVENT));
+}
+
+void
+ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("lq threshold range %d, lq %d\n", newThreshold, lq));
+}
+
+
+
+A_UINT32
+a_copy_to_user(void *to, const void *from, A_UINT32 n)
+{
+    return(copy_to_user(to, from, n));
+}
+
+A_UINT32
+a_copy_from_user(void *to, const void *from, A_UINT32 n)
+{
+    return(copy_from_user(to, from, n));
+}
+
+
+A_STATUS
+ar6000_get_driver_cfg(struct net_device *dev,
+                        A_UINT16 cfgParam,
+                        void *result)
+{
+
+    A_STATUS    ret = 0;
+
+    switch(cfgParam)
+    {
+        case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
+           *((A_UINT32 *)result) = wlanNodeCaching;
+           break;
+        case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
+           *((A_UINT32 *)result) = logWmiRawMsgs;
+            break;
+        default:
+           ret = EINVAL;
+           break;
+    }
+
+    return ret;
+}
+
+void
+ar6000_keepalive_rx(void *devt, A_UINT8 configured)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+    ar->arKeepaliveConfigured = configured;
+    wake_up(&arEvent);
+}
+
+void
+ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList,
+                        A_UINT8 *bssidList)
+{
+    A_UINT8 i, j;
+
+    A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
+
+    for (i = 0; i < numPMKID; i++) {
+        A_PRINTF("\nBSSID %d ", i);
+            for (j = 0; j < ATH_MAC_LEN; j++) {
+                A_PRINTF("%2.2x", bssidList[j]);
+            }
+        bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN);
+        A_PRINTF("\nPMKID %d ", i);
+            for (j = 0; j < WMI_PMKID_LEN; j++) {
+                A_PRINTF("%2.2x", pmkidList->pmkid[j]);
+            }
+        pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN +
+                                  WMI_PMKID_LEN);
+    }
+}
+
+void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid)
+{
+    sta_t *conn=NULL;
+    A_BOOL isPsqEmpty = FALSE;
+
+    conn = ieee80211_find_conn_for_aid(ar, aid);
+
+    /* If the PS q for this STA is not empty, dequeue and send a pkt from
+     * the head of the q. Also update the More data bit in the WMI_DATA_HDR
+     * if there are more pkts for this STA in the PS q. If there are no more
+     * pkts for this STA, update the PVB for this STA.
+     */
+    A_MUTEX_LOCK(&conn->psqLock);
+    isPsqEmpty  = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+    A_MUTEX_UNLOCK(&conn->psqLock);
+
+    if (isPsqEmpty) {
+        /* TODO:No buffered pkts for this STA. Send out a NULL data frame */
+    } else {
+        struct sk_buff *skb = NULL;
+
+        A_MUTEX_LOCK(&conn->psqLock);
+        skb = A_NETBUF_DEQUEUE(&conn->psq);
+        A_MUTEX_UNLOCK(&conn->psqLock);
+        /* Set the STA flag to PSPolled, so that the frame will go out */
+        STA_SET_PS_POLLED(conn);
+        ar6000_data_tx(skb, ar->arNetDev);
+        STA_CLR_PS_POLLED(conn);
+
+        /* Clear the PVB for this STA if the queue has become empty */
+        A_MUTEX_LOCK(&conn->psqLock);
+        isPsqEmpty  = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+        A_MUTEX_UNLOCK(&conn->psqLock);
+
+        if (isPsqEmpty) {
+            wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+        }
+    }
+}
+
+void ar6000_dtimexpiry_event(AR_SOFTC_T *ar)
+{
+    A_BOOL isMcastQueued = FALSE;
+    struct sk_buff *skb = NULL;
+
+    /* If there are no associated STAs, ignore the DTIM expiry event.
+     * There can be potential race conditions where the last associated
+     * STA may disconnect & before the host could clear the 'Indicate DTIM'
+     * request to the firmware, the firmware would have just indicated a DTIM
+     * expiry event. The race is between 'clear DTIM expiry cmd' going
+     * from the host to the firmware & the DTIM expiry event happening from
+     * the firmware to the host.
+     */
+    if (ar->sta_list_index == 0) {
+        return;
+    }
+
+    A_MUTEX_LOCK(&ar->mcastpsqLock);
+    isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+    A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+    A_ASSERT(isMcastQueued == FALSE);
+
+    /* Flush the mcast psq to the target */
+    /* Set the STA flag to DTIMExpired, so that the frame will go out */
+    ar->DTIMExpired = TRUE;
+
+    A_MUTEX_LOCK(&ar->mcastpsqLock);
+    while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+        skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+        ar6000_data_tx(skb, ar->arNetDev);
+
+        A_MUTEX_LOCK(&ar->mcastpsqLock);
+    }
+    A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+    /* Reset the DTIMExpired flag back to 0 */
+    ar->DTIMExpired = FALSE;
+
+    /* Clear the LSB of the BitMapCtl field of the TIM IE */
+    wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+}
+
+void
+read_rssi_compensation_param(AR_SOFTC_T *ar)
+{
+    HIF_DEVICE *device= ar->arHifDevice;
+    A_UINT32 rssicomp;
+    A_UINT32 param;
+
+    if (BMIReadMemory(device,
+            HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data),
+            (A_UCHAR *)&rssicomp,
+            4)!= A_OK)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
+        return;
+    }
+
+    rssicomp += 0x40;
+    if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+        return ;
+    }
+    rssi_compensation_param.a_enable = (A_INT16) (param & 0xffff);
+    rssi_compensation_param.a_param_a = (A_INT16) (param >> 16);
+
+    rssicomp += 4;
+    if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+        return ;
+    }
+    rssi_compensation_param.a_param_b = (A_INT16) (param & 0xffff);
+    rssi_compensation_param.bg_enable = (A_INT16) (param >> 16);
+
+    rssicomp += 4;
+    if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+        return ;
+    }
+    rssi_compensation_param.bg_param_a = (A_INT16) (param & 0xffff);
+    rssi_compensation_param.bg_param_b = (A_INT16) (param >> 16);
+
+    if (rssi_compensation_param.bg_enable != 0x1)
+         rssi_compensation_param.bg_enable = 0;
+
+    if (rssi_compensation_param.a_enable != 0x1)
+         rssi_compensation_param.a_enable = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\
+        rssi_compensation_param.bg_enable,
+        rssi_compensation_param.bg_param_a,
+        rssi_compensation_param.bg_param_b));
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\
+        rssi_compensation_param.a_enable,
+        rssi_compensation_param.a_param_a,
+        rssi_compensation_param.a_param_b));
+
+    return ;
+}
+
+A_INT32
+rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt)
+{
+
+    if (freq > 5000)
+    {
+        if (rssi_compensation_param.a_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d, totalPkt = %d\n", rssi,totalPkt));
+            rssi = rssi * rssi_compensation_param.a_param_a + totalPkt * rssi_compensation_param.a_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.bg_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d, totalPkt = %d\n", rssi,totalPkt));
+            rssi = rssi * rssi_compensation_param.bg_param_a + totalPkt * rssi_compensation_param.bg_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+A_INT16
+rssi_compensation_calc(AR_SOFTC_T *ar, A_INT16 rssi)
+{
+    if (ar->arBssChannel > 5000)
+    {
+        if (rssi_compensation_param.a_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d\n", rssi));
+            rssi = rssi * rssi_compensation_param.a_param_a + rssi_compensation_param.a_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.bg_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation  = %d\n", rssi));
+            rssi = rssi * rssi_compensation_param.bg_param_a + rssi_compensation_param.bg_param_b;
+            rssi = (rssi-50) /100;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+A_INT16
+rssi_compensation_reverse_calc(AR_SOFTC_T *ar, A_INT16 rssi, A_BOOL Above)
+{
+    A_INT16 i;
+
+    if (ar->arBssChannel > 5000)
+    {
+        if (rssi_compensation_param.a_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation  = %d\n", rssi));
+            rssi = rssi * 100;
+            rssi = (rssi - rssi_compensation_param.a_param_b) / rssi_compensation_param.a_param_a;
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+        }
+    }
+    else
+    {
+        if (rssi_compensation_param.bg_enable)
+        {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation  = %d\n", rssi));
+
+            if (Above) {
+                for (i=95; i>=0; i--) {
+                    if (rssi <=  rssi_compensation_table[i]) {
+                        rssi = 0 - i;
+                        break;
+                    }
+                }
+            } else {
+                for (i=0; i<=95; i++) {
+                    if (rssi >=  rssi_compensation_table[i]) {
+                        rssi = 0 - i;
+                        break;
+                    }
+                }
+            }
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+        }
+    }
+
+    return rssi;
+}
+
+#ifdef WAPI_ENABLE
+void ap_wapi_rekey_event(AR_SOFTC_T *ar, A_UINT8 type, A_UINT8 *mac)
+{
+    union iwreq_data wrqu;
+    A_CHAR buf[20];
+
+    A_MEMZERO(buf, sizeof(buf));
+
+    strcpy(buf, "WAPI_REKEY");
+    buf[10] = type;
+    A_MEMCPY(&buf[11], mac, ATH_MAC_LEN);
+
+    A_MEMZERO(&wrqu, sizeof(wrqu));
+    wrqu.data.length = 10+1+ATH_MAC_LEN;
+    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+    A_PRINTF("WAPI REKEY - %d - %02x:%02x\n", type, mac[4], mac[5]);
+}
+#endif
+
+#ifdef USER_KEYS
+static A_STATUS
+
+ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
+{
+    A_STATUS status = A_OK;
+    struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
+    struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
+    CRYPTO_TYPE  keyType = ar->user_saved_keys.keyType;
+
+    if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            goto _reinstall_keys_out;
+        }
+
+        if (uik->ik_keylen) {
+            status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
+                    ar->user_saved_keys.keyType, PAIRWISE_USAGE,
+                    uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
+                    uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG);
+        }
+
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
+    }
+
+    if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            goto _reinstall_keys_out;
+        }
+
+        if (bik->ik_keylen) {
+            status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
+                    ar->user_saved_keys.keyType, GROUP_USAGE,
+                    bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
+                    bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG);
+        }
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
+    }
+
+_reinstall_keys_out:
+    ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+    ar->user_key_ctrl      = 0;
+
+    return status;
+}
+#endif /* USER_KEYS */
+
+
+void
+ar6000_dset_open_req(
+    void *context,
+    A_UINT32 id,
+    A_UINT32 targHandle,
+    A_UINT32 targReplyFn,
+    A_UINT32 targReplyArg)
+{
+}
+
+void
+ar6000_dset_close(
+    void *context,
+    A_UINT32 access_cookie)
+{
+    return;
+}
+
+void
+ar6000_dset_data_req(
+   void *context,
+   A_UINT32 accessCookie,
+   A_UINT32 offset,
+   A_UINT32 length,
+   A_UINT32 targBuf,
+   A_UINT32 targReplyFn,
+   A_UINT32 targReplyArg)
+{
+}
+
+int
+ar6000_ap_mode_profile_commit(struct ar6_softc *ar)
+{
+    WMI_CONNECT_CMD p;
+    unsigned long  flags;
+
+    /* No change in AP's profile configuration */
+    if(ar->ap_profile_flag==0) {
+        A_PRINTF("COMMIT: No change in profile!!!\n");
+        return -ENODATA;
+    }
+
+    if(!ar->arSsidLen) {
+        A_PRINTF("SSID not set!!!\n");
+        return -ECHRNG;
+    }
+
+    switch(ar->arAuthMode) {
+    case NONE_AUTH:
+        if((ar->arPairwiseCrypto != NONE_CRYPT) &&
+#ifdef WAPI_ENABLE
+           (ar->arPairwiseCrypto != WAPI_CRYPT) &&
+#endif
+           (ar->arPairwiseCrypto != WEP_CRYPT)) {
+            A_PRINTF("Cipher not supported in AP mode Open auth\n");
+            return -EOPNOTSUPP;
+        }
+        break;
+    case WPA_PSK_AUTH:
+    case WPA2_PSK_AUTH:
+    case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+        break;
+    default:
+        A_PRINTF("This key mgmt type not supported in AP mode\n");
+        return -EOPNOTSUPP;
+    }
+
+    /* Update the arNetworkType */
+    ar->arNetworkType = ar->arNextMode;
+
+    A_MEMZERO(&p,sizeof(p));
+    p.ssidLength = ar->arSsidLen;
+    A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength);
+    p.channel = ar->arChannelHint;
+    p.networkType = ar->arNetworkType;
+
+    p.dot11AuthMode = ar->arDot11AuthMode;
+    p.authMode = ar->arAuthMode;
+    p.pairwiseCryptoType = ar->arPairwiseCrypto;
+    p.pairwiseCryptoLen = ar->arPairwiseCryptoLen;
+    p.groupCryptoType = ar->arGroupCrypto;
+    p.groupCryptoLen = ar->arGroupCryptoLen;
+    p.ctrl_flags = ar->arConnectCtrlFlags;
+
+    ar->arConnected = FALSE;
+
+    wmi_ap_profile_commit(ar->arWmi, &p);
+    spin_lock_irqsave(&ar->arLock, flags);
+    ar->arConnected  = TRUE;
+    netif_carrier_on(ar->arNetDev);
+    spin_unlock_irqrestore(&ar->arLock, flags);
+    ar->ap_profile_flag = 0;
+    return 0;
+}
+
+
+A_STATUS
+ar6000_connect_to_ap(struct ar6_softc *ar)
+{
+    /* The ssid length check prevents second "essid off" from the user,
+       to be treated as a connect cmd. The second "essid off" is ignored.
+    */
+    if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) && ar->arNetworkType!=AP_NETWORK)
+    {
+        A_STATUS status;
+        if((ADHOC_NETWORK != ar->arNetworkType) &&
+           (NONE_AUTH==ar->arAuthMode)          &&
+           (WEP_CRYPT==ar->arPairwiseCrypto)) {
+                ar6000_install_static_wep_keys(ar);
+        }
+
+        if (!ar->arUserBssFilter) {
+            if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+                return -EIO;
+            }
+        }
+#ifdef WAPI_ENABLE
+        if (ar->arWapiEnable)  {
+            ar->arPairwiseCrypto = WAPI_CRYPT;
+            ar->arPairwiseCryptoLen = 0;
+            ar->arGroupCrypto = WAPI_CRYPT;
+            ar->arGroupCryptoLen = 0;
+            ar->arAuthMode = NONE_AUTH;
+            ar->arConnectCtrlFlags |= CONNECT_IGNORE_WPAx_GROUP_CIPHER;
+        }
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Connect called with authmode %d dot11 auth %d"\
+                        " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                        " GRP crypto Len %d\n",
+                        ar->arAuthMode, ar->arDot11AuthMode,
+                        ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                        ar->arGroupCrypto, ar->arGroupCryptoLen));
+        reconnect_flag = 0;
+        /* Set the listen interval into 1000TUs. This value will be indicated to Ap in the conn.
+           later set it back locally at the STA to 100/1000 TUs depending on the power mode */
+        if ((ar->arNetworkType == INFRA_NETWORK)) {
+            wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0);
+        }
+        status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                                 ar->arDot11AuthMode, ar->arAuthMode,
+                                 ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                                 ar->arGroupCrypto,ar->arGroupCryptoLen,
+                                 ar->arSsidLen, ar->arSsid,
+                                 ar->arReqBssid, ar->arChannelHint,
+                                 ar->arConnectCtrlFlags);
+        if (status != A_OK) {
+            wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0);
+            if (!ar->arUserBssFilter) {
+                wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+            }
+            return status;
+        }
+
+        if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+            ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+        {
+            A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+        }
+
+        ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+        
+        ar->arConnectPending = TRUE;
+        return status;    
+    }
+    return A_ERROR;
+}
+
+A_STATUS 
+ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
+{
+    A_STATUS status = A_OK;
+    AR6000_WLAN_STATE oldstate = ar->arWlanState;
+    if (ar->arWmiReady == FALSE || 
+        (state!=WLAN_DISABLED && state!=WLAN_ENABLED)) {
+        return A_ERROR;
+    }
+    if (state == ar->arWlanState) {
+        return A_OK;
+    }
+    ar->arWlanState = state;
+    do {
+        if (ar->arWlanState == WLAN_ENABLED) {
+            /* Enable foreground scanning */
+            if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
+                                   ar->scParams.fg_end_period,
+                                   ar->scParams.bg_period,
+                                   ar->scParams.minact_chdwell_time,
+                                   ar->scParams.maxact_chdwell_time,
+                                   ar->scParams.pas_chdwell_time,
+                                   ar->scParams.shortScanRatio,
+                                   ar->scParams.scanCtrlFlags,
+                                   ar->scParams.max_dfsch_act_time,
+                                   ar->scParams.maxact_scan_per_ssid) != A_OK) {
+               status = A_ERROR;
+               break;
+            }
+            if (ar->arSsidLen) {
+                if (ar6000_connect_to_ap(ar) != A_OK) {
+                    status = A_ERROR;
+                    break;
+                }
+            }
+        } else {
+            /* Disconnect from the AP and disable foreground scanning */
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                wmi_disconnect_cmd(ar->arWmi);
+            } else {
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+    
+            if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0) != A_OK) {
+               status = A_ERROR;
+               break;
+            }
+        }
+    } while (0);
+    if (status!=A_OK) {
+        ar->arWlanState = oldstate;
+    }
+    return status;
+}
+
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie)
+{
+    sta_t *conn = NULL;
+    conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr);
+
+    A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE);
+    A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE);
+
+    if(conn) {
+        A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE);
+    }
+
+    return 0;
+}
+
+A_STATUS
+is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd)
+{
+    if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) {
+        cmd -= SIOCSIWCOMMIT;
+        if(sioctl_filter[cmd] == 0xFF) return A_OK;
+        if(sioctl_filter[cmd] & mode) return A_OK;
+    } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) {
+        cmd -= SIOCIWFIRSTPRIV;
+        if(pioctl_filter[cmd] == 0xFF) return A_OK;
+        if(pioctl_filter[cmd] & mode) return A_OK;
+    } else {
+        return A_ERROR;
+    }
+    return A_ENOTSUP;
+}
+
+A_STATUS
+is_xioctl_allowed(A_UINT8 mode, int cmd)
+{
+    if(sizeof(xioctl_filter)-1 < cmd) {
+        A_PRINTF("Filter for this cmd=%d not defined\n",cmd);
+        return 0;
+    }
+    if(xioctl_filter[cmd] == 0xFF) return A_OK;
+    if(xioctl_filter[cmd] & mode) return A_OK;
+    return A_ERROR;
+}
+
+#ifdef WAPI_ENABLE
+int
+ap_set_wapi_key(struct ar6_softc *ar, void *ikey)
+{
+    struct ieee80211req_key *ik = (struct ieee80211req_key *)ikey;
+    KEY_USAGE   keyUsage = 0;
+    A_STATUS    status;
+
+    if (A_MEMCMP(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN) == 0) {
+        keyUsage = GROUP_USAGE;
+    } else {
+        keyUsage = PAIRWISE_USAGE;
+    }
+    A_PRINTF("WAPI_KEY: Type:%d ix:%d mac:%02x:%02x len:%d\n",
+        keyUsage, ik->ik_keyix, ik->ik_macaddr[4], ik->ik_macaddr[5],
+        ik->ik_keylen);
+
+    status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, WAPI_CRYPT, keyUsage,
+                            ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                            ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                            SYNC_BOTH_WMIFLAG);
+
+    if (A_OK != status) {
+        return -EIO;
+    }
+    return 0;
+}
+#endif
+
+void ar6000_peer_event(
+    void *context,
+    A_UINT8 eventCode,
+    A_UINT8 *macAddr)
+{
+    A_UINT8 pos;
+
+    for (pos=0;pos<6;pos++)
+        printk("%02x: ",*(macAddr+pos));
+    printk("\n");
+}
+
+#ifdef HTC_TEST_SEND_PKTS
+#define HTC_TEST_DUPLICATE 8
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *dupskb)
+{
+    struct ar_cookie *cookie;
+    struct ar_cookie *cookieArray[HTC_TEST_DUPLICATE];
+    struct sk_buff   *new_skb;
+    int    i;
+    int    pkts = 0;
+    HTC_PACKET_QUEUE pktQueue;
+    EPPING_HEADER    *eppingHdr;
+
+    eppingHdr = A_NETBUF_DATA(dupskb);
+
+    if (eppingHdr->Cmd_h == EPPING_CMD_NO_ECHO) {
+        /* skip test if this is already a tx perf test */
+        return;
+    }
+
+    for (i = 0; i < HTC_TEST_DUPLICATE; i++,pkts++) {
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        cookie = ar6000_alloc_cookie(ar);
+        if (cookie != NULL) {
+            ar->arTxPending[eid]++;
+            ar->arTotalTxDataPending++;
+        }
+
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+        if (NULL == cookie) {
+            break;
+        }
+
+        new_skb = A_NETBUF_ALLOC(A_NETBUF_LEN(dupskb));
+
+        if (new_skb == NULL) {
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+            ar6000_free_cookie(ar,cookie);
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            break;
+        }
+
+        A_NETBUF_PUT_DATA(new_skb, A_NETBUF_DATA(dupskb), A_NETBUF_LEN(dupskb));
+        cookie->arc_bp[0] = (A_UINT32)new_skb;
+        cookie->arc_bp[1] = MapNo;
+        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+                               cookie,
+                               A_NETBUF_DATA(new_skb),
+                               A_NETBUF_LEN(new_skb),
+                               eid,
+                               AR6K_DATA_PKT_TAG);
+
+        cookieArray[i] = cookie;
+
+        {
+            EPPING_HEADER *pHdr = (EPPING_HEADER *)A_NETBUF_DATA(new_skb);
+            pHdr->Cmd_h = EPPING_CMD_NO_ECHO;  /* do not echo the packet */
+        }
+    }
+
+    if (pkts == 0) {
+        return;
+    }
+
+    INIT_HTC_PACKET_QUEUE(&pktQueue);
+
+    for (i = 0; i < pkts; i++) {
+        HTC_PACKET_ENQUEUE(&pktQueue,&cookieArray[i]->HtcPkt);
+    }
+
+    HTCSendPktsMultiple(ar->arHtcTarget, &pktQueue);
+
+}
+
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(setupbtdev);
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c
new file mode 100644
index 000000000000..62f5f2158c18
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c
@@ -0,0 +1,455 @@
+/*
+ * 
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ * 
+ */
+
+#include "ar6000_drv.h"
+
+#ifdef HTC_RAW_INTERFACE
+
+static void
+ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T        *ar = (AR_SOFTC_T *)Context;
+    raw_htc_buffer    *busy;
+    HTC_RAW_STREAM_ID streamID; 
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    busy = (raw_htc_buffer *)pPacket->pPktContext;
+    A_ASSERT(busy != NULL);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /*
+         * HTC provides A_ECANCELED status when it doesn't want to be refilled
+         * (probably due to a shutdown)
+         */
+        return;
+    }
+
+    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+    
+#ifdef CF
+   if (down_trylock(&arRaw->raw_htc_read_sem[streamID])) {
+#else
+    if (down_interruptible(&arRaw->raw_htc_read_sem[streamID])) {
+#endif /* CF */
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+    }
+
+    A_ASSERT((pPacket->Status != A_OK) || 
+             (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
+
+    busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
+    busy->currPtr = HTC_HEADER_LEN;
+    arRaw->read_buffer_available[streamID] = TRUE;
+    //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("raw read cb:  0x%X 0x%X \n", busy->currPtr,busy->length);
+    up(&arRaw->raw_htc_read_sem[streamID]);
+
+    /* Signal the waiting process */
+    AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) read process\n", streamID));
+    wake_up_interruptible(&arRaw->raw_htc_read_queue[streamID]);
+}
+
+static void
+ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
+{
+    AR_SOFTC_T          *ar = (AR_SOFTC_T  *)Context;
+    raw_htc_buffer      *free;
+    HTC_RAW_STREAM_ID   streamID;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    
+    free = (raw_htc_buffer *)pPacket->pPktContext;
+    A_ASSERT(free != NULL);
+
+    if (pPacket->Status == A_ECANCELED) {
+        /*
+         * HTC provides A_ECANCELED status when it doesn't want to be refilled
+         * (probably due to a shutdown)
+         */
+        return;
+    }
+
+    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+    
+#ifdef CF
+    if (down_trylock(&arRaw->raw_htc_write_sem[streamID])) {
+#else
+    if (down_interruptible(&arRaw->raw_htc_write_sem[streamID])) {
+#endif
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+    }
+
+    A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
+
+    free->length = 0;
+    arRaw->write_buffer_available[streamID] = TRUE;
+    up(&arRaw->raw_htc_write_sem[streamID]);
+
+    /* Signal the waiting process */
+    AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) write process\n", streamID));
+    wake_up_interruptible(&arRaw->raw_htc_write_queue[streamID]);
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T        *ar,
+                                           HTC_RAW_STREAM_ID StreamID)
+{
+    A_STATUS                 status;
+    HTC_SERVICE_CONNECT_RESP response;
+    A_UINT8                  streamNo;
+    HTC_SERVICE_CONNECT_REQ  connect;
+    
+    do {      
+        
+        A_MEMZERO(&connect,sizeof(connect));
+            /* pass the stream ID as meta data to the RAW streams service */
+        streamNo = (A_UINT8)StreamID;
+        connect.pMetaData = &streamNo;
+        connect.MetaDataLength = sizeof(A_UINT8);
+            /* these fields are the same for all endpoints */
+        connect.EpCallbacks.pContext = ar;
+        connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;   
+        connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;   
+            /* simple interface, we don't need these optional callbacks */      
+        connect.EpCallbacks.EpRecvRefill = NULL;
+        connect.EpCallbacks.EpSendFull = NULL;
+        connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;  
+        
+            /* connect to the raw streams service, we may be able to get 1 or more
+             * connections, depending on WHAT is running on the target */
+        connect.ServiceID = HTC_RAW_STREAMS_SVC;
+        
+        A_MEMZERO(&response,sizeof(response));
+        
+            /* try to connect to the raw stream, it is okay if this fails with 
+             * status HTC_SERVICE_NO_MORE_EP */
+        status = HTCConnectService(ar->arHtcTarget, 
+                                   &connect,
+                                   &response);
+        
+        if (A_FAILED(status)) {
+            if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTC RAW , No more streams allowed \n"));
+                status = A_OK;    
+            }
+            break;    
+        }
+
+            /* set endpoint mapping for the RAW HTC streams */
+        arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("HTC RAW : stream ID: %d, endpoint: %d\n", 
+                        StreamID, arRawStream2EndpointID(ar,StreamID)));
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar)
+{
+    A_STATUS status;
+    int streamID, endPt, count2;
+    raw_htc_buffer *buffer;
+    HTC_SERVICE_ID servicepriority;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    if (!arRaw) {
+        arRaw = ar->arRawHtc = A_MALLOC(sizeof(AR_RAW_HTC_T));
+        if (arRaw) {
+            A_MEMZERO(arRaw, sizeof(AR_RAW_HTC_T));
+        }
+    }
+    A_ASSERT(ar->arHtcTarget != NULL);
+    if (!arRaw) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Faile to allocate memory for HTC RAW interface\n"));
+        return -ENOMEM;
+    }
+    /* wait for target */
+    status = HTCWaitTarget(ar->arHtcTarget);
+        
+    if (A_FAILED(status)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTCWaitTarget failed (%d)\n", status));
+        return -ENODEV;  
+    }
+    
+    for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
+        arRaw->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
+    }
+        
+    for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
+        /* Initialize the data structures */
+        init_MUTEX(&arRaw->raw_htc_read_sem[streamID]);
+        init_MUTEX(&arRaw->raw_htc_write_sem[streamID]);
+        init_waitqueue_head(&arRaw->raw_htc_read_queue[streamID]);
+        init_waitqueue_head(&arRaw->raw_htc_write_queue[streamID]);
+
+            /* try to connect to the raw service */
+        status = ar6000_connect_raw_service(ar,streamID);
+        
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (arRawStream2EndpointID(ar,streamID) == 0) {
+            break;    
+        }
+        
+        for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
+            /* Initialize the receive buffers */
+            buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+            buffer = &arRaw->raw_htc_read_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+            
+            SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
+                                          buffer,
+                                          buffer->data,
+                                          HTC_RAW_BUFFER_SIZE,
+                                          arRawStream2EndpointID(ar,streamID));
+            
+            /* Queue buffers to HTC for receive */
+            if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
+            {
+                BMIInit();
+                return -EIO;
+            }
+        }
+
+        for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
+            /* Initialize the receive buffers */
+            buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+            memset(buffer, 0, sizeof(raw_htc_buffer));
+        }
+
+        arRaw->read_buffer_available[streamID] = FALSE;
+        arRaw->write_buffer_available[streamID] = TRUE;
+    }
+    
+    if (A_FAILED(status)) {
+        return -EIO;    
+    }
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("HTC RAW, number of streams the target supports: %d \n", streamID));
+            
+    servicepriority = HTC_RAW_STREAMS_SVC;  /* only 1 */
+    
+        /* set callbacks and priority list */
+    HTCSetCreditDistribution(ar->arHtcTarget,
+                             ar,
+                             NULL,  /* use default */
+                             NULL,  /* use default */
+                             &servicepriority,
+                             1);
+
+    /* Start the HTC component */
+    if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
+        BMIInit();
+        return -EIO;
+    }
+
+    (ar)->arRawIfInit = TRUE;
+    
+    return 0;
+}
+
+int ar6000_htc_raw_close(AR_SOFTC_T *ar)
+{
+    A_PRINTF("ar6000_htc_raw_close called \n");
+    HTCStop(ar->arHtcTarget);
+    
+        /* reset the device */
+    ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, FALSE);
+    /* Initialize the BMI component */
+    BMIInit();
+
+    if (ar->arRawHtc) {
+        A_FREE(ar->arRawHtc);
+        ar->arRawHtc = NULL;
+    }
+    return 0;
+}
+
+raw_htc_buffer *
+get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
+{
+    int count;
+    raw_htc_buffer *busy;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    /* Check for data */
+    for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
+        busy = &arRaw->raw_htc_read_buffer[StreamID][count];
+        if (busy->length) {
+            break;
+        }
+    }
+    if (busy->length) {
+        arRaw->read_buffer_available[StreamID] = TRUE;
+    } else {
+        arRaw->read_buffer_available[StreamID] = FALSE;
+    }
+
+    return busy;
+}
+
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, 
+                            char __user *buffer, size_t length)
+{
+    int readPtr;
+    raw_htc_buffer *busy;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    if (arRawStream2EndpointID(ar,StreamID) == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+        return -EFAULT;    
+    }
+    
+    if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+        return -ERESTARTSYS;
+    }
+
+    busy = get_filled_buffer(ar,StreamID);
+    while (!arRaw->read_buffer_available[StreamID]) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+
+        /* Wait for the data */
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) read process\n", StreamID));
+        if (wait_event_interruptible(arRaw->raw_htc_read_queue[StreamID],
+                                     arRaw->read_buffer_available[StreamID]))
+        {
+            return -EINTR;
+        }
+        if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+            return -ERESTARTSYS;
+        }
+        busy = get_filled_buffer(ar,StreamID);
+    }
+
+    /* Read the data */
+    readPtr = busy->currPtr;
+    if (length > busy->length - HTC_HEADER_LEN) {
+        length = busy->length - HTC_HEADER_LEN;
+    }
+    if (copy_to_user(buffer, &busy->data[readPtr], length)) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+        return -EFAULT;
+    }
+
+    busy->currPtr += length;
+        
+    if (busy->currPtr == busy->length)
+    {    
+        busy->currPtr = 0;
+        busy->length = 0;        
+        HTC_PACKET_RESET_RX(&busy->HTCPacket);                                          
+        //AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("raw read ioctl:  ep for packet:%d \n", busy->HTCPacket.Endpoint));
+        HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
+    }
+    arRaw->read_buffer_available[StreamID] = FALSE;
+    up(&arRaw->raw_htc_read_sem[StreamID]);
+
+    return length;
+}
+
+static raw_htc_buffer *
+get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
+{
+    int count;
+    raw_htc_buffer *free;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+    free = NULL;
+    for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
+        free = &arRaw->raw_htc_write_buffer[StreamID][count];
+        if (free->length == 0) {
+            break;
+        }
+    }
+    if (!free->length) {
+        arRaw->write_buffer_available[StreamID] = TRUE;
+    } else {
+        arRaw->write_buffer_available[StreamID] = FALSE;
+    }
+
+    return free;
+}
+
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+                     char __user *buffer, size_t length)
+{
+    int writePtr;
+    raw_htc_buffer *free;
+    AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+    if (arRawStream2EndpointID(ar,StreamID) == 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+        return -EFAULT;    
+    }
+    
+    if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+        return -ERESTARTSYS;
+    }
+
+    /* Search for a free buffer */
+    free = get_free_buffer(ar,StreamID);
+
+    /* Check if there is space to write else wait */
+    while (!arRaw->write_buffer_available[StreamID]) {
+        up(&arRaw->raw_htc_write_sem[StreamID]);
+
+        /* Wait for buffer to become free */
+        AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) write process\n", StreamID));
+        if (wait_event_interruptible(arRaw->raw_htc_write_queue[StreamID],
+                                     arRaw->write_buffer_available[StreamID]))
+        {
+            return -EINTR;
+        }
+        if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+            return -ERESTARTSYS;
+        }
+        free = get_free_buffer(ar,StreamID);
+    }
+
+    /* Send the data */
+    writePtr = HTC_HEADER_LEN;
+    if (length > (HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN)) {
+        length = HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN;
+    }
+
+    if (copy_from_user(&free->data[writePtr], buffer, length)) {
+        up(&arRaw->raw_htc_read_sem[StreamID]);
+        return -EFAULT;
+    }
+
+    free->length = length;
+        
+    SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
+                           free,
+                           &free->data[writePtr],
+                           length,
+                           arRawStream2EndpointID(ar,StreamID),
+                           AR6K_DATA_PKT_TAG);
+    
+    HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
+    
+    arRaw->write_buffer_available[StreamID] = FALSE;
+    up(&arRaw->raw_htc_write_sem[StreamID]);
+
+    return length;
+}
+#endif /* HTC_RAW_INTERFACE */
diff --git a/drivers/net/wireless/ath6kl/os/linux/cfg80211.c b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c
new file mode 100644
index 000000000000..402f98931b46
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c
@@ -0,0 +1,1467 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <net/cfg80211.h>
+
+#include "ar6000_drv.h"
+
+
+extern A_WAITQUEUE_HEAD arEvent;
+extern unsigned int wmitimeout;
+extern int reconnect_flag;
+
+
+#define RATETAB_ENT(_rate, _rateid, _flags) {   \
+    .bitrate    = (_rate),                  \
+    .flags      = (_flags),                 \
+    .hw_value   = (_rateid),                \
+}
+
+#define CHAN2G(_channel, _freq, _flags) {   \
+    .band           = IEEE80211_BAND_2GHZ,  \
+    .hw_value       = (_channel),           \
+    .center_freq    = (_freq),              \
+    .flags          = (_flags),             \
+    .max_antenna_gain   = 0,                \
+    .max_power      = 30,                   \
+}
+
+#define CHAN5G(_channel, _flags) {              \
+    .band           = IEEE80211_BAND_5GHZ,      \
+    .hw_value       = (_channel),               \
+    .center_freq    = 5000 + (5 * (_channel)),  \
+    .flags          = (_flags),                 \
+    .max_antenna_gain   = 0,                    \
+    .max_power      = 30,                       \
+}
+
+static struct
+ieee80211_rate ar6k_rates[] = {
+    RATETAB_ENT(10,  0x1,   0),
+    RATETAB_ENT(20,  0x2,   0),
+    RATETAB_ENT(55,  0x4,   0),
+    RATETAB_ENT(110, 0x8,   0),
+    RATETAB_ENT(60,  0x10,  0),
+    RATETAB_ENT(90,  0x20,  0),
+    RATETAB_ENT(120, 0x40,  0),
+    RATETAB_ENT(180, 0x80,  0),
+    RATETAB_ENT(240, 0x100, 0),
+    RATETAB_ENT(360, 0x200, 0),
+    RATETAB_ENT(480, 0x400, 0),
+    RATETAB_ENT(540, 0x800, 0),
+};
+
+#define ar6k_a_rates     (ar6k_rates + 4)
+#define ar6k_a_rates_size    8
+#define ar6k_g_rates     (ar6k_rates + 0)
+#define ar6k_g_rates_size    12
+
+static struct
+ieee80211_channel ar6k_2ghz_channels[] = {
+    CHAN2G(1, 2412, 0),
+    CHAN2G(2, 2417, 0),
+    CHAN2G(3, 2422, 0),
+    CHAN2G(4, 2427, 0),
+    CHAN2G(5, 2432, 0),
+    CHAN2G(6, 2437, 0),
+    CHAN2G(7, 2442, 0),
+    CHAN2G(8, 2447, 0),
+    CHAN2G(9, 2452, 0),
+    CHAN2G(10, 2457, 0),
+    CHAN2G(11, 2462, 0),
+    CHAN2G(12, 2467, 0),
+    CHAN2G(13, 2472, 0),
+    CHAN2G(14, 2484, 0),
+};
+
+static struct
+ieee80211_channel ar6k_5ghz_a_channels[] = {
+    CHAN5G(34, 0),      CHAN5G(36, 0),
+    CHAN5G(38, 0),      CHAN5G(40, 0),
+    CHAN5G(42, 0),      CHAN5G(44, 0),
+    CHAN5G(46, 0),      CHAN5G(48, 0),
+    CHAN5G(52, 0),      CHAN5G(56, 0),
+    CHAN5G(60, 0),      CHAN5G(64, 0),
+    CHAN5G(100, 0),     CHAN5G(104, 0),
+    CHAN5G(108, 0),     CHAN5G(112, 0),
+    CHAN5G(116, 0),     CHAN5G(120, 0),
+    CHAN5G(124, 0),     CHAN5G(128, 0),
+    CHAN5G(132, 0),     CHAN5G(136, 0),
+    CHAN5G(140, 0),     CHAN5G(149, 0),
+    CHAN5G(153, 0),     CHAN5G(157, 0),
+    CHAN5G(161, 0),     CHAN5G(165, 0),
+    CHAN5G(184, 0),     CHAN5G(188, 0),
+    CHAN5G(192, 0),     CHAN5G(196, 0),
+    CHAN5G(200, 0),     CHAN5G(204, 0),
+    CHAN5G(208, 0),     CHAN5G(212, 0),
+    CHAN5G(216, 0),
+};
+
+static struct
+ieee80211_supported_band ar6k_band_2ghz = {
+    .n_channels = ARRAY_SIZE(ar6k_2ghz_channels),
+    .channels = ar6k_2ghz_channels,
+    .n_bitrates = ar6k_g_rates_size,
+    .bitrates = ar6k_g_rates,
+};
+
+static struct
+ieee80211_supported_band ar6k_band_5ghz = {
+    .n_channels = ARRAY_SIZE(ar6k_5ghz_a_channels),
+    .channels = ar6k_5ghz_a_channels,
+    .n_bitrates = ar6k_a_rates_size,
+    .bitrates = ar6k_a_rates,
+};
+
+static int
+ar6k_set_wpa_version(AR_SOFTC_T *ar, enum nl80211_wpa_versions wpa_version)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: %u\n", __func__, wpa_version));
+
+    if (!wpa_version) {
+        ar->arAuthMode = NONE_AUTH;
+    } else if (wpa_version & NL80211_WPA_VERSION_1) {
+        ar->arAuthMode = WPA_AUTH;
+    } else if (wpa_version & NL80211_WPA_VERSION_2) {
+        ar->arAuthMode = WPA2_AUTH;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: %u not spported\n", __func__, wpa_version));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static int
+ar6k_set_auth_type(AR_SOFTC_T *ar, enum nl80211_auth_type auth_type)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, auth_type));
+
+    switch (auth_type) {
+    case NL80211_AUTHTYPE_OPEN_SYSTEM:
+        ar->arDot11AuthMode = OPEN_AUTH;
+        break;
+    case NL80211_AUTHTYPE_SHARED_KEY:
+        ar->arDot11AuthMode = SHARED_AUTH;
+        break;
+    case NL80211_AUTHTYPE_NETWORK_EAP:
+        ar->arDot11AuthMode = LEAP_AUTH;
+        break;
+    default:
+        ar->arDot11AuthMode = OPEN_AUTH;
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: 0x%x not spported\n", __func__, auth_type));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static int
+ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, A_BOOL ucast)
+{
+    A_UINT8  *ar_cipher = ucast ? &ar->arPairwiseCrypto :
+                                &ar->arGroupCrypto;
+    A_UINT8  *ar_cipher_len = ucast ? &ar->arPairwiseCryptoLen :
+                                    &ar->arGroupCryptoLen;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: cipher 0x%x, ucast %u\n", __func__, cipher, ucast));
+
+    switch (cipher) {
+    case 0:
+    case IW_AUTH_CIPHER_NONE:
+        *ar_cipher = NONE_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    case WLAN_CIPHER_SUITE_WEP40:
+        *ar_cipher = WEP_CRYPT;
+        *ar_cipher_len = 5;
+        break;
+    case WLAN_CIPHER_SUITE_WEP104:
+        *ar_cipher = WEP_CRYPT;
+        *ar_cipher_len = 13;
+        break;
+    case WLAN_CIPHER_SUITE_TKIP:
+        *ar_cipher = TKIP_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    case WLAN_CIPHER_SUITE_CCMP:
+        *ar_cipher = AES_CRYPT;
+        *ar_cipher_len = 0;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: cipher 0x%x not supported\n", __func__, cipher));
+        return -ENOTSUPP;
+    }
+
+    return A_OK;
+}
+
+static void
+ar6k_set_key_mgmt(AR_SOFTC_T *ar, A_UINT32 key_mgmt)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, key_mgmt));
+
+    if (WLAN_AKM_SUITE_PSK == key_mgmt) {
+        if (WPA_AUTH == ar->arAuthMode) {
+            ar->arAuthMode = WPA_PSK_AUTH;
+        } else if (WPA2_AUTH == ar->arAuthMode) {
+            ar->arAuthMode = WPA2_PSK_AUTH;
+        }
+    } else if (WLAN_AKM_SUITE_8021X != key_mgmt) {
+        ar->arAuthMode = NONE_AUTH;
+    }
+}
+
+static int
+ar6k_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
+                      struct cfg80211_connect_params *sme)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready yet\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: destroy in progress\n", __func__));
+        return -EBUSY;
+    }
+
+    if(!sme->ssid_len || IEEE80211_MAX_SSID_LEN < sme->ssid_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    if(ar->arSkipScan == TRUE &&
+       ((sme->channel && sme->channel->center_freq == 0) ||
+        (sme->bssid && !sme->bssid[0] && !sme->bssid[1] && !sme->bssid[2] &&
+         !sme->bssid[3] && !sme->bssid[4] && !sme->bssid[5])))
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s:SkipScan: channel or bssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    if(down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+        return -ERESTARTSYS;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if(ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+        /*
+        * sleep until the command queue drains
+        */
+        wait_event_interruptible_timeout(arEvent,
+        ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: cmd queue drain timeout\n", __func__));
+            up(&ar->arSem);
+            return -EINTR;
+        }
+    }
+
+    if(ar->arConnected == TRUE &&
+       ar->arSsidLen == sme->ssid_len &&
+       !A_MEMCMP(ar->arSsid, sme->ssid, ar->arSsidLen)) {
+        reconnect_flag = TRUE;
+        status = wmi_reconnect_cmd(ar->arWmi,
+                                   ar->arReqBssid,
+                                   ar->arChannelHint);
+
+        up(&ar->arSem);
+        if (status != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_reconnect_cmd failed\n", __func__));
+            return -EIO;
+        }
+        return 0;
+    }
+
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = sme->ssid_len;
+    A_MEMCPY(ar->arSsid, sme->ssid, sme->ssid_len);
+
+    if(sme->channel){
+        ar->arChannelHint = sme->channel->center_freq;
+    }
+
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    if(sme->bssid){
+        if(A_MEMCMP(&sme->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+            A_MEMCPY(ar->arReqBssid, sme->bssid, sizeof(ar->arReqBssid));
+        }
+    }
+
+    ar6k_set_wpa_version(ar, sme->crypto.wpa_versions);
+    ar6k_set_auth_type(ar, sme->auth_type);
+
+    if(sme->crypto.n_ciphers_pairwise) {
+        ar6k_set_cipher(ar, sme->crypto.ciphers_pairwise[0], true);
+    }
+    ar6k_set_cipher(ar, sme->crypto.cipher_group, false);
+
+    if(sme->crypto.n_akm_suites) {
+        ar6k_set_key_mgmt(ar, sme->crypto.akm_suites[0]);
+    }
+
+    ar->arNetworkType = INFRA_NETWORK;
+
+    if((sme->key_len) &&
+       (NONE_AUTH == ar->arAuthMode) &&
+        (WEP_CRYPT == ar->arPairwiseCrypto)) {
+        struct ar_key *key = NULL;
+
+        if(sme->key_idx < WMI_MIN_KEY_INDEX || sme->key_idx > WMI_MAX_KEY_INDEX) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("%s: key index %d out of bounds\n", __func__, sme->key_idx));
+            up(&ar->arSem);
+            return -ENOENT;
+        }
+
+        key = &ar->keys[sme->key_idx];
+        key->key_len = sme->key_len;
+        A_MEMCPY(key->key, sme->key, key->key_len);
+        key->cipher = ar->arPairwiseCrypto;
+        ar->arDefTxKeyIndex = sme->key_idx;
+
+        wmi_addKey_cmd(ar->arWmi, sme->key_idx,
+                    ar->arPairwiseCrypto,
+                    GROUP_USAGE | TX_USAGE,
+                    key->key_len,
+                    NULL,
+                    key->key, KEY_OP_INIT_VAL, NULL,
+                    NO_SYNC_WMIFLAG);
+    }
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+            up(&ar->arSem);
+            return -EIO;
+        }
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+                    " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                    " GRP crypto Len %d channel hint %u\n",
+                    __func__, ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                    ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+    reconnect_flag = 0;
+    status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                            ar->arDot11AuthMode, ar->arAuthMode,
+                            ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                            ar->arGroupCrypto,ar->arGroupCryptoLen,
+                            ar->arSsidLen, ar->arSsid,
+                            ar->arReqBssid, ar->arChannelHint,
+                            ar->arConnectCtrlFlags);
+
+    up(&ar->arSem);
+
+    if (A_EINVAL == status) {
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Invalid request\n", __func__));
+        return -ENOENT;
+    } else if (status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_connect_cmd failed\n", __func__));
+        return -EIO;
+    }
+
+    if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+        ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+    {
+        A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+    }
+
+    ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+    ar->arConnectPending = TRUE;
+
+    return 0;
+}
+
+void
+ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+                A_UINT8 *bssid, A_UINT16 listenInterval,
+                A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+                A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                A_UINT8 assocRespLen, A_UINT8 *assocInfo)
+{
+    A_UINT16 size = 0;
+    A_UINT16 capability = 0;
+    struct cfg80211_bss *bss = NULL;
+    struct ieee80211_mgmt *mgmt = NULL;
+    struct ieee80211_channel *ibss_channel = NULL;
+    s32 signal = 50 * 100;
+    A_UINT8 ie_buf_len = 0;
+    unsigned char ie_buf[256];
+    unsigned char *ptr_ie_buf = ie_buf;
+    unsigned char *ieeemgmtbuf = NULL;
+    A_UINT8 source_mac[ATH_MAC_LEN];
+
+    A_UINT8 assocReqIeOffset = sizeof(A_UINT16)  +  /* capinfo*/
+                               sizeof(A_UINT16);    /* listen interval */
+    A_UINT8 assocRespIeOffset = sizeof(A_UINT16) +  /* capinfo*/
+                                sizeof(A_UINT16) +  /* status Code */
+                                sizeof(A_UINT16);   /* associd */
+    A_UINT8 *assocReqIe = assocInfo + beaconIeLen + assocReqIeOffset;
+    A_UINT8 *assocRespIe = assocInfo + beaconIeLen + assocReqLen + assocRespIeOffset;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    assocReqLen -= assocReqIeOffset;
+    assocRespLen -= assocRespIeOffset;
+
+    if((ADHOC_NETWORK & networkType)) {
+        if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in ibss mode\n", __func__));
+            return;
+        }
+    }
+
+    /* Before informing the join/connect event, make sure that
+     * bss entry is present in scan list, if it not present
+     * construct and insert into scan list, otherwise that
+     * event will be dropped on the way by cfg80211, due to
+     * this keys will not be plumbed in case of WEP and
+     * application will not be aware of join/connect status. */
+    bss = cfg80211_get_bss(ar->wdev->wiphy, NULL, bssid,
+                           ar->wdev->ssid, ar->wdev->ssid_len,
+                           ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS),
+                           ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS));
+
+    if(!bss) {
+        if (ADHOC_NETWORK & networkType) {
+            /* construct 802.11 mgmt beacon */
+            if(ptr_ie_buf) {
+                *ptr_ie_buf++ = WLAN_EID_SSID;
+                *ptr_ie_buf++ = ar->arSsidLen;
+                A_MEMCPY(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
+                ptr_ie_buf +=ar->arSsidLen;
+
+                *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
+                *ptr_ie_buf++ = 2; /* length */
+                *ptr_ie_buf++ = 0; /* ATIM window */
+                *ptr_ie_buf++ = 0; /* ATIM window */
+
+                /* TODO: update ibss params and include supported rates,
+                 * DS param set, extened support rates, wmm. */
+
+                ie_buf_len = ptr_ie_buf - ie_buf;
+            }
+
+            capability |= IEEE80211_CAPINFO_IBSS;
+            if(WEP_CRYPT == ar->arPairwiseCrypto) {
+                capability |= IEEE80211_CAPINFO_PRIVACY;
+            }
+            A_MEMCPY(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN);
+            ptr_ie_buf = ie_buf;
+        } else {
+            capability = *(A_UINT16 *)(&assocInfo[beaconIeLen]);
+            A_MEMCPY(source_mac, bssid, ATH_MAC_LEN);
+            ptr_ie_buf = assocReqIe;
+            ie_buf_len = assocReqLen;
+        }
+
+        size = offsetof(struct ieee80211_mgmt, u)
+             + sizeof(mgmt->u.beacon)
+             + ie_buf_len;
+
+        ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+        if(!ieeemgmtbuf) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                            ("%s: ieeeMgmtbuf alloc error\n", __func__));
+            return;
+        }
+
+        A_MEMZERO(ieeemgmtbuf, size);
+        mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+        mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
+        A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+        A_MEMCPY(mgmt->sa, source_mac, ATH_MAC_LEN);
+        A_MEMCPY(mgmt->bssid, bssid, ATH_MAC_LEN);
+        mgmt->u.beacon.beacon_int = beaconInterval;
+        mgmt->u.beacon.capab_info = capability;
+        A_MEMCPY(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
+
+        ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
+
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: inform bss with bssid %02x:%02x:%02x:%02x:%02x:%02x "\
+                         "channel %d beaconInterval %d capability 0x%x\n",
+                        __func__,
+                        mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2],
+                        mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5],
+                        ibss_channel->hw_value, beaconInterval, capability));
+
+        bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
+                                        ibss_channel, mgmt,
+                                        le16_to_cpu(size),
+                                        signal, GFP_KERNEL);
+        A_FREE(ieeemgmtbuf);
+        cfg80211_put_bss(bss);
+    }
+
+    if((ADHOC_NETWORK & networkType)) {
+        cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+        return;
+    }
+
+    if (FALSE == ar->arConnected) {
+        /* inform connect result to cfg80211 */
+        cfg80211_connect_result(ar->arNetDev, bssid,
+                                assocReqIe, assocReqLen,
+                                assocRespIe, assocRespLen,
+                                WLAN_STATUS_SUCCESS, GFP_KERNEL);
+    } else {
+        /* inform roam event to cfg80211 */
+        cfg80211_roamed(ar->arNetDev, bssid,
+                        assocReqIe, assocReqLen,
+                        assocRespIe, assocRespLen,
+                        GFP_KERNEL);
+    }
+}
+
+static int
+ar6k_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
+                        A_UINT16 reason_code)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason_code));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->bIsDestroyProgress) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+        return -EBUSY;
+    }
+
+    if(down_interruptible(&ar->arSem)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+        return -ERESTARTSYS;
+    }
+
+    reconnect_flag = 0;
+    wmi_disconnect_cmd(ar->arWmi);
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = 0;
+
+    if (ar->arSkipScan == FALSE) {
+        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    }
+
+    up(&ar->arSem);
+
+    return 0;
+}
+
+void
+ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+                               A_UINT8 *bssid, A_UINT8 assocRespLen,
+                               A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason));
+
+    if((ADHOC_NETWORK & ar->arNetworkType)) {
+        if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                            ("%s: ath6k not in ibss mode\n", __func__));
+            return;
+        }
+        A_MEMZERO(bssid, ETH_ALEN);
+        cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+        return;
+    }
+
+    if(FALSE == ar->arConnected) {
+        if(NO_NETWORK_AVAIL == reason) {
+            /* connect cmd failed */
+            cfg80211_connect_result(ar->arNetDev, bssid,
+                                    NULL, 0,
+                                    NULL, 0,
+                                    WLAN_STATUS_UNSPECIFIED_FAILURE,
+                                    GFP_KERNEL);
+        }
+    } else {
+        /* connection loss due to disconnect cmd or low rssi */
+        cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL);
+    }
+}
+
+void
+ar6k_cfg80211_scan_node(void *arg, bss_t *ni)
+{
+    struct wiphy *wiphy = (struct wiphy *)arg;
+    A_UINT16 size;
+    unsigned char *ieeemgmtbuf = NULL;
+    struct ieee80211_mgmt *mgmt;
+    struct ieee80211_channel *channel;
+    struct ieee80211_supported_band *band;
+    struct ieee80211_common_ie  *cie;
+    s32 signal;
+    int freq;
+
+    cie = &ni->ni_cie;
+
+#define CHAN_IS_11A(x)  (!((x >= 2412) && (x <= 2484)))
+    if(CHAN_IS_11A(cie->ie_chan)) {
+        /* 11a */
+        band = wiphy->bands[IEEE80211_BAND_5GHZ];
+    } else if((cie->ie_erp) || (cie->ie_xrates)) {
+        /* 11g */
+        band = wiphy->bands[IEEE80211_BAND_2GHZ];
+    } else {
+        /* 11b */
+        band = wiphy->bands[IEEE80211_BAND_2GHZ];
+    }
+
+    size = ni->ni_framelen + offsetof(struct ieee80211_mgmt, u);
+    ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+    if(!ieeemgmtbuf)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ieeeMgmtbuf alloc error\n", __func__));
+        return;
+    }
+
+    /* Note:
+       TODO: Update target to include 802.11 mac header while sending bss info.
+       Target removes 802.11 mac header while sending the bss info to host,
+       cfg80211 needs it, for time being just filling the da, sa and bssid fields alone.
+    */
+    mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+    A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+    A_MEMCPY(mgmt->sa, ni->ni_macaddr, ATH_MAC_LEN);
+    A_MEMCPY(mgmt->bssid, ni->ni_macaddr, ATH_MAC_LEN);
+    A_MEMCPY(ieeemgmtbuf + offsetof(struct ieee80211_mgmt, u),
+             ni->ni_buf, ni->ni_framelen);
+
+    freq    = cie->ie_chan;
+    channel = ieee80211_get_channel(wiphy, freq);
+    signal  = ni->ni_snr * 100;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: bssid %02x:%02x:%02x:%02x:%02x:%02x channel %d freq %d size %d\n",
+                   __func__,
+                   mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2],
+                   mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5],
+                   channel->hw_value, freq, size));
+    cfg80211_inform_bss_frame(wiphy, channel, mgmt,
+                              le16_to_cpu(size),
+                              signal, GFP_KERNEL);
+
+    A_FREE (ieeemgmtbuf);
+}
+
+static int
+ar6k_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
+                   struct cfg80211_scan_request *request)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    int ret = 0;
+    A_BOOL forceFgScan = FALSE;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi,
+                             (ar->arConnected ? ALL_BUT_BSS_FILTER : ALL_BSS_FILTER),
+                             0) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+            return -EIO;
+        }
+    }
+
+    if(request->n_ssids &&
+       request->ssids[0].ssid_len) {
+        A_UINT8 i;
+
+        if(request->n_ssids > MAX_PROBED_SSID_INDEX) {
+            request->n_ssids = MAX_PROBED_SSID_INDEX;
+        }
+
+        for (i = 0; i < request->n_ssids; i++) {
+            wmi_probedSsid_cmd(ar->arWmi, i, SPECIFIC_SSID_FLAG,
+                               request->ssids[i].ssid_len,
+                               request->ssids[i].ssid);
+        }
+    }
+
+    if(ar->arConnected) {
+        forceFgScan = TRUE;
+    }
+
+    if(wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, forceFgScan, FALSE, \
+                         0, 0, 0, NULL) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_startscan_cmd failed\n", __func__));
+        ret = -EIO;
+    }
+
+    ar->scan_request = request;
+
+    return ret;
+}
+
+void
+ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: status %d\n", __func__, status));
+
+    if(ar->scan_request)
+    {
+        /* Translate data to cfg80211 mgmt format */
+        wmi_iterate_nodes(ar->arWmi, ar6k_cfg80211_scan_node, ar->wdev->wiphy);
+
+        cfg80211_scan_done(ar->scan_request,
+                          (status & A_ECANCELED) ? true : false);
+
+        if(ar->scan_request->n_ssids &&
+           ar->scan_request->ssids[0].ssid_len) {
+            A_UINT8 i;
+
+            for (i = 0; i < ar->scan_request->n_ssids; i++) {
+                wmi_probedSsid_cmd(ar->arWmi, i, DISABLE_SSID_FLAG,
+                                   0, NULL);
+            }
+        }
+        ar->scan_request = NULL;
+    }
+}
+
+static int
+ar6k_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, const A_UINT8 *mac_addr,
+                      struct key_params *params)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    struct ar_key *key = NULL;
+    A_UINT8 key_usage;
+    A_UINT8 key_type;
+    A_STATUS status = 0;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s:\n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    key = &ar->keys[key_index];
+    A_MEMZERO(key, sizeof(struct ar_key));
+
+    if(!mac_addr || is_broadcast_ether_addr(mac_addr)) {
+        key_usage = GROUP_USAGE;
+    } else {
+        key_usage = PAIRWISE_USAGE;
+    }
+
+    if(params) {
+        if(params->key_len > WLAN_MAX_KEY_LEN ||
+            params->seq_len > IW_ENCODE_SEQ_MAX_SIZE)
+            return -EINVAL;
+
+        key->key_len = params->key_len;
+        A_MEMCPY(key->key, params->key, key->key_len);
+        key->seq_len = params->seq_len;
+        A_MEMCPY(key->seq, params->seq, key->seq_len);
+        key->cipher = params->cipher;
+    }
+
+    switch (key->cipher) {
+    case WLAN_CIPHER_SUITE_WEP40:
+    case WLAN_CIPHER_SUITE_WEP104:
+        key_type = WEP_CRYPT;
+        if(key_index == ar->arDefTxKeyIndex) {
+            key_usage = GROUP_USAGE | TX_USAGE;
+        }
+        break;
+
+    case WLAN_CIPHER_SUITE_TKIP:
+        key_type = TKIP_CRYPT;
+        break;
+
+    case WLAN_CIPHER_SUITE_CCMP:
+        key_type = AES_CRYPT;
+        break;
+
+    default:
+        return -ENOTSUPP;
+    }
+
+    if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+        (GROUP_USAGE & key_usage))
+    {
+        A_UNTIMEOUT(&ar->disconnect_timer);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: index %d, key_len %d, key_type 0x%x,"\
+                    " key_usage 0x%x, seq_len %d\n",
+                    __func__, key_index, key->key_len, key_type,
+                    key_usage, key->seq_len));
+
+    status = wmi_addKey_cmd(ar->arWmi, key_index, key_type, key_usage,
+                    key->key_len, key->seq, key->key, KEY_OP_INIT_VAL,
+                    (A_UINT8*)mac_addr, SYNC_BOTH_WMIFLAG);
+
+
+    if(status != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, const A_UINT8 *mac_addr)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    if(!ar->keys[key_index].key_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d is empty\n", __func__, key_index));
+        return 0;
+    }
+
+    ar->keys[key_index].key_len = 0;
+
+    return wmi_deleteKey_cmd(ar->arWmi, key_index);
+}
+
+
+static int
+ar6k_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
+                      A_UINT8 key_index, const A_UINT8 *mac_addr, void *cookie,
+                      void (*callback)(void *cookie, struct key_params*))
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+    struct ar_key *key = NULL;
+    struct key_params params;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n", __func__, key_index));
+        return -ENOENT;
+    }
+
+    key = &ar->keys[key_index];
+    A_MEMZERO(&params, sizeof(params));
+    params.cipher = key->cipher;
+    params.key_len = key->key_len;
+    params.seq_len = key->seq_len;
+    params.seq = key->seq;
+    params.key = key->key;
+
+    callback(cookie, &params);
+
+    return key->key_len ? 0 : -ENOENT;
+}
+
+
+static int
+ar6k_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *ndev,
+                              A_UINT8 key_index)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                        ("%s: key index %d out of bounds\n",
+                        __func__, key_index));
+        return -ENOENT;
+    }
+
+    if(!ar->keys[key_index].key_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: invalid key index %d\n",
+                        __func__, key_index));
+        return -EINVAL;
+    }
+
+    ar->arDefTxKeyIndex = key_index;
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_default_mgmt_key(struct wiphy *wiphy, struct net_device *ndev,
+                                   A_UINT8 key_index)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+    return -ENOTSUPP;
+}
+
+void
+ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+                    ("%s: keyid %d, ismcast %d\n", __func__, keyid, ismcast));
+
+    cfg80211_michael_mic_failure(ar->arNetDev, ar->arBssid,
+                                 (ismcast ? NL80211_KEYTYPE_GROUP : NL80211_KEYTYPE_PAIRWISE),
+                                 keyid, NULL, GFP_KERNEL);
+}
+
+static int
+ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, A_UINT32 changed)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: changed 0x%x\n", __func__, changed));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if (changed & WIPHY_PARAM_RTS_THRESHOLD) {
+        if (wmi_set_rts_cmd(ar->arWmi,wiphy->rts_threshold) != A_OK){
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_rts_cmd failed\n", __func__));
+            return -EIO;
+        }
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev,
+                               const A_UINT8 *peer,
+                               const struct cfg80211_bitrate_mask *mask)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: mask 0x%x\n", __func__, mask->fixed));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    status = wmi_set_fixrates_cmd(ar->arWmi, mask->fixed);
+
+    if(status == A_EINVAL) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: invalid params\n", __func__));
+        return -EINVAL;
+    } else if(status != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_fixrates_cmd failed\n", __func__));
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_txpower(struct wiphy *wiphy, enum tx_power_setting type, int dbm)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+    A_UINT8 ar_dbm;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x, dbm %d\n", __func__, type, dbm));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    ar->arTxPwrSet = FALSE;
+    switch(type) {
+    case TX_POWER_AUTOMATIC:
+        return 0;
+    case TX_POWER_LIMITED:
+        ar->arTxPwr = ar_dbm = dbm;
+        ar->arTxPwrSet = TRUE;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x not supported\n", __func__, type));
+        return -EOPNOTSUPP;
+    }
+
+    wmi_set_txPwr_cmd(ar->arWmi, ar_dbm);
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_get_txpower(struct wiphy *wiphy, int *dbm)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if((ar->arConnected == TRUE)) {
+        ar->arTxPwr = 0;
+
+        if(wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_get_txPwr_cmd failed\n", __func__));
+            return -EIO;
+        }
+
+        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, 5 * HZ);
+
+        if(signal_pending(current)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Target did not respond\n", __func__));
+            return -EINTR;
+        }
+    }
+
+    *dbm = ar->arTxPwr;
+    return 0;
+}
+
+static int
+ar6k_cfg80211_set_power_mgmt(struct wiphy *wiphy,
+                             struct net_device *dev,
+                             bool pmgmt, int timeout)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    WMI_POWER_MODE_CMD pwrMode;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: pmgmt %d, timeout %d\n", __func__, pmgmt, timeout));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(pmgmt) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__));
+        pwrMode.powerMode = MAX_PERF_POWER;
+    } else {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__));
+        pwrMode.powerMode = REC_POWER;
+    }
+
+    if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != A_OK) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_powermode_cmd failed\n", __func__));
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_add_virtual_intf(struct wiphy *wiphy, char *name,
+            				    enum nl80211_iftype type, u32 *flags,
+            				    struct vif_params *params)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+    /* Multiple virtual interface is not supported.
+     * The default interface supports STA and IBSS type
+     */
+    return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev)
+{
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+    /* Multiple virtual interface is not supported.
+     * The default interface supports STA and IBSS type
+     */
+    return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
+                           enum nl80211_iftype type, u32 *flags,
+                           struct vif_params *params)
+{
+    AR_SOFTC_T *ar = ar6k_priv(ndev);
+    struct wireless_dev *wdev = ar->wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type %u\n", __func__, type));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    switch (type) {
+    case NL80211_IFTYPE_STATION:
+        ar->arNetworkType = INFRA_NETWORK;
+        break;
+    case NL80211_IFTYPE_ADHOC:
+        ar->arNetworkType = ADHOC_NETWORK;
+        break;
+    default:
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: type %u\n", __func__, type));
+        return -EOPNOTSUPP;
+    }
+
+    wdev->iftype = type;
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
+                        struct cfg80211_ibss_params *ibss_param)
+{
+    AR_SOFTC_T *ar = ar6k_priv(dev);
+    A_STATUS status;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    if(!ibss_param->ssid_len || IEEE80211_MAX_SSID_LEN < ibss_param->ssid_len) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+        return -EINVAL;
+    }
+
+    ar->arSsidLen = ibss_param->ssid_len;
+    A_MEMCPY(ar->arSsid, ibss_param->ssid, ar->arSsidLen);
+
+    if(ibss_param->channel) {
+        ar->arChannelHint = ibss_param->channel->center_freq;
+    }
+
+    if(ibss_param->channel_fixed) {
+        /* TODO: channel_fixed: The channel should be fixed, do not search for
+         * IBSSs to join on other channels. Target firmware does not support this
+         * feature, needs to be updated.*/
+    }
+
+    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    if(ibss_param->bssid) {
+        if(A_MEMCMP(&ibss_param->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+            A_MEMCPY(ar->arReqBssid, ibss_param->bssid, sizeof(ar->arReqBssid));
+        }
+    }
+
+    ar6k_set_wpa_version(ar, 0);
+    ar6k_set_auth_type(ar, NL80211_AUTHTYPE_OPEN_SYSTEM);
+
+    if(ibss_param->privacy) {
+        ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, true);
+        ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, false);
+    } else {
+        ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, true);
+        ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, false);
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+                    " PW crypto %d PW crypto Len %d GRP crypto %d"\
+                    " GRP crypto Len %d channel hint %u\n",
+                    __func__, ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                    ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+    status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+                            ar->arDot11AuthMode, ar->arAuthMode,
+                            ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+                            ar->arGroupCrypto,ar->arGroupCryptoLen,
+                            ar->arSsidLen, ar->arSsid,
+                            ar->arReqBssid, ar->arChannelHint,
+                            ar->arConnectCtrlFlags);
+
+    return 0;
+}
+
+static int
+ar6k_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->arWmiReady == FALSE) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+        return -EIO;
+    }
+
+    if(ar->arWlanState == WLAN_DISABLED) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+        return -EIO;
+    }
+
+    wmi_disconnect_cmd(ar->arWmi);
+    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    ar->arSsidLen = 0;
+
+    return 0;
+}
+
+
+static const
+A_UINT32 cipher_suites[] = {
+    WLAN_CIPHER_SUITE_WEP40,
+    WLAN_CIPHER_SUITE_WEP104,
+    WLAN_CIPHER_SUITE_TKIP,
+    WLAN_CIPHER_SUITE_CCMP,
+};
+
+static struct
+cfg80211_ops ar6k_cfg80211_ops = {
+    .change_virtual_intf = ar6k_cfg80211_change_iface,
+    .add_virtual_intf = ar6k_cfg80211_add_virtual_intf,
+    .del_virtual_intf = ar6k_cfg80211_del_virtual_intf,
+    .scan = ar6k_cfg80211_scan,
+    .connect = ar6k_cfg80211_connect,
+    .disconnect = ar6k_cfg80211_disconnect,
+    .add_key = ar6k_cfg80211_add_key,
+    .get_key = ar6k_cfg80211_get_key,
+    .del_key = ar6k_cfg80211_del_key,
+    .set_default_key = ar6k_cfg80211_set_default_key,
+    .set_default_mgmt_key = ar6k_cfg80211_set_default_mgmt_key,
+    .set_wiphy_params = ar6k_cfg80211_set_wiphy_params,
+    .set_bitrate_mask = ar6k_cfg80211_set_bitrate_mask,
+    .set_tx_power = ar6k_cfg80211_set_txpower,
+    .get_tx_power = ar6k_cfg80211_get_txpower,
+    .set_power_mgmt = ar6k_cfg80211_set_power_mgmt,
+    .join_ibss = ar6k_cfg80211_join_ibss,
+    .leave_ibss = ar6k_cfg80211_leave_ibss,
+};
+
+struct wireless_dev *
+ar6k_cfg80211_init(struct device *dev)
+{
+    int ret = 0;
+    struct wireless_dev *wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    wdev = kzalloc(sizeof(struct wireless_dev), GFP_KERNEL);
+    if(!wdev) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't allocate wireless device\n", __func__));
+        return ERR_PTR(-ENOMEM);
+    }
+
+    /* create a new wiphy for use with cfg80211 */
+    wdev->wiphy = wiphy_new(&ar6k_cfg80211_ops, sizeof(AR_SOFTC_T));
+    if(!wdev->wiphy) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't allocate wiphy device\n", __func__));
+        kfree(wdev);
+        return ERR_PTR(-ENOMEM);
+    }
+
+    /* set device pointer for wiphy */
+    set_wiphy_dev(wdev->wiphy, dev);
+
+    wdev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+                                   BIT(NL80211_IFTYPE_ADHOC);
+    /* max num of ssids that can be probed during scanning */
+    wdev->wiphy->max_scan_ssids = MAX_PROBED_SSID_INDEX;
+    wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &ar6k_band_2ghz;
+    wdev->wiphy->bands[IEEE80211_BAND_5GHZ] = &ar6k_band_5ghz;
+    wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+
+    wdev->wiphy->cipher_suites = cipher_suites;
+    wdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);
+
+    ret = wiphy_register(wdev->wiphy);
+    if(ret < 0) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                        ("%s: Couldn't register wiphy device\n", __func__));
+        wiphy_free(wdev->wiphy);
+        return ERR_PTR(ret);
+    }
+
+    return wdev;
+}
+
+void
+ar6k_cfg80211_deinit(AR_SOFTC_T *ar)
+{
+    struct wireless_dev *wdev = ar->wdev;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+    if(ar->scan_request) {
+        cfg80211_scan_done(ar->scan_request, true);
+        ar->scan_request = NULL;
+    }
+
+    if(!wdev)
+        return;
+
+    wiphy_unregister(wdev->wiphy);
+    wiphy_free(wdev->wiphy);
+    kfree(wdev);
+}
+
+
+
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/eeprom.c b/drivers/net/wireless/ath6kl/os/linux/eeprom.c
new file mode 100644
index 000000000000..1c182751a939
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/eeprom.c
@@ -0,0 +1,581 @@
+/*
+ *
+ * Copyright (c) 2004-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/fs.h>
+
+#include "AR6002/hw2.0/hw/gpio_reg.h"
+#include "AR6002/hw2.0/hw/si_reg.h"
+
+//
+// defines
+//
+
+#define MAX_FILENAME 1023
+#define EEPROM_WAIT_LIMIT 16 
+
+#define HOST_INTEREST_ITEM_ADDRESS(item)          \
+        (AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+#define EEPROM_SZ 768
+
+/* soft mac */
+#define ATH_MAC_LEN                         6
+#define ATH_SOFT_MAC_TMP_BUF_LEN            64
+unsigned char mac_addr[ATH_MAC_LEN];
+unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
+char *p_mac = NULL;
+/* soft mac */
+
+//
+// static variables
+//
+
+static A_UCHAR eeprom_data[EEPROM_SZ];
+static A_UINT32 sys_sleep_reg;
+static HIF_DEVICE *p_bmi_device;
+
+//
+// Functions
+//
+
+/* soft mac */
+static int
+wmic_ether_aton(const char *orig, A_UINT8 *eth)
+{
+  const char *bufp;
+  int i;
+
+  i = 0;
+  for(bufp = orig; *bufp != '\0'; ++bufp) {
+    unsigned int val;
+    unsigned char c = *bufp++;
+    if (c >= '0' && c <= '9') val = c - '0';
+    else if (c >= 'a' && c <= 'f') val = c - 'a' + 10;
+    else if (c >= 'A' && c <= 'F') val = c - 'A' + 10;
+    else {
+        printk("%s: MAC value is invalid\n", __FUNCTION__);
+        break;
+    }
+
+    val <<= 4;
+    c = *bufp++;
+    if (c >= '0' && c <= '9') val |= c - '0';
+    else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10;
+    else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10;
+    else {
+        printk("%s: MAC value is invalid\n", __FUNCTION__);
+        break;
+    }
+
+    eth[i] = (unsigned char) (val & 0377);
+    if(++i == ATH_MAC_LEN) {
+	    /* That's it.  Any trailing junk? */
+	    if (*bufp != '\0') {
+		    return 0;
+	    }
+	    return 1;
+    }
+    if (*bufp != ':')
+	    break;
+  }
+  return 0;
+}
+
+static void
+update_mac(unsigned char* eeprom, int size, unsigned char* macaddr)
+{
+	int i;
+	A_UINT16* ptr = (A_UINT16*)(eeprom+4);
+	A_UINT16  checksum = 0;
+
+	memcpy(eeprom+10,macaddr,6);
+
+	*ptr = 0;
+	ptr = (A_UINT16*)eeprom;
+
+	for (i=0; i<size; i+=2) {
+		checksum ^= *ptr++;
+	}
+	checksum = ~checksum;
+
+	ptr = (A_UINT16*)(eeprom+4);
+	*ptr = checksum;
+	return;
+}
+/* soft mac */
+
+/* Read a Target register and return its value. */
+inline void
+BMI_read_reg(A_UINT32 address, A_UINT32 *pvalue)
+{
+    BMIReadSOCRegister(p_bmi_device, address, pvalue);
+}
+
+/* Write a value to a Target register. */
+inline void
+BMI_write_reg(A_UINT32 address, A_UINT32 value)
+{
+    BMIWriteSOCRegister(p_bmi_device, address, value);
+}
+
+/* Read Target memory word and return its value. */
+inline void
+BMI_read_mem(A_UINT32 address, A_UINT32 *pvalue)
+{
+    BMIReadMemory(p_bmi_device, address, (A_UCHAR*)(pvalue), 4);
+}
+
+/* Write a word to a Target memory. */
+inline void
+BMI_write_mem(A_UINT32 address, A_UINT8 *p_data, A_UINT32 sz)
+{
+    BMIWriteMemory(p_bmi_device, address, (A_UCHAR*)(p_data), sz); 
+}
+
+/*
+ * Enable and configure the Target's Serial Interface
+ * so we can access the EEPROM.
+ */
+static void
+enable_SI(HIF_DEVICE *p_device)
+{
+    A_UINT32 regval;
+
+    printk("%s\n", __FUNCTION__);
+
+    p_bmi_device = p_device;
+
+    BMI_read_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
+    BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
+
+    BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+    regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
+
+    BMI_read_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, &regval);
+    regval &= ~RESET_CONTROL_SI0_RST_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
+
+
+    BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, &regval);
+    regval &= ~GPIO_PIN0_CONFIG_MASK;
+    BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
+
+    BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, &regval);
+    regval &= ~GPIO_PIN1_CONFIG_MASK;
+    BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
+
+    /* SI_CONFIG = 0x500a6; */
+    regval =    SI_CONFIG_BIDIR_OD_DATA_SET(1)  |
+                SI_CONFIG_I2C_SET(1)            |
+                SI_CONFIG_POS_SAMPLE_SET(1)     |
+                SI_CONFIG_INACTIVE_CLK_SET(1)   |
+                SI_CONFIG_INACTIVE_DATA_SET(1)   |
+                SI_CONFIG_DIVIDER_SET(6);
+    BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
+    
+}
+
+static void
+disable_SI(void)
+{
+    A_UINT32 regval;
+    
+    printk("%s\n", __FUNCTION__);
+
+    BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
+    BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+    regval |= CLOCK_CONTROL_SI0_CLK_MASK;
+    BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
+    BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
+}
+
+/*
+ * Tell the Target to start an 8-byte read from EEPROM,
+ * putting the results in Target RX_DATA registers.
+ */
+static void
+request_8byte_read(int offset)
+{
+    A_UINT32 regval;
+
+//    printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
+
+    
+    /* SI_TX_DATA0 = read from offset */
+        regval =(0xa1<<16)|
+                ((offset & 0xff)<<8)    |
+                (0xa0 | ((offset & 0xff00)>>7));
+    
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+        regval = SI_CS_START_SET(1)      |
+                SI_CS_RX_CNT_SET(8)     |
+                SI_CS_TX_CNT_SET(3);
+        BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Tell the Target to start a 4-byte write to EEPROM,
+ * writing values from Target TX_DATA registers.
+ */
+static void
+request_4byte_write(int offset, A_UINT32 data)
+{
+    A_UINT32 regval;
+
+    printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
+
+        /* SI_TX_DATA0 = write data to offset */
+        regval =    ((data & 0xffff) <<16)    |
+                ((offset & 0xff)<<8)    |
+                (0xa0 | ((offset & 0xff00)>>7));
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+        regval =    data >> 16;
+        BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
+
+        regval =    SI_CS_START_SET(1)      |
+                SI_CS_RX_CNT_SET(0)     |
+                SI_CS_TX_CNT_SET(6);
+        BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Check whether or not an EEPROM request that was started
+ * earlier has completed yet.
+ */
+static A_BOOL
+request_in_progress(void)
+{
+    A_UINT32 regval;
+
+    /* Wait for DONE_INT in SI_CS */
+    BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+
+//    printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
+    if (regval & SI_CS_DONE_ERR_MASK) {
+        printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
+    }
+
+    return (!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * try to detect the type of EEPROM,16bit address or 8bit address
+ */
+
+static void eeprom_type_detect(void)
+{
+    A_UINT32 regval;
+    A_UINT8 i = 0;
+
+    request_8byte_read(0x100);
+   /* Wait for DONE_INT in SI_CS */
+    do{
+        BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+        if (regval & SI_CS_DONE_ERR_MASK) {
+            printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);     
+            break;
+        }
+        if (i++ == EEPROM_WAIT_LIMIT) {
+            printk("%s: EEPROM not responding\n", __FUNCTION__);
+        }
+    } while(!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * Extract the results of a completed EEPROM Read request
+ * and return them to the caller.
+ */
+inline void
+read_8byte_results(A_UINT32 *data)
+{
+    /* Read SI_RX_DATA0 and SI_RX_DATA1 */
+    BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
+    BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
+}
+
+
+/*
+ * Wait for a previously started command to complete.
+ * Timeout if the command is takes "too long".
+ */
+static void
+wait_for_eeprom_completion(void)
+{
+    int i=0;
+
+    while (request_in_progress()) {
+        if (i++ == EEPROM_WAIT_LIMIT) {
+            printk("%s: EEPROM not responding\n", __FUNCTION__);
+        }
+    }
+}
+
+/*
+ * High-level function which starts an 8-byte read,
+ * waits for it to complete, and returns the result.
+ */
+static void
+fetch_8bytes(int offset, A_UINT32 *data)
+{
+    request_8byte_read(offset);
+    wait_for_eeprom_completion();
+    read_8byte_results(data);
+
+    /* Clear any pending intr */
+    BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
+}
+
+/*
+ * High-level function which starts a 4-byte write,
+ * and waits for it to complete.
+ */
+inline void
+commit_4bytes(int offset, A_UINT32 data)
+{
+    request_4byte_write(offset, data);
+    wait_for_eeprom_completion();
+}
+/* ATHENV */
+#ifdef ANDROID_ENV
+void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
+{
+    A_UINT32 first_word;
+    A_UINT32 board_data_addr;
+    int i;
+
+    printk("%s: Enter\n", __FUNCTION__);
+
+    enable_SI(device);
+    eeprom_type_detect();
+
+    if (fake_file) {
+        /*
+         * Transfer from file to Target RAM.
+         * Fetch source data from file.
+         */
+        mm_segment_t		oldfs;
+        struct file		*filp;
+        struct inode		*inode = NULL;
+        int			length;
+
+        /* open file */
+        oldfs = get_fs();
+        set_fs(KERNEL_DS);
+        filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
+
+        if (IS_ERR(filp)) {
+            printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
+            set_fs(oldfs);
+            return;
+        }
+
+        if (!filp->f_op) {
+            printk("%s: File Operation Method Error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+    	inode = filp->f_path.dentry->d_inode;
+#else
+    	inode = filp->f_dentry->d_inode;
+#endif
+
+        if (!inode) {
+            printk("%s: Get inode from filp failed\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+
+        /* file's size */
+        length = i_size_read(inode->i_mapping->host);
+        printk("%s: length=%d\n", __FUNCTION__, length);
+        if (length != EEPROM_SZ) {
+            printk("%s: The file's size is not as expected\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        /* read data */
+        if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
+            printk("%s: file read error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+        /* read data out successfully */
+        filp_close(filp, NULL);
+        set_fs(oldfs);
+    } else {
+        /*
+         * Read from EEPROM to file OR transfer from EEPROM to Target RAM.
+         * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
+         */
+
+        fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0]));
+
+        /* Check the first word of EEPROM for validity */
+        first_word = *((A_UINT32 *)eeprom_data);
+
+        if ((first_word == 0) || (first_word == 0xffffffff)) {
+            printk("Did not find EEPROM with valid Board Data.\n");
+        }
+
+        for (i=8; i<EEPROM_SZ; i+=8) {
+            fetch_8bytes(i, (A_UINT32 *)(&eeprom_data[i]));
+        }
+    }
+
+    /* soft mac */
+    if (p_mac) {
+
+        mm_segment_t		oldfs;
+        struct file		*filp;
+        struct inode		*inode = NULL;
+        int			length;
+        
+        /* open file */
+        oldfs = get_fs();
+        set_fs(KERNEL_DS);
+        filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
+        
+        printk("%s try to open file %s\n", __FUNCTION__, p_mac);
+
+        if (IS_ERR(filp)) {
+            printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
+            set_fs(oldfs);
+            return;
+        }
+        
+        if (!filp->f_op) {
+            printk("%s: File Operation Method Error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+    	inode = filp->f_path.dentry->d_inode;
+#else
+    	inode = filp->f_dentry->d_inode;
+#endif
+        if (!inode) {
+            printk("%s: Get inode from filp failed\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+        printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+        
+        /* file's size */
+        length = i_size_read(inode->i_mapping->host);
+        printk("%s: length=%d\n", __FUNCTION__, length);
+        if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
+            printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+        
+        /* read data */
+        if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
+            printk("%s: file read error\n", __FUNCTION__);
+            filp_close(filp, NULL);
+            set_fs(oldfs);
+            return;
+        }
+
+#if 0
+        /* the data we just read */
+        printk("%s: mac address from the file:\n", __FUNCTION__);
+        for (i = 0; i < length; i++)
+            printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
+        printk("\n");
+#endif
+
+        /* read data out successfully */
+        filp_close(filp, NULL);
+        set_fs(oldfs);
+
+        /* convert mac address */
+        if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
+            printk("%s: convert mac value fail\n", __FUNCTION__);
+            return;
+        }
+
+#if 0
+        /* the converted mac address */
+        printk("%s: the converted mac value\n", __FUNCTION__);
+        for (i = 0; i < ATH_MAC_LEN; i++)
+            printk("[0x%x],", mac_addr[i]);
+        printk("\n");
+#endif
+    }
+    /* soft mac */
+
+    /* Determine where in Target RAM to write Board Data */
+    BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
+    if (board_data_addr == 0) {
+        printk("hi_board_data is zero\n");
+    }
+
+    /* soft mac */
+#if 1
+    /* Update MAC address in RAM */
+    if (p_mac) {
+	    update_mac(eeprom_data, EEPROM_SZ, mac_addr);
+    }
+#endif
+#if 0
+    /* mac address in eeprom array */
+    printk("%s: mac values in eeprom array\n", __FUNCTION__);
+    for (i = 10; i < 10 + 6; i++)
+        printk("[0x%x],", eeprom_data[i]);
+    printk("\n");
+#endif
+    /* soft mac */
+
+    /* Write EEPROM data to Target RAM */
+    BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ);
+
+    /* Record the fact that Board Data IS initialized */
+    {
+       A_UINT32 one = 1;
+       BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
+                     (A_UINT8 *)&one, sizeof(A_UINT32));
+    }
+
+    disable_SI();
+}
+#endif
+/* ATHENV */
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c
new file mode 100644
index 000000000000..29b7fac80949
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c
@@ -0,0 +1,119 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#include "hci_transport_api.h"
+
+#include "AR6002/hw4.0/hw/apb_athr_wlan_map.h"
+#include "AR6002/hw4.0/hw/uart_reg.h"
+#include "AR6002/hw4.0/hw/rtc_wlan_reg.h"
+
+HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+A_STATUS    (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+void        (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS    (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+A_STATUS    (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+A_STATUS    (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+extern HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks;
+
+A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks)
+{
+    ar6kHciTransCallbacks = *hciTransCallbacks;
+
+    _HCI_TransportAttach = HCI_TransportAttach;
+    _HCI_TransportDetach = HCI_TransportDetach;
+    _HCI_TransportAddReceivePkts = HCI_TransportAddReceivePkts;
+    _HCI_TransportSendPkt = HCI_TransportSendPkt;
+    _HCI_TransportStop = HCI_TransportStop;
+    _HCI_TransportStart = HCI_TransportStart;
+    _HCI_TransportEnableDisableAsyncRecv = HCI_TransportEnableDisableAsyncRecv;
+    _HCI_TransportRecvHCIEventSync = HCI_TransportRecvHCIEventSync;
+    _HCI_TransportSetBaudRate = HCI_TransportSetBaudRate;
+
+    return A_OK;
+}
+
+A_STATUS
+ar6000_get_hif_dev(HIF_DEVICE *device, void *config)
+{
+    A_STATUS status;
+
+    status = HIFConfigureDevice(device,
+                                HIF_DEVICE_GET_OS_DEVICE,
+                                (HIF_DEVICE_OS_DEVICE_INFO *)config, 
+                                sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+    return status;
+}
+
+A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, 
+                                A_UINT32 scale, 
+                                A_UINT32 step)
+{
+    A_UINT32 regAddress;
+    A_UINT32 regVal;
+    A_STATUS status;
+
+    regAddress = WLAN_UART_BASE_ADDRESS | UART_CLKDIV_ADDRESS;
+    regVal = ((A_UINT32)scale << 16) | step;
+    /* change the HCI UART scale/step values through the diagnostic window */
+    status = ar6000_WriteRegDiag(hifDevice, &regAddress, &regVal);                     
+
+    return status;
+}
+
+A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data)
+{
+    A_UINT32 regAddress;
+    A_STATUS status;
+
+    regAddress = WLAN_RTC_BASE_ADDRESS | WLAN_CPU_CLOCK_ADDRESS;
+    /* read CPU clock settings*/
+    status = ar6000_ReadRegDiag(hifDevice, &regAddress, data);
+
+    return status;
+}
+
+EXPORT_SYMBOL(ar6000_register_hci_transport);
+EXPORT_SYMBOL(ar6000_get_hif_dev);
+EXPORT_SYMBOL(ar6000_set_uart_config);
+EXPORT_SYMBOL(ar6000_get_core_clock_config);
+EXPORT_SYMBOL(_HCI_TransportAttach);
+EXPORT_SYMBOL(_HCI_TransportDetach);
+EXPORT_SYMBOL(_HCI_TransportAddReceivePkts);
+EXPORT_SYMBOL(_HCI_TransportSendPkt);
+EXPORT_SYMBOL(_HCI_TransportStop);
+EXPORT_SYMBOL(_HCI_TransportStart);
+EXPORT_SYMBOL(_HCI_TransportEnableDisableAsyncRecv);
+EXPORT_SYMBOL(_HCI_TransportRecvHCIEventSync);
+EXPORT_SYMBOL(_HCI_TransportSetBaudRate);
diff --git a/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c
new file mode 100644
index 000000000000..3cbf5849e8fb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c
@@ -0,0 +1,1126 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include <linux/etherdevice.h>
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define  ATH_DEBUG_HCI_RECV      ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define  ATH_DEBUG_HCI_SEND      ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define  ATH_DEBUG_HCI_DUMP      ATH_DEBUG_MAKE_MODULE_MASK(9)
+#else
+#include "ar6000_drv.h"
+#endif  /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "epping_test.h"
+#include "gmboxif.h"
+#include "ar3kconfig.h"
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+    /* only build on newer kernels which have BT configured */
+#if defined(CONFIG_BT_MODULE) || defined(CONFIG_BT)
+#define CONFIG_BLUEZ_HCI_BRIDGE  
+#endif
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = 0;
+unsigned int hciuartscale = 0;
+unsigned int hciuartstep = 0;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(ar3khcibaud, int, 0644);
+module_param(hciuartscale, int, 0644);
+module_param(hciuartstep, int, 0644);
+#else
+
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(ar3khcibaud, "i");
+MODULE_PARM(hciuartscale, "i");
+MODULE_PARM(hciuartstep, "i");
+#endif
+#else
+extern unsigned int ar3khcibaud;
+extern unsigned int hciuartscale;
+extern unsigned int hciuartstep;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+typedef struct {
+    void                    *pHCIDev;          /* HCI bridge device */
+    HCI_TRANSPORT_PROPERTIES HCIProps;         /* HCI bridge props */
+    struct hci_dev          *pBtStackHCIDev;   /* BT Stack HCI dev */
+    A_BOOL                  HciNormalMode;     /* Actual HCI mode enabled (non-TEST)*/
+    A_BOOL                  HciRegistered;     /* HCI device registered with stack */
+    HTC_PACKET_QUEUE        HTCPacketStructHead;
+    A_UINT8                 *pHTCStructAlloc;
+    spinlock_t              BridgeLock;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    HCI_TRANSPORT_MISC_HANDLES    HCITransHdl; 
+#else
+    AR_SOFTC_T              *ar;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+} AR6K_HCI_BRIDGE_INFO;
+
+#define MAX_ACL_RECV_BUFS           16
+#define MAX_EVT_RECV_BUFS           8
+#define MAX_HCI_WRITE_QUEUE_DEPTH   32
+#define MAX_ACL_RECV_LENGTH         1200
+#define MAX_EVT_RECV_LENGTH         257
+#define TX_PACKET_RSV_OFFSET        32
+#define NUM_HTC_PACKET_STRUCTS     ((MAX_ACL_RECV_BUFS + MAX_EVT_RECV_BUFS + MAX_HCI_WRITE_QUEUE_DEPTH) * 2)
+
+#define HCI_GET_OP_CODE(p)          (((A_UINT16)((p)[1])) << 8) | ((A_UINT16)((p)[0]))
+
+extern unsigned int setupbtdev;
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+AR6K_HCI_BRIDGE_INFO *g_pHcidevInfo;
+#endif
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static void     bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_BOOL   bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                                 HCI_TRANSPORT_PACKET_TYPE Type, 
+                                 struct sk_buff            *skb);
+static struct sk_buff *bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length);
+static void     bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb);   
+                               
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar);
+void     ar6000_cleanup_hci(void *ar);
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb);
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void     ar6000_cleanup_hci(AR_SOFTC_T *ar);
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#define LOCK_BRIDGE(dev)   spin_lock_bh(&(dev)->BridgeLock)
+#define UNLOCK_BRIDGE(dev) spin_unlock_bh(&(dev)->BridgeLock)
+
+static inline void FreeBtOsBuf(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, void *osbuf)
+{    
+    if (pHcidevInfo->HciNormalMode) {
+        bt_free_buffer(pHcidevInfo, (struct sk_buff *)osbuf);
+    } else {
+            /* in test mode, these are just ordinary netbuf allocations */
+        A_NETBUF_FREE(osbuf);
+    }
+}
+
+static void FreeHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, HTC_PACKET *pPacket)
+{
+    LOCK_BRIDGE(pHcidevInfo);
+    HTC_PACKET_ENQUEUE(&pHcidevInfo->HTCPacketStructHead,pPacket);
+    UNLOCK_BRIDGE(pHcidevInfo);  
+}
+
+static HTC_PACKET * AllocHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    HTC_PACKET  *pPacket = NULL;
+    LOCK_BRIDGE(pHcidevInfo);
+    pPacket = HTC_PACKET_DEQUEUE(&pHcidevInfo->HTCPacketStructHead);
+    UNLOCK_BRIDGE(pHcidevInfo);  
+    return pPacket;
+}
+
+#define BLOCK_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
+
+static void RefillRecvBuffers(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                              HCI_TRANSPORT_PACKET_TYPE Type, 
+                              int                       NumBuffers)
+{
+    int                 length, i;
+    void                *osBuf = NULL;
+    HTC_PACKET_QUEUE    queue;
+    HTC_PACKET          *pPacket;
+
+    INIT_HTC_PACKET_QUEUE(&queue);
+    
+    if (Type == HCI_ACL_TYPE) {     
+        if (pHcidevInfo->HciNormalMode) {  
+            length = HCI_MAX_FRAME_SIZE;
+        } else {
+            length = MAX_ACL_RECV_LENGTH;    
+        }
+    } else {
+        length = MAX_EVT_RECV_LENGTH;
+    }
+    
+        /* add on transport head and tail room */ 
+    length += pHcidevInfo->HCIProps.HeadRoom + pHcidevInfo->HCIProps.TailRoom;
+        /* round up to the required I/O padding */      
+    length = BLOCK_ROUND_UP_PWR2(length,pHcidevInfo->HCIProps.IOBlockPad);
+             
+    for (i = 0; i < NumBuffers; i++) {   
+           
+        if (pHcidevInfo->HciNormalMode) {   
+            osBuf = bt_alloc_buffer(pHcidevInfo,length);       
+        } else {
+            osBuf = A_NETBUF_ALLOC(length);  
+        }
+          
+        if (NULL == osBuf) {
+            break;    
+        }            
+         
+        pPacket = AllocHTCStruct(pHcidevInfo);
+        if (NULL == pPacket) {
+            FreeBtOsBuf(pHcidevInfo,osBuf);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+            break;    
+        }     
+        
+        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),length,Type);
+            /* add to queue */
+        HTC_PACKET_ENQUEUE(&queue,pPacket);
+    }
+    
+    if (i > 0) {
+        HCI_TransportAddReceivePkts(pHcidevInfo->pHCIDev, &queue);    
+    }
+}
+
+static A_STATUS ar6000_hci_transport_ready(HCI_TRANSPORT_HANDLE     HCIHandle, 
+                                           HCI_TRANSPORT_PROPERTIES *pProps, 
+                                           void                     *pContext)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    A_STATUS              status;
+    AR3K_CONFIG_INFO      ar3kconfig;
+    
+    pHcidevInfo->pHCIDev = HCIHandle;
+    
+    A_MEMCPY(&pHcidevInfo->HCIProps,pProps,sizeof(*pProps));
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE,("HCI ready (hci:0x%X, headroom:%d, tailroom:%d blockpad:%d) \n", 
+            (A_UINT32)HCIHandle, 
+            pHcidevInfo->HCIProps.HeadRoom, 
+            pHcidevInfo->HCIProps.TailRoom,
+            pHcidevInfo->HCIProps.IOBlockPad));
+    
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice)->hard_header_len);
+#else
+    A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= pHcidevInfo->ar->arNetDev->hard_header_len);
+#endif
+                             
+        /* provide buffers */
+    RefillRecvBuffers(pHcidevInfo, HCI_ACL_TYPE, MAX_ACL_RECV_BUFS);
+    RefillRecvBuffers(pHcidevInfo, HCI_EVENT_TYPE, MAX_EVT_RECV_BUFS);
+   
+    do {
+            /* start transport */
+        status = HCI_TransportStart(pHcidevInfo->pHCIDev);
+         
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (!pHcidevInfo->HciNormalMode) {
+                /* in test mode, no need to go any further */
+            break;    
+        }
+
+        // The delay is required when AR6K is driving the BT reset line
+        // where time is needed after the BT chip is out of reset (HCI_TransportStart)
+        // and before the first HCI command is issued (AR3KConfigure)
+        // FIXME
+        // The delay should be configurable and be only applied when AR6K driving the BT
+        // reset line. This could be done by some module parameter or based on some HW config
+        // info. For now apply 100ms delay blindly
+        A_MDELAY(100);
+        
+        A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+        ar3kconfig.pHCIDev = pHcidevInfo->pHCIDev;
+        ar3kconfig.pHCIProps = &pHcidevInfo->HCIProps;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        ar3kconfig.pHIFDevice = (HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice);
+#else
+        ar3kconfig.pHIFDevice = pHcidevInfo->ar->arHifDevice;
+#endif
+        ar3kconfig.pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+        
+        if (ar3khcibaud != 0) {
+                /* user wants ar3k baud rate change */
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY;
+            ar3kconfig.AR3KBaudRate = ar3khcibaud;    
+        }
+        
+        if ((hciuartscale != 0) || (hciuartstep != 0)) {   
+                /* user wants to tune HCI bridge UART scale/step values */
+            ar3kconfig.AR6KScale = (A_UINT16)hciuartscale;
+            ar3kconfig.AR6KStep = (A_UINT16)hciuartstep;           
+            ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP;
+        }
+        
+            /* configure the AR3K device */         
+        status = AR3KConfigure(&ar3kconfig);
+        if (A_FAILED(status)) {
+            break; 
+        }
+        
+        status = bt_register_hci(pHcidevInfo);
+        
+    } while (FALSE);
+
+    return status; 
+}
+
+static void ar6000_hci_transport_failure(void *pContext, A_STATUS Status)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: transport failure! \n"));
+    
+    if (pHcidevInfo->HciNormalMode) {
+        /* TODO .. */    
+    }
+}
+
+static void ar6000_hci_transport_removed(void *pContext)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: transport removed. \n"));
+    
+    A_ASSERT(pHcidevInfo->pHCIDev != NULL);
+        
+    HCI_TransportDetach(pHcidevInfo->pHCIDev);
+    bt_cleanup_hci(pHcidevInfo);
+    pHcidevInfo->pHCIDev = NULL;
+}
+
+static void ar6000_hci_send_complete(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    void                 *osbuf = pPacket->pPktContext;
+    A_ASSERT(osbuf != NULL);
+    A_ASSERT(pHcidevInfo != NULL);
+    
+    if (A_FAILED(pPacket->Status)) {
+        if ((pPacket->Status != A_ECANCELED) && (pPacket->Status != A_NO_RESOURCE)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: Send Packet Failed: %d \n",pPacket->Status)); 
+        }   
+    }
+            
+    FreeHTCStruct(pHcidevInfo,pPacket);    
+    FreeBtOsBuf(pHcidevInfo,osbuf);
+    
+}
+
+static void ar6000_hci_pkt_recv(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    struct sk_buff       *skb;
+    
+    A_ASSERT(pHcidevInfo != NULL);
+    skb = (struct sk_buff *)pPacket->pPktContext;
+    A_ASSERT(skb != NULL);
+          
+    do {
+        
+        if (A_FAILED(pPacket->Status)) {
+            break;
+        }
+  
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, 
+                        ("HCI Bridge, packet received type : %d len:%d \n",
+                        HCI_GET_PACKET_TYPE(pPacket),pPacket->ActualLength));
+    
+            /* set the actual buffer position in the os buffer, HTC recv buffers posted to HCI are set
+             * to fill the front of the buffer */
+        A_NETBUF_PUT(skb,pPacket->ActualLength + pHcidevInfo->HCIProps.HeadRoom);
+        A_NETBUF_PULL(skb,pHcidevInfo->HCIProps.HeadRoom);
+        
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("<<< Recv HCI %s packet len:%d \n",
+                        (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) ? "EVENT" : "ACL",
+                        skb->len));
+            AR_DEBUG_PRINTBUF(skb->data, skb->len,"BT HCI RECV Packet Dump");
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {
+                /* indicate the packet */         
+            if (bt_indicate_recv(pHcidevInfo,HCI_GET_PACKET_TYPE(pPacket),skb)) {
+                    /* bt stack accepted the packet */
+                skb = NULL;
+            }  
+            break;
+        }
+        
+            /* for testing, indicate packet to the network stack */ 
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        skb->dev = (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice);        
+        if ((((struct net_device *)pHcidevInfo->HCITransHdl.netDevice)->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = eth_type_trans(skb, (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice));
+#else
+        skb->dev = pHcidevInfo->ar->arNetDev;        
+        if ((pHcidevInfo->ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+            skb->protocol = eth_type_trans(skb, pHcidevInfo->ar->arNetDev);
+#endif
+            netif_rx(skb);
+            skb = NULL;
+        } 
+        
+    } while (FALSE);
+    
+    FreeHTCStruct(pHcidevInfo,pPacket);
+    
+    if (skb != NULL) {
+            /* packet was not accepted, free it */
+        FreeBtOsBuf(pHcidevInfo,skb);       
+    }
+    
+}
+
+static void  ar6000_hci_pkt_refill(void *pContext, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    int                  refillCount;
+
+    if (Type == HCI_ACL_TYPE) {
+        refillCount =  MAX_ACL_RECV_BUFS - BuffersAvailable;   
+    } else {
+        refillCount =  MAX_EVT_RECV_BUFS - BuffersAvailable;     
+    }
+    
+    if (refillCount > 0) {
+        RefillRecvBuffers(pHcidevInfo,Type,refillCount);
+    }
+    
+}
+
+static HCI_SEND_FULL_ACTION  ar6000_hci_pkt_send_full(void *pContext, HTC_PACKET *pPacket)
+{
+    AR6K_HCI_BRIDGE_INFO    *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+    HCI_SEND_FULL_ACTION    action = HCI_SEND_FULL_KEEP;
+    
+    if (!pHcidevInfo->HciNormalMode) {
+            /* for epping testing, check packet tag, some epping packets are
+             * special and cannot be dropped */
+        if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_DATA_PKT_TAG) {
+            action = HCI_SEND_FULL_DROP;     
+        }
+    }
+    
+    return action;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    HCI_TRANSPORT_CONFIG_INFO config;
+    A_STATUS                  status = A_OK;
+    int                       i;
+    HTC_PACKET                *pPacket;
+    AR6K_HCI_BRIDGE_INFO      *pHcidevInfo;
+        
+       
+    do {
+        
+        pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)A_MALLOC(sizeof(AR6K_HCI_BRIDGE_INFO));
+        
+        if (NULL == pHcidevInfo) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        A_MEMZERO(pHcidevInfo, sizeof(AR6K_HCI_BRIDGE_INFO));
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        g_pHcidevInfo = pHcidevInfo;
+        pHcidevInfo->HCITransHdl = *(HCI_TRANSPORT_MISC_HANDLES *)ar;
+#else
+        ar->hcidev_info = pHcidevInfo;
+        pHcidevInfo->ar = ar;
+#endif
+        spin_lock_init(&pHcidevInfo->BridgeLock);
+        INIT_HTC_PACKET_QUEUE(&pHcidevInfo->HTCPacketStructHead);
+
+        ar->exitCallback = AR3KConfigureExit;
+    
+        status = bt_setup_hci(pHcidevInfo);
+        if (A_FAILED(status)) {
+            break;    
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {      
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in normal mode... \n"));    
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in test mode... \n"));     
+        }
+        
+        pHcidevInfo->pHTCStructAlloc = (A_UINT8 *)A_MALLOC((sizeof(HTC_PACKET)) * NUM_HTC_PACKET_STRUCTS);
+        
+        if (NULL == pHcidevInfo->pHTCStructAlloc) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        pPacket = (HTC_PACKET *)pHcidevInfo->pHTCStructAlloc;
+        for (i = 0; i < NUM_HTC_PACKET_STRUCTS; i++,pPacket++) {
+            FreeHTCStruct(pHcidevInfo,pPacket);                
+        }
+        
+        A_MEMZERO(&config,sizeof(HCI_TRANSPORT_CONFIG_INFO));        
+        config.ACLRecvBufferWaterMark = MAX_ACL_RECV_BUFS / 2;
+        config.EventRecvBufferWaterMark = MAX_EVT_RECV_BUFS / 2;
+        config.MaxSendQueueDepth = MAX_HCI_WRITE_QUEUE_DEPTH;
+        config.pContext = pHcidevInfo;    
+        config.TransportFailure = ar6000_hci_transport_failure;
+        config.TransportReady = ar6000_hci_transport_ready;
+        config.TransportRemoved = ar6000_hci_transport_removed;
+        config.pHCISendComplete = ar6000_hci_send_complete;
+        config.pHCIPktRecv = ar6000_hci_pkt_recv;
+        config.pHCIPktRecvRefill = ar6000_hci_pkt_refill;
+        config.pHCISendFull = ar6000_hci_pkt_send_full;
+       
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        pHcidevInfo->pHCIDev = HCI_TransportAttach(pHcidevInfo->HCITransHdl.htcHandle, &config);
+#else
+        pHcidevInfo->pHCIDev = HCI_TransportAttach(ar->arHtcTarget, &config);
+#endif
+
+        if (NULL == pHcidevInfo->pHCIDev) {
+            status = A_ERROR;      
+        }
+    
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        if (pHcidevInfo != NULL) {
+            if (NULL == pHcidevInfo->pHCIDev) {
+                /* GMBOX may not be present in older chips */
+                /* just return success */ 
+                status = A_OK;
+            }
+        }
+        ar6000_cleanup_hci(ar);    
+    }
+    
+    return status;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void  ar6000_cleanup_hci(void *ar)
+#else
+void  ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+    
+    if (pHcidevInfo != NULL) {
+        bt_cleanup_hci(pHcidevInfo);   
+        
+        if (pHcidevInfo->pHCIDev != NULL) {
+            HCI_TransportStop(pHcidevInfo->pHCIDev);
+            HCI_TransportDetach(pHcidevInfo->pHCIDev);
+            pHcidevInfo->pHCIDev = NULL;
+        } 
+        
+        if (pHcidevInfo->pHTCStructAlloc != NULL) {
+            A_FREE(pHcidevInfo->pHTCStructAlloc);
+            pHcidevInfo->pHTCStructAlloc = NULL;    
+        }
+        
+        A_FREE(pHcidevInfo);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+        ar->hcidev_info = NULL;
+#endif
+    }
+    
+    
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb)
+#else
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+    int              status = A_OK;
+    int              length;
+    EPPING_HEADER    *pHeader;
+    HTC_PACKET       *pPacket;   
+    HTC_TX_TAG       htc_tag = AR6K_DATA_PKT_TAG;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+            
+    do {
+        
+        if (NULL == pHcidevInfo) {
+            status = A_ERROR;
+            break;    
+        }
+        
+        if (NULL == pHcidevInfo->pHCIDev) {
+            status = A_ERROR;
+            break;    
+        }
+        
+        if (pHcidevInfo->HciNormalMode) {
+                /* this interface cannot run when normal WMI is running */
+            status = A_ERROR;
+            break;    
+        }
+        
+        pHeader = (EPPING_HEADER *)A_NETBUF_DATA(skb);
+        
+        if (!IS_EPPING_PACKET(pHeader)) {
+            status = A_EINVAL;
+            break;
+        }
+                       
+        if (IS_EPING_PACKET_NO_DROP(pHeader)) {
+            htc_tag = AR6K_CONTROL_PKT_TAG;   
+        }
+        
+        length = sizeof(EPPING_HEADER) + pHeader->DataLength;
+                
+        pPacket = AllocHTCStruct(pHcidevInfo);
+        if (NULL == pPacket) {        
+            status = A_NO_MEMORY;
+            break;
+        } 
+     
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               skb,
+                               A_NETBUF_DATA(skb),
+                               length,
+                               HCI_ACL_TYPE,  /* send every thing out as ACL */
+                               htc_tag);
+             
+        HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);                           
+        pPacket = NULL;
+            
+    } while (FALSE);
+            
+    return status;
+}
+
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+    AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+    AR3K_CONFIG_INFO *config = (AR3K_CONFIG_INFO *)ar3kconfig;
+
+    config->pHCIDev = pHcidevInfo->pHCIDev;
+    config->pHCIProps = &pHcidevInfo->HCIProps;
+    config->pHIFDevice = ar->arHifDevice;
+    config->pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+    config->Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+    config->AR3KBaudRate = 115200;    
+}
+
+#ifdef CONFIG_BLUEZ_HCI_BRIDGE   
+/*** BT Stack Entrypoints *******/
+
+/*
+ * bt_open - open a handle to the device
+*/
+static int bt_open(struct hci_dev *hdev)
+{
+ 
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_open - enter - x\n"));
+    set_bit(HCI_RUNNING, &hdev->flags);
+    set_bit(HCI_UP, &hdev->flags);
+    set_bit(HCI_INIT, &hdev->flags);         
+    return 0;
+}
+
+/*
+ * bt_close - close handle to the device
+*/
+static int bt_close(struct hci_dev *hdev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_close - enter\n"));
+    clear_bit(HCI_RUNNING, &hdev->flags);
+    return 0;
+}
+
+/*
+ * bt_send_frame - send data frames
+*/
+static int bt_send_frame(struct sk_buff *skb)
+{
+    struct hci_dev             *hdev = (struct hci_dev *)skb->dev;
+    HCI_TRANSPORT_PACKET_TYPE  type;
+    AR6K_HCI_BRIDGE_INFO       *pHcidevInfo;
+    A_UINT8                    *pTemp;
+    HTC_PACKET                 *pPacket;
+    A_STATUS                   status = A_OK;
+    struct sk_buff             *txSkb = NULL;
+    
+    if (!hdev) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_send_frame - no device\n"));
+        return -ENODEV;
+    }
+      
+    if (!test_bit(HCI_RUNNING, &hdev->flags)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_send_frame - not open\n"));
+        return -EBUSY;
+    }
+  
+    pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;   
+    A_ASSERT(pHcidevInfo != NULL);
+      
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("+bt_send_frame type: %d \n",bt_cb(skb)->pkt_type));
+    type = HCI_COMMAND_TYPE;
+    
+    switch (bt_cb(skb)->pkt_type) {
+        case HCI_COMMAND_PKT:
+            type = HCI_COMMAND_TYPE;
+            hdev->stat.cmd_tx++;
+            break;
+ 
+        case HCI_ACLDATA_PKT:
+            type = HCI_ACL_TYPE;
+            hdev->stat.acl_tx++;
+            break;
+
+        case HCI_SCODATA_PKT:
+            /* we don't support SCO over the bridge */
+            kfree_skb(skb);
+            return 0;
+        default:
+            A_ASSERT(FALSE);
+            kfree_skb(skb);
+            return 0;
+    } 
+
+    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(">>> Send HCI %s packet len: %d\n",
+                        (type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
+                        skb->len));
+        if (type == HCI_COMMAND_TYPE) {
+            A_UINT16 opcode = HCI_GET_OP_CODE(skb->data);
+            AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("    HCI Command: OGF:0x%X OCF:0x%X \r\n", 
+                  opcode >> 10, opcode & 0x3FF));
+        }
+        AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
+    }
+    
+    do {
+        
+        txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom + 
+                             pHcidevInfo->HCIProps.TailRoom + skb->len, 
+                             GFP_ATOMIC);
+
+        if (txSkb == NULL) {
+            status = A_NO_MEMORY;
+            break;    
+        }
+        
+        bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
+        txSkb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+        skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom);
+        A_MEMCPY(txSkb->data, skb->data, skb->len);
+        skb_put(txSkb,skb->len);
+        
+            /* push on header transport space */
+        pTemp = (A_UINT8 *)skb_push(txSkb, pHcidevInfo->HCIProps.HeadRoom);           
+        pPacket = AllocHTCStruct(pHcidevInfo);        
+        if (NULL == pPacket) {
+            status = A_NO_MEMORY;
+            break;    
+        }       
+              
+        SET_HTC_PACKET_INFO_TX(pPacket,
+                               txSkb,
+                               pTemp + pHcidevInfo->HCIProps.HeadRoom, 
+                               txSkb->len,
+                               type, 
+                               AR6K_CONTROL_PKT_TAG); /* HCI packets cannot be dropped */
+        
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: bt_send_frame skb:0x%X \n",(A_UINT32)txSkb));
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: type:%d, Total Length:%d Bytes \n",
+                                      type, txSkb->len));
+                                      
+        status = HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);   
+        pPacket = NULL;
+        txSkb = NULL;
+        
+    } while (FALSE);
+   
+    if (txSkb != NULL) {
+        kfree_skb(txSkb);    
+    }
+    
+    kfree_skb(skb);        
+       
+    AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("-bt_send_frame  \n"));
+    return 0;
+}
+
+/*
+ * bt_ioctl - ioctl processing
+*/
+static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_ioctl - enter\n"));
+    return -ENOIOCTLCMD;
+}
+
+/*
+ * bt_flush - flush outstandingbpackets
+*/
+static int bt_flush(struct hci_dev *hdev)
+{
+    AR6K_HCI_BRIDGE_INFO    *pHcidevInfo; 
+    
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_flush - enter\n"));
+    
+    pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;   
+    
+    /* TODO??? */   
+    
+    return 0;
+}
+
+
+/*
+ * bt_destruct - 
+*/
+static void bt_destruct(struct hci_dev *hdev)
+{
+    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_destruct - enter\n"));
+    /* nothing to do here */
+}
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    A_STATUS                    status = A_OK;
+    struct hci_dev              *pHciDev = NULL;
+    HIF_DEVICE_OS_DEVICE_INFO   osDevInfo;
+    
+    if (!setupbtdev) {
+        return A_OK;    
+    } 
+        
+    do {
+            
+        A_MEMZERO(&osDevInfo,sizeof(osDevInfo));
+            /* get the underlying OS device */
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+        status = ar6000_get_hif_dev((HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice), 
+                                    &osDevInfo);
+#else
+        status = HIFConfigureDevice(pHcidevInfo->ar->arHifDevice, 
+                                    HIF_DEVICE_GET_OS_DEVICE,
+                                    &osDevInfo, 
+                                    sizeof(osDevInfo));
+#endif
+                                    
+        if (A_FAILED(status)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to OS device info from HIF\n"));
+            break;
+        }
+        
+            /* allocate a BT HCI struct for this device */
+        pHciDev = hci_alloc_dev();
+        if (NULL == pHciDev) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge - failed to allocate bt struct \n"));
+            status = A_NO_MEMORY;
+            break;
+        }    
+            /* save the device, we'll register this later */
+        pHcidevInfo->pBtStackHCIDev = pHciDev;       
+        SET_HCIDEV_DEV(pHciDev,osDevInfo.pOSDevice);          
+        pHciDev->type = HCI_VIRTUAL;
+        pHciDev->driver_data = pHcidevInfo;
+        pHciDev->open     = bt_open;
+        pHciDev->close    = bt_close;
+        pHciDev->send     = bt_send_frame;
+        pHciDev->ioctl    = bt_ioctl;
+        pHciDev->flush    = bt_flush;
+        pHciDev->destruct = bt_destruct;
+        pHciDev->owner = THIS_MODULE; 
+            /* driver is running in normal BT mode */
+        pHcidevInfo->HciNormalMode = TRUE;  
+        
+    } while (FALSE);
+    
+    if (A_FAILED(status)) {
+        bt_cleanup_hci(pHcidevInfo);    
+    }
+    
+    return status;
+}
+
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{   
+    int   err;      
+        
+    if (pHcidevInfo->HciRegistered) {
+        pHcidevInfo->HciRegistered = FALSE;
+        clear_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags);
+        clear_bit(HCI_UP, &pHcidevInfo->pBtStackHCIDev->flags);
+        clear_bit(HCI_INIT, &pHcidevInfo->pBtStackHCIDev->flags);   
+        A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+            /* unregister */
+        if ((err = hci_unregister_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to unregister with bluetooth %d\n",err));
+        }          
+    }   
+    
+    if (pHcidevInfo->pBtStackHCIDev != NULL) {
+        kfree(pHcidevInfo->pBtStackHCIDev);
+        pHcidevInfo->pBtStackHCIDev = NULL;
+    }  
+}
+
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    int       err;
+    A_STATUS  status = A_OK;
+    
+    do {          
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: registering HCI... \n"));
+        A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+             /* mark that we are registered */
+        pHcidevInfo->HciRegistered = TRUE;
+        if ((err = hci_register_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to register with bluetooth %d\n",err));
+            pHcidevInfo->HciRegistered = FALSE;
+            status = A_ERROR;
+            break;
+        }
+    
+        AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: HCI registered \n"));
+        
+    } while (FALSE);
+    
+    return status;
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                               HCI_TRANSPORT_PACKET_TYPE Type, 
+                               struct                    sk_buff *skb)
+{
+    A_UINT8               btType;
+    int                   len;
+    A_BOOL                success = FALSE;
+    BT_HCI_EVENT_HEADER   *pEvent;
+    
+    do {
+             
+        if (!test_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags)) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_indicate_recv - not running\n"));
+            break;
+        }
+    
+        switch (Type) {
+            case HCI_ACL_TYPE:
+                btType = HCI_ACLDATA_PKT;
+                break;
+            case HCI_EVENT_TYPE:  
+                btType = HCI_EVENT_PKT;  
+                break;
+            default:
+                btType = 0;
+                A_ASSERT(FALSE);
+                break;
+        } 
+        
+        if (0 == btType) {
+            break;    
+        }
+        
+            /* set the final type */
+        bt_cb(skb)->pkt_type = btType;
+            /* set dev */
+        skb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+        len = skb->len;
+        
+        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_RECV)) {
+            if (bt_cb(skb)->pkt_type == HCI_EVENT_PKT) {                
+                pEvent = (BT_HCI_EVENT_HEADER *)skb->data; 
+                AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, ("BT HCI EventCode: %d, len:%d \n", 
+                        pEvent->EventCode, pEvent->ParamLength));
+            } 
+        }
+        
+            /* pass receive packet up the stack */    
+        if (hci_recv_frame(skb) != 0) {
+            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: hci_recv_frame failed \n"));
+            break;
+        } else {
+            AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, 
+                    ("HCI Bridge: Indicated RCV of type:%d, Length:%d \n",btType,len));
+        }
+            
+        success = TRUE;
+    
+    } while (FALSE); 
+    
+    return success;
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) 
+{ 
+    struct sk_buff *skb;         
+        /* in normal HCI mode we need to alloc from the bt core APIs */
+    skb = bt_skb_alloc(Length, GFP_ATOMIC);
+    if (NULL == skb) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc bt sk_buff \n"));
+    }
+    return skb;
+}
+
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+    kfree_skb(skb);    
+}
+
+#else // { CONFIG_BLUEZ_HCI_BRIDGE
+
+    /* stubs when we only want to test the HCI bridging Interface without the HT stack */
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    return A_OK;    
+}
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{   
+     
+}
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+    A_ASSERT(FALSE);
+    return A_ERROR;    
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO      *pHcidevInfo, 
+                               HCI_TRANSPORT_PACKET_TYPE Type, 
+                               struct                    sk_buff *skb)
+{
+    A_ASSERT(FALSE);
+    return FALSE;    
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) 
+{
+    A_ASSERT(FALSE);
+    return NULL;
+}
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+    A_ASSERT(FALSE);
+}
+
+#endif // } CONFIG_BLUEZ_HCI_BRIDGE
+
+#else  // { ATH_AR6K_ENABLE_GMBOX
+
+    /* stubs when GMBOX support is not needed */
+    
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    return A_OK;   
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_cleanup_hci(void *ar)
+#else
+void ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+    return;    
+}
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+    return;
+}
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+int hci_test_send(void *ar, struct sk_buff *skb)
+#else
+int hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+    return -EOPNOTSUPP;
+}
+
+#endif // } ATH_AR6K_ENABLE_GMBOX
+
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+static int __init
+hcibridge_init_module(void)
+{
+    A_STATUS status;
+    HCI_TRANSPORT_CALLBACKS hciTransCallbacks;
+
+    hciTransCallbacks.setupTransport = ar6000_setup_hci;
+    hciTransCallbacks.cleanupTransport = ar6000_cleanup_hci;
+
+    status = ar6000_register_hci_transport(&hciTransCallbacks);
+    if(status != A_OK)
+        return -ENODEV;
+
+    return 0;
+}
+
+static void __exit
+hcibridge_cleanup_module(void)
+{
+}
+
+module_init(hcibridge_init_module);
+module_exit(hcibridge_cleanup_module);
+MODULE_LICENSE("GPL and additional rights");
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h
new file mode 100644
index 000000000000..3df15b71133a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h
@@ -0,0 +1,694 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _AR6000_H_
+#define _AR6000_H_
+
+#include <linux/version.h>
+
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17)
+#include <linux/config.h>
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
+#include <linux/autoconf.h>
+#else
+#include <generated/autoconf.h>
+#endif
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/skbuff.h>
+#include <linux/if_ether.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/iw_handler.h>
+#include <linux/if_arp.h>
+#include <linux/ip.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+#include <asm/semaphore.h>
+#else
+#include <linux/semaphore.h>
+#endif
+#include <linux/wireless.h>
+#ifdef ATH6K_CONFIG_CFG80211
+#include <net/cfg80211.h>
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include <linux/module.h>
+#include <asm/io.h>
+
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "bmi.h"
+#include <ieee80211.h>
+#include <ieee80211_ioctl.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include "gpio_api.h"
+#include "gpio.h"
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include <host_version.h>
+#include <linux/rtnetlink.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+#include <asm/uaccess.h>
+#else
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#endif
+#include "ar6000_api.h"
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#include <testcmd.h>
+#endif
+#include <linux/firmware.h>
+
+#include "targaddrs.h"
+#include "dbglog_api.h"
+#include "ar6000_diag.h"
+#include "common_drv.h"
+#include "roaming.h"
+#include "hci_transport_api.h"
+#define ATH_MODULE_NAME driver
+#include "a_debug.h"
+#include "hw/apb_map.h"
+#include "hw/rtc_reg.h"
+#include "hw/mbox_reg.h"
+#include "hw/gpio_reg.h"
+
+#define  ATH_DEBUG_DBG_LOG       ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define  ATH_DEBUG_WLAN_CONNECT  ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define  ATH_DEBUG_WLAN_SCAN     ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define  ATH_DEBUG_WLAN_TX       ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define  ATH_DEBUG_WLAN_RX       ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define  ATH_DEBUG_HTC_RAW       ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define  ATH_DEBUG_HCI_BRIDGE    ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define  ATH_DEBUG_HCI_RECV      ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define  ATH_DEBUG_HCI_SEND      ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define  ATH_DEBUG_HCI_DUMP      ATH_DEBUG_MAKE_MODULE_MASK(9)
+
+#ifndef  __dev_put
+#define  __dev_put(dev) dev_put(dev)
+#endif
+
+
+#ifdef USER_KEYS
+
+#define USER_SAVEDKEYS_STAT_INIT     0
+#define USER_SAVEDKEYS_STAT_RUN      1
+
+// TODO this needs to move into the AR_SOFTC struct
+struct USER_SAVEDKEYS {
+    struct ieee80211req_key   ucast_ik;
+    struct ieee80211req_key   bcast_ik;
+    CRYPTO_TYPE               keyType;
+    A_BOOL                    keyOk;
+};
+#endif
+
+#define DBG_INFO        0x00000001
+#define DBG_ERROR       0x00000002
+#define DBG_WARNING     0x00000004
+#define DBG_SDIO        0x00000008
+#define DBG_HIF         0x00000010
+#define DBG_HTC         0x00000020
+#define DBG_WMI         0x00000040
+#define DBG_WMI2        0x00000080
+#define DBG_DRIVER      0x00000100
+
+#define DBG_DEFAULTS    (DBG_ERROR|DBG_WARNING)
+
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_AR6000                        1
+#define AR6000_MAX_RX_BUFFERS             16
+#define AR6000_BUFFER_SIZE                1664
+#define AR6000_MAX_AMSDU_RX_BUFFERS       4
+#define AR6000_AMSDU_REFILL_THRESHOLD     3
+#define AR6000_AMSDU_BUFFER_SIZE          (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
+#define AR6000_MAX_RX_MESSAGE_SIZE        (max(WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH,WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))
+
+#define AR6000_TX_TIMEOUT                 10
+#define AR6000_ETH_ADDR_LEN               6
+#define AR6000_MAX_ENDPOINTS              4
+#define MAX_NODE_NUM                      15
+/* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
+#define MAX_DEF_COOKIE_NUM                150
+#define MAX_HI_COOKIE_NUM                 15 /* 10% of MAX_COOKIE_NUM */
+#define MAX_COOKIE_NUM                    (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
+
+/* MAX_DEFAULT_SEND_QUEUE_DEPTH is used to set the default queue depth for the
+ * WMM send queues.  If a queue exceeds this depth htc will query back to the
+ * OS specific layer by calling EpSendFull().  This gives the OS layer the
+ * opportunity to drop the packet if desired.  Therefore changing
+ * MAX_DEFAULT_SEND_QUEUE_DEPTH does not affect resource utilization but
+ * does impact the threshold used to identify if a packet should be
+ * dropped. */
+#define MAX_DEFAULT_SEND_QUEUE_DEPTH      (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
+
+#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT        1
+#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT  1
+#define A_DISCONNECT_TIMER_INTERVAL       10 * 1000
+#define A_DEFAULT_LISTEN_INTERVAL         100
+#define A_MAX_WOW_LISTEN_INTERVAL         1000
+
+enum {
+    DRV_HB_CHALLENGE = 0,
+    APP_HB_CHALLENGE
+};
+
+enum {
+    WLAN_INIT_MODE_NONE = 0,
+    WLAN_INIT_MODE_USR,
+    WLAN_INIT_MODE_UDEV,
+    WLAN_INIT_MODE_DRV
+};
+
+typedef enum _AR6K_BIN_FILE {
+    AR6K_OTP_FILE,
+    AR6K_FIRMWARE_FILE,
+    AR6K_PATCH_FILE,
+    AR6K_BOARD_DATA_FILE,
+} AR6K_BIN_FILE;
+
+#ifdef SETUPHCI_ENABLED
+#define SETUPHCI_DEFAULT           1
+#else
+#define SETUPHCI_DEFAULT           0
+#endif /* SETUPHCI_ENABLED */
+
+#ifdef SETUPBTDEV_ENABLED
+#define SETUPBTDEV_DEFAULT         1
+#else
+#define SETUPBTDEV_DEFAULT         0
+#endif /* SETUPBTDEV_ENABLED */
+
+#ifdef BMIENABLE_SET
+#define BMIENABLE_DEFAULT          1
+#else
+#define BMIENABLE_DEFAULT          0
+#endif /* BMIENABLE_SET */
+
+#ifdef ENABLEUARTPRINT_SET
+#define ENABLEUARTPRINT_DEFAULT    1
+#else
+#define ENABLEUARTPRINT_DEFAULT    0
+#endif /* ENABLEARTPRINT_SET */
+
+#ifdef ATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+#define NOHIFSCATTERSUPPORT_DEFAULT    1
+#else /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+#define NOHIFSCATTERSUPPORT_DEFAULT    0
+#endif /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+
+#ifdef AR600x_BT_AR3001
+#define AR3KHCIBAUD_DEFAULT        3000000
+#define HCIUARTSCALE_DEFAULT       1
+#define HCIUARTSTEP_DEFAULT        8937
+#else
+#define AR3KHCIBAUD_DEFAULT        0
+#define HCIUARTSCALE_DEFAULT       0
+#define HCIUARTSTEP_DEFAULT        0
+#endif /* AR600x_BT_AR3001 */
+
+#ifdef INIT_MODE_DRV_ENABLED
+#define WLAN_INIT_MODE_DEFAULT     WLAN_INIT_MODE_DRV
+#else
+#define WLAN_INIT_MODE_DEFAULT     WLAN_INIT_MODE_USR
+#endif /* INIT_MODE_DRV_ENABLED */
+
+#define AR6K_PATCH_DOWNLOAD_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_PATCH_DOWNLOAD_ADDRESS; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_PATCH_DOWNLOAD_ADDRESS; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+#define AR6K_DATA_DOWNLOAD_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_DATA_DOWNLOAD_ADDRESS; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_DATA_DOWNLOAD_ADDRESS; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+#define AR6K_APP_START_OVERRIDE_ADDRESS(_param, _ver) do { \
+    if ((_ver) == AR6003_REV1_VERSION) { \
+        (_param) = AR6003_REV1_APP_START_OVERRIDE; \
+    } else if ((_ver) == AR6003_REV2_VERSION) { \
+        (_param) = AR6003_REV2_APP_START_OVERRIDE; \
+    } else { \
+       AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+       A_ASSERT(0); \
+    } \
+} while (0)
+
+/* AR6003 1.0 definitions */
+#define AR6003_REV1_VERSION                 0x300002ba
+#define AR6003_REV1_DATA_DOWNLOAD_ADDRESS   AR6003_REV1_OTP_DATA_ADDRESS
+#define AR6003_REV1_PATCH_DOWNLOAD_ADDRESS  0x57ea6c
+#define AR6003_REV1_OTP_FILE                "ath6k/AR6003/hw1.0/otp.bin.z77"
+#define AR6003_REV1_FIRMWARE_FILE           "ath6k/AR6003/hw1.0/athwlan.bin.z77"
+#define AR6003_REV1_TCMD_FIRMWARE_FILE      "ath6k/AR6003/hw1.0/athtcmd_ram.bin"
+#define AR6003_REV1_ART_FIRMWARE_FILE       "ath6k/AR6003/hw1.0/device.bin"
+#define AR6003_REV1_PATCH_FILE              "ath6k/AR6003/hw1.0/data.patch.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.WB31.bin"
+#else
+#define AR6003_REV1_BOARD_DATA_FILE         "ath6k/AR6003/hw1.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* AR6003 2.0 definitions */
+#define AR6003_REV2_VERSION                 0x30000384 
+#define AR6003_REV2_DATA_DOWNLOAD_ADDRESS   AR6003_REV2_OTP_DATA_ADDRESS
+#define AR6003_REV2_PATCH_DOWNLOAD_ADDRESS  0x57e918
+#define AR6003_REV2_OTP_FILE                "ath6k/AR6003/hw2.0/otp.bin.z77"
+#define AR6003_REV2_FIRMWARE_FILE           "ath6k/AR6003/hw2.0/athwlan.bin.z77"
+#define AR6003_REV2_TCMD_FIRMWARE_FILE      "ath6k/AR6003/hw2.0/athtcmd_ram.bin"
+#define AR6003_REV2_ART_FIRMWARE_FILE       "ath6k/AR6003/hw2.0/device.bin"
+#define AR6003_REV2_PATCH_FILE              "ath6k/AR6003/hw2.0/data.patch.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.WB31.bin"
+#else
+#define AR6003_REV2_BOARD_DATA_FILE         "ath6k/AR6003/hw2.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* HTC RAW streams */
+typedef enum _HTC_RAW_STREAM_ID {
+    HTC_RAW_STREAM_NOT_MAPPED = -1,
+    HTC_RAW_STREAM_0 = 0,
+    HTC_RAW_STREAM_1 = 1,
+    HTC_RAW_STREAM_2 = 2,
+    HTC_RAW_STREAM_3 = 3,
+    HTC_RAW_STREAM_NUM_MAX
+} HTC_RAW_STREAM_ID;
+
+#define RAW_HTC_READ_BUFFERS_NUM    4
+#define RAW_HTC_WRITE_BUFFERS_NUM   4
+
+#define HTC_RAW_BUFFER_SIZE  1664
+
+typedef struct {
+    int currPtr;
+    int length;
+    unsigned char data[HTC_RAW_BUFFER_SIZE];
+    HTC_PACKET    HTCPacket;
+} raw_htc_buffer;
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*
+ *  add TCMD_MODE besides wmi and bypasswmi
+ *  in TCMD_MODE, only few TCMD releated wmi commands
+ *  counld be hanlder
+ */
+enum {
+    AR6000_WMI_MODE = 0,
+    AR6000_BYPASS_MODE,
+    AR6000_TCMD_MODE,
+    AR6000_WLAN_MODE
+};
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+struct ar_wep_key {
+    A_UINT8                 arKeyIndex;
+    A_UINT8                 arKeyLen;
+    A_UINT8                 arKey[64];
+} ;
+
+#ifdef ATH6K_CONFIG_CFG80211
+struct ar_key {
+    A_UINT8     key[WLAN_MAX_KEY_LEN];
+    A_UINT8     key_len;
+    A_UINT8     seq[IW_ENCODE_SEQ_MAX_SIZE];
+    A_UINT8     seq_len;
+    A_UINT32    cipher;
+};
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+
+struct ar_node_mapping {
+    A_UINT8                 macAddress[6];
+    A_UINT8                 epId;
+    A_UINT8                 txPending;
+};
+
+struct ar_cookie {
+    A_UINT32               arc_bp[2];    /* Must be first field */
+    HTC_PACKET             HtcPkt;       /* HTC packet wrapper */
+    struct ar_cookie *arc_list_next;
+};
+
+struct ar_hb_chlng_resp {
+    A_TIMER                 timer;
+    A_UINT32                frequency;
+    A_UINT32                seqNum;
+    A_BOOL                  outstanding;
+    A_UINT8                 missCnt;
+    A_UINT8                 missThres;
+};
+
+/* Per STA data, used in AP mode */
+/*TODO: All this should move to OS independent dir */
+
+#define STA_PWR_MGMT_MASK 0x1
+#define STA_PWR_MGMT_SHIFT 0x0
+#define STA_PWR_MGMT_AWAKE 0x0
+#define STA_PWR_MGMT_SLEEP 0x1
+
+#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK)
+
+#define STA_PS_POLLED_MASK 0x1
+#define STA_PS_POLLED_SHIFT 0x1
+#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+
+typedef struct {
+    A_UINT16                flags;
+    A_UINT8                 mac[ATH_MAC_LEN];
+    A_UINT8                 aid;
+    A_UINT8                 keymgmt;
+    A_UINT8                 ucipher;
+    A_UINT8                 auth;
+    A_UINT8                 wpa_ie[IEEE80211_MAX_IE];
+    A_NETBUF_QUEUE_T        psq;    /* power save q */
+    A_MUTEX_T               psqLock;
+} sta_t;
+
+typedef struct ar6_raw_htc {
+    HTC_ENDPOINT_ID         arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
+    HTC_RAW_STREAM_ID       arEp2RawMapping[ENDPOINT_MAX];
+    struct semaphore        raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
+    struct semaphore        raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
+    wait_queue_head_t       raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
+    wait_queue_head_t       raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
+    raw_htc_buffer          raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
+    raw_htc_buffer          raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
+    A_BOOL                  write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+    A_BOOL                  read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+} AR_RAW_HTC_T;
+
+typedef struct ar6_softc {
+    struct net_device       *arNetDev;    /* net_device pointer */
+    void                    *arWmi;
+    int                     arTxPending[ENDPOINT_MAX];
+    int                     arTotalTxDataPending;
+    A_UINT8                 arNumDataEndPts;
+    A_BOOL                  arWmiEnabled;
+    A_BOOL                  arWmiReady;
+    A_BOOL                  arConnected;
+    HTC_HANDLE              arHtcTarget;
+    void                    *arHifDevice;
+    spinlock_t              arLock;
+    struct semaphore        arSem;
+    int                     arSsidLen;
+    u_char                  arSsid[32];
+    A_UINT8                 arNextMode;
+    A_UINT8                 arNetworkType;
+    A_UINT8                 arDot11AuthMode;
+    A_UINT8                 arAuthMode;
+    A_UINT8                 arPairwiseCrypto;
+    A_UINT8                 arPairwiseCryptoLen;
+    A_UINT8                 arGroupCrypto;
+    A_UINT8                 arGroupCryptoLen;
+    A_UINT8                 arDefTxKeyIndex;
+    struct ar_wep_key       arWepKeyList[WMI_MAX_KEY_INDEX + 1];
+    A_UINT8                 arBssid[6];
+    A_UINT8                 arReqBssid[6];
+    A_UINT16                arChannelHint;
+    A_UINT16                arBssChannel;
+    A_UINT16                arListenInterval;
+    struct ar6000_version   arVersion;
+    A_UINT32                arTargetType;
+    A_INT8                  arRssi;
+    A_UINT8                 arTxPwr;
+    A_BOOL                  arTxPwrSet;
+    A_INT32                 arBitRate;
+    struct net_device_stats arNetStats;
+    struct iw_statistics    arIwStats;
+    A_INT8                  arNumChannels;
+    A_UINT16                arChannelList[32];
+    A_UINT32                arRegCode;
+    A_BOOL                  statsUpdatePending;
+    TARGET_STATS            arTargetStats;
+    A_INT8                  arMaxRetries;
+    A_UINT8                 arPhyCapability;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    A_UINT8                 tcmdRxReport;
+    A_UINT32                tcmdRxTotalPkt;
+    A_INT32                 tcmdRxRssi;
+    A_UINT32                tcmdPm;
+    A_UINT32                arTargetMode;
+    A_UINT32                tcmdRxcrcErrPkt;
+    A_UINT32                tcmdRxsecErrPkt;
+    A_UINT16                tcmdRateCnt[TCMD_MAX_RATES];
+    A_UINT16                tcmdRateCntShortGuard[TCMD_MAX_RATES];
+#endif
+    AR6000_WLAN_STATE       arWlanState;
+    struct ar_node_mapping  arNodeMap[MAX_NODE_NUM];
+    A_UINT8                 arIbssPsEnable;
+    A_UINT8                 arNodeNum;
+    A_UINT8                 arNexEpId;
+    struct ar_cookie        *arCookieList;
+    A_UINT32                arCookieCount;
+    A_UINT32                arRateMask;
+    A_UINT8                 arSkipScan;
+    A_UINT16                arBeaconInterval;
+    A_BOOL                  arConnectPending;
+    A_BOOL                  arWmmEnabled;
+    struct ar_hb_chlng_resp arHBChallengeResp;
+    A_UINT8                 arKeepaliveConfigured;
+    A_UINT32                arMgmtFilter;
+    HTC_ENDPOINT_ID         arAc2EpMapping[WMM_NUM_AC];
+    A_BOOL                  arAcStreamActive[WMM_NUM_AC];
+    A_UINT8                 arAcStreamPriMap[WMM_NUM_AC];
+    A_UINT8                 arHiAcStreamActivePri;
+    A_UINT8                 arEp2AcMapping[ENDPOINT_MAX];
+    HTC_ENDPOINT_ID         arControlEp;
+#ifdef HTC_RAW_INTERFACE
+    AR_RAW_HTC_T            *arRawHtc;
+#endif
+    A_BOOL                  arNetQueueStopped;
+    A_BOOL                  arRawIfInit;
+    int                     arDeviceIndex;
+    COMMON_CREDIT_STATE_INFO arCreditStateInfo;
+    A_BOOL                  arWMIControlEpFull;
+    A_BOOL                  dbgLogFetchInProgress;
+    A_UCHAR                 log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
+    A_UINT32                log_cnt;
+    A_UINT32                dbglog_init_done;
+    A_UINT32                arConnectCtrlFlags;
+#ifdef USER_KEYS
+    A_INT32                 user_savedkeys_stat;
+    A_UINT32                user_key_ctrl;
+    struct USER_SAVEDKEYS   user_saved_keys;
+#endif
+    USER_RSSI_THOLD rssi_map[12];
+    A_UINT8                arUserBssFilter;
+    A_UINT16                ap_profile_flag;    /* AP mode */
+    WMI_AP_ACL              g_acl;              /* AP mode */
+    sta_t                   sta_list[AP_MAX_NUM_STA]; /* AP mode */
+    A_UINT8                 sta_list_index;     /* AP mode */
+    struct ieee80211req_key ap_mode_bkey;           /* AP mode */
+    A_NETBUF_QUEUE_T        mcastpsq;    /* power save q for Mcast frames */
+    A_MUTEX_T               mcastpsqLock;
+    A_BOOL                  DTIMExpired; /* flag to indicate DTIM expired */
+    A_UINT8                 intra_bss;   /* enable/disable intra bss data forward */
+    void                    *aggr_cntxt;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+    void                    *hcidev_info;
+#endif
+    WMI_AP_MODE_STAT        arAPStats;
+    A_UINT8                 ap_hidden_ssid;
+    A_UINT8                 ap_country_code[3];
+    A_UINT8                 ap_wmode;
+    A_UINT8                 ap_dtim_period;
+    A_UINT16                ap_beacon_interval;
+    A_UINT16                arRTS;
+    A_UINT16                arACS; /* AP mode - Auto Channel Selection */
+    HTC_PACKET_QUEUE        amsdu_rx_buffer_queue;
+    A_BOOL                  bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */
+    A_TIMER                 disconnect_timer;
+    A_UINT8		    rxMetaVersion;
+#ifdef WAPI_ENABLE
+    A_UINT8                 arWapiEnable;
+#endif
+	WMI_BTCOEX_CONFIG_EVENT arBtcoexConfig;
+	WMI_BTCOEX_STATS_EVENT  arBtcoexStats;
+    A_INT32                 (*exitCallback)(void *config);  /* generic callback at AR6K exit */
+    HIF_DEVICE_OS_DEVICE_INFO   osDevInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+    struct wireless_dev *wdev;
+    struct cfg80211_scan_request    *scan_request;
+    struct ar_key   keys[WMI_MAX_KEY_INDEX + 1];
+#endif /* ATH6K_CONFIG_CFG80211 */
+#if CONFIG_PM
+    A_UINT16                arOsPowerCtrl;
+    A_UINT16                arWowState;
+#endif
+    A_BOOL                  scan_complete;
+    WMI_SCAN_PARAMS_CMD     scParams;
+} AR_SOFTC_T;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+/* Looks like we need this for 2.4 kernels */
+static inline void *ar6k_priv(struct net_device *dev)
+{
+    return(dev->priv);
+}
+#else
+#ifdef ATH6K_CONFIG_CFG80211
+static inline void *ar6k_priv(struct net_device *dev)
+{
+    return (wdev_priv(dev->ieee80211_ptr));
+}
+#else
+#define ar6k_priv   netdev_priv
+#endif /* ATH6K_CONFIG_CFG80211 */
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) */
+
+#define arAc2EndpointID(ar,ac)          (ar)->arAc2EpMapping[(ac)]
+#define arSetAc2EndpointIDMap(ar,ac,ep)  \
+{  (ar)->arAc2EpMapping[(ac)] = (ep); \
+   (ar)->arEp2AcMapping[(ep)] = (ac); }
+#define arEndpoint2Ac(ar,ep)           (ar)->arEp2AcMapping[(ep)]
+
+#define arRawIfEnabled(ar) (ar)->arRawIfInit
+#define arRawStream2EndpointID(ar,raw)          (ar)->arRawHtc->arRaw2EpMapping[(raw)]
+#define arSetRawStream2EndpointIDMap(ar,raw,ep)  \
+{  (ar)->arRawHtc->arRaw2EpMapping[(raw)] = (ep); \
+   (ar)->arRawHtc->arEp2RawMapping[(ep)] = (raw); }
+#define arEndpoint2RawStreamID(ar,ep)           (ar)->arRawHtc->arEp2RawMapping[(ep)]
+
+struct ar_giwscan_param {
+    char    *current_ev;
+    char    *end_buf;
+    A_UINT32 bytes_needed;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+    struct iw_request_info *info;
+#endif
+};
+
+#define AR6000_STAT_INC(ar, stat)       (ar->arNetStats.stat++)
+
+#define AR6000_SPIN_LOCK(lock, param)   do {                            \
+    if (irqs_disabled()) {                                              \
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled:AR6000_LOCK\n"));                 \
+    }                                                                   \
+    spin_lock_bh(lock);                                                 \
+} while (0)
+
+#define AR6000_SPIN_UNLOCK(lock, param) do {                            \
+    if (irqs_disabled()) {                                              \
+        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled: AR6000_UNLOCK\n"));              \
+    }                                                                   \
+    spin_unlock_bh(lock);                                               \
+} while (0)
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
+void ar6000_gpio_init(void);
+void ar6000_init_profile_info(AR_SOFTC_T *ar);
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
+int ar6000_init(struct net_device *dev);
+int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
+int ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+#ifdef HTC_RAW_INTERFACE
+
+#ifndef __user
+#define __user
+#endif
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar);
+int ar6000_htc_raw_close(AR_SOFTC_T *ar);
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
+                            HTC_RAW_STREAM_ID StreamID,
+                            char __user *buffer, size_t count);
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
+                             HTC_RAW_STREAM_ID StreamID,
+                             char __user *buffer, size_t count);
+
+#endif /* HTC_RAW_INTERFACE */
+
+/* AP mode */
+/*TODO: These routines should be moved to a file that is common across OS */
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr);
+
+sta_t *
+ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid);
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason);
+
+/* HCI support */
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void     ar6000_cleanup_hci(AR_SOFTC_T *ar);
+void     ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig);
+
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif
+
+ATH_DEBUG_DECLARE_EXTERN(htc);
+ATH_DEBUG_DECLARE_EXTERN(wmi);
+ATH_DEBUG_DECLARE_EXTERN(bmi);
+ATH_DEBUG_DECLARE_EXTERN(hif);
+ATH_DEBUG_DECLARE_EXTERN(wlan);
+ATH_DEBUG_DECLARE_EXTERN(misc);
+
+extern A_UINT8 bcast_mac[];
+extern A_UINT8 null_mac[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AR6000_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h
new file mode 100644
index 000000000000..fc5c363f9936
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h
@@ -0,0 +1,175 @@
+#ifndef _AR6XAPI_LINUX_H
+#define _AR6XAPI_LINUX_H
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ar6_softc;
+
+void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap,
+                        A_UINT32 ver);
+A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid);
+void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
+                          A_UINT8 *bssid, A_UINT16 listenInterval,
+                          A_UINT16 beaconInterval, NETWORK_TYPE networkType,
+                          A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                          A_UINT8 assocRespLen,A_UINT8 *assocInfo);
+void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
+                             A_UINT8 *bssid, A_UINT8 assocRespLen,
+                             A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
+                              A_BOOL ismcast);
+void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
+void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
+void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
+void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
+void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
+void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
+                                 WMI_NEIGHBOR_INFO *info);
+void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
+void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
+void ar6000_targetStats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len);
+void ar6000_rssiThreshold_event(struct ar6_softc *ar,
+                                WMI_RSSI_THRESHOLD_VAL newThreshold,
+                                A_INT16 rssi);
+void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
+void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
+                                A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
+void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel);
+void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
+void
+ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
+
+void
+ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
+                      WMI_GET_WOW_LIST_REPLY *wow_reply);
+
+void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
+                             WMI_PMKID *pmkidList, A_UINT8 *bssidList);
+
+void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
+void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
+void ar6000_gpio_ack_rx(void);
+
+A_INT32 rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt);
+A_INT16 rssi_compensation_calc(struct ar6_softc *ar, A_INT16 rssi);
+A_INT16 rssi_compensation_reverse_calc(struct ar6_softc *ar, A_INT16 rssi, A_BOOL Above);
+
+void ar6000_dbglog_init_done(struct ar6_softc *ar);
+
+#ifdef SEND_EVENT_TO_APP
+void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
+#endif
+
+void ar6000_tx_retry_err_event(void *devt);
+
+void ar6000_snrThresholdEvent_rx(void *devt,
+                                 WMI_SNR_THRESHOLD_VAL newThreshold,
+                                 A_UINT8 snr);
+
+void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
+
+
+void ar6000_ratemask_rx(void *devt, A_UINT32 ratemask);
+
+A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
+                                A_UINT16 cfgParam,
+                                void *result);
+void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
+
+void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
+                         A_INT8 *buffer, A_UINT32 length);
+
+int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
+
+void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid);
+
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
+HTC_ENDPOINT_ID  ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac);
+A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep );
+
+void ar6000_btcoex_config_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len);
+
+void ar6000_btcoex_stats_event(struct ar6_softc *ar,  A_UINT8 *ptr, A_UINT32 len) ;
+
+void ar6000_dset_open_req(void *devt,
+                          A_UINT32 id,
+                          A_UINT32 targ_handle,
+                          A_UINT32 targ_reply_fn,
+                          A_UINT32 targ_reply_arg);
+void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
+void ar6000_dset_data_req(void *devt,
+                          A_UINT32 access_cookie,
+                          A_UINT32 offset,
+                          A_UINT32 length,
+                          A_UINT32 targ_buf,
+                          A_UINT32 targ_reply_fn,
+                          A_UINT32 targ_reply_arg);
+
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+void prof_count_rx(unsigned int addr, unsigned int count);
+#endif
+
+A_UINT32 ar6000_getnodeAge (void);
+
+A_UINT32 ar6000_getclkfreq (void);
+
+int ar6000_ap_mode_profile_commit(struct ar6_softc *ar);
+
+struct ieee80211req_wpaie;
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie);
+
+A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd);
+
+A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd);
+
+void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid);
+
+void ar6000_dtimexpiry_event(struct ar6_softc *ar);
+
+void ar6000_aggr_rcv_addba_req_evt(struct ar6_softc *ar, WMI_ADDBA_REQ_EVENT *cmd);
+void ar6000_aggr_rcv_addba_resp_evt(struct ar6_softc *ar, WMI_ADDBA_RESP_EVENT *cmd);
+void ar6000_aggr_rcv_delba_req_evt(struct ar6_softc *ar, WMI_DELBA_EVENT *cmd);
+void ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd);
+
+#ifdef WAPI_ENABLE
+int ap_set_wapi_key(struct ar6_softc *ar, void *ik);
+void ap_wapi_rekey_event(struct ar6_softc *ar, A_UINT8 type, A_UINT8 *mac);
+#endif
+
+A_STATUS ar6000_connect_to_ap(struct ar6_softc *ar);
+A_STATUS ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h
new file mode 100644
index 000000000000..e661741f3b9e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h
@@ -0,0 +1,1202 @@
+/*
+ * Copyright (c) 2004-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _ATHDRV_LINUX_H
+#define _ATHDRV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * There are two types of ioctl's here: Standard ioctls and
+ * eXtended ioctls.  All extended ioctls (XIOCTL) are multiplexed
+ * off of the single ioctl command, AR6000_IOCTL_EXTENDED.  The
+ * arguments for every XIOCTL starts with a 32-bit command word
+ * that is used to select which extended ioctl is in use.  After
+ * the command word are command-specific arguments.
+ */
+
+/* Linux standard Wireless Extensions, private ioctl interfaces */
+#define IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)
+#define IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+1)
+#define IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+2)
+#define IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+3)
+#define IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+4)
+#define IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+5)
+//#define IEEE80211_IOCTL_GETPARAM             (SIOCIWFIRSTPRIV+6)
+//#define IEEE80211_IOCTL_SETWMMPARAMS         (SIOCIWFIRSTPRIV+7)
+//#define IEEE80211_IOCTL_GETWMMPARAMS         (SIOCIWFIRSTPRIV+8)
+//#define IEEE80211_IOCTL_GETOPTIE             (SIOCIWFIRSTPRIV+9)
+//#define IEEE80211_IOCTL_SETAUTHALG           (SIOCIWFIRSTPRIV+10)
+#define IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+10)
+
+
+
+/*                      ====WMI Ioctls====                                    */
+/*
+ *
+ * Many ioctls simply provide WMI services to application code:
+ * an application makes such an ioctl call with a set of arguments
+ * that are packaged into the corresponding WMI message, and sent
+ * to the Target.
+ */
+
+#define AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+11)
+/*
+ * arguments:
+ *   ar6000_version *revision
+ */
+
+#define AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+12)
+/*
+ * arguments:
+ *   WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
+ * uses: WMI_SET_POWER_MODE_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+13)
+/*
+ * arguments:
+ *   WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
+ * uses: WMI_SET_SCAN_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+14)
+/*
+ * arguments:
+ *   UINT32 listenInterval
+ * uses: WMI_SET_LISTEN_INT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+15)
+/*
+ * arguments:
+ *   WMI_BSS_FILTER filter (see include/wmi.h)
+ * uses: WMI_SET_BSS_FILTER_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)
+/*
+ * arguments:
+ *   WMI_CHANNEL_PARAMS_CMD chParams
+ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)
+/*
+ * arguments:
+ *   WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
+ * uses: WMI_SETPROBED_SSID_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)
+/*
+ * arguments:
+ *   WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
+ * uses: WMI_SET_POWER_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)
+/*
+ * arguments:
+ *   WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
+ * uses: WMI_ADD_BAD_AP_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)
+/*
+ * arguments:
+ *   ar6000_queuereq queueRequest (see below)
+ */
+
+#define AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)
+/*
+ * arguments:
+ *   WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
+ * uses: WMI_CREATE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)
+/*
+ * arguments:
+ *   WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
+ * uses: WMI_DELETE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD   (SIOCIWFIRSTPRIV+23)
+/*
+ * arguments:
+ *   WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
+/*
+ * arguments:
+ *   WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
+ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)
+/*
+ * arguments:
+ *   TARGET_STATS *targetStats (see below)
+ * uses: WMI_GET_STATISTICS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)
+/*
+ * arguments:
+ *   WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
+ * uses: WMI_SET_ASSOC_INFO_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)
+/*
+ * arguments:
+ *   WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
+ * uses: WMI_SET_ACCESS_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)
+/*
+ * arguments:
+ *   UINT32 beaconMissTime
+ * uses: WMI_SET_BMISS_TIME_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)
+/*
+ * arguments:
+ *   WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
+ * uses: WMI_SET_DISC_TIMEOUT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)
+/*
+ * arguments:
+ *   WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
+ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
+ */
+
+/*
+ * There is a very small space available for driver-private
+ * wireless ioctls.  In order to circumvent this limitation,
+ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
+ * single AR6000_IOCTL_EXTENDED ioctl.
+ */
+#define AR6000_IOCTL_EXTENDED                (SIOCIWFIRSTPRIV+31)
+
+
+/*                         ====BMI Extended Ioctls====                        */
+
+#define AR6000_XIOCTL_BMI_DONE                                  1
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
+ * uses: BMI_DONE
+ */
+
+#define AR6000_XIOCTL_BMI_READ_MEMORY                           2
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
+ *       UINT32 address
+ *       UINT32 length
+ *     }
+ *     char results[length]
+ *   }
+ * uses: BMI_READ_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_MEMORY                          3
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
+ *   UINT32 address
+ *   UINT32 length
+ *   char data[length]
+ * uses: BMI_WRITE_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_EXECUTE                               4
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
+ *   UINT32 TargetAddress
+ *   UINT32 parameter
+ * uses: BMI_EXECUTE
+ */
+
+#define AR6000_XIOCTL_BMI_SET_APP_START                         5
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
+ *   UINT32 TargetAddress
+ * uses: BMI_SET_APP_START
+ */
+
+#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER                     6
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
+ *       UINT32 TargetAddress, 32-bit aligned
+ *     }
+ *     UINT32 result
+ *   }
+ * uses: BMI_READ_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER                    7
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
+ *       UINT32 TargetAddress, 32-bit aligned
+ *       UINT32 newValue
+ *     }
+ * uses: BMI_WRITE_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_TEST                                  8
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
+ *   UINT32 address
+ *   UINT32 length
+ *   UINT32 count
+ */
+
+
+
+/* Historical Host-side DataSet support */
+#define AR6000_XIOCTL_UNUSED9                                   9
+#define AR6000_XIOCTL_UNUSED10                                  10
+#define AR6000_XIOCTL_UNUSED11                                  11
+
+/*                      ====Misc Extended Ioctls====                          */
+
+#define AR6000_XIOCTL_FORCE_TARGET_RESET                        12
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
+ */
+
+
+#ifdef HTC_RAW_INTERFACE
+/* HTC Raw Interface Ioctls */
+#define AR6000_XIOCTL_HTC_RAW_OPEN                              13
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_CLOSE                             14
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_READ                              15
+/*
+ * arguments:
+ *   union {
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
+ *       UINT32 mailboxID
+ *       UINT32 length
+ *     }
+ *     results[length]
+ *   }
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_WRITE                             16
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
+ *   UINT32 mailboxID
+ *   UINT32 length
+ *   char buffer[length]
+ */
+#endif /* HTC_RAW_INTERFACE */
+
+#define AR6000_XIOCTL_CHECK_TARGET_READY                        17
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
+ */
+
+
+
+/*                ====GPIO (General Purpose I/O) Extended Ioctls====          */
+
+#define AR6000_XIOCTL_GPIO_OUTPUT_SET                           18
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
+ *   ar6000_gpio_output_set_cmd_s (see below)
+ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INPUT_GET                            19
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
+ * uses: WMIX_GPIO_INPUT_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_SET                         20
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
+ *   ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_GET                         21
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
+ *   ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_ACK                             22
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
+ *   ar6000_cpio_intr_ack_cmd_s (see below)
+ * uses: WMIX_GPIO_INTR_ACK_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_WAIT                            23
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
+ */
+
+
+
+/*                    ====more wireless commands====                          */
+
+#define AR6000_XIOCTL_SET_ADHOC_BSSID                           24
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
+ *   WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
+ */
+
+#define AR6000_XIOCTL_SET_OPT_MODE                              25
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
+ *   WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
+ * uses: WMI_SET_OPT_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_OPT_SEND_FRAME                            26
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
+ *   WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
+ * uses: WMI_OPT_TX_FRAME_CMDID
+ */
+
+#define AR6000_XIOCTL_SET_BEACON_INTVAL                         27
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL)
+ *   WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
+ * uses: WMI_SET_BEACON_INT_CMDID
+ */
+
+
+#define IEEE80211_IOCTL_SETAUTHALG                              28
+
+
+#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE                        29
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
+ *   WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
+ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+
+
+#define AR6000_XIOCTL_SET_MAX_SP                                30
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
+ *   WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
+ * uses: WMI_SET_MAX_SP_LEN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_TBL                          31
+
+#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL                         32
+
+#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS                 33
+
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
+ *   WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
+ *   WMI_SET_POWERSAVE_TIMERS_CMDID
+ */
+
+#define AR6000_XIOCTRL_WMI_GET_POWER_MODE                        34
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
+ */
+
+#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE                       35
+typedef enum {
+    WLAN_DISABLED,
+    WLAN_ENABLED
+} AR6000_WLAN_STATE;
+/*
+ * arguments:
+ * enable/disable
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_DATA                         36
+
+#define AR6000_XIOCTL_WMI_SETRETRYLIMITS                37
+/*
+ * arguments:
+ *   WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
+ * uses: WMI_SET_RETRY_LIMITS_CMDID
+ */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*       ====extended commands for radio test ====                          */
+
+#define AR6000_XIOCTL_TCMD_CONT_TX                      38
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
+ *   WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_TX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_CONT_RX                      39
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
+ *   WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_RX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_PM                           40
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
+ *   WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
+ * uses: WMI_TCMD_PM_CMDID
+ */
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+#define AR6000_XIOCTL_WMI_STARTSCAN                     41
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
+ *   UINT8  scanType
+ *   UINT8  scanConnected
+ *   A_BOOL forceFgScan
+ * uses: WMI_START_SCAN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SETFIXRATES                   42
+
+#define AR6000_XIOCTL_WMI_GETFIXRATES                   43
+
+
+#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44
+/*
+ * arguments:
+ *   WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_CLR_RSSISNR                   45
+/*
+ * arguments:
+ *   WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_CLR_RSSISNR_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46
+/*
+ * arguments:
+ *   WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_RTS                        47
+/*
+ * arguments:
+ *   WMI_SET_RTS_MODE_CMD (see include/wmi.h)
+ * uses: WMI_SET_RTS_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48
+
+#define AR6000_XIOCTL_WMI_SET_AUTHMODE                  49
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
+ *   UINT8  mode
+ * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_REASSOCMODE               50
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
+ *   UINT8  mode
+ * uses: WMI_SET_WMM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_WMM                       51
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
+ * UINT32 frequency
+ * UINT8  threshold
+ */
+#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
+ * UINT32 cookie
+ */
+#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53
+
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
+ *   UINT32 regDomain
+ */
+#define AR6000_XIOCTL_WMI_GET_RD                        54
+
+#define AR6000_XIOCTL_DIAG_READ                         55
+
+#define AR6000_XIOCTL_DIAG_WRITE                        56
+
+/*
+ * arguments cmd (AR6000_XIOCTL_SET_TXOP)
+ * WMI_TXOP_CFG  txopEnable
+ */
+#define AR6000_XIOCTL_WMI_SET_TXOP                      57
+
+#ifdef USER_KEYS
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
+ * UINT32 keyOpCtrl
+ * uses AR6000_USER_SETKEYS_INFO
+ */
+#define AR6000_XIOCTL_USER_SETKEYS                      58
+#endif /* USER_KEYS */
+
+#define AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59
+/*
+ * arguments:
+ *   UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
+ *   UINT8 keepaliveInterval
+ * uses: WMI_SET_KEEPALIVE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60
+/*
+ * arguments:
+ *   UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
+ *   UINT8 keepaliveInterval
+ *   A_BOOL configured
+ * uses: WMI_GET_KEEPALIVE_CMDID
+ */
+
+/*               ====ROM Patching Extended Ioctls====                       */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61
+/*
+ * arguments:
+ *     union {
+ *       struct {
+ *         UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
+ *         UINT32 ROM Address
+ *         UINT32 RAM Address
+ *         UINT32 number of bytes
+ *         UINT32 activate? (0 or 1)
+ *       }
+ *       A_UINT32 resulting rompatch ID
+ *     }
+ * uses: BMI_ROMPATCH_INSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
+ *       UINT32 rompatch ID
+ *     }
+ * uses: BMI_ROMPATCH_UNINSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
+ *       UINT32 rompatch count
+ *       UINT32 rompatch IDs[rompatch count]
+ *     }
+ * uses: BMI_ROMPATCH_ACTIVATE
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64
+/*
+ * arguments:
+ *     struct {
+ *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
+ *       UINT32 rompatch count
+ *       UINT32 rompatch IDs[rompatch count]
+ *     }
+ * uses: BMI_ROMPATCH_DEACTIVATE
+ */
+
+#define AR6000_XIOCTL_WMI_SET_APPIE             65
+/*
+ * arguments:
+ *      struct {
+ *          UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
+ *          UINT32  app_frmtype;
+ *          UINT32  app_buflen;
+ *          UINT8   app_buf[];
+ *      }
+ */
+#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER    66
+/*
+ * arguments:
+ *      A_UINT32 filter_type;
+ */
+
+#define AR6000_XIOCTL_DBGLOG_CFG_MODULE             67
+
+#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS         68
+
+#define AR6000_XIOCTL_WMI_SET_WSC_STATUS            70
+/*
+ * arguments:
+ *      A_UINT32 wsc_status;
+ *            (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
+ */
+
+/*
+ * arguments:
+ *      struct {
+ *          A_UINT8 streamType;
+ *          A_UINT8 status;
+ *      }
+ * uses: WMI_SET_BT_STATUS_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_STATUS             71
+
+/*
+ * arguments:
+ *      struct {
+ *           A_UINT8 paramType;
+ *           union {
+ *               A_UINT8 noSCOPkts;
+ *               BT_PARAMS_A2DP a2dpParams;
+ *               BT_COEX_REGS regs;
+ *           };
+ *      }
+ * uses: WMI_SET_BT_PARAM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_PARAMS             72
+
+#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE       73
+#define AR6000_XIOCTL_WMI_SET_WOW_MODE              74
+#define AR6000_XIOCTL_WMI_GET_WOW_LIST              75
+#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN           76
+#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN           77
+
+
+
+#define AR6000_XIOCTL_TARGET_INFO                   78
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
+ *   A_UINT32 TargetVersion (returned)
+ *   A_UINT32 TargetType    (returned)
+ * (See also bmi_msg.h target_ver and target_type)
+ */
+
+#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE         79
+/*
+ * arguments:
+ *      none
+ */
+
+#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE       80
+/*
+ * This ioctl is used to emulate traffic activity
+ * timeouts.  Activity/inactivity will trigger the driver
+ * to re-balance credits.
+ *
+ * arguments:
+ *      ar6000_traffic_activity_change
+ */
+
+#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS    81
+/*
+ * This ioctl is used to set the connect control flags
+ *
+ * arguments:
+ *      A_UINT32 connectCtrlFlags
+ */
+
+#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS              82
+/*
+ * This IOCTL sets any Authentication,Key Management and Protection
+ * related parameters. This is used along with the information set in
+ * Connect Command.
+ * Currently this enables Multiple PMKIDs to an AP.
+ *
+ * arguments:
+ *      struct {
+ *          A_UINT32    akmpInfo;
+ *      }
+ * uses: WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_GET_PMKID_LIST            83
+
+#define AR6000_XIOCTL_WMI_SET_PMKID_LIST            84
+/*
+ * This IOCTL is used to set a list of PMKIDs. This list of
+ * PMKIDs is used in the [Re]AssocReq Frame. This list is used
+ * only if the MultiPMKID option is enabled via the
+ * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS  IOCTL.
+ *
+ * arguments:
+ *      struct {
+ *          A_UINT32    numPMKID;
+ *          WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
+ *      }
+ * uses: WMI_SET_PMKIDLIST_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_SET_PARAMS                85
+#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER     86
+#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER     87
+
+
+/* Historical DSETPATCH support for INI patches */
+#define AR6000_XIOCTL_UNUSED90                      90
+
+
+/* Support LZ-compressed firmware download */
+#define AR6000_XIOCTL_BMI_LZ_STREAM_START           91
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START)
+ *   UINT32 address
+ * uses: BMI_LZ_STREAM_START
+ */
+
+#define AR6000_XIOCTL_BMI_LZ_DATA                   92
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA)
+ *   UINT32 length
+ *   char data[length]
+ * uses: BMI_LZ_DATA
+ */
+
+#define AR6000_XIOCTL_PROF_CFG                      93
+/*
+ * arguments:
+ *   A_UINT32 period
+ *   A_UINT32 nbins
+ */
+
+#define AR6000_XIOCTL_PROF_ADDR_SET                 94
+/*
+ * arguments:
+ *   A_UINT32 Target address
+ */
+
+#define AR6000_XIOCTL_PROF_START                    95
+
+#define AR6000_XIOCTL_PROF_STOP                     96
+
+#define AR6000_XIOCTL_PROF_COUNT_GET                97
+
+#define AR6000_XIOCTL_WMI_ABORT_SCAN                98
+
+/*
+ * AP mode
+ */
+#define AR6000_XIOCTL_AP_GET_STA_LIST               99
+
+#define AR6000_XIOCTL_AP_HIDDEN_SSID                100
+
+#define AR6000_XIOCTL_AP_SET_NUM_STA                101
+
+#define AR6000_XIOCTL_AP_SET_ACL_MAC                102
+
+#define AR6000_XIOCTL_AP_GET_ACL_LIST               103
+
+#define AR6000_XIOCTL_AP_COMMIT_CONFIG              104
+
+#define IEEE80211_IOCTL_GETWPAIE                    105
+
+#define AR6000_XIOCTL_AP_CONN_INACT_TIME            106
+
+#define AR6000_XIOCTL_AP_PROT_SCAN_TIME             107
+
+#define AR6000_XIOCTL_AP_SET_COUNTRY                108
+
+#define AR6000_XIOCTL_AP_SET_DTIM                   109
+
+
+
+
+#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT       110
+
+#define AR6000_XIOCTL_SET_IP                        111
+
+#define AR6000_XIOCTL_AP_SET_ACL_POLICY             112
+
+#define AR6000_XIOCTL_AP_INTRA_BSS_COMM             113
+
+#define AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO        114
+
+#define AR6000_XIOCTL_MODULE_DEBUG_SET_MASK         115
+
+#define AR6000_XIOCTL_MODULE_DEBUG_GET_MASK         116
+
+#define AR6000_XIOCTL_DUMP_RCV_AGGR_STATS           117
+
+#define AR6000_XIOCTL_SET_HT_CAP                    118
+
+#define AR6000_XIOCTL_SET_HT_OP                     119
+
+#define AR6000_XIOCTL_AP_GET_STAT                   120
+
+#define AR6000_XIOCTL_SET_TX_SELECT_RATES           121
+
+#define AR6000_XIOCTL_SETUP_AGGR                    122
+
+#define AR6000_XIOCTL_ALLOW_AGGR                    123
+
+#define AR6000_XIOCTL_AP_GET_HIDDEN_SSID            124
+
+#define AR6000_XIOCTL_AP_GET_COUNTRY                125
+
+#define AR6000_XIOCTL_AP_GET_WMODE                  126
+
+#define AR6000_XIOCTL_AP_GET_DTIM                   127
+
+#define AR6000_XIOCTL_AP_GET_BINTVL                 128
+
+#define AR6000_XIOCTL_AP_GET_RTS                    129
+
+#define AR6000_XIOCTL_DELE_AGGR                     130
+
+#define AR6000_XIOCTL_FETCH_TARGET_REGS             131
+
+#define AR6000_XIOCTL_HCI_CMD                       132
+
+#define AR6000_XIOCTL_ACL_DATA                      133
+
+#define AR6000_XIOCTL_WLAN_CONN_PRECEDENCE          134
+
+#define AR6000_XIOCTL_AP_SET_11BG_RATESET           135
+
+#define AR6000_XIOCTL_WMI_SET_AP_PS                 136
+
+#define AR6000_XIOCTL_WMI_MCAST_FILTER              137
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT					138
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV			139
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 	140
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG				141
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG				142
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG			143
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG						144
+
+#define AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS   			145
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG					146
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_STATS						147
+/*
+ * arguments:
+ *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_QOS_SUPP)
+ *   UINT8  mode
+ * uses: WMI_SET_QOS_SUPP_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_QOS_SUPP                  148 
+
+
+/*
+ * arguments:
+ *   WMI_AP_PS_CMD apPsCmd
+ * uses: WMI_AP_PS_CMDID
+ */
+
+/* used by AR6000_IOCTL_WMI_GETREV */
+struct ar6000_version {
+    A_UINT32        host_ver;
+    A_UINT32        target_ver;
+    A_UINT32        wlan_ver;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
+struct ar6000_queuereq {
+    A_UINT8         trafficClass;
+    A_UINT16        activeTsids;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
+typedef struct targetStats_t {
+    A_UINT64    tx_packets;
+    A_UINT64    tx_bytes;
+    A_UINT64    tx_unicast_pkts;
+    A_UINT64    tx_unicast_bytes;
+    A_UINT64    tx_multicast_pkts;
+    A_UINT64    tx_multicast_bytes;
+    A_UINT64    tx_broadcast_pkts;
+    A_UINT64    tx_broadcast_bytes;
+    A_UINT64    tx_rts_success_cnt;
+    A_UINT64    tx_packet_per_ac[4];
+
+    A_UINT64    tx_errors;
+    A_UINT64    tx_failed_cnt;
+    A_UINT64    tx_retry_cnt;
+    A_UINT64    tx_mult_retry_cnt;
+    A_UINT64    tx_rts_fail_cnt;
+
+    A_UINT64    rx_packets;
+    A_UINT64    rx_bytes;
+    A_UINT64    rx_unicast_pkts;
+    A_UINT64    rx_unicast_bytes;
+    A_UINT64    rx_multicast_pkts;
+    A_UINT64    rx_multicast_bytes;
+    A_UINT64    rx_broadcast_pkts;
+    A_UINT64    rx_broadcast_bytes;
+    A_UINT64    rx_fragment_pkt;
+
+    A_UINT64    rx_errors;
+    A_UINT64    rx_crcerr;
+    A_UINT64    rx_key_cache_miss;
+    A_UINT64    rx_decrypt_err;
+    A_UINT64    rx_duplicate_frames;
+
+    A_UINT64    tkip_local_mic_failure;
+    A_UINT64    tkip_counter_measures_invoked;
+    A_UINT64    tkip_replays;
+    A_UINT64    tkip_format_errors;
+    A_UINT64    ccmp_format_errors;
+    A_UINT64    ccmp_replays;
+
+    A_UINT64    power_save_failure_cnt;
+
+    A_UINT64    cs_bmiss_cnt;
+    A_UINT64    cs_lowRssi_cnt;
+    A_UINT64    cs_connect_cnt;
+    A_UINT64    cs_disconnect_cnt;
+
+    A_INT32     tx_unicast_rate;
+    A_INT32     rx_unicast_rate;
+
+    A_UINT32    lq_val;
+
+    A_UINT32    wow_num_pkts_dropped;
+    A_UINT16    wow_num_events_discarded;
+
+    A_INT16     noise_floor_calibation;
+    A_INT16     cs_rssi;
+    A_INT16     cs_aveBeacon_rssi;
+    A_UINT8     cs_aveBeacon_snr;
+    A_UINT8     cs_lastRoam_msec;
+    A_UINT8     cs_snr;
+
+    A_UINT8     wow_num_host_pkt_wakeups;
+    A_UINT8     wow_num_host_event_wakeups;
+
+    A_UINT32   arp_received;
+    A_UINT32   arp_matched;
+    A_UINT32   arp_replied;
+}TARGET_STATS;
+
+typedef struct targetStats_cmd_t {
+    TARGET_STATS targetStats;
+    int clearStats;
+} TARGET_STATS_CMD;
+
+/* used by AR6000_XIOCTL_USER_SETKEYS */
+
+/*
+ * Setting this bit to 1 doesnot initialize the RSC on the firmware
+ */
+#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL    1
+#define AR6000_USER_SETKEYS_RSC_UNCHANGED     0x00000002
+
+typedef struct {
+    A_UINT32  keyOpCtrl;  /* Bit Map of Key Mgmt Ctrl Flags */
+} AR6000_USER_SETKEYS_INFO;
+
+
+/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
+struct ar6000_gpio_output_set_cmd_s {
+    A_UINT32 set_mask;
+    A_UINT32 clear_mask;
+    A_UINT32 enable_mask;
+    A_UINT32 disable_mask;
+};
+
+/*
+ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
+ */
+struct ar6000_gpio_register_cmd_s {
+    A_UINT32 gpioreg_id;
+    A_UINT32 value;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
+struct ar6000_gpio_intr_ack_cmd_s {
+    A_UINT32 ack_mask;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
+struct ar6000_gpio_intr_wait_cmd_s {
+    A_UINT32 intr_mask;
+    A_UINT32 input_values;
+};
+
+/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
+typedef struct ar6000_dbglog_module_config_s {
+    A_UINT32 valid;
+    A_UINT16 mmask;
+    A_UINT16 tsr;
+    A_BOOL   rep;
+    A_UINT16 size;
+} DBGLOG_MODULE_CONFIG;
+
+typedef struct user_rssi_thold_t {
+    A_INT16     tag;
+    A_INT16     rssi;
+} USER_RSSI_THOLD;
+
+typedef struct user_rssi_params_t {
+    A_UINT8            weight;
+    A_UINT32           pollTime;
+    USER_RSSI_THOLD    tholds[12];
+} USER_RSSI_PARAMS;
+
+typedef struct ar6000_get_btcoex_config_cmd_t{
+	A_UINT32 btProfileType;
+	A_UINT32 linkId;
+ }AR6000_GET_BTCOEX_CONFIG_CMD;
+
+typedef struct ar6000_btcoex_config_t {
+    AR6000_GET_BTCOEX_CONFIG_CMD  configCmd;
+    A_UINT32 * configEvent;
+} AR6000_BTCOEX_CONFIG;
+
+typedef struct ar6000_btcoex_stats_t {
+    A_UINT32 * statsEvent;
+ }AR6000_BTCOEX_STATS;
+/*
+ * Host driver may have some config parameters. Typically, these
+ * config params are one time config parameters. These could
+ * correspond to any of the underlying modules. Host driver exposes
+ * an api for the underlying modules to get this config.
+ */
+#define AR6000_DRIVER_CFG_BASE                  0x8000
+
+/* Should driver perform wlan node caching? */
+#define AR6000_DRIVER_CFG_GET_WLANNODECACHING   0x8001
+/*Should we log raw WMI msgs */
+#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS      0x8002
+
+/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
+struct ar6000_diag_window_cmd_s {
+    unsigned int addr;
+    unsigned int value;
+};
+
+
+struct ar6000_traffic_activity_change {
+    A_UINT32    StreamID;   /* stream ID to indicate activity change */
+    A_UINT32    Active;     /* active (1) or inactive (0) */
+};
+
+/* Used with AR6000_XIOCTL_PROF_COUNT_GET */
+struct prof_count_s {
+    A_UINT32    addr;       /* bin start address */
+    A_UINT32    count;      /* hit count */
+};
+
+
+/* used by AR6000_XIOCTL_MODULE_DEBUG_SET_MASK */
+/*         AR6000_XIOCTL_MODULE_DEBUG_GET_MASK */
+/*         AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO */
+struct drv_debug_module_s {
+    A_CHAR      modulename[128];   /* name of module */
+    A_UINT32    mask;              /* new mask to set .. or .. current mask */
+};
+
+
+/* All HCI related rx events are sent up to the host app
+ * via a wmi event id. It can contain ACL data or HCI event, 
+ * based on which it will be de-multiplexed.
+ */
+typedef enum {
+    PAL_HCI_EVENT = 0,
+    PAL_HCI_RX_DATA,
+} WMI_PAL_EVENT_INFO;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h
new file mode 100644
index 000000000000..a2bd9e953cd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h
@@ -0,0 +1,47 @@
+/*
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _ATHTYPES_LINUX_H_
+#define _ATHTYPES_LINUX_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <sys/types.h>
+#endif
+
+typedef int8_t      A_INT8;
+typedef int16_t     A_INT16;
+typedef int32_t     A_INT32;
+typedef int64_t     A_INT64;
+
+typedef u_int8_t     A_UINT8;
+typedef u_int16_t    A_UINT16;
+typedef u_int32_t    A_UINT32;
+typedef u_int64_t    A_UINT64;
+
+typedef int             A_BOOL;
+typedef char            A_CHAR;
+typedef unsigned char   A_UCHAR;
+typedef unsigned long   A_ATH_TIMER;
+
+
+#endif /* _ATHTYPES_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h
new file mode 100644
index 000000000000..2fac60b8a589
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h
@@ -0,0 +1,46 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _AR6K_CFG80211_H_
+#define _AR6K_CFG80211_H_
+
+struct wireless_dev *ar6k_cfg80211_init(struct device *dev);
+void ar6k_cfg80211_deinit(AR_SOFTC_T *ar);
+
+void ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status);
+
+void ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+                                A_UINT8 *bssid, A_UINT16 listenInterval,
+                                A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+                                A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+                                A_UINT8 assocRespLen, A_UINT8 *assocInfo);
+
+void ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+                                    A_UINT8 *bssid, A_UINT8 assocRespLen,
+                                    A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+
+void ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast);
+
+#endif /* _AR6K_CFG80211_H_ */
+
+
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h
new file mode 100644
index 000000000000..78b95bf7faa4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _CONFIG_LINUX_H_
+#define _CONFIG_LINUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/version.h>
+
+/*
+ * Host-side GPIO support is optional.
+ * If run-time access to GPIO pins is not required, then
+ * this should be changed to #undef.
+ */
+#define CONFIG_HOST_GPIO_SUPPORT
+
+/*
+ * Host side Test Command support
+ */
+#define CONFIG_HOST_TCMD_SUPPORT
+
+#define USE_4BYTE_REGISTER_ACCESS
+
+/* Host-side support for Target-side profiling */
+#undef CONFIG_TARGET_PROFILE_SUPPORT
+
+/* IP/TCP checksum offload */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+#define CONFIG_CHECKSUM_OFFLOAD
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h
new file mode 100644
index 000000000000..6ef4cb6953d9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _DEBUG_LINUX_H_
+#define _DEBUG_LINUX_H_
+
+    /* macro to remove parens */
+#define ATH_PRINTX_ARG(arg...) arg
+
+#ifdef DEBUG
+    /* NOTE: the AR_DEBUG_PRINTF macro is defined here to handle special handling of variable arg macros
+     * which may be compiler dependent. */
+#define AR_DEBUG_PRINTF(mask, args) do {        \
+    if (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (mask)) {                    \
+        A_PRINTF(ATH_PRINTX_ARG args);    \
+    }                                            \
+} while (0)
+#else
+    /* on non-debug builds, keep in error and warning messages in the driver, all other
+     * message tracing will get compiled out */
+#define AR_DEBUG_PRINTF(mask, args) \
+    if ((mask) & (ATH_DEBUG_ERR | ATH_DEBUG_WARN)) { A_PRINTF(ATH_PRINTX_ARG args); }
+
+#endif
+
+    /* compile specific macro to get the function name string */
+#define _A_FUNCNAME_  __func__
+
+
+#endif /* _DEBUG_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h
new file mode 100644
index 000000000000..b3d51b44906a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h
@@ -0,0 +1,70 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+//    Copyright (c) 2009 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "hci_transport_api.h"
+#include "common_drv.h"
+
+extern HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+extern void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+extern A_STATUS    (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+extern void        (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS    (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+extern A_STATUS    (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, 
+                                          HTC_PACKET           *pPacket,
+                                          int                  MaxPollMS);
+extern A_STATUS    (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+
+#define HCI_TransportAttach(HTCHandle, pInfo)   \
+            _HCI_TransportAttach((HTCHandle), (pInfo))
+#define HCI_TransportDetach(HciTrans)    \
+            _HCI_TransportDetach(HciTrans)
+#define HCI_TransportAddReceivePkts(HciTrans, pQueue)   \
+            _HCI_TransportAddReceivePkts((HciTrans), (pQueue))
+#define HCI_TransportSendPkt(HciTrans, pPacket, Synchronous)  \
+            _HCI_TransportSendPkt((HciTrans), (pPacket), (Synchronous))
+#define HCI_TransportStop(HciTrans)  \
+            _HCI_TransportStop((HciTrans))
+#define HCI_TransportStart(HciTrans)  \
+            _HCI_TransportStart((HciTrans))
+#define HCI_TransportEnableDisableAsyncRecv(HciTrans, Enable)   \
+            _HCI_TransportEnableDisableAsyncRecv((HciTrans), (Enable))
+#define HCI_TransportRecvHCIEventSync(HciTrans, pPacket, MaxPollMS)   \
+            _HCI_TransportRecvHCIEventSync((HciTrans), (pPacket), (MaxPollMS))
+#define HCI_TransportSetBaudRate(HciTrans, Baud)    \
+            _HCI_TransportSetBaudRate((HciTrans), (Baud))
+
+
+extern A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks);
+
+extern A_STATUS ar6000_get_hif_dev(HIF_DEVICE *device, void *config);
+
+extern A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, A_UINT32 scale, A_UINT32 step);
+
+/* get core clock register settings
+ * data: 0 - 40/44MHz
+ *       1 - 80/88MHz
+ *       where (5G band/2.4G band)
+ * assume 2.4G band for now
+ */
+extern A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data);
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h
new file mode 100644
index 000000000000..29c68886d92e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _IEEE80211_IOCTL_H_
+#define _IEEE80211_IOCTL_H_
+
+#include <linux/version.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
+ */
+
+/*
+ * WPA/RSN get/set key request.  Specify the key/cipher
+ * type and whether the key is to be used for sending and/or
+ * receiving.  The key index should be set only when working
+ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
+ * Otherwise a unicast/pairwise key is specified by the bssid
+ * (on a station) or mac address (on an ap).  They key length
+ * must include any MIC key data; otherwise it should be no
+ more than IEEE80211_KEYBUF_SIZE.
+ */
+struct ieee80211req_key {
+    u_int8_t    ik_type;    /* key/cipher type */
+    u_int8_t    ik_pad;
+    u_int16_t   ik_keyix;   /* key index */
+    u_int8_t    ik_keylen;  /* key length in bytes */
+    u_int8_t    ik_flags;
+#define IEEE80211_KEY_XMIT  0x01
+#define IEEE80211_KEY_RECV  0x02
+#define IEEE80211_KEY_DEFAULT   0x80    /* default xmit key */
+    u_int8_t    ik_macaddr[IEEE80211_ADDR_LEN];
+    u_int64_t   ik_keyrsc;  /* key receive sequence counter */
+    u_int64_t   ik_keytsc;  /* key transmit sequence counter */
+    u_int8_t    ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
+};
+/*
+ * Delete a key either by index or address.  Set the index
+ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
+ */
+struct ieee80211req_del_key {
+    u_int8_t    idk_keyix;  /* key index */
+    u_int8_t    idk_macaddr[IEEE80211_ADDR_LEN];
+};
+/*
+ * MLME state manipulation request.  IEEE80211_MLME_ASSOC
+ * only makes sense when operating as a station.  The other
+ * requests can be used when operating as a station or an
+ * ap (to effect a station).
+ */
+struct ieee80211req_mlme {
+    u_int8_t    im_op;      /* operation to perform */
+#define IEEE80211_MLME_ASSOC        1   /* associate station */
+#define IEEE80211_MLME_DISASSOC     2   /* disassociate station */
+#define IEEE80211_MLME_DEAUTH       3   /* deauthenticate station */
+#define IEEE80211_MLME_AUTHORIZE    4   /* authorize station */
+#define IEEE80211_MLME_UNAUTHORIZE  5   /* unauthorize station */
+    u_int16_t   im_reason;  /* 802.11 reason code */
+    u_int8_t    im_macaddr[IEEE80211_ADDR_LEN];
+};
+
+struct ieee80211req_addpmkid {
+    u_int8_t    pi_bssid[IEEE80211_ADDR_LEN];
+    u_int8_t    pi_enable;
+    u_int8_t    pi_pmkid[16];
+};
+
+#define AUTH_ALG_OPEN_SYSTEM    0x01
+#define AUTH_ALG_SHARED_KEY 0x02
+#define AUTH_ALG_LEAP       0x04
+
+struct ieee80211req_authalg {
+   u_int8_t auth_alg;
+};  
+
+/* 
+ * Request to add an IE to a Management Frame
+ */
+enum{
+    IEEE80211_APPIE_FRAME_BEACON     = 0,
+    IEEE80211_APPIE_FRAME_PROBE_REQ  = 1,
+    IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
+    IEEE80211_APPIE_FRAME_ASSOC_REQ  = 3,
+    IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
+    IEEE80211_APPIE_NUM_OF_FRAME     = 5
+};
+
+/*
+ * The Maximum length of the IE that can be added to a Management frame
+ */
+#define IEEE80211_APPIE_FRAME_MAX_LEN  200
+
+struct ieee80211req_getset_appiebuf {
+    u_int32_t app_frmtype; /* management frame type for which buffer is added */
+    u_int32_t app_buflen;  /*application supplied buffer length */
+    u_int8_t  app_buf[];
+};
+
+/* 
+ * The following definitions are used by an application to set filter
+ * for receiving management frames 
+ */
+enum {
+     IEEE80211_FILTER_TYPE_BEACON      =   0x1,
+     IEEE80211_FILTER_TYPE_PROBE_REQ   =   0x2,
+     IEEE80211_FILTER_TYPE_PROBE_RESP  =   0x4,
+     IEEE80211_FILTER_TYPE_ASSOC_REQ   =   0x8,
+     IEEE80211_FILTER_TYPE_ASSOC_RESP  =   0x10,
+     IEEE80211_FILTER_TYPE_AUTH        =   0x20,
+     IEEE80211_FILTER_TYPE_DEAUTH      =   0x40,
+     IEEE80211_FILTER_TYPE_DISASSOC    =   0x80,
+     IEEE80211_FILTER_TYPE_ALL         =   0xFF  /* used to check the valid filter bits */
+};
+
+struct ieee80211req_set_filter {
+      u_int32_t app_filterype; /* management frame filter type */
+};
+
+enum {
+    IEEE80211_PARAM_AUTHMODE = 3,   /* Authentication Mode */
+    IEEE80211_PARAM_MCASTCIPHER = 5,
+    IEEE80211_PARAM_MCASTKEYLEN = 6,    /* multicast key length */
+    IEEE80211_PARAM_UCASTCIPHER = 8,
+    IEEE80211_PARAM_UCASTKEYLEN = 9,    /* unicast key length */
+    IEEE80211_PARAM_WPA     = 10,   /* WPA mode (0,1,2) */
+    IEEE80211_PARAM_ROAMING     = 12,   /* roaming mode */
+    IEEE80211_PARAM_PRIVACY     = 13,   /* privacy invoked */
+    IEEE80211_PARAM_COUNTERMEASURES = 14,   /* WPA/TKIP countermeasures */
+    IEEE80211_PARAM_DROPUNENCRYPTED = 15,   /* discard unencrypted frames */
+    IEEE80211_PARAM_WAPI = 16,   /* WAPI policy from wapid */        
+};
+
+/*
+ * Values for IEEE80211_PARAM_WPA
+ */
+#define WPA_MODE_WPA1   1
+#define WPA_MODE_WPA2   2
+#define WPA_MODE_AUTO   3
+#define WPA_MODE_NONE   4
+
+struct ieee80211req_wpaie {
+    u_int8_t    wpa_macaddr[IEEE80211_ADDR_LEN];
+    u_int8_t    wpa_ie[IEEE80211_MAX_IE];
+    u_int8_t    rsn_ie[IEEE80211_MAX_IE];
+};
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
+#define IW_ENCODE_ALG_PMK       4
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IEEE80211_IOCTL_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h
new file mode 100644
index 000000000000..23d81c2bc3da
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h
@@ -0,0 +1,361 @@
+/*
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _OSAPI_LINUX_H_
+#define _OSAPI_LINUX_H_
+
+#ifdef __KERNEL__
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+#include <linux/jiffies.h>
+#endif
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#ifdef KERNEL_2_4
+#include <asm/arch/irq.h>
+#include <asm/irq.h>
+#endif
+
+#include <linux/cache.h>
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK           __attribute__ ((packed))
+#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE                  __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE                  __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK                __ATTRIB_PACK
+
+/*
+ * Endianes macros
+ */
+#define A_BE2CPU8(x)       ntohb(x)
+#define A_BE2CPU16(x)      ntohs(x)
+#define A_BE2CPU32(x)      ntohl(x)
+
+#define A_LE2CPU8(x)       (x)
+#define A_LE2CPU16(x)      (x)
+#define A_LE2CPU32(x)      (x)
+
+#define A_CPU2BE8(x)       htonb(x)
+#define A_CPU2BE16(x)      htons(x)
+#define A_CPU2BE32(x)      htonl(x)
+
+#define A_MEMCPY(dst, src, len)         memcpy((A_UINT8 *)(dst), (src), (len))
+#define A_MEMZERO(addr, len)            memset(addr, 0, len)
+#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size)                  kmalloc((size), GFP_KERNEL)
+#define A_MALLOC_NOWAIT(size)           kmalloc((size), GFP_ATOMIC)
+#define A_FREE(addr)                    kfree(addr)
+#define A_PRINTF(args...)               printk(KERN_ALERT args)
+#define A_PRINTF_LOG(args...)           printk(args)
+#define A_SPRINTF(buf, args...)			sprintf (buf, args)
+
+/* Mutual Exclusion */
+typedef spinlock_t                      A_MUTEX_T;
+#define A_MUTEX_INIT(mutex)             spin_lock_init(mutex)
+#define A_MUTEX_LOCK(mutex)             spin_lock_bh(mutex)
+#define A_MUTEX_UNLOCK(mutex)           spin_unlock_bh(mutex)
+#define A_IS_MUTEX_VALID(mutex)         TRUE  /* okay to return true, since A_MUTEX_DELETE does nothing */
+#define A_MUTEX_DELETE(mutex)           /* spin locks are not kernel resources so nothing to free.. */
+
+/* Get current time in ms adding a constant offset (in ms) */
+#define A_GET_MS(offset)    \
+	(jiffies + ((offset) / 1000) * HZ)
+
+/*
+ * Timer Functions
+ */
+#define A_MDELAY(msecs)                 mdelay(msecs)
+typedef struct timer_list               A_TIMER;
+
+#define A_INIT_TIMER(pTimer, pFunction, pArg) do {              \
+    init_timer(pTimer);                                         \
+    (pTimer)->function = (pFunction);                           \
+    (pTimer)->data   = (unsigned long)(pArg);                   \
+} while (0)
+
+/*
+ * Start a Timer that elapses after 'periodMSec' milli-seconds
+ * Support is provided for a one-shot timer. The 'repeatFlag' is
+ * ignored.
+ */
+#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do {                   \
+    if (repeatFlag) {                                                       \
+        printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__);     \
+        panic("Timer Repeat");                                              \
+    }                                                                       \
+    mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000);                \
+} while (0)
+
+/*
+ * Cancel the Timer. 
+ */
+#define A_UNTIMEOUT(pTimer) do {                                \
+    del_timer((pTimer));                                        \
+} while (0)
+
+#define A_DELETE_TIMER(pTimer) do {                             \
+} while (0)
+
+/*
+ * Wait Queue related functions
+ */
+typedef wait_queue_head_t               A_WAITQUEUE_HEAD;
+#define A_INIT_WAITQUEUE_HEAD(head)     init_waitqueue_head(head)
+#ifndef wait_event_interruptible_timeout
+#define __wait_event_interruptible_timeout(wq, condition, ret)          \
+do {                                                                    \
+        wait_queue_t __wait;                                            \
+        init_waitqueue_entry(&__wait, current);                         \
+                                                                        \
+        add_wait_queue(&wq, &__wait);                                   \
+        for (;;) {                                                      \
+                set_current_state(TASK_INTERRUPTIBLE);                  \
+                if (condition)                                          \
+                        break;                                          \
+                if (!signal_pending(current)) {                         \
+                        ret = schedule_timeout(ret);                    \
+                        if (!ret)                                       \
+                                break;                                  \
+                        continue;                                       \
+                }                                                       \
+                ret = -ERESTARTSYS;                                     \
+                break;                                                  \
+        }                                                               \
+        current->state = TASK_RUNNING;                                  \
+        remove_wait_queue(&wq, &__wait);                                \
+} while (0)
+
+#define wait_event_interruptible_timeout(wq, condition, timeout)        \
+({                                                                      \
+        long __ret = timeout;                                           \
+        if (!(condition))                                               \
+                __wait_event_interruptible_timeout(wq, condition, __ret); \
+        __ret;                                                          \
+})
+#endif /* wait_event_interruptible_timeout */
+
+#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
+    wait_event_interruptible_timeout(head, condition, timeout); \
+} while (0)
+
+#define A_WAKE_UP(head)                 wake_up(head)
+
+#ifdef DEBUG
+extern unsigned int panic_on_assert;
+#define A_ASSERT(expr)  \
+    if (!(expr)) {   \
+        printk(KERN_ALERT"Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#expr); \
+        if (panic_on_assert) panic(#expr);                                                               \
+    }
+#else
+#define A_ASSERT(expr)
+#endif /* DEBUG */
+
+#ifdef ANDROID_ENV
+struct firmware;
+int android_request_firmware(const struct firmware **firmware_p, const char *filename,
+                     struct device *device);
+void android_release_firmware(const struct firmware *firmware);
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) android_request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) android_release_firmware(_pf)
+#else
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) release_firmware(_pf)
+#endif 
+
+/*
+ * Initialization of the network buffer subsystem
+ */
+#define A_NETBUF_INIT()
+
+/*
+ * Network buffer queue support
+ */
+typedef struct sk_buff_head A_NETBUF_QUEUE_T;
+
+#define A_NETBUF_QUEUE_INIT(q)  \
+    a_netbuf_queue_init(q)
+
+#define A_NETBUF_ENQUEUE(q, pkt) \
+    a_netbuf_enqueue((q), (pkt))
+#define A_NETBUF_PREQUEUE(q, pkt) \
+    a_netbuf_prequeue((q), (pkt))
+#define A_NETBUF_DEQUEUE(q) \
+    (a_netbuf_dequeue(q))
+#define A_NETBUF_QUEUE_SIZE(q)  \
+    a_netbuf_queue_size(q)
+#define A_NETBUF_QUEUE_EMPTY(q) \
+    a_netbuf_queue_empty(q)
+
+/*
+ * Network buffer support
+ */
+#define A_NETBUF_ALLOC(size) \
+    a_netbuf_alloc(size)
+#define A_NETBUF_ALLOC_RAW(size) \
+    a_netbuf_alloc_raw(size)
+#define A_NETBUF_FREE(bufPtr) \
+    a_netbuf_free(bufPtr)
+#define A_NETBUF_DATA(bufPtr) \
+    a_netbuf_to_data(bufPtr)
+#define A_NETBUF_LEN(bufPtr) \
+    a_netbuf_to_len(bufPtr)
+#define A_NETBUF_PUSH(bufPtr, len) \
+    a_netbuf_push(bufPtr, len)
+#define A_NETBUF_PUT(bufPtr, len) \
+    a_netbuf_put(bufPtr, len)
+#define A_NETBUF_TRIM(bufPtr,len) \
+    a_netbuf_trim(bufPtr, len)
+#define A_NETBUF_PULL(bufPtr, len) \
+    a_netbuf_pull(bufPtr, len)
+#define A_NETBUF_HEADROOM(bufPtr)\
+    a_netbuf_headroom(bufPtr)
+#define A_NETBUF_SETLEN(bufPtr,len) \
+    a_netbuf_setlen(bufPtr, len)
+
+/* Add data to end of a buffer  */
+#define A_NETBUF_PUT_DATA(bufPtr, srcPtr,  len) \
+    a_netbuf_put_data(bufPtr, srcPtr, len) 
+
+/* Add data to start of the  buffer */
+#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr,  len) \
+    a_netbuf_push_data(bufPtr, srcPtr, len) 
+
+/* Remove data at start of the buffer */
+#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
+    a_netbuf_pull_data(bufPtr, dstPtr, len) 
+
+/* Remove data from the end of the buffer */
+#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
+    a_netbuf_trim_data(bufPtr, dstPtr, len) 
+
+/* View data as "size" contiguous bytes of type "t" */
+#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
+    (t )( ((struct skbuf *)(bufPtr))->data)
+
+/* return the beginning of the headroom for the buffer */
+#define A_NETBUF_HEAD(bufPtr) \
+        ((((struct sk_buff *)(bufPtr))->head))
+    
+/*
+ * OS specific network buffer access routines
+ */
+void *a_netbuf_alloc(int size);
+void *a_netbuf_alloc_raw(int size);
+void a_netbuf_free(void *bufPtr);
+void *a_netbuf_to_data(void *bufPtr);
+A_UINT32 a_netbuf_to_len(void *bufPtr);
+A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
+A_INT32 a_netbuf_headroom(void *bufPtr);
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
+
+/*
+ * Kernel v.s User space functions
+ */
+A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
+A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
+
+/* In linux, WLAN Rx and Tx run in different contexts, so no need to check
+ * for any commands/data queued for WLAN */
+#define A_CHECK_DRV_TX()   
+             
+#define A_GET_CACHE_LINE_BYTES()    L1_CACHE_BYTES
+
+static inline void *A_ALIGN_TO_CACHE_LINE(void *ptr) {   
+    return (void *)L1_CACHE_ALIGN((A_UINT32)ptr);
+}
+   
+#else /* __KERNEL__ */
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK           __attribute__ ((packed))
+#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE                  __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE                  __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK                __ATTRIB_PACK
+
+#define A_MEMCPY(dst, src, len)         memcpy((dst), (src), (len))
+#define A_MEMZERO(addr, len)            memset((addr), 0, (len))
+#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size)                  malloc(size)
+#define A_FREE(addr)                    free(addr)
+
+#ifdef ANDROID
+#ifndef err
+#include <errno.h>
+#define err(_s, args...) do { \
+    fprintf(stderr, "%s: line %d ", __FILE__, __LINE__); \
+    fprintf(stderr, args); fprintf(stderr, ": %d\n", errno); \
+    exit(_s); } while (0)
+#endif
+#else
+#include <err.h>
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _OSAPI_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h
new file mode 100644
index 000000000000..97e090f95481
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_config.h" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the tunable configuration items for the WLAN module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_CONFIG_H_
+#define _HOST_WLAN_CONFIG_H_
+
+/* Include definitions here that can be used to tune the WLAN module behavior.
+ * Different customers can tune the behavior as per their needs, here. 
+ */
+
+/* This configuration item when defined will consider the barker preamble 
+ * mentioned in the ERP IE of the beacons from the AP to determine the short 
+ * preamble support sent in the (Re)Assoc request frames.
+ */
+#define WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 0
+
+/* This config item when defined will not send the power module state transition
+ * failure events that happen during scan, to the host. 
+ */
+#define WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 0
+
+/*
+ * This configuration item enable/disable keepalive support.
+ * Keepalive support: In the absence of any data traffic to AP, null 
+ * frames will be sent to the AP at periodic interval, to keep the association
+ * active. This configuration item defines the periodic interval.
+ * Use value of zero to disable keepalive support
+ * Default: 60 seconds
+ */
+#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 
+
+
+#endif /* _HOST_WLAN_CONFIG_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h
new file mode 100644
index 000000000000..ab9a9fc0d0fd
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ */
+
+#ifndef _WMI_FILTER_LINUX_H_
+#define  _WMI_FILTER_LINUX_H_
+
+/*
+ * sioctl_filter - Standard ioctl
+ * pioctl_filter - Priv ioctl
+ * xioctl_filter - eXtended ioctl
+ *
+ * ---- Possible values for the WMI filter ---------------
+ * (0) - Block this cmd always (or) not implemented
+ * (INFRA_NETWORK) - Allow this cmd only in STA mode
+ * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode
+ * (AP_NETWORK) -    Allow this cmd only in AP mode
+ * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode
+ * (ADHOC_NETWORK | AP_NETWORK) -    Block this cmd in STA mode
+ * (INFRA_NETWORK | AP_NETWORK) -    Block this cmd in IBSS mode
+ * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set
+ * (0xFF) - Allow this cmd always irrespective of mode
+ */
+
+A_UINT8 sioctl_filter[] = {
+(AP_NETWORK),                                   /* SIOCSIWCOMMIT   0x8B00   */
+(0xFF),                                         /* SIOCGIWNAME     0x8B01   */
+(0),                                            /* SIOCSIWNWID     0x8B02   */
+(0),                                            /* SIOCGIWNWID     0x8B03   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWFREQ     0x8B04   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWFREQ     0x8B05   */
+(0xFF),                                         /* SIOCSIWMODE     0x8B06   */
+(0xFF),                                         /* SIOCGIWMODE     0x8B07   */
+(0),                                            /* SIOCSIWSENS     0x8B08   */
+(0),                                            /* SIOCGIWSENS     0x8B09   */
+(0),                                            /* SIOCSIWRANGE    0x8B0A   */
+(0xFF),                                         /* SIOCGIWRANGE    0x8B0B   */
+(0),                                            /* SIOCSIWPRIV     0x8B0C   */
+(0),                                            /* SIOCGIWPRIV     0x8B0D   */
+(0),                                            /* SIOCSIWSTATS    0x8B0E   */
+(0),                                            /* SIOCGIWSTATS    0x8B0F   */
+(0),                                            /* SIOCSIWSPY      0x8B10   */
+(0),                                            /* SIOCGIWSPY      0x8B11   */
+(0),                                            /* SIOCSIWTHRSPY   0x8B12   */
+(0),                                            /* SIOCGIWTHRSPY   0x8B13   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWAP       0x8B14   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWAP       0x8B15   */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWMLME     0X8B16   */
+#else
+(0),                                            /* Dummy           0        */
+#endif /* LINUX_VERSION_CODE */
+(0),                                            /* SIOCGIWAPLIST   0x8B17   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWSCAN     0x8B18   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCGIWSCAN     0x8B19   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWESSID    0x8B1A   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWESSID    0x8B1B   */
+(0),                                            /* SIOCSIWNICKN    0x8B1C   */
+(0),                                            /* SIOCGIWNICKN    0x8B1D   */
+(0),                                            /* Dummy           0        */
+(0),                                            /* Dummy           0        */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWRATE     0x8B20   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWRATE     0x8B21   */
+(0),                                            /* SIOCSIWRTS      0x8B22   */
+(0),                                            /* SIOCGIWRTS      0x8B23   */
+(0),                                            /* SIOCSIWFRAG     0x8B24   */
+(0),                                            /* SIOCGIWFRAG     0x8B25   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWTXPOW    0x8B26   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWTXPOW    0x8B27   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCSIWRETRY    0x8B28   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* SIOCGIWRETRY    0x8B29   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWENCODE   0x8B2A   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWENCODE   0x8B2B   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCSIWPOWER    0x8B2C   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* SIOCGIWPOWER    0x8B2D   */
+};
+
+
+
+A_UINT8 pioctl_filter[] = {
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)     */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+1)     */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+2)     */
+(AP_NETWORK),                                   /* IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+3)     */
+(INFRA_NETWORK),                                /* IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+4)     */
+(0),                                            /* IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+5)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+6)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+7)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+8)     */
+(0),                                            /*                                      (SIOCIWFIRSTPRIV+9)     */
+(0),                                            /* IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+10)    */
+(0xFF),                                         /* AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+11)    */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+12)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+13)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+14)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+15)    */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)    */
+(INFRA_NETWORK),                                /* AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD    (SIOCIWFIRSTPRIV+23)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/
+(0xFF),                                         /* AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)    */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)    */
+(ADHOC_NETWORK),                                /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)    */
+};
+
+
+
+A_UINT8 xioctl_filter[] = {
+(0xFF),                                         /* Dummy                                           0    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_DONE                          1    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_READ_MEMORY                   2    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_WRITE_MEMORY                  3    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_EXECUTE                       4    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_SET_APP_START                 5    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER             6    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER            7    */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_TEST                          8    */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED9                           9    */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED10                          10   */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED11                          11   */
+(0xFF),                                         /* AR6000_XIOCTL_FORCE_TARGET_RESET                12   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_OPEN                      13   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_CLOSE                     14   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_READ                      15   */
+(0xFF),                                         /* AR6000_XIOCTL_HTC_RAW_WRITE                     16   */
+(0xFF),                                         /* AR6000_XIOCTL_CHECK_TARGET_READY                17   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_OUTPUT_SET                   18   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INPUT_GET                    19   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_REGISTER_SET                 20   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_REGISTER_GET                 21   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INTR_ACK                     22   */
+(0xFF),                                         /* AR6000_XIOCTL_GPIO_INTR_WAIT                    23   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_ADHOC_BSSID                   24   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_OPT_MODE                      25   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_OPT_SEND_FRAME                    26   */
+(ADHOC_NETWORK | AP_NETWORK),                   /* AR6000_XIOCTL_SET_BEACON_INTVAL                 27   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* IEEE80211_IOCTL_SETAUTHALG                      28   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE                29   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_MAX_SP                        30   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_ROAM_TBL                  31   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL                 32   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS         33   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTRL_WMI_GET_POWER_MODE               34   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE               35   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_ROAM_DATA                 36   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SETRETRYLIMITS                37   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_CONT_TX                      38   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_CONT_RX                      39   */
+(0xFF),                                         /* AR6000_XIOCTL_TCMD_PM                           40   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_STARTSCAN                     41   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SETFIXRATES                   42   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_GETFIXRATES                   43   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_CLR_RSSISNR                   45   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_RTS                       47   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_SET_AUTHMODE                  49   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_REASSOCMODE               50   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_WMM                       51   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53   */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK),   /* AR6000_XIOCTL_WMI_GET_RD                        54   */
+(0xFF),                                         /* AR6000_XIOCTL_DIAG_READ                         55   */
+(0xFF),                                         /* AR6000_XIOCTL_DIAG_WRITE                        56   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_TXOP                      57   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_USER_SETKEYS                      58   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59   */
+(INFRA_NETWORK),                                /* AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_APPIE                     65   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER        66   */
+(0xFF),                                         /* AR6000_XIOCTL_DBGLOG_CFG_MODULE                 67   */
+(0xFF),                                         /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS             68   */
+(0xFF),                                         /* Dummy                                           69   */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_SET_WSC_STATUS                70   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BT_STATUS                 71   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_BT_PARAMS                 72   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE           73   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_WOW_MODE                  74   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_WOW_LIST                  75   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN               76   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN               77   */
+(0xFF),                                         /* AR6000_XIOCTL_TARGET_INFO                       78   */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE             79   */
+(0xFF),                                         /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE           80   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS        81   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS               82   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_GET_PMKID_LIST                83   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_SET_PMKID_LIST                84   */
+(0xFF),                                         /* Dummy                                           85   */
+(0xFF),                                         /* Dummy                                           86   */
+(0xFF),                                         /* Dummy                                           87   */
+(0xFF),                                         /* Dummy                                           88   */
+(0xFF),                                         /* Dummy                                           89   */
+(0xFF),                                         /* AR6000_XIOCTL_UNUSED90                          90   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_LZ_STREAM_START               91   */
+(0xFF),                                         /* AR6000_XIOCTL_BMI_LZ_DATA                       92   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_CFG                          93   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_ADDR_SET                     94   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_START                        95   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_STOP                         96   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_PROF_COUNT_GET                    97   */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_WMI_ABORT_SCAN                    98   */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_STA_LIST                   99   */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_HIDDEN_SSID                    100  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_NUM_STA                    101  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_ACL_MAC                    102  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_ACL_LIST                   103  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_COMMIT_CONFIG                  104  */
+(AP_NETWORK),                                   /* IEEE80211_IOCTL_GETWPAIE                        105  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_CONN_INACT_TIME                106  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_PROT_SCAN_TIME                 107  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_WMI_SET_COUNTRY                   108  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_DTIM                       109  */
+(0xFF),                                         /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT           110  */
+(INFRA_NETWORK | ADHOC_NETWORK),                /* AR6000_XIOCTL_SET_IP                            111  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_ACL_POLICY                 112  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_INTRA_BSS_COMM                 113  */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO            114  */
+(0xFF),                                         /* AR6000_XIOCTL_MODULE_DEBUG_SET_MASK             115  */
+(0xFF),                                         /* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK             116  */
+(0xFF),                                         /* AR6000_XIOCTL_DUMP_RCV_AGGR_STATS               117  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_HT_CAP                        118  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_HT_OP                         119  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_STAT                       120  */
+(0xFF),                                         /* AR6000_XIOCTL_SET_TX_SELECT_RATES               121  */
+(0xFF),                                         /* AR6000_XIOCTL_SETUP_AGGR                        122  */
+(0xFF),                                         /* AR6000_XIOCTL_ALLOW_AGGR                        123  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_HIDDEN_SSID                124  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_COUNTRY                    125  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_WMODE                      126  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_GET_DTIM                       127  */
+(AP_NETWORK | ADHOC_NETWORK),                   /* AR6000_XIOCTL_AP_GET_BINTVL                     128  */
+(0xFF),                                         /* AR6000_XIOCTL_AP_GET_RTS                        129  */
+(0xFF),                                         /* AR6000_XIOCTL_DELE_AGGR                         130  */
+(0xFF),                                         /* AR6000_XIOCTL_FETCH_TARGET_REGS                 131  */
+(0xFF),                                         /* AR6000_XIOCTL_HCI_CMD                           132  */
+(0xFF),                                         /* AR6000_XIOCTL_ACL_DATA                          133  */
+(0xFF),                                         /* AR6000_XIOCTL_WLAN_CONN_PRECEDENCE              134  */
+(AP_NETWORK),                                   /* AR6000_XIOCTL_AP_SET_11BG_RATESET               135  */
+(0xFF),
+(0xFF),
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT 138*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV 139*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/*  AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG  140*/
+(INFRA_NETWORK | ADHOC_NETWORK), 				/*  AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG 141*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/*  AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG 142*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG  143*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG	 144*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS	145*/
+(INFRA_NETWORK | ADHOC_NETWORK),				/* AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG  146*/
+(INFRA_NETWORK | ADHOC_NETWORK), 				/* AR6000_XIOCTL_WMI_GET_BTCOEX_GET_STATS 147*/
+
+};
+
+#endif /*_WMI_FILTER_LINUX_H_*/
diff --git a/drivers/net/wireless/ath6kl/os/linux/ioctl.c b/drivers/net/wireless/ath6kl/os/linux/ioctl.c
new file mode 100644
index 000000000000..902f0701dabd
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ioctl.c
@@ -0,0 +1,4559 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#include "ar6000_drv.h"
+#include "ieee80211_ioctl.h"
+#include "ar6kap_common.h"
+#include "targaddrs.h"
+#include "a_hci.h"
+#include "wlan_config.h"
+
+extern int enablerssicompensation;
+A_UINT32 tcmdRxFreq;
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+extern int tspecCompliance;
+extern int bmienable;
+extern int bypasswmi;
+extern int loghci;
+
+static int
+ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    /* currently assume only roam times are required */
+    if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
+        return -EIO;
+    }
+
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_ROAM_CTRL_CMD cmd;
+    A_UINT8 size = sizeof(cmd);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
+        if (cmd.info.bssBiasInfo.numBss > 1) {
+            size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
+        }
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
+    A_UINT8 size = sizeof(cmd);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if (copy_from_user(&cmd, userdata, size)) {
+        return -EFAULT;
+    }
+
+    if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
+        return -EIO;
+    }
+
+    return 0;
+}
+
+static int
+ar6000_ioctl_set_qos_supp(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_QOS_SUPP_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_qos_supp_cmd(ar->arWmi, cmd.status);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_WMM_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    if (cmd.status == WMI_WMM_ENABLED) {
+        ar->arWmmEnabled = TRUE;
+    } else {
+        ar->arWmmEnabled = FALSE;
+    }
+
+    ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_WMM_TXOP_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_STATUS ret = 0;
+
+    if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
+                            &ar->arRegCode, sizeof(ar->arRegCode)))
+        ret = -EFAULT;
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_AP_SET_COUNTRY_CMD cmd;
+    A_STATUS ret;
+
+    if ((dev->flags & IFF_UP) != IFF_UP) {
+        return -EIO;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+
+    ret = wmi_set_country(ar->arWmi, cmd.countryCode);
+    A_MEMCPY(ar->ap_country_code, cmd.countryCode, 3);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+
+/* Get power mode command */
+static int
+ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE_CMD power_mode;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
+    if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
+        ret = -EFAULT;
+    }
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) {
+        A_PRINTF("ERROR: Only wmode is allowed in AP mode\n");
+        return -EIO;
+    }
+
+    if (cmd.numChannels > 1) {
+        cmdp = A_MALLOC(130);
+        if (copy_from_user(cmdp, rq->ifr_data,
+                           sizeof (*cmdp) +
+                           ((cmd.numChannels - 1) * sizeof(A_UINT16))))
+        {
+            kfree(cmdp);
+            return -EFAULT;
+        }
+    } else {
+        cmdp = &cmd;
+    }
+
+    if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
+        ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
+    {
+        ret = -EINVAL;
+    }
+
+    if (!ret &&
+        (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
+                                   cmdp->numChannels, cmdp->channelList)
+         != A_OK))
+    {
+        ret = -EIO;
+    }
+
+    if (cmd.numChannels > 1) {
+        kfree(cmdp);
+    }
+
+    ar->ap_wmode = cmdp->phyMode;
+    /* Set the profile change flag to allow a commit cmd */
+    ar->ap_profile_flag = 1;
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
+{
+#define SWAP_THOLD(thold1, thold2) do { \
+    USER_RSSI_THOLD tmpThold;           \
+    tmpThold.tag = thold1.tag;          \
+    tmpThold.rssi = thold1.rssi;        \
+    thold1.tag = thold2.tag;            \
+    thold1.rssi = thold2.rssi;          \
+    thold2.tag = tmpThold.tag;          \
+    thold2.rssi = tmpThold.rssi;        \
+} while (0)
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+    USER_RSSI_PARAMS rssiParams;
+    A_INT32 i, j;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
+        return -EFAULT;
+    }
+    cmd.weight = rssiParams.weight;
+    cmd.pollTime = rssiParams.pollTime;
+
+    A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map));
+    /*
+     *  only 6 elements, so use bubble sorting, in ascending order
+     */
+    for (i = 5; i > 0; i--) {
+        for (j = 0; j < i; j++) { /* above tholds */
+            if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+                SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+            } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+                return EFAULT;
+            }
+        }
+    }
+    for (i = 11; i > 6; i--) {
+        for (j = 6; j < i; j++) { /* below tholds */
+            if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+                SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+            } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+                return EFAULT;
+            }
+        }
+    }
+
+#ifdef DEBUG
+    for (i = 0; i < 12; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("thold[%d].tag: %d, thold[%d].rssi: %d \n",
+                i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi));
+    }
+#endif
+
+    if (enablerssicompensation) {
+        for (i = 0; i < 6; i++)
+            ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, TRUE);
+        for (i = 6; i < 12; i++)
+            ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, FALSE);
+    }
+
+    cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi;
+    cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi;
+    cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi;
+    cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi;
+    cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi;
+    cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi;
+    cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi;
+    cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi;
+    cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi;
+    cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi;
+    cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi;
+    cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi;
+
+    if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+
+static int
+ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_PROBED_SSID_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
+                                  cmd.ssid) != A_OK)
+    {
+        ret = -EIO;
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_ADD_BAD_AP_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
+        return -EIO;
+    }
+
+    if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
+        /*
+         * This is a delete badAP.
+         */
+        if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
+            ret = -EIO;
+        }
+    } else {
+        if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
+            ret = -EIO;
+        }
+    }
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_CREATE_PSTREAM_CMD cmd;
+    A_STATUS ret;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
+    if (ret == A_OK)
+        ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_DELETE_PSTREAM_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
+
+    switch (ret) {
+        case A_OK:
+            return 0;
+        case A_EBUSY :
+            return -EBUSY;
+        case A_NO_MEMORY:
+            return -ENOMEM;
+        case A_EINVAL:
+        default:
+            return -EFAULT;
+    }
+}
+
+static int
+ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar6000_queuereq qreq;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if( copy_from_user(&qreq, rq->ifr_data,
+                  sizeof(struct ar6000_queuereq)))
+        return -EFAULT;
+
+    qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
+
+    if (copy_to_user(rq->ifr_data, &qreq,
+                 sizeof(struct ar6000_queuereq)))
+    {
+        ret = -EFAULT;
+    }
+
+    return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
+                                 struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT32    buf[4+TCMD_MAX_RATES];
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->tcmdRxReport = 0;
+    if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    buf[0] = ar->tcmdRxTotalPkt;
+    buf[1] = ar->tcmdRxRssi;
+    buf[2] = ar->tcmdRxcrcErrPkt;
+    buf[3] = ar->tcmdRxsecErrPkt;
+    A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32)), ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
+    A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32))+(TCMD_MAX_RATES *sizeof(A_UINT16)), ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+    if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
+        ret = -EFAULT;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+void
+ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+    TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
+
+    if (enablerssicompensation) {
+        rx_rep->u.report.rssiInDBm = rssi_compensation_calc_tcmd(tcmdRxFreq, rx_rep->u.report.rssiInDBm,rx_rep->u.report.totalPkt);
+    }
+
+
+    ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
+    ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
+    ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt;
+    ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt;
+    ar->tcmdRxReport = 1;
+    A_MEMZERO(ar->tcmdRateCnt,  sizeof(ar->tcmdRateCnt));
+    A_MEMZERO(ar->tcmdRateCntShortGuard,  sizeof(ar->tcmdRateCntShortGuard));
+    A_MEMCPY(ar->tcmdRateCnt, rx_rep->u.report.rateCnt, sizeof(ar->tcmdRateCnt));
+    A_MEMCPY(ar->tcmdRateCntShortGuard, rx_rep->u.report.rateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+    wake_up(&arEvent);
+}
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+static int
+ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_TARGET_ERROR_REPORT_BITMASK cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
+
+    return  (ret==0 ? ret : -EINVAL);
+}
+
+static int
+ar6000_clear_target_stats(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+       return -EIO;
+    }
+    AR6000_SPIN_LOCK(&ar->arLock, 0);
+    A_MEMZERO(pStats, sizeof(TARGET_STATS));
+    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+    return ret;
+}
+
+static int
+ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    TARGET_STATS_CMD cmd;
+    TARGET_STATS *pStats = &ar->arTargetStats;
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+        ret = -EFAULT;
+    }
+
+    if (cmd.clearStats == 1) {
+        ret = ar6000_clear_target_stats(dev);
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_get_ap_stats(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_AP_MODE_STAT cmd;
+    WMI_AP_MODE_STAT *pStats = &ar->arAPStats;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+                                sizeof(cmd)))
+    {
+        return -EFAULT;
+    }
+    if (cmd.action == AP_CLEAR_STATS) {
+        A_UINT8 i;
+        AR6000_SPIN_LOCK(&ar->arLock, 0);
+        for(i = 0; i < AP_MAX_NUM_STA; i++) {
+            pStats->sta[i].tx_bytes = 0;
+            pStats->sta[i].tx_pkts = 0;
+            pStats->sta[i].tx_error = 0;
+            pStats->sta[i].tx_discard = 0;
+            pStats->sta[i].rx_bytes = 0;
+            pStats->sta[i].rx_pkts = 0;
+            pStats->sta[i].rx_error = 0;
+            pStats->sta[i].rx_discard = 0;
+        }
+        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+        return ret;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+        ret = -EFAULT;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+static int
+ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_ACCESS_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_access_params_cmd(ar->arWmi, cmd.ac, cmd.txop, cmd.eCWmin, cmd.eCWmax,
+                                  cmd.aifsn) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_DISC_TIMEOUT_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_VOICE_PKT_SIZE_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_MAX_SP_LEN_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+
+static int
+ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_BT_STATUS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_SET_BT_PARAMS_CMD cmd;
+    int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+        return -EFAULT;
+    }
+
+    if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+    return (ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_fe_ant_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_FE_ANT_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(struct net_device * dev,  char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_btinquiry_page_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_sco_config_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_SCO_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_sco_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_a2dp_config_cmd(struct net_device * dev,
+														char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_A2DP_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_a2dp_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_aclcoex_config_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_aclcoex_config_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar60000_xioctl_set_btcoex_debug_cmd(struct net_device * dev, char * userdata)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+	WMI_SET_BTCOEX_DEBUG_CMD cmd;
+    int ret = 0;
+
+	if (ar->arWmiReady == FALSE) {
+		return -EIO;
+	}
+
+	if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+		return -EFAULT;
+	}
+
+    if (wmi_set_btcoex_debug_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+
+	return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_bt_operating_status_cmd(struct net_device * dev, char * userdata)
+{
+     AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+     WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD cmd;
+     int ret = 0;
+
+    if (ar->arWmiReady == FALSE) {
+	return -EIO;
+    }
+
+    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+	return -EFAULT;
+    }
+
+    if (wmi_set_btcoex_bt_operating_status_cmd(ar->arWmi, &cmd) == A_OK)
+    {
+        ret = 0;
+    } else {
+        ret = -EINVAL;
+    }
+    return(ret);
+}
+
+static int
+ar6000_xioctl_get_btcoex_config_cmd(struct net_device * dev, char * userdata,
+											struct ifreq *rq)
+{
+
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    AR6000_BTCOEX_CONFIG btcoexConfig;
+    WMI_BTCOEX_CONFIG_EVENT *pbtcoexConfigEv = &ar->arBtcoexConfig;
+
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+            return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+            return -EIO;
+    }
+	if (copy_from_user(&btcoexConfig.configCmd, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+		return -EFAULT;
+	}
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (wmi_get_btcoex_config_cmd(ar->arWmi, (WMI_GET_BTCOEX_CONFIG_CMD *)&btcoexConfig.configCmd) != A_OK)
+    {
+    	up(&ar->arSem);
+    	return -EIO;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+       ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(btcoexConfig.configEvent, pbtcoexConfigEv, sizeof(WMI_BTCOEX_CONFIG_EVENT))) {
+            ret = -EFAULT;
+    }
+    up(&ar->arSem);
+    return ret;
+}
+
+static int
+ar6000_xioctl_get_btcoex_stats_cmd(struct net_device * dev, char * userdata, struct ifreq *rq)
+{
+	AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    AR6000_BTCOEX_STATS btcoexStats;
+    WMI_BTCOEX_STATS_EVENT *pbtcoexStats = &ar->arBtcoexStats;
+    int ret = 0;
+
+    if (ar->bIsDestroyProgress) {
+            return -EBUSY;
+    }
+    if (ar->arWmiReady == FALSE) {
+            return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+	if (copy_from_user(&btcoexStats.statsEvent, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+		return -EFAULT;
+	}
+
+    if (wmi_get_btcoex_stats_cmd(ar->arWmi) != A_OK)
+    {
+    	up(&ar->arSem);
+    	return -EIO;
+    }
+
+    ar->statsUpdatePending = TRUE;
+
+    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+       ret = -EINTR;
+    }
+
+    if (!ret && copy_to_user(btcoexStats.statsEvent, pbtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT))) {
+            ret = -EFAULT;
+    }
+
+
+    up(&ar->arSem);
+
+	return(ret);
+}
+
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+struct ar6000_gpio_intr_wait_cmd_s  gpio_intr_results;
+/* gpio_reg_results and gpio_data_available are protected by arSem */
+static struct ar6000_gpio_register_cmd_s gpio_reg_results;
+static A_BOOL gpio_data_available; /* Requested GPIO data available */
+static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
+static A_BOOL gpio_ack_received;   /* GPIO ack was received */
+
+/* Host-side initialization for General Purpose I/O support */
+void ar6000_gpio_init(void)
+{
+    gpio_intr_available = FALSE;
+    gpio_data_available = FALSE;
+    gpio_ack_received   = FALSE;
+}
+
+/*
+ * Called when a GPIO interrupt is received from the Target.
+ * intr_values shows which GPIO pins have interrupted.
+ * input_values shows a recent value of GPIO pins.
+ */
+void
+ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
+{
+    gpio_intr_results.intr_mask = intr_mask;
+    gpio_intr_results.input_values = input_values;
+    *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
+    wake_up(&arEvent);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
+ * call.
+ */
+void
+ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
+{
+    gpio_reg_results.gpioreg_id = reg_id;
+    gpio_reg_results.value = value;
+    *((volatile A_BOOL *)&gpio_data_available) = TRUE;
+    wake_up(&arEvent);
+}
+
+/*
+ * This is called when an acknowledgement is received from the Target
+ * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
+ * call.
+ */
+void
+ar6000_gpio_ack_rx(void)
+{
+    gpio_ack_received = TRUE;
+    wake_up(&arEvent);
+}
+
+A_STATUS
+ar6000_gpio_output_set(struct net_device *dev,
+                       A_UINT32 set_mask,
+                       A_UINT32 clear_mask,
+                       A_UINT32 enable_mask,
+                       A_UINT32 disable_mask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_ack_received = FALSE;
+    return wmi_gpio_output_set(ar->arWmi,
+                set_mask, clear_mask, enable_mask, disable_mask);
+}
+
+static A_STATUS
+ar6000_gpio_input_get(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+    return wmi_gpio_input_get(ar->arWmi);
+}
+
+static A_STATUS
+ar6000_gpio_register_set(struct net_device *dev,
+                         A_UINT32 gpioreg_id,
+                         A_UINT32 value)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_ack_received = FALSE;
+    return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
+}
+
+static A_STATUS
+ar6000_gpio_register_get(struct net_device *dev,
+                         A_UINT32 gpioreg_id)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+    return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
+}
+
+static A_STATUS
+ar6000_gpio_intr_ack(struct net_device *dev,
+                     A_UINT32 ack_mask)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    gpio_intr_available = FALSE;
+    return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static struct prof_count_s prof_count_results;
+static A_BOOL prof_count_available; /* Requested GPIO data available */
+
+static A_STATUS
+prof_count_get(struct net_device *dev)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    *((volatile A_BOOL *)&prof_count_available) = FALSE;
+    return wmi_prof_count_get_cmd(ar->arWmi);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous prof_count_get call.
+ */
+void
+prof_count_rx(A_UINT32 addr, A_UINT32 count)
+{
+    prof_count_results.addr = addr;
+    prof_count_results.count = count;
+    *((volatile A_BOOL *)&prof_count_available) = TRUE;
+    wake_up(&arEvent);
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+
+static A_STATUS
+ar6000_create_acl_data_osbuf(struct net_device *dev, A_UINT8 *userdata, void **p_osbuf)
+{
+    void *osbuf = NULL;
+    A_UINT8 tmp_space[8];
+    HCI_ACL_DATA_PKT *acl;
+    A_UINT8 hdr_size, *datap=NULL;
+    A_STATUS ret = A_OK;
+
+    /* ACL is in data path. There is a need to create pool
+     * mechanism for allocating and freeing NETBUFs - ToDo later.
+     */
+
+    *p_osbuf = NULL;
+    acl = (HCI_ACL_DATA_PKT *)tmp_space;
+    hdr_size = sizeof(acl->hdl_and_flags) + sizeof(acl->data_len);
+
+    do {
+        if (a_copy_from_user(acl, userdata, hdr_size)) {
+            ret = A_EFAULT;
+            break;
+        }
+
+        osbuf = A_NETBUF_ALLOC(hdr_size + acl->data_len);
+        if (osbuf == NULL) {
+           ret = A_NO_MEMORY;
+           break;
+        }
+        A_NETBUF_PUT(osbuf, hdr_size + acl->data_len);
+        datap = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+
+        /* Real copy to osbuf */
+        acl = (HCI_ACL_DATA_PKT *)(datap);
+        A_MEMCPY(acl, tmp_space, hdr_size);
+        if (a_copy_from_user(acl->data, userdata + hdr_size, acl->data_len)) {
+            ret = A_EFAULT;
+            break;
+        }
+    } while(FALSE);
+
+    if (ret == A_OK) {
+        *p_osbuf = osbuf;
+    } else {
+        A_NETBUF_FREE(osbuf);
+    }
+    return ret;
+}
+
+
+
+int
+ar6000_ioctl_ap_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+    int ret=0;
+
+    switch(param) {
+        case IEEE80211_PARAM_WPA:
+            switch (value) {
+                case WPA_MODE_WPA1:
+                    ar->arAuthMode = WPA_AUTH;
+                    break;
+                case WPA_MODE_WPA2:
+                    ar->arAuthMode = WPA2_AUTH;
+                    break;
+                case WPA_MODE_AUTO:
+                    ar->arAuthMode = WPA_AUTH | WPA2_AUTH;
+                    break;
+                case WPA_MODE_NONE:
+                    ar->arAuthMode = NONE_AUTH;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_AUTHMODE:
+            if(value == IEEE80211_AUTH_WPA_PSK) {
+                if (WPA_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH;
+                } else if (WPA2_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA2_PSK_AUTH;
+                } else if ((WPA_AUTH | WPA2_AUTH) == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH | WPA2_PSK_AUTH;
+                } else {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error -  Setting PSK "\
+                        "mode when WPA param was set to %d\n",
+                        ar->arAuthMode));
+                    ret = -EIO;
+                }
+            }
+            break;
+        case IEEE80211_PARAM_UCASTCIPHER:
+            ar->arPairwiseCrypto = 0;
+            if(value & (1<<IEEE80211_CIPHER_AES_CCM)) {
+                ar->arPairwiseCrypto |= AES_CRYPT;
+            }
+            if(value & (1<<IEEE80211_CIPHER_TKIP)) {
+                ar->arPairwiseCrypto |= TKIP_CRYPT;
+            }
+            if(!ar->arPairwiseCrypto) {
+                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+                           ("Error - Invalid cipher in WPA \n"));
+                ret = -EIO;
+            }
+            break;
+        case IEEE80211_PARAM_PRIVACY:
+            if(value == 0) {
+                ar->arDot11AuthMode      = OPEN_AUTH;
+                ar->arAuthMode           = NONE_AUTH;
+                ar->arPairwiseCrypto     = NONE_CRYPT;
+                ar->arPairwiseCryptoLen  = 0;
+                ar->arGroupCrypto        = NONE_CRYPT;
+                ar->arGroupCryptoLen     = 0;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IEEE80211_PARAM_WAPI:
+            A_PRINTF("WAPI Policy: %d\n", value);
+            ar->arDot11AuthMode      = OPEN_AUTH;
+            ar->arAuthMode           = NONE_AUTH;
+            if(value & 0x1) {
+                ar->arPairwiseCrypto     = WAPI_CRYPT;
+                ar->arGroupCrypto        = WAPI_CRYPT;
+            } else {
+                ar->arPairwiseCrypto     = NONE_CRYPT;
+                ar->arGroupCrypto        = NONE_CRYPT;
+            }
+            break;
+#endif
+    }
+    return ret;
+}
+
+int
+ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+    A_BOOL profChanged = FALSE;
+    int ret=0;
+
+    if(ar->arNextMode == AP_NETWORK) {
+        ar->ap_profile_flag = 1; /* There is a change in profile */
+        switch (param) {
+            case IEEE80211_PARAM_WPA:
+            case IEEE80211_PARAM_AUTHMODE:
+            case IEEE80211_PARAM_UCASTCIPHER:
+            case IEEE80211_PARAM_PRIVACY:
+            case IEEE80211_PARAM_WAPI:
+                ret = ar6000_ioctl_ap_setparam(ar, param, value);
+                return ret;
+        }
+    }
+
+    switch (param) {
+        case IEEE80211_PARAM_WPA:
+            switch (value) {
+                case WPA_MODE_WPA1:
+                    ar->arAuthMode = WPA_AUTH;
+                    profChanged    = TRUE;
+                    break;
+                case WPA_MODE_WPA2:
+                    ar->arAuthMode = WPA2_AUTH;
+                    profChanged    = TRUE;
+                    break;
+                case WPA_MODE_NONE:
+                    ar->arAuthMode = NONE_AUTH;
+                    profChanged    = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_AUTHMODE:
+            switch(value) {
+                case IEEE80211_AUTH_WPA_PSK:
+                    if (WPA_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA_PSK_AUTH;
+                        profChanged    = TRUE;
+                    } else if (WPA2_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA2_PSK_AUTH;
+                        profChanged    = TRUE;
+                    } else {
+                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error -  Setting PSK "\
+                            "mode when WPA param was set to %d\n",
+                            ar->arAuthMode));
+                        ret = -EIO;
+                    }
+                    break;
+                case IEEE80211_AUTH_WPA_CCKM:
+                    if (WPA2_AUTH == ar->arAuthMode) {
+                        ar->arAuthMode = WPA2_AUTH_CCKM;
+                    } else {
+                        ar->arAuthMode = WPA_AUTH_CCKM;
+                    }
+                    break;
+                default:
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_UCASTCIPHER:
+            switch (value) {
+                case IEEE80211_CIPHER_AES_CCM:
+                    ar->arPairwiseCrypto = AES_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_TKIP:
+                    ar->arPairwiseCrypto = TKIP_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_WEP:
+                    ar->arPairwiseCrypto = WEP_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+                case IEEE80211_CIPHER_NONE:
+                    ar->arPairwiseCrypto = NONE_CRYPT;
+                    profChanged          = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_UCASTKEYLEN:
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+                ret = -EIO;
+            } else {
+                ar->arPairwiseCryptoLen = value;
+            }
+            break;
+        case IEEE80211_PARAM_MCASTCIPHER:
+            switch (value) {
+                case IEEE80211_CIPHER_AES_CCM:
+                    ar->arGroupCrypto = AES_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_TKIP:
+                    ar->arGroupCrypto = TKIP_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_WEP:
+                    ar->arGroupCrypto = WEP_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+                case IEEE80211_CIPHER_NONE:
+                    ar->arGroupCrypto = NONE_CRYPT;
+                    profChanged       = TRUE;
+                    break;
+            }
+            break;
+        case IEEE80211_PARAM_MCASTKEYLEN:
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+                ret = -EIO;
+            } else {
+                ar->arGroupCryptoLen = value;
+            }
+            break;
+        case IEEE80211_PARAM_COUNTERMEASURES:
+            if (ar->arWmiReady == FALSE) {
+                return -EIO;
+            }
+            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+            break;
+        default:
+            break;
+    }
+    if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) {
+        /*
+         * profile has changed.  Erase ssid to signal change
+         */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+    }
+
+    return ret;
+}
+
+int
+ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik)
+{
+    KEY_USAGE keyUsage;
+    A_STATUS status;
+    CRYPTO_TYPE keyType = NONE_CRYPT;
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = FALSE;
+#endif
+    if ( (0 == memcmp(ik->ik_macaddr, null_mac, IEEE80211_ADDR_LEN)) ||
+         (0 == memcmp(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN)) ) {
+        keyUsage = GROUP_USAGE;
+        if(ar->arNextMode == AP_NETWORK) {
+            A_MEMCPY(&ar->ap_mode_bkey, ik,
+                     sizeof(struct ieee80211req_key));
+#ifdef WAPI_ENABLE
+            if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                return ap_set_wapi_key(ar, ik);
+            }
+#endif
+        }
+#ifdef USER_KEYS
+        A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
+                 sizeof(struct ieee80211req_key));
+#endif
+    } else {
+        keyUsage = PAIRWISE_USAGE;
+#ifdef USER_KEYS
+        A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
+                 sizeof(struct ieee80211req_key));
+#endif
+#ifdef WAPI_ENABLE
+        if(ar->arNextMode == AP_NETWORK) {
+            if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+                return ap_set_wapi_key(ar, ik);
+            }
+        }
+#endif
+    }
+
+    switch (ik->ik_type) {
+        case IEEE80211_CIPHER_WEP:
+            keyType = WEP_CRYPT;
+            break;
+        case IEEE80211_CIPHER_TKIP:
+            keyType = TKIP_CRYPT;
+            break;
+        case IEEE80211_CIPHER_AES_CCM:
+            keyType = AES_CRYPT;
+            break;
+        default:
+            break;
+    }
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyType = keyType;
+#endif
+    if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
+        if (NONE_CRYPT == keyType) {
+            return -EIO;
+        }
+
+        if (WEP_CRYPT == keyType) {
+             int index = ik->ik_keyix;
+
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(ik->ik_keylen)) {
+                return -EIO;
+            }
+
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                            sizeof(ar->arWepKeyList[index].arKey));
+            A_MEMCPY(ar->arWepKeyList[index].arKey, ik->ik_keydata, ik->ik_keylen);
+            ar->arWepKeyList[index].arKeyLen = ik->ik_keylen;
+
+            if(ik->ik_flags & IEEE80211_KEY_DEFAULT){
+                ar->arDefTxKeyIndex = index;
+            }
+
+            return 0;
+        }
+
+        if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+            (GROUP_USAGE & keyUsage))
+        {
+            A_UNTIMEOUT(&ar->disconnect_timer);
+        }
+
+        status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
+                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+                                ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+                                SYNC_BOTH_WMIFLAG);
+
+        if (status != A_OK) {
+            return -EIO;
+        }
+    } else {
+        status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
+    }
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = TRUE;
+#endif
+
+    return 0;
+}
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    HIF_DEVICE *hifDevice = ar->arHifDevice;
+    int ret = 0, param;
+    unsigned int address = 0;
+    unsigned int length = 0;
+    unsigned char *buffer;
+    char *userdata;
+    A_UINT32 connectCtrlFlags;
+
+
+    WMI_SET_AKMP_PARAMS_CMD  akmpParams;
+    WMI_SET_PMKID_LIST_CMD   pmkidInfo;
+
+    WMI_SET_HT_CAP_CMD htCap;
+    WMI_SET_HT_OP_CMD htOp;
+
+    /*
+     * ioctl operations may have to wait for the Target, so we cannot hold rtnl.
+     * Prevent the device from disappearing under us and release the lock during
+     * the ioctl operation.
+     */
+    dev_hold(dev);
+    rtnl_unlock();
+
+    if (cmd == AR6000_IOCTL_EXTENDED) {
+        /*
+         * This allows for many more wireless ioctls than would otherwise
+         * be available.  Applications embed the actual ioctl command in
+         * the first word of the parameter block, and use the command
+         * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
+         */
+        get_user(cmd, (int *)rq->ifr_data);
+        userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
+        if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) {
+            A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd);
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+    }
+    } else {
+        A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd);
+        if(ret == A_ENOTSUP) {
+            A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd);
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+        } else if (ret == A_ERROR) {
+            /* It is not our ioctl (out of range ioctl) */
+            ret = -EOPNOTSUPP;
+            goto ioctl_done;
+        }
+        userdata = (char *)rq->ifr_data;
+    }
+
+    if ((ar->arWlanState == WLAN_DISABLED) &&
+        ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
+         (cmd != AR6000_XIOCTL_DIAG_READ) &&
+         (cmd != AR6000_XIOCTL_DIAG_WRITE)))
+    {
+        ret = -EIO;
+        goto ioctl_done;
+    }
+
+    ret = 0;
+    switch(cmd)
+    {
+        case IEEE80211_IOCTL_SETPARAM:
+        {
+            int param, value;
+            int *ptr = (int *)rq->ifr_ifru.ifru_newname;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                param = *ptr++;
+                value = *ptr;
+                ret = ar6000_ioctl_setparam(ar,param,value);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_SETKEY:
+        {
+            struct ieee80211req_key keydata;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&keydata, userdata,
+                            sizeof(struct ieee80211req_key))) {
+                ret = -EFAULT;
+            } else {
+                ar6000_ioctl_setkey(ar, &keydata);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_DELKEY:
+        case IEEE80211_IOCTL_SETOPTIE:
+        {
+            //ret = -EIO;
+            break;
+        }
+        case IEEE80211_IOCTL_SETMLME:
+        {
+            struct ieee80211req_mlme mlme;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&mlme, userdata,
+                            sizeof(struct ieee80211req_mlme))) {
+                ret = -EFAULT;
+            } else {
+                switch (mlme.im_op) {
+                    case IEEE80211_MLME_AUTHORIZE:
+                        A_PRINTF("setmlme AUTHORIZE %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        break;
+                    case IEEE80211_MLME_UNAUTHORIZE:
+                        A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        break;
+                    case IEEE80211_MLME_DEAUTH:
+                        A_PRINTF("setmlme DEAUTH %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        //remove_sta(ar, mlme.im_macaddr);
+                        break;
+                    case IEEE80211_MLME_DISASSOC:
+                        A_PRINTF("setmlme DISASSOC %02X:%02X\n",
+                            mlme.im_macaddr[4], mlme.im_macaddr[5]);
+                        //remove_sta(ar, mlme.im_macaddr);
+                        break;
+                    default:
+                        ret = 0;
+                        goto ioctl_done;
+                }
+
+                wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr,
+                                mlme.im_reason);
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_ADDPMKID:
+        {
+            struct ieee80211req_addpmkid  req;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) {
+                ret = -EFAULT;
+            } else {
+                A_STATUS status;
+
+                AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
+                    req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2],
+                    req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5],
+                    req.pi_enable));
+
+                status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid,
+                              req.pi_enable);
+
+                if (status != A_OK) {
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+            }
+            break;
+        }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+        case AR6000_XIOCTL_TCMD_CONT_TX:
+            {
+                TCMD_CONT_TX txCmd;
+
+                if (ar->tcmdPm == TCMD_PM_SLEEP) {
+                    A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+
+                if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                } else {
+                    wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
+                }
+            }
+            break;
+        case AR6000_XIOCTL_TCMD_CONT_RX:
+            {
+                TCMD_CONT_RX rxCmd;
+
+                if (ar->tcmdPm == TCMD_PM_SLEEP) {
+                    A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+
+                switch(rxCmd.act)
+                {
+                    case TCMD_CONT_RX_PROMIS:
+                    case TCMD_CONT_RX_FILTER:
+                    case TCMD_CONT_RX_SETMAC:
+                    case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE:
+                         wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
+                                                sizeof(TCMD_CONT_RX));
+                         tcmdRxFreq = rxCmd.u.para.freq;
+                         break;
+                    case TCMD_CONT_RX_REPORT:
+                         ar6000_ioctl_tcmd_get_rx_report(dev, rq,
+                         (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
+                         break;
+                    default:
+                         A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
+                         ret = -EINVAL;
+                         goto ioctl_done;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_TCMD_PM:
+            {
+                TCMD_PM pmCmd;
+
+                if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                ar->tcmdPm = pmCmd.mode;
+                wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
+            }
+            break;
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+        case AR6000_XIOCTL_BMI_DONE:
+            if(bmienable)
+            {
+                rtnl_lock(); /* ar6000_init expects to be called holding rtnl lock */
+                ret = ar6000_init(dev);
+                rtnl_unlock();
+            }
+            else
+            {
+                ret = BMIDone(hifDevice);
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_READ_MEMORY:
+            get_user(address, (unsigned int *)userdata);
+            get_user(length, (unsigned int *)userdata + 1);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Read Memory (address: 0x%x, length: %d)\n",
+                             address, length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                ret = BMIReadMemory(hifDevice, address, buffer, length);
+                if (copy_to_user(rq->ifr_data, buffer, length)) {
+                    ret = -EFAULT;
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_WRITE_MEMORY:
+            get_user(address, (unsigned int *)userdata);
+            get_user(length, (unsigned int *)userdata + 1);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Write Memory (address: 0x%x, length: %d)\n",
+                             address, length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(address) +
+                                   sizeof(length)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    ret = BMIWriteMemory(hifDevice, address, buffer, length);
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+        case AR6000_XIOCTL_BMI_TEST:
+           AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("No longer supported\n"));
+           ret = -EOPNOTSUPP;
+           break;
+
+        case AR6000_XIOCTL_BMI_EXECUTE:
+            get_user(address, (unsigned int *)userdata);
+            get_user(param, (unsigned int *)userdata + 1);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Execute (address: 0x%x, param: %d)\n",
+                             address, param));
+            ret = BMIExecute(hifDevice, address, (A_UINT32*)&param);
+            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+            break;
+
+        case AR6000_XIOCTL_BMI_SET_APP_START:
+            get_user(address, (unsigned int *)userdata);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Set App Start (address: 0x%x)\n", address));
+            ret = BMISetAppStart(hifDevice, address);
+            break;
+
+        case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
+            get_user(address, (unsigned int *)userdata);
+            ret = BMIReadSOCRegister(hifDevice, address, (A_UINT32*)&param);
+            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+            break;
+
+        case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
+            get_user(address, (unsigned int *)userdata);
+            get_user(param, (unsigned int *)userdata + 1);
+            ret = BMIWriteSOCRegister(hifDevice, address, param);
+            break;
+
+#ifdef HTC_RAW_INTERFACE
+        case AR6000_XIOCTL_HTC_RAW_OPEN:
+            ret = A_OK;
+            if (!arRawIfEnabled(ar)) {
+                /* make sure block size is set in case the target was reset since last
+                  * BMI phase (i.e. flashup downloads) */
+                ret = ar6000_set_htc_params(ar->arHifDevice,
+                                            ar->arTargetType,
+                                            0,  /* use default yield */
+                                            0   /* use default number of HTC ctrl buffers */
+                                            );
+                if (A_FAILED(ret)) {
+                    break;
+                }
+                /* Terminate the BMI phase */
+                ret = BMIDone(hifDevice);
+                if (ret == A_OK) {
+                    ret = ar6000_htc_raw_open(ar);
+                }
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_CLOSE:
+            if (arRawIfEnabled(ar)) {
+                ret = ar6000_htc_raw_close(ar);
+                arRawIfEnabled(ar) = FALSE;
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_READ:
+            if (arRawIfEnabled(ar)) {
+                unsigned int streamID;
+                get_user(streamID, (unsigned int *)userdata);
+                get_user(length, (unsigned int *)userdata + 1);
+                buffer = rq->ifr_data + sizeof(length);
+                ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
+                                          buffer, length);
+                put_user(ret, (unsigned int *)rq->ifr_data);
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+
+        case AR6000_XIOCTL_HTC_RAW_WRITE:
+            if (arRawIfEnabled(ar)) {
+                unsigned int streamID;
+                get_user(streamID, (unsigned int *)userdata);
+                get_user(length, (unsigned int *)userdata + 1);
+                buffer = userdata + sizeof(streamID) + sizeof(length);
+                ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
+                                           buffer, length);
+                put_user(ret, (unsigned int *)rq->ifr_data);
+            } else {
+                ret = A_ERROR;
+            }
+            break;
+#endif /* HTC_RAW_INTERFACE */
+
+        case AR6000_XIOCTL_BMI_LZ_STREAM_START:
+            get_user(address, (unsigned int *)userdata);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Start Compressed Stream (address: 0x%x)\n", address));
+            ret = BMILZStreamStart(hifDevice, address);
+            break;
+
+        case AR6000_XIOCTL_BMI_LZ_DATA:
+            get_user(length, (unsigned int *)userdata);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Send Compressed Data (length: %d)\n", length));
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(length)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    ret = BMILZData(hifDevice, buffer, length);
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+            break;
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+        /*
+         * Optional support for Target-side profiling.
+         * Not needed in production.
+         */
+
+        /* Configure Target-side profiling */
+        case AR6000_XIOCTL_PROF_CFG:
+        {
+            A_UINT32 period;
+            A_UINT32 nbins;
+            get_user(period, (unsigned int *)userdata);
+            get_user(nbins, (unsigned int *)userdata + 1);
+
+            if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) {
+                ret = -EIO;
+            }
+
+            break;
+        }
+
+        /* Start a profiling bucket/bin at the specified address */
+        case AR6000_XIOCTL_PROF_ADDR_SET:
+        {
+            A_UINT32 addr;
+            get_user(addr, (unsigned int *)userdata);
+
+            if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) {
+                ret = -EIO;
+            }
+
+            break;
+        }
+
+        /* START Target-side profiling */
+        case AR6000_XIOCTL_PROF_START:
+            wmi_prof_start_cmd(ar->arWmi);
+            break;
+
+        /* STOP Target-side profiling */
+        case AR6000_XIOCTL_PROF_STOP:
+            wmi_prof_stop_cmd(ar->arWmi);
+            break;
+        case AR6000_XIOCTL_PROF_COUNT_GET:
+        {
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            prof_count_available = FALSE;
+            ret = prof_count_get(dev);
+            if (ret != A_OK) {
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            /* Wait for Target to respond. */
+            wait_event_interruptible(arEvent, prof_count_available);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                if (copy_to_user(userdata, &prof_count_results,
+                                 sizeof(prof_count_results)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+        case AR6000_IOCTL_WMI_GETREV:
+        {
+            if (copy_to_user(rq->ifr_data, &ar->arVersion,
+                             sizeof(ar->arVersion)))
+            {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETPWR:
+        {
+            WMI_POWER_MODE_CMD pwrModeCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&pwrModeCmd, userdata,
+                                   sizeof(pwrModeCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
+                       != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
+        {
+            WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&ibssPmCaps, userdata,
+                                   sizeof(ibssPmCaps)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
+                    ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
+                {
+                    ret = -EIO;
+                }
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                ar->arIbssPsEnable = ibssPmCaps.power_saving;
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_AP_PS:
+        {
+            WMI_AP_PS_CMD apPsCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&apPsCmd, userdata,
+                                   sizeof(apPsCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_apps_cmd(ar->arWmi, apPsCmd.psType, apPsCmd.idle_time,
+                    apPsCmd.ps_period, apPsCmd.sleep_period) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_PMPARAMS:
+        {
+            WMI_POWER_PARAMS_CMD pmParams;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&pmParams, userdata,
+                                      sizeof(pmParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
+                                     pmParams.pspoll_number,
+                                     pmParams.dtim_policy,
+                                     pmParams.tx_wakeup_policy,
+                                     pmParams.num_tx_to_wakeup,
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+                                     IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 
+#else
+                                     SEND_POWER_SAVE_FAIL_EVENT_ALWAYS
+#endif
+                                     ) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETSCAN:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&ar->scParams, userdata,
+                                      sizeof(ar->scParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (CAN_SCAN_IN_CONNECT(ar->scParams.scanCtrlFlags)) {
+                    ar->arSkipScan = FALSE;
+                } else {
+                    ar->arSkipScan = TRUE;
+                }
+
+                if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
+                                       ar->scParams.fg_end_period,
+                                       ar->scParams.bg_period,
+                                       ar->scParams.minact_chdwell_time,
+                                       ar->scParams.maxact_chdwell_time,
+                                       ar->scParams.pas_chdwell_time,
+                                       ar->scParams.shortScanRatio,
+                                       ar->scParams.scanCtrlFlags,
+                                       ar->scParams.max_dfsch_act_time,
+                                       ar->scParams.maxact_scan_per_ssid) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETLISTENINT:
+        {
+            WMI_LISTEN_INT_CMD listenCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&listenCmd, userdata,
+                                      sizeof(listenCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                    if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
+                        ret = -EIO;
+                    } else {
+                        AR6000_SPIN_LOCK(&ar->arLock, 0);
+                        ar->arListenInterval = param;
+                        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+                    }
+
+                }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_BMISS_TIME:
+        {
+            WMI_BMISS_TIME_CMD bmissCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bmissCmd, userdata,
+                                      sizeof(bmissCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SETBSSFILTER:
+        {
+            WMI_BSS_FILTER_CMD filt;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&filt, userdata,
+                                   sizeof(filt)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask)
+                        != A_OK) {
+                    ret = -EIO;
+                } else {
+                    ar->arUserBssFilter = param;
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_snr_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_CLR_RSSISNR:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            ret = wmi_clr_rssi_snr(ar->arWmi);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
+        {
+            ret = ar6000_ioctl_set_lq_threshold(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
+        {
+            WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setLpreambleCmd, userdata,
+                                   sizeof(setLpreambleCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status,
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 
+                           WMI_DONOT_IGNORE_BARKER_IN_ERP
+#else
+                           WMI_IGNORE_BARKER_IN_ERP
+#endif
+                ) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_RTS:
+        {
+            WMI_SET_RTS_CMD rtsCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&rtsCmd, userdata,
+                                   sizeof(rtsCmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ar->arRTS = rtsCmd.threshold;
+                if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
+                       != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WMM:
+        {
+            ret = ar6000_ioctl_set_wmm(dev, rq);
+            break;
+        }
+       case AR6000_XIOCTL_WMI_SET_QOS_SUPP:
+        {
+            ret = ar6000_ioctl_set_qos_supp(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_TXOP:
+        {
+            ret = ar6000_ioctl_set_txop(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_RD:
+        {
+            ret = ar6000_ioctl_get_rd(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
+        {
+            ret = ar6000_ioctl_set_channelParams(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_PROBEDSSID:
+        {
+            ret = ar6000_ioctl_set_probedSsid(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_BADAP:
+        {
+            ret = ar6000_ioctl_set_badAp(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_CREATE_QOS:
+        {
+            ret = ar6000_ioctl_create_qos(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_DELETE_QOS:
+        {
+            ret = ar6000_ioctl_delete_qos(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
+        {
+            ret = ar6000_ioctl_get_qos_queue(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_GET_TARGET_STATS:
+        {
+            ret = ar6000_ioctl_get_target_stats(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
+        {
+            ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
+        {
+            WMI_SET_ASSOC_INFO_CMD cmd;
+            A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                get_user(cmd.ieType, userdata);
+                if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
+                    ret = -EIO;
+                } else {
+                    get_user(cmd.bufferSize, userdata + 1);
+                    if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
+                        ret = -EFAULT;
+                        break;
+                    }
+                    if (copy_from_user(assocInfo, userdata + 2,
+                                       cmd.bufferSize))
+                    {
+                        ret = -EFAULT;
+                    } else {
+                        if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
+                                                 cmd.bufferSize,
+                                                 assocInfo) != A_OK)
+                        {
+                            ret = -EIO;
+                        }
+                    }
+                }
+            }
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
+        {
+            ret = ar6000_ioctl_set_access_params(dev, rq);
+            break;
+        }
+        case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
+        {
+            ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_FORCE_TARGET_RESET:
+        {
+            if (ar->arHtcTarget)
+            {
+//                HTCForceReset(htcTarget);
+            }
+            else
+            {
+                AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("ar6000_ioctl cannot attempt reset.\n"));
+            }
+            break;
+        }
+        case AR6000_XIOCTL_TARGET_INFO:
+        case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
+        {
+            /* If we made it to here, then the Target exists and is ready. */
+
+            if (cmd == AR6000_XIOCTL_TARGET_INFO) {
+                if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
+                                 sizeof(ar->arVersion.target_ver)))
+                {
+                    ret = -EFAULT;
+                }
+                if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
+                                 sizeof(ar->arTargetType)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
+        {
+            WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
+
+            if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
+            {
+                ret = -EFAULT;
+            } else {
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                /* Start a cyclic timer with the parameters provided. */
+                if (hbparam.frequency) {
+                    ar->arHBChallengeResp.frequency = hbparam.frequency;
+                }
+                if (hbparam.threshold) {
+                    ar->arHBChallengeResp.missThres = hbparam.threshold;
+                }
+
+                /* Delete the pending timer and start a new one */
+                if (timer_pending(&ar->arHBChallengeResp.timer)) {
+                    A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+                }
+                A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
+        {
+            A_UINT32 cookie;
+
+            if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            /* Send the challenge on the control channel */
+            if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+#ifdef USER_KEYS
+        case AR6000_XIOCTL_USER_SETKEYS:
+        {
+
+            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
+
+            if (copy_from_user(&ar->user_key_ctrl, userdata,
+                               sizeof(ar->user_key_ctrl)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
+            break;
+        }
+#endif /* USER_KEYS */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+        case AR6000_XIOCTL_GPIO_OUTPUT_SET:
+        {
+            struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_output_set_cmd, userdata,
+                                sizeof(gpio_output_set_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_output_set(dev,
+                                             gpio_output_set_cmd.set_mask,
+                                             gpio_output_set_cmd.clear_mask,
+                                             gpio_output_set_cmd.enable_mask,
+                                             gpio_output_set_cmd.disable_mask);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INPUT_GET:
+        {
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            ret = ar6000_gpio_input_get(dev);
+            if (ret != A_OK) {
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            /* Wait for Target to respond. */
+            wait_event_interruptible(arEvent, gpio_data_available);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
+
+                if (copy_to_user(userdata, &gpio_reg_results.value,
+                                 sizeof(gpio_reg_results.value)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_REGISTER_SET:
+        {
+            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_register_cmd, userdata,
+                                sizeof(gpio_register_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_register_set(dev,
+                                               gpio_register_cmd.gpioreg_id,
+                                               gpio_register_cmd.value);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+
+                /* Wait for acknowledgement from Target */
+                wait_event_interruptible(arEvent, gpio_ack_received);
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_REGISTER_GET:
+        {
+            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_register_cmd, userdata,
+                                sizeof(gpio_register_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
+                if (ret != A_OK) {
+                    up(&ar->arSem);
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+
+                /* Wait for Target to respond. */
+                wait_event_interruptible(arEvent, gpio_data_available);
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                } else {
+                    A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
+                    if (copy_to_user(userdata, &gpio_reg_results,
+                                     sizeof(gpio_reg_results)))
+                    {
+                        ret = -EFAULT;
+                    }
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INTR_ACK:
+        {
+            struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+
+            if (copy_from_user(&gpio_intr_ack_cmd, userdata,
+                                sizeof(gpio_intr_ack_cmd)))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
+                if (ret != A_OK) {
+                    ret = EIO;
+                }
+            }
+            up(&ar->arSem);
+            break;
+        }
+        case AR6000_XIOCTL_GPIO_INTR_WAIT:
+        {
+            /* Wait for Target to report an interrupt. */
+            wait_event_interruptible(arEvent, gpio_intr_available);
+
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            } else {
+                if (copy_to_user(userdata, &gpio_intr_results,
+                                 sizeof(gpio_intr_results)))
+                {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+        case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
+        {
+            struct ar6000_dbglog_module_config_s config;
+
+            if (copy_from_user(&config, userdata, sizeof(config))) {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+
+            /* Send the challenge on the control channel */
+            if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
+                                            config.tsr, config.rep,
+                                            config.size, config.valid) != A_OK)
+            {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
+        {
+            /* Send the challenge on the control channel */
+            if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
+            {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_ADHOC_BSSID:
+        {
+            WMI_SET_ADHOC_BSSID_CMD adhocBssid;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&adhocBssid, userdata,
+                                      sizeof(adhocBssid)))
+            {
+                ret = -EFAULT;
+            } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
+                                AR6000_ETH_ADDR_LEN) == 0)
+            {
+                ret = -EFAULT;
+            } else {
+
+                A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
+        }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_OPT_MODE:
+        {
+        WMI_SET_OPT_MODE_CMD optModeCmd;
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&optModeCmd, userdata,
+                                      sizeof(optModeCmd)))
+            {
+                ret = -EFAULT;
+            } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
+                ret = -EFAULT;
+
+            } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
+                       != A_OK)
+            {
+                ret = -EIO;
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_OPT_SEND_FRAME:
+        {
+        WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
+            A_UINT8 data[MAX_OPT_DATA_LEN];
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&optTxFrmCmd, userdata,
+                                      sizeof(optTxFrmCmd)))
+            {
+                ret = -EFAULT;
+            } else if (copy_from_user(data,
+                                      userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
+                                      optTxFrmCmd.optIEDataLen))
+            {
+                ret = -EFAULT;
+            } else {
+                ret = wmi_opt_tx_frame_cmd(ar->arWmi,
+                                           optTxFrmCmd.frmType,
+                                           optTxFrmCmd.dstAddr,
+                                           optTxFrmCmd.bssid,
+                                           optTxFrmCmd.optIEDataLen,
+                                           data);
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
+        {
+            WMI_SET_RETRY_LIMITS_CMD setRetryParams;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setRetryParams, userdata,
+                                      sizeof(setRetryParams)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
+                                          setRetryParams.trafficClass,
+                                          setRetryParams.maxRetries,
+                                          setRetryParams.enableNotify) != A_OK)
+                {
+                    ret = -EIO;
+                }
+                AR6000_SPIN_LOCK(&ar->arLock, 0);
+                ar->arMaxRetries = setRetryParams.maxRetries;
+                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_BEACON_INTVAL:
+        {
+            WMI_BEACON_INT_CMD bIntvlCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bIntvlCmd, userdata,
+                       sizeof(bIntvlCmd)))
+            {
+                ret = -EFAULT;
+            } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
+                        != A_OK)
+            {
+                ret = -EIO;
+            }
+            if(ret == 0) {
+                ar->ap_beacon_interval = bIntvlCmd.beaconInterval;
+                ar->ap_profile_flag = 1; /* There is a change in profile */
+            }
+            break;
+        }
+        case IEEE80211_IOCTL_SETAUTHALG:
+        {
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            struct ieee80211req_authalg req;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&req, userdata,
+                       sizeof(struct ieee80211req_authalg)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) {
+                    ar->arDot11AuthMode  |= OPEN_AUTH;
+                    ar->arPairwiseCrypto  = NONE_CRYPT;
+                    ar->arGroupCrypto     = NONE_CRYPT;
+                }
+                if (req.auth_alg & AUTH_ALG_SHARED_KEY) {
+                    ar->arDot11AuthMode  |= SHARED_AUTH;
+                    ar->arPairwiseCrypto  = WEP_CRYPT;
+                    ar->arGroupCrypto     = WEP_CRYPT;
+                    ar->arAuthMode        = NONE_AUTH;
+                }
+                if (req.auth_alg == AUTH_ALG_LEAP) {
+                    ar->arDot11AuthMode   = LEAP_AUTH;
+                }
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
+            ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_SET_MAX_SP:
+            ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
+            ret = ar6000_ioctl_get_roam_tbl(dev, rq);
+            break;
+        case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
+            ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
+            break;
+        case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
+            ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
+            break;
+        case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
+            ret = ar6000_ioctl_get_power_mode(dev, rq);
+            break;
+        case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
+        {
+            AR6000_WLAN_STATE state;
+            get_user(state, (unsigned int *)userdata);
+            if (ar6000_set_wlan_state(ar, state)!=A_OK) {
+                ret = -EIO;
+            }       
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
+            ret = ar6000_ioctl_get_roam_data(dev, rq);
+            break;
+
+        case AR6000_XIOCTL_WMI_SET_BT_STATUS:
+            ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
+            break;
+
+        case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
+            ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
+            break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT:
+			ret = ar6000_xioctl_set_btcoex_fe_ant_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV:
+			ret = ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_sco_config_cmd( dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_a2dp_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG:
+			ret = ar6000_xioctl_set_btcoex_aclcoex_config_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG:
+			ret = ar60000_xioctl_set_btcoex_debug_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS:
+			ret = ar6000_xioctl_set_btcoex_bt_operating_status_cmd(dev, userdata);
+			break;
+
+		case AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG:
+			ret = ar6000_xioctl_get_btcoex_config_cmd(dev, userdata, rq);
+			break;
+
+		case AR6000_XIOCTL_WMI_GET_BTCOEX_STATS:
+			ret = ar6000_xioctl_get_btcoex_stats_cmd(dev, userdata, rq);
+			break;
+
+        case AR6000_XIOCTL_WMI_STARTSCAN:
+        {
+            WMI_START_SCAN_CMD setStartScanCmd, *cmdp;
+
+            if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                } else if (copy_from_user(&setStartScanCmd, userdata,
+                                          sizeof(setStartScanCmd)))
+                {
+                    ret = -EFAULT;
+                } else {
+                    if (setStartScanCmd.numChannels > 1) {
+                        cmdp = A_MALLOC(130);
+                        if (copy_from_user(cmdp, userdata,
+                                           sizeof (*cmdp) +
+                                           ((setStartScanCmd.numChannels - 1) *
+                                           sizeof(A_UINT16))))
+                        {
+                            kfree(cmdp);
+                            ret = -EFAULT;
+                            goto ioctl_done;
+                        }
+                    } else {
+                        cmdp = &setStartScanCmd;
+                    }
+
+                    if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType,
+                                          cmdp->forceFgScan,
+                                          cmdp->isLegacy,
+                                          cmdp->homeDwellTime,
+                                          cmdp->forceScanInterval,
+                                          cmdp->numChannels,
+                                          cmdp->channelList) != A_OK)
+                    {
+                        ret = -EIO;
+                    }
+                }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SETFIXRATES:
+        {
+            WMI_FIX_RATES_CMD setFixRatesCmd;
+            A_STATUS returnStatus;
+
+            if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                } else if (copy_from_user(&setFixRatesCmd, userdata,
+                                          sizeof(setFixRatesCmd)))
+                {
+                    ret = -EFAULT;
+                } else {
+                    returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
+                    if (returnStatus == A_EINVAL) {
+                        ret = -EINVAL;
+                    } else if(returnStatus != A_OK) {
+                        ret = -EIO;
+                    } else {
+                        ar->ap_profile_flag = 1; /* There is a change in profile */
+                    }
+                }
+            break;
+        }
+
+        case AR6000_XIOCTL_WMI_GETFIXRATES:
+        {
+            WMI_FIX_RATES_CMD getFixRatesCmd;
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            int ret = 0;
+
+            if (ar->bIsDestroyProgress) {
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            /* Used copy_from_user/copy_to_user to access user space data */
+            if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
+                ret = -EFAULT;
+            } else {
+                ar->arRateMask = 0xFFFFFFFF;
+
+                if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
+                    up(&ar->arSem);
+                    ret = -EIO;
+                    goto ioctl_done;
+                }
+
+                wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFFFFFF, wmitimeout * HZ);
+
+                if (signal_pending(current)) {
+                    ret = -EINTR;
+                }
+
+                if (!ret) {
+                    getFixRatesCmd.fixRateMask = ar->arRateMask;
+                }
+
+                if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
+                   ret = -EFAULT;
+                }
+
+                up(&ar->arSem);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_AUTHMODE:
+        {
+            WMI_SET_AUTH_MODE_CMD setAuthMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setAuthMode, userdata,
+                                      sizeof(setAuthMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
+        {
+            WMI_SET_REASSOC_MODE_CMD setReassocMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setReassocMode, userdata,
+                                      sizeof(setReassocMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DIAG_READ:
+        {
+            A_UINT32 addr, data;
+            get_user(addr, (unsigned int *)userdata);
+            addr = TARG_VTOP(ar->arTargetType, addr);
+            if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+                ret = -EIO;
+            }
+            put_user(data, (unsigned int *)userdata + 1);
+            break;
+        }
+        case AR6000_XIOCTL_DIAG_WRITE:
+        {
+            A_UINT32 addr, data;
+            get_user(addr, (unsigned int *)userdata);
+            get_user(data, (unsigned int *)userdata + 1);
+            addr = TARG_VTOP(ar->arTargetType, addr);
+            if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+                ret = -EIO;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
+        {
+             WMI_SET_KEEPALIVE_CMD setKeepAlive;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&setKeepAlive, userdata,
+                        sizeof(setKeepAlive))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_SET_PARAMS:
+        {
+             WMI_SET_PARAMS_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd) + cmd.length))
+            {
+                ret = -EFAULT;
+            } else {
+                 if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_SET_MCAST_FILTER:
+        {
+             WMI_SET_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+                                                                                     cmd.multicast_mac[1],
+                                                                                     cmd.multicast_mac[2],
+                                                                                     cmd.multicast_mac[3]) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER:
+        {
+             WMI_SET_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+                                                                                     cmd.multicast_mac[1],
+                                                                                     cmd.multicast_mac[2],
+                                                                                     cmd.multicast_mac[3]) != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_MCAST_FILTER:
+        {
+             WMI_MCAST_FILTER_CMD cmd;
+             if (ar->arWmiReady == FALSE) {
+                 ret = -EIO;
+                 goto ioctl_done;
+             } else if (copy_from_user(&cmd, userdata,
+                        sizeof(cmd))){
+                 ret = -EFAULT;
+             } else {
+                 if (wmi_mcast_filter_cmd(ar->arWmi, cmd.enable)  != A_OK) {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
+        {
+            AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+            WMI_GET_KEEPALIVE_CMD getKeepAlive;
+            int ret = 0;
+            if (ar->bIsDestroyProgress) {
+                ret =-EBUSY;
+                goto ioctl_done;
+            }
+            if (ar->arWmiReady == FALSE) {
+               ret = -EIO;
+               goto ioctl_done;
+            }
+            if (down_interruptible(&ar->arSem)) {
+                ret = -ERESTARTSYS;
+                goto ioctl_done;
+            }
+            if (ar->bIsDestroyProgress) {
+                up(&ar->arSem);
+                ret = -EBUSY;
+                goto ioctl_done;
+            }
+            if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
+               ret = -EFAULT;
+            } else {
+            getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
+            ar->arKeepaliveConfigured = 0xFF;
+            if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
+                up(&ar->arSem);
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
+            if (signal_pending(current)) {
+                ret = -EINTR;
+            }
+
+            if (!ret) {
+                getKeepAlive.configured = ar->arKeepaliveConfigured;
+            }
+            if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
+               ret = -EFAULT;
+            }
+            up(&ar->arSem);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_APPIE:
+        {
+            WMI_SET_APPIE_CMD appIEcmd;
+            A_UINT8           appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
+            A_UINT32            fType,ieLen;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            }
+            get_user(fType, (A_UINT32 *)userdata);
+            appIEcmd.mgmtFrmType = fType;
+            if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
+                ret = -EIO;
+            } else {
+                get_user(ieLen, (A_UINT32 *)(userdata + 4));
+                appIEcmd.ieLen = ieLen;
+                A_PRINTF("WPSIE: Type-%d, Len-%d\n",appIEcmd.mgmtFrmType, appIEcmd.ieLen);
+                if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
+                    ret = -EIO;
+                    break;
+                }
+                if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
+                    ret = -EFAULT;
+                } else {
+                    if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
+                                          appIEcmd.ieLen,  appIeInfo) != A_OK)
+                    {
+                        ret = -EIO;
+                    }
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
+        {
+            WMI_BSS_FILTER_CMD cmd;
+            A_UINT32    filterType;
+
+            if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+            if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
+                                    IEEE80211_FILTER_TYPE_PROBE_RESP))
+            {
+                cmd.bssFilter = ALL_BSS_FILTER;
+            } else {
+                cmd.bssFilter = NONE_BSS_FILTER;
+            }
+            if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
+                ret = -EIO;
+            } else {
+                ar->arUserBssFilter = cmd.bssFilter;
+            }
+
+            AR6000_SPIN_LOCK(&ar->arLock, 0);
+            ar->arMgmtFilter = filterType;
+            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
+        {
+            A_UINT32    wsc_status;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+                goto ioctl_done;
+            } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
+            {
+                ret = -EFAULT;
+                goto ioctl_done;
+            }
+            if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
+                ret = -EIO;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
+        {
+            A_UINT32 ROM_addr;
+            A_UINT32 RAM_addr;
+            A_UINT32 nbytes;
+            A_UINT32 do_activate;
+            A_UINT32 rompatch_id;
+
+            get_user(ROM_addr, (A_UINT32 *)userdata);
+            get_user(RAM_addr, (A_UINT32 *)userdata + 1);
+            get_user(nbytes, (A_UINT32 *)userdata + 2);
+            get_user(do_activate, (A_UINT32 *)userdata + 3);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Install rompatch from ROM: 0x%x to RAM: 0x%x  length: %d\n",
+                             ROM_addr, RAM_addr, nbytes));
+            ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
+                                        nbytes, do_activate, &rompatch_id);
+            if (ret == A_OK) {
+                put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
+        {
+            A_UINT32 rompatch_id;
+
+            get_user(rompatch_id, (A_UINT32 *)userdata);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("UNinstall rompatch_id %d\n", rompatch_id));
+            ret = BMIrompatchUninstall(hifDevice, rompatch_id);
+            break;
+        }
+
+        case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
+        case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
+        {
+            A_UINT32 rompatch_count;
+
+            get_user(rompatch_count, (A_UINT32 *)userdata);
+            AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Change rompatch activation count=%d\n", rompatch_count));
+            length = sizeof(A_UINT32) * rompatch_count;
+            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+                A_MEMZERO(buffer, length);
+                if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
+                {
+                    ret = -EFAULT;
+                } else {
+                    if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
+                        ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+                    } else {
+                        ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+                    }
+                }
+                A_FREE(buffer);
+            } else {
+                ret = -ENOMEM;
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_SET_IP:
+        {
+            WMI_SET_IP_CMD setIP;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setIP, userdata,
+                                      sizeof(setIP)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_ip_cmd(ar->arWmi,
+                                &setIP) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+
+        case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
+        {
+            WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setHostSleepMode, userdata,
+                                      sizeof(setHostSleepMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
+                                &setHostSleepMode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_SET_WOW_MODE:
+        {
+            WMI_SET_WOW_MODE_CMD setWowMode;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&setWowMode, userdata,
+                                      sizeof(setWowMode)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_wow_mode_cmd(ar->arWmi,
+                                &setWowMode) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_GET_WOW_LIST:
+        {
+            WMI_GET_WOW_LIST_CMD getWowList;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&getWowList, userdata,
+                                      sizeof(getWowList)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_get_wow_list_cmd(ar->arWmi,
+                                &getWowList) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
+        {
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+            WMI_ADD_WOW_PATTERN_CMD cmd;
+            A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
+            A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
+
+            do {
+                if (ar->arWmiReady == FALSE) {
+                    ret = -EIO;
+                    break;        
+                } 
+                if(copy_from_user(&cmd, userdata,
+                            sizeof(WMI_ADD_WOW_PATTERN_CMD))) 
+                {
+                    ret = -EFAULT;
+                    break;        
+                }
+                if (copy_from_user(pattern_data,
+                                      userdata + 3,
+                                      cmd.filter_size)) 
+                {
+                    ret = -EFAULT;
+                    break;        
+                }
+                if (copy_from_user(mask_data,
+                                  (userdata + 3 + cmd.filter_size),
+                                  cmd.filter_size))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (wmi_add_wow_pattern_cmd(ar->arWmi,
+                            &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            } while(FALSE);
+#undef WOW_PATTERN_SIZE
+#undef WOW_MASK_SIZE
+            break;
+        }
+        case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
+        {
+            WMI_DEL_WOW_PATTERN_CMD delWowPattern;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&delWowPattern, userdata,
+                                      sizeof(delWowPattern)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_del_wow_pattern_cmd(ar->arWmi,
+                                &delWowPattern) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
+            if (ar->arHtcTarget != NULL) {
+                HTCDumpCreditStates(ar->arHtcTarget);
+#ifdef HTC_EP_STAT_PROFILING
+                {
+                    HTC_ENDPOINT_STATS stats;
+                    int i;
+
+                    for (i = 0; i < 5; i++) {
+                        if (HTCGetEndpointStatistics(ar->arHtcTarget,
+                                                     i,
+                                                     HTC_EP_STAT_SAMPLE_AND_CLEAR,
+                                                     &stats)) {
+                            A_PRINTF(KERN_ALERT"------- Profiling Endpoint : %d \n", i);
+                            A_PRINTF(KERN_ALERT"TxCreditLowIndications : %d \n", stats.TxCreditLowIndications);
+                            A_PRINTF(KERN_ALERT"TxIssued : %d \n", stats.TxIssued);
+                            A_PRINTF(KERN_ALERT"TxDropped: %d \n", stats.TxDropped);
+                            A_PRINTF(KERN_ALERT"TxPacketsBundled : %d \n", stats.TxPacketsBundled);
+                            A_PRINTF(KERN_ALERT"TxBundles : %d \n", stats.TxBundles);
+                            A_PRINTF(KERN_ALERT"TxCreditRpts : %d \n", stats.TxCreditRpts);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromRx : %d \n", stats.TxCreditRptsFromRx);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromOther : %d \n", stats.TxCreditRptsFromOther);
+                            A_PRINTF(KERN_ALERT"TxCreditsRptsFromEp0 : %d \n", stats.TxCreditRptsFromEp0);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromRx : %d \n", stats.TxCreditsFromRx);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromOther : %d \n", stats.TxCreditsFromOther);
+                            A_PRINTF(KERN_ALERT"TxCreditsFromEp0 : %d \n", stats.TxCreditsFromEp0);
+                            A_PRINTF(KERN_ALERT"TxCreditsConsummed : %d \n", stats.TxCreditsConsummed);
+                            A_PRINTF(KERN_ALERT"TxCreditsReturned : %d \n", stats.TxCreditsReturned);
+                            A_PRINTF(KERN_ALERT"RxReceived : %d \n", stats.RxReceived);
+                            A_PRINTF(KERN_ALERT"RxPacketsBundled : %d \n", stats.RxPacketsBundled);
+                            A_PRINTF(KERN_ALERT"RxLookAheads : %d \n", stats.RxLookAheads);
+                            A_PRINTF(KERN_ALERT"RxBundleLookAheads : %d \n", stats.RxBundleLookAheads);
+                            A_PRINTF(KERN_ALERT"RxBundleIndFromHdr : %d \n", stats.RxBundleIndFromHdr);
+                            A_PRINTF(KERN_ALERT"RxAllocThreshHit : %d \n", stats.RxAllocThreshHit);
+                            A_PRINTF(KERN_ALERT"RxAllocThreshBytes : %d \n", stats.RxAllocThreshBytes);
+                            A_PRINTF(KERN_ALERT"---- \n");
+
+                        }
+            }
+                }
+#endif
+            }
+            break;
+        case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
+            if (ar->arHtcTarget != NULL) {
+                struct ar6000_traffic_activity_change data;
+
+                if (copy_from_user(&data, userdata, sizeof(data)))
+                {
+                    ret = -EFAULT;
+                    goto ioctl_done;
+                }
+                    /* note, this is used for testing (mbox ping testing), indicate activity
+                     * change using the stream ID as the traffic class */
+                ar6000_indicate_tx_activity(ar,
+                                            (A_UINT8)data.StreamID,
+                                            data.Active ? TRUE : FALSE);
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&connectCtrlFlags, userdata,
+                                      sizeof(connectCtrlFlags)))
+            {
+                ret = -EFAULT;
+            } else {
+                ar->arConnectCtrlFlags = connectCtrlFlags;
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&akmpParams, userdata,
+                                      sizeof(WMI_SET_AKMP_PARAMS_CMD)))
+            {
+                ret = -EFAULT;
+            } else {
+                if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                if (copy_from_user(&pmkidInfo.numPMKID, userdata,
+                                      sizeof(pmkidInfo.numPMKID)))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (copy_from_user(&pmkidInfo.pmkidList,
+                                   userdata + sizeof(pmkidInfo.numPMKID),
+                                   pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
+                {
+                    ret = -EFAULT;
+                    break;
+                }
+                if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else  {
+                if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
+                    ret = -EIO;
+                }
+            }
+            break;
+        case AR6000_XIOCTL_WMI_ABORT_SCAN:
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            ret = wmi_abort_scan_cmd(ar->arWmi);
+            break;
+        case AR6000_XIOCTL_AP_HIDDEN_SSID:
+        {
+            A_UINT8    hidden_ssid;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid);
+                ar->ap_hidden_ssid = hidden_ssid;
+                ar->ap_profile_flag = 1; /* There is a change in profile */
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_STA_LIST:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else {
+                A_UINT8 i;
+                ap_get_sta_t temp;
+                A_MEMZERO(&temp, sizeof(temp));
+                for(i=0;i<AP_MAX_NUM_STA;i++) {
+                    A_MEMCPY(temp.sta[i].mac, ar->sta_list[i].mac, ATH_MAC_LEN);
+                    temp.sta[i].aid = ar->sta_list[i].aid;
+                    temp.sta[i].keymgmt = ar->sta_list[i].keymgmt;
+                    temp.sta[i].ucipher = ar->sta_list[i].ucipher;
+                    temp.sta[i].auth = ar->sta_list[i].auth;
+                }
+                if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp,
+                                 sizeof(ar->sta_list))) {
+                    ret = -EFAULT;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_NUM_STA:
+        {
+            A_UINT8    num_sta;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) {
+                ret = -EFAULT;
+            } else if(num_sta > AP_MAX_NUM_STA) {
+                /* value out of range */
+                ret = -EINVAL;
+            } else {
+                wmi_ap_set_num_sta(ar->arWmi, num_sta);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_ACL_POLICY:
+        {
+            A_UINT8    policy;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&policy, userdata, sizeof(policy))) {
+                ret = -EFAULT;
+            } else if(policy == ar->g_acl.policy) {
+                /* No change in policy */
+            } else {
+                if(!(policy & AP_ACL_RETAIN_LIST_MASK)) {
+                    /* clear ACL list */
+                    memset(&ar->g_acl,0,sizeof(WMI_AP_ACL));
+                }
+                ar->g_acl.policy = policy;
+                wmi_ap_set_acl_policy(ar->arWmi, policy);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_ACL_MAC:
+        {
+            WMI_AP_ACL_MAC_CMD    acl;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&acl, userdata, sizeof(acl))) {
+                ret = -EFAULT;
+            } else {
+                if(acl_add_del_mac(&ar->g_acl, &acl)) {
+                    wmi_ap_acl_mac_list(ar->arWmi, &acl);
+                } else {
+                    A_PRINTF("ACL list error\n");
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_ACL_LIST:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl,
+                                 sizeof(WMI_AP_ACL))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_COMMIT_CONFIG:
+        {
+            ret = ar6000_ap_mode_profile_commit(ar);
+            break;
+        }
+        case IEEE80211_IOCTL_GETWPAIE:
+        {
+            struct ieee80211req_wpaie wpaie;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) {
+                ret = -EFAULT;
+            } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) {
+                ret = -EFAULT;
+            } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_CONN_INACT_TIME:
+        {
+            A_UINT32    period;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&period, userdata, sizeof(period))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_conn_inact_time(ar->arWmi, period);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_PROT_SCAN_TIME:
+        {
+            WMI_AP_PROT_SCAN_TIME_CMD  bgscan;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_COUNTRY:
+        {
+            ret = ar6000_ioctl_set_country(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_DTIM:
+        {
+            WMI_AP_SET_DTIM_CMD  d;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&d, userdata, sizeof(d))) {
+                ret = -EFAULT;
+            } else {
+                if(d.dtim > 0 && d.dtim < 11) {
+                    ar->ap_dtim_period = d.dtim;
+                    wmi_ap_set_dtim(ar->arWmi, d.dtim);
+                    ar->ap_profile_flag = 1; /* There is a change in profile */
+                } else {
+                    A_PRINTF("DTIM out of range. Valid range is [1-10]\n");
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT:
+        {
+            WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            }
+            if (copy_from_user(&evtCfgCmd, userdata,
+                               sizeof(evtCfgCmd))) {
+                ret = -EFAULT;
+                break;
+            }
+            ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd);
+            break;
+        }
+        case AR6000_XIOCTL_AP_INTRA_BSS_COMM:
+        {
+            A_UINT8    intra=0;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&intra, userdata, sizeof(intra))) {
+                ret = -EFAULT;
+            } else {
+                ar->intra_bss = (intra?1:0);
+            }
+            break;
+        }
+        case AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            a_dump_module_debug_info_by_name(moduleinfo.modulename);
+            ret = 0;
+            break;
+        }
+        case AR6000_XIOCTL_MODULE_DEBUG_SET_MASK:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (A_FAILED(a_set_module_mask(moduleinfo.modulename, moduleinfo.mask))) {
+                ret = -EFAULT;
+            }
+
+            break;
+        }
+        case AR6000_XIOCTL_MODULE_DEBUG_GET_MASK:
+        {
+            struct drv_debug_module_s moduleinfo;
+
+            if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (A_FAILED(a_get_module_mask(moduleinfo.modulename, &moduleinfo.mask))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            if (copy_to_user(userdata, &moduleinfo, sizeof(moduleinfo))) {
+                ret = -EFAULT;
+                break;
+            }
+
+            break;
+        }
+#ifdef ATH_AR6K_11N_SUPPORT
+        case AR6000_XIOCTL_DUMP_RCV_AGGR_STATS:
+        {
+            PACKET_LOG *copy_of_pkt_log;
+
+            aggr_dump_stats(ar->aggr_cntxt, &copy_of_pkt_log);
+            if (copy_to_user(rq->ifr_data, copy_of_pkt_log, sizeof(PACKET_LOG))) {
+                ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_SETUP_AGGR:
+        {
+            WMI_ADDBA_REQ_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_setup_aggr_cmd(ar->arWmi, cmd.tid);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_DELE_AGGR:
+        {
+            WMI_DELBA_REQ_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_delete_aggr_cmd(ar->arWmi, cmd.tid, cmd.is_sender_initiator);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_ALLOW_AGGR:
+        {
+            WMI_ALLOW_AGGR_CMD cmd;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                wmi_allow_aggr_cmd(ar->arWmi, cmd.tx_allow_aggr, cmd.rx_allow_aggr);
+            }
+        }
+        break;
+
+        case AR6000_XIOCTL_SET_HT_CAP:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&htCap, userdata,
+                                      sizeof(htCap)))
+            {
+                ret = -EFAULT;
+            } else {
+
+                if (wmi_set_ht_cap_cmd(ar->arWmi, &htCap) != A_OK)
+                {
+                    ret = -EIO;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_SET_HT_OP:
+        {
+             if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&htOp, userdata,
+                                      sizeof(htOp)))
+            {
+                 ret = -EFAULT;
+             } else {
+
+                if (wmi_set_ht_op_cmd(ar->arWmi, htOp.sta_chan_width) != A_OK)
+                {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+#endif
+        case AR6000_XIOCTL_ACL_DATA:
+        {
+            void *osbuf = NULL;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (ar6000_create_acl_data_osbuf(dev, (A_UINT8*)userdata, &osbuf) != A_OK) {
+                     ret = -EIO;
+            } else {
+                if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != A_OK) {
+                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n"));
+                } else {
+                    /* Send data buffer over HTC */
+                    ar6000_acl_data_tx(osbuf, ar->arNetDev);
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_HCI_CMD:
+        {
+            char tmp_buf[512];
+            A_INT8 i;
+            WMI_HCI_CMD *cmd = (WMI_HCI_CMD *)tmp_buf;
+            A_UINT8 size;
+
+            size = sizeof(cmd->cmd_buf_sz);
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(cmd, userdata, size)) {
+                 ret = -EFAULT;
+            } else if(copy_from_user(cmd->buf, userdata + size, cmd->cmd_buf_sz)) {
+                    ret = -EFAULT;
+            } else {
+                if (wmi_send_hci_cmd(ar->arWmi, cmd->buf, cmd->cmd_buf_sz) != A_OK) {
+                     ret = -EIO;
+                }else if(loghci) {
+                    A_PRINTF_LOG("HCI Command To PAL --> \n");
+                    for(i = 0; i < cmd->cmd_buf_sz; i++) {
+                        A_PRINTF_LOG("0x%02x ",cmd->buf[i]);
+                        if((i % 10) == 0) {
+                            A_PRINTF_LOG("\n");
+                        }
+                    }
+                    A_PRINTF_LOG("\n");
+                    A_PRINTF_LOG("==================================\n");
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_WLAN_CONN_PRECEDENCE:
+        {
+            WMI_SET_BT_WLAN_CONN_PRECEDENCE cmd;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+                ret = -EFAULT;
+            } else {
+                if (cmd.precedence == BT_WLAN_CONN_PRECDENCE_WLAN ||
+                            cmd.precedence == BT_WLAN_CONN_PRECDENCE_PAL) {
+                    if ( wmi_set_wlan_conn_precedence_cmd(ar->arWmi, cmd.precedence) != A_OK) {
+                        ret = -EIO;
+                    }
+                } else {
+                    ret = -EINVAL;
+                }
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_STAT:
+        {
+            ret = ar6000_ioctl_get_ap_stats(dev, rq);
+            break;
+        }
+        case AR6000_XIOCTL_SET_TX_SELECT_RATES:
+        {
+            WMI_SET_TX_SELECT_RATES_CMD masks;
+
+             if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&masks, userdata,
+                                      sizeof(masks)))
+            {
+                 ret = -EFAULT;
+             } else {
+
+                if (wmi_set_tx_select_rates_cmd(ar->arWmi, masks.rateMasks) != A_OK)
+                {
+                     ret = -EIO;
+               }
+             }
+             break;
+        }
+        case AR6000_XIOCTL_AP_GET_HIDDEN_SSID:
+        {
+            WMI_AP_HIDDEN_SSID_CMD ssid;
+            ssid.hidden_ssid = ar->ap_hidden_ssid;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_HIDDEN_SSID_CMD *)rq->ifr_data,
+                                    &ssid, sizeof(WMI_AP_HIDDEN_SSID_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_COUNTRY:
+        {
+            WMI_AP_SET_COUNTRY_CMD cty;
+            A_MEMCPY(cty.countryCode, ar->ap_country_code, 3);
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_SET_COUNTRY_CMD *)rq->ifr_data,
+                                    &cty, sizeof(WMI_AP_SET_COUNTRY_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_WMODE:
+        {
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((A_UINT8 *)rq->ifr_data,
+                                    &ar->ap_wmode, sizeof(A_UINT8))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_DTIM:
+        {
+            WMI_AP_SET_DTIM_CMD dtim;
+            dtim.dtim = ar->ap_dtim_period;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_AP_SET_DTIM_CMD *)rq->ifr_data,
+                                    &dtim, sizeof(WMI_AP_SET_DTIM_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_BINTVL:
+        {
+            WMI_BEACON_INT_CMD bi;
+            bi.beaconInterval = ar->ap_beacon_interval;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_BEACON_INT_CMD *)rq->ifr_data,
+                                    &bi, sizeof(WMI_BEACON_INT_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_GET_RTS:
+        {
+            WMI_SET_RTS_CMD rts;
+            rts.threshold = ar->arRTS;
+
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if(copy_to_user((WMI_SET_RTS_CMD *)rq->ifr_data,
+                                    &rts, sizeof(WMI_SET_RTS_CMD))) {
+                    ret = -EFAULT;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_FETCH_TARGET_REGS:
+        {
+            A_UINT32 targregs[AR6003_FETCH_TARG_REGS_COUNT];
+
+            if (ar->arTargetType == TARGET_TYPE_AR6003) {
+                ar6k_FetchTargetRegs(hifDevice, targregs);
+                if (copy_to_user((A_UINT32 *)rq->ifr_data, &targregs, sizeof(targregs)))
+                {
+                    ret = -EFAULT;
+                }
+            } else {
+                ret = -EOPNOTSUPP;
+            }
+            break;
+        }
+        case AR6000_XIOCTL_AP_SET_11BG_RATESET:
+        {
+            WMI_AP_SET_11BG_RATESET_CMD  rate;
+            if (ar->arWmiReady == FALSE) {
+                ret = -EIO;
+            } else if (copy_from_user(&rate, userdata, sizeof(rate))) {
+                ret = -EFAULT;
+            } else {
+                wmi_ap_set_rateset(ar->arWmi, rate.rateset);
+            }
+            break;
+        }
+        default:
+            ret = -EOPNOTSUPP;
+    }
+
+ioctl_done:
+    rtnl_lock(); /* restore rtnl state */
+    dev_put(dev);
+
+    return ret;
+}
+
+A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild)
+{
+    A_UINT8 i;
+
+    for(i=0;i<ATH_MAC_LEN;i++) {
+        if((wild & 1<<i) && (new_wild & 1<<i)) continue;
+        if(mac[i] != new_mac[i]) return 1;
+    }
+    if((A_MEMCMP(new_mac, null_mac, 6)==0) && new_wild &&
+        (wild != new_wild)) {
+        return 1;
+    }
+
+    return 0;
+}
+
+A_UINT8    acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl)
+{
+    A_INT8    already_avail=-1, free_slot=-1, i;
+
+    /* To check whether this mac is already there in our list */
+    for(i=AP_ACL_SIZE-1;i>=0;i--)
+    {
+        if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i],
+            acl->wildcard)==0)
+                already_avail = i;
+
+        if(!((1 << i) & a->index))
+            free_slot = i;
+    }
+
+    if(acl->action == ADD_MAC_ADDR)
+    {
+        /* Dont add mac if it is already available */
+        if((already_avail >= 0) || (free_slot == -1))
+            return 0;
+
+        A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN);
+        a->index = a->index | (1 << free_slot);
+        acl->index = free_slot;
+        a->wildcard[free_slot] = acl->wildcard;
+        return 1;
+    }
+    else if(acl->action == DEL_MAC_ADDR)
+    {
+        if(acl->index > AP_ACL_SIZE)
+            return 0;
+
+        if(!(a->index & (1 << acl->index)))
+            return 0;
+
+        A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN);
+        a->index = a->index & ~(1 << acl->index);
+        a->wildcard[acl->index] = 0;
+        return 1;
+    }
+
+    return 0;
+}
diff --git a/drivers/net/wireless/ath6kl/os/linux/netbuf.c b/drivers/net/wireless/ath6kl/os/linux/netbuf.c
new file mode 100644
index 000000000000..62b26c540449
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/netbuf.c
@@ -0,0 +1,233 @@
+
+/*
+ * 
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ * 
+ */
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <a_config.h>
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_packet.h"
+
+#define AR6000_DATA_OFFSET    64
+
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+    skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+    skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
+{
+    return((void *) skb_dequeue((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
+{
+    return(skb_queue_len((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
+{
+    return(skb_queue_empty((struct sk_buff_head *) q));
+}
+
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
+{
+    skb_queue_head_init((struct sk_buff_head *) q);
+}
+
+void *
+a_netbuf_alloc(int size)
+{
+    struct sk_buff *skb;
+    size += 2 * (A_GET_CACHE_LINE_BYTES()); /* add some cacheline space at front and back of buffer */
+    skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
+    skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + A_GET_CACHE_LINE_BYTES());    
+    return ((void *)skb);
+}
+
+/*
+ * Allocate an SKB w.o. any encapsulation requirement.
+ */
+void *
+a_netbuf_alloc_raw(int size)
+{
+    struct sk_buff *skb;
+
+    skb = dev_alloc_skb(size);
+
+    return ((void *)skb);
+}
+
+void
+a_netbuf_free(void *bufPtr)
+{
+    struct sk_buff *skb = (struct sk_buff *)bufPtr;
+
+    dev_kfree_skb(skb);
+}
+
+A_UINT32
+a_netbuf_to_len(void *bufPtr)
+{
+    return (((struct sk_buff *)bufPtr)->len);
+}
+
+void *
+a_netbuf_to_data(void *bufPtr)
+{
+    return (((struct sk_buff *)bufPtr)->data);
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_push(void *bufPtr, A_INT32 len)
+{
+    skb_push((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+    skb_push((struct sk_buff *) bufPtr, len);
+    A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_put(void *bufPtr, A_INT32 len)
+{
+    skb_put((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+    char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+        ((struct sk_buff *)bufPtr)->len);
+    skb_put((struct sk_buff *)bufPtr, len);
+    A_MEMCPY(start, srcPtr, len);
+
+    return A_OK;
+}
+
+
+/*
+ * Trim the network buffer pointed to by bufPtr to len # of bytes 
+ */
+A_STATUS
+a_netbuf_setlen(void *bufPtr, A_INT32 len)
+{
+    skb_trim((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer.
+ */
+A_STATUS
+a_netbuf_trim(void *bufPtr, A_INT32 len)
+{
+    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+    return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer and return the data.
+ */
+A_STATUS
+a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+    char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+        (((struct sk_buff *)bufPtr)->len - len));
+    
+    A_MEMCPY(dstPtr, start, len);
+    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+    return A_OK;
+}
+
+
+/*
+ * Returns the number of bytes available to a a_netbuf_push()
+ */
+A_INT32
+a_netbuf_headroom(void *bufPtr)
+{
+    return (skb_headroom((struct sk_buff *)bufPtr));
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ */
+A_STATUS
+a_netbuf_pull(void *bufPtr, A_INT32 len)
+{
+    skb_pull((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ * and return the data
+ */
+A_STATUS
+a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+    A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
+    skb_pull((struct sk_buff *)bufPtr, len);
+
+    return A_OK;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(a_netbuf_to_data);
+EXPORT_SYMBOL(a_netbuf_put);
+EXPORT_SYMBOL(a_netbuf_pull);
+EXPORT_SYMBOL(a_netbuf_alloc);
+EXPORT_SYMBOL(a_netbuf_free);
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c
new file mode 100644
index 000000000000..9d17574aef09
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c
@@ -0,0 +1,2703 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#include "ar6000_drv.h"
+
+static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+
+#if WIRELESS_EXT > 14
+/*
+ * Encode a WPA or RSN information element as a custom
+ * element using the hostap format.
+ */
+static u_int
+encode_ie(void *buf, size_t bufsize,
+    const u_int8_t *ie, size_t ielen,
+    const char *leader, size_t leader_len)
+{
+    u_int8_t *p;
+    int i;
+
+    if (bufsize < leader_len)
+        return 0;
+    p = buf;
+    memcpy(p, leader, leader_len);
+    bufsize -= leader_len;
+    p += leader_len;
+    for (i = 0; i < ielen && bufsize > 2; i++)
+    {
+        p += sprintf((char*)p, "%02x", ie[i]);
+        bufsize -= 2;
+    }
+    return (i == ielen ? p - (u_int8_t *)buf : 0);
+}
+#endif /* WIRELESS_EXT > 14 */
+
+void
+ar6000_scan_node(void *arg, bss_t *ni)
+{
+    struct iw_event iwe;
+#if WIRELESS_EXT > 14
+    char buf[256];
+#endif
+    struct ar_giwscan_param *param;
+    A_CHAR *current_ev;
+    A_CHAR *end_buf;
+    struct ieee80211_common_ie  *cie;
+    A_CHAR *current_val;
+    A_INT32 j;
+    A_UINT32 rate_len, data_len = 0;
+
+    param = (struct ar_giwscan_param *)arg;
+
+    current_ev = param->current_ev;
+    end_buf = param->end_buf;
+
+    cie = &ni->ni_cie;
+
+    if ((end_buf - current_ev) > IW_EV_ADDR_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWAP;
+        iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
+        A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
+        current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe,
+                          IW_EV_ADDR_LEN);
+    }
+    param->bytes_needed += IW_EV_ADDR_LEN;
+
+    data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN;
+    if ((end_buf - current_ev) > data_len)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWESSID;
+        iwe.u.data.flags = 1;
+        iwe.u.data.length = cie->ie_ssid[1];
+        current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe,
+                          (char*)&cie->ie_ssid[2]);
+    }
+    param->bytes_needed += data_len;
+
+    if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
+        if ((end_buf - current_ev) > IW_EV_UINT_LEN)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = SIOCGIWMODE;
+            iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
+                         IW_MODE_MASTER : IW_MODE_ADHOC;
+            current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe,
+                          IW_EV_UINT_LEN);
+        }
+        param->bytes_needed += IW_EV_UINT_LEN;
+    }
+
+    if ((end_buf - current_ev) > IW_EV_FREQ_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWFREQ;
+        iwe.u.freq.m = cie->ie_chan * 100000;
+        iwe.u.freq.e = 1;
+        current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe,
+                          IW_EV_FREQ_LEN);
+    }
+    param->bytes_needed += IW_EV_FREQ_LEN;
+
+    if ((end_buf - current_ev) > IW_EV_QUAL_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = IWEVQUAL;
+        ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
+        current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe,
+                          IW_EV_QUAL_LEN);
+    }
+    param->bytes_needed += IW_EV_QUAL_LEN;
+
+    if ((end_buf - current_ev) > IW_EV_POINT_LEN)
+    {
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWENCODE;
+        if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
+            iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
+        } else {
+            iwe.u.data.flags = IW_ENCODE_DISABLED;
+        }
+        iwe.u.data.length = 0;
+        current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, "");
+    }
+    param->bytes_needed += IW_EV_POINT_LEN;
+
+    /* supported bit rate */
+    A_MEMZERO(&iwe, sizeof(iwe));
+    iwe.cmd = SIOCGIWRATE;
+    iwe.u.bitrate.fixed = 0;
+    iwe.u.bitrate.disabled = 0;
+    iwe.u.bitrate.value = 0;
+    current_val = current_ev + IW_EV_LCP_LEN;
+    param->bytes_needed += IW_EV_LCP_LEN;
+
+    if (cie->ie_rates != NULL) {
+        rate_len = cie->ie_rates[1];
+        data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+        if ((end_buf - current_ev) > data_len)
+        {
+            for (j = 0; j < rate_len; j++) {
+                    unsigned char val;
+                    val = cie->ie_rates[2 + j];
+                    iwe.u.bitrate.value =
+                        (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+                    current_val = iwe_stream_add_value(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                                      param->info,
+#endif
+                                      current_ev,
+                                      current_val,
+                                      end_buf,
+                                      &iwe,
+                                      IW_EV_PARAM_LEN);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_xrates != NULL) {
+        rate_len = cie->ie_xrates[1];
+        data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+        if ((end_buf - current_ev) > data_len)
+        {
+            for (j = 0; j < rate_len; j++) {
+                    unsigned char val;
+                    val = cie->ie_xrates[2 + j];
+                    iwe.u.bitrate.value =
+                        (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+                    current_val = iwe_stream_add_value(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                                      param->info,
+#endif
+                                      current_ev,
+                                      current_val,
+                                      end_buf,
+                                      &iwe,
+                                      IW_EV_PARAM_LEN);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+    /* remove fixed header if no rates were added */
+    if ((current_val - current_ev) > IW_EV_LCP_LEN)
+        current_ev = current_val;
+
+#if WIRELESS_EXT >= 18
+    /* IE */
+    if (cie->ie_wpa != NULL) {
+        data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_wpa[1] + 2;
+            current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, (char*)cie->ie_wpa);
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+        data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_rsn[1] + 2;
+            current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, (char*)cie->ie_rsn);
+        }
+        param->bytes_needed += data_len;
+    }
+
+#endif /* WIRELESS_EXT >= 18 */
+
+    if ((end_buf - current_ev) > IW_EV_CHAR_LEN)
+    {
+        /* protocol */
+        A_MEMZERO(&iwe, sizeof(iwe));
+        iwe.cmd = SIOCGIWNAME;
+#define CHAN_IS_11A(x)              (!((x >= 2412) && (x <= 2484)))
+        if (CHAN_IS_11A(cie->ie_chan)) {
+            if (cie->ie_htcap) {
+                /* 11na */
+                snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11na");
+            }
+            else {
+                /* 11a */
+                snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a");
+            }
+        } else if ((cie->ie_erp) || (cie->ie_xrates)) {
+            if (cie->ie_htcap) {
+                /* 11ng */
+                snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11ng");
+            }
+            else {
+                /* 11g */
+                snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g");
+            }
+        } else {
+            /* 11b */
+            snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b");
+        }
+        current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, IW_EV_CHAR_LEN);
+    }
+    param->bytes_needed += IW_EV_CHAR_LEN;
+
+#if WIRELESS_EXT > 14
+    A_MEMZERO(&iwe, sizeof(iwe));
+    iwe.cmd = IWEVCUSTOM;
+    iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
+    data_len = iwe.u.data.length + IW_EV_POINT_LEN;
+    if ((end_buf - current_ev) > data_len)
+    {
+        current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, buf);
+    }
+    param->bytes_needed += data_len;
+
+#if WIRELESS_EXT < 18
+    if (cie->ie_wpa != NULL) {
+        static const char wpa_leader[] = "wpa_ie=";
+        data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
+                                          cie->ie_wpa[1]+2,
+                                          wpa_leader, sizeof(wpa_leader)-1);
+
+            if (iwe.u.data.length != 0) {
+                current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                              param->info,
+#endif
+                              current_ev, end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+        static const char rsn_leader[] = "rsn_ie=";
+        data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
+                                          cie->ie_rsn[1]+2,
+                                          rsn_leader, sizeof(rsn_leader)-1);
+
+            if (iwe.u.data.length != 0) {
+                current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                              param->info,
+#endif
+                              current_ev, end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WIRELESS_EXT < 18 */
+
+    if (cie->ie_wmm != NULL) {
+        static const char wmm_leader[] = "wmm_ie=";
+        data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
+                                          cie->ie_wmm[1]+2,
+                                          wmm_leader, sizeof(wmm_leader)-1);
+            if (iwe.u.data.length != 0) {
+                current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                              param->info,
+#endif
+                              current_ev, end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+    if (cie->ie_ath != NULL) {
+        static const char ath_leader[] = "ath_ie=";
+        data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
+                                          cie->ie_ath[1]+2,
+                                          ath_leader, sizeof(ath_leader)-1);
+            if (iwe.u.data.length != 0) {
+                current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                              param->info,
+#endif
+                              current_ev, end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+
+#ifdef WAPI_ENABLE
+    if (cie->ie_wapi != NULL) {
+        static const char wapi_leader[] = "wapi_ie=";
+        data_len = (sizeof(wapi_leader) - 1) + ((cie->ie_wapi[1] + 2) * 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len) {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVCUSTOM;
+            iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wapi,
+                                      cie->ie_wapi[1] + 2,
+                                      wapi_leader, sizeof(wapi_leader) - 1);
+            if (iwe.u.data.length != 0) {
+                current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                                              param->info,
+#endif
+                                              current_ev, end_buf, &iwe, buf);
+            }
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WAPI_ENABLE */
+
+#endif /* WIRELESS_EXT > 14 */
+
+#if WIRELESS_EXT >= 18
+    if (cie->ie_wsc != NULL) {
+        data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN;
+        if ((end_buf - current_ev) > data_len)
+        {
+            A_MEMZERO(&iwe, sizeof(iwe));
+            iwe.cmd = IWEVGENIE;
+            iwe.u.data.length = cie->ie_wsc[1] + 2;
+            current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+                          param->info,
+#endif
+                          current_ev, end_buf, &iwe, (char*)cie->ie_wsc);
+        }
+        param->bytes_needed += data_len;
+    }
+#endif /* WIRELESS_EXT >= 18 */
+
+    param->current_ev = current_ev;
+}
+
+int
+ar6000_ioctl_giwscan(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct ar_giwscan_param param;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    param.current_ev = extra;
+    param.end_buf = extra + data->length;
+    param.bytes_needed = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+    param.info = info;
+#endif
+
+    /* Translate data to WE format */
+    wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
+
+    /* check if bytes needed is greater than bytes consumed */
+    if (param.bytes_needed > (param.current_ev - extra))
+    {
+        /* Request one byte more than needed, because when "data->length" equals bytes_needed,
+        it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions
+        checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/
+        data->length = param.bytes_needed + 1;
+
+        return -E2BIG;
+    }
+
+    return 0;
+}
+
+extern int reconnect_flag;
+/* SIOCSIWESSID */
+static int
+ar6000_ioctl_siwessid(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *ssid)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_STATUS status;
+    A_UINT8     arNetworkType;
+    A_UINT8 prevMode = ar->arNetworkType;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+#if defined(WIRELESS_EXT)
+    if (WIRELESS_EXT >= 20) {
+        data->length += 1;
+    }
+#endif
+
+    /*
+     * iwconfig passes a null terminated string with length including this
+     * so we need to account for this
+     */
+    if (data->flags && (!data->length || (data->length == 1) ||
+        ((data->length - 1) > sizeof(ar->arSsid))))
+    {
+        /*
+         * ssid is invalid
+         */
+        return -EINVAL;
+    }
+
+    if (ar->arNextMode == AP_NETWORK) {
+        /* SSID change for AP network - Will take effect on commit */
+        if(A_MEMCMP(ar->arSsid,ssid,32) != 0) {
+             ar->arSsidLen = data->length - 1;
+            A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+            ar->ap_profile_flag = 1; /* There is a change in profile */
+        }
+        return 0;
+    } else if(ar->arNetworkType == AP_NETWORK) {
+        A_UINT8 ctr;
+        struct sk_buff *skb;
+
+        /* We are switching from AP to STA | IBSS mode, cleanup the AP state */
+        for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) {
+            remove_sta(ar, ar->sta_list[ctr].mac, 0);
+        }
+        A_MUTEX_LOCK(&ar->mcastpsqLock);
+        while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+            skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+            A_NETBUF_FREE(skb);
+        }
+        A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+    }
+
+    /* Added for bug 25178, return an IOCTL error instead of target returning
+       Illegal parameter error when either the BSSID or channel is missing
+       and we cannot scan during connect.
+     */
+    if (data->flags) {
+        if (ar->arSkipScan == TRUE &&
+            (ar->arChannelHint == 0 ||
+             (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
+              !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
+        {
+            return -EINVAL;
+        }
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+        /*
+         * sleep until the command queue drains
+         */
+        wait_event_interruptible_timeout(arEvent,
+            ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            return -EINTR;
+        }
+    }
+
+    if (!data->flags) {
+        arNetworkType = ar->arNetworkType;
+        ar6000_init_profile_info(ar);
+        ar->arNetworkType = arNetworkType;
+    }
+
+    /* Update the arNetworkType */
+    ar->arNetworkType = ar->arNextMode;
+
+
+    if ((prevMode != AP_NETWORK) &&
+        ((ar->arSsidLen) || ((ar->arSsidLen == 0) && ar->arConnected) || (!data->flags)))
+    {
+        if ((!data->flags) ||
+            (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
+            (ar->arSsidLen != (data->length - 1)))
+        {
+            /*
+             * SSID set previously or essid off has been issued.
+             *
+             * Disconnect Command is issued in two cases after wmi is ready
+             * (1) ssid is different from the previous setting
+             * (2) essid off has been issued
+             *
+             */
+            if (ar->arWmiReady == TRUE) {
+                reconnect_flag = 0;
+                status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+                status = wmi_disconnect_cmd(ar->arWmi);
+                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+                ar->arSsidLen = 0;
+                if (ar->arSkipScan == FALSE) {
+                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+                }
+                if (!data->flags) {
+                    up(&ar->arSem);
+                    return 0;
+                }
+            } else {
+                 up(&ar->arSem);
+            }
+        }
+        else
+        {
+            /*
+             * SSID is same, so we assume profile hasn't changed.
+             * If the interface is up and wmi is ready, we issue
+             * a reconnect cmd. Issue a reconnect only we are already
+             * connected.
+             */
+            if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
+            {
+                reconnect_flag = TRUE;
+                status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
+                                           ar->arChannelHint);
+                up(&ar->arSem);
+                if (status != A_OK) {
+                    return -EIO;
+                }
+                return 0;
+            }
+            else{
+                /*
+                 * Dont return if connect is pending.
+                 */
+                if(!(ar->arConnectPending)) {
+                    up(&ar->arSem);
+                    return 0;
+                }
+            }
+        }
+    }
+
+    ar->arSsidLen = data->length - 1;
+    A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+
+    if (ar6000_connect_to_ap(ar)!= A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }else{
+      up(&ar->arSem);
+    }
+    return 0;
+}
+
+/* SIOCGIWESSID */
+static int
+ar6000_ioctl_giwessid(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *essid)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (!ar->arSsidLen) {
+        return -EINVAL;
+    }
+
+    data->flags = 1;
+    data->length = ar->arSsidLen;
+    A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
+
+    return 0;
+}
+
+
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
+{
+    A_UINT8 index;
+    A_UINT8 keyUsage;
+
+    for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
+        if (ar->arWepKeyList[index].arKeyLen) {
+            keyUsage = GROUP_USAGE;
+            if (index == ar->arDefTxKeyIndex) {
+                keyUsage |= TX_USAGE;
+            }
+            wmi_addKey_cmd(ar->arWmi,
+                           index,
+                           WEP_CRYPT,
+                           keyUsage,
+                           ar->arWepKeyList[index].arKeyLen,
+                           NULL,
+                           ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+                           NO_SYNC_WMIFLAG);
+        }
+    }
+}
+
+/*
+ * SIOCSIWRATE
+ */
+int
+ar6000_ioctl_siwrate(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT32  kbps;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (rrq->fixed) {
+        kbps = rrq->value / 1000;           /* rrq->value is in bps */
+    } else {
+        kbps = -1;                          /* -1 indicates auto rate */
+    }
+    if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BitRate is not Valid %d\n", kbps));
+        return -EINVAL;
+    }
+    ar->arBitRate = kbps;
+    if(ar->arWmiReady == TRUE)
+    {
+        if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) {
+            return -EINVAL;
+        }
+    }
+    return 0;
+}
+
+/*
+ * SIOCGIWRATE
+ */
+int
+ar6000_ioctl_giwrate(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if(ar->arWmiReady == TRUE)
+    {
+        ar->arBitRate = 0xFFFF;
+        if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
+            up(&ar->arSem);
+            return -EIO;
+        }
+        wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
+        if (signal_pending(current)) {
+            ret = -EINTR;
+        }
+    }
+    /* If the interface is down or wmi is not ready or the target is not
+       connected - return the value stored in the device structure */
+    if (!ret) {
+        if (ar->arBitRate == -1) {
+            rrq->fixed = TRUE;
+            rrq->value = 0;
+        } else {
+            rrq->value = ar->arBitRate * 1000;
+        }
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+/*
+ * SIOCSIWTXPOW
+ */
+static int
+ar6000_ioctl_siwtxpow(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8 dbM;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (rrq->disabled) {
+        return -EOPNOTSUPP;
+    }
+
+    if (rrq->fixed) {
+        if (rrq->flags != IW_TXPOW_DBM) {
+            return -EOPNOTSUPP;
+        }
+        ar->arTxPwr= dbM = rrq->value;
+        ar->arTxPwrSet = TRUE;
+    } else {
+        ar->arTxPwr = dbM = 0;
+        ar->arTxPwrSet = FALSE;
+    }
+    if(ar->arWmiReady == TRUE)
+    {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("Set tx pwr cmd %d dbM\n", dbM));
+        wmi_set_txPwr_cmd(ar->arWmi, dbM);
+    }
+    return 0;
+}
+
+/*
+ * SIOCGIWTXPOW
+ */
+int
+ar6000_ioctl_giwtxpow(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
+    {
+        ar->arTxPwr = 0;
+
+        if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+            up(&ar->arSem);
+            return -EIO;
+        }
+
+        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
+
+        if (signal_pending(current)) {
+            ret = -EINTR;
+         }
+    }
+   /* If the interace is down or wmi is not ready or target is not connected
+      then return value stored in the device structure */
+
+    if (!ret) {
+         if (ar->arTxPwrSet == TRUE) {
+            rrq->fixed = TRUE;
+        }
+        rrq->value = ar->arTxPwr;
+        rrq->flags = IW_TXPOW_DBM;
+        //
+        // IWLIST need this flag to get TxPower
+        //
+        rrq->disabled = 0;
+    }
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+/*
+ * SIOCSIWRETRY
+ * since iwconfig only provides us with one max retry value, we use it
+ * to apply to data frames of the BE traffic class.
+ */
+static int
+ar6000_ioctl_siwretry(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (rrq->disabled) {
+        return -EOPNOTSUPP;
+    }
+
+    if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
+        return -EOPNOTSUPP;
+    }
+
+    if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
+            return - EINVAL;
+    }
+    if(ar->arWmiReady == TRUE)
+    {
+        if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
+                                     rrq->value, 0) != A_OK){
+            return -EINVAL;
+        }
+    }
+    ar->arMaxRetries = rrq->value;
+    return 0;
+}
+
+/*
+ * SIOCGIWRETRY
+ */
+static int
+ar6000_ioctl_giwretry(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_param *rrq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    rrq->disabled = 0;
+    switch (rrq->flags & IW_RETRY_TYPE) {
+    case IW_RETRY_LIFETIME:
+        return -EOPNOTSUPP;
+        break;
+    case IW_RETRY_LIMIT:
+        rrq->flags = IW_RETRY_LIMIT;
+        switch (rrq->flags & IW_RETRY_MODIFIER) {
+        case IW_RETRY_MIN:
+            rrq->flags |= IW_RETRY_MIN;
+            rrq->value = WMI_MIN_RETRIES;
+            break;
+        case IW_RETRY_MAX:
+            rrq->flags |= IW_RETRY_MAX;
+            rrq->value = ar->arMaxRetries;
+            break;
+        }
+        break;
+    }
+    return 0;
+}
+
+/*
+ * SIOCSIWENCODE
+ */
+static int
+ar6000_ioctl_siwencode(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *keybuf)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int index;
+    A_INT32 auth = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if(ar->arNextMode != AP_NETWORK) {
+    /*
+     *  Static WEP Keys should be configured before setting the SSID
+     */
+    if (ar->arSsid[0] && erq->length) {
+        return -EIO;
+    }
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    index = erq->flags & IW_ENCODE_INDEX;
+
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                  ((index - 1) > WMI_MAX_KEY_INDEX)))
+    {
+        return -EIO;
+    }
+
+    if (erq->flags & IW_ENCODE_DISABLED) {
+        /*
+         * Encryption disabled
+         */
+        if (index) {
+            /*
+             * If key index was specified then clear the specified key
+             */
+            index--;
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            ar->arWepKeyList[index].arKeyLen = 0;
+        }
+        ar->arDot11AuthMode       = OPEN_AUTH;
+        ar->arPairwiseCrypto      = NONE_CRYPT;
+        ar->arGroupCrypto         = NONE_CRYPT;
+        ar->arAuthMode            = NONE_AUTH;
+    } else {
+        /*
+         * Enabling WEP encryption
+         */
+        if (index) {
+            index--;                /* keyindex is off base 1 in iwconfig */
+        }
+
+        if (erq->flags & IW_ENCODE_OPEN) {
+            auth |= OPEN_AUTH;
+            ar->arDefTxKeyIndex = index;
+        }
+        if (erq->flags & IW_ENCODE_RESTRICTED) {
+            auth |= SHARED_AUTH;
+        }
+
+        if (!auth) {
+            auth = OPEN_AUTH;
+        }
+
+        if (erq->length) {
+            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
+                return -EIO;
+            }
+
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
+            ar->arWepKeyList[index].arKeyLen = erq->length;
+            ar->arDot11AuthMode       = auth;
+        } else {
+            if (ar->arWepKeyList[index].arKeyLen == 0) {
+                return -EIO;
+            }
+            ar->arDefTxKeyIndex = index;
+
+            if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) {
+                wmi_addKey_cmd(ar->arWmi,
+                               index,
+                               WEP_CRYPT,
+                               GROUP_USAGE | TX_USAGE,
+                               ar->arWepKeyList[index].arKeyLen,
+                               NULL,
+                               ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+                               NO_SYNC_WMIFLAG);
+            }
+        }
+
+        ar->arPairwiseCrypto      = WEP_CRYPT;
+        ar->arGroupCrypto         = WEP_CRYPT;
+        ar->arAuthMode            = NONE_AUTH;
+    }
+
+    if(ar->arNextMode != AP_NETWORK) {
+    /*
+     * profile has changed.  Erase ssid to signal change
+     */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+    return 0;
+}
+
+static int
+ar6000_ioctl_giwencode(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *key)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT8 keyIndex;
+    struct ar_wep_key *wk;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arPairwiseCrypto == NONE_CRYPT) {
+        erq->length = 0;
+        erq->flags = IW_ENCODE_DISABLED;
+    } else {
+        if (ar->arPairwiseCrypto == WEP_CRYPT) {
+            /* get the keyIndex */
+            keyIndex = erq->flags & IW_ENCODE_INDEX;
+            if (0 == keyIndex) {
+                keyIndex = ar->arDefTxKeyIndex;
+            } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
+                       (keyIndex - 1 > WMI_MAX_KEY_INDEX))
+            {
+                keyIndex = WMI_MIN_KEY_INDEX;
+            } else {
+                keyIndex--;
+            }
+            erq->flags = keyIndex + 1;
+            erq->flags &= ~IW_ENCODE_DISABLED;
+            wk = &ar->arWepKeyList[keyIndex];
+            if (erq->length > wk->arKeyLen) {
+                erq->length = wk->arKeyLen;
+            }
+            if (wk->arKeyLen) {
+                A_MEMCPY(key, wk->arKey, erq->length);
+            }
+        } else {
+            erq->flags &= ~IW_ENCODE_DISABLED;
+            if (ar->user_saved_keys.keyOk) {
+                erq->length = ar->user_saved_keys.ucast_ik.ik_keylen;
+                if (erq->length) {
+                    A_MEMCPY(key, ar->user_saved_keys.ucast_ik.ik_keydata, erq->length);
+                }
+            } else {
+                erq->length = 1;    // not really printing any key but let iwconfig know enc is on
+            }
+        }
+
+        if (ar->arDot11AuthMode & OPEN_AUTH) {
+            erq->flags |= IW_ENCODE_OPEN;
+        }
+        if (ar->arDot11AuthMode & SHARED_AUTH) {
+            erq->flags |= IW_ENCODE_RESTRICTED;
+        }
+    }
+
+    return 0;
+}
+
+#if WIRELESS_EXT >= 18
+/*
+ * SIOCSIWGENIE
+ */
+static int
+ar6000_ioctl_siwgenie(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+#ifdef WAPI_ENABLE
+    A_UINT8    *ie = erq->pointer;
+    A_UINT8    ie_type = ie[0];
+    A_UINT16   ie_length = erq->length;
+    A_UINT8    wapi_ie[128];
+#endif
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+#ifdef WAPI_ENABLE
+    if (ie_type == IEEE80211_ELEMID_WAPI) {
+        if(copy_from_user(wapi_ie, ie, ie_length))
+            return -EIO;
+        wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
+    }
+#endif
+    return 0;
+}
+
+
+/*
+ * SIOCGIWGENIE
+ */
+static int
+ar6000_ioctl_giwgenie(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+    erq->length = 0;
+    erq->flags = 0;
+
+    return 0;
+}
+
+/*
+ * SIOCSIWAUTH
+ */
+static int
+ar6000_ioctl_siwauth(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_param *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    A_BOOL profChanged;
+    A_UINT16 param;
+    A_INT32 ret;
+    A_INT32 value;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    param = data->flags & IW_AUTH_INDEX;
+    value = data->value;
+    profChanged = TRUE;
+    ret = 0;
+
+    switch (param) {
+        case IW_AUTH_WPA_VERSION:
+            if (value & IW_AUTH_WPA_VERSION_DISABLED) {
+                ar->arAuthMode = NONE_AUTH;
+            } else if (value & IW_AUTH_WPA_VERSION_WPA) {
+                    ar->arAuthMode = WPA_AUTH;
+            } else if (value & IW_AUTH_WPA_VERSION_WPA2) {
+                    ar->arAuthMode = WPA2_AUTH;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_CIPHER_PAIRWISE:
+            if (value & IW_AUTH_CIPHER_NONE) {
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP40) {
+                ar->arPairwiseCrypto = WEP_CRYPT;
+                ar->arPairwiseCryptoLen = 5;
+            } else if (value & IW_AUTH_CIPHER_TKIP) {
+                ar->arPairwiseCrypto = TKIP_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_CCMP) {
+                ar->arPairwiseCrypto = AES_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP104) {
+                ar->arPairwiseCrypto = WEP_CRYPT;
+                ar->arPairwiseCryptoLen = 13;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_CIPHER_GROUP:
+            if (value & IW_AUTH_CIPHER_NONE) {
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP40) {
+                ar->arGroupCrypto = WEP_CRYPT;
+                ar->arGroupCryptoLen = 5;
+            } else if (value & IW_AUTH_CIPHER_TKIP) {
+                ar->arGroupCrypto = TKIP_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_CCMP) {
+                ar->arGroupCrypto = AES_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            } else if (value & IW_AUTH_CIPHER_WEP104) {
+                ar->arGroupCrypto = WEP_CRYPT;
+                ar->arGroupCryptoLen = 13;
+            } else {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_KEY_MGMT:
+            if (value & IW_AUTH_KEY_MGMT_PSK) {
+                if (WPA_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA_PSK_AUTH;
+                } else if (WPA2_AUTH == ar->arAuthMode) {
+                    ar->arAuthMode = WPA2_PSK_AUTH;
+                } else {
+                    ret = -1;
+                }
+            } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) {
+                ar->arAuthMode = NONE_AUTH;
+            }
+            break;
+        case IW_AUTH_TKIP_COUNTERMEASURES:
+            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_DROP_UNENCRYPTED:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_80211_AUTH_ALG:
+            ar->arDot11AuthMode = 0;
+            if (value & IW_AUTH_ALG_OPEN_SYSTEM) {
+                ar->arDot11AuthMode  |= OPEN_AUTH;
+            }
+            if (value & IW_AUTH_ALG_SHARED_KEY) {
+                ar->arDot11AuthMode  |= SHARED_AUTH;
+            }
+            if (value & IW_AUTH_ALG_LEAP) {
+                ar->arDot11AuthMode   = LEAP_AUTH;
+            }
+            if(ar->arDot11AuthMode == 0) {
+                ret = -1;
+                profChanged    = FALSE;
+            }
+            break;
+        case IW_AUTH_WPA_ENABLED:
+            if (!value) {
+                ar->arAuthMode = NONE_AUTH;
+                /* when the supplicant is stopped, it calls this
+                 * handler with value=0. The followings need to be
+                 * reset if the STA were to connect again
+                 * without security
+                 */
+                ar->arDot11AuthMode = OPEN_AUTH;
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            }
+            break;
+        case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_ROAMING_CONTROL:
+            profChanged    = FALSE;
+            break;
+        case IW_AUTH_PRIVACY_INVOKED:
+            if (!value) {
+                ar->arPairwiseCrypto = NONE_CRYPT;
+                ar->arPairwiseCryptoLen = 0;
+                ar->arGroupCrypto = NONE_CRYPT;
+                ar->arGroupCryptoLen = 0;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IW_AUTH_WAPI_ENABLED:
+            ar->arWapiEnable = value;
+            break;
+#endif
+        default:
+           ret = -1;
+           profChanged    = FALSE;
+           break;
+    }
+
+    if (profChanged == TRUE) {
+        /*
+         * profile has changed.  Erase ssid to signal change
+         */
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    return ret;
+}
+
+
+/*
+ * SIOCGIWAUTH
+ */
+static int
+ar6000_ioctl_giwauth(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_param *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_UINT16 param;
+    A_INT32 ret;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    param = data->flags & IW_AUTH_INDEX;
+    ret = 0;
+    data->value = 0;
+
+
+    switch (param) {
+        case IW_AUTH_WPA_VERSION:
+            if (ar->arAuthMode == NONE_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_DISABLED;
+            } else if (ar->arAuthMode == WPA_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_WPA;
+            } else if (ar->arAuthMode == WPA2_AUTH) {
+                data->value |= IW_AUTH_WPA_VERSION_WPA2;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_CIPHER_PAIRWISE:
+            if (ar->arPairwiseCrypto == NONE_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_NONE;
+            } else if (ar->arPairwiseCrypto == WEP_CRYPT) {
+                if (ar->arPairwiseCryptoLen == 13) {
+                    data->value |= IW_AUTH_CIPHER_WEP104;
+                } else {
+                    data->value |= IW_AUTH_CIPHER_WEP40;
+                }
+            } else if (ar->arPairwiseCrypto == TKIP_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_TKIP;
+            } else if (ar->arPairwiseCrypto == AES_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_CCMP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_CIPHER_GROUP:
+            if (ar->arGroupCrypto == NONE_CRYPT) {
+                    data->value |= IW_AUTH_CIPHER_NONE;
+            } else if (ar->arGroupCrypto == WEP_CRYPT) {
+                if (ar->arGroupCryptoLen == 13) {
+                    data->value |= IW_AUTH_CIPHER_WEP104;
+                } else {
+                    data->value |= IW_AUTH_CIPHER_WEP40;
+                }
+            } else if (ar->arGroupCrypto == TKIP_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_TKIP;
+            } else if (ar->arGroupCrypto == AES_CRYPT) {
+                data->value |= IW_AUTH_CIPHER_CCMP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_KEY_MGMT:
+            if ((ar->arAuthMode == WPA_PSK_AUTH) ||
+                (ar->arAuthMode == WPA2_PSK_AUTH)) {
+                data->value |= IW_AUTH_KEY_MGMT_PSK;
+            } else if ((ar->arAuthMode == WPA_AUTH) ||
+                       (ar->arAuthMode == WPA2_AUTH)) {
+                data->value |= IW_AUTH_KEY_MGMT_802_1X;
+            }
+            break;
+        case IW_AUTH_TKIP_COUNTERMEASURES:
+            // TODO. Save countermeassure enable/disable
+            data->value = 0;
+            break;
+        case IW_AUTH_DROP_UNENCRYPTED:
+            break;
+        case IW_AUTH_80211_AUTH_ALG:
+            if (ar->arDot11AuthMode == OPEN_AUTH) {
+                data->value |= IW_AUTH_ALG_OPEN_SYSTEM;
+            } else if (ar->arDot11AuthMode == SHARED_AUTH) {
+                data->value |= IW_AUTH_ALG_SHARED_KEY;
+            } else if (ar->arDot11AuthMode == LEAP_AUTH) {
+                data->value |= IW_AUTH_ALG_LEAP;
+            } else {
+                ret = -1;
+            }
+            break;
+        case IW_AUTH_WPA_ENABLED:
+            if (ar->arAuthMode == NONE_AUTH) {
+                data->value = 0;
+            } else {
+                data->value = 1;
+            }
+            break;
+        case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+            break;
+        case IW_AUTH_ROAMING_CONTROL:
+            break;
+        case IW_AUTH_PRIVACY_INVOKED:
+            if (ar->arPairwiseCrypto == NONE_CRYPT) {
+                data->value = 0;
+            } else {
+                data->value = 1;
+            }
+            break;
+#ifdef WAPI_ENABLE
+        case IW_AUTH_WAPI_ENABLED:
+            data->value = ar->arWapiEnable;
+            break;
+#endif
+        default:
+           ret = -1;
+           break;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCSIWPMKSA
+ */
+static int
+ar6000_ioctl_siwpmksa(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_INT32 ret;
+    A_STATUS status;
+    struct iw_pmksa *pmksa;
+
+    pmksa = (struct iw_pmksa *)extra;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    ret = 0;
+    status = A_OK;
+
+    switch (pmksa->cmd) {
+        case IW_PMKSA_ADD:
+            status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, TRUE);
+            break;
+        case IW_PMKSA_REMOVE:
+            status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, FALSE);
+            break;
+        case IW_PMKSA_FLUSH:
+            if (ar->arConnected == TRUE) {
+                status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+            }
+            break;
+        default:
+            ret=-1;
+            break;
+    }
+    if (status != A_OK) {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+#ifdef WAPI_ENABLE
+
+#define PN_INIT 0x5c365c36
+
+static int ar6000_set_wapi_key(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
+    KEY_USAGE   keyUsage = 0;
+    A_INT32     keyLen;
+    A_UINT8     *keyData;
+    A_INT32     index;
+    A_UINT32    *PN;
+    A_INT32     i;
+    A_STATUS    status;
+    A_UINT8     wapiKeyRsc[16];
+    CRYPTO_TYPE keyType = WAPI_CRYPT;
+    const A_UINT8 broadcastMac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+    index = erq->flags & IW_ENCODE_INDEX;
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                ((index - 1) > WMI_MAX_KEY_INDEX))) {
+        return -EIO;
+    }
+
+    index--;
+    if (index < 0 || index > 4) {
+        return -EIO;
+    }
+    keyData = (A_UINT8 *)(ext + 1);
+    keyLen = erq->length - sizeof(struct iw_encode_ext);
+    A_MEMCPY(wapiKeyRsc, ext->tx_seq, sizeof(wapiKeyRsc));
+
+    if (A_MEMCMP(ext->addr.sa_data, broadcastMac, sizeof(broadcastMac)) == 0) {
+        keyUsage |= GROUP_USAGE;
+        PN = (A_UINT32 *)wapiKeyRsc;
+        for (i = 0; i < 4; i++) {
+            PN[i] = PN_INIT;
+        }
+    } else {
+        keyUsage |= PAIRWISE_USAGE;
+    }
+    status = wmi_addKey_cmd(ar->arWmi,
+                            index,
+                            keyType,
+                            keyUsage,
+                            keyLen,
+                            wapiKeyRsc,
+                            keyData,
+                            KEY_OP_INIT_WAPIPN,
+                            NULL,
+                            SYNC_BEFORE_WMIFLAG);
+    if (A_OK != status) {
+        return -EIO;
+    }
+    return 0;
+}
+
+#endif
+
+/*
+ * SIOCSIWENCODEEXT
+ */
+static int
+ar6000_ioctl_siwencodeext(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    A_INT32 index;
+    struct iw_encode_ext *ext;
+    KEY_USAGE keyUsage;
+    A_INT32 keyLen;
+    A_UINT8 *keyData;
+    A_UINT8 keyRsc[8];
+    A_STATUS status;
+    CRYPTO_TYPE keyType;
+#ifdef USER_KEYS
+    struct ieee80211req_key ik;
+#endif /* USER_KEYS */
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+#ifdef USER_KEYS
+    ar->user_saved_keys.keyOk = FALSE;
+#endif /* USER_KEYS */
+
+    index = erq->flags & IW_ENCODE_INDEX;
+
+    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+                  ((index - 1) > WMI_MAX_KEY_INDEX)))
+    {
+        return -EIO;
+    }
+
+    ext = (struct iw_encode_ext *)extra;
+    if (erq->flags & IW_ENCODE_DISABLED) {
+        /*
+         * Encryption disabled
+         */
+        if (index) {
+            /*
+             * If key index was specified then clear the specified key
+             */
+            index--;
+            A_MEMZERO(ar->arWepKeyList[index].arKey,
+                      sizeof(ar->arWepKeyList[index].arKey));
+            ar->arWepKeyList[index].arKeyLen = 0;
+        }
+    } else {
+        /*
+         * Enabling WEP encryption
+         */
+        if (index) {
+            index--;                /* keyindex is off base 1 in iwconfig */
+        }
+
+        keyUsage = 0;
+        keyLen = erq->length - sizeof(struct iw_encode_ext);
+
+        if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
+            keyUsage = TX_USAGE;
+            ar->arDefTxKeyIndex = index;
+            // Just setting the key index
+            if (keyLen == 0) {
+                return 0;
+            }
+        }
+
+        if (keyLen <= 0) {
+            return -EIO;
+        }
+
+        /* key follows iw_encode_ext */
+        keyData = (A_UINT8 *)(ext + 1);
+
+        switch (ext->alg) {
+            case IW_ENCODE_ALG_WEP:
+                keyType = WEP_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_WEP;
+#endif /* USER_KEYS */
+                if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) {
+                    return -EIO;
+                }
+
+                /* Check whether it is static wep. */
+                if (!ar->arConnected) {
+                    A_MEMZERO(ar->arWepKeyList[index].arKey,
+                          sizeof(ar->arWepKeyList[index].arKey));
+                    A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen);
+                    ar->arWepKeyList[index].arKeyLen = keyLen;
+
+                    return 0;
+                }
+                break;
+            case IW_ENCODE_ALG_TKIP:
+                keyType = TKIP_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_TKIP;
+#endif /* USER_KEYS */
+                break;
+            case IW_ENCODE_ALG_CCMP:
+                keyType = AES_CRYPT;
+#ifdef USER_KEYS
+                ik.ik_type = IEEE80211_CIPHER_AES_CCM;
+#endif /* USER_KEYS */
+                break;
+#ifdef WAPI_ENABLE
+            case IW_ENCODE_ALG_SM4:
+                if (ar->arWapiEnable) {
+                    return ar6000_set_wapi_key(dev, info, erq, extra);
+                } else {
+                    return -EIO;
+                }
+#endif
+            case IW_ENCODE_ALG_PMK:
+                ar->arConnectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD;
+                return wmi_set_pmk_cmd(ar->arWmi, keyData);
+            default:
+                return -EIO;
+        }
+
+
+        if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+            keyUsage |= GROUP_USAGE;
+        } else {
+            keyUsage |= PAIRWISE_USAGE;
+        }
+
+        if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
+            A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc));
+        } else {
+            A_MEMZERO(keyRsc, sizeof(keyRsc));
+        }
+
+        if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+            (GROUP_USAGE & keyUsage))
+        {
+            A_UNTIMEOUT(&ar->disconnect_timer);
+        }
+
+         status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage,
+                            keyLen, keyRsc,
+                            keyData, KEY_OP_INIT_VAL,
+                            (A_UINT8*)ext->addr.sa_data,
+                            SYNC_BOTH_WMIFLAG);
+         if (status != A_OK) {
+            return -EIO;
+         }
+
+#ifdef USER_KEYS
+        ik.ik_keyix = index;
+        ik.ik_keylen = keyLen;
+        memcpy(ik.ik_keydata, keyData, keyLen);
+        memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc));
+        memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
+        if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+            memcpy(&ar->user_saved_keys.bcast_ik, &ik,
+                       sizeof(struct ieee80211req_key));
+        } else {
+            memcpy(&ar->user_saved_keys.ucast_ik, &ik,
+                      sizeof(struct ieee80211req_key));
+        }
+        ar->user_saved_keys.keyOk = TRUE;
+#endif /* USER_KEYS */
+    }
+
+
+    return 0;
+}
+
+/*
+ * SIOCGIWENCODEEXT
+ */
+static int
+ar6000_ioctl_giwencodeext(struct net_device *dev,
+              struct iw_request_info *info,
+              struct iw_point *erq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arPairwiseCrypto == NONE_CRYPT) {
+        erq->length = 0;
+        erq->flags = IW_ENCODE_DISABLED;
+    } else {
+        erq->length = 0;
+    }
+
+    return 0;
+}
+#endif // WIRELESS_EXT >= 18
+
+#if WIRELESS_EXT > 20
+static int ar6000_ioctl_siwpower(struct net_device *dev,
+                 struct iw_request_info *info,
+                 union iwreq_data *wrqu, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE power_mode;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (wrqu->power.disabled)
+        power_mode = MAX_PERF_POWER;
+    else
+        power_mode = REC_POWER;
+
+    if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
+        return -EIO;
+    return 0;
+}
+
+static int ar6000_ioctl_giwpower(struct net_device *dev,
+                 struct iw_request_info *info,
+                 union iwreq_data *wrqu, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    WMI_POWER_MODE power_mode;
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    power_mode = wmi_get_power_mode_cmd(ar->arWmi);
+
+    if (power_mode == MAX_PERF_POWER)
+        wrqu->power.disabled = 1;
+    else
+        wrqu->power.disabled = 0;
+
+    return 0;
+}
+#endif // WIRELESS_EXT > 20
+
+/*
+ * SIOCGIWNAME
+ */
+int
+ar6000_ioctl_giwname(struct net_device *dev,
+           struct iw_request_info *info,
+           char *name, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    switch (ar->arPhyCapability) {
+    case (WMI_11A_CAPABILITY):
+        strncpy(name, "AR6000 802.11a", IFNAMSIZ);
+        break;
+    case (WMI_11G_CAPABILITY):
+        strncpy(name, "AR6000 802.11g", IFNAMSIZ);
+        break;
+    case (WMI_11AG_CAPABILITY):
+        strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
+        break;
+    case (WMI_11NA_CAPABILITY):
+        strncpy(name, "AR6000 802.11na", IFNAMSIZ);
+        break;
+    case (WMI_11NG_CAPABILITY):
+        strncpy(name, "AR6000 802.11ng", IFNAMSIZ);
+        break;
+    case (WMI_11NAG_CAPABILITY):
+        strncpy(name, "AR6000 802.11nag", IFNAMSIZ);
+        break;
+    default:
+        strncpy(name, "AR6000 802.11", IFNAMSIZ);
+        break;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCSIWFREQ
+ */
+int
+ar6000_ioctl_siwfreq(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_freq *freq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    /*
+     * We support limiting the channels via wmiconfig.
+     *
+     * We use this command to configure the channel hint for the connect cmd
+     * so it is possible the target will end up connecting to a different
+     * channel.
+     */
+    if (freq->e > 1) {
+        return -EINVAL;
+    } else if (freq->e == 1) {
+        ar->arChannelHint = freq->m / 100000;
+    } else {
+        if(freq->m) {
+            ar->arChannelHint = wlan_ieee2freq(freq->m);
+        } else {
+            /* Auto Channel Selection */
+            ar->arChannelHint = 0;
+        }
+    }
+
+    ar->ap_profile_flag = 1; /* There is a change in profile */
+
+    A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
+    return 0;
+}
+
+/*
+ * SIOCGIWFREQ
+ */
+int
+ar6000_ioctl_giwfreq(struct net_device *dev,
+                struct iw_request_info *info,
+                struct iw_freq *freq, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arNetworkType == AP_NETWORK) {
+        if(ar->arChannelHint) {
+            freq->m = ar->arChannelHint * 100000;
+        } else if(ar->arACS) {
+            freq->m = ar->arACS * 100000;
+        } else {
+            return -EINVAL;
+        }
+    } else {
+        if (ar->arConnected != TRUE) {
+            return -EINVAL;
+        } else {
+            freq->m = ar->arBssChannel * 100000;
+        }
+    }
+
+    freq->e = 1;
+
+    return 0;
+}
+
+/*
+ * SIOCSIWMODE
+ */
+int
+ar6000_ioctl_siwmode(struct net_device *dev,
+            struct iw_request_info *info,
+            __u32 *mode, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    /*
+     * clear SSID during mode switch in connected state
+     */
+    if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == TRUE) ){
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    switch (*mode) {
+    case IW_MODE_INFRA:
+        ar->arNextMode = INFRA_NETWORK;
+        break;
+    case IW_MODE_ADHOC:
+        ar->arNextMode = ADHOC_NETWORK;
+        break;
+    case IW_MODE_MASTER:
+        ar->arNextMode = AP_NETWORK;
+        break;
+    default:
+        return -EINVAL;
+    }
+
+    /* clear all shared parameters between AP and STA|IBSS modes when we
+     * switch between them. Switch between STA & IBSS modes does'nt clear
+     * the shared profile. This is as per the original design for switching
+     * between STA & IBSS.
+     */
+    if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) {
+        ar->arDot11AuthMode      = OPEN_AUTH;
+        ar->arAuthMode           = NONE_AUTH;
+        ar->arPairwiseCrypto     = NONE_CRYPT;
+        ar->arPairwiseCryptoLen  = 0;
+        ar->arGroupCrypto        = NONE_CRYPT;
+        ar->arGroupCryptoLen     = 0;
+        ar->arChannelHint        = 0;
+        ar->arBssChannel         = 0;
+        A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    /* SSID has to be cleared to trigger a profile change while switching
+     * between STA & IBSS modes having the same SSID
+     */
+    if (ar->arNetworkType != ar->arNextMode) {
+        A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+        ar->arSsidLen = 0;
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCGIWMODE
+ */
+int
+ar6000_ioctl_giwmode(struct net_device *dev,
+            struct iw_request_info *info,
+            __u32 *mode, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    switch (ar->arNetworkType) {
+    case INFRA_NETWORK:
+        *mode = IW_MODE_INFRA;
+        break;
+    case ADHOC_NETWORK:
+        *mode = IW_MODE_ADHOC;
+        break;
+    case AP_NETWORK:
+        *mode = IW_MODE_MASTER;
+        break;
+    default:
+        return -EIO;
+    }
+    return 0;
+}
+
+/*
+ * SIOCSIWSENS
+ */
+int
+ar6000_ioctl_siwsens(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *sens, char *extra)
+{
+    return 0;
+}
+
+/*
+ * SIOCGIWSENS
+ */
+int
+ar6000_ioctl_giwsens(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_param *sens, char *extra)
+{
+    sens->value = 0;
+    sens->fixed = 1;
+
+    return 0;
+}
+
+/*
+ * SIOCGIWRANGE
+ */
+int
+ar6000_ioctl_giwrange(struct net_device *dev,
+             struct iw_request_info *info,
+             struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    struct iw_range *range = (struct iw_range *) extra;
+    int i, ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        up(&ar->arSem);
+        return -EBUSY;
+    }
+
+    ar->arNumChannels = -1;
+    A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
+
+    if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
+        up(&ar->arSem);
+        return -EIO;
+    }
+
+    wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
+
+    if (signal_pending(current)) {
+        up(&ar->arSem);
+        return -EINTR;
+    }
+
+    data->length = sizeof(struct iw_range);
+    A_MEMZERO(range, sizeof(struct iw_range));
+
+    range->txpower_capa = 0;
+
+    range->min_pmp = 1 * 1024;
+    range->max_pmp = 65535 * 1024;
+    range->min_pmt = 1 * 1024;
+    range->max_pmt = 1000 * 1024;
+    range->pmp_flags = IW_POWER_PERIOD;
+    range->pmt_flags = IW_POWER_TIMEOUT;
+    range->pm_capa = 0;
+
+    range->we_version_compiled = WIRELESS_EXT;
+    range->we_version_source = 13;
+
+    range->retry_capa = IW_RETRY_LIMIT;
+    range->retry_flags = IW_RETRY_LIMIT;
+    range->min_retry = 0;
+    range->max_retry = 255;
+
+    range->num_frequency = range->num_channels = ar->arNumChannels;
+    for (i = 0; i < ar->arNumChannels; i++) {
+        range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
+        range->freq[i].m = ar->arChannelList[i] * 100000;
+        range->freq[i].e = 1;
+         /*
+         * Linux supports max of 32 channels, bail out once you
+         * reach the max.
+         */
+        if (i == IW_MAX_FREQUENCIES) {
+            break;
+        }
+    }
+
+    /* Max quality is max field value minus noise floor */
+    range->max_qual.qual  = 0xff - 161;
+
+    /*
+     * In order to use dBm measurements, 'level' must be lower
+     * than any possible measurement (see iw_print_stats() in
+     * wireless tools).  It's unclear how this is meant to be
+     * done, but setting zero in these values forces dBm and
+     * the actual numbers are not used.
+     */
+    range->max_qual.level = 0;
+    range->max_qual.noise = 0;
+
+    range->sensitivity = 3;
+
+    range->max_encoding_tokens = 4;
+    /* XXX query driver to find out supported key sizes */
+    range->num_encoding_sizes = 3;
+    range->encoding_size[0] = 5;        /* 40-bit */
+    range->encoding_size[1] = 13;       /* 104-bit */
+    range->encoding_size[2] = 16;       /* 128-bit */
+
+    range->num_bitrates = 0;
+
+    /* estimated maximum TCP throughput values (bps) */
+    range->throughput = 22000000;
+
+    range->min_rts = 0;
+    range->max_rts = 2347;
+    range->min_frag = 256;
+    range->max_frag = 2346;
+
+    up(&ar->arSem);
+
+    return ret;
+}
+
+
+/*
+ * SIOCSIWAP
+ * This ioctl is used to set the desired bssid for the connect command.
+ */
+int
+ar6000_ioctl_siwap(struct net_device *dev,
+              struct iw_request_info *info,
+              struct sockaddr *ap_addr, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ap_addr->sa_family != ARPHRD_ETHER) {
+        return -EIO;
+    }
+
+    if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
+        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+    } else {
+        A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data,  sizeof(ar->arReqBssid));
+    }
+
+    return 0;
+}
+
+/*
+ * SIOCGIWAP
+ */
+int
+ar6000_ioctl_giwap(struct net_device *dev,
+              struct iw_request_info *info,
+              struct sockaddr *ap_addr, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arNetworkType == AP_NETWORK) {
+        A_MEMCPY(&ap_addr->sa_data, dev->dev_addr, ATH_MAC_LEN);
+        ap_addr->sa_family = ARPHRD_ETHER;
+        return 0;
+    }
+
+    if (ar->arConnected != TRUE) {
+        return -EINVAL;
+    }
+
+    A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
+    ap_addr->sa_family = ARPHRD_ETHER;
+
+    return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+/*
+ * SIOCSIWMLME
+ */
+int
+ar6000_ioctl_siwmlme(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->bIsDestroyProgress) {
+        return -EBUSY;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (down_interruptible(&ar->arSem)) {
+        return -ERESTARTSYS;
+    }
+
+    if (data->pointer && data->length == sizeof(struct iw_mlme)) {
+
+        A_UINT8 arNetworkType;
+        struct iw_mlme mlme;
+
+        if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme)))
+            return -EIO;
+
+        switch (mlme.cmd) {
+
+            case IW_MLME_DEAUTH:
+                /* fall through */
+            case IW_MLME_DISASSOC:
+                if ((ar->arConnected != TRUE) ||
+                    (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) {
+
+                    up(&ar->arSem);
+                    return -EINVAL;
+                }
+                wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+                arNetworkType = ar->arNetworkType;
+                ar6000_init_profile_info(ar);
+                ar->arNetworkType = arNetworkType;
+                reconnect_flag = 0;
+                wmi_disconnect_cmd(ar->arWmi);
+                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+                ar->arSsidLen = 0;
+                if (ar->arSkipScan == FALSE) {
+                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+                }
+                break;
+
+            case IW_MLME_AUTH:
+                /* fall through */
+            case IW_MLME_ASSOC:
+                /* fall through */
+            default:
+                up(&ar->arSem);
+                return -EOPNOTSUPP;
+        }
+    }
+
+    up(&ar->arSem);
+    return 0;
+}
+#endif /* LINUX_VERSION_CODE */
+
+/*
+ * SIOCGIWAPLIST
+ */
+int
+ar6000_ioctl_iwaplist(struct net_device *dev,
+            struct iw_request_info *info,
+            struct iw_point *data, char *extra)
+{
+    return -EIO;            /* for now */
+}
+
+/*
+ * SIOCSIWSCAN
+ */
+int
+ar6000_ioctl_siwscan(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *extra)
+{
+#define ACT_DWELLTIME_DEFAULT   105
+#define HOME_TXDRAIN_TIME       100
+#define SCAN_INT                HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+    int ret = 0;
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    if (!ar->arUserBssFilter) {
+        if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+            return -EIO;
+        }
+    }
+
+    if (ar->arConnected) {
+        if  (wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+            return -EIO;
+        }
+    }
+
+#ifdef ANDROID_ENV
+#if WIRELESS_EXT >= 18
+    if (data->pointer && (data->length == sizeof(struct iw_scan_req)))
+    {
+        if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID)
+        {
+            struct iw_scan_req req;
+            if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req)))
+                return -EIO;
+            if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK)
+                return -EIO;
+        }
+        else
+        {
+            if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+                return -EIO;
+        }
+    }
+    else
+    {
+        if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+            return -EIO;
+    }
+#endif
+#endif /* ANDROID_ENV */
+
+    if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
+                          0, 0, 0, NULL) != A_OK) {
+        ret = -EIO;
+    }
+
+    if (ret == 0) {
+        ar->scan_complete = 0;
+    }
+
+    return ret;
+#undef  ACT_DWELLTIME_DEFAULT
+#undef HOME_TXDRAIN_TIME
+#undef SCAN_INT
+}
+
+
+/*
+ * Units are in db above the noise floor. That means the
+ * rssi values reported in the tx/rx descriptors in the
+ * driver are the SNR expressed in db.
+ *
+ * If you assume that the noise floor is -95, which is an
+ * excellent assumption 99.5 % of the time, then you can
+ * derive the absolute signal level (i.e. -95 + rssi).
+ * There are some other slight factors to take into account
+ * depending on whether the rssi measurement is from 11b,
+ * 11g, or 11a.   These differences are at most 2db and
+ * can be documented.
+ *
+ * NB: various calculations are based on the orinoco/wavelan
+ *     drivers for compatibility
+ */
+static void
+ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
+{
+    if (rssi < 0) {
+        iq->qual = 0;
+    } else {
+        iq->qual = rssi;
+    }
+
+    /* NB: max is 94 because noise is hardcoded to 161 */
+    if (iq->qual > 94)
+        iq->qual = 94;
+
+    iq->noise = 161;        /* -95dBm */
+    iq->level = iq->noise + iq->qual;
+    iq->updated = 7;
+}
+
+
+int
+ar6000_ioctl_siwcommit(struct net_device *dev,
+                     struct iw_request_info *info,
+                     struct iw_point *data, char *extra)
+{
+    AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+    if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+        A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+        return -EOPNOTSUPP;
+    }
+
+    if (ar->arWmiReady == FALSE) {
+        return -EIO;
+    }
+
+    if (ar->arWlanState == WLAN_DISABLED) {
+        return -EIO;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AP: SSID %s freq %d authmode %d dot11 auth %d"\
+                    " PW crypto %d GRP crypto %d\n",
+                    ar->arSsid, ar->arChannelHint,
+                    ar->arAuthMode, ar->arDot11AuthMode,
+                    ar->arPairwiseCrypto, ar->arGroupCrypto));
+
+    ar6000_ap_mode_profile_commit(ar);
+
+    /* if there is a profile switch from STA|IBSS mode to AP mode,
+     * update the host driver association state for the STA|IBSS mode.
+     */
+    if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) {
+        ar->arConnectPending = FALSE;
+        ar->arConnected = FALSE;
+        /* Stop getting pkts from upper stack */
+        netif_stop_queue(ar->arNetDev);
+        A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+        ar->arBssChannel = 0;
+        ar->arBeaconInterval = 0;
+
+        /* Flush the Tx queues */
+        ar6000_TxDataCleanup(ar);
+
+        /* Start getting pkts from upper stack */
+        netif_wake_queue(ar->arNetDev);
+    }
+
+    return 0;
+}
+
+/* Structures to export the Wireless Handlers */
+static const iw_handler ath_handlers[] = {
+    (iw_handler) ar6000_ioctl_siwcommit,        /* SIOCSIWCOMMIT */
+    (iw_handler) ar6000_ioctl_giwname,          /* SIOCGIWNAME */
+    (iw_handler) NULL,                          /* SIOCSIWNWID */
+    (iw_handler) NULL,                          /* SIOCGIWNWID */
+    (iw_handler) ar6000_ioctl_siwfreq,          /* SIOCSIWFREQ */
+    (iw_handler) ar6000_ioctl_giwfreq,          /* SIOCGIWFREQ */
+    (iw_handler) ar6000_ioctl_siwmode,          /* SIOCSIWMODE */
+    (iw_handler) ar6000_ioctl_giwmode,          /* SIOCGIWMODE */
+    (iw_handler) ar6000_ioctl_siwsens,          /* SIOCSIWSENS */
+    (iw_handler) ar6000_ioctl_giwsens,          /* SIOCGIWSENS */
+    (iw_handler) NULL /* not _used */,          /* SIOCSIWRANGE */
+    (iw_handler) ar6000_ioctl_giwrange,         /* SIOCGIWRANGE */
+    (iw_handler) NULL /* not used */,           /* SIOCSIWPRIV */
+    (iw_handler) NULL /* kernel code */,        /* SIOCGIWPRIV */
+    (iw_handler) NULL /* not used */,           /* SIOCSIWSTATS */
+    (iw_handler) NULL /* kernel code */,        /* SIOCGIWSTATS */
+    (iw_handler) NULL,                          /* SIOCSIWSPY */
+    (iw_handler) NULL,                          /* SIOCGIWSPY */
+    (iw_handler) NULL,                          /* SIOCSIWTHRSPY */
+    (iw_handler) NULL,                          /* SIOCGIWTHRSPY */
+    (iw_handler) ar6000_ioctl_siwap,            /* SIOCSIWAP */
+    (iw_handler) ar6000_ioctl_giwap,            /* SIOCGIWAP */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+    (iw_handler) ar6000_ioctl_siwmlme,          /* SIOCSIWMLME */
+#else
+    (iw_handler) NULL,                          /* -- hole -- */
+#endif  /* LINUX_VERSION_CODE */
+    (iw_handler) ar6000_ioctl_iwaplist,         /* SIOCGIWAPLIST */
+    (iw_handler) ar6000_ioctl_siwscan,          /* SIOCSIWSCAN */
+    (iw_handler) ar6000_ioctl_giwscan,          /* SIOCGIWSCAN */
+    (iw_handler) ar6000_ioctl_siwessid,         /* SIOCSIWESSID */
+    (iw_handler) ar6000_ioctl_giwessid,         /* SIOCGIWESSID */
+    (iw_handler) NULL,                          /* SIOCSIWNICKN */
+    (iw_handler) NULL,                          /* SIOCGIWNICKN */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) ar6000_ioctl_siwrate,          /* SIOCSIWRATE */
+    (iw_handler) ar6000_ioctl_giwrate,          /* SIOCGIWRATE */
+    (iw_handler) NULL,                          /* SIOCSIWRTS */
+    (iw_handler) NULL,                          /* SIOCGIWRTS */
+    (iw_handler) NULL,                          /* SIOCSIWFRAG */
+    (iw_handler) NULL,                          /* SIOCGIWFRAG */
+    (iw_handler) ar6000_ioctl_siwtxpow,         /* SIOCSIWTXPOW */
+    (iw_handler) ar6000_ioctl_giwtxpow,         /* SIOCGIWTXPOW */
+    (iw_handler) ar6000_ioctl_siwretry,         /* SIOCSIWRETRY */
+    (iw_handler) ar6000_ioctl_giwretry,         /* SIOCGIWRETRY */
+    (iw_handler) ar6000_ioctl_siwencode,        /* SIOCSIWENCODE */
+    (iw_handler) ar6000_ioctl_giwencode,        /* SIOCGIWENCODE */
+#if WIRELESS_EXT > 20
+    (iw_handler) ar6000_ioctl_siwpower,         /* SIOCSIWPOWER */
+    (iw_handler) ar6000_ioctl_giwpower,         /* SIOCGIWPOWER */
+#endif // WIRELESS_EXT > 20
+#if WIRELESS_EXT >= 18
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) NULL,                          /* -- hole -- */
+    (iw_handler) ar6000_ioctl_siwgenie,         /* SIOCSIWGENIE */
+    (iw_handler) ar6000_ioctl_giwgenie,         /* SIOCGIWGENIE */
+    (iw_handler) ar6000_ioctl_siwauth,          /* SIOCSIWAUTH */
+    (iw_handler) ar6000_ioctl_giwauth,          /* SIOCGIWAUTH */
+    (iw_handler) ar6000_ioctl_siwencodeext,     /* SIOCSIWENCODEEXT */
+    (iw_handler) ar6000_ioctl_giwencodeext,     /* SIOCGIWENCODEEXT */
+    (iw_handler) ar6000_ioctl_siwpmksa,         /* SIOCSIWPMKSA */
+#endif // WIRELESS_EXT >= 18
+};
+
+struct iw_handler_def ath_iw_handler_def = {
+    .standard         = (iw_handler *)ath_handlers,
+    .num_standard     = ARRAY_SIZE(ath_handlers),
+    .private          = NULL,
+    .num_private      = 0,
+};
diff --git a/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h
new file mode 100644
index 000000000000..567a3ff185ca
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h
@@ -0,0 +1,112 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RX_INTERNAL_H__
+#define __AGGR_RX_INTERNAL_H__
+
+#include "a_osapi.h"
+#include "aggr_recv_api.h"
+
+#define AGGR_WIN_IDX(x, y)          ((x) % (y))
+#define AGGR_INCR_IDX(x, y)         AGGR_WIN_IDX(((x)+1), (y))
+#define AGGR_DCRM_IDX(x, y)         AGGR_WIN_IDX(((x)-1), (y))
+#define IEEE80211_MAX_SEQ_NO        0xFFF
+#define IEEE80211_NEXT_SEQ_NO(x)    (((x) + 1) & IEEE80211_MAX_SEQ_NO)
+
+
+#define NUM_OF_TIDS         8
+#define AGGR_SZ_DEFAULT     8
+
+#define AGGR_WIN_SZ_MIN     2
+#define AGGR_WIN_SZ_MAX     8
+/* TID Window sz is double of what is negotiated. Derive TID_WINDOW_SZ from win_sz, per tid */
+#define TID_WINDOW_SZ(_x)   ((_x) << 1)
+
+#define AGGR_NUM_OF_FREE_NETBUFS    16
+
+#define AGGR_GET_RXTID_STATS(_p, _x)    (&(_p->stat[(_x)]))
+#define AGGR_GET_RXTID(_p, _x)    (&(_p->RxTid[(_x)]))
+
+/* Hold q is a function of win_sz, which is negotiated per tid */
+#define HOLD_Q_SZ(_x)   (TID_WINDOW_SZ((_x))*sizeof(OSBUF_HOLD_Q))
+/* AGGR_RX_TIMEOUT value is important as a (too) small value can cause frames to be 
+ * delivered out of order and a (too) large value can cause undesirable latency in
+ * certain situations. */
+#define AGGR_RX_TIMEOUT     400  /* Timeout(in ms) for delivery of frames, if they are stuck */
+
+typedef enum {
+    ALL_SEQNO = 0,
+    CONTIGUOUS_SEQNO = 1,
+}DELIVERY_ORDER;
+
+typedef struct {
+    void        *osbuf;
+    A_BOOL      is_amsdu;
+    A_UINT16    seq_no;
+}OSBUF_HOLD_Q;
+
+
+#if 0
+typedef struct {
+    A_UINT16    seqno_st;
+    A_UINT16    seqno_end;
+}WINDOW_SNAPSHOT;
+#endif
+
+typedef struct {
+    A_BOOL              aggr;       /* is it ON or OFF */
+    A_BOOL              progress;   /* TRUE when frames have arrived after a timer start */
+    A_BOOL              timerMon;   /* TRUE if the timer started for the sake of this TID */
+    A_UINT16            win_sz;     /* negotiated window size */
+    A_UINT16            seq_next;   /* Next seq no, in current window */
+    A_UINT32            hold_q_sz;  /* Num of frames that can be held in hold q */
+    OSBUF_HOLD_Q        *hold_q;    /* Hold q for re-order */
+#if 0    
+    WINDOW_SNAPSHOT     old_win;    /* Sliding window snapshot - for timeout */
+#endif    
+    A_NETBUF_QUEUE_T    q;          /* q head for enqueuing frames for dispatch */
+    A_MUTEX_T           lock;
+}RXTID;
+
+typedef struct {
+    A_UINT32    num_into_aggr;      /* hitting at the input of this module */
+    A_UINT32    num_dups;           /* duplicate */
+    A_UINT32    num_oow;            /* out of window */
+    A_UINT32    num_mpdu;           /* single payload 802.3/802.11 frame */
+    A_UINT32    num_amsdu;          /* AMSDU */
+    A_UINT32    num_delivered;      /* frames delivered to IP stack */
+    A_UINT32    num_timeouts;       /* num of timeouts, during which frames delivered */
+    A_UINT32    num_hole;           /* frame not present, when window moved over */
+    A_UINT32    num_bar;            /* num of resets of seq_num, via BAR */
+}RXTID_STATS;
+
+typedef struct {
+    A_UINT8             aggr_sz;            /* config value of aggregation size */    
+    A_UINT8             timerScheduled;
+    A_TIMER             timer;              /* timer for returning held up pkts in re-order que */    
+    void                *dev;               /* dev handle */
+    RX_CALLBACK         rx_fn;              /* callback function to return frames; to upper layer */
+    RXTID               RxTid[NUM_OF_TIDS]; /* Per tid window */
+    ALLOC_NETBUFS       netbuf_allocator;   /* OS netbuf alloc fn */
+    A_NETBUF_QUEUE_T    freeQ;              /* pre-allocated buffers - for A_MSDU slicing */
+    RXTID_STATS         stat[NUM_OF_TIDS];  /* Tid based statistics */
+    PACKET_LOG          pkt_log;            /* Log info of the packets */
+}AGGR_INFO;
+
+#endif /* __AGGR_RX_INTERNAL_H__ */
diff --git a/drivers/net/wireless/ath6kl/reorder/makefile b/drivers/net/wireless/ath6kl/reorder/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c
new file mode 100644
index 000000000000..3bfba4fbc051
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c
@@ -0,0 +1,662 @@
+/*
+ *
+ * Copyright (c) 2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifdef  ATH_AR6K_11N_SUPPORT
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include <a_debug.h>
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include "aggr_rx_internal.h"
+#include "wmi.h"
+
+extern A_STATUS
+wmi_dot3_2_dix(void *osbuf);
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf);
+
+static void
+aggr_timeout(A_ATH_TIMER arg);
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order);
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q);
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr);
+
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator)
+{
+    AGGR_INFO   *p_aggr = NULL;
+    RXTID *rxtid;
+    A_UINT8 i;
+    A_STATUS status = A_OK;
+
+    A_PRINTF("In aggr_init..\n");
+
+    do {
+        p_aggr = A_MALLOC(sizeof(AGGR_INFO));
+        if(!p_aggr) {
+            A_PRINTF("Failed to allocate memory for aggr_node\n");
+            status = A_ERROR;
+            break;
+        }
+
+        /* Init timer and data structures */
+        A_MEMZERO(p_aggr, sizeof(AGGR_INFO));
+        p_aggr->aggr_sz = AGGR_SZ_DEFAULT;
+        A_INIT_TIMER(&p_aggr->timer, aggr_timeout, p_aggr);
+        p_aggr->timerScheduled = FALSE;
+        A_NETBUF_QUEUE_INIT(&p_aggr->freeQ);
+
+        p_aggr->netbuf_allocator = netbuf_allocator;
+        p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+
+        for(i = 0; i < NUM_OF_TIDS; i++) {
+            rxtid = AGGR_GET_RXTID(p_aggr, i);
+            rxtid->aggr = FALSE;
+            rxtid->progress = FALSE;
+            rxtid->timerMon = FALSE;
+            A_NETBUF_QUEUE_INIT(&rxtid->q);
+            A_MUTEX_INIT(&rxtid->lock);
+        }
+    }while(FALSE);
+
+    A_PRINTF("going out of aggr_init..status %s\n",
+                    (status == A_OK) ? "OK":"Error");
+
+    if(status != A_OK) {
+        /* Cleanup */
+        aggr_module_destroy(p_aggr);
+    }
+    return ((status == A_OK) ? p_aggr : NULL);
+}
+
+/* utility function to clear rx hold_q for a tid */
+static void
+aggr_delete_tid_state(AGGR_INFO *p_aggr, A_UINT8 tid)
+{
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+
+    A_ASSERT(tid < NUM_OF_TIDS && p_aggr);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    if(rxtid->aggr) {
+        aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+    }
+
+    rxtid->aggr = FALSE;
+    rxtid->progress = FALSE;
+    rxtid->timerMon = FALSE;
+    rxtid->win_sz = 0;
+    rxtid->seq_next = 0;
+    rxtid->hold_q_sz = 0;
+
+    if(rxtid->hold_q) {
+        A_FREE(rxtid->hold_q);
+        rxtid->hold_q = NULL;
+    }
+
+    A_MEMZERO(stats, sizeof(RXTID_STATS));
+}
+
+void
+aggr_module_destroy(void *cntxt)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    A_UINT8 i, k;
+    A_PRINTF("%s(): aggr = %p\n",_A_FUNCNAME_, p_aggr);
+    A_ASSERT(p_aggr);
+
+    if(p_aggr) {
+        if(p_aggr->timerScheduled) {
+            A_UNTIMEOUT(&p_aggr->timer);
+            p_aggr->timerScheduled = FALSE;
+        }
+
+        for(i = 0; i < NUM_OF_TIDS; i++) {
+            rxtid = AGGR_GET_RXTID(p_aggr, i);
+            /* Free the hold q contents and hold_q*/
+            if(rxtid->hold_q) {
+                for(k = 0; k< rxtid->hold_q_sz; k++) {
+                    if(rxtid->hold_q[k].osbuf) {
+                        A_NETBUF_FREE(rxtid->hold_q[k].osbuf);
+                    }
+                }
+                A_FREE(rxtid->hold_q);
+            }
+            /* Free the dispatch q contents*/
+            while(A_NETBUF_QUEUE_SIZE(&rxtid->q)) {
+                A_NETBUF_FREE(A_NETBUF_DEQUEUE(&rxtid->q));
+            }
+            if (A_IS_MUTEX_VALID(&rxtid->lock)) {
+                A_MUTEX_DELETE(&rxtid->lock);
+            }
+        }
+        /* free the freeQ and its contents*/
+        while(A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+            A_NETBUF_FREE(A_NETBUF_DEQUEUE(&p_aggr->freeQ));
+        }
+        A_FREE(p_aggr);
+    }
+    A_PRINTF("out aggr_module_destroy\n");
+}
+
+
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+    A_ASSERT(p_aggr && fn && dev);
+
+    p_aggr->rx_fn = fn;
+    p_aggr->dev = dev;
+}
+
+
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+    stats->num_bar++;
+
+    aggr_deque_frms(p_aggr, tid, seq_no, ALL_SEQNO);
+}
+
+
+void
+aggr_recv_addba_req_evt(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    A_PRINTF("%s(): win_sz = %d aggr %d\n", _A_FUNCNAME_, win_sz, rxtid->aggr);
+    if(win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) {
+        A_PRINTF("win_sz %d, tid %d\n", win_sz, tid);
+    }
+
+    if(rxtid->aggr) {
+        /* Just go and  deliver all the frames up from this
+         * queue, as if we got DELBA and re-initialize the queue
+         */
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+
+    rxtid->seq_next = seq_no;
+    /* create these queues, only upon receiving of ADDBA for a
+     * tid, reducing memory requirement
+     */
+    rxtid->hold_q = A_MALLOC(HOLD_Q_SZ(win_sz));
+    if((rxtid->hold_q == NULL)) {
+        A_PRINTF("Failed to allocate memory, tid = %d\n", tid);
+        A_ASSERT(0);
+    }
+    A_MEMZERO(rxtid->hold_q, HOLD_Q_SZ(win_sz));
+
+    /* Update rxtid for the window sz */
+    rxtid->win_sz = win_sz;
+    /* hold_q_sz inicates the depth of holding q - which  is
+     * a factor of win_sz. Compute once, as it will be used often
+     */
+    rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz);
+    /* There should be no frames on q - even when second ADDBA comes in.
+     * If aggr was previously ON on this tid, we would have cleaned up
+     * the q
+     */
+    if(A_NETBUF_QUEUE_SIZE(&rxtid->q) != 0) {
+        A_PRINTF("ERROR: Frames still on queue ?\n");
+        A_ASSERT(0);
+    }
+
+    rxtid->aggr = TRUE;
+}
+
+void
+aggr_recv_delba_req_evt(void *cntxt, A_UINT8 tid)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+
+    A_ASSERT(p_aggr);
+    A_PRINTF("%s(): tid %d\n", _A_FUNCNAME_, tid);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+
+    if(rxtid->aggr) {
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+}
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order)
+{
+    RXTID *rxtid;
+    OSBUF_HOLD_Q *node;
+    A_UINT16 idx, idx_end, seq_end;
+    RXTID_STATS *stats;
+
+    A_ASSERT(p_aggr);
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    /* idx is absolute location for first frame */
+    idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+
+    /* idx_end is typically the last possible frame in the window,
+     * but changes to 'the' seq_no, when BAR comes. If seq_no
+     * is non-zero, we will go up to that and stop.
+     * Note: last seq no in current window will occupy the same
+     * index position as index that is just previous to start.
+     * An imp point : if win_sz is 7, for seq_no space of 4095,
+     * then, there would be holes when sequence wrap around occurs.
+     * Target should judiciously choose the win_sz, based on
+     * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz
+     * 2, 4, 8, 16 win_sz works fine).
+     * We must deque from "idx" to "idx_end", including both.
+     */
+    seq_end = (seq_no) ? seq_no : rxtid->seq_next;
+    idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
+
+    /* Critical section begins */
+    A_MUTEX_LOCK(&rxtid->lock);
+    do {
+
+        node = &rxtid->hold_q[idx];
+
+        if((order == CONTIGUOUS_SEQNO) && (!node->osbuf))
+            break;
+
+        /* chain frames and deliver frames bcos:
+         *  1. either the frames are in order and window is contiguous, OR
+         *  2. we need to deque frames, irrespective of holes
+         */
+        if(node->osbuf) {
+            if(node->is_amsdu) {
+                aggr_slice_amsdu(p_aggr, rxtid, &node->osbuf);
+            } else {
+                A_NETBUF_ENQUEUE(&rxtid->q, node->osbuf);
+            }
+            node->osbuf = NULL;
+        } else {
+            stats->num_hole++;
+        }
+
+        /* window is moving */
+        rxtid->seq_next = IEEE80211_NEXT_SEQ_NO(rxtid->seq_next);
+        idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+    } while(idx != idx_end);
+    /* Critical section ends */
+    A_MUTEX_UNLOCK(&rxtid->lock);
+
+    stats->num_delivered += A_NETBUF_QUEUE_SIZE(&rxtid->q);
+    aggr_dispatch_frames(p_aggr, &rxtid->q);
+}
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr)
+{
+    void *buf = NULL;
+
+    /* Starving for buffers?  get more from OS
+     *  check for low netbuffers( < 1/4 AGGR_NUM_OF_FREE_NETBUFS) :
+     *      re-allocate bufs if so
+     * allocate a free buf from freeQ
+     */
+    if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) {
+        p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+    }
+
+    if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+        buf = A_NETBUF_DEQUEUE(&p_aggr->freeQ);
+    }
+
+    return buf;
+}
+
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf)
+{
+    void *new_buf;
+    A_UINT16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len;
+    A_UINT8 *framep;
+
+    /* Frame format at this point:
+     *  [DIX hdr | 802.3 | 802.3 | ... | 802.3]
+     *
+     * Strip the DIX header.
+     * Iterate through the osbuf and do:
+     *  grab a free netbuf from freeQ
+     *  find the start and end of a frame
+     *  copy it to netbuf(Vista can do better here)
+     *  convert all msdu's(802.3) frames to upper layer format - os routine
+     *      -for now lets convert from 802.3 to dix
+     *  enque this to dispatch q of tid
+     * repeat
+     * free the osbuf - to OS. It's been sliced.
+     */
+
+    mac_hdr_len = sizeof(ATH_MAC_HDR);
+    framep = A_NETBUF_DATA(*osbuf) + mac_hdr_len;
+    amsdu_len = A_NETBUF_LEN(*osbuf) - mac_hdr_len;
+
+    while(amsdu_len > mac_hdr_len) {
+        /* Begin of a 802.3 frame */
+        payload_8023_len = A_BE2CPU16(((ATH_MAC_HDR *)framep)->typeOrLen);
+#define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
+#define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
+        if(payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) {
+            A_PRINTF("802.3 AMSDU frame bound check failed. len %d\n", payload_8023_len);
+            break;
+        }
+        frame_8023_len = payload_8023_len + mac_hdr_len;
+        new_buf = aggr_get_osbuf(p_aggr);
+        if(new_buf == NULL) {
+            A_PRINTF("No buffer available \n");
+            break;
+        }
+
+        A_MEMCPY(A_NETBUF_DATA(new_buf), framep, frame_8023_len);
+        A_NETBUF_PUT(new_buf, frame_8023_len);
+        if (wmi_dot3_2_dix(new_buf) != A_OK) {
+            A_PRINTF("dot3_2_dix err..\n");
+            A_NETBUF_FREE(new_buf);
+            break;
+        }
+
+        A_NETBUF_ENQUEUE(&rxtid->q, new_buf);
+
+        /* Is this the last subframe within this aggregate ? */
+        if ((amsdu_len - frame_8023_len) == 0) {
+            break;
+        }
+
+        /* Add the length of A-MSDU subframe padding bytes -
+         * Round to nearest word.
+         */
+        frame_8023_len = ((frame_8023_len + 3) & ~3);
+
+        framep += frame_8023_len;
+        amsdu_len -= frame_8023_len;
+    }
+
+    A_NETBUF_FREE(*osbuf);
+    *osbuf = NULL;
+}
+
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID *rxtid;
+    RXTID_STATS *stats;
+    A_UINT16 idx, st, cur, end;
+    A_UINT16 *log_idx;
+    OSBUF_HOLD_Q *node;
+    PACKET_LOG *log;
+
+    A_ASSERT(p_aggr);
+    A_ASSERT(tid < NUM_OF_TIDS);
+
+    rxtid = AGGR_GET_RXTID(p_aggr, tid);
+    stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+    stats->num_into_aggr++;
+
+    if(!rxtid->aggr) {
+        if(is_amsdu) {
+            aggr_slice_amsdu(p_aggr, rxtid, osbuf);
+            stats->num_amsdu++;
+            aggr_dispatch_frames(p_aggr, &rxtid->q);
+        }
+        return;
+    }
+
+    /* Check the incoming sequence no, if it's in the window */
+    st = rxtid->seq_next;
+    cur = seq_no;
+    end = (st + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+    /* Log the pkt info for future analysis */
+    log = &p_aggr->pkt_log;
+    log_idx = &log->last_idx;
+    log->info[*log_idx].cur = cur;
+    log->info[*log_idx].st = st;
+    log->info[*log_idx].end = end;
+    *log_idx = IEEE80211_NEXT_SEQ_NO(*log_idx);
+
+    if(((st < end) && (cur < st || cur > end)) ||
+      ((st > end) && (cur > end) && (cur < st))) {
+        /* the cur frame is outside the window. Since we know
+         * our target would not do this without reason it must
+         * be assumed that the window has moved for some valid reason.
+         * Therefore, we dequeue all frames and start fresh.
+         */
+        A_UINT16 extended_end;
+
+        extended_end = (end + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+
+        if(((end < extended_end) && (cur < end || cur > extended_end)) ||
+           ((end > extended_end) && (cur > extended_end) && (cur < end))) {
+            // dequeue all frames in queue and shift window to new frame
+            aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+            //set window start so that new frame is last frame in window
+            if(cur >= rxtid->hold_q_sz-1) {
+                rxtid->seq_next = cur - (rxtid->hold_q_sz-1);
+            }else{
+                rxtid->seq_next = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+            }
+        } else {
+            // dequeue only those frames that are outside the new shifted window
+            if(cur >= rxtid->hold_q_sz-1) {
+                st = cur - (rxtid->hold_q_sz-1);
+            }else{
+                st = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+            }
+
+            aggr_deque_frms(p_aggr, tid, st, ALL_SEQNO);
+        }
+
+        stats->num_oow++;
+    }
+
+    idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz);
+
+    /*enque the frame, in hold_q */
+    node = &rxtid->hold_q[idx];
+
+    A_MUTEX_LOCK(&rxtid->lock);
+    if(node->osbuf) {
+        /* Is the cur frame duplicate or something beyond our
+         * window(hold_q -> which is 2x, already)?
+         * 1. Duplicate is easy - drop incoming frame.
+         * 2. Not falling in current sliding window.
+         *  2a. is the frame_seq_no preceding current tid_seq_no?
+         *      -> drop the frame. perhaps sender did not get our ACK.
+         *         this is taken care of above.
+         *  2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ);
+         *      -> Taken care of it above, by moving window forward.
+         *
+         */
+        A_NETBUF_FREE(node->osbuf);
+        stats->num_dups++;
+    }
+
+    node->osbuf = *osbuf;
+    node->is_amsdu = is_amsdu;
+    node->seq_no = seq_no;
+    if(node->is_amsdu) {
+        stats->num_amsdu++;
+    } else {
+        stats->num_mpdu++;
+    }
+    A_MUTEX_UNLOCK(&rxtid->lock);
+
+    *osbuf = NULL;
+    aggr_deque_frms(p_aggr, tid, 0, CONTIGUOUS_SEQNO);
+
+    if(p_aggr->timerScheduled) {
+        rxtid->progress = TRUE;
+    }else{
+        for(idx=0 ; idx<rxtid->hold_q_sz ; idx++) {
+            if(rxtid->hold_q[idx].osbuf) {
+                /* there is a frame in the queue and no timer so
+                 * start a timer to ensure that the frame doesn't remain
+                 * stuck forever. */
+                p_aggr->timerScheduled = TRUE;
+                A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+                rxtid->progress = FALSE;
+                rxtid->timerMon = TRUE;
+                break;
+            }
+        }
+    }
+}
+
+/*
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ *  hold Q state.  Examples include when a Connect event or disconnect event is
+ *  received.
+ */
+void
+aggr_reset_state(void *cntxt)
+{
+    A_UINT8 tid;
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+    A_ASSERT(p_aggr);
+
+    for(tid=0 ; tid<NUM_OF_TIDS ; tid++) {
+        aggr_delete_tid_state(p_aggr, tid);
+    }
+}
+
+
+static void
+aggr_timeout(A_ATH_TIMER arg)
+{
+    A_UINT8 i,j;
+    AGGR_INFO *p_aggr = (AGGR_INFO *)arg;
+    RXTID   *rxtid;
+    RXTID_STATS *stats;
+    /*
+     * If the q for which the timer was originally started has
+     * not progressed then it is necessary to dequeue all the
+     * contained frames so that they are not held forever.
+     */
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+        stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+
+        if(rxtid->aggr == FALSE ||
+           rxtid->timerMon == FALSE ||
+           rxtid->progress == TRUE) {
+            continue;
+        }
+        // dequeue all frames in for this tid
+        stats->num_timeouts++;
+        A_PRINTF("TO: st %d end %d\n", rxtid->seq_next, ((rxtid->seq_next + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO));
+        aggr_deque_frms(p_aggr, i, 0, ALL_SEQNO);
+    }
+
+    p_aggr->timerScheduled = FALSE;
+    // determine whether a new timer should be started.
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+
+        if(rxtid->aggr == TRUE && rxtid->hold_q) {
+            for(j = 0 ; j < rxtid->hold_q_sz ; j++)
+            {
+                if(rxtid->hold_q[j].osbuf)
+                {
+                    p_aggr->timerScheduled = TRUE;
+                    rxtid->timerMon = TRUE;
+                    rxtid->progress = FALSE;
+                    break;
+                }
+            }
+
+            if(j >= rxtid->hold_q_sz) {
+                rxtid->timerMon = FALSE;
+            }
+        }
+    }
+
+    if(p_aggr->timerScheduled) {
+        /* Rearm the timer*/
+        A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+    }
+
+}
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q)
+{
+    void *osbuf;
+
+    while((osbuf = A_NETBUF_DEQUEUE(q))) {
+        p_aggr->rx_fn(p_aggr->dev, osbuf);
+    }
+}
+
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf)
+{
+    AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+    RXTID   *rxtid;
+    RXTID_STATS *stats;
+    A_UINT8 i;
+
+    *log_buf = &p_aggr->pkt_log;
+    A_PRINTF("\n\n================================================\n");
+    A_PRINTF("tid: num_into_aggr, dups, oow, mpdu, amsdu, delivered, timeouts, holes, bar, seq_next\n");
+    for(i = 0; i < NUM_OF_TIDS; i++) {
+        stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+        rxtid = AGGR_GET_RXTID(p_aggr, i);
+        A_PRINTF("%d: %d %d %d %d %d %d %d %d %d : %d\n", i, stats->num_into_aggr, stats->num_dups,
+                    stats->num_oow, stats->num_mpdu,
+                    stats->num_amsdu, stats->num_delivered, stats->num_timeouts,
+                    stats->num_hole, stats->num_bar,
+                    rxtid->seq_next);
+    }
+    A_PRINTF("================================================\n\n");
+
+}
+
+#endif  /* ATH_AR6K_11N_SUPPORT */
diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h
new file mode 100644
index 000000000000..708b6b044d27
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h
@@ -0,0 +1,397 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _NET80211_IEEE80211_H_
+#define _NET80211_IEEE80211_H_
+
+#include "athstartpack.h"
+
+/*
+ * 802.11 protocol definitions.
+ */
+#define IEEE80211_WEP_KEYLEN        5   /* 40bit */
+#define IEEE80211_WEP_IVLEN         3   /* 24bit */
+#define IEEE80211_WEP_KIDLEN        1   /* 1 octet */
+#define IEEE80211_WEP_CRCLEN        4   /* CRC-32 */
+#define IEEE80211_WEP_NKID          4   /* number of key ids */
+
+/*
+ * 802.11i defines an extended IV for use with non-WEP ciphers.
+ * When the EXTIV bit is set in the key id byte an additional
+ * 4 bytes immediately follow the IV for TKIP.  For CCMP the
+ * EXTIV bit is likewise set but the 8 bytes represent the
+ * CCMP header rather than IV+extended-IV.
+ */
+#define IEEE80211_WEP_EXTIV         0x20
+#define IEEE80211_WEP_EXTIVLEN      4   /* extended IV length */
+#define IEEE80211_WEP_MICLEN        8   /* trailing MIC */
+
+#define IEEE80211_CRC_LEN           4
+
+#ifdef WAPI_ENABLE
+#define IEEE80211_WAPI_EXTIVLEN      10   /* extended IV length */
+#endif /* WAPI ENABLE */
+
+
+#define IEEE80211_ADDR_LEN  6       /* size of 802.11 address */
+/* is 802.11 address multicast/broadcast? */
+#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
+#define IEEE80211_IS_BROADCAST(_a)  (*(_a) == 0xFF)
+#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN)
+#define WEP_TRAILER IEEE80211_WEP_CRCLEN
+#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+                    IEEE80211_WEP_EXTIVLEN)
+#define CCMP_TRAILER IEEE80211_WEP_MICLEN
+#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+                    IEEE80211_WEP_EXTIVLEN)
+#define TKIP_TRAILER IEEE80211_WEP_CRCLEN
+#define TKIP_MICLEN  IEEE80211_WEP_MICLEN
+
+
+#define IEEE80211_ADDR_EQ(addr1, addr2)     \
+    (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
+
+#define IEEE80211_ADDR_COPY(dst,src)    A_MEMCPY(dst,src,IEEE80211_ADDR_LEN)
+
+#define IEEE80211_KEYBUF_SIZE 16
+#define IEEE80211_MICBUF_SIZE (8+8)  /* space for both tx and rx */
+
+/*
+ * NB: these values are ordered carefully; there are lots of
+ * of implications in any reordering.  In particular beware
+ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
+ */
+#define IEEE80211_CIPHER_WEP            0
+#define IEEE80211_CIPHER_TKIP           1
+#define IEEE80211_CIPHER_AES_OCB        2
+#define IEEE80211_CIPHER_AES_CCM        3
+#define IEEE80211_CIPHER_CKIP           5
+#define IEEE80211_CIPHER_CCKM_KRK       6
+#define IEEE80211_CIPHER_NONE           7       /* pseudo value */
+
+#define IEEE80211_CIPHER_MAX            (IEEE80211_CIPHER_NONE+1)
+
+#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
+        (((len) == 5) || ((len) == 13) || ((len) == 16))
+
+
+
+/*
+ * generic definitions for IEEE 802.11 frames
+ */
+PREPACK struct ieee80211_frame {
+    A_UINT8    i_fc[2];
+    A_UINT8    i_dur[2];
+    A_UINT8    i_addr1[IEEE80211_ADDR_LEN];
+    A_UINT8    i_addr2[IEEE80211_ADDR_LEN];
+    A_UINT8    i_addr3[IEEE80211_ADDR_LEN];
+    A_UINT8    i_seq[2];
+    /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
+    /* see below */
+} POSTPACK;
+
+PREPACK struct ieee80211_qosframe {
+    A_UINT8 i_fc[2];
+    A_UINT8 i_dur[2];
+    A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
+    A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
+    A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
+    A_UINT8 i_seq[2];
+    A_UINT8 i_qos[2];
+} POSTPACK;
+
+#define IEEE80211_FC0_VERSION_MASK          0x03
+#define IEEE80211_FC0_VERSION_SHIFT         0
+#define IEEE80211_FC0_VERSION_0             0x00
+#define IEEE80211_FC0_TYPE_MASK             0x0c
+#define IEEE80211_FC0_TYPE_SHIFT            2
+#define IEEE80211_FC0_TYPE_MGT              0x00
+#define IEEE80211_FC0_TYPE_CTL              0x04
+#define IEEE80211_FC0_TYPE_DATA             0x08
+
+#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
+#define IEEE80211_FC0_SUBTYPE_SHIFT         4
+/* for TYPE_MGT */
+#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
+#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
+#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
+#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
+#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
+#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
+#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
+#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
+#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
+#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
+#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
+/* for TYPE_CTL */
+#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
+#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
+#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
+#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
+#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
+#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
+/* for TYPE_DATA (bit combination) */
+#define IEEE80211_FC0_SUBTYPE_DATA          0x00
+#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
+#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
+#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
+#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
+#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
+#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
+#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
+#define IEEE80211_FC0_SUBTYPE_QOS           0x80
+#define IEEE80211_FC0_SUBTYPE_QOS_NULL      0xc0
+
+#define IEEE80211_FC1_DIR_MASK              0x03
+#define IEEE80211_FC1_DIR_NODS              0x00    /* STA->STA */
+#define IEEE80211_FC1_DIR_TODS              0x01    /* STA->AP  */
+#define IEEE80211_FC1_DIR_FROMDS            0x02    /* AP ->STA */
+#define IEEE80211_FC1_DIR_DSTODS            0x03    /* AP ->AP  */
+
+#define IEEE80211_FC1_MORE_FRAG             0x04
+#define IEEE80211_FC1_RETRY                 0x08
+#define IEEE80211_FC1_PWR_MGT               0x10
+#define IEEE80211_FC1_MORE_DATA             0x20
+#define IEEE80211_FC1_WEP                   0x40
+#define IEEE80211_FC1_ORDER                 0x80
+
+#define IEEE80211_SEQ_FRAG_MASK             0x000f
+#define IEEE80211_SEQ_FRAG_SHIFT            0
+#define IEEE80211_SEQ_SEQ_MASK              0xfff0
+#define IEEE80211_SEQ_SEQ_SHIFT             4
+
+#define IEEE80211_NWID_LEN                  32
+
+/*
+ * 802.11 rate set.
+ */
+#define IEEE80211_RATE_SIZE     8       /* 802.11 standard */
+#define IEEE80211_RATE_MAXSIZE  15      /* max rates we'll handle */
+
+#define WMM_NUM_AC                  4   /* 4 AC categories */
+
+#define WMM_PARAM_ACI_M         0x60    /* Mask for ACI field */
+#define WMM_PARAM_ACI_S         5   /* Shift for ACI field */
+#define WMM_PARAM_ACM_M         0x10    /* Mask for ACM bit */
+#define WMM_PARAM_ACM_S         4       /* Shift for ACM bit */
+#define WMM_PARAM_AIFSN_M       0x0f    /* Mask for aifsn field */
+#define WMM_PARAM_LOGCWMIN_M    0x0f    /* Mask for CwMin field (in log) */
+#define WMM_PARAM_LOGCWMAX_M    0xf0    /* Mask for CwMax field (in log) */
+#define WMM_PARAM_LOGCWMAX_S    4   /* Shift for CwMax field */
+
+#define WMM_AC_TO_TID(_ac) (       \
+    ((_ac) == WMM_AC_VO) ? 6 : \
+    ((_ac) == WMM_AC_VI) ? 5 : \
+    ((_ac) == WMM_AC_BK) ? 1 : \
+    0)
+
+#define TID_TO_WMM_AC(_tid) (      \
+    ((_tid) < 1) ? WMM_AC_BE : \
+    ((_tid) < 3) ? WMM_AC_BK : \
+    ((_tid) < 6) ? WMM_AC_VI : \
+    WMM_AC_VO)
+/*
+ * Management information element payloads.
+ */
+
+enum {
+    IEEE80211_ELEMID_SSID       = 0,
+    IEEE80211_ELEMID_RATES      = 1,
+    IEEE80211_ELEMID_FHPARMS    = 2,
+    IEEE80211_ELEMID_DSPARMS    = 3,
+    IEEE80211_ELEMID_CFPARMS    = 4,
+    IEEE80211_ELEMID_TIM        = 5,
+    IEEE80211_ELEMID_IBSSPARMS  = 6,
+    IEEE80211_ELEMID_COUNTRY    = 7,
+    IEEE80211_ELEMID_CHALLENGE  = 16,
+    /* 17-31 reserved for challenge text extension */
+    IEEE80211_ELEMID_PWRCNSTR   = 32,
+    IEEE80211_ELEMID_PWRCAP     = 33,
+    IEEE80211_ELEMID_TPCREQ     = 34,
+    IEEE80211_ELEMID_TPCREP     = 35,
+    IEEE80211_ELEMID_SUPPCHAN   = 36,
+    IEEE80211_ELEMID_CHANSWITCH = 37,
+    IEEE80211_ELEMID_MEASREQ    = 38,
+    IEEE80211_ELEMID_MEASREP    = 39,
+    IEEE80211_ELEMID_QUIET      = 40,
+    IEEE80211_ELEMID_IBSSDFS    = 41,
+    IEEE80211_ELEMID_ERP        = 42,
+    IEEE80211_ELEMID_HTCAP_ANA  = 45,   /* Address ANA, and non-ANA story, for interop. CL#171733 */
+    IEEE80211_ELEMID_RSN        = 48,
+    IEEE80211_ELEMID_XRATES     = 50,
+    IEEE80211_ELEMID_HTINFO_ANA = 61,
+#ifdef WAPI_ENABLE
+    IEEE80211_ELEMID_WAPI       = 68,
+#endif
+    IEEE80211_ELEMID_TPC        = 150,
+    IEEE80211_ELEMID_CCKM       = 156,
+    IEEE80211_ELEMID_VENDOR     = 221,  /* vendor private */
+};
+
+#define ATH_OUI             0x7f0300        /* Atheros OUI */
+#define ATH_OUI_TYPE        0x01
+#define ATH_OUI_SUBTYPE     0x01
+#define ATH_OUI_VERSION     0x00
+
+#define WPA_OUI             0xf25000
+#define WPA_OUI_TYPE        0x01
+#define WPA_VERSION         1          /* current supported version */
+
+#define WPA_CSE_NULL        0x00
+#define WPA_CSE_WEP40       0x01
+#define WPA_CSE_TKIP        0x02
+#define WPA_CSE_CCMP        0x04
+#define WPA_CSE_WEP104      0x05
+
+#define WPA_ASE_NONE        0x00
+#define WPA_ASE_8021X_UNSPEC    0x01
+#define WPA_ASE_8021X_PSK   0x02
+
+#define RSN_OUI         0xac0f00
+#define RSN_VERSION     1       /* current supported version */
+
+#define RSN_CSE_NULL        0x00
+#define RSN_CSE_WEP40       0x01
+#define RSN_CSE_TKIP        0x02
+#define RSN_CSE_WRAP        0x03
+#define RSN_CSE_CCMP        0x04
+#define RSN_CSE_WEP104      0x05
+
+#define RSN_ASE_NONE            0x00
+#define RSN_ASE_8021X_UNSPEC    0x01
+#define RSN_ASE_8021X_PSK       0x02
+
+#define RSN_CAP_PREAUTH         0x01
+
+#define WMM_OUI                 0xf25000
+#define WMM_OUI_TYPE            0x02
+#define WMM_INFO_OUI_SUBTYPE    0x00
+#define WMM_PARAM_OUI_SUBTYPE   0x01
+#define WMM_VERSION             1
+
+/* WMM stream classes */
+#define WMM_NUM_AC  4
+#define WMM_AC_BE   0       /* best effort */
+#define WMM_AC_BK   1       /* background */
+#define WMM_AC_VI   2       /* video */
+#define WMM_AC_VO   3       /* voice */
+
+/* TSPEC related */
+#define ACTION_CATEGORY_CODE_TSPEC                 17
+#define ACTION_CODE_TSPEC_ADDTS                    0
+#define ACTION_CODE_TSPEC_ADDTS_RESP               1
+#define ACTION_CODE_TSPEC_DELTS                    2
+
+typedef enum {
+    TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
+    TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
+    TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
+    TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
+    TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
+    TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
+    TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
+    TSPEC_STATUS_CODE_DELTS_SENT    = 0x30,
+    TSPEC_STATUS_CODE_DELTS_RECV    = 0x31,
+} TSPEC_STATUS_CODE;
+
+#define TSPEC_TSID_MASK             0xF
+#define TSPEC_TSID_S                1
+
+/*
+ * WMM/802.11e Tspec Element
+ */
+typedef PREPACK struct wmm_tspec_ie_t {
+    A_UINT8     elementId;
+    A_UINT8     len;
+    A_UINT8     oui[3];
+    A_UINT8     ouiType;
+    A_UINT8     ouiSubType;
+    A_UINT8     version;
+    A_UINT16    tsInfo_info;
+    A_UINT8     tsInfo_reserved;
+    A_UINT16    nominalMSDU;
+    A_UINT16    maxMSDU;
+    A_UINT32    minServiceInt;
+    A_UINT32    maxServiceInt;
+    A_UINT32    inactivityInt;
+    A_UINT32    suspensionInt;
+    A_UINT32    serviceStartTime;
+    A_UINT32    minDataRate;
+    A_UINT32    meanDataRate;
+    A_UINT32    peakDataRate;
+    A_UINT32    maxBurstSize;
+    A_UINT32    delayBound;
+    A_UINT32    minPhyRate;
+    A_UINT16    sba;
+    A_UINT16    mediumTime;
+} POSTPACK WMM_TSPEC_IE;
+
+
+/*
+ * BEACON management packets
+ *
+ *  octet timestamp[8]
+ *  octet beacon interval[2]
+ *  octet capability information[2]
+ *  information element
+ *      octet elemid
+ *      octet length
+ *      octet information[length]
+ */
+
+#define IEEE80211_BEACON_INTERVAL(beacon) \
+    ((beacon)[8] | ((beacon)[9] << 8))
+#define IEEE80211_BEACON_CAPABILITY(beacon) \
+    ((beacon)[10] | ((beacon)[11] << 8))
+
+#define IEEE80211_CAPINFO_ESS               0x0001
+#define IEEE80211_CAPINFO_IBSS              0x0002
+#define IEEE80211_CAPINFO_CF_POLLABLE       0x0004
+#define IEEE80211_CAPINFO_CF_POLLREQ        0x0008
+#define IEEE80211_CAPINFO_PRIVACY           0x0010
+#define IEEE80211_CAPINFO_SHORT_PREAMBLE    0x0020
+#define IEEE80211_CAPINFO_PBCC              0x0040
+#define IEEE80211_CAPINFO_CHNL_AGILITY      0x0080
+/* bits 8-9 are reserved */
+#define IEEE80211_CAPINFO_SHORT_SLOTTIME    0x0400
+#define IEEE80211_CAPINFO_APSD              0x0800
+/* bit 12 is reserved */
+#define IEEE80211_CAPINFO_DSSSOFDM          0x2000
+/* bits 14-15 are reserved */
+
+/*
+ * Authentication Modes
+ */
+
+enum ieee80211_authmode {
+    IEEE80211_AUTH_NONE     = 0,
+    IEEE80211_AUTH_OPEN     = 1,
+    IEEE80211_AUTH_SHARED   = 2,
+    IEEE80211_AUTH_8021X    = 3,
+    IEEE80211_AUTH_AUTO     = 4,   /* auto-select/accept */
+    /* NB: these are used only for ioctls */
+    IEEE80211_AUTH_WPA      = 5,  /* WPA/RSN  w/ 802.1x */
+    IEEE80211_AUTH_WPA_PSK  = 6,  /* WPA/RSN  w/ PSK */
+    IEEE80211_AUTH_WPA_CCKM = 7,  /* WPA/RSN IE  w/ CCKM */
+};
+
+#define IEEE80211_PS_MAX_QUEUE    50 /*Maximum no of buffers that can be queues for PS*/
+
+#include "athendpack.h"
+
+#endif /* _NET80211_IEEE80211_H_ */
diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h
new file mode 100644
index 000000000000..faa1d653509e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h
@@ -0,0 +1,81 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211_node.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _IEEE80211_NODE_H_
+#define _IEEE80211_NODE_H_
+
+/*
+ * Node locking definitions.
+ */
+#define IEEE80211_NODE_LOCK_INIT(_nt)   A_MUTEX_INIT(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \
+                                               A_MUTEX_DELETE(&(_nt)->nt_nodelock); }
+       
+#define IEEE80211_NODE_LOCK(_nt)        A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK(_nt)      A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_BH(_nt)     A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK_BH(_nt)   A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_ASSERT(_nt)
+
+/*
+ * Node reference counting definitions.
+ *
+ * ieee80211_node_initref   initialize the reference count to 1
+ * ieee80211_node_incref    add a reference
+ * ieee80211_node_decref    remove a reference
+ * ieee80211_node_dectestref    remove a reference and return 1 if this
+ *              is the last reference, otherwise 0
+ * ieee80211_node_refcnt    reference count for printing (only)
+ */
+#define ieee80211_node_initref(_ni)     ((_ni)->ni_refcnt = 1)
+#define ieee80211_node_incref(_ni)      ((_ni)->ni_refcnt++)
+#define ieee80211_node_decref(_ni)      ((_ni)->ni_refcnt--)
+#define ieee80211_node_dectestref(_ni)  (((_ni)->ni_refcnt--) == 1)
+#define ieee80211_node_refcnt(_ni)      ((_ni)->ni_refcnt)
+
+#define IEEE80211_NODE_HASHSIZE 32
+/* simple hash is enough for variation of macaddr */
+#define IEEE80211_NODE_HASH(addr)   \
+    (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
+        IEEE80211_NODE_HASHSIZE)
+
+/*
+ * Table of ieee80211_node instances.  Each ieee80211com
+ * has at least one for holding the scan candidates.
+ * When operating as an access point or in ibss mode there
+ * is a second table for associated stations or neighbors.
+ */
+struct ieee80211_node_table {
+    void                   *nt_wmip;       /* back reference */
+    A_MUTEX_T               nt_nodelock;    /* on node table */
+    struct bss              *nt_node_first; /* information of all nodes */
+    struct bss              *nt_node_last;  /* information of all nodes */
+    struct bss              *nt_hash[IEEE80211_NODE_HASHSIZE];
+    const char              *nt_name;   /* for debugging */
+    A_UINT32                nt_scangen; /* gen# for timeout scan */
+    A_TIMER                 nt_inact_timer;
+    A_UINT8                 isTimerArmed;   /* is the node timer armed */
+    A_UINT32                nt_nodeAge; /* node aging time */
+#ifdef OS_ROAM_MANAGEMENT
+    A_UINT32                nt_si_gen; /* gen# for scan indication*/
+#endif
+};
+
+#define WLAN_NODE_INACT_TIMEOUT_MSEC            120000
+
+#endif /* _IEEE80211_NODE_H_ */
diff --git a/drivers/net/wireless/ath6kl/wlan/src/makefile b/drivers/net/wireless/ath6kl/wlan/src/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c
new file mode 100644
index 000000000000..4f87d031459c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c
@@ -0,0 +1,569 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_node.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 node handling support.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#define ATH_MODULE_NAME wlan
+#include <a_debug.h>
+#include "htc.h"
+#include "htc_api.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211_node.h>
+
+#define ATH_DEBUG_WLAN ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef DEBUG
+
+static ATH_DEBUG_MASK_DESCRIPTION wlan_debug_desc[] = {
+    { ATH_DEBUG_WLAN , "General WLAN Node Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wlan,
+                                 "wlan",
+                                 "WLAN Node Management",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(wlan_debug_desc),
+                                 wlan_debug_desc);
+                                 
+#endif
+
+static void wlan_node_timeout(A_ATH_TIMER arg);
+
+static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt,
+                                     const A_UINT8 *macaddr);
+
+bss_t *
+wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
+{
+    bss_t *ni;
+
+    ni = A_MALLOC_NOWAIT(sizeof(bss_t));
+
+    if (ni != NULL) {
+        if (wh_size)
+        {
+        ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
+        if (ni->ni_buf == NULL) {
+            A_FREE(ni);
+            ni = NULL;
+            return ni;
+        }
+        }
+    } else {
+        return ni;
+    }
+
+    /* Make sure our lists are clean */
+    ni->ni_list_next = NULL;
+    ni->ni_list_prev = NULL;
+    ni->ni_hash_next = NULL;
+    ni->ni_hash_prev = NULL;
+
+    //
+    // ni_scangen never initialized before and during suspend/resume of winmobile,
+    // that some junk has been stored in this, due to this scan list didn't properly updated
+    //
+    ni->ni_scangen   = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+    ni->ni_si_gen    = 0;
+#endif
+
+    return ni;
+}
+
+void
+wlan_node_free(bss_t *ni)
+{
+    if (ni->ni_buf != NULL) {
+        A_FREE(ni->ni_buf);
+    }
+    A_FREE(ni);
+}
+
+void
+wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+                const A_UINT8 *macaddr)
+{
+    int hash;
+    A_UINT32 timeoutValue = 0;
+
+    A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
+    hash = IEEE80211_NODE_HASH (macaddr);
+    ieee80211_node_initref (ni);     /* mark referenced */
+
+    timeoutValue = nt->nt_nodeAge;
+
+    ni->ni_tstamp = A_GET_MS (timeoutValue);
+
+    IEEE80211_NODE_LOCK_BH(nt);
+
+    /* Insert at the end of the node list */
+    ni->ni_list_next = NULL;
+    ni->ni_list_prev = nt->nt_node_last;
+    if(nt->nt_node_last != NULL)
+    {
+        nt->nt_node_last->ni_list_next = ni;
+    }
+    nt->nt_node_last = ni;
+    if(nt->nt_node_first == NULL)
+    {
+        nt->nt_node_first = ni;
+    }
+
+    /* Insert into the hash list i.e. the bucket */
+    if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
+    {
+        nt->nt_hash[hash]->ni_hash_prev = ni;
+    }
+    ni->ni_hash_prev = NULL;
+    nt->nt_hash[hash] = ni;
+
+    if (!nt->isTimerArmed) {
+        A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0);
+        nt->isTimerArmed = TRUE;
+    }
+
+    IEEE80211_NODE_UNLOCK_BH(nt);
+}
+
+static bss_t *
+_ieee80211_find_node(struct ieee80211_node_table *nt,
+    const A_UINT8 *macaddr)
+{
+    bss_t *ni;
+    int hash;
+
+    IEEE80211_NODE_LOCK_ASSERT(nt);
+
+    hash = IEEE80211_NODE_HASH(macaddr);
+    for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
+        if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
+            ieee80211_node_incref(ni);  /* mark referenced */
+            return ni;
+        }
+    }
+    return NULL;
+}
+
+bss_t *
+wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
+{
+    bss_t *ni;
+
+    IEEE80211_NODE_LOCK(nt);
+    ni = _ieee80211_find_node(nt, macaddr);
+    IEEE80211_NODE_UNLOCK(nt);
+    return ni;
+}
+
+/*
+ * Reclaim a node.  If this is the last reference count then
+ * do the normal free work.  Otherwise remove it from the node
+ * table and mark it gone by clearing the back-reference.
+ */
+void
+wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
+{
+    IEEE80211_NODE_LOCK(nt);
+
+    if(ni->ni_list_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        nt->nt_node_first = ni->ni_list_next;
+    }
+    else
+    {
+        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+    }
+
+    if(ni->ni_list_next == NULL)
+    {
+        /* Last in list so fix list tail */
+        nt->nt_node_last = ni->ni_list_prev;
+    }
+    else
+    {
+        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+    }
+
+    if(ni->ni_hash_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        int hash;
+        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+        nt->nt_hash[hash] = ni->ni_hash_next;
+    }
+    else
+    {
+        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+    }
+
+    if(ni->ni_hash_next != NULL)
+    {
+        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+    }
+    wlan_node_free(ni);
+
+    IEEE80211_NODE_UNLOCK(nt);
+}
+
+static void
+wlan_node_dec_free(bss_t *ni)
+{
+    if (ieee80211_node_dectestref(ni)) {
+        wlan_node_free(ni);
+    }
+}
+
+void
+wlan_free_allnodes(struct ieee80211_node_table *nt)
+{
+    bss_t *ni;
+
+    while ((ni = nt->nt_node_first) != NULL) {
+        wlan_node_reclaim(nt, ni);
+    }
+}
+
+void
+wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+                   void *arg)
+{
+    bss_t *ni;
+    A_UINT32 gen;
+
+    gen = ++nt->nt_scangen;
+
+    IEEE80211_NODE_LOCK(nt);
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        if (ni->ni_scangen != gen) {
+            ni->ni_scangen = gen;
+            (void) ieee80211_node_incref(ni);
+            (*f)(arg, ni);
+            wlan_node_dec_free(ni);
+        }
+    }
+    IEEE80211_NODE_UNLOCK(nt);
+}
+
+/*
+ * Node table support.
+ */
+void
+wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
+{
+    int i;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt));
+    IEEE80211_NODE_LOCK_INIT(nt);
+
+    A_REGISTER_MODULE_DEBUG_INFO(wlan);
+    
+    nt->nt_node_first = nt->nt_node_last = NULL;
+    for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
+    {
+        nt->nt_hash[i] = NULL;
+    }
+
+    A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
+    nt->isTimerArmed = FALSE;
+    nt->nt_wmip = wmip;
+    nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+    //
+    // nt_scangen never initialized before and during suspend/resume of winmobile, 
+    // that some junk has been stored in this, due to this scan list didn't properly updated
+    //
+    nt->nt_scangen   = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+    nt->nt_si_gen    = 0;
+#endif
+}
+
+void
+wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge)
+{
+    nt->nt_nodeAge = nodeAge;
+    return;
+}
+static void
+wlan_node_timeout (A_ATH_TIMER arg)
+{
+    struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
+    bss_t *bss, *nextBss;
+    A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
+    A_UINT32 timeoutValue = 0;
+
+    timeoutValue = nt->nt_nodeAge;
+
+    wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+    bss = nt->nt_node_first;
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+        {
+
+            if (bss->ni_tstamp <= A_GET_MS(0))
+            {
+               /*
+                * free up all but the current bss - if set
+                */
+                wlan_node_reclaim(nt, bss);
+            }
+            else
+            {
+                /*
+                 * Re-arm timer, only when we have a bss other than
+                 * current bss AND it is not aged-out.
+                 */
+                reArmTimer = TRUE;
+            }
+        }
+        bss = nextBss;
+    }
+
+    if (reArmTimer)
+        A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0);
+
+    nt->isTimerArmed = reArmTimer;
+}
+
+void
+wlan_node_table_cleanup(struct ieee80211_node_table *nt)
+{
+    A_UNTIMEOUT(&nt->nt_inact_timer);
+    A_DELETE_TIMER(&nt->nt_inact_timer);
+    wlan_free_allnodes(nt);
+    IEEE80211_NODE_LOCK_DESTROY(nt);
+}
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+    bss_t   *ni = NULL;
+    A_UCHAR *pIESsid = NULL;
+
+    IEEE80211_NODE_LOCK (nt);
+
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        pIESsid = ni->ni_cie.ie_ssid;
+        if (pIESsid[1] <= 32) {
+
+            // Step 1 : Check SSID
+            if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+                //
+                // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID
+                // Profile, otherwise check whether WPA2 or WPA
+                //
+                if (TRUE == bMatchSSID) {
+                    ieee80211_node_incref (ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+
+                // Step 2 : if SSID matches, check WPA or WPA2
+                if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
+                    ieee80211_node_incref (ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+                if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
+                    ieee80211_node_incref(ni);  /* mark referenced */
+                    IEEE80211_NODE_UNLOCK (nt);
+                    return ni;
+                }
+            }
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK (nt);
+
+    return NULL;
+}
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
+{
+    IEEE80211_NODE_LOCK (nt);
+    wlan_node_dec_free (ni);
+    IEEE80211_NODE_UNLOCK (nt);
+}
+
+void
+wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni)
+{
+    if(ni->ni_list_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        nt->nt_node_first = ni->ni_list_next;
+    }
+    else
+    {
+        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+    }
+
+    if(ni->ni_list_next == NULL)
+    {
+        /* Last in list so fix list tail */
+        nt->nt_node_last = ni->ni_list_prev;
+    }
+    else
+    {
+        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+    }
+
+    if(ni->ni_hash_prev == NULL)
+    {
+        /* First in list so fix the list head */
+        int hash;
+        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+        nt->nt_hash[hash] = ni->ni_hash_next;
+    }
+    else
+    {
+        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+    }
+
+    if(ni->ni_hash_next != NULL)
+    {
+        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+    }
+}
+
+bss_t *
+wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid)
+{
+    bss_t *bss, *nextBss;
+
+    IEEE80211_NODE_LOCK(nt);
+
+    bss = nt->nt_node_first;
+
+    while (bss != NULL)
+    {
+        nextBss = bss->ni_list_next;
+
+        if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0)
+        {
+            wlan_node_remove_core (nt, bss);
+            IEEE80211_NODE_UNLOCK(nt);
+            return bss;
+        }
+
+        bss = nextBss;
+    }
+
+    IEEE80211_NODE_UNLOCK(nt);
+    return NULL;
+}
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+                    A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+    bss_t   *ni = NULL;
+    bss_t   *best_ni = NULL;
+    A_UCHAR *pIESsid = NULL;
+
+    IEEE80211_NODE_LOCK (nt);
+
+    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+        pIESsid = ni->ni_cie.ie_ssid;
+        if (pIESsid[1] <= 32) {
+
+            // Step 1 : Check SSID
+            if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+                if (ni->ni_cie.ie_capInfo & 0x10)
+                {
+
+                    if ((NULL != ni->ni_cie.ie_rsn) && (WPA2_PSK_AUTH == authMode))
+                    {
+                        /* WPA2 */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                    else if ((NULL != ni->ni_cie.ie_wpa) && (WPA_PSK_AUTH == authMode))
+                    {
+                        /* WPA */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                    else if (WEP_CRYPT == pairwiseCryptoType)
+                    {
+                        /* WEP */
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                }
+                else
+                {
+                    /* open AP */
+                    if ((OPEN_AUTH == authMode) && (NONE_CRYPT == pairwiseCryptoType))
+                    {
+                        if (NULL == best_ni)
+                        {
+                            best_ni = ni;
+                        }
+                        else if (ni->ni_rssi > best_ni->ni_rssi)
+                        {
+                            best_ni = ni;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK (nt);
+
+    return best_ni;
+}
+
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c
new file mode 100644
index 000000000000..0d5bce78165f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c
@@ -0,0 +1,196 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_recv_beacon.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 input handling.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+
+#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do {         \
+    if ((_len) < (_minlen)) {                   \
+        return A_EINVAL;                         \
+    }                               \
+} while (0)
+
+#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do {         \
+    if ((__elem) == NULL) {                     \
+        return A_EINVAL;                         \
+    }                               \
+    if ((__elem)[1] > (__maxlen)) {                 \
+        return A_EINVAL;                         \
+    }                               \
+} while (0)
+
+
+/* unaligned little endian access */
+#define LE_READ_2(p)                            \
+    ((A_UINT16)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8)))
+
+#define LE_READ_4(p)                            \
+    ((A_UINT32)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
+      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+
+static int __inline
+iswpaoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
+}
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+/* unused functions for now */
+#if 0
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+static int __inline
+iswmminfo(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
+}
+#endif
+
+static int __inline
+isatherosoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
+}
+
+static int __inline
+iswscoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
+}
+
+A_STATUS
+wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
+{
+    A_UINT8 *frm, *efrm;
+    A_UINT8 elemid_ssid = FALSE;
+
+    frm = buf;
+    efrm = (A_UINT8 *) (frm + framelen);
+
+    /*
+     * beacon/probe response frame format
+     *  [8] time stamp
+     *  [2] beacon interval
+     *  [2] capability information
+     *  [tlv] ssid
+     *  [tlv] supported rates
+     *  [tlv] country information
+     *  [tlv] parameter set (FH/DS)
+     *  [tlv] erp information
+     *  [tlv] extended supported rates
+     *  [tlv] WMM
+     *  [tlv] WPA or RSN
+     *  [tlv] Atheros Advanced Capabilities
+     */
+    IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
+    A_MEMZERO(cie, sizeof(*cie));
+
+    cie->ie_tstamp = frm; frm += 8;
+    cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
+    cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
+    cie->ie_chan = 0;
+
+    while (frm < efrm) {
+        switch (*frm) {
+        case IEEE80211_ELEMID_SSID:
+            if (!elemid_ssid) {
+                cie->ie_ssid = frm;
+                elemid_ssid = TRUE;
+            }
+            break;
+        case IEEE80211_ELEMID_RATES:
+            cie->ie_rates = frm;
+            break;
+        case IEEE80211_ELEMID_COUNTRY:
+            cie->ie_country = frm;
+            break;
+        case IEEE80211_ELEMID_FHPARMS:
+            break;
+        case IEEE80211_ELEMID_DSPARMS:
+            cie->ie_chan = frm[2];
+            break;
+        case IEEE80211_ELEMID_TIM:
+            cie->ie_tim = frm;
+            break;
+        case IEEE80211_ELEMID_IBSSPARMS:
+            break;
+        case IEEE80211_ELEMID_XRATES:
+            cie->ie_xrates = frm;
+            break;
+        case IEEE80211_ELEMID_ERP:
+            if (frm[1] != 1) {
+                //A_PRINTF("Discarding ERP Element - Bad Len\n");
+                return A_EINVAL;
+            }
+            cie->ie_erp = frm[2];
+            break;
+        case IEEE80211_ELEMID_RSN:
+            cie->ie_rsn = frm;
+            break;
+        case IEEE80211_ELEMID_HTCAP_ANA:
+            cie->ie_htcap = frm;
+            break;
+        case IEEE80211_ELEMID_HTINFO_ANA:
+            cie->ie_htop = frm;
+            break;
+#ifdef WAPI_ENABLE
+		case IEEE80211_ELEMID_WAPI:
+            cie->ie_wapi = frm;
+            break;
+#endif
+        case IEEE80211_ELEMID_VENDOR:
+            if (iswpaoui(frm)) {
+                cie->ie_wpa = frm;
+            } else if (iswmmoui(frm)) {
+                cie->ie_wmm = frm;
+            } else if (isatherosoui(frm)) {
+                cie->ie_ath = frm;
+            } else if(iswscoui(frm)) {
+                cie->ie_wsc = frm;
+            }
+            break;
+        default:
+            break;
+        }
+        frm += frm[1] + 2;
+    }
+    IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
+    IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
+
+    return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c
new file mode 100644
index 000000000000..0d1c24ec1ca6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c
@@ -0,0 +1,57 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_utils.c" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements frequently used wlan utilies
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+
+/*
+ * converts ieee channel number to frequency
+ */
+A_UINT16
+wlan_ieee2freq(int chan)
+{
+    if (chan == 14) {
+        return 2484;
+    }
+    if (chan < 14) {    /* 0-13 */
+        return (2407 + (chan*5));
+    }
+    if (chan < 27) {    /* 15-26 */
+        return (2512 + ((chan-15)*20));
+    }
+    return (5000 + (chan*5));
+}
+
+/*
+ * Converts MHz frequency to IEEE channel number.
+ */
+A_UINT32
+wlan_freq2ieee(A_UINT16 freq)
+{
+    if (freq == 2484)
+        return 14;
+    if (freq < 2484)
+        return (freq - 2407) / 5;
+    if (freq < 5000)
+        return 15 + ((freq - 2512) / 20);
+    return (freq - 5000) / 5;
+}
diff --git a/drivers/net/wireless/ath6kl/wmi/makefile b/drivers/net/wireless/ath6kl/wmi/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+#    Copyright (c) 2005-2007 Atheros Corporation.  All rights reserved.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/wmi/wmi.c b/drivers/net/wireless/ath6kl/wmi/wmi.c
new file mode 100644
index 000000000000..3a7667d2c39e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/wmi.c
@@ -0,0 +1,6536 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi.c" company="Atheros">
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements the hardware independent layer of the
+// Wireless Module Interface (WMI) protocol.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include "htc.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211.h>
+#include <ieee80211_node.h>
+#include "dset_api.h"
+#include "gpio_api.h"
+#include "wmi_host.h"
+#include "a_drv.h"
+#include "a_drv_api.h"
+#define ATH_MODULE_NAME wmi
+#include "a_debug.h"
+#include "dbglog_api.h"
+#include "roaming.h"
+
+#define ATH_DEBUG_WMI ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef DEBUG
+
+static ATH_DEBUG_MASK_DESCRIPTION wmi_debug_desc[] = {
+    { ATH_DEBUG_WMI , "General WMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wmi,
+                                 "wmi",
+                                 "Wireless Module Interface",
+                                 ATH_DEBUG_MASK_DEFAULTS,
+                                 ATH_DEBUG_DESCRIPTION_COUNT(wmi_debug_desc),
+                                 wmi_debug_desc);
+
+#endif
+
+#ifndef REXOS
+#define DBGARG      _A_FUNCNAME_
+#define DBGFMT      "%s() : "
+#define DBG_WMI     ATH_DEBUG_WMI
+#define DBG_ERROR   ATH_DEBUG_ERR
+#define DBG_WMI2    ATH_DEBUG_WMI
+#define A_DPRINTF   AR_DEBUG_PRINTF
+#endif
+
+static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+
+static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                       int len);
+static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_sync_point(struct wmi_t *wmip);
+
+static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                         int len);
+static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                       int len);
+static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                             int len);
+
+static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+
+static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                      int len);
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex);
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+                  WMI_SYNC_FLAG syncflag);
+
+A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+
+void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+
+static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap,
+                                        int len);
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS wmi_addba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_addba_resp_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_delba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_btcoex_stats_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+static A_STATUS wmi_hci_event_rx(struct wmi_t *, A_UINT8 *, int);
+
+#ifdef WAPI_ENABLE
+static A_STATUS wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+                                     int len);
+#endif
+
+#if defined(UNDER_CE)
+#if defined(NDIS51_MINIPORT)
+unsigned int processDot11Hdr = 0;
+#else
+unsigned int processDot11Hdr = 1;
+#endif
+#else
+extern unsigned int processDot11Hdr;
+#endif
+
+int wps_enable;
+static const A_INT32 wmi_rateTable[][2] = {
+  //{W/O SGI, with SGI}
+    {1000, 1000},
+    {2000, 2000},
+    {5500, 5500},
+    {11000, 11000},
+    {6000, 6000},
+    {9000, 9000},
+    {12000, 12000},
+    {18000, 18000},
+    {24000, 24000},
+    {36000, 36000},
+    {48000, 48000},
+    {54000, 54000},
+    {6500, 7200},
+    {13000, 14400},
+    {19500, 21700},
+    {26000, 28900},
+    {39000, 43300},
+    {52000, 57800},
+    {58500, 65000},
+    {65000, 72200},
+    {13500, 15000},
+    {27000, 30000},
+    {40500, 45000},
+    {54000, 60000},
+    {81000, 90000},
+    {108000, 120000},
+    {121500, 135000},
+    {135000, 150000},
+    {0, 0}};
+
+#define MODE_A_SUPPORT_RATE_START       ((A_INT32) 4)
+#define MODE_A_SUPPORT_RATE_STOP        ((A_INT32) 11)
+
+#define MODE_GONLY_SUPPORT_RATE_START   MODE_A_SUPPORT_RATE_START
+#define MODE_GONLY_SUPPORT_RATE_STOP    MODE_A_SUPPORT_RATE_STOP
+
+#define MODE_B_SUPPORT_RATE_START       ((A_INT32) 0)
+#define MODE_B_SUPPORT_RATE_STOP        ((A_INT32) 3)
+
+#define MODE_G_SUPPORT_RATE_START       ((A_INT32) 0)
+#define MODE_G_SUPPORT_RATE_STOP        ((A_INT32) 11)
+
+#define MODE_GHT20_SUPPORT_RATE_START   ((A_INT32) 0)
+#define MODE_GHT20_SUPPORT_RATE_STOP    ((A_INT32) 19)
+
+#define MAX_NUMBER_OF_SUPPORT_RATES     (MODE_GHT20_SUPPORT_RATE_STOP + 1)
+
+/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
+const A_UINT8 up_to_ac[]= {
+                WMM_AC_BE,
+                WMM_AC_BK,
+                WMM_AC_BK,
+                WMM_AC_BE,
+                WMM_AC_VI,
+                WMM_AC_VI,
+                WMM_AC_VO,
+                WMM_AC_VO,
+            };
+
+#include "athstartpack.h"
+
+/* This stuff is used when we want a simple layer-3 visibility */
+typedef PREPACK struct _iphdr {
+    A_UINT8     ip_ver_hdrlen;          /* version and hdr length */
+    A_UINT8     ip_tos;                 /* type of service */
+    A_UINT16    ip_len;                 /* total length */
+    A_UINT16    ip_id;                  /* identification */
+    A_INT16     ip_off;                 /* fragment offset field */
+#define IP_DF 0x4000                    /* dont fragment flag */
+#define IP_MF 0x2000                    /* more fragments flag */
+#define IP_OFFMASK 0x1fff               /* mask for fragmenting bits */
+    A_UINT8     ip_ttl;                 /* time to live */
+    A_UINT8     ip_p;                   /* protocol */
+    A_UINT16    ip_sum;                 /* checksum */
+    A_UINT8     ip_src[4];              /* source and dest address */
+    A_UINT8     ip_dst[4];
+} POSTPACK iphdr;
+
+#include "athendpack.h"
+
+A_INT16 rssi_event_value = 0;
+A_INT16 snr_event_value = 0;
+
+A_BOOL is_probe_ssid = FALSE;
+
+void *
+wmi_init(void *devt)
+{
+    struct wmi_t *wmip;
+
+    A_REGISTER_MODULE_DEBUG_INFO(wmi);
+
+    wmip = A_MALLOC(sizeof(struct wmi_t));
+    if (wmip == NULL) {
+        return (NULL);
+    }
+    A_MEMZERO(wmip, sizeof(*wmip));
+    A_MUTEX_INIT(&wmip->wmi_lock);
+    wmip->wmi_devt = devt;
+    wlan_node_table_init(wmip, &wmip->wmi_scan_table);
+    wmi_qos_state_init(wmip);
+
+    wmip->wmi_powerMode = REC_POWER;
+    wmip->wmi_phyMode = WMI_11G_MODE;
+
+    wmip->wmi_pair_crypto_type  = NONE_CRYPT;
+    wmip->wmi_grp_crypto_type   = NONE_CRYPT;
+
+    return (wmip);
+}
+
+void
+wmi_qos_state_init(struct wmi_t *wmip)
+{
+    A_UINT8 i;
+
+    if (wmip == NULL) {
+        return;
+    }
+    LOCK_WMI(wmip);
+
+    /* Initialize QoS States */
+    wmip->wmi_numQoSStream = 0;
+
+    wmip->wmi_fatPipeExists = 0;
+
+    for (i=0; i < WMM_NUM_AC; i++) {
+        wmip->wmi_streamExistsForAC[i]=0;
+    }
+
+    UNLOCK_WMI(wmip);
+
+    A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
+}
+
+void
+wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid)
+{
+    A_ASSERT( eid != ENDPOINT_UNUSED);
+    wmip->wmi_endpoint_id = eid;
+}
+
+HTC_ENDPOINT_ID
+wmi_get_control_ep(struct wmi_t * wmip)
+{
+    return(wmip->wmi_endpoint_id);
+}
+
+void
+wmi_shutdown(struct wmi_t *wmip)
+{
+    if (wmip != NULL) {
+        wlan_node_table_cleanup(&wmip->wmi_scan_table);
+        if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
+            A_MUTEX_DELETE(&wmip->wmi_lock);
+        }
+        A_FREE(wmip);
+    }
+}
+
+/*
+ *  performs DIX to 802.3 encapsulation for transmit packets.
+ *  uses passed in buffer.  Returns buffer or NULL if failed.
+ *  Assumes the entire DIX header is contigous and that there is
+ *  enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
+ */
+A_STATUS
+wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
+{
+    A_UINT8          *datap;
+    A_UINT16         typeorlen;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_HEADROOM(osbuf) <
+        (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+    {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+        /*
+         * packet is already in 802.3 format - return success
+         */
+        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+        return (A_OK);
+    }
+
+    /*
+     * Save mac fields and length to be inserted later
+     */
+    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+                                  sizeof(ATH_LLC_SNAP_HDR));
+
+    /*
+     * Make room for LLC+SNAP headers
+     */
+    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+    llcHdr->dsap      = 0xAA;
+    llcHdr->ssap      = 0xAA;
+    llcHdr->cntl      = 0x03;
+    llcHdr->orgCode[0] = 0x0;
+    llcHdr->orgCode[1] = 0x0;
+    llcHdr->orgCode[2] = 0x0;
+    llcHdr->etherType = typeorlen;
+
+    return (A_OK);
+}
+
+A_STATUS wmi_meta_add(struct wmi_t *wmip, void *osbuf, A_UINT8 *pVersion,void *pTxMetaS)
+{
+    switch(*pVersion){
+	case 0:
+    		return (A_OK);
+    	case WMI_META_VERSION_1:
+	        {
+        	WMI_TX_META_V1     *pV1= NULL;
+        	A_ASSERT(osbuf != NULL);
+        	if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+            		return A_NO_MEMORY;
+        	}
+
+        	pV1 = (WMI_TX_META_V1 *)A_NETBUF_DATA(osbuf);
+        	/* the pktID is used in conjunction with txComplete messages
+        	* allowing the target to notify which tx requests have been
+        	* completed and how. */
+        	pV1->pktID = 0;
+        	/* the ratePolicyID allows the host to specify which rate policy
+        	* to use for transmitting this packet. 0 means use default behavior. */
+        	pV1->ratePolicyID = 0;
+        	A_ASSERT(pVersion != NULL);
+        	/* the version must be used to populate the meta field of the WMI_DATA_HDR */
+        	*pVersion = WMI_META_VERSION_1;
+        	return (A_OK);
+    		}
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+	case WMI_META_VERSION_2:
+		{
+     		WMI_TX_META_V2 *pV2 ;
+        	A_ASSERT(osbuf != NULL);
+        	if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+            		return A_NO_MEMORY;
+        	}
+         	pV2 = (WMI_TX_META_V2 *)A_NETBUF_DATA(osbuf);
+         	A_MEMCPY(pV2,(WMI_TX_META_V2 *)pTxMetaS,sizeof(WMI_TX_META_V2));
+         	return (A_OK);
+    		}
+#endif
+	default:
+		return (A_OK);
+    }
+}
+
+/* Adds a WMI data header */
+A_STATUS
+wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData,
+                    WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS)
+{
+    WMI_DATA_HDR     *dtHdr;
+//    A_UINT8 metaVersion = 0;
+    A_STATUS status;
+
+    A_ASSERT(osbuf != NULL);
+
+    /* adds the meta data field after the wmi data hdr. If metaVersion
+     * is returns 0 then no meta field was added. */
+    if ((status = wmi_meta_add(wmip, osbuf, &metaVersion,pTxMetaS)) != A_OK) {
+        return status;
+    }
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+    A_MEMZERO(dtHdr, sizeof(WMI_DATA_HDR));
+
+    WMI_DATA_HDR_SET_MSG_TYPE(dtHdr, msgType);
+    WMI_DATA_HDR_SET_DATA_TYPE(dtHdr, data_type);
+
+    if (bMoreData) {
+        WMI_DATA_HDR_SET_MORE_BIT(dtHdr);
+    }
+
+    WMI_DATA_HDR_SET_META(dtHdr, metaVersion);
+    //dtHdr->rssi = 0;
+
+    return (A_OK);
+}
+
+
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled)
+{
+    A_UINT8         *datap;
+    A_UINT8         trafficClass = WMM_AC_BE;
+    A_UINT16        ipType = IP_ETHERTYPE;
+    WMI_DATA_HDR    *dtHdr;
+    A_BOOL           streamExists = FALSE;
+    A_UINT8        userPriority;
+    A_UINT32            hdrsize, metasize;
+    ATH_LLC_SNAP_HDR    *llcHdr;
+
+    WMI_CREATE_PSTREAM_CMD  cmd;
+
+    A_ASSERT(osbuf != NULL);
+
+    //
+    // Initialize header size
+    //
+    hdrsize = 0;
+
+    datap = A_NETBUF_DATA(osbuf);
+    dtHdr = (WMI_DATA_HDR *)datap;
+    metasize = (WMI_DATA_HDR_GET_META(dtHdr))? WMI_MAX_TX_META_SZ : 0;
+
+    if (!wmmEnabled)
+    {
+            /* If WMM is disabled all traffic goes as BE traffic */
+        userPriority = 0;
+    }
+    else
+    {
+        if (processDot11Hdr)
+        {
+             hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+             llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+                          hdrsize);
+
+
+        }
+        else
+        {
+            llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+                          sizeof(ATH_MAC_HDR));
+        }
+
+        if (llcHdr->etherType == A_CPU2BE16(ipType))
+        {
+            /* Extract the endpoint info from the TOS field in the IP header */
+
+            userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority);
+        }
+        else
+        {
+            userPriority = layer2Priority & 0x7;
+        }
+    }
+
+    trafficClass = convert_userPriority_to_trafficClass(userPriority);
+
+    WMI_DATA_HDR_SET_UP(dtHdr, userPriority);
+    //dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT;  /* lower 3-bits are 802.1d priority */
+
+    LOCK_WMI(wmip);
+    streamExists = wmip->wmi_fatPipeExists;
+    UNLOCK_WMI(wmip);
+
+    if (!(streamExists & (1 << trafficClass)))
+    {
+
+        A_MEMZERO(&cmd, sizeof(cmd));
+        cmd.trafficClass = trafficClass;
+        cmd.userPriority = userPriority;
+        cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
+            /* Implicit streams are created with TSID 0xFF */
+
+        cmd.tsid = WMI_IMPLICIT_PSTREAM;
+        wmi_create_pstream_cmd(wmip, &cmd);
+    }
+
+    return trafficClass;
+}
+
+A_STATUS
+wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode)
+{
+    A_UINT8          *datap;
+    A_UINT16         typeorlen;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+    struct           ieee80211_frame *wh;
+    A_UINT32         hdrsize;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_HEADROOM(osbuf) <
+        (sizeof(struct ieee80211_qosframe) +  sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+    {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+/*
+         * packet is already in 802.3 format - return success
+         */
+        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+        goto AddDot11Hdr;
+    }
+
+    /*
+     * Save mac fields and length to be inserted later
+     */
+    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+                                  sizeof(ATH_LLC_SNAP_HDR));
+
+    // Remove the Ethernet hdr
+    A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR));
+    /*
+     * Make room for LLC+SNAP headers
+     */
+    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+    datap = A_NETBUF_DATA(osbuf);
+
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+    llcHdr->dsap       = 0xAA;
+    llcHdr->ssap       = 0xAA;
+    llcHdr->cntl       = 0x03;
+    llcHdr->orgCode[0] = 0x0;
+    llcHdr->orgCode[1] = 0x0;
+    llcHdr->orgCode[2] = 0x0;
+    llcHdr->etherType  = typeorlen;
+
+AddDot11Hdr:
+    /* Make room for 802.11 hdr */
+    if (wmip->wmi_is_wmm_enabled)
+    {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+        if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+        {
+            return A_NO_MEMORY;
+        }
+        wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+        wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS;
+    }
+    else
+    {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32));
+        if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+        {
+            return A_NO_MEMORY;
+        }
+        wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+        wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA;
+    }
+    /* Setup the SA & DA */
+    IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac);
+
+    if (mode == INFRA_NETWORK) {
+        IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac);
+    }
+    else if (mode == ADHOC_NETWORK) {
+        IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac);
+    }
+
+    return (A_OK);
+}
+
+A_STATUS
+wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+    A_UINT8          *datap;
+    struct           ieee80211_frame *pwh,wh;
+    A_UINT8          type,subtype;
+    ATH_LLC_SNAP_HDR *llcHdr;
+    ATH_MAC_HDR      macHdr;
+    A_UINT32         hdrsize;
+
+    A_ASSERT(osbuf != NULL);
+    datap = A_NETBUF_DATA(osbuf);
+
+    pwh = (struct ieee80211_frame *)datap;
+    type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+    subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
+
+    A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame));
+
+    /* strip off the 802.11 hdr*/
+    if (subtype == IEEE80211_FC0_SUBTYPE_QOS) {
+        hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+        A_NETBUF_PULL(osbuf, hdrsize);
+    } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) {
+        A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame));
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+
+    macHdr.typeOrLen = llcHdr->etherType;
+
+    switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) {
+    case IEEE80211_FC1_DIR_NODS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+        break;
+    case IEEE80211_FC1_DIR_TODS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+        break;
+    case IEEE80211_FC1_DIR_FROMDS:
+        IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+        IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3);
+        break;
+    case IEEE80211_FC1_DIR_DSTODS:
+        break;
+    }
+
+    // Remove the LLC Hdr.
+    A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR));
+
+    // Insert the ATH MAC hdr.
+
+    A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR));
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR));
+
+    return A_OK;
+}
+
+/*
+ *  performs 802.3 to DIX encapsulation for received packets.
+ *  Assumes the entire 802.3 header is contigous.
+ */
+A_STATUS
+wmi_dot3_2_dix(void *osbuf)
+{
+    A_UINT8          *datap;
+    ATH_MAC_HDR      macHdr;
+    ATH_LLC_SNAP_HDR *llcHdr;
+
+    A_ASSERT(osbuf != NULL);
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
+    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+    macHdr.typeOrLen = llcHdr->etherType;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+    return (A_OK);
+}
+
+/*
+ * Removes a WMI data header
+ */
+A_STATUS
+wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+    A_ASSERT(osbuf != NULL);
+
+    return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
+}
+
+void
+wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
+{
+    wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
+}
+
+/*
+ * WMI Extended Event received from Target.
+ */
+A_STATUS
+wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
+{
+    WMIX_CMD_HDR *cmd;
+    A_UINT16 id;
+    A_UINT8 *datap;
+    A_UINT32 len;
+    A_STATUS status = A_OK;
+
+    if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    id = cmd->commandId;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    len = A_NETBUF_LEN(osbuf);
+
+    switch (id) {
+    case (WMIX_DSETOPENREQ_EVENTID):
+        status = wmi_dset_open_req_rx(wmip, datap, len);
+        break;
+#ifdef CONFIG_HOST_DSET_SUPPORT
+    case (WMIX_DSETCLOSE_EVENTID):
+        status = wmi_dset_close_rx(wmip, datap, len);
+        break;
+    case (WMIX_DSETDATAREQ_EVENTID):
+        status = wmi_dset_data_req_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+    case (WMIX_GPIO_INTR_EVENTID):
+        wmi_gpio_intr_rx(wmip, datap, len);
+        break;
+    case (WMIX_GPIO_DATA_EVENTID):
+        wmi_gpio_data_rx(wmip, datap, len);
+        break;
+    case (WMIX_GPIO_ACK_EVENTID):
+        wmi_gpio_ack_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+    case (WMIX_HB_CHALLENGE_RESP_EVENTID):
+        wmi_hbChallengeResp_rx(wmip, datap, len);
+        break;
+    case (WMIX_DBGLOG_EVENTID):
+        wmi_dbglog_event_rx(wmip, datap, len);
+        break;
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+    case (WMIX_PROF_COUNT_EVENTID):
+        wmi_prof_count_rx(wmip, datap, len);
+        break;
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+    default:
+        A_DPRINTF(DBG_WMI|DBG_ERROR,
+            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+        wmip->wmi_stats.cmd_id_err++;
+        status = A_ERROR;
+        break;
+    }
+
+    return status;
+}
+
+/*
+ * Control Path
+ */
+A_UINT32 cmdRecvNum;
+
+A_STATUS
+wmi_control_rx(struct wmi_t *wmip, void *osbuf)
+{
+    WMI_CMD_HDR *cmd;
+    A_UINT16 id;
+    A_UINT8 *datap;
+    A_UINT32 len, i, loggingReq;
+    A_STATUS status = A_OK;
+
+    A_ASSERT(osbuf != NULL);
+    if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    id = cmd->commandId;
+
+    if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+        wmip->wmi_stats.cmd_len_err++;
+        return A_ERROR;
+    }
+
+    datap = A_NETBUF_DATA(osbuf);
+    len = A_NETBUF_LEN(osbuf);
+
+    loggingReq = 0;
+
+    ar6000_get_driver_cfg(wmip->wmi_devt,
+                    AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
+                    &loggingReq);
+
+    if(loggingReq) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
+        for(i = 0; i < len; i++)
+            AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
+    }
+
+    LOCK_WMI(wmip);
+    cmdRecvNum++;
+    UNLOCK_WMI(wmip);
+
+    switch (id) {
+    case (WMI_GET_BITRATE_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
+        status = wmi_bitrate_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_CHANNEL_LIST_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
+        status = wmi_channelList_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_TX_PWR_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
+        status = wmi_txPwr_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_READY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
+        status = wmi_ready_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
+        break;
+    case (WMI_CONNECT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
+        status = wmi_connect_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_DISCONNECT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
+        status = wmi_disconnect_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_PEER_NODE_EVENTID):
+        A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG));
+        status = wmi_peer_node_event_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_TKIP_MICERR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
+        status = wmi_tkip_micerr_event_rx(wmip, datap, len);
+        break;
+    case (WMI_BSSINFO_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
+        {
+            /*
+             * convert WMI_BSS_INFO_HDR2 to WMI_BSS_INFO_HDR
+             * Take a local copy of the WMI_BSS_INFO_HDR2 from the wmi buffer
+             * and reconstruct the WMI_BSS_INFO_HDR in its place
+            */
+            WMI_BSS_INFO_HDR2 bih2;
+            WMI_BSS_INFO_HDR *bih;
+            A_MEMCPY(&bih2, datap, sizeof(WMI_BSS_INFO_HDR2));
+
+            A_NETBUF_PUSH(osbuf, 4);
+            datap = A_NETBUF_DATA(osbuf);
+            len = A_NETBUF_LEN(osbuf);
+            bih = (WMI_BSS_INFO_HDR *)datap;
+
+            bih->channel = bih2.channel;
+            bih->frameType = bih2.frameType;
+            bih->snr = bih2.snr;
+            bih->rssi = bih2.snr - 95;
+            bih->ieMask = bih2.ieMask;
+            A_MEMCPY(bih->bssid, bih2.bssid, ATH_MAC_LEN);
+
+            status = wmi_bssInfo_event_rx(wmip, datap, len);
+            A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        }
+        break;
+    case (WMI_REGDOMAIN_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
+        status = wmi_regDomain_event_rx(wmip, datap, len);
+        break;
+    case (WMI_PSTREAM_TIMEOUT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
+        status = wmi_pstream_timeout_event_rx(wmip, datap, len);
+            /* pstreams are fatpipe abstractions that get implicitly created.
+             * User apps only deal with thinstreams. creation of a thinstream
+             * by the user or data traffic flow in an AC triggers implicit
+             * pstream creation. Do we need to send this event to App..?
+             * no harm in sending it.
+             */
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_NEIGHBOR_REPORT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
+        status = wmi_neighborReport_event_rx(wmip, datap, len);
+        break;
+    case (WMI_SCAN_COMPLETE_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
+        status = wmi_scanComplete_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_CMDERROR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
+        status = wmi_errorEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_STATISTICS_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
+        status = wmi_statsEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_RSSI_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_ERROR_REPORT_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
+        status = wmi_reportErrorEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_OPT_RX_FRAME_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
+        status = wmi_opt_frame_event_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_ROAM_TBL_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
+        status = wmi_roam_tbl_event_rx(wmip, datap, len);
+        break;
+    case (WMI_EXTENSION_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
+        status = wmi_control_rx_xtnd(wmip, osbuf);
+        break;
+    case (WMI_CAC_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
+        status = wmi_cac_event_rx(wmip, datap, len);
+        break;
+    case (WMI_CHANNEL_CHANGE_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG));
+        status = wmi_channel_change_event_rx(wmip, datap, len);
+        break;
+    case (WMI_REPORT_ROAM_DATA_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
+        status = wmi_roam_data_event_rx(wmip, datap, len);
+        break;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+    case (WMI_TEST_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
+        status = wmi_tcmd_test_report_rx(wmip, datap, len);
+        break;
+#endif
+    case (WMI_GET_FIXRATES_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
+        status = wmi_ratemask_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_TX_RETRY_ERR_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
+        status = wmi_txRetryErrEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_SNR_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_snrThresholdEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_LQ_THRESHOLD_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
+        status = wmi_lqThresholdEvent_rx(wmip, datap, len);
+        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+        break;
+    case (WMI_APLIST_EVENTID):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
+        status = wmi_aplistEvent_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_KEEPALIVE_CMDID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
+        status = wmi_keepalive_reply_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_WOW_LIST_EVENTID):
+        status = wmi_get_wow_list_event_rx(wmip, datap, len);
+        break;
+    case (WMI_GET_PMKID_LIST_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
+        status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
+        break;
+    case (WMI_PSPOLL_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG));
+        status = wmi_pspoll_event_rx(wmip, datap, len);
+        break;
+    case (WMI_DTIMEXPIRY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG));
+        status = wmi_dtimexpiry_event_rx(wmip, datap, len);
+        break;
+    case (WMI_SET_PARAMS_REPLY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
+        status = wmi_set_params_event_rx(wmip, datap, len);
+        break;
+#ifdef ATH_AR6K_11N_SUPPORT
+    case (WMI_ADDBA_REQ_EVENTID):
+        status = wmi_addba_req_event_rx(wmip, datap, len);
+        break;
+    case (WMI_ADDBA_RESP_EVENTID):
+        status = wmi_addba_resp_event_rx(wmip, datap, len);
+        break;
+    case (WMI_DELBA_REQ_EVENTID):
+        status = wmi_delba_req_event_rx(wmip, datap, len);
+        break;
+	case (WMI_REPORT_BTCOEX_CONFIG_EVENTID):
+	    A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_CONFIG_EVENTID", DBGARG));
+    	status = wmi_btcoex_config_event_rx(wmip, datap, len);
+	    break;
+	case (WMI_REPORT_BTCOEX_STATS_EVENTID):
+	    A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_STATS_EVENTID", DBGARG));
+    	status = wmi_btcoex_stats_event_rx(wmip, datap, len);
+	    break;
+#endif
+    case (WMI_TX_COMPLETE_EVENTID):
+        {
+            int index;
+            TX_COMPLETE_MSG_V1 *pV1;
+            WMI_TX_COMPLETE_EVENT *pEv = (WMI_TX_COMPLETE_EVENT *)datap;
+            A_PRINTF("comp: %d %d %d\n", pEv->numMessages, pEv->msgLen, pEv->msgType);
+
+            for(index = 0 ; index < pEv->numMessages ; index++) {
+                pV1 = (TX_COMPLETE_MSG_V1 *)(datap + sizeof(WMI_TX_COMPLETE_EVENT) + index*sizeof(TX_COMPLETE_MSG_V1));
+                A_PRINTF("msg: %d %d %d %d\n", pV1->status, pV1->pktID, pV1->rateIdx, pV1->ackFailures);
+            }
+        }
+        break;
+    case (WMI_HCI_EVENT_EVENTID):
+        status = wmi_hci_event_rx(wmip, datap, len);
+        break;
+#ifdef WAPI_ENABLE
+    case (WMI_WAPI_REKEY_EVENTID):
+        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_WAPI_REKEY_EVENTID", DBGARG));
+        status = wmi_wapi_rekey_event_rx(wmip, datap, len);
+        break;
+#endif
+    default:
+        A_DPRINTF(DBG_WMI|DBG_ERROR,
+            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+        wmip->wmi_stats.cmd_id_err++;
+        status = A_ERROR;
+        break;
+    }
+
+    A_NETBUF_FREE(osbuf);
+
+    return status;
+}
+
+/* Send a "simple" wmi command -- one with no arguments */
+static A_STATUS
+wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid)
+{
+    void *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(0);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+
+/* Send a "simple" extended wmi command -- one with no arguments.
+   Enabling this command only if GPIO or profiling support is enabled.
+   This is to suppress warnings on some platforms */
+#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid)
+{
+    void *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(0);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+#endif
+
+static A_STATUS
+wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
+
+    if (len < sizeof(WMI_READY_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+    wmip->wmi_ready = TRUE;
+    A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability,
+                      ev->version);
+
+    return A_OK;
+}
+
+#define LE_READ_4(p)                            \
+    ((A_UINT32)                            \
+     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
+      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+
+static A_STATUS
+wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CONNECT_EVENT *ev;
+    A_UINT8 *pie,*peie;
+
+    if (len < sizeof(WMI_CONNECT_EVENT))
+    {
+        return A_EINVAL;
+    }
+    ev = (WMI_CONNECT_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+        DBGARG, ev->channel,
+        ev->bssid[0], ev->bssid[1], ev->bssid[2],
+        ev->bssid[3], ev->bssid[4], ev->bssid[5]));
+
+    A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
+
+    /* initialize pointer to start of assoc rsp IEs */
+    pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen +
+                            sizeof(A_UINT16)  +  /* capinfo*/
+                            sizeof(A_UINT16)  +  /* status Code */
+                            sizeof(A_UINT16)  ;  /* associd */
+
+    /* initialize pointer to end of assoc rsp IEs */
+    peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen;
+
+    while (pie < peie)
+    {
+        switch (*pie)
+        {
+            case IEEE80211_ELEMID_VENDOR:
+                if (iswmmoui(pie))
+                {
+                    if(iswmmparam (pie))
+                    {
+                        wmip->wmi_is_wmm_enabled = TRUE;
+                    }
+                }
+            break;
+        }
+
+        if (wmip->wmi_is_wmm_enabled)
+        {
+            break;
+        }
+        pie += pie[1] + 2;
+    }
+
+    A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
+                         ev->listenInterval, ev->beaconInterval,
+                         (NETWORK_TYPE) ev->networkType, ev->beaconIeLen,
+                         ev->assocReqLen, ev->assocRespLen,
+                         ev->assocInfo);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_REG_DOMAIN_EVENT *ev;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_REG_DOMAIN_EVENT *)datap;
+
+    A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_NEIGHBOR_REPORT_EVENT *ev;
+    int numAps;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
+    numAps = ev->numberOfAps;
+
+    if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
+        return A_EINVAL;
+    }
+
+    A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_DISCONNECT_EVENT *ev;
+
+    if (len < sizeof(WMI_DISCONNECT_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    ev = (WMI_DISCONNECT_EVENT *)datap;
+
+    A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
+
+    wmip->wmi_is_wmm_enabled = FALSE;
+    wmip->wmi_pair_crypto_type = NONE_CRYPT;
+    wmip->wmi_grp_crypto_type = NONE_CRYPT;
+
+    A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
+                            ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PEER_NODE_EVENT *ev;
+
+    if (len < sizeof(WMI_PEER_NODE_EVENT)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_PEER_NODE_EVENT *)datap;
+    if (ev->eventCode == PEER_NODE_JOIN_EVENT) {
+        A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG));
+    } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) {
+        A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG));
+    }
+
+    A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TKIP_MICERR_EVENT *ev;
+
+    if (len < sizeof(*ev)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    ev = (WMI_TKIP_MICERR_EVENT *)datap;
+    A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    bss_t *bss = NULL;
+    WMI_BSS_INFO_HDR *bih;
+    A_UINT8 *buf;
+    A_UINT32 nodeCachingAllowed = 1;
+    A_UCHAR cached_ssid_len = 0;
+    A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0};
+    A_UINT8 beacon_ssid_len = 0;
+
+    if (len <= sizeof(WMI_BSS_INFO_HDR)) {
+        return A_EINVAL;
+    }
+
+    bih = (WMI_BSS_INFO_HDR *)datap;
+    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+
+    if (bih->rssi > 0) {
+        if (NULL == bss)
+            return A_OK;  //no node found in the table, just drop the node with incorrect RSSI
+        else
+            bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX
+    }
+
+    A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
+    /* What is driver config for wlan node caching? */
+    if(ar6000_get_driver_cfg(wmip->wmi_devt,
+                    AR6000_DRIVER_CFG_GET_WLANNODECACHING,
+                    &nodeCachingAllowed) != A_OK) {
+        return A_EINVAL;
+    }
+
+    if(!nodeCachingAllowed) {
+        return A_OK;
+    }
+
+    buf = datap + sizeof(WMI_BSS_INFO_HDR);
+    len -= sizeof(WMI_BSS_INFO_HDR);
+
+    A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
+              "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG,
+              bih->channel, (unsigned char) bih->rssi, bih->bssid[0],
+              bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4],
+              bih->bssid[5]));
+
+    if(wps_enable && (bih->frameType == PROBERESP_FTYPE) )
+        return A_OK;
+
+    if (bss != NULL) {
+        /*
+         * Free up the node.  Not the most efficient process given
+         * we are about to allocate a new node but it is simple and should be
+         * adequate.
+         */
+
+        /* In case of hidden AP, beacon will not have ssid,
+         * but a directed probe response will have it,
+         * so cache the probe-resp-ssid if already present. */
+        if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType))
+        {
+            A_UCHAR *ie_ssid;
+
+            ie_ssid = bss->ni_cie.ie_ssid;
+            if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0))
+            {
+                cached_ssid_len = ie_ssid[1];
+                memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len);
+            }
+        }
+
+        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+    }
+
+    /*  beacon/probe response frame format
+     *  [8] time stamp
+     *  [2] beacon interval
+     *  [2] capability information
+     *  [tlv] ssid */
+    beacon_ssid_len = buf[SSID_IE_LEN_INDEX];
+
+    /* If ssid is cached for this hidden AP, then change buffer len accordingly. */
+    if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+        (0 != cached_ssid_len) &&
+        (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+    {
+        len += (cached_ssid_len - beacon_ssid_len);
+    }
+
+    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+    if (bss == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    bss->ni_snr        = bih->snr;
+    bss->ni_rssi       = bih->rssi;
+    A_ASSERT(bss->ni_buf != NULL);
+
+    /* In case of hidden AP, beacon will not have ssid,
+     * but a directed probe response will have it,
+     * so place the cached-ssid(probe-resp) in the bssinfo. */
+    if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+         (0 != cached_ssid_len) &&
+         (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+    {
+        A_UINT8 *ni_buf = bss->ni_buf;
+        int buf_len = len;
+
+        /* copy the first 14 bytes such as
+         * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */
+        A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1);
+
+        ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len;
+        ni_buf += (SSID_IE_LEN_INDEX + 1);
+
+        buf += (SSID_IE_LEN_INDEX + 1);
+        buf_len -= (SSID_IE_LEN_INDEX + 1);
+
+        /* copy the cached ssid */
+        A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len);
+        ni_buf += cached_ssid_len;
+
+        buf += beacon_ssid_len;
+        buf_len -= beacon_ssid_len;
+
+        if (cached_ssid_len > beacon_ssid_len)
+            buf_len -= (cached_ssid_len - beacon_ssid_len);
+
+        /* now copy the rest of bytes */
+        A_MEMCPY(ni_buf, buf, buf_len);
+    }
+    else
+        A_MEMCPY(bss->ni_buf, buf, len);
+
+    bss->ni_framelen = len;
+    if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
+        wlan_node_free(bss);
+        return A_EINVAL;
+    }
+
+    /*
+     * Update the frequency in ie_chan, overwriting of channel number
+     * which is done in wlan_parse_beacon
+     */
+    bss->ni_cie.ie_chan = bih->channel;
+    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    bss_t *bss;
+    WMI_OPT_RX_INFO_HDR *bih;
+    A_UINT8 *buf;
+
+    if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
+        return A_EINVAL;
+    }
+
+    bih = (WMI_OPT_RX_INFO_HDR *)datap;
+    buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
+    len -= sizeof(WMI_OPT_RX_INFO_HDR);
+
+    A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
+        bih->bssid[4], bih->bssid[5]));
+
+    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+    if (bss != NULL) {
+        /*
+         * Free up the node.  Not the most efficient process given
+         * we are about to allocate a new node but it is simple and should be
+         * adequate.
+         */
+        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+    }
+
+    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+    if (bss == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    bss->ni_snr        = bih->snr;
+    bss->ni_cie.ie_chan = bih->channel;
+    A_ASSERT(bss->ni_buf != NULL);
+    A_MEMCPY(bss->ni_buf, buf, len);
+    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+    return A_OK;
+}
+
+    /* This event indicates inactivity timeout of a fatpipe(pstream)
+     * at the target
+     */
+static A_STATUS
+wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PSTREAM_TIMEOUT_EVENT *ev;
+
+    if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
+        return A_EINVAL;
+    }
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
+
+    ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
+
+        /* When the pstream (fat pipe == AC) timesout, it means there were no
+         * thinStreams within this pstream & it got implicitly created due to
+         * data flow on this AC. We start the inactivity timer only for
+         * implicitly created pstream. Just reset the host state.
+     */
+        /* Set the activeTsids for this AC to 0 */
+    LOCK_WMI(wmip);
+    wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
+    wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
+    UNLOCK_WMI(wmip);
+
+        /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
+    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_BIT_RATE_REPLY *reply;
+    A_INT32 rate;
+    A_UINT32 sgi,index;
+    /* 54149:
+     * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY.
+     * since there is difference in the length and to avoid returning
+     * error value.
+     */
+    if (len < sizeof(WMI_BIT_RATE_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_BIT_RATE_REPLY *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
+
+    if (reply->rateIndex == (A_INT8) RATE_AUTO) {
+        rate = RATE_AUTO;
+    } else {
+        // the SGI state is stored as the MSb of the rateIndex
+        index = reply->rateIndex & 0x7f;
+        sgi = (reply->rateIndex & 0x80)? 1:0;
+        rate = wmi_rateTable[index][sgi];
+    }
+
+    A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
+    return A_OK;
+}
+
+static A_STATUS
+wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_FIX_RATES_REPLY *reply;
+
+    if (len < sizeof(WMI_FIX_RATES_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_FIX_RATES_REPLY *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
+
+    A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CHANNEL_LIST_REPLY *reply;
+
+    if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CHANNEL_LIST_REPLY *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
+                          reply->channelList);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TX_PWR_REPLY *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TX_PWR_REPLY *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
+
+    return A_OK;
+}
+static A_STATUS
+wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_GET_KEEPALIVE_CMD *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_GET_KEEPALIVE_CMD *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETOPENREQ_EVENT *dsetopenreq;
+
+    if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
+        return A_EINVAL;
+    }
+    dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
+    A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
+                        dsetopenreq->dset_id,
+                        dsetopenreq->targ_dset_handle,
+                        dsetopenreq->targ_reply_fn,
+                        dsetopenreq->targ_reply_arg);
+
+    return A_OK;
+}
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS
+wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETCLOSE_EVENT *dsetclose;
+
+    if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
+    A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_DSETDATAREQ_EVENT *dsetdatareq;
+
+    if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
+    A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
+                         dsetdatareq->access_cookie,
+                         dsetdatareq->offset,
+                         dsetdatareq->length,
+                         dsetdatareq->targ_buf,
+                         dsetdatareq->targ_reply_fn,
+                         dsetdatareq->targ_reply_arg);
+
+    return A_OK;
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+static A_STATUS
+wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_SCAN_COMPLETE_EVENT *ev;
+
+    ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
+    A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status);
+    is_probe_ssid = FALSE;
+
+    return A_OK;
+}
+
+/*
+ * Target is reporting a programming error.  This is for
+ * developer aid only.  Target only checks a few common violations
+ * and it is responsibility of host to do all error checking.
+ * Behavior of target after wmi error event is undefined.
+ * A reset is recommended.
+ */
+static A_STATUS
+wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CMD_ERROR_EVENT *ev;
+
+    ev = (WMI_CMD_ERROR_EVENT *)datap;
+    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
+    switch (ev->errorCode) {
+    case (INVALID_PARAM):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
+        break;
+    case (ILLEGAL_STATE):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
+        break;
+    case (INTERNAL_ERROR):
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
+        break;
+    }
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, datap, len);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_RSSI_THRESHOLD_EVENT *reply;
+    WMI_RSSI_THRESHOLD_VAL newThreshold;
+    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+    A_UINT8 upper_rssi_threshold, lower_rssi_threshold;
+    A_INT16 rssi;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+    newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range;
+    rssi = reply->rssi;
+
+    /*
+     * Identify the threshold breached and communicate that to the app. After
+     * that install a new set of thresholds based on the signal quality
+     * reported by the target
+     */
+    if (newThreshold) {
+        /* Upper threshold breached */
+        if (rssi < sq_thresh->upper_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: "
+                      " %d\n", DBGARG, rssi));
+        } else if ((rssi < sq_thresh->upper_threshold[1]) &&
+                   (rssi >= sq_thresh->upper_threshold[0]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD1_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[2]) &&
+                   (rssi >= sq_thresh->upper_threshold[1]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD2_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[3]) &&
+                   (rssi >= sq_thresh->upper_threshold[2]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD3_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[4]) &&
+                   (rssi >= sq_thresh->upper_threshold[3]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD4_ABOVE;
+        } else if ((rssi < sq_thresh->upper_threshold[5]) &&
+                   (rssi >= sq_thresh->upper_threshold[4]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD5_ABOVE;
+        } else if (rssi >= sq_thresh->upper_threshold[5]) {
+            newThreshold = WMI_RSSI_THRESHOLD6_ABOVE;
+        }
+    } else {
+        /* Lower threshold breached */
+        if (rssi > sq_thresh->lower_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: "
+                      "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0]));
+        } else if ((rssi > sq_thresh->lower_threshold[1]) &&
+                   (rssi <= sq_thresh->lower_threshold[0]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD6_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[2]) &&
+                   (rssi <= sq_thresh->lower_threshold[1]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD5_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[3]) &&
+                   (rssi <= sq_thresh->lower_threshold[2]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD4_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[4]) &&
+                   (rssi <= sq_thresh->lower_threshold[3]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD3_BELOW;
+        } else if ((rssi > sq_thresh->lower_threshold[5]) &&
+                   (rssi <= sq_thresh->lower_threshold[4]))
+        {
+            newThreshold = WMI_RSSI_THRESHOLD2_BELOW;
+        } else if (rssi <= sq_thresh->lower_threshold[5]) {
+            newThreshold = WMI_RSSI_THRESHOLD1_BELOW;
+        }
+    }
+    /* Calculate and install the next set of thresholds */
+    lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh,
+                                      sq_thresh->lower_threshold_valid_count);
+    upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh,
+                                      sq_thresh->upper_threshold_valid_count);
+    /* Issue a wmi command to install the thresholds */
+    cmd.thresholdAbove1_Val = upper_rssi_threshold;
+    cmd.thresholdBelow1_Val = lower_rssi_threshold;
+    cmd.weight = sq_thresh->weight;
+    cmd.pollTime = sq_thresh->polling_interval;
+
+    rssi_event_value = rssi;
+
+    if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n",
+                  DBGARG));
+    }
+
+    A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ERROR_REPORT_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CAC_EVENT *reply;
+    WMM_TSPEC_IE *tspec_ie;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CAC_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) &&
+        (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) {
+        tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion);
+
+        wmi_delete_pstream_cmd(wmip, reply->ac,
+                (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK);
+    }
+    else if (reply->cac_indication == CAC_INDICATION_NO_RESP) {
+        A_UINT16 activeTsids;
+        A_UINT8 i;
+
+        /* following assumes that there is only one outstanding ADDTS request
+           when this event is received */
+        LOCK_WMI(wmip);
+        activeTsids = wmip->wmi_streamExistsForAC[reply->ac];
+        UNLOCK_WMI(wmip);
+
+        for (i = 0; i < sizeof(activeTsids) * 8; i++) {
+            if ((activeTsids >> i) & 1) {
+                break;
+            }
+        }
+        if (i < (sizeof(activeTsids) * 8)) {
+            wmi_delete_pstream_cmd(wmip, reply->ac, i);
+        }
+    }
+
+    A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
+                reply->cac_indication, reply->statusCode,
+                reply->tspecSuggestion);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_CHANNEL_CHANGE_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_CHANNEL_CHANGE_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel,
+                               reply->newChannel);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_HB_CHALLENGE_RESP_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
+
+    A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ROAM_TBL *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ROAM_TBL *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_TARGET_ROAM_DATA *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_TARGET_ROAM_DATA *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) {
+        return A_EINVAL;
+    }
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_SNR_THRESHOLD_EVENT *reply;
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+    WMI_SNR_THRESHOLD_VAL newThreshold;
+    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+    A_UINT8 upper_snr_threshold, lower_snr_threshold;
+    A_INT16 snr;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range;
+    snr = reply->snr;
+    /*
+     * Identify the threshold breached and communicate that to the app. After
+     * that install a new set of thresholds based on the signal quality
+     * reported by the target
+     */
+    if (newThreshold) {
+        /* Upper threshold breached */
+        if (snr < sq_thresh->upper_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: "
+                     "%d\n", DBGARG, snr));
+        } else if ((snr < sq_thresh->upper_threshold[1]) &&
+                   (snr >= sq_thresh->upper_threshold[0]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD1_ABOVE;
+        } else if ((snr < sq_thresh->upper_threshold[2]) &&
+                   (snr >= sq_thresh->upper_threshold[1]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD2_ABOVE;
+        } else if ((snr < sq_thresh->upper_threshold[3]) &&
+                   (snr >= sq_thresh->upper_threshold[2]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD3_ABOVE;
+        } else if (snr >= sq_thresh->upper_threshold[3]) {
+            newThreshold = WMI_SNR_THRESHOLD4_ABOVE;
+        }
+    } else {
+        /* Lower threshold breached */
+        if (snr > sq_thresh->lower_threshold[0]) {
+            A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: "
+                      "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0]));
+        } else if ((snr > sq_thresh->lower_threshold[1]) &&
+                   (snr <= sq_thresh->lower_threshold[0]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD4_BELOW;
+        } else if ((snr > sq_thresh->lower_threshold[2]) &&
+                   (snr <= sq_thresh->lower_threshold[1]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD3_BELOW;
+        } else if ((snr > sq_thresh->lower_threshold[3]) &&
+                   (snr <= sq_thresh->lower_threshold[2]))
+        {
+            newThreshold = WMI_SNR_THRESHOLD2_BELOW;
+        } else if (snr <= sq_thresh->lower_threshold[3]) {
+            newThreshold = WMI_SNR_THRESHOLD1_BELOW;
+        }
+    }
+
+    /* Calculate and install the next set of thresholds */
+    lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh,
+                                      sq_thresh->lower_threshold_valid_count);
+    upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh,
+                                      sq_thresh->upper_threshold_valid_count);
+
+    /* Issue a wmi command to install the thresholds */
+    cmd.thresholdAbove1_Val = upper_snr_threshold;
+    cmd.thresholdBelow1_Val = lower_snr_threshold;
+    cmd.weight = sq_thresh->weight;
+    cmd.pollTime = sq_thresh->polling_interval;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n"
+              ,DBGARG, snr, newThreshold, lower_snr_threshold,
+              upper_snr_threshold));
+
+    snr_event_value = snr;
+
+    if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n",
+                  DBGARG));
+    }
+    A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_LQ_THRESHOLD_EVENT *reply;
+
+    if (len < sizeof(*reply)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt,
+                                (WMI_LQ_THRESHOLD_VAL) reply->range,
+                                reply->lq);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_UINT16 ap_info_entry_size;
+    WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
+    WMI_AP_INFO_V1 *ap_info_v1;
+    A_UINT8 i;
+
+    if (len < sizeof(WMI_APLIST_EVENT)) {
+        return A_EINVAL;
+    }
+
+    if (ev->apListVer == APLIST_VER1) {
+        ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
+        ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
+    } else {
+        return A_EINVAL;
+    }
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
+    if (len < (int)(sizeof(WMI_APLIST_EVENT) +
+              (ev->numAP - 1) * ap_info_entry_size))
+    {
+        return A_EINVAL;
+    }
+
+    /*
+     * AP List Ver1 Contents
+     */
+    for (i = 0; i < ev->numAP; i++) {
+        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
+                    "Channel %d\n", i,
+                   ap_info_v1->bssid[0], ap_info_v1->bssid[1],
+                   ap_info_v1->bssid[2], ap_info_v1->bssid[3],
+                   ap_info_v1->bssid[4], ap_info_v1->bssid[5],
+                   ap_info_v1->channel));
+        ap_info_v1++;
+    }
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_UINT32 dropped;
+
+    dropped = *((A_UINT32 *)datap);
+    datap += sizeof(dropped);
+    len -= sizeof(dropped);
+    A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, (A_INT8*)datap, len);
+    return A_OK;
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS
+wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
+        gpio_intr->intr_mask, gpio_intr->input_values));
+
+    A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
+        gpio_data->reg_id, gpio_data->value));
+
+    A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_GPIO_ACK_RX();
+
+    return A_OK;
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+/*
+ * Called to send a wmi command. Command specific data is already built
+ * on osbuf and current osbuf->data points to it.
+ */
+A_STATUS
+wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+               WMI_SYNC_FLAG syncflag)
+{
+    A_STATUS status;
+#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID))
+    WMI_CMD_HDR         *cHdr;
+    HTC_ENDPOINT_ID     eid  = wmip->wmi_endpoint_id;
+
+    A_ASSERT(osbuf != NULL);
+
+    if (syncflag >= END_WMIFLAG) {
+        A_NETBUF_FREE(osbuf);
+        return A_EINVAL;
+    }
+
+    if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+        /*
+         * We want to make sure all data currently queued is transmitted before
+         * the cmd execution.  Establish a new sync point.
+         */
+        wmi_sync_point(wmip);
+    }
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        return A_NO_MEMORY;
+    }
+
+    cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    cHdr->commandId = (A_UINT16) cmdId;
+    cHdr->info1 = 0; // added for virtual interface
+
+    /*
+     * Only for OPT_TX_CMD, use BE endpoint.
+     */
+    if (IS_OPT_TX_CMD(cmdId)) {
+        if ((status=wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE, FALSE,0,NULL)) != A_OK) {
+            A_NETBUF_FREE(osbuf);
+            return status;
+        }
+        eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE);
+    }
+    A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid);
+
+    if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+        /*
+         * We want to make sure all new data queued waits for the command to
+         * execute. Establish a new sync point.
+         */
+        wmi_sync_point(wmip);
+    }
+    return (A_OK);
+#undef IS_OPT_TX_CMD
+}
+
+A_STATUS
+wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+                  WMI_SYNC_FLAG syncflag)
+{
+    WMIX_CMD_HDR     *cHdr;
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+        A_NETBUF_FREE(osbuf);
+        return A_NO_MEMORY;
+    }
+
+    cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+    cHdr->commandId = (A_UINT32) cmdId;
+
+    return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
+}
+
+A_STATUS
+wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
+                DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
+                CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
+                CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen,
+                int ssidLength, A_UCHAR *ssid,
+                A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
+{
+    void *osbuf;
+    WMI_CONNECT_CMD *cc;
+
+    if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
+        return A_EINVAL;
+    }
+    if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
+
+    cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cc, sizeof(*cc));
+
+    if (ssidLength)
+    {
+        A_MEMCPY(cc->ssid, ssid, ssidLength);
+    }
+
+    cc->ssidLength          = ssidLength;
+    cc->networkType         = netType;
+    cc->dot11AuthMode       = dot11AuthMode;
+    cc->authMode            = authMode;
+    cc->pairwiseCryptoType  = pairwiseCrypto;
+    cc->pairwiseCryptoLen   = pairwiseCryptoLen;
+    cc->groupCryptoType     = groupCrypto;
+    cc->groupCryptoLen      = groupCryptoLen;
+    cc->channel             = channel;
+    cc->ctrl_flags          = ctrl_flags;
+
+    if (bssid != NULL) {
+        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+    }
+   
+    wmip->wmi_pair_crypto_type  = pairwiseCrypto;
+    wmip->wmi_grp_crypto_type   = groupCrypto;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
+{
+    void *osbuf;
+    WMI_RECONNECT_CMD *cc;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
+
+    cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cc, sizeof(*cc));
+
+    cc->channel = channel;
+
+    if (bssid != NULL) {
+        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disconnect_cmd(struct wmi_t *wmip)
+{
+    A_STATUS status;
+
+    /* Bug fix for 24817(elevator bug) - the disconnect command does not
+       need to do a SYNC before.*/
+    status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID);
+
+    return status;
+}
+
+A_STATUS
+wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+                  A_BOOL forceFgScan, A_BOOL isLegacy,
+                  A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+                  A_INT8 numChan, A_UINT16 *channelList)
+{
+    void *osbuf;
+    WMI_START_SCAN_CMD *sc;
+    A_INT8 size;
+
+    size = sizeof (*sc);
+
+    if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
+        return A_EINVAL;
+    }
+
+    if (numChan) {
+        if (numChan > WMI_MAX_CHANNELS) {
+            return A_EINVAL;
+        }
+        size += sizeof(A_UINT16) * (numChan - 1);
+    }
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
+    sc->scanType = scanType;
+    sc->forceFgScan = forceFgScan;
+    sc->isLegacy = isLegacy;
+    sc->homeDwellTime = homeDwellTime;
+    sc->forceScanInterval = forceScanInterval;
+    sc->numChannels = numChan;
+    if (numChan) {
+        A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16));
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+                   A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+                   A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
+                   A_UINT16 pas_chdw_msec,
+                   A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+                   A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid)
+{
+    void *osbuf;
+    WMI_SCAN_PARAMS_CMD *sc;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*sc));
+
+    sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(sc, sizeof(*sc));
+    sc->fg_start_period  = fg_start_sec;
+    sc->fg_end_period    = fg_end_sec;
+    sc->bg_period        = bg_sec;
+    sc->minact_chdwell_time = minact_chdw_msec;
+    sc->maxact_chdwell_time = maxact_chdw_msec;
+    sc->pas_chdwell_time = pas_chdw_msec;
+    sc->shortScanRatio   = shScanRatio;
+    sc->scanCtrlFlags    = scanCtrlFlags;
+    sc->max_dfsch_act_time = max_dfsch_act_time;
+    sc->maxact_scan_per_ssid = maxact_scan_per_ssid;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
+{
+    void *osbuf;
+    WMI_BSS_FILTER_CMD *cmd;
+
+    if (filter >= LAST_BSS_FILTER) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->bssFilter = filter;
+    cmd->ieMask = ieMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+                   A_UINT8 ssidLength, A_UCHAR *ssid)
+{
+    void *osbuf;
+    WMI_PROBED_SSID_CMD *cmd;
+
+    if (index > MAX_PROBED_SSID_INDEX) {
+        return A_EINVAL;
+    }
+    if (ssidLength > sizeof(cmd->ssid)) {
+        return A_EINVAL;
+    }
+    if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
+        return A_EINVAL;
+    }
+    if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
+        return A_EINVAL;
+    }
+
+    if (flag & SPECIFIC_SSID_FLAG) {
+        is_probe_ssid = TRUE;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->entryIndex = index;
+    cmd->flag       = flag;
+    cmd->ssidLength = ssidLength;
+    A_MEMCPY(cmd->ssid, ssid, ssidLength);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
+{
+    void *osbuf;
+    WMI_LISTEN_INT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->listenInterval = listenInterval;
+    cmd->numBeacons = listenBeacons;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
+{
+    void *osbuf;
+    WMI_BMISS_TIME_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->bmissTime = bmissTime;
+    cmd->numBeacons =  bmissBeacons;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+                     A_UINT8 ieLen, A_UINT8 *ieInfo)
+{
+    void *osbuf;
+    WMI_SET_ASSOC_INFO_CMD *cmd;
+    A_UINT16 cmdLen;
+
+    cmdLen = sizeof(*cmd) + ieLen - 1;
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+
+    cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, cmdLen);
+    cmd->ieType = ieType;
+    cmd->bufferSize = ieLen;
+    A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
+{
+    void *osbuf;
+    WMI_POWER_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->powerMode = powerMode;
+    wmip->wmi_powerMode = powerMode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+                   A_UINT16 atim_windows, A_UINT16 timeout_value)
+{
+    void *osbuf;
+    WMI_IBSS_PM_CAPS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->power_saving = pmEnable;
+    cmd->ttl = ttl;
+    cmd->atim_windows = atim_windows;
+    cmd->timeout_value = timeout_value;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+                   A_UINT32 ps_period, A_UINT8 sleep_period)
+{
+    void *osbuf;
+    WMI_AP_PS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_AP_PS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->psType = psType;
+    cmd->idle_time = idle_time;
+    cmd->ps_period = ps_period;
+    cmd->sleep_period = sleep_period;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AP_PS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+                 A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+                 A_UINT16 tx_wakeup_policy, A_UINT16 num_tx_to_wakeup,
+                 A_UINT16 ps_fail_event_policy)
+{
+    void *osbuf;
+    WMI_POWER_PARAMS_CMD *pm;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*pm));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*pm));
+
+    pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(pm, sizeof(*pm));
+    pm->idle_period   = idlePeriod;
+    pm->pspoll_number = psPollNum;
+    pm->dtim_policy   = dtimPolicy;
+    pm->tx_wakeup_policy = tx_wakeup_policy;
+    pm->num_tx_to_wakeup = num_tx_to_wakeup;
+    pm->ps_fail_event_policy = ps_fail_event_policy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
+{
+    void *osbuf;
+    WMI_DISC_TIMEOUT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->disconnectTimeout = timeout;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
+               A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
+               A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr,
+               WMI_SYNC_FLAG sync_flag)
+{
+    void *osbuf;
+    WMI_ADD_CIPHER_KEY_CMD *cmd;
+
+    if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
+        (keyMaterial == NULL))
+    {
+        return A_EINVAL;
+    }
+
+    if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keyIndex = keyIndex;
+    cmd->keyType  = keyType;
+    cmd->keyUsage = keyUsage;
+    cmd->keyLength = keyLength;
+    A_MEMCPY(cmd->key, keyMaterial, keyLength);
+#ifdef WAPI_ENABLE
+    if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) {
+#else
+    if (NULL != keyRSC) {
+#endif // WAPI_ENABLE
+        A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
+    }
+    cmd->key_op_ctrl = key_op_ctrl;
+
+    if(macAddr) {
+        A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
+}
+
+A_STATUS
+wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
+{
+    void *osbuf;
+    WMI_ADD_KRK_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_krk_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID);
+}
+
+A_STATUS
+wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
+{
+    void *osbuf;
+    WMI_DELETE_CIPHER_KEY_CMD *cmd;
+
+    if (keyIndex > WMI_MAX_KEY_INDEX) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keyIndex = keyIndex;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+                 A_BOOL set)
+{
+    void *osbuf;
+    WMI_SET_PMKID_CMD *cmd;
+
+    if (bssid == NULL) {
+        return A_EINVAL;
+    }
+
+    if ((set == TRUE) && (pmkId == NULL)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+    if (set == TRUE) {
+        A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
+        cmd->enable = PMKID_ENABLE;
+    } else {
+        A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
+        cmd->enable = PMKID_DISABLE;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
+{
+    void *osbuf;
+    WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+                        WMI_SET_AKMP_PARAMS_CMD *akmpParams)
+{
+    void *osbuf;
+    WMI_SET_AKMP_PARAMS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->akmpInfo = akmpParams->akmpInfo;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+                       WMI_SET_PMKID_LIST_CMD *pmkInfo)
+{
+    void *osbuf;
+    WMI_SET_PMKID_LIST_CMD *cmd;
+    A_UINT16 cmdLen;
+    A_UINT8 i;
+
+    cmdLen = sizeof(pmkInfo->numPMKID) +
+             pmkInfo->numPMKID * sizeof(WMI_PMKID);
+
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+    cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->numPMKID = pmkInfo->numPMKID;
+
+    for (i = 0; i < cmd->numPMKID; i++) {
+        A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
+                 WMI_PMKID_LEN);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID);
+}
+
+A_STATUS
+wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+    WMI_DATA_HDR     *dtHdr;
+
+    A_ASSERT( eid != wmip->wmi_endpoint_id);
+    A_ASSERT(osbuf != NULL);
+
+    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+        return A_NO_MEMORY;
+    }
+
+    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+    dtHdr->info =
+      (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid));
+
+    return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid));
+}
+
+typedef struct _WMI_DATA_SYNC_BUFS {
+    A_UINT8            trafficClass;
+    void               *osbuf;
+}WMI_DATA_SYNC_BUFS;
+
+static A_STATUS
+wmi_sync_point(struct wmi_t *wmip)
+{
+    void *cmd_osbuf;
+    WMI_SYNC_CMD *cmd;
+    WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
+    A_UINT8 i,numPriStreams=0;
+    A_STATUS status = A_OK;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    memset(dataSyncBufs,0,sizeof(dataSyncBufs));
+
+    /* lock out while we walk through the priority list and assemble our local array */
+    LOCK_WMI(wmip);
+
+    for (i=0; i < WMM_NUM_AC ; i++) {
+        if (wmip->wmi_fatPipeExists & (1 << i)) {
+            numPriStreams++;
+            dataSyncBufs[numPriStreams-1].trafficClass = i;
+        }
+    }
+
+    UNLOCK_WMI(wmip);
+
+    /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
+
+    do {
+        /*
+         * We allocate all network buffers needed so we will be able to
+         * send all required frames.
+         */
+        cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+        if (cmd_osbuf == NULL) {
+            status = A_NO_MEMORY;
+            break;
+    }
+
+        A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd));
+
+        cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf));
+        A_MEMZERO(cmd, sizeof(*cmd));
+
+        /* In the SYNC cmd sent on the control Ep, send a bitmap of the data
+         * eps on which the Data Sync will be sent
+         */
+        cmd->dataSyncMap = wmip->wmi_fatPipeExists;
+
+        for (i=0; i < numPriStreams ; i++) {
+            dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
+            if (dataSyncBufs[i].osbuf == NULL) {
+                status = A_NO_MEMORY;
+                break;
+            }
+        } //end for
+
+        /* if Buffer allocation for any of the dataSync fails, then do not
+         * send the Synchronize cmd on the control ep
+         */
+        if (A_FAILED(status)) {
+            break;
+        }
+
+    /*
+     * Send sync cmd followed by sync data messages on all endpoints being
+     * used
+     */
+    status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
+                          NO_SYNC_WMIFLAG);
+
+        if (A_FAILED(status)) {
+            break;
+    }
+            /* cmd buffer sent, we no longer own it */
+        cmd_osbuf = NULL;
+
+        for(i=0; i < numPriStreams; i++) {
+            A_ASSERT(dataSyncBufs[i].osbuf != NULL);
+            status = wmi_dataSync_send(wmip,
+                                       dataSyncBufs[i].osbuf,
+                                       A_WMI_Ac2EndpointID(wmip->wmi_devt,
+                                                            dataSyncBufs[i].
+                                                            trafficClass)
+                                      );
+
+            if (A_FAILED(status)) {
+                break;
+            }
+            /* we don't own this buffer anymore, NULL it out of the array so it
+             * won't get cleaned up */
+            dataSyncBufs[i].osbuf = NULL;
+        } //end for
+
+    } while(FALSE);
+
+    /* free up any resources left over (possibly due to an error) */
+
+    if (cmd_osbuf != NULL) {
+        A_NETBUF_FREE(cmd_osbuf);
+            }
+
+    for (i = 0; i < numPriStreams; i++) {
+        if (dataSyncBufs[i].osbuf != NULL) {
+            A_NETBUF_FREE(dataSyncBufs[i].osbuf);
+        }
+    }
+
+    return (status);
+}
+
+A_STATUS
+wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
+{
+    void *osbuf;
+    WMI_CREATE_PSTREAM_CMD *cmd;
+    A_UINT8 fatPipeExistsForAC=0;
+    A_INT32 minimalPHY = 0;
+    A_INT32 nominalPHY = 0;
+
+    /* Validate all the parameters. */
+    if( !((params->userPriority < 8) &&
+         (params->userPriority <= 0x7) &&
+         (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass)  &&
+         (params->trafficDirection == UPLINK_TRAFFIC ||
+            params->trafficDirection == DNLINK_TRAFFIC ||
+            params->trafficDirection == BIDIR_TRAFFIC) &&
+         (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
+            params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
+         (params->voicePSCapability == DISABLE_FOR_THIS_AC  ||
+            params->voicePSCapability == ENABLE_FOR_THIS_AC ||
+            params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
+         (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
+    {
+        return  A_EINVAL;
+    }
+
+    //
+    // check nominal PHY rate is >= minimalPHY, so that DUT
+    // can allow TSRS IE
+    //
+
+    // get the physical rate
+    minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps
+
+    // check minimal phy < nominal phy rate
+    //
+    if (params->nominalPHY >= minimalPHY)
+    {
+        nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps
+        A_DPRINTF(DBG_WMI,
+                  (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG,
+                  minimalPHY, nominalPHY));
+
+        params->nominalPHY = nominalPHY;
+    }
+    else
+    {
+        params->nominalPHY = 0;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Sending create_pstream_cmd: ac=%d    tsid:%d\n", DBGARG,
+        params->trafficClass, params->tsid));
+
+    cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd, params, sizeof(*cmd));
+
+        /* this is an implicitly created Fat pipe */
+    if ((A_UINT32)params->tsid == (A_UINT32)WMI_IMPLICIT_PSTREAM) {
+        LOCK_WMI(wmip);
+        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+        UNLOCK_WMI(wmip);
+    } else {
+            /* this is an explicitly created thin stream within a fat pipe */
+    LOCK_WMI(wmip);
+        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+    wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
+            /* if a thinstream becomes active, the fat pipe automatically
+            * becomes active
+            */
+        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+    UNLOCK_WMI(wmip);
+    }
+
+        /* Indicate activty change to driver layer only if this is the
+         * first TSID to get created in this AC explicitly or an implicit
+         * fat pipe is getting created.
+         */
+    if (!fatPipeExistsForAC) {
+        A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
+    }
+
+    /* mike: should be SYNC_BEFORE_WMIFLAG */
+    return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
+{
+    void *osbuf;
+    WMI_DELETE_PSTREAM_CMD *cmd;
+    A_STATUS status;
+    A_UINT16 activeTsids=0;
+
+    /* validate the parameters */
+    if (trafficClass > 3) {
+        A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass));
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->trafficClass = trafficClass;
+    cmd->tsid = tsid;
+
+    LOCK_WMI(wmip);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+        /* Check if the tsid was created & exists */
+    if (!(activeTsids & (1<<tsid))) {
+
+        A_NETBUF_FREE(osbuf);
+        A_DPRINTF(DBG_WMI,
+        (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
+            /* TODO: return a more appropriate err code */
+        return A_ERROR;
+    }
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
+
+    status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
+                         SYNC_BEFORE_WMIFLAG));
+
+    LOCK_WMI(wmip);
+    wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+
+        /* Indicate stream inactivity to driver layer only if all tsids
+         * within this AC are deleted.
+         */
+    if(!activeTsids) {
+        A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
+        wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
+    }
+
+    return status;
+}
+
+A_STATUS
+wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask)
+{
+    void *osbuf;
+    WMI_FRAME_RATES_CMD *cmd;
+    A_UINT8 frameType;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT " type %02X, subType %02X, rateMask %04x\n", DBGARG, type, subType, rateMask));
+
+    if((type != IEEE80211_FRAME_TYPE_MGT && type != IEEE80211_FRAME_TYPE_CTL) ||
+        (subType > 15)){
+
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    frameType = (A_UINT8)((subType << 4) | type);
+
+    cmd->bEnableMask = bEnable;
+    cmd->frameType = frameType;
+    cmd->frameRateMask = rateMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * used to set the bit rate.  rate is in Kbps.  If rate == -1
+ * then auto selection is used.
+ */
+A_STATUS
+wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate)
+{
+    void *osbuf;
+    WMI_BIT_RATE_CMD *cmd;
+    A_INT8 drix, mrix, crix;
+
+    if (dataRate != -1) {
+        drix = wmi_validate_bitrate(wmip, dataRate);
+        if(drix == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        drix = -1;
+    }
+
+    if (mgmtRate != -1) {
+        mrix = wmi_validate_bitrate(wmip, mgmtRate);
+        if(mrix == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        mrix = -1;
+    }
+    if (ctlRate != -1) {
+        crix = wmi_validate_bitrate(wmip, ctlRate);
+        if(crix == A_EINVAL){
+            return A_EINVAL;
+        }
+    } else {
+        crix = -1;
+    }
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->rateIndex = drix;
+    cmd->mgmtRateIndex = mrix;
+    cmd->ctlRateIndex  = crix;
+
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_bitrate_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID);
+}
+
+/*
+ * Returns TRUE iff the given rate index is legal in the current PHY mode.
+ */
+A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex)
+{
+    WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode;
+    A_BOOL isValid = TRUE;
+    switch(phyMode) {
+        case WMI_11A_MODE:
+            if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
+                isValid = FALSE;
+            }
+            break;
+
+        case WMI_11B_MODE:
+            if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
+                isValid = FALSE;
+            }
+            break;
+
+        case WMI_11GONLY_MODE:
+            if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
+                isValid = FALSE;
+            }
+            break;
+
+        case WMI_11G_MODE:
+        case WMI_11AG_MODE:        
+            if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
+                isValid = FALSE;
+            }
+            break;        
+        default:
+            A_ASSERT(FALSE);
+            break;
+    }
+
+    return isValid;
+}
+
+A_INT8
+wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
+{
+    A_INT8 i;
+    if (rate != -1)
+    {
+        for (i=0;;i++)
+        {
+            if (wmi_rateTable[(A_UINT32) i][0] == 0) {
+                return A_EINVAL;
+            }
+            if (wmi_rateTable[(A_UINT32) i][0] == rate) {
+                break;
+            }
+        }
+    }
+    else{
+     i = -1;
+    }
+
+    if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) {
+        return A_EINVAL;
+    }
+
+    return i;
+}
+
+A_STATUS
+wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask)
+{
+    void *osbuf;
+    WMI_FIX_RATES_CMD *cmd;
+#if 0
+    A_INT32 rateIndex;
+/* This check does not work for AR6003 as the HT modes are enabled only when
+ * the STA is connected to a HT_BSS and is not based only on channel. It is
+ * safe to skip this check however because rate control will only use rates
+ * that are permitted by the valid rate mask and the fix rate mask. Meaning
+ * the fix rate mask is not sufficient by itself to cause an invalid rate
+ * to be used. */
+    /* Make sure all rates in the mask are valid in the current PHY mode */
+    for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
+       if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
+            if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
+                A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
+                return A_EINVAL;
+            }
+       }
+    }
+#endif
+
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->fixRateMask = fixRatesMask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_ratemask_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID);
+}
+
+A_STATUS
+wmi_get_channelList_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID);
+}
+
+/*
+ * used to generate a wmi sey channel Parameters cmd.
+ * mode should always be specified and corresponds to the phy mode of the
+ * wlan.
+ * numChan should alway sbe specified. If zero indicates that all available
+ * channels should be used.
+ * channelList is an array of channel frequencies (in Mhz) which the radio
+ * should limit its operation to.  It should be NULL if numChan == 0.  Size of
+ * array should correspond to numChan entries.
+ */
+A_STATUS
+wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+                          WMI_PHY_MODE mode, A_INT8 numChan,
+                          A_UINT16 *channelList)
+{
+    void *osbuf;
+    WMI_CHANNEL_PARAMS_CMD *cmd;
+    A_INT8 size;
+
+    size = sizeof (*cmd);
+
+    if (numChan) {
+        if (numChan > WMI_MAX_CHANNELS) {
+            return A_EINVAL;
+        }
+        size += sizeof(A_UINT16) * (numChan - 1);
+    }
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    wmip->wmi_phyMode = mode;
+    cmd->scanParam   = scanParam;
+    cmd->phyMode     = mode;
+    cmd->numChannels = numChan;
+    A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+    /*
+     * Parse the command and store the threshold values here. The checks
+     * for valid values can be put here
+     */
+    sq_thresh->weight = rssiCmd->weight;
+    sq_thresh->polling_interval = rssiCmd->pollTime;
+
+    sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->upper_threshold_valid_count = 6;
+
+    /* List sorted in descending order */
+    sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+    sq_thresh->lower_threshold_valid_count = 6;
+
+    if (!rssi_event_value) {
+    /*
+     * Configuring the thresholds to their extremes allows the host to get an
+     * event from the target which is used for the configuring the correct
+     * thresholds
+     */
+    rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0];
+    rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0];
+    } else {
+        /*
+         * In case the user issues multiple times of rssi_threshold_setting,
+         * we should not use the extreames anymore, the target does not expect that.
+         */
+        rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh,
+                                              sq_thresh->upper_threshold_valid_count);
+        rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh,
+                                              sq_thresh->lower_threshold_valid_count);
+}
+}
+
+A_STATUS
+wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+
+     /* Check these values are in ascending order */
+    if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
+        rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
+        rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
+        rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
+        rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
+        rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
+        rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
+        rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
+        rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
+        rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val)
+    {
+        return A_EINVAL;
+    }
+
+    wmi_cache_configure_rssithreshold(wmip, rssiCmd);
+
+    return (wmi_send_rssi_threshold_params(wmip, rssiCmd));
+}
+
+A_STATUS
+wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd)
+{
+    void    *osbuf;
+    WMI_SET_IP_CMD *cmd;
+
+    /* Multicast address are not valid */
+    if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) ||
+       (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD));
+    cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
+                              WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
+    A_UINT16 activeTsids=0;
+    A_UINT8 streamExists=0;
+    A_UINT8 i;
+
+    if( hostModeCmd->awake == hostModeCmd->asleep) {
+        return A_EINVAL;
+    }
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
+
+    if(hostModeCmd->asleep) {
+        /*
+         * Relinquish credits from all implicitly created pstreams since when we
+         * go to sleep. If user created explicit thinstreams exists with in a
+         * fatpipe leave them intact for the user to delete
+         */
+        LOCK_WMI(wmip);
+        streamExists = wmip->wmi_fatPipeExists;
+        UNLOCK_WMI(wmip);
+
+        for(i=0;i< WMM_NUM_AC;i++) {
+            if (streamExists & (1<<i)) {
+                LOCK_WMI(wmip);
+                activeTsids = wmip->wmi_streamExistsForAC[i];
+                UNLOCK_WMI(wmip);
+                /* If there are no user created thin streams delete the fatpipe */
+                if(!activeTsids) {
+                    streamExists &= ~(1<<i);
+                    /*Indicate inactivity to drv layer for this fatpipe(pstream)*/
+                    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt,i);
+                }
+            }
+        }
+
+        /* Update the fatpipes that exists*/
+        LOCK_WMI(wmip);
+        wmip->wmi_fatPipeExists = streamExists;
+        UNLOCK_WMI(wmip);
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wow_mode_cmd(struct wmi_t *wmip,
+                              WMI_SET_WOW_MODE_CMD *wowModeCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SET_WOW_MODE_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_wow_list_cmd(struct wmi_t *wmip,
+                              WMI_GET_WOW_LIST_CMD *wowListCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_GET_WOW_LIST_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+static A_STATUS
+wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_GET_WOW_LIST_REPLY *reply;
+
+    if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_GET_WOW_LIST_REPLY *)datap;
+
+    A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
+                          reply);
+
+    return A_OK;
+}
+
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+                                 WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
+                                 A_UINT8* pattern, A_UINT8* mask,
+                                 A_UINT8 pattern_size)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_ADD_WOW_PATTERN_CMD *cmd;
+    A_UINT8 *filter_mask = NULL;
+
+    size = sizeof (*cmd);
+
+    size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->filter_list_id = addWowCmd->filter_list_id;
+    cmd->filter_offset = addWowCmd->filter_offset;
+    cmd->filter_size = addWowCmd->filter_size;
+
+    A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
+
+    filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
+    A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
+
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+                              WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_DEL_WOW_PATTERN_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
+                            NO_SYNC_WMIFLAG));
+
+}
+
+void
+wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    SQ_THRESHOLD_PARAMS *sq_thresh =
+           &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+    /*
+     * Parse the command and store the threshold values here. The checks
+     * for valid values can be put here
+     */
+    sq_thresh->weight = snrCmd->weight;
+    sq_thresh->polling_interval = snrCmd->pollTime;
+
+    sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val;
+    sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val;
+    sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val;
+    sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val;
+    sq_thresh->upper_threshold_valid_count = 4;
+
+    /* List sorted in descending order */
+    sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val;
+    sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val;
+    sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val;
+    sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val;
+    sq_thresh->lower_threshold_valid_count = 4;
+
+    if (!snr_event_value) {
+    /*
+     * Configuring the thresholds to their extremes allows the host to get an
+     * event from the target which is used for the configuring the correct
+     * thresholds
+     */
+    snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0];
+    snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0];
+    } else {
+        /*
+         * In case the user issues multiple times of snr_threshold_setting,
+         * we should not use the extreames anymore, the target does not expect that.
+         */
+        snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh,
+                                              sq_thresh->upper_threshold_valid_count);
+        snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh,
+                                              sq_thresh->lower_threshold_valid_count);
+    }
+
+}
+A_STATUS
+wmi_set_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
+        snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
+        snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
+        snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
+        snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
+        snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val)
+    {
+        return A_EINVAL;
+    }
+    wmi_cache_configure_snrthreshold(wmip, snrCmd);
+    return (wmi_send_snr_threshold_params(wmip, snrCmd));
+}
+
+A_STATUS
+wmi_clr_rssi_snr(struct wmi_t *wmip)
+{
+    void    *osbuf;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(int));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lq_threshold_params(struct wmi_t *wmip,
+                             WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
+    /* These values are in ascending order */
+    if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
+        lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
+        lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
+        lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
+        lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
+        lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
+
+        return A_EINVAL;
+    }
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    cmd->bitmask = mask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
+{
+    void *osbuf;
+    WMIX_HB_CHALLENGE_RESP_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->cookie = cookie;
+    cmd->source = source;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
+                              NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+                            A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+                            A_UINT32 valid)
+{
+    void *osbuf;
+    WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->config.cfgmmask = mmask;
+    cmd->config.cfgtsr = tsr;
+    cmd->config.cfgrep = rep;
+    cmd->config.cfgsize = size;
+    cmd->config.cfgvalid = valid;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
+                              NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_stats_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID);
+}
+
+A_STATUS
+wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
+{
+    void *osbuf;
+    WMI_ADD_BAD_AP_CMD *cmd;
+
+    if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->badApIndex = apIndex;
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG));
+}
+
+A_STATUS
+wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
+{
+    void *osbuf;
+    WMI_DELETE_BAD_AP_CMD *cmd;
+
+    if (apIndex > WMI_MAX_BAD_AP_INDEX) {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->badApIndex = apIndex;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_abort_scan_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID);
+}
+
+A_STATUS
+wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
+{
+    void *osbuf;
+    WMI_SET_TX_PWR_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->dbM = dbM;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_txPwr_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID);
+}
+
+A_UINT16
+wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
+{
+    A_UINT16 activeTsids=0;
+
+    LOCK_WMI(wmip);
+    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+    UNLOCK_WMI(wmip);
+
+    return activeTsids;
+}
+
+A_STATUS
+wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID);
+}
+
+A_STATUS
+wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
+{
+    void *osbuf;
+    A_UINT32 size = sizeof(A_UINT8);
+    WMI_TARGET_ROAM_DATA *cmd;
+
+    osbuf = A_NETBUF_ALLOC(size);      /* no payload */
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
+    cmd->roamDataType = roamDataType;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+                      A_UINT8 size)
+{
+    void *osbuf;
+    WMI_SET_ROAM_CTRL_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    A_MEMCPY(cmd, p, size);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+                            A_UINT8 size)
+{
+    void *osbuf;
+    WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
+
+    /* These timers can't be zero */
+    if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
+       !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
+         pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
+       !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
+         pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
+        return A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+
+    A_MEMCPY(cmd, pCmd, size);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+/* Send a command to Target to change GPIO output pins. */
+A_STATUS
+wmi_gpio_output_set(struct wmi_t *wmip,
+                    A_UINT32 set_mask,
+                    A_UINT32 clear_mask,
+                    A_UINT32 enable_mask,
+                    A_UINT32 disable_mask)
+{
+    void *osbuf;
+    WMIX_GPIO_OUTPUT_SET_CMD *output_set;
+    int size;
+
+    size = sizeof(*output_set);
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
+        set_mask, clear_mask, enable_mask, disable_mask));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    output_set->set_mask                   = set_mask;
+    output_set->clear_mask                 = clear_mask;
+    output_set->enable_mask                = enable_mask;
+    output_set->disable_mask               = disable_mask;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target requesting state of the GPIO input pins */
+A_STATUS
+wmi_gpio_input_get(struct wmi_t *wmip)
+{
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID);
+}
+
+/* Send a command to the Target that changes the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_set(struct wmi_t *wmip,
+                      A_UINT32 gpioreg_id,
+                      A_UINT32 value)
+{
+    void *osbuf;
+    WMIX_GPIO_REGISTER_SET_CMD *register_set;
+    int size;
+
+    size = sizeof(*register_set);
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    register_set->gpioreg_id               = gpioreg_id;
+    register_set->value                    = value;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target to fetch the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_get(struct wmi_t *wmip,
+                      A_UINT32 gpioreg_id)
+{
+    void *osbuf;
+    WMIX_GPIO_REGISTER_GET_CMD *register_get;
+    int size;
+
+    size = sizeof(*register_get);
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
+
+    register_get->gpioreg_id               = gpioreg_id;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target acknowledging some GPIO interrupts. */
+A_STATUS
+wmi_gpio_intr_ack(struct wmi_t *wmip,
+                  A_UINT32 ack_mask)
+{
+    void *osbuf;
+    WMIX_GPIO_INTR_ACK_CMD *intr_ack;
+    int size;
+
+    size = sizeof(*intr_ack);
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
+
+    intr_ack->ack_mask               = ack_mask;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+A_STATUS
+wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac,  A_UINT16 txop, A_UINT8 eCWmin,
+                          A_UINT8 eCWmax, A_UINT8 aifsn)
+{
+    void *osbuf;
+    WMI_SET_ACCESS_PARAMS_CMD *cmd;
+
+    if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
+        (aifsn > WMI_MAX_AIFSN_ACPARAM) || (ac >= WMM_NUM_AC))
+    {
+        return A_EINVAL;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->txop   = txop;
+    cmd->eCWmin = eCWmin;
+    cmd->eCWmax = eCWmax;
+    cmd->aifsn  = aifsn;
+    cmd->ac = ac;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+                         A_UINT8 trafficClass, A_UINT8 maxRetries,
+                         A_UINT8 enableNotify)
+{
+    void *osbuf;
+    WMI_SET_RETRY_LIMITS_CMD *cmd;
+
+    if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
+        (frameType != DATA_FRAMETYPE))
+    {
+        return A_EINVAL;
+    }
+
+    if (maxRetries > WMI_MAX_RETRIES) {
+        return A_EINVAL;
+    }
+
+    if (frameType != DATA_FRAMETYPE) {
+        trafficClass = 0;
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->frameType    = frameType;
+    cmd->trafficClass = trafficClass;
+    cmd->maxRetries   = maxRetries;
+    cmd->enableNotify = enableNotify;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
+{
+    if (bssid != NULL) {
+        A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
+    }
+}
+
+A_STATUS
+wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
+{
+    void *osbuf;
+    WMI_SET_OPT_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->optMode = optMode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
+                         SYNC_BOTH_WMIFLAG));
+}
+
+A_STATUS
+wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+                      A_UINT8 frmType,
+                      A_UINT8 *dstMacAddr,
+                      A_UINT8 *bssid,
+                      A_UINT16 optIEDataLen,
+                      A_UINT8 *optIEData)
+{
+    void *osbuf;
+    WMI_OPT_TX_FRAME_CMD *cmd;
+    osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
+
+    cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
+
+    cmd->frmType    = frmType;
+    cmd->optIEDataLen   = optIEDataLen;
+    //cmd->optIEData     = (A_UINT8 *)((int)cmd + sizeof(*cmd));
+    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+    A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
+    A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
+{
+    void *osbuf;
+    WMI_BEACON_INT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->beaconInterval = intvl;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
+{
+    void *osbuf;
+    WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->voicePktSize = voicePktSize;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
+{
+    void *osbuf;
+    WMI_SET_MAX_SP_LEN_CMD *cmd;
+
+    /* maxSPLen is a two-bit value. If user trys to set anything
+     * other than this, then its invalid
+     */
+    if(maxSPLen & ~0x03)
+        return  A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->maxSPLen = maxSPLen;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_determine_userPriority(
+    A_UINT8 *pkt,
+    A_UINT32 layer2Pri)
+{
+    A_UINT8 ipPri;
+    iphdr *ipHdr = (iphdr *)pkt;
+
+    /* Determine IPTOS priority */
+    /*
+     * IP Tos format :
+     *      (Refer Pg 57 WMM-test-plan-v1.2)
+     * IP-TOS - 8bits
+     *          : DSCP(6-bits) ECN(2-bits)
+     *          : DSCP - P2 P1 P0 X X X
+     *              where (P2 P1 P0) form 802.1D
+     */
+    ipPri = ipHdr->ip_tos >> 5;
+    ipPri &= 0x7;
+
+    if ((layer2Pri & 0x7) > ipPri)
+        return ((A_UINT8)layer2Pri & 0x7);
+    else
+        return ipPri;
+}
+
+A_UINT8
+convert_userPriority_to_trafficClass(A_UINT8 userPriority)
+{
+    return  (up_to_ac[userPriority & 0x7]);
+}
+
+A_UINT8
+wmi_get_power_mode_cmd(struct wmi_t *wmip)
+{
+    return wmip->wmi_powerMode;
+}
+
+A_STATUS
+wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
+{
+    A_STATUS ret = A_OK;
+
+#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0)
+#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF  0
+#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF      0
+#define TSPEC_DELAY_BOUND_ATHEROS_DEF         0
+#define TSPEC_MEDIUM_TIME_ATHEROS_DEF         0
+#define TSPEC_SBA_ATHEROS_DEF                 0x2000  /* factor is 1 */
+
+    /* Verify TSPEC params for ATHEROS compliance */
+    if(tspecCompliance == ATHEROS_COMPLIANCE) {
+        if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) ||
+            (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) ||
+            (pCmd->minDataRate != pCmd->meanDataRate) ||
+            (pCmd->minDataRate != pCmd->peakDataRate) ||
+            (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) ||
+            (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) ||
+            (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) ||
+            (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) {
+
+            A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG));
+            //A_PRINTF("%s: Invalid TSPEC params\n", __func__);
+            ret = A_EINVAL;
+        }
+    }
+
+    return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+
+   A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+   A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
+
+   return A_OK;
+}
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+A_STATUS
+wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+    void *osbuf;
+    WMI_SET_AUTH_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->mode = mode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+    void *osbuf;
+    WMI_SET_REASSOC_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->mode = mode;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy)
+{
+    void *osbuf;
+    WMI_SET_LPREAMBLE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+    cmd->preamblePolicy = preamblePolicy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
+{
+    void *osbuf;
+    WMI_SET_RTS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->threshold = threshold;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
+{
+    void *osbuf;
+    WMI_SET_WMM_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
+            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_qos_supp_cmd(struct wmi_t *wmip, A_UINT8 status)
+{
+    void *osbuf;
+    WMI_SET_QOS_SUPP_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_QOS_SUPP_CMD*)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->status = status;
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_QOS_SUPP_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
+{
+    void *osbuf;
+    WMI_SET_WMM_TXOP_CMD *cmd;
+
+    if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
+        return A_EINVAL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->txopEnable = cfg;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
+            NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode)
+{
+    void *osbuf;
+    WMI_AP_SET_COUNTRY_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    A_MEMCPY(cmd->countryCode,countryCode,3);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* WMI  layer doesn't need to know the data type of the test cmd.
+   This would be beneficial for customers like Qualcomm, who might
+   have different test command requirements from differnt manufacturers
+ */
+A_STATUS
+wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len)
+{
+    void *osbuf;
+    char *data;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    osbuf= A_NETBUF_ALLOC(len);
+    if(osbuf == NULL)
+    {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, len);
+    data = A_NETBUF_DATA(osbuf);
+    A_MEMCPY(data, buf, len);
+
+    return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
+         NO_SYNC_WMIFLAG));
+}
+
+#endif
+
+A_STATUS
+wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
+{
+    void *osbuf;
+    WMI_SET_BT_STATUS_CMD *cmd;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Enter - streamType=%d, status=%d\n", streamType, status));
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->streamType = streamType;
+    cmd->status = status;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
+{
+    void *osbuf;
+    WMI_SET_BT_PARAMS_CMD* alloc_cmd;
+
+    AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("cmd params is %d\n", cmd->paramType));
+
+    if (cmd->paramType == BT_PARAM_SCO) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n", cmd->info.scoParams.numScoCyclesForceTrigger,
+        cmd->info.scoParams.dataResponseTimeout,
+        cmd->info.scoParams.stompScoRules,
+        cmd->info.scoParams.scoOptFlags,
+        cmd->info.scoParams.stompDutyCyleVal,
+        cmd->info.scoParams.stompDutyCyleMaxVal,
+        cmd->info.scoParams.psPollLatencyFraction,
+        cmd->info.scoParams.noSCOSlots,
+        cmd->info.scoParams.noIdleSlots,
+        cmd->info.scoParams.scoOptOffRssi,
+        cmd->info.scoParams.scoOptOnRssi,
+        cmd->info.scoParams.scoOptRtsCount));
+    }
+    else if (cmd->paramType == BT_PARAM_A2DP) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("A2DP params %d %d %d %d %d %d %d %d\n", cmd->info.a2dpParams.a2dpWlanUsageLimit,
+        cmd->info.a2dpParams.a2dpBurstCntMin,
+        cmd->info.a2dpParams.a2dpDataRespTimeout,
+        cmd->info.a2dpParams.a2dpOptFlags,
+        cmd->info.a2dpParams.isCoLocatedBtRoleMaster,
+        cmd->info.a2dpParams.a2dpOptOffRssi,
+        cmd->info.a2dpParams.a2dpOptOnRssi,
+        cmd->info.a2dpParams.a2dpOptRtsCount));
+    }
+    else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Ant config %d\n", cmd->info.antType));
+    }
+    else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("co-located BT %d\n", cmd->info.coLocatedBtDev));
+    }
+    else if (cmd->paramType == BT_PARAM_ACLCOEX) {
+      AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("ACL params %d %d %d\n", cmd->info.aclCoexParams.aclWlanMediumUsageTime,
+        cmd->info.aclCoexParams.aclBtMediumUsageTime,
+        cmd->info.aclCoexParams.aclDataRespTimeout));
+    }
+    else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) {
+      A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG));
+    }
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_FE_ANT_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_FE_ANT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_FE_ANT_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+
+A_STATUS
+wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+    A_PRINTF("colocated bt = %d\n", alloc_cmd->btcoexCoLocatedBTdev);
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD* cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_SCO_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_SCO_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_SCO_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_A2DP_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_A2DP_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_A2DP_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_A2DP_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip,
+						WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+    WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    alloc_cmd = (WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID ,
+                         NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd)
+{
+	void *osbuf;
+	WMI_SET_BTCOEX_DEBUG_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_SET_BTCOEX_DEBUG_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_DEBUG_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_DEBUG_CMDID ,
+							 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+					WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd)
+{
+	void *osbuf;
+	WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ,
+								 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd)
+{
+	void *osbuf;
+	WMI_GET_BTCOEX_CONFIG_CMD *alloc_cmd;
+
+	osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+	if (osbuf == NULL) {
+			return A_NO_MEMORY;
+	}
+	A_NETBUF_PUT(osbuf, sizeof(*cmd));
+	alloc_cmd = (WMI_GET_BTCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+	A_MEMZERO(alloc_cmd, sizeof(*cmd));
+	A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_GET_BTCOEX_CONFIG_CMD));
+	return (wmi_cmd_send(wmip, osbuf, WMI_GET_BTCOEX_CONFIG_CMDID ,
+							 NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_stats_cmd(struct wmi_t *wmip)
+{
+
+    return wmi_simple_cmd(wmip, WMI_GET_BTCOEX_STATS_CMDID);
+
+}
+
+A_STATUS
+wmi_get_keepalive_configured(struct wmi_t *wmip)
+{
+    void *osbuf;
+    WMI_GET_KEEPALIVE_CMD *cmd;
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+    cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_get_keepalive_cmd(struct wmi_t *wmip)
+{
+    return wmip->wmi_keepaliveInterval;
+}
+
+A_STATUS
+wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
+{
+    void *osbuf;
+    WMI_SET_KEEPALIVE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->keepaliveInterval = keepaliveInterval;
+    wmip->wmi_keepaliveInterval = keepaliveInterval;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer)
+{
+    void *osbuf;
+    WMI_SET_PARAMS_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd) + length);
+
+    cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->opcode = opcode;
+    cmd->length = length;
+    A_MEMCPY(cmd->buffer, buffer, length);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+    void *osbuf;
+    WMI_SET_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->multicast_mac[0] = 0x01;
+    cmd->multicast_mac[1] = 0x00;
+    cmd->multicast_mac[2] = 0x5e;
+    cmd->multicast_mac[3] = dot2&0x7F;
+    cmd->multicast_mac[4] = dot3;
+    cmd->multicast_mac[5] = dot4;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+    void *osbuf;
+    WMI_SET_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->multicast_mac[0] = 0x01;
+    cmd->multicast_mac[1] = 0x00;
+    cmd->multicast_mac[2] = 0x5e;
+    cmd->multicast_mac[3] = dot2&0x7F;
+    cmd->multicast_mac[4] = dot3;
+    cmd->multicast_mac[5] = dot4;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable)
+{
+    void *osbuf;
+    WMI_MCAST_FILTER_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->enable = enable;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_MCAST_FILTER_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
+                  A_UINT8 *ieInfo)
+{
+    void *osbuf;
+    WMI_SET_APPIE_CMD *cmd;
+    A_UINT16 cmdLen;
+
+    cmdLen = sizeof(*cmd) + ieLen - 1;
+    osbuf = A_NETBUF_ALLOC(cmdLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, cmdLen);
+
+    cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, cmdLen);
+
+    cmd->mgmtFrmType = mgmtFrmType;
+    cmd->ieLen = ieLen;
+    A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
+{
+    void *osbuf;
+    A_UINT8 *data;
+
+    osbuf = A_NETBUF_ALLOC(dataLen);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, dataLen);
+
+    data = A_NETBUF_DATA(osbuf);
+
+    A_MEMCPY(data, cmd, dataLen);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_INT32
+wmi_get_rate(A_INT8 rateindex)
+{
+    if (rateindex == RATE_AUTO) {
+        return 0;
+    } else {
+        return(wmi_rateTable[(A_UINT32) rateindex][0]);
+    }
+}
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss)
+{
+    if (NULL != bss)
+    {
+        wlan_node_return (&wmip->wmi_scan_table, bss);
+    }
+}
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge)
+{
+    wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge);
+}
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+    bss_t *node = NULL;
+    node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
+                               ssidLength, bIsWPA2, bMatchSSID);
+    return node;
+}
+
+
+void
+wmi_free_allnodes(struct wmi_t *wmip)
+{
+    wlan_free_allnodes(&wmip->wmi_scan_table);
+}
+
+bss_t *
+wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+    bss_t *ni=NULL;
+    ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+    return ni;
+}
+
+void
+wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+    bss_t *ni=NULL;
+
+    ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+    if (ni != NULL) {
+        wlan_node_reclaim(&wmip->wmi_scan_table, ni);
+    }
+
+    return;
+}
+
+A_STATUS
+wmi_dset_open_reply(struct wmi_t *wmip,
+                    A_UINT32 status,
+                    A_UINT32 access_cookie,
+                    A_UINT32 dset_size,
+                    A_UINT32 dset_version,
+                    A_UINT32 targ_handle,
+                    A_UINT32 targ_reply_fn,
+                    A_UINT32 targ_reply_arg)
+{
+    void *osbuf;
+    WMIX_DSETOPEN_REPLY_CMD *open_reply;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip));
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*open_reply));
+    open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+    open_reply->status                   = status;
+    open_reply->targ_dset_handle         = targ_handle;
+    open_reply->targ_reply_fn            = targ_reply_fn;
+    open_reply->targ_reply_arg           = targ_reply_arg;
+    open_reply->access_cookie            = access_cookie;
+    open_reply->size                     = dset_size;
+    open_reply->version                  = dset_version;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+    WMI_PMKID_LIST_REPLY *reply;
+    A_UINT32 expected_len;
+
+    if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_PMKID_LIST_REPLY *)datap;
+    expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
+
+    if (len < expected_len) {
+        return A_EINVAL;
+    }
+
+    A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
+                           reply->pmkidList, reply->bssidList[0]);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+    WMI_SET_PARAMS_REPLY *reply;
+
+    if (len < sizeof(WMI_SET_PARAMS_REPLY)) {
+        return A_EINVAL;
+    }
+    reply = (WMI_SET_PARAMS_REPLY *)datap;
+
+    if (A_OK == reply->status)
+    {
+
+    }
+    else
+    {
+
+    }
+
+    return A_OK;
+}
+
+
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+A_STATUS
+wmi_dset_data_reply(struct wmi_t *wmip,
+                    A_UINT32 status,
+                    A_UINT8 *user_buf,
+                    A_UINT32 length,
+                    A_UINT32 targ_buf,
+                    A_UINT32 targ_reply_fn,
+                    A_UINT32 targ_reply_arg)
+{
+    void *osbuf;
+    WMIX_DSETDATA_REPLY_CMD *data_reply;
+    A_UINT32 size;
+
+    size = sizeof(*data_reply) + length;
+
+    if (size <= length) {
+        return A_ERROR;
+    }
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+    A_NETBUF_PUT(osbuf, size);
+    data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+    data_reply->status                     = status;
+    data_reply->targ_buf                   = targ_buf;
+    data_reply->targ_reply_fn              = targ_reply_fn;
+    data_reply->targ_reply_arg             = targ_reply_arg;
+    data_reply->length                     = length;
+
+    if (status == A_OK) {
+        if (a_copy_from_user(data_reply->buf, user_buf, length)) {
+            A_NETBUF_FREE(osbuf);
+            return A_ERROR;
+        }
+    }
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
+                             NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+A_STATUS
+wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
+{
+    void *osbuf;
+    char *cmd;
+
+    wps_enable = status;
+
+    osbuf = a_netbuf_alloc(sizeof(1));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    a_netbuf_put(osbuf, sizeof(1));
+
+    cmd = (char *)(a_netbuf_to_data(osbuf));
+
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd[0] = (status?1:0);
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS
+wmi_prof_cfg_cmd(struct wmi_t *wmip,
+                 A_UINT32 period,
+                 A_UINT32 nbins)
+{
+    void *osbuf;
+    WMIX_PROF_CFG_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->period = period;
+    cmd->nbins  = nbins;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr)
+{
+    void *osbuf;
+    WMIX_PROF_ADDR_SET_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->addr = addr;
+
+    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_start_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID);
+}
+
+A_STATUS
+wmi_prof_stop_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID);
+}
+
+A_STATUS
+wmi_prof_count_get_cmd(struct wmi_t *wmip)
+{
+    return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID);
+}
+
+/* Called to handle WMIX_PROF_CONT_EVENTID */
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap;
+
+    A_DPRINTF(DBG_WMI,
+        (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG,
+        prof_data->addr, prof_data->count));
+
+    A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count);
+
+    return A_OK;
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef OS_ROAM_MANAGEMENT
+
+#define ETHERNET_MAC_ADDRESS_LENGTH    6
+
+void
+wmi_scan_indication (struct wmi_t *wmip)
+{
+    struct ieee80211_node_table *nt;
+    A_UINT32 gen;
+    A_UINT32 size;
+    A_UINT32 bsssize;
+    bss_t *bss;
+    A_UINT32 numbss;
+    PNDIS_802_11_BSSID_SCAN_INFO psi;
+    PBYTE  pie;
+    NDIS_802_11_FIXED_IEs *pFixed;
+    NDIS_802_11_VARIABLE_IEs *pVar;
+    A_UINT32  RateSize;
+
+    struct ar6kScanIndication
+    {
+        NDIS_802_11_STATUS_INDICATION     ind;
+        NDIS_802_11_BSSID_SCAN_INFO_LIST  slist;
+    } *pAr6kScanIndEvent;
+
+    nt = &wmip->wmi_scan_table;
+
+    ++nt->nt_si_gen;
+
+
+    gen = nt->nt_si_gen;
+
+    size = offsetof(struct ar6kScanIndication, slist) +
+           offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo);
+
+    numbss = 0;
+
+    IEEE80211_NODE_LOCK(nt);
+
+    //calc size
+    for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+        if (bss->ni_si_gen != gen) {
+            bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs);
+            bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+            if (bss->ni_cie.ie_rsn) {
+                bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+            }
+#endif
+            if (bss->ni_cie.ie_wpa) {
+                bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+            }
+
+            // bsssize must be a multiple of 4 to maintain alignment.
+            bsssize = (bsssize + 3) & ~3;
+
+            size += bsssize;
+
+            numbss++;
+        }
+    }
+
+    if (0 == numbss)
+    {
+//        RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n"));
+        ar6000_scan_indication (wmip->wmi_devt, NULL, 0);
+        IEEE80211_NODE_UNLOCK (nt);
+        return;
+    }
+
+    pAr6kScanIndEvent = A_MALLOC(size);
+
+    if (NULL == pAr6kScanIndEvent)
+    {
+        IEEE80211_NODE_UNLOCK(nt);
+        return;
+    }
+
+    A_MEMZERO(pAr6kScanIndEvent, size);
+
+    //copy data
+    pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList;
+    pAr6kScanIndEvent->slist.Version = 1;
+    pAr6kScanIndEvent->slist.NumItems = numbss;
+
+    psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0];
+
+    for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+        if (bss->ni_si_gen != gen) {
+
+            bss->ni_si_gen = gen;
+
+            //Set scan time
+            psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+            // Copy data to bssid_ex
+            bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs);
+            bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+            if (bss->ni_cie.ie_rsn) {
+                bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+            }
+#endif
+            if (bss->ni_cie.ie_wpa) {
+                bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+            }
+
+            // bsssize must be a multiple of 4 to maintain alignment.
+            bsssize = (bsssize + 3) & ~3;
+
+            psi->Bssid.Length = bsssize;
+
+            memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH);
+
+
+//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) ||
+//  ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70)))
+//            RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5]));
+
+            psi->Bssid.Ssid.SsidLength = 0;
+            pie = bss->ni_cie.ie_ssid;
+
+            if (pie) {
+                // Format of SSID IE is:
+                //  Type   (1 octet)
+                //  Length (1 octet)
+                //  SSID (Length octets)
+                //
+                //  Validation of the IE should have occurred within WMI.
+                //
+                if (pie[1] <= 32) {
+                    psi->Bssid.Ssid.SsidLength = pie[1];
+                    memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength);
+                }
+            }
+            psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0;
+
+            //Post the RSSI value relative to the Standard Noise floor value.
+            psi->Bssid.Rssi = bss->ni_rssi;
+
+            if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) {
+
+                if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) {
+                    psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24;
+                }
+                else {
+                    psi->Bssid.NetworkTypeInUse = Ndis802_11DS;
+                }
+            }
+            else {
+                psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5;
+            }
+
+            psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration);
+            psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us)
+            psi->Bssid.Configuration.ATIMWindow =  0;
+            psi->Bssid.Configuration.DSConfig =  bss->ni_cie.ie_chan * 1000;
+            psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS;
+
+            RateSize = 0;
+            pie = bss->ni_cie.ie_rates;
+            if (pie) {
+                RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX;
+                memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize);
+            }
+            pie = bss->ni_cie.ie_xrates;
+            if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) {
+                memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2],
+                       (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize));
+            }
+
+            // Copy the fixed IEs
+            psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs);
+
+            pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs;
+            memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp));
+            pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt;
+            pFixed->Capabilities = bss->ni_cie.ie_capInfo;
+
+            // Copy selected variable IEs
+
+            pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs));
+
+#ifdef SUPPORT_WPA2
+            // Copy the WPAv2 IE
+            if (bss->ni_cie.ie_rsn) {
+                pie = bss->ni_cie.ie_rsn;
+                psi->Bssid.IELength += pie[1] + 2;
+                memcpy(pVar, pie, pie[1] + 2);
+                pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+            }
+#endif
+            // Copy the WPAv1 IE
+            if (bss->ni_cie.ie_wpa) {
+                pie = bss->ni_cie.ie_wpa;
+                psi->Bssid.IELength += pie[1] + 2;
+                memcpy(pVar, pie, pie[1] + 2);
+                pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+            }
+
+            // Advance buffer pointer
+            psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid));
+        }
+    }
+
+    IEEE80211_NODE_UNLOCK(nt);
+
+//    wmi_free_allnodes(wmip);
+
+//    RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss));
+
+    ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size);
+
+    A_FREE(pAr6kScanIndEvent);
+}
+#endif
+
+A_UINT8
+ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+                           A_UINT32 size)
+{
+    A_UINT32 index;
+    A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1];
+
+    /* The list is already in sorted order. Get the next lower value */
+    for (index = 0; index < size; index ++) {
+        if (rssi < sq_thresh->upper_threshold[index]) {
+            threshold = (A_UINT8)sq_thresh->upper_threshold[index];
+            break;
+        }
+    }
+
+    return threshold;
+}
+
+A_UINT8
+ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+                           A_UINT32 size)
+{
+    A_UINT32 index;
+    A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1];
+
+    /* The list is already in sorted order. Get the next lower value */
+    for (index = 0; index < size; index ++) {
+        if (rssi > sq_thresh->lower_threshold[index]) {
+            threshold = (A_UINT8)sq_thresh->lower_threshold[index];
+            break;
+        }
+    }
+
+    return threshold;
+}
+static A_STATUS
+wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+
+    cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+static A_STATUS
+wmi_send_snr_threshold_params(struct wmi_t *wmip,
+                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+    void    *osbuf;
+    A_INT8  size;
+    WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
+
+    size = sizeof (*cmd);
+
+    osbuf = A_NETBUF_ALLOC(size);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, size);
+    cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, size);
+    A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
+                            NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd)
+{
+    void *osbuf;
+    WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(alloc_cmd, sizeof(*cmd));
+    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID,
+            NO_SYNC_WMIFLAG));
+}
+
+bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id)
+{
+    wmi_get_current_bssid (wmip, id);
+    return wlan_node_remove (&wmip->wmi_scan_table, id);
+}
+
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss)
+{
+    wlan_setup_node (&wmip->wmi_scan_table, bss, id);
+    return A_OK;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS
+wmi_addba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_ADDBA_REQ_EVENT *cmd = (WMI_ADDBA_REQ_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_ADDBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+
+static A_STATUS
+wmi_addba_resp_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_ADDBA_RESP_EVENT *cmd = (WMI_ADDBA_RESP_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_ADDBA_RESP_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+static A_STATUS
+wmi_delba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_DELBA_EVENT *cmd = (WMI_DELBA_EVENT *)datap;
+
+    A_WMI_AGGR_RECV_DELBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+A_STATUS
+wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+	A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_BTCOEX_CONFIG_EVENT(wmip->wmi_devt, datap, len);
+
+     return A_OK;
+}
+
+
+A_STATUS
+wmi_btcoex_stats_event_rx(struct wmi_t * wmip,A_UINT8 * datap,int len)
+{
+	A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+    A_WMI_BTCOEX_STATS_EVENT(wmip->wmi_devt, datap, len);
+
+     return A_OK;
+
+}
+#endif
+
+static A_STATUS
+wmi_hci_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_HCI_EVENT *cmd = (WMI_HCI_EVENT *)datap;
+    A_WMI_HCI_EVENT_EVT(wmip->wmi_devt, cmd);
+
+    return A_OK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+////                                                                        ////
+////                AP mode functions                                       ////
+////                                                                        ////
+////////////////////////////////////////////////////////////////////////////////
+/*
+ * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG
+ *
+ * When AR6K in AP mode, This command will be called after
+ * changing ssid, channel etc. It will pass the profile to
+ * target with a flag which will indicate which parameter changed,
+ * also if this flag is 0, there was no change in parametes, so
+ * commit cmd will not be sent to target. Without calling this IOCTL
+ * the changes will not take effect.
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p)
+{
+    void *osbuf;
+    WMI_CONNECT_CMD *cm;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cm));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cm));
+    cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cm, sizeof(*cm));
+
+    A_MEMCPY(cm,p,sizeof(*cm));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID
+ *
+ * This command will be used to enable/disable hidden ssid functioanlity of
+ * beacon. If it is enabled, ssid will be NULL in beacon.
+ */
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid)
+{
+    void *osbuf;
+    WMI_AP_HIDDEN_SSID_CMD *hs;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD));
+    hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(hs, sizeof(*hs));
+
+    hs->hidden_ssid          = hidden_ssid;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid));
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA
+ *
+ * This command is used to limit max num of STA that can connect
+ * with this AP. This value should not exceed AP_MAX_NUM_STA (this
+ * is max num of STA supported by AP). Value was already validated
+ * in ioctl.c
+ */
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta)
+{
+    void *osbuf;
+    WMI_AP_SET_NUM_STA_CMD *ns;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD));
+    ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(ns, sizeof(*ns));
+
+    ns->num_sta          = num_sta;
+
+    A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta));
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl)
+{
+    void *osbuf;
+    WMI_AP_ACL_MAC_CMD *a;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD));
+    a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(a, sizeof(*a));
+    A_MEMCPY(a,acl,sizeof(*acl));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MLME
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason)
+{
+    void *osbuf;
+    WMI_AP_SET_MLME_CMD *mlme;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD));
+    mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(mlme, sizeof(*mlme));
+
+    mlme->cmd = cmd;
+    A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN);
+    mlme->reason = reason;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+    WMI_PSPOLL_EVENT *ev;
+
+    if (len < sizeof(WMI_PSPOLL_EVENT)) {
+        return A_EINVAL;
+    }
+    ev = (WMI_PSPOLL_EVENT *)datap;
+
+    A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid);
+    return A_OK;
+}
+
+static A_STATUS
+wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+    A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt);
+    return A_OK;
+}
+
+#ifdef WAPI_ENABLE
+static A_STATUS
+wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+    A_UINT8 *ev;
+
+    if (len < 7) {
+        return A_EINVAL;
+    }
+    ev = (A_UINT8 *)datap;
+
+    A_WMI_WAPI_REKEY_EVENT(wmip->wmi_devt, *ev, &ev[1]);
+    return A_OK;
+}
+#endif
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag)
+{
+    WMI_AP_SET_PVB_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD));
+    cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->aid = aid;
+    cmd->flag = flag;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period)
+{
+    WMI_AP_CONN_INACT_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD));
+    cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->period = period;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell)
+{
+    WMI_AP_PROT_SCAN_TIME_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+    cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->period_min = period;
+    cmd->dwell_ms   = dwell;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim)
+{
+    WMI_AP_SET_DTIM_CMD *cmd;
+    void *osbuf = NULL;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD));
+    cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+
+    cmd->dtim = dtim;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY
+ *
+ * This command is used to set ACL policay. While changing policy, if you
+ * want to retain the existing MAC addresses in the ACL list, policy should be
+ * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared.
+ * If there is no chage in policy, the list will be intact.
+ */
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy)
+{
+    void *osbuf;
+    WMI_AP_ACL_POLICY_CMD *po;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+}
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD));
+    po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(po, sizeof(*po));
+
+    po->policy = policy;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset)
+{
+    void *osbuf;
+    WMI_AP_SET_11BG_RATESET_CMD *rs;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+    rs = (WMI_AP_SET_11BG_RATESET_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(rs, sizeof(*rs));
+
+    rs->rateset = rateset;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_11BG_RATESET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd)
+{
+    void *osbuf;
+    WMI_SET_HT_CAP_CMD *htCap;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*htCap));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*htCap));
+
+    htCap = (WMI_SET_HT_CAP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(htCap, sizeof(*htCap));
+    A_MEMCPY(htCap, cmd, sizeof(*htCap));
+    
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_CAP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width)
+{
+    void *osbuf;
+    WMI_SET_HT_OP_CMD *htInfo;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*htInfo));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*htInfo));
+
+    htInfo = (WMI_SET_HT_OP_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(htInfo, sizeof(*htInfo));
+    htInfo->sta_chan_width = sta_chan_width;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_OP_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray)
+{
+    void *osbuf;
+    WMI_SET_TX_SELECT_RATES_CMD *pData;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*pData));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*pData));
+
+    pData = (WMI_SET_TX_SELECT_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMCPY(pData, pMaskArray, sizeof(*pData));
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_SELECT_RATES_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz)
+{
+    void *osbuf;
+    WMI_HCI_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + sz);
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd) + sz);
+    cmd = (WMI_HCI_CMD *)(A_NETBUF_DATA(osbuf));
+
+    cmd->cmd_buf_sz = sz;
+    A_MEMCPY(cmd->buf, buf, sz);
+    return (wmi_cmd_send(wmip, osbuf, WMI_HCI_CMD_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask)
+{
+    void *osbuf;
+    WMI_ALLOW_AGGR_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ALLOW_AGGR_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tx_allow_aggr = tx_tidmask;
+    cmd->rx_allow_aggr = rx_tidmask;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ALLOW_AGGR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid)
+{
+    void *osbuf;
+    WMI_ADDBA_REQ_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_ADDBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tid = tid;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_ADDBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink)
+{
+    void *osbuf;
+    WMI_DELBA_REQ_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_DELBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->tid = tid;
+    cmd->is_sender_initiator = uplink;  /* uplink =1 - uplink direction, 0=downlink direction */
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_DELBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion,
+                            A_BOOL rxDot11Hdr, A_BOOL defragOnHost)
+{
+    void *osbuf;
+    WMI_RX_FRAME_FORMAT_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_RX_FRAME_FORMAT_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->dot11Hdr = (rxDot11Hdr==TRUE)? 1:0;
+    cmd->defragOnHost = (defragOnHost==TRUE)? 1:0;
+    cmd->metaVersion = rxMetaVersion;  /*  */
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_RX_FRAME_FORMAT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode)
+{
+    void *osbuf;
+    WMI_SET_THIN_MODE_CMD *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_THIN_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+    cmd->enable = (bThinMode==TRUE)? 1:0;
+
+    /* Delete the local aggr state, on host */
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_THIN_MODE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence)
+{
+    void *osbuf;
+    WMI_SET_BT_WLAN_CONN_PRECEDENCE *cmd;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+    cmd = (WMI_SET_BT_WLAN_CONN_PRECEDENCE *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(cmd, sizeof(*cmd));
+    cmd->precedence = precedence;
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+                         NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk)
+{
+    void *osbuf;
+    WMI_SET_PMK_CMD *p;
+
+    osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_PMK_CMD));
+    if (osbuf == NULL) {
+        return A_NO_MEMORY;
+    }
+
+    A_NETBUF_PUT(osbuf, sizeof(WMI_SET_PMK_CMD));
+
+    p = (WMI_SET_PMK_CMD *)(A_NETBUF_DATA(osbuf));
+    A_MEMZERO(p, sizeof(*p));
+
+    A_MEMCPY(p->pmk, pmk, WMI_PMK_LEN);
+
+    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+                   A_UINT32 ssidLength,
+                   A_UINT32 dot11AuthMode, A_UINT32 authMode,
+                   A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+    bss_t *node = NULL;
+    node = wlan_find_matching_Ssidnode (&wmip->wmi_scan_table, pSsid,
+                               ssidLength, dot11AuthMode, authMode, pairwiseCryptoType, grpwiseCryptoTyp);
+
+    return node;
+}
+
+A_UINT16
+wmi_ieee2freq (int chan)
+{
+    A_UINT16 freq = 0;
+    freq = wlan_ieee2freq (chan);
+    return freq;
+
+}
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq)
+{
+    A_UINT16 chan = 0;
+    chan = wlan_freq2ieee (freq);
+    return chan;
+}
diff --git a/drivers/net/wireless/ath6kl/wmi/wmi_host.h b/drivers/net/wireless/ath6kl/wmi/wmi_host.h
new file mode 100644
index 000000000000..474e239e316c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/wmi_host.h
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_host.h" company="Atheros">
+//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+// 
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains local definitios for the wmi host module.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_HOST_H_
+#define _WMI_HOST_H_
+
+#include "roaming.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct wmi_stats {
+    A_UINT32    cmd_len_err;
+    A_UINT32    cmd_id_err;
+};
+
+#define SSID_IE_LEN_INDEX 13
+
+/* Host side link management data structures */
+#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6
+#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+typedef struct sq_threshold_params_s {
+    A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS];
+    A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS];
+    A_UINT32 upper_threshold_valid_count;
+    A_UINT32 lower_threshold_valid_count;
+    A_UINT32 polling_interval;
+    A_UINT8 weight;
+    A_UINT8  last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target.
+    A_UINT8  last_rssi_poll_event; //Not sure if it belongs to host or target
+} SQ_THRESHOLD_PARAMS;
+struct wmi_t {
+    A_BOOL                          wmi_ready;
+    A_BOOL                          wmi_numQoSStream;
+    A_UINT16                        wmi_streamExistsForAC[WMM_NUM_AC];
+    A_UINT8                         wmi_fatPipeExists;
+    void                           *wmi_devt;
+    struct wmi_stats                wmi_stats;
+    struct ieee80211_node_table     wmi_scan_table;
+    A_UINT8                         wmi_bssid[ATH_MAC_LEN];
+    A_UINT8                         wmi_powerMode;
+    A_UINT8                         wmi_phyMode;
+    A_UINT8                         wmi_keepaliveInterval;
+    A_MUTEX_T                       wmi_lock;
+    HTC_ENDPOINT_ID                wmi_endpoint_id;
+    SQ_THRESHOLD_PARAMS            wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX];
+    CRYPTO_TYPE                     wmi_pair_crypto_type;
+    CRYPTO_TYPE                     wmi_grp_crypto_type;
+    A_BOOL                          wmi_is_wmm_enabled;
+};
+
+
+#define LOCK_WMI(w)     A_MUTEX_LOCK(&(w)->wmi_lock);
+#define UNLOCK_WMI(w)   A_MUTEX_UNLOCK(&(w)->wmi_lock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_HOST_H_ */
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index fbf965b31c14..c81af3e45b17 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -275,6 +275,14 @@ config AT91_CF
 	  Say Y here to support the CompactFlash controller on AT91 chips.
 	  Or choose M to compile the driver as a module named "at91_cf".
 
+config PCMCIA_MX31ADS
+	tristate "MX31ADS PCMCIA support"
+	depends on ARM && MACH_MX31ADS && PCMCIA
+	help
+	  Say Y here to include support for the Freescale i.MX31 PCMCIA controller.
+
+	  This driver is also available as a module called mx31ads_pcmcia.
+
 config ELECTRA_CF
 	tristate "Electra CompactFlash Controller"
 	depends on PCMCIA && PPC_PASEMI
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 047394d98ac2..4c1fc112554a 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_OMAP_CF)				+= omap_cf.o
 obj-$(CONFIG_BFIN_CFPCMCIA)			+= bfin_cf_pcmcia.o
 obj-$(CONFIG_AT91_CF)				+= at91_cf.o
 obj-$(CONFIG_ELECTRA_CF)			+= electra_cf.o
+obj-$(CONFIG_PCMCIA_MX31ADS)			+= mx31ads-pcmcia.o
 
 sa11xx_core-y					+= soc_common.o sa11xx_base.o
 pxa2xx_core-y					+= soc_common.o pxa2xx_base.o
diff --git a/drivers/pcmcia/mx31ads-pcmcia.c b/drivers/pcmcia/mx31ads-pcmcia.c
new file mode 100644
index 000000000000..351cf989f6f2
--- /dev/null
+++ b/drivers/pcmcia/mx31ads-pcmcia.c
@@ -0,0 +1,1291 @@
+/*======================================================================
+    drivers/pcmcia/mx31ads-pcmica.c
+
+    Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+
+    Device driver for the PCMCIA control functionality of i.Mx31
+    microprocessors.
+
+    The contents of this file are subject to the Mozilla Public
+    License Version 1.1 (the "License"); you may not use this file
+    except in compliance with the License. You may obtain a copy of
+    the License at http://www.mozilla.org/MPL/
+
+    Software distributed under the License is distributed on an "AS
+    IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+    implied. See the License for the specific language governing
+    rights and limitations under the License.
+
+    The initial developer of the original code is John G. Dorsey
+    <john+@cs.cmu.edu>.  Portions created by John G. Dorsey are
+    Copyright (C) 1999 John G. Dorsey.  All Rights Reserved.
+
+    Alternatively, the contents of this file may be used under the
+    terms of the GNU Public License version 2 (the "GPL"), in which
+    case the provisions of the GPL are applicable instead of the
+    above.  If you wish to allow the use of your version of this file
+    only under the terms of the GPL and not to allow others to use
+    your version of this file under the MPL, indicate your decision
+    by deleting the provisions above and replace them with the notice
+    and other provisions required by the GPL.  If you do not delete
+    the provisions above, a recipient may use your version of this
+    file under either the MPL or the GPL.
+
+======================================================================*/
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/ss.h>
+#include <asm/mach-types.h>
+#include <mach/pcmcia.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+
+#include "mx31ads-pcmcia.h"
+#include <linux/irq.h>
+
+#define	MX31ADS_PCMCIA_IRQ	MXC_INT_PCMCIA
+
+/*
+ * The mapping of window size to bank size value
+ */
+static bsize_map_t bsize_map[] = {
+	/* Window size  Bank size       */
+	{POR_1, POR_BSIZE_1},
+	{POR_2, POR_BSIZE_2},
+	{POR_4, POR_BSIZE_4},
+	{POR_8, POR_BSIZE_8},
+	{POR_16, POR_BSIZE_16},
+	{POR_32, POR_BSIZE_32},
+	{POR_64, POR_BSIZE_64},
+	{POR_128, POR_BSIZE_128},
+	{POR_256, POR_BSIZE_256},
+	{POR_512, POR_BSIZE_512},
+
+	{POR_1K, POR_BSIZE_1K},
+	{POR_2K, POR_BSIZE_2K},
+	{POR_4K, POR_BSIZE_4K},
+	{POR_8K, POR_BSIZE_8K},
+	{POR_16K, POR_BSIZE_16K},
+	{POR_32K, POR_BSIZE_32K},
+	{POR_64K, POR_BSIZE_64K},
+	{POR_128K, POR_BSIZE_128K},
+	{POR_256K, POR_BSIZE_256K},
+	{POR_512K, POR_BSIZE_512K},
+
+	{POR_1M, POR_BSIZE_1M},
+	{POR_2M, POR_BSIZE_2M},
+	{POR_4M, POR_BSIZE_4M},
+	{POR_8M, POR_BSIZE_8M},
+	{POR_16M, POR_BSIZE_16M},
+	{POR_32M, POR_BSIZE_32M},
+	{POR_64M, POR_BSIZE_64M}
+};
+
+#define to_mx31ads_pcmcia_socket(x)	container_of(x, struct mx31ads_pcmcia_socket, socket)
+
+/* mx31ads_pcmcia_find_bsize()
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * Find the bsize according to the window size passed in
+ *
+ * Return:
+ */
+static int mx31ads_pcmcia_find_bsize(unsigned long win_size)
+{
+	int i, nr = sizeof(bsize_map) / sizeof(bsize_map_t);
+	int bsize = -1;
+
+	for (i = 0; i < nr; i++) {
+		if (bsize_map[i].win_size == win_size) {
+			bsize = bsize_map[i].bsize;
+			break;
+		}
+	}
+
+	pr_debug(KERN_INFO "nr = %d bsize = 0x%0x\n", nr, bsize);
+	if (bsize < 0 || i > nr) {
+		pr_debug(KERN_INFO "No such bsize\n");
+		return -ENODEV;
+	}
+
+	return bsize;
+}
+
+/* mx31ads_common_pcmcia_sock_init()
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * (Re-)Initialise the socket, turning on status interrupts
+ * and PCMCIA bus.  This must wait for power to stabilise
+ * so that the card status signals report correctly.
+ *
+ * Returns: 0
+ */
+static int mx31ads_common_pcmcia_sock_init(struct pcmcia_socket *sock)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+
+	pr_debug(KERN_INFO "initializing socket\n");
+
+	skt->ops->socket_init(skt);
+	return 0;
+}
+
+/*
+ * mx31ads_common_pcmcia_config_skt
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * Convert PCMCIA socket state to our socket configure structure.
+ */
+static int
+mx31ads_common_pcmcia_config_skt(struct mx31ads_pcmcia_socket *skt,
+				 socket_state_t * state)
+{
+	int ret;
+
+	ret = skt->ops->configure_socket(skt, state);
+	if (ret == 0) {
+		/*
+		 * This really needs a better solution.  The IRQ
+		 * may or may not be claimed by the driver.
+		 */
+		if (skt->irq_state != 1 && state->io_irq) {
+			skt->irq_state = 1;
+			set_irq_type(skt->irq, IRQF_TRIGGER_FALLING);
+		} else if (skt->irq_state == 1 && state->io_irq == 0) {
+			skt->irq_state = 0;
+			set_irq_type(skt->irq, IRQF_TRIGGER_RISING);
+		}
+
+		skt->cs_state = *state;
+	}
+
+	if (ret < 0)
+		pr_debug(KERN_ERR "mx31ads_common_pcmcia: unable to configure"
+			 " socket\n");
+
+	return ret;
+}
+
+/*
+ * mx31ads_common_pcmcia_suspend()
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * Remove power on the socket, disable IRQs from the card.
+ * Turn off status interrupts, and disable the PCMCIA bus.
+ *
+ * Returns: 0
+ */
+static int mx31ads_common_pcmcia_suspend(struct pcmcia_socket *sock)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+	int ret;
+
+	pr_debug(KERN_INFO "suspending socket\n");
+
+	ret = mx31ads_common_pcmcia_config_skt(skt, &dead_socket);
+	if (ret == 0)
+		skt->ops->socket_suspend(skt);
+
+	return ret;
+}
+
+static unsigned int mx31ads_common_pcmcia_skt_state(struct mx31ads_pcmcia_socket
+						    *skt)
+{
+	struct pcmcia_state state;
+	unsigned int stat;
+
+	memset(&state, 0, sizeof(struct pcmcia_state));
+
+	skt->ops->socket_state(skt, &state);
+
+	stat = state.detect ? SS_DETECT : 0;
+	stat |= state.ready ? SS_READY : 0;
+	stat |= state.wrprot ? SS_WRPROT : 0;
+	stat |= state.vs_3v ? SS_3VCARD : 0;
+	stat |= state.vs_Xv ? SS_XVCARD : 0;
+
+	/* The power status of individual sockets is not available
+	 * explicitly from the hardware, so we just remember the state
+	 * and regurgitate it upon request:
+	 */
+	stat |= skt->cs_state.Vcc ? SS_POWERON : 0;
+
+	if (skt->cs_state.flags & SS_IOCARD)
+		stat |= state.bvd1 ? SS_STSCHG : 0;
+	else {
+		if (state.bvd1 == 0)
+			stat |= SS_BATDEAD;
+		else if (state.bvd2 == 0)
+			stat |= SS_BATWARN;
+	}
+
+	pr_debug(KERN_INFO "stat = 0x%08x\n", stat);
+
+	return stat;
+}
+
+/*
+ *  Implements the get_status() operation for the in-kernel PCMCIA
+ * service (formerly SS_GetStatus in Card Services). Essentially just
+ * fills in bits in `status' according to internal driver state or
+ * the value of the voltage detect chipselect register.
+ *
+ * As a debugging note, during card startup, the PCMCIA core issues
+ * three set_socket() commands in a row the first with RESET deasserted,
+ * the second with RESET asserted, and the last with RESET deasserted
+ * again. Following the third set_socket(), a get_status() command will
+ * be issued. The kernel is looking for the SS_READY flag (see
+ * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
+ *
+ * Returns: 0
+ */
+static int mx31ads_common_pcmcia_get_status(struct pcmcia_socket *sock,
+					    unsigned int *status)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+
+	skt->status = mx31ads_common_pcmcia_skt_state(skt);
+	*status = skt->status;
+
+	return 0;
+}
+
+/*
+ * Implements the set_socket() operation for the in-kernel PCMCIA
+ * service (formerly SS_SetSocket in Card Services). We more or
+ * less punt all of this work and let the kernel handle the details
+ * of power configuration, reset, &c. We also record the value of
+ * `state' in order to regurgitate it to the PCMCIA core later.
+ *
+ * Returns: 0
+ */
+static int mx31ads_common_pcmcia_set_socket(struct pcmcia_socket *sock,
+					    socket_state_t * state)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+
+	pr_debug(KERN_INFO
+		 "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
+		 (state->csc_mask == 0) ? "<NONE> " : "",
+		 (state->csc_mask & SS_DETECT) ? "DETECT " : "",
+		 (state->csc_mask & SS_READY) ? "READY " : "",
+		 (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
+		 (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
+		 (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
+		 (state->flags == 0) ? "<NONE> " : "",
+		 (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
+		 (state->flags & SS_IOCARD) ? "IOCARD " : "",
+		 (state->flags & SS_RESET) ? "RESET " : "",
+		 (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
+		 (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
+		 state->Vcc, state->Vpp, state->io_irq);
+
+	pr_debug(KERN_INFO
+		 "csc_mask: %08x flags: %08x Vcc: %d Vpp: %d io_irq: %d\n",
+		 state->csc_mask, state->flags, state->Vcc, state->Vpp,
+		 state->io_irq);
+
+	return mx31ads_common_pcmcia_config_skt(skt, state);
+}
+
+/*
+ * Set address and profile to window registers PBR, POR, POFR
+ */
+static int mx31ads_pcmcia_set_window_reg(ulong start, ulong end, u_int window)
+{
+	int bsize;
+	ulong size = end - start + 1;
+
+	bsize = mx31ads_pcmcia_find_bsize(size);
+	if (bsize < 0) {
+		pr_debug("Cannot set the window register\n");
+		return -1;
+	}
+	/* Disable the window */
+	_reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV;
+
+	/* Set PBR, POR, POFR */
+	_reg_PCMCIA_PBR(window) = start;
+	_reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PRS_MASK
+				     | PCMCIA_POR_WPEN
+				     | PCMCIA_POR_WP
+				     | PCMCIA_POR_BSIZE_MASK
+				     | PCMCIA_POR_PPS_8);
+	_reg_PCMCIA_POR(window) |= bsize | PCMCIA_POR_PPS_16;
+
+	switch (window) {
+	case IO_WINDOW:
+		_reg_PCMCIA_POR(window) |= PCMCIA_POR_PRS(PCMCIA_POR_PRS_IO);
+		break;
+
+	case ATTRIBUTE_MEMORY_WINDOW:
+		_reg_PCMCIA_POR(window) |=
+		    PCMCIA_POR_PRS(PCMCIA_POR_PRS_ATTRIBUTE);
+		break;
+
+	case COMMON_MEMORY_WINDOW:
+		_reg_PCMCIA_POR(window) |=
+		    PCMCIA_POR_PRS(PCMCIA_POR_PRS_COMMON);
+		break;
+
+	default:
+		pr_debug("Window %d is not support\n", window);
+		return -1;
+	}
+	_reg_PCMCIA_POFR(window) = 0;
+
+	/* Enable the window */
+	_reg_PCMCIA_POR(window) |= PCMCIA_POR_PV;
+
+	return 0;
+}
+
+/*
+ * Implements the set_io_map() operation for the in-kernel PCMCIA
+ * service (formerly SS_SetIOMap in Card Services). We configure
+ * the map speed as requested, but override the address ranges
+ * supplied by Card Services.
+ *
+ * Returns: 0 on success, -1 on error
+ */
+static int
+mx31ads_common_pcmcia_set_io_map(struct pcmcia_socket *sock,
+				 struct pccard_io_map *map)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+	unsigned short speed = map->speed;
+
+	pr_debug("map %u  speed %u start 0x%08x stop 0x%08x\n",
+		 map->map, map->speed, map->start, map->stop);
+	pr_debug("flags: %s%s%s%s%s%s%s%s\n",
+		 (map->flags == 0) ? "<NONE>" : "",
+		 (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
+		 (map->flags & MAP_16BIT) ? "16BIT " : "",
+		 (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
+		 (map->flags & MAP_0WS) ? "0WS " : "",
+		 (map->flags & MAP_WRPROT) ? "WRPROT " : "",
+		 (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
+		 (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
+
+	if (map->map >= MAX_IO_WIN) {
+		pr_debug(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__,
+			 map->map);
+		return -1;
+	}
+
+	if (map->flags & MAP_ACTIVE) {
+		if (speed == 0)
+			speed = PCMCIA_IO_ACCESS;
+	} else {
+		speed = 0;
+	}
+
+	skt->spd_io[map->map] = speed;
+	skt->ops->set_timing(skt);
+
+	if (map->stop == 1)
+		map->stop = PAGE_SIZE - 1;
+
+	skt->socket.io_offset = (unsigned long)skt->virt_io;
+	map->stop -= map->start;
+	map->stop += (unsigned long)skt->virt_io;
+	map->start = (unsigned long)skt->virt_io;
+
+	mx31ads_pcmcia_set_window_reg(skt->res_io.start, skt->res_io.end,
+				      IO_WINDOW);
+
+	pr_debug(KERN_ERR "IO window: _reg_PCMCIA_PBR(%d) = %08x\n",
+		 IO_WINDOW, _reg_PCMCIA_PBR(IO_WINDOW));
+	pr_debug(KERN_ERR "IO window: _reg_PCMCIA_POR(%d) = %08x\n",
+		 IO_WINDOW, _reg_PCMCIA_POR(IO_WINDOW));
+
+	return 0;
+}
+
+/*
+ * Implements the set_mem_map() operation for the in-kernel PCMCIA
+ * service (formerly SS_SetMemMap in Card Services). We configure
+ * the map speed as requested, but override the address ranges
+ * supplied by Card Services.
+ *
+ * Returns: 0 on success, -1 on error
+ */
+static int
+mx31ads_common_pcmcia_set_mem_map(struct pcmcia_socket *sock,
+				  struct pccard_mem_map *map)
+{
+	struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock);
+	struct resource *res;
+	unsigned short speed = map->speed;
+
+	pr_debug
+	    (KERN_INFO
+	     "map %u speed %u card_start %08x flags%08x static_start %08lx\n",
+	     map->map, map->speed, map->card_start, map->flags,
+	     map->static_start);
+	pr_debug(KERN_INFO "flags: %s%s%s%s%s%s%s%s\n",
+		 (map->flags == 0) ? "<NONE>" : "",
+		 (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
+		 (map->flags & MAP_16BIT) ? "16BIT " : "",
+		 (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
+		 (map->flags & MAP_0WS) ? "0WS " : "",
+		 (map->flags & MAP_WRPROT) ? "WRPROT " : "",
+		 (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
+		 (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
+
+	if (map->map >= MAX_WIN)
+		return -EINVAL;
+
+	if (map->flags & MAP_ACTIVE) {
+		if (speed == 0)
+			speed = 300;
+	} else {
+		speed = 0;
+	}
+
+	if (map->flags & MAP_ATTRIB) {
+		res = &skt->res_attr;
+		skt->spd_attr[map->map] = speed;
+		skt->spd_mem[map->map] = 0;
+		mx31ads_pcmcia_set_window_reg(res->start, res->end,
+					      ATTRIBUTE_MEMORY_WINDOW);
+
+		pr_debug(KERN_INFO "Attr window: _reg_PCMCIA_PBR(%d) = %08x\n",
+			 ATTRIBUTE_MEMORY_WINDOW,
+			 _reg_PCMCIA_PBR(ATTRIBUTE_MEMORY_WINDOW));
+		pr_debug(KERN_INFO "_reg_PCMCIA_POR(%d) = %08x\n",
+			 ATTRIBUTE_MEMORY_WINDOW,
+			 _reg_PCMCIA_POR(ATTRIBUTE_MEMORY_WINDOW));
+
+	} else {
+		res = &skt->res_mem;
+		skt->spd_attr[map->map] = 0;
+		skt->spd_mem[map->map] = speed;
+		mx31ads_pcmcia_set_window_reg(res->start, res->end,
+					      COMMON_MEMORY_WINDOW);
+
+		pr_debug(KERN_INFO "Com window: _reg_PCMCIA_PBR(%d) = %08x\n",
+			 COMMON_MEMORY_WINDOW,
+			 _reg_PCMCIA_PBR(COMMON_MEMORY_WINDOW));
+		pr_debug(KERN_INFO "Com window: _reg_PCMCIA_POR(%d) = %08x\n",
+			 COMMON_MEMORY_WINDOW,
+			 _reg_PCMCIA_POR(COMMON_MEMORY_WINDOW));
+	}
+
+	skt->ops->set_timing(skt);
+
+	map->static_start = res->start + map->card_start;
+
+	return 0;
+}
+
+static struct pccard_operations mx31ads_common_pcmcia_operations = {
+	.init = mx31ads_common_pcmcia_sock_init,
+	.suspend = mx31ads_common_pcmcia_suspend,
+	.get_status = mx31ads_common_pcmcia_get_status,
+	.set_socket = mx31ads_common_pcmcia_set_socket,
+	.set_io_map = mx31ads_common_pcmcia_set_io_map,
+	.set_mem_map = mx31ads_common_pcmcia_set_mem_map,
+};
+
+/* ============================================================================== */
+
+static inline void mx31ads_pcmcia_irq_config(void)
+{
+	/* Setup irq */
+	_reg_PCMCIA_PER =
+	    (PCMCIA_PER_RDYLE | PCMCIA_PER_CDE1 | PCMCIA_PER_CDE2);
+}
+
+static inline void mx31ads_pcmcia_invalidate_windows(void)
+{
+	int i;
+
+	for (i = 0; i < PCMCIA_WINDOWS; i++) {
+		_reg_PCMCIA_PBR(i) = 0;
+		_reg_PCMCIA_POR(i) = 0;
+		_reg_PCMCIA_POFR(i) = 0;
+	}
+}
+
+extern void gpio_pcmcia_active(void);
+extern void gpio_pcmcia_inactive(void);
+
+static int mx31ads_pcmcia_hw_init(struct mx31ads_pcmcia_socket *skt)
+{
+	/* Configure the pins for PCMCIA */
+	gpio_pcmcia_active();
+
+	/*
+	 * enabling interrupts at this time causes a flood of interrupts
+	 * if a card is present, so wait for configure_socket
+	 * to enable them when requested.
+	 *
+	 * mx31ads_pcmcia_irq_config();
+	 */
+	mx31ads_pcmcia_invalidate_windows();
+
+	/* Register interrupt. */
+	skt->irq = MX31ADS_PCMCIA_IRQ;
+
+	return 0;
+}
+
+static void mx31ads_pcmcia_free_irq(struct mx31ads_pcmcia_socket *skt,
+				    unsigned int irq)
+{
+	free_irq(irq, skt);
+}
+
+static void mx31ads_pcmcia_hw_shutdown(struct mx31ads_pcmcia_socket *skt)
+{
+	mx31ads_pcmcia_invalidate_windows();
+	mx31ads_pcmcia_free_irq(skt, MX31ADS_PCMCIA_IRQ);
+
+	/* Disable the pins */
+	gpio_pcmcia_inactive();
+}
+
+/*
+ * Get the socket state
+ */
+static void
+mx31ads_pcmcia_socket_state(struct mx31ads_pcmcia_socket *skt,
+			    struct pcmcia_state *state)
+{
+	unsigned long pins;
+
+	pins = _reg_PCMCIA_PIPR;
+	pr_debug(KERN_INFO "_reg_PCMCIA_PIPR = 0x%08lx\n", pins);
+
+	state->ready = (pins & PCMCIA_PIPR_RDY) ? 1 : 0;
+	state->bvd2 = (pins & PCMCIA_PIPR_BVD2) ? 1 : 0;
+	state->bvd1 = (pins & PCMCIA_PIPR_BVD1) ? 1 : 0;
+
+	if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) {
+		state->detect = 0;
+		skt->cs_state.csc_mask |= SS_INSERTION;
+	} else {
+		state->detect = 1;
+	}
+	state->detect = (pins & PCMCIA_PIPR_CD) ? 0 : 1;
+	state->wrprot = (pins & PCMCIA_PIPR_WP) ? 1 : 0;
+	state->poweron = (pins & PCMCIA_PIPR_POWERON) ? 1 : 0;
+#if 0
+	if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) {
+		state->detect = 0;
+		skt->cs_state.csc_mask |= SS_INSERTION;
+	} else {
+		state->detect = 1;
+	}
+	if (pins & PCMCIA_PIPR_VS_5V) {
+		state->vs_3v = 0;
+		skt->cs_state.Vcc = 33;
+	} else {
+		state->vs_3v = 1;
+		skt->cs_state.Vcc = 50;
+	}
+#endif
+	state->vs_3v = (pins & PCMCIA_PIPR_VS_5V) ? 0 : 1;
+	state->vs_Xv = 0;
+}
+
+static __inline__ void mx31ads_pcmcia_low_power(bool enable)
+{
+	if (enable)
+		_reg_PCMCIA_PGCR |= PCMCIA_PGCR_LPMEN;
+	else
+		_reg_PCMCIA_PGCR &= ~PCMCIA_PGCR_LPMEN;
+}
+
+static __inline__ void mx31ads_pcmcia_soft_reset(void)
+{
+	_reg_PCMCIA_PGCR |= PCMCIA_PGCR_RESET;
+	msleep(2);
+
+	_reg_PCMCIA_PGCR &= ~(PCMCIA_PGCR_RESET | PCMCIA_PGCR_LPMEN);
+	_reg_PCMCIA_PGCR |= PCMCIA_PGCR_POE;
+	msleep(2);
+	pr_debug(KERN_INFO "_reg_PCMCIA_PGCR = %08x\n", _reg_PCMCIA_PGCR);
+}
+
+static int
+mx31ads_pcmcia_configure_socket(struct mx31ads_pcmcia_socket *skt,
+				const socket_state_t * state)
+{
+	int ret = 0;
+
+	if (state->Vcc != 0 && state->Vcc != 33 && state->Vcc != 50) {
+		pr_debug(KERN_ERR "mx31ads-pcmcia: unrecognized Vcc %d\n",
+			 state->Vcc);
+		return -1;
+	}
+
+	pr_debug(KERN_INFO "PIPR = %x, desired Vcc = %d.%dV\n",
+		 _reg_PCMCIA_PIPR, state->Vcc / 10, state->Vcc % 10);
+
+	if (!(skt->socket.state & SOCKET_PRESENT) && (skt->pre_stat == 1)) {
+		pr_debug(KERN_INFO "Socket enter low power mode\n");
+		skt->pre_stat = 0;
+		mx31ads_pcmcia_low_power(1);
+	}
+
+	if (state->flags & SS_RESET) {
+		mx31ads_pcmcia_soft_reset();
+
+		/* clean out previous tenant's trash */
+		_reg_PCMCIA_PGSR = (PCMCIA_PGSR_NWINE
+				    | PCMCIA_PGSR_LPE
+				    | PCMCIA_PGSR_SE
+				    | PCMCIA_PGSR_CDE | PCMCIA_PGSR_WPE);
+	}
+	/* enable interrupts if requested, else turn 'em off */
+	if (skt->irq)
+		mx31ads_pcmcia_irq_config();
+	else
+		_reg_PCMCIA_PER = 0;
+
+	if (skt->socket.state & SOCKET_PRESENT) {
+		skt->pre_stat = 1;
+	}
+	return ret;
+}
+
+static void mx31ads_pcmcia_enable_irq(struct mx31ads_pcmcia_socket *skt,
+				      unsigned int irq)
+{
+	set_irq_type(irq, IRQF_TRIGGER_RISING);
+	set_irq_type(irq, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING);
+}
+
+static void mx31ads_pcmcia_disable_irq(struct mx31ads_pcmcia_socket *skt,
+				       unsigned int irq)
+{
+	set_irq_type(irq, IRQF_TRIGGER_NONE);
+}
+
+/*
+ * Enable card status IRQs on (re-)initialisation.  This can
+ * be called at initialisation, power management event, or
+ * pcmcia event.
+ */
+static void mx31ads_pcmcia_socket_init(struct mx31ads_pcmcia_socket *skt)
+{
+	mx31ads_pcmcia_soft_reset();
+
+	mx31ads_pcmcia_enable_irq(skt, MX31ADS_PCMCIA_IRQ);
+}
+
+/*
+ * Disable card status IRQ on suspend.
+ */
+static void mx31ads_pcmcia_socket_suspend(struct mx31ads_pcmcia_socket *skt)
+{
+	mx31ads_pcmcia_disable_irq(skt, MX31ADS_PCMCIA_IRQ);
+	mx31ads_pcmcia_low_power(1);
+}
+
+/* ==================================================================================== */
+
+/*
+ * PCMCIA strobe hold time
+ */
+static inline u_int mx31ads_pcmcia_por_psht(u_int pcmcia_cycle_ns,
+					    u_int hclk_cycle_ns)
+{
+	u_int psht;
+
+	return psht = pcmcia_cycle_ns / hclk_cycle_ns;
+}
+
+/*
+ * PCMCIA strobe set up time
+ */
+static inline u_int mx31ads_pcmcia_por_psst(u_int pcmcia_cycle_ns,
+					    u_int hclk_cycle_ns)
+{
+	u_int psst;
+
+	return psst = pcmcia_cycle_ns / hclk_cycle_ns;
+}
+
+/*
+ * PCMCIA strobe length time
+ */
+static inline u_int mx31ads_pcmcia_por_pslt(u_int pcmcia_cycle_ns,
+					    u_int hclk_cycle_ns)
+{
+	u_int pslt;
+
+	return pslt = pcmcia_cycle_ns / hclk_cycle_ns + 2;
+}
+
+/*
+ * mx31ads_pcmcia_default_mecr_timing
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * Calculate MECR clock wait states for given CPU clock
+ * speed and command wait state. This function can be over-
+ * written by a board specific version.
+ *
+ * The default is to simply calculate the BS values as specified in
+ * the INTEL SA1100 development manual
+ * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
+ * that's section 10.2.5 in _my_ version of the manual ;)
+ */
+static unsigned int mx31ads_pcmcia_default_mecr_timing(struct
+						       mx31ads_pcmcia_socket
+						       *skt,
+						       unsigned int cpu_speed,
+						       unsigned int cmd_time)
+{
+	return 0;
+}
+
+/*
+ * Calculate the timing code
+ */
+static u_int mx31ads_pcmcia_cal_code(u_int speed_ns, u_int clk_ns)
+{
+	u_int code;
+
+	code = PCMCIA_POR_PSHT(mx31ads_pcmcia_por_psht(speed_ns, clk_ns))
+	    | PCMCIA_POR_PSST(mx31ads_pcmcia_por_psst(speed_ns, clk_ns))
+	    | PCMCIA_POR_PSL(mx31ads_pcmcia_por_pslt(speed_ns, clk_ns));
+
+	return code;
+}
+
+/*
+ * set MECR value for socket <sock> based on this sockets
+ * io, mem and attribute space access speed.
+ * Call board specific BS value calculation to allow boards
+ * to tweak the BS values.
+ */
+static int mx31ads_pcmcia_set_window_timing(u_int speed_ns, u_int window,
+					    u_int clk_ns)
+{
+	u_int code = 0;
+
+	switch (window) {
+	case IO_WINDOW:
+		code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns);
+		break;
+	case COMMON_MEMORY_WINDOW:
+		code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns);
+		break;
+	case ATTRIBUTE_MEMORY_WINDOW:
+		code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns);
+		break;
+	default:
+		break;
+	}
+
+	/* Disable the window */
+	_reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV;
+
+	/* Clear the register fisrt */
+	_reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PSST_MASK
+				     | PCMCIA_POR_PSL_MASK
+				     | PCMCIA_POR_PSHT_MASK);
+	/* And then set the register */
+	_reg_PCMCIA_POR(window) |= code;
+
+	/* Enable the window */
+	_reg_PCMCIA_POR(window) |= PCMCIA_POR_PV;
+
+	return 0;
+}
+
+static unsigned short calc_speed(unsigned short *spds, int num,
+				 unsigned short dflt)
+{
+	unsigned short speed = 0;
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (speed < spds[i])
+			speed = spds[i];
+	if (speed == 0)
+		speed = dflt;
+
+	return speed;
+}
+
+static void
+mx31ads_common_pcmcia_get_timing(struct mx31ads_pcmcia_socket *skt,
+				 struct mx31ads_pcmcia_timing *timing)
+{
+	timing->io = calc_speed(skt->spd_io, MAX_IO_WIN, PCMCIA_IO_ACCESS);
+	timing->mem = calc_speed(skt->spd_mem, MAX_WIN, PCMCIA_3V_MEM_ACCESS);
+	timing->attr =
+	    calc_speed(skt->spd_attr, MAX_WIN, PCMCIA_ATTR_MEM_ACCESS);
+}
+
+static int mx31ads_pcmcia_set_timing(struct mx31ads_pcmcia_socket *skt)
+{
+	u_int clk_ns;
+	struct mx31ads_pcmcia_timing timing;
+
+	/* How many nanoseconds */
+	clk_ns = (1000 * 1000 * 1000) / clk_get_rate(skt->clk);
+	pr_debug(KERN_INFO "clk_ns = %d\n", clk_ns);
+
+	mx31ads_common_pcmcia_get_timing(skt, &timing);
+	pr_debug(KERN_INFO "timing: io %d, mem %d, attr %d\n", timing.io,
+		 timing.mem, timing.attr);
+
+	mx31ads_pcmcia_set_window_timing(timing.io, IO_WINDOW, clk_ns);
+	mx31ads_pcmcia_set_window_timing(timing.mem, COMMON_MEMORY_WINDOW,
+					 clk_ns);
+	mx31ads_pcmcia_set_window_timing(timing.attr, ATTRIBUTE_MEMORY_WINDOW,
+					 clk_ns);
+
+	return 0;
+}
+
+static int mx31ads_pcmcia_show_timing(struct mx31ads_pcmcia_socket *skt,
+				      char *buf)
+{
+	return 0;
+}
+
+static struct pcmcia_low_level mx31ads_pcmcia_ops = {
+	.owner = THIS_MODULE,
+	.hw_init = mx31ads_pcmcia_hw_init,
+	.hw_shutdown = mx31ads_pcmcia_hw_shutdown,
+	.socket_state = mx31ads_pcmcia_socket_state,
+	.configure_socket = mx31ads_pcmcia_configure_socket,
+
+	.socket_init = mx31ads_pcmcia_socket_init,
+	.socket_suspend = mx31ads_pcmcia_socket_suspend,
+
+	.get_timing = mx31ads_pcmcia_default_mecr_timing,
+	.set_timing = mx31ads_pcmcia_set_timing,
+	.show_timing = mx31ads_pcmcia_show_timing,
+};
+
+/* =================================================================================== */
+
+LIST_HEAD(mx31ads_pcmcia_sockets);
+DECLARE_MUTEX(mx31ads_pcmcia_sockets_lock);
+
+static DEFINE_SPINLOCK(status_lock);
+
+struct bittbl {
+	unsigned int mask;
+	const char *name;
+};
+
+static struct bittbl status_bits[] = {
+	{SS_WRPROT, "SS_WRPROT"},
+	{SS_BATDEAD, "SS_BATDEAD"},
+	{SS_BATWARN, "SS_BATWARN"},
+	{SS_READY, "SS_READY"},
+	{SS_DETECT, "SS_DETECT"},
+	{SS_POWERON, "SS_POWERON"},
+	{SS_STSCHG, "SS_STSCHG"},
+	{SS_3VCARD, "SS_3VCARD"},
+	{SS_XVCARD, "SS_XVCARD"},
+};
+
+static struct bittbl conf_bits[] = {
+	{SS_PWR_AUTO, "SS_PWR_AUTO"},
+	{SS_IOCARD, "SS_IOCARD"},
+	{SS_RESET, "SS_RESET"},
+	{SS_DMA_MODE, "SS_DMA_MODE"},
+	{SS_SPKR_ENA, "SS_SPKR_ENA"},
+	{SS_OUTPUT_ENA, "SS_OUTPUT_ENA"},
+};
+
+static void
+dump_bits(char **p, const char *prefix, unsigned int val, struct bittbl *bits,
+	  int sz)
+{
+	char *b = *p;
+	int i;
+
+	b += sprintf(b, "%-9s:", prefix);
+	for (i = 0; i < sz; i++)
+		if (val & bits[i].mask)
+			b += sprintf(b, " %s", bits[i].name);
+	*b++ = '\n';
+	*p = b;
+}
+
+/*
+ * Implements the /sys/class/pcmcia_socket/??/status file.
+ *
+ * Returns: the number of characters added to the buffer
+ */
+static ssize_t show_status(struct device *dev, struct device_attribute *attr,
+			   char *buf)
+{
+	struct mx31ads_pcmcia_socket *skt =
+	    container_of(dev, struct mx31ads_pcmcia_socket, socket.dev);
+	char *p = buf;
+
+	p += sprintf(p, "slot     : %d\n", skt->nr);
+
+	dump_bits(&p, "status", skt->status,
+		  status_bits, ARRAY_SIZE(status_bits));
+	dump_bits(&p, "csc_mask", skt->cs_state.csc_mask,
+		  status_bits, ARRAY_SIZE(status_bits));
+	dump_bits(&p, "cs_flags", skt->cs_state.flags,
+		  conf_bits, ARRAY_SIZE(conf_bits));
+
+	p += sprintf(p, "Vcc      : %d\n", skt->cs_state.Vcc);
+	p += sprintf(p, "Vpp      : %d\n", skt->cs_state.Vpp);
+	p += sprintf(p, "IRQ      : %d (%d)\n", skt->cs_state.io_irq, skt->irq);
+	if (skt->ops->show_timing)
+		p += skt->ops->show_timing(skt, p);
+
+	return p - buf;
+}
+
+static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
+
+static void mx31ads_common_check_status(struct mx31ads_pcmcia_socket *skt)
+{
+	unsigned int events;
+
+	pr_debug(KERN_INFO "entering PCMCIA monitoring thread\n");
+
+	do {
+		unsigned int status;
+		unsigned long flags;
+
+		status = mx31ads_common_pcmcia_skt_state(skt);
+
+		spin_lock_irqsave(&status_lock, flags);
+		events = (status ^ skt->status) & skt->cs_state.csc_mask;
+		skt->status = status;
+		spin_unlock_irqrestore(&status_lock, flags);
+
+		pr_debug(KERN_INFO "events: %s%s%s%s%s%s\n",
+			 events == 0 ? "<NONE>" : "",
+			 events & SS_DETECT ? "DETECT " : "",
+			 events & SS_READY ? "READY " : "",
+			 events & SS_BATDEAD ? "BATDEAD " : "",
+			 events & SS_BATWARN ? "BATWARN " : "",
+			 events & SS_STSCHG ? "STSCHG " : "");
+
+		if (events)
+			pcmcia_parse_events(&skt->socket, events);
+	} while (events);
+}
+
+/*
+ * Service routine for socket driver interrupts (requested by the
+ * low-level PCMCIA init() operation via mx31ads_common_pcmcia_thread()).
+ * The actual interrupt-servicing work is performed by
+ * mx31ads_common_pcmcia_thread(), largely because the Card Services event-
+ * handling code performs scheduling operations which cannot be
+ * executed from within an interrupt context.
+ */
+static irqreturn_t mx31ads_common_pcmcia_interrupt(int irq, void *dev)
+{
+	struct mx31ads_pcmcia_socket *skt = dev;
+	volatile u32 pscr, pgsr;
+
+	dev_dbg(dev, "servicing IRQ %d\n", irq);
+
+	/* clear interrupt states */
+	pscr = _reg_PCMCIA_PSCR;
+	_reg_PCMCIA_PSCR = pscr;
+
+	pgsr = _reg_PCMCIA_PGSR;
+	_reg_PCMCIA_PGSR = pgsr;
+
+	mx31ads_common_check_status(skt);
+
+	return IRQ_HANDLED;
+}
+
+/* Let's poll for events in addition to IRQs since IRQ only is unreliable... */
+static void mx31ads_common_pcmcia_poll_event(unsigned long dummy)
+{
+	struct mx31ads_pcmcia_socket *skt =
+	    (struct mx31ads_pcmcia_socket *)dummy;
+	pr_debug(KERN_INFO "polling for events\n");
+
+	mod_timer(&skt->poll_timer, jiffies + PCMCIA_POLL_PERIOD);
+
+	mx31ads_common_check_status(skt);
+}
+
+#define mx31ads_pcmcia_cpufreq_register()
+#define mx31ads_pcmcia_cpufreq_unregister()
+
+static int mx31ads_common_drv_pcmcia_probe(struct platform_device *pdev,
+					   struct pcmcia_low_level *ops)
+{
+	struct mx31ads_pcmcia_socket *skt;
+	int vs, value, ret;
+	struct pccard_io_map map;
+
+	down(&mx31ads_pcmcia_sockets_lock);
+
+	skt = kzalloc(sizeof(struct mx31ads_pcmcia_socket), GFP_KERNEL);
+	if (!skt) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	/*
+	 * Initialise the socket structure.
+	 */
+	skt->socket.ops = &mx31ads_common_pcmcia_operations;
+	skt->socket.owner = ops->owner;
+	skt->socket.driver_data = skt;
+
+	init_timer(&skt->poll_timer);
+	skt->poll_timer.function = mx31ads_common_pcmcia_poll_event;
+	skt->poll_timer.data = (unsigned long)skt;
+	skt->poll_timer.expires = jiffies + PCMCIA_POLL_PERIOD;
+
+	skt->irq = MX31ADS_PCMCIA_IRQ;
+	skt->socket.dev.parent = &pdev->dev;
+	skt->ops = ops;
+
+	skt->clk = clk_get(NULL, "ahb_clk");
+
+	skt->res_skt.start = _PCMCIA(0);
+	skt->res_skt.end = _PCMCIA(0) + PCMCIASp - 1;
+	skt->res_skt.name = MX31ADS_PCMCIA;
+	skt->res_skt.flags = IORESOURCE_MEM;
+
+	ret = request_resource(&iomem_resource, &skt->res_skt);
+	if (ret)
+		goto out_err_1;
+
+	skt->res_io.start = _PCMCIAIO(0);
+	skt->res_io.end = _PCMCIAIO(0) + PCMCIAIOSp - 1;
+	skt->res_io.name = "io";
+	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+
+	ret = request_resource(&skt->res_skt, &skt->res_io);
+	if (ret)
+		goto out_err_2;
+
+	skt->res_mem.start = _PCMCIAMem(0);
+	skt->res_mem.end = _PCMCIAMem(0) + PCMCIAMemSp - 1;
+	skt->res_mem.name = "memory";
+	skt->res_mem.flags = IORESOURCE_MEM;
+
+	ret = request_resource(&skt->res_skt, &skt->res_mem);
+	if (ret)
+		goto out_err_3;
+
+	skt->res_attr.start = _PCMCIAAttr(0);
+	skt->res_attr.end = _PCMCIAAttr(0) + PCMCIAAttrSp - 1;
+	skt->res_attr.name = "attribute";
+	skt->res_attr.flags = IORESOURCE_MEM;
+
+	ret = request_resource(&skt->res_skt, &skt->res_attr);
+	if (ret)
+		goto out_err_4;
+
+	skt->virt_io = ioremap(skt->res_io.start, 0x10000);
+	if (skt->virt_io == NULL) {
+		ret = -ENOMEM;
+		goto out_err_5;
+	}
+
+	if (list_empty(&mx31ads_pcmcia_sockets))
+		mx31ads_pcmcia_cpufreq_register();
+
+	list_add(&skt->node, &mx31ads_pcmcia_sockets);
+
+	/*
+	 * We initialize default socket timing here, because
+	 * we are not guaranteed to see a SetIOMap operation at
+	 * runtime.
+	 */
+	ops->set_timing(skt);
+
+	ret = ops->hw_init(skt);
+	if (ret)
+		goto out_err_6;
+
+	ret = request_irq(skt->irq, mx31ads_common_pcmcia_interrupt,
+			  IRQF_SHARED | IRQF_DISABLED, "PCMCIA IRQ", skt);
+	if (ret)
+		goto out_err_6;
+
+	skt->socket.features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
+	skt->socket.resource_ops = &pccard_static_ops;
+	skt->socket.irq_mask = 0;
+	skt->socket.map_size = PCMCIAPrtSp;
+	skt->socket.pci_irq = skt->irq;
+	skt->socket.io_offset = (unsigned long)skt->virt_io;
+
+	skt->status = mx31ads_common_pcmcia_skt_state(skt);
+	skt->pre_stat = 0;
+	ret = pcmcia_register_socket(&skt->socket);
+	if (ret)
+		goto out_err_7;
+	/* FIXED ME  workaround for binding with ide-cs. ide usage io port 0x100~0x107 and 0x10e */
+	map.map = 0;
+	map.flags = MAP_ACTIVE | MAP_16BIT;
+	map.start = 0;
+	map.stop = PCMCIAIOSp - 1;
+	map.speed = 0;
+	mx31ads_common_pcmcia_set_io_map(&skt->socket, &map);
+
+	vs = _reg_PCMCIA_PIPR & PCMCIA_PIPR_VS;
+	value = vs & PCMCIA_PIPR_VS_5V ? 50 : 33;
+	dev_dbg(&pdev->dev, "PCMCIA: Voltage the card supports: %d.%dV\n",
+		value / 10, value % 10);
+
+	add_timer(&skt->poll_timer);
+
+	ret = device_create_file(&skt->socket.dev, &dev_attr_status);
+	if (ret < 0)
+		goto out_err_8;
+
+	platform_set_drvdata(pdev, skt);
+	ret = 0;
+	goto out;
+
+      out_err_8:
+	del_timer_sync(&skt->poll_timer);
+	pcmcia_unregister_socket(&skt->socket);
+
+      out_err_7:
+	flush_scheduled_work();
+	free_irq(skt->irq, skt);
+	ops->hw_shutdown(skt);
+      out_err_6:
+	list_del(&skt->node);
+	iounmap(skt->virt_io);
+      out_err_5:
+	release_resource(&skt->res_attr);
+      out_err_4:
+	release_resource(&skt->res_mem);
+      out_err_3:
+	release_resource(&skt->res_io);
+      out_err_2:
+	release_resource(&skt->res_skt);
+      out_err_1:
+
+	kfree(skt);
+      out:
+	up(&mx31ads_pcmcia_sockets_lock);
+	return ret;
+}
+
+static int mx31ads_drv_pcmcia_remove(struct platform_device *pdev)
+{
+	struct mx31ads_pcmcia_socket *skt = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	down(&mx31ads_pcmcia_sockets_lock);
+
+	del_timer_sync(&skt->poll_timer);
+
+	pcmcia_unregister_socket(&skt->socket);
+
+	flush_scheduled_work();
+
+	skt->ops->hw_shutdown(skt);
+
+	mx31ads_common_pcmcia_config_skt(skt, &dead_socket);
+
+	list_del(&skt->node);
+	iounmap(skt->virt_io);
+	skt->virt_io = NULL;
+	release_resource(&skt->res_attr);
+	release_resource(&skt->res_mem);
+	release_resource(&skt->res_io);
+	release_resource(&skt->res_skt);
+
+	if (list_empty(&mx31ads_pcmcia_sockets))
+		mx31ads_pcmcia_cpufreq_unregister();
+
+	up(&mx31ads_pcmcia_sockets_lock);
+
+	kfree(skt);
+
+	return 0;
+}
+
+static int mx31ads_drv_pcmcia_probe(struct platform_device *pdev)
+{
+	if (!machine_is_mx31ads())
+		return -ENODEV;
+
+	return mx31ads_common_drv_pcmcia_probe(pdev, &mx31ads_pcmcia_ops);
+}
+
+static int mx31ads_drv_pcmcia_suspend(struct platform_device *pdev,
+				      pm_message_t state)
+{
+	return pcmcia_socket_dev_suspend(&pdev->dev, state);
+}
+
+static int mx31ads_drv_pcmcia_resume(struct platform_device *pdev)
+{
+	return pcmcia_socket_dev_resume(&pdev->dev);
+}
+
+/*
+ * Low level functions
+ */
+static struct platform_driver mx31ads_pcmcia_driver = {
+	.driver = {
+		   .name = MX31ADS_PCMCIA,
+		   },
+	.probe = mx31ads_drv_pcmcia_probe,
+	.remove = mx31ads_drv_pcmcia_remove,
+	.suspend = mx31ads_drv_pcmcia_suspend,
+	.resume = mx31ads_drv_pcmcia_resume,
+};
+
+/* mx31ads_pcmcia_init()
+ *
+ */
+static int __init mx31ads_pcmcia_init(void)
+{
+	int ret;
+
+	if ((ret = platform_driver_register(&mx31ads_pcmcia_driver)))
+		return ret;
+	pr_debug(KERN_INFO "PCMCIA: Initialize i.Mx31 pcmcia socket\n");
+
+	return ret;
+}
+
+/* mx31ads_pcmcia_exit()
+ *
+ */
+static void __exit mx31ads_pcmcia_exit(void)
+{
+	platform_driver_unregister(&mx31ads_pcmcia_driver);
+}
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX31 PCMCIA Socket Controller");
+MODULE_LICENSE("GPL");
+
+module_init(mx31ads_pcmcia_init);
+module_exit(mx31ads_pcmcia_exit);
diff --git a/drivers/pcmcia/mx31ads-pcmcia.h b/drivers/pcmcia/mx31ads-pcmcia.h
new file mode 100644
index 000000000000..3f7014b3e8bf
--- /dev/null
+++ b/drivers/pcmcia/mx31ads-pcmcia.h
@@ -0,0 +1,155 @@
+/*
+ * linux/drivers/pcmcia/mx31ads-pcmcia.h
+ *
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This file contains definitions for the PCMCIA support code common to
+ * integrated SOCs like the i.Mx31 microprocessors.
+ */
+#ifndef _ASM_ARCH_PCMCIA
+#define _ASM_ARCH_PCMCIA
+
+/* include the world */
+#include <linux/cpufreq.h>
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/ss.h>
+#include <pcmcia/cistpl.h>
+#include "cs_internal.h"
+
+#define	MX31ADS_PCMCIA	"Mx31ads_pcmcia_socket"
+
+struct device;
+struct pcmcia_low_level;
+
+/*
+ * This structure encapsulates per-socket state which we might need to
+ * use when responding to a Card Services query of some kind.
+ */
+struct mx31ads_pcmcia_socket {
+	struct pcmcia_socket socket;
+
+	/*
+	 * Info from low level handler
+	 */
+	struct device *dev;
+	unsigned int nr;
+	unsigned int irq;
+
+	struct clk *clk;
+
+	/*
+	 * Core PCMCIA state
+	 */
+	struct pcmcia_low_level *ops;
+
+	unsigned int status;
+	unsigned int pre_stat;
+	socket_state_t cs_state;
+
+	unsigned short spd_io[MAX_IO_WIN];
+	unsigned short spd_mem[MAX_WIN];
+	unsigned short spd_attr[MAX_WIN];
+
+	struct resource res_skt;
+	struct resource res_io;
+	struct resource res_mem;
+	struct resource res_attr;
+	void *virt_io;
+
+	unsigned int irq_state;
+
+	struct timer_list poll_timer;
+	struct list_head node;
+};
+
+struct pcmcia_state {
+	unsigned detect:1,
+	    ready:1, bvd1:1, bvd2:1, wrprot:1, vs_3v:1, vs_Xv:1, poweron:1;
+};
+
+struct pcmcia_low_level {
+	struct module *owner;
+
+	/* first socket in system */
+	int first;
+	/* nr of sockets */
+	int nr;
+
+	int (*hw_init) (struct mx31ads_pcmcia_socket *);
+	void (*hw_shutdown) (struct mx31ads_pcmcia_socket *);
+
+	void (*socket_state) (struct mx31ads_pcmcia_socket *,
+			      struct pcmcia_state *);
+	int (*configure_socket) (struct mx31ads_pcmcia_socket *,
+				 const socket_state_t *);
+
+	/*
+	 * Enable card status IRQs on (re-)initialisation.  This can
+	 * be called at initialisation, power management event, or
+	 * pcmcia event.
+	 */
+	void (*socket_init) (struct mx31ads_pcmcia_socket *);
+
+	/*
+	 * Disable card status IRQs and PCMCIA bus on suspend.
+	 */
+	void (*socket_suspend) (struct mx31ads_pcmcia_socket *);
+
+	/*
+	 * Hardware specific timing routines.
+	 * If provided, the get_timing routine overrides the SOC default.
+	 */
+	unsigned int (*get_timing) (struct mx31ads_pcmcia_socket *,
+				    unsigned int, unsigned int);
+	int (*set_timing) (struct mx31ads_pcmcia_socket *);
+	int (*show_timing) (struct mx31ads_pcmcia_socket *, char *);
+
+#ifdef CONFIG_CPU_FREQ
+	/*
+	 * CPUFREQ support.
+	 */
+	int (*frequency_change) (struct mx31ads_pcmcia_socket *, unsigned long,
+				 struct cpufreq_freqs *);
+#endif
+};
+
+struct mx31ads_pcmcia_timing {
+	unsigned short io;
+	unsigned short mem;
+	unsigned short attr;
+};
+
+typedef struct {
+	ulong win_size;
+	int bsize;
+} bsize_map_t;
+
+/*
+ * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
+ * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
+ * a minimum value of 165ns, as well. Section 4.7.2 (describing
+ * common and attribute memory write timing) says that twWE has a
+ * minimum value of 150ns for a 250ns cycle time (for 5V operation;
+ * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
+ * operation, also section 4.7.4). Section 4.7.3 says that taOE
+ * has a maximum value of 150ns for a 300ns cycle time (for 5V
+ * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
+ *
+ * When configuring memory maps, Card Services appears to adopt the policy
+ * that a memory access time of "0" means "use the default." The default
+ * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
+ * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
+ * memory command width time is 300ns.
+ */
+#define PCMCIA_IO_ACCESS		(165)
+#define PCMCIA_5V_MEM_ACCESS	(150)
+#define PCMCIA_3V_MEM_ACCESS	(300)
+#define PCMCIA_ATTR_MEM_ACCESS	(300)
+
+/*
+ * The socket driver actually works nicely in interrupt-driven form,
+ * so the (relatively infrequent) polling is "just to be sure."
+ */
+#define PCMCIA_POLL_PERIOD    (2*HZ)
+#endif
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index bdbc4f73fcdc..f90ffbf4c436 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -103,4 +103,25 @@ config CHARGER_PCF50633
 	help
 	 Say Y to include support for NXP PCF50633 Main Battery Charger.
 
+config BATTERY_STMP3XXX
+	tristate "Sigmatel STMP3xxx SoC battery charger driver"
+	depends on ARCH_STMP3XXX
+	help
+	  Say Y to enable support for the battery charger state machine
+	  for the Sigmatel STMP3xxx based SoC's.
+
+config BATTERY_MXS
+	tristate "MXS SoC battery charger driver"
+	depends on ARCH_MXS
+	help
+	  Say Y to enable support for the battery charger state machine
+	  for the Sigmatel MXS based SoC's.
+
+config MXS_VBUS_CURRENT_DRAW
+	tristate "MXS SoC USB2.0 VBUS Current Limitation"
+	depends on ARCH_MXS
+	help
+	  Say Y to enable 100mA limitation when USB vbus power on system
+	  before enumeration to match USB2.0 requirement.
+
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 380d17c9ae29..cc430bda39d3 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -28,3 +28,5 @@ obj-$(CONFIG_BATTERY_BQ27x00)	+= bq27x00_battery.o
 obj-$(CONFIG_BATTERY_DA9030)	+= da9030_battery.o
 obj-$(CONFIG_BATTERY_MAX17040)	+= max17040_battery.o
 obj-$(CONFIG_CHARGER_PCF50633)	+= pcf50633-charger.o
+obj-$(CONFIG_BATTERY_STMP3XXX)	+= stmp37xx/
+obj-$(CONFIG_BATTERY_MXS)	+= mxs/
diff --git a/drivers/power/mxs/Makefile b/drivers/power/mxs/Makefile
new file mode 100644
index 000000000000..c7675a9ec52b
--- /dev/null
+++ b/drivers/power/mxs/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the MXS battery charger driver
+#
+
+obj-$(CONFIG_BATTERY_MXS) += mxs-battery.o
+
+mxs-battery-objs := ddi_bc_api.o ddi_bc_hw.o ddi_bc_init.o \
+		         ddi_bc_ramp.o ddi_bc_sm.o ddi_power_battery.o linux.o fiq.o
+
diff --git a/drivers/power/mxs/ddi_bc_api.c b/drivers/power/mxs/ddi_bc_api.c
new file mode 100644
index 000000000000..26d064bff9a2
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_api.c
@@ -0,0 +1,559 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* Includes */
+
+
+#include <linux/kernel.h>
+#include "ddi_bc_internal.h"
+
+
+/* Variables */
+
+
+/* This structure holds the current Battery Charger configuration. */
+
+ddi_bc_Cfg_t g_ddi_bc_Configuration;
+
+extern uint32_t g_ddi_bc_u32StateTimer;
+extern ddi_bc_BrokenReason_t ddi_bc_gBrokenReason;
+extern bool bRestartChargeCycle;
+
+
+/* Code */
+
+
+
+
+/* brief Report the Battery Charger configuration. */
+
+/* fntype Function */
+
+/* This function reports the Battery Charger configuration. */
+
+/* Note that, if the Battery Charger has not yet been initialized, the data */
+/* returned by this function is unknown. */
+
+/* param[in,out]  pCfg  A pointer to a structure that will receive the data. */
+
+
+void ddi_bc_QueryCfg(ddi_bc_Cfg_t *pCfg)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Return the current configuration. */
+	/* -------------------------------------------------------------------------- */
+
+	*pCfg = g_ddi_bc_Configuration;
+
+}
+
+
+
+/* brief Shut down the Battery Charger. */
+
+/* fntype Function */
+
+/* This function immediately shuts down the Battery Charger hardware and */
+/* returns the state machine to the Uninitialized state. Use this function to */
+/* safely mummify the battery charger before retiring it from memory. */
+
+
+void ddi_bc_ShutDown()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Uninitialized state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED;
+
+}
+
+
+
+/* brief Advances the state machine. */
+
+/* fntype Function */
+
+/* This function advances the state machine. */
+
+/* retval DDI_BC_STATUS_SUCCESS          If all goes well */
+/* retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+/* retval DDI_BC_STATUS_BROKEN           If the battery violated a time-out */
+/*                                        and has been declared broken. */
+
+
+ddi_bc_Status_t ddi_bc_StateMachine()
+{
+	int ret, state;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Execute the function for the current state. */
+	/* -------------------------------------------------------------------------- */
+
+	state = g_ddi_bc_State;
+	ret = (stateFunctionTable[g_ddi_bc_State] ());
+	if (state != g_ddi_bc_State)
+		pr_debug("Charger: transit from state %d to %d\n",
+			state, g_ddi_bc_State);
+	return ret;
+
+}
+
+
+
+/* brief Get the Battery Charger's current state. */
+
+/* fntype Function */
+
+/* This function returns the current state. */
+
+/* retval The current state. */
+
+
+ddi_bc_State_t ddi_bc_GetState()
+{
+	/* -------------------------------------------------------------------------- */
+	/* Return the current state. */
+	/* -------------------------------------------------------------------------- */
+
+	return g_ddi_bc_State;
+
+}
+
+
+
+/* brief Disable the Battery Charger. */
+
+/* fntype Function */
+
+/* This function forces the Battery Charger into the Disabled state. */
+
+/* retval DDI_BC_STATUS_SUCCESS          If all goes well */
+/* retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+
+
+ddi_bc_Status_t ddi_bc_SetDisable()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_BROKEN) {
+		return DDI_BC_STATUS_BROKEN;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. This will jam the current to zero and power off */
+	/* the charging hardware. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Disabled state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+
+/* brief Enable the Battery Charger. */
+
+/* fntype Function */
+
+/* If the Battery Charger is in the Disabled state, this function moves it to */
+/* the Waiting to Charge state. */
+
+/* retval DDI_BC_STATUS_SUCCESS          If all goes well */
+/* retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+/* retval DDI_BC_STATUS_NOT_DISABLED     If the Battery Charger is not */
+/*                                        disabled. */
+
+
+ddi_bc_Status_t ddi_bc_SetEnable()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If we're not in the Disabled state, this is pointless. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State != DDI_BC_STATE_DISABLED) {
+		return DDI_BC_STATUS_NOT_DISABLED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Waiting to Charge state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+
+/* brief Declare the battery to be broken. */
+
+/* fntype Function */
+
+/* This function forces the Battery Charger into the Broken state. */
+
+/* retval DDI_BC_STATUS_SUCCESS          If all goes well */
+/* retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+
+
+ddi_bc_Status_t ddi_bc_SetBroken()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. This will jam the current to zero and power off */
+	/* the charging hardware. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Broken state. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+	g_ddi_bc_State = DDI_BC_STATE_BROKEN;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+
+/* brief Declare the battery to be fixed. */
+
+/* fntype Function */
+
+/* If the Battery Charger is in the Broken state, this function moves it to */
+/* the Disabled state. */
+
+/* retval DDI_BC_STATUS_SUCCESS          If all goes well */
+/* retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+/* retval DDI_BC_STATUS_NOT_BROKEN       If the Battery Charger is not broken. */
+
+
+ddi_bc_Status_t ddi_bc_SetFixed()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If we're not in the Broken state, this is pointless. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State != DDI_BC_STATE_BROKEN) {
+		return DDI_BC_STATUS_NOT_BROKEN;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Unitialize the Broken Reason */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED;
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Disabled state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+
+/* brief Set the current limit. */
+
+/* fntype Function */
+
+/* This function applies a limit to the current that the Battery Charger can */
+/* draw. */
+
+/* param[in]  u16Limit  The maximum current the Battery Charger can draw */
+/*                       (in mA). */
+
+/* retval  The expressible version of the limit. */
+
+
+uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Set the limit and return what is actually expressible. */
+	/* -------------------------------------------------------------------------- */
+
+	return ddi_bc_RampSetLimit(u16Limit);
+
+}
+
+
+
+/* brief Report the current limit. */
+
+/* fntype Function */
+
+/* This function reports the limit to the current that the Battery Charger can */
+/* draw. */
+
+/* retval  The current limit. */
+
+
+uint16_t ddi_bc_GetCurrentLimit(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Set the limit and return what is actually expressible. */
+	/* -------------------------------------------------------------------------- */
+
+	return ddi_bc_RampGetLimit();
+
+}
+
+
+
+/* brief Set the battery charger state machine period. */
+
+/* fntype Function */
+
+/* This function sets a new state machine period.  The Period and Slope should */
+/* be coordinated to achieve the minimal ramp step current which will minimize */
+/* transients on the system. */
+
+/* param[in]  u32StateMachinePeriod  (in milliseconds) */
+/* param[in]  u16CurrentRampSlope (in mA/s) */
+
+/* retval SUCCESS                        If all goes well */
+/* retval ERROR_DDI_BCM_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                        initialized. */
+
+
+ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t u32StateMachinePeriod,
+					    uint16_t u16CurrentRampSlope)
+{
+	/* -------------------------------------------------------------------------- */
+	/* Check if we've been initialized yet. */
+	/* -------------------------------------------------------------------------- */
+	bool bDisableRequired;
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+
+	if (g_ddi_bc_State == DDI_BC_STATE_DISABLED)
+		bDisableRequired = false;
+	else {
+		bDisableRequired = true;
+		ddi_bc_SetDisable();
+	}
+
+	/* Looking at the code, changing the period while the battery charger is running */
+	/* doesn't seem to have a negative affect.  One could wrap this in the mutex */
+	/* or implement further coordination if it did. */
+	g_ddi_bc_Configuration.u32StateMachinePeriod = u32StateMachinePeriod;
+	g_ddi_bc_Configuration.u16CurrentRampSlope = u16CurrentRampSlope;
+
+	if (bDisableRequired)
+		ddi_bc_SetEnable();
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+
+/* brief Report the state machine period. */
+
+/* fntype Function */
+
+/* This function reports the battery charger period. */
+
+/* retval  The battery charger period (in milliseconds). */
+
+
+uint32_t ddi_bc_GetStateMachinePeriod()
+{
+	return g_ddi_bc_Configuration.u32StateMachinePeriod;
+}
+
+
+
+/* brief Report the current ramp slope. */
+
+/* fntype Function */
+
+/* This function reports the current ramp slope. */
+
+/* retval  The current ramp slope (in mA/s). */
+
+
+uint32_t ddi_bc_GetCurrentRampSlope()
+{
+	return g_ddi_bc_Configuration.u16CurrentRampSlope;
+}
+
+
+
+/* brief Report the time spent in the present state (milliseconds) */
+
+/* fntype Function */
+
+/* This function reports the time spent in the present charging state.  Note that */
+/* for the states that actually charge the battery, this time does not include the */
+/* time spent under alarm conditions such as die termperature alarm or battery */
+/* temperature alarm. */
+
+/* retval  The time spent in the current state in milliseconds. */
+
+
+uint32_t ddi_bc_GetStateTime(void)
+{
+	return g_ddi_bc_u32StateTimer;
+}
+
+
+
+/* brief Report the reason for being in the broken state */
+
+/* fntype Function */
+
+
+/* retval  ddi_bc_BrokenReason_t enumeration */
+
+
+ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void)
+{
+	return ddi_bc_gBrokenReason;
+}
+
+
+
+/* brief Restart the charge cycle */
+
+/* fntype Function */
+
+
+/* retval  SUCCESS */
+
+
+ddi_bc_Status_t ddi_bc_ForceChargingToStart(void)
+{
+	static int16_t restarts;
+
+	if (restarts < DDI_BC_MAX_RESTART_CYCLES) {
+		restarts++;
+		bRestartChargeCycle = true;
+	}
+
+	return DDI_BC_STATUS_SUCCESS;
+}
+
+
+/* End of file */
+
+/* @} */
diff --git a/drivers/power/mxs/ddi_bc_hw.c b/drivers/power/mxs/ddi_bc_hw.c
new file mode 100644
index 000000000000..f1fdb6f2b065
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_hw.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ddi_bc_internal.h"
+
+
+/* Includes and external references */
+
+
+
+/* Variables */
+
+
+
+/* Code */
+
+
+
+/*  */
+/* brief Report if the battery charging hardware is available. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports if the battery charging hardware is available by */
+/*  reading the corresponding laser fuse bit. */
+/*  */
+/* retval  Zero if the battery charging hardware is not available. Non-zero */
+/*           otherwise. */
+/*  */
+
+int ddi_bc_hwBatteryChargerIsEnabled(void)
+{
+	/* TODO: replace ddi_bc_hwBatteryChargerIsEnabled with the function below in the code */
+	return (int)ddi_power_GetBatteryChargerEnabled();
+}
+
+
+/*  */
+/* brief Report the battery configuration. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the hardware battery configuration. */
+/*  */
+/* retval  A value that indicates the battery configuration. */
+/*  */
+
+ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void)
+{
+	/* TODO: replace ddi_bc_hwGetBatteryMode() with the function below. */
+	return (ddi_bc_BatteryMode_t) ddi_power_GetBatteryMode();
+}
+
+
+
+/*  */
+/* brief Report the voltage across the battery. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the voltage across the battery. */
+/*  */
+/* retval The voltage across the battery, in mV. */
+/*  */
+
+uint16_t ddi_bc_hwGetBatteryVoltage(void)
+{
+	/* TODO: replace ddi_bc_hwGetBattery with function below */
+	return ddi_power_GetBattery();
+}
+
+
+/*  */
+/* brief Report on the presence of the power supply. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function repots on whether or not the 5V power supply is present. */
+/*  */
+/* retval  Zero if the power supply is not present. Non-zero otherwise. */
+/*  */
+
+int ddi_bc_hwPowerSupplyIsPresent(void)
+{
+	/* TODO: replace ddi_bc_hwPowerSupplyIsPresent with the functino below. */
+	return (int)ddi_power_Get5vPresentFlag();
+}
+
+
+/*  */
+/* brief Report the maximum charging current. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the maximum charging current that will be offered to */
+/*  the battery, as currently set in the hardware. */
+/*  */
+/* retval  The maximum current setting in the hardware. */
+/*  */
+
+uint16_t ddi_bc_hwGetMaxCurrent(void)
+{
+	/* TODO: replace ddi_bc_hwGetMaxCurrent() with the below function */
+	return (uint16_t) ddi_power_GetMaxBatteryChargeCurrent();
+}
+
+
+/*  */
+/* brief Set the maximum charging current. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function sets the maximum charging current that will be offered to the */
+/*  battery. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 780mA (see the data sheet for details). If the given */
+/*  current cannot be expressed exactly, then the largest expressible smaller */
+/*  value will be used. The return reports the actual value that was effected. */
+/*  */
+/* param[in]  u16Limit  The maximum charging current, in mA. */
+/*  */
+/* retval  The actual value that was effected. */
+/*  */
+
+uint16_t ddi_bc_hwSetMaxCurrent(uint16_t u16Limit)
+{
+	/* TODO: replace ddi_bc_hwSetMaxChargeCurrent */
+	return ddi_power_SetMaxBatteryChargeCurrent(u16Limit);
+}
+
+
+/*  */
+/* brief Set the charging current threshold. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function sets the charging current threshold. When the actual current */
+/*  flow to the battery is less than this threshold, the HW_POWER_STS.CHRGSTS */
+/*  flag is clear. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 180mA (see the data sheet for details). If the given */
+/*  current cannot be expressed exactly, then the largest expressible smaller */
+/*  value will be used. The return reports the actual value that was effected. */
+/*  */
+/* param[in]  u16Threshold  The charging current threshold, in mA. */
+/*  */
+/* retval  The actual value that was effected. */
+/*  */
+
+uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t u16Threshold)
+{
+	/* TODO: replace calls to ddi_bc_hwSetCurrentThreshold with the one below */
+	return ddi_power_SetBatteryChargeCurrentThreshold(u16Threshold);
+
+}
+
+
+/*  */
+/* brief Report the charging current threshold. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the charging current threshold. When the actual */
+/*  current flow to the battery is less than this threshold, the */
+/*  HW_POWER_STS.CHRGSTS flag is clear. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 180mA (see the data sheet for details). */
+/*  */
+/* retval  The charging current threshold, in mA. */
+/*  */
+
+uint16_t ddi_bc_hwGetCurrentThreshold(void)
+{
+	/* TODO: replace calls to ddi_bc_hwGetCurrentThreshold with function below */
+	return ddi_power_GetBatteryChargeCurrentThreshold();
+}
+
+
+/*  */
+/* brief Report if the charger hardware power is on. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports if the charger hardware power is on. */
+/*  */
+/* retval  Zero if the charger hardware is not powered. Non-zero otherwise. */
+/*  */
+
+int ddi_bc_hwChargerPowerIsOn(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */
+	/* stands for "power down". Thus, when the bit is set, the battery charger */
+	/* hardware is POWERED DOWN. */
+	/* -------------------------------------------------------------------------- */
+
+	/* -------------------------------------------------------------------------- */
+	/* Read the register and return the result. */
+	/* -------------------------------------------------------------------------- */
+
+	/* TODO: replace ddi_bc_hwChargerPowerIsOn with function below */
+	return ddi_power_GetChargerPowered();
+}
+
+
+/*  */
+/* brief Turn the charging hardware on or off. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function turns the charging hardware on or off. */
+/*  */
+/* param[in]  on  Indicates whether the charging hardware should be on or off. */
+/*  */
+
+void ddi_bc_hwSetChargerPower(int on)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */
+	/* stands for "power down". Thus, when the bit is set, the battery charger */
+	/* hardware is POWERED DOWN. */
+	/* -------------------------------------------------------------------------- */
+
+	/* -------------------------------------------------------------------------- */
+	/* Hit the power switch. */
+	/* -------------------------------------------------------------------------- */
+
+	/* TODO: replace ddi_bc_hwSetChargerPower with functino below */
+	ddi_power_SetChargerPowered(on);
+}
+
+
+/*  */
+/* brief Reports if the charging current has fallen below the threshold. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports if the charging current that the battery is accepting */
+/*  has fallen below the threshold. */
+/*  */
+/*  Note that this bit is regarded by the hardware guys as very slightly */
+/*  unreliable. They recommend that you don't believe a value of zero until */
+/*  you've sampled it twice. */
+/*  */
+/* retval  Zero if the battery is accepting less current than indicated by the */
+/*           charging threshold. Non-zero otherwise. */
+/*  */
+
+int ddi_bc_hwGetChargeStatus(void)
+{
+	return ddi_power_GetChargeStatus();
+}
+
+
+/*  */
+/* brief Report on the die temperature. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports on the die temperature. */
+/*  */
+/* param[out]  pLow   The low  end of the temperature range. */
+/* param[out]  pHigh  The high end of the temperature range. */
+/*  */
+
+void ddi_bc_hwGetDieTemp(int16_t *pLow, int16_t *pHigh)
+{
+	/* TODO: replace ddi_bc_hwGetDieTemp with function below */
+	ddi_power_GetDieTemp(pLow, pHigh);
+}
+
+
+/*  */
+/* brief Report the battery temperature reading. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function examines the configured LRADC channel and reports the battery */
+/*  temperature reading. */
+/*  */
+/* param[out]  pReading  A pointer to a variable that will receive the */
+/*                         temperature reading. */
+/*  */
+/* retval  DDI_BC_STATUS_SUCCESS          If the operation succeeded. */
+/* retval  DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                          initialized. */
+/*  */
+
+ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t *pReading)
+{
+	return (ddi_bc_Status_t)DDI_BC_STATUS_HARDWARE_DISABLED;
+}
+
+
+/*  */
+/* brief Convert a current in mA to a hardware setting. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function converts a current measurement in mA to a hardware setting */
+/*  used by HW_POWER_BATTCHRG.STOP_ILIMIT or HW_POWER_BATTCHRG.BATTCHRG_I. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 780mA (see the data sheet for details). If the given */
+/*  current cannot be expressed exactly, then the largest expressible smaller */
+/*  value will be used. */
+/*  */
+/* param[in]  u16Current  The current of interest. */
+/*  */
+/* retval  The corresponding setting. */
+/*  */
+
+uint8_t ddi_bc_hwCurrentToSetting(uint16_t u16Current)
+{
+	return ddi_power_convert_current_to_setting(u16Current);
+}
+
+
+/*  */
+/* brief Convert a hardware current setting to a value in mA. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function converts a setting used by HW_POWER_BATTCHRG.STOP_ILIMIT or */
+/*  HW_POWER_BATTCHRG.BATTCHRG_I into an actual current measurement in mA. */
+/*  */
+/*  Note that the hardware current fields are 6 bits wide. The higher bits in */
+/*  the 8-bit input parameter are ignored. */
+/*  */
+/* param[in]  u8Setting  A hardware current setting. */
+/*  */
+/* retval  The corresponding current in mA. */
+/*  */
+
+uint16_t ddi_bc_hwSettingToCurrent(uint8_t u8Setting)
+{
+	return ddi_power_convert_setting_to_current(u8Setting);
+}
+
+
+/*  */
+/* brief Compute the actual current expressible in the hardware. */
+/*  */
+/* fntype Function */
+/*  */
+/*  Given a desired current, this function computes the actual current */
+/*  expressible in the hardware. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 780mA (see the data sheet for details). If the given */
+/*  current cannot be expressed exactly, then the largest expressible smaller */
+/*  value will be used. */
+/*  */
+/* param[in]  u16Current  The current of interest. */
+/*  */
+/* retval  The corresponding current in mA. */
+/*  */
+
+uint16_t ddi_bc_hwExpressibleCurrent(uint16_t u16Current)
+{
+	/* TODO: replace the bc function with this one */
+	return ddi_power_ExpressibleCurrent(u16Current);
+}
+
+
+/*  */
+/* brief Checks to see if the DCDC has been manually enabled */
+/*  */
+/* fntype Function */
+/*  */
+/* retval  true if DCDC is ON, false if DCDC is OFF. */
+/*  */
+
+bool ddi_bc_hwIsDcdcOn(void)
+{
+	return ddi_power_IsDcdcOn();
+}
+
+
+/* End of file */
+
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_hw.h b/drivers/power/mxs/ddi_bc_hw.h
new file mode 100644
index 000000000000..9275c5b3a7ba
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_hw.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef _DDI_BC_HW_H
+#define _DDI_BC_HW_H
+
+
+/* Definitions */
+
+
+/*  The enumeration of battery modes. */
+
+typedef enum _ddi_bc_BatteryMode {
+	DDI_BC_BATTERY_MODE_LI_ION_2_CELLS = 0,
+	DDI_BC_BATTERY_MODE_LI_ION_1_CELL = 1,
+	DDI_BC_BATTERY_MODE_2_CELLS = 2,
+	DDI_BC_BATTERY_MODE_1_CELL = 3
+} ddi_bc_BatteryMode_t;
+
+/*  The enumeration of bias current sources. */
+
+typedef enum _ddi_bc_BiasCurrentSource {
+	DDI_BC_EXTERNAL_BIAS_CURRENT = 0,
+	DDI_BC_INTERNAL_BIAS_CURRENT = 1,
+} ddi_bc_BiasCurrentSource_t;
+
+
+/* Prototypes */
+
+
+extern int ddi_bc_hwBatteryChargerIsEnabled(void);
+extern ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void);
+extern ddi_bc_BiasCurrentSource_t ddi_bc_hwGetBiasCurrentSource(void);
+extern ddi_bc_Status_t
+ddi_bc_hwSetBiasCurrentSource(ddi_bc_BiasCurrentSource_t);
+extern ddi_bc_Status_t ddi_bc_hwSetChargingVoltage(uint16_t);
+extern uint16_t ddi_bc_hwGetBatteryVoltage(void);
+extern int ddi_bc_hwPowerSupplyIsPresent(void);
+extern uint16_t ddi_bc_hwSetMaxCurrent(uint16_t);
+extern uint16_t ddi_bc_hwGetMaxCurrent(void);
+extern uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t);
+extern uint16_t ddi_bc_hwGetCurrentThreshold(void);
+extern int ddi_bc_hwChargerPowerIsOn(void);
+extern void ddi_bc_hwSetChargerPower(int);
+extern int ddi_bc_hwGetChargeStatus(void);
+extern void ddi_bc_hwGetDieTemp(int16_t *, int16_t *);
+extern ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t *);
+uint8_t ddi_bc_hwCurrentToSetting(uint16_t);
+uint16_t ddi_bc_hwSettingToCurrent(uint8_t);
+uint16_t ddi_bc_hwExpressibleCurrent(uint16_t);
+
+
+/*  */
+/* brief Checks to see if the DCDC has been manually enabled */
+/*  */
+/* fntype Function */
+/*  */
+/* retval  true if DCDC is ON, false if DCDC is OFF. */
+/*  */
+
+bool ddi_bc_hwIsDcdcOn(void);
+
+
+/* End of file */
+
+#endif				/* _DDI_BC_H */
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_init.c b/drivers/power/mxs/ddi_bc_init.c
new file mode 100644
index 000000000000..c93f8969f92c
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_init.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ddi_bc_internal.h"
+
+
+/* addtogroup ddi_bc */
+/*  @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file       ddi_bc_init.c */
+/* brief      Contains the Battery Charger initialization function. */
+/* date       06/2005 */
+/*  */
+/*  This file contains Battery Charger initialization function. */
+/*  */
+
+
+
+/* Includes and external references */
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+
+/* Code */
+
+
+
+/* brief Initialize the Battery Charger. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function initializes the Battery Charger. */
+/*  */
+/* param[in]  pCfg  A pointer to the new configuration. */
+/*  */
+/* retval  DDI_BC_STATUS_SUCCESS */
+/*              If the operation succeeded. */
+/* retval  DDI_BC_STATUS_ALREADY_INITIALIZED */
+/*              If the Battery Charger is already initialized. */
+/* retval  DDI_BC_STATUS_HARDWARE_DISABLED */
+/*              If the Battery Charger hardware is disabled by a laser fuse. */
+/* retval  DDI_BC_STATUS_BAD_BATTERY_MODE */
+/*              If the power supply is set up for a non-rechargeable battery. */
+/* retval  DDI_BC_STATUS_CLOCK_GATE_CLOSED */
+/*              If the clock gate for the power supply registers is closed. */
+/* retval  DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE */
+/*              If the charging voltage is not either 4100 or 4200. */
+/* retval  DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL */
+/*              If the LRADC channel number for monitoring battery temperature */
+/*              is bad. */
+/*  */
+
+ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t *pCfg)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* We can only be initialized if we're in the Uninitialized state. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State != DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_ALREADY_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check if the battery charger hardware has been disabled by laser fuse. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_power_GetBatteryChargerEnabled())
+		return DDI_BC_STATUS_HARDWARE_DISABLED;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if the power supply has been set up for a non-rechargeable battery. */
+	/* -------------------------------------------------------------------------- */
+
+	switch (ddi_power_GetBatteryMode()) {
+
+	case DDI_POWER_BATT_MODE_LIION:
+		break;
+
+		/* TODO: we'll need to do NiMH also */
+	default:
+		return DDI_BC_STATUS_BAD_BATTERY_MODE;
+		/* break; */
+
+	}
+
+	/* -------------------------------------------------------------------------- */
+	/* Make sure that the clock gate has been opened for the power supply */
+	/* registers. If not, then none of our writes to those registers will */
+	/* succeed, which will kind of slow us down... */
+	/* -------------------------------------------------------------------------- */
+
+	if (ddi_power_GetPowerClkGate()) {
+		return DDI_BC_STATUS_CLOCK_GATE_CLOSED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check the incoming configuration for nonsense. */
+	/* -------------------------------------------------------------------------- */
+
+	/*  */
+	/* Only permitted charging voltage: 4200mV. */
+	/*  */
+
+	if (pCfg->u16ChargingVoltage != DDI_BC_LIION_CHARGING_VOLTAGE) {
+		return DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE;
+	}
+	/*  */
+	/* There are 8 LRADC channels. */
+	/*  */
+
+	if (pCfg->u8BatteryTempChannel > 7) {
+		return DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Accept the configuration. */
+	/* -------------------------------------------------------------------------- */
+
+	/* -------------------------------------------------------------------------- */
+	/*  ddi_bc_Cfg_t.u16ChargingThresholdCurrent is destined for the */
+	/*  register field HW_POWER_BATTCHRG.STOP_ILIMIT.  This 4-bit field */
+	/*  is unevenly quantized to provide a useful range of currents.  A */
+	/*  side effect of the quantization is that the field can only be */
+	/*  set to certain unevenly-spaced values. */
+	/*  */
+	/*  Here, we use the two functions that manipulate the register field */
+	/*  to adjust u16ChargingThresholdCurrent to match the quantized value. */
+	/* -------------------------------------------------------------------------- */
+	pCfg->u16ChargingThresholdCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16ChargingThresholdCurrent);
+
+	/* -------------------------------------------------------------------------- */
+	/*  ...similar situation with ddi_bc_Cfg_t.u16BatteryTempSafeCurrent and */
+	/*  u16DieTempSafeCurrent. */
+	/* -------------------------------------------------------------------------- */
+	pCfg->u16BatteryTempSafeCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16BatteryTempSafeCurrent);
+	pCfg->u16DieTempSafeCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16DieTempSafeCurrent);
+
+	g_ddi_bc_Configuration = *pCfg;
+
+	/* -------------------------------------------------------------------------- */
+	/* Turn the charger hardware off. This is a very important initial condition */
+	/* because we only flip the power switch on the hardware when we make */
+	/* transitions. Baseline, it needs to be off. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_power_SetChargerPowered(0);
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. This will jam the current to zero and power off */
+	/* the charging hardware. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Disabled state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("%s: success\n", __func__);
+#endif
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/* End of file */
+
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_internal.h b/drivers/power/mxs/ddi_bc_internal.h
new file mode 100644
index 000000000000..b5bceeffae98
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_internal.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_bc */
+/*  @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file ddi_bc_internal.h */
+/* brief Internal header file for the Battery Charger device driver. */
+/* date 06/2005 */
+/*  */
+/*  This file contains internal declarations for the Battery Charger device */
+/*  driver. */
+
+
+#ifndef _DDI_BC_INTERNAL_H
+#define _DDI_BC_INTERNAL_H
+
+
+/* Includes */
+
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_hw.h"
+#include "ddi_bc_ramp.h"
+#include "ddi_bc_sm.h"
+#include "ddi_power_battery.h"
+
+
+/* Externs */
+
+#include <linux/kernel.h>
+
+extern bool g_ddi_bc_Configured;
+extern ddi_bc_Cfg_t g_ddi_bc_Configuration;
+
+
+/* End of file */
+
+#endif				/* _DDI_BC_H */
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_ramp.c b/drivers/power/mxs/ddi_bc_ramp.c
new file mode 100644
index 000000000000..76efc0d5c32d
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_ramp.c
@@ -0,0 +1,724 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_bc */
+/*  @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file       ddi_bc_ramp.c */
+/* brief      Contains the Battery Charger current ramp controller. */
+/* date       06/2005 */
+/*  */
+/*  This file contains Battery Charger current ramp controller. */
+/*  */
+
+
+
+/* Includes and external references */
+
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+
+/* Definitions */
+
+
+/*  This is the control structure for the current ramp. */
+
+typedef struct _ddi_bc_RampControl {
+
+	uint32_t u32AccumulatedTime;
+
+	/* < The accumulated time since we last changed the actual */
+	/* < current setting in the hardware. If the time between */
+	/* < steps is quite short, we may have to wait for several steps */
+	/* < before we can actually change the hardware setting. */
+
+	uint16_t u16Target;
+
+	/* < The target current, regardless of expressibility. */
+
+	uint16_t u16Limit;
+
+	/* < The current limit, regardless of expressibility. */
+
+	uint8_t dieTempAlarm:1;
+
+	/* < Indicates if we are operating under a die temperature */
+	/* < alarm. */
+
+	uint8_t batteryTempAlarm:1;
+
+	/* < Indicates if we are operating under a battery temperature */
+	/* < alarm. */
+
+	uint8_t ambientTempAlarm:1;
+
+	/* < Indicates if we are operating under an ambient temperature */
+	/* < alarm. */
+
+} ddi_bc_RampControl_t;
+
+
+/* Variables */
+
+
+/*  This structure contains control information for the current ramp. */
+
+static ddi_bc_RampControl_t g_RampControl;
+
+
+/* Code */
+
+
+
+/*  */
+/* brief Reset the current ramp. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function resets the current ramp. */
+/*  */
+/*  Note that this function does NOT reset the temperature alarms or the current */
+/*  limit. Those can only be changed explicitly. */
+/*  */
+
+void ddi_bc_RampReset()
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the control structure. */
+	/* -------------------------------------------------------------------------- */
+
+	g_RampControl.u32AccumulatedTime = 0;
+	g_RampControl.u16Target = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Step the ramp. Note that we don't care if this function returns an error. */
+	/* We're stepping the ramp to make sure it takes immediate effect, if */
+	/* possible. But, for example, if the Battery Charger is not yet */
+	/* initialized, it doesn't matter. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(0);
+
+}
+
+
+/*  */
+/* brief Set the target current. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function sets the target current and implements it immediately. */
+/*  */
+/*  Note that this function does NOT reset the temperature alarms. Those can */
+/*  only be reset explicitly. */
+/*  */
+/* param[in]  u16Target  The target current. */
+/*  */
+/* retval  The expressible version of the target. */
+/*  */
+
+uint16_t ddi_bc_RampSetTarget(uint16_t u16Target)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Set the target. */
+	/* -------------------------------------------------------------------------- */
+
+	g_RampControl.u16Target = u16Target;
+
+	/* -------------------------------------------------------------------------- */
+	/* Step the ramp. Note that we don't care if this function returns an error. */
+	/* We're stepping the ramp to make sure it takes immediate effect, if */
+	/* possible. But, for example, if the Battery Charger is not yet */
+	/* initialized, it doesn't matter. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(0);
+
+	/* -------------------------------------------------------------------------- */
+	/* Compute and return the expressible target. */
+	/* -------------------------------------------------------------------------- */
+
+	return ddi_bc_hwExpressibleCurrent(u16Target);
+
+}
+
+
+/*  */
+/* brief Report the target. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the target. */
+/*  */
+/* retval  The target. */
+/*  */
+
+uint16_t ddi_bc_RampGetTarget(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Return the target. */
+	/* -------------------------------------------------------------------------- */
+
+	return g_RampControl.u16Target;
+
+}
+
+
+/*  */
+/* brief Set the current limit. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function sets the current limit and implements it immediately. */
+/*  */
+/* param[in]  u16Limit  The current limit. */
+/*  */
+/* retval  The expressible version of the limit. */
+/*  */
+
+uint16_t ddi_bc_RampSetLimit(uint16_t u16Limit)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Set the limit. */
+	/* -------------------------------------------------------------------------- */
+
+	g_RampControl.u16Limit = u16Limit;
+
+	/* -------------------------------------------------------------------------- */
+	/* Step the ramp. Note that we don't care if this function returns an error. */
+	/* We're stepping the ramp to make sure it takes immediate effect, if */
+	/* possible. But, for example, if the Battery Charger is not yet */
+	/* initialized, it doesn't matter. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(0);
+
+	/* -------------------------------------------------------------------------- */
+	/* Compute and return the expressible limit. */
+	/* -------------------------------------------------------------------------- */
+
+	return ddi_bc_hwExpressibleCurrent(u16Limit);
+
+}
+
+
+/*  */
+/* brief Report the current limit. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the current limit. */
+/*  */
+/* retval  The current limit. */
+/*  */
+
+uint16_t ddi_bc_RampGetLimit(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Return the current limit. */
+	/* -------------------------------------------------------------------------- */
+
+	return g_RampControl.u16Limit;
+
+}
+
+
+/*  */
+/* brief Update alarms. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function checks for all alarms and updates the current ramp */
+/*  accordingly. */
+/*  */
+
+void ddi_bc_RampUpdateAlarms()
+{
+
+	/* Set to true if something changed and we need to step the ramp right away. */
+
+	int iStepTheRamp = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Are we monitoring die temperature? */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_Configuration.monitorDieTemp) {
+
+		/* ---------------------------------------------------------------------- */
+		/* Get the die temperature range. */
+		/* ---------------------------------------------------------------------- */
+
+		int16_t i16Low;
+		int16_t i16High;
+
+		ddi_bc_hwGetDieTemp(&i16Low, &i16High);
+
+		/* ---------------------------------------------------------------------- */
+		/* Now we need to decide if it's time to raise or lower the alarm. The */
+		/* first question to ask is: Were we already under an alarm? */
+		/* ---------------------------------------------------------------------- */
+
+		if (g_RampControl.dieTempAlarm) {
+
+			/* ------------------------------------------------------------------ */
+			/* If control arrives here, we were already under an alarm. We'll */
+			/* change that if the high end of the temperature range drops below */
+			/* the low temperature mark. */
+			/* ------------------------------------------------------------------ */
+
+			if (i16High < g_ddi_bc_Configuration.u8DieTempLow) {
+
+				/* -------------------------------------------------------------- */
+				/* If control arrives here, we're safe now. Drop the alarm. */
+				/* -------------------------------------------------------------- */
+
+				g_RampControl.dieTempAlarm = 0;
+
+				iStepTheRamp = !0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				printk("Battery charger: releasing "
+				       "die temp alarm: [%d, %d] < %d\r\n",
+				       (int32_t) i16Low, (int32_t) i16High,
+				       (int32_t) g_ddi_bc_Configuration.
+				       u8DieTempLow);
+#endif
+
+			}
+
+		} else {
+
+			/* ------------------------------------------------------------------ */
+			/* If control arrives here, we were not under an alarm. We'll change */
+			/* that if the high end of the temperature range rises above the */
+			/* high temperature mark. */
+			/* ------------------------------------------------------------------ */
+
+			if (i16High >= g_ddi_bc_Configuration.u8DieTempHigh) {
+
+				/* -------------------------------------------------------------- */
+				/* If control arrives here, we're running too hot. Raise the */
+				/* alarm. */
+				/* -------------------------------------------------------------- */
+
+				g_RampControl.dieTempAlarm = 1;
+
+				iStepTheRamp = !0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				printk("Battery charger: declaring "
+				       "die temp alarm: [%d, %d] >= %d\r\n",
+				       (int32_t) i16Low, (int32_t) i16High,
+				       (int32_t) g_ddi_bc_Configuration.
+				       u8DieTempLow);
+#endif
+			}
+
+		}
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Are we monitoring battery temperature? */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_Configuration.monitorBatteryTemp) {
+
+		ddi_bc_Status_t status;
+
+		/* ---------------------------------------------------------------------- */
+		/* Get the battery temperature reading. */
+		/* ---------------------------------------------------------------------- */
+
+		uint16_t u16Reading;
+
+		status = ddi_bc_hwGetBatteryTemp(&u16Reading);
+
+		/* ---------------------------------------------------------------------- */
+		/* If there was a problem, then we ignore the reading. Otherwise, let's */
+		/* have a look. */
+		/* ---------------------------------------------------------------------- */
+
+		if (status == DDI_BC_STATUS_SUCCESS) {
+
+			/* ------------------------------------------------------------------ */
+			/* Now we need to decide if it's time to raise or lower the alarm. */
+			/* The first question to ask is: Were we already under an alarm? */
+			/* ------------------------------------------------------------------ */
+
+			if (g_RampControl.batteryTempAlarm) {
+
+				/* -------------------------------------------------------------- */
+				/* If control arrives here, we were already under an alarm. */
+				/* We'll change that if the reading drops below the low mark. */
+				/* -------------------------------------------------------------- */
+
+				if (u16Reading <
+				    g_ddi_bc_Configuration.u16BatteryTempLow) {
+
+					/* ---------------------------------------------------------- */
+					/* If control arrives here, we're safe now. Drop the alarm. */
+					/* ---------------------------------------------------------- */
+
+					g_RampControl.batteryTempAlarm = 0;
+
+					iStepTheRamp = !0;
+
+				}
+
+			} else {
+
+				/* -------------------------------------------------------------- */
+				/* If control arrives here, we were not under an alarm. We'll */
+				/* change that if the reading rises above the high mark. */
+				/* -------------------------------------------------------------- */
+
+				if (u16Reading >=
+				    g_ddi_bc_Configuration.u16BatteryTempHigh) {
+
+					/* ---------------------------------------------------------- */
+					/* If control arrives here, we're running too hot. Raise the */
+					/* alarm. */
+					/* ---------------------------------------------------------- */
+
+					g_RampControl.batteryTempAlarm = 1;
+
+					iStepTheRamp = !0;
+
+				}
+
+			}
+
+		}
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Do we need to step the ramp? */
+	/* -------------------------------------------------------------------------- */
+
+	if (iStepTheRamp)
+		ddi_bc_RampStep(0);
+
+}
+
+
+/*  */
+/* brief Reports the state of the die temperature alarm. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the state of the die temperature alarm. */
+/*  */
+/* retval  The state of the die temperature alarm. */
+/*  */
+
+int ddi_bc_RampGetDieTempAlarm(void)
+{
+	return g_RampControl.dieTempAlarm;
+}
+
+
+/*  */
+/* brief Reports the state of the battery temperature alarm. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the state of the battery temperature alarm. */
+/*  */
+/* retval  The state of the battery temperature alarm. */
+/*  */
+
+int ddi_bc_RampGetBatteryTempAlarm(void)
+{
+	return g_RampControl.batteryTempAlarm;
+}
+
+
+/*  */
+/* brief Reports the state of the ambient temperature alarm. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the state of the ambient temperature alarm. */
+/*  */
+/* retval  The state of the ambient temperature alarm. */
+/*  */
+
+int ddi_bc_RampGetAmbientTempAlarm(void)
+{
+	return g_RampControl.ambientTempAlarm;
+}
+
+
+/*  */
+/* brief Step the current ramp. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function steps the current ramp forward through the given amount of time. */
+/*  */
+/* param[in] u32Time  The time increment to add. */
+/*  */
+/* retval  DDI_BC_STATUS_SUCCESS          If the operation succeeded. */
+/* retval  DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet */
+/*                                          initialized. */
+/*  */
+
+ddi_bc_Status_t ddi_bc_RampStep(uint32_t u32Time)
+{
+
+	uint16_t u16MaxNow;
+	uint16_t u16Target;
+	uint16_t u16Cart;
+	int32_t i32Delta;
+
+	/* -------------------------------------------------------------------------- */
+	/* Make sure the Battery Charger is initialized. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return DDI_BC_STATUS_NOT_INITIALIZED;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Figure out how much current the hardware is set to draw right now. */
+	/* -------------------------------------------------------------------------- */
+
+	u16MaxNow = ddi_bc_hwGetMaxCurrent();
+
+	/* -------------------------------------------------------------------------- */
+	/* Start with the target. */
+	/* -------------------------------------------------------------------------- */
+
+	u16Target = g_RampControl.u16Target;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check the target against the hard limit. */
+	/* -------------------------------------------------------------------------- */
+
+	if (u16Target > g_RampControl.u16Limit)
+		u16Target = g_RampControl.u16Limit;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if the die temperature alarm is active. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_RampControl.dieTempAlarm) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we are under a die temperature alarm. Clamp */
+		/* the target current. */
+		/* ---------------------------------------------------------------------- */
+
+		if (u16Target > g_ddi_bc_Configuration.u16DieTempSafeCurrent) {
+			u16Target =
+			    g_ddi_bc_Configuration.u16DieTempSafeCurrent;
+		}
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check if the battery temperature alarm is active. */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_RampControl.batteryTempAlarm) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we are under a battery temperature alarm. */
+		/* Clamp the target current. */
+		/* ---------------------------------------------------------------------- */
+
+		if (u16Target >
+		    g_ddi_bc_Configuration.u16BatteryTempSafeCurrent) {
+			u16Target =
+			    g_ddi_bc_Configuration.u16BatteryTempSafeCurrent;
+		}
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Now we know the target current. Figure out what is actually expressible */
+	/* in the hardware. */
+	/* -------------------------------------------------------------------------- */
+
+	u16Target = ddi_bc_hwExpressibleCurrent(u16Target);
+
+	/* -------------------------------------------------------------------------- */
+	/* Compute the difference between the expressible target and what's actually */
+	/* set in the hardware right now. */
+	/* -------------------------------------------------------------------------- */
+
+	i32Delta = ((int32_t) u16Target) - ((int32_t) u16MaxNow);
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if the delta is zero. */
+	/* -------------------------------------------------------------------------- */
+
+	if (i32Delta == 0) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, there is no difference between what we want */
+		/* and what's set in the hardware. */
+		/*  */
+		/* Before we leave, though, we don't want to leave any accumulated time */
+		/* laying around for the next ramp up. Zero it out. */
+		/* ---------------------------------------------------------------------- */
+
+		g_RampControl.u32AccumulatedTime = 0;
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check if the delta is negative. */
+	/* -------------------------------------------------------------------------- */
+
+	if (i32Delta < 0) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the new target is lower than what's */
+		/* currently set in the hardware. Since that means we're *reducing* the */
+		/* current draw, we can do it right now. Just gimme a sec here... */
+		/* ---------------------------------------------------------------------- */
+
+		ddi_bc_hwSetMaxCurrent(u16Target);
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+		printk("Battery charger: setting max charge "
+		       "current to: %hdmA\r\n", u16Target);
+#endif
+
+		/* ---------------------------------------------------------------------- */
+		/* Flip the power switch on the charging hardware according to the new */
+		/* current setting. */
+		/* ---------------------------------------------------------------------- */
+
+		ddi_bc_hwSetChargerPower(u16Target != 0);
+
+		/* ---------------------------------------------------------------------- */
+		/* We don't want to leave any accumulated time laying around for the */
+		/* next ramp up. Zero it out. */
+		/* ---------------------------------------------------------------------- */
+
+		g_RampControl.u32AccumulatedTime = 0;
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, the target current is higher than what's set in */
+	/* the hardware right now. That means we're going to ramp it up. To do that, */
+	/* we're going to "buy" more milliamps by "spending" milliseconds of time. */
+	/* Add the time we've "banked" to the time we've been credited in this call. */
+	/* -------------------------------------------------------------------------- */
+
+	u32Time += g_RampControl.u32AccumulatedTime;
+
+	/* -------------------------------------------------------------------------- */
+	/* Now we know how much we can spend. How much current will it buy? */
+	/* -------------------------------------------------------------------------- */
+
+	u16Cart = (g_ddi_bc_Configuration.u16CurrentRampSlope * u32Time) / 1000;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check how the current we can afford stacks up against the target we want. */
+	/* -------------------------------------------------------------------------- */
+
+	if ((u16MaxNow + u16Cart) < u16Target) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we can't afford to buy all the current we */
+		/* want. Compute the maximum we can afford, and then figure out what we */
+		/* can actually express in the hardware. */
+		/* ---------------------------------------------------------------------- */
+
+		u16Target = ddi_bc_hwExpressibleCurrent(u16MaxNow + u16Cart);
+
+		/* ---------------------------------------------------------------------- */
+		/* Check if the result isn't actually different from what's set in the */
+		/* the hardware right now. */
+		/* ---------------------------------------------------------------------- */
+
+		if (u16Target == u16MaxNow) {
+
+			/* ------------------------------------------------------------------ */
+			/* If control arrives here, we are so poor that we can't yet afford */
+			/* to buy enough current to make a change in the expressible */
+			/* hardware setting. Since we didn't spend any of our time, put the */
+			/* new balance back in the bank. */
+			/* ------------------------------------------------------------------ */
+
+			g_RampControl.u32AccumulatedTime = u32Time;
+
+			/* ------------------------------------------------------------------ */
+			/* Leave dispiritedly. */
+			/* ------------------------------------------------------------------ */
+
+			return DDI_BC_STATUS_SUCCESS;
+
+		}
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we can afford to buy enough current to get us */
+	/* all the way to the target. Set it. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_hwSetMaxCurrent(u16Target);
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: setting max charge"
+	       "current to: %hdmA\r\n", u16Target);
+#endif
+
+	/* -------------------------------------------------------------------------- */
+	/* Flip the power switch on the charging hardware according to the new */
+	/* current setting. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_hwSetChargerPower(u16Target != 0);
+
+	/* -------------------------------------------------------------------------- */
+	/* We're at the target, so we're finished buying current. Zero out the */
+	/* account. */
+	/* -------------------------------------------------------------------------- */
+
+	g_RampControl.u32AccumulatedTime = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/* End of file */
+
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_ramp.h b/drivers/power/mxs/ddi_bc_ramp.h
new file mode 100644
index 000000000000..b43db8147f52
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_ramp.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_bc */
+/* ! @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file ddi_bc_ramp.h */
+/* brief Internal header file for Battery Charger current ramp controller. */
+/* date 06/2005 */
+/* ! */
+/* ! This file contains internal declarations for Battery current ramp */
+/* ! controller. */
+
+
+#ifndef _DDI_BC_RAMP_H
+#define _DDI_BC_RAMP_H
+
+
+/* Prototypes */
+
+
+extern void ddi_bc_RampReset(void);
+extern uint16_t ddi_bc_RampSetTarget(uint16_t);
+extern uint16_t ddi_bc_RampGetTarget(void);
+extern uint16_t ddi_bc_RampSetLimit(uint16_t);
+extern uint16_t ddi_bc_RampGetLimit(void);
+extern void ddi_bc_RampUpdateAlarms(void);
+extern int ddi_bc_RampGetDieTempAlarm(void);
+extern int ddi_bc_RampGetBatteryTempAlarm(void);
+extern int ddi_bc_RampGetAmbientTempAlarm(void);
+extern ddi_bc_Status_t ddi_bc_RampStep(uint32_t);
+
+
+/* End of file */
+
+#endif				/* _DDI_BC_H */
+/* ! @} */
diff --git a/drivers/power/mxs/ddi_bc_sm.c b/drivers/power/mxs/ddi_bc_sm.c
new file mode 100644
index 000000000000..6626ed82c192
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_sm.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_bc */
+/*  @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file       ddi_bc_sm.c */
+/* brief      Contains the Battery Charger state machine. */
+
+
+
+/* Includes */
+
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+#include <linux/delay.h>
+
+
+/* Definitions */
+
+
+/* This is the minimum time we must charge before we transition from */
+/* the charging state to the topping off. If we reach the */
+/* u16ChargingThresholdCurrent charge curent before then, the battery was */
+/* already full so we can avoid the risk of charging it past .1C for */
+/* too long. */
+
+#define TRANSITION_TO_TOPOFF_MINIMUM_CHARGE_TIME_mS (1 * 60 * 1000)	/* 1 minute */
+
+
+/* Variables */
+
+
+/* The current state. */
+
+ddi_bc_State_t g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED;
+
+/* This table contains pointers to the functions that implement states. The */
+/* table is indexed by state. Note that it's critically important for this */
+/* table to agree with the state enumeration in ddi_bc.h. */
+
+static ddi_bc_Status_t ddi_bc_Uninitialized(void);
+static ddi_bc_Status_t ddi_bc_Broken(void);
+static ddi_bc_Status_t ddi_bc_Disabled(void);
+static ddi_bc_Status_t ddi_bc_WaitingToCharge(void);
+static ddi_bc_Status_t ddi_bc_Conditioning(void);
+static ddi_bc_Status_t ddi_bc_Charging(void);
+static ddi_bc_Status_t ddi_bc_ToppingOff(void);
+
+
+ddi_bc_Status_t(*const (stateFunctionTable[])) (void) = {
+ddi_bc_Uninitialized,
+	    ddi_bc_Broken,
+	    ddi_bc_Disabled,
+	    ddi_bc_WaitingToCharge,
+	    ddi_bc_Conditioning,
+	    ddi_bc_Charging, ddi_bc_ToppingOff};
+
+/* Used by states that need to watch the time. */
+uint32_t g_ddi_bc_u32StateTimer;
+
+/* Always attempt to charge on first 5V connection */
+bool bRestartChargeCycle = true;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+static uint16_t u16ExternalBatteryPowerVoltageCheck;
+#endif
+
+ddi_bc_BrokenReason_t ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED;
+
+
+/* Code */
+
+
+
+/*  */
+/* brief Transition to the Waiting to Charge state. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the transition to the Waiting to Charge state. */
+/*  */
+
+static void TransitionToWaitingToCharge(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Waiting to Charge state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now waiting to charge\n");
+#endif
+
+}
+
+
+/*  */
+/* brief Transition to the Conditioning state. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the transition to the Conditioning state. */
+/*  */
+
+static void TransitionToConditioning(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Set up the current ramp for conditioning. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ConditioningCurrent);
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Conditioning state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_CONDITIONING;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now conditioning\n");
+#endif
+
+}
+
+
+/*  */
+/* brief Transition to the Charging state. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the transition to the Charging state. */
+/*  */
+
+static void TransitionToCharging(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Set up the current ramp for charging. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent);
+
+	/* -------------------------------------------------------------------------- */
+	/* We'll be finished charging when the current flow drops below this level. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration.
+				     u16ChargingThresholdCurrent);
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Charging state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_CHARGING;
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now charging\n");
+#endif
+}
+
+
+/*  */
+/* brief Transition to the Topping Off state. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the transition to the Topping Off state. */
+/*  */
+
+static void TransitionToToppingOff(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Set up the current ramp for topping off. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent);
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Topping Off state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_TOPPING_OFF;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now topping off\n");
+#endif
+
+}
+
+
+/*  */
+/* brief Transition to the Broken state. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the transition to the Broken state. */
+/*  */
+
+static void TransitionToBroken(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	/* -------------------------------------------------------------------------- */
+	/* Reset the current ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampReset();
+
+	/* -------------------------------------------------------------------------- */
+	/* Move to the Broken state. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_State = DDI_BC_STATE_BROKEN;
+
+	pr_info("charger------ ddi_bc_gBrokenReason=%d\n",
+		ddi_bc_gBrokenReason);
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: declaring a broken battery\n");
+#endif
+
+}
+
+
+/*  */
+/* brief Uninitialized state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Uninitialized state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_Uninitialized(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* Increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	/* -------------------------------------------------------------------------- */
+	/* The only way to leave this state is with a call to ddi_bc_Initialize. So, */
+	/* calling this state function does nothing. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Broken state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Broken state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_Broken(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* Increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	/* -------------------------------------------------------------------------- */
+	/* The only way to leave this state is with a call to ddi_bc_SetFixed. So, */
+	/* calling this state function does nothing. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Disabled state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Disabled state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_Disabled(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* Increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	/* -------------------------------------------------------------------------- */
+	/* The only way to leave this state is with a call to ddi_bc_SetEnable. So, */
+	/* calling this state function does nothing. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Waitin to Charge state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Waiting to Charge state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_WaitingToCharge(void)
+{
+	uint16_t u16BatteryVoltage;
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* Increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if the power supply is present. If not, we're not going anywhere. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+		u16ExternalBatteryPowerVoltageCheck = 0;
+#endif
+		return DDI_BC_STATUS_SUCCESS;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're connected to a power supply. Have a look */
+	/* at the battery voltage. */
+	/* -------------------------------------------------------------------------- */
+
+	u16BatteryVoltage = ddi_bc_hwGetBatteryVoltage();
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	if (u16ExternalBatteryPowerVoltageCheck) {
+		if ((u16ExternalBatteryPowerVoltageCheck - u16BatteryVoltage) >
+		    300) {
+			/*
+			 * If control arrives here, battery voltage has
+			 * dropped too quickly after the first charge
+			 * cycle.  We think an external voltage regulator is
+			 * connected.
+			 */
+
+			ddi_bc_gBrokenReason =
+			    DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED;
+
+			TransitionToBroken();
+
+			/* ---------------------------------------------------------------------- */
+			/* Tell our caller the battery appears to be broken. */
+			/* ---------------------------------------------------------------------- */
+
+			return DDI_BC_STATUS_BROKEN;
+		} else {
+			/* reset this check */
+			u16ExternalBatteryPowerVoltageCheck = 0;
+		}
+
+	}
+#endif
+
+
+	/* -------------------------------------------------------------------------- */
+	/* If the battery voltage isn't low, we don't need to be charging it. We */
+	/* use a 5% margin to decide. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!bRestartChargeCycle) {
+		uint16_t x;
+
+		x = u16BatteryVoltage + (u16BatteryVoltage / 20);
+
+		if (x >= g_ddi_bc_Configuration.u16ChargingVoltage)
+			return DDI_BC_STATUS_SUCCESS;
+
+	}
+
+	bRestartChargeCycle = false;
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, the battery is low. How low? */
+	/* -------------------------------------------------------------------------- */
+
+	if (u16BatteryVoltage <
+	    g_ddi_bc_Configuration.u16ConditioningThresholdVoltage) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the battery is very low and it needs to be */
+		/* conditioned. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToConditioning();
+
+	} else {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the battery isn't too terribly low. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToCharging();
+
+	}
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Conditioning state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Conditioning state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_Conditioning(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* If we're not under an alarm, increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) {
+		g_ddi_bc_u32StateTimer +=
+		    g_ddi_bc_Configuration.u32StateMachinePeriod;
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Check if the power supply is still around. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the power supply has been removed. Go back */
+		/* and wait. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToWaitingToCharge();
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're still connected to a power supply. */
+	/* Check if a battery is connected.  If the voltage rises to high with only */
+	/* conditioning charge current, we determine that a battery is not connected. */
+	/* If that is not the case and a battery is connected, check */
+	/* if the battery voltage indicates it still needs conditioning. */
+	/* -------------------------------------------------------------------------- */
+
+/* 	if (ddi_bc_hwGetBatteryVoltage() >= 3900) { */
+	if ((ddi_bc_hwGetBatteryVoltage() >
+	     g_ddi_bc_Configuration.u16ConditioningMaxVoltage) &&
+	    (ddi_power_GetMaxBatteryChargeCurrent() <
+	     g_ddi_bc_Configuration.u16ConditioningCurrent)) {
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, voltage has risen too quickly for so */
+		/* little charge being applied so their must be no battery connected. */
+		/* ---------------------------------------------------------------------- */
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_NO_BATTERY_DETECTED;
+
+		TransitionToBroken();
+
+		/* ---------------------------------------------------------------------- */
+		/* Tell our caller the battery appears to be broken. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_BROKEN;
+
+	}
+
+	if (ddi_bc_hwGetBatteryVoltage() >=
+	    g_ddi_bc_Configuration.u16ConditioningMaxVoltage) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, this battery no longer needs conditioning. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToCharging();
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* Have we been in this state too long? */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_u32StateTimer >=
+	    g_ddi_bc_Configuration.u32ConditioningTimeout) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we've been here too long. */
+		/* ---------------------------------------------------------------------- */
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+		TransitionToBroken();
+
+		/* ---------------------------------------------------------------------- */
+		/* Tell our caller the battery appears to be broken. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_BROKEN;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're staying in this state. Step the current */
+	/* ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Charging state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Charging state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_Charging(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* This variable counts the number of times we've seen the charging status */
+	/* bit cleared. */
+	/* -------------------------------------------------------------------------- */
+
+	static int iStatusCount;
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* If we're not under an alarm, increment the state timer. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) {
+		g_ddi_bc_u32StateTimer +=
+		    g_ddi_bc_Configuration.u32StateMachinePeriod;
+	}
+	/* Check if the power supply is still around. */
+
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the power supply has been removed. Go back */
+		/* and wait. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToWaitingToCharge();
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're still connected to a power supply. We need */
+	/* to decide now if the battery is still charging, or if it's nearly full. */
+	/* If it's still charging, we'll stay in this state. Otherwise, we'll move */
+	/* to the Topping Off state. */
+	/*  */
+	/* Most of the time, we decide that the battery is still charging simply by */
+	/* checking if the the actual current flow is above the charging threshold */
+	/* current (as indicated by the charge status bit). However, if we're */
+	/* still ramping up to full charging current, the hardware may still be set */
+	/* to deliver an amount that's less than the threshold. In that case, the */
+	/* charging status bit would *definitely* show a low charging current, but */
+	/* that doesn't mean the battery is ready for topping off. */
+	/*  */
+	/* So, in summary, we will move to the Topping Off state if both of the */
+	/* following are true: */
+	/*  */
+	/*  1) The maximum current set in the hardware is greater than the charging */
+	/*     threshold. */
+	/*  -AND- */
+	/*  2) The actual current flow is also higher than the threshold (as */
+	/*     indicated by the charge status bit). */
+	/*  */
+	/* -------------------------------------------------------------------------- */
+
+
+
+		ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration.
+					     u16ChargingThresholdCurrent);
+
+
+	{
+		uint16_t u16ActualProgrammedCurrent = ddi_bc_hwGetMaxCurrent();
+
+		/* ---------------------------------------------------------------------- */
+		/* Get the Maximum current that we will ramp to. */
+		/* ---------------------------------------------------------------------- */
+
+		/* ---------------------------------------------------------------------- */
+		/* Not all possible values are expressible by the BATTCHRG_I bitfield. */
+		/* The following coverts the max current value into the the closest hardware */
+		/* expressible bitmask equivalent.  Then, it converts this back to the actual */
+		/* decimal current value that this bitmask represents. */
+		/* ---------------------------------------------------------------------- */
+
+		uint16_t u16CurrentRampTarget = ddi_bc_RampGetTarget();
+
+		if (u16CurrentRampTarget > ddi_bc_RampGetLimit())
+			u16CurrentRampTarget = ddi_bc_RampGetLimit();
+
+		/* ---------------------------------------------------------------------- */
+		/* Not all possible values are expressible by the BATTCHRG_I bitfield. */
+		/* The following coverts the max current value into the the closest hardware */
+		/* expressible bitmask equivalent.  Then, it converts this back to the actual */
+		/* decimal current value that this bitmask represents. */
+		/* ---------------------------------------------------------------------- */
+
+		u16CurrentRampTarget =
+		    ddi_bc_hwExpressibleCurrent(u16CurrentRampTarget);
+
+		/* ---------------------------------------------------------------------- */
+		/* We want to wait before we check the charge status bit until the ramping */
+		/* up is complete.  Because the charge status bit is noisy, we want to */
+		/* disregard it until the programmed charge currint in BATTCHRG_I is well */
+		/* beyond the STOP_ILIMIT value. */
+		/* ---------------------------------------------------------------------- */
+		if ((u16ActualProgrammedCurrent >= u16CurrentRampTarget) &&
+		    !ddi_bc_hwGetChargeStatus()) {
+			uint8_t u8IlimitThresholdLimit;
+			/* ---------------------------------------------------------------------- */
+			/* If control arrives here, the hardware flag is telling us that the */
+			/* charging current has fallen below the threshold. We need to see this */
+			/* happen twice consecutively before we believe it. Increment the count. */
+			/* ---------------------------------------------------------------------- */
+
+			iStatusCount++;
+
+
+			u8IlimitThresholdLimit = 10;
+
+			/* ---------------------------------------------------------------------- */
+			/* How many times in a row have we seen this status bit low? */
+			/* ---------------------------------------------------------------------- */
+
+			if (iStatusCount >= u8IlimitThresholdLimit) {
+
+				/*
+				 * If control arrives here, we've seen the
+				 * CHRGSTS bit low too many times. This means
+				 * it's time to move to the Topping Off state.
+				 * First, reset the status count for the next
+				 * time we're in this state.
+				 */
+
+				iStatusCount = 0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				u16ExternalBatteryPowerVoltageCheck =
+				    ddi_bc_hwGetBatteryVoltage();
+#endif
+
+
+
+				/* Move to the Topping Off state */
+
+
+				TransitionToToppingOff();
+
+				/* ------------------------------------------------------------------ */
+				/* Return success. */
+				/* ------------------------------------------------------------------ */
+
+				return DDI_BC_STATUS_SUCCESS;
+
+			}
+
+		} else {
+
+			/* ---------------------------------------------------------------------- */
+			/* If control arrives here, the battery is still charging. Clear the */
+			/* status count. */
+			/* ---------------------------------------------------------------------- */
+
+			iStatusCount = 0;
+
+		}
+
+	}
+
+	/* -------------------------------------------------------------------------- */
+	/* Have we been in this state too long? */
+	/* -------------------------------------------------------------------------- */
+
+	if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32ChargingTimeout) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we've been here too long. */
+		/* ---------------------------------------------------------------------- */
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+		TransitionToBroken();
+
+		/* ---------------------------------------------------------------------- */
+		/* Tell our caller the battery appears to be broken. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_BROKEN;
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're staying in this state. Step the current */
+	/* ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/*  */
+/* brief Topping Off state function. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function implements the Topping Off state. */
+/*  */
+
+static ddi_bc_Status_t ddi_bc_ToppingOff(void)
+{
+
+	/* -------------------------------------------------------------------------- */
+	/* The first order of business is to update alarms. */
+
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampUpdateAlarms();
+
+	/* -------------------------------------------------------------------------- */
+	/* Increment the state timer. Notice that, unlike other states, we increment */
+	/* the state timer whether or not we're under an alarm. */
+	/* -------------------------------------------------------------------------- */
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	/* -------------------------------------------------------------------------- */
+	/* Check if the power supply is still around. */
+	/* -------------------------------------------------------------------------- */
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, the power supply has been removed. Go back */
+		/* and wait. */
+		/* --------------------------------------------------------------------- */
+
+		TransitionToWaitingToCharge();
+
+		/* ---------------------------------------------------------------------- */
+		/* Return success. */
+		/* ---------------------------------------------------------------------- */
+
+		return DDI_BC_STATUS_SUCCESS;
+
+	}
+
+	/* -------------------------------------------------------------------------- */
+	/* Are we done topping off? */
+	/* -------------------------------------------------------------------------- */
+	if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32TopOffPeriod) {
+
+		/* ---------------------------------------------------------------------- */
+		/* If control arrives here, we're done topping off. */
+		/* ---------------------------------------------------------------------- */
+
+		TransitionToWaitingToCharge();
+
+	}
+	/* -------------------------------------------------------------------------- */
+	/* If control arrives here, we're staying in this state. Step the current */
+	/* ramp. */
+	/* -------------------------------------------------------------------------- */
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	/* -------------------------------------------------------------------------- */
+	/* Return success. */
+	/* -------------------------------------------------------------------------- */
+
+	return DDI_BC_STATUS_SUCCESS;
+
+}
+
+
+/* End of file */
+
+/*  @} */
diff --git a/drivers/power/mxs/ddi_bc_sm.h b/drivers/power/mxs/ddi_bc_sm.h
new file mode 100644
index 000000000000..40bd4a494fb3
--- /dev/null
+++ b/drivers/power/mxs/ddi_bc_sm.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_bc */
+/*  @{ */
+/*  */
+/* Copyright (c) 2004-2005 SigmaTel, Inc. */
+/*  */
+/* file ddi_bc_sm.h */
+/* brief Header file for the Battery Charger state machine. */
+/* date 06/2005 */
+/*  */
+/*  This file contains declarations for the Battery Charger state machine. */
+
+
+#ifndef _DDI_BC_SM_H
+#define _DDI_BC_SM_H
+
+
+/* Externs */
+
+
+/*  The current state. */
+
+extern ddi_bc_State_t g_ddi_bc_State;
+
+/*  The state function table. */
+
+extern ddi_bc_Status_t(*const (stateFunctionTable[])) (void);
+
+
+/* End of file */
+
+#endif				/* _DDI_BC_H */
+/*  @} */
diff --git a/drivers/power/mxs/ddi_power_battery.c b/drivers/power/mxs/ddi_power_battery.c
new file mode 100644
index 000000000000..762f29bd784e
--- /dev/null
+++ b/drivers/power/mxs/ddi_power_battery.c
@@ -0,0 +1,1908 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+/* addtogroup ddi_power */
+/*  @{ */
+/*  */
+/* Copyright(C) 2005 SigmaTel, Inc. */
+/*  */
+/* file ddi_power_battery.c */
+/* brief Implementation file for the power driver battery charger. */
+/*  */
+
+/*   Includes and external references */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/processor.h> /* cpu_relax */
+#include <mach/hardware.h>
+#include <mach/ddi_bc.h>
+#include <mach/lradc.h>
+#include <mach/regs-power.h>
+#include <mach/regs-lradc.h>
+#include <mach/lradc.h>
+#include "ddi_bc_internal.h"
+
+/* brief Base voltage to start battery calculations for LiIon */
+#define BATT_BRWNOUT_LIION_BASE_MV 2800
+/* brief Constant to help with determining whether to round up or */
+/*  not during calculation */
+#define BATT_BRWNOUT_LIION_CEILING_OFFSET_MV 39
+/* brief Number of mV to add if rounding up in LiIon mode */
+#define BATT_BRWNOUT_LIION_LEVEL_STEP_MV 40
+/* brief Constant value to be calculated by preprocessing */
+#define BATT_BRWNOUT_LIION_EQN_CONST \
+	(BATT_BRWNOUT_LIION_BASE_MV - BATT_BRWNOUT_LIION_CEILING_OFFSET_MV)
+/* brief Base voltage to start battery calculations for Alkaline/NiMH */
+#define BATT_BRWNOUT_ALKAL_BASE_MV 800
+/* brief Constant to help with determining whether to round up or */
+/*  not during calculation */
+#define BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV 19
+/* brief Number of mV to add if rounding up in Alkaline/NiMH mode */
+#define BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV 20
+/* brief Constant value to be calculated by preprocessing */
+#define BATT_BRWNOUT_ALKAL_EQN_CONST \
+	(BATT_BRWNOUT_ALKAL_BASE_MV - BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV)
+
+#define GAIN_CORRECTION 1012    /* 1.012 */
+
+#define VBUSVALID_THRESH_2_90V		0x0
+#define VBUSVALID_THRESH_4_00V		0x1
+#define VBUSVALID_THRESH_4_10V		0x2
+#define VBUSVALID_THRESH_4_20V		0x3
+#define VBUSVALID_THRESH_4_30V		0x4
+#define VBUSVALID_THRESH_4_40V		0x5
+#define VBUSVALID_THRESH_4_50V		0x6
+#define VBUSVALID_THRESH_4_60V		0x7
+
+#define LINREG_OFFSET_STEP_BELOW	0x2
+#define BP_POWER_BATTMONITOR_BATT_VAL	16
+#define BP_POWER_CHARGE_BATTCHRG_I	0
+#define BP_POWER_CHARGE_STOP_ILIMIT	8
+
+#define VDD4P2_ENABLED
+
+#define DDI_POWER_BATTERY_XFER_THRESHOLD_MV 3200
+
+
+#ifndef BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV
+#define BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV 4000
+#endif
+
+#ifndef BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV
+#define BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV 3800
+#endif
+
+/* #define DEBUG_IRQS */
+
+/* to be re-enabled once FIQ functionality is added */
+#define DISABLE_VDDIO_BO_PROTECTION
+
+#ifdef CONFIG_ARCH_MX28
+#define BM_POWER_STS_VBUSVALID BM_POWER_STS_VBUSVALID0
+#endif
+
+/* Globals & Variables */
+
+
+
+/* Select your 5V Detection method */
+
+static ddi_power_5vDetection_t DetectionMethod =
+			DDI_POWER_5V_VDD5V_GT_VDDIO;
+/* static ddi_power_5vDetection_t DetectionMethod = DDI_POWER_5V_VBUSVALID; */
+
+
+/* Code */
+
+
+#if 0
+static void dump_regs(void)
+{
+	printk("HW_POWER_CHARGE      0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE));
+	printk("HW_POWER_STS         0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_STS));
+	printk("HW_POWER_BATTMONITOR 0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR));
+}
+#endif
+
+/*  This array maps bit numbers to current increments, as used in the register */
+/*  fields HW_POWER_CHARGE.STOP_ILIMIT and HW_POWER_CHARGE.BATTCHRG_I. */
+static const uint16_t currentPerBit[] = {  10,  20,  50, 100, 200, 400 };
+
+uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current)
+{
+	int       i;
+	uint16_t  u16Mask;
+	uint16_t  u16Setting = 0;
+
+	/* Scan across the bit field, adding in current increments. */
+	u16Mask = (0x1 << 5);
+
+	for (i = 5; (i >= 0) && (u16Current > 0); i--, u16Mask >>= 1) {
+		if (u16Current >= currentPerBit[i]) {
+			u16Current -= currentPerBit[i];
+			u16Setting |= u16Mask;
+		}
+	}
+
+	/* Return the result. */
+	return u16Setting;
+}
+
+
+/*  See hw_power.h for details. */
+
+uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting)
+{
+	int       i;
+	uint16_t  u16Mask;
+	uint16_t  u16Current = 0;
+
+	/* Scan across the bit field, adding in current increments. */
+	u16Mask = (0x1 << 5);
+
+	for (i = 5; i >= 0; i--, u16Mask >>= 1) {
+		if (u16Setting & u16Mask)
+			u16Current += currentPerBit[i];
+	}
+
+	/* Return the result. */
+	return u16Current;
+}
+
+void ddi_power_Enable5vDetection(void)
+{
+	u32 val;
+	/* Disable hardware power down when 5V is inserted or removed */
+	__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	/* Enabling VBUSVALID hardware detection even if VDD5V_GT_VDDIO
+	 * is the detection method being used for 5V status (hardware
+	 * or software).  This is in case any other drivers (such as
+	 * USB) are specifically monitoring VBUSVALID status
+	 */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	/* Set 5V detection threshold to 4.3V for VBUSVALID. */
+	__raw_writel(
+		BF_POWER_5VCTRL_VBUSVALID_TRSH(VBUSVALID_THRESH_4_30V),
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	/* gotta set LINREG_OFFSET to STEP_BELOW according to manual */
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+	val &= ~(BM_POWER_VDDIOCTRL_LINREG_OFFSET);
+	val |= BF_POWER_VDDIOCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL);
+	val &= ~(BM_POWER_VDDACTRL_LINREG_OFFSET);
+	val |= BF_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDACTRL);
+
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+	val &= ~(BM_POWER_VDDDCTRL_LINREG_OFFSET);
+	val |= BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	/* enable vbusvalid irq */
+
+
+	/* enable 5V Detection interrupt vbusvalid irq */
+	switch (DetectionMethod) {
+	case DDI_POWER_5V_VBUSVALID:
+		/* Check VBUSVALID for 5V present */
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+		break;
+	case DDI_POWER_5V_VDD5V_GT_VDDIO:
+		/* Check VDD5V_GT_VDDIO for 5V present */
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+		break;
+	}
+}
+
+/*
+ * This function prepares the hardware for a 5V-to-battery handoff. It assumes
+ * the current configuration is using 5V as the power source.  The 5V
+ * interrupt will be set up for a 5V removal.
+ */
+void ddi_power_enable_5v_to_battery_handoff(void)
+{
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* detect 5v unplug */
+	__raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+#ifndef VDD4P2_ENABLED
+	/* Enable automatic transition to DCDC */
+	__raw_writel(BM_POWER_5VCTRL_DCDC_XFER,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+}
+
+/*
+ * This function will handle all the power rail transitions necesarry to power
+ * the chip from the battery when it was previously powered from the 5V power
+ * source.
+ */
+void ddi_power_execute_5v_to_battery_handoff(void)
+{
+	int val;
+#ifdef VDD4P2_ENABLED
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	val &= ~(BM_POWER_DCDC4P2_ENABLE_DCDC | BM_POWER_DCDC4P2_ENABLE_4P2);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	/* make VBUSVALID_TRSH 4400mV and set PWD_CHARGE_4P2 */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	__raw_writel(BF_POWER_5VCTRL_VBUSVALID_TRSH(VBUSVALID_THRESH_4_40V),
+		REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+#else
+	/* VDDD has different configurations depending on the battery type */
+	/* and battery level. */
+
+	/* For LiIon battery, we will use the DCDC to power VDDD. */
+	/* Use LinReg offset for DCDC mode. */
+	__raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_SET);
+	/* Turn on the VDDD DCDC output and turn off the VDDD LinReg output. */
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+
+	__raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+	/* Make sure stepping is enabled when using DCDC. */
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+
+	/* Power VDDA and VDDIO from the DCDC. */
+
+	/* Use LinReg offset for DCDC mode. */
+	__raw_writel(BF_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+	/* Turn on the VDDA DCDC converter output and turn off LinReg output. */
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+	__raw_writel(BM_POWER_VDDACTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	/* Make sure stepping is enabled when using DCDC. */
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	/* Use LinReg offset for DCDC mode. */
+	__raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET(
+					LINREG_OFFSET_STEP_BELOW
+						),
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+
+	/* Turn on the VDDIO DCDC output and turn on the LinReg output.*/
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+				HW_POWER_BASE + HW_POWER_5VCTRL_CLR_CLR);
+
+	/* Make sure stepping is enabled when using DCDC. */
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+#endif
+
+}
+
+/*
+ * This function sets up battery-to-5V handoff. The power switch from
+ * battery to 5V is automatic. This funtion enables the 5V present detection
+ * such that the 5V interrupt can be generated if it is enabled. (The interrupt
+ * handler can inform software the 5V present event.) To deal with noise or
+ * a high current, this function enables DCDC1/2 based on the battery mode.
+ */
+void ddi_power_enable_battery_to_5v_handoff(void)
+{
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* detect 5v plug-in */
+	__raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+#ifndef VDD4P2_ENABLED
+	/* Force current from 5V to be zero by disabling its entry source. */
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+	/* Allow DCDC be to active when 5V is present. */
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+}
+
+/* This function handles the transitions on each of theVDD5V_GT_VDDIO power
+ * rails necessary to power the chip from the 5V power supply when it was
+ * previously powered from the battery power supply.
+ */
+void ddi_power_execute_battery_to_5v_handoff(void)
+{
+
+#ifdef VDD4P2_ENABLED
+	ddi_power_Enable4p2(450);
+#else
+	/* Disable the DCDC during 5V connections. */
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC,
+				HW_POWER_BAE + HW_POWER_5VCTRL_CLR);
+
+	/* Power the VDDD/VDDA/VDDIO rail from the linear regulator.  The DCDC */
+	/* is ready to automatically power the chip when 5V is removed. */
+	/* Use this configuration when powering from 5V */
+
+	/* Use LinReg offset for LinReg mode */
+	__raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+
+	/* Turn on the VDDD LinReg and turn on the VDDD DCDC output.  The */
+	/* ENABLE_DCDC must be cleared to avoid LinReg and DCDC conflict. */
+	__raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_CLR);
+
+	/* Make sure stepping is disabled when using linear regulators */
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+
+	/* Use LinReg offset for LinReg mode */
+	__raw_writel(BM_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BAE + HW_POWER_VDDACTRL_SET);
+
+
+	/* Turn on the VDDA LinReg output and prepare the DCDC for transfer. */
+	/* ENABLE_DCDC must be clear to avoid DCDC and LinReg conflict. */
+	stmp3xxx_set(BM_POWER_VDDACTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	/* Make sure stepping is disabled when using linear regulators */
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING,
+				 HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+
+	/* Use LinReg offset for LinReg mode. */
+	__raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET(
+					LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+
+	/* Turn on the VDDIO LinReg output and prepare the VDDIO DCDC output. */
+	/* ENABLE_DCDC must be cleared to prevent DCDC and LinReg conflict. */
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	/* Make sure stepping is disabled when using DCDC. */
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING,
+			REGS_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+#endif
+}
+
+
+void ddi_power_Start4p2Dcdc(bool battery_ready)
+{
+	uint32_t temp_reg, old_values;
+	bool vdda_pwdn = false, vddd_pwdn = false, vddio_pwdn = false;
+
+#ifndef CONFIG_ARCH_MX28
+	/* set vbusvalid threshold to 2.9V because of errata */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+#endif
+
+#if 0
+	if (battery_ready)
+		ddi_power_EnableBatteryIrq();
+	else
+		enable_4p2_fiq_shutdown();
+#endif
+
+	/* enable hardware shutdown on battery brownout */
+	__raw_writel(
+			BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT |
+			__raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR),
+			REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+
+	/* set VBUS DROOP threshold to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	/* turn of vbus valid detection.  Part of errate
+	 * workaround. */
+	__raw_writel(BM_POWER_5VCTRL_PWRUP_VBUS_CMPS,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)
+		& BM_POWER_VDDIOCTRL_PWDN_BRNOUT)
+		vddio_pwdn = true;
+
+	if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL)
+		& BM_POWER_VDDDCTRL_PWDN_BRNOUT)
+		vddd_pwdn = true;
+
+	if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL)
+		& BM_POWER_VDDACTRL_PWDN_BRNOUT)
+		vdda_pwdn = true;
+
+	__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL)
+	& (~BM_POWER_VDDACTRL_PWDN_BRNOUT),
+	REGS_POWER_BASE + HW_POWER_VDDACTRL);
+
+	__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL)
+	& (~BM_POWER_VDDDCTRL_PWDN_BRNOUT),
+	REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+	__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)
+	& (~BM_POWER_VDDIOCTRL_PWDN_BRNOUT),
+	REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+
+	if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS)
+		& BM_POWER_STS_VDDIO_BO) == 0)
+		__raw_writel(BM_POWER_CTRL_VDDIO_BO_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS)
+		& BM_POWER_STS_VDDD_BO) == 0)
+		__raw_writel(BM_POWER_CTRL_VDDD_BO_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS)
+		& BM_POWER_STS_VDDA_BO) == 0)
+		__raw_writel(BM_POWER_CTRL_VDDA_BO_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	temp_reg = (BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO |
+		BM_POWER_CTRL_ENIRQ_VDD5V_DROOP |
+		BM_POWER_CTRL_ENIRQ_VBUS_VALID);
+
+	/* save off old brownout enable values */
+	old_values = __raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+		temp_reg;
+
+	/* disable irqs affected by errata */
+	__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* Enable DCDC from 4P2 */
+	__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) |
+			BM_POWER_DCDC4P2_ENABLE_DCDC,
+			REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	/* give a delay to check for errate noise problem */
+	mdelay(1);
+
+	temp_reg = (BM_POWER_CTRL_VDDD_BO_IRQ |
+		BM_POWER_CTRL_VDDA_BO_IRQ |
+		BM_POWER_CTRL_VDDIO_BO_IRQ |
+		BM_POWER_CTRL_VDD5V_DROOP_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ);
+
+	__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	/* stay in this loop until the false brownout indciations
+	 * no longer occur or until 5V actually goes away
+	 */
+	while ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & temp_reg) &&
+		!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ)) {
+		__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+		mdelay(1);
+	}
+	/* revert to previous enable irq values */
+	__raw_writel(old_values, REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+	if (vdda_pwdn)
+		__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL)
+		| BM_POWER_VDDACTRL_PWDN_BRNOUT,
+		REGS_POWER_BASE + HW_POWER_VDDACTRL);
+
+	if (vddd_pwdn)
+		__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL)
+		| BM_POWER_VDDDCTRL_PWDN_BRNOUT,
+		REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+	if (vddio_pwdn)
+		__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)
+		| BM_POWER_VDDIOCTRL_PWDN_BRNOUT,
+		REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+
+	if (DetectionMethod == DDI_POWER_5V_VBUSVALID)
+		__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+}
+
+
+/* set the optimal CMPTRIP for the best possible 5V
+ * disconnection handling but without drawing power
+ * from the power on a stable 4p2 rails (at 4.2V).
+ */
+void ddi_power_handle_cmptrip(void)
+{
+	enum ddi_power_5v_status pmu_5v_status;
+	uint32_t temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	temp &= ~(BM_POWER_DCDC4P2_CMPTRIP);
+
+	pmu_5v_status = ddi_power_GetPmu5vStatus();
+
+	/* CMPTRIP should remain at 31 when 5v is disconnected
+	 * or 5v is connected but hasn't been handled yet
+	 */
+	if (pmu_5v_status != existing_5v_connection)
+		temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+	else if (ddi_power_GetBattery() >
+			BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV)
+		temp |= (1 << BP_POWER_DCDC4P2_CMPTRIP);
+	else if (ddi_power_GetBattery() >
+			BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV)
+		temp |= (24 << BP_POWER_DCDC4P2_CMPTRIP);
+	else
+		temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+
+
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+}
+
+void ddi_power_Init4p2Params(void)
+{
+	uint32_t temp;
+
+	ddi_power_handle_cmptrip();
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	/* DROPOUT CTRL to 10, TRG to 0 */
+	temp &= ~(BM_POWER_DCDC4P2_TRG | BM_POWER_DCDC4P2_DROPOUT_CTRL);
+	temp |= (0xa << BP_POWER_DCDC4P2_DROPOUT_CTRL);
+
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL);
+
+	/* HEADROOM_ADJ to 4, CHARGE_4P2_ILIMIT to 0 */
+	temp &= ~(BM_POWER_5VCTRL_HEADROOM_ADJ |
+			BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
+	temp |= (4 << BP_POWER_5VCTRL_HEADROOM_ADJ);
+
+}
+
+bool ddi_power_IsBattRdyForXfer(void)
+{
+	uint16_t u16BatteryVoltage = ddi_power_GetBattery();
+
+	if (u16BatteryVoltage > DDI_POWER_BATTERY_XFER_THRESHOLD_MV)
+		return true;
+	else
+		return false;
+}
+
+void ddi_power_EnableVbusDroopIrq(void)
+{
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+}
+
+
+void ddi_power_Enable4p2(uint16_t target_current_limit_ma)
+{
+
+	uint16_t u16BatteryVoltage;
+	uint32_t temp_reg;
+
+	ddi_power_Init4p2Params();
+	/* disable 4p2 rail brownouts for now. (they
+	 * should have already been off at this point) */
+	__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	u16BatteryVoltage = ddi_power_GetBattery();
+
+	if (ddi_power_IsBattRdyForXfer()) {
+
+		/* PWD_CHARGE_4P2 should already be set but just in case... */
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+		/* set CMPTRIP to DCDC_4P2 pin >= BATTERY pin */
+		temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+		temp_reg &= ~(BM_POWER_DCDC4P2_CMPTRIP);
+		temp_reg |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+		__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+		/* since we have a good battery, we can go ahead
+		 * and turn on the Dcdcing from the 4p2 source.
+		 * This is helpful in working around the chip
+		 * errata.
+		 */
+		ddi_power_Start4p2Dcdc(true);
+
+		/* Enable VbusDroopIrq to handle errata */
+
+		/* set vbus droop detection level to 4.3V */
+		__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+		ddi_power_EnableVbusDroopIrq();
+		/* now that the DCDC4P2 problems are cleared,
+		 * turn on and ramp up the 4p2 regulator
+		 */
+		temp_reg = ddi_power_BringUp4p2Regulator(
+			target_current_limit_ma, true);
+
+		/* if we still have our 5V connection, we can disable
+		 * battery brownout interrupt.  This is because the
+		 * VDD5V DROOP IRQ handler will also shutdown if battery
+		 * is browned out and it will enable the battery brownout
+		 * and bring VBUSVALID_TRSH level back to a normal level
+		 * which caused the hardware battery brownout shutdown
+		 * to be enabled.  The benefit of this is that device
+		 * that have detachable batteries (or devices going through
+		 * the assembly line and running this firmware to test
+		 *  with) can avoid shutting down if 5V is present and
+		 *  battery voltage goes away.
+		 */
+		if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+			(BM_POWER_CTRL_VBUSVALID_IRQ |
+			BM_POWER_CTRL_VDD5V_DROOP_IRQ))) {
+			ddi_power_EnableBatteryBoInterrupt(false);
+		}
+
+
+
+		printk(KERN_DEBUG "4P2 rail started.  5V current limit\
+			set to %dmA\n",	temp_reg);
+
+	} else {
+
+		printk(KERN_ERR "4P2 rail was attempted to be started \
+			from a system\
+			with a very low battery voltage.  This is not\
+			yet handled by the kernel driver, only by the\
+			bootlets.  Remaining on battery power.\n");
+
+		if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &&
+					BM_POWER_5VCTRL_ENABLE_DCDC))
+			ddi_power_EnableBatteryBoInterrupt(true);
+
+#if 0
+		/* enable hardware shutdown (if 5v disconnected)
+		 * on battery brownout */
+		__raw_writel(
+			BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT |
+			__raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR),
+			REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+
+		/* turn on and ramp up the 4p2 regulator */
+		temp_reg = ddi_power_BringUp4p2Regulator(
+			target_current_limit_ma, false);
+
+		Configure4p2FiqShutdown();
+
+		SetVbusValidThresh(0);
+#endif
+	}
+
+}
+
+/* enable and ramp up 4p2 regulator */
+uint16_t ddi_power_BringUp4p2Regulator(
+		uint16_t target_current_limit_ma,
+		bool b4p2_dcdc_enabled)
+{
+	uint32_t temp_reg;
+	uint16_t charge_4p2_ilimit = 0;
+
+	/* initial current limit to 0 */
+	__raw_writel(BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	__raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) |
+		BM_POWER_DCDC4P2_ENABLE_4P2,
+		REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	/* set 4p2 target voltage to zero */
+	temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	temp_reg &= (~BM_POWER_DCDC4P2_TRG);
+	__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	/* Enable 4P2 regulator*/
+	__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	if (target_current_limit_ma > 780)
+		target_current_limit_ma = 780;
+
+	ddi_power_Set4p2BoLevel(4150);
+
+	/* possibly not necessary but recommended for unloaded
+	 * 4p2 rail
+	 */
+	__raw_writel(BM_POWER_CHARGE_ENABLE_LOAD,
+		REGS_POWER_BASE + HW_POWER_CHARGE_SET);
+
+	while (charge_4p2_ilimit < target_current_limit_ma) {
+
+		if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+			(BM_POWER_CTRL_VBUSVALID_IRQ |
+			BM_POWER_CTRL_VDD5V_DROOP_IRQ))
+			break;
+
+
+		charge_4p2_ilimit += 100;
+		if (charge_4p2_ilimit > target_current_limit_ma)
+			charge_4p2_ilimit = target_current_limit_ma;
+
+		ddi_power_set_4p2_ilimit(charge_4p2_ilimit);
+
+		/* dcdc4p2 enable_dcdc must be enabled for
+		 * 4p2 bo indication to function.  If not enabled,
+		 * skip using bo level detection
+		 */
+		if (!(b4p2_dcdc_enabled))
+			msleep(1);
+		else if	(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+			BM_POWER_STS_DCDC_4P2_BO)
+			msleep(1);
+		else {
+			charge_4p2_ilimit = target_current_limit_ma;
+			ddi_power_set_4p2_ilimit(charge_4p2_ilimit);
+		}
+	}
+
+	ddi_power_Set4p2BoLevel(3600);
+
+	__raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* rail should now be up and loaded.  Extra
+	 * internal load is not necessary.
+	 */
+	__raw_writel(BM_POWER_CHARGE_ENABLE_LOAD,
+		REGS_POWER_BASE + HW_POWER_CHARGE_CLR);
+
+	return charge_4p2_ilimit;
+
+}
+
+
+void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv)
+{
+	uint16_t bo_reg_value;
+	uint32_t temp;
+
+	if (bo_voltage_mv < 3600)
+		bo_voltage_mv = 3600;
+	else if (bo_voltage_mv > 4375)
+		bo_voltage_mv = 4375;
+
+	bo_reg_value = (bo_voltage_mv - 3600) / 25;
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	temp &= (~BM_POWER_DCDC4P2_BO);
+	temp |= (bo_reg_value << BP_POWER_DCDC4P2_BO);
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+}
+
+
+
+void ddi_power_init_handoff(void)
+{
+	int val;
+	/* The following settings give optimal power supply capability */
+
+	/* enable 5v presence detection */
+	ddi_power_Enable5vDetection();
+
+	if (ddi_power_Get5vPresentFlag())
+		/* It's 5V mode, enable 5V-to-battery handoff */
+		ddi_power_enable_5v_to_battery_handoff();
+	else
+		/* It's battery mode, enable battery-to-5V handoff */
+		ddi_power_enable_battery_to_5v_handoff();
+
+	/* Finally enable the battery adjust */
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	val |= BM_POWER_BATTMONITOR_EN_BATADJ;
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+}
+
+
+void ddi_power_EnableBatteryInterrupt(bool enable)
+{
+
+	__raw_writel(BM_POWER_CTRL_BATT_BO_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+}
+
+
+#define REGS_LRADC_BASE IO_ADDRESS(LRADC_PHYS_ADDR)
+
+int ddi_power_init_battery(void)
+{
+
+	int ret = 0;
+
+	if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &&
+			BM_POWER_5VCTRL_ENABLE_DCDC)) {
+		printk(KERN_ERR "WARNING: Power Supply not\
+			initialized correctly by \
+			pre-kernel bootlets. HW_POWER_5VCTRL \
+			ENABLE_DCDC should already be set.  Kernel \
+			power driver behavior may not be reliable \n");
+		ret = 1;
+	}
+	if ((__raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR) &
+		BM_POWER_BATTMONITOR_BATT_VAL) == 0) {
+		ret = 1;
+		printk(KERN_INFO "WARNING : No battery connected !\r\n");
+		return ret;
+	}
+
+	/* the following code to enable automatic battery measurement
+	 * should have already been enabled in the boot prep files.  Not
+	 * sure if this is necessary or possibly susceptible to
+	 * mis-coordination
+	 */
+
+
+	ret = !hw_lradc_present(BATTERY_VOLTAGE_CH);
+
+	if (ret) {
+		printk(KERN_ERR "%s: hw_lradc_present failed\n", __func__);
+		return -ENODEV;
+	} else {
+		uint16_t wait_time = 0;
+
+		hw_lradc_configure_channel(BATTERY_VOLTAGE_CH, 0 /* div2 */ ,
+					   0 /* acc */ ,
+					   0 /* num_samples */);
+
+		/* Setup the trigger loop forever */
+		hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_BATTERY,
+			1 << BATTERY_VOLTAGE_CH,
+			1 << LRADC_DELAY_TRIGGER_BATTERY,
+			0, 200);
+
+		/* Clear the accumulator & NUM_SAMPLES */
+		__raw_writel(0xFFFFFFFF,
+			REGS_LRADC_BASE + HW_LRADC_CHn_CLR(BATTERY_VOLTAGE_CH));
+
+		/* clear previous "measurement performed" status */
+		__raw_writel(1 << BATTERY_VOLTAGE_CH,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+		/* set to LiIon scale factor */
+		__raw_writel(BM_LRADC_CONVERSION_SCALE_FACTOR,
+			REGS_LRADC_BASE + HW_LRADC_CONVERSION_SET);
+
+		/* kick off the trigger */
+		hw_lradc_set_delay_trigger_kick(
+				LRADC_DELAY_TRIGGER_BATTERY, 1);
+
+
+		/* wait for 1st converstion to be complete before
+		 * enabling automatic copy to power supply
+		 * peripheral
+		 */
+		while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1) &
+			1 << BATTERY_VOLTAGE_CH) &&
+				(wait_time < 10)) {
+			wait_time++;
+			mdelay(1);
+		}
+
+		__raw_writel(BM_LRADC_CONVERSION_AUTOMATIC,
+			REGS_LRADC_BASE + HW_LRADC_CONVERSION_SET);
+#ifdef CONFIG_ARCH_MX28
+		/* workaround for mx28 lradc result incorrect in the
+		first several ms */
+		for (wait_time = 0; wait_time < 20; wait_time++)
+			if (ddi_bc_hwGetBatteryVoltage() < 1000) {
+				pr_info("ddi_bc_hwGetBatteryVoltage=%u\n",
+				ddi_bc_hwGetBatteryVoltage());
+				mdelay(100);
+			} else
+				break;
+#endif
+	}
+
+#ifndef VDD4P2_ENABLED
+	/* prepare handoff */
+	ddi_power_init_handoff();
+#endif
+	return ret;
+}
+
+/*
+ * Use the the lradc channel
+ * get the die temperature from on-chip sensor.
+ */
+uint16_t MeasureInternalDieTemperature(void)
+{
+	uint32_t  ch8Value, ch9Value, lradc_irq_mask, channel;
+
+	channel = g_ddi_bc_Configuration.u8BatteryTempChannel;
+	lradc_irq_mask = 1 << channel;
+
+	/* power up internal tep sensor block */
+	__raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD,
+			REGS_LRADC_BASE + HW_LRADC_CTRL2_CLR);
+
+	/* mux to the lradc 8th temp channel */
+	__raw_writel((0xF << (4 * channel)),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR);
+	__raw_writel((8 << (4 * channel)),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_SET);
+
+	/* Clear the interrupt flag */
+	__raw_writel(lradc_irq_mask,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << channel),
+			REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+
+	/* Wait for conversion complete*/
+	while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1)
+			& lradc_irq_mask))
+		cpu_relax();
+
+	/* Clear the interrupt flag again */
+	__raw_writel(lradc_irq_mask,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+	/* read temperature value and clr lradc */
+	ch8Value = __raw_readl(REGS_LRADC_BASE +
+			HW_LRADC_CHn(channel)) & BM_LRADC_CHn_VALUE;
+
+
+	__raw_writel(BM_LRADC_CHn_VALUE,
+			REGS_LRADC_BASE + HW_LRADC_CHn_CLR(channel));
+
+	/* mux to the lradc 9th temp channel */
+	__raw_writel((0xF << (4 * channel)),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR);
+	__raw_writel((9 << (4 * channel)),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_SET);
+
+	/* Clear the interrupt flag */
+	__raw_writel(lradc_irq_mask,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << channel),
+			REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	/* Wait for conversion complete */
+	while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1)
+			& lradc_irq_mask))
+		cpu_relax();
+
+	/* Clear the interrupt flag */
+	__raw_writel(lradc_irq_mask,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	/* read temperature value */
+	ch9Value = __raw_readl(
+			REGS_LRADC_BASE + HW_LRADC_CHn(channel))
+		  & BM_LRADC_CHn_VALUE;
+
+
+	__raw_writel(BM_LRADC_CHn_VALUE,
+			REGS_LRADC_BASE + HW_LRADC_CHn_CLR(channel));
+
+	/* power down temp sensor block */
+	__raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD,
+			REGS_LRADC_BASE + HW_LRADC_CTRL2_SET);
+
+
+	return (uint16_t)((ch9Value-ch8Value)*GAIN_CORRECTION/4000);
+}
+
+
+
+/*  Name: ddi_power_GetBatteryMode */
+/*  */
+/* brief */
+
+ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void)
+{
+	return DDI_POWER_BATT_MODE_LIION;
+}
+
+
+/*  Name: ddi_power_GetBatteryChargerEnabled */
+/*  */
+/* brief */
+
+bool ddi_power_GetBatteryChargerEnabled(void)
+{
+#if 0
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_BATT_CHRG_PRESENT) ? 1 : 0;
+#endif
+	return 1;
+}
+
+
+/*  */
+/* brief Report if the charger hardware power is on. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports if the charger hardware power is on. */
+/*  */
+/* retval  Zero if the charger hardware is not powered. Non-zero otherwise. */
+/*  */
+/*  Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */
+/*  stands for "power down". Thus, when the bit is set, the battery charger */
+/*  hardware is POWERED DOWN. */
+
+bool ddi_power_GetChargerPowered(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_PWD_BATTCHRG) ? 0 : 1;
+}
+
+
+/*  */
+/* brief Turn the charging hardware on or off. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function turns the charging hardware on or off. */
+/*  */
+/* param[in]  on  Indicates whether the charging hardware should be on or off. */
+/*  */
+/*  Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */
+/*  stands for "power down". Thus, when the bit is set, the battery charger */
+/*  hardware is POWERED DOWN. */
+
+void ddi_power_SetChargerPowered(bool bPowerOn)
+{
+	/* Hit the battery charge power switch. */
+	if (bPowerOn) {
+		__raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG,
+			REGS_POWER_BASE + HW_POWER_CHARGE_CLR);
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+	} else {
+		__raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG,
+			REGS_POWER_BASE + HW_POWER_CHARGE_SET);
+#ifndef VDD4P2_ENABLED
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+	}
+
+/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */
+#if 0
+	printk("Battery charger: charger %s\n", bPowerOn ? "ON!" : "OFF");
+	dump_regs();
+#endif
+}
+
+
+/*  */
+/* brief Reports if the charging current has fallen below the threshold. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports if the charging current that the battery is accepting */
+/*  has fallen below the threshold. */
+/*  */
+/*  Note that this bit is regarded by the hardware guys as very slightly */
+/*  unreliable. They recommend that you don't believe a value of zero until */
+/*  you've sampled it twice. */
+/*  */
+/* retval  Zero if the battery is accepting less current than indicated by the */
+/*           charging threshold. Non-zero otherwise. */
+/*  */
+
+int ddi_power_GetChargeStatus(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_CHRGSTS) ? 1 : 0;
+}
+
+
+/* Battery Voltage */
+
+
+
+/*  */
+/* brief Report the voltage across the battery. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the voltage across the battery. Should return a */
+/*  value in range ~3000 - 4200 mV. */
+/*  */
+/* retval The voltage across the battery, in mV. */
+/*  */
+
+
+/* brief Constant value for 8mV steps used in battery translation */
+#define BATT_VOLTAGE_8_MV 8
+
+uint16_t ddi_power_GetBattery(void)
+{
+	uint32_t    u16BattVolt;
+
+	/* Get the raw result of battery measurement */
+	u16BattVolt = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	u16BattVolt &= BM_POWER_BATTMONITOR_BATT_VAL;
+	u16BattVolt >>= BP_POWER_BATTMONITOR_BATT_VAL;
+
+	/* Adjust for 8-mV LSB resolution and return */
+	u16BattVolt *= BATT_VOLTAGE_8_MV;
+
+/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */
+#if 0
+	printk("Battery charger: %u mV\n", u16BattVolt);
+#endif
+
+	return u16BattVolt;
+}
+
+#if 0
+
+/*  */
+/* brief Report the voltage across the battery. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports the voltage across the battery. */
+/*  */
+/* retval The voltage across the battery, in mV. */
+/*  */
+
+uint16_t ddi_power_GetBatteryBrownout(void)
+{
+	uint32_t    u16BatteryBrownoutLevel;
+
+	/* Get battery brownout level */
+	u16BatteryBrownoutLevel = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	u16BatteryBrownoutLevel &= BM_POWER_BATTMONITOR_BRWNOUT_LVL;
+	u16BatteryBrownoutLevel >>= BP_POWER_BATTMONITOR_BRWNOUT_LVL;
+
+	/* Calculate battery brownout level */
+	switch (ddi_power_GetBatteryMode()) {
+	case DDI_POWER_BATT_MODE_LIION:
+		u16BatteryBrownoutLevel *= BATT_BRWNOUT_LIION_LEVEL_STEP_MV;
+		u16BatteryBrownoutLevel += BATT_BRWNOUT_LIION_BASE_MV;
+		break;
+	case DDI_POWER_BATT_MODE_ALKALINE_NIMH:
+		u16BatteryBrownoutLevel *= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV;
+		u16BatteryBrownoutLevel += BATT_BRWNOUT_ALKAL_BASE_MV;
+		break;
+	default:
+		u16BatteryBrownoutLevel = 0;
+		break;
+	}
+	return u16BatteryBrownoutLevel;
+}
+
+
+/*  */
+/* brief Set battery brownout level */
+/*  */
+/* fntype     Reentrant Function */
+/*  */
+/*  This function sets the battery brownout level in millivolt. It transforms the */
+/*  input brownout value from millivolts to the hardware register bit field value */
+/*  taking the ceiling value in the calculation. */
+/*  */
+/* param[in]  u16BattBrownout_mV      Battery battery brownout level in mV */
+/*  */
+/* return     SUCCESS */
+/*  */
+
+int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV)
+{
+	int16_t i16BrownoutLevel;
+	int ret = 0;
+
+	/* Calculate battery brownout level */
+	switch (ddi_power_GetBatteryMode()) {
+	case DDI_POWER_BATT_MODE_LIION:
+		i16BrownoutLevel  = u16BattBrownout_mV -
+			BATT_BRWNOUT_LIION_EQN_CONST;
+		i16BrownoutLevel /= BATT_BRWNOUT_LIION_LEVEL_STEP_MV;
+		break;
+	case DDI_POWER_BATT_MODE_ALKALINE_NIMH:
+		i16BrownoutLevel  = u16BattBrownout_mV -
+			BATT_BRWNOUT_ALKAL_EQN_CONST;
+		i16BrownoutLevel /= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Do a check to make sure nothing went wrong. */
+	if (i16BrownoutLevel <= 0x0f) {
+		/* Write the battery brownout level */
+		__raw_writel(
+			BF_POWER_BATTMONITOR_BRWNOUT_LVL(i16BrownoutLevel),
+				REGS_POWER_BASE + HW_POWER_BATTMONITOR_SET);
+	} else
+		ret = -EINVAL;
+
+	return ret;
+}
+#endif
+
+
+/* Currents */
+
+
+
+
+/*  Name: ddi_power_SetMaxBatteryChargeCurrent */
+/*  */
+/* brief */
+
+uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur)
+{
+	uint32_t   u16OldSetting;
+	uint32_t   u16NewSetting;
+	uint32_t   u16ToggleMask;
+
+	/* Get the old setting. */
+	u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >>
+		BP_POWER_CHARGE_BATTCHRG_I;
+
+	/* Convert the new threshold into a setting. */
+	u16NewSetting = ddi_power_convert_current_to_setting(u16MaxCur);
+
+	/* Compute the toggle mask. */
+	u16ToggleMask = u16OldSetting ^ u16NewSetting;
+
+	/* Write to the toggle register.*/
+	__raw_writel(u16ToggleMask << BP_POWER_CHARGE_BATTCHRG_I,
+			REGS_POWER_BASE + HW_POWER_CHARGE_TOG);
+
+	/* Tell the caller what current we're set at now. */
+	return ddi_power_convert_setting_to_current(u16NewSetting);
+}
+
+
+/*  Name: ddi_power_GetMaxBatteryChargeCurrent */
+/*  */
+/* brief */
+
+uint16_t ddi_power_GetMaxBatteryChargeCurrent(void)
+{
+	uint32_t u8Bits;
+
+	/* Get the raw data from register */
+	u8Bits = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >>
+		BP_POWER_CHARGE_BATTCHRG_I;
+
+	/* Translate raw data to current (in mA) and return it */
+	return ddi_power_convert_setting_to_current(u8Bits);
+}
+
+
+/*  Name: ddi_power_GetMaxChargeCurrent */
+/*  */
+/* brief */
+
+uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh)
+{
+	uint32_t   u16OldSetting;
+	uint32_t   u16NewSetting;
+	uint32_t   u16ToggleMask;
+
+	/* ------------------------------------------------------------------- */
+	/* See ddi_power_SetMaxBatteryChargeCurrent for an explanation of */
+	/* why we're using the toggle register here. */
+	/*  */
+	/* Since this function doesn't have any major hardware effect, */
+	/* we could use the usual macros for writing to this bit field. But, */
+	/* for the sake of parallel construction and any potentially odd */
+	/* effects on the status bit, we use the toggle register in the same */
+	/* way as ddi_bc_hwSetMaxCurrent. */
+	/* ------------------------------------------------------------------- */
+
+	/* ------------------------------------------------------------------- */
+	/* The threshold hardware can't express as large a range as the max */
+	/* current setting, but we can use the same functions as long as we */
+	/* add an extra check here. */
+	/*  */
+	/* Thresholds larger than 180mA can't be expressed. */
+	/* ------------------------------------------------------------------- */
+
+	if (u16Thresh > 180)
+		u16Thresh = 180;
+
+
+	/* Create the mask */
+
+
+	/* Get the old setting. */
+	u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >>
+		BP_POWER_CHARGE_STOP_ILIMIT;
+
+	/* Convert the new threshold into a setting. */
+	u16NewSetting = ddi_power_convert_current_to_setting(u16Thresh);
+
+	/* Compute the toggle mask. */
+	u16ToggleMask = u16OldSetting ^ u16NewSetting;
+
+
+	/* Write to the register */
+
+
+	/* Write to the toggle register. */
+	__raw_writel(BF_POWER_CHARGE_STOP_ILIMIT(u16ToggleMask),
+			REGS_POWER_BASE + HW_POWER_CHARGE_TOG);
+
+	/* Tell the caller what current we're set at now. */
+	return ddi_power_convert_setting_to_current(u16NewSetting);
+}
+
+
+/*  Name: ddi_power_GetBatteryChargeCurrentThreshold */
+/*  */
+/* brief */
+
+uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void)
+{
+	uint32_t u16Threshold;
+
+	u16Threshold = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >>
+		BP_POWER_CHARGE_STOP_ILIMIT;
+
+	return ddi_power_convert_setting_to_current(u16Threshold);
+}
+
+
+/* Conversion */
+
+
+
+/*  */
+/* brief Compute the actual current expressible in the hardware. */
+/*  */
+/* fntype Function */
+/*  */
+/*  Given a desired current, this function computes the actual current */
+/*  expressible in the hardware. */
+/*  */
+/*  Note that the hardware has a minimum resolution of 10mA and a maximum */
+/*  expressible value of 780mA (see the data sheet for details). If the given */
+/*  current cannot be expressed exactly, then the largest expressible smaller */
+/*  value will be used. */
+/*  */
+/* param[in]  u16Current  The current of interest. */
+/*  */
+/* retval  The corresponding current in mA. */
+/*  */
+
+uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current)
+{
+	return ddi_power_convert_setting_to_current(
+		ddi_power_convert_current_to_setting(u16Current));
+}
+
+
+/*  Name: ddi_power_Get5VPresent */
+/*  */
+/* brief */
+
+
+bool ddi_power_Get5vPresentFlag(void)
+{
+	switch (DetectionMethod) {
+	case DDI_POWER_5V_VBUSVALID:
+		/* Check VBUSVALID for 5V present */
+		return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+			BM_POWER_STS_VBUSVALID) != 0);
+	case DDI_POWER_5V_VDD5V_GT_VDDIO:
+		/* Check VDD5V_GT_VDDIO for 5V present */
+		return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+			BM_POWER_STS_VDD5V_GT_VDDIO) != 0);
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+
+
+
+/*  */
+/* brief Report on the die temperature. */
+/*  */
+/* fntype Function */
+/*  */
+/*  This function reports on the die temperature. */
+/*  */
+/* param[out]  pLow   The low  end of the temperature range. */
+/* param[out]  pHigh  The high end of the temperature range. */
+/*  */
+
+/* Temperature constant */
+#define TEMP_READING_ERROR_MARGIN 5
+#define KELVIN_TO_CELSIUS_CONST 273
+
+void ddi_power_GetDieTemp(int16_t *pLow, int16_t *pHigh)
+{
+	int16_t i16High, i16Low;
+	uint16_t u16Reading;
+
+	/* Get the reading in Kelvins */
+	u16Reading = MeasureInternalDieTemperature();
+
+	/* Adjust for error margin */
+	i16High = u16Reading + TEMP_READING_ERROR_MARGIN;
+	i16Low  = u16Reading - TEMP_READING_ERROR_MARGIN;
+
+	/* Convert to Celsius */
+	i16High -= KELVIN_TO_CELSIUS_CONST;
+	i16Low  -= KELVIN_TO_CELSIUS_CONST;
+
+/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */
+#if 0
+	printk("Battery charger: Die temp %d to %d C\n", i16Low, i16High);
+#endif
+	/* Return the results */
+	*pHigh = i16High;
+	*pLow  = i16Low;
+}
+
+
+/*  */
+/* brief Checks to see if the DCDC has been manually enabled */
+/*  */
+/* fntype Function */
+/*  */
+/* retval  true if DCDC is ON, false if DCDC is OFF. */
+/*  */
+
+bool ddi_power_IsDcdcOn(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & BM_POWER_5VCTRL_ENABLE_DCDC) ? 1 : 0;
+}
+
+
+
+/*  See hw_power.h for details. */
+
+void ddi_power_SetPowerClkGate(bool bGate)
+{
+	/* Gate/Ungate the clock to the power block */
+#ifndef CONFIG_ARCH_MX28
+	if (bGate) {
+		__raw_writel(BM_POWER_CTRL_CLKGATE,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_CLKGATE,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+#endif
+}
+
+
+/*  See hw_power.h for details. */
+
+bool ddi_power_GetPowerClkGate(void)
+{
+#ifdef CONFIG_ARCH_MX28
+	return 0;
+#else
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & BM_POWER_CTRL_CLKGATE) ? 1 : 0;
+#endif
+}
+
+
+enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void)
+{
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+
+		if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+			BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO) {
+			if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) ||
+				ddi_power_Get5vPresentFlag())
+				return new_5v_connection;
+			else
+				return existing_5v_disconnection;
+		} else {
+			if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) ||
+				!ddi_power_Get5vPresentFlag() ||
+				ddi_power_Get5vDroopFlag())
+				return new_5v_disconnection;
+			else
+				return existing_5v_connection;
+		}
+	} else {
+
+		if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+			BM_POWER_CTRL_POLARITY_VBUSVALID) {
+			if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+				BM_POWER_CTRL_VBUSVALID_IRQ) ||
+				ddi_power_Get5vPresentFlag())
+				return new_5v_connection;
+			else
+				return existing_5v_disconnection;
+		} else {
+			if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+				BM_POWER_CTRL_VBUSVALID_IRQ) ||
+				!ddi_power_Get5vPresentFlag() ||
+				ddi_power_Get5vDroopFlag())
+				return new_5v_disconnection;
+			else
+				return existing_5v_connection;
+		}
+
+	}
+}
+
+void ddi_power_disable_5v_connection_irq(void)
+{
+
+	__raw_writel((BM_POWER_CTRL_ENIRQ_VBUS_VALID |
+		BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO),
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+}
+
+void ddi_power_enable_5v_disconnect_detection(void)
+{
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO |
+		BM_POWER_CTRL_POLARITY_VBUSVALID,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	}
+}
+
+void ddi_power_enable_5v_connect_detection(void)
+{
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO |
+		BM_POWER_CTRL_POLARITY_VBUSVALID,
+		REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	}
+}
+
+void ddi_power_EnableBatteryBoInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_BATT_BO_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+		__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+		/* todo: make sure the battery brownout comparator
+		 * is enabled in HW_POWER_BATTMONITOR
+		 */
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+}
+
+void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+		__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+}
+
+void ddi_power_EnableVdd5vDroopInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+}
+
+
+void ddi_power_Enable5vDisconnectShutdown(bool bEnable)
+{
+	if (bEnable) {
+		__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+	}
+}
+
+
+void ddi_power_enable_5v_to_battery_xfer(bool bEnable)
+{
+	if (bEnable) {
+		/* order matters */
+
+		/* we can enable this in in vbus droop or 4p2 fiq handler
+		 * ddi_power_EnableBatteryBoInterrupt(true);
+		 */
+		ddi_power_Enable5vDisconnectShutdown(false);
+	} else {
+		/* order matters */
+		ddi_power_Enable5vDisconnectShutdown(true);
+		ddi_power_EnableBatteryBoInterrupt(false);
+	}
+}
+
+
+void ddi_power_init_4p2_protection(void)
+{
+	/* set vbus droop detection level to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	/* VBUSDROOP THRESHOLD to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	ddi_power_EnableVbusDroopIrq();
+
+#ifndef CONFIG_ARCH_MX28
+	/* VBUSVALID THRESH = 2.9V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+#endif
+
+}
+
+/* determine if all the bits are in a 'DCDC 4P2 Enabled' state. */
+bool ddi_power_check_4p2_bits(void)
+{
+
+
+	uint32_t temp;
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
+		BM_POWER_5VCTRL_PWD_CHARGE_4P2;
+
+	/* if PWD_CHARGE_4P2 = 1, 4p2 is disabled */
+	if (temp)
+		return false;
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) &
+		BM_POWER_DCDC4P2_ENABLE_DCDC;
+
+	if (!temp)
+		return false;
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) &
+			BM_POWER_DCDC4P2_ENABLE_4P2;
+
+	if (temp)
+		return true;
+	else
+		return false;
+
+}
+
+uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit)
+{
+	uint32_t temp_reg;
+
+	if (ilimit > 780)
+		ilimit = 780;
+	temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL);
+	temp_reg &= (~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
+	temp_reg |= BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(
+		ddi_power_convert_current_to_setting(
+				ilimit));
+	__raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_5VCTRL);
+
+	return ilimit;
+}
+
+void ddi_power_shutdown(void)
+{
+	__raw_writel(0x3e770001, REGS_POWER_BASE + HW_POWER_RESET);
+}
+
+void ddi_power_handle_dcdc4p2_bo(void)
+{
+	ddi_power_EnableBatteryBoInterrupt(true);
+	ddi_power_EnableDcdc4p2BoInterrupt(false);
+}
+
+void ddi_power_enable_vddio_interrupt(bool enable)
+{
+	if (enable) {
+		__raw_writel(BM_POWER_CTRL_VDDIO_BO_IRQ,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+#ifndef DISABLE_VDDIO_BO_PROTECTION
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+#endif
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+
+}
+
+
+void ddi_power_handle_vddio_brnout(void)
+{
+	if (ddi_power_GetPmu5vStatus() == new_5v_connection ||
+		(ddi_power_GetPmu5vStatus() == new_5v_disconnection)) {
+		ddi_power_enable_vddio_interrupt(false);
+	} else {
+#ifdef DEBUG_IRQS
+		ddi_power_enable_vddio_interrupt(false);
+		printk(KERN_ALERT "VDDIO BO TRIED TO SHUTDOWN!!!\n");
+		return;
+#else
+		ddi_power_shutdown();
+#endif
+	}
+}
+
+void ddi_power_handle_vdd5v_droop(void)
+{
+	uint32_t temp;
+
+	/* handle errata */
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	temp |= (BF_POWER_DCDC4P2_CMPTRIP(31) | BM_POWER_DCDC4P2_TRG);
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+
+	/* if battery is below brownout level, shutdown asap */
+	if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_BATT_BO)
+		ddi_power_shutdown();
+
+	/* due to 5v connect vddio bo chip bug, we need to
+	 * disable vddio interrupts until we reset the 5v
+	 * detection for 5v connect detect.  We want to allow
+	 * some debounce time before enabling connect detection.
+	 */
+	ddi_power_enable_vddio_interrupt(false);
+
+	ddi_power_EnableBatteryBoInterrupt(true);
+	ddi_power_EnableDcdc4p2BoInterrupt(false);
+	ddi_power_EnableVdd5vDroopInterrupt(false);
+
+}
+
+void ddi_power_InitOutputBrownouts(void)
+{
+	uint32_t temp;
+
+	__raw_writel(BM_POWER_CTRL_VDDD_BO_IRQ |
+		BM_POWER_CTRL_VDDA_BO_IRQ |
+		BM_POWER_CTRL_VDDIO_BO_IRQ,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+		REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+	temp &= ~BM_POWER_VDDDCTRL_PWDN_BRNOUT;
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL);
+	temp &= ~BM_POWER_VDDACTRL_PWDN_BRNOUT;
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDACTRL);
+
+	temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+	temp &= ~BM_POWER_VDDIOCTRL_PWDN_BRNOUT;
+	__raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+}
+
+/* used for debugging purposes only */
+void ddi_power_disable_power_interrupts(void)
+{
+	__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO |
+		BM_POWER_CTRL_ENIRQ_VDD5V_DROOP |
+		BM_POWER_CTRL_ENIRQ_PSWITCH |
+		BM_POWER_CTRL_ENIRQ_DC_OK |
+		BM_POWER_CTRL_ENIRQBATT_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VBUS_VALID |
+		BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+}
+
+bool ddi_power_Get5vDroopFlag(void)
+{
+	if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+		BM_POWER_STS_VDD5V_DROOP)
+		return true;
+	else
+		return false;
+}
+
+
+/* End of file */
+
+/*  @} */
diff --git a/drivers/power/mxs/ddi_power_battery.h b/drivers/power/mxs/ddi_power_battery.h
new file mode 100644
index 000000000000..6a25569f25d3
--- /dev/null
+++ b/drivers/power/mxs/ddi_power_battery.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* brief Battery modes */
+typedef enum {
+	/* 37xx battery modes */
+	/* brief LiIon battery powers the player */
+	DDI_POWER_BATT_MODE_LIION           = 0,
+	/* brief Alkaline/NiMH battery powers the player */
+	DDI_POWER_BATT_MODE_ALKALINE_NIMH   = 1,
+} ddi_power_BatteryMode_t;
+
+
+/* brief Possible 5V detection methods */
+typedef enum {
+	/* brief Use VBUSVALID comparator for detection */
+	DDI_POWER_5V_VBUSVALID,
+	/* brief Use VDD5V_GT_VDDIO comparison for detection */
+	DDI_POWER_5V_VDD5V_GT_VDDIO
+} ddi_power_5vDetection_t;
+
+
+enum ddi_power_5v_status {
+	new_5v_connection,
+	existing_5v_connection,
+	new_5v_disconnection,
+	existing_5v_disconnection,
+} ;
+
+
+uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current);
+uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting);
+void ddi_power_enable_5v_to_battery_handoff(void);
+void ddi_power_execute_5v_to_battery_handoff(void);
+void ddi_power_enable_battery_to_5v_handoff(void);
+void ddi_power_execute_battery_to_5v_handoff(void);
+int ddi_power_init_battery(void);
+ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void);
+bool ddi_power_GetBatteryChargerEnabled(void);
+bool ddi_power_GetChargerPowered(void);
+void ddi_power_SetChargerPowered(bool bPowerOn);
+int ddi_power_GetChargeStatus(void);
+uint16_t ddi_power_GetBattery(void);
+uint16_t ddi_power_GetBatteryBrownout(void);
+int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV);
+uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur);
+uint16_t ddi_power_GetMaxBatteryChargeCurrent(void);
+uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh);
+uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void);
+uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current);
+bool ddi_power_Get5vPresentFlag(void);
+void ddi_power_GetDieTemp(int16_t *pLow, int16_t *pHigh);
+bool ddi_power_IsDcdcOn(void);
+void ddi_power_SetPowerClkGate(bool bGate);
+bool ddi_power_GetPowerClkGate(void);
+enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void);
+void ddi_power_EnableBatteryBoFiq(bool bEnable);
+void ddi_power_disable_5v_connection_irq(void);
+void ddi_power_enable_5v_disconnect_detection(void);
+void ddi_power_enable_5v_connect_detection(void);
+void ddi_power_Enable5vDisconnectShutdown(bool bEnable);
+void ddi_power_enable_5v_to_battery_xfer(bool bEnable);
+void ddi_power_init_4p2_protection(void);
+bool ddi_power_check_4p2_bits(void);
+void ddi_power_Start4p2Dcdc(bool battery_ready);
+void ddi_power_Init4p2Params(void);
+bool ddi_power_IsBattRdyForXfer(void);
+void ddi_power_EnableVbusDroopIrq(void);
+void ddi_power_Enable4p2(uint16_t target_current_limit_ma);
+uint16_t ddi_power_BringUp4p2Regulator(
+		uint16_t target_current_limit_ma,
+		bool b4p2_dcdc_enabled);
+void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv);
+void ddi_power_EnableBatteryBoInterrupt(bool bEnable);
+void ddi_power_handle_cmptrip(void);
+uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit);
+void ddi_power_shutdown(void);
+void ddi_power_handle_dcdc4p2_bo(void);
+void ddi_power_enable_vddio_interrupt(bool enable);
+void ddi_power_handle_vddio_brnout(void);
+void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable);
+void ddi_power_handle_vdd5v_droop(void);
+void ddi_power_InitOutputBrownouts(void);
+void ddi_power_disable_power_interrupts(void);
+bool ddi_power_Get5vDroopFlag(void);
diff --git a/drivers/power/mxs/fiq.S b/drivers/power/mxs/fiq.S
new file mode 100644
index 000000000000..1ad380d07efd
--- /dev/null
+++ b/drivers/power/mxs/fiq.S
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <asm/pgtable-hwdef.h>
+#include <mach/regs-power.h>
+#include <mach/../../regs-clkctrl.h>
+#include <mach/regs-timrot.h>
+
+	.align 5
+	.globl power_fiq_start
+	.globl power_fiq_end
+	.globl power_fiq_count
+	.globl lock_vector_tlb
+
+power_fiq_start:
+	ldr 	r8,power_reg
+	ldr	r9,[r8,#HW_POWER_CTRL ]
+	ldr	r10,power_off
+
+	@ when VDDIO_BO_IRQ,
+	@ disabled, handled in IRQ for now
+	@tst 	r9, #BM_POWER_CTRL_VDDIO_BO_IRQ
+
+
+	@ when BATT_BO_IRQ,  VDDD_BO_IRQ, VDDA_BO_IRQ, power off chip
+	ldr     r11,power_bo
+	tst	r9, r11
+	strne 	r10,[r8,#HW_POWER_RESET]
+
+	@VDD5V_DROOP_IRQ
+	tst     r9, #BM_POWER_CTRL_VDD5V_DROOP_IRQ
+	beq	    check_dcdc4p2
+
+	@ handle errata
+	ldr	r10, [r8, #HW_POWER_DCDC4P2]
+	orr	r10,r10,#(BM_POWER_DCDC4P2_TRG)
+	orr 	r10,r10,#(BF_POWER_DCDC4P2_CMPTRIP(31))
+	str	r10,[r8, #(HW_POWER_DCDC4P2)]
+
+	@ if battery is below brownout level, shutdown asap
+	ldr	r10,  [r8, #HW_POWER_STS]
+	tst	r10, #BM_POWER_STS_BATT_BO
+	ldr	r10, power_off
+	strne	r10, [r8, #HW_POWER_RESET]
+
+	@ disable viddio irq
+	mov	r11, #BM_POWER_CTRL_ENIRQ_VDDIO_BO
+	str 	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	@ enable battery BO irq
+	mov	r11, #BM_POWER_CTRL_BATT_BO_IRQ
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+	mov	r11, #BM_POWER_CTRL_ENIRQBATT_BO
+	str	r11, [r8, #HW_POWER_CTRL_SET]
+
+	@ disable dcdc4p2 interrupt
+	mov	r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	@ disable vdd5v_droop interrupt
+	mov	r11, #BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+
+check_dcdc4p2:
+		@ when DCDC4P2_BO_IRQ,
+	tst 	r9, #BM_POWER_CTRL_DCDC4P2_BO_IRQ
+
+	mov	r11, #BM_POWER_CTRL_BATT_BO_IRQ
+	strne	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	mov	r11, #BM_POWER_CTRL_ENIRQBATT_BO
+	strne   r11, [r8, #HW_POWER_CTRL_SET]
+
+	mov	r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+	strne	r11, [r8, #HW_POWER_CTRL_CLR]
+
+
+
+	@return from fiq
+	subs    pc,lr, #4
+
+power_reg:
+	.long IO_ADDRESS(POWER_PHYS_ADDR)
+power_off:
+	.long 0x3e770001
+power_bo:
+	.long BM_POWER_CTRL_BATT_BO_IRQ | \
+	      BM_POWER_CTRL_VDDA_BO_IRQ | BM_POWER_CTRL_VDDD_BO_IRQ
+power_fiq_count:
+	.long 0
+power_fiq_end:
+
+lock_vector_tlb:
+
+	mov r1, r0 @ set r1 to the value of the address to be locked down
+	mcr p15,0,r1,c8,c7,1    @ invalidate TLB single entry to ensure that
+				@ LockAddr is not already in the TLB
+	mrc p15,0,r0,c10,c0,0   @ read the lockdown register
+	orr r0,r0,#1            @ set the preserve bit
+	mcr p15,0,r0,c10,c0,0   @ write to the lockdown register
+	ldr r1,[r1]             @ TLB will miss, and entry will be loaded
+	mrc p15,0,r0,c10,c0,0   @ read the lockdown register (victim will have
+				@ incremented)
+	bic r0,r0,#1            @ clear preserve bit
+	mcr p15,0,r0,c10,c0,0   @ write to the lockdown registerADR r1,LockAddr
+	mov pc,lr		@
diff --git a/drivers/power/mxs/linux.c b/drivers/power/mxs/linux.c
new file mode 100644
index 000000000000..1c2dfc10f7ca
--- /dev/null
+++ b/drivers/power/mxs/linux.c
@@ -0,0 +1,1182 @@
+/*
+ * Linux glue to MXS battery state machine.
+ *
+ * Author: Steve Longerbeam <stevel@embeddedalley.com>
+ *
+ * Copyright (C) 2008 EmbeddedAlley Solutions Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/jiffies.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/clk.h>
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <mach/regulator.h>
+#include <mach/regs-power.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/clock.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/interrupt.h>
+#include <asm/fiq.h>
+
+enum application_5v_status{
+	_5v_connected_verified,
+	_5v_connected_unverified,
+	_5v_disconnected_unverified,
+	_5v_disconnected_verified,
+};
+
+struct mxs_info {
+	struct device *dev;
+	struct regulator *regulator;
+
+	struct power_supply bat;
+	struct power_supply ac;
+	struct power_supply usb;
+
+	ddi_bc_Cfg_t *sm_cfg;
+	struct mutex sm_lock;
+	struct timer_list sm_timer;
+	struct work_struct sm_work;
+	struct resource *irq_vdd5v;
+	struct resource *irq_dcdc4p2_bo;
+	struct resource *irq_batt_brnout;
+	struct resource *irq_vddd_brnout;
+	struct resource *irq_vdda_brnout;
+	struct resource *irq_vddio_brnout;
+	struct resource *irq_vdd5v_droop;
+	int is_ac_online;
+	int source_protection_mode;
+	uint32_t sm_new_5v_connection_jiffies;
+	uint32_t sm_new_5v_disconnection_jiffies;
+	enum application_5v_status sm_5v_connection_status;
+
+
+
+
+#define USB_ONLINE      0x01
+#define USB_REG_SET     0x02
+#define USB_SM_RESTART  0x04
+#define USB_SHUTDOWN    0x08
+#define USB_N_SEND      0x10
+	int is_usb_online;
+};
+
+#define to_mxs_info(x) container_of((x), struct mxs_info, bat)
+
+#ifndef NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA
+#define NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA 780
+#endif
+
+#ifndef POWERED_USB_5V_CURRENT_LIMIT_MA
+#define POWERED_USB_5V_CURRENT_LIMIT_MA 450
+#endif
+
+#ifndef UNPOWERED_USB_5V_CURRENT_LIMIT_MA
+#define UNPOWERED_USB_5V_CURRENT_LIMIT_MA 80
+#endif
+
+#ifndef _5V_DEBOUNCE_TIME_MS
+#define _5V_DEBOUNCE_TIME_MS 500
+#endif
+
+#ifndef OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV
+#define OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV 3350
+#endif
+
+#ifdef CONFIG_ARCH_MX23
+#define IRQ_DCDC4P2_BRNOUT IRQ_DCDC4P2_BO
+#endif
+
+#define  POWER_FIQ
+
+/* #define DEBUG_IRQS */
+
+/* There is no direct way to detect wall power presence, so assume the AC
+ * power source is valid if 5V presents and USB device is disconnected.
+ * If USB device is connected then assume that AC is offline and USB power
+ * is online.
+ */
+
+
+#define is_ac_online()	\
+		(ddi_power_Get5vPresentFlag() ? (!fsl_is_usb_plugged()) : 0)
+#define is_usb_online()	\
+		(ddi_power_Get5vPresentFlag() ? (!!fsl_is_usb_plugged()) : 0)
+
+
+
+void init_protection(struct mxs_info *info)
+{
+	enum ddi_power_5v_status pmu_5v_status;
+	uint16_t battery_voltage;
+
+	pmu_5v_status = ddi_power_GetPmu5vStatus();
+	battery_voltage = ddi_power_GetBattery();
+
+	/* InitializeFiqSystem(); */
+	ddi_power_InitOutputBrownouts();
+
+
+	/* if we start the kernel with 4p2 already started
+	 * by the bootlets, we need to hand off from this
+	 * state to the kernel 4p2 enabled state.
+	 */
+	if ((pmu_5v_status == existing_5v_connection) &&
+		 ddi_power_check_4p2_bits()) {
+		ddi_power_enable_5v_disconnect_detection();
+
+		/* includes VBUS DROOP workaround for errata */
+		ddi_power_init_4p2_protection();
+
+		/* if we still have our 5V connection, we can disable
+		 * battery brownout interrupt.  This is because the
+		 * VDD5V DROOP IRQ handler will also shutdown if battery
+		 * is browned out and it will enable the battery brownout
+		 * and bring VBUSVALID_TRSH level back to a normal level
+		 * which caused the hardware battery brownout shutdown
+		 * to be enabled.  The benefit of this is that device
+		 * that have detachable batteries (or devices going through
+		 * the assembly line and running this firmware to test
+		 *  with) can avoid shutting down if 5V is present and
+		 *  battery voltage goes away.
+		 */
+		ddi_power_EnableBatteryBoInterrupt(false);
+
+		info->sm_5v_connection_status = _5v_connected_verified;
+	} else {
+#ifdef DEBUG_IRQS
+		if (battery_voltage <
+			OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) {
+			printk(KERN_CRIT "Polled battery voltage measurement is\
+				less than %dmV.  Kernel should be halted/\
+				shutdown\n",
+				OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV);
+
+			return;
+		}
+#endif
+		info->sm_5v_connection_status = _5v_disconnected_verified;
+		ddi_power_EnableBatteryBoInterrupt(true);
+
+	}
+
+
+	/* all brownouts are now handled software fiqs.  We
+	 * can now disable the hardware protection mechanisms
+	 *  because leaving them on yields ~2kV ESD level
+	 *  versus ~4kV ESD levels when they are off.  This
+	 *  difference is suspected to be cause by the fast
+	 *  falling edge pswitch functionality being tripped
+	 *  by ESD events.  This functionality is disabled
+	 *  when PWD_OFF is disabled.
+	 */
+#ifdef DISABLE_HARDWARE_PROTECTION_MECHANISMS
+	__raw_writel(BM_POWER_RESET_PWD_OFF,
+		HW_POWER_RESET_SET_ADDR);
+#endif
+
+
+
+
+}
+
+
+
+static void check_and_handle_5v_connection(struct mxs_info *info)
+{
+
+	switch (ddi_power_GetPmu5vStatus()) {
+
+	case new_5v_connection:
+		ddi_power_enable_5v_disconnect_detection();
+		info->sm_5v_connection_status = _5v_connected_unverified;
+
+	case existing_5v_connection:
+		if (info->sm_5v_connection_status != _5v_connected_verified) {
+			/* we allow some time to pass before considering
+			 * the 5v connection to be ready to use.  This
+			 * will give the USB system time to enumerate
+			 * (coordination with USB driver to be added
+			 * in the future).
+			 */
+
+			/* handle jiffies rollover case */
+			if ((jiffies - info->sm_new_5v_connection_jiffies)
+				< 0) {
+				info->sm_new_5v_connection_jiffies = jiffies;
+				break;
+			}
+
+			if ((jiffies_to_msecs(jiffies -
+				info->sm_new_5v_connection_jiffies)) >
+				_5V_DEBOUNCE_TIME_MS) {
+				info->sm_5v_connection_status =
+					_5v_connected_verified;
+				dev_dbg(info->dev,
+					"5v connection verified\n");
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	#ifdef CONFIG_USB_GADGET
+		/* if there is USB 2.0 current limitation requirement,
+		* waiting for USB enum done.
+		*/
+		if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
+			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) ==
+			(0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
+			dev_info(info->dev, "waiting USB enum done...\r\n");
+		}
+		while ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
+			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
+			== (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) {
+			msleep(50);
+		}
+	#endif
+#endif
+				ddi_power_Enable4p2(450);
+
+				/* part of handling for errata.  It is
+				 *  now "somewhat" safe to
+				 * turn on vddio interrupts again
+				 */
+				ddi_power_enable_vddio_interrupt(true);
+			}
+		}
+		break;
+
+	case new_5v_disconnection:
+
+		ddi_bc_SetDisable();
+		ddi_bc_SetCurrentLimit(0);
+		if (info->regulator)
+			regulator_set_current_limit(info->regulator, 0, 0);
+		info->is_usb_online = 0;
+		info->is_ac_online = 0;
+
+		info->sm_5v_connection_status = _5v_disconnected_unverified;
+
+	case existing_5v_disconnection:
+
+		if (info->sm_5v_connection_status !=
+			_5v_disconnected_verified) {
+			if ((jiffies - info->sm_new_5v_disconnection_jiffies)
+				< 0) {
+				info->sm_new_5v_connection_jiffies = jiffies;
+				break;
+			}
+
+			if ((jiffies_to_msecs(jiffies -
+				info->sm_new_5v_disconnection_jiffies)) >
+				_5V_DEBOUNCE_TIME_MS) {
+				info->sm_5v_connection_status =
+					_5v_disconnected_verified;
+				ddi_power_execute_5v_to_battery_handoff();
+				ddi_power_enable_5v_connect_detection();
+
+				/* part of handling for errata.
+				 * It is now safe to
+				 * turn on vddio interrupts again
+				 */
+				ddi_power_enable_vddio_interrupt(true);
+				dev_dbg(info->dev,
+					"5v disconnection handled\n");
+
+				__raw_writel(__raw_readl(REGS_POWER_BASE +
+				HW_POWER_5VCTRL) &
+				(~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
+				| (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT),
+				REGS_POWER_BASE + HW_POWER_5VCTRL);
+
+			}
+		}
+
+		break;
+	}
+}
+
+
+static void handle_battery_voltage_changes(struct mxs_info *info)
+{
+#if 0
+	uint16_t battery_voltage;
+
+	battery_voltage = ddi_power_GetBattery();
+
+	if (info->sm_5v_connection_status != _5v_connected_verified) {
+		if (battery_voltage <
+			OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) {
+			printk(KERN_CRIT "Polled battery voltage measurement is\
+				less than %dmV.  Shutting down the \
+				system\n",
+				OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV);
+
+			shutdown_os();
+			return;
+		}
+	} else
+#endif
+	{
+		ddi_power_handle_cmptrip();
+
+		if (ddi_power_IsBattRdyForXfer())
+			ddi_power_enable_5v_to_battery_xfer(true);
+		else
+			ddi_power_enable_5v_to_battery_xfer(false);
+
+	}
+}
+
+
+/*
+ * Power properties
+ */
+static enum power_supply_property mxs_power_props[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+static int mxs_power_get_property(struct power_supply *psy,
+				     enum power_supply_property psp,
+				     union power_supply_propval *val)
+{
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		if (psy->type == POWER_SUPPLY_TYPE_MAINS)
+			/* ac online */
+			val->intval = is_ac_online();
+		else
+			/* usb online */
+			val->intval = is_usb_online();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+/*
+ * Battery properties
+ */
+static enum power_supply_property mxs_bat_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_HEALTH,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_TEMP,
+};
+
+static int mxs_bat_get_property(struct power_supply *psy,
+				     enum power_supply_property psp,
+				     union power_supply_propval *val)
+{
+	struct mxs_info *info = to_mxs_info(psy);
+	ddi_bc_State_t state;
+	ddi_bc_BrokenReason_t reason;
+	int temp_alarm;
+	int16_t temp_lo, temp_hi;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		state = ddi_bc_GetState();
+		switch (state) {
+		case DDI_BC_STATE_CONDITIONING:
+		case DDI_BC_STATE_CHARGING:
+		case DDI_BC_STATE_TOPPING_OFF:
+			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+			break;
+		case DDI_BC_STATE_DISABLED:
+			val->intval = ddi_power_Get5vPresentFlag() ?
+				POWER_SUPPLY_STATUS_NOT_CHARGING :
+			POWER_SUPPLY_STATUS_DISCHARGING;
+			break;
+		default:
+			/* TODO: detect full */
+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+			break;
+		}
+		break;
+	case POWER_SUPPLY_PROP_PRESENT:
+		/* is battery present */
+		state = ddi_bc_GetState();
+		switch (state) {
+		case DDI_BC_STATE_WAITING_TO_CHARGE:
+		case DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE:
+		case DDI_BC_STATE_CONDITIONING:
+		case DDI_BC_STATE_CHARGING:
+		case DDI_BC_STATE_TOPPING_OFF:
+		case DDI_BC_STATE_DISABLED:
+			val->intval = 1;
+			break;
+		case DDI_BC_STATE_BROKEN:
+			val->intval = !(ddi_bc_GetBrokenReason() ==
+					DDI_BC_BROKEN_NO_BATTERY_DETECTED);
+			break;
+		default:
+			val->intval = 0;
+			break;
+		}
+		break;
+	case POWER_SUPPLY_PROP_HEALTH:
+		temp_alarm = ddi_bc_RampGetDieTempAlarm();
+		if (temp_alarm) {
+			val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
+		} else {
+			state = ddi_bc_GetState();
+			switch (state) {
+			case DDI_BC_STATE_BROKEN:
+				reason = ddi_bc_GetBrokenReason();
+				val->intval =
+				   (reason == DDI_BC_BROKEN_CHARGING_TIMEOUT) ?
+					POWER_SUPPLY_HEALTH_DEAD :
+					POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
+				break;
+			case DDI_BC_STATE_UNINITIALIZED:
+				val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
+				break;
+			default:
+				val->intval = POWER_SUPPLY_HEALTH_GOOD;
+				break;
+			}
+		}
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		/* uV */
+		val->intval = ddi_power_GetBattery() * 1000;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		/* uA */
+		val->intval = ddi_power_GetMaxBatteryChargeCurrent() * 1000;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		mutex_lock(&info->sm_lock);
+		ddi_power_GetDieTemp(&temp_lo, &temp_hi);
+		mutex_unlock(&info->sm_lock);
+		val->intval = temp_lo + (temp_hi - temp_lo) / 2;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void state_machine_timer(unsigned long data)
+{
+	struct mxs_info *info = (struct mxs_info *)data;
+	ddi_bc_Cfg_t *cfg = info->sm_cfg;
+	int ret;
+
+	/* schedule next call to state machine */
+	mod_timer(&info->sm_timer,
+		  jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod));
+
+	ret = schedule_work(&info->sm_work);
+	if (!ret)
+		dev_dbg(info->dev, "state machine failed to schedule\n");
+
+}
+/*
+ * Assumption:
+ * AC power can't be switched to USB w/o system reboot
+ * and vice-versa
+ */
+static void state_machine_work(struct work_struct *work)
+{
+	struct mxs_info *info =
+		container_of(work, struct mxs_info, sm_work);
+
+	mutex_lock(&info->sm_lock);
+
+	handle_battery_voltage_changes(info);
+
+	check_and_handle_5v_connection(info);
+
+	if ((info->sm_5v_connection_status != _5v_connected_verified) ||
+			!(info->regulator)) {
+		mod_timer(&info->sm_timer, jiffies + msecs_to_jiffies(100));
+		goto out;
+	}
+
+	/* if we made it here, we have a verified 5v connection */
+#ifndef CONFIG_MXS_VBUS_CURRENT_DRAW
+		if (info->is_ac_online)
+			goto done;
+
+		/* ac supply connected */
+		dev_dbg(info->dev, "changed power connection to ac/5v.\n)");
+		dev_dbg(info->dev, "5v current limit set to %u.\n",
+			NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA);
+
+		info->is_ac_online = 1;
+		info->is_usb_online = 0;
+		ddi_power_set_4p2_ilimit(
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA);
+		ddi_bc_SetCurrentLimit(
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/);
+		if (regulator_set_current_limit(info->regulator,
+				0,
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000)) {
+			dev_err(info->dev, "reg_set_current(%duA) failed\n",
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000);
+		}
+		ddi_bc_SetEnable();
+		goto done;
+#else
+
+	if (!is_usb_online())
+		goto out;
+
+	if (info->is_usb_online & USB_REG_SET)
+		goto done;
+
+	info->is_ac_online = 0;
+	info->is_usb_online |= USB_ONLINE;
+
+
+
+	if (!(info->is_usb_online & USB_N_SEND)) {
+		info->is_usb_online |= USB_N_SEND;
+	}
+
+
+	dev_dbg(info->dev, "%s: charge current set to %dmA\n", __func__,
+			POWERED_USB_5V_CURRENT_LIMIT_MA);
+
+	if (regulator_set_current_limit(info->regulator,
+		0,
+		POWERED_USB_5V_CURRENT_LIMIT_MA*1000)) {
+		dev_err(info->dev, "reg_set_current(%duA) failed\n",
+				POWERED_USB_5V_CURRENT_LIMIT_MA*1000);
+	} else {
+		ddi_bc_SetCurrentLimit(POWERED_USB_5V_CURRENT_LIMIT_MA/*mA*/);
+		ddi_bc_SetEnable();
+	}
+
+	if (info->is_usb_online & USB_SM_RESTART) {
+		info->is_usb_online &= ~USB_SM_RESTART;
+		ddi_bc_SetEnable();
+	}
+
+	info->is_usb_online |= USB_REG_SET;
+
+#endif
+	dev_dbg(info->dev, "changed power connection to usb/5v present\n");
+
+done:
+	ddi_bc_StateMachine();
+out:
+	mutex_unlock(&info->sm_lock);
+}
+
+
+
+static int bc_sm_restart(struct mxs_info *info)
+{
+	ddi_bc_Status_t bcret;
+	int ret = 0;
+
+	mutex_lock(&info->sm_lock);
+
+	/* ungate power clk */
+	ddi_power_SetPowerClkGate(0);
+
+	/*
+	 * config battery charger state machine and move it to the Disabled
+	 * state. This must be done before starting the state machine.
+	 */
+	bcret = ddi_bc_Init(info->sm_cfg);
+	if (bcret != DDI_BC_STATUS_SUCCESS) {
+		dev_err(info->dev, "battery charger init failed: %d\n", bcret);
+		ret = -EIO;
+		goto out;
+	} else {
+
+		if (!info->regulator) {
+			info->regulator = regulator_get(NULL, "charger-1");
+			if (!info->regulator || IS_ERR(info->regulator)) {
+				dev_err(info->dev,
+				"%s: failed to get regulator\n", __func__);
+				info->regulator = NULL;
+			} else {
+				regulator_set_current_limit(
+						info->regulator, 0, 0);
+				regulator_set_mode(info->regulator,
+						   REGULATOR_MODE_FAST);
+			}
+		}
+	}
+
+
+
+	/* schedule first call to state machine */
+	mod_timer(&info->sm_timer, jiffies + 1);
+out:
+	mutex_unlock(&info->sm_lock);
+	return ret;
+}
+
+#ifndef POWER_FIQ
+
+static irqreturn_t mxs_irq_dcdc4p2_bo(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "dcdc4p2 brownout interrupt occurred\n");
+
+#endif
+	ddi_power_handle_dcdc4p2_bo();
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxs_irq_batt_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "battery brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+
+
+static irqreturn_t mxs_irq_vddd_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "vddd brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+static irqreturn_t mxs_irq_vdda_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "vdda brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxs_irq_vdd5v_droop(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "vdd5v droop interrupt occurred\n");
+#endif
+	ddi_power_handle_vdd5v_droop();
+
+	return IRQ_HANDLED;
+}
+
+#endif /* if POWER_FIQ */
+
+static irqreturn_t mxs_irq_vddio_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct mxs_info *info = (struct mxs_info *)cookie;
+	dev_info(info->dev, "vddio brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_handle_vddio_brnout();
+#endif
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxs_irq_vdd5v(int irq, void *cookie)
+{
+	struct mxs_info *info = (struct mxs_info *)cookie;
+
+	switch (ddi_power_GetPmu5vStatus()) {
+
+	case new_5v_connection:
+
+		ddi_power_disable_5v_connection_irq();
+		dev_dbg(info->dev, "new 5v connection detected\n");
+		info->sm_new_5v_connection_jiffies = jiffies;
+		mod_timer(&info->sm_timer, jiffies + 1);
+		break;
+
+	case new_5v_disconnection:
+
+		/* due to 5v connect vddio bo chip bug, we need to
+		 * disable vddio interrupts until we reset the 5v
+		 * detection for 5v connect detect.  We want to allow
+		 * some debounce time before enabling connect detection.
+		 * This is handled in the vdd5v_droop interrupt for now.
+		 */
+		/* ddi_power_enable_vddio_interrupt(false); */
+
+		ddi_power_disable_5v_connection_irq();
+		dev_dbg(info->dev, "new 5v disconnection detected\n");
+		info->sm_new_5v_disconnection_jiffies = jiffies;
+		mod_timer(&info->sm_timer, jiffies + 1);
+		break;
+
+	default:
+
+		break;
+
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mxs_bat_probe(struct platform_device *pdev)
+{
+	struct mxs_info *info;
+	int ret = 0;
+
+
+	/* enable usb device presence detection */
+	fsl_enable_usb_plugindetect();
+
+	ret = ddi_power_init_battery();
+	if (ret) {
+		printk(KERN_ERR "Aborting power driver initialization\n");
+		return 1;
+	}
+
+
+	if (!pdev->dev.platform_data) {
+		printk(KERN_ERR "%s: missing platform data\n", __func__);
+		return -ENODEV;
+	}
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->irq_vdd5v = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (info->irq_vdd5v == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vddio_brnout = platform_get_resource(
+		pdev, IORESOURCE_IRQ, 5);
+	if (info->irq_vddio_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+#ifndef POWER_FIQ
+	info->irq_dcdc4p2_bo = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (info->irq_dcdc4p2_bo == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_batt_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
+	if (info->irq_batt_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vddd_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 3);
+	if (info->irq_vddd_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vdda_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 4);
+	if (info->irq_vdda_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+
+	info->irq_vdd5v_droop = platform_get_resource(pdev, IORESOURCE_IRQ, 6);
+	if (info->irq_vdd5v_droop == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+#endif
+
+
+	platform_set_drvdata(pdev, info);
+
+	info->dev    = &pdev->dev;
+	info->sm_cfg = pdev->dev.platform_data;
+
+	/* initialize bat power_supply struct */
+	info->bat.name           = "battery";
+	info->bat.type           = POWER_SUPPLY_TYPE_BATTERY;
+	info->bat.properties     = mxs_bat_props;
+	info->bat.num_properties = ARRAY_SIZE(mxs_bat_props);
+	info->bat.get_property   = mxs_bat_get_property;
+
+	/* initialize ac power_supply struct */
+	info->ac.name           = "ac";
+	info->ac.type           = POWER_SUPPLY_TYPE_MAINS;
+	info->ac.properties     = mxs_power_props;
+	info->ac.num_properties = ARRAY_SIZE(mxs_power_props);
+	info->ac.get_property   = mxs_power_get_property;
+
+	/* initialize usb power_supply struct */
+	info->usb.name           = "usb";
+	info->usb.type           = POWER_SUPPLY_TYPE_USB;
+	info->usb.properties     = mxs_power_props;
+	info->usb.num_properties = ARRAY_SIZE(mxs_power_props);
+	info->usb.get_property   = mxs_power_get_property;
+
+	init_timer(&info->sm_timer);
+	info->sm_timer.data = (unsigned long)info;
+	info->sm_timer.function = state_machine_timer;
+
+	mutex_init(&info->sm_lock);
+	INIT_WORK(&info->sm_work, state_machine_work);
+
+	/* init LRADC channels to measure battery voltage and die temp */
+
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	ret = bc_sm_restart(info);
+	if (ret)
+		goto free_info;
+
+
+	ret = request_irq(info->irq_vdd5v->start,
+			mxs_irq_vdd5v, IRQF_DISABLED | IRQF_SHARED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vddio_brnout->start,
+			mxs_irq_vddio_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+#ifndef POWER_FIQ
+	ret = request_irq(info->irq_dcdc4p2_bo->start,
+			mxs_irq_dcdc4p2_bo, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_batt_brnout->start,
+			mxs_irq_batt_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vddd_brnout->start,
+			mxs_irq_vddd_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vdda_brnout->start,
+			mxs_irq_vdda_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+
+	ret = request_irq(info->irq_vdd5v_droop->start,
+			mxs_irq_vdd5v_droop, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+#endif
+
+	ret = power_supply_register(&pdev->dev, &info->bat);
+	if (ret) {
+		dev_err(info->dev, "failed to register battery\n");
+		goto free_irq;
+	}
+
+	ret = power_supply_register(&pdev->dev, &info->ac);
+	if (ret) {
+		dev_err(info->dev, "failed to register ac power supply\n");
+		goto unregister_bat;
+	}
+
+	ret = power_supply_register(&pdev->dev, &info->usb);
+	if (ret) {
+		dev_err(info->dev, "failed to register usb power supply\n");
+		goto unregister_ac;
+	}
+
+	/* handoff protection handling from bootlets protection method
+	 * to kernel protection method
+	 */
+	init_protection(info);
+
+
+	return 0;
+
+unregister_ac:
+	power_supply_unregister(&info->ac);
+unregister_bat:
+	power_supply_unregister(&info->bat);
+free_irq:
+	free_irq(info->irq_vdd5v->start, pdev);
+	free_irq(info->irq_vddio_brnout->start, pdev);
+#ifndef	POWER_FIQ
+	free_irq(info->irq_dcdc4p2_bo->start, pdev);
+	free_irq(info->irq_batt_brnout->start, pdev);
+	free_irq(info->irq_vddd_brnout->start, pdev);
+	free_irq(info->irq_vdda_brnout->start, pdev);
+	free_irq(info->irq_vdd5v_droop->start, pdev);
+#endif
+
+stop_sm:
+	ddi_bc_ShutDown();
+free_info:
+	kfree(info);
+	return ret;
+}
+
+static int mxs_bat_remove(struct platform_device *pdev)
+{
+	struct mxs_info *info = platform_get_drvdata(pdev);
+
+	if (info->regulator)
+		regulator_put(info->regulator);
+	free_irq(info->irq_vdd5v->start, pdev);
+	free_irq(info->irq_vddio_brnout->start, pdev);
+#ifndef	POWER_FIQ
+	free_irq(info->irq_dcdc4p2_bo->start, pdev);
+	free_irq(info->irq_batt_brnout->start, pdev);
+	free_irq(info->irq_vddd_brnout->start, pdev);
+	free_irq(info->irq_vdda_brnout->start, pdev);
+	free_irq(info->irq_vdd5v_droop->start, pdev);
+#endif
+	ddi_bc_ShutDown();
+	power_supply_unregister(&info->usb);
+	power_supply_unregister(&info->ac);
+	power_supply_unregister(&info->bat);
+	return 0;
+}
+
+static void mxs_bat_shutdown(struct platform_device *pdev)
+{
+	ddi_bc_ShutDown();
+}
+
+
+#ifdef CONFIG_PM
+
+static int mxs_bat_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+	struct mxs_info *info = platform_get_drvdata(pdev);
+
+	mutex_lock(&info->sm_lock);
+
+	/* enable USB 5v wake up so don't disable irq here*/
+
+	ddi_bc_SetDisable();
+	/* cancel state machine timer */
+	del_timer_sync(&info->sm_timer);
+
+	mutex_unlock(&info->sm_lock);
+	return 0;
+}
+
+static int mxs_bat_resume(struct platform_device *pdev)
+{
+	struct mxs_info *info = platform_get_drvdata(pdev);
+	ddi_bc_Cfg_t *cfg = info->sm_cfg;
+
+	mutex_lock(&info->sm_lock);
+
+	if (is_ac_online()) {
+		/* ac supply connected */
+		dev_dbg(info->dev, "ac/5v present, enabling state machine\n");
+
+		info->is_ac_online = 1;
+		info->is_usb_online = 0;
+		ddi_bc_SetCurrentLimit(
+			NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/);
+		ddi_bc_SetEnable();
+	} else if (is_usb_online()) {
+		/* usb supply connected */
+		dev_dbg(info->dev, "usb/5v present, enabling state machine\n");
+
+		info->is_ac_online = 0;
+		info->is_usb_online = 1;
+		ddi_bc_SetCurrentLimit(POWERED_USB_5V_CURRENT_LIMIT_MA /*mA*/);
+		ddi_bc_SetEnable();
+	} else {
+		/* not powered */
+		dev_dbg(info->dev, "%s: 5v not present\n", __func__);
+
+		info->is_ac_online = 0;
+		info->is_usb_online = 0;
+	}
+
+	/* enable 5v irq */
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+		REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+	/* reschedule calls to state machine */
+	mod_timer(&info->sm_timer,
+		  jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod));
+
+	mutex_unlock(&info->sm_lock);
+	return 0;
+}
+
+#else
+#define mxs_bat_suspend NULL
+#define mxs_bat_resume  NULL
+#endif
+
+static struct platform_driver mxs_batdrv = {
+	.probe		= mxs_bat_probe,
+	.remove		= mxs_bat_remove,
+	.shutdown       = mxs_bat_shutdown,
+	.suspend	= mxs_bat_suspend,
+	.resume		= mxs_bat_resume,
+	.driver		= {
+		.name	= "mxs-battery",
+		.owner	= THIS_MODULE,
+	},
+};
+
+#ifdef POWER_FIQ
+static int power_relinquish(void *data, int relinquish)
+{
+	return -1;
+}
+
+static struct fiq_handler power_fiq = {
+	.name = "mxs-battery",
+	.fiq_op = power_relinquish
+};
+
+static struct pt_regs fiq_regs;
+extern char power_fiq_start[], power_fiq_end[];
+extern void lock_vector_tlb(void *);
+extern long power_fiq_count;
+static struct proc_dir_entry *power_fiq_proc;
+#endif
+
+static int __init mxs_bat_init(void)
+{
+	struct clk *cpu, *pll0;
+
+#ifdef POWER_FIQ
+	int ret;
+	ret = claim_fiq(&power_fiq);
+	if (ret) {
+		pr_err("Can't claim fiq");
+	} else {
+		get_fiq_regs(&fiq_regs);
+		set_fiq_handler(power_fiq_start, power_fiq_end-power_fiq_start);
+		lock_vector_tlb((void *)0xffff0000);
+		lock_vector_tlb(REGS_POWER_BASE);
+
+		/* disable interrupts to be configured as FIQs */
+		disable_irq(IRQ_DCDC4P2_BRNOUT);
+		disable_irq(IRQ_BATT_BRNOUT);
+		disable_irq(IRQ_VDDD_BRNOUT);
+#ifndef CONFIG_ARCH_MX28
+		disable_irq(IRQ_VDD18_BRNOUT);
+#endif
+		disable_irq(IRQ_VDD5V_DROOP);
+
+
+		/* Enable these interrupts as FIQs */
+		mxs_set_irq_fiq(IRQ_DCDC4P2_BRNOUT, 1);
+		mxs_set_irq_fiq(IRQ_BATT_BRNOUT, 1);
+		mxs_set_irq_fiq(IRQ_VDDD_BRNOUT, 1);
+#ifndef CONFIG_ARCH_MX28
+		mxs_set_irq_fiq(IRQ_VDD18_BRNOUT, 1);
+#endif
+		mxs_set_irq_fiq(IRQ_VDD5V_DROOP, 1);
+
+
+		/* enable FIQ functionality */
+		mxs_enable_fiq_functionality(1);
+
+		enable_irq(IRQ_DCDC4P2_BRNOUT);
+		enable_irq(IRQ_BATT_BRNOUT);
+		enable_irq(IRQ_VDDD_BRNOUT);
+#ifndef CONFIG_ARCH_MX28
+		enable_irq(IRQ_VDD18_BRNOUT);
+#endif
+		enable_irq(IRQ_VDD5V_DROOP);
+
+	}
+#endif
+
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	if (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
+		BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000)
+		&& ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
+		BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0)) {
+#ifdef CONFIG_USB_GADGET
+		printk(KERN_INFO "USB GADGET exist,wait USB enum done...\r\n");
+		while (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL)
+			& BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) &&
+			((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) &
+			BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0))
+			;
+#else
+		printk(KERN_INFO "USB GADGET not exist,\
+		release current limit and let CPU clock up...\r\n");
+#endif
+	}
+	cpu = clk_get(NULL, "cpu");
+	pll0 = clk_get(NULL, "ref_cpu");
+	clk_set_parent(cpu, pll0);
+#endif
+	return platform_driver_register(&mxs_batdrv);
+}
+
+static void __exit mxs_bat_exit(void)
+{
+	platform_driver_unregister(&mxs_batdrv);
+}
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	fs_initcall(mxs_bat_init);
+#else
+	module_init(mxs_bat_init);
+#endif
+module_exit(mxs_bat_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Steve Longerbeam <stevel@embeddedalley.com>");
+MODULE_DESCRIPTION("Linux glue to MXS battery state machine");
diff --git a/drivers/power/stmp37xx/Makefile b/drivers/power/stmp37xx/Makefile
new file mode 100644
index 000000000000..65f670efdc93
--- /dev/null
+++ b/drivers/power/stmp37xx/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the STMP3xxx battery charger driver
+#
+
+obj-$(CONFIG_BATTERY_STMP3XXX) += stmp3xxx-battery.o
+
+stmp3xxx-battery-objs := ddi_bc_api.o ddi_bc_hw.o ddi_bc_init.o \
+		         ddi_bc_ramp.o ddi_bc_sm.o ddi_power_battery.o linux.o \
+			 fiq.o
+
diff --git a/drivers/power/stmp37xx/ddi_bc_api.c b/drivers/power/stmp37xx/ddi_bc_api.c
new file mode 100644
index 000000000000..5fd062ec4eb9
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_api.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file       ddi_bc_api.c
+//! \brief      Contains the Battery Charger API.
+//! \date       06/2005
+//!
+//! This file contains Battery Charger API.
+//!
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes
+////////////////////////////////////////////////////////////////////////////////
+
+#include "ddi_bc_internal.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+//! This structure holds the current Battery Charger configuration.
+
+ddi_bc_Cfg_t g_ddi_bc_Configuration;
+
+extern uint32_t g_ddi_bc_u32StateTimer;
+extern ddi_bc_BrokenReason_t ddi_bc_gBrokenReason;
+extern bool bRestartChargeCycle;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the Battery Charger configuration.
+//!
+//! \fntype Function
+//!
+//! This function reports the Battery Charger configuration.
+//!
+//! Note that, if the Battery Charger has not yet been initialized, the data
+//! returned by this function is unknown.
+//!
+//! \param[in,out]  pCfg  A pointer to a structure that will receive the data.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_QueryCfg(ddi_bc_Cfg_t * pCfg)
+{
+
+	//--------------------------------------------------------------------------
+	// Return the current configuration.
+	//--------------------------------------------------------------------------
+
+	*pCfg = g_ddi_bc_Configuration;
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Shut down the Battery Charger.
+//!
+//! \fntype Function
+//!
+//! This function immediately shuts down the Battery Charger hardware and
+//! returns the state machine to the Uninitialized state. Use this function to
+//! safely “mummify” the battery charger before retiring it from memory.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_ShutDown()
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the current ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Move to the Uninitialized state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED;
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Advances the state machine.
+//!
+//! \fntype Function
+//!
+//! This function advances the state machine.
+//!
+//! \retval DDI_BC_STATUS_SUCCESS          If all goes well
+//! \retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//! \retval DDI_BC_STATUS_BROKEN           If the battery violated a time-out
+//!                                        and has been declared broken.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_StateMachine()
+{
+
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// Execute the function for the current state.
+	//--------------------------------------------------------------------------
+
+	return (stateFunctionTable[g_ddi_bc_State] ());
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Get the Battery Charger's current state.
+//!
+//! \fntype Function
+//!
+//! This function returns the current state.
+//!
+//! \retval The current state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_State_t ddi_bc_GetState()
+{
+	//--------------------------------------------------------------------------
+	// Return the current state.
+	//--------------------------------------------------------------------------
+
+	return (g_ddi_bc_State);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Disable the Battery Charger.
+//!
+//! \fntype Function
+//!
+//! This function forces the Battery Charger into the Disabled state.
+//!
+//! \retval DDI_BC_STATUS_SUCCESS          If all goes well
+//! \retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_SetDisable()
+{
+
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_BROKEN) {
+		return (DDI_BC_STATUS_BROKEN);
+	}
+	//--------------------------------------------------------------------------
+	// Reset the current ramp. This will jam the current to zero and power off
+	// the charging hardware.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Move to the Disabled state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Enable the Battery Charger.
+//!
+//! \fntype Function
+//!
+//! If the Battery Charger is in the Disabled state, this function moves it to
+//! the Waiting to Charge state.
+//!
+//! \retval DDI_BC_STATUS_SUCCESS          If all goes well
+//! \retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//! \retval DDI_BC_STATUS_NOT_DISABLED     If the Battery Charger is not
+//!                                        disabled.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_SetEnable()
+{
+
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// If we're not in the Disabled state, this is pointless.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State != DDI_BC_STATE_DISABLED) {
+		return (DDI_BC_STATUS_NOT_DISABLED);
+	}
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+	//--------------------------------------------------------------------------
+	// Move to the Waiting to Charge state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Declare the battery to be broken.
+//!
+//! \fntype Function
+//!
+//! This function forces the Battery Charger into the Broken state.
+//!
+//! \retval DDI_BC_STATUS_SUCCESS          If all goes well
+//! \retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_SetBroken()
+{
+
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// Reset the current ramp. This will jam the current to zero and power off
+	// the charging hardware.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Move to the Broken state.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+	g_ddi_bc_State = DDI_BC_STATE_BROKEN;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Declare the battery to be fixed.
+//!
+//! \fntype Function
+//!
+//! If the Battery Charger is in the Broken state, this function moves it to
+//! the Disabled state.
+//!
+//! \retval DDI_BC_STATUS_SUCCESS          If all goes well
+//! \retval DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//! \retval DDI_BC_STATUS_NOT_BROKEN       If the Battery Charger is not broken.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_SetFixed()
+{
+
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// If we're not in the Broken state, this is pointless.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State != DDI_BC_STATE_BROKEN) {
+		return (DDI_BC_STATUS_NOT_BROKEN);
+	}
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Unitialize the Broken Reason
+	//--------------------------------------------------------------------------
+
+	ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED;
+
+	//--------------------------------------------------------------------------
+	// Move to the Disabled state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the current limit.
+//!
+//! \fntype Function
+//!
+//! This function applies a limit to the current that the Battery Charger can
+//! draw.
+//!
+//! \param[in]  u16Limit  The maximum current the Battery Charger can draw
+//!                       (in mA).
+//!
+//! \retval  The expressible version of the limit.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit)
+{
+
+	//--------------------------------------------------------------------------
+	// Set the limit and return what is actually expressible.
+	//--------------------------------------------------------------------------
+
+	return (ddi_bc_RampSetLimit(u16Limit));
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the current limit.
+//!
+//! \fntype Function
+//!
+//! This function reports the limit to the current that the Battery Charger can
+//! draw.
+//!
+//! \retval  The current limit.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_GetCurrentLimit(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Set the limit and return what is actually expressible.
+	//--------------------------------------------------------------------------
+
+	return (ddi_bc_RampGetLimit());
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the battery charger state machine period.
+//!
+//! \fntype Function
+//!
+//! This function sets a new state machine period.  The Period and Slope should
+//! be coordinated to achieve the minimal ramp step current which will minimize
+//! transients on the system.
+//!
+//! \param[in]  u32StateMachinePeriod  (in milliseconds)
+//! \param[in]  u16CurrentRampSlope (in mA/s)
+//!
+//! \retval SUCCESS                        If all goes well
+//! \retval ERROR_DDI_BCM_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                        initialized.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t u32StateMachinePeriod,
+					    uint16_t u16CurrentRampSlope)
+{
+	//--------------------------------------------------------------------------
+	// Check if we've been initialized yet.
+	//--------------------------------------------------------------------------
+	bool bDisableRequired;
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+
+	if (g_ddi_bc_State == DDI_BC_STATE_DISABLED)
+		bDisableRequired = false;
+	else {
+		bDisableRequired = true;
+		ddi_bc_SetDisable();
+	}
+
+	// Looking at the code, changing the period while the battery charger is running
+	// doesn't seem to have a negative affect.  One could wrap this in the mutex
+	// or implement further coordination if it did.
+	g_ddi_bc_Configuration.u32StateMachinePeriod = u32StateMachinePeriod;
+	g_ddi_bc_Configuration.u16CurrentRampSlope = u16CurrentRampSlope;
+
+	if (bDisableRequired)
+		ddi_bc_SetEnable();
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the state machine period.
+//!
+//! \fntype Function
+//!
+//! This function reports the battery charger period.
+//!
+//! \retval  The battery charger period (in milliseconds).
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint32_t ddi_bc_GetStateMachinePeriod()
+{
+	return (g_ddi_bc_Configuration.u32StateMachinePeriod);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the current ramp slope.
+//!
+//! \fntype Function
+//!
+//! This function reports the current ramp slope.
+//!
+//! \retval  The current ramp slope (in mA/s).
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint32_t ddi_bc_GetCurrentRampSlope()
+{
+	return (g_ddi_bc_Configuration.u16CurrentRampSlope);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the time spent in the present state (milliseconds)
+//!
+//! \fntype Function
+//!
+//! This function reports the time spent in the present charging state.  Note that
+//! for the states that actually charge the battery, this time does not include the
+//! time spent under alarm conditions such as die termperature alarm or battery
+//! temperature alarm.
+//!
+//! \retval  The time spent in the current state in milliseconds.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint32_t ddi_bc_GetStateTime(void)
+{
+	return g_ddi_bc_u32StateTimer;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the reason for being in the broken state
+//!
+//! \fntype Function
+//!
+//!
+//! \retval  ddi_bc_BrokenReason_t enumeration
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void)
+{
+	return ddi_bc_gBrokenReason;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Restart the charge cycle
+//!
+//! \fntype Function
+//!
+//!
+//! \retval  SUCCESS
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_ForceChargingToStart(void)
+{
+	static int16_t restarts = 0;
+
+	if (restarts < DDI_BC_MAX_RESTART_CYCLES) {
+		restarts++;
+		bRestartChargeCycle = true;
+	}
+
+	return (DDI_BC_STATUS_SUCCESS);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_hw.c b/drivers/power/stmp37xx/ddi_bc_hw.c
new file mode 100644
index 000000000000..71b170021cb0
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_hw.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ddi_bc_internal.h"
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file       ddi_bc_hw.c
+//! \brief      Contains the Battery Charger hardware operations.
+//! \date       06/2005
+//!
+//! This file contains Battery Charger hardware operations.
+//!
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes and external references
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report if the battery charging hardware is available.
+//!
+//! \fntype Function
+//!
+//! This function reports if the battery charging hardware is available by
+//! reading the corresponding laser fuse bit.
+//!
+//! \retval  Zero if the battery charging hardware is not available. Non-zero
+//!          otherwise.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_hwBatteryChargerIsEnabled(void)
+{
+	//TODO: replace ddi_bc_hwBatteryChargerIsEnabled with the function below in the code
+	return (int)ddi_power_GetBatteryChargerEnabled();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the battery configuration.
+//!
+//! \fntype Function
+//!
+//! This function reports the hardware battery configuration.
+//!
+//! \retval  A value that indicates the battery configuration.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void)
+{
+	//TODO: replace ddi_bc_hwGetBatteryMode() with the function below.
+	return (ddi_bc_BatteryMode_t) ddi_power_GetBatteryMode();
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the voltage across the battery.
+//!
+//! \fntype Function
+//!
+//! This function reports the voltage across the battery.
+//!
+//! \retval The voltage across the battery, in mV.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwGetBatteryVoltage(void)
+{
+	//TODO: replace ddi_bc_hwGetBattery with function below
+	return ddi_power_GetBattery();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report on the presence of the power supply.
+//!
+//! \fntype Function
+//!
+//! This function repots on whether or not the 5V power supply is present.
+//!
+//! \retval  Zero if the power supply is not present. Non-zero otherwise.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_hwPowerSupplyIsPresent(void)
+{
+	// TODO: replace ddi_bc_hwPowerSupplyIsPresent with the functino below.
+	return (int)ddi_power_Get5vPresentFlag();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the maximum charging current.
+//!
+//! \fntype Function
+//!
+//! This function reports the maximum charging current that will be offered to
+//! the battery, as currently set in the hardware.
+//!
+//! \retval  The maximum current setting in the hardware.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwGetMaxCurrent(void)
+{
+	// TODO: replace ddi_bc_hwGetMaxCurrent() with the below function
+	return (uint16_t) ddi_power_GetMaxBatteryChargeCurrent();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the maximum charging current.
+//!
+//! \fntype Function
+//!
+//! This function sets the maximum charging current that will be offered to the
+//! battery.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 780mA (see the data sheet for details). If the given
+//! current cannot be expressed exactly, then the largest expressible smaller
+//! value will be used. The return reports the actual value that was effected.
+//!
+//! \param[in]  u16Limit  The maximum charging current, in mA.
+//!
+//! \retval  The actual value that was effected.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwSetMaxCurrent(uint16_t u16Limit)
+{
+	//TODO: replace ddi_bc_hwSetMaxChargeCurrent
+	return ddi_power_SetMaxBatteryChargeCurrent(u16Limit);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the charging current threshold.
+//!
+//! \fntype Function
+//!
+//! This function sets the charging current threshold. When the actual current
+//! flow to the battery is less than this threshold, the HW_POWER_STS.CHRGSTS
+//! flag is clear.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 180mA (see the data sheet for details). If the given
+//! current cannot be expressed exactly, then the largest expressible smaller
+//! value will be used. The return reports the actual value that was effected.
+//!
+//! \param[in]  u16Threshold  The charging current threshold, in mA.
+//!
+//! \retval  The actual value that was effected.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t u16Threshold)
+{
+	//TODO: replace calls to ddi_bc_hwSetCurrentThreshold with the one below
+	return ddi_power_SetBatteryChargeCurrentThreshold(u16Threshold);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the charging current threshold.
+//!
+//! \fntype Function
+//!
+//! This function reports the charging current threshold. When the actual
+//! current flow to the battery is less than this threshold, the
+//! HW_POWER_STS.CHRGSTS flag is clear.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 180mA (see the data sheet for details).
+//!
+//! \retval  The charging current threshold, in mA.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwGetCurrentThreshold(void)
+{
+	//TODO: replace calls to ddi_bc_hwGetCurrentThreshold with function below
+	return ddi_power_GetBatteryChargeCurrentThreshold();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report if the charger hardware power is on.
+//!
+//! \fntype Function
+//!
+//! This function reports if the charger hardware power is on.
+//!
+//! \retval  Zero if the charger hardware is not powered. Non-zero otherwise.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_hwChargerPowerIsOn(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD"
+	// stands for "power down". Thus, when the bit is set, the battery charger
+	// hardware is POWERED DOWN.
+	//--------------------------------------------------------------------------
+
+	//--------------------------------------------------------------------------
+	// Read the register and return the result.
+	//--------------------------------------------------------------------------
+
+	//TODO: replace ddi_bc_hwChargerPowerIsOn with function below
+	return ddi_power_GetChargerPowered();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Turn the charging hardware on or off.
+//!
+//! \fntype Function
+//!
+//! This function turns the charging hardware on or off.
+//!
+//! \param[in]  on  Indicates whether the charging hardware should be on or off.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_hwSetChargerPower(int on)
+{
+
+	//--------------------------------------------------------------------------
+	// Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD"
+	// stands for "power down". Thus, when the bit is set, the battery charger
+	// hardware is POWERED DOWN.
+	//--------------------------------------------------------------------------
+
+	//--------------------------------------------------------------------------
+	// Hit the power switch.
+	//--------------------------------------------------------------------------
+
+	//TODO: replace ddi_bc_hwSetChargerPower with functino below
+	ddi_power_SetChargerPowered(on);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reports if the charging current has fallen below the threshold.
+//!
+//! \fntype Function
+//!
+//! This function reports if the charging current that the battery is accepting
+//! has fallen below the threshold.
+//!
+//! Note that this bit is regarded by the hardware guys as very slightly
+//! unreliable. They recommend that you don't believe a value of zero until
+//! you've sampled it twice.
+//!
+//! \retval  Zero if the battery is accepting less current than indicated by the
+//!          charging threshold. Non-zero otherwise.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_hwGetChargeStatus(void)
+{
+	return ddi_power_GetChargeStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report on the die temperature.
+//!
+//! \fntype Function
+//!
+//! This function reports on the die temperature.
+//!
+//! \param[out]  pLow   The low  end of the temperature range.
+//! \param[out]  pHigh  The high end of the temperature range.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_hwGetDieTemp(int16_t * pLow, int16_t * pHigh)
+{
+	// TODO: replace ddi_bc_hwGetDieTemp with function below
+	ddi_power_GetDieTemp(pLow, pHigh);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the battery temperature reading.
+//!
+//! \fntype Function
+//!
+//! This function examines the configured LRADC channel and reports the battery
+//! temperature reading.
+//!
+//! \param[out]  pReading  A pointer to a variable that will receive the
+//!                        temperature reading.
+//!
+//! \retval  DDI_BC_STATUS_SUCCESS          If the operation succeeded.
+//! \retval  DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                         initialized.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t * pReading)
+{
+	return (ddi_bc_Status_t)DDI_BC_STATUS_HARDWARE_DISABLED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Convert a current in mA to a hardware setting.
+//!
+//! \fntype Function
+//!
+//! This function converts a current measurement in mA to a hardware setting
+//! used by HW_POWER_BATTCHRG.STOP_ILIMIT or HW_POWER_BATTCHRG.BATTCHRG_I.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 780mA (see the data sheet for details). If the given
+//! current cannot be expressed exactly, then the largest expressible smaller
+//! value will be used.
+//!
+//! \param[in]  u16Current  The current of interest.
+//!
+//! \retval  The corresponding setting.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint8_t ddi_bc_hwCurrentToSetting(uint16_t u16Current)
+{
+	return ddi_power_convert_current_to_setting(u16Current);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Convert a hardware current setting to a value in mA.
+//!
+//! \fntype Function
+//!
+//! This function converts a setting used by HW_POWER_BATTCHRG.STOP_ILIMIT or
+//! HW_POWER_BATTCHRG.BATTCHRG_I into an actual current measurement in mA.
+//!
+//! Note that the hardware current fields are 6 bits wide. The higher bits in
+//! the 8-bit input parameter are ignored.
+//!
+//! \param[in]  u8Setting  A hardware current setting.
+//!
+//! \retval  The corresponding current in mA.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwSettingToCurrent(uint8_t u8Setting)
+{
+	return ddi_power_convert_setting_to_current(u8Setting);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Compute the actual current expressible in the hardware.
+//!
+//! \fntype Function
+//!
+//! Given a desired current, this function computes the actual current
+//! expressible in the hardware.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 780mA (see the data sheet for details). If the given
+//! current cannot be expressed exactly, then the largest expressible smaller
+//! value will be used.
+//!
+//! \param[in]  u16Current  The current of interest.
+//!
+//! \retval  The corresponding current in mA.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_hwExpressibleCurrent(uint16_t u16Current)
+{
+	//TODO: replace the bc function with this one
+	return ddi_power_ExpressibleCurrent(u16Current);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Checks to see if the DCDC has been manually enabled
+//!
+//! \fntype Function
+//!
+//! \retval  true if DCDC is ON, false if DCDC is OFF.
+//!
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_bc_hwIsDcdcOn(void)
+{
+	return ddi_power_IsDcdcOn();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_hw.h b/drivers/power/stmp37xx/ddi_bc_hw.h
new file mode 100644
index 000000000000..68ef98aa4303
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_hw.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file ddi_bc_hw.h
+//! \brief Internal header file for Battery Charger hardware operations.
+//! \date 06/2005
+//!
+//! This file contains internal declarations for Battery Charger hardware
+//! operations.
+//!
+//! \see ddi_bc.c and related files.
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _DDI_BC_HW_H
+#define _DDI_BC_HW_H
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! The enumeration of battery modes.
+
+typedef enum _ddi_bc_BatteryMode {
+	DDI_BC_BATTERY_MODE_LI_ION_2_CELLS = 0,
+	DDI_BC_BATTERY_MODE_LI_ION_1_CELL = 1,
+	DDI_BC_BATTERY_MODE_2_CELLS = 2,
+	DDI_BC_BATTERY_MODE_1_CELL = 3
+} ddi_bc_BatteryMode_t;
+
+//! The enumeration of bias current sources.
+
+typedef enum _ddi_bc_BiasCurrentSource {
+	DDI_BC_EXTERNAL_BIAS_CURRENT = 0,
+	DDI_BC_INTERNAL_BIAS_CURRENT = 1,
+} ddi_bc_BiasCurrentSource_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+extern int ddi_bc_hwBatteryChargerIsEnabled(void);
+extern ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void);
+extern ddi_bc_BiasCurrentSource_t ddi_bc_hwGetBiasCurrentSource(void);
+extern ddi_bc_Status_t
+ddi_bc_hwSetBiasCurrentSource(ddi_bc_BiasCurrentSource_t);
+extern ddi_bc_Status_t ddi_bc_hwSetChargingVoltage(uint16_t);
+extern uint16_t ddi_bc_hwGetBatteryVoltage(void);
+extern int ddi_bc_hwPowerSupplyIsPresent(void);
+extern uint16_t ddi_bc_hwSetMaxCurrent(uint16_t);
+extern uint16_t ddi_bc_hwGetMaxCurrent(void);
+extern uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t);
+extern uint16_t ddi_bc_hwGetCurrentThreshold(void);
+extern int ddi_bc_hwChargerPowerIsOn(void);
+extern void ddi_bc_hwSetChargerPower(int);
+extern int ddi_bc_hwGetChargeStatus(void);
+extern void ddi_bc_hwGetDieTemp(int16_t *, int16_t *);
+extern ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t *);
+uint8_t ddi_bc_hwCurrentToSetting(uint16_t);
+uint16_t ddi_bc_hwSettingToCurrent(uint8_t);
+uint16_t ddi_bc_hwExpressibleCurrent(uint16_t);
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Checks to see if the DCDC has been manually enabled
+//!
+//! \fntype Function
+//!
+//! \retval  true if DCDC is ON, false if DCDC is OFF.
+//!
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_bc_hwIsDcdcOn(void);
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+#endif				// _DDI_BC_H
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_init.c b/drivers/power/stmp37xx/ddi_bc_init.c
new file mode 100644
index 000000000000..246a35dcb3df
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_init.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ddi_bc_internal.h"
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file       ddi_bc_init.c
+//! \brief      Contains the Battery Charger initialization function.
+//! \date       06/2005
+//!
+//! This file contains Battery Charger initialization function.
+//!
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes and external references
+////////////////////////////////////////////////////////////////////////////////
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//! \brief Initialize the Battery Charger.
+//!
+//! \fntype Function
+//!
+//! This function initializes the Battery Charger.
+//!
+//! \param[in]  pCfg  A pointer to the new configuration.
+//!
+//! \retval  DDI_BC_STATUS_SUCCESS
+//!             If the operation succeeded.
+//! \retval  DDI_BC_STATUS_ALREADY_INITIALIZED
+//!             If the Battery Charger is already initialized.
+//! \retval  DDI_BC_STATUS_HARDWARE_DISABLED
+//!             If the Battery Charger hardware is disabled by a laser fuse.
+//! \retval  DDI_BC_STATUS_BAD_BATTERY_MODE
+//!             If the power supply is set up for a non-rechargeable battery.
+//! \retval  DDI_BC_STATUS_CLOCK_GATE_CLOSED
+//!             If the clock gate for the power supply registers is closed.
+//! \retval  DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE
+//!             If the charging voltage is not either 4100 or 4200.
+//! \retval  DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL
+//!             If the LRADC channel number for monitoring battery temperature
+//!             is bad.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t * pCfg)
+{
+
+	//--------------------------------------------------------------------------
+	// We can only be initialized if we're in the Uninitialized state.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State != DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_ALREADY_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// Check if the battery charger hardware has been disabled by laser fuse.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_power_GetBatteryChargerEnabled())
+		return (DDI_BC_STATUS_HARDWARE_DISABLED);
+
+	//--------------------------------------------------------------------------
+	// Check if the power supply has been set up for a non-rechargeable battery.
+	//--------------------------------------------------------------------------
+
+	switch (ddi_power_GetBatteryMode()) {
+
+	case DDI_POWER_BATT_MODE_LIION:
+		break;
+
+		// TODO: we'll need to do NiMH also
+	default:
+		return (DDI_BC_STATUS_BAD_BATTERY_MODE);
+		//break;
+
+	}
+
+	//--------------------------------------------------------------------------
+	// Make sure that the clock gate has been opened for the power supply
+	// registers. If not, then none of our writes to those registers will
+	// succeed, which will kind of slow us down...
+	//--------------------------------------------------------------------------
+
+	if (ddi_power_GetPowerClkGate()) {
+		return (DDI_BC_STATUS_CLOCK_GATE_CLOSED);
+	}
+	//--------------------------------------------------------------------------
+	// Check the incoming configuration for nonsense.
+	//--------------------------------------------------------------------------
+
+	//
+	// Only permitted charging voltage: 4200mV.
+	//
+
+	if (pCfg->u16ChargingVoltage != DDI_BC_LIION_CHARGING_VOLTAGE) {
+		return (DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE);
+	}
+	//
+	// There are 8 LRADC channels.
+	//
+
+	if (pCfg->u8BatteryTempChannel > 7) {
+		return (DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL);
+	}
+	//--------------------------------------------------------------------------
+	// Accept the configuration.
+	//--------------------------------------------------------------------------
+
+	//--------------------------------------------------------------------------
+	//  ddi_bc_Cfg_t.u16ChargingThresholdCurrent is destined for the
+	//  register field HW_POWER_BATTCHRG.STOP_ILIMIT.  This 4-bit field
+	//  is unevenly quantized to provide a useful range of currents.  A
+	//  side effect of the quantization is that the field can only be
+	//  set to certain unevenly-spaced values.
+	//
+	//  Here, we use the two functions that manipulate the register field
+	//  to adjust u16ChargingThresholdCurrent to match the quantized value.
+	//--------------------------------------------------------------------------
+	pCfg->u16ChargingThresholdCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16ChargingThresholdCurrent);
+
+	//--------------------------------------------------------------------------
+	//  ...similar situation with ddi_bc_Cfg_t.u16BatteryTempSafeCurrent and
+	//  u16DieTempSafeCurrent.
+	//--------------------------------------------------------------------------
+	pCfg->u16BatteryTempSafeCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16BatteryTempSafeCurrent);
+	pCfg->u16DieTempSafeCurrent =
+	    ddi_power_ExpressibleCurrent(pCfg->u16DieTempSafeCurrent);
+
+	g_ddi_bc_Configuration = *pCfg;
+
+	//--------------------------------------------------------------------------
+	// Turn the charger hardware off. This is a very important initial condition
+	// because we only flip the power switch on the hardware when we make
+	// transitions. Baseline, it needs to be off.
+	//--------------------------------------------------------------------------
+
+	ddi_power_SetChargerPowered(0);
+
+	//--------------------------------------------------------------------------
+	// Reset the current ramp. This will jam the current to zero and power off
+	// the charging hardware.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Move to the Disabled state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_DISABLED;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("%s: success\n", __func__);
+#endif
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_internal.h b/drivers/power/stmp37xx/ddi_bc_internal.h
new file mode 100644
index 000000000000..c1fb1b20f271
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_internal.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file ddi_bc_internal.h
+//! \brief Internal header file for the Battery Charger device driver.
+//! \date 06/2005
+//!
+//! This file contains internal declarations for the Battery Charger device
+//! driver.
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _DDI_BC_INTERNAL_H
+#define _DDI_BC_INTERNAL_H
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes
+////////////////////////////////////////////////////////////////////////////////
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_hw.h"
+#include "ddi_bc_ramp.h"
+#include "ddi_bc_sm.h"
+#include "ddi_power_battery.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+
+extern bool g_ddi_bc_Configured;
+extern ddi_bc_Cfg_t g_ddi_bc_Configuration;
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+#endif				// _DDI_BC_H
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_ramp.c b/drivers/power/stmp37xx/ddi_bc_ramp.c
new file mode 100644
index 000000000000..1de3a53259f8
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_ramp.c
@@ -0,0 +1,724 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file       ddi_bc_ramp.c
+//! \brief      Contains the Battery Charger current ramp controller.
+//! \date       06/2005
+//!
+//! This file contains Battery Charger current ramp controller.
+//!
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes and external references
+////////////////////////////////////////////////////////////////////////////////
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! This is the control structure for the current ramp.
+
+typedef struct _ddi_bc_RampControl {
+
+	uint32_t u32AccumulatedTime;
+
+	//!< The accumulated time since we last changed the actual
+	//!< current setting in the hardware. If the time between
+	//!< steps is quite short, we may have to wait for several steps
+	//!< before we can actually change the hardware setting.
+
+	uint16_t u16Target;
+
+	//!< The target current, regardless of expressibility.
+
+	uint16_t u16Limit;
+
+	//!< The current limit, regardless of expressibility.
+
+	uint8_t dieTempAlarm:1;
+
+	//!< Indicates if we are operating under a die temperature
+	//!< alarm.
+
+	uint8_t batteryTempAlarm:1;
+
+	//!< Indicates if we are operating under a battery temperature
+	//!< alarm.
+
+	uint8_t ambientTempAlarm:1;
+
+	//!< Indicates if we are operating under an ambient temperature
+	//!< alarm.
+
+} ddi_bc_RampControl_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+//! This structure contains control information for the current ramp.
+
+static ddi_bc_RampControl_t g_RampControl;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reset the current ramp.
+//!
+//! \fntype Function
+//!
+//! This function resets the current ramp.
+//!
+//! Note that this function does NOT reset the temperature alarms or the current
+//! limit. Those can only be changed explicitly.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_RampReset()
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the control structure.
+	//--------------------------------------------------------------------------
+
+	g_RampControl.u32AccumulatedTime = 0;
+	g_RampControl.u16Target = 0;
+
+	//--------------------------------------------------------------------------
+	// Step the ramp. Note that we don't care if this function returns an error.
+	// We're stepping the ramp to make sure it takes immediate effect, if
+	// possible. But, for example, if the Battery Charger is not yet
+	// initialized, it doesn't matter.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(0);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the target current.
+//!
+//! \fntype Function
+//!
+//! This function sets the target current and implements it immediately.
+//!
+//! Note that this function does NOT reset the temperature alarms. Those can
+//! only be reset explicitly.
+//!
+//! \param[in]  u16Target  The target current.
+//!
+//! \retval  The expressible version of the target.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_RampSetTarget(uint16_t u16Target)
+{
+
+	//--------------------------------------------------------------------------
+	// Set the target.
+	//--------------------------------------------------------------------------
+
+	g_RampControl.u16Target = u16Target;
+
+	//--------------------------------------------------------------------------
+	// Step the ramp. Note that we don't care if this function returns an error.
+	// We're stepping the ramp to make sure it takes immediate effect, if
+	// possible. But, for example, if the Battery Charger is not yet
+	// initialized, it doesn't matter.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(0);
+
+	//--------------------------------------------------------------------------
+	// Compute and return the expressible target.
+	//--------------------------------------------------------------------------
+
+	return (ddi_bc_hwExpressibleCurrent(u16Target));
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the target.
+//!
+//! \fntype Function
+//!
+//! This function reports the target.
+//!
+//! \retval  The target.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_RampGetTarget(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Return the target.
+	//--------------------------------------------------------------------------
+
+	return (g_RampControl.u16Target);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set the current limit.
+//!
+//! \fntype Function
+//!
+//! This function sets the current limit and implements it immediately.
+//!
+//! \param[in]  u16Limit  The current limit.
+//!
+//! \retval  The expressible version of the limit.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_RampSetLimit(uint16_t u16Limit)
+{
+
+	//--------------------------------------------------------------------------
+	// Set the limit.
+	//--------------------------------------------------------------------------
+
+	g_RampControl.u16Limit = u16Limit;
+
+	//--------------------------------------------------------------------------
+	// Step the ramp. Note that we don't care if this function returns an error.
+	// We're stepping the ramp to make sure it takes immediate effect, if
+	// possible. But, for example, if the Battery Charger is not yet
+	// initialized, it doesn't matter.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(0);
+
+	//--------------------------------------------------------------------------
+	// Compute and return the expressible limit.
+	//--------------------------------------------------------------------------
+
+	return (ddi_bc_hwExpressibleCurrent(u16Limit));
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the current limit.
+//!
+//! \fntype Function
+//!
+//! This function reports the current limit.
+//!
+//! \retval  The current limit.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_bc_RampGetLimit(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Return the current limit.
+	//--------------------------------------------------------------------------
+
+	return (g_RampControl.u16Limit);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Update alarms.
+//!
+//! \fntype Function
+//!
+//! This function checks for all alarms and updates the current ramp
+//! accordingly.
+//!
+////////////////////////////////////////////////////////////////////////////////
+void ddi_bc_RampUpdateAlarms()
+{
+
+	// Set to true if something changed and we need to step the ramp right away.
+
+	int iStepTheRamp = 0;
+
+	//--------------------------------------------------------------------------
+	// Are we monitoring die temperature?
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_Configuration.monitorDieTemp) {
+
+		//----------------------------------------------------------------------
+		// Get the die temperature range.
+		//----------------------------------------------------------------------
+
+		int16_t i16Low;
+		int16_t i16High;
+
+		ddi_bc_hwGetDieTemp(&i16Low, &i16High);
+
+		//----------------------------------------------------------------------
+		// Now we need to decide if it's time to raise or lower the alarm. The
+		// first question to ask is: Were we already under an alarm?
+		//----------------------------------------------------------------------
+
+		if (g_RampControl.dieTempAlarm) {
+
+			//------------------------------------------------------------------
+			// If control arrives here, we were already under an alarm. We'll
+			// change that if the high end of the temperature range drops below
+			// the low temperature mark.
+			//------------------------------------------------------------------
+
+			if (i16High < g_ddi_bc_Configuration.u8DieTempLow) {
+
+				//--------------------------------------------------------------
+				// If control arrives here, we're safe now. Drop the alarm.
+				//--------------------------------------------------------------
+
+				g_RampControl.dieTempAlarm = 0;
+
+				iStepTheRamp = !0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				printk("Battery charger: releasing "
+				       "die temp alarm: [%d, %d] < %d\r\n",
+				       (int32_t) i16Low, (int32_t) i16High,
+				       (int32_t) g_ddi_bc_Configuration.
+				       u8DieTempLow);
+#endif
+
+			}
+
+		} else {
+
+			//------------------------------------------------------------------
+			// If control arrives here, we were not under an alarm. We'll change
+			// that if the high end of the temperature range rises above the
+			// high temperature mark.
+			//------------------------------------------------------------------
+
+			if (i16High >= g_ddi_bc_Configuration.u8DieTempHigh) {
+
+				//--------------------------------------------------------------
+				// If control arrives here, we're running too hot. Raise the
+				// alarm.
+				//--------------------------------------------------------------
+
+				g_RampControl.dieTempAlarm = 1;
+
+				iStepTheRamp = !0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				printk("Battery charger: declaring "
+				       "die temp alarm: [%d, %d] >= %d\r\n",
+				       (int32_t) i16Low, (int32_t) i16High,
+				       (int32_t) g_ddi_bc_Configuration.
+				       u8DieTempLow);
+#endif
+			}
+
+		}
+
+	}
+	//--------------------------------------------------------------------------
+	// Are we monitoring battery temperature?
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_Configuration.monitorBatteryTemp) {
+
+		ddi_bc_Status_t status;
+
+		//----------------------------------------------------------------------
+		// Get the battery temperature reading.
+		//----------------------------------------------------------------------
+
+		uint16_t u16Reading;
+
+		status = ddi_bc_hwGetBatteryTemp(&u16Reading);
+
+		//----------------------------------------------------------------------
+		// If there was a problem, then we ignore the reading. Otherwise, let's
+		// have a look.
+		//----------------------------------------------------------------------
+
+		if (status == DDI_BC_STATUS_SUCCESS) {
+
+			//------------------------------------------------------------------
+			// Now we need to decide if it's time to raise or lower the alarm.
+			// The first question to ask is: Were we already under an alarm?
+			//------------------------------------------------------------------
+
+			if (g_RampControl.batteryTempAlarm) {
+
+				//--------------------------------------------------------------
+				// If control arrives here, we were already under an alarm.
+				// We'll change that if the reading drops below the low mark.
+				//--------------------------------------------------------------
+
+				if (u16Reading <
+				    g_ddi_bc_Configuration.u16BatteryTempLow) {
+
+					//----------------------------------------------------------
+					// If control arrives here, we're safe now. Drop the alarm.
+					//----------------------------------------------------------
+
+					g_RampControl.batteryTempAlarm = 0;
+
+					iStepTheRamp = !0;
+
+				}
+
+			} else {
+
+				//--------------------------------------------------------------
+				// If control arrives here, we were not under an alarm. We'll
+				// change that if the reading rises above the high mark.
+				//--------------------------------------------------------------
+
+				if (u16Reading >=
+				    g_ddi_bc_Configuration.u16BatteryTempHigh) {
+
+					//----------------------------------------------------------
+					// If control arrives here, we're running too hot. Raise the
+					// alarm.
+					//----------------------------------------------------------
+
+					g_RampControl.batteryTempAlarm = 1;
+
+					iStepTheRamp = !0;
+
+				}
+
+			}
+
+		}
+
+	}
+	//--------------------------------------------------------------------------
+	// Do we need to step the ramp?
+	//--------------------------------------------------------------------------
+
+	if (iStepTheRamp)
+		ddi_bc_RampStep(0);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reports the state of the die temperature alarm.
+//!
+//! \fntype Function
+//!
+//! This function reports the state of the die temperature alarm.
+//!
+//! \retval  The state of the die temperature alarm.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_RampGetDieTempAlarm(void)
+{
+	return (g_RampControl.dieTempAlarm);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reports the state of the battery temperature alarm.
+//!
+//! \fntype Function
+//!
+//! This function reports the state of the battery temperature alarm.
+//!
+//! \retval  The state of the battery temperature alarm.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_RampGetBatteryTempAlarm(void)
+{
+	return (g_RampControl.batteryTempAlarm);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reports the state of the ambient temperature alarm.
+//!
+//! \fntype Function
+//!
+//! This function reports the state of the ambient temperature alarm.
+//!
+//! \retval  The state of the ambient temperature alarm.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_bc_RampGetAmbientTempAlarm(void)
+{
+	return (g_RampControl.ambientTempAlarm);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Step the current ramp.
+//!
+//! \fntype Function
+//!
+//! This function steps the current ramp forward through the given amount of time.
+//!
+//! \param[in] u32Time  The time increment to add.
+//!
+//! \retval  DDI_BC_STATUS_SUCCESS          If the operation succeeded.
+//! \retval  DDI_BC_STATUS_NOT_INITIALIZED  If the Battery Charger is not yet
+//!                                         initialized.
+//!
+////////////////////////////////////////////////////////////////////////////////
+ddi_bc_Status_t ddi_bc_RampStep(uint32_t u32Time)
+{
+
+	uint16_t u16MaxNow;
+	uint16_t u16Target;
+	uint16_t u16Cart;
+	int32_t i32Delta;
+
+	//--------------------------------------------------------------------------
+	// Make sure the Battery Charger is initialized.
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) {
+		return (DDI_BC_STATUS_NOT_INITIALIZED);
+	}
+	//--------------------------------------------------------------------------
+	// Figure out how much current the hardware is set to draw right now.
+	//--------------------------------------------------------------------------
+
+	u16MaxNow = ddi_bc_hwGetMaxCurrent();
+
+	//--------------------------------------------------------------------------
+	// Start with the target.
+	//--------------------------------------------------------------------------
+
+	u16Target = g_RampControl.u16Target;
+
+	//--------------------------------------------------------------------------
+	// Check the target against the hard limit.
+	//--------------------------------------------------------------------------
+
+	if (u16Target > g_RampControl.u16Limit)
+		u16Target = g_RampControl.u16Limit;
+
+	//--------------------------------------------------------------------------
+	// Check if the die temperature alarm is active.
+	//--------------------------------------------------------------------------
+
+	if (g_RampControl.dieTempAlarm) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we are under a die temperature alarm. Clamp
+		// the target current.
+		//----------------------------------------------------------------------
+
+		if (u16Target > g_ddi_bc_Configuration.u16DieTempSafeCurrent) {
+			u16Target =
+			    g_ddi_bc_Configuration.u16DieTempSafeCurrent;
+		}
+
+	}
+	//--------------------------------------------------------------------------
+	// Check if the battery temperature alarm is active.
+	//--------------------------------------------------------------------------
+
+	if (g_RampControl.batteryTempAlarm) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we are under a battery temperature alarm.
+		// Clamp the target current.
+		//----------------------------------------------------------------------
+
+		if (u16Target >
+		    g_ddi_bc_Configuration.u16BatteryTempSafeCurrent) {
+			u16Target =
+			    g_ddi_bc_Configuration.u16BatteryTempSafeCurrent;
+		}
+
+	}
+	//--------------------------------------------------------------------------
+	// Now we know the target current. Figure out what is actually expressible
+	// in the hardware.
+	//--------------------------------------------------------------------------
+
+	u16Target = ddi_bc_hwExpressibleCurrent(u16Target);
+
+	//--------------------------------------------------------------------------
+	// Compute the difference between the expressible target and what's actually
+	// set in the hardware right now.
+	//--------------------------------------------------------------------------
+
+	i32Delta = ((int32_t) u16Target) - ((int32_t) u16MaxNow);
+
+	//--------------------------------------------------------------------------
+	// Check if the delta is zero.
+	//--------------------------------------------------------------------------
+
+	if (i32Delta == 0) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, there is no difference between what we want
+		// and what's set in the hardware.
+		//
+		// Before we leave, though, we don't want to leave any accumulated time
+		// laying around for the next ramp up. Zero it out.
+		//----------------------------------------------------------------------
+
+		g_RampControl.u32AccumulatedTime = 0;
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+	//--------------------------------------------------------------------------
+	// Check if the delta is negative.
+	//--------------------------------------------------------------------------
+
+	if (i32Delta < 0) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the new target is lower than what's
+		// currently set in the hardware. Since that means we're *reducing* the
+		// current draw, we can do it right now. Just gimme a sec here...
+		//----------------------------------------------------------------------
+
+		ddi_bc_hwSetMaxCurrent(u16Target);
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+		printk("Battery charger: setting max charge "
+		       "current to: %hdmA\r\n", u16Target);
+#endif
+
+		//----------------------------------------------------------------------
+		// Flip the power switch on the charging hardware according to the new
+		// current setting.
+		//----------------------------------------------------------------------
+
+		ddi_bc_hwSetChargerPower(u16Target != 0);
+
+		//----------------------------------------------------------------------
+		// We don't want to leave any accumulated time laying around for the
+		// next ramp up. Zero it out.
+		//----------------------------------------------------------------------
+
+		g_RampControl.u32AccumulatedTime = 0;
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, the target current is higher than what's set in
+	// the hardware right now. That means we're going to ramp it up. To do that,
+	// we're going to "buy" more milliamps by "spending" milliseconds of time.
+	// Add the time we've "banked" to the time we've been credited in this call.
+	//--------------------------------------------------------------------------
+
+	u32Time += g_RampControl.u32AccumulatedTime;
+
+	//--------------------------------------------------------------------------
+	// Now we know how much we can spend. How much current will it buy?
+	//--------------------------------------------------------------------------
+
+	u16Cart = (g_ddi_bc_Configuration.u16CurrentRampSlope * u32Time) / 1000;
+
+	//--------------------------------------------------------------------------
+	// Check how the current we can afford stacks up against the target we want.
+	//--------------------------------------------------------------------------
+
+	if ((u16MaxNow + u16Cart) < u16Target) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we can't afford to buy all the current we
+		// want. Compute the maximum we can afford, and then figure out what we
+		// can actually express in the hardware.
+		//----------------------------------------------------------------------
+
+		u16Target = ddi_bc_hwExpressibleCurrent(u16MaxNow + u16Cart);
+
+		//----------------------------------------------------------------------
+		// Check if the result isn't actually different from what's set in the
+		// the hardware right now.
+		//----------------------------------------------------------------------
+
+		if (u16Target == u16MaxNow) {
+
+			//------------------------------------------------------------------
+			// If control arrives here, we are so poor that we can't yet afford
+			// to buy enough current to make a change in the expressible
+			// hardware setting. Since we didn't spend any of our time, put the
+			// new balance back in the bank.
+			//------------------------------------------------------------------
+
+			g_RampControl.u32AccumulatedTime = u32Time;
+
+			//------------------------------------------------------------------
+			// Leave dispiritedly.
+			//------------------------------------------------------------------
+
+			return (DDI_BC_STATUS_SUCCESS);
+
+		}
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we can afford to buy enough current to get us
+	// all the way to the target. Set it.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_hwSetMaxCurrent(u16Target);
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: setting max charge"
+	       "current to: %hdmA\r\n", u16Target);
+#endif
+
+	//--------------------------------------------------------------------------
+	// Flip the power switch on the charging hardware according to the new
+	// current setting.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_hwSetChargerPower(u16Target != 0);
+
+	//--------------------------------------------------------------------------
+	// We're at the target, so we're finished buying current. Zero out the
+	// account.
+	//--------------------------------------------------------------------------
+
+	g_RampControl.u32AccumulatedTime = 0;
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_ramp.h b/drivers/power/stmp37xx/ddi_bc_ramp.h
new file mode 100644
index 000000000000..5111a5496fcf
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_ramp.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file ddi_bc_ramp.h
+//! \brief Internal header file for Battery Charger current ramp controller.
+//! \date 06/2005
+//!
+//! This file contains internal declarations for Battery current ramp
+//! controller.
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _DDI_BC_RAMP_H
+#define _DDI_BC_RAMP_H
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+extern void ddi_bc_RampReset(void);
+extern uint16_t ddi_bc_RampSetTarget(uint16_t);
+extern uint16_t ddi_bc_RampGetTarget(void);
+extern uint16_t ddi_bc_RampSetLimit(uint16_t);
+extern uint16_t ddi_bc_RampGetLimit(void);
+extern void ddi_bc_RampUpdateAlarms(void);
+extern int ddi_bc_RampGetDieTempAlarm(void);
+extern int ddi_bc_RampGetBatteryTempAlarm(void);
+extern int ddi_bc_RampGetAmbientTempAlarm(void);
+extern ddi_bc_Status_t ddi_bc_RampStep(uint32_t);
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+#endif				// _DDI_BC_H
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_sm.c b/drivers/power/stmp37xx/ddi_bc_sm.c
new file mode 100644
index 000000000000..c4175688d9ab
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_sm.c
@@ -0,0 +1,916 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file       ddi_bc_sm.c
+//! \brief      Contains the Battery Charger state machine.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Includes
+////////////////////////////////////////////////////////////////////////////////
+
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+
+#include <linux/delay.h>
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+// This is the minimum time we must charge before we transition from
+// the charging state to the topping off. If we reach the
+// u16ChargingThresholdCurrent charge curent before then, the battery was
+// already full so we can avoid the risk of charging it past .1C for
+// too long.
+
+#define TRANSITION_TO_TOPOFF_MINIMUM_CHARGE_TIME_mS 1 * 60 * 1000	// 1 minute
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+// The current state.
+
+ddi_bc_State_t g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED;
+
+// This table contains pointers to the functions that implement states. The
+// table is indexed by state. Note that it's critically important for this
+// table to agree with the state enumeration in ddi_bc.h.
+
+static ddi_bc_Status_t ddi_bc_Uninitialized(void);
+static ddi_bc_Status_t ddi_bc_Broken(void);
+static ddi_bc_Status_t ddi_bc_Disabled(void);
+static ddi_bc_Status_t ddi_bc_WaitingToCharge(void);
+static ddi_bc_Status_t ddi_bc_Conditioning(void);
+static ddi_bc_Status_t ddi_bc_Charging(void);
+static ddi_bc_Status_t ddi_bc_ToppingOff(void);
+
+
+ddi_bc_Status_t(*const (stateFunctionTable[])) (void) = {
+ddi_bc_Uninitialized,
+	    ddi_bc_Broken,
+	    ddi_bc_Disabled,
+	    ddi_bc_WaitingToCharge,
+	    ddi_bc_Conditioning,
+	    ddi_bc_Charging, ddi_bc_ToppingOff};
+
+// Used by states that need to watch the time.
+uint32_t g_ddi_bc_u32StateTimer = 0;
+
+/* Always attempt to charge on first 5V connection */
+bool bRestartChargeCycle = true;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+static uint16_t u16ExternalBatteryPowerVoltageCheck = 0;
+#endif
+
+ddi_bc_BrokenReason_t ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Transition to the Waiting to Charge state.
+//!
+//! \fntype Function
+//!
+//! This function implements the transition to the Waiting to Charge state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static void TransitionToWaitingToCharge(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Reset the current ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Move to the Waiting to Charge state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now waiting to charge\n");
+#endif
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Transition to the Conditioning state.
+//!
+//! \fntype Function
+//!
+//! This function implements the transition to the Conditioning state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static void TransitionToConditioning(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Set up the current ramp for conditioning.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ConditioningCurrent);
+
+	//--------------------------------------------------------------------------
+	// Move to the Conditioning state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_CONDITIONING;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now conditioning\n");
+#endif
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Transition to the Charging state.
+//!
+//! \fntype Function
+//!
+//! This function implements the transition to the Charging state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static void TransitionToCharging(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Set up the current ramp for charging.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent);
+
+	//--------------------------------------------------------------------------
+	// We'll be finished charging when the current flow drops below this level.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration.
+				     u16ChargingThresholdCurrent);
+
+	//--------------------------------------------------------------------------
+	// Move to the Charging state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_CHARGING;
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now charging\n");
+#endif
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Transition to the Topping Off state.
+//!
+//! \fntype Function
+//!
+//! This function implements the transition to the Topping Off state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static void TransitionToToppingOff(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Set up the current ramp for topping off.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent);
+
+	//--------------------------------------------------------------------------
+	// Move to the Topping Off state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_TOPPING_OFF;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: now topping off\n");
+#endif
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Transition to the Broken state.
+//!
+//! \fntype Function
+//!
+//! This function implements the transition to the Broken state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static void TransitionToBroken(void)
+{
+
+	//--------------------------------------------------------------------------
+	// Reset the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer = 0;
+
+	//--------------------------------------------------------------------------
+	// Reset the current ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampReset();
+
+	//--------------------------------------------------------------------------
+	// Move to the Broken state.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_State = DDI_BC_STATE_BROKEN;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	printk("Battery charger: declaring a broken battery\n");
+#endif
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Uninitialized state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Uninitialized state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_Uninitialized(void)
+{
+
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// Increment the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	//--------------------------------------------------------------------------
+	// The only way to leave this state is with a call to ddi_bc_Initialize. So,
+	// calling this state function does nothing.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Broken state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Broken state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_Broken(void)
+{
+
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// Increment the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	//--------------------------------------------------------------------------
+	// The only way to leave this state is with a call to ddi_bc_SetFixed. So,
+	// calling this state function does nothing.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Disabled state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Disabled state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_Disabled(void)
+{
+
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// Increment the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	//--------------------------------------------------------------------------
+	// The only way to leave this state is with a call to ddi_bc_SetEnable. So,
+	// calling this state function does nothing.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Waitin to Charge state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Waiting to Charge state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_WaitingToCharge(void)
+{
+	uint16_t u16BatteryVoltage;
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// Increment the state timer.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	//--------------------------------------------------------------------------
+	// Check if the power supply is present. If not, we're not going anywhere.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+		u16ExternalBatteryPowerVoltageCheck = 0;
+#endif
+		return (DDI_BC_STATUS_SUCCESS);
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're connected to a power supply. Have a look
+	// at the battery voltage.
+	//--------------------------------------------------------------------------
+
+	u16BatteryVoltage = ddi_bc_hwGetBatteryVoltage();
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+	if (u16ExternalBatteryPowerVoltageCheck) {
+		if ((u16ExternalBatteryPowerVoltageCheck - u16BatteryVoltage) >
+		    300) {
+			/*
+			 * If control arrives here, battery voltage has
+			 * dropped too quickly after the first charge
+			 * cycle.  We think an external voltage regulator is
+			 * connected.
+			 */
+
+			ddi_bc_gBrokenReason =
+			    DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED;
+
+			TransitionToBroken();
+
+			//----------------------------------------------------------------------
+			// Tell our caller the battery appears to be broken.
+			//----------------------------------------------------------------------
+
+			return (DDI_BC_STATUS_BROKEN);
+		} else {
+			// reset this check
+			u16ExternalBatteryPowerVoltageCheck = 0;
+		}
+
+	}
+#endif
+
+
+	//--------------------------------------------------------------------------
+	// If the battery voltage isn't low, we don't need to be charging it. We
+	// use a 5% margin to decide.
+	//--------------------------------------------------------------------------
+
+	if (!bRestartChargeCycle) {
+		uint16_t x;
+
+		x = u16BatteryVoltage + (u16BatteryVoltage / 20);
+
+		if (x >= g_ddi_bc_Configuration.u16ChargingVoltage)
+			return (DDI_BC_STATUS_SUCCESS);
+
+	}
+
+	bRestartChargeCycle = false;
+	//--------------------------------------------------------------------------
+	// If control arrives here, the battery is low. How low?
+	//--------------------------------------------------------------------------
+
+	if (u16BatteryVoltage <
+	    g_ddi_bc_Configuration.u16ConditioningThresholdVoltage) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the battery is very low and it needs to be
+		// conditioned.
+		//----------------------------------------------------------------------
+
+		TransitionToConditioning();
+
+	} else {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the battery isn't too terribly low.
+		//----------------------------------------------------------------------
+
+		TransitionToCharging();
+
+	}
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Conditioning state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Conditioning state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_Conditioning(void)
+{
+
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// If we're not under an alarm, increment the state timer.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) {
+		g_ddi_bc_u32StateTimer +=
+		    g_ddi_bc_Configuration.u32StateMachinePeriod;
+	}
+	//--------------------------------------------------------------------------
+	// Check if the power supply is still around.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the power supply has been removed. Go back
+		// and wait.
+		//----------------------------------------------------------------------
+
+		TransitionToWaitingToCharge();
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're still connected to a power supply.
+	// Check if a battery is connected.  If the voltage rises to high with only
+	// conditioning charge current, we determine that a battery is not connected.
+	// If that is not the case and a battery is connected, check
+	// if the battery voltage indicates it still needs conditioning.
+	//--------------------------------------------------------------------------
+
+//	if (ddi_bc_hwGetBatteryVoltage() >= 3900) {
+	if ((ddi_bc_hwGetBatteryVoltage() >
+	     g_ddi_bc_Configuration.u16ConditioningMaxVoltage) &&
+	    (ddi_power_GetMaxBatteryChargeCurrent() <
+	     g_ddi_bc_Configuration.u16ConditioningCurrent)) {
+		//----------------------------------------------------------------------
+		// If control arrives here, voltage has risen too quickly for so
+		// little charge being applied so their must be no battery connected.
+		//----------------------------------------------------------------------
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_NO_BATTERY_DETECTED;
+
+		TransitionToBroken();
+
+		//----------------------------------------------------------------------
+		// Tell our caller the battery appears to be broken.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_BROKEN);
+
+	}
+
+	if (ddi_bc_hwGetBatteryVoltage() >=
+	    g_ddi_bc_Configuration.u16ConditioningMaxVoltage) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, this battery no longer needs conditioning.
+		//----------------------------------------------------------------------
+
+		TransitionToCharging();
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+	//--------------------------------------------------------------------------
+	// Have we been in this state too long?
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_u32StateTimer >=
+	    g_ddi_bc_Configuration.u32ConditioningTimeout) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we've been here too long.
+		//----------------------------------------------------------------------
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+		TransitionToBroken();
+
+		//----------------------------------------------------------------------
+		// Tell our caller the battery appears to be broken.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_BROKEN);
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're staying in this state. Step the current
+	// ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Charging state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Charging state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_Charging(void)
+{
+
+	//--------------------------------------------------------------------------
+	// This variable counts the number of times we've seen the charging status
+	// bit cleared.
+	//--------------------------------------------------------------------------
+
+	static int iStatusCount = 0;
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// If we're not under an alarm, increment the state timer.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) {
+		g_ddi_bc_u32StateTimer +=
+		    g_ddi_bc_Configuration.u32StateMachinePeriod;
+	}
+	/* Check if the power supply is still around. */
+
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the power supply has been removed. Go back
+		// and wait.
+		//----------------------------------------------------------------------
+
+		TransitionToWaitingToCharge();
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're still connected to a power supply. We need
+	// to decide now if the battery is still charging, or if it's nearly full.
+	// If it's still charging, we'll stay in this state. Otherwise, we'll move
+	// to the Topping Off state.
+	//
+	// Most of the time, we decide that the battery is still charging simply by
+	// checking if the the actual current flow is above the charging threshold
+	// current (as indicated by the charge status bit). However, if we're
+	// still ramping up to full charging current, the hardware may still be set
+	// to deliver an amount that's less than the threshold. In that case, the
+	// charging status bit would *definitely* show a low charging current, but
+	// that doesn't mean the battery is ready for topping off.
+	//
+	// So, in summary, we will move to the Topping Off state if both of the
+	// following are true:
+	//
+	//  1) The maximum current set in the hardware is greater than the charging
+	//     threshold.
+	//  -AND-
+	//  2) The actual current flow is also higher than the threshold (as
+	//     indicated by the charge status bit).
+	//
+	//--------------------------------------------------------------------------
+
+
+
+		ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration.
+					     u16ChargingThresholdCurrent);
+
+
+	{
+		uint16_t u16ActualProgrammedCurrent = ddi_bc_hwGetMaxCurrent();
+
+		//----------------------------------------------------------------------
+		// Get the Maximum current that we will ramp to.
+		//----------------------------------------------------------------------
+
+		//----------------------------------------------------------------------
+		// Not all possible values are expressible by the BATTCHRG_I bitfield.
+		// The following coverts the max current value into the the closest hardware
+		// expressible bitmask equivalent.  Then, it converts this back to the actual
+		// decimal current value that this bitmask represents.
+		//----------------------------------------------------------------------
+
+		uint16_t u16CurrentRampTarget = ddi_bc_RampGetTarget();
+
+		if (u16CurrentRampTarget > ddi_bc_RampGetLimit())
+			u16CurrentRampTarget = ddi_bc_RampGetLimit();
+
+		//----------------------------------------------------------------------
+		// Not all possible values are expressible by the BATTCHRG_I bitfield.
+		// The following coverts the max current value into the the closest hardware
+		// expressible bitmask equivalent.  Then, it converts this back to the actual
+		// decimal current value that this bitmask represents.
+		//----------------------------------------------------------------------
+
+		u16CurrentRampTarget =
+		    ddi_bc_hwExpressibleCurrent(u16CurrentRampTarget);
+
+		//----------------------------------------------------------------------
+		// We want to wait before we check the charge status bit until the ramping
+		// up is complete.  Because the charge status bit is noisy, we want to
+		// disregard it until the programmed charge currint in BATTCHRG_I is well
+		// beyond the STOP_ILIMIT value.
+		//----------------------------------------------------------------------
+		if ((u16ActualProgrammedCurrent >= u16CurrentRampTarget) &&
+		    !ddi_bc_hwGetChargeStatus()) {
+			uint8_t u8IlimitThresholdLimit;
+			//----------------------------------------------------------------------
+			// If control arrives here, the hardware flag is telling us that the
+			// charging current has fallen below the threshold. We need to see this
+			// happen twice consecutively before we believe it. Increment the count.
+			//----------------------------------------------------------------------
+
+			iStatusCount++;
+
+
+			u8IlimitThresholdLimit = 10;
+
+			//----------------------------------------------------------------------
+			// How many times in a row have we seen this status bit low?
+			//----------------------------------------------------------------------
+
+			if (iStatusCount >= u8IlimitThresholdLimit) {
+
+				/*
+				 * If control arrives here, we've seen the
+				 * CHRGSTS bit low too many times. This means
+				 * it's time to move to the Topping Off state.
+				 * First, reset the status count for the next
+				 * time we're in this state.
+				 */
+
+				iStatusCount = 0;
+
+#ifdef CONFIG_POWER_SUPPLY_DEBUG
+				u16ExternalBatteryPowerVoltageCheck =
+				    ddi_bc_hwGetBatteryVoltage();
+#endif
+
+
+
+				/* Move to the Topping Off state */
+
+
+				TransitionToToppingOff();
+
+				//------------------------------------------------------------------
+				// Return success.
+				//------------------------------------------------------------------
+
+				return (DDI_BC_STATUS_SUCCESS);
+
+			}
+
+		} else {
+
+			//----------------------------------------------------------------------
+			// If control arrives here, the battery is still charging. Clear the
+			// status count.
+			//----------------------------------------------------------------------
+
+			iStatusCount = 0;
+
+		}
+
+	}
+
+	//--------------------------------------------------------------------------
+	// Have we been in this state too long?
+	//--------------------------------------------------------------------------
+
+	if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32ChargingTimeout) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we've been here too long.
+		//----------------------------------------------------------------------
+
+		ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT;
+
+		TransitionToBroken();
+
+		//----------------------------------------------------------------------
+		// Tell our caller the battery appears to be broken.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_BROKEN);
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're staying in this state. Step the current
+	// ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Topping Off state function.
+//!
+//! \fntype Function
+//!
+//! This function implements the Topping Off state.
+//!
+////////////////////////////////////////////////////////////////////////////////
+static ddi_bc_Status_t ddi_bc_ToppingOff(void)
+{
+
+	//--------------------------------------------------------------------------
+	// The first order of business is to update alarms.
+
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampUpdateAlarms();
+
+	//--------------------------------------------------------------------------
+	// Increment the state timer. Notice that, unlike other states, we increment
+	// the state timer whether or not we're under an alarm.
+	//--------------------------------------------------------------------------
+
+	g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod;
+
+	//--------------------------------------------------------------------------
+	// Check if the power supply is still around.
+	//--------------------------------------------------------------------------
+
+	if (!ddi_bc_hwPowerSupplyIsPresent()) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, the power supply has been removed. Go back
+		// and wait.
+		//---------------------------------------------------------------------
+
+		TransitionToWaitingToCharge();
+
+		//----------------------------------------------------------------------
+		// Return success.
+		//----------------------------------------------------------------------
+
+		return (DDI_BC_STATUS_SUCCESS);
+
+	}
+
+	//--------------------------------------------------------------------------
+	// Are we done topping off?
+	//--------------------------------------------------------------------------
+	if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32TopOffPeriod) {
+
+		//----------------------------------------------------------------------
+		// If control arrives here, we're done topping off.
+		//----------------------------------------------------------------------
+
+		TransitionToWaitingToCharge();
+
+	}
+	//--------------------------------------------------------------------------
+	// If control arrives here, we're staying in this state. Step the current
+	// ramp.
+	//--------------------------------------------------------------------------
+
+	ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod);
+
+	//--------------------------------------------------------------------------
+	// Return success.
+	//--------------------------------------------------------------------------
+
+	return (DDI_BC_STATUS_SUCCESS);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_bc_sm.h b/drivers/power/stmp37xx/ddi_bc_sm.h
new file mode 100644
index 000000000000..0e5fd8a1f144
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_bc_sm.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_bc
+//! @{
+//
+// Copyright (c) 2004-2005 SigmaTel, Inc.
+//
+//! \file ddi_bc_sm.h
+//! \brief Header file for the Battery Charger state machine.
+//! \date 06/2005
+//!
+//! This file contains declarations for the Battery Charger state machine.
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _DDI_BC_SM_H
+#define _DDI_BC_SM_H
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+
+//! The current state.
+
+extern ddi_bc_State_t g_ddi_bc_State;
+
+//! The state function table.
+
+extern ddi_bc_Status_t(*const (stateFunctionTable[])) (void);
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+#endif				// _DDI_BC_H
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_power_battery.c b/drivers/power/stmp37xx/ddi_power_battery.c
new file mode 100644
index 000000000000..e2e46dd535a9
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_power_battery.c
@@ -0,0 +1,1815 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+//! \addtogroup ddi_power
+//! @{
+//
+// Copyright(C) 2005 SigmaTel, Inc.
+//
+//! \file ddi_power_battery.c
+//! \brief Implementation file for the power driver battery charger.
+//!
+////////////////////////////////////////////////////////////////////////////////
+//   Includes and external references
+////////////////////////////////////////////////////////////////////////////////
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <asm/processor.h> /* cpu_relax */
+#include <mach/platform.h>
+#include <mach/hardware.h>
+#include <mach/ddi_bc.h>
+#include <mach/lradc.h>
+#include <mach/regs-power.h>
+#include <mach/regs-lradc.h>
+#include <mach/lradc.h>
+#include "ddi_bc_internal.h"
+#include <mach/platform.h>
+
+//! \brief Base voltage to start battery calculations for LiIon
+#define BATT_BRWNOUT_LIION_BASE_MV 2800
+//! \brief Constant to help with determining whether to round up or
+//! not during calculation
+#define BATT_BRWNOUT_LIION_CEILING_OFFSET_MV 39
+//! \brief Number of mV to add if rounding up in LiIon mode
+#define BATT_BRWNOUT_LIION_LEVEL_STEP_MV 40
+//! \brief Constant value to be calculated by preprocessing
+#define BATT_BRWNOUT_LIION_EQN_CONST \
+	(BATT_BRWNOUT_LIION_BASE_MV - BATT_BRWNOUT_LIION_CEILING_OFFSET_MV)
+//! \brief Base voltage to start battery calculations for Alkaline/NiMH
+#define BATT_BRWNOUT_ALKAL_BASE_MV 800
+//! \brief Constant to help with determining whether to round up or
+//! not during calculation
+#define BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV 19
+//! \brief Number of mV to add if rounding up in Alkaline/NiMH mode
+#define BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV 20
+//! \brief Constant value to be calculated by preprocessing
+#define BATT_BRWNOUT_ALKAL_EQN_CONST \
+	(BATT_BRWNOUT_ALKAL_BASE_MV - BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV)
+
+#define GAIN_CORRECTION 1012    // 1.012
+
+#define VBUSVALID_THRESH_2_90V		0x0
+#define VBUSVALID_THRESH_4_00V		0x1
+#define VBUSVALID_THRESH_4_10V		0x2
+#define VBUSVALID_THRESH_4_20V		0x3
+#define VBUSVALID_THRESH_4_30V		0x4
+#define VBUSVALID_THRESH_4_40V		0x5
+#define VBUSVALID_THRESH_4_50V		0x6
+#define VBUSVALID_THRESH_4_60V		0x7
+
+#define LINREG_OFFSET_STEP_BELOW	0x2
+#define BP_POWER_BATTMONITOR_BATT_VAL	16
+#define BP_POWER_CHARGE_BATTCHRG_I	0
+#define BP_POWER_CHARGE_STOP_ILIMIT	8
+
+#define VDD4P2_ENABLED
+
+#define DDI_POWER_BATTERY_XFER_THRESHOLD_MV 3200
+
+
+#ifndef BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV
+#define BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV 4000
+#endif
+
+#ifndef BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV
+#define BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV 3800
+#endif
+
+/* #define DEBUG_IRQS */
+
+/* to be re-enabled once FIQ functionality is added */
+#define DISABLE_VDDIO_BO_PROTECTION
+////////////////////////////////////////////////////////////////////////////////
+// Globals & Variables
+////////////////////////////////////////////////////////////////////////////////
+
+
+/* Select your 5V Detection method */
+
+/* static ddi_power_5vDetection_t DetectionMethod =
+			DDI_POWER_5V_VDD5V_GT_VDDIO; */
+static ddi_power_5vDetection_t DetectionMethod = DDI_POWER_5V_VBUSVALID;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+#if 0
+static void dump_regs(void)
+{
+	printk("HW_POWER_CHARGE      0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE));
+	printk("HW_POWER_STS         0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_STS));
+	printk("HW_POWER_BATTMONITOR 0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR));
+}
+#endif
+
+//! This array maps bit numbers to current increments, as used in the register
+//! fields HW_POWER_CHARGE.STOP_ILIMIT and HW_POWER_CHARGE.BATTCHRG_I.
+static const uint16_t currentPerBit[] = {  10,  20,  50, 100, 200, 400 };
+
+uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current)
+{
+	int       i;
+	uint16_t  u16Mask;
+	uint16_t  u16Setting = 0;
+
+	// Scan across the bit field, adding in current increments.
+	u16Mask = (0x1 << 5);
+
+	for (i = 5; (i >= 0) && (u16Current > 0); i--, u16Mask >>= 1) {
+		if (u16Current >= currentPerBit[i]) {
+			u16Current -= currentPerBit[i];
+			u16Setting |= u16Mask;
+		}
+	}
+
+	// Return the result.
+	return(u16Setting);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! See hw_power.h for details.
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting)
+{
+	int       i;
+	uint16_t  u16Mask;
+	uint16_t  u16Current = 0;
+
+	// Scan across the bit field, adding in current increments.
+	u16Mask = (0x1 << 5);
+
+	for (i = 5; i >= 0; i--, u16Mask >>= 1) {
+		if (u16Setting & u16Mask) u16Current += currentPerBit[i];
+	}
+
+	// Return the result.
+	return(u16Current);
+}
+
+void ddi_power_Enable5vDetection(void)
+{
+	u32 val;
+	// Disable hardware power down when 5V is inserted or removed
+	__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	/* Enabling VBUSVALID hardware detection even if VDD5V_GT_VDDIO
+	 * is the detection method being used for 5V status (hardware
+	 * or software).  This is in case any other drivers (such as
+	 * USB) are specifically monitoring VBUSVALID status
+	 */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	// Set 5V detection threshold to 4.3V for VBUSVALID.
+	__raw_writel(
+		BF(VBUSVALID_THRESH_4_30V, POWER_5VCTRL_VBUSVALID_TRSH),
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	// gotta set LINREG_OFFSET to STEP_BELOW according to manual
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+	val &= ~(BM_POWER_VDDIOCTRL_LINREG_OFFSET);
+	val |= BF(LINREG_OFFSET_STEP_BELOW, POWER_VDDIOCTRL_LINREG_OFFSET);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL);
+	val &= ~(BM_POWER_VDDACTRL_LINREG_OFFSET);
+	val |= BF(LINREG_OFFSET_STEP_BELOW, POWER_VDDACTRL_LINREG_OFFSET);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDACTRL);
+
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+	val &= ~(BM_POWER_VDDDCTRL_LINREG_OFFSET);
+	val |= BF(LINREG_OFFSET_STEP_BELOW, POWER_VDDDCTRL_LINREG_OFFSET);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	/* enable vbusvalid irq */
+
+
+	/* enable 5V Detection interrupt vbusvalid irq */
+	switch (DetectionMethod) {
+	case DDI_POWER_5V_VBUSVALID:
+		/* Check VBUSVALID for 5V present */
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+		break;
+	case DDI_POWER_5V_VDD5V_GT_VDDIO:
+		/* Check VDD5V_GT_VDDIO for 5V present */
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+		break;
+	}
+}
+
+/*
+ * This function prepares the hardware for a 5V-to-battery handoff. It assumes
+ * the current configuration is using 5V as the power source.  The 5V
+ * interrupt will be set up for a 5V removal.
+ */
+void ddi_power_enable_5v_to_battery_handoff(void)
+{
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* detect 5v unplug */
+	__raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+#ifndef VDD4P2_ENABLED
+	// Enable automatic transition to DCDC
+	__raw_writel(BM_POWER_5VCTRL_DCDC_XFER,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+}
+
+/*
+ * This function will handle all the power rail transitions necesarry to power
+ * the chip from the battery when it was previously powered from the 5V power
+ * source.
+ */
+void ddi_power_execute_5v_to_battery_handoff(void)
+{
+	int val;
+#ifdef VDD4P2_ENABLED
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2);
+	val &= ~(BM_POWER_DCDC4P2_ENABLE_DCDC | BM_POWER_DCDC4P2_ENABLE_4P2);
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_DCDC4P2);
+
+	__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+
+	/* make VBUSVALID_TRSH 4400mV and set PWD_CHARGE_4P2 */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+		HW_POWER_5VCTRL_CLR_ADDR);
+
+	__raw_writel(BF_POWER_5VCTRL_VBUSVALID_TRSH(VBUSVALID_THRESH_4_40V),
+		HW_POWER_5VCTRL_SET_ADDR);
+
+#else
+	// VDDD has different configurations depending on the battery type
+	// and battery level.
+
+	// For LiIon battery, we will use the DCDC to power VDDD.
+	// Use LinReg offset for DCDC mode.
+	__raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_SET);
+	// Turn on the VDDD DCDC output and turn off the VDDD LinReg output.
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+
+	__raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+	// Make sure stepping is enabled when using DCDC.
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR);
+
+	// Power VDDA and VDDIO from the DCDC.
+
+	/* Use LinReg offset for DCDC mode. */
+	__raw_writel(BF_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+	// Turn on the VDDA DCDC converter output and turn off LinReg output.
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+	__raw_writel(BM_POWER_VDDACTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	// Make sure stepping is enabled when using DCDC.
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	// Use LinReg offset for DCDC mode.
+	__raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET(
+					LINREG_OFFSET_STEP_BELOW
+						),
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+
+	/* Turn on the VDDIO DCDC output and turn on the LinReg output.*/
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+				HW_POWER_BASE + HW_POWER_5VCTRL_CLR_CLR);
+
+	// Make sure stepping is enabled when using DCDC.
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+#endif
+
+}
+
+/*
+ * This function sets up battery-to-5V handoff. The power switch from
+ * battery to 5V is automatic. This funtion enables the 5V present detection
+ * such that the 5V interrupt can be generated if it is enabled. (The interrupt
+ * handler can inform software the 5V present event.) To deal with noise or
+ * a high current, this function enables DCDC1/2 based on the battery mode.
+ */
+void ddi_power_enable_battery_to_5v_handoff(void)
+{
+	/* Clear vbusvalid interrupt flag */
+	__raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+				REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+
+	/* detect 5v plug-in */
+	__raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+				REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+#ifndef VDD4P2_ENABLED
+	// Force current from 5V to be zero by disabling its entry source.
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+	// Allow DCDC be to active when 5V is present.
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC,
+				REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+}
+
+/* This function handles the transitions on each of theVDD5V_GT_VDDIO power
+ * rails necessary to power the chip from the 5V power supply when it was
+ * previously powered from the battery power supply.
+ */
+void ddi_power_execute_battery_to_5v_handoff(void)
+{
+
+#ifdef VDD4P2_ENABLED
+	ddi_power_Enable4p2(450);
+#else
+	// Disable the DCDC during 5V connections.
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC,
+				HW_POWER_BAE + HW_POWER_5VCTRL_CLR);
+
+	// Power the VDDD/VDDA/VDDIO rail from the linear regulator.  The DCDC
+	// is ready to automatically power the chip when 5V is removed.
+	// Use this configuration when powering from 5V
+
+	// Use LinReg offset for LinReg mode
+	__raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+
+	// Turn on the VDDD LinReg and turn on the VDDD DCDC output.  The
+	// ENABLE_DCDC must be cleared to avoid LinReg and DCDC conflict.
+	__raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_CLR);
+
+	// Make sure stepping is disabled when using linear regulators
+	__raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING,
+				HW_POWER_BAE + HW_POWER_VDDDCTRL_SET);
+
+	// Use LinReg offset for LinReg mode
+	__raw_writel(BM_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BAE + HW_POWER_VDDACTRL_SET);
+
+
+	// Turn on the VDDA LinReg output and prepare the DCDC for transfer.
+	// ENABLE_DCDC must be clear to avoid DCDC and LinReg conflict.
+	stmp3xxx_set(BM_POWER_VDDACTRL_ENABLE_LINREG,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDACTRL_CLR);
+
+	// Make sure stepping is disabled when using linear regulators
+	__raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING,
+				 HW_POWER_BASE + HW_POWER_VDDACTRL_SET);
+
+	// Use LinReg offset for LinReg mode.
+	__raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET(
+					LINREG_OFFSET_STEP_BELOW),
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+
+	// Turn on the VDDIO LinReg output and prepare the VDDIO DCDC output.
+        // ENABLE_DCDC must be cleared to prevent DCDC and LinReg conflict.
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET,
+				HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR);
+	__raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	// Make sure stepping is disabled when using DCDC.
+	__raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING,
+			REGS_POWER_BASE + HW_POWER_VDDIOCTRL_SET);
+#endif
+}
+
+
+void ddi_power_Start4p2Dcdc(bool battery_ready)
+{
+
+	uint32_t temp_reg, old_values;
+
+	/* set vbusvalid threshold to 2.9V because of errata */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+			HW_POWER_5VCTRL_CLR_ADDR);
+
+
+#if 0
+	if (battery_ready)
+		ddi_power_EnableBatteryIrq();
+	else
+		enable_4p2_fiq_shutdown();
+#endif
+
+	/* enable hardware shutdown on battery brownout */
+	__raw_writel(
+			BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT |
+			__raw_readl(HW_POWER_BATTMONITOR_ADDR),
+			HW_POWER_BATTMONITOR_ADDR);
+
+	/* set VBUS DROOP threshold to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+			HW_POWER_5VCTRL_CLR_ADDR);
+
+	/* turn of vbus valid detection.  Part of errate
+	 * workaround. */
+	__raw_writel(BM_POWER_5VCTRL_PWRUP_VBUS_CMPS,
+			HW_POWER_5VCTRL_SET_ADDR);
+
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			HW_POWER_5VCTRL_CLR_ADDR);
+
+
+	temp_reg = (BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO |
+		BM_POWER_CTRL_ENIRQ_VDD5V_DROOP |
+		BM_POWER_CTRL_ENIRQ_VBUS_VALID);
+
+	/* save off old brownout enable values */
+	old_values = __raw_readl(HW_POWER_CTRL_ADDR) &
+		temp_reg;
+
+	/* disable irqs affected by errata */
+	__raw_writel(temp_reg, HW_POWER_CTRL_CLR_ADDR);
+
+	/* Enable DCDC from 4P2 */
+	__raw_writel(__raw_readl(HW_POWER_DCDC4P2_ADDR) |
+			BM_POWER_DCDC4P2_ENABLE_DCDC,
+			HW_POWER_DCDC4P2_ADDR);
+
+	/* give a delay to check for errate noise problem */
+	mdelay(1);
+
+	temp_reg = (BM_POWER_CTRL_VDDD_BO_IRQ |
+		BM_POWER_CTRL_VDDA_BO_IRQ |
+		BM_POWER_CTRL_VDDIO_BO_IRQ |
+		BM_POWER_CTRL_VDD5V_DROOP_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ);
+
+	/* stay in this loop until the false brownout indciations
+	 * no longer occur or until 5V actually goes away
+	 */
+	while ((__raw_readl(HW_POWER_CTRL_ADDR) & temp_reg) &&
+		!(__raw_readl(HW_POWER_CTRL_ADDR) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ)) {
+		__raw_writel(temp_reg, HW_POWER_CTRL_CLR_ADDR);
+
+		mdelay(1);
+	}
+
+	/* revert to previous enable irq values */
+	__raw_writel(old_values, HW_POWER_CTRL_SET_ADDR);
+
+	if (DetectionMethod == DDI_POWER_5V_VBUSVALID)
+		__raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT,
+			HW_POWER_5VCTRL_SET_ADDR);
+}
+
+
+/* set the optimal CMPTRIP for the best possible 5V
+ * disconnection handling but without drawing power
+ * from the power on a stable 4p2 rails (at 4.2V).
+ */
+void ddi_power_handle_cmptrip(void)
+{
+	enum ddi_power_5v_status pmu_5v_status;
+	uint32_t temp = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+	temp &= ~(BM_POWER_DCDC4P2_CMPTRIP);
+
+	pmu_5v_status = ddi_power_GetPmu5vStatus();
+
+	/* CMPTRIP should remain at 31 when 5v is disconnected
+	 * or 5v is connected but hasn't been handled yet
+	 */
+	if (pmu_5v_status != existing_5v_connection)
+		temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+	else if (ddi_power_GetBattery() >
+			BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV)
+		temp |= (1 << BP_POWER_DCDC4P2_CMPTRIP);
+	else if (ddi_power_GetBattery() >
+			BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV)
+		temp |= (24 << BP_POWER_DCDC4P2_CMPTRIP);
+	else
+		temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+
+
+	__raw_writel(temp, HW_POWER_DCDC4P2_ADDR);
+}
+
+void ddi_power_Init4p2Params(void)
+{
+	uint32_t temp;
+
+	ddi_power_handle_cmptrip();
+
+	temp = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+
+	/* DROPOUT CTRL to 10, TRG to 0 */
+	temp &= ~(BM_POWER_DCDC4P2_TRG | BM_POWER_DCDC4P2_DROPOUT_CTRL);
+	temp |= (0xa << BP_POWER_DCDC4P2_DROPOUT_CTRL);
+
+	__raw_writel(temp, HW_POWER_DCDC4P2_ADDR);
+
+
+	temp = __raw_readl(HW_POWER_5VCTRL_ADDR);
+
+	/* HEADROOM_ADJ to 4, CHARGE_4P2_ILIMIT to 0 */
+	temp &= ~(BM_POWER_5VCTRL_HEADROOM_ADJ |
+			BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
+	temp |= (4 << BP_POWER_5VCTRL_HEADROOM_ADJ);
+
+}
+
+bool ddi_power_IsBattRdyForXfer(void)
+{
+	uint16_t u16BatteryVoltage = ddi_power_GetBattery();
+
+	if (u16BatteryVoltage > DDI_POWER_BATTERY_XFER_THRESHOLD_MV)
+		return true;
+	else
+		return false;
+
+}
+
+void ddi_power_EnableVbusDroopIrq(void)
+{
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			HW_POWER_CTRL_SET_ADDR);
+
+}
+
+
+void ddi_power_Enable4p2(uint16_t target_current_limit_ma)
+{
+
+	uint16_t u16BatteryVoltage;
+	uint32_t temp_reg;
+
+	ddi_power_Init4p2Params();
+
+	/* disable 4p2 rail brownouts for now. (they
+	 * should have already been off at this point) */
+	__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+		HW_POWER_CTRL_CLR_ADDR);
+
+	u16BatteryVoltage = ddi_power_GetBattery();
+
+	if (ddi_power_IsBattRdyForXfer()) {
+
+		/* PWD_CHARGE_4P2 should already be set but just in case... */
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+				HW_POWER_5VCTRL_SET_ADDR);
+
+		/* set CMPTRIP to DCDC_4P2 pin >= BATTERY pin */
+		temp_reg = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+		temp_reg &= ~(BM_POWER_DCDC4P2_CMPTRIP);
+		temp_reg |= (31 << BP_POWER_DCDC4P2_CMPTRIP);
+		__raw_writel(temp_reg, HW_POWER_DCDC4P2_ADDR);
+
+		/* since we have a good battery, we can go ahead
+		 * and turn on the Dcdcing from the 4p2 source.
+		 * This is helpful in working around the chip
+		 * errata.
+		 */
+		ddi_power_Start4p2Dcdc(true);
+
+		/* Enable VbusDroopIrq to handle errata */
+
+		/* set vbus droop detection level to 4.3V */
+		__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+				HW_POWER_5VCTRL_CLR_ADDR);
+
+		ddi_power_EnableVbusDroopIrq();
+		/* now that the DCDC4P2 problems are cleared,
+		 * turn on and ramp up the 4p2 regulator
+		 */
+		temp_reg = ddi_power_BringUp4p2Regulator(
+			target_current_limit_ma, true);
+
+		/* if we still have our 5V connection, we can disable
+		 * battery brownout interrupt.  This is because the
+		 * VDD5V DROOP IRQ handler will also shutdown if battery
+		 * is browned out and it will enable the battery brownout
+		 * and bring VBUSVALID_TRSH level back to a normal level
+		 * which caused the hardware battery brownout shutdown
+		 * to be enabled.  The benefit of this is that device
+		 * that have detachable batteries (or devices going through
+		 * the assembly line and running this firmware to test
+		 *  with) can avoid shutting down if 5V is present and
+		 *  battery voltage goes away.
+		 */
+		if (!(__raw_readl(HW_POWER_CTRL_ADDR) &
+			(BM_POWER_CTRL_VBUSVALID_IRQ |
+			BM_POWER_CTRL_VDD5V_DROOP_IRQ))) {
+			ddi_power_EnableBatteryBoInterrupt(false);
+		}
+
+
+
+		printk(KERN_INFO "4P2 rail started.  5V current limit\
+			set to %dmA\n",	temp_reg);
+
+	} else {
+
+		printk(KERN_ERR "4P2 rail was attempted to be started \
+			from a system\
+			with a very low battery voltage.  This is not\
+			yet handled by the kernel driver, only by the\
+			bootlets.  Remaining on battery power.\n");
+
+		if ((__raw_readl(HW_POWER_5VCTRL_ADDR) &&
+					BM_POWER_5VCTRL_ENABLE_DCDC))
+			ddi_power_EnableBatteryBoInterrupt(true);
+
+#if 0
+		/* enable hardware shutdown (if 5v disconnected)
+		 * on battery brownout */
+		__raw_writel(
+			BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT |
+			__raw_readl(HW_POWER_BATTMONITOR_ADDR),
+			HW_POWER_BATTMONITOR_ADDR);
+
+		/* turn on and ramp up the 4p2 regulator */
+		temp_reg = ddi_power_BringUp4p2Regulator(
+			target_current_limit_ma, false);
+
+		Configure4p2FiqShutdown();
+
+		SetVbusValidThresh(0);
+#endif
+	}
+}
+
+/* enable and ramp up 4p2 regulator */
+uint16_t ddi_power_BringUp4p2Regulator(
+		uint16_t target_current_limit_ma,
+		bool b4p2_dcdc_enabled)
+{
+	uint32_t temp_reg;
+	uint16_t charge_4p2_ilimit = 0;
+
+	/* initial current limit to 0 */
+	__raw_writel(BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT,
+		HW_POWER_5VCTRL_CLR_ADDR);
+
+	__raw_writel(__raw_readl(HW_POWER_DCDC4P2_ADDR) |
+		BM_POWER_DCDC4P2_ENABLE_4P2,
+		HW_POWER_DCDC4P2_ADDR);
+
+	/* set 4p2 target voltage to zero */
+	temp_reg = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+	temp_reg &= (~BM_POWER_DCDC4P2_TRG);
+	__raw_writel(temp_reg, HW_POWER_DCDC4P2_ADDR);
+
+	/* Enable 4P2 regulator*/
+	__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			HW_POWER_5VCTRL_CLR_ADDR);
+
+	if (target_current_limit_ma > 780)
+		target_current_limit_ma = 780;
+
+	ddi_power_Set4p2BoLevel(4150);
+
+	/* possibly not necessary but recommended for unloaded
+	 * 4p2 rail
+	 */
+	__raw_writel(BM_POWER_CHARGE_ENABLE_LOAD,
+		HW_POWER_CHARGE_SET_ADDR);
+
+	while (charge_4p2_ilimit < target_current_limit_ma) {
+
+		if (__raw_readl(HW_POWER_CTRL_ADDR) &
+			(BM_POWER_CTRL_VBUSVALID_IRQ |
+			BM_POWER_CTRL_VDD5V_DROOP_IRQ))
+			break;
+
+
+		charge_4p2_ilimit += 100;
+		if (charge_4p2_ilimit > target_current_limit_ma)
+			charge_4p2_ilimit = target_current_limit_ma;
+
+		ddi_power_set_4p2_ilimit(charge_4p2_ilimit);
+
+		/* dcdc4p2 enable_dcdc must be enabled for
+		 * 4p2 bo indication to function.  If not enabled,
+		 * skip using bo level detection
+		 */
+		if (!(b4p2_dcdc_enabled))
+			msleep(1);
+		else if	(__raw_readl(HW_POWER_STS_ADDR) &
+			BM_POWER_STS_DCDC_4P2_BO)
+			msleep(1);
+		else {
+			charge_4p2_ilimit = target_current_limit_ma;
+			ddi_power_set_4p2_ilimit(charge_4p2_ilimit);
+		}
+	}
+
+	ddi_power_Set4p2BoLevel(3600);
+
+	__raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+
+	/* rail should now be up and loaded.  Extra
+	 * internal load is not necessary.
+	 */
+	__raw_writel(BM_POWER_CHARGE_ENABLE_LOAD,
+		HW_POWER_CHARGE_CLR_ADDR);
+
+	return charge_4p2_ilimit;
+
+}
+
+
+void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv)
+{
+	uint16_t bo_reg_value;
+	uint32_t temp;
+
+	if (bo_voltage_mv < 3600)
+		bo_voltage_mv = 3600;
+	else if (bo_voltage_mv > 4375)
+		bo_voltage_mv = 4375;
+
+	bo_reg_value = (bo_voltage_mv - 3600) / 25;
+
+	temp = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+	temp &= (~BM_POWER_DCDC4P2_BO);
+	temp |= (bo_reg_value << BP_POWER_DCDC4P2_BO);
+	__raw_writel(temp, HW_POWER_DCDC4P2_ADDR);
+}
+
+
+
+void ddi_power_init_handoff(void)
+{
+	int val;
+	/* The following settings give optimal power supply capability */
+
+	// enable 5v presence detection
+	ddi_power_Enable5vDetection();
+
+	if (ddi_power_Get5vPresentFlag())
+		/* It's 5V mode, enable 5V-to-battery handoff */
+		ddi_power_enable_5v_to_battery_handoff();
+	else
+		/* It's battery mode, enable battery-to-5V handoff */
+		ddi_power_enable_battery_to_5v_handoff();
+
+	// Finally enable the battery adjust
+	val = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	val |= BM_POWER_BATTMONITOR_EN_BATADJ;
+	__raw_writel(val, REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+}
+
+
+void ddi_power_EnableBatteryInterrupt(bool enable)
+{
+
+	__raw_writel(BM_POWER_CTRL_BATT_BO_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			HW_POWER_CTRL_SET_ADDR);
+
+}
+
+
+int ddi_power_init_battery(void)
+{
+
+	int ret = 0;
+
+	if (!(__raw_readl(HW_POWER_5VCTRL_ADDR) &&
+			BM_POWER_5VCTRL_ENABLE_DCDC)) {
+		printk(KERN_ERR "WARNING: Power Supply not\
+			initialized correctly by \
+			pre-kernel bootlets. HW_POWER_5VCTRL \
+			ENABLE_DCDC should already be set.  Kernel \
+			power driver behavior may not be reliable \n");
+		ret = 1;
+	}
+
+	/* the following code to enable automatic battery measurement
+	 * should have already been enabled in the boot prep files.  Not
+	 * sure if this is necessary or possibly susceptible to
+	 * mis-coordination
+	 */
+
+
+	ret = !hw_lradc_present(BATTERY_VOLTAGE_CH);
+
+	if (ret) {
+		printk(KERN_ERR "%s: hw_lradc_present failed\n", __func__);
+		return -ENODEV;
+	} else {
+		uint16_t wait_time = 0;
+
+		hw_lradc_configure_channel(BATTERY_VOLTAGE_CH, 0 /* div2 */ ,
+					   0 /* acc */ ,
+					   0 /* num_samples */);
+
+		/* Setup the trigger loop forever */
+		hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_BATTERY,
+			1 << BATTERY_VOLTAGE_CH,
+			1 << LRADC_DELAY_TRIGGER_BATTERY,
+			0, 200);
+
+		/* Clear the accumulator & NUM_SAMPLES */
+		stmp3xxx_clearl(0xFFFFFFFF,
+			REGS_LRADC_BASE + HW_LRADC_CHn(BATTERY_VOLTAGE_CH));
+
+		/* clear previous "measurement performed" status */
+		__raw_writel(1 << BATTERY_VOLTAGE_CH,
+			HW_LRADC_CTRL1_CLR_ADDR);
+
+		/* set to LiIon scale factor */
+		__raw_writel(BM_LRADC_CONVERSION_SCALE_FACTOR,
+			HW_LRADC_CONVERSION_SET_ADDR);
+
+		/* kick off the trigger */
+		hw_lradc_set_delay_trigger_kick(
+				LRADC_DELAY_TRIGGER_BATTERY, 1);
+
+
+		/* wait for 1st converstion to be complete before
+		 * enabling automatic copy to power supply
+		 * peripheral
+		 */
+		while (!(__raw_readl(HW_LRADC_CTRL1_ADDR) &
+			1 << BATTERY_VOLTAGE_CH) &&
+				(wait_time < 10)) {
+			wait_time++;
+			udelay(1);
+		}
+
+		__raw_writel(BM_LRADC_CONVERSION_AUTOMATIC,
+			HW_LRADC_CONVERSION_SET_ADDR);
+	}
+
+#ifndef VDD4P2_ENABLED
+	/* prepare handoff */
+	ddi_power_init_handoff();
+#endif
+	return ret;
+}
+
+/*
+ * Use the the lradc1 channel
+ * get the die temperature from on-chip sensor.
+ */
+uint16_t MeasureInternalDieTemperature(void)
+{
+	uint32_t  ch8Value, ch9Value;
+
+	/* power up internal tep sensor block */
+	__raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD,
+			REGS_LRADC_BASE + HW_LRADC_CTRL2_CLR);
+
+	/* mux to the lradc 8th temp channel */
+	__raw_writel(BF(0xF, LRADC_CTRL4_LRADC1SELECT),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR);
+	__raw_writel(BF(8, LRADC_CTRL4_LRADC1SELECT),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_SET);
+
+	/* Clear the interrupt flag */
+	__raw_writel(BM_LRADC_CTRL1_LRADC1_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BF(1 << LRADC_CH1, LRADC_CTRL0_SCHEDULE),
+			REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+
+	/* Wait for conversion complete*/
+	while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1)
+			& BM_LRADC_CTRL1_LRADC1_IRQ))
+                cpu_relax();
+
+	/* Clear the interrupt flag again */
+	__raw_writel(BM_LRADC_CTRL1_LRADC1_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+
+	// read temperature value and clr lradc
+	ch8Value = __raw_readl(REGS_LRADC_BASE +
+			HW_LRADC_CHn(LRADC_CH1)) & BM_LRADC_CHn_VALUE;
+
+
+	__raw_writel(BM_LRADC_CHn_VALUE,
+			REGS_LRADC_BASE + HW_LRADC_CHn_CLR(LRADC_CH1));
+
+	/* mux to the lradc 9th temp channel */
+	__raw_writel(BF(0xF, LRADC_CTRL4_LRADC1SELECT),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR);
+	__raw_writel(BF(9, LRADC_CTRL4_LRADC1SELECT),
+			REGS_LRADC_BASE + HW_LRADC_CTRL4_SET);
+
+	/* Clear the interrupt flag */
+	__raw_writel(BM_LRADC_CTRL1_LRADC1_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	__raw_writel(BF(1 << LRADC_CH1, LRADC_CTRL0_SCHEDULE),
+			REGS_LRADC_BASE + HW_LRADC_CTRL0_SET);
+	// Wait for conversion complete
+	while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1)
+			& BM_LRADC_CTRL1_LRADC1_IRQ))
+                cpu_relax();
+
+	/* Clear the interrupt flag */
+	__raw_writel(BM_LRADC_CTRL1_LRADC1_IRQ,
+			REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR);
+	// read temperature value
+	ch9Value = __raw_readl(
+			REGS_LRADC_BASE + HW_LRADC_CHn(LRADC_CH1))
+		  & BM_LRADC_CHn_VALUE;
+
+
+	__raw_writel(BM_LRADC_CHn_VALUE,
+			REGS_LRADC_BASE + HW_LRADC_CHn_CLR(LRADC_CH1));
+
+	/* power down temp sensor block */
+	__raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD,
+			REGS_LRADC_BASE + HW_LRADC_CTRL2_SET);
+
+
+	return (uint16_t)((ch9Value-ch8Value)*GAIN_CORRECTION/4000);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_GetBatteryMode
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void)
+{
+	return DDI_POWER_BATT_MODE_LIION;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_GetBatteryChargerEnabled
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_power_GetBatteryChargerEnabled(void)
+{
+#if 0
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_BATT_CHRG_PRESENT) ? 1 : 0;
+#endif
+	return 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report if the charger hardware power is on.
+//!
+//! \fntype Function
+//!
+//! This function reports if the charger hardware power is on.
+//!
+//! \retval  Zero if the charger hardware is not powered. Non-zero otherwise.
+//!
+//! Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD"
+//! stands for "power down". Thus, when the bit is set, the battery charger
+//! hardware is POWERED DOWN.
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_power_GetChargerPowered(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_PWD_BATTCHRG) ? 0 : 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Turn the charging hardware on or off.
+//!
+//! \fntype Function
+//!
+//! This function turns the charging hardware on or off.
+//!
+//! \param[in]  on  Indicates whether the charging hardware should be on or off.
+//!
+//! Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD"
+//! stands for "power down". Thus, when the bit is set, the battery charger
+//! hardware is POWERED DOWN.
+////////////////////////////////////////////////////////////////////////////////
+void ddi_power_SetChargerPowered(bool bPowerOn)
+{
+	// Hit the battery charge power switch.
+	if (bPowerOn) {
+		__raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG,
+			REGS_POWER_BASE + HW_POWER_CHARGE_CLR);
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+	} else {
+		__raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG,
+			REGS_POWER_BASE + HW_POWER_CHARGE_SET);
+#ifndef VDD4P2_ENABLED
+		__raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2,
+			REGS_POWER_BASE + HW_POWER_5VCTRL_SET);
+#endif
+	}
+
+//#ifdef CONFIG_POWER_SUPPLY_DEBUG
+#if 0
+	printk("Battery charger: charger %s\n", bPowerOn ? "ON!" : "OFF");
+	dump_regs();
+#endif
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Reports if the charging current has fallen below the threshold.
+//!
+//! \fntype Function
+//!
+//! This function reports if the charging current that the battery is accepting
+//! has fallen below the threshold.
+//!
+//! Note that this bit is regarded by the hardware guys as very slightly
+//! unreliable. They recommend that you don't believe a value of zero until
+//! you've sampled it twice.
+//!
+//! \retval  Zero if the battery is accepting less current than indicated by the
+//!          charging threshold. Non-zero otherwise.
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_power_GetChargeStatus(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_CHRGSTS) ? 1 : 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// Battery Voltage
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the voltage across the battery.
+//!
+//! \fntype Function
+//!
+//! This function reports the voltage across the battery. Should return a
+//! value in range ~3000 - 4200 mV.
+//!
+//! \retval The voltage across the battery, in mV.
+//!
+////////////////////////////////////////////////////////////////////////////////
+
+//! \brief Constant value for 8mV steps used in battery translation
+#define BATT_VOLTAGE_8_MV 8
+
+uint16_t ddi_power_GetBattery(void)
+{
+	uint32_t    u16BattVolt;
+
+	// Get the raw result of battery measurement
+	u16BattVolt = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	u16BattVolt &= BM_POWER_BATTMONITOR_BATT_VAL;
+	u16BattVolt >>= BP_POWER_BATTMONITOR_BATT_VAL;
+
+	// Adjust for 8-mV LSB resolution and return
+	u16BattVolt *= BATT_VOLTAGE_8_MV;
+
+//#ifdef CONFIG_POWER_SUPPLY_DEBUG
+#if 0
+	printk("Battery charger: %u mV\n", u16BattVolt);
+#endif
+
+	return u16BattVolt;
+}
+
+#if 0
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report the voltage across the battery.
+//!
+//! \fntype Function
+//!
+//! This function reports the voltage across the battery.
+//!
+//! \retval The voltage across the battery, in mV.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_GetBatteryBrownout(void)
+{
+	uint32_t    u16BatteryBrownoutLevel;
+
+	// Get battery brownout level
+	u16BatteryBrownoutLevel = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR);
+	u16BatteryBrownoutLevel &= BM_POWER_BATTMONITOR_BRWNOUT_LVL;
+	u16BatteryBrownoutLevel >>= BP_POWER_BATTMONITOR_BRWNOUT_LVL;
+
+	// Calculate battery brownout level
+	switch (ddi_power_GetBatteryMode()) {
+        case DDI_POWER_BATT_MODE_LIION:
+		u16BatteryBrownoutLevel *= BATT_BRWNOUT_LIION_LEVEL_STEP_MV;
+		u16BatteryBrownoutLevel += BATT_BRWNOUT_LIION_BASE_MV;
+		break;
+        case DDI_POWER_BATT_MODE_ALKALINE_NIMH:
+		u16BatteryBrownoutLevel *= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV;
+		u16BatteryBrownoutLevel += BATT_BRWNOUT_ALKAL_BASE_MV;
+		break;
+        default:
+		u16BatteryBrownoutLevel = 0;
+		break;
+	}
+	return u16BatteryBrownoutLevel;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Set battery brownout level
+//!
+//! \fntype     Reentrant Function
+//!
+//! This function sets the battery brownout level in millivolt. It transforms the
+//! input brownout value from millivolts to the hardware register bit field value
+//! taking the ceiling value in the calculation.
+//!
+//! \param[in]  u16BattBrownout_mV      Battery battery brownout level in mV
+//!
+//! \return     SUCCESS
+//!
+////////////////////////////////////////////////////////////////////////////////
+int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV)
+{
+	int16_t i16BrownoutLevel;
+	int ret = 0;
+
+	// Calculate battery brownout level
+	switch (ddi_power_GetBatteryMode()) {
+        case DDI_POWER_BATT_MODE_LIION:
+		i16BrownoutLevel  = u16BattBrownout_mV -
+			BATT_BRWNOUT_LIION_EQN_CONST;
+		i16BrownoutLevel /= BATT_BRWNOUT_LIION_LEVEL_STEP_MV;
+		break;
+        case DDI_POWER_BATT_MODE_ALKALINE_NIMH:
+		i16BrownoutLevel  = u16BattBrownout_mV -
+			BATT_BRWNOUT_ALKAL_EQN_CONST;
+		i16BrownoutLevel /= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV;
+		break;
+        default:
+		return -EINVAL;
+	}
+
+	// Do a check to make sure nothing went wrong.
+	if (i16BrownoutLevel <= 0x0f) {
+		//Write the battery brownout level
+		__raw_writel(
+			BF(i16BrownoutLevel, POWER_BATTMONITOR_BRWNOUT_LVL),
+				REGS_POWER_BASE + HW_POWER_BATTMONITOR_SET);
+	} else
+		ret = -EINVAL;
+
+	return ret;
+}
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// Currents
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_SetMaxBatteryChargeCurrent
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur)
+{
+	uint32_t   u16OldSetting;
+	uint32_t   u16NewSetting;
+	uint32_t   u16ToggleMask;
+
+	// Get the old setting.
+	u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >>
+		BP_POWER_CHARGE_BATTCHRG_I;
+
+	// Convert the new threshold into a setting.
+	u16NewSetting = ddi_power_convert_current_to_setting(u16MaxCur);
+
+	/* Compute the toggle mask. */
+	u16ToggleMask = u16OldSetting ^ u16NewSetting;
+
+	/* Write to the toggle register.*/
+	__raw_writel(u16ToggleMask << BP_POWER_CHARGE_BATTCHRG_I,
+			REGS_POWER_BASE + HW_POWER_CHARGE_TOG);
+
+	// Tell the caller what current we're set at now.
+	return ddi_power_convert_setting_to_current(u16NewSetting);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_GetMaxBatteryChargeCurrent
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_GetMaxBatteryChargeCurrent(void)
+{
+	uint32_t u8Bits;
+
+	// Get the raw data from register
+	u8Bits = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >>
+		BP_POWER_CHARGE_BATTCHRG_I;
+
+	// Translate raw data to current (in mA) and return it
+	return ddi_power_convert_setting_to_current(u8Bits);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_GetMaxChargeCurrent
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh)
+{
+	uint32_t   u16OldSetting;
+	uint32_t   u16NewSetting;
+	uint32_t   u16ToggleMask;
+
+	//-------------------------------------------------------------------
+	// See ddi_power_SetMaxBatteryChargeCurrent for an explanation of
+	// why we're using the toggle register here.
+	//
+	// Since this function doesn't have any major hardware effect,
+	// we could use the usual macros for writing to this bit field. But,
+	// for the sake of parallel construction and any potentially odd
+	// effects on the status bit, we use the toggle register in the same
+	// way as ddi_bc_hwSetMaxCurrent.
+	//-------------------------------------------------------------------
+
+	//-------------------------------------------------------------------
+	// The threshold hardware can't express as large a range as the max
+	// current setting, but we can use the same functions as long as we
+	// add an extra check here.
+	//
+	// Thresholds larger than 180mA can't be expressed.
+	//-------------------------------------------------------------------
+
+	if (u16Thresh > 180)
+		u16Thresh = 180;
+
+	////////////////////////////////////////
+	// Create the mask
+	////////////////////////////////////////
+
+	// Get the old setting.
+	u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >>
+		BP_POWER_CHARGE_STOP_ILIMIT;
+
+	// Convert the new threshold into a setting.
+	u16NewSetting = ddi_power_convert_current_to_setting(u16Thresh);
+
+	// Compute the toggle mask.
+	u16ToggleMask = u16OldSetting ^ u16NewSetting;
+
+	/////////////////////////////////////////
+	// Write to the register
+	/////////////////////////////////////////
+
+	// Write to the toggle register.
+	__raw_writel(BF_POWER_CHARGE_STOP_ILIMIT(u16ToggleMask),
+			REGS_POWER_BASE + HW_POWER_CHARGE_TOG);
+
+	// Tell the caller what current we're set at now.
+	return ddi_power_convert_setting_to_current(u16NewSetting);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_GetBatteryChargeCurrentThreshold
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void)
+{
+	uint32_t u16Threshold;
+
+	u16Threshold = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >>
+		BP_POWER_CHARGE_STOP_ILIMIT;
+
+	return ddi_power_convert_setting_to_current(u16Threshold);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// Conversion
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Compute the actual current expressible in the hardware.
+//!
+//! \fntype Function
+//!
+//! Given a desired current, this function computes the actual current
+//! expressible in the hardware.
+//!
+//! Note that the hardware has a minimum resolution of 10mA and a maximum
+//! expressible value of 780mA (see the data sheet for details). If the given
+//! current cannot be expressed exactly, then the largest expressible smaller
+//! value will be used.
+//!
+//! \param[in]  u16Current  The current of interest.
+//!
+//! \retval  The corresponding current in mA.
+//!
+////////////////////////////////////////////////////////////////////////////////
+uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current)
+{
+	return ddi_power_convert_setting_to_current(
+		ddi_power_convert_current_to_setting(u16Current));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! Name: ddi_power_Get5VPresent
+//!
+//! \brief
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_power_Get5vPresentFlag(void)
+{
+	switch (DetectionMethod) {
+	case DDI_POWER_5V_VBUSVALID:
+		// Check VBUSVALID for 5V present
+		return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_VBUSVALID) != 0);
+	case DDI_POWER_5V_VDD5V_GT_VDDIO:
+		// Check VDD5V_GT_VDDIO for 5V present
+		return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_VDD5V_GT_VDDIO) != 0);
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Report on the die temperature.
+//!
+//! \fntype Function
+//!
+//! This function reports on the die temperature.
+//!
+//! \param[out]  pLow   The low  end of the temperature range.
+//! \param[out]  pHigh  The high end of the temperature range.
+//!
+////////////////////////////////////////////////////////////////////////////////
+// Temperature constant
+#define TEMP_READING_ERROR_MARGIN 5
+#define KELVIN_TO_CELSIUS_CONST 273
+
+void ddi_power_GetDieTemp(int16_t * pLow, int16_t * pHigh)
+{
+	int16_t i16High, i16Low;
+	uint16_t u16Reading;
+
+	// Get the reading in Kelvins
+	u16Reading = MeasureInternalDieTemperature();
+
+	// Adjust for error margin
+	i16High = u16Reading + TEMP_READING_ERROR_MARGIN;
+	i16Low  = u16Reading - TEMP_READING_ERROR_MARGIN;
+
+	// Convert to Celsius
+	i16High -= KELVIN_TO_CELSIUS_CONST;
+	i16Low  -= KELVIN_TO_CELSIUS_CONST;
+
+//#ifdef CONFIG_POWER_SUPPLY_DEBUG
+#if 0
+	printk("Battery charger: Die temp %d to %d C\n", i16Low, i16High);
+#endif
+	// Return the results
+	*pHigh = i16High;
+	*pLow  = i16Low;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+//!
+//! \brief Checks to see if the DCDC has been manually enabled
+//!
+//! \fntype Function
+//!
+//! \retval  true if DCDC is ON, false if DCDC is OFF.
+//!
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_power_IsDcdcOn(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & BM_POWER_5VCTRL_ENABLE_DCDC) ? 1 : 0;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+//! See hw_power.h for details.
+////////////////////////////////////////////////////////////////////////////////
+void ddi_power_SetPowerClkGate(bool bGate)
+{
+	// Gate/Ungate the clock to the power block
+	if (bGate) {
+		__raw_writel(BM_POWER_CTRL_CLKGATE,
+			REGS_POWER_BASE + HW_POWER_CTRL_SET);
+	} else {
+		__raw_writel(BM_POWER_CTRL_CLKGATE,
+			REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+	}
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//! See hw_power.h for details.
+////////////////////////////////////////////////////////////////////////////////
+bool ddi_power_GetPowerClkGate(void)
+{
+	return (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & BM_POWER_CTRL_CLKGATE) ? 1 : 0;
+}
+
+
+enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void)
+{
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+
+		if (__raw_readl(HW_POWER_CTRL_ADDR) &
+			BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO) {
+			if ((__raw_readl(HW_POWER_CTRL_ADDR) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) ||
+				ddi_power_Get5vPresentFlag())
+				return new_5v_connection;
+			else
+				return existing_5v_disconnection;
+		} else {
+			if ((__raw_readl(HW_POWER_CTRL_ADDR) &
+				BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) ||
+				!ddi_power_Get5vPresentFlag() ||
+				ddi_power_Get5vDroopFlag())
+				return new_5v_disconnection;
+			else
+				return existing_5v_connection;
+		}
+	} else {
+
+		if (__raw_readl(HW_POWER_CTRL_ADDR) &
+			BM_POWER_CTRL_POLARITY_VBUSVALID) {
+			if ((__raw_readl(HW_POWER_CTRL_ADDR) &
+				BM_POWER_CTRL_VBUSVALID_IRQ) ||
+				ddi_power_Get5vPresentFlag())
+				return new_5v_connection;
+			else
+				return existing_5v_disconnection;
+		} else {
+			if ((__raw_readl(HW_POWER_CTRL_ADDR) &
+				BM_POWER_CTRL_VBUSVALID_IRQ) ||
+				!ddi_power_Get5vPresentFlag() ||
+				ddi_power_Get5vDroopFlag())
+				return new_5v_disconnection;
+			else
+				return existing_5v_connection;
+		}
+
+	}
+}
+
+void ddi_power_disable_5v_connection_irq(void)
+{
+
+	__raw_writel((BM_POWER_CTRL_ENIRQ_VBUS_VALID |
+		BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO),
+		HW_POWER_CTRL_CLR_ADDR);
+}
+
+void ddi_power_enable_5v_disconnect_detection(void)
+{
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO |
+		BM_POWER_CTRL_POLARITY_VBUSVALID,
+		HW_POWER_CTRL_CLR_ADDR);
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ,
+		HW_POWER_CTRL_CLR_ADDR);
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+			HW_POWER_CTRL_SET_ADDR);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+			HW_POWER_CTRL_SET_ADDR);
+	}
+}
+
+void ddi_power_enable_5v_connect_detection(void)
+{
+	__raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO |
+		BM_POWER_CTRL_POLARITY_VBUSVALID,
+		HW_POWER_CTRL_SET_ADDR);
+
+	__raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ |
+		BM_POWER_CTRL_VBUSVALID_IRQ,
+		HW_POWER_CTRL_CLR_ADDR);
+
+	if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+			HW_POWER_CTRL_SET_ADDR);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID,
+			HW_POWER_CTRL_SET_ADDR);
+	}
+}
+
+void ddi_power_EnableBatteryBoInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_BATT_BO_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+		__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			HW_POWER_CTRL_SET_ADDR);
+		/* todo: make sure the battery brownout comparator
+		 * is enabled in HW_POWER_BATTMONITOR
+		 */
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQBATT_BO,
+			HW_POWER_CTRL_CLR_ADDR);
+	}
+}
+
+void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+		__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+			HW_POWER_CTRL_SET_ADDR);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO,
+			HW_POWER_CTRL_CLR_ADDR);
+	}
+}
+
+void ddi_power_EnableVdd5vDroopInterrupt(bool bEnable)
+{
+	if (bEnable) {
+
+		__raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			HW_POWER_CTRL_SET_ADDR);
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP,
+			HW_POWER_CTRL_CLR_ADDR);
+	}
+}
+
+
+void ddi_power_Enable5vDisconnectShutdown(bool bEnable)
+{
+	if (bEnable) {
+		__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+			HW_POWER_5VCTRL_SET_ADDR);
+	} else {
+		__raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT,
+			HW_POWER_5VCTRL_CLR_ADDR);
+	}
+}
+
+
+void ddi_power_enable_5v_to_battery_xfer(bool bEnable)
+{
+	if (bEnable) {
+		/* order matters */
+
+		/* we can enable this in in vbus droop or 4p2 fiq handler
+		 * ddi_power_EnableBatteryBoInterrupt(true);
+		 */
+		ddi_power_Enable5vDisconnectShutdown(false);
+	} else {
+		/* order matters */
+		ddi_power_Enable5vDisconnectShutdown(true);
+		ddi_power_EnableBatteryBoInterrupt(false);
+	}
+}
+
+
+void ddi_power_init_4p2_protection(void)
+{
+	/* set vbus droop detection level to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+			HW_POWER_5VCTRL_CLR_ADDR);
+
+	/* VBUSDROOP THRESHOLD to 4.3V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH,
+		HW_POWER_5VCTRL_CLR_ADDR);
+
+	ddi_power_EnableVbusDroopIrq();
+
+	/* VBUSVALID THRESH = 2.9V */
+	__raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH,
+		HW_POWER_5VCTRL_CLR_ADDR);
+
+}
+
+/* determine if all the bits are in a 'DCDC 4P2 Enabled' state. */
+bool ddi_power_check_4p2_bits(void)
+{
+
+
+	uint32_t temp;
+
+	temp = __raw_readl(HW_POWER_5VCTRL_ADDR) &
+		BM_POWER_5VCTRL_PWD_CHARGE_4P2;
+
+	/* if PWD_CHARGE_4P2 = 1, 4p2 is disabled */
+	if (temp)
+		return false;
+
+	temp = __raw_readl(HW_POWER_DCDC4P2_ADDR) &
+		BM_POWER_DCDC4P2_ENABLE_DCDC;
+
+	if (!temp)
+		return false;
+
+	temp = __raw_readl(HW_POWER_DCDC4P2_ADDR) &
+			BM_POWER_DCDC4P2_ENABLE_4P2;
+
+	if (temp)
+		return true;
+	else
+		return false;
+
+}
+
+uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit)
+{
+	uint32_t temp_reg;
+
+	if (ilimit > 780)
+		ilimit = 780;
+	temp_reg = __raw_readl(HW_POWER_5VCTRL_ADDR);
+	temp_reg &= (~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
+	temp_reg |= BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(
+		ddi_power_convert_current_to_setting(
+				ilimit));
+	__raw_writel(temp_reg, HW_POWER_5VCTRL_ADDR);
+
+	return ilimit;
+}
+
+void ddi_power_shutdown(void)
+{
+	__raw_writel(0x3e770001, HW_POWER_RESET_ADDR);
+}
+
+void ddi_power_handle_dcdc4p2_bo(void)
+{
+	ddi_power_EnableBatteryBoInterrupt(true);
+	ddi_power_EnableDcdc4p2BoInterrupt(false);
+}
+
+void ddi_power_enable_vddio_interrupt(bool enable)
+{
+	if (enable) {
+		__raw_writel(BM_POWER_CTRL_VDDIO_BO_IRQ,
+			HW_POWER_CTRL_CLR_ADDR);
+#ifndef DISABLE_VDDIO_BO_PROTECTION
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+			HW_POWER_CTRL_SET_ADDR);
+#endif
+	} else {
+		__raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+			HW_POWER_CTRL_CLR_ADDR);
+	}
+}
+
+void ddi_power_handle_vddio_brnout(void)
+{
+	if (ddi_power_GetPmu5vStatus() == new_5v_connection) {
+		ddi_power_enable_vddio_interrupt(false);
+	} else {
+#ifdef DEBUG_IRQS
+		ddi_power_enable_vddio_interrupt(false);
+		printk(KERN_ALERT "VDDIO BO TRIED TO SHUTDOWN!!!\n");
+		return;
+#else
+		ddi_power_shutdown();
+#endif
+	}
+}
+
+void ddi_power_handle_vdd5v_droop(void)
+{
+	uint32_t temp;
+
+	/* handle errata */
+	temp = __raw_readl(HW_POWER_DCDC4P2_ADDR);
+	temp |= (BF(31, POWER_DCDC4P2_CMPTRIP) | BM_POWER_DCDC4P2_TRG);
+	__raw_writel(temp, HW_POWER_DCDC4P2_ADDR);
+
+
+	/* if battery is below brownout level, shutdown asap */
+	if (__raw_readl(HW_POWER_STS_ADDR) & BM_POWER_STS_BATT_BO)
+		ddi_power_shutdown();
+
+	/* due to 5v connect vddio bo chip bug, we need to
+	 * disable vddio interrupts until we reset the 5v
+	 * detection for 5v connect detect.  We want to allow
+	 * some debounce time before enabling connect detection.
+	 */
+	ddi_power_enable_vddio_interrupt(false);
+
+	ddi_power_EnableBatteryBoInterrupt(true);
+	ddi_power_EnableDcdc4p2BoInterrupt(false);
+	ddi_power_EnableVdd5vDroopInterrupt(false);
+
+}
+
+void ddi_power_InitOutputBrownouts(void)
+{
+	uint32_t temp;
+
+	__raw_writel(BM_POWER_CTRL_VDDD_BO_IRQ |
+		BM_POWER_CTRL_VDDA_BO_IRQ |
+		BM_POWER_CTRL_VDDIO_BO_IRQ,
+		HW_POWER_CTRL_CLR_ADDR);
+
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO,
+		HW_POWER_CTRL_SET_ADDR);
+
+	temp = __raw_readl(HW_POWER_VDDDCTRL_ADDR);
+	temp &= ~BM_POWER_VDDDCTRL_PWDN_BRNOUT;
+	__raw_writel(temp, HW_POWER_VDDDCTRL_ADDR);
+
+	temp = __raw_readl(HW_POWER_VDDACTRL_ADDR);
+	temp &= ~BM_POWER_VDDACTRL_PWDN_BRNOUT;
+	__raw_writel(temp, HW_POWER_VDDACTRL_ADDR);
+
+	temp = __raw_readl(HW_POWER_VDDIOCTRL_ADDR);
+	temp &= ~BM_POWER_VDDIOCTRL_PWDN_BRNOUT;
+	__raw_writel(temp, HW_POWER_VDDIOCTRL_ADDR);
+}
+
+/* used for debugging purposes only */
+void ddi_power_disable_power_interrupts(void)
+{
+	__raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO |
+		BM_POWER_CTRL_ENIRQ_VDD5V_DROOP |
+		BM_POWER_CTRL_ENIRQ_PSWITCH |
+		BM_POWER_CTRL_ENIRQ_DC_OK |
+		BM_POWER_CTRL_ENIRQBATT_BO |
+		BM_POWER_CTRL_ENIRQ_VDDIO_BO |
+		BM_POWER_CTRL_ENIRQ_VDDA_BO |
+		BM_POWER_CTRL_ENIRQ_VDDD_BO |
+		BM_POWER_CTRL_ENIRQ_VBUS_VALID |
+		BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+		HW_POWER_CTRL_CLR_ADDR);
+
+}
+
+bool ddi_power_Get5vDroopFlag(void)
+{
+	if (__raw_readl(HW_POWER_STS_ADDR) &
+		BM_POWER_STS_VDD5V_DROOP)
+		return true;
+	else
+		return false;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////
+//! @}
diff --git a/drivers/power/stmp37xx/ddi_power_battery.h b/drivers/power/stmp37xx/ddi_power_battery.h
new file mode 100644
index 000000000000..892feb639566
--- /dev/null
+++ b/drivers/power/stmp37xx/ddi_power_battery.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+//! \brief Battery modes
+typedef enum {
+	// 37xx battery modes
+        //! \brief LiIon battery powers the player
+	DDI_POWER_BATT_MODE_LIION           = 0,
+        //! \brief Alkaline/NiMH battery powers the player
+	DDI_POWER_BATT_MODE_ALKALINE_NIMH   = 1,
+} ddi_power_BatteryMode_t;
+
+
+//! \brief Possible 5V detection methods
+typedef enum {
+	//! \brief Use VBUSVALID comparator for detection
+	DDI_POWER_5V_VBUSVALID,
+	//! \brief Use VDD5V_GT_VDDIO comparison for detection
+	DDI_POWER_5V_VDD5V_GT_VDDIO
+} ddi_power_5vDetection_t;
+
+
+enum ddi_power_5v_status {
+	new_5v_connection,
+	existing_5v_connection,
+	new_5v_disconnection,
+	existing_5v_disconnection,
+} ;
+
+
+uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current);
+uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting);
+void ddi_power_enable_5v_to_battery_handoff(void);
+void ddi_power_execute_5v_to_battery_handoff(void);
+void ddi_power_enable_battery_to_5v_handoff(void);
+void ddi_power_execute_battery_to_5v_handoff(void);
+int ddi_power_init_battery(void);
+ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void);
+bool ddi_power_GetBatteryChargerEnabled(void);
+bool ddi_power_GetChargerPowered(void);
+void ddi_power_SetChargerPowered(bool bPowerOn);
+int ddi_power_GetChargeStatus(void);
+uint16_t ddi_power_GetBattery(void);
+uint16_t ddi_power_GetBatteryBrownout(void);
+int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV);
+uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur);
+uint16_t ddi_power_GetMaxBatteryChargeCurrent(void);
+uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh);
+uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void);
+uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current);
+bool ddi_power_Get5vPresentFlag(void);
+void ddi_power_GetDieTemp(int16_t * pLow, int16_t * pHigh);
+bool ddi_power_IsDcdcOn(void);
+void ddi_power_SetPowerClkGate(bool bGate);
+bool ddi_power_GetPowerClkGate(void);
+enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void);
+void ddi_power_EnableBatteryBoFiq(bool bEnable);
+void ddi_power_disable_5v_connection_irq(void);
+void ddi_power_enable_5v_disconnect_detection(void);
+void ddi_power_enable_5v_connect_detection(void);
+void ddi_power_Enable5vDisconnectShutdown(bool bEnable);
+void ddi_power_enable_5v_to_battery_xfer(bool bEnable);
+void ddi_power_init_4p2_protection(void);
+bool ddi_power_check_4p2_bits(void);
+void ddi_power_Start4p2Dcdc(bool battery_ready);
+void ddi_power_Init4p2Params(void);
+bool ddi_power_IsBattRdyForXfer(void);
+void ddi_power_EnableVbusDroopIrq(void);
+void ddi_power_Enable4p2(uint16_t target_current_limit_ma);
+uint16_t ddi_power_BringUp4p2Regulator(
+		uint16_t target_current_limit_ma,
+		bool b4p2_dcdc_enabled);
+void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv);
+void ddi_power_EnableBatteryBoInterrupt(bool bEnable);
+void ddi_power_handle_cmptrip(void);
+uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit);
+void ddi_power_shutdown(void);
+void ddi_power_handle_dcdc4p2_bo(void);
+void ddi_power_enable_vddio_interrupt(bool enable);
+void ddi_power_handle_vddio_brnout(void);
+void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable);
+void ddi_power_handle_vdd5v_droop(void);
+void ddi_power_InitOutputBrownouts(void);
+void ddi_power_disable_power_interrupts(void);
+bool ddi_power_Get5vDroopFlag(void);
diff --git a/drivers/power/stmp37xx/fiq.S b/drivers/power/stmp37xx/fiq.S
new file mode 100644
index 000000000000..09c185dd1536
--- /dev/null
+++ b/drivers/power/stmp37xx/fiq.S
@@ -0,0 +1,108 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+#include <asm/pgtable-hwdef.h>
+#include <mach/regs-power.h>
+#include <mach/regs-clkctrl.h>
+#include <mach/regs-timrot.h>
+
+	.align 5
+	.globl power_fiq_start
+	.globl power_fiq_end
+	.globl power_fiq_count
+	.globl lock_vector_tlb
+
+power_fiq_start:
+
+	ldr 	r8,power_reg
+	ldr	r9,[r8,#HW_POWER_CTRL ]
+	ldr	r10,power_off
+
+	@ when VDDIO_BO_IRQ,
+	@ disabled, handled in IRQ for now
+	@tst 	r9, #BM_POWER_CTRL_VDDIO_BO_IRQ
+
+
+	@ when BATT_BO_IRQ,  VDDD_BO_IRQ, VDDA_BO_IRQ, power off chip
+	ldr     r11,power_bo
+	tst	r9, r11
+	strne 	r10,[r8,#HW_POWER_RESET]
+
+	@VDD5V_DROOP_IRQ
+	tst     r9, #BM_POWER_CTRL_VDD5V_DROOP_IRQ
+	beq	    check_dcdc4p2
+
+	@ handle errata
+	ldr	r10, [r8, #HW_POWER_DCDC4P2]
+	orr	r10,r10,#(BM_POWER_DCDC4P2_TRG)
+	orr 	r10,r10,#(BF_POWER_DCDC4P2_CMPTRIP(31))
+	str	r10,[r8, #(HW_POWER_DCDC4P2)]
+
+	@ if battery is below brownout level, shutdown asap
+	ldr	r10,  [r8, #HW_POWER_STS]
+	tst	r10, #BM_POWER_STS_BATT_BO
+	ldr	r10, power_off
+	strne	r10, [r8, #HW_POWER_RESET]
+
+	@ disable viddio irq
+	mov	r11, #BM_POWER_CTRL_ENIRQ_VDDIO_BO
+	str 	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	@ enable battery BO irq
+	mov	r11, #BM_POWER_CTRL_BATT_BO_IRQ
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+	mov	r11, #BM_POWER_CTRL_ENIRQBATT_BO
+	str	r11, [r8, #HW_POWER_CTRL_SET]
+
+	@ disable dcdc4p2 interrupt
+	mov	r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	@ disable vdd5v_droop interrupt
+	mov	r11, #BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
+	str	r11, [r8, #HW_POWER_CTRL_CLR]
+
+check_dcdc4p2:
+		@ when DCDC4P2_BO_IRQ,
+	tst 	r9, #BM_POWER_CTRL_DCDC4P2_BO_IRQ
+
+	mov	r11, #BM_POWER_CTRL_BATT_BO_IRQ
+	strne	r11, [r8, #HW_POWER_CTRL_CLR]
+
+	mov	r11, #BM_POWER_CTRL_ENIRQBATT_BO
+	strne   r11, [r8, #HW_POWER_CTRL_SET]
+
+	mov	r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+	strne	r11, [r8, #HW_POWER_CTRL_CLR]
+
+
+
+	@return from fiq
+	subs    pc,lr, #4
+
+power_reg:
+	.long REGS_POWER_BASE
+power_off:
+	.long 0x3e770001
+power_bo:
+	.long BM_POWER_CTRL_BATT_BO_IRQ | \
+	      BM_POWER_CTRL_VDDA_BO_IRQ | BM_POWER_CTRL_VDDD_BO_IRQ
+power_fiq_count:
+	.long 0
+power_fiq_end:
+
+lock_vector_tlb:
+
+	mov r1, r0 @ set r1 to the value of the address to be locked down
+	mcr p15,0,r1,c8,c7,1    @ invalidate TLB single entry to ensure that
+				@ LockAddr is not already in the TLB
+	mrc p15,0,r0,c10,c0,0   @ read the lockdown register
+	orr r0,r0,#1            @ set the preserve bit
+	mcr p15,0,r0,c10,c0,0   @ write to the lockdown register
+	ldr r1,[r1]             @ TLB will miss, and entry will be loaded
+	mrc p15,0,r0,c10,c0,0   @ read the lockdown register (victim will have
+				@ incremented)
+	bic r0,r0,#1            @ clear preserve bit
+	mcr p15,0,r0,c10,c0,0   @ write to the lockdown registerADR r1,LockAddr
+	mov pc,lr		@
diff --git a/drivers/power/stmp37xx/linux.c b/drivers/power/stmp37xx/linux.c
new file mode 100644
index 000000000000..8f9703753664
--- /dev/null
+++ b/drivers/power/stmp37xx/linux.c
@@ -0,0 +1,1151 @@
+/*
+ * Linux glue to STMP3xxx battery state machine.
+ *
+ * Author: Steve Longerbeam <stevel@embeddedalley.com>
+ *
+ * Copyright (C) 2008 EmbeddedAlley Solutions Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/jiffies.h>
+#include <linux/sched.h>
+#include <mach/ddi_bc.h>
+#include "ddi_bc_internal.h"
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <mach/regulator.h>
+#include <mach/regs-power.h>
+#include <mach/regs-usbphy.h>
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <mach/regs-icoll.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/interrupt.h>
+#include <asm/fiq.h>
+
+enum application_5v_status{
+	_5v_connected_verified,
+	_5v_connected_unverified,
+	_5v_disconnected_unverified,
+	_5v_disconnected_verified,
+};
+
+struct stmp3xxx_info {
+	struct device *dev;
+	struct regulator *regulator;
+
+	struct power_supply bat;
+	struct power_supply ac;
+	struct power_supply usb;
+
+	ddi_bc_Cfg_t *sm_cfg;
+	struct mutex sm_lock;
+	struct timer_list sm_timer;
+	struct work_struct sm_work;
+	struct resource *irq_vdd5v;
+	struct resource *irq_dcdc4p2_bo;
+	struct resource *irq_batt_brnout;
+	struct resource *irq_vddd_brnout;
+	struct resource *irq_vdda_brnout;
+	struct resource *irq_vddio_brnout;
+	struct resource *irq_vdd5v_droop;
+	int is_ac_online;
+	int source_protection_mode;
+	uint32_t sm_new_5v_connection_jiffies;
+	uint32_t sm_new_5v_disconnection_jiffies;
+	enum application_5v_status sm_5v_connection_status;
+
+
+
+
+#define USB_ONLINE      0x01
+#define USB_REG_SET     0x02
+#define USB_SM_RESTART  0x04
+#define USB_SHUTDOWN    0x08
+#define USB_N_SEND      0x10
+	int is_usb_online;
+};
+
+#define to_stmp3xxx_info(x) container_of((x), struct stmp3xxx_info, bat)
+
+#ifndef NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA
+#define NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA 780
+#endif
+
+#ifndef POWERED_USB_5V_CURRENT_LIMIT_MA
+#define POWERED_USB_5V_CURRENT_LIMIT_MA 450
+#endif
+
+#ifndef UNPOWERED_USB_5V_CURRENT_LIMIT_MA
+#define UNPOWERED_USB_5V_CURRENT_LIMIT_MA 80
+#endif
+
+#ifndef _5V_DEBOUNCE_TIME_MS
+#define _5V_DEBOUNCE_TIME_MS 500
+#endif
+
+#ifndef OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV
+#define OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV 3350
+#endif
+
+#define  POWER_FIQ
+
+/* #define DEBUG_IRQS */
+
+/* There is no direct way to detect wall power presence, so assume the AC
+ * power source is valid if 5V presents and USB device is disconnected.
+ * If USB device is connected then assume that AC is offline and USB power
+ * is online.
+ */
+
+#define is_usb_plugged()(__raw_readl(REGS_USBPHY_BASE + HW_USBPHY_STATUS) & \
+		BM_USBPHY_STATUS_DEVPLUGIN_STATUS)
+
+#define is_ac_online()	\
+		(ddi_power_Get5vPresentFlag() ? (!is_usb_plugged()) : 0)
+#define is_usb_online()	\
+		(ddi_power_Get5vPresentFlag() ? (!!is_usb_plugged()) : 0)
+
+
+
+void init_protection(struct stmp3xxx_info *info)
+{
+	enum ddi_power_5v_status pmu_5v_status;
+	uint16_t battery_voltage;
+
+	pmu_5v_status = ddi_power_GetPmu5vStatus();
+	battery_voltage = ddi_power_GetBattery();
+
+	/* InitializeFiqSystem(); */
+
+	ddi_power_InitOutputBrownouts();
+
+
+	/* if we start the kernel with 4p2 already started
+	 * by the bootlets, we need to hand off from this
+	 * state to the kernel 4p2 enabled state.
+	 */
+	if ((pmu_5v_status == existing_5v_connection) &&
+		 ddi_power_check_4p2_bits()) {
+		ddi_power_enable_5v_disconnect_detection();
+
+		/* includes VBUS DROOP workaround for errata */
+		ddi_power_init_4p2_protection();
+
+		/* if we still have our 5V connection, we can disable
+		 * battery brownout interrupt.  This is because the
+		 * VDD5V DROOP IRQ handler will also shutdown if battery
+		 * is browned out and it will enable the battery brownout
+		 * and bring VBUSVALID_TRSH level back to a normal level
+		 * which caused the hardware battery brownout shutdown
+		 * to be enabled.  The benefit of this is that device
+		 * that have detachable batteries (or devices going through
+		 * the assembly line and running this firmware to test
+		 *  with) can avoid shutting down if 5V is present and
+		 *  battery voltage goes away.
+		 */
+		ddi_power_EnableBatteryBoInterrupt(false);
+
+		info->sm_5v_connection_status = _5v_connected_verified;
+	} else {
+#ifdef DEBUG_IRQS
+		if (battery_voltage <
+			OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) {
+			printk(KERN_CRIT "Polled battery voltage measurement is\
+				less than %dmV.  Kernel should be halted/\
+				shutdown\n",
+				OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV);
+
+			return;
+		}
+#endif
+		info->sm_5v_connection_status = _5v_disconnected_verified;
+		ddi_power_EnableBatteryBoInterrupt(true);
+
+	}
+
+
+	/* all brownouts are now handled software fiqs.  We
+	 * can now disable the hardware protection mechanisms
+	 *  because leaving them on yields ~2kV ESD level
+	 *  versus ~4kV ESD levels when they are off.  This
+	 *  difference is suspected to be cause by the fast
+	 *  falling edge pswitch functionality being tripped
+	 *  by ESD events.  This functionality is disabled
+	 *  when PWD_OFF is disabled.
+	 */
+#ifdef DISABLE_HARDWARE_PROTECTION_MECHANISMS
+	__raw_writel(BM_POWER_RESET_PWD_OFF,
+		HW_POWER_RESET_SET_ADDR);
+#endif
+
+
+
+
+}
+
+
+
+static void check_and_handle_5v_connection(struct stmp3xxx_info *info)
+{
+
+	switch (ddi_power_GetPmu5vStatus()) {
+
+	case new_5v_connection:
+		ddi_power_enable_5v_disconnect_detection();
+		info->sm_5v_connection_status = _5v_connected_unverified;
+
+	case existing_5v_connection:
+		if (info->sm_5v_connection_status != _5v_connected_verified) {
+			/* we allow some time to pass before considering
+			 * the 5v connection to be ready to use.  This
+			 * will give the USB system time to enumerate
+			 * (coordination with USB driver to be added
+			 * in the future).
+			 */
+
+			/* handle jiffies rollover case */
+			if ((jiffies - info->sm_new_5v_connection_jiffies)
+				< 0) {
+				info->sm_new_5v_connection_jiffies = jiffies;
+				break;
+			}
+
+			if ((jiffies_to_msecs(jiffies -
+				info->sm_new_5v_connection_jiffies)) >
+				_5V_DEBOUNCE_TIME_MS) {
+				info->sm_5v_connection_status =
+					_5v_connected_verified;
+				dev_info(info->dev,
+					"5v connection verified\n");
+				ddi_power_Enable4p2(450);
+
+
+				/* part of handling for errata.  It is
+				 *  now "somewhat" safe to
+				 * turn on vddio interrupts again
+				 */
+				ddi_power_enable_vddio_interrupt(true);
+			}
+		}
+		break;
+
+	case new_5v_disconnection:
+
+		ddi_bc_SetDisable();
+		ddi_bc_SetCurrentLimit(0);
+		if (info->regulator)
+			regulator_set_current_limit(info->regulator, 0, 0);
+		info->is_usb_online = 0;
+		info->is_ac_online = 0;
+
+		info->sm_5v_connection_status = _5v_disconnected_unverified;
+
+	case existing_5v_disconnection:
+
+		if (info->sm_5v_connection_status !=
+			_5v_disconnected_verified) {
+			if ((jiffies - info->sm_new_5v_disconnection_jiffies)
+				< 0) {
+				info->sm_new_5v_connection_jiffies = jiffies;
+				break;
+			}
+
+			if ((jiffies_to_msecs(jiffies -
+				info->sm_new_5v_disconnection_jiffies)) >
+				_5V_DEBOUNCE_TIME_MS) {
+				info->sm_5v_connection_status =
+					_5v_disconnected_verified;
+				ddi_power_execute_5v_to_battery_handoff();
+				ddi_power_enable_5v_connect_detection();
+
+				/* part of handling for errata.
+				 * It is now safe to
+				 * turn on vddio interrupts again
+				 */
+				ddi_power_enable_vddio_interrupt(true);
+				dev_info(info->dev,
+					"5v disconnection handled\n");
+
+			}
+		}
+
+		break;
+	}
+}
+
+
+static void handle_battery_voltage_changes(struct stmp3xxx_info *info)
+{
+#if 0
+	uint16_t battery_voltage;
+
+	battery_voltage = ddi_power_GetBattery();
+
+	if (info->sm_5v_connection_status != _5v_connected_verified) {
+		if (battery_voltage <
+			OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) {
+			printk(KERN_CRIT "Polled battery voltage measurement is\
+				less than %dmV.  Shutting down the \
+				system\n",
+				OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV);
+
+			shutdown_os();
+			return;
+		}
+	} else
+#endif
+	{
+		ddi_power_handle_cmptrip();
+
+		if (ddi_power_IsBattRdyForXfer())
+			ddi_power_enable_5v_to_battery_xfer(true);
+		else
+			ddi_power_enable_5v_to_battery_xfer(false);
+
+	}
+}
+
+
+/*
+ * Power properties
+ */
+static enum power_supply_property stmp3xxx_power_props[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+static int stmp3xxx_power_get_property(struct power_supply *psy,
+				     enum power_supply_property psp,
+				     union power_supply_propval *val)
+{
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		if (psy->type == POWER_SUPPLY_TYPE_MAINS)
+			/* ac online */
+			val->intval = is_ac_online();
+		else
+			/* usb online */
+			val->intval = is_usb_online();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+/*
+ * Battery properties
+ */
+static enum power_supply_property stmp3xxx_bat_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_HEALTH,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_TEMP,
+};
+
+static int stmp3xxx_bat_get_property(struct power_supply *psy,
+				     enum power_supply_property psp,
+				     union power_supply_propval *val)
+{
+	struct stmp3xxx_info *info = to_stmp3xxx_info(psy);
+	ddi_bc_State_t state;
+	ddi_bc_BrokenReason_t reason;
+	int temp_alarm;
+	int16_t temp_lo, temp_hi;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		state = ddi_bc_GetState();
+		switch (state) {
+		case DDI_BC_STATE_CONDITIONING:
+		case DDI_BC_STATE_CHARGING:
+		case DDI_BC_STATE_TOPPING_OFF:
+			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+			break;
+		case DDI_BC_STATE_DISABLED:
+			val->intval = ddi_power_Get5vPresentFlag() ?
+				POWER_SUPPLY_STATUS_NOT_CHARGING :
+			POWER_SUPPLY_STATUS_DISCHARGING;
+			break;
+		default:
+			/* TODO: detect full */
+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+			break;
+		}
+		break;
+	case POWER_SUPPLY_PROP_PRESENT:
+		/* is battery present */
+		state = ddi_bc_GetState();
+		switch (state) {
+		case DDI_BC_STATE_WAITING_TO_CHARGE:
+		case DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE:
+		case DDI_BC_STATE_CONDITIONING:
+		case DDI_BC_STATE_CHARGING:
+		case DDI_BC_STATE_TOPPING_OFF:
+		case DDI_BC_STATE_DISABLED:
+			val->intval = 1;
+			break;
+		case DDI_BC_STATE_BROKEN:
+			val->intval = !(ddi_bc_GetBrokenReason() ==
+					DDI_BC_BROKEN_NO_BATTERY_DETECTED);
+			break;
+		default:
+			val->intval = 0;
+			break;
+		}
+		break;
+	case POWER_SUPPLY_PROP_HEALTH:
+		temp_alarm = ddi_bc_RampGetDieTempAlarm();
+		if (temp_alarm) {
+			val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
+		} else {
+			state = ddi_bc_GetState();
+			switch (state) {
+			case DDI_BC_STATE_BROKEN:
+				reason = ddi_bc_GetBrokenReason();
+				val->intval =
+				   (reason == DDI_BC_BROKEN_CHARGING_TIMEOUT) ?
+					POWER_SUPPLY_HEALTH_DEAD :
+					POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
+				break;
+			case DDI_BC_STATE_UNINITIALIZED:
+				val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
+				break;
+			default:
+				val->intval = POWER_SUPPLY_HEALTH_GOOD;
+				break;
+			}
+		}
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		/* uV */
+		val->intval = ddi_power_GetBattery() * 1000;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		/* uA */
+		val->intval = ddi_power_GetMaxBatteryChargeCurrent() * 1000;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		mutex_lock(&info->sm_lock);
+		ddi_power_GetDieTemp(&temp_lo, &temp_hi);
+		mutex_unlock(&info->sm_lock);
+		val->intval = temp_lo + (temp_hi - temp_lo) / 2;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void state_machine_timer(unsigned long data)
+{
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)data;
+	ddi_bc_Cfg_t *cfg = info->sm_cfg;
+	int ret;
+
+	/* schedule next call to state machine */
+	mod_timer(&info->sm_timer,
+		  jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod));
+
+	ret = schedule_work(&info->sm_work);
+	if (!ret)
+		dev_dbg(info->dev, "state machine failed to schedule\n");
+
+}
+/*
+ * Assumption:
+ * AC power can't be switched to USB w/o system reboot
+ * and vice-versa
+ */
+static void state_machine_work(struct work_struct *work)
+{
+	struct stmp3xxx_info *info =
+		container_of(work, struct stmp3xxx_info, sm_work);
+
+	mutex_lock(&info->sm_lock);
+
+	handle_battery_voltage_changes(info);
+
+	check_and_handle_5v_connection(info);
+
+	if ((info->sm_5v_connection_status != _5v_connected_verified) ||
+			!(info->regulator)) {
+		mod_timer(&info->sm_timer, jiffies + msecs_to_jiffies(100));
+		goto out;
+	}
+
+	/* if we made it here, we have a verified 5v connection */
+
+	if (is_ac_online()) {
+		if (info->is_ac_online)
+			goto done;
+
+		/* ac supply connected */
+		dev_info(info->dev, "changed power connection to ac/5v.\n)");
+		dev_info(info->dev, "5v current limit set to %u.\n",
+			NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA);
+
+		info->is_ac_online = 1;
+		info->is_usb_online = 0;
+		ddi_power_set_4p2_ilimit(
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA);
+		ddi_bc_SetCurrentLimit(
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/);
+		if (regulator_set_current_limit(info->regulator,
+				0,
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000)) {
+			dev_err(info->dev, "reg_set_current(%duA) failed\n",
+				NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000);
+		}
+		ddi_bc_SetEnable();
+		goto done;
+	}
+
+	if (!is_usb_online())
+		goto out;
+
+	if (info->is_usb_online & USB_REG_SET)
+		goto done;
+
+	info->is_ac_online = 0;
+	info->is_usb_online |= USB_ONLINE;
+
+
+
+	if (!(info->is_usb_online & USB_N_SEND)) {
+		info->is_usb_online |= USB_N_SEND;
+	}
+
+
+	dev_dbg(info->dev, "%s: charge current set to %dmA\n", __func__,
+			POWERED_USB_5V_CURRENT_LIMIT_MA);
+
+	if (regulator_set_current_limit(info->regulator,
+		0,
+		POWERED_USB_5V_CURRENT_LIMIT_MA*1000)) {
+		dev_err(info->dev, "reg_set_current(%duA) failed\n",
+				POWERED_USB_5V_CURRENT_LIMIT_MA*1000);
+	} else {
+		ddi_bc_SetCurrentLimit(POWERED_USB_5V_CURRENT_LIMIT_MA/*mA*/);
+		ddi_bc_SetEnable();
+	}
+
+	if (info->is_usb_online & USB_SM_RESTART) {
+		info->is_usb_online &= ~USB_SM_RESTART;
+		ddi_bc_SetEnable();
+	}
+
+	info->is_usb_online |= USB_REG_SET;
+
+	dev_info(info->dev, "changed power connection to usb/5v present\n");
+
+
+done:
+	ddi_bc_StateMachine();
+out:
+	mutex_unlock(&info->sm_lock);
+}
+
+
+
+static int bc_sm_restart(struct stmp3xxx_info *info)
+{
+	ddi_bc_Status_t bcret;
+	int ret = 0;
+
+	mutex_lock(&info->sm_lock);
+
+	/* ungate power clk */
+	ddi_power_SetPowerClkGate(0);
+
+	/*
+	 * config battery charger state machine and move it to the Disabled
+	 * state. This must be done before starting the state machine.
+	 */
+	bcret = ddi_bc_Init(info->sm_cfg);
+	if (bcret != DDI_BC_STATUS_SUCCESS) {
+		dev_err(info->dev, "battery charger init failed: %d\n", bcret);
+		ret = -EIO;
+		goto out;
+	} else {
+
+		if (!info->regulator) {
+			info->regulator = regulator_get(NULL, "charger-1");
+			if (!info->regulator || IS_ERR(info->regulator)) {
+				dev_err(info->dev,
+				"%s: failed to get regulator\n", __func__);
+				info->regulator = NULL;
+			} else {
+				regulator_set_current_limit(
+						info->regulator, 0, 0);
+				regulator_set_mode(info->regulator,
+						   REGULATOR_MODE_FAST);
+			}
+		}
+	}
+
+
+
+	/* schedule first call to state machine */
+	mod_timer(&info->sm_timer, jiffies + 1);
+out:
+	mutex_unlock(&info->sm_lock);
+	return ret;
+}
+
+#ifndef POWER_FIQ
+
+static irqreturn_t stmp3xxx_irq_dcdc4p2_bo(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "dcdc4p2 brownout interrupt occurred\n");
+
+#endif
+	ddi_power_handle_dcdc4p2_bo();
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stmp3xxx_irq_batt_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "battery brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+static irqreturn_t stmp3xxx_irq_vddd_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "vddd brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+static irqreturn_t stmp3xxx_irq_vdda_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "vdda brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_shutdown();
+#endif
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stmp3xxx_irq_vdd5v_droop(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "vdd5v droop interrupt occurred\n");
+#endif
+	ddi_power_handle_vdd5v_droop();
+
+	return IRQ_HANDLED;
+}
+
+#endif /* if POWER_FIQ */
+
+static irqreturn_t stmp3xxx_irq_vddio_brnout(int irq, void *cookie)
+{
+#ifdef DEBUG_IRQS
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+	dev_info(info->dev, "vddio brownout interrupt occurred\n");
+	ddi_power_disable_power_interrupts();
+#else
+	ddi_power_handle_vddio_brnout();
+#endif
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stmp3xxx_irq_vdd5v(int irq, void *cookie)
+{
+	struct stmp3xxx_info *info = (struct stmp3xxx_info *)cookie;
+
+
+	switch (ddi_power_GetPmu5vStatus()) {
+
+	case new_5v_connection:
+
+		ddi_power_disable_5v_connection_irq();
+		dev_info(info->dev, "new 5v connection detected\n");
+		info->sm_new_5v_connection_jiffies = jiffies;
+		mod_timer(&info->sm_timer, jiffies + 1);
+		break;
+
+	case new_5v_disconnection:
+
+		/* due to 5v connect vddio bo chip bug, we need to
+		 * disable vddio interrupts until we reset the 5v
+		 * detection for 5v connect detect.  We want to allow
+		 * some debounce time before enabling connect detection.
+		 * This is handled in the vdd5v_droop interrupt for now.
+		 */
+		/* ddi_power_enable_vddio_interrupt(false); */
+
+		ddi_power_disable_5v_connection_irq();
+		dev_info(info->dev, "new 5v disconnection detected\n");
+		info->sm_new_5v_disconnection_jiffies = jiffies;
+		mod_timer(&info->sm_timer, jiffies + 1);
+		break;
+
+	default:
+
+		break;
+
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int stmp3xxx_bat_probe(struct platform_device *pdev)
+{
+	struct stmp3xxx_info *info;
+	int ret = 0;
+
+
+
+	ret = ddi_power_init_battery();
+	if (ret) {
+		printk(KERN_ERR "Aborting power driver initialization\n");
+		return 1;
+	}
+
+
+	if (!pdev->dev.platform_data) {
+		printk(KERN_ERR "%s: missing platform data\n", __func__);
+		return -ENODEV;
+	}
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->irq_vdd5v = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (info->irq_vdd5v == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vddio_brnout = platform_get_resource(
+		pdev, IORESOURCE_IRQ, 5);
+	if (info->irq_vddio_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+#ifndef POWER_FIQ
+	info->irq_dcdc4p2_bo = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (info->irq_dcdc4p2_bo == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_batt_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
+	if (info->irq_batt_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vddd_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 3);
+	if (info->irq_vddd_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+	info->irq_vdda_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 4);
+	if (info->irq_vdda_brnout == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+
+
+	info->irq_vdd5v_droop = platform_get_resource(pdev, IORESOURCE_IRQ, 6);
+	if (info->irq_vdd5v_droop == NULL) {
+		printk(KERN_ERR "%s: failed to get irq resouce\n", __func__);
+		goto free_info;
+	}
+#endif
+
+
+	platform_set_drvdata(pdev, info);
+
+	info->dev    = &pdev->dev;
+	info->sm_cfg = pdev->dev.platform_data;
+
+	/* initialize bat power_supply struct */
+	info->bat.name           = "battery";
+	info->bat.type           = POWER_SUPPLY_TYPE_BATTERY;
+	info->bat.properties     = stmp3xxx_bat_props;
+	info->bat.num_properties = ARRAY_SIZE(stmp3xxx_bat_props);
+	info->bat.get_property   = stmp3xxx_bat_get_property;
+
+	/* initialize ac power_supply struct */
+	info->ac.name           = "ac";
+	info->ac.type           = POWER_SUPPLY_TYPE_MAINS;
+	info->ac.properties     = stmp3xxx_power_props;
+	info->ac.num_properties = ARRAY_SIZE(stmp3xxx_power_props);
+	info->ac.get_property   = stmp3xxx_power_get_property;
+
+	/* initialize usb power_supply struct */
+	info->usb.name           = "usb";
+	info->usb.type           = POWER_SUPPLY_TYPE_USB;
+	info->usb.properties     = stmp3xxx_power_props;
+	info->usb.num_properties = ARRAY_SIZE(stmp3xxx_power_props);
+	info->usb.get_property   = stmp3xxx_power_get_property;
+
+	init_timer(&info->sm_timer);
+	info->sm_timer.data = (unsigned long)info;
+	info->sm_timer.function = state_machine_timer;
+
+	mutex_init(&info->sm_lock);
+	INIT_WORK(&info->sm_work, state_machine_work);
+
+	/* init LRADC channels to measure battery voltage and die temp */
+
+	__raw_writel(BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT,
+		REGS_POWER_BASE + HW_POWER_5VCTRL_CLR);
+
+	ret = bc_sm_restart(info);
+	if (ret)
+		goto free_info;
+
+
+	ret = request_irq(info->irq_vdd5v->start,
+			stmp3xxx_irq_vdd5v, IRQF_DISABLED | IRQF_SHARED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vddio_brnout->start,
+			stmp3xxx_irq_vddio_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+#ifndef POWER_FIQ
+	ret = request_irq(info->irq_dcdc4p2_bo->start,
+			stmp3xxx_irq_dcdc4p2_bo, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_batt_brnout->start,
+			stmp3xxx_irq_batt_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vddd_brnout->start,
+			stmp3xxx_irq_vddd_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+	ret = request_irq(info->irq_vdda_brnout->start,
+			stmp3xxx_irq_vdda_brnout, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+
+
+	ret = request_irq(info->irq_vdd5v_droop->start,
+			stmp3xxx_irq_vdd5v_droop, IRQF_DISABLED,
+			pdev->name, info);
+	if (ret) {
+		dev_err(info->dev, "failed to request irq\n");
+		goto stop_sm;
+	}
+#endif
+
+	ret = power_supply_register(&pdev->dev, &info->bat);
+	if (ret) {
+		dev_err(info->dev, "failed to register battery\n");
+		goto free_irq;
+	}
+
+	ret = power_supply_register(&pdev->dev, &info->ac);
+	if (ret) {
+		dev_err(info->dev, "failed to register ac power supply\n");
+		goto unregister_bat;
+	}
+
+	ret = power_supply_register(&pdev->dev, &info->usb);
+	if (ret) {
+		dev_err(info->dev, "failed to register usb power supply\n");
+		goto unregister_ac;
+	}
+
+	/* handoff protection handling from bootlets protection method
+	 * to kernel protection method
+	 */
+	init_protection(info);
+
+	/* enable usb device presence detection */
+	__raw_writel(BM_USBPHY_CTRL_ENDEVPLUGINDETECT,
+			REGS_USBPHY_BASE + HW_USBPHY_CTRL_SET);
+
+	return 0;
+
+unregister_ac:
+	power_supply_unregister(&info->ac);
+unregister_bat:
+	power_supply_unregister(&info->bat);
+free_irq:
+	free_irq(info->irq_vdd5v->start, pdev);
+	free_irq(info->irq_vddio_brnout->start, pdev);
+#ifndef	POWER_FIQ
+	free_irq(info->irq_dcdc4p2_bo->start, pdev);
+	free_irq(info->irq_batt_brnout->start, pdev);
+	free_irq(info->irq_vddd_brnout->start, pdev);
+	free_irq(info->irq_vdda_brnout->start, pdev);
+	free_irq(info->irq_vdd5v_droop->start, pdev);
+#endif
+
+stop_sm:
+	ddi_bc_ShutDown();
+free_info:
+	kfree(info);
+	return ret;
+}
+
+static int stmp3xxx_bat_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_info *info = platform_get_drvdata(pdev);
+
+	if (info->regulator)
+		regulator_put(info->regulator);
+	free_irq(info->irq_vdd5v->start, pdev);
+	free_irq(info->irq_vddio_brnout->start, pdev);
+#ifndef	POWER_FIQ
+	free_irq(info->irq_dcdc4p2_bo->start, pdev);
+	free_irq(info->irq_batt_brnout->start, pdev);
+	free_irq(info->irq_vddd_brnout->start, pdev);
+	free_irq(info->irq_vdda_brnout->start, pdev);
+	free_irq(info->irq_vdd5v_droop->start, pdev);
+#endif
+	ddi_bc_ShutDown();
+	power_supply_unregister(&info->usb);
+	power_supply_unregister(&info->ac);
+	power_supply_unregister(&info->bat);
+	return 0;
+}
+
+static void stmp3xxx_bat_shutdown(struct platform_device *pdev)
+{
+	ddi_bc_ShutDown();
+}
+
+
+#ifdef CONFIG_PM
+
+static int stmp3xxx_bat_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+	struct stmp3xxx_info *info = platform_get_drvdata(pdev);
+
+	mutex_lock(&info->sm_lock);
+
+	/* enable USB 5v wake up so don't disable irq here*/
+
+	ddi_bc_SetDisable();
+	/* cancel state machine timer */
+	del_timer_sync(&info->sm_timer);
+
+	mutex_unlock(&info->sm_lock);
+	return 0;
+}
+
+static int stmp3xxx_bat_resume(struct platform_device *pdev)
+{
+	struct stmp3xxx_info *info = platform_get_drvdata(pdev);
+	ddi_bc_Cfg_t *cfg = info->sm_cfg;
+
+	mutex_lock(&info->sm_lock);
+
+	if (is_ac_online()) {
+		/* ac supply connected */
+		dev_info(info->dev, "ac/5v present, enabling state machine\n");
+
+		info->is_ac_online = 1;
+		info->is_usb_online = 0;
+		ddi_bc_SetCurrentLimit(
+			NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/);
+		ddi_bc_SetEnable();
+	} else if (is_usb_online()) {
+		/* usb supply connected */
+		dev_info(info->dev, "usb/5v present, enabling state machine\n");
+
+		info->is_ac_online = 0;
+		info->is_usb_online = 1;
+		ddi_bc_SetCurrentLimit(POWERED_USB_5V_CURRENT_LIMIT_MA /*mA*/);
+		ddi_bc_SetEnable();
+	} else {
+		/* not powered */
+		dev_info(info->dev, "%s: 5v not present\n", __func__);
+
+		info->is_ac_online = 0;
+		info->is_usb_online = 0;
+	}
+
+	/* enable 5v irq */
+	__raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO,
+		REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+	/* reschedule calls to state machine */
+	mod_timer(&info->sm_timer,
+		  jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod));
+
+	mutex_unlock(&info->sm_lock);
+	return 0;
+}
+
+#else
+#define stmp3xxx_bat_suspend NULL
+#define stmp3xxx_bat_resume  NULL
+#endif
+
+static struct platform_driver stmp3xxx_batdrv = {
+	.probe		= stmp3xxx_bat_probe,
+	.remove		= stmp3xxx_bat_remove,
+	.shutdown       = stmp3xxx_bat_shutdown,
+	.suspend	= stmp3xxx_bat_suspend,
+	.resume		= stmp3xxx_bat_resume,
+	.driver		= {
+		.name	= "stmp3xxx-battery",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int power_relinquish(void *data, int relinquish)
+{
+	return -1;
+}
+
+static struct fiq_handler power_fiq = {
+	.name = "stmp3xxx-battery",
+	.fiq_op = power_relinquish
+};
+
+static struct pt_regs fiq_regs;
+extern char power_fiq_start[], power_fiq_end[];
+extern void lock_vector_tlb(void *);
+extern long power_fiq_count;
+static struct proc_dir_entry *power_fiq_proc;
+
+static int __init stmp3xxx_bat_init(void)
+{
+#ifdef POWER_FIQ
+	int ret;
+	ret = claim_fiq(&power_fiq);
+	if (ret) {
+		pr_err("Can't claim fiq");
+	} else {
+		get_fiq_regs(&fiq_regs);
+		set_fiq_handler(power_fiq_start, power_fiq_end-power_fiq_start);
+		lock_vector_tlb((void *)0xffff0000);
+		lock_vector_tlb(REGS_POWER_BASE);
+
+		/* disable interrupts to be configured as FIQs */
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_DCDC4P2_BO));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_BATT_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDDD_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDD18_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDD5V_DROOP));
+
+		/* Enable these interrupts as FIQs */
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ,
+			HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_DCDC4P2_BO));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ,
+			HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_BATT_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ,
+			HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDDD_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ,
+			HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD18_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ,
+			HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD5V_DROOP));
+
+		/* enable FIQ functionality */
+		__raw_writel(BM_ICOLL_CTRL_FIQ_FINAL_ENABLE,
+				HW_ICOLL_CTRL_SET_ADDR);
+
+		/* enable these interrupts */
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_DCDC4P2_BO));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_BATT_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDDD_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD18_BRNOUT));
+
+		__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+				HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD5V_DROOP));
+
+	}
+#endif
+	return platform_driver_register(&stmp3xxx_batdrv);
+}
+
+static void __exit stmp3xxx_bat_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_batdrv);
+}
+
+module_init(stmp3xxx_bat_init);
+module_exit(stmp3xxx_bat_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Steve Longerbeam <stevel@embeddedalley.com>");
+MODULE_DESCRIPTION("Linux glue to STMP3xxx battery state machine");
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index f4317798e47c..804c32cabb50 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -117,4 +117,45 @@ config REGULATOR_LP3971
 	 Say Y here to support the voltage regulators and convertors
 	 on National Semiconductors LP3971 PMIC
 
+config REGULATOR_MC13892
+	tristate "MC13892 Regulator Support"
+	depends on REGULATOR
+	depends on MXC_PMIC_MC13892
+	default y
+
+config REGULATOR_MC13783
+	tristate "MC13783 Regulator Support"
+	depends on REGULATOR
+	depends on MXC_PMIC_MC13783
+	default y
+
+config REGULATOR_MC34704
+	tristate "MC34704 Regulator Support"
+	depends on REGULATOR
+	depends on MXC_PMIC_MC34704
+	default y
+
+config REGULATOR_STMP3XXX
+	tristate "STMP3xxx Regulator Support"
+	depends on REGULATOR
+	depends on ARCH_STMP3XXX
+	default y
+
+config REGULATOR_MXS
+	tristate "MXS Regulator Support"
+	depends on REGULATOR
+	depends on ARCH_MXS
+	default y
+
+config REGULATOR_MC9S08DZ60
+	tristate "mc9s08dz60 Regulator Support"
+	depends on REGULATOR
+	depends on MXC_PMIC_MC9S08DZ60
+	default y
+
+config REGULATOR_MAX17135
+	tristate "Maxim MAX17135 Regulator Support"
+	depends on REGULATOR
+	default n
+
 endif
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4d762c4cccfd..d88116ba8139 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -2,7 +2,6 @@
 # Makefile for regulator drivers.
 #
 
-
 obj-$(CONFIG_REGULATOR) += core.o
 obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
 obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
@@ -16,5 +15,14 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
 obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
+obj-$(CONFIG_REGULATOR_MAX17135) += max17135-regulator.o
+
+obj-$(CONFIG_REGULATOR_MC13892) += reg-mc13892.o
+obj-$(CONFIG_REGULATOR_MC13783) += reg-mc13783.o
+obj-$(CONFIG_REGULATOR_MC34704) += reg-mc34704.o
+obj-$(CONFIG_REGULATOR_STMP3XXX) += stmp3xxx.o
+obj-$(CONFIG_REGULATOR_MXS) += mxs-regulator.o
+
+obj-$(CONFIG_REGULATOR_MC9S08DZ60) += reg-mc9s08dz60.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 98c3a74e9949..bfbe990c7028 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -37,7 +37,7 @@ static int has_full_constraints;
  */
 struct regulator_map {
 	struct list_head list;
-	struct device *dev;
+	const char *dev_name;   /* The dev_name() for the consumer */
 	const char *supply;
 	struct regulator_dev *regulator;
 };
@@ -857,23 +857,39 @@ out:
  * set_consumer_device_supply: Bind a regulator to a symbolic supply
  * @rdev:         regulator source
  * @consumer_dev: device the supply applies to
+ * @consumer_dev_name: dev_name() string for device supply applies to
  * @supply:       symbolic name for supply
  *
  * Allows platform initialisation code to map physical regulator
  * sources to symbolic names for supplies for use by devices.  Devices
  * should use these symbolic names to request regulators, avoiding the
  * need to provide board-specific regulator names as platform data.
+ *
+ * Only one of consumer_dev and consumer_dev_name may be specified.
  */
 static int set_consumer_device_supply(struct regulator_dev *rdev,
-	struct device *consumer_dev, const char *supply)
+	struct device *consumer_dev, const char *consumer_dev_name,
+	const char *supply)
 {
 	struct regulator_map *node;
+	int has_dev;
+
+	if (consumer_dev && consumer_dev_name)
+		return -EINVAL;
+
+	if (!consumer_dev_name && consumer_dev)
+		consumer_dev_name = dev_name(consumer_dev);
 
 	if (supply == NULL)
 		return -EINVAL;
 
+	if (consumer_dev_name != NULL)
+		has_dev = 1;
+	else
+		has_dev = 0;
+
 	list_for_each_entry(node, &regulator_map_list, list) {
-		if (consumer_dev != node->dev)
+		if (consumer_dev_name != node->dev_name)
 			continue;
 		if (strcmp(node->supply, supply) != 0)
 			continue;
@@ -886,30 +902,45 @@ static int set_consumer_device_supply(struct regulator_dev *rdev,
 		return -EBUSY;
 	}
 
-	node = kmalloc(sizeof(struct regulator_map), GFP_KERNEL);
+	node = kzalloc(sizeof(struct regulator_map), GFP_KERNEL);
 	if (node == NULL)
 		return -ENOMEM;
 
 	node->regulator = rdev;
-	node->dev = consumer_dev;
 	node->supply = supply;
 
+	if (has_dev) {
+		node->dev_name = kstrdup(consumer_dev_name, GFP_KERNEL);
+		if (node->dev_name == NULL) {
+			kfree(node);
+			return -ENOMEM;
+		}
+	}
+
 	list_add(&node->list, &regulator_map_list);
 	return 0;
 }
 
 static void unset_consumer_device_supply(struct regulator_dev *rdev,
-	struct device *consumer_dev)
+	const char *consumer_dev_name, struct device *consumer_dev)
 {
 	struct regulator_map *node, *n;
 
+	if (consumer_dev && !consumer_dev_name)
+		consumer_dev_name = dev_name(consumer_dev);
+
 	list_for_each_entry_safe(node, n, &regulator_map_list, list) {
-		if (rdev == node->regulator &&
-			consumer_dev == node->dev) {
-			list_del(&node->list);
-			kfree(node);
-			return;
-		}
+		if (rdev != node->regulator)
+			continue;
+
+		if (consumer_dev_name && node->dev_name &&
+		    strcmp(consumer_dev_name, node->dev_name))
+			continue;
+
+		list_del(&node->list);
+		kfree(node->dev_name);
+		kfree(node);
+		return;
 	}
 }
 
@@ -920,6 +951,7 @@ static void unset_regulator_supplies(struct regulator_dev *rdev)
 	list_for_each_entry_safe(node, n, &regulator_map_list, list) {
 		if (rdev == node->regulator) {
 			list_del(&node->list);
+			kfree(node->dev_name);
 			kfree(node);
 			return;
 		}
@@ -1019,21 +1051,36 @@ struct regulator *regulator_get(struct device *dev, const char *id)
 	struct regulator_dev *rdev;
 	struct regulator_map *map;
 	struct regulator *regulator = ERR_PTR(-ENODEV);
+	const char *devname = NULL;
 
 	if (id == NULL) {
 		printk(KERN_ERR "regulator: get() with no identifier\n");
 		return regulator;
 	}
 
+	if (dev)
+		devname = dev_name(dev);
+
 	mutex_lock(&regulator_list_mutex);
 
 	list_for_each_entry(map, &regulator_map_list, list) {
-		if (dev == map->dev &&
-		    strcmp(map->supply, id) == 0) {
+		/* If the mapping has a device set up it must match */
+		if (map->dev_name &&
+		    (!devname || strcmp(map->dev_name, devname)))
+			continue;
+
+		if (strcmp(map->supply, id) == 0) {
 			rdev = map->regulator;
 			goto found;
 		}
 	}
+	list_for_each_entry(rdev, &regulator_list, list) {
+		if (strcmp(rdev->desc->name, id) == 0) {
+			goto found;
+		}
+	}
+	printk(KERN_ERR "regulator: Unable to get requested regulator: %s\n",
+	       id);
 	mutex_unlock(&regulator_list_mutex);
 	return regulator;
 
@@ -2067,11 +2114,13 @@ struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
 	for (i = 0; i < init_data->num_consumer_supplies; i++) {
 		ret = set_consumer_device_supply(rdev,
 			init_data->consumer_supplies[i].dev,
+			init_data->consumer_supplies[i].dev_name,
 			init_data->consumer_supplies[i].supply);
 		if (ret < 0) {
 			for (--i; i >= 0; i--)
 				unset_consumer_device_supply(rdev,
-					init_data->consumer_supplies[i].dev);
+				    init_data->consumer_supplies[i].dev_name,
+				    init_data->consumer_supplies[i].dev);
 			goto scrub;
 		}
 	}
diff --git a/drivers/regulator/max17135-regulator.c b/drivers/regulator/max17135-regulator.c
new file mode 100644
index 000000000000..3fdec795fbeb
--- /dev/null
+++ b/drivers/regulator/max17135-regulator.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/max17135.h>
+#include <linux/gpio.h>
+
+/*
+ * Define this as 1 when using a Rev 1 MAX17135 part.  These parts have
+ * some limitations, including an inability to turn on the PMIC via I2C.
+ */
+#define MAX17135_REV 1
+
+/*
+ * PMIC Register Addresses
+ */
+enum {
+    REG_MAX17135_EXT_TEMP = 0x0,
+    REG_MAX17135_CONFIG,
+    REG_MAX17135_INT_TEMP = 0x4,
+    REG_MAX17135_STATUS,
+    REG_MAX17135_PRODUCT_REV,
+    REG_MAX17135_PRODUCT_ID,
+    REG_MAX17135_DVR,
+    REG_MAX17135_ENABLE,
+    REG_MAX17135_FAULT,  /*0x0A*/
+    REG_MAX17135_HVINP,
+    REG_MAX17135_PRGM_CTRL,
+    REG_MAX17135_TIMING1 = 0x10,    /* Timing regs base address is 0x10 */
+    REG_MAX17135_TIMING2,
+    REG_MAX17135_TIMING3,
+    REG_MAX17135_TIMING4,
+    REG_MAX17135_TIMING5,
+    REG_MAX17135_TIMING6,
+    REG_MAX17135_TIMING7,
+    REG_MAX17135_TIMING8,
+};
+#define MAX17135_REG_NUM        21
+#define MAX17135_MAX_REGISTER   0xFF
+
+/*
+ * Bitfield macros that use rely on bitfield width/shift information.
+ */
+#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
+#define BITFVAL(field, val) ((val) << (field ## _LSH))
+#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
+
+/*
+ * Shift and width values for each register bitfield
+ */
+#define EXT_TEMP_LSH    7
+#define EXT_TEMP_WID    9
+
+#define THERMAL_SHUTDOWN_LSH    0
+#define THERMAL_SHUTDOWN_WID    1
+
+#define INT_TEMP_LSH    7
+#define INT_TEMP_WID    9
+
+#define STAT_BUSY_LSH   0
+#define STAT_BUSY_WID   1
+#define STAT_OPEN_LSH   1
+#define STAT_OPEN_WID   1
+#define STAT_SHRT_LSH   2
+#define STAT_SHRT_WID   1
+
+#define PROD_REV_LSH    0
+#define PROD_REV_WID    8
+
+#define PROD_ID_LSH     0
+#define PROD_ID_WID     8
+
+#define DVR_LSH         0
+#define DVR_WID         8
+
+#define ENABLE_LSH      0
+#define ENABLE_WID      1
+#define VCOM_ENABLE_LSH 1
+#define VCOM_ENABLE_WID 1
+
+#define FAULT_FBPG_LSH      0
+#define FAULT_FBPG_WID      1
+#define FAULT_HVINP_LSH     1
+#define FAULT_HVINP_WID     1
+#define FAULT_HVINN_LSH     2
+#define FAULT_HVINN_WID     1
+#define FAULT_FBNG_LSH      3
+#define FAULT_FBNG_WID      1
+#define FAULT_HVINPSC_LSH   4
+#define FAULT_HVINPSC_WID   1
+#define FAULT_HVINNSC_LSH   5
+#define FAULT_HVINNSC_WID   1
+#define FAULT_OT_LSH        6
+#define FAULT_OT_WID        1
+#define FAULT_POK_LSH       7
+#define FAULT_POK_WID       1
+
+#define HVINP_LSH           0
+#define HVINP_WID           4
+
+#define CTRL_DVR_LSH        0
+#define CTRL_DVR_WID        1
+#define CTRL_TIMING_LSH     1
+#define CTRL_TIMING_WID     1
+
+#define TIMING1_LSH         0
+#define TIMING1_WID         8
+#define TIMING2_LSH         0
+#define TIMING2_WID         8
+#define TIMING3_LSH         0
+#define TIMING3_WID         8
+#define TIMING4_LSH         0
+#define TIMING4_WID         8
+#define TIMING5_LSH         0
+#define TIMING5_WID         8
+#define TIMING6_LSH         0
+#define TIMING6_WID         8
+#define TIMING7_LSH         0
+#define TIMING7_WID         8
+#define TIMING8_LSH         0
+#define TIMING8_WID         8
+
+/*
+ * Regulator definitions
+ *   *_MIN_uV  - minimum microvolt for regulator
+ *   *_MAX_uV  - maximum microvolt for regulator
+ *   *_STEP_uV - microvolts between regulator output levels
+ *   *_MIN_VAL - minimum register field value for regulator
+ *   *_MAX_VAL - maximum register field value for regulator
+ */
+#define MAX17135_HVINP_MIN_uV    5000000
+#define MAX17135_HVINP_MAX_uV   20000000
+#define MAX17135_HVINP_STEP_uV   1000000
+#define MAX17135_HVINP_MIN_VAL         0
+#define MAX17135_HVINP_MAX_VAL         1
+
+#define MAX17135_HVINN_MIN_uV    5000000
+#define MAX17135_HVINN_MAX_uV   20000000
+#define MAX17135_HVINN_STEP_uV   1000000
+#define MAX17135_HVINN_MIN_VAL         0
+#define MAX17135_HVINN_MAX_VAL         1
+
+#define MAX17135_GVDD_MIN_uV    5000000
+#define MAX17135_GVDD_MAX_uV   20000000
+#define MAX17135_GVDD_STEP_uV   1000000
+#define MAX17135_GVDD_MIN_VAL         0
+#define MAX17135_GVDD_MAX_VAL         1
+
+#define MAX17135_GVEE_MIN_uV    5000000
+#define MAX17135_GVEE_MAX_uV   20000000
+#define MAX17135_GVEE_STEP_uV   1000000
+#define MAX17135_GVEE_MIN_VAL         0
+#define MAX17135_GVEE_MAX_VAL         1
+
+#if (MAX17135_REV == 1)
+#define MAX17135_VCOM_MIN_uV   -4325000
+#define MAX17135_VCOM_MAX_uV    -500000
+#define MAX17135_VCOM_STEP_uV     15000
+#define MAX17135_VCOM_MIN_VAL         0
+#define MAX17135_VCOM_MAX_VAL       255
+/* Required due to discrepancy between
+ * observed VCOM programming and
+ * what is suggested in the spec.
+ */
+#define MAX17135_VCOM_FUDGE_FACTOR 330000
+#else
+#define MAX17135_VCOM_MIN_uV   -3050000
+#define MAX17135_VCOM_MAX_uV    -500000
+#define MAX17135_VCOM_STEP_uV     10000
+#define MAX17135_VCOM_MIN_VAL         0
+#define MAX17135_VCOM_MAX_VAL       255
+#define MAX17135_VCOM_FUDGE_FACTOR 330000
+#endif
+
+#define MAX17135_VCOM_VOLTAGE_DEFAULT -1250000
+
+#define MAX17135_VNEG_MIN_uV    5000000
+#define MAX17135_VNEG_MAX_uV   20000000
+#define MAX17135_VNEG_STEP_uV   1000000
+#define MAX17135_VNEG_MIN_VAL         0
+#define MAX17135_VNEG_MAX_VAL         1
+
+#define MAX17135_VPOS_MIN_uV    5000000
+#define MAX17135_VPOS_MAX_uV   20000000
+#define MAX17135_VPOS_STEP_uV   1000000
+#define MAX17135_VPOS_MIN_VAL         0
+#define MAX17135_VPOS_MAX_VAL         1
+
+struct max17135 {
+	/* chip revision */
+	int rev;
+
+	struct device *dev;
+
+	/* Platform connection */
+	struct i2c_client *i2c_client;
+
+	/* Client devices */
+	struct platform_device *pdev[MAX17135_REG_NUM];
+
+	/* GPIOs */
+	int gpio_pmic_pwrgood;
+	int gpio_pmic_vcom_ctrl;
+	int gpio_pmic_wakeup;
+	int gpio_pmic_intr;
+
+	bool vcom_setup;
+
+	int max_wait;
+};
+
+/*
+ * Regulator operations
+ */
+static int max17135_hvinp_set_voltage(struct regulator_dev *reg,
+					int minuV, int uV)
+{
+	unsigned int reg_val;
+	unsigned int fld_val;
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+
+	if ((uV >= MAX17135_HVINP_MIN_uV) &&
+	    (uV <= MAX17135_HVINP_MAX_uV))
+		fld_val = (uV - MAX17135_HVINP_MIN_uV) /
+			MAX17135_HVINP_STEP_uV;
+	else
+		return -EINVAL;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP);
+
+	reg_val &= ~BITFMASK(HVINP);
+	reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */
+
+	return i2c_smbus_write_byte_data(client, REG_MAX17135_HVINP, reg_val);
+}
+
+static int max17135_hvinp_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int reg_val;
+	unsigned int fld_val;
+	int volt;
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_HVINP);
+
+	fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH;
+
+	if ((fld_val >= MAX17135_HVINP_MIN_VAL) &&
+		(fld_val <= MAX17135_HVINP_MAX_VAL)) {
+		volt = (fld_val * MAX17135_HVINP_STEP_uV) +
+			MAX17135_HVINP_MIN_uV;
+	} else {
+		printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n");
+		volt = 0;
+	}
+	return volt;
+}
+
+static int max17135_hvinp_enable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int max17135_hvinp_disable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+/* Convert uV to the VCOM register bitfield setting */
+static inline int vcom_uV_to_rs(int uV)
+{
+	return (MAX17135_VCOM_MAX_uV - uV) / MAX17135_VCOM_STEP_uV;
+}
+
+/* Convert the VCOM register bitfield setting to uV */
+static inline int vcom_rs_to_uV(int rs)
+{
+	return MAX17135_VCOM_MAX_uV - (MAX17135_VCOM_STEP_uV * rs);
+}
+
+static int max17135_vcom_set_voltage(struct regulator_dev *reg,
+					int minuV, int uV)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+	int vcom_read;
+
+	if ((uV < MAX17135_VCOM_MIN_uV) || (uV > MAX17135_VCOM_MAX_uV))
+		return -EINVAL;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR);
+
+	/*
+	 * Only program VCOM if it is not set to the desired value.
+	 * Programming VCOM excessively degrades ability to keep
+	 * DVR register value persistent.
+	 */
+	vcom_read = vcom_rs_to_uV(reg_val) - MAX17135_VCOM_FUDGE_FACTOR;
+	if (vcom_read != MAX17135_VCOM_VOLTAGE_DEFAULT) {
+		reg_val &= ~BITFMASK(DVR);
+		reg_val |= BITFVAL(DVR,
+			vcom_uV_to_rs(uV + MAX17135_VCOM_FUDGE_FACTOR));
+		i2c_smbus_write_byte_data(client, REG_MAX17135_DVR, reg_val);
+
+		reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */
+		return i2c_smbus_write_byte_data(client,
+			REG_MAX17135_PRGM_CTRL, reg_val);
+	}
+}
+
+static int max17135_vcom_get_voltage(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_DVR);
+	return vcom_rs_to_uV(BITFEXT(reg_val, DVR));
+}
+
+static int max17135_vcom_enable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+
+	/*
+	 * Check to see if we need to set the VCOM voltage.
+	 * Should only be done one time. And, we can
+	 * only change vcom voltage if we have been enabled.
+	 */
+	if (!max17135->vcom_setup
+		&& gpio_get_value(max17135->gpio_pmic_pwrgood)) {
+		max17135_vcom_set_voltage(reg,
+			MAX17135_VCOM_VOLTAGE_DEFAULT,
+			MAX17135_VCOM_VOLTAGE_DEFAULT);
+		max17135->vcom_setup = true;
+	}
+
+	/* enable VCOM regulator output */
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(VCOM_ENABLE);
+	reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+	return 0;
+}
+
+static int max17135_vcom_disable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(VCOM_ENABLE);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+	return 0;
+}
+
+static int max17135_wait_power_good(struct max17135 *max17135)
+{
+	int i;
+
+	for (i = 0; i < max17135->max_wait * 3; i++) {
+		if (gpio_get_value(max17135->gpio_pmic_pwrgood))
+			return 0;
+
+		msleep(1);
+	}
+	return -ETIMEDOUT;
+}
+
+static int max17135_display_enable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_wakeup, 1);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(ENABLE);
+	reg_val |= BITFVAL(ENABLE, 1);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+#endif
+
+	return max17135_wait_power_good(max17135);
+}
+
+static int max17135_display_disable(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+#if (MAX17135_REV == 1)
+	gpio_set_value(max17135->gpio_pmic_wakeup, 0);
+#else
+	struct i2c_client *client = max17135->i2c_client;
+	unsigned int reg_val;
+
+	reg_val = i2c_smbus_read_byte_data(client, REG_MAX17135_ENABLE);
+	reg_val &= ~BITFMASK(ENABLE);
+	i2c_smbus_write_byte_data(client, REG_MAX17135_ENABLE, reg_val);
+	msleep(PMIC_DISABLE__V3P3_DESERT/1000);
+#endif
+	return 0;
+}
+
+static int max17135_display_is_enabled(struct regulator_dev *reg)
+{
+	struct max17135 *max17135 = rdev_get_drvdata(reg);
+	int gpio = gpio_get_value(max17135->gpio_pmic_wakeup);
+
+	if (gpio == 0)
+		return 0;
+	else
+		return 1;
+}
+
+/*
+ * Regulator operations
+ */
+
+static struct regulator_ops max17135_display_ops = {
+	.enable = max17135_display_enable,
+	.disable = max17135_display_disable,
+	.is_enabled = max17135_display_is_enabled,
+};
+
+static struct regulator_ops max17135_gvdd_ops = {
+};
+
+static struct regulator_ops max17135_gvee_ops = {
+};
+
+static struct regulator_ops max17135_hvinn_ops = {
+};
+
+static struct regulator_ops max17135_hvinp_ops = {
+	.enable = max17135_hvinp_enable,
+	.disable = max17135_hvinp_disable,
+	.get_voltage = max17135_hvinp_get_voltage,
+	.set_voltage = max17135_hvinp_set_voltage,
+};
+
+static struct regulator_ops max17135_vcom_ops = {
+	.enable = max17135_vcom_enable,
+	.disable = max17135_vcom_disable,
+	.get_voltage = max17135_vcom_get_voltage,
+	.set_voltage = max17135_vcom_set_voltage,
+};
+
+static struct regulator_ops max17135_vneg_ops = {
+};
+
+static struct regulator_ops max17135_vpos_ops = {
+};
+
+/*
+ * Regulator descriptors
+ */
+static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = {
+{
+	.name = "DISPLAY",
+	.id = MAX17135_DISPLAY,
+	.ops = &max17135_display_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "GVDD",
+	.id = MAX17135_GVDD,
+	.ops = &max17135_gvdd_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "GVEE",
+	.id = MAX17135_GVEE,
+	.ops = &max17135_gvee_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "HVINN",
+	.id = MAX17135_HVINN,
+	.ops = &max17135_hvinn_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "HVINP",
+	.id = MAX17135_HVINP,
+	.ops = &max17135_hvinp_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VCOM",
+	.id = MAX17135_VCOM,
+	.ops = &max17135_vcom_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VNEG",
+	.id = MAX17135_VNEG,
+	.ops = &max17135_vneg_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+{
+	.name = "VPOS",
+	.id = MAX17135_VPOS,
+	.ops = &max17135_vpos_ops,
+	.type = REGULATOR_VOLTAGE,
+	.owner = THIS_MODULE,
+},
+};
+
+/*
+ * Regulator init/probing/exit functions
+ */
+static int max17135_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	rdev = regulator_register(&max17135_reg[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  dev_get_drvdata(&pdev->dev));
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			max17135_reg[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+static int max17135_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct platform_driver max17135_regulator_driver = {
+	.probe = max17135_regulator_probe,
+	.remove = max17135_regulator_remove,
+	.driver = {
+		.name = "max17135-reg",
+	},
+};
+
+static int max17135_register_regulator(struct max17135 *max17135, int reg,
+				     struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	struct i2c_client *client = max17135->i2c_client;
+	/* If we can't find PMIC via I2C, we should not register regulators */
+	if (i2c_smbus_read_byte_data(client,
+		REG_MAX17135_PRODUCT_REV >= 0)) {
+		dev_err(max17135->dev,
+			"Max17135 PMIC not found!\n");
+		return -ENXIO;
+	}
+
+	if (max17135->pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("max17135-reg", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	max17135->pdev[reg] = pdev;
+
+	initdata->driver_data = max17135;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.parent = max17135->dev;
+	platform_set_drvdata(pdev, max17135);
+
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(max17135->dev,
+		       "Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		max17135->pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+
+static int max17135_i2c_probe(struct i2c_client *client,
+			    const struct i2c_device_id *id)
+{
+	int i;
+	struct max17135 *max17135;
+	struct max17135_platform_data *pdata = client->dev.platform_data;
+	int ret = 0;
+
+	if (!pdata || !pdata->regulator_init)
+		return -ENODEV;
+
+	/* Create the PMIC data structure */
+	max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL);
+	if (max17135 == NULL) {
+		kfree(client);
+		return -ENOMEM;
+	}
+
+	/* Initialize the PMIC data structure */
+	i2c_set_clientdata(client, max17135);
+	max17135->dev = &client->dev;
+	max17135->i2c_client = client;
+
+	max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
+	max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
+	max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
+	max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
+
+	max17135->vcom_setup = false;
+
+	ret = platform_driver_register(&max17135_regulator_driver);
+	if (ret < 0)
+		goto err;
+
+	for (i = 0; i <= MAX17135_VPOS; i++) {
+		ret = max17135_register_regulator(max17135, i, &pdata->regulator_init[i]);
+		if (ret != 0) {
+			dev_err(max17135->dev, "Platform init() failed: %d\n",
+			ret);
+		goto err;
+		}
+	}
+
+	max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
+		pdata->gvdd_pwrup + pdata->gvee_pwrup;
+
+	/* Initialize the PMIC device */
+	dev_info(&client->dev, "PMIC MAX17135 for eInk display\n");
+
+	return ret;
+err:
+	kfree(max17135);
+
+	return ret;
+}
+
+
+static int max17135_i2c_remove(struct i2c_client *i2c)
+{
+	struct max17135 *max17135 = i2c_get_clientdata(i2c);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(max17135->pdev); i++)
+		platform_device_unregister(max17135->pdev[i]);
+
+	platform_driver_unregister(&max17135_regulator_driver);
+
+	kfree(max17135);
+
+	return 0;
+}
+
+static const struct i2c_device_id max17135_i2c_id[] = {
+       { "max17135", 0 },
+       { }
+};
+MODULE_DEVICE_TABLE(i2c, max17135_i2c_id);
+
+
+static struct i2c_driver max17135_i2c_driver = {
+	.driver = {
+		   .name = "max17135",
+		   .owner = THIS_MODULE,
+	},
+	.probe = max17135_i2c_probe,
+	.remove = max17135_i2c_remove,
+	.id_table = max17135_i2c_id,
+};
+
+static int __init max17135_init(void)
+{
+	return i2c_add_driver(&max17135_i2c_driver);
+}
+module_init(max17135_init);
+
+static void __exit max17135_exit(void)
+{
+	i2c_del_driver(&max17135_i2c_driver);
+}
+module_exit(max17135_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("MAX17135 regulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/mxs-regulator.c b/drivers/regulator/mxs-regulator.c
new file mode 100644
index 000000000000..fd6f6a6a5286
--- /dev/null
+++ b/drivers/regulator/mxs-regulator.c
@@ -0,0 +1,301 @@
+/*
+ * Freescale STMP378X voltage regulators
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <mach/power.h>
+#include <mach/regulator.h>
+
+static int mxs_set_voltage(struct regulator_dev *reg, int MiniV, int uv)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	if (mxs_reg->rdata->set_voltage)
+		return mxs_reg->rdata->set_voltage(mxs_reg, uv);
+	else
+		return -ENOTSUPP;
+}
+
+
+static int mxs_get_voltage(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	if (mxs_reg->rdata->get_voltage)
+		return mxs_reg->rdata->get_voltage(mxs_reg);
+	else
+		return -ENOTSUPP;
+}
+
+static int mxs_set_current(struct regulator_dev *reg, int min_uA, int uA)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	if (mxs_reg->rdata->set_current)
+		return mxs_reg->rdata->set_current(mxs_reg, uA);
+	else
+		return -ENOTSUPP;
+}
+
+static int mxs_get_current(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	if (mxs_reg->rdata->get_current)
+		return mxs_reg->rdata->get_current(mxs_reg);
+	else
+		return -ENOTSUPP;
+}
+
+static int mxs_enable(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	return mxs_reg->rdata->enable(mxs_reg);
+}
+
+static int mxs_disable(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	return mxs_reg->rdata->disable(mxs_reg);
+}
+
+static int mxs_is_enabled(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	return mxs_reg->rdata->is_enabled(mxs_reg);
+}
+
+static int mxs_set_mode(struct regulator_dev *reg, unsigned int mode)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	return mxs_reg->rdata->set_mode(mxs_reg, mode);
+}
+
+static unsigned int mxs_get_mode(struct regulator_dev *reg)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	return mxs_reg->rdata->get_mode(mxs_reg);
+}
+
+static unsigned int mxs_get_optimum_mode(struct regulator_dev *reg,
+				int input_uV, int output_uV, int load_uA)
+{
+	struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg);
+
+	if (mxs_reg->rdata->get_optimum_mode)
+		return mxs_reg->rdata->get_optimum_mode(mxs_reg, input_uV,
+							 output_uV, load_uA);
+	else
+		return -ENOTSUPP;
+}
+
+static struct regulator_ops mxs_rops = {
+	.set_voltage	= mxs_set_voltage,
+	.get_voltage	= mxs_get_voltage,
+	.set_current_limit	= mxs_set_current,
+	.get_current_limit	= mxs_get_current,
+	.enable		= mxs_enable,
+	.disable	= mxs_disable,
+	.is_enabled	= mxs_is_enabled,
+	.set_mode	= mxs_set_mode,
+	.get_mode	= mxs_get_mode,
+	.get_optimum_mode = mxs_get_optimum_mode,
+};
+
+static struct regulator_desc mxs_reg_desc[] = {
+	{
+		.name = "vddd",
+		.id = MXS_VDDD,
+		.ops = &mxs_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vdda",
+		.id = MXS_VDDA,
+		.ops = &mxs_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vddio",
+		.id = MXS_VDDIO,
+		.ops = &mxs_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vddd_bo",
+		.id = MXS_VDDDBO,
+		.ops = &mxs_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "overall_current",
+		.id = MXS_OVERALL_CUR,
+		.ops = &mxs_rops,
+		.irq = 0,
+		.type = REGULATOR_CURRENT,
+		.owner = THIS_MODULE
+	},
+};
+
+static int reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	unsigned long flags;
+	struct mxs_regulator *sreg =
+		container_of(self, struct mxs_regulator , nb);
+
+	switch (event) {
+	case MXS_REG5V_IS_USB:
+		spin_lock_irqsave(&sreg->lock, flags);
+		sreg->rdata->max_current = 500000;
+		spin_unlock_irqrestore(&sreg->lock, flags);
+		break;
+	case MXS_REG5V_NOT_USB:
+		spin_lock_irqsave(&sreg->lock, flags);
+		sreg->rdata->max_current = 0x7fffffff;
+		spin_unlock_irqrestore(&sreg->lock, flags);
+		break;
+	}
+
+	return 0;
+}
+
+int mxs_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct mxs_regulator *sreg;
+	struct regulator_init_data *initdata;
+
+	sreg = platform_get_drvdata(pdev);
+	initdata = pdev->dev.platform_data;
+	sreg->cur_current = 0;
+	sreg->next_current = 0;
+	sreg->cur_voltage = 0;
+
+	init_waitqueue_head(&sreg->wait_q);
+	spin_lock_init(&sreg->lock);
+
+	if (pdev->id > MXS_OVERALL_CUR) {
+		rdesc = kzalloc(sizeof(struct regulator_desc), GFP_KERNEL);
+		memcpy(rdesc, &mxs_reg_desc[MXS_OVERALL_CUR],
+			sizeof(struct regulator_desc));
+		rdesc->name = kstrdup(sreg->rdata->name, GFP_KERNEL);
+	} else
+		rdesc = &mxs_reg_desc[pdev->id];
+
+	pr_debug("probing regulator %s %s %d\n",
+			sreg->rdata->name,
+			rdesc->name,
+			pdev->id);
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg);
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		return PTR_ERR(rdev);
+	}
+
+	if (sreg->rdata->max_current) {
+		struct regulator *regu;
+		regu = regulator_get(NULL, sreg->rdata->name);
+		sreg->nb.notifier_call = reg_callback;
+		regulator_register_notifier(regu, &sreg->nb);
+	}
+
+	return 0;
+}
+
+
+int mxs_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+
+}
+
+int mxs_register_regulator(
+		struct mxs_regulator *reg_data, int reg,
+			      struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = platform_device_alloc("mxs_reg", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->dev.platform_data = initdata;
+
+	platform_set_drvdata(pdev, reg_data);
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		pr_debug("Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+	}
+	pr_debug("register regulator %s, %d: %d\n",
+			reg_data->rdata->name, reg, ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mxs_register_regulator);
+
+struct platform_driver mxs_reg = {
+	.driver = {
+		.name	= "mxs_reg",
+	},
+	.probe	= mxs_regulator_probe,
+	.remove	= mxs_regulator_remove,
+};
+
+int mxs_regulator_init(void)
+{
+	return platform_driver_register(&mxs_reg);
+}
+
+void mxs_regulator_exit(void)
+{
+	platform_driver_unregister(&mxs_reg);
+}
+
+postcore_initcall(mxs_regulator_init);
+module_exit(mxs_regulator_exit);
diff --git a/drivers/regulator/reg-mc13783.c b/drivers/regulator/reg-mc13783.c
new file mode 100644
index 000000000000..1cc0d37481c0
--- /dev/null
+++ b/drivers/regulator/reg-mc13783.c
@@ -0,0 +1,2662 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/mfd/mc13783/core.h>
+#include <linux/platform_device.h>
+#include <linux/pmic_status.h>
+#include <linux/pmic_external.h>
+
+/*
+ * Convenience conversion.
+ * Here atm, maybe there is somewhere better for this.
+ */
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+/*!
+ * @enum regulator_voltage_sw
+ * @brief PMIC regulator SW output voltage.
+ */
+enum {
+	SW_0_9V = 0,		/*!< 0.900 V */
+	SW_0_925V,		/*!< 0.925 V */
+	SW_0_95V,		/*!< 0.950 V */
+	SW_0_975V,		/*!< 0.975 V */
+	SW_1V,			/*!< 1.000 V */
+	SW_1_025V,		/*!< 1.025 V */
+	SW_1_05V,		/*!< 1.050 V */
+	SW_1_075V,		/*!< 1.075 V */
+	SW_1_1V,		/*!< 1.100 V */
+	SW_1_125V,		/*!< 1.125 V */
+	SW_1_15V,		/*!< 1.150 V */
+	SW_1_175V,		/*!< 1.175 V */
+	SW_1_2V,		/*!< 1.200 V */
+	SW_1_225V,		/*!< 1.225 V */
+	SW_1_25V,		/*!< 1.250 V */
+	SW_1_275V,		/*!< 1.275 V */
+	SW_1_3V,		/*!< 1.300 V */
+	SW_1_325V,		/*!< 1.325 V */
+	SW_1_35V,		/*!< 1.350 V */
+	SW_1_375V,		/*!< 1.375 V */
+	SW_1_4V,		/*!< 1.400 V */
+	SW_1_425V,		/*!< 1.425 V */
+	SW_1_45V,		/*!< 1.450 V */
+	SW_1_475V,		/*!< 1.475 V */
+	SW_1_5V,		/*!< 1.500 V */
+	SW_1_525V,		/*!< 1.525 V */
+	SW_1_55V,		/*!< 1.550 V */
+	SW_1_575V,		/*!< 1.575 V */
+	SW_1_6V,		/*!< 1.600 V */
+	SW_1_625V,		/*!< 1.625 V */
+	SW_1_65V,		/*!< 1.650 V */
+	SW_1_675V,		/*!< 1.675 V */
+	SW_1_7V,		/*!< 1.700 V */
+	SW_1_8V = 36,		/*!< 1.800 V */
+	SW_1_85V = 40,		/*!< 1.850 V */
+	SW_2V = 44,		/*!< 2_000 V */
+	SW_2_1V = 48,		/*!< 2_100 V */
+	SW_2_2V = 52,		/*!< 2_200 V */
+} regulator_voltage_sw;
+
+/*!
+ * @enum regulator_voltage_violo
+ * @brief PMIC regulator VIOLO output voltage.
+ */
+enum {
+	VIOLO_1_2V = 0,		/*!< 1.2 V */
+	VIOLO_1_3V,		/*!< 1.3 V */
+	VIOLO_1_5V,		/*!< 1.5 V */
+	VIOLO_1_8V,		/*!< 1.8 V */
+} regulator_voltage_violo;
+
+/*!
+ * @enum regulator_voltage_vdig
+ * @brief PMIC regulator VDIG output voltage.
+ */
+enum {
+	VDIG_1_2V = 0,		/*!< 1.2 V */
+	VDIG_1_3V,		/*!< 1.3 V */
+	VDIG_1_5V,		/*!< 1.5 V */
+	VDIG_1_8V,		/*!< 1.8 V */
+} regulator_voltage_vdig;
+
+/*!
+ * @enum regulator_voltage_vgen
+ * @brief PMIC regulator VGEN output voltage.
+ */
+enum {
+	VGEN_1_2V = 0,		/*!< 1.2 V */
+	VGEN_1_3V,		/*!< 1.3 V */
+	VGEN_1_5V,		/*!< 1.5 V */
+	VGEN_1_8V,		/*!< 1.8 V */
+	VGEN_1_1V,		/*!< 1.1 V */
+	VGEN_2V,		/*!< 2 V */
+	VGEN_2_775V,		/*!< 2.775 V */
+	VGEN_2_4V,		/*!< 2.4 V */
+} regulator_voltage_vgen;
+
+/*!
+ * @enum regulator_voltage_vrfdig
+ * @brief PMIC regulator VRFDIG output voltage.
+ */
+enum {
+	VRFDIG_1_2V = 0,	/*!< 1.2 V */
+	VRFDIG_1_5V,		/*!< 1.5 V */
+	VRFDIG_1_8V,		/*!< 1.8 V */
+	VRFDIG_1_875V,		/*!< 1.875 V */
+} regulator_voltage_vrfdig;
+
+/*!
+ * @enum regulator_voltage_vrfref
+ * @brief PMIC regulator VRFREF output voltage.
+ */
+enum {
+	VRFREF_2_475V = 0,	/*!< 2.475 V */
+	VRFREF_2_6V,		/*!< 2.600 V */
+	VRFREF_2_7V,		/*!< 2.700 V */
+	VRFREF_2_775V,		/*!< 2.775 V */
+} regulator_voltage_vrfref;
+
+/*!
+ * @enum regulator_voltage_vrfcp
+ * @brief PMIC regulator VRFCP output voltage.
+ */
+enum {
+	VRFCP_2_7V = 0,		/*!< 2.700 V */
+	VRFCP_2_775V,		/*!< 2.775 V */
+} regulator_voltage_vrfcp;
+
+/*!
+ * @enum regulator_voltage_vsim
+ * @brief PMIC linear regulator VSIM output voltage.
+ */
+enum {
+	VSIM_1_8V = 0,		/*!< 1.8 V */
+	VSIM_2_9V,		/*!< 2.90 V */
+	VSIM_3V = 1,		/*!< 3 V */
+} regulator_voltage_vsim;
+
+/*!
+ * @enum regulator_voltage_vesim
+ * @brief PMIC regulator VESIM output voltage.
+ */
+enum {
+	VESIM_1_8V = 0,		/*!< 1.80 V */
+	VESIM_2_9V,		/*!< 2.90 V */
+} regulator_voltage_vesim;
+
+/*!
+ * @enum regulator_voltage_vcam
+ * @brief PMIC regulator VCAM output voltage.
+ */
+enum {
+	VCAM_1_5V = 0,		/*!< 1.50 V */
+	VCAM_1_8V,		/*!< 1.80 V */
+	VCAM_2_5V,		/*!< 2.50 V */
+	VCAM_2_55V,		/*!< 2.55 V */
+	VCAM_2_6V,		/*!< 2.60 V */
+	VCAM_2_75V,		/*!< 2.75 V */
+	VCAM_2_8V,		/*!< 2.80 V */
+	VCAM_3V,		/*!< 3.00 V */
+} regulator_voltage_vcam;
+
+/*!
+ * @enum regulator_voltage_vvib
+ * @brief PMIC linear regulator V_VIB output voltage.
+ */
+enum {
+	VVIB_1_3V = 0,		/*!< 1.30 V */
+	VVIB_1_8V,		/*!< 1.80 V */
+	VVIB_2V,		/*!< 2 V */
+	VVIB_3V,		/*!< 3 V */
+} regulator_voltage_vvib;
+
+/*!
+ * @enum regulator_voltage_vmmc
+ * @brief MC13783 PMIC regulator VMMC output voltage.
+ */
+enum {
+	VMMC_1_6V = 0,		/*!< 1.60 V */
+	VMMC_1_8V,		/*!< 1.80 V */
+	VMMC_2V,		/*!< 2.00 V */
+	VMMC_2_6V,		/*!< 2.60 V */
+	VMMC_2_7V,		/*!< 2.70 V */
+	VMMC_2_8V,		/*!< 2.80 V */
+	VMMC_2_9V,		/*!< 2.90 V */
+	VMMC_3V,		/*!< 3.00 V */
+} regulator_voltage_vmmc;
+
+/*!
+ * @enum regulator_voltage_vrf
+ * @brief PMIC regulator VRF output voltage.
+ */
+enum {
+	VRF_1_5V = 0,		/*!< 1.500 V */
+	VRF_1_875V,		/*!< 1.875 V */
+	VRF_2_7V,		/*!< 2.700 V */
+	VRF_2_775V,		/*!< 2.775 V */
+} regulator_voltage_vrf;
+
+/*!
+ * @enum regulator_voltage_sw3
+ * @brief PMIC Switch mode regulator SW3 output voltages.
+ */
+enum {
+	SW3_5V = 0,		/*!< 5.0 V */
+	SW3_5_5V = 3,		/*!< 5.5 V */
+} regulator_voltage_sw3;
+
+/*!
+     * The \b TPmicDVSTransitionSpeed enum defines the rate with which the
+     * voltage transition occurs.
+     */
+enum {
+	ESysDependent,
+	E25mVEach4us,
+	E25mVEach8us,
+	E25mvEach16us
+} DVS_transition_speed;
+
+/*
+ * Reg Regulator Mode 0
+ */
+#define VAUDIO_EN_LSH	0
+#define VAUDIO_EN_WID	1
+#define VAUDIO_EN_ENABLE	1
+#define VAUDIO_EN_DISABLE	0
+#define VIOHI_EN_LSH	3
+#define VIOHI_EN_WID	1
+#define VIOHI_EN_ENABLE	1
+#define VIOHI_EN_DISABLE	0
+#define VIOLO_EN_LSH	6
+#define VIOLO_EN_WID	1
+#define VIOLO_EN_ENABLE	1
+#define VIOLO_EN_DISABLE	0
+#define VDIG_EN_LSH	9
+#define VDIG_EN_WID	1
+#define VDIG_EN_ENABLE	1
+#define VDIG_EN_DISABLE	0
+#define VGEN_EN_LSH	12
+#define VGEN_EN_WID	1
+#define VGEN_EN_ENABLE	1
+#define VGEN_EN_DISABLE	0
+#define VRFDIG_EN_LSH	15
+#define VRFDIG_EN_WID	1
+#define VRFDIG_EN_ENABLE	1
+#define VRFDIG_EN_DISABLE	0
+#define VRFREF_EN_LSH	18
+#define VRFREF_EN_WID	1
+#define VRFREF_EN_ENABLE	1
+#define VRFREF_EN_DISABLE	0
+#define VRFCP_EN_LSH	21
+#define VRFCP_EN_WID	1
+#define VRFCP_EN_ENABLE	1
+#define VRFCP_EN_DISABLE	0
+
+/*
+ * Reg Regulator Mode 1
+ */
+#define VSIM_EN_LSH	0
+#define VSIM_EN_WID	1
+#define VSIM_EN_ENABLE	1
+#define VSIM_EN_DISABLE	0
+#define VESIM_EN_LSH	3
+#define VESIM_EN_WID	1
+#define VESIM_EN_ENABLE	1
+#define VESIM_EN_DISABLE	0
+#define VCAM_EN_LSH	6
+#define VCAM_EN_WID	1
+#define VCAM_EN_ENABLE	1
+#define VCAM_EN_DISABLE	0
+#define VRFBG_EN_LSH	9
+#define VRFBG_EN_WID	1
+#define VRFBG_EN_ENABLE	1
+#define VRFBG_EN_DISABLE	0
+#define VVIB_EN_LSH	11
+#define VVIB_EN_WID	1
+#define VVIB_EN_ENABLE	1
+#define VVIB_EN_DISABLE	0
+#define VRF1_EN_LSH	12
+#define VRF1_EN_WID	1
+#define VRF1_EN_ENABLE	1
+#define VRF1_EN_DISABLE	0
+#define VRF2_EN_LSH	15
+#define VRF2_EN_WID	1
+#define VRF2_EN_ENABLE	1
+#define VRF2_EN_DISABLE	0
+#define VMMC1_EN_LSH	18
+#define VMMC1_EN_WID	1
+#define VMMC1_EN_ENABLE	1
+#define VMMC1_EN_DISABLE	0
+#define VMMC2_EN_LSH	21
+#define VMMC2_EN_WID	1
+#define VMMC2_EN_ENABLE	1
+#define VMMC2_EN_DISABLE	0
+
+/*
+ * Reg Regulator Setting 0
+ */
+#define VIOLO_LSH		2
+#define VIOLO_WID		2
+#define VDIG_LSH		4
+#define VDIG_WID		2
+#define VGEN_LSH		6
+#define VGEN_WID		3
+#define VRFDIG_LSH		9
+#define VRFDIG_WID		2
+#define VRFREF_LSH		11
+#define VRFREF_WID		2
+#define VRFCP_LSH		13
+#define VRFCP_WID		1
+#define VSIM_LSH		14
+#define VSIM_WID		1
+#define VESIM_LSH		15
+#define VESIM_WID		1
+#define VCAM_LSH		16
+#define VCAM_WID		3
+
+/*
+ * Reg Regulator Setting 1
+ */
+#define VVIB_LSH		0
+#define VVIB_WID		2
+#define VRF1_LSH		2
+#define VRF1_WID		2
+#define VRF2_LSH		4
+#define VRF2_WID		2
+#define VMMC1_LSH		6
+#define VMMC1_WID		3
+#define VMMC2_LSH		9
+#define VMMC2_WID		3
+
+/*
+ * Reg Switcher 0
+ */
+#define SW1A_LSH		0
+#define SW1A_WID		6
+#define SW1A_DVS_LSH	6
+#define SW1A_DVS_WID	6
+#define SW1A_STDBY_LSH	12
+#define SW1A_STDBY_WID	6
+
+/*
+ * Reg Switcher 1
+ */
+#define SW1B_LSH		0
+#define SW1B_WID		6
+#define SW1B_DVS_LSH	6
+#define SW1B_DVS_WID	6
+#define SW1B_STDBY_LSH	12
+#define SW1B_STDBY_WID	6
+
+/*
+ * Reg Switcher 2
+ */
+#define SW2A_LSH		0
+#define SW2A_WID		6
+#define SW2A_DVS_LSH	6
+#define SW2A_DVS_WID	6
+#define SW2A_STDBY_LSH	12
+#define SW2A_STDBY_WID	6
+
+/*
+ * Reg Switcher 3
+ */
+#define SW2B_LSH		0
+#define SW2B_WID		6
+#define SW2B_DVS_LSH	6
+#define SW2B_DVS_WID	6
+#define SW2B_STDBY_LSH	12
+#define SW2B_STDBY_WID	6
+
+/*
+ * Reg Switcher 4
+ */
+#define SW1A_MODE_LSH		0
+#define SW1A_MODE_WID		2
+#define SW1A_STBY_MODE_LSH		2
+#define SW1A_STBY_MODE_WID		2
+#define SW1A_DVS_SPEED_LSH		6
+#define SW1A_DVS_SPEED_WID		2
+#define SW1B_MODE_LSH		10
+#define SW1B_MODE_WID		2
+#define SW1B_STBY_MODE_LSH		12
+#define SW1B_STBY_MODE_WID		2
+#define SW1B_DVS_SPEED_LSH		14
+#define SW1B_DVS_SPEED_WID		2
+
+/*
+ * Reg Switcher 5
+ */
+#define SW2A_MODE_LSH		0
+#define SW2A_MODE_WID		2
+#define SW2A_STBY_MODE_LSH		2
+#define SW2A_STBY_MODE_WID		2
+#define SW2A_DVS_SPEED_LSH		6
+#define SW2A_DVS_SPEED_WID		2
+#define SW2B_MODE_LSH		10
+#define SW2B_MODE_WID		2
+#define SW2B_STBY_MODE_LSH		12
+#define SW2B_STBY_MODE_WID		2
+#define SW2B_DVS_SPEED_LSH		14
+#define SW2B_DVS_SPEED_WID		2
+#define SW3_LSH			18
+#define SW3_WID			2
+#define SW3_EN_LSH			20
+#define SW3_EN_WID			2
+#define SW3_EN_ENABLE		1
+#define SW3_EN_DISABLE		0
+
+/*
+ * Reg Regulator Misc.
+ */
+#define GPO1_EN_LSH	6
+#define GPO1_EN_WID	1
+#define GPO1_EN_ENABLE	1
+#define GPO1_EN_DISABLE	0
+#define GPO2_EN_LSH	8
+#define GPO2_EN_WID	1
+#define GPO2_EN_ENABLE	1
+#define GPO2_EN_DISABLE	0
+#define GPO3_EN_LSH	10
+#define GPO3_EN_WID	1
+#define GPO3_EN_ENABLE	1
+#define GPO3_EN_DISABLE	0
+#define GPO4_EN_LSH	12
+#define GPO4_EN_WID	1
+#define GPO4_EN_ENABLE	1
+#define GPO4_EN_DISABLE	0
+
+/*
+ * Switcher mode configuration
+ */
+#define SW_MODE_SYNC_RECT_EN	0
+#define SW_MODE_PULSE_NO_SKIP_EN	1
+#define SW_MODE_PULSE_SKIP_EN	2
+#define SW_MODE_LOW_POWER_EN	3
+
+#define dvs_speed E25mvEach16us
+
+static int mc13783_vaudio_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE);
+	register_mask = BITFMASK(VAUDIO_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vaudio_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE);
+	register_mask = BITFMASK(VAUDIO_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_viohi_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE);
+	register_mask = BITFMASK(VIOHI_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_viohi_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE);
+	register_mask = BITFMASK(VIOHI_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_violo_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0, register1 = 0;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1200) && (mV < 1300))
+		voltage = VIOLO_1_2V;
+	else if ((mV >= 1300) && (mV < 1500))
+		voltage = VIOLO_1_3V;
+	else if ((mV >= 1500) && (mV < 1800))
+		voltage = VIOLO_1_5V;
+	else
+		voltage = VIOLO_1_8V;
+
+	register_val = BITFVAL(VIOLO, voltage);
+	register_mask = BITFMASK(VIOLO);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_violo_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				 &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VIOLO);
+
+	switch (voltage) {
+	case VIOLO_1_2V:
+		mV = 1200;
+		break;
+	case VIOLO_1_3V:
+		mV = 1300;
+		break;
+	case VIOLO_1_5V:
+		mV = 1500;
+		break;
+	case VIOLO_1_8V:
+		mV = 1800;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_violo_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOLO_EN, VIOLO_EN_ENABLE);
+	register_mask = BITFMASK(VIOLO_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_violo_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOLO_EN, VIOLO_EN_DISABLE);
+	register_mask = BITFMASK(VIOLO_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vdig_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1200) && (mV < 1300))
+		voltage = VDIG_1_2V;
+	else if ((mV >= 1300) && (mV < 1500))
+		voltage = VDIG_1_3V;
+	else if ((mV >= 1500) && (mV < 1800))
+		voltage = VDIG_1_5V;
+	else
+		voltage = VDIG_1_8V;
+
+	register_val = BITFVAL(VDIG, voltage);
+	register_mask = BITFMASK(VDIG);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vdig_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VDIG);
+
+	switch (voltage) {
+	case VDIG_1_2V:
+		mV = 1200;
+		break;
+	case VDIG_1_3V:
+		mV = 1300;
+		break;
+	case VDIG_1_5V:
+		mV = 1500;
+		break;
+	case VDIG_1_8V:
+		mV = 1800;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vdig_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE);
+	register_mask = BITFMASK(VDIG_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vdig_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE);
+	register_mask = BITFMASK(VDIG_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vgen_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+	int vgenid = rdev_get_id(reg);
+
+	printk(KERN_INFO "VGEN ID is %d\n", vgenid);
+
+	if ((mV >= 1100) && (mV < 1200))
+		voltage = VGEN_1_1V;
+	else if ((mV >= 1200) && (mV < 1300))
+		voltage = VGEN_1_2V;
+	else if ((mV >= 1300) && (mV < 1500))
+		voltage = VGEN_1_3V;
+	else if ((mV >= 1500) && (mV < 1800))
+		voltage = VGEN_1_5V;
+	else if ((mV >= 1800) && (mV < 2000))
+		voltage = VGEN_1_8V;
+	else if ((mV >= 2000) && (mV < 2400))
+		voltage = VGEN_2V;
+	else if ((mV >= 2400) && (mV < 2775))
+		voltage = VGEN_2_4V;
+	else
+		voltage = VGEN_2_775V;
+
+	register_val = BITFVAL(VGEN, voltage);
+	register_mask = BITFMASK(VGEN);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vgen_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VGEN);
+
+	switch (voltage) {
+	case VGEN_1_2V:
+		mV = 1200;
+		break;
+	case VGEN_1_3V:
+		mV = 1300;
+		break;
+	case VGEN_1_5V:
+		mV = 1500;
+		break;
+	case VGEN_1_8V:
+		mV = 1800;
+		break;
+	case VGEN_1_1V:
+		mV = 1100;
+		break;
+	case VGEN_2V:
+		mV = 2000;
+		break;
+	case VGEN_2_775V:
+		mV = 2775;
+		break;
+	case VGEN_2_4V:
+		mV = 2400;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vgen_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN_EN, VGEN_EN_ENABLE);
+	register_mask = BITFMASK(VGEN_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vgen_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN_EN, VGEN_EN_DISABLE);
+	register_mask = BITFMASK(VGEN_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfdig_set_voltage(struct regulator_dev *reg,
+				      int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1200) && (mV < 1500))
+		voltage = VRFDIG_1_2V;
+	else if ((mV >= 1500) && (mV < 1300))
+		voltage = VRFDIG_1_5V;
+	else if ((mV >= 1800) && (mV < 1875))
+		voltage = VRFDIG_1_8V;
+	else
+		voltage = VRFDIG_1_875V;
+
+	register_val = BITFVAL(VRFDIG, voltage);
+	register_mask = BITFMASK(VRFDIG);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfdig_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VRFDIG);
+
+	switch (voltage) {
+	case VRFDIG_1_2V:
+		mV = 1200;
+		break;
+	case VRFDIG_1_5V:
+		mV = 1500;
+		break;
+	case VRFDIG_1_8V:
+		mV = 1800;
+		break;
+	case VRFDIG_1_875V:
+		mV = 1875;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vrfdig_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_ENABLE);
+	register_mask = BITFMASK(VRFDIG_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfdig_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_DISABLE);
+	register_mask = BITFMASK(VRFDIG_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfref_set_voltage(struct regulator_dev *reg,
+				      int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2475) && (mV < 2600))
+		voltage = VRFREF_2_475V;
+	else if ((mV >= 2600) && (mV < 2700))
+		voltage = VRFREF_2_6V;
+	else if ((mV >= 2700) && (mV < 2775))
+		voltage = VRFREF_2_7V;
+	else
+		voltage = VRFREF_2_775V;
+
+	register_val = BITFVAL(VRFREF, voltage);
+	register_mask = BITFMASK(VRFREF);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfref_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VRFREF);
+
+	switch (voltage) {
+	case VRFREF_2_475V:
+		mV = 2475;
+		break;
+	case VRFREF_2_6V:
+		mV = 2600;
+		break;
+	case VRFREF_2_7V:
+		mV = 2700;
+		break;
+	case VRFREF_2_775V:
+		mV = 2775;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vrfref_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFREF_EN, VRFREF_EN_ENABLE);
+	register_mask = BITFMASK(VRFREF_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfref_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFREF_EN, VRFREF_EN_DISABLE);
+	register_mask = BITFMASK(VRFREF_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfcp_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2700) && (mV < 2775))
+		voltage = VRFCP_2_7V;
+	else
+		voltage = VRFCP_2_775V;
+
+	register_val = BITFVAL(VRFCP, voltage);
+	register_mask = BITFMASK(VRFCP);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfcp_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VRFCP);
+
+	switch (voltage) {
+	case VRFCP_2_7V:
+		mV = 2700;
+		break;
+	case VRFCP_2_775V:
+		mV = 2775;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vrfcp_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFCP_EN, VRFCP_EN_ENABLE);
+	register_mask = BITFMASK(VRFCP_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrfcp_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VRFCP_EN, VRFCP_EN_DISABLE);
+	register_mask = BITFMASK(VRFCP_EN);
+	register1 = REG_REGULATOR_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vsim_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1800) && (mV < 2900))
+		voltage = VSIM_1_8V;
+	else
+		voltage = VSIM_2_9V;
+
+	register_val = BITFVAL(VSIM, voltage);
+	register_mask = BITFMASK(VSIM);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vsim_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VSIM);
+
+	switch (voltage) {
+	case VSIM_1_8V:
+		mV = 1800;
+		break;
+	case VSIM_2_9V:
+		mV = 1900;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vsim_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VSIM_EN, VSIM_EN_ENABLE);
+	register_mask = BITFMASK(VSIM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vsim_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VSIM_EN, VSIM_EN_DISABLE);
+	register_mask = BITFMASK(VSIM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vesim_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1800) && (mV < 2900))
+		voltage = VESIM_1_8V;
+	else
+		voltage = VESIM_2_9V;
+
+	register_val = BITFVAL(VESIM, voltage);
+	register_mask = BITFMASK(VESIM);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vesim_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VESIM);
+
+	switch (voltage) {
+	case VESIM_1_8V:
+		mV = 1800;
+		break;
+	case VESIM_2_9V:
+		mV = 1900;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vesim_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VESIM_EN, VESIM_EN_ENABLE);
+	register_mask = BITFMASK(VESIM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vesim_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VESIM_EN, VESIM_EN_DISABLE);
+	register_mask = BITFMASK(VESIM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vcam_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1500) && (mV < 1800))
+		voltage = VCAM_1_5V;
+	else if ((mV >= 1800) && (mV < 2500))
+		voltage = VCAM_1_8V;
+	else if ((mV >= 2500) && (mV < 2550))
+		voltage = VCAM_2_5V;
+	else if ((mV >= 2550) && (mV < 2600))
+		voltage = VCAM_2_55V;
+	if ((mV >= 2600) && (mV < 2750))
+		voltage = VCAM_2_6V;
+	else if ((mV >= 2750) && (mV < 2800))
+		voltage = VCAM_2_75V;
+	else if ((mV >= 2800) && (mV < 3000))
+		voltage = VCAM_2_8V;
+	else
+		voltage = VCAM_3V;
+
+	register_val = BITFVAL(VCAM, voltage);
+	register_mask = BITFMASK(VCAM);
+	register1 = REG_REGULATOR_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vcam_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VCAM);
+
+	switch (voltage) {
+	case VCAM_1_5V:
+		mV = 1500;
+		break;
+	case VCAM_1_8V:
+		mV = 1800;
+		break;
+	case VCAM_2_5V:
+		mV = 2500;
+		break;
+	case VCAM_2_55V:
+		mV = 2550;
+		break;
+	case VCAM_2_6V:
+		mV = 2600;
+		break;
+	case VCAM_2_75V:
+		mV = 2750;
+		break;
+	case VCAM_2_8V:
+		mV = 2800;
+		break;
+	case VCAM_3V:
+		mV = 3000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vcam_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE);
+	register_mask = BITFMASK(VCAM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vcam_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE);
+	register_mask = BITFMASK(VCAM_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vvib_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1300) && (mV < 1800))
+		voltage = VVIB_1_3V;
+	else if ((mV >= 1800) && (mV < 2000))
+		voltage = VVIB_1_8V;
+	else if ((mV >= 2000) && (mV < 3000))
+		voltage = VVIB_2V;
+	else
+		voltage = VVIB_3V;
+
+	register_val = BITFVAL(VVIB, voltage);
+	register_mask = BITFMASK(VVIB);
+	register1 = REG_REGULATOR_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vvib_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1,
+				  &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VVIB);
+
+	switch (voltage) {
+	case VVIB_1_3V:
+		mV = 1300;
+		break;
+	case VVIB_1_8V:
+		mV = 1800;
+		break;
+	case VVIB_2V:
+		mV = 2000;
+		break;
+	case VVIB_3V:
+		mV = 3000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vvib_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VVIB_EN, VVIB_EN_ENABLE);
+	register_mask = BITFMASK(VVIB_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vvib_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VVIB_EN, VVIB_EN_DISABLE);
+	register_mask = BITFMASK(VVIB_EN);
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrf_set_voltage(struct regulator_dev *reg, int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, rf = rdev_get_id(reg), mV = uV / 1000;
+
+	if ((mV >= 1500) && (mV < 1875))
+		voltage = VRF_1_5V;
+	else if ((mV >= 1875) && (mV < 2700))
+		voltage = VRF_1_875V;
+	else if ((mV >= 2700) && (mV < 2775))
+		voltage = VRF_2_7V;
+	else
+		voltage = VRF_2_775V;
+
+	switch (rf) {
+	case MC13783_VRF1:
+		register_val = BITFVAL(VRF1, voltage);
+		register_mask = BITFMASK(VRF1);
+		break;
+	case MC13783_VRF2:
+		register_val = BITFVAL(VRF2, voltage);
+		register_mask = BITFMASK(VRF2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	register1 = REG_REGULATOR_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrf_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, rf = rdev_get_id(reg), mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1,
+				  &register_val, PMIC_ALL_BITS));
+
+	switch (rf) {
+	case MC13783_VRF1:
+		voltage = BITFEXT(register_val, VRF1);
+		break;
+	case MC13783_VRF2:
+		voltage = BITFEXT(register_val, VRF2);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	switch (voltage) {
+	case VRF_1_5V:
+		mV = 1500;
+		break;
+	case VRF_1_875V:
+		mV = 1875;
+		break;
+	case VRF_2_7V:
+		mV = 2700;
+		break;
+	case VRF_2_775V:
+		mV = 2775;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vrf_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int vrf = rdev_get_id(reg);
+
+	switch (vrf) {
+	case MC13783_VRF1:
+		register_val = BITFVAL(VRF1_EN, VRF1_EN_ENABLE);
+		register_mask = BITFMASK(VRF1_EN);
+		break;
+	case MC13783_VRF2:
+		register_val = BITFVAL(VRF2_EN, VRF2_EN_ENABLE);
+		register_mask = BITFMASK(VRF2_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vrf_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int vrf = rdev_get_id(reg);
+
+	switch (vrf) {
+	case MC13783_VRF1:
+		register_val = BITFVAL(VRF1_EN, VRF1_EN_DISABLE);
+		register_mask = BITFMASK(VRF1_EN);
+		break;
+	case MC13783_VRF2:
+		register_val = BITFVAL(VRF2_EN, VRF2_EN_DISABLE);
+		register_mask = BITFMASK(VRF2_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vmmc_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mmc = rdev_get_id(reg), mV = uV / 1000;
+
+	printk(KERN_INFO "VMMC ID is %d\n", mmc);
+
+	if ((mV >= 1600) && (mV < 1800))
+		voltage = VMMC_1_6V;
+	else if ((mV >= 1800) && (mV < 2000))
+		voltage = VMMC_1_8V;
+	else if ((mV >= 2000) && (mV < 2600))
+		voltage = VMMC_2V;
+	else if ((mV >= 2600) && (mV < 2700))
+		voltage = VMMC_2_6V;
+	else if ((mV >= 2700) && (mV < 2800))
+		voltage = VMMC_2_7V;
+	else if ((mV >= 2800) && (mV < 2900))
+		voltage = VMMC_2_8V;
+	else if ((mV >= 2900) && (mV < 3000))
+		voltage = VMMC_2_9V;
+	else
+		voltage = VMMC_3V;
+
+	switch (mmc) {
+	case MC13783_VMMC1:
+		register_val = BITFVAL(VMMC1, voltage);
+		register_mask = BITFMASK(VMMC1);
+		break;
+	case MC13783_VMMC2:
+		register_val = BITFVAL(VMMC2, voltage);
+		register_mask = BITFMASK(VMMC2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	register1 = REG_REGULATOR_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vmmc_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mmc = rdev_get_id(reg), mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1,
+				  &register_val, PMIC_ALL_BITS));
+
+	switch (mmc) {
+	case MC13783_VMMC1:
+		voltage = BITFEXT(register_val, VMMC1);
+		break;
+	case MC13783_VMMC2:
+		voltage = BITFEXT(register_val, VMMC2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (voltage) {
+	case VMMC_1_6V:
+		mV = 1600;
+		break;
+	case VMMC_1_8V:
+		mV = 1800;
+		break;
+	case VMMC_2V:
+		mV = 2000;
+		break;
+	case VMMC_2_6V:
+		mV = 2600;
+		break;
+	case VMMC_2_7V:
+		mV = 2700;
+		break;
+	case VMMC_2_8V:
+		mV = 2800;
+		break;
+	case VMMC_2_9V:
+		mV = 2900;
+		break;
+	case VMMC_3V:
+		mV = 3000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_vmmc_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int vmmc = rdev_get_id(reg);
+
+	switch (vmmc) {
+	case MC13783_VMMC1:
+		register_val = BITFVAL(VMMC1_EN, VMMC1_EN_ENABLE);
+		register_mask = BITFMASK(VMMC1_EN);
+		break;
+	case MC13783_VMMC2:
+		register_val = BITFVAL(VMMC2_EN, VMMC2_EN_ENABLE);
+		register_mask = BITFMASK(VMMC2_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_vmmc_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int vmmc = rdev_get_id(reg);
+
+	switch (vmmc) {
+	case MC13783_VMMC1:
+		register_val = BITFVAL(VMMC1_EN, VMMC1_EN_DISABLE);
+		register_mask = BITFMASK(VMMC1_EN);
+		break;
+	case MC13783_VMMC2:
+		register_val = BITFVAL(VMMC2_EN, VMMC2_EN_DISABLE);
+		register_mask = BITFMASK(VMMC2_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_REGULATOR_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_gpo_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13783_GPO1:
+		register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE);
+		register_mask = BITFMASK(GPO1_EN);
+		break;
+	case MC13783_GPO2:
+		register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE);
+		register_mask = BITFMASK(GPO2_EN);
+		break;
+	case MC13783_GPO3:
+		register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE);
+		register_mask = BITFMASK(GPO3_EN);
+		break;
+	case MC13783_GPO4:
+		register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE);
+		register_mask = BITFMASK(GPO4_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISCELLANEOUS;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_gpo_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13783_GPO1:
+		register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE);
+		register_mask = BITFMASK(GPO1_EN);
+		break;
+	case MC13783_GPO2:
+		register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE);
+		register_mask = BITFMASK(GPO2_EN);
+		break;
+	case MC13783_GPO3:
+		register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE);
+		register_mask = BITFMASK(GPO3_EN);
+		break;
+	case MC13783_GPO4:
+		register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE);
+		register_mask = BITFMASK(GPO4_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISCELLANEOUS;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw3_set_voltage(struct regulator_dev *reg, int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0, register1 = 0;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 5000) && (mV < 5500))
+		voltage = SW3_5V;
+	else
+		voltage = SW3_5_5V;
+
+	register_val = BITFVAL(SW3, voltage);
+	register_mask = BITFMASK(SW3);
+	register1 = REG_SWITCHERS_5;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw3_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5,
+				 &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, SW3);
+
+	if (voltage == SW3_5_5V)
+		mV = 5500;
+	else
+		mV = 5000;
+
+	return mV * 1000;
+}
+
+static int mc13783_sw3_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(SW3_EN, SW3_EN_ENABLE);
+	register_mask = BITFMASK(SW3_EN);
+	register1 = REG_SWITCHERS_5;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw3_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(SW3_EN, SW3_EN_DISABLE);
+	register_mask = BITFMASK(SW3_EN);
+	register1 = REG_SWITCHERS_5;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw_set_normal_voltage(struct regulator_dev *reg,
+					 int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1 = 0;
+	int voltage, sw = rdev_get_id(reg), mV = uV / 1000;
+
+	if ((mV >= 900) && (mV < 925))
+		voltage = SW_0_9V;
+	else if ((mV >= 925) && (mV < 950))
+		voltage = SW_0_925V;
+	else if ((mV >= 950) && (mV < 975))
+		voltage = SW_0_95V;
+	else if ((mV >= 975) && (mV < 1000))
+		voltage = SW_0_975V;
+	else if ((mV >= 1000) && (mV < 1025))
+		voltage = SW_1V;
+	else if ((mV >= 1025) && (mV < 1050))
+		voltage = SW_1_025V;
+	else if ((mV >= 1050) && (mV < 1075))
+		voltage = SW_1_05V;
+	else if ((mV >= 1075) && (mV < 1100))
+		voltage = SW_1_075V;
+	else if ((mV >= 1100) && (mV < 1125))
+		voltage = SW_1_1V;
+	else if ((mV >= 1125) && (mV < 1150))
+		voltage = SW_1_125V;
+	else if ((mV >= 1150) && (mV < 1175))
+		voltage = SW_1_15V;
+	else if ((mV >= 1175) && (mV < 1200))
+		voltage = SW_1_175V;
+	else if ((mV >= 1200) && (mV < 1225))
+		voltage = SW_1_2V;
+	else if ((mV >= 1225) && (mV < 1250))
+		voltage = SW_1_225V;
+	else if ((mV >= 1250) && (mV < 1275))
+		voltage = SW_1_25V;
+	else if ((mV >= 1275) && (mV < 1300))
+		voltage = SW_1_275V;
+	else if ((mV >= 1300) && (mV < 1325))
+		voltage = SW_1_3V;
+	else if ((mV >= 1325) && (mV < 1350))
+		voltage = SW_1_325V;
+	else if ((mV >= 1350) && (mV < 1375))
+		voltage = SW_1_35V;
+	else if ((mV >= 1375) && (mV < 1400))
+		voltage = SW_1_375V;
+	else if ((mV >= 1400) && (mV < 1425))
+		voltage = SW_1_4V;
+	else if ((mV >= 1425) && (mV < 1450))
+		voltage = SW_1_425V;
+	else if ((mV >= 1450) && (mV < 1475))
+		voltage = SW_1_45V;
+	else if ((mV >= 1475) && (mV < 1500))
+		voltage = SW_1_475V;
+	else if ((mV >= 1500) && (mV < 1525))
+		voltage = SW_1_5V;
+	else if ((mV >= 1525) && (mV < 1550))
+		voltage = SW_1_525V;
+	else if ((mV >= 1550) && (mV < 1575))
+		voltage = SW_1_55V;
+	else if ((mV >= 1575) && (mV < 1600))
+		voltage = SW_1_575V;
+	else if ((mV >= 1600) && (mV < 1625))
+		voltage = SW_1_6V;
+	else if ((mV >= 1625) && (mV < 1650))
+		voltage = SW_1_625V;
+	else if ((mV >= 1650) && (mV < 1675))
+		voltage = SW_1_65V;
+	else if ((mV >= 1675) && (mV < 1700))
+		voltage = SW_1_675V;
+	else if ((mV >= 1700) && (mV < 1800))
+		voltage = SW_1_7V;
+	else if ((mV >= 1800) && (mV < 1850))
+		voltage = SW_1_8V;
+	else if ((mV >= 1850) && (mV < 2000))
+		voltage = SW_1_85V;
+	else if ((mV >= 2000) && (mV < 2100))
+		voltage = SW_2V;
+	else if ((mV >= 2100) && (mV < 2200))
+		voltage = SW_2_1V;
+	else
+		voltage = SW_2_2V;
+
+	switch (sw) {
+	case MC13783_SW1A:
+		register1 = REG_SWITCHERS_0;
+		register_val = BITFVAL(SW1A, voltage);
+		register_mask = BITFMASK(SW1A);
+		break;
+	case MC13783_SW1B:
+		register1 = REG_SWITCHERS_1;
+		register_val = BITFVAL(SW1B, voltage);
+		register_mask = BITFMASK(SW1B);
+		break;
+	case MC13783_SW2A:
+		register1 = REG_SWITCHERS_2;
+		register_val = BITFVAL(SW2A, voltage);
+		register_mask = BITFMASK(SW2A);
+		break;
+	case MC13783_SW2B:
+		register1 = REG_SWITCHERS_3;
+		register_val = BITFVAL(SW2B, voltage);
+		register_mask = BITFMASK(SW2B);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw_get_normal_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0, sw = rdev_get_id(reg);
+
+	switch (sw) {
+	case MC13783_SW1A:
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW1A);
+		break;
+	case MC13783_SW1B:
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW1B);
+		break;
+	case MC13783_SW2A:
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW2A);
+		break;
+	case MC13783_SW2B:
+		CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW2B);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (voltage) {
+	case SW_0_9V:
+		mV = 900;
+		break;
+	case SW_0_925V:
+		mV = 925;
+		break;
+	case SW_0_95V:
+		mV = 950;
+		break;
+	case SW_0_975V:
+		mV = 975;
+		break;
+	case SW_1V:
+		mV = 1000;
+		break;
+	case SW_1_025V:
+		mV = 1025;
+		break;
+	case SW_1_05V:
+		mV = 1050;
+		break;
+	case SW_1_075V:
+		mV = 1075;
+		break;
+	case SW_1_1V:
+		mV = 1100;
+		break;
+	case SW_1_125V:
+		mV = 1125;
+		break;
+	case SW_1_15V:
+		mV = 1150;
+		break;
+	case SW_1_175V:
+		mV = 1175;
+		break;
+	case SW_1_2V:
+		mV = 1200;
+		break;
+	case SW_1_225V:
+		mV = 1225;
+		break;
+	case SW_1_25V:
+		mV = 1250;
+		break;
+	case SW_1_275V:
+		mV = 1275;
+		break;
+	case SW_1_3V:
+		mV = 1300;
+		break;
+	case SW_1_325V:
+		mV = 1325;
+		break;
+	case SW_1_35V:
+		mV = 1350;
+		break;
+	case SW_1_375V:
+		mV = 1375;
+		break;
+	case SW_1_4V:
+		mV = 1400;
+		break;
+	case SW_1_425V:
+		mV = 1425;
+		break;
+	case SW_1_45V:
+		mV = 1450;
+		break;
+	case SW_1_475V:
+		mV = 1475;
+		break;
+	case SW_1_5V:
+		mV = 1500;
+		break;
+	case SW_1_525V:
+		mV = 1525;
+		break;
+	case SW_1_55V:
+		mV = 1550;
+		break;
+	case SW_1_575V:
+		mV = 1575;
+		break;
+	case SW_1_6V:
+		mV = 1600;
+		break;
+	case SW_1_625V:
+		mV = 1625;
+		break;
+	case SW_1_65V:
+		mV = 1650;
+		break;
+	case SW_1_675V:
+		mV = 1675;
+		break;
+	case SW_1_7V:
+		mV = 1700;
+		break;
+	case SW_1_8V:
+		mV = 1800;
+		break;
+	case SW_1_85V:
+		mV = 1850;
+		break;
+	case SW_2V:
+		mV = 2000;
+		break;
+	case SW_2_1V:
+		mV = 2100;
+		break;
+	case SW_2_2V:
+		mV = 2200;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13783_sw_normal_enable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13783_sw_normal_disable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13783_sw_stby_enable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13783_sw_stby_disable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13783_sw_set_stby_voltage(struct regulator_dev *reg, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1 = 0;
+	int voltage, sw = rdev_get_id(reg), mV = uV / 1000;
+
+	if ((mV >= 900) && (mV < 925))
+		voltage = SW_0_9V;
+	else if ((mV >= 925) && (mV < 950))
+		voltage = SW_0_925V;
+	else if ((mV >= 950) && (mV < 975))
+		voltage = SW_0_95V;
+	else if ((mV >= 975) && (mV < 1000))
+		voltage = SW_0_975V;
+	else if ((mV >= 1000) && (mV < 1025))
+		voltage = SW_1V;
+	else if ((mV >= 1025) && (mV < 1050))
+		voltage = SW_1_025V;
+	else if ((mV >= 1050) && (mV < 1075))
+		voltage = SW_1_05V;
+	else if ((mV >= 1075) && (mV < 1100))
+		voltage = SW_1_075V;
+	else if ((mV >= 1100) && (mV < 1125))
+		voltage = SW_1_1V;
+	else if ((mV >= 1125) && (mV < 1150))
+		voltage = SW_1_125V;
+	else if ((mV >= 1150) && (mV < 1175))
+		voltage = SW_1_15V;
+	else if ((mV >= 1175) && (mV < 1200))
+		voltage = SW_1_175V;
+	else if ((mV >= 1200) && (mV < 1225))
+		voltage = SW_1_2V;
+	else if ((mV >= 1225) && (mV < 1250))
+		voltage = SW_1_225V;
+	else if ((mV >= 1250) && (mV < 1275))
+		voltage = SW_1_25V;
+	else if ((mV >= 1275) && (mV < 1300))
+		voltage = SW_1_275V;
+	else if ((mV >= 1300) && (mV < 1325))
+		voltage = SW_1_3V;
+	else if ((mV >= 1325) && (mV < 1350))
+		voltage = SW_1_325V;
+	else if ((mV >= 1350) && (mV < 1375))
+		voltage = SW_1_35V;
+	else if ((mV >= 1375) && (mV < 1400))
+		voltage = SW_1_375V;
+	else if ((mV >= 1400) && (mV < 1425))
+		voltage = SW_1_4V;
+	else if ((mV >= 1425) && (mV < 1450))
+		voltage = SW_1_425V;
+	else if ((mV >= 1450) && (mV < 1475))
+		voltage = SW_1_45V;
+	else if ((mV >= 1475) && (mV < 1500))
+		voltage = SW_1_475V;
+	else if ((mV >= 1500) && (mV < 1525))
+		voltage = SW_1_5V;
+	else if ((mV >= 1525) && (mV < 1550))
+		voltage = SW_1_525V;
+	else if ((mV >= 1550) && (mV < 1575))
+		voltage = SW_1_55V;
+	else if ((mV >= 1575) && (mV < 1600))
+		voltage = SW_1_575V;
+	else if ((mV >= 1600) && (mV < 1625))
+		voltage = SW_1_6V;
+	else if ((mV >= 1625) && (mV < 1650))
+		voltage = SW_1_625V;
+	else if ((mV >= 1650) && (mV < 1675))
+		voltage = SW_1_65V;
+	else if ((mV >= 1675) && (mV < 1700))
+		voltage = SW_1_675V;
+	else if ((mV >= 1700) && (mV < 1800))
+		voltage = SW_1_7V;
+	else if ((mV >= 1800) && (mV < 1850))
+		voltage = SW_1_8V;
+	else if ((mV >= 1850) && (mV < 2000))
+		voltage = SW_1_85V;
+	else if ((mV >= 2000) && (mV < 2100))
+		voltage = SW_2V;
+	else if ((mV >= 2100) && (mV < 2200))
+		voltage = SW_2_1V;
+	else
+		voltage = SW_2_2V;
+
+	switch (sw) {
+	case MC13783_SW1A:
+		register1 = REG_SWITCHERS_0;
+		register_val = BITFVAL(SW1A_STDBY, voltage);
+		register_mask = BITFMASK(SW1A_STDBY);
+		break;
+	case MC13783_SW1B:
+		register1 = REG_SWITCHERS_1;
+		register_val = BITFVAL(SW1B_STDBY, voltage);
+		register_mask = BITFMASK(SW1B_STDBY);
+		break;
+	case MC13783_SW2A:
+		register1 = REG_SWITCHERS_2;
+		register_val = BITFVAL(SW2A_STDBY, voltage);
+		register_mask = BITFMASK(SW2A_STDBY);
+		break;
+	case MC13783_SW2B:
+		register1 = REG_SWITCHERS_3;
+		register_val = BITFVAL(SW2B_STDBY, voltage);
+		register_mask = BITFMASK(SW2B_STDBY);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13783_sw_set_normal_mode(struct regulator_dev *reg,
+				      unsigned int mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int register1 = 0;
+	unsigned int l_mode;
+	int sw = rdev_get_id(reg);
+
+	switch (mode) {
+	case REGULATOR_MODE_FAST:
+		/* SYNC RECT mode */
+		l_mode = SW_MODE_SYNC_RECT_EN;
+		break;
+	case REGULATOR_MODE_NORMAL:
+		/* PULSE SKIP mode */
+		l_mode = SW_MODE_PULSE_SKIP_EN;
+		break;
+	case REGULATOR_MODE_IDLE:
+		/* LOW POWER mode */
+		l_mode = SW_MODE_LOW_POWER_EN;
+		break;
+	case REGULATOR_MODE_STANDBY:
+		/* NO PULSE SKIP mode */
+		l_mode = SW_MODE_PULSE_NO_SKIP_EN;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (sw) {
+	case MC13783_SW1A:
+		reg_val = BITFVAL(SW1A_MODE, l_mode);
+		reg_mask = BITFMASK(SW1A_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW1B:
+		reg_val = BITFVAL(SW1B_MODE, l_mode);
+		reg_mask = BITFMASK(SW1B_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW2A:
+		reg_val = BITFVAL(SW2A_MODE, l_mode);
+		reg_mask = BITFMASK(SW2A_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	case MC13783_SW2B:
+		reg_val = BITFVAL(SW2B_MODE, l_mode);
+		reg_mask = BITFMASK(SW2B_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return pmic_write_reg(register1, reg_val, reg_mask);
+}
+
+static unsigned int mc13783_sw_get_normal_mode(struct regulator_dev *reg)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int register1 = 0;
+	unsigned int l_mode = 0;
+	int sw = rdev_get_id(reg);
+	int ret = 0;
+
+	switch (sw) {
+	case MC13783_SW1A:
+		reg_mask = BITFMASK(SW1A_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW1B:
+		reg_mask = BITFMASK(SW1B_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW2A:
+		reg_mask = BITFMASK(SW2A_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	case MC13783_SW2B:
+		reg_mask = BITFMASK(SW2B_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = pmic_read_reg(register1, &reg_val, reg_mask);
+	if (ret != 0)
+		return ret;
+
+	switch (sw) {
+	case MC13783_SW1A:
+		l_mode = BITFEXT(reg_val, SW1A_MODE);
+		break;
+	case MC13783_SW1B:
+		l_mode = BITFEXT(reg_val, SW1B_MODE);
+		break;
+	case MC13783_SW2A:
+		l_mode = BITFEXT(reg_val, SW2A_MODE);
+		break;
+	case MC13783_SW2B:
+		l_mode = BITFEXT(reg_val, SW2B_MODE);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (l_mode == SW_MODE_SYNC_RECT_EN) {
+		return REGULATOR_MODE_FAST;
+	} else if (l_mode == SW_MODE_PULSE_NO_SKIP_EN) {
+		return REGULATOR_MODE_STANDBY;
+	} else if (l_mode == SW_MODE_PULSE_SKIP_EN) {
+		return REGULATOR_MODE_NORMAL;
+	} else if (l_mode == SW_MODE_LOW_POWER_EN) {
+		return REGULATOR_MODE_IDLE;
+	} else {
+		return -EINVAL;
+	}
+}
+
+static int mc13783_sw_set_stby_mode(struct regulator_dev *reg,
+				    unsigned int mode)
+{
+	unsigned int reg_val = 0, reg_mask = 0;
+	unsigned int register1 = 0;
+	unsigned int l_mode;
+	int sw = rdev_get_id(reg);
+
+	switch (mode) {
+	case REGULATOR_MODE_FAST:
+		/* SYNC RECT mode */
+		l_mode = SW_MODE_SYNC_RECT_EN;
+		break;
+	case REGULATOR_MODE_NORMAL:
+		/* PULSE SKIP mode */
+		l_mode = SW_MODE_PULSE_SKIP_EN;
+		break;
+	case REGULATOR_MODE_IDLE:
+		/* LOW POWER mode */
+		l_mode = SW_MODE_LOW_POWER_EN;
+		break;
+	case REGULATOR_MODE_STANDBY:
+		/* NO PULSE SKIP mode */
+		l_mode = SW_MODE_PULSE_NO_SKIP_EN;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (sw) {
+	case MC13783_SW1A:
+		reg_val = BITFVAL(SW1A_STBY_MODE, l_mode);
+		reg_mask = BITFMASK(SW1A_STBY_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW1B:
+		reg_val = BITFVAL(SW1B_STBY_MODE, l_mode);
+		reg_mask = BITFMASK(SW1B_STBY_MODE);
+		register1 = REG_SWITCHERS_4;
+		break;
+	case MC13783_SW2A:
+		reg_val = BITFVAL(SW2A_STBY_MODE, l_mode);
+		reg_mask = BITFMASK(SW2A_STBY_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	case MC13783_SW2B:
+		reg_val = BITFVAL(SW2B_STBY_MODE, l_mode);
+		reg_mask = BITFMASK(SW2B_STBY_MODE);
+		register1 = REG_SWITCHERS_5;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return pmic_write_reg(register1, reg_val, reg_mask);
+}
+
+static struct regulator_ops mc13783_vaudio_ops = {
+	.enable = mc13783_vaudio_enable,
+	.disable = mc13783_vaudio_disable,
+};
+
+static struct regulator_ops mc13783_viohi_ops = {
+	.enable = mc13783_viohi_enable,
+	.disable = mc13783_viohi_disable,
+};
+
+static struct regulator_ops mc13783_violo_ops = {
+	.set_voltage = mc13783_violo_set_voltage,
+	.get_voltage = mc13783_violo_get_voltage,
+	.enable = mc13783_violo_enable,
+	.disable = mc13783_violo_disable,
+};
+
+static struct regulator_ops mc13783_vdig_ops = {
+	.set_voltage = mc13783_vdig_set_voltage,
+	.get_voltage = mc13783_vdig_get_voltage,
+	.enable = mc13783_vdig_enable,
+	.disable = mc13783_vdig_disable,
+};
+
+static struct regulator_ops mc13783_vgen_ops = {
+	.set_voltage = mc13783_vgen_set_voltage,
+	.get_voltage = mc13783_vgen_get_voltage,
+	.enable = mc13783_vgen_enable,
+	.disable = mc13783_vgen_disable,
+};
+
+static struct regulator_ops mc13783_vrfdig_ops = {
+	.set_voltage = mc13783_vrfdig_set_voltage,
+	.get_voltage = mc13783_vrfdig_get_voltage,
+	.enable = mc13783_vrfdig_enable,
+	.disable = mc13783_vrfdig_disable,
+};
+
+static struct regulator_ops mc13783_vrfref_ops = {
+	.set_voltage = mc13783_vrfref_set_voltage,
+	.get_voltage = mc13783_vrfref_get_voltage,
+	.enable = mc13783_vrfref_enable,
+	.disable = mc13783_vrfref_disable,
+};
+
+static struct regulator_ops mc13783_vrfcp_ops = {
+	.set_voltage = mc13783_vrfcp_set_voltage,
+	.get_voltage = mc13783_vrfcp_get_voltage,
+	.enable = mc13783_vrfcp_enable,
+	.disable = mc13783_vrfcp_disable,
+};
+
+static struct regulator_ops mc13783_vsim_ops = {
+	.set_voltage = mc13783_vsim_set_voltage,
+	.get_voltage = mc13783_vsim_get_voltage,
+	.enable = mc13783_vsim_enable,
+	.disable = mc13783_vsim_disable,
+};
+
+static struct regulator_ops mc13783_vesim_ops = {
+	.set_voltage = mc13783_vesim_set_voltage,
+	.get_voltage = mc13783_vesim_get_voltage,
+	.enable = mc13783_vesim_enable,
+	.disable = mc13783_vesim_disable,
+};
+
+static struct regulator_ops mc13783_vcam_ops = {
+	.set_voltage = mc13783_vcam_set_voltage,
+	.get_voltage = mc13783_vcam_get_voltage,
+	.enable = mc13783_vcam_enable,
+	.disable = mc13783_vcam_disable,
+};
+
+static struct regulator_ops mc13783_vvib_ops = {
+	.set_voltage = mc13783_vvib_set_voltage,
+	.get_voltage = mc13783_vvib_get_voltage,
+	.enable = mc13783_vvib_enable,
+	.disable = mc13783_vvib_disable,
+};
+
+static struct regulator_ops mc13783_vrf_ops = {
+	.set_voltage = mc13783_vrf_set_voltage,
+	.get_voltage = mc13783_vrf_get_voltage,
+	.enable = mc13783_vrf_enable,
+	.disable = mc13783_vrf_disable,
+};
+
+static struct regulator_ops mc13783_vmmc_ops = {
+	.set_voltage = mc13783_vmmc_set_voltage,
+	.get_voltage = mc13783_vmmc_get_voltage,
+	.enable = mc13783_vmmc_enable,
+	.disable = mc13783_vmmc_disable,
+};
+
+static struct regulator_ops mc13783_gpo_ops = {
+	.enable = mc13783_gpo_enable,
+	.disable = mc13783_gpo_disable,
+};
+
+static struct regulator_ops mc13783_sw3_ops = {
+	.set_voltage = mc13783_sw3_set_voltage,
+	.get_voltage = mc13783_sw3_get_voltage,
+	.enable = mc13783_sw3_enable,
+	.disable = mc13783_sw3_disable,
+};
+
+static struct regulator_ops mc13783_sw1_ops = {
+	.set_voltage = mc13783_sw_set_normal_voltage,
+	.get_voltage = mc13783_sw_get_normal_voltage,
+	.get_mode = mc13783_sw_get_normal_mode,
+	.set_mode = mc13783_sw_set_normal_mode,
+	.set_suspend_voltage = mc13783_sw_set_stby_voltage,
+	.set_suspend_enable = mc13783_sw_stby_enable,
+	.set_suspend_disable = mc13783_sw_stby_disable,
+	.set_suspend_mode = mc13783_sw_set_stby_mode,
+};
+
+static struct regulator_ops mc13783_sw_normal_ops = {
+	.set_voltage = mc13783_sw_set_normal_voltage,
+	.get_voltage = mc13783_sw_get_normal_voltage,
+	.get_mode = mc13783_sw_get_normal_mode,
+	.set_mode = mc13783_sw_set_normal_mode,
+	.enable = mc13783_sw_normal_enable,
+	.disable = mc13783_sw_normal_disable,
+};
+
+static struct regulator_desc reg_mc13783[] = {
+	{
+		.name = "SW1A",
+		.id = MC13783_SW1A,
+		.ops = &mc13783_sw1_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW1B",
+		.id = MC13783_SW1B,
+		.ops = &mc13783_sw_normal_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW2A",
+		.id = MC13783_SW2A,
+		.ops = &mc13783_sw_normal_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW2B",
+		.id = MC13783_SW2B,
+		.ops = &mc13783_sw_normal_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW3",
+		.id = MC13783_SW3,
+		.ops = &mc13783_sw3_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VAUDIO",
+		.id = MC13783_VAUDIO,
+		.ops = &mc13783_vaudio_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VIOHI",
+		.id = MC13783_VIOHI,
+		.ops = &mc13783_viohi_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VIOLO",
+		.id = MC13783_VIOLO,
+		.ops = &mc13783_violo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VDIG",
+		.id = MC13783_VDIG,
+		.ops = &mc13783_vdig_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VGEN",
+		.id = MC13783_VGEN,
+		.ops = &mc13783_vgen_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRFDIG",
+		.id = MC13783_VRFDIG,
+		.ops = &mc13783_vrfdig_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRFREF",
+		.id = MC13783_VRFREF,
+		.ops = &mc13783_vrfref_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRFCP",
+		.id = MC13783_VRFCP,
+		.ops = &mc13783_vrfcp_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VSIM",
+		.id = MC13783_VSIM,
+		.ops = &mc13783_vsim_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VESIM",
+		.id = MC13783_VESIM,
+		.ops = &mc13783_vesim_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VCAM",
+		.id = MC13783_VCAM,
+		.ops = &mc13783_vcam_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRFBG",
+		.id = MC13783_VRFBG,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VVIB",
+		.id = MC13783_VVIB,
+		.ops = &mc13783_vvib_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRF1",
+		.id = MC13783_VRF1,
+		.ops = &mc13783_vrf_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VRF2",
+		.id = MC13783_VRF2,
+		.ops = &mc13783_vrf_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VMMC1",
+		.id = MC13783_VMMC1,
+		.ops = &mc13783_vmmc_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VMMC2",
+		.id = MC13783_VMMC2,
+		.ops = &mc13783_vmmc_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO1",
+		.id = MC13783_GPO1,
+		.ops = &mc13783_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO2",
+		.id = MC13783_GPO2,
+		.ops = &mc13783_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO3",
+		.id = MC13783_GPO3,
+		.ops = &mc13783_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO4",
+		.id = MC13783_GPO4,
+		.ops = &mc13783_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+};
+
+/*
+ * Init and Exit
+ */
+
+static int reg_mc13783_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	/* register regulator */
+	rdev = regulator_register(&reg_mc13783[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  dev_get_drvdata(&pdev->dev));
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			reg_mc13783[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+	platform_set_drvdata(pdev, rdev);
+
+	return 0;
+}
+
+static int mc13783_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+}
+
+int mc13783_register_regulator(struct mc13783 *mc13783, int reg,
+			       struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	if (mc13783->pmic.pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("mc13783-regulatr", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	mc13783->pmic.pdev[reg] = pdev;
+
+	initdata->driver_data = mc13783;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.parent = mc13783->dev;
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(mc13783->dev, "Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		mc13783->pmic.pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mc13783_register_regulator);
+
+static struct platform_driver mc13783_regulator_driver = {
+	.probe = reg_mc13783_probe,
+	.remove = mc13783_regulator_remove,
+	.driver		= {
+		.name	= "mc13783-regulatr",
+			/* o left out due to string length */
+	},
+};
+
+static int __init mc13783_regulator_subsys_init(void)
+{
+	return platform_driver_register(&mc13783_regulator_driver);
+}
+subsys_initcall(mc13783_regulator_subsys_init);
+
+static void __exit mc13783_regulator_exit(void)
+{
+	platform_driver_unregister(&mc13783_regulator_driver);
+}
+module_exit(mc13783_regulator_exit);
+
+
+/* Module information */
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC13783 Regulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/reg-mc13892.c b/drivers/regulator/reg-mc13892.c
new file mode 100644
index 000000000000..e10cc70b2e02
--- /dev/null
+++ b/drivers/regulator/reg-mc13892.c
@@ -0,0 +1,1850 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/mfd/mc13892/core.h>
+#include <linux/platform_device.h>
+#include <linux/pmic_status.h>
+#include <linux/pmic_external.h>
+
+/*
+ * Convenience conversion.
+ * Here atm, maybe there is somewhere better for this.
+ */
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+enum {
+	VDIG_1_05V = 0,
+	VDIG_1_25V,
+	VDIG_1_65V,
+	VDIG_1_80V,
+} regulator_voltage_vdig;
+
+enum {
+	VPLL_1_05V = 0,
+	VPLL_1_25V,
+	VPLL_1_65V,
+	VPLL_1_80V,
+} regulator_voltage_vpll;
+
+enum {
+	VGEN1_1_2V = 0,
+	VGEN1_1_5V,
+	VGEN1_2_775V,
+	VGEN1_3_15V,
+} regulator_voltage_vgen1;
+
+enum {
+	VGEN2_1_2V = 0,
+	VGEN2_1_5V,
+	VGEN2_1_6V,
+	VGEN2_1_8V,
+	VGEN2_2_7V,
+	VGEN2_2_8V,
+	VGEN2_3_0V,
+	VGEN2_3_15V,
+} regulator_voltage_vgen2;
+
+enum {
+	VGEN3_1_8V = 0,
+	VGEN3_2_9V,
+} regulator_voltage_vgen3;
+
+enum {
+	VSD_1_8V = 0,
+	VSD_2_0V,
+	VSD_2_6V,
+	VSD_2_7V,
+	VSD_2_8V,
+	VSD_2_9V,
+	VSD_3_0V,
+	VSD_3_15V,
+} regulator_voltage_vsd;
+
+enum {
+	VCAM_2_5V,
+	VCAM_2_6V,
+	VCAM_2_75V,
+	VCAM_3_0V,
+} regulator_voltage_vcam;
+
+enum {
+	VAUDIO_2_3V,
+	VAUDIO_2_5V,
+	VAUDIO_2_775V,
+	VAUDIO_3V,
+} regulator_voltage_vaudio;
+
+enum {
+	VUSB2_2_4V,
+	VUSB2_2_6V,
+	VUSB2_2_7V,
+	VUSB2_2_775V,
+} regulator_voltage_vusb2;
+
+enum {
+	VVIDEO_2_7V,
+	VVIDEO_2_775V,
+	VVIDEO_2_5V,
+	VVIDEO_2_6V,
+} regulator_voltage_vvideo;
+
+#define VAUDIO_LSH	4
+#define VAUDIO_WID	2
+#define VAUDIO_EN_LSH	15
+#define VAUDIO_EN_WID	1
+#define VAUDIO_EN_ENABLE	1
+#define VAUDIO_EN_DISABLE	0
+
+#define VUSB2_LSH	11
+#define VUSB2_WID	2
+#define VUSB2_EN_LSH	18
+#define VUSB2_EN_WID	1
+#define VUSB2_EN_ENABLE	1
+#define VUSB2_EN_DISABLE	0
+
+#define VVIDEO_LSH	2
+#define VVIDEO_WID	2
+#define VVIDEO_EN_LSH	12
+#define VVIDEO_EN_WID	1
+#define VVIDEO_EN_ENABLE	1
+#define VVIDEO_EN_DISABLE	0
+
+#define SWBST_EN_LSH	20
+#define SWBST_EN_WID	1
+#define SWBST_EN_ENABLE	1
+#define SWBST_EN_DISABLE	0
+
+#define VIOHI_EN_LSH	3
+#define VIOHI_EN_WID	1
+#define VIOHI_EN_ENABLE	1
+#define VIOHI_EN_DISABLE	0
+
+#define VDIG_LSH	4
+#define VDIG_WID	2
+#define VDIG_EN_LSH	9
+#define VDIG_EN_WID	1
+#define VDIG_EN_ENABLE	1
+#define VDIG_EN_DISABLE	0
+
+#define VPLL_LSH	9
+#define VPLL_WID	2
+#define VPLL_EN_LSH	15
+#define VPLL_EN_WID	1
+#define VPLL_EN_ENABLE	1
+#define VPLL_EN_DISABLE	0
+
+#define VGEN1_LSH	0
+#define VGEN1_WID	2
+#define VGEN1_EN_LSH	0
+#define VGEN1_EN_WID	1
+#define VGEN1_EN_ENABLE	1
+#define VGEN1_EN_DISABLE	0
+
+#define VGEN2_LSH	6
+#define VGEN2_WID	3
+#define VGEN2_EN_LSH	12
+#define VGEN2_EN_WID	1
+#define VGEN2_EN_ENABLE	1
+#define VGEN2_EN_DISABLE	0
+
+#define VGEN3_LSH	14
+#define VGEN3_WID	1
+#define VGEN3_EN_LSH	0
+#define VGEN3_EN_WID	1
+#define VGEN3_EN_ENABLE	1
+#define VGEN3_EN_DISABLE	0
+
+#define VSD_LSH	6
+#define VSD_WID	3
+#define VSD_EN_LSH	18
+#define VSD_EN_WID	1
+#define VSD_EN_ENABLE	1
+#define VSD_EN_DISABLE	0
+
+#define VCAM_LSH	16
+#define VCAM_WID	2
+#define VCAM_EN_LSH	6
+#define VCAM_EN_WID	1
+#define VCAM_EN_ENABLE	1
+#define VCAM_EN_DISABLE	0
+#define VCAM_CONFIG_LSH	9
+#define VCAM_CONFIG_WID	1
+#define VCAM_CONFIG_EXT	1
+#define VCAM_CONFIG_INT	0
+
+#define SW1_LSH		0
+#define SW1_WID		5
+#define SW1_DVS_LSH	5
+#define SW1_DVS_WID	5
+#define SW1_STDBY_LSH	10
+#define SW1_STDBY_WID	5
+
+#define SW2_LSH		0
+#define SW2_WID		5
+#define SW2_DVS_LSH	5
+#define SW2_DVS_WID	5
+#define SW2_STDBY_LSH	10
+#define SW2_STDBY_WID	5
+
+#define SW3_LSH		0
+#define SW3_WID		5
+#define SW3_STDBY_LSH	10
+#define SW3_STDBY_WID	5
+
+#define SW4_LSH		0
+#define SW4_WID		5
+#define SW4_STDBY_LSH	10
+#define SW4_STDBY_WID	5
+
+#define VUSB_EN_LSH	3
+#define VUSB_EN_WID	1
+#define VUSB_EN_ENABLE	1
+#define VUSB_EN_DISABLE	0
+
+#define GPO1_EN_LSH	6
+#define GPO1_EN_WID	1
+#define GPO1_EN_ENABLE	1
+#define GPO1_EN_DISABLE	0
+
+#define GPO2_EN_LSH	8
+#define GPO2_EN_WID	1
+#define GPO2_EN_ENABLE	1
+#define GPO2_EN_DISABLE	0
+
+#define GPO3_EN_LSH	10
+#define GPO3_EN_WID	1
+#define GPO3_EN_ENABLE	1
+#define GPO3_EN_DISABLE	0
+
+#define GPO4_EN_LSH	12
+#define GPO4_EN_WID	1
+#define GPO4_EN_ENABLE	1
+#define GPO4_EN_DISABLE	0
+
+#define GPO4_ADIN_LSH	21
+#define GPO4_ADIN_WID	1
+#define GPO4_ADIN_ENABLE	1
+#define GPO4_ADIN_DISABLE	0
+
+#define PWGT1SPI_EN_LSH	15
+#define PWGT1SPI_EN_WID	1
+#define PWGT1SPI_EN_ENABLE	0
+#define PWGT1SPI_EN_DISABLE	1
+
+#define PWGT2SPI_EN_LSH	16
+#define PWGT2SPI_EN_WID	1
+#define PWGT2SPI_EN_ENABLE	0
+#define PWGT2SPI_EN_DISABLE	1
+
+#define SWXHI_LSH	23
+#define SWXHI_WID	1
+#define SWXHI_ON	1
+#define SWXHI_OFF	0
+
+static int mc13892_get_sw_hi_bit(int sw)
+{
+	unsigned int register_val = 0;
+	unsigned int reg = 0;
+
+	switch (sw) {
+	case MC13892_SW1:
+		reg = REG_SW_0;
+		break;
+	case MC13892_SW2:
+		reg = REG_SW_1;
+		break;
+	case MC13892_SW3:
+		reg = REG_SW_2;
+		break;
+	case MC13892_SW4:
+		reg = REG_SW_3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	CHECK_ERROR(pmic_read_reg(reg, &register_val, PMIC_ALL_BITS));
+	return (register_val & 0x800000) >> SWXHI_LSH;
+}
+
+static int mc13892_get_voltage_value(int *hi, int mV)
+{
+	int voltage;
+
+	if (mV < 600)
+		mV = 600;
+	if (mV > 1850)
+		mV = 1850;
+
+	if (mV > 1375)
+		*hi = 1;
+	if (mV < 1100)
+		*hi = 0;
+
+	if (*hi == 0)
+		voltage = (mV - 600) / 25;
+	else
+		voltage = (mV - 1100) / 25;
+
+	return voltage;
+}
+
+static int mc13892_get_voltage_mV(int hi, int voltage)
+{
+	int mV;
+
+	if (hi == 0)
+		mV = voltage * 25 + 600;
+	else
+		mV = voltage * 25 + 1100;
+
+	return mV;
+}
+
+static int mc13892_sw_set_voltage(struct regulator_dev *reg, int MiniV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1 = 0;
+	int voltage;
+	int sw = rdev_get_id(reg);
+	int mV = uV / 1000;
+	int hi;
+
+	hi = mc13892_get_sw_hi_bit(sw);
+	voltage = mc13892_get_voltage_value(&hi, mV);
+
+	switch (sw) {
+	case MC13892_SW1:
+		register1 = REG_SW_0;
+		register_val = BITFVAL(SW1, voltage);
+		register_mask = BITFMASK(SW1);
+		break;
+	case MC13892_SW2:
+		register1 = REG_SW_1;
+		register_val = BITFVAL(SW2, voltage);
+		register_mask = BITFMASK(SW2);
+		break;
+	case MC13892_SW3:
+		register1 = REG_SW_2;
+		register_val = BITFVAL(SW3, voltage);
+		register_mask = BITFMASK(SW3);
+		break;
+	case MC13892_SW4:
+		register1 = REG_SW_3;
+		register_val = BITFVAL(SW4, voltage);
+		register_mask = BITFMASK(SW4);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	register_val |= (hi << SWXHI_LSH);
+	register_mask |= (1 << SWXHI_LSH);
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_sw_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0;
+	int mV = 0;
+	int sw = rdev_get_id(reg);
+	int hi;
+
+	switch (sw) {
+	case MC13892_SW1:
+		CHECK_ERROR(pmic_read_reg(REG_SW_0,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW1);
+		break;
+	case MC13892_SW2:
+		CHECK_ERROR(pmic_read_reg(REG_SW_1,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW2);
+		break;
+	case MC13892_SW3:
+		CHECK_ERROR(pmic_read_reg(REG_SW_2,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW3);
+		break;
+	case MC13892_SW4:
+		CHECK_ERROR(pmic_read_reg(REG_SW_3,
+					  &register_val, PMIC_ALL_BITS));
+		voltage = BITFEXT(register_val, SW4);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	hi = mc13892_get_sw_hi_bit(sw);
+	mV = mc13892_get_voltage_mV(hi, voltage);
+
+	return mV * 1000;
+}
+
+static int mc13892_sw_stby_enable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13892_sw_stby_disable(struct regulator_dev *reg)
+{
+	return 0;
+}
+
+static int mc13892_sw_stby_set_mode(struct regulator_dev *reg, unsigned int mode)
+{
+	return 0;
+}
+
+static int mc13892_sw_stby_set_voltage(struct regulator_dev *reg, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1 = 0;
+	int voltage, mV = uV / 1000, hi;
+	int sw = rdev_get_id(reg);
+
+	hi = mc13892_get_sw_hi_bit(sw);
+	voltage = mc13892_get_voltage_value(&hi, mV);
+
+	switch (sw) {
+	case MC13892_SW1:
+		register1 = REG_SW_0;
+		register_val = BITFVAL(SW1_STDBY, voltage);
+		register_mask = BITFMASK(SW1_STDBY);
+		break;
+	case MC13892_SW2:
+		register1 = REG_SW_1;
+		register_val = BITFVAL(SW2_STDBY, voltage);
+		register_mask = BITFMASK(SW2_STDBY);
+		break;
+	case MC13892_SW3:
+		register1 = REG_SW_2;
+		register_val = BITFVAL(SW3_STDBY, voltage);
+		register_mask = BITFMASK(SW3_STDBY);
+		break;
+	case MC13892_SW4:
+		register1 = REG_SW_3;
+		register_val = BITFVAL(SW4_STDBY, voltage);
+		register_mask = BITFMASK(SW4_STDBY);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	register_val |= (hi << SWXHI_LSH);
+	register_mask |= (1 << SWXHI_LSH);
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_swbst_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(SWBST_EN, SWBST_EN_ENABLE);
+	register_mask = BITFMASK(SWBST_EN);
+	register1 = REG_SW_5;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_swbst_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(SWBST_EN, SWBST_EN_DISABLE);
+	register_mask = BITFMASK(SWBST_EN);
+	register1 = REG_SW_5;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_viohi_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE);
+	register_mask = BITFMASK(VIOHI_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_viohi_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE);
+	register_mask = BITFMASK(VIOHI_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vusb_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VUSB_EN, VUSB_EN_ENABLE);
+	register_mask = BITFMASK(VUSB_EN);
+	register1 = REG_USB1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vusb_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VUSB_EN, VUSB_EN_DISABLE);
+	register_mask = BITFMASK(VUSB_EN);
+	register1 = REG_USB1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vdig_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1050) && (mV < 1250))
+		voltage = VDIG_1_05V;
+	else if ((mV >= 1250) && (mV < 1650))
+		voltage = VDIG_1_25V;
+	else if ((mV >= 1650) && (mV < 1800))
+		voltage = VDIG_1_65V;
+	else
+		voltage = VDIG_1_80V;
+
+	register_val = BITFVAL(VDIG, voltage);
+	register_mask = BITFMASK(VDIG);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vdig_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VDIG);
+
+	switch (voltage) {
+	case VDIG_1_05V:
+		mV = 1050;
+		break;
+	case VDIG_1_25V:
+		mV = 1250;
+		break;
+	case VDIG_1_65V:
+		mV = 1650;
+		break;
+	case VDIG_1_80V:
+		mV = 1800;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vdig_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE);
+	register_mask = BITFMASK(VDIG_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vdig_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE);
+	register_mask = BITFMASK(VDIG_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vpll_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1050) && (mV < 1250))
+		voltage = VPLL_1_05V;
+	else if ((mV >= 1250) && (mV < 1650))
+		voltage = VPLL_1_25V;
+	else if ((mV >= 1650) && (mV < 1800))
+		voltage = VPLL_1_65V;
+	else
+		voltage = VPLL_1_80V;
+
+	register_val = BITFVAL(VPLL, voltage);
+	register_mask = BITFMASK(VPLL);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vpll_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VPLL);
+
+	switch (voltage) {
+	case VPLL_1_05V:
+		mV = 1050;
+		break;
+	case VPLL_1_25V:
+		mV = 1250;
+		break;
+	case VPLL_1_65V:
+		mV = 1650;
+		break;
+	case VPLL_1_80V:
+		mV = 1800;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vpll_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VPLL_EN, VPLL_EN_ENABLE);
+	register_mask = BITFMASK(VPLL_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vpll_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VPLL_EN, VPLL_EN_DISABLE);
+	register_mask = BITFMASK(VPLL_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vaudio_set_voltage(struct regulator_dev *reg,
+				      int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2300) && (mV < 2500))
+		voltage = VAUDIO_2_3V;
+	else if ((mV >= 2500) && (mV < 2775))
+		voltage = VAUDIO_2_5V;
+	else if ((mV >= 2775) && (mV < 3000))
+		voltage = VAUDIO_2_775V;
+	else
+		voltage = VAUDIO_3V;
+
+	register_val = BITFVAL(VAUDIO, voltage);
+	register_mask = BITFMASK(VAUDIO);
+	register1 = REG_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vaudio_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_1, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VAUDIO);
+
+	switch (voltage) {
+	case VAUDIO_2_3V:
+		mV = 2300;
+		break;
+	case VAUDIO_2_5V:
+		mV = 2500;
+		break;
+	case VAUDIO_2_775V:
+		mV = 2775;
+		break;
+	case VAUDIO_3V:
+		mV = 3000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vaudio_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE);
+	register_mask = BITFMASK(VAUDIO_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vaudio_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE);
+	register_mask = BITFMASK(VAUDIO_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vusb2_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2400) && (mV < 2600))
+		voltage = VUSB2_2_4V;
+	else if ((mV >= 2600) && (mV < 2700))
+		voltage = VUSB2_2_6V;
+	else if ((mV >= 2700) && (mV < 2775))
+		voltage = VUSB2_2_7V;
+	else
+		voltage = VUSB2_2_775V;
+
+	register_val = BITFVAL(VUSB2, voltage);
+	register_mask = BITFMASK(VUSB2);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vusb2_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VUSB2);
+
+	switch (voltage) {
+	case VUSB2_2_4V:
+		mV = 2400;
+		break;
+	case VUSB2_2_6V:
+		mV = 2600;
+		break;
+	case VUSB2_2_7V:
+		mV = 2700;
+		break;
+	case VUSB2_2_775V:
+		mV = 2775;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vusb2_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VUSB2_EN, VUSB2_EN_ENABLE);
+	register_mask = BITFMASK(VUSB2_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vusb2_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VUSB2_EN, VUSB2_EN_DISABLE);
+	register_mask = BITFMASK(VUSB2_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vvideo_set_voltage(struct regulator_dev *reg,
+				      int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2500) && (mV < 2600))
+		voltage = VVIDEO_2_5V;
+	else if ((mV >= 2600) && (mV < 2700))
+		voltage = VVIDEO_2_6V;
+	else if ((mV >= 2700) && (mV < 2775))
+		voltage = VVIDEO_2_7V;
+	else
+		voltage = VVIDEO_2_775V;
+
+	register_val = BITFVAL(VVIDEO, voltage);
+	register_mask = BITFMASK(VVIDEO);
+	register1 = REG_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vvideo_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_1, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VVIDEO);
+
+	switch (voltage) {
+	case VVIDEO_2_5V:
+		mV = 2500;
+		break;
+	case VVIDEO_2_6V:
+		mV = 2600;
+		break;
+	case VVIDEO_2_7V:
+		mV = 2700;
+		break;
+	case VVIDEO_2_775V:
+		mV = 2775;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vvideo_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_ENABLE);
+	register_mask = BITFMASK(VVIDEO_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vvideo_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_DISABLE);
+	register_mask = BITFMASK(VVIDEO_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vsd_set_voltage(struct regulator_dev *reg,
+				   int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1800) && (mV < 2000))
+		voltage = VSD_1_8V;
+	else if ((mV >= 2000) && (mV < 2600))
+		voltage = VSD_2_0V;
+	else if ((mV >= 2600) && (mV < 2700))
+		voltage = VSD_2_6V;
+	else if ((mV >= 2700) && (mV < 2800))
+		voltage = VSD_2_7V;
+	else if ((mV >= 2800) && (mV < 2900))
+		voltage = VSD_2_8V;
+	else if ((mV >= 2900) && (mV < 3000))
+		voltage = VSD_2_9V;
+	else if ((mV >= 3000) && (mV < 3150))
+		voltage = VSD_3_0V;
+	else
+		voltage = VSD_3_15V;
+
+	register_val = BITFVAL(VSD, voltage);
+	register_mask = BITFMASK(VSD);
+	register1 = REG_SETTING_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vsd_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_1, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VSD);
+
+	switch (voltage) {
+	case VSD_1_8V:
+		mV = 1800;
+		break;
+	case VSD_2_0V:
+		mV = 2000;
+		break;
+	case VSD_2_6V:
+		mV = 2600;
+		break;
+	case VSD_2_7V:
+		mV = 2700;
+		break;
+	case VSD_2_8V:
+		mV = 2800;
+		break;
+	case VSD_2_9V:
+		mV = 2900;
+		break;
+	case VSD_3_0V:
+		mV = 3000;
+		break;
+	case VSD_3_15V:
+		mV = 3150;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vsd_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VSD_EN, VSD_EN_ENABLE);
+	register_mask = BITFMASK(VSD_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vsd_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VSD_EN, VSD_EN_DISABLE);
+	register_mask = BITFMASK(VSD_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vcam_set_voltage(struct regulator_dev *reg,
+				    int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 2500) && (mV < 2600))
+		voltage = VCAM_2_5V;
+	else if ((mV >= 2600) && (mV < 2750))
+		voltage = VCAM_2_6V;
+	else if ((mV >= 2750) && (mV < 3000))
+		voltage = VCAM_2_75V;
+	else
+		voltage = VCAM_3_0V;
+
+	register_val = BITFVAL(VCAM, voltage);
+	register_mask = BITFMASK(VCAM);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vcam_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VCAM);
+
+	switch (voltage) {
+	case VCAM_2_5V:
+		mV = 2500;
+		break;
+	case VCAM_2_6V:
+		mV = 2600;
+		break;
+	case VCAM_2_75V:
+		mV = 2750;
+		break;
+	case VCAM_3_0V:
+		mV = 3000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vcam_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE);
+	register_mask = BITFMASK(VCAM_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vcam_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE);
+	register_mask = BITFMASK(VCAM_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vcam_set_mode(struct regulator_dev *reg, unsigned int mode)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	switch (mode) {
+	case REGULATOR_MODE_FAST:
+		register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_EXT);
+		break;
+	case REGULATOR_MODE_NORMAL:
+		register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_INT);
+		break;
+	default:
+		return -EINVAL;
+	}
+	register_mask = BITFMASK(VCAM_CONFIG);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+unsigned int mc13892_vcam_get_mode(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int config = 0, mode = VCAM_CONFIG_INT;
+
+	CHECK_ERROR(pmic_read_reg(REG_MODE_1, &register_val, PMIC_ALL_BITS));
+	config = BITFEXT(register_val, VCAM_CONFIG);
+
+	switch (config) {
+	case VCAM_CONFIG_EXT:
+		mode = REGULATOR_MODE_FAST;
+		break;
+	case VCAM_CONFIG_INT:
+		mode = REGULATOR_MODE_NORMAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return mode;
+}
+
+static int mc13892_vgen1_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1200) && (mV < 1500))
+		voltage = VGEN1_1_2V;
+	else if ((mV >= 1500) && (mV < 2775))
+		voltage = VGEN1_1_5V;
+	else if ((mV >= 2775) && (mV < 3150))
+		voltage = VGEN1_2_775V;
+	else
+		voltage = VGEN1_3_15V;
+
+	register_val = BITFVAL(VGEN1, voltage);
+	register_mask = BITFMASK(VGEN1);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen1_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VGEN1);
+
+	switch (voltage) {
+	case VGEN1_1_2V:
+		mV = 1200;
+		break;
+	case VGEN1_1_5V:
+		mV = 1500;
+		break;
+	case VGEN1_2_775V:
+		mV = 2775;
+		break;
+	case VGEN1_3_15V:
+		mV = 3150;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vgen1_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN1_EN, VGEN1_EN_ENABLE);
+	register_mask = BITFMASK(VGEN1_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen1_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN1_EN, VGEN1_EN_DISABLE);
+	register_mask = BITFMASK(VGEN1_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen2_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1200) && (mV < 1500))
+		voltage = VGEN2_1_2V;
+	else if ((mV >= 1500) && (mV < 1600))
+		voltage = VGEN2_1_5V;
+	else if ((mV >= 1600) && (mV < 1800))
+		voltage = VGEN2_1_6V;
+	else if ((mV >= 1800) && (mV < 2700))
+		voltage = VGEN2_1_8V;
+	else if ((mV >= 2700) && (mV < 2800))
+		voltage = VGEN2_2_7V;
+	else if ((mV >= 2800) && (mV < 3000))
+		voltage = VGEN2_2_8V;
+	else if ((mV >= 3000) && (mV < 3150))
+		voltage = VGEN2_3_0V;
+	else
+		voltage = VGEN2_3_15V;
+
+	register_val = BITFVAL(VGEN2, voltage);
+	register_mask = BITFMASK(VGEN2);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen2_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VGEN2);
+
+	switch (voltage) {
+	case VGEN2_1_2V:
+		mV = 1200;
+		break;
+	case VGEN2_1_5V:
+		mV = 1500;
+		break;
+	case VGEN2_1_6V:
+		mV = 1600;
+		break;
+	case VGEN2_1_8V:
+		mV = 1800;
+		break;
+	case VGEN2_2_7V:
+		mV = 2700;
+		break;
+	case VGEN2_2_8V:
+		mV = 2800;
+		break;
+	case VGEN2_3_0V:
+		mV = 3000;
+		break;
+	case VGEN2_3_15V:
+		mV = 3150;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vgen2_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN2_EN, VGEN2_EN_ENABLE);
+	register_mask = BITFMASK(VGEN2_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen2_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN2_EN, VGEN2_EN_DISABLE);
+	register_mask = BITFMASK(VGEN2_EN);
+	register1 = REG_MODE_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen3_set_voltage(struct regulator_dev *reg,
+				     int minuV, int uV)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int voltage, mV = uV / 1000;
+
+	if ((mV >= 1800) && (mV < 2900))
+		voltage = VGEN3_1_8V;
+	else
+		voltage = VGEN3_2_9V;
+
+	register_val = BITFVAL(VGEN3, voltage);
+	register_mask = BITFMASK(VGEN3);
+	register1 = REG_SETTING_0;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen3_get_voltage(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0;
+	int voltage = 0, mV = 0;
+
+	CHECK_ERROR(pmic_read_reg(REG_SETTING_0, &register_val, PMIC_ALL_BITS));
+	voltage = BITFEXT(register_val, VGEN3);
+
+	switch (voltage) {
+	case VGEN3_1_8V:
+		mV = 1800;
+		break;
+	case VGEN3_2_9V:
+		mV = 2900;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return mV * 1000;
+}
+
+static int mc13892_vgen3_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN3_EN, VGEN3_EN_ENABLE);
+	register_mask = BITFMASK(VGEN3_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_vgen3_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+
+	register_val = BITFVAL(VGEN3_EN, VGEN3_EN_DISABLE);
+	register_mask = BITFMASK(VGEN3_EN);
+	register1 = REG_MODE_1;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_gpo_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13892_GPO1:
+		register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE);
+		register_mask = BITFMASK(GPO1_EN);
+		break;
+	case MC13892_GPO2:
+		register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE);
+		register_mask = BITFMASK(GPO2_EN);
+		break;
+	case MC13892_GPO3:
+		register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE);
+		register_mask = BITFMASK(GPO3_EN);
+		break;
+	case MC13892_GPO4:
+		register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE) +
+		    BITFVAL(GPO4_ADIN, GPO4_ADIN_DISABLE);
+		register_mask = BITFMASK(GPO4_EN) + BITFMASK(GPO4_ADIN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISC;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_gpo_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13892_GPO1:
+		register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE);
+		register_mask = BITFMASK(GPO1_EN);
+		break;
+	case MC13892_GPO2:
+		register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE);
+		register_mask = BITFMASK(GPO2_EN);
+		break;
+	case MC13892_GPO3:
+		register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE);
+		register_mask = BITFMASK(GPO3_EN);
+		break;
+	case MC13892_GPO4:
+		register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE);
+		register_mask = BITFMASK(GPO4_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISC;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_power_gating_enable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13892_PWGT1:
+		register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_ENABLE);
+		register_mask = BITFMASK(PWGT1SPI_EN);
+		break;
+	case MC13892_PWGT2:
+		register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_ENABLE);
+		register_mask = BITFMASK(PWGT2SPI_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISC;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static int mc13892_power_gating_disable(struct regulator_dev *reg)
+{
+	unsigned int register_val = 0, register_mask = 0;
+	unsigned int register1;
+	int gpo = rdev_get_id(reg);
+
+	switch (gpo) {
+	case MC13892_PWGT1:
+		register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_DISABLE);
+		register_mask = BITFMASK(PWGT1SPI_EN);
+		break;
+	case MC13892_PWGT2:
+		register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_DISABLE);
+		register_mask = BITFMASK(PWGT2SPI_EN);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	register1 = REG_POWER_MISC;
+
+	return pmic_write_reg(register1, register_val, register_mask);
+}
+
+static struct regulator_ops mc13892_sw_ops = {
+	.enable = mc13892_sw_stby_enable,
+	.disable = mc13892_sw_stby_disable,
+	.set_voltage = mc13892_sw_set_voltage,
+	.get_voltage = mc13892_sw_get_voltage,
+	.set_suspend_voltage = mc13892_sw_stby_set_voltage,
+	.set_suspend_enable = mc13892_sw_stby_enable,
+	.set_suspend_disable = mc13892_sw_stby_disable,
+	.set_suspend_mode = mc13892_sw_stby_set_mode,
+};
+
+static struct regulator_ops mc13892_swbst_ops = {
+	.enable = mc13892_swbst_enable,
+	.disable = mc13892_swbst_disable,
+};
+
+static struct regulator_ops mc13892_viohi_ops = {
+	.enable = mc13892_viohi_enable,
+	.disable = mc13892_viohi_disable,
+};
+
+static struct regulator_ops mc13892_vusb_ops = {
+	.enable = mc13892_vusb_enable,
+	.disable = mc13892_vusb_disable,
+};
+
+static struct regulator_ops mc13892_vdig_ops = {
+	.set_voltage = mc13892_vdig_set_voltage,
+	.get_voltage = mc13892_vdig_get_voltage,
+	.enable = mc13892_vdig_enable,
+	.disable = mc13892_vdig_disable,
+};
+
+static struct regulator_ops mc13892_vpll_ops = {
+	.set_voltage = mc13892_vpll_set_voltage,
+	.get_voltage = mc13892_vpll_get_voltage,
+	.enable = mc13892_vpll_enable,
+	.disable = mc13892_vpll_disable,
+};
+
+static struct regulator_ops mc13892_vusb2_ops = {
+	.set_voltage = mc13892_vusb2_set_voltage,
+	.get_voltage = mc13892_vusb2_get_voltage,
+	.enable = mc13892_vusb2_enable,
+	.disable = mc13892_vusb2_disable,
+};
+
+static struct regulator_ops mc13892_vvideo_ops = {
+	.set_voltage = mc13892_vvideo_set_voltage,
+	.get_voltage = mc13892_vvideo_get_voltage,
+	.enable = mc13892_vvideo_enable,
+	.disable = mc13892_vvideo_disable,
+};
+
+static struct regulator_ops mc13892_vaudio_ops = {
+	.set_voltage = mc13892_vaudio_set_voltage,
+	.get_voltage = mc13892_vaudio_get_voltage,
+	.enable = mc13892_vaudio_enable,
+	.disable = mc13892_vaudio_disable,
+};
+
+static struct regulator_ops mc13892_vsd_ops = {
+	.set_voltage = mc13892_vsd_set_voltage,
+	.get_voltage = mc13892_vsd_get_voltage,
+	.enable = mc13892_vsd_enable,
+	.disable = mc13892_vsd_disable,
+};
+
+static struct regulator_ops mc13892_vcam_ops = {
+	.set_voltage = mc13892_vcam_set_voltage,
+	.get_voltage = mc13892_vcam_get_voltage,
+	.enable = mc13892_vcam_enable,
+	.disable = mc13892_vcam_disable,
+	.set_mode = mc13892_vcam_set_mode,
+	.get_mode = mc13892_vcam_get_mode,
+};
+
+static struct regulator_ops mc13892_vgen1_ops = {
+	.set_voltage = mc13892_vgen1_set_voltage,
+	.get_voltage = mc13892_vgen1_get_voltage,
+	.enable = mc13892_vgen1_enable,
+	.disable = mc13892_vgen1_disable,
+};
+
+static struct regulator_ops mc13892_vgen2_ops = {
+	.set_voltage = mc13892_vgen2_set_voltage,
+	.get_voltage = mc13892_vgen2_get_voltage,
+	.enable = mc13892_vgen2_enable,
+	.disable = mc13892_vgen2_disable,
+};
+
+static struct regulator_ops mc13892_vgen3_ops = {
+	.set_voltage = mc13892_vgen3_set_voltage,
+	.get_voltage = mc13892_vgen3_get_voltage,
+	.enable = mc13892_vgen3_enable,
+	.disable = mc13892_vgen3_disable,
+};
+
+static struct regulator_ops mc13892_gpo_ops = {
+	.enable = mc13892_gpo_enable,
+	.disable = mc13892_gpo_disable,
+};
+
+static struct regulator_ops mc13892_power_gating_ops = {
+	.enable = mc13892_power_gating_enable,
+	.disable = mc13892_power_gating_disable,
+
+};
+
+static struct regulator_desc mc13892_reg[] = {
+	{
+		.name = "SW1",
+		.id = MC13892_SW1,
+		.ops = &mc13892_sw_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW2",
+		.id = MC13892_SW2,
+		.ops = &mc13892_sw_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW3",
+		.id = MC13892_SW3,
+		.ops = &mc13892_sw_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SW4",
+		.id = MC13892_SW4,
+		.ops = &mc13892_sw_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "SWBST",
+		.id = MC13892_SWBST,
+		.ops = &mc13892_swbst_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VIOHI",
+		.id = MC13892_VIOHI,
+		.ops = &mc13892_viohi_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VPLL",
+		.id = MC13892_VPLL,
+		.ops = &mc13892_vpll_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VDIG",
+		.id = MC13892_VDIG,
+		.ops = &mc13892_vdig_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VSD",
+		.id = MC13892_VSD,
+		.ops = &mc13892_vsd_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VUSB2",
+		.id = MC13892_VUSB2,
+		.ops = &mc13892_vusb2_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VVIDEO",
+		.id = MC13892_VVIDEO,
+		.ops = &mc13892_vvideo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VAUDIO",
+		.id = MC13892_VAUDIO,
+		.ops = &mc13892_vaudio_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VCAM",
+		.id = MC13892_VCAM,
+		.ops = &mc13892_vcam_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VGEN1",
+		.id = MC13892_VGEN1,
+		.ops = &mc13892_vgen1_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VGEN2",
+		.id = MC13892_VGEN2,
+		.ops = &mc13892_vgen2_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VGEN3",
+		.id = MC13892_VGEN3,
+		.ops = &mc13892_vgen3_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "VUSB",
+		.id = MC13892_VUSB,
+		.ops = &mc13892_vusb_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO1",
+		.id = MC13892_GPO1,
+		.ops = &mc13892_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO2",
+		.id = MC13892_GPO2,
+		.ops = &mc13892_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO3",
+		.id = MC13892_GPO3,
+		.ops = &mc13892_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "GPO4",
+		.id = MC13892_GPO4,
+		.ops = &mc13892_gpo_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "PWGT1",
+		.id = MC13892_PWGT1,
+		.ops = &mc13892_power_gating_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "PWGT2",
+		.id = MC13892_PWGT2,
+		.ops = &mc13892_power_gating_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+};
+
+static int mc13892_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	/* register regulator */
+	rdev = regulator_register(&mc13892_reg[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  dev_get_drvdata(&pdev->dev));
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			mc13892_reg[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+
+static int mc13892_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+}
+
+int mc13892_register_regulator(struct mc13892 *mc13892, int reg,
+			      struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	if (mc13892->pmic.pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("mc13892-regulatr", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	mc13892->pmic.pdev[reg] = pdev;
+
+	initdata->driver_data = mc13892;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.parent = mc13892->dev;
+	platform_set_drvdata(pdev, mc13892);
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(mc13892->dev, "Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		mc13892->pmic.pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mc13892_register_regulator);
+
+static struct platform_driver mc13892_regulator_driver = {
+	.probe = mc13892_regulator_probe,
+	.remove = mc13892_regulator_remove,
+	.driver		= {
+		.name	= "mc13892-regulatr",
+	},
+};
+
+static int __init mc13892_regulator_init(void)
+{
+	return platform_driver_register(&mc13892_regulator_driver);
+}
+subsys_initcall(mc13892_regulator_init);
+
+static void __exit mc13892_regulator_exit(void)
+{
+	platform_driver_unregister(&mc13892_regulator_driver);
+}
+module_exit(mc13892_regulator_exit);
+
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC13892 Regulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/reg-mc34704.c b/drivers/regulator/reg-mc34704.c
new file mode 100644
index 000000000000..a3a7e5d7ea90
--- /dev/null
+++ b/drivers/regulator/reg-mc34704.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/ioctl.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/mfd/mc34704/core.h>
+#include <linux/platform_device.h>
+#include <linux/pmic_status.h>
+#include <linux/pmic_external.h>
+
+#define MC34704_ONOFFA	0x8
+#define MC34704_ONOFFC	0x4
+#define MC34704_ONOFFD	0x2
+#define MC34704_ONOFFE	0x1
+
+/* Private data for MC34704 regulators */
+
+struct reg_mc34704_priv {
+	short enable;		/* enable bit, if available */
+	short v_default;	/* default regulator voltage in mV */
+	int dvs_min;		/* minimum voltage change in units of 2.5% */
+	int dvs_max;		/* maximum voltage change in units of 2.5% */
+	char i2c_dvs;		/* i2c DVS register number */
+	char i2c_stat;		/* i2c status register number */
+};
+struct reg_mc34704_priv mc34704_reg_priv[] = {
+	{
+	 .v_default = REG1_V_MV,
+	 .dvs_min = REG1_DVS_MIN_PCT / 2.5,
+	 .dvs_max = REG1_DVS_MAX_PCT / 2.5,
+	 .i2c_dvs = 0x4,
+	 .i2c_stat = 0x5,
+	 .enable = MC34704_ONOFFA,
+	 },
+	{
+	 .v_default = REG2_V_MV,
+	 .dvs_min = REG2_DVS_MIN_PCT / 2.5,
+	 .dvs_max = REG2_DVS_MAX_PCT / 2.5,
+	 .i2c_dvs = 0x6,
+	 .i2c_stat = 0x7,
+	 },
+	{
+	 .v_default = REG3_V_MV,
+	 .dvs_min = REG3_DVS_MIN_PCT / 2.5,
+	 .dvs_max = REG3_DVS_MAX_PCT / 2.5,
+	 .i2c_dvs = 0x8,
+	 .i2c_stat = 0x9,
+	 },
+	{
+	 .v_default = REG4_V_MV,
+	 .dvs_min = REG4_DVS_MIN_PCT / 2.5,
+	 .dvs_max = REG4_DVS_MAX_PCT / 2.5,
+	 .i2c_dvs = 0xA,
+	 .i2c_stat = 0xB,
+	 },
+	{
+	 .v_default = REG5_V_MV,
+	 .dvs_min = REG5_DVS_MIN_PCT / 2.5,
+	 .dvs_max = REG5_DVS_MAX_PCT / 2.5,
+	 .i2c_dvs = 0xC,
+	 .i2c_stat = 0xE,
+	 .enable = MC34704_ONOFFE,
+	 },
+};
+
+static int mc34704_set_voltage(struct regulator_dev *reg, int MiniV, int uV)
+{
+	struct reg_mc34704_priv *priv = rdev_get_drvdata(reg);
+	int mV = uV / 1000;
+	int dV = mV - priv->v_default;
+
+	/* compute dynamic voltage scaling value */
+	int dvs = 1000 * dV / priv->v_default / 25;
+
+	/* clip to regulator limits */
+	if (dvs > priv->dvs_max)
+		dvs = priv->dvs_max;
+	if (dvs < priv->dvs_min)
+		dvs = priv->dvs_min;
+
+	return pmic_write_reg(priv->i2c_dvs, dvs << 1, 0x1E);
+}
+
+static int mc34704_get_voltage(struct regulator_dev *reg)
+{
+	int mV;
+	struct reg_mc34704_priv *priv = rdev_get_drvdata(reg);
+	int val, dvs;
+
+	CHECK_ERROR(pmic_read_reg(priv->i2c_dvs, &val, 0xF));
+
+	dvs = (val >> 1) & 0xF;
+
+	/* dvs is 4-bit 2's complement; sign-extend it */
+	if (dvs & 8)
+		dvs |= -1 & ~0xF;
+
+	/* Regulator voltage is adjusted by (dvs * 2.5%) */
+	mV = priv->v_default * (1000 + 25 * dvs) / 1000;
+
+	return 1000 * mV;
+}
+
+static int mc34704_enable_reg(struct regulator_dev *reg)
+{
+	struct reg_mc34704_priv *priv = rdev_get_drvdata(reg);
+
+	if (priv->enable)
+		return pmic_write_reg(REG_MC34704_GENERAL2, -1, priv->enable);
+
+	return PMIC_ERROR;
+}
+
+static int mc34704_disable_reg(struct regulator_dev *reg)
+{
+	struct reg_mc34704_priv *priv = rdev_get_drvdata(reg);
+
+	if (priv->enable)
+		return pmic_write_reg(REG_MC34704_GENERAL2, 0, priv->enable);
+
+	return PMIC_ERROR;
+}
+
+static int mc34704_is_reg_enabled(struct regulator_dev *reg)
+{
+	struct reg_mc34704_priv *priv = rdev_get_drvdata(reg);
+	int val;
+
+	if (priv->enable) {
+		CHECK_ERROR(pmic_read_reg(REG_MC34704_GENERAL2, &val,
+					  priv->enable));
+		return val ? 1 : 0;
+	} else {
+		return PMIC_ERROR;
+	}
+}
+
+static struct regulator_ops mc34704_full_ops = {
+	.set_voltage = mc34704_set_voltage,
+	.get_voltage = mc34704_get_voltage,
+	.enable = mc34704_enable_reg,
+	.disable = mc34704_disable_reg,
+	.is_enabled = mc34704_is_reg_enabled,
+};
+
+static struct regulator_ops mc34704_partial_ops = {
+	.set_voltage = mc34704_set_voltage,
+	.get_voltage = mc34704_get_voltage,
+};
+
+static struct regulator_desc reg_mc34704[] = {
+	{
+	 .name = "REG1_BKLT",
+	 .id = MC34704_BKLT,
+	 .ops = &mc34704_full_ops,
+	 .irq = 0,
+	 .type = REGULATOR_VOLTAGE,
+	 .owner = THIS_MODULE},
+	{
+	 .name = "REG2_CPU",
+	 .id = MC34704_CPU,
+	 .ops = &mc34704_partial_ops,
+	 .irq = 0,
+	 .type = REGULATOR_VOLTAGE,
+	 .owner = THIS_MODULE},
+	{
+	 .name = "REG3_CORE",
+	 .id = MC34704_CORE,
+	 .ops = &mc34704_partial_ops,
+	 .irq = 0,
+	 .type = REGULATOR_VOLTAGE,
+	 .owner = THIS_MODULE},
+	{
+	 .name = "REG4_DDR",
+	 .id = MC34704_DDR,
+	 .ops = &mc34704_partial_ops,
+	 .irq = 0,
+	 .type = REGULATOR_VOLTAGE,
+	 .owner = THIS_MODULE},
+	{
+	 .name = "REG5_PERS",
+	 .id = MC34704_PERS,
+	 .ops = &mc34704_full_ops,
+	 .irq = 0,
+	 .type = REGULATOR_VOLTAGE,
+	 .owner = THIS_MODULE},
+};
+
+static int mc34704_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	/* register regulator */
+	rdev = regulator_register(&reg_mc34704[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  (void *)&mc34704_reg_priv[pdev->id]);
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			reg_mc34704[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+static int mc34704_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+}
+
+int mc34704_register_regulator(struct mc34704 *mc34704, int reg,
+			       struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	if (mc34704->pmic.pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("mc34704-regulatr", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	mc34704->pmic.pdev[reg] = pdev;
+
+	initdata->driver_data = mc34704;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.driver_data = &mc34704_reg_priv[reg];
+	pdev->dev.parent = mc34704->dev;
+	platform_set_drvdata(pdev, mc34704);
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(mc34704->dev, "Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		mc34704->pmic.pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mc34704_register_regulator);
+
+static struct platform_driver mc34704_regulator_driver = {
+	.probe = mc34704_regulator_probe,
+	.remove = mc34704_regulator_remove,
+	.driver = {
+		   .name = "mc34704-regulatr",
+		   },
+};
+
+static int __init mc34704_regulator_init(void)
+{
+	return platform_driver_register(&mc34704_regulator_driver);
+}
+subsys_initcall(mc34704_regulator_init);
+
+static void __exit mc34704_regulator_exit(void)
+{
+	platform_driver_unregister(&mc34704_regulator_driver);
+}
+module_exit(mc34704_regulator_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC34704 Regulator Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/reg-mc9s08dz60.c b/drivers/regulator/reg-mc9s08dz60.c
new file mode 100644
index 000000000000..16994b7d2efc
--- /dev/null
+++ b/drivers/regulator/reg-mc9s08dz60.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/mfd/mc9s08dz60/core.h>
+#include <linux/mfd/mc9s08dz60/pmic.h>
+#include <linux/platform_device.h>
+#include <linux/pmic_status.h>
+
+/* lcd */
+static int mc9s08dz60_lcd_enable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 1);
+}
+
+static int mc9s08dz60_lcd_disable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 0);
+}
+
+static struct regulator_ops mc9s08dz60_lcd_ops = {
+	.enable = mc9s08dz60_lcd_enable,
+	.disable = mc9s08dz60_lcd_disable,
+};
+
+/* wifi */
+static int mc9s08dz60_wifi_enable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1);
+}
+
+static int mc9s08dz60_wifi_disable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0);
+}
+
+static struct regulator_ops mc9s08dz60_wifi_ops = {
+	.enable = mc9s08dz60_wifi_enable,
+	.disable = mc9s08dz60_wifi_disable,
+};
+
+/* hdd */
+static int mc9s08dz60_hdd_enable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 1);
+}
+
+static int mc9s08dz60_hdd_disable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 0);
+}
+
+static struct regulator_ops mc9s08dz60_hdd_ops = {
+	.enable = mc9s08dz60_hdd_enable,
+	.disable = mc9s08dz60_hdd_disable,
+};
+
+/* gps */
+static int mc9s08dz60_gps_enable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 1);
+}
+
+static int mc9s08dz60_gps_disable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0);
+}
+
+static struct regulator_ops mc9s08dz60_gps_ops = {
+	.enable = mc9s08dz60_gps_enable,
+	.disable = mc9s08dz60_gps_disable,
+};
+
+/* speaker */
+static int mc9s08dz60_speaker_enable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 1);
+}
+
+static int mc9s08dz60_speaker_disable(struct regulator_dev *reg)
+{
+	return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 0);
+}
+
+static struct regulator_ops mc9s08dz60_speaker_ops = {
+	.enable = mc9s08dz60_speaker_enable,
+	.disable = mc9s08dz60_speaker_disable,
+};
+
+static struct regulator_desc mc9s08dz60_reg[] = {
+	{
+		.name = "LCD",
+		.id = MC9S08DZ60_LCD,
+		.ops = &mc9s08dz60_lcd_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	 },
+	{
+		.name = "WIFI",
+		.id = MC9S08DZ60_WIFI,
+		.ops = &mc9s08dz60_wifi_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	 },
+	{
+		.name = "HDD",
+		.id = MC9S08DZ60_HDD,
+		.ops = &mc9s08dz60_hdd_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	 },
+	{
+		.name = "GPS",
+		.id = MC9S08DZ60_GPS,
+		.ops = &mc9s08dz60_gps_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	 },
+	{
+		.name = "SPKR",
+		.id = MC9S08DZ60_SPKR,
+		.ops = &mc9s08dz60_speaker_ops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	 },
+
+};
+
+static int mc9s08dz60_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev;
+
+	/* register regulator */
+	rdev = regulator_register(&mc9s08dz60_reg[pdev->id], &pdev->dev,
+				  pdev->dev.platform_data,
+				  dev_get_drvdata(&pdev->dev));
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			mc9s08dz60_reg[pdev->id].name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+
+static int mc9s08dz60_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+}
+
+int mc9s08dz60_register_regulator(struct mc9s08dz60 *mc9s08dz60, int reg,
+			      struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	if (mc9s08dz60->pmic.pdev[reg])
+		return -EBUSY;
+
+	pdev = platform_device_alloc("mc9s08dz60-regu", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	mc9s08dz60->pmic.pdev[reg] = pdev;
+
+	initdata->driver_data = mc9s08dz60;
+
+	pdev->dev.platform_data = initdata;
+	pdev->dev.parent = mc9s08dz60->dev;
+	platform_set_drvdata(pdev, mc9s08dz60);
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		dev_err(mc9s08dz60->dev,
+			"Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+		mc9s08dz60->pmic.pdev[reg] = NULL;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mc9s08dz60_register_regulator);
+
+static struct platform_driver mc9s08dz60_regulator_driver = {
+	.probe = mc9s08dz60_regulator_probe,
+	.remove = mc9s08dz60_regulator_remove,
+	.driver		= {
+		.name	= "mc9s08dz60-regu",
+	},
+};
+
+static int __init mc9s08dz60_regulator_init(void)
+{
+	return platform_driver_register(&mc9s08dz60_regulator_driver);
+}
+subsys_initcall(mc9s08dz60_regulator_init);
+
+static void __exit mc9s08dz60_regulator_exit(void)
+{
+	platform_driver_unregister(&mc9s08dz60_regulator_driver);
+}
+module_exit(mc9s08dz60_regulator_exit);
+
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC9S08DZ60 Regulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/stmp3xxx.c b/drivers/regulator/stmp3xxx.c
new file mode 100644
index 000000000000..137e6e641ea4
--- /dev/null
+++ b/drivers/regulator/stmp3xxx.c
@@ -0,0 +1,301 @@
+/*
+ * Freescale STMP378X voltage regulators
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <mach/power.h>
+#include <mach/regulator.h>
+
+static int stmp3xxx_set_voltage(struct regulator_dev *reg, int MiniV, int uv)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	if (stmp_reg->rdata->set_voltage)
+		return stmp_reg->rdata->set_voltage(stmp_reg, uv);
+	else
+		return -ENOTSUPP;
+}
+
+
+static int stmp3xxx_get_voltage(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	if (stmp_reg->rdata->get_voltage)
+		return stmp_reg->rdata->get_voltage(stmp_reg);
+	else
+		return -ENOTSUPP;
+}
+
+static int stmp3xxx_set_current(struct regulator_dev *reg, int min_uA, int uA)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	if (stmp_reg->rdata->set_current)
+		return stmp_reg->rdata->set_current(stmp_reg, uA);
+	else
+		return -ENOTSUPP;
+}
+
+static int stmp3xxx_get_current(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	if (stmp_reg->rdata->get_current)
+		return stmp_reg->rdata->get_current(stmp_reg);
+	else
+		return -ENOTSUPP;
+}
+
+static int stmp3xxx_enable(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	return stmp_reg->rdata->enable(stmp_reg);
+}
+
+static int stmp3xxx_disable(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	return stmp_reg->rdata->disable(stmp_reg);
+}
+
+static int stmp3xxx_is_enabled(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	return stmp_reg->rdata->is_enabled(stmp_reg);
+}
+
+static int stmp3xxx_set_mode(struct regulator_dev *reg, unsigned int mode)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	return stmp_reg->rdata->set_mode(stmp_reg, mode);
+}
+
+static unsigned int stmp3xxx_get_mode(struct regulator_dev *reg)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	return stmp_reg->rdata->get_mode(stmp_reg);
+}
+
+static unsigned int stmp3xxx_get_optimum_mode(struct regulator_dev *reg,
+				int input_uV, int output_uV, int load_uA)
+{
+	struct stmp3xxx_regulator *stmp_reg = rdev_get_drvdata(reg);
+
+	if (stmp_reg->rdata->get_optimum_mode)
+		return stmp_reg->rdata->get_optimum_mode(stmp_reg, input_uV,
+							 output_uV, load_uA);
+	else
+		return -ENOTSUPP;
+}
+
+static struct regulator_ops stmp3xxx_rops = {
+	.set_voltage	= stmp3xxx_set_voltage,
+	.get_voltage	= stmp3xxx_get_voltage,
+	.set_current_limit	= stmp3xxx_set_current,
+	.get_current_limit	= stmp3xxx_get_current,
+	.enable		= stmp3xxx_enable,
+	.disable	= stmp3xxx_disable,
+	.is_enabled	= stmp3xxx_is_enabled,
+	.set_mode	= stmp3xxx_set_mode,
+	.get_mode	= stmp3xxx_get_mode,
+	.get_optimum_mode = stmp3xxx_get_optimum_mode,
+};
+
+static struct regulator_desc stmp3xxx_reg_desc[] = {
+	{
+		.name = "vddd",
+		.id = STMP3XXX_VDDD,
+		.ops = &stmp3xxx_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vdda",
+		.id = STMP3XXX_VDDA,
+		.ops = &stmp3xxx_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vddio",
+		.id = STMP3XXX_VDDIO,
+		.ops = &stmp3xxx_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "vddd_bo",
+		.id = STMP3XXX_VDDDBO,
+		.ops = &stmp3xxx_rops,
+		.irq = 0,
+		.type = REGULATOR_VOLTAGE,
+		.owner = THIS_MODULE
+	},
+	{
+		.name = "overall_current",
+		.id = STMP3XXX_OVERALL_CUR,
+		.ops = &stmp3xxx_rops,
+		.irq = 0,
+		.type = REGULATOR_CURRENT,
+		.owner = THIS_MODULE
+	},
+};
+
+static int reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	unsigned long flags;
+	struct stmp3xxx_regulator *sreg =
+		container_of(self, struct stmp3xxx_regulator , nb);
+
+	switch (event) {
+	case STMP3XXX_REG5V_IS_USB:
+		spin_lock_irqsave(&sreg->lock, flags);
+		sreg->rdata->max_current = 500000;
+		spin_unlock_irqrestore(&sreg->lock, flags);
+		break;
+	case STMP3XXX_REG5V_NOT_USB:
+		spin_lock_irqsave(&sreg->lock, flags);
+		sreg->rdata->max_current = 0x7fffffff;
+		spin_unlock_irqrestore(&sreg->lock, flags);
+		break;
+	}
+
+	return 0;
+}
+
+int stmp3xxx_regulator_probe(struct platform_device *pdev)
+{
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct stmp3xxx_regulator *sreg;
+	struct regulator_init_data *initdata;
+
+	sreg = platform_get_drvdata(pdev);
+	initdata = pdev->dev.platform_data;
+	sreg->cur_current = 0;
+	sreg->next_current = 0;
+	sreg->cur_voltage = 0;
+
+	init_waitqueue_head(&sreg->wait_q);
+	spin_lock_init(&sreg->lock);
+
+	if (pdev->id > STMP3XXX_OVERALL_CUR) {
+		rdesc = kzalloc(sizeof(struct regulator_desc), GFP_KERNEL);
+		memcpy(rdesc, &stmp3xxx_reg_desc[STMP3XXX_OVERALL_CUR],
+			sizeof(struct regulator_desc));
+		rdesc->name = kstrdup(sreg->rdata->name, GFP_KERNEL);
+	} else
+		rdesc = &stmp3xxx_reg_desc[pdev->id];
+
+	pr_debug("probing regulator %s %s %d\n",
+			sreg->rdata->name,
+			rdesc->name,
+			pdev->id);
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg);
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		return PTR_ERR(rdev);
+	}
+
+	if (sreg->rdata->max_current) {
+		struct regulator *regu;
+		regu = regulator_get(NULL, sreg->rdata->name);
+		sreg->nb.notifier_call = reg_callback;
+		regulator_register_notifier(regu, &sreg->nb);
+	}
+
+	return 0;
+}
+
+
+int stmp3xxx_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+
+	return 0;
+
+}
+
+int stmp3xxx_register_regulator(
+		struct stmp3xxx_regulator *reg_data, int reg,
+			      struct regulator_init_data *initdata)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	pdev = platform_device_alloc("stmp3xxx_reg", reg);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->dev.platform_data = initdata;
+
+	platform_set_drvdata(pdev, reg_data);
+	ret = platform_device_add(pdev);
+
+	if (ret != 0) {
+		pr_debug("Failed to register regulator %d: %d\n",
+			reg, ret);
+		platform_device_del(pdev);
+	}
+	pr_debug("register regulator %s, %d: %d\n",
+			reg_data->rdata->name, reg, ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(stmp3xxx_register_regulator);
+
+struct platform_driver stmp3xxx_reg = {
+	.driver = {
+		.name	= "stmp3xxx_reg",
+	},
+	.probe	= stmp3xxx_regulator_probe,
+	.remove	= stmp3xxx_regulator_remove,
+};
+
+int stmp3xxx_regulator_init(void)
+{
+	return platform_driver_register(&stmp3xxx_reg);
+}
+
+void stmp3xxx_regulator_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_reg);
+}
+
+postcore_initcall(stmp3xxx_regulator_init);
+module_exit(stmp3xxx_regulator_exit);
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 81adbdbd5042..09492700cddf 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -717,6 +717,52 @@ config RTC_DRV_PXA
          This RTC driver uses PXA RTC registers available since pxa27x
          series (RDxR, RYxR) instead of legacy RCNR, RTAR.
 
+config RTC_MXC
+	tristate "Freescale MXC Real Time Clock"
+	depends on ARCH_MXC
+	depends on RTC_CLASS
+	help
+	  Support for Freescale RTC MXC
+
+config RTC_DRV_MXC_V2
+	tristate "Freescale MXC Secure Real Time Clock"
+	depends on ARCH_MXC
+	depends on RTC_CLASS
+	help
+	  Support for Freescale SRTC MXC
+
+config RTC_DRV_IMXDI
+	tristate "Freescale IMX DryIce Real Time Clock"
+	depends on ARCH_MXC
+	depends on RTC_CLASS
+	help
+	  Support for Freescale IMX DryIce RTC
+
+config RTC_MC13892
+	tristate "Freescale MC13892 Real Time Clock"
+	depends on ARCH_MXC && MXC_PMIC_MC13892
+	depends on RTC_CLASS
+	help
+	  Support for Freescale MC13892 RTC
+
+config RTC_DRV_STMP3XXX
+	tristate "Sigmatel STMP3xxx series SoC RTC"
+	depends on ARCH_STMP3XXX && RTC_CLASS
+	help
+	  Say Y here to get support for the real-time clock peripheral
+	  on Sigmatel STMP3xxx series SoCs (tested on STMP3700).
+
+	  This driver can also be build as a module. If so, the module
+	  will be called rtc-stmp3xxx.
+
+config RTC_DRV_MXS
+	tristate "Freescale MXS series SoC RTC"
+	depends on ARCH_MXS && RTC_CLASS
+	help
+	  Say Y here to get support for the real-time clock peripheral
+	  on Freescale MXS series SoCs
+	  This driver can also be build as a module. If so, the module
+	  will be called rtc-mxs.
 
 config RTC_DRV_SUN4V
 	bool "SUN4V Hypervisor RTC"
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3c0f2b2ac927..91da97eca589 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -78,3 +78,9 @@ obj-$(CONFIG_RTC_DRV_WM8350)	+= rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)	+= rtc-x1205.o
 obj-$(CONFIG_RTC_DRV_PCF50633)	+= rtc-pcf50633.o
 obj-$(CONFIG_RTC_DRV_PS3)	+= rtc-ps3.o
+obj-$(CONFIG_RTC_MXC)		+= rtc-mxc.o
+obj-$(CONFIG_RTC_DRV_MXC_V2)	+= rtc-mxc_v2.o
+obj-$(CONFIG_RTC_DRV_IMXDI)	+= rtc-imxdi.o
+obj-$(CONFIG_RTC_MC13892)		+= rtc-mc13892.o
+obj-$(CONFIG_RTC_DRV_STMP3XXX)	+= rtc-stmp3xxx.o
+obj-$(CONFIG_RTC_DRV_MXS)	+= rtc-mxs.o
diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
new file mode 100644
index 000000000000..b54fb638c840
--- /dev/null
+++ b/drivers/rtc/rtc-imxdi.c
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* based on rtc-mc13892.c */
+
+/*
+ * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
+ * to implement a Linux RTC. Times and alarms are truncated to seconds.
+ * Since the RTC framework performs API locking via rtc->ops_lock the
+ * only simultaneous accesses we need to deal with is updating DryIce
+ * registers while servicing an alarm.
+ *
+ * Note that reading the DSR (DryIce Status Register) automatically clears
+ * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
+ * LP (Low Power) domain and set the WCF upon completion. Writes to the
+ * DIER (DryIce Interrupt Enable Register) are the only exception. These
+ * occur at normal bus speeds and do not set WCF.  Periodic interrupts are
+ * not supported by the hardware.
+ */
+
+/* #define DEBUG */
+/* #define DI_DEBUG_REGIO */
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/workqueue.h>
+
+/* DryIce Register Definitions */
+
+#define DTCMR     0x00           /* Time Counter MSB Reg */
+#define DTCLR     0x04           /* Time Counter LSB Reg */
+
+#define DCAMR     0x08           /* Clock Alarm MSB Reg */
+#define DCALR     0x0c           /* Clock Alarm LSB Reg */
+#define DCAMR_UNSET  0xFFFFFFFF  /* doomsday - 1 sec */
+
+#define DCR       0x10           /* Control Reg */
+#define DCR_TCE   (1 << 3)       /* Time Counter Enable */
+
+#define DSR       0x14           /* Status Reg */
+#define DSR_WBF   (1 << 10)      /* Write Busy Flag */
+#define DSR_WNF   (1 << 9)       /* Write Next Flag */
+#define DSR_WCF   (1 << 8)       /* Write Complete Flag */
+#define DSR_WEF   (1 << 7)       /* Write Error Flag */
+#define DSR_CAF   (1 << 4)       /* Clock Alarm Flag */
+#define DSR_NVF   (1 << 1)       /* Non-Valid Flag */
+#define DSR_SVF   (1 << 0)       /* Security Violation Flag */
+
+#define DIER      0x18           /* Interrupt Enable Reg */
+#define DIER_WNIE (1 << 9)       /* Write Next Interrupt Enable */
+#define DIER_WCIE (1 << 8)       /* Write Complete Interrupt Enable */
+#define DIER_WEIE (1 << 7)       /* Write Error Interrupt Enable */
+#define DIER_CAIE (1 << 4)       /* Clock Alarm Interrupt Enable */
+
+#ifndef DI_DEBUG_REGIO
+/* dryice read register */
+#define di_read(pdata, reg)  __raw_readl((pdata)->ioaddr + (reg))
+
+/* dryice write register */
+#define di_write(pdata, val, reg)  __raw_writel((val), (pdata)->ioaddr + (reg))
+#else
+/* dryice read register - debug version */
+static inline u32 di_read(struct rtc_drv_data *pdata, int reg)
+{
+	u32 val = __raw_readl(pdata->ioaddr + reg);
+	pr_info("di_read(0x%02x) = 0x%08x\n", reg, val);
+	return val;
+}
+
+/* dryice write register - debug version */
+static inline void di_write(struct rtc_drv_data *pdata, u32 val, int reg)
+{
+	printk(KERN_INFO "di_write(0x%08x, 0x%02x)\n", val, reg);
+	__raw_writel(val, pdata->ioaddr + reg);
+}
+#endif
+
+/*
+ * dryice write register with wait and error handling.
+ * all registers, except for DIER, should use this method.
+ */
+#define di_write_wait_err(pdata, val, reg, rc, label) \
+		do { \
+			if (di_write_wait((pdata), (val), (reg))) { \
+				rc = -EIO; \
+				goto label; \
+			} \
+		} while (0)
+
+struct rtc_drv_data {
+	struct platform_device *pdev;  /* pointer to platform dev */
+	struct rtc_device *rtc;        /* pointer to rtc struct */
+	unsigned long baseaddr;        /* physical bass address */
+	void __iomem *ioaddr;          /* virtual base address */
+	int size;                      /* size of register region */
+	int irq;                       /* dryice normal irq */
+	struct clk *clk;               /* dryice clock control */
+	u32 dsr;                       /* copy of dsr reg from isr */
+	spinlock_t irq_lock;           /* irq resource lock */
+	wait_queue_head_t write_wait;  /* write-complete queue */
+	struct mutex write_mutex;      /* force reg writes to be sequential */
+	struct work_struct work;       /* schedule alarm work */
+};
+
+/*
+ * enable a dryice interrupt
+ */
+static inline void di_int_enable(struct rtc_drv_data *pdata, u32 intr)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pdata->irq_lock, flags);
+	di_write(pdata, di_read(pdata, DIER) | intr, DIER);
+	spin_unlock_irqrestore(&pdata->irq_lock, flags);
+}
+
+/*
+ * disable a dryice interrupt
+ */
+static inline void di_int_disable(struct rtc_drv_data *pdata, u32 intr)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pdata->irq_lock, flags);
+	di_write(pdata, di_read(pdata, DIER) & ~intr, DIER);
+	spin_unlock_irqrestore(&pdata->irq_lock, flags);
+}
+
+/*
+ * This function attempts to clear the dryice write-error flag.
+ *
+ * A dryice write error is similar to a bus fault and should not occur in
+ * normal operation.  Clearing the flag requires another write, so the root
+ * cause of the problem may need to be fixed before the flag can be cleared.
+ */
+static void clear_write_error(struct rtc_drv_data *pdata)
+{
+	int cnt;
+
+	dev_warn(&pdata->pdev->dev, "WARNING: Register write error!\n");
+
+	for (;;) {
+		/* clear the write error flag */
+		di_write(pdata, DSR_WEF, DSR);
+
+		/* wait for it to take effect */
+		for (cnt = 0; cnt < 100; cnt++) {
+			if ((di_read(pdata, DSR) & DSR_WEF) == 0)
+				return;
+			udelay(10);
+		}
+		dev_err(&pdata->pdev->dev,
+			"ERROR: Cannot clear write-error flag!\n");
+	}
+}
+
+/*
+ * Write a dryice register and wait until it completes.
+ *
+ * This function uses interrupts to determine when the
+ * write has completed.
+ */
+static int di_write_wait(struct rtc_drv_data *pdata, u32 val, int reg)
+{
+	int ret;
+	int rc = 0;
+
+	/* serialize register writes */
+	mutex_lock(&pdata->write_mutex);
+
+	/* enable the write-complete interrupt */
+	di_int_enable(pdata, DIER_WCIE);
+
+	pdata->dsr = 0;
+
+	/* do the register write */
+	di_write(pdata, val, reg);
+
+	/* wait for the write to finish */
+	ret = wait_event_interruptible_timeout(pdata->write_wait,
+					       pdata->dsr & (DSR_WCF | DSR_WEF),
+					       1 * HZ);
+	if (ret == 0)
+		dev_warn(&pdata->pdev->dev, "Write-wait timeout\n");
+
+	/* check for write error */
+	if (pdata->dsr & DSR_WEF) {
+		clear_write_error(pdata);
+		rc = -EIO;
+	}
+	mutex_unlock(&pdata->write_mutex);
+	return rc;
+}
+
+/*
+ * rtc device ioctl
+ *
+ * The rtc framework handles the basic rtc ioctls on behalf
+ * of the driver by calling the functions registered in the
+ * rtc_ops structure.
+ */
+static int dryice_rtc_ioctl(struct device *dev, unsigned int cmd,
+			    unsigned long arg)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+
+	dev_dbg(dev, "%s(0x%x)\n", __func__, cmd);
+	switch (cmd) {
+	case RTC_AIE_OFF:  /* alarm disable */
+		di_int_disable(pdata, DIER_CAIE);
+		return 0;
+
+	case RTC_AIE_ON:  /* alarm enable */
+		di_int_enable(pdata, DIER_CAIE);
+		return 0;
+	}
+	return -ENOIOCTLCMD;
+}
+
+/*
+ * read the seconds portion of the current time from the dryice time counter
+ */
+static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	unsigned long now;
+
+	dev_dbg(dev, "%s\n", __func__);
+	now = di_read(pdata, DTCMR);
+	rtc_time_to_tm(now, tm);
+
+	return 0;
+}
+
+/*
+ * set the seconds portion of dryice time counter and clear the
+ * fractional part.
+ */
+static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	unsigned long now;
+	int rc;
+
+	dev_dbg(dev, "%s\n", __func__);
+	rc = rtc_tm_to_time(tm, &now);
+	if (rc == 0) {
+		/* zero the fractional part first */
+		di_write_wait_err(pdata, 0, DTCLR, rc, err);
+		di_write_wait_err(pdata, now, DTCMR, rc, err);
+	}
+err:
+	return rc;
+}
+
+/*
+ * read the seconds portion of the alarm register.
+ * the fractional part of the alarm register is always zero.
+ */
+static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	u32 dcamr;
+
+	dev_dbg(dev, "%s\n", __func__);
+	dcamr = di_read(pdata, DCAMR);
+	rtc_time_to_tm(dcamr, &alarm->time);
+
+	/* alarm is enabled if the interrupt is enabled */
+	alarm->enabled = (di_read(pdata, DIER) & DIER_CAIE) != 0;
+
+	/* don't allow the DSR read to mess up DSR_WCF */
+	mutex_lock(&pdata->write_mutex);
+
+	/* alarm is pending if the alarm flag is set */
+	alarm->pending = (di_read(pdata, DSR) & DSR_CAF) != 0;
+
+	mutex_unlock(&pdata->write_mutex);
+
+	return 0;
+}
+
+/*
+ * set the seconds portion of dryice alarm register
+ */
+static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	unsigned long now;
+	unsigned long alarm_time;
+	int rc;
+
+	dev_dbg(dev, "%s\n", __func__);
+	rc = rtc_tm_to_time(&alarm->time, &alarm_time);
+	if (rc)
+		return rc;
+
+	/* don't allow setting alarm in the past */
+	now = di_read(pdata, DTCMR);
+	if (alarm_time < now)
+		return -EINVAL;
+
+	/* write the new alarm time */
+	di_write_wait_err(pdata, (u32)alarm_time, DCAMR, rc, err);
+
+	if (alarm->enabled)
+		di_int_enable(pdata, DIER_CAIE);  /* enable alarm intr */
+	else
+		di_int_disable(pdata, DIER_CAIE); /* disable alarm intr */
+err:
+	return rc;
+}
+
+static struct rtc_class_ops dryice_rtc_ops = {
+	.ioctl = dryice_rtc_ioctl,
+	.read_time = dryice_rtc_read_time,
+	.set_time = dryice_rtc_set_time,
+	.read_alarm = dryice_rtc_read_alarm,
+	.set_alarm = dryice_rtc_set_alarm,
+};
+
+/*
+ * dryice "normal" interrupt handler
+ */
+static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
+{
+	struct rtc_drv_data *pdata = dev_id;
+	u32 dsr, dier;
+	irqreturn_t rc = IRQ_NONE;
+
+	dier = di_read(pdata, DIER);
+
+	/* handle write complete and write error cases */
+	if ((dier & DIER_WCIE)) {
+		/*If the write wait queue is empty then there is no pending
+		   operations. It means the interrupt is for DryIce -Security.
+		   IRQ must be returned as none.*/
+		if (list_empty_careful(&pdata->write_wait.task_list))
+			return rc;
+
+		/* DSR_WCF clears itself on DSR read */
+	    dsr = di_read(pdata, DSR);
+		if ((dsr & (DSR_WCF | DSR_WEF))) {
+			/* mask the interrupt */
+			di_int_disable(pdata, DIER_WCIE);
+
+			/* save the dsr value for the wait queue */
+			pdata->dsr |= dsr;
+
+			wake_up_interruptible(&pdata->write_wait);
+			rc = IRQ_HANDLED;
+		}
+	}
+
+	/* handle the alarm case */
+	if ((dier & DIER_CAIE)) {
+		/* DSR_WCF clears itself on DSR read */
+	    dsr = di_read(pdata, DSR);
+		if (dsr & DSR_CAF) {
+			/* mask the interrupt */
+			di_int_disable(pdata, DIER_CAIE);
+
+			/* finish alarm in user context */
+			schedule_work(&pdata->work);
+			rc = IRQ_HANDLED;
+		}
+	}
+	return rc;
+}
+
+/*
+ * post the alarm event from user context so it can sleep
+ * on the write completion.
+ */
+static void dryice_work(struct work_struct *work)
+{
+	struct rtc_drv_data *pdata = container_of(work, struct rtc_drv_data,
+						  work);
+	int rc;
+
+	/* dismiss the interrupt (ignore error) */
+	di_write_wait_err(pdata, DSR_CAF, DSR, rc, err);
+err:
+	/*
+	 * pass the alarm event to the rtc framework. note that
+	 * rtc_update_irq expects to be called with interrupts off.
+	 */
+	local_irq_disable();
+	rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
+	local_irq_enable();
+}
+
+/*
+ * probe for dryice rtc device
+ */
+static int dryice_rtc_probe(struct platform_device *pdev)
+{
+	struct rtc_device *rtc;
+	struct resource *res;
+	struct rtc_drv_data *pdata = NULL;
+	void __iomem *ioaddr = NULL;
+	int rc = 0;
+
+	dev_dbg(&pdev->dev, "%s\n", __func__);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->pdev = pdev;
+	pdata->irq = -1;
+	pdata->size = res->end - res->start + 1;
+
+	if (!request_mem_region(res->start, pdata->size, pdev->name)) {
+		rc = -EBUSY;
+		goto err;
+	}
+	pdata->baseaddr = res->start;
+	ioaddr = ioremap(pdata->baseaddr, pdata->size);
+	if (!ioaddr) {
+		rc = -ENOMEM;
+		goto err;
+	}
+	pdata->ioaddr = ioaddr;
+	pdata->irq = platform_get_irq(pdev, 0);
+
+	init_waitqueue_head(&pdata->write_wait);
+
+	INIT_WORK(&pdata->work, dryice_work);
+
+	mutex_init(&pdata->write_mutex);
+
+	pdata->clk = clk_get(NULL, "dryice_clk");
+	clk_enable(pdata->clk);
+
+	if (pdata->irq >= 0) {
+		if (request_irq(pdata->irq, dryice_norm_irq, IRQF_SHARED,
+				pdev->name, pdata) < 0) {
+			dev_warn(&pdev->dev, "interrupt not available.\n");
+			pdata->irq = -1;
+			goto err;
+		}
+	}
+
+	/*
+	 * Initialize dryice hardware
+	 */
+
+	/* put dryice into valid state */
+	if (di_read(pdata, DSR) & DSR_NVF)
+		di_write_wait_err(pdata, DSR_NVF | DSR_SVF, DSR, rc, err);
+
+	/* mask alarm interrupt */
+	di_int_disable(pdata, DIER_CAIE);
+
+	/* initialize alarm */
+	di_write_wait_err(pdata, DCAMR_UNSET, DCAMR, rc, err);
+	di_write_wait_err(pdata, 0, DCALR, rc, err);
+
+	/* clear alarm flag */
+	if (di_read(pdata, DSR) & DSR_CAF)
+		di_write_wait_err(pdata, DSR_CAF, DSR, rc, err);
+
+	/* the timer won't count if it has never been written to */
+	if (!di_read(pdata, DTCMR))
+		di_write_wait_err(pdata, 0, DTCMR, rc, err);
+
+	/* start keeping time */
+	if (!(di_read(pdata, DCR) & DCR_TCE))
+		di_write_wait_err(pdata, di_read(pdata, DCR) | DCR_TCE, DCR,
+				  rc, err);
+
+	rtc = rtc_device_register(pdev->name, &pdev->dev,
+				  &dryice_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc)) {
+		rc = PTR_ERR(rtc);
+		goto err;
+	}
+	pdata->rtc = rtc;
+	platform_set_drvdata(pdev, pdata);
+
+	return 0;
+err:
+	if (pdata->rtc)
+		rtc_device_unregister(pdata->rtc);
+
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdata);
+
+	if (pdata->clk) {
+		clk_disable(pdata->clk);
+		clk_put(pdata->clk);
+	}
+
+	if (pdata->ioaddr)
+		iounmap(pdata->ioaddr);
+
+	if (pdata->baseaddr)
+		release_mem_region(pdata->baseaddr, pdata->size);
+
+	kfree(pdata);
+
+	return rc;
+}
+
+static int __exit dryice_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	flush_scheduled_work();
+
+	if (pdata->rtc)
+		rtc_device_unregister(pdata->rtc);
+
+	/* mask alarm interrupt */
+	di_int_disable(pdata, DIER_CAIE);
+
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdata);
+
+	if (pdata->clk) {
+		clk_disable(pdata->clk);
+		clk_put(pdata->clk);
+	}
+
+	if (pdata->ioaddr)
+		iounmap(pdata->ioaddr);
+
+	if (pdata->baseaddr)
+		release_mem_region(pdata->baseaddr, pdata->size);
+
+	kfree(pdata);
+
+	return 0;
+}
+
+static struct platform_driver dryice_rtc_driver = {
+	.driver = {
+		   .name = "imxdi_rtc",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = dryice_rtc_probe,
+	.remove = __exit_p(dryice_rtc_remove),
+};
+
+static int __init dryice_rtc_init(void)
+{
+	pr_info("IMXDI Realtime Clock Driver (RTC)\n");
+	return platform_driver_register(&dryice_rtc_driver);
+}
+
+static void __exit dryice_rtc_exit(void)
+{
+	platform_driver_unregister(&dryice_rtc_driver);
+}
+
+module_init(dryice_rtc_init);
+module_exit(dryice_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IMXDI Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-mc13892.c b/drivers/rtc/rtc-mc13892.c
new file mode 100644
index 000000000000..e579c1853a26
--- /dev/null
+++ b/drivers/rtc/rtc-mc13892.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pmic_status.h>
+#include <linux/pmic_external.h>
+
+#define RTC_TIME_LSH		0
+#define RTC_DAY_LSH		0
+#define RTCALARM_TIME_LSH	0
+#define RTCALARM_DAY_LSH	0
+
+#define RTC_TIME_WID		17
+#define RTC_DAY_WID		15
+#define RTCALARM_TIME_WID	17
+#define RTCALARM_DAY_WID	15
+
+static unsigned long rtc_status;
+
+static int mxc_rtc_open(struct device *dev)
+{
+	if (test_and_set_bit(1, &rtc_status))
+		return -EBUSY;
+	return 0;
+}
+
+static void mxc_rtc_release(struct device *dev)
+{
+	clear_bit(1, &rtc_status);
+}
+
+static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
+			 unsigned long arg)
+{
+	switch (cmd) {
+	case RTC_AIE_OFF:
+		pr_debug("alarm off\n");
+		CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0x100000, 0x100000));
+		return 0;
+	case RTC_AIE_ON:
+		pr_debug("alarm on\n");
+		CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0, 0x100000));
+		return 0;
+	}
+
+	return -ENOIOCTLCMD;
+}
+
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0, day_reg_val2;
+	unsigned int mask, value;
+	unsigned long time;
+
+	do {
+		mask = BITFMASK(RTC_DAY);
+		CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask));
+		day_reg_val = BITFEXT(value, RTC_DAY);
+
+		mask = BITFMASK(RTC_TIME);
+		CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask));
+		tod_reg_val = BITFEXT(value, RTC_TIME);
+
+		mask = BITFMASK(RTC_DAY);
+		CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask));
+		day_reg_val2 = BITFEXT(value, RTC_DAY);
+	} while (day_reg_val != day_reg_val2);
+
+	time = (unsigned long)((unsigned long)(tod_reg_val &
+					       0x0001FFFF) +
+			       (unsigned long)(day_reg_val * 86400));
+
+	rtc_time_to_tm(time, tm);
+
+	return 0;
+}
+
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val, day_reg_val2 = 0;
+	unsigned int mask, value;
+	unsigned long time;
+
+	if (rtc_valid_tm(tm))
+		return -1;
+
+	rtc_tm_to_time(tm, &time);
+
+	tod_reg_val = time % 86400;
+	day_reg_val = time / 86400;
+
+	do {
+		mask = BITFMASK(RTC_DAY);
+		value = BITFVAL(RTC_DAY, day_reg_val);
+		CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask));
+
+		mask = BITFMASK(RTC_TIME);
+		value = BITFVAL(RTC_TIME, tod_reg_val);
+		CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask));
+
+		mask = BITFMASK(RTC_DAY);
+		CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask));
+		day_reg_val2 = BITFEXT(value, RTC_DAY);
+	} while (day_reg_val != day_reg_val2);
+
+	return 0;
+}
+
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+	unsigned long time;
+
+	mask = BITFMASK(RTCALARM_TIME);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask));
+	tod_reg_val = BITFEXT(value, RTCALARM_TIME);
+
+	mask = BITFMASK(RTCALARM_DAY);
+	CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask));
+	day_reg_val = BITFEXT(value, RTCALARM_DAY);
+
+	time = (unsigned long)((unsigned long)(tod_reg_val &
+					       0x0001FFFF) +
+			       (unsigned long)(day_reg_val * 86400));
+	rtc_time_to_tm(time, &(alrm->time));
+
+	return 0;
+}
+
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	unsigned int tod_reg_val = 0;
+	unsigned int day_reg_val = 0;
+	unsigned int mask, value;
+	unsigned long time;
+
+	if (rtc_valid_tm(&alrm->time))
+		return -1;
+
+	rtc_tm_to_time(&alrm->time, &time);
+
+	tod_reg_val = time % 86400;
+	day_reg_val = time / 86400;
+
+	mask = BITFMASK(RTCALARM_TIME);
+	value = BITFVAL(RTCALARM_TIME, tod_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask));
+
+	mask = BITFMASK(RTCALARM_DAY);
+	value = BITFVAL(RTCALARM_DAY, day_reg_val);
+	CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask));
+
+	return 0;
+}
+
+struct rtc_drv_data {
+	struct rtc_device *rtc;
+	pmic_event_callback_t event;
+};
+
+static struct rtc_class_ops mxc_rtc_ops = {
+	.open = mxc_rtc_open,
+	.release = mxc_rtc_release,
+	.ioctl = mxc_rtc_ioctl,
+	.read_time = mxc_rtc_read_time,
+	.set_time = mxc_rtc_set_time,
+	.read_alarm = mxc_rtc_read_alarm,
+	.set_alarm = mxc_rtc_set_alarm,
+};
+
+static void mxc_rtc_alarm_int(void *data)
+{
+	struct rtc_drv_data *pdata = data;
+
+	rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
+}
+
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = NULL;
+
+	printk(KERN_INFO "mc13892 rtc probe start\n");
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->event.func = mxc_rtc_alarm_int;
+	pdata->event.param = pdata;
+	CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, pdata->event));
+
+	device_init_wakeup(&pdev->dev, 1);
+	pdata->rtc = rtc_device_register(pdev->name, &pdev->dev,
+					 &mxc_rtc_ops, THIS_MODULE);
+
+	platform_set_drvdata(pdev, pdata);
+	if (IS_ERR(pdata->rtc))
+		return -1;
+
+	printk(KERN_INFO "mc13892 rtc probe succeed\n");
+	return 0;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	rtc_device_unregister(pdata->rtc);
+	CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, pdata->event));
+
+	return 0;
+}
+
+static struct platform_driver mxc_rtc_driver = {
+	.driver = {
+		   .name = "pmic_rtc",
+		   },
+	.probe = mxc_rtc_probe,
+	.remove = __exit_p(mxc_rtc_remove),
+};
+
+static int __init mxc_rtc_init(void)
+{
+	return platform_driver_register(&mxc_rtc_driver);
+}
+
+static void __exit mxc_rtc_exit(void)
+{
+	platform_driver_unregister(&mxc_rtc_driver);
+
+}
+
+module_init(mxc_rtc_init);
+module_exit(mxc_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MC13892 Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
new file mode 100644
index 000000000000..00e5158ab931
--- /dev/null
+++ b/drivers/rtc/rtc-mxc.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Implementation based on rtc-ds1553.c
+ */
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+
+#include <mach/hardware.h>
+#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
+#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
+#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)
+
+#define RTC_SW_BIT      (1 << 0)
+#define RTC_ALM_BIT     (1 << 2)
+#define RTC_1HZ_BIT     (1 << 4)
+#define RTC_2HZ_BIT     (1 << 7)
+#define RTC_SAM0_BIT    (1 << 8)
+#define RTC_SAM1_BIT    (1 << 9)
+#define RTC_SAM2_BIT    (1 << 10)
+#define RTC_SAM3_BIT    (1 << 11)
+#define RTC_SAM4_BIT    (1 << 12)
+#define RTC_SAM5_BIT    (1 << 13)
+#define RTC_SAM6_BIT    (1 << 14)
+#define RTC_SAM7_BIT    (1 << 15)
+#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
+                         RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
+                         RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
+
+#define RTC_ENABLE_BIT  (1 << 7)
+
+#define MAX_PIE_NUM     9
+#define MAX_PIE_FREQ    512
+const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
+	{2, RTC_2HZ_BIT},
+	{4, RTC_SAM0_BIT},
+	{8, RTC_SAM1_BIT},
+	{16, RTC_SAM2_BIT},
+	{32, RTC_SAM3_BIT},
+	{64, RTC_SAM4_BIT},
+	{128, RTC_SAM5_BIT},
+	{256, RTC_SAM6_BIT},
+	{MAX_PIE_FREQ, RTC_SAM7_BIT},
+};
+
+/* Those are the bits from a classic RTC we want to mimic */
+#define RTC_IRQF                0x80	/* any of the following 3 is active */
+#define RTC_PF                  0x40	/* Periodic interrupt */
+#define RTC_AF                  0x20	/* Alarm interrupt */
+#define RTC_UF                  0x10	/* Update interrupt for 1Hz RTC */
+
+#define MXC_RTC_TIME            0
+#define MXC_RTC_ALARM           1
+
+#define RTC_HOURMIN    0x00	/*  32bit rtc hour/min counter reg */
+#define RTC_SECOND     0x04	/*  32bit rtc seconds counter reg */
+#define RTC_ALRM_HM    0x08	/*  32bit rtc alarm hour/min reg */
+#define RTC_ALRM_SEC   0x0C	/*  32bit rtc alarm seconds reg */
+#define RTC_RTCCTL     0x10	/*  32bit rtc control reg */
+#define RTC_RTCISR     0x14	/*  32bit rtc interrupt status reg */
+#define RTC_RTCIENR    0x18	/*  32bit rtc interrupt enable reg */
+#define RTC_STPWCH     0x1C	/*  32bit rtc stopwatch min reg */
+#define RTC_DAYR       0x20	/*  32bit rtc days counter reg */
+#define RTC_DAYALARM   0x24	/*  32bit rtc day alarm reg */
+#define RTC_TEST1      0x28	/*  32bit rtc test reg 1 */
+#define RTC_TEST2      0x2C	/*  32bit rtc test reg 2 */
+#define RTC_TEST3      0x30	/*  32bit rtc test reg 3 */
+
+struct rtc_plat_data {
+	struct rtc_device *rtc;
+	void __iomem *ioaddr;
+	unsigned long baseaddr;
+	int irq;
+	struct clk *clk;
+	unsigned int irqen;
+	int alrm_sec;
+	int alrm_min;
+	int alrm_hour;
+	int alrm_mday;
+};
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#define RTC_VERSION		"1.0"
+#define MXC_EXTERNAL_RTC_OK	0
+#define MXC_EXTERNAL_RTC_ERR	-1
+#define MXC_EXTERNAL_RTC_NONE	-2
+
+static u32 rtc_freq = 2;	/* minimun value for PIE */
+static unsigned long rtc_status;
+
+static struct rtc_time g_rtc_alarm = {
+	.tm_year = 0,
+	.tm_mon = 0,
+	.tm_mday = 0,
+	.tm_hour = 0,
+	.tm_mon = 0,
+	.tm_sec = 0,
+};
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+/*!
+ * This function is used to obtain the RTC time or the alarm value in
+ * second.
+ *
+ * @param  time_alarm   use MXC_RTC_TIME for RTC time value; MXC_RTC_ALARM for alarm value
+ *
+ * @return The RTC time or alarm time in second.
+ */
+static u32 get_alarm_or_time(struct device *dev, int time_alarm)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 day, hr, min, sec, hr_min;
+	if (time_alarm == MXC_RTC_TIME) {
+		day = readw(ioaddr + RTC_DAYR);
+		hr_min = readw(ioaddr + RTC_HOURMIN);
+		sec = readw(ioaddr + RTC_SECOND);
+	} else if (time_alarm == MXC_RTC_ALARM) {
+		day = readw(ioaddr + RTC_DAYALARM);
+		hr_min = (0x0000FFFF) & readw(ioaddr + RTC_ALRM_HM);
+		sec = readw(ioaddr + RTC_ALRM_SEC);
+	} else {
+		panic("wrong value for time_alarm=%d\n", time_alarm);
+	}
+
+	hr = hr_min >> 8;
+	min = hr_min & 0x00FF;
+
+	return ((((day * 24 + hr) * 60) + min) * 60 + sec);
+}
+
+/*!
+ * This function sets the RTC alarm value or the time value.
+ *
+ * @param  time_alarm   the new alarm value to be updated in the RTC
+ * @param  time         use MXC_RTC_TIME for RTC time value; MXC_RTC_ALARM for alarm value
+ */
+static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time)
+{
+	u32 day, hr, min, sec, temp;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	day = time / 86400;
+	time -= day * 86400;
+	/* time is within a day now */
+	hr = time / 3600;
+	time -= hr * 3600;
+	/* time is within an hour now */
+	min = time / 60;
+	sec = time - min * 60;
+
+	temp = (hr << 8) + min;
+
+	if (time_alarm == MXC_RTC_TIME) {
+		writew(day, ioaddr + RTC_DAYR);
+		writew(sec, ioaddr + RTC_SECOND);
+		writew(temp, ioaddr + RTC_HOURMIN);
+	} else if (time_alarm == MXC_RTC_ALARM) {
+		writew(day, ioaddr + RTC_DAYALARM);
+		writew(sec, ioaddr + RTC_ALRM_SEC);
+		writew(temp, ioaddr + RTC_ALRM_HM);
+	} else {
+		panic("wrong value for time_alarm=%d\n", time_alarm);
+	}
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param  alrm         the new alarm value to be updated in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+	struct rtc_time alarm_tm, now_tm;
+	unsigned long now, time;
+	int ret;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	now = get_alarm_or_time(dev, MXC_RTC_TIME);
+	rtc_time_to_tm(now, &now_tm);
+	alarm_tm.tm_year = now_tm.tm_year;
+	alarm_tm.tm_mon = now_tm.tm_mon;
+	alarm_tm.tm_mday = now_tm.tm_mday;
+	alarm_tm.tm_hour = alrm->tm_hour;
+	alarm_tm.tm_min = alrm->tm_min;
+	alarm_tm.tm_sec = alrm->tm_sec;
+	rtc_tm_to_time(&now_tm, &now);
+	rtc_tm_to_time(&alarm_tm, &time);
+	if (time < now) {
+		time += 60 * 60 * 24;
+		rtc_time_to_tm(time, &alarm_tm);
+	}
+	ret = rtc_tm_to_time(&alarm_tm, &time);
+
+	/* clear all the interrupt status bits */
+	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
+
+	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
+
+	return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param  irq          RTC IRQ number
+ * @param  dev_id       device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 status;
+	u32 events = 0;
+	spin_lock(&rtc_lock);
+	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
+	/* clear interrupt sources */
+	writew(status, ioaddr + RTC_RTCISR);
+
+	/* clear alarm interrupt if it has occurred */
+	if (status & RTC_ALM_BIT) {
+		status &= ~RTC_ALM_BIT;
+	}
+
+	/* update irq data & counter */
+	if (status & RTC_ALM_BIT) {
+		events |= (RTC_AF | RTC_IRQF);
+	}
+	if (status & RTC_1HZ_BIT) {
+		events |= (RTC_UF | RTC_IRQF);
+	}
+	if (status & PIT_ALL_ON) {
+		events |= (RTC_PF | RTC_IRQF);
+	}
+
+	if ((status & RTC_ALM_BIT) && rtc_valid_tm(&g_rtc_alarm)) {
+		rtc_update_alarm(&pdev->dev, &g_rtc_alarm);
+	}
+
+	spin_unlock(&rtc_lock);
+	rtc_update_irq(pdata->rtc, 1, events);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to open the RTC driver by registering the RTC
+ * interrupt service routine.
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_open(struct device *dev)
+{
+	if (test_and_set_bit(1, &rtc_status))
+		return -EBUSY;
+	return 0;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void mxc_rtc_release(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	spin_lock_irq(&rtc_lock);
+	writew(0, ioaddr + RTC_RTCIENR);	/* Disable all rtc interrupts */
+	writew(0xFFFFFFFF, ioaddr + RTC_RTCISR);	/* Clear all interrupt status */
+	spin_unlock_irq(&rtc_lock);
+	rtc_status = 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param  cmd          ioctl command as defined in include/linux/rtc.h
+ * @param  arg          value for the ioctl command
+ *
+ * @return  0 if successful or negative value otherwise.
+ */
+static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
+			 unsigned long arg)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	int i;
+	switch (cmd) {
+	case RTC_PIE_OFF:
+		writew((readw(ioaddr + RTC_RTCIENR) & ~PIT_ALL_ON),
+		       ioaddr + RTC_RTCIENR);
+		return 0;
+	case RTC_IRQP_SET:
+		if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0)
+			return -EINVAL;	/* Also make sure a power of 2Hz */
+		if ((arg > 64) && (!capable(CAP_SYS_RESOURCE)))
+			return -EACCES;
+		rtc_freq = arg;
+		return 0;
+	case RTC_IRQP_READ:
+		return put_user(rtc_freq, (u32 *) arg);
+	case RTC_PIE_ON:
+		for (i = 0; i < MAX_PIE_NUM; i++) {
+			if (PIE_BIT_DEF[i][0] == rtc_freq) {
+				break;
+			}
+		}
+		if (i == MAX_PIE_NUM) {
+			return -EACCES;
+		}
+		spin_lock_irq(&rtc_lock);
+		writew((readw(ioaddr + RTC_RTCIENR) | PIE_BIT_DEF[i][1]),
+		       ioaddr + RTC_RTCIENR);
+		spin_unlock_irq(&rtc_lock);
+		return 0;
+	case RTC_AIE_OFF:
+		spin_lock_irq(&rtc_lock);
+		writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_ALM_BIT),
+		       ioaddr + RTC_RTCIENR);
+		spin_unlock_irq(&rtc_lock);
+		return 0;
+
+	case RTC_AIE_ON:
+		spin_lock_irq(&rtc_lock);
+		writew((readw(ioaddr + RTC_RTCIENR) | RTC_ALM_BIT),
+		       ioaddr + RTC_RTCIENR);
+		spin_unlock_irq(&rtc_lock);
+		return 0;
+
+	case RTC_UIE_OFF:	/* UIE is for the 1Hz interrupt */
+		spin_lock_irq(&rtc_lock);
+		writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_1HZ_BIT),
+		       ioaddr + RTC_RTCIENR);
+		spin_unlock_irq(&rtc_lock);
+		return 0;
+
+	case RTC_UIE_ON:
+		spin_lock_irq(&rtc_lock);
+		writew((readw(ioaddr + RTC_RTCIENR) | RTC_1HZ_BIT),
+		       ioaddr + RTC_RTCIENR);
+		spin_unlock_irq(&rtc_lock);
+		return 0;
+	}
+	return -ENOIOCTLCMD;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param  tm           contains the RTC time value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	u32 val;
+
+	/* Avoid roll-over from reading the different registers */
+	do {
+		val = get_alarm_or_time(dev, MXC_RTC_TIME);
+	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
+
+	rtc_time_to_tm(val, tm);
+	return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param  tm           the time value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long time;
+	int ret;
+	ret = rtc_tm_to_time(tm, &time);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Avoid roll-over from reading the different registers */
+	do {
+		set_alarm_or_time(dev, MXC_RTC_TIME, time);
+	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
+
+	return ret;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param  alrm         contains the RTC alarm value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
+	alrm->pending =
+	    ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT) != 0) ? 1 : 0;
+
+	return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param  alrm         the alarm value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	int ret;
+
+	spin_lock_irq(&rtc_lock);
+	if (rtc_valid_tm(&alrm->time)) {
+		if (alrm->time.tm_sec > 59 ||
+		    alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+			ret = -EINVAL;
+			goto out;
+		}
+		ret = rtc_update_alarm(dev, &alrm->time);
+	} else {
+		if ((ret = rtc_valid_tm(&alrm->time)))
+			goto out;
+		ret = rtc_update_alarm(dev, &alrm->time);
+	}
+
+	if (ret == 0) {
+		memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
+
+		if (alrm->enabled) {
+			writew((readw(ioaddr + RTC_RTCIENR) | RTC_ALM_BIT),
+			       ioaddr + RTC_RTCIENR);
+		} else {
+			writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_ALM_BIT),
+			       ioaddr + RTC_RTCIENR);
+		}
+	}
+      out:
+	spin_unlock_irq(&rtc_lock);
+
+	return ret;
+}
+
+/*!
+ * This function is used to provide the content for the /proc/driver/rtc
+ * file.
+ *
+ * @param  buf          the buffer to hold the information that the driver wants to write
+ *
+ * @return  The number of bytes written into the rtc file.
+ */
+static int mxc_rtc_proc(struct device *dev, struct seq_file *sq)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	char *p = sq->buf;
+
+	p += sprintf(p, "alarm_IRQ\t: %s\n",
+		     (((readw(ioaddr + RTC_RTCIENR)) & RTC_ALM_BIT) !=
+		      0) ? "yes" : "no");
+	p += sprintf(p, "update_IRQ\t: %s\n",
+		     (((readw(ioaddr + RTC_RTCIENR)) & RTC_1HZ_BIT) !=
+		      0) ? "yes" : "no");
+	p += sprintf(p, "periodic_IRQ\t: %s\n",
+		     (((readw(ioaddr + RTC_RTCIENR)) & PIT_ALL_ON) !=
+		      0) ? "yes" : "no");
+	p += sprintf(p, "periodic_freq\t: %d\n", rtc_freq);
+
+	return p - (sq->buf);
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops mxc_rtc_ops = {
+	.open = mxc_rtc_open,
+	.release = mxc_rtc_release,
+	.ioctl = mxc_rtc_ioctl,
+	.read_time = mxc_rtc_read_time,
+	.set_time = mxc_rtc_set_time,
+	.read_alarm = mxc_rtc_read_alarm,
+	.set_alarm = mxc_rtc_set_alarm,
+	.proc = mxc_rtc_proc,
+};
+
+/*! MXC RTC Power management control */
+
+static struct timespec mxc_rtc_delta;
+
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+	struct clk *clk;
+	struct timespec tv;
+	struct resource *res;
+	struct rtc_device *rtc;
+	struct rtc_plat_data *pdata = NULL;
+	u32 reg;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->clk = clk_get(&pdev->dev, "rtc_clk");
+	clk_enable(pdata->clk);
+
+	pdata->baseaddr = res->start;
+	pdata->ioaddr = ((void *)(IO_ADDRESS(pdata->baseaddr)));
+	/* Configure and enable the RTC */
+	pdata->irq = platform_get_irq(pdev, 0);
+	if (pdata->irq >= 0) {
+		if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED,
+				pdev->name, pdev) < 0) {
+			dev_warn(&pdev->dev, "interrupt not available.\n");
+			pdata->irq = -1;
+		}
+	}
+	rtc =
+	    rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops,
+				THIS_MODULE);
+	if (IS_ERR(rtc)) {
+		ret = PTR_ERR(rtc);
+		if (pdata->irq >= 0)
+			free_irq(pdata->irq, pdev);
+		kfree(pdata);
+		return ret;
+	}
+	pdata->rtc = rtc;
+	platform_set_drvdata(pdev, pdata);
+	tv.tv_nsec = 0;
+	tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME);
+	clk = clk_get(NULL, "ckil");
+	if (clk_get_rate(clk) == 32768)
+		reg = RTC_INPUT_CLK_32768HZ;
+	else if (clk_get_rate(clk) == 32000)
+		reg = RTC_INPUT_CLK_32000HZ;
+	else if (clk_get_rate(clk) == 38400)
+		reg = RTC_INPUT_CLK_38400HZ;
+	else {
+		printk(KERN_ALERT "rtc clock is not valid");
+		return -EINVAL;
+	}
+	clk_put(clk);
+	reg |= RTC_ENABLE_BIT;
+	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
+	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
+		printk(KERN_ALERT "rtc : hardware module can't be enabled!\n");
+		return -EPERM;
+	}
+	printk("Real TIme clock Driver v%s \n", RTC_VERSION);
+	return ret;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
+	rtc_device_unregister(pdata->rtc);
+	if (pdata->irq >= 0) {
+		free_irq(pdata->irq, pdev);
+	}
+	clk_disable(pdata->clk);
+	clk_put(pdata->clk);
+	kfree(pdata);
+	mxc_rtc_release(NULL);
+	return 0;
+}
+
+/*!
+ * This function is called to save the system time delta relative to
+ * the MXC RTC when enterring a low power state. This time delta is
+ * then used on resume to adjust the system time to account for time
+ * loss while suspended.
+ *
+ * @param   pdev  not used
+ * @param   state Power state to enter.
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct timespec tv;
+
+	/* calculate time delta for suspend */
+	/* RTC precision is 1 second; adjust delta for avg 1/2 sec err */
+	tv.tv_nsec = NSEC_PER_SEC >> 1;
+	tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME);
+	set_normalized_timespec(&mxc_rtc_delta,
+				xtime.tv_sec - tv.tv_sec,
+				xtime.tv_nsec - tv.tv_nsec);
+
+	return 0;
+}
+
+/*!
+ * This function is called to correct the system time based on the
+ * current MXC RTC time relative to the time delta saved during
+ * suspend.
+ *
+ * @param   pdev  not used
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_resume(struct platform_device *pdev)
+{
+	struct timespec tv;
+	struct timespec ts;
+
+	tv.tv_nsec = 0;
+	tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME);
+
+	/* restore wall clock using delta against this RTC;
+	 * adjust again for avg 1/2 second RTC sampling error
+	 */
+	set_normalized_timespec(&ts,
+				tv.tv_sec + mxc_rtc_delta.tv_sec,
+				(NSEC_PER_SEC >> 1) + mxc_rtc_delta.tv_nsec);
+	do_settimeofday(&ts);
+
+	return 0;
+}
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_rtc_driver = {
+	.driver = {
+		   .name = "mxc_rtc",
+		   },
+	.probe = mxc_rtc_probe,
+	.remove = __exit_p(mxc_rtc_remove),
+	.suspend = mxc_rtc_suspend,
+	.resume = mxc_rtc_resume,
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return  -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init mxc_rtc_init(void)
+{
+	return platform_driver_register(&mxc_rtc_driver);
+}
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit mxc_rtc_exit(void)
+{
+	platform_driver_unregister(&mxc_rtc_driver);
+
+}
+
+device_initcall_sync(mxc_rtc_init);
+module_exit(mxc_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 000000000000..beb31415a4da
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,767 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Implementation based on rtc-ds1553.c
+ */
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc_v2.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <linux/mxc_srtc.h>
+
+
+#define SRTC_LPSCLR_LLPSC_LSH	17	 /* start bit for LSB time value */
+
+#define SRTC_LPPDR_INIT       0x41736166	/* init for glitch detect */
+
+#define SRTC_LPCR_SWR_LP      (1 << 0)	/* lp software reset */
+#define SRTC_LPCR_EN_LP       (1 << 3)	/* lp enable */
+#define SRTC_LPCR_WAE         (1 << 4)	/* lp wakeup alarm enable */
+#define SRTC_LPCR_SAE         (1 << 5)	/* lp security alarm enable */
+#define SRTC_LPCR_SI          (1 << 6)	/* lp security interrupt enable */
+#define SRTC_LPCR_ALP         (1 << 7)	/* lp alarm flag */
+#define SRTC_LPCR_LTC         (1 << 8)	/* lp lock time counter */
+#define SRTC_LPCR_LMC         (1 << 9)	/* lp lock monotonic counter */
+#define SRTC_LPCR_SV          (1 << 10)	/* lp security violation */
+#define SRTC_LPCR_NSA         (1 << 11)	/* lp non secure access */
+#define SRTC_LPCR_NVEIE       (1 << 12)	/* lp non valid state exit int en */
+#define SRTC_LPCR_IEIE        (1 << 13)	/* lp init state exit int enable */
+#define SRTC_LPCR_NVE         (1 << 14)	/* lp non valid state exit bit */
+#define SRTC_LPCR_IE          (1 << 15)	/* lp init state exit bit */
+
+#define SRTC_LPCR_ALL_INT_EN (SRTC_LPCR_WAE | SRTC_LPCR_SAE | \
+			      SRTC_LPCR_SI | SRTC_LPCR_ALP | \
+			      SRTC_LPCR_NVEIE | SRTC_LPCR_IEIE)
+
+#define SRTC_LPSR_TRI         (1 << 0)	/* lp time read invalidate */
+#define SRTC_LPSR_PGD         (1 << 1)	/* lp power supply glitc detected */
+#define SRTC_LPSR_CTD         (1 << 2)	/* lp clock tampering detected */
+#define SRTC_LPSR_ALP         (1 << 3)	/* lp alarm flag */
+#define SRTC_LPSR_MR          (1 << 4)	/* lp monotonic counter rollover */
+#define SRTC_LPSR_TR          (1 << 5)	/* lp time rollover */
+#define SRTC_LPSR_EAD         (1 << 6)	/* lp external alarm detected */
+#define SRTC_LPSR_IT0         (1 << 7)	/* lp IIM throttle */
+#define SRTC_LPSR_IT1         (1 << 8)
+#define SRTC_LPSR_IT2         (1 << 9)
+#define SRTC_LPSR_SM0         (1 << 10)	/* lp security mode */
+#define SRTC_LPSR_SM1         (1 << 11)
+#define SRTC_LPSR_STATE_LP0   (1 << 12)	/* lp state */
+#define SRTC_LPSR_STATE_LP1   (1 << 13)
+#define SRTC_LPSR_NVES        (1 << 14)	/* lp non-valid state exit status */
+#define SRTC_LPSR_IES         (1 << 15)	/* lp init state exit status */
+
+#define MAX_PIE_NUM     15
+#define MAX_PIE_FREQ    32768
+#define MIN_PIE_FREQ	1
+
+#define SRTC_PI0         (1 << 0)
+#define SRTC_PI1         (1 << 1)
+#define SRTC_PI2         (1 << 2)
+#define SRTC_PI3         (1 << 3)
+#define SRTC_PI4         (1 << 4)
+#define SRTC_PI5         (1 << 5)
+#define SRTC_PI6         (1 << 6)
+#define SRTC_PI7         (1 << 7)
+#define SRTC_PI8         (1 << 8)
+#define SRTC_PI9         (1 << 9)
+#define SRTC_PI10        (1 << 10)
+#define SRTC_PI11        (1 << 11)
+#define SRTC_PI12        (1 << 12)
+#define SRTC_PI13        (1 << 13)
+#define SRTC_PI14        (1 << 14)
+#define SRTC_PI15        (1 << 15)
+
+#define PIT_ALL_ON      (SRTC_PI1 | SRTC_PI2 | SRTC_PI3 | \
+			SRTC_PI4 | SRTC_PI5 | SRTC_PI6 | SRTC_PI7 | \
+			SRTC_PI8 | SRTC_PI9 | SRTC_PI10 | SRTC_PI11 | \
+			SRTC_PI12 | SRTC_PI13 | SRTC_PI14 | SRTC_PI15)
+
+#define SRTC_SWR_HP      (1 << 0)	/* hp software reset */
+#define SRTC_EN_HP       (1 << 3)	/* hp enable */
+#define SRTC_TS          (1 << 4)	/* time syncronize hp with lp */
+
+#define SRTC_IE_AHP      (1 << 16)	/* Alarm HP Interrupt Enable bit */
+#define SRTC_IE_WDHP     (1 << 18)	/* Write Done HP Interrupt Enable bit */
+#define SRTC_IE_WDLP     (1 << 19)	/* Write Done LP Interrupt Enable bit */
+
+#define SRTC_ISR_AHP     (1 << 16)	/* interrupt status: alarm hp */
+#define SRTC_ISR_WDHP    (1 << 18)	/* interrupt status: write done hp */
+#define SRTC_ISR_WDLP    (1 << 19)	/* interrupt status: write done lp */
+#define SRTC_ISR_WPHP    (1 << 20)	/* interrupt status: write pending hp */
+#define SRTC_ISR_WPLP    (1 << 21)	/* interrupt status: write pending lp */
+
+#define SRTC_LPSCMR	0x00	/* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR	0x04	/* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR	0x08	/* LP Secure Alarm Reg */
+#define SRTC_LPSMCR	0x0C	/* LP Secure Monotonic Counter Reg */
+#define SRTC_LPCR	0x10	/* LP Control Reg */
+#define SRTC_LPSR	0x14	/* LP Status Reg */
+#define SRTC_LPPDR	0x18	/* LP Power Supply Glitch Detector Reg */
+#define SRTC_LPGR	0x1C	/* LP General Purpose Reg */
+#define SRTC_HPCMR	0x20	/* HP Counter MSB Reg */
+#define SRTC_HPCLR	0x24	/* HP Counter LSB Reg */
+#define SRTC_HPAMR	0x28	/* HP Alarm MSB Reg */
+#define SRTC_HPALR	0x2C	/* HP Alarm LSB Reg */
+#define SRTC_HPCR	0x30	/* HP Control Reg */
+#define SRTC_HPISR	0x34	/* HP Interrupt Status Reg */
+#define SRTC_HPIENR	0x38	/* HP Interrupt Enable Reg */
+
+#define SRTC_SECMODE_MASK	0x3	/* the mask of SRTC security mode */
+#define SRTC_SECMODE_LOW	0x0	/* Low Security */
+#define SRTC_SECMODE_MED	0x1	/* Medium Security */
+#define SRTC_SECMODE_HIGH	0x2	/* High Security */
+#define SRTC_SECMODE_RESERVED	0x3	/* Reserved */
+
+struct rtc_drv_data {
+	struct rtc_device *rtc;
+	void __iomem *ioaddr;
+	unsigned long baseaddr;
+	int irq;
+	struct clk *clk;
+	bool irq_enable;
+};
+
+
+/* completion event for implementing RTC_WAIT_FOR_TIME_SET ioctl */
+DECLARE_COMPLETION(srtc_completion);
+/* global to save difference of 47-bit counter value */
+static int64_t time_diff;
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+static unsigned long rtc_status;
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+/*!
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ */
+static inline void rtc_write_sync_lp(void __iomem *ioaddr)
+{
+	unsigned int i, count;
+	/* Wait for 3 CKIL cycles */
+	for (i = 0; i < 3; i++) {
+		count = __raw_readl(ioaddr + SRTC_LPSCLR);
+		while
+			((__raw_readl(ioaddr + SRTC_LPSCLR)) == count);
+	}
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param  alrm         the new alarm value to be updated in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	struct rtc_time alarm_tm, now_tm;
+	unsigned long now, time;
+	int ret;
+
+	now = __raw_readl(ioaddr + SRTC_LPSCMR);
+	rtc_time_to_tm(now, &now_tm);
+
+	alarm_tm.tm_year = now_tm.tm_year;
+	alarm_tm.tm_mon = now_tm.tm_mon;
+	alarm_tm.tm_mday = now_tm.tm_mday;
+
+	alarm_tm.tm_hour = alrm->tm_hour;
+	alarm_tm.tm_min = alrm->tm_min;
+	alarm_tm.tm_sec = alrm->tm_sec;
+
+	rtc_tm_to_time(&now_tm, &now);
+	rtc_tm_to_time(&alarm_tm, &time);
+
+	if (time < now) {
+		time += 60 * 60 * 24;
+		rtc_time_to_tm(time, &alarm_tm);
+	}
+	ret = rtc_tm_to_time(&alarm_tm, &time);
+
+	__raw_writel(time, ioaddr + SRTC_LPSAR);
+
+	/* clear alarm interrupt status bit */
+	__raw_writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR);
+
+	return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param  irq          RTC IRQ number
+ * @param  dev_id       device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 lp_status, lp_cr;
+	u32 events = 0;
+
+	clk_enable(pdata->clk);
+	lp_status = __raw_readl(ioaddr + SRTC_LPSR);
+	lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+
+	/* update irq data & counter */
+	if (lp_status & SRTC_LPSR_ALP) {
+		if (lp_cr & SRTC_LPCR_ALP)
+			events |= (RTC_AF | RTC_IRQF);
+
+		/* disable further lp alarm interrupts */
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+	}
+
+	/* Update interrupt enables */
+	__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+
+	/* If no interrupts are enabled, turn off interrupts in kernel */
+	if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) {
+		disable_irq_nosync(pdata->irq);
+		pdata->irq_enable = false;
+	}
+
+	/* clear interrupt status */
+	__raw_writel(lp_status, ioaddr + SRTC_LPSR);
+	clk_disable(pdata->clk);
+
+	rtc_update_irq(pdata->rtc, 1, events);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to open the RTC driver.
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_open(struct device *dev)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	clk_enable(pdata->clk);
+
+	if (test_and_set_bit(1, &rtc_status))
+		return -EBUSY;
+	return 0;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void mxc_rtc_release(struct device *dev)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+
+	clk_disable(pdata->clk);
+
+	rtc_status = 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param  cmd          ioctl command as defined in include/linux/rtc.h
+ * @param  arg          value for the ioctl command
+ *
+ * @return  0 if successful or negative value otherwise.
+ */
+static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
+			 unsigned long arg)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long lock_flags = 0;
+	u32 lp_cr;
+	u64 time_47bit;
+	int retVal;
+
+	switch (cmd) {
+	case RTC_AIE_OFF:
+		spin_lock_irqsave(&rtc_lock, lock_flags);
+		lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+		if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0)
+		    && (pdata->irq_enable)) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+		__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+		spin_unlock_irqrestore(&rtc_lock, lock_flags);
+		return 0;
+
+	case RTC_AIE_ON:
+		spin_lock_irqsave(&rtc_lock, lock_flags);
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+		lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+		lp_cr |= SRTC_LPCR_ALP | SRTC_LPCR_WAE;
+		__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+		spin_unlock_irqrestore(&rtc_lock, lock_flags);
+		return 0;
+
+	case RTC_READ_TIME_47BIT:
+		time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+		time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+		if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64)))
+			return -EFAULT;
+
+		return 0;
+
+	case RTC_WAIT_TIME_SET:
+
+		/* don't block without releasing mutex first */
+		mutex_unlock(&pdata->rtc->ops_lock);
+
+		/* sleep until awakened by SRTC driver when LPSCMR is changed */
+		wait_for_completion(&srtc_completion);
+
+		/* relock mutex because rtc_dev_ioctl will unlock again */
+		retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock);
+
+		/* copy the new time difference = new time - previous time
+		  * to the user param. The difference is a signed value */
+		if (arg && copy_to_user((int64_t *) arg, &time_diff,
+			sizeof(int64_t)))
+			return -EFAULT;
+
+		return retVal;
+
+	}
+
+	return -ENOIOCTLCMD;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param  tm           contains the RTC time value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSCMR), tm);
+	return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param  tm           the time value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long time;
+	u64 old_time_47bit, new_time_47bit;
+	int ret;
+	ret = rtc_tm_to_time(tm, &time);
+	if (ret != 0)
+		return ret;
+
+	old_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	old_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+	__raw_writel(time, ioaddr + SRTC_LPSCMR);
+	rtc_write_sync_lp(ioaddr);
+
+	new_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	new_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+	/* update the difference between previous time and new time */
+	time_diff = new_time_47bit - old_time_47bit;
+
+	/* signal all waiting threads that time changed */
+	complete_all(&srtc_completion);
+	/* reinitialize completion variable */
+	INIT_COMPLETION(srtc_completion);
+
+	return 0;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param  alrm         contains the RTC alarm value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSAR), &alrm->time);
+	alrm->pending =
+	    ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP) != 0) ? 1 : 0;
+
+	return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param  alrm         the alarm value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long lock_flags = 0;
+	u32 lp_cr;
+	int ret;
+
+	if (rtc_valid_tm(&alrm->time)) {
+		if (alrm->time.tm_sec > 59 ||
+		    alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+			return -EINVAL;
+		}
+	}
+
+	spin_lock_irqsave(&rtc_lock, lock_flags);
+	lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+
+	ret = rtc_update_alarm(dev, &alrm->time);
+	if (ret)
+		goto out;
+
+	if (alrm->enabled)
+		lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+	else
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+	if (lp_cr & SRTC_LPCR_ALL_INT_EN) {
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+	} else {
+		if (pdata->irq_enable) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+
+out:
+	spin_unlock_irqrestore(&rtc_lock, lock_flags);
+	rtc_write_sync_lp(ioaddr);
+	return ret;
+}
+
+/*!
+ * This function is used to provide the content for the /proc/driver/rtc
+ * file.
+ *
+ * @param  seq  buffer to hold the information that the driver wants to write
+ *
+ * @return  The number of bytes written into the rtc file.
+ */
+static int mxc_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	clk_enable(pdata->clk);
+	seq_printf(seq, "alarm_IRQ\t: %s\n",
+		   (((__raw_readl(ioaddr + SRTC_LPCR)) & SRTC_LPCR_ALP) !=
+		    0) ? "yes" : "no");
+	clk_disable(pdata->clk);
+
+	return 0;
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops mxc_rtc_ops = {
+	.open = mxc_rtc_open,
+	.release = mxc_rtc_release,
+	.ioctl = mxc_rtc_ioctl,
+	.read_time = mxc_rtc_read_time,
+	.set_time = mxc_rtc_set_time,
+	.read_alarm = mxc_rtc_read_alarm,
+	.set_alarm = mxc_rtc_set_alarm,
+	.proc = mxc_rtc_proc,
+};
+
+/*! MXC RTC Power management control */
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+	struct clk *clk;
+	struct timespec tv;
+	struct resource *res;
+	struct rtc_device *rtc;
+	struct rtc_drv_data *pdata = NULL;
+	struct mxc_srtc_platform_data *plat_data = NULL;
+	void __iomem *ioaddr;
+	void __iomem *srtc_secmode_addr;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->clk = clk_get(&pdev->dev, "rtc_clk");
+	clk_enable(pdata->clk);
+	pdata->baseaddr = res->start;
+	pdata->ioaddr = ioremap(pdata->baseaddr, 0x40);
+	ioaddr = pdata->ioaddr;
+
+	/* Configure and enable the RTC */
+	pdata->irq = platform_get_irq(pdev, 0);
+	if (pdata->irq >= 0) {
+		if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED,
+				pdev->name, pdev) < 0) {
+			dev_warn(&pdev->dev, "interrupt not available.\n");
+			pdata->irq = -1;
+		} else {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	clk = clk_get(NULL, "rtc_clk");
+	if (clk_get_rate(clk) != 32768) {
+		printk(KERN_ALERT "rtc clock is not valid");
+		ret = -EINVAL;
+		clk_put(clk);
+		goto err_out;
+	}
+	clk_put(clk);
+
+	/* initialize glitch detect */
+	__raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+	udelay(100);
+
+	/* clear lp interrupt status */
+	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+	udelay(100);
+
+	plat_data = (struct mxc_srtc_platform_data *)pdev->dev.platform_data;
+
+	/* move out of init state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA),
+		     ioaddr + SRTC_LPCR);
+
+	udelay(100);
+
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0)
+		;
+
+	/* move out of non-valid state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+		      SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+
+	udelay(100);
+
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0)
+		;
+
+	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+	udelay(100);
+
+	rtc = rtc_device_register(pdev->name, &pdev->dev,
+				  &mxc_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc)) {
+		ret = PTR_ERR(rtc);
+		goto err_out;
+	}
+
+	pdata->rtc = rtc;
+	platform_set_drvdata(pdev, pdata);
+
+	tv.tv_nsec = 0;
+	tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR);
+
+	/* By default, devices should wakeup if they can */
+	/* So srtc is set as "should wakeup" as it can */
+	device_init_wakeup(&pdev->dev, 1);
+
+	clk_disable(pdata->clk);
+
+	return ret;
+
+err_out:
+	clk_disable(pdata->clk);
+	iounmap(ioaddr);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+	kfree(pdata);
+	return ret;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	rtc_device_unregister(pdata->rtc);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+
+	clk_disable(pdata->clk);
+	clk_put(pdata->clk);
+	kfree(pdata);
+	return 0;
+}
+
+/*!
+ * This function is called to save the system time delta relative to
+ * the MXC RTC when enterring a low power state. This time delta is
+ * then used on resume to adjust the system time to account for time
+ * loss while suspended.
+ *
+ * @param   pdev  not used
+ * @param   state Power state to enter.
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		enable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			disable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is called to correct the system time based on the
+ * current MXC RTC time relative to the time delta saved during
+ * suspend.
+ *
+ * @param   pdev  not used
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_resume(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			enable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_rtc_driver = {
+	.driver = {
+		   .name = "mxc_rtc",
+		   },
+	.probe = mxc_rtc_probe,
+	.remove = __exit_p(mxc_rtc_remove),
+	.suspend = mxc_rtc_suspend,
+	.resume = mxc_rtc_resume,
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return  -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init mxc_rtc_init(void)
+{
+	return platform_driver_register(&mxc_rtc_driver);
+}
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit mxc_rtc_exit(void)
+{
+	platform_driver_unregister(&mxc_rtc_driver);
+
+}
+
+module_init(mxc_rtc_init);
+module_exit(mxc_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-mxs.c b/drivers/rtc/rtc-mxs.c
new file mode 100644
index 000000000000..bb4c33b1a0ba
--- /dev/null
+++ b/drivers/rtc/rtc-mxs.c
@@ -0,0 +1,321 @@
+/*
+ * Freescale STMP37XX/STMP378X Real Time Clock driver
+ *
+ * Copyright (c) 2007 Sigmatel, Inc.
+ * Peter Hartley, <peter.hartley@sigmatel.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/uaccess.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-rtc.h>
+
+struct mxs_rtc_data {
+	struct rtc_device *rtc;
+	unsigned int base;
+	int irq_alarm;
+	int irq_sample;
+	unsigned irq_count;
+};
+
+/* Time read/write */
+static int mxs_rtc_gettime(struct device *pdev, struct rtc_time *rtc_tm)
+{
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	while (__raw_readl(rtc_data->base + HW_RTC_STAT) &
+			   BF_RTC_STAT_STALE_REGS(0x80))
+		cpu_relax();
+
+	rtc_time_to_tm(__raw_readl(rtc_data->base + HW_RTC_SECONDS), rtc_tm);
+	return 0;
+}
+
+static int mxs_rtc_settime(struct device *pdev, struct rtc_time *rtc_tm)
+{
+	unsigned long t;
+	int rc = rtc_tm_to_time(rtc_tm, &t);
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	if (rc == 0) {
+		__raw_writel(t, rtc_data->base + HW_RTC_SECONDS);
+
+		/* The datasheet doesn't say which way round the
+		 * NEW_REGS/STALE_REGS bitfields go. In fact it's 0x1=P0,
+		 * 0x2=P1, .., 0x20=P5, 0x40=ALARM, 0x80=SECONDS,
+		 */
+		while (__raw_readl(rtc_data->base + HW_RTC_STAT) &
+				   BF_RTC_STAT_NEW_REGS(0x80))
+			cpu_relax();
+	}
+	return rc;
+}
+
+static irqreturn_t mxs_rtc_interrupt(int irq, void *dev_id)
+{
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(dev_id);
+	u32 status;
+	u32 events = 0;
+
+	status = __raw_readl(rtc_data->base + HW_RTC_CTRL) &
+			(BM_RTC_CTRL_ALARM_IRQ | BM_RTC_CTRL_ONEMSEC_IRQ);
+	if (status & BM_RTC_CTRL_ALARM_IRQ) {
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ,
+			rtc_data->base + HW_RTC_CTRL_CLR);
+		events |= RTC_AF | RTC_IRQF;
+	}
+	if (status & BM_RTC_CTRL_ONEMSEC_IRQ) {
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ,
+			rtc_data->base + HW_RTC_CTRL_CLR);
+		if (++rtc_data->irq_count % 1000 == 0) {
+			events |= RTC_UF | RTC_IRQF;
+			rtc_data->irq_count = 0;
+		}
+	}
+
+	if (events)
+		rtc_update_irq(rtc_data->rtc, 1, events);
+
+	return IRQ_HANDLED;
+}
+
+static int mxs_rtc_open(struct device *pdev)
+{
+	int r;
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	r = request_irq(rtc_data->irq_alarm, mxs_rtc_interrupt,
+			IRQF_DISABLED, "RTC alarm", pdev);
+	if (r) {
+		dev_err(pdev, "Cannot claim IRQ%d\n", rtc_data->irq_alarm);
+		goto fail_1;
+	}
+	r = request_irq(rtc_data->irq_sample, mxs_rtc_interrupt,
+			IRQF_DISABLED, "RTC tick", pdev);
+	if (r) {
+		dev_err(pdev, "Cannot claim IRQ%d\n", rtc_data->irq_sample);
+		goto fail_2;
+	}
+
+	return 0;
+fail_2:
+	free_irq(rtc_data->irq_alarm, pdev);
+fail_1:
+	return r;
+}
+
+static void mxs_rtc_release(struct device *pdev)
+{
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN | BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+		rtc_data->base + HW_RTC_CTRL_CLR);
+	free_irq(rtc_data->irq_alarm, pdev);
+	free_irq(rtc_data->irq_sample, pdev);
+}
+
+static int mxs_rtc_ioctl(struct device *pdev, unsigned int cmd,
+			      unsigned long arg)
+{
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	switch (cmd) {
+	case RTC_AIE_OFF:
+		__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+				BM_RTC_PERSISTENT0_ALARM_WAKE_EN,
+				rtc_data->base + HW_RTC_PERSISTENT0_CLR);
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN,
+				rtc_data->base + HW_RTC_CTRL_CLR);
+		break;
+	case RTC_AIE_ON:
+		__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+				BM_RTC_PERSISTENT0_ALARM_WAKE_EN,
+				rtc_data->base + HW_RTC_PERSISTENT0_SET);
+
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN,
+				rtc_data->base + HW_RTC_CTRL_SET);
+		break;
+	case RTC_UIE_ON:
+		rtc_data->irq_count = 0;
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+			rtc_data->base + HW_RTC_CTRL_SET);
+		break;
+	case RTC_UIE_OFF:
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+			rtc_data->base + HW_RTC_CTRL_CLR);
+		break;
+	default:
+		return -ENOIOCTLCMD;
+	}
+
+	return 0;
+}
+static int mxs_rtc_read_alarm(struct device *pdev, struct rtc_wkalrm *alm)
+{
+	u32 t;
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	t = __raw_readl(rtc_data->base + HW_RTC_ALARM);
+	rtc_time_to_tm(t, &alm->time);
+	return 0;
+}
+
+static int mxs_rtc_set_alarm(struct device *pdev, struct rtc_wkalrm *alm)
+{
+	unsigned long t;
+	struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev);
+
+	rtc_tm_to_time(&alm->time, &t);
+	__raw_writel(t, rtc_data->base + HW_RTC_ALARM);
+	return 0;
+}
+
+static struct rtc_class_ops mxs_rtc_ops = {
+	.open		= mxs_rtc_open,
+	.release	= mxs_rtc_release,
+	.ioctl          = mxs_rtc_ioctl,
+	.read_time	= mxs_rtc_gettime,
+	.set_time	= mxs_rtc_settime,
+	.read_alarm	= mxs_rtc_read_alarm,
+	.set_alarm	= mxs_rtc_set_alarm,
+};
+
+static int mxs_rtc_probe(struct platform_device *pdev)
+{
+	u32 hwversion;
+	u32 rtc_stat;
+	struct resource *res;
+	struct mxs_rtc_data *rtc_data;
+
+	rtc_data = kzalloc(sizeof(*rtc_data), GFP_KERNEL);
+
+	if (!rtc_data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		kfree(rtc_data);
+		return -ENODEV;
+	}
+	rtc_data->base = (unsigned int)IO_ADDRESS(res->start);
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		kfree(rtc_data);
+		return -ENODEV;
+	}
+	rtc_data->irq_alarm = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (res == NULL) {
+		kfree(rtc_data);
+		return -ENODEV;
+	}
+	rtc_data->irq_sample = res->start;
+
+	__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE,
+		     rtc_data->base + HW_RTC_PERSISTENT0_CLR);
+
+	hwversion = __raw_readl(rtc_data->base + HW_RTC_VERSION);
+	rtc_stat = __raw_readl(rtc_data->base + HW_RTC_STAT);
+	printk(KERN_INFO "MXS RTC driver v1.0 hardware v%u.%u.%u\n",
+	       (hwversion >> 24),
+	       (hwversion >> 16) & 0xFF,
+	       hwversion & 0xFFFF);
+
+	rtc_data->rtc = rtc_device_register(pdev->name, &pdev->dev,
+				&mxs_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc_data->rtc)) {
+		kfree(rtc_data);
+		return PTR_ERR(rtc_data->rtc);
+	}
+
+	platform_set_drvdata(pdev, rtc_data);
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	return 0;
+}
+
+static int mxs_rtc_remove(struct platform_device *dev)
+{
+	struct mxs_rtc_data *rtc_data = platform_get_drvdata(dev);
+
+	if (rtc_data) {
+		rtc_device_unregister(rtc_data->rtc);
+		kfree(rtc_data);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_rtc_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int mxs_rtc_resume(struct platform_device *dev)
+{
+	struct mxs_rtc_data *rtc_data = platform_get_drvdata(dev);
+
+	__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE,
+		     rtc_data->base + HW_RTC_PERSISTENT0_CLR);
+	return 0;
+}
+#else
+#define mxs_rtc_suspend	NULL
+#define mxs_rtc_resume	NULL
+#endif
+
+static struct platform_driver mxs_rtcdrv = {
+	.probe		= mxs_rtc_probe,
+	.remove		= mxs_rtc_remove,
+	.suspend	= mxs_rtc_suspend,
+	.resume		= mxs_rtc_resume,
+	.driver		= {
+		.name	= "mxs-rtc",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init mxs_rtc_init(void)
+{
+	return platform_driver_register(&mxs_rtcdrv);
+}
+
+static void __exit mxs_rtc_exit(void)
+{
+	platform_driver_unregister(&mxs_rtcdrv);
+}
+
+module_init(mxs_rtc_init);
+module_exit(mxs_rtc_exit);
+
+MODULE_DESCRIPTION("MXS RTC Driver");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
new file mode 100644
index 000000000000..f3d06b204a55
--- /dev/null
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -0,0 +1,292 @@
+/*
+ * Freescale STMP37XX/STMP378X Real Time Clock driver
+ *
+ * Copyright (c) 2007 Sigmatel, Inc.
+ * Peter Hartley, <peter.hartley@sigmatel.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/uaccess.h>
+
+#include <mach/stmp3xxx.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <mach/regs-rtc.h>
+
+struct stmp3xxx_rtc_data {
+	struct rtc_device *rtc;
+	unsigned irq_count;
+};
+
+/* Time read/write */
+static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
+{
+	while (__raw_readl(REGS_RTC_BASE + HW_RTC_STAT) & BF(0x80, RTC_STAT_STALE_REGS))
+		cpu_relax();
+
+	rtc_time_to_tm(__raw_readl(REGS_RTC_BASE + HW_RTC_SECONDS), rtc_tm);
+	return 0;
+}
+
+static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
+{
+	unsigned long t;
+	int rc = rtc_tm_to_time(rtc_tm, &t);
+
+	if (rc == 0) {
+		__raw_writel(t, REGS_RTC_BASE + HW_RTC_SECONDS);
+
+		/* The datasheet doesn't say which way round the
+		 * NEW_REGS/STALE_REGS bitfields go. In fact it's 0x1=P0,
+		 * 0x2=P1, .., 0x20=P5, 0x40=ALARM, 0x80=SECONDS,
+		 */
+		while (__raw_readl(REGS_RTC_BASE + HW_RTC_STAT) & BF(0x80, RTC_STAT_NEW_REGS))
+			cpu_relax();
+	}
+	return rc;
+}
+
+static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = to_platform_device(dev_id);
+	struct stmp3xxx_rtc_data *data = platform_get_drvdata(pdev);
+	u32 status;
+	u32 events = 0;
+
+	status = __raw_readl(REGS_RTC_BASE + HW_RTC_CTRL) &
+			(BM_RTC_CTRL_ALARM_IRQ | BM_RTC_CTRL_ONEMSEC_IRQ);
+	if (status & BM_RTC_CTRL_ALARM_IRQ) {
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ,
+			REGS_RTC_BASE + HW_RTC_CTRL_CLR);
+		events |= RTC_AF | RTC_IRQF;
+	}
+	if (status & BM_RTC_CTRL_ONEMSEC_IRQ) {
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ,
+			REGS_RTC_BASE + HW_RTC_CTRL_CLR);
+		if (++data->irq_count % 1000 == 0) {
+			events |= RTC_UF | RTC_IRQF;
+			data->irq_count = 0;
+		}
+	}
+
+	if (events)
+		rtc_update_irq(data->rtc, 1, events);
+
+	return IRQ_HANDLED;
+}
+
+static int stmp3xxx_rtc_open(struct device *dev)
+{
+	int r;
+
+	r = request_irq(IRQ_RTC_ALARM, stmp3xxx_rtc_interrupt,
+			IRQF_DISABLED, "RTC alarm", dev);
+	if (r) {
+		dev_err(dev, "Cannot claim IRQ%d\n", IRQ_RTC_ALARM);
+		goto fail_1;
+	}
+	r = request_irq(IRQ_RTC_1MSEC, stmp3xxx_rtc_interrupt,
+			IRQF_DISABLED, "RTC tick", dev);
+	if (r) {
+		dev_err(dev, "Cannot claim IRQ%d\n", IRQ_RTC_1MSEC);
+		goto fail_2;
+	}
+
+	return 0;
+fail_2:
+	free_irq(IRQ_RTC_ALARM, dev);
+fail_1:
+	return r;
+}
+
+static void stmp3xxx_rtc_release(struct device *dev)
+{
+	__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN | BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+		REGS_RTC_BASE + HW_RTC_CTRL_CLR);
+	free_irq(IRQ_RTC_ALARM, dev);
+	free_irq(IRQ_RTC_1MSEC, dev);
+}
+
+static int stmp3xxx_rtc_ioctl(struct device *dev, unsigned int cmd,
+			      unsigned long arg)
+{
+	struct stmp3xxx_rtc_data *data = dev_get_drvdata(dev);
+
+	switch (cmd) {
+	case RTC_AIE_OFF:
+		__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+				BM_RTC_PERSISTENT0_ALARM_WAKE_EN,
+				REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR);
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN,
+				REGS_RTC_BASE + HW_RTC_CTRL_CLR);
+		break;
+	case RTC_AIE_ON:
+		__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+				BM_RTC_PERSISTENT0_ALARM_WAKE_EN,
+				REGS_RTC_BASE + HW_RTC_PERSISTENT0_SET);
+
+		__raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN,
+				REGS_RTC_BASE + HW_RTC_CTRL_SET);
+		break;
+	case RTC_UIE_ON:
+		data->irq_count = 0;
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+			REGS_RTC_BASE + HW_RTC_CTRL_SET);
+		break;
+	case RTC_UIE_OFF:
+		__raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN,
+			REGS_RTC_BASE + HW_RTC_CTRL_CLR);
+		break;
+	default:
+		return -ENOIOCTLCMD;
+	}
+
+	return 0;
+}
+static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	u32 t = __raw_readl(REGS_RTC_BASE + HW_RTC_ALARM);
+
+	rtc_time_to_tm(t, &alm->time);
+
+	return 0;
+}
+
+static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	unsigned long t;
+
+	rtc_tm_to_time(&alm->time, &t);
+	__raw_writel(t, REGS_RTC_BASE + HW_RTC_ALARM);
+	return 0;
+}
+
+static struct rtc_class_ops stmp3xxx_rtc_ops = {
+	.open		= stmp3xxx_rtc_open,
+	.release	= stmp3xxx_rtc_release,
+	.ioctl          = stmp3xxx_rtc_ioctl,
+	.read_time	= stmp3xxx_rtc_gettime,
+	.set_time	= stmp3xxx_rtc_settime,
+	.read_alarm	= stmp3xxx_rtc_read_alarm,
+	.set_alarm	= stmp3xxx_rtc_set_alarm,
+};
+
+static int stmp3xxx_rtc_remove(struct platform_device *dev)
+{
+	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(dev);
+
+	if (rtc_data) {
+		rtc_device_unregister(rtc_data->rtc);
+		kfree(rtc_data);
+	}
+
+	return 0;
+}
+
+static int stmp3xxx_rtc_probe(struct platform_device *pdev)
+{
+	u32 hwversion = __raw_readl(REGS_RTC_BASE + HW_RTC_VERSION);
+	u32 rtc_stat = __raw_readl(REGS_RTC_BASE + HW_RTC_STAT);
+	struct stmp3xxx_rtc_data *rtc_data = kzalloc(sizeof *rtc_data,
+						     GFP_KERNEL);
+
+	if ((rtc_stat & BM_RTC_STAT_RTC_PRESENT) == 0)
+		return -ENODEV;
+	if (!rtc_data)
+		return -ENOMEM;
+
+	stmp3xxx_reset_block(REGS_RTC_BASE, 1);
+
+	__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE,
+		     REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR);
+	__raw_writel(BM_RTC_PERSISTENT0_AUTO_RESTART,
+		     REGS_RTC_BASE + HW_RTC_PERSISTENT0_SET);
+
+	printk(KERN_INFO "STMP3xxx RTC driver v1.0 hardware v%u.%u.%u\n",
+	       (hwversion >> 24),
+	       (hwversion >> 16) & 0xFF,
+	       hwversion & 0xFFFF);
+
+	rtc_data->rtc = rtc_device_register(pdev->name, &pdev->dev,
+				&stmp3xxx_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc_data->rtc)) {
+		kfree(rtc_data);
+		return PTR_ERR(rtc_data->rtc);
+	}
+
+	platform_set_drvdata(pdev, rtc_data);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stmp3xxx_rtc_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int stmp3xxx_rtc_resume(struct platform_device *dev)
+{
+	stmp3xxx_reset_block(REGS_RTC_BASE, 1);
+	__raw_writel(BM_RTC_PERSISTENT0_ALARM_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE_EN |
+			BM_RTC_PERSISTENT0_ALARM_WAKE,
+		     REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR);
+	return 0;
+}
+#else
+#define stmp3xxx_rtc_suspend	NULL
+#define stmp3xxx_rtc_resume	NULL
+#endif
+
+static struct platform_driver stmp3xxx_rtcdrv = {
+	.probe		= stmp3xxx_rtc_probe,
+	.remove		= stmp3xxx_rtc_remove,
+	.suspend	= stmp3xxx_rtc_suspend,
+	.resume		= stmp3xxx_rtc_resume,
+	.driver		= {
+		.name	= "stmp3xxx-rtc",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init stmp3xxx_rtc_init(void)
+{
+	return platform_driver_register(&stmp3xxx_rtcdrv);
+}
+
+static void __exit stmp3xxx_rtc_exit(void)
+{
+	platform_driver_unregister(&stmp3xxx_rtcdrv);
+}
+
+module_init(stmp3xxx_rtc_init);
+module_exit(stmp3xxx_rtc_exit);
+
+MODULE_DESCRIPTION("STMP3xxx RTC Driver");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index fb867a9f55e9..d5da26f34cee 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -942,6 +942,10 @@ static void autoconfig_16550a(struct uart_8250_port *up)
 	 * Check for presence of the EFR when DLAB is set.
 	 * Only ST16C650V1 UARTs pass this test.
 	 */
+#ifndef CONFIG_ARCH_MXC
+	/* This test fails as EFR reads 0, but our uart requires LCR=0xBF
+	 *  to access EFR.
+	 */
 	serial_outp(up, UART_LCR, UART_LCR_DLAB);
 	if (serial_in(up, UART_EFR) == 0) {
 		serial_outp(up, UART_EFR, 0xA8);
@@ -955,6 +959,7 @@ static void autoconfig_16550a(struct uart_8250_port *up)
 		serial_outp(up, UART_EFR, 0);
 		return;
 	}
+#endif
 
 	/*
 	 * Maybe it requires 0xbf to be written to the LCR.
@@ -1477,7 +1482,12 @@ static void transmit_chars(struct uart_8250_port *up)
 
 	count = up->tx_loadsz;
 	do {
+#ifdef CONFIG_ARCH_MXC
+		/* Seems like back-to-back accesses are a problem */
+		serial_out_sync(up, UART_TX, xmit->buf[xmit->tail]);
+#else
 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
+#endif
 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 		up->port.icount.tx++;
 		if (uart_circ_empty(xmit))
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6553833c12db..b41db4d22436 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -304,6 +304,110 @@ config SERIAL_AMBA_PL010_CONSOLE
 	  your boot loader (lilo or loadlin) about how to pass options to the
 	  kernel at boot time.)
 
+config SERIAL_MXC
+    tristate "MXC Internal serial port support"
+    depends on ARCH_MXC
+    select SERIAL_CORE
+    help
+      This selects the Freescale Semiconductor MXC Internal UART driver.
+      If unsure, say N.
+
+config SERIAL_MXC_CONSOLE
+    bool "Support for console on a MXC/MX27/MX21 Internal serial port"
+    depends on SERIAL_MXC=y
+    select SERIAL_CORE_CONSOLE
+    help
+	  Say Y here if you wish to use an MXC Internal UART as the system
+	  console (the system console is the device which receives all kernel
+	  messages and warnings and which allows logins in single user mode).
+
+	  Even if you say Y here, the currently visible framebuffer console
+	  (/dev/tty0) will still be used as the system console by default, but
+	  you can alter that using a kernel command line option such as
+	  "console=ttymxc". (Try "man bootparam" or see the documentation of
+	  your boot loader (lilo or loadlin) about how to pass options to the
+	  kernel at boot time.)
+
+config SERIAL_STMP_DBG
+        tristate "STMP debug serial port support"
+        depends on ARCH_STMP3XXX
+        select SERIAL_CORE
+        help
+          Driver for Sigmatel 36XX/37XX internal debug serial port
+
+config SERIAL_STMP_DBG_CONSOLE
+        bool "Support for console on STMP37XX DBG serial port"
+        depends on SERIAL_STMP_DBG=y
+        select SERIAL_CORE_CONSOLE
+        ---help---
+          Say Y here if you wish to use the STMP36XX/37XX debug serial port as the
+          system console (the system console is the device which receives all
+          kernel messages and warnings and which allows logins in single user
+          mode).
+
+          Even if you say Y here, the currently visible framebuffer console
+          (/dev/tty0) will still be used as the system console by default, but
+          you can alter that using a kernel command line option such as
+          "console=ttyAM0". (Try "man bootparam" or see the documentation of
+          your boot loader (lilo or loadlin) about how to pass options to the
+          kernel at boot time.)
+
+config SERIAL_STMP_APP
+        tristate "STMP app serial port support"
+        depends on ARCH_STMP3XXX
+        select SERIAL_CORE
+        help
+          Driver for Sigmatel 36XX/37XX internal application serial port
+
+config SERIAL_MXS_DUART
+        tristate "i.MXS debug serial port support"
+        depends on ARCH_MXS
+        select SERIAL_CORE
+        help
+          Driver for Freescale i.MXS internal debug serial port
+
+config SERIAL_MXS_AUART
+	tristate "i.MXS Application serial port support"
+	depends on ARCH_MXS
+	select SERIAL_CORE
+	help
+	  Driver for Freescale i.MXS internal application serial port
+
+config SERIAL_MXS_AUART_CONSOLE
+       bool "Support for console on i.MXS application serial port"
+       depends on SERIAL_MXS_AUART=y
+       select SERIAL_CORE_CONSOLE
+       ---help---
+         Say Y here if you wish to use the i.MXS app serial port as the
+         system console (the system console is the device which receives all
+         kernel messages and warnings and which allows logins in single user
+         mode).
+
+         Even if you say Y here, the currently visible framebuffer console
+         (/dev/tty0) will still be used as the system console by default, but
+         you can alter that using a kernel command line option such as
+         "console=ttySP1". (Try "man bootparam" or see the documentation of
+         your boot loader (lilo or loadlin) about how to pass options to the
+         kernel at boot time.)
+
+
+config SERIAL_MXS_DUART_CONSOLE
+        bool "Support for console on i.MXS debug serial port"
+        depends on SERIAL_MXS_DUART=y
+        select SERIAL_CORE_CONSOLE
+        ---help---
+          Say Y here if you wish to use the i.MXS debug serial port as the
+          system console (the system console is the device which receives all
+          kernel messages and warnings and which allows logins in single user
+          mode).
+
+          Even if you say Y here, the currently visible framebuffer console
+          (/dev/tty0) will still be used as the system console by default, but
+          you can alter that using a kernel command line option such as
+          "console=ttyAM0". (Try "man bootparam" or see the documentation of
+          your boot loader (lilo or loadlin) about how to pass options to the
+          kernel at boot time.)
+
 config SERIAL_AMBA_PL011
 	tristate "ARM AMBA PL011 serial port support"
 	depends on ARM_AMBA
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d5a29981c6c4..c18dddb3777d 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -73,6 +73,12 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
 obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
 obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
 obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
+obj-$(CONFIG_SERIAL_MXC) += mxc_uart.o
+obj-$(CONFIG_SERIAL_MXC_CONSOLE) += mxc_uart_early.o
+obj-$(CONFIG_SERIAL_STMP_DBG) += stmp-dbg.o
+obj-$(CONFIG_SERIAL_STMP_APP) += stmp-app.o
+obj-$(CONFIG_SERIAL_MXS_DUART) += mxs-duart.o
+obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
 obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
 obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
 obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
diff --git a/drivers/serial/mxc_uart.c b/drivers/serial/mxc_uart.c
new file mode 100644
index 000000000000..8f2cd0c87dfe
--- /dev/null
+++ b/drivers/serial/mxc_uart.c
@@ -0,0 +1,1976 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/serial/mxc_uart.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC serial ports based on
+ * drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * @ingroup UART
+ */
+
+/*
+ * Include Files
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/console.h>
+#include <linux/platform_device.h>
+#include <linux/sysrq.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <asm/div64.h>
+#include <mach/hardware.h>
+#include <mach/mxc_uart.h>
+
+#if defined(CONFIG_SERIAL_MXC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+#define SERIAL_MXC_MAJOR        207
+#define SERIAL_MXC_MINOR        16
+#define MXC_ISR_PASS_LIMIT      256
+#define UART_CREAD_BIT          256
+
+#define MXC_UART_NR		8
+
+/* IRDA minimum pulse duration in micro seconds */
+#define MIN_PULSE_DUR           2
+/*
+ * Transmit DMA buffer size is set to 1024 bytes, this is limited
+ * by UART_XMIT_SIZE.
+ */
+#define TXDMA_BUFF_SIZE         UART_XMIT_SIZE
+/*
+ * Receive DMA sub-buffer size
+ */
+#define RXDMA_BUFF_SIZE         128
+
+/*!
+ * This structure is used to store the information for DMA data transfer.
+ */
+typedef struct {
+	/*!
+	 * Holds the read channel number.
+	 */
+	int rd_channel;
+	/*!
+	 * Holds the write channel number.
+	 */
+	int wr_channel;
+	/*!
+	 * UART Transmit Event ID
+	 */
+	int tx_event_id;
+	/*!
+	 * UART Receive Event ID
+	 */
+	int rx_event_id;
+	/*!
+	 * DMA Transmit tasklet
+	 */
+	struct tasklet_struct dma_tx_tasklet;
+	/*!
+	 * Flag indicates if the channel is in use
+	 */
+	int dma_txchnl_inuse;
+} dma_info;
+
+/*!
+ * This is used to indicate if we want echo cancellation in the Irda mode.
+ */
+static int echo_cancel;
+extern void gpio_uart_active(int port, int no_irda);
+extern void gpio_uart_inactive(int port, int no_irda);
+extern void config_uartdma_event(int port);
+
+static uart_mxc_port *mxc_ports[MXC_UART_NR];
+
+/*!
+ * This array holds the DMA channel information for each MXC UART
+ */
+static dma_info dma_list[MXC_UART_NR];
+
+/*!
+ * This function is called by the core driver to stop UART transmission.
+ * This might be due to the TTY layer indicating that the user wants to stop
+ * transmission.
+ *
+ * @param   port       the port structure for the UART passed in by the core
+ *                     driver
+ */
+static void mxcuart_stop_tx(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	volatile unsigned int cr1;
+
+	cr1 = readl(port->membase + MXC_UARTUCR1);
+	/* Disable Transmitter rdy interrupt */
+	if (umxc->dma_enabled == 1) {
+		cr1 &= ~MXC_UARTUCR1_TXDMAEN;
+	} else {
+		cr1 &= ~MXC_UARTUCR1_TRDYEN;
+	}
+	writel(cr1, port->membase + MXC_UARTUCR1);
+}
+
+/*!
+ * DMA Transmit tasklet method is scheduled on completion of a DMA transmit
+ * to send out any more data that is available in the UART xmit buffer.
+ *
+ * @param   arg  driver private data
+ */
+static void dma_tx_do_tasklet(unsigned long arg)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) arg;
+	struct circ_buf *xmit = &umxc->port.info->xmit;
+	mxc_dma_requestbuf_t writechnl_request;
+	int tx_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&umxc->port.lock, flags);
+	tx_num = uart_circ_chars_pending(xmit);
+	if (tx_num > 0) {
+		if (xmit->tail > xmit->head) {
+			memcpy(umxc->tx_buf, xmit->buf + xmit->tail,
+			       UART_XMIT_SIZE - xmit->tail);
+			memcpy(umxc->tx_buf + (UART_XMIT_SIZE - xmit->tail),
+			       xmit->buf, xmit->head);
+		} else {
+			memcpy(umxc->tx_buf, xmit->buf + xmit->tail, tx_num);
+		}
+		umxc->tx_handle = dma_map_single(umxc->port.dev, umxc->tx_buf,
+						 TXDMA_BUFF_SIZE,
+						 DMA_TO_DEVICE);
+
+		writechnl_request.dst_addr = umxc->port.mapbase + MXC_UARTUTXD;
+		writechnl_request.src_addr = umxc->tx_handle;
+		writechnl_request.num_of_bytes = tx_num;
+
+		if ((mxc_dma_config(dma_list[umxc->port.line].wr_channel,
+				    &writechnl_request, 1,
+				    MXC_DMA_MODE_WRITE)) == 0) {
+			mxc_dma_enable(dma_list[umxc->port.line].wr_channel);
+		}
+	} else {
+		/* No more data available in the xmit queue, clear the flag */
+		dma_list[umxc->port.line].dma_txchnl_inuse = 0;
+	}
+	spin_unlock_irqrestore(&umxc->port.lock, flags);
+}
+
+/*!
+ * DMA Write callback is called by the SDMA controller after it has sent out all
+ * the data from the user buffer. This function updates the xmit buffer pointers.
+ *
+ * @param   arg   driver private data
+ * @param   error any DMA error
+ * @param   count amount of data that was transferred
+ */
+static void mxcuart_dma_writecallback(void *arg, int error, unsigned int count)
+{
+	uart_mxc_port *umxc = arg;
+	struct circ_buf *xmit = &umxc->port.info->xmit;
+	int tx_num;
+
+	if (error != MXC_DMA_TRANSFER_ERROR) {
+		tx_num = count;
+		umxc->port.icount.tx += tx_num;
+		xmit->tail = (xmit->tail + tx_num) & (UART_XMIT_SIZE - 1);
+	}
+
+	dma_unmap_single(umxc->port.dev, umxc->tx_handle, TXDMA_BUFF_SIZE,
+			 DMA_TO_DEVICE);
+	tx_num = uart_circ_chars_pending(xmit);
+	/* Schedule a tasklet to send out the pending characters */
+	if (tx_num > 0) {
+		tasklet_schedule(&dma_list[umxc->port.line].dma_tx_tasklet);
+	} else {
+		dma_list[umxc->port.line].dma_txchnl_inuse = 0;
+	}
+	if (tx_num < WAKEUP_CHARS) {
+		uart_write_wakeup(&umxc->port);
+	}
+}
+
+/*!
+ * This function is called by the core driver to start transmitting characters.
+ * This function enables the transmit interrupts.
+ *
+ * @param   port       the port structure for the UART passed in by the core
+ *                     driver
+ */
+static void mxcuart_start_tx(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	struct circ_buf *xmit = &umxc->port.info->xmit;
+	volatile unsigned int cr1;
+	mxc_dma_requestbuf_t writechnl_request;
+	int tx_num;
+
+	cr1 = readl(port->membase + MXC_UARTUCR1);
+	/* Enable Transmitter rdy interrupt */
+	if (umxc->dma_enabled == 1) {
+		/*
+		 * If the channel is in use then return immediately and use
+		 * the dma_tx tasklet to transfer queued data when current DMA
+		 * transfer is complete
+		 */
+		if (dma_list[umxc->port.line].dma_txchnl_inuse == 1) {
+			return;
+		}
+		tx_num = uart_circ_chars_pending(xmit);
+		if (tx_num > 0) {
+			dma_list[umxc->port.line].dma_txchnl_inuse = 1;
+			if (xmit->tail > xmit->head) {
+				memcpy(umxc->tx_buf, xmit->buf + xmit->tail,
+				       UART_XMIT_SIZE - xmit->tail);
+				memcpy(umxc->tx_buf +
+				       (UART_XMIT_SIZE - xmit->tail), xmit->buf,
+				       xmit->head);
+			} else {
+				memcpy(umxc->tx_buf, xmit->buf + xmit->tail,
+				       tx_num);
+			}
+			umxc->tx_handle =
+			    dma_map_single(umxc->port.dev, umxc->tx_buf,
+					   TXDMA_BUFF_SIZE, DMA_TO_DEVICE);
+
+			writechnl_request.dst_addr =
+			    umxc->port.mapbase + MXC_UARTUTXD;
+			writechnl_request.src_addr = umxc->tx_handle;
+			writechnl_request.num_of_bytes = tx_num;
+			if ((mxc_dma_config
+			     (dma_list[umxc->port.line].wr_channel,
+			      &writechnl_request, 1,
+			      MXC_DMA_MODE_WRITE)) == 0) {
+				mxc_dma_enable(dma_list[umxc->port.line].
+					       wr_channel);
+			}
+			cr1 |= MXC_UARTUCR1_TXDMAEN;
+		}
+	} else {
+		cr1 |= MXC_UARTUCR1_TRDYEN;
+	}
+	writel(cr1, port->membase + MXC_UARTUCR1);
+}
+
+/*!
+ * This function is called by the core driver to stop receiving characters; the
+ * port is in the process of being closed.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ */
+static void mxcuart_stop_rx(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	volatile unsigned int cr1;
+
+	cr1 = readl(port->membase + MXC_UARTUCR1);
+	if (umxc->dma_enabled == 1) {
+		cr1 &= ~MXC_UARTUCR1_RXDMAEN;
+	} else {
+		cr1 &= ~MXC_UARTUCR1_RRDYEN;
+	}
+	writel(cr1, port->membase + MXC_UARTUCR1);
+}
+
+/*!
+ * This function is called by the core driver to enable the modem status
+ * interrupts. If the port is configured to be in DTE mode then it enables the
+ * DCDDELT and RIDELT interrupts in addition to the DTRDEN interrupt. The RTSDEN
+ * interrupt is enabled only for interrupt-driven hardware flow control.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ */
+static void mxcuart_enable_ms(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	volatile unsigned int cr1, cr3;
+
+	/*
+	 * RTS interrupt is enabled only if we are using interrupt-driven
+	 * software controlled hardware flow control
+	 */
+	if (umxc->hardware_flow == 0) {
+		cr1 = readl(umxc->port.membase + MXC_UARTUCR1);
+		cr1 |= MXC_UARTUCR1_RTSDEN;
+		writel(cr1, umxc->port.membase + MXC_UARTUCR1);
+	}
+	cr3 = readl(umxc->port.membase + MXC_UARTUCR3);
+	cr3 |= MXC_UARTUCR3_DTRDEN;
+	if (umxc->mode == MODE_DTE) {
+		cr3 |= MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI;
+	}
+	writel(cr3, umxc->port.membase + MXC_UARTUCR3);
+}
+
+/*!
+ * This function is called from the interrupt service routine if the status bit
+ * indicates that the receive fifo data level is above the set threshold. The
+ * function reads the character and queues them into the TTY layers read
+ * buffer. The function also looks for break characters, parity and framing
+ * errors in the received character and sets the appropriate flag in the TTY
+ * receive buffer.
+ *
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ */
+static void mxcuart_rx_chars(uart_mxc_port * umxc)
+{
+	volatile unsigned int ch, sr2;
+	unsigned int status, flag, max_count = 256;
+
+	sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+	while (((sr2 & MXC_UARTUSR2_RDR) == 1) && (max_count-- > 0)) {
+		ch = readl(umxc->port.membase + MXC_UARTURXD);
+
+		flag = TTY_NORMAL;
+		status = ch | UART_CREAD_BIT;
+		ch &= 0xFF;	/* Clear the upper bits */
+		umxc->port.icount.rx++;
+
+		/*
+		 * Check to see if there is an  error in the received
+		 * character. Perform the appropriate actions based on the
+		 * error bit that was set.
+		 */
+		if (status & MXC_UARTURXD_ERR) {
+			if (status & MXC_UARTURXD_BRK) {
+				/*
+				 * Clear the frame and parity error bits
+				 * as these always get set on receiving a
+				 * break character
+				 */
+				status &= ~(MXC_UARTURXD_FRMERR |
+					    MXC_UARTURXD_PRERR);
+				umxc->port.icount.brk++;
+				if (uart_handle_break(&umxc->port)) {
+					goto ignore_char;
+				}
+			} else if (status & MXC_UARTURXD_FRMERR) {
+				umxc->port.icount.frame++;
+			} else if (status & MXC_UARTURXD_PRERR) {
+				umxc->port.icount.parity++;
+			}
+			if (status & MXC_UARTURXD_OVRRUN) {
+				umxc->port.icount.overrun++;
+			}
+
+			status &= umxc->port.read_status_mask;
+
+			if (status & MXC_UARTURXD_BRK) {
+				flag = TTY_BREAK;
+			} else if (status & MXC_UARTURXD_FRMERR) {
+				flag = TTY_FRAME;
+			} else if (status & MXC_UARTURXD_PRERR) {
+				flag = TTY_PARITY;
+			}
+		}
+
+		if (uart_handle_sysrq_char(&umxc->port, ch)) {
+			goto ignore_char;
+		}
+
+		uart_insert_char(&umxc->port, status, MXC_UARTURXD_OVRRUN, ch,
+				 flag);
+	      ignore_char:
+		sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+	}
+	tty_flip_buffer_push(umxc->port.info->port.tty);
+}
+
+/*!
+ * This function is called from the interrupt service routine if the status bit
+ * indicates that the transmit fifo is emptied below its set threshold and
+ * requires data. The function pulls characters from the TTY layers write
+ * buffer and writes it out to the UART transmit fifo.
+ *
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ */
+static void mxcuart_tx_chars(uart_mxc_port * umxc)
+{
+	struct circ_buf *xmit = &umxc->port.info->xmit;
+	int count;
+
+	/*
+	 * Transmit the XON/XOFF character if required
+	 */
+	if (umxc->port.x_char) {
+		writel(umxc->port.x_char, umxc->port.membase + MXC_UARTUTXD);
+		umxc->port.icount.tx++;
+		umxc->port.x_char = 0;
+		return;
+	}
+
+	/*
+	 * Check to see if there is any data to be sent and that the
+	 * port has not been currently stopped by anything.
+	 */
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&umxc->port)) {
+		mxcuart_stop_tx(&umxc->port);
+		return;
+	}
+
+	count = umxc->port.fifosize - umxc->tx_threshold;
+	do {
+		writel(xmit->buf[xmit->tail],
+		       umxc->port.membase + MXC_UARTUTXD);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		umxc->port.icount.tx++;
+		if (uart_circ_empty(xmit)) {
+			break;
+		}
+	} while (--count > 0);
+
+	/*
+	 * Check to see if we have flushed enough characters to ask for more
+	 * to be sent to us, if so, we notify the user space that we can
+	 * accept more data
+	 */
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
+		uart_write_wakeup(&umxc->port);
+	}
+
+	if (uart_circ_empty(xmit)) {
+		mxcuart_stop_tx(&umxc->port);
+	}
+}
+
+/*!
+ * This function is called from the interrupt service routine if there is a
+ * change in the modem signals. This function handles these signal changes and
+ * also clears the appropriate status register bits.
+ *
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ * @param   sr1    contents of status register 1
+ * @param   sr2    contents of status register 2
+ */
+static void mxcuart_modem_status(uart_mxc_port * umxc, unsigned int sr1,
+				 unsigned int sr2)
+{
+	if (umxc->mode == MODE_DTE) {
+		if (sr2 & MXC_UARTUSR2_DCDDELT) {
+			uart_handle_dcd_change(&umxc->port,
+					       !(sr2 & MXC_UARTUSR2_DCDIN));
+		}
+		if (sr2 & MXC_UARTUSR2_RIDELT) {
+			umxc->port.icount.rng++;
+		}
+	}
+	if (sr1 & MXC_UARTUSR1_DTRD) {
+		umxc->port.icount.dsr++;
+	}
+	if ((umxc->hardware_flow == 0) && (sr1 & MXC_UARTUSR1_RTSD)) {
+		uart_handle_cts_change(&umxc->port, sr1 & MXC_UARTUSR1_RTSS);
+	}
+
+	wake_up_interruptible(&umxc->port.info->delta_msr_wait);
+}
+
+/*!
+ * Interrupt service routine registered to handle the muxed ANDed interrupts.
+ * This routine is registered only in the case where the UART interrupts are
+ * muxed.
+ *
+ * @param   irq    the interrupt number
+ * @param   dev_id driver private data
+ *
+ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ *          \b IRQ_RETVAL is defined in \b include/linux/interrupt.h.
+ */
+static irqreturn_t mxcuart_int(int irq, void *dev_id)
+{
+	uart_mxc_port *umxc = dev_id;
+	volatile unsigned int sr1, sr2, cr1, cr;
+	unsigned int pass_counter = MXC_ISR_PASS_LIMIT;
+	unsigned int term_cond = 0;
+	int handled = 0;
+
+	sr1 = readl(umxc->port.membase + MXC_UARTUSR1);
+	sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+	cr1 = readl(umxc->port.membase + MXC_UARTUCR1);
+
+	do {
+		/* Clear the bits that triggered the interrupt */
+		writel(sr1, umxc->port.membase + MXC_UARTUSR1);
+		writel(sr2, umxc->port.membase + MXC_UARTUSR2);
+		/*
+		 * Read if there is data available
+		 */
+		if (sr2 & MXC_UARTUSR2_RDR) {
+			mxcuart_rx_chars(umxc);
+		}
+
+		if ((sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD)) ||
+		    (sr2 & (MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT))) {
+			mxcuart_modem_status(umxc, sr1, sr2);
+		}
+
+		/*
+		 * Send data if there is data to be sent
+		 */
+		if ((cr1 & MXC_UARTUCR1_TRDYEN) && (sr1 & MXC_UARTUSR1_TRDY)) {
+			/* Echo cancellation for IRDA Transmit chars */
+			if (umxc->ir_mode == IRDA && echo_cancel) {
+				/* Disable the receiver */
+				cr = readl(umxc->port.membase + MXC_UARTUCR2);
+				cr &= ~MXC_UARTUCR2_RXEN;
+				writel(cr, umxc->port.membase + MXC_UARTUCR2);
+				/* Enable Transmit complete intr to reenable RX */
+				cr = readl(umxc->port.membase + MXC_UARTUCR4);
+				cr |= MXC_UARTUCR4_TCEN;
+				writel(cr, umxc->port.membase + MXC_UARTUCR4);
+			}
+			mxcuart_tx_chars(umxc);
+		}
+
+		if (pass_counter-- == 0) {
+			break;
+		}
+
+		sr1 = readl(umxc->port.membase + MXC_UARTUSR1);
+		sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+
+		/* Is the transmit complete to reenable the receiver? */
+		if (umxc->ir_mode == IRDA && echo_cancel) {
+			if (sr2 & MXC_UARTUSR2_TXDC) {
+				cr = readl(umxc->port.membase + MXC_UARTUCR2);
+				cr |= MXC_UARTUCR2_RXEN;
+				writel(cr, umxc->port.membase + MXC_UARTUCR2);
+				/* Disable the Transmit complete interrupt bit */
+				cr = readl(umxc->port.membase + MXC_UARTUCR4);
+				cr &= ~MXC_UARTUCR4_TCEN;
+				writel(cr, umxc->port.membase + MXC_UARTUCR4);
+			}
+		}
+
+		/*
+		 * If there is no data to send or receive and if there is no
+		 * change in the modem status signals then quit the routine
+		 */
+		term_cond = sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD);
+		term_cond |= sr2 & (MXC_UARTUSR2_RDR | MXC_UARTUSR2_DCDDELT);
+		term_cond |= !(sr2 & MXC_UARTUSR2_TXFE);
+	} while (term_cond > 0);
+
+	handled = 1;
+	return IRQ_RETVAL(handled);
+}
+
+/*!
+ * Interrupt service routine registered to handle the transmit interrupts. This
+ * routine is registered only in the case where the UART interrupts are not
+ * muxed.
+ *
+ * @param   irq    the interrupt number
+ * @param   dev_id driver private data
+ *
+ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ *          \b IRQ_RETVAL is defined in include/linux/interrupt.h.
+ */
+static irqreturn_t mxcuart_tx_int(int irq, void *dev_id)
+{
+	uart_mxc_port *umxc = dev_id;
+	int handled = 0;
+	volatile unsigned int sr2, cr;
+
+	/* Echo cancellation for IRDA Transmit chars */
+	if (umxc->ir_mode == IRDA && echo_cancel) {
+		/* Disable the receiver */
+		cr = readl(umxc->port.membase + MXC_UARTUCR2);
+		cr &= ~MXC_UARTUCR2_RXEN;
+		writel(cr, umxc->port.membase + MXC_UARTUCR2);
+		/* Enable Transmit complete to reenable receiver */
+		cr = readl(umxc->port.membase + MXC_UARTUCR4);
+		cr |= MXC_UARTUCR4_TCEN;
+		writel(cr, umxc->port.membase + MXC_UARTUCR4);
+	}
+
+	mxcuart_tx_chars(umxc);
+
+	/* Is the transmit complete to reenable the receiver? */
+	if (umxc->ir_mode == IRDA && echo_cancel) {
+		sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+		if (sr2 & MXC_UARTUSR2_TXDC) {
+			cr = readl(umxc->port.membase + MXC_UARTUCR2);
+			cr |= MXC_UARTUCR2_RXEN;
+			writel(cr, umxc->port.membase + MXC_UARTUCR2);
+			/* Disable the Transmit complete interrupt bit */
+			cr = readl(umxc->port.membase + MXC_UARTUCR4);
+			cr &= ~MXC_UARTUCR4_TCEN;
+			writel(cr, umxc->port.membase + MXC_UARTUCR4);
+		}
+	}
+
+	handled = 1;
+
+	return IRQ_RETVAL(handled);
+}
+
+/*!
+ * Interrupt service routine registered to handle the receive interrupts. This
+ * routine is registered only in the case where the UART interrupts are not
+ * muxed.
+ *
+ * @param   irq    the interrupt number
+ * @param   dev_id driver private data
+ *
+ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ *          \b IRQ_RETVAL is defined in include/linux/interrupt.h.
+ */
+static irqreturn_t mxcuart_rx_int(int irq, void *dev_id)
+{
+	uart_mxc_port *umxc = dev_id;
+	int handled = 0;
+
+	/* Clear the aging timer bit */
+	writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1);
+	mxcuart_rx_chars(umxc);
+	handled = 1;
+
+	return IRQ_RETVAL(handled);
+}
+
+/*!
+ * Interrupt service routine registered to handle the master interrupts. This
+ * routine is registered only in the case where the UART interrupts are not
+ * muxed.
+ *
+ * @param   irq    the interrupt number
+ * @param   dev_id driver private data
+ *
+ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
+ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
+ *          \b IRQ_RETVAL is defined in include/linux/interrupt.h.
+ */
+static irqreturn_t mxcuart_mint_int(int irq, void *dev_id)
+{
+	uart_mxc_port *umxc = dev_id;
+	int handled = 0;
+	volatile unsigned int sr1, sr2;
+
+	sr1 = readl(umxc->port.membase + MXC_UARTUSR1);
+	sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+	/* Clear the modem status interrupt bits */
+	writel(MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD,
+	       umxc->port.membase + MXC_UARTUSR1);
+	writel(MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT,
+	       umxc->port.membase + MXC_UARTUSR2);
+	mxcuart_modem_status(umxc, sr1, sr2);
+	handled = 1;
+
+	return IRQ_RETVAL(handled);
+}
+
+/*!
+ * This function is called by the core driver to test whether the transmitter
+ * fifo and shift register for the UART port are empty.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ *
+ * @return  The function returns TIOCSER_TEMT if it is empty, else returns 0.
+ */
+static unsigned int mxcuart_tx_empty(struct uart_port *port)
+{
+	volatile unsigned int sr2;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	sr2 = readl(port->membase + MXC_UARTUSR2);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return sr2 & MXC_UARTUSR2_TXDC ? TIOCSER_TEMT : 0;
+}
+
+/*!
+ * This function is called by the core driver to get the current status of the
+ * modem input signals. The state of the output signals is not collected.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ *
+ * @return  The function returns an integer that contains the ORed value of the
+ *          status of all the modem input signals or error.
+ */
+static unsigned int mxcuart_get_mctrl(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	unsigned int result = 0;
+	volatile unsigned int sr1, sr2;
+
+	sr1 = readl(umxc->port.membase + MXC_UARTUSR1);
+	sr2 = readl(umxc->port.membase + MXC_UARTUSR2);
+
+	if (sr1 & MXC_UARTUSR1_RTSS) {
+		result |= TIOCM_CTS;
+	}
+	if (umxc->mode == MODE_DTE) {
+		if (!(sr2 & MXC_UARTUSR2_DCDIN)) {
+			result |= TIOCM_CAR;
+		}
+		if (!(sr2 & MXC_UARTUSR2_RIIN)) {
+			result |= TIOCM_RI;
+		}
+	}
+	return result;
+}
+
+/*!
+ * This function is called by the core driver to set the state of the modem
+ * control lines.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ * @param   mctrl  the state that the modem control lines should be changed to
+ */
+static void mxcuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	volatile unsigned int cr2 = 0, cr3 = 0, uts = 0;
+
+	cr2 = readl(port->membase + MXC_UARTUCR2);
+	cr3 = readl(port->membase + MXC_UARTUCR3);
+	uts = readl(port->membase + MXC_UARTUTS);
+
+	if (mctrl & TIOCM_RTS) {
+		/*
+		 * Return to hardware-driven hardware flow control if the
+		 * option is enabled
+		 */
+		if (umxc->hardware_flow == 1) {
+			cr2 |= MXC_UARTUCR2_CTSC;
+		} else {
+			cr2 |= MXC_UARTUCR2_CTS;
+			cr2 &= ~MXC_UARTUCR2_CTSC;
+		}
+	} else {
+		cr2 &= ~(MXC_UARTUCR2_CTS | MXC_UARTUCR2_CTSC);
+	}
+	writel(cr2, port->membase + MXC_UARTUCR2);
+
+	if (mctrl & TIOCM_DTR) {
+		cr3 |= MXC_UARTUCR3_DSR;
+	} else {
+		cr3 &= ~MXC_UARTUCR3_DSR;
+	}
+	writel(cr3, port->membase + MXC_UARTUCR3);
+
+	if (mctrl & TIOCM_LOOP) {
+		if (umxc->ir_mode == IRDA) {
+			echo_cancel = 0;
+		} else {
+			uts |= MXC_UARTUTS_LOOP;
+		}
+	} else {
+		if (umxc->ir_mode == IRDA) {
+			echo_cancel = 1;
+		} else {
+			uts &= ~MXC_UARTUTS_LOOP;
+		}
+	}
+	writel(uts, port->membase + MXC_UARTUTS);
+}
+
+/*!
+ * This function is called by the core driver to control the transmission of
+ * the break signal. If break_state is non-zero, the break signal is
+ * transmitted, the signal is terminated when another call is made with
+ * break_state set to 0.
+ *
+ * @param   port          the port structure for the UART passed in by the core
+ *                        driver
+ * @param   break_state   the requested state of the break signal
+ */
+static void mxcuart_break_ctl(struct uart_port *port, int break_state)
+{
+	volatile unsigned int cr1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	cr1 = readl(port->membase + MXC_UARTUCR1);
+	if (break_state == -1) {
+		cr1 |= MXC_UARTUCR1_SNDBRK;
+	} else {
+		cr1 &= ~MXC_UARTUCR1_SNDBRK;
+	}
+	writel(cr1, port->membase + MXC_UARTUCR1);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/*!
+ * The read DMA callback, this method is called when the DMA buffer has received its
+ * data. This functions copies the data to the tty buffer and updates the tty buffer
+ * pointers. It also queues the DMA buffer back to the DMA system.
+ *
+ * @param   arg   driver private data
+ * @param   error any DMA error
+ * @param   cnt   amount of data that was transferred
+ */
+static void mxcuart_dmaread_callback(void *arg, int error, unsigned int cnt)
+{
+	uart_mxc_port *umxc = arg;
+	struct tty_struct *tty = umxc->port.info->port.tty;
+	int buff_id, flip_cnt, num_bufs;
+	mxc_dma_requestbuf_t readchnl_request;
+	mxc_uart_rxdmamap *rx_buf_elem = NULL;
+	unsigned int sr1, sr2;
+	char flag;
+
+	num_bufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE;
+	/* Clear the aging timer bit */
+	writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1);
+
+	buff_id = umxc->dma_rxbuf_id;
+	flag = TTY_NORMAL;
+
+	if ((umxc->dma_rxbuf_id += 1) >= num_bufs) {
+		umxc->dma_rxbuf_id = 0;
+	}
+
+	rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + buff_id);
+
+	if (error == MXC_DMA_TRANSFER_ERROR) {
+
+		sr1 = __raw_readl(umxc->port.membase + MXC_UARTUSR1);
+		sr2 = __raw_readl(umxc->port.membase + MXC_UARTUSR2);
+
+		if (sr2 & MXC_UARTUSR2_BRCD) {
+			umxc->port.icount.brk++;
+			if (uart_handle_break(&umxc->port)) {
+				goto drop_data;
+			}
+		} else if (sr1 & MXC_UARTUSR1_PARITYERR) {
+			umxc->port.icount.parity++;
+		} else if (sr1 & MXC_UARTUSR1_FRAMERR) {
+			umxc->port.icount.frame++;
+		} else if (sr2 & MXC_UARTUSR2_ORE) {
+			umxc->port.icount.overrun++;
+
+		}
+
+		if (umxc->port.read_status_mask & MXC_UARTURXD_BRK) {
+			if (sr2 & MXC_UARTUSR2_BRCD)
+				flag = TTY_BREAK;
+		} else if (umxc->port.read_status_mask & MXC_UARTURXD_PRERR) {
+			if (sr1 & MXC_UARTUSR1_PARITYERR)
+				flag = TTY_PARITY;
+		} else if (umxc->port.read_status_mask & MXC_UARTURXD_FRMERR) {
+			if (sr1 & MXC_UARTUSR1_FRAMERR)
+				flag = TTY_FRAME;
+		} else if (umxc->port.read_status_mask & MXC_UARTURXD_OVRRUN) {
+			if (sr2 & MXC_UARTUSR2_ORE)
+				flag = TTY_OVERRUN;
+		}
+/* By default clearing all error bits in status reg */
+		__raw_writel((MXC_UARTUSR2_BRCD | MXC_UARTUSR2_ORE),
+			     umxc->port.membase + MXC_UARTUSR2);
+		__raw_writel((MXC_UARTUSR1_PARITYERR | MXC_UARTUSR1_FRAMERR),
+			     umxc->port.membase + MXC_UARTUSR1);
+	}
+
+	flip_cnt = tty_buffer_request_room(tty, cnt);
+
+	/* Check for space availability in the TTY Flip buffer */
+	if (flip_cnt <= 0) {
+		goto drop_data;
+	}
+	umxc->port.icount.rx += flip_cnt;
+
+	tty_insert_flip_string(tty, rx_buf_elem->rx_buf, flip_cnt);
+
+	if (flag != TTY_NORMAL) {
+		tty_insert_flip_char(tty, 0, flag);
+	}
+
+	tty_flip_buffer_push(tty);
+	umxc->port.info->port.tty->real_raw = 1;
+
+      drop_data:
+	readchnl_request.src_addr = umxc->port.mapbase;
+	readchnl_request.dst_addr = rx_buf_elem->rx_handle;
+	readchnl_request.num_of_bytes = RXDMA_BUFF_SIZE;
+	mxc_dma_config(dma_list[umxc->port.line].rd_channel, &readchnl_request,
+		       1, MXC_DMA_MODE_READ);
+	mxc_dma_enable(dma_list[umxc->port.line].rd_channel);
+}
+
+/*!
+ * Allocates DMA read and write channels, creates DMA read and write buffers and
+ * sets the channel specific parameters.
+ *
+ * @param   d_info the structure that holds all the DMA information for a
+ *                 particular MXC UART
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int mxcuart_initdma(dma_info * d_info, uart_mxc_port * umxc)
+{
+	int ret = 0, rxbufs, i, j;
+	mxc_dma_requestbuf_t *readchnl_reqelem;
+	mxc_uart_rxdmamap *rx_buf_elem;
+
+	/* Request for the read and write channels */
+	d_info->rd_channel = mxc_dma_request(umxc->dma_rx_id, "MXC UART Read");
+	if (d_info->rd_channel < 0) {
+		printk(KERN_ERR "MXC UART: Cannot allocate DMA read channel\n");
+		return -1;
+	} else {
+		d_info->wr_channel =
+		    mxc_dma_request(umxc->dma_tx_id, "MXC UART Write");
+		if (d_info->wr_channel < 0) {
+			mxc_dma_free(d_info->rd_channel);
+			printk(KERN_ERR
+			       "MXC UART: Cannot allocate DMA write channel\n");
+			return -1;
+		}
+	}
+
+	/* Allocate the DMA Transmit Buffer */
+	if ((umxc->tx_buf = kmalloc(TXDMA_BUFF_SIZE, GFP_KERNEL)) == NULL) {
+		ret = -1;
+		goto err_dma_tx_buff;
+	}
+	rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE;
+	/* Allocate the DMA Virtual Receive Buffer */
+	if ((umxc->rx_dmamap = kmalloc(rxbufs * sizeof(mxc_uart_rxdmamap),
+				       GFP_KERNEL)) == NULL) {
+		ret = -1;
+		goto err_dma_rx_buff;
+	}
+
+	/* Allocate the DMA Receive Request structures */
+	if ((readchnl_reqelem =
+	     kmalloc(rxbufs * sizeof(mxc_dma_requestbuf_t),
+		     GFP_KERNEL)) == NULL) {
+		ret = -1;
+		goto err_request;
+	}
+
+	for (i = 0; i < rxbufs; i++) {
+		rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i);
+		rx_buf_elem->rx_buf =
+		    dma_alloc_coherent(NULL, RXDMA_BUFF_SIZE,
+				       &rx_buf_elem->rx_handle, GFP_DMA);
+		if (rx_buf_elem->rx_buf == NULL) {
+			for (j = 0; j < i; j++) {
+				rx_buf_elem =
+				    (mxc_uart_rxdmamap *) (umxc->rx_dmamap + j);
+				dma_free_coherent(NULL, RXDMA_BUFF_SIZE,
+						  rx_buf_elem->rx_buf,
+						  rx_buf_elem->rx_handle);
+			}
+			ret = -1;
+			goto cleanup;
+		}
+	}
+
+	umxc->dma_rxbuf_id = 0;
+	/* Setup the DMA read request structures */
+	for (i = 0; i < rxbufs; i++) {
+		rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i);
+		(readchnl_reqelem + i)->src_addr = umxc->port.mapbase;
+		(readchnl_reqelem + i)->dst_addr = rx_buf_elem->rx_handle;
+		(readchnl_reqelem + i)->num_of_bytes = RXDMA_BUFF_SIZE;
+	}
+	mxc_dma_config(d_info->rd_channel, readchnl_reqelem, rxbufs,
+		       MXC_DMA_MODE_READ);
+	mxc_dma_callback_set(d_info->rd_channel, mxcuart_dmaread_callback,
+			     umxc);
+	mxc_dma_callback_set(d_info->wr_channel, mxcuart_dma_writecallback,
+			     umxc);
+
+	/* Start the read channel */
+	mxc_dma_enable(d_info->rd_channel);
+	kfree(readchnl_reqelem);
+	tasklet_init(&d_info->dma_tx_tasklet, dma_tx_do_tasklet,
+		     (unsigned long)umxc);
+	d_info->dma_txchnl_inuse = 0;
+	return ret;
+      cleanup:
+	kfree(readchnl_reqelem);
+      err_request:
+	kfree(umxc->rx_dmamap);
+      err_dma_rx_buff:
+	kfree(umxc->tx_buf);
+      err_dma_tx_buff:
+	mxc_dma_free(d_info->rd_channel);
+	mxc_dma_free(d_info->wr_channel);
+
+	return ret;
+}
+
+/*!
+ * Stops DMA and frees the DMA resources
+ *
+ * @param   d_info the structure that holds all the DMA information for a
+ *                 particular MXC UART
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ */
+static void mxcuart_freedma(dma_info * d_info, uart_mxc_port * umxc)
+{
+	int i, rxbufs;
+	mxc_uart_rxdmamap *rx_buf_elem;
+
+	rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE;
+
+	for (i = 0; i < rxbufs; i++) {
+		rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i);
+		dma_free_coherent(NULL, RXDMA_BUFF_SIZE,
+				  rx_buf_elem->rx_buf, rx_buf_elem->rx_handle);
+	}
+	kfree(umxc->rx_dmamap);
+	kfree(umxc->tx_buf);
+	mxc_dma_free(d_info->rd_channel);
+	mxc_dma_free(d_info->wr_channel);
+}
+
+/*!
+ * This function is called to free the interrupts.
+ *
+ * @param   umxc   the MXC UART port structure, this includes the \b uart_port
+ *                 structure and other members that are specific to MXC UARTs
+ */
+static void mxcuart_free_interrupts(uart_mxc_port * umxc)
+{
+	free_irq(umxc->port.irq, umxc);
+	if (umxc->ints_muxed == 0) {
+		free_irq(umxc->irqs[0], umxc);
+		free_irq(umxc->irqs[1], umxc);
+	}
+}
+
+/*!
+ * Calculate and set the UART port clock value
+ *
+ * @param   umxc     the MXC UART port structure, this includes the \b uart_port
+ *                   structure and other members that are specific to MXC UARTs
+ * @param   per_clk  peripheral clock coming into the MXC UART module
+ * @param   req_baud current baudrate requested
+ * @param   div      returns the reference frequency divider value
+ */
+static void mxcuart_set_ref_freq(uart_mxc_port * umxc, unsigned long per_clk,
+				 unsigned int req_baud, int *div)
+{
+	unsigned int d = 1;
+
+	/*
+	 * Choose the smallest possible prescaler to maximize
+	 * the chance of using integer scaling.  Ensure that
+	 * the calculation won't overflow.  Limit the denom
+	 * to 15 bits since a 16-bit denom doesn't work.
+	 */
+	if (req_baud < (1 << (31 - (4 + 15))))
+		d = per_clk / (req_baud << (4 + 15)) + 1;
+
+	umxc->port.uartclk = per_clk / d;
+
+	/*
+	 * Set the ONEMS register that is used by IR special case bit and
+	 * the Escape character detect logic
+	 */
+	writel(umxc->port.uartclk / 1000, umxc->port.membase + MXC_UARTONEMS);
+	*div = d;
+}
+
+/*!
+ * This function is called by the core driver to initialize the low-level
+ * driver. The function grabs the interrupt resources and registers its
+ * interrupt service routines. It then initializes the IOMUX registers to
+ * configure the pins for UART signals and finally initializes the various
+ * UART registers and enables the port for reception.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int mxcuart_startup(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	int retval;
+	volatile unsigned int cr, cr1 = 0, cr2 = 0, ufcr = 0;
+
+	/*
+	 * Some UARTs need separate registrations for the interrupts as
+	 * they do not take the muxed interrupt output to the ARM core
+	 */
+	if (umxc->ints_muxed == 1) {
+		retval = request_irq(umxc->port.irq, mxcuart_int, 0,
+				     "mxcintuart", umxc);
+		if (retval != 0) {
+			return retval;
+		}
+	} else {
+		retval = request_irq(umxc->port.irq, mxcuart_tx_int,
+				     0, "mxcintuart", umxc);
+		if (retval != 0) {
+			return retval;
+		} else {
+			retval = request_irq(umxc->irqs[0], mxcuart_rx_int,
+					     0, "mxcintuart", umxc);
+			if (retval != 0) {
+				free_irq(umxc->port.irq, umxc);
+				return retval;
+			} else {
+				retval =
+				    request_irq(umxc->irqs[1], mxcuart_mint_int,
+						0, "mxcintuart", umxc);
+				if (retval != 0) {
+					free_irq(umxc->port.irq, umxc);
+					free_irq(umxc->irqs[0], umxc);
+					return retval;
+				}
+			}
+		}
+	}
+
+	/* Initialize the DMA if we need SDMA data transfer */
+	if (umxc->dma_enabled == 1) {
+		retval = mxcuart_initdma(dma_list + umxc->port.line, umxc);
+		if (retval != 0) {
+			printk
+			    (KERN_ERR
+			     "MXC UART: Failed to initialize DMA for UART %d\n",
+			     umxc->port.line);
+			mxcuart_free_interrupts(umxc);
+			return retval;
+		}
+		/* Configure the GPR register to receive SDMA events */
+		config_uartdma_event(umxc->port.line);
+	}
+
+	/*
+	 * Clear Status Registers 1 and 2
+	 */
+	writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1);
+	writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2);
+
+	/* Configure the IOMUX for the UART */
+	gpio_uart_active(umxc->port.line, umxc->ir_mode);
+
+	/*
+	 * Set the transceiver invert bits if required
+	 */
+	if (umxc->ir_mode == IRDA) {
+		echo_cancel = 1;
+		writel(umxc->ir_rx_inv | MXC_UARTUCR4_IRSC, umxc->port.membase
+		       + MXC_UARTUCR4);
+		writel(umxc->rxd_mux | umxc->ir_tx_inv,
+		       umxc->port.membase + MXC_UARTUCR3);
+	} else {
+		writel(umxc->rxd_mux, umxc->port.membase + MXC_UARTUCR3);
+	}
+
+	/*
+	 * Initialize UCR1,2 and UFCR registers
+	 */
+	if (umxc->dma_enabled == 1) {
+		cr2 = (MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN);
+	} else {
+		cr2 =
+		    (MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN);
+	}
+
+	writel(cr2, umxc->port.membase + MXC_UARTUCR2);
+	/* Wait till we are out of software reset */
+	do {
+		cr = readl(umxc->port.membase + MXC_UARTUCR2);
+	} while (!(cr & MXC_UARTUCR2_SRST));
+
+	if (umxc->mode == MODE_DTE) {
+		ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) |
+			 MXC_UARTUFCR_DCEDTE | MXC_UARTUFCR_RFDIV | umxc->
+			 rx_threshold);
+	} else {
+		ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) |
+			 MXC_UARTUFCR_RFDIV | umxc->rx_threshold);
+	}
+	writel(ufcr, umxc->port.membase + MXC_UARTUFCR);
+
+	/*
+	 * Finally enable the UART and the Receive interrupts
+	 */
+	if (umxc->ir_mode == IRDA) {
+		cr1 |= MXC_UARTUCR1_IREN;
+	}
+	if (umxc->dma_enabled == 1) {
+		cr1 |= (MXC_UARTUCR1_RXDMAEN | MXC_UARTUCR1_ATDMAEN |
+			MXC_UARTUCR1_UARTEN);
+	} else {
+		cr1 |= (MXC_UARTUCR1_RRDYEN | MXC_UARTUCR1_UARTEN);
+	}
+	writel(cr1, umxc->port.membase + MXC_UARTUCR1);
+
+	return 0;
+}
+
+/*!
+ * This function is called by the core driver for the low-level driver to free
+ * its resources. The function frees all its interrupts and disables the UART.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ */
+static void mxcuart_shutdown(struct uart_port *port)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+
+	/* Disable the IOMUX for the UART */
+	gpio_uart_inactive(umxc->port.line, umxc->ir_mode);
+	mxcuart_free_interrupts(umxc);
+	/* Disable all interrupts, port and break condition */
+	writel(0, umxc->port.membase + MXC_UARTUCR1);
+	writel(0, umxc->port.membase + MXC_UARTUCR3);
+	if (umxc->dma_enabled == 1) {
+		mxcuart_freedma(dma_list + umxc->port.line, umxc);
+	}
+}
+
+/*!
+ * This function is called while changing the UART parameters. It is called to
+ * check if the Infrared special case bit (IRSC) in control register 4 should
+ * be set.
+ *
+ * @param   baudrate   the desired baudrate
+ *
+ * @return  The functions returns 0 if the IRSC bit does not have to be set,
+ *          else it returns a 1.
+ */
+/*
+static int mxcuart_setir_special(u_int baudrate)
+{
+        u_int thresh_val;
+
+        thresh_val = 1000000 / (8 * MIN_PULSE_DUR);
+        if (baudrate > thresh_val) {
+                return 0;
+        }
+
+        return 1;
+}
+*/
+
+/*!
+ * This function is called by the core driver to change the UART parameters,
+ * including baudrate, word length, parity, stop bits. The function also updates
+ * the port structures mask registers to indicate the types of events the user is
+ * interested in receiving.
+ *
+ * @param   port    the port structure for the UART passed in by the core driver
+ * @param   termios the desired termios settings
+ * @param   old     old termios
+ */
+static void mxcuart_set_termios(struct uart_port *port,
+				struct ktermios *termios, struct ktermios *old)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+	volatile unsigned int cr4 = 0, cr2 = 0, ufcr;
+	u_int num, denom, baud;
+	u_int cr2_mask;		/* Used to add the changes to CR2 */
+	unsigned long flags, per_clk;
+	int div;
+
+	cr2_mask = ~(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTSC | MXC_UARTUCR2_PREN |
+		     MXC_UARTUCR2_PROE | MXC_UARTUCR2_STPB | MXC_UARTUCR2_WS);
+
+	per_clk = clk_get_rate(umxc->clk);
+
+	/*
+	 * Ask the core to get the baudrate, if requested baudrate is not
+	 * between max and min, then either use the baudrate in old termios
+	 * setting. If it's still invalid, we try 9600 baud.
+	 */
+	baud = uart_get_baud_rate(&umxc->port, termios, old, 0, per_clk / 16);
+	/* Set the Reference frequency divider */
+	mxcuart_set_ref_freq(umxc, per_clk, baud, &div);
+
+	/* Byte size, default is 8-bit mode */
+	switch (termios->c_cflag & CSIZE) {
+	case CS7:
+		cr2 = 0;
+		break;
+	default:
+		cr2 = MXC_UARTUCR2_WS;
+		break;
+	}
+	/* Check to see if we need 2 Stop bits */
+	if (termios->c_cflag & CSTOPB) {
+		cr2 |= MXC_UARTUCR2_STPB;
+	}
+
+	/* Check to see if we need Parity checking */
+	if (termios->c_cflag & PARENB) {
+		cr2 |= MXC_UARTUCR2_PREN;
+		if (termios->c_cflag & PARODD) {
+			cr2 |= MXC_UARTUCR2_PROE;
+		}
+	}
+	spin_lock_irqsave(&umxc->port.lock, flags);
+
+	ufcr = readl(umxc->port.membase + MXC_UARTUFCR);
+	ufcr = (ufcr & (~MXC_UARTUFCR_RFDIV_MASK)) |
+	    ((6 - div) << MXC_UARTUFCR_RFDIV_OFFSET);
+	writel(ufcr, umxc->port.membase + MXC_UARTUFCR);
+
+	/*
+	 * Update the per-port timeout
+	 */
+	uart_update_timeout(&umxc->port, termios->c_cflag, baud);
+
+	umxc->port.read_status_mask = MXC_UARTURXD_OVRRUN;
+	/*
+	 * Enable appropriate events to be passed to the TTY layer
+	 */
+	if (termios->c_iflag & INPCK) {
+		umxc->port.read_status_mask |= MXC_UARTURXD_FRMERR |
+		    MXC_UARTURXD_PRERR;
+	}
+	if (termios->c_iflag & (BRKINT | PARMRK)) {
+		umxc->port.read_status_mask |= MXC_UARTURXD_BRK;
+	}
+
+	/*
+	 * Characters to ignore
+	 */
+	umxc->port.ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR) {
+		umxc->port.ignore_status_mask |= MXC_UARTURXD_FRMERR |
+		    MXC_UARTURXD_PRERR;
+	}
+	if (termios->c_iflag & IGNBRK) {
+		umxc->port.ignore_status_mask |= MXC_UARTURXD_BRK;
+		/*
+		 * If we are ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support)
+		 */
+		if (termios->c_iflag & IGNPAR) {
+			umxc->port.ignore_status_mask |= MXC_UARTURXD_OVRRUN;
+		}
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set, still receive characters
+	 * from the port, but throw them away.
+	 */
+	if ((termios->c_cflag & CREAD) == 0) {
+		umxc->port.ignore_status_mask |= UART_CREAD_BIT;
+	}
+
+	cr4 = readl(umxc->port.membase + MXC_UARTUCR4);
+	if (UART_ENABLE_MS(port, termios->c_cflag)) {
+		mxcuart_enable_ms(port);
+		if (umxc->hardware_flow == 1) {
+			cr4 = (cr4 & (~MXC_UARTUCR4_CTSTL_MASK)) |
+			    (umxc->cts_threshold << MXC_UARTUCR4_CTSTL_OFFSET);
+			cr2 |= MXC_UARTUCR2_CTSC;
+			umxc->port.info->port.tty->hw_stopped = 0;
+		} else {
+			cr2 |= MXC_UARTUCR2_IRTS;
+		}
+	} else {
+		cr2 |= MXC_UARTUCR2_IRTS;
+	}
+
+	/* Add Parity, character length and stop bits information */
+	cr2 |= (readl(umxc->port.membase + MXC_UARTUCR2) & cr2_mask);
+	writel(cr2, umxc->port.membase + MXC_UARTUCR2);
+	/*
+	   if (umxc->ir_mode == IRDA) {
+	   ret = mxcuart_setir_special(baud);
+	   if (ret == 0) {
+	   cr4 &= ~MXC_UARTUCR4_IRSC;
+	   } else {
+	   cr4 |= MXC_UARTUCR4_IRSC;
+	   }
+	   } */
+	writel(cr4, umxc->port.membase + MXC_UARTUCR4);
+
+	/*
+	 * Set baud rate
+	 */
+
+	/* Use integer scaling, if possible. Limit the denom to 15 bits. */
+	num = 0;
+	denom = (umxc->port.uartclk + 8 * baud) / (16 * baud) - 1;
+
+	/* Use fractional scaling if needed to limit the max error to 0.5% */
+	if (denom < 100) {
+		u64 n64 = (u64) 16 * 0x8000 * baud + (umxc->port.uartclk / 2);
+		do_div(n64, umxc->port.uartclk);
+		num = (u_int) n64 - 1;
+		denom = 0x7fff;
+	}
+	writel(num, umxc->port.membase + MXC_UARTUBIR);
+	writel(denom, umxc->port.membase + MXC_UARTUBMR);
+
+	spin_unlock_irqrestore(&umxc->port.lock, flags);
+}
+
+/*!
+ * This function is called by the core driver to know the UART type.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ *
+ * @return  The function returns a pointer to a string describing the UART port.
+ */
+static const char *mxcuart_type(struct uart_port *port)
+{
+	return port->type == PORT_IMX ? "Freescale i.MX" : NULL;
+}
+
+/*!
+ * This function is called by the core driver to release the memory resources
+ * currently in use by the UART port.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ */
+static void mxcuart_release_port(struct uart_port *port)
+{
+	release_mem_region(port->mapbase, SZ_4K);
+}
+
+/*!
+ * This function is called by the core driver to request memory resources for
+ * the UART port.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ *
+ * @return  The function returns \b -EBUSY on failure, else it returns 0.
+ */
+static int mxcuart_request_port(struct uart_port *port)
+{
+	struct platform_device *pdev = to_platform_device(port->dev);
+	struct resource *mmres;
+	void *ret;
+
+	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mmres)
+		return -ENODEV;
+
+	ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
+							"serial_mxc");
+
+	return  ret ? 0 : -EBUSY;
+}
+
+/*!
+ * This function is called by the core driver to perform any autoconfiguration
+ * steps required for the UART port. This function sets the port->type field.
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ * @param   flags  bit mask of the required configuration
+ */
+static void mxcuart_config_port(struct uart_port *port, int flags)
+{
+	if ((flags & UART_CONFIG_TYPE) && (mxcuart_request_port(port) == 0)) {
+		port->type = PORT_IMX;
+	}
+}
+
+/*!
+ * This function is called by the core driver to verify that the new serial
+ * port information contained within \a ser is suitable for this UART port type.
+ * The function checks to see if the UART port type specified by the user
+ * application while setting the UART port information matches what is stored
+ * in the define \b PORT_MXC found in the header file include/linux/serial_core.h
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ * @param   ser    the new serial port information
+ *
+ * @return  The function returns 0 on success or \b -EINVAL if the port type
+ *          specified is not equal to \b PORT_MXC.
+ */
+static int mxcuart_verify_port(struct uart_port *port,
+			       struct serial_struct *ser)
+{
+	int ret = 0;
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) {
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+/*!
+ * This function is used to send a high priority XON/XOFF character
+ *
+ * @param   port   the port structure for the UART passed in by the core driver
+ * @param   ch     the character to send
+ */
+static void mxcuart_send_xchar(struct uart_port *port, char ch)
+{
+	unsigned long flags;
+
+	port->x_char = ch;
+	if (port->info->port.tty->hw_stopped) {
+		return;
+	}
+
+	if (ch) {
+		spin_lock_irqsave(&port->lock, flags);
+		port->ops->start_tx(port);
+		spin_unlock_irqrestore(&port->lock, flags);
+	}
+}
+
+/*!
+ * This function is used enable/disable the MXC UART clocks
+ *
+ * @param   port      the port structure for the UART passed in by the core driver
+ * @param   state     New PM state
+ * @param   oldstate  Current PM state
+ */
+static void
+mxcuart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
+{
+	uart_mxc_port *umxc = (uart_mxc_port *) port;
+
+	if (state)
+		clk_disable(umxc->clk);
+	else
+		clk_enable(umxc->clk);
+}
+
+/*!
+ * This structure contains the pointers to the control functions that are
+ * invoked by the core serial driver to access the UART hardware. The
+ * structure is passed to serial_core.c file during registration.
+ */
+static struct uart_ops mxc_ops = {
+	.tx_empty = mxcuart_tx_empty,
+	.set_mctrl = mxcuart_set_mctrl,
+	.get_mctrl = mxcuart_get_mctrl,
+	.stop_tx = mxcuart_stop_tx,
+	.start_tx = mxcuart_start_tx,
+	.stop_rx = mxcuart_stop_rx,
+	.enable_ms = mxcuart_enable_ms,
+	.break_ctl = mxcuart_break_ctl,
+	.startup = mxcuart_startup,
+	.shutdown = mxcuart_shutdown,
+	.set_termios = mxcuart_set_termios,
+	.type = mxcuart_type,
+	.pm = mxcuart_pm,
+	.release_port = mxcuart_release_port,
+	.request_port = mxcuart_request_port,
+	.config_port = mxcuart_config_port,
+	.verify_port = mxcuart_verify_port,
+	.send_xchar = mxcuart_send_xchar,
+};
+
+#ifdef CONFIG_SERIAL_MXC_CONSOLE
+
+/*
+ * Write out a character once the UART is ready
+ */
+static inline void mxcuart_console_write_char(struct uart_port *port, char ch)
+{
+	volatile unsigned int status;
+
+	do {
+		status = readl(port->membase + MXC_UARTUSR1);
+	} while ((status & MXC_UARTUSR1_TRDY) == 0);
+	writel(ch, port->membase + MXC_UARTUTXD);
+}
+
+/*!
+ * This function is called to write the console messages through the UART port.
+ *
+ * @param   co    the console structure
+ * @param   s     the log message to be written to the UART
+ * @param   count length of the message
+ */
+static void mxcuart_console_write(struct console *co, const char *s,
+				  u_int count)
+{
+	struct uart_port *port = &mxc_ports[co->index]->port;
+	volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3;
+	int i;
+
+	/*
+	 * First save the control registers and then disable the interrupts
+	 */
+	oldcr1 = readl(port->membase + MXC_UARTUCR1);
+	oldcr2 = readl(port->membase + MXC_UARTUCR2);
+	oldcr3 = readl(port->membase + MXC_UARTUCR3);
+	cr2 =
+	    oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN |
+		       MXC_UARTUCR2_ESCI);
+	cr3 =
+	    oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI |
+		       MXC_UARTUCR3_DTRDEN);
+	writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1);
+	writel(cr2, port->membase + MXC_UARTUCR2);
+	writel(cr3, port->membase + MXC_UARTUCR3);
+	/*
+	 * Do each character
+	 */
+	for (i = 0; i < count; i++) {
+		mxcuart_console_write_char(port, s[i]);
+		if (s[i] == '\n') {
+			mxcuart_console_write_char(port, '\r');
+		}
+	}
+	/*
+	 * Finally, wait for the transmitter to become empty
+	 */
+	do {
+		status = readl(port->membase + MXC_UARTUSR2);
+	} while (!(status & MXC_UARTUSR2_TXDC));
+
+	/*
+	 * Restore the control registers
+	 */
+	writel(oldcr1, port->membase + MXC_UARTUCR1);
+	writel(oldcr2, port->membase + MXC_UARTUCR2);
+	writel(oldcr3, port->membase + MXC_UARTUCR3);
+}
+
+/*!
+ * Initializes the UART port to be used to print console message with the
+ * options specified. If no options are specified, then the function
+ * initializes the UART with the default options of baudrate=115200, 8 bit
+ * word size, no parity, no flow control.
+ *
+ * @param   co      The console structure
+ * @param   options Any console options passed in from the command line
+ *
+ * @return  The function returns 0 on success or error.
+ */
+static int __init mxcuart_console_setup(struct console *co, char *options)
+{
+	uart_mxc_port *umxc;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+	volatile unsigned int cr = 0;
+
+	/*
+	 * Check whether an invalid uart number had been specified, and if
+	 * so, search for the first available port that does have console
+	 * support
+	 */
+	if (co->index >= MXC_UART_NR) {
+		co->index = 0;
+	}
+	umxc = mxc_ports[co->index];
+
+	if (umxc == NULL) {
+		return -ENODEV;
+	}
+
+	clk_enable(umxc->clk);
+
+	/* initialize port.lock else oops */
+	spin_lock_init(&umxc->port.lock);
+
+	/*
+	 * Initialize the UART registers
+	 */
+	writel(MXC_UARTUCR1_UARTEN, umxc->port.membase + MXC_UARTUCR1);
+	/* Enable the transmitter and do a software reset */
+	writel(MXC_UARTUCR2_TXEN, umxc->port.membase + MXC_UARTUCR2);
+	/* Wait till we are out of software reset */
+	do {
+		cr = readl(umxc->port.membase + MXC_UARTUCR2);
+	} while (!(cr & MXC_UARTUCR2_SRST));
+
+	writel(0x0, umxc->port.membase + MXC_UARTUCR3);
+	writel(0x0, umxc->port.membase + MXC_UARTUCR4);
+	/* Set TXTL to 2, RXTL to 1 and RFDIV to 2 */
+	cr = 0x0800 | MXC_UARTUFCR_RFDIV | 0x1;
+	if (umxc->mode == MODE_DTE) {
+		cr |= MXC_UARTUFCR_DCEDTE;
+	}
+	writel(cr, umxc->port.membase + MXC_UARTUFCR);
+	writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1);
+	writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2);
+
+	if (options != NULL) {
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	}
+	gpio_uart_active(umxc->port.line, umxc->ir_mode);
+	return uart_set_options(&umxc->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver mxc_reg;
+
+/*!
+ * This structure contains the pointers to the UART console functions. It is
+ * passed as an argument when registering the console.
+ */
+static struct console mxc_console = {
+	.name = "ttymxc",
+	.write = mxcuart_console_write,
+	.device = uart_console_device,
+	.setup = mxcuart_console_setup,
+	.flags = CON_PRINTBUFFER,
+	.index = -1,
+	.data = &mxc_reg,
+};
+
+/*!
+ * This function registers the console callback functions with the kernel.
+ */
+static int __init mxcuart_console_init(void)
+{
+	register_console(&mxc_console);
+	return 0;
+}
+
+console_initcall(mxcuart_console_init);
+
+static int __init find_port(struct uart_port *p)
+{
+	int line;
+	struct uart_port *port;
+	for (line = 0; line < MXC_UART_NR; line++) {
+		if (!mxc_ports[line])
+			continue;
+		port = &mxc_ports[line]->port;
+		if (uart_match_port(p, port))
+			return line;
+	}
+	return -ENODEV;
+}
+
+int __init mxc_uart_start_console(struct uart_port *port, char *options)
+{
+	int line;
+	line = find_port(port);
+	if (line < 0)
+		return -ENODEV;
+
+	add_preferred_console("ttymxc", line, options);
+	printk("Switching Console to ttymxc%d at %s 0x%lx (options '%s')\n",
+	       line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
+	       port->iotype ==
+	       UPIO_MEM ? (unsigned long)port->mapbase : (unsigned long)port->
+	       iobase, options);
+
+	if (!(mxc_console.flags & CON_ENABLED)) {
+		mxc_console.flags &= ~CON_PRINTBUFFER;
+		register_console(&mxc_console);
+	}
+	return 0;
+}
+
+#define MXC_CONSOLE     &mxc_console
+#else
+#define MXC_CONSOLE     NULL
+#endif				/* CONFIG_SERIAL_MXC_CONSOLE */
+
+/*!
+ * This structure contains the information such as the name of the UART driver
+ * that appears in the /dev folder, major and minor numbers etc. This structure
+ * is passed to the serial_core.c file.
+ */
+static struct uart_driver mxc_reg = {
+	.owner = THIS_MODULE,
+	.driver_name = "ttymxc",
+	.dev_name = "ttymxc",
+	.major = SERIAL_MXC_MAJOR,
+	.minor = SERIAL_MXC_MINOR,
+	.nr = MXC_UART_NR,
+	.cons = MXC_CONSOLE,
+};
+
+/*!
+ * This function is called to put the UART in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which UART
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxcuart_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	uart_mxc_port *umxc = platform_get_drvdata(pdev);
+
+	if (umxc == NULL)
+		return 0;	/* skip disabled ports */
+
+	if (umxc->port.info && umxc->port.info->flags & UIF_INITIALIZED)
+		uart_suspend_port(&mxc_reg, &umxc->port);
+
+	if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED)
+		umxc->port.info->port.tty->hw_stopped = 1;
+
+	return 0;
+}
+
+/*!
+ * This function is called to bring the UART back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which UART
+ *                to resume
+ *
+ * @return  The function returns 0 on success and -1 on failure
+ */
+static int mxcuart_resume(struct platform_device *pdev)
+{
+	uart_mxc_port *umxc = platform_get_drvdata(pdev);
+
+	if (umxc == NULL)
+		return 0;	/* skip disabled ports */
+
+	if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED) {
+		umxc->port.info->port.tty->hw_stopped = 0;
+		uart_resume_port(&mxc_reg, &umxc->port);
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is called during the driver binding process. Based on the UART
+ * that is being probed this function adds the appropriate UART port structure
+ * in the core driver.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions
+ *
+ * @return  The function returns 0 if successful; -1 otherwise.
+ */
+static int mxcuart_probe(struct platform_device *pdev)
+{
+	int id = pdev->id;
+	struct resource *res;
+	void __iomem *base;
+
+	mxc_ports[id] = pdev->dev.platform_data;
+	mxc_ports[id]->port.ops = &mxc_ops;
+
+	/* Do not use UARTs that are disabled during integration */
+	if (mxc_ports[id]->enabled == 1) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res)
+			return -ENODEV;
+
+		base = ioremap(res->start, res->end - res->start + 1);
+		if (!base)
+			return -ENOMEM;
+
+		mxc_ports[id]->port.membase = base;
+		mxc_ports[id]->port.mapbase = res->start;
+		mxc_ports[id]->port.dev = &pdev->dev;
+		mxc_ports[id]->port.irq = platform_get_irq(pdev, 0);
+		mxc_ports[id]->irqs[0] = platform_get_irq(pdev, 1);
+		mxc_ports[id]->irqs[1] = platform_get_irq(pdev, 2);
+		spin_lock_init(&mxc_ports[id]->port.lock);
+		/* Enable the low latency flag for DMA UART ports */
+		if (mxc_ports[id]->dma_enabled == 1) {
+			mxc_ports[id]->port.flags |= UPF_LOW_LATENCY;
+		}
+
+		mxc_ports[id]->clk = clk_get(&pdev->dev, "uart_clk");
+		if (mxc_ports[id]->clk == NULL)
+			return -1;
+
+		uart_add_one_port(&mxc_reg, &mxc_ports[id]->port);
+		platform_set_drvdata(pdev, mxc_ports[id]);
+	}
+	return 0;
+}
+
+/*!
+ * Dissociates the driver from the UART device. Removes the appropriate UART
+ * port structure from the core driver.
+ *
+ * @param   pdev  the device structure used to give information on which UART
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxcuart_remove(struct platform_device *pdev)
+{
+	uart_mxc_port *umxc = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	if (umxc) {
+		uart_remove_one_port(&mxc_reg, &umxc->port);
+		iounmap(umxc->port.membase);
+	}
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcuart_driver = {
+	.driver = {
+		   .name = "mxcintuart",
+		   },
+	.probe = mxcuart_probe,
+	.remove = mxcuart_remove,
+	.suspend = mxcuart_suspend,
+	.resume = mxcuart_resume,
+};
+
+/*!
+ * This function is used to initialize the UART driver module. The function
+ * registers the power management callback functions with the kernel and also
+ * registers the UART callback functions with the core serial driver.
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxcuart_init(void)
+{
+	int ret = 0;
+
+	printk(KERN_INFO "Serial: MXC Internal UART driver\n");
+	ret = uart_register_driver(&mxc_reg);
+	if (ret == 0) {
+		/* Register the device driver structure. */
+		ret = platform_driver_register(&mxcuart_driver);
+		if (ret != 0) {
+			uart_unregister_driver(&mxc_reg);
+		}
+	}
+	return ret;
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxcuart_exit(void)
+{
+	platform_driver_unregister(&mxcuart_driver);
+	uart_unregister_driver(&mxc_reg);
+}
+
+module_init(mxcuart_init);
+module_exit(mxcuart_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC serial port driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/mxc_uart_early.c b/drivers/serial/mxc_uart_early.c
new file mode 100644
index 000000000000..f4b6493a9a64
--- /dev/null
+++ b/drivers/serial/mxc_uart_early.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drivers/serial/mxc_uart_early.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC serial ports based on
+ * drivers/char/8250_early.c, Copyright 2004 Hewlett-Packard Development Company,
+ * L.P.	by Bjorn Helgaasby.
+ *
+ * Early serial console for MXC UARTS.
+ *
+ * This is for use before the serial driver has initialized, in
+ * particular, before the UARTs have been discovered and named.
+ * Instead of specifying the console device as, e.g., "ttymxc0",
+ * we locate the device directly by its MMIO or I/O port address.
+ *
+ * The user can specify the device directly, e.g.,
+ *	console=mxcuart,0x43f90000,115200n8
+ * or platform code can call early_uart_console_init() to set
+ * the early UART device.
+ *
+ * After the normal serial driver starts, we try to locate the
+ * matching ttymxc device and start a console there.
+ */
+
+/*
+ * Include Files
+ */
+
+#include <linux/tty.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/clk.h>
+#include <mach/mxc_uart.h>
+
+struct mxc_early_uart_device {
+	struct uart_port port;
+	char options[16];	/* e.g., 115200n8 */
+	unsigned int baud;
+	struct clk *clk;
+};
+static struct mxc_early_uart_device mxc_early_device __initdata;
+
+/*
+ * Write out a character once the UART is ready
+ */
+static void __init mxcuart_console_write_char(struct uart_port *port, int ch)
+{
+	unsigned int status;
+
+	do {
+		status = readl(port->membase + MXC_UARTUSR2);
+	} while ((status & MXC_UARTUSR2_TXFE) == 0);
+	writel(ch, port->membase + MXC_UARTUTXD);
+}
+
+/*!
+ * This function is called to write the console messages through the UART port.
+ *
+ * @param   co    the console structure
+ * @param   s     the log message to be written to the UART
+ * @param   count length of the message
+ */
+void __init early_mxcuart_console_write(struct console *co, const char *s,
+					u_int count)
+{
+	struct uart_port *port = &mxc_early_device.port;
+	volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3;
+
+	/*
+	 * First save the control registers and then disable the interrupts
+	 */
+	oldcr1 = readl(port->membase + MXC_UARTUCR1);
+	oldcr2 = readl(port->membase + MXC_UARTUCR2);
+	oldcr3 = readl(port->membase + MXC_UARTUCR3);
+	cr2 =
+	    oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN |
+		       MXC_UARTUCR2_ESCI);
+	cr3 =
+	    oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI |
+		       MXC_UARTUCR3_DTRDEN);
+	writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1);
+	writel(cr2, port->membase + MXC_UARTUCR2);
+	writel(cr3, port->membase + MXC_UARTUCR3);
+
+	/* Transmit string */
+	uart_console_write(port, s, count, mxcuart_console_write_char);
+
+	/*
+	 * Finally, wait for the transmitter to become empty
+	 */
+	do {
+		status = readl(port->membase + MXC_UARTUSR2);
+	} while (!(status & MXC_UARTUSR2_TXDC));
+
+	/*
+	 * Restore the control registers
+	 */
+	writel(oldcr1, port->membase + MXC_UARTUCR1);
+	writel(oldcr2, port->membase + MXC_UARTUCR2);
+	writel(oldcr3, port->membase + MXC_UARTUCR3);
+}
+
+static unsigned int __init probe_baud(struct uart_port *port)
+{
+	/* FIXME Return Default Baud Rate */
+	return 115200;
+}
+
+static int __init mxc_early_uart_setup(struct console *console, char *options)
+{
+	struct mxc_early_uart_device *device = &mxc_early_device;
+	struct uart_port *port = &device->port;
+	int length;
+
+	if (device->port.membase || device->port.iobase)
+		return -ENODEV;
+
+	/* Enable Early MXC UART Clock */
+	clk_enable(device->clk);
+
+	port->uartclk = 5600000;
+	port->iotype = UPIO_MEM;
+	port->membase = ioremap(port->mapbase, SZ_4K);
+
+	if (options) {
+		device->baud = simple_strtoul(options, NULL, 0);
+		length = min(strlen(options), sizeof(device->options));
+		strncpy(device->options, options, length);
+	} else {
+		device->baud = probe_baud(port);
+		snprintf(device->options, sizeof(device->options), "%u",
+			 device->baud);
+	}
+	printk(KERN_INFO
+	       "MXC_Early serial console at MMIO 0x%x (options '%s')\n",
+	       port->mapbase, device->options);
+	return 0;
+}
+
+static struct console mxc_early_uart_console __initdata = {
+	.name = "ttymxc",
+	.write = early_mxcuart_console_write,
+	.setup = mxc_early_uart_setup,
+	.flags = CON_PRINTBUFFER | CON_BOOT,
+	.index = -1,
+};
+
+int __init mxc_early_serial_console_init(unsigned long base, struct clk *clk)
+{
+	mxc_early_device.clk = clk;
+	mxc_early_device.port.mapbase = base;
+
+	register_console(&mxc_early_uart_console);
+	return 0;
+}
+
+int __init mxc_early_uart_console_disable(void)
+{
+	struct mxc_early_uart_device *device = &mxc_early_device;
+	struct uart_port *port = &device->port;
+
+	if (mxc_early_uart_console.index >= 0) {
+		iounmap(port->membase);
+		clk_disable(device->clk);
+		clk_put(device->clk);
+	}
+	return 0;
+}
+late_initcall(mxc_early_uart_console_disable);
diff --git a/drivers/serial/mxc_uart_reg.h b/drivers/serial/mxc_uart_reg.h
new file mode 100644
index 000000000000..c0d1e812fe6a
--- /dev/null
+++ b/drivers/serial/mxc_uart_reg.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MXC_UART_REG_H__
+#define __MXC_UART_REG_H__
+
+/* Address offsets of the UART registers */
+#define MXC_UARTURXD            0x000	/* Receive reg */
+#define MXC_UARTUTXD            0x040	/* Transmitter reg */
+#define	MXC_UARTUCR1            0x080	/* Control reg 1 */
+#define MXC_UARTUCR2            0x084	/* Control reg 2 */
+#define MXC_UARTUCR3            0x088	/* Control reg 3 */
+#define MXC_UARTUCR4            0x08C	/* Control reg 4 */
+#define MXC_UARTUFCR            0x090	/* FIFO control reg */
+#define MXC_UARTUSR1            0x094	/* Status reg 1 */
+#define MXC_UARTUSR2            0x098	/* Status reg 2 */
+#define MXC_UARTUESC            0x09C	/* Escape character reg */
+#define MXC_UARTUTIM            0x0A0	/* Escape timer reg */
+#define MXC_UARTUBIR            0x0A4	/* BRM incremental reg */
+#define MXC_UARTUBMR            0x0A8	/* BRM modulator reg */
+#define MXC_UARTUBRC            0x0AC	/* Baud rate count reg */
+#define MXC_UARTONEMS           0x0B0	/* One millisecond reg */
+#define MXC_UARTUTS             0x0B4	/* Test reg */
+
+/* Bit definations of UCR1 */
+#define MXC_UARTUCR1_ADEN       0x8000
+#define MXC_UARTUCR1_ADBR       0x4000
+#define MXC_UARTUCR1_TRDYEN     0x2000
+#define MXC_UARTUCR1_IDEN       0x1000
+#define MXC_UARTUCR1_RRDYEN     0x0200
+#define MXC_UARTUCR1_RXDMAEN    0x0100
+#define MXC_UARTUCR1_IREN       0x0080
+#define MXC_UARTUCR1_TXMPTYEN   0x0040
+#define MXC_UARTUCR1_RTSDEN     0x0020
+#define MXC_UARTUCR1_SNDBRK     0x0010
+#define MXC_UARTUCR1_TXDMAEN    0x0008
+#define MXC_UARTUCR1_ATDMAEN    0x0004
+#define MXC_UARTUCR1_DOZE       0x0002
+#define MXC_UARTUCR1_UARTEN     0x0001
+
+/* Bit definations of UCR2 */
+#define MXC_UARTUCR2_ESCI       0x8000
+#define MXC_UARTUCR2_IRTS       0x4000
+#define MXC_UARTUCR2_CTSC       0x2000
+#define MXC_UARTUCR2_CTS        0x1000
+#define MXC_UARTUCR2_PREN       0x0100
+#define MXC_UARTUCR2_PROE       0x0080
+#define MXC_UARTUCR2_STPB       0x0040
+#define MXC_UARTUCR2_WS         0x0020
+#define MXC_UARTUCR2_RTSEN      0x0010
+#define MXC_UARTUCR2_ATEN       0x0008
+#define MXC_UARTUCR2_TXEN       0x0004
+#define MXC_UARTUCR2_RXEN       0x0002
+#define MXC_UARTUCR2_SRST       0x0001
+
+/* Bit definations of UCR3 */
+#define MXC_UARTUCR3_DTREN      0x2000
+#define MXC_UARTUCR3_PARERREN   0x1000
+#define MXC_UARTUCR3_FRAERREN   0x0800
+#define MXC_UARTUCR3_DSR        0x0400
+#define MXC_UARTUCR3_DCD        0x0200
+#define MXC_UARTUCR3_RI         0x0100
+#define MXC_UARTUCR3_RXDSEN     0x0040
+#define MXC_UARTUCR3_AWAKEN     0x0010
+#define MXC_UARTUCR3_DTRDEN     0x0008
+#define MXC_UARTUCR3_RXDMUXSEL  0x0004
+#define MXC_UARTUCR3_INVT       0x0002
+
+/* Bit definations of UCR4 */
+#define MXC_UARTUCR4_CTSTL_OFFSET       10
+#define MXC_UARTUCR4_CTSTL_MASK         (0x3F << 10)
+#define MXC_UARTUCR4_INVR               0x0200
+#define MXC_UARTUCR4_ENIRI              0x0100
+#define MXC_UARTUCR4_REF16              0x0040
+#define MXC_UARTUCR4_IRSC               0x0020
+#define MXC_UARTUCR4_TCEN               0x0008
+#define MXC_UARTUCR4_OREN               0x0002
+#define MXC_UARTUCR4_DREN               0x0001
+
+/* Bit definations of UFCR */
+#define MXC_UARTUFCR_RFDIV              0x0200	/* Ref freq div is set to 2 */
+#define MXC_UARTUFCR_RFDIV_OFFSET       7
+#define MXC_UARTUFCR_RFDIV_MASK         (0x7 << 7)
+#define MXC_UARTUFCR_TXTL_OFFSET        10
+#define MXC_UARTUFCR_DCEDTE             0x0040
+
+/* Bit definations of URXD */
+#define MXC_UARTURXD_ERR        0x4000
+#define MXC_UARTURXD_OVRRUN     0x2000
+#define MXC_UARTURXD_FRMERR     0x1000
+#define MXC_UARTURXD_BRK        0x0800
+#define MXC_UARTURXD_PRERR      0x0400
+
+/* Bit definations of USR1 */
+#define MXC_UARTUSR1_PARITYERR  0x8000
+#define MXC_UARTUSR1_RTSS       0x4000
+#define MXC_UARTUSR1_TRDY       0x2000
+#define MXC_UARTUSR1_RTSD       0x1000
+#define MXC_UARTUSR1_FRAMERR    0x0400
+#define MXC_UARTUSR1_RRDY       0x0200
+#define MXC_UARTUSR1_AGTIM      0x0100
+#define MXC_UARTUSR1_DTRD       0x0080
+#define MXC_UARTUSR1_AWAKE      0x0010
+
+/* Bit definations of USR2 */
+#define MXC_UARTUSR2_TXFE       0x4000
+#define MXC_UARTUSR2_IDLE       0x1000
+#define MXC_UARTUSR2_RIDELT     0x0400
+#define MXC_UARTUSR2_RIIN       0x0200
+#define MXC_UARTUSR2_DCDDELT    0x0040
+#define MXC_UARTUSR2_DCDIN      0x0020
+#define MXC_UARTUSR2_TXDC       0x0008
+#define MXC_UARTUSR2_ORE        0x0002
+#define MXC_UARTUSR2_RDR        0x0001
+
+/* Bit definations of UTS */
+#define MXC_UARTUTS_LOOP        0x1000
+
+#endif				/* __MXC_UART_REG_H__ */
diff --git a/drivers/serial/mxs-auart.c b/drivers/serial/mxs-auart.c
new file mode 100644
index 000000000000..63d7d9128efc
--- /dev/null
+++ b/drivers/serial/mxs-auart.c
@@ -0,0 +1,1108 @@
+/*
+ * Freescale STMP37XX/STMP378X Application UART driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
+#include <mach/device.h>
+#include <mach/dmaengine.h>
+
+#include "regs-uartapp.h"
+
+#define MXS_AUART_MAJOR	242
+#define MXS_AUART_RX_THRESHOLD 16
+
+static struct uart_driver auart_driver;
+
+struct mxs_auart_port {
+	struct uart_port port;
+
+	unsigned int flags;
+#define MXS_AUART_PORT_OPEN	0x80000000
+#define MXS_AUART_PORT_DMA_MODE	0x80000000
+	unsigned int ctrl;
+
+	unsigned int irq[3];
+
+	struct clk *clk;
+	struct device *dev;
+	unsigned int dma_rx_chan;
+	unsigned int dma_tx_chan;
+	unsigned int dma_rx_buffer_size;
+	struct list_head rx_done;
+	struct list_head free;
+	struct mxs_dma_desc *tx;
+	struct tasklet_struct rx_task;
+};
+
+static void mxs_auart_stop_tx(struct uart_port *u);
+static void mxs_auart_submit_tx(struct mxs_auart_port *s, int size);
+static void mxs_auart_submit_rx(struct mxs_auart_port *s);
+
+static inline struct mxs_auart_port *to_auart_port(struct uart_port *u)
+{
+	return container_of(u, struct mxs_auart_port, port);
+}
+
+static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
+{
+	struct circ_buf *xmit = &s->port.info->xmit;
+
+	if (s->flags & MXS_AUART_PORT_DMA_MODE) {
+		int i = 0, size;
+		char *buffer = s->tx->buffer;
+
+		if (mxs_dma_desc_pending(s->tx))
+			return;
+		while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
+			if (i >= PAGE_SIZE)
+				break;
+			if (s->port.x_char) {
+				buffer[i++] = s->port.x_char;
+				s->port.x_char = 0;
+				continue;
+			}
+			size = min_t(u32, PAGE_SIZE - i,
+				     CIRC_CNT_TO_END(xmit->head,
+						     xmit->tail,
+						     UART_XMIT_SIZE));
+			memcpy(buffer + i, xmit->buf + xmit->tail, size);
+			xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
+			if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+				uart_write_wakeup(&s->port);
+			i += size;
+		}
+		if (i)
+			mxs_auart_submit_tx(s, i);
+		else {
+			if (uart_tx_stopped(&s->port))
+				mxs_auart_stop_tx(&s->port);
+		}
+		return;
+	}
+
+	while (!(__raw_readl(s->port.membase + HW_UARTAPP_STAT) &
+		 BM_UARTAPP_STAT_TXFF)) {
+		if (s->port.x_char) {
+			__raw_writel(s->port.x_char,
+				     s->port.membase + HW_UARTAPP_DATA);
+			s->port.x_char = 0;
+			continue;
+		}
+		if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
+			__raw_writel(xmit->buf[xmit->tail],
+				     s->port.membase + HW_UARTAPP_DATA);
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+				uart_write_wakeup(&s->port);
+		} else
+			break;
+	}
+	if (uart_circ_empty(&(s->port.info->xmit)))
+		__raw_writel(BM_UARTAPP_INTR_TXIEN,
+			     s->port.membase + HW_UARTAPP_INTR_CLR);
+	else
+		__raw_writel(BM_UARTAPP_INTR_TXIEN,
+			     s->port.membase + HW_UARTAPP_INTR_SET);
+
+	if (uart_tx_stopped(&s->port))
+		mxs_auart_stop_tx(&s->port);
+}
+
+static inline unsigned int
+mxs_auart_rx_char(struct mxs_auart_port *s, unsigned int stat, u8 c)
+{
+	int flag;
+
+	flag = TTY_NORMAL;
+	if (stat & BM_UARTAPP_STAT_BERR) {
+		stat &= ~BM_UARTAPP_STAT_BERR;
+		s->port.icount.brk++;
+		if (uart_handle_break(&s->port))
+			return stat;
+		flag = TTY_BREAK;
+	} else if (stat & BM_UARTAPP_STAT_PERR) {
+		stat &= ~BM_UARTAPP_STAT_PERR;
+		s->port.icount.parity++;
+		flag = TTY_PARITY;
+	} else if (stat & BM_UARTAPP_STAT_FERR) {
+		stat &= ~BM_UARTAPP_STAT_FERR;
+		s->port.icount.frame++;
+		flag = TTY_FRAME;
+	}
+
+	if (stat & BM_UARTAPP_STAT_OERR)
+		s->port.icount.overrun++;
+
+	if (uart_handle_sysrq_char(&s->port, c))
+		return stat;
+
+	uart_insert_char(&s->port, stat, BM_UARTAPP_STAT_OERR, c, flag);
+	return stat;
+}
+
+static void mxs_auart_rx_chars(struct mxs_auart_port *s)
+{
+	u8 c;
+	struct tty_struct *tty = s->port.info->port.tty;
+	u32 stat = 0;
+
+	if (s->flags & MXS_AUART_PORT_DMA_MODE) {
+		int i, count;
+		struct list_head *p, *q;
+		LIST_HEAD(list);
+		struct mxs_dma_desc *pdesc;
+		mxs_dma_cooked(s->dma_rx_chan, &list);
+		stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT);
+		list_for_each_safe(p, q, &list) {
+			u8 *buffer;
+			list_del(p);
+			pdesc = list_entry(p, struct mxs_dma_desc, node);
+			count = stat & BM_UARTAPP_STAT_RXCOUNT;
+			buffer = pdesc->buffer;
+			for (i = 0; i < count; i++)
+				stat = mxs_auart_rx_char(s, stat, buffer[i]);
+			list_add(p, &s->free);
+			stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT);
+		}
+		mxs_auart_submit_rx(s);
+		goto out;
+	}
+	for (;;) {
+		stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT);
+		if (stat & BM_UARTAPP_STAT_RXFE)
+			break;
+		c = __raw_readl(s->port.membase + HW_UARTAPP_DATA);
+		stat = mxs_auart_rx_char(s, stat, c);
+		__raw_writel(stat, s->port.membase + HW_UARTAPP_STAT);
+	}
+out:
+	__raw_writel(stat, s->port.membase + HW_UARTAPP_STAT);
+	tty_flip_buffer_push(tty);
+}
+
+/* Allocate and initialize rx and tx DMA chains */
+static int mxs_auart_dma_init(struct mxs_auart_port *s)
+{
+	int ret, i;
+	struct list_head *p, *n;
+	struct mxs_dma_desc *pdesc;
+
+	ret = mxs_dma_request(s->dma_rx_chan, s->dev, dev_name(s->dev));
+	if (ret)
+		goto fail_get_dma_rx;
+	ret = mxs_dma_request(s->dma_tx_chan, s->dev, dev_name(s->dev));
+	if (ret)
+		goto fail_get_dma_tx;
+	ret = -ENOMEM;
+	INIT_LIST_HEAD(&s->rx_done);
+	INIT_LIST_HEAD(&s->free);
+	s->tx = NULL;
+
+
+	for (i = 0; i < 5; i++) {
+		pdesc = mxs_dma_alloc_desc();
+		if (pdesc == NULL || IS_ERR(pdesc))
+			goto fail_alloc_desc;
+
+		if (s->tx == NULL) {
+			pdesc->buffer = dma_alloc_coherent(s->dev, PAGE_SIZE,
+						   &pdesc->cmd.address,
+						   GFP_DMA);
+			if (pdesc->buffer == NULL)
+				goto fail_alloc_desc;
+			s->tx = pdesc;
+		} else {
+			pdesc->buffer = dma_alloc_coherent(s->dev,
+						s->dma_rx_buffer_size,
+						&pdesc->cmd.address,
+						GFP_DMA);
+			if (pdesc->buffer == NULL)
+				goto fail_alloc_desc;
+			list_add_tail(&pdesc->node, &s->free);
+		}
+	}
+	/*
+	   Tell DMA to select UART.
+	   Both DMA channels are shared between app UART and IrDA.
+	   Target id of 0 means UART, 1 means IrDA
+	 */
+	mxs_dma_set_target(s->dma_rx_chan, 0);
+	mxs_dma_set_target(s->dma_tx_chan, 0);
+
+	mxs_dma_enable_irq(s->dma_rx_chan, 1);
+	mxs_dma_enable_irq(s->dma_tx_chan, 1);
+
+	return 0;
+fail_alloc_desc:
+	if (s->tx) {
+		if (s->tx->buffer)
+			dma_free_coherent(s->dev,
+					  PAGE_SIZE,
+					  s->tx->buffer,
+					  s->tx->cmd.address);
+		s->tx->buffer = NULL;
+		mxs_dma_free_desc(s->tx);
+		s->tx = NULL;
+	}
+	list_for_each_safe(p, n, &s->free) {
+		list_del(p);
+		pdesc = list_entry(p, struct mxs_dma_desc, node);
+		if (pdesc->buffer)
+			dma_free_coherent(s->dev,
+					  s->dma_rx_buffer_size,
+					  pdesc->buffer,
+					  pdesc->cmd.address);
+		pdesc->buffer = NULL;
+		mxs_dma_free_desc(pdesc);
+	}
+	mxs_dma_release(s->dma_tx_chan, s->dev);
+fail_get_dma_tx:
+	mxs_dma_release(s->dma_rx_chan, s->dev);
+fail_get_dma_rx:
+	WARN_ON(ret);
+	return ret;
+}
+
+static void mxs_auart_dma_exit(struct mxs_auart_port *s)
+{
+	struct list_head *p, *n;
+		LIST_HEAD(list);
+	struct mxs_dma_desc *pdesc;
+
+	mxs_dma_enable_irq(s->dma_rx_chan, 0);
+	mxs_dma_enable_irq(s->dma_tx_chan, 0);
+
+	mxs_dma_disable(s->dma_tx_chan);
+	mxs_dma_disable(s->dma_rx_chan);
+
+	mxs_dma_get_cooked(s->dma_tx_chan, &list);
+	mxs_dma_get_cooked(s->dma_rx_chan, &s->free);
+
+	mxs_dma_release(s->dma_tx_chan, s->dev);
+	mxs_dma_release(s->dma_rx_chan, s->dev);
+
+	if (s->tx) {
+		if (s->tx->buffer)
+			dma_free_coherent(s->dev,
+					  PAGE_SIZE,
+					  s->tx->buffer,
+					  s->tx->cmd.address);
+		s->tx->buffer = NULL;
+		mxs_dma_free_desc(s->tx);
+		s->tx = NULL;
+	}
+	list_for_each_safe(p, n, &s->free) {
+		list_del(p);
+		pdesc = list_entry(p, struct mxs_dma_desc, node);
+		if (pdesc->buffer)
+			dma_free_coherent(s->dev,
+					  s->dma_rx_buffer_size,
+					  pdesc->buffer,
+					  pdesc->cmd.address);
+		pdesc->buffer = NULL;
+		mxs_dma_free_desc(pdesc);
+	}
+}
+
+static void mxs_auart_submit_rx(struct mxs_auart_port *s)
+{
+	int ret;
+	unsigned int pio_value;
+	struct list_head *p, *n;
+	struct mxs_dma_desc *pdesc;
+
+	pio_value = BM_UARTAPP_CTRL0_RXTO_ENABLE |
+		     BF_UARTAPP_CTRL0_RXTIMEOUT(0x80) |
+		     BF_UARTAPP_CTRL0_XFER_COUNT(s->dma_rx_buffer_size);
+
+	list_for_each_safe(p, n, &s->free) {
+		list_del(p);
+		pdesc = list_entry(p, struct mxs_dma_desc, node);
+		pdesc->cmd.cmd.bits.bytes = s->dma_rx_buffer_size;
+		pdesc->cmd.cmd.bits.terminate_flush = 1;
+		pdesc->cmd.cmd.bits.pio_words = 1;
+		pdesc->cmd.cmd.bits.wait4end = 1;
+		pdesc->cmd.cmd.bits.dec_sem = 1;
+		pdesc->cmd.cmd.bits.irq = 1;
+		pdesc->cmd.cmd.bits.chain = 1;
+		pdesc->cmd.cmd.bits.command = DMA_WRITE;
+		pdesc->cmd.pio_words[0] = pio_value;
+		ret = mxs_dma_desc_append(s->dma_rx_chan, pdesc);
+		if (ret)
+			pr_info("%s append dma desc, %d\n", __func__, ret);
+	}
+	ret = mxs_dma_enable(s->dma_rx_chan);
+	if (ret)
+		pr_info("%s enable dma desc, %d\n", __func__, ret);
+}
+
+static irqreturn_t mxs_auart_irq_dma_rx(int irq, void *context)
+{
+	struct mxs_auart_port *s = context;
+
+	mxs_dma_ack_irq(s->dma_rx_chan);
+	mxs_auart_rx_chars(s);
+	return IRQ_HANDLED;
+}
+
+static void mxs_auart_submit_tx(struct mxs_auart_port *s, int size)
+{
+	int ret;
+	struct mxs_dma_desc *d = s->tx;
+
+	d->cmd.pio_words[0] = BF_UARTAPP_CTRL1_XFER_COUNT(size);
+	d->cmd.cmd.bits.bytes = size;
+	d->cmd.cmd.bits.pio_words = 1;
+	d->cmd.cmd.bits.wait4end = 1;
+	d->cmd.cmd.bits.dec_sem = 1;
+	d->cmd.cmd.bits.irq = 1;
+	d->cmd.cmd.bits.command = DMA_READ;
+	ret = mxs_dma_desc_append(s->dma_tx_chan, s->tx);
+	if (ret)
+		pr_info("append dma desc, %d\n", ret);
+
+	ret = mxs_dma_enable(s->dma_tx_chan);
+	if (ret)
+		pr_info("enable dma desc, %d\n", ret);
+}
+
+static irqreturn_t mxs_auart_irq_dma_tx(int irq, void *context)
+{
+	struct mxs_auart_port *s = context;
+
+	LIST_HEAD(list);
+	mxs_dma_ack_irq(s->dma_tx_chan);
+	mxs_dma_cooked(s->dma_tx_chan, &list);
+	mxs_auart_tx_chars(s);
+	return IRQ_HANDLED;
+}
+
+static int mxs_auart_request_port(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	if (!request_mem_region((u32)u->mapbase, SZ_4K, dev_name(s->dev)))
+		return -EBUSY;
+	return 0;
+
+}
+
+static int mxs_auart_verify_port(struct uart_port *u,
+				    struct serial_struct *ser)
+{
+	if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
+		return -EINVAL;
+	return 0;
+}
+
+static void mxs_auart_config_port(struct uart_port *u, int flags)
+{
+}
+
+static const char *mxs_auart_type(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	return dev_name(s->dev);
+}
+
+static void mxs_auart_release_port(struct uart_port *u)
+{
+	release_mem_region(u->mapbase, SZ_4K);
+}
+
+static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	u32 ctrl = __raw_readl(u->membase + HW_UARTAPP_CTRL2);
+
+	ctrl &= ~BM_UARTAPP_CTRL2_RTS;
+	if (mctrl & TIOCM_RTS)
+		ctrl |= BM_UARTAPP_CTRL2_RTS;
+	s->ctrl = mctrl;
+	__raw_writel(ctrl, u->membase + HW_UARTAPP_CTRL2);
+}
+
+static u32 mxs_auart_get_mctrl(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+	u32 stat = __raw_readl(u->membase + HW_UARTAPP_STAT);
+	int ctrl2 = __raw_readl(u->membase + HW_UARTAPP_CTRL2);
+	u32 mctrl = s->ctrl;
+
+	mctrl &= ~TIOCM_CTS;
+	if (stat & BM_UARTAPP_STAT_CTS)
+		mctrl |= TIOCM_CTS;
+
+	if (ctrl2 & BM_UARTAPP_CTRL2_RTS)
+		mctrl |= TIOCM_RTS;
+
+	return mctrl;
+}
+
+static void mxs_auart_settermios(struct uart_port *u,
+				 struct ktermios *termios,
+				 struct ktermios *old)
+{
+	u32 bm, ctrl, ctrl2, div;
+	unsigned int cflag, baud;
+
+	if (termios == NULL) {
+		printk(KERN_ERR "Empty ktermios setting:!\n");
+		return;
+	}
+
+	cflag = termios->c_cflag;
+
+	ctrl = BM_UARTAPP_LINECTRL_FEN;
+	ctrl2 = __raw_readl(u->membase + HW_UARTAPP_CTRL2);
+
+	/* byte size */
+	switch (cflag & CSIZE) {
+	case CS5:
+		bm = 0;
+		break;
+	case CS6:
+		bm = 1;
+		break;
+	case CS7:
+		bm = 2;
+		break;
+	case CS8:
+		bm = 3;
+		break;
+	default:
+		return;
+	}
+
+	ctrl |= BF_UARTAPP_LINECTRL_WLEN(bm);
+
+	/* parity */
+	if (cflag & PARENB) {
+		ctrl |= BM_UARTAPP_LINECTRL_PEN;
+		if ((cflag & PARODD) == 0)
+			ctrl |= BM_UARTAPP_LINECTRL_EPS;
+	}
+
+	/* figure out the stop bits requested */
+	if (cflag & CSTOPB)
+		ctrl |= BM_UARTAPP_LINECTRL_STP2;
+
+	/* figure out the hardware flow control settings */
+	if (cflag & CRTSCTS)
+		ctrl2 |= BM_UARTAPP_CTRL2_CTSEN /* | BM_UARTAPP_CTRL2_RTSEN */ ;
+	else
+		ctrl2 &= ~BM_UARTAPP_CTRL2_CTSEN;
+
+	/* set baud rate */
+	baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
+	div = u->uartclk * 32 / baud;
+	ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
+	ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVINT(div >> 6);
+
+	if ((cflag & CREAD) != 0)
+		ctrl2 |= BM_UARTAPP_CTRL2_RXE;
+
+	__raw_writel(ctrl, u->membase + HW_UARTAPP_LINECTRL);
+	__raw_writel(ctrl2, u->membase + HW_UARTAPP_CTRL2);
+}
+
+static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
+{
+	u32 istatus, istat;
+	struct mxs_auart_port *s = context;
+	u32 stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT);
+
+	istatus = istat = __raw_readl(s->port.membase + HW_UARTAPP_INTR);
+
+	if (istat & BM_UARTAPP_INTR_CTSMIS) {
+		uart_handle_cts_change(&s->port, stat & BM_UARTAPP_STAT_CTS);
+		__raw_writel(BM_UARTAPP_INTR_CTSMIS,
+				s->port.membase + HW_UARTAPP_INTR_CLR);
+		istat &= ~BM_UARTAPP_INTR_CTSMIS;
+	}
+	if (istat & (BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS)) {
+		mxs_auart_rx_chars(s);
+		istat &= ~(BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS);
+	}
+
+	if (istat & BM_UARTAPP_INTR_TXIS) {
+		mxs_auart_tx_chars(s);
+		istat &= ~BM_UARTAPP_INTR_TXIS;
+	}
+	/* modem status interrupt bits are undefined
+	after reset,and the hardware do not support
+	DSRMIS,DCDMIS and RIMIS bit,so we should ingore
+	them when they are pending. */
+	if (istat & (BM_UARTAPP_INTR_ABDIS
+		| BM_UARTAPP_INTR_OEIS
+		| BM_UARTAPP_INTR_BEIS
+		| BM_UARTAPP_INTR_PEIS
+		| BM_UARTAPP_INTR_FEIS
+		| BM_UARTAPP_INTR_RTIS
+		| BM_UARTAPP_INTR_TXIS
+		| BM_UARTAPP_INTR_RXIS
+		| BM_UARTAPP_INTR_CTSMIS)) {
+		dev_info(s->dev, "Unhandled status %x\n", istat);
+	}
+	__raw_writel(istatus & (BM_UARTAPP_INTR_ABDIS
+		| BM_UARTAPP_INTR_OEIS
+		| BM_UARTAPP_INTR_BEIS
+		| BM_UARTAPP_INTR_PEIS
+		| BM_UARTAPP_INTR_FEIS
+		| BM_UARTAPP_INTR_RTIS
+		| BM_UARTAPP_INTR_TXIS
+		| BM_UARTAPP_INTR_RXIS
+		| BM_UARTAPP_INTR_DSRMIS
+		| BM_UARTAPP_INTR_DCDMIS
+		| BM_UARTAPP_INTR_CTSMIS
+		| BM_UARTAPP_INTR_RIMIS),
+			s->port.membase + HW_UARTAPP_INTR_CLR);
+
+	return IRQ_HANDLED;
+}
+
+static int mxs_auart_free_irqs(struct mxs_auart_port *s)
+{
+	int irqn = 0;
+
+	for (irqn = 0; irqn < ARRAY_SIZE(s->irq); irqn++)
+		free_irq(s->irq[irqn], s);
+	return 0;
+}
+
+static int mxs_auart_request_irqs(struct mxs_auart_port *s)
+{
+	int err = 0;
+
+	/*
+	 * order counts. resources should be listed in the same order
+	 */
+	irq_handler_t handlers[] = {
+		mxs_auart_irq_handle,
+		mxs_auart_irq_dma_rx,
+		mxs_auart_irq_dma_tx,
+	};
+	char *handlers_names[] = {
+		"auart internal",
+		"auart dma rx",
+		"auart dma tx",
+	};
+	int irqn;
+
+	for (irqn = 0; irqn < ARRAY_SIZE(handlers); irqn++) {
+		err = request_irq(s->irq[irqn], handlers[irqn],
+				  0, handlers_names[irqn], s);
+		if (err)
+			goto out;
+	}
+	return 0;
+out:
+	mxs_auart_free_irqs(s);
+	return err;
+}
+
+static inline void mxs_auart_reset(struct uart_port *u)
+{
+	int i;
+	unsigned int reg;
+
+	__raw_writel(BM_UARTAPP_CTRL0_SFTRST,
+		     u->membase + HW_UARTAPP_CTRL0_CLR);
+
+	for (i = 0; i < 10000; i++) {
+		reg = __raw_readl(u->membase + HW_UARTAPP_CTRL0);
+		if (!(reg & BM_UARTAPP_CTRL0_SFTRST))
+			break;
+		udelay(3);
+	}
+
+	__raw_writel(BM_UARTAPP_CTRL0_CLKGATE,
+		     u->membase + HW_UARTAPP_CTRL0_CLR);
+}
+
+static int mxs_auart_startup(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	mxs_auart_reset(u);
+
+	__raw_writel(BM_UARTAPP_CTRL2_UARTEN,
+		     s->port.membase + HW_UARTAPP_CTRL2_SET);
+
+	/* Enable the Application UART DMA bits. */
+	if (s->flags & MXS_AUART_PORT_DMA_MODE) {
+		int ret;
+		ret = mxs_auart_dma_init(s);
+		if (ret) {
+			__raw_writel(BM_UARTAPP_CTRL2_UARTEN,
+				     s->port.membase + HW_UARTAPP_CTRL2_CLR);
+			return ret;
+		}
+		__raw_writel(BM_UARTAPP_CTRL2_TXDMAE | BM_UARTAPP_CTRL2_RXDMAE
+			      | BM_UARTAPP_CTRL2_DMAONERR,
+			     s->port.membase + HW_UARTAPP_CTRL2_SET);
+		/* clear any pending interrupts */
+		__raw_writel(0, s->port.membase + HW_UARTAPP_INTR);
+
+		/* reset all dma channels */
+		mxs_dma_reset(s->dma_tx_chan);
+		mxs_dma_reset(s->dma_rx_chan);
+	} else
+		__raw_writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN,
+			     s->port.membase + HW_UARTAPP_INTR);
+
+	__raw_writel(BM_UARTAPP_INTR_CTSMIEN,
+		     s->port.membase + HW_UARTAPP_INTR_SET);
+
+	/*
+	 * Enable fifo so all four bytes of a DMA word are written to
+	 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
+	 */
+	__raw_writel(BM_UARTAPP_LINECTRL_FEN,
+		     s->port.membase + HW_UARTAPP_LINECTRL_SET);
+
+	if (s->flags & MXS_AUART_PORT_DMA_MODE)
+		mxs_auart_submit_rx(s);
+	return mxs_auart_request_irqs(s);
+}
+
+static void mxs_auart_shutdown(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	__raw_writel(BM_UARTAPP_CTRL0_SFTRST,
+		     s->port.membase + HW_UARTAPP_CTRL0_SET);
+
+	if (s->flags & MXS_AUART_PORT_DMA_MODE)
+		mxs_auart_dma_exit(s);
+	else
+		__raw_writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN |
+				BM_UARTAPP_INTR_CTSMIEN,
+			     s->port.membase + HW_UARTAPP_INTR_CLR);
+	mxs_auart_free_irqs(s);
+}
+
+static unsigned int mxs_auart_tx_empty(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	if (s->flags & MXS_AUART_PORT_DMA_MODE)
+		return mxs_dma_desc_pending(s->tx) ? 0 : TIOCSER_TEMT;
+
+	if (__raw_readl(u->membase + HW_UARTAPP_STAT) &
+	    BM_UARTAPP_STAT_TXFE)
+		return TIOCSER_TEMT;
+	else
+		return 0;
+}
+
+static void mxs_auart_start_tx(struct uart_port *u)
+{
+	struct mxs_auart_port *s = to_auart_port(u);
+
+	/* enable transmitter */
+	__raw_writel(BM_UARTAPP_CTRL2_TXE, u->membase + HW_UARTAPP_CTRL2_SET);
+
+	mxs_auart_tx_chars(s);
+}
+
+static void mxs_auart_stop_tx(struct uart_port *u)
+{
+	__raw_writel(BM_UARTAPP_CTRL2_TXE, u->membase + HW_UARTAPP_CTRL2_CLR);
+}
+
+static void mxs_auart_stop_rx(struct uart_port *u)
+{
+	__raw_writel(BM_UARTAPP_CTRL2_RXE, u->membase + HW_UARTAPP_CTRL2_CLR);
+}
+
+static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
+{
+	if (ctl)
+		__raw_writel(BM_UARTAPP_LINECTRL_BRK,
+			     u->membase + HW_UARTAPP_LINECTRL_SET);
+	else
+		__raw_writel(BM_UARTAPP_LINECTRL_BRK,
+			     u->membase + HW_UARTAPP_LINECTRL_CLR);
+}
+
+static void mxs_auart_enable_ms(struct uart_port *port)
+{
+	/* just empty */
+}
+
+static struct uart_ops mxs_auart_ops = {
+	.tx_empty       = mxs_auart_tx_empty,
+	.start_tx       = mxs_auart_start_tx,
+	.stop_tx	= mxs_auart_stop_tx,
+	.stop_rx	= mxs_auart_stop_rx,
+	.enable_ms      = mxs_auart_enable_ms,
+	.break_ctl      = mxs_auart_break_ctl,
+	.set_mctrl	= mxs_auart_set_mctrl,
+	.get_mctrl      = mxs_auart_get_mctrl,
+	.startup	= mxs_auart_startup,
+	.shutdown       = mxs_auart_shutdown,
+	.set_termios    = mxs_auart_settermios,
+	.type	   	= mxs_auart_type,
+	.release_port   = mxs_auart_release_port,
+	.request_port   = mxs_auart_request_port,
+	.config_port    = mxs_auart_config_port,
+	.verify_port    = mxs_auart_verify_port,
+};
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+static struct mxs_auart_port auart_port[CONFIG_MXS_AUART_PORTS] = {};
+
+static void
+auart_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct uart_port *port;
+	unsigned int status, old_cr;
+	int i;
+
+	if (co->index >	CONFIG_MXS_AUART_PORTS || co->index < 0)
+		return;
+
+	port = &auart_port[co->index].port;
+
+	/* First save the CR then disable the interrupts */
+	old_cr = __raw_readl(port->membase + HW_UARTAPP_CTRL2);
+	__raw_writel(BM_UARTAPP_CTRL2_UARTEN | BM_UARTAPP_CTRL2_TXE,
+		     port->membase + HW_UARTAPP_CTRL2_SET);
+
+	/* Now, do each character */
+	for (i = 0; i < count; i++) {
+		do {
+			status = __raw_readl(port->membase + HW_UARTAPP_STAT);
+		} while (status & BM_UARTAPP_STAT_TXFF);
+
+		__raw_writel(s[i], port->membase + HW_UARTAPP_DATA);
+		if (s[i] == '\n') {
+			do {
+				status = __raw_readl(port->membase +
+						     HW_UARTAPP_STAT);
+			} while (status & BM_UARTAPP_STAT_TXFF);
+			__raw_writel('\r', port->membase + HW_UARTAPP_DATA);
+		}
+	}
+
+	/*
+	 *      Finally, wait for transmitter to become empty
+	 *      and restore the TCR
+	 */
+	do {
+		status = __raw_readl(port->membase + HW_UARTAPP_STAT);
+	} while (status & BM_UARTAPP_STAT_BUSY);
+	__raw_writel(old_cr, port->membase + HW_UARTAPP_CTRL2);
+}
+
+static void __init
+auart_console_get_options(struct uart_port *port, int *baud,
+			  int *parity, int *bits)
+{
+	if (__raw_readl(port->membase + HW_UARTAPP_CTRL2)
+				& BM_UARTAPP_CTRL2_UARTEN) {
+		unsigned int lcr_h, quot;
+		lcr_h = __raw_readl(port->membase + HW_UARTAPP_LINECTRL);
+
+		*parity = 'n';
+		if (lcr_h & BM_UARTAPP_LINECTRL_PEN) {
+			if (lcr_h & BM_UARTAPP_LINECTRL_EPS)
+				*parity = 'e';
+			else
+				*parity = 'o';
+		}
+
+		if ((lcr_h & BM_UARTAPP_LINECTRL_WLEN)
+				== BF_UARTAPP_LINECTRL_WLEN(2))
+			*bits = 7;
+		else
+			*bits = 8;
+
+		quot = (((__raw_readl(port->membase + HW_UARTAPP_LINECTRL)
+				& BM_UARTAPP_LINECTRL_BAUD_DIVINT))
+				    >> (BP_UARTAPP_LINECTRL_BAUD_DIVINT - 6))
+			| (((__raw_readl(port->membase + HW_UARTAPP_LINECTRL)
+				& BM_UARTAPP_LINECTRL_BAUD_DIVFRAC))
+					>> BP_UARTAPP_LINECTRL_BAUD_DIVFRAC);
+		if (quot == 0)
+			quot = 1;
+		*baud = (port->uartclk << 2) / quot;
+	}
+}
+
+static int __init auart_console_setup(struct console *co, char *options)
+{
+	struct mxs_auart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index > CONFIG_MXS_AUART_PORTS || co->index < 0)
+		return -EINVAL;
+
+	port = &auart_port[co->index].port;
+
+	if (port->port.membase == 0) {
+		if (cpu_is_mx23()) {
+			if (co->index == 1) {
+				port->port.membase = IO_ADDRESS(0x8006C000);
+				port->port.mapbase = 0x8006C000;
+			} else {
+				port->port.membase = IO_ADDRESS(0x8006E000);
+				port->port.mapbase = 0x8006E000;
+			}
+		}
+
+		port->port.fifosize = 16;
+		port->port.ops = &mxs_auart_ops;
+		port->port.flags = ASYNC_BOOT_AUTOCONF;
+		port->port.line = 0;
+	}
+	mxs_auart_reset(port);
+
+	__raw_writel(BM_UARTAPP_CTRL2_UARTEN,
+		port->port.membase + HW_UARTAPP_CTRL2_SET);
+
+	if (port->clk == NULL || IS_ERR(port->clk)) {
+		port->clk = clk_get(NULL, "uart");
+		if (port->clk == NULL || IS_ERR(port->clk))
+			return -ENODEV;
+		port->port.uartclk = clk_get_rate(port->clk);
+	}
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		auart_console_get_options(port, &baud, &parity, &bits);
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console auart_console = {
+	.name = "ttySP",
+	.write = auart_console_write,
+	.device = uart_console_device,
+	.setup = auart_console_setup,
+	.flags = CON_PRINTBUFFER,
+	.index = -1,
+	.data = &auart_driver,
+};
+
+#ifdef CONFIG_MXS_EARLY_CONSOLE
+static int __init auart_console_init(void)
+{
+	register_console(&auart_console);
+	return 0;
+}
+
+console_initcall(auart_console_init);
+#endif
+
+#endif
+static struct uart_driver auart_driver = {
+	.owner = THIS_MODULE,
+	.driver_name = "auart",
+	.dev_name = "ttySP",
+	.major = MXS_AUART_MAJOR,
+	.minor = 0,
+	.nr = CONFIG_MXS_AUART_PORTS,
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+	.cons = &auart_console,
+#endif
+};
+
+static int __devinit mxs_auart_probe(struct platform_device *pdev)
+{
+	struct mxs_auart_plat_data *plat;
+	struct mxs_auart_port *s;
+	u32 version;
+	int i, ret = 0;
+	struct resource *r;
+
+	s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
+	if (!s) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	plat = pdev->dev.platform_data;
+	if (plat == NULL) {
+		ret = -ENOMEM;
+		goto out_free;
+	}
+
+	if (plat && plat->clk)
+		s->clk = clk_get(NULL, plat->clk);
+	else
+		s->clk = clk_get(NULL, "uart");
+	if (IS_ERR(s->clk)) {
+		ret = PTR_ERR(s->clk);
+		goto out_free;
+	}
+
+	clk_enable(s->clk);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		ret = -ENXIO;
+		goto out_free_clk;
+	}
+	s->port.mapbase = r->start;
+	s->port.membase = (void __iomem *)IO_ADDRESS(r->start);
+	s->port.ops = &mxs_auart_ops;
+	s->port.iotype = UPIO_MEM;
+	s->port.line = pdev->id < 0 ? 0 : pdev->id;
+	s->port.fifosize = plat->fifo_size;
+	s->port.timeout = plat->timeout ? plat->timeout : (HZ / 10);
+	s->port.uartclk = clk_get_rate(s->clk);
+	s->port.type = PORT_IMX;
+	s->port.dev = s->dev = get_device(&pdev->dev);
+
+	s->flags = plat->dma_mode ? MXS_AUART_PORT_DMA_MODE : 0;
+	s->ctrl = 0;
+	s->dma_rx_buffer_size = plat->dma_rx_buffer_size;
+
+	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
+		s->irq[i] = platform_get_irq(pdev, i);
+		if (s->irq[i] < 0) {
+			ret = s->irq[i];
+			goto out_free_clk;
+		}
+	}
+	s->port.irq = s->irq[0];
+
+	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!r) {
+		ret = -ENXIO;
+		goto out_free_clk;
+	}
+	s->dma_rx_chan = r->start;
+
+	r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+	if (!r) {
+		ret = -ENXIO;
+		goto out_free_clk;
+	}
+	s->dma_tx_chan = r->start;
+
+	platform_set_drvdata(pdev, s);
+
+	device_init_wakeup(&pdev->dev, 1);
+
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+	memcpy(&auart_port[pdev->id], s, sizeof(struct mxs_auart_port));
+#endif
+
+	ret = uart_add_one_port(&auart_driver, &s->port);
+	if (ret)
+		goto out_free_clk;
+
+	version = __raw_readl(s->port.membase + HW_UARTAPP_VERSION);
+	printk(KERN_INFO "Found APPUART %d.%d.%d\n",
+	       (version >> 24) & 0xFF,
+	       (version >> 16) & 0xFF, version & 0xFFFF);
+	return 0;
+
+out_free_clk:
+	if (!IS_ERR(s->clk))
+		clk_put(s->clk);
+out_free:
+	kfree(s);
+out:
+	return ret;
+}
+
+static int __devexit mxs_auart_remove(struct platform_device *pdev)
+{
+	struct mxs_auart_port *s;
+
+	s = platform_get_drvdata(pdev);
+	if (s) {
+		put_device(s->dev);
+		clk_disable(s->clk);
+		clk_put(s->clk);
+		uart_remove_one_port(&auart_driver, &s->port);
+		kfree(s);
+	}
+	return 0;
+}
+
+static struct platform_driver mxs_auart_driver = {
+	.probe = mxs_auart_probe,
+	.remove = __devexit_p(mxs_auart_remove),
+	.driver = {
+		.name = "mxs-auart",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init mxs_auart_init(void)
+{
+	int r;
+
+	r = uart_register_driver(&auart_driver);
+	if (r)
+		goto out;
+	r = platform_driver_register(&mxs_auart_driver);
+	if (r)
+		goto out_err;
+	return 0;
+out_err:
+	uart_unregister_driver(&auart_driver);
+out:
+	return r;
+}
+
+static void __exit mxs_auart_exit(void)
+{
+	platform_driver_unregister(&mxs_auart_driver);
+	uart_unregister_driver(&auart_driver);
+}
+
+module_init(mxs_auart_init)
+module_exit(mxs_auart_exit)
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Freescale MXS application uart driver");
diff --git a/drivers/serial/mxs-duart.c b/drivers/serial/mxs-duart.c
new file mode 100644
index 000000000000..171b8628faee
--- /dev/null
+++ b/drivers/serial/mxs-duart.c
@@ -0,0 +1,803 @@
+/*
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#if defined(CONFIG_SERIAL_MXS_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/device.h>
+#include "regs-duart.h"
+
+/* treated as variable unless submitted to open-source */
+#define PORT_DUART		100
+#define SERIAL_DUART_MAJOR	204
+#define SERIAL_DUART_MINOR	16
+#define SERIAL_RX_LIMIT		256
+#define ISR_PASS_LIMIT		256
+
+#define DUART_DEVID		"DebugUART"
+
+static int force_cd = 1;
+static struct uart_driver duart_drv;
+
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct duart_port {
+	struct uart_port port;
+	struct clk *clk;
+	unsigned int im;	/* interrupt mask */
+	unsigned int old_status;
+	int suspended;
+};
+
+static void duart_stop_tx(struct uart_port *port)
+{
+	struct duart_port *dp = container_of(port, struct duart_port, port);
+
+	dp->im &= ~BM_UARTDBGIMSC_TXIM;
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+}
+
+static void duart_start_tx(struct uart_port *port)
+{
+	struct duart_port *dp = container_of(port, struct duart_port, port);
+
+	dp->im |= BM_UARTDBGIMSC_TXIM;
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+}
+
+static void duart_stop_rx(struct uart_port *port)
+{
+	struct duart_port *dp = container_of(port, struct duart_port, port);
+
+	dp->im &= ~(BM_UARTDBGIMSC_OEIM | BM_UARTDBGIMSC_BEIM |
+		    BM_UARTDBGIMSC_PEIM | BM_UARTDBGIMSC_FEIM |
+		    BM_UARTDBGIMSC_RTIM | BM_UARTDBGIMSC_RXIM);
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+}
+
+static void duart_enable_ms(struct uart_port *port)
+{
+	struct duart_port *dp = container_of(port, struct duart_port, port);
+
+	dp->im |= BM_UARTDBGIMSC_RIMIM | BM_UARTDBGIMSC_CTSMIM |
+	    BM_UARTDBGIMSC_DCDMIM | BM_UARTDBGIMSC_DSRMIM;
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+}
+
+static void duart_rx_chars(struct duart_port *dp)
+{
+	struct tty_struct *tty = dp->port.info->port.tty;
+	unsigned int status, ch, flag, rsr, max_count = SERIAL_RX_LIMIT;
+
+	status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
+	while ((status & BM_UARTDBGFR_RXFE) == 0 && max_count--) {
+		ch = __raw_readl(dp->port.membase + HW_UARTDBGDR);
+		flag = TTY_NORMAL;
+		dp->port.icount.rx++;
+
+		/*
+		 * Note that the error handling code is
+		 * out of the main execution path
+		 */
+		rsr = __raw_readl(dp->port.membase + HW_UARTDBGRSR_ECR);
+		if (unlikely(rsr & (BM_UARTDBGRSR_ECR_OE |
+				    BM_UARTDBGRSR_ECR_BE |
+				    BM_UARTDBGRSR_ECR_PE |
+				    BM_UARTDBGRSR_ECR_FE))) {
+			if (rsr & BM_UARTDBGRSR_ECR_BE) {
+				rsr &= ~(BM_UARTDBGRSR_ECR_FE |
+					 BM_UARTDBGRSR_ECR_PE);
+				dp->port.icount.brk++;
+				if (uart_handle_break(&dp->port))
+					goto ignore_char;
+			} else if (rsr & BM_UARTDBGRSR_ECR_PE)
+				dp->port.icount.parity++;
+			else if (rsr & BM_UARTDBGRSR_ECR_FE)
+				dp->port.icount.frame++;
+			if (rsr & BM_UARTDBGRSR_ECR_OE)
+				dp->port.icount.overrun++;
+
+			rsr &= dp->port.read_status_mask;
+
+			if (rsr & BM_UARTDBGRSR_ECR_BE)
+				flag = TTY_BREAK;
+			else if (rsr & BM_UARTDBGRSR_ECR_PE)
+				flag = TTY_PARITY;
+			else if (rsr & BM_UARTDBGRSR_ECR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (uart_handle_sysrq_char(&dp->port, ch))
+			goto ignore_char;
+
+		uart_insert_char(&dp->port, rsr, BM_UARTDBGRSR_ECR_OE, ch,
+				 flag);
+
+ignore_char:
+		status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
+	}
+	tty_flip_buffer_push(tty);
+	return;
+}
+
+static void duart_tx_chars(struct duart_port *dp)
+{
+	int count;
+	struct circ_buf *xmit = &dp->port.info->xmit;
+
+	if (dp->port.x_char) {
+		__raw_writel(dp->port.x_char, dp->port.membase + HW_UARTDBGDR);
+		dp->port.icount.tx++;
+		dp->port.x_char = 0;
+		return;
+	}
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&dp->port)) {
+		duart_stop_tx(&dp->port);
+		return;
+	}
+
+	count = dp->port.fifosize >> 1;
+	do {
+		__raw_writel(xmit->buf[xmit->tail],
+			     dp->port.membase + HW_UARTDBGDR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		dp->port.icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+	} while (--count > 0);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&dp->port);
+
+	if (uart_circ_empty(xmit))
+		duart_stop_tx(&dp->port);
+}
+
+static void duart_modem_status(struct duart_port *dp)
+{
+	unsigned int status, delta;
+	status = __raw_readl(dp->port.membase + HW_UARTDBGFR) &
+	    (BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS);
+
+	delta = status ^ dp->old_status;
+	dp->old_status = status;
+
+	if (!delta)
+		return;
+
+	if (delta & BM_UARTDBGFR_DCD)
+		uart_handle_dcd_change(&dp->port, status & BM_UARTDBGFR_DCD);
+
+	if (delta & BM_UARTDBGFR_DSR)
+		dp->port.icount.dsr++;
+
+	if (delta & BM_UARTDBGFR_CTS)
+		uart_handle_cts_change(&dp->port, status & BM_UARTDBGFR_CTS);
+
+	wake_up_interruptible(&dp->port.info->delta_msr_wait);
+}
+
+static irqreturn_t duart_int(int irq, void *dev_id)
+{
+	int handled = 0;
+	struct duart_port *dp = dev_id;
+	unsigned int status, pass_counter = ISR_PASS_LIMIT;
+
+	spin_lock(&dp->port.lock);
+
+	status = __raw_readl(dp->port.membase + HW_UARTDBGMIS);
+	while (status) {
+		handled = 1;
+
+		__raw_writel(status & ~(BM_UARTDBGMIS_TXMIS |
+					BM_UARTDBGMIS_RTMIS |
+					BM_UARTDBGMIS_RXMIS),
+			     dp->port.membase + HW_UARTDBGICR);
+
+		if (status & (BM_UARTDBGMIS_RTMIS | BM_UARTDBGMIS_RXMIS))
+			duart_rx_chars(dp);
+		if (status & (BM_UARTDBGMIS_DSRMMIS |
+			      BM_UARTDBGMIS_DCDMMIS |
+			      BM_UARTDBGMIS_CTSMMIS | BM_UARTDBGMIS_RIMMIS))
+			duart_modem_status(dp);
+		if (status & BM_UARTDBGMIS_TXMIS)
+			duart_tx_chars(dp);
+
+		if (pass_counter-- == 0)
+			break;
+
+		status = __raw_readl(dp->port.membase + HW_UARTDBGMIS);
+	};
+
+	spin_unlock(&dp->port.lock);
+
+	return IRQ_RETVAL(handled);
+}
+
+static unsigned int duart_tx_empty(struct uart_port *port)
+{
+	struct duart_port *dp = (struct duart_port *)port;
+	unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
+	return status & (BM_UARTDBGFR_BUSY | BM_UARTDBGFR_TXFF) ?
+	    0 : TIOCSER_TEMT;
+}
+
+static unsigned int duart_get_mctrl(struct uart_port *port)
+{
+	unsigned int result = 0;
+	struct duart_port *dp = (struct duart_port *)port;
+	unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR);
+
+#define TEST_AND_SET_BIT(uartbit, tiocmbit)	do { \
+		if (status & uartbit)		\
+			result |= tiocmbit;	\
+	} while (0)
+
+	TEST_AND_SET_BIT(BM_UARTDBGFR_DCD, TIOCM_CAR);
+	TEST_AND_SET_BIT(BM_UARTDBGFR_DSR, TIOCM_DSR);
+	TEST_AND_SET_BIT(BM_UARTDBGFR_CTS, TIOCM_CTS);
+	TEST_AND_SET_BIT(BM_UARTDBGFR_RI, TIOCM_RNG);
+#undef TEST_AND_SET_BIT
+	if (force_cd)
+		result |= TIOCM_CAR;
+	return result;
+}
+
+static void duart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	unsigned int cr;
+	struct duart_port *dp = (struct duart_port *)port;
+
+	cr = __raw_readl(dp->port.membase + HW_UARTDBGCR);
+
+#define	TEST_AND_SET_BIT(tiocmbit, uartbit)	do { \
+		if (mctrl & tiocmbit)		\
+			cr |= uartbit;		\
+		else				\
+			cr &= ~uartbit;		\
+	} while (0)
+
+	TEST_AND_SET_BIT(TIOCM_RTS, BM_UARTDBGCR_RTS);
+	TEST_AND_SET_BIT(TIOCM_DTR, BM_UARTDBGCR_DTR);
+	TEST_AND_SET_BIT(TIOCM_OUT1, BM_UARTDBGCR_OUT1);
+	TEST_AND_SET_BIT(TIOCM_OUT2, BM_UARTDBGCR_OUT2);
+	TEST_AND_SET_BIT(TIOCM_LOOP, BM_UARTDBGCR_LBE);
+#undef TEST_AND_SET_BIT
+
+	__raw_writel(cr, dp->port.membase + HW_UARTDBGCR);
+}
+
+static void duart_break_ctl(struct uart_port *port, int break_state)
+{
+	unsigned long flags;
+	unsigned int lcr_h;
+	struct duart_port *dp = (struct duart_port *)port;
+
+	spin_lock_irqsave(&dp->port.lock, flags);
+	lcr_h = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
+	if (break_state == -1)
+		lcr_h |= BM_UARTDBGLCR_H_BRK;
+	else
+		lcr_h &= ~BM_UARTDBGLCR_H_BRK;
+	__raw_writel(lcr_h, dp->port.membase + HW_UARTDBGLCR_H);
+	spin_unlock_irqrestore(&dp->port.lock, flags);
+}
+
+static int duart_startup(struct uart_port *port)
+{
+	u32 cr, lcr;
+	int retval;
+	struct duart_port *dp = (struct duart_port *)port;
+
+	/*
+	 * Allocate the IRQ
+	 */
+	retval = request_irq(dp->port.irq, duart_int, 0, DUART_DEVID, dp);
+	if (retval)
+		return retval;
+
+	/* wake up the UART */
+	__raw_writel(0, dp->port.membase + HW_UARTDBGDR);
+
+	__raw_writel(BF_UARTDBGIFLS_TXIFLSEL(BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF)
+		     |
+		     BF_UARTDBGIFLS_RXIFLSEL(BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF),
+		     dp->port.membase + HW_UARTDBGIFLS);
+
+	/*
+	 * Provoke TX FIFO interrupt into asserting.
+	 */
+	cr = BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_RXE | BM_UARTDBGCR_TXE;
+	__raw_writel(cr, dp->port.membase + HW_UARTDBGCR);
+
+	lcr = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
+	lcr |= BM_UARTDBGLCR_H_FEN;
+	__raw_writel(lcr, dp->port.membase + HW_UARTDBGLCR_H);
+
+	/*
+	 * initialise the old status of the modem signals
+	 */
+	dp->old_status = __raw_readl(dp->port.membase + HW_UARTDBGFR) &
+	    (BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS);
+	/*
+	 * Finally, enable interrupts
+	 */
+	dp->im = BM_UARTDBGIMSC_RXIM | BM_UARTDBGIMSC_RTIM;
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+
+	return 0;
+}
+
+static void duart_shutdown(struct uart_port *port)
+{
+	unsigned long flags;
+	unsigned int val;
+	struct duart_port *dp = (struct duart_port *)port;
+
+	/*
+	 * disable all interrupts
+	 */
+	spin_lock_irqsave(&dp->port.lock, flags);
+	dp->im = 0;
+	__raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC);
+	__raw_writel(0xffff, dp->port.membase + HW_UARTDBGICR);
+	spin_unlock_irqrestore(&dp->port.lock, flags);
+
+	free_irq(dp->port.irq, dp);
+
+	/*
+	 * disable the port
+	 */
+	__raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE,
+		     dp->port.membase + HW_UARTDBGCR);
+	/*
+	 * disable break condition and fifos
+	 */
+	val = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H);
+	val &= ~(BM_UARTDBGLCR_H_BRK | BM_UARTDBGLCR_H_FEN);
+	__raw_writel(val, dp->port.membase + HW_UARTDBGLCR_H);
+}
+
+static void
+duart_set_termios(struct uart_port *port, struct ktermios *termios,
+		  struct ktermios *old)
+{
+	unsigned int lcr_h, old_cr;
+	unsigned long flags;
+	unsigned int baud, quot;
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
+	quot = (port->uartclk << 2) / baud;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr_h = BF_UARTDBGLCR_H_WLEN(0);
+		break;
+	case CS6:
+		lcr_h = BF_UARTDBGLCR_H_WLEN(1);
+		break;
+	case CS7:
+		lcr_h = BF_UARTDBGLCR_H_WLEN(2);
+		break;
+	default:		/* CS8 */
+		lcr_h = BF_UARTDBGLCR_H_WLEN(3);
+		break;
+	}
+	if (termios->c_cflag & CSTOPB)
+		lcr_h |= BM_UARTDBGLCR_H_STP2;
+	if (termios->c_cflag & PARENB) {
+		lcr_h |= BM_UARTDBGLCR_H_PEN;
+		if (!(termios->c_cflag & PARODD))
+			lcr_h |= BM_UARTDBGLCR_H_EPS;
+	}
+	lcr_h |= BM_UARTDBGLCR_H_FEN;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = BM_UARTDBGRSR_ECR_OE;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= BM_UARTDBGRSR_ECR_FE |
+		    BM_UARTDBGRSR_ECR_PE;
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= BM_UARTDBGRSR_ECR_BE;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= BM_UARTDBGRSR_ECR_FE |
+		    BM_UARTDBGRSR_ECR_PE;
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= BM_UARTDBGRSR_ECR_BE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= BM_UARTDBGRSR_ECR_OE;
+	}
+
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		duart_enable_ms(port);
+
+	/* first, disable everything */
+	old_cr = __raw_readl(port->membase + HW_UARTDBGCR);
+	__raw_writel(0, port->membase + HW_UARTDBGCR);
+
+	/* Set baud rate */
+	__raw_writel(quot & 0x3f, port->membase + HW_UARTDBGFBRD);
+	__raw_writel(quot >> 6, port->membase + HW_UARTDBGIBRD);
+	/*
+	 * ----------v----------v----------v----------v-----
+	 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+	 * ----------^----------^----------^----------^-----
+	 */
+	__raw_writel(lcr_h, port->membase + HW_UARTDBGLCR_H);
+	__raw_writel(old_cr, port->membase + HW_UARTDBGCR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *duart_type(struct uart_port *port)
+{
+	return port->type == PORT_DUART ? DUART_DEVID : NULL;
+}
+
+/*
+ * Release the memory region(s) being used by 'port'
+ */
+static void duart_release_port(struct uart_port *port)
+{
+	release_mem_region(port->mapbase, PAGE_SIZE);
+}
+
+/*
+ * Request the memory region(s) being used by 'port'
+ */
+static int duart_request_port(struct uart_port *port)
+{
+	return request_mem_region(port->mapbase, PAGE_SIZE, DUART_DEVID)
+	    != NULL ? 0 : -EBUSY;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void duart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_DUART;
+		duart_request_port(port);
+	}
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int duart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_DUART)
+		ret = -EINVAL;
+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
+		ret = -EINVAL;
+	if (ser->baud_base < 9600)
+		ret = -EINVAL;
+	return ret;
+}
+
+static struct uart_ops duart_pops = {
+	.tx_empty = duart_tx_empty,
+	.set_mctrl = duart_set_mctrl,
+	.get_mctrl = duart_get_mctrl,
+	.stop_tx = duart_stop_tx,
+	.start_tx = duart_start_tx,
+	.stop_rx = duart_stop_rx,
+	.enable_ms = duart_enable_ms,
+	.break_ctl = duart_break_ctl,
+	.startup = duart_startup,
+	.shutdown = duart_shutdown,
+	.set_termios = duart_set_termios,
+	.type = duart_type,
+	.release_port = duart_release_port,
+	.request_port = duart_request_port,
+	.config_port = duart_config_port,
+	.verify_port = duart_verify_port,
+};
+
+static struct duart_port duart_port = {
+	.port = {
+		 .iotype = SERIAL_IO_MEM,
+#ifdef CONFIG_MXS_EARLY_CONSOLE
+		 .membase = MXS_DEBUG_CONSOLE_VIRT,
+		 .mapbase = MXS_DEBUG_CONSOLE_PHYS,
+#endif
+		 .fifosize = 16,
+		 .ops = &duart_pops,
+		 .flags = ASYNC_BOOT_AUTOCONF,
+		 .line = 0,
+		 },
+};
+
+#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE
+
+static void
+duart_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct uart_port *port = &duart_port.port;
+	unsigned int status, old_cr;
+	int i;
+	/*
+	 *      First save the CR then disable the interrupts
+	 */
+	old_cr = __raw_readl(port->membase + HW_UARTDBGCR);
+	__raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE,
+		     port->membase + HW_UARTDBGCR);
+	/*
+	 *      Now, do each character
+	 */
+	for (i = 0; i < count; i++) {
+		do {
+			status = __raw_readl(port->membase + HW_UARTDBGFR);
+		} while (status & BM_UARTDBGFR_TXFF);
+
+		__raw_writel(s[i], port->membase + HW_UARTDBGDR);
+		if (s[i] == '\n') {
+			do {
+				status = __raw_readl(port->membase +
+						     HW_UARTDBGFR);
+			} while (status & BM_UARTDBGFR_TXFF);
+			__raw_writel('\r', port->membase + HW_UARTDBGDR);
+		}
+	}
+
+	/*
+	 *      Finally, wait for transmitter to become empty
+	 *      and restore the TCR
+	 */
+	do {
+		status = __raw_readl(port->membase + HW_UARTDBGFR);
+	} while (status & BM_UARTDBGFR_BUSY);
+	__raw_writel(old_cr, port->membase + HW_UARTDBGCR);
+}
+
+static void __init
+duart_console_get_options(struct uart_port *port, int *baud,
+			  int *parity, int *bits)
+{
+	if (__raw_readl(port->membase + HW_UARTDBGCR) & BM_UARTDBGCR_UARTEN) {
+		unsigned int lcr_h, quot;
+		lcr_h = __raw_readl(port->membase + HW_UARTDBGLCR_H);
+
+		*parity = 'n';
+		if (lcr_h & BM_UARTDBGLCR_H_PEN) {
+			if (lcr_h & BM_UARTDBGLCR_H_EPS)
+				*parity = 'e';
+			else
+				*parity = 'o';
+		}
+
+		if ((lcr_h & BM_UARTDBGLCR_H_WLEN) == BF_UARTDBGLCR_H_WLEN(2))
+			*bits = 7;
+		else
+			*bits = 8;
+
+		quot = (__raw_readl(port->membase + HW_UARTDBGFBRD) & 0x3F) |
+		    __raw_readl(port->membase + HW_UARTDBGIBRD) << 6;
+		if (quot == 0)
+			quot = 1;
+		*baud = (port->uartclk << 2) / quot;
+	}
+}
+
+static int __init duart_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index)
+		return -EINVAL;
+
+	port = &duart_port.port;
+
+	if (duart_port.clk == NULL || IS_ERR(duart_port.clk)) {
+		duart_port.clk = clk_get(NULL, "uart");
+		if (duart_port.clk == NULL || IS_ERR(duart_port.clk))
+			return -ENODEV;
+		duart_port.port.uartclk = clk_get_rate(duart_port.clk);
+	}
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		duart_console_get_options(port, &baud, &parity, &bits);
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console duart_console = {
+	.name = "ttyAM",
+	.write = duart_console_write,
+	.device = uart_console_device,
+	.setup = duart_console_setup,
+	.flags = CON_PRINTBUFFER,
+	.index = -1,
+	.data = &duart_drv,
+};
+
+#ifdef CONFIG_MXS_EARLY_CONSOLE
+static int __init duart_console_init(void)
+{
+	register_console(&duart_console);
+	return 0;
+}
+
+console_initcall(duart_console_init);
+#endif
+
+#endif
+
+static struct uart_driver duart_drv = {
+	.owner = THIS_MODULE,
+	.driver_name = "ttyAM",
+	.dev_name = "ttyAM",
+	.major = SERIAL_DUART_MAJOR,
+	.minor = SERIAL_DUART_MINOR,
+	.nr = 1,
+#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE
+	.cons = &duart_console,
+#endif
+};
+
+static int __devinit duart_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOMEM;
+	/*
+	 * Will use mapbase and membase here if !CONFIG_MXS_EARLY_CONSOLE,
+	 * or use the overridden values later if CONFIG_MXS_EARLY_CONSOLE
+	 */
+	duart_port.port.mapbase = res->start;
+	duart_port.port.membase =
+	    (unsigned char __iomem *)IO_ADDRESS(res->start);
+
+	duart_port.port.irq = platform_get_irq(pdev, 0);
+	if (duart_port.port.irq < 0)
+		return -EINVAL;
+	device_init_wakeup(&pdev->dev, 1);
+
+	duart_port.clk = clk_get(NULL, "uart");
+	if (duart_port.clk == NULL || IS_ERR(duart_port.clk))
+		return -ENODEV;
+	duart_port.suspended = 0;
+	duart_port.port.dev = &pdev->dev;
+	duart_port.port.uartclk = clk_get_rate(duart_port.clk);
+	uart_add_one_port(&duart_drv, &duart_port.port);
+	return 0;
+}
+
+static int __devexit duart_remove(struct platform_device *pdev)
+{
+	clk_put(duart_port.clk);
+	uart_remove_one_port(&duart_drv, &duart_port.port);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int duart_suspend(struct platform_device *pdev,
+		pm_message_t state)
+{
+	int ret = 0;
+	if (!duart_port.suspended) {
+		ret = uart_suspend_port(&duart_drv, &duart_port.port);
+		if (!ret)
+			duart_port.suspended = 1;
+	}
+	return ret;
+}
+
+static int duart_resume(struct platform_device *pdev,
+		pm_message_t state)
+{
+	int ret = 0;
+	if (duart_port.suspended) {
+		ret = uart_resume_port(&duart_drv, &duart_port.port);
+		if (!ret)
+			duart_port.suspended = 0;
+	}
+	return ret;
+}
+#else
+#define	duart_suspend	NULL
+#define	duart_resume	NULL
+#endif
+
+static struct platform_driver duart_driver = {
+	.probe = duart_probe,
+	.remove = __devexit_p(duart_remove),
+	.suspend = duart_suspend,
+	.resume = duart_resume,
+	.driver = {
+		   .name = "mxs-duart",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init duart_init(void)
+{
+	int ret;
+	ret = uart_register_driver(&duart_drv);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&duart_driver);
+	if (ret)
+		uart_unregister_driver(&duart_drv);
+
+	return ret;
+}
+
+static void __exit duart_exit(void)
+{
+	platform_driver_unregister(&duart_driver);
+	uart_unregister_driver(&duart_drv);
+}
+
+module_init(duart_init);
+module_exit(duart_exit);
+module_param(force_cd, int, 0644);
+MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd/Freescale Inc");
+MODULE_DESCRIPTION("i.MXS debug uart");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/regs-duart.h b/drivers/serial/regs-duart.h
new file mode 100644
index 000000000000..0b5932c79a55
--- /dev/null
+++ b/drivers/serial/regs-duart.h
@@ -0,0 +1,301 @@
+/*
+ * Freescale UARTDBG Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.21
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___UARTDBG_H
+#define __ARCH_ARM___UARTDBG_H
+
+
+#define HW_UARTDBGDR	(0x00000000)
+
+#define BP_UARTDBGDR_UNAVAILABLE	16
+#define BM_UARTDBGDR_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGDR_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
+#define BP_UARTDBGDR_RESERVED	12
+#define BM_UARTDBGDR_RESERVED	0x0000F000
+#define BF_UARTDBGDR_RESERVED(v)  \
+		(((v) << 12) & BM_UARTDBGDR_RESERVED)
+#define BM_UARTDBGDR_OE	0x00000800
+#define BM_UARTDBGDR_BE	0x00000400
+#define BM_UARTDBGDR_PE	0x00000200
+#define BM_UARTDBGDR_FE	0x00000100
+#define BP_UARTDBGDR_DATA	0
+#define BM_UARTDBGDR_DATA	0x000000FF
+#define BF_UARTDBGDR_DATA(v)  \
+		(((v) << 0) & BM_UARTDBGDR_DATA)
+
+#define HW_UARTDBGRSR_ECR	(0x00000004)
+
+#define BP_UARTDBGRSR_ECR_UNAVAILABLE	8
+#define BM_UARTDBGRSR_ECR_UNAVAILABLE	0xFFFFFF00
+#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
+		(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
+#define BP_UARTDBGRSR_ECR_EC	4
+#define BM_UARTDBGRSR_ECR_EC	0x000000F0
+#define BF_UARTDBGRSR_ECR_EC(v)  \
+		(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
+#define BM_UARTDBGRSR_ECR_OE	0x00000008
+#define BM_UARTDBGRSR_ECR_BE	0x00000004
+#define BM_UARTDBGRSR_ECR_PE	0x00000002
+#define BM_UARTDBGRSR_ECR_FE	0x00000001
+
+#define HW_UARTDBGFR	(0x00000018)
+
+#define BP_UARTDBGFR_UNAVAILABLE	16
+#define BM_UARTDBGFR_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGFR_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
+#define BP_UARTDBGFR_RESERVED	9
+#define BM_UARTDBGFR_RESERVED	0x0000FE00
+#define BF_UARTDBGFR_RESERVED(v)  \
+		(((v) << 9) & BM_UARTDBGFR_RESERVED)
+#define BM_UARTDBGFR_RI	0x00000100
+#define BM_UARTDBGFR_TXFE	0x00000080
+#define BM_UARTDBGFR_RXFF	0x00000040
+#define BM_UARTDBGFR_TXFF	0x00000020
+#define BM_UARTDBGFR_RXFE	0x00000010
+#define BM_UARTDBGFR_BUSY	0x00000008
+#define BM_UARTDBGFR_DCD	0x00000004
+#define BM_UARTDBGFR_DSR	0x00000002
+#define BM_UARTDBGFR_CTS	0x00000001
+
+#define HW_UARTDBGILPR	(0x00000020)
+
+#define BP_UARTDBGILPR_UNAVAILABLE	8
+#define BM_UARTDBGILPR_UNAVAILABLE	0xFFFFFF00
+#define BF_UARTDBGILPR_UNAVAILABLE(v) \
+		(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
+#define BP_UARTDBGILPR_ILPDVSR	0
+#define BM_UARTDBGILPR_ILPDVSR	0x000000FF
+#define BF_UARTDBGILPR_ILPDVSR(v)  \
+		(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
+
+#define HW_UARTDBGIBRD	(0x00000024)
+
+#define BP_UARTDBGIBRD_UNAVAILABLE	16
+#define BM_UARTDBGIBRD_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
+#define BP_UARTDBGIBRD_BAUD_DIVINT	0
+#define BM_UARTDBGIBRD_BAUD_DIVINT	0x0000FFFF
+#define BF_UARTDBGIBRD_BAUD_DIVINT(v)  \
+		(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
+
+#define HW_UARTDBGFBRD	(0x00000028)
+
+#define BP_UARTDBGFBRD_UNAVAILABLE	8
+#define BM_UARTDBGFBRD_UNAVAILABLE	0xFFFFFF00
+#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
+		(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
+#define BP_UARTDBGFBRD_RESERVED	6
+#define BM_UARTDBGFBRD_RESERVED	0x000000C0
+#define BF_UARTDBGFBRD_RESERVED(v)  \
+		(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
+#define BP_UARTDBGFBRD_BAUD_DIVFRAC	0
+#define BM_UARTDBGFBRD_BAUD_DIVFRAC	0x0000003F
+#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v)  \
+		(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
+
+#define HW_UARTDBGLCR_H	(0x0000002c)
+
+#define BP_UARTDBGLCR_H_UNAVAILABLE	16
+#define BM_UARTDBGLCR_H_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
+#define BP_UARTDBGLCR_H_RESERVED	8
+#define BM_UARTDBGLCR_H_RESERVED	0x0000FF00
+#define BF_UARTDBGLCR_H_RESERVED(v)  \
+		(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
+#define BM_UARTDBGLCR_H_SPS	0x00000080
+#define BP_UARTDBGLCR_H_WLEN	5
+#define BM_UARTDBGLCR_H_WLEN	0x00000060
+#define BF_UARTDBGLCR_H_WLEN(v)  \
+		(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
+#define BM_UARTDBGLCR_H_FEN	0x00000010
+#define BM_UARTDBGLCR_H_STP2	0x00000008
+#define BM_UARTDBGLCR_H_EPS	0x00000004
+#define BM_UARTDBGLCR_H_PEN	0x00000002
+#define BM_UARTDBGLCR_H_BRK	0x00000001
+
+#define HW_UARTDBGCR	(0x00000030)
+
+#define BP_UARTDBGCR_UNAVAILABLE	16
+#define BM_UARTDBGCR_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGCR_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
+#define BM_UARTDBGCR_CTSEN	0x00008000
+#define BM_UARTDBGCR_RTSEN	0x00004000
+#define BM_UARTDBGCR_OUT2	0x00002000
+#define BM_UARTDBGCR_OUT1	0x00001000
+#define BM_UARTDBGCR_RTS	0x00000800
+#define BM_UARTDBGCR_DTR	0x00000400
+#define BM_UARTDBGCR_RXE	0x00000200
+#define BM_UARTDBGCR_TXE	0x00000100
+#define BM_UARTDBGCR_LBE	0x00000080
+#define BP_UARTDBGCR_RESERVED	3
+#define BM_UARTDBGCR_RESERVED	0x00000078
+#define BF_UARTDBGCR_RESERVED(v)  \
+		(((v) << 3) & BM_UARTDBGCR_RESERVED)
+#define BM_UARTDBGCR_SIRLP	0x00000004
+#define BM_UARTDBGCR_SIREN	0x00000002
+#define BM_UARTDBGCR_UARTEN	0x00000001
+
+#define HW_UARTDBGIFLS	(0x00000034)
+
+#define BP_UARTDBGIFLS_UNAVAILABLE	16
+#define BM_UARTDBGIFLS_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
+#define BP_UARTDBGIFLS_RESERVED	6
+#define BM_UARTDBGIFLS_RESERVED	0x0000FFC0
+#define BF_UARTDBGIFLS_RESERVED(v)  \
+		(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
+#define BP_UARTDBGIFLS_RXIFLSEL	3
+#define BM_UARTDBGIFLS_RXIFLSEL	0x00000038
+#define BF_UARTDBGIFLS_RXIFLSEL(v)  \
+		(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT      0x0
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7       0x7
+#define BP_UARTDBGIFLS_TXIFLSEL	0
+#define BM_UARTDBGIFLS_TXIFLSEL	0x00000007
+#define BF_UARTDBGIFLS_TXIFLSEL(v)  \
+		(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT      0x0
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7       0x7
+
+#define HW_UARTDBGIMSC	(0x00000038)
+
+#define BP_UARTDBGIMSC_UNAVAILABLE	16
+#define BM_UARTDBGIMSC_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
+#define BP_UARTDBGIMSC_RESERVED	11
+#define BM_UARTDBGIMSC_RESERVED	0x0000F800
+#define BF_UARTDBGIMSC_RESERVED(v)  \
+		(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
+#define BM_UARTDBGIMSC_OEIM	0x00000400
+#define BM_UARTDBGIMSC_BEIM	0x00000200
+#define BM_UARTDBGIMSC_PEIM	0x00000100
+#define BM_UARTDBGIMSC_FEIM	0x00000080
+#define BM_UARTDBGIMSC_RTIM	0x00000040
+#define BM_UARTDBGIMSC_TXIM	0x00000020
+#define BM_UARTDBGIMSC_RXIM	0x00000010
+#define BM_UARTDBGIMSC_DSRMIM	0x00000008
+#define BM_UARTDBGIMSC_DCDMIM	0x00000004
+#define BM_UARTDBGIMSC_CTSMIM	0x00000002
+#define BM_UARTDBGIMSC_RIMIM	0x00000001
+
+#define HW_UARTDBGRIS	(0x0000003c)
+
+#define BP_UARTDBGRIS_UNAVAILABLE	16
+#define BM_UARTDBGRIS_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGRIS_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
+#define BP_UARTDBGRIS_RESERVED	11
+#define BM_UARTDBGRIS_RESERVED	0x0000F800
+#define BF_UARTDBGRIS_RESERVED(v)  \
+		(((v) << 11) & BM_UARTDBGRIS_RESERVED)
+#define BM_UARTDBGRIS_OERIS	0x00000400
+#define BM_UARTDBGRIS_BERIS	0x00000200
+#define BM_UARTDBGRIS_PERIS	0x00000100
+#define BM_UARTDBGRIS_FERIS	0x00000080
+#define BM_UARTDBGRIS_RTRIS	0x00000040
+#define BM_UARTDBGRIS_TXRIS	0x00000020
+#define BM_UARTDBGRIS_RXRIS	0x00000010
+#define BM_UARTDBGRIS_DSRRMIS	0x00000008
+#define BM_UARTDBGRIS_DCDRMIS	0x00000004
+#define BM_UARTDBGRIS_CTSRMIS	0x00000002
+#define BM_UARTDBGRIS_RIRMIS	0x00000001
+
+#define HW_UARTDBGMIS	(0x00000040)
+
+#define BP_UARTDBGMIS_UNAVAILABLE	16
+#define BM_UARTDBGMIS_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGMIS_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
+#define BP_UARTDBGMIS_RESERVED	11
+#define BM_UARTDBGMIS_RESERVED	0x0000F800
+#define BF_UARTDBGMIS_RESERVED(v)  \
+		(((v) << 11) & BM_UARTDBGMIS_RESERVED)
+#define BM_UARTDBGMIS_OEMIS	0x00000400
+#define BM_UARTDBGMIS_BEMIS	0x00000200
+#define BM_UARTDBGMIS_PEMIS	0x00000100
+#define BM_UARTDBGMIS_FEMIS	0x00000080
+#define BM_UARTDBGMIS_RTMIS	0x00000040
+#define BM_UARTDBGMIS_TXMIS	0x00000020
+#define BM_UARTDBGMIS_RXMIS	0x00000010
+#define BM_UARTDBGMIS_DSRMMIS	0x00000008
+#define BM_UARTDBGMIS_DCDMMIS	0x00000004
+#define BM_UARTDBGMIS_CTSMMIS	0x00000002
+#define BM_UARTDBGMIS_RIMMIS	0x00000001
+
+#define HW_UARTDBGICR	(0x00000044)
+
+#define BP_UARTDBGICR_UNAVAILABLE	16
+#define BM_UARTDBGICR_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGICR_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
+#define BP_UARTDBGICR_RESERVED	11
+#define BM_UARTDBGICR_RESERVED	0x0000F800
+#define BF_UARTDBGICR_RESERVED(v)  \
+		(((v) << 11) & BM_UARTDBGICR_RESERVED)
+#define BM_UARTDBGICR_OEIC	0x00000400
+#define BM_UARTDBGICR_BEIC	0x00000200
+#define BM_UARTDBGICR_PEIC	0x00000100
+#define BM_UARTDBGICR_FEIC	0x00000080
+#define BM_UARTDBGICR_RTIC	0x00000040
+#define BM_UARTDBGICR_TXIC	0x00000020
+#define BM_UARTDBGICR_RXIC	0x00000010
+#define BM_UARTDBGICR_DSRMIC	0x00000008
+#define BM_UARTDBGICR_DCDMIC	0x00000004
+#define BM_UARTDBGICR_CTSMIC	0x00000002
+#define BM_UARTDBGICR_RIMIC	0x00000001
+
+#define HW_UARTDBGDMACR	(0x00000048)
+
+#define BP_UARTDBGDMACR_UNAVAILABLE	16
+#define BM_UARTDBGDMACR_UNAVAILABLE	0xFFFF0000
+#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
+		(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
+#define BP_UARTDBGDMACR_RESERVED	3
+#define BM_UARTDBGDMACR_RESERVED	0x0000FFF8
+#define BF_UARTDBGDMACR_RESERVED(v)  \
+		(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
+#define BM_UARTDBGDMACR_DMAONERR	0x00000004
+#define BM_UARTDBGDMACR_TXDMAE	0x00000002
+#define BM_UARTDBGDMACR_RXDMAE	0x00000001
+#endif /* __ARCH_ARM___UARTDBG_H */
diff --git a/drivers/serial/regs-uartapp.h b/drivers/serial/regs-uartapp.h
new file mode 100644
index 000000000000..aad9a7866556
--- /dev/null
+++ b/drivers/serial/regs-uartapp.h
@@ -0,0 +1,307 @@
+/*
+ * Freescale UARTAPP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.42
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___UARTAPP_H
+#define __ARCH_ARM___UARTAPP_H
+
+
+#define HW_UARTAPP_CTRL0	(0x00000000)
+#define HW_UARTAPP_CTRL0_SET	(0x00000004)
+#define HW_UARTAPP_CTRL0_CLR	(0x00000008)
+#define HW_UARTAPP_CTRL0_TOG	(0x0000000c)
+
+#define BM_UARTAPP_CTRL0_SFTRST	0x80000000
+#define BM_UARTAPP_CTRL0_CLKGATE	0x40000000
+#define BM_UARTAPP_CTRL0_RUN	0x20000000
+#define BM_UARTAPP_CTRL0_RX_SOURCE	0x10000000
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE	0x08000000
+#define BP_UARTAPP_CTRL0_RXTIMEOUT	16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT	0x07FF0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)  \
+		(((v) << 16) & BM_UARTAPP_CTRL0_RXTIMEOUT)
+#define BP_UARTAPP_CTRL0_XFER_COUNT	0
+#define BM_UARTAPP_CTRL0_XFER_COUNT	0x0000FFFF
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  \
+		(((v) << 0) & BM_UARTAPP_CTRL0_XFER_COUNT)
+
+#define HW_UARTAPP_CTRL1	(0x00000010)
+#define HW_UARTAPP_CTRL1_SET	(0x00000014)
+#define HW_UARTAPP_CTRL1_CLR	(0x00000018)
+#define HW_UARTAPP_CTRL1_TOG	(0x0000001c)
+
+#define BP_UARTAPP_CTRL1_RSVD2	29
+#define BM_UARTAPP_CTRL1_RSVD2	0xE0000000
+#define BF_UARTAPP_CTRL1_RSVD2(v) \
+		(((v) << 29) & BM_UARTAPP_CTRL1_RSVD2)
+#define BM_UARTAPP_CTRL1_RUN	0x10000000
+#define BP_UARTAPP_CTRL1_RSVD1	16
+#define BM_UARTAPP_CTRL1_RSVD1	0x0FFF0000
+#define BF_UARTAPP_CTRL1_RSVD1(v)  \
+		(((v) << 16) & BM_UARTAPP_CTRL1_RSVD1)
+#define BP_UARTAPP_CTRL1_XFER_COUNT	0
+#define BM_UARTAPP_CTRL1_XFER_COUNT	0x0000FFFF
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  \
+		(((v) << 0) & BM_UARTAPP_CTRL1_XFER_COUNT)
+
+#define HW_UARTAPP_CTRL2	(0x00000020)
+#define HW_UARTAPP_CTRL2_SET	(0x00000024)
+#define HW_UARTAPP_CTRL2_CLR	(0x00000028)
+#define HW_UARTAPP_CTRL2_TOG	(0x0000002c)
+
+#define BM_UARTAPP_CTRL2_INVERT_RTS	0x80000000
+#define BM_UARTAPP_CTRL2_INVERT_CTS	0x40000000
+#define BM_UARTAPP_CTRL2_INVERT_TX	0x20000000
+#define BM_UARTAPP_CTRL2_INVERT_RX	0x10000000
+#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE	0x08000000
+#define BM_UARTAPP_CTRL2_DMAONERR	0x04000000
+#define BM_UARTAPP_CTRL2_TXDMAE	0x02000000
+#define BM_UARTAPP_CTRL2_RXDMAE	0x01000000
+#define BM_UARTAPP_CTRL2_RSVD2	0x00800000
+#define BP_UARTAPP_CTRL2_RXIFLSEL	20
+#define BM_UARTAPP_CTRL2_RXIFLSEL	0x00700000
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)  \
+		(((v) << 20) & BM_UARTAPP_CTRL2_RXIFLSEL)
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY      0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF       0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5       0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6       0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7       0x7
+#define BM_UARTAPP_CTRL2_RSVD3	0x00080000
+#define BP_UARTAPP_CTRL2_TXIFLSEL	16
+#define BM_UARTAPP_CTRL2_TXIFLSEL	0x00070000
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)  \
+		(((v) << 16) & BM_UARTAPP_CTRL2_TXIFLSEL)
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY          0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF       0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5       0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6       0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7       0x7
+#define BM_UARTAPP_CTRL2_CTSEN	0x00008000
+#define BM_UARTAPP_CTRL2_RTSEN	0x00004000
+#define BM_UARTAPP_CTRL2_OUT2	0x00002000
+#define BM_UARTAPP_CTRL2_OUT1	0x00001000
+#define BM_UARTAPP_CTRL2_RTS	0x00000800
+#define BM_UARTAPP_CTRL2_DTR	0x00000400
+#define BM_UARTAPP_CTRL2_RXE	0x00000200
+#define BM_UARTAPP_CTRL2_TXE	0x00000100
+#define BM_UARTAPP_CTRL2_LBE	0x00000080
+#define BM_UARTAPP_CTRL2_USE_LCR2	0x00000040
+#define BP_UARTAPP_CTRL2_RSVD4	3
+#define BM_UARTAPP_CTRL2_RSVD4	0x00000038
+#define BF_UARTAPP_CTRL2_RSVD4(v)  \
+		(((v) << 3) & BM_UARTAPP_CTRL2_RSVD4)
+#define BM_UARTAPP_CTRL2_SIRLP	0x00000004
+#define BM_UARTAPP_CTRL2_SIREN	0x00000002
+#define BM_UARTAPP_CTRL2_UARTEN	0x00000001
+
+#define HW_UARTAPP_LINECTRL	(0x00000030)
+#define HW_UARTAPP_LINECTRL_SET	(0x00000034)
+#define HW_UARTAPP_LINECTRL_CLR	(0x00000038)
+#define HW_UARTAPP_LINECTRL_TOG	(0x0000003c)
+
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT	16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT	0xFFFF0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) \
+		(((v) << 16) & BM_UARTAPP_LINECTRL_BAUD_DIVINT)
+#define BP_UARTAPP_LINECTRL_RSVD	14
+#define BM_UARTAPP_LINECTRL_RSVD	0x0000C000
+#define BF_UARTAPP_LINECTRL_RSVD(v)  \
+		(((v) << 14) & BM_UARTAPP_LINECTRL_RSVD)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC	8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC	0x00003F00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v)  \
+		(((v) << 8) & BM_UARTAPP_LINECTRL_BAUD_DIVFRAC)
+#define BM_UARTAPP_LINECTRL_SPS	0x00000080
+#define BP_UARTAPP_LINECTRL_WLEN	5
+#define BM_UARTAPP_LINECTRL_WLEN	0x00000060
+#define BF_UARTAPP_LINECTRL_WLEN(v)  \
+		(((v) << 5) & BM_UARTAPP_LINECTRL_WLEN)
+#define BM_UARTAPP_LINECTRL_FEN	0x00000010
+#define BM_UARTAPP_LINECTRL_STP2	0x00000008
+#define BM_UARTAPP_LINECTRL_EPS	0x00000004
+#define BM_UARTAPP_LINECTRL_PEN	0x00000002
+#define BM_UARTAPP_LINECTRL_BRK	0x00000001
+
+#define HW_UARTAPP_LINECTRL2	(0x00000040)
+#define HW_UARTAPP_LINECTRL2_SET	(0x00000044)
+#define HW_UARTAPP_LINECTRL2_CLR	(0x00000048)
+#define HW_UARTAPP_LINECTRL2_TOG	(0x0000004c)
+
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT	16
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT	0xFFFF0000
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) \
+		(((v) << 16) & BM_UARTAPP_LINECTRL2_BAUD_DIVINT)
+#define BP_UARTAPP_LINECTRL2_RSVD	14
+#define BM_UARTAPP_LINECTRL2_RSVD	0x0000C000
+#define BF_UARTAPP_LINECTRL2_RSVD(v)  \
+		(((v) << 14) & BM_UARTAPP_LINECTRL2_RSVD)
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC	8
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC	0x00003F00
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)  \
+		(((v) << 8) & BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC)
+#define BM_UARTAPP_LINECTRL2_SPS	0x00000080
+#define BP_UARTAPP_LINECTRL2_WLEN	5
+#define BM_UARTAPP_LINECTRL2_WLEN	0x00000060
+#define BF_UARTAPP_LINECTRL2_WLEN(v)  \
+		(((v) << 5) & BM_UARTAPP_LINECTRL2_WLEN)
+#define BM_UARTAPP_LINECTRL2_FEN	0x00000010
+#define BM_UARTAPP_LINECTRL2_STP2	0x00000008
+#define BM_UARTAPP_LINECTRL2_EPS	0x00000004
+#define BM_UARTAPP_LINECTRL2_PEN	0x00000002
+#define BM_UARTAPP_LINECTRL2_RSVD1	0x00000001
+
+#define HW_UARTAPP_INTR	(0x00000050)
+#define HW_UARTAPP_INTR_SET	(0x00000054)
+#define HW_UARTAPP_INTR_CLR	(0x00000058)
+#define HW_UARTAPP_INTR_TOG	(0x0000005c)
+
+#define BP_UARTAPP_INTR_RSVD1	28
+#define BM_UARTAPP_INTR_RSVD1	0xF0000000
+#define BF_UARTAPP_INTR_RSVD1(v) \
+		(((v) << 28) & BM_UARTAPP_INTR_RSVD1)
+#define BM_UARTAPP_INTR_ABDIEN	0x08000000
+#define BM_UARTAPP_INTR_OEIEN	0x04000000
+#define BM_UARTAPP_INTR_BEIEN	0x02000000
+#define BM_UARTAPP_INTR_PEIEN	0x01000000
+#define BM_UARTAPP_INTR_FEIEN	0x00800000
+#define BM_UARTAPP_INTR_RTIEN	0x00400000
+#define BM_UARTAPP_INTR_TXIEN	0x00200000
+#define BM_UARTAPP_INTR_RXIEN	0x00100000
+#define BM_UARTAPP_INTR_DSRMIEN	0x00080000
+#define BM_UARTAPP_INTR_DCDMIEN	0x00040000
+#define BM_UARTAPP_INTR_CTSMIEN	0x00020000
+#define BM_UARTAPP_INTR_RIMIEN	0x00010000
+#define BP_UARTAPP_INTR_RSVD2	12
+#define BM_UARTAPP_INTR_RSVD2	0x0000F000
+#define BF_UARTAPP_INTR_RSVD2(v)  \
+		(((v) << 12) & BM_UARTAPP_INTR_RSVD2)
+#define BM_UARTAPP_INTR_ABDIS	0x00000800
+#define BM_UARTAPP_INTR_OEIS	0x00000400
+#define BM_UARTAPP_INTR_BEIS	0x00000200
+#define BM_UARTAPP_INTR_PEIS	0x00000100
+#define BM_UARTAPP_INTR_FEIS	0x00000080
+#define BM_UARTAPP_INTR_RTIS	0x00000040
+#define BM_UARTAPP_INTR_TXIS	0x00000020
+#define BM_UARTAPP_INTR_RXIS	0x00000010
+#define BM_UARTAPP_INTR_DSRMIS	0x00000008
+#define BM_UARTAPP_INTR_DCDMIS	0x00000004
+#define BM_UARTAPP_INTR_CTSMIS	0x00000002
+#define BM_UARTAPP_INTR_RIMIS	0x00000001
+
+#define HW_UARTAPP_DATA	(0x00000060)
+
+#define BP_UARTAPP_DATA_DATA	0
+#define BM_UARTAPP_DATA_DATA	0xFFFFFFFF
+#define BF_UARTAPP_DATA_DATA(v)	(v)
+
+#define HW_UARTAPP_STAT	(0x00000070)
+
+#define BM_UARTAPP_STAT_PRESENT	0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE   0x1
+#define BM_UARTAPP_STAT_HISPEED	0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE   0x1
+#define BM_UARTAPP_STAT_BUSY	0x20000000
+#define BM_UARTAPP_STAT_CTS	0x10000000
+#define BM_UARTAPP_STAT_TXFE	0x08000000
+#define BM_UARTAPP_STAT_RXFF	0x04000000
+#define BM_UARTAPP_STAT_TXFF	0x02000000
+#define BM_UARTAPP_STAT_RXFE	0x01000000
+#define BP_UARTAPP_STAT_RXBYTE_INVALID	20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID	0x00F00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)  \
+		(((v) << 20) & BM_UARTAPP_STAT_RXBYTE_INVALID)
+#define BM_UARTAPP_STAT_OERR	0x00080000
+#define BM_UARTAPP_STAT_BERR	0x00040000
+#define BM_UARTAPP_STAT_PERR	0x00020000
+#define BM_UARTAPP_STAT_FERR	0x00010000
+#define BP_UARTAPP_STAT_RXCOUNT	0
+#define BM_UARTAPP_STAT_RXCOUNT	0x0000FFFF
+#define BF_UARTAPP_STAT_RXCOUNT(v)  \
+		(((v) << 0) & BM_UARTAPP_STAT_RXCOUNT)
+
+#define HW_UARTAPP_DEBUG	(0x00000080)
+
+#define BP_UARTAPP_DEBUG_RXIBAUD_DIV	16
+#define BM_UARTAPP_DEBUG_RXIBAUD_DIV	0xFFFF0000
+#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) \
+		(((v) << 16) & BM_UARTAPP_DEBUG_RXIBAUD_DIV)
+#define BP_UARTAPP_DEBUG_RXFBAUD_DIV	10
+#define BM_UARTAPP_DEBUG_RXFBAUD_DIV	0x0000FC00
+#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v)  \
+		(((v) << 10) & BM_UARTAPP_DEBUG_RXFBAUD_DIV)
+#define BP_UARTAPP_DEBUG_RSVD1	6
+#define BM_UARTAPP_DEBUG_RSVD1	0x000003C0
+#define BF_UARTAPP_DEBUG_RSVD1(v)  \
+		(((v) << 6) & BM_UARTAPP_DEBUG_RSVD1)
+#define BM_UARTAPP_DEBUG_TXDMARUN	0x00000020
+#define BM_UARTAPP_DEBUG_RXDMARUN	0x00000010
+#define BM_UARTAPP_DEBUG_TXCMDEND	0x00000008
+#define BM_UARTAPP_DEBUG_RXCMDEND	0x00000004
+#define BM_UARTAPP_DEBUG_TXDMARQ	0x00000002
+#define BM_UARTAPP_DEBUG_RXDMARQ	0x00000001
+
+#define HW_UARTAPP_VERSION	(0x00000090)
+
+#define BP_UARTAPP_VERSION_MAJOR	24
+#define BM_UARTAPP_VERSION_MAJOR	0xFF000000
+#define BF_UARTAPP_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_UARTAPP_VERSION_MAJOR)
+#define BP_UARTAPP_VERSION_MINOR	16
+#define BM_UARTAPP_VERSION_MINOR	0x00FF0000
+#define BF_UARTAPP_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_UARTAPP_VERSION_MINOR)
+#define BP_UARTAPP_VERSION_STEP	0
+#define BM_UARTAPP_VERSION_STEP	0x0000FFFF
+#define BF_UARTAPP_VERSION_STEP(v)  \
+		(((v) << 0) & BM_UARTAPP_VERSION_STEP)
+
+#define HW_UARTAPP_AUTOBAUD	(0x000000a0)
+
+#define BP_UARTAPP_AUTOBAUD_REFCHAR1	24
+#define BM_UARTAPP_AUTOBAUD_REFCHAR1	0xFF000000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v) \
+		(((v) << 24) & BM_UARTAPP_AUTOBAUD_REFCHAR1)
+#define BP_UARTAPP_AUTOBAUD_REFCHAR0	16
+#define BM_UARTAPP_AUTOBAUD_REFCHAR0	0x00FF0000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v)  \
+		(((v) << 16) & BM_UARTAPP_AUTOBAUD_REFCHAR0)
+#define BP_UARTAPP_AUTOBAUD_RSVD1	5
+#define BM_UARTAPP_AUTOBAUD_RSVD1	0x0000FFE0
+#define BF_UARTAPP_AUTOBAUD_RSVD1(v)  \
+		(((v) << 5) & BM_UARTAPP_AUTOBAUD_RSVD1)
+#define BM_UARTAPP_AUTOBAUD_UPDATE_TX	0x00000010
+#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS	0x00000008
+#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT	0x00000004
+#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT	0x00000002
+#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE	0x00000001
+#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/drivers/serial/stmp-app.c b/drivers/serial/stmp-app.c
new file mode 100644
index 000000000000..b0ca0837cffe
--- /dev/null
+++ b/drivers/serial/stmp-app.c
@@ -0,0 +1,1081 @@
+/*
+ * Freescale STMP37XX/STMP378X Application UART driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <mach/regs-apbx.h>
+#include <mach/regs-uartapp.h>
+#include <mach/regs-pinctrl.h>
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+
+#include <asm/mach-types.h>
+
+#include "stmp-app.h"
+
+static int pio_mode /* = 0 */; 	/* PIO mode = 1, DMA mode = 0	*/
+
+static struct platform_driver stmp_appuart_driver = {
+	.probe = stmp_appuart_probe,
+	.remove = __devexit_p(stmp_appuart_remove),
+	.suspend = stmp_appuart_suspend,
+	.resume = stmp_appuart_resume,
+	.driver = {
+		.name = "stmp3xxx-appuart",
+		.owner = THIS_MODULE,
+	},
+};
+
+static struct uart_driver stmp_appuart_uart = {
+	.owner = THIS_MODULE,
+	.driver_name = "appuart",
+	.dev_name = "ttySP",
+	.major = 242,
+	.minor = 0,
+	.nr = 1,
+};
+
+static inline struct stmp_appuart_port *to_appuart(struct uart_port *u)
+{
+	return container_of(u, struct stmp_appuart_port, port);
+}
+
+static struct uart_ops stmp_appuart_ops = {
+	.tx_empty       = stmp_appuart_tx_empty,
+	.start_tx       = stmp_appuart_start_tx,
+	.stop_tx	= stmp_appuart_stop_tx,
+	.stop_rx	= stmp_appuart_stop_rx,
+	.enable_ms      = stmp_appuart_enable_ms,
+	.break_ctl      = stmp_appuart_break_ctl,
+	.set_mctrl	= stmp_appuart_set_mctrl,
+	.get_mctrl      = stmp_appuart_get_mctrl,
+	.startup	= stmp_appuart_startup,
+	.shutdown       = stmp_appuart_shutdown,
+	.set_termios    = stmp_appuart_settermios,
+	.type	   	= stmp_appuart_type,
+	.release_port   = stmp_appuart_release_port,
+	.request_port   = stmp_appuart_request_port,
+	.config_port    = stmp_appuart_config_port,
+	.verify_port    = stmp_appuart_verify_port,
+};
+
+static inline int chr(int c)
+{
+	if (c < 0x20 || c > 0x7F)
+		return '#';
+	return c;
+}
+
+/* Allocate and initialize rx and tx DMA chains */
+static inline int stmp_appuart_dma_init(struct stmp_appuart_port *s)
+{
+	int err = 0;
+	struct stmp3xxx_dma_descriptor *t = &s->tx_desc;
+#ifndef RX_CHAIN
+	struct stmp3xxx_dma_descriptor *r = &s->rx_desc;
+#else
+	int i;
+#endif
+
+	err = stmp3xxx_dma_request(s->dma_rx, s->dev, dev_name(s->dev));
+	if (err)
+		goto out;
+	err = stmp3xxx_dma_request(s->dma_tx, s->dev, dev_name(s->dev));
+	if (err)
+		goto out1;
+
+#ifndef RX_CHAIN
+	err = stmp3xxx_dma_allocate_command(s->dma_rx, r);
+	if (err)
+		goto out2;
+#endif
+	err = stmp3xxx_dma_allocate_command(s->dma_tx, t);
+	if (err)
+		goto out3;
+	t->virtual_buf_ptr = dma_alloc_coherent(s->dev,
+						TX_BUFFER_SIZE,
+						&t->command->buf_ptr, GFP_DMA);
+	if (!t->virtual_buf_ptr)
+		goto out4;
+#ifdef DEBUG
+	memset(t->virtual_buf_ptr, 0x4B, TX_BUFFER_SIZE);
+#endif
+
+#ifndef RX_CHAIN
+	r->virtual_buf_ptr = dma_alloc_coherent(s->dev,
+						RX_BUFFER_SIZE,
+						&r->command->buf_ptr, GFP_DMA);
+	if (!r->virtual_buf_ptr)
+		goto out5;
+#ifdef DEBUG
+	memset(r->virtual_buf_ptr, 0x4C, RX_BUFFER_SIZE);
+#endif
+#else
+	stmp3xxx_dma_make_chain(s->dma_rx, &s->rx_chain, s->rxd, RX_CHAIN);
+	for (i = 0; i < RX_CHAIN; i++) {
+		struct stmp3xxx_dma_descriptor *r = s->rxd + i;
+
+		r->command->cmd =
+		    BF(RX_BUFFER_SIZE, APBX_CHn_CMD_XFER_COUNT) |
+		    BF(1, APBX_CHn_CMD_CMDWORDS) |
+		    BM_APBX_CHn_CMD_WAIT4ENDCMD |
+		    BM_APBX_CHn_CMD_SEMAPHORE |
+		    BM_APBX_CHn_CMD_IRQONCMPLT |
+		    BM_APBX_CHn_CMD_CHAIN |
+		    BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__DMA_WRITE);
+		r->virtual_buf_ptr = dma_alloc_coherent(s->dev,
+							RX_BUFFER_SIZE,
+							&r->command->buf_ptr,
+							GFP_DMA);
+		r->command->pio_words[0] =	/* BM_UARTAPP_CTRL0_RUN | */
+		    BF(RX_BUFFER_SIZE, UARTAPP_CTRL0_XFER_COUNT) |
+		    BM_UARTAPP_CTRL0_RXTO_ENABLE |
+		    BF(3, UARTAPP_CTRL0_RXTIMEOUT);
+	}
+#endif
+	return 0;
+
+	/*
+	 * would be necessary on other error paths
+
+	dma_free_coherent( s->dev, RX_BUFFER_SIZE, r->virtual_buf_ptr,
+			   r->command->buf_ptr);
+	*/
+out5:
+	dma_free_coherent(s->dev, TX_BUFFER_SIZE, t->virtual_buf_ptr,
+			   t->command->buf_ptr);
+out4:
+	stmp3xxx_dma_free_command(s->dma_tx, t);
+out3:
+#ifndef RX_CHAIN
+	stmp3xxx_dma_free_command(s->dma_rx, r);
+#endif
+out2:
+	stmp3xxx_dma_release(s->dma_tx);
+out1:
+	stmp3xxx_dma_release(s->dma_rx);
+out:
+	WARN_ON(err);
+	return err;
+}
+
+
+static void stmp_appuart_on(struct platform_device *dev)
+{
+	struct stmp_appuart_port *s = platform_get_drvdata(dev);
+
+	if (!pio_mode) {
+		/*
+		   Tell DMA to select UART.
+		   Both DMA channels are shared between app UART and IrDA.
+		   Target id of 0 means UART, 1 means IrDA
+		 */
+		stmp3xxx_dma_set_alt_target(s->dma_rx, 0);
+		stmp3xxx_dma_set_alt_target(s->dma_tx, 0);
+		/*
+		  Reset DMA channels
+		 */
+		stmp3xxx_dma_reset_channel(s->dma_rx);
+		stmp3xxx_dma_reset_channel(s->dma_tx);
+		stmp3xxx_dma_enable_interrupt(s->dma_rx);
+		stmp3xxx_dma_enable_interrupt(s->dma_tx);
+	}
+}
+
+#ifdef CONFIG_CPU_FREQ
+static int stmp_appuart_updateclk(struct device *dev, void *clkdata)
+{
+	struct stmp_appuart_port *s = dev_get_drvdata(dev);
+
+	if (s) {
+		s->port.uartclk = clk_get_rate(s->clk) * 1000;
+		/* FIXME: perform actual update */
+	}
+	return 0;
+}
+
+static int stmp_appuart_notifier(struct notifier_block *self,
+				 unsigned long phase, void *p)
+{
+	int r = 0;
+
+	if ((phase == CPUFREQ_POSTCHANGE) || (phase == CPUFREQ_RESUMECHANGE)) {
+		/* get new uartclock and setspeed */
+		r = driver_for_each_device(&stmp_appuart_driver.driver,
+					   NULL, p, stmp_appuart_updateclk);
+	}
+	return (r == 0) ? NOTIFY_OK : NOTIFY_DONE;
+}
+
+static struct notifier_block stmp_appuart_nb = {
+	.notifier_call = &stmp_appuart_notifier,
+};
+#endif /* CONFIG_CPU_FREQ */
+
+static int __devinit stmp_appuart_probe(struct platform_device *device)
+{
+	struct stmp_appuart_port *s;
+	int err = 0;
+	struct resource *r;
+	int i;
+	u32 version;
+	int (*pinctl)(int req, int id);
+
+	s = kzalloc(sizeof(struct stmp_appuart_port), GFP_KERNEL);
+	if (!s) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	spin_lock_init(&s->lock);
+
+	s->clk = clk_get(NULL, "uart");
+	if (IS_ERR(s->clk)) {
+		err = PTR_ERR(s->clk);
+		goto out_free;
+	}
+	clk_enable(s->clk);
+	r = platform_get_resource(device, IORESOURCE_MEM, 0);
+	if (!r) {
+		err = -ENXIO;
+		goto out_free_clk;
+	}
+	s->port.mapbase = r->start;
+	s->port.irq = platform_get_irq(device, 0);
+	s->port.ops = &stmp_appuart_ops;
+	s->port.iotype = UPIO_MEM;
+	s->port.line = device->id < 0 ? 0 : device->id;
+	s->port.fifosize = 16;
+	s->port.timeout = HZ/10;
+	s->port.uartclk = clk_get_rate(s->clk) * 1000;
+	s->port.type = PORT_IMX;
+	s->port.dev = s->dev = get_device(&device->dev);
+	s->ctrl = 0;
+	s->keep_irq = 0;
+
+	r = platform_get_resource(device, IORESOURCE_MEM, 0);
+	if (!r) {
+		err = -ENXIO;
+		goto out_free_clk;
+	}
+
+	dev_dbg(s->dev, "%s\n", __func__);
+	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
+		s->irq[i] = platform_get_irq(device, i);
+		dev_dbg(s->dev, "Resources: irq[%d] = %d\n", i, s->irq[i]);
+		if (s->irq[i] < 0) {
+			err = s->irq[i];
+			goto out_free_clk;
+		}
+	}
+
+	r = platform_get_resource(device, IORESOURCE_DMA, 0);
+	if (!r) {
+		err = -ENXIO;
+		goto out_free;
+	}
+	s->dma_rx = r->start;
+
+	r = platform_get_resource(device, IORESOURCE_DMA, 1);
+	if (!r) {
+		err = -ENXIO;
+		goto out_free;
+	}
+	s->dma_tx = r->start;
+
+	r = platform_get_resource(device, IORESOURCE_MEM, 0);
+	if (!r) {
+		err = -ENXIO;
+		goto out_free;
+	}
+	s->mem = (void __iomem *)(r->start - STMP3XXX_REGS_PHBASE
+			+ (u32)STMP3XXX_REGS_BASE);
+	s->memsize = r->end - r->start;
+
+#ifdef CONFIG_CPU_FREQ
+	cpufreq_register_notifier(&stmp_appuart_nb,
+				  CPUFREQ_TRANSITION_NOTIFIER);
+#endif
+	platform_set_drvdata(device, s);
+
+	device_init_wakeup(&device->dev, 1);
+
+	stmp_appuart_dma_init(s);
+	stmp_appuart_on(device);
+
+	pinctl = device->dev.platform_data;
+	if (pinctl) {
+		err = pinctl(1, device->id);
+		if (err)
+			goto out_free_clk;
+	}
+
+	err = uart_add_one_port(&stmp_appuart_uart, &s->port);
+	if (err)
+		goto out_free_pins;
+
+	version = __raw_readl(REGS_UARTAPP1_BASE + HW_UARTAPP_VERSION);
+	printk(KERN_INFO "Found APPUART %d.%d.%d\n",
+	       (version >> 24) & 0xFF,
+	       (version >> 16) & 0xFF, version & 0xFFFF);
+	return 0;
+
+out_free_pins:
+	if (pinctl)
+		pinctl(0, device->id);
+out_free_clk:
+	clk_put(s->clk);
+out_free:
+	platform_set_drvdata(device, NULL);
+	kfree(s);
+out:
+	return err;
+}
+
+static int __devexit stmp_appuart_remove(struct platform_device *device)
+{
+	struct stmp_appuart_port *s;
+	void (*pinctl)(int req, int id);
+
+	s = platform_get_drvdata(device);
+	if (s) {
+		pinctl = device->dev.platform_data;
+		put_device(s->dev);
+		clk_disable(s->clk);
+		clk_put(s->clk);
+		uart_remove_one_port(&stmp_appuart_uart, &s->port);
+		if (pinctl)
+			pinctl(0, device->id);
+		kfree(s);
+		platform_set_drvdata(device, NULL);
+	}
+
+	return 0;
+}
+
+static int stmp_appuart_suspend(struct platform_device *device,
+				pm_message_t state)
+{
+#ifdef CONFIG_PM
+	struct stmp_appuart_port *s = platform_get_drvdata(device);
+
+	if (!s)
+		return 0;
+	s->keep_irq = device_may_wakeup(&device->dev);
+	uart_suspend_port(&stmp_appuart_uart, &s->port);
+	if (!s->keep_irq)
+		clk_disable(s->clk);
+#endif
+	return 0;
+}
+
+static int stmp_appuart_resume(struct platform_device *device)
+{
+#ifdef CONFIG_PM
+	struct stmp_appuart_port *s = platform_get_drvdata(device);
+
+	if (!s)
+		return 0;
+
+	if (!s->keep_irq)
+		clk_enable(s->clk);
+	stmp_appuart_on(device);
+	uart_resume_port(&stmp_appuart_uart, &s->port);
+	s->keep_irq = 0;
+#endif
+	return 0;
+}
+
+static int __init stmp_appuart_init()
+{
+	int r;
+
+	r = uart_register_driver(&stmp_appuart_uart);
+	if (r)
+		goto out;
+	r = platform_driver_register(&stmp_appuart_driver);
+	if (r)
+		goto out_err;
+	return 0;
+out_err:
+	uart_unregister_driver(&stmp_appuart_uart);
+out:
+	return r;
+}
+
+static void __exit stmp_appuart_exit()
+{
+	platform_driver_unregister(&stmp_appuart_driver);
+	uart_unregister_driver(&stmp_appuart_uart);
+}
+
+module_init(stmp_appuart_init)
+module_exit(stmp_appuart_exit)
+
+static void stmp_appuart_stop_rx(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+	__raw_writel(BM_UARTAPP_CTRL2_RXE, s->mem + HW_STMP3XXX_CLR);
+}
+
+static void stmp_appuart_break_ctl(struct uart_port *u, int ctl)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s: break = %s\n", __func__, ctl ? "on" : "off");
+	if (ctl)
+		__raw_writel(BM_UARTAPP_LINECTRL_BRK,
+			      s->mem + HW_UARTAPP_LINECTRL_SET);
+	else
+		__raw_writel(BM_UARTAPP_LINECTRL_BRK,
+				s->mem + HW_UARTAPP_LINECTRL_CLR);
+}
+
+static void stmp_appuart_enable_ms(struct uart_port *port)
+{
+	/* just empty */
+}
+
+static void stmp_appuart_set_mctrl(struct uart_port *u, unsigned mctrl)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	u32 ctrl = __raw_readl(s->mem + HW_UARTAPP_CTRL2);
+
+	dev_dbg(s->dev, "%s (%x)\n", __func__, mctrl);
+	ctrl &= ~BM_UARTAPP_CTRL2_RTS;
+	if (mctrl & TIOCM_RTS) {
+		dev_dbg(s->dev, "...RTS\n");
+		ctrl |= BM_UARTAPP_CTRL2_RTS;
+	}
+	s->ctrl = mctrl;
+	dev_dbg(s->dev, "...%x; ctrl = %x\n", s->ctrl, ctrl);
+	__raw_writel(ctrl, s->mem + HW_UARTAPP_CTRL2);
+}
+
+static u32 stmp_appuart_get_mctrl(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+	u32 stat = __raw_readl(s->mem + HW_UARTAPP_STAT);
+	int ctrl2 = __raw_readl(s->mem + HW_UARTAPP_CTRL2);
+	u32 mctrl = s->ctrl;
+
+	dev_dbg(s->dev, "%s:\n", __func__);
+	mctrl &= ~TIOCM_CTS;
+	if (stat & BM_UARTAPP_STAT_CTS) {
+		dev_dbg(s->dev, "CTS");
+		mctrl |= TIOCM_CTS;
+	}
+	if (ctrl2 & BM_UARTAPP_CTRL2_RTS) {
+		dev_dbg(s->dev, "RTS");
+		mctrl |= TIOCM_RTS;
+	}
+	dev_dbg(s->dev, "...%x\n", mctrl);
+	return mctrl;
+}
+
+static int stmp_appuart_request_port(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+	int err = 0;
+
+	if (!request_mem_region((u32)s->mem, s->memsize, dev_name(s->dev)))
+		err = -ENXIO;
+	return err;
+
+}
+
+static void stmp_appuart_release_port(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	release_mem_region((u32)s->mem, s->memsize);
+}
+
+static int stmp_appuart_verify_port(struct uart_port *u,
+				    struct serial_struct *ser)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+	return 0;
+}
+
+static void stmp_appuart_config_port(struct uart_port *u, int flags)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+}
+
+static const char *stmp_appuart_type(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+	return dev_name(s->dev);
+}
+
+static void stmp_appuart_settermios(struct uart_port *u,
+				    struct ktermios *nw, struct ktermios *old)
+{
+	static struct ktermios saved;
+	struct stmp_appuart_port *s = to_appuart(u);
+	unsigned int cflag;
+	u32 bm, ctrl, ctrl2, div;
+	int err = 0;
+	unsigned baud;
+
+	dev_dbg(s->dev, "%s\n", __func__);
+
+	if (nw)
+		memcpy(&saved, nw, sizeof *nw);
+	else
+		nw = old = &saved;
+
+	cflag = nw->c_cflag;
+
+	ctrl = BM_UARTAPP_LINECTRL_FEN;
+	ctrl2 = __raw_readl(s->mem + HW_UARTAPP_CTRL2);
+
+	/* byte size */
+	switch (cflag & CSIZE) {
+	case CS5:
+		bm = 0;
+		break;
+	case CS6:
+		bm = 1;
+		break;
+	case CS7:
+		bm = 2;
+		break;
+	case CS8:
+		bm = 3;
+		break;
+	default:
+		err = -EINVAL;
+		break;
+	}
+	if (err)
+		goto out;
+
+	dev_dbg(s->dev, "Byte size %d bytes, mask %x\n",
+		bm + 5, BF(bm, UARTAPP_LINECTRL_WLEN));
+	ctrl |= BF(bm, UARTAPP_LINECTRL_WLEN);
+
+	/* parity */
+	if (cflag & PARENB) {
+		dev_dbg(s->dev, "Parity check enabled\n");
+		ctrl |= BM_UARTAPP_LINECTRL_PEN | BM_UARTAPP_LINECTRL_SPS;
+		if ((cflag & PARODD) == 0) {
+			dev_dbg(s->dev, "(Even) mask = %x\n",
+				BM_UARTAPP_LINECTRL_PEN |
+				BM_UARTAPP_LINECTRL_SPS |
+				BM_UARTAPP_LINECTRL_EPS);
+			ctrl |= BM_UARTAPP_LINECTRL_EPS;
+		} else
+			dev_dbg(s->dev, "(Odd) mask = %x\n",
+				BM_UARTAPP_LINECTRL_PEN |
+				BM_UARTAPP_LINECTRL_SPS);
+	} else
+		dev_dbg(s->dev, "Parity check disabled.\n");
+
+	/* figure out the stop bits requested */
+	if (cflag & CSTOPB) {
+		dev_dbg(s->dev, "Stop bits, mask = %x\n",
+			BM_UARTAPP_LINECTRL_STP2);
+		ctrl |= BM_UARTAPP_LINECTRL_STP2;
+	} else
+		dev_dbg(s->dev, "No stop bits\n");
+
+	/* figure out the hardware flow control settings */
+	if (cflag & CRTSCTS) {
+		dev_dbg(s->dev, "RTS/CTS flow control\n");
+		ctrl2 |= BM_UARTAPP_CTRL2_CTSEN /* | BM_UARTAPP_CTRL2_RTSEN */ ;
+	} else {
+		dev_dbg(s->dev, "RTS/CTS disabled\n");
+		ctrl2 &= ~BM_UARTAPP_CTRL2_CTSEN;
+	}
+
+	/* set baud rate */
+	baud = uart_get_baud_rate(u, nw, old, 0, u->uartclk);
+	dev_dbg(s->dev, "Baud rate requested: %d (clk = %d)\n",
+		baud, u->uartclk);
+	div = u->uartclk * 32 / baud;
+	ctrl |= BF(div & 0x3F, UARTAPP_LINECTRL_BAUD_DIVFRAC);
+	ctrl |= BF(div >> 6, UARTAPP_LINECTRL_BAUD_DIVINT);
+
+	if ((cflag & CREAD) != 0) {
+		dev_dbg(s->dev, "RX started\n");
+		ctrl2 |= BM_UARTAPP_CTRL2_RXE | BM_UARTAPP_CTRL2_RXDMAE;
+	}
+
+	if (!err) {
+		dev_dbg(s->dev, "CTRLS = %x + %x\n", ctrl, ctrl2);
+		__raw_writel(ctrl,
+			     s->mem + HW_UARTAPP_LINECTRL);
+		__raw_writel(ctrl2,
+			     s->mem + HW_UARTAPP_CTRL2);
+	}
+out:
+	return /* err */ ;
+}
+
+static int stmp_appuart_free_irqs(struct stmp_appuart_port *s)
+{
+	int irqn = 0;
+
+	if (s->keep_irq) {
+		dev_dbg(s->dev, "keep_irq != 0, ignoring\n");
+		return 0;
+	}
+	for (irqn = 0; irqn < ARRAY_SIZE(s->irq); irqn++)
+		free_irq(s->irq[irqn], s);
+	return 0;
+}
+
+void stmp_appuart_rx(struct stmp_appuart_port *s, u8 * rx_buffer, int count)
+{
+	u8 c;
+	int flag;
+	struct tty_struct *tty = s->port.info->port.tty;
+	u32 stat;
+
+	spin_lock(&s->lock);
+	stat = __raw_readl(s->mem + HW_UARTAPP_STAT);
+
+	if (count < 0) {
+		count =
+		    __raw_readl(s->mem +
+				HW_UARTAPP_STAT) & BM_UARTAPP_STAT_RXCOUNT;
+		dev_dbg(s->dev, "count = %d\n", count);
+	}
+
+	for (;;) {
+		if (!rx_buffer) {
+			if (stat & BM_UARTAPP_STAT_RXFE)
+				break;
+			c = __raw_readl(s->mem + HW_UARTAPP_DATA) & 0xFF;
+		} else {
+			if (count-- <= 0)
+				break;
+			c = *rx_buffer++;
+			dev_dbg(s->dev, "Received: %x(%c)\n", c, chr(c));
+		}
+
+		flag = TTY_NORMAL;
+		if (stat & BM_UARTAPP_STAT_BERR) {
+			stat &= ~BM_UARTAPP_STAT_BERR;
+			s->port.icount.brk++;
+			if (uart_handle_break(&s->port))
+				goto ignore;
+			flag = TTY_BREAK;
+		} else if (stat & BM_UARTAPP_STAT_PERR) {
+			stat &= ~BM_UARTAPP_STAT_PERR;
+			s->port.icount.parity++;
+			flag = TTY_PARITY;
+		} else if (stat & BM_UARTAPP_STAT_FERR) {
+			stat &= ~BM_UARTAPP_STAT_FERR;
+			s->port.icount.frame++;
+			flag = TTY_FRAME;
+		}
+
+		if (stat & BM_UARTAPP_STAT_OERR)
+			s->port.icount.overrun++;
+
+		if (uart_handle_sysrq_char(&s->port, c))
+			goto ignore;
+
+		uart_insert_char(&s->port, stat, BM_UARTAPP_STAT_OERR, c, flag);
+ignore:
+		if (pio_mode) {
+			__raw_writel(stat, s->mem + HW_UARTAPP_STAT);
+			stat =
+			    __raw_readl(s->mem + HW_UARTAPP_STAT);
+		}
+	}
+
+	__raw_writel(stat, s->mem + HW_UARTAPP_STAT);
+	tty_flip_buffer_push(tty);
+	spin_unlock(&s->lock);
+}
+
+static inline void stmp_appuart_submit_rx(struct stmp_appuart_port *s)
+{
+#ifndef RX_CHAIN
+	struct stmp3xxx_dma_descriptor *r = &s->rx_desc;
+
+	dev_dbg(s->dev, "Submitting RX DMA request\n");
+	r->command->cmd =
+	    BM_APBX_CHn_CMD_HALTONTERMINATE |
+	    BF(RX_BUFFER_SIZE, APBX_CHn_CMD_XFER_COUNT) |
+	    BF(1, APBX_CHn_CMD_CMDWORDS) |
+	    BM_APBX_CHn_CMD_WAIT4ENDCMD |
+	    BM_APBX_CHn_CMD_SEMAPHORE |
+	    BM_APBX_CHn_CMD_IRQONCMPLT |
+	    BF(BV_APBX_CHn_CMD_COMMAND__DMA_WRITE, APBX_CHn_CMD_COMMAND);
+	r->command->pio_words[0] =
+	    __raw_readl(REGS_UARTAPP1_BASE +
+			HW_UARTAPP_CTRL0) | BF(RX_BUFFER_SIZE,
+					       UARTAPP_CTRL0_XFER_COUNT) |
+	    BM_UARTAPP_CTRL0_RXTO_ENABLE | BF(3, UARTAPP_CTRL0_RXTIMEOUT);
+	r->command->pio_words[0] &= ~BM_UARTAPP_CTRL0_RUN;
+
+	stmp3xxx_dma_reset_channel(s->dma_rx);
+	stmp3xxx_dma_go(s->dma_rx, r, 1);
+#endif
+}
+
+static irqreturn_t stmp_appuart_irq_int(int irq, void *context)
+{
+	u32 istatus;
+	struct stmp_appuart_port *s = context;
+	u32 stat = __raw_readl(s->mem + HW_UARTAPP_STAT);
+
+	istatus = __raw_readl(s->mem + HW_UARTAPP_INTR);
+	dev_dbg(s->dev, "IRQ: int(%d), status = %08X\n", irq, istatus);
+
+	if (istatus & BM_UARTAPP_INTR_CTSMIS) {
+		uart_handle_cts_change(&s->port, stat & BM_UARTAPP_STAT_CTS);
+		dev_dbg(s->dev, "CTS change: %x\n", stat & BM_UARTAPP_STAT_CTS);
+		__raw_writel(BM_UARTAPP_INTR_CTSMIS,
+				s->mem + HW_UARTAPP_INTR_CLR);
+	}
+
+	else if (istatus & BM_UARTAPP_INTR_RTIS) {
+		dev_dbg(s->dev, "RX timeout, draining out\n");
+		stmp_appuart_submit_rx(s);
+	}
+
+	else
+		dev_info(s->dev, "Unhandled status %x\n", istatus);
+
+	__raw_writel(istatus & 0xFFFF,
+			s->mem + HW_UARTAPP_INTR_CLR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stmp_appuart_irq_rx(int irq, void *context)
+{
+	struct stmp_appuart_port *s = context;
+	int count = -1;
+
+	stmp3xxx_dma_clear_interrupt(s->dma_rx);
+	dev_dbg(s->dev, "%s(%d), count = %d\n", __func__, irq, count);
+
+#ifndef RX_CHAIN
+	stmp_appuart_rx(s, s->rx_desc.virtual_buf_ptr, count);
+	stmp_appuart_submit_rx(s);
+#else
+	if (circ_advance_cooked(&s->rx_chain) == 0) {
+		BUG();
+		return IRQ_HANDLED;
+	}
+
+	circ_advance_active(&s->rx_chain, 1);
+	while (s->rx_chain.cooked_count) {
+		stmp_appuart_rx(s,
+				stmp3xxx_dma_circ_get_cooked_head(&s->
+								  rx_chain)->virtual_buf_ptr,
+				-1);
+		circ_advance_free(&s->rx_chain, 1);
+	}
+#endif
+	return IRQ_HANDLED;
+}
+
+static void stmp_appuart_submit_tx(struct stmp_appuart_port *s, int size)
+{
+	struct stmp3xxx_dma_descriptor *d = &s->tx_desc;
+
+	dev_dbg(s->dev, "Submitting TX DMA request, %d bytes\n", size);
+	d->command->pio_words[0] =
+	    /* BM_UARTAPP_CTRL1_RUN | */ BF(size, UARTAPP_CTRL1_XFER_COUNT);
+	d->command->cmd = BF(size, APBX_CHn_CMD_XFER_COUNT) |
+	    BF(1, APBX_CHn_CMD_CMDWORDS) |
+	    BM_APBX_CHn_CMD_WAIT4ENDCMD |
+	    BM_APBX_CHn_CMD_SEMAPHORE |
+	    BM_APBX_CHn_CMD_IRQONCMPLT |
+	    BF(BV_APBX_CHn_CMD_COMMAND__DMA_READ, APBX_CHn_CMD_COMMAND);
+	stmp3xxx_dma_go(s->dma_tx, d, 1);
+}
+
+static irqreturn_t stmp_appuart_irq_tx(int irq, void *context)
+{
+	struct stmp_appuart_port *s = context;
+	struct uart_port *u = &s->port;
+	int bytes;
+
+	stmp3xxx_dma_clear_interrupt(s->dma_tx);
+	dev_dbg(s->dev, "%s(%d)\n", __func__, irq);
+
+	bytes = stmp_appuart_copy_tx(u, s->tx_desc.virtual_buf_ptr,
+				     TX_BUFFER_SIZE);
+	if (bytes > 0) {
+		dev_dbg(s->dev, "Sending %d bytes\n", bytes);
+		stmp_appuart_submit_tx(s, bytes);
+	}
+	return IRQ_HANDLED;
+}
+
+static int stmp_appuart_request_irqs(struct stmp_appuart_port *s)
+{
+	int err = 0;
+
+	/*
+	 * order counts. resources should be listed in the same order
+	 */
+	irq_handler_t handlers[] = {
+		stmp_appuart_irq_int,
+		stmp_appuart_irq_rx,
+		stmp_appuart_irq_tx,
+	};
+	char *handlers_names[] = {
+		"appuart internal",
+		"appuart rx",
+		"appuart tx",
+	};
+	int irqn;
+
+	if (s->keep_irq) {
+		dev_dbg(s->dev, "keep_irq is set, skipping request_irq");
+		return 0;
+	}
+	for (irqn = 0; irqn < ARRAY_SIZE(handlers); irqn++) {
+		err = request_irq(s->irq[irqn], handlers[irqn],
+				  0, handlers_names[irqn], s);
+		dev_dbg(s->dev, "Requested IRQ %d with status %d\n",
+			s->irq[irqn], err);
+		if (err)
+			goto out;
+	}
+	return 0;
+out:
+	stmp_appuart_free_irqs(s);
+	return err;
+}
+
+static struct timer_list timer_task;
+
+static void stmp_appuart_check_rx(unsigned long data)
+{
+	stmp_appuart_rx((struct stmp_appuart_port *)data, NULL, -1);
+	mod_timer(&timer_task, jiffies + 2 * HZ);
+}
+
+static int stmp_appuart_startup(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+	int err;
+
+	dev_dbg(s->dev, "%s\n", __func__);
+
+	s->tx_buffer_index = 0;
+
+	err = stmp_appuart_request_irqs(s);
+	if (err)
+		goto out;
+
+	if (!s->keep_irq)
+		/* Release the block from reset and start the clocks. */
+		stmp3xxx_reset_block(s->mem, 0);
+
+	__raw_writel(BM_UARTAPP_CTRL2_UARTEN,
+			s->mem + HW_UARTAPP_CTRL2_SET);
+	/* Enable the Application UART DMA bits. */
+	if (!pio_mode) {
+		__raw_writel(BM_UARTAPP_CTRL2_TXDMAE | BM_UARTAPP_CTRL2_RXDMAE
+			      | BM_UARTAPP_CTRL2_DMAONERR,
+			      s->mem + HW_UARTAPP_CTRL2_SET);
+		/* clear any pending interrupts */
+		__raw_writel(0, s->mem + HW_UARTAPP_INTR);
+
+		/* reset all dma channels */
+		stmp3xxx_dma_reset_channel(s->dma_tx);
+		stmp3xxx_dma_reset_channel(s->dma_rx);
+	} else {
+		__raw_writel(BM_UARTAPP_INTR_RXIEN |
+			     BM_UARTAPP_INTR_RTIEN,
+			     s->mem + HW_UARTAPP_INTR);
+	}
+	__raw_writel(BM_UARTAPP_INTR_CTSMIEN,
+			s->mem + HW_UARTAPP_INTR_SET);
+
+	/*
+	 * Enable fifo so all four bytes of a DMA word are written to
+	 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
+	 */
+	__raw_writel(BM_UARTAPP_LINECTRL_FEN, s->mem + HW_UARTAPP_LINECTRL_SET);
+
+	if (!pio_mode) {
+#ifndef RX_CHAIN
+		stmp_appuart_submit_rx(s);
+#else
+		circ_clear_chain(&s->rx_chain);
+		stmp3xxx_dma_go(s->dma_rx, &s->rxd[0], 0);
+		circ_advance_active(&s->rx_chain, 1);
+#endif
+	} else {
+		init_timer(&timer_task);
+		timer_task.function = stmp_appuart_check_rx;
+		timer_task.expires = jiffies + HZ;
+		timer_task.data = (unsigned long)s;
+		add_timer(&timer_task);
+	}
+
+out:
+	return err;
+}
+
+static void stmp_appuart_shutdown(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+
+	if (!s->keep_irq)
+		/* set the IP block to RESET; this should disable clock too. */
+		__raw_writel(
+			BM_UARTAPP_CTRL0_SFTRST, s->mem + HW_UARTAPP_CTRL0_SET);
+
+	if (!pio_mode) {
+		/* reset all dma channels */
+		stmp3xxx_dma_reset_channel(s->dma_tx);
+		stmp3xxx_dma_reset_channel(s->dma_rx);
+	} else {
+		del_timer(&timer_task);
+	}
+	stmp_appuart_free_irqs(s);
+}
+
+static unsigned int stmp_appuart_tx_empty(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	if (pio_mode)
+		if (__raw_readl(s->mem + HW_UARTAPP_STAT) &
+		    BM_UARTAPP_STAT_TXFE)
+			return TIOCSER_TEMT;
+		else
+			return 0;
+	else
+		return stmp3xxx_dma_running(s->dma_tx) ? 0 : TIOCSER_TEMT;
+}
+
+static void stmp_appuart_start_tx(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+	int bytes;
+
+	dev_dbg(s->dev, "%s\n", __func__);
+
+	/* enable transmitter */
+	__raw_writel(BM_UARTAPP_CTRL2_TXE, s->mem + HW_UARTAPP_CTRL2_SET);
+
+	if (!pio_mode) {
+		if (stmp3xxx_dma_running(s->dma_tx))
+			return;
+		bytes = stmp_appuart_copy_tx(u, s->tx_desc.virtual_buf_ptr,
+					     TX_BUFFER_SIZE);
+		if (bytes <= 0)
+			return;
+
+		dev_dbg(s->dev, "Started DMA transfer with descriptor %p, "
+			"command %p, %d bytes long\n",
+			&s->tx_desc, s->tx_desc.command, bytes);
+		stmp_appuart_submit_tx(s, bytes);
+	} else {
+		int count = 0;
+		u8 c;
+
+		while (!
+		       (__raw_readl
+			(s->mem + HW_UARTAPP_STAT) & BM_UARTAPP_STAT_TXFF)) {
+			if (stmp_appuart_copy_tx(u, &c, 1) <= 0)
+				break;
+			dev_dbg(s->dev, "%d: '%c'/%x\n", ++count, chr(c), c);
+			__raw_writel(c, s->mem + HW_UARTAPP_DATA);
+		}
+	}
+}
+
+static void stmp_appuart_stop_tx(struct uart_port *u)
+{
+	struct stmp_appuart_port *s = to_appuart(u);
+
+	dev_dbg(s->dev, "%s\n", __func__);
+	__raw_writel(BM_UARTAPP_CTRL2_TXE, s->mem + HW_UARTAPP_CTRL2_CLR);
+}
+
+static int stmp_appuart_copy_tx(struct uart_port *u, u8 * target,
+				int tx_buffer_size)
+{
+	int last = 0, portion;
+	struct circ_buf *xmit = &u->info->xmit;
+
+	while (last < tx_buffer_size) {	/* let's fill the only descriptor */
+		if (u->x_char) {
+			target[last++] = u->x_char;
+			u->x_char = 0;
+		} else if (!uart_circ_empty(xmit) && !uart_tx_stopped(u)) {
+			portion = min((u32) tx_buffer_size,
+				      (u32) uart_circ_chars_pending(xmit));
+			portion = min((u32) portion,
+				      (u32) CIRC_CNT_TO_END(xmit->head,
+							    xmit->tail,
+							    UART_XMIT_SIZE));
+			memcpy(target + last, &xmit->buf[xmit->tail], portion);
+			xmit->tail = (xmit->tail + portion) &
+			    (UART_XMIT_SIZE - 1);
+			if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+				uart_write_wakeup(u);
+			last += portion;
+		} else {	/* All tx data copied into buffer */
+			return last;
+		}
+	}
+	return last;
+}
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("stmp3xxx app uart driver");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+module_param(pio_mode, int, 0);
diff --git a/drivers/serial/stmp-app.h b/drivers/serial/stmp-app.h
new file mode 100644
index 000000000000..938c89bc5214
--- /dev/null
+++ b/drivers/serial/stmp-app.h
@@ -0,0 +1,82 @@
+/*
+ * Freescale STMP37XX/STMP378X Application UART driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __STMP_APPUART_H
+#define __STMP_APPUART_H
+
+#define RX_BUFFER_SIZE	4
+#define TX_BUFFER_SIZE	0xFFF0
+
+#include <mach/dma.h>
+
+/* #define RX_CHAIN 2 */
+
+struct stmp_appuart_port {
+	int	keep_irq;
+	int	irq[3];
+	void __iomem *mem;
+	u32	memsize;
+	int	dma_rx, dma_tx;
+	struct clk *clk;
+	struct device *dev;
+	struct uart_port port;
+	unsigned tx_buffer_index;
+	struct stmp3xxx_dma_descriptor tx_desc;
+#ifndef RX_CHAIN
+	struct stmp3xxx_dma_descriptor rx_desc;
+#else
+	struct stmp3xxx_dma_descriptor rxd[RX_CHAIN];
+	struct stmp37xx_circ_dma_chain rx_chain;
+#endif
+
+	u32 ctrl;
+	u8 running;
+	spinlock_t lock; /* protects irq handler */
+};
+
+#ifdef CONFIG_CPU_FREQ
+static int stmp_appuart_updateclk(struct device *dev, void *clkdata);
+static int stmp_appuart_notifier(struct notifier_block *self,
+		unsigned long phase, void *p);
+#endif /* CONFIG_CPU_FREQ */
+static int __init stmp_appuart_probe(struct platform_device *device);
+static int stmp_appuart_remove(struct platform_device *device);
+static int stmp_appuart_suspend(struct platform_device *device,
+		pm_message_t state);
+static int stmp_appuart_resume(struct platform_device *device);
+static int __init stmp_appuart_init(void);
+static void __exit stmp_appuart_exit(void);
+static int stmp_appuart_request_port(struct uart_port *u);
+static void stmp_appuart_release_port(struct uart_port *u);
+static int stmp_appuart_verify_port(struct uart_port *u,
+		struct serial_struct *);
+static void stmp_appuart_config_port(struct uart_port *u, int flags);
+static const char *stmp_appuart_type(struct uart_port *u);
+static void stmp_appuart_settermios(struct uart_port *u,
+		struct ktermios *nw, struct ktermios *old);
+static void stmp_appuart_shutdown(struct uart_port *u);
+static int stmp_appuart_startup(struct uart_port *u);
+static u32 stmp_appuart_get_mctrl(struct uart_port *u);
+static void stmp_appuart_set_mctrl(struct uart_port *u, unsigned mctrl);
+static void stmp_appuart_enable_ms(struct uart_port *port);
+static void stmp_appuart_break_ctl(struct uart_port *port, int ctl);
+static unsigned int stmp_appuart_tx_empty(struct uart_port *u);
+static void stmp_appuart_stop_rx(struct uart_port *u);
+static void stmp_appuart_start_tx(struct uart_port *u);
+static void stmp_appuart_stop_tx(struct uart_port *u);
+static int stmp_appuart_copy_tx(struct uart_port *u, u8 *target, int size);
+#endif
diff --git a/drivers/serial/stmp-dbg.c b/drivers/serial/stmp-dbg.c
new file mode 100644
index 000000000000..40040f3df5c9
--- /dev/null
+++ b/drivers/serial/stmp-dbg.c
@@ -0,0 +1,884 @@
+/*
+ *  Freescale STMP37XX/STMP378X Debug UART driver
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  Copyright 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Modifications for STMP36XX Debug Serial (c) 2005 Sigmatel Inc
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/autoconf.h>
+
+#if defined(CONFIG_SERIAL_STMP_DBG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <mach/regs-uartdbg.h>
+
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+
+#include "stmp-dbg.h"
+
+/* treated as variable unless submitted to open-source */
+#define PORT_STMPDBG		100
+#define UART_NR			1
+#define SERIAL_STMPDBG_MAJOR	204
+#define SERIAL_STMPDBG_MINOR	16
+
+#define ISR_PASS_LIMIT		256
+
+#define STMPDBG_DEVID		"Debug UART"
+
+
+static int force_cd = 1;
+
+static struct uart_driver stmpdbg_reg;
+
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct uart_stmpdbg_port {
+	struct uart_port	port;
+	struct clk		*clk;
+	unsigned int		im;	/* interrupt mask */
+	unsigned int		old_status;
+	int			suspended;
+};
+
+
+static void stmpdbg_stop_tx(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+
+	uap->im &= ~UART011_TXIM;
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void stmpdbg_start_tx(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+
+	uap->im |= UART011_TXIM;
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void stmpdbg_stop_rx(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+
+	uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
+		     UART011_PEIM|UART011_BEIM|UART011_OEIM);
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void stmpdbg_enable_ms(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+
+	uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void stmpdbg_rx_chars(struct uart_stmpdbg_port *uap)
+{
+	struct tty_struct *tty = uap->port.info->port.tty;
+	unsigned int status, ch, flag, rsr, max_count = 256;
+
+	status = __raw_readl(uap->port.membase + UART01x_FR);
+	while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
+#if 0
+		if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+			if (tty->low_latency)
+				tty_flip_buffer_push(tty);
+			/*
+			 * If this failed then we will throw away the
+			 * bytes but must do so to clear interrupts
+			 */
+		}
+#endif
+
+		ch = __raw_readl(uap->port.membase + UART01x_DR);
+		flag = TTY_NORMAL;
+		uap->port.icount.rx++;
+
+		/*
+		 * Note that the error handling code is
+		 * out of the main execution path
+		 */
+		rsr = __raw_readl(uap->port.membase + UART01x_RSR)
+			| UART_DUMMY_RSR_RX;
+		if (unlikely(rsr & UART01x_RSR_ANY)) {
+			if (rsr & UART01x_RSR_BE) {
+				rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
+				uap->port.icount.brk++;
+				if (uart_handle_break(&uap->port))
+					goto ignore_char;
+			} else if (rsr & UART01x_RSR_PE)
+				uap->port.icount.parity++;
+			else if (rsr & UART01x_RSR_FE)
+				uap->port.icount.frame++;
+			if (rsr & UART01x_RSR_OE)
+				uap->port.icount.overrun++;
+
+			rsr &= uap->port.read_status_mask;
+
+			if (rsr & UART01x_RSR_BE)
+				flag = TTY_BREAK;
+			else if (rsr & UART01x_RSR_PE)
+				flag = TTY_PARITY;
+			else if (rsr & UART01x_RSR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (uart_handle_sysrq_char(&uap->port, ch))
+			goto ignore_char;
+
+		uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
+
+ignore_char:
+		status = __raw_readl(uap->port.membase + UART01x_FR);
+	}
+	tty_flip_buffer_push(tty);
+	return;
+}
+
+static void stmpdbg_tx_chars(struct uart_stmpdbg_port *uap)
+{
+	struct circ_buf *xmit = &uap->port.info->xmit;
+	int count;
+
+	if (uap->port.x_char) {
+		__raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
+		uap->port.icount.tx++;
+		uap->port.x_char = 0;
+		return;
+	}
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
+		stmpdbg_stop_tx(&uap->port);
+		return;
+	}
+
+	count = uap->port.fifosize >> 1;
+	do {
+		__raw_writel(xmit->buf[xmit->tail],
+				uap->port.membase + UART01x_DR);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		uap->port.icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+	} while (--count > 0);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&uap->port);
+
+	if (uart_circ_empty(xmit))
+		stmpdbg_stop_tx(&uap->port);
+}
+
+static void stmpdbg_modem_status(struct uart_stmpdbg_port *uap)
+{
+	unsigned int status, delta;
+
+	status = __raw_readl(uap->port.membase + UART01x_FR) &
+		UART01x_FR_MODEM_ANY;
+
+	delta = status ^ uap->old_status;
+	uap->old_status = status;
+
+	if (!delta)
+		return;
+
+	if (delta & UART01x_FR_DCD)
+		uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
+
+	if (delta & UART01x_FR_DSR)
+		uap->port.icount.dsr++;
+
+	if (delta & UART01x_FR_CTS)
+		uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
+
+	wake_up_interruptible(&uap->port.info->delta_msr_wait);
+}
+
+static irqreturn_t stmpdbg_int(int irq, void *dev_id)
+{
+	struct uart_stmpdbg_port *uap = dev_id;
+	unsigned int status, pass_counter = ISR_PASS_LIMIT;
+	int handled = 0;
+
+	spin_lock(&uap->port.lock);
+
+	status = __raw_readl(uap->port.membase + UART011_MIS);
+	if (status) {
+		do {
+			__raw_writel(status & ~(UART011_TXIS|UART011_RTIS|
+					  UART011_RXIS),
+			       uap->port.membase + UART011_ICR);
+
+			if (status & (UART011_RTIS|UART011_RXIS))
+				stmpdbg_rx_chars(uap);
+			if (status & (UART011_DSRMIS|UART011_DCDMIS|
+				      UART011_CTSMIS|UART011_RIMIS))
+				stmpdbg_modem_status(uap);
+			if (status & UART011_TXIS)
+				stmpdbg_tx_chars(uap);
+
+			if (pass_counter-- == 0)
+				break;
+
+			status = __raw_readl(uap->port.membase + UART011_MIS);
+		} while (status != 0);
+		handled = 1;
+	}
+
+	spin_unlock(&uap->port.lock);
+
+	return IRQ_RETVAL(handled);
+}
+
+static unsigned int stmpdbg_tx_empty(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
+	return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int stmpdbg_get_mctrl(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned int result = 0;
+	unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
+
+#define TEST_AND_SET_BIT(uartbit, tiocmbit)	do { \
+		if (status & uartbit)		\
+			result |= tiocmbit;	\
+	} while (0)
+
+	TEST_AND_SET_BIT(UART01x_FR_DCD, TIOCM_CAR);
+	TEST_AND_SET_BIT(UART01x_FR_DSR, TIOCM_DSR);
+	TEST_AND_SET_BIT(UART01x_FR_CTS, TIOCM_CTS);
+	TEST_AND_SET_BIT(UART011_FR_RI, TIOCM_RNG);
+#undef TEST_AND_SET_BIT
+	if (force_cd)
+		result |= TIOCM_CAR;
+	return result;
+}
+
+static void stmpdbg_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned int cr;
+
+	cr = __raw_readl(uap->port.membase + UART011_CR);
+
+#define	TEST_AND_SET_BIT(tiocmbit, uartbit)	do { \
+		if (mctrl & tiocmbit)		\
+			cr |= uartbit;		\
+		else				\
+			cr &= ~uartbit;		\
+	} while (0)
+
+	TEST_AND_SET_BIT(TIOCM_RTS, UART011_CR_RTS);
+	TEST_AND_SET_BIT(TIOCM_DTR, UART011_CR_DTR);
+	TEST_AND_SET_BIT(TIOCM_OUT1, UART011_CR_OUT1);
+	TEST_AND_SET_BIT(TIOCM_OUT2, UART011_CR_OUT2);
+	TEST_AND_SET_BIT(TIOCM_LOOP, UART011_CR_LBE);
+#undef TEST_AND_SET_BIT
+
+	__raw_writel(cr, uap->port.membase + UART011_CR);
+}
+
+static void stmpdbg_break_ctl(struct uart_port *port, int break_state)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned long flags;
+	unsigned int lcr_h;
+
+	spin_lock_irqsave(&uap->port.lock, flags);
+	lcr_h = __raw_readl(uap->port.membase + UART011_LCRH);
+	if (break_state == -1)
+		lcr_h |= UART01x_LCRH_BRK;
+	else
+		lcr_h &= ~UART01x_LCRH_BRK;
+	__raw_writel(lcr_h, uap->port.membase + UART011_LCRH);
+	spin_unlock_irqrestore(&uap->port.lock, flags);
+}
+
+static int stmpdbg_startup(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	u32 cr, lcr;
+	int retval;
+
+	/*
+	 * Allocate the IRQ
+	 */
+	retval = request_irq(uap->port.irq, stmpdbg_int, 0, STMPDBG_DEVID, uap);
+	if (retval)
+		return retval;
+
+	__raw_writel(0, uap->port.membase + UART01x_DR); /* wake up the UART */
+
+	__raw_writel(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
+	       uap->port.membase + UART011_IFLS);
+
+	/*
+	 * Provoke TX FIFO interrupt into asserting.
+	 */
+	cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
+	__raw_writel(cr, uap->port.membase + UART011_CR);
+
+	lcr = __raw_readl(uap->port.membase + UART011_LCRH);
+	lcr |= UART01x_LCRH_FEN;
+	__raw_writel(lcr, uap->port.membase + UART011_LCRH);
+
+	/*
+	 * initialise the old status of the modem signals
+	 */
+	uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) &
+		UART01x_FR_MODEM_ANY;
+
+	/*
+	 * Finally, enable interrupts
+	 */
+	spin_lock_irq(&uap->port.lock);
+	uap->im = UART011_RXIM | UART011_RTIM;
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+	spin_unlock_irq(&uap->port.lock);
+
+	return 0;
+}
+
+static void stmpdbg_shutdown(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned long val;
+
+	/*
+	 * disable all interrupts
+	 */
+	spin_lock_irq(&uap->port.lock);
+	uap->im = 0;
+	__raw_writel(uap->im, uap->port.membase + UART011_IMSC);
+	__raw_writel(0xffff, uap->port.membase + UART011_ICR);
+	spin_unlock_irq(&uap->port.lock);
+
+	free_irq(uap->port.irq, uap);
+
+	/*
+	 * disable the port
+	 */
+	__raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE,
+			uap->port.membase + UART011_CR);
+
+	/*
+	 * disable break condition and fifos
+	 */
+	val = __raw_readl(uap->port.membase + UART011_LCRH);
+	val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
+	__raw_writel(val, uap->port.membase + UART011_LCRH);
+}
+
+static void
+stmpdbg_set_termios(struct uart_port *port, struct ktermios *termios,
+		     struct ktermios *old)
+{
+	unsigned int lcr_h, old_cr;
+	unsigned long flags;
+	unsigned int baud, quot;
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+	quot = port->uartclk * 4 / baud;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr_h = UART01x_LCRH_WLEN_5;
+		break;
+	case CS6:
+		lcr_h = UART01x_LCRH_WLEN_6;
+		break;
+	case CS7:
+		lcr_h = UART01x_LCRH_WLEN_7;
+		break;
+	default: /* CS8 */
+		lcr_h = UART01x_LCRH_WLEN_8;
+		break;
+	}
+	if (termios->c_cflag & CSTOPB)
+		lcr_h |= UART01x_LCRH_STP2;
+	if (termios->c_cflag & PARENB) {
+		lcr_h |= UART01x_LCRH_PEN;
+		if (!(termios->c_cflag & PARODD))
+			lcr_h |= UART01x_LCRH_EPS;
+	}
+	lcr_h |= UART01x_LCRH_FEN;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = UART01x_RSR_OE;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= UART01x_RSR_BE;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= UART01x_RSR_BE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= UART01x_RSR_OE;
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set.
+	 */
+	if ((termios->c_cflag & CREAD) == 0)
+		port->ignore_status_mask |= UART_DUMMY_RSR_RX;
+
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		stmpdbg_enable_ms(port);
+
+	/* first, disable everything */
+	old_cr = __raw_readl(port->membase + UART011_CR);
+	__raw_writel(0, port->membase + UART011_CR);
+
+	/* Set baud rate */
+	__raw_writel(quot & 0x3f, port->membase + UART011_FBRD);
+	__raw_writel(quot >> 6, port->membase + UART011_IBRD);
+
+	/*
+	 * ----------v----------v----------v----------v-----
+	 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+	 * ----------^----------^----------^----------^-----
+	 */
+	__raw_writel(lcr_h, port->membase + UART011_LCRH);
+	__raw_writel(old_cr, port->membase + UART011_CR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *stmpdbg_type(struct uart_port *port)
+{
+	return port->type == PORT_STMPDBG ? STMPDBG_DEVID : NULL;
+}
+
+
+/*
+ * Release the memory region(s) being used by 'port'
+ */
+static void stmpdbg_release_port(struct uart_port *port)
+{
+	release_mem_region(port->mapbase, UART_PORT_SIZE);
+}
+
+/*
+ * Request the memory region(s) being used by 'port'
+ */
+static int stmpdbg_request_port(struct uart_port *port)
+{
+	return request_mem_region(port->mapbase, UART_PORT_SIZE, STMPDBG_DEVID)
+			!= NULL ? 0 : -EBUSY;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void stmpdbg_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_STMPDBG;
+		stmpdbg_request_port(port);
+	}
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int stmpdbg_verify_port(struct uart_port *port,
+		struct serial_struct *ser)
+{
+	int ret = 0;
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_STMPDBG)
+		ret = -EINVAL;
+	if (ser->irq < 0 || ser->irq >= NR_IRQS)
+		ret = -EINVAL;
+	if (ser->baud_base < 9600)
+		ret = -EINVAL;
+	return ret;
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+/*
+ * Console polling routines for writing and reading from the UART while
+ * in an interrupt or debug context.
+ */
+
+static int stmpdbg_get_poll_char(struct uart_port *port)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+	unsigned int status;
+
+	/* Wait until a character arrives. */
+
+	do {
+		status = __raw_readl(uap->port.membase + UART01x_FR);
+	} while (status & UART01x_FR_RXFE);
+
+	/* Read the character and return it. */
+
+	return __raw_readl(uap->port.membase + UART01x_DR) & 0xff;
+
+}
+
+static void stmpdbg_put_poll_char(struct uart_port *port, unsigned char c)
+{
+	struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port;
+
+	/* Wait until the transmit FIFO is empty. */
+
+	while (!(__raw_readl(uap->port.membase + UART01x_FR) & UART011_FR_TXFE))
+		barrier();
+
+	/* Transmit the character. */
+
+	__raw_writel(c, uap->port.membase + UART01x_DR);
+
+}
+
+#endif /* CONFIG_CONSOLE_POLL */
+
+static struct uart_ops stmpdbg_pops = {
+	.tx_empty	= stmpdbg_tx_empty,
+	.set_mctrl	= stmpdbg_set_mctrl,
+	.get_mctrl	= stmpdbg_get_mctrl,
+	.stop_tx	= stmpdbg_stop_tx,
+	.start_tx	= stmpdbg_start_tx,
+	.stop_rx	= stmpdbg_stop_rx,
+	.enable_ms	= stmpdbg_enable_ms,
+	.break_ctl	= stmpdbg_break_ctl,
+	.startup	= stmpdbg_startup,
+	.shutdown	= stmpdbg_shutdown,
+	.set_termios	= stmpdbg_set_termios,
+	.type		= stmpdbg_type,
+	.release_port	= stmpdbg_release_port,
+	.request_port	= stmpdbg_request_port,
+	.config_port	= stmpdbg_config_port,
+	.verify_port	= stmpdbg_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_get_char  = stmpdbg_get_poll_char,
+	.poll_put_char  = stmpdbg_put_poll_char,
+#endif
+};
+
+static struct uart_stmpdbg_port stmpdbg_ports[UART_NR] = {
+	{
+		.port	= {
+			/* This *is* the virtual address */
+			.membase	= (void *)REGS_UARTDBG_BASE + HW_UARTDBGDR,
+			.mapbase	= REGS_UARTDBG_PHYS + HW_UARTDBGDR,
+			.iotype		= SERIAL_IO_MEM,
+			.irq		= IRQ_DEBUG_UART,
+			.fifosize	= 16,
+			.ops		= &stmpdbg_pops,
+			.flags		= ASYNC_BOOT_AUTOCONF,
+			.line		= 0,
+			.uartclk	= 24000000,
+		},
+	}
+};
+
+#ifdef CONFIG_SERIAL_STMP_DBG_CONSOLE
+
+static void
+stmpdbg_console_write(struct console *co, const char *s, unsigned int count)
+{
+	struct uart_port *port = &stmpdbg_ports[co->index].port;
+	unsigned int status, old_cr;
+	int i;
+
+	/*
+	 *	First save the CR then disable the interrupts
+	 */
+	old_cr = UART_GET_CR(port);
+	UART_PUT_CR(port, UART01x_CR_UARTEN);
+
+	/*
+	 *	Now, do each character
+	 */
+	for (i = 0; i < count; i++) {
+		do {
+			status = UART_GET_FR(port);
+		} while (!UART_TX_READY(status));
+		UART_PUT_CHAR(port, s[i]);
+		if (s[i] == '\n') {
+			do {
+				status = UART_GET_FR(port);
+			} while (!UART_TX_READY(status));
+			UART_PUT_CHAR(port, '\r');
+		}
+	}
+
+	/*
+	 *	Finally, wait for transmitter to become empty
+	 *	and restore the TCR
+	 */
+	do {
+		status = UART_GET_FR(port);
+	} while (status & UART01x_FR_BUSY);
+	UART_PUT_CR(port, old_cr);
+}
+
+static void __init
+stmpdbg_console_get_options(struct uart_port *port, int *baud,
+			     int *parity, int *bits)
+{
+	if (UART_GET_CR(port) & UART01x_CR_UARTEN) {
+		unsigned int lcr_h, quot;
+		lcr_h = UART_GET_LCRH(port);
+
+		*parity = 'n';
+		if (lcr_h & UART01x_LCRH_PEN) {
+			if (lcr_h & UART01x_LCRH_EPS)
+				*parity = 'e';
+			else
+				*parity = 'o';
+		}
+
+		if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
+			*bits = 7;
+		else
+			*bits = 8;
+
+		quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8;
+		*baud = port->uartclk / (16 * (quot + 1));
+	}
+}
+
+static int __init stmpdbg_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (co->index >= UART_NR)
+		co->index = 0;
+	port = &stmpdbg_ports[co->index].port;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		stmpdbg_console_get_options(port, &baud, &parity, &bits);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+
+static struct console stmpdbg_console = {
+	.name		= "ttyAM",
+	.write		= stmpdbg_console_write,
+	.device		= uart_console_device,
+	.setup		= stmpdbg_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &stmpdbg_reg,
+};
+
+static int __init stmpdbg_console_init(void)
+{
+	/*
+	 * All port initializations are done statically
+	 */
+	register_console(&stmpdbg_console);
+	return 0;
+}
+console_initcall(stmpdbg_console_init);
+
+static int __init stmpdbg_late_console_init(void)
+{
+	if (!(stmpdbg_console.flags & CON_ENABLED))
+		register_console(&stmpdbg_console);
+	return 0;
+}
+late_initcall(stmpdbg_late_console_init);
+
+#endif
+
+static struct uart_driver stmpdbg_reg = {
+	.owner			= THIS_MODULE,
+	.driver_name		= "ttyAM",
+	.dev_name		= "ttyAM",
+	.major			= SERIAL_STMPDBG_MAJOR,
+	.minor			= SERIAL_STMPDBG_MINOR,
+	.nr			= UART_NR,
+#ifdef CONFIG_SERIAL_STMP_DBG_CONSOLE
+	.cons			= &stmpdbg_console,
+#endif
+};
+
+static int __devinit stmpdbguart_probe(struct platform_device *device)
+{
+	int ret = 0;
+	int i;
+	void (*cfg)(int request, int port) = NULL;
+
+	if (device->dev.platform_data)
+		cfg = device->dev.platform_data;
+
+	device_init_wakeup(&device->dev, 1);
+
+	for (i = 0; i < UART_NR; i++) {
+		stmpdbg_ports[i].clk = clk_get(NULL, "uart");
+		if (IS_ERR(stmpdbg_ports[i].clk))
+			continue;
+		stmpdbg_ports[i].suspended = 0;
+		stmpdbg_ports[i].port.dev = &device->dev;
+		stmpdbg_ports[i].port.uartclk =
+			clk_get_rate(stmpdbg_ports[i].clk) * 1000;
+		if (cfg)
+			(*cfg)(1, i);
+		uart_add_one_port(&stmpdbg_reg, &stmpdbg_ports[i].port);
+	}
+	return ret;
+}
+
+static int __devexit stmpdbguart_remove(struct platform_device *device)
+{
+	int i;
+	void (*cfg)(int request, int port) = NULL;
+
+	if (device->dev.platform_data)
+		cfg = device->dev.platform_data;
+	for (i = 0; i < UART_NR; i++) {
+		clk_put(stmpdbg_ports[i].clk);
+		uart_remove_one_port(&stmpdbg_reg, &stmpdbg_ports[0].port);
+		if (cfg)
+			(*cfg)(0, i);
+	}
+	return 0;
+}
+
+static int stmpdbguart_suspend(struct platform_device *device,
+					pm_message_t state)
+{
+#ifdef CONFIG_PM
+	int i;
+	int deep_sleep = (stmp37xx_pm_get_target() != PM_SUSPEND_STANDBY);
+
+	for (i = 0; i < UART_NR; i++) {
+		if (deep_sleep) {
+			uart_suspend_port(&stmpdbg_reg,
+				     &stmpdbg_ports[i].port);
+			clk_disable(stmpdbg_ports[i].clk);
+			stmpdbg_ports[i].suspended = 1;
+		}
+	}
+#endif
+	return 0;
+}
+
+static int stmpdbguart_resume(struct platform_device *device)
+{
+	int ret = 0;
+#ifdef CONFIG_PM
+	int i;
+
+	for (i = 0; i < UART_NR; i++) {
+		if (stmpdbg_ports[i].suspended) {
+			clk_enable(stmpdbg_ports[i].clk);
+			uart_resume_port(&stmpdbg_reg, &stmpdbg_ports[i].port);
+		}
+		stmpdbg_ports[i].suspended = 0;
+	}
+#endif
+	return ret;
+}
+
+static struct platform_driver stmpdbguart_driver = {
+	.probe = stmpdbguart_probe,
+	.remove = __devexit_p(stmpdbguart_remove),
+	.suspend = stmpdbguart_suspend,
+	.resume = stmpdbguart_resume,
+	.driver = {
+		.name = "stmp3xxx-dbguart",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init stmpdbg_init(void)
+{
+	int ret;
+
+	ret = uart_register_driver(&stmpdbg_reg);
+	if (ret)
+		goto out;
+
+	ret = platform_driver_register(&stmpdbguart_driver);
+	if (ret)
+		uart_unregister_driver(&stmpdbg_reg);
+out:
+	return ret;
+}
+
+static void __exit stmpdbg_exit(void)
+{
+	platform_driver_unregister(&stmpdbguart_driver);
+	uart_unregister_driver(&stmpdbg_reg);
+}
+
+module_init(stmpdbg_init);
+module_exit(stmpdbg_exit);
+module_param(force_cd, int, 0644);
+MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd/Sigmatel Inc");
+MODULE_DESCRIPTION("STMP37xx debug uart");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/stmp-dbg.h b/drivers/serial/stmp-dbg.h
new file mode 100644
index 000000000000..38f3e6747fb3
--- /dev/null
+++ b/drivers/serial/stmp-dbg.h
@@ -0,0 +1,180 @@
+/*
+ *  Freescale STMP37XX/STMP378X Debug UART driver
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __STMP_DBG_H
+#define __STMP_DBG_H
+/*
+ * UART register offsets
+ */
+#define UART01x_DR		0x00	/* Data read or written 	*/
+#define UART01x_RSR		0x04	/* Receive status register 	*/
+#define UART01x_ECR		0x04	/* Error clear register (write) */
+#define UART010_LCRH		0x08	/* Line control register, MSB 	*/
+#define UART010_LCRM		0x0C	/* Line control register, 	*/
+#define UART010_LCRL		0x10	/* Line control register, LSB	*/
+#define UART010_CR		0x14	/* Control register. 		*/
+#define UART01x_FR		0x18	/* Flag register (Read only). 	*/
+#define UART010_IIR		0x1C	/* Interrupt identification 	*/
+#define UART010_ICR		0x1C	/* Interrupt clear register	*/
+#define UART01x_ILPR		0x20	/* IrDA low power counter 	*/
+#define UART011_IBRD		0x24	/* Integer baud rate divisor 	*/
+#define UART011_FBRD		0x28	/* Fractional baud rate divisor	*/
+#define UART011_LCRH		0x2c	/* Line control			*/
+#define UART011_CR		0x30	/* Control 			*/
+#define UART011_IFLS		0x34	/* Interrupt fifo level select 	*/
+#define UART011_IMSC		0x38	/* Interrupt mask		*/
+#define UART011_RIS		0x3c	/* Raw  	*/
+#define UART011_MIS		0x40	/* Masked 	*/
+#define UART011_ICR		0x44	/* Interrupt clear register	*/
+#define UART011_DMACR		0x48	/* DMA control register		*/
+
+#define UART011_DR_OE		(1 << 11)
+#define UART011_DR_BE		(1 << 10)
+#define UART011_DR_PE		(1 << 9)
+#define UART011_DR_FE		(1 << 8)
+
+#define UART01x_RSR_OE		0x08
+#define UART01x_RSR_BE		0x04
+#define UART01x_RSR_PE		0x02
+#define UART01x_RSR_FE		0x01
+
+#define UART011_FR_RI		0x100
+#define UART011_FR_TXFE		0x080
+#define UART011_FR_RXFF		0x040
+#define UART01x_FR_TXFF		0x020
+#define UART01x_FR_RXFE		0x010
+#define UART01x_FR_BUSY		0x008
+#define UART01x_FR_DCD		0x004
+#define UART01x_FR_DSR		0x002
+#define UART01x_FR_CTS		0x001
+#define UART01x_FR_TMSK		(UART01x_FR_TXFF + UART01x_FR_BUSY)
+
+#define UART011_CR_CTSEN	0x8000	/* CTS hardware flow control */
+#define UART011_CR_RTSEN	0x4000	/* RTS hardware flow control */
+#define UART011_CR_OUT2		0x2000	/* OUT2 */
+#define UART011_CR_OUT1		0x1000	/* OUT1 */
+#define UART011_CR_RTS		0x0800	/* RTS */
+#define UART011_CR_DTR		0x0400	/* DTR */
+#define UART011_CR_RXE		0x0200	/* receive enable */
+#define UART011_CR_TXE		0x0100	/* transmit enable */
+#define UART011_CR_LBE		0x0080	/* loopback enable */
+#define UART010_CR_RTIE		0x0040
+#define UART010_CR_TIE		0x0020
+#define UART010_CR_RIE		0x0010
+#define UART010_CR_MSIE		0x0008
+#define UART01x_CR_IIRLP	0x0004	/* SIR low power mode */
+#define UART01x_CR_SIREN	0x0002	/* SIR enable */
+#define UART01x_CR_UARTEN	0x0001	/* UART enable */
+
+#define UART011_LCRH_SPS	0x80
+#define UART01x_LCRH_WLEN_8	0x60
+#define UART01x_LCRH_WLEN_7	0x40
+#define UART01x_LCRH_WLEN_6	0x20
+#define UART01x_LCRH_WLEN_5	0x00
+#define UART01x_LCRH_FEN	0x10
+#define UART01x_LCRH_STP2	0x08
+#define UART01x_LCRH_EPS	0x04
+#define UART01x_LCRH_PEN	0x02
+#define UART01x_LCRH_BRK	0x01
+
+#define UART010_IIR_RTIS	0x08
+#define UART010_IIR_TIS		0x04
+#define UART010_IIR_RIS		0x02
+#define UART010_IIR_MIS		0x01
+
+#define UART011_IFLS_RX1_8	(0 << 3)
+#define UART011_IFLS_RX2_8	(1 << 3)
+#define UART011_IFLS_RX4_8	(2 << 3)
+#define UART011_IFLS_RX6_8	(3 << 3)
+#define UART011_IFLS_RX7_8	(4 << 3)
+#define UART011_IFLS_TX1_8	(0 << 0)
+#define UART011_IFLS_TX2_8	(1 << 0)
+#define UART011_IFLS_TX4_8	(2 << 0)
+#define UART011_IFLS_TX6_8	(3 << 0)
+#define UART011_IFLS_TX7_8	(4 << 0)
+
+/* Interrupt masks */
+#define UART011_OEIM		(1 << 10)	/* overrun error 	*/
+#define UART011_BEIM		(1 << 9)	/* break error 		*/
+#define UART011_PEIM		(1 << 8)	/* parity error 	*/
+#define UART011_FEIM		(1 << 7)	/* framing error 	*/
+#define UART011_RTIM		(1 << 6)	/* receive timeout 	*/
+#define UART011_TXIM		(1 << 5)	/* transmit 		*/
+#define UART011_RXIM		(1 << 4)	/* receive 		*/
+#define UART011_DSRMIM		(1 << 3)	/* DSR interrupt mask 	*/
+#define UART011_DCDMIM		(1 << 2)	/* DCD interrupt mask 	*/
+#define UART011_CTSMIM		(1 << 1)	/* CTS interrupt mask 	*/
+#define UART011_RIMIM		(1 << 0)	/* RI interrupt mask 	*/
+
+/* Interrupt statuses */
+#define UART011_OEIS		(1 << 10)	/* overrun error 	*/
+#define UART011_BEIS		(1 << 9)	/* break error 		*/
+#define UART011_PEIS		(1 << 8)	/* parity error 	*/
+#define UART011_FEIS		(1 << 7)	/* framing error  	*/
+#define UART011_RTIS		(1 << 6)	/* receive timeout  	*/
+#define UART011_TXIS		(1 << 5)	/* transmit  		*/
+#define UART011_RXIS		(1 << 4)	/* receive  		*/
+#define UART011_DSRMIS		(1 << 3)	/* DSR  		*/
+#define UART011_DCDMIS		(1 << 2)	/* DCD  		*/
+#define UART011_CTSMIS		(1 << 1)	/* CTS  		*/
+#define UART011_RIMIS		(1 << 0)	/* RI  			*/
+
+/* Interrupt clear masks */
+#define UART011_OEIC		(1 << 10)	/* overrun error 	*/
+#define UART011_BEIC		(1 << 9)	/* break error  	*/
+#define UART011_PEIC		(1 << 8)	/* parity error  	*/
+#define UART011_FEIC		(1 << 7)	/* framing error  	*/
+#define UART011_RTIC		(1 << 6)	/* receive timeout  	*/
+#define UART011_TXIC		(1 << 5)	/* transmit  		*/
+#define UART011_RXIC		(1 << 4)	/* receive  		*/
+#define UART011_DSRMIC		(1 << 3)	/* DSR  		*/
+#define UART011_DCDMIC		(1 << 2)	/* DCD  		*/
+#define UART011_CTSMIC		(1 << 1)	/* CTS  		*/
+#define UART011_RIMIC		(1 << 0)	/* RI  			*/
+
+#define UART011_DMAONERR	(1 << 2)	/* disable dma on error */
+#define UART011_TXDMAE		(1 << 1)	/* enable transmit dma 	*/
+#define UART011_RXDMAE		(1 << 0)	/* enable receive dma 	*/
+
+#define UART01x_RSR_ANY		(UART01x_RSR_OE | UART01x_RSR_BE | \
+				 UART01x_RSR_PE | UART01x_RSR_FE)
+#define UART01x_FR_MODEM_ANY	(UART01x_FR_DCD | UART01x_FR_DSR | \
+				 UART01x_FR_CTS)
+
+/*
+ * Access macros for the AMBA UARTs
+ */
+#define UART_GET_INT_STATUS(p)	readb((p)->membase + UART010_IIR)
+#define UART_PUT_ICR(p, c)	writel((c), (p)->membase + UART010_ICR)
+#define UART_GET_FR(p)		readb((p)->membase + UART01x_FR)
+#define UART_GET_CHAR(p)	readb((p)->membase + UART01x_DR)
+#define UART_PUT_CHAR(p, c)	writel((c), (p)->membase + UART01x_DR)
+#define UART_GET_RSR(p)		readb((p)->membase + UART01x_RSR)
+#define UART_GET_CR(p)		readb((p)->membase + UART010_CR)
+#define UART_PUT_CR(p, c)	writel((c), (p)->membase + UART010_CR)
+#define UART_GET_LCRL(p)	readb((p)->membase + UART010_LCRL)
+#define UART_PUT_LCRL(p, c)	writel((c), (p)->membase + UART010_LCRL)
+#define UART_GET_LCRM(p)	readb((p)->membase + UART010_LCRM)
+#define UART_PUT_LCRM(p, c)	writel((c), (p)->membase + UART010_LCRM)
+#define UART_GET_LCRH(p)	readb((p)->membase + UART010_LCRH)
+#define UART_PUT_LCRH(p, c)	writel((c), (p)->membase + UART010_LCRH)
+#define UART_RX_DATA(s)		(((s) & UART01x_FR_RXFE) == 0)
+#define UART_TX_READY(s)	(((s) & UART01x_FR_TXFF) == 0)
+#define UART_TX_EMPTY(p)	((UART_GET_FR(p) & UART01x_FR_TMSK) == 0)
+
+#define UART_DUMMY_RSR_RX	/*256*/0
+#define UART_PORT_SIZE		64
+
+#endif /* STMP_DBG_H */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2c733c27db2f..736a12ff9045 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -227,6 +227,45 @@ config SPI_XILINX
 	  See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
 	  Product Specification document (DS464) for hardware details.
 
+config SPI_MXC
+	tristate "MXC CSPI controller as SPI Master"
+	depends on ARCH_MXC && SPI_MASTER
+	select SPI_BITBANG
+	help
+	  This implements the SPI master mode using MXC CSPI.
+
+config SPI_MXC_TEST_LOOPBACK
+	bool "LOOPBACK Testing of CSPIs"
+	depends on SPI_MXC
+	select SPI_SPIDEV
+	default n
+
+config SPI_MXC_SELECT1
+	bool "CSPI1"
+	depends on SPI_MXC
+	default y
+
+config SPI_MXC_SELECT2
+	bool "CSPI2"
+	depends on SPI_MXC && (!ARCH_MXC91221)
+	default n
+
+config SPI_MXC_SELECT3
+	bool "CSPI3"
+	depends on SPI_MXC && (ARCH_MX3 || ARCH_MX27 || ARCH_MX25 || ARCH_MX37 || ARCH_MX51)
+	default n
+
+config SPI_STMP3XXX
+	tristate "Freescale STMP37xx/378x SPI/SSP controller"
+	depends on ARCH_STMP3XXX && SPI_MASTER
+	help
+	  SPI driver for Freescale STMP37xx/378x SoC SSP interface
+
+config SPI_MXS
+	tristate "Freescale MXS SPI/SSP controller"
+	depends on ARCH_MXS && SPI_MASTER
+	help
+	  SPI driver for Freescale MXS SoC SSP interface
 #
 # Add new SPI master controllers in alphabetical order above this line
 #
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3de408d294ba..b6dbdf064181 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -29,8 +29,11 @@ obj-$(CONFIG_SPI_MPC8xxx)		+= spi_mpc8xxx.o
 obj-$(CONFIG_SPI_S3C24XX_GPIO)		+= spi_s3c24xx_gpio.o
 obj-$(CONFIG_SPI_S3C24XX)		+= spi_s3c24xx.o
 obj-$(CONFIG_SPI_TXX9)			+= spi_txx9.o
+obj-$(CONFIG_SPI_MXC)			+= mxc_spi.o
 obj-$(CONFIG_SPI_XILINX)		+= xilinx_spi.o
 obj-$(CONFIG_SPI_SH_SCI)		+= spi_sh_sci.o
+obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
+obj-$(CONFIG_SPI_MXS)			+= spi_mxs.o
 # 	... add above this line ...
 
 # SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
new file mode 100644
index 000000000000..d0e23563f2a9
--- /dev/null
+++ b/drivers/spi/mxc_spi.c
@@ -0,0 +1,1312 @@
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-licensisr_locke.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup SPI Configurable Serial Peripheral Interface (CSPI) Driver
+ */
+
+/*!
+ * @file mxc_spi.c
+ * @brief This file contains the implementation of the SPI master controller services
+ *
+ *
+ * @ingroup SPI
+ */
+
+#include <linux/completion.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+#include <mach/hardware.h>
+
+#define MXC_CSPIRXDATA		0x00
+#define MXC_CSPITXDATA		0x04
+#define MXC_CSPICTRL		0x08
+#define MXC_CSPICONFIG		0x08
+#define MXC_CSPIINT			0x0C
+
+#define MXC_CSPICTRL_DISABLE	0x0
+#define MXC_CSPICTRL_SLAVE	0x0
+#define MXC_CSPICTRL_CSMASK	0x3
+#define MXC_CSPICTRL_SMC	(1 << 3)
+
+#define MXC_CSPIINT_TEEN_SHIFT		0
+#define MXC_CSPIINT_THEN_SHIFT	1
+#define MXC_CSPIINT_TFEN_SHIFT		2
+#define MXC_CSPIINT_RREN_SHIFT		3
+#define MXC_CSPIINT_RHEN_SHIFT       4
+#define MXC_CSPIINT_RFEN_SHIFT        5
+#define MXC_CSPIINT_ROEN_SHIFT        6
+
+#define MXC_HIGHPOL	0x0
+#define MXC_NOPHA	0x0
+#define MXC_LOWSSPOL		0x0
+
+#define MXC_CSPISTAT_TE		0
+#define MXC_CSPISTAT_TH		1
+#define MXC_CSPISTAT_TF		2
+#define MXC_CSPISTAT_RR		3
+#define MXC_CSPISTAT_RH		4
+#define MXC_CSPISTAT_RF		5
+#define MXC_CSPISTAT_RO		6
+
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+
+/*!
+ * @struct mxc_spi_unique_def
+ * @brief This structure contains information that differs with
+ * SPI master controller hardware version
+ */
+struct mxc_spi_unique_def {
+	/* Width of valid bits in MXC_CSPIINT */
+	unsigned int intr_bit_shift;
+	/* Chip Select shift */
+	unsigned int cs_shift;
+	/* Bit count shift */
+	unsigned int bc_shift;
+	/* Bit count mask */
+	unsigned int bc_mask;
+	/* Data Control shift */
+	unsigned int drctrl_shift;
+	/* Transfer Complete shift */
+	unsigned int xfer_complete;
+	/* Bit counnter overflow shift */
+	unsigned int bc_overflow;
+	/* FIFO Size */
+	unsigned int fifo_size;
+	/* Control reg address */
+	unsigned int ctrl_reg_addr;
+	/* Status reg address */
+	unsigned int stat_reg_addr;
+	/* Period reg address */
+	unsigned int period_reg_addr;
+	/* Test reg address */
+	unsigned int test_reg_addr;
+	/* Reset reg address */
+	unsigned int reset_reg_addr;
+	/* SPI mode mask */
+	unsigned int mode_mask;
+	/* SPI enable */
+	unsigned int spi_enable;
+	/* XCH bit */
+	unsigned int xch;
+	/* Spi mode shift */
+	unsigned int mode_shift;
+	/* Spi master mode enable */
+	unsigned int master_enable;
+	/* TX interrupt enable diff */
+	unsigned int tx_inten_dif;
+	/* RX interrupt enable bit diff */
+	unsigned int rx_inten_dif;
+	/* Interrupt status diff */
+	unsigned int int_status_dif;
+	/* Low pol shift */
+	unsigned int low_pol_shift;
+	/* Phase shift */
+	unsigned int pha_shift;
+	/* SS control shift */
+	unsigned int ss_ctrl_shift;
+	/* SS pol shift */
+	unsigned int ss_pol_shift;
+	/* Maximum data rate */
+	unsigned int max_data_rate;
+	/* Data mask */
+	unsigned int data_mask;
+	/* Data shift */
+	unsigned int data_shift;
+	/* Loopback control */
+	unsigned int lbc;
+	/* RX count off */
+	unsigned int rx_cnt_off;
+	/* RX count mask */
+	unsigned int rx_cnt_mask;
+	/* Reset start */
+	unsigned int reset_start;
+	/* SCLK control inactive state shift */
+	unsigned int sclk_ctl_shift;
+};
+
+struct mxc_spi;
+
+/*!
+ * Structure to group together all the data buffers and functions
+ * used in data transfers.
+ */
+struct mxc_spi_xfer {
+	/* Transmit buffer */
+	const void *tx_buf;
+	/* Receive buffer */
+	void *rx_buf;
+	/* Data transfered count */
+	unsigned int count;
+	/* Data received count, descending sequence, zero means no more data to
+	   be received */
+	unsigned int rx_count;
+	/* Function to read the FIFO data to rx_buf */
+	void (*rx_get) (struct mxc_spi *, u32 val);
+	/* Function to get the data to be written to FIFO */
+	 u32(*tx_get) (struct mxc_spi *);
+};
+
+/*!
+ * This structure is a way for the low level driver to define their own
+ * \b spi_master structure. This structure includes the core \b spi_master
+ * structure that is provided by Linux SPI Framework/driver as an
+ * element and has other elements that are specifically required by this
+ * low-level driver.
+ */
+struct mxc_spi {
+	/* SPI Master and a simple I/O queue runner */
+	struct spi_bitbang mxc_bitbang;
+	/* Completion flags used in data transfers */
+	struct completion xfer_done;
+	/* Data transfer structure */
+	struct mxc_spi_xfer transfer;
+	/* Resource structure, which will maintain base addresses and IRQs */
+	struct resource *res;
+	/* Base address of CSPI, used in readl and writel */
+	void *base;
+	/* CSPI IRQ number */
+	int irq;
+	/* CSPI Clock id */
+	struct clk *clk;
+	/* CSPI input clock SCLK */
+	unsigned long spi_ipg_clk;
+	/* CSPI registers' bit pattern */
+	struct mxc_spi_unique_def *spi_ver_def;
+	/* Control reg address */
+	void *ctrl_addr;
+	/* Status reg address */
+	void *stat_addr;
+	/* Period reg address */
+	void *period_addr;
+	/* Test reg address */
+	void *test_addr;
+	/* Reset reg address */
+	void *reset_addr;
+	/* Chipselect active function */
+	void (*chipselect_active) (int cspi_mode, int status, int chipselect);
+	/* Chipselect inactive function */
+	void (*chipselect_inactive) (int cspi_mode, int status, int chipselect);
+};
+
+#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
+struct spi_chip_info {
+	int lb_enable;
+};
+
+static struct spi_chip_info lb_chip_info = {
+	.lb_enable = 1,
+};
+
+static struct spi_board_info loopback_info[] = {
+#ifdef CONFIG_SPI_MXC_SELECT1
+	{
+	 .modalias = "spidev",
+	 .controller_data = &lb_chip_info,
+	 .irq = 0,
+	 .max_speed_hz = 4000000,
+	 .bus_num = 1,
+	 .chip_select = 4,
+	 },
+#endif
+#ifdef CONFIG_SPI_MXC_SELECT2
+	{
+	 .modalias = "spidev",
+	 .controller_data = &lb_chip_info,
+	 .irq = 0,
+	 .max_speed_hz = 4000000,
+	 .bus_num = 2,
+	 .chip_select = 4,
+	 },
+#endif
+#ifdef CONFIG_SPI_MXC_SELECT3
+	{
+	 .modalias = "spidev",
+	 .controller_data = &lb_chip_info,
+	 .irq = 0,
+	 .max_speed_hz = 4000000,
+	 .bus_num = 3,
+	 .chip_select = 4,
+	 },
+#endif
+};
+#endif
+
+static struct mxc_spi_unique_def spi_ver_2_3 = {
+	.intr_bit_shift = 8,
+	.cs_shift = 18,
+	.bc_shift = 20,
+	.bc_mask = 0xFFF,
+	.drctrl_shift = 16,
+	.xfer_complete = (1 << 7),
+	.bc_overflow = 0,
+	.fifo_size = 64,
+	.ctrl_reg_addr = 4,
+	.stat_reg_addr = 0x18,
+	.period_reg_addr = 0x1C,
+	.test_reg_addr = 0x20,
+	.reset_reg_addr = 0x8,
+	.mode_mask = 0xF,
+	.spi_enable = 0x1,
+	.xch = (1 << 2),
+	.mode_shift = 4,
+	.master_enable = 0,
+	.tx_inten_dif = 0,
+	.rx_inten_dif = 0,
+	.int_status_dif = 0,
+	.low_pol_shift = 4,
+	.pha_shift = 0,
+	.ss_ctrl_shift = 8,
+	.ss_pol_shift = 12,
+	.max_data_rate = 0xF,
+	.data_mask = 0xFF,
+	.data_shift = 8,
+	.lbc = (1 << 31),
+	.rx_cnt_off = 8,
+	.rx_cnt_mask = (0x7F << 8),
+	.reset_start = 0,
+	.sclk_ctl_shift = 20,
+};
+
+static struct mxc_spi_unique_def spi_ver_0_7 = {
+	.intr_bit_shift = 8,
+	.cs_shift = 12,
+	.bc_shift = 20,
+	.bc_mask = 0xFFF,
+	.drctrl_shift = 8,
+	.xfer_complete = (1 << 7),
+	.bc_overflow = 0,
+	.fifo_size = 8,
+	.ctrl_reg_addr = 0,
+	.stat_reg_addr = 0x14,
+	.period_reg_addr = 0x18,
+	.test_reg_addr = 0x1C,
+	.reset_reg_addr = 0x0,
+	.mode_mask = 0x1,
+	.spi_enable = 0x1,
+	.xch = (1 << 2),
+	.mode_shift = 1,
+	.master_enable = 1 << 1,
+	.tx_inten_dif = 0,
+	.rx_inten_dif = 0,
+	.int_status_dif = 0,
+	.low_pol_shift = 4,
+	.pha_shift = 5,
+	.ss_ctrl_shift = 6,
+	.ss_pol_shift = 7,
+	.max_data_rate = 0x7,
+	.data_mask = 0x7,
+	.data_shift = 16,
+	.lbc = (1 << 14),
+	.rx_cnt_off = 4,
+	.rx_cnt_mask = (0xF << 4),
+	.reset_start = 1,
+};
+
+static struct mxc_spi_unique_def spi_ver_0_5 = {
+	.intr_bit_shift = 9,
+	.cs_shift = 12,
+	.bc_shift = 20,
+	.bc_mask = 0xFFF,
+	.drctrl_shift = 8,
+	.xfer_complete = (1 << 8),
+	.bc_overflow = (1 << 7),
+	.fifo_size = 8,
+	.ctrl_reg_addr = 0,
+	.stat_reg_addr = 0x14,
+	.period_reg_addr = 0x18,
+	.test_reg_addr = 0x1C,
+	.reset_reg_addr = 0x0,
+	.mode_mask = 0x1,
+	.spi_enable = 0x1,
+	.xch = (1 << 2),
+	.mode_shift = 1,
+	.master_enable = 1 << 1,
+	.tx_inten_dif = 0,
+	.rx_inten_dif = 0,
+	.int_status_dif = 0,
+	.low_pol_shift = 4,
+	.pha_shift = 5,
+	.ss_ctrl_shift = 6,
+	.ss_pol_shift = 7,
+	.max_data_rate = 0x7,
+	.data_mask = 0x7,
+	.data_shift = 16,
+	.lbc = (1 << 14),
+	.rx_cnt_off = 4,
+	.rx_cnt_mask = (0xF << 4),
+	.reset_start = 1,
+};
+
+static struct mxc_spi_unique_def spi_ver_0_4 = {
+	.intr_bit_shift = 9,
+	.cs_shift = 24,
+	.bc_shift = 8,
+	.bc_mask = 0x1F,
+	.drctrl_shift = 20,
+	.xfer_complete = (1 << 8),
+	.bc_overflow = (1 << 7),
+	.fifo_size = 8,
+	.ctrl_reg_addr = 0,
+	.stat_reg_addr = 0x14,
+	.period_reg_addr = 0x18,
+	.test_reg_addr = 0x1C,
+	.reset_reg_addr = 0x0,
+	.mode_mask = 0x1,
+	.spi_enable = 0x1,
+	.xch = (1 << 2),
+	.mode_shift = 1,
+	.master_enable = 1 << 1,
+	.tx_inten_dif = 0,
+	.rx_inten_dif = 0,
+	.int_status_dif = 0,
+	.low_pol_shift = 4,
+	.pha_shift = 5,
+	.ss_ctrl_shift = 6,
+	.ss_pol_shift = 7,
+	.max_data_rate = 0x7,
+	.data_mask = 0x7,
+	.data_shift = 16,
+	.lbc = (1 << 14),
+	.rx_cnt_off = 4,
+	.rx_cnt_mask = (0xF << 4),
+	.reset_start = 1,
+};
+
+static struct mxc_spi_unique_def spi_ver_0_0 = {
+	.intr_bit_shift = 18,
+	.cs_shift = 19,
+	.bc_shift = 0,
+	.bc_mask = 0x1F,
+	.drctrl_shift = 12,
+	.xfer_complete = (1 << 3),
+	.bc_overflow = (1 << 8),
+	.fifo_size = 8,
+	.ctrl_reg_addr = 0,
+	.stat_reg_addr = 0x0C,
+	.period_reg_addr = 0x14,
+	.test_reg_addr = 0x10,
+	.reset_reg_addr = 0x1C,
+	.mode_mask = 0x1,
+	.spi_enable = (1 << 10),
+	.xch = (1 << 9),
+	.mode_shift = 11,
+	.master_enable = 1 << 11,
+	.tx_inten_dif = 9,
+	.rx_inten_dif = 10,
+	.int_status_dif = 1,
+	.low_pol_shift = 5,
+	.pha_shift = 6,
+	.ss_ctrl_shift = 7,
+	.ss_pol_shift = 8,
+	.max_data_rate = 0x10,
+	.data_mask = 0x1F,
+	.data_shift = 14,
+	.lbc = (1 << 14),
+	.rx_cnt_off = 4,
+	.rx_cnt_mask = (0xF << 4),
+	.reset_start = 1,
+};
+
+extern void gpio_spi_active(int cspi_mod);
+extern void gpio_spi_inactive(int cspi_mod);
+
+#define MXC_SPI_BUF_RX(type)	\
+void mxc_spi_buf_rx_##type(struct mxc_spi *master_drv_data, u32 val)\
+{\
+	type *rx = master_drv_data->transfer.rx_buf;\
+	*rx++ = (type)val;\
+	master_drv_data->transfer.rx_buf = rx;\
+}
+
+#define MXC_SPI_BUF_TX(type)    \
+u32 mxc_spi_buf_tx_##type(struct mxc_spi *master_drv_data)\
+{\
+	u32 val;\
+	const type *tx = master_drv_data->transfer.tx_buf;\
+	val = *tx++;\
+	master_drv_data->transfer.tx_buf = tx;\
+	return val;\
+}
+
+MXC_SPI_BUF_RX(u8)
+    MXC_SPI_BUF_TX(u8)
+    MXC_SPI_BUF_RX(u16)
+    MXC_SPI_BUF_TX(u16)
+    MXC_SPI_BUF_RX(u32)
+    MXC_SPI_BUF_TX(u32)
+
+/*!
+ * This function enables CSPI interrupt(s)
+ *
+ * @param        master_data the pointer to mxc_spi structure
+ * @param        irqs        the irq(s) to set (can be a combination)
+ *
+ * @return       This function returns 0 if successful, -1 otherwise.
+ */
+static int spi_enable_interrupt(struct mxc_spi *master_data, unsigned int irqs)
+{
+	if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) {
+		return -1;
+	}
+
+	__raw_writel((irqs | __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)),
+		     MXC_CSPIINT + master_data->ctrl_addr);
+	return 0;
+}
+
+/*!
+ * This function disables CSPI interrupt(s)
+ *
+ * @param        master_data the pointer to mxc_spi structure
+ * @param        irqs        the irq(s) to reset (can be a combination)
+ *
+ * @return       This function returns 0 if successful, -1 otherwise.
+ */
+static int spi_disable_interrupt(struct mxc_spi *master_data, unsigned int irqs)
+{
+	if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) {
+		return -1;
+	}
+
+	__raw_writel((~irqs &
+		      __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)),
+		     MXC_CSPIINT + master_data->ctrl_addr);
+	return 0;
+}
+
+/*!
+ * This function sets the baud rate for the SPI module.
+ *
+ * @param        master_data the pointer to mxc_spi structure
+ * @param        baud        the baud rate
+ *
+ * @return       This function returns the baud rate divisor.
+ */
+static unsigned int spi_find_baudrate(struct mxc_spi *master_data,
+				      unsigned int baud)
+{
+	unsigned int divisor;
+	unsigned int shift = 0;
+
+	/* Calculate required divisor (rounded) */
+	divisor = (master_data->spi_ipg_clk + baud / 2) / baud;
+	while (divisor >>= 1)
+		shift++;
+
+	if (master_data->spi_ver_def == &spi_ver_0_0) {
+		shift = (shift - 1) * 2;
+	} else if (master_data->spi_ver_def == &spi_ver_2_3) {
+		shift = shift;
+	} else {
+		shift -= 2;
+	}
+
+	if (shift > master_data->spi_ver_def->max_data_rate)
+		shift = master_data->spi_ver_def->max_data_rate;
+
+	return (shift << master_data->spi_ver_def->data_shift);
+}
+
+/*!
+ * This function loads the transmit fifo.
+ *
+ * @param  base             the CSPI base address
+ * @param  count            number of words to put in the TxFIFO
+ * @param  master_drv_data  spi master structure
+ */
+static void spi_put_tx_data(void *base, unsigned int count,
+			    struct mxc_spi *master_drv_data)
+{
+	unsigned int ctrl_reg;
+	unsigned int data;
+	int i = 0;
+
+	/* Perform Tx transaction */
+	for (i = 0; i < count; i++) {
+		data = master_drv_data->transfer.tx_get(master_drv_data);
+		__raw_writel(data, base + MXC_CSPITXDATA);
+	}
+
+	ctrl_reg = __raw_readl(base + MXC_CSPICTRL);
+
+	ctrl_reg |= master_drv_data->spi_ver_def->xch;
+
+	__raw_writel(ctrl_reg, base + MXC_CSPICTRL);
+
+	return;
+}
+
+/*!
+ * This function configures the hardware CSPI for the current SPI device.
+ * It sets the word size, transfer mode, data rate for this device.
+ *
+ * @param       spi     	the current SPI device
+ * @param	is_active 	indicates whether to active/deactivate the current device
+ */
+void mxc_spi_chipselect(struct spi_device *spi, int is_active)
+{
+	struct mxc_spi *master_drv_data;
+	struct mxc_spi_xfer *ptransfer;
+	struct mxc_spi_unique_def *spi_ver_def;
+	unsigned int ctrl_reg = 0;
+	unsigned int config_reg = 0;
+	unsigned int xfer_len;
+	unsigned int cs_value;
+
+	if (is_active == BITBANG_CS_INACTIVE) {
+		/*Need to deselect the slave */
+		return;
+	}
+
+	/* Get the master controller driver data from spi device's master */
+
+	master_drv_data = spi_master_get_devdata(spi->master);
+	clk_enable(master_drv_data->clk);
+	spi_ver_def = master_drv_data->spi_ver_def;
+
+	xfer_len = spi->bits_per_word;
+
+	if (spi_ver_def == &spi_ver_2_3) {
+		/* Control Register Settings for transfer to this slave */
+		ctrl_reg = master_drv_data->spi_ver_def->spi_enable;
+		ctrl_reg |=
+		    ((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def->
+		     cs_shift);
+		ctrl_reg |=
+		    (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+		      spi_ver_def->mode_mask) << spi_ver_def->mode_shift);
+		ctrl_reg |=
+		    spi_find_baudrate(master_drv_data, spi->max_speed_hz);
+		ctrl_reg |=
+		    (((xfer_len -
+		       1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift);
+
+		if (spi->mode & SPI_CPHA)
+			config_reg |=
+			    (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+			      spi_ver_def->mode_mask) <<
+			     spi_ver_def->pha_shift);
+
+		if ((spi->mode & SPI_CPOL)) {
+			config_reg |=
+			    (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+			      spi_ver_def->mode_mask) <<
+			     spi_ver_def->low_pol_shift);
+			config_reg |=
+			    (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+			      spi_ver_def->mode_mask) <<
+			     spi_ver_def->sclk_ctl_shift);
+		}
+		cs_value = (__raw_readl(MXC_CSPICONFIG +
+					master_drv_data->ctrl_addr) >>
+			    spi_ver_def->ss_pol_shift) & spi_ver_def->mode_mask;
+		if (spi->mode & SPI_CS_HIGH) {
+			config_reg |=
+			    ((((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+			       spi_ver_def->mode_mask) | cs_value) <<
+			     spi_ver_def->ss_pol_shift);
+		} else
+			config_reg |=
+			    ((~((1 << (spi->chip_select &
+				       MXC_CSPICTRL_CSMASK)) &
+				spi_ver_def->mode_mask) & cs_value) <<
+			     spi_ver_def->ss_pol_shift);
+		config_reg |=
+		    (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) &
+		      spi_ver_def->mode_mask) << spi_ver_def->ss_ctrl_shift);
+		__raw_writel(0, master_drv_data->base + MXC_CSPICTRL);
+		__raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL);
+		__raw_writel(config_reg,
+			     MXC_CSPICONFIG + master_drv_data->ctrl_addr);
+	} else {
+		/* Control Register Settings for transfer to this slave */
+		ctrl_reg = master_drv_data->spi_ver_def->spi_enable;
+		ctrl_reg |=
+		    (((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def->
+		      cs_shift) | spi_ver_def->mode_mask <<
+		     spi_ver_def->mode_shift);
+		ctrl_reg |=
+		    spi_find_baudrate(master_drv_data, spi->max_speed_hz);
+		ctrl_reg |=
+		    (((xfer_len -
+		       1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift);
+		if (spi->mode & SPI_CPHA)
+			ctrl_reg |=
+			    spi_ver_def->mode_mask << spi_ver_def->pha_shift;
+		if (spi->mode & SPI_CPOL)
+			ctrl_reg |=
+			    spi_ver_def->mode_mask << spi_ver_def->
+			    low_pol_shift;
+		if (spi->mode & SPI_CS_HIGH)
+			ctrl_reg |=
+			    spi_ver_def->mode_mask << spi_ver_def->ss_pol_shift;
+		if (spi_ver_def == &spi_ver_0_7)
+			ctrl_reg |=
+			    spi_ver_def->mode_mask << spi_ver_def->
+			    ss_ctrl_shift;
+
+		__raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL);
+	}
+
+	/* Initialize the functions for transfer */
+	ptransfer = &master_drv_data->transfer;
+	if (xfer_len <= 8) {
+		ptransfer->rx_get = mxc_spi_buf_rx_u8;
+		ptransfer->tx_get = mxc_spi_buf_tx_u8;
+	} else if (xfer_len <= 16) {
+		ptransfer->rx_get = mxc_spi_buf_rx_u16;
+		ptransfer->tx_get = mxc_spi_buf_tx_u16;
+	} else {
+		ptransfer->rx_get = mxc_spi_buf_rx_u32;
+		ptransfer->tx_get = mxc_spi_buf_tx_u32;
+	}
+#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
+	{
+		struct spi_chip_info *lb_chip =
+		    (struct spi_chip_info *)spi->controller_data;
+		if (!lb_chip)
+			__raw_writel(0, master_drv_data->test_addr);
+		else if (lb_chip->lb_enable)
+			__raw_writel(spi_ver_def->lbc,
+				     master_drv_data->test_addr);
+	}
+#endif
+	clk_disable(master_drv_data->clk);
+	return;
+}
+
+/*!
+ * This function is called when an interrupt occurs on the SPI modules.
+ * It is the interrupt handler for the SPI modules.
+ *
+ * @param        irq        the irq number
+ * @param        dev_id     the pointer on the device
+ *
+ * @return       The function returns IRQ_HANDLED when handled.
+ */
+static irqreturn_t mxc_spi_isr(int irq, void *dev_id)
+{
+	struct mxc_spi *master_drv_data = dev_id;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned int status;
+	int fifo_size;
+	unsigned int pass_counter;
+
+	fifo_size = master_drv_data->spi_ver_def->fifo_size;
+	pass_counter = fifo_size;
+
+	/* Read the interrupt status register to determine the source */
+	status = __raw_readl(master_drv_data->stat_addr);
+	do {
+		u32 rx_tmp =
+		    __raw_readl(master_drv_data->base + MXC_CSPIRXDATA);
+
+		if (master_drv_data->transfer.rx_buf)
+			master_drv_data->transfer.rx_get(master_drv_data,
+							 rx_tmp);
+		(master_drv_data->transfer.count)--;
+		(master_drv_data->transfer.rx_count)--;
+		ret = IRQ_HANDLED;
+		if (pass_counter-- == 0) {
+			break;
+		}
+		status = __raw_readl(master_drv_data->stat_addr);
+	} while (status &
+		 (1 <<
+		  (MXC_CSPISTAT_RR +
+		   master_drv_data->spi_ver_def->int_status_dif)));
+
+	if (master_drv_data->transfer.rx_count)
+		return ret;
+
+	if (master_drv_data->transfer.count) {
+		if (master_drv_data->transfer.tx_buf) {
+			u32 count = (master_drv_data->transfer.count >
+				     fifo_size) ? fifo_size :
+			    master_drv_data->transfer.count;
+			master_drv_data->transfer.rx_count = count;
+			spi_put_tx_data(master_drv_data->base, count,
+					master_drv_data);
+		}
+	} else {
+		complete(&master_drv_data->xfer_done);
+	}
+
+	return ret;
+}
+
+/*!
+ * This function initialize the current SPI device.
+ *
+ * @param        spi     the current SPI device.
+ *
+ */
+int mxc_spi_setup(struct spi_device *spi)
+{
+	if (spi->max_speed_hz < 0) {
+		return -EINVAL;
+	}
+
+	if (!spi->bits_per_word)
+		spi->bits_per_word = 8;
+
+	pr_debug("%s: mode %d, %u bpw, %d hz\n", __FUNCTION__,
+		 spi->mode, spi->bits_per_word, spi->max_speed_hz);
+
+	return 0;
+}
+
+static int mxc_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
+{
+	return 0;
+}
+
+/*!
+ * This function is called when the data has to transfer from/to the
+ * current SPI device in poll mode
+ *
+ * @param        spi        the current spi device
+ * @param        t          the transfer request - read/write buffer pairs
+ *
+ * @return       Returns 0 on success.
+ */
+int mxc_spi_poll_transfer(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct mxc_spi *master_drv_data = NULL;
+	int count, i;
+	volatile unsigned int status;
+	u32 rx_tmp;
+	u32 fifo_size;
+	int chipselect_status;
+
+	mxc_spi_chipselect(spi, BITBANG_CS_ACTIVE);
+
+	/* Get the master controller driver data from spi device's master */
+	master_drv_data = spi_master_get_devdata(spi->master);
+
+	chipselect_status = __raw_readl(MXC_CSPICONFIG +
+					master_drv_data->ctrl_addr);
+	chipselect_status >>= master_drv_data->spi_ver_def->ss_pol_shift &
+	    master_drv_data->spi_ver_def->mode_mask;
+	if (master_drv_data->chipselect_active)
+		master_drv_data->chipselect_active(spi->master->bus_num,
+						   chipselect_status,
+						   (spi->chip_select &
+						    MXC_CSPICTRL_CSMASK) + 1);
+
+	clk_enable(master_drv_data->clk);
+
+	/* Modify the Tx, Rx, Count */
+	master_drv_data->transfer.tx_buf = t->tx_buf;
+	master_drv_data->transfer.rx_buf = t->rx_buf;
+	master_drv_data->transfer.count = t->len;
+	fifo_size = master_drv_data->spi_ver_def->fifo_size;
+
+	count = (t->len > fifo_size) ? fifo_size : t->len;
+	spi_put_tx_data(master_drv_data->base, count, master_drv_data);
+
+	while ((((status = __raw_readl(master_drv_data->test_addr)) &
+		 master_drv_data->spi_ver_def->rx_cnt_mask) >> master_drv_data->
+		spi_ver_def->rx_cnt_off) != count) ;
+
+	for (i = 0; i < count; i++) {
+		rx_tmp = __raw_readl(master_drv_data->base + MXC_CSPIRXDATA);
+		master_drv_data->transfer.rx_get(master_drv_data, rx_tmp);
+	}
+
+	clk_disable(master_drv_data->clk);
+	if (master_drv_data->chipselect_inactive)
+		master_drv_data->chipselect_inactive(spi->master->bus_num,
+						     chipselect_status,
+						     (spi->chip_select &
+						      MXC_CSPICTRL_CSMASK) + 1);
+	return 0;
+}
+
+/*!
+ * This function is called when the data has to transfer from/to the
+ * current SPI device. It enables the Rx interrupt, initiates the transfer.
+ * When Rx interrupt occurs, the completion flag is set. It then disables
+ * the Rx interrupt.
+ *
+ * @param        spi        the current spi device
+ * @param        t          the transfer request - read/write buffer pairs
+ *
+ * @return       Returns 0 on success -1 on failure.
+ */
+int mxc_spi_transfer(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct mxc_spi *master_drv_data = NULL;
+	int count;
+	int chipselect_status;
+	u32 fifo_size;
+
+	/* Get the master controller driver data from spi device's master */
+
+	master_drv_data = spi_master_get_devdata(spi->master);
+
+	chipselect_status = __raw_readl(MXC_CSPICONFIG +
+					master_drv_data->ctrl_addr);
+	chipselect_status >>= master_drv_data->spi_ver_def->ss_pol_shift &
+	    master_drv_data->spi_ver_def->mode_mask;
+	if (master_drv_data->chipselect_active)
+		master_drv_data->chipselect_active(spi->master->bus_num,
+						   chipselect_status,
+						   (spi->chip_select &
+						    MXC_CSPICTRL_CSMASK) + 1);
+
+	clk_enable(master_drv_data->clk);
+	/* Modify the Tx, Rx, Count */
+	master_drv_data->transfer.tx_buf = t->tx_buf;
+	master_drv_data->transfer.rx_buf = t->rx_buf;
+	master_drv_data->transfer.count = t->len;
+	fifo_size = master_drv_data->spi_ver_def->fifo_size;
+	INIT_COMPLETION(master_drv_data->xfer_done);
+
+	/* Enable the Rx Interrupts */
+
+	spi_enable_interrupt(master_drv_data,
+			     1 << (MXC_CSPIINT_RREN_SHIFT +
+				   master_drv_data->spi_ver_def->rx_inten_dif));
+	count = (t->len > fifo_size) ? fifo_size : t->len;
+
+	/* Perform Tx transaction */
+	master_drv_data->transfer.rx_count = count;
+	spi_put_tx_data(master_drv_data->base, count, master_drv_data);
+
+	/* Wait for transfer completion */
+	wait_for_completion(&master_drv_data->xfer_done);
+
+	/* Disable the Rx Interrupts */
+
+	spi_disable_interrupt(master_drv_data,
+			      1 << (MXC_CSPIINT_RREN_SHIFT +
+				    master_drv_data->spi_ver_def->
+				    rx_inten_dif));
+
+	clk_disable(master_drv_data->clk);
+	if (master_drv_data->chipselect_inactive)
+		master_drv_data->chipselect_inactive(spi->master->bus_num,
+						     chipselect_status,
+						     (spi->chip_select &
+						      MXC_CSPICTRL_CSMASK) + 1);
+	return (t->len - master_drv_data->transfer.count);
+}
+
+/*!
+ * This function releases the current SPI device's resources.
+ *
+ * @param        spi     the current SPI device.
+ *
+ */
+void mxc_spi_cleanup(struct spi_device *spi)
+{
+}
+
+/*!
+ * This function is called during the driver binding process. Based on the CSPI
+ * hardware module that is being probed this function adds the appropriate SPI module
+ * structure in the SPI core driver.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions.
+ *
+ * @return  The function returns 0 on successful registration and initialization
+ *          of CSPI module. Otherwise returns specific error code.
+ */
+static int mxc_spi_probe(struct platform_device *pdev)
+{
+	struct mxc_spi_master *mxc_platform_info;
+	struct spi_master *master;
+	struct mxc_spi *master_drv_data = NULL;
+	unsigned int spi_ver;
+	int ret = -ENODEV;
+
+	/* Get the platform specific data for this master device */
+
+	mxc_platform_info = (struct mxc_spi_master *)pdev->dev.platform_data;
+	if (!mxc_platform_info) {
+		dev_err(&pdev->dev, "can't get the platform data for CSPI\n");
+		return -EINVAL;
+	}
+
+	/* Allocate SPI master controller */
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi));
+	if (!master) {
+		dev_err(&pdev->dev, "can't alloc for spi_master\n");
+		return -ENOMEM;
+	}
+
+	/* Set this device's driver data to master */
+
+	platform_set_drvdata(pdev, master);
+
+	/* Set this master's data from platform_info */
+
+	master->bus_num = pdev->id + 1;
+	master->num_chipselect = mxc_platform_info->maxchipselect;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
+	master->num_chipselect += 1;
+#endif
+	/* Set the master controller driver data for this master */
+
+	master_drv_data = spi_master_get_devdata(master);
+	master_drv_data->mxc_bitbang.master = spi_master_get(master);
+	if (mxc_platform_info->chipselect_active)
+		master_drv_data->chipselect_active =
+		    mxc_platform_info->chipselect_active;
+	if (mxc_platform_info->chipselect_inactive)
+		master_drv_data->chipselect_inactive =
+		    mxc_platform_info->chipselect_inactive;
+
+	/* Identify SPI version */
+
+	spi_ver = mxc_platform_info->spi_version;
+	if (spi_ver == 7) {
+		master_drv_data->spi_ver_def = &spi_ver_0_7;
+	} else if (spi_ver == 5) {
+		master_drv_data->spi_ver_def = &spi_ver_0_5;
+	} else if (spi_ver == 4) {
+		master_drv_data->spi_ver_def = &spi_ver_0_4;
+	} else if (spi_ver == 0) {
+		master_drv_data->spi_ver_def = &spi_ver_0_0;
+	} else if (spi_ver == 23) {
+		master_drv_data->spi_ver_def = &spi_ver_2_3;
+	}
+
+	dev_dbg(&pdev->dev, "SPI_REV 0.%d\n", spi_ver);
+
+	/* Set the master bitbang data */
+
+	master_drv_data->mxc_bitbang.chipselect = mxc_spi_chipselect;
+	master_drv_data->mxc_bitbang.txrx_bufs = mxc_spi_transfer;
+	master_drv_data->mxc_bitbang.master->setup = mxc_spi_setup;
+	master_drv_data->mxc_bitbang.master->cleanup = mxc_spi_cleanup;
+	master_drv_data->mxc_bitbang.setup_transfer = mxc_spi_setup_transfer;
+
+	/* Initialize the completion object */
+
+	init_completion(&master_drv_data->xfer_done);
+
+	/* Set the master controller register addresses and irqs */
+
+	master_drv_data->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!master_drv_data->res) {
+		dev_err(&pdev->dev, "can't get platform resource for CSPI%d\n",
+			master->bus_num);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	if (!request_mem_region(master_drv_data->res->start,
+				master_drv_data->res->end -
+				master_drv_data->res->start + 1, pdev->name)) {
+		dev_err(&pdev->dev, "request_mem_region failed for CSPI%d\n",
+			master->bus_num);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	master_drv_data->base = ioremap(master_drv_data->res->start,
+		master_drv_data->res->end - master_drv_data->res->start + 1);
+	if (!master_drv_data->base) {
+		dev_err(&pdev->dev, "invalid base address for CSPI%d\n",
+			master->bus_num);
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	master_drv_data->irq = platform_get_irq(pdev, 0);
+	if (master_drv_data->irq < 0) {
+		dev_err(&pdev->dev, "can't get IRQ for CSPI%d\n",
+			master->bus_num);
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	/* Register for SPI Interrupt */
+
+	ret = request_irq(master_drv_data->irq, mxc_spi_isr,
+			  0, "CSPI_IRQ", master_drv_data);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "request_irq failed for CSPI%d\n",
+			master->bus_num);
+		goto err1;
+	}
+
+	/* Setup any GPIO active */
+
+	gpio_spi_active(master->bus_num - 1);
+
+	/* Enable the CSPI Clock, CSPI Module, set as a master */
+
+	master_drv_data->ctrl_addr =
+	    master_drv_data->base + master_drv_data->spi_ver_def->ctrl_reg_addr;
+	master_drv_data->stat_addr =
+	    master_drv_data->base + master_drv_data->spi_ver_def->stat_reg_addr;
+	master_drv_data->period_addr =
+	    master_drv_data->base +
+	    master_drv_data->spi_ver_def->period_reg_addr;
+	master_drv_data->test_addr =
+	    master_drv_data->base + master_drv_data->spi_ver_def->test_reg_addr;
+	master_drv_data->reset_addr =
+	    master_drv_data->base +
+	    master_drv_data->spi_ver_def->reset_reg_addr;
+
+	master_drv_data->clk = clk_get(&pdev->dev, "cspi_clk");
+	clk_enable(master_drv_data->clk);
+	master_drv_data->spi_ipg_clk = clk_get_rate(master_drv_data->clk);
+
+	__raw_writel(master_drv_data->spi_ver_def->reset_start,
+		     master_drv_data->reset_addr);
+	udelay(1);
+	__raw_writel((master_drv_data->spi_ver_def->spi_enable +
+		      master_drv_data->spi_ver_def->master_enable),
+		     master_drv_data->base + MXC_CSPICTRL);
+	__raw_writel(MXC_CSPIPERIOD_32KHZ, master_drv_data->period_addr);
+	__raw_writel(0, MXC_CSPIINT + master_drv_data->ctrl_addr);
+
+	/* Start the SPI Master Controller driver */
+
+	ret = spi_bitbang_start(&master_drv_data->mxc_bitbang);
+
+	if (ret != 0)
+		goto err2;
+
+	printk(KERN_INFO "CSPI: %s-%d probed\n", pdev->name, pdev->id);
+
+#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
+	{
+		int i;
+		struct spi_board_info *bi = &loopback_info[0];
+		for (i = 0; i < ARRAY_SIZE(loopback_info); i++, bi++) {
+			if (bi->bus_num != master->bus_num)
+				continue;
+
+			dev_info(&pdev->dev,
+				 "registering loopback device '%s'\n",
+				 bi->modalias);
+
+			spi_new_device(master, bi);
+		}
+	}
+#endif
+	clk_disable(master_drv_data->clk);
+	return ret;
+
+      err2:
+	gpio_spi_inactive(master->bus_num - 1);
+	clk_disable(master_drv_data->clk);
+	clk_put(master_drv_data->clk);
+	free_irq(master_drv_data->irq, master_drv_data);
+      err1:
+	iounmap(master_drv_data->base);
+	release_mem_region(pdev->resource[0].start,
+			   pdev->resource[0].end - pdev->resource[0].start + 1);
+      err:
+	spi_master_put(master);
+	kfree(master);
+	platform_set_drvdata(pdev, NULL);
+	return ret;
+}
+
+/*!
+ * Dissociates the driver from the SPI master controller. Disables the CSPI module.
+ * It handles the release of SPI resources like IRQ, memory,..etc.
+ *
+ * @param   pdev  the device structure used to give information on which SPI
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+
+	if (master) {
+		struct mxc_spi *master_drv_data =
+		    spi_master_get_devdata(master);
+
+		gpio_spi_inactive(master->bus_num - 1);
+
+		/* Disable the CSPI module */
+		clk_enable(master_drv_data->clk);
+		__raw_writel(MXC_CSPICTRL_DISABLE,
+			     master_drv_data->base + MXC_CSPICTRL);
+		clk_disable(master_drv_data->clk);
+		/* Unregister for SPI Interrupt */
+
+		free_irq(master_drv_data->irq, master_drv_data);
+
+		iounmap(master_drv_data->base);
+		release_mem_region(master_drv_data->res->start,
+				   master_drv_data->res->end -
+				   master_drv_data->res->start + 1);
+
+		/* Stop the SPI Master Controller driver */
+
+		spi_bitbang_stop(&master_drv_data->mxc_bitbang);
+
+		spi_master_put(master);
+	}
+
+	printk(KERN_INFO "CSPI: %s-%d removed\n", pdev->name, pdev->id);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int spi_bitbang_suspend(struct spi_bitbang *bitbang)
+{
+	unsigned long flags;
+	unsigned limit = 500;
+
+	spin_lock_irqsave(&bitbang->lock, flags);
+	while (!list_empty(&bitbang->queue) && limit--) {
+		spin_unlock_irqrestore(&bitbang->lock, flags);
+
+		dev_dbg(&bitbang->master->dev, "wait for queue\n");
+		msleep(10);
+
+		spin_lock_irqsave(&bitbang->lock, flags);
+	}
+	if (!list_empty(&bitbang->queue)) {
+		dev_err(&bitbang->master->dev, "queue didn't empty\n");
+		return -EBUSY;
+	}
+	spin_unlock_irqrestore(&bitbang->lock, flags);
+
+	return 0;
+}
+
+static void spi_bitbang_resume(struct spi_bitbang *bitbang)
+{
+	spin_lock_init(&bitbang->lock);
+	INIT_LIST_HEAD(&bitbang->queue);
+
+	bitbang->busy = 0;
+}
+
+/*!
+ * This function puts the SPI master controller in low-power mode/state.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_spi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct mxc_spi *master_drv_data = spi_master_get_devdata(master);
+	int ret = 0;
+
+	spi_bitbang_suspend(&master_drv_data->mxc_bitbang);
+	clk_enable(master_drv_data->clk);
+	__raw_writel(MXC_CSPICTRL_DISABLE,
+		     master_drv_data->base + MXC_CSPICTRL);
+	clk_disable(master_drv_data->clk);
+	gpio_spi_inactive(master->bus_num - 1);
+
+	return ret;
+}
+
+/*!
+ * This function brings the SPI master controller back from low-power state.
+ *
+ * @param   pdev  the device structure used to give information on which SDHC
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_spi_resume(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct mxc_spi *master_drv_data = spi_master_get_devdata(master);
+
+	gpio_spi_active(master->bus_num - 1);
+
+	spi_bitbang_resume(&master_drv_data->mxc_bitbang);
+	clk_enable(master_drv_data->clk);
+	__raw_writel(master_drv_data->spi_ver_def->spi_enable,
+		     master_drv_data->base + MXC_CSPICTRL);
+	clk_disable(master_drv_data->clk);
+	return 0;
+}
+#else
+#define mxc_spi_suspend  NULL
+#define mxc_spi_resume   NULL
+#endif				/* CONFIG_PM */
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_spi_driver = {
+	.driver = {
+		   .name = "mxc_spi",
+		   .bus = &platform_bus_type,
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxc_spi_probe,
+	.remove = mxc_spi_remove,
+	.suspend_late = mxc_spi_suspend,
+	.resume_early = mxc_spi_resume,
+};
+
+/*!
+ * This function implements the init function of the SPI device.
+ * It is called when the module is loaded. It enables the required
+ * clocks to CSPI module(if any) and activates necessary GPIO pins.
+ *
+ * @return       This function returns 0.
+ */
+static int __init mxc_spi_init(void)
+{
+	pr_debug("Registering the SPI Controller Driver\n");
+	return platform_driver_register(&mxc_spi_driver);
+}
+
+/*!
+ * This function implements the exit function of the SPI device.
+ * It is called when the module is unloaded. It deactivates the
+ * the GPIO pin associated with CSPI hardware modules.
+ *
+ */
+static void __exit mxc_spi_exit(void)
+{
+	pr_debug("Unregistering the SPI Controller Driver\n");
+	platform_driver_unregister(&mxc_spi_driver);
+}
+
+subsys_initcall(mxc_spi_init);
+module_exit(mxc_spi_exit);
+
+MODULE_DESCRIPTION("SPI Master Controller driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_mxs.c b/drivers/spi/spi_mxs.c
new file mode 100644
index 000000000000..744be68d9433
--- /dev/null
+++ b/drivers/spi/spi_mxs.c
@@ -0,0 +1,711 @@
+/*
+ * Freescale MXS SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <asm/dma.h>
+
+#include <mach/regs-ssp.h>
+#include <mach/dmaengine.h>
+#include <mach/device.h>
+#include <mach/system.h>
+#include <mach/hardware.h>
+
+#include "spi_mxs.h"
+
+/* 0 means DMA modei(recommended, default), !0 - PIO mode */
+static int pio /* = 0 */ ;
+static int debug;
+
+/**
+ * mxs_spi_init_hw
+ *
+ * Initialize the SSP port
+ */
+static int mxs_spi_init_hw(struct mxs_spi *ss)
+{
+	int err;
+
+	ss->clk = clk_get(NULL, "ssp.0");
+	if (IS_ERR(ss->clk)) {
+		err = PTR_ERR(ss->clk);
+		goto out;
+	}
+	clk_enable(ss->clk);
+
+	mxs_reset_block((void *)ss->regs, 0);
+	mxs_dma_reset(ss->dma);
+
+	return 0;
+
+out:
+	return err;
+}
+
+static void mxs_spi_release_hw(struct mxs_spi *ss)
+{
+	if (ss->clk && !IS_ERR(ss->clk)) {
+		clk_disable(ss->clk);
+		clk_put(ss->clk);
+	}
+}
+
+static int mxs_spi_setup_transfer(struct spi_device *spi,
+				  struct spi_transfer *t)
+{
+	u8 bits_per_word;
+	u32 hz;
+	struct mxs_spi *ss /* = spi_master_get_devdata(spi->master) */ ;
+	u16 rate;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	bits_per_word = spi->bits_per_word;
+	if (t && t->bits_per_word)
+		bits_per_word = t->bits_per_word;
+
+	/*
+	   Calculate speed:
+	   - by default, use maximum speed from ssp clk
+	   - if device overrides it, use it
+	   - if transfer specifies other speed, use transfer's one
+	 */
+	hz = 1000 * ss->speed_khz / ss->divider;
+	if (spi->max_speed_hz)
+		hz = min(hz, spi->max_speed_hz);
+	if (t && t->speed_hz)
+		hz = min(hz, t->speed_hz);
+
+	if (hz == 0) {
+		dev_err(&spi->dev, "Cannot continue with zero clock\n");
+		return -EINVAL;
+	}
+
+	if (bits_per_word != 8) {
+		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+			__func__, bits_per_word);
+		return -EINVAL;
+	}
+
+	dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %ukHz/%d = %uHz\n",
+		hz, ss->speed_khz, ss->divider,
+		ss->speed_khz * 1000 / ss->divider);
+
+	if (ss->speed_khz * 1000 / ss->divider < hz) {
+		dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
+			__func__, hz);
+		return -EINVAL;
+	}
+
+	rate = 1000 * ss->speed_khz / ss->divider / hz;
+
+	__raw_writel(BF_SSP_TIMING_CLOCK_DIVIDE(ss->divider) |
+		     BF_SSP_TIMING_CLOCK_RATE(rate - 1),
+		     ss->regs + HW_SSP_TIMING);
+
+	__raw_writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
+		     BF_SSP_CTRL1_WORD_LENGTH
+		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
+		     ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+		     ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
+		     (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE),
+		     ss->regs + HW_SSP_CTRL1);
+
+	__raw_writel(0x00, ss->regs + HW_SSP_CMD0_SET);
+
+	return 0;
+}
+
+static void mxs_spi_cleanup(struct spi_device *spi)
+{
+	struct mxs_spi_platform_data *pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_pin_release)
+		pdata->hw_pin_release();
+}
+
+/* the spi->mode bits understood by this driver: */
+#define MODEBITS (SPI_CPOL | SPI_CPHA)
+static int mxs_spi_setup(struct spi_device *spi)
+{
+	struct mxs_spi_platform_data *pdata;
+	struct mxs_spi *ss;
+	int err = 0;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	if (!spi->bits_per_word)
+		spi->bits_per_word = 8;
+
+	if (spi->mode & ~MODEBITS) {
+		dev_err(&spi->dev, "%s: unsupported mode bits %x\n",
+			__func__, spi->mode & ~MODEBITS);
+		err = -EINVAL;
+		goto out;
+	}
+
+	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w\n",
+		__func__, spi->mode & MODEBITS, spi->bits_per_word);
+
+	pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_pin_init) {
+		err = pdata->hw_pin_init();
+		if (err)
+			goto out;
+	}
+
+	err = mxs_spi_setup_transfer(spi, NULL);
+	if (err)
+		goto out2;
+	return 0;
+
+out2:
+	if (pdata && pdata->hw_pin_release)
+		pdata->hw_pin_release();
+out:
+	dev_err(&spi->dev, "Failed to setup transfer, error = %d\n", err);
+	return err;
+}
+
+static inline u32 mxs_spi_cs(unsigned cs)
+{
+	return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
+	    ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
+}
+
+static int mxs_spi_txrx_dma(struct mxs_spi *ss, int cs,
+			    unsigned char *buf, dma_addr_t dma_buf, int len,
+			    int *first, int *last, int write)
+{
+	u32 c0 = 0;
+	dma_addr_t spi_buf_dma = dma_buf;
+	int count, status = 0;
+	enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+	c0 |= (*first ? BM_SSP_CTRL0_LOCK_CS : 0);
+	c0 |= (*last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
+	c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
+	c0 |= BM_SSP_CTRL0_DATA_XFER;
+
+	c0 |= mxs_spi_cs(cs);
+
+	c0 |= BF_SSP_CTRL0_XFER_COUNT(len);
+
+	if (!dma_buf)
+		spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir);
+
+	ss->pdesc->cmd.cmd.bits.bytes = len;
+	ss->pdesc->cmd.cmd.bits.pio_words = 1;
+	ss->pdesc->cmd.cmd.bits.wait4end = 1;
+	ss->pdesc->cmd.cmd.bits.dec_sem = 1;
+	ss->pdesc->cmd.cmd.bits.irq = 1;
+	ss->pdesc->cmd.cmd.bits.command = write ? DMA_READ : DMA_WRITE;
+	ss->pdesc->cmd.address = spi_buf_dma;
+	ss->pdesc->cmd.pio_words[0] = c0;
+	mxs_dma_desc_append(ss->dma, ss->pdesc);
+
+	mxs_dma_reset(ss->dma);
+	mxs_dma_ack_irq(ss->dma);
+	mxs_dma_enable_irq(ss->dma, 1);
+	init_completion(&ss->done);
+	mxs_dma_enable(ss->dma);
+	wait_for_completion(&ss->done);
+	count = 10000;
+	while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)
+	       && count--)
+		continue;
+	if (count <= 0) {
+		printk(KERN_ERR "%c: timeout on line %s:%d\n",
+		       write ? 'W' : 'C', __func__, __LINE__);
+		status = -ETIMEDOUT;
+	}
+
+	if (!dma_buf)
+		dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir);
+
+	return status;
+}
+
+static inline void mxs_spi_enable(struct mxs_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_SET);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_CLR);
+}
+
+static inline void mxs_spi_disable(struct mxs_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_SET);
+}
+
+static int mxs_spi_txrx_pio(struct mxs_spi *ss, int cs,
+			    unsigned char *buf, int len,
+			    int *first, int *last, int write)
+{
+	int count;
+
+	if (*first) {
+		mxs_spi_enable(ss);
+		*first = 0;
+	}
+
+	__raw_writel(mxs_spi_cs(cs), ss->regs + HW_SSP_CTRL0_SET);
+
+	while (len--) {
+		if (*last && len == 0) {
+			mxs_spi_disable(ss);
+			*last = 0;
+		}
+		__raw_writel(BM_SSP_CTRL0_XFER_COUNT,
+			     ss->regs + HW_SSP_CTRL0_CLR);
+		__raw_writel(1, ss->regs + HW_SSP_CTRL0_SET);	/* byte-by-byte */
+
+		if (write)
+			__raw_writel(BM_SSP_CTRL0_READ,
+				     ss->regs + HW_SSP_CTRL0_CLR);
+		else
+			__raw_writel(BM_SSP_CTRL0_READ,
+				     ss->regs + HW_SSP_CTRL0_SET);
+
+		/* Run! */
+		__raw_writel(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0_SET);
+		count = 10000;
+		while (((__raw_readl(ss->regs + HW_SSP_CTRL0) &
+			 BM_SSP_CTRL0_RUN) == 0) && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR "%c: timeout on line %s:%d\n",
+			       write ? 'W' : 'C', __func__, __LINE__);
+			break;
+		}
+
+		if (write)
+			__raw_writel(*buf, ss->regs + HW_SSP_DATA);
+
+		/* Set TRANSFER */
+		__raw_writel(BM_SSP_CTRL0_DATA_XFER,
+			     ss->regs + HW_SSP_CTRL0_SET);
+
+		if (!write) {
+			count = 10000;
+			while (count-- &&
+			       (__raw_readl(ss->regs + HW_SSP_STATUS) &
+				BM_SSP_STATUS_FIFO_EMPTY))
+				continue;
+			if (count <= 0) {
+				printk(KERN_ERR "%c: timeout on line %s:%d\n",
+				       write ? 'W' : 'C', __func__, __LINE__);
+				break;
+			}
+			*buf = (__raw_readl(ss->regs + HW_SSP_DATA) & 0xFF);
+		}
+
+		count = 10000;
+		while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)
+		       && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR "%c: timeout on line %s:%d\n",
+			       write ? 'W' : 'C', __func__, __LINE__);
+			break;
+		}
+
+		/* advance to the next byte */
+		buf++;
+	}
+	return len < 0 ? 0 : -ETIMEDOUT;
+}
+
+static int mxs_spi_handle_message(struct mxs_spi *ss, struct spi_message *m)
+{
+	int first, last;
+	struct spi_transfer *t, *tmp_t;
+	int status = 0;
+	int cs;
+
+	first = last = 0;
+
+	cs = m->spi->chip_select;
+
+	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
+
+		mxs_spi_setup_transfer(m->spi, t);
+
+		if (&t->transfer_list == m->transfers.next)
+			first = !0;
+		if (&t->transfer_list == m->transfers.prev)
+			last = !0;
+		if (t->rx_buf && t->tx_buf) {
+			pr_debug("%s: cannot send and receive simultaneously\n",
+				 __func__);
+			return -EINVAL;
+		}
+
+		/*
+		   REVISIT:
+		   here driver completely ignores setting of t->cs_change
+		 */
+		if (t->tx_buf) {
+			status = pio ?
+			    mxs_spi_txrx_pio(ss, cs, (void *)t->tx_buf,
+					     t->len, &first, &last, 1) :
+			    mxs_spi_txrx_dma(ss, cs, (void *)t->tx_buf,
+					     t->tx_dma, t->len, &first, &last,
+					     1);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Tx ",
+							     DUMP_PREFIX_OFFSET,
+							     t->tx_buf, t->len);
+				else
+					pr_debug("Tx: %d bytes\n", t->len);
+			}
+		}
+		if (t->rx_buf) {
+			status = pio ?
+			    mxs_spi_txrx_pio(ss, cs, t->rx_buf,
+					     t->len, &first, &last, 0) :
+			    mxs_spi_txrx_dma(ss, cs, t->rx_buf,
+					     t->rx_dma, t->len, &first, &last,
+					     0);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Rx ",
+							     DUMP_PREFIX_OFFSET,
+							     t->rx_buf, t->len);
+				else
+					pr_debug("Rx: %d bytes\n", t->len);
+			}
+		}
+
+		if (status)
+			break;
+
+		first = last = 0;
+
+	}
+	return status;
+}
+
+/**
+ * mxs_spi_handle
+ *
+ * The workhorse of the driver - it handles messages from the list
+ *
+ **/
+static void mxs_spi_handle(struct work_struct *w)
+{
+	struct mxs_spi *ss = container_of(w, struct mxs_spi, work);
+	unsigned long flags;
+	struct spi_message *m;
+
+	BUG_ON(w == NULL);
+
+	spin_lock_irqsave(&ss->lock, flags);
+	while (!list_empty(&ss->queue)) {
+		m = list_entry(ss->queue.next, struct spi_message, queue);
+		list_del_init(&m->queue);
+		spin_unlock_irqrestore(&ss->lock, flags);
+
+		m->status = mxs_spi_handle_message(ss, m);
+		if (m->complete)
+			m->complete(m->context);
+
+		spin_lock_irqsave(&ss->lock, flags);
+	}
+	spin_unlock_irqrestore(&ss->lock, flags);
+
+	return;
+}
+
+/**
+ * mxs_spi_transfer
+ *
+ * Called indirectly from spi_async, queues all the messages to
+ * spi_handle_message
+ *
+ * @spi: spi device
+ * @m: message to be queued
+**/
+static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+	struct mxs_spi *ss = spi_master_get_devdata(spi->master);
+	unsigned long flags;
+
+	m->status = -EINPROGRESS;
+	spin_lock_irqsave(&ss->lock, flags);
+	list_add_tail(&m->queue, &ss->queue);
+	queue_work(ss->workqueue, &ss->work);
+	spin_unlock_irqrestore(&ss->lock, flags);
+	return 0;
+}
+
+static irqreturn_t mxs_spi_irq_dma(int irq, void *dev_id)
+{
+	struct mxs_spi *ss = dev_id;
+
+	mxs_dma_ack_irq(ss->dma);
+	mxs_dma_cooked(ss->dma, NULL);
+	complete(&ss->done);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxs_spi_irq_err(int irq, void *dev_id)
+{
+	struct mxs_spi *ss = dev_id;
+	u32 c1, st;
+
+	c1 = __raw_readl(ss->regs + HW_SSP_CTRL1);
+	st = __raw_readl(ss->regs + HW_SSP_STATUS);
+	printk(KERN_ERR "IRQ - ERROR!, status = 0x%08X, c1 = 0x%08X\n", st, c1);
+	__raw_writel(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1_CLR);
+
+	return IRQ_HANDLED;
+}
+
+static int __init mxs_spi_probe(struct platform_device *dev)
+{
+	int err = 0;
+	struct spi_master *master;
+	struct mxs_spi *ss;
+	struct resource *r;
+	u32 mem;
+
+	/* Get resources(memory, IRQ) associated with the device */
+	master = spi_alloc_master(&dev->dev, sizeof(struct mxs_spi));
+
+	if (master == NULL) {
+		err = -ENOMEM;
+		goto out0;
+	}
+
+	platform_set_drvdata(dev, master);
+
+	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss = spi_master_get_devdata(master);
+	ss->master_dev = &dev->dev;
+
+	INIT_WORK(&ss->work, mxs_spi_handle);
+	INIT_LIST_HEAD(&ss->queue);
+	spin_lock_init(&ss->lock);
+	ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev));
+	master->transfer = mxs_spi_transfer;
+	master->setup = mxs_spi_setup;
+	master->cleanup = mxs_spi_cleanup;
+
+	if (!request_mem_region(r->start,
+				resource_size(r), dev_name(&dev->dev))) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+	mem = r->start;
+
+	ss->regs = IO_ADDRESS(r->start);
+
+	ss->irq_dma = platform_get_irq(dev, 0);
+	if (ss->irq_dma < 0) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+	ss->irq_err = platform_get_irq(dev, 1);
+	if (ss->irq_err < 0) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+
+	r = platform_get_resource(dev, IORESOURCE_DMA, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss->dma = r->start;
+	err = mxs_dma_request(ss->dma, &dev->dev, (char *)dev_name(&dev->dev));
+	if (err)
+		goto out_put_master;
+
+	ss->pdesc = mxs_dma_alloc_desc();
+	if (ss->pdesc == NULL || IS_ERR(ss->pdesc)) {
+		err = -ENOMEM;
+		goto out_free_dma;
+	}
+
+	master->bus_num = dev->id + 1;
+	master->num_chipselect = 1;
+
+	/* SPI controller initializations */
+	err = mxs_spi_init_hw(ss);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot initialize hardware\n");
+		goto out_free_dma_desc;
+	}
+
+	clk_set_rate(ss->clk, 120 * 1000 * 1000);
+	ss->speed_khz = clk_get_rate(ss->clk) / 1000;
+	ss->divider = 2;
+	dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n",
+		 ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
+
+	/* Register for SPI Interrupt */
+	err = request_irq(ss->irq_dma, mxs_spi_irq_dma, 0,
+			  dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq failed, %d\n", err);
+		goto out_release_hw;
+	}
+	err = request_irq(ss->irq_err, mxs_spi_irq_err, IRQF_SHARED,
+			  dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err);
+		goto out_free_irq;
+	}
+
+	err = spi_register_master(master);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot register spi master, %d\n", err);
+		goto out_free_irq_2;
+	}
+	dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d, bus %d, %s\n",
+		 mem, (u32) ss->regs, ss->irq_dma,
+		 master->bus_num, pio ? "PIO" : "DMA");
+	return 0;
+
+out_free_irq_2:
+	free_irq(ss->irq_err, ss);
+out_free_irq:
+	free_irq(ss->irq_dma, ss);
+out_free_dma_desc:
+	mxs_dma_free_desc(ss->pdesc);
+out_free_dma:
+	mxs_dma_release(ss->dma, &dev->dev);
+out_release_hw:
+	mxs_spi_release_hw(ss);
+out_put_master:
+	spi_master_put(master);
+out0:
+	return err;
+}
+
+static int __devexit mxs_spi_remove(struct platform_device *dev)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(dev);
+	if (master == NULL)
+		goto out0;
+	ss = spi_master_get_devdata(master);
+	if (ss == NULL)
+		goto out1;
+	free_irq(ss->irq_err, ss);
+	free_irq(ss->irq_dma, ss);
+	if (ss->workqueue)
+		destroy_workqueue(ss->workqueue);
+	mxs_dma_free_desc(ss->pdesc);
+	mxs_dma_release(ss->dma, &dev->dev);
+	mxs_spi_release_hw(ss);
+	platform_set_drvdata(dev, 0);
+out1:
+	spi_master_put(master);
+out0:
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_spi_suspend(struct platform_device *pdev, pm_message_t pmsg)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	ss->saved_timings = __raw_readl(ss->regs + HW_SSP_TIMING);
+	clk_disable(ss->clk);
+
+	return 0;
+}
+
+static int mxs_spi_resume(struct platform_device *pdev)
+{
+	struct mxs_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	clk_enable(ss->clk);
+	__raw_writel(BM_SSP_CTRL0_SFTRST | BM_SSP_CTRL0_CLKGATE,
+		     ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(ss->saved_timings, ss->regs + HW_SSP_TIMING);
+
+	return 0;
+}
+
+#else
+#define mxs_spi_suspend NULL
+#define mxs_spi_resume  NULL
+#endif
+
+static struct platform_driver mxs_spi_driver = {
+	.probe = mxs_spi_probe,
+	.remove = __devexit_p(mxs_spi_remove),
+	.driver = {
+		   .name = "mxs-spi",
+		   .owner = THIS_MODULE,
+		   },
+	.suspend = mxs_spi_suspend,
+	.resume = mxs_spi_resume,
+};
+
+static int __init mxs_spi_init(void)
+{
+	return platform_driver_register(&mxs_spi_driver);
+}
+
+static void __exit mxs_spi_exit(void)
+{
+	platform_driver_unregister(&mxs_spi_driver);
+}
+
+module_init(mxs_spi_init);
+module_exit(mxs_spi_exit);
+module_param(pio, int, S_IRUGO);
+module_param(debug, int, S_IRUGO);
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_DESCRIPTION("MXS SPI/SSP");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_mxs.h b/drivers/spi/spi_mxs.h
new file mode 100644
index 000000000000..ba605bf3b56e
--- /dev/null
+++ b/drivers/spi/spi_mxs.h
@@ -0,0 +1,52 @@
+/*
+ * Freescale MXS SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __SPI_STMP_H
+#define __SPI_STMP_H
+
+#include <mach/dma.h>
+
+struct mxs_spi {
+	void __iomem *regs;	/* vaddr of the control registers */
+
+	u32 irq_dma;
+	u32 irq_err;
+	u32 dma;
+	struct mxs_dma_desc *pdesc;
+
+	u32 speed_khz;
+	u32 saved_timings;
+	u32 divider;
+
+	struct clk *clk;
+	struct device *master_dev;
+
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	spinlock_t lock;
+	struct list_head queue;
+
+	struct completion done;
+};
+
+#endif /* __SPI_STMP_H */
diff --git a/drivers/spi/spi_stmp.c b/drivers/spi/spi_stmp.c
new file mode 100644
index 000000000000..5862ea8269d0
--- /dev/null
+++ b/drivers/spi/spi_stmp.c
@@ -0,0 +1,696 @@
+/*
+ * Freescale STMP378X SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <asm/dma.h>
+
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+#include <mach/regs-ssp.h>
+#include <mach/regs-apbh.h>
+#include "spi_stmp.h"
+
+/* 0 means DMA modei(recommended, default), !0 - PIO mode */
+static int pio /* = 0 */;
+static int debug;
+
+/**
+ * stmp_spi_init_hw
+ *
+ * Initialize the SSP port
+ */
+static int stmp_spi_init_hw(struct stmp_spi *ss)
+{
+	int err;
+
+	err = stmp37xx_spi_pins_request((char *)dev_name(ss->master_dev), ss->id);
+	if (err)
+		goto out;
+
+	ss->clk = clk_get(NULL, "ssp");
+	if (IS_ERR(ss->clk)) {
+		err = PTR_ERR(ss->clk);
+		goto out_free_pins;
+	}
+	clk_enable(ss->clk);
+
+	stmp3xxx_reset_block((void *)ss->regs, 0);
+	stmp3xxx_dma_reset_channel(ss->dma);
+
+	return 0;
+
+out_free_pins:
+	stmp37xx_spi_pins_release((char *)dev_name(ss->master_dev), ss->id);
+out:
+	return err;
+}
+
+static void stmp_spi_release_hw(struct stmp_spi *ss)
+{
+	if (ss->clk && !IS_ERR(ss->clk)) {
+		clk_disable(ss->clk);
+		clk_put(ss->clk);
+	}
+	stmp37xx_spi_pins_release((char *)dev_name(ss->master_dev), ss->id);
+}
+
+static int stmp_spi_setup_transfer(struct spi_device *spi,
+		struct spi_transfer *t)
+{
+	u8 bits_per_word;
+	u32 hz;
+	struct stmp_spi *ss /* = spi_master_get_devdata(spi->master) */;
+	u16 rate;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	bits_per_word = spi->bits_per_word;
+	if (t && t->bits_per_word)
+		bits_per_word = t->bits_per_word;
+
+	/*
+	  Calculate speed:
+		- by default, use maximum speed from ssp clk
+		- if device overrides it, use it
+		- if transfer specifies other speed, use transfer's one
+	 */
+	hz = 1000 * ss->speed_khz / ss->divider;
+	if (spi->max_speed_hz)
+		hz = min(hz, spi->max_speed_hz);
+	if (t && t->speed_hz)
+		hz = min(hz, t->speed_hz);
+
+	if (hz == 0) {
+		dev_err(&spi->dev, "Cannot continue with zero clock\n");
+		return -EINVAL;
+	}
+
+	if (bits_per_word != 8) {
+		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+			__func__, bits_per_word);
+		return -EINVAL;
+	}
+
+	dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %uHz/%d = %uHz\n",
+		hz, ss->speed_khz, ss->divider,
+		ss->speed_khz * 1000 / ss->divider);
+
+	if (ss->speed_khz * 1000 / ss->divider < hz) {
+		dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
+			__func__, hz);
+		return -EINVAL;
+	}
+
+	rate = 1000 * ss->speed_khz/ss->divider/hz;
+
+	__raw_writel(BF(ss->divider, SSP_TIMING_CLOCK_DIVIDE) |
+		BF(rate - 1, SSP_TIMING_CLOCK_RATE), ss->regs + HW_SSP_TIMING);
+
+	__raw_writel(BF(BV_SSP_CTRL1_SSP_MODE__SPI, SSP_CTRL1_SSP_MODE) |
+		BF(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS, SSP_CTRL1_WORD_LENGTH) |
+		((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+		((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
+		(pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE), ss->regs + HW_SSP_CTRL1);
+
+	__raw_writel(0x00, ss->regs + HW_SSP_CMD0_SET);
+
+	return 0;
+}
+
+
+static void stmp_spi_cleanup(struct spi_device *spi)
+{
+	struct stmp37xx_spi_platform_data *pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_release)
+		pdata->hw_release(spi);
+}
+
+/* the spi->mode bits understood by this driver: */
+#define MODEBITS (SPI_CPOL | SPI_CPHA)
+static int stmp_spi_setup(struct spi_device *spi)
+{
+	struct stmp37xx_spi_platform_data *pdata;
+	struct stmp_spi *ss;
+	int err = 0;
+
+	ss = spi_master_get_devdata(spi->master);
+
+	if (!spi->bits_per_word)
+		spi->bits_per_word = 8;
+
+	if (spi->mode & ~MODEBITS) {
+		dev_err(&spi->dev, "%s: unsupported mode bits %x\n",
+			__func__, spi->mode & ~MODEBITS);
+		err = -EINVAL;
+		goto out;
+	}
+
+	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w\n",
+		__func__, spi->mode & MODEBITS, spi->bits_per_word);
+
+	pdata = spi->dev.platform_data;
+
+	if (pdata && pdata->hw_init) {
+		err = pdata->hw_init(spi);
+		if (err)
+			goto out;
+	}
+
+	err = stmp_spi_setup_transfer(spi, NULL);
+	if (err)
+		goto out2;
+	return 0;
+
+out2:
+	if (pdata)
+		pdata->hw_release(spi);
+out:
+	dev_err(&spi->dev, "Failed to setup transfer, error = %d\n", err);
+	return err;
+}
+
+static inline u32 stmp_spi_cs(unsigned cs)
+{
+	return  ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
+		((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
+}
+
+static int stmp_spi_txrx_dma(struct stmp_spi *ss, int cs,
+		unsigned char *buf, dma_addr_t dma_buf, int len,
+		int *first, int *last, int write)
+{
+	u32 c0 = 0;
+	dma_addr_t spi_buf_dma = dma_buf;
+	int count, status = 0;
+	enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+	c0 |= (*first ? BM_SSP_CTRL0_LOCK_CS : 0);
+	c0 |= (*last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
+	c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
+	c0 |= BM_SSP_CTRL0_DATA_XFER;
+
+	c0 |= stmp_spi_cs(cs);
+
+	c0 |= BF(len, SSP_CTRL0_XFER_COUNT);
+
+	if (!dma_buf)
+		spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir);
+
+	ss->d.command->cmd =
+		BF(len, APBH_CHn_CMD_XFER_COUNT) |
+		BF(1, APBH_CHn_CMD_CMDWORDS) |
+		BM_APBH_CHn_CMD_WAIT4ENDCMD |
+		BM_APBH_CHn_CMD_IRQONCMPLT  |
+		BF(write ? BV_APBH_CHn_CMD_COMMAND__DMA_READ :
+			BV_APBH_CHn_CMD_COMMAND__DMA_WRITE,
+			APBH_CHn_CMD_COMMAND);
+	ss->d.command->pio_words[0] = c0;
+	ss->d.command->buf_ptr = spi_buf_dma;
+
+	stmp3xxx_dma_reset_channel(ss->dma);
+	stmp3xxx_dma_clear_interrupt(ss->dma);
+	stmp3xxx_dma_enable_interrupt(ss->dma);
+	init_completion(&ss->done);
+	stmp3xxx_dma_go(ss->dma, &ss->d, 1);
+	wait_for_completion(&ss->done);
+	count = 10000;
+	while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) && count--)
+		continue;
+	if (count <= 0) {
+		printk(KERN_ERR"%c: timeout on line %s:%d\n",
+				write ? 'W':'C', __func__, __LINE__);
+		status = -ETIMEDOUT;
+	}
+
+	if (!dma_buf)
+		dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir);
+
+	return status;
+}
+
+static inline void stmp_spi_enable(struct stmp_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_SET);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_CLR);
+}
+
+static inline void stmp_spi_disable(struct stmp_spi *ss)
+{
+	__raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_SET);
+}
+
+static int stmp_spi_txrx_pio(struct stmp_spi *ss, int cs,
+		unsigned char *buf, int len,
+		int *first, int *last, int write)
+{
+	int count;
+
+	if (*first) {
+		stmp_spi_enable(ss);
+		*first = 0;
+	}
+
+	__raw_writel(stmp_spi_cs(cs), ss->regs + HW_SSP_CTRL0_SET);
+
+	while (len--) {
+		if (*last && len == 0) {
+			stmp_spi_disable(ss);
+			*last = 0;
+		}
+		__raw_writel(BM_SSP_CTRL0_XFER_COUNT,
+				ss->regs + HW_SSP_CTRL0_CLR);
+		__raw_writel(1, ss->regs + HW_SSP_CTRL0_SET); /* byte-by-byte */
+
+		if (write)
+			__raw_writel(BM_SSP_CTRL0_READ,
+				ss->regs + HW_SSP_CTRL0_CLR);
+		else
+			__raw_writel(BM_SSP_CTRL0_READ,
+				ss->regs + HW_SSP_CTRL0_SET);
+
+		/* Run! */
+		__raw_writel(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0_SET);
+		count = 10000;
+		while (((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) == 0) && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR"%c: timeout on line %s:%d\n",
+					write ? 'W':'C', __func__, __LINE__);
+			break;
+		}
+
+		if (write)
+			__raw_writel(*buf, ss->regs + HW_SSP_DATA);
+
+		/* Set TRANSFER */
+		__raw_writel(BM_SSP_CTRL0_DATA_XFER,
+			ss->regs + HW_SSP_CTRL0_SET);
+
+		if (!write) {
+			count = 10000;
+			while (count-- &&
+				(__raw_readl(ss->regs + HW_SSP_STATUS) &
+					BM_SSP_STATUS_FIFO_EMPTY))
+				continue;
+			if (count <= 0) {
+				printk(KERN_ERR"%c: timeout on line %s:%d\n",
+					write ? 'W':'C', __func__, __LINE__);
+				break;
+			}
+			*buf = (__raw_readl(ss->regs + HW_SSP_DATA) & 0xFF);
+		}
+
+		count = 10000;
+		while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) && count--)
+			continue;
+		if (count <= 0) {
+			printk(KERN_ERR"%c: timeout on line %s:%d\n",
+				write ? 'W':'C', __func__, __LINE__);
+			break;
+		}
+
+		/* advance to the next byte */
+		buf++;
+	}
+	return len < 0 ? 0 : -ETIMEDOUT;
+}
+
+static int stmp_spi_handle_message(struct stmp_spi *ss, struct spi_message *m)
+{
+	int first, last;
+	struct spi_transfer *t, *tmp_t;
+	int status = 0;
+	int cs;
+
+	first = last = 0;
+
+	cs = m->spi->chip_select;
+
+	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
+
+		stmp_spi_setup_transfer(m->spi, t);
+
+		if (&t->transfer_list == m->transfers.next)
+			first = !0;
+		if (&t->transfer_list == m->transfers.prev)
+			last = !0;
+		if (t->rx_buf && t->tx_buf) {
+			pr_debug("%s: cannot send and receive simultaneously\n",
+				__func__);
+			return -EINVAL;
+		}
+
+		/*
+		  REVISIT:
+		  here driver completely ignores setting of t->cs_change
+		 */
+		if (t->tx_buf) {
+			status = pio ?
+			   stmp_spi_txrx_pio(ss, cs, (void *)t->tx_buf,
+				   t->len, &first, &last, 1) :
+			   stmp_spi_txrx_dma(ss, cs, (void *)t->tx_buf,
+				   t->tx_dma, t->len, &first, &last, 1);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Tx ",
+						DUMP_PREFIX_OFFSET,
+						t->tx_buf, t->len);
+				else
+					pr_debug("Tx: %d bytes\n", t->len);
+			}
+		}
+		if (t->rx_buf) {
+			status = pio ?
+			   stmp_spi_txrx_pio(ss, cs, t->rx_buf,
+				   t->len, &first, &last, 0):
+			   stmp_spi_txrx_dma(ss, cs, t->rx_buf,
+				   t->rx_dma, t->len, &first, &last, 0);
+			if (debug) {
+				if (t->len < 0x10)
+					print_hex_dump_bytes("Rx ",
+						DUMP_PREFIX_OFFSET,
+						t->rx_buf, t->len);
+				else
+					pr_debug("Rx: %d bytes\n", t->len);
+			}
+		}
+
+		if (status)
+			break;
+
+		first = last = 0;
+
+	}
+	return status;
+}
+
+/**
+ * stmp_spi_handle
+ *
+ * The workhorse of the driver - it handles messages from the list
+ *
+ **/
+static void stmp_spi_handle(struct work_struct *w)
+{
+	struct stmp_spi *ss = container_of(w, struct stmp_spi, work);
+	unsigned long flags;
+	struct spi_message *m;
+
+	BUG_ON(w == NULL);
+
+	spin_lock_irqsave(&ss->lock, flags);
+	while (!list_empty(&ss->queue)) {
+		m = list_entry(ss->queue.next, struct spi_message, queue);
+		list_del_init(&m->queue);
+		spin_unlock_irqrestore(&ss->lock, flags);
+
+		m->status = stmp_spi_handle_message(ss, m);
+		if (m->complete)
+			m->complete(m->context);
+
+		spin_lock_irqsave(&ss->lock, flags);
+	}
+	spin_unlock_irqrestore(&ss->lock, flags);
+
+	return;
+}
+
+/**
+ * stmp_spi_transfer
+ *
+ * Called indirectly from spi_async, queues all the messages to
+ * spi_handle_message
+ *
+ * @spi: spi device
+ * @m: message to be queued
+**/
+static int stmp_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+	struct stmp_spi *ss = spi_master_get_devdata(spi->master);
+	unsigned long flags;
+
+	m->status = -EINPROGRESS;
+	spin_lock_irqsave(&ss->lock, flags);
+	list_add_tail(&m->queue, &ss->queue);
+	queue_work(ss->workqueue, &ss->work);
+	spin_unlock_irqrestore(&ss->lock, flags);
+	return 0;
+}
+
+static irqreturn_t stmp_spi_irq(int irq, void *dev_id)
+{
+	struct stmp_spi *ss = dev_id;
+
+	stmp3xxx_dma_clear_interrupt(ss->dma);
+	complete(&ss->done);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stmp_spi_irq_err(int irq, void *dev_id)
+{
+	struct stmp_spi *ss = dev_id;
+	u32 c1, st;
+
+	c1 = __raw_readl(ss->regs + HW_SSP_CTRL1);
+	st = __raw_readl(ss->regs + HW_SSP_STATUS);
+	printk(KERN_ERR"IRQ - ERROR!, status = 0x%08X, c1 = 0x%08X\n", st, c1);
+	__raw_writel(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1_CLR);
+
+	return IRQ_HANDLED;
+}
+
+static int __init stmp_spi_probe(struct platform_device *dev)
+{
+	int err = 0;
+	struct spi_master *master;
+	struct stmp_spi *ss;
+	struct resource *r;
+	u32 mem;
+
+	/* Get resources(memory, IRQ) associated with the device */
+	master = spi_alloc_master(&dev->dev, sizeof(struct stmp_spi));
+
+	if (master == NULL) {
+		err = -ENOMEM;
+		goto out0;
+	}
+
+	platform_set_drvdata(dev, master);
+
+	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss = spi_master_get_devdata(master);
+	ss->master_dev = &dev->dev;
+	ss->id = dev->id;
+
+	INIT_WORK(&ss->work, stmp_spi_handle);
+	INIT_LIST_HEAD(&ss->queue);
+	spin_lock_init(&ss->lock);
+	ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev));
+	master->transfer = stmp_spi_transfer;
+	master->setup = stmp_spi_setup;
+	master->cleanup = stmp_spi_cleanup;
+
+	if (!request_mem_region(r->start,
+			r->end - r->start + 1, dev_name(&dev->dev))) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+	mem = r->start;
+
+	ss->regs = r->start - STMP3XXX_REGS_PHBASE + STMP3XXX_REGS_BASE;
+
+	ss->irq = platform_get_irq(dev, 0);
+	if (ss->irq < 0) {
+		err = -ENXIO;
+		goto out_put_master;
+	}
+
+	r = platform_get_resource(dev, IORESOURCE_DMA, 0);
+	if (r == NULL) {
+		err = -ENODEV;
+		goto out_put_master;
+	}
+
+	ss->dma = r->start;
+	err = stmp3xxx_dma_request(ss->dma, &dev->dev, (char *)dev_name(&dev->dev));
+	if (err)
+		goto out_put_master;
+
+	err = stmp3xxx_dma_allocate_command(ss->dma, &ss->d);
+	if (err)
+		goto out_free_dma;
+
+	master->bus_num = dev->id;
+	master->num_chipselect = 1;
+
+	/* SPI controller initializations */
+	err = stmp_spi_init_hw(ss);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot initialize hardware\n");
+		goto out_free_dma_desc;
+	}
+
+	clk_set_rate(ss->clk, 120000);
+	ss->speed_khz = clk_get_rate(ss->clk);
+	ss->divider = 2;
+	dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n",
+		ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
+
+	/* Register for SPI Interrupt */
+	err = request_irq(ss->irq, stmp_spi_irq, 0,
+			dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq failed, %d\n", err);
+		goto out_release_hw;
+	}
+	err = request_irq(IRQ_SSP_ERROR, stmp_spi_irq_err, IRQF_SHARED,
+			dev_name(&dev->dev), ss);
+	if (err) {
+		dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err);
+		goto out_free_irq;
+	}
+
+	err = spi_register_master(master);
+	if (err) {
+		dev_dbg(&dev->dev, "cannot register spi master, %d\n", err);
+		goto out_free_irq_2;
+	}
+	dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d, bus %d, %s\n",
+			mem, (u32)ss->regs, ss->irq,
+			master->bus_num, pio ? "PIO" : "DMA");
+	return 0;
+
+out_free_irq_2:
+	free_irq(IRQ_SSP_ERROR, ss);
+out_free_irq:
+	free_irq(ss->irq, ss);
+out_free_dma_desc:
+	stmp3xxx_dma_free_command(ss->dma, &ss->d);
+out_free_dma:
+	stmp3xxx_dma_release(ss->dma);
+out_release_hw:
+	stmp_spi_release_hw(ss);
+out_put_master:
+	spi_master_put(master);
+out0:
+	return err;
+}
+
+static int __devexit stmp_spi_remove(struct platform_device *dev)
+{
+	struct stmp_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(dev);
+	if (master == NULL)
+		goto out0;
+	ss = spi_master_get_devdata(master);
+	if (ss == NULL)
+		goto out1;
+	free_irq(ss->irq, ss);
+	if (ss->workqueue)
+		destroy_workqueue(ss->workqueue);
+	stmp3xxx_dma_free_command(ss->dma, &ss->d);
+	stmp3xxx_dma_release(ss->dma);
+	stmp_spi_release_hw(ss);
+	platform_set_drvdata(dev, 0);
+out1:
+	spi_master_put(master);
+out0:
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stmp_spi_suspend(struct platform_device *pdev, pm_message_t pmsg)
+{
+	struct stmp_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	ss->saved_timings = __raw_readl(ss->regs + HW_SSP_TIMING);
+	clk_disable(ss->clk);
+
+	return 0;
+}
+
+static int stmp_spi_resume(struct platform_device *pdev)
+{
+	struct stmp_spi *ss;
+	struct spi_master *master;
+
+	master = platform_get_drvdata(pdev);
+	ss = spi_master_get_devdata(master);
+
+	clk_enable(ss->clk);
+	__raw_writel(BM_SSP_CTRL0_SFTRST | BM_SSP_CTRL0_CLKGATE,
+		ss->regs + HW_SSP_CTRL0_CLR);
+	__raw_writel(ss->saved_timings, ss->regs + HW_SSP_TIMING);
+
+	return 0;
+}
+
+#else
+#define stmp_spi_suspend NULL
+#define stmp_spi_resume  NULL
+#endif
+
+static struct platform_driver stmp_spi_driver = {
+	.probe	= stmp_spi_probe,
+	.remove	= __devexit_p(stmp_spi_remove),
+	.driver = {
+		.name = "stmp3xxx_ssp",
+		.owner = THIS_MODULE,
+	},
+	.suspend = stmp_spi_suspend,
+	.resume  = stmp_spi_resume,
+};
+
+static int __init stmp_spi_init(void)
+{
+	return platform_driver_register(&stmp_spi_driver);
+}
+
+static void __exit stmp_spi_exit(void)
+{
+	platform_driver_unregister(&stmp_spi_driver);
+}
+
+module_init(stmp_spi_init);
+module_exit(stmp_spi_exit);
+module_param(pio, int, S_IRUGO);
+module_param(debug, int, S_IRUGO);
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP37xx SPI/SSP");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_stmp.h b/drivers/spi/spi_stmp.h
new file mode 100644
index 000000000000..764edd6f9c9f
--- /dev/null
+++ b/drivers/spi/spi_stmp.h
@@ -0,0 +1,51 @@
+/*
+ * Freescale STMP378X SPI master driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __SPI_STMP_H
+#define __SPI_STMP_H
+
+#include <mach/dma.h>
+
+/* These two come from arch/arm/mach-xxxxx/spi.c */
+int stmp37xx_spi_pins_request(char *id, int ssp);
+void stmp37xx_spi_pins_release(char *id, int ssp);
+
+struct stmp_spi {
+	int		id;
+
+	void __iomem	*regs;	/* vaddr of the control registers */
+
+	u32		irq;
+	u32		dma;
+	struct stmp3xxx_dma_descriptor d;
+
+	u32		speed_khz;
+	u32		saved_timings;
+	u32		divider;
+
+	struct clk	*clk;
+	struct device	*master_dev;
+
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+	spinlock_t lock;
+	struct list_head queue;
+
+	struct completion done;
+};
+
+#endif /* __SPI_STMP_H */
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index f934393f3959..ae41f79d995d 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -18,6 +18,8 @@
 #include <linux/mm.h>
 #include <linux/oom.h>
 #include <linux/sched.h>
+#include <linux/nodemask.h>
+#include <linux/vmstat.h>
 
 static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask);
 
@@ -67,6 +69,15 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 	int array_size = ARRAY_SIZE(lowmem_adj);
 	int other_free = global_page_state(NR_FREE_PAGES);
 	int other_file = global_page_state(NR_FILE_PAGES);
+	int node;
+
+	for_each_node_state(node, N_HIGH_MEMORY) {
+		struct zone *z =
+			&NODE_DATA(node)->node_zones[ZONE_DMA];
+
+		other_free -= zone_page_state(z, NR_FREE_PAGES);
+		other_file -= zone_page_state(z, NR_FILE_PAGES);
+	}
 
 	if (lowmem_adj_size < array_size)
 		array_size = lowmem_adj_size;
@@ -105,7 +116,7 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 			task_unlock(p);
 			continue;
 		}
-		oom_adj = mm->oom_adj;
+		oom_adj = p->oomkilladj;
 		if (oom_adj < min_adj) {
 			task_unlock(p);
 			continue;
diff --git a/drivers/usb/core/generic.c b/drivers/usb/core/generic.c
index 30ecac3af15a..66e8a424c9f4 100644
--- a/drivers/usb/core/generic.c
+++ b/drivers/usb/core/generic.c
@@ -20,6 +20,8 @@
 #include <linux/usb.h>
 #include "usb.h"
 #include "hcd.h"
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
 
 static inline const char *plural(int n)
 {
@@ -190,20 +192,40 @@ static void generic_disconnect(struct usb_device *udev)
 
 #ifdef	CONFIG_PM
 
+extern void usb_host_set_wakeup(struct device *wkup_dev, bool para);
 static int generic_suspend(struct usb_device *udev, pm_message_t msg)
 {
 	int rc;
+	u32 temp;
 
 	/* Normal USB devices suspend through their upstream port.
 	 * Root hubs don't have upstream ports to suspend,
 	 * so we have to shut down their downstream HC-to-USB
 	 * interfaces manually by doing a bus (or "global") suspend.
 	 */
-	if (!udev->parent)
+	if (!udev->parent) {
+		struct usb_hcd  *hcd =
+			container_of(udev->bus, struct usb_hcd, self);
+		struct fsl_usb2_platform_data *pdata;
+		pdata = hcd->self.controller->platform_data;
+
 		rc = hcd_bus_suspend(udev, msg);
 
+		if (device_may_wakeup(hcd->self.controller)) {
+			clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+			/* enable remote wake up irq */
+			usb_host_set_wakeup(hcd->self.controller, true);
+
+			/* Put PHY into low power mode */
+			temp = readl(hcd->regs + 0x184);
+			writel(temp | (1 << 23), (hcd->regs + 0x184));
+
+			if (pdata->usb_clock_for_pm)
+				pdata->usb_clock_for_pm(false);
+		}
 	/* Non-root devices don't need to do anything for FREEZE or PRETHAW */
-	else if (msg.event == PM_EVENT_FREEZE || msg.event == PM_EVENT_PRETHAW)
+	} else if (msg.event == PM_EVENT_FREEZE ||
+			msg.event == PM_EVENT_PRETHAW)
 		rc = 0;
 	else
 		rc = usb_port_suspend(udev, msg);
@@ -214,15 +236,23 @@ static int generic_suspend(struct usb_device *udev, pm_message_t msg)
 static int generic_resume(struct usb_device *udev, pm_message_t msg)
 {
 	int rc;
+	u32 temp;
 
 	/* Normal USB devices resume/reset through their upstream port.
 	 * Root hubs don't have upstream ports to resume or reset,
 	 * so we have to start up their downstream HC-to-USB
 	 * interfaces manually by doing a bus (or "global") resume.
 	 */
-	if (!udev->parent)
+	if (!udev->parent) {
+		struct usb_hcd  *hcd =
+			container_of(udev->bus, struct usb_hcd, self);
+
+		if (device_may_wakeup(hcd->self.controller)) {
+			temp = readl(hcd->regs + 0x184);
+			writel(temp & (~(1 << 23)), (hcd->regs + 0x184));
+		}
 		rc = hcd_bus_resume(udev, msg);
-	else
+	} else
 		rc = usb_port_resume(udev, msg);
 	return rc;
 }
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 95ccfa0b9fc5..d27ad104731c 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -40,6 +40,7 @@
 #include <linux/workqueue.h>
 
 #include <linux/usb.h>
+#include <linux/fsl_devices.h>
 
 #include "usb.h"
 #include "hcd.h"
@@ -117,6 +118,8 @@ static inline int is_root_hub(struct usb_device *udev)
 	return (udev->parent == NULL);
 }
 
+extern int usb_host_wakeup_irq(struct device *wkup_dev);
+extern void usb_host_set_wakeup(struct device *wkup_dev, bool para);
 /*-------------------------------------------------------------------------*/
 
 /*
@@ -1873,6 +1876,7 @@ EXPORT_SYMBOL_GPL(usb_bus_start_enum);
 irqreturn_t usb_hcd_irq (int irq, void *__hcd)
 {
 	struct usb_hcd		*hcd = __hcd;
+	struct fsl_usb2_platform_data *pdata;
 	unsigned long		flags;
 	irqreturn_t		rc;
 
@@ -1882,8 +1886,23 @@ irqreturn_t usb_hcd_irq (int irq, void *__hcd)
 	 */
 	local_irq_save(flags);
 
-	if (unlikely(hcd->state == HC_STATE_HALT ||
-		     !test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))) {
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		/* Need open clock for register access */
+		pdata = hcd->self.controller->platform_data;
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(true);
+
+		/* if receive a remote wakeup interrrupt after suspend */
+		if (usb_host_wakeup_irq(hcd->self.controller)) {
+			/* disable remote wake up irq */
+			usb_host_set_wakeup(hcd->self.controller, false);
+
+			set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+			hcd->driver->irq(hcd);
+			rc = IRQ_HANDLED;
+		} else
+			rc = IRQ_NONE;
+	} else if (unlikely(hcd->state == HC_STATE_HALT)) {
 		rc = IRQ_NONE;
 	} else if (hcd->driver->irq(hcd) == IRQ_NONE) {
 		rc = IRQ_NONE;
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 71f86c60d83c..4abdddcff459 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -37,6 +37,24 @@
 #endif
 #endif
 
+#ifdef CONFIG_ARCH_STMP3XXX
+#define STMP3XXX_USB_HOST_HACK
+#endif
+
+#ifdef CONFIG_ARCH_MXS
+#define MXS_USB_HOST_HACK
+
+#include <linux/fsl_devices.h>
+extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata,
+					 bool enable);
+#endif
+
+#ifdef STMP3XXX_USB_HOST_HACK
+#include <linux/fsl_devices.h>
+#include <mach/regs-usbphy.h>
+#include <mach/platform.h>
+#endif
+
 struct usb_hub {
 	struct device		*intfdev;	/* the "interface" device */
 	struct usb_device	*hdev;
@@ -1160,6 +1178,11 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
 		return -E2BIG;
 	}
 
+	/* Defaultly disable autosuspend for hub and reley on sys
+	 * to enable it.
+	 */
+	hdev->autosuspend_disabled = 1;
+
 #ifdef	CONFIG_USB_OTG_BLACKLIST_HUB
 	if (hdev->parent) {
 		dev_warn(&intf->dev, "ignoring external hub\n");
@@ -2696,6 +2719,33 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
 			break;
 		}
 	}
+
+#ifdef STMP3XXX_USB_HOST_HACK
+	{	/*Must enable HOSTDISCONDETECT after second reset*/
+		if (port1 == 1) {
+			if (udev->speed == USB_SPEED_HIGH) {
+				stmp3xxx_setl(
+					BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+					REGS_USBPHY_BASE + HW_USBPHY_CTRL);
+			}
+		}
+	}
+#endif
+
+#ifdef MXS_USB_HOST_HACK
+	{	/*Must enable HOSTDISCONDETECT after second reset*/
+		if (port1 == 1) {
+			if (udev->speed == USB_SPEED_HIGH) {
+				struct device *dev = hcd->self.controller;
+				struct fsl_usb2_platform_data *pdata;
+				pdata = (struct fsl_usb2_platform_data *)
+					 dev->platform_data;
+				fsl_platform_set_usb_phy_dis(pdata, 1);
+			}
+		}
+	}
+#endif
+
 	if (retval)
 		goto fail;
 
@@ -2823,6 +2873,53 @@ static void hub_port_connect_change(struct usb_hub *hub, int port1,
 		"port %d, status %04x, change %04x, %s\n",
 		port1, portstatus, portchange, portspeed (portstatus));
 
+#ifdef STMP3XXX_USB_HOST_HACK
+	{
+	/*
+	 * FIXME: the USBPHY of STMP3xxx SoC has bug. The usb port power
+	 * is never enabled during standard ehci reset procedure if the
+	 * external device once passed plug/unplug procedure. This work-
+	 * around resets and reinitiates USBPHY before the ehci port reset
+	 * sequence started.
+	 */
+		struct device *dev = hcd->self.controller;
+		struct fsl_usb2_platform_data *pdata;
+
+		pdata = (struct fsl_usb2_platform_data *)dev->platform_data;
+		if (dev->parent && dev->type) {
+			if (port1 == 1 && pdata->platform_init)
+				pdata->platform_init(NULL);
+		}
+		if (port1 == 1) {
+			if (!(portstatus&USB_PORT_STAT_CONNECTION)) {
+				/* Must clear HOSTDISCONDETECT when disconnect*/
+				stmp3xxx_clearl(
+					BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+					REGS_USBPHY_BASE + HW_USBPHY_CTRL);
+			}
+		}
+	}
+#endif
+
+#ifdef MXS_USB_HOST_HACK
+	{
+		struct device *dev = hcd->self.controller;
+		struct fsl_usb2_platform_data *pdata;
+
+		pdata = (struct fsl_usb2_platform_data *)dev->platform_data;
+		if (dev->parent && dev->type) {
+			if (port1 == 1 && pdata->platform_init)
+				pdata->platform_init(NULL);
+		}
+		if (port1 == 1) {
+			if (!(portstatus&USB_PORT_STAT_CONNECTION)) {
+				/* Must clear HOSTDISCONDETECT when disconnect*/
+				fsl_platform_set_usb_phy_dis(pdata, 0);
+			}
+		}
+	}
+#endif
+
 	if (hub->has_indicators) {
 		set_port_led(hub, port1, HUB_LED_AUTO);
 		hub->indicator[port1-1] = INDICATOR_AUTO;
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 7f8e83a954ac..a19d73730470 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -209,17 +209,6 @@ config USB_OMAP
 	default USB_GADGET
 	select USB_GADGET_SELECTED
 
-config USB_OTG
-	boolean "OTG Support"
-	depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD
-	help
-	   The most notable feature of USB OTG is support for a
-	   "Dual-Role" device, which can act as either a device
-	   or a host.  The initial role choice can be changed
-	   later, when two dual-role devices talk to each other.
-
-	   Select this only if your OMAP board has a Mini-AB connector.
-
 config USB_GADGET_PXA25X
 	boolean "PXA 25x or IXP 4xx"
 	depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX
@@ -474,6 +463,40 @@ config USB_GOKU
 	default USB_GADGET
 	select USB_GADGET_SELECTED
 
+config USB_GADGET_ARC
+	boolean "Freescale USB Device Controller"
+	depends on ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS
+	select USB_GADGET_DUALSPEED
+	select USB_OTG_UTILS
+	select USB_GADGET_DUALSPEED if USB_GADGET_FSL_1504 || USB_GADGET_FSL_UTMI
+	help
+	   Some Freescale processors have a USBOTG controller,
+	   which supports device mode.
+
+	   Say "y" to link the driver statically, or "m" to build a
+	   dynamically linked module called "arc_udc" and force all
+	   gadget drivers to also be dynamically linked.
+
+config USB_STATIC_IRAM_PPH
+	bool "Apply static IRAM patch"
+	depends on USB_GADGET_ARC && (ARCH_MX37 || ARCH_MX3 || ARCH_MX25 || ARCH_MX51)
+	help
+	   Apply static IRAM patch to peripheral driver.
+
+config USB_ARC
+	tristate
+	depends on USB_GADGET_ARC
+	default USB_GADGET
+	select USB_GADGET_SELECTED
+
+config WORKAROUND_ARCUSB_REG_RW
+        bool "work around mx28 arch register write"
+        depends on ARCH_MX28 && USB_ARC
+        default ARCH_MX28
+        help
+           MX28 require read ARC register before write. Use SWP intructure to
+           implement this requirement.
+
 config USB_GADGET_LANGWELL
 	boolean "Intel Langwell USB Device Controller"
 	depends on PCI
@@ -542,6 +565,18 @@ config USB_GADGET_DUALSPEED
 	  Means that gadget drivers should include extra descriptors
 	  and code to handle dual-speed controllers.
 
+config USB_OTG
+	boolean "OTG Support"
+	depends on (USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD) || \
+		   (USB_GADGET_ARC && (ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS) && USB_EHCI_HCD)
+	help
+	   The most notable feature of USB OTG is support for a
+	   "Dual-Role" device, which can act as either a device
+	   or a host.  The initial role choice can be changed
+	   later, when two dual-role devices talk to each other.
+
+	   Select this only if your OMAP board has a Mini-AB connector.
+
 #
 # USB Gadget Drivers
 #
@@ -692,6 +727,12 @@ config USB_FILE_STORAGE
 	  Say "y" to link the driver statically, or "m" to build a
 	  dynamically linked module called "g_file_storage".
 
+config FSL_UTP
+	bool "UTP over Storage Gadget"
+	depends on USB_FILE_STORAGE
+	help
+	  Freescale's extension to MSC protocol
+
 config USB_FILE_STORAGE_TEST
 	bool "File-backed Storage Gadget testing version"
 	depends on USB_FILE_STORAGE
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index e6017e6bf6da..477114e43372 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_USB_FSL_QE)	+= fsl_qe_udc.o
 obj-$(CONFIG_USB_CI13XXX)	+= ci13xxx_udc.o
 obj-$(CONFIG_USB_S3C_HSOTG)	+= s3c-hsotg.o
 obj-$(CONFIG_USB_LANGWELL)	+= langwell_udc.o
+obj-$(CONFIG_USB_ARC)		+= arcotg_udc.o
 
 #
 # USB gadget drivers
diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
new file mode 100644
index 000000000000..9947da5fa035
--- /dev/null
+++ b/drivers/usb/gadget/arcotg_udc.c
@@ -0,0 +1,3104 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#undef DEBUG
+#undef VERBOSE
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/dmapool.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/dma.h>
+#include <asm/cacheflush.h>
+
+#include "arcotg_udc.h"
+#include <mach/arc_otg.h>
+#include <linux/iram_alloc.h>
+
+#define	DRIVER_DESC	"ARC USBOTG Device Controller driver"
+#define	DRIVER_AUTHOR	"Freescale Semiconductor"
+#define	DRIVER_VERSION	"1 August 2005"
+
+#ifdef CONFIG_PPC_MPC512x
+#define BIG_ENDIAN_DESC
+#endif
+
+#ifdef BIG_ENDIAN_DESC
+#define cpu_to_hc32(x)	(x)
+#define hc32_to_cpu(x)	(x)
+#else
+#define cpu_to_hc32(x)	cpu_to_le32((x))
+#define hc32_to_cpu(x)	le32_to_cpu((x))
+#endif
+
+#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
+
+static const char driver_name[] = "fsl-usb2-udc";
+static const char driver_desc[] = DRIVER_DESC;
+
+volatile static struct usb_dr_device *dr_regs;
+volatile static struct usb_sys_interface *usb_sys_regs;
+
+/* it is initialized in probe()  */
+static struct fsl_udc *udc_controller;
+
+#ifdef POSTPONE_FREE_LAST_DTD
+static struct ep_td_struct *last_free_td;
+#endif
+static const struct usb_endpoint_descriptor
+fsl_ep0_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+	.bEndpointAddress =	0,
+	.bmAttributes =		USB_ENDPOINT_XFER_CONTROL,
+	.wMaxPacketSize =	USB_MAX_CTRL_PAYLOAD,
+};
+static const size_t g_iram_size = IRAM_TD_PPH_SIZE;
+static unsigned long g_iram_base;
+static __iomem void *g_iram_addr;
+
+typedef int (*dev_sus)(struct device *dev, pm_message_t state);
+typedef int (*dev_res) (struct device *dev);
+static int udc_suspend(struct fsl_udc *udc);
+static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state);
+static int fsl_udc_resume(struct platform_device *pdev);
+static void fsl_ep_fifo_flush(struct usb_ep *_ep);
+
+#ifdef CONFIG_USB_OTG
+/* Get platform resource from OTG driver */
+extern struct resource *otg_get_resources(void);
+#endif
+
+extern void fsl_platform_set_test_mode(struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode);
+
+static inline void
+dr_wake_up_enable(struct fsl_udc *udc, bool enable)
+{
+	struct fsl_usb2_platform_data *pdata;
+	pdata = udc->pdata;
+
+	if (enable && (!device_may_wakeup(udc_controller->gadget.dev.parent)))
+		return;
+
+	if (pdata->wake_up_enable)
+		pdata->wake_up_enable(pdata, enable);
+}
+
+#ifdef CONFIG_WORKAROUND_ARCUSB_REG_RW
+static void safe_writel(u32 val32, void *addr)
+{
+	__asm__ ("swp %0, %0, [%1]" : : "r"(val32), "r"(addr));
+}
+#endif
+
+#ifdef CONFIG_PPC32
+#define fsl_readl(addr)		in_le32((addr))
+#define fsl_writel(addr, val32) out_le32((val32), (addr))
+#elif defined (CONFIG_WORKAROUND_ARCUSB_REG_RW)
+#define fsl_readl(addr)		readl((addr))
+#define fsl_writel(val32, addr) safe_writel(val32, addr)
+#else
+#define fsl_readl(addr)		readl((addr))
+#define fsl_writel(addr, val32) writel((addr), (val32))
+#endif
+
+/********************************************************************
+ *	Internal Used Function
+********************************************************************/
+
+#ifdef DUMP_QUEUES
+static void dump_ep_queue(struct fsl_ep *ep)
+{
+	int ep_index;
+	struct fsl_req *req;
+	struct ep_td_struct *dtd;
+
+	if (list_empty(&ep->queue)) {
+		pr_debug("udc: empty\n");
+		return;
+	}
+
+	ep_index = ep_index(ep) * 2 + ep_is_in(ep);
+	pr_debug("udc: ep=0x%p  index=%d\n", ep, ep_index);
+
+	list_for_each_entry(req, &ep->queue, queue) {
+		pr_debug("udc: req=0x%p  dTD count=%d\n", req, req->dtd_count);
+		pr_debug("udc: dTD head=0x%p  tail=0x%p\n", req->head,
+			 req->tail);
+
+		dtd = req->head;
+
+		while (dtd) {
+			if (le32_to_cpu(dtd->next_td_ptr) & DTD_NEXT_TERMINATE)
+				break;	/* end of dTD list */
+
+			dtd = dtd->next_td_virt;
+		}
+	}
+}
+#else
+static inline void dump_ep_queue(struct fsl_ep *ep)
+{
+}
+#endif
+
+#if (defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+/*
+ * The Phy at MX35 and MX25 have bugs, it must disable, and re-eable phy
+ * if the phy clock is disabled before
+ */
+static void reset_phy(void)
+{
+	u32 phyctrl;
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl &= ~PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl |= PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+}
+#else
+static void reset_phy(void){; }
+#endif
+/*-----------------------------------------------------------------
+ * done() - retire a request; caller blocked irqs
+ * @status : request status to be set, only works when
+ *	request is still in progress.
+ *--------------------------------------------------------------*/
+static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
+{
+	struct fsl_udc *udc = NULL;
+	unsigned char stopped = ep->stopped;
+	struct ep_td_struct *curr_td, *next_td;
+	int j;
+
+	udc = (struct fsl_udc *)ep->udc;
+	/* Removed the req from fsl_ep->queue */
+	list_del_init(&req->queue);
+
+	/* req.status should be set as -EINPROGRESS in ep_queue() */
+	if (req->req.status == -EINPROGRESS)
+		req->req.status = status;
+	else
+		status = req->req.status;
+
+	/* Free dtd for the request */
+	next_td = req->head;
+	for (j = 0; j < req->dtd_count; j++) {
+		curr_td = next_td;
+		if (j != req->dtd_count - 1) {
+			next_td = curr_td->next_td_virt;
+#ifdef POSTPONE_FREE_LAST_DTD
+			dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
+		} else {
+			if (last_free_td != NULL)
+				dma_pool_free(udc->td_pool, last_free_td,
+						last_free_td->td_dma);
+			last_free_td = curr_td;
+		}
+#else
+		}
+
+		dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
+#endif
+	}
+
+	if (USE_MSC_WR(req->req.length)) {
+		req->req.dma -= 1;
+		memmove(req->req.buf, req->req.buf + 1, MSC_BULK_CB_WRAP_LEN);
+	}
+
+	if (req->mapped) {
+		dma_unmap_single(ep->udc->gadget.dev.parent,
+			req->req.dma, req->req.length,
+			ep_is_in(ep)
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+		req->req.dma = DMA_ADDR_INVALID;
+		req->mapped = 0;
+	} else
+		dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
+			req->req.dma, req->req.length,
+			ep_is_in(ep)
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+
+	if (status && (status != -ESHUTDOWN))
+		VDBG("complete %s req %p stat %d len %u/%u",
+			ep->ep.name, &req->req, status,
+			req->req.actual, req->req.length);
+
+	ep->stopped = 1;
+
+	spin_unlock(&ep->udc->lock);
+	/* complete() is from gadget layer,
+	 * eg fsg->bulk_in_complete() */
+	if (req->req.complete)
+		req->req.complete(&ep->ep, &req->req);
+
+	spin_lock(&ep->udc->lock);
+	ep->stopped = stopped;
+}
+
+/*-----------------------------------------------------------------
+ * nuke(): delete all requests related to this ep
+ * called with spinlock held
+ *--------------------------------------------------------------*/
+static void nuke(struct fsl_ep *ep, int status)
+{
+	ep->stopped = 1;
+
+	/* Flush fifo */
+	fsl_ep_fifo_flush(&ep->ep);
+
+	/* Whether this eq has request linked */
+	while (!list_empty(&ep->queue)) {
+		struct fsl_req *req = NULL;
+
+		req = list_entry(ep->queue.next, struct fsl_req, queue);
+		done(ep, req, status);
+	}
+	dump_ep_queue(ep);
+}
+
+/*------------------------------------------------------------------
+	Internal Hardware related function
+ ------------------------------------------------------------------*/
+
+static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
+{
+	u32 temp;
+
+	if (!device_may_wakeup(udc_controller->gadget.dev.parent))
+		return;
+
+	if (enable) {
+		temp = fsl_readl(&dr_regs->portsc1);
+		temp |= PORTSCX_PHY_LOW_POWER_SPD;
+		fsl_writel(temp, &dr_regs->portsc1);
+
+		if (udc_controller->pdata->usb_clock_for_pm)
+			udc_controller->pdata->usb_clock_for_pm(false);
+	} else {
+		if (udc_controller->pdata->usb_clock_for_pm)
+			udc_controller->pdata->usb_clock_for_pm(true);
+
+		/* Due to mx35/mx25's phy's bug */
+		reset_phy();
+		temp = fsl_readl(&dr_regs->portsc1);
+		temp &= ~PORTSCX_PHY_LOW_POWER_SPD;
+		fsl_writel(temp, &dr_regs->portsc1);
+	}
+}
+
+static int dr_controller_setup(struct fsl_udc *udc)
+{
+	unsigned int tmp = 0, portctrl = 0;
+	unsigned int __attribute((unused)) ctrl = 0;
+	unsigned long timeout;
+	struct fsl_usb2_platform_data *pdata;
+
+#define FSL_UDC_RESET_TIMEOUT 1000
+
+	/* before here, make sure dr_regs has been initialized */
+	if (!udc)
+		return -EINVAL;
+	pdata = udc->pdata;
+
+	/* Stop and reset the usb controller */
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp &= ~USB_CMD_RUN_STOP;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp |= USB_CMD_CTRL_RESET;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	/* Wait for reset to complete */
+	timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
+	while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
+		if (time_after(jiffies, timeout)) {
+			ERR("udc reset timeout! \n");
+			return -ETIMEDOUT;
+		}
+		cpu_relax();
+	}
+
+	/* Set the controller as device mode */
+	tmp = fsl_readl(&dr_regs->usbmode);
+	tmp &= ~USB_MODE_CTRL_MODE_MASK;	/* clear mode bits */
+	tmp |= USB_MODE_CTRL_MODE_DEVICE;
+	/* Disable Setup Lockout */
+	tmp |= USB_MODE_SETUP_LOCK_OFF;
+	if (pdata->es)
+		tmp |= USB_MODE_ES;
+	fsl_writel(tmp, &dr_regs->usbmode);
+
+	fsl_platform_set_device_mode(pdata);
+
+	/* Clear the setup status */
+	fsl_writel(0, &dr_regs->usbsts);
+
+	tmp = udc->ep_qh_dma;
+	tmp &= USB_EP_LIST_ADDRESS_MASK;
+	fsl_writel(tmp, &dr_regs->endpointlistaddr);
+
+	VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
+		(int)udc->ep_qh, (int)tmp,
+		fsl_readl(&dr_regs->endpointlistaddr));
+
+	/* Config PHY interface */
+	portctrl = fsl_readl(&dr_regs->portsc1);
+	portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
+	switch (udc->phy_mode) {
+	case FSL_USB2_PHY_ULPI:
+		portctrl |= PORTSCX_PTS_ULPI;
+		break;
+	case FSL_USB2_PHY_UTMI_WIDE:
+		portctrl |= PORTSCX_PTW_16BIT;
+		/* fall through */
+	case FSL_USB2_PHY_UTMI:
+		portctrl |= PORTSCX_PTS_UTMI;
+		break;
+	case FSL_USB2_PHY_SERIAL:
+		portctrl |= PORTSCX_PTS_FSLS;
+		break;
+	default:
+		return -EINVAL;
+	}
+	fsl_writel(portctrl, &dr_regs->portsc1);
+
+	if (pdata->change_ahb_burst) {
+		/* if usb should not work in default INCRx mode */
+		tmp = fsl_readl(&dr_regs->sbuscfg);
+		tmp = (tmp & ~0x07) | pdata->ahb_burst_mode;
+		fsl_writel(tmp, &dr_regs->sbuscfg);
+	}
+
+	if (pdata->have_sysif_regs) {
+		/* Config control enable i/o output, cpu endian register */
+		ctrl = __raw_readl(&usb_sys_regs->control);
+		ctrl |= USB_CTRL_IOENB;
+		__raw_writel(ctrl, &usb_sys_regs->control);
+	}
+
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+	/* Turn on cache snooping hardware, since some PowerPC platforms
+	 * wholly rely on hardware to deal with cache coherent. */
+
+	if (pdata->have_sysif_regs) {
+		/* Setup Snooping for all the 4GB space */
+		tmp = SNOOP_SIZE_2GB;	/* starts from 0x0, size 2G */
+		__raw_writel(tmp, &usb_sys_regs->snoop1);
+		tmp |= 0x80000000;	/* starts from 0x8000000, size 2G */
+		__raw_writel(tmp, &usb_sys_regs->snoop2);
+	}
+#endif
+
+	return 0;
+}
+
+/* Enable DR irq and set controller to run state */
+static void dr_controller_run(struct fsl_udc *udc)
+{
+	u32 temp;
+
+	fsl_platform_pullup_enable(udc->pdata);
+
+	/* Enable DR irq reg */
+	temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
+		| USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
+		| USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
+
+	fsl_writel(temp, &dr_regs->usbintr);
+
+	if (device_may_wakeup(udc_controller->gadget.dev.parent)) {
+		/* enable BSV irq */
+		temp = fsl_readl(&dr_regs->otgsc);
+		temp |= OTGSC_B_SESSION_VALID_IRQ_EN;
+		fsl_writel(temp, &dr_regs->otgsc);
+	}
+
+	/* If vbus not on and used low power mode */
+	if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_B_SESSION_VALID)
+	    && device_may_wakeup(udc_controller->gadget.dev.parent)) {
+		/* enable wake up */
+		dr_wake_up_enable(udc, true);
+		/* Set stopped before low power mode */
+		udc->stopped = 1;
+		/* close PHY clock */
+		dr_phy_low_power_mode(udc, true);
+		printk(KERN_INFO "udc enter low power mode \n");
+	} else {
+#ifdef CONFIG_ARCH_MX37
+		/*
+		 add some delay for USB timing issue. USB may be
+		 recognize as FS device
+		 during USB gadget remote wake up function
+		*/
+		mdelay(100);
+#endif
+		/* Clear stopped bit */
+		udc->stopped = 0;
+		/* Set controller to Run */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		temp |= USB_CMD_RUN_STOP;
+		fsl_writel(temp, &dr_regs->usbcmd);
+		printk(KERN_INFO "udc run \n");
+	}
+
+	return;
+}
+
+static void dr_controller_stop(struct fsl_udc *udc)
+{
+	unsigned int tmp;
+
+	pr_debug("%s\n", __func__);
+
+	/* if we're in OTG mode, and the Host is currently using the port,
+	 * stop now and don't rip the controller out from under the
+	 * ehci driver
+	 */
+	if (udc->gadget.is_otg) {
+		if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+			pr_debug("udc: Leaving early\n");
+			return;
+		}
+	}
+
+	/* disable all INTR */
+	fsl_writel(0, &dr_regs->usbintr);
+
+	/* disable wake up */
+	dr_wake_up_enable(udc, false);
+	/* disable BSV irq */
+	tmp = fsl_readl(&dr_regs->otgsc);
+	tmp &= ~OTGSC_B_SESSION_VALID_IRQ_EN;
+	fsl_writel(tmp, &dr_regs->otgsc);
+
+	/* Set stopped bit for isr */
+	udc->stopped = 1;
+
+	/* disable IO output */
+/*	usb_sys_regs->control = 0; */
+
+	fsl_platform_pullup_disable(udc->pdata);
+
+	/* set controller to Stop */
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp &= ~USB_CMD_RUN_STOP;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	return;
+}
+
+void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
+{
+	unsigned int tmp_epctrl = 0;
+
+	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (dir) {
+		if (ep_num)
+			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
+		tmp_epctrl |= EPCTRL_TX_ENABLE;
+		tmp_epctrl |= ((unsigned int)(ep_type)
+				<< EPCTRL_TX_EP_TYPE_SHIFT);
+	} else {
+		if (ep_num)
+			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
+		tmp_epctrl |= EPCTRL_RX_ENABLE;
+		tmp_epctrl |= ((unsigned int)(ep_type)
+				<< EPCTRL_RX_EP_TYPE_SHIFT);
+	}
+
+	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
+}
+
+static void
+dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
+{
+	u32 tmp_epctrl = 0;
+
+	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+
+	if (value) {
+		/* set the stall bit */
+		if (dir)
+			tmp_epctrl |= EPCTRL_TX_EP_STALL;
+		else
+			tmp_epctrl |= EPCTRL_RX_EP_STALL;
+	} else {
+		/* clear the stall bit and reset data toggle */
+		if (dir) {
+			tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
+			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
+		} else {
+			tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
+			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
+		}
+	}
+	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
+}
+
+/* Get stall status of a specific ep
+   Return: 0: not stalled; 1:stalled */
+static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
+{
+	u32 epctrl;
+
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (dir)
+		return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
+	else
+		return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
+}
+
+/********************************************************************
+	Internal Structure Build up functions
+********************************************************************/
+
+/*------------------------------------------------------------------
+* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
+ * @zlt: Zero Length Termination Select (1: disable; 0: enable)
+ * @mult: Mult field
+ ------------------------------------------------------------------*/
+static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
+		unsigned char dir, unsigned char ep_type,
+		unsigned int max_pkt_len,
+		unsigned int zlt, unsigned char mult)
+{
+	struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
+	unsigned int tmp = 0;
+
+	/* set the Endpoint Capabilites in QH */
+	switch (ep_type) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		/* Interrupt On Setup (IOS). for control ep  */
+		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
+			| EP_QUEUE_HEAD_IOS;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
+			| (mult << EP_QUEUE_HEAD_MULT_POS);
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+	case USB_ENDPOINT_XFER_INT:
+		tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
+		break;
+	default:
+		VDBG("error ep type is %d", ep_type);
+		return;
+	}
+	if (zlt)
+		tmp |= EP_QUEUE_HEAD_ZLT_SEL;
+	p_QH->max_pkt_length = cpu_to_hc32(tmp);
+
+	return;
+}
+
+/* Setup qh structure and ep register for ep0. */
+static void ep0_setup(struct fsl_udc *udc)
+{
+	/* the intialization of an ep includes: fields in QH, Regs,
+	 * fsl_ep struct */
+	struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
+			USB_MAX_CTRL_PAYLOAD, 0, 0);
+	struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
+			USB_MAX_CTRL_PAYLOAD, 0, 0);
+	dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
+	dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
+
+	return;
+
+}
+
+/***********************************************************************
+		Endpoint Management Functions
+***********************************************************************/
+
+/*-------------------------------------------------------------------------
+ * when configurations are set, or when interface settings change
+ * for example the do_set_interface() in gadget layer,
+ * the driver will enable or disable the relevant endpoints
+ * ep0 doesn't use this routine. It is always enabled.
+-------------------------------------------------------------------------*/
+static int fsl_ep_enable(struct usb_ep *_ep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct fsl_udc *udc = NULL;
+	struct fsl_ep *ep = NULL;
+	unsigned short max = 0;
+	unsigned char mult = 0, zlt;
+	int retval = -EINVAL;
+	unsigned long flags = 0;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+
+	pr_debug("udc: %s ep.name=%s\n", __func__, ep->ep.name);
+	/* catch various bogus parameters */
+	if (!_ep || !desc || ep->desc
+			|| (desc->bDescriptorType != USB_DT_ENDPOINT))
+		return -EINVAL;
+
+	udc = ep->udc;
+
+	if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
+		return -ESHUTDOWN;
+
+	max = le16_to_cpu(desc->wMaxPacketSize);
+
+	/* Disable automatic zlp generation.  Driver is reponsible to indicate
+	 * explicitly through req->req.zero.  This is needed to enable multi-td
+	 * request. */
+	zlt = 1;
+
+	/* Assume the max packet size from gadget is always correct */
+	switch (desc->bmAttributes & 0x03) {
+	case USB_ENDPOINT_XFER_CONTROL:
+	case USB_ENDPOINT_XFER_BULK:
+	case USB_ENDPOINT_XFER_INT:
+		/* mult = 0.  Execute N Transactions as demonstrated by
+		 * the USB variable length packet protocol where N is
+		 * computed using the Maximum Packet Length (dQH) and
+		 * the Total Bytes field (dTD) */
+		mult = 0;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		/* Calculate transactions needed for high bandwidth iso */
+		mult = (unsigned char)(1 + ((max >> 11) & 0x03));
+		max = max & 0x7ff;	/* bit 0~10 */
+		/* 3 transactions at most */
+		if (mult > 3)
+			goto en_done;
+		break;
+	default:
+		goto en_done;
+	}
+
+	spin_lock_irqsave(&udc->lock, flags);
+	ep->ep.maxpacket = max;
+	ep->desc = desc;
+	ep->stopped = 0;
+
+	/* Controller related setup */
+	/* Init EPx Queue Head (Ep Capabilites field in QH
+	 * according to max, zlt, mult) */
+	struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
+			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
+					?  USB_SEND : USB_RECV),
+			(unsigned char) (desc->bmAttributes
+					& USB_ENDPOINT_XFERTYPE_MASK),
+			max, zlt, mult);
+
+	/* Init endpoint ctrl register */
+	dr_ep_setup((unsigned char) ep_index(ep),
+			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
+					? USB_SEND : USB_RECV),
+			(unsigned char) (desc->bmAttributes
+					& USB_ENDPOINT_XFERTYPE_MASK));
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+	retval = 0;
+
+	VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
+			ep->desc->bEndpointAddress & 0x0f,
+			(desc->bEndpointAddress & USB_DIR_IN)
+				? "in" : "out", max);
+en_done:
+	return retval;
+}
+
+/*---------------------------------------------------------------------
+ * @ep : the ep being unconfigured. May not be ep0
+ * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
+*---------------------------------------------------------------------*/
+static int fsl_ep_disable(struct usb_ep *_ep)
+{
+	struct fsl_udc *udc = NULL;
+	struct fsl_ep *ep = NULL;
+	unsigned long flags = 0;
+	u32 epctrl;
+	int ep_num;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	if (!_ep || !ep->desc) {
+		VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
+		return -EINVAL;
+	}
+
+	/* disable ep on controller */
+	ep_num = ep_index(ep);
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl &= ~EPCTRL_TX_ENABLE;
+	else
+		epctrl &= ~EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+
+	udc = (struct fsl_udc *)ep->udc;
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* nuke all pending requests (does flush) */
+	nuke(ep, -ESHUTDOWN);
+
+	ep->desc = 0;
+	ep->stopped = 1;
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	VDBG("disabled %s OK", _ep->name);
+	return 0;
+}
+
+/*---------------------------------------------------------------------
+ * allocate a request object used by this endpoint
+ * the main operation is to insert the req->queue to the eq->queue
+ * Returns the request, or null if one could not be allocated
+*---------------------------------------------------------------------*/
+static struct usb_request *
+fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+	struct fsl_req *req = NULL;
+
+	req = kzalloc(sizeof *req, gfp_flags);
+	if (!req)
+		return NULL;
+
+	req->req.dma = DMA_ADDR_INVALID;
+	pr_debug("udc: req=0x%p   set req.dma=0x%x\n", req, req->req.dma);
+	INIT_LIST_HEAD(&req->queue);
+
+	return &req->req;
+}
+
+static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct fsl_req *req = NULL;
+
+	req = container_of(_req, struct fsl_req, req);
+
+	if (_req)
+		kfree(req);
+}
+
+static void update_qh(struct fsl_req *req)
+{
+	struct fsl_ep *ep = req->ep;
+	int i = ep_index(ep) * 2 + ep_is_in(ep);
+	u32 temp;
+	struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
+
+	/* Write dQH next pointer and terminate bit to 0 */
+	temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
+	if (NEED_IRAM(req->ep)) {
+		/* set next dtd stop bit,ensure only one dtd in this list */
+		req->cur->next_td_ptr |= cpu_to_hc32(DTD_NEXT_TERMINATE);
+		temp = req->cur->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
+	}
+	dQH->next_dtd_ptr = cpu_to_hc32(temp);
+	/* Clear active and halt bit */
+	temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
+			     | EP_QUEUE_HEAD_STATUS_HALT));
+	dQH->size_ioc_int_sts &= temp;
+
+	/* Prime endpoint by writing 1 to ENDPTPRIME */
+	temp = ep_is_in(ep)
+	    ? (1 << (ep_index(ep) + 16))
+	    : (1 << (ep_index(ep)));
+	fsl_writel(temp, &dr_regs->endpointprime);
+}
+
+/*-------------------------------------------------------------------------*/
+static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
+{
+	u32 temp, bitmask, tmp_stat;
+
+	/* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
+	VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
+
+	bitmask = ep_is_in(ep)
+		? (1 << (ep_index(ep) + 16))
+		: (1 << (ep_index(ep)));
+
+	/* check if the pipe is empty */
+	if (!(list_empty(&ep->queue))) {
+		/* Add td to the end */
+		struct fsl_req *lastreq;
+		lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
+		if (NEED_IRAM(ep)) {
+			/* only one dtd in dqh */
+			lastreq->tail->next_td_ptr =
+			    cpu_to_hc32(req->head->td_dma | DTD_NEXT_TERMINATE);
+			goto out;
+		} else {
+			lastreq->tail->next_td_ptr =
+			    cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
+		}
+		/* Read prime bit, if 1 goto done */
+		if (fsl_readl(&dr_regs->endpointprime) & bitmask)
+			goto out;
+		do {
+			/* Set ATDTW bit in USBCMD */
+			temp = fsl_readl(&dr_regs->usbcmd);
+			fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
+
+			/* Read correct status bit */
+			tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
+
+		} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
+
+		/* Write ATDTW bit to 0 */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
+
+		if (tmp_stat)
+			goto out;
+	}
+	update_qh(req);
+out:
+	return 0;
+}
+
+/* Fill in the dTD structure
+ * @req: request that the transfer belongs to
+ * @length: return actually data length of the dTD
+ * @dma: return dma address of the dTD
+ * @is_last: return flag if it is the last dTD of the request
+ * return: pointer to the built dTD */
+static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
+		dma_addr_t *dma, int *is_last)
+{
+	u32 swap_temp;
+	struct ep_td_struct *dtd;
+
+	/* how big will this transfer be? */
+	*length = min(req->req.length - req->req.actual,
+			(unsigned)EP_MAX_LENGTH_TRANSFER);
+	if (NEED_IRAM(req->ep))
+		*length = min(*length, g_iram_size);
+	dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
+	if (dtd == NULL)
+		return dtd;
+
+	dtd->td_dma = *dma;
+	/* Clear reserved field */
+	swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
+	swap_temp &= ~DTD_RESERVED_FIELDS;
+	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
+
+	/* Init all of buffer page pointers */
+	swap_temp = (u32) (req->req.dma + req->req.actual);
+	if (NEED_IRAM(req->ep))
+		swap_temp = (u32) (req->req.dma);
+	dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
+	dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
+	dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
+	dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
+	dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
+
+	req->req.actual += *length;
+
+	/* zlp is needed if req->req.zero is set */
+	if (req->req.zero) {
+		if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
+			*is_last = 1;
+		else
+			*is_last = 0;
+	} else if (req->req.length == req->req.actual)
+		*is_last = 1;
+	else
+		*is_last = 0;
+
+	if ((*is_last) == 0)
+		VDBG("multi-dtd request!\n");
+	/* Fill in the transfer size; set active bit */
+	swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
+
+	/* Enable interrupt for the last dtd of a request */
+	if (*is_last && !req->req.no_interrupt)
+		swap_temp |= DTD_IOC;
+	if (NEED_IRAM(req->ep))
+		swap_temp |= DTD_IOC;
+
+	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
+
+	mb();
+
+	VDBG("length = %d address= 0x%x", *length, (int)*dma);
+
+	return dtd;
+}
+
+/* Generate dtd chain for a request */
+static int fsl_req_to_dtd(struct fsl_req *req)
+{
+	unsigned	count;
+	int		is_last;
+	int		is_first = 1;
+	struct ep_td_struct	*last_dtd = NULL, *dtd;
+	dma_addr_t dma;
+
+	if (NEED_IRAM(req->ep)) {
+		req->oridma = req->req.dma;
+		/* here, replace user buffer to iram buffer */
+		if (ep_is_in(req->ep)) {
+			req->req.dma = req->ep->udc->iram_buffer[1];
+			if ((list_empty(&req->ep->queue))) {
+				/* copy data only when no bulk in transfer is
+				   running */
+				memcpy((char *)req->ep->udc->iram_buffer_v[1],
+				       req->req.buf, min(req->req.length,
+							 g_iram_size));
+			}
+		} else {
+			req->req.dma = req->ep->udc->iram_buffer[0];
+		}
+	}
+
+	if (USE_MSC_WR(req->req.length))
+		req->req.dma += 1;
+
+	do {
+		dtd = fsl_build_dtd(req, &count, &dma, &is_last);
+		if (dtd == NULL)
+			return -ENOMEM;
+
+		if (is_first) {
+			is_first = 0;
+			req->head = dtd;
+		} else {
+			last_dtd->next_td_ptr = cpu_to_hc32(dma);
+			last_dtd->next_td_virt = dtd;
+		}
+		last_dtd = dtd;
+
+		req->dtd_count++;
+	} while (!is_last);
+
+	dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
+	req->cur = req->head;
+	req->tail = dtd;
+
+	return 0;
+}
+
+/* queues (submits) an I/O request to an endpoint */
+static int
+fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
+	struct fsl_req *req = container_of(_req, struct fsl_req, req);
+	struct fsl_udc *udc;
+	unsigned long flags;
+	int is_iso = 0;
+
+	/* catch various bogus parameters */
+	if (!_req || !req->req.buf || (ep_index(ep)
+				      && !list_empty(&req->queue))) {
+		VDBG("%s, bad params\n", __func__);
+		return -EINVAL;
+	}
+	if (!_ep || (!ep->desc && ep_index(ep))) {
+		VDBG("%s, bad ep\n", __func__);
+		return -EINVAL;
+	}
+	if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+		if (req->req.length > ep->ep.maxpacket)
+			return -EMSGSIZE;
+		is_iso = 1;
+	}
+
+	udc = ep->udc;
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+
+	req->ep = ep;
+
+	/* map virtual address to hardware */
+	if (req->req.dma == DMA_ADDR_INVALID) {
+		req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
+					req->req.buf,
+					req->req.length, ep_is_in(ep)
+						? DMA_TO_DEVICE
+						: DMA_FROM_DEVICE);
+		req->mapped = 1;
+	} else {
+		dma_sync_single_for_device(ep->udc->gadget.dev.parent,
+					req->req.dma, req->req.length,
+					ep_is_in(ep)
+						? DMA_TO_DEVICE
+						: DMA_FROM_DEVICE);
+		req->mapped = 0;
+	}
+
+	req->req.status = -EINPROGRESS;
+	req->req.actual = 0;
+	req->dtd_count = 0;
+	if (NEED_IRAM(ep)) {
+		req->last_one = 0;
+		req->buffer_offset = 0;
+	}
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* build dtds and push them to device queue */
+	if (!fsl_req_to_dtd(req)) {
+		fsl_queue_td(ep, req);
+	} else {
+		spin_unlock_irqrestore(&udc->lock, flags);
+		return -ENOMEM;
+	}
+
+	/* irq handler advances the queue */
+	if (req != NULL)
+		list_add_tail(&req->queue, &ep->queue);
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return 0;
+}
+
+/* dequeues (cancels, unlinks) an I/O request from an endpoint */
+static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
+	struct fsl_req *req;
+	unsigned long flags;
+	int ep_num, stopped, ret = 0;
+	u32 epctrl;
+
+	if (!_ep || !_req)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ep->udc->lock, flags);
+	stopped = ep->stopped;
+
+	/* Stop the ep before we deal with the queue */
+	ep->stopped = 1;
+	ep_num = ep_index(ep);
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl &= ~EPCTRL_TX_ENABLE;
+	else
+		epctrl &= ~EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+
+	/* make sure it's actually queued on this endpoint */
+	list_for_each_entry(req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* The request is in progress, or completed but not dequeued */
+	if (ep->queue.next == &req->queue) {
+		_req->status = -ECONNRESET;
+		fsl_ep_fifo_flush(_ep);	/* flush current transfer */
+
+		/* The request isn't the last request in this ep queue */
+		if (req->queue.next != &ep->queue) {
+			struct ep_queue_head *qh;
+			struct fsl_req *next_req;
+
+			qh = ep->qh;
+			next_req = list_entry(req->queue.next, struct fsl_req,
+					queue);
+
+			/* Point the QH to the first TD of next request */
+			fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
+		}
+
+		/* The request hasn't been processed, patch up the TD chain */
+	} else {
+		struct fsl_req *prev_req;
+
+		prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
+		fsl_writel(fsl_readl(&req->tail->next_td_ptr),
+				&prev_req->tail->next_td_ptr);
+
+	}
+
+	done(ep, req, -ECONNRESET);
+
+	/* Enable EP */
+out:	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl |= EPCTRL_TX_ENABLE;
+	else
+		epctrl |= EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+	ep->stopped = stopped;
+
+	spin_unlock_irqrestore(&ep->udc->lock, flags);
+	return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------
+ * modify the endpoint halt feature
+ * @ep: the non-isochronous endpoint being stalled
+ * @value: 1--set halt  0--clear halt
+ * Returns zero, or a negative error code.
+*----------------------------------------------------------------*/
+static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
+{
+	struct fsl_ep *ep = NULL;
+	unsigned long flags = 0;
+	int status = -EOPNOTSUPP;	/* operation not supported */
+	unsigned char ep_dir = 0, ep_num = 0;
+	struct fsl_udc *udc = NULL;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	udc = ep->udc;
+	if (!_ep || !ep->desc) {
+		status = -EINVAL;
+		goto out;
+	}
+
+	if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+		status = -EOPNOTSUPP;
+		goto out;
+	}
+
+	/* Attempt to halt IN ep will fail if any transfer requests
+	 * are still queue */
+	if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
+		status = -EAGAIN;
+		goto out;
+	}
+
+	status = 0;
+	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
+	ep_num = (unsigned char)(ep_index(ep));
+	spin_lock_irqsave(&ep->udc->lock, flags);
+	dr_ep_change_stall(ep_num, ep_dir, value);
+	spin_unlock_irqrestore(&ep->udc->lock, flags);
+
+	if (ep_index(ep) == 0) {
+		udc->ep0_dir = 0;
+	}
+out:
+	VDBG(" %s %s halt stat %d", ep->ep.name,
+			value ?  "set" : "clear", status);
+
+	return status;
+}
+
+static int arcotg_fifo_status(struct usb_ep *_ep)
+{
+	struct fsl_ep *ep;
+	struct fsl_udc *udc;
+	int size = 0;
+	u32 bitmask;
+	struct ep_queue_head *d_qh;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	if (!_ep || (!ep->desc && ep_index(ep) != 0))
+		return -ENODEV;
+
+	udc = (struct fsl_udc *)ep->udc;
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+
+	d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
+
+	bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
+	    (1 << (ep_index(ep)));
+
+	if (fsl_readl(&dr_regs->endptstatus) & bitmask)
+		size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
+		    >> DTD_LENGTH_BIT_POS;
+
+	pr_debug("%s %u\n", __func__, size);
+	return size;
+}
+
+static void fsl_ep_fifo_flush(struct usb_ep *_ep)
+{
+	struct fsl_ep *ep;
+	int ep_num, ep_dir;
+	u32 bits;
+	unsigned long timeout;
+#define FSL_UDC_FLUSH_TIMEOUT 1000
+
+	if (!_ep) {
+		return;
+	} else {
+		ep = container_of(_ep, struct fsl_ep, ep);
+		if (!ep->desc)
+			return;
+	}
+	ep_num = ep_index(ep);
+	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
+
+	if (ep_num == 0)
+		bits = (1 << 16) | 1;
+	else if (ep_dir == USB_SEND)
+		bits = 1 << (16 + ep_num);
+	else
+		bits = 1 << ep_num;
+
+	timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
+	do {
+		fsl_writel(bits, &dr_regs->endptflush);
+
+		/* Wait until flush complete */
+		while (fsl_readl(&dr_regs->endptflush)) {
+			if (time_after(jiffies, timeout)) {
+				ERR("ep flush timeout\n");
+				return;
+			}
+			cpu_relax();
+		}
+		/* See if we need to flush again */
+	} while (fsl_readl(&dr_regs->endptstatus) & bits);
+}
+
+static struct usb_ep_ops fsl_ep_ops = {
+	.enable = fsl_ep_enable,
+	.disable = fsl_ep_disable,
+
+	.alloc_request = fsl_alloc_request,
+	.free_request = fsl_free_request,
+
+	.queue = fsl_ep_queue,
+	.dequeue = fsl_ep_dequeue,
+
+	.set_halt = fsl_ep_set_halt,
+	.fifo_status = arcotg_fifo_status,
+	.fifo_flush = fsl_ep_fifo_flush,	/* flush fifo */
+};
+
+/*-------------------------------------------------------------------------
+		Gadget Driver Layer Operations
+-------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+ * Get the current frame number (from DR frame_index Reg )
+ *----------------------------------------------------------------------*/
+static int fsl_get_frame(struct usb_gadget *gadget)
+{
+	return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
+}
+
+/*-----------------------------------------------------------------------
+ * Tries to wake up the host connected to this gadget
+ -----------------------------------------------------------------------*/
+static int fsl_wakeup(struct usb_gadget *gadget)
+{
+	struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
+	u32 portsc;
+
+	/* Remote wakeup feature not enabled by host */
+	if (!udc->remote_wakeup)
+		return -ENOTSUPP;
+
+	portsc = fsl_readl(&dr_regs->portsc1);
+	/* not suspended? */
+	if (!(portsc & PORTSCX_PORT_SUSPEND))
+		return 0;
+	/* trigger force resume */
+	portsc |= PORTSCX_PORT_FORCE_RESUME;
+	fsl_writel(portsc, &dr_regs->portsc1);
+	return 0;
+}
+
+static int can_pullup(struct fsl_udc *udc)
+{
+	return udc->driver && udc->softconnect && udc->vbus_active;
+}
+
+/* Notify controller that VBUS is powered, Called by whatever
+   detects VBUS sessions */
+static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	struct fsl_udc	*udc;
+	unsigned long	flags;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	spin_lock_irqsave(&udc->lock, flags);
+	VDBG("VBUS %s\n", is_active ? "on" : "off");
+	udc->vbus_active = (is_active != 0);
+	if (can_pullup(udc))
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	else
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	spin_unlock_irqrestore(&udc->lock, flags);
+	return 0;
+}
+
+/* constrain controller's VBUS power usage
+ * This call is used by gadget drivers during SET_CONFIGURATION calls,
+ * reporting how much power the device may consume.  For example, this
+ * could affect how quickly batteries are recharged.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+{
+	struct fsl_udc *udc;
+	struct fsl_usb2_platform_data *pdata;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	if (udc->transceiver)
+		return otg_set_power(udc->transceiver, mA);
+	pdata = udc->pdata;
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_draw) {
+		pdata->xcvr_ops->set_vbus_draw(pdata->xcvr_ops, pdata, mA);
+		return 0;
+	}
+	return -ENOTSUPP;
+}
+
+/* Change Data+ pullup status
+ * this func is used by usb_gadget_connect/disconnet
+ */
+static int fsl_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct fsl_udc *udc;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	udc->softconnect = (is_on != 0);
+	if (can_pullup(udc))
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	else
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+
+	return 0;
+}
+
+/* defined in gadget.h */
+static struct usb_gadget_ops fsl_gadget_ops = {
+	.get_frame = fsl_get_frame,
+	.wakeup = fsl_wakeup,
+/*	.set_selfpowered = fsl_set_selfpowered,	*/ /* Always selfpowered */
+	.vbus_session = fsl_vbus_session,
+	.vbus_draw = fsl_vbus_draw,
+	.pullup = fsl_pullup,
+};
+
+/* Set protocol stall on ep0, protocol stall will automatically be cleared
+   on new transaction */
+static void ep0stall(struct fsl_udc *udc)
+{
+	u32 tmp;
+
+	/* must set tx and rx to stall at the same time */
+	tmp = fsl_readl(&dr_regs->endptctrl[0]);
+	tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
+	fsl_writel(tmp, &dr_regs->endptctrl[0]);
+	udc->ep0_dir = 0;
+}
+
+/* Prime a status phase for ep0 */
+static int ep0_prime_status(struct fsl_udc *udc, int direction)
+{
+	struct fsl_req *req = udc->status_req;
+	struct fsl_ep *ep;
+	int status = 0;
+
+	if (direction == EP_DIR_IN)
+		udc->ep0_dir = USB_DIR_IN;
+	else
+		udc->ep0_dir = USB_DIR_OUT;
+
+	ep = &udc->eps[0];
+
+	req->ep = ep;
+	req->req.length = 0;
+	req->req.status = -EINPROGRESS;
+
+	status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC);
+	return status;
+}
+
+static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
+{
+	struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
+
+	if (!ep->name)
+		return 0;
+
+	nuke(ep, -ESHUTDOWN);
+
+	return 0;
+}
+
+/*
+ * ch9 Set address
+ */
+static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
+{
+	/* Save the new address to device struct */
+	udc->device_address = (u8) value;
+	/* Update usb state */
+	udc->usb_state = USB_STATE_ADDRESS;
+	/* Status phase */
+	if (ep0_prime_status(udc, EP_DIR_IN))
+		ep0stall(udc);
+}
+
+/*
+ * ch9 Get status
+ */
+static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
+		u16 index, u16 length)
+{
+	u16 tmp = 0;		/* Status, cpu endian */
+
+	struct fsl_req *req;
+	struct fsl_ep *ep;
+	int status = 0;
+
+	ep = &udc->eps[0];
+
+	if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+		/* Get device status */
+		tmp = 1 << USB_DEVICE_SELF_POWERED;
+		tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
+		/* Get interface status */
+		/* We don't have interface information in udc driver */
+		tmp = 0;
+	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
+		/* Get endpoint status */
+		struct fsl_ep *target_ep;
+
+		target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
+
+		/* stall if endpoint doesn't exist */
+		if (!target_ep->desc)
+			goto stall;
+		tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
+				<< USB_ENDPOINT_HALT;
+	}
+
+	udc->ep0_dir = USB_DIR_IN;
+	/* Borrow the per device data_req */
+	/* status_req had been used to prime status */
+	req = udc->data_req;
+	/* Fill in the reqest structure */
+	*((u16 *) req->req.buf) = cpu_to_le16(tmp);
+	req->ep = ep;
+	req->req.length = 2;
+
+	status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC);
+	if (status) {
+		udc_reset_ep_queue(udc, 0);
+		ERR("Can't respond to getstatus request \n");
+		goto stall;
+	}
+	return;
+stall:
+	ep0stall(udc);
+
+}
+
+static void setup_received_irq(struct fsl_udc *udc,
+		struct usb_ctrlrequest *setup)
+{
+	u16 wValue = le16_to_cpu(setup->wValue);
+	u16 wIndex = le16_to_cpu(setup->wIndex);
+	u16 wLength = le16_to_cpu(setup->wLength);
+	struct usb_gadget *gadget = &(udc->gadget);
+	unsigned mA = 500;
+	udc_reset_ep_queue(udc, 0);
+
+	if (wLength) {
+		int dir;
+		dir = EP_DIR_IN;
+		if (setup->bRequestType & USB_DIR_IN) {
+			dir = EP_DIR_OUT;
+		}
+		if (ep0_prime_status(udc, dir))
+			ep0stall(udc);
+	}
+	/* We process some stardard setup requests here */
+	switch (setup->bRequest) {
+	case USB_REQ_GET_STATUS:
+		/* Data+Status phase from udc */
+		if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
+					!= (USB_DIR_IN | USB_TYPE_STANDARD))
+			break;
+		ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
+		return;
+
+	case USB_REQ_SET_ADDRESS:
+		/* Status phase from udc */
+		if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
+						| USB_RECIP_DEVICE))
+			break;
+		ch9setaddress(udc, wValue, wIndex, wLength);
+		return;
+	case USB_REQ_SET_CONFIGURATION:
+		fsl_vbus_draw(gadget, mA);
+	     break;
+	case USB_REQ_CLEAR_FEATURE:
+	case USB_REQ_SET_FEATURE:
+		/* Status phase from udc */
+	{
+		int rc = -EOPNOTSUPP;
+		u16 ptc = 0;
+
+		if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
+				== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
+			int pipe = get_pipe_by_windex(wIndex);
+			struct fsl_ep *ep;
+
+			if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
+				break;
+			ep = get_ep_by_pipe(udc, pipe);
+
+			spin_unlock(&udc->lock);
+			rc = fsl_ep_set_halt(&ep->ep,
+					(setup->bRequest == USB_REQ_SET_FEATURE)
+						? 1 : 0);
+			spin_lock(&udc->lock);
+
+		} else if ((setup->bRequestType & (USB_RECIP_MASK
+				| USB_TYPE_MASK)) == (USB_RECIP_DEVICE
+				| USB_TYPE_STANDARD)) {
+			/* Note: The driver has not include OTG support yet.
+			 * This will be set when OTG support is added */
+			if (setup->wValue == USB_DEVICE_TEST_MODE)
+				ptc = setup->wIndex >> 8;
+			else if (gadget_is_otg(&udc->gadget)) {
+				if (setup->bRequest ==
+				    USB_DEVICE_B_HNP_ENABLE)
+					udc->gadget.b_hnp_enable = 1;
+				else if (setup->bRequest ==
+					 USB_DEVICE_A_HNP_SUPPORT)
+					udc->gadget.a_hnp_support = 1;
+				else if (setup->bRequest ==
+					 USB_DEVICE_A_ALT_HNP_SUPPORT)
+					udc->gadget.a_alt_hnp_support = 1;
+			}
+			rc = 0;
+		} else
+			break;
+
+		if (rc == 0) {
+			if (ep0_prime_status(udc, EP_DIR_IN))
+				ep0stall(udc);
+		}
+		if (ptc) {
+			u32 tmp;
+
+			mdelay(10);
+			fsl_platform_set_test_mode(udc->pdata, ptc);
+			tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
+			fsl_writel(tmp, &dr_regs->portsc1);
+			printk(KERN_INFO "udc: switch to test mode 0x%x.\n", ptc);
+		}
+
+		return;
+	}
+
+	default:
+		break;
+	}
+
+	/* Requests handled by gadget */
+	if (wLength) {
+		/* Data phase from gadget, status phase from udc */
+		udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
+				?  USB_DIR_IN : USB_DIR_OUT;
+		spin_unlock(&udc->lock);
+		if (udc->driver->setup(&udc->gadget,
+				&udc->local_setup_buff) < 0) {
+			/* cancel status phase */
+			udc_reset_ep_queue(udc, 0);
+			ep0stall(udc);
+		}
+	} else {
+		/* No data phase, IN status from gadget */
+		udc->ep0_dir = USB_DIR_IN;
+		spin_unlock(&udc->lock);
+		if (udc->driver->setup(&udc->gadget,
+				&udc->local_setup_buff) < 0)
+			ep0stall(udc);
+	}
+	spin_lock(&udc->lock);
+}
+
+/* Process request for Data or Status phase of ep0
+ * prime status phase if needed */
+static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
+		struct fsl_req *req)
+{
+	if (udc->usb_state == USB_STATE_ADDRESS) {
+		/* Set the new address */
+		u32 new_address = (u32) udc->device_address;
+		fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
+				&dr_regs->deviceaddr);
+	}
+
+	done(ep0, req, 0);
+}
+
+/* Tripwire mechanism to ensure a setup packet payload is extracted without
+ * being corrupted by another incoming setup packet */
+static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
+{
+	u32 temp;
+	struct ep_queue_head *qh;
+	struct fsl_usb2_platform_data *pdata = udc->pdata;
+
+	qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
+
+	/* Clear bit in ENDPTSETUPSTAT */
+	temp = fsl_readl(&dr_regs->endptsetupstat);
+	fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
+
+	/* while a hazard exists when setup package arrives */
+	do {
+		/* Set Setup Tripwire */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
+
+		/* Copy the setup packet to local buffer */
+		if (pdata->le_setup_buf) {
+			u32 *p = (u32 *)buffer_ptr;
+			u32 *s = (u32 *)qh->setup_buffer;
+
+			/* Convert little endian setup buffer to CPU endian */
+			*p++ = le32_to_cpu(*s++);
+			*p = le32_to_cpu(*s);
+		} else {
+			memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+		}
+	} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
+
+	/* Clear Setup Tripwire */
+	temp = fsl_readl(&dr_regs->usbcmd);
+	fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
+}
+
+static void iram_process_ep_complete(struct fsl_req *curr_req,
+				     int cur_transfer)
+{
+	char *buf;
+	u32 len;
+	int in = ep_is_in(curr_req->ep);
+
+	if (in)
+		buf = (char *)udc_controller->iram_buffer_v[1];
+	else
+		buf = (char *)udc_controller->iram_buffer_v[0];
+
+	if (curr_req->cur->next_td_ptr == cpu_to_hc32(DTD_NEXT_TERMINATE)
+	    || (cur_transfer < g_iram_size)
+	    || (curr_req->req.length == curr_req->req.actual))
+		curr_req->last_one = 1;
+
+	if (curr_req->last_one) {
+		/* the last transfer */
+		if (!in) {
+			memcpy(curr_req->req.buf + curr_req->buffer_offset, buf,
+			       cur_transfer);
+		}
+		if (curr_req->tail->next_td_ptr !=
+				    cpu_to_hc32(DTD_NEXT_TERMINATE)) {
+			/* have next request,queue it */
+			struct fsl_req *next_req;
+			next_req =
+			    list_entry(curr_req->queue.next,
+				       struct fsl_req, queue);
+			if (in)
+				memcpy(buf, next_req->req.buf,
+				       min(g_iram_size, next_req->req.length));
+			update_qh(next_req);
+		}
+		curr_req->req.dma = curr_req->oridma;
+	} else {
+		/* queue next dtd */
+		/* because had next dtd, so should finish */
+		/* tranferring g_iram_size data */
+		curr_req->buffer_offset += g_iram_size;
+		/* pervious set stop bit,now clear it */
+		curr_req->cur->next_td_ptr &= ~cpu_to_hc32(DTD_NEXT_TERMINATE);
+		curr_req->cur = curr_req->cur->next_td_virt;
+		if (in) {
+			len =
+			    min(curr_req->req.length - curr_req->buffer_offset,
+				g_iram_size);
+			memcpy(buf, curr_req->req.buf + curr_req->buffer_offset,
+			       len);
+		} else {
+			memcpy(curr_req->req.buf + curr_req->buffer_offset -
+			       g_iram_size, buf, g_iram_size);
+		}
+		update_qh(curr_req);
+	}
+}
+
+/* process-ep_req(): free the completed Tds for this req */
+static int process_ep_req(struct fsl_udc *udc, int pipe,
+		struct fsl_req *curr_req)
+{
+	struct ep_td_struct *curr_td;
+	int	td_complete, actual, remaining_length, j, tmp;
+	int	status = 0;
+	int	errors = 0;
+	struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
+	int direction = pipe % 2;
+	int total = 0, real_len;
+
+	curr_td = curr_req->head;
+	td_complete = 0;
+	actual = curr_req->req.length;
+	real_len = curr_req->req.length;
+
+	for (j = 0; j < curr_req->dtd_count; j++) {
+		remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
+					& DTD_PACKET_SIZE)
+				>> DTD_LENGTH_BIT_POS;
+		if (NEED_IRAM(curr_req->ep)) {
+			if (real_len >= g_iram_size) {
+				actual = g_iram_size;
+				real_len -= g_iram_size;
+			} else {	/* the last packet */
+				actual = real_len;
+				curr_req->last_one = 1;
+			}
+		}
+		actual -= remaining_length;
+		total += actual;
+
+		errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK;
+		if (errors) {
+			if (errors & DTD_STATUS_HALTED) {
+				ERR("dTD error %08x QH=%d\n", errors, pipe);
+				/* Clear the errors and Halt condition */
+				tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
+				tmp &= ~errors;
+				curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
+				status = -EPIPE;
+				/* FIXME: continue with next queued TD? */
+
+				break;
+			}
+			if (errors & DTD_STATUS_DATA_BUFF_ERR) {
+				VDBG("Transfer overflow");
+				status = -EPROTO;
+				break;
+			} else if (errors & DTD_STATUS_TRANSACTION_ERR) {
+				VDBG("ISO error");
+				status = -EILSEQ;
+				break;
+			} else
+				ERR("Unknown error has occured (0x%x)!\r\n",
+					errors);
+
+		} else if (hc32_to_cpu(curr_td->size_ioc_sts)
+				& DTD_STATUS_ACTIVE) {
+			VDBG("Request not complete");
+			status = REQ_UNCOMPLETE;
+			return status;
+		} else if (remaining_length) {
+			if (direction) {
+				VDBG("Transmit dTD remaining length not zero");
+				status = -EPROTO;
+				break;
+			} else {
+				td_complete++;
+				break;
+			}
+		} else {
+			td_complete++;
+			VDBG("dTD transmitted successful ");
+		}
+		if (NEED_IRAM(curr_req->ep))
+			if (curr_td->
+			    next_td_ptr & cpu_to_hc32(DTD_NEXT_TERMINATE))
+				break;
+		if (j != curr_req->dtd_count - 1)
+			curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
+	}
+
+	if (status)
+		return status;
+	curr_req->req.actual = total;
+	if (NEED_IRAM(curr_req->ep))
+		iram_process_ep_complete(curr_req, actual);
+	return 0;
+}
+
+/* Process a DTD completion interrupt */
+static void dtd_complete_irq(struct fsl_udc *udc)
+{
+	u32 bit_pos;
+	int i, ep_num, direction, bit_mask, status;
+	struct fsl_ep *curr_ep;
+	struct fsl_req *curr_req, *temp_req;
+
+	/* Clear the bits in the register */
+	bit_pos = fsl_readl(&dr_regs->endptcomplete);
+	fsl_writel(bit_pos, &dr_regs->endptcomplete);
+
+	if (!bit_pos)
+		return;
+
+	for (i = 0; i < udc->max_ep * 2; i++) {
+		ep_num = i >> 1;
+		direction = i % 2;
+
+		bit_mask = 1 << (ep_num + 16 * direction);
+
+		if (!(bit_pos & bit_mask))
+			continue;
+
+		curr_ep = get_ep_by_pipe(udc, i);
+
+		/* If the ep is configured */
+		if (curr_ep->name == NULL) {
+			INFO("Invalid EP?");
+			continue;
+		}
+
+		/* process the req queue until an uncomplete request */
+		list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
+				queue) {
+			status = process_ep_req(udc, i, curr_req);
+
+			VDBG("status of process_ep_req= %d, ep = %d",
+					status, ep_num);
+			if (status == REQ_UNCOMPLETE)
+				break;
+			/* write back status to req */
+			curr_req->req.status = status;
+
+			if (ep_num == 0) {
+				ep0_req_complete(udc, curr_ep, curr_req);
+				break;
+			} else {
+				if (NEED_IRAM(curr_ep)) {
+					if (curr_req->last_one)
+						done(curr_ep, curr_req, status);
+					/* only check the 1th req */
+					break;
+				} else
+					done(curr_ep, curr_req, status);
+			}
+		}
+		dump_ep_queue(curr_ep);
+	}
+}
+
+/* Process a port change interrupt */
+static void port_change_irq(struct fsl_udc *udc)
+{
+	u32 speed;
+
+	if (udc->bus_reset)
+		udc->bus_reset = 0;
+
+	/* Bus resetting is finished */
+	if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
+		/* Get the speed */
+		speed = (fsl_readl(&dr_regs->portsc1)
+				& PORTSCX_PORT_SPEED_MASK);
+		switch (speed) {
+		case PORTSCX_PORT_SPEED_HIGH:
+			udc->gadget.speed = USB_SPEED_HIGH;
+			break;
+		case PORTSCX_PORT_SPEED_FULL:
+			udc->gadget.speed = USB_SPEED_FULL;
+			break;
+		case PORTSCX_PORT_SPEED_LOW:
+			udc->gadget.speed = USB_SPEED_LOW;
+			break;
+		default:
+			udc->gadget.speed = USB_SPEED_UNKNOWN;
+			break;
+		}
+	}
+
+	/* Update USB state */
+	if (!udc->resume_state)
+		udc->usb_state = USB_STATE_DEFAULT;
+}
+
+/* Process suspend interrupt */
+static void suspend_irq(struct fsl_udc *udc)
+{
+	pr_debug("%s\n", __func__);
+
+	udc->resume_state = udc->usb_state;
+	udc->usb_state = USB_STATE_SUSPENDED;
+
+	/* report suspend to the driver, serial.c does not support this */
+	if (udc->driver->suspend)
+		udc->driver->suspend(&udc->gadget);
+}
+
+/* Process Wake up interrupt */
+static void wake_up_irq(struct fsl_udc *udc)
+{
+	pr_debug("%s\n", __func__);
+
+	/* disable wake up irq */
+	dr_wake_up_enable(udc_controller, false);
+
+	udc->stopped = 0;
+}
+
+static void bus_resume(struct fsl_udc *udc)
+{
+	udc->usb_state = udc->resume_state;
+	udc->resume_state = 0;
+
+	/* report resume to the driver, serial.c does not support this */
+	if (udc->driver->resume)
+		udc->driver->resume(&udc->gadget);
+}
+
+/* Clear up all ep queues */
+static int reset_queues(struct fsl_udc *udc)
+{
+	u8 pipe;
+
+	for (pipe = 0; pipe < udc->max_pipes; pipe++)
+		udc_reset_ep_queue(udc, pipe);
+
+	/* report disconnect; the driver is already quiesced */
+	udc->driver->disconnect(&udc->gadget);
+
+	return 0;
+}
+
+/* Process reset interrupt */
+static void reset_irq(struct fsl_udc *udc)
+{
+	u32 temp;
+
+	/* Clear the device address */
+	temp = fsl_readl(&dr_regs->deviceaddr);
+	fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
+
+	udc->device_address = 0;
+
+	/* Clear usb state */
+	udc->resume_state = 0;
+	udc->ep0_dir = 0;
+	udc->remote_wakeup = 0;	/* default to 0 on reset */
+	udc->gadget.b_hnp_enable = 0;
+	udc->gadget.a_hnp_support = 0;
+	udc->gadget.a_alt_hnp_support = 0;
+
+	/* Clear all the setup token semaphores */
+	temp = fsl_readl(&dr_regs->endptsetupstat);
+	fsl_writel(temp, &dr_regs->endptsetupstat);
+
+	/* Clear all the endpoint complete status bits */
+	temp = fsl_readl(&dr_regs->endptcomplete);
+	fsl_writel(temp, &dr_regs->endptcomplete);
+
+	/* Write 1s to the flush register */
+	fsl_writel(0xffffffff, &dr_regs->endptflush);
+
+	/* Bus is reseting */
+	udc->bus_reset = 1;
+	/* Reset all the queues, include XD, dTD, EP queue
+	 * head and TR Queue */
+	reset_queues(udc);
+	udc->usb_state = USB_STATE_DEFAULT;
+}
+
+/* if wakup udc, return true; else return false*/
+bool try_wake_up_udc(struct fsl_udc *udc)
+{
+	u32 irq_src;
+
+	/* when udc is stopped, only handle wake up irq */
+	if (udc->stopped) {
+		if (!device_may_wakeup(&(udc->pdata->pdev->dev)))
+			return false;
+
+		dr_phy_low_power_mode(udc_controller, false);
+
+		/* check to see if wake up irq */
+		irq_src =  fsl_readl(&dr_regs->usbctrl);
+		if (irq_src & USB_CTRL_OTG_WUIR) {
+			wake_up_irq(udc);
+		} else {
+			dr_phy_low_power_mode(udc_controller, true);
+		}
+	}
+
+	if (!device_may_wakeup(udc_controller->gadget.dev.parent))
+		return true;
+
+	/* check if Vbus change irq */
+	irq_src = fsl_readl(&dr_regs->otgsc);
+	if (irq_src & OTGSC_B_SESSION_VALID_IRQ_STS) {
+		u32 tmp;
+		fsl_writel(irq_src, &dr_regs->otgsc);
+		tmp = fsl_readl(&dr_regs->usbcmd);
+		/* check BSV bit to see if fall or rise */
+		if (irq_src & OTGSC_B_SESSION_VALID) {
+			udc->stopped = 0;
+			fsl_writel(tmp | USB_CMD_RUN_STOP, &dr_regs->usbcmd);
+			printk(KERN_INFO "udc out low power mode\n");
+		} else {
+			printk(KERN_INFO "udc enter low power mode \n");
+			fsl_writel(tmp & ~USB_CMD_RUN_STOP, &dr_regs->usbcmd);
+			/* enable wake up */
+			dr_wake_up_enable(udc, true);
+			udc->stopped = 1;
+			/* close USB PHY clock */
+			dr_phy_low_power_mode(udc, true);
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/*
+ * USB device controller interrupt handler
+ */
+static irqreturn_t fsl_udc_irq(int irq, void *_udc)
+{
+	struct fsl_udc *udc = _udc;
+	u32 irq_src;
+	irqreturn_t status = IRQ_NONE;
+	unsigned long flags;
+
+	if (try_wake_up_udc(udc) == false)
+		return IRQ_NONE;
+
+	spin_lock_irqsave(&udc->lock, flags);
+	irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
+	/* Clear notification bits */
+	fsl_writel(irq_src, &dr_regs->usbsts);
+
+	/* VDBG("irq_src [0x%8x]", irq_src); */
+
+	/* Need to resume? */
+	if (udc->usb_state == USB_STATE_SUSPENDED)
+		if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
+			bus_resume(udc);
+
+	/* USB Interrupt */
+	if (irq_src & USB_STS_INT) {
+		VDBG("Packet int");
+		/* Setup package, we only support ep0 as control ep */
+		if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
+			tripwire_handler(udc, 0,
+					(u8 *) (&udc->local_setup_buff));
+			setup_received_irq(udc, &udc->local_setup_buff);
+			status = IRQ_HANDLED;
+		}
+
+		/* completion of dtd */
+		if (fsl_readl(&dr_regs->endptcomplete)) {
+			dtd_complete_irq(udc);
+			status = IRQ_HANDLED;
+		}
+	}
+
+	/* SOF (for ISO transfer) */
+	if (irq_src & USB_STS_SOF) {
+		status = IRQ_HANDLED;
+	}
+
+	/* Port Change */
+	if (irq_src & USB_STS_PORT_CHANGE) {
+		port_change_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	/* Reset Received */
+	if (irq_src & USB_STS_RESET) {
+		VDBG("reset int");
+		reset_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	/* Sleep Enable (Suspend) */
+	if (irq_src & USB_STS_SUSPEND) {
+		suspend_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
+		VDBG("Error IRQ %x ", irq_src);
+	}
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+	return status;
+}
+
+/*----------------------------------------------------------------*
+ * Hook to gadget drivers
+ * Called by initialization code of gadget drivers
+*----------------------------------------------------------------*/
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+	int retval = -ENODEV;
+	unsigned long flags = 0;
+	u32 portsc;
+
+	if (!udc_controller)
+		return -ENODEV;
+
+	if (!driver || (driver->speed != USB_SPEED_FULL
+				&& driver->speed != USB_SPEED_HIGH)
+			|| !driver->bind || !driver->disconnect
+			|| !driver->setup)
+		return -EINVAL;
+
+	if (udc_controller->driver)
+		return -EBUSY;
+
+	/* lock is needed but whether should use this lock or another */
+	spin_lock_irqsave(&udc_controller->lock, flags);
+
+	driver->driver.bus = 0;
+	/* hook up the driver */
+	udc_controller->driver = driver;
+	udc_controller->gadget.dev.driver = &driver->driver;
+	spin_unlock_irqrestore(&udc_controller->lock, flags);
+
+	if (udc_controller->pdata->usb_clock_for_pm)
+		udc_controller->pdata->usb_clock_for_pm(true);
+
+	portsc = fsl_readl(&dr_regs->portsc1);
+	portsc &= ~PORTSCX_PHY_LOW_POWER_SPD;
+	fsl_writel(portsc, &dr_regs->portsc1);
+
+	/* bind udc driver to gadget driver */
+	retval = driver->bind(&udc_controller->gadget);
+	if (retval) {
+		VDBG("bind to %s --> %d", driver->driver.name, retval);
+		udc_controller->gadget.dev.driver = 0;
+		udc_controller->driver = 0;
+		goto out;
+	}
+
+	if (udc_controller->transceiver) {
+		/* Suspend the controller until OTG enable it */
+		udc_controller->stopped = 1;
+		printk(KERN_INFO "Suspend udc for OTG auto detect\n");
+		dr_wake_up_enable(udc_controller, true);
+		dr_phy_low_power_mode(udc_controller, true);
+
+		/* export udc suspend/resume call to OTG */
+		udc_controller->gadget.dev.driver->suspend = (dev_sus)fsl_udc_suspend;
+		udc_controller->gadget.dev.driver->resume = (dev_res)fsl_udc_resume;
+
+		/* connect to bus through transceiver */
+		if (udc_controller->transceiver) {
+			retval = otg_set_peripheral(udc_controller->transceiver,
+						    &udc_controller->gadget);
+			if (retval < 0) {
+				ERR("can't bind to transceiver\n");
+				driver->unbind(&udc_controller->gadget);
+				udc_controller->gadget.dev.driver = 0;
+				udc_controller->driver = 0;
+				return retval;
+			}
+		}
+	} else {
+		/* Enable DR IRQ reg and Set usbcmd reg  Run bit */
+		dr_controller_run(udc_controller);
+		udc_controller->usb_state = USB_STATE_ATTACHED;
+		udc_controller->ep0_dir = 0;
+	}
+	printk(KERN_INFO "%s: bind to driver %s \n",
+			udc_controller->gadget.name, driver->driver.name);
+
+out:
+	if (retval)
+		printk(KERN_DEBUG "retval %d \n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+/* Disconnect from gadget driver */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+	struct fsl_ep *loop_ep;
+	unsigned long flags;
+	u32 portsc;
+
+	if (!udc_controller)
+		return -ENODEV;
+
+	if (!driver || driver != udc_controller->driver || !driver->unbind)
+		return -EINVAL;
+
+	if (udc_controller->transceiver)
+		(void)otg_set_peripheral(udc_controller->transceiver, 0);
+
+	/* open phy clock for following operation */
+	dr_phy_low_power_mode(udc_controller, false);
+
+	/* stop DR, disable intr */
+	dr_controller_stop(udc_controller);
+
+	/* in fact, no needed */
+	udc_controller->usb_state = USB_STATE_ATTACHED;
+	udc_controller->ep0_dir = 0;
+
+	/* stand operation */
+	spin_lock_irqsave(&udc_controller->lock, flags);
+	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+	nuke(&udc_controller->eps[0], -ESHUTDOWN);
+	list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
+			ep.ep_list)
+		nuke(loop_ep, -ESHUTDOWN);
+	spin_unlock_irqrestore(&udc_controller->lock, flags);
+
+	/* disconnect gadget before unbinding */
+	driver->disconnect(&udc_controller->gadget);
+
+	/* unbind gadget and unhook driver. */
+	driver->unbind(&udc_controller->gadget);
+	udc_controller->gadget.dev.driver = 0;
+	udc_controller->driver = 0;
+
+	dr_wake_up_enable(udc_controller, false);
+
+	portsc = fsl_readl(&dr_regs->portsc1);
+	portsc |= PORTSCX_PHY_LOW_POWER_SPD;
+	fsl_writel(portsc, &dr_regs->portsc1);
+
+	if (udc_controller->pdata->usb_clock_for_pm)
+		udc_controller->pdata->usb_clock_for_pm(false);
+
+	printk(KERN_INFO "unregistered gadget driver '%s'\r\n",
+	       driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/*-------------------------------------------------------------------------
+		PROC File System Support
+-------------------------------------------------------------------------*/
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+
+#include <linux/seq_file.h>
+
+static const char proc_filename[] = "driver/fsl_usb2_udc";
+
+static int fsl_proc_read(char *page, char **start, off_t off, int count,
+		int *eof, void *_dev)
+{
+	char *buf = page;
+	char *next = buf;
+	unsigned size = count;
+	unsigned long flags;
+	int t, i;
+	u32 tmp_reg;
+	struct fsl_ep *ep = NULL;
+	struct fsl_req *req;
+	struct fsl_usb2_platform_data *pdata;
+
+	struct fsl_udc *udc = udc_controller;
+	pdata = udc->pdata;
+	if (off != 0)
+		return 0;
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* ------basic driver infomation ---- */
+	t = scnprintf(next, size,
+			DRIVER_DESC "\n"
+			"%s version: %s\n"
+			"Gadget driver: %s\n\n",
+			driver_name, DRIVER_VERSION,
+			udc->driver ? udc->driver->driver.name : "(none)");
+	size -= t;
+	next += t;
+
+	/* ------ DR Registers ----- */
+	tmp_reg = fsl_readl(&dr_regs->usbcmd);
+	t = scnprintf(next, size,
+			"USBCMD reg:\n"
+			"SetupTW: %d\n"
+			"Run/Stop: %s\n\n",
+			(tmp_reg & USB_CMD_SUTW) ? 1 : 0,
+			(tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbsts);
+	t = scnprintf(next, size,
+			"USB Status Reg:\n"
+			"Dr Suspend: %d" "Reset Received: %d" "System Error: %s"
+			"USB Error Interrupt: %s\n\n",
+			(tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
+			(tmp_reg & USB_STS_RESET) ? 1 : 0,
+			(tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
+			(tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbintr);
+	t = scnprintf(next, size,
+			"USB Intrrupt Enable Reg:\n"
+			"Sleep Enable: %d" "SOF Received Enable: %d"
+			"Reset Enable: %d\n"
+			"System Error Enable: %d"
+			"Port Change Dectected Enable: %d\n"
+			"USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n",
+			(tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
+			(tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->frindex);
+	t = scnprintf(next, size,
+			"USB Frame Index Reg:" "Frame Number is 0x%x\n\n",
+			(tmp_reg & USB_FRINDEX_MASKS));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->deviceaddr);
+	t = scnprintf(next, size,
+			"USB Device Address Reg:" "Device Addr is 0x%x\n\n",
+			(tmp_reg & USB_DEVICE_ADDRESS_MASK));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
+	t = scnprintf(next, size,
+			"USB Endpoint List Address Reg:"
+			"Device Addr is 0x%x\n\n",
+			(tmp_reg & USB_EP_LIST_ADDRESS_MASK));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->portsc1);
+	t = scnprintf(next, size,
+		"USB Port Status&Control Reg:\n"
+		"Port Transceiver Type : %s" "Port Speed: %s \n"
+		"PHY Low Power Suspend: %s" "Port Reset: %s"
+		"Port Suspend Mode: %s \n" "Over-current Change: %s"
+		"Port Enable/Disable Change: %s\n"
+		"Port Enabled/Disabled: %s"
+		"Current Connect Status: %s\n\n", ({
+			char *s;
+			switch (tmp_reg & PORTSCX_PTS_FSLS) {
+			case PORTSCX_PTS_UTMI:
+				s = "UTMI"; break;
+			case PORTSCX_PTS_ULPI:
+				s = "ULPI "; break;
+			case PORTSCX_PTS_FSLS:
+				s = "FS/LS Serial"; break;
+			default:
+				s = "None"; break;
+			}
+			s; }), ({
+			char *s;
+			switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
+			case PORTSCX_PORT_SPEED_FULL:
+				s = "Full Speed"; break;
+			case PORTSCX_PORT_SPEED_LOW:
+				s = "Low Speed"; break;
+			case PORTSCX_PORT_SPEED_HIGH:
+				s = "High Speed"; break;
+			default:
+				s = "Undefined"; break;
+			}
+			s;
+		}),
+		(tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
+		"Normal PHY mode" : "Low power mode",
+		(tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
+		"Not in Reset",
+		(tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
+		(tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
+		"No",
+		(tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
+		"Not change",
+		(tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
+		"Not correct",
+		(tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
+		"Attached" : "Not-Att");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbmode);
+	t = scnprintf(next, size,
+			"USB Mode Reg:" "Controller Mode is : %s\n\n", ({
+				char *s;
+				switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
+				case USB_MODE_CTRL_MODE_IDLE:
+					s = "Idle"; break;
+				case USB_MODE_CTRL_MODE_DEVICE:
+					s = "Device Controller"; break;
+				case USB_MODE_CTRL_MODE_HOST:
+					s = "Host Controller"; break;
+				default:
+					s = "None"; break;
+				}
+				s;
+			}));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
+	t = scnprintf(next, size,
+			"Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
+			(tmp_reg & EP_SETUP_STATUS_MASK));
+	size -= t;
+	next += t;
+
+	for (i = 0; i < udc->max_ep / 2; i++) {
+		tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
+		t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
+				i, tmp_reg);
+		size -= t;
+		next += t;
+	}
+	tmp_reg = fsl_readl(&dr_regs->endpointprime);
+	t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	if (pdata->have_sysif_regs) {
+		tmp_reg = usb_sys_regs->snoop1;
+		t = scnprintf(next, size, "\nSnoop1 Reg = [0x%x]\n\n", tmp_reg);
+		size -= t;
+		next += t;
+
+		tmp_reg = usb_sys_regs->control;
+		t = scnprintf(next, size, "General Control Reg = [0x%x]\n\n",
+				tmp_reg);
+		size -= t;
+		next += t;
+	}
+
+	/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
+	ep = &udc->eps[0];
+	t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
+			ep->ep.name, ep_maxpacket(ep), ep_index(ep));
+	size -= t;
+	next += t;
+
+	if (list_empty(&ep->queue)) {
+		t = scnprintf(next, size, "its req queue is empty\n\n");
+		size -= t;
+		next += t;
+	} else {
+		list_for_each_entry(req, &ep->queue, queue) {
+			t = scnprintf(next, size,
+				"req %p actual 0x%x length 0x%x  buf %p\n",
+				&req->req, req->req.actual,
+				req->req.length, req->req.buf);
+			size -= t;
+			next += t;
+		}
+	}
+	/* other gadget->eplist ep */
+	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
+		if (ep->desc) {
+			t = scnprintf(next, size,
+					"\nFor %s Maxpkt is 0x%x "
+					"index is 0x%x\n",
+					ep->ep.name, ep_maxpacket(ep),
+					ep_index(ep));
+			size -= t;
+			next += t;
+
+			if (list_empty(&ep->queue)) {
+				t = scnprintf(next, size,
+						"its req queue is empty\n\n");
+				size -= t;
+				next += t;
+			} else {
+				list_for_each_entry(req, &ep->queue, queue) {
+					t = scnprintf(next, size,
+						"req %p actual 0x%x length"
+						"0x%x  buf %p\n",
+						&req->req, req->req.actual,
+						req->req.length, req->req.buf);
+					size -= t;
+					next += t;
+					} /* end for each_entry of ep req */
+				}	/* end for else */
+			}	/* end for if(ep->queue) */
+		}		/* end (ep->desc) */
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	*eof = 1;
+	return count - size;
+}
+
+#define create_proc_file()	create_proc_read_entry(proc_filename, \
+				0, NULL, fsl_proc_read, NULL)
+
+#define remove_proc_file()	remove_proc_entry(proc_filename, NULL)
+
+#else				/* !CONFIG_USB_GADGET_DEBUG_FILES */
+
+#define create_proc_file()	do {} while (0)
+#define remove_proc_file()	do {} while (0)
+
+#endif				/* CONFIG_USB_GADGET_DEBUG_FILES */
+
+/*-------------------------------------------------------------------------*/
+
+/* Release udc structures */
+static void fsl_udc_release(struct device *dev)
+{
+	complete(udc_controller->done);
+	dma_free_coherent(dev, udc_controller->ep_qh_size,
+			udc_controller->ep_qh, udc_controller->ep_qh_dma);
+	kfree(udc_controller);
+}
+
+/******************************************************************
+	Internal structure setup functions
+*******************************************************************/
+/*------------------------------------------------------------------
+ * init resource for globle controller
+ * Return the udc handle on success or NULL on failure
+ ------------------------------------------------------------------*/
+static int __init struct_udc_setup(struct fsl_udc *udc,
+		struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata;
+	size_t size;
+
+	pdata = pdev->dev.platform_data;
+	udc->phy_mode = pdata->phy_mode;
+
+	udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
+	if (!udc->eps) {
+		ERR("malloc fsl_ep failed\n");
+		return -1;
+	}
+
+	/* initialized QHs, take care of alignment */
+	size = udc->max_ep * sizeof(struct ep_queue_head);
+	if (size < QH_ALIGNMENT)
+		size = QH_ALIGNMENT;
+	else if ((size % QH_ALIGNMENT) != 0) {
+		size += QH_ALIGNMENT + 1;
+		size &= ~(QH_ALIGNMENT - 1);
+	}
+	udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
+					&udc->ep_qh_dma, GFP_KERNEL);
+	if (!udc->ep_qh) {
+		ERR("malloc QHs for udc failed\n");
+		kfree(udc->eps);
+		return -1;
+	}
+
+	udc->ep_qh_size = size;
+
+	/* Initialize ep0 status request structure */
+	/* FIXME: fsl_alloc_request() ignores ep argument */
+	udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
+			struct fsl_req, req);
+	/* allocate a small amount of memory to get valid address */
+	udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
+	udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
+	/* Initialize ep0 data request structure */
+	udc->data_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
+			struct fsl_req, req);
+	udc->data_req->req.buf = kmalloc(8, GFP_KERNEL);
+	udc->data_req->req.dma = virt_to_phys(udc->data_req->req.buf);
+
+	udc->resume_state = USB_STATE_NOTATTACHED;
+	udc->usb_state = USB_STATE_POWERED;
+	udc->ep0_dir = 0;
+	udc->remote_wakeup = 0;	/* default to 0 on reset */
+	spin_lock_init(&udc->lock);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------
+ * Setup the fsl_ep struct for eps
+ * Link fsl_ep->ep to gadget->ep_list
+ * ep0out is not used so do nothing here
+ * ep0in should be taken care
+ *--------------------------------------------------------------*/
+static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
+		char *name, int link)
+{
+	struct fsl_ep *ep = &udc->eps[index];
+
+	ep->udc = udc;
+	strcpy(ep->name, name);
+	ep->ep.name = ep->name;
+
+	ep->ep.ops = &fsl_ep_ops;
+	ep->stopped = 0;
+
+	/* for ep0: maxP defined in desc
+	 * for other eps, maxP is set by epautoconfig() called by gadget layer
+	 */
+	ep->ep.maxpacket = (unsigned short) ~0;
+
+	/* the queue lists any req for this ep */
+	INIT_LIST_HEAD(&ep->queue);
+
+	/* gagdet.ep_list used for ep_autoconfig so no ep0 */
+	if (link)
+		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	ep->gadget = &udc->gadget;
+	ep->qh = &udc->ep_qh[index];
+
+	return 0;
+}
+
+/* Driver probe function
+ * all intialization operations implemented here except enabling usb_intr reg
+ * board setup should have been done in the platform code
+ */
+static int __init fsl_udc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	int ret = -ENODEV;
+	unsigned int i;
+	u32 dccparams;
+
+	udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
+	if (udc_controller == NULL) {
+		ERR("malloc udc failed\n");
+		return -ENOMEM;
+	}
+	udc_controller->pdata = pdata;
+
+#ifdef CONFIG_USB_OTG
+	/* Memory and interrupt resources will be passed from OTG */
+	udc_controller->transceiver = otg_get_transceiver();
+	if (!udc_controller->transceiver) {
+		printk(KERN_ERR "Can't find OTG driver!\n");
+		ret = -ENODEV;
+		goto err1a;
+	}
+#endif
+
+	if ((pdev->dev.parent) &&
+		(to_platform_device(pdev->dev.parent)->resource)) {
+		pdev->resource =
+			to_platform_device(pdev->dev.parent)->resource;
+		pdev->num_resources =
+			to_platform_device(pdev->dev.parent)->num_resources;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENXIO;
+		goto err1a;
+	}
+
+#ifndef CONFIG_USB_OTG
+	if (!request_mem_region(res->start, resource_size(res),
+				driver_name)) {
+		ERR("request mem region for %s failed \n", pdev->name);
+		ret = -EBUSY;
+		goto err1a;
+	}
+#endif
+
+	dr_regs = ioremap(res->start, resource_size(res));
+	if (!dr_regs) {
+		ret = -ENOMEM;
+		goto err1;
+	}
+	pdata->regs = (void *)dr_regs;
+	/*
+	 * do platform specific init: check the clock, grab/config pins, etc.
+	 */
+	if (pdata->platform_init && pdata->platform_init(pdev)) {
+		ret = -ENODEV;
+		goto err2a;
+	}
+
+	/* Due to mx35/mx25's phy's bug */
+	reset_phy();
+
+	if (pdata->have_sysif_regs)
+		usb_sys_regs = (struct usb_sys_interface *)
+				((u32)dr_regs + USB_DR_SYS_OFFSET);
+
+	/* Read Device Controller Capability Parameters register */
+	dccparams = fsl_readl(&dr_regs->dccparams);
+	if (!(dccparams & DCCPARAMS_DC)) {
+		ERR("This SOC doesn't support device role\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+	/* Get max device endpoints */
+	/* DEN is bidirectional ep number, max_ep doubles the number */
+	udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
+
+	udc_controller->irq = platform_get_irq(pdev, 0);
+	if (!udc_controller->irq) {
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
+			driver_name, udc_controller);
+	if (ret != 0) {
+		ERR("cannot request irq %d err %d \n",
+				udc_controller->irq, ret);
+		goto err2;
+	}
+
+	/* Initialize the udc structure including QH member and other member */
+	if (struct_udc_setup(udc_controller, pdev)) {
+		ERR("Can't initialize udc data structure\n");
+		ret = -ENOMEM;
+		goto err3;
+	}
+
+	if (!udc_controller->transceiver) {
+		/* initialize usb hw reg except for regs for EP,
+		 * leave usbintr reg untouched */
+		dr_controller_setup(udc_controller);
+	}
+
+	/* Setup gadget structure */
+	udc_controller->gadget.ops = &fsl_gadget_ops;
+	udc_controller->gadget.is_dualspeed = 1;
+	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
+	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
+	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+	udc_controller->gadget.name = driver_name;
+
+	/* Setup gadget.dev and register with kernel */
+	dev_set_name(&udc_controller->gadget.dev, "gadget");
+	udc_controller->gadget.dev.release = fsl_udc_release;
+	udc_controller->gadget.dev.parent = &pdev->dev;
+	ret = device_register(&udc_controller->gadget.dev);
+	if (ret < 0)
+		goto err3;
+
+	if (udc_controller->transceiver) {
+		udc_controller->gadget.is_otg = 1;
+		/* now didn't support lpm in OTG mode*/
+		device_set_wakeup_capable(&pdev->dev, 0);
+	}
+
+	/* setup QH and epctrl for ep0 */
+	ep0_setup(udc_controller);
+
+	/* setup udc->eps[] for ep0 */
+	struct_ep_setup(udc_controller, 0, "ep0", 0);
+	/* for ep0: the desc defined here;
+	 * for other eps, gadget layer called ep_enable with defined desc
+	 */
+	udc_controller->eps[0].desc = &fsl_ep0_desc;
+	udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
+
+	/* setup the udc->eps[] for non-control endpoints and link
+	 * to gadget.ep_list */
+	for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
+		char name[14];
+
+		sprintf(name, "ep%dout", i);
+		struct_ep_setup(udc_controller, i * 2, name, 1);
+		sprintf(name, "ep%din", i);
+		struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
+	}
+
+	/* use dma_pool for TD management */
+	udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
+			sizeof(struct ep_td_struct),
+			DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
+	if (udc_controller->td_pool == NULL) {
+		ret = -ENOMEM;
+		goto err4;
+	}
+	if (g_iram_size) {
+		g_iram_addr = iram_alloc(USB_IRAM_SIZE, &g_iram_base);
+		for (i = 0; i < IRAM_PPH_NTD; i++) {
+			udc_controller->iram_buffer[i] =
+				g_iram_base + i * g_iram_size;
+			udc_controller->iram_buffer_v[i] =
+				g_iram_addr + i * g_iram_size;
+		}
+	}
+#ifdef POSTPONE_FREE_LAST_DTD
+	last_free_td = NULL;
+#endif
+#ifndef CONFIG_USB_OTG
+	/* disable all INTR */
+	fsl_writel(0, &dr_regs->usbintr);
+
+	dr_wake_up_enable(udc_controller, false);
+	udc_controller->stopped = 1;
+
+#if !(defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+{
+	u32 portsc;
+	portsc = fsl_readl(&dr_regs->portsc1);
+	portsc |= PORTSCX_PHY_LOW_POWER_SPD;
+	fsl_writel(portsc, &dr_regs->portsc1);
+}
+#endif
+	if (udc_controller->pdata->usb_clock_for_pm)
+		udc_controller->pdata->usb_clock_for_pm(false);
+#endif
+	create_proc_file();
+	return 0;
+
+err4:
+	device_unregister(&udc_controller->gadget.dev);
+err3:
+	free_irq(udc_controller->irq, udc_controller);
+err2:
+	if (pdata->platform_uninit)
+		pdata->platform_uninit(pdata);
+err2a:
+	iounmap((u8 __iomem *)dr_regs);
+err1:
+	if (!udc_controller->transceiver)
+		release_mem_region(res->start, resource_size(res));
+err1a:
+	kfree(udc_controller);
+	udc_controller = NULL;
+	return ret;
+}
+
+/* Driver removal function
+ * Free resources and finish pending transactions
+ */
+static int __exit fsl_udc_remove(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	DECLARE_COMPLETION(done);
+
+	if (!udc_controller)
+		return -ENODEV;
+	udc_controller->done = &done;
+	/* open USB PHY clock */
+	dr_phy_low_power_mode(udc_controller, false);
+
+	/* DR has been stopped in usb_gadget_unregister_driver() */
+	remove_proc_file();
+
+	/* Free allocated memory */
+	if (g_iram_size)
+		iram_free(g_iram_base, IRAM_PPH_NTD * g_iram_size);
+	kfree(udc_controller->status_req->req.buf);
+	kfree(udc_controller->status_req);
+	kfree(udc_controller->data_req->req.buf);
+	kfree(udc_controller->data_req);
+	kfree(udc_controller->eps);
+#ifdef POSTPONE_FREE_LAST_DTD
+	if (last_free_td != NULL)
+		dma_pool_free(udc_controller->td_pool, last_free_td,
+				last_free_td->td_dma);
+#endif
+	dma_pool_destroy(udc_controller->td_pool);
+	free_irq(udc_controller->irq, udc_controller);
+	iounmap((u8 __iomem *)dr_regs);
+
+#ifndef CONFIG_USB_OTG
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, resource_size(res));
+#endif
+
+	device_unregister(&udc_controller->gadget.dev);
+	/* free udc --wait for the release() finished */
+	wait_for_completion(&done);
+
+	/*
+	 * do platform specific un-initialization:
+	 * release iomux pins, etc.
+	 */
+	if (pdata->platform_uninit)
+		pdata->platform_uninit(pdata);
+
+	return 0;
+}
+
+static int udc_suspend(struct fsl_udc *udc)
+{
+	u32 mode, usbcmd;
+
+	/* open clock for register access */
+	if (udc_controller->pdata->usb_clock_for_pm)
+		udc_controller->pdata->usb_clock_for_pm(true);
+
+	mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
+	usbcmd = fsl_readl(&dr_regs->usbcmd);
+
+	pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
+
+	/*
+	 * If the controller is already stopped, then this must be a
+	 * PM suspend.  Remember this fact, so that we will leave the
+	 * controller stopped at PM resume time.
+	 */
+	if (udc->stopped) {
+		pr_debug("gadget already stopped, leaving early\n");
+		udc->already_stopped = 1;
+		goto out;
+	}
+
+	if (mode != USB_MODE_CTRL_MODE_DEVICE) {
+		pr_debug("gadget not in device mode, leaving early\n");
+		goto out;
+	}
+
+	udc->stopped = 1;
+	/* if the suspend is not for switch to host in otg mode */
+	if ((!(udc->gadget.is_otg)) ||
+			(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+		dr_wake_up_enable(udc, true);
+		dr_phy_low_power_mode(udc, true);
+	}
+
+	/* stop the controller */
+	usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
+	fsl_writel(usbcmd, &dr_regs->usbcmd);
+
+	printk(KERN_INFO "USB Gadget suspended\n");
+out:
+	if (udc_controller->pdata->usb_clock_for_pm)
+		udc_controller->pdata->usb_clock_for_pm(false);
+	return 0;
+}
+
+/*-----------------------------------------------------------------
+ * Modify Power management attributes
+ * Used by OTG statemachine to disable gadget temporarily
+ -----------------------------------------------------------------*/
+static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	if (((!(udc_controller->gadget.is_otg)) ||
+			(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) &&
+			(udc_controller->usb_state > USB_STATE_POWERED) &&
+			(udc_controller->usb_state < USB_STATE_SUSPENDED))
+		return -EBUSY;
+
+	return udc_suspend(udc_controller);
+}
+
+/*-----------------------------------------------------------------
+ * Invoked on USB resume. May be called in_interrupt.
+ * Here we start the DR controller and enable the irq
+ *-----------------------------------------------------------------*/
+static int fsl_udc_resume(struct platform_device *pdev)
+{
+	pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
+		 udc_controller->stopped, udc_controller->already_stopped);
+
+	/*
+	 * If the controller was stopped at suspend time, then
+	 * don't resume it now.
+	 */
+	if (udc_controller->already_stopped) {
+		udc_controller->already_stopped = 0;
+		pr_debug("gadget was already stopped, leaving early\n");
+		return 0;
+	}
+
+	/* Enable DR irq reg and set controller Run */
+	if (udc_controller->stopped) {
+		dr_wake_up_enable(udc_controller, false);
+		dr_phy_low_power_mode(udc_controller, false);
+		mdelay(1);
+
+		dr_controller_setup(udc_controller);
+		dr_controller_run(udc_controller);
+	}
+	udc_controller->usb_state = USB_STATE_ATTACHED;
+	udc_controller->ep0_dir = 0;
+
+	printk(KERN_INFO "USB Gadget resumed\n");
+	return 0;
+}
+
+/*-------------------------------------------------------------------------
+	Register entry point for the peripheral controller driver
+--------------------------------------------------------------------------*/
+
+static struct platform_driver udc_driver = {
+	.remove  = __exit_p(fsl_udc_remove),
+	/* these suspend and resume are not usb suspend and resume */
+	.suspend = fsl_udc_suspend,
+	.resume  = fsl_udc_resume,
+	.probe = fsl_udc_probe,
+	.driver  = {
+		.name = driver_name,
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init udc_init(void)
+{
+	printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
+	return platform_driver_register(&udc_driver);
+}
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	fs_initcall(udc_init);
+#else
+	module_init(udc_init);
+#endif
+static void __exit udc_exit(void)
+{
+	platform_driver_unregister(&udc_driver);
+	printk(KERN_INFO "%s unregistered \n", driver_desc);
+}
+
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h
new file mode 100644
index 000000000000..cb216745d340
--- /dev/null
+++ b/drivers/usb/gadget/arcotg_udc.h
@@ -0,0 +1,708 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file arcotg_udc.h
+ * @brief Freescale USB device/endpoint management registers
+ * @ingroup USB
+ */
+
+#ifndef __ARCOTG_UDC_H
+#define __ARCOTG_UDC_H
+
+#include <mach/hardware.h>
+
+#define TRUE 1
+#define FALSE 0
+
+#define MSC_BULK_CB_WRAP_LEN 31
+#ifdef CONFIG_ARCH_MXC
+#define USE_MSC_WR(len) (((cpu_is_mx37_rev(CHIP_REV_1_0) == 1) ||\
+	(cpu_is_mx51_rev(CHIP_REV_2_0) < 0)) && ((len) == MSC_BULK_CB_WRAP_LEN))
+#else
+#define USE_MSC_WR(len) false
+#endif
+
+/* Iram patch */
+#ifdef CONFIG_USB_STATIC_IRAM_PPH
+/* size of 1 qTD's buffer,one is for BULK IN and other is BULK OUT */
+#define IRAM_TD_PPH_SIZE	(USB_IRAM_SIZE / 2)
+#define IRAM_PPH_NTD	2	/* number of TDs in IRAM  */
+#else
+#define IRAM_TD_PPH_SIZE	0
+#define IRAM_PPH_NTD	0
+#endif
+
+#define NEED_IRAM(ep) ((g_iram_size) && \
+	((ep)->desc->bmAttributes == USB_ENDPOINT_XFER_BULK))
+
+#ifdef CONFIG_ARCH_MX5
+#define POSTPONE_FREE_LAST_DTD
+#else
+#undef POSTPONE_FREE_LAST_DTD
+#endif
+
+/* ### define USB registers here
+ */
+#define USB_MAX_ENDPOINTS		8
+#define USB_MAX_PIPES			(USB_MAX_ENDPOINTS*2)
+#define USB_MAX_CTRL_PAYLOAD		64
+#define	USB_DR_SYS_OFFSET		0x400
+
+#define	USB_DR_OFFSET	0x3100
+
+struct usb_dr_device {
+	/* Capability register */
+	u32 id;
+	u32 res1[35];
+	u32 sbuscfg;		/* sbuscfg ahb burst */
+	u32 res11[27];
+	u16 caplength;		/* Capability Register Length */
+	u16 hciversion;		/* Host Controller Interface Version */
+	u32 hcsparams;		/* Host Controller Structual Parameters */
+	u32 hccparams;		/* Host Controller Capability Parameters */
+	u32 res2[5];
+	u32 dciversion;		/* Device Controller Interface Version */
+	u32 dccparams;		/* Device Controller Capability Parameters */
+	u32 res3[6];
+	/* Operation register */
+	u32 usbcmd;		/* USB Command Register */
+	u32 usbsts;		/* USB Status Register */
+	u32 usbintr;		/* USB Interrupt Enable Register */
+	u32 frindex;		/* Frame Index Register */
+	u32 res4;
+	u32 deviceaddr;		/* Device Address */
+	u32 endpointlistaddr;	/* Endpoint List Address Register */
+	u32 res5;
+	u32 burstsize;		/* Master Interface Data Burst Size Register */
+	u32 txttfilltuning;	/* Transmit FIFO Tuning Controls Register */
+	u32 res6[6];
+	u32 configflag;		/* Configure Flag Register */
+	u32 portsc1;		/* Port 1 Status and Control Register */
+	u32 res7[7];
+	u32 otgsc;		/* On-The-Go Status and Control */
+	u32 usbmode;		/* USB Mode Register */
+	u32 endptsetupstat;	/* Endpoint Setup Status Register */
+	u32 endpointprime;	/* Endpoint Initialization Register */
+	u32 endptflush;		/* Endpoint Flush Register */
+	u32 endptstatus;	/* Endpoint Status Register */
+	u32 endptcomplete;	/* Endpoint Complete Register */
+	u32 endptctrl[8 * 2];	/* Endpoint Control Registers */
+	u32 res8[256];
+#ifdef CONFIG_ARCH_MX5
+	u32 res9[128];		/* i.MX51 start from 0x800 */
+#endif
+	u32 usbctrl;
+	u32 otgmirror;
+	u32 phyctrl0;
+	u32 phyctrl1;
+	u32 ctrl1;
+	u32 uh2ctrl;
+};
+
+ /* non-EHCI USB system interface registers (Big Endian) */
+struct usb_sys_interface {
+	u32 snoop1;
+	u32 snoop2;
+	u32 age_cnt_thresh;	/* Age Count Threshold Register */
+	u32 pri_ctrl;		/* Priority Control Register */
+	u32 si_ctrl;		/* System Interface Control Register */
+	u8 res[236];
+	u32 control;		/* General Purpose Control Register */
+};
+
+/* ep0 transfer state */
+#define WAIT_FOR_SETUP          0
+#define DATA_STATE_XMIT         1
+#define DATA_STATE_NEED_ZLP     2
+#define WAIT_FOR_OUT_STATUS     3
+#define DATA_STATE_RECV         4
+
+/* Device Controller Capability Parameter register */
+#define DCCPARAMS_DC				0x00000080
+#define DCCPARAMS_DEN_MASK			0x0000001f
+
+/* Frame Index Register Bit Masks */
+#define	USB_FRINDEX_MASKS			(0x3fff)
+/* USB CMD  Register Bit Masks */
+#define  USB_CMD_RUN_STOP                     (0x00000001)
+#define  USB_CMD_CTRL_RESET                   (0x00000002)
+#define  USB_CMD_PERIODIC_SCHEDULE_EN         (0x00000010)
+#define  USB_CMD_ASYNC_SCHEDULE_EN            (0x00000020)
+#define  USB_CMD_INT_AA_DOORBELL              (0x00000040)
+#define  USB_CMD_ASP                          (0x00000300)
+#define  USB_CMD_ASYNC_SCH_PARK_EN            (0x00000800)
+#define  USB_CMD_SUTW                         (0x00002000)
+#define  USB_CMD_ATDTW                        (0x00004000)
+#define  USB_CMD_ITC                          (0x00FF0000)
+
+/* bit 15,3,2 are frame list size */
+#define  USB_CMD_FRAME_SIZE_1024              (0x00000000)
+#define  USB_CMD_FRAME_SIZE_512               (0x00000004)
+#define  USB_CMD_FRAME_SIZE_256               (0x00000008)
+#define  USB_CMD_FRAME_SIZE_128               (0x0000000C)
+#define  USB_CMD_FRAME_SIZE_64                (0x00008000)
+#define  USB_CMD_FRAME_SIZE_32                (0x00008004)
+#define  USB_CMD_FRAME_SIZE_16                (0x00008008)
+#define  USB_CMD_FRAME_SIZE_8                 (0x0000800C)
+
+/* bit 9-8 are async schedule park mode count */
+#define  USB_CMD_ASP_00                       (0x00000000)
+#define  USB_CMD_ASP_01                       (0x00000100)
+#define  USB_CMD_ASP_10                       (0x00000200)
+#define  USB_CMD_ASP_11                       (0x00000300)
+#define  USB_CMD_ASP_BIT_POS                  (8)
+
+/* bit 23-16 are interrupt threshold control */
+#define  USB_CMD_ITC_NO_THRESHOLD             (0x00000000)
+#define  USB_CMD_ITC_1_MICRO_FRM              (0x00010000)
+#define  USB_CMD_ITC_2_MICRO_FRM              (0x00020000)
+#define  USB_CMD_ITC_4_MICRO_FRM              (0x00040000)
+#define  USB_CMD_ITC_8_MICRO_FRM              (0x00080000)
+#define  USB_CMD_ITC_16_MICRO_FRM             (0x00100000)
+#define  USB_CMD_ITC_32_MICRO_FRM             (0x00200000)
+#define  USB_CMD_ITC_64_MICRO_FRM             (0x00400000)
+#define  USB_CMD_ITC_BIT_POS                  (16)
+
+/* USB STS Register Bit Masks */
+#define  USB_STS_INT                          (0x00000001)
+#define  USB_STS_ERR                          (0x00000002)
+#define  USB_STS_PORT_CHANGE                  (0x00000004)
+#define  USB_STS_FRM_LST_ROLL                 (0x00000008)
+#define  USB_STS_SYS_ERR                      (0x00000010)
+#define  USB_STS_IAA                          (0x00000020)
+#define  USB_STS_RESET                        (0x00000040)
+#define  USB_STS_SOF                          (0x00000080)
+#define  USB_STS_SUSPEND                      (0x00000100)
+#define  USB_STS_HC_HALTED                    (0x00001000)
+#define  USB_STS_RCL                          (0x00002000)
+#define  USB_STS_PERIODIC_SCHEDULE            (0x00004000)
+#define  USB_STS_ASYNC_SCHEDULE               (0x00008000)
+
+/* USB INTR Register Bit Masks */
+#define  USB_INTR_INT_EN                      (0x00000001)
+#define  USB_INTR_ERR_INT_EN                  (0x00000002)
+#define  USB_INTR_PTC_DETECT_EN               (0x00000004)
+#define  USB_INTR_FRM_LST_ROLL_EN             (0x00000008)
+#define  USB_INTR_SYS_ERR_EN                  (0x00000010)
+#define  USB_INTR_ASYN_ADV_EN                 (0x00000020)
+#define  USB_INTR_RESET_EN                    (0x00000040)
+#define  USB_INTR_SOF_EN                      (0x00000080)
+#define  USB_INTR_DEVICE_SUSPEND              (0x00000100)
+
+/* Device Address bit masks */
+#define  USB_DEVICE_ADDRESS_MASK              (0xFE000000)
+#define  USB_DEVICE_ADDRESS_BIT_POS           (25)
+
+/* endpoint list address bit masks */
+#define USB_EP_LIST_ADDRESS_MASK              (0xfffff800)
+
+/* PORTSCX  Register Bit Masks */
+#define  PORTSCX_CURRENT_CONNECT_STATUS       (0x00000001)
+#define  PORTSCX_CONNECT_STATUS_CHANGE        (0x00000002)
+#define  PORTSCX_PORT_ENABLE                  (0x00000004)
+#define  PORTSCX_PORT_EN_DIS_CHANGE           (0x00000008)
+#define  PORTSCX_OVER_CURRENT_ACT             (0x00000010)
+#define  PORTSCX_OVER_CURRENT_CHG             (0x00000020)
+#define  PORTSCX_PORT_FORCE_RESUME            (0x00000040)
+#define  PORTSCX_PORT_SUSPEND                 (0x00000080)
+#define  PORTSCX_PORT_RESET                   (0x00000100)
+#define  PORTSCX_LINE_STATUS_BITS             (0x00000C00)
+#define  PORTSCX_PORT_POWER                   (0x00001000)
+#define  PORTSCX_PORT_INDICTOR_CTRL           (0x0000C000)
+#define  PORTSCX_PORT_TEST_CTRL               (0x000F0000)
+#define  PORTSCX_WAKE_ON_CONNECT_EN           (0x00100000)
+#define  PORTSCX_WAKE_ON_CONNECT_DIS          (0x00200000)
+#define  PORTSCX_WAKE_ON_OVER_CURRENT         (0x00400000)
+#define  PORTSCX_PHY_LOW_POWER_SPD            (0x00800000)
+#define  PORTSCX_PORT_FORCE_FULL_SPEED        (0x01000000)
+#define  PORTSCX_PORT_SPEED_MASK              (0x0C000000)
+#define  PORTSCX_PORT_WIDTH                   (0x10000000)
+#define  PORTSCX_PHY_TYPE_SEL                 (0xC0000000)
+
+/* bit 11-10 are line status */
+#define  PORTSCX_LINE_STATUS_SE0              (0x00000000)
+#define  PORTSCX_LINE_STATUS_JSTATE           (0x00000400)
+#define  PORTSCX_LINE_STATUS_KSTATE           (0x00000800)
+#define  PORTSCX_LINE_STATUS_UNDEF            (0x00000C00)
+#define  PORTSCX_LINE_STATUS_BIT_POS          (10)
+
+/* bit 15-14 are port indicator control */
+#define  PORTSCX_PIC_OFF                      (0x00000000)
+#define  PORTSCX_PIC_AMBER                    (0x00004000)
+#define  PORTSCX_PIC_GREEN                    (0x00008000)
+#define  PORTSCX_PIC_UNDEF                    (0x0000C000)
+#define  PORTSCX_PIC_BIT_POS                  (14)
+
+/* bit 19-16 are port test control */
+#define  PORTSCX_PTC_DISABLE                  (0x00000000)
+#define  PORTSCX_PTC_JSTATE                   (0x00010000)
+#define  PORTSCX_PTC_KSTATE                   (0x00020000)
+#define  PORTSCX_PTC_SEQNAK                   (0x00030000)
+#define  PORTSCX_PTC_PACKET                   (0x00040000)
+#define  PORTSCX_PTC_FORCE_EN                 (0x00050000)
+#define  PORTSCX_PTC_BIT_POS                  (16)
+
+/* bit 27-26 are port speed */
+#define  PORTSCX_PORT_SPEED_FULL              (0x00000000)
+#define  PORTSCX_PORT_SPEED_LOW               (0x04000000)
+#define  PORTSCX_PORT_SPEED_HIGH              (0x08000000)
+#define  PORTSCX_PORT_SPEED_UNDEF             (0x0C000000)
+#define  PORTSCX_SPEED_BIT_POS                (26)
+
+/* OTGSC Register Bit Masks */
+#define  OTGSC_B_SESSION_VALID_IRQ_EN           (1 << 27)
+#define  OTGSC_B_SESSION_VALID_IRQ_STS          (1 << 19)
+#define  OTGSC_B_SESSION_VALID                  (1 << 11)
+
+/* bit 28 is parallel transceiver width for UTMI interface */
+#define  PORTSCX_PTW                          (0x10000000)
+#define  PORTSCX_PTW_8BIT                     (0x00000000)
+#define  PORTSCX_PTW_16BIT                    (0x10000000)
+
+/* bit 31-30 are port transceiver select */
+#define  PORTSCX_PTS_UTMI                     (0x00000000)
+#define  PORTSCX_PTS_ULPI                     (0x80000000)
+#define  PORTSCX_PTS_FSLS                     (0xC0000000)
+#define  PORTSCX_PTS_BIT_POS                  (30)
+
+/* USB MODE Register Bit Masks */
+#define  USB_MODE_CTRL_MODE_IDLE              (0x00000000)
+#define  USB_MODE_CTRL_MODE_DEVICE            (0x00000002)
+#define  USB_MODE_CTRL_MODE_HOST              (0x00000003)
+#define  USB_MODE_CTRL_MODE_MASK              0x00000003
+#define  USB_MODE_CTRL_MODE_RSV               (0x00000001)
+#define  USB_MODE_ES                          0x00000004 /* (big) Endian Sel */
+#define  USB_MODE_SETUP_LOCK_OFF              (0x00000008)
+#define  USB_MODE_STREAM_DISABLE              (0x00000010)
+/* Endpoint Flush Register */
+#define EPFLUSH_TX_OFFSET		      (0x00010000)
+#define EPFLUSH_RX_OFFSET		      (0x00000000)
+
+/* Endpoint Setup Status bit masks */
+#define  EP_SETUP_STATUS_MASK                 (0x0000003F)
+#define  EP_SETUP_STATUS_EP0		      (0x00000001)
+
+/* ENDPOINTCTRLx  Register Bit Masks */
+#define  EPCTRL_TX_ENABLE                     (0x00800000)
+#define  EPCTRL_TX_DATA_TOGGLE_RST            (0x00400000)	/* Not EP0 */
+#define  EPCTRL_TX_DATA_TOGGLE_INH            (0x00200000)	/* Not EP0 */
+#define  EPCTRL_TX_TYPE                       (0x000C0000)
+#define  EPCTRL_TX_DATA_SOURCE                (0x00020000)	/* Not EP0 */
+#define  EPCTRL_TX_EP_STALL                   (0x00010000)
+#define  EPCTRL_RX_ENABLE                     (0x00000080)
+#define  EPCTRL_RX_DATA_TOGGLE_RST            (0x00000040)	/* Not EP0 */
+#define  EPCTRL_RX_DATA_TOGGLE_INH            (0x00000020)	/* Not EP0 */
+#define  EPCTRL_RX_TYPE                       (0x0000000C)
+#define  EPCTRL_RX_DATA_SINK                  (0x00000002)	/* Not EP0 */
+#define  EPCTRL_RX_EP_STALL                   (0x00000001)
+
+/* bit 19-18 and 3-2 are endpoint type */
+#define  EPCTRL_EP_TYPE_CONTROL               (0)
+#define  EPCTRL_EP_TYPE_ISO                   (1)
+#define  EPCTRL_EP_TYPE_BULK                  (2)
+#define  EPCTRL_EP_TYPE_INTERRUPT             (3)
+#define  EPCTRL_TX_EP_TYPE_SHIFT              (18)
+#define  EPCTRL_RX_EP_TYPE_SHIFT              (2)
+
+/* SNOOPn Register Bit Masks */
+#define  SNOOP_ADDRESS_MASK                   (0xFFFFF000)
+#define  SNOOP_SIZE_ZERO                      (0x00)	/* snooping disable */
+#define  SNOOP_SIZE_4KB                       (0x0B)	/* 4KB snoop size */
+#define  SNOOP_SIZE_8KB                       (0x0C)
+#define  SNOOP_SIZE_16KB                      (0x0D)
+#define  SNOOP_SIZE_32KB                      (0x0E)
+#define  SNOOP_SIZE_64KB                      (0x0F)
+#define  SNOOP_SIZE_128KB                     (0x10)
+#define  SNOOP_SIZE_256KB                     (0x11)
+#define  SNOOP_SIZE_512KB                     (0x12)
+#define  SNOOP_SIZE_1MB                       (0x13)
+#define  SNOOP_SIZE_2MB                       (0x14)
+#define  SNOOP_SIZE_4MB                       (0x15)
+#define  SNOOP_SIZE_8MB                       (0x16)
+#define  SNOOP_SIZE_16MB                      (0x17)
+#define  SNOOP_SIZE_32MB                      (0x18)
+#define  SNOOP_SIZE_64MB                      (0x19)
+#define  SNOOP_SIZE_128MB                     (0x1A)
+#define  SNOOP_SIZE_256MB                     (0x1B)
+#define  SNOOP_SIZE_512MB                     (0x1C)
+#define  SNOOP_SIZE_1GB                       (0x1D)
+#define  SNOOP_SIZE_2GB                       (0x1E)	/* 2GB snoop size */
+
+/* pri_ctrl Register Bit Masks */
+#define  PRI_CTRL_PRI_LVL1                    (0x0000000C)
+#define  PRI_CTRL_PRI_LVL0                    (0x00000003)
+
+/* si_ctrl Register Bit Masks */
+#define  SI_CTRL_ERR_DISABLE                  (0x00000010)
+#define  SI_CTRL_IDRC_DISABLE                 (0x00000008)
+#define  SI_CTRL_RD_SAFE_EN                   (0x00000004)
+#define  SI_CTRL_RD_PREFETCH_DISABLE          (0x00000002)
+#define  SI_CTRL_RD_PREFEFETCH_VAL            (0x00000001)
+
+/* control Register Bit Masks */
+#define  USB_CTRL_IOENB                       (0x00000004)
+#define  USB_CTRL_ULPI_INT0EN                 (0x00000001)
+#define  USB_CTRL_OTG_WUIR                   (0x80000000)
+#define  USB_CTRL_OTG_WUIE                   (0x08000000)
+#define  USB_CTRL_OTG_VWUE			(0x00001000)
+#define  USB_CTRL_OTG_IWUE			(0x00100000)
+
+/* PHY control0 Register Bit Masks */
+#define	PHY_CTRL0_CONF2			(1 << 26)
+#define PHY_CTRL0_USBEN			(1 << 24) /* USB UTMI PHY Enable */
+
+/* USB UH2 CTRL Register Bits */
+#define USB_UH2_OVBWK_EN		(1 << 6) /* OTG VBUS Wakeup Enable */
+#define USB_UH2_OIDWK_EN		(1 << 5) /* OTG ID Wakeup Enable */
+/*!
+ * Endpoint Queue Head data struct
+ * Rem: all the variables of qh are LittleEndian Mode
+ * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
+ */
+struct ep_queue_head {
+	/*!
+	 * Mult(31-30) , Zlt(29) , Max Pkt len  and IOS(15)
+	 */
+	u32 max_pkt_length;
+
+	/*!
+	 *  Current dTD Pointer(31-5)
+	 */
+	u32 curr_dtd_ptr;
+
+	/*!
+	 *  Next dTD Pointer(31-5), T(0)
+	 */
+	u32 next_dtd_ptr;
+
+	/*!
+	 *  Total bytes (30-16), IOC (15), MultO(11-10), STS (7-0)
+	 */
+	u32 size_ioc_int_sts;
+
+	/*!
+	 * Buffer pointer Page 0 (31-12)
+	 */
+	u32 buff_ptr0;
+
+	/*!
+	 * Buffer pointer Page 1 (31-12)
+	 */
+	u32 buff_ptr1;
+
+	/*!
+	 * Buffer pointer Page 2 (31-12)
+	 */
+	u32 buff_ptr2;
+
+	/*!
+	 * Buffer pointer Page 3 (31-12)
+	 */
+	u32 buff_ptr3;
+
+	/*!
+	 * Buffer pointer Page 4 (31-12)
+	 */
+	u32 buff_ptr4;
+
+	/*!
+	 * reserved field 1
+	 */
+	u32 res1;
+	/*!
+	 * Setup data 8 bytes
+	 */
+	u8 setup_buffer[8];	/* Setup data 8 bytes */
+
+	/*!
+	 * reserved field 2,pad out to 64 bytes
+	 */
+	u32 res2[4];
+};
+
+/* Endpoint Queue Head Bit Masks */
+#define  EP_QUEUE_HEAD_MULT_POS               (30)
+#define  EP_QUEUE_HEAD_ZLT_SEL                (0x20000000)
+#define  EP_QUEUE_HEAD_MAX_PKT_LEN_POS        (16)
+#define  EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info)   (((ep_info)>>16)&0x07ff)
+#define  EP_QUEUE_HEAD_IOS                    (0x00008000)
+#define  EP_QUEUE_HEAD_NEXT_TERMINATE         (0x00000001)
+#define  EP_QUEUE_HEAD_IOC                    (0x00008000)
+#define  EP_QUEUE_HEAD_MULTO                  (0x00000C00)
+#define  EP_QUEUE_HEAD_STATUS_HALT	      (0x00000040)
+#define  EP_QUEUE_HEAD_STATUS_ACTIVE          (0x00000080)
+#define  EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
+#define  EP_QUEUE_HEAD_NEXT_POINTER_MASK      0xFFFFFFE0
+#define  EP_QUEUE_FRINDEX_MASK                (0x000007FF)
+#define  EP_MAX_LENGTH_TRANSFER               (0x4000)
+
+/*!
+ * Endpoint Transfer Descriptor data struct
+ *  Rem: all the variables of td are LittleEndian Mode
+ *       must be 32-byte aligned
+ */
+struct ep_td_struct {
+	/*!
+	 *  Next TD pointer(31-5), T(0) set indicate invalid
+	 */
+	u32 next_td_ptr;
+
+	/*!
+	 *  Total bytes (30-16), IOC (15),MultO(11-10), STS (7-0)
+	 */
+	u32 size_ioc_sts;
+
+	/*!
+	 * Buffer pointer Page 0
+	 */
+	u32 buff_ptr0;
+
+	/*!
+	 * Buffer pointer Page 1
+	 */
+	u32 buff_ptr1;
+
+	/*!
+	 * Buffer pointer Page 2
+	 */
+	u32 buff_ptr2;
+
+	/*!
+	 * Buffer pointer Page 3
+	 */
+	u32 buff_ptr3;
+
+	/*!
+	 * Buffer pointer Page 4
+	 */
+	u32 buff_ptr4;
+
+	/*!
+	 * dma address of this td
+	 * */
+	dma_addr_t td_dma;
+
+	/*!
+	 * virtual address of next td
+	 * */
+	struct ep_td_struct *next_td_virt;
+
+	/*!
+	 * make it an even 16 words
+	 * */
+	u32 res[7];
+};
+
+/*!
+ * Endpoint Transfer Descriptor bit Masks
+ */
+#define  DTD_NEXT_TERMINATE                   (0x00000001)
+#define  DTD_IOC                              (0x00008000)
+#define  DTD_STATUS_ACTIVE                    (0x00000080)
+#define  DTD_STATUS_HALTED                    (0x00000040)
+#define  DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
+#define  DTD_STATUS_TRANSACTION_ERR           (0x00000008)
+#define  DTD_RESERVED_FIELDS                  (0x80007300)
+#define  DTD_ADDR_MASK                        0xFFFFFFE0
+#define  DTD_PACKET_SIZE                      (0x7FFF0000)
+#define  DTD_LENGTH_BIT_POS                   (16)
+#define  DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
+                                               DTD_STATUS_DATA_BUFF_ERR | \
+                                               DTD_STATUS_TRANSACTION_ERR)
+/* Alignment requirements; must be a power of two */
+#define DTD_ALIGNMENT				0x20
+#define QH_ALIGNMENT				2048
+
+/* Controller dma boundary */
+#define UDC_DMA_BOUNDARY			0x1000
+
+/* -----------------------------------------------------------------------*/
+/* ##### enum data
+*/
+typedef enum {
+	e_ULPI,
+	e_UTMI_8BIT,
+	e_UTMI_16BIT,
+	e_SERIAL
+} e_PhyInterface;
+
+/*-------------------------------------------------------------------------*/
+
+struct fsl_req {
+	struct usb_request req;
+	struct list_head queue;
+	/* ep_queue() func will add
+	   a request->queue into a udc_ep->queue 'd tail */
+	struct fsl_ep *ep;
+	unsigned mapped;
+
+	struct ep_td_struct *head, *tail;	/* For dTD List
+						   this is a BigEndian Virtual addr */
+	unsigned int dtd_count;
+	/* just for IRAM patch */
+	dma_addr_t oridma;	/* original dma */
+	size_t buffer_offset;	/* offset of user buffer */
+	int last_one;		/* mark if reach to last packet */
+	struct ep_td_struct *cur;	/* current tranfer dtd */
+};
+
+#define REQ_UNCOMPLETE		(1)
+
+struct fsl_ep {
+	struct usb_ep ep;
+	struct list_head queue;
+	struct fsl_udc *udc;
+	struct ep_queue_head *qh;
+	const struct usb_endpoint_descriptor *desc;
+	struct usb_gadget *gadget;
+
+	char name[14];
+	unsigned stopped:1;
+};
+
+#define EP_DIR_IN	1
+#define EP_DIR_OUT	0
+
+struct fsl_udc {
+	struct usb_gadget gadget;
+	struct usb_gadget_driver *driver;
+	struct fsl_usb2_platform_data *pdata;
+	struct fsl_ep *eps;
+	unsigned int max_ep;
+	unsigned int irq;
+
+	struct usb_ctrlrequest local_setup_buff;
+	spinlock_t lock;
+	u32 xcvr_type;
+	struct otg_transceiver *transceiver;
+	unsigned softconnect:1;
+	unsigned vbus_active:1;
+	unsigned stopped:1;
+	unsigned remote_wakeup:1;
+	unsigned already_stopped:1;
+
+	struct ep_queue_head *ep_qh;	/* Endpoints Queue-Head */
+	struct fsl_req *status_req;	/* ep0 status request */
+	struct fsl_req *data_req;	/* ep0 data request */
+	struct dma_pool *td_pool;	/* dma pool for DTD */
+	enum fsl_usb2_phy_modes phy_mode;
+
+	size_t ep_qh_size;		/* size after alignment adjustment*/
+	dma_addr_t ep_qh_dma;		/* dma address of QH */
+
+	u32 max_pipes;		/* Device max pipes */
+	u32 max_use_endpts;	/* Max endpointes to be used */
+	u32 bus_reset;		/* Device is bus reseting */
+	u32 resume_state;	/* USB state to resume */
+	u32 usb_state;		/* USB current state */
+	u32 usb_next_state;	/* USB next state */
+	u32 ep0_dir;		/* Endpoint zero direction: can be
+				   USB_DIR_IN or USB_DIR_OUT */
+	u32 usb_sof_count;	/* SOF count */
+	u32 errors;		/* USB ERRORs count */
+	u8 device_address;	/* Device USB address */
+
+	struct completion *done;	/* to make sure release() is done */
+	u32 iram_buffer[IRAM_PPH_NTD];
+	void *iram_buffer_v[IRAM_PPH_NTD];
+};
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+#define DBG(fmt, args...) 	printk(KERN_DEBUG "[%s]  " fmt "\n", \
+				__func__, ## args)
+#else
+#define DBG(fmt, args...)	do {} while (0)
+#endif
+
+#if 0
+static void dump_msg(const char *label, const u8 * buf, unsigned int length)
+{
+	unsigned int start, num, i;
+	char line[52], *p;
+
+	if (length >= 512)
+		return;
+	pr_debug("udc: %s, length %u:\n", label, length);
+	start = 0;
+	while (length > 0) {
+		num = min(length, 16u);
+		p = line;
+		for (i = 0; i < num; ++i) {
+			if (i == 8)
+				*p++ = ' ';
+			sprintf(p, " %02x", buf[i]);
+			p += 3;
+		}
+		*p = 0;
+		printk(KERN_DEBUG "%6x: %s\n", start, line);
+		buf += num;
+		start += num;
+		length -= num;
+	}
+}
+#endif
+
+#ifdef VERBOSE
+#define VDBG		DBG
+#else
+#define VDBG(stuff...)	do {} while (0)
+#endif
+
+#define ERR(stuff...)		printk(KERN_ERR "udc: " stuff)
+#define INFO(stuff...)		printk(KERN_INFO "udc: " stuff)
+
+/*-------------------------------------------------------------------------*/
+
+/* ### Add board specific defines here
+ */
+
+/*
+ * ### pipe direction macro from device view
+ */
+#define USB_RECV	(0)	/* OUT EP */
+#define USB_SEND	(1)	/* IN EP */
+
+/*
+ * ### internal used help routines.
+ */
+#define ep_index(EP)         ((EP)->desc->bEndpointAddress&0xF)
+#define ep_maxpacket(EP)     ((EP)->ep.maxpacket)
+
+#define ep_is_in(EP)	( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
+				USB_DIR_IN ):((EP)->desc->bEndpointAddress \
+				& USB_DIR_IN)==USB_DIR_IN)
+
+#define get_ep_by_pipe(udc, pipe)	((pipe == 1)? &udc->eps[0]: \
+					&udc->eps[pipe])
+#define get_pipe_by_windex(windex)	((windex & USB_ENDPOINT_NUMBER_MASK) \
+					* 2 + ((windex & USB_DIR_IN) ? 1 : 0))
+
+/* Bulk only class request */
+#define USB_BULK_RESET_REQUEST          0xff
+
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_STMP3XXX) || \
+	defined(CONFIG_ARCH_MXS)
+#include <mach/fsl_usb_gadget.h>
+#elif CONFIG_PPC32
+#include <asm/fsl_usb_gadget.h>
+#endif
+
+#endif				/* __ARCOTG_UDC_H */
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 1e6aa504d58a..66105ce49672 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -369,7 +369,11 @@ static struct {
 } mod_data = {					// Default values
 	.transport_parm		= "BBB",
 	.protocol_parm		= "SCSI",
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	.removable		= 1,
+#else
 	.removable		= 0,
+#endif
 	.can_stall		= 1,
 	.cdrom			= 0,
 	.vendor			= DRIVER_VENDOR_ID,
@@ -714,8 +718,16 @@ struct fsg_dev {
 	unsigned int		nluns;
 	struct lun		*luns;
 	struct lun		*curlun;
+
+#ifdef CONFIG_FSL_UTP
+	void			*utp;
+#endif
 };
 
+#ifdef CONFIG_FSL_UTP
+#include "fsl_updater.h"
+#endif
+
 typedef void (*fsg_routine_t)(struct fsg_dev *);
 
 static int exception_in_progress(struct fsg_dev *fsg)
@@ -752,7 +764,7 @@ static void dump_msg(struct fsg_dev *fsg, const char *label,
 	if (length < 512) {
 		DBG(fsg, "%s, length %u:\n", label, length);
 		print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
-				16, 1, buf, length, 0);
+				16, 1, buf, length, !0);
 	}
 }
 
@@ -838,7 +850,11 @@ device_desc = {
 
 	.iManufacturer =	STRING_MANUFACTURER,
 	.iProduct =		STRING_PRODUCT,
+#ifdef CONFIG_FSL_UTP
+	.iSerialNumber = 0,
+#else
 	.iSerialNumber =	STRING_SERIAL,
+#endif
 	.bNumConfigurations =	1,
 };
 
@@ -2068,6 +2084,13 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 	}
 #endif
 
+#ifdef CONFIG_FSL_UTP
+	if (utp_get_sense(fsg) == 0) {	/* got the sense from the UTP */
+		sd = UTP_CTX(fsg)->sd;
+		sdinfo = UTP_CTX(fsg)->sdinfo;
+		valid = 0;
+	} else
+#endif
 	if (!curlun) {		// Unsupported LUNs are okay
 		fsg->bad_lun_okay = 1;
 		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
@@ -2089,6 +2112,9 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 	buf[7] = 18 - 8;			// Additional sense length
 	buf[12] = ASC(sd);
 	buf[13] = ASCQ(sd);
+#ifdef CONFIG_FSL_UTP
+	put_unaligned_be32(UTP_CTX(fsg)->sdinfo_h, &buf[8]);
+#endif
 	return 18;
 }
 
@@ -2849,6 +2875,13 @@ static int do_scsi_command(struct fsg_dev *fsg)
 	fsg->phase_error = 0;
 	fsg->short_packet_received = 0;
 
+#ifdef CONFIG_FSL_UTP
+	reply = utp_handle_message(fsg, fsg->cmnd, reply);
+
+	if (reply != -EINVAL)
+		return reply;
+#endif
+
 	down_read(&fsg->filesem);	// We're using the backing file
 	switch (fsg->cmnd[0]) {
 
@@ -3537,10 +3570,12 @@ static int fsg_main_thread(void *fsg_)
 	/* Allow the thread to be frozen */
 	set_freezable();
 
+#ifndef CONFIG_FSL_UTP
 	/* Arrange for userspace references to be interpreted as kernel
 	 * pointers.  That way we can pass a kernel pointer to a routine
 	 * that expects a __user pointer and it will work okay. */
 	set_fs(get_ds());
+#endif
 
 	/* The main loop */
 	while (fsg->state != FSG_STATE_TERMINATED) {
@@ -3851,6 +3886,9 @@ static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
 	}
 
 	set_gadget_data(gadget, NULL);
+#ifdef CONFIG_FSL_UTP
+	utp_exit(fsg);
+#endif
 }
 
 
@@ -3889,6 +3927,17 @@ static int __init check_parameters(struct fsg_dev *fsg)
 
 	prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
 
+#ifdef CONFIG_FSL_UTP
+	mod_data.can_stall = 0;
+	mod_data.removable = 1;
+	mod_data.nluns = 1;
+	mod_data.file[0] = NULL;
+	mod_data.vendor = 0x066F;
+	mod_data.product = 0x37FF;
+	pr_info("%s:UTP settings are in place now, overriding defaults\n",
+		__func__);
+#endif
+
 #ifdef CONFIG_USB_FILE_STORAGE_TEST
 	if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
 		;		// Use default setting
@@ -3941,8 +3990,9 @@ static int __init check_parameters(struct fsg_dev *fsg)
 
 	return 0;
 }
-
-
+#ifdef CONFIG_FSL_UTP
+#include "fsl_updater.c"
+#endif
 static int __init fsg_bind(struct usb_gadget *gadget)
 {
 	struct fsg_dev		*fsg = the_fsg;
@@ -3970,6 +4020,10 @@ static int __init fsg_bind(struct usb_gadget *gadget)
 		}
 	}
 
+#ifdef CONFIG_FSL_UTP
+	utp_init(fsg);
+#endif
+
 	/* Find out how many LUNs there should be */
 	i = mod_data.nluns;
 	if (i == 0)
@@ -4242,7 +4296,6 @@ static int __init fsg_init(void)
 {
 	int		rc;
 	struct fsg_dev	*fsg;
-
 	if ((rc = fsg_alloc()) != 0)
 		return rc;
 	fsg = the_fsg;
@@ -4250,8 +4303,12 @@ static int __init fsg_init(void)
 		kref_put(&fsg->ref, fsg_release);
 	return rc;
 }
-module_init(fsg_init);
 
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	fs_initcall(fsg_init);
+#else
+	module_init(fsg_init);
+#endif
 
 static void __exit fsg_cleanup(void)
 {
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 42a74b8a0bb8..2b8c435db49e 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2004-2010 Freescale Semicondutor, Inc. All rights reserved.
  *
  * Author: Li Yang <leoli@freescale.com>
  *         Jiang Bo <tanya.jiang@freescale.com>
@@ -2475,8 +2475,11 @@ static int __init udc_init(void)
 	return platform_driver_probe(&udc_driver, fsl_udc_probe);
 }
 
-module_init(udc_init);
-
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	fs_initcall(udc_init);
+#else
+	module_init(udc_init);
+#endif
 static void __exit udc_exit(void)
 {
 	platform_driver_unregister(&udc_driver);
diff --git a/drivers/usb/gadget/fsl_updater.c b/drivers/usb/gadget/fsl_updater.c
new file mode 100644
index 000000000000..50acce441a90
--- /dev/null
+++ b/drivers/usb/gadget/fsl_updater.c
@@ -0,0 +1,548 @@
+/*
+ * Freescale UUT driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+static u64 get_be64(u8 *buf)
+{
+	return ((u64)get_unaligned_be32(buf) << 32) |
+		get_unaligned_be32(buf + 4);
+}
+
+static int utp_init(struct fsg_dev *fsg)
+{
+	init_waitqueue_head(&utp_context.wq);
+	init_waitqueue_head(&utp_context.list_full_wq);
+
+	INIT_LIST_HEAD(&utp_context.read);
+	INIT_LIST_HEAD(&utp_context.write);
+	mutex_init(&utp_context.lock);
+
+	/* the max message is 64KB */
+	utp_context.buffer = vmalloc(0x10000);
+	if (!utp_context.buffer)
+		return -EIO;
+	utp_context.utp_version = 0x1ull;
+	fsg->utp = &utp_context;
+	return misc_register(&utp_dev);
+}
+
+static void utp_exit(struct fsg_dev *fsg)
+{
+	vfree(utp_context.buffer);
+	misc_deregister(&utp_dev);
+}
+
+static struct utp_user_data *utp_user_data_alloc(size_t size)
+{
+	struct utp_user_data *uud;
+
+	uud = kzalloc(size + sizeof(*uud), GFP_KERNEL);
+	if (!uud)
+		return uud;
+	uud->data.size = size + sizeof(uud->data);
+	INIT_LIST_HEAD(&uud->link);
+	return uud;
+}
+
+static void utp_user_data_free(struct utp_user_data *uud)
+{
+	mutex_lock(&utp_context.lock);
+	list_del(&uud->link);
+	mutex_unlock(&utp_context.lock);
+	kfree(uud);
+}
+
+/* Get the number of element for list */
+static u32 count_list(struct list_head *l)
+{
+	u32 count = 0;
+	struct list_head *tmp;
+
+	list_for_each(tmp, l) {
+		count++;
+	}
+
+	return count;
+}
+/* The routine will not go on if utp_context.queue is empty */
+#define WAIT_ACTIVITY(queue) \
+ wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue))
+
+/* Called by userspace program (uuc) */
+static ssize_t utp_file_read(struct file *file,
+			     char __user *buf,
+			     size_t size,
+			     loff_t *off)
+{
+	struct utp_user_data *uud;
+	size_t size_to_put;
+	int free = 0;
+
+	WAIT_ACTIVITY(read);
+
+	mutex_lock(&utp_context.lock);
+	uud = list_first_entry(&utp_context.read, struct utp_user_data, link);
+	mutex_unlock(&utp_context.lock);
+	size_to_put = uud->data.size;
+
+	if (size >= size_to_put)
+		free = !0;
+	if (copy_to_user(buf, &uud->data, size_to_put))
+		return -EACCES;
+	if (free)
+		utp_user_data_free(uud);
+	else {
+		pr_info("sizeof = %d, size = %d\n",
+			sizeof(uud->data),
+			uud->data.size);
+
+		pr_err("Will not free utp_user_data, because buffer size = %d,"
+			"need to put %d\n", size, size_to_put);
+	}
+
+	/*
+	 * The user program has already finished data process,
+	 * go on getting data from the host
+	 */
+	wake_up(&utp_context.list_full_wq);
+
+	return size_to_put;
+}
+
+static ssize_t utp_file_write(struct file *file, const char __user *buf,
+				size_t size, loff_t *off)
+{
+	struct utp_user_data *uud;
+
+	if (size < sizeof(uud->data))
+		return -EINVAL;
+	uud = utp_user_data_alloc(size);
+	if (copy_from_user(&uud->data, buf, size))
+		return -EACCES;
+	mutex_lock(&utp_context.lock);
+	list_add_tail(&uud->link, &utp_context.write);
+	/* Go on EXEC routine process */
+	wake_up(&utp_context.wq);
+	mutex_unlock(&utp_context.lock);
+	return size;
+}
+
+/* Will be called when the host wants to get the sense data */
+static int utp_get_sense(struct fsg_dev *fsg)
+{
+	if (UTP_CTX(fsg)->processed == 0)
+		return -1;
+
+	UTP_CTX(fsg)->processed = 0;
+	return 0;
+}
+
+static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size)
+{
+	struct fsg_buffhd	*bh;
+	int			rc;
+	u32			amount_left;
+	unsigned int		amount;
+
+	/* Get the starting Logical Block Address and check that it's
+	 * not too big */
+
+	amount_left = size;
+	if (unlikely(amount_left == 0))
+		return -EIO;		/* No default reply*/
+
+	pr_debug("%s: sending %d\n", __func__, size);
+	for (;;) {
+		/* Figure out how much we need to read:
+		 * Try to read the remaining amount.
+		 * But don't read more than the buffer size.
+		 * And don't try to read past the end of the file.
+		 * Finally, if we're not at a page boundary, don't read past
+		 *	the next page.
+		 * If this means reading 0 then we were asked to read past
+		 *	the end of file. */
+		amount = min((unsigned int) amount_left, mod_data.buflen);
+
+		/* Wait for the next buffer to become available */
+		bh = fsg->next_buffhd_to_fill;
+		while (bh->state != BUF_STATE_EMPTY) {
+			rc = sleep_thread(fsg);
+			if (rc)
+				return rc;
+		}
+
+		/* If we were asked to read past the end of file,
+		 * end with an empty buffer. */
+		if (amount == 0) {
+			bh->inreq->length = 0;
+			bh->state = BUF_STATE_FULL;
+			break;
+		}
+
+		/* Perform the read */
+		pr_info("Copied to %p, %d bytes started from %d\n",
+				bh->buf, amount, size - amount_left);
+		/* from upt buffer to file_storeage buffer */
+		memcpy(bh->buf, data + size - amount_left, amount);
+		amount_left  -= amount;
+		fsg->residue -= amount;
+
+		bh->inreq->length = amount;
+		bh->state = BUF_STATE_FULL;
+
+		/* Send this buffer and go read some more */
+		bh->inreq->zero = 0;
+
+		/* USB Physical transfer: Data from device to host */
+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
+				&bh->inreq_busy, &bh->state);
+
+		fsg->next_buffhd_to_fill = bh->next;
+
+		if (amount_left <= 0)
+			break;
+	}
+
+	return size - amount_left;
+}
+
+static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size)
+{
+	struct fsg_buffhd	*bh;
+	int			get_some_more;
+	u32			amount_left_to_req, amount_left_to_write;
+	unsigned int		amount;
+	int			rc;
+	loff_t			offset;
+
+	/* Carry out the file writes */
+	get_some_more = 1;
+	amount_left_to_req = amount_left_to_write = size;
+
+	if (unlikely(amount_left_to_write == 0))
+		return -EIO;
+
+	offset = 0;
+	while (amount_left_to_write > 0) {
+
+		/* Queue a request for more data from the host */
+		bh = fsg->next_buffhd_to_fill;
+		if (bh->state == BUF_STATE_EMPTY && get_some_more) {
+
+			/* Figure out how much we want to get:
+			 * Try to get the remaining amount.
+			 * But don't get more than the buffer size.
+			 * And don't try to go past the end of the file.
+			 * If we're not at a page boundary,
+			 *	don't go past the next page.
+			 * If this means getting 0, then we were asked
+			 *	to write past the end of file.
+			 * Finally, round down to a block boundary. */
+			amount = min(amount_left_to_req, mod_data.buflen);
+
+			if (amount == 0) {
+				get_some_more = 0;
+				/* cry now */
+				continue;
+			}
+
+			/* Get the next buffer */
+			amount_left_to_req -= amount;
+			if (amount_left_to_req == 0)
+				get_some_more = 0;
+
+			/* amount is always divisible by 512, hence by
+			 * the bulk-out maxpacket size */
+			bh->outreq->length = bh->bulk_out_intended_length =
+					amount;
+			bh->outreq->short_not_ok = 1;
+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
+					&bh->outreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+			continue;
+		}
+
+		/* Write the received data to the backing file */
+		bh = fsg->next_buffhd_to_drain;
+		if (bh->state == BUF_STATE_EMPTY && !get_some_more)
+			break;			/* We stopped early */
+		if (bh->state == BUF_STATE_FULL) {
+			smp_rmb();
+			fsg->next_buffhd_to_drain = bh->next;
+			bh->state = BUF_STATE_EMPTY;
+
+			/* Did something go wrong with the transfer? */
+			if (bh->outreq->status != 0)
+				/* cry again, COMMUNICATION_FAILURE */
+				break;
+
+			amount = bh->outreq->actual;
+
+			/* Perform the write */
+			memcpy(data + offset, bh->buf, amount);
+
+			offset += amount;
+			if (signal_pending(current))
+				return -EINTR;		/* Interrupted!*/
+			amount_left_to_write -= amount;
+			fsg->residue -= amount;
+
+			/* Did the host decide to stop early? */
+			if (bh->outreq->actual != bh->outreq->length) {
+				fsg->short_packet_received = 1;
+				break;
+			}
+			continue;
+		}
+
+		/* Wait for something to happen */
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	return -EIO;
+}
+
+static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply)
+{
+	UTP_CTX(fsg)->processed = true;
+	UTP_CTX(fsg)->sdinfo = reply & 0xFFFFFFFF;
+	UTP_CTX(fsg)->sdinfo_h = (reply >> 32) & 0xFFFFFFFF;
+	UTP_CTX(fsg)->sd = (UTP_SENSE_KEY << 16) | code;
+}
+
+static void utp_poll(struct fsg_dev *fsg)
+{
+	struct utp_context *ctx = UTP_CTX(fsg);
+	struct utp_user_data *uud = NULL;
+
+	mutex_lock(&ctx->lock);
+	if (!list_empty(&ctx->write))
+		uud = list_first_entry(&ctx->write, struct utp_user_data, link);
+	mutex_unlock(&ctx->lock);
+
+	if (uud) {
+		if (uud->data.flags & UTP_FLAG_STATUS) {
+			printk(KERN_WARNING "%s: exit with status %d\n",
+					__func__, uud->data.status);
+			UTP_SS_EXIT(fsg, uud->data.status);
+		} else {
+			pr_debug("%s: pass\n", __func__);
+			UTP_SS_PASS(fsg);
+		}
+		utp_user_data_free(uud);
+	} else {
+		pr_debug("%s: still busy...\n", __func__);
+		UTP_SS_BUSY(fsg, --ctx->counter);
+	}
+}
+
+static int utp_exec(struct fsg_dev *fsg,
+		    char *command,
+		    int cmdsize,
+		    unsigned long long payload)
+{
+	struct utp_user_data *uud = NULL, *uud2r;
+	struct utp_context *ctx = UTP_CTX(fsg);
+
+	uud2r = utp_user_data_alloc(cmdsize + 1);
+	uud2r->data.flags = UTP_FLAG_COMMAND;
+	uud2r->data.payload = payload;
+	strncpy(uud2r->data.command, command, cmdsize);
+
+	mutex_lock(&ctx->lock);
+	list_add_tail(&uud2r->link, &ctx->read);
+	mutex_unlock(&ctx->lock);
+	/* wake up the read routine */
+	wake_up(&ctx->wq);
+
+	if (command[0] == '!')	/* there will be no response */
+		return 0;
+
+	/*
+	 * the user program (uuc) will return utp_message
+	 * and add list to write list
+	 */
+	WAIT_ACTIVITY(write);
+
+	mutex_lock(&ctx->lock);
+	if (!list_empty(&ctx->write)) {
+		uud = list_first_entry(&ctx->write, struct utp_user_data, link);
+#ifdef DEBUG
+		pr_info("UUD:\n\tFlags = %02X\n", uud->data.flags);
+		if (uud->data.flags & UTP_FLAG_DATA) {
+			pr_info("\tbufsize = %d\n", uud->data.bufsize);
+			print_hex_dump(KERN_DEBUG, "\t", DUMP_PREFIX_NONE,
+				16, 2, uud->data.data, uud->data.bufsize, true);
+		}
+		if (uud->data.flags & UTP_FLAG_REPORT_BUSY)
+			pr_info("\tBUSY\n");
+#endif
+	}
+	mutex_unlock(&ctx->lock);
+
+	if (uud->data.flags & UTP_FLAG_DATA) {
+		memcpy(ctx->buffer, uud->data.data, uud->data.bufsize);
+		UTP_SS_SIZE(fsg, uud->data.bufsize);
+	} else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
+		ctx->counter = 0xFFFF;
+		UTP_SS_BUSY(fsg, ctx->counter);
+	} else if (uud->data.flags & UTP_FLAG_STATUS) {
+		printk(KERN_WARNING "%s: exit with status %d\n", __func__,
+				uud->data.status);
+		UTP_SS_EXIT(fsg, uud->data.status);
+	} else {
+		pr_debug("%s: pass\n", __func__);
+		UTP_SS_PASS(fsg);
+	}
+	utp_user_data_free(uud);
+	return 0;
+}
+
+static int utp_send_status(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	u8			status = USB_STATUS_PASS;
+	struct bulk_cs_wrap	*csw;
+	int 			rc;
+
+	/* Wait for the next buffer to become available */
+	bh = fsg->next_buffhd_to_fill;
+	while (bh->state != BUF_STATE_EMPTY) {
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	if (fsg->phase_error) {
+		DBG(fsg, "sending phase-error status\n");
+		status = USB_STATUS_PHASE_ERROR;
+
+	} else if ((UTP_CTX(fsg)->sd & 0xFFFF) != UTP_REPLY_PASS) {
+		status = USB_STATUS_FAIL;
+	}
+
+	csw = bh->buf;
+
+	/* Store and send the Bulk-only CSW */
+	csw->Signature = __constant_cpu_to_le32(USB_BULK_CS_SIG);
+	csw->Tag = fsg->tag;
+	csw->Residue = cpu_to_le32(fsg->residue);
+	csw->Status = status;
+
+	bh->inreq->length = USB_BULK_CS_WRAP_LEN;
+	bh->inreq->zero = 0;
+	start_transfer(fsg, fsg->bulk_in, bh->inreq,
+			&bh->inreq_busy, &bh->state);
+	fsg->next_buffhd_to_fill = bh->next;
+	return 0;
+}
+
+static int utp_handle_message(struct fsg_dev *fsg,
+			      char *cdb_data,
+			      int default_reply)
+{
+	struct utp_msg *m = (struct utp_msg *)cdb_data;
+	void *data = NULL;
+	int r;
+	struct utp_user_data *uud2r;
+	unsigned long long param;
+	unsigned long tag;
+
+	if (m->f0 != 0xF0)
+		return default_reply;
+
+	tag = get_unaligned_be32((void *)&m->utp_msg_tag);
+	param = get_be64((void *)&m->param);
+	pr_debug("Type 0x%x, tag 0x%08lx, param %llx\n",
+			m->utp_msg_type, tag, param);
+
+	switch ((enum utp_msg_type)m->utp_msg_type) {
+
+	case UTP_POLL:
+		if (get_be64((void *)&m->param) == 1) {
+			pr_debug("%s: version request\n", __func__);
+			UTP_SS_EXIT(fsg, UTP_CTX(fsg)->utp_version);
+			break;
+		}
+		utp_poll(fsg);
+		break;
+	case UTP_EXEC:
+		pr_debug("%s: EXEC\n", __func__);
+		data = kzalloc(fsg->data_size, GFP_KERNEL);
+		/* copy data from usb buffer to utp buffer */
+		utp_do_write(fsg, data, fsg->data_size);
+		utp_exec(fsg, data, fsg->data_size, param);
+		kfree(data);
+		break;
+	case UTP_GET: /* data from device to host */
+		pr_debug("%s: GET, %d bytes\n", __func__, fsg->data_size);
+		r = utp_do_read(fsg, UTP_CTX(fsg)->buffer, fsg->data_size);
+		UTP_SS_PASS(fsg);
+		break;
+	case UTP_PUT: /* data from host to device */
+		pr_debug("%s: PUT, %d bytes\n", __func__, fsg->data_size);
+		uud2r = utp_user_data_alloc(fsg->data_size);
+		uud2r->data.bufsize = fsg->data_size;
+		uud2r->data.flags = UTP_FLAG_DATA;
+		utp_do_write(fsg, uud2r->data.data, fsg->data_size);
+		/* don't know what will be written */
+		mutex_lock(&UTP_CTX(fsg)->lock);
+		list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read);
+		mutex_unlock(&UTP_CTX(fsg)->lock);
+		wake_up(&UTP_CTX(fsg)->wq);
+		/*
+		 * Return PASS or FAIL according to uuc's status
+		 * Please open it if need to check uuc's status
+		 * and use another version uuc
+		 */
+#if 0
+		struct utp_user_data *uud = NULL;
+		struct utp_context *ctx;
+		WAIT_ACTIVITY(write);
+		ctx = UTP_CTX(fsg);
+		mutex_lock(&ctx->lock);
+
+		if (!list_empty(&ctx->write))
+			uud = list_first_entry(&ctx->write,
+					struct utp_user_data, link);
+
+		mutex_unlock(&ctx->lock);
+		if (uud) {
+			if (uud->data.flags & UTP_FLAG_STATUS) {
+				printk(KERN_WARNING "%s: exit with status %d\n",
+					 __func__, uud->data.status);
+				UTP_SS_EXIT(fsg, uud->data.status);
+			} else {
+				pr_debug("%s: pass\n", __func__);
+				UTP_SS_PASS(fsg);
+			}
+			utp_user_data_free(uud);
+		} else{
+			UTP_SS_PASS(fsg);
+		}
+#endif
+		UTP_SS_PASS(fsg);
+
+		wait_event_interruptible(UTP_CTX(fsg)->list_full_wq,
+			count_list(&UTP_CTX(fsg)->read) < 7);
+		break;
+	}
+
+	utp_send_status(fsg);
+	return -1;
+}
+
diff --git a/drivers/usb/gadget/fsl_updater.h b/drivers/usb/gadget/fsl_updater.h
new file mode 100644
index 000000000000..70e4defa1a9c
--- /dev/null
+++ b/drivers/usb/gadget/fsl_updater.h
@@ -0,0 +1,141 @@
+/*
+ * Freescale UUT driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __FSL_UPDATER_H
+#define __FSL_UPDATER_H
+
+#include <linux/miscdevice.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+
+static int utp_init(struct fsg_dev *fsg);
+static void utp_exit(struct fsg_dev *fsg);
+static ssize_t utp_file_read(struct file *file,
+			     char __user *buf,
+			     size_t size,
+			     loff_t *off);
+
+static ssize_t utp_file_write(struct file *file,
+			      const char __user *buf,
+			      size_t size,
+			      loff_t *off);
+
+static struct utp_user_data *utp_user_data_alloc(size_t size);
+static void utp_user_data_free(struct utp_user_data *uud);
+static int utp_get_sense(struct fsg_dev *fsg);
+static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size);
+static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size);
+static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply);
+static int utp_handle_message(struct fsg_dev *fsg,
+			      char *cdb_data,
+			      int default_reply);
+
+#define UTP_REPLY_PASS		0
+#define UTP_REPLY_EXIT		0x8001
+#define UTP_REPLY_BUSY		0x8002
+#define UTP_REPLY_SIZE		0x8003
+#define UTP_SENSE_KEY		9
+
+#define UTP_MINOR		222
+/* MISC_DYNAMIC_MINOR would be better, but... */
+
+#define UTP_COMMAND_SIZE	80
+
+#define UTP_SS_EXIT(fsg, r) 	utp_set_sense(fsg, UTP_REPLY_EXIT, (u64)r)
+#define UTP_SS_PASS(fsg)	utp_set_sense(fsg, UTP_REPLY_PASS, 0)
+#define UTP_SS_BUSY(fsg, r)	utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r)
+#define UTP_SS_SIZE(fsg, r)	utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r)
+
+/* the structure of utp message which is mapped to 16-byte SCSI CBW's CDB */
+#pragma pack(1)
+struct utp_msg {
+	u8  f0;
+	u8  utp_msg_type;
+	u32 utp_msg_tag;
+	union {
+		struct {
+			u32 param_lsb;
+			u32 param_msb;
+		};
+		u64 param;
+	};
+};
+
+enum utp_msg_type {
+	UTP_POLL = 0,
+	UTP_EXEC,
+	UTP_GET,
+	UTP_PUT,
+};
+
+static struct utp_context {
+	wait_queue_head_t wq;
+	wait_queue_head_t list_full_wq;
+	struct mutex lock;
+	struct list_head read;
+	struct list_head write;
+	u32 sd, sdinfo, sdinfo_h;			/* sense data */
+	int processed;
+	u8 *buffer;
+	u32 counter;
+	u64 utp_version;
+} utp_context;
+
+static const struct file_operations utp_fops = {
+	.open	= nonseekable_open,
+	.read	= utp_file_read,
+	.write	= utp_file_write,
+};
+
+static struct miscdevice utp_dev = {
+	.minor 	= UTP_MINOR,
+	.name 	= "utp",
+	.fops	= &utp_fops,
+};
+
+#define UTP_FLAG_COMMAND	0x00000001
+#define UTP_FLAG_DATA		0x00000002
+#define UTP_FLAG_STATUS		0x00000004
+#define UTP_FLAG_REPORT_BUSY	0x10000000
+struct utp_message {
+	u32 	flags;
+	size_t 	size;
+	union {
+		struct {
+			u64 payload;
+			char command[1];
+		};
+		struct {
+			size_t bufsize;
+			u8 data[1];
+		};
+		u32 status;
+	};
+};
+
+struct utp_user_data {
+	struct  list_head 	link;
+	struct  utp_message	data;
+};
+#pragma pack()
+
+static inline struct utp_context *UTP_CTX(struct fsg_dev *fsg)
+{
+	return (struct utp_context *)fsg->utp;
+}
+
+#endif /* __FSL_UPDATER_H */
+
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 8e0e9a0b7364..60a154db0cf7 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -92,6 +92,12 @@
 #define	gadget_is_pxa27x(g)	0
 #endif
 
+#ifdef CONFIG_USB_GADGET_ARC
+#define	gadget_is_arcotg(g)	!strcmp("fsl-usb2-udc", (g)->name)
+#else
+#define	gadget_is_arcotg(g)	0
+#endif
+
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 #define gadget_is_atmel_usba(g)	!strcmp("atmel_usba_udc", (g)->name)
 #else
@@ -239,6 +245,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x23;
 	else if (gadget_is_langwell(gadget))
 		return 0x24;
+	else if (gadget_is_arcotg(gadget))
+		return 0x25;
 	return -ENOENT;
 }
 
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
index 7d33f50b5874..3580a705c3e7 100644
--- a/drivers/usb/gadget/inode.c
+++ b/drivers/usb/gadget/inode.c
@@ -40,6 +40,8 @@
 #include <linux/usb/gadgetfs.h>
 #include <linux/usb/gadget.h>
 
+#include <linux/delay.h>
+#include <linux/time.h>
 
 /*
  * The gadgetfs API maps each endpoint to a file descriptor so that you
@@ -81,6 +83,9 @@ MODULE_DESCRIPTION (DRIVER_DESC);
 MODULE_AUTHOR ("David Brownell");
 MODULE_LICENSE ("GPL");
 
+/* Cancel IO, To store the bulkin and bulkout ep data. */
+static struct ep_data *gp_ep_bulkin_data;
+static struct ep_data *gp_ep_bulkout_data;
 
 /*----------------------------------------------------------------------*/
 
@@ -265,6 +270,10 @@ static const char *CHIP;
 #define INFO(dev,fmt,args...) \
 	xprintk(dev , KERN_INFO , fmt , ## args)
 
+/* Cancel IO */
+static int mtp_ctrl_cmd;
+static int gbCancelFlag;
+static unsigned long mtptimestamp;
 
 /*----------------------------------------------------------------------*/
 
@@ -275,6 +284,17 @@ static const char *CHIP;
  * precise FIFO status when recovering from cancellation.
  */
 
+/* Cancel IO */
+static void cancel_io_process(struct work_struct *work)
+{
+	if (gp_ep_bulkout_data->req->status == -EINPROGRESS)
+		usb_ep_dequeue(gp_ep_bulkout_data->ep, gp_ep_bulkout_data->req);
+
+	if (gp_ep_bulkin_data->req->status == -EINPROGRESS)
+		usb_ep_dequeue(gp_ep_bulkin_data->ep, gp_ep_bulkin_data->req);
+}
+static DECLARE_DELAYED_WORK(cancel_work, cancel_io_process);
+
 static void epio_complete (struct usb_ep *ep, struct usb_request *req)
 {
 	struct ep_data	*epdata = ep->driver_data;
@@ -868,6 +888,8 @@ ep_open (struct inode *inode, struct file *fd)
 {
 	struct ep_data		*data = inode->i_private;
 	int			value = -EBUSY;
+	char *epin = "ep1in";
+	char *epout = "ep1out";
 
 	if (down_interruptible (&data->lock) != 0)
 		return -EINTR;
@@ -880,6 +902,12 @@ ep_open (struct inode *inode, struct file *fd)
 		get_ep (data);
 		fd->private_data = data;
 		VDEBUG (data->dev, "%s ready\n", data->name);
+		/* Cancel IO */
+		if (0 == strcmp(data->name, epin))
+			gp_ep_bulkin_data = fd->private_data;
+
+		if (0 == strcmp(data->name, epout))
+			gp_ep_bulkout_data = fd->private_data;
 	} else
 		DBG (data->dev, "%s state %d\n",
 			data->name, data->state);
@@ -1043,8 +1071,12 @@ ep0_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr)
 // FIXME don't call this with the spinlock held ...
 				if (copy_to_user (buf, dev->req->buf, len))
 					retval = -EFAULT;
+				else
+					/* Bug of Cancel IO 6 bytes read. */
+					retval = len;
 				clean_req (dev->gadget->ep0, dev->req);
 				/* NOTE userspace can't yet choose to stall */
+				dev->state = STATE_DEV_CONNECTED;	/* Cancel IO */
 			}
 		}
 		goto done;
@@ -1058,6 +1090,12 @@ ep0_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr)
 	len -= len % sizeof (struct usb_gadgetfs_event);
 	dev->usermode_setup = 1;
 
+    /* Cancel IO, signal abort blocked IO. */
+	if (mtp_ctrl_cmd == 1) {
+		mtp_ctrl_cmd = 0;
+		schedule_delayed_work(&cancel_work, HZ / 100);
+	}
+
 scan:
 	/* return queued events right away */
 	if (dev->ev_next != 0) {
@@ -1384,6 +1422,16 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
 	struct usb_gadgetfs_event	*event;
 	u16				w_value = le16_to_cpu(ctrl->wValue);
 	u16				w_length = le16_to_cpu(ctrl->wLength);
+	struct timeval tv;
+
+    /* Cancel IO */
+	if (0x67 == ctrl->bRequest && 1 == gbCancelFlag
+	    && dev->state == STATE_DEV_SETUP)
+		dev->state = STATE_DEV_CONNECTED;
+
+	if (0x67 == ctrl->bRequest && 2 == mtp_ctrl_cmd
+	    && dev->state == STATE_DEV_SETUP)
+		dev->state = STATE_DEV_CONNECTED;
 
 	spin_lock (&dev->lock);
 	dev->setup_abort = 0;
@@ -1411,6 +1459,11 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
 	 */
 	} else if (dev->state == STATE_DEV_SETUP)
 		dev->setup_abort = 1;
+	/*Cancel IO */
+	if (mtp_ctrl_cmd == 1 && gbCancelFlag == 1 && dev->setup_abort == 1) {
+		INFO(dev, "0x64->setup\n");
+		dev->setup_abort = 0;
+	}
 
 	req->buf = dev->rbuf;
 	req->dma = DMA_ADDR_INVALID;
@@ -1543,11 +1596,63 @@ delegate:
 				/* we can't currently stall these */
 				dev->setup_can_stall = 0;
 			}
+			/* Cancel IO */
+			if (0x67 == ctrl->bRequest && 1 == gbCancelFlag) {
+				gbCancelFlag = 0;
+
+				setup_req(gadget->ep0, dev->req, 4);
+				*(unsigned long *)dev->req->buf = 0x20190004;
+				usb_ep_queue(gadget->ep0, dev->req, GFP_ATOMIC);
+
+				spin_unlock(&dev->lock);
+				return 0;
+			}
+			if (ctrl->bRequest == 0x67 && mtp_ctrl_cmd == 2) {
+				/* get status */
+				mtp_ctrl_cmd = 0;
+			}
 
 			/* state changes when reader collects event */
 			event = next_event (dev, GADGETFS_SETUP);
 			event->u.setup = *ctrl;
+			/*  Cancel IO */
+			if (0x64 == ctrl->bRequest) {
+				mtp_ctrl_cmd = 1;
+				gbCancelFlag = 1;
+
+				/* get the timestamp */
+				do_gettimeofday(&tv);
+				mtptimestamp = tv.tv_usec;
+				event->u.setup.wValue =
+				    (unsigned short)tv.tv_usec;
+			}
+			if (0x66 == ctrl->bRequest) {
+				/* get the timestamp */
+				do_gettimeofday(&tv);
+				mtptimestamp = tv.tv_usec;
+				event->u.setup.wValue =
+				    (unsigned short)tv.tv_usec;
+			}
+
 			ep0_readable (dev);
+			/* Reset request. */
+			if (ctrl->bRequest == 0x66) {	/* reset ,send ZLP */
+				mtp_ctrl_cmd = 2;
+
+				if (gp_ep_bulkout_data->req->status ==
+				    -EINPROGRESS) {
+					usb_ep_dequeue(gp_ep_bulkout_data->ep,
+						       gp_ep_bulkout_data->req);
+				}
+				if (gp_ep_bulkin_data->req->status ==
+				    -EINPROGRESS) {
+					usb_ep_dequeue(gp_ep_bulkin_data->ep,
+						       gp_ep_bulkin_data->req);
+				}
+			}
+			if (ctrl->bRequest == 0x65)
+				pr_debug("i:0x65,not supported\n");
+
 			spin_unlock (&dev->lock);
 			return 0;
 		}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1a920c70b5a1..6abc0ba016c0 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -59,9 +59,101 @@ config USB_EHCI_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called ehci-hcd.
 
+config USB_EHCI_ARC
+	bool "Support for Freescale controller"
+	depends on USB_EHCI_HCD && (ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS)
+	select USB_OTG_UTILS
+	---help---
+	   Some Freescale processors have an integrated High Speed
+	   USBOTG controller, which supports EHCI host mode.
+
+	   Say "y" here to add support for this controller
+	   to the EHCI HCD driver.
+
+config USB_EHCI_ARC_H1
+	bool "Support for Host1 port on Freescale controller"
+	depends on USB_EHCI_ARC	&& (ARCH_MX27 || ARCH_MX3 || ARCH_MX28)
+	---help---
+	  Enable support for the USB Host1 port.
+
+config USB_EHCI_ARC_H2
+	bool "Support for Host2 port on Freescale controller"
+	depends on USB_EHCI_ARC	&& \
+		   (ARCH_MX25 || ARCH_MX27 || ARCH_MX3 || ARCH_MX35)
+	---help---
+	  Enable support for the USB Host2 port.
+
+config USB_EHCI_ARC_OTG
+	bool "Support for DR host port on Freescale controller"
+	depends on USB_EHCI_ARC
+	default y
+	---help---
+	  Enable support for the USB OTG port in HS/FS Host mode.
+
+config USB_STATIC_IRAM
+	bool "Use IRAM for USB"
+	depends on USB_EHCI_ARC
+	---help---
+	  Enable this option to use IRAM instead of DRAM for USB
+	  structures and buffers.  This option will reduce bus
+	  contention on systems with large (VGA+) framebuffer
+	  devices and heavy USB activity.  There are performance
+	  penalties and usage restrictions when using this option.
+
+	  If in doubt, say N.
+
+choice
+	prompt "Select transceiver for DR port"
+	depends on USB_EHCI_ARC_OTG
+	default USB_EHCI_FSL_1504 if ARCH_MX3
+	default USB_EHCI_FSL_1301 if ARCH_MX27
+	default USB_EHCI_FSL_UTMI if (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51 || ARCH_STMP3XXX || ARCH_MXS)
+	---help---
+	  Choose the transceiver to use with the Freescale DR port.
+
+config USB_EHCI_FSL_MC13783
+	bool "Freescale MC13783"
+	depends on !MACH_MX25_3DS
+	---help---
+	  Enable support for the Full Speed Freescale MC13783 transceiver.
+
+	  The mx27ads, mx31ads and mx32ads boards require modifications
+	  to support this transceiver.
+
+config USB_EHCI_FSL_1301
+	bool "Philips ISP1301"
+	depends on !MACH_MX25_3DS
+	---help---
+	  Enable support for the Full Speed Philips ISP1301 transceiver.
+
+	  This is the factory default for the mx27ads board.
+	  The mx31ads and mx32ads boards require modifications
+	  to support this transceiver.
+
+config USB_EHCI_FSL_1504
+	bool "Philips ISP1504"
+	depends on MACH_MX27ADS || MACH_MX31ADS || MACH_MX32ADS ||MACH_MX31_3DS
+	---help---
+	  Enable support for the High Speed Philips ISP1504 transceiver.
+
+	  This is the factory default for the mx31ads and mx32ads boards.
+	  The mx27ads board requires modifications to support this transceiver.
+
+config USB_EHCI_FSL_UTMI
+	bool "Internal UTMI"
+	depends on (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51 || ARCH_STMP3XXX || ARCH_MXS)
+	---help---
+	  Enable support for the on-chip High Speed UTMI transceiver.
+
+	  This is the factory default for the mx35ads board.
+
+endchoice
+
+
 config USB_EHCI_ROOT_HUB_TT
 	bool "Root Hub Transaction Translators"
 	depends on USB_EHCI_HCD
+	default y if USB_EHCI_ARC
 	---help---
 	  Some EHCI chips have vendor-specific extensions to integrate
 	  transaction translators, so that no OHCI or UHCI companion
@@ -308,7 +400,7 @@ config USB_SL811_HCD
 	help
 	  The SL811HS is a single-port USB controller that supports either
 	  host side or peripheral side roles.  Enable this option if your
-	  board has this chip, and you want to use it as a host controller. 
+	  board has this chip, and you want to use it as a host controller.
 	  If unsure, say N.
 
 	  To compile this driver as a module, choose M here: the
diff --git a/drivers/usb/host/ehci-arc.c b/drivers/usb/host/ehci-arc.c
new file mode 100644
index 000000000000..21133fb8e47a
--- /dev/null
+++ b/drivers/usb/host/ehci-arc.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2005 MontaVista Software
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
+ * by Hunter Wu.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/usb/otg.h>
+
+#include "ehci-fsl.h"
+#include <mach/fsl_usb.h>
+
+#undef EHCI_PROC_PTC
+#ifdef EHCI_PROC_PTC		/* /proc PORTSC:PTC support */
+/*
+ * write a PORTSC:PTC value to /proc/driver/ehci-ptc
+ * to put the controller into test mode.
+ */
+#include <linux/proc_fs.h>
+#include <asm/uaccess.h>
+#define EFPSL 3			/* ehci fsl proc string length */
+
+static int ehci_fsl_proc_read(char *page, char **start, off_t off, int count,
+			      int *eof, void *data)
+{
+	return 0;
+}
+
+static int ehci_fsl_proc_write(struct file *file, const char __user *buffer,
+			       unsigned long count, void *data)
+{
+	int ptc;
+	u32 portsc;
+	struct ehci_hcd *ehci = (struct ehci_hcd *) data;
+	char str[EFPSL] = {0};
+
+	if (count > EFPSL-1)
+		return -EINVAL;
+
+	if (copy_from_user(str, buffer, count))
+		return -EFAULT;
+
+	str[count] = '\0';
+
+	ptc = simple_strtoul(str, NULL, 0);
+
+	portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
+	portsc &= ~(0xf << 16);
+	portsc |= (ptc << 16);
+	printk(KERN_INFO "PTC %x  portsc %08x\n", ptc, portsc);
+
+	ehci_writel(ehci, portsc, &ehci->regs->port_status[0]);
+
+	return count;
+}
+
+static int ehci_testmode_init(struct ehci_hcd *ehci)
+{
+	struct proc_dir_entry *entry;
+
+	entry = create_proc_read_entry("driver/ehci-ptc", 0644, NULL,
+				       ehci_fsl_proc_read, ehci);
+	if (!entry)
+		return -ENODEV;
+
+	entry->write_proc = ehci_fsl_proc_write;
+	return 0;
+}
+#else
+static int ehci_testmode_init(struct ehci_hcd *ehci)
+{
+	return 0;
+}
+#endif	/* /proc PORTSC:PTC support */
+
+
+/* configure so an HC device and id are always provided */
+/* always called with process context; sleeping is OK */
+
+/**
+ * usb_hcd_fsl_probe - initialize FSL-based HCDs
+ * @drvier: Driver to be used for this HCD
+ * @pdev: USB Host Controller being probed
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller.
+ *
+ */
+int usb_hcd_fsl_probe(const struct hc_driver *driver,
+		      struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata;
+	struct usb_hcd *hcd;
+	struct resource *res;
+	int irq;
+	int retval;
+
+	pr_debug("initializing FSL-SOC USB Controller\n");
+
+	/* Need platform data for setup */
+	pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev,
+			"No platform data for %s.\n", dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+
+	/*
+	 * This is a host mode driver, verify that we're supposed to be
+	 * in host mode.
+	 */
+	if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
+	      (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
+	      (pdata->operating_mode == FSL_USB2_DR_OTG))) {
+		dev_err(&pdev->dev,
+			"Non Host Mode configured for %s. Wrong driver linked.\n",
+			dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+
+	hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		retval = -ENOMEM;
+		goto err1;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev,
+			"Found HC with no IRQ. Check %s setup!\n",
+			dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+	irq = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	if (pdata->operating_mode != FSL_USB2_DR_OTG) {
+		if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+					driver->description)) {
+			dev_dbg(&pdev->dev, "controller already in use\n");
+			retval = -EBUSY;
+			goto err2;
+		}
+	}
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+
+	if (hcd->regs == NULL) {
+		dev_dbg(&pdev->dev, "error mapping memory\n");
+		retval = -EFAULT;
+		goto err3;
+	}
+	pdata->regs = hcd->regs;
+
+	/*
+	 * do platform specific init: check the clock, grab/config pins, etc.
+	 */
+	if (pdata->platform_init && pdata->platform_init(pdev)) {
+		retval = -ENODEV;
+		goto err3;
+	}
+
+	fsl_platform_set_host_mode(hcd);
+	hcd->power_budget = pdata->power_budget;
+
+	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+	if (retval != 0)
+		goto err4;
+
+	fsl_platform_set_vbus_power(pdata, 1);
+
+	if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+		struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+		dbg("pdev=0x%p  hcd=0x%p  ehci=0x%p\n", pdev, hcd, ehci);
+
+		ehci->transceiver = otg_get_transceiver();
+		dbg("ehci->transceiver=0x%p\n", ehci->transceiver);
+
+		if (!ehci->transceiver) {
+			printk(KERN_ERR "can't find transceiver\n");
+			retval = -ENODEV;
+			goto err4;
+		}
+
+		retval = otg_set_host(ehci->transceiver, &ehci_to_hcd(ehci)->self);
+		if (retval)
+			otg_put_transceiver(ehci->transceiver);
+	}
+
+	if (pdata->suspended) {
+		pdata->suspended = 0;
+		if (pdata->already_suspended)
+			pdata->already_suspended = 0;
+	}
+
+	fsl_platform_set_ahb_burst(hcd);
+	ehci_testmode_init(hcd_to_ehci(hcd));
+	return retval;
+
+err4:
+	iounmap(hcd->regs);
+err3:
+	if (pdata->operating_mode != FSL_USB2_DR_OTG)
+		release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err2:
+	usb_put_hcd(hcd);
+err1:
+	dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
+	if (pdata->platform_uninit)
+		pdata->platform_uninit(pdata);
+	return retval;
+}
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/**
+ * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
+ * @dev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_fsl_probe().
+ *
+ */
+static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
+			       struct platform_device *pdev)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	u32 tmp;
+
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		/* Need open clock for register access */
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(true);
+
+		tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+		if (tmp & PORT_PHCD) {
+			tmp &= ~PORT_PHCD;
+			ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
+			msleep(100);
+
+			if (pdata->usb_clock_for_pm)
+				pdata->usb_clock_for_pm(false);
+		}
+	}
+
+	/* DDD shouldn't we turn off the power here? */
+	fsl_platform_set_vbus_power(pdata, 0);
+
+	if (ehci->transceiver) {
+		(void)otg_set_host(ehci->transceiver, 0);
+		otg_put_transceiver(ehci->transceiver);
+	} else {
+		release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	}
+
+	usb_remove_hcd(hcd);
+	usb_put_hcd(hcd);
+
+	/*
+	 * do platform specific un-initialization:
+	 * release iomux pins, etc.
+	 */
+	if (pdata->platform_uninit)
+		pdata->platform_uninit(pdata);
+
+	iounmap(hcd->regs);
+}
+
+static void fsl_setup_phy(struct ehci_hcd *ehci,
+			  enum fsl_usb2_phy_modes phy_mode, int port_offset)
+{
+	u32 portsc;
+
+	portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
+	portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
+
+	switch (phy_mode) {
+	case FSL_USB2_PHY_ULPI:
+		portsc |= PORT_PTS_ULPI;
+		break;
+	case FSL_USB2_PHY_SERIAL:
+		portsc |= PORT_PTS_SERIAL;
+		break;
+	case FSL_USB2_PHY_UTMI_WIDE:
+		portsc |= PORT_PTS_PTW;
+		/* fall through */
+	case FSL_USB2_PHY_UTMI:
+		portsc |= PORT_PTS_UTMI;
+		break;
+	case FSL_USB2_PHY_NONE:
+		break;
+	}
+	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
+}
+
+/* called after powerup, by probe or system-pm "wakeup" */
+static int ehci_fsl_reinit(struct ehci_hcd *ehci)
+{
+	fsl_platform_usb_setup(ehci);
+	ehci_port_power(ehci, 0);
+
+	return 0;
+}
+
+/* called during probe() after chip reset completes */
+static int ehci_fsl_setup(struct usb_hcd *hcd)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	int retval;
+
+	/* EHCI registers start at offset 0x100 */
+	ehci->caps = hcd->regs + 0x100;
+	ehci->regs = hcd->regs + 0x100 +
+	    HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+	dbg_hcs_params(ehci, "reset");
+	dbg_hcc_params(ehci, "reset");
+
+	/* cache this readonly data; minimize chip reads */
+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+	retval = ehci_halt(ehci);
+	if (retval)
+		return retval;
+
+	/* data structure init */
+	retval = ehci_init(hcd);
+	if (retval)
+		return retval;
+
+	hcd->has_tt = 1;
+
+	ehci->sbrn = 0x20;
+
+	ehci_reset(ehci);
+
+	retval = ehci_fsl_reinit(ehci);
+	return retval;
+}
+
+static const struct hc_driver ehci_fsl_hc_driver = {
+	.description = hcd_name,
+	.product_desc = "Freescale On-Chip EHCI Host Controller",
+	.hcd_priv_size = sizeof(struct ehci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq = ehci_irq,
+	.flags = HCD_USB2,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.reset = ehci_fsl_setup,
+	.start = ehci_run,
+	.stop = ehci_stop,
+	.shutdown = ehci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue = ehci_urb_enqueue,
+	.urb_dequeue = ehci_urb_dequeue,
+	.endpoint_disable = ehci_endpoint_disable,
+	.endpoint_reset = ehci_endpoint_reset,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number = ehci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data = ehci_hub_status_data,
+	.hub_control = ehci_hub_control,
+	.bus_suspend = ehci_bus_suspend,
+	.bus_resume = ehci_bus_resume,
+	.start_port_reset = ehci_start_port_reset,
+	.relinquish_port = ehci_relinquish_port,
+	.port_handed_over = ehci_port_handed_over,
+
+	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static int ehci_fsl_drv_probe(struct platform_device *pdev)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	/* FIXME we only want one one probe() not two */
+	return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
+}
+
+static int ehci_fsl_drv_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	/* FIXME we only want one one remove() not two */
+	usb_hcd_fsl_remove(hcd, pdev);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/* suspend/resume, section 4.3 */
+
+/* These routines rely on the bus (pci, platform, etc)
+ * to handle powerdown and wakeup, and currently also on
+ * transceivers that don't need any software attention to set up
+ * the right sort of wakeup.
+ *
+ * They're also used for turning on/off the port when doing OTG.
+ */
+static int ehci_fsl_drv_suspend(struct platform_device *pdev,
+				pm_message_t message)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	u32 tmp, port_status;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	if (device_may_wakeup(&(pdev->dev))) {
+		/* Need open clock for register access */
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(true);
+	}
+
+#ifdef DEBUG
+	u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
+	mode &= USBMODE_CM_MASK;
+	tmp = ehci_readl(ehci, hcd->regs + 0x140);	/* usbcmd */
+
+	printk(KERN_DEBUG "%s('%s'): suspend=%d already_suspended=%d "
+	       "mode=%d  usbcmd %08x\n", __func__, pdata->name,
+	       pdata->suspended, pdata->already_suspended, mode, tmp);
+#endif
+
+	/*
+	 * If the controller is already suspended, then this must be a
+	 * PM suspend.  Remember this fact, so that we will leave the
+	 * controller suspended at PM resume time.
+	 */
+	if (pdata->suspended) {
+		pr_debug("%s: already suspended, leaving early\n", __func__);
+		pdata->already_suspended = 1;
+		goto err1;
+	}
+
+	pr_debug("%s: suspending...\n", __func__);
+
+	printk(KERN_INFO "USB Host suspended\n");
+
+	port_status = ehci_readl(ehci, &ehci->regs->port_status[0]);
+	pdev->dev.power.power_state = PMSG_SUSPEND;
+
+	/* ignore non-host interrupts */
+	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+	/* save EHCI registers */
+	pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
+	pdata->pm_command &= ~CMD_RUN;
+	pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
+	pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
+	pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
+	pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
+	pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
+	pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
+	pdata->pm_configured_flag  =
+		ehci_readl(ehci, &ehci->regs->configured_flag);
+	pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
+
+	/* clear the W1C bits */
+	pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
+
+	/* clear PHCD bit */
+	pdata->pm_portsc &= ~PORT_PHCD;
+
+	pdata->suspended = 1;
+
+	if (!device_may_wakeup(&(pdev->dev))) {
+		/* clear PP to cut power to the port */
+		tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+		tmp &= ~PORT_POWER;
+		ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
+		goto err1;
+	}
+
+	tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+
+	if (pdata->platform_suspend)
+		pdata->platform_suspend(pdata);
+err1:
+	if (device_may_wakeup(&(pdev->dev))) {
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(false);
+	}
+	return 0;
+}
+
+static int ehci_fsl_drv_resume(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	u32 tmp;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	pr_debug("%s('%s'): suspend=%d already_suspended=%d\n", __func__,
+		pdata->name, pdata->suspended, pdata->already_suspended);
+
+	/*
+	 * If the controller was already suspended at suspend time,
+	 * then don't resume it now.
+	 */
+	if (pdata->already_suspended) {
+		pr_debug("already suspended, leaving early\n");
+		pdata->already_suspended = 0;
+		return 0;
+	}
+
+	if (!pdata->suspended) {
+		pr_debug("not suspended, leaving early\n");
+		return 0;
+	}
+
+	/* If hcd is resumed by non-usb wakeup events,
+	 * then usb clocks are still not open when come here */
+	if (device_may_wakeup(&(pdev->dev))) {
+		/* Need open clock for register access */
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(true);
+	}
+
+	tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+
+	pdata->suspended = 0;
+
+	pr_debug("%s resuming...\n", __func__);
+
+	/* set host mode */
+	fsl_platform_set_host_mode(hcd);
+
+	if (pdata->platform_resume)
+		pdata->platform_resume(pdata);
+
+	/* restore EHCI registers */
+	ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
+	ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
+	ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
+	ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
+	ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
+	ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
+	ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
+	ehci_writel(ehci, pdata->pm_configured_flag,
+		    &ehci->regs->configured_flag);
+
+	/* set bit should be done by wakeup irq routine if may wakeup */
+	if (!device_may_wakeup(&(pdev->dev)))
+		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+	else
+		while (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
+			msleep(1);
+
+	pdev->dev.power.power_state = PMSG_ON;
+
+	tmp = ehci_readl(ehci, &ehci->regs->command);
+	tmp |= CMD_RUN;
+	ehci_writel(ehci, tmp, &ehci->regs->command);
+
+	usb_hcd_resume_root_hub(hcd);
+
+	printk(KERN_INFO "USB Host resumed\n");
+
+	if (device_may_wakeup(&(pdev->dev))) {
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(false);
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_USB_OTG */
+
+MODULE_ALIAS("platform:fsl-ehci");
+
+static struct platform_driver ehci_fsl_driver = {
+	.probe = ehci_fsl_drv_probe,
+	.remove = ehci_fsl_drv_remove,
+	.shutdown = usb_hcd_platform_shutdown,
+#ifdef CONFIG_PM
+	.suspend = ehci_fsl_drv_suspend,
+	.resume = ehci_fsl_drv_resume,
+#endif
+	.driver = {
+		   .name = "fsl-ehci",
+	},
+};
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index b5e59db53347..8a12eec68a90 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,6 +19,9 @@
 #define _EHCI_FSL_H
 
 /* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_SBUSCFG     0x90
+#define FSL_SOC_USB_BURSTSIZE	0x160
+#define FSL_SOC_USB_TXFILLTUNING	0x164
 #define FSL_SOC_USB_ULPIVP	0x170
 #define FSL_SOC_USB_PORTSC1	0x184
 #define PORT_PTS_MSK		(3<<30)
@@ -26,8 +29,12 @@
 #define PORT_PTS_ULPI		(2<<30)
 #define	PORT_PTS_SERIAL		(3<<30)
 #define PORT_PTS_PTW		(1<<28)
+#define PORT_PTS_PHCD		(1<<23)
 #define FSL_SOC_USB_PORTSC2	0x188
 #define FSL_SOC_USB_USBMODE	0x1a8
+#define USBMODE_CM_HOST		(3 << 0)	/* controller mode: host */
+#define USBMODE_ES		(1 << 2)	/* (Big) Endian Select */
+
 #define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
 #define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
 #define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 11c627ce6022..1a9266e7e798 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -289,8 +289,13 @@ static void end_unlink_async(struct ehci_hcd *ehci);
 static void ehci_work(struct ehci_hcd *ehci);
 
 #include "ehci-hub.c"
+#ifdef CONFIG_USB_STATIC_IRAM
+#include "ehci-mem-iram.c"
+#include "ehci-q-iram.c"
+#else
 #include "ehci-mem.c"
 #include "ehci-q.c"
+#endif
 #include "ehci-sched.c"
 
 /*-------------------------------------------------------------------------*/
@@ -1097,6 +1102,11 @@ MODULE_LICENSE ("GPL");
 #define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
 #endif
 
+#ifdef CONFIG_USB_EHCI_ARC
+#include "ehci-arc.c"
+#define	PLATFORM_DRIVER		ehci_fsl_driver
+#endif
+
 #ifdef CONFIG_PPC_PS3
 #include "ehci-ps3.c"
 #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index f46ad27c9a90..de459bbd1eb1 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -151,9 +151,12 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
 		}
 
 		/* enable remote wakeup on all ports */
-		if (hcd->self.root_hub->do_remote_wakeup)
-			t2 |= PORT_WAKE_BITS;
-		else
+		if (hcd->self.root_hub->do_remote_wakeup) {
+			if (t1 & PORT_CONNECT)
+				t2 |= PORT_WKOC_E|PORT_WKDISC_E;
+			else
+				t2 |= PORT_WKOC_E|PORT_WKCONN_E;
+		} else
 			t2 &= ~PORT_WAKE_BITS;
 
 		if (t1 != t2) {
@@ -549,6 +552,37 @@ ehci_hub_descriptor (
 	desc->wHubCharacteristics = cpu_to_le16(temp);
 }
 
+#ifdef CONFIG_USB_OTG
+static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	u32 status;
+
+	if (!port)
+		return -EINVAL;
+	port--;
+
+	/* start port reset before HNP protocol time out */
+	status = readl(&ehci->regs->port_status[port]);
+	if (!(status & PORT_CONNECT))
+		return -ENODEV;
+
+	/* khubd will finish the reset later */
+	if (ehci_is_TDI(ehci))
+		writel(PORT_RESET | (status & ~(PORT_CSC | PORT_PEC
+				| PORT_OCC)), &ehci->regs->port_status[port]);
+	else
+		writel(PORT_RESET, &ehci->regs->port_status[port]);
+
+	return 0;
+}
+#else
+static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
+{
+	return 0;
+}
+#endif /* CONFIG_USB_OTG */
+
 /*-------------------------------------------------------------------------*/
 
 static int ehci_hub_control (
diff --git a/drivers/usb/host/ehci-mem-iram.c b/drivers/usb/host/ehci-mem-iram.c
new file mode 100644
index 000000000000..fd7b42b22758
--- /dev/null
+++ b/drivers/usb/host/ehci-mem-iram.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2001 by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* this file is part of ehci-hcd.c */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * There's basically three types of memory:
+ *	- data used only by the HCD ... kmalloc is fine
+ *	- async and periodic schedules, shared by HC and HCD ... these
+ *	  need to use dma_pool or dma_alloc_coherent
+ *	- driver buffers, read/written by HC ... single shot DMA mapped
+ *
+ * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
+ * No memory seen by this driver is pageable.
+ */
+
+/*-------------------------------------------------------------------------*/
+
+/* Allocate the key transfer structures from the previously allocated pool */
+#include <linux/smp_lock.h>
+#include <linux/iram_alloc.h>
+
+bool use_iram_qtd;
+
+struct memDesc {
+	u32 start;
+	u32 end;
+	struct memDesc *next;
+} ;
+
+static u32 g_usb_pool_start;
+static s32 g_usb_pool_count;
+static u32 g_total_pages;
+static u32 g_alignment = 32;
+struct memDesc *g_allocated_desc;
+static spinlock_t g_usb_sema;
+static u32 g_debug_qtd_allocated;
+static u32 g_debug_qH_allocated;
+static int g_alloc_map;
+static unsigned long g_iram_base;
+static __iomem void *g_iram_addr;
+
+/*!
+ * usb_pool_initialize
+ *
+ * @param       memPool         start address of the pool
+ * @param       poolSize        memory pool size
+ * @param       alignment       alignment for example page alignmnet will be 4K
+ *
+ * @return      0 for success  -1 for errors
+ */
+static int usb_pool_initialize(u32 memPool, u32 poolSize, u32 alignment)
+{
+	if (g_usb_pool_count) {
+		printk(KERN_INFO "usb_pool_initialize : already initialzed.\n");
+		return 0;
+	}
+
+	g_alignment = alignment;
+	if (g_alignment == 0) {
+		printk(KERN_INFO
+		       "usb_pool_initialize : g_alignment can not be zero.\n");
+		g_alignment = 32;
+	}
+
+	g_total_pages = poolSize / g_alignment;
+	g_usb_pool_start = (u32) memPool;
+
+	g_allocated_desc = kmalloc(sizeof(struct memDesc), GFP_KERNEL);
+	if (!g_allocated_desc) {
+		printk(KERN_ALERT "usb_pool_initialize : kmalloc failed \n");
+		return (-1);
+	}
+
+	g_allocated_desc->start = 0;
+	g_allocated_desc->end = 0;
+	g_allocated_desc->next = NULL;
+
+	spin_lock_init(&g_usb_sema);
+	g_usb_pool_count++;
+	return (0);
+}
+
+static void usb_pool_deinit()
+{
+	if (--g_usb_pool_count < 0)
+		g_usb_pool_count = 0;
+}
+
+/*!
+ * usb_malloc
+ *
+ * @param       size        memory pool size
+ *
+ * @return      physical address, 0 for error
+ */
+static u32 usb_malloc(u32 size, gfp_t mem_flags)
+{
+	unsigned long flags;
+	struct memDesc *prevDesc = NULL;
+	struct memDesc *nextDesc = NULL;
+	struct memDesc *currentDesc = NULL;
+	u32 pages = (size + g_alignment - 1) / g_alignment;
+
+	if ((size == 0) || (pages > g_total_pages))
+		return 0;
+
+	currentDesc = kmalloc(sizeof(struct memDesc), mem_flags);
+	if (!currentDesc) {
+		printk(KERN_ALERT "usb_malloc: kmalloc failed \n");
+		return 0;
+	}
+
+	spin_lock_irqsave(&g_usb_sema, flags);
+
+	/* Create the first Allocated descriptor */
+	if (!g_allocated_desc->next) {
+		g_allocated_desc->next = currentDesc;
+		currentDesc->start = 0;
+		currentDesc->end = pages;
+		currentDesc->next = NULL;
+		spin_unlock_irqrestore(&g_usb_sema, flags);
+		return (g_usb_pool_start + currentDesc->start * g_alignment);
+	}
+
+	/* Find the free spot */
+	prevDesc = g_allocated_desc;
+	while (prevDesc->next) {
+		nextDesc = prevDesc->next;
+		if (pages <= nextDesc->start - prevDesc->end) {
+			currentDesc->start = prevDesc->end;
+			currentDesc->end = currentDesc->start + pages;
+			currentDesc->next = nextDesc;
+			prevDesc->next = currentDesc;
+			break;
+		}
+		prevDesc = nextDesc;
+	}
+
+	/* Do not find the free spot inside the chain, append to the end */
+	if (!prevDesc->next) {
+		if (pages > (g_total_pages - prevDesc->end)) {
+			spin_unlock_irqrestore(&g_usb_sema, flags);
+			kfree(currentDesc);
+			return 0;
+		} else {
+			currentDesc->start = prevDesc->end;
+			currentDesc->end = currentDesc->start + pages;
+			currentDesc->next = NULL;
+			prevDesc->next = currentDesc;
+		}
+	}
+
+	spin_unlock_irqrestore(&g_usb_sema, flags);
+	return (g_usb_pool_start + currentDesc->start * g_alignment);
+}
+
+/*!
+ * usb_free
+ *
+ * @param       physical        physical address try to free
+ *
+ */
+static void usb_free(u32 physical)
+{
+	unsigned long flags;
+	struct memDesc *prevDesc = NULL;
+	struct memDesc *nextDesc = NULL;
+	u32 pages = (physical - g_usb_pool_start) / g_alignment;
+
+	/* Protect the memory pool data structures. */
+	spin_lock_irqsave(&g_usb_sema, flags);
+
+	prevDesc = g_allocated_desc;
+	while (prevDesc->next) {
+		nextDesc = prevDesc->next;
+		if (nextDesc->start == pages) {
+			prevDesc->next = nextDesc->next;
+			kfree(nextDesc);
+			break;
+		}
+		prevDesc = prevDesc->next;
+	}
+	/* All done with memory pool data structures. */
+	spin_unlock_irqrestore(&g_usb_sema, flags);
+}
+
+static int address_to_buffer(struct ehci_hcd *ehci, int address)
+{
+	int i;
+
+	for (i = 0; i < IRAM_NTD; i++) {
+		if (ehci->usb_address[i] == address)
+			return i;
+	}
+	return IRAM_NTD;
+}
+
+static void use_buffer(struct ehci_hcd *ehci, int address)
+{
+	int i;
+
+	for (i = 0; i < IRAM_NTD; i++) {
+		if (ehci->usb_address[i] == address)
+			return;
+	}
+
+	if (ehci->usb_address[0] == 0) {
+		ehci->usb_address[0] = address;
+		printk(KERN_INFO "usb_address[0] %x\n", address);
+		return;
+	} else if (ehci->usb_address[1] == 0) {
+		ehci->usb_address[1] = address;
+		printk(KERN_INFO "usb_address[1] %x\n", address);
+		return;
+	} else
+		printk(KERN_ALERT "qh_make run out of iRAM, already be used");
+}
+
+static u32 alloc_iram_buf(void)
+{
+	int i;
+
+	for (i = 0; i < IRAM_NTD; i++) {
+		if (!(g_alloc_map & (1 << i))) {
+			g_alloc_map |= (1 << i);
+			return g_iram_base + i * (IRAM_TD_SIZE * 2);
+		}
+	}
+	panic("Out of IRAM buffers\n");
+}
+
+void free_iram_buf(u32 buf)
+{
+	int i = (buf - g_iram_base) / (IRAM_TD_SIZE * 2);
+
+	g_alloc_map &= ~(1 << i);
+}
+
+static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
+				 dma_addr_t dma)
+{
+	memset(qtd, 0, sizeof *qtd);
+	qtd->qtd_dma = dma;
+	qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
+	qtd->hw_next = EHCI_LIST_END(ehci);
+	qtd->hw_alt_next = EHCI_LIST_END(ehci);
+	INIT_LIST_HEAD(&qtd->qtd_list);
+}
+
+static struct ehci_qtd *ehci_qtd_alloc(struct ehci_hcd *ehci, gfp_t flags)
+{
+	struct ehci_qtd *qtd;
+	dma_addr_t dma;
+
+	if (use_iram_qtd) {
+		dma = usb_malloc(sizeof(struct ehci_qtd), flags);
+		if (dma != 0)
+			qtd = (struct ehci_qtd *)(g_iram_addr + (dma - g_iram_base));
+		else
+			qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma);
+	}
+	else
+		qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma);
+
+	if (qtd != NULL) {
+		ehci_qtd_init(ehci, qtd, dma);
+		++g_debug_qtd_allocated;
+	} else {
+		panic
+		    ("out of i-ram for qtd allocation g_debug_qtd_allocated %d \
+			size%d \n", g_debug_qtd_allocated,
+			sizeof(struct ehci_qtd));
+	}
+	return qtd;
+}
+
+static inline void ehci_qtd_free(struct ehci_hcd *ehci, struct ehci_qtd *qtd)
+{
+	if ((qtd->qtd_dma & (g_iram_base & 0xFFF00000)) ==
+	    (g_iram_base & 0xFFF00000))
+		usb_free(qtd->qtd_dma);
+	else
+		dma_pool_free(ehci->qtd_pool, qtd, qtd->qtd_dma);
+	--g_debug_qtd_allocated;
+}
+
+static void qh_destroy(struct ehci_qh *qh)
+{
+	struct ehci_hcd *ehci = qh->ehci;
+
+	/* clean qtds first, and know this is not linked */
+	if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
+		ehci_dbg(ehci, "unused qh not empty!\n");
+		BUG();
+	}
+	if (qh->dummy)
+		ehci_qtd_free(ehci, qh->dummy);
+	int i;
+	for (i = 0; i < IRAM_NTD; i++) {
+		if (ehci->usb_address[i] == (qh->hw_info1 & 0x7F))
+			ehci->usb_address[i] = 0;
+	}
+
+	if ((qh->qh_dma & (g_iram_base & 0xFFF00000)) ==
+	    (g_iram_base & 0xFFF00000))
+		usb_free(qh->qh_dma);
+	else
+		dma_pool_free(ehci->qh_pool, qh, qh->qh_dma);
+	--g_debug_qH_allocated;
+}
+
+static struct ehci_qh *ehci_qh_alloc(struct ehci_hcd *ehci, gfp_t flags)
+{
+	struct ehci_qh *qh;
+	dma_addr_t dma;
+
+	dma = usb_malloc(sizeof(struct ehci_qh), flags);
+	if (dma != 0)
+		qh = (struct ehci_qh *)(g_iram_addr + (dma - g_iram_base));
+	else
+		qh = (struct ehci_qh *)
+		    dma_pool_alloc(ehci->qh_pool, flags, &dma);
+	++g_debug_qH_allocated;
+	if (qh == NULL) {
+		panic("run out of i-ram for qH allocation\n");
+		return qh;
+	}
+
+	memset(qh, 0, sizeof *qh);
+	qh->refcount = 1;
+	qh->ehci = ehci;
+	qh->qh_dma = dma;
+	INIT_LIST_HEAD(&qh->qtd_list);
+
+	/* dummy td enables safe urb queuing */
+	qh->dummy = ehci_qtd_alloc(ehci, flags);
+	if (qh->dummy == NULL) {
+		ehci_dbg(ehci, "no dummy td\n");
+		dma_pool_free(ehci->qh_pool, qh, qh->qh_dma);
+		qh = NULL;
+	}
+	return qh;
+}
+
+/* to share a qh (cpu threads, or hc) */
+static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
+{
+	WARN_ON(!qh->refcount);
+	qh->refcount++;
+	return qh;
+}
+
+static inline void qh_put(struct ehci_qh *qh)
+{
+	if (!--qh->refcount)
+		qh_destroy(qh);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* The queue heads and transfer descriptors are managed from pools tied
+ * to each of the "per device" structures.
+ * This is the initialisation and cleanup code.
+ */
+
+static void ehci_mem_cleanup(struct ehci_hcd *ehci)
+{
+	if (ehci->async)
+		qh_put(ehci->async);
+	ehci->async = NULL;
+
+	/* DMA consistent memory and pools */
+	if (ehci->qtd_pool)
+		dma_pool_destroy(ehci->qtd_pool);
+	ehci->qtd_pool = NULL;
+
+	if (ehci->qh_pool) {
+		dma_pool_destroy(ehci->qh_pool);
+		ehci->qh_pool = NULL;
+	}
+
+	if (ehci->itd_pool)
+		dma_pool_destroy(ehci->itd_pool);
+	ehci->itd_pool = NULL;
+
+	if (ehci->sitd_pool)
+		dma_pool_destroy(ehci->sitd_pool);
+	ehci->sitd_pool = NULL;
+
+	if (ehci->periodic)
+		dma_free_coherent(ehci_to_hcd(ehci)->self.controller,
+				  ehci->periodic_size * sizeof(u32),
+				  ehci->periodic, ehci->periodic_dma);
+	ehci->periodic = NULL;
+
+	if (ehci->iram_buffer[0])
+		free_iram_buf(ehci->iram_buffer[0]);
+	if (ehci->iram_buffer[1])
+		free_iram_buf(ehci->iram_buffer[1]);
+
+	iounmap(g_iram_addr);
+	iram_free(g_iram_base, USB_IRAM_SIZE);
+
+	/* shadow periodic table */
+	kfree(ehci->pshadow);
+	ehci->pshadow = NULL;
+	usb_pool_deinit();
+}
+
+/* remember to add cleanup code (above) if you add anything here */
+static int ehci_mem_init(struct ehci_hcd *ehci, gfp_t flags)
+{
+	int i;
+	g_usb_pool_count = 0;
+	g_debug_qtd_allocated = 0;
+	g_debug_qH_allocated = 0;
+	g_alloc_map = 0;
+
+	if (cpu_is_mx37())
+		use_iram_qtd = 0;
+	else
+		use_iram_qtd = 1;
+
+	g_iram_addr = iram_alloc(USB_IRAM_SIZE, &g_iram_base);
+
+	usb_pool_initialize(g_iram_base + IRAM_TD_SIZE * IRAM_NTD * 2,
+			    USB_IRAM_SIZE - IRAM_TD_SIZE * IRAM_NTD * 2, 32);
+
+	if (!ehci->iram_buffer[0]) {
+		ehci->iram_buffer[0] = alloc_iram_buf();
+		ehci->iram_buffer_v[0] = g_iram_addr + (ehci->iram_buffer[0] - g_iram_base);
+		ehci->iram_buffer[1] = alloc_iram_buf();
+		ehci->iram_buffer_v[1] = g_iram_addr + (ehci->iram_buffer[1] - g_iram_base);
+	}
+
+	/* QTDs for control/bulk/intr transfers */
+	ehci->qtd_pool = dma_pool_create("ehci_qtd",
+					ehci_to_hcd(ehci)->self.controller,
+					sizeof(struct ehci_qtd),
+					32/* byte alignment (for hw parts) */
+					 , 4096 /* can't cross 4K */);
+	if (!ehci->qtd_pool)
+		goto fail;
+
+	/* QHs for control/bulk/intr transfers */
+	ehci->qh_pool = dma_pool_create("ehci_qh",
+					ehci_to_hcd(ehci)->self.controller,
+					sizeof(struct ehci_qh),
+					32 /* byte alignment (for hw parts) */ ,
+					4096 /* can't cross 4K */);
+	if (!ehci->qh_pool)
+		goto fail;
+
+	ehci->async = ehci_qh_alloc(ehci, flags);
+	if (!ehci->async)
+		goto fail;
+
+	/* ITD for high speed ISO transfers */
+	ehci->itd_pool = dma_pool_create("ehci_itd",
+					ehci_to_hcd(ehci)->self.controller,
+					sizeof(struct ehci_itd),
+					32/* byte alignment (for hw parts) */
+					 , 4096 /* can't cross 4K */);
+	if (!ehci->itd_pool)
+		goto fail;
+
+	/* SITD for full/low speed split ISO transfers */
+	ehci->sitd_pool = dma_pool_create("ehci_sitd",
+					ehci_to_hcd(ehci)->self.controller,
+					sizeof(struct ehci_sitd),
+					32/* byte alignment (for hw parts) */
+					  , 4096 /* can't cross 4K */);
+	if (!ehci->sitd_pool)
+		goto fail;
+
+	ehci->periodic = (__le32 *)
+	    dma_alloc_coherent(ehci_to_hcd(ehci)->self.controller,
+			       ehci->periodic_size * sizeof(__le32),
+			       &ehci->periodic_dma, 0);
+
+	if (ehci->periodic == NULL)
+		goto fail;
+
+	for (i = 0; i < ehci->periodic_size; i++)
+		ehci->periodic[i] = EHCI_LIST_END(ehci);
+
+	/* software shadow of hardware table */
+	ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
+	if (ehci->pshadow != NULL)
+		return 0;
+
+fail:
+	ehci_dbg(ehci, "couldn't init memory\n");
+	ehci_mem_cleanup(ehci);
+	return -ENOMEM;
+}
diff --git a/drivers/usb/host/ehci-q-iram.c b/drivers/usb/host/ehci-q-iram.c
new file mode 100644
index 000000000000..318888563380
--- /dev/null
+++ b/drivers/usb/host/ehci-q-iram.c
@@ -0,0 +1,1345 @@
+/*
+ * Copyright (C) 2001-2004 by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#undef EHCI_NO_ERR_COUNT
+static size_t g_iram_size = IRAM_TD_SIZE;
+
+/* this file is part of ehci-hcd.c */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * EHCI hardware queue manipulation ... the core.  QH/QTD manipulation.
+ *
+ * Control, bulk, and interrupt traffic all use "qh" lists.  They list "qtd"
+ * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
+ * buffers needed for the larger number).  We use one QH per endpoint, queue
+ * multiple urbs (all three types) per endpoint.  URBs may need several qtds.
+ *
+ * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with
+ * interrupts) needs careful scheduling.  Performance improvements can be
+ * an ongoing challenge.  That's in "ehci-sched.c".
+ *
+ * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
+ * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
+ * (b) special fields in qh entries or (c) split iso entries.  TTs will
+ * buffer low/full speed data so the host collects it at high speed.
+ */
+
+/*-------------------------------------------------------------------------*/
+/* fill a qtd, returning how much of the buffer we were able to queue up */
+static int qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf,
+		    size_t len, int token, int maxpacket)
+{
+	int i, count;
+	u64 addr = buf;
+	struct urb *urb = qtd->urb;
+
+	if (usb_pipebulk(urb->pipe) &&
+	    (address_to_buffer(ehci, usb_pipedevice(urb->pipe)) != 2)) {
+		urb->use_iram = 1;
+		qtd->buffer_offset = (size_t) (buf - urb->transfer_dma);
+		token |= QTD_IOC;
+		if (usb_pipeout(urb->pipe)) {
+			addr = ehci->iram_buffer[address_to_buffer(ehci,
+						usb_pipedevice(urb->pipe))];
+		} else if (usb_pipein(urb->pipe)) {
+			addr = ehci->iram_buffer[address_to_buffer(ehci,
+						usb_pipedevice(urb->pipe))] +
+						g_iram_size;
+		}
+	} else {
+		urb->use_iram = 0;
+		addr = buf;
+	}
+	len = min(g_iram_size, len);
+
+	/* one buffer entry per 4K ... first might be short or unaligned */
+	qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32) addr);
+	qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32) (addr >> 32));
+	count = 0x1000 - (buf & 0x0fff);	/* rest of that page */
+	if (likely(len < count))	/* ... iff needed */
+		count = len;
+	else {
+		buf += 0x1000;
+		buf &= ~0x0fff;
+
+		/* per-qtd limit: from 16K to 20K (best alignment) */
+		for (i = 1; count < len && i < 5; i++) {
+			addr = buf;
+			qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32) addr);
+			qtd->hw_buf_hi[i] =
+			    cpu_to_hc32(ehci, (u32) (addr >> 32));
+			buf += 0x1000;
+			if ((count + 0x1000) < len)
+				count += 0x1000;
+			else
+				count = len;
+		}
+
+		/* short packets may only terminate transfers */
+		if (count != len)
+			count -= (count % maxpacket);
+	}
+	qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token);
+	qtd->length = count;
+
+	return count;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static inline void
+qh_update(struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd)
+{
+	/* writes to an active overlay are unsafe */
+	BUG_ON(qh->qh_state != QH_STATE_IDLE);
+
+	qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma);
+	qh->hw_alt_next = EHCI_LIST_END(ehci);
+
+	/* Except for control endpoints, we make hardware maintain data
+	 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
+	 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
+	 * ever clear it.
+	 */
+	if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) {
+		unsigned is_out, epnum;
+
+		is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8));
+		epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f;
+		if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
+			qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE);
+			usb_settoggle(qh->dev, epnum, is_out, 1);
+		}
+	}
+
+	/* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
+	wmb();
+	qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING);
+}
+
+/* if it weren't for a common silicon quirk (writing the dummy into the qh
+ * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
+ * recovery (including urb dequeue) would need software changes to a QH...
+ */
+static void qh_refresh(struct ehci_hcd *ehci, struct ehci_qh *qh)
+{
+	struct ehci_qtd *qtd;
+
+	if (list_empty(&qh->qtd_list))
+		qtd = qh->dummy;
+	else {
+		qtd = list_entry(qh->qtd_list.next, struct ehci_qtd, qtd_list);
+		/* first qtd may already be partially processed */
+		if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current)
+			qtd = NULL;
+	}
+
+	if (qtd)
+		qh_update(ehci, qh, qtd);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int qtd_copy_status(struct ehci_hcd *ehci,
+			   struct urb *urb, size_t length, u32 token)
+{
+	int status = -EINPROGRESS;
+
+	/* count IN/OUT bytes, not SETUP (even short packets) */
+	if (likely(QTD_PID(token) != 2))
+		urb->actual_length += length - QTD_LENGTH(token);
+
+	/* don't modify error codes */
+	if (unlikely(urb->unlinked))
+		return status;
+
+	/* force cleanup after short read; not always an error */
+	if (unlikely(IS_SHORT_READ(token)))
+		status = -EREMOTEIO;
+
+	/* serious "can't proceed" faults reported by the hardware */
+	if (token & QTD_STS_HALT) {
+		if (token & QTD_STS_BABBLE) {
+			/* FIXME "must" disable babbling device's port too */
+			status = -EOVERFLOW;
+		} else if (token & QTD_STS_MMF) {
+			/* fs/ls interrupt xfer missed the complete-split */
+			status = -EPROTO;
+		} else if (token & QTD_STS_DBE) {
+			status = (QTD_PID(token) == 1)	/* IN ? */
+			    ? -ENOSR	/* hc couldn't read data */
+			    : -ECOMM;	/* hc couldn't write data */
+		} else if (token & QTD_STS_XACT) {
+			/* timeout, bad crc, wrong PID, etc; retried */
+			if (QTD_CERR(token))
+				status = -EPIPE;
+			else {
+				ehci_dbg(ehci, "devpath %s ep%d%s 3strikes\n",
+					 urb->dev->devpath,
+					 usb_pipeendpoint(urb->pipe),
+					 usb_pipein(urb->pipe) ? "in" : "out");
+				status = -EPROTO;
+			}
+			/* CERR nonzero + no errors + halt --> stall */
+		} else if (QTD_CERR(token))
+			status = -EPIPE;
+		else		/* unknown */
+			status = -EPROTO;
+
+		ehci_vdbg(ehci,
+			  "dev%d ep%d%s qtd token %08x --> status %d\n",
+			  usb_pipedevice(urb->pipe),
+			  usb_pipeendpoint(urb->pipe),
+			  usb_pipein(urb->pipe) ? "in" : "out", token, status);
+
+		/* if async CSPLIT failed, try cleaning out the TT buffer */
+		if (status != -EPIPE && urb->dev->tt && !usb_pipeint(urb->pipe)
+		    && ((token & QTD_STS_MMF) != 0 || QTD_CERR(token) == 0)
+		    && (!ehci_is_TDI(ehci)
+			|| urb->dev->tt->hub !=
+			ehci_to_hcd(ehci)->self.root_hub)) {
+#ifdef DEBUG
+			struct usb_device *tt = urb->dev->tt->hub;
+			dev_dbg(&tt->dev,
+				"clear tt buffer port %d, a%d ep%d t%08x\n",
+				urb->dev->ttport, urb->dev->devnum,
+				usb_pipeendpoint(urb->pipe), token);
+#endif /* DEBUG */
+			/* REVISIT ARC-derived cores don't clear the root
+			 * hub TT buffer in this way...
+			 */
+			usb_hub_tt_clear_buffer(urb->dev, urb->pipe);
+		}
+	}
+
+	return status;
+}
+
+static void
+ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status)
+__releases(ehci->lock) __acquires(ehci->lock)
+{
+	if (likely(urb->hcpriv != NULL)) {
+		struct ehci_qh *qh = (struct ehci_qh *)urb->hcpriv;
+
+		/* S-mask in a QH means it's an interrupt urb */
+		if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) {
+
+			/* ... update hc-wide periodic stats (for usbfs) */
+			ehci_to_hcd(ehci)->self.bandwidth_int_reqs--;
+		}
+		qh_put(qh);
+	}
+
+	if (unlikely(urb->unlinked)) {
+		COUNT(ehci->stats.unlink);
+	} else {
+		/* report non-error and short read status as zero */
+		if (status == -EINPROGRESS || status == -EREMOTEIO)
+			status = 0;
+		COUNT(ehci->stats.complete);
+	}
+
+#ifdef EHCI_URB_TRACE
+	ehci_dbg(ehci,
+		 "%s %s urb %p ep%d%s status %d len %d/%d\n",
+		 __func__, urb->dev->devpath, urb,
+		 usb_pipeendpoint(urb->pipe),
+		 usb_pipein(urb->pipe) ? "in" : "out",
+		 status, urb->actual_length, urb->transfer_buffer_length);
+#endif
+
+	/* complete() can reenter this HCD */
+	usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
+	spin_unlock(&ehci->lock);
+	usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status);
+	spin_lock(&ehci->lock);
+}
+
+static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh);
+static void unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh);
+
+static void intr_deschedule(struct ehci_hcd *ehci, struct ehci_qh *qh);
+static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh);
+
+/*
+ * Process and free completed qtds for a qh, returning URBs to drivers.
+ * Chases up to qh->hw_current.  Returns number of completions called,
+ * indicating how much "real" work we did.
+ */
+static unsigned qh_completions(struct ehci_hcd *ehci, struct ehci_qh *qh)
+{
+	struct ehci_qtd *last = NULL, *end = qh->dummy;
+	struct list_head *entry, *tmp;
+	int last_status = -EINPROGRESS;
+	int stopped;
+	unsigned count = 0;
+	u8 state;
+	__le32 halt = HALT_BIT(ehci);
+	__hc32 temp_hw_qtd_next = 0;
+
+	if (unlikely(list_empty(&qh->qtd_list)))
+		return count;
+
+	/* completions (or tasks on other cpus) must never clobber HALT
+	 * till we've gone through and cleaned everything up, even when
+	 * they add urbs to this qh's queue or mark them for unlinking.
+	 *
+	 * NOTE:  unlinking expects to be done in queue order.
+	 */
+	state = qh->qh_state;
+	qh->qh_state = QH_STATE_COMPLETING;
+	stopped = (state == QH_STATE_IDLE);
+
+	/* remove de-activated QTDs from front of queue.
+	 * after faults (including short reads), cleanup this urb
+	 * then let the queue advance.
+	 * if queue is stopped, handles unlinks.
+	 */
+	list_for_each_safe(entry, tmp, &qh->qtd_list) {
+		struct ehci_qtd *qtd;
+		struct urb *urb;
+		struct ehci_qtd *qtd2;
+		struct urb *urb2;
+
+		u32 token = 0;
+
+		qtd = list_entry(entry, struct ehci_qtd, qtd_list);
+		urb = qtd->urb;
+
+		/* clean up any state from previous QTD ... */
+		if (last) {
+			if (likely(last->urb != urb)) {
+				ehci_urb_done(ehci, last->urb, last_status);
+				count++;
+				last_status = -EINPROGRESS;
+			}
+			ehci_qtd_free(ehci, last);
+			last = NULL;
+		}
+
+		/* ignore urbs submitted during completions we reported */
+		if (qtd == end)
+			break;
+
+		/* hardware copies qtd out of qh overlay */
+		rmb();
+		token = hc32_to_cpu(ehci, qtd->hw_token);
+
+		/* always clean up qtds the hc de-activated */
+		if ((token & QTD_STS_ACTIVE) == 0) {
+
+			/* on STALL, error, and short reads this urb must
+			 * complete and all its qtds must be recycled.
+			 */
+			if ((token & QTD_STS_HALT) != 0) {
+				stopped = 1;
+
+			/* magic dummy for some short reads; qh won't advance.
+			 * that silicon quirk can kick in with this dummy too.
+			 *
+			 * other short reads won't stop the queue, including
+			 * control transfers (status stage handles that) or
+			 * most other single-qtd reads ... the queue stops if
+			 * URB_SHORT_NOT_OK was set so the driver submitting
+			 * the urbs could clean it up.
+			 */
+			} else if (IS_SHORT_READ(token)
+				&& !(qtd->hw_alt_next & EHCI_LIST_END(ehci))) {
+				if (urb->use_iram && usb_pipein(urb->pipe)) {
+					if (urb->transfer_buffer == NULL) {
+						memcpy(phys_to_virt
+						       (urb->transfer_dma) +
+						       qtd->buffer_offset,
+						       ehci->
+						       iram_buffer_v
+						       [address_to_buffer
+							(ehci,
+							 usb_pipedevice(urb->
+									pipe))]
+						       + g_iram_size,
+						       min(g_iram_size,
+							   qtd->length));
+					} else {
+						memcpy(urb->transfer_buffer +
+						       qtd->buffer_offset,
+						       ehci->
+						       iram_buffer_v
+						       [address_to_buffer
+							(ehci,
+							 usb_pipedevice(urb->
+									pipe))]
+						       + g_iram_size,
+						       min(g_iram_size,
+							   qtd->length));
+					}
+				}
+				stopped = 1;
+				goto halt;
+			} else if (urb->use_iram && (!qtd->last_one)
+				   && usb_pipeout(urb->pipe)) {
+				ehci->
+				    iram_in_use[address_to_buffer
+						(ehci,
+						 usb_pipedevice(urb->pipe))] =
+				    1;
+				qtd2 =
+				    list_entry(tmp, struct ehci_qtd, qtd_list);
+				if (urb->transfer_buffer == NULL) {
+					memcpy(ehci->
+					       iram_buffer_v[address_to_buffer
+							     (ehci,
+							      usb_pipedevice
+							      (urb->pipe))],
+					       phys_to_virt(urb->transfer_dma) +
+					       qtd->buffer_offset + qtd->length,
+					       min(g_iram_size, qtd2->length));
+				} else {
+					memcpy(ehci->
+					       iram_buffer_v[address_to_buffer
+							     (ehci,
+							      usb_pipedevice
+							      (urb->pipe))],
+					       urb->transfer_buffer +
+					       qtd->buffer_offset + qtd->length,
+					       min(g_iram_size, qtd2->length));
+				}
+				temp_hw_qtd_next =
+				    QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE;
+			} else if (urb->use_iram && (qtd->last_one)
+				   && usb_pipeout(urb->pipe)) {
+				urb->use_iram = 0;
+				qtd2 =
+				    list_entry(tmp, struct ehci_qtd, qtd_list);
+				if (tmp != &qh->qtd_list) {
+					urb2 = qtd2->urb;
+					if (urb2 && urb2->use_iram == 1) {
+						ehci->
+						    iram_in_use
+						    [address_to_buffer
+						     (ehci,
+						      usb_pipedevice(urb->
+								     pipe))] =
+						    1;
+						if (urb2->transfer_buffer ==
+						    NULL) {
+							memcpy(ehci->
+							       iram_buffer_v
+							[address_to_buffer
+								(ehci,
+								 usb_pipedevice
+								 (urb->pipe))],
+							       phys_to_virt
+							       (urb2->
+								transfer_dma),
+							       min(g_iram_size,
+								   qtd2->
+								   length));
+						} else {
+							memcpy(ehci->
+							       iram_buffer_v
+							[address_to_buffer
+								(ehci,
+								 usb_pipedevice
+								 (urb->pipe))],
+							       urb2->
+							       transfer_buffer,
+							       min(g_iram_size,
+								   qtd2->
+								   length));
+						}
+					} else {
+						ehci->
+						    iram_in_use
+						    [address_to_buffer
+						     (ehci,
+						      usb_pipedevice(urb->
+								     pipe))] =
+						    0;
+					}
+				} else {
+					ehci->
+					    iram_in_use[address_to_buffer
+							(ehci,
+							 usb_pipedevice(urb->
+									pipe))]
+					    = 0;
+				}
+				temp_hw_qtd_next =
+				    QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE;
+			} else if (urb->use_iram && usb_pipein(urb->pipe)) {
+				if (urb->transfer_buffer == NULL) {
+					memcpy(phys_to_virt(urb->transfer_dma) +
+					       qtd->buffer_offset,
+					       ehci->
+					       iram_buffer_v[address_to_buffer
+							     (ehci,
+							      usb_pipedevice
+							      (urb->pipe))] +
+					       g_iram_size, min(g_iram_size,
+								qtd->length));
+				} else {
+					memcpy(urb->transfer_buffer +
+					       qtd->buffer_offset,
+					       ehci->
+					       iram_buffer_v[address_to_buffer
+							     (ehci,
+							      usb_pipedevice
+							      (urb->pipe))] +
+					       g_iram_size, min(g_iram_size,
+								qtd->length));
+				}
+				temp_hw_qtd_next =
+				    QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE;
+			}
+			/* stop scanning when we reach qtds the hc is using */
+		} else if (likely(!stopped
+				  && HC_IS_RUNNING(ehci_to_hcd(ehci)->state))) {
+			break;
+
+		/* scan the whole queue for unlinks whenever it stops */
+		} else {
+			stopped = 1;
+
+			/* cancel everything if we halt, suspend, etc */
+			if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state))
+				last_status = -ESHUTDOWN;
+
+			/* this qtd is active; skip it unless a previous qtd
+			 * for its urb faulted, or its urb was canceled.
+			 */
+			else if (last_status == -EINPROGRESS && !urb->unlinked)
+				continue;
+
+			/* qh unlinked; token in overlay may be most current */
+			if (state == QH_STATE_IDLE
+					&& cpu_to_hc32(ehci, qtd->qtd_dma)
+						== qh->hw_current)
+				token = hc32_to_cpu(ehci, qh->hw_token);
+
+			/* qh unlinked; token in overlay may be most current */
+			if (state == QH_STATE_IDLE
+			    && cpu_to_hc32(ehci, qtd->qtd_dma)
+			    == qh->hw_current)
+				token = hc32_to_cpu(ehci, qh->hw_token);
+
+			/* force halt for unlinked or blocked qh, so we'll
+			 * patch the qh later and so that completions can't
+			 * activate it while we "know" it's stopped.
+			 */
+			if ((halt & qh->hw_token) == 0) {
+halt:
+				qh->hw_token |= halt;
+				wmb();
+			}
+		}
+
+		/* unless we already know the urb's status, collect qtd status
+		 * and update count of bytes transferred.  in common short read
+		 * cases with only one data qtd (including control transfers),
+		 * queue processing won't halt.  but with two or more qtds (for
+		 * example, with a 32 KB transfer), when the first qtd gets a
+		 * short read the second must be removed by hand.
+		 */
+		if (last_status == -EINPROGRESS) {
+			last_status = qtd_copy_status(ehci, urb,
+					qtd->length, token);
+			if (last_status == -EREMOTEIO
+					&& (qtd->hw_alt_next
+						& EHCI_LIST_END(ehci)))
+				last_status = -EINPROGRESS;
+		}
+
+		/* if we're removing something not at the queue head,
+		 * patch the hardware queue pointer.
+		 */
+
+		if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
+			last = list_entry(qtd->qtd_list.prev,
+					  struct ehci_qtd, qtd_list);
+			last->hw_next = qtd->hw_next;
+		}
+
+/* remove qtd; it's recycled after possible urb completion */
+		list_del(&qtd->qtd_list);
+		last = qtd;
+	}
+
+	/* last urb's completion might still need calling */
+	if (likely(last != NULL)) {
+		ehci_urb_done(ehci, last->urb, last_status);
+		count++;
+		ehci_qtd_free(ehci, last);
+	}
+
+	/* restore original state; caller must unlink or relink */
+	qh->qh_state = state;
+
+	/* be sure the hardware's done with the qh before refreshing
+	 * it after fault cleanup, or recovering from silicon wrongly
+	 * overlaying the dummy qtd (which reduces DMA chatter).
+	 */
+	if ((stopped != 0) || (qh->hw_qtd_next == EHCI_LIST_END(ehci))
+	    && (temp_hw_qtd_next == 0)) {
+		switch (state) {
+		case QH_STATE_IDLE:
+			qh_refresh(ehci, qh);
+			break;
+		case QH_STATE_LINKED:
+			/* We won't refresh a QH that's linked (after the HC
+			 * stopped the queue).  That avoids a race:
+			 *  - HC reads first part of QH;
+			 *  - CPU updates that first part and the token;
+			 *  - HC reads rest of that QH, including token
+			 * Result:  HC gets an inconsistent image, and then
+			 * DMAs to/from the wrong memory (corrupting it).
+			 *
+			 * That should be rare for interrupt transfers,
+			 * except maybe high bandwidth ...
+			 */
+			if ((cpu_to_hc32(ehci, QH_SMASK)
+			     & qh->hw_info2) != 0) {
+				intr_deschedule(ehci, qh);
+				(void)qh_schedule(ehci, qh);
+			} else
+				unlink_async(ehci, qh);
+			break;
+			/* otherwise, unlink already started */
+		}
+	}
+	if (temp_hw_qtd_next)
+		qh->hw_qtd_next = temp_hw_qtd_next;
+
+	return count;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* high bandwidth multiplier, as encoded in highspeed endpoint descriptors */
+#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
+/* ... and packet size, for any kind of endpoint descriptor */
+#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
+
+/*
+ * reverse of qh_urb_transaction:  free a list of TDs.
+ * used for cleanup after errors, before HC sees an URB's TDs.
+ */
+static void qtd_list_free(struct ehci_hcd *ehci,
+			  struct urb *urb, struct list_head *qtd_list)
+{
+	struct list_head *entry, *temp;
+
+	list_for_each_safe(entry, temp, qtd_list) {
+		struct ehci_qtd *qtd;
+
+		qtd = list_entry(entry, struct ehci_qtd, qtd_list);
+		list_del(&qtd->qtd_list);
+		ehci_qtd_free(ehci, qtd);
+	}
+}
+
+/*
+ * create a list of filled qtds for this URB; won't link into qh.
+ */
+static struct list_head *qh_urb_transaction(struct ehci_hcd *ehci,
+					    struct urb *urb,
+					    struct list_head *head, gfp_t flags)
+{
+	struct ehci_qtd *qtd, *qtd_prev;
+	dma_addr_t buf;
+	int len, maxpacket;
+	int is_input;
+	u32 token;
+
+	/*
+	 * URBs map to sequences of QTDs:  one logical transaction
+	 */
+	qtd = ehci_qtd_alloc(ehci, flags);
+	if (unlikely(!qtd))
+		return NULL;
+	list_add_tail(&qtd->qtd_list, head);
+	qtd->urb = urb;
+
+	token = QTD_STS_ACTIVE;
+	token |= (EHCI_TUNE_CERR << 10);
+	/* for split transactions, SplitXState initialized to zero */
+
+	len = urb->transfer_buffer_length;
+	is_input = usb_pipein(urb->pipe);
+	if (usb_pipecontrol(urb->pipe)) {
+		/* SETUP pid */
+		qtd_fill(ehci, qtd, urb->setup_dma,
+			 sizeof(struct usb_ctrlrequest),
+			 token | (2 /* "setup" */  << 8), 8);
+
+		/* ... and always at least one more pid */
+		token ^= QTD_TOGGLE;
+		qtd_prev = qtd;
+		qtd = ehci_qtd_alloc(ehci, flags);
+		if (unlikely(!qtd))
+			goto cleanup;
+		qtd->urb = urb;
+		qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
+		list_add_tail(&qtd->qtd_list, head);
+
+		/* for zero length DATA stages, STATUS is always IN */
+		if (len == 0)
+			token |= (1 /* "in" */  << 8);
+	}
+
+	/*
+	 * data transfer stage:  buffer setup
+	 */
+	buf = urb->transfer_dma;
+
+	if (is_input)
+		token |= (1 /* "in" */  << 8);
+	/* else it's already initted to "out" pid (0 << 8) */
+
+	maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
+
+	/*
+	 * buffer gets wrapped in one or more qtds;
+	 * last one may be "short" (including zero len)
+	 * and may serve as a control status ack
+	 */
+	for (;;) {
+		int this_qtd_len;
+		this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket);
+		if (urb->use_iram && (!qtd->buffer_offset)
+		    && usb_pipeout(urb->pipe)
+		    && (ehci->
+			iram_in_use[address_to_buffer
+				    (ehci, usb_pipedevice(urb->pipe))] == 0)) {
+			ehci->
+			    iram_in_use[address_to_buffer
+					(ehci, usb_pipedevice(urb->pipe))] = 1;
+			if (urb->transfer_buffer == NULL) {
+				memcpy(ehci->
+				       iram_buffer_v[address_to_buffer
+						     (ehci,
+						      usb_pipedevice(urb->
+								     pipe))],
+				       phys_to_virt(urb->transfer_dma),
+				       min((int)g_iram_size, len));
+			} else {
+				memcpy(ehci->
+				       iram_buffer_v[address_to_buffer
+						     (ehci,
+						      usb_pipedevice(urb->
+								     pipe))],
+				       urb->transfer_buffer,
+				       min((int)g_iram_size, len));
+			}
+		}
+		len -= this_qtd_len;
+		buf += this_qtd_len;
+
+		/*
+		 * short reads advance to a "magic" dummy instead of the next
+		 * qtd ... that forces the queue to stop, for manual cleanup.
+		 * (this will usually be overridden later.)
+		 */
+		if (is_input)
+			qtd->hw_alt_next = ehci->async->hw_alt_next;
+
+		/* qh makes control packets use qtd toggle; maybe switch it */
+		if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
+			token ^= QTD_TOGGLE;
+
+		if (likely(len <= 0)) {
+			qtd->last_one = 1;
+			break;
+		}
+		qtd_prev = qtd;
+		qtd = ehci_qtd_alloc(ehci, flags);
+		if (unlikely(!qtd))
+			goto cleanup;
+		qtd->urb = urb;
+		if (urb->use_iram)
+			qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma) | 0x1;
+		else
+			qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
+
+		list_add_tail(&qtd->qtd_list, head);
+	}
+
+	/*
+	 * unless the caller requires manual cleanup after short reads,
+	 * have the alt_next mechanism keep the queue running after the
+	 * last data qtd (the only one, for control and most other cases).
+	 */
+	if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
+		   || usb_pipecontrol(urb->pipe)))
+		qtd->hw_alt_next = EHCI_LIST_END(ehci);
+
+	/*
+	 * control requests may need a terminating data "status" ack;
+	 * bulk ones may need a terminating short packet (zero length).
+	 */
+	if (likely(urb->transfer_buffer_length != 0)) {
+		int one_more = 0;
+
+		if (usb_pipecontrol(urb->pipe)) {
+			one_more = 1;
+			token ^= 0x0100;	/* "in" <--> "out"  */
+			token |= QTD_TOGGLE;	/* force DATA1 */
+		} else if (usb_pipebulk(urb->pipe)
+			   && (urb->transfer_flags & URB_ZERO_PACKET)
+			   && !(urb->transfer_buffer_length % maxpacket))
+			one_more = 1;
+		if (one_more) {
+			qtd_prev = qtd;
+			qtd = ehci_qtd_alloc(ehci, flags);
+			if (unlikely(!qtd))
+				goto cleanup;
+			qtd->urb = urb;
+			qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
+			list_add_tail(&qtd->qtd_list, head);
+
+			/* never any data in such packets */
+			qtd_fill(ehci, qtd, 0, 0, token, 0);
+		}
+	}
+
+	/* by default, enable interrupt on urb completion */
+	if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
+		qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC);
+	return head;
+
+cleanup:
+	qtd_list_free(ehci, urb, head);
+	return NULL;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Would be best to create all qh's from config descriptors,
+ * when each interface/altsetting is established.  Unlink
+ * any previous qh and cancel its urbs first; endpoints are
+ * implicitly reset then (data toggle too).
+ * That'd mean updating how usbcore talks to HCDs. (2.7?)
+ */
+
+/*
+ * Each QH holds a qtd list; a QH is used for everything except iso.
+ *
+ * For interrupt urbs, the scheduler must set the microframe scheduling
+ * mask(s) each time the QH gets scheduled.  For highspeed, that's
+ * just one microframe in the s-mask.  For split interrupt transactions
+ * there are additional complications: c-mask, maybe FSTNs.
+ */
+static struct ehci_qh *qh_make(struct ehci_hcd *ehci,
+			       struct urb *urb, gfp_t flags)
+{
+	struct ehci_qh *qh = ehci_qh_alloc(ehci, flags);
+	u32 info1 = 0, info2 = 0;
+	int is_input, type;
+	int maxp = 0;
+	struct usb_tt		*tt = urb->dev->tt;
+
+	if (!qh)
+		return qh;
+
+	/*
+	 * init endpoint/device data for this QH
+	 */
+	info1 |= usb_pipeendpoint(urb->pipe) << 8;
+	info1 |= usb_pipedevice(urb->pipe) << 0;
+
+	is_input = usb_pipein(urb->pipe);
+	type = usb_pipetype(urb->pipe);
+	maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
+
+	/* 1024 byte maxpacket is a hardware ceiling.  High bandwidth
+	 * acts like up to 3KB, but is built from smaller packets.
+	 */
+	if (max_packet(maxp) > 1024) {
+		ehci_dbg(ehci, "bogus qh maxpacket %d\n", max_packet(maxp));
+		goto done;
+	}
+
+	/* Compute interrupt scheduling parameters just once, and save.
+	 * - allowing for high bandwidth, how many nsec/uframe are used?
+	 * - split transactions need a second CSPLIT uframe; same question
+	 * - splits also need a schedule gap (for full/low speed I/O)
+	 * - qh has a polling interval
+	 *
+	 * For control/bulk requests, the HC or TT handles these.
+	 */
+	if (type == PIPE_INTERRUPT) {
+		qh->usecs =
+		    NS_TO_US(usb_calc_bus_time
+			     (USB_SPEED_HIGH, is_input, 0,
+			      hb_mult(maxp) * max_packet(maxp)));
+		qh->start = NO_FRAME;
+
+		if (urb->dev->speed == USB_SPEED_HIGH) {
+			qh->c_usecs = 0;
+			qh->gap_uf = 0;
+
+			qh->period = urb->interval >> 3;
+			if (qh->period == 0 && urb->interval != 1) {
+				/* NOTE interval 2 or 4 uframes could work.
+				 * But interval 1 scheduling is simpler, and
+				 * includes high bandwidth.
+				 */
+				dbg("intr period %d uframes, NYET!",
+				    urb->interval);
+				goto done;
+			}
+		} else {
+			int think_time;
+
+			/* gap is f(FS/LS transfer times) */
+			qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
+							   is_input, 0,
+							   maxp) / (125 * 1000);
+
+			/* FIXME this just approximates SPLIT/CSPLIT times */
+			if (is_input) {
+				qh->c_usecs = qh->usecs + HS_USECS(0);
+				qh->usecs = HS_USECS(1);
+			} else {
+				qh->usecs += HS_USECS(1);
+				qh->c_usecs = HS_USECS(0);
+			}
+
+			think_time = tt ? tt->think_time : 0;
+			qh->tt_usecs = NS_TO_US(think_time +
+						usb_calc_bus_time(urb->dev->
+								  speed,
+								  is_input, 0,
+								  max_packet
+								  (maxp)));
+			qh->period = urb->interval;
+		}
+	}
+
+	/* support for tt scheduling, and access to toggles */
+	qh->dev = urb->dev;
+
+	/* using TT? */
+	switch (urb->dev->speed) {
+	case USB_SPEED_LOW:
+		info1 |= (1 << 12);	/* EPS "low" */
+		/* FALL THROUGH */
+
+	case USB_SPEED_FULL:
+		/* EPS 0 means "full" */
+		if (type != PIPE_INTERRUPT)
+			info1 |= (EHCI_TUNE_RL_TT << 28);
+		if (type == PIPE_CONTROL) {
+			info1 |= (1 << 27);	/* for TT */
+			info1 |= 1 << 14;	/* toggle from qtd */
+		}
+		info1 |= maxp << 16;
+
+		info2 |= (EHCI_TUNE_MULT_TT << 30);
+
+		/* Some Freescale processors have an erratum in which the
+		 * port number in the queue head was 0..N-1 instead of 1..N.
+		 */
+		if (ehci_has_fsl_portno_bug(ehci))
+			info2 |= (urb->dev->ttport - 1) << 23;
+		else
+			info2 |= urb->dev->ttport << 23;
+
+		/* set the address of the TT; for TDI's integrated
+		 * root hub tt, leave it zeroed.
+		 */
+		if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub)
+			info2 |= tt->hub->devnum << 16;
+
+		/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
+
+		break;
+
+	case USB_SPEED_HIGH:	/* no TT involved */
+		info1 |= (2 << 12);	/* EPS "high" */
+		if (type == PIPE_CONTROL) {
+			info1 |= (EHCI_TUNE_RL_HS << 28);
+			info1 |= 64 << 16;	/* usb2 fixed maxpacket */
+			info1 |= 1 << 14;	/* toggle from qtd */
+			info2 |= (EHCI_TUNE_MULT_HS << 30);
+		} else if (type == PIPE_BULK) {
+			info1 |= (EHCI_TUNE_RL_HS << 28);
+			/* The USB spec says that high speed bulk endpoints
+			 * always use 512 byte maxpacket.  But some device
+			 * vendors decided to ignore that, and MSFT is happy
+			 * to help them do so.  So now people expect to use
+			 * such nonconformant devices with Linux too; sigh.
+			 */
+			info1 |= max_packet(maxp) << 16;
+			info2 |= (EHCI_TUNE_MULT_HS << 30);
+			use_buffer(ehci, usb_pipedevice(urb->pipe));
+		} else {	/* PIPE_INTERRUPT */
+			info1 |= max_packet(maxp) << 16;
+			info2 |= hb_mult(maxp) << 30;
+		}
+		break;
+	default:
+		dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed);
+done:
+		qh_put(qh);
+		return NULL;
+	}
+
+	/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
+
+	/* init as live, toggle clear, advance to dummy */
+	qh->qh_state = QH_STATE_IDLE;
+	qh->hw_info1 = cpu_to_hc32(ehci, info1);
+	qh->hw_info2 = cpu_to_hc32(ehci, info2);
+	usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
+	qh_refresh(ehci, qh);
+	return qh;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* move qh (and its qtds) onto async queue; maybe enable queue.  */
+
+static void qh_link_async(struct ehci_hcd *ehci, struct ehci_qh *qh)
+{
+	__hc32 dma = QH_NEXT(ehci, qh->qh_dma);
+	struct ehci_qh *head;
+
+	/* (re)start the async schedule? */
+	head = ehci->async;
+	timer_action_done(ehci, TIMER_ASYNC_OFF);
+	if (!head->qh_next.qh) {
+		u32 cmd = ehci_readl(ehci, &ehci->regs->command);
+
+		if (!(cmd & CMD_ASE)) {
+			/* in case a clear of CMD_ASE didn't take yet */
+			(void)handshake(ehci, &ehci->regs->status,
+					STS_ASS, 0, 150);
+			cmd |= CMD_ASE | CMD_RUN;
+			ehci_writel(ehci, cmd, &ehci->regs->command);
+			ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
+			/* posted write need not be known to HC yet ... */
+		}
+	}
+
+	/* clear halt and/or toggle; and maybe recover from silicon quirk */
+	if (qh->qh_state == QH_STATE_IDLE)
+		qh_refresh(ehci, qh);
+
+	/* splice right after start */
+	qh->qh_next = head->qh_next;
+	qh->hw_next = head->hw_next;
+	wmb();
+
+	head->qh_next.qh = qh;
+	head->hw_next = dma;
+
+	qh->qh_state = QH_STATE_LINKED;
+	/* qtd completions reported later by interrupt */
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * For control/bulk/interrupt, return QH with these TDs appended.
+ * Allocates and initializes the QH if necessary.
+ * Returns null if it can't allocate a QH it needs to.
+ * If the QH has TDs (urbs) already, that's great.
+ */
+static struct ehci_qh *qh_append_tds(struct ehci_hcd *ehci,
+				     struct urb *urb,
+				     struct list_head *qtd_list,
+				     int epnum, void **ptr)
+{
+	struct ehci_qh *qh = NULL;
+	__hc32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f);
+
+	qh = (struct ehci_qh *)*ptr;
+	if (unlikely(qh == NULL)) {
+		/* can't sleep here, we have ehci->lock... */
+		qh = qh_make(ehci, urb, GFP_ATOMIC);
+		*ptr = qh;
+	}
+	if (likely(qh != NULL)) {
+		struct ehci_qtd *qtd;
+
+		if (unlikely(list_empty(qtd_list)))
+			qtd = NULL;
+		else
+			qtd = list_entry(qtd_list->next, struct ehci_qtd,
+					 qtd_list);
+
+		/* control qh may need patching ... */
+		if (unlikely(epnum == 0)) {
+
+			/* usb_reset_device() briefly reverts to address 0 */
+			if (usb_pipedevice(urb->pipe) == 0)
+				qh->hw_info1 &= ~qh_addr_mask;
+		}
+
+		/* just one way to queue requests: swap with the dummy qtd.
+		 * only hc or qh_refresh() ever modify the overlay.
+		 */
+		if (likely(qtd != NULL)) {
+			struct ehci_qtd *dummy;
+			dma_addr_t dma;
+			__hc32 token;
+
+			/* to avoid racing the HC, use the dummy td instead of
+			 * the first td of our list (becomes new dummy).  both
+			 * tds stay deactivated until we're done, when the
+			 * HC is allowed to fetch the old dummy (4.10.2).
+			 */
+			token = qtd->hw_token;
+			qtd->hw_token = HALT_BIT(ehci);
+			wmb();
+			dummy = qh->dummy;
+
+			dma = dummy->qtd_dma;
+			*dummy = *qtd;
+			dummy->qtd_dma = dma;
+
+			list_del(&qtd->qtd_list);
+			list_add(&dummy->qtd_list, qtd_list);
+			__list_splice(qtd_list, qh->qtd_list.prev);
+
+			ehci_qtd_init(ehci, qtd, qtd->qtd_dma);
+			qh->dummy = qtd;
+
+			/* hc must see the new dummy at list end */
+			dma = qtd->qtd_dma;
+			qtd = list_entry(qh->qtd_list.prev,
+					 struct ehci_qtd, qtd_list);
+			if (urb->use_iram)
+				qtd->hw_next = QTD_NEXT(ehci, dma) | 0x1;
+			else
+				qtd->hw_next = QTD_NEXT(ehci, dma);
+
+			/* let the hc process these next qtds */
+			wmb();
+			dummy->hw_token = token;
+
+			urb->hcpriv = qh_get(qh);
+		}
+	}
+	return qh;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int
+submit_async(struct ehci_hcd *ehci,
+	     struct urb *urb, struct list_head *qtd_list, gfp_t mem_flags)
+{
+	struct ehci_qtd *qtd;
+	int epnum;
+	unsigned long flags;
+	struct ehci_qh *qh = NULL;
+	int rc;
+
+	qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
+	epnum = urb->ep->desc.bEndpointAddress;
+
+#ifdef EHCI_URB_TRACE
+	ehci_dbg(ehci,
+		 "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
+		 __func__, urb->dev->devpath, urb,
+		 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
+		 urb->transfer_buffer_length, qtd, urb->ep->hcpriv);
+#endif
+
+	spin_lock_irqsave(&ehci->lock, flags);
+	if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
+			       &ehci_to_hcd(ehci)->flags))) {
+		rc = -ESHUTDOWN;
+		goto done;
+	}
+	rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
+	if (unlikely(rc))
+		goto done;
+
+	qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
+	if (unlikely(qh == NULL)) {
+		usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
+		rc = -ENOMEM;
+		goto done;
+	}
+
+	/* Control/bulk operations through TTs don't need scheduling,
+	 * the HC and TT handle it when the TT has a buffer ready.
+	 */
+	if (likely(qh->qh_state == QH_STATE_IDLE))
+		qh_link_async(ehci, qh_get(qh));
+done:
+	spin_unlock_irqrestore(&ehci->lock, flags);
+	if (unlikely(qh == NULL))
+		qtd_list_free(ehci, urb, qtd_list);
+	return rc;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* the async qh for the qtds being reclaimed are now unlinked from the HC */
+
+static void end_unlink_async(struct ehci_hcd *ehci)
+{
+	struct ehci_qh *qh = ehci->reclaim;
+	struct ehci_qh *next;
+
+	iaa_watchdog_done(ehci);
+
+	qh->qh_state = QH_STATE_IDLE;
+	qh->qh_next.qh = NULL;
+	qh_put(qh);		/* refcount from reclaim */
+
+	/* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
+	next = qh->reclaim;
+	ehci->reclaim = next;
+	qh->reclaim = NULL;
+
+	qh_completions(ehci, qh);
+
+	if (!list_empty(&qh->qtd_list)
+	    && HC_IS_RUNNING(ehci_to_hcd(ehci)->state))
+		qh_link_async(ehci, qh);
+	else {
+		qh_put(qh);	/* refcount from async list */
+
+		/* it's not free to turn the async schedule on/off; leave it
+		 * active but idle for a while once it empties.
+		 */
+		if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)
+		    && ehci->async->qh_next.qh == NULL)
+			timer_action(ehci, TIMER_ASYNC_OFF);
+	}
+
+	if (next) {
+		ehci->reclaim = NULL;
+		start_unlink_async(ehci, next);
+	}
+}
+
+/* makes sure the async qh will become idle */
+/* caller must own ehci->lock */
+
+static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh)
+{
+	int cmd = ehci_readl(ehci, &ehci->regs->command);
+	struct ehci_qh *prev;
+
+#ifdef DEBUG
+	assert_spin_locked(&ehci->lock);
+	if (ehci->reclaim
+	    || (qh->qh_state != QH_STATE_LINKED
+		&& qh->qh_state != QH_STATE_UNLINK_WAIT)
+	    )
+		BUG();
+#endif
+
+	/* stop async schedule right now? */
+	if (unlikely(qh == ehci->async)) {
+		/* can't get here without STS_ASS set */
+		if (ehci_to_hcd(ehci)->state != HC_STATE_HALT &&
+			!ehci->reclaim) {
+			/* ... and CMD_IAAD clear */
+			ehci_writel(ehci, cmd & ~CMD_ASE, &ehci->regs->command);
+			wmb();
+			/* handshake later, if we need to */
+			timer_action_done(ehci, TIMER_ASYNC_OFF);
+		}
+		return;
+	}
+
+	qh->qh_state = QH_STATE_UNLINK;
+	ehci->reclaim = qh = qh_get(qh);
+
+	prev = ehci->async;
+	while (prev->qh_next.qh != qh)
+		prev = prev->qh_next.qh;
+
+	prev->hw_next = qh->hw_next;
+	prev->qh_next = qh->qh_next;
+	wmb();
+
+	if (unlikely(ehci_to_hcd(ehci)->state == HC_STATE_HALT)) {
+		/* if (unlikely (qh->reclaim != 0))
+		 *  this will recurse, probably not much
+		 */
+		end_unlink_async(ehci);
+		return;
+	}
+
+	cmd |= CMD_IAAD;
+	ehci_writel(ehci, cmd, &ehci->regs->command);
+	(void)ehci_readl(ehci, &ehci->regs->command);
+	iaa_watchdog_start(ehci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void scan_async(struct ehci_hcd *ehci)
+{
+	struct ehci_qh *qh;
+	enum ehci_timer_action action = TIMER_IO_WATCHDOG;
+
+	if (!++(ehci->stamp))
+		ehci->stamp++;
+	timer_action_done(ehci, TIMER_ASYNC_SHRINK);
+rescan:
+	qh = ehci->async->qh_next.qh;
+	if (likely(qh != NULL)) {
+		do {
+			/* clean any finished work for this qh */
+			if (!list_empty(&qh->qtd_list)
+			    && qh->stamp != ehci->stamp) {
+				int temp;
+
+				/* unlinks could happen here; completion
+				 * reporting drops the lock.  rescan using
+				 * the latest schedule, but don't rescan
+				 * qhs we already finished (no looping).
+				 */
+				qh = qh_get(qh);
+				qh->stamp = ehci->stamp;
+				temp = qh_completions(ehci, qh);
+				qh_put(qh);
+				if (temp != 0)
+					goto rescan;
+			}
+
+			/* unlink idle entries, reducing HC PCI usage as well
+			 * as HCD schedule-scanning costs.  delay for any qh
+			 * we just scanned, there's a not-unusual case that it
+			 * doesn't stay idle for long.
+			 * (plus, avoids some kind of re-activation race.)
+			 */
+			if (list_empty(&qh->qtd_list)) {
+				if (qh->stamp == ehci->stamp)
+					action = TIMER_ASYNC_SHRINK;
+				else if (!ehci->reclaim
+					 && qh->qh_state == QH_STATE_LINKED)
+					start_unlink_async(ehci, qh);
+			}
+
+			qh = qh->qh_next.qh;
+		} while (qh);
+	}
+	if (action == TIMER_ASYNC_SHRINK)
+		timer_action(ehci, TIMER_ASYNC_SHRINK);
+}
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 2bfff30f4704..4b81f5e77c8b 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -138,6 +138,18 @@ struct ehci_hcd {			/* one per controller */
 
 	u8			sbrn;		/* packed release number */
 
+	/*
+	 * OTG controllers and transceivers need software interaction;
+	 * other external transceivers should be software-transparent
+	 */
+	struct otg_transceiver   *transceiver;
+#ifdef CONFIG_USB_STATIC_IRAM
+	u32			iram_buffer[2];
+	u32			iram_buffer_v[2];
+	int  			iram_in_use[2];
+	int			usb_address[2];
+#endif
+
 	/* irq statistics */
 #ifdef EHCI_STATS
 	struct ehci_stats	stats;
@@ -240,6 +252,10 @@ struct ehci_qtd {
 	struct list_head	qtd_list;		/* sw qtd list */
 	struct urb		*urb;			/* qtd's urb */
 	size_t			length;			/* length of buffer */
+#ifdef CONFIG_USB_STATIC_IRAM
+	size_t			buffer_offset;
+	int			last_one;
+#endif
 } __attribute__ ((aligned (32)));
 
 /* mask NakCnt+T in qh->hw_alt_next */
@@ -710,6 +726,10 @@ static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 #define STUB_DEBUG_FILES
 #endif	/* DEBUG */
 
+#ifdef CONFIG_USB_STATIC_IRAM
+#define IRAM_TD_SIZE	1024		/* size of 1 qTD's buffer */
+#define IRAM_NTD	2		/* number of TDs in IRAM  */
+#endif
 /*-------------------------------------------------------------------------*/
 
 #endif /* __LINUX_EHCI_HCD_H */
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index aa884d072f0b..d1aa47345a10 100644
--- a/drivers/usb/otg/Kconfig
+++ b/drivers/usb/otg/Kconfig
@@ -59,4 +59,11 @@ config NOP_USB_XCEIV
 	 built-in with usb ip or which are autonomous and doesn't require any
 	 phy programming such as ISP1x04 etc.
 
+config MXC_OTG
+	tristate "USB OTG pin detect support"
+	select USB_OTG
+	depends on USB_GADGET_ARC && USB_EHCI_HCD
+	help
+	  Support for USB OTG PIN detect on MXC platforms.
+
 endif # USB || OTG
diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
index 208167856529..836060a7ee24 100644
--- a/drivers/usb/otg/Makefile
+++ b/drivers/usb/otg/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_USB_GPIO_VBUS)	+= gpio_vbus.o
 obj-$(CONFIG_ISP1301_OMAP)	+= isp1301_omap.o
 obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
 obj-$(CONFIG_NOP_USB_XCEIV)	+= nop-usb-xceiv.o
+fsl_otg_arc-objs		:= fsl_otg.o otg_fsm.o
+obj-$(CONFIG_MXC_OTG) += fsl_otg_arc.o
 
 ccflags-$(CONFIG_USB_DEBUG)	+= -DDEBUG
 ccflags-$(CONFIG_USB_GADGET_DEBUG) += -DDEBUG
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
new file mode 100644
index 000000000000..593ad75d083d
--- /dev/null
+++ b/drivers/usb/otg/fsl_otg.c
@@ -0,0 +1,1306 @@
+/*
+ * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *         Jerry Huang <Chang-Ming.Huang@freescale.com>
+ *
+ * Initialization based on code from Shlomi Gridish.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/proc_fs.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/reboot.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/usb.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/workqueue.h>
+#include <linux/time.h>
+#include <linux/usb/fsl_xcvr.h>
+#include <linux/fsl_devices.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/byteorder.h>
+#include <asm/uaccess.h>
+#include <asm/unaligned.h>
+#include "fsl_otg.h"
+
+#define CONFIG_USB_OTG_DEBUG_FILES
+#define DRIVER_VERSION "$Revision: 1.55 $"
+#define DRIVER_AUTHOR "Jerry Huang/Li Yang"
+#define DRIVER_DESC "Freescale USB OTG Driver"
+#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
+
+
+MODULE_DESCRIPTION("Freescale USB OTG Transceiver Driver");
+
+static const char driver_name[] = "fsl-usb2-otg";
+
+const pm_message_t otg_suspend_state = {
+	.event = 1,
+};
+
+#define HA_DATA_PULSE 1
+
+volatile static struct usb_dr_mmap *usb_dr_regs;
+static struct fsl_otg *fsl_otg_dev;
+static int srp_wait_done;
+static int gpio_id;
+/* FSM timers */
+struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
+	*b_ase0_brst_tmr, *b_se0_srp_tmr;
+
+/* Driver specific timers */
+struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
+	*b_srp_wait_tmr, *a_wait_enum_tmr;
+
+static struct list_head active_timers;
+
+static struct fsl_otg_config fsl_otg_initdata = {
+	.otg_port = 1,
+};
+
+int write_ulpi(u8 addr, u8 data)
+{
+	u32 temp;
+	temp = 0x60000000 | (addr << 16) | data;
+	temp = cpu_to_le32(temp);
+	usb_dr_regs->ulpiview = temp;
+	return 0;
+}
+
+/* prototype declaration */
+void fsl_otg_add_timer(void *timer);
+void fsl_otg_del_timer(void *timer);
+
+/* -------------------------------------------------------------*/
+/* Operations that will be called from OTG Finite State Machine */
+
+/* Charge vbus for vbus pulsing in SRP */
+void fsl_otg_chrg_vbus(int on)
+{
+	if (on)
+		usb_dr_regs->otgsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) &
+				 ~OTGSC_INTSTS_MASK &
+				 ~OTGSC_CTRL_VBUS_DISCHARGE) |
+				OTGSC_CTRL_VBUS_CHARGE);
+	else
+		usb_dr_regs->otgsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) &
+				 ~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_VBUS_CHARGE));
+}
+
+/* Discharge vbus through a resistor to ground */
+void fsl_otg_dischrg_vbus(int on)
+{
+	if (on)
+		usb_dr_regs->otgsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) &
+				 ~OTGSC_INTSTS_MASK)
+				| OTGSC_CTRL_VBUS_DISCHARGE);
+	else
+		usb_dr_regs->otgsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) &
+				 ~OTGSC_INTSTS_MASK &
+				 ~OTGSC_CTRL_VBUS_DISCHARGE));
+}
+
+/* A-device driver vbus, controlled through PP bit in PORTSC */
+void fsl_otg_drv_vbus(struct fsl_usb2_platform_data *pdata, int on)
+{
+/*	if (on)
+		usb_dr_regs->portsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->portsc) &
+				 ~PORTSC_W1C_BITS) | PORTSC_PORT_POWER);
+	else
+		usb_dr_regs->portsc =
+		    cpu_to_le32(le32_to_cpu(usb_dr_regs->portsc) &
+				~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER);
+*/
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
+		pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on);
+}
+
+/*
+ * Pull-up D+, signalling connect by periperal. Also used in
+ * data-line pulsing in SRP
+ */
+void fsl_otg_loc_conn(int on)
+{
+	if (on)
+		usb_dr_regs->otgsc =
+		    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) &
+				 ~OTGSC_INTSTS_MASK) | OTGSC_CTRL_DATA_PULSING);
+	else
+		usb_dr_regs->otgsc =
+		    cpu_to_le32(le32_to_cpu(usb_dr_regs->otgsc) &
+				~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_DATA_PULSING);
+}
+
+/* Generate SOF by host.  This is controlled through suspend/resume the
+ * port.  In host mode, controller will automatically send SOF.
+ * Suspend will block the data on the port.
+ */
+void fsl_otg_loc_sof(int on)
+{
+	u32 tmpval;
+
+	tmpval = readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
+	if (on)
+		tmpval |= PORTSC_PORT_FORCE_RESUME;
+	else
+		tmpval |= PORTSC_PORT_SUSPEND;
+	writel(tmpval, &fsl_otg_dev->dr_mem_map->portsc);
+
+}
+
+/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
+void fsl_otg_start_pulse(void)
+{
+	srp_wait_done = 0;
+#ifdef HA_DATA_PULSE
+	usb_dr_regs->otgsc =
+	    cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK)
+			| OTGSC_HA_DATA_PULSE);
+#else
+	fsl_otg_loc_conn(1);
+#endif
+
+	fsl_otg_add_timer(b_data_pulse_tmr);
+}
+
+void fsl_otg_pulse_vbus(void);
+
+void b_data_pulse_end(unsigned long foo)
+{
+#ifdef HA_DATA_PULSE
+#else
+	fsl_otg_loc_conn(0);
+#endif
+
+	/* Do VBUS pulse after data pulse */
+	fsl_otg_pulse_vbus();
+}
+
+void fsl_otg_pulse_vbus(void)
+{
+	srp_wait_done = 0;
+	fsl_otg_chrg_vbus(1);
+	/* start the timer to end vbus charge */
+	fsl_otg_add_timer(b_vbus_pulse_tmr);
+}
+
+void b_vbus_pulse_end(unsigned long foo)
+{
+	fsl_otg_chrg_vbus(0);
+
+	/* As USB3300 using the same a_sess_vld and b_sess_vld voltage
+	 * we need to discharge the bus for a while to distinguish
+	 * residual voltage of vbus pulsing and A device pull up */
+	fsl_otg_dischrg_vbus(1);
+	fsl_otg_add_timer(b_srp_wait_tmr);
+}
+
+void b_srp_end(unsigned long foo)
+{
+	fsl_otg_dischrg_vbus(0);
+	srp_wait_done = 1;
+
+	if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
+	    fsl_otg_dev->fsm.b_sess_vld)
+		fsl_otg_dev->fsm.b_srp_done = 1;
+}
+
+/* Workaround for a_host suspending too fast.  When a_bus_req=0,
+ * a_host will start by SRP.  It needs to set b_hnp_enable before
+ * actually suspending to start HNP
+ */
+void a_wait_enum(unsigned long foo)
+{
+	VDBG("a_wait_enum timeout\n");
+	if (!fsl_otg_dev->otg.host->b_hnp_enable)
+		fsl_otg_add_timer(a_wait_enum_tmr);
+	else
+		otg_statemachine(&fsl_otg_dev->fsm);
+}
+
+/* ------------------------------------------------------*/
+
+/* The timeout callback function to set time out bit */
+void set_tmout(unsigned long indicator)
+{
+	*(int *)indicator = 1;
+}
+
+/* Initialize timers */
+int fsl_otg_init_timers(struct otg_fsm *fsm)
+{
+	/* FSM used timers */
+	a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
+				(unsigned long)&fsm->a_wait_vrise_tmout);
+	if (a_wait_vrise_tmr == NULL)
+		return -ENOMEM;
+
+	a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
+				(unsigned long)&fsm->a_wait_bcon_tmout);
+	if (a_wait_bcon_tmr == NULL)
+		return -ENOMEM;
+
+	a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
+				(unsigned long)&fsm->a_aidl_bdis_tmout);
+	if (a_aidl_bdis_tmr == NULL)
+		return -ENOMEM;
+
+	b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
+				(unsigned long)&fsm->b_ase0_brst_tmout);
+	if (b_ase0_brst_tmr == NULL)
+		return -ENOMEM;
+
+	b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
+				(unsigned long)&fsm->b_se0_srp);
+	if (b_se0_srp_tmr == NULL)
+		return -ENOMEM;
+
+	b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
+				(unsigned long)&fsm->b_srp_done);
+	if (b_srp_fail_tmr == NULL)
+		return -ENOMEM;
+
+	a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
+				(unsigned long)&fsm);
+	if (a_wait_enum_tmr == NULL)
+		return -ENOMEM;
+
+	/* device driver used timers */
+	b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
+	if (b_srp_wait_tmr == NULL)
+		return -ENOMEM;
+
+	b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
+				TB_DATA_PLS, 0);
+	if (b_data_pulse_tmr == NULL)
+		return -ENOMEM;
+
+	b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
+				TB_VBUS_PLS, 0);
+	if (b_vbus_pulse_tmr == NULL)
+		return -ENOMEM;
+
+	return 0;
+}
+
+/* Uninitialize timers */
+void fsl_otg_uninit_timers(void)
+{
+	/* FSM used timers */
+	if (a_wait_vrise_tmr != NULL)
+		kfree(a_wait_vrise_tmr);
+	if (a_wait_bcon_tmr != NULL)
+		kfree(a_wait_bcon_tmr);
+	if (a_aidl_bdis_tmr != NULL)
+		kfree(a_aidl_bdis_tmr);
+	if (b_ase0_brst_tmr != NULL)
+		kfree(b_ase0_brst_tmr);
+	if (b_se0_srp_tmr != NULL)
+		kfree(b_se0_srp_tmr);
+	if (b_srp_fail_tmr != NULL)
+		kfree(b_srp_fail_tmr);
+	if (a_wait_enum_tmr != NULL)
+		kfree(a_wait_enum_tmr);
+
+	/* device driver used timers */
+	if (b_srp_wait_tmr != NULL)
+		kfree(b_srp_wait_tmr);
+	if (b_data_pulse_tmr != NULL)
+		kfree(b_data_pulse_tmr);
+	if (b_vbus_pulse_tmr != NULL)
+		kfree(b_vbus_pulse_tmr);
+}
+
+/* Add timer to timer list */
+void fsl_otg_add_timer(void *gtimer)
+{
+	struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
+	struct fsl_otg_timer *tmp_timer;
+
+	/* Check if the timer is already in the active list,
+	 * if so update timer count
+	 */
+	list_for_each_entry(tmp_timer, &active_timers, list)
+	    if (tmp_timer == timer) {
+		timer->count = timer->expires;
+		return;
+	}
+	timer->count = timer->expires;
+	list_add_tail(&timer->list, &active_timers);
+}
+
+/* Remove timer from the timer list; clear timeout status */
+void fsl_otg_del_timer(void *gtimer)
+{
+	struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
+	struct fsl_otg_timer *tmp_timer, *del_tmp;
+
+	list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
+		if (tmp_timer == timer)
+			list_del(&timer->list);
+}
+
+/* Reduce timer count by 1, and find timeout conditions.
+ * Called by fsl_otg 1ms timer interrupt
+ */
+int fsl_otg_tick_timer(void)
+{
+	struct fsl_otg_timer *tmp_timer, *del_tmp;
+	int expired = 0;
+
+	list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
+		tmp_timer->count--;
+		/* check if timer expires */
+		if (!tmp_timer->count) {
+			list_del(&tmp_timer->list);
+			tmp_timer->function(tmp_timer->data);
+			expired = 1;
+		}
+	}
+
+	return expired;
+}
+
+/* Reset controller, not reset the bus */
+void otg_reset_controller(void)
+{
+	u32 command;
+
+	command = readl(&usb_dr_regs->usbcmd);
+	command |= (1 << 1);
+	writel(command, &usb_dr_regs->usbcmd);
+	while (readl(&usb_dr_regs->usbcmd) & (1 << 1)) ;
+}
+
+/* Call suspend/resume routines in host driver */
+int fsl_otg_start_host(struct otg_fsm *fsm, int on)
+{
+	struct otg_transceiver *xceiv = fsm->transceiver;
+	struct device *dev;
+	struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg);
+	struct platform_driver *host_pdrv;
+	struct platform_device *host_pdev;
+	u32 retval = 0;
+
+	if (!xceiv->host)
+		return -ENODEV;
+	dev = xceiv->host->controller;
+	host_pdrv = container_of((dev->driver), struct platform_driver, driver);
+	host_pdev = to_platform_device(dev);
+
+	/* Update a_vbus_vld state as a_vbus_vld int is disabled
+	 * in device mode
+	 */
+	fsm->a_vbus_vld =
+	    (le32_to_cpu(usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID) ? 1 : 0;
+	if (on) {
+		/* start fsl usb host controller */
+		if (otg_dev->host_working)
+			goto end;
+		else {
+			otg_reset_controller();
+			VDBG("host on......\n");
+			if (host_pdrv->resume) {
+				retval = host_pdrv->resume(host_pdev);
+				if (fsm->id) {
+					/* default-b */
+					fsl_otg_drv_vbus(dev->platform_data, 1);
+					/* Workaround: b_host can't driver
+					 * vbus, but PP in PORTSC needs to
+					 * be 1 for host to work.
+					 * So we set drv_vbus bit in
+					 * transceiver to 0 thru ULPI. */
+#if defined(CONFIG_ISP1504_MXC)
+					write_ulpi(0x0c, 0x20);
+#endif
+				}
+			}
+
+			otg_dev->host_working = 1;
+		}
+	} else {
+		/* stop fsl usb host controller */
+		if (!otg_dev->host_working)
+			goto end;
+		else {
+			VDBG("host off......\n");
+			if (host_pdrv->suspend) {
+				retval = host_pdrv->suspend(host_pdev,
+							otg_suspend_state);
+				if (fsm->id)
+					/* default-b */
+					fsl_otg_drv_vbus(dev->platform_data, 0);
+			}
+			otg_dev->host_working = 0;
+		}
+	}
+end:
+	return retval;
+}
+
+/* Call suspend and resume function in udc driver
+ * to stop and start udc driver.
+ */
+int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
+{
+	struct otg_transceiver *xceiv = fsm->transceiver;
+	struct device *dev;
+	struct platform_driver *gadget_pdrv;
+	struct platform_device *gadget_pdev;
+
+	if (!xceiv->gadget || !xceiv->gadget->dev.parent)
+		return -ENODEV;
+
+	VDBG("gadget %s \n", on ? "on" : "off");
+	dev = xceiv->gadget->dev.parent;
+
+	gadget_pdrv = container_of((dev->driver),
+			struct platform_driver, driver);
+	gadget_pdev = to_platform_device(dev);
+
+	if (on)
+		gadget_pdrv->resume(gadget_pdev);
+	else
+		gadget_pdrv->suspend(gadget_pdev, otg_suspend_state);
+
+	return 0;
+}
+
+/* Called by initialization code of host driver.  Register host controller
+ * to the OTG.  Suspend host for OTG role detection.
+ */
+static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
+{
+	struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+	if (!otg_p || otg_dev != fsl_otg_dev)
+		return -ENODEV;
+
+	otg_p->host = host;
+
+	otg_dev->fsm.a_bus_drop = 0;
+	otg_dev->fsm.a_bus_req = 1;
+
+	if (host) {
+		VDBG("host off......\n");
+
+		otg_p->host->otg_port = fsl_otg_initdata.otg_port;
+		otg_p->host->is_b_host = otg_dev->fsm.id;
+		/* must leave time for khubd to finish its thing
+		 * before yanking the host driver out from under it,
+		 * so suspend the host after a short delay.
+		 */
+		otg_dev->host_working = 1;
+		schedule_delayed_work(&otg_dev->otg_event, 100);
+		return 0;
+	} else {		/* host driver going away */
+
+		if (!(le32_to_cpu(otg_dev->dr_mem_map->otgsc) &
+		      OTGSC_STS_USB_ID)) {
+			/* Mini-A cable connected */
+			struct otg_fsm *fsm = &otg_dev->fsm;
+
+			otg_p->state = OTG_STATE_UNDEFINED;
+			fsm->protocol = PROTO_UNDEF;
+		}
+		if (gpio_id) {
+			if (gpio_get_value(gpio_id)) {
+				struct otg_fsm *fsm = &otg_dev->fsm;
+				otg_p->state = OTG_STATE_UNDEFINED;
+				fsm->protocol = PROTO_UNDEF;
+			}
+		}
+	}
+
+	otg_dev->host_working = 0;
+
+	otg_statemachine(&otg_dev->fsm);
+
+	return 0;
+}
+
+/* Called by initialization code of udc.  Register udc to OTG.*/
+static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p,
+				  struct usb_gadget *gadget)
+{
+	struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+	VDBG("otg_dev 0x%x\n", (int)otg_dev);
+	VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
+
+	if (!otg_p || otg_dev != fsl_otg_dev)
+		return -ENODEV;
+
+	if (!gadget) {
+		if (!otg_dev->otg.default_a)
+			otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
+		usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
+		otg_dev->otg.gadget = 0;
+		otg_dev->fsm.b_bus_req = 0;
+		otg_statemachine(&otg_dev->fsm);
+		return 0;
+	}
+#ifdef DEBUG
+	/*
+	 * debug the initial state of the ID pin when only
+	 * the gadget driver is loaded and no cable is connected.
+	 * sometimes, we get an ID irq right
+	 * after the udc driver's otg_get_transceiver() call
+	 * that indicates that IDpin=0, which means a Mini-A
+	 * connector is attached.  not good.
+	 */
+	DBG("before: fsm.id ID pin=%d", otg_dev->fsm.id);
+	otg_dev->fsm.id = (otg_dev->dr_mem_map->otgsc & OTGSC_STS_USB_ID) ?
+	    1 : 0;
+	DBG("after:  fsm.id ID pin=%d", otg_dev->fsm.id);
+	/*if (!otg_dev->fsm.id) {
+	   printk("OTG Control = 0x%x\n",
+	   isp1504_read(ISP1504_OTGCTL,
+	   &otg_dev->dr_mem_map->ulpiview));
+	   } */
+#endif
+
+	otg_p->gadget = gadget;
+	otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
+
+	otg_dev->fsm.b_bus_req = 1;
+
+	/* start the gadget right away if the ID pin says Mini-B */
+	DBG("ID pin=%d\n", otg_dev->fsm.id);
+	if (otg_dev->fsm.id == 1) {
+		fsl_otg_start_host(&otg_dev->fsm, 0);
+		otg_drv_vbus(&otg_dev->fsm, 0);
+		fsl_otg_start_gadget(&otg_dev->fsm, 1);
+	}
+
+	return 0;
+}
+
+/* Set OTG port power, only for B-device */
+static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA)
+{
+	if (!fsl_otg_dev)
+		return -ENODEV;
+	if (otg_p->state == OTG_STATE_B_PERIPHERAL)
+		printk(KERN_INFO "FSL OTG:Draw %d mA\n", mA);
+
+	return 0;
+}
+
+/* Delayed pin detect interrupt processing.
+ *
+ * When the Mini-A cable is disconnected from the board,
+ * the pin-detect interrupt happens before the disconnnect
+ * interrupts for the connected device(s).  In order to
+ * process the disconnect interrupt(s) prior to switching
+ * roles, the pin-detect interrupts are delayed, and handled
+ * by this routine.
+ */
+static void fsl_otg_event(struct work_struct *work)
+{
+	struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
+	struct otg_fsm *fsm = &og->fsm;
+
+	if (fsm->id) {		/* switch to gadget */
+		fsl_otg_start_host(fsm, 0);
+		otg_drv_vbus(fsm, 0);
+		fsl_otg_start_gadget(fsm, 1);
+	}
+}
+
+/* B-device start SRP */
+static int fsl_otg_start_srp(struct otg_transceiver *otg_p)
+{
+	struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+	if (!otg_p || otg_dev != fsl_otg_dev
+	    || otg_p->state != OTG_STATE_B_IDLE)
+		return -ENODEV;
+
+	otg_dev->fsm.b_bus_req = 1;
+	otg_statemachine(&otg_dev->fsm);
+
+	return 0;
+}
+
+/* A_host suspend will call this function to start hnp */
+static int fsl_otg_start_hnp(struct otg_transceiver *otg_p)
+{
+	struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+	if (!otg_p || otg_dev != fsl_otg_dev)
+		return -ENODEV;
+
+	/* printk("start_hnp.............\n"); */
+	/* clear a_bus_req to enter a_suspend state */
+	otg_dev->fsm.a_bus_req = 0;
+	otg_statemachine(&otg_dev->fsm);
+
+	return 0;
+}
+/* Interrupt handler for gpio id pin */
+irqreturn_t fsl_otg_isr_gpio(int irq, void *dev_id)
+{
+	struct otg_fsm *fsm;
+	struct fsl_usb2_platform_data *pdata =
+		(struct fsl_usb2_platform_data *)dev_id;
+	struct fsl_otg *p_otg;
+	struct otg_transceiver *otg_trans = otg_get_transceiver();
+	int value;
+	p_otg = container_of(otg_trans, struct fsl_otg, otg);
+	fsm = &p_otg->fsm;
+
+	if (pdata->id_gpio == 0)
+		return IRQ_NONE;
+
+	value = gpio_get_value(pdata->id_gpio) ? 1 : 0;
+
+	if (value)
+		set_irq_type(gpio_to_irq(pdata->id_gpio), IRQ_TYPE_LEVEL_LOW);
+	else
+		set_irq_type(gpio_to_irq(pdata->id_gpio), IRQ_TYPE_LEVEL_HIGH);
+
+
+	if (value == p_otg->fsm.id)
+		return IRQ_HANDLED;
+
+	p_otg->fsm.id = value;
+
+	otg_trans->default_a = (fsm->id == 0);
+	/* clear conn information */
+	if (fsm->id)
+		fsm->b_conn = 0;
+	else
+		fsm->a_conn = 0;
+
+	if (otg_trans->host)
+		otg_trans->host->is_b_host = fsm->id;
+	if (otg_trans->gadget)
+		otg_trans->gadget->is_a_peripheral = !fsm->id;
+
+	VDBG("ID int (ID is %d)\n", fsm->id);
+	if (fsm->id) {  /* switch to gadget */
+		schedule_delayed_work(&p_otg->otg_event, 100);
+
+	} else {        /* switch to host */
+		cancel_delayed_work(&p_otg->otg_event);
+		fsl_otg_start_gadget(fsm, 0);
+		otg_drv_vbus(fsm, 1);
+		fsl_otg_start_host(fsm, 1);
+	}
+	return IRQ_HANDLED;
+}
+/* Interrupt handler.  OTG/host/peripheral share the same int line.
+ * OTG driver clears OTGSC interrupts and leaves USB interrupts
+ * intact.  It needs to have knowledge of some USB interrupts
+ * such as port change.
+ */
+irqreturn_t fsl_otg_isr(int irq, void *dev_id)
+{
+	struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
+	struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
+	u32 otg_int_src, otg_sc;
+
+	otg_sc = le32_to_cpu(usb_dr_regs->otgsc);
+	otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
+
+	/* Only clear otg interrupts */
+	usb_dr_regs->otgsc |= cpu_to_le32(otg_sc & OTGSC_INTSTS_MASK);
+
+	/*FIXME: ID change not generate when init to 0 */
+	fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
+	otg->default_a = (fsm->id == 0);
+
+	/* process OTG interrupts */
+	if (otg_int_src) {
+		if (otg_int_src & OTGSC_INTSTS_USB_ID) {
+			fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
+			otg->default_a = (fsm->id == 0);
+			/* clear conn information */
+			if (fsm->id)
+				fsm->b_conn = 0;
+			else
+				fsm->a_conn = 0;
+
+			if (otg->host)
+				otg->host->is_b_host = fsm->id;
+			if (otg->gadget)
+				otg->gadget->is_a_peripheral = !fsm->id;
+			VDBG("ID int (ID is %d)\n", fsm->id);
+
+			if (fsm->id) {	/* switch to gadget */
+				schedule_delayed_work(&((struct fsl_otg *)
+							dev_id)->otg_event,
+							100);
+			} else {	/* switch to host */
+				cancel_delayed_work(&
+						    ((struct fsl_otg *)dev_id)->
+						    otg_event);
+				fsl_otg_start_gadget(fsm, 0);
+				otg_drv_vbus(fsm, 1);
+				fsl_otg_start_host(fsm, 1);
+			}
+
+			return IRQ_HANDLED;
+		}
+	}
+
+	return IRQ_NONE;
+}
+
+static void fsl_otg_fsm_drv_vbus(int on)
+{
+	struct otg_fsm *fsm = &(fsl_otg_dev->fsm);
+	struct otg_transceiver *xceiv = fsm->transceiver;
+	struct device *dev;
+	/*
+	 * The host is assigned at otg_set_host
+	 */
+	if (!xceiv->host)
+		return;
+	/*
+	 * The dev is assigned at usb_create_hcd which is called earlier
+	 * than otg_set_host at host driver's probe
+	 */
+	dev = xceiv->host->controller;
+	fsl_otg_drv_vbus(dev->platform_data, on);
+}
+
+static struct otg_fsm_ops fsl_otg_ops = {
+	.chrg_vbus = fsl_otg_chrg_vbus,
+	.drv_vbus = fsl_otg_fsm_drv_vbus,
+	.loc_conn = fsl_otg_loc_conn,
+	.loc_sof = fsl_otg_loc_sof,
+	.start_pulse = fsl_otg_start_pulse,
+
+	.add_timer = fsl_otg_add_timer,
+	.del_timer = fsl_otg_del_timer,
+
+	.start_host = fsl_otg_start_host,
+	.start_gadget = fsl_otg_start_gadget,
+};
+
+/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
+static int fsl_otg_conf(struct platform_device *pdev)
+{
+	int status;
+	struct fsl_otg *fsl_otg_tc;
+	struct fsl_usb2_platform_data *pdata;
+
+	pdata = pdev->dev.platform_data;
+
+	DBG();
+
+	if (fsl_otg_dev)
+		return 0;
+
+	/* allocate space to fsl otg device */
+	fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
+	if (!fsl_otg_tc)
+		return -ENODEV;
+
+	INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
+
+	INIT_LIST_HEAD(&active_timers);
+	status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
+	if (status) {
+		printk(KERN_INFO "Couldn't init OTG timers\n");
+		fsl_otg_uninit_timers();
+		kfree(fsl_otg_tc);
+		return status;
+	}
+	spin_lock_init(&fsl_otg_tc->fsm.lock);
+
+	/* Set OTG state machine operations */
+	fsl_otg_tc->fsm.ops = &fsl_otg_ops;
+
+	/* initialize the otg structure */
+	fsl_otg_tc->otg.label = DRIVER_DESC;
+	fsl_otg_tc->otg.set_host = fsl_otg_set_host;
+	fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral;
+	fsl_otg_tc->otg.set_power = fsl_otg_set_power;
+	fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp;
+	fsl_otg_tc->otg.start_srp = fsl_otg_start_srp;
+
+	fsl_otg_dev = fsl_otg_tc;
+
+	/* Store the otg transceiver */
+	status = otg_set_transceiver(&fsl_otg_tc->otg);
+	if (status) {
+		printk(KERN_WARNING ": unable to register OTG transceiver.\n");
+		return status;
+	}
+
+	return 0;
+}
+
+/* OTG Initialization*/
+int usb_otg_start(struct platform_device *pdev)
+{
+	struct fsl_otg *p_otg;
+	struct otg_transceiver *otg_trans = otg_get_transceiver();
+	struct otg_fsm *fsm;
+	volatile unsigned long *p;
+	int status;
+	struct resource *res;
+	u32 temp;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	p_otg = container_of(otg_trans, struct fsl_otg, otg);
+	fsm = &p_otg->fsm;
+
+	/* Initialize the state machine structure with default values */
+	SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
+	fsm->transceiver = &p_otg->otg;
+
+	/* We don't require predefined MEM/IRQ resource index */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	/* We don't request_mem_region here to enable resource sharing
+	 * with host/device */
+
+	usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
+	p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
+	pdata->regs = (void *)usb_dr_regs;
+
+	gpio_id = pdata->id_gpio;
+	/* request irq */
+	if (pdata->id_gpio == 0) {
+		p_otg->irq = platform_get_irq(pdev, 0);
+		status = request_irq(p_otg->irq, fsl_otg_isr,
+				IRQF_SHARED, driver_name, p_otg);
+	} else {
+		status = request_irq(gpio_to_irq(pdata->id_gpio),
+					fsl_otg_isr_gpio,
+					IRQF_SHARED, driver_name, pdata);
+	}
+	if (status) {
+		dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n",
+			p_otg->irq, status);
+		iounmap(p_otg->dr_mem_map);
+		kfree(p_otg);
+		return status;
+	}
+
+	if (pdata->platform_init && pdata->platform_init(pdev) != 0)
+		return -EINVAL;
+
+	/* stop the controller */
+	temp = readl(&p_otg->dr_mem_map->usbcmd);
+	temp &= ~USB_CMD_RUN_STOP;
+	writel(temp, &p_otg->dr_mem_map->usbcmd);
+
+	/* reset the controller */
+	temp = readl(&p_otg->dr_mem_map->usbcmd);
+	temp |= USB_CMD_CTRL_RESET;
+	writel(temp, &p_otg->dr_mem_map->usbcmd);
+
+	/* wait reset completed */
+	while (readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET) ;
+
+	/* configure the VBUSHS as IDLE(both host and device) */
+	temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
+	writel(temp, &p_otg->dr_mem_map->usbmode);
+
+	/* configure PHY interface */
+	temp = readl(&p_otg->dr_mem_map->portsc);
+	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
+	switch (pdata->phy_mode) {
+	case FSL_USB2_PHY_ULPI:
+		temp |= PORTSC_PTS_ULPI;
+		break;
+	case FSL_USB2_PHY_UTMI_WIDE:
+		temp |= PORTSC_PTW_16BIT;
+		/* fall through */
+	case FSL_USB2_PHY_UTMI:
+		temp |= PORTSC_PTS_UTMI;
+		/* fall through */
+	default:
+		break;
+	}
+	writel(temp, &p_otg->dr_mem_map->portsc);
+
+	if (pdata->have_sysif_regs) {
+		/* configure control enable IO output, big endian register */
+		p = (volatile unsigned long *)(&p_otg->dr_mem_map->control);
+		temp = *p;
+		temp |= USB_CTRL_IOENB;
+		*p = temp;
+	}
+
+	/* disable all interrupt and clear all OTGSC status */
+	temp = readl(&p_otg->dr_mem_map->otgsc);
+	temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
+	temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
+	writel(temp, &p_otg->dr_mem_map->otgsc);
+
+
+	/*
+	 * The identification (id) input is FALSE when a Mini-A plug is inserted
+	 * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
+	 * Also: record initial state of ID pin
+	 */
+	if (le32_to_cpu(p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
+		p_otg->fsm.id = 1;
+	} else {
+		p_otg->fsm.id = 0;
+	}
+
+	if (pdata->id_gpio != 0) {
+		p_otg->fsm.id = gpio_get_value(pdata->id_gpio) ? 1 : 0;
+		if (p_otg->fsm.id)
+			set_irq_type(gpio_to_irq(pdata->id_gpio),
+				IRQ_TYPE_LEVEL_LOW);
+		else
+			set_irq_type(gpio_to_irq(pdata->id_gpio),
+				IRQ_TYPE_LEVEL_HIGH);
+	}
+	p_otg->otg.state = p_otg->fsm.id ? OTG_STATE_UNDEFINED :
+					   OTG_STATE_A_IDLE;
+
+	DBG("initial ID pin=%d\n", p_otg->fsm.id);
+
+	/* enable OTG ID pin interrupt */
+	temp = readl(&p_otg->dr_mem_map->otgsc);
+	if (!pdata->id_gpio)
+		temp |= OTGSC_INTR_USB_ID_EN;
+	temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
+
+	writel(temp, &p_otg->dr_mem_map->otgsc);
+
+	return 0;
+}
+
+/*-------------------------------------------------------------------------
+		PROC File System Support
+-------------------------------------------------------------------------*/
+#ifdef CONFIG_USB_OTG_DEBUG_FILES
+
+#include <linux/seq_file.h>
+
+static const char proc_filename[] = "driver/isp1504_otg";
+
+static int otg_proc_read(char *page, char **start, off_t off, int count,
+			 int *eof, void *_dev)
+{
+	struct otg_fsm *fsm = &fsl_otg_dev->fsm;
+	char *buf = page;
+	char *next = buf;
+	unsigned size = count;
+	unsigned long flags;
+	int t;
+	u32 tmp_reg;
+
+	if (off != 0)
+		return 0;
+
+	spin_lock_irqsave(&fsm->lock, flags);
+
+	/* ------basic driver infomation ---- */
+	t = scnprintf(next, size,
+		      DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
+		      DRIVER_VERSION);
+	size -= t;
+	next += t;
+
+	/* ------ Registers ----- */
+	tmp_reg = le32_to_cpu(usb_dr_regs->otgsc);
+	t = scnprintf(next, size, "OTGSC reg: %08x\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	tmp_reg = le32_to_cpu(usb_dr_regs->portsc);
+	t = scnprintf(next, size, "PORTSC reg: %08x\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	tmp_reg = le32_to_cpu(usb_dr_regs->usbmode);
+	t = scnprintf(next, size, "USBMODE reg: %08x\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	tmp_reg = le32_to_cpu(usb_dr_regs->usbcmd);
+	t = scnprintf(next, size, "USBCMD reg: %08x\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	tmp_reg = le32_to_cpu(usb_dr_regs->usbsts);
+	t = scnprintf(next, size, "USBSTS reg: %08x\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	/* ------ State ----- */
+	t = scnprintf(next, size,
+		      "OTG state: %s\n\n",
+		      state_string(fsl_otg_dev->otg.state));
+	size -= t;
+	next += t;
+
+#if 1 || defined DEBUG
+	/* ------ State Machine Variables ----- */
+	t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld);
+	size -= t;
+	next += t;
+
+	t = scnprintf(next, size, "id: %d\n", fsm->id);
+	size -= t;
+	next += t;
+#endif
+
+	spin_unlock_irqrestore(&fsm->lock, flags);
+
+	*eof = 1;
+	return count - size;
+}
+
+#define create_proc_file()	create_proc_read_entry(proc_filename, \
+				0, NULL, otg_proc_read, NULL)
+
+#define remove_proc_file()	remove_proc_entry(proc_filename, NULL)
+
+#else				/* !CONFIG_USB_OTG_DEBUG_FILES */
+
+#define create_proc_file()	do {} while (0)
+#define remove_proc_file()	do {} while (0)
+
+#endif				/*CONFIG_USB_OTG_DEBUG_FILES */
+
+/*----------------------------------------------------------*/
+/* Char driver interface to control some OTG input */
+
+/* This function handle some ioctl command,such as get otg
+ * status and set host suspend
+ */
+static int fsl_otg_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	u32 retval = 0;
+
+	switch (cmd) {
+	case GET_OTG_STATUS:
+		retval = fsl_otg_dev->host_working;
+		break;
+
+	case SET_A_SUSPEND_REQ:
+		fsl_otg_dev->fsm.a_suspend_req = arg;
+		break;
+
+	case SET_A_BUS_DROP:
+		fsl_otg_dev->fsm.a_bus_drop = arg;
+		break;
+
+	case SET_A_BUS_REQ:
+		fsl_otg_dev->fsm.a_bus_req = arg;
+		break;
+
+	case SET_B_BUS_REQ:
+		fsl_otg_dev->fsm.b_bus_req = arg;
+		break;
+
+	default:
+		break;
+	}
+
+	otg_statemachine(&fsl_otg_dev->fsm);
+
+	return retval;
+}
+
+static int fsl_otg_open(struct inode *inode, struct file *file)
+{
+
+	return 0;
+}
+
+static int fsl_otg_release(struct inode *inode, struct file *file)
+{
+
+	return 0;
+}
+
+static struct file_operations otg_fops = {
+	.owner = THIS_MODULE,
+	.llseek = NULL,
+	.read = NULL,
+	.write = NULL,
+	.ioctl = fsl_otg_ioctl,
+	.open = fsl_otg_open,
+	.release = fsl_otg_release,
+};
+
+static int __init fsl_otg_probe(struct platform_device *pdev)
+{
+	int status;
+	struct fsl_usb2_platform_data *pdata;
+
+	DBG("pdev=0x%p\n", pdev);
+
+	if (!pdev)
+		return -ENODEV;
+
+	if (!pdev->dev.platform_data)
+		return -ENOMEM;
+
+	pdata = pdev->dev.platform_data;
+
+	/* configure the OTG */
+	status = fsl_otg_conf(pdev);
+	if (status) {
+		printk(KERN_INFO "Couldn't init OTG module\n");
+		return -status;
+	}
+
+	/* start OTG */
+	status = usb_otg_start(pdev);
+
+	if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) {
+		printk(KERN_WARNING FSL_OTG_NAME
+		       ": unable to register FSL OTG device\n");
+		return -EIO;
+	}
+
+	create_proc_file();
+	return status;
+}
+
+static int fsl_otg_remove(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	otg_set_transceiver(NULL);
+	free_irq(fsl_otg_dev->irq, fsl_otg_dev);
+
+	iounmap((void *)usb_dr_regs);
+
+	kfree(fsl_otg_dev);
+
+	remove_proc_file();
+
+	unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
+
+	if (pdata->platform_uninit)
+		pdata->platform_uninit(pdata);
+
+	return 0;
+}
+
+struct platform_driver fsl_otg_driver = {
+	.probe = fsl_otg_probe,
+	.remove = fsl_otg_remove,
+	.driver = {
+		.name = driver_name,
+		.owner = THIS_MODULE,
+	},
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __init fsl_usb_otg_init(void)
+{
+	printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION);
+	return platform_driver_register(&fsl_otg_driver);
+}
+
+static void __exit fsl_usb_otg_exit(void)
+{
+	platform_driver_unregister(&fsl_otg_driver);
+	printk(KERN_INFO DRIVER_DESC " unloaded\n");
+}
+
+subsys_initcall(fsl_usb_otg_init);
+module_exit(fsl_usb_otg_exit);
+
+MODULE_DESCRIPTION(DRIVER_INFO);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/otg/fsl_otg.h b/drivers/usb/otg/fsl_otg.h
new file mode 100644
index 000000000000..41e105fb91fd
--- /dev/null
+++ b/drivers/usb/otg/fsl_otg.h
@@ -0,0 +1,412 @@
+/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "otg_fsm.h"
+#include <linux/usb/otg.h>
+#include <linux/ioctl.h>
+
+ /* USB Command  Register Bit Masks */
+#define USB_CMD_RUN_STOP		(0x1<<0  )
+#define USB_CMD_CTRL_RESET		(0x1<<1  )
+#define USB_CMD_PERIODIC_SCHEDULE_EN	(0x1<<4  )
+#define USB_CMD_ASYNC_SCHEDULE_EN	(0x1<<5  )
+#define USB_CMD_INT_AA_DOORBELL		(0x1<<6  )
+#define USB_CMD_ASP			(0x3<<8  )
+#define USB_CMD_ASYNC_SCH_PARK_EN	(0x1<<11 )
+#define USB_CMD_SUTW			(0x1<<13 )
+#define USB_CMD_ATDTW			(0x1<<14 )
+#define USB_CMD_ITC			(0xFF<<16)
+
+/* bit 15,3,2 are frame list size */
+#define USB_CMD_FRAME_SIZE_1024		(0x0<<15 | 0x0<<2)
+#define USB_CMD_FRAME_SIZE_512		(0x0<<15 | 0x1<<2)
+#define USB_CMD_FRAME_SIZE_256		(0x0<<15 | 0x2<<2)
+#define USB_CMD_FRAME_SIZE_128		(0x0<<15 | 0x3<<2)
+#define USB_CMD_FRAME_SIZE_64		(0x1<<15 | 0x0<<2)
+#define USB_CMD_FRAME_SIZE_32		(0x1<<15 | 0x1<<2)
+#define USB_CMD_FRAME_SIZE_16		(0x1<<15 | 0x2<<2)
+#define USB_CMD_FRAME_SIZE_8		(0x1<<15 | 0x3<<2)
+
+/* bit 9-8 are async schedule park mode count */
+#define USB_CMD_ASP_00			(0x0<<8)
+#define USB_CMD_ASP_01			(0x1<<8)
+#define USB_CMD_ASP_10			(0x2<<8)
+#define USB_CMD_ASP_11			(0x3<<8)
+#define USB_CMD_ASP_BIT_POS		(8)
+
+/* bit 23-16 are interrupt threshold control */
+#define USB_CMD_ITC_NO_THRESHOLD	(0x00<<16)
+#define USB_CMD_ITC_1_MICRO_FRM		(0x01<<16)
+#define USB_CMD_ITC_2_MICRO_FRM		(0x02<<16)
+#define USB_CMD_ITC_4_MICRO_FRM		(0x04<<16)
+#define USB_CMD_ITC_8_MICRO_FRM		(0x08<<16)
+#define USB_CMD_ITC_16_MICRO_FRM	(0x10<<16)
+#define USB_CMD_ITC_32_MICRO_FRM	(0x20<<16)
+#define USB_CMD_ITC_64_MICRO_FRM	(0x40<<16)
+#define USB_CMD_ITC_BIT_POS		(16)
+
+/* USB Status Register Bit Masks */
+#define USB_STS_INT			(0x1<<0 )
+#define USB_STS_ERR			(0x1<<1 )
+#define USB_STS_PORT_CHANGE		(0x1<<2 )
+#define USB_STS_FRM_LST_ROLL		(0x1<<3 )
+#define USB_STS_SYS_ERR			(0x1<<4 )
+#define USB_STS_IAA			(0x1<<5 )
+#define USB_STS_RESET_RECEIVED		(0x1<<6 )
+#define USB_STS_SOF			(0x1<<7 )
+#define USB_STS_DCSUSPEND		(0x1<<8 )
+#define USB_STS_HC_HALTED		(0x1<<12)
+#define USB_STS_RCL			(0x1<<13)
+#define USB_STS_PERIODIC_SCHEDULE	(0x1<<14)
+#define USB_STS_ASYNC_SCHEDULE		(0x1<<15)
+
+/* USB Interrupt Enable Register Bit Masks */
+#define USB_INTR_INT_EN			(0x1<<0 )
+#define USB_INTR_ERR_INT_EN		(0x1<<1 )
+#define USB_INTR_PC_DETECT_EN		(0x1<<2 )
+#define USB_INTR_FRM_LST_ROLL_EN	(0x1<<3 )
+#define USB_INTR_SYS_ERR_EN		(0x1<<4 )
+#define USB_INTR_ASYN_ADV_EN		(0x1<<5 )
+#define USB_INTR_RESET_EN		(0x1<<6 )
+#define USB_INTR_SOF_EN			(0x1<<7 )
+#define USB_INTR_DEVICE_SUSPEND		(0x1<<8 )
+
+/* Device Address bit masks */
+#define USB_DEVICE_ADDRESS_MASK		(0x7F<<25)
+#define USB_DEVICE_ADDRESS_BIT_POS	(25)
+/* PORTSC  Register Bit Masks,Only one PORT in OTG mode*/
+#define PORTSC_CURRENT_CONNECT_STATUS	(0x1<<0)
+#define PORTSC_CONNECT_STATUS_CHANGE	(0x1<<1)
+#define PORTSC_PORT_ENABLE		(0x1<<2)
+#define PORTSC_PORT_EN_DIS_CHANGE	(0x1<<3)
+#define PORTSC_OVER_CURRENT_ACT		(0x1<<4)
+#define PORTSC_OVER_CUURENT_CHG		(0x1<<5)
+#define PORTSC_PORT_FORCE_RESUME	(0x1<<6)
+#define PORTSC_PORT_SUSPEND		(0x1<<7)
+#define PORTSC_PORT_RESET		(0x1<<8)
+#define PORTSC_LINE_STATUS_BITS		(0x3<<10)
+#define PORTSC_PORT_POWER		(0x1<<12)
+#define PORTSC_PORT_INDICTOR_CTRL	(0x3<<14)
+#define PORTSC_PORT_TEST_CTRL		(0xF<<16)
+#define PORTSC_WAKE_ON_CONNECT_EN	(0x1<<20)
+#define PORTSC_WAKE_ON_CONNECT_DIS	(0x1<<21)
+#define PORTSC_WAKE_ON_OVER_CURRENT	(0x1<<22)
+#define PORTSC_PHY_LOW_POWER_SPD	(0x1<<23)
+#define PORTSC_PORT_FORCE_FULL_SPEED	(0x1<<24)
+#define PORTSC_PORT_SPEED_MASK		(0x3<<26)
+#define PORTSC_TRANSCEIVER_WIDTH	(0x1<<28)
+#define PORTSC_PHY_TYPE_SEL		(0x3<<30)
+/* bit 11-10 are line status */
+#define PORTSC_LINE_STATUS_SE0		(0x0<<10)
+#define PORTSC_LINE_STATUS_JSTATE	(0x1<<10)
+#define PORTSC_LINE_STATUS_KSTATE	(0x2<<10)
+#define PORTSC_LINE_STATUS_UNDEF	(0x3<<10)
+#define PORTSC_LINE_STATUS_BIT_POS	(10)
+
+/* bit 15-14 are port indicator control */
+#define PORTSC_PIC_OFF			(0x0<<14)
+#define PORTSC_PIC_AMBER		(0x1<<14)
+#define PORTSC_PIC_GREEN		(0x2<<14)
+#define PORTSC_PIC_UNDEF		(0x3<<14)
+#define PORTSC_PIC_BIT_POS		(14)
+
+/* bit 19-16 are port test control */
+#define PORTSC_PTC_DISABLE		(0x0<<16)
+#define PORTSC_PTC_JSTATE		(0x1<<16)
+#define PORTSC_PTC_KSTATE		(0x2<<16)
+#define PORTSC_PTC_SEQNAK		(0x3<<16)
+#define PORTSC_PTC_PACKET		(0x4<<16)
+#define PORTSC_PTC_FORCE_EN		(0x5<<16)
+#define PORTSC_PTC_BIT_POS		(16)
+
+/* bit 27-26 are port speed */
+#define PORTSC_PORT_SPEED_FULL		(0x0<<26)
+#define PORTSC_PORT_SPEED_LOW		(0x1<<26)
+#define PORTSC_PORT_SPEED_HIGH		(0x2<<26)
+#define PORTSC_PORT_SPEED_UNDEF		(0x3<<26)
+#define PORTSC_SPEED_BIT_POS		(26)
+
+/* bit 28 is parallel transceiver width for UTMI interface */
+#define PORTSC_PTW			(0x1<<28)
+#define PORTSC_PTW_8BIT			(0x0<<28)
+#define PORTSC_PTW_16BIT		(0x1<<28)
+
+/* bit 31-30 are port transceiver select */
+#define PORTSC_PTS_UTMI			(0x0<<30)
+#define PORTSC_PTS_ULPI			(0x2<<30)
+#define PORTSC_PTS_FSLS_SERIAL		(0x3<<30)
+#define PORTSC_PTS_BIT_POS		(30)
+
+#define PORTSC_W1C_BITS                    \
+       (PORTSC_CONNECT_STATUS_CHANGE |     \
+	PORTSC_PORT_EN_DIS_CHANGE    |     \
+	PORTSC_OVER_CUURENT_CHG)
+
+/* OTG Status Control Register Bit Masks */
+#define OTGSC_CTRL_VBUS_DISCHARGE	(0x1<<0)
+#define OTGSC_CTRL_VBUS_CHARGE		(0x1<<1)
+#define OTGSC_CTRL_OTG_TERMINATION	(0x1<<3)
+#define OTGSC_CTRL_DATA_PULSING		(0x1<<4)
+#define OTGSC_CTRL_ID_PULL_EN		(0x1<<5)
+#define OTGSC_HA_DATA_PULSE		(0x1<<6)
+#define OTGSC_HA_BA			(0x1<<7)
+#define OTGSC_STS_USB_ID		(0x1<<8)
+#define OTGSC_STS_A_VBUS_VALID		(0x1<<9)
+#define OTGSC_STS_A_SESSION_VALID	(0x1<<10)
+#define OTGSC_STS_B_SESSION_VALID	(0x1<<11)
+#define OTGSC_STS_B_SESSION_END		(0x1<<12)
+#define OTGSC_STS_1MS_TOGGLE		(0x1<<13)
+#define OTGSC_STS_DATA_PULSING		(0x1<<14)
+#define OTGSC_INTSTS_USB_ID		(0x1<<16)
+#define OTGSC_INTSTS_A_VBUS_VALID	(0x1<<17)
+#define OTGSC_INTSTS_A_SESSION_VALID	(0x1<<18)
+#define OTGSC_INTSTS_B_SESSION_VALID	(0x1<<19)
+#define OTGSC_INTSTS_B_SESSION_END	(0x1<<20)
+#define OTGSC_INTSTS_1MS		(0x1<<21)
+#define OTGSC_INTSTS_DATA_PULSING	(0x1<<22)
+#define OTGSC_INTR_USB_ID_EN		(0x1<<24)
+#define OTGSC_INTR_A_VBUS_VALID_EN	(0x1<<25)
+#define OTGSC_INTR_A_SESSION_VALID_EN	(0x1<<26)
+#define OTGSC_INTR_B_SESSION_VALID_EN	(0x1<<27)
+#define OTGSC_INTR_B_SESSION_END_EN	(0x1<<28)
+#define OTGSC_INTR_1MS_TIMER_EN		(0x1<<29)
+#define OTGSC_INTR_DATA_PULSING_EN	(0x1<<30)
+#define OTGSC_INTSTS_MASK		(0x00ff0000)
+
+/* USB MODE Register Bit Masks */
+#define  USB_MODE_CTRL_MODE_IDLE	(0x0<<0)
+#define  USB_MODE_CTRL_MODE_DEVICE	(0x2<<0)
+#define  USB_MODE_CTRL_MODE_HOST	(0x3<<0)
+#define  USB_MODE_CTRL_MODE_RSV		(0x1<<0)
+#define  USB_MODE_SETUP_LOCK_OFF	(0x1<<3)
+#define  USB_MODE_STREAM_DISABLE	(0x1<<4)
+#define  USB_MODE_ES			(0x1<<2) /* (big) Endian Select */
+
+#define MPC8349_OTG_IRQ			(38)
+#define CFG_IMMR_BASE	        	(0xfe000000)
+#define MPC83xx_USB_DR_BASE     	(CFG_IMMR_BASE + 0x23000)
+
+/* control Register Bit Masks */
+#define  USB_CTRL_IOENB			(0x1<<2)
+#define  USB_CTRL_ULPI_INT0EN		(0x1<<0)
+
+/* BCSR5 */
+#define BCSR5_INT_USB			(0x02)
+
+/* USB module clk cfg */
+#define SCCR_OFFS			(0xA08)
+#define SCCR_USB_CLK_DISABLE		(0x00000000)	/* USB clk disable */
+#define SCCR_USB_MPHCM_11		(0x00c00000)
+#define SCCR_USB_MPHCM_01		(0x00400000)
+#define SCCR_USB_MPHCM_10		(0x00800000)
+#define SCCR_USB_DRCM_11		(0x00300000)
+#define SCCR_USB_DRCM_01		(0x00100000)
+#define SCCR_USB_DRCM_10		(0x00200000)
+
+#define SICRL_OFFS			(0x114)
+#define SICRL_USB0			(0x40000000)
+#define SICRL_USB1			(0x20000000)
+
+#define SICRH_OFFS			(0x118)
+#define SICRH_USB_UTMI			(0x00020000)
+
+/* OTG interrupt enable bit masks */
+#define  OTGSC_INTERRUPT_ENABLE_BITS_MASK  \
+	(OTGSC_INTR_USB_ID_EN            | \
+	OTGSC_INTR_1MS_TIMER_EN          | \
+	OTGSC_INTR_A_VBUS_VALID_EN       | \
+	OTGSC_INTR_A_SESSION_VALID_EN    | \
+	OTGSC_INTR_B_SESSION_VALID_EN    | \
+	OTGSC_INTR_B_SESSION_END_EN      | \
+	OTGSC_INTR_DATA_PULSING_EN)
+
+/* OTG interrupt status bit masks */
+#define  OTGSC_INTERRUPT_STATUS_BITS_MASK  \
+	(OTGSC_INTSTS_USB_ID          |    \
+	OTGSC_INTR_1MS_TIMER_EN       |    \
+	OTGSC_INTSTS_A_VBUS_VALID     |    \
+	OTGSC_INTSTS_A_SESSION_VALID  |    \
+	OTGSC_INTSTS_B_SESSION_VALID  |    \
+	OTGSC_INTSTS_B_SESSION_END    |    \
+	OTGSC_INTSTS_DATA_PULSING)
+
+/*
+ *  A-DEVICE timing  constants
+ */
+
+/* Wait for VBUS Rise  */
+#define TA_WAIT_VRISE	(100)	/* a_wait_vrise 100 ms, section: 6.6.5.1 */
+
+/* Wait for B-Connect */
+#define TA_WAIT_BCON	(10000)  /* a_wait_bcon > 1 sec, section: 6.6.5.2
+				  * This is only used to get out of
+				  * OTG_STATE_A_WAIT_BCON state if there was
+				  * no connection for these many milliseconds
+				  */
+
+/* A-Idle to B-Disconnect */
+/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
+ * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
+ * in the test description
+ */
+#define TA_AIDL_BDIS	(5000)	/* a_suspend minimum 200 ms, section: 6.6.5.3 */
+
+/* B-Idle to A-Disconnect */
+#define TA_BIDL_ADIS	(12)	/* 3 to 200 ms */
+
+/* B-device timing constants */
+
+
+/* Data-Line Pulse Time*/
+#define TB_DATA_PLS	(10)	/* b_srp_init,continue 5~10ms, section:5.3.3 */
+#define TB_DATA_PLS_MIN	(5)	/* minimum 5 ms */
+#define TB_DATA_PLS_MAX	(10)	/* maximum 10 ms */
+
+/* SRP Initiate Time  */
+#define TB_SRP_INIT	(100)	/* b_srp_init,maximum 100 ms, section:5.3.8 */
+
+/* SRP Fail Time  */
+#define TB_SRP_FAIL	(7000)	/* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
+
+/* SRP result wait time */
+#define TB_SRP_WAIT	(60)
+
+/* VBus time */
+#define TB_VBUS_PLS	(30)	/* time to keep vbus pulsing asserted */
+
+/* Discharge time */
+/* This time should be less than 10ms. It varies from system to system. */
+#define TB_VBUS_DSCHRG	(8)
+
+/* A-SE0 to B-Reset  */
+#define TB_ASE0_BRST	(20)	/* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
+
+/* A bus suspend timer before we can switch to b_wait_aconn */
+#define TB_A_SUSPEND	(7)
+#define TB_BUS_RESUME	(12)
+
+/* SE0 Time Before SRP */
+#define TB_SE0_SRP	(2)	/* b_idle,minimum 2 ms, section:5.3.2 */
+
+
+#define SET_OTG_STATE(otg_ptr, newstate)	((otg_ptr)->state=newstate)
+
+struct usb_dr_mmap {
+	/* Capability register */
+	u8 res1[256];
+	u16 caplength;		/* Capability Register Length */
+	u16 hciversion;		/* Host Controller Interface Version */
+	u32 hcsparams;		/* Host Controller Structual Parameters */
+	u32 hccparams;		/* Host Controller Capability Parameters */
+	u8 res2[20];
+	u32 dciversion;		/* Device Controller Interface Version */
+	u32 dccparams;		/* Device Controller Capability Parameters */
+	u8 res3[24];
+	/* Operation register */
+	u32 usbcmd;		/* USB Command Register */
+	u32 usbsts;		/* USB Status Register */
+	u32 usbintr;		/* USB Interrupt Enable Register */
+	u32 frindex;		/* Frame Index Register */
+	u8 res4[4];
+	u32 deviceaddr;		/* Device Address */
+	u32 endpointlistaddr;	/* Endpoint List Address Register */
+	u8 res5[4];
+	u32 burstsize;		/* Master Interface Data Burst Size Register */
+	u32 txttfilltuning;	/* Transmit FIFO Tuning Controls Register */
+	u8 res6[8];
+	u32 ulpiview;		/* ULPI register access */
+	u8 res7[12];
+	u32 configflag;		/* Configure Flag Register */
+	u32 portsc;		/* Port 1 Status and Control Register */
+	u8 res8[28];
+	u32 otgsc;		/* On-The-Go Status and Control */
+	u32 usbmode;		/* USB Mode Register */
+	u32 endptsetupstat;	/* Endpoint Setup Status Register */
+	u32 endpointprime;	/* Endpoint Initialization Register */
+	u32 endptflush;		/* Endpoint Flush Register */
+	u32 endptstatus;	/* Endpoint Status Register */
+	u32 endptcomplete;	/* Endpoint Complete Register */
+	u32 endptctrl[6];	/* Endpoint Control Registers */
+	u8 res9[552];
+	u32 snoop1;
+	u32 snoop2;
+	u32 age_cnt_thresh;	/* Age Count Threshold Register */
+	u32 pri_ctrl;		/* Priority Control Register */
+	u32 si_ctrl;		/* System Interface Control Register */
+	u8 res10[236];
+#ifdef CONFIG_ARCH_MX5
+	u32 res11[128];
+#endif
+	u32 control;		/* General Purpose Control Register */
+};
+
+
+struct fsl_otg_timer {
+	unsigned long expires;	/* Number of count increase to timeout */
+	unsigned long count;	/* Tick counter */
+	void (*function)(unsigned long);	/* Timeout function */
+	unsigned long data;	/* Data passed to function */
+	struct list_head list;
+};
+
+struct fsl_otg_timer inline *otg_timer_initializer
+(void (*function)(unsigned long), unsigned long expires, unsigned long data)
+{
+	struct fsl_otg_timer *timer;
+	timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
+	if (timer == NULL)
+		return NULL;
+	timer->function = function;
+	timer->expires = expires;
+	timer->data = data;
+	return timer;
+}
+
+struct fsl_otg {
+	struct otg_transceiver otg;
+	struct otg_fsm fsm;
+	struct usb_dr_mmap *dr_mem_map;
+	struct delayed_work otg_event;
+
+	/*used for usb host */
+	struct work_struct work_wq;
+	u8	host_working;
+
+	int irq;
+};
+
+struct fsl_otg_config {
+	u8 otg_port;
+};
+
+/*For SRP and HNP handle*/
+#define FSL_OTG_MAJOR	66
+#define FSL_OTG_NAME	"fsl-usb2-otg"
+/*Command to OTG driver(ioctl)*/
+#define OTG_IOCTL_MAGIC		FSL_OTG_MAJOR
+/*if otg work as host,it should return 1,otherwise it return 0*/
+#define GET_OTG_STATUS		_IOR(OTG_IOCTL_MAGIC, 1, int)
+#define SET_A_SUSPEND_REQ	_IOW(OTG_IOCTL_MAGIC, 2, int)
+#define SET_A_BUS_DROP		_IOW(OTG_IOCTL_MAGIC, 3, int)
+#define SET_A_BUS_REQ		_IOW(OTG_IOCTL_MAGIC, 4, int)
+#define SET_B_BUS_REQ		_IOW(OTG_IOCTL_MAGIC, 5, int)
+#define GET_A_SUSPEND_REQ	_IOR(OTG_IOCTL_MAGIC, 6, int)
+#define GET_A_BUS_DROP		_IOR(OTG_IOCTL_MAGIC, 7, int)
+#define GET_A_BUS_REQ		_IOR(OTG_IOCTL_MAGIC, 8, int)
+#define GET_B_BUS_REQ		_IOR(OTG_IOCTL_MAGIC, 9, int)
+
+extern const char *state_string(enum usb_otg_state state);
diff --git a/drivers/usb/otg/otg_fsm.c b/drivers/usb/otg/otg_fsm.c
new file mode 100644
index 000000000000..955b21cdd609
--- /dev/null
+++ b/drivers/usb/otg/otg_fsm.c
@@ -0,0 +1,371 @@
+/* OTG Finite State Machine from OTG spec
+ *
+ * Copyright (C) 2006-2008 Freescale Semiconductor, Inc.
+ *
+ * Author: 	Li Yang <LeoLi@freescale.com>
+ * 		Jerry Huang <Chang-Ming.Huang@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/usb/otg.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/usb.h>
+#include <linux/usb/gadget.h>
+
+#include <asm/types.h>
+#include "otg_fsm.h"
+
+
+/* Defined by device specific driver, for different timer implementation */
+extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
+	*b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr;
+
+const char *state_string(enum usb_otg_state state)
+{
+	switch (state) {
+	case OTG_STATE_A_IDLE:		return "a_idle";
+	case OTG_STATE_A_WAIT_VRISE:	return "a_wait_vrise";
+	case OTG_STATE_A_WAIT_BCON:	return "a_wait_bcon";
+	case OTG_STATE_A_HOST:		return "a_host";
+	case OTG_STATE_A_SUSPEND:	return "a_suspend";
+	case OTG_STATE_A_PERIPHERAL:	return "a_peripheral";
+	case OTG_STATE_A_WAIT_VFALL:	return "a_wait_vfall";
+	case OTG_STATE_A_VBUS_ERR:	return "a_vbus_err";
+	case OTG_STATE_B_IDLE:		return "b_idle";
+	case OTG_STATE_B_SRP_INIT:	return "b_srp_init";
+	case OTG_STATE_B_PERIPHERAL:	return "b_peripheral";
+	case OTG_STATE_B_WAIT_ACON:	return "b_wait_acon";
+	case OTG_STATE_B_HOST:		return "b_host";
+	default:			return "UNDEFINED";
+	}
+}
+
+/* Change USB protocol when there is a protocol change */
+static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
+{
+	int ret = 0;
+
+	if (fsm->protocol != protocol) {
+		VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
+				fsm->protocol, protocol);
+		/* stop old protocol */
+		if (fsm->protocol == PROTO_HOST)
+			ret = fsm->ops->start_host(fsm, 0);
+		else if (fsm->protocol == PROTO_GADGET)
+			ret = fsm->ops->start_gadget(fsm, 0);
+		if (ret)
+			return ret;
+
+		/* start new protocol */
+		if (protocol == PROTO_HOST)
+			ret = fsm->ops->start_host(fsm, 1);
+		else if (protocol == PROTO_GADGET)
+			ret = fsm->ops->start_gadget(fsm, 1);
+		if (ret)
+			return ret;
+
+		fsm->protocol = protocol;
+		return 0;
+	}
+
+	return 0;
+}
+
+static int state_changed;
+
+/* Called when leaving a state.  Do state clean up jobs here */
+void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
+{
+	switch (old_state) {
+	case OTG_STATE_B_IDLE:
+		otg_del_timer(fsm, b_se0_srp_tmr);
+		fsm->b_se0_srp = 0;
+		break;
+	case OTG_STATE_B_SRP_INIT:
+		fsm->b_srp_done = 0;
+		break;
+	case OTG_STATE_B_PERIPHERAL:
+		break;
+	case OTG_STATE_B_WAIT_ACON:
+		otg_del_timer(fsm, b_ase0_brst_tmr);
+		fsm->b_ase0_brst_tmout = 0;
+		break;
+	case OTG_STATE_B_HOST:
+		break;
+	case OTG_STATE_A_IDLE:
+		break;
+	case OTG_STATE_A_WAIT_VRISE:
+		otg_del_timer(fsm, a_wait_vrise_tmr);
+		fsm->a_wait_vrise_tmout = 0;
+		break;
+	case OTG_STATE_A_WAIT_BCON:
+		otg_del_timer(fsm, a_wait_bcon_tmr);
+		fsm->a_wait_bcon_tmout = 0;
+		break;
+	case OTG_STATE_A_HOST:
+		otg_del_timer(fsm, a_wait_enum_tmr);
+		break;
+	case OTG_STATE_A_SUSPEND:
+		otg_del_timer(fsm, a_aidl_bdis_tmr);
+		fsm->a_aidl_bdis_tmout = 0;
+		fsm->a_suspend_req = 0;
+		break;
+	case OTG_STATE_A_PERIPHERAL:
+		break;
+	case OTG_STATE_A_WAIT_VFALL:
+		otg_del_timer(fsm, a_wait_vrise_tmr);
+		break;
+	case OTG_STATE_A_VBUS_ERR:
+		break;
+	default:
+		break;
+	}
+}
+
+/* Called when entering a state */
+int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
+{
+	state_changed = 1;
+	if (fsm->transceiver->state == new_state)
+		return 0;
+	VDBG("Set state: %s \n", state_string(new_state));
+	otg_leave_state(fsm, fsm->transceiver->state);
+	switch (new_state) {
+	case OTG_STATE_B_IDLE:
+		otg_drv_vbus(fsm, 0);
+		otg_chrg_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_UNDEF);
+		otg_add_timer(fsm, b_se0_srp_tmr);
+		break;
+	case OTG_STATE_B_SRP_INIT:
+		otg_start_pulse(fsm);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_UNDEF);
+		otg_add_timer(fsm, b_srp_fail_tmr);
+		break;
+	case OTG_STATE_B_PERIPHERAL:
+		otg_chrg_vbus(fsm, 0);
+		otg_loc_conn(fsm, 1);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_GADGET);
+		break;
+	case OTG_STATE_B_WAIT_ACON:
+		otg_chrg_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		otg_add_timer(fsm, b_ase0_brst_tmr);
+		fsm->a_bus_suspend = 0;
+		break;
+	case OTG_STATE_B_HOST:
+		otg_chrg_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 1);
+		otg_set_protocol(fsm, PROTO_HOST);
+		usb_bus_start_enum(fsm->transceiver->host,
+				fsm->transceiver->host->otg_port);
+		break;
+	case OTG_STATE_A_IDLE:
+		otg_drv_vbus(fsm, 0);
+		otg_chrg_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		break;
+	case OTG_STATE_A_WAIT_VRISE:
+		otg_drv_vbus(fsm, 1);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		otg_add_timer(fsm, a_wait_vrise_tmr);
+		break;
+	case OTG_STATE_A_WAIT_BCON:
+		otg_drv_vbus(fsm, 1);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		otg_add_timer(fsm, a_wait_bcon_tmr);
+		break;
+	case OTG_STATE_A_HOST:
+		otg_drv_vbus(fsm, 1);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 1);
+		otg_set_protocol(fsm, PROTO_HOST);
+		/* When HNP is triggered while a_bus_req = 0, a_host will
+		 * suspend too fast to complete a_set_b_hnp_en */
+		if (!fsm->a_bus_req || fsm->a_suspend_req)
+			otg_add_timer(fsm, a_wait_enum_tmr);
+		break;
+	case OTG_STATE_A_SUSPEND:
+		otg_drv_vbus(fsm, 1);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		otg_add_timer(fsm, a_aidl_bdis_tmr);
+
+		break;
+	case OTG_STATE_A_PERIPHERAL:
+		otg_loc_conn(fsm, 1);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_GADGET);
+		otg_drv_vbus(fsm, 1);
+		break;
+	case OTG_STATE_A_WAIT_VFALL:
+		otg_drv_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_HOST);
+		break;
+	case OTG_STATE_A_VBUS_ERR:
+		otg_drv_vbus(fsm, 0);
+		otg_loc_conn(fsm, 0);
+		otg_loc_sof(fsm, 0);
+		otg_set_protocol(fsm, PROTO_UNDEF);
+		break;
+	default:
+		break;
+	}
+
+	fsm->transceiver->state = new_state;
+	return 0;
+}
+
+/* State change judgement */
+int otg_statemachine(struct otg_fsm *fsm)
+{
+	enum usb_otg_state state;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsm->lock, flags);
+
+	state = fsm->transceiver->state;
+	state_changed = 0;
+	/* State machine state change judgement */
+
+	switch (state) {
+	case OTG_STATE_UNDEFINED:
+		VDBG("fsm->id = %d \n", fsm->id);
+		if (fsm->id)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		else
+			otg_set_state(fsm, OTG_STATE_A_IDLE);
+		break;
+	case OTG_STATE_B_IDLE:
+		if (!fsm->id)
+			otg_set_state(fsm, OTG_STATE_A_IDLE);
+		else if (fsm->b_sess_vld && fsm->transceiver->gadget)
+			otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+		else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
+			otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
+		break;
+	case OTG_STATE_B_SRP_INIT:
+		if (!fsm->id || fsm->b_srp_done)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		break;
+	case OTG_STATE_B_PERIPHERAL:
+		if (!fsm->id || !fsm->b_sess_vld)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		else if (fsm->b_bus_req && fsm->transceiver->
+				gadget->b_hnp_enable && fsm->a_bus_suspend)
+			otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
+		break;
+	case OTG_STATE_B_WAIT_ACON:
+		if (fsm->a_conn)
+			otg_set_state(fsm, OTG_STATE_B_HOST);
+		else if (!fsm->id || !fsm->b_sess_vld)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
+			fsm->b_ase0_brst_tmout = 0;
+			otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+		}
+		break;
+	case OTG_STATE_B_HOST:
+		if (!fsm->id || !fsm->b_sess_vld)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		else if (!fsm->b_bus_req || !fsm->a_conn)
+			otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+		break;
+	case OTG_STATE_A_IDLE:
+		if (fsm->id)
+			otg_set_state(fsm, OTG_STATE_B_IDLE);
+		else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
+			otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
+		break;
+	case OTG_STATE_A_WAIT_VRISE:
+		if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
+				fsm->a_wait_vrise_tmout) {
+			otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+		}
+		break;
+	case OTG_STATE_A_WAIT_BCON:
+		if (!fsm->a_vbus_vld)
+			otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+		else if (fsm->b_conn)
+			otg_set_state(fsm, OTG_STATE_A_HOST);
+		else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+		break;
+	case OTG_STATE_A_HOST:
+		if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
+				fsm->transceiver->host->b_hnp_enable)
+			otg_set_state(fsm, OTG_STATE_A_SUSPEND);
+		else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+		else if (!fsm->a_vbus_vld)
+			otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+		break;
+	case OTG_STATE_A_SUSPEND:
+		if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable)
+			otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
+		else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+		else if (fsm->a_bus_req || fsm->b_bus_resume)
+			otg_set_state(fsm, OTG_STATE_A_HOST);
+		else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+		else if (!fsm->a_vbus_vld)
+			otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+		break;
+	case OTG_STATE_A_PERIPHERAL:
+		if (fsm->id || fsm->a_bus_drop)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+		else if (fsm->b_bus_suspend)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+		else if (!fsm->a_vbus_vld)
+			otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+		break;
+	case OTG_STATE_A_WAIT_VFALL:
+		if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
+					!fsm->b_conn))
+			otg_set_state(fsm, OTG_STATE_A_IDLE);
+		break;
+	case OTG_STATE_A_VBUS_ERR:
+		if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
+			otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+		break;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&fsm->lock, flags);
+
+	/*	VDBG("quit statemachine, changed = %d \n", state_changed); */
+	return state_changed;
+}
diff --git a/drivers/usb/otg/otg_fsm.h b/drivers/usb/otg/otg_fsm.h
new file mode 100644
index 000000000000..cd6894c80403
--- /dev/null
+++ b/drivers/usb/otg/otg_fsm.h
@@ -0,0 +1,151 @@
+/* Copyright (C) 2006-2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if 0
+#define DEBUG 	1
+#define VERBOSE	1
+#endif
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_DEBUG "j=%lu [%s] " fmt "\n", jiffies, \
+				 __func__, ## args)
+#else
+#define DBG(fmt, args...)	do {} while (0)
+#endif
+
+#ifdef VERBOSE
+#define VDBG		DBG
+#else
+#define VDBG(stuff...)	do {} while (0)
+#endif
+
+#ifdef VERBOSE
+#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
+#else
+#define MPC_LOC do {} while (0)
+#endif
+
+#define PROTO_UNDEF	(0)
+#define PROTO_HOST	(1)
+#define PROTO_GADGET	(2)
+
+/* OTG state machine according to the OTG spec */
+struct otg_fsm {
+	/* Input */
+	int a_bus_resume;
+	int a_bus_suspend;
+	int a_conn;
+	int a_sess_vld;
+	int a_srp_det;
+	int a_vbus_vld;
+	int b_bus_resume;
+	int b_bus_suspend;
+	int b_conn;
+	int b_se0_srp;
+	int b_sess_end;
+	int b_sess_vld;
+	int id;
+
+	/* Internal variables */
+	int a_set_b_hnp_en;
+	int b_srp_done;
+	int b_hnp_enable;
+
+	/* Timeout indicator for timers */
+	int a_wait_vrise_tmout;
+	int a_wait_bcon_tmout;
+	int a_aidl_bdis_tmout;
+	int b_ase0_brst_tmout;
+
+	/* Informative variables */
+	int a_bus_drop;
+	int a_bus_req;
+	int a_clr_err;
+	int a_suspend_req;
+	int b_bus_req;
+
+	/* Output */
+	int drv_vbus;
+	int loc_conn;
+	int loc_sof;
+
+	struct otg_fsm_ops *ops;
+	struct otg_transceiver *transceiver;
+
+	/* Current usb protocol used: 0:undefine; 1:host; 2:client */
+	int protocol;
+	spinlock_t lock;
+};
+
+struct otg_fsm_ops {
+	void	(*chrg_vbus)(int on);
+	void	(*drv_vbus)(int on);
+	void	(*loc_conn)(int on);
+	void	(*loc_sof)(int on);
+	void	(*start_pulse)(void);
+	void	(*add_timer)(void *timer);
+	void	(*del_timer)(void *timer);
+	int	(*start_host)(struct otg_fsm *fsm, int on);
+	int	(*start_gadget)(struct otg_fsm *fsm, int on);
+};
+
+
+static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
+{
+	fsm->ops->chrg_vbus(on);
+}
+
+static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
+{
+	if (fsm->drv_vbus != on) {
+		fsm->drv_vbus = on;
+		fsm->ops->drv_vbus(on);
+	}
+}
+
+static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
+{
+	if (fsm->loc_conn != on) {
+		fsm->loc_conn = on;
+		fsm->ops->loc_conn(on);
+	}
+}
+
+static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
+{
+	if (fsm->loc_sof != on) {
+		fsm->loc_sof = on;
+		fsm->ops->loc_sof(on);
+	}
+}
+
+static inline void otg_start_pulse(struct otg_fsm *fsm)
+{
+	fsm->ops->start_pulse();
+}
+
+static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
+{
+	fsm->ops->add_timer(timer);
+}
+
+static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
+{
+	fsm->ops->del_timer(timer);
+}
+
+int otg_statemachine(struct otg_fsm *fsm);
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index 8060b85fe1a3..11dd37de45c7 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -329,8 +329,11 @@ static int usb_stor_control_thread(void * __us)
 
 		/* we've got a command, let's do it! */
 		else {
-			US_DEBUG(usb_stor_show_command(us->srb));
-			us->proto_handler(us->srb, us);
+			US_DEBUGP(usb_stor_show_command(us->srb));
+#ifdef CONFIG_MACH_MX51_BABBAGE
+			if (us->srb->cmnd[0] != 0x85)
+#endif
+				us->proto_handler(us->srb, us);
 		}
 
 		/* lock access to the state */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3b54b3940178..1b3bd4429adc 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -381,6 +381,14 @@ config FB_CLPS711X
 	  Say Y to enable the Framebuffer driver for the CLPS7111 and
 	  EP7212 processors.
 
+if ARCH_MXC
+source "drivers/video/mxc/Kconfig"
+endif
+
+if ARCH_MXS
+source "drivers/video/mxs/Kconfig"
+endif
+
 config FB_SA1100
 	bool "SA-1100 LCD support"
 	depends on (FB = y) && ARM && ARCH_SA1100
@@ -1978,6 +1986,16 @@ config FB_PNX4008_DUM_RGB
 	---help---
 	  Say Y here to enable support for PNX4008 RGB Framebuffer
 
+config FB_STMP37XX
+	tristate "STMP 37XX LCD Framebuffer driver"
+	depends on FB && (ARCH_STMP37XX || ARCH_STMP378X)
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	---help---
+	  Say Y here to enable support for the framebuffer driver for the
+	  Sigmatel STMP37XX board.
+
 config FB_IBM_GXT4500
 	tristate "Framebuffer support for IBM GXT4500P adaptor"
 	depends on FB && PPC
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 01a819f47371..d3d951e0c4eb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -117,6 +117,9 @@ obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o
 obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
 obj-$(CONFIG_FB_PNX4008_DUM)	  += pnx4008/
 obj-$(CONFIG_FB_PNX4008_DUM_RGB)  += pnx4008/
+obj-$(CONFIG_FB_MXC)		  += mxc/
+obj-$(CONFIG_FB_MXS)		  += mxs/
+obj-$(CONFIG_FB_STMP37XX)	  += stmp37xxfb.o
 obj-$(CONFIG_FB_IBM_GXT4500)	  += gxt4500.o
 obj-$(CONFIG_FB_PS3)		  += ps3fb.o
 obj-$(CONFIG_FB_SM501)            += sm501fb.o
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index f9d19be05540..17432a6edfa0 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -229,3 +229,51 @@ config BACKLIGHT_SAHARA
 	help
 	  If you have a Tabletkiosk Sahara Touch-iT, say y to enable the
 	  backlight driver.
+
+menuconfig BACKLIGHT_MXC
+	bool "Freescale MXC/i.MX Backlight Drivers"
+	depends on BACKLIGHT_CLASS_DEVICE && ARCH_MXC
+	default y
+	help
+	  If you have a Freescale MC13783 PMIC, say y to enable the
+	  backlight driver.
+
+config BACKLIGHT_MXC_IPU
+	tristate "IPU PWM Backlight Driver"
+	depends on BACKLIGHT_MXC && MXC_IPU_V1
+	default y
+
+config BACKLIGHT_MXC_LCDC
+	tristate "LCDC PWM Backlight Driver"
+	depends on BACKLIGHT_MXC && (ARCH_MX21 || ARCH_MX27 || ARCH_MX25)
+	default y
+
+config BACKLIGHT_MXC_PMIC
+	tristate "PMIC Backlight Driver"
+	depends on BACKLIGHT_MXC && MXC_MC13783_LIGHT && MXC_MC13783_POWER
+	default y
+
+config BACKLIGHT_MXC_MC13892
+	tristate "Mc13892 Backlight Driver"
+	depends on BACKLIGHT_MXC && MXC_MC13892_LIGHT
+	default y
+
+config BACKLIGHT_STMP37XX
+	tristate "SigmaTel STMP37xx Backlight Driver"
+	depends on BACKLIGHT_CLASS_DEVICE && (ARCH_STMP37XX || ARCH_STMP378X)
+	default y
+	help
+	  If you have a STMP37xx, say y to enable the
+	  backlight driver.
+
+config BACKLIGHT_MXS
+	tristate "Freescale MXS Backlight Driver"
+	depends on BACKLIGHT_CLASS_DEVICE && ARCH_MXS
+	default y
+	help
+	  If you have a MXS, say y to enable the backlight driver.
+
+config BACKLIGHT_WM8350
+    tristate "WM8350 Backlight Driver"
+    depends on BACKLIGHT_MXC && REGULATOR_WM8350
+    default y
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 4eb178c1d684..2f530db27d5d 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -25,3 +25,10 @@ obj-$(CONFIG_BACKLIGHT_MBP_NVIDIA) += mbp_nvidia_bl.o
 obj-$(CONFIG_BACKLIGHT_TOSA)	+= tosa_bl.o
 obj-$(CONFIG_BACKLIGHT_SAHARA)	+= kb3886_bl.o
 
+obj-$(CONFIG_BACKLIGHT_MXC_LCDC) += mxc_lcdc_bl.o
+obj-$(CONFIG_BACKLIGHT_MXC_IPU)	+= mxc_ipu_bl.o
+obj-$(CONFIG_BACKLIGHT_MXC_PMIC) += mxc_pmic_bl.o
+obj-$(CONFIG_BACKLIGHT_WM8350) += wm8350_bl.o
+obj-$(CONFIG_BACKLIGHT_MXC_MC13892) += mxc_mc13892_bl.o
+obj-$(CONFIG_BACKLIGHT_STMP37XX) += stmp37xx_bl.o
+obj-$(CONFIG_BACKLIGHT_MXS) += mxs_bl.o
diff --git a/drivers/video/backlight/mxc_ipu_bl.c b/drivers/video/backlight/mxc_ipu_bl.c
new file mode 100644
index 000000000000..95b044cdd7e2
--- /dev/null
+++ b/drivers/video/backlight/mxc_ipu_bl.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @defgroup IPU_BL MXC IPU Backlight Driver
+ */
+/*!
+ * @file mxc_ipu_bl.c
+ *
+ * @brief Backlight Driver for IPU PWM on Freescale MXC/i.MX platforms.
+ *
+ * This file contains API defined in include/linux/clk.h for setting up and
+ * retrieving clocks.
+ *
+ * Based on Sharp's Corgi Backlight Driver
+ *
+ * @ingroup IPU_BL
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/ipu.h>
+
+#define MXC_MAX_INTENSITY 	255
+#define MXC_DEFAULT_INTENSITY 	127
+#define MXC_INTENSITY_OFF 	0
+
+struct mxcbl_dev_data {
+	int intensity;
+};
+
+static int fb_id;
+
+static int mxcbl_send_intensity(struct backlight_device *bd)
+{
+	int intensity = bd->props.brightness;
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+
+	ipu_sdc_set_brightness(intensity);
+
+	devdata->intensity = intensity;
+	return 0;
+}
+
+static int mxcbl_get_intensity(struct backlight_device *bd)
+{
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+	return devdata->intensity;
+}
+
+static int mxcbl_check_fb(struct fb_info *info)
+{
+	int id = info->fix.id[4] - '0';
+	if (id == fb_id) {
+		if ((id == 3) && !strcmp(info->fix.id, "DISP3 FG")) {
+			return 0;
+		}
+		return 1;
+	}
+	return 0;
+}
+
+static struct backlight_ops mxcbl_ops = {
+	.get_brightness = mxcbl_get_intensity,
+	.update_status = mxcbl_send_intensity,
+	.check_fb = mxcbl_check_fb,
+};
+
+static int __init mxcbl_probe(struct platform_device *pdev)
+{
+	struct backlight_device *bd;
+	struct mxcbl_dev_data *devdata;
+	int ret = 0;
+
+	devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL);
+	if (!devdata)
+		return -ENOMEM;
+	fb_id = (int)pdev->dev.platform_data;
+
+	bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata,
+				       &mxcbl_ops);
+	if (IS_ERR(bd)) {
+		ret = PTR_ERR(bd);
+		goto err0;
+	}
+	platform_set_drvdata(pdev, bd);
+
+	bd->props.brightness = MXC_DEFAULT_INTENSITY;
+	bd->props.max_brightness = MXC_MAX_INTENSITY;
+	bd->props.power = FB_BLANK_UNBLANK;
+	bd->props.fb_blank = FB_BLANK_UNBLANK;
+	backlight_update_status(bd);
+
+	printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev));
+	return 0;
+      err0:
+	kfree(devdata);
+	return ret;
+}
+
+static int mxcbl_remove(struct platform_device *pdev)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+
+	bd->props.brightness = MXC_INTENSITY_OFF;
+	backlight_update_status(bd);
+
+	backlight_device_unregister(bd);
+
+	return 0;
+}
+
+static struct platform_driver mxcbl_driver = {
+	.probe = mxcbl_probe,
+	.remove = mxcbl_remove,
+	.driver = {
+		   .name = "mxc_ipu_bl",
+		   },
+};
+
+static int __init mxcbl_init(void)
+{
+	return platform_driver_register(&mxcbl_driver);
+}
+
+static void __exit mxcbl_exit(void)
+{
+	platform_driver_unregister(&mxcbl_driver);
+}
+
+late_initcall(mxcbl_init);
+module_exit(mxcbl_exit);
+
+MODULE_DESCRIPTION("Freescale MXC/i.MX IPU PWM Backlight Driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/mxc_lcdc_bl.c b/drivers/video/backlight/mxc_lcdc_bl.c
new file mode 100644
index 000000000000..dce952d11950
--- /dev/null
+++ b/drivers/video/backlight/mxc_lcdc_bl.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @defgroup LCDC_BL MXC LCDC Backlight Driver
+ */
+/*!
+ * @file mxc_lcdc_bl.c
+ *
+ * @brief Backlight Driver for LCDC PWM on Freescale MXC/i.MX platforms.
+ *
+ * This file contains API defined in include/linux/clk.h for setting up and
+ * retrieving clocks.
+ *
+ * Based on Sharp's Corgi Backlight Driver
+ *
+ * @ingroup LCDC_BL
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/clk.h>
+
+#define MXC_MAX_INTENSITY 	255
+#define MXC_DEFAULT_INTENSITY 	127
+#define MXC_INTENSITY_OFF 	0
+
+extern void mx2fb_set_brightness(uint8_t);
+
+struct mxcbl_dev_data {
+	struct clk *clk;
+	int intensity;
+};
+
+static int mxcbl_send_intensity(struct backlight_device *bd)
+{
+	int intensity = bd->props.brightness;
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+
+	if ((devdata->intensity == 0) && (intensity != 0))
+		clk_enable(devdata->clk);
+
+	/* PWM contrast control register */
+	mx2fb_set_brightness(intensity);
+
+	if ((devdata->intensity != 0) && (intensity == 0))
+		clk_disable(devdata->clk);
+
+	devdata->intensity = intensity;
+	return 0;
+}
+
+static int mxcbl_get_intensity(struct backlight_device *bd)
+{
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+	return devdata->intensity;
+}
+
+static int mxcbl_check_fb(struct fb_info *info)
+{
+	if (strcmp(info->fix.id, "DISP0 BG") == 0) {
+		return 1;
+	}
+	return 0;
+}
+
+static struct backlight_ops mxcbl_ops = {
+	.get_brightness = mxcbl_get_intensity,
+	.update_status = mxcbl_send_intensity,
+	.check_fb = mxcbl_check_fb,
+};
+
+static int __init mxcbl_probe(struct platform_device *pdev)
+{
+	struct backlight_device *bd;
+	struct mxcbl_dev_data *devdata;
+	int ret = 0;
+
+	devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL);
+	if (!devdata)
+		return -ENOMEM;
+
+	devdata->clk = clk_get(NULL, "lcdc_clk");
+
+	bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata,
+				       &mxcbl_ops);
+	if (IS_ERR(bd)) {
+		ret = PTR_ERR(bd);
+		goto err0;
+	}
+	platform_set_drvdata(pdev, bd);
+
+	bd->props.brightness = MXC_DEFAULT_INTENSITY;
+	bd->props.max_brightness = MXC_MAX_INTENSITY;
+	bd->props.power = FB_BLANK_UNBLANK;
+	bd->props.fb_blank = FB_BLANK_UNBLANK;
+	mx2fb_set_brightness(MXC_DEFAULT_INTENSITY);
+
+	printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev));
+	return 0;
+      err0:
+	kfree(devdata);
+	return ret;
+}
+
+static int mxcbl_remove(struct platform_device *pdev)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+
+	bd->props.brightness = MXC_INTENSITY_OFF;
+	backlight_update_status(bd);
+
+	backlight_device_unregister(bd);
+
+	return 0;
+}
+
+static struct platform_driver mxcbl_driver = {
+	.probe = mxcbl_probe,
+	.remove = mxcbl_remove,
+	.driver = {
+		   .name = "mxc_lcdc_bl",
+		   },
+};
+
+static int __init mxcbl_init(void)
+{
+	return platform_driver_register(&mxcbl_driver);
+}
+
+static void __exit mxcbl_exit(void)
+{
+	platform_driver_unregister(&mxcbl_driver);
+}
+
+module_init(mxcbl_init);
+module_exit(mxcbl_exit);
+
+MODULE_DESCRIPTION("Freescale MXC/i.MX LCDC PWM Backlight Driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/mxc_mc13892_bl.c b/drivers/video/backlight/mxc_mc13892_bl.c
new file mode 100644
index 000000000000..6640dd5fce70
--- /dev/null
+++ b/drivers/video/backlight/mxc_mc13892_bl.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+
+#include <linux/pmic_light.h>
+#include <linux/pmic_external.h>
+
+/*
+#define MXC_MAX_INTENSITY 	255
+#define MXC_DEFAULT_INTENSITY 	127
+*/
+/* workaround for atlas hot issue */
+#define MXC_MAX_INTENSITY 	128
+#define MXC_DEFAULT_INTENSITY 	64
+
+#define MXC_INTENSITY_OFF 	0
+
+struct mxcbl_dev_data {
+	int intensity;
+	int suspend;
+};
+
+static int mxcbl_set_intensity(struct backlight_device *bd)
+{
+	int brightness = bd->props.brightness;
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		brightness = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		brightness = 0;
+	if (devdata->suspend)
+		brightness = 0;
+
+	brightness = brightness / 4;
+	mc13892_bklit_set_dutycycle(LIT_MAIN, brightness);
+	devdata->intensity = brightness;
+
+	return 0;
+}
+
+static int mxcbl_get_intensity(struct backlight_device *bd)
+{
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+	return devdata->intensity;
+}
+
+static int mxcbl_check_fb(struct fb_info *info)
+{
+	char *id = info->fix.id;
+
+	if (!strcmp(id, "DISP3 BG"))
+		return 1;
+	else
+		return 0;
+}
+
+static struct backlight_ops bl_ops;
+
+static int __init mxcbl_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct backlight_device *bd;
+	struct mxcbl_dev_data *devdata;
+	pmic_version_t pmic_version;
+
+	pr_debug("mc13892 backlight start probe\n");
+
+	devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL);
+	if (!devdata)
+		return -ENOMEM;
+
+	bl_ops.check_fb = mxcbl_check_fb;
+	bl_ops.get_brightness = mxcbl_get_intensity;
+	bl_ops.update_status = mxcbl_set_intensity;
+	bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata,
+				       &bl_ops);
+	if (IS_ERR(bd)) {
+		ret = PTR_ERR(bd);
+		goto err0;
+	}
+
+	platform_set_drvdata(pdev, bd);
+
+	/* according to LCD spec, current should be 18mA */
+	/* workaround for MC13892 TO1.1 crash issue, set current 6mA */
+	pmic_version = pmic_get_version();
+	if (pmic_version.revision < 20)
+		mc13892_bklit_set_current(LIT_MAIN, LIT_CURR_6);
+	else
+		mc13892_bklit_set_current(LIT_MAIN, LIT_CURR_18);
+	bd->props.brightness = MXC_DEFAULT_INTENSITY;
+	bd->props.max_brightness = MXC_MAX_INTENSITY;
+	bd->props.power = FB_BLANK_UNBLANK;
+	bd->props.fb_blank = FB_BLANK_UNBLANK;
+	backlight_update_status(bd);
+	pr_debug("mc13892 backlight probed successfully\n");
+	return 0;
+
+      err0:
+	kfree(devdata);
+	return ret;
+}
+
+static int mxcbl_remove(struct platform_device *pdev)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	kfree(devdata);
+	backlight_device_unregister(bd);
+	return 0;
+}
+
+static int mxcbl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	devdata->suspend = 1;
+	backlight_update_status(bd);
+	return 0;
+}
+
+static int mxcbl_resume(struct platform_device *pdev)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	devdata->suspend = 0;
+	backlight_update_status(bd);
+	return 0;
+}
+
+static struct platform_driver mxcbl_driver = {
+	.probe = mxcbl_probe,
+	.remove = mxcbl_remove,
+	.suspend = mxcbl_suspend,
+	.resume = mxcbl_resume,
+	.driver = {
+		   .name = "mxc_mc13892_bl",
+		   },
+};
+
+static int __init mxcbl_init(void)
+{
+	return platform_driver_register(&mxcbl_driver);
+}
+
+static void __exit mxcbl_exit(void)
+{
+	platform_driver_unregister(&mxcbl_driver);
+}
+
+module_init(mxcbl_init);
+module_exit(mxcbl_exit);
+
+MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/mxc_pmic_bl.c b/drivers/video/backlight/mxc_pmic_bl.c
new file mode 100644
index 000000000000..add55596e445
--- /dev/null
+++ b/drivers/video/backlight/mxc_pmic_bl.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*!
+ * @defgroup PMIC_BL MXC PMIC Backlight Driver
+ */
+/*!
+ * @file mxc_pmic_bl.c
+ *
+ * @brief PMIC Backlight Driver for Freescale MXC/i.MX platforms.
+ *
+ * This file contains API defined in include/linux/clk.h for setting up and
+ * retrieving clocks.
+ *
+ * Based on Sharp's Corgi Backlight Driver
+ *
+ * @ingroup PMIC_BL
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/pmic_light.h>
+
+#include <mach/pmic_power.h>
+
+#define MXC_MAX_INTENSITY 	255
+#define MXC_DEFAULT_INTENSITY 	127
+#define MXC_INTENSITY_OFF 	0
+
+struct mxcbl_dev_data {
+	int bl_id;
+	int intensity;
+	struct backlight_ops bl_ops;
+};
+
+static int pmic_bl_use_count;
+static int main_fb_id;
+static int sec_fb_id;
+
+static int mxcbl_send_intensity(struct backlight_device *bd)
+{
+	int intensity = bd->props.brightness;
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+
+	intensity = intensity / 16;
+	pmic_bklit_set_dutycycle(devdata->bl_id, intensity);
+
+	devdata->intensity = intensity;
+	return 0;
+}
+
+static int mxcbl_get_intensity(struct backlight_device *bd)
+{
+	struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev);
+	return devdata->intensity;
+}
+
+static int mxcbl_check_main_fb(struct fb_info *info)
+{
+	int id = info->fix.id[4] - '0';
+
+	if (id == main_fb_id) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static int mxcbl_check_sec_fb(struct fb_info *info)
+{
+	int id = info->fix.id[4] - '0';
+
+	if (id == sec_fb_id) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static int __init mxcbl_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct backlight_device *bd;
+	struct mxcbl_dev_data *devdata;
+
+	devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL);
+	if (!devdata)
+		return -ENOMEM;
+	devdata->bl_id = pdev->id;
+
+	if (pdev->id == 0) {
+		devdata->bl_ops.check_fb = mxcbl_check_main_fb;
+		main_fb_id = (int)pdev->dev.platform_data;
+	} else {
+		devdata->bl_ops.check_fb = mxcbl_check_sec_fb;
+		sec_fb_id = (int)pdev->dev.platform_data;
+	}
+
+	devdata->bl_ops.get_brightness = mxcbl_get_intensity;
+	devdata->bl_ops.update_status = mxcbl_send_intensity,
+	    bd =
+	    backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata,
+				      &devdata->bl_ops);
+	if (IS_ERR(bd)) {
+		ret = PTR_ERR(bd);
+		goto err0;
+	}
+
+	platform_set_drvdata(pdev, bd);
+
+	if (pmic_bl_use_count++ == 0) {
+		pmic_power_regulator_on(SW_SW3);
+		pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN);
+
+		pmic_bklit_tcled_master_enable();
+		pmic_bklit_enable_edge_slow();
+		pmic_bklit_set_cycle_time(0);
+	}
+
+	pmic_bklit_set_current(devdata->bl_id, 7);
+	bd->props.brightness = MXC_DEFAULT_INTENSITY;
+	bd->props.max_brightness = MXC_MAX_INTENSITY;
+	bd->props.power = FB_BLANK_UNBLANK;
+	bd->props.fb_blank = FB_BLANK_UNBLANK;
+	backlight_update_status(bd);
+
+	printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev));
+	return 0;
+      err0:
+	kfree(devdata);
+	return ret;
+}
+
+static int mxcbl_remove(struct platform_device *pdev)
+{
+	struct backlight_device *bd = platform_get_drvdata(pdev);
+
+	bd->props.brightness = MXC_INTENSITY_OFF;
+	backlight_update_status(bd);
+
+	if (--pmic_bl_use_count == 0) {
+		pmic_bklit_tcled_master_disable();
+
+		pmic_power_regulator_off(SW_SW3);
+		pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN);
+	}
+
+	backlight_device_unregister(bd);
+
+	printk("MXC Backlight Driver Unloaded\n");
+
+	return 0;
+}
+
+static struct platform_driver mxcbl_driver = {
+	.probe = mxcbl_probe,
+	.remove = mxcbl_remove,
+	.driver = {
+		   .name = "mxc_pmic_bl",
+		   },
+};
+
+static int __init mxcbl_init(void)
+{
+	return platform_driver_register(&mxcbl_driver);
+}
+
+static void __exit mxcbl_exit(void)
+{
+	platform_driver_unregister(&mxcbl_driver);
+}
+
+module_init(mxcbl_init);
+module_exit(mxcbl_exit);
+
+MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/mxs_bl.c b/drivers/video/backlight/mxs_bl.c
new file mode 100644
index 000000000000..2e2e9a8ebad4
--- /dev/null
+++ b/drivers/video/backlight/mxs_bl.c
@@ -0,0 +1,384 @@
+/*
+ * Backlight Driver for Freescale MXS
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/lcdif.h>
+#include <mach/regulator.h>
+
+struct mxs_bl_data {
+	struct notifier_block nb;
+	struct notifier_block reg_nb;
+	struct notifier_block reg_init_nb;
+	struct backlight_device *bd;
+	struct mxs_platform_bl_data *pdata;
+	int current_intensity;
+	int saved_intensity;
+	int mxsbl_suspended;
+	int mxsbl_constrained;
+};
+
+static int mxsbl_do_probe(struct mxs_bl_data *data,
+		struct mxs_platform_bl_data *pdata);
+static int mxsbl_set_intensity(struct backlight_device *bd);
+static inline void bl_register_reg(struct mxs_platform_bl_data *pdata,
+				   struct mxs_bl_data *data);
+
+
+/*
+ * If we got here init is done
+ */
+static int bl_init_reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	struct mxs_bl_data *bdata;
+	struct mxs_platform_bl_data *pdata;
+	struct regulator *r = regulator_get(NULL, "mxs-bl-1");
+
+	bdata = container_of(self, struct mxs_bl_data, reg_init_nb);
+	pdata = bdata->pdata;
+
+	if (r && !IS_ERR(r))
+		regulator_put(r);
+	else
+		goto out;
+
+	bl_register_reg(pdata, bdata);
+
+	if (pdata->regulator) {
+
+		printk(KERN_NOTICE"%s: setting intensity\n", __func__);
+
+		bus_unregister_notifier(&platform_bus_type,
+					&bdata->reg_init_nb);
+		mutex_lock(&bdata->bd->ops_lock);
+		mxsbl_set_intensity(bdata->bd);
+		mutex_unlock(&bdata->bd->ops_lock);
+	}
+
+out:
+	return 0;
+}
+
+static int bl_reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	struct mxs_bl_data *bdata;
+	struct mxs_platform_bl_data *pdata;
+	bdata = container_of(self, struct mxs_bl_data, reg_nb);
+	pdata = bdata->pdata;
+
+	mutex_lock(&bdata->bd->ops_lock);
+
+	switch (event) {
+	case MXS_REG5V_IS_USB:
+		bdata->bd->props.max_brightness = pdata->bl_cons_intensity;
+		bdata->bd->props.brightness = pdata->bl_cons_intensity;
+		bdata->saved_intensity = bdata->current_intensity;
+		bdata->mxsbl_constrained = 1;
+		break;
+	case MXS_REG5V_NOT_USB:
+		bdata->bd->props.max_brightness = pdata->bl_max_intensity;
+		bdata->bd->props.brightness = bdata->saved_intensity;
+		bdata->mxsbl_constrained = 0;
+		break;
+	}
+
+	mxsbl_set_intensity(bdata->bd);
+	mutex_unlock(&bdata->bd->ops_lock);
+	return 0;
+}
+
+static inline void bl_unregister_reg(struct mxs_platform_bl_data *pdata,
+				  struct mxs_bl_data *data)
+{
+	if (!pdata)
+		return;
+	if (pdata->regulator)
+		regulator_unregister_notifier(pdata->regulator,
+					    &data->reg_nb);
+	if (pdata->regulator)
+		regulator_put(pdata->regulator);
+	pdata->regulator = NULL;
+}
+
+static inline void bl_register_reg(struct mxs_platform_bl_data *pdata,
+				   struct mxs_bl_data *data)
+{
+	pdata->regulator = regulator_get(NULL, "mxs-bl-1");
+	if (pdata->regulator && !IS_ERR(pdata->regulator)) {
+		regulator_set_mode(pdata->regulator, REGULATOR_MODE_FAST);
+		if (pdata->regulator) {
+			data->reg_nb.notifier_call = bl_reg_callback;
+			regulator_register_notifier(pdata->regulator,
+						    &data->reg_nb);
+		}
+	} else{
+		printk(KERN_ERR "%s: failed to get regulator\n", __func__);
+		pdata->regulator = NULL;
+	}
+
+}
+
+static int bl_callback(struct notifier_block *self,
+		       unsigned long event, void *data)
+{
+	struct mxs_platform_fb_entry *pentry = data;
+	struct mxs_bl_data *bdata;
+	struct mxs_platform_bl_data *pdata;
+
+	switch (event) {
+	case MXS_LCDIF_PANEL_INIT:
+		bdata = container_of(self, struct mxs_bl_data, nb);
+		pdata = pentry->bl_data;
+		bdata->pdata = pdata;
+		if (pdata) {
+			bl_register_reg(pdata, bdata);
+			if (!pdata->regulator) {
+				/* wait for regulator to appear */
+				bdata->reg_init_nb.notifier_call =
+						bl_init_reg_callback;
+				bus_register_notifier(&platform_bus_type,
+						      &bdata->reg_init_nb);
+			}
+			return mxsbl_do_probe(bdata, pdata);
+		}
+		break;
+
+	case MXS_LCDIF_PANEL_RELEASE:
+		bdata = container_of(self, struct mxs_bl_data, nb);
+		pdata = pentry->bl_data;
+		if (pdata) {
+			bus_unregister_notifier(&platform_bus_type,
+						&bdata->reg_init_nb);
+			bl_unregister_reg(pdata, bdata);
+			pdata->free_bl(pdata);
+		}
+		bdata->pdata = NULL;
+		break;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxsbl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxs_bl_data *data = platform_get_drvdata(pdev);
+	struct mxs_platform_bl_data *pdata = data->pdata;
+
+	data->mxsbl_suspended = 1;
+	if (pdata) {
+		dev_dbg(&pdev->dev, "real suspend\n");
+		mxsbl_set_intensity(data->bd);
+	}
+	return 0;
+}
+
+static int mxsbl_resume(struct platform_device *pdev)
+{
+	struct mxs_bl_data *data = platform_get_drvdata(pdev);
+	struct mxs_platform_bl_data *pdata = data->pdata;
+	int ret = 0;
+
+	data->mxsbl_suspended = 0;
+	if (pdata) {
+		dev_dbg(&pdev->dev, "real resume\n");
+		pdata->free_bl(pdata);
+		ret = pdata->init_bl(pdata);
+		if (ret)
+			goto out;
+		mxsbl_set_intensity(data->bd);
+	}
+out:
+	return ret;
+}
+#else
+#define mxsbl_suspend	NULL
+#define mxsbl_resume	NULL
+#endif
+/*
+ *  This function should be called with bd->ops_lock held
+ *  Suspend/resume ?
+ */
+static int mxsbl_set_intensity(struct backlight_device *bd)
+{
+	struct platform_device *pdev = dev_get_drvdata(&bd->dev);
+	struct mxs_bl_data *data = platform_get_drvdata(pdev);
+	struct mxs_platform_bl_data *pdata = data->pdata;
+
+	if (pdata) {
+		int ret;
+
+		ret = pdata->set_bl_intensity(pdata, bd,
+					      data->mxsbl_suspended);
+		if (ret)
+			bd->props.brightness = data->current_intensity;
+		else
+			data->current_intensity = bd->props.brightness;
+		return ret;
+	} else
+		return -ENODEV;
+}
+
+static int mxsbl_get_intensity(struct backlight_device *bd)
+{
+	struct platform_device *pdev = dev_get_drvdata(&bd->dev);
+	struct mxs_bl_data *data = platform_get_drvdata(pdev);
+
+	return data->current_intensity;
+}
+
+static struct backlight_ops mxsbl_ops = {
+	.get_brightness = mxsbl_get_intensity,
+	.update_status  = mxsbl_set_intensity,
+};
+
+static int mxsbl_do_probe(struct mxs_bl_data *data,
+		struct mxs_platform_bl_data *pdata)
+{
+	int ret = pdata->init_bl(pdata);
+
+	if (ret)
+		goto out;
+
+	data->bd->props.power = FB_BLANK_UNBLANK;
+	data->bd->props.fb_blank = FB_BLANK_UNBLANK;
+	if (data->mxsbl_constrained) {
+		data->bd->props.max_brightness = pdata->bl_cons_intensity;
+		data->bd->props.brightness = pdata->bl_cons_intensity;
+	} else {
+		data->bd->props.max_brightness = pdata->bl_max_intensity;
+		data->bd->props.brightness = pdata->bl_default_intensity;
+	}
+
+	data->pdata = pdata;
+	mxsbl_set_intensity(data->bd);
+
+out:
+	return ret;
+}
+
+static int __init mxsbl_probe(struct platform_device *pdev)
+{
+	struct mxs_bl_data *data;
+	struct mxs_platform_bl_data *pdata = pdev->dev.platform_data;
+	int ret = 0;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	data->bd = backlight_device_register(pdev->name, &pdev->dev, pdev,
+					&mxsbl_ops);
+	if (IS_ERR(data->bd)) {
+		ret = PTR_ERR(data->bd);
+		goto out_1;
+	}
+
+	get_device(&pdev->dev);
+
+	data->nb.notifier_call = bl_callback;
+	mxs_lcdif_register_client(&data->nb);
+	platform_set_drvdata(pdev, data);
+
+	if (pdata) {
+		ret = mxsbl_do_probe(data, pdata);
+		if (ret)
+			goto out_2;
+	}
+
+	goto out;
+
+out_2:
+	put_device(&pdev->dev);
+out_1:
+	kfree(data);
+out:
+	return ret;
+}
+
+static int mxsbl_remove(struct platform_device *pdev)
+{
+	struct mxs_platform_bl_data *pdata = pdev->dev.platform_data;
+	struct mxs_bl_data *data = platform_get_drvdata(pdev);
+	struct backlight_device *bd = data->bd;
+
+	bd->props.power = FB_BLANK_POWERDOWN;
+	bd->props.fb_blank = FB_BLANK_POWERDOWN;
+	bd->props.brightness = 0;
+	data->current_intensity = bd->props.brightness;
+
+	if (pdata) {
+		pdata->set_bl_intensity(pdata, bd, data->mxsbl_suspended);
+		if (pdata->free_bl)
+			pdata->free_bl(pdata);
+	}
+	backlight_device_unregister(bd);
+	if (pdata->regulator)
+		regulator_put(pdata->regulator);
+	put_device(&pdev->dev);
+	platform_set_drvdata(pdev, NULL);
+	mxs_lcdif_unregister_client(&data->nb);
+	kfree(data);
+
+	return 0;
+}
+
+static struct platform_driver mxsbl_driver = {
+	.probe		= mxsbl_probe,
+	.remove		= __devexit_p(mxsbl_remove),
+	.suspend	= mxsbl_suspend,
+	.resume		= mxsbl_resume,
+	.driver		= {
+		.name	= "mxs-bl",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init mxs_init(void)
+{
+	return platform_driver_register(&mxsbl_driver);
+}
+
+static void __exit mxs_exit(void)
+{
+	platform_driver_unregister(&mxsbl_driver);
+}
+
+module_init(mxs_init);
+module_exit(mxs_exit);
+
+MODULE_AUTHOR("Embedded Alley Solutions, Inc <sources@embeddedalley.com>");
+MODULE_DESCRIPTION("MXS Backlight Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 887166267443..29024e83b36a 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -56,9 +56,19 @@ static int pwm_backlight_get_brightness(struct backlight_device *bl)
 	return bl->props.brightness;
 }
 
+static int pwm_backlight_check_fb(struct fb_info *info)
+{
+	char *id = info->fix.id;
+	if (!strcmp(id, "DISP3 BG"))
+	    return 1;
+	else
+	return 0;
+}
+
 static struct backlight_ops pwm_backlight_ops = {
 	.update_status	= pwm_backlight_update_status,
 	.get_brightness	= pwm_backlight_get_brightness,
+	.check_fb = pwm_backlight_check_fb,
 };
 
 static int pwm_backlight_probe(struct platform_device *pdev)
diff --git a/drivers/video/backlight/stmp37xx_bl.c b/drivers/video/backlight/stmp37xx_bl.c
new file mode 100644
index 000000000000..6b4d9a0ccbaa
--- /dev/null
+++ b/drivers/video/backlight/stmp37xx_bl.c
@@ -0,0 +1,378 @@
+/*
+ * Backlight Driver for Freescale STMP37XX/STMP378X
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/lcdif.h>
+#include <mach/regulator.h>
+
+struct stmp3xxx_bl_data {
+	struct notifier_block nb;
+	struct notifier_block reg_nb;
+	struct notifier_block reg_init_nb;
+	struct backlight_device *bd;
+	struct stmp3xxx_platform_bl_data *pdata;
+	int current_intensity;
+	int saved_intensity;
+	int stmp3xxxbl_suspended;
+	int stmp3xxxbl_constrained;
+};
+
+static int stmp3xxxbl_do_probe(struct stmp3xxx_bl_data *data,
+		struct stmp3xxx_platform_bl_data *pdata);
+static int stmp3xxxbl_set_intensity(struct backlight_device *bd);
+static inline void bl_register_reg(struct stmp3xxx_platform_bl_data *pdata,
+				   struct stmp3xxx_bl_data *data);
+
+
+/*
+ * If we got here init is done
+ */
+static int bl_init_reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	struct stmp3xxx_bl_data *bdata;
+	struct stmp3xxx_platform_bl_data *pdata;
+	struct regulator *r = regulator_get(NULL, "stmp3xxx-bl-1");
+
+	bdata = container_of(self, struct stmp3xxx_bl_data, reg_init_nb);
+	pdata = bdata->pdata;
+
+	if (r && !IS_ERR(r))
+		regulator_put(r);
+	else
+		goto out;
+
+	bl_register_reg(pdata, bdata);
+
+	if (pdata->regulator) {
+
+		printk(KERN_NOTICE"%s: setting intensity\n", __func__);
+
+		bus_unregister_notifier(&platform_bus_type,
+					&bdata->reg_init_nb);
+		mutex_lock(&bdata->bd->ops_lock);
+		stmp3xxxbl_set_intensity(bdata->bd);
+		mutex_unlock(&bdata->bd->ops_lock);
+	}
+
+out:
+	return 0;
+}
+
+static int bl_reg_callback(struct notifier_block *self,
+			unsigned long event, void *data)
+{
+	struct stmp3xxx_bl_data *bdata;
+	struct stmp3xxx_platform_bl_data *pdata;
+	bdata = container_of(self, struct stmp3xxx_bl_data, reg_nb);
+	pdata = bdata->pdata;
+
+	mutex_lock(&bdata->bd->ops_lock);
+
+	switch (event) {
+	case STMP3XXX_REG5V_IS_USB:
+		bdata->bd->props.max_brightness = pdata->bl_cons_intensity;
+		bdata->bd->props.brightness = pdata->bl_cons_intensity;
+		bdata->saved_intensity = bdata->current_intensity;
+		bdata->stmp3xxxbl_constrained = 1;
+		break;
+	case STMP3XXX_REG5V_NOT_USB:
+		bdata->bd->props.max_brightness = pdata->bl_max_intensity;
+		bdata->bd->props.brightness = bdata->saved_intensity;
+		bdata->stmp3xxxbl_constrained = 0;
+		break;
+	}
+
+	stmp3xxxbl_set_intensity(bdata->bd);
+	mutex_unlock(&bdata->bd->ops_lock);
+	return 0;
+}
+
+static inline void bl_unregister_reg(struct stmp3xxx_platform_bl_data *pdata,
+				  struct stmp3xxx_bl_data *data)
+{
+	if (!pdata)
+		return;
+	if (pdata->regulator)
+		regulator_unregister_notifier(pdata->regulator,
+					    &data->reg_nb);
+	if (pdata->regulator)
+		regulator_put(pdata->regulator);
+	pdata->regulator = NULL;
+}
+
+static inline void bl_register_reg(struct stmp3xxx_platform_bl_data *pdata,
+				   struct stmp3xxx_bl_data *data)
+{
+	pdata->regulator = regulator_get(NULL, "stmp3xxx-bl-1");
+	if (pdata->regulator && !IS_ERR(pdata->regulator)) {
+		regulator_set_mode(pdata->regulator, REGULATOR_MODE_FAST);
+		if (pdata->regulator) {
+			data->reg_nb.notifier_call = bl_reg_callback;
+			regulator_register_notifier(pdata->regulator,
+						    &data->reg_nb);
+		}
+	} else{
+		printk(KERN_ERR "%s: failed to get regulator\n", __func__);
+		pdata->regulator = NULL;
+	}
+
+}
+
+static int bl_callback(struct notifier_block *self,
+		       unsigned long event, void *data)
+{
+	struct stmp3xxx_platform_fb_entry *pentry = data;
+	struct stmp3xxx_bl_data *bdata;
+	struct stmp3xxx_platform_bl_data *pdata;
+
+	switch (event) {
+	case STMP3XXX_LCDIF_PANEL_INIT:
+		bdata = container_of(self, struct stmp3xxx_bl_data, nb);
+		pdata = pentry->bl_data;
+		bdata->pdata = pdata;
+		if (pdata) {
+			bl_register_reg(pdata, bdata);
+			if (!pdata->regulator) {
+				/* wait for regulator to appear */
+				bdata->reg_init_nb.notifier_call =
+						bl_init_reg_callback;
+				bus_register_notifier(&platform_bus_type,
+						      &bdata->reg_init_nb);
+			}
+			return stmp3xxxbl_do_probe(bdata, pdata);
+		}
+		break;
+
+	case STMP3XXX_LCDIF_PANEL_RELEASE:
+		bdata = container_of(self, struct stmp3xxx_bl_data, nb);
+		pdata = pentry->bl_data;
+		if (pdata) {
+			bus_unregister_notifier(&platform_bus_type,
+						&bdata->reg_init_nb);
+			bl_unregister_reg(pdata, bdata);
+			pdata->free_bl(pdata);
+		}
+		bdata->pdata = NULL;
+		break;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stmp3xxxbl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct stmp3xxx_bl_data *data = platform_get_drvdata(pdev);
+	struct stmp3xxx_platform_bl_data *pdata = data->pdata;
+
+	data->stmp3xxxbl_suspended = 1;
+	if (pdata) {
+		dev_dbg(&pdev->dev, "real suspend\n");
+		stmp3xxxbl_set_intensity(data->bd);
+	}
+	return 0;
+}
+
+static int stmp3xxxbl_resume(struct platform_device *pdev)
+{
+	struct stmp3xxx_bl_data *data = platform_get_drvdata(pdev);
+	struct stmp3xxx_platform_bl_data *pdata = data->pdata;
+	int ret = 0;
+
+	data->stmp3xxxbl_suspended = 0;
+	if (pdata) {
+		dev_dbg(&pdev->dev, "real resume\n");
+		pdata->free_bl(pdata);
+		ret = pdata->init_bl(pdata);
+		if (ret)
+			goto out;
+		stmp3xxxbl_set_intensity(data->bd);
+	}
+out:
+	return ret;
+}
+#else
+#define stmp3xxxbl_suspend	NULL
+#define stmp3xxxbl_resume	NULL
+#endif
+/*
+ *  This function should be called with bd->ops_lock held
+ *  Suspend/resume ?
+ */
+static int stmp3xxxbl_set_intensity(struct backlight_device *bd)
+{
+	struct platform_device *pdev = dev_get_drvdata(&bd->dev);
+	struct stmp3xxx_bl_data *data = platform_get_drvdata(pdev);
+	struct stmp3xxx_platform_bl_data *pdata = data->pdata;
+
+	if (pdata) {
+		int ret;
+
+		ret = pdata->set_bl_intensity(pdata, bd,
+					      data->stmp3xxxbl_suspended);
+		if (ret)
+			bd->props.brightness = data->current_intensity;
+		else
+			data->current_intensity = bd->props.brightness;
+		return ret;
+	} else
+		return -ENODEV;
+}
+
+static int stmp3xxxbl_get_intensity(struct backlight_device *bd)
+{
+	struct platform_device *pdev = dev_get_drvdata(&bd->dev);
+	struct stmp3xxx_bl_data *data = platform_get_drvdata(pdev);
+
+	return data->current_intensity;
+}
+
+static struct backlight_ops stmp3xxxbl_ops = {
+	.get_brightness = stmp3xxxbl_get_intensity,
+	.update_status  = stmp3xxxbl_set_intensity,
+};
+
+static int stmp3xxxbl_do_probe(struct stmp3xxx_bl_data *data,
+		struct stmp3xxx_platform_bl_data *pdata)
+{
+	int ret = pdata->init_bl(pdata);
+
+	if (ret)
+		goto out;
+
+	data->bd->props.power = FB_BLANK_UNBLANK;
+	data->bd->props.fb_blank = FB_BLANK_UNBLANK;
+	if (data->stmp3xxxbl_constrained) {
+		data->bd->props.max_brightness = pdata->bl_cons_intensity;
+		data->bd->props.brightness = pdata->bl_cons_intensity;
+	} else {
+		data->bd->props.max_brightness = pdata->bl_max_intensity;
+		data->bd->props.brightness = pdata->bl_default_intensity;
+	}
+
+	data->pdata = pdata;
+	stmp3xxxbl_set_intensity(data->bd);
+
+out:
+	return ret;
+}
+
+static int __init stmp3xxxbl_probe(struct platform_device *pdev)
+{
+	struct stmp3xxx_bl_data *data;
+	struct stmp3xxx_platform_bl_data *pdata = pdev->dev.platform_data;
+	int ret = 0;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	data->bd = backlight_device_register(pdev->name, &pdev->dev, pdev,
+					&stmp3xxxbl_ops);
+	if (IS_ERR(data->bd)) {
+		ret = PTR_ERR(data->bd);
+		goto out_1;
+	}
+
+	get_device(&pdev->dev);
+
+	data->nb.notifier_call = bl_callback;
+	stmp3xxx_lcdif_register_client(&data->nb);
+	platform_set_drvdata(pdev, data);
+
+	if (pdata) {
+		ret = stmp3xxxbl_do_probe(data, pdata);
+		if (ret)
+			goto out_2;
+	}
+
+	goto out;
+
+out_2:
+	put_device(&pdev->dev);
+out_1:
+	kfree(data);
+out:
+	return ret;
+}
+
+static int stmp3xxxbl_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_platform_bl_data *pdata = pdev->dev.platform_data;
+	struct stmp3xxx_bl_data *data = platform_get_drvdata(pdev);
+	struct backlight_device *bd = data->bd;
+
+	bd->props.power = FB_BLANK_POWERDOWN;
+	bd->props.fb_blank = FB_BLANK_POWERDOWN;
+	bd->props.brightness = 0;
+	data->current_intensity = bd->props.brightness;
+
+	if (pdata) {
+		pdata->set_bl_intensity(pdata, bd, data->stmp3xxxbl_suspended);
+		if (pdata->free_bl)
+			pdata->free_bl(pdata);
+	}
+	backlight_device_unregister(bd);
+	if (pdata->regulator)
+		regulator_put(pdata->regulator);
+	put_device(&pdev->dev);
+	platform_set_drvdata(pdev, NULL);
+	stmp3xxx_lcdif_unregister_client(&data->nb);
+	kfree(data);
+
+	return 0;
+}
+
+static struct platform_driver stmp3xxxbl_driver = {
+	.probe		= stmp3xxxbl_probe,
+	.remove		= __devexit_p(stmp3xxxbl_remove),
+	.suspend	= stmp3xxxbl_suspend,
+	.resume		= stmp3xxxbl_resume,
+	.driver		= {
+		.name	= "stmp3xxx-bl",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init stmp3xxx_init(void)
+{
+	return platform_driver_register(&stmp3xxxbl_driver);
+}
+
+static void __exit stmp3xxx_exit(void)
+{
+	platform_driver_unregister(&stmp3xxxbl_driver);
+}
+
+module_init(stmp3xxx_init);
+module_exit(stmp3xxx_exit);
+
+MODULE_AUTHOR("Embedded Alley Solutions, Inc <sources@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP3xxx Backlight Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/wm8350_bl.c b/drivers/video/backlight/wm8350_bl.c
new file mode 100644
index 000000000000..88014fba6b7e
--- /dev/null
+++ b/drivers/video/backlight/wm8350_bl.c
@@ -0,0 +1,298 @@
+/*
+ *  Backlight driver for DCDC2  on i.MX32ADS board
+ *
+ *  Copyright(C) 2007 Wolfson Microelectronics PLC.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mutex.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+#include <linux/backlight.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/wm8350/pmic.h>
+#include <linux/mfd/wm8350/bl.h>
+
+struct wm8350_backlight {
+	struct backlight_properties props;
+	struct backlight_device *device;
+	struct regulator *dcdc;
+	struct regulator *isink;
+	struct notifier_block notifier;
+	struct work_struct work;
+	struct mutex mutex;
+	int intensity;
+	int suspend;
+	int retries;
+};
+
+/* hundredths of uA, 405 = 4.05 uA */
+static const int intensity_huA[] = {
+	405, 482, 573, 681, 810, 963, 1146, 1362, 1620, 1927, 2291, 2725,
+	3240, 3853, 4582, 5449, 6480, 7706, 9164, 10898, 12960, 15412, 18328,
+	21796, 25920, 30824, 36656, 43592, 51840, 61648, 73313, 87184,
+	103680, 123297, 146626, 174368, 207360, 246594, 293251, 348737,
+	414720, 493188, 586503, 697473, 829440, 986376, 1173005, 1394946,
+	1658880, 1972752, 2346011, 2789892, 3317760, 3945504, 4692021,
+	5579785, 6635520, 7891008, 9384042, 11159570, 13271040, 15782015,
+	18768085, 22319140,
+};
+
+static void bl_work(struct work_struct *work)
+{
+	struct wm8350_backlight *bl =
+		container_of(work, struct wm8350_backlight, work);
+	struct regulator *isink = bl->isink;
+
+	mutex_lock(&bl->mutex);
+	if (bl->intensity >= 0 &&
+		bl->intensity < ARRAY_SIZE(intensity_huA)) {
+		bl->retries = 0;
+		regulator_set_current_limit(isink,
+			0, intensity_huA[bl->intensity] / 100);
+	} else
+		printk(KERN_ERR "wm8350: Backlight intensity error\n");
+	mutex_unlock(&bl->mutex);
+}
+
+static int wm8350_bl_notifier(struct notifier_block *self,
+	unsigned long event, void *data)
+{
+	struct wm8350_backlight *bl =
+		container_of(self, struct wm8350_backlight, notifier);
+	struct regulator *isink = bl->isink;
+
+	if (event & REGULATOR_EVENT_UNDER_VOLTAGE)
+		printk(KERN_ERR "wm8350: BL DCDC undervoltage\n");
+	if (event & REGULATOR_EVENT_REGULATION_OUT)
+		printk(KERN_ERR "wm8350: BL ISINK out of regulation\n");
+
+	mutex_lock(&bl->mutex);
+	if (bl->retries) {
+		bl->retries--;
+		regulator_disable(isink);
+		regulator_set_current_limit(isink, 0, bl->intensity);
+		regulator_enable(isink);
+	} else {
+		printk(KERN_ERR
+			"wm8350: BL regulation retry failure - disable\n");
+		bl->intensity = 0;
+		regulator_disable(isink);
+	}
+	mutex_unlock(&bl->mutex);
+	return 0;
+}
+
+static int wm8350_bl_send_intensity(struct backlight_device *bd)
+{
+	struct wm8350_backlight *bl =
+		(struct wm8350_backlight *)dev_get_drvdata(&bd->dev);
+	int intensity = bd->props.brightness;
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bl->suspend)
+		intensity = 0;
+
+	mutex_lock(&bl->mutex);
+	bl->intensity = intensity;
+	mutex_unlock(&bl->mutex);
+	schedule_work(&bl->work);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int wm8350_bl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct wm8350_backlight *bl =
+		(struct wm8350_backlight *)platform_get_drvdata(pdev);
+
+	bl->suspend = 1;
+	backlight_update_status(bl->device);
+	return 0;
+}
+
+static int wm8350_bl_resume(struct platform_device *pdev)
+{
+	struct wm8350_backlight *bl =
+		(struct wm8350_backlight *)platform_get_drvdata(pdev);
+
+	bl->suspend = 0;
+	backlight_update_status(bl->device);
+	return 0;
+}
+#else
+#define wm8350_bl_suspend	NULL
+#define wm8350_bl_resume	NULL
+#endif
+
+static int wm8350_bl_get_intensity(struct backlight_device *bd)
+{
+	struct wm8350_backlight *bl =
+		(struct wm8350_backlight *)dev_get_drvdata(&bd->dev);
+	return bl->intensity;
+}
+
+static struct backlight_ops wm8350_bl_ops = {
+	.get_brightness = wm8350_bl_get_intensity,
+	.update_status  = wm8350_bl_send_intensity,
+};
+
+static int wm8350_bl_probe(struct platform_device *pdev)
+{
+	struct regulator *isink, *dcdc;
+	struct wm8350_backlight *bl;
+	struct wm8350_bl_platform_data *pdata = pdev->dev.platform_data;
+	struct wm8350 *pmic;
+	int ret;
+
+	if (pdata == NULL) {
+		printk(KERN_ERR "%s: no platform data\n", __func__);
+		return -ENODEV;
+	}
+
+	if (pdata->isink != WM8350_ISINK_A && pdata->isink != WM8350_ISINK_B) {
+		printk(KERN_ERR "%s: invalid ISINK\n", __func__);
+		return -EINVAL;
+	}
+	if (pdata->dcdc != WM8350_DCDC_2 && pdata->dcdc != WM8350_DCDC_5) {
+		printk(KERN_ERR "%s: invalid DCDC\n", __func__);
+		return -EINVAL;
+	}
+
+	printk(KERN_INFO "wm8350: backlight using %s and %s\n",
+		pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB",
+		pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5");
+
+	isink = regulator_get(&pdev->dev,
+		pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB");
+	if (IS_ERR(isink) || isink == NULL) {
+		printk(KERN_ERR "%s: cant get ISINK\n", __func__);
+		return PTR_ERR(isink);
+	}
+
+	dcdc = regulator_get(&pdev->dev,
+		pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5");
+	if (IS_ERR(dcdc) || dcdc == NULL) {
+		printk(KERN_ERR "%s: cant get DCDC\n", __func__);
+		regulator_put(isink);
+		return PTR_ERR(dcdc);
+	}
+
+	bl = kzalloc(sizeof(*bl), GFP_KERNEL);
+	if (bl == NULL) {
+		regulator_put(isink);
+		regulator_put(dcdc);
+		return -ENOMEM;
+	}
+
+	mutex_init(&bl->mutex);
+	INIT_WORK(&bl->work, bl_work);
+	bl->props.max_brightness = pdata->max_brightness;
+	bl->props.power = pdata->power;
+	bl->props.brightness = pdata->brightness;
+	bl->retries = pdata->retries;
+	bl->dcdc = dcdc;
+	bl->isink = isink;
+	platform_set_drvdata(pdev, bl);
+	pmic = regulator_get_drvdata(bl->isink);
+
+	wm8350_bl_ops.check_fb = pdata->check_fb;
+
+	bl->device = backlight_device_register(dev_name(&pdev->dev), &pdev->dev,
+		bl, &wm8350_bl_ops);
+	if (IS_ERR(bl->device)) {
+		ret =  PTR_ERR(bl->device);
+		regulator_put(dcdc);
+		regulator_put(isink);
+		kfree(bl);
+		return ret;
+	}
+
+	bl->notifier.notifier_call = wm8350_bl_notifier;
+	regulator_register_notifier(dcdc, &bl->notifier);
+	regulator_register_notifier(isink, &bl->notifier);
+	bl->device->props = bl->props;
+
+	regulator_set_current_limit(isink, 0, 20000);
+
+	wm8350_isink_set_flash(pmic, pdata->isink,
+		WM8350_ISINK_FLASH_DISABLE,
+		WM8350_ISINK_FLASH_TRIG_BIT,
+		WM8350_ISINK_FLASH_DUR_32MS,
+		WM8350_ISINK_FLASH_ON_1_00S,
+		WM8350_ISINK_FLASH_OFF_1_00S,
+		WM8350_ISINK_FLASH_MODE_EN);
+
+	wm8350_dcdc25_set_mode(pmic, pdata->dcdc,
+		WM8350_ISINK_MODE_BOOST, WM8350_ISINK_ILIM_NORMAL,
+		pdata->voltage_ramp, pdata->isink == WM8350_ISINK_A ?
+		WM8350_DC5_FBSRC_ISINKA : WM8350_DC5_FBSRC_ISINKB);
+
+	wm8350_dcdc_set_slot(pmic, pdata->dcdc, 15, 0,
+		pdata->dcdc == WM8350_DCDC_2 ?
+		WM8350_DC2_ERRACT_SHUTDOWN_CONV : WM8350_DC5_ERRACT_NONE);
+
+	regulator_enable(isink);
+	backlight_update_status(bl->device);
+	return 0;
+}
+
+static int wm8350_bl_remove(struct platform_device *pdev)
+{
+	struct wm8350_backlight *bl =
+		(struct wm8350_backlight *)platform_get_drvdata(pdev);
+	struct regulator *isink = bl->isink, *dcdc = bl->dcdc;
+
+	bl->intensity = 0;
+	backlight_update_status(bl->device);
+	schedule_work(&bl->work);
+	flush_scheduled_work();
+	backlight_device_unregister(bl->device);
+
+	regulator_set_current_limit(isink, 0, 0);
+	regulator_disable(isink);
+	regulator_unregister_notifier(isink, &bl->notifier);
+	regulator_unregister_notifier(dcdc, &bl->notifier);
+	regulator_put(isink);
+	regulator_put(dcdc);
+	return 0;
+}
+
+struct platform_driver imx32ads_backlight_driver = {
+	.driver		= {
+		.name	= "wm8350-bl",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= wm8350_bl_probe,
+	.remove		= wm8350_bl_remove,
+	.suspend	= wm8350_bl_suspend,
+	.resume		= wm8350_bl_resume,
+};
+
+static int __devinit imx32ads_backlight_init(void)
+{
+	return platform_driver_register(&imx32ads_backlight_driver);
+}
+
+static void imx32ads_backlight_exit(void)
+{
+	platform_driver_unregister(&imx32ads_backlight_driver);
+}
+
+device_initcall_sync(imx32ads_backlight_init);
+module_exit(imx32ads_backlight_exit);
+
+MODULE_AUTHOR("Liam Girdwood <lg@opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("WM8350 Backlight driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig
new file mode 100644
index 000000000000..66a7f84c5656
--- /dev/null
+++ b/drivers/video/mxc/Kconfig
@@ -0,0 +1,103 @@
+config FB_MXC
+	tristate "MXC Framebuffer support"
+	depends on FB && (MXC_IPU || ARCH_MX21 || ARCH_MX27 || ARCH_MX25)
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	select FB_MODE_HELPERS
+	default y
+	help
+	  This is a framebuffer device for the MXC LCD Controller.
+	  See <http://www.linux-fbdev.org/> for information on framebuffer
+	  devices.
+
+	  If you plan to use the LCD display with your MXC system, say
+	  Y here.
+
+config FB_MXC_SYNC_PANEL
+	depends on FB_MXC
+	tristate "Synchronous Panel Framebuffer"
+	default y
+
+config FB_MXC_EPSON_VGA_SYNC_PANEL
+	depends on FB_MXC_SYNC_PANEL
+	tristate "Epson VGA Panel"
+	default n
+
+config FB_MXC_TVOUT_TVE
+	tristate "MXC TVE TV Out Encoder"
+	depends on FB_MXC_SYNC_PANEL
+	depends on MXC_IPU_V3
+
+config FB_MXC_LDB
+	tristate "MXC LDB"
+	depends on FB_MXC_SYNC_PANEL
+	depends on MXC_IPU_V3
+
+config FB_MXC_CLAA_WVGA_SYNC_PANEL
+	depends on FB_MXC_SYNC_PANEL
+	tristate "CLAA WVGA Panel"
+
+config FB_MXC_CH7026
+	depends on FB_MXC_SYNC_PANEL
+	tristate "Chrontel CH7026 VGA Interface Chip"
+
+config FB_MXC_TVOUT_CH7024
+	tristate "CH7024 TV Out Encoder"
+	depends on FB_MXC_SYNC_PANEL
+
+config FB_MXC_LOW_PWR_DISPLAY
+	bool "Low Power Display Refresh Mode"
+	depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
+	default y
+
+config FB_MXC_INTERNAL_MEM
+	bool "Framebuffer in Internal RAM"
+	depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM
+	default y
+
+config FB_MXC_ASYNC_PANEL
+	depends on FB_MXC
+	bool "Asynchronous Panels"
+	default n
+
+menu "Asynchronous Panel Type"
+	depends on FB_MXC_ASYNC_PANEL && FB_MXC
+
+config FB_MXC_EPSON_PANEL
+    depends on FB_MXC_ASYNC_PANEL
+	default n
+	bool "Epson 176x220 Panel"
+
+endmenu
+
+config FB_MXC_EINK_PANEL
+	depends on FB_MXC
+	depends on DMA_ENGINE
+	select FB_DEFERRED_IO
+	tristate "E-Ink Panel Framebuffer"
+
+config FB_MXC_EINK_AUTO_UPDATE_MODE
+    bool "E-Ink Auto-update Mode Support"
+    default n
+    depends on FB_MXC_EINK_PANEL
+
+config FB_MXC_ELCDIF_FB
+	depends on FB && ARCH_MXC
+	tristate "Support MXC ELCDIF framebuffer"
+
+choice
+	prompt "Async Panel Interface Type"
+	depends on FB_MXC_ASYNC_PANEL && FB_MXC
+	default FB_MXC_ASYNC_PANEL_IFC_16_BIT
+
+config FB_MXC_ASYNC_PANEL_IFC_8_BIT
+	bool "8-bit Parallel Bus Interface"
+
+config FB_MXC_ASYNC_PANEL_IFC_16_BIT
+	bool "16-bit Parallel Bus Interface"
+
+config FB_MXC_ASYNC_PANEL_IFC_SERIAL
+	bool "Serial Bus Interface"
+
+endchoice
diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile
new file mode 100644
index 000000000000..c428bb95a948
--- /dev/null
+++ b/drivers/video/mxc/Makefile
@@ -0,0 +1,24 @@
+ifeq ($(CONFIG_ARCH_MX21)$(CONFIG_ARCH_MX27)$(CONFIG_ARCH_MX25),y)
+	obj-$(CONFIG_FB_MXC_TVOUT)              += fs453.o
+	obj-$(CONFIG_FB_MXC_SYNC_PANEL)         += mx2fb.o mxcfb_modedb.o
+	obj-$(CONFIG_FB_MXC_EPSON_PANEL)        += mx2fb_epson.o
+else
+ifeq ($(CONFIG_MXC_IPU_V1),y)
+	obj-$(CONFIG_FB_MXC_SYNC_PANEL)         += mxcfb.o mxcfb_modedb.o
+else
+	obj-$(CONFIG_FB_MXC_SYNC_PANEL)         += mxc_ipuv3_fb.o
+endif
+	obj-$(CONFIG_FB_MXC_EPSON_PANEL)        += mxcfb_epson.o
+	obj-$(CONFIG_FB_MXC_EPSON_QVGA_PANEL)   += mxcfb_epson_qvga.o
+	obj-$(CONFIG_FB_MXC_TOSHIBA_QVGA_PANEL) += mxcfb_toshiba_qvga.o
+	obj-$(CONFIG_FB_MXC_SHARP_128_PANEL)    += mxcfb_sharp_128x128.o
+endif
+obj-$(CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL)   += mxcfb_epson_vga.o
+obj-$(CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL)   += mxcfb_claa_wvga.o
+obj-$(CONFIG_FB_MXC_TVOUT_CH7024)           += ch7024.o
+obj-$(CONFIG_FB_MXC_TVOUT_TVE)              += tve.o
+obj-$(CONFIG_FB_MXC_LDB)                    += ldb.o
+obj-$(CONFIG_FB_MXC_CH7026)		    		+= mxcfb_ch7026.o
+#obj-$(CONFIG_FB_MODE_HELPERS)				+= mxc_edid.o
+obj-$(CONFIG_FB_MXC_EINK_PANEL)             += mxc_epdc_fb.o
+obj-$(CONFIG_FB_MXC_ELCDIF_FB)		    += mxc_elcdif_fb.o
diff --git a/drivers/video/mxc/ch7024.c b/drivers/video/mxc/ch7024.c
new file mode 100644
index 000000000000..35ffb7570c2b
--- /dev/null
+++ b/drivers/video/mxc/ch7024.c
@@ -0,0 +1,866 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ch7024.c
+ * @brief Driver for CH7024 TV encoder
+ *
+ * @ingroup Framebuffer
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sysfs.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <asm/uaccess.h>
+#include <asm/atomic.h>
+#include <mach/gpio.h>
+#include <mach/hw_events.h>
+
+/*!
+ * CH7024 registers
+ */
+#define CH7024_DEVID		0x00
+#define CH7024_REVID		0x01
+#define CH7024_PG		0x02
+
+#define CH7024_RESET		0x03
+#define CH7024_POWER		0x04
+#define CH7024_TVHUE		0x05
+#define CH7024_TVSAT		0x06
+#define CH7024_TVCTA		0x07
+#define CH7024_TVBRI		0x08
+#define CH7024_TVSHARP		0x09
+#define CH7024_OUT_FMT		0x0A
+#define CH7024_XTAL		0x0B
+#define CH7024_IDF1		0x0C
+#define CH7024_IDF2		0x0D
+#define CH7024_SYNC		0x0E
+#define CH7024_TVFILTER1	0x0F
+#define CH7024_TVFILTER2	0x10
+#define CH7024_IN_TIMING1	0x11
+#define CH7024_IN_TIMING2	0x12
+#define CH7024_IN_TIMING3	0x13
+#define CH7024_IN_TIMING4	0x14
+#define CH7024_IN_TIMING5	0x15
+#define CH7024_IN_TIMING6	0x16
+#define CH7024_IN_TIMING7	0x17
+#define CH7024_IN_TIMING8	0x18
+#define CH7024_IN_TIMING9	0x19
+#define CH7024_IN_TIMING10	0x1A
+#define CH7024_IN_TIMING11	0x1B
+#define CH7024_ACIV		0x1C
+#define CH7024_CLK_TREE		0x1D
+#define CH7024_OUT_TIMING1	0x1E
+#define CH7024_OUT_TIMING2	0x1F
+#define CH7024_V_POS1		0x20
+#define CH7024_V_POS2		0x21
+#define CH7024_H_POS1		0x22
+#define CH7024_H_POS2		0x23
+#define CH7024_PCLK_A1		0x24
+#define CH7024_PCLK_A2		0x25
+#define CH7024_PCLK_A3		0x26
+#define CH7024_PCLK_A4		0x27
+#define CH7024_CLK_P1		0x28
+#define CH7024_CLK_P2		0x29
+#define CH7024_CLK_P3		0x2A
+#define CH7024_CLK_N1		0x2B
+#define CH7024_CLK_N2		0x2C
+#define CH7024_CLK_N3		0x2D
+#define CH7024_CLK_T		0x2E
+#define CH7024_PLL1		0x2F
+#define CH7024_PLL2		0x30
+#define CH7024_PLL3		0x31
+#define CH7024_SC_FREQ1		0x34
+#define CH7024_SC_FREQ2		0x35
+#define CH7024_SC_FREQ3		0x36
+#define CH7024_SC_FREQ4		0x37
+#define CH7024_DAC_TRIM		0x62
+#define CH7024_DATA_IO		0x63
+#define CH7024_ATT_DISP		0x7E
+
+/*!
+ * CH7024 register values
+ */
+/* video output formats */
+#define CH7024_VOS_NTSC_M	0x0
+#define CH7024_VOS_NTSC_J	0x1
+#define CH7024_VOS_NTSC_443	0x2
+#define CH7024_VOS_PAL_BDGHKI	0x3
+#define CH7024_VOS_PAL_M	0x4
+#define CH7024_VOS_PAL_N	0x5
+#define CH7024_VOS_PAL_NC	0x6
+#define CH7024_VOS_PAL_60	0x7
+/* crystal predefined */
+#define CH7024_XTAL_13MHZ	0x4
+#define CH7024_XTAL_26MHZ	0xB
+
+/* chip ID */
+#define CH7024_DEVICE_ID	0x45
+
+/* clock source define */
+#define CLK_HIGH	0
+#define CLK_LOW		1
+
+/* CH7024 presets structs */
+struct ch7024_clock {
+	u32 A;
+	u32 P;
+	u32 N;
+	u32 T;
+	u8 PLLN1;
+	u8 PLLN2;
+	u8 PLLN3;
+};
+
+struct ch7024_input_timing {
+	u32 HTI;
+	u32 VTI;
+	u32 HAI;
+	u32 VAI;
+	u32 HW;
+	u32 HO;
+	u32 VW;
+	u32 VO;
+	u32 VOS;
+};
+
+#define TVOUT_FMT_OFF	0
+#define TVOUT_FMT_NTSC	1
+#define TVOUT_FMT_PAL	2
+
+static int enabled;		/* enable power on or not */
+static int pm_status;		/* status before suspend */
+
+static struct i2c_client *ch7024_client;
+static struct fb_info *ch7024_fbi;
+static int ch7024_cur_mode;
+static u32 detect_gpio;
+static struct regulator *io_reg;
+static struct regulator *core_reg;
+static struct regulator *analog_reg;
+
+static void hp_detect_wq_handler(struct work_struct *);
+DECLARE_DELAYED_WORK(ch7024_wq, hp_detect_wq_handler);
+
+static inline int ch7024_read_reg(u8 reg)
+{
+	return i2c_smbus_read_byte_data(ch7024_client, reg);
+}
+
+static inline int ch7024_write_reg(u8 reg, u8 word)
+{
+	return i2c_smbus_write_byte_data(ch7024_client, reg, word);
+}
+
+/**
+ * PAL B/D/G/H/K/I clock and timting structures
+ */
+static struct ch7024_clock ch7024_clk_pal = {
+	.A = 0x0,
+	.P = 0x36b00,
+	.N = 0x41eb00,
+	.T = 0x3f,
+	.PLLN1 = 0x0,
+	.PLLN2 = 0x1b,
+	.PLLN3 = 0x12,
+};
+
+static struct ch7024_input_timing ch7024_timing_pal = {
+	.HTI = 950,
+	.VTI = 560,
+	.HAI = 640,
+	.VAI = 480,
+	.HW = 60,
+	.HO = 250,
+	.VW = 40,
+	.VO = 40,
+	.VOS = CH7024_VOS_PAL_BDGHKI,
+};
+
+/**
+ * NTSC_M clock and timting structures
+ * TODO: change values to work well.
+ */
+static struct ch7024_clock ch7024_clk_ntsc = {
+	.A = 0x0,
+	.P = 0x2ac90,
+	.N = 0x36fc90,
+	.T = 0x3f,
+	.PLLN1 = 0x0,
+	.PLLN2 = 0x1b,
+	.PLLN3 = 0x12,
+};
+
+static struct ch7024_input_timing ch7024_timing_ntsc = {
+	.HTI = 801,
+	.VTI = 554,
+	.HAI = 640,
+	.VAI = 480,
+	.HW = 60,
+	.HO = 101,
+	.VW = 20,
+	.VO = 54,
+	.VOS = CH7024_VOS_NTSC_M,
+};
+
+static struct fb_videomode video_modes[] = {
+	{
+	 /* NTSC TV output */
+	 "TV-NTSC", 60, 640, 480, 37594,
+	 0, 101,
+	 0, 54,
+	 60, 20,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* PAL TV output */
+	 "TV-PAL", 50, 640, 480, 37594,
+	 0, 250,
+	 0, 40,
+	 60, 40,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+/**
+ * ch7024_setup
+ * initial the CH7024 chipset by setting register
+ * @param:
+ * 	vos: output video format
+ * @return:
+ * 	0 successful
+ * 	otherwise failed
+ */
+static int ch7024_setup(int vos)
+{
+	struct ch7024_input_timing *ch_timing;
+	struct ch7024_clock *ch_clk;
+#ifdef DEBUG_CH7024
+	int i, val;
+#endif
+
+	/* select output video format */
+	if (vos == TVOUT_FMT_PAL) {
+		ch_timing = &ch7024_timing_pal;
+		ch_clk = &ch7024_clk_pal;
+		pr_debug("CH7024: change to PAL video\n");
+	} else if (vos == TVOUT_FMT_NTSC) {
+		ch_timing = &ch7024_timing_ntsc;
+		ch_clk = &ch7024_clk_ntsc;
+		pr_debug("CH7024: change to NTSC video\n");
+	} else {
+
+		pr_debug("CH7024: no such video format.\n");
+		return -EINVAL;
+	}
+	ch7024_write_reg(CH7024_RESET, 0x0);
+	ch7024_write_reg(CH7024_RESET, 0x3);
+
+	ch7024_write_reg(CH7024_POWER, 0x0C);	/* power on, disable DAC */
+	ch7024_write_reg(CH7024_XTAL, CH7024_XTAL_26MHZ);
+	ch7024_write_reg(CH7024_SYNC, 0x0D);	/* SLAVE mode, and TTL */
+	ch7024_write_reg(CH7024_IDF1, 0x00);
+	ch7024_write_reg(CH7024_TVFILTER1, 0x00);	/* set XCH=0 */
+	ch7024_write_reg(CH7024_CLK_TREE, 0x9E);	/* Invert input clk */
+
+	/* set input clock and divider */
+	/* set PLL */
+	ch7024_write_reg(CH7024_PLL1, ch_clk->PLLN1);
+	ch7024_write_reg(CH7024_PLL2, ch_clk->PLLN2);
+	ch7024_write_reg(CH7024_PLL3, ch_clk->PLLN3);
+	/* set A register */
+	ch7024_write_reg(CH7024_PCLK_A1, (ch_clk->A >> 24) & 0xFF);
+	ch7024_write_reg(CH7024_PCLK_A2, (ch_clk->A >> 16) & 0xFF);
+	ch7024_write_reg(CH7024_PCLK_A3, (ch_clk->A >> 8) & 0xFF);
+	ch7024_write_reg(CH7024_PCLK_A4, ch_clk->A & 0xFF);
+	/* set P register */
+	ch7024_write_reg(CH7024_CLK_P1, (ch_clk->P >> 16) & 0xFF);
+	ch7024_write_reg(CH7024_CLK_P2, (ch_clk->P >> 8) & 0xFF);
+	ch7024_write_reg(CH7024_CLK_P3, ch_clk->P & 0xFF);
+	/* set N register */
+	ch7024_write_reg(CH7024_CLK_N1, (ch_clk->N >> 16) & 0xFF);
+	ch7024_write_reg(CH7024_CLK_N2, (ch_clk->N >> 8) & 0xFF);
+	ch7024_write_reg(CH7024_CLK_N3, ch_clk->N & 0xFF);
+	/* set T register */
+	ch7024_write_reg(CH7024_CLK_T, ch_clk->T & 0xFF);
+
+	/* set sub-carrier frequency generation method */
+	ch7024_write_reg(CH7024_ACIV, 0x00);	/* ACIV = 0, automatical SCF */
+	/* TV out pattern and DAC switch */
+	ch7024_write_reg(CH7024_OUT_FMT, (0x10 | ch_timing->VOS) & 0xFF);
+
+	/* input settings */
+	/* input format, RGB666 */
+	ch7024_write_reg(CH7024_IDF2, 0x02);
+	/* HAI/HTI VAI */
+	ch7024_write_reg(CH7024_IN_TIMING1, ((ch_timing->HTI >> 5) & 0x38) |
+			 ((ch_timing->HAI >> 8) & 0x07));
+	ch7024_write_reg(CH7024_IN_TIMING2, ch_timing->HAI & 0xFF);
+	ch7024_write_reg(CH7024_IN_TIMING8, ch_timing->VAI & 0xFF);
+	/* HTI VTI */
+	ch7024_write_reg(CH7024_IN_TIMING3, ch_timing->HTI & 0xFF);
+	ch7024_write_reg(CH7024_IN_TIMING9, ch_timing->VTI & 0xFF);
+	/* HW/HO(h) VW */
+	ch7024_write_reg(CH7024_IN_TIMING4, ((ch_timing->HW >> 5) & 0x18) |
+			 ((ch_timing->HO >> 8) & 0x7));
+	ch7024_write_reg(CH7024_IN_TIMING6, ch_timing->HW & 0xFF);
+	ch7024_write_reg(CH7024_IN_TIMING11, ch_timing->VW & 0x3F);
+	/* HO(l) VO/VAI/VTI */
+	ch7024_write_reg(CH7024_IN_TIMING5, ch_timing->HO & 0xFF);
+	ch7024_write_reg(CH7024_IN_TIMING7, ((ch_timing->VO >> 4) & 0x30) |
+			 ((ch_timing->VTI >> 6) & 0x0C) |
+			 ((ch_timing->VAI >> 8) & 0x03));
+	ch7024_write_reg(CH7024_IN_TIMING10, ch_timing->VO & 0xFF);
+
+	/* adjust the brightness */
+	ch7024_write_reg(CH7024_TVBRI, 0x90);
+
+	ch7024_write_reg(CH7024_OUT_TIMING1, 0x4);
+	ch7024_write_reg(CH7024_OUT_TIMING2, 0xe0);
+
+	if (vos == TVOUT_FMT_PAL) {
+		ch7024_write_reg(CH7024_V_POS1, 0x03);
+		ch7024_write_reg(CH7024_V_POS2, 0x7d);
+	} else {
+		ch7024_write_reg(CH7024_V_POS1, 0x02);
+		ch7024_write_reg(CH7024_V_POS2, 0x7b);
+	}
+
+	ch7024_write_reg(CH7024_POWER, 0x00);
+
+#ifdef DEBUG_CH7024
+	for (i = 0; i < CH7024_SC_FREQ4; i++) {
+
+		val = ch7024_read_reg(i);
+		pr_debug("CH7024, reg[0x%x] = %x\n", i, val);
+	}
+#endif
+	return 0;
+}
+
+/**
+ * ch7024_enable
+ * Enable the ch7024 Power to begin TV encoder
+ */
+static int ch7024_enable(void)
+{
+	int en = enabled;
+
+	if (!enabled) {
+		regulator_enable(core_reg);
+		regulator_enable(io_reg);
+		regulator_enable(analog_reg);
+		msleep(200);
+		enabled = 1;
+		ch7024_write_reg(CH7024_POWER, 0x00);
+		pr_debug("CH7024 power on.\n");
+	}
+	return en;
+}
+
+/**
+ * ch7024_disable
+ * Disable the ch7024 Power to stop TV encoder
+ */
+static void ch7024_disable(void)
+{
+	if (enabled) {
+		enabled = 0;
+		ch7024_write_reg(CH7024_POWER, 0x0D);
+		regulator_disable(analog_reg);
+		regulator_disable(io_reg);
+		regulator_disable(core_reg);
+		pr_debug("CH7024 power off.\n");
+	}
+}
+
+static int ch7024_detect(void)
+{
+	int en;
+	int detect = 0;
+
+	if (gpio_get_value(detect_gpio) == 1) {
+		set_irq_type(ch7024_client->irq, IRQF_TRIGGER_FALLING);
+
+		en = ch7024_enable();
+
+		ch7024_write_reg(CH7024_DAC_TRIM, 0xB4);
+		msleep(50);
+		detect = ch7024_read_reg(CH7024_ATT_DISP) & 0x3;
+		ch7024_write_reg(CH7024_DAC_TRIM, 0x34);
+
+		if (!en)
+			ch7024_disable();
+	} else {
+		set_irq_type(ch7024_client->irq, IRQF_TRIGGER_RISING);
+	}
+	dev_dbg(&ch7024_client->dev, "detect = %d\n", detect);
+	return (detect);
+}
+
+static irqreturn_t hp_detect_handler(int irq, void *data)
+{
+	disable_irq(irq);
+	schedule_delayed_work(&ch7024_wq, 50);
+
+	return IRQ_HANDLED;
+}
+
+static void hp_detect_wq_handler(struct work_struct *work)
+{
+	int detect;
+	struct mxc_hw_event event = { HWE_PHONEJACK_PLUG, 0 };
+
+	detect = ch7024_detect();
+
+	enable_irq(ch7024_client->irq);
+
+	sysfs_notify(&ch7024_client->dev.kobj, NULL, "headphone");
+
+	/* send hw event by netlink */
+	event.args = detect;
+	hw_event_send(1, &event);
+}
+
+int ch7024_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		if ((ch7024_fbi != NULL) || strcmp(fbi->fix.id, "DISP3 BG"))
+			break;
+
+		ch7024_fbi = fbi;
+		fb_add_videomode(&video_modes[0], &ch7024_fbi->modelist);
+		fb_add_videomode(&video_modes[1], &ch7024_fbi->modelist);
+		break;
+	case FB_EVENT_MODE_CHANGE:
+		if (ch7024_fbi != fbi)
+			break;
+
+		if (!fbi->mode) {
+			ch7024_disable();
+			ch7024_cur_mode = TVOUT_FMT_OFF;
+			return 0;
+		}
+
+		if (fb_mode_is_equal(fbi->mode, &video_modes[0])) {
+			ch7024_cur_mode = TVOUT_FMT_NTSC;
+			ch7024_enable();
+			ch7024_setup(TVOUT_FMT_NTSC);
+		} else if (fb_mode_is_equal(fbi->mode, &video_modes[1])) {
+			ch7024_cur_mode = TVOUT_FMT_PAL;
+			ch7024_enable();
+			ch7024_setup(TVOUT_FMT_PAL);
+		} else {
+			ch7024_disable();
+			ch7024_cur_mode = TVOUT_FMT_OFF;
+			return 0;
+		}
+		break;
+	case FB_EVENT_BLANK:
+		if ((ch7024_fbi != fbi) || (ch7024_cur_mode == TVOUT_FMT_OFF))
+			return 0;
+
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			ch7024_enable();
+			ch7024_setup(ch7024_cur_mode);
+		} else {
+			ch7024_disable();
+		}
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = ch7024_fb_event,
+};
+
+static ssize_t show_headphone(struct device_driver *dev, char *buf)
+{
+	int detect;
+
+	detect = ch7024_detect();
+
+	if (detect == 0) {
+		strcpy(buf, "none\n");
+	} else if (detect == 1) {
+		strcpy(buf, "cvbs\n");
+	} else {
+		strcpy(buf, "headset\n");
+	}
+
+	return strlen(buf);
+}
+
+DRIVER_ATTR(headphone, 0644, show_headphone, NULL);
+
+static ssize_t show_brightness(struct device_driver *dev, char *buf)
+{
+	u32 reg;
+	reg = ch7024_read_reg(CH7024_TVBRI);
+	return snprintf(buf, PAGE_SIZE, "%u", reg);
+}
+
+static ssize_t store_brightness(struct device_driver *dev, const char *buf,
+				size_t count)
+{
+	char *endp;
+	int brightness = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	if (brightness > 255)
+		brightness = 255;
+
+	ch7024_write_reg(CH7024_TVBRI, brightness);
+
+	return count;
+}
+
+DRIVER_ATTR(brightness, 0644, show_brightness, store_brightness);
+
+static ssize_t show_contrast(struct device_driver *dev, char *buf)
+{
+	u32 reg;
+	reg = ch7024_read_reg(CH7024_TVCTA);
+
+	reg *= 2;		/* Scale to 0 - 255 */
+
+	return snprintf(buf, PAGE_SIZE, "%u", reg);
+}
+
+static ssize_t store_contrast(struct device_driver *dev, const char *buf,
+			      size_t count)
+{
+	char *endp;
+	int contrast = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	contrast /= 2;
+	if (contrast > 127)
+		contrast = 127;
+
+	ch7024_write_reg(CH7024_TVCTA, contrast);
+
+	return count;
+}
+
+DRIVER_ATTR(contrast, 0644, show_contrast, store_contrast);
+
+static ssize_t show_hue(struct device_driver *dev, char *buf)
+{
+	u32 reg;
+	reg = ch7024_read_reg(CH7024_TVHUE);
+
+	reg *= 2;		/* Scale to 0 - 255 */
+
+	return snprintf(buf, PAGE_SIZE, "%u", reg);
+}
+
+static ssize_t store_hue(struct device_driver *dev, const char *buf,
+			 size_t count)
+{
+	char *endp;
+	int hue = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	hue /= 2;
+	if (hue > 127)
+		hue = 127;
+
+	ch7024_write_reg(CH7024_TVHUE, hue);
+
+	return count;
+}
+
+DRIVER_ATTR(hue, 0644, show_hue, store_hue);
+
+static ssize_t show_saturation(struct device_driver *dev, char *buf)
+{
+	u32 reg;
+	reg = ch7024_read_reg(CH7024_TVSAT);
+
+	reg *= 2;		/* Scale to 0 - 255 */
+
+	return snprintf(buf, PAGE_SIZE, "%u", reg);
+}
+
+static ssize_t store_saturation(struct device_driver *dev, const char *buf,
+				size_t count)
+{
+	char *endp;
+	int saturation = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	saturation /= 2;
+	if (saturation > 127)
+		saturation = 127;
+
+	ch7024_write_reg(CH7024_TVSAT, saturation);
+
+	return count;
+}
+
+DRIVER_ATTR(saturation, 0644, show_saturation, store_saturation);
+
+static ssize_t show_sharpness(struct device_driver *dev, char *buf)
+{
+	u32 reg;
+	reg = ch7024_read_reg(CH7024_TVSHARP);
+
+	reg *= 32;		/* Scale to 0 - 255 */
+
+	return snprintf(buf, PAGE_SIZE, "%u", reg);
+}
+
+static ssize_t store_sharpness(struct device_driver *dev, const char *buf,
+			       size_t count)
+{
+	char *endp;
+	int sharpness = simple_strtoul(buf, &endp, 0);
+	size_t size = endp - buf;
+
+	if (*endp && isspace(*endp))
+		size++;
+	if (size != count)
+		return -EINVAL;
+
+	sharpness /= 32;	/* Scale to 0 - 7 */
+	if (sharpness > 7)
+		sharpness = 7;
+
+	ch7024_write_reg(CH7024_TVSHARP, sharpness);
+
+	return count;
+}
+
+DRIVER_ATTR(sharpness, 0644, show_sharpness, store_sharpness);
+
+static int ch7024_probe(struct i2c_client *client, const struct i2c_device_id *dev_id)
+{
+	int ret, i;
+	u32 id;
+	u32 irqtype;
+	struct mxc_tvout_platform_data *plat_data = client->dev.platform_data;
+
+	ch7024_client = client;
+
+	io_reg = regulator_get(&client->dev, plat_data->io_reg);
+	core_reg = regulator_get(&client->dev, plat_data->core_reg);
+	analog_reg = regulator_get(&client->dev, plat_data->analog_reg);
+
+	regulator_enable(io_reg);
+	regulator_enable(core_reg);
+	regulator_enable(analog_reg);
+	msleep(200);
+
+	id = ch7024_read_reg(CH7024_DEVID);
+
+	regulator_disable(core_reg);
+	regulator_disable(io_reg);
+	regulator_disable(analog_reg);
+
+	if (id < 0 || id != CH7024_DEVICE_ID) {
+		printk(KERN_ERR
+		       "ch7024: TV encoder not present: id = %x\n", id);
+		return -ENODEV;
+	}
+	printk(KERN_ERR "ch7024: TV encoder present: id = %x\n", id);
+
+	detect_gpio = plat_data->detect_line;
+
+	if (client->irq > 0) {
+		if (ch7024_detect() == 0)
+			irqtype = IRQF_TRIGGER_RISING;
+		else
+			irqtype = IRQF_TRIGGER_FALLING;
+
+		ret = request_irq(client->irq, hp_detect_handler, irqtype,
+				  client->name, client);
+		if (ret < 0)
+			goto err0;
+
+		ret = driver_create_file(&client->driver->driver,
+					 &driver_attr_headphone);
+		if (ret < 0)
+			goto err1;
+	}
+
+	ret = driver_create_file(&client->driver->driver,
+				 &driver_attr_brightness);
+	if (ret)
+		goto err2;
+
+	ret = driver_create_file(&client->driver->driver,
+				 &driver_attr_contrast);
+	if (ret)
+		goto err3;
+	ret = driver_create_file(&client->driver->driver, &driver_attr_hue);
+	if (ret)
+		goto err4;
+	ret = driver_create_file(&client->driver->driver,
+				 &driver_attr_saturation);
+	if (ret)
+		goto err5;
+	ret = driver_create_file(&client->driver->driver,
+				 &driver_attr_sharpness);
+	if (ret)
+		goto err6;
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0) {
+			ch7024_fbi = registered_fb[i];
+			break;
+		}
+	}
+	if (ch7024_fbi != NULL) {
+		fb_add_videomode(&video_modes[0], &ch7024_fbi->modelist);
+		fb_add_videomode(&video_modes[1], &ch7024_fbi->modelist);
+	}
+	fb_register_client(&nb);
+
+	return 0;
+      err6:
+	driver_remove_file(&client->driver->driver, &driver_attr_saturation);
+      err5:
+	driver_remove_file(&client->driver->driver, &driver_attr_hue);
+      err4:
+	driver_remove_file(&client->driver->driver, &driver_attr_contrast);
+      err3:
+	driver_remove_file(&client->driver->driver, &driver_attr_brightness);
+      err2:
+	driver_remove_file(&client->driver->driver, &driver_attr_headphone);
+      err1:
+	free_irq(client->irq, client);
+      err0:
+	return ret;
+}
+
+static int ch7024_remove(struct i2c_client *client)
+{
+	free_irq(client->irq, client);
+
+	regulator_put(io_reg);
+	regulator_put(core_reg);
+	regulator_put(analog_reg);
+
+	driver_remove_file(&client->driver->driver, &driver_attr_headphone);
+	driver_remove_file(&client->driver->driver, &driver_attr_brightness);
+	driver_remove_file(&client->driver->driver, &driver_attr_contrast);
+	driver_remove_file(&client->driver->driver, &driver_attr_hue);
+	driver_remove_file(&client->driver->driver, &driver_attr_saturation);
+	driver_remove_file(&client->driver->driver, &driver_attr_sharpness);
+
+	fb_unregister_client(&nb);
+
+	ch7024_client = 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * PM suspend/resume routing
+ */
+static int ch7024_suspend(struct i2c_client *client, pm_message_t state)
+{
+	pr_debug("Ch7024 suspend routing..\n");
+	if (enabled) {
+		ch7024_disable();
+		pm_status = 1;
+	} else {
+		pm_status = 0;
+	}
+	return 0;
+}
+
+static int ch7024_resume(struct i2c_client *client)
+{
+	pr_debug("Ch7024 resume routing..\n");
+	if (pm_status) {
+		ch7024_enable();
+		ch7024_setup(ch7024_cur_mode);
+	}
+	return 0;
+}
+#else
+#define ch7024_suspend	NULL
+#define ch7024_resume	NULL
+#endif
+
+static const struct i2c_device_id ch7024_id[] = {
+	{ "ch7024", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, ch7024_id);
+
+static struct i2c_driver ch7024_driver = {
+	.driver = {
+		   .name = "ch7024",
+		   },
+	.probe = ch7024_probe,
+	.remove = ch7024_remove,
+	.suspend = ch7024_suspend,
+	.resume = ch7024_resume,
+	.id_table = ch7024_id,
+};
+
+static int __init ch7024_init(void)
+{
+	return i2c_add_driver(&ch7024_driver);
+}
+
+static void __exit ch7024_exit(void)
+{
+	i2c_del_driver(&ch7024_driver);
+}
+
+module_init(ch7024_init);
+module_exit(ch7024_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("CH7024 TV encoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/elcdif_regs.h b/drivers/video/mxc/elcdif_regs.h
new file mode 100644
index 000000000000..2eceba5864e0
--- /dev/null
+++ b/drivers/video/mxc/elcdif_regs.h
@@ -0,0 +1,678 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on arch/arm/mach-mx28/include/mach/regs-lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#ifndef __ELCDIF_REGS_INCLUDED_
+#define __ELCDIF_REGS_INCLUDED_
+
+#define HW_ELCDIF_CTRL	(0x00000000)
+#define HW_ELCDIF_CTRL_SET	(0x00000004)
+#define HW_ELCDIF_CTRL_CLR	(0x00000008)
+#define HW_ELCDIF_CTRL_TOG	(0x0000000c)
+
+#define BM_ELCDIF_CTRL_SFTRST	0x80000000
+#define BM_ELCDIF_CTRL_CLKGATE	0x40000000
+#define BM_ELCDIF_CTRL_YCBCR422_INPUT	0x20000000
+#define BM_ELCDIF_CTRL_READ_WRITEB	0x10000000
+#define BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE	0x08000000
+#define BM_ELCDIF_CTRL_DATA_SHIFT_DIR	0x04000000
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT  0x0
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1
+#define BP_ELCDIF_CTRL_SHIFT_NUM_BITS	21
+#define BM_ELCDIF_CTRL_SHIFT_NUM_BITS	0x03E00000
+#define BF_ELCDIF_CTRL_SHIFT_NUM_BITS(v)  \
+		(((v) << 21) & BM_ELCDIF_CTRL_SHIFT_NUM_BITS)
+#define BM_ELCDIF_CTRL_DVI_MODE	0x00100000
+#define BM_ELCDIF_CTRL_BYPASS_COUNT	0x00080000
+#define BM_ELCDIF_CTRL_VSYNC_MODE	0x00040000
+#define BM_ELCDIF_CTRL_DOTCLK_MODE	0x00020000
+#define BM_ELCDIF_CTRL_DATA_SELECT	0x00010000
+#define BV_ELCDIF_CTRL_DATA_SELECT__CMD_MODE  0x0
+#define BV_ELCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1
+#define BP_ELCDIF_CTRL_INPUT_DATA_SWIZZLE	14
+#define BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE	0x0000C000
+#define BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(v)  \
+		(((v) << 14) & BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BP_ELCDIF_CTRL_CSC_DATA_SWIZZLE	12
+#define BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE	0x00003000
+#define BF_ELCDIF_CTRL_CSC_DATA_SWIZZLE(v)  \
+		(((v) << 12) & BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BP_ELCDIF_CTRL_LCD_DATABUS_WIDTH	10
+#define BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH	0x00000C00
+#define BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(v)  \
+		(((v) << 10) & BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH)
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT  0x1
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3
+#define BP_ELCDIF_CTRL_WORD_LENGTH	8
+#define BM_ELCDIF_CTRL_WORD_LENGTH	0x00000300
+#define BF_ELCDIF_CTRL_WORD_LENGTH(v)  \
+		(((v) << 8) & BM_ELCDIF_CTRL_WORD_LENGTH)
+#define BV_ELCDIF_CTRL_WORD_LENGTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_WORD_LENGTH__8_BIT  0x1
+#define BV_ELCDIF_CTRL_WORD_LENGTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_WORD_LENGTH__24_BIT 0x3
+#define BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC	0x00000080
+#define BM_ELCDIF_CTRL_ENABLE_PXP_HANDSHAKE	0x00000040
+#define BM_ELCDIF_CTRL_ELCDIF_MASTER	0x00000020
+#define BM_ELCDIF_CTRL_RSRVD0	0x00000010
+#define BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT	0x00000008
+#define BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT	0x00000004
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1
+#define BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT	0x00000002
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID          0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1
+#define BM_ELCDIF_CTRL_RUN	0x00000001
+
+#define HW_ELCDIF_CTRL1	(0x00000010)
+#define HW_ELCDIF_CTRL1_SET	(0x00000014)
+#define HW_ELCDIF_CTRL1_CLR	(0x00000018)
+#define HW_ELCDIF_CTRL1_TOG	(0x0000001c)
+
+#define BP_ELCDIF_CTRL1_RSRVD1	28
+#define BM_ELCDIF_CTRL1_RSRVD1	0xF0000000
+#define BF_ELCDIF_CTRL1_RSRVD1(v) \
+		(((v) << 28) & BM_ELCDIF_CTRL1_RSRVD1)
+#define BM_ELCDIF_CTRL1_COMBINE_MPU_WR_STRB	0x08000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ_EN	0x04000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ	0x02000000
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW	0x01000000
+#define BM_ELCDIF_CTRL1_INTERLACE_FIELDS	0x00800000
+#define BM_ELCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD	0x00400000
+#define BM_ELCDIF_CTRL1_FIFO_CLEAR	0x00200000
+#define BM_ELCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS	0x00100000
+#define BP_ELCDIF_CTRL1_BYTE_PACKING_FORMAT	16
+#define BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT	0x000F0000
+#define BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(v)  \
+		(((v) << 16) & BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT)
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ_EN	0x00008000
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ_EN	0x00004000
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN	0x00002000
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN	0x00001000
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ	0x00000800
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ	0x00000400
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ	0x00000200
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST    0x1
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ	0x00000100
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST    0x1
+#define BP_ELCDIF_CTRL1_RSRVD0	3
+#define BM_ELCDIF_CTRL1_RSRVD0	0x000000F8
+#define BF_ELCDIF_CTRL1_RSRVD0(v)  \
+		(((v) << 3) & BM_ELCDIF_CTRL1_RSRVD0)
+#define BM_ELCDIF_CTRL1_BUSY_ENABLE	0x00000004
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED  0x1
+#define BM_ELCDIF_CTRL1_MODE86	0x00000002
+#define BV_ELCDIF_CTRL1_MODE86__8080_MODE 0x0
+#define BV_ELCDIF_CTRL1_MODE86__6800_MODE 0x1
+#define BM_ELCDIF_CTRL1_RESET	0x00000001
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_LOW  0x0
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1
+
+#define HW_ELCDIF_CTRL2	(0x00000020)
+#define HW_ELCDIF_CTRL2_SET	(0x00000024)
+#define HW_ELCDIF_CTRL2_CLR	(0x00000028)
+#define HW_ELCDIF_CTRL2_TOG	(0x0000002c)
+
+#define BP_ELCDIF_CTRL2_RSRVD5	24
+#define BM_ELCDIF_CTRL2_RSRVD5	0xFF000000
+#define BF_ELCDIF_CTRL2_RSRVD5(v) \
+		(((v) << 24) & BM_ELCDIF_CTRL2_RSRVD5)
+#define BP_ELCDIF_CTRL2_OUTSTANDING_REQS	21
+#define BM_ELCDIF_CTRL2_OUTSTANDING_REQS	0x00E00000
+#define BF_ELCDIF_CTRL2_OUTSTANDING_REQS(v)  \
+		(((v) << 21) & BM_ELCDIF_CTRL2_OUTSTANDING_REQS)
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_1  0x0
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_2  0x1
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_4  0x2
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8  0x3
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4
+#define BM_ELCDIF_CTRL2_BURST_LEN_8	0x00100000
+#define BM_ELCDIF_CTRL2_RSRVD4	0x00080000
+#define BP_ELCDIF_CTRL2_ODD_LINE_PATTERN	16
+#define BM_ELCDIF_CTRL2_ODD_LINE_PATTERN	0x00070000
+#define BF_ELCDIF_CTRL2_ODD_LINE_PATTERN(v)  \
+		(((v) << 16) & BM_ELCDIF_CTRL2_ODD_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD3	0x00008000
+#define BP_ELCDIF_CTRL2_EVEN_LINE_PATTERN	12
+#define BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN	0x00007000
+#define BF_ELCDIF_CTRL2_EVEN_LINE_PATTERN(v)  \
+		(((v) << 12) & BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD2	0x00000800
+#define BM_ELCDIF_CTRL2_READ_PACK_DIR	0x00000400
+#define BM_ELCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT	0x00000200
+#define BM_ELCDIF_CTRL2_READ_MODE_6_BIT_INPUT	0x00000100
+#define BM_ELCDIF_CTRL2_RSRVD1	0x00000080
+#define BP_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS	4
+#define BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS	0x00000070
+#define BF_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v)  \
+		(((v) << 4) & BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS)
+#define BP_ELCDIF_CTRL2_INITIAL_DUMMY_READ	1
+#define BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ	0x0000000E
+#define BF_ELCDIF_CTRL2_INITIAL_DUMMY_READ(v)  \
+		(((v) << 1) & BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ)
+#define BM_ELCDIF_CTRL2_RSRVD0	0x00000001
+
+#define HW_ELCDIF_TRANSFER_COUNT	(0x00000030)
+
+#define BP_ELCDIF_TRANSFER_COUNT_V_COUNT	16
+#define BM_ELCDIF_TRANSFER_COUNT_V_COUNT	0xFFFF0000
+#define BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v) \
+		(((v) << 16) & BM_ELCDIF_TRANSFER_COUNT_V_COUNT)
+#define BP_ELCDIF_TRANSFER_COUNT_H_COUNT	0
+#define BM_ELCDIF_TRANSFER_COUNT_H_COUNT	0x0000FFFF
+#define BF_ELCDIF_TRANSFER_COUNT_H_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_TRANSFER_COUNT_H_COUNT)
+
+#define HW_ELCDIF_CUR_BUF	(0x00000040)
+
+#define BP_ELCDIF_CUR_BUF_ADDR	0
+#define BM_ELCDIF_CUR_BUF_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_CUR_BUF_ADDR(v)	(v)
+
+#define HW_ELCDIF_NEXT_BUF	(0x00000050)
+
+#define BP_ELCDIF_NEXT_BUF_ADDR	0
+#define BM_ELCDIF_NEXT_BUF_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_NEXT_BUF_ADDR(v)	(v)
+
+#define HW_ELCDIF_TIMING	(0x00000060)
+
+#define BP_ELCDIF_TIMING_CMD_HOLD	24
+#define BM_ELCDIF_TIMING_CMD_HOLD	0xFF000000
+#define BF_ELCDIF_TIMING_CMD_HOLD(v) \
+		(((v) << 24) & BM_ELCDIF_TIMING_CMD_HOLD)
+#define BP_ELCDIF_TIMING_CMD_SETUP	16
+#define BM_ELCDIF_TIMING_CMD_SETUP	0x00FF0000
+#define BF_ELCDIF_TIMING_CMD_SETUP(v)  \
+		(((v) << 16) & BM_ELCDIF_TIMING_CMD_SETUP)
+#define BP_ELCDIF_TIMING_DATA_HOLD	8
+#define BM_ELCDIF_TIMING_DATA_HOLD	0x0000FF00
+#define BF_ELCDIF_TIMING_DATA_HOLD(v)  \
+		(((v) << 8) & BM_ELCDIF_TIMING_DATA_HOLD)
+#define BP_ELCDIF_TIMING_DATA_SETUP	0
+#define BM_ELCDIF_TIMING_DATA_SETUP	0x000000FF
+#define BF_ELCDIF_TIMING_DATA_SETUP(v)  \
+		(((v) << 0) & BM_ELCDIF_TIMING_DATA_SETUP)
+
+#define HW_ELCDIF_VDCTRL0	(0x00000070)
+#define HW_ELCDIF_VDCTRL0_SET	(0x00000074)
+#define HW_ELCDIF_VDCTRL0_CLR	(0x00000078)
+#define HW_ELCDIF_VDCTRL0_TOG	(0x0000007c)
+
+#define BP_ELCDIF_VDCTRL0_RSRVD2	30
+#define BM_ELCDIF_VDCTRL0_RSRVD2	0xC0000000
+#define BF_ELCDIF_VDCTRL0_RSRVD2(v) \
+		(((v) << 30) & BM_ELCDIF_VDCTRL0_RSRVD2)
+#define BM_ELCDIF_VDCTRL0_VSYNC_OEB	0x20000000
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT  0x1
+#define BM_ELCDIF_VDCTRL0_ENABLE_PRESENT	0x10000000
+#define BM_ELCDIF_VDCTRL0_VSYNC_POL	0x08000000
+#define BM_ELCDIF_VDCTRL0_HSYNC_POL	0x04000000
+#define BM_ELCDIF_VDCTRL0_DOTCLK_POL	0x02000000
+#define BM_ELCDIF_VDCTRL0_ENABLE_POL	0x01000000
+#define BP_ELCDIF_VDCTRL0_RSRVD1	22
+#define BM_ELCDIF_VDCTRL0_RSRVD1	0x00C00000
+#define BF_ELCDIF_VDCTRL0_RSRVD1(v)  \
+		(((v) << 22) & BM_ELCDIF_VDCTRL0_RSRVD1)
+#define BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT	0x00200000
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT	0x00100000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE	0x00080000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE_MODE	0x00040000
+#define BP_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH	0
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH	0x0003FFFF
+#define BF_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH)
+
+#define HW_ELCDIF_VDCTRL1	(0x00000080)
+
+#define BP_ELCDIF_VDCTRL1_VSYNC_PERIOD	0
+#define BM_ELCDIF_VDCTRL1_VSYNC_PERIOD	0xFFFFFFFF
+#define BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v)	(v)
+
+#define HW_ELCDIF_VDCTRL2	(0x00000090)
+
+#define BP_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH	18
+#define BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH	0xFFFC0000
+#define BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \
+		(((v) << 18) & BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH)
+#define BP_ELCDIF_VDCTRL2_HSYNC_PERIOD	0
+#define BM_ELCDIF_VDCTRL2_HSYNC_PERIOD	0x0003FFFF
+#define BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL2_HSYNC_PERIOD)
+
+#define HW_ELCDIF_VDCTRL3	(0x000000a0)
+
+#define BP_ELCDIF_VDCTRL3_RSRVD0	30
+#define BM_ELCDIF_VDCTRL3_RSRVD0	0xC0000000
+#define BF_ELCDIF_VDCTRL3_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_VDCTRL3_RSRVD0)
+#define BM_ELCDIF_VDCTRL3_MUX_SYNC_SIGNALS	0x20000000
+#define BM_ELCDIF_VDCTRL3_VSYNC_ONLY	0x10000000
+#define BP_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT	16
+#define BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT	0x0FFF0000
+#define BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v)  \
+		(((v) << 16) & BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT)
+#define BP_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT	0
+#define BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT	0x0000FFFF
+#define BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT)
+
+#define HW_ELCDIF_VDCTRL4	(0x000000b0)
+
+#define BP_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL	29
+#define BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL	0xE0000000
+#define BF_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \
+		(((v) << 29) & BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL)
+#define BP_ELCDIF_VDCTRL4_RSRVD0	19
+#define BM_ELCDIF_VDCTRL4_RSRVD0	0x1FF80000
+#define BF_ELCDIF_VDCTRL4_RSRVD0(v)  \
+		(((v) << 19) & BM_ELCDIF_VDCTRL4_RSRVD0)
+#define BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON	0x00040000
+#define BP_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT	0
+#define BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT	0x0003FFFF
+#define BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT)
+
+#define HW_ELCDIF_DVICTRL0	(0x000000c0)
+
+#define BP_ELCDIF_DVICTRL0_RSRVD1	28
+#define BM_ELCDIF_DVICTRL0_RSRVD1	0xF0000000
+#define BF_ELCDIF_DVICTRL0_RSRVD1(v) \
+		(((v) << 28) & BM_ELCDIF_DVICTRL0_RSRVD1)
+#define BP_ELCDIF_DVICTRL0_H_ACTIVE_CNT	16
+#define BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT	0x0FFF0000
+#define BF_ELCDIF_DVICTRL0_H_ACTIVE_CNT(v)  \
+		(((v) << 16) & BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT)
+#define BP_ELCDIF_DVICTRL0_RSRVD0	12
+#define BM_ELCDIF_DVICTRL0_RSRVD0	0x0000F000
+#define BF_ELCDIF_DVICTRL0_RSRVD0(v)  \
+		(((v) << 12) & BM_ELCDIF_DVICTRL0_RSRVD0)
+#define BP_ELCDIF_DVICTRL0_H_BLANKING_CNT	0
+#define BM_ELCDIF_DVICTRL0_H_BLANKING_CNT	0x00000FFF
+#define BF_ELCDIF_DVICTRL0_H_BLANKING_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL0_H_BLANKING_CNT)
+
+#define HW_ELCDIF_DVICTRL1	(0x000000d0)
+
+#define BP_ELCDIF_DVICTRL1_RSRVD0	30
+#define BM_ELCDIF_DVICTRL1_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL1_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL1_RSRVD0)
+#define BP_ELCDIF_DVICTRL1_F1_START_LINE	20
+#define BM_ELCDIF_DVICTRL1_F1_START_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL1_F1_START_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL1_F1_START_LINE)
+#define BP_ELCDIF_DVICTRL1_F1_END_LINE	10
+#define BM_ELCDIF_DVICTRL1_F1_END_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL1_F1_END_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL1_F1_END_LINE)
+#define BP_ELCDIF_DVICTRL1_F2_START_LINE	0
+#define BM_ELCDIF_DVICTRL1_F2_START_LINE	0x000003FF
+#define BF_ELCDIF_DVICTRL1_F2_START_LINE(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL1_F2_START_LINE)
+
+#define HW_ELCDIF_DVICTRL2	(0x000000e0)
+
+#define BP_ELCDIF_DVICTRL2_RSRVD0	30
+#define BM_ELCDIF_DVICTRL2_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL2_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL2_RSRVD0)
+#define BP_ELCDIF_DVICTRL2_F2_END_LINE	20
+#define BM_ELCDIF_DVICTRL2_F2_END_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL2_F2_END_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL2_F2_END_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_START_LINE	10
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_END_LINE	0
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE	0x000003FF
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE)
+
+#define HW_ELCDIF_DVICTRL3	(0x000000f0)
+
+#define BP_ELCDIF_DVICTRL3_RSRVD0	30
+#define BM_ELCDIF_DVICTRL3_RSRVD0	0xC0000000
+#define BF_ELCDIF_DVICTRL3_RSRVD0(v) \
+		(((v) << 30) & BM_ELCDIF_DVICTRL3_RSRVD0)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_START_LINE	20
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE	0x3FF00000
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v)  \
+		(((v) << 20) & BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_END_LINE	10
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE	0x000FFC00
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v)  \
+		(((v) << 10) & BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE)
+#define BP_ELCDIF_DVICTRL3_V_LINES_CNT	0
+#define BM_ELCDIF_DVICTRL3_V_LINES_CNT	0x000003FF
+#define BF_ELCDIF_DVICTRL3_V_LINES_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL3_V_LINES_CNT)
+
+#define HW_ELCDIF_DVICTRL4	(0x00000100)
+
+#define BP_ELCDIF_DVICTRL4_Y_FILL_VALUE	24
+#define BM_ELCDIF_DVICTRL4_Y_FILL_VALUE	0xFF000000
+#define BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(v) \
+		(((v) << 24) & BM_ELCDIF_DVICTRL4_Y_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CB_FILL_VALUE	16
+#define BM_ELCDIF_DVICTRL4_CB_FILL_VALUE	0x00FF0000
+#define BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(v)  \
+		(((v) << 16) & BM_ELCDIF_DVICTRL4_CB_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CR_FILL_VALUE	8
+#define BM_ELCDIF_DVICTRL4_CR_FILL_VALUE	0x0000FF00
+#define BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(v)  \
+		(((v) << 8) & BM_ELCDIF_DVICTRL4_CR_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_H_FILL_CNT	0
+#define BM_ELCDIF_DVICTRL4_H_FILL_CNT	0x000000FF
+#define BF_ELCDIF_DVICTRL4_H_FILL_CNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DVICTRL4_H_FILL_CNT)
+
+#define HW_ELCDIF_CSC_COEFF0	(0x00000110)
+
+#define BP_ELCDIF_CSC_COEFF0_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF0_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF0_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF0_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF0_C0	16
+#define BM_ELCDIF_CSC_COEFF0_C0	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF0_C0(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF0_C0)
+#define BP_ELCDIF_CSC_COEFF0_RSRVD0	2
+#define BM_ELCDIF_CSC_COEFF0_RSRVD0	0x0000FFFC
+#define BF_ELCDIF_CSC_COEFF0_RSRVD0(v)  \
+		(((v) << 2) & BM_ELCDIF_CSC_COEFF0_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER	0
+#define BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER	0x00000003
+#define BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER)
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD           0x1
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL    0x2
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED         0x3
+
+#define HW_ELCDIF_CSC_COEFF1	(0x00000120)
+
+#define BP_ELCDIF_CSC_COEFF1_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF1_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF1_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF1_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF1_C2	16
+#define BM_ELCDIF_CSC_COEFF1_C2	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF1_C2(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF1_C2)
+#define BP_ELCDIF_CSC_COEFF1_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF1_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF1_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF1_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF1_C1	0
+#define BM_ELCDIF_CSC_COEFF1_C1	0x000003FF
+#define BF_ELCDIF_CSC_COEFF1_C1(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF1_C1)
+
+#define HW_ELCDIF_CSC_COEFF2	(0x00000130)
+
+#define BP_ELCDIF_CSC_COEFF2_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF2_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF2_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF2_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF2_C4	16
+#define BM_ELCDIF_CSC_COEFF2_C4	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF2_C4(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF2_C4)
+#define BP_ELCDIF_CSC_COEFF2_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF2_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF2_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF2_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF2_C3	0
+#define BM_ELCDIF_CSC_COEFF2_C3	0x000003FF
+#define BF_ELCDIF_CSC_COEFF2_C3(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF2_C3)
+
+#define HW_ELCDIF_CSC_COEFF3	(0x00000140)
+
+#define BP_ELCDIF_CSC_COEFF3_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF3_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF3_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF3_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF3_C6	16
+#define BM_ELCDIF_CSC_COEFF3_C6	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF3_C6(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF3_C6)
+#define BP_ELCDIF_CSC_COEFF3_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF3_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF3_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF3_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF3_C5	0
+#define BM_ELCDIF_CSC_COEFF3_C5	0x000003FF
+#define BF_ELCDIF_CSC_COEFF3_C5(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF3_C5)
+
+#define HW_ELCDIF_CSC_COEFF4	(0x00000150)
+
+#define BP_ELCDIF_CSC_COEFF4_RSRVD1	26
+#define BM_ELCDIF_CSC_COEFF4_RSRVD1	0xFC000000
+#define BF_ELCDIF_CSC_COEFF4_RSRVD1(v) \
+		(((v) << 26) & BM_ELCDIF_CSC_COEFF4_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF4_C8	16
+#define BM_ELCDIF_CSC_COEFF4_C8	0x03FF0000
+#define BF_ELCDIF_CSC_COEFF4_C8(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_COEFF4_C8)
+#define BP_ELCDIF_CSC_COEFF4_RSRVD0	10
+#define BM_ELCDIF_CSC_COEFF4_RSRVD0	0x0000FC00
+#define BF_ELCDIF_CSC_COEFF4_RSRVD0(v)  \
+		(((v) << 10) & BM_ELCDIF_CSC_COEFF4_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF4_C7	0
+#define BM_ELCDIF_CSC_COEFF4_C7	0x000003FF
+#define BF_ELCDIF_CSC_COEFF4_C7(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_COEFF4_C7)
+
+#define HW_ELCDIF_CSC_OFFSET	(0x00000160)
+
+#define BP_ELCDIF_CSC_OFFSET_RSRVD1	25
+#define BM_ELCDIF_CSC_OFFSET_RSRVD1	0xFE000000
+#define BF_ELCDIF_CSC_OFFSET_RSRVD1(v) \
+		(((v) << 25) & BM_ELCDIF_CSC_OFFSET_RSRVD1)
+#define BP_ELCDIF_CSC_OFFSET_CBCR_OFFSET	16
+#define BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET	0x01FF0000
+#define BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET)
+#define BP_ELCDIF_CSC_OFFSET_RSRVD0	9
+#define BM_ELCDIF_CSC_OFFSET_RSRVD0	0x0000FE00
+#define BF_ELCDIF_CSC_OFFSET_RSRVD0(v)  \
+		(((v) << 9) & BM_ELCDIF_CSC_OFFSET_RSRVD0)
+#define BP_ELCDIF_CSC_OFFSET_Y_OFFSET	0
+#define BM_ELCDIF_CSC_OFFSET_Y_OFFSET	0x000001FF
+#define BF_ELCDIF_CSC_OFFSET_Y_OFFSET(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_OFFSET_Y_OFFSET)
+
+#define HW_ELCDIF_CSC_LIMIT	(0x00000170)
+
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MIN	24
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MIN	0xFF000000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MIN(v) \
+		(((v) << 24) & BM_ELCDIF_CSC_LIMIT_CBCR_MIN)
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MAX	16
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MAX	0x00FF0000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MAX(v)  \
+		(((v) << 16) & BM_ELCDIF_CSC_LIMIT_CBCR_MAX)
+#define BP_ELCDIF_CSC_LIMIT_Y_MIN	8
+#define BM_ELCDIF_CSC_LIMIT_Y_MIN	0x0000FF00
+#define BF_ELCDIF_CSC_LIMIT_Y_MIN(v)  \
+		(((v) << 8) & BM_ELCDIF_CSC_LIMIT_Y_MIN)
+#define BP_ELCDIF_CSC_LIMIT_Y_MAX	0
+#define BM_ELCDIF_CSC_LIMIT_Y_MAX	0x000000FF
+#define BF_ELCDIF_CSC_LIMIT_Y_MAX(v)  \
+		(((v) << 0) & BM_ELCDIF_CSC_LIMIT_Y_MAX)
+
+#define HW_ELCDIF_DATA	(0x00000180)
+
+#define BP_ELCDIF_DATA_DATA_THREE	24
+#define BM_ELCDIF_DATA_DATA_THREE	0xFF000000
+#define BF_ELCDIF_DATA_DATA_THREE(v) \
+		(((v) << 24) & BM_ELCDIF_DATA_DATA_THREE)
+#define BP_ELCDIF_DATA_DATA_TWO	16
+#define BM_ELCDIF_DATA_DATA_TWO	0x00FF0000
+#define BF_ELCDIF_DATA_DATA_TWO(v)  \
+		(((v) << 16) & BM_ELCDIF_DATA_DATA_TWO)
+#define BP_ELCDIF_DATA_DATA_ONE	8
+#define BM_ELCDIF_DATA_DATA_ONE	0x0000FF00
+#define BF_ELCDIF_DATA_DATA_ONE(v)  \
+		(((v) << 8) & BM_ELCDIF_DATA_DATA_ONE)
+#define BP_ELCDIF_DATA_DATA_ZERO	0
+#define BM_ELCDIF_DATA_DATA_ZERO	0x000000FF
+#define BF_ELCDIF_DATA_DATA_ZERO(v)  \
+		(((v) << 0) & BM_ELCDIF_DATA_DATA_ZERO)
+
+#define HW_ELCDIF_BM_ERROR_STAT	(0x00000190)
+
+#define BP_ELCDIF_BM_ERROR_STAT_ADDR	0
+#define BM_ELCDIF_BM_ERROR_STAT_ADDR	0xFFFFFFFF
+#define BF_ELCDIF_BM_ERROR_STAT_ADDR(v)	(v)
+
+#define HW_ELCDIF_CRC_STAT	(0x000001a0)
+
+#define BP_ELCDIF_CRC_STAT_CRC_VALUE	0
+#define BM_ELCDIF_CRC_STAT_CRC_VALUE	0xFFFFFFFF
+#define BF_ELCDIF_CRC_STAT_CRC_VALUE(v)	(v)
+
+#define HW_ELCDIF_STAT	(0x000001b0)
+
+#define BM_ELCDIF_STAT_PRESENT	0x80000000
+#define BM_ELCDIF_STAT_DMA_REQ	0x40000000
+#define BM_ELCDIF_STAT_LFIFO_FULL	0x20000000
+#define BM_ELCDIF_STAT_LFIFO_EMPTY	0x10000000
+#define BM_ELCDIF_STAT_TXFIFO_FULL	0x08000000
+#define BM_ELCDIF_STAT_TXFIFO_EMPTY	0x04000000
+#define BM_ELCDIF_STAT_BUSY	0x02000000
+#define BM_ELCDIF_STAT_DVI_CURRENT_FIELD	0x01000000
+#define BP_ELCDIF_STAT_RSRVD0	9
+#define BM_ELCDIF_STAT_RSRVD0	0x00FFFE00
+#define BF_ELCDIF_STAT_RSRVD0(v)  \
+		(((v) << 9) & BM_ELCDIF_STAT_RSRVD0)
+#define BP_ELCDIF_STAT_LFIFO_COUNT	0
+#define BM_ELCDIF_STAT_LFIFO_COUNT	0x000001FF
+#define BF_ELCDIF_STAT_LFIFO_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_STAT_LFIFO_COUNT)
+
+#define HW_ELCDIF_VERSION	(0x000001c0)
+
+#define BP_ELCDIF_VERSION_MAJOR	24
+#define BM_ELCDIF_VERSION_MAJOR	0xFF000000
+#define BF_ELCDIF_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_ELCDIF_VERSION_MAJOR)
+#define BP_ELCDIF_VERSION_MINOR	16
+#define BM_ELCDIF_VERSION_MINOR	0x00FF0000
+#define BF_ELCDIF_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_ELCDIF_VERSION_MINOR)
+#define BP_ELCDIF_VERSION_STEP	0
+#define BM_ELCDIF_VERSION_STEP	0x0000FFFF
+#define BF_ELCDIF_VERSION_STEP(v)  \
+		(((v) << 0) & BM_ELCDIF_VERSION_STEP)
+
+#define HW_ELCDIF_DEBUG0	(0x000001d0)
+
+#define BM_ELCDIF_DEBUG0_STREAMING_END_DETECTED	0x80000000
+#define BM_ELCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT	0x40000000
+#define BM_ELCDIF_DEBUG0_SYNC_SIGNALS_ON_REG	0x20000000
+#define BM_ELCDIF_DEBUG0_DMACMDKICK	0x10000000
+#define BM_ELCDIF_DEBUG0_ENABLE	0x08000000
+#define BM_ELCDIF_DEBUG0_HSYNC	0x04000000
+#define BM_ELCDIF_DEBUG0_VSYNC	0x02000000
+#define BM_ELCDIF_DEBUG0_CUR_FRAME_TX	0x01000000
+#define BM_ELCDIF_DEBUG0_EMPTY_WORD	0x00800000
+#define BP_ELCDIF_DEBUG0_CUR_STATE	16
+#define BM_ELCDIF_DEBUG0_CUR_STATE	0x007F0000
+#define BF_ELCDIF_DEBUG0_CUR_STATE(v)  \
+		(((v) << 16) & BM_ELCDIF_DEBUG0_CUR_STATE)
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B0_READY	0x00008000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B0_DONE	0x00004000
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B1_READY	0x00002000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B1_DONE	0x00001000
+#define BP_ELCDIF_DEBUG0_CUR_REQ_STATE	10
+#define BM_ELCDIF_DEBUG0_CUR_REQ_STATE	0x00000C00
+#define BF_ELCDIF_DEBUG0_CUR_REQ_STATE(v)  \
+		(((v) << 10) & BM_ELCDIF_DEBUG0_CUR_REQ_STATE)
+#define BM_ELCDIF_DEBUG0_MST_AVALID	0x00000200
+#define BP_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS	4
+#define BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS	0x000001F0
+#define BF_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS(v)  \
+		(((v) << 4) & BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS)
+#define BP_ELCDIF_DEBUG0_MST_WORDS	0
+#define BM_ELCDIF_DEBUG0_MST_WORDS	0x0000000F
+#define BF_ELCDIF_DEBUG0_MST_WORDS(v)  \
+		(((v) << 0) & BM_ELCDIF_DEBUG0_MST_WORDS)
+
+#define HW_ELCDIF_DEBUG1	(0x000001e0)
+
+#define BP_ELCDIF_DEBUG1_H_DATA_COUNT	16
+#define BM_ELCDIF_DEBUG1_H_DATA_COUNT	0xFFFF0000
+#define BF_ELCDIF_DEBUG1_H_DATA_COUNT(v) \
+		(((v) << 16) & BM_ELCDIF_DEBUG1_H_DATA_COUNT)
+#define BP_ELCDIF_DEBUG1_V_DATA_COUNT	0
+#define BM_ELCDIF_DEBUG1_V_DATA_COUNT	0x0000FFFF
+#define BF_ELCDIF_DEBUG1_V_DATA_COUNT(v)  \
+		(((v) << 0) & BM_ELCDIF_DEBUG1_V_DATA_COUNT)
+
+#define HW_ELCDIF_DEBUG2	(0x000001f0)
+
+#define BP_ELCDIF_DEBUG2_MST_ADDRESS	0
+#define BM_ELCDIF_DEBUG2_MST_ADDRESS	0xFFFFFFFF
+#define BF_ELCDIF_DEBUG2_MST_ADDRESS(v)	(v)
+#endif /* __ELCDIF_REGS_INCLUDED_ */
diff --git a/drivers/video/mxc/epdc_regs.h b/drivers/video/mxc/epdc_regs.h
new file mode 100644
index 000000000000..1d0635b928ad
--- /dev/null
+++ b/drivers/video/mxc/epdc_regs.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+#ifndef __EPDC_REGS_INCLUDED__
+#define __EPDC_REGS_INCLUDED__
+
+extern void __iomem *epdc_base;
+
+//*************************************
+// Register addresses
+//*************************************
+
+#define EPDC_CTRL			(epdc_base + 0x000)
+#define EPDC_CTRL_SET			(epdc_base + 0x004)
+#define EPDC_CTRL_CLEAR		(epdc_base + 0x008)
+#define EPDC_CTRL_TOGGLE		(epdc_base + 0x00C)
+#define EPDC_WVADDR			(epdc_base + 0x020)
+#define EPDC_WB_ADDR			(epdc_base + 0x030)
+#define EPDC_RES			(epdc_base + 0x040)
+#define EPDC_FORMAT			(epdc_base + 0x050)
+#define EPDC_FORMAT_SET		(epdc_base + 0x054)
+#define EPDC_FORMAT_CLEAR		(epdc_base + 0x058)
+#define EPDC_FORMAT_TOGGLE		(epdc_base + 0x05C)
+#define EPDC_FIFOCTRL			(epdc_base + 0x0A0)
+#define EPDC_FIFOCTRL_SET		(epdc_base + 0x0A4)
+#define EPDC_FIFOCTRL_CLEAR		(epdc_base + 0x0A8)
+#define EPDC_FIFOCTRL_TOGGLE		(epdc_base + 0x0AC)
+#define EPDC_UPD_ADDR			(epdc_base + 0x100)
+#define EPDC_UPD_CORD			(epdc_base + 0x120)
+#define EPDC_UPD_SIZE			(epdc_base + 0x140)
+#define EPDC_UPD_CTRL			(epdc_base + 0x160)
+#define EPDC_UPD_FIXED			(epdc_base + 0x180)
+#define EPDC_TEMP			(epdc_base + 0x1A0)
+#define EPDC_TCE_CTRL			(epdc_base + 0x200)
+#define EPDC_TCE_SDCFG			(epdc_base + 0x220)
+#define EPDC_TCE_GDCFG			(epdc_base + 0x240)
+#define EPDC_TCE_HSCAN1		(epdc_base + 0x260)
+#define EPDC_TCE_HSCAN2		(epdc_base + 0x280)
+#define EPDC_TCE_VSCAN			(epdc_base + 0x2A0)
+#define EPDC_TCE_OE			(epdc_base + 0x2C0)
+#define EPDC_TCE_POLARITY		(epdc_base + 0x2E0)
+#define EPDC_TCE_TIMING1		(epdc_base + 0x300)
+#define EPDC_TCE_TIMING2		(epdc_base + 0x310)
+#define EPDC_TCE_TIMING3		(epdc_base + 0x320)
+#define EPDC_IRQ_MASK			(epdc_base + 0x400)
+#define EPDC_IRQ_MASK_SET		(epdc_base + 0x404)
+#define EPDC_IRQ_MASK_CLEAR		(epdc_base + 0x408)
+#define EPDC_IRQ_MASK_TOGGLE		(epdc_base + 0x40C)
+#define EPDC_IRQ			(epdc_base + 0x420)
+#define EPDC_IRQ_SET			(epdc_base + 0x424)
+#define EPDC_IRQ_CLEAR			(epdc_base + 0x428)
+#define EPDC_IRQ_TOGGLE		(epdc_base + 0x42C)
+#define EPDC_STATUS_LUTS		(epdc_base + 0x440)
+#define EPDC_STATUS_LUTS_SET	(epdc_base + 0x444)
+#define EPDC_STATUS_LUTS_CLEAR	(epdc_base + 0x448)
+#define EPDC_STATUS_LUTS_TOGGLE	(epdc_base + 0x44C)
+#define EPDC_STATUS_NEXTLUT		(epdc_base + 0x460)
+#define EPDC_STATUS_COL		(epdc_base + 0x480)
+#define EPDC_STATUS			(epdc_base + 0x4A0)
+#define EPDC_STATUS_SET		(epdc_base + 0x4A4)
+#define EPDC_STATUS_CLEAR		(epdc_base + 0x4A8)
+#define EPDC_STATUS_TOGGLE		(epdc_base + 0x4AC)
+#define EPDC_DEBUG			(epdc_base + 0x500)
+#define EPDC_DEBUG_LUT0		(epdc_base + 0x540)
+#define EPDC_DEBUG_LUT1		(epdc_base + 0x550)
+#define EPDC_DEBUG_LUT2		(epdc_base + 0x560)
+#define EPDC_DEBUG_LUT3		(epdc_base + 0x570)
+#define EPDC_DEBUG_LUT4		(epdc_base + 0x580)
+#define EPDC_DEBUG_LUT5		(epdc_base + 0x590)
+#define EPDC_DEBUG_LUT6		(epdc_base + 0x5A0)
+#define EPDC_DEBUG_LUT7		(epdc_base + 0x5B0)
+#define EPDC_DEBUG_LUT8		(epdc_base + 0x5C0)
+#define EPDC_DEBUG_LUT9		(epdc_base + 0x5D0)
+#define EPDC_DEBUG_LUT10		(epdc_base + 0x5E0)
+#define EPDC_DEBUG_LUT11		(epdc_base + 0x5F0)
+#define EPDC_DEBUG_LUT12		(epdc_base + 0x600)
+#define EPDC_DEBUG_LUT13		(epdc_base + 0x610)
+#define EPDC_DEBUG_LUT14		(epdc_base + 0x620)
+#define EPDC_DEBUG_LUT15		(epdc_base + 0x630)
+#define EPDC_GPIO			(epdc_base + 0x700)
+#define EPDC_VERSION			(epdc_base + 0x7F0)
+
+/*
+ * Register field definitions
+ */
+
+enum {
+/* EPDC_CTRL field values */
+	EPDC_CTRL_SFTRST = 0x80000000,
+	EPDC_CTRL_CLKGATE = 0x40000000,
+	EPDC_CTRL_SRAM_POWERDOWN = 0x100,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
+	EPDC_CTRL_BURST_LEN_8_8 = 0x1,
+	EPDC_CTRL_BURST_LEN_8_16 = 0,
+
+/* EPDC_RES field values */
+	EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
+	EPDC_RES_VERTICAL_OFFSET = 16,
+	EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
+	EPDC_RES_HORIZONTAL_OFFSET = 0,
+
+/* EPDC_FORMAT field values */
+	EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
+
+/* EPDC_FIFOCTRL field values */
+	EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
+
+/* EPDC_UPD_CORD field values */
+	EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
+	EPDC_UPD_CORD_YCORD_OFFSET = 16,
+	EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
+	EPDC_UPD_CORD_XCORD_OFFSET = 0,
+
+/* EPDC_UPD_SIZE field values */
+	EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
+	EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
+	EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
+	EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
+
+/* EPDC_UPD_CTRL field values */
+	EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
+	EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000,
+	EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+	EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
+
+/* EPDC_UPD_FIXED field values */
+	EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
+	EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
+	EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
+	EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
+	EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
+	EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
+
+/* EPDC_TCE_CTRL field values */
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
+	EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
+	EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
+	EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
+	EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
+	EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
+	EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
+	EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
+	EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
+	EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
+	EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
+	EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
+
+/* EPDC_TCE_SDCFG field values */
+	EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
+	EPDC_TCE_SDCFG_SDSHR = 0x100000,
+	EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
+	EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
+	EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
+
+/* EPDC_TCE_GDCFG field values */
+	EPDC_TCE_SDCFG_GDRL = 0x10,
+	EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
+	EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
+	EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
+
+/* EPDC_TCE_HSCAN1 field values */
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
+	EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
+	EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_HSCAN2 field values */
+	EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
+
+/* EPDC_TCE_VSCAN field values */
+	EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
+	EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
+	EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
+	EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_OE field values */
+	EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
+	EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
+	EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
+	EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
+	EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
+	EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
+	EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
+	EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
+
+/* EPDC_TCE_POLARITY field values */
+	EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
+	EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
+	EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
+	EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
+	EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
+
+/* EPDC_TCE_TIMING1 field values */
+	EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
+	EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
+
+/* EPDC_TCE_TIMING2 field values */
+	EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
+
+/* EPDC_TCE_TIMING3 field values */
+	EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
+
+/* EPDC_IRQ_MASK/EPDC_IRQ field values */
+	EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
+	EPDC_IRQ_LUT_COL_IRQ = 0x20000,
+	EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
+	EPDC_IRQ_FRAME_END_IRQ = 0x80000,
+	EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
+	EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+
+/* EPDC_STATUS_NEXTLUT field values */
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xF,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
+
+/* EPDC_STATUS field values */
+	EPDC_STATUS_LUTS_UNDERRUN = 0x4,
+	EPDC_STATUS_LUTS_BUSY = 0x2,
+	EPDC_STATUS_WB_BUSY = 0x1,
+
+/* EPDC_DEBUG field values */
+	EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
+	EPDC_DEBUG_COLLISION_OFF = 0x1,
+
+/* EPDC_GPIO field values */
+	EPDC_GPIO_PWRCOM = 0x40,
+	EPDC_GPIO_PWRCTRL_MASK = 0x3C,
+	EPDC_GPIO_PWRCTRL_OFFSET = 2,
+	EPDC_GPIO_BDR_MASK = 0x3,
+	EPDC_GPIO_BDR_OFFSET = 0,
+};
+
+#endif	/* __EPDC_REGS_INCLUDED__ */
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
new file mode 100644
index 000000000000..fe58146df3cb
--- /dev/null
+++ b/drivers/video/mxc/ldb.c
@@ -0,0 +1,1448 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file mxc_ldb.c
+ *
+ * @brief This file contains the LDB driver device interface and fops
+ * functions.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/ldb.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <mach/hardware.h>
+
+#define LDB_BGREF_RMODE_MASK		0x00008000
+#define LDB_BGREF_RMODE_INT		0x00008000
+#define LDB_BGREF_RMODE_EXT		0x0
+
+#define LDB_DI1_VS_POL_MASK		0x00000400
+#define LDB_DI1_VS_POL_ACT_LOW		0x00000400
+#define LDB_DI1_VS_POL_ACT_HIGH		0x0
+#define LDB_DI0_VS_POL_MASK		0x00000200
+#define LDB_DI0_VS_POL_ACT_LOW		0x00000200
+#define LDB_DI0_VS_POL_ACT_HIGH		0x0
+
+#define LDB_BIT_MAP_CH1_MASK		0x00000100
+#define LDB_BIT_MAP_CH1_JEIDA		0x00000100
+#define LDB_BIT_MAP_CH1_SPWG		0x0
+#define LDB_BIT_MAP_CH0_MASK		0x00000040
+#define LDB_BIT_MAP_CH0_JEIDA		0x00000040
+#define LDB_BIT_MAP_CH0_SPWG		0x0
+
+#define LDB_DATA_WIDTH_CH1_MASK		0x00000080
+#define LDB_DATA_WIDTH_CH1_24		0x00000080
+#define LDB_DATA_WIDTH_CH1_18		0x0
+#define LDB_DATA_WIDTH_CH0_MASK		0x00000020
+#define LDB_DATA_WIDTH_CH0_24		0x00000020
+#define LDB_DATA_WIDTH_CH0_18		0x0
+
+#define LDB_CH1_MODE_MASK		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI1		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI0		0x00000004
+#define LDB_CH1_MODE_DISABLE		0x0
+#define LDB_CH0_MODE_MASK		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI1		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI0		0x00000001
+#define LDB_CH0_MODE_DISABLE		0x0
+
+#define LDB_SPLIT_MODE_EN		0x00000010
+
+enum ldb_chan_mode_opt {
+	LDB_SIN_DI0 = 0,
+	LDB_SIN_DI1 = 1,
+	LDB_SEP = 2,
+	LDB_DUL_DI0 = 3,
+	LDB_DUL_DI1 = 4,
+	LDB_SPL_DI0 = 5,
+	LDB_SPL_DI1 = 6,
+};
+
+static struct ldb_data {
+	struct fb_info *fbi[2];
+	bool ch_working[2];
+	uint32_t chan_mode_opt;
+	uint32_t chan_bit_map[2];
+	uint32_t bgref_rmode;
+	uint32_t base_addr;
+	uint32_t *control_reg;
+	struct clk *ldb_di_clk[2];
+	struct regulator *lvds_bg_reg;
+	struct list_head modelist;
+} ldb;
+
+static struct device *g_ldb_dev;
+static u32 *ldb_reg;
+static bool enabled[2];
+static int g_chan_mode_opt;
+static int g_chan_bit_map[2];
+static bool g_enable_ldb;
+static bool g_boot_cmd;
+
+DEFINE_SPINLOCK(ldb_lock);
+
+struct fb_videomode mxcfb_ldb_modedb[] = {
+	{
+	 "1080P60", 60, 1920, 1080, 7692,
+	 100, 40,
+	 30, 3,
+	 10, 2,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 "XGA", 60, 1024, 768, 15385,
+	 220, 40,
+	 21, 7,
+	 60, 10,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+int mxcfb_ldb_modedb_sz = ARRAY_SIZE(mxcfb_ldb_modedb);
+
+static int bits_per_pixel(int pixel_fmt)
+{
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 24;
+		break;
+	case IPU_PIX_FMT_BGR666:
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_LVDS666:
+		return 18;
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int valid_mode(int pixel_fmt)
+{
+	return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR24) ||
+		(pixel_fmt == IPU_PIX_FMT_LVDS666) ||
+		(pixel_fmt == IPU_PIX_FMT_RGB666) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR666));
+}
+
+static void ldb_disable(int ipu_di)
+{
+	uint32_t reg;
+	int i = 0;
+
+	spin_lock(&ldb_lock);
+
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (ipu_di != 0 || !ldb.ch_working[0] || !enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			     LDB_CH0_MODE_DISABLE,
+			     ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_disable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+
+		ldb.ch_working[0] = false;
+		enabled[0] = false;
+		break;
+	case LDB_SIN_DI1:
+		if (ipu_di != 1 || !ldb.ch_working[1] || !enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			     LDB_CH1_MODE_DISABLE,
+			     ldb.control_reg);
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_disable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		ldb.ch_working[1] = false;
+		enabled[1] = false;
+		break;
+	case LDB_SPL_DI0:
+	case LDB_DUL_DI0:
+		if (ipu_di != 0 || !enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		for (i = 0; i < 2; i++) {
+			if (ldb.ch_working[i]) {
+				reg = __raw_readl(ldb.control_reg);
+				if (i == 0)
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH0_MODE_DISABLE,
+						     ldb.control_reg);
+				else
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH1_MODE_DISABLE,
+						     ldb.control_reg);
+
+				if (ldb.chan_mode_opt == LDB_SPL_DI0) {
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+						     ldb.control_reg);
+				}
+
+				ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+							"ldb_di1_clk" :
+							"ldb_di0_clk");
+				clk_disable(ldb.ldb_di_clk[i]);
+				clk_put(ldb.ldb_di_clk[i]);
+
+				ldb.ch_working[i] = false;
+			}
+		}
+		enabled[0] = false;
+		break;
+	case LDB_SPL_DI1:
+	case LDB_DUL_DI1:
+		if (ipu_di != 1 || !enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		for (i = 0; i < 2; i++) {
+			if (ldb.ch_working[i]) {
+				reg = __raw_readl(ldb.control_reg);
+				if (i == 0)
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH0_MODE_DISABLE,
+						     ldb.control_reg);
+				else
+					__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+						     LDB_CH1_MODE_DISABLE,
+						     ldb.control_reg);
+
+				if (ldb.chan_mode_opt == LDB_SPL_DI1) {
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+						     ldb.control_reg);
+				}
+
+				ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+							"ldb_di1_clk" :
+							"ldb_di0_clk");
+				clk_disable(ldb.ldb_di_clk[i]);
+				clk_put(ldb.ldb_di_clk[i]);
+
+				ldb.ch_working[i] = false;
+			}
+		}
+		enabled[1] = false;
+		break;
+	case LDB_SEP:
+		if (ldb.ch_working[ipu_di] && enabled[ipu_di]) {
+			reg = __raw_readl(ldb.control_reg);
+			if (ipu_di == 0)
+				__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+					     LDB_CH0_MODE_DISABLE,
+					     ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+					     LDB_CH1_MODE_DISABLE,
+					     ldb.control_reg);
+
+			ldb.ldb_di_clk[ipu_di] = clk_get(NULL, ipu_di ?
+							       "ldb_di1_clk" :
+							       "ldb_di0_clk");
+			clk_disable(ldb.ldb_di_clk[ipu_di]);
+			clk_put(ldb.ldb_di_clk[ipu_di]);
+
+			ldb.ch_working[ipu_di] = false;
+			enabled[ipu_di] = false;
+		}
+		break;
+	default:
+		break;
+	}
+
+	spin_unlock(&ldb_lock);
+	return;
+}
+
+static void ldb_enable(int ipu_di)
+{
+	uint32_t reg;
+
+	spin_lock(&ldb_lock);
+
+	reg = __raw_readl(ldb.control_reg);
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (ldb.ch_working[0] || ipu_di != 0 || enabled[0]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			      LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		enabled[0] = true;
+		break;
+	case LDB_SIN_DI1:
+		if (ldb.ch_working[1] || ipu_di != 1 || enabled[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[1] = true;
+		enabled[1] = true;
+		break;
+	case LDB_SEP:
+		if (ldb.ch_working[ipu_di] || enabled[ipu_di]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		if (ipu_di == 0) {
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			clk_enable(ldb.ldb_di_clk[0]);
+			clk_put(ldb.ldb_di_clk[0]);
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+			ldb.ch_working[0] = true;
+		} else {
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			clk_enable(ldb.ldb_di_clk[1]);
+			clk_put(ldb.ldb_di_clk[1]);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			ldb.ch_working[1] = true;
+		}
+		enabled[ipu_di] = true;
+		break;
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		if (ipu_di != 0 || enabled[0])
+			return;
+		else
+			goto proc;
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		if (ipu_di != 1 || enabled[1])
+			return;
+proc:
+		if (ldb.ch_working[0] || ldb.ch_working[1]) {
+			spin_unlock(&ldb_lock);
+			return;
+		}
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		if (ldb.chan_mode_opt == LDB_DUL_DI0 ||
+		    ldb.chan_mode_opt == LDB_SPL_DI0) {
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI0,
+				      ldb.control_reg);
+		} else if (ldb.chan_mode_opt == LDB_DUL_DI1 ||
+			   ldb.chan_mode_opt == LDB_SPL_DI1) {
+			__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+				      LDB_CH0_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+		}
+		if (ldb.chan_mode_opt == LDB_SPL_DI0 ||
+		    ldb.chan_mode_opt == LDB_SPL_DI1) {
+			reg = __raw_readl(ldb.control_reg);
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+		}
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		enabled[ipu_di] = true;
+		break;
+	default:
+		break;
+	}
+	spin_unlock(&ldb_lock);
+	return;
+}
+
+int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+	mm_segment_t old_fs;
+	int ipu_di = 0;
+
+	switch (val) {
+	case FB_EVENT_BLANK:
+		if (ldb.fbi[0] != fbi && ldb.fbi[1] != fbi)
+			return 0;
+
+		if (fbi->fbops->fb_ioctl) {
+			old_fs = get_fs();
+			set_fs(KERNEL_DS);
+			fbi->fbops->fb_ioctl(fbi,
+					MXCFB_GET_FB_IPU_DI,
+					(unsigned long)&ipu_di);
+			set_fs(old_fs);
+		} else
+			return 0;
+
+		if (*((int *)event->data) == FB_BLANK_UNBLANK)
+			ldb_enable(ipu_di);
+		else
+			ldb_disable(ipu_di);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = ldb_fb_event,
+};
+
+static int mxc_ldb_ioctl(struct inode *inode, struct file *file,
+		unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	uint32_t reg;
+
+	switch (cmd) {
+	case LDB_BGREF_RMODE:
+		{
+		ldb_bgref_parm parm;
+
+		if (copy_from_user(&parm, (ldb_bgref_parm *) arg,
+				   sizeof(ldb_bgref_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.bgref_mode == LDB_EXT_REF)
+			__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+				      LDB_BGREF_RMODE_EXT, ldb.control_reg);
+		else if (parm.bgref_mode == LDB_INT_REF)
+			__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+				      LDB_BGREF_RMODE_INT, ldb.control_reg);
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_VSYNC_POL:
+		{
+		ldb_vsync_parm parm;
+
+		if (copy_from_user(&parm, (ldb_vsync_parm *) arg,
+				   sizeof(ldb_vsync_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.vsync_mode == LDB_VS_ACT_H) {
+			if (parm.di == 0)
+				__raw_writel((reg &
+					~LDB_DI0_VS_POL_MASK) |
+					LDB_DI0_VS_POL_ACT_HIGH,
+					ldb.control_reg);
+			else
+				__raw_writel((reg &
+					~LDB_DI1_VS_POL_MASK) |
+					LDB_DI1_VS_POL_ACT_HIGH,
+					ldb.control_reg);
+		} else if (parm.vsync_mode == LDB_VS_ACT_L) {
+			if (parm.di == 0)
+				__raw_writel((reg &
+					~LDB_DI0_VS_POL_MASK) |
+					LDB_DI0_VS_POL_ACT_LOW,
+					ldb.control_reg);
+			else
+				__raw_writel((reg &
+					~LDB_DI1_VS_POL_MASK) |
+					LDB_DI1_VS_POL_ACT_LOW,
+					ldb.control_reg);
+
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_BIT_MAP:
+		{
+		ldb_bitmap_parm parm;
+
+		if (copy_from_user(&parm, (ldb_bitmap_parm *) arg,
+				   sizeof(ldb_bitmap_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.bitmap_mode == LDB_BIT_MAP_SPWG) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH0_SPWG,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH1_SPWG,
+					      ldb.control_reg);
+		} else if (parm.bitmap_mode == LDB_BIT_MAP_JEIDA) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH0_JEIDA,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+					      LDB_BIT_MAP_CH1_JEIDA,
+					      ldb.control_reg);
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_DATA_WIDTH:
+		{
+		ldb_data_width_parm parm;
+
+		if (copy_from_user(&parm, (ldb_data_width_parm *) arg,
+				   sizeof(ldb_data_width_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+		reg = __raw_readl(ldb.control_reg);
+		if (parm.data_width == 24) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH0_24,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH1_24,
+					      ldb.control_reg);
+		} else if (parm.data_width == 18) {
+			if (parm.channel == 0)
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH0_18,
+					      ldb.control_reg);
+			else
+				__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+					      LDB_DATA_WIDTH_CH1_18,
+					      ldb.control_reg);
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_CHAN_MODE:
+		{
+		ldb_chan_mode_parm parm;
+		struct clk *pll4_clk;
+		unsigned long pll4_rate = 0;
+
+		if (copy_from_user(&parm, (ldb_chan_mode_parm *) arg,
+				   sizeof(ldb_chan_mode_parm)))
+			return -EFAULT;
+
+		spin_lock(&ldb_lock);
+
+		/* TODO:Set the correct pll4 rate for all situations */
+		pll4_clk = clk_get(NULL, "pll4");
+		pll4_rate = clk_get_rate(pll4_clk);
+		pll4_rate = 455000000;
+		clk_set_rate(pll4_clk, pll4_rate);
+		clk_put(pll4_clk);
+
+		reg = __raw_readl(ldb.control_reg);
+		switch (parm.channel_mode) {
+		case LDB_CHAN_MODE_SIN:
+			if (parm.di == 0) {
+				ldb.chan_mode_opt = LDB_SIN_DI0;
+
+				ldb.ldb_di_clk[0] = clk_get(NULL,
+							    "ldb_di0_clk");
+				clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+				clk_put(ldb.ldb_di_clk[0]);
+
+				__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+					      LDB_CH0_MODE_EN_TO_DI0,
+					      ldb.control_reg);
+			} else {
+				ldb.chan_mode_opt = LDB_SIN_DI1;
+
+				ldb.ldb_di_clk[1] = clk_get(NULL,
+							    "ldb_di1_clk");
+				clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+				clk_put(ldb.ldb_di_clk[1]);
+
+				__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+					      LDB_CH1_MODE_EN_TO_DI1,
+					      ldb.control_reg);
+			}
+			break;
+		case LDB_CHAN_MODE_SEP:
+			ldb.chan_mode_opt = LDB_SEP;
+
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+			clk_put(ldb.ldb_di_clk[0]);
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+			clk_put(ldb.ldb_di_clk[1]);
+
+			__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+					      LDB_CH1_MODE_MASK)) |
+				      LDB_CH0_MODE_EN_TO_DI0 |
+				      LDB_CH1_MODE_EN_TO_DI1,
+				      ldb.control_reg);
+			break;
+		case LDB_CHAN_MODE_DUL:
+		case LDB_CHAN_MODE_SPL:
+			ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+			ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+			if (parm.di == 0) {
+				if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+					ldb.chan_mode_opt = LDB_DUL_DI0;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     pll4_rate/7);
+				} else {
+					ldb.chan_mode_opt = LDB_SPL_DI0;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     2*pll4_rate/7);
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     2*pll4_rate/7);
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg | LDB_SPLIT_MODE_EN,
+						      ldb.control_reg);
+				}
+
+				reg = __raw_readl(ldb.control_reg);
+				__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+						      LDB_CH1_MODE_MASK)) |
+					      LDB_CH0_MODE_EN_TO_DI0 |
+					      LDB_CH1_MODE_EN_TO_DI0,
+					      ldb.control_reg);
+			} else {
+				if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+					ldb.chan_mode_opt = LDB_DUL_DI1;
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     pll4_rate/7);
+				} else {
+					ldb.chan_mode_opt = LDB_SPL_DI1;
+					clk_set_rate(ldb.ldb_di_clk[0],
+						     2*pll4_rate/7);
+					clk_set_rate(ldb.ldb_di_clk[1],
+						     2*pll4_rate/7);
+					reg = __raw_readl(ldb.control_reg);
+					__raw_writel(reg | LDB_SPLIT_MODE_EN,
+						      ldb.control_reg);
+				}
+
+				reg = __raw_readl(ldb.control_reg);
+				__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+						      LDB_CH1_MODE_MASK)) |
+					      LDB_CH0_MODE_EN_TO_DI1 |
+					      LDB_CH1_MODE_EN_TO_DI1,
+					      ldb.control_reg);
+			}
+			clk_put(ldb.ldb_di_clk[0]);
+			clk_put(ldb.ldb_di_clk[1]);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		spin_unlock(&ldb_lock);
+		break;
+		}
+	case LDB_ENABLE:
+		{
+		int ipu_di;
+
+		if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+			return -EFAULT;
+
+		ldb_enable(ipu_di);
+		break;
+		}
+	case LDB_DISABLE:
+		{
+		int ipu_di;
+
+		if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+			return -EFAULT;
+
+		ldb_disable(ipu_di);
+		break;
+		}
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int mxc_ldb_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mxc_ldb_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mxc_ldb_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+static const struct file_operations mxc_ldb_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_ldb_open,
+	.mmap = mxc_ldb_mmap,
+	.release = mxc_ldb_release,
+	.ioctl = mxc_ldb_ioctl
+};
+
+/*!
+ * This function is called by the driver framework to initialize the LDB
+ * device.
+ *
+ * @param	dev	The device structure for the LDB passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int ldb_probe(struct platform_device *pdev)
+{
+	int ret = 0, i, ipu_di, ipu_di_pix_fmt[2];
+	bool primary = false, find_1080p = false;
+	struct resource *res;
+	struct ldb_platform_data *plat_data = pdev->dev.platform_data;
+	mm_segment_t old_fs;
+	struct clk *ldb_clk_parent;
+	unsigned long ldb_clk_prate = 455000000;
+	struct fb_var_screeninfo *var[2];
+	uint32_t reg;
+	struct device *temp;
+	int mxc_ldb_major;
+	const struct fb_videomode *mode;
+	struct class *mxc_ldb_class;
+
+	if (g_enable_ldb == false)
+		return -ENODEV;
+
+	spin_lock_init(&ldb_lock);
+
+	g_ldb_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res))
+		return -ENODEV;
+
+	memset(&ldb, 0, sizeof(struct ldb_data));
+	enabled[0] = enabled[1] = false;
+	var[0] = var[1] = NULL;
+	if (g_boot_cmd) {
+		ldb.chan_mode_opt = g_chan_mode_opt;
+		ldb.chan_bit_map[0] = g_chan_bit_map[0];
+		ldb.chan_bit_map[1] = g_chan_bit_map[1];
+	}
+
+	ldb.base_addr = res->start;
+	ldb_reg = ioremap(ldb.base_addr, res->end - res->start + 1);
+	ldb.control_reg = ldb_reg + 2;
+
+	INIT_LIST_HEAD(&ldb.modelist);
+	for (i = 0; i < mxcfb_ldb_modedb_sz; i++)
+		fb_add_videomode(&mxcfb_ldb_modedb[i], &ldb.modelist);
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if ((registered_fb[i]->var.sync & FB_SYNC_EXT) &&
+		    (registered_fb[i]->var.vmode == FB_VMODE_NONINTERLACED)) {
+			ldb.fbi[i] = registered_fb[i];
+
+			mode = fb_match_mode(&ldb.fbi[i]->var, &ldb.modelist);
+			if (mode) {
+				dev_dbg(g_ldb_dev, "fb mode found\n");
+				fb_videomode_to_var(&ldb.fbi[i]->var, mode);
+			} else {
+				dev_warn(g_ldb_dev,
+						"can't find video mode\n");
+				goto err0;
+			}
+			/*
+			 * Default ldb mode:
+			 * 1080p: DI0 split, SPWG
+			 * others: single, SPWG
+			 */
+			if (g_boot_cmd == false) {
+				ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+				if (fb_mode_is_equal(mode, &mxcfb_ldb_modedb[0])) {
+					ldb.chan_mode_opt = LDB_SPL_DI0;
+					ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+					ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+					find_1080p = true;
+					dev_warn(g_ldb_dev, "default split mode\n");
+				} else if (!find_1080p) {
+					if (strcmp(ldb.fbi[i]->fix.id,
+					    "DISP3 BG") == 0) {
+						ldb.chan_mode_opt = LDB_SIN_DI0;
+						ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+						dev_warn(g_ldb_dev,
+							 "default di0 single mode\n");
+					} else if (strcmp(ldb.fbi[i]->fix.id,
+						   "DISP3 BG - DI1") == 0) {
+						ldb.chan_mode_opt = LDB_SIN_DI1;
+						ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+						dev_warn(g_ldb_dev,
+							 "default di1 single mode\n");
+					}
+				}
+			}
+
+			acquire_console_sem();
+			fb_blank(ldb.fbi[i], FB_BLANK_POWERDOWN);
+			release_console_sem();
+
+			if (i == 0)
+				primary = true;
+
+			if (ldb.fbi[1] != NULL)
+				break;
+		}
+	}
+
+	/*
+	 * We cannot support two LVDS panel with different pixel clock rates
+	 * except that one's pixel clock rate is two times of the others'.
+	 */
+	if (ldb.fbi[1] && ldb.fbi[0] != NULL) {
+		if (ldb.fbi[0]->var.pixclock != ldb.fbi[1]->var.pixclock &&
+		    ldb.fbi[0]->var.pixclock != 2 * ldb.fbi[1]->var.pixclock &&
+		    ldb.fbi[1]->var.pixclock != 2 * ldb.fbi[0]->var.pixclock)
+			return -EINVAL;
+	}
+
+	ldb.bgref_rmode = plat_data->ext_ref;
+	ldb.lvds_bg_reg = regulator_get(&pdev->dev, plat_data->lvds_bg_reg);
+	if (!IS_ERR(ldb.lvds_bg_reg)) {
+		regulator_set_voltage(ldb.lvds_bg_reg, 2500000, 2500000);
+		regulator_enable(ldb.lvds_bg_reg);
+	}
+
+	for (i = 0; i < 2; i++) {
+		if (ldb.fbi[i] != NULL) {
+			if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG") == 0)
+				ipu_di = 0;
+			else if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG - DI1")
+				 == 0)
+				ipu_di = 1;
+			else {
+				dev_err(g_ldb_dev, "Wrong framebuffer\n");
+				goto err0;
+			}
+
+			var[ipu_di] = &ldb.fbi[i]->var;
+			if (ldb.fbi[i]->fbops->fb_ioctl) {
+				old_fs = get_fs();
+				set_fs(KERNEL_DS);
+				ldb.fbi[i]->fbops->fb_ioctl(ldb.fbi[i],
+						MXCFB_GET_DIFMT,
+						(unsigned long)&(ipu_di_pix_fmt[ipu_di]));
+				set_fs(old_fs);
+			} else {
+				dev_err(g_ldb_dev, "Can't get framebuffer "
+						   "information\n");
+				goto err0;
+			}
+
+			if (!valid_mode(ipu_di_pix_fmt[ipu_di])) {
+				dev_err(g_ldb_dev, "Unsupport pixel format "
+						   "for ldb input\n");
+				goto err0;
+			}
+
+			reg = __raw_readl(ldb.control_reg);
+			if (var[ipu_di]->sync & FB_SYNC_VERT_HIGH_ACT) {
+				if (ipu_di == 0)
+					__raw_writel((reg &
+						~LDB_DI0_VS_POL_MASK) |
+						LDB_DI0_VS_POL_ACT_HIGH,
+						ldb.control_reg);
+				else
+					__raw_writel((reg &
+						~LDB_DI1_VS_POL_MASK) |
+						LDB_DI1_VS_POL_ACT_HIGH,
+						ldb.control_reg);
+			} else {
+				if (ipu_di == 0)
+					__raw_writel((reg &
+						~LDB_DI0_VS_POL_MASK) |
+						LDB_DI0_VS_POL_ACT_LOW,
+						ldb.control_reg);
+				else
+					__raw_writel((reg &
+						~LDB_DI1_VS_POL_MASK) |
+						LDB_DI1_VS_POL_ACT_LOW,
+						ldb.control_reg);
+			}
+
+			/* TODO:Set the correct pll4 rate for all situations */
+			if (ipu_di == 1) {
+				ldb.ldb_di_clk[1] =
+					clk_get(&pdev->dev, "ldb_di1_clk");
+				ldb_clk_parent =
+					clk_get_parent(ldb.ldb_di_clk[1]);
+				clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+				clk_put(ldb.ldb_di_clk[1]);
+			} else {
+				ldb.ldb_di_clk[0] =
+					clk_get(&pdev->dev, "ldb_di0_clk");
+				ldb_clk_parent =
+					clk_get_parent(ldb.ldb_di_clk[0]);
+				clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+				clk_put(ldb.ldb_di_clk[0]);
+			}
+		}
+	}
+
+	reg = __raw_readl(ldb.control_reg);
+	if (ldb.bgref_rmode == LDB_EXT_REF)
+		__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+			      LDB_BGREF_RMODE_EXT, ldb.control_reg);
+	else
+		__raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+			      LDB_BGREF_RMODE_INT, ldb.control_reg);
+
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+		if (var[0] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+			      LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		break;
+	case LDB_SIN_DI1:
+		if (var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_SEP:
+		if (var[0] == NULL || var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffers on DI0/1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+				      LDB_DATA_WIDTH_CH0_18,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[0]);
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI0 |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		if (var[0] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_24 |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_18 |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_mode_opt == LDB_SPL_DI0)
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		if (ldb.chan_mode_opt == LDB_DUL_DI0) {
+			clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+		} else {
+			clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+			clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+		}
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI0 |
+			      LDB_CH1_MODE_EN_TO_DI0, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		if (var[1] == NULL) {
+			dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+			break;
+		}
+
+		reg = __raw_readl(ldb.control_reg);
+		if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_24 |
+				      LDB_DATA_WIDTH_CH1_24,
+				      ldb.control_reg);
+		else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+			__raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+					      LDB_DATA_WIDTH_CH1_MASK)) |
+				      LDB_DATA_WIDTH_CH0_18 |
+				      LDB_DATA_WIDTH_CH1_18,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+				      LDB_BIT_MAP_CH0_JEIDA,
+				      ldb.control_reg);
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_SPWG,
+				      ldb.control_reg);
+		else
+			__raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+				      LDB_BIT_MAP_CH1_JEIDA,
+				      ldb.control_reg);
+
+		reg = __raw_readl(ldb.control_reg);
+		if (ldb.chan_mode_opt == LDB_SPL_DI1)
+			__raw_writel(reg | LDB_SPLIT_MODE_EN,
+				      ldb.control_reg);
+
+		ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+		ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+		if (ldb.chan_mode_opt == LDB_DUL_DI1) {
+			clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+		} else {
+			clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+			clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+		}
+		clk_enable(ldb.ldb_di_clk[0]);
+		clk_enable(ldb.ldb_di_clk[1]);
+		clk_put(ldb.ldb_di_clk[0]);
+		clk_put(ldb.ldb_di_clk[1]);
+
+		reg = __raw_readl(ldb.control_reg);
+		__raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+				      LDB_CH1_MODE_MASK)) |
+			      LDB_CH0_MODE_EN_TO_DI1 |
+			      LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+		ldb.ch_working[0] = true;
+		ldb.ch_working[1] = true;
+		break;
+	default:
+		break;
+	}
+
+	mxc_ldb_major = register_chrdev(0, "mxc_ldb", &mxc_ldb_fops);
+	if (mxc_ldb_major < 0) {
+		dev_err(g_ldb_dev, "Unable to register MXC LDB as a char "
+				   "device\n");
+		ret = mxc_ldb_major;
+		goto err0;
+	}
+
+	mxc_ldb_class = class_create(THIS_MODULE, "mxc_ldb");
+	if (IS_ERR(mxc_ldb_class)) {
+		dev_err(g_ldb_dev, "Unable to create class for MXC LDB\n");
+		ret = PTR_ERR(mxc_ldb_class);
+		goto err1;
+	}
+
+	temp = device_create(mxc_ldb_class, NULL, MKDEV(mxc_ldb_major, 0),
+			NULL, "mxc_ldb");
+	if (IS_ERR(temp)) {
+		dev_err(g_ldb_dev, "Unable to create class device for "
+				   "MXC LDB\n");
+		ret = PTR_ERR(temp);
+		goto err2;
+	}
+
+	ret = fb_register_client(&nb);
+	if (ret < 0)
+		goto err2;
+
+	if (primary && ldb.fbi[0] != NULL) {
+		acquire_console_sem();
+		fb_blank(ldb.fbi[0], FB_BLANK_UNBLANK);
+		release_console_sem();
+		fb_show_logo(ldb.fbi[0], 0);
+	}
+
+	return ret;
+err2:
+	class_destroy(mxc_ldb_class);
+err1:
+	unregister_chrdev(mxc_ldb_major, "mxc_ldb");
+err0:
+	iounmap(ldb_reg);
+	return ret;
+}
+
+static int ldb_remove(struct platform_device *pdev)
+{
+	int i;
+
+	__raw_writel(0, ldb.control_reg);
+
+	for (i = 0; i < 2; i++) {
+		if (ldb.ch_working[i]) {
+			ldb.ldb_di_clk[i] = clk_get(NULL,
+					    i ? "ldb_di1_clk" : "ldb_di0_clk");
+			clk_disable(ldb.ldb_di_clk[i]);
+			clk_put(ldb.ldb_di_clk[i]);
+			ldb.ch_working[i] = false;
+		}
+	}
+
+	fb_unregister_client(&nb);
+	return 0;
+}
+
+static int ldb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		ldb_disable(0);
+		break;
+	case LDB_SIN_DI1:
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		ldb_disable(1);
+		break;
+	case LDB_SEP:
+		ldb_disable(0);
+		ldb_disable(1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int ldb_resume(struct platform_device *pdev)
+{
+	switch (ldb.chan_mode_opt) {
+	case LDB_SIN_DI0:
+	case LDB_DUL_DI0:
+	case LDB_SPL_DI0:
+		ldb_enable(0);
+		break;
+	case LDB_SIN_DI1:
+	case LDB_DUL_DI1:
+	case LDB_SPL_DI1:
+		ldb_enable(1);
+		break;
+	case LDB_SEP:
+		ldb_enable(0);
+		ldb_enable(1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static struct platform_driver mxcldb_driver = {
+	.driver = {
+		   .name = "mxc_ldb",
+		   },
+	.probe = ldb_probe,
+	.remove = ldb_remove,
+	.suspend = ldb_suspend,
+	.resume = ldb_resume,
+};
+
+/*
+ * Parse user specified options (`lvds=')
+ * example:
+ * lvds=single(separate, dual or split),(di=0 or di=1),
+ *	ch0_map=SPWG or JEIDA,ch1_map=SPWG or JEIDA
+ *
+ */
+static int __init ldb_setup(char *options)
+{
+	g_enable_ldb = true;
+
+	if (!strlen(options))
+		return 1;
+	else if (!strsep(&options, "="))
+		return 1;
+
+	if (!strncmp(options, "single", 6)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=0", 4))
+			g_chan_mode_opt = LDB_SIN_DI0;
+		else
+			g_chan_mode_opt = LDB_SIN_DI1;
+	} else if (!strncmp(options, "separate", 8)) {
+		g_chan_mode_opt = LDB_SEP;
+	} else if (!strncmp(options, "dual", 4)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=", 3)) {
+			if (simple_strtoul(options + 3, NULL, 0) == 0)
+				g_chan_mode_opt = LDB_DUL_DI0;
+			else
+				g_chan_mode_opt = LDB_DUL_DI1;
+		}
+	} else if (!strncmp(options, "split", 5)) {
+		strsep(&options, ",");
+		if (!strncmp(options, "di=", 3)) {
+			if (simple_strtoul(options + 3, NULL, 0) == 0)
+				g_chan_mode_opt = LDB_SPL_DI0;
+			else
+				g_chan_mode_opt = LDB_SPL_DI1;
+		}
+	} else
+		return 1;
+
+	if ((strsep(&options, ",") != NULL) &&
+	    !strncmp(options, "ch0_map=", 8)) {
+		if (!strncmp(options + 8, "SPWG", 4))
+			g_chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+		else
+			g_chan_bit_map[0] = LDB_BIT_MAP_JEIDA;
+	}
+
+	if (!(g_chan_mode_opt == LDB_SIN_DI0 ||
+	      g_chan_mode_opt == LDB_SIN_DI1) &&
+	    (strsep(&options, ",") != NULL) &&
+	    !strncmp(options, "ch1_map=", 8)) {
+		if (!strncmp(options + 8, "SPWG", 4))
+			g_chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+		else
+			g_chan_bit_map[1] = LDB_BIT_MAP_JEIDA;
+	}
+
+	g_boot_cmd = true;
+
+	return 1;
+}
+__setup("ldb", ldb_setup);
+
+static int __init ldb_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&mxcldb_driver);
+	return 0;
+}
+
+static void __exit ldb_uninit(void)
+{
+	platform_driver_unregister(&mxcldb_driver);
+}
+
+module_init(ldb_init);
+module_exit(ldb_uninit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC LDB driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mx2fb.c b/drivers/video/mxc/mx2fb.c
new file mode 100644
index 000000000000..4921f96be00a
--- /dev/null
+++ b/drivers/video/mxc/mx2fb.c
@@ -0,0 +1,1347 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer_MX27 Framebuffer Driver for MX27.
+ */
+
+/*!
+ * @file mx2fb.c
+ *
+ * @brief Frame buffer driver for MX27 ADS.
+ *
+ * @ingroup Framebuffer_MX27
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/mxcfb.h>
+#include <linux/uaccess.h>
+#include <mach/hardware.h>
+
+#include "mx2fb.h"
+
+#define MX2FB_TYPE_BG          0
+#define MX2FB_TYPE_GW          1
+
+extern void gpio_lcdc_active(void);
+extern void gpio_lcdc_inactive(void);
+extern void board_power_lcd(int on);
+
+static char *fb_mode = 0;
+static int fb_enabled = 0;
+static unsigned long default_bpp = 16;
+static ATOMIC_NOTIFIER_HEAD(mx2fb_notifier_list);
+static struct clk *lcdc_clk;
+/*!
+ * @brief Structure containing the MX2 specific framebuffer information.
+ */
+struct mx2fb_info {
+	int type;
+	char *id;
+	int registered;
+	int blank;
+	unsigned long pseudo_palette[16];
+};
+
+/* Framebuffer APIs */
+static int mx2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
+static int mx2fb_set_par(struct fb_info *info);
+static int mx2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			   unsigned blue, unsigned transp,
+			   struct fb_info *info);
+static int mx2fb_pan_display(struct fb_var_screeninfo *var,
+			     struct fb_info *info);
+static int mx2fb_blank(int blank_mode, struct fb_info *info);
+static int mx2fb_ioctl(struct fb_info *info, unsigned int cmd,
+		       unsigned long arg);
+
+/* Driver entries */
+int __init mx2fb_init(void);
+void __exit mx2fb_exit(void);
+#ifndef MODULE
+static int __init mx2fb_setup(char *);
+#endif
+
+/* Internal functions */
+static int __init _init_fbinfo(struct fb_info *info,
+			       struct platform_device *pdev);
+static int __init _install_fb(struct fb_info *info,
+			      struct platform_device *pdev);
+static void __exit _uninstall_fb(struct fb_info *info);
+static int _map_video_memory(struct fb_info *info);
+static void _unmap_video_memory(struct fb_info *info);
+static void _set_fix(struct fb_info *info);
+static void _enable_lcdc(struct fb_info *info);
+static void _disable_lcdc(struct fb_info *info);
+static void _enable_graphic_window(struct fb_info *info);
+static void _disable_graphic_window(struct fb_info *info);
+static void _update_lcdc(struct fb_info *info);
+static void _request_irq(void);
+static void _free_irq(void);
+
+#ifdef CONFIG_PM
+static int mx2fb_suspend(struct platform_device *pdev, pm_message_t state);
+static int mx2fb_resume(struct platform_device *pdev);
+#else
+#define mx2fb_suspend	0
+#define mx2fb_resume	0
+#endif
+
+static int mx2fb_probe(struct platform_device *pdev);
+
+#ifdef CONFIG_FB_MXC_TVOUT
+#include <linux/video_encoder.h>
+/*
+ * FIXME: VGA mode is not defined by video_encoder.h
+ * while FS453 supports VGA output.
+ */
+#ifndef VIDEO_ENCODER_VGA
+#define VIDEO_ENCODER_VGA	32
+#endif
+
+#define MODE_PAL		"TV-PAL"
+#define MODE_NTSC		"TV-NTSC"
+#define MODE_VGA		"TV-VGA"
+
+extern int fs453_ioctl(unsigned int cmd, void *arg);
+#endif
+
+struct mx2fb_info mx2fbi_bg = {
+	.type = MX2FB_TYPE_BG,
+	.id = "DISP0 BG",
+	.registered = 0,
+};
+
+static struct mx2fb_info mx2fbi_gw = {
+	.type = MX2FB_TYPE_GW,
+	.id = "DISP0 FG",
+	.registered = 0,
+};
+
+/*! Current graphic window information */
+static struct fb_gwinfo g_gwinfo = {
+	.enabled = 0,
+	.alpha_value = 255,
+	.ck_enabled = 0,
+	.ck_red = 0,
+	.ck_green = 0,
+	.ck_blue = 0,
+	.xpos = 0,
+	.ypos = 0,
+};
+
+/*!
+ * @brief Framebuffer information structures.
+ * There are up to 3 framebuffers: background, TVout, and graphic window.
+ * If graphic window is configured, it must be the last framebuffer.
+ */
+static struct fb_info mx2fb_info[] = {
+	{.par = &mx2fbi_bg},
+	{.par = &mx2fbi_gw},
+};
+
+/*!
+ * @brief This structure contains pointers to the power management
+ * callback functions.
+ */
+static struct platform_driver mx2fb_driver = {
+	.driver = {
+		   .name = "mxc_sdc_fb",
+		   .owner = THIS_MODULE,
+		   .bus = &platform_bus_type,
+		   },
+	.probe = mx2fb_probe,
+	.suspend = mx2fb_suspend,
+	.resume = mx2fb_resume,
+};
+
+/*!
+ * @brief Framebuffer file operations
+ */
+static struct fb_ops mx2fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mx2fb_check_var,
+	.fb_set_par = mx2fb_set_par,
+	.fb_setcolreg = mx2fb_setcolreg,
+	.fb_blank = mx2fb_blank,
+	.fb_pan_display = mx2fb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	//.fb_cursor = soft_cursor,
+	.fb_ioctl = mx2fb_ioctl,
+};
+
+/*!
+ * @brief Validates a var passed in.
+ *
+ * @param var	Frame buffer variable screen structure
+ * @param info	Frame buffer structure that represents a single frame buffer
+ *
+ * @return	Negative errno on error, or zero on success.
+ *
+ * Checks to see if the hardware supports the state requested by var passed
+ * in. This function does not alter the hardware state! If the var passed in
+ * is slightly off by what the hardware can support then we alter the var
+ * PASSED in to what we can do. If the hardware doesn't support mode change
+ * a -EINVAL will be returned by the upper layers.
+ *
+ */
+static int mx2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	unsigned long htotal, vtotal;
+
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if (var->xoffset < 0)
+		var->xoffset = 0;
+
+	if (var->yoffset < 0)
+		var->yoffset = 0;
+
+	if (var->xoffset + info->var.xres > info->var.xres_virtual)
+		var->xoffset = info->var.xres_virtual - info->var.xres;
+
+	if (var->yoffset + info->var.yres > info->var.yres_virtual)
+		var->yoffset = info->var.yres_virtual - info->var.yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16)) {
+		var->bits_per_pixel = default_bpp;
+	}
+
+	switch (var->bits_per_pixel) {
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	if (var->pixclock < 1000) {
+		htotal = var->xres + var->right_margin + var->hsync_len +
+		    var->left_margin;
+		vtotal = var->yres + var->lower_margin + var->vsync_len +
+		    var->upper_margin;
+		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+		var->pixclock = KHZ2PICOS(var->pixclock);
+		dev_dbg(info->device,
+			"pixclock set for 60Hz refresh = %u ps\n",
+			var->pixclock);
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	/* Copy nonstd field to/from sync for fbset usage */
+	var->sync |= var->nonstd;
+	var->nonstd |= var->sync;
+
+	return 0;
+}
+
+/*!
+ * @brief Alters the hardware state.
+ *
+ * @param info	Frame buffer structure that represents a single frame buffer
+ *
+ * @return Zero on success others on failure
+ *
+ * Using the fb_var_screeninfo in fb_info we set the resolution of this
+ * particular framebuffer. This function alters the fb_fix_screeninfo stored
+ * in fb_info. It doesn't not alter var in fb_info since we are using that
+ * data. This means we depend on the data in var inside fb_info to be
+ * supported by the hardware. mx2fb_check_var is always called before
+ * mx2fb_set_par to ensure this.
+ */
+static int mx2fb_set_par(struct fb_info *info)
+{
+	unsigned long len;
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	_set_fix(info);
+
+	len = info->var.yres_virtual * info->fix.line_length;
+	if (len > info->fix.smem_len) {
+		if (info->fix.smem_start)
+			_unmap_video_memory(info);
+
+		/* Memory allocation for framebuffer */
+		if (_map_video_memory(info)) {
+			dev_err(info->device, "Unable to allocate fb memory\n");
+			return -ENOMEM;
+		}
+	}
+
+	_update_lcdc(info);
+	if (info->fbops->fb_blank)
+		info->fbops->fb_blank(mx2fbi->blank, info);
+
+	return 0;
+}
+
+/*!
+ * @brief Sets a color register.
+ *
+ * @param regno		Which register in the CLUT we are programming
+ * @param red		The red value which can be up to 16 bits wide
+ * @param green		The green value which can be up to 16 bits wide
+ * @param blue		The blue value which can be up to 16 bits wide.
+ * @param transp	If supported the alpha value which can be up to
+ *                      16 bits wide.
+ * @param info		Frame buffer info structure
+ *
+ * @return		Negative errno on error, or zero on success.
+ *
+ * Set a single color register. The values supplied have a 16 bit magnitude
+ * which needs to be scaled in this function for the hardware. Things to take
+ * into consideration are how many color registers, if any, are supported with
+ * the current color visual. With truecolor mode no color palettes are
+ * supported. Here a psuedo palette is created which we store the value in
+ * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
+ * color palette.
+ */
+static int mx2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			   unsigned blue, unsigned transp, struct fb_info *info)
+{
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (info->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = info->pseudo_palette;
+			u32 v;
+
+#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
+			red = CNVT_TOHW(red, info->var.red.length);
+			green = CNVT_TOHW(green, info->var.green.length);
+			blue = CNVT_TOHW(blue, info->var.blue.length);
+			transp = CNVT_TOHW(transp, info->var.transp.length);
+#undef CNVT_TOHW
+
+			v = (red << info->var.red.offset) |
+			    (green << info->var.green.offset) |
+			    (blue << info->var.blue.offset) |
+			    (transp << info->var.transp.offset);
+
+			pal[regno] = v;
+			ret = 0;
+		}
+		break;
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * @brief Pans the display.
+ *
+ * @param var	Frame buffer variable screen structure
+ * @param info	Frame buffer structure that represents a single frame buffer
+ *
+ * @return	Negative errno on error, or zero on success.
+ *
+ * Pan (or wrap, depending on the `vmode' field) the display using the
+ * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
+ * don't fit, return -EINVAL.
+ */
+static int mx2fb_pan_display(struct fb_var_screeninfo *var,
+			     struct fb_info *info)
+{
+	if ((info->var.xoffset == var->xoffset) &&
+	    (info->var.yoffset == var->yoffset)) {
+		return 0;	/* No change, do nothing */
+	}
+
+	if (var->xoffset < 0 || var->yoffset < 0
+	    || var->xoffset + info->var.xres > info->var.xres_virtual
+	    || var->yoffset + info->var.yres > info->var.yres_virtual)
+		return -EINVAL;
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	_update_lcdc(info);
+
+	if (var->vmode & FB_VMODE_YWRAP) {
+		info->var.vmode |= FB_VMODE_YWRAP;
+	} else {
+		info->var.vmode &= ~FB_VMODE_YWRAP;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Blanks the display.
+ *
+ * @param blank_mode	The blank mode we want.
+ * @param info		Frame buffer structure that represents a single frame buffer
+ *
+ * @return		Negative errno on error, or zero on success.
+ *
+ * Blank the screen if blank_mode != 0, else unblank. Return 0 if blanking
+ * succeeded, != 0 if un-/blanking failed.
+ * blank_mode == 2: suspend vsync
+ * blank_mode == 3: suspend hsync
+ * blank_mode == 4: powerdown
+ */
+static int mx2fb_blank(int blank_mode, struct fb_info *info)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	dev_dbg(info->device, "blank mode = %d\n", blank_mode);
+
+	mx2fbi->blank = blank_mode;
+
+	switch (blank_mode) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		_disable_lcdc(info);
+		break;
+	case FB_BLANK_UNBLANK:
+		_enable_lcdc(info);
+		break;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Ioctl function to support customized ioctl operations.
+ *
+ * @param info	Framebuffer structure that represents a single frame buffer
+ * @param cmd	The command number
+ * @param arg	Argument which depends on cmd
+ *
+ * @return	Negative errno on error, or zero on success.
+ */
+static int mx2fb_ioctl(struct fb_info *info, unsigned int cmd,
+		       unsigned long arg)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+	struct mx2fb_gbl_alpha ga;
+	struct mx2fb_color_key ck;
+
+	switch (cmd) {
+	case MX2FB_SET_GBL_ALPHA:
+		if (mx2fbi->type != MX2FB_TYPE_GW)
+			return -ENODEV;
+
+		if (!arg)
+			return -EINVAL;
+
+		/* set graphic window information */
+		if (copy_from_user((void *)&ga, (void *)arg, sizeof(ga)))
+			return -EFAULT;
+
+		g_gwinfo.alpha_value = ga.alpha;
+
+		if (g_gwinfo.enabled)
+			_enable_graphic_window(info);
+		else
+			_disable_graphic_window(info);
+		break;
+	case MX2FB_SET_CLR_KEY:
+		if (mx2fbi->type != MX2FB_TYPE_GW)
+			return -ENODEV;
+
+		if (!arg)
+			return -EINVAL;
+
+		/* set graphic window information */
+		if (copy_from_user((void *)&ck, (void *)arg, sizeof(ck)))
+			return -EFAULT;
+
+		g_gwinfo.ck_enabled = ck.enable;
+		g_gwinfo.ck_red = (ck.color_key & 0x003F0000) >> 16;
+		g_gwinfo.ck_green = (ck.color_key & 0x00003F00) >> 8;
+		g_gwinfo.ck_blue = ck.color_key & 0x0000003F;
+
+		if (g_gwinfo.enabled)
+			_enable_graphic_window(info);
+		else
+			_disable_graphic_window(info);
+		break;
+	case FBIOGET_GWINFO:
+		if (mx2fbi->type != MX2FB_TYPE_GW)
+			return -ENODEV;
+
+		if (!arg)
+			return -EINVAL;
+
+		/* get graphic window information */
+		if (copy_to_user((void *)arg, (void *)&g_gwinfo,
+				 sizeof(g_gwinfo)))
+			return -EFAULT;
+		break;
+	case FBIOPUT_GWINFO:
+		if (mx2fbi->type != MX2FB_TYPE_GW)
+			return -ENODEV;
+
+		if (!arg)
+			return -EINVAL;
+
+		/* set graphic window information */
+		if (copy_from_user((void *)&g_gwinfo, (void *)arg,
+				   sizeof(g_gwinfo)))
+			return -EFAULT;
+
+		if (g_gwinfo.enabled)
+			_enable_graphic_window(info);
+		else
+			_disable_graphic_window(info);
+		break;
+#ifdef CONFIG_FB_MXC_TVOUT
+	case ENCODER_GET_CAPABILITIES:{
+			int ret;
+			struct video_encoder_capability cap;
+
+			if (mx2fbi->type != MX2FB_TYPE_BG)
+				return -ENODEV;
+
+			ret = fs453_ioctl(cmd, &cap);
+			if (ret)
+				return ret;
+
+			if (copy_to_user((void *)arg, &cap, sizeof(cap)))
+				return -EFAULT;
+			break;
+		}
+	case ENCODER_SET_NORM:{
+			int ret;
+			unsigned long mode;
+			char *smode;
+			struct fb_var_screeninfo var;
+
+			if (mx2fbi->type != MX2FB_TYPE_BG)
+				return -ENODEV;
+
+			if (copy_from_user(&mode, (void *)arg, sizeof(mode)))
+				return -EFAULT;
+			if ((ret = fs453_ioctl(cmd, &mode)))
+				return ret;
+
+			if (mode == VIDEO_ENCODER_PAL)
+				smode = MODE_PAL;
+			else if (mode == VIDEO_ENCODER_NTSC)
+				smode = MODE_NTSC;
+			else
+				smode = MODE_VGA;
+
+			var = info->var;
+			var.nonstd = 0;
+			ret = fb_find_mode(&var, info, smode, mxcfb_modedb,
+					   mxcfb_modedb_sz, NULL, default_bpp);
+			if ((ret != 1) && (ret != 2))	/* specified mode not found */
+				return -ENODEV;
+
+			info->var = var;
+			fb_mode = smode;
+			return mx2fb_set_par(info);
+		}
+	case ENCODER_SET_INPUT:
+	case ENCODER_SET_OUTPUT:
+	case ENCODER_ENABLE_OUTPUT:{
+			unsigned long varg;
+
+			if (mx2fbi->type != MX2FB_TYPE_BG)
+				return -ENODEV;
+
+			if (copy_from_user(&varg, (void *)arg, sizeof(varg)))
+				return -EFAULT;
+			return fs453_ioctl(cmd, &varg);
+		}
+#endif
+	default:
+		dev_dbg(info->device, "Unknown ioctl command (0x%08X)\n", cmd);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*!
+ * @brief Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param info	framebuffer information pointer
+ * @return	Negative errno on error, or zero on success.
+ */
+static void _set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	strncpy(fix->id, mx2fbi->id, strlen(mx2fbi->id));
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+}
+
+/*!
+ * @brief Initialize framebuffer information structure.
+ *
+ * @param info	framebuffer information pointer
+ * @param pdev	pointer to struct device
+ * @return	Negative errno on error, or zero on success.
+ */
+static int __init _init_fbinfo(struct fb_info *info,
+			       struct platform_device *pdev)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	info->device = &pdev->dev;
+	info->var.activate = FB_ACTIVATE_NOW;
+	info->fbops = &mx2fb_ops;
+	info->flags = FBINFO_FLAG_DEFAULT;
+	info->pseudo_palette = &mx2fbi->pseudo_palette;
+
+	/* Allocate colormap */
+	fb_alloc_cmap(&info->cmap, 16, 0);
+
+	return 0;
+}
+
+/*!
+ * @brief Install framebuffer into the system.
+ *
+ * @param info	framebuffer information pointer
+ * @param pdev  pointer to struct device
+ * @return	Negative errno on error, or zero on success.
+ */
+static int __init _install_fb(struct fb_info *info,
+			      struct platform_device *pdev)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	if (_init_fbinfo(info, pdev))
+		return -EINVAL;
+
+	if (fb_mode == 0)
+		fb_mode = pdev->dev.platform_data;
+
+	if (!fb_find_mode(&info->var, info, fb_mode, mxcfb_modedb,
+			  mxcfb_modedb_sz, NULL, default_bpp)) {
+		fb_dealloc_cmap(&info->cmap);
+		return -EBUSY;
+	}
+
+	/* Default Y virtual size is 2x panel size */
+	/* info->var.yres_virtual = info->var.yres << 1; */
+
+	if (mx2fbi->type == MX2FB_TYPE_GW)
+		mx2fbi->blank = FB_BLANK_NORMAL;
+	else
+		mx2fbi->blank = FB_BLANK_UNBLANK;
+
+	if (mx2fb_set_par(info)) {
+		fb_dealloc_cmap(&info->cmap);
+		return -EINVAL;
+	}
+
+	if (register_framebuffer(info) < 0) {
+		_unmap_video_memory(info);
+		fb_dealloc_cmap(&info->cmap);
+		return -EINVAL;
+	}
+
+	mx2fbi->registered = 1;
+	dev_info(info->device, "fb%d: %s fb device registered successfully.\n",
+		 info->node, info->fix.id);
+
+	return 0;
+}
+
+/*!
+ * @brief Uninstall framebuffer from the system.
+ *
+ * @param info	framebuffer information pointer
+ */
+static void __exit _uninstall_fb(struct fb_info *info)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	if (!mx2fbi->registered)
+		return;
+
+	unregister_framebuffer(info);
+	_unmap_video_memory(info);
+	if (&info->cmap)
+		fb_dealloc_cmap(&info->cmap);
+
+	mx2fbi->registered = 0;
+}
+
+/*!
+ * @brief Allocate memory for framebuffer.
+ *
+ * @param info	framebuffer information pointer
+ * @return	Negative errno on error, or zero on success.
+ */
+static int _map_video_memory(struct fb_info *info)
+{
+	info->fix.smem_len = info->fix.line_length * info->var.yres_virtual;
+	info->screen_base = dma_alloc_coherent(0,
+					       info->fix.smem_len,
+					       (dma_addr_t *) & info->fix.
+					       smem_start,
+					       GFP_DMA | GFP_KERNEL);
+
+	if (info->screen_base == 0) {
+		dev_err(info->device, "Unable to allocate fb memory\n");
+		return -EBUSY;
+	}
+	dev_dbg(info->device, "Allocated fb @ paddr=0x%08lX, size=%d.\n",
+		info->fix.smem_start, info->fix.smem_len);
+
+	info->screen_size = info->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)info->screen_base, 0, info->fix.smem_len);
+
+	return 0;
+}
+
+/*!
+ * @brief Release memory for framebuffer.
+ * @param info	framebuffer information pointer
+ */
+static void _unmap_video_memory(struct fb_info *info)
+{
+	dma_free_coherent(0, info->fix.smem_len, info->screen_base,
+			  (dma_addr_t) info->fix.smem_start);
+
+	info->screen_base = 0;
+	info->fix.smem_start = 0;
+	info->fix.smem_len = 0;
+}
+
+/*!
+ * @brief Enable LCD controller.
+ * @param info	framebuffer information pointer
+ */
+static void _enable_lcdc(struct fb_info *info)
+{
+	static int first_enable = 1;
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	/*
+	 * Graphic window can only be enabled while the HCLK to the LCDC
+	 * is disabled. Once enabled it can subsequently be disabled and
+	 * enabled without turning off the HCLK.
+	 * The graphic window is enabled and then disabled here. So next
+	 * time to enable graphic window the HCLK to LCDC does not need
+	 * to be disabled, and the flicker (due to disabling of HCLK to
+	 * LCDC) is avoided.
+	 */
+	if (first_enable) {
+		_enable_graphic_window(info);
+		_disable_graphic_window(info);
+		first_enable = 0;
+	}
+
+	if (mx2fbi->type == MX2FB_TYPE_GW)
+		_enable_graphic_window(info);
+	else if (!fb_enabled) {
+		clk_enable(lcdc_clk);
+		gpio_lcdc_active();
+		board_power_lcd(1);
+		fb_enabled++;
+#ifdef CONFIG_FB_MXC_TVOUT
+		if (fb_mode) {
+			unsigned long mode = 0;
+
+			if (strcmp(fb_mode, MODE_VGA) == 0)
+				mode = VIDEO_ENCODER_VGA;
+			else if (strcmp(fb_mode, MODE_NTSC) == 0)
+				mode = VIDEO_ENCODER_NTSC;
+			else if (strcmp(fb_mode, MODE_PAL) == 0)
+				mode = VIDEO_ENCODER_PAL;
+			if (mode)
+				fs453_ioctl(ENCODER_SET_NORM, &mode);
+		}
+#endif
+	}
+}
+
+/*!
+ * @brief Disable LCD controller.
+ * @param info	framebuffer information pointer
+ */
+static void _disable_lcdc(struct fb_info *info)
+{
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	if (mx2fbi->type == MX2FB_TYPE_GW)
+		_disable_graphic_window(info);
+	else {
+		if (fb_enabled) {
+			gpio_lcdc_inactive();
+			board_power_lcd(0);
+			clk_disable(lcdc_clk);
+			fb_enabled = 0;
+		}
+#ifdef CONFIG_FB_MXC_TVOUT
+		if (fb_mode) {
+			int enable = 0;
+
+			if ((strcmp(fb_mode, MODE_VGA) == 0)
+			    || (strcmp(fb_mode, MODE_NTSC) == 0)
+			    || (strcmp(fb_mode, MODE_PAL) == 0))
+				fs453_ioctl(ENCODER_ENABLE_OUTPUT, &enable);
+		}
+#endif
+	}
+}
+
+/*!
+ * @brief Enable graphic window.
+ * @param info	framebuffer information pointer
+ */
+static void _enable_graphic_window(struct fb_info *info)
+{
+	struct fb_var_screeninfo *var = &info->var;
+
+	g_gwinfo.enabled = 1;
+
+	g_gwinfo.base = (var->yoffset * var->xres_virtual + var->xoffset);
+	g_gwinfo.base *= (var->bits_per_pixel) / 8;
+	g_gwinfo.base += info->fix.smem_start;
+
+	g_gwinfo.xres = var->xres;
+	g_gwinfo.yres = var->yres;
+	g_gwinfo.xres_virtual = var->xres_virtual;
+
+	mx2_gw_set(&g_gwinfo);
+}
+
+/*!
+ * @brief Disable graphic window.
+ * @param info	framebuffer information pointer
+ */
+static void _disable_graphic_window(struct fb_info *info)
+{
+	unsigned long i = 0;
+
+	g_gwinfo.enabled = 0;
+
+	/*
+	 * Set alpha value to zero and reduce gw size, otherwise the graphic
+	 * window will not be able to be enabled again.
+	 */
+	__raw_writel(__raw_readl(LCDC_REG(LCDC_LGWCR)) & 0x00FFFFFF,
+		     LCDC_REG(LCDC_LGWCR));
+	__raw_writel(((16 >> 4) << 20) + 16, LCDC_REG(LCDC_LGWSR));
+	while (i < 1000)
+		i++;
+
+	/* Now disable graphic window */
+	__raw_writel(__raw_readl(LCDC_REG(LCDC_LGWCR)) & ~0x00400000,
+		     LCDC_REG(LCDC_LGWCR));
+
+	dev_dbg(info->device, "Graphic window disabled.\n");
+}
+
+/*!
+ * @brief Setup graphic window properties.
+ * @param gwinfo	graphic window information pointer
+ */
+void mx2_gw_set(struct fb_gwinfo *gwinfo)
+{
+	int width, height, xpos, ypos;
+	int width_bg, height_bg;
+	unsigned long lgwcr = 0x00400000;	/* Graphic window control register */
+
+	if (!gwinfo->enabled) {
+		_disable_graphic_window(0);
+		return;
+	}
+
+	/* Graphic window start address register */
+	__raw_writel(gwinfo->base, LCDC_REG(LCDC_LGWSAR));
+
+	/*
+	 * The graphic window width, height, x position and y position
+	 * must be synced up width the background window, otherwise there
+	 * may be flickering.
+	 */
+	width_bg = (__raw_readl(LCDC_REG(LCDC_LSR)) & 0x03F00000) >> 16;
+	height_bg = __raw_readl(LCDC_REG(LCDC_LSR)) & 0x000003FF;
+
+	width = (gwinfo->xres > width_bg) ? width_bg : gwinfo->xres;
+	height = (gwinfo->yres > height_bg) ? height_bg : gwinfo->yres;
+
+	xpos = gwinfo->xpos;
+	ypos = gwinfo->ypos;
+
+	if (xpos + width > width_bg)
+		xpos = width_bg - width;
+	if (ypos + height > height_bg)
+		ypos = height_bg - height;
+
+	/* Graphic window size register */
+	__raw_writel(((width >> 4) << 20) + height, LCDC_REG(LCDC_LGWSR));
+
+	/* Graphic window virtual page width register */
+	__raw_writel(gwinfo->xres_virtual >> 1, LCDC_REG(LCDC_LGWVPWR));
+
+	/* Graphic window position register */
+	__raw_writel(((xpos & 0x000003FF) << 16) | (ypos & 0x000003FF),
+		     LCDC_REG(LCDC_LGWPR));
+
+	/* Graphic window panning offset register */
+	__raw_writel(0, LCDC_REG(LCDC_LGWPOR));
+
+	/* Graphic window DMA control register */
+	if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0)
+		__raw_writel(0x00040060, LCDC_REG(LCDC_LGWDCR));
+	else
+		__raw_writel(0x00020010, LCDC_REG(LCDC_LGWDCR));
+
+	/* Graphic window control register */
+	lgwcr |= (gwinfo->alpha_value & 0x000000FF) << 24;
+	lgwcr |= gwinfo->ck_enabled ? 0x00800000 : 0;
+	lgwcr |= gwinfo->vs_reversed ? 0x00200000 : 0;
+
+	/*
+	 * Color keying value
+	 * Todo: assume always use RGB565
+	 */
+	lgwcr |= (gwinfo->ck_red & 0x0000003F) << 12;
+	lgwcr |= (gwinfo->ck_green & 0x0000003F) << 6;
+	lgwcr |= gwinfo->ck_blue & 0x0000003F;
+
+	__raw_writel(lgwcr, LCDC_REG(LCDC_LGWCR));
+
+	pr_debug("Graphic window enabled.\n");
+}
+
+/*!
+ * @brief Update LCDC registers
+ * @param info	framebuffer information pointer
+ */
+static void _update_lcdc(struct fb_info *info)
+{
+	unsigned long base;
+	unsigned long perclk, pcd, pcr;
+	struct fb_var_screeninfo *var = &info->var;
+	struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par;
+
+	if (mx2fbi->type == MX2FB_TYPE_GW) {
+		_enable_graphic_window(info);
+		return;
+	}
+
+	base = (var->yoffset * var->xres_virtual + var->xoffset);
+	base *= (var->bits_per_pixel) / 8;
+	base += info->fix.smem_start;
+
+	/* Screen start address register */
+	__raw_writel(base, LCDC_REG(LCDC_LSSAR));
+
+	/* Size register */
+	dev_dbg(info->device, "xres = %d, yres = %d\n",
+		info->var.xres, info->var.yres);
+	__raw_writel(((info->var.xres >> 4) << 20) + info->var.yres,
+		     LCDC_REG(LCDC_LSR));
+
+	/* Virtual page width register */
+	__raw_writel(info->var.xres_virtual >> 1, LCDC_REG(LCDC_LVPWR));
+
+	/* To setup LCDC pixel clock */
+	perclk = clk_round_rate(lcdc_clk, 134000000);
+	if (clk_set_rate(lcdc_clk, perclk)) {
+		printk(KERN_INFO "mx2fb: Unable to set clock to %lu\n", perclk);
+		perclk = clk_get_rate(lcdc_clk);
+	}
+
+	/* Calculate pixel clock divider, and round to the nearest integer */
+	pcd = (perclk * 8 / (PICOS2KHZ(var->pixclock) * 1000UL) + 4) / 8;
+	if (--pcd > 0x3F)
+		pcd = 0x3F;
+
+	/* Panel configuration register */
+	pcr = 0xFA008B80 | pcd;
+	pcr |= (var->sync & FB_SYNC_CLK_LAT_FALL) ? 0x00200000 : 0;
+	pcr |= (var->sync & FB_SYNC_DATA_INVERT) ? 0x01000000 : 0;
+	pcr |= (var->sync & FB_SYNC_SHARP_MODE) ? 0x00000040 : 0;
+	pcr |= (var->sync & FB_SYNC_OE_LOW_ACT) ? 0x00100000 : 0;
+	__raw_writel(pcr, LCDC_REG(LCDC_LPCR));
+
+	/* Horizontal and vertical configuration register */
+	__raw_writel(((var->hsync_len - 1) << 26)
+		     + ((var->right_margin - 1) << 8)
+		     + (var->left_margin - 3), LCDC_REG(LCDC_LHCR));
+	__raw_writel((var->vsync_len << 26)
+		     + (var->lower_margin << 8)
+		     + var->upper_margin, LCDC_REG(LCDC_LVCR));
+
+	/* Sharp configuration register */
+	__raw_writel(0x00120300, LCDC_REG(LCDC_LSCR));
+
+	/* Refresh mode control reigster */
+	__raw_writel(0x00000000, LCDC_REG(LCDC_LRMCR));
+
+	/* DMA control register */
+	if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0)
+		__raw_writel(0x00040060, LCDC_REG(LCDC_LDCR));
+	else
+		__raw_writel(0x00020010, LCDC_REG(LCDC_LDCR));
+}
+
+/*!
+ * @brief Set LCD brightness
+ * @param level	brightness level
+ */
+void mx2fb_set_brightness(uint8_t level)
+{
+	/* Set LCDC PWM contract control register */
+	__raw_writel(0x00A90300 | level, LCDC_REG(LCDC_LPCCR));
+}
+
+EXPORT_SYMBOL(mx2fb_set_brightness);
+
+/*
+ * @brief LCDC interrupt handler
+ */
+static irqreturn_t mx2fb_isr(int irq, void *dev_id)
+{
+	struct fb_event event;
+	unsigned long status = __raw_readl(LCDC_REG(LCDC_LISR));
+
+	if (status & MX2FB_INT_EOF) {
+		event.info = &mx2fb_info[0];
+		atomic_notifier_call_chain(&mx2fb_notifier_list,
+					   FB_EVENT_MXC_EOF, &event);
+	}
+
+	if (status & MX2FB_INT_GW_EOF) {
+		event.info = &mx2fb_info[1];
+		atomic_notifier_call_chain(&mx2fb_notifier_list,
+					   FB_EVENT_MXC_EOF, &event);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * @brief Config and request LCDC interrupt
+ */
+static void _request_irq(void)
+{
+	unsigned long status;
+	unsigned long flags;
+
+	/* Read to clear the status */
+	status = __raw_readl(LCDC_REG(LCDC_LISR));
+
+	if (request_irq(MXC_INT_LCDC, mx2fb_isr, 0, "LCDC", 0))
+		pr_info("Request LCDC IRQ failed.\n");
+	else {
+		spin_lock_irqsave(&mx2fb_notifier_list.lock, flags);
+
+		/* Enable interrupt in case client has registered */
+		if (mx2fb_notifier_list.head != NULL) {
+			unsigned long status;
+			unsigned long ints = MX2FB_INT_EOF;
+
+			ints |= MX2FB_INT_GW_EOF;
+
+			/* Read to clear the status */
+			status = __raw_readl(LCDC_REG(LCDC_LISR));
+
+			/* Configure interrupt condition for EOF */
+			__raw_writel(0x0, LCDC_REG(LCDC_LICR));
+
+			/* Enable EOF and graphic window EOF interrupt */
+			__raw_writel(ints, LCDC_REG(LCDC_LIER));
+		}
+
+		spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags);
+	}
+}
+
+/*!
+ * @brief Free LCDC interrupt handler
+ */
+static void _free_irq(void)
+{
+	/* Disable all LCDC interrupt */
+	__raw_writel(0x0, LCDC_REG(LCDC_LIER));
+
+	free_irq(MXC_INT_LCDC, 0);
+}
+
+/*!
+ * @brief Register a client notifier
+ * @param nb	notifier block to callback on events
+ */
+int mx2fb_register_client(struct notifier_block *nb)
+{
+	unsigned long flags;
+	int ret;
+
+	ret = atomic_notifier_chain_register(&mx2fb_notifier_list, nb);
+
+	spin_lock_irqsave(&mx2fb_notifier_list.lock, flags);
+
+	/* Enable interrupt in case client has registered */
+	if (mx2fb_notifier_list.head != NULL) {
+		unsigned long status;
+		unsigned long ints = MX2FB_INT_EOF;
+
+		ints |= MX2FB_INT_GW_EOF;
+
+		/* Read to clear the status */
+		status = __raw_readl(LCDC_REG(LCDC_LISR));
+
+		/* Configure interrupt condition for EOF */
+		__raw_writel(0x0, LCDC_REG(LCDC_LICR));
+
+		/* Enable EOF and graphic window EOF interrupt */
+		__raw_writel(ints, LCDC_REG(LCDC_LIER));
+	}
+
+	spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags);
+
+	return ret;
+}
+
+/*!
+ * @brief Unregister a client notifier
+ * @param nb	notifier block to callback on events
+ */
+int mx2fb_unregister_client(struct notifier_block *nb)
+{
+	unsigned long flags;
+	int ret;
+
+	ret = atomic_notifier_chain_unregister(&mx2fb_notifier_list, nb);
+
+	spin_lock_irqsave(&mx2fb_notifier_list.lock, flags);
+
+	/* Mask interrupt in case no client registered */
+	if (mx2fb_notifier_list.head == NULL)
+		__raw_writel(0x0, LCDC_REG(LCDC_LIER));
+
+	spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags);
+
+	return ret;
+}
+
+#ifdef CONFIG_PM
+/*
+ * Power management hooks. Note that we won't be called from IRQ context,
+ * unlike the blank functions above, so we may sleep.
+ */
+
+/*!
+ * @brief Suspends the framebuffer and blanks the screen.
+ * Power management support
+ */
+static int mx2fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	_disable_lcdc(&mx2fb_info[0]);
+
+	return 0;
+}
+
+/*!
+ * @brief Resumes the framebuffer and unblanks the screen.
+ * Power management support
+ */
+static int mx2fb_resume(struct platform_device *pdev)
+{
+	_enable_lcdc(&mx2fb_info[0]);
+
+	return 0;
+}
+
+#endif				/* CONFIG_PM */
+
+/*!
+ * @brief Probe routine for the framebuffer driver. It is called during the
+ *        driver binding process.
+ *
+ * @return Appropriate error code to the kernel common code
+ */
+static int mx2fb_probe(struct platform_device *pdev)
+{
+	int ret, i;
+
+	lcdc_clk = clk_get(&pdev->dev, "lcdc_clk");
+
+	for (i = 0; i < sizeof(mx2fb_info) / sizeof(struct fb_info); i++) {
+		if ((ret = _install_fb(&mx2fb_info[i], pdev))) {
+			dev_err(&pdev->dev,
+				"Failed to register framebuffer %d\n", i);
+			return ret;
+		}
+	}
+	_request_irq();
+
+	return 0;
+}
+
+/*!
+ * @brief Initialization
+ */
+int __init mx2fb_init(void)
+{
+	/*
+	 * For kernel boot options (in 'video=xxxfb:<options>' format)
+	 */
+#ifndef MODULE
+	{
+		char *option;
+
+		if (fb_get_options("mxcfb", &option))
+			return -ENODEV;
+		mx2fb_setup(option);
+	}
+#endif
+	return platform_driver_register(&mx2fb_driver);
+}
+
+/*!
+ * @brief Cleanup
+ */
+void __exit mx2fb_exit(void)
+{
+	int i;
+
+	_free_irq();
+	for (i = sizeof(mx2fb_info) / sizeof(struct fb_info); i > 0; i--)
+		_uninstall_fb(&mx2fb_info[i - 1]);
+
+	platform_driver_unregister(&mx2fb_driver);
+}
+
+#ifndef MODULE
+/*!
+ * @brief Setup
+ * Parse user specified options
+ * Example: video=mxcfb:240x320,bpp=16,Sharp-QVGA
+ */
+static int __init mx2fb_setup(char *options)
+{
+	char *opt;
+
+	if (!options || !*options)
+		return 0;
+
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+
+		if (!strncmp(opt, "bpp=", 4))
+			default_bpp = simple_strtoul(opt + 4, NULL, 0);
+		else
+			fb_mode = opt;
+	}
+
+	return 0;
+}
+#endif
+
+/* Modularization */
+module_init(mx2fb_init);
+module_exit(mx2fb_exit);
+
+EXPORT_SYMBOL(mx2_gw_set);
+EXPORT_SYMBOL(mx2fb_register_client);
+EXPORT_SYMBOL(mx2fb_unregister_client);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MX2 framebuffer driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mx2fb.h b/drivers/video/mxc/mx2fb.h
new file mode 100644
index 000000000000..ed20d78289ce
--- /dev/null
+++ b/drivers/video/mxc/mx2fb.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file    mx2fb.h
+ *
+ * @brief Header file for the MX27 Frame buffer
+ *
+ * @ingroup Framebuffer
+ */
+#ifndef __MX2FB_H__
+#define __MX2FB_H__
+
+/*! @brief MX27 LCDC graphic window information */
+struct fb_gwinfo {
+	/*! Non-zero if graphic window is enabled */
+	__u32 enabled;
+
+	/* The fields below are valid only when graphic window is enabled */
+
+	/*! Graphic window alpha value from 0 to 255 */
+	__u32 alpha_value;
+
+	/*! Non-zero if graphic window color keying is enabled. */
+	__u32 ck_enabled;
+
+	/*
+	 * The fields ck_red, ck_green and ck_blue are valid only when
+	 * graphic window and the color keying are enabled. They are the
+	 * color component of graphic window color keying.
+	 */
+
+	/*! Color keying red component */
+	__u32 ck_red;
+
+	/*! Color keying green component */
+	__u32 ck_green;
+
+	/*! Color keying blue component */
+	__u32 ck_blue;
+
+	/*! Graphic window x position */
+	__u32 xpos;
+
+	/*! Graphic window y position */
+	__u32 ypos;
+
+	/*! Non-zero if graphic window vertical scan in reverse direction. */
+	__u32 vs_reversed;
+
+	/*
+	 * The following fields are valid for FBIOGET_GWINFO and
+	 * mx2_gw_set(). FBIOPUT_GWINFO ignores these fields.
+	 */
+	__u32 base;		/* Graphic window start address */
+	__u32 xres;		/* Visible x resolution */
+	__u32 yres;		/* Visible y resolution */
+	__u32 xres_virtual;	/* Virtual x resolution */
+};
+
+/* 0x46E0-0x46FF are reserved for MX27 */
+#define FBIOGET_GWINFO		0x46E0	/*!< Get graphic window information */
+#define FBIOPUT_GWINFO		0x46E1	/*!< Set graphic window information */
+
+struct mx2fb_gbl_alpha {
+	int enable;
+	int alpha;
+};
+
+struct mx2fb_color_key {
+	int enable;
+	__u32 color_key;
+};
+
+#define MX2FB_SET_GBL_ALPHA	_IOW('M', 0, struct mx2fb_gbl_alpha)
+#define MX2FB_SET_CLR_KEY	_IOW('M', 1, struct mx2fb_color_key)
+#define MX2FB_WAIT_FOR_VSYNC	_IOW('F', 0x20, u_int32_t)
+
+#ifdef __KERNEL__
+
+/*
+ * LCDC register definitions
+ */
+#define LCDC_LSSAR		0x00
+#define LCDC_LSR		0x04
+#define LCDC_LVPWR		0x08
+#define LCDC_LCPR		0x0C
+#define LCDC_LCWHBR		0x10
+#define LCDC_LCCMR		0x14
+#define LCDC_LPCR		0x18
+#define LCDC_LHCR		0x1C
+#define LCDC_LVCR		0x20
+#define LCDC_LPOR		0x24
+#define LCDC_LSCR		0x28
+#define LCDC_LPCCR		0x2C
+#define LCDC_LDCR		0x30
+#define LCDC_LRMCR		0x34
+#define LCDC_LICR		0x38
+#define LCDC_LIER		0x3C
+#define LCDC_LISR		0x40
+#define LCDC_LGWSAR		0x50
+#define LCDC_LGWSR		0x54
+#define LCDC_LGWVPWR		0x58
+#define LCDC_LGWPOR		0x5C
+#define LCDC_LGWPR		0x60
+#define LCDC_LGWCR		0x64
+#define LCDC_LGWDCR		0x68
+#define LCDC_LAUSCR		0x80
+#define LCDC_LAUSCCR		0x84
+
+#define LCDC_REG(reg)		(IO_ADDRESS(LCDC_BASE_ADDR) + reg)
+
+#define MX2FB_INT_BOF		0x0001	/* Beginning of Frame */
+#define MX2FB_INT_EOF		0x0002	/* End of Frame */
+#define MX2FB_INT_ERR_RES	0x0004	/* Error Response */
+#define MX2FB_INT_UDR_ERR	0x0008	/* Under Run Error */
+#define MX2FB_INT_GW_BOF	0x0010	/* Graphic Window BOF */
+#define MX2FB_INT_GW_EOF	0x0020	/* Graphic Window EOF */
+#define MX2FB_INT_GW_ERR_RES	0x0040	/* Graphic Window ERR_RES */
+#define MX2FB_INT_GW_UDR_ERR	0x0080	/* Graphic Window UDR_ERR */
+
+#define FB_EVENT_MXC_EOF	0x8001	/* End of Frame event */
+
+int mx2fb_register_client(struct notifier_block *nb);
+int mx2fb_unregister_client(struct notifier_block *nb);
+
+void mx2_gw_set(struct fb_gwinfo *gwinfo);
+
+#endif				/* __KERNEL__ */
+
+#endif				/* __MX2FB_H__ */
diff --git a/drivers/video/mxc/mxc_edid.c b/drivers/video/mxc/mxc_edid.c
new file mode 100644
index 000000000000..23c5470b387f
--- /dev/null
+++ b/drivers/video/mxc/mxc_edid.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxc_edid.c
+ *
+ * @brief MXC EDID tools
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/fb.h>
+
+#define EDID_LENGTH 128
+
+static u8 edid[EDID_LENGTH];
+
+int read_edid(struct i2c_adapter *adp,
+	      struct fb_var_screeninfo *einfo,
+	      int *dvi)
+{
+	u8 buf0[2] = {0, 0};
+	int dat = 0;
+	u16 addr = 0x50;
+	struct i2c_msg msg[2] = {
+		{
+		.addr	= addr,
+		.flags	= 0,
+		.len	= 1,
+		.buf	= buf0,
+		}, {
+		.addr	= addr,
+		.flags	= I2C_M_RD,
+		.len	= EDID_LENGTH,
+		.buf	= edid,
+		},
+	};
+
+	if (adp == NULL || einfo == NULL)
+		return -EINVAL;
+
+	buf0[0] = 0x00;
+	memset(&edid, 0, sizeof(edid));
+	memset(einfo, 0, sizeof(struct fb_var_screeninfo));
+	dat = i2c_transfer(adp, msg, 2);
+
+	/* If 0x50 fails, try 0x37. */
+	if (edid[1] == 0x00) {
+		msg[0].addr = msg[1].addr = 0x37;
+		dat = i2c_transfer(adp, msg, 2);
+	}
+
+	if (edid[1] == 0x00)
+		return -ENOENT;
+
+	*dvi = 0;
+	if ((edid[20] == 0x80) || (edid[20] == 0x88) || (edid[20] == 0))
+		*dvi = 1;
+
+	dat = fb_parse_edid(edid, einfo);
+	if (dat)
+		return -dat;
+
+	/* This is valid for version 1.3 of the EDID */
+	if ((edid[18] == 1) && (edid[19] == 3)) {
+		einfo->height = edid[21] * 10;
+		einfo->width = edid[22] * 10;
+	}
+
+	return 0;
+}
diff --git a/drivers/video/mxc/mxc_elcdif_fb.c b/drivers/video/mxc/mxc_elcdif_fb.c
new file mode 100644
index 000000000000..1619a6593f64
--- /dev/null
+++ b/drivers/video/mxc/mxc_elcdif_fb.c
@@ -0,0 +1,1436 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on drivers/video/mxc/mxc_ipuv3_fb.c, drivers/video/mxs/lcdif.c
+ *	    and arch/arm/mach-mx28/include/mach/lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/mxcfb.h>
+#include <linux/uaccess.h>
+
+#include <mach/hardware.h>
+
+#include "elcdif_regs.h"
+
+/*  ELCDIF Pixel format definitions */
+/*  Four-character-code (FOURCC) */
+#define fourcc(a, b, c, d) \
+	(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * ELCDIF RGB Formats
+ */
+#define ELCDIF_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')
+#define ELCDIF_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')
+#define ELCDIF_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')
+#define ELCDIF_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')
+#define ELCDIF_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')
+#define ELCDIF_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')
+#define ELCDIF_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')
+#define ELCDIF_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')
+#define ELCDIF_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')
+#define ELCDIF_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')
+#define ELCDIF_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')
+#define ELCDIF_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')
+
+struct mxc_elcdif_fb_data {
+	int cur_blank;
+	int next_blank;
+	int output_pix_fmt;
+	int elcdif_mode;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	dma_addr_t cur_phys;
+	int dma_irq;
+	int err_irq;
+	void *virt_start;
+	struct completion vsync_complete;
+	struct semaphore flip_sem;
+	u32 pseudo_palette[16];
+};
+
+struct elcdif_signal_cfg {
+	unsigned clk_pol:1;	/* true = falling edge */
+	unsigned enable_pol:1;	/* true = active high */
+	unsigned Hsync_pol:1;	/* true = active high */
+	unsigned Vsync_pol:1;	/* true = active high */
+};
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info);
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *info);
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *info);
+static char *fb_mode;
+static unsigned long default_bpp = 16;
+static void __iomem *elcdif_base;
+static struct device *g_elcdif_dev;
+static bool g_elcdif_axi_clk_enable;
+static bool g_elcdif_pix_clk_enable;
+static struct clk *g_elcdif_axi_clk;
+static struct clk *g_elcdif_pix_clk;
+
+static inline void setup_dotclk_panel(u32 pixel_clk,
+				      u16 v_pulse_width,
+				      u16 v_period,
+				      u16 v_wait_cnt,
+				      u16 v_active,
+				      u16 h_pulse_width,
+				      u16 h_period,
+				      u16 h_wait_cnt,
+				      u16 h_active,
+				      int in_pixel_format,
+				      int out_pixel_format,
+				      struct elcdif_signal_cfg sig_cfg,
+				      int enable_present)
+{
+	u32 val, rounded_pixel_clk;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	dev_dbg(g_elcdif_dev, "pixel clk = %d\n", pixel_clk);
+	rounded_pixel_clk = clk_round_rate(g_elcdif_pix_clk, pixel_clk);
+	clk_set_rate(g_elcdif_pix_clk, rounded_pixel_clk);
+
+	__raw_writel(BM_ELCDIF_CTRL_DATA_SHIFT_DIR,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS
+		    (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8),
+		     elcdif_base + HW_ELCDIF_CTRL2_SET);
+
+	/* Recover on underflow */
+	__raw_writel(BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	/* Configure the input pixel format */
+	__raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+		     BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT |
+		     BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	switch (in_pixel_format) {
+	case ELCDIF_PIX_FMT_RGB565:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(0) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB24:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB32:
+		__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7),
+			     elcdif_base + HW_ELCDIF_CTRL1_SET);
+		__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+			     BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	default:
+		dev_err(g_elcdif_dev, "ELCDIF unsupported input pixel format "
+		       "%d\n", in_pixel_format);
+		break;
+	}
+
+	/* Configure the output pixel format */
+	__raw_writel(BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	switch (out_pixel_format) {
+	case ELCDIF_PIX_FMT_RGB565:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(0),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB666:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(2),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	case ELCDIF_PIX_FMT_RGB24:
+		__raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(3),
+			     elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+	default:
+		dev_err(g_elcdif_dev, "ELCDIF unsupported output pixel format "
+		       "%d\n", out_pixel_format);
+		break;
+	}
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+	val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+		 BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+	val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+	       BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+	__raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_POL |
+		 BM_ELCDIF_VDCTRL0_HSYNC_POL |
+		 BM_ELCDIF_VDCTRL0_ENABLE_POL |
+		 BM_ELCDIF_VDCTRL0_DOTCLK_POL);
+	if (sig_cfg.Vsync_pol)
+		val |= BM_ELCDIF_VDCTRL0_VSYNC_POL;
+	if (sig_cfg.Hsync_pol)
+		val |= BM_ELCDIF_VDCTRL0_HSYNC_POL;
+	if (sig_cfg.clk_pol)
+		val |= BM_ELCDIF_VDCTRL0_DOTCLK_POL;
+	if (sig_cfg.enable_pol)
+		val |= BM_ELCDIF_VDCTRL0_ENABLE_POL;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	/* vsync is output */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_OEB);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	/*
+	 * need enable sig for true RGB i/f.  Or, if not true RGB, leave it
+	 * zero.
+	 */
+	if (enable_present) {
+		val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+		val |= BM_ELCDIF_VDCTRL0_ENABLE_PRESENT;
+		__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+	}
+
+	/*
+	 * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines
+	 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+	val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+		 BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT);
+	val |= BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+	       BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+	__raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH,
+		     elcdif_base + HW_ELCDIF_VDCTRL0_CLR);
+	__raw_writel(v_pulse_width, elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+	__raw_writel(BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v_period),
+		     elcdif_base + HW_ELCDIF_VDCTRL1);
+
+	__raw_writel(BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) |
+		     BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(h_period),
+		     elcdif_base + HW_ELCDIF_VDCTRL2);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+	val &= ~BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT;
+	val |= BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL3);
+	val &= ~(BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT |
+		 BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT);
+	val |= BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) |
+	       BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+	val |= BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON;
+	__raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+	return;
+}
+
+static inline void release_dotclk_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL0);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL1);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL2);
+	__raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+	return;
+}
+
+static inline void setup_dvi_panel(u16 h_active, u16 v_active,
+				   u16 h_blanking, u16 v_lines,
+				   u16 v1_blank_start, u16 v1_blank_end,
+				   u16 v2_blank_start, u16 v2_blank_end,
+				   u16 f1_start, u16 f1_end,
+				   u16 f2_start, u16 f2_end)
+{
+	u32 val;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	/* 32bit packed format (RGB) */
+	__raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) |
+		     BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+	val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+		 BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+	val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+	       BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+	/* set elcdif to DVI mode */
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	/* convert input RGB -> YCbCr */
+	__raw_writel(BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	/* interlace odd and even fields */
+	__raw_writel(BM_ELCDIF_CTRL1_INTERLACE_FIELDS,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	__raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+		     BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+		     BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |	/* 24 bit */
+		      BM_ELCDIF_CTRL_DATA_SELECT |	/* data mode */
+		      BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |	/* no swap */
+		      BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(1),	/* 8 bit */
+		      elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	/* ELCDIF_DVI */
+	/* set frame size */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL0);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL0);
+
+	/* set start/end of field-1 and start of field-2 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL1);
+	val &= ~(BM_ELCDIF_DVICTRL1_F1_START_LINE |
+		 BM_ELCDIF_DVICTRL1_F1_END_LINE |
+		 BM_ELCDIF_DVICTRL1_F2_START_LINE);
+	val |= BF_ELCDIF_DVICTRL1_F1_START_LINE(f1_start) |
+	       BF_ELCDIF_DVICTRL1_F1_END_LINE(f1_end) |
+	       BF_ELCDIF_DVICTRL1_F2_START_LINE(f2_start);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL1);
+
+	/* set first vertical blanking interval and end of filed-2 */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL2);
+	val &= ~(BM_ELCDIF_DVICTRL2_F2_END_LINE |
+		 BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE |
+		 BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE);
+	val |= BF_ELCDIF_DVICTRL2_F2_END_LINE(f2_end) |
+	       BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) |
+	       BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL2);
+
+	/* set second vertical blanking interval */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL3);
+	val &= ~(BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE |
+		      BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE);
+	val |= BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) |
+	       BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL3);
+
+	/* fill the rest area black color if the input frame
+	 * is not 720 pixels/line
+	 */
+	if (h_active != 720) {
+		/* the input frame can't be less then (720-256) pixels/line */
+		if (720 - h_active > 0xff)
+			h_active = 720 - 0xff;
+
+		val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL4);
+		val &= ~(BM_ELCDIF_DVICTRL4_H_FILL_CNT |
+			      BM_ELCDIF_DVICTRL4_Y_FILL_VALUE |
+			      BM_ELCDIF_DVICTRL4_CB_FILL_VALUE |
+			      BM_ELCDIF_DVICTRL4_CR_FILL_VALUE);
+		val |= BF_ELCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) |
+		       BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(16) |
+		       BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(128) |
+		       BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(128);
+		__raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL4);
+	}
+
+	/* Color Space Conversion RGB->YCbCr */
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF0);
+	val &= ~(BM_ELCDIF_CSC_COEFF0_C0 |
+		      BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER);
+	val |= BF_ELCDIF_CSC_COEFF0_C0(0x41) |
+	       BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF0);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF1);
+	val &= ~(BM_ELCDIF_CSC_COEFF1_C1 | BM_ELCDIF_CSC_COEFF1_C2);
+	val |= BF_ELCDIF_CSC_COEFF1_C1(0x81) |
+	       BF_ELCDIF_CSC_COEFF1_C2(0x19);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF1);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF2);
+	val &= ~(BM_ELCDIF_CSC_COEFF2_C3 | BM_ELCDIF_CSC_COEFF2_C4);
+	val |= BF_ELCDIF_CSC_COEFF2_C3(0x3DB) |
+	       BF_ELCDIF_CSC_COEFF2_C4(0x3B6);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF2);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF3);
+	val &= ~(BM_ELCDIF_CSC_COEFF3_C5 | BM_ELCDIF_CSC_COEFF3_C6);
+	val |= BF_ELCDIF_CSC_COEFF3_C5(0x70) |
+	       BF_ELCDIF_CSC_COEFF3_C6(0x70);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF3);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF4);
+	val &= ~(BM_ELCDIF_CSC_COEFF4_C7 | BM_ELCDIF_CSC_COEFF4_C8);
+	val |= BF_ELCDIF_CSC_COEFF4_C7(0x3A2) |
+	       BF_ELCDIF_CSC_COEFF4_C8(0x3EE);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF4);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_OFFSET);
+	val &= ~(BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET |
+		 BM_ELCDIF_CSC_OFFSET_Y_OFFSET);
+	val |= BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) |
+	       BF_ELCDIF_CSC_OFFSET_Y_OFFSET(0x10);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_OFFSET);
+
+	val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_LIMIT);
+	val &= ~(BM_ELCDIF_CSC_LIMIT_CBCR_MIN |
+		 BM_ELCDIF_CSC_LIMIT_CBCR_MAX |
+		 BM_ELCDIF_CSC_LIMIT_Y_MIN |
+		 BM_ELCDIF_CSC_LIMIT_Y_MAX);
+	val |= BF_ELCDIF_CSC_LIMIT_CBCR_MIN(16) |
+	       BF_ELCDIF_CSC_LIMIT_CBCR_MAX(240) |
+	       BF_ELCDIF_CSC_LIMIT_Y_MIN(16) |
+	       BF_ELCDIF_CSC_LIMIT_Y_MAX(235);
+	__raw_writel(val, elcdif_base + HW_ELCDIF_CSC_LIMIT);
+
+	return;
+}
+
+static inline void release_dvi_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+			elcdif_base + HW_ELCDIF_CTRL_CLR);
+	return;
+}
+
+static inline void mxc_init_elcdif(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_CLKGATE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	/* Reset controller */
+	__raw_writel(BM_ELCDIF_CTRL_SFTRST,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	udelay(10);
+
+	/* Take controller out of reset */
+	__raw_writel(BM_ELCDIF_CTRL_SFTRST | BM_ELCDIF_CTRL_CLKGATE,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+	/* Setup the bus protocol */
+	__raw_writel(BM_ELCDIF_CTRL1_MODE86,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_BUSY_ENABLE,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+	/* Take display out of reset */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+	/* VSYNC is an input by default */
+	__raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_OEB,
+		     elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+	/* Reset display */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	udelay(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);
+	udelay(10);
+
+	return;
+}
+
+static inline int mxc_elcdif_dma_init(dma_addr_t phys)
+{
+	int ret = 0;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+
+	__raw_writel(phys, elcdif_base + HW_ELCDIF_CUR_BUF);
+	__raw_writel(phys, elcdif_base + HW_ELCDIF_NEXT_BUF);
+	return ret;
+}
+
+static inline void mxc_elcdif_dma_release(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	return;
+}
+
+static inline void mxc_elcdif_run(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	__raw_writel(BM_ELCDIF_CTRL_RUN,
+		     elcdif_base + HW_ELCDIF_CTRL_SET);
+	return;
+}
+
+static inline void mxc_elcdif_stop(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	__raw_writel(BM_ELCDIF_CTRL_RUN,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	__raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+		     elcdif_base + HW_ELCDIF_CTRL_CLR);
+	msleep(1);
+	__raw_writel(BM_ELCDIF_CTRL_CLKGATE, elcdif_base + HW_ELCDIF_CTRL_SET);
+	return;
+}
+
+static int mxc_elcdif_blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+				elcdif_base + HW_ELCDIF_CTRL_CLR);
+		for (count = 10000; count; count--) {
+			if (__raw_readl(elcdif_base + HW_ELCDIF_STAT) &
+			    BM_ELCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			msleep(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+			      elcdif_base + HW_ELCDIF_CTRL_SET);
+		break;
+
+	default:
+		dev_err(g_elcdif_dev, "unknown blank parameter\n");
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_init_panel(void)
+{
+	if (!g_elcdif_axi_clk_enable) {
+		clk_enable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = true;
+	}
+
+	/*
+	 * Make sure we do a high-to-low transition to reset the panel.
+	 * First make it low for 100 msec, hi for 10 msec, low for 10 msec,
+	 * then hi.
+	 */
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);	/* low */
+	msleep(100);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);	/* high */
+	msleep(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_CLR);	/* low */
+
+	/* For the Samsung, Reset must be held low at least 30 uSec
+	 * Therefore, we'll hold it low for about 10 mSec just to be sure.
+	 * Then we'll wait 1 mSec afterwards.
+	 */
+	msleep(10);
+	__raw_writel(BM_ELCDIF_CTRL1_RESET,
+		     elcdif_base + HW_ELCDIF_CTRL1_SET);	/* high */
+	msleep(1);
+
+	return 0;
+}
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+	uint32_t pixfmt = 0;
+
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	switch (fbi->var.bits_per_pixel) {
+	case 32:
+		pixfmt = ELCDIF_PIX_FMT_RGB32;
+		break;
+	case 24:
+		pixfmt = ELCDIF_PIX_FMT_RGB24;
+		break;
+	case 18:
+		pixfmt = ELCDIF_PIX_FMT_RGB666;
+		break;
+	case 16:
+		pixfmt = ELCDIF_PIX_FMT_RGB565;
+		break;
+	case 8:
+		pixfmt = ELCDIF_PIX_FMT_RGB332;
+		break;
+	}
+	return pixfmt;
+}
+
+static int mxc_elcdif_fb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+static irqreturn_t lcd_irq_handler(int irq, void *dev_id)
+{
+	struct mxc_elcdif_fb_data *data = dev_id;
+	u32 status_lcd = __raw_readl(elcdif_base + HW_ELCDIF_CTRL1);
+	dev_dbg(g_elcdif_dev, "%s: irq %d\n", __func__, irq);
+
+	if (status_lcd & BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: VSYNC irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+		complete(&data->vsync_complete);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: frame done irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+		up(&data->flip_sem);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_UNDERFLOW_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: underflow irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_UNDERFLOW_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	}
+	if (status_lcd & BM_ELCDIF_CTRL1_OVERFLOW_IRQ) {
+		dev_dbg(g_elcdif_dev, "%s: overflow irq\n", __func__);
+		__raw_writel(BM_ELCDIF_CTRL1_OVERFLOW_IRQ,
+			     elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	}
+	return IRQ_HANDLED;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+static int mxc_elcdif_fb_setcolreg(u_int regno, u_int red, u_int green,
+				 u_int blue, u_int transp,
+				 struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+	return ret;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_elcdif_fb_set_par(struct fb_info *fbi)
+{
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+	struct elcdif_signal_cfg sig_cfg;
+	int mem_len;
+
+	dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
+
+	sema_init(&data->flip_sem, 1);
+
+	/* release prev panel */
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_elcdif_blank_panel(FB_BLANK_POWERDOWN);
+	mxc_elcdif_stop();
+	release_dotclk_panel();
+	mxc_elcdif_dma_release();
+	mxc_elcdif_fb_set_fix(fbi);
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+		if (fbi->fix.smem_start)
+			mxc_elcdif_fb_unmap_video_memory(fbi);
+
+		if (mxc_elcdif_fb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+	}
+
+	if (data->next_blank != FB_BLANK_UNBLANK)
+		return 0;
+
+	/* init next panel */
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_init_elcdif();
+	mxc_elcdif_init_panel();
+
+	dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+		(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+	memset(&sig_cfg, 0, sizeof(sig_cfg));
+	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+		sig_cfg.Hsync_pol = true;
+	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+		sig_cfg.Vsync_pol = true;
+	if (fbi->var.sync & FB_SYNC_CLK_LAT_FALL)
+		sig_cfg.clk_pol = true;
+	if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+		sig_cfg.enable_pol = true;
+
+	setup_dotclk_panel((PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+			   fbi->var.vsync_len,
+			   fbi->var.upper_margin +
+			   fbi->var.yres + fbi->var.lower_margin,
+			   fbi->var.upper_margin,
+			   fbi->var.yres,
+			   fbi->var.hsync_len,
+			   fbi->var.left_margin +
+			   fbi->var.xres + fbi->var.right_margin,
+			   fbi->var.left_margin,
+			   fbi->var.xres,
+			   bpp_to_pixfmt(fbi),
+			   data->output_pix_fmt,
+			   sig_cfg,
+			   1);
+	mxc_elcdif_dma_init(fbi->fix.smem_start);
+	mxc_elcdif_run();
+	mxc_elcdif_blank_panel(FB_BLANK_UNBLANK);
+
+	fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
+							 &fbi->modelist);
+	return 0;
+}
+
+static int mxc_elcdif_fb_check_var(struct fb_var_screeninfo *var,
+				 struct fb_info *info)
+{
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+		var->bits_per_pixel = default_bpp;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->red.length = 3;
+		var->red.offset = 5;
+		var->red.msb_right = 0;
+
+		var->green.length = 3;
+		var->green.offset = 2;
+		var->green.msb_right = 0;
+
+		var->blue.length = 2;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	return 0;
+}
+
+static int mxc_elcdif_fb_wait_for_vsync(u32 channel, struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+
+	if (data->cur_blank != FB_BLANK_UNBLANK) {
+		dev_err(info->device, "can't wait for VSYNC when fb "
+			"is blank\n");
+		return -EINVAL;
+	}
+
+	init_completion(&data->vsync_complete);
+
+	__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_SET);
+	ret = wait_for_completion_interruptible_timeout(
+				&data->vsync_complete, 1 * HZ);
+	if (ret == 0) {
+		dev_err(info->device,
+			"MXC ELCDIF wait for vsync: timeout %d\n",
+			ret);
+		ret = -ETIME;
+	} else if (ret > 0) {
+		ret = 0;
+	}
+	__raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	if (!ret) {
+		dev_err(info->device, "wait for vsync timed out\n");
+		ret = -ETIMEDOUT;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			unsigned long arg)
+{
+	u32 channel = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case MXCFB_WAIT_FOR_VSYNC:
+		if (!get_user(channel, (__u32 __user *) arg))
+			ret = mxc_elcdif_fb_wait_for_vsync(channel, info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+
+	if (data->cur_blank == blank)
+		return ret;
+
+	data->next_blank = blank;
+
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	ret = mxc_elcdif_blank_panel(blank);
+	if (ret == 0)
+		data->cur_blank = blank;
+	else
+		return ret;
+
+	if (blank == FB_BLANK_UNBLANK) {
+		ret = mxc_elcdif_fb_set_par(info);
+		if (ret)
+			return ret;
+	}
+
+	if (data->cur_blank != FB_BLANK_UNBLANK) {
+		if (g_elcdif_axi_clk_enable) {
+			clk_disable(g_elcdif_axi_clk);
+			g_elcdif_axi_clk_enable = false;
+		}
+		if (g_elcdif_pix_clk_enable) {
+			clk_disable(g_elcdif_pix_clk);
+			g_elcdif_pix_clk_enable = false;
+		}
+	} else {
+		if (!g_elcdif_axi_clk_enable) {
+			clk_enable(g_elcdif_axi_clk);
+			g_elcdif_axi_clk_enable = true;
+		}
+		if (!g_elcdif_pix_clk_enable) {
+			clk_enable(g_elcdif_pix_clk);
+			g_elcdif_pix_clk_enable = true;
+		}
+	}
+
+	return ret;
+}
+
+static int mxc_elcdif_fb_pan_display(struct fb_var_screeninfo *var,
+				struct fb_info *info)
+{
+	struct mxc_elcdif_fb_data *data =
+				(struct mxc_elcdif_fb_data *)info->par;
+	int ret = 0;
+	unsigned long base;
+
+	if (data->cur_blank != FB_BLANK_UNBLANK) {
+		dev_err(info->device, "can't do pan display when fb "
+			"is blank\n");
+		return -EINVAL;
+	}
+
+	if (var->xoffset > 0) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((var->yoffset + var->yres > var->yres_virtual)) {
+		dev_err(info->device, "y panning exceeds\n");
+		return -EINVAL;
+	}
+
+	/* update framebuffer visual */
+	base = (var->yoffset * var->xres_virtual + var->xoffset);
+	base *= (var->bits_per_pixel) / 8;
+	base += info->fix.smem_start;
+
+	__raw_writel(base, elcdif_base + HW_ELCDIF_NEXT_BUF);
+
+	init_completion(&data->vsync_complete);
+
+	/*
+	 * Wait for an interrupt or we will lose frame
+	 * if we call pan-dislay too fast.
+	 */
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_SET);
+	down(&data->flip_sem);
+	__raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+		elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+	return ret;
+}
+
+static struct fb_ops mxc_elcdif_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mxc_elcdif_fb_check_var,
+	.fb_set_par = mxc_elcdif_fb_set_par,
+	.fb_setcolreg = mxc_elcdif_fb_setcolreg,
+	.fb_ioctl = mxc_elcdif_fb_ioctl,
+	.fb_blank = mxc_elcdif_fb_blank,
+	.fb_pan_display = mxc_elcdif_fb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *fbi)
+{
+	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+				    fbi->fix.line_length;
+
+	fbi->screen_base = dma_alloc_writecombine(fbi->device,
+				fbi->fix.smem_len,
+				(dma_addr_t *)&fbi->fix.smem_start,
+				GFP_DMA);
+	if (fbi->screen_base == 0) {
+		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+		fbi->fix.smem_len = 0;
+		fbi->fix.smem_start = 0;
+		return -EBUSY;
+	}
+
+	dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *fbi)
+{
+	dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+			      fbi->screen_base, fbi->fix.smem_start);
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+static int mxc_elcdif_fb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_elcdif_fb_data *data;
+	struct resource *res;
+	struct fb_info *fbi;
+	struct mxc_fb_platform_data *pdata = pdev->dev.platform_data;
+
+	fbi = framebuffer_alloc(sizeof(struct mxc_elcdif_fb_data), &pdev->dev);
+	if (fbi == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	data = (struct mxc_elcdif_fb_data *)fbi->par;
+	data->cur_blank = data->next_blank = FB_BLANK_UNBLANK;
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+	fbi->fbops = &mxc_elcdif_fb_ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = data->pseudo_palette;
+
+	ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
+	if (ret)
+		goto out;
+
+	g_elcdif_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto err0;
+	}
+	data->dma_irq = res->start;
+
+	ret = request_irq(data->dma_irq, lcd_irq_handler, 0,
+			  "mxc_elcdif_fb", data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+				data->dma_irq, ret);
+		goto err0;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto err1;
+	}
+	elcdif_base = ioremap(res->start, SZ_4K);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res) {
+		fbi->fix.smem_len = res->end - res->start + 1;
+		fbi->fix.smem_start = res->start;
+		fbi->screen_base = ioremap(fbi->fix.smem_start,
+					   fbi->fix.smem_len);
+	}
+
+	strcpy(fbi->fix.id, "mxc_elcdif_fb");
+
+	fbi->var.xres = 800;
+	fbi->var.yres = 480;
+
+	if (pdata && !data->output_pix_fmt)
+		data->output_pix_fmt = pdata->interface_pix_fmt;
+
+	if (pdata && pdata->mode && pdata->num_modes)
+		fb_videomode_to_modelist(pdata->mode, pdata->num_modes,
+				&fbi->modelist);
+
+	if (!fb_mode && pdata && pdata->mode_str)
+		fb_mode = pdata->mode_str;
+
+	if (fb_mode) {
+		ret = fb_find_mode(&fbi->var, fbi, fb_mode, NULL, 0, NULL,
+				   default_bpp);
+		if ((!ret || (ret > 2)) && pdata && pdata->mode &&
+		    pdata->num_modes)
+			fb_find_mode(&fbi->var, fbi, fb_mode, pdata->mode,
+					pdata->num_modes, NULL, default_bpp);
+	}
+
+	mxc_elcdif_fb_check_var(&fbi->var, fbi);
+
+	fbi->var.xres_virtual = fbi->var.xres;
+	fbi->var.yres_virtual = fbi->var.yres * 3;
+
+	mxc_elcdif_fb_set_fix(fbi);
+
+	if (!res || !res->end)
+		if (mxc_elcdif_fb_map_video_memory(fbi) < 0) {
+			ret = -ENOMEM;
+			goto err2;
+		}
+
+	g_elcdif_axi_clk = clk_get(g_elcdif_dev, "elcdif_axi");
+	if (g_elcdif_axi_clk == NULL) {
+		dev_err(&pdev->dev, "can't get ELCDIF axi clk\n");
+		ret = -ENODEV;
+		goto err3;
+	}
+	g_elcdif_pix_clk = clk_get(g_elcdif_dev, "elcdif_pix");
+	if (g_elcdif_pix_clk == NULL) {
+		dev_err(&pdev->dev, "can't get ELCDIF pix clk\n");
+		ret = -ENODEV;
+		goto err3;
+	}
+	/*
+	 * Set an appropriate pixel clk rate first, so that we can
+	 * access ELCDIF registers.
+	 */
+	clk_set_rate(g_elcdif_pix_clk, 25000000);
+
+	ret = register_framebuffer(fbi);
+	if (ret)
+		goto err3;
+
+	platform_set_drvdata(pdev, fbi);
+
+	return 0;
+err3:
+	mxc_elcdif_fb_unmap_video_memory(fbi);
+err2:
+	iounmap(elcdif_base);
+err1:
+	free_irq(data->dma_irq, data);
+err0:
+	fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+out:
+	return ret;
+}
+
+static int mxc_elcdif_fb_remove(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+	mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+	mxc_elcdif_stop();
+	release_dotclk_panel();
+	mxc_elcdif_dma_release();
+
+	if (g_elcdif_axi_clk_enable) {
+		clk_disable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = false;
+	}
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+	clk_put(g_elcdif_axi_clk);
+	clk_put(g_elcdif_pix_clk);
+
+	free_irq(data->dma_irq, data);
+	mxc_elcdif_fb_unmap_video_memory(fbi);
+
+	if (&fbi->cmap)
+		fb_dealloc_cmap(&fbi->cmap);
+
+	unregister_framebuffer(fbi);
+	framebuffer_release(fbi);
+
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_elcdif_fb_suspend(struct platform_device *pdev,
+			       pm_message_t state)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+	int saved_blank;
+
+	acquire_console_sem();
+	fb_set_suspend(fbi, 1);
+	saved_blank = data->cur_blank;
+	mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+	data->next_blank = saved_blank;
+	if (!g_elcdif_pix_clk_enable) {
+		clk_enable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = true;
+	}
+	mxc_elcdif_stop();
+	mxc_elcdif_dma_release();
+	if (g_elcdif_pix_clk_enable) {
+		clk_disable(g_elcdif_pix_clk);
+		g_elcdif_pix_clk_enable = false;
+	}
+	if (g_elcdif_axi_clk_enable) {
+		clk_disable(g_elcdif_axi_clk);
+		g_elcdif_axi_clk_enable = false;
+	}
+	release_console_sem();
+	return 0;
+}
+
+static int mxc_elcdif_fb_resume(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+	acquire_console_sem();
+	mxc_elcdif_fb_blank(data->next_blank, fbi);
+	fb_set_suspend(fbi, 0);
+	release_console_sem();
+
+	return 0;
+}
+#else
+#define	mxc_elcdif_fb_suspend	NULL
+#define	mxc_elcdif_fb_resume	NULL
+#endif
+
+static struct platform_driver mxc_elcdif_fb_driver = {
+	.probe		= mxc_elcdif_fb_probe,
+	.remove		= mxc_elcdif_fb_remove,
+	.suspend	= mxc_elcdif_fb_suspend,
+	.resume		= mxc_elcdif_fb_resume,
+	.driver		= {
+		.name   = "mxc_elcdif_fb",
+		.owner	= THIS_MODULE,
+	},
+};
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * 	video=trident:800x600,bpp=16,noaccel
+ */
+int mxc_elcdif_fb_setup(char *options)
+{
+	char *opt;
+	if (!options || !*options)
+		return 0;
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+
+		if (!strncmp(opt, "bpp=", 4))
+			default_bpp = simple_strtoul(opt + 4, NULL, 0);
+		else
+			fb_mode = opt;
+	}
+	return 0;
+}
+
+static int __init mxc_elcdif_fb_init(void)
+{
+	char *option = NULL;
+
+	if (fb_get_options("mxc_elcdif_fb", &option))
+		return -ENODEV;
+	mxc_elcdif_fb_setup(option);
+
+	return platform_driver_register(&mxc_elcdif_fb_driver);
+}
+
+static void __exit mxc_elcdif_fb_exit(void)
+{
+	platform_driver_unregister(&mxc_elcdif_fb_driver);
+}
+
+module_init(mxc_elcdif_fb_init);
+module_exit(mxc_elcdif_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC ELCDIF Framebuffer Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c
new file mode 100644
index 000000000000..109fa314a3cf
--- /dev/null
+++ b/drivers/video/mxc/mxc_epdc_fb.c
@@ -0,0 +1,3065 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X LCDIF
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*#define		NO_POWERDOWN*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+#include <linux/firmware.h>
+#include <linux/kthread.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+#include <linux/mxcfb.h>
+#include <linux/gpio.h>
+#include <linux/regulator/driver.h>
+
+#include "epdc_regs.h"
+
+/*
+ * Enable this define to have a default panel
+ * loaded during driver initialization
+ */
+/*#define DEFAULT_PANEL_HW_INIT*/
+
+#define NUM_SCREENS	2
+#define EPDC_NUM_LUTS 16
+#define EPDC_MAX_NUM_UPDATES 20
+#define INVALID_LUT -1
+#define TEMP_USE_DEFAULT 8
+#define INIT_UPDATE_MARKER 0x12345678
+#define PAN_UPDATE_MARKER 0x12345679
+
+#define LUT_UPDATE_NONE	0
+#define LUT_UPDATE_NEW	1
+#define LUT_UPDATE_COLLISION	2
+
+#define POWER_STATE_OFF	0
+#define POWER_STATE_ON	1
+
+static unsigned long default_bpp = 16;
+
+struct mxc_epdc_platform_fb_entry {
+	char name[16];
+	u16 x_res;
+	u16 y_res;
+	u16 bpp;
+	u32 cycle_time_ns;
+	struct list_head link;
+};
+
+struct mxc_epdc_platform_fb_data {
+	struct list_head list;
+	struct mxc_epdc_platform_fb_entry *cur;
+};
+
+struct update_marker_data {
+	u32 update_marker;
+	struct completion update_completion;
+	int lut_num;
+};
+
+/* This structure represents a list node containing both
+ * a memory region allocated as an output buffer for the PxP
+ * update processing task, and the update description (mode, region, etc.) */
+struct update_data_list {
+	struct list_head list;
+	struct mxcfb_update_data upd_data;	/* Update parameters */
+	dma_addr_t phys_addr;			/* Pointer to phys address of processed Y buf */
+	void *virt_addr;
+	u32 epdc_offs;				/* Add to buffer pointer to resolve alignment */
+	u32 size;
+	int lut_num;				/* Assigned before update is processed into working buffer */
+	int collision_mask;			/* Set when update results in collision */
+						/* Represents other LUTs that we collide with */
+	struct update_marker_data *upd_marker_data;
+	bool is_collision;
+};
+
+struct mxc_epdc_fb_data {
+	struct fb_info info;
+	u32 pseudo_palette[16];
+	struct list_head list;
+	struct mxc_epdc_platform_fb_entry *cur;
+	int blank;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	u32 fb_offset;
+	int native_width;
+	int native_height;
+	int epdc_irq;
+	struct device *dev;
+	wait_queue_head_t vsync_wait_q;
+	u32 vsync_count;
+	void *par;
+	int power_state;
+	struct clk *epdc_clk_axi;
+	struct clk *epdc_clk_pix;
+	struct regulator *display_regulator;
+	struct regulator *vcom_regulator;
+
+	/* FB elements related to EPDC updates */
+	bool in_init;
+	bool hw_ready;
+	bool waiting_for_idle;
+	u32 auto_mode;
+	struct update_data_list *upd_buf_queue;
+	struct update_data_list *upd_buf_free_list;
+	struct update_data_list *upd_buf_collision_list;
+	struct update_data_list *cur_update;
+	spinlock_t queue_lock;
+	int trt_entries;
+	u8 *temp_range_bounds;
+	struct mxcfb_waveform_modes wv_modes;
+	u32 *waveform_buffer_virt;
+	u32 waveform_buffer_phys;
+	u32 waveform_buffer_size;
+	u32 *working_buffer_virt;
+	u32 working_buffer_phys;
+	u32 working_buffer_size;
+	struct update_marker_data update_marker_array[EPDC_MAX_NUM_UPDATES];
+	u32 lut_update_type[EPDC_NUM_LUTS];
+	struct completion updates_done;
+	struct work_struct epdc_done_work;
+	struct mutex power_mutex;
+	bool powering_down;
+
+	/* FB elements related to PxP DMA */
+	struct completion pxp_tx_cmpl;
+	struct pxp_channel *pxp_chan;
+	struct pxp_config_data pxp_conf;
+	struct dma_async_tx_descriptor *txd;
+	dma_cookie_t cookie;
+	struct scatterlist sg[2];
+	struct mutex pxp_mutex; /* protects access to PxP */
+};
+
+struct waveform_data_header {
+	unsigned int wi0;
+	unsigned int wi1;
+	unsigned int wi2;
+	unsigned int wi3;
+	unsigned int wi4;
+	unsigned int wi5;
+	unsigned int wi6;
+	unsigned int xwia:24;
+	unsigned int cs1:8;
+	unsigned int wmta:24;
+	unsigned int fvsn:8;
+	unsigned int luts:8;
+	unsigned int mc:8;
+	unsigned int trc:8;
+	unsigned int reserved0_0:8;
+	unsigned int eb:8;
+	unsigned int sb:8;
+	unsigned int reserved0_1:8;
+	unsigned int reserved0_2:8;
+	unsigned int reserved0_3:8;
+	unsigned int reserved0_4:8;
+	unsigned int reserved0_5:8;
+	unsigned int cs2:8;
+};
+
+struct mxcfb_waveform_data_file {
+	struct waveform_data_header wdh;
+	u32 *data;	/* Temperature Range Table + Waveform Data */
+};
+
+void __iomem *epdc_base;
+
+#define NUM_PANELS 1
+
+static struct fb_videomode panel_modes[NUM_PANELS] = {
+	{
+	 /* 800x600 @ 60 Hz , pixel clk @ 20MHz */
+	 "E-INK SVGA", 60, 800, 600, 50000, 10, 217, 4, 10, 20, 4,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+/*
+ * This is a temporary placeholder
+ * Ultimately, this declaration will be off in a panel-specific file,
+ * and will include implementations for all of the panel functions
+ */
+static struct mxc_epdc_platform_fb_entry ed060sc4_fb_entry = {
+	.name = "ed060sc4",
+	.x_res = 800,
+	.y_res = 600,
+	.bpp = 16,
+	.cycle_time_ns = 200,
+};
+
+/* forward declaration */
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
+static int mxc_epdc_fb_init_hw(struct fb_info *info);
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+			      struct mxcfb_rect *update_region);
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
+
+#ifdef DEBUG
+static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+			    struct pxp_config_data *pxp_conf)
+{
+	dev_err(fb_data->dev, "S0 fmt 0x%x",
+		pxp_conf->s0_param.pixel_fmt);
+	dev_err(fb_data->dev, "S0 width 0x%x",
+		pxp_conf->s0_param.width);
+	dev_err(fb_data->dev, "S0 height 0x%x",
+		pxp_conf->s0_param.height);
+	dev_err(fb_data->dev, "S0 ckey 0x%x",
+		pxp_conf->s0_param.color_key);
+	dev_err(fb_data->dev, "S0 ckey en 0x%x",
+		pxp_conf->s0_param.color_key_enable);
+
+	dev_err(fb_data->dev, "OL0 combine en 0x%x",
+		pxp_conf->ol_param[0].combine_enable);
+	dev_err(fb_data->dev, "OL0 fmt 0x%x",
+		pxp_conf->ol_param[0].pixel_fmt);
+	dev_err(fb_data->dev, "OL0 width 0x%x",
+		pxp_conf->ol_param[0].width);
+	dev_err(fb_data->dev, "OL0 height 0x%x",
+		pxp_conf->ol_param[0].height);
+	dev_err(fb_data->dev, "OL0 ckey 0x%x",
+		pxp_conf->ol_param[0].color_key);
+	dev_err(fb_data->dev, "OL0 ckey en 0x%x",
+		pxp_conf->ol_param[0].color_key_enable);
+	dev_err(fb_data->dev, "OL0 alpha 0x%x",
+		pxp_conf->ol_param[0].global_alpha);
+	dev_err(fb_data->dev, "OL0 alpha en 0x%x",
+		pxp_conf->ol_param[0].global_alpha_enable);
+	dev_err(fb_data->dev, "OL0 local alpha en 0x%x",
+		pxp_conf->ol_param[0].local_alpha_enable);
+
+	dev_err(fb_data->dev, "Out fmt 0x%x",
+		pxp_conf->out_param.pixel_fmt);
+	dev_err(fb_data->dev, "Out width 0x%x",
+		pxp_conf->out_param.width);
+	dev_err(fb_data->dev, "Out height 0x%x",
+		pxp_conf->out_param.height);
+
+	dev_err(fb_data->dev,
+		"drect left 0x%x right 0x%x width 0x%x height 0x%x",
+		pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
+		pxp_conf->proc_data.drect.width,
+		pxp_conf->proc_data.drect.height);
+	dev_err(fb_data->dev,
+		"srect left 0x%x right 0x%x width 0x%x height 0x%x",
+		pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
+		pxp_conf->proc_data.srect.width,
+		pxp_conf->proc_data.srect.height);
+	dev_err(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
+	dev_err(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
+	dev_err(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
+	dev_err(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
+	dev_err(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
+}
+
+static void dump_epdc_reg(void)
+{
+	printk(KERN_DEBUG "\n\n");
+	printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
+	printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
+	printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
+	printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
+	printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
+	printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
+	printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
+	printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
+	printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
+	printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
+	printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
+	printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
+	printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
+	printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
+	printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
+	printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
+	printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
+	printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
+	printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
+	printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
+	printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
+	printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
+	printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
+	printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
+	printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
+	printk(KERN_DEBUG "EPDC_STATUS_COL 0x%x\n", __raw_readl(EPDC_STATUS_COL));
+	printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
+	printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT0 0x%x\n", __raw_readl(EPDC_DEBUG_LUT0));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT1 0x%x\n", __raw_readl(EPDC_DEBUG_LUT1));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT2 0x%x\n", __raw_readl(EPDC_DEBUG_LUT2));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT3 0x%x\n", __raw_readl(EPDC_DEBUG_LUT3));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT4 0x%x\n", __raw_readl(EPDC_DEBUG_LUT4));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT5 0x%x\n", __raw_readl(EPDC_DEBUG_LUT5));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT6 0x%x\n", __raw_readl(EPDC_DEBUG_LUT6));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT7 0x%x\n", __raw_readl(EPDC_DEBUG_LUT7));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT8 0x%x\n", __raw_readl(EPDC_DEBUG_LUT8));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT9 0x%x\n", __raw_readl(EPDC_DEBUG_LUT9));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT10 0x%x\n", __raw_readl(EPDC_DEBUG_LUT10));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT11 0x%x\n", __raw_readl(EPDC_DEBUG_LUT11));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT12 0x%x\n", __raw_readl(EPDC_DEBUG_LUT12));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT13 0x%x\n", __raw_readl(EPDC_DEBUG_LUT13));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT14 0x%x\n", __raw_readl(EPDC_DEBUG_LUT14));
+	printk(KERN_DEBUG "EPDC_DEBUG_LUT15 0x%x\n", __raw_readl(EPDC_DEBUG_LUT15));
+	printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
+	printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
+	printk(KERN_DEBUG "\n\n");
+}
+
+static void dump_update_data(struct device *dev,
+			     struct update_data_list *upd_data_list)
+{
+	dev_err(dev,
+		"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, LUT = %d, Coll Mask = %d\n",
+		upd_data_list->upd_data.update_region.left,
+		upd_data_list->upd_data.update_region.top,
+		upd_data_list->upd_data.update_region.width,
+		upd_data_list->upd_data.update_region.height,
+		upd_data_list->upd_data.waveform_mode, upd_data_list->lut_num,
+		upd_data_list->collision_mask);
+}
+
+static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Collision List:\n");
+	if (list_empty(&fb_data->upd_buf_collision_list->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_collision_list->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Free List:\n");
+	if (list_empty(&fb_data->upd_buf_free_list->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_queue(struct mxc_epdc_fb_data *fb_data)
+{
+	struct update_data_list *plist;
+
+	dev_err(fb_data->dev, "Queue:\n");
+	if (list_empty(&fb_data->upd_buf_queue->list))
+		dev_err(fb_data->dev, "Empty");
+	list_for_each_entry(plist, &fb_data->upd_buf_queue->list, list) {
+		dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+			(u32)plist->virt_addr, plist->phys_addr);
+		dump_update_data(fb_data->dev, plist);
+	}
+}
+
+static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
+{
+	dump_free_list(fb_data);
+	dump_queue(fb_data);
+	dump_collision_list(fb_data);
+	dev_err(fb_data->dev, "Current update being processed:\n");
+	if (fb_data->cur_update == NULL)
+		dev_err(fb_data->dev, "No current update\n");
+	else
+		dump_update_data(fb_data->dev, fb_data->cur_update);
+}
+#else
+static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+				   struct pxp_config_data *pxp_conf) {}
+static inline void dump_epdc_reg(void) {}
+static inline void dump_update_data(struct device *dev,
+			     struct update_data_list *upd_data_list) {}
+static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
+
+#endif
+
+static struct fb_var_screeninfo mxc_epdc_fb_default __devinitdata = {
+	.activate = FB_ACTIVATE_TEST,
+	.height = -1,
+	.width = -1,
+	.pixclock = 20000,
+	.left_margin = 8,
+	.right_margin = 142,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo mxc_epdc_fb_fix __devinitdata = {
+	.id = "mxc_epdc_fb",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.visual = FB_VISUAL_TRUECOLOR,
+	.xpanstep = 0,
+	.ypanstep = 0,
+	.ywrapstep = 0,
+	.accel = FB_ACCEL_NONE,
+	.line_length = 800 * 2,
+};
+
+/********************************************************
+ * Start Low-Level EPDC Functions
+ ********************************************************/
+
+static inline void epdc_lut_complete_intr(u32 lut_num, bool enable)
+{
+	if (enable)
+		__raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
+	else
+		__raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_working_buf_intr(bool enable)
+{
+	if (enable)
+		__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
+	else
+		__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_clear_working_buf_irq(void)
+{
+	__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
+		     EPDC_IRQ_CLEAR);
+}
+
+static inline void epdc_set_temp(u32 temp)
+{
+	__raw_writel(temp, EPDC_TEMP);
+}
+
+static inline void epdc_set_screen_res(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
+	__raw_writel(val, EPDC_RES);
+}
+
+static inline void epdc_set_update_addr(u32 addr)
+{
+	__raw_writel(addr, EPDC_UPD_ADDR);
+}
+
+static inline void epdc_set_update_coord(u32 x, u32 y)
+{
+	u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
+	__raw_writel(val, EPDC_UPD_CORD);
+}
+
+static inline void epdc_set_update_dimensions(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
+	__raw_writel(val, EPDC_UPD_SIZE);
+}
+
+static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
+			       bool use_test_mode, u32 np_val)
+{
+	u32 reg_val = 0;
+
+	if (use_test_mode) {
+		reg_val |=
+		    ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
+		     EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
+
+		__raw_writel(reg_val, EPDC_UPD_FIXED);
+
+		reg_val = EPDC_UPD_CTRL_USE_FIXED;
+	} else {
+		__raw_writel(reg_val, EPDC_UPD_FIXED);
+	}
+
+	reg_val |=
+	    ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
+	     EPDC_UPD_CTRL_LUT_SEL_MASK) |
+	    ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
+	     EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
+	    update_mode;
+
+	__raw_writel(reg_val, EPDC_UPD_CTRL);
+}
+
+static inline bool epdc_is_lut_complete(u32 lut_num)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	bool is_compl = val & (1 << lut_num) ? true : false;
+
+	return is_compl;
+}
+
+static inline void epdc_clear_lut_complete_irq(u32 lut_num)
+{
+	__raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
+}
+
+static inline bool epdc_is_lut_active(u32 lut_num)
+{
+	u32 val = __raw_readl(EPDC_STATUS_LUTS);
+	bool is_active = val & (1 << lut_num) ? true : false;
+
+	return is_active;
+}
+
+static inline bool epdc_any_luts_active(void)
+{
+	bool any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
+
+	return any_active;
+}
+
+static inline bool epdc_any_luts_available(void)
+{
+	bool luts_available =
+	    (__raw_readl(EPDC_STATUS_NEXTLUT) &
+	     EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
+	return luts_available;
+}
+
+static inline int epdc_get_next_lut(void)
+{
+	u32 val =
+	    __raw_readl(EPDC_STATUS_NEXTLUT) &
+	    EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
+	return val;
+}
+
+static inline bool epdc_is_working_buffer_busy(void)
+{
+	u32 val = __raw_readl(EPDC_STATUS);
+	bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
+
+	return is_busy;
+}
+
+static inline bool epdc_is_working_buffer_complete(void)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
+
+	return is_compl;
+}
+
+static inline bool epdc_is_collision(void)
+{
+	u32 val = __raw_readl(EPDC_IRQ);
+	return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
+}
+
+static inline int epdc_get_colliding_luts(void)
+{
+	u32 val = __raw_readl(EPDC_STATUS_COL);
+	return val;
+}
+
+static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
+				       u32 hsync_width, u32 hsync_line_length)
+{
+	u32 reg_val =
+	    ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
+	     EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
+	    | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
+	       EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
+	__raw_writel(reg_val, EPDC_TCE_HSCAN1);
+
+	reg_val =
+	    ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
+	     EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
+	    | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
+	       EPDC_TCE_HSCAN2_LINE_END_MASK);
+	__raw_writel(reg_val, EPDC_TCE_HSCAN2);
+}
+
+static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
+				     u32 vsync_width)
+{
+	u32 reg_val =
+	    ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
+	     EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
+	    | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
+	       EPDC_TCE_VSCAN_FRAME_END_MASK)
+	    | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
+	       EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
+	__raw_writel(reg_val, EPDC_TCE_VSCAN);
+}
+
+void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
+{
+	struct mxc_epdc_platform_fb_entry *pentry = fb_data->cur;
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	u32 reg_val;
+
+	/* Reset */
+	__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
+	while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
+		;
+	__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
+
+	/* Enable clock gating (clear to enable) */
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+	while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
+		;
+
+	/* EPDC_CTRL */
+	reg_val = __raw_readl(EPDC_CTRL);
+	reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
+	reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
+	__raw_writel(reg_val, EPDC_CTRL_SET);
+
+	/* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
+	reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
+	    | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
+	    | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
+	       EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
+	__raw_writel(reg_val, EPDC_FORMAT);
+
+	/* EPDC_FIFOCTRL (disabled) */
+	reg_val =
+	    ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
+	     EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
+	    | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
+	       EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
+	    | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
+	       EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
+	__raw_writel(reg_val, EPDC_FIFOCTRL);
+
+	/* EPDC_TEMP - 8 for room temperature */
+	epdc_set_temp(8);
+
+	/* EPDC_RES */
+	epdc_set_screen_res(pentry->x_res, pentry->y_res);
+
+	/*
+	 * EPDC_TCE_CTRL
+	 * VSCAN_HOLDOFF = 4
+	 * VCOM_MODE = MANUAL
+	 * VCOM_VAL = 0
+	 * DDR_MODE = DISABLED
+	 * LVDS_MODE_CE = DISABLED
+	 * LVDS_MODE = DISABLED
+	 * DUAL_SCAN = DISABLED
+	 * SDDO_WIDTH = 8bit
+	 * PIXELS_PER_SDCLK = 4
+	 */
+	reg_val =
+	    ((4 << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+	     EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+	    | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
+	__raw_writel(reg_val, EPDC_TCE_CTRL);
+
+	/* EPDC_TCE_HSCAN */
+	epdc_set_horizontal_timing(screeninfo->left_margin,
+				   screeninfo->right_margin,
+				   screeninfo->hsync_len,
+				   screeninfo->hsync_len);
+
+	/* EPDC_TCE_VSCAN */
+	epdc_set_vertical_timing(screeninfo->upper_margin,
+				 screeninfo->lower_margin,
+				 screeninfo->vsync_len);
+
+	/* EPDC_TCE_OE */
+	reg_val =
+	    ((10 << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+	     EPDC_TCE_OE_SDOED_WIDTH_MASK)
+	    | ((20 << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+	       EPDC_TCE_OE_SDOED_DLY_MASK)
+	    | ((10 << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+	       EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+	    | ((20 << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+	       EPDC_TCE_OE_SDOEZ_DLY_MASK);
+	__raw_writel(reg_val, EPDC_TCE_OE);
+
+	/* EPDC_TCE_TIMING1 */
+	__raw_writel(0x0, EPDC_TCE_TIMING1);
+
+	/* EPDC_TCE_TIMING2 */
+	reg_val =
+	    ((480 << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+	     EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+	    | ((20 << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+	       EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+	__raw_writel(reg_val, EPDC_TCE_TIMING2);
+
+	/* EPDC_TCE_TIMING3 */
+	reg_val =
+	    ((0 << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+	     EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+	    | ((1 << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+	       EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+	__raw_writel(reg_val, EPDC_TCE_TIMING3);
+
+	/*
+	 * EPDC_TCE_SDCFG
+	 * SDCLK_HOLD = 1
+	 * SDSHR = 1
+	 * NUM_CE = 1
+	 * SDDO_REFORMAT = FLIP_PIXELS
+	 * SDDO_INVERT = DISABLED
+	 * PIXELS_PER_CE = display horizontal resolution
+	 */
+	reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
+	    | ((1 << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
+	    | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
+	    | ((pentry->x_res << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
+	       EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
+	__raw_writel(reg_val, EPDC_TCE_SDCFG);
+
+	/*
+	 * EPDC_TCE_GDCFG
+	 * GDRL = 1
+	 * GDOE_MODE = 0;
+	 * GDSP_MODE = 0;
+	 */
+	reg_val = EPDC_TCE_SDCFG_GDRL;
+	__raw_writel(reg_val, EPDC_TCE_GDCFG);
+
+	/*
+	 * EPDC_TCE_POLARITY
+	 * SDCE_POL = ACTIVE LOW
+	 * SDLE_POL = ACTIVE HIGH
+	 * SDOE_POL = ACTIVE HIGH
+	 * GDOE_POL = ACTIVE HIGH
+	 * GDSP_POL = ACTIVE LOW
+	 */
+	reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
+	    | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
+	    | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
+	__raw_writel(reg_val, EPDC_TCE_POLARITY);
+
+	/* EPDC_IRQ_MASK */
+	__raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
+
+	/*
+	 * EPDC_GPIO
+	 * PWRCOM = ?
+	 * PWRCTRL = ?
+	 * BDR = ?
+	 */
+	reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
+	    | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
+	__raw_writel(reg_val, EPDC_GPIO);
+}
+
+static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
+{
+	mutex_lock(&fb_data->power_mutex);
+
+	/*
+	 * If power down request is pending, clear
+	 * powering_down to cancel the request.
+	 */
+	if (fb_data->powering_down)
+		fb_data->powering_down = false;
+
+	if (fb_data->power_state == POWER_STATE_ON) {
+		mutex_unlock(&fb_data->power_mutex);
+		return;
+	}
+
+	dev_dbg(fb_data->dev, "EPDC Powerup\n");
+
+	/* Enable clocks to EPDC */
+	clk_enable(fb_data->epdc_clk_axi);
+	clk_enable(fb_data->epdc_clk_pix);
+
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+
+	/* Enable power to the EPD panel */
+	regulator_enable(fb_data->display_regulator);
+	regulator_enable(fb_data->vcom_regulator);
+
+	fb_data->power_state = POWER_STATE_ON;
+
+	mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
+{
+	mutex_lock(&fb_data->power_mutex);
+
+	/* If powering_down has been cleared, a powerup
+	 * request is pre-empting this powerdown request.
+	 */
+	if (!fb_data->powering_down
+		|| (fb_data->power_state == POWER_STATE_OFF)) {
+		mutex_unlock(&fb_data->power_mutex);
+		return;
+	}
+
+	dev_dbg(fb_data->dev, "EPDC Powerdown\n");
+
+	/* Disable power to the EPD panel */
+	regulator_disable(fb_data->vcom_regulator);
+	regulator_disable(fb_data->display_regulator);
+
+	/* Disable clocks to EPDC */
+	__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
+	clk_disable(fb_data->epdc_clk_pix);
+	clk_disable(fb_data->epdc_clk_axi);
+
+	fb_data->power_state = POWER_STATE_OFF;
+	fb_data->powering_down = false;
+
+	mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data)
+{
+	/* Initialize EPDC, passing pointer to EPDC registers */
+	epdc_init_settings(fb_data);
+	__raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
+	__raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
+	epdc_powerup(fb_data);
+	draw_mode0(fb_data);
+	epdc_powerdown(fb_data);
+}
+
+static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+
+	if (offset < info->fix.smem_len) {
+		/* mapping framebuffer memory */
+		len = info->fix.smem_len - offset;
+		vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
+	} else
+		return -EINVAL;
+
+	len = PAGE_ALIGN(len);
+	if (vma->vm_end - vma->vm_start > len)
+		return -EINVAL;
+
+	/* make buffers bufferable */
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+		dev_dbg(info->device, "mmap remap_pfn_range failed\n");
+		return -ENOBUFS;
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green,
+				 u_int blue, u_int transp, struct fb_info *info)
+{
+	if (regno >= 256)	/* no. of hw registers */
+		return 1;
+	/*
+	 * Program hardware... do anything you want with transp
+	 */
+
+	/* grayscale works only partially under directcolor */
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		red = CNVT_TOHW(red, info->var.red.length);
+		green = CNVT_TOHW(green, info->var.green.length);
+		blue = CNVT_TOHW(blue, info->var.blue.length);
+		transp = CNVT_TOHW(transp, info->var.transp.length);
+		break;
+	case FB_VISUAL_DIRECTCOLOR:
+		red = CNVT_TOHW(red, 8);	/* expect 8 bit DAC */
+		green = CNVT_TOHW(green, 8);
+		blue = CNVT_TOHW(blue, 8);
+		/* hey, there is bug in transp handling... */
+		transp = CNVT_TOHW(transp, 8);
+		break;
+	}
+#undef CNVT_TOHW
+	/* Truecolor has hardware independent palette */
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+		if (regno >= 16)
+			return 1;
+
+		((u32 *) (info->pseudo_palette))[regno] =
+		    (red << info->var.red.offset) |
+		    (green << info->var.green.offset) |
+		    (blue << info->var.blue.offset) |
+		    (transp << info->var.transp.offset);
+	}
+	return 0;
+}
+
+static void adjust_coordinates(struct mxc_epdc_fb_data *fb_data, struct mxcfb_rect *update_region)
+{
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	u32 rotation = fb_data->info.var.rotate;
+	u32 temp;
+
+	switch (rotation) {
+	case FB_ROTATE_UR:
+		/* No adjustment needed */
+		break;
+	case FB_ROTATE_CW:
+		temp = update_region->top;
+		update_region->top = update_region->left;
+		update_region->left = screeninfo->yres - (temp + update_region->height);
+		temp = update_region->width;
+		update_region->width = update_region->height;
+		update_region->height = temp;
+		break;
+	case FB_ROTATE_UD:
+		update_region->top = screeninfo->yres - (update_region->top + update_region->height);
+		update_region->left = screeninfo->xres - (update_region->left + update_region->width);
+		break;
+	case FB_ROTATE_CCW:
+		temp = update_region->left;
+		update_region->left = update_region->top;
+		update_region->top = screeninfo->xres - (temp + update_region->width);
+		temp = update_region->width;
+		update_region->width = update_region->height;
+		update_region->height = temp;
+		break;
+	}
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxc_epdc_fb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_epdc_fb_set_par(struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+	struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+	struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+	int i;
+	int ret;
+
+	/*
+	 * Update PxP config data (used to process FB regions for updates)
+	 * based on FB info and processing tasks required
+	 */
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = screeninfo->xres;
+	proc_data->drect.height = proc_data->srect.height = screeninfo->yres;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = screeninfo->rotate;
+	proc_data->bgcolor = 0;
+	proc_data->overlay_state = 0;
+	proc_data->lut_transform = PXP_LUT_NONE;
+
+	/*
+	 * configure S0 channel parameters
+	 * Parameters should match FB format/width/height
+	 */
+	if (screeninfo->grayscale) {
+		pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY;
+		if (screeninfo->grayscale == GRAYSCALE_8BIT_INVERTED)
+			proc_data->lut_transform = PXP_LUT_INVERT;
+	} else {
+		switch (screeninfo->bits_per_pixel) {
+		case 16:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+			break;
+		case 24:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24;
+			break;
+		case 32:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32;
+			break;
+		default:
+			pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+			break;
+		}
+	}
+	pxp_conf->s0_param.width = screeninfo->xres;
+	pxp_conf->s0_param.height = screeninfo->yres;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/*
+	 * Initialize Output channel parameters
+	 * Output is Y-only greyscale
+	 * Output width/height will vary based on update region size
+	 */
+	pxp_conf->out_param.width = screeninfo->xres;
+	pxp_conf->out_param.height = screeninfo->yres;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+	/*
+	 * If HW not yet initialized, check to see if we are being sent
+	 * an initialization request.
+	 */
+	if (!fb_data->hw_ready) {
+		for (i = 0; i < NUM_PANELS; i++) {
+			/* Check resolution for a match with supported panel types */
+			if ((screeninfo->xres != panel_modes[i].xres) ||
+				(screeninfo->yres != panel_modes[i].yres))
+				continue;
+
+			/* Found a match - Grab timing params */
+			screeninfo->left_margin = panel_modes[i].left_margin;
+			screeninfo->right_margin = panel_modes[i].right_margin;
+			screeninfo->upper_margin = panel_modes[i].upper_margin;
+			screeninfo->lower_margin = panel_modes[i].lower_margin;
+			screeninfo->hsync_len = panel_modes[i].hsync_len;
+			screeninfo->vsync_len = panel_modes[i].vsync_len;
+
+			/* Initialize EPDC settings and init panel */
+			ret =
+			    mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+			if (ret) {
+				dev_err(fb_data->dev, "Failed to load panel waveform data\n");
+				return ret;
+			}
+
+			break;
+		}
+	}
+
+	mxc_epdc_fb_set_fix(info);
+
+	return 0;
+}
+
+static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var,
+				 struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	if (!var->xres)
+		var->xres = 1;
+	if (!var->yres)
+		var->yres = 1;
+
+	if (var->xres_virtual < var->xoffset + var->xres)
+		var->xres_virtual = var->xoffset + var->xres;
+	if (var->yres_virtual < var->yoffset + var->yres)
+		var->yres_virtual = var->yoffset + var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+		var->bits_per_pixel = default_bpp;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		if (var->grayscale != 0) {
+			/*
+			 * For 8-bit grayscale, R, G, and B offset are equal.
+			 *
+			 */
+			var->red.length = 8;
+			var->red.offset = 0;
+			var->red.msb_right = 0;
+
+			var->green.length = 8;
+			var->green.offset = 0;
+			var->green.msb_right = 0;
+
+			var->blue.length = 8;
+			var->blue.offset = 0;
+			var->blue.msb_right = 0;
+
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			var->transp.msb_right = 0;
+		} else {
+			var->red.length = 3;
+			var->red.offset = 5;
+			var->red.msb_right = 0;
+
+			var->green.length = 3;
+			var->green.offset = 2;
+			var->green.msb_right = 0;
+
+			var->blue.length = 2;
+			var->blue.offset = 0;
+			var->blue.msb_right = 0;
+
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			var->transp.msb_right = 0;
+		}
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	switch (var->rotate) {
+	case FB_ROTATE_UR:
+	case FB_ROTATE_UD:
+		var->xres = var->xres_virtual = fb_data->native_width;
+		var->yres = fb_data->native_height;
+		var->yres_virtual = var->yres * 2;
+		break;
+	case FB_ROTATE_CW:
+	case FB_ROTATE_CCW:
+		var->xres = var->xres_virtual = fb_data->native_height;
+		var->yres = fb_data->native_width;
+		var->yres_virtual = var->yres * 2;
+		break;
+	default:
+		/* Invalid rotation value */
+		var->rotate = 0;
+		dev_dbg(fb_data->dev, "Invalid rotation request\n");
+		return -EINVAL;
+	}
+
+	var->height = -1;
+	var->width = -1;
+
+	return 0;
+}
+
+static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp)
+{
+	int i;
+	int index = -1;
+
+	if (fb_data->trt_entries == 0) {
+		dev_err(fb_data->dev,
+			"No TRT exists...using default temp index\n");
+		return TEMP_USE_DEFAULT;
+	}
+
+	/* Search temperature ranges for a match */
+	for (i = 0; i < fb_data->trt_entries - 1; i++) {
+		if ((temp >= fb_data->temp_range_bounds[i])
+			&& (temp < fb_data->temp_range_bounds[i+1])) {
+			index = i;
+			break;
+		}
+	}
+
+	if (index < 0) {
+		dev_err(fb_data->dev,
+			"No TRT index match...using default temp index\n");
+		return TEMP_USE_DEFAULT;
+	}
+
+	dev_dbg(fb_data->dev, "Using temperature index %d\n", index);
+
+	return index;
+}
+
+static int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	int temp_index;
+
+	if (temperature != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature);
+		epdc_set_temp(temp_index);
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode);
+
+	if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+		|| (auto_mode == AUTO_UPDATE_MODE_REGION_MODE))
+		fb_data->auto_mode = auto_mode;
+	else {
+		dev_err(fb_data->dev, "Invalid auto update mode parameter.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
+				   struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct update_data_list *upd_data_list = NULL;
+	struct mxcfb_rect *screen_upd_region; /* Region on screen to update */
+	struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */
+	struct mxcfb_rect pxp_upd_region;
+	u32 src_width;
+	unsigned long flags;
+	int i;
+	u32 offset_from_8, bytes_per_pixel;
+	u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks;
+	u32 pxp_input_offs, pxp_output_offs, pxp_output_shift;
+	int adj_left, adj_top;
+	u32 hist_stat = 0;
+	int temp_index;
+	bool wait_for_power = false;
+
+	int ret;
+
+	/* Has EPDC HW been initialized? */
+	if (!fb_data->hw_ready) {
+		dev_err(fb_data->dev, "Display HW not properly initialized.  Aborting update.\n");
+		return -EPERM;
+	}
+
+	/* Check validity of update params */
+	if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) &&
+		(upd_data->update_mode != UPDATE_MODE_FULL)) {
+		dev_err(fb_data->dev,
+			"Update mode 0x%x is invalid.  Aborting update.\n",
+			upd_data->update_mode);
+		return -EINVAL;
+	}
+	if ((upd_data->waveform_mode > 255) &&
+		(upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) {
+		dev_err(fb_data->dev,
+			"Update waveform mode 0x%x is invalid.  Aborting update.\n",
+			upd_data->waveform_mode);
+		return -EINVAL;
+	}
+	if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->info.var.xres) ||
+		(upd_data->update_region.top + upd_data->update_region.height > fb_data->info.var.yres)) {
+		dev_err(fb_data->dev,
+			"Update region is outside bounds of framebuffer.  Aborting update.\n");
+		return -EINVAL;
+	}
+	if (upd_data->use_alt_buffer &&
+		((upd_data->update_region.width != upd_data->alt_buffer_data.alt_update_region.width) ||
+		(upd_data->update_region.height != upd_data->alt_buffer_data.alt_update_region.height))) {
+		dev_err(fb_data->dev,
+			"Alternate update region dimensions must match screen update region dimensions.\n");
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/*
+	 * If we are waiting to go into suspend, or the FB is blanked,
+	 * we do not accept new updates
+	 */
+	if ((fb_data->waiting_for_idle) || (fb_data->blank != FB_BLANK_UNBLANK)) {
+		dev_dbg(fb_data->dev, "EPDC not active.  Update request abort.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return -EPERM;
+	}
+
+	/*
+	 * Get available intermediate (PxP output) buffer to hold
+	 * processed update region
+	 */
+	if (list_empty(&fb_data->upd_buf_free_list->list)) {
+		dev_err(fb_data->dev, "No free intermediate buffers available.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return -ENOMEM;
+	}
+
+	/* Grab first available buffer and delete it from the free list */
+	upd_data_list =
+	    list_entry(fb_data->upd_buf_free_list->list.next,
+		       struct update_data_list, list);
+
+	list_del_init(&upd_data_list->list);
+
+	/*
+	 * We can release lock on queues now
+	 * that we have grabbed the one we need
+	 */
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	/* copy update parameters to the current update data object */
+	memcpy(&upd_data_list->upd_data, upd_data,
+	       sizeof(struct mxcfb_update_data));
+	memcpy(&upd_data_list->upd_data.update_region, &upd_data->update_region,
+	       sizeof(struct mxcfb_rect));
+
+	/*
+	 * Hold on to original screen update region, which we
+	 * will ultimately use when telling EPDC where to update on panel
+	 */
+	screen_upd_region = &upd_data_list->upd_data.update_region;
+
+	/*
+	 * Gotta do a whole bunch of buffer ptr manipulation to
+	 * work around HW restrictions for PxP & EPDC
+	 */
+
+	/*
+	 * Are we using FB or an alternate (overlay)
+	 * buffer for source of update?
+	 */
+	if (upd_data->use_alt_buffer) {
+		src_width = upd_data->alt_buffer_data.width;
+		src_upd_region = &upd_data->alt_buffer_data.alt_update_region;
+	} else {
+		src_width = fb_data->info.var.xres;
+		src_upd_region = screen_upd_region;
+	}
+
+	/*
+	 * Compute buffer offset to account for
+	 * PxP limitation (must read 8x8 pixel blocks)
+	 */
+	offset_from_8 = src_upd_region->left & 0x7;
+	bytes_per_pixel = fb_data->info.var.bits_per_pixel/8;
+	if ((offset_from_8 * fb_data->info.var.bits_per_pixel/8 % 4) != 0) {
+		/* Leave a gap between PxP input addr and update region pixels */
+		pxp_input_offs =
+			(src_upd_region->top * src_width + src_upd_region->left)
+			* bytes_per_pixel & 0xFFFFFFFC;
+		/* Update region should change to reflect relative position to input ptr */
+		pxp_upd_region.top = 0;
+		pxp_upd_region.left = (offset_from_8 & 0x3) % bytes_per_pixel;
+	} else {
+		pxp_input_offs =
+			(src_upd_region->top * src_width + src_upd_region->left)
+			* bytes_per_pixel;
+		/* Update region should change to reflect relative position to input ptr */
+		pxp_upd_region.top = 0;
+		pxp_upd_region.left = 0;
+	}
+
+	/* Update region to meet 8x8 pixel requirement */
+	adj_left = pxp_upd_region.left & 0x7;
+	adj_top = pxp_upd_region.top & 0x7;
+	pxp_upd_region.width = ALIGN(src_upd_region->width + adj_left, 8);
+	pxp_upd_region.height = ALIGN(src_upd_region->height + adj_top, 8);
+	pxp_upd_region.top &= ~0x7;
+	pxp_upd_region.left &= ~0x7;
+
+	switch (fb_data->info.var.rotate) {
+	case FB_ROTATE_UR:
+	default:
+		post_rotation_xcoord = pxp_upd_region.left;
+		post_rotation_ycoord = pxp_upd_region.top;
+		width_pxp_blocks = pxp_upd_region.width;
+		break;
+	case FB_ROTATE_CW:
+		width_pxp_blocks = pxp_upd_region.height;
+		post_rotation_xcoord = width_pxp_blocks - src_upd_region->height;
+		post_rotation_ycoord = pxp_upd_region.left;
+		break;
+	case FB_ROTATE_UD:
+		width_pxp_blocks = pxp_upd_region.width;
+		post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left;
+		post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top;
+		break;
+	case FB_ROTATE_CCW:
+		width_pxp_blocks = pxp_upd_region.height;
+		post_rotation_xcoord = pxp_upd_region.top;
+		post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left;
+		break;
+	}
+
+	pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
+		+ post_rotation_xcoord;
+
+	pxp_output_shift = ALIGN(pxp_output_offs, 8) - pxp_output_offs;
+
+	upd_data_list->epdc_offs = pxp_output_offs + pxp_output_shift;
+
+	/* Source address either comes from alternate buffer
+	   provided in update data, or from the framebuffer. */
+	if (upd_data->use_alt_buffer)
+		sg_dma_address(&fb_data->sg[0]) =
+			upd_data->alt_buffer_data.phys_addr + pxp_input_offs;
+	else {
+		sg_dma_address(&fb_data->sg[0]) =
+			fb_data->info.fix.smem_start + fb_data->fb_offset
+			+ pxp_input_offs;
+		sg_set_page(&fb_data->sg[0],
+			virt_to_page(fb_data->info.screen_base),
+			fb_data->info.fix.smem_len,
+			offset_in_page(fb_data->info.screen_base));
+	}
+
+	/* Update sg[1] to point to output of PxP proc task */
+	sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr + pxp_output_offs;
+	sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr),
+		    upd_data_list->size,
+		    offset_in_page(upd_data_list->virt_addr));
+
+	mutex_lock(&fb_data->pxp_mutex);
+
+	/* This is a blocking call, so upon return PxP tx should be done */
+	ret = pxp_process_update(fb_data, &pxp_upd_region);
+	if (ret) {
+		dev_err(fb_data->dev, "Unable to submit PxP update task.\n");
+		mutex_unlock(&fb_data->pxp_mutex);
+		return ret;
+	}
+
+	mutex_unlock(&fb_data->pxp_mutex);
+
+	/* If needed, enable EPDC HW while ePxP is processing */
+	if ((fb_data->power_state == POWER_STATE_OFF)
+		|| fb_data->powering_down) {
+		wait_for_power = true;
+		epdc_powerup(fb_data);
+	}
+
+	mutex_lock(&fb_data->pxp_mutex);
+
+	/* This is a blocking call, so upon return PxP tx should be done */
+	ret = pxp_complete_update(fb_data, &hist_stat);
+	if (ret) {
+		dev_err(fb_data->dev, "Unable to complete PxP update task.\n");
+		mutex_unlock(&fb_data->pxp_mutex);
+		return ret;
+	}
+
+	mutex_unlock(&fb_data->pxp_mutex);
+
+	/* Grab lock for queue manipulation and update submission */
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* Update coordinates for rotation */
+	adjust_coordinates(fb_data, &upd_data_list->upd_data.update_region);
+
+	/* Update waveform mode from PxP histogram results */
+	if (upd_data_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO) {
+		if (hist_stat & 0x1)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_du;
+		else if (hist_stat & 0x2)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc4;
+		else if (hist_stat & 0x4)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc8;
+		else if (hist_stat & 0x8)
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc16;
+		else
+			upd_data_list->upd_data.waveform_mode =
+				fb_data->wv_modes.mode_gc32;
+
+		/* Pass selected waveform mode back to user */
+		upd_data->waveform_mode = upd_data_list->upd_data.waveform_mode;
+
+		dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n",
+			hist_stat, upd_data_list->upd_data.waveform_mode);
+	}
+
+	/* If marker specified, associate it with a completion */
+	if (upd_data->update_marker != 0) {
+		/* Find available update marker and set it up */
+		for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+			/* Marker value set to 0 signifies it is not currently in use */
+			if (fb_data->update_marker_array[i].update_marker == 0) {
+				fb_data->update_marker_array[i].update_marker = upd_data->update_marker;
+				init_completion(&fb_data->update_marker_array[i].update_completion);
+				upd_data_list->upd_marker_data = &fb_data->update_marker_array[i];
+				break;
+			}
+		}
+	} else {
+		if (upd_data_list->upd_marker_data)
+			upd_data_list->upd_marker_data->update_marker = 0;
+	}
+
+	upd_data_list->is_collision = false;
+
+	/*
+	 * Is the working buffer idle?
+	 * If either the working buffer is busy, or there are no LUTs available,
+	 * then we return and let the ISR handle the update later
+	 */
+	if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) {
+		/* Add processed Y buffer to update list */
+		list_add_tail(&upd_data_list->list,
+			      &fb_data->upd_buf_queue->list);
+
+		/* Return and allow the udpate to be submitted by the ISR. */
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return 0;
+	}
+
+	/* Save current update */
+	fb_data->cur_update = upd_data_list;
+
+	/* LUTs are available, so we get one here */
+	upd_data_list->lut_num = epdc_get_next_lut();
+
+	/* Associate LUT with update marker */
+	if (upd_data_list->upd_marker_data)
+		if (upd_data_list->upd_marker_data->update_marker != 0)
+			upd_data_list->upd_marker_data->lut_num = upd_data_list->lut_num;
+
+	/* Mark LUT as containing new update */
+	fb_data->lut_update_type[upd_data_list->lut_num] = LUT_UPDATE_NEW;
+
+	/* Clear status and Enable LUT complete and WB complete IRQs */
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_addr(upd_data_list->phys_addr + upd_data_list->epdc_offs);
+	epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top);
+	epdc_set_update_dimensions(screen_upd_region->width, screen_upd_region->height);
+	if (upd_data_list->upd_data.temp != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, upd_data_list->upd_data.temp);
+		epdc_set_temp(temp_index);
+	}
+	epdc_submit_update(upd_data_list->lut_num,
+			   upd_data_list->upd_data.waveform_mode,
+			   upd_data_list->upd_data.update_mode, false, 0);
+
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	return 0;
+}
+
+static int mxc_epdc_fb_wait_update_complete(u32 update_marker,
+					    struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	int ret;
+	int i;
+
+	/* 0 is an invalid update_marker value */
+	if (update_marker == 0)
+		return -EINVAL;
+
+	/* Wait for completion associated with update_marker requested */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		if (fb_data->update_marker_array[i].update_marker == update_marker) {
+			dev_dbg(fb_data->dev, "Waiting for marker %d\n", update_marker);
+			ret = wait_for_completion_timeout(&fb_data->update_marker_array[i].update_completion, msecs_to_jiffies(5000));
+			if (!ret)
+				dev_err(fb_data->dev, "Timed out waiting for update completion\n");
+
+			dev_dbg(fb_data->dev, "marker %d signalled!\n", update_marker);
+
+			/* Reset marker so it can be reused */
+			fb_data->update_marker_array[i].update_marker = 0;
+
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			     unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct mxcfb_waveform_modes modes;
+	int temperature;
+	u32 auto_mode = 0;
+	struct mxcfb_update_data upd_data;
+	u32 update_marker = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case MXCFB_SET_WAVEFORM_MODES:
+		if (!copy_from_user(&modes, argp, sizeof(modes))) {
+			memcpy(&fb_data->wv_modes, &modes, sizeof(modes));
+			ret = 0;
+		}
+		break;
+	case MXCFB_SET_TEMPERATURE:
+		if (!get_user(temperature, (int32_t __user *) arg))
+			ret =
+			    mxc_epdc_fb_set_temperature(temperature,
+							info);
+		break;
+	case MXCFB_SET_AUTO_UPDATE_MODE:
+		if (!get_user(auto_mode, (__u32 __user *) arg))
+			ret =
+			    mxc_epdc_fb_set_auto_update(auto_mode, info);
+		break;
+	case MXCFB_SEND_UPDATE:
+		if (!copy_from_user(&upd_data, argp, sizeof(upd_data))) {
+			ret = mxc_epdc_fb_send_update(&upd_data, info);
+			if (ret == 0 && copy_to_user(argp, &upd_data, sizeof(upd_data)))
+				ret = -EFAULT;
+		} else {
+			ret = -EFAULT;
+		}
+
+		break;
+	case MXCFB_WAIT_FOR_UPDATE_COMPLETE:
+		if (!get_user(update_marker, (__u32 __user *) arg))
+			ret =
+			    mxc_epdc_fb_wait_update_complete(update_marker,
+							     info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data,
+				     u16 y1, u16 y2)
+{
+	struct mxcfb_update_data update;
+
+	/* Do partial screen update, Update full horizontal lines */
+	update.update_region.left = 0;
+	update.update_region.width = fb_data->info.var.xres;
+	update.update_region.top = y1;
+	update.update_region.height = y2 - y1;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.update_marker = 0;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, &fb_data->info);
+}
+
+/* this is called back from the deferred io workqueue */
+static void mxc_epdc_fb_deferred_io(struct fb_info *info,
+				    struct list_head *pagelist)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct page *page;
+	unsigned long beg, end;
+	int y1, y2, miny, maxy;
+
+	if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+		return;
+
+	miny = INT_MAX;
+	maxy = 0;
+	list_for_each_entry(page, pagelist, lru) {
+		beg = page->index << PAGE_SHIFT;
+		end = beg + PAGE_SIZE - 1;
+		y1 = beg / info->fix.line_length;
+		y2 = end / info->fix.line_length;
+		if (y2 >= info->var.yres)
+			y2 = info->var.yres - 1;
+		if (miny > y1)
+			miny = y1;
+		if (maxy < y2)
+			maxy = y2;
+	}
+
+	mxc_epdc_fb_update_pages(fb_data, miny, maxy);
+}
+
+static void mxc_epdc_fb_disable(struct mxc_epdc_fb_data *fb_data)
+{
+	unsigned long flags;
+	/* Grab queue lock to prevent any new updates from being submitted */
+
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* If any updates in flight, we must wait for them to complete */
+	if (!(list_empty(&fb_data->upd_buf_collision_list->list) &&
+		list_empty(&fb_data->upd_buf_queue->list) &&
+		(fb_data->cur_update == NULL))) {
+		/* Initialize event signalling updates are done */
+		init_completion(&fb_data->updates_done);
+		fb_data->waiting_for_idle = true;
+
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		/* Wait for any currently active updates to complete */
+		wait_for_completion_timeout(&fb_data->updates_done, msecs_to_jiffies(2000));
+		spin_lock_irqsave(&fb_data->queue_lock, flags);
+		fb_data->waiting_for_idle = false;
+	}
+
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+}
+
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	dev_dbg(fb_data->dev, "blank = %d\n", blank);
+
+	if (fb_data->blank == blank)
+		return 0;
+
+	fb_data->blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		mxc_epdc_fb_disable(fb_data);
+		break;
+	}
+	return 0;
+}
+
+static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var,
+				   struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	struct mxcfb_update_data update;
+	int ret = 0;
+	u_int y_bottom;
+
+	dev_dbg(info->device, "%s: var->xoffset %d, info->var.xoffset %d\n",
+		 __func__, var->xoffset, info->var.xoffset);
+	/* check if var is valid; also, xpan is not supported */
+	if (!var || (var->xoffset != info->var.xoffset) ||
+	    (var->yoffset + var->yres > var->yres_virtual)) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((info->var.xoffset == var->xoffset) &&
+	    (info->var.yoffset == var->yoffset))
+		return 0;	/* No change, do nothing */
+
+	y_bottom = var->yoffset;
+
+	if (!(var->vmode & FB_VMODE_YWRAP))
+		y_bottom += var->yres;
+
+	if (y_bottom > info->var.yres_virtual)
+		return -EINVAL;
+
+	fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset)
+		* (var->bits_per_pixel) / 8;
+
+	/* Update to new view of FB */
+	update.update_region.left = 0;
+	update.update_region.width = fb_data->info.var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = fb_data->info.var.yres;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.update_marker = PAN_UPDATE_MARKER;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, &fb_data->info);
+
+	/* Block on initial update */
+	ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+	if (ret < 0)
+		dev_err(fb_data->dev,
+			"Wait for update complete failed.  Error = 0x%x", ret);
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	if (var->vmode & FB_VMODE_YWRAP)
+		info->var.vmode |= FB_VMODE_YWRAP;
+	else
+		info->var.vmode &= ~FB_VMODE_YWRAP;
+
+	return ret;
+}
+
+static struct fb_ops mxc_epdc_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mxc_epdc_fb_check_var,
+	.fb_set_par = mxc_epdc_fb_set_par,
+	.fb_setcolreg = mxc_epdc_fb_setcolreg,
+	.fb_pan_display = mxc_epdc_fb_pan_display,
+	.fb_ioctl = mxc_epdc_fb_ioctl,
+	.fb_mmap = mxc_epdc_fb_mmap,
+	.fb_blank = mxc_epdc_fb_blank,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_deferred_io mxc_epdc_fb_defio = {
+	.delay = HZ / 2,
+	.deferred_io = mxc_epdc_fb_deferred_io,
+};
+
+static void epdc_done_work_func(struct work_struct *work)
+{
+	struct mxc_epdc_fb_data *fb_data =
+		container_of(work, struct mxc_epdc_fb_data, epdc_done_work);
+	epdc_powerdown(fb_data);
+}
+
+static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data)
+{
+	int count = 0;
+	struct update_data_list *plist;
+
+	/* Count buffers in free buffer list */
+	list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list)
+		count++;
+
+	/* Check to see if all buffers are in this list */
+	if (count == EPDC_MAX_NUM_UPDATES)
+		return true;
+	else
+		return false;
+}
+
+static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id)
+{
+	struct mxc_epdc_fb_data *fb_data = dev_id;
+	struct update_data_list *collision_update;
+	struct mxcfb_rect *next_upd_region;
+	unsigned long flags;
+	int temp_index;
+	u32 luts_completed_mask;
+	u32 temp_mask;
+	u32 lut;
+	bool ignore_collision = false;
+	int i, j;
+
+	/*
+	 * If we just completed one-time panel init, bypass
+	 * queue handling, clear interrupt and return
+	 */
+	if (fb_data->in_init) {
+		if (epdc_is_working_buffer_complete()) {
+			epdc_working_buf_intr(false);
+			epdc_clear_working_buf_irq();
+			dev_dbg(fb_data->dev, "Cleared WB for init update\n");
+		}
+
+		if (epdc_is_lut_complete(0)) {
+			epdc_lut_complete_intr(0, false);
+			epdc_clear_lut_complete_irq(0);
+			fb_data->in_init = false;
+			dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n");
+		}
+
+		return IRQ_HANDLED;
+	}
+
+	if (!(__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)))
+		return IRQ_HANDLED;
+
+	if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) {
+		dev_err(fb_data->dev, "TCE underrun!  Panel may lock up.\n");
+		return IRQ_HANDLED;
+	}
+
+	/* Protect access to buffer queues and to update HW */
+	spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+	/* Free any LUTs that have completed */
+	luts_completed_mask = 0;
+	for (i = 0; i < EPDC_NUM_LUTS; i++) {
+		if (!epdc_is_lut_complete(i))
+			continue;
+
+		dev_dbg(fb_data->dev, "\nLUT %d completed\n", i);
+
+		/* Disable IRQ for completed LUT */
+		epdc_lut_complete_intr(i, false);
+
+		/*
+		 * Go through all updates in the collision list and
+		 * unmask any updates that were colliding with
+		 * the completed LUT.
+		 */
+		list_for_each_entry(collision_update,
+				    &fb_data->upd_buf_collision_list->
+				    list, list) {
+			collision_update->collision_mask =
+			    collision_update->collision_mask & ~(1 << i);
+		}
+
+		epdc_clear_lut_complete_irq(i);
+
+		luts_completed_mask |= 1 << i;
+
+		fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+		/* Signal completion if anyone waiting on this LUT */
+		for (j = 0; j < EPDC_MAX_NUM_UPDATES; j++) {
+			if (fb_data->update_marker_array[j].lut_num != i)
+				continue;
+
+			/* Signal completion of update */
+			dev_dbg(fb_data->dev,
+				"Signaling marker %d\n",
+				fb_data->update_marker_array[j].update_marker);
+			complete(&fb_data->update_marker_array[j].update_completion);
+			/* Ensure this doesn't get signaled again inadvertently */
+			fb_data->update_marker_array[j].lut_num = INVALID_LUT;
+		}
+	}
+
+	/* Check to see if all updates have completed */
+	if (is_free_list_full(fb_data) &&
+		(fb_data->cur_update == NULL) &&
+		!epdc_any_luts_active()) {
+
+#ifndef NO_POWERDOWN
+		/*
+		 * Set variable to prevent overlapping
+		  * enable/disable requests
+		  */
+		fb_data->powering_down = true;
+
+		/* Schedule task to disable EPDC HW until next update */
+		schedule_work(&fb_data->epdc_done_work);
+#endif
+
+		if (fb_data->waiting_for_idle)
+			complete(&fb_data->updates_done);
+	}
+
+	/* Is Working Buffer busy? */
+	if (epdc_is_working_buffer_busy()) {
+		/* Can't submit another update until WB is done */
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Were we waiting on working buffer?
+	 * If so, update queues and check for collisions
+	 */
+	if (fb_data->cur_update != NULL) {
+		dev_dbg(fb_data->dev, "\nWorking buffer completed\n");
+
+		/* Was there a collision? */
+		if (epdc_is_collision()) {
+			/* Check list of colliding LUTs, and add to our collision mask */
+			fb_data->cur_update->collision_mask =
+			    epdc_get_colliding_luts();
+
+			dev_dbg(fb_data->dev, "\nCollision mask = 0x%x\n",
+			       epdc_get_colliding_luts());
+
+			/* Clear collisions that just completed */
+			fb_data->cur_update->collision_mask &= ~luts_completed_mask;
+
+			/*
+			 * If this is a re-collision, AND we re-collide
+			 * with only new updates, then we don't want
+			 * to re-submit it again.
+			 */
+			if (fb_data->cur_update->is_collision) {
+				/*
+				 * Check whether collided LUTs are
+				 * new updates or resubmitted collisions
+				 */
+				temp_mask = fb_data->cur_update->collision_mask;
+				lut = 0;
+				while (temp_mask != 0) {
+					if ((temp_mask & 0x1) &&
+						(fb_data->lut_update_type[lut] == LUT_UPDATE_NEW)) {
+						dev_dbg(fb_data->dev, "Ignoring collision with new update.\n");
+						ignore_collision = true;
+						break;
+					}
+					lut++;
+					temp_mask = temp_mask >> 1;
+				}
+			}
+
+			if (ignore_collision) {
+				/* Add to free buffer list */
+				list_add_tail(&fb_data->cur_update->list,
+					 &fb_data->upd_buf_free_list->list);
+			} else {
+				/*
+				 * If update has a marker, clear the LUT, since we
+				 * don't want to signal that it is complete.
+				 */
+				if (fb_data->cur_update->upd_marker_data)
+					if (fb_data->cur_update->upd_marker_data->update_marker != 0)
+						fb_data->cur_update->upd_marker_data->lut_num = INVALID_LUT;
+
+				fb_data->cur_update->is_collision = true;
+
+				/* Move to collision list */
+				list_add_tail(&fb_data->cur_update->list,
+					 &fb_data->upd_buf_collision_list->list);
+			}
+		} else {
+			/* Add to free buffer list */
+			list_add_tail(&fb_data->cur_update->list,
+				 &fb_data->upd_buf_free_list->list);
+		}
+		/* Clear current update */
+		fb_data->cur_update = NULL;
+
+		/* Clear IRQ for working buffer */
+		epdc_working_buf_intr(false);
+		epdc_clear_working_buf_irq();
+	}
+
+	/* Check to see if any LUTs are free */
+	if (!epdc_any_luts_available()) {
+		dev_dbg(fb_data->dev, "No luts available.\n");
+		spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Are any of our collision updates able to go now?
+	 * Go through all updates in the collision list and check to see
+	 * if the collision mask has been fully cleared
+	 */
+	list_for_each_entry(collision_update,
+			    &fb_data->upd_buf_collision_list->list, list) {
+
+		if (collision_update->collision_mask != 0)
+			continue;
+
+		dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
+		/*
+		 * We have a collision cleared, so select it
+		 * and we will retry the update
+		 */
+		fb_data->cur_update = collision_update;
+		list_del_init(&fb_data->cur_update->list);
+		break;
+	}
+
+	/*
+	 * If we didn't find a collision update ready to go,
+	 * we try to grab one from the update queue
+	 */
+	if (fb_data->cur_update == NULL) {
+		/* Is update list empty? */
+		if (list_empty(&fb_data->upd_buf_queue->list)) {
+			dev_dbg(fb_data->dev, "No pending updates.\n");
+
+			/* No updates pending, so we are done */
+			spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+			return IRQ_HANDLED;
+		} else {
+			dev_dbg(fb_data->dev, "Found a pending update!\n");
+
+			/* Process next item in update list */
+			fb_data->cur_update =
+			    list_entry(fb_data->upd_buf_queue->list.next,
+				       struct update_data_list, list);
+			list_del_init(&fb_data->cur_update->list);
+		}
+	}
+
+	/* LUTs are available, so we get one here */
+	fb_data->cur_update->lut_num = epdc_get_next_lut();
+
+	/* Associate LUT with update marker */
+	if ((fb_data->cur_update->upd_marker_data)
+		&& (fb_data->cur_update->upd_marker_data->update_marker != 0))
+		fb_data->cur_update->upd_marker_data->lut_num =
+						fb_data->cur_update->lut_num;
+
+	/* Mark LUT as containing new update */
+	if (fb_data->cur_update->is_collision)
+		fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_COLLISION;
+	else
+		fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_NEW;
+
+	/* Enable Collision and WB complete IRQs */
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+	/* Program EPDC update to process buffer */
+	next_upd_region = &fb_data->cur_update->upd_data.update_region;
+	if (fb_data->cur_update->upd_data.temp != TEMP_USE_AMBIENT) {
+		temp_index = mxc_epdc_fb_get_temp_index(fb_data, fb_data->cur_update->upd_data.temp);
+		epdc_set_temp(temp_index);
+	}
+	epdc_set_update_addr(fb_data->cur_update->phys_addr + fb_data->cur_update->epdc_offs);
+	epdc_set_update_coord(next_upd_region->left, next_upd_region->top);
+	epdc_set_update_dimensions(next_upd_region->width,
+				   next_upd_region->height);
+	epdc_submit_update(fb_data->cur_update->lut_num,
+			   fb_data->cur_update->upd_data.waveform_mode,
+			   fb_data->cur_update->upd_data.update_mode, false, 0);
+
+	/* Release buffer queues */
+	spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data)
+{
+	u32 *upd_buf_ptr;
+	int i;
+
+	upd_buf_ptr = (u32 *)fb_data->info.screen_base;
+
+	epdc_working_buf_intr(true);
+	epdc_lut_complete_intr(0, true);
+	fb_data->in_init = true;
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_addr(fb_data->phys_start);
+	epdc_set_update_coord(0, 0);
+	epdc_set_update_dimensions(fb_data->info.var.xres,
+				   fb_data->info.var.yres);
+	epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL, true, 0xFF);
+
+	dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n");
+
+	/* Will timeout after ~4-5 seconds */
+
+	for (i = 0; i < 40; i++) {
+		if (!epdc_is_lut_active(0)) {
+			dev_dbg(fb_data->dev, "Mode0 init complete\n");
+			return;
+		}
+		msleep(100);
+	}
+
+	dev_err(fb_data->dev, "Mode0 init failed!\n");
+
+	return;
+}
+
+static int mxc_epdc_fb_init_hw(struct fb_info *info)
+{
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+	const struct firmware *fw;
+	struct mxcfb_update_data update;
+	struct mxcfb_waveform_data_file *wv_file;
+	int wv_data_offs;
+	int ret;
+	int i;
+
+	ret = request_firmware(&fw, "imx/epdc.fw", fb_data->dev);
+	if (ret) {
+		printk(KERN_ERR "Failed to load image imx/epdc.ihex err %d\n",
+		       ret);
+		return ret;
+	}
+
+	wv_file = (struct mxcfb_waveform_data_file *)fw->data;
+
+	/* Get size and allocate temperature range table */
+	fb_data->trt_entries = wv_file->wdh.trc + 1;
+	fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL);
+
+	for (i = 0; i < fb_data->trt_entries; i++)
+		dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i));
+
+	/* Copy TRT data */
+	memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries);
+
+	/* Get offset and size for waveform data */
+	wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1;
+	fb_data->waveform_buffer_size = fw->size - wv_data_offs;
+
+	/* Allocate memory for waveform data */
+	fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev,
+						fb_data->waveform_buffer_size,
+						  &fb_data->waveform_buffer_phys,
+						  GFP_DMA);
+	if (fb_data->waveform_buffer_virt == NULL) {
+		dev_err(fb_data->dev, "Can't allocate mem for waveform!\n");
+		ret = -ENOMEM;
+	}
+
+	memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs,
+		fb_data->waveform_buffer_size);
+
+	release_firmware(fw);
+
+	/* Enable clocks to access EPDC regs */
+	clk_enable(fb_data->epdc_clk_axi);
+
+	/* Enable pix clk for EPDC */
+	clk_enable(fb_data->epdc_clk_pix);
+	clk_set_rate(fb_data->epdc_clk_pix, 20000000);
+
+	epdc_init_sequence(fb_data);
+
+	/* Enable clocks to access EPDC regs */
+	clk_disable(fb_data->epdc_clk_axi);
+	clk_disable(fb_data->epdc_clk_pix);
+
+	fb_data->hw_ready = true;
+
+	update.update_region.left = 0;
+	update.update_region.width = info->var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = info->var.yres;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.waveform_mode = WAVEFORM_MODE_AUTO;
+	update.update_marker = INIT_UPDATE_MARKER;
+	update.temp = TEMP_USE_AMBIENT;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, info);
+
+	/* Block on initial update */
+	ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+	if (ret < 0)
+		dev_err(fb_data->dev,
+			"Wait for update complete failed.  Error = 0x%x", ret);
+
+	return 0;
+}
+
+static ssize_t store_update(struct device *device,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct mxcfb_update_data update;
+	struct fb_info *info = dev_get_drvdata(device);
+	struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+	if (strncmp(buf, "direct", 6) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_du;
+	else if (strncmp(buf, "gc16", 4) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_gc16;
+	else if (strncmp(buf, "gc4", 3) == 0)
+		update.waveform_mode = fb_data->wv_modes.mode_gc4;
+
+	/* Now, request full screen update */
+	update.update_region.left = 0;
+	update.update_region.width = info->var.xres;
+	update.update_region.top = 0;
+	update.update_region.height = info->var.yres;
+	update.update_mode = UPDATE_MODE_FULL;
+	update.temp = TEMP_USE_AMBIENT;
+	update.update_marker = 0;
+	update.use_alt_buffer = false;
+
+	mxc_epdc_fb_send_update(&update, info);
+
+	return count;
+}
+
+static struct device_attribute fb_attrs[] = {
+	__ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update),
+};
+
+int __devinit mxc_epdc_fb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_epdc_fb_data *fb_data;
+	struct resource *res;
+	struct fb_info *info;
+	struct mxc_epdc_platform_fb_data *pdata;
+	struct mxc_epdc_platform_fb_entry *pentry;
+	struct pxp_config_data *pxp_conf;
+	struct pxp_proc_data *proc_data;
+	struct scatterlist *sg;
+	struct update_data_list *upd_list;
+	struct update_data_list *plist, *temp_list;
+	int i;
+
+	fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc(
+			sizeof(struct mxc_epdc_fb_data), &pdev->dev);
+	if (fb_data == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	fb_data->dev = &pdev->dev;
+	/* We want to use hard-coded structure defined in this file */
+	pentry = &ed060sc4_fb_entry;
+	fb_data->cur = pentry;
+	platform_set_drvdata(pdev, fb_data);
+	info = &fb_data->info;
+
+	/* Allocate color map for the FB */
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret)
+		goto out_fbdata;
+
+	dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", pentry->x_res,
+		pentry->y_res, pentry->bpp);
+
+	fb_data->mem_size = pentry->x_res * pentry->y_res * pentry->bpp/8;
+
+	fb_data->map_size = PAGE_ALIGN(fb_data->mem_size) * NUM_SCREENS;
+	dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENODEV;
+		goto out_cmap;
+	}
+
+	epdc_base = ioremap(res->start, SZ_4K);
+	if (epdc_base == NULL) {
+		ret = -ENOMEM;
+		goto out_cmap;
+	}
+
+	/* Allocate FB memory */
+	info->screen_base = dma_alloc_writecombine(&pdev->dev,
+						  fb_data->map_size,
+						  &fb_data->phys_start,
+						  GFP_KERNEL);
+
+	if (info->screen_base == NULL) {
+		ret = -ENOMEM;
+		goto out_mapregs;
+	}
+	dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base,
+		fb_data->phys_start);
+
+	mxc_epdc_fb_default.bits_per_pixel = pentry->bpp;
+	mxc_epdc_fb_default.xres = pentry->x_res;
+	mxc_epdc_fb_default.yres = pentry->y_res;
+	mxc_epdc_fb_default.xres_virtual = pentry->x_res;
+	/* Additional screens allow for panning  and buffer flipping */
+	mxc_epdc_fb_default.yres_virtual = pentry->y_res * NUM_SCREENS;
+
+	mxc_epdc_fb_fix.smem_start = fb_data->phys_start;
+	mxc_epdc_fb_fix.smem_len = fb_data->map_size;
+	mxc_epdc_fb_fix.ypanstep = 0;
+
+	switch (pentry->bpp) {
+	case 32:
+	case 24:
+		mxc_epdc_fb_default.red.offset = 16;
+		mxc_epdc_fb_default.red.length = 8;
+		mxc_epdc_fb_default.green.offset = 8;
+		mxc_epdc_fb_default.green.length = 8;
+		mxc_epdc_fb_default.blue.offset = 0;
+		mxc_epdc_fb_default.blue.length = 8;
+		break;
+
+	case 16:
+		mxc_epdc_fb_default.red.offset = 11;
+		mxc_epdc_fb_default.red.length = 5;
+		mxc_epdc_fb_default.green.offset = 5;
+		mxc_epdc_fb_default.green.length = 6;
+		mxc_epdc_fb_default.blue.offset = 0;
+		mxc_epdc_fb_default.blue.length = 5;
+		break;
+
+	default:
+		dev_err(&pdev->dev, "unsupported bitwidth %d\n", pentry->bpp);
+		ret = -EINVAL;
+		goto out_dma_fb;
+	}
+
+	fb_data->native_width = pentry->x_res;
+	fb_data->native_height = pentry->y_res;
+
+	info->fbops = &mxc_epdc_fb_ops;
+	info->var = mxc_epdc_fb_default;
+	info->fix = mxc_epdc_fb_fix;
+	info->var.activate = FB_ACTIVATE_NOW;
+	info->pseudo_palette = fb_data->pseudo_palette;
+	info->screen_size = info->fix.smem_len;
+	fb_data->par = NULL;
+	info->flags = FBINFO_FLAG_DEFAULT;
+
+	mxc_epdc_fb_set_fix(info);
+
+	fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE;
+
+	init_waitqueue_head(&fb_data->vsync_wait_q);
+	fb_data->vsync_count = 0;
+
+	fb_data->fb_offset = 0;
+
+	/* Allocate head objects for our lists */
+	fb_data->upd_buf_queue =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	fb_data->upd_buf_collision_list =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	fb_data->upd_buf_free_list =
+	    kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+	if ((fb_data->upd_buf_queue == NULL) || (fb_data->upd_buf_free_list == NULL)
+	    || (fb_data->upd_buf_collision_list == NULL)) {
+		ret = -ENOMEM;
+		goto out_dma_fb;
+	}
+
+	/*
+	 * Initialize lists for update requests, update collisions,
+	 * and available update (PxP output) buffers
+	 */
+	INIT_LIST_HEAD(&fb_data->upd_buf_queue->list);
+	INIT_LIST_HEAD(&fb_data->upd_buf_free_list->list);
+	INIT_LIST_HEAD(&fb_data->upd_buf_collision_list->list);
+
+	/* Allocate update buffers and add them to the list */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL);
+		if (upd_list == NULL) {
+			ret = -ENOMEM;
+			goto out_upd_buffers;
+		}
+
+		/* Clear update data structure */
+		memset(&upd_list->upd_data, 0,
+		       sizeof(struct mxcfb_update_data));
+
+		/*
+		 * Each update buffer is 1 byte per pixel, and can
+		 * be as big as the full-screen frame buffer
+		 */
+		upd_list->size = info->var.xres * info->var.yres;
+
+		/* Allocate memory for PxP output buffer */
+		upd_list->virt_addr =
+		    dma_alloc_coherent(fb_data->info.device, upd_list->size,
+				       &upd_list->phys_addr, GFP_DMA);
+		if (upd_list->virt_addr == NULL) {
+			kfree(upd_list);
+			ret = -ENOMEM;
+			goto out_upd_buffers;
+		}
+
+		/* Add newly allocated buffer to free list */
+		list_add(&upd_list->list, &fb_data->upd_buf_free_list->list);
+
+		dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n",
+			upd_list->size, upd_list->phys_addr);
+	}
+
+	fb_data->working_buffer_size = pentry->y_res * pentry->x_res * 2;
+	/* Allocate memory for EPDC working buffer */
+	fb_data->working_buffer_virt =
+	    dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size,
+			       &fb_data->working_buffer_phys, GFP_DMA);
+	if (fb_data->working_buffer_virt == NULL) {
+		dev_err(&pdev->dev, "Can't allocate mem for working buf!\n");
+		ret = -ENOMEM;
+		goto out_upd_buffers;
+	}
+
+	fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi");
+	fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix");
+
+	fb_data->in_init = false;
+
+	fb_data->hw_ready = false;
+
+	/*
+	 * Set default waveform mode values.
+	 * Should be overwritten via ioctl.
+	 */
+	fb_data->wv_modes.mode_init = 0;
+	fb_data->wv_modes.mode_du = 1;
+	fb_data->wv_modes.mode_gc4 = 3;
+	fb_data->wv_modes.mode_gc8 = 2;
+	fb_data->wv_modes.mode_gc16 = 2;
+	fb_data->wv_modes.mode_gc32 = 2;
+
+	/* Initialize markers */
+	for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+		fb_data->update_marker_array[i].update_marker = 0;
+		fb_data->update_marker_array[i].lut_num = INVALID_LUT;
+	}
+
+	/* Initialize all LUTs to inactive */
+	for (i = 0; i < EPDC_NUM_LUTS; i++)
+		fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+	/* Retrieve EPDC IRQ num */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma_work_buf;
+	}
+	fb_data->epdc_irq = res->start;
+
+	/* Register IRQ handler */
+	ret = request_irq(fb_data->epdc_irq, mxc_epdc_irq_handler, 0,
+			"fb_dma", fb_data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+			fb_data->epdc_irq, ret);
+		ret = -ENODEV;
+		goto out_dma_work_buf;
+	}
+
+	INIT_WORK(&fb_data->epdc_done_work, epdc_done_work_func);
+
+	info->fbdefio = &mxc_epdc_fb_defio;
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+	fb_deferred_io_init(info);
+#endif
+
+	/* get pmic regulators */
+	fb_data->display_regulator = regulator_get(NULL, "DISPLAY");
+	if (IS_ERR(fb_data->display_regulator)) {
+		dev_err(&pdev->dev, "Unable to get display PMIC regulator."
+			"err = 0x%x\n", fb_data->display_regulator);
+		ret = -ENODEV;
+		goto out_dma_work_buf;
+	}
+	fb_data->vcom_regulator = regulator_get(NULL, "VCOM");
+	if (IS_ERR(fb_data->vcom_regulator)) {
+		regulator_put(fb_data->display_regulator);
+		dev_err(&pdev->dev, "Unable to get VCOM regulator."
+			"err = 0x%x\n", fb_data->vcom_regulator);
+		ret = -ENODEV;
+		goto out_dma_work_buf;
+	}
+
+	if (device_create_file(info->dev, &fb_attrs[0]))
+		dev_err(&pdev->dev, "Unable to create file from fb_attrs\n");
+
+	fb_data->cur_update = NULL;
+
+	spin_lock_init(&fb_data->queue_lock);
+
+	mutex_init(&fb_data->pxp_mutex);
+
+	mutex_init(&fb_data->power_mutex);
+
+	/* PxP DMA interface */
+	dmaengine_get();
+
+	/*
+	 * Fill out PxP config data structure based on FB info and
+	 * processing tasks required
+	 */
+	pxp_conf = &fb_data->pxp_conf;
+	proc_data = &pxp_conf->proc_data;
+
+	/* Initialize non-channel-specific PxP parameters */
+	proc_data->drect.left = proc_data->srect.left = 0;
+	proc_data->drect.top = proc_data->srect.top = 0;
+	proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres;
+	proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres;
+	proc_data->scaling = 0;
+	proc_data->hflip = 0;
+	proc_data->vflip = 0;
+	proc_data->rotate = 0;
+	proc_data->bgcolor = 0;
+	proc_data->overlay_state = 0;
+	proc_data->lut_transform = PXP_LUT_NONE;
+
+	/*
+	 * We initially configure PxP for RGB->YUV conversion,
+	 * and only write out Y component of the result.
+	 */
+
+	/*
+	 * Initialize S0 channel parameters
+	 * Parameters should match FB format/width/height
+	 */
+	pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+	pxp_conf->s0_param.width = fb_data->info.var.xres;
+	pxp_conf->s0_param.height = fb_data->info.var.yres;
+	pxp_conf->s0_param.color_key = -1;
+	pxp_conf->s0_param.color_key_enable = false;
+
+	/*
+	 * Initialize OL0 channel parameters
+	 * No overlay will be used for PxP operation
+	 */
+	 for (i = 0; i < 8; i++) {
+		pxp_conf->ol_param[i].combine_enable = false;
+		pxp_conf->ol_param[i].width = 0;
+		pxp_conf->ol_param[i].height = 0;
+		pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
+		pxp_conf->ol_param[i].color_key_enable = false;
+		pxp_conf->ol_param[i].color_key = -1;
+		pxp_conf->ol_param[i].global_alpha_enable = false;
+		pxp_conf->ol_param[i].global_alpha = 0;
+		pxp_conf->ol_param[i].local_alpha_enable = false;
+	}
+
+	/*
+	 * Initialize Output channel parameters
+	 * Output is Y-only greyscale
+	 * Output width/height will vary based on update region size
+	 */
+	pxp_conf->out_param.width = fb_data->info.var.xres;
+	pxp_conf->out_param.height = fb_data->info.var.yres;
+	pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+	/*
+	 * Ensure this is set to NULL here...we will initialize pxp_chan
+	 * later in our thread.
+	 */
+	fb_data->pxp_chan = NULL;
+
+	/* Initialize Scatter-gather list containing 2 buffer addresses. */
+	sg = fb_data->sg;
+	sg_init_table(sg, 2);
+
+	/*
+	 * For use in PxP transfers:
+	 * sg[0] holds the FB buffer pointer
+	 * sg[1] holds the Output buffer pointer (configured before TX request)
+	 */
+	sg_dma_address(&sg[0]) = info->fix.smem_start;
+	sg_set_page(&sg[0], virt_to_page(info->screen_base),
+		    info->fix.smem_len, offset_in_page(info->screen_base));
+
+	fb_data->waiting_for_idle = false;
+	fb_data->blank = FB_BLANK_UNBLANK;
+	fb_data->power_state = POWER_STATE_OFF;
+	fb_data->powering_down = false;
+
+	/* Register FB */
+	ret = register_framebuffer(info);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"register_framebuffer failed with error %d\n", ret);
+		goto out_irq;
+	}
+
+#ifdef DEFAULT_PANEL_HW_INIT
+	ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to read firmware!\n");
+		goto out_dmaengine;
+	}
+#endif
+
+	goto out;
+
+out_dmaengine:
+	dmaengine_put();
+	unregister_framebuffer(&fb_data->info);
+out_irq:
+	free_irq(fb_data->epdc_irq, fb_data);
+out_dma_work_buf:
+	dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
+		fb_data->working_buffer_virt, fb_data->working_buffer_phys);
+out_upd_buffers:
+	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+		list_del(&plist->list);
+		dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+				      plist->phys_addr);
+		kfree(plist);
+	}
+out_dma_fb:
+	dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base,
+			      fb_data->phys_start);
+
+out_mapregs:
+	iounmap(epdc_base);
+out_cmap:
+	fb_dealloc_cmap(&info->cmap);
+out_fbdata:
+	kfree(fb_data);
+out:
+	return ret;
+}
+
+static int mxc_epdc_fb_remove(struct platform_device *pdev)
+{
+	struct update_data_list *plist, *temp_list;
+	struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
+
+	mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
+
+	regulator_put(fb_data->display_regulator);
+	regulator_put(fb_data->vcom_regulator);
+
+	unregister_framebuffer(&fb_data->info);
+	free_irq(fb_data->epdc_irq, fb_data);
+
+	dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
+				fb_data->working_buffer_virt,
+			      fb_data->working_buffer_phys);
+	if (fb_data->waveform_buffer_virt != NULL)
+		dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size,
+				fb_data->waveform_buffer_virt,
+			      fb_data->waveform_buffer_phys);
+	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+		list_del(&plist->list);
+		dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+				      plist->phys_addr);
+		kfree(plist);
+	}
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+	fb_deferred_io_cleanup(&fb_data->info);
+#endif
+
+	dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base,
+			      fb_data->phys_start);
+
+	/* Release PxP-related resources */
+	if (fb_data->pxp_chan != NULL)
+		dma_release_channel(&fb_data->pxp_chan->dma_chan);
+
+	dmaengine_put();
+
+	iounmap(epdc_base);
+
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+	fb_deferred_io_cleanup(&fb_data->info);
+#endif
+	fb_dealloc_cmap(&fb_data->info.cmap);
+
+	framebuffer_release(&fb_data->info);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_epdc_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int mxc_epdc_fb_resume(struct platform_device *pdev)
+{
+	struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+
+	mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
+	return 0;
+}
+#else
+#define mxc_epdc_fb_suspend	NULL
+#define mxc_epdc_fb_resume	NULL
+#endif
+
+static struct platform_driver mxc_epdc_fb_driver = {
+	.probe = mxc_epdc_fb_probe,
+	.remove = mxc_epdc_fb_remove,
+	.suspend = mxc_epdc_fb_suspend,
+	.resume = mxc_epdc_fb_resume,
+	.driver = {
+		   .name = "mxc_epdc_fb",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+/* Callback function triggered after PxP receives an EOF interrupt */
+static void pxp_dma_done(void *arg)
+{
+	struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
+	struct dma_chan *chan = tx_desc->txd.chan;
+	struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+	struct mxc_epdc_fb_data *fb_data = pxp_chan->client;
+
+	/* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */
+	complete(&fb_data->pxp_tx_cmpl);
+}
+
+/* Function to request PXP DMA channel */
+static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data)
+{
+	dma_cap_mask_t mask;
+	struct dma_chan *chan;
+
+	/*
+	 * Request a free channel
+	 */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+	dma_cap_set(DMA_PRIVATE, mask);
+	chan = dma_request_channel(mask, NULL, NULL);
+	if (!chan) {
+		dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n");
+		return -EBUSY;
+	}
+
+	dev_dbg(fb_data->dev, "Successfully received channel.\n");
+
+	fb_data->pxp_chan = to_pxp_channel(chan);
+
+	dev_dbg(fb_data->dev, "dma_chan = 0x%x\n", fb_data->pxp_chan->dma_chan);
+
+	fb_data->pxp_chan->client = fb_data;
+
+	init_completion(&fb_data->pxp_tx_cmpl);
+
+	return 0;
+}
+
+/*
+ * Function to call PxP DMA driver and send our latest FB update region
+ * through the PxP and out to an intermediate buffer.
+ * Note: This is a blocking call, so upon return the PxP tx should be complete.
+ */
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+			      struct mxcfb_rect *update_region)
+{
+	dma_cookie_t cookie;
+	struct scatterlist *sg = fb_data->sg;
+	struct dma_chan *dma_chan;
+	struct pxp_tx_desc *desc;
+	struct dma_async_tx_descriptor *txd;
+	struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+	struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data;
+	int i, ret;
+
+	dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n");
+
+	/* First, check to see that we have acquired a PxP Channel object */
+	if (fb_data->pxp_chan == NULL) {
+		/*
+		 * PxP Channel has not yet been created and initialized,
+		 * so let's go ahead and try
+		 */
+		ret = pxp_chan_init(fb_data);
+		if (ret) {
+			/*
+			 * PxP channel init failed, and we can't use the
+			 * PxP until the PxP DMA driver has loaded, so we abort
+			 */
+			dev_err(fb_data->dev, "PxP chan init failed\n");
+			return -ENODEV;
+		}
+	}
+
+	/*
+	 * Init completion, so that we
+	 * can be properly informed of the completion
+	 * of the PxP task when it is done.
+	 */
+	init_completion(&fb_data->pxp_tx_cmpl);
+
+	dev_dbg(fb_data->dev, "sg[0] = 0x%x, sg[1] = 0x%x\n",
+		sg_dma_address(&sg[0]), sg_dma_address(&sg[1]));
+
+	dma_chan = &fb_data->pxp_chan->dma_chan;
+
+	txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
+						     DMA_TO_DEVICE,
+						     DMA_PREP_INTERRUPT);
+	if (!txd) {
+		dev_err(fb_data->info.device,
+			"Error preparing a DMA transaction descriptor.\n");
+		return -EIO;
+	}
+
+	txd->callback_param = txd;
+	txd->callback = pxp_dma_done;
+
+	/*
+	 * Configure PxP for processing of new update region
+	 * The rest of our config params were set up in
+	 * probe() and should not need to be changed.
+	 */
+	proc_data->srect.top = update_region->top;
+	proc_data->srect.left = update_region->left;
+	proc_data->srect.width = update_region->width;
+	proc_data->srect.height = update_region->height;
+
+	/*
+	 * Because only YUV/YCbCr image can be scaled, configure
+	 * drect equivalent to srect, as such do not perform scaling.
+	 */
+	proc_data->drect.top = 0;
+	proc_data->drect.left = 0;
+	proc_data->drect.width = proc_data->srect.width;
+	proc_data->drect.height = proc_data->srect.height;
+
+	/* PXP expects rotation in terms of degrees */
+	proc_data->rotate = fb_data->info.var.rotate * 90;
+	if (proc_data->rotate > 270)
+		proc_data->rotate = 0;
+
+	pxp_conf->out_param.width = update_region->width;
+	pxp_conf->out_param.height = update_region->height;
+
+	desc = to_tx_desc(txd);
+	int length = desc->len;
+	for (i = 0; i < length; i++) {
+		if (i == 0) {/* S0 */
+			memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data));
+			pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
+			memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
+				sizeof(struct pxp_layer_param));
+		} else if (i == 1) {
+			pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
+			memcpy(&desc->layer_param.out_param, &pxp_conf->out_param,
+				sizeof(struct pxp_layer_param));
+		}
+		/* TODO: OverLay */
+
+		desc = desc->next;
+	}
+
+	/* Submitting our TX starts the PxP processing task */
+	cookie = txd->tx_submit(txd);
+	dev_dbg(fb_data->info.device, "%d: Submit %p #%d\n", __LINE__, txd,
+		cookie);
+	if (cookie < 0) {
+		dev_err(fb_data->info.device, "Error sending FB through PxP\n");
+		return -EIO;
+	}
+
+	fb_data->txd = txd;
+
+	/* trigger ePxP */
+	dma_async_issue_pending(dma_chan);
+
+	return 0;
+}
+
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat)
+{
+	int ret;
+	/*
+	 * Wait for completion event, which will be set
+	 * through our TX callback function.
+	 */
+	ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10);
+	if (ret <= 0) {
+		dev_info(fb_data->info.device,
+			 "PxP operation failed due to %s\n",
+			 ret < 0 ? "user interrupt" : "timeout");
+		dma_release_channel(&fb_data->pxp_chan->dma_chan);
+		fb_data->pxp_chan = NULL;
+		return ret ? : -ETIMEDOUT;
+	}
+
+	*hist_stat = to_tx_desc(fb_data->txd)->hist_status;
+	dma_release_channel(&fb_data->pxp_chan->dma_chan);
+	fb_data->pxp_chan = NULL;
+
+	dev_dbg(fb_data->dev, "TX completed\n");
+
+	return 0;
+}
+
+static int __init mxc_epdc_fb_init(void)
+{
+	return platform_driver_register(&mxc_epdc_fb_driver);
+}
+late_initcall(mxc_epdc_fb_init);
+
+
+static void __exit mxc_epdc_fb_exit(void)
+{
+	platform_driver_unregister(&mxc_epdc_fb_driver);
+}
+module_exit(mxc_epdc_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC EPDC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
new file mode 100644
index 000000000000..f345ff2fa972
--- /dev/null
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -0,0 +1,1867 @@
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+#include <mach/hardware.h>
+
+/*
+ * Driver name
+ */
+#define MXCFB_NAME      "mxc_sdc_fb"
+/*!
+ * Structure containing the MXC specific framebuffer information.
+ */
+struct mxcfb_info {
+	char *fb_mode_str;
+	int default_bpp;
+	int cur_blank;
+	int next_blank;
+	ipu_channel_t ipu_ch;
+	int ipu_di;
+	u32 ipu_di_pix_fmt;
+	bool ipu_ext_clk;
+	bool overlay;
+	bool alpha_chan_en;
+	dma_addr_t alpha_phy_addr0;
+	dma_addr_t alpha_phy_addr1;
+	void *alpha_virt_addr0;
+	void *alpha_virt_addr1;
+	uint32_t alpha_mem_len;
+	uint32_t ipu_ch_irq;
+	uint32_t cur_ipu_buf;
+	uint32_t cur_ipu_alpha_buf;
+
+	u32 pseudo_palette[16];
+
+	bool wait4vsync;
+	uint32_t waitcnt;
+	struct semaphore flip_sem;
+	struct semaphore alpha_flip_sem;
+	struct completion vsync_complete;
+};
+
+struct mxcfb_alloc_list {
+	struct list_head list;
+	dma_addr_t phy_addr;
+	void *cpu_addr;
+	u32 size;
+};
+
+enum {
+	BOTH_ON,
+	SRC_ON,
+	TGT_ON,
+	BOTH_OFF
+};
+
+static bool g_dp_in_use;
+LIST_HEAD(fb_alloc_list);
+static struct fb_info *mxcfb_info[3];
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+	uint32_t pixfmt = 0;
+
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	switch (fbi->var.bits_per_pixel) {
+	case 24:
+		pixfmt = IPU_PIX_FMT_BGR24;
+		break;
+	case 32:
+		pixfmt = IPU_PIX_FMT_BGR32;
+		break;
+	case 16:
+		pixfmt = IPU_PIX_FMT_RGB565;
+		break;
+	}
+	return pixfmt;
+}
+
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
+static int mxcfb_blank(int blank, struct fb_info *info);
+static int mxcfb_map_video_memory(struct fb_info *fbi);
+static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+static int mxcfb_option_setup(struct fb_info *info, char *options);
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+static int _setup_disp_channel1(struct fb_info *fbi)
+{
+	ipu_channel_params_t params;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	memset(&params, 0, sizeof(params));
+	params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
+
+	/*
+	 * Assuming interlaced means yuv output, below setting also
+	 * valid for mem_dc_sync. FG should have the same vmode as BG.
+	 */
+	if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		struct mxcfb_info *mxc_fbi_tmp;
+		int i;
+
+		for (i = 0; i < num_registered_fb; i++) {
+			mxc_fbi_tmp = (struct mxcfb_info *)
+				(registered_fb[i]->par);
+			if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) {
+				fbi->var.vmode =
+				registered_fb[i]->var.vmode;
+				mxc_fbi->ipu_di_pix_fmt =
+				mxc_fbi_tmp->ipu_di_pix_fmt;
+				break;
+			}
+		}
+	}
+	if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
+		if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+			params.mem_dc_sync.interlaced = true;
+			params.mem_dc_sync.out_pixel_fmt =
+				IPU_PIX_FMT_YUV444;
+		} else {
+			if (mxc_fbi->ipu_di_pix_fmt)
+				params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+			else
+				params.mem_dc_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		}
+		params.mem_dc_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+	} else {
+		if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+			params.mem_dp_bg_sync.interlaced = true;
+			params.mem_dp_bg_sync.out_pixel_fmt =
+				IPU_PIX_FMT_YUV444;
+		} else {
+			if (mxc_fbi->ipu_di_pix_fmt)
+				params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+			else
+				params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		}
+		params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+		if (mxc_fbi->alpha_chan_en)
+			params.mem_dp_bg_sync.alpha_chan_en = true;
+	}
+	ipu_init_channel(mxc_fbi->ipu_ch, &params);
+
+	return 0;
+}
+
+static int _setup_disp_channel2(struct fb_info *fbi)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	int fb_stride;
+
+	switch (bpp_to_pixfmt(fbi)) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV420P:
+		fb_stride = fbi->var.xres_virtual;
+		break;
+	default:
+		fb_stride = fbi->fix.line_length;
+	}
+
+	mxc_fbi->cur_ipu_buf = 1;
+	sema_init(&mxc_fbi->flip_sem, 1);
+	if (mxc_fbi->alpha_chan_en) {
+		mxc_fbi->cur_ipu_alpha_buf = 1;
+		sema_init(&mxc_fbi->alpha_flip_sem, 1);
+	}
+	fbi->var.xoffset = fbi->var.yoffset = 0;
+
+	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+					 bpp_to_pixfmt(fbi),
+					 fbi->var.xres, fbi->var.yres,
+					 fb_stride,
+					 IPU_ROTATE_NONE,
+					 fbi->fix.smem_start +
+					 (fbi->fix.line_length * fbi->var.yres),
+					 fbi->fix.smem_start,
+					 0, 0);
+	if (retval) {
+		dev_err(fbi->device,
+			"ipu_init_channel_buffer error %d\n", retval);
+	}
+
+	if (mxc_fbi->alpha_chan_en) {
+		retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch,
+						 IPU_ALPHA_IN_BUFFER,
+						 IPU_PIX_FMT_GENERIC,
+						 fbi->var.xres, fbi->var.yres,
+						 fbi->var.xres,
+						 IPU_ROTATE_NONE,
+						 mxc_fbi->alpha_phy_addr1,
+						 mxc_fbi->alpha_phy_addr0,
+						 0, 0);
+		if (retval) {
+			dev_err(fbi->device,
+				"ipu_init_channel_buffer error %d\n", retval);
+			return retval;
+		}
+	}
+
+	return retval;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+	int retval = 0;
+	u32 mem_len, alpha_mem_len;
+	ipu_di_signal_cfg_t sig_cfg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
+
+	ipu_disable_irq(mxc_fbi->ipu_ch_irq);
+	ipu_disable_channel(mxc_fbi->ipu_ch, true);
+	ipu_uninit_channel(mxc_fbi->ipu_ch);
+	ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+	mxcfb_set_fix(fbi);
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+		if (fbi->fix.smem_start)
+			mxcfb_unmap_video_memory(fbi);
+
+		if (mxcfb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+	}
+	if (mxc_fbi->alpha_chan_en) {
+		alpha_mem_len = fbi->var.xres * fbi->var.yres;
+		if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) ||
+		    (alpha_mem_len > mxc_fbi->alpha_mem_len)) {
+			if (mxc_fbi->alpha_phy_addr0)
+				dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr0,
+						  mxc_fbi->alpha_phy_addr0);
+			if (mxc_fbi->alpha_phy_addr1)
+				dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr1,
+						  mxc_fbi->alpha_phy_addr1);
+
+			mxc_fbi->alpha_virt_addr0 =
+					dma_alloc_coherent(fbi->device,
+						  alpha_mem_len,
+						  &mxc_fbi->alpha_phy_addr0,
+						  GFP_DMA | GFP_KERNEL);
+
+			mxc_fbi->alpha_virt_addr1 =
+					dma_alloc_coherent(fbi->device,
+						  alpha_mem_len,
+						  &mxc_fbi->alpha_phy_addr1,
+						  GFP_DMA | GFP_KERNEL);
+			if (mxc_fbi->alpha_virt_addr0 == NULL ||
+			    mxc_fbi->alpha_virt_addr1 == NULL) {
+				dev_err(fbi->device, "mxcfb: dma alloc for"
+					" alpha buffer failed.\n");
+				if (mxc_fbi->alpha_virt_addr0)
+					dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr0,
+						  mxc_fbi->alpha_phy_addr0);
+				if (mxc_fbi->alpha_virt_addr1)
+					dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr1,
+						  mxc_fbi->alpha_phy_addr1);
+				return -ENOMEM;
+			}
+			mxc_fbi->alpha_mem_len = alpha_mem_len;
+		}
+	}
+
+	if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
+		return retval;
+
+	_setup_disp_channel1(fbi);
+
+	if (!mxc_fbi->overlay) {
+		uint32_t out_pixel_fmt;
+
+		memset(&sig_cfg, 0, sizeof(sig_cfg));
+		if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+			sig_cfg.interlaced = true;
+			out_pixel_fmt = IPU_PIX_FMT_YUV444;
+		} else {
+			if (mxc_fbi->ipu_di_pix_fmt)
+				out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+			else
+				out_pixel_fmt = IPU_PIX_FMT_RGB666;
+		}
+		if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
+			sig_cfg.odd_field_first = true;
+		if ((fbi->var.sync & FB_SYNC_EXT) || mxc_fbi->ipu_ext_clk)
+			sig_cfg.ext_clk = true;
+		if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+			sig_cfg.Hsync_pol = true;
+		if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+			sig_cfg.Vsync_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
+			sig_cfg.clk_pol = true;
+		if (fbi->var.sync & FB_SYNC_DATA_INVERT)
+			sig_cfg.data_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+			sig_cfg.enable_pol = true;
+		if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
+			sig_cfg.clkidle_en = true;
+
+		dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+			(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+		if (ipu_init_sync_panel(mxc_fbi->ipu_di,
+					(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+					fbi->var.xres, fbi->var.yres,
+					out_pixel_fmt,
+					fbi->var.left_margin,
+					fbi->var.hsync_len,
+					fbi->var.right_margin,
+					fbi->var.upper_margin,
+					fbi->var.vsync_len,
+					fbi->var.lower_margin,
+					0, sig_cfg) != 0) {
+			dev_err(fbi->device,
+				"mxcfb: Error initializing panel.\n");
+			return -EINVAL;
+		}
+
+		fbi->mode =
+		    (struct fb_videomode *)fb_match_mode(&fbi->var,
+							 &fbi->modelist);
+		ipu_disp_set_window_pos(mxc_fbi->ipu_ch, 0, 0);
+	}
+
+	retval = _setup_disp_channel2(fbi);
+	if (retval)
+		return retval;
+
+	ipu_enable_channel(mxc_fbi->ipu_ch);
+
+	return retval;
+}
+
+static int _swap_channels(struct fb_info *fbi,
+			  struct fb_info *fbi_to, bool both_on)
+{
+	int retval, tmp;
+	ipu_channel_t old_ch;
+	struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi->par;
+	struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
+
+	if (both_on) {
+		ipu_disable_channel(mxc_fbi_to->ipu_ch, true);
+		ipu_uninit_channel(mxc_fbi_to->ipu_ch);
+	}
+
+	/* switch the mxc fbi parameters */
+	old_ch = mxc_fbi_from->ipu_ch;
+	mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch;
+	mxc_fbi_to->ipu_ch = old_ch;
+	tmp = mxc_fbi_from->ipu_ch_irq;
+	mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
+	mxc_fbi_to->ipu_ch_irq = tmp;
+
+	_setup_disp_channel1(fbi);
+	retval = _setup_disp_channel2(fbi);
+	if (retval)
+		return retval;
+
+	/* switch between dp and dc, disable old idmac, enable new idmac */
+	retval = ipu_swap_channel(old_ch, mxc_fbi_from->ipu_ch);
+	ipu_uninit_channel(old_ch);
+
+	if (both_on) {
+		_setup_disp_channel1(fbi_to);
+		retval = _setup_disp_channel2(fbi_to);
+		if (retval)
+			return retval;
+		ipu_enable_channel(mxc_fbi_to->ipu_ch);
+	}
+
+	return retval;
+}
+
+static int swap_channels(struct fb_info *fbi)
+{
+	int i;
+	int swap_mode;
+	ipu_channel_t ch_to;
+	struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi->par;
+	struct fb_info *fbi_to = NULL;
+	struct mxcfb_info *mxc_fbi_to;
+
+	/* what's the target channel? */
+	if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC)
+		ch_to = MEM_DC_SYNC;
+	else
+		ch_to = MEM_BG_SYNC;
+
+	for (i = 0; i < num_registered_fb; i++) {
+		mxc_fbi_to =
+			(struct mxcfb_info *)mxcfb_info[i]->par;
+		if (mxc_fbi_to->ipu_ch == ch_to) {
+			fbi_to = mxcfb_info[i];
+			break;
+		}
+	}
+	if (fbi_to == NULL)
+		return -1;
+
+	ipu_clear_irq(mxc_fbi_from->ipu_ch_irq);
+	ipu_clear_irq(mxc_fbi_to->ipu_ch_irq);
+	ipu_free_irq(mxc_fbi_from->ipu_ch_irq, fbi);
+	ipu_free_irq(mxc_fbi_to->ipu_ch_irq, fbi_to);
+
+	if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) {
+		if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
+			swap_mode = BOTH_ON;
+		else
+			swap_mode = SRC_ON;
+	} else {
+		if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
+			swap_mode = TGT_ON;
+		else
+			swap_mode = BOTH_OFF;
+	}
+
+	/* tvout di-1: for DC use UYVY, for DP use RGB */
+	if (mxc_fbi_from->ipu_di == 1 && ch_to == MEM_DC_SYNC) {
+		fbi->var.bits_per_pixel = 16;
+		fbi->var.nonstd = IPU_PIX_FMT_UYVY;
+	} else if (mxc_fbi_from->ipu_di == 1 && ch_to == MEM_BG_SYNC) {
+		fbi->var.nonstd = 0;
+	} else if (mxc_fbi_from->ipu_di == 0 && ch_to == MEM_DC_SYNC) {
+		fbi_to->var.nonstd = 0;
+	} else if (mxc_fbi_from->ipu_di == 0 && ch_to == MEM_BG_SYNC) {
+		fbi->var.bits_per_pixel = 16;
+		fbi->var.nonstd = IPU_PIX_FMT_UYVY;
+	}
+
+	switch (swap_mode) {
+	case BOTH_ON:
+		/* disable target->switch src->enable target */
+		_swap_channels(fbi, fbi_to, true);
+		break;
+	case SRC_ON:
+		/* just switch src */
+		_swap_channels(fbi, fbi_to, false);
+		break;
+	case TGT_ON:
+		/* just switch target */
+		_swap_channels(fbi_to, fbi, false);
+		break;
+	case BOTH_OFF:
+		/* switch directly, no more need to do */
+		mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch;
+		mxc_fbi_from->ipu_ch = ch_to;
+		i = mxc_fbi_from->ipu_ch_irq;
+		mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
+		mxc_fbi_to->ipu_ch_irq = i;
+		break;
+	default:
+		break;
+	}
+
+	if (ipu_request_irq(mxc_fbi_from->ipu_ch_irq, mxcfb_irq_handler, 0,
+		MXCFB_NAME, fbi) != 0) {
+		dev_err(fbi->device, "Error registering irq %d\n",
+			mxc_fbi_from->ipu_ch_irq);
+		return -EBUSY;
+	}
+	ipu_disable_irq(mxc_fbi_from->ipu_ch_irq);
+	if (ipu_request_irq(mxc_fbi_to->ipu_ch_irq, mxcfb_irq_handler, 0,
+		MXCFB_NAME, fbi_to) != 0) {
+		dev_err(fbi_to->device, "Error registering irq %d\n",
+			mxc_fbi_to->ipu_ch_irq);
+		return -EBUSY;
+	}
+	ipu_disable_irq(mxc_fbi_to->ipu_ch_irq);
+
+	return 0;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param       var      framebuffer variable parameters
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	u32 vtotal;
+	u32 htotal;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	/* fg should not bigger than bg */
+	if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		struct fb_info *fbi_tmp;
+		struct mxcfb_info *mxc_fbi_tmp;
+		int i, bg_xres, bg_yres;
+		int16_t pos_x, pos_y;
+
+		bg_xres = var->xres;
+		bg_yres = var->yres;
+
+		for (i = 0; i < num_registered_fb; i++) {
+			fbi_tmp = registered_fb[i];
+			mxc_fbi_tmp = (struct mxcfb_info *)
+				(fbi_tmp->par);
+			if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) {
+				bg_xres = fbi_tmp->var.xres;
+				bg_yres = fbi_tmp->var.yres;
+				break;
+			}
+		}
+
+		ipu_disp_get_window_pos(mxc_fbi->ipu_ch, &pos_x, &pos_y);
+
+		if ((var->xres + pos_x) > bg_xres)
+			var->xres = bg_xres - pos_x;
+		if ((var->yres + pos_y) > bg_yres)
+			var->yres = bg_yres - pos_y;
+	}
+
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
+	    (var->bits_per_pixel != 8))
+		var->bits_per_pixel = 16;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->red.length = 3;
+		var->red.offset = 5;
+		var->red.msb_right = 0;
+
+		var->green.length = 3;
+		var->green.offset = 2;
+		var->green.msb_right = 0;
+
+		var->blue.length = 2;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	if (var->pixclock < 1000) {
+		htotal = var->xres + var->right_margin + var->hsync_len +
+		    var->left_margin;
+		vtotal = var->yres + var->lower_margin + var->vsync_len +
+		    var->upper_margin;
+		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+		var->pixclock = KHZ2PICOS(var->pixclock);
+		dev_dbg(info->device,
+			"pixclock set for 60Hz refresh = %u ps\n",
+			var->pixclock);
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	return 0;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			   u_int trans, struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * Function to handle custom ioctls for MXC framebuffer.
+ *
+ * @param       inode   inode struct
+ *
+ * @param       file    file struct
+ *
+ * @param       cmd     Ioctl command to handle
+ *
+ * @param       arg     User pointer to command arguments
+ *
+ * @param       fbi     framebuffer information pointer
+ */
+static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+	int __user *argp = (void __user *)arg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	switch (cmd) {
+	case MXCFB_SET_GBL_ALPHA:
+		{
+			struct mxcfb_gbl_alpha ga;
+
+			if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (ipu_disp_set_global_alpha(mxc_fbi->ipu_ch,
+						      (bool)ga.enable,
+						      ga.alpha)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (ga.enable)
+				mxc_fbi->alpha_chan_en = false;
+
+			if (ga.enable)
+				dev_dbg(fbi->device,
+					"Set global alpha of %s to %d\n",
+					fbi->fix.id, ga.alpha);
+			break;
+		}
+	case MXCFB_SET_LOC_ALPHA:
+		{
+			struct mxcfb_loc_alpha la;
+			int i;
+			char *video_plane_idstr = "";
+
+			if (copy_from_user(&la, (void *)arg, sizeof(la))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (ipu_disp_set_global_alpha(mxc_fbi->ipu_ch,
+						      !(bool)la.enable, 0)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (la.enable && !la.alpha_in_pixel) {
+				mxc_fbi->alpha_chan_en = true;
+
+				if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
+					video_plane_idstr = "DISP3 BG";
+				else if (mxc_fbi->ipu_ch == MEM_BG_SYNC)
+					video_plane_idstr = "DISP3 FG";
+
+				for (i = 0; i < num_registered_fb; i++) {
+					char *idstr = registered_fb[i]->fix.id;
+					if (strcmp(idstr, video_plane_idstr) == 0) {
+						((struct mxcfb_info *)(registered_fb[i]->par))->alpha_chan_en = false;
+						break;
+					}
+				}
+			} else
+				mxc_fbi->alpha_chan_en = false;
+
+			mxcfb_set_par(fbi);
+
+			la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0;
+			la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1;
+			if (copy_to_user((void *)arg, &la, sizeof(la))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (la.enable)
+				dev_dbg(fbi->device,
+					"Enable DP local alpha for %s\n",
+					fbi->fix.id);
+			break;
+		}
+	case MXCFB_SET_LOC_ALP_BUF:
+		{
+			unsigned long base;
+			uint32_t ipu_alp_ch_irq;
+
+			if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) ||
+			     (mxc_fbi->ipu_ch == MEM_BG_SYNC)) &&
+			     (mxc_fbi->alpha_chan_en))) {
+				dev_err(fbi->device,
+					"Should use background or overlay "
+					"framebuffer to set the alpha buffer "
+					"number\n");
+				return -EINVAL;
+			}
+
+			if (get_user(base, argp))
+				return -EFAULT;
+
+			if (base != mxc_fbi->alpha_phy_addr0 &&
+			    base != mxc_fbi->alpha_phy_addr1) {
+				dev_err(fbi->device,
+					"Wrong alpha buffer physical address "
+					"%lu\n", base);
+				return -EINVAL;
+			}
+
+			if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
+				ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
+			else
+				ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
+
+			down(&mxc_fbi->alpha_flip_sem);
+
+			mxc_fbi->cur_ipu_alpha_buf =
+						!mxc_fbi->cur_ipu_alpha_buf;
+			if (ipu_update_channel_buffer(mxc_fbi->ipu_ch,
+						      IPU_ALPHA_IN_BUFFER,
+						      mxc_fbi->
+							cur_ipu_alpha_buf,
+						      base) == 0) {
+				ipu_select_buffer(mxc_fbi->ipu_ch,
+						  IPU_ALPHA_IN_BUFFER,
+						  mxc_fbi->cur_ipu_alpha_buf);
+				ipu_clear_irq(ipu_alp_ch_irq);
+				ipu_enable_irq(ipu_alp_ch_irq);
+			} else {
+				dev_err(fbi->device,
+					"Error updating %s SDC alpha buf %d "
+					"to address=0x%08lX\n",
+					fbi->fix.id,
+					mxc_fbi->cur_ipu_alpha_buf, base);
+			}
+			break;
+		}
+	case MXCFB_SET_CLR_KEY:
+		{
+			struct mxcfb_color_key key;
+			if (copy_from_user(&key, (void *)arg, sizeof(key))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_disp_set_color_key(mxc_fbi->ipu_ch,
+							key.enable,
+							key.color_key);
+			dev_dbg(fbi->device, "Set color key to 0x%08X\n",
+				key.color_key);
+			break;
+		}
+	case MXCFB_SET_GAMMA:
+		{
+			struct mxcfb_gamma gamma;
+			if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu_ch,
+							gamma.enable,
+							gamma.constk,
+							gamma.slopek);
+			break;
+		}
+	case MXCFB_WAIT_FOR_VSYNC:
+		{
+			if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+				struct mxcfb_info *bg_mxcfbi = NULL;
+				int i;
+				for (i = 0; i < num_registered_fb; i++) {
+					bg_mxcfbi =
+					((struct mxcfb_info *)(registered_fb[i]->par));
+
+					if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC)
+						break;
+				}
+				if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) {
+					retval = -EINVAL;
+					break;
+				}
+			}
+			if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) {
+				retval = -EINVAL;
+				break;
+			}
+
+			init_completion(&mxc_fbi->vsync_complete);
+
+			ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+			mxc_fbi->wait4vsync = 1;
+			ipu_enable_irq(mxc_fbi->ipu_ch_irq);
+			retval = wait_for_completion_interruptible_timeout(
+				&mxc_fbi->vsync_complete, 1 * HZ);
+			if (retval == 0) {
+				dev_err(fbi->device,
+					"MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
+					retval);
+				mxc_fbi->wait4vsync = 0;
+				retval = -ETIME;
+			} else if (retval > 0) {
+				retval = 0;
+			}
+			break;
+		}
+	case FBIO_ALLOC:
+		{
+			int size;
+			struct mxcfb_alloc_list *mem;
+
+			mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+			if (mem == NULL)
+				return -ENOMEM;
+
+			if (get_user(size, argp))
+				return -EFAULT;
+
+			mem->size = PAGE_ALIGN(size);
+
+			mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
+							   &mem->phy_addr,
+							   GFP_DMA);
+			if (mem->cpu_addr == NULL) {
+				kfree(mem);
+				return -ENOMEM;
+			}
+
+			list_add(&mem->list, &fb_alloc_list);
+
+			dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
+				mem->size, mem->phy_addr);
+
+			if (put_user(mem->phy_addr, argp))
+				return -EFAULT;
+
+			break;
+		}
+	case FBIO_FREE:
+		{
+			unsigned long offset;
+			struct mxcfb_alloc_list *mem;
+
+			if (get_user(offset, argp))
+				return -EFAULT;
+
+			retval = -EINVAL;
+			list_for_each_entry(mem, &fb_alloc_list, list) {
+				if (mem->phy_addr == offset) {
+					list_del(&mem->list);
+					dma_free_coherent(fbi->device,
+							  mem->size,
+							  mem->cpu_addr,
+							  mem->phy_addr);
+					kfree(mem);
+					retval = 0;
+					break;
+				}
+			}
+
+			break;
+		}
+	case MXCFB_SET_OVERLAY_POS:
+		{
+			struct mxcfb_pos pos;
+			struct fb_info *bg_fbi = NULL;
+			struct mxcfb_info *bg_mxcfbi = NULL;
+			int i;
+
+			if (mxc_fbi->ipu_ch != MEM_FG_SYNC) {
+				dev_err(fbi->device, "Should use the overlay "
+					"framebuffer to set the position of "
+					"the overlay window\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			for (i = 0; i < num_registered_fb; i++) {
+				bg_mxcfbi =
+				((struct mxcfb_info *)(registered_fb[i]->par));
+
+				if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC) {
+					bg_fbi = registered_fb[i];
+					break;
+				}
+			}
+
+			if (bg_fbi == NULL) {
+				dev_err(fbi->device, "Cannot find the "
+					"background framebuffer\n");
+				retval = -ENOENT;
+				break;
+			}
+
+			if (fbi->var.xres + pos.x > bg_fbi->var.xres) {
+				if (bg_fbi->var.xres < fbi->var.xres)
+					pos.x = 0;
+				else
+					pos.x = bg_fbi->var.xres - fbi->var.xres;
+			}
+			if (fbi->var.yres + pos.y > bg_fbi->var.yres) {
+				if (bg_fbi->var.yres < fbi->var.yres)
+					pos.y = 0;
+				else
+					pos.y = bg_fbi->var.yres - fbi->var.yres;
+			}
+
+			retval = ipu_disp_set_window_pos(mxc_fbi->ipu_ch,
+							 pos.x, pos.y);
+
+			if (copy_to_user((void *)arg, &pos, sizeof(pos))) {
+				retval = -EFAULT;
+				break;
+			}
+			break;
+		}
+	case MXCFB_GET_FB_IPU_CHAN:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_ch, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_DIFMT:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_FB_IPU_DI:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di, argp))
+				return -EFAULT;
+			break;
+		}
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*
+ * mxcfb_blank():
+ *      Blank the display.
+ */
+static int mxcfb_blank(int blank, struct fb_info *info)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	dev_dbg(info->device, "blank = %d\n", blank);
+
+	if (mxc_fbi->cur_blank == blank)
+		return 0;
+
+	mxc_fbi->next_blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		ipu_disable_channel(mxc_fbi->ipu_ch, true);
+		ipu_uninit_channel(mxc_fbi->ipu_ch);
+		break;
+	case FB_BLANK_UNBLANK:
+		mxcfb_set_par(info);
+		break;
+	}
+	mxc_fbi->cur_blank = blank;
+	return 0;
+}
+
+/*
+ * Pan or Wrap the Display
+ *
+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
+ *
+ * @param               var     Variable screen buffer information
+ * @param               info    Framebuffer information pointer
+ */
+static int
+mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par,
+			  *mxc_graphic_fbi = NULL;
+	u_int y_bottom;
+	unsigned long base, active_alpha_phy_addr = 0;
+	bool loc_alpha_en = false;
+	int i = 0;
+
+	if (var->xoffset > 0) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((info->var.xoffset == var->xoffset) &&
+	    (info->var.yoffset == var->yoffset))
+		return 0;	/* No change, do nothing */
+
+	/* no pan display during fb blank */
+	if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		struct mxcfb_info *bg_mxcfbi = NULL;
+		int j;
+		for (j = 0; j < num_registered_fb; j++) {
+			bg_mxcfbi =
+				((struct mxcfb_info *)(registered_fb[j]->par));
+
+			if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC)
+				break;
+		}
+		if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK)
+			return -EINVAL;
+	}
+	if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK)
+		return -EINVAL;
+
+	y_bottom = var->yoffset;
+
+	if (!(var->vmode & FB_VMODE_YWRAP))
+		y_bottom += var->yres;
+
+	if (y_bottom > info->var.yres_virtual)
+		return -EINVAL;
+
+	base = (var->yoffset * var->xres_virtual + var->xoffset);
+	base = (var->bits_per_pixel) * base / 8;
+	base += info->fix.smem_start;
+
+	/* Check if DP local alpha is enabled and find the graphic fb */
+	if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		for (i = 0; i < num_registered_fb; i++) {
+			char *idstr = registered_fb[i]->fix.id;
+			if ((strcmp(idstr, "DISP3 BG") == 0 ||
+			     strcmp(idstr, "DISP3 FG") == 0) &&
+			    ((struct mxcfb_info *)
+			      (registered_fb[i]->par))->alpha_chan_en) {
+				loc_alpha_en = true;
+				mxc_graphic_fbi = (struct mxcfb_info *)
+						(registered_fb[i]->par);
+				active_alpha_phy_addr = mxc_fbi->cur_ipu_buf ?
+					mxc_graphic_fbi->alpha_phy_addr1 :
+					mxc_graphic_fbi->alpha_phy_addr0;
+				dev_dbg(info->device, "Updating SDC graphic "
+					"buf %d address=0x%08lX\n",
+					mxc_fbi->cur_ipu_buf,
+					active_alpha_phy_addr);
+				break;
+			}
+		}
+	}
+
+	down(&mxc_fbi->flip_sem);
+
+	mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+
+	dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
+		info->fix.id, mxc_fbi->cur_ipu_buf, base);
+
+	if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				      mxc_fbi->cur_ipu_buf, base) == 0) {
+		/* Update the DP local alpha buffer only for graphic plane */
+		if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi &&
+		    ipu_update_channel_buffer(mxc_graphic_fbi->ipu_ch,
+					      IPU_ALPHA_IN_BUFFER,
+					      mxc_fbi->cur_ipu_buf,
+					      active_alpha_phy_addr) == 0) {
+			ipu_select_buffer(mxc_graphic_fbi->ipu_ch,
+					  IPU_ALPHA_IN_BUFFER,
+					  mxc_fbi->cur_ipu_buf);
+		}
+
+		ipu_select_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				  mxc_fbi->cur_ipu_buf);
+		ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu_ch_irq);
+	} else {
+		dev_err(info->device,
+			"Error updating SDC buf %d to address=0x%08lX\n",
+			mxc_fbi->cur_ipu_buf, base);
+		mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+		ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu_ch_irq);
+		return -EBUSY;
+	}
+
+	dev_dbg(info->device, "Update complete\n");
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	if (var->vmode & FB_VMODE_YWRAP)
+		info->var.vmode |= FB_VMODE_YWRAP;
+	else
+		info->var.vmode &= ~FB_VMODE_YWRAP;
+
+	return 0;
+}
+
+/*
+ * Function to handle custom mmap for MXC framebuffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       vma     Pointer to vm_area_struct
+ */
+static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
+{
+	bool found = false;
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+	struct mxcfb_alloc_list *mem;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	if (offset < fbi->fix.smem_len) {
+		/* mapping framebuffer memory */
+		len = fbi->fix.smem_len - offset;
+		vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
+	} else if ((vma->vm_pgoff ==
+			(mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) ||
+		   (vma->vm_pgoff ==
+			(mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) {
+		len = mxc_fbi->alpha_mem_len;
+	} else {
+		list_for_each_entry(mem, &fb_alloc_list, list) {
+			if (offset == mem->phy_addr) {
+				found = true;
+				len = mem->size;
+				break;
+			}
+		}
+		if (!found)
+			return -EINVAL;
+	}
+
+	len = PAGE_ALIGN(len);
+	if (vma->vm_end - vma->vm_start > len)
+		return -EINVAL;
+
+	/* make buffers bufferable */
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+		dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
+		return -ENOBUFS;
+	}
+
+	return 0;
+}
+
+/*!
+ * This structure contains the pointers to the control functions that are
+ * invoked by the core framebuffer driver to perform operations like
+ * blitting, rectangle filling, copy regions and cursor definition.
+ */
+static struct fb_ops mxcfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_set_par = mxcfb_set_par,
+	.fb_check_var = mxcfb_check_var,
+	.fb_setcolreg = mxcfb_setcolreg,
+	.fb_pan_display = mxcfb_pan_display,
+	.fb_ioctl = mxcfb_ioctl,
+	.fb_mmap = mxcfb_mmap,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_blank = mxcfb_blank,
+};
+
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
+{
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if (mxc_fbi->wait4vsync) {
+		complete(&mxc_fbi->vsync_complete);
+		ipu_disable_irq(irq);
+		mxc_fbi->wait4vsync = 0;
+	} else {
+		if (!ipu_check_buffer_busy(mxc_fbi->ipu_ch,
+				IPU_INPUT_BUFFER, mxc_fbi->cur_ipu_buf)
+				|| (mxc_fbi->waitcnt > 2)) {
+			/*
+			 * This interrupt come after pan display select
+			 * cur_ipu_buf buffer, this buffer should become
+			 * idle after show. If it keep busy, clear it manually.
+			 */
+			if (mxc_fbi->waitcnt > 2)
+				ipu_clear_buffer_ready(mxc_fbi->ipu_ch,
+						IPU_INPUT_BUFFER,
+						mxc_fbi->cur_ipu_buf);
+			up(&mxc_fbi->flip_sem);
+			ipu_disable_irq(irq);
+			mxc_fbi->waitcnt = 0;
+		} else
+			mxc_fbi->waitcnt++;
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id)
+{
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	up(&mxc_fbi->alpha_flip_sem);
+	ipu_disable_irq(irq);
+	return IRQ_HANDLED;
+}
+
+/*
+ * Suspends the framebuffer and blanks the screen. Power management support
+ */
+static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	int saved_blank;
+#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
+	void *fbmem;
+#endif
+
+	acquire_console_sem();
+	fb_set_suspend(fbi, 1);
+	saved_blank = mxc_fbi->cur_blank;
+	mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
+	mxc_fbi->next_blank = saved_blank;
+	release_console_sem();
+
+	return 0;
+}
+
+/*
+ * Resumes the framebuffer and unblanks the screen. Power management support
+ */
+static int mxcfb_resume(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	acquire_console_sem();
+	mxcfb_blank(mxc_fbi->next_blank, fbi);
+	fb_set_suspend(fbi, 0);
+	release_console_sem();
+
+	return 0;
+}
+
+/*
+ * Main framebuffer functions
+ */
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_map_video_memory(struct fb_info *fbi)
+{
+	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+				    fbi->fix.line_length;
+
+	fbi->screen_base = dma_alloc_writecombine(fbi->device,
+				fbi->fix.smem_len,
+				(dma_addr_t *)&fbi->fix.smem_start,
+				GFP_DMA);
+	if (fbi->screen_base == 0) {
+		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+		fbi->fix.smem_len = 0;
+		fbi->fix.smem_start = 0;
+		return -EBUSY;
+	}
+
+	dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+	dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+			      fbi->screen_base, fbi->fix.smem_start);
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+/*!
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures.  This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return      Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
+	if (!fbi)
+		return NULL;
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+
+	fbi->fbops = ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+	/*
+	 * Allocate colormap
+	 */
+	fb_alloc_cmap(&fbi->cmap, 16, 0);
+
+	return fbi;
+}
+
+static ssize_t show_disp_chan(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
+
+	if (mxcfbi->ipu_ch == MEM_BG_SYNC)
+		return sprintf(buf, "2-layer-fb-bg\n");
+	else if (mxcfbi->ipu_ch == MEM_FG_SYNC)
+		return sprintf(buf, "2-layer-fb-fg\n");
+	else if (mxcfbi->ipu_ch == MEM_DC_SYNC)
+		return sprintf(buf, "1-layer-fb\n");
+	else
+		return sprintf(buf, "err: no display chan\n");
+}
+
+static ssize_t swap_disp_chan(struct device *dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
+	struct mxcfb_info *fg_mxcfbi = NULL;
+
+	acquire_console_sem();
+	/* swap only happen between DP-BG and DC, while DP-FG disable */
+	if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
+	     (strstr(buf, "1-layer-fb") != NULL)) ||
+	    ((mxcfbi->ipu_ch == MEM_DC_SYNC) &&
+	     (strstr(buf, "2-layer-fb-bg") != NULL))) {
+		int i;
+
+		for (i = 0; i < num_registered_fb; i++) {
+			fg_mxcfbi =
+				(struct mxcfb_info *)mxcfb_info[i]->par;
+			if (fg_mxcfbi->ipu_ch == MEM_FG_SYNC)
+				break;
+			else
+				fg_mxcfbi = NULL;
+		}
+		if (!fg_mxcfbi ||
+			fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
+			dev_err(dev,
+				"Can not switch while fb2(fb-fg) is on.\n");
+			release_console_sem();
+			return count;
+		}
+
+		if (swap_channels(info) < 0)
+			dev_err(dev, "Swap display channel failed.\n");
+	}
+
+	release_console_sem();
+	return count;
+}
+DEVICE_ATTR(fsl_disp_property, 644, show_disp_chan, swap_disp_chan);
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(struct platform_device *pdev)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+	struct mxc_fb_platform_data *plat_data = pdev->dev.platform_data;
+	struct resource *res;
+	char *options;
+	char name[] = "mxcdi0fb";
+	int ret = 0;
+
+	/*
+	 * Initialize FB structures
+	 */
+	fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
+	if (!fbi) {
+		ret = -ENOMEM;
+		goto err0;
+	}
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	name[5] += pdev->id;
+	if (fb_get_options(name, &options))
+		return -ENODEV;
+
+	if (options)
+		mxcfb_option_setup(fbi, options);
+
+	if (!g_dp_in_use) {
+		mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
+		mxcfbi->ipu_ch = MEM_BG_SYNC;
+		mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
+	} else {
+		mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF;
+		mxcfbi->ipu_ch = MEM_DC_SYNC;
+		mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
+	}
+
+	mxcfbi->ipu_di = pdev->id;
+
+	if (pdev->id == 0) {
+		ipu_disp_set_global_alpha(mxcfbi->ipu_ch, true, 0x80);
+		ipu_disp_set_color_key(mxcfbi->ipu_ch, false, 0);
+		strcpy(fbi->fix.id, "DISP3 BG");
+
+		if (!g_dp_in_use)
+			if (ipu_request_irq(IPU_IRQ_BG_ALPHA_SYNC_EOF,
+					    mxcfb_alpha_irq_handler, 0,
+					    MXCFB_NAME, fbi) != 0) {
+				dev_err(&pdev->dev, "Error registering BG "
+						    "alpha irq handler.\n");
+				ret = -EBUSY;
+				goto err1;
+			}
+		g_dp_in_use = true;
+	} else if (pdev->id == 1) {
+		strcpy(fbi->fix.id, "DISP3 BG - DI1");
+
+		if (!g_dp_in_use)
+			if (ipu_request_irq(IPU_IRQ_BG_ALPHA_SYNC_EOF,
+					    mxcfb_alpha_irq_handler, 0,
+					    MXCFB_NAME, fbi) != 0) {
+				dev_err(&pdev->dev, "Error registering BG "
+						    "alpha irq handler.\n");
+				ret = -EBUSY;
+				goto err1;
+			}
+		g_dp_in_use = true;
+	} else if (pdev->id == 2) {	/* Overlay */
+		mxcfbi->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF;
+		mxcfbi->ipu_ch = MEM_FG_SYNC;
+		mxcfbi->ipu_di = -1;
+		mxcfbi->overlay = true;
+		mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
+
+		strcpy(fbi->fix.id, "DISP3 FG");
+
+		if (ipu_request_irq(IPU_IRQ_FG_ALPHA_SYNC_EOF,
+				    mxcfb_alpha_irq_handler, 0,
+				    MXCFB_NAME, fbi) != 0) {
+			dev_err(&pdev->dev, "Error registering FG alpha irq "
+					    "handler.\n");
+			ret = -EBUSY;
+			goto err1;
+		}
+	}
+
+	mxcfb_info[pdev->id] = fbi;
+
+	if (ipu_request_irq(mxcfbi->ipu_ch_irq, mxcfb_irq_handler, 0,
+			    MXCFB_NAME, fbi) != 0) {
+		dev_err(&pdev->dev, "Error registering BG irq handler.\n");
+		ret = -EBUSY;
+		goto err1;
+	}
+	ipu_disable_irq(mxcfbi->ipu_ch_irq);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res && res->end) {
+		fbi->fix.smem_len = res->end - res->start + 1;
+		fbi->fix.smem_start = res->start;
+		fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len);
+	}
+
+	/* Need dummy values until real panel is configured */
+	fbi->var.xres = 240;
+	fbi->var.yres = 320;
+
+	if (!mxcfbi->default_bpp)
+		mxcfbi->default_bpp = 16;
+
+	if (plat_data && !mxcfbi->ipu_di_pix_fmt)
+		mxcfbi->ipu_di_pix_fmt = plat_data->interface_pix_fmt;
+
+	if (plat_data && plat_data->mode && plat_data->num_modes)
+		fb_videomode_to_modelist(plat_data->mode, plat_data->num_modes,
+				&fbi->modelist);
+
+	if (!mxcfbi->fb_mode_str && plat_data && plat_data->mode_str)
+		mxcfbi->fb_mode_str = plat_data->mode_str;
+
+	if (mxcfbi->fb_mode_str) {
+		ret = fb_find_mode(&fbi->var, fbi, mxcfbi->fb_mode_str, NULL, 0, NULL,
+				mxcfbi->default_bpp);
+		if ((!ret || (ret > 2)) && plat_data && plat_data->mode && plat_data->num_modes)
+			fb_find_mode(&fbi->var, fbi, mxcfbi->fb_mode_str, plat_data->mode,
+					plat_data->num_modes, NULL, mxcfbi->default_bpp);
+	}
+
+	mxcfb_check_var(&fbi->var, fbi);
+
+	/* Default Y virtual size is 2x panel size */
+	fbi->var.yres_virtual = fbi->var.yres * 3;
+
+	mxcfb_set_fix(fbi);
+
+	/* alocate fb first */
+	if (!res || !res->end)
+		if (mxcfb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+
+	ret = register_framebuffer(fbi);
+	if (ret < 0)
+		goto err2;
+
+	platform_set_drvdata(pdev, fbi);
+
+	ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property);
+	if (ret)
+		dev_err(&pdev->dev, "Error %d on creating file\n", ret);
+
+	return 0;
+
+err2:
+	ipu_free_irq(mxcfbi->ipu_ch_irq, fbi);
+err1:
+	fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+err0:
+	return ret;
+}
+
+static int mxcfb_remove(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if (!fbi)
+		return 0;
+
+	mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
+	ipu_free_irq(mxc_fbi->ipu_ch_irq, fbi);
+	mxcfb_unmap_video_memory(fbi);
+
+	if (&fbi->cmap)
+		fb_dealloc_cmap(&fbi->cmap);
+
+	unregister_framebuffer(fbi);
+	framebuffer_release(fbi);
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcfb_driver = {
+	.driver = {
+		   .name = MXCFB_NAME,
+		   },
+	.probe = mxcfb_probe,
+	.remove = mxcfb_remove,
+	.suspend = mxcfb_suspend,
+	.resume = mxcfb_resume,
+};
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * 	video=mxcdi0fb:RGB24, 1024x768M-16@60,bpp=16,noaccel
+ */
+static int mxcfb_option_setup(struct fb_info *info, char *options)
+{
+	struct mxcfb_info *mxcfbi = info->par;
+	char *opt;
+
+	if (!options || !*options)
+		return 0;
+
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+
+		if (!strncmp(opt, "RGB24", 5)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB24;
+			continue;
+		}
+		if (!strncmp(opt, "BGR24", 5)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_BGR24;
+			continue;
+		}
+		if (!strncmp(opt, "RGB565", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB565;
+			continue;
+		}
+		if (!strncmp(opt, "RGB666", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB666;
+			continue;
+		}
+		if (!strncmp(opt, "YUV444", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUV444;
+			continue;
+		}
+		if (!strncmp(opt, "LVDS666", 7)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_LVDS666;
+			continue;
+		}
+		if (!strncmp(opt, "YUYV16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUYV;
+			continue;
+		}
+		if (!strncmp(opt, "UYVY16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_UYVY;
+			continue;
+		}
+		if (!strncmp(opt, "YVYU16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YVYU;
+			continue;
+		}
+		if (!strncmp(opt, "VYUY16", 6)) {
+			mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_VYUY;
+			continue;
+		}
+		if (!strncmp(opt, "ext_clk", 7)) {
+			mxcfbi->ipu_ext_clk = true;
+			continue;
+		}
+		if (!strncmp(opt, "bpp=", 4))
+			mxcfbi->default_bpp =
+				simple_strtoul(opt + 4, NULL, 0);
+		else
+			mxcfbi->fb_mode_str = opt;
+	}
+
+	return 0;
+}
+
+/*!
+ * Main entry function for the framebuffer. The function registers the power
+ * management callback functions with the kernel and also registers the MXCFB
+ * callback functions with the core Linux framebuffer driver \b fbmem.c
+ *
+ * @return      Error code indicating success or failure
+ */
+int __init mxcfb_init(void)
+{
+	return platform_driver_register(&mxcfb_driver);
+}
+
+void mxcfb_exit(void)
+{
+	platform_driver_unregister(&mxcfb_driver);
+}
+
+module_init(mxcfb_init);
+module_exit(mxcfb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxcfb.c b/drivers/video/mxc/mxcfb.c
new file mode 100644
index 000000000000..5152a8850148
--- /dev/null
+++ b/drivers/video/mxc/mxcfb.c
@@ -0,0 +1,1377 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+#include <mach/hardware.h>
+
+/*
+ * Driver name
+ */
+#define MXCFB_NAME      "mxc_sdc_fb"
+/*!
+ * Structure containing the MXC specific framebuffer information.
+ */
+struct mxcfb_info {
+	int blank;
+	ipu_channel_t ipu_ch;
+	uint32_t ipu_ch_irq;
+	uint32_t cur_ipu_buf;
+
+	u32 pseudo_palette[16];
+
+	struct semaphore flip_sem;
+	spinlock_t fb_lock;
+};
+
+struct mxcfb_data {
+	struct fb_info *fbi;
+	struct fb_info *fbi_ovl;
+	volatile int32_t vsync_flag;
+	wait_queue_head_t vsync_wq;
+	wait_queue_head_t suspend_wq;
+	bool suspended;
+	int backlight_level;
+};
+
+struct mxcfb_alloc_list {
+	struct list_head list;
+	dma_addr_t phy_addr;
+	void *cpu_addr;
+	u32 size;
+};
+
+static struct mxcfb_data mxcfb_drv_data;
+
+static char *fb_mode = NULL;
+static unsigned long default_bpp = 16;
+#ifdef CONFIG_FB_MXC_INTERNAL_MEM
+static struct clk *iram_clk;
+#endif
+LIST_HEAD(fb_alloc_list);
+
+static uint32_t bpp_to_pixfmt(int bpp)
+{
+	uint32_t pixfmt = 0;
+	switch (bpp) {
+	case 24:
+		pixfmt = IPU_PIX_FMT_BGR24;
+		break;
+	case 32:
+		pixfmt = IPU_PIX_FMT_BGR32;
+		break;
+	case 16:
+		pixfmt = IPU_PIX_FMT_RGB565;
+		break;
+	}
+	return pixfmt;
+}
+
+extern void gpio_lcd_active(void);
+extern void gpio_lcd_inactive(void);
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
+static int mxcfb_blank(int blank, struct fb_info *info);
+static int mxcfb_map_video_memory(struct fb_info *fbi, bool use_internal_ram);
+static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	if (mxc_fbi->ipu_ch == MEM_SDC_FG)
+		strncpy(fix->id, "DISP3 FG", 8);
+	else
+		strncpy(fix->id, "DISP3 BG", 8);
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+	int retval;
+	bool use_iram = false;
+	u32 mem_len;
+	ipu_di_signal_cfg_t sig_cfg;
+	ipu_panel_t mode = IPU_PANEL_TFT;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	ipu_disable_irq(mxc_fbi->ipu_ch_irq);
+	ipu_disable_channel(mxc_fbi->ipu_ch, true);
+	ipu_uninit_channel(mxc_fbi->ipu_ch);
+	ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+	mxcfb_set_fix(fbi);
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (mem_len > fbi->fix.smem_len) {
+		if (fbi->fix.smem_start)
+			mxcfb_unmap_video_memory(fbi);
+
+#ifdef CONFIG_FB_MXC_INTERNAL_MEM
+		if (mxc_fbi->ipu_ch == MEM_SDC_BG) {
+			use_iram = true;
+		}
+#endif
+		if (mxcfb_map_video_memory(fbi, use_iram) < 0)
+			return -ENOMEM;
+	}
+
+	ipu_init_channel(mxc_fbi->ipu_ch, NULL);
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	if (mxc_fbi->ipu_ch == MEM_SDC_BG) {
+		memset(&sig_cfg, 0, sizeof(sig_cfg));
+		if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+			sig_cfg.Hsync_pol = true;
+		if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+			sig_cfg.Vsync_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
+			sig_cfg.clk_pol = true;
+		if (fbi->var.sync & FB_SYNC_DATA_INVERT)
+			sig_cfg.data_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+			sig_cfg.enable_pol = true;
+		if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
+			sig_cfg.clkidle_en = true;
+		if (fbi->var.sync & FB_SYNC_SHARP_MODE)
+			mode = IPU_PANEL_SHARP_TFT;
+
+		dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+			(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+		if (ipu_sdc_init_panel(mode,
+				       (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+				       fbi->var.xres, fbi->var.yres,
+				       (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
+				       IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
+				       fbi->var.left_margin,
+				       fbi->var.hsync_len,
+				       fbi->var.right_margin,
+				       fbi->var.upper_margin,
+				       fbi->var.vsync_len,
+				       fbi->var.lower_margin, sig_cfg) != 0) {
+			dev_err(fbi->device,
+				"mxcfb: Error initializing panel.\n");
+			return -EINVAL;
+		}
+
+		fbi->mode =
+		    (struct fb_videomode *)fb_match_mode(&fbi->var,
+							 &fbi->modelist);
+	}
+
+	ipu_disp_set_window_pos(mxc_fbi->ipu_ch, 0, 0);
+
+	mxc_fbi->cur_ipu_buf = 1;
+	sema_init(&mxc_fbi->flip_sem, 1);
+	fbi->var.xoffset = fbi->var.yoffset = 0;
+
+	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+					 bpp_to_pixfmt(fbi->var.bits_per_pixel),
+					 fbi->var.xres, fbi->var.yres,
+					 fbi->var.xres_virtual,
+					 IPU_ROTATE_NONE,
+					 fbi->fix.smem_start +
+					 (fbi->fix.line_length * fbi->var.yres),
+					 fbi->fix.smem_start,
+					 0, 0);
+	if (retval) {
+		dev_err(fbi->device,
+			"ipu_init_channel_buffer error %d\n", retval);
+		return retval;
+	}
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK) {
+		ipu_enable_channel(mxc_fbi->ipu_ch);
+	}
+
+	return 0;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param       var      framebuffer variable parameters
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	u32 vtotal;
+	u32 htotal;
+
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+#ifdef CONFIG_FB_MXC_INTERNAL_MEM
+	if ((info->fix.smem_start == FB_RAM_BASE_ADDR) &&
+	    ((var->yres_virtual * var->xres_virtual * var->bits_per_pixel / 8) >
+	     FB_RAM_SIZE)) {
+		return -EINVAL;
+	}
+#endif
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16)) {
+		var->bits_per_pixel = default_bpp;
+	}
+
+	switch (var->bits_per_pixel) {
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	if (var->pixclock < 1000) {
+		htotal = var->xres + var->right_margin + var->hsync_len +
+		    var->left_margin;
+		vtotal = var->yres + var->lower_margin + var->vsync_len +
+		    var->upper_margin;
+		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+		var->pixclock = KHZ2PICOS(var->pixclock);
+		dev_dbg(info->device,
+			"pixclock set for 60Hz refresh = %u ps\n",
+			var->pixclock);
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	/* nonstd used for YUV formats, but only RGB supported */
+	var->nonstd = 0;
+
+	return 0;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+static int
+mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+		u_int trans, struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * Function to handle custom ioctls for MXC framebuffer.
+ *
+ * @param       inode   inode struct
+ *
+ * @param       file    file struct
+ *
+ * @param       cmd     Ioctl command to handle
+ *
+ * @param       arg     User pointer to command arguments
+ *
+ * @param       fbi     framebuffer information pointer
+ */
+static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+	int __user *argp = (void __user *)arg;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	switch (cmd) {
+	case MXCFB_SET_GBL_ALPHA:
+		{
+			struct mxcfb_gbl_alpha ga;
+			if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval =
+			    ipu_sdc_set_global_alpha((bool) ga.enable,
+						     ga.alpha);
+			dev_dbg(fbi->device, "Set global alpha to %d\n",
+				ga.alpha);
+			break;
+		}
+	case MXCFB_SET_CLR_KEY:
+		{
+			struct mxcfb_color_key key;
+			if (copy_from_user(&key, (void *)arg, sizeof(key))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_sdc_set_color_key(MEM_SDC_BG, key.enable,
+						       key.color_key);
+			dev_dbg(fbi->device, "Set color key to 0x%08X\n",
+				key.color_key);
+			break;
+		}
+	case MXCFB_WAIT_FOR_VSYNC:
+		{
+#ifndef CONFIG_ARCH_MX3
+			mxcfb_drv_data.vsync_flag = 0;
+			ipu_enable_irq(IPU_IRQ_SDC_DISP3_VSYNC);
+			if (!wait_event_interruptible_timeout
+			    (mxcfb_drv_data.vsync_wq,
+			     mxcfb_drv_data.vsync_flag != 0, 1 * HZ)) {
+				dev_err(fbi->device,
+					"MXCFB_WAIT_FOR_VSYNC: timeout\n");
+				retval = -ETIME;
+				break;
+			} else if (signal_pending(current)) {
+				dev_err(fbi->device,
+					"MXCFB_WAIT_FOR_VSYNC: interrupt received\n");
+				retval = -ERESTARTSYS;
+				break;
+			}
+#endif
+			break;
+		}
+	case MXCFB_GET_FB_IPU_CHAN:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_ch, argp))
+				return -EFAULT;
+
+			break;
+		}
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*
+ * Function to handle custom ioctls for MXC framebuffer.
+ *
+ * @param       inode   inode struct
+ *
+ * @param       file    file struct
+ *
+ * @param       cmd     Ioctl command to handle
+ *
+ * @param       arg     User pointer to command arguments
+ *
+ * @param       fbi     framebuffer information pointer
+ */
+static int mxcfb_ioctl_ovl(struct fb_info *fbi, unsigned int cmd,
+			   unsigned long arg)
+{
+	int retval = 0;
+	int __user *argp = (void __user *)arg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	switch (cmd) {
+	case FBIO_ALLOC:
+		{
+			int size;
+			struct mxcfb_alloc_list *mem;
+
+			mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+			if (mem == NULL)
+				return -ENOMEM;
+
+			if (get_user(size, argp))
+				return -EFAULT;
+
+			mem->size = PAGE_ALIGN(size);
+
+			mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
+							   &mem->phy_addr,
+							   GFP_DMA);
+			if (mem->cpu_addr == NULL) {
+				kfree(mem);
+				return -ENOMEM;
+			}
+
+			list_add(&mem->list, &fb_alloc_list);
+
+			dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
+				mem->size, mem->phy_addr);
+
+			if (put_user(mem->phy_addr, argp))
+				return -EFAULT;
+
+			break;
+		}
+	case FBIO_FREE:
+		{
+			unsigned long offset;
+			struct mxcfb_alloc_list *mem;
+
+			if (get_user(offset, argp))
+				return -EFAULT;
+
+			retval = -EINVAL;
+			list_for_each_entry(mem, &fb_alloc_list, list) {
+				if (mem->phy_addr == offset) {
+					list_del(&mem->list);
+					dma_free_coherent(fbi->device,
+							  mem->size,
+							  mem->cpu_addr,
+							  mem->phy_addr);
+					kfree(mem);
+					retval = 0;
+					break;
+				}
+			}
+
+			break;
+		}
+	case MXCFB_SET_OVERLAY_POS:
+		{
+			struct mxcfb_pos pos;
+			if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_disp_set_window_pos(mxc_fbi->ipu_ch,
+							pos.x, pos.y);
+			break;
+		}
+	case MXCFB_GET_FB_IPU_CHAN:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_ch, argp))
+				return -EFAULT;
+
+			break;
+		}
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*
+ * mxcfb_blank():
+ *      Blank the display.
+ */
+static int mxcfb_blank(int blank, struct fb_info *info)
+{
+	int retval;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	dev_dbg(info->device, "blank = %d\n", blank);
+
+	if (mxc_fbi->blank == blank)
+		return 0;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	mxc_fbi->blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		ipu_disable_channel(MEM_SDC_BG, true);
+		gpio_lcd_inactive();
+		break;
+	case FB_BLANK_UNBLANK:
+		gpio_lcd_active();
+		ipu_enable_channel(MEM_SDC_BG);
+		break;
+	}
+	return 0;
+}
+
+/*
+ * mxcfb_blank_ovl():
+ *      Blank the display.
+ */
+static int mxcfb_blank_ovl(int blank, struct fb_info *info)
+{
+	int retval;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	dev_dbg(info->device, "ovl blank = %d\n", blank);
+
+	if (mxc_fbi->blank == blank)
+		return 0;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	mxc_fbi->blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		ipu_disable_channel(MEM_SDC_FG, true);
+		break;
+	case FB_BLANK_UNBLANK:
+		ipu_enable_channel(MEM_SDC_FG);
+		break;
+	}
+	return 0;
+}
+
+/*
+ * Pan or Wrap the Display
+ *
+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
+ *
+ * @param               var     Variable screen buffer information
+ * @param               info    Framebuffer information pointer
+ */
+static int
+mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+	unsigned long lock_flags = 0;
+	int retval;
+	u_int y_bottom;
+	unsigned long base;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	if (var->xoffset > 0) {
+		dev_dbg(info->device, "x panning not supported\n");
+		return -EINVAL;
+	}
+
+	if ((info->var.xoffset == var->xoffset) &&
+	    (info->var.yoffset == var->yoffset)) {
+		return 0;	// No change, do nothing
+	}
+
+	y_bottom = var->yoffset;
+
+	if (!(var->vmode & FB_VMODE_YWRAP)) {
+		y_bottom += var->yres;
+	}
+
+	if (y_bottom > info->var.yres_virtual) {
+		return -EINVAL;
+	}
+
+	base = (var->yoffset * var->xres_virtual + var->xoffset);
+	base *= (var->bits_per_pixel) / 8;
+	base += info->fix.smem_start;
+
+	down(&mxc_fbi->flip_sem);
+
+	spin_lock_irqsave(&mxc_fbi->fb_lock, lock_flags);
+
+	dev_dbg(info->device, "Updating SDC BG buf %d address=0x%08lX\n",
+		mxc_fbi->cur_ipu_buf, base);
+
+	mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+	if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				      mxc_fbi->cur_ipu_buf, base) == 0) {
+		ipu_select_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				  mxc_fbi->cur_ipu_buf);
+		ipu_clear_irq(mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu_ch_irq);
+	} else {
+		dev_err(info->device,
+			"Error updating SDC buf %d to address=0x%08lX\n",
+			mxc_fbi->cur_ipu_buf, base);
+	}
+
+	spin_unlock_irqrestore(&mxc_fbi->fb_lock, lock_flags);
+
+	dev_dbg(info->device, "Update complete\n");
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	if (var->vmode & FB_VMODE_YWRAP) {
+		info->var.vmode |= FB_VMODE_YWRAP;
+	} else {
+		info->var.vmode &= ~FB_VMODE_YWRAP;
+	}
+
+	return 0;
+}
+
+/*
+ * Function to handle custom mmap for MXC framebuffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       vma     Pointer to vm_area_struct
+ */
+static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
+{
+	bool found = false;
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+	struct mxcfb_alloc_list *mem;
+
+	if (offset < fbi->fix.smem_len) {
+		/* mapping framebuffer memory */
+		len = fbi->fix.smem_len - offset;
+		vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
+	} else {
+		list_for_each_entry(mem, &fb_alloc_list, list) {
+			if (offset == mem->phy_addr) {
+				found = true;
+				len = mem->size;
+				break;
+			}
+		}
+		if (!found) {
+			return -EINVAL;
+		}
+	}
+
+	len = PAGE_ALIGN(len);
+	if (vma->vm_end - vma->vm_start > len) {
+		return -EINVAL;
+	}
+
+	/* make buffers write-thru cacheable */
+	vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) &
+				     ~L_PTE_BUFFERABLE);
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+		dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
+		return -ENOBUFS;
+
+	}
+
+	return 0;
+}
+
+/*!
+ * This structure contains the pointers to the control functions that are
+ * invoked by the core framebuffer driver to perform operations like
+ * blitting, rectangle filling, copy regions and cursor definition.
+ */
+static struct fb_ops mxcfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_set_par = mxcfb_set_par,
+	.fb_check_var = mxcfb_check_var,
+	.fb_setcolreg = mxcfb_setcolreg,
+	.fb_pan_display = mxcfb_pan_display,
+	.fb_ioctl = mxcfb_ioctl,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_blank = mxcfb_blank,
+};
+
+static struct fb_ops mxcfb_ovl_ops = {
+	.owner = THIS_MODULE,
+	.fb_set_par = mxcfb_set_par,
+	.fb_check_var = mxcfb_check_var,
+	.fb_setcolreg = mxcfb_setcolreg,
+	.fb_pan_display = mxcfb_pan_display,
+	.fb_ioctl = mxcfb_ioctl_ovl,
+	.fb_mmap = mxcfb_mmap,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_blank = mxcfb_blank_ovl,
+};
+
+static irqreturn_t mxcfb_vsync_irq_handler(int irq, void *dev_id)
+{
+	struct mxcfb_data *fb_data = dev_id;
+
+	ipu_disable_irq(irq);
+
+	fb_data->vsync_flag = 1;
+	wake_up_interruptible(&fb_data->vsync_wq);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
+{
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	up(&mxc_fbi->flip_sem);
+	ipu_disable_irq(irq);
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_PM
+/*
+ * Power management hooks.      Note that we won't be called from IRQ context,
+ * unlike the blank functions above, so we may sleep.
+ */
+
+/*
+ * Suspends the framebuffer and blanks the screen. Power management support
+ */
+static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxcfb_data *drv_data = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)drv_data->fbi->par;
+	struct mxcfb_info *mxc_fbi_ovl =
+	    (struct mxcfb_info *)drv_data->fbi_ovl->par;
+#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
+	void *fbmem;
+#endif
+
+	drv_data->suspended = true;
+
+	acquire_console_sem();
+	fb_set_suspend(drv_data->fbi, 1);
+	fb_set_suspend(drv_data->fbi_ovl, 1);
+	release_console_sem();
+
+	if (mxc_fbi_ovl->blank == FB_BLANK_UNBLANK) {
+		ipu_disable_channel(MEM_SDC_FG, true);
+	}
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK) {
+#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
+		if (drv_data->fbi->fix.smem_start != FB_RAM_BASE_ADDR) {
+			fbmem = ioremap(FB_RAM_BASE_ADDR, FB_RAM_SIZE);
+			memcpy(fbmem, drv_data->fbi->screen_base, FB_RAM_SIZE);
+			iounmap(fbmem);
+			mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+			ipu_update_channel_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER,
+						  mxc_fbi->cur_ipu_buf,
+						  FB_RAM_BASE_ADDR);
+			ipu_select_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER,
+					  mxc_fbi->cur_ipu_buf);
+		}
+		ipu_lowpwr_display_enable();
+#else
+		ipu_disable_channel(MEM_SDC_BG, true);
+		gpio_lcd_inactive();
+#endif
+	}
+	return 0;
+}
+
+/*
+ * Resumes the framebuffer and unblanks the screen. Power management support
+ */
+static int mxcfb_resume(struct platform_device *pdev)
+{
+	struct mxcfb_data *drv_data = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)drv_data->fbi->par;
+	struct mxcfb_info *mxc_fbi_ovl =
+	    (struct mxcfb_info *)drv_data->fbi_ovl->par;
+
+	drv_data->suspended = false;
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK) {
+#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
+		ipu_lowpwr_display_disable();
+		if (drv_data->fbi->fix.smem_start != FB_RAM_BASE_ADDR) {
+			mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf;
+			ipu_update_channel_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER,
+						  mxc_fbi->cur_ipu_buf,
+						  drv_data->fbi->fix.
+						  smem_start);
+			ipu_select_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER,
+					  mxc_fbi->cur_ipu_buf);
+		}
+#else
+		gpio_lcd_active();
+		ipu_enable_channel(MEM_SDC_BG);
+#endif
+	}
+
+	if (mxc_fbi_ovl->blank == FB_BLANK_UNBLANK) {
+		ipu_enable_channel(MEM_SDC_FG);
+	}
+
+	acquire_console_sem();
+	fb_set_suspend(drv_data->fbi, 0);
+	fb_set_suspend(drv_data->fbi_ovl, 0);
+	release_console_sem();
+
+	wake_up_interruptible(&drv_data->suspend_wq);
+	return 0;
+}
+#else
+#define mxcfb_suspend   NULL
+#define mxcfb_resume    NULL
+#endif
+
+/*
+ * Main framebuffer functions
+ */
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       use_internal_ram flag on whether to use internal RAM for memory
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_map_video_memory(struct fb_info *fbi, bool use_internal_ram)
+{
+	int retval = 0;
+
+#ifdef CONFIG_FB_MXC_INTERNAL_MEM
+	if (use_internal_ram) {
+		fbi->fix.smem_len = FB_RAM_SIZE;
+		fbi->fix.smem_start = FB_RAM_BASE_ADDR;
+		if (fbi->fix.smem_len <
+		    (fbi->var.yres_virtual * fbi->fix.line_length)) {
+			dev_err(fbi->device,
+				"Not enough internal RAM for framebuffer configuration\n");
+			retval = -EINVAL;
+			goto err0;
+		}
+
+		if (request_mem_region(fbi->fix.smem_start, fbi->fix.smem_len,
+				       fbi->device->driver->name) == NULL) {
+			dev_err(fbi->device,
+				"Unable to request internal RAM\n");
+			retval = -ENOMEM;
+			goto err0;
+		}
+
+		if (!(fbi->screen_base = ioremap(fbi->fix.smem_start,
+						 fbi->fix.smem_len))) {
+			dev_err(fbi->device,
+				"Unable to map fb memory to virtual address\n");
+			release_mem_region(fbi->fix.smem_start,
+					   fbi->fix.smem_len);
+			retval = -EIO;
+			goto err0;
+		}
+
+		iram_clk = clk_get(NULL, "iram_clk");
+		clk_enable(iram_clk);
+	} else
+#endif
+	{
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+		    fbi->fix.line_length;
+		fbi->screen_base =
+		    dma_alloc_writecombine(fbi->device,
+					   fbi->fix.smem_len,
+					   (dma_addr_t *) & fbi->fix.smem_start,
+					   GFP_DMA);
+
+		if (fbi->screen_base == 0) {
+			dev_err(fbi->device,
+				"Unable to allocate framebuffer memory\n");
+			retval = -EBUSY;
+			goto err0;
+		}
+	}
+
+	dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+
+      err0:
+	fbi->fix.smem_len = 0;
+	fbi->fix.smem_start = 0;
+	fbi->screen_base = NULL;
+	return retval;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+#ifdef CONFIG_FB_MXC_INTERNAL_MEM
+	if (fbi->fix.smem_start == FB_RAM_BASE_ADDR) {
+		iounmap(fbi->screen_base);
+		release_mem_region(fbi->fix.smem_start, fbi->fix.smem_len);
+		fbi->fix.smem_start = 0;
+		fbi->fix.smem_len = 0;
+		clk_disable(iram_clk);
+	} else
+#endif
+	{
+		dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+				      fbi->screen_base, fbi->fix.smem_start);
+	}
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+/*!
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures.  This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return      Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
+	if (!fbi)
+		return NULL;
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+
+	fbi->fbops = ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+	spin_lock_init(&mxcfbi->fb_lock);
+
+	/*
+	 * Allocate colormap
+	 */
+	fb_alloc_cmap(&fbi->cmap, 16, 0);
+
+	return fbi;
+}
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(struct platform_device *pdev)
+{
+	char *mode = pdev->dev.platform_data;
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+	struct fb_info *fbi_ovl;
+	int ret = 0;
+
+	/*
+	 * Initialize FB structures
+	 */
+	fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
+	if (!fbi) {
+		ret = -ENOMEM;
+		goto err0;
+	}
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	mxcfbi->ipu_ch_irq = IPU_IRQ_SDC_BG_EOF;
+	mxcfbi->cur_ipu_buf = 0;
+	mxcfbi->ipu_ch = MEM_SDC_BG;
+
+	ipu_sdc_set_global_alpha(true, 0xFF);
+	ipu_sdc_set_color_key(MEM_SDC_BG, false, 0);
+
+	if (ipu_request_irq(IPU_IRQ_SDC_BG_EOF, mxcfb_irq_handler, 0,
+			    MXCFB_NAME, fbi) != 0) {
+		dev_err(&pdev->dev, "Error registering BG irq handler.\n");
+		ret = -EBUSY;
+		goto err1;
+	}
+	ipu_disable_irq(IPU_IRQ_SDC_BG_EOF);
+
+	if (fb_mode == NULL) {
+		fb_mode = mode;
+	}
+
+	if (!fb_find_mode(&fbi->var, fbi, fb_mode, mxcfb_modedb,
+			  mxcfb_modedb_sz, NULL, default_bpp)) {
+		ret = -EBUSY;
+		goto err2;
+	}
+	fb_videomode_to_modelist(mxcfb_modedb, mxcfb_modedb_sz, &fbi->modelist);
+
+	/* Default Y virtual size is 2x panel size */
+#ifndef CONFIG_FB_MXC_INTERNAL_MEM
+	fbi->var.yres_virtual = fbi->var.yres * 2;
+#endif
+
+	mxcfb_drv_data.fbi = fbi;
+	mxcfb_drv_data.backlight_level = 255;
+	mxcfb_drv_data.suspended = false;
+	init_waitqueue_head(&mxcfb_drv_data.suspend_wq);
+
+	mxcfbi->blank = FB_BLANK_NORMAL;
+	ret = mxcfb_set_par(fbi);
+	if (ret < 0) {
+		goto err2;
+	}
+	mxcfb_blank(FB_BLANK_UNBLANK, fbi);
+
+	/*
+	 * Register framebuffer
+	 */
+	ret = register_framebuffer(fbi);
+	if (ret < 0) {
+		goto err2;
+	}
+
+	/*
+	 * Initialize Overlay FB structures
+	 */
+	fbi_ovl = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ovl_ops);
+	if (!fbi_ovl) {
+		ret = -ENOMEM;
+		goto err3;
+	}
+	mxcfb_drv_data.fbi_ovl = fbi_ovl;
+	mxcfbi = (struct mxcfb_info *)fbi_ovl->par;
+
+	mxcfbi->ipu_ch_irq = IPU_IRQ_SDC_FG_EOF;
+	mxcfbi->cur_ipu_buf = 0;
+	mxcfbi->ipu_ch = MEM_SDC_FG;
+
+	if (ipu_request_irq(IPU_IRQ_SDC_FG_EOF, mxcfb_irq_handler, 0,
+			    MXCFB_NAME, fbi_ovl) != 0) {
+		dev_err(fbi->device, "Error registering FG irq handler.\n");
+		ret = -EBUSY;
+		goto err4;
+	}
+	ipu_disable_irq(mxcfbi->ipu_ch_irq);
+
+	/* Default Y virtual size is 2x panel size */
+	fbi_ovl->var = fbi->var;
+	fbi_ovl->var.yres_virtual = fbi->var.yres * 2;
+
+	/* Overlay is blanked by default */
+	mxcfbi->blank = FB_BLANK_NORMAL;
+
+	ret = mxcfb_set_par(fbi_ovl);
+	if (ret < 0) {
+		goto err5;
+	}
+
+	/*
+	 * Register overlay framebuffer
+	 */
+	ret = register_framebuffer(fbi_ovl);
+	if (ret < 0) {
+		goto err5;
+	}
+
+	platform_set_drvdata(pdev, &mxcfb_drv_data);
+
+	init_waitqueue_head(&mxcfb_drv_data.vsync_wq);
+	if (!cpu_is_mx31() && !cpu_is_mx32()) {
+		if ((ret = ipu_request_irq(IPU_IRQ_SDC_DISP3_VSYNC,
+					   mxcfb_vsync_irq_handler,
+					   0, MXCFB_NAME,
+					   &mxcfb_drv_data)) < 0) {
+			goto err6;
+		}
+		ipu_disable_irq(IPU_IRQ_SDC_DISP3_VSYNC);
+	}
+
+	printk(KERN_INFO "mxcfb: fb registered, using mode %s\n", fb_mode);
+	return 0;
+
+      err6:
+	unregister_framebuffer(fbi_ovl);
+      err5:
+	ipu_free_irq(IPU_IRQ_SDC_FG_EOF, fbi_ovl);
+      err4:
+	fb_dealloc_cmap(&fbi_ovl->cmap);
+	framebuffer_release(fbi_ovl);
+      err3:
+	unregister_framebuffer(fbi);
+      err2:
+	ipu_free_irq(IPU_IRQ_SDC_BG_EOF, fbi);
+      err1:
+	fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+      err0:
+	printk(KERN_ERR "mxcfb: failed to register fb\n");
+	return ret;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcfb_driver = {
+	.driver = {
+		   .name = MXCFB_NAME,
+		   },
+	.probe = mxcfb_probe,
+	.suspend = mxcfb_suspend,
+	.resume = mxcfb_resume,
+};
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * 	video=trident:800x600,bpp=16,noaccel
+ */
+int mxcfb_setup(char *options)
+{
+	char *opt;
+	if (!options || !*options)
+		return 0;
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+		if (!strncmp(opt, "bpp=", 4))
+			default_bpp = simple_strtoul(opt + 4, NULL, 0);
+		else
+			fb_mode = opt;
+	}
+	return 0;
+}
+
+/*!
+ * Main entry function for the framebuffer. The function registers the power
+ * management callback functions with the kernel and also registers the MXCFB
+ * callback functions with the core Linux framebuffer driver \b fbmem.c
+ *
+ * @return      Error code indicating success or failure
+ */
+int __init mxcfb_init(void)
+{
+	int ret = 0;
+#ifndef MODULE
+	char *option = NULL;
+#endif
+
+#ifndef MODULE
+	if (fb_get_options("mxcfb", &option))
+		return -ENODEV;
+	mxcfb_setup(option);
+#endif
+
+	ret = platform_driver_register(&mxcfb_driver);
+	return ret;
+}
+
+void mxcfb_exit(void)
+{
+	struct fb_info *fbi = mxcfb_drv_data.fbi;
+
+	if (fbi) {
+		mxcfb_unmap_video_memory(fbi);
+
+		if (&fbi->cmap)
+			fb_dealloc_cmap(&fbi->cmap);
+
+		unregister_framebuffer(fbi);
+		framebuffer_release(fbi);
+	}
+
+	fbi = mxcfb_drv_data.fbi_ovl;
+	if (fbi) {
+		mxcfb_unmap_video_memory(fbi);
+
+		if (&fbi->cmap)
+			fb_dealloc_cmap(&fbi->cmap);
+
+		unregister_framebuffer(fbi);
+		framebuffer_release(fbi);
+	}
+#ifndef CONFIG_ARCH_MX3
+	ipu_free_irq(IPU_IRQ_SDC_DISP3_VSYNC, &mxcfb_drv_data);
+#endif
+
+	platform_driver_unregister(&mxcfb_driver);
+}
+
+module_init(mxcfb_init);
+module_exit(mxcfb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxcfb_ch7026.c b/drivers/video/mxc/mxcfb_ch7026.c
new file mode 100644
index 000000000000..5610b75b7da7
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_ch7026.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb_epson_vga.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/mxcfb.h>
+#include <linux/ipu.h>
+#include <mach/hardware.h>
+
+static struct i2c_client *ch7026_client;
+
+static int lcd_init(void);
+static void lcd_poweron(struct fb_info *info);
+static void lcd_poweroff(void);
+
+static void (*lcd_reset) (void);
+static struct regulator *io_reg;
+static struct regulator *core_reg;
+static struct regulator *analog_reg;
+
+	/* 8 800x600-60 VESA */
+static struct fb_videomode mode = {
+	NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4,
+	FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA
+};
+
+static void lcd_init_fb(struct fb_info *info)
+{
+	struct fb_var_screeninfo var;
+
+	memset(&var, 0, sizeof(var));
+
+	fb_videomode_to_var(&var, &mode);
+
+	var.activate = FB_ACTIVATE_ALL;
+
+	acquire_console_sem();
+	info->flags |= FBINFO_MISC_USEREVENT;
+	fb_set_var(info, &var);
+	fb_blank(info, FB_BLANK_UNBLANK);
+	info->flags &= ~FBINFO_MISC_USEREVENT;
+	release_console_sem();
+}
+
+static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+
+	if (strcmp(event->info->fix.id, "DISP3 BG - DI1"))
+		return 0;
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		lcd_init_fb(event->info);
+		lcd_poweron(event->info);
+		break;
+	case FB_EVENT_BLANK:
+		if (*((int *)event->data) == FB_BLANK_UNBLANK)
+			lcd_poweron(event->info);
+		else
+			lcd_poweroff();
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = lcd_fb_event,
+};
+
+/*!
+ * This function is called whenever the SPI slave device is detected.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int __devinit lcd_probe(struct device *dev)
+{
+	int ret = 0;
+	int i;
+	struct mxc_lcd_platform_data *plat = dev->platform_data;
+
+	if (plat) {
+
+		io_reg = regulator_get(dev, plat->io_reg);
+		if (!IS_ERR(io_reg)) {
+			regulator_set_voltage(io_reg, 1800000, 1800000);
+			regulator_enable(io_reg);
+		} else {
+			io_reg = NULL;
+		}
+
+		core_reg = regulator_get(dev, plat->core_reg);
+		if (!IS_ERR(core_reg)) {
+			regulator_set_voltage(core_reg, 2500000, 2500000);
+			regulator_enable(core_reg);
+		} else {
+			core_reg = NULL;
+		}
+		analog_reg = regulator_get(dev, plat->analog_reg);
+		if (!IS_ERR(analog_reg)) {
+			regulator_set_voltage(analog_reg, 2775000, 2775000);
+			regulator_enable(analog_reg);
+		} else {
+			analog_reg = NULL;
+		}
+		msleep(100);
+
+		lcd_reset = plat->reset;
+		if (lcd_reset)
+			lcd_reset();
+	}
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG - DI1") == 0) {
+			ret = lcd_init();
+			if (ret < 0)
+				goto err;
+
+			lcd_init_fb(registered_fb[i]);
+			fb_show_logo(registered_fb[i], 0);
+			lcd_poweron(registered_fb[i]);
+		}
+	}
+
+	fb_register_client(&nb);
+	return 0;
+err:
+	if (io_reg)
+		regulator_disable(io_reg);
+	if (core_reg)
+		regulator_disable(core_reg);
+	if (analog_reg)
+		regulator_disable(analog_reg);
+
+	return ret;
+}
+
+static int __devinit ch7026_probe(struct i2c_client *client,
+				  const struct i2c_device_id *id)
+{
+	ch7026_client = client;
+
+	return lcd_probe(&client->dev);
+}
+
+static int __devexit ch7026_remove(struct i2c_client *client)
+{
+	fb_unregister_client(&nb);
+	lcd_poweroff();
+	regulator_put(io_reg);
+	regulator_put(core_reg);
+	regulator_put(analog_reg);
+
+	return 0;
+}
+
+static int ch7026_suspend(struct i2c_client *client, pm_message_t message)
+{
+	return 0;
+}
+
+static int ch7026_resume(struct i2c_client *client)
+{
+	return 0;
+}
+
+u8 reg_init[][2] = {
+	{ 0x02, 0x01 },
+	{ 0x02, 0x03 },
+	{ 0x03, 0x00 },
+	{ 0x06, 0x6B },
+	{ 0x08, 0x08 },
+	{ 0x09, 0x80 },
+	{ 0x0C, 0x0A },
+	{ 0x0D, 0x89 },
+	{ 0x0F, 0x23 },
+	{ 0x10, 0x20 },
+	{ 0x11, 0x20 },
+	{ 0x12, 0x40 },
+	{ 0x13, 0x28 },
+	{ 0x14, 0x80 },
+	{ 0x15, 0x52 },
+	{ 0x16, 0x58 },
+	{ 0x17, 0x74 },
+	{ 0x19, 0x01 },
+	{ 0x1A, 0x04 },
+	{ 0x1B, 0x23 },
+	{ 0x1C, 0x20 },
+	{ 0x1D, 0x20 },
+	{ 0x1F, 0x28 },
+	{ 0x20, 0x80 },
+	{ 0x21, 0x12 },
+	{ 0x22, 0x58 },
+	{ 0x23, 0x74 },
+	{ 0x25, 0x01 },
+	{ 0x26, 0x04 },
+	{ 0x37, 0x20 },
+	{ 0x39, 0x20 },
+	{ 0x3B, 0x20 },
+	{ 0x41, 0xA2 },
+	{ 0x4D, 0x03 },
+	{ 0x4E, 0x13 },
+	{ 0x4F, 0xB1 },
+	{ 0x50, 0x3B },
+	{ 0x51, 0x54 },
+	{ 0x52, 0x12 },
+	{ 0x53, 0x13 },
+	{ 0x55, 0xE5 },
+	{ 0x5E, 0x80 },
+	{ 0x69, 0x64 },
+	{ 0x7D, 0x62 },
+	{ 0x04, 0x00 },
+	{ 0x06, 0x69 },
+
+	/*
+	NOTE: The following five repeated sentences are used here to wait memory initial complete, please don't remove...(you could refer to Appendix A of programming guide document (CH7025(26)B Programming Guide Rev2.03.pdf) for detailed information about memory initialization!
+	*/
+	{ 0x03, 0x00 },
+	{ 0x03, 0x00 },
+	{ 0x03, 0x00 },
+	{ 0x03, 0x00 },
+	{ 0x03, 0x00 },
+
+	{ 0x06, 0x68 },
+	{ 0x02, 0x02 },
+	{ 0x02, 0x03 },
+};
+
+#define REGMAP_LENGTH (sizeof(reg_init) / (2*sizeof(u8)))
+
+/*
+ * Send init commands to L4F00242T03
+ *
+ */
+static int lcd_init(void)
+{
+	int i;
+	int dat;
+
+	dev_dbg(&ch7026_client->dev, "initializing CH7026\n");
+
+	/* read device ID */
+	msleep(100);
+	dat = i2c_smbus_read_byte_data(ch7026_client, 0x00);
+	dev_dbg(&ch7026_client->dev, "read id = 0x%02X\n", dat);
+	if (dat != 0x54)
+		return -ENODEV;
+
+	for (i = 0; i < REGMAP_LENGTH; ++i) {
+		if (i2c_smbus_write_byte_data
+		    (ch7026_client, reg_init[i][0], reg_init[i][1]) < 0)
+			return -EIO;
+	}
+
+	return 0;
+}
+
+static int lcd_on;
+/*
+ * Send Power On commands to L4F00242T03
+ *
+ */
+static void lcd_poweron(struct fb_info *info)
+{
+	u16 data[4];
+	u32 refresh;
+
+	if (lcd_on)
+		return;
+
+	dev_dbg(&ch7026_client->dev, "turning on LCD\n");
+
+	data[0] = PICOS2KHZ(info->var.pixclock) / 10;
+	data[2] = info->var.hsync_len + info->var.left_margin +
+	    info->var.xres + info->var.right_margin;
+	data[3] = info->var.vsync_len + info->var.upper_margin +
+	    info->var.yres + info->var.lower_margin;
+
+	refresh = data[2] * data[3];
+	refresh = (PICOS2KHZ(info->var.pixclock) * 1000) / refresh;
+	data[1] = refresh * 100;
+
+	lcd_on = 1;
+}
+
+/*
+ * Send Power Off commands to L4F00242T03
+ *
+ */
+static void lcd_poweroff(void)
+{
+	if (!lcd_on)
+		return;
+
+	dev_dbg(&ch7026_client->dev, "turning off LCD\n");
+
+	lcd_on = 0;
+}
+
+static const struct i2c_device_id ch7026_id[] = {
+	{"ch7026", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, ch7026_id);
+
+static struct i2c_driver ch7026_driver = {
+	.driver = {
+		   .name = "ch7026",
+		   },
+	.probe = ch7026_probe,
+	.remove = ch7026_remove,
+	.suspend = ch7026_suspend,
+	.resume = ch7026_resume,
+	.id_table = ch7026_id,
+};
+
+static int __init ch7026_init(void)
+{
+	return i2c_add_driver(&ch7026_driver);
+}
+
+static void __exit ch7026_exit(void)
+{
+	i2c_del_driver(&ch7026_driver);
+}
+
+module_init(ch7026_init);
+module_exit(ch7026_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("CH7026 VGA driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxcfb_claa_wvga.c b/drivers/video/mxc/mxcfb_claa_wvga.c
new file mode 100644
index 000000000000..8f696c19e7d9
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_claa_wvga.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb_claa_wvga.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+
+static void lcd_poweron(void);
+static void lcd_poweroff(void);
+
+static struct platform_device *plcd_dev;
+static struct regulator *io_reg;
+static struct regulator *core_reg;
+static int lcd_on;
+
+static struct fb_videomode video_modes[] = {
+	{
+	 /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
+	 "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
+	 FB_SYNC_CLK_LAT_FALL,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+static void lcd_init_fb(struct fb_info *info)
+{
+	struct fb_var_screeninfo var;
+
+	memset(&var, 0, sizeof(var));
+
+	fb_videomode_to_var(&var, &video_modes[0]);
+
+	var.activate = FB_ACTIVATE_ALL;
+	var.yres_virtual = var.yres * 3;
+
+	acquire_console_sem();
+	info->flags |= FBINFO_MISC_USEREVENT;
+	fb_set_var(info, &var);
+	info->flags &= ~FBINFO_MISC_USEREVENT;
+	release_console_sem();
+}
+
+static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+
+	if (strcmp(event->info->fix.id, "DISP3 BG") &&
+	    strcmp(event->info->fix.id, "mxc_elcdif_fb"))
+		return 0;
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		lcd_init_fb(event->info);
+		fb_show_logo(event->info, 0);
+		lcd_poweron();
+		break;
+	case FB_EVENT_BLANK:
+		if ((event->info->var.xres != 800) ||
+		    (event->info->var.yres != 480)) {
+			break;
+		}
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			lcd_poweron();
+		} else {
+			lcd_poweroff();
+		}
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = lcd_fb_event,
+};
+
+/*!
+ * This function is called whenever the SPI slave device is detected.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int __devinit lcd_probe(struct platform_device *pdev)
+{
+	int i;
+	struct mxc_lcd_platform_data *plat = pdev->dev.platform_data;
+
+	if (plat) {
+		if (plat->reset)
+			plat->reset();
+
+		io_reg = regulator_get(&pdev->dev, plat->io_reg);
+		if (IS_ERR(io_reg))
+			io_reg = NULL;
+		core_reg = regulator_get(&pdev->dev, plat->core_reg);
+		if (!IS_ERR(core_reg)) {
+			regulator_set_voltage(io_reg, 1800000, 1800000);
+		} else {
+			core_reg = NULL;
+		}
+	}
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0 ||
+		    strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) {
+			lcd_init_fb(registered_fb[i]);
+			fb_show_logo(registered_fb[i], 0);
+			lcd_poweron();
+		} else if (strcmp(registered_fb[i]->fix.id, "DISP3 FG") == 0) {
+			lcd_init_fb(registered_fb[i]);
+		}
+	}
+
+	fb_register_client(&nb);
+
+	plcd_dev = pdev;
+
+	return 0;
+}
+
+static int __devexit lcd_remove(struct platform_device *pdev)
+{
+	fb_unregister_client(&nb);
+	lcd_poweroff();
+	if (io_reg)
+		regulator_put(io_reg);
+	if (core_reg)
+		regulator_put(core_reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lcd_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int lcd_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define lcd_suspend NULL
+#define lcd_resume NULL
+#endif
+
+/*!
+ * platform driver structure for CLAA WVGA
+ */
+static struct platform_driver lcd_driver = {
+	.driver = {
+		   .name = "lcd_claa"},
+	.probe = lcd_probe,
+	.remove = __devexit_p(lcd_remove),
+	.suspend = lcd_suspend,
+	.resume = lcd_resume,
+};
+
+/*
+ * Send Power On commands to L4F00242T03
+ *
+ */
+static void lcd_poweron(void)
+{
+	if (lcd_on)
+		return;
+
+	dev_dbg(&plcd_dev->dev, "turning on LCD\n");
+	if (core_reg)
+		regulator_enable(core_reg);
+	if (io_reg)
+		regulator_enable(io_reg);
+	lcd_on = 1;
+}
+
+/*
+ * Send Power Off commands to L4F00242T03
+ *
+ */
+static void lcd_poweroff(void)
+{
+	lcd_on = 0;
+	dev_dbg(&plcd_dev->dev, "turning off LCD\n");
+	if (io_reg)
+		regulator_disable(io_reg);
+	if (core_reg)
+		regulator_disable(core_reg);
+}
+
+static int __init claa_lcd_init(void)
+{
+	return platform_driver_register(&lcd_driver);
+}
+
+static void __exit claa_lcd_exit(void)
+{
+	platform_driver_unregister(&lcd_driver);
+}
+
+module_init(claa_lcd_init);
+module_exit(claa_lcd_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("CLAA WVGA LCD init driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxcfb_epson.c b/drivers/video/mxc/mxcfb_epson.c
new file mode 100644
index 000000000000..25b05e4b1a0e
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_epson.c
@@ -0,0 +1,1158 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxcfb_epson.c
+ *
+ * @brief MXC Frame buffer driver for ADC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/uaccess.h>
+#include <mach/ipu.h>
+#include <mach/mxcfb.h>
+
+#define PARTIAL_REFRESH
+#define MXCFB_REFRESH_DEFAULT MXCFB_REFRESH_PARTIAL
+/*
+ * Driver name
+ */
+#define MXCFB_NAME      "MXCFB_EPSON"
+
+#define MXCFB_SCREEN_TOP_OFFSET         0
+#define MXCFB_SCREEN_LEFT_OFFSET        2
+#define MXCFB_SCREEN_WIDTH              176
+#define MXCFB_SCREEN_HEIGHT             220
+
+/*!
+ * Enum defining Epson panel commands.
+ */
+enum {
+	DISON = 0xAF,
+	DISOFF = 0xAE,
+	DISCTL = 0xCA,
+	SD_CSET = 0x15,
+	SD_PSET = 0x75,
+	DATCTL = 0xBC,
+	SLPIN = 0x95,
+	SLPOUT = 0x94,
+	DISNOR = 0xA6,
+	RAMWR = 0x5C,
+	VOLCTR = 0xC6,
+	GCP16 = 0xCC,
+	GCP64 = 0xCB,
+};
+
+struct mxcfb_info {
+	int open_count;
+	int blank;
+	uint32_t disp_num;
+
+	u32 pseudo_palette[16];
+
+	int32_t cur_update_mode;
+	dma_addr_t alloc_start_paddr;
+	void *alloc_start_vaddr;
+	u32 alloc_size;
+	uint32_t snoop_window_size;
+};
+
+struct mxcfb_data {
+	struct fb_info *fbi;
+	volatile int32_t vsync_flag;
+	wait_queue_head_t vsync_wq;
+	wait_queue_head_t suspend_wq;
+	bool suspended;
+};
+
+static struct mxcfb_data mxcfb_drv_data;
+static unsigned long default_bpp = 16;
+
+void slcd_gpio_config(void);
+extern void gpio_lcd_active(void);
+static int mxcfb_blank(int blank, struct fb_info *fbi);
+
+static uint32_t bpp_to_pixfmt(int bpp)
+{
+	uint32_t pixfmt = 0;
+	switch (bpp) {
+	case 24:
+		pixfmt = IPU_PIX_FMT_BGR24;
+		break;
+	case 32:
+		pixfmt = IPU_PIX_FMT_BGR32;
+		break;
+	case 16:
+		pixfmt = IPU_PIX_FMT_RGB565;
+		break;
+	}
+	return pixfmt;
+}
+
+/*!
+ * This function sets display region in the Epson panel
+ *
+ * @param        disp    display panel to config
+ * @param	 x1	 x-coordinate of one vertex.
+ * @param	 x2	 x-coordinate of second vertex.
+ * @param	 y1	 y-coordinate of one vertex.
+ * @param	 y2	 y-coordinate of second vertex.
+ */
+void set_panel_region(int disp, uint32_t x1, uint32_t x2,
+		      uint32_t y1, uint32_t y2)
+{
+	uint32_t param[8];
+
+	memset(param, 0, sizeof(uint32_t) * 8);
+	param[0] = x1;
+	param[2] = x2;
+	param[4] = y1;
+	param[6] = y2;
+
+	// SD_CSET
+	ipu_adc_write_cmd(disp, CMD, SD_CSET, param, 4);
+	// SD_PSET
+
+	ipu_adc_write_cmd(disp, CMD, SD_PSET, &(param[4]), 4);
+}
+
+/*!
+ * Function to create and initiate template command buffer for ADC. This
+ * template will be written to Panel memory.
+ */
+static void init_channel_template(int disp)
+{
+	/* template command buffer for ADC is 32 */
+	uint32_t tempCmd[TEMPLATE_BUF_SIZE];
+	uint32_t i = 0;
+
+	memset(tempCmd, 0, sizeof(uint32_t) * TEMPLATE_BUF_SIZE);
+	/* setup update display region */
+	/* whole the screen during init */
+	/*WRITE Y COORDINATE CMND */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, SD_PSET);
+	/*WRITE Y START ADDRESS CMND LSB[22:8] */
+	tempCmd[i++] = ipu_adc_template_gen(WR_YADDR, 1, SINGLE_STEP, 0x01);
+	/*WRITE Y START ADDRESS CMND MSB[22:16] */
+	tempCmd[i++] = ipu_adc_template_gen(WR_YADDR, 1, SINGLE_STEP, 0x09);
+	/*WRITE Y STOP ADDRESS CMND LSB */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP,
+					    MXCFB_SCREEN_HEIGHT - 1);
+	/*WRITE Y STOP ADDRESS CMND MSB */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0);
+	/*WRITE X COORDINATE CMND */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, SD_CSET);
+	/*WRITE X ADDRESS CMND LSB[7:0] */
+	tempCmd[i++] = ipu_adc_template_gen(WR_XADDR, 1, SINGLE_STEP, 0x01);
+	/*WRITE X ADDRESS CMND MSB[22:8] */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0);
+	/*WRITE X STOP ADDRESS CMND LSB */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP,
+					    MXCFB_SCREEN_WIDTH + 1);
+	/*WRITE X STOP ADDRESS CMND MSB */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0);
+	/*WRITE MEMORY CMND MSB */
+	tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, RAMWR);
+	/*WRITE DATA CMND and STP */
+	tempCmd[i++] = ipu_adc_template_gen(WR_DATA, 1, STOP, 0);
+
+	ipu_adc_write_template(disp, tempCmd, true);
+}
+
+/*!
+ * Function to initialize the panel. First it resets the panel and then
+ * initilizes panel.
+ */
+static void _init_panel(int disp)
+{
+	uint32_t cmd_param;
+	uint32_t i;
+
+	gpio_lcd_active();
+	slcd_gpio_config();
+
+	// DATCTL
+#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT
+	// 16-bit 565 mode
+	cmd_param = 0x28;
+#else
+	// 8-bit 666 mode
+	cmd_param = 0x08;
+#endif
+	ipu_adc_write_cmd(disp, CMD, DATCTL, &cmd_param, 1);
+
+	// Sleep OUT
+	ipu_adc_write_cmd(disp, CMD, SLPOUT, 0, 0);
+
+	// Set display to white
+	// Setup page and column addresses
+	set_panel_region(disp, MXCFB_SCREEN_LEFT_OFFSET,
+			 MXCFB_SCREEN_WIDTH + MXCFB_SCREEN_LEFT_OFFSET - 1,
+			 0, MXCFB_SCREEN_HEIGHT - 1);
+	// Do RAM write cmd
+	ipu_adc_write_cmd(disp, CMD, RAMWR, 0, 0);
+#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT
+	for (i = 0; i < (MXCFB_SCREEN_WIDTH * MXCFB_SCREEN_HEIGHT); i++)
+#else
+	for (i = 0; i < (MXCFB_SCREEN_WIDTH * MXCFB_SCREEN_HEIGHT * 3); i++)
+#endif
+		ipu_adc_write_cmd(disp, DAT, 0xFFFF, 0, 0);
+
+	// Pause 80 ms
+	mdelay(80);
+
+	// Display ON
+	ipu_adc_write_cmd(disp, CMD, DISON, 0, 0);
+	// Pause 200 ms
+	mdelay(200);
+
+	pr_debug("initialized panel\n");
+}
+
+#ifdef PARTIAL_REFRESH
+static irqreturn_t mxcfb_sys2_eof_irq_handler(int irq, void *dev_id)
+{
+	ipu_channel_params_t params;
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+	uint32_t stat[2], seg_size;
+	uint32_t lsb, msb;
+	uint32_t update_height, start_line, start_addr, end_line, end_addr;
+	uint32_t stride_pixels = (fbi->fix.line_length * 8) /
+	    fbi->var.bits_per_pixel;
+
+	ipu_adc_get_snooping_status(&stat[0], &stat[1]);
+	//DPRINTK("snoop status = 0x%08X%08X\n", stat[1], stat[0]);
+
+	if (!stat[0] && !stat[1]) {
+		dev_err(fbi->device, "error no bus snooping bits set\n");
+		return IRQ_HANDLED;
+	}
+	ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF);
+
+	lsb = ffs(stat[0]);
+	if (lsb) {
+		lsb--;
+	} else {
+		lsb = ffs(stat[1]);
+		lsb += 32 - 1;
+	}
+	msb = fls(stat[1]);
+	if (msb) {
+		msb += 32;
+	} else {
+		msb = fls(stat[0]);
+	}
+
+	seg_size = mxc_fbi->snoop_window_size / 64;
+
+	start_addr = lsb * seg_size;	// starting address offset
+	start_line = start_addr / fbi->fix.line_length;
+	start_addr = start_line * fbi->fix.line_length;	// Addr aligned to line
+	start_addr += fbi->fix.smem_start;
+
+	end_addr = msb * seg_size;	// ending address offset
+	end_line = end_addr / fbi->fix.line_length;
+	end_line++;
+
+	if (end_line > fbi->var.yres) {
+		end_line = fbi->var.yres;
+	}
+
+	update_height = end_line - start_line;
+	dev_dbg(fbi->device, "updating rows %d to %d, start addr = 0x%08X\n",
+		start_line, end_line, start_addr);
+
+	ipu_uninit_channel(ADC_SYS1);
+	params.adc_sys1.disp = mxc_fbi->disp_num;
+	params.adc_sys1.ch_mode = WriteTemplateNonSeq;
+	params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET;
+	params.adc_sys1.out_top = start_line;
+	ipu_init_channel(ADC_SYS1, &params);
+
+	ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER,
+				bpp_to_pixfmt(fbi->var.bits_per_pixel),
+				MXCFB_SCREEN_WIDTH,
+				update_height,
+				stride_pixels,
+				IPU_ROTATE_NONE, (dma_addr_t) start_addr, 0,
+				0, 0);
+	ipu_enable_channel(ADC_SYS1);
+	ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0);
+	ipu_enable_irq(IPU_IRQ_ADC_SYS1_EOF);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxcfb_sys1_eof_irq_handler(int irq, void *dev_id)
+{
+	ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF);
+	ipu_disable_channel(ADC_SYS1, false);
+
+	ipu_enable_channel(ADC_SYS2);
+	ipu_enable_irq(IPU_IRQ_ADC_SYS2_EOF);
+
+	return IRQ_HANDLED;
+}
+#endif
+
+/*!
+ * Function to initialize Asynchronous Display Controller. It also initilizes
+ * the ADC System 1 channel. Configure ADC display 0 parallel interface for
+ * the panel.
+ *
+ * @param       fbi     framebuffer information pointer
+ */
+static void mxcfb_init_panel(struct fb_info *fbi)
+{
+	int msb;
+	int panel_stride;
+	ipu_channel_params_t params;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT
+	uint32_t pix_fmt = IPU_PIX_FMT_RGB565;
+	ipu_adc_sig_cfg_t sig = { 0, 0, 0, 0, 0, 0, 0, 0,
+		IPU_ADC_BURST_WCS,
+		IPU_ADC_IFC_MODE_SYS80_TYPE2,
+		16, 0, 0, IPU_ADC_SER_NO_RW
+	};
+	mxc_fbi->disp_num = DISP0;
+#elif defined(CONFIG_FB_MXC_ASYNC_PANEL_IFC_8_BIT)
+	uint32_t pix_fmt = IPU_PIX_FMT_RGB666;
+	ipu_adc_sig_cfg_t sig = { 0, 0, 0, 0, 0, 0, 0, 0,
+		IPU_ADC_BURST_WCS,
+		IPU_ADC_IFC_MODE_SYS80_TYPE2,
+		8, 0, 0, IPU_ADC_SER_NO_RW
+	};
+	mxc_fbi->disp_num = DISP0;
+#else
+	uint32_t pix_fmt = IPU_PIX_FMT_RGB565;
+	ipu_adc_sig_cfg_t sig = { 0, 1, 0, 0, 0, 0, 0, 0,
+		IPU_ADC_BURST_SERIAL,
+		IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
+		16, 0, 0, IPU_ADC_SER_NO_RW
+	};
+	fbi->disp_num = DISP1;
+#endif
+
+#ifdef PARTIAL_REFRESH
+	if (ipu_request_irq(IPU_IRQ_ADC_SYS2_EOF, mxcfb_sys2_eof_irq_handler, 0,
+			    MXCFB_NAME, fbi) != 0) {
+		dev_err(fbi->device, "Error registering SYS2 irq handler.\n");
+		return;
+	}
+
+	if (ipu_request_irq(IPU_IRQ_ADC_SYS1_EOF, mxcfb_sys1_eof_irq_handler, 0,
+			    MXCFB_NAME, fbi) != 0) {
+		dev_err(fbi->device, "Error registering SYS1 irq handler.\n");
+		return;
+	}
+	ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF);
+	ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF);
+#endif
+	// Init DI interface
+	msb = fls(MXCFB_SCREEN_WIDTH);
+	if (!(MXCFB_SCREEN_WIDTH & ((1UL << msb) - 1)))
+		msb--;		// Already aligned to power 2
+	panel_stride = 1UL << msb;
+	ipu_adc_init_panel(mxc_fbi->disp_num,
+			   MXCFB_SCREEN_WIDTH + MXCFB_SCREEN_LEFT_OFFSET,
+			   MXCFB_SCREEN_HEIGHT,
+			   pix_fmt, panel_stride, sig, XY, 0, VsyncInternal);
+
+	ipu_adc_init_ifc_timing(mxc_fbi->disp_num, true,
+				190, 17, 104, 190, 5000000);
+	ipu_adc_init_ifc_timing(mxc_fbi->disp_num, false, 123, 17, 68, 0, 0);
+
+	// Needed to turn on ADC clock for panel init
+	memset(&params, 0, sizeof(params));
+	params.adc_sys1.disp = mxc_fbi->disp_num;
+	params.adc_sys1.ch_mode = WriteTemplateNonSeq;
+	params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET;
+	params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET;
+	ipu_init_channel(ADC_SYS1, &params);
+
+	_init_panel(mxc_fbi->disp_num);
+	init_channel_template(mxc_fbi->disp_num);
+}
+
+int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
+			   struct mxcfb_rect *update_region)
+{
+	unsigned long start_addr;
+	int ret_mode;
+	uint32_t dummy;
+	ipu_channel_params_t params;
+	struct mxcfb_rect rect;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	uint32_t stride_pixels = (fbi->fix.line_length * 8) /
+	    fbi->var.bits_per_pixel;
+	uint32_t memsize = fbi->fix.smem_len;
+
+	if (mxc_fbi->cur_update_mode == mode)
+		return mode;
+
+	ret_mode = mxc_fbi->cur_update_mode;
+
+	ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF);
+	ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE, 0, 0, 0);
+#ifdef PARTIAL_REFRESH
+	ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF);
+	ipu_adc_set_update_mode(ADC_SYS2, IPU_ADC_REFRESH_NONE, 0, 0, 0);
+#endif
+
+	ipu_disable_channel(ADC_SYS1, true);
+	ipu_clear_irq(IPU_IRQ_ADC_SYS1_EOF);
+#ifdef PARTIAL_REFRESH
+	ipu_disable_channel(ADC_SYS2, true);
+	ipu_clear_irq(IPU_IRQ_ADC_SYS2_EOF);
+#endif
+	ipu_adc_get_snooping_status(&dummy, &dummy);
+
+	mxc_fbi->cur_update_mode = mode;
+
+	switch (mode) {
+	case MXCFB_REFRESH_OFF:
+		if (ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE,
+					    0, 0, 0) < 0)
+			dev_err(fbi->device, "Error enabling auto refesh.\n");
+		if (ipu_adc_set_update_mode(ADC_SYS2, IPU_ADC_REFRESH_NONE,
+					    0, 0, 0) < 0)
+			dev_err(fbi->device, "Error enabling auto refesh.\n");
+#if 0
+		ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER,
+					bpp_to_pixfmt(fbi->var.bits_per_pixel),
+					1, 1, 4,
+					IPU_ROTATE_NONE,
+					fbi->fix.smem_start,
+					fbi->fix.smem_start, 0, 0);
+		ipu_enable_channel(ADC_SYS2);
+		ipu_select_buffer(ADC_SYS2, IPU_INPUT_BUFFER, 0);
+		ipu_select_buffer(ADC_SYS2, IPU_INPUT_BUFFER, 1);
+		msleep(10);
+#endif
+		ipu_uninit_channel(ADC_SYS1);
+#ifdef PARTIAL_REFRESH
+		ipu_uninit_channel(ADC_SYS2);
+#endif
+		break;
+	case MXCFB_REFRESH_PARTIAL:
+#ifdef PARTIAL_REFRESH
+		ipu_adc_get_snooping_status(&dummy, &dummy);
+
+		params.adc_sys2.disp = DISP0;
+		params.adc_sys2.ch_mode = WriteTemplateNonSeq;
+		params.adc_sys2.out_left = 0;
+		params.adc_sys2.out_top = 0;
+		ipu_init_channel(ADC_SYS2, &params);
+
+		if (ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE,
+					    0, 0, 0) < 0) {
+			dev_err(fbi->device, "Error enabling auto refesh.\n");
+		}
+		if (ipu_adc_set_update_mode
+		    (ADC_SYS2, IPU_ADC_AUTO_REFRESH_SNOOP, 30,
+		     fbi->fix.smem_start, &memsize) < 0) {
+			dev_err(fbi->device, "Error enabling auto refesh.\n");
+		}
+		mxc_fbi->snoop_window_size = memsize;
+
+		ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER,
+					bpp_to_pixfmt(fbi->var.bits_per_pixel),
+					1, 1, 4,
+					IPU_ROTATE_NONE,
+					fbi->fix.smem_start, 0, 0, 0);
+
+		params.adc_sys1.disp = mxc_fbi->disp_num;
+		params.adc_sys1.ch_mode = WriteTemplateNonSeq;
+		params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET;
+		params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET;
+		ipu_init_channel(ADC_SYS1, &params);
+
+		ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER,
+					bpp_to_pixfmt(fbi->var.bits_per_pixel),
+					MXCFB_SCREEN_WIDTH, MXCFB_SCREEN_HEIGHT,
+					stride_pixels, IPU_ROTATE_NONE,
+					fbi->fix.smem_start, 0, 0, 0);
+		ipu_enable_channel(ADC_SYS1);
+		ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0);
+		ipu_enable_irq(IPU_IRQ_ADC_SYS1_EOF);
+		break;
+#endif
+	case MXCFB_REFRESH_AUTO:
+		if (update_region == NULL) {
+			update_region = &rect;
+			rect.top = 0;
+			rect.left = 0;
+			rect.height = MXCFB_SCREEN_HEIGHT;
+			rect.width = MXCFB_SCREEN_WIDTH;
+		}
+		params.adc_sys1.disp = mxc_fbi->disp_num;
+		params.adc_sys1.ch_mode = WriteTemplateNonSeq;
+		params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET +
+		    update_region->left;
+		params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET +
+		    update_region->top;
+		ipu_init_channel(ADC_SYS1, &params);
+
+		// Address aligned to line
+		start_addr = update_region->top * fbi->fix.line_length;
+		start_addr += fbi->fix.smem_start;
+		start_addr += update_region->left * fbi->var.bits_per_pixel / 8;
+
+		ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER,
+					bpp_to_pixfmt(fbi->var.bits_per_pixel),
+					update_region->width,
+					update_region->height, stride_pixels,
+					IPU_ROTATE_NONE, start_addr, 0, 0, 0);
+		ipu_enable_channel(ADC_SYS1);
+		ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0);
+
+		if (ipu_adc_set_update_mode
+		    (ADC_SYS1, IPU_ADC_AUTO_REFRESH_SNOOP, 30,
+		     fbi->fix.smem_start, &memsize) < 0)
+			dev_err(fbi->device, "Error enabling auto refesh.\n");
+
+		mxc_fbi->snoop_window_size = memsize;
+
+		break;
+	}
+	return ret_mode;
+}
+
+/*
+ * Open the main framebuffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       user    Set if opened by user or clear if opened by kernel
+ */
+static int mxcfb_open(struct fb_info *fbi, int user)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	mxc_fbi->open_count++;
+
+	retval = mxcfb_blank(FB_BLANK_UNBLANK, fbi);
+	return retval;
+}
+
+/*
+ * Close the main framebuffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       user    Set if opened by user or clear if opened by kernel
+ */
+static int mxcfb_release(struct fb_info *fbi, int user)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	--mxc_fbi->open_count;
+	if (mxc_fbi->open_count == 0) {
+		retval = mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
+	}
+	return retval;
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	// Set framebuffer id to IPU display number.
+	strcpy(fix->id, "DISP0 FB");
+	fix->id[4] = '0' + mxc_fbi->disp_num;
+
+	// Init settings based on the panel size
+	fix->line_length = MXCFB_SCREEN_WIDTH * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 0;
+	fix->ypanstep = 0;
+
+	return 0;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+	int retval = 0;
+	int mode;
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	mode = mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL);
+
+	mxcfb_set_fix(fbi);
+
+	if (mode != MXCFB_REFRESH_OFF) {
+#ifdef PARTIAL_REFRESH
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_PARTIAL, NULL);
+#else
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_AUTO, NULL);
+#endif
+	}
+	return 0;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param       var      framebuffer variable parameters
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
+{
+	if (var->xres > MXCFB_SCREEN_WIDTH)
+		var->xres = MXCFB_SCREEN_WIDTH;
+	if (var->yres > MXCFB_SCREEN_HEIGHT)
+		var->yres = MXCFB_SCREEN_HEIGHT;
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16)) {
+		var->bits_per_pixel = default_bpp;
+	}
+
+	switch (var->bits_per_pixel) {
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+	var->nonstd = 0;
+
+	var->pixclock = -1;
+	var->left_margin = -1;
+	var->right_margin = -1;
+	var->upper_margin = -1;
+	var->lower_margin = -1;
+	var->hsync_len = -1;
+	var->vsync_len = -1;
+
+	var->vmode = FB_VMODE_NONINTERLACED;
+	var->sync = 0;
+
+	return 0;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+static int
+mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+		u_int trans, struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * mxcfb_blank():
+ *      Blank the display.
+ */
+static int mxcfb_blank(int blank, struct fb_info *fbi)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	dev_dbg(fbi->device, "blank = %d\n", blank);
+
+	if ((retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq,
+					       (mxcfb_drv_data.suspended ==
+						false))) < 0) {
+		return retval;
+	}
+
+	mxc_fbi->blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL);
+		break;
+	case FB_BLANK_UNBLANK:
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_DEFAULT, NULL);
+		break;
+	}
+	return 0;
+}
+
+/*!
+ * This structure contains the pointers to the control functions that are
+ * invoked by the core framebuffer driver to perform operations like
+ * blitting, rectangle filling, copy regions and cursor definition.
+ */
+static struct fb_ops mxcfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_open = mxcfb_open,
+	.fb_release = mxcfb_release,
+	.fb_set_par = mxcfb_set_par,
+	.fb_check_var = mxcfb_check_var,
+	.fb_setcolreg = mxcfb_setcolreg,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_blank = mxcfb_blank,
+};
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_map_video_memory(struct fb_info *fbi)
+{
+	u32 msb;
+	u32 offset;
+	struct mxcfb_info *mxcfbi = fbi->par;
+
+	fbi->fix.smem_len = fbi->var.xres_virtual * fbi->var.yres_virtual * 4;
+
+	// Set size to power of 2.
+	msb = fls(fbi->fix.smem_len);
+	if (!(fbi->fix.smem_len & ((1UL << msb) - 1)))
+		msb--;		// Already aligned to power 2
+	if (msb < 11)
+		msb = 11;
+	mxcfbi->alloc_size = (1UL << msb) * 2;
+
+	mxcfbi->alloc_start_vaddr = dma_alloc_coherent(fbi->device,
+						       mxcfbi->alloc_size,
+						       &mxcfbi->
+						       alloc_start_paddr,
+						       GFP_KERNEL | GFP_DMA);
+
+	if (mxcfbi->alloc_start_vaddr == 0) {
+		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+		return -ENOMEM;
+	}
+	dev_dbg(fbi->device, "allocated fb memory @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) mxcfbi->alloc_start_paddr, mxcfbi->alloc_size);
+
+	offset =
+	    ((mxcfbi->alloc_size / 2) - 1) & ~((mxcfbi->alloc_size / 2) - 1);
+	fbi->fix.smem_start = mxcfbi->alloc_start_paddr + offset;
+	dev_dbg(fbi->device, "aligned fb start @ paddr=0x%08lX, size=%u.\n",
+		fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_base = mxcfbi->alloc_start_vaddr + offset;
+
+	/* Clear the screen */
+	memset(fbi->screen_base, 0, fbi->fix.smem_len);
+	return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	dma_free_coherent(fbi->device, mxc_fbi->alloc_size,
+			  mxc_fbi->alloc_start_vaddr,
+			  mxc_fbi->alloc_start_paddr);
+	return 0;
+}
+
+/*!
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures.  This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return      Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
+	if (!fbi)
+		return NULL;
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	/*
+	 * Fill in fb_info structure information
+	 */
+	fbi->var.xres = fbi->var.xres_virtual = MXCFB_SCREEN_WIDTH;
+	fbi->var.yres = fbi->var.yres_virtual = MXCFB_SCREEN_HEIGHT;
+	fbi->var.activate = FB_ACTIVATE_NOW;
+	mxcfb_check_var(&fbi->var, fbi);
+
+	mxcfb_set_fix(fbi);
+
+	fbi->fbops = ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+	/*
+	 * Allocate colormap
+	 */
+	fb_alloc_cmap(&fbi->cmap, 16, 0);
+
+	return fbi;
+}
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(struct platform_device *pdev)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxc_fbi;
+	int ret;
+
+	platform_set_drvdata(pdev, &mxcfb_drv_data);
+
+	/*
+	 * Initialize FB structures
+	 */
+	fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
+	if (!fbi) {
+		ret = -ENOMEM;
+		goto err0;
+	}
+	mxcfb_drv_data.fbi = fbi;
+	mxc_fbi = fbi->par;
+
+	mxcfb_drv_data.suspended = false;
+	init_waitqueue_head(&mxcfb_drv_data.suspend_wq);
+
+	/*
+	 * Allocate memory
+	 */
+	ret = mxcfb_map_video_memory(fbi);
+	if (ret < 0) {
+		goto err1;
+	}
+
+	mxcfb_init_panel(fbi);
+
+	/*
+	 * Register framebuffer
+	 */
+	ret = register_framebuffer(fbi);
+	if (ret < 0) {
+		goto err2;
+	}
+
+	dev_info(&pdev->dev, "%s registered\n", MXCFB_NAME);
+
+	return 0;
+
+      err2:
+	mxcfb_unmap_video_memory(fbi);
+      err1:
+	if (&fbi->cmap)
+		fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+      err0:
+	return ret;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * Power management hooks.      Note that we won't be called from IRQ context,
+ * unlike the blank functions above, so we may sleep.
+ */
+
+/*!
+ * Suspends the framebuffer and blanks the screen. Power management support
+ *
+ * @param	pdev	pointer to device structure.
+ * @param	state	state of the device.
+ *
+ * @return	success
+ */
+static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxcfb_data *drv_data = platform_get_drvdata(pdev);
+	struct fb_info *fbi = drv_data->fbi;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	drv_data->suspended = true;
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL);
+	/* Display OFF */
+	ipu_adc_write_cmd(mxc_fbi->disp_num, CMD, DISOFF, 0, 0);
+
+	return 0;
+}
+
+/*!
+ * Resumes the framebuffer and unblanks the screen. Power management support
+ *
+ * @param       pdev     pointer to device structure.
+ *
+ * @return      success
+ */
+static int mxcfb_resume(struct platform_device *pdev)
+{
+	struct mxcfb_data *drv_data = platform_get_drvdata(pdev);
+	struct fb_info *fbi = drv_data->fbi;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	// Display ON
+	ipu_adc_write_cmd(mxc_fbi->disp_num, CMD, DISON, 0, 0);
+	drv_data->suspended = false;
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
+		mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_DEFAULT, NULL);
+	wake_up_interruptible(&drv_data->suspend_wq);
+
+	return 0;
+}
+#else
+#define mxcfb_suspend   NULL
+#define mxcfb_resume    NULL
+#endif
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcfb_driver = {
+	.driver = {
+		   .name = MXCFB_NAME,
+		   },
+	.probe = mxcfb_probe,
+	.suspend = mxcfb_suspend,
+	.resume = mxcfb_resume,
+};
+
+/*!
+ * Device definition for the Framebuffer
+ */
+static struct platform_device mxcfb_device = {
+	.name = MXCFB_NAME,
+	.id = 0,
+	.dev = {
+		.coherent_dma_mask = 0xFFFFFFFF,
+		}
+};
+
+/*!
+ * Main entry function for the framebuffer. The function registers the power
+ * management callback functions with the kernel and also registers the MXCFB
+ * callback functions with the core Linux framebuffer driver \b fbmem.c
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&mxcfb_driver);
+	if (ret == 0) {
+		ret = platform_device_register(&mxcfb_device);
+		if (ret != 0) {
+			platform_driver_unregister(&mxcfb_driver);
+		}
+	}
+	return ret;
+}
+
+static void mxcfb_exit(void)
+{
+	struct fb_info *fbi = dev_get_drvdata(&mxcfb_device.dev);
+
+	if (fbi) {
+		mxcfb_unmap_video_memory(fbi);
+
+		if (&fbi->cmap)
+			fb_dealloc_cmap(&fbi->cmap);
+
+		unregister_framebuffer(fbi);
+		framebuffer_release(fbi);
+	}
+
+	platform_device_unregister(&mxcfb_device);
+	platform_driver_unregister(&mxcfb_driver);
+}
+
+module_init(mxcfb_init);
+module_exit(mxcfb_exit);
+
+EXPORT_SYMBOL(mxcfb_set_refresh_mode);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC Epson framebuffer driver");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxcfb_epson_vga.c b/drivers/video/mxc/mxcfb_epson_vga.c
new file mode 100644
index 000000000000..18a343ef4276
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_epson_vga.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb_epson_vga.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+#include <linux/mxcfb.h>
+#include <linux/ipu.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+static struct spi_device *lcd_spi;
+static struct device *lcd_dev;
+
+static void lcd_init(void);
+static void lcd_poweron(void);
+static void lcd_poweroff(void);
+
+static void (*lcd_reset) (void);
+static struct regulator *io_reg;
+static struct regulator *core_reg;
+
+static struct fb_videomode video_modes[] = {
+	{
+	 /* 480x640 @ 60 Hz */
+	 "Epson-VGA", 60, 480, 640, 41701, 60, 41, 10, 5, 20, 10,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+static void lcd_init_fb(struct fb_info *info)
+{
+	struct fb_var_screeninfo var;
+
+	memset(&var, 0, sizeof(var));
+
+	fb_videomode_to_var(&var, &video_modes[0]);
+
+	if (machine_is_mx31_3ds()) {
+		var.upper_margin = 0;
+		var.left_margin = 0;
+	}
+
+	var.activate = FB_ACTIVATE_ALL;
+	var.yres_virtual = var.yres * 3;
+
+	acquire_console_sem();
+	info->flags |= FBINFO_MISC_USEREVENT;
+	fb_set_var(info, &var);
+	info->flags &= ~FBINFO_MISC_USEREVENT;
+	release_console_sem();
+}
+
+static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+
+	if (strcmp(event->info->fix.id, "DISP3 BG")) {
+		return 0;
+	}
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		lcd_init_fb(event->info);
+		lcd_poweron();
+		break;
+	case FB_EVENT_BLANK:
+		if ((event->info->var.xres != 480) ||
+		    (event->info->var.yres != 640)) {
+			break;
+		}
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			lcd_poweron();
+		} else {
+			lcd_poweroff();
+		}
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = lcd_fb_event,
+};
+
+/*!
+ * This function is called whenever the SPI slave device is detected.
+ *
+ * @param	spi	the SPI slave device
+ *
+ * @return 	Returns 0 on SUCCESS and error on FAILURE.
+ */
+static int __devinit lcd_probe(struct device *dev)
+{
+	int i;
+	struct mxc_lcd_platform_data *plat = dev->platform_data;
+
+	lcd_dev = dev;
+
+	if (plat) {
+		io_reg = regulator_get(dev, plat->io_reg);
+		if (!IS_ERR(io_reg)) {
+			regulator_set_voltage(io_reg, 1800000, 1800000);
+			regulator_enable(io_reg);
+		}
+		core_reg = regulator_get(dev, plat->core_reg);
+		if (!IS_ERR(core_reg)) {
+			regulator_set_voltage(core_reg, 2800000, 2800000);
+			regulator_enable(core_reg);
+		}
+
+		lcd_reset = plat->reset;
+		if (lcd_reset)
+			lcd_reset();
+	}
+
+	lcd_init();
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0) {
+			lcd_init_fb(registered_fb[i]);
+			fb_show_logo(registered_fb[i], 0);
+			lcd_poweron();
+		}
+	}
+
+	fb_register_client(&nb);
+
+	return 0;
+}
+
+static int __devinit lcd_plat_probe(struct platform_device *pdev)
+{
+	ipu_adc_sig_cfg_t sig;
+	ipu_channel_params_t param;
+
+	memset(&sig, 0, sizeof(sig));
+	sig.ifc_width = 9;
+	sig.clk_pol = 1;
+	ipu_init_async_panel(0, IPU_PANEL_SERIAL, 90, IPU_PIX_FMT_GENERIC, sig);
+
+	memset(&param, 0, sizeof(param));
+	ipu_init_channel(DIRECT_ASYNC1, &param);
+
+	return lcd_probe(&pdev->dev);
+}
+
+static int __devinit lcd_spi_probe(struct spi_device *spi)
+{
+	lcd_spi = spi;
+
+	spi->bits_per_word = 9;
+	spi_setup(spi);
+
+	return lcd_probe(&spi->dev);
+}
+
+static int __devexit lcd_remove(struct device *dev)
+{
+	fb_unregister_client(&nb);
+	lcd_poweroff();
+	regulator_put(io_reg);
+	regulator_put(core_reg);
+
+	return 0;
+}
+
+static int __devexit lcd_spi_remove(struct spi_device *spi)
+{
+	int ret = lcd_remove(&spi->dev);
+	lcd_spi = NULL;
+	return ret;
+}
+
+static int __devexit lcd_plat_remove(struct platform_device *pdev)
+{
+	return lcd_remove(&pdev->dev);
+}
+
+static int lcd_suspend(struct spi_device *spi, pm_message_t message)
+{
+	lcd_poweroff();
+	return 0;
+}
+
+static int lcd_resume(struct spi_device *spi)
+{
+	if (lcd_reset)
+		lcd_reset();
+
+	lcd_init();
+	lcd_poweron();
+	return 0;
+}
+
+/*!
+ * spi driver structure for LTV350QV
+ */
+static struct spi_driver lcd_spi_dev_driver = {
+
+	.driver = {
+		   .name = "lcd_spi",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = lcd_spi_probe,
+	.remove = __devexit_p(lcd_spi_remove),
+	.suspend = lcd_suspend,
+	.resume = lcd_resume,
+};
+
+static struct platform_driver lcd_plat_driver = {
+	.driver = {
+		   .name = "lcd_spi",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = lcd_plat_probe,
+	.remove = __devexit_p(lcd_plat_remove),
+};
+
+#define param(x) ((x) | 0x100)
+
+/*
+ * Send init commands to L4F00242T03
+ *
+ */
+static void lcd_init(void)
+{
+	const u16 cmd[] = { 0x36, param(0), 0x3A, param(0x60) };
+
+	dev_dbg(lcd_dev, "initializing LCD\n");
+	if (lcd_spi) {
+		spi_write(lcd_spi, (const u8 *)cmd, ARRAY_SIZE(cmd));
+	} else {
+		ipu_disp_direct_write(DIRECT_ASYNC1, 0x36, 0);
+		ipu_disp_direct_write(DIRECT_ASYNC1, 0x100, 0);
+		ipu_disp_direct_write(DIRECT_ASYNC1, 0x3A, 0);
+		ipu_disp_direct_write(DIRECT_ASYNC1, 0x160, 0);
+		msleep(1);
+		ipu_uninit_channel(DIRECT_ASYNC1);
+	}
+}
+
+static int lcd_on;
+/*
+ * Send Power On commands to L4F00242T03
+ *
+ */
+static void lcd_poweron(void)
+{
+	const u16 slpout = 0x11;
+	const u16 dison = 0x29;
+	ipu_channel_params_t param;
+	if (lcd_on)
+		return;
+
+	dev_dbg(lcd_dev, "turning on LCD\n");
+
+	if (lcd_spi) {
+		msleep(60);
+		spi_write(lcd_spi, (const u8 *)&slpout, 1);
+		msleep(60);
+		spi_write(lcd_spi, (const u8 *)&dison, 1);
+	} else {
+		memset(&param, 0, sizeof(param));
+		ipu_init_channel(DIRECT_ASYNC1, &param);
+		ipu_disp_direct_write(DIRECT_ASYNC1, slpout, 0);
+		msleep(60);
+		ipu_disp_direct_write(DIRECT_ASYNC1, dison, 0);
+		msleep(1);
+		ipu_uninit_channel(DIRECT_ASYNC1);
+	}
+	lcd_on = 1;
+}
+
+/*
+ * Send Power Off commands to L4F00242T03
+ *
+ */
+static void lcd_poweroff(void)
+{
+	const u16 slpin = 0x10;
+	const u16 disoff = 0x28;
+	ipu_channel_params_t param;
+	if (!lcd_on)
+		return;
+
+	dev_dbg(lcd_dev, "turning off LCD\n");
+
+	if (lcd_spi) {
+		msleep(60);
+		spi_write(lcd_spi, (const u8 *)&disoff, 1);
+		msleep(60);
+		spi_write(lcd_spi, (const u8 *)&slpin, 1);
+	} else {
+		memset(&param, 0, sizeof(param));
+		ipu_init_channel(DIRECT_ASYNC1, &param);
+		ipu_disp_direct_write(DIRECT_ASYNC1, disoff, 0);
+		msleep(60);
+		ipu_disp_direct_write(DIRECT_ASYNC1, slpin, 0);
+		msleep(1);
+		ipu_uninit_channel(DIRECT_ASYNC1);
+	}
+	lcd_on = 0;
+}
+
+static int __init epson_lcd_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&lcd_plat_driver);
+	if (ret)
+		return ret;
+
+	return spi_register_driver(&lcd_spi_dev_driver);
+
+}
+
+static void __exit epson_lcd_exit(void)
+{
+	spi_unregister_driver(&lcd_spi_dev_driver);
+}
+
+module_init(epson_lcd_init);
+module_exit(epson_lcd_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Epson VGA LCD init driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxcfb_modedb.c b/drivers/video/mxc/mxcfb_modedb.c
new file mode 100644
index 000000000000..ad31c6b4f856
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_modedb.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/mxcfb.h>
+
+struct fb_videomode mxcfb_modedb[] = {
+	{
+	 /* 240x320 @ 60 Hz */
+	 "Sharp-QVGA", 60, 240, 320, 185925, 9, 16, 7, 9, 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
+	 FB_SYNC_DATA_INVERT | FB_SYNC_CLK_IDLE_EN,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* 240x33 @ 60 Hz */
+	 "Sharp-CLI", 60, 240, 33, 185925, 9, 16, 7, 9 + 287, 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
+	 FB_SYNC_DATA_INVERT | FB_SYNC_CLK_IDLE_EN,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* 640x480 @ 60 Hz */
+	 "NEC-VGA", 60, 640, 480, 38255, 144, 0, 34, 40, 1, 1,
+	 FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* 640x480 @ 60 Hz */
+	 "CPT-VGA", 60, 640, 480, 39683, 45, 114, 33, 11, 1, 1,
+	 FB_SYNC_CLK_LAT_FALL,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* NTSC TV output */
+	 "TV-NTSC", 60, 640, 480, 37538,
+	 38, 858 - 640 - 38 - 3,
+	 36, 518 - 480 - 36 - 1,
+	 3, 1,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* PAL TV output */
+	 "TV-PAL", 50, 640, 480, 37538,
+	 38, 960 - 640 - 38 - 32,
+	 32, 555 - 480 - 32 - 3,
+	 32, 3,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* TV output VGA mode, 640x480 @ 65 Hz */
+	 "TV-VGA", 60, 640, 480, 40574, 35, 45, 9, 1, 46, 5,
+	 0, FB_VMODE_NONINTERLACED, 0,
+	 },
+};
+
+int mxcfb_modedb_sz = ARRAY_SIZE(mxcfb_modedb);
diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c
new file mode 100644
index 000000000000..b1982f868e8c
--- /dev/null
+++ b/drivers/video/mxc/tve.c
@@ -0,0 +1,917 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file tve.c
+ * @brief Driver for i.MX TV encoder
+ *
+ * @ingroup Framebuffer
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/clk.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+#include <linux/irq.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <asm/uaccess.h>
+#include <asm/atomic.h>
+#include <mach/hardware.h>
+
+#define TVE_ENABLE			(1UL)
+#define TVE_DAC_FULL_RATE		(0UL<<1)
+#define TVE_DAC_DIV2_RATE		(1UL<<1)
+#define TVE_DAC_DIV4_RATE		(2UL<<1)
+#define TVE_IPU_CLK_ENABLE		(1UL<<3)
+
+#define CD_LM_INT		0x00000001
+#define CD_SM_INT		0x00000002
+#define CD_MON_END_INT		0x00000004
+#define CD_CH_0_LM_ST		0x00000001
+#define CD_CH_0_SM_ST		0x00000010
+#define CD_CH_1_LM_ST		0x00000002
+#define CD_CH_1_SM_ST		0x00000020
+#define CD_CH_2_LM_ST		0x00000004
+#define CD_CH_2_SM_ST		0x00000040
+#define CD_MAN_TRIG		0x00000100
+
+#define TVE_STAND_MASK			(0x0F<<8)
+#define TVE_NTSC_STAND			(0UL<<8)
+#define TVE_PAL_STAND			(3UL<<8)
+#define TVE_HD720P60_STAND		(4UL<<8)
+
+#define TVOUT_FMT_OFF			0
+#define TVOUT_FMT_NTSC			1
+#define TVOUT_FMT_PAL			2
+#define TVOUT_FMT_720P60		3
+
+static int enabled;		/* enable power on or not */
+DEFINE_SPINLOCK(tve_lock);
+
+static struct fb_info *tve_fbi;
+static struct fb_modelist tve_modelist;
+static bool g_enable_tve;
+
+struct tve_data {
+	struct platform_device *pdev;
+	int revision;
+	int cur_mode;
+	int output_mode;
+	int detect;
+	void *base;
+	int irq;
+	int blank;
+	struct clk *clk;
+	struct regulator *dac_reg;
+	struct regulator *dig_reg;
+	struct delayed_work cd_work;
+} tve;
+
+struct tve_reg_mapping {
+	u32 tve_com_conf_reg;
+	u32 tve_cd_cont_reg;
+	u32 tve_int_cont_reg;
+	u32 tve_stat_reg;
+	u32 tve_mv_cont_reg;
+};
+
+struct tve_reg_fields_mapping {
+	u32 cd_en;
+	u32 cd_trig_mode;
+	u32 cd_lm_int;
+	u32 cd_sm_int;
+	u32 cd_mon_end_int;
+	u32 cd_man_trig;
+	u32 sync_ch_mask;
+	u32 tvout_mode_mask;
+	u32 sync_ch_offset;
+	u32 tvout_mode_offset;
+	u32 cd_ch_stat_offset;
+};
+
+static struct tve_reg_mapping tve_regs_v1 = {
+	0, 0x14, 0x28, 0x2C, 0x48
+};
+
+static struct tve_reg_fields_mapping tve_reg_fields_v1 = {
+	1, 2, 1, 2, 4, 0x00010000, 0x7000, 0x70, 12, 4, 8
+};
+
+static struct tve_reg_mapping tve_regs_v2 = {
+	0, 0x34, 0x64, 0x68, 0xDC
+};
+
+static struct tve_reg_fields_mapping tve_reg_fields_v2 = {
+	1, 2, 1, 2, 4, 0x01000000, 0x700000, 0x7000, 20, 12, 16
+};
+
+
+struct tve_reg_mapping *tve_regs;
+struct tve_reg_fields_mapping *tve_reg_fields;
+
+/* For MX37 need modify some fields in tve_probe */
+static struct fb_videomode video_modes[] = {
+	{
+	 /* NTSC TV output */
+	 "TV-NTSC", 60, 720, 480, 74074,
+	 122, 15,
+	 18, 26,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT,
+	 FB_VMODE_INTERLACED,
+	 0,},
+	{
+	 /* PAL TV output */
+	 "TV-PAL", 50, 720, 576, 74074,
+	 132, 11,
+	 22, 26,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT,
+	 FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
+	 0,},
+	{
+	 /* 720p60 TV output */
+	 "720P60", 60, 1280, 720, 13468,
+	 260, 109,
+	 25, 4,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+			FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+enum tvout_mode {
+	TV_OFF,
+	CVBS0,
+	CVBS2,
+	CVBS02,
+	SVIDEO,
+	SVIDEO_CVBS,
+	YPBPR,
+	RGB
+};
+
+static unsigned short tvout_mode_to_channel_map[8] = {
+	0,	/* TV_OFF */
+	1,	/* CVBS0 */
+	4,	/* CVBS2 */
+	5,	/* CVBS02 */
+	1,	/* SVIDEO */
+	5,	/* SVIDEO_CVBS */
+	1,	/* YPBPR */
+	7	/* RGB */
+};
+
+
+static void tve_set_tvout_mode(int mode)
+{
+	u32 conf_reg;
+
+	conf_reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+	conf_reg &= ~(tve_reg_fields->sync_ch_mask |
+				tve_reg_fields->tvout_mode_mask);
+	/* clear sync_ch and tvout_mode fields */
+	conf_reg |=
+		mode << tve_reg_fields->
+		tvout_mode_offset | tvout_mode_to_channel_map[mode] <<
+		tve_reg_fields->sync_ch_offset;
+	__raw_writel(conf_reg, tve.base + tve_regs->tve_com_conf_reg);
+}
+
+static int _is_tvout_mode_hd_compatible(void)
+{
+	u32 conf_reg, mode;
+
+	conf_reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+	mode = (conf_reg >> tve_reg_fields->tvout_mode_offset) & 7;
+	if (mode == YPBPR || mode == RGB) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+
+/**
+ * tve_setup
+ * initial the CH7024 chipset by setting register
+ * @param:
+ * 	vos: output video format
+ * @return:
+ * 	0 successful
+ * 	otherwise failed
+ */
+static int tve_setup(int mode)
+{
+	u32 reg;
+	struct clk *tve_parent_clk;
+	unsigned long parent_clock_rate = 216000000, di1_clock_rate = 27000000;
+	unsigned long tve_clock_rate = 216000000;
+	struct clk *ipu_di1_clk;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve_lock, lock_flags);
+
+	switch (mode) {
+	case TVOUT_FMT_PAL:
+	case TVOUT_FMT_NTSC:
+		parent_clock_rate = 216000000;
+		di1_clock_rate = 27000000;
+		break;
+	case TVOUT_FMT_720P60:
+		parent_clock_rate = 297000000;
+		if (cpu_is_mx53())
+			tve_clock_rate = 297000000;
+		di1_clock_rate = 74250000;
+		break;
+	}
+	if (enabled)
+		clk_disable(tve.clk);
+
+	tve_parent_clk = clk_get_parent(tve.clk);
+	ipu_di1_clk = clk_get(NULL, "ipu_di1_clk");
+
+	clk_disable(tve_parent_clk);
+	clk_set_rate(tve_parent_clk, parent_clock_rate);
+
+	if (cpu_is_mx53())
+		clk_set_rate(tve.clk, tve_clock_rate);
+
+	clk_enable(tve.clk);
+	clk_set_rate(ipu_di1_clk, di1_clock_rate);
+
+	if (tve.cur_mode == mode) {
+		if (!enabled)
+			clk_disable(tve.clk);
+		spin_unlock_irqrestore(&tve_lock, lock_flags);
+		return 0;
+	}
+
+	tve.cur_mode = mode;
+
+	/* select output video format */
+	if (mode == TVOUT_FMT_PAL) {
+		reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_PAL_STAND;
+		__raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg);
+		pr_debug("TVE: change to PAL video\n");
+	} else if (mode == TVOUT_FMT_NTSC) {
+		reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_NTSC_STAND;
+		__raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg);
+		pr_debug("TVE: change to NTSC video\n");
+	} else if (mode == TVOUT_FMT_720P60) {
+		if (!_is_tvout_mode_hd_compatible()) {
+			tve_set_tvout_mode(YPBPR);
+			pr_debug("The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD720P60_STAND;
+		__raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg);
+		pr_debug("TVE: change to 720P60 video\n");
+	} else if (mode == TVOUT_FMT_OFF) {
+		__raw_writel(0x0, tve.base + tve_regs->tve_com_conf_reg);
+		pr_debug("TVE: change to OFF video\n");
+	} else {
+		pr_debug("TVE: no such video format.\n");
+		if (!enabled)
+			clk_disable(tve.clk);
+		spin_unlock_irqrestore(&tve_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	if (!enabled)
+		clk_disable(tve.clk);
+
+	spin_unlock_irqrestore(&tve_lock, lock_flags);
+	return 0;
+}
+
+/**
+ * tve_enable
+ * Enable the tve Power to begin TV encoder
+ */
+static void tve_enable(void)
+{
+	u32 reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve_lock, lock_flags);
+	if (!enabled) {
+		enabled = 1;
+		clk_enable(tve.clk);
+		reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+		__raw_writel(reg | TVE_IPU_CLK_ENABLE | TVE_ENABLE,
+					tve.base + tve_regs->tve_com_conf_reg);
+		pr_debug("TVE power on.\n");
+	}
+
+	/* enable interrupt */
+	__raw_writel(CD_SM_INT | CD_LM_INT | CD_MON_END_INT,
+				tve.base + tve_regs->tve_stat_reg);
+	__raw_writel(CD_SM_INT | CD_LM_INT | CD_MON_END_INT,
+				tve.base + tve_regs->tve_int_cont_reg);
+	spin_unlock_irqrestore(&tve_lock, lock_flags);
+}
+
+/**
+ * tve_disable
+ * Disable the tve Power to stop TV encoder
+ */
+static void tve_disable(void)
+{
+	u32 reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve_lock, lock_flags);
+	if (enabled) {
+		enabled = 0;
+		reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg);
+		__raw_writel(reg & ~TVE_ENABLE & ~TVE_IPU_CLK_ENABLE,
+				tve.base + tve_regs->tve_com_conf_reg);
+		clk_disable(tve.clk);
+		pr_debug("TVE power off.\n");
+	}
+	spin_unlock_irqrestore(&tve_lock, lock_flags);
+}
+
+static int tve_update_detect_status(void)
+{
+	int old_detect = tve.detect;
+	u32 stat_lm, stat_sm, stat;
+	u32 int_ctl;
+	u32 cd_cont_reg;
+	u32 timeout = 40;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve_lock, lock_flags);
+
+	if (!enabled) {
+		pr_warning("Warning: update tve status while it disabled!\n");
+		tve.detect = 0;
+		goto done;
+	}
+
+	int_ctl = __raw_readl(tve.base + tve_regs->tve_int_cont_reg);
+	cd_cont_reg = __raw_readl(tve.base + tve_regs->tve_cd_cont_reg);
+
+	if ((cd_cont_reg & 0x1) == 0) {
+		pr_warning("Warning: pls enable TVE CD first!\n");
+		goto done;
+	}
+
+	stat = __raw_readl(tve.base + tve_regs->tve_stat_reg);
+	while (((stat & CD_MON_END_INT) == 0) && (timeout > 0)) {
+		spin_unlock_irqrestore(&tve_lock, lock_flags);
+		msleep(2);
+		spin_lock_irqsave(&tve_lock, lock_flags);
+		timeout -= 2;
+		if (!enabled) {
+			pr_warning("Warning: update tve status while it disabled!\n");
+			tve.detect = 0;
+			goto done;
+		} else
+			stat = __raw_readl(tve.base + tve_regs->tve_stat_reg);
+	}
+	if (((stat & CD_MON_END_INT) == 0) && (timeout <= 0)) {
+		pr_warning("Warning: get detect resultwithout CD_MON_END_INT!\n");
+		goto done;
+	}
+
+	stat = stat >> tve_reg_fields->cd_ch_stat_offset;
+	stat_lm = stat & (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST);
+	if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST)) &&
+		((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST | CD_CH_2_SM_ST)) == 0)
+		) {
+			tve.detect = 3;
+			tve.output_mode = YPBPR;
+	} else if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST)) &&
+		((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST)) == 0)) {
+			tve.detect = 4;
+			tve.output_mode = SVIDEO;
+	} else if (stat_lm == CD_CH_0_LM_ST) {
+		stat_sm = stat & CD_CH_0_SM_ST;
+		if (stat_sm != 0) {
+			/* headset */
+			tve.detect = 2;
+			tve.output_mode = TV_OFF;
+		} else {
+			tve.detect = 1;
+			tve.output_mode = CVBS0;
+		}
+	} else if (stat_lm == CD_CH_2_LM_ST) {
+		stat_sm = stat & CD_CH_2_SM_ST;
+		if (stat_sm != 0) {
+			/* headset */
+			tve.detect = 2;
+			tve.output_mode = TV_OFF;
+		} else {
+			tve.detect = 1;
+			tve.output_mode = CVBS2;
+		}
+	} else {
+		/* none */
+		tve.detect = 0;
+		tve.output_mode = TV_OFF;
+	}
+
+	tve_set_tvout_mode(tve.output_mode);
+
+	/* clear interrupt */
+	__raw_writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT,
+			tve.base + tve_regs->tve_stat_reg);
+
+	__raw_writel(int_ctl | CD_SM_INT | CD_LM_INT,
+			tve.base + tve_regs->tve_int_cont_reg);
+
+	if (old_detect != tve.detect)
+		sysfs_notify(&tve.pdev->dev.kobj, NULL, "headphone");
+
+	dev_dbg(&tve.pdev->dev, "detect = %d mode = %d\n",
+			tve.detect, tve.output_mode);
+done:
+	spin_unlock_irqrestore(&tve_lock, lock_flags);
+	return tve.detect;
+}
+
+static void cd_work_func(struct work_struct *work)
+{
+	tve_update_detect_status();
+}
+#if 0
+static int tve_man_detect(void)
+{
+	u32 cd_cont;
+	u32 int_cont;
+
+	if (!enabled)
+		return -1;
+
+	int_cont = __raw_readl(tve.base + tve_regs->tve_int_cont_reg);
+	__raw_writel(int_cont &
+				~(tve_reg_fields->cd_sm_int | tve_reg_fields->cd_lm_int),
+				tve.base + tve_regs->tve_int_cont_reg);
+
+	cd_cont = __raw_readl(tve.base + tve_regs->tve_cd_cont_reg);
+	__raw_writel(cd_cont | tve_reg_fields->cd_trig_mode,
+				tve.base + tve_regs->tve_cd_cont_reg);
+
+	__raw_writel(tve_reg_fields->cd_sm_int | tve_reg_fields->
+			cd_lm_int | tve_reg_fields->
+			cd_mon_end_int | tve_reg_fields->cd_man_trig,
+			tve.base + tve_regs->tve_stat_reg);
+
+	while ((__raw_readl(tve.base + tve_regs->tve_stat_reg)
+		& tve_reg_fields->cd_mon_end_int) == 0)
+		msleep(5);
+
+	tve_update_detect_status();
+
+	__raw_writel(cd_cont, tve.base + tve_regs->tve_cd_cont_reg);
+	__raw_writel(int_cont, tve.base + tve_regs->tve_int_cont_reg);
+
+	return tve.detect;
+}
+#endif
+
+static irqreturn_t tve_detect_handler(int irq, void *data)
+{
+	u32 int_ctl = __raw_readl(tve.base + tve_regs->tve_int_cont_reg);
+
+	/* disable INT first */
+	int_ctl &= ~(CD_SM_INT | CD_LM_INT | CD_MON_END_INT);
+	__raw_writel(int_ctl, tve.base + tve_regs->tve_int_cont_reg);
+
+	__raw_writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT,
+			tve.base + tve_regs->tve_stat_reg);
+
+	schedule_delayed_work(&tve.cd_work, msecs_to_jiffies(1000));
+
+	return IRQ_HANDLED;
+}
+
+/* Re-construct clk for tve display */
+static inline void tve_recfg_fb(struct fb_info *fbi)
+{
+	struct fb_var_screeninfo var;
+
+	memset(&var, 0, sizeof(var));
+	fb_videomode_to_var(&var, fbi->mode);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	fb_set_var(fbi, &var);
+}
+
+int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		pr_debug("fb registered event\n");
+		if ((tve_fbi != NULL) || strcmp(fbi->fix.id, "DISP3 BG - DI1"))
+			break;
+
+		tve_fbi = fbi;
+		fb_add_videomode(&video_modes[0], &tve_modelist.list);
+		fb_add_videomode(&video_modes[1], &tve_modelist.list);
+		fb_add_videomode(&video_modes[2], &tve_modelist.list);
+		break;
+	case FB_EVENT_MODE_CHANGE:
+	{
+		struct fb_videomode cur_mode;
+		struct fb_videomode *mode;
+		struct list_head *pos;
+		struct fb_modelist *modelist;
+
+		if (tve_fbi != fbi)
+			break;
+
+		fb_var_to_videomode(&cur_mode, &fbi->var);
+
+		list_for_each(pos, &tve_modelist.list) {
+			modelist = list_entry(pos, struct fb_modelist, list);
+			mode = &modelist->mode;
+			if (fb_mode_is_equal(&cur_mode, mode)) {
+				fbi->mode = mode;
+				break;
+			}
+		}
+
+		if (!fbi->mode) {
+			tve_disable();
+			tve.cur_mode = TVOUT_FMT_OFF;
+			return 0;
+		}
+
+		pr_debug("fb mode change event: xres=%d, yres=%d\n",
+			 fbi->mode->xres, fbi->mode->yres);
+
+		tve_disable();
+
+		if (fb_mode_is_equal(fbi->mode, &video_modes[0])) {
+			tve_setup(TVOUT_FMT_NTSC);
+			tve_enable();
+		} else if (fb_mode_is_equal(fbi->mode, &video_modes[1])) {
+			tve_setup(TVOUT_FMT_PAL);
+			tve_enable();
+		} else if (fb_mode_is_equal(fbi->mode, &video_modes[2])) {
+			tve_setup(TVOUT_FMT_720P60);
+			tve_enable();
+		} else {
+			tve_setup(TVOUT_FMT_OFF);
+		}
+		break;
+	}
+	case FB_EVENT_BLANK:
+		if ((tve_fbi != fbi) || (fbi->mode == NULL))
+			return 0;
+
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			if (tve.blank != FB_BLANK_UNBLANK) {
+				if (fb_mode_is_equal(fbi->mode, &video_modes[0])) {
+					tve_disable();
+					tve_setup(TVOUT_FMT_NTSC);
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else if (fb_mode_is_equal(fbi->mode,
+							&video_modes[1])) {
+					tve_disable();
+					tve_setup(TVOUT_FMT_PAL);
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else if (fb_mode_is_equal(fbi->mode,
+							&video_modes[2])) {
+					tve_disable();
+					tve_setup(TVOUT_FMT_720P60);
+					tve_enable();
+					tve_recfg_fb(fbi);
+				} else {
+					tve_setup(TVOUT_FMT_OFF);
+				}
+				tve.blank = FB_BLANK_UNBLANK;
+			}
+		} else {
+			tve_disable();
+			tve.blank = FB_BLANK_POWERDOWN;
+		}
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = tve_fb_event,
+};
+
+static ssize_t show_headphone(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	int detect;
+
+	if (!enabled) {
+		strcpy(buf, "tve power off\n");
+		return strlen(buf);
+	}
+
+	detect = tve_update_detect_status();
+
+	if (detect == 0)
+		strcpy(buf, "none\n");
+	else if (detect == 1)
+		strcpy(buf, "cvbs\n");
+	else if (detect == 2)
+		strcpy(buf, "headset\n");
+	else if (detect == 3)
+		strcpy(buf, "component\n");
+	else
+		strcpy(buf, "svideo\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL);
+
+static int _tve_get_revision(void)
+{
+	u32 conf_reg;
+	u32 rev = 0;
+
+	/* find out TVE rev based on the base addr default value
+	 * can be used at the init/probe ONLY */
+	conf_reg = __raw_readl(tve.base);
+	switch (conf_reg) {
+	case 0x00842000:
+		rev = 1;
+		break;
+	case 0x00100000:
+		rev = 2;
+		break;
+	}
+	return rev;
+}
+
+static int tve_probe(struct platform_device *pdev)
+{
+	int ret, i, primary = 0;
+	struct resource *res;
+	struct tve_platform_data *plat_data = pdev->dev.platform_data;
+	u32 conf_reg;
+
+	if (g_enable_tve == false)
+		return -ENODEV;
+
+	INIT_LIST_HEAD(&tve_modelist.list);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL)
+		return -ENOMEM;
+
+	tve.pdev = pdev;
+	tve.base = ioremap(res->start, res->end - res->start);
+
+	tve.irq = platform_get_irq(pdev, 0);
+	if (tve.irq < 0) {
+		ret = tve.irq;
+		goto err0;
+	}
+
+	ret = request_irq(tve.irq, tve_detect_handler, 0, pdev->name, pdev);
+	if (ret < 0)
+		goto err0;
+
+	ret = device_create_file(&pdev->dev, &dev_attr_headphone);
+	if (ret < 0)
+		goto err1;
+
+	for (i = 0; i < num_registered_fb; i++) {
+		if (strcmp(registered_fb[i]->fix.id, "DISP3 BG - DI1") == 0) {
+			tve_fbi = registered_fb[i];
+			if (i == 0) {
+				primary = 1;
+				acquire_console_sem();
+				fb_blank(tve_fbi, FB_BLANK_POWERDOWN);
+				release_console_sem();
+			}
+			break;
+		}
+	}
+
+	/* adjust video mode for mx37 */
+	if (cpu_is_mx37()) {
+		video_modes[0].left_margin = 121;
+		video_modes[0].right_margin = 16;
+		video_modes[0].upper_margin = 17;
+		video_modes[0].lower_margin = 5;
+		video_modes[1].left_margin = 131;
+		video_modes[1].right_margin = 12;
+		video_modes[1].upper_margin = 21;
+		video_modes[1].lower_margin = 3;
+	}
+
+	if (tve_fbi != NULL) {
+		fb_add_videomode(&video_modes[0], &tve_modelist.list);
+		fb_add_videomode(&video_modes[1], &tve_modelist.list);
+		fb_add_videomode(&video_modes[2], &tve_modelist.list);
+	}
+
+	tve.dac_reg = regulator_get(&pdev->dev, plat_data->dac_reg);
+	if (!IS_ERR(tve.dac_reg)) {
+		regulator_set_voltage(tve.dac_reg, 2500000, 2500000);
+		regulator_enable(tve.dac_reg);
+	}
+
+	tve.dig_reg = regulator_get(&pdev->dev, plat_data->dig_reg);
+	if (!IS_ERR(tve.dig_reg)) {
+		regulator_set_voltage(tve.dig_reg, 1250000, 1250000);
+		regulator_enable(tve.dig_reg);
+	}
+
+	tve.clk = clk_get(&pdev->dev, "tve_clk");
+	clk_set_rate(tve.clk, 216000000);
+	clk_enable(tve.clk);
+
+	tve.revision = _tve_get_revision();
+	if (tve.revision == 1) {
+		tve_regs = &tve_regs_v1;
+		tve_reg_fields = &tve_reg_fields_v1;
+	} else {
+		tve_regs = &tve_regs_v2;
+		tve_reg_fields = &tve_reg_fields_v2;
+	}
+
+	/* Setup cable detect, for YPrPb mode, default use channel#0 for Y */
+	INIT_DELAYED_WORK(&tve.cd_work, cd_work_func);
+	if (tve.revision == 1)
+		__raw_writel(0x01067701, tve.base + tve_regs->tve_cd_cont_reg);
+	else
+		__raw_writel(0x00770601, tve.base + tve_regs->tve_cd_cont_reg);
+
+	conf_reg = 0;
+	__raw_writel(conf_reg, tve.base + tve_regs->tve_com_conf_reg);
+
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 5);
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 4);
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 3);
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 2);
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4);
+	__raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg);
+
+	clk_disable(tve.clk);
+
+	ret = fb_register_client(&nb);
+	if (ret < 0)
+		goto err2;
+
+	tve.blank = -1;
+
+	/* is primary display? */
+	if (primary) {
+		struct fb_var_screeninfo var;
+		const struct fb_videomode *mode;
+
+		memset(&var, 0, sizeof(var));
+		mode = fb_match_mode(&tve_fbi->var, &tve_modelist.list);
+		if (mode) {
+			pr_debug("TVE: fb mode found\n");
+			fb_videomode_to_var(&var, mode);
+		} else {
+			pr_warning("TVE: can not find video mode\n");
+			goto done;
+		}
+		acquire_console_sem();
+		tve_fbi->flags |= FBINFO_MISC_USEREVENT;
+		fb_set_var(tve_fbi, &var);
+		tve_fbi->flags &= ~FBINFO_MISC_USEREVENT;
+		release_console_sem();
+
+		acquire_console_sem();
+		fb_blank(tve_fbi, FB_BLANK_UNBLANK);
+		release_console_sem();
+
+		fb_show_logo(tve_fbi, 0);
+	}
+
+done:
+	return 0;
+err2:
+	device_remove_file(&pdev->dev, &dev_attr_headphone);
+err1:
+	free_irq(tve.irq, pdev);
+err0:
+	iounmap(tve.base);
+	return ret;
+}
+
+static int tve_remove(struct platform_device *pdev)
+{
+	if (enabled) {
+		clk_disable(tve.clk);
+		enabled = 0;
+	}
+	free_irq(tve.irq, pdev);
+	device_remove_file(&pdev->dev, &dev_attr_headphone);
+	fb_unregister_client(&nb);
+	return 0;
+}
+
+/*!
+ * PM suspend/resume routing
+ */
+static int tve_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	if (enabled) {
+		__raw_writel(0, tve.base + tve_regs->tve_int_cont_reg);
+		__raw_writel(0, tve.base + tve_regs->tve_cd_cont_reg);
+		__raw_writel(0, tve.base + tve_regs->tve_com_conf_reg);
+		clk_disable(tve.clk);
+	}
+	return 0;
+}
+
+static int tve_resume(struct platform_device *pdev)
+{
+	if (enabled) {
+		clk_enable(tve.clk);
+
+		/* Setup cable detect */
+		if (tve.revision == 1)
+			__raw_writel(0x01067701,
+				tve.base + tve_regs->tve_cd_cont_reg);
+		else
+			__raw_writel(0x00770601,
+				tve.base + tve_regs->tve_cd_cont_reg);
+
+		if (tve.cur_mode == TVOUT_FMT_NTSC) {
+			tve_disable();
+			tve.cur_mode = TVOUT_FMT_OFF;
+			tve_setup(TVOUT_FMT_NTSC);
+		} else if (tve.cur_mode == TVOUT_FMT_PAL) {
+			tve_disable();
+			tve.cur_mode = TVOUT_FMT_OFF;
+			tve_setup(TVOUT_FMT_PAL);
+		} else if (tve.cur_mode == TVOUT_FMT_720P60) {
+			tve_disable();
+			tve.cur_mode = TVOUT_FMT_OFF;
+			tve_setup(TVOUT_FMT_720P60);
+		}
+		tve_enable();
+	}
+
+	return 0;
+}
+
+static struct platform_driver tve_driver = {
+	.driver = {
+		   .name = "tve",
+		   },
+	.probe = tve_probe,
+	.remove = tve_remove,
+	.suspend = tve_suspend,
+	.resume = tve_resume,
+};
+
+static int __init enable_tve_setup(char *options)
+{
+	g_enable_tve = true;
+
+	return 1;
+}
+__setup("tve", enable_tve_setup);
+
+static int __init tve_init(void)
+{
+	return platform_driver_register(&tve_driver);
+}
+
+static void __exit tve_exit(void)
+{
+	platform_driver_unregister(&tve_driver);
+}
+
+module_init(tve_init);
+module_exit(tve_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX TV encoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxs/Kconfig b/drivers/video/mxs/Kconfig
new file mode 100644
index 000000000000..35b896e95d4f
--- /dev/null
+++ b/drivers/video/mxs/Kconfig
@@ -0,0 +1,28 @@
+config FB_MXS
+	tristate "MXS Framebuffer driver"
+	depends on FB && ARCH_MXS
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	default y
+	---help---
+	  Say Y here to enable support for the framebuffer driver for the
+	  Freescale MXS Board.
+
+config FB_MXS_LCD_43WVF1G
+	depends on FB_MXS
+	tristate "SEIKO 4.3' LCD WVGA(800x480) PANEL"
+	default y if ARCH_MX28
+
+config FB_MXS_LCD_LMS430
+	depends on FB_MXS
+	bool "LMS430"
+	default y if ARCH_MX23
+	---help---
+	  Use LMS430 dotclock LCD panel for MXS
+
+config FB_MXS_TVENC
+	depends on ARCH_MXS
+	bool "TVENC"
+	---help---
+	  Use TVOUT encoder for MXS
diff --git a/drivers/video/mxs/Makefile b/drivers/video/mxs/Makefile
new file mode 100644
index 000000000000..fbab953718c7
--- /dev/null
+++ b/drivers/video/mxs/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_ARCH_MXS)				+= lcdif.o
+obj-$(CONFIG_FB_MXS)				+= mxsfb.o
+obj-$(CONFIG_FB_MXS_LCD_43WVF1G)		+= lcd_43wvf1g.o
+obj-$(CONFIG_FB_MXS_LCD_LMS430)			+= lcd_lms430.o
+# TVOUT support
+obj-$(CONFIG_FB_MXS_TVENC)			+= tvenc.o
diff --git a/drivers/video/mxs/lcd_43wvf1g.c b/drivers/video/mxs/lcd_43wvf1g.c
new file mode 100644
index 000000000000..1a8157f277a0
--- /dev/null
+++ b/drivers/video/mxs/lcd_43wvf1g.c
@@ -0,0 +1,289 @@
+/*
+ * Freescale MX28 Seiko 43WVF1G LCD panel driver
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/notifier.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
+
+#include <mach/device.h>
+#include <mach/lcdif.h>
+#include <mach/regs-pwm.h>
+#include <mach/system.h>
+
+#define DOTCLK_H_ACTIVE  800
+#define DOTCLK_H_PULSE_WIDTH 10
+#define DOTCLK_HF_PORCH  164
+#define DOTCLK_HB_PORCH  89
+#define DOTCLK_H_WAIT_CNT  (DOTCLK_H_PULSE_WIDTH + DOTCLK_HB_PORCH)
+#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)
+
+#define DOTCLK_V_ACTIVE  480
+#define DOTCLK_V_PULSE_WIDTH  10
+#define DOTCLK_VF_PORCH  10
+#define DOTCLK_VB_PORCH  23
+#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
+#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)
+
+static struct mxs_platform_bl_data bl_data;
+static struct clk *lcd_clk;
+
+static int init_panel(struct device *dev, dma_addr_t phys, int memsize,
+		      struct mxs_platform_fb_entry *pentry)
+{
+	int ret = 0;
+	lcd_clk = clk_get(dev, "dis_lcdif");
+	if (IS_ERR(lcd_clk)) {
+		ret = PTR_ERR(lcd_clk);
+		goto out;
+	}
+	ret = clk_enable(lcd_clk);
+	if (ret) {
+		clk_put(lcd_clk);
+		goto out;
+	}
+
+	ret = clk_set_rate(lcd_clk, 1000000 / pentry->cycle_time_ns);	/* kHz */
+	if (ret) {
+		clk_disable(lcd_clk);
+		clk_put(lcd_clk);
+		goto out;
+	}
+
+	/*
+	 * Make sure we do a high-to-low transition to reset the panel.
+	 * First make it low for 100 msec, hi for 10 msec, low for 10 msec,
+	 * then hi.
+	 */
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);	/* low */
+	mdelay(100);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);	/* high */
+	mdelay(10);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);	/* low */
+
+	/* For the Samsung, Reset must be held low at least 30 uSec
+	 * Therefore, we'll hold it low for about 10 mSec just to be sure.
+	 * Then we'll wait 1 mSec afterwards.
+	 */
+	mdelay(10);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);	/* high */
+	mdelay(1);
+
+	setup_dotclk_panel(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD,
+			   DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE,
+			   DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD,
+			   DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0);
+
+	ret = mxs_lcdif_dma_init(dev, phys, memsize);
+	if (ret)
+		goto out;
+
+	mxs_lcd_set_bl_pdata(pentry->bl_data);
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry);
+	return 0;
+
+out:
+	return ret;
+}
+
+static void release_panel(struct device *dev,
+			  struct mxs_platform_fb_entry *pentry)
+{
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry);
+	release_dotclk_panel();
+	mxs_lcdif_dma_release();
+	clk_disable(lcd_clk);
+	clk_put(lcd_clk);
+}
+
+static int blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+		for (count = 10000; count; count--) {
+			if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
+			    BM_LCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			udelay(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			     REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static struct mxs_platform_fb_entry fb_entry = {
+	.name = "43wvf1g",
+	.x_res = 480,
+	.y_res = 800,
+	.bpp = 32,
+	.cycle_time_ns = 30,
+	.lcd_type = MXS_LCD_PANEL_DOTCLK,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.stop_panel = mxs_lcdif_stop,
+	.pan_display = mxs_lcdif_pan_display,
+	.bl_data = &bl_data,
+};
+
+static struct clk *pwm_clk;
+
+static int init_bl(struct mxs_platform_bl_data *data)
+{
+	int ret = 0;
+
+	pwm_clk = clk_get(NULL, "pwm");
+	if (IS_ERR(pwm_clk)) {
+		ret = PTR_ERR(pwm_clk);
+		return ret;
+	}
+	clk_enable(pwm_clk);
+	mxs_reset_block(REGS_PWM_BASE, 1);
+
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(599),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
+
+	return 0;
+}
+
+static void free_bl(struct mxs_platform_bl_data *data)
+{
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(599),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
+
+	clk_disable(pwm_clk);
+	clk_put(pwm_clk);
+}
+
+static int values[] = { 0, 4, 9, 14, 20, 27, 35, 45, 57, 75, 100 };
+
+static int power[] = {
+	0, 1500, 3600, 6100, 10300,
+	15500, 74200, 114200, 155200,
+	190100, 191000
+};
+
+static int bl_to_power(int br)
+{
+	int base;
+	int rem;
+
+	if (br > 100)
+		br = 100;
+	base = power[br / 10];
+	rem = br % 10;
+	if (!rem)
+		return base;
+	else
+		return base + (rem * (power[br / 10 + 1]) - base) / 10;
+}
+
+static int set_bl_intensity(struct mxs_platform_bl_data *data,
+			    struct backlight_device *bd, int suspended)
+{
+	int intensity = bd->props.brightness;
+	int scaled_int;
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (suspended)
+		intensity = 0;
+
+	/*
+	 * This is not too cool but what can we do?
+	 * Luminance changes non-linearly...
+	 */
+	if (regulator_set_current_limit
+	    (data->regulator, bl_to_power(intensity), bl_to_power(intensity)))
+		return -EBUSY;
+
+	scaled_int = values[intensity / 10];
+	if (scaled_int < 100) {
+		int rem = intensity - 10 * (intensity / 10);	/* r = i % 10; */
+		scaled_int += rem * (values[intensity / 10 + 1] -
+				     values[intensity / 10]) / 10;
+	}
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(scaled_int) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(399),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	return 0;
+}
+
+static struct mxs_platform_bl_data bl_data = {
+	.bl_max_intensity = 100,
+	.bl_default_intensity = 50,
+	.bl_cons_intensity = 50,
+	.init_bl = init_bl,
+	.free_bl = free_bl,
+	.set_bl_intensity = set_bl_intensity,
+};
+
+static int __init register_devices(void)
+{
+	struct platform_device *pdev;
+	pdev = mxs_get_device("mxs-fb", 0);
+	if (pdev == NULL || IS_ERR(pdev))
+		return -ENODEV;
+
+	mxs_lcd_register_entry(&fb_entry, pdev->dev.platform_data);
+
+	return 0;
+}
+
+subsys_initcall(register_devices);
diff --git a/drivers/video/mxs/lcd_lms430.c b/drivers/video/mxs/lcd_lms430.c
new file mode 100644
index 000000000000..c167774d5785
--- /dev/null
+++ b/drivers/video/mxs/lcd_lms430.c
@@ -0,0 +1,300 @@
+/*
+ * Freescale MXS Samsung LMS430 LCD panel initialization
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/notifier.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
+
+#include <mach/device.h>
+#include <mach/lcdif.h>
+#include <mach/regs-pwm.h>
+#include <mach/system.h>
+
+#define REGS_PWM_BASE IO_ADDRESS(PWM_PHYS_ADDR)
+
+#define DOTCLK_H_ACTIVE  480
+#define DOTCLK_H_PULSE_WIDTH 1
+#define DOTCLK_HF_PORCH  8
+#define DOTCLK_HB_PORCH  15
+#define DOTCLK_H_WAIT_CNT  (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH))
+#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)
+
+#define DOTCLK_V_ACTIVE  272
+#define DOTCLK_V_PULSE_WIDTH  1
+#define DOTCLK_VF_PORCH  4
+#define DOTCLK_VB_PORCH  12
+#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
+#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)
+
+static struct mxs_platform_bl_data bl_data;
+static struct clk *lcd_clk;
+
+static int init_panel(struct device *dev, dma_addr_t phys, int memsize,
+		      struct mxs_platform_fb_entry *pentry)
+{
+	int ret = 0;
+	lcd_clk = clk_get(NULL, "lcdif");
+	if (IS_ERR(lcd_clk)) {
+		ret = PTR_ERR(lcd_clk);
+		goto out;
+	}
+	ret = clk_enable(lcd_clk);
+	if (ret) {
+		clk_put(lcd_clk);
+		goto out;
+	}
+
+	ret = clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns);	/* Hz */
+	if (ret) {
+		clk_disable(lcd_clk);
+		clk_put(lcd_clk);
+		goto out;
+	}
+
+	/*
+	 * Make sure we do a high-to-low transition to reset the panel.
+	 * First make it low for 100 msec, hi for 10 msec, low for 10 msec,
+	 * then hi.
+	 */
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);	/* low */
+	mdelay(100);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);	/* high */
+	mdelay(10);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);	/* low */
+
+	/* For the Samsung, Reset must be held low at least 30 uSec
+	 * Therefore, we'll hold it low for about 10 mSec just to be sure.
+	 * Then we'll wait 1 mSec afterwards.
+	 */
+	mdelay(10);
+	__raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);	/* high */
+	mdelay(1);
+
+	setup_dotclk_panel(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD,
+			   DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE,
+			   DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD,
+			   DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0);
+
+	ret = mxs_lcdif_dma_init(dev, phys, memsize);
+	if (ret)
+		goto out;
+
+	mxs_lcd_set_bl_pdata(pentry->bl_data);
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry);
+	return 0;
+
+out:
+	return ret;
+}
+
+static void release_panel(struct device *dev,
+			  struct mxs_platform_fb_entry *pentry)
+{
+	/* Reset LCD panel signel. */
+	__raw_writel(BM_LCDIF_CTRL1_RESET,
+		REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	mdelay(100);
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry);
+	release_dotclk_panel();
+	mxs_lcdif_dma_release();
+	clk_disable(lcd_clk);
+	clk_put(lcd_clk);
+	__raw_writel(BM_LCDIF_CTRL_CLKGATE,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+}
+
+static int blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+		for (count = 10000; count; count--) {
+			if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
+			    BM_LCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			udelay(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			     REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static struct mxs_platform_fb_entry fb_entry = {
+	.name = "lms430",
+	.x_res = 272,
+	.y_res = 480,
+	.bpp = 32,
+	.cycle_time_ns = 150,
+	.lcd_type = MXS_LCD_PANEL_DOTCLK,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.stop_panel = mxs_lcdif_stop,
+	.pan_display = mxs_lcdif_pan_display,
+	.bl_data = &bl_data,
+};
+
+static struct clk *pwm_clk;
+
+static int init_bl(struct mxs_platform_bl_data *data)
+{
+	int ret = 0;
+
+	pwm_clk = clk_get(NULL, "pwm");
+	if (IS_ERR(pwm_clk)) {
+		ret = PTR_ERR(pwm_clk);
+		return ret;
+	}
+	clk_enable(pwm_clk);
+	mxs_reset_block(REGS_PWM_BASE, 1);
+
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(599),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
+
+	return 0;
+}
+
+static void free_bl(struct mxs_platform_bl_data *data)
+{
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(599),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
+
+	clk_disable(pwm_clk);
+	clk_put(pwm_clk);
+}
+
+static int values[] = { 0, 4, 9, 14, 20, 27, 35, 45, 57, 75, 100 };
+
+static int power[] = {
+	0, 1500, 3600, 6100, 10300,
+	15500, 74200, 114200, 155200,
+	190100, 191000
+};
+
+static int bl_to_power(int br)
+{
+	int base;
+	int rem;
+
+	if (br > 100)
+		br = 100;
+	base = power[br / 10];
+	rem = br % 10;
+	if (!rem)
+		return base;
+	else
+		return base + (rem * (power[br / 10 + 1]) - base) / 10;
+}
+
+static int set_bl_intensity(struct mxs_platform_bl_data *data,
+			    struct backlight_device *bd, int suspended)
+{
+	int intensity = bd->props.brightness;
+	int scaled_int;
+
+	if (bd->props.power != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+		intensity = 0;
+	if (suspended)
+		intensity = 0;
+
+	/*
+	 * This is not too cool but what can we do?
+	 * Luminance changes non-linearly...
+	 */
+	if (regulator_set_current_limit
+	    (data->regulator, bl_to_power(intensity), bl_to_power(intensity)))
+		return -EBUSY;
+
+	scaled_int = values[intensity / 10];
+	if (scaled_int < 100) {
+		int rem = intensity - 10 * (intensity / 10);	/* r = i % 10; */
+		scaled_int += rem * (values[intensity / 10 + 1] -
+				     values[intensity / 10]) / 10;
+	}
+	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(scaled_int) |
+		     BF_PWM_ACTIVEn_ACTIVE(0),
+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
+		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
+		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
+		     BF_PWM_PERIODn_PERIOD(399),
+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
+	return 0;
+}
+
+static struct mxs_platform_bl_data bl_data = {
+	.bl_max_intensity = 100,
+	.bl_default_intensity = 50,
+	.bl_cons_intensity = 50,
+	.init_bl = init_bl,
+	.free_bl = free_bl,
+	.set_bl_intensity = set_bl_intensity,
+};
+
+static int __init register_devices(void)
+{
+	struct platform_device *pdev;
+	pdev = mxs_get_device("mxs-fb", 0);
+	if (pdev == NULL || IS_ERR(pdev))
+		return -ENODEV;
+
+	mxs_lcd_register_entry(&fb_entry, pdev->dev.platform_data);
+
+	return 0;
+}
+
+subsys_initcall(register_devices);
diff --git a/drivers/video/mxs/lcdif.c b/drivers/video/mxs/lcdif.c
new file mode 100644
index 000000000000..f7d48a6fb3e9
--- /dev/null
+++ b/drivers/video/mxs/lcdif.c
@@ -0,0 +1,136 @@
+/*
+ * Freescale MXS LCDIF low-level routines
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/hardware.h>
+#include <mach/lcdif.h>
+#include <mach/regs-lcdif.h>
+#include <mach/system.h>
+
+#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR)
+
+void mxs_init_lcdif(void)
+{
+	__raw_writel(BM_LCDIF_CTRL_CLKGATE,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+	/* Reset controller */
+	__raw_writel(BM_LCDIF_CTRL_SFTRST, REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+	udelay(10);
+
+	/* Take controller out of reset */
+	__raw_writel(BM_LCDIF_CTRL_SFTRST | BM_LCDIF_CTRL_CLKGATE,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+	/* Setup the bus protocol */
+	__raw_writel(BM_LCDIF_CTRL1_MODE86,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	__raw_writel(BM_LCDIF_CTRL1_BUSY_ENABLE,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+
+	/* Take display out of reset */
+	__raw_writel(BM_LCDIF_CTRL1_RESET,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+
+	/* VSYNC is an input by default */
+	__raw_writel(BM_LCDIF_VDCTRL0_VSYNC_OEB,
+		     REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET);
+
+	/* Reset display */
+	__raw_writel(BM_LCDIF_CTRL1_RESET,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	udelay(10);
+	__raw_writel(BM_LCDIF_CTRL1_RESET,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+	udelay(10);
+}
+EXPORT_SYMBOL(mxs_init_lcdif);
+
+int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize)
+{
+	__raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+
+	__raw_writel(phys, REGS_LCDIF_BASE + HW_LCDIF_CUR_BUF);
+	__raw_writel(phys, REGS_LCDIF_BASE + HW_LCDIF_NEXT_BUF);
+
+	return 0;
+}
+EXPORT_SYMBOL(mxs_lcdif_dma_init);
+
+void mxs_lcdif_dma_release(void)
+{
+	__raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+	return;
+}
+EXPORT_SYMBOL(mxs_lcdif_dma_release);
+
+void mxs_lcdif_run(void)
+{
+	__raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+	__raw_writel(BM_LCDIF_CTRL_RUN, REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+}
+EXPORT_SYMBOL(mxs_lcdif_run);
+
+void mxs_lcdif_stop(void)
+{
+	__raw_writel(BM_LCDIF_CTRL_RUN, REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+	__raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER,
+		     REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+	udelay(100);
+}
+EXPORT_SYMBOL(mxs_lcdif_stop);
+
+int mxs_lcdif_pan_display(dma_addr_t addr)
+{
+	__raw_writel(addr, REGS_LCDIF_BASE + HW_LCDIF_NEXT_BUF);
+
+	return 0;
+}
+
+EXPORT_SYMBOL(mxs_lcdif_pan_display);
+
+static BLOCKING_NOTIFIER_HEAD(lcdif_client_list);
+
+int mxs_lcdif_register_client(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&lcdif_client_list, nb);
+}
+
+EXPORT_SYMBOL(mxs_lcdif_register_client);
+
+void mxs_lcdif_unregister_client(struct notifier_block *nb)
+{
+	blocking_notifier_chain_unregister(&lcdif_client_list, nb);
+}
+EXPORT_SYMBOL(mxs_lcdif_unregister_client);
+
+void mxs_lcdif_notify_clients(unsigned long event,
+			      struct mxs_platform_fb_entry *pentry)
+{
+	blocking_notifier_call_chain(&lcdif_client_list, event, pentry);
+}
+EXPORT_SYMBOL(mxs_lcdif_notify_clients);
diff --git a/drivers/video/mxs/mxsfb.c b/drivers/video/mxs/mxsfb.c
new file mode 100644
index 000000000000..ba7acbad3392
--- /dev/null
+++ b/drivers/video/mxs/mxsfb.c
@@ -0,0 +1,949 @@
+/*
+ * Freescale MXS framebuffer driver
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-lcdif.h>
+#include <mach/clock.h>
+#include <mach/lcdif.h>
+
+#define NUM_SCREENS	1
+
+enum {
+	F_DISABLE = 0,
+	F_ENABLE,
+	F_REENABLE,
+};
+
+struct mxs_fb_data {
+	struct fb_info info;
+	struct mxs_platform_fb_data *pdata;
+	struct work_struct work;
+	struct mutex blank_mutex;
+	u32 state;
+	u32 task_state;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	dma_addr_t cur_phys;
+	int irq;
+	unsigned long regbase;
+	void *virt_start;
+	struct device *dev;
+	wait_queue_head_t vsync_wait_q;
+	u32 vsync_count;
+	void *par;
+};
+
+/* forward declaration */
+static int mxsfb_blank(int blank, struct fb_info *info);
+static unsigned char *default_panel_name;
+static struct mxs_fb_data *cdata;
+static void init_timings(struct mxs_fb_data *data);
+
+static void mxsfb_enable_controller(struct mxs_fb_data *data)
+{
+	struct mxs_platform_fb_entry *pentry = data->pdata->cur;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return;
+
+	mxs_init_lcdif();
+	init_timings(data);
+	pentry->init_panel(data->dev, data->phys_start,
+			   data->info.fix.smem_len, data->pdata->cur);
+	pentry->run_panel();
+
+	if (pentry->blank_panel)
+		pentry->blank_panel(FB_BLANK_UNBLANK);
+}
+
+static void mxsfb_disable_controller(struct mxs_fb_data *data)
+{
+	struct mxs_platform_fb_entry *pentry = data->pdata->cur;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return;
+
+	if (pentry->blank_panel)
+		pentry->blank_panel(FB_BLANK_POWERDOWN);
+
+	if (pentry->stop_panel)
+		pentry->stop_panel();
+	pentry->release_panel(data->dev, pentry);
+}
+
+static void set_controller_state(struct mxs_fb_data *data, u32 state)
+{
+	struct mxs_platform_fb_entry *pentry = data->pdata->cur;
+	struct fb_info *info = &data->info;
+	u32 old_state;
+
+	mutex_lock(&data->blank_mutex);
+	old_state = data->state;
+	pr_debug("%s, old_state %d, state %d\n", __func__, old_state, state);
+
+	switch (state) {
+	case F_DISABLE:
+		/*
+		 * Disable controller
+		 */
+		if (old_state != F_DISABLE) {
+			data->state = F_DISABLE;
+			mxsfb_disable_controller(data);
+		}
+		break;
+
+	case F_REENABLE:
+		/*
+		 * Re-enable the controller when panel changed.
+		 */
+		if (old_state == F_ENABLE) {
+			mxsfb_disable_controller(data);
+
+			pentry = data->pdata->cur = data->pdata->next;
+			info->fix.smem_len = pentry->y_res * pentry->x_res *
+			    pentry->bpp / 8;
+			info->screen_size = info->fix.smem_len;
+			memset((void *)info->screen_base, 0, info->screen_size);
+
+			mxsfb_enable_controller(data);
+
+			data->state = F_ENABLE;
+		} else if (old_state == F_DISABLE) {
+			pentry = data->pdata->cur = data->pdata->next;
+			info->fix.smem_len = pentry->y_res * pentry->x_res *
+			    pentry->bpp / 8;
+			info->screen_size = info->fix.smem_len;
+			memset((void *)info->screen_base, 0, info->screen_size);
+
+			data->state = F_DISABLE;
+		}
+		break;
+
+	case F_ENABLE:
+		if (old_state != F_ENABLE) {
+			data->state = F_ENABLE;
+			mxsfb_enable_controller(data);
+		}
+		break;
+	}
+	mutex_unlock(&data->blank_mutex);
+
+}
+
+static void mxsfb_task(struct work_struct *work)
+{
+	struct mxs_fb_data *data = container_of(work, struct mxs_fb_data, work);
+
+	u32 state = xchg(&data->task_state, -1);
+	pr_debug("%s: state = %d, data->task_state = %d\n",
+		 __func__, state, data->task_state);
+
+	set_controller_state(data, state);
+}
+
+static void mxs_schedule_work(struct mxs_fb_data *data, u32 state)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	data->task_state = state;
+	schedule_work(&data->work);
+
+	local_irq_restore(flags);
+}
+
+static irqreturn_t lcd_irq_handler(int irq, void *dev_id)
+{
+	struct mxs_fb_data *data = dev_id;
+	u32 status_lcd = __raw_readl(data->regbase + HW_LCDIF_CTRL1);
+	pr_debug("%s: irq %d\n", __func__, irq);
+
+	if (status_lcd & BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ) {
+		pr_debug("%s: VSYNC irq\n", __func__);
+		data->vsync_count++;
+		__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ,
+			     data->regbase + HW_LCDIF_CTRL1_CLR);
+		wake_up_interruptible(&data->vsync_wait_q);
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+		pr_debug("%s: frame done irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+			     data->regbase + HW_LCDIF_CTRL1_CLR);
+		data->vsync_count++;
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_UNDERFLOW_IRQ) {
+		pr_debug("%s: underflow irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_UNDERFLOW_IRQ,
+			     data->regbase + HW_LCDIF_CTRL1_CLR);
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_OVERFLOW_IRQ) {
+		pr_debug("%s: overflow irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_OVERFLOW_IRQ,
+			     data->regbase + HW_LCDIF_CTRL1_CLR);
+	}
+	return IRQ_HANDLED;
+}
+
+static struct fb_var_screeninfo mxsfb_default __devinitdata = {
+	.activate = FB_ACTIVATE_TEST,
+	.height = -1,
+	.width = -1,
+	.pixclock = 20000,
+	.left_margin = 64,
+	.right_margin = 64,
+	.upper_margin = 32,
+	.lower_margin = 32,
+	.hsync_len = 64,
+	.vsync_len = 2,
+	.vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo mxsfb_fix __devinitdata = {
+	.id = "mxsfb",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.visual = FB_VISUAL_TRUECOLOR,
+	.xpanstep = 0,
+	.ypanstep = 0,
+	.ywrapstep = 0,
+	.accel = FB_ACCEL_NONE,
+};
+
+int mxsfb_get_info(struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix)
+{
+	if (!cdata)
+		return -ENODEV;
+
+	*var = cdata->info.var;
+	*fix = cdata->info.fix;
+	return 0;
+}
+
+void mxsfb_cfg_pxp(int enable, dma_addr_t pxp_phys)
+{
+	if (enable)
+		cdata->pdata->cur->pan_display(pxp_phys);
+	else
+		cdata->pdata->cur->pan_display(cdata->cur_phys);
+}
+
+static int mxsfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+
+	unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
+
+	if (off < info->fix.smem_len)
+		return dma_mmap_writecombine(data->dev, vma,
+					     data->virt_start,
+					     data->phys_start,
+					     info->fix.smem_len);
+	else
+		return -EINVAL;
+}
+
+static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			   u_int transp, struct fb_info *info)
+{
+	if (regno >= 256)	/* no. of hw registers */
+		return 1;
+	/*
+	 * Program hardware... do anything you want with transp
+	 */
+
+	/* grayscale works only partially under directcolor */
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+	/* Directcolor:
+	 *   var->{color}.offset contains start of bitfield
+	 *   var->{color}.length contains length of bitfield
+	 *   {hardwarespecific} contains width of RAMDAC
+	 *   cmap[X] is programmed to
+	 *      (X << red.offset) | (X << green.offset) | (X << blue.offset)
+	 *   RAMDAC[X] is programmed to (red, green, blue)
+	 *
+	 * Pseudocolor:
+	 *    uses offset = 0 && length = RAMDAC register width.
+	 *    var->{color}.offset is 0
+	 *    var->{color}.length contains widht of DAC
+	 *    cmap is not used
+	 *    RAMDAC[X] is programmed to (red, green, blue)
+	 * Truecolor:
+	 *    does not use DAC. Usually 3 are present.
+	 *    var->{color}.offset contains start of bitfield
+	 *    var->{color}.length contains length of bitfield
+	 *    cmap is programmed to
+	 *      (red << red.offset) | (green << green.offset) |
+	 *      (blue << blue.offset) | (transp << transp.offset)
+	 *    RAMDAC does not exist
+	 */
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		red = CNVT_TOHW(red, info->var.red.length);
+		green = CNVT_TOHW(green, info->var.green.length);
+		blue = CNVT_TOHW(blue, info->var.blue.length);
+		transp = CNVT_TOHW(transp, info->var.transp.length);
+		break;
+	case FB_VISUAL_DIRECTCOLOR:
+		red = CNVT_TOHW(red, 8);	/* expect 8 bit DAC */
+		green = CNVT_TOHW(green, 8);
+		blue = CNVT_TOHW(blue, 8);
+		/* hey, there is bug in transp handling... */
+		transp = CNVT_TOHW(transp, 8);
+		break;
+	}
+#undef CNVT_TOHW
+	/* Truecolor has hardware independent palette */
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+		if (regno >= 16)
+			return 1;
+
+		((u32 *) (info->pseudo_palette))[regno] =
+		    (red << info->var.red.offset) |
+		    (green << info->var.green.offset) |
+		    (blue << info->var.blue.offset) |
+		    (transp << info->var.transp.offset);
+	}
+	return 0;
+}
+
+static inline u_long get_line_length(int xres_virtual, int bpp)
+{
+	u_long length;
+
+	length = xres_virtual * bpp;
+	length = (length + 31) & ~31;
+	length >>= 3;
+	return length;
+}
+
+static int get_matching_pentry(struct mxs_platform_fb_entry *pentry,
+			       void *data, int ret_prev)
+{
+	struct fb_var_screeninfo *info = data;
+	pr_debug("%s: %d:%d:%d vs %d:%d:%d\n", __func__,
+		 pentry->x_res, pentry->y_res, pentry->bpp,
+		 info->yres, info->xres, info->bits_per_pixel);
+	if (pentry->x_res == info->yres && pentry->y_res == info->xres &&
+	    pentry->bpp == info->bits_per_pixel)
+		ret_prev = (int)pentry;
+	return ret_prev;
+}
+
+static int get_matching_pentry_by_name(struct mxs_platform_fb_entry *pentry,
+				       void *data, int ret_prev)
+{
+	unsigned char *name = data;
+	if (!strcmp(pentry->name, name))
+		ret_prev = (int)pentry;
+	return ret_prev;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ * XXX: REVISIT
+ */
+static int mxsfb_set_par(struct fb_info *info)
+{
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+	struct mxs_platform_fb_data *pdata = data->pdata;
+	struct mxs_platform_fb_entry *pentry;
+	pentry = (void *)mxs_lcd_iterate_pdata(pdata,
+					       get_matching_pentry, &info->var);
+
+	dev_dbg(data->dev, "%s: xres %d, yres %d, bpp %d\n",
+		__func__,
+		info->var.xres, info->var.yres, info->var.bits_per_pixel);
+	if (!pentry)
+		return -EINVAL;
+
+	info->fix.line_length = get_line_length(info->var.xres_virtual,
+						info->var.bits_per_pixel);
+
+	if (pentry == pdata->cur || !pdata->cur)
+		return 0;
+
+	/* init next panel */
+	pdata->next = pentry;
+
+	set_controller_state(data, F_REENABLE);
+
+	return 0;
+}
+
+static int mxsfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	u32 line_length;
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+	struct mxs_platform_fb_data *pdata = data->pdata;
+
+	/*
+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
+	 */
+
+	if (var->vmode & FB_VMODE_CONUPDATE) {
+		var->vmode |= FB_VMODE_YWRAP;
+		var->xoffset = info->var.xoffset;
+		var->yoffset = info->var.yoffset;
+	}
+
+	pr_debug("%s: xres %d, yres %d, bpp %d\n", __func__,
+		 var->xres, var->yres, var->bits_per_pixel);
+	/*
+	 *  Some very basic checks
+	 */
+	if (!var->xres)
+		var->xres = 1;
+	if (!var->yres)
+		var->yres = 1;
+	if (var->xres > var->xres_virtual)
+		var->xres_virtual = var->xres;
+	if (var->yres > var->yres_virtual)
+		var->yres_virtual = var->yres;
+
+	if (var->xres_virtual < var->xoffset + var->xres)
+		var->xres_virtual = var->xoffset + var->xres;
+	if (var->yres_virtual < var->yoffset + var->yres)
+		var->yres_virtual = var->yoffset + var->yres;
+
+	line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
+	dev_dbg(data->dev,
+		"line_length %d, var->yres_virtual %d, data->mem_size %d\n",
+		line_length, var->yres_virtual, data->mem_size);
+	if (line_length * var->yres_virtual > data->map_size)
+		return -ENOMEM;
+
+	if (!mxs_lcd_iterate_pdata(pdata, get_matching_pentry, var))
+		return -EINVAL;
+
+	if (var->bits_per_pixel == 16) {
+		/* RGBA 5551 */
+		if (var->transp.length) {
+			var->red.offset = 0;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 5;
+			var->blue.offset = 10;
+			var->blue.length = 5;
+			var->transp.offset = 15;
+			var->transp.length = 1;
+		} else {	/* RGB 565 */
+			var->red.offset = 0;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 6;
+			var->blue.offset = 11;
+			var->blue.length = 5;
+			var->transp.offset = 0;
+			var->transp.length = 0;
+		}
+	} else {
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+	}
+
+	var->red.msb_right = 0;
+	var->green.msb_right = 0;
+	var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+
+	return 0;
+}
+
+static int mxsfb_wait_for_vsync(u32 channel, struct fb_info *info)
+{
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+	u32 count = data->vsync_count;
+	int ret = 0;
+
+	__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		     data->regbase + HW_LCDIF_CTRL1_SET);
+	ret = wait_event_interruptible_timeout(data->vsync_wait_q,
+					       count != data->vsync_count,
+					       HZ / 10);
+	__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		     data->regbase + HW_LCDIF_CTRL1_CLR);
+	if (!ret) {
+		dev_err(data->dev, "wait for vsync timed out\n");
+		ret = -ETIMEDOUT;
+	}
+	return ret;
+}
+
+static int mxsfb_ioctl(struct fb_info *info, unsigned int cmd,
+		       unsigned long arg)
+{
+	u32 channel = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case FBIO_WAITFORVSYNC:
+		if (!get_user(channel, (__u32 __user *) arg))
+			ret = mxsfb_wait_for_vsync(channel, info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int mxsfb_blank(int blank, struct fb_info *info)
+{
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+	int ret = 0;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		pr_debug("%s: FB_BLANK_POWERDOWN\n", __func__);
+		mxs_schedule_work(data, F_DISABLE);
+		break;
+
+	case FB_BLANK_UNBLANK:
+		pr_debug("%s: FB_BLANK_UNBLANK\n", __func__);
+		mxs_schedule_work(data, F_ENABLE);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static int mxsfb_pan_display(struct fb_var_screeninfo *var,
+			     struct fb_info *info)
+{
+	struct mxs_fb_data *data = (struct mxs_fb_data *)info;
+	int ret = 0;
+
+	pr_debug("%s: var->xoffset %d, info->var.xoffset %d\n",
+		 __func__, var->xoffset, info->var.xoffset);
+	/* check if var is valid; also, xpan is not supported */
+	if (!var || (var->xoffset != info->var.xoffset) ||
+	    (var->yoffset + var->yres > var->yres_virtual)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!data->pdata->cur->pan_display) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* update framebuffer visual */
+	data->cur_phys = data->phys_start +
+	    info->fix.line_length * var->yoffset;
+	data->pdata->cur->pan_display(data->cur_phys);
+out:
+	return ret;
+}
+
+static struct fb_ops mxsfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = mxsfb_check_var,
+	.fb_set_par = mxsfb_set_par,
+	.fb_mmap = mxsfb_mmap,
+	.fb_setcolreg = mxsfb_setcolreg,
+	.fb_ioctl = mxsfb_ioctl,
+	.fb_blank = mxsfb_blank,
+	.fb_pan_display = mxsfb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static void init_timings(struct mxs_fb_data *data)
+{
+	unsigned phase_time;
+	unsigned timings;
+
+	/* Just use a phase_time of 1. As optimal as it gets, now. */
+	phase_time = 1;
+
+	/* Program all 4 timings the same */
+	timings = phase_time;
+	timings |= timings << 8;
+	timings |= timings << 16;
+	__raw_writel(timings, data->regbase + HW_LCDIF_TIMING);
+}
+
+#ifdef CONFIG_CPU_FREQ
+
+struct mxsfb_notifier_block {
+	struct mxs_fb_data *fb_data;
+	struct notifier_block nb;
+};
+
+static int mxsfb_notifier(struct notifier_block *self,
+			  unsigned long phase, void *p)
+{
+	struct mxsfb_notifier_block *block =
+	    container_of(self, struct mxsfb_notifier_block, nb);
+	struct mxs_fb_data *data = block->fb_data;
+	struct mxs_platform_fb_entry *pentry = data->pdata->cur;
+	u32 old_state = data->state;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return NOTIFY_BAD;
+
+	/* REVISIT */
+	switch (phase) {
+	case CPUFREQ_PRECHANGE:
+		if (old_state == F_ENABLE)
+			if (pentry->blank_panel)
+				pentry->blank_panel(FB_BLANK_POWERDOWN);
+		break;
+
+	case CPUFREQ_POSTCHANGE:
+		if (old_state == F_ENABLE)
+			if (pentry->blank_panel)
+				pentry->blank_panel(FB_BLANK_UNBLANK);
+		break;
+
+	default:
+		dev_dbg(data->dev, "didn't handle notify %ld\n", phase);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct mxsfb_notifier_block mxsfb_nb = {
+	.nb = {
+	       .notifier_call = mxsfb_notifier,
+	       },
+};
+#endif /* CONFIG_CPU_FREQ */
+
+static int get_max_memsize(struct mxs_platform_fb_entry *pentry,
+			   void *data, int ret_prev)
+{
+	struct mxs_fb_data *fbdata = data;
+	int sz = pentry->x_res * pentry->y_res * pentry->bpp / 8;
+	fbdata->mem_size = sz < ret_prev ? ret_prev : sz;
+	pr_debug("%s: mem_size now %d\n", __func__, fbdata->mem_size);
+	return fbdata->mem_size;
+}
+
+static int __devinit mxsfb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxs_fb_data *data;
+	struct resource *res;
+	struct fb_info *info;
+	struct mxs_platform_fb_data *pdata = pdev->dev.platform_data;
+	struct mxs_platform_fb_entry *pentry = NULL;
+
+	if (pdata == NULL) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (default_panel_name) {
+		pentry = (void *)mxs_lcd_iterate_pdata(pdata,
+						       get_matching_pentry_by_name,
+						       default_panel_name);
+		if (pentry) {
+			mxs_lcd_move_pentry_up(pentry, pdata);
+			pdata->cur = pentry;
+		}
+	}
+	if (!default_panel_name || !pentry)
+		pentry = pdata->cur;
+	if (!pentry || !pentry->init_panel || !pentry->run_panel ||
+	    !pentry->release_panel) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	data =
+	    (struct mxs_fb_data *)framebuffer_alloc(sizeof(struct mxs_fb_data) +
+						    sizeof(u32) * 256 -
+						    sizeof(struct fb_info),
+						    &pdev->dev);
+	if (data == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	cdata = data;
+	data->dev = &pdev->dev;
+	data->pdata = pdata;
+	platform_set_drvdata(pdev, data);
+	info = &data->info;
+
+	dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", pentry->x_res,
+		pentry->y_res, pentry->bpp);
+
+	mxs_lcd_iterate_pdata(pdata, get_max_memsize, data);
+
+	data->map_size = PAGE_ALIGN(data->mem_size) * NUM_SCREENS;
+	dev_dbg(&pdev->dev, "memory to allocate: %d\n", data->map_size);
+
+	data->virt_start = dma_alloc_writecombine(&pdev->dev,
+						  data->map_size,
+						  &data->phys_start,
+						  GFP_KERNEL);
+
+	if (data->virt_start == NULL) {
+		ret = -ENOMEM;
+		goto out_dma;
+	}
+	dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", data->virt_start,
+		data->phys_start);
+	mutex_init(&data->blank_mutex);
+	INIT_WORK(&data->work, mxsfb_task);
+	data->state = F_ENABLE;
+
+	mxsfb_default.bits_per_pixel = pentry->bpp;
+	/* NB: rotated */
+	mxsfb_default.xres = pentry->y_res;
+	mxsfb_default.yres = pentry->x_res;
+	mxsfb_default.xres_virtual = pentry->y_res;
+	mxsfb_default.yres_virtual = data->map_size /
+	    (pentry->y_res * pentry->bpp / 8);
+	if (mxsfb_default.yres_virtual >= mxsfb_default.yres * 2)
+		mxsfb_default.yres_virtual = mxsfb_default.yres * 2;
+	else
+		mxsfb_default.yres_virtual = mxsfb_default.yres;
+
+	mxsfb_fix.smem_start = data->phys_start;
+	mxsfb_fix.smem_len = pentry->y_res * pentry->x_res * pentry->bpp / 8;
+	mxsfb_fix.ypanstep = 1;
+
+	switch (pentry->bpp) {
+	case 32:
+	case 24:
+		mxsfb_default.red.offset = 16;
+		mxsfb_default.red.length = 8;
+		mxsfb_default.green.offset = 8;
+		mxsfb_default.green.length = 8;
+		mxsfb_default.blue.offset = 0;
+		mxsfb_default.blue.length = 8;
+		break;
+
+	case 16:
+		mxsfb_default.red.offset = 11;
+		mxsfb_default.red.length = 5;
+		mxsfb_default.green.offset = 5;
+		mxsfb_default.green.length = 6;
+		mxsfb_default.blue.offset = 0;
+		mxsfb_default.blue.length = 5;
+		break;
+
+	default:
+		dev_err(&pdev->dev, "unsupported bitwidth %d\n", pentry->bpp);
+		ret = -EINVAL;
+		goto out_dma;
+	}
+
+	info->screen_base = data->virt_start;
+	info->fbops = &mxsfb_ops;
+	info->var = mxsfb_default;
+	info->fix = mxsfb_fix;
+	info->pseudo_palette = &data->par;
+	data->par = NULL;
+	info->flags = FBINFO_FLAG_DEFAULT;
+
+	init_waitqueue_head(&data->vsync_wait_q);
+	data->vsync_count = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma;
+	}
+	data->regbase = (unsigned long)IO_ADDRESS(res->start);
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma;
+	}
+	data->irq = res->start;
+
+	mxsfb_check_var(&info->var, info);
+
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret)
+		goto out_cmap;
+
+	mxsfb_set_par(info);
+
+	mxs_init_lcdif();
+	ret = pentry->init_panel(data->dev, data->phys_start,
+				 mxsfb_fix.smem_len, pentry);
+	if (ret) {
+		dev_err(&pdev->dev, "cannot initialize LCD panel\n");
+		goto out_panel;
+	}
+	dev_dbg(&pdev->dev, "LCD panel initialized\n");
+	init_timings(data);
+
+	ret = request_irq(data->irq, lcd_irq_handler, 0, "fb_irq", data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+			data->irq, ret);
+		goto out_panel;
+	}
+	ret = register_framebuffer(info);
+	if (ret)
+		goto out_irq;
+
+	pentry->run_panel();
+	/* REVISIT: temporary workaround for MX23EVK */
+	mxsfb_disable_controller(data);
+	mxsfb_enable_controller(data);
+	data->cur_phys = data->phys_start;
+	dev_dbg(&pdev->dev, "LCD running now\n");
+
+#ifdef CONFIG_CPU_FREQ
+	mxsfb_nb.fb_data = data;
+	cpufreq_register_notifier(&mxsfb_nb.nb, CPUFREQ_TRANSITION_NOTIFIER);
+#endif /* CONFIG_CPU_FREQ */
+
+	goto out;
+
+out_irq:
+	free_irq(data->irq, data);
+out_panel:
+	fb_dealloc_cmap(&info->cmap);
+out_cmap:
+	dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start,
+			      data->phys_start);
+out_dma:
+	kfree(data);
+out:
+	return ret;
+}
+
+static int mxsfb_remove(struct platform_device *pdev)
+{
+	struct mxs_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_DISABLE);
+
+	unregister_framebuffer(&data->info);
+	framebuffer_release(&data->info);
+	fb_dealloc_cmap(&data->info.cmap);
+	free_irq(data->irq, data);
+	dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start,
+			      data->phys_start);
+	kfree(data);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxsfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mxs_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_DISABLE);
+
+	return 0;
+}
+
+static int mxsfb_resume(struct platform_device *pdev)
+{
+	struct mxs_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_ENABLE);
+	return 0;
+}
+#else
+#define mxsfb_suspend	NULL
+#define	mxsfb_resume	NULL
+#endif
+
+static struct platform_driver mxsfb_driver = {
+	.probe = mxsfb_probe,
+	.remove = mxsfb_remove,
+	.suspend = mxsfb_suspend,
+	.resume = mxsfb_resume,
+	.driver = {
+		   .name = "mxs-fb",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init mxsfb_init(void)
+{
+	return platform_driver_register(&mxsfb_driver);
+}
+
+static void __exit mxsfb_exit(void)
+{
+	platform_driver_unregister(&mxsfb_driver);
+}
+
+module_init(mxsfb_init);
+module_exit(mxsfb_exit);
+
+/*
+ * LCD panel select
+ */
+static int __init default_panel_select(char *str)
+{
+	default_panel_name = str;
+	return 0;
+}
+
+__setup("lcd_panel=", default_panel_select);
+
+MODULE_AUTHOR("Vitaly Wool <vital@embeddedalley.com>");
+MODULE_DESCRIPTION("MXS Framebuffer Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxs/regs-tvenc.h b/drivers/video/mxs/regs-tvenc.h
new file mode 100644
index 000000000000..bd2493e2dee5
--- /dev/null
+++ b/drivers/video/mxs/regs-tvenc.h
@@ -0,0 +1,583 @@
+/*
+ * Freescale TVENC Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.00
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___TVENC_H
+#define __ARCH_ARM___TVENC_H
+
+
+#define HW_TVENC_CTRL	(0x00000000)
+#define HW_TVENC_CTRL_SET	(0x00000004)
+#define HW_TVENC_CTRL_CLR	(0x00000008)
+#define HW_TVENC_CTRL_TOG	(0x0000000c)
+
+#define BM_TVENC_CTRL_SFTRST	0x80000000
+#define BM_TVENC_CTRL_CLKGATE	0x40000000
+#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT	0x20000000
+#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT	0x10000000
+#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT	0x08000000
+#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT	0x04000000
+#define BP_TVENC_CTRL_RSRVD1	6
+#define BM_TVENC_CTRL_RSRVD1	0x03FFFFC0
+#define BF_TVENC_CTRL_RSRVD1(v)  \
+		(((v) << 6) & BM_TVENC_CTRL_RSRVD1)
+#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE	0x00000020
+#define BM_TVENC_CTRL_DAC_FIFO_NO_READ	0x00000010
+#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST	0x00000008
+#define BP_TVENC_CTRL_RSRVD2	1
+#define BM_TVENC_CTRL_RSRVD2	0x00000006
+#define BF_TVENC_CTRL_RSRVD2(v)  \
+		(((v) << 1) & BM_TVENC_CTRL_RSRVD2)
+#define BM_TVENC_CTRL_DAC_MUX_MODE	0x00000001
+
+#define HW_TVENC_CONFIG	(0x00000010)
+#define HW_TVENC_CONFIG_SET	(0x00000014)
+#define HW_TVENC_CONFIG_CLR	(0x00000018)
+#define HW_TVENC_CONFIG_TOG	(0x0000001c)
+
+#define BP_TVENC_CONFIG_RSRVD5	28
+#define BM_TVENC_CONFIG_RSRVD5	0xF0000000
+#define BF_TVENC_CONFIG_RSRVD5(v) \
+		(((v) << 28) & BM_TVENC_CONFIG_RSRVD5)
+#define BM_TVENC_CONFIG_DEFAULT_PICFORM	0x08000000
+#define BP_TVENC_CONFIG_YDEL_ADJ	24
+#define BM_TVENC_CONFIG_YDEL_ADJ	0x07000000
+#define BF_TVENC_CONFIG_YDEL_ADJ(v)  \
+		(((v) << 24) & BM_TVENC_CONFIG_YDEL_ADJ)
+#define BM_TVENC_CONFIG_RSRVD4	0x00800000
+#define BM_TVENC_CONFIG_RSRVD3	0x00400000
+#define BM_TVENC_CONFIG_ADD_YPBPR_PED	0x00200000
+#define BM_TVENC_CONFIG_PAL_SHAPE	0x00100000
+#define BM_TVENC_CONFIG_NO_PED	0x00080000
+#define BM_TVENC_CONFIG_COLOR_BAR_EN	0x00040000
+#define BP_TVENC_CONFIG_YGAIN_SEL	16
+#define BM_TVENC_CONFIG_YGAIN_SEL	0x00030000
+#define BF_TVENC_CONFIG_YGAIN_SEL(v)  \
+		(((v) << 16) & BM_TVENC_CONFIG_YGAIN_SEL)
+#define BP_TVENC_CONFIG_CGAIN	14
+#define BM_TVENC_CONFIG_CGAIN	0x0000C000
+#define BF_TVENC_CONFIG_CGAIN(v)  \
+		(((v) << 14) & BM_TVENC_CONFIG_CGAIN)
+#define BP_TVENC_CONFIG_CLK_PHS	12
+#define BM_TVENC_CONFIG_CLK_PHS	0x00003000
+#define BF_TVENC_CONFIG_CLK_PHS(v)  \
+		(((v) << 12) & BM_TVENC_CONFIG_CLK_PHS)
+#define BM_TVENC_CONFIG_RSRVD2	0x00000800
+#define BM_TVENC_CONFIG_FSYNC_ENBL	0x00000400
+#define BM_TVENC_CONFIG_FSYNC_PHS	0x00000200
+#define BM_TVENC_CONFIG_HSYNC_PHS	0x00000100
+#define BM_TVENC_CONFIG_VSYNC_PHS	0x00000080
+#define BP_TVENC_CONFIG_SYNC_MODE	4
+#define BM_TVENC_CONFIG_SYNC_MODE	0x00000070
+#define BF_TVENC_CONFIG_SYNC_MODE(v)  \
+		(((v) << 4) & BM_TVENC_CONFIG_SYNC_MODE)
+#define BM_TVENC_CONFIG_RSRVD1	0x00000008
+#define BP_TVENC_CONFIG_ENCD_MODE	0
+#define BM_TVENC_CONFIG_ENCD_MODE	0x00000007
+#define BF_TVENC_CONFIG_ENCD_MODE(v)  \
+		(((v) << 0) & BM_TVENC_CONFIG_ENCD_MODE)
+
+#define HW_TVENC_FILTCTRL	(0x00000020)
+#define HW_TVENC_FILTCTRL_SET	(0x00000024)
+#define HW_TVENC_FILTCTRL_CLR	(0x00000028)
+#define HW_TVENC_FILTCTRL_TOG	(0x0000002c)
+
+#define BP_TVENC_FILTCTRL_RSRVD1	20
+#define BM_TVENC_FILTCTRL_RSRVD1	0xFFF00000
+#define BF_TVENC_FILTCTRL_RSRVD1(v) \
+		(((v) << 20) & BM_TVENC_FILTCTRL_RSRVD1)
+#define BM_TVENC_FILTCTRL_YSHARP_BW	0x00080000
+#define BM_TVENC_FILTCTRL_YD_OFFSETSEL	0x00040000
+#define BM_TVENC_FILTCTRL_SEL_YLPF	0x00020000
+#define BM_TVENC_FILTCTRL_SEL_CLPF	0x00010000
+#define BM_TVENC_FILTCTRL_SEL_YSHARP	0x00008000
+#define BM_TVENC_FILTCTRL_YLPF_COEFSEL	0x00004000
+#define BM_TVENC_FILTCTRL_COEFSEL_CLPF	0x00002000
+#define BM_TVENC_FILTCTRL_YS_GAINSGN	0x00001000
+#define BP_TVENC_FILTCTRL_YS_GAINSEL	10
+#define BM_TVENC_FILTCTRL_YS_GAINSEL	0x00000C00
+#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)  \
+		(((v) << 10) & BM_TVENC_FILTCTRL_YS_GAINSEL)
+#define BM_TVENC_FILTCTRL_RSRVD2	0x00000200
+#define BM_TVENC_FILTCTRL_RSRVD3	0x00000100
+#define BP_TVENC_FILTCTRL_RSRVD4	0
+#define BM_TVENC_FILTCTRL_RSRVD4	0x000000FF
+#define BF_TVENC_FILTCTRL_RSRVD4(v)  \
+		(((v) << 0) & BM_TVENC_FILTCTRL_RSRVD4)
+
+#define HW_TVENC_SYNCOFFSET	(0x00000030)
+#define HW_TVENC_SYNCOFFSET_SET	(0x00000034)
+#define HW_TVENC_SYNCOFFSET_CLR	(0x00000038)
+#define HW_TVENC_SYNCOFFSET_TOG	(0x0000003c)
+
+#define BM_TVENC_SYNCOFFSET_RSRVD1	0x80000000
+#define BP_TVENC_SYNCOFFSET_HSO	20
+#define BM_TVENC_SYNCOFFSET_HSO	0x7FF00000
+#define BF_TVENC_SYNCOFFSET_HSO(v)  \
+		(((v) << 20) & BM_TVENC_SYNCOFFSET_HSO)
+#define BP_TVENC_SYNCOFFSET_VSO	10
+#define BM_TVENC_SYNCOFFSET_VSO	0x000FFC00
+#define BF_TVENC_SYNCOFFSET_VSO(v)  \
+		(((v) << 10) & BM_TVENC_SYNCOFFSET_VSO)
+#define BP_TVENC_SYNCOFFSET_HLC	0
+#define BM_TVENC_SYNCOFFSET_HLC	0x000003FF
+#define BF_TVENC_SYNCOFFSET_HLC(v)  \
+		(((v) << 0) & BM_TVENC_SYNCOFFSET_HLC)
+
+#define HW_TVENC_HTIMINGSYNC0	(0x00000040)
+#define HW_TVENC_HTIMINGSYNC0_SET	(0x00000044)
+#define HW_TVENC_HTIMINGSYNC0_CLR	(0x00000048)
+#define HW_TVENC_HTIMINGSYNC0_TOG	(0x0000004c)
+
+#define BP_TVENC_HTIMINGSYNC0_RSRVD2	26
+#define BM_TVENC_HTIMINGSYNC0_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGSYNC0_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_END	16
+#define BM_TVENC_HTIMINGSYNC0_SYNC_END	0x03FF0000
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGSYNC0_SYNC_END)
+#define BP_TVENC_HTIMINGSYNC0_RSRVD1	10
+#define BM_TVENC_HTIMINGSYNC0_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGSYNC0_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT	0
+#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT	0x000003FF
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGSYNC0_SYNC_STRT)
+
+#define HW_TVENC_HTIMINGSYNC1	(0x00000050)
+#define HW_TVENC_HTIMINGSYNC1_SET	(0x00000054)
+#define HW_TVENC_HTIMINGSYNC1_CLR	(0x00000058)
+#define HW_TVENC_HTIMINGSYNC1_TOG	(0x0000005c)
+
+#define BP_TVENC_HTIMINGSYNC1_RSRVD2	26
+#define BM_TVENC_HTIMINGSYNC1_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGSYNC1_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND	16
+#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND	0x03FF0000
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGSYNC1_SYNC_EQEND)
+#define BP_TVENC_HTIMINGSYNC1_RSRVD1	10
+#define BM_TVENC_HTIMINGSYNC1_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGSYNC1_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND	0
+#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND	0x000003FF
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGSYNC1_SYNC_SREND)
+
+#define HW_TVENC_HTIMINGACTIVE	(0x00000060)
+#define HW_TVENC_HTIMINGACTIVE_SET	(0x00000064)
+#define HW_TVENC_HTIMINGACTIVE_CLR	(0x00000068)
+#define HW_TVENC_HTIMINGACTIVE_TOG	(0x0000006c)
+
+#define BP_TVENC_HTIMINGACTIVE_RSRVD2	26
+#define BM_TVENC_HTIMINGACTIVE_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGACTIVE_RSRVD2)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_END	16
+#define BM_TVENC_HTIMINGACTIVE_ACTV_END	0x03FF0000
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGACTIVE_ACTV_END)
+#define BP_TVENC_HTIMINGACTIVE_RSRVD1	10
+#define BM_TVENC_HTIMINGACTIVE_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGACTIVE_RSRVD1)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT	0
+#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT	0x000003FF
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGACTIVE_ACTV_STRT)
+
+#define HW_TVENC_HTIMINGBURST0	(0x00000070)
+#define HW_TVENC_HTIMINGBURST0_SET	(0x00000074)
+#define HW_TVENC_HTIMINGBURST0_CLR	(0x00000078)
+#define HW_TVENC_HTIMINGBURST0_TOG	(0x0000007c)
+
+#define BP_TVENC_HTIMINGBURST0_RSRVD2	26
+#define BM_TVENC_HTIMINGBURST0_RSRVD2	0xFC000000
+#define BF_TVENC_HTIMINGBURST0_RSRVD2(v) \
+		(((v) << 26) & BM_TVENC_HTIMINGBURST0_RSRVD2)
+#define BP_TVENC_HTIMINGBURST0_WBRST_STRT	16
+#define BM_TVENC_HTIMINGBURST0_WBRST_STRT	0x03FF0000
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)  \
+		(((v) << 16) & BM_TVENC_HTIMINGBURST0_WBRST_STRT)
+#define BP_TVENC_HTIMINGBURST0_RSRVD1	10
+#define BM_TVENC_HTIMINGBURST0_RSRVD1	0x0000FC00
+#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_HTIMINGBURST0_RSRVD1)
+#define BP_TVENC_HTIMINGBURST0_NBRST_STRT	0
+#define BM_TVENC_HTIMINGBURST0_NBRST_STRT	0x000003FF
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGBURST0_NBRST_STRT)
+
+#define HW_TVENC_HTIMINGBURST1	(0x00000080)
+#define HW_TVENC_HTIMINGBURST1_SET	(0x00000084)
+#define HW_TVENC_HTIMINGBURST1_CLR	(0x00000088)
+#define HW_TVENC_HTIMINGBURST1_TOG	(0x0000008c)
+
+#define BP_TVENC_HTIMINGBURST1_RSRVD1	10
+#define BM_TVENC_HTIMINGBURST1_RSRVD1	0xFFFFFC00
+#define BF_TVENC_HTIMINGBURST1_RSRVD1(v) \
+		(((v) << 10) & BM_TVENC_HTIMINGBURST1_RSRVD1)
+#define BP_TVENC_HTIMINGBURST1_BRST_END	0
+#define BM_TVENC_HTIMINGBURST1_BRST_END	0x000003FF
+#define BF_TVENC_HTIMINGBURST1_BRST_END(v)  \
+		(((v) << 0) & BM_TVENC_HTIMINGBURST1_BRST_END)
+
+#define HW_TVENC_VTIMING0	(0x00000090)
+#define HW_TVENC_VTIMING0_SET	(0x00000094)
+#define HW_TVENC_VTIMING0_CLR	(0x00000098)
+#define HW_TVENC_VTIMING0_TOG	(0x0000009c)
+
+#define BP_TVENC_VTIMING0_RSRVD3	26
+#define BM_TVENC_VTIMING0_RSRVD3	0xFC000000
+#define BF_TVENC_VTIMING0_RSRVD3(v) \
+		(((v) << 26) & BM_TVENC_VTIMING0_RSRVD3)
+#define BP_TVENC_VTIMING0_VSTRT_PREEQ	16
+#define BM_TVENC_VTIMING0_VSTRT_PREEQ	0x03FF0000
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)  \
+		(((v) << 16) & BM_TVENC_VTIMING0_VSTRT_PREEQ)
+#define BP_TVENC_VTIMING0_RSRVD2	14
+#define BM_TVENC_VTIMING0_RSRVD2	0x0000C000
+#define BF_TVENC_VTIMING0_RSRVD2(v)  \
+		(((v) << 14) & BM_TVENC_VTIMING0_RSRVD2)
+#define BP_TVENC_VTIMING0_VSTRT_ACTV	8
+#define BM_TVENC_VTIMING0_VSTRT_ACTV	0x00003F00
+#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)  \
+		(((v) << 8) & BM_TVENC_VTIMING0_VSTRT_ACTV)
+#define BP_TVENC_VTIMING0_RSRVD1	6
+#define BM_TVENC_VTIMING0_RSRVD1	0x000000C0
+#define BF_TVENC_VTIMING0_RSRVD1(v)  \
+		(((v) << 6) & BM_TVENC_VTIMING0_RSRVD1)
+#define BP_TVENC_VTIMING0_VSTRT_SUBPH	0
+#define BM_TVENC_VTIMING0_VSTRT_SUBPH	0x0000003F
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)  \
+		(((v) << 0) & BM_TVENC_VTIMING0_VSTRT_SUBPH)
+
+#define HW_TVENC_VTIMING1	(0x000000a0)
+#define HW_TVENC_VTIMING1_SET	(0x000000a4)
+#define HW_TVENC_VTIMING1_CLR	(0x000000a8)
+#define HW_TVENC_VTIMING1_TOG	(0x000000ac)
+
+#define BP_TVENC_VTIMING1_RSRVD3	30
+#define BM_TVENC_VTIMING1_RSRVD3	0xC0000000
+#define BF_TVENC_VTIMING1_RSRVD3(v) \
+		(((v) << 30) & BM_TVENC_VTIMING1_RSRVD3)
+#define BP_TVENC_VTIMING1_VSTRT_POSTEQ	24
+#define BM_TVENC_VTIMING1_VSTRT_POSTEQ	0x3F000000
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)  \
+		(((v) << 24) & BM_TVENC_VTIMING1_VSTRT_POSTEQ)
+#define BP_TVENC_VTIMING1_RSRVD2	22
+#define BM_TVENC_VTIMING1_RSRVD2	0x00C00000
+#define BF_TVENC_VTIMING1_RSRVD2(v)  \
+		(((v) << 22) & BM_TVENC_VTIMING1_RSRVD2)
+#define BP_TVENC_VTIMING1_VSTRT_SERRA	16
+#define BM_TVENC_VTIMING1_VSTRT_SERRA	0x003F0000
+#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)  \
+		(((v) << 16) & BM_TVENC_VTIMING1_VSTRT_SERRA)
+#define BP_TVENC_VTIMING1_RSRVD1	10
+#define BM_TVENC_VTIMING1_RSRVD1	0x0000FC00
+#define BF_TVENC_VTIMING1_RSRVD1(v)  \
+		(((v) << 10) & BM_TVENC_VTIMING1_RSRVD1)
+#define BP_TVENC_VTIMING1_LAST_FLD_LN	0
+#define BM_TVENC_VTIMING1_LAST_FLD_LN	0x000003FF
+#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)  \
+		(((v) << 0) & BM_TVENC_VTIMING1_LAST_FLD_LN)
+
+#define HW_TVENC_MISC	(0x000000b0)
+#define HW_TVENC_MISC_SET	(0x000000b4)
+#define HW_TVENC_MISC_CLR	(0x000000b8)
+#define HW_TVENC_MISC_TOG	(0x000000bc)
+
+#define BP_TVENC_MISC_RSRVD3	25
+#define BM_TVENC_MISC_RSRVD3	0xFE000000
+#define BF_TVENC_MISC_RSRVD3(v) \
+		(((v) << 25) & BM_TVENC_MISC_RSRVD3)
+#define BP_TVENC_MISC_LPF_RST_OFF	16
+#define BM_TVENC_MISC_LPF_RST_OFF	0x01FF0000
+#define BF_TVENC_MISC_LPF_RST_OFF(v)  \
+		(((v) << 16) & BM_TVENC_MISC_LPF_RST_OFF)
+#define BP_TVENC_MISC_RSRVD2	12
+#define BM_TVENC_MISC_RSRVD2	0x0000F000
+#define BF_TVENC_MISC_RSRVD2(v)  \
+		(((v) << 12) & BM_TVENC_MISC_RSRVD2)
+#define BM_TVENC_MISC_NTSC_LN_CNT	0x00000800
+#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT	0x00000400
+#define BP_TVENC_MISC_FSC_PHASE_RST	8
+#define BM_TVENC_MISC_FSC_PHASE_RST	0x00000300
+#define BF_TVENC_MISC_FSC_PHASE_RST(v)  \
+		(((v) << 8) & BM_TVENC_MISC_FSC_PHASE_RST)
+#define BP_TVENC_MISC_BRUCHB	6
+#define BM_TVENC_MISC_BRUCHB	0x000000C0
+#define BF_TVENC_MISC_BRUCHB(v)  \
+		(((v) << 6) & BM_TVENC_MISC_BRUCHB)
+#define BP_TVENC_MISC_AGC_LVL_CTRL	4
+#define BM_TVENC_MISC_AGC_LVL_CTRL	0x00000030
+#define BF_TVENC_MISC_AGC_LVL_CTRL(v)  \
+		(((v) << 4) & BM_TVENC_MISC_AGC_LVL_CTRL)
+#define BM_TVENC_MISC_RSRVD1	0x00000008
+#define BM_TVENC_MISC_CS_INVERT_CTRL	0x00000004
+#define BP_TVENC_MISC_Y_BLANK_CTRL	0
+#define BM_TVENC_MISC_Y_BLANK_CTRL	0x00000003
+#define BF_TVENC_MISC_Y_BLANK_CTRL(v)  \
+		(((v) << 0) & BM_TVENC_MISC_Y_BLANK_CTRL)
+
+#define HW_TVENC_COLORSUB0	(0x000000c0)
+#define HW_TVENC_COLORSUB0_SET	(0x000000c4)
+#define HW_TVENC_COLORSUB0_CLR	(0x000000c8)
+#define HW_TVENC_COLORSUB0_TOG	(0x000000cc)
+
+#define BP_TVENC_COLORSUB0_PHASE_INC	0
+#define BM_TVENC_COLORSUB0_PHASE_INC	0xFFFFFFFF
+#define BF_TVENC_COLORSUB0_PHASE_INC(v)	(v)
+
+#define HW_TVENC_COLORSUB1	(0x000000d0)
+#define HW_TVENC_COLORSUB1_SET	(0x000000d4)
+#define HW_TVENC_COLORSUB1_CLR	(0x000000d8)
+#define HW_TVENC_COLORSUB1_TOG	(0x000000dc)
+
+#define BP_TVENC_COLORSUB1_PHASE_OFFSET	0
+#define BM_TVENC_COLORSUB1_PHASE_OFFSET	0xFFFFFFFF
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)	(v)
+
+#define HW_TVENC_COPYPROTECT	(0x000000e0)
+#define HW_TVENC_COPYPROTECT_SET	(0x000000e4)
+#define HW_TVENC_COPYPROTECT_CLR	(0x000000e8)
+#define HW_TVENC_COPYPROTECT_TOG	(0x000000ec)
+
+#define BP_TVENC_COPYPROTECT_RSRVD1	16
+#define BM_TVENC_COPYPROTECT_RSRVD1	0xFFFF0000
+#define BF_TVENC_COPYPROTECT_RSRVD1(v) \
+		(((v) << 16) & BM_TVENC_COPYPROTECT_RSRVD1)
+#define BM_TVENC_COPYPROTECT_WSS_ENBL	0x00008000
+#define BM_TVENC_COPYPROTECT_CGMS_ENBL	0x00004000
+#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA	0
+#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA	0x00003FFF
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)  \
+		(((v) << 0) & BM_TVENC_COPYPROTECT_WSS_CGMS_DATA)
+
+#define HW_TVENC_CLOSEDCAPTION	(0x000000f0)
+#define HW_TVENC_CLOSEDCAPTION_SET	(0x000000f4)
+#define HW_TVENC_CLOSEDCAPTION_CLR	(0x000000f8)
+#define HW_TVENC_CLOSEDCAPTION_TOG	(0x000000fc)
+
+#define BP_TVENC_CLOSEDCAPTION_RSRVD1	20
+#define BM_TVENC_CLOSEDCAPTION_RSRVD1	0xFFF00000
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) \
+		(((v) << 20) & BM_TVENC_CLOSEDCAPTION_RSRVD1)
+#define BP_TVENC_CLOSEDCAPTION_CC_ENBL	18
+#define BM_TVENC_CLOSEDCAPTION_CC_ENBL	0x000C0000
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)  \
+		(((v) << 18) & BM_TVENC_CLOSEDCAPTION_CC_ENBL)
+#define BP_TVENC_CLOSEDCAPTION_CC_FILL	16
+#define BM_TVENC_CLOSEDCAPTION_CC_FILL	0x00030000
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)  \
+		(((v) << 16) & BM_TVENC_CLOSEDCAPTION_CC_FILL)
+#define BP_TVENC_CLOSEDCAPTION_CC_DATA	0
+#define BM_TVENC_CLOSEDCAPTION_CC_DATA	0x0000FFFF
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)  \
+		(((v) << 0) & BM_TVENC_CLOSEDCAPTION_CC_DATA)
+
+#define HW_TVENC_COLORBURST	(0x00000140)
+#define HW_TVENC_COLORBURST_SET	(0x00000144)
+#define HW_TVENC_COLORBURST_CLR	(0x00000148)
+#define HW_TVENC_COLORBURST_TOG	(0x0000014c)
+
+#define BP_TVENC_COLORBURST_NBA	24
+#define BM_TVENC_COLORBURST_NBA	0xFF000000
+#define BF_TVENC_COLORBURST_NBA(v) \
+		(((v) << 24) & BM_TVENC_COLORBURST_NBA)
+#define BP_TVENC_COLORBURST_PBA	16
+#define BM_TVENC_COLORBURST_PBA	0x00FF0000
+#define BF_TVENC_COLORBURST_PBA(v)  \
+		(((v) << 16) & BM_TVENC_COLORBURST_PBA)
+#define BP_TVENC_COLORBURST_RSRVD1	12
+#define BM_TVENC_COLORBURST_RSRVD1	0x0000F000
+#define BF_TVENC_COLORBURST_RSRVD1(v)  \
+		(((v) << 12) & BM_TVENC_COLORBURST_RSRVD1)
+#define BP_TVENC_COLORBURST_RSRVD2	0
+#define BM_TVENC_COLORBURST_RSRVD2	0x00000FFF
+#define BF_TVENC_COLORBURST_RSRVD2(v)  \
+		(((v) << 0) & BM_TVENC_COLORBURST_RSRVD2)
+
+#define HW_TVENC_MACROVISION0	(0x00000150)
+#define HW_TVENC_MACROVISION0_SET	(0x00000154)
+#define HW_TVENC_MACROVISION0_CLR	(0x00000158)
+#define HW_TVENC_MACROVISION0_TOG	(0x0000015c)
+
+#define BP_TVENC_MACROVISION0_DATA	0
+#define BM_TVENC_MACROVISION0_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION0_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION1	(0x00000160)
+#define HW_TVENC_MACROVISION1_SET	(0x00000164)
+#define HW_TVENC_MACROVISION1_CLR	(0x00000168)
+#define HW_TVENC_MACROVISION1_TOG	(0x0000016c)
+
+#define BP_TVENC_MACROVISION1_DATA	0
+#define BM_TVENC_MACROVISION1_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION1_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION2	(0x00000170)
+#define HW_TVENC_MACROVISION2_SET	(0x00000174)
+#define HW_TVENC_MACROVISION2_CLR	(0x00000178)
+#define HW_TVENC_MACROVISION2_TOG	(0x0000017c)
+
+#define BP_TVENC_MACROVISION2_DATA	0
+#define BM_TVENC_MACROVISION2_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION2_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION3	(0x00000180)
+#define HW_TVENC_MACROVISION3_SET	(0x00000184)
+#define HW_TVENC_MACROVISION3_CLR	(0x00000188)
+#define HW_TVENC_MACROVISION3_TOG	(0x0000018c)
+
+#define BP_TVENC_MACROVISION3_DATA	0
+#define BM_TVENC_MACROVISION3_DATA	0xFFFFFFFF
+#define BF_TVENC_MACROVISION3_DATA(v)	(v)
+
+#define HW_TVENC_MACROVISION4	(0x00000190)
+#define HW_TVENC_MACROVISION4_SET	(0x00000194)
+#define HW_TVENC_MACROVISION4_CLR	(0x00000198)
+#define HW_TVENC_MACROVISION4_TOG	(0x0000019c)
+
+#define BP_TVENC_MACROVISION4_RSRVD2	24
+#define BM_TVENC_MACROVISION4_RSRVD2	0xFF000000
+#define BF_TVENC_MACROVISION4_RSRVD2(v) \
+		(((v) << 24) & BM_TVENC_MACROVISION4_RSRVD2)
+#define BP_TVENC_MACROVISION4_MACV_TST	16
+#define BM_TVENC_MACROVISION4_MACV_TST	0x00FF0000
+#define BF_TVENC_MACROVISION4_MACV_TST(v)  \
+		(((v) << 16) & BM_TVENC_MACROVISION4_MACV_TST)
+#define BP_TVENC_MACROVISION4_RSRVD1	11
+#define BM_TVENC_MACROVISION4_RSRVD1	0x0000F800
+#define BF_TVENC_MACROVISION4_RSRVD1(v)  \
+		(((v) << 11) & BM_TVENC_MACROVISION4_RSRVD1)
+#define BP_TVENC_MACROVISION4_DATA	0
+#define BM_TVENC_MACROVISION4_DATA	0x000007FF
+#define BF_TVENC_MACROVISION4_DATA(v)  \
+		(((v) << 0) & BM_TVENC_MACROVISION4_DATA)
+
+#define HW_TVENC_DACCTRL	(0x000001a0)
+#define HW_TVENC_DACCTRL_SET	(0x000001a4)
+#define HW_TVENC_DACCTRL_CLR	(0x000001a8)
+#define HW_TVENC_DACCTRL_TOG	(0x000001ac)
+
+#define BM_TVENC_DACCTRL_TEST3	0x80000000
+#define BM_TVENC_DACCTRL_RSRVD1	0x40000000
+#define BM_TVENC_DACCTRL_RSRVD2	0x20000000
+#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN	0x10000000
+#define BM_TVENC_DACCTRL_TEST2	0x08000000
+#define BM_TVENC_DACCTRL_RSRVD3	0x04000000
+#define BM_TVENC_DACCTRL_RSRVD4	0x02000000
+#define BM_TVENC_DACCTRL_JACK1_DET_EN	0x01000000
+#define BM_TVENC_DACCTRL_TEST1	0x00800000
+#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT	0x00400000
+#define BP_TVENC_DACCTRL_JACK_DIS_ADJ	20
+#define BM_TVENC_DACCTRL_JACK_DIS_ADJ	0x00300000
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)  \
+		(((v) << 20) & BM_TVENC_DACCTRL_JACK_DIS_ADJ)
+#define BM_TVENC_DACCTRL_GAINDN	0x00080000
+#define BM_TVENC_DACCTRL_GAINUP	0x00040000
+#define BM_TVENC_DACCTRL_INVERT_CLK	0x00020000
+#define BM_TVENC_DACCTRL_SELECT_CLK	0x00010000
+#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE	0x00008000
+#define BM_TVENC_DACCTRL_RSRVD5	0x00004000
+#define BM_TVENC_DACCTRL_RSRVD6	0x00002000
+#define BM_TVENC_DACCTRL_PWRUP1	0x00001000
+#define BM_TVENC_DACCTRL_WELL_TOVDD	0x00000800
+#define BM_TVENC_DACCTRL_RSRVD7	0x00000400
+#define BM_TVENC_DACCTRL_RSRVD8	0x00000200
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1	0x00000100
+#define BM_TVENC_DACCTRL_LOWER_SIGNAL	0x00000080
+#define BP_TVENC_DACCTRL_RVAL	4
+#define BM_TVENC_DACCTRL_RVAL	0x00000070
+#define BF_TVENC_DACCTRL_RVAL(v)  \
+		(((v) << 4) & BM_TVENC_DACCTRL_RVAL)
+#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM	0x00000008
+#define BM_TVENC_DACCTRL_HALF_CURRENT	0x00000004
+#define BP_TVENC_DACCTRL_CASC_ADJ	0
+#define BM_TVENC_DACCTRL_CASC_ADJ	0x00000003
+#define BF_TVENC_DACCTRL_CASC_ADJ(v)  \
+		(((v) << 0) & BM_TVENC_DACCTRL_CASC_ADJ)
+
+#define HW_TVENC_DACSTATUS	(0x000001b0)
+#define HW_TVENC_DACSTATUS_SET	(0x000001b4)
+#define HW_TVENC_DACSTATUS_CLR	(0x000001b8)
+#define HW_TVENC_DACSTATUS_TOG	(0x000001bc)
+
+#define BP_TVENC_DACSTATUS_RSRVD1	13
+#define BM_TVENC_DACSTATUS_RSRVD1	0xFFFFE000
+#define BF_TVENC_DACSTATUS_RSRVD1(v) \
+		(((v) << 13) & BM_TVENC_DACSTATUS_RSRVD1)
+#define BM_TVENC_DACSTATUS_RSRVD2	0x00001000
+#define BM_TVENC_DACSTATUS_RSRVD3	0x00000800
+#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS	0x00000400
+#define BM_TVENC_DACSTATUS_RSRVD4	0x00000200
+#define BM_TVENC_DACSTATUS_RSRVD5	0x00000100
+#define BM_TVENC_DACSTATUS_JACK1_GROUNDED	0x00000080
+#define BM_TVENC_DACSTATUS_RSRVD6	0x00000040
+#define BM_TVENC_DACSTATUS_RSRVD7	0x00000020
+#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ	0x00000010
+#define BM_TVENC_DACSTATUS_RSRVD8	0x00000008
+#define BM_TVENC_DACSTATUS_RSRVD9	0x00000004
+#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ	0x00000002
+#define BM_TVENC_DACSTATUS_ENIRQ_JACK	0x00000001
+
+#define HW_TVENC_VDACTEST	(0x000001c0)
+#define HW_TVENC_VDACTEST_SET	(0x000001c4)
+#define HW_TVENC_VDACTEST_CLR	(0x000001c8)
+#define HW_TVENC_VDACTEST_TOG	(0x000001cc)
+
+#define BP_TVENC_VDACTEST_RSRVD1	14
+#define BM_TVENC_VDACTEST_RSRVD1	0xFFFFC000
+#define BF_TVENC_VDACTEST_RSRVD1(v) \
+		(((v) << 14) & BM_TVENC_VDACTEST_RSRVD1)
+#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN	0x00002000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT	0x00001000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP	0x00000800
+#define BM_TVENC_VDACTEST_TEST_FIFO_FULL	0x00000400
+#define BP_TVENC_VDACTEST_DATA	0
+#define BM_TVENC_VDACTEST_DATA	0x000003FF
+#define BF_TVENC_VDACTEST_DATA(v)  \
+		(((v) << 0) & BM_TVENC_VDACTEST_DATA)
+
+#define HW_TVENC_VERSION	(0x000001d0)
+
+#define BP_TVENC_VERSION_MAJOR	24
+#define BM_TVENC_VERSION_MAJOR	0xFF000000
+#define BF_TVENC_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_TVENC_VERSION_MAJOR)
+#define BP_TVENC_VERSION_MINOR	16
+#define BM_TVENC_VERSION_MINOR	0x00FF0000
+#define BF_TVENC_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_TVENC_VERSION_MINOR)
+#define BP_TVENC_VERSION_STEP	0
+#define BM_TVENC_VERSION_STEP	0x0000FFFF
+#define BF_TVENC_VERSION_STEP(v)  \
+		(((v) << 0) & BM_TVENC_VERSION_STEP)
+#endif /* __ARCH_ARM___TVENC_H */
diff --git a/drivers/video/mxs/tvenc.c b/drivers/video/mxs/tvenc.c
new file mode 100644
index 000000000000..7aaa1fd013b0
--- /dev/null
+++ b/drivers/video/mxs/tvenc.c
@@ -0,0 +1,279 @@
+/*
+ * Freescale STMP378X dvi panel initialization
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <mach/regs-lcdif.h>
+#include <mach/regs-lradc.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-apbh.h>
+#include <mach/gpio.h>
+#include <mach/lcdif.h>
+#include "regs-tvenc.h"
+
+enum {
+	TVENC_MODE_OFF = 0,
+	TVENC_MODE_NTSC,
+	TVENC_MODE_PAL,
+};
+
+#define REGS_TVENC_BASE (IO_ADDRESS(TVENC_PHYS_ADDR))
+
+/* NTSC 720x480 mode */
+#define NTSC_X_RES	720
+#define NTSC_Y_RES	480
+#define NTSC_H_BLANKING	262
+#define NTSC_V_LINES	525
+
+/* PAL 720x576 mode */
+#define PAL_X_RES	720
+#define PAL_Y_RES	576
+#define PAL_H_BLANKING	274
+#define PAL_V_LINES	625
+
+/* frame size */
+#define DVI_H_BLANKING(m)	(m == TVENC_MODE_NTSC ? \
+				      NTSC_H_BLANKING : PAL_H_BLANKING)
+#define DVI_V_LINES(m)		(m == TVENC_MODE_NTSC ? \
+				      NTSC_V_LINES : PAL_V_LINES)
+#define DVI_H_ACTIVE(m)		(m == TVENC_MODE_NTSC ? NTSC_X_RES : PAL_X_RES)
+#define DVI_V_ACTIVE(m)		(m == TVENC_MODE_NTSC ? NTSC_Y_RES : PAL_Y_RES)
+/* fileds range */
+#define DVI_F1_START(m)		1
+#define DVI_F1_END(m)		(DVI_V_LINES(m) / 2)
+#define DVI_F2_START(m)		(DVI_F1_END(m) + 1)
+#define DVI_F2_END(m)		DVI_V_LINES(m)
+/* blanking range */
+#define DVI_V1_BLANK_START(m)	DVI_F1_END(m)
+#define DVI_V1_BLANK_END(m)	(DVI_V1_BLANK_START(m) + \
+				 (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2)
+#define DVI_V2_BLANK_START(m)	DVI_F2_END(m)
+#define DVI_V2_BLANK_END(m)	((DVI_V2_BLANK_START(m) + \
+				 (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2 - 1) % \
+				 DVI_V_LINES(m))
+
+static struct clk *lcd_clk;
+static struct clk *clk_tv108M_ng;
+static struct clk *clk_tv27M;
+
+static int tvenc_mode;
+
+static void init_tvenc_hw(int mode)
+{
+	/* Reset module */
+	__raw_writel(BM_TVENC_CTRL_SFTRST, REGS_TVENC_BASE + HW_TVENC_CTRL_SET);
+	udelay(10);
+
+	/* Take module out of reset */
+	__raw_writel(BM_TVENC_CTRL_SFTRST | BM_TVENC_CTRL_CLKGATE,
+			REGS_TVENC_BASE + HW_TVENC_CTRL_CLR);
+
+	if (mode == TVENC_MODE_NTSC) {
+		/* Config NTSC-M mode, 8-bit Y/C in, SYNC out */
+		__raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+				BM_TVENC_CONFIG_PAL_SHAPE |
+				BM_TVENC_CONFIG_YGAIN_SEL |
+				BM_TVENC_CONFIG_CGAIN,
+				REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+		__raw_writel(BM_TVENC_CONFIG_FSYNC_PHS |
+			      BF_TVENC_CONFIG_SYNC_MODE(0x4),
+			      REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+		/* 859 pixels/line for NTSC */
+		__raw_writel(857, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+		__raw_writel(0x21F07C1F, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+		__raw_writel(BM_TVENC_COLORBURST_NBA |
+				BM_TVENC_COLORBURST_PBA,
+				REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+		__raw_writel(BF_TVENC_COLORBURST_NBA(0xc8) |
+			      BF_TVENC_COLORBURST_PBA(0x0),
+			      REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+	} else if (mode == TVENC_MODE_PAL) {
+		/* Config PAL-B mode, 8-bit Y/C in, SYNC out */
+		__raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+				BM_TVENC_CONFIG_ENCD_MODE |
+				BM_TVENC_CONFIG_YGAIN_SEL |
+				BM_TVENC_CONFIG_CGAIN |
+				BM_TVENC_CONFIG_FSYNC_PHS,
+				REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+		__raw_writel(BM_TVENC_CONFIG_PAL_SHAPE |
+			      BF_TVENC_CONFIG_YGAIN_SEL(0x1)
+			      | BF_TVENC_CONFIG_CGAIN(0x1)
+			      | BF_TVENC_CONFIG_ENCD_MODE(0x1)
+			      | BF_TVENC_CONFIG_SYNC_MODE(0x4),
+			      REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+		/* 863 pixels/line for PAL */
+		__raw_writel(863, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+		__raw_writel(0x2A098ACB, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+		__raw_writel(BM_TVENC_COLORBURST_NBA |
+				BM_TVENC_COLORBURST_PBA,
+				REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+		__raw_writel(BF_TVENC_COLORBURST_NBA(0xd6) |
+			      BF_TVENC_COLORBURST_PBA(0x2a),
+			      REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+	}
+
+	/* Power up DAC */
+	__raw_writel(BM_TVENC_DACCTRL_GAINDN |
+		     BM_TVENC_DACCTRL_GAINUP |
+		     BM_TVENC_DACCTRL_PWRUP1 |
+		     BM_TVENC_DACCTRL_DUMP_TOVDD1 |
+		     BF_TVENC_DACCTRL_RVAL(0x3),
+		     REGS_TVENC_BASE + HW_TVENC_DACCTRL);
+
+	/* set all to zero is a requirement for NTSC */
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION0);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION1);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION2);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION3);
+	__raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION4);
+}
+
+static int init_panel(struct device *dev, dma_addr_t phys, int memsize,
+		      struct mxs_platform_fb_entry *pentry)
+{
+	int ret = 0;
+
+	lcd_clk = clk_get(dev, "lcdif");
+	clk_enable(lcd_clk);
+	clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns);/* kHz */
+
+	clk_tv108M_ng = clk_get(NULL, "tv108M_ng");
+	clk_tv27M = clk_get(NULL, "tv27M");
+	clk_enable(clk_tv108M_ng);
+	clk_enable(clk_tv27M);
+
+	tvenc_mode = pentry->x_res == NTSC_Y_RES ? TVENC_MODE_NTSC :
+	    TVENC_MODE_PAL;
+
+	init_tvenc_hw(tvenc_mode);
+
+	setup_dvi_panel(DVI_H_ACTIVE(tvenc_mode), DVI_V_ACTIVE(tvenc_mode),
+			DVI_H_BLANKING(tvenc_mode), DVI_V_LINES(tvenc_mode),
+			DVI_V1_BLANK_START(tvenc_mode),
+			DVI_V1_BLANK_END(tvenc_mode),
+			DVI_V2_BLANK_START(tvenc_mode),
+			DVI_V2_BLANK_END(tvenc_mode),
+			DVI_F1_START(tvenc_mode), DVI_F1_END(tvenc_mode),
+			DVI_F2_START(tvenc_mode), DVI_F2_END(tvenc_mode));
+
+	ret = mxs_lcdif_dma_init(dev, phys, memsize);
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry);
+
+	return ret;
+}
+
+static void release_panel(struct device *dev,
+			  struct mxs_platform_fb_entry *pentry)
+{
+	mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry);
+	release_dvi_panel();
+
+	mxs_lcdif_dma_release();
+
+	clk_disable(clk_tv108M_ng);
+	clk_disable(clk_tv27M);
+	clk_disable(lcd_clk);
+	clk_put(clk_tv108M_ng);
+	clk_put(clk_tv27M);
+	clk_put(lcd_clk);
+}
+
+static int blank_panel(int blank)
+{
+	int ret = 0, count;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+				REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+		/* Wait until current transfer is complete, max 30ms */
+		for (count = 30000; count > 0; count--) {
+			if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
+			    BM_LCDIF_STAT_TXFIFO_EMPTY)
+				break;
+			udelay(1);
+		}
+		break;
+
+	case FB_BLANK_UNBLANK:
+		__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+			      REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct mxs_platform_fb_entry ntsc_fb_entry = {
+	.name = "tvenc_ntsc",
+	/* x/y swapped */
+	.x_res = NTSC_Y_RES,
+	.y_res = NTSC_X_RES,
+	.bpp = 32,
+	/* the pix_clk should be near 27Mhz for proper syncronization */
+	.cycle_time_ns = 37,
+	.lcd_type = MXS_LCD_PANEL_DVI,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.pan_display = mxs_lcdif_pan_display,
+};
+
+static struct mxs_platform_fb_entry pal_fb_entry = {
+	.name = "tvenc_pal",
+	/* x/y swapped */
+	.x_res = PAL_Y_RES,
+	.y_res = PAL_X_RES,
+	.bpp = 32,
+	/* the pix_clk should be near 27Mhz for proper syncronization */
+	.cycle_time_ns = 37,
+	.lcd_type = MXS_LCD_PANEL_DVI,
+	.init_panel = init_panel,
+	.release_panel = release_panel,
+	.blank_panel = blank_panel,
+	.run_panel = mxs_lcdif_run,
+	.pan_display = mxs_lcdif_pan_display,
+};
+
+static int __init register_devices(void)
+{
+	struct platform_device *pdev;
+	pdev = mxs_get_device("mxs-fb", 0);
+	if (pdev == NULL || IS_ERR(pdev))
+		return -ENODEV;
+
+	mxs_lcd_register_entry(&ntsc_fb_entry, pdev->dev.platform_data);
+	mxs_lcd_register_entry(&pal_fb_entry, pdev->dev.platform_data);
+	return 0;
+}
+
+subsys_initcall(register_devices);
diff --git a/drivers/video/stmp37xxfb.c b/drivers/video/stmp37xxfb.c
new file mode 100644
index 000000000000..32d3b9c06577
--- /dev/null
+++ b/drivers/video/stmp37xxfb.c
@@ -0,0 +1,964 @@
+/*
+ * Freescale STMP37XX/STMP378X framebuffer driver
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-pinctrl.h>
+#include <mach/regs-lcdif.h>
+#include <mach/regs-clkctrl.h>
+#include <mach/regs-apbh.h>
+#include <mach/lcdif.h>
+
+#include <mach/stmp3xxx.h>
+
+#define NUM_SCREENS	1
+
+enum {
+	F_DISABLE = 0,
+	F_ENABLE,
+	F_REENABLE,
+};
+
+struct stmp3xxx_fb_data {
+	struct fb_info info;
+	struct stmp3xxx_platform_fb_data *pdata;
+	struct work_struct work;
+	struct mutex blank_mutex;
+	u32 state;
+	u32 task_state;
+	ssize_t mem_size;
+	ssize_t map_size;
+	dma_addr_t phys_start;
+	dma_addr_t cur_phys;
+	int dma_irq;
+	int err_irq;
+	void *virt_start;
+	struct device *dev;
+	wait_queue_head_t vsync_wait_q;
+	u32 vsync_count;
+	void *par;
+};
+
+/* forward declaration */
+static int stmp3xxxfb_blank(int blank, struct fb_info *info);
+static unsigned char *default_panel_name;
+static struct stmp3xxx_fb_data *cdata;
+static void init_timings(struct stmp3xxx_fb_data *data);
+
+static void stmp3xxxfb_enable_controller(struct stmp3xxx_fb_data *data)
+{
+	struct stmp3xxx_platform_fb_entry *pentry = data->pdata->cur;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return;
+
+	stmp3xxx_init_lcdif();
+	init_timings(data);
+	pentry->init_panel(data->dev, data->phys_start,
+			data->info.fix.smem_len, data->pdata->cur);
+	pentry->run_panel();
+
+	if (pentry->blank_panel)
+		pentry->blank_panel(FB_BLANK_UNBLANK);
+}
+
+static void stmp3xxxfb_disable_controller(struct stmp3xxx_fb_data *data)
+{
+	struct stmp3xxx_platform_fb_entry *pentry = data->pdata->cur;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return;
+
+	if (pentry->blank_panel)
+		pentry->blank_panel(FB_BLANK_POWERDOWN);
+
+	if (pentry->stop_panel)
+		pentry->stop_panel();
+	pentry->release_panel(data->dev, pentry);
+}
+
+static void set_controller_state(struct stmp3xxx_fb_data *data, u32 state)
+{
+	struct stmp3xxx_platform_fb_entry *pentry = data->pdata->cur;
+	struct fb_info *info = &data->info;
+	u32 old_state;
+
+	mutex_lock(&data->blank_mutex);
+	old_state = data->state;
+	pr_debug("%s, old_state %d, state %d\n", __func__, old_state, state);
+
+	switch (state) {
+	case F_DISABLE:
+		/*
+		 * Disable controller
+		 */
+		if (old_state != F_DISABLE) {
+			data->state = F_DISABLE;
+			stmp3xxxfb_disable_controller(data);
+		}
+		break;
+
+	case F_REENABLE:
+		/*
+		 * Re-enable the controller when panel changed.
+		 */
+		if (old_state == F_ENABLE) {
+			stmp3xxxfb_disable_controller(data);
+
+			pentry = data->pdata->cur = data->pdata->next;
+			info->fix.smem_len = pentry->y_res * pentry->x_res *
+						pentry->bpp / 8;
+			info->screen_size = info->fix.smem_len;
+			memset((void *)info->screen_base, 0, info->screen_size);
+
+			stmp3xxxfb_enable_controller(data);
+
+			data->state = F_ENABLE;
+		} else if (old_state == F_DISABLE) {
+			pentry = data->pdata->cur = data->pdata->next;
+			info->fix.smem_len = pentry->y_res * pentry->x_res *
+						pentry->bpp / 8;
+			info->screen_size = info->fix.smem_len;
+			memset((void *)info->screen_base, 0, info->screen_size);
+
+			data->state = F_DISABLE;
+		}
+		break;
+
+	case F_ENABLE:
+		if (old_state != F_ENABLE) {
+			data->state = F_ENABLE;
+			stmp3xxxfb_enable_controller(data);
+		}
+		break;
+	}
+	mutex_unlock(&data->blank_mutex);
+
+}
+
+static void stmp3xxxfb_task(struct work_struct *work)
+{
+	struct stmp3xxx_fb_data *data =
+			container_of(work, struct stmp3xxx_fb_data, work);
+
+	u32 state = xchg(&data->task_state, -1);
+	pr_debug("%s: state = %d, data->task_state = %d\n",
+				__func__, state, data->task_state);
+
+	set_controller_state(data, state);
+}
+
+static void stmp3xxx_schedule_work(struct stmp3xxx_fb_data *data, u32 state)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	data->task_state = state;
+	schedule_work(&data->work);
+
+	local_irq_restore(flags);
+}
+
+static irqreturn_t lcd_irq_handler(int irq, void *dev_id)
+{
+	struct stmp3xxx_fb_data *data = dev_id;
+	u32 status_lcd = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CTRL1);
+	u32 status_apbh = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1);
+	pr_debug("%s: irq %d\n", __func__, irq);
+
+	if (status_apbh & BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ)
+		__raw_writel(BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ,
+			REGS_APBH_BASE + HW_APBH_CTRL1_CLR);
+
+	if (status_lcd & BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ) {
+		pr_debug("%s: VSYNC irq\n", __func__);
+		data->vsync_count++;
+		__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ,
+			REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+		wake_up_interruptible(&data->vsync_wait_q);
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+		pr_debug("%s: frame done irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+			REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+		data->vsync_count++;
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_UNDERFLOW_IRQ) {
+		pr_debug("%s: underflow irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_UNDERFLOW_IRQ,
+			REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	}
+	if (status_lcd & BM_LCDIF_CTRL1_OVERFLOW_IRQ) {
+		pr_debug("%s: overflow irq\n", __func__);
+		__raw_writel(BM_LCDIF_CTRL1_OVERFLOW_IRQ,
+			REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	}
+	return IRQ_HANDLED;
+}
+
+static struct fb_var_screeninfo stmp3xxxfb_default __devinitdata = {
+	.activate =	FB_ACTIVATE_TEST,
+	.height =	-1,
+	.width =	-1,
+	.pixclock =	20000,
+	.left_margin =	64,
+	.right_margin =	64,
+	.upper_margin =	32,
+	.lower_margin =	32,
+	.hsync_len =	64,
+	.vsync_len =	2,
+	.vmode =	FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo stmp3xxxfb_fix __devinitdata = {
+	.id =		"stmp3xxxfb",
+	.type =		FB_TYPE_PACKED_PIXELS,
+	.visual =       FB_VISUAL_TRUECOLOR,
+	.xpanstep =	0,
+	.ypanstep =	0,
+	.ywrapstep =	0,
+	.accel =	FB_ACCEL_NONE,
+};
+
+int stmp3xxxfb_get_info(struct fb_var_screeninfo *var,
+			struct fb_fix_screeninfo *fix)
+{
+	if (!cdata)
+		return -ENODEV;
+
+	*var = cdata->info.var;
+	*fix = cdata->info.fix;
+	return 0;
+}
+
+void stmp3xxxfb_cfg_pxp(int enable, dma_addr_t pxp_phys)
+{
+	if (enable)
+		cdata->pdata->cur->pan_display(pxp_phys);
+	else
+		cdata->pdata->cur->pan_display(cdata->cur_phys);
+}
+
+static int stmp3xxxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+
+	unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
+
+	if (off < info->fix.smem_len)
+		return dma_mmap_writecombine(data->dev, vma,
+				data->virt_start,
+				data->phys_start,
+				info->fix.smem_len);
+	else
+		return -EINVAL;
+}
+
+static int stmp3xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			 u_int transp, struct fb_info *info)
+{
+	if (regno >= 256)	/* no. of hw registers */
+		return 1;
+	/*
+	* Program hardware... do anything you want with transp
+	*/
+
+	/* grayscale works only partially under directcolor */
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue =
+		    (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+	/* Directcolor:
+	 *   var->{color}.offset contains start of bitfield
+	 *   var->{color}.length contains length of bitfield
+	 *   {hardwarespecific} contains width of RAMDAC
+	 *   cmap[X] is programmed to
+	 *	(X << red.offset) | (X << green.offset) | (X << blue.offset)
+	 *   RAMDAC[X] is programmed to (red, green, blue)
+	 *
+	 * Pseudocolor:
+	 *    uses offset = 0 && length = RAMDAC register width.
+	 *    var->{color}.offset is 0
+	 *    var->{color}.length contains widht of DAC
+	 *    cmap is not used
+	 *    RAMDAC[X] is programmed to (red, green, blue)
+	 * Truecolor:
+	 *    does not use DAC. Usually 3 are present.
+	 *    var->{color}.offset contains start of bitfield
+	 *    var->{color}.length contains length of bitfield
+	 *    cmap is programmed to
+	 *	(red << red.offset) | (green << green.offset) |
+	 *	(blue << blue.offset) | (transp << transp.offset)
+	 *    RAMDAC does not exist
+	 */
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		red = CNVT_TOHW(red, info->var.red.length);
+		green = CNVT_TOHW(green, info->var.green.length);
+		blue = CNVT_TOHW(blue, info->var.blue.length);
+		transp = CNVT_TOHW(transp, info->var.transp.length);
+		break;
+	case FB_VISUAL_DIRECTCOLOR:
+		red = CNVT_TOHW(red, 8);	/* expect 8 bit DAC */
+		green = CNVT_TOHW(green, 8);
+		blue = CNVT_TOHW(blue, 8);
+		/* hey, there is bug in transp handling... */
+		transp = CNVT_TOHW(transp, 8);
+		break;
+	}
+#undef CNVT_TOHW
+	/* Truecolor has hardware independent palette */
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+		if (regno >= 16)
+			return 1;
+
+		((u32 *) (info->pseudo_palette))[regno] =
+				(red << info->var.red.offset) |
+				(green << info->var.green.offset) |
+				(blue << info->var.blue.offset) |
+				(transp << info->var.transp.offset);
+	}
+	return 0;
+}
+
+static inline u_long get_line_length(int xres_virtual, int bpp)
+{
+	u_long length;
+
+	length = xres_virtual * bpp;
+	length = (length + 31) & ~31;
+	length >>= 3;
+	return length;
+}
+
+static int get_matching_pentry(struct stmp3xxx_platform_fb_entry *pentry,
+			       void *data, int ret_prev)
+{
+	struct fb_var_screeninfo *info = data;
+	pr_debug("%s: %d:%d:%d vs %d:%d:%d\n", __func__,
+		pentry->x_res, pentry->y_res, pentry->bpp,
+		info->yres, info->xres, info->bits_per_pixel);
+	if (pentry->x_res == info->yres && pentry->y_res == info->xres &&
+	    pentry->bpp == info->bits_per_pixel)
+		ret_prev = (int)pentry;
+	return ret_prev;
+}
+
+static int get_matching_pentry_by_name(
+		struct stmp3xxx_platform_fb_entry *pentry,
+		void *data,
+		int ret_prev)
+{
+	unsigned char *name = data;
+	if (!strcmp(pentry->name, name))
+		ret_prev = (int)pentry;
+	return ret_prev;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ * XXX: REVISIT
+ */
+static int stmp3xxxfb_set_par(struct fb_info *info)
+{
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+	struct stmp3xxx_platform_fb_data *pdata = data->pdata;
+	struct stmp3xxx_platform_fb_entry *pentry;
+	pentry = (void *)stmp3xxx_lcd_iterate_pdata(pdata,
+						get_matching_pentry,
+						&info->var);
+
+	dev_dbg(data->dev, "%s: xres %d, yres %d, bpp %d\n",
+		__func__,
+		info->var.xres,
+		info->var.yres,
+		info->var.bits_per_pixel);
+	if (!pentry)
+		return -EINVAL;
+
+	info->fix.line_length = get_line_length(info->var.xres_virtual,
+						info->var.bits_per_pixel);
+
+	if (pentry == pdata->cur || !pdata->cur)
+		return 0;
+
+	/* init next panel */
+	pdata->next = pentry;
+
+	set_controller_state(data, F_REENABLE);
+
+	return 0;
+}
+
+static int stmp3xxxfb_check_var(struct fb_var_screeninfo *var,
+				struct fb_info *info)
+{
+	u32 line_length;
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+	struct stmp3xxx_platform_fb_data *pdata = data->pdata;
+
+	/*
+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
+	 */
+
+	if (var->vmode & FB_VMODE_CONUPDATE) {
+		var->vmode |= FB_VMODE_YWRAP;
+		var->xoffset = info->var.xoffset;
+		var->yoffset = info->var.yoffset;
+	}
+
+	pr_debug("%s: xres %d, yres %d, bpp %d\n", __func__,
+		var->xres,  var->yres, var->bits_per_pixel);
+	/*
+	 *  Some very basic checks
+	 */
+	if (!var->xres)
+		var->xres = 1;
+	if (!var->yres)
+		var->yres = 1;
+	if (var->xres > var->xres_virtual)
+		var->xres_virtual = var->xres;
+	if (var->yres > var->yres_virtual)
+		var->yres_virtual = var->yres;
+
+	if (var->xres_virtual < var->xoffset + var->xres)
+		var->xres_virtual = var->xoffset + var->xres;
+	if (var->yres_virtual < var->yoffset + var->yres)
+		var->yres_virtual = var->yoffset + var->yres;
+
+	line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
+	dev_dbg(data->dev,
+		"line_length %d, var->yres_virtual %d, data->mem_size %d\n",
+		line_length, var->yres_virtual, data->mem_size);
+	if (line_length * var->yres_virtual > data->map_size)
+		return -ENOMEM;
+
+	if (!stmp3xxx_lcd_iterate_pdata(pdata, get_matching_pentry, var))
+		return -EINVAL;
+
+	if (var->bits_per_pixel == 16) {
+		/* RGBA 5551 */
+		if (var->transp.length) {
+			var->red.offset = 0;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 5;
+			var->blue.offset = 10;
+			var->blue.length = 5;
+			var->transp.offset = 15;
+			var->transp.length = 1;
+		} else {	/* RGB 565 */
+			var->red.offset = 0;
+			var->red.length = 5;
+			var->green.offset = 5;
+			var->green.length = 6;
+			var->blue.offset = 11;
+			var->blue.length = 5;
+			var->transp.offset = 0;
+			var->transp.length = 0;
+		}
+	} else {
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+	}
+
+	var->red.msb_right = 0;
+	var->green.msb_right = 0;
+	var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+
+	return 0;
+}
+
+
+static int stmp3xxxfb_wait_for_vsync(u32 channel, struct fb_info *info)
+{
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+	u32 count = data->vsync_count;
+	int ret = 0;
+
+	__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+	ret = wait_event_interruptible_timeout(data->vsync_wait_q,
+			count != data->vsync_count, HZ / 10);
+	__raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+		REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+	if (!ret) {
+		dev_err(data->dev, "wait for vsync timed out\n");
+		ret = -ETIMEDOUT;
+	}
+	return ret;
+}
+
+static int stmp3xxxfb_ioctl(struct fb_info *info, unsigned int cmd,
+			unsigned long arg)
+{
+	u32 channel = 0;
+	int ret = -EINVAL;
+
+	switch (cmd) {
+	case FBIO_WAITFORVSYNC:
+		if (!get_user(channel, (__u32 __user *) arg))
+			ret = stmp3xxxfb_wait_for_vsync(channel, info);
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int stmp3xxxfb_blank(int blank, struct fb_info *info)
+{
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+	int ret = 0;
+
+	switch (blank) {
+	case FB_BLANK_NORMAL:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_POWERDOWN:
+		pr_debug("%s: FB_BLANK_POWERDOWN\n", __func__);
+		stmp3xxx_schedule_work(data, F_DISABLE);
+		break;
+
+	case FB_BLANK_UNBLANK:
+		pr_debug("%s: FB_BLANK_UNBLANK\n", __func__);
+		stmp3xxx_schedule_work(data, F_ENABLE);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static int stmp3xxxfb_pan_display(struct fb_var_screeninfo *var,
+				struct fb_info *info)
+{
+	struct stmp3xxx_fb_data *data = (struct stmp3xxx_fb_data *)info;
+	int ret = 0;
+
+	pr_debug("%s: var->xoffset %d, info->var.xoffset %d\n",
+		__func__, var->xoffset, info->var.xoffset);
+	/* check if var is valid; also, xpan is not supported */
+	if (!var || (var->xoffset != info->var.xoffset) ||
+	    (var->yoffset + var->yres > var->yres_virtual)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!data->pdata->cur->pan_display) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* update framebuffer visual */
+	data->cur_phys = data->phys_start +
+			info->fix.line_length * var->yoffset;
+	data->pdata->cur->pan_display(data->cur_phys);
+out:
+	return ret;
+}
+
+static struct fb_ops stmp3xxxfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = stmp3xxxfb_check_var,
+	.fb_set_par = stmp3xxxfb_set_par,
+	.fb_mmap = stmp3xxxfb_mmap,
+	.fb_setcolreg = stmp3xxxfb_setcolreg,
+	.fb_ioctl = stmp3xxxfb_ioctl,
+	.fb_blank = stmp3xxxfb_blank,
+	.fb_pan_display = stmp3xxxfb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static void init_timings(struct stmp3xxx_fb_data *data)
+{
+	unsigned phase_time;
+	unsigned timings;
+
+	/* Just use a phase_time of 1. As optimal as it gets, now. */
+	phase_time = 1;
+
+	/* Program all 4 timings the same */
+	timings = phase_time;
+	timings |= timings << 8;
+	timings |= timings << 16;
+	__raw_writel(timings, REGS_LCDIF_BASE + HW_LCDIF_TIMING);
+}
+
+#ifdef CONFIG_CPU_FREQ
+
+struct stmp3xxxfb_notifier_block {
+	struct stmp3xxx_fb_data *fb_data;
+	struct notifier_block nb;
+};
+
+static int stmp3xxxfb_notifier(struct notifier_block *self,
+				unsigned long phase, void *p)
+{
+	struct stmp3xxxfb_notifier_block *block =
+		container_of(self, struct stmp3xxxfb_notifier_block, nb);
+	struct stmp3xxx_fb_data *data = block->fb_data;
+	struct stmp3xxx_platform_fb_entry *pentry = data->pdata->cur;
+	u32 old_state = data->state;
+
+	if (!data || !data->pdata || !data->pdata->cur)
+		return NOTIFY_BAD;
+
+	/* REVISIT */
+	switch (phase) {
+	case CPUFREQ_PRECHANGE:
+		if (old_state == F_ENABLE)
+			if (pentry->blank_panel)
+				pentry->blank_panel(FB_BLANK_POWERDOWN);
+		break;
+
+	case CPUFREQ_POSTCHANGE:
+		if (old_state == F_ENABLE)
+			if (pentry->blank_panel)
+				pentry->blank_panel(FB_BLANK_UNBLANK);
+		break;
+
+	default:
+		dev_dbg(data->dev, "didn't handle notify %ld\n", phase);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct stmp3xxxfb_notifier_block stmp3xxxfb_nb = {
+	.nb = {
+		.notifier_call = stmp3xxxfb_notifier,
+	},
+};
+#endif /* CONFIG_CPU_FREQ */
+
+static int get_max_memsize(struct stmp3xxx_platform_fb_entry *pentry,
+			   void *data, int ret_prev)
+{
+	struct stmp3xxx_fb_data *fbdata = data;
+	int sz = pentry->x_res * pentry->y_res * pentry->bpp / 8;
+	fbdata->mem_size = sz < ret_prev ? ret_prev : sz;
+	pr_debug("%s: mem_size now %d\n", __func__, fbdata->mem_size);
+	return fbdata->mem_size;
+}
+
+static int __devinit stmp3xxxfb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct stmp3xxx_fb_data *data;
+	struct resource *res;
+	struct fb_info *info;
+	struct stmp3xxx_platform_fb_data *pdata = pdev->dev.platform_data;
+	struct stmp3xxx_platform_fb_entry *pentry;
+
+	if (pdata == NULL) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (default_panel_name) {
+		pentry = (void *)stmp3xxx_lcd_iterate_pdata(pdata,
+					get_matching_pentry_by_name,
+					default_panel_name);
+		if (pentry) {
+			stmp3xxx_lcd_move_pentry_up(pentry, pdata);
+			pdata->cur = pentry;
+		}
+	}
+	if (!default_panel_name || !pentry)
+		pentry = pdata->cur;
+	if (!pentry || !pentry->init_panel || !pentry->run_panel ||
+	    !pentry->release_panel) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	data = (struct stmp3xxx_fb_data *)framebuffer_alloc(
+				sizeof(struct stmp3xxx_fb_data) +
+				sizeof(u32) * 256 -
+				sizeof(struct fb_info), &pdev->dev);
+	if (data == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	cdata = data;
+	data->dev = &pdev->dev;
+	data->pdata = pdata;
+	platform_set_drvdata(pdev, data);
+	info = &data->info;
+
+	dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", pentry->x_res,
+		pentry->y_res, pentry->bpp);
+
+	stmp3xxx_lcd_iterate_pdata(pdata, get_max_memsize, data);
+
+	data->map_size = PAGE_ALIGN(data->mem_size) * NUM_SCREENS;
+	dev_dbg(&pdev->dev, "memory to allocate: %d\n", data->map_size);
+
+	data->virt_start = dma_alloc_writecombine(&pdev->dev,
+					data->map_size,
+					&data->phys_start,
+					GFP_KERNEL);
+
+	if (data->virt_start == NULL) {
+		ret = -ENOMEM;
+		goto out_dma;
+	}
+	dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", data->virt_start,
+		data->phys_start);
+	mutex_init(&data->blank_mutex);
+	INIT_WORK(&data->work, stmp3xxxfb_task);
+	data->state = F_ENABLE;
+
+	stmp3xxxfb_default.bits_per_pixel = pentry->bpp;
+	/* NB: rotated */
+	stmp3xxxfb_default.xres = pentry->y_res;
+	stmp3xxxfb_default.yres = pentry->x_res;
+	stmp3xxxfb_default.xres_virtual = pentry->y_res;
+	stmp3xxxfb_default.yres_virtual = data->map_size /
+					(pentry->y_res * pentry->bpp / 8);
+	if (stmp3xxxfb_default.yres_virtual >= stmp3xxxfb_default.yres * 2)
+		stmp3xxxfb_default.yres_virtual = stmp3xxxfb_default.yres * 2;
+	else
+		stmp3xxxfb_default.yres_virtual = stmp3xxxfb_default.yres;
+
+	stmp3xxxfb_fix.smem_start = data->phys_start;
+	stmp3xxxfb_fix.smem_len = pentry->y_res * pentry->x_res * pentry->bpp /
+		8;
+	stmp3xxxfb_fix.ypanstep = 1;
+
+	switch (pentry->bpp) {
+	case 32:
+	case 24:
+		stmp3xxxfb_default.red.offset = 16;
+		stmp3xxxfb_default.red.length = 8;
+		stmp3xxxfb_default.green.offset = 8;
+		stmp3xxxfb_default.green.length = 8;
+		stmp3xxxfb_default.blue.offset = 0;
+		stmp3xxxfb_default.blue.length = 8;
+		break;
+
+	case 16:
+		stmp3xxxfb_default.red.offset = 11;
+		stmp3xxxfb_default.red.length = 5;
+		stmp3xxxfb_default.green.offset = 5;
+		stmp3xxxfb_default.green.length = 6;
+		stmp3xxxfb_default.blue.offset = 0;
+		stmp3xxxfb_default.blue.length = 5;
+		break;
+
+	default:
+		dev_err(&pdev->dev, "unsupported bitwidth %d\n", pentry->bpp);
+		ret = -EINVAL;
+		goto out_dma;
+	}
+
+	info->screen_base = data->virt_start;
+	info->fbops = &stmp3xxxfb_ops;
+	info->var = stmp3xxxfb_default;
+	info->fix = stmp3xxxfb_fix;
+	info->pseudo_palette = &data->par;
+	data->par = NULL;
+	info->flags = FBINFO_FLAG_DEFAULT;
+
+	init_waitqueue_head(&data->vsync_wait_q);
+	data->vsync_count = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma;
+	}
+	data->dma_irq = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot get IRQ resource\n");
+		ret = -ENODEV;
+		goto out_dma;
+	}
+	data->err_irq = res->start;
+
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret)
+		goto out_cmap;
+
+	stmp3xxx_init_lcdif();
+	ret = pentry->init_panel(data->dev, data->phys_start,
+				stmp3xxxfb_fix.smem_len, pentry);
+	if (ret) {
+		dev_err(&pdev->dev, "cannot initialize LCD panel\n");
+		goto out_panel;
+	}
+	dev_dbg(&pdev->dev, "LCD panel initialized\n");
+	init_timings(data);
+
+	ret = request_irq(data->dma_irq, lcd_irq_handler, 0, "fb_dma", data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+				data->dma_irq, ret);
+		goto out_panel;
+	}
+	ret = request_irq(data->err_irq, lcd_irq_handler, 0, "fb_error", data);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+				data->err_irq, ret);
+		goto out_irq;
+	}
+	ret = register_framebuffer(info);
+	if (ret)
+		goto out_register;
+
+	pentry->run_panel();
+	dev_dbg(&pdev->dev, "LCD DMA channel has been started\n");
+	data->cur_phys = data->phys_start;
+	dev_dbg(&pdev->dev, "LCD running now\n");
+
+#ifdef CONFIG_CPU_FREQ
+	stmp3xxxfb_nb.fb_data = data;
+	cpufreq_register_notifier(&stmp3xxxfb_nb.nb,
+				CPUFREQ_TRANSITION_NOTIFIER);
+#endif /* CONFIG_CPU_FREQ */
+
+	goto out;
+
+out_register:
+	free_irq(data->err_irq, data);
+out_irq:
+	free_irq(data->dma_irq, data);
+out_panel:
+	fb_dealloc_cmap(&info->cmap);
+out_cmap:
+	dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start,
+			data->phys_start);
+out_dma:
+	kfree(data);
+out:
+	return ret;
+}
+
+static int stmp3xxxfb_remove(struct platform_device *pdev)
+{
+	struct stmp3xxx_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_DISABLE);
+
+	unregister_framebuffer(&data->info);
+	framebuffer_release(&data->info);
+	fb_dealloc_cmap(&data->info.cmap);
+	free_irq(data->dma_irq, data);
+	free_irq(data->err_irq, data);
+	dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start,
+			data->phys_start);
+	kfree(data);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stmp3xxxfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct stmp3xxx_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_DISABLE);
+
+	return 0;
+}
+
+static int stmp3xxxfb_resume(struct platform_device *pdev)
+{
+	struct stmp3xxx_fb_data *data = platform_get_drvdata(pdev);
+
+	set_controller_state(data, F_ENABLE);
+	return 0;
+}
+#else
+#define stmp3xxxfb_suspend	NULL
+#define	stmp3xxxfb_resume	NULL
+#endif
+
+static struct platform_driver stmp3xxxfb_driver = {
+	.probe		= stmp3xxxfb_probe,
+	.remove		= stmp3xxxfb_remove,
+	.suspend	= stmp3xxxfb_suspend,
+	.resume		= stmp3xxxfb_resume,
+	.driver		= {
+		.name   = "stmp3xxx-fb",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init stmp3xxxfb_init(void)
+{
+	return platform_driver_register(&stmp3xxxfb_driver);
+}
+
+static void __exit stmp3xxxfb_exit(void)
+{
+	platform_driver_unregister(&stmp3xxxfb_driver);
+}
+
+module_init(stmp3xxxfb_init);
+module_exit(stmp3xxxfb_exit);
+
+/*
+ * LCD panel select
+ */
+static int __init default_panel_select(char *str)
+{
+	default_panel_name = str;
+	return 0;
+}
+__setup("lcd_panel=", default_panel_select);
+
+MODULE_AUTHOR("Vitaly Wool <vital@embeddedalley.com>");
+MODULE_DESCRIPTION("STMP3xxx Framebuffer Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 65244c02551b..0d51b737ea78 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <mach/hardware.h>
 
 #include "../w1.h"
 #include "../w1_int.h"
@@ -43,6 +44,8 @@
 #define MXC_W1_INTERRUPT        0x0A
 #define MXC_W1_INTERRUPT_EN     0x0C
 
+static DECLARE_COMPLETION(transmit_done);
+
 struct mxc_w1_device {
 	void __iomem *regs;
 	unsigned int clkdiv;
@@ -102,10 +105,155 @@ static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
 	return ((__raw_readb(ctrl_addr)) >> 3) & 0x1;
 }
 
+static void mxc_w1_ds2_write_byte(void *data, u8 byte)
+{
+	struct mxc_w1_device *dev = (struct mxc_w1_device *)data;
+	INIT_COMPLETION(transmit_done);
+	__raw_writeb(byte, (dev->regs + MXC_W1_TXRX));
+	__raw_writeb(0x10, (dev->regs + MXC_W1_INTERRUPT_EN));
+	wait_for_completion(&transmit_done);
+}
+static u8 mxc_w1_ds2_read_byte(void *data)
+{
+	volatile u8 reg_val;
+	struct mxc_w1_device *dev = (struct mxc_w1_device *)data;
+	mxc_w1_ds2_write_byte(data, 0xFF);
+	reg_val = __raw_readb((dev->regs + MXC_W1_TXRX));
+	return reg_val;
+}
+static u8 mxc_w1_read_byte(void *data)
+{
+	volatile u8 reg_val;
+	struct mxc_w1_device *dev = (struct mxc_w1_device *)data;
+	reg_val = __raw_readb((dev->regs + MXC_W1_TXRX));
+	return reg_val;
+}
+static irqreturn_t w1_interrupt_handler(int irq, void *data)
+{
+	u8 reg_val;
+	irqreturn_t ret = IRQ_NONE;
+	struct mxc_w1_device *dev = (struct mxc_w1_device *)data;
+	reg_val = __raw_readb((dev->regs + MXC_W1_INTERRUPT));
+	if ((reg_val & 0x10)) {
+		complete(&transmit_done);
+		reg_val = __raw_readb((dev->regs + MXC_W1_TXRX));
+		ret = IRQ_HANDLED;
+	}
+	return ret;
+}
+void search_ROM_accelerator(void *data, struct w1_master *master, u8 search_type,
+			    w1_slave_found_callback cb)
+{
+	u64 rn[2], last_rn[2], rn2[2];
+	u64 rn1, rom_id, temp, temp1;
+	int i, j, z, w, last_zero, loop;
+	u8 bit, reg_val, bit2;
+	u8 byte, byte1;
+	int disc, prev_disc, last_disc;
+	struct mxc_w1_device *dev = (struct mxc_w1_device *)data;
+	last_rn[0] = 0;
+	last_rn[1] = 0;
+	rom_id = 0;
+	prev_disc = 0;
+	loop = 0;
+	disc = -1;
+	last_disc = 0;
+	last_zero = 0;
+	while (!last_zero) {
+		/*
+		 * Reset bus and all 1-wire device state machines
+		 * so they can respond to our requests.
+		 *
+		 * Return 0 - device(s) present, 1 - no devices present.
+		 */
+		if (mxc_w1_ds2_reset_bus(data)) {
+			pr_debug("No devices present on the wire.\n");
+			break;
+		}
+		rn[0] = 0;
+		rn[1] = 0;
+		__raw_writeb(0x80, (dev->regs + MXC_W1_CONTROL));
+		mdelay(1);
+		mxc_w1_ds2_write_byte(data, 0xF0);
+		__raw_writeb(0x02, (dev->regs + MXC_W1_COMMAND));
+		memcpy(rn2, last_rn, 16);
+		z = 0;
+		w = 0;
+		for (i = 0; i < 16; i++) {
+			reg_val = rn2[z] >> (8 * w);
+			mxc_w1_ds2_write_byte(data, reg_val);
+			reg_val = mxc_w1_read_byte(data);
+			if ((reg_val & 0x3) == 0x3) {
+				pr_debug("Device is Not Responding\n");
+				break;
+			}
+			for (j = 0; j < 8; j += 2) {
+				byte = 0xFF;
+				byte1 = 1;
+				byte ^= byte1 << j;
+				bit = (reg_val >> j) & 0x1;
+				bit2 = (reg_val >> j);
+				if (bit) {
+					prev_disc = disc;
+					disc = 8 * i + j;
+					reg_val &= byte;
+				}
+			}
+			rn1 = 0;
+			rn1 = reg_val;
+			rn[z] |= rn1 << (8 * w);
+			w++;
+			if (i == 7) {
+				z++;
+				w = 0;
+			}
+		}
+		if ((disc == -1) || (disc == prev_disc))
+			last_zero = 1;
+		if (disc == last_disc)
+			disc = prev_disc;
+		z = 0;
+		rom_id = 0;
+		for (i = 0, j = 1; i < 64; i++) {
+			temp = 0;
+			temp = (rn[z] >> j) & 0x1;
+			rom_id |= (temp << i);
+			j += 2;
+			if (i == 31) {
+				z++;
+				j = 1;
+			}
+
+		}
+		if (disc > 63) {
+			last_rn[0] = rn[0];
+			temp1 = rn[1];
+			loop = disc % 64;
+			temp = 1;
+			temp1 |= (temp << (loop + 1)) - 1;
+			temp1 |= (temp << (loop + 1));
+			last_rn[1] = temp1;
+
+		} else {
+			last_rn[1] = 0;
+			temp1 = rn[0];
+			temp = 1;
+			temp1 |= (temp << (loop + 1)) - 1;
+			temp1 |= (temp << (loop + 1));
+			last_rn[0] = temp1;
+		}
+		last_disc = disc;
+		cb(master, rom_id);
+	}
+}
+
 static int __init mxc_w1_probe(struct platform_device *pdev)
 {
 	struct mxc_w1_device *mdev;
+	struct mxc_w1_config *data =
+	    (struct mxc_w1_config *)pdev->dev.platform_data;
 	struct resource *res;
+	int irq = 0;
 	int err = 0;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -143,6 +291,22 @@ static int __init mxc_w1_probe(struct platform_device *pdev)
 	mdev->bus_master.data = mdev;
 	mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
 	mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
+	if (data->search_rom_accelerator) {
+		mdev->bus_master.write_byte = &mxc_w1_ds2_write_byte;
+		mdev->bus_master.read_byte = &mxc_w1_ds2_read_byte;
+		mdev->bus_master.search = &search_ROM_accelerator;
+		irq = platform_get_irq(pdev, 0);
+		if (irq < 0) {
+			err = -ENOENT;
+			goto failed_irq; 
+		}
+		err = request_irq(irq, w1_interrupt_handler, 0, "mxc_w1", mdev);
+		if (err) {
+			pr_debug("OWire:request_irq(%d) returned error %d\n",
+				 irq, err);
+			goto failed_irq;
+		}
+	}
 
 	err = w1_add_master_device(&mdev->bus_master);
 
@@ -153,6 +317,9 @@ static int __init mxc_w1_probe(struct platform_device *pdev)
 	return 0;
 
 failed_add:
+	if (irq)
+		free_irq(irq, mdev);
+failed_irq:
 	iounmap(mdev->regs);
 failed_ioremap:
 	release_mem_region(res->start, resource_size(res));
@@ -170,6 +337,9 @@ static int mxc_w1_remove(struct platform_device *pdev)
 {
 	struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
 	struct resource *res;
+	struct mxc_w1_config *data =
+	    (struct mxc_w1_config *)pdev->dev.platform_data;
+	int irq;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
@@ -177,6 +347,11 @@ static int mxc_w1_remove(struct platform_device *pdev)
 
 	iounmap(mdev->regs);
 	release_mem_region(res->start, resource_size(res));
+
+	irq = platform_get_irq(pdev, 0);
+	if ((irq >= 0) && (data->search_rom_accelerator))
+		free_irq(irq, mdev);
+
 	clk_disable(mdev->clk);
 	clk_put(mdev->clk);
 
diff --git a/drivers/w1/slaves/Kconfig b/drivers/w1/slaves/Kconfig
index 1f51366417b9..ad77126801f5 100644
--- a/drivers/w1/slaves/Kconfig
+++ b/drivers/w1/slaves/Kconfig
@@ -22,12 +22,34 @@ config W1_SLAVE_DS2431
 	  Say Y here if you want to use a 1-wire
 	  1kb EEPROM family device (DS2431)
 
+config W1_SLAVE_DS2751
+        tristate "Battery Level sensing support (DS2751)"
+        depends on W1
+        help
+          Say Y here if you want to use a 1-wire
+          battery level sensing device (DS2751).
+
+config W1_SLAVE_DS2751_CRC
+        bool "Protect DS2751 data with a CRC16"
+        depends on W1_SLAVE_DS2751
+        select CRC16
+        help
+          Say Y here to protect DS2751 data with a CRC16.
+          Each block has 30 bytes of data and a two byte CRC16.
+          Full block writes are only allowed if the CRC is valid.
+
 config W1_SLAVE_DS2433
 	tristate "4kb EEPROM family support (DS2433)"
 	help
 	  Say Y here if you want to use a 1-wire
 	  4kb EEPROM family device (DS2433).
 
+config W1_SLAVE_DS2438
+	tristate "Smart Battery Monitor (DS2438)"
+	help
+	  Say Y here if you want to use a 1-wire
+	  Smart Battery Monitor family device (DS2438).
+
 config W1_SLAVE_DS2433_CRC
 	bool "Protect DS2433 data with a CRC16"
 	depends on W1_SLAVE_DS2433
diff --git a/drivers/w1/slaves/Makefile b/drivers/w1/slaves/Makefile
index f1f51f19b129..fd53f53d8681 100644
--- a/drivers/w1/slaves/Makefile
+++ b/drivers/w1/slaves/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_W1_SLAVE_DS2431)	+= w1_ds2431.o
 obj-$(CONFIG_W1_SLAVE_DS2433)	+= w1_ds2433.o
 obj-$(CONFIG_W1_SLAVE_DS2760)	+= w1_ds2760.o
 obj-$(CONFIG_W1_SLAVE_BQ27000)	+= w1_bq27000.o
+obj-$(CONFIG_W1_SLAVE_DS2751)	+= w1_ds2751.o
+obj-$(CONFIG_W1_SLAVE_DS2438)	+= w1_ds2438.o
diff --git a/drivers/w1/slaves/w1_ds2438.c b/drivers/w1/slaves/w1_ds2438.c
new file mode 100644
index 000000000000..cfe65d7431ab
--- /dev/null
+++ b/drivers/w1/slaves/w1_ds2438.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/types.h>
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/workqueue.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/idr.h>
+#include <linux/power_supply.h>
+
+#include "../w1.h"
+#include "../w1_int.h"
+#include "../w1_family.h"
+#include "w1_ds2438.h"
+
+struct ds2438_device_info {
+	/* DS2438 data, valid after calling ds2438_battery_read_status() */
+	unsigned long update_time;	/* jiffies when data read */
+	char raw[DS2438_PAGE_SIZE];	/* raw DS2438 data */
+	int voltage_uV;
+	int current_uA;
+	int accum_current_uAh;
+	int temp_C;
+	int charge_status;
+	u8 init:1;
+	u8 setup:1;
+	u8 calibrate:1;
+	u8 input_src:1;
+	u8 ee_flg:1;
+	u8 resv_bit:3;
+	u8 threshold:8;
+	u16 resv_bytes;
+	u32 senser;
+
+	struct power_supply bat;
+	struct device *w1_dev;
+	struct ds2438_ops ops;
+	struct workqueue_struct *monitor_wqueue;
+	struct delayed_work monitor_work;
+};
+
+#define DS2438_SENSER	25
+#define to_ds2438_device_info(x) container_of((x), struct ds2438_device_info, \
+					      bat);
+
+
+static enum power_supply_property ds2438_battery_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_TEMP,
+	POWER_SUPPLY_PROP_CHARGE_NOW,
+};
+
+static char ds2438_sensers_title[] = "DS2438 senserin thousands of resister:";
+static unsigned int cache_time = 1000;
+module_param(cache_time, uint, 0644);
+MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
+
+static ssize_t ds2438_show_input(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	return sprintf(buf, "%s\n", di->input_src ? "1:VDD" : "0:VAD");
+}
+
+static ssize_t ds2438_show_senser(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	int len;
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	len = sprintf(buf, "%s\n", ds2438_sensers_title);
+	len += sprintf(buf + len, "%d\n", di->senser);
+	return len;
+}
+
+static ssize_t ds2438_show_ee(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	return sprintf(buf, "%d\n", di->ee_flg);
+}
+
+static ssize_t ds2438_show_threshold(struct device *dev,
+				     struct device_attribute *attr, char *buf)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	return sprintf(buf, "%d\n", di->threshold);
+}
+
+static ssize_t ds2438_set_input(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+	di->input_src = !!simple_strtoul(buf, NULL, 0);
+	return count;
+}
+
+static ssize_t ds2438_set_senser(struct device *dev,
+				 struct device_attribute *attr, const char *buf,
+				 size_t count)
+{
+	u32 resister;
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+	resister = simple_strtoul(buf, NULL, 0);
+	if (resister)
+		di->senser = resister;
+	return count;
+}
+
+static ssize_t ds2438_set_ee(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	di->ee_flg = !!simple_strtoul(buf, NULL, 0);
+	di->setup = 1;
+	return count;
+}
+
+static ssize_t ds2438_set_threshold(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	int threshold;
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	threshold = simple_strtoul(buf, NULL, 0);
+	if (threshold < 256) {
+		di->threshold = threshold;
+		di->setup = 1;
+		return count;
+	}
+	return -EINVAL;
+}
+
+static ssize_t ds2438_set_calibrate(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct power_supply *psy = dev_get_drvdata(dev);
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	di->calibrate = !!simple_strtoul(buf, NULL, 0);
+	return count;
+}
+
+static struct device_attribute ds2438_dev_attr[] = {
+	__ATTR(input_src, 0664, ds2438_show_input, ds2438_set_input),
+	__ATTR(senser, 0664, ds2438_show_senser, ds2438_set_senser),
+	__ATTR(ee_flg, 0664, ds2438_show_ee, ds2438_set_ee),
+	__ATTR(threshold, 0664, ds2438_show_threshold, ds2438_set_threshold),
+	__ATTR(calibrate, 0220, NULL, ds2438_set_calibrate),
+};
+
+static void ds2438_setup(struct ds2438_device_info *di)
+{
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	if (di->init && di->setup) {
+		if (di->ee_flg)
+			di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_EE;
+		else
+			di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_EE;
+		if (di->input_src)
+			di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_AD;
+		else
+			di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_AD;
+		di->raw[PAGE0_THRESHOLD] = di->threshold;
+	} else {
+		di->ee_flg = !!(di->raw[PAGE0_STAT_CTRL] & DS2438_CTRL_EE);
+		di->input_src = !!(di->raw[PAGE0_STAT_CTRL] & DS2438_CTRL_AD);
+		di->threshold = di->raw[PAGE0_THRESHOLD];
+		di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD | DS2438_CTRL_CA;
+	}
+	di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL);
+	if (!di->init) {
+		di->calibrate = 1;
+		di->init = 1;
+	}
+	di->setup = 0;
+}
+
+static void ds2438_calibrate(struct ds2438_device_info *di)
+{
+	int current_raw;
+	/* disable ICA */
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_IAD;
+	di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL);
+
+	/* Zero offset */
+	di->ops.load_sram(di->w1_dev, PAGE1_ETM);
+	di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw);
+	ds2438_writew(di->raw + PAGE1_OFFSET_LSB, 0);
+	di->ops.drain_sram(di->w1_dev, PAGE1_ETM_BYTE0);
+
+	/* enable ICA & read current */
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD;
+	di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL);
+	/*wait current convert about 36HZ */
+	mdelay(30);
+	/* disable ICA */
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_IAD;
+	di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL);
+	/* read current value */
+	current_raw = ds2438_readw(di->raw + PAGE0_CURRENT_LSB);
+	/* write offset by current value */
+	di->ops.load_sram(di->w1_dev, PAGE1_ETM);
+	di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw);
+	ds2438_writew(di->raw + PAGE1_OFFSET_LSB, current_raw << 8);
+	di->ops.write_page(di->w1_dev, PAGE1_ETM, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE1_ETM);
+
+	/*enable ICA again */
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD;
+	di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL);
+	di->calibrate = 0;
+}
+
+/*
+ * power supply temperture is in tenths of degree.
+ */
+static inline int ds2438_get_temp(u16 raw)
+{
+	int degree, s;
+	s = !!(raw & 0x8000);
+
+	if (s)
+		raw = ((~raw & 0x7FFF) + 1);
+	degree = ((raw >> 8) * 10) + (((raw & 0xFF) * 5) + 63) / 128;
+	return s ? -degree : degree;
+}
+
+/*
+ * power supply current is in uA.
+ */
+static inline int ds2438_get_current(u32 senser, u16 raw)
+{
+	int s, current_uA;
+	s = !!(raw & 0xFC00);
+	/* (x * 1000 * 1000)uA / (4096 * (Rsens / 1000)) */
+	raw &= 0x3FF;
+	current_uA = raw * 125 * 125 * 125;
+	current_uA /= (senser << 3);
+	return s ? -current_uA : current_uA;
+}
+
+/*
+ * power supply current is in uAh.
+ */
+static inline int ds2438_get_ica(u32 senser, u8 raw)
+{
+	int charge_uAh;
+	/* (x * 1000 * 1000)uA / (2048 * (Rsens / 1000)) */
+	charge_uAh = (raw * 125 * 125 * 125) >> 4;
+	charge_uAh /= (senser << 4);
+	return charge_uAh;
+}
+
+static int ds2438_battery_update_page1(struct ds2438_device_info *di)
+{
+	int ica_raw;
+	di->ops.load_sram(di->w1_dev, PAGE1_ETM);
+	di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw);
+	ica_raw = di->raw[PAGE1_ICA];
+	di->accum_current_uAh = ds2438_get_ica(di->senser, ica_raw);
+	return 0;
+}
+
+static int ds2438_battery_read_status(struct ds2438_device_info *di)
+{
+	u8 status;
+	int temp_raw, voltage_raw, current_raw;
+
+	if (!(di->init) || di->setup)
+		ds2438_setup(di);
+
+	if (di->calibrate)
+		ds2438_calibrate(di);
+
+	if (di->update_time && time_before(jiffies, di->update_time +
+					   msecs_to_jiffies(cache_time)))
+		return 0;
+
+	di->ops.load_sram(di->w1_dev, PAGE0_CONTROL);
+	di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw);
+	status = di->raw[PAGE0_STAT_CTRL];
+	temp_raw = ds2438_readw(di->raw + PAGE0_TEMP_LSB);
+	voltage_raw = ds2438_readw(di->raw + PAGE0_VOLTAGE_LSB);
+	current_raw = ds2438_readw(di->raw + PAGE0_CURRENT_LSB);
+	di->temp_C = ds2438_get_temp(temp_raw);
+	di->voltage_uV = voltage_raw * 10000;
+	di->current_uA = ds2438_get_current(di->senser, current_raw);
+
+	ds2438_battery_update_page1(di);
+
+	if (!(status & DS2438_STAT_TB))
+		di->ops.command(di->w1_dev, DS2438_CONVERT_TEMP, 0);
+	if (!(status & DS2438_STAT_ADB))
+		di->ops.command(di->w1_dev, DS2438_CONVERT_VOLT, 0);
+	di->update_time = jiffies;
+	return 0;
+}
+
+static void ds2438_battery_update_status(struct ds2438_device_info *di)
+{
+	int old_charge_status = di->charge_status;
+
+	ds2438_battery_read_status(di);
+
+	if (di->charge_status != old_charge_status)
+		power_supply_changed(&di->bat);
+}
+
+static void ds2438_battery_work(struct work_struct *work)
+{
+	struct ds2438_device_info *di = container_of(work,
+						     struct ds2438_device_info,
+						     monitor_work.work);
+	const int interval = HZ * 60;
+
+	dev_dbg(di->w1_dev, "%s\n", __func__);
+
+	ds2438_battery_update_status(di);
+	queue_delayed_work(di->monitor_wqueue, &di->monitor_work, interval);
+}
+
+static void ds2438_battery_external_power_changed(struct power_supply *psy)
+{
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	dev_dbg(di->w1_dev, "%s\n", __func__);
+
+	cancel_delayed_work(&di->monitor_work);
+	queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ / 10);
+}
+
+static int ds2438_battery_get_property(struct power_supply *psy,
+				       enum power_supply_property psp,
+				       union power_supply_propval *val)
+{
+	struct ds2438_device_info *di = to_ds2438_device_info(psy);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		val->intval = di->charge_status;
+		return 0;
+	default:
+		break;
+	}
+
+	ds2438_battery_read_status(di);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		val->intval = di->voltage_uV;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		val->intval = di->current_uA;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		val->intval = di->temp_C;
+		break;
+	case POWER_SUPPLY_PROP_CHARGE_NOW:
+		val->intval = di->accum_current_uAh;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* W1 slave DS2438 famliy operations */
+static int ds2438_read_page(struct device *dev, u8 page, u8 *buf)
+{
+	struct w1_slave *slave = container_of(dev, struct w1_slave, dev);
+	if ((page >= DS2438_PAGE_NUM) || (buf == NULL))
+		return -EINVAL;
+
+	mutex_lock(&slave->master->mutex);
+	if (!w1_reset_select_slave(slave)) {
+		w1_write_8(slave->master, W1_READ_SCRATCHPAD);
+		w1_write_8(slave->master, page);
+		w1_read_block(slave->master, buf, DS2438_PAGE_SIZE);
+	}
+	mutex_unlock(&slave->master->mutex);
+	return 0;
+}
+
+static int ds2438_write_page(struct device *dev, u8 page, u8 *buf)
+{
+	struct w1_slave *slave = container_of(dev, struct w1_slave, dev);
+	if ((page >= DS2438_PAGE_NUM) || (buf == NULL))
+		return -EINVAL;
+
+	mutex_lock(&slave->master->mutex);
+	if (!w1_reset_select_slave(slave)) {
+		w1_write_8(slave->master, DS2438_WRITE_SCRATCHPAD);
+		w1_write_8(slave->master, page);
+		w1_write_block(slave->master, buf, DS2438_PAGE_SIZE);
+	}
+	mutex_unlock(&slave->master->mutex);
+	return 0;
+}
+
+static int ds2438_command(struct device *dev, u8 command, u8 data)
+{
+	struct w1_slave *slave = container_of(dev, struct w1_slave, dev);
+
+	mutex_lock(&slave->master->mutex);
+	if (!w1_reset_select_slave(slave)) {
+		w1_write_8(slave->master, command);
+		switch (command) {
+		case DS2438_COPY_SCRATCHPAD:
+		case DS2438_RECALL_MEMORY:
+			w1_write_8(slave->master, data);
+		}
+	}
+	mutex_unlock(&slave->master->mutex);
+	return 0;
+}
+
+static int ds2438_drain_sram(struct device *dev, u8 page)
+{
+	return ds2438_command(dev, DS2438_COPY_SCRATCHPAD, page);
+}
+
+static int ds2438_load_sram(struct device *dev, u8 page)
+{
+	return ds2438_command(dev, DS2438_RECALL_MEMORY, page);
+}
+
+static inline void ds2438_defaut_ops(struct ds2438_ops *ops)
+{
+	ops->read_page = ds2438_read_page;
+	ops->write_page = ds2438_write_page;
+	ops->drain_sram = ds2438_drain_sram;
+	ops->load_sram = ds2438_load_sram;
+	ops->command = ds2438_command;
+}
+
+static int ds2438_add_slave(struct w1_slave *slave)
+{
+	int i, retval = 0;
+	struct ds2438_device_info *di;
+
+	di = kzalloc(sizeof(*di), GFP_KERNEL);
+	if (!di) {
+		retval = -ENOMEM;
+		goto di_alloc_failed;
+	}
+
+	di->w1_dev = &slave->dev;
+	di->bat.name = dev_name(&slave->dev);
+	di->bat.type = POWER_SUPPLY_TYPE_BATTERY;
+	di->bat.properties = ds2438_battery_props;
+	di->bat.num_properties = ARRAY_SIZE(ds2438_battery_props);
+	di->bat.get_property = ds2438_battery_get_property;
+	di->bat.external_power_changed = ds2438_battery_external_power_changed;
+	ds2438_defaut_ops(&di->ops);
+	di->senser = DS2438_SENSER;
+	di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN;
+
+	retval = power_supply_register(&slave->dev, &di->bat);
+	if (retval) {
+		dev_err(&slave->dev, "failed to register battery\n");
+		goto batt_failed;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ds2438_dev_attr); i++) {
+		if (device_create_file(di->bat.dev, ds2438_dev_attr + i)) {
+			printk(KERN_ERR "Customize attribute file fail!\n");
+			break;
+		}
+	}
+
+	if (i != ARRAY_SIZE(ds2438_dev_attr)) {
+		for (; i >= 0; i++)
+			device_remove_file(di->bat.dev, ds2438_dev_attr + i);
+		goto workqueue_failed;
+	}
+	INIT_DELAYED_WORK(&di->monitor_work, ds2438_battery_work);
+	di->monitor_wqueue = create_singlethread_workqueue(dev_name(&slave->dev));
+	if (!di->monitor_wqueue) {
+		retval = -ESRCH;
+		goto workqueue_failed;
+	}
+	dev_set_drvdata(&slave->dev, di);
+	queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ / 2);
+
+	goto success;
+
+      workqueue_failed:
+	power_supply_unregister(&di->bat);
+      batt_failed:
+	kfree(di);
+      di_alloc_failed:
+      success:
+	return retval;
+}
+
+static void ds2438_remove_slave(struct w1_slave *slave)
+{
+	struct ds2438_device_info *di = dev_get_drvdata(&slave->dev);
+
+	cancel_rearming_delayed_workqueue(di->monitor_wqueue,
+					  &di->monitor_work);
+	destroy_workqueue(di->monitor_wqueue);
+	power_supply_unregister(&di->bat);
+}
+
+static struct w1_family_ops w1_ds2438_fops = {
+	.add_slave = ds2438_add_slave,
+	.remove_slave = ds2438_remove_slave,
+};
+
+static struct w1_family w1_family_ds2438 = {
+	.fid = W1_FAMILY_DS2438,
+	.fops = &w1_ds2438_fops,
+};
+
+static int __init w1_ds2438_init(void)
+{
+	pr_info("1-wire driver for the DS2438 smart battery monitor\n");
+	return w1_register_family(&w1_family_ds2438);
+}
+
+static void __exit w1_ds2438_fini(void)
+{
+	w1_unregister_family(&w1_family_ds2438);
+}
+
+module_init(w1_ds2438_init);
+module_exit(w1_ds2438_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductors Inc");
+MODULE_DESCRIPTION("1-wire DS2438 family, smart battery monitor.");
diff --git a/drivers/w1/slaves/w1_ds2438.h b/drivers/w1/slaves/w1_ds2438.h
new file mode 100644
index 000000000000..fe22b6ec253b
--- /dev/null
+++ b/drivers/w1/slaves/w1_ds2438.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __W1_DS2438_H__
+#define __W1_DS2438_H__
+
+#include <asm/types.h>
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/types.h>
+
+#define DS2438_DEV_NAME	"ds2438-battery"
+
+#define DS2438_PAGE_SIZE	8
+#define DS2438_PAGE_NUM		8
+
+#define DS2438_CONVERT_TEMP	0x44
+#define DS2438_CONVERT_VOLT	0xB4
+#define DS2438_WRITE_SCRATCHPAD	0x4E
+#define DS2438_COPY_SCRATCHPAD	0x48
+#define DS2438_RECALL_MEMORY	0xB8
+
+enum DS2438_PAGE {
+	PAGE0_CONTROL = 0,
+	PAGE1_ETM,
+	PAGE2_STAMP,
+	PAGE3_RESV3,
+	PAGE4_RESV4,
+	PAGE5_RESV5,
+	PAGE6_RESV6,
+	PAGE7_CCA,
+};
+
+enum DS2438_REG {
+	/* PAGE 0 */
+	PAGE0_STAT_CTRL = 0,
+	PAGE0_TEMP_LSB = 1,
+	PAGE0_TEMP_MSB = 2,
+	PAGE0_VOLTAGE_LSB = 3,
+	PAGE0_VOLTAGE_MSB = 4,
+	PAGE0_CURRENT_LSB = 5,
+	PAGE0_CURRENT_MSB = 6,
+	PAGE0_THRESHOLD = 7,
+
+	/* PAGE 1 */
+	PAGE1_ETM_BYTE0 = 0,
+	PAGE1_ETM_BYTE1 = 1,
+	PAGE1_ETM_BYTE2 = 2,
+	PAGE1_ETM_BYTE3 = 3,
+	PAGE1_ICA = 4,
+	PAGE1_OFFSET_LSB = 5,
+	PAGE1_OFFSET_MSB = 6,
+
+	/* PAGE 2 */
+	PAGE2_DISCONNECT_BYTE0 = 0,
+	PAGE2_DISCONNECT_BYTE1 = 1,
+	PAGE2_DISCONNECT_BYTE2 = 2,
+	PAGE2_DISCONNECT_BYTE3 = 3,
+	PAGE2_END_CHARGE_BYTE0 = 4,
+	PAGE2_END_CHARGE_BYTE1 = 5,
+	PAGE2_END_CHARGE_BYTE2 = 6,
+	PAGE2_END_CHARGE_BYTE3 = 7,
+
+	/* PAGE 3 */
+	/* PAGE 4 */
+	/* PAGE 5 */
+	/* PAGE 6 */
+	/* PAGE 7 */
+	PAGE7_CCA_LSB = 4,
+	PAGE7_CCA_MSB = 5,
+	PAGE7_DCA_LSB = 6,
+	PAGE7_DCA_MSB = 7,
+};
+
+#define DS2438_CTRL_IAD		(1 << 0)
+#define DS2438_CTRL_CA		(1 << 1)
+#define DS2438_CTRL_EE		(1 << 2)
+#define DS2438_CTRL_AD		(1 << 3)
+#define DS2438_STAT_TB		(1 << 4)
+#define DS2438_STAT_NVB		(1 << 5)
+#define DS2438_STAT_ADB		(1 << 6)
+
+struct ds2438_ops {
+	int (*read_page) (struct device *, u8, u8 *);
+	int (*read_byte) (struct device *, u8, u8, u8 *);
+	int (*read_halfword) (struct device *, u8, u8, u16 *);
+	int (*read_word) (struct device *, u8, u8, u32 *);
+	int (*write_page) (struct device *, u8, u8 *);
+	int (*write_byte) (struct device *, u8, u8, u8);
+	int (*write_halfword) (struct device *, u8, u8, u16);
+	int (*write_word) (struct device *, u8, u8, u32);
+	int (*drain_sram) (struct device *, u8);
+	int (*load_sram) (struct device *, u8);
+	int (*command) (struct device *, u8, u8);
+};
+
+static inline u16 ds2438_readw(u8 *raw)
+{
+	return ((*(raw + 1)) << 8) | (*raw);
+}
+
+static inline void ds2438_writew(u8 *raw, u16 data)
+{
+	*raw++ = data & 0xFF;
+	*raw = (data >> 8) & 0xFF;
+}
+#endif				/* __W1_DS2438_H__ */
diff --git a/drivers/w1/slaves/w1_ds2751.c b/drivers/w1/slaves/w1_ds2751.c
new file mode 100644
index 000000000000..9346a21bdc70
--- /dev/null
+++ b/drivers/w1/slaves/w1_ds2751.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Implementation based on w1_ds2433.c
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#ifdef CONFIG_W1_F51_CRC
+#include <linux/crc16.h>
+
+#define CRC16_INIT		0
+#define CRC16_VALID		0xb001
+
+#endif
+
+#include "../w1.h"
+#include "../w1_int.h"
+#include "../w1_family.h"
+
+#define W1_EEPROM_SIZE		32
+#define W1_PAGE_SIZE		32
+#define W1_PAGE_BITS		5
+#define W1_PAGE_MASK		0x1F
+
+#define W1_F51_TIME		300
+
+#define W1_F51_READ_EEPROM	0xB8
+#define W1_F51_WRITE_SCRATCH	0x6C
+#define W1_F51_READ_SCRATCH	0x69
+#define W1_F51_COPY_SCRATCH	0x48
+#define W1_STATUS_OFFSET        0x0001
+#define W1_EEPROM_OFFSET        0x0007
+#define W1_SPECIAL_OFFSET       0x0008
+#define W1_EEPROM_BLOCK_0       0x0020
+#define W1_EEPROM_BLOCK_1       0x0030
+#define W1_SRAM                 0x0080
+struct w1_f51_data {
+	u8 memory[W1_EEPROM_SIZE];
+	u32 validcrc;
+};
+
+/**
+ * Check the file size bounds and adjusts count as needed.
+ * This would not be needed if the file size didn't reset to 0 after a write.
+ */
+static inline size_t w1_f51_fix_count(loff_t off, size_t count, size_t size)
+{
+	if (off > size)
+		return 0;
+
+	if ((off + count) > size)
+		return (size - off);
+
+	return count;
+}
+
+#ifdef CONFIG_W1_F51_CRC
+static int w1_f51_refresh_block(struct w1_slave *sl, struct w1_f51_data *data,
+				int block)
+{
+	u8 wrbuf[3];
+	int off = block * W1_PAGE_SIZE;
+	if (data->validcrc & (1 << block))
+		return 0;
+
+	if (w1_reset_select_slave(sl)) {
+		data->validcrc = 0;
+		return -EIO;
+	}
+	wrbuf[0] = W1_F51_READ_EEPROM;
+	wrbuf[1] = off & 0xff;
+	wrbuf[2] = off >> 8;
+	w1_write_block(sl->master, wrbuf, 3);
+	w1_read_block(sl->master, &data->memory[off], W1_PAGE_SIZE);
+
+	/* cache the block if the CRC is valid */
+	if (crc16(CRC16_INIT, &data->memory[off], W1_PAGE_SIZE) == CRC16_VALID)
+		data->validcrc |= (1 << block);
+
+	return 0;
+}
+#endif				/* CONFIG_W1_F51_CRC */
+
+static ssize_t w1_f51_read_bin(struct kobject *kobj, char *buf, loff_t off,
+			       size_t count)
+{
+	struct w1_slave *sl = kobj_to_w1_slave(kobj);
+#ifdef CONFIG_W1_F51_CRC
+	struct w1_f51_data *data = sl->family_data;
+	int i, min_page, max_page;
+#else
+	u8 wrbuf[3];
+#endif
+
+	if ((count = w1_f51_fix_count(off, count, W1_EEPROM_SIZE)) == 0) {
+		return 0;
+	}
+	mutex_lock(&sl->master->mutex);
+#ifdef CONFIG_W1_F51_CRC
+	min_page = (off >> W1_PAGE_BITS);
+	max_page = (off + count - 1) >> W1_PAGE_BITS;
+	for (i = min_page; i <= max_page; i++) {
+		if (w1_f51_refresh_block(sl, data, i)) {
+			count = -EIO;
+			goto out_up;
+		}
+	}
+	memcpy(buf, &data->memory[off], count);
+
+#else				/* CONFIG_W1_F51_CRC */
+
+	/* read directly from the EEPROM */
+	if (w1_reset_select_slave(sl)) {
+		count = -EIO;
+		goto out_up;
+	}
+	off = (loff_t) W1_EEPROM_BLOCK_0;
+	wrbuf[0] = W1_F51_READ_EEPROM;
+	wrbuf[1] = off & 0xff;
+	wrbuf[2] = off >> 8;
+	w1_write_block(sl->master, wrbuf, 3);
+	if (w1_reset_select_slave(sl)) {
+		count = -EIO;
+		goto out_up;
+	}
+
+	wrbuf[0] = W1_F51_READ_SCRATCH;
+	wrbuf[1] = off & 0xff;
+	wrbuf[2] = off >> 8;
+	w1_write_block(sl->master, wrbuf, 3);
+	w1_read_block(sl->master, buf, count);
+
+#endif				/* CONFIG_W1_F51_CRC */
+
+      out_up:
+	mutex_unlock(&sl->master->mutex);
+	return count;
+}
+
+/**
+ * Writes to the scratchpad and reads it back for verification.
+ * Then copies the scratchpad to EEPROM.
+ * The data must be on one page.
+ * The master must be locked.
+ *
+ * @param sl	The slave structure
+ * @param addr	Address for the write
+ * @param len   length must be <= (W1_PAGE_SIZE - (addr & W1_PAGE_MASK))
+ * @param data	The data to write
+ * @return	0=Success -1=failure
+ */
+static int w1_f51_write(struct w1_slave *sl, int addr, int len, const u8 * data)
+{
+	u8 wrbuf[4];
+	u8 rdbuf[W1_EEPROM_SIZE + 3];
+	u8 es = (addr + len - 1) & 0x1f;
+	/* Write the data to the scratchpad */
+	if (w1_reset_select_slave(sl))
+		return -1;
+	wrbuf[0] = W1_F51_WRITE_SCRATCH;
+	wrbuf[1] = addr & 0xff;
+	wrbuf[2] = addr >> 8;
+
+	w1_write_block(sl->master, wrbuf, 3);
+	w1_write_block(sl->master, data, len);
+	/* Read the scratchpad and verify */
+	if (w1_reset_select_slave(sl))
+		return -1;
+	wrbuf[0] = W1_F51_READ_SCRATCH;
+	w1_write_block(sl->master, wrbuf, 3);
+	w1_read_block(sl->master, rdbuf, len + 3);
+	/* Compare what was read against the data written */
+	if (memcmp(data, &rdbuf[0], len) != 0) {
+		printk("Error reading the scratch Pad\n");
+		return -1;
+	}
+	/* Copy the scratchpad to EEPROM */
+	if (w1_reset_select_slave(sl))
+		return -1;
+	wrbuf[0] = W1_F51_COPY_SCRATCH;
+	wrbuf[3] = es;
+	w1_write_block(sl->master, wrbuf, 4);
+	/* Sleep for 5 ms to wait for the write to complete */
+	msleep(5);
+
+	/* Reset the bus to wake up the EEPROM (this may not be needed) */
+	w1_reset_bus(sl->master);
+
+	return 0;
+}
+
+static ssize_t w1_f51_write_bin(struct kobject *kobj, char *buf, loff_t off,
+				size_t count)
+{
+	struct w1_slave *sl = kobj_to_w1_slave(kobj);
+	int addr;
+
+	if ((count = w1_f51_fix_count(off, count, W1_EEPROM_SIZE)) == 0)
+		return 0;
+	off = (loff_t) 0x0020;
+#ifdef CONFIG_W1_F51_CRC
+	/* can only write full blocks in cached mode */
+	if ((off & W1_PAGE_MASK) || (count & W1_PAGE_MASK)) {
+		dev_err(&sl->dev, "invalid offset/count off=%d cnt=%zd\n",
+			(int)off, count);
+		return -EINVAL;
+	}
+
+	/* make sure the block CRCs are valid */
+	for (idx = 0; idx < count; idx += W1_PAGE_SIZE) {
+		if (crc16(CRC16_INIT, &buf[idx], W1_PAGE_SIZE) != CRC16_VALID) {
+			dev_err(&sl->dev, "bad CRC at offset %d\n", (int)off);
+			return -EINVAL;
+		}
+	}
+#endif				/* CONFIG_W1_F51_CRC */
+
+	mutex_lock(&sl->master->mutex);
+
+	/* Can only write data to one page at a time */
+	addr = off;
+	if (w1_f51_write(sl, addr, count, buf) < 0) {
+		count = -EIO;
+		goto out_up;
+	}
+
+      out_up:
+	mutex_unlock(&sl->master->mutex);
+
+	return count;
+}
+
+static struct bin_attribute w1_f51_bin_attr = {
+	.attr = {
+		 .name = "eeprom",
+		 .mode = S_IRUGO | S_IWUSR,
+		 .owner = THIS_MODULE,
+		 },
+	.size = W1_EEPROM_SIZE,
+	.read = w1_f51_read_bin,
+	.write = w1_f51_write_bin,
+};
+
+static int w1_f51_add_slave(struct w1_slave *sl)
+{
+	int err;
+#ifdef CONFIG_W1_F51_CRC
+	struct w1_f51_data *data;
+	data = kmalloc(sizeof(struct w1_f51_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+	memset(data, 0, sizeof(struct w1_f51_data));
+	sl->family_data = data;
+
+#endif				/* CONFIG_W1_F51_CRC */
+
+	err = sysfs_create_bin_file(&sl->dev.kobj, &w1_f51_bin_attr);
+
+#ifdef CONFIG_W1_F51_CRC
+	if (err)
+		kfree(data);
+#endif				/* CONFIG_W1_F51_CRC */
+
+	return err;
+}
+
+static void w1_f51_remove_slave(struct w1_slave *sl)
+{
+#ifdef CONFIG_W1_F51_CRC
+	kfree(sl->family_data);
+	sl->family_data = NULL;
+#endif				/* CONFIG_W1_F51_CRC */
+	sysfs_remove_bin_file(&sl->dev.kobj, &w1_f51_bin_attr);
+}
+
+static struct w1_family_ops w1_f51_fops = {
+	.add_slave = w1_f51_add_slave,
+	.remove_slave = w1_f51_remove_slave,
+};
+
+static struct w1_family w1_family_51 = {
+	.fid = W1_EEPROM_DS2751,
+	.fops = &w1_f51_fops,
+};
+
+static int __init w1_f51_init(void)
+{
+	return w1_register_family(&w1_family_51);
+}
+
+static void __exit w1_f51_fini(void)
+{
+	w1_unregister_family(&w1_family_51);
+}
+
+module_init(w1_f51_init);
+module_exit(w1_f51_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductors Inc");
+MODULE_DESCRIPTION
+    ("w1 family 51 driver for DS2751, Battery Level Sensing Device");
diff --git a/drivers/w1/w1_family.h b/drivers/w1/w1_family.h
index 3ca1b9298f21..c541f9215765 100644
--- a/drivers/w1/w1_family.h
+++ b/drivers/w1/w1_family.h
@@ -32,8 +32,10 @@
 #define W1_THERM_DS18S20 	0x10
 #define W1_THERM_DS1822  	0x22
 #define W1_EEPROM_DS2433  	0x23
+#define W1_EEPROM_DS2751        0x51
 #define W1_THERM_DS18B20 	0x28
 #define W1_EEPROM_DS2431	0x2D
+#define W1_FAMILY_DS2438	0x26
 #define W1_FAMILY_DS2760	0x30
 
 #define MAXNAMELEN		32
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b1ccc04f3c9a..d018bc14de67 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -203,6 +203,36 @@ config PNX4008_WATCHDOG
 
 	  Say N if you are unsure.
 
+config MXC_WATCHDOG
+	tristate "MXC watchdog"
+	depends on WATCHDOG && WATCHDOG_NOWAYOUT
+	depends on ARCH_MXC
+	help
+	  Watchdog timer embedded into MXC chips. This will
+	  reboot your system when timeout is reached.
+
+	  NOTE: once enabled, this timer cannot be disabled.
+	  To compile this driver as a module, choose M here: the
+	  module will be called mxc_wdt.
+
+config STMP3XXX_WATCHDOG
+	tristate "Sigmatel STMP3XXX watchdog"
+	depends on ARCH_STMP3XXX
+	help
+	  Say Y here if to include support for the watchdog timer
+	  for the Sigmatel STMP37XX/378X SoC.
+	  To compile this driver as a module, choose M here: the
+	  module will be called stmp3xxx_wdt.
+
+config MXS_WATCHDOG
+	tristate "Freescale mxs watchdog"
+	depends on ARCH_MXS
+	help
+	  Say Y here if to include support for the watchdog timer
+	  for the Freescale mxs family SoC.
+	  To compile this driver as a module, choose M here: the
+	  module will be called mxs_wdt.
+
 config IOP_WATCHDOG
 	tristate "IOP Watchdog"
 	depends on PLAT_IOP
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 3d774294a2b7..1d17acb072ca 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -38,12 +38,15 @@ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
 obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
 obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
 obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
+obj-$(CONFIG_MXC_WATCHDOG)	+= mxc_wdt.o
+obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o
 obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
 obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
 obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
 obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o
+obj-$(CONFIG_MXS_WATCHDOG) += mxs-wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/mxc_wdt.c b/drivers/watchdog/mxc_wdt.c
new file mode 100644
index 000000000000..30c21aa5d219
--- /dev/null
+++ b/drivers/watchdog/mxc_wdt.c
@@ -0,0 +1,376 @@
+/*
+ * linux/drivers/char/watchdog/mxc_wdt.c
+ *
+ * Watchdog driver for FSL MXC. It is based on omap1610_wdt.c
+ *
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * 2005 (c) MontaVista Software, Inc.
+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * History:
+ *
+ * 20051207: <AKuster@mvista.com>
+ *	     	Full rewrite based on
+ *		linux-2.6.15-rc5/drivers/char/watchdog/omap_wdt.c
+ *	     	Add platform resource support
+ *
+ */
+
+/*!
+ * @defgroup WDOG Watchdog Timer (WDOG) Driver
+ */
+/*!
+ * @file mxc_wdt.c
+ *
+ * @brief Watchdog timer driver
+ *
+ * @ingroup WDOG
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+
+#include "mxc_wdt.h"
+
+#define DVR_VER "2.0"
+
+#define WDOG_SEC_TO_COUNT(s)  ((s * 2) << 8)
+#define WDOG_COUNT_TO_SEC(c)  ((c >> 8) / 2)
+
+static void __iomem  *wdt_base_reg;
+static int mxc_wdt_users;
+static struct clk *mxc_wdt_clk;
+
+static unsigned timer_margin = TIMER_MARGIN_DEFAULT;
+module_param(timer_margin, uint, 0);
+MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
+
+static unsigned dev_num = 0;
+
+static void mxc_wdt_ping(void *base)
+{
+	/* issue the service sequence instructions */
+	__raw_writew(WDT_MAGIC_1, base + MXC_WDT_WSR);
+	__raw_writew(WDT_MAGIC_2, base + MXC_WDT_WSR);
+}
+
+static void mxc_wdt_config(void *base)
+{
+	u16 val;
+
+	val = __raw_readw(base + MXC_WDT_WCR);
+	val |= 0xFF00 | WCR_WOE_BIT | WCR_WDA_BIT | WCR_SRS_BIT;
+	/* enable suspend WDT */
+	val |= WCR_WDZST_BIT | WCR_WDBG_BIT;
+	/* generate reset if wdog times out */
+	val &= ~WCR_WRE_BIT;
+
+	__raw_writew(val, base + MXC_WDT_WCR);
+}
+
+static void mxc_wdt_enable(void *base)
+{
+	u16 val;
+
+	val = __raw_readw(base + MXC_WDT_WCR);
+	val |= WCR_WDE_BIT;
+	__raw_writew(val, base + MXC_WDT_WCR);
+}
+
+static void mxc_wdt_disable(void *base)
+{
+	/* disable not supported by this chip */
+}
+
+static void mxc_wdt_adjust_timeout(unsigned new_timeout)
+{
+	if (new_timeout < TIMER_MARGIN_MIN)
+		new_timeout = TIMER_MARGIN_DEFAULT;
+	if (new_timeout > TIMER_MARGIN_MAX)
+		new_timeout = TIMER_MARGIN_MAX;
+	timer_margin = new_timeout;
+}
+
+static u16 mxc_wdt_get_timeout(void *base)
+{
+	u16 val;
+
+	val = __raw_readw(base + MXC_WDT_WCR);
+	return WDOG_COUNT_TO_SEC(val);
+}
+
+static u16 mxc_wdt_get_bootreason(void *base)
+{
+	u16 val;
+
+	val = __raw_readw(base + MXC_WDT_WRSR);
+	return val;
+}
+
+static void mxc_wdt_set_timeout(void *base)
+{
+	u16 val;
+	val = __raw_readw(base + MXC_WDT_WCR);
+	val = (val & 0x00FF) | WDOG_SEC_TO_COUNT(timer_margin);
+	__raw_writew(val, base + MXC_WDT_WCR);
+	val = __raw_readw(base + MXC_WDT_WCR);
+	timer_margin = WDOG_COUNT_TO_SEC(val);
+}
+
+/*
+ *	Allow only one task to hold it open
+ */
+
+static int mxc_wdt_open(struct inode *inode, struct file *file)
+{
+
+	if (test_and_set_bit(1, (unsigned long *)&mxc_wdt_users))
+		return -EBUSY;
+
+	mxc_wdt_config(wdt_base_reg);
+	mxc_wdt_set_timeout(wdt_base_reg);
+	mxc_wdt_enable(wdt_base_reg);
+	mxc_wdt_ping(wdt_base_reg);
+
+	return 0;
+}
+
+static int mxc_wdt_release(struct inode *inode, struct file *file)
+{
+	/*
+	 *      Shut off the timer unless NOWAYOUT is defined.
+	 */
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+	mxc_wdt_disable(wdt_base_reg);
+
+#else
+	printk(KERN_CRIT "mxc_wdt: Unexpected close, not stopping!\n");
+#endif
+	mxc_wdt_users = 0;
+	return 0;
+}
+
+static ssize_t
+mxc_wdt_write(struct file *file, const char __user * data,
+	      size_t len, loff_t * ppos)
+{
+	/* Refresh LOAD_TIME. */
+	if (len)
+		mxc_wdt_ping(wdt_base_reg);
+	return len;
+}
+
+static int
+mxc_wdt_ioctl(struct inode *inode, struct file *file,
+	      unsigned int cmd, unsigned long arg)
+{
+	int new_margin;
+	int bootr;
+
+	static struct watchdog_info ident = {
+		.identity = "MXC Watchdog",
+		.options = WDIOF_SETTIMEOUT,
+		.firmware_version = 0,
+	};
+
+	switch (cmd) {
+	default:
+		return -ENOIOCTLCMD;
+	case WDIOC_GETSUPPORT:
+		return copy_to_user((struct watchdog_info __user *)arg, &ident,
+				    sizeof(ident));
+	case WDIOC_GETSTATUS:
+		return put_user(0, (int __user *)arg);
+	case WDIOC_GETBOOTSTATUS:
+		bootr = mxc_wdt_get_bootreason(wdt_base_reg);
+		return put_user(bootr, (int __user *)arg);
+	case WDIOC_KEEPALIVE:
+		mxc_wdt_ping(wdt_base_reg);
+		return 0;
+	case WDIOC_SETTIMEOUT:
+		if (get_user(new_margin, (int __user *)arg))
+			return -EFAULT;
+
+		mxc_wdt_adjust_timeout(new_margin);
+		mxc_wdt_disable(wdt_base_reg);
+		mxc_wdt_set_timeout(wdt_base_reg);
+		mxc_wdt_enable(wdt_base_reg);
+		mxc_wdt_ping(wdt_base_reg);
+		return 0;
+
+	case WDIOC_GETTIMEOUT:
+		mxc_wdt_ping(wdt_base_reg);
+		new_margin = mxc_wdt_get_timeout(wdt_base_reg);
+		return put_user(new_margin, (int __user *)arg);
+	}
+}
+
+static struct file_operations mxc_wdt_fops = {
+	.owner = THIS_MODULE,
+	.write = mxc_wdt_write,
+	.ioctl = mxc_wdt_ioctl,
+	.open = mxc_wdt_open,
+	.release = mxc_wdt_release,
+};
+
+static struct miscdevice mxc_wdt_miscdev = {
+	.minor = WATCHDOG_MINOR,
+	.name = "watchdog",
+	.fops = &mxc_wdt_fops
+};
+
+static int __init mxc_wdt_probe(struct platform_device *pdev)
+{
+	struct resource *res, *mem;
+	int ret;
+
+	/* reserve static register mappings */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, dev_num);
+	if (!res)
+		return -ENOENT;
+
+	mem = request_mem_region(res->start, res->end - res->start + 1,
+				 pdev->name);
+	if (mem == NULL)
+		return -EBUSY;
+
+	platform_set_drvdata(pdev, mem);
+
+	wdt_base_reg = ioremap(res->start, res->end - res->start + 1);
+	mxc_wdt_disable(wdt_base_reg);
+	mxc_wdt_adjust_timeout(timer_margin);
+
+	mxc_wdt_users = 0;
+
+	mxc_wdt_miscdev.this_device = &pdev->dev;
+
+	mxc_wdt_clk = clk_get(NULL, "wdog_clk");
+	clk_enable(mxc_wdt_clk);
+
+	ret = misc_register(&mxc_wdt_miscdev);
+	if (ret)
+		goto fail;
+
+	pr_info("MXC Watchdog # %d Timer: initial timeout %d sec\n", dev_num,
+		timer_margin);
+
+	return 0;
+
+      fail:
+	iounmap(wdt_base_reg);
+	release_resource(mem);
+	pr_info("MXC Watchdog Probe failed\n");
+	return ret;
+}
+
+static void mxc_wdt_shutdown(struct platform_device *pdev)
+{
+	mxc_wdt_disable(wdt_base_reg);
+	pr_info("MXC Watchdog # %d shutdown\n", dev_num);
+}
+
+static int __exit mxc_wdt_remove(struct platform_device *pdev)
+{
+	struct resource *mem = platform_get_drvdata(pdev);
+	misc_deregister(&mxc_wdt_miscdev);
+	iounmap(wdt_base_reg);
+	release_resource(mem);
+	pr_info("MXC Watchdog # %d removed\n", dev_num);
+	return 0;
+}
+
+#ifdef	CONFIG_PM
+
+/* REVISIT ... not clear this is the best way to handle system suspend; and
+ * it's very inappropriate for selective device suspend (e.g. suspending this
+ * through sysfs rather than by stopping the watchdog daemon).  Also, this
+ * may not play well enough with NOWAYOUT...
+ */
+
+static int mxc_wdt_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	if (mxc_wdt_users) {
+		mxc_wdt_disable(wdt_base_reg);
+	}
+	return 0;
+}
+
+static int mxc_wdt_resume(struct platform_device *pdev)
+{
+	if (mxc_wdt_users) {
+		mxc_wdt_enable(wdt_base_reg);
+		mxc_wdt_ping(wdt_base_reg);
+	}
+	return 0;
+}
+
+#else
+#define	mxc_wdt_suspend	NULL
+#define	mxc_wdt_resume		NULL
+#endif
+
+static struct platform_driver mxc_wdt_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "mxc_wdt",
+		   },
+	.probe = mxc_wdt_probe,
+	.shutdown = mxc_wdt_shutdown,
+	.remove = __exit_p(mxc_wdt_remove),
+	.suspend = mxc_wdt_suspend,
+	.resume = mxc_wdt_resume,
+};
+
+static int __init mxc_wdt_init(void)
+{
+	pr_info("MXC WatchDog Driver %s\n", DVR_VER);
+
+	if ((timer_margin < TIMER_MARGIN_MIN) ||
+	    (timer_margin > TIMER_MARGIN_MAX)) {
+		pr_info("MXC watchdog error. wrong timer_margin %d\n",
+			timer_margin);
+		pr_info("    Range: %d to %d seconds\n", TIMER_MARGIN_MIN,
+			TIMER_MARGIN_MAX);
+		return -EINVAL;
+	}
+
+	return platform_driver_register(&mxc_wdt_driver);
+}
+
+static void __exit mxc_wdt_exit(void)
+{
+	platform_driver_unregister(&mxc_wdt_driver);
+	pr_info("MXC WatchDog Driver removed\n");
+}
+
+module_init(mxc_wdt_init);
+module_exit(mxc_wdt_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/drivers/watchdog/mxc_wdt.h b/drivers/watchdog/mxc_wdt.h
new file mode 100644
index 000000000000..cd09b9acf99f
--- /dev/null
+++ b/drivers/watchdog/mxc_wdt.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/drivers/char/watchdog/mxc_wdt.h
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *      MXC Watchdog timer register definitions
+ *
+ * Author: MontaVista Software, Inc.
+ *       <AKuster@mvista.com> or <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __MXC_WDT_H__
+#define __MXC_WDT_H__
+
+#define MXC_WDT_WCR             0x00
+#define MXC_WDT_WSR             0x02
+#define MXC_WDT_WRSR            0x04
+#define WCR_WOE_BIT             (1 << 6)
+#define WCR_WDA_BIT             (1 << 5)
+#define WCR_SRS_BIT             (1 << 4)
+#define WCR_WRE_BIT             (1 << 3)
+#define WCR_WDE_BIT             (1 << 2)
+#define WCR_WDBG_BIT            (1 << 1)
+#define WCR_WDZST_BIT           (1 << 0)
+#define WDT_MAGIC_1             0x5555
+#define WDT_MAGIC_2             0xAAAA
+
+#define TIMER_MARGIN_MAX    	127
+#define TIMER_MARGIN_DEFAULT	60	/* 60 secs */
+#define TIMER_MARGIN_MIN	1
+
+#endif				/* __MXC_WDT_H__ */
diff --git a/drivers/watchdog/mxs-wdt.c b/drivers/watchdog/mxs-wdt.c
new file mode 100644
index 000000000000..7f3615b833f6
--- /dev/null
+++ b/drivers/watchdog/mxs-wdt.c
@@ -0,0 +1,303 @@
+/*
+ * Watchdog driver for Freescale STMP37XX/STMP378X
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-rtc.h>
+
+#define DEFAULT_HEARTBEAT	19
+#define MAX_HEARTBEAT		(0x10000000 >> 6)
+
+/* missing bitmask in headers */
+#define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER	0x80000000
+
+#define WDT_IN_USE		0
+#define WDT_OK_TO_CLOSE		1
+
+#define WDOG_COUNTER_RATE	1000 /* 1 kHz clock */
+
+static unsigned long wdt_status;
+static int heartbeat = DEFAULT_HEARTBEAT;
+static unsigned long boot_status;
+static unsigned long wdt_base;
+static DEFINE_SPINLOCK(mxs_wdt_io_lock);
+
+static void wdt_enable(u32 value)
+{
+	spin_lock(&mxs_wdt_io_lock);
+	__raw_writel(value, wdt_base + HW_RTC_WATCHDOG);
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+		     wdt_base + HW_RTC_PERSISTENT1_SET);
+	__raw_writel(BM_RTC_CTRL_WATCHDOGEN, wdt_base + HW_RTC_CTRL_SET);
+	spin_unlock(&mxs_wdt_io_lock);
+}
+
+static void wdt_disable(void)
+{
+	spin_lock(&mxs_wdt_io_lock);
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+		     wdt_base + HW_RTC_PERSISTENT1_CLR);
+	__raw_writel(BM_RTC_CTRL_WATCHDOGEN, wdt_base + HW_RTC_CTRL_CLR);
+	spin_unlock(&mxs_wdt_io_lock);
+}
+
+static void wdt_ping(void)
+{
+	wdt_enable(heartbeat * WDOG_COUNTER_RATE);
+}
+
+static int mxs_wdt_open(struct inode *inode, struct file *file)
+{
+	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+		return -EBUSY;
+
+	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+	wdt_ping();
+
+	return nonseekable_open(inode, file);
+}
+
+static ssize_t mxs_wdt_write(struct file *file, const char __user *data,
+	size_t len, loff_t *ppos)
+{
+	if (len) {
+		if (WATCHDOG_NOWAYOUT == 0) {
+			size_t i;
+
+			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+			for (i = 0; i != len; i++) {
+				char c;
+
+				if (get_user(c, data + i))
+					return -EFAULT;
+				if (c == 'V')
+					set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+			}
+		}
+		wdt_ping();
+	}
+
+	return len;
+}
+
+static struct watchdog_info ident = {
+	.options	= WDIOF_CARDRESET |
+			  WDIOF_MAGICCLOSE |
+			  WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING,
+	.identity	= "MXS Watchdog",
+};
+
+static long mxs_wdt_ioctl(struct file *file, unsigned int cmd,
+	unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	int __user *p = argp;
+	int new_heartbeat, opts;
+	int ret = -ENOTTY;
+
+	switch (cmd) {
+	case WDIOC_GETSUPPORT:
+		ret = copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
+		break;
+
+	case WDIOC_GETSTATUS:
+		ret = put_user(0, p);
+		break;
+
+	case WDIOC_GETBOOTSTATUS:
+		ret = put_user(boot_status, p);
+		break;
+
+	case WDIOC_SETOPTIONS:
+		if (get_user(opts, p)) {
+			ret = -EFAULT;
+			break;
+		}
+		if (opts & WDIOS_DISABLECARD)
+			wdt_disable();
+		else if (opts & WDIOS_ENABLECARD)
+			wdt_ping();
+		else {
+			pr_debug("%s: unknown option 0x%x\n", __func__, opts);
+			ret = -EINVAL;
+			break;
+		}
+		ret = 0;
+		break;
+
+	case WDIOC_KEEPALIVE:
+		wdt_ping();
+		ret = 0;
+		break;
+
+	case WDIOC_SETTIMEOUT:
+		if (get_user(new_heartbeat, p)) {
+			ret = -EFAULT;
+			break;
+		}
+		if (new_heartbeat <= 0 || new_heartbeat > MAX_HEARTBEAT) {
+			ret = -EINVAL;
+			break;
+		}
+
+		heartbeat = new_heartbeat;
+		wdt_ping();
+		/* Fall through */
+
+	case WDIOC_GETTIMEOUT:
+		ret = put_user(heartbeat, p);
+		break;
+	}
+	return ret;
+}
+
+static int mxs_wdt_release(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+
+	if (WATCHDOG_NOWAYOUT == 0) {
+		if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status)) {
+			wdt_ping();
+			pr_debug("%s: Device closed unexpectdly\n", __func__);
+			ret = -EINVAL;
+		} else {
+			wdt_disable();
+			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+		}
+	}
+	clear_bit(WDT_IN_USE, &wdt_status);
+
+	return ret;
+}
+
+static const struct file_operations mxs_wdt_fops = {
+	.owner = THIS_MODULE,
+	.llseek = no_llseek,
+	.write = mxs_wdt_write,
+	.unlocked_ioctl = mxs_wdt_ioctl,
+	.open = mxs_wdt_open,
+	.release = mxs_wdt_release,
+};
+
+static struct miscdevice mxs_wdt_miscdev = {
+	.minor = WATCHDOG_MINOR,
+	.name = "watchdog",
+	.fops = &mxs_wdt_fops,
+};
+
+static int __devinit mxs_wdt_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct resource *res;
+
+	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
+		heartbeat = DEFAULT_HEARTBEAT;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL)
+		return -ENODEV;
+	wdt_base = (unsigned long)IO_ADDRESS(res->start);
+
+	boot_status = __raw_readl(wdt_base + HW_RTC_PERSISTENT1) &
+			BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER;
+	boot_status = !!boot_status;
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+		     wdt_base + HW_RTC_PERSISTENT1_CLR);
+
+	wdt_disable();		/* disable for now */
+
+	ret = misc_register(&mxs_wdt_miscdev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "cannot register misc device\n");
+		return ret;
+	}
+
+	printk(KERN_INFO "mxs watchdog: initialized, heartbeat %d sec\n",
+		heartbeat);
+
+	return ret;
+}
+
+static int __devexit mxs_wdt_remove(struct platform_device *pdev)
+{
+	misc_deregister(&mxs_wdt_miscdev);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int wdt_suspended;
+static u32 wdt_saved_time;
+
+static int mxs_wdt_suspend(struct platform_device *pdev,
+				pm_message_t state)
+{
+	if (__raw_readl(wdt_base + HW_RTC_CTRL) & BM_RTC_CTRL_WATCHDOGEN) {
+		wdt_saved_time = __raw_readl(wdt_base + HW_RTC_WATCHDOG);
+		wdt_disable();
+		wdt_suspended = 1;
+	}
+	return 0;
+}
+
+static int mxs_wdt_resume(struct platform_device *pdev)
+{
+	if (wdt_suspended) {
+		wdt_suspended = 0;
+		wdt_enable(wdt_saved_time);
+	}
+	return 0;
+}
+#else
+#define mxs_wdt_suspend	NULL
+#define mxs_wdt_resume	NULL
+#endif
+
+static struct platform_driver mxs_wdt_driver = {
+	.driver = {
+		.name = "mxs-wdt",
+	},
+	.probe = mxs_wdt_probe,
+	.remove = __devexit_p(mxs_wdt_remove),
+	.suspend = mxs_wdt_suspend,
+	.resume = mxs_wdt_resume,
+};
+
+static int __init mxs_wdt_init(void)
+{
+	return platform_driver_register(&mxs_wdt_driver);
+}
+
+static void __exit mxs_wdt_exit(void)
+{
+	return platform_driver_unregister(&mxs_wdt_driver);
+}
+
+module_init(mxs_wdt_init);
+module_exit(mxs_wdt_exit);
+
+MODULE_DESCRIPTION("MXS Watchdog Driver");
+MODULE_LICENSE("GPL");
+
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat,
+		 "Watchdog heartbeat period in seconds from 1 to "
+		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
+		 __MODULE_STRING(DEFAULT_HEARTBEAT));
+
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/drivers/watchdog/stmp3xxx_wdt.c b/drivers/watchdog/stmp3xxx_wdt.c
index 5dd952681f32..b5947b752acd 100644
--- a/drivers/watchdog/stmp3xxx_wdt.c
+++ b/drivers/watchdog/stmp3xxx_wdt.c
@@ -3,7 +3,7 @@
  *
  * Author: Vitaly Wool <vital@embeddedalley.com>
  *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  */
 #include <linux/init.h>
@@ -39,18 +39,18 @@ static void wdt_enable(u32 value)
 {
 	spin_lock(&stmp3xxx_wdt_io_lock);
 	__raw_writel(value, REGS_RTC_BASE + HW_RTC_WATCHDOG);
-	stmp3xxx_setl(BM_RTC_CTRL_WATCHDOGEN, REGS_RTC_BASE + HW_RTC_CTRL);
-	stmp3xxx_setl(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
-			REGS_RTC_BASE + HW_RTC_PERSISTENT1);
+	__raw_writel(BM_RTC_CTRL_WATCHDOGEN, REGS_RTC_BASE + HW_RTC_CTRL_SET);
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+			REGS_RTC_BASE + HW_RTC_PERSISTENT1_SET);
 	spin_unlock(&stmp3xxx_wdt_io_lock);
 }
 
 static void wdt_disable(void)
 {
 	spin_lock(&stmp3xxx_wdt_io_lock);
-	stmp3xxx_clearl(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
-			REGS_RTC_BASE + HW_RTC_PERSISTENT1);
-	stmp3xxx_clearl(BM_RTC_CTRL_WATCHDOGEN, REGS_RTC_BASE + HW_RTC_CTRL);
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+			REGS_RTC_BASE + HW_RTC_PERSISTENT1_CLR);
+	__raw_writel(BM_RTC_CTRL_WATCHDOGEN, REGS_RTC_BASE + HW_RTC_CTRL_CLR);
 	spin_unlock(&stmp3xxx_wdt_io_lock);
 }
 
@@ -210,8 +210,8 @@ static int __devinit stmp3xxx_wdt_probe(struct platform_device *pdev)
 	boot_status = __raw_readl(REGS_RTC_BASE + HW_RTC_PERSISTENT1) &
 			BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER;
 	boot_status = !!boot_status;
-	stmp3xxx_clearl(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
-			REGS_RTC_BASE + HW_RTC_PERSISTENT1);
+	__raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER,
+			REGS_RTC_BASE + HW_RTC_PERSISTENT1_CLR);
 	wdt_disable();		/* disable for now */
 
 	ret = misc_register(&stmp3xxx_wdt_miscdev);